From ac1ba0f774ac0901d082ac4f500fde617dd4b39a Mon Sep 17 00:00:00 2001 From: Philip Smart Date: Tue, 5 May 2020 23:53:09 +0100 Subject: [PATCH] Re-added ZPU and made it one of 3 selectable soft cpus. Verified Evo, Flex and Small models work in this environment. --- bridge.vhd | 656 +- build_id.v | 4 +- common/clkgen.vhd | 13 +- common/config_pkg.vhd | 7 + common/dpram.vhd | 3 +- emu.sv | 53 +- sharpmz-lite.qsf | 720 +- sharpmz.vhd | 2 - sys/sys_top.v | 40 +- zpu/build/CYC1000_zpu.qpf | 23 + zpu/build/CYC1000_zpu.qsf | 421 + zpu/build/CYC1000_zpu_Toplevel.vhd | 176 + zpu/build/CYC1000_zpu_constraints.sdc | 135 + zpu/build/Clock_12to100.cmp | 25 + zpu/build/Clock_12to100.ppf | 12 + zpu/build/Clock_12to100.qip | 5 + zpu/build/Clock_12to100.vhd | 397 + zpu/build/Clock_25to100.cmp | 25 + zpu/build/Clock_25to100.ppf | 12 + zpu/build/Clock_25to100.qip | 5 + zpu/build/Clock_25to100.vhd | 397 + zpu/build/Clock_50to100.cmp | 25 + zpu/build/Clock_50to100.cnx | 209 + zpu/build/Clock_50to100.cnxerr | 7 + zpu/build/Clock_50to100.ppf | 12 + zpu/build/Clock_50to100.qip | 5 + zpu/build/Clock_50to100.vhd | 399 + zpu/build/DE0_nano_zpu.qpf | 6 + zpu/build/DE0_nano_zpu.qsf | 476 + zpu/build/DE0_nano_zpu.sdc | 92 + zpu/build/DE0_nano_zpu_Toplevel.vhd | 176 + zpu/build/DE0_nano_zpu_constraints.sdc | 137 + zpu/build/DE10_nano_zpu.qpf | 32 + zpu/build/DE10_nano_zpu.qsf | 498 + zpu/build/DE10_nano_zpu.qsf.1405 | 478 + zpu/build/DE10_nano_zpu.qsf.2406 | 486 + zpu/build/DE10_nano_zpu_Toplevel.vhd | 174 + zpu/build/DE10_nano_zpu_constraints.sdc | 154 + zpu/build/E115_zpu.cdf | 13 + zpu/build/E115_zpu.qpf | 23 + zpu/build/E115_zpu.qsf | 302 + zpu/build/E115_zpu.qsf.2406 | 176 + zpu/build/E115_zpu_Toplevel.vhd | 177 + zpu/build/E115_zpu_constraints.sdc | 129 + zpu/build/Makefile | 303 + zpu/build/QMV_zpu.cdf | 13 + zpu/build/QMV_zpu.qpf | 23 + zpu/build/QMV_zpu.qsf | 473 + zpu/build/QMV_zpu_Toplevel.vhd | 175 + zpu/build/QMV_zpu_constraints.sdc | 121 + zpu/build/ReVerSE-U16.qpf | 30 + zpu/build/ReVerSE_U16.qpf | 23 + zpu/build/ReVerSE_U16.qsf | 211 + zpu/build/ReVerSE_U16_Toplevel.vhd | 165 + zpu/build/clean.sh | 4 + zpu/build/ddd | 617 + zpu/build/simulation/modelsim/QMV_zpu.sft | 1 + zpu/build/simulation/modelsim/QMV_zpu.vho | 465015 +++++++++++++++ .../simulation/modelsim/QMV_zpu_modelsim.xrf | 22081 + zpu/cpu/zpu_core_evo.vhd | 3567 + zpu/cpu/zpu_core_evo.vhd..2 | 3598 + zpu/cpu/zpu_core_evo.vhd.1 | 3565 + zpu/cpu/zpu_core_evo.vhd.bakPreMultChange | 3539 + zpu/cpu/zpu_core_evo_L2.vhd | 226 + zpu/cpu/zpu_core_flex.vhd | 1184 + zpu/cpu/zpu_core_medium.vhd | 1252 + zpu/cpu/zpu_core_small.vhd | 771 + zpu/cpu/zpu_pkg.vhd | 473 + zpu/cpu/zpu_uart_debug.vhd | 516 + .../WishBone/I2C/i2c_master_bit_ctrl.vhd | 576 + .../WishBone/I2C/i2c_master_byte_ctrl.vhd | 367 + zpu/devices/WishBone/I2C/i2c_master_top.vhd | 362 + zpu/devices/WishBone/I2C/readme | 25 + zpu/devices/WishBone/SDRAM.old/sdram.qip | 2 + zpu/devices/WishBone/SDRAM.old/sdram.sdc | 19 + zpu/devices/WishBone/SDRAM.old/sdram.vhd | 494 + zpu/devices/WishBone/SDRAM/48LC16M16.qip | 2 + zpu/devices/WishBone/SDRAM/48LC16M16.sdc | 90 + .../WishBone/SDRAM/48LC16M16_cached.qip | 2 + zpu/devices/WishBone/SDRAM/W9864G6.qip | 2 + zpu/devices/WishBone/SDRAM/W9864G6.sdc | 90 + zpu/devices/WishBone/SDRAM/W9864G6_cached.qip | 2 + zpu/devices/WishBone/SDRAM/wbsdram.vhd | 504 + zpu/devices/WishBone/SDRAM/wbsdram_cached.vhd | 712 + zpu/devices/WishBone/SRAM/sram.vhd | 159 + zpu/devices/sysbus/BRAM/BootROM.vhd | 1 + zpu/devices/sysbus/BRAM/DualPortBootBRAM.vhd | 1 + zpu/devices/sysbus/BRAM/IOCP_BootROM.vhd | 1121 + .../sysbus/BRAM/IOCP_DualPortBootBRAM.vhd | 4306 + .../sysbus/BRAM/IOCP_SinglePortBRAM.vhd | 164 + .../sysbus/BRAM/IOCP_SinglePortBootBRAM.vhd | 4248 + .../sysbus/BRAM/IOCP_ZPUTA_BootROM.vhd | 8240 + .../BRAM/IOCP_ZPUTA_DualPortBootBRAM.vhd | 31314 + .../sysbus/BRAM/IOCP_ZPUTA_SinglePortBRAM.vhd | 26027 + .../BRAM/IOCP_ZPUTA_SinglePortBootBRAM.vhd | 31256 + zpu/devices/sysbus/BRAM/IOCP_zOS_BootROM.vhd | 9500 + zpu/devices/sysbus/BRAM/SinglePortBRAM.vhd | 1 + .../BRAM/SinglePortBRAM.vhd.uninitialized | 161 + .../sysbus/BRAM/SinglePortBootBRAM.vhd | 1 + zpu/devices/sysbus/BRAM/ZPUTA_BootROM.vhd | 7220 + .../sysbus/BRAM/ZPUTA_DualPortBootBRAM.vhd | 28702 + .../sysbus/BRAM/ZPUTA_SinglePortBRAM.vhd | 26028 + .../sysbus/BRAM/ZPUTA_SinglePortBootBRAM.vhd | 28644 + .../BRAM/byteaddr_dp_32bit_bram_tmpl.vhd | 226 + .../BRAM/byteaddr_sp_32bit_bram_tmpl.vhd | 168 + .../BRAM/dualport_rom_epilogue_byteaddr.vhd | 40 + .../BRAM/dualport_rom_prologue_byteaddr.vhd | 71 + zpu/devices/sysbus/BRAM/rom_epilogue.vhd | 36 + .../sysbus/BRAM/rom_epilogue_byteaddr.vhd | 44 + zpu/devices/sysbus/BRAM/rom_prologue.vhd | 64 + .../sysbus/BRAM/rom_prologue_byteaddr.vhd | 67 + zpu/devices/sysbus/BRAM/zOS_BootROM.vhd | 8479 + .../sysbus/BRAM/zOS_DualPortBootBRAM.vhd | 33738 ++ .../sysbus/BRAM/zOS_SinglePortBootBRAM.vhd | 33680 ++ zpu/devices/sysbus/RAM/dpram.vhd | 154 + zpu/devices/sysbus/SDMMC/SDCard.vhd | 567 + zpu/devices/sysbus/SDRAM.bak/oddrff.vhd | 50 + zpu/devices/sysbus/SDRAM.bak/sdram.qip | 2 + zpu/devices/sysbus/SDRAM.bak/sdram.sdc | 26 + zpu/devices/sysbus/SDRAM.bak/sdram.sdc.hold | 19 + zpu/devices/sysbus/SDRAM.bak/sdram.vhd | 488 + .../sysbus/SDRAM.bak/sdram_controller.vhd | 728 + zpu/devices/sysbus/SDRAM/48LC16M16.qip | 2 + zpu/devices/sysbus/SDRAM/48LC16M16.sdc | 91 + zpu/devices/sysbus/SDRAM/48LC16M16_cached.qip | 2 + zpu/devices/sysbus/SDRAM/AS4C16M16SA.qip | 2 + zpu/devices/sysbus/SDRAM/AS4C16M16SA.sdc | 92 + .../sysbus/SDRAM/AS4C16M16SA_cached.qip | 2 + zpu/devices/sysbus/SDRAM/W9864G6.qip | 2 + zpu/devices/sysbus/SDRAM/W9864G6.sdc | 91 + zpu/devices/sysbus/SDRAM/W9864G6_cached.qip | 2 + zpu/devices/sysbus/SDRAM/sdram.vhd | 517 + zpu/devices/sysbus/SDRAM/sdram_cached.vhd | 737 + .../sysbus/intr/interrupt_controller.vhd | 67 + zpu/devices/sysbus/ioctl/ioctl.vhd | 528 + zpu/devices/sysbus/ps2/io_ps2_com.vhd | 236 + zpu/devices/sysbus/spi/spi.vhd | 105 + zpu/devices/sysbus/timer/timer_controller.vhd | 131 + zpu/devices/sysbus/uart/uart.vhd | 511 + zpu/zpu_soc.vhd | 2333 + zpu/zpu_soc_pkg.tmpl.vhd | 246 + zpu/zpu_soc_pkg.vhd | 386 + 142 files changed, 809733 insertions(+), 603 deletions(-) create mode 100644 zpu/build/CYC1000_zpu.qpf create mode 100644 zpu/build/CYC1000_zpu.qsf create mode 100644 zpu/build/CYC1000_zpu_Toplevel.vhd create mode 100644 zpu/build/CYC1000_zpu_constraints.sdc create mode 100644 zpu/build/Clock_12to100.cmp create mode 100644 zpu/build/Clock_12to100.ppf create mode 100644 zpu/build/Clock_12to100.qip create mode 100644 zpu/build/Clock_12to100.vhd create mode 100644 zpu/build/Clock_25to100.cmp create mode 100644 zpu/build/Clock_25to100.ppf create mode 100644 zpu/build/Clock_25to100.qip create mode 100644 zpu/build/Clock_25to100.vhd create mode 100644 zpu/build/Clock_50to100.cmp create mode 100644 zpu/build/Clock_50to100.cnx create mode 100644 zpu/build/Clock_50to100.cnxerr create mode 100644 zpu/build/Clock_50to100.ppf create mode 100644 zpu/build/Clock_50to100.qip create mode 100644 zpu/build/Clock_50to100.vhd create mode 100644 zpu/build/DE0_nano_zpu.qpf create mode 100644 zpu/build/DE0_nano_zpu.qsf create mode 100644 zpu/build/DE0_nano_zpu.sdc create mode 100644 zpu/build/DE0_nano_zpu_Toplevel.vhd create mode 100644 zpu/build/DE0_nano_zpu_constraints.sdc create mode 100644 zpu/build/DE10_nano_zpu.qpf create mode 100644 zpu/build/DE10_nano_zpu.qsf create mode 100644 zpu/build/DE10_nano_zpu.qsf.1405 create mode 100644 zpu/build/DE10_nano_zpu.qsf.2406 create mode 100644 zpu/build/DE10_nano_zpu_Toplevel.vhd create mode 100644 zpu/build/DE10_nano_zpu_constraints.sdc create mode 100644 zpu/build/E115_zpu.cdf create mode 100644 zpu/build/E115_zpu.qpf create mode 100644 zpu/build/E115_zpu.qsf create mode 100644 zpu/build/E115_zpu.qsf.2406 create mode 100644 zpu/build/E115_zpu_Toplevel.vhd create mode 100644 zpu/build/E115_zpu_constraints.sdc create mode 100644 zpu/build/Makefile create mode 100644 zpu/build/QMV_zpu.cdf create mode 100644 zpu/build/QMV_zpu.qpf create mode 100644 zpu/build/QMV_zpu.qsf create mode 100644 zpu/build/QMV_zpu_Toplevel.vhd create mode 100644 zpu/build/QMV_zpu_constraints.sdc create mode 100644 zpu/build/ReVerSE-U16.qpf create mode 100644 zpu/build/ReVerSE_U16.qpf create mode 100644 zpu/build/ReVerSE_U16.qsf create mode 100644 zpu/build/ReVerSE_U16_Toplevel.vhd create mode 100755 zpu/build/clean.sh create mode 100644 zpu/build/ddd create mode 100644 zpu/build/simulation/modelsim/QMV_zpu.sft create mode 100644 zpu/build/simulation/modelsim/QMV_zpu.vho create mode 100644 zpu/build/simulation/modelsim/QMV_zpu_modelsim.xrf create mode 100755 zpu/cpu/zpu_core_evo.vhd create mode 100755 zpu/cpu/zpu_core_evo.vhd..2 create mode 100755 zpu/cpu/zpu_core_evo.vhd.1 create mode 100755 zpu/cpu/zpu_core_evo.vhd.bakPreMultChange create mode 100644 zpu/cpu/zpu_core_evo_L2.vhd create mode 100644 zpu/cpu/zpu_core_flex.vhd create mode 100644 zpu/cpu/zpu_core_medium.vhd create mode 100644 zpu/cpu/zpu_core_small.vhd create mode 100644 zpu/cpu/zpu_pkg.vhd create mode 100644 zpu/cpu/zpu_uart_debug.vhd create mode 100644 zpu/devices/WishBone/I2C/i2c_master_bit_ctrl.vhd create mode 100644 zpu/devices/WishBone/I2C/i2c_master_byte_ctrl.vhd create mode 100644 zpu/devices/WishBone/I2C/i2c_master_top.vhd create mode 100644 zpu/devices/WishBone/I2C/readme create mode 100644 zpu/devices/WishBone/SDRAM.old/sdram.qip create mode 100644 zpu/devices/WishBone/SDRAM.old/sdram.sdc create mode 100644 zpu/devices/WishBone/SDRAM.old/sdram.vhd create mode 100644 zpu/devices/WishBone/SDRAM/48LC16M16.qip create mode 100644 zpu/devices/WishBone/SDRAM/48LC16M16.sdc create mode 100644 zpu/devices/WishBone/SDRAM/48LC16M16_cached.qip create mode 100644 zpu/devices/WishBone/SDRAM/W9864G6.qip create mode 100644 zpu/devices/WishBone/SDRAM/W9864G6.sdc create mode 100644 zpu/devices/WishBone/SDRAM/W9864G6_cached.qip create mode 100644 zpu/devices/WishBone/SDRAM/wbsdram.vhd create mode 100644 zpu/devices/WishBone/SDRAM/wbsdram_cached.vhd create mode 100644 zpu/devices/WishBone/SRAM/sram.vhd create mode 120000 zpu/devices/sysbus/BRAM/BootROM.vhd create mode 120000 zpu/devices/sysbus/BRAM/DualPortBootBRAM.vhd create mode 100644 zpu/devices/sysbus/BRAM/IOCP_BootROM.vhd create mode 100644 zpu/devices/sysbus/BRAM/IOCP_DualPortBootBRAM.vhd create mode 100644 zpu/devices/sysbus/BRAM/IOCP_SinglePortBRAM.vhd create mode 100644 zpu/devices/sysbus/BRAM/IOCP_SinglePortBootBRAM.vhd create mode 100644 zpu/devices/sysbus/BRAM/IOCP_ZPUTA_BootROM.vhd create mode 100644 zpu/devices/sysbus/BRAM/IOCP_ZPUTA_DualPortBootBRAM.vhd create mode 100644 zpu/devices/sysbus/BRAM/IOCP_ZPUTA_SinglePortBRAM.vhd create mode 100644 zpu/devices/sysbus/BRAM/IOCP_ZPUTA_SinglePortBootBRAM.vhd create mode 100644 zpu/devices/sysbus/BRAM/IOCP_zOS_BootROM.vhd create mode 120000 zpu/devices/sysbus/BRAM/SinglePortBRAM.vhd create mode 100644 zpu/devices/sysbus/BRAM/SinglePortBRAM.vhd.uninitialized create mode 120000 zpu/devices/sysbus/BRAM/SinglePortBootBRAM.vhd create mode 100644 zpu/devices/sysbus/BRAM/ZPUTA_BootROM.vhd create mode 100644 zpu/devices/sysbus/BRAM/ZPUTA_DualPortBootBRAM.vhd create mode 100644 zpu/devices/sysbus/BRAM/ZPUTA_SinglePortBRAM.vhd create mode 100644 zpu/devices/sysbus/BRAM/ZPUTA_SinglePortBootBRAM.vhd create mode 100644 zpu/devices/sysbus/BRAM/byteaddr_dp_32bit_bram_tmpl.vhd create mode 100644 zpu/devices/sysbus/BRAM/byteaddr_sp_32bit_bram_tmpl.vhd create mode 100644 zpu/devices/sysbus/BRAM/dualport_rom_epilogue_byteaddr.vhd create mode 100644 zpu/devices/sysbus/BRAM/dualport_rom_prologue_byteaddr.vhd create mode 100644 zpu/devices/sysbus/BRAM/rom_epilogue.vhd create mode 100644 zpu/devices/sysbus/BRAM/rom_epilogue_byteaddr.vhd create mode 100644 zpu/devices/sysbus/BRAM/rom_prologue.vhd create mode 100644 zpu/devices/sysbus/BRAM/rom_prologue_byteaddr.vhd create mode 100644 zpu/devices/sysbus/BRAM/zOS_BootROM.vhd create mode 100644 zpu/devices/sysbus/BRAM/zOS_DualPortBootBRAM.vhd create mode 100644 zpu/devices/sysbus/BRAM/zOS_SinglePortBootBRAM.vhd create mode 100644 zpu/devices/sysbus/RAM/dpram.vhd create mode 100644 zpu/devices/sysbus/SDMMC/SDCard.vhd create mode 100644 zpu/devices/sysbus/SDRAM.bak/oddrff.vhd create mode 100644 zpu/devices/sysbus/SDRAM.bak/sdram.qip create mode 100644 zpu/devices/sysbus/SDRAM.bak/sdram.sdc create mode 100644 zpu/devices/sysbus/SDRAM.bak/sdram.sdc.hold create mode 100644 zpu/devices/sysbus/SDRAM.bak/sdram.vhd create mode 100644 zpu/devices/sysbus/SDRAM.bak/sdram_controller.vhd create mode 100644 zpu/devices/sysbus/SDRAM/48LC16M16.qip create mode 100644 zpu/devices/sysbus/SDRAM/48LC16M16.sdc create mode 100644 zpu/devices/sysbus/SDRAM/48LC16M16_cached.qip create mode 100644 zpu/devices/sysbus/SDRAM/AS4C16M16SA.qip create mode 100644 zpu/devices/sysbus/SDRAM/AS4C16M16SA.sdc create mode 100644 zpu/devices/sysbus/SDRAM/AS4C16M16SA_cached.qip create mode 100644 zpu/devices/sysbus/SDRAM/W9864G6.qip create mode 100644 zpu/devices/sysbus/SDRAM/W9864G6.sdc create mode 100644 zpu/devices/sysbus/SDRAM/W9864G6_cached.qip create mode 100644 zpu/devices/sysbus/SDRAM/sdram.vhd create mode 100644 zpu/devices/sysbus/SDRAM/sdram_cached.vhd create mode 100644 zpu/devices/sysbus/intr/interrupt_controller.vhd create mode 100644 zpu/devices/sysbus/ioctl/ioctl.vhd create mode 100644 zpu/devices/sysbus/ps2/io_ps2_com.vhd create mode 100644 zpu/devices/sysbus/spi/spi.vhd create mode 100644 zpu/devices/sysbus/timer/timer_controller.vhd create mode 100644 zpu/devices/sysbus/uart/uart.vhd create mode 100644 zpu/zpu_soc.vhd create mode 100644 zpu/zpu_soc_pkg.tmpl.vhd create mode 100644 zpu/zpu_soc_pkg.vhd diff --git a/bridge.vhd b/bridge.vhd index 0aec0d6..b5a2178 100644 --- a/bridge.vhd +++ b/bridge.vhd @@ -12,7 +12,13 @@ -- Credits: -- Copyright: (c) 2018 Philip Smart -- --- History: November 2018 - Initial creation. +-- History: November 2018 - Initial creation. +-- April 2020 - Started to blend in ZPU developments after giving up on the +-- STORM processor (very nice but I hit a cache bug and it wasnt a +-- quick fix, the STORM is no longer maintained). I moved onto the +-- Neo430 from the same designer which is very nice but a little +-- underpowered for what I need in this emulator, hence settling on +-- my own version of the ZPU which I can customise as necessary. -- --------------------------------------------------------------------------------------------------------- -- This source file is free software: you can redistribute it and-or modify @@ -36,48 +42,65 @@ use ieee.std_logic_unsigned.all; use pkgs.config_pkg.all; use pkgs.clkgen_pkg.all; use pkgs.mctrl_pkg.all; +use work.zpu_soc_pkg.all; +use work.zpu_pkg.all; entity bridge is port( - -------------------- Clock Input ---------------------------- - clkmaster : in std_logic; -- Master Clock(50MHz) - clksys : out std_logic; -- System clock. - clkvid : out std_logic; -- Pixel base clock of video. - -------------------- Reset ---------------------------- - cold_reset : in std_logic; - warm_reset : in std_logic; - -------------------- main_leds ---------------------------- - main_leds : out std_logic_vector(7 downto 0); -- main_leds Green[7:0] - -------------------- PS2 ---------------------------- - ps2_key : in std_logic_vector(10 downto 0); -- PS2 Key data. - -------------------- VGA ---------------------------- - vga_hb_o : out std_logic; -- VGA Horizontal Blank - vga_vb_o : out std_logic; -- VGA Vertical Blank - vga_hs_o : out std_logic; -- VGA H_SYNC - vga_vs_o : out std_logic; -- VGA V_SYNC - vga_r_o : out std_logic_vector(7 downto 0); -- VGA Red[3:0], [7:4] = 0 - vga_g_o : out std_logic_vector(7 downto 0); -- VGA Green[3:0] - vga_b_o : out std_logic_vector(7 downto 0); -- VGA Blue[3:0] - -------------------- AUDIO ------------------------------ - audio_l_o : out std_logic; - audio_r_o : out std_logic; - - uart_rx : in std_logic; - uart_tx : out std_logic; - sd_sck : out std_logic; - sd_mosi : out std_logic; - sd_miso : in std_logic; - sd_cs : out std_logic; - sd_cd : out std_logic; - -------------------- HPS Interface ------------------------------ - ioctl_download : in std_logic; -- HPS Downloading to FPGA. - ioctl_upload : in std_logic; -- HPS Uploading from FPGA. - ioctl_clk : in std_logic; -- HPS I/O Clock. - ioctl_wr : in std_logic; -- HPS Write Enable to FPGA. - ioctl_rd : in std_logic; -- HPS Read Enable from FPGA. - ioctl_addr : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. - ioctl_dout : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. - ioctl_din : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS. + -------------------- Clock Input ---------------------------- + clkmaster : in std_logic; -- Master Clock(50MHz) + clksys : out std_logic; -- System clock. + clkvid : out std_logic; -- Pixel base clock of video. + -------------------- Reset ---------------------------- + cold_reset : in std_logic; + warm_reset : in std_logic; + -------------------- main_leds ---------------------------- + main_leds : out std_logic_vector(7 downto 0); -- main_leds Green[7:0] + -------------------- PS2 ---------------------------- + ps2_key : in std_logic_vector(10 downto 0); -- PS2 Key data. + -------------------- VGA ---------------------------- + vga_hb_o : out std_logic; -- VGA Horizontal Blank + vga_vb_o : out std_logic; -- VGA Vertical Blank + vga_hs_o : out std_logic; -- VGA H_SYNC + vga_vs_o : out std_logic; -- VGA V_SYNC + vga_r_o : out std_logic_vector(7 downto 0); -- VGA Red[3:0], [7:4] = 0 + vga_g_o : out std_logic_vector(7 downto 0); -- VGA Green[3:0] + vga_b_o : out std_logic_vector(7 downto 0); -- VGA Blue[3:0] + -------------------- AUDIO ------------------------------ + audio_l_o : out std_logic; + audio_r_o : out std_logic; + -------------------- ZPU UART CONSOLE & DEBUG ------------------------------ + uart_rx_0 : in std_logic; + uart_tx_0 : out std_logic; + uart_rx_1 : in std_logic; + uart_tx_1 : out std_logic; + -------------------- SDCARD ------------------------------ + sd_sck : out std_logic; + sd_mosi : out std_logic; + sd_miso : in std_logic; + sd_cs : out std_logic; + sd_cd : out std_logic; + -------------------- SDRAM ------------------------------ + sdram_clk : out std_logic; + sdram_cke : out std_logic; + sdram_addr : out std_logic_vector(12 downto 0); + sdram_ba : out std_logic_vector(1 downto 0); + sdram_dq : inout std_logic_vector(15 downto 0); + sdram_dqml : out std_logic; + sdram_dqmh : out std_logic; + sdram_cs_n : out std_logic; + sdram_cas_n : out std_logic; + sdram_ras_n : out std_logic; + sdram_we_n : out std_logic; + -------------------- HPS Interface ------------------------------ + ioctl_download : in std_logic; -- HPS Downloading to FPGA. + ioctl_upload : in std_logic; -- HPS Uploading from FPGA. + ioctl_clk : in std_logic; -- HPS I/O Clock. + ioctl_wr : in std_logic; -- HPS Write Enable to FPGA. + ioctl_rd : in std_logic; -- HPS Read Enable from FPGA. + ioctl_addr : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into. + ioctl_dout : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA. + ioctl_din : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS. ); end bridge; @@ -86,237 +109,340 @@ architecture rtl of bridge is -- -- Signals. -- -signal CON_CLKMASTER : std_logic; -signal CON_CLKSYS : std_logic; -signal CON_CLKVID : std_logic; -signal CON_CLKIOP : std_logic; -signal CON_COLD_RESET : std_logic; -signal CON_WARM_RESET : std_logic; -signal CON_MAIN_LEDS : std_logic_vector(7 downto 0); -signal CON_PS2_KEY : std_logic_vector(10 downto 0); -signal CON_VGA_HB_O : std_logic; -signal CON_VGA_VB_O : std_logic; -signal CON_VGA_HS_O : std_logic; -signal CON_VGA_VS_O : std_logic; -signal CON_VGA_R_O : std_logic_vector(7 downto 0); -signal CON_VGA_G_O : std_logic_vector(7 downto 0); -signal CON_VGA_B_O : std_logic_vector(7 downto 0); -signal CON_AUDIO_L_O : std_logic; -signal CON_AUDIO_R_O : std_logic; -signal CON_IOCTL_DOWNLOAD : std_logic; -signal CON_IOCTL_UPLOAD : std_logic; -signal CON_IOCTL_CLK : std_logic; -signal CON_IOCTL_WR : std_logic; -signal CON_IOCTL_RD : std_logic; -signal CON_IOCTL_ADDR : std_logic_vector(24 downto 0); -signal CON_IOCTL_DOUT : std_logic_vector(31 downto 0); -signal CON_IOCTL_DIN : std_logic_vector(31 downto 0); +signal CON_CLKMASTER : std_logic; +signal CON_CLKSYS : std_logic; +signal CON_CLKVID : std_logic; +signal CON_CLKIOP : std_logic; +signal CON_CLKIOPMEM : std_logic; +signal CON_PLL_LOCKED : std_logic; +signal CON_COLD_RESET : std_logic; +signal CON_WARM_RESET : std_logic; +signal CON_MAIN_LEDS : std_logic_vector(7 downto 0); +signal CON_PS2_KEY : std_logic_vector(10 downto 0); +signal CON_VGA_HB_O : std_logic; +signal CON_VGA_VB_O : std_logic; +signal CON_VGA_HS_O : std_logic; +signal CON_VGA_VS_O : std_logic; +signal CON_VGA_R_O : std_logic_vector(7 downto 0); +signal CON_VGA_G_O : std_logic_vector(7 downto 0); +signal CON_VGA_B_O : std_logic_vector(7 downto 0); +signal CON_AUDIO_L_O : std_logic; +signal CON_AUDIO_R_O : std_logic; +signal CON_SDRAM_DQM : std_logic_vector(1 downto 0); +signal CON_IOCTL_DOWNLOAD : std_logic; +signal CON_IOCTL_UPLOAD : std_logic; +signal CON_IOCTL_CLK : std_logic; +signal CON_IOCTL_WR : std_logic; +signal CON_IOCTL_RD : std_logic; +signal CON_IOCTL_ADDR : std_logic_vector(24 downto 0); +signal CON_IOCTL_DOUT : std_logic_vector(31 downto 0); +signal CON_IOCTL_DIN : std_logic_vector(31 downto 0); -- -- IO Processor Signals. -- -signal IOP_IOCTL_DOWNLOAD : std_logic; -signal IOP_IOCTL_UPLOAD : std_logic; -signal IOP_IOCTL_CLK : std_logic; -signal IOP_IOCTL_WR : std_logic; -signal IOP_IOCTL_RD : std_logic; -signal IOP_IOCTL_ADDR : std_logic_vector(24 downto 0); -signal IOP_IOCTL_DOUT : std_logic_vector(31 downto 0); -signal IOP_IOCTL_DIN : std_logic_vector(31 downto 0); -signal IOP_IOCTL_SENSE : std_logic; -signal IOP_IOCTL_SELECT : std_logic; +signal IOP_IOCTL_DOWNLOAD : std_logic; +signal IOP_IOCTL_UPLOAD : std_logic; +signal IOP_IOCTL_CLK : std_logic; +signal IOP_IOCTL_WR : std_logic; +signal IOP_IOCTL_RD : std_logic; +signal IOP_IOCTL_ADDR : std_logic_vector(24 downto 0); +signal IOP_IOCTL_DOUT : std_logic_vector(31 downto 0); +signal IOP_IOCTL_DIN : std_logic_vector(31 downto 0); +signal IOP_IOCTL_SENSE : std_logic; +signal IOP_IOCTL_SELECT : std_logic; -- -- -- -signal CON_UART_TX : std_logic; -signal CON_UART_RX : std_logic; -signal CON_SPI_SCLK : std_logic; -signal CON_SPI_MOSI : std_logic; -signal CON_SPI_MISO : std_logic; -signal CON_SPI_CS : std_logic_vector(7 downto 0); +signal CON_UART_RX_0 : std_logic; +signal CON_UART_TX_0 : std_logic; +signal CON_UART_RX_1 : std_logic; +signal CON_UART_TX_1 : std_logic; +signal CON_SPI_SCLK : std_logic_vector(SOC_SD_DEVICES-1 downto 0); +signal CON_SPI_MOSI : std_logic_vector(SOC_SD_DEVICES-1 downto 0); +signal CON_SPI_MISO : std_logic_vector(SOC_SD_DEVICES-1 downto 0); +signal CON_SPI_CS : std_logic_vector(SOC_SD_DEVICES-1 downto 0); +signal sysclk : std_logic; +signal memclk : std_logic; -- -- Components -- component sharpmz port ( - -------------------- Clock Input ---------------------------- - CLKMASTER : in std_logic; -- Master Clock(50MHz) - CLKSYS : out std_logic; -- System clock. - CLKVID : out std_logic; -- Pixel base clock of video. - CLKIOP : out std_logic; -- IO processor clock. - -------------------- Reset ---------------------------- - COLD_RESET : in std_logic; - WARM_RESET : in std_logic; - -------------------- main_leds ---------------------------- - MAIN_LEDS : out std_logic_vector(7 downto 0); -- main_leds Green[7:0] - -------------------- PS2 ---------------------------- - PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data. - -------------------- VGA ---------------------------- - VGA_HB_O : out std_logic; -- VGA Horizontal Blank - VGA_VB_O : out std_logic; -- VGA Vertical Blank - VGA_HS_O : out std_logic; -- VGA H_SYNC - VGA_VS_O : out std_logic; -- VGA V_SYNC - VGA_R_O : out std_logic_vector(7 downto 0); -- VGA Red[3:0], [7:4] = 0 - VGA_G_O : out std_logic_vector(7 downto 0); -- VGA Green[3:0] - VGA_B_O : out std_logic_vector(7 downto 0); -- VGA Blue[3:0] - -------------------- AUDIO ------------------------------ - AUDIO_L_O : out std_logic; - AUDIO_R_O : out std_logic; - -------------------- HPS Interface ------------------------------ - IOCTL_DOWNLOAD : in std_logic; -- Downloading to FPGA. - IOCTL_UPLOAD : in std_logic; -- Uploading from FPGA. - IOCTL_CLK : in std_logic; -- I/O Clock. - IOCTL_WR : in std_logic; -- Write Enable to FPGA. - IOCTL_RD : in std_logic; -- Read Enable from FPGA. - IOCTL_ADDR : in std_logic_vector(24 downto 0); -- Address in FPGA to write into. - IOCTL_DOUT : in std_logic_vector(31 downto 0); -- Data to be written into FPGA. - IOCTL_DIN : out std_logic_vector(31 downto 0) -- Data to be read into HPS. + -------------------- Clock Input ---------------------------- + CLKMASTER : in std_logic; -- Master Clock(50MHz) + CLKSYS : out std_logic; -- System clock. + CLKVID : out std_logic; -- Pixel base clock of video. + -------------------- Reset ---------------------------- + COLD_RESET : in std_logic; + WARM_RESET : in std_logic; + -------------------- main_leds ---------------------------- + MAIN_LEDS : out std_logic_vector(7 downto 0); -- main_leds Green[7:0] + -------------------- PS2 ---------------------------- + PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data. + -------------------- VGA ---------------------------- + VGA_HB_O : out std_logic; -- VGA Horizontal Blank + VGA_VB_O : out std_logic; -- VGA Vertical Blank + VGA_HS_O : out std_logic; -- VGA H_SYNC + VGA_VS_O : out std_logic; -- VGA V_SYNC + VGA_R_O : out std_logic_vector(7 downto 0); -- VGA Red[3:0], [7:4] = 0 + VGA_G_O : out std_logic_vector(7 downto 0); -- VGA Green[3:0] + VGA_B_O : out std_logic_vector(7 downto 0); -- VGA Blue[3:0] + -------------------- AUDIO ------------------------------ + AUDIO_L_O : out std_logic; + AUDIO_R_O : out std_logic; + -------------------- SDRAM ------------------------------ + + -------------------- HPS Interface ------------------------------ + IOCTL_DOWNLOAD : in std_logic; -- Downloading to FPGA. + IOCTL_UPLOAD : in std_logic; -- Uploading from FPGA. + IOCTL_CLK : in std_logic; -- I/O Clock. + IOCTL_WR : in std_logic; -- Write Enable to FPGA. + IOCTL_RD : in std_logic; -- Read Enable from FPGA. + IOCTL_ADDR : in std_logic_vector(24 downto 0); -- Address in FPGA to write into. + IOCTL_DOUT : in std_logic_vector(31 downto 0); -- Data to be written into FPGA. + IOCTL_DIN : out std_logic_vector(31 downto 0) -- Data to be read into HPS. ); end component; +component zpu_soc + generic ( + SYSCLK_FREQUENCY : integer := SYSTEM_FREQUENCY -- System clock frequency + ); + port ( + -- Global Control -- + SYSCLK : in std_logic; -- System clock, running at frequency indicated in SYSCLK_FREQUENCY + MEMCLK : in std_logic; -- Memory clock, running at twice frequency indicated in SYSCLK_FREQUENCY + RESET_IN : in std_logic; + + -- UART 0 & 1 + UART_RX_0 : in std_logic; + UART_TX_0 : out std_logic; + UART_RX_1 : in std_logic; + UART_TX_1 : out std_logic; + + -- SPI signals + SPI_MISO : in std_logic := '1'; -- Allow the SPI interface not to be plumbed in. + SPI_MOSI : out std_logic; + SPI_CLK : out std_logic; + SPI_CS : out std_logic; + + -- SD Card (SPI) signals + SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0) := (others => '1'); + SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + + -- PS/2 signals + PS2K_CLK_IN : in std_logic := '1'; + PS2K_DAT_IN : in std_logic := '1'; + PS2K_CLK_OUT : out std_logic; + PS2K_DAT_OUT : out std_logic; + PS2M_CLK_IN : in std_logic := '1'; + PS2M_DAT_IN : in std_logic := '1'; + PS2M_CLK_OUT : out std_logic; + PS2M_DAT_OUT : out std_logic; + + -- I²C signals + I2C_SCL_IO : inout std_logic; + I2C_SDA_IO : inout std_logic; + + -- IOCTL Bus + IOCTL_DOWNLOAD : out std_logic; -- Downloading to FPGA. + IOCTL_UPLOAD : out std_logic; -- Uploading from FPGA. + IOCTL_CLK : out std_logic; -- I/O Clock. + IOCTL_WR : out std_logic; -- Write Enable to FPGA. + IOCTL_RD : out std_logic; -- Read Enable from FPGA. + IOCTL_SENSE : in std_logic; -- Sense to see if HPS accessing ioctl bus. + IOCTL_SELECT : out std_logic; -- Enable IOP control over ioctl bus. + IOCTL_ADDR : out std_logic_vector(24 downto 0); -- Address in FPGA to write into. + IOCTL_DOUT : out std_logic_vector(31 downto 0); -- Data to be written into FPGA. + IOCTL_DIN : in std_logic_vector(31 downto 0); -- Data to be read into HPS. + + -- SDRAM signals + SDRAM_CLK : out std_logic; -- sdram is accessed at 100MHz + SDRAM_CKE : out std_logic; -- clock enable. + SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus + SDRAM_ADDR : out std_logic_vector(12 downto 0); -- 12 bit multiplexed address bus + SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks + SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks + SDRAM_CS_n : out std_logic; -- a single chip select + SDRAM_WE_n : out std_logic; -- write enable + SDRAM_RAS_n : out std_logic; -- row address select + SDRAM_CAS_n : out std_logic; -- columns address select + SDRAM_READY : out std_logic -- sd ready. + + -- DDR2 DRAM + --DDR2_ADDR : out std_logic_vector(13 downto 0); -- 14 bit multiplexed address bus + --DDR2_DQ : inout std_logic_vector(63 downto 0); -- 64 bit bidirectional data bus + --DDR2_DQS : inout std_logic_vector(7 downto 0); -- 8 bit bidirectional data bus + --DDR2_DQM : out std_logic_vector(17 downto 0); -- eight byte masks + --DDR2_ODT : out std_logic_vector(1 downto 0); -- 14 bit multiplexed address bus + --DDR2_BA : out std_logic_vector(2 downto 0); -- 8 banks + --DDR2_CS : out std_logic_vector(1 downto 0); -- 2 chip selects. + --DDR2_WE : out std_logic; -- write enable + --DDR2_RAS : out std_logic; -- row address select + --DDR2_CAS : out std_logic; -- columns address select + --DDR2_CKE : out std_logic_vector(1 downto 0); -- 2 clock enable. + --DDR2_CLK : out std_logic_vector(1 downto 0) -- 2 clocks. +); +end component; + --component STORM_SoC -- port ( -- -- Global Control -- --- CLK_I : in std_logic; --- RST_I : in std_logic; +-- CLK_I : in std_logic; +-- RST_I : in std_logic; -- -- -- General purpose (debug) UART -- --- UART0_RXD_I : in std_logic; --- UART0_TXD_O : out std_logic; +-- UART0_RXD_I : in std_logic; +-- UART0_TXD_O : out std_logic; -- -- -- System Control -- --- START_I : in std_logic; -- low active --- BOOT_CONFIG_I : in std_logic_vector(03 downto 0); -- low active --- LED_BAR_O : out std_logic_vector(07 downto 0); +-- START_I : in std_logic; -- low active +-- BOOT_CONFIG_I : in std_logic_vector(03 downto 0); -- low active +-- LED_BAR_O : out std_logic_vector(07 downto 0); -- -- -- GP Input Pins -- --- GP_INPUT_I : in std_logic_vector(07 downto 0); +-- GP_INPUT_I : in std_logic_vector(07 downto 0); -- -- -- GP Output Pins -- --- GP_OUTPUT_O : out std_logic_vector(07 downto 0); +-- GP_OUTPUT_O : out std_logic_vector(07 downto 0); -- -- -- I²C Port -- --- I2C_SCL_IO : inout std_logic; --- I2C_SDA_IO : inout std_logic; +-- I2C_SCL_IO : inout std_logic; +-- I2C_SDA_IO : inout std_logic; -- -- -- SPI Port 0 [3 devices] -- --- SPI_P0_CLK_O : out std_logic; --- SPI_P0_MISO_I : in std_logic; --- SPI_P0_MOSI_O : out std_logic; --- SPI_P0_CS_O : out std_logic_vector(02 downto 0); +-- SPI_P0_CLK_O : out std_logic; +-- SPI_P0_MISO_I : in std_logic; +-- SPI_P0_MOSI_O : out std_logic; +-- SPI_P0_CS_O : out std_logic_vector(02 downto 0); -- -- -- SPI Port 1 [3 devices] -- --- SPI_P1_CLK_O : out std_logic; --- SPI_P1_MISO_I : in std_logic; --- SPI_P1_MOSI_O : out std_logic; --- SPI_P1_CS_O : out std_logic_vector(02 downto 0); +-- SPI_P1_CLK_O : out std_logic; +-- SPI_P1_MISO_I : in std_logic; +-- SPI_P1_MOSI_O : out std_logic; +-- SPI_P1_CS_O : out std_logic_vector(02 downto 0); -- -- -- SPI Port 2 [2 devices] -- --- SPI_P2_CLK_O : out std_logic; --- SPI_P2_MISO_I : in std_logic; --- SPI_P2_MOSI_O : out std_logic; --- SPI_P2_CS_O : out std_logic_vector(01 downto 0); +-- SPI_P2_CLK_O : out std_logic; +-- SPI_P2_MISO_I : in std_logic; +-- SPI_P2_MOSI_O : out std_logic; +-- SPI_P2_CS_O : out std_logic_vector(01 downto 0); -- -- -- PWM Port 0 -- ----- PWM0_PORT_O : out std_logic_vector(07 downto 0) +---- PWM0_PORT_O : out std_logic_vector(07 downto 0) -- -- -- IOCTL Bus -- --- IOCTL_DOWNLOAD : out std_logic; -- Downloading to FPGA. --- IOCTL_UPLOAD : out std_logic; -- Uploading from FPGA. --- IOCTL_CLK : out std_logic; -- I/O Clock. --- IOCTL_WR : out std_logic; -- Write Enable to FPGA. --- IOCTL_RD : out std_logic; -- Read Enable from FPGA. --- IOCTL_SENSE : in std_logic; -- Sense to see if HPS accessing ioctl bus. --- IOCTL_SELECT : out std_logic; -- Enable IOP control over ioctl bus. --- IOCTL_ADDR : out std_logic_vector(24 downto 0); -- Address in FPGA to write into. --- IOCTL_DOUT : out std_logic_vector(31 downto 0); -- Data to be written into FPGA. --- IOCTL_DIN : in std_logic_vector(31 downto 0) -- Data to be read into HPS. +-- IOCTL_DOWNLOAD : out std_logic; -- Downloading to FPGA. +-- IOCTL_UPLOAD : out std_logic; -- Uploading from FPGA. +-- IOCTL_CLK : out std_logic; -- I/O Clock. +-- IOCTL_WR : out std_logic; -- Write Enable to FPGA. +-- IOCTL_RD : out std_logic; -- Read Enable from FPGA. +-- IOCTL_SENSE : in std_logic; -- Sense to see if HPS accessing ioctl bus. +-- IOCTL_SELECT : out std_logic; -- Enable IOP control over ioctl bus. +-- IOCTL_ADDR : out std_logic_vector(24 downto 0); -- Address in FPGA to write into. +-- IOCTL_DOUT : out std_logic_vector(31 downto 0); -- Data to be written into FPGA. +-- IOCTL_DIN : in std_logic_vector(31 downto 0) -- Data to be read into HPS. -- ---- -- SDRAM Interface -- ----- SDRAM_CLK_O : out std_logic; ----- SDRAM_CSN_O : out std_logic; ----- SDRAM_CKE_O : out std_logic; ----- SDRAM_RASN_O : out std_logic; ----- SDRAM_CASN_O : out std_logic; ----- SDRAM_WEN_O : out std_logic; ----- SDRAM_DQM_O : out std_logic_vector(01 downto 0); ----- SDRAM_BA_O : out std_logic_vector(01 downto 0); ----- SDRAM_ADR_O : out std_logic_vector(11 downto 0); ----- SDRAM_DAT_IO : inout std_logic_vector(15 downto 0) +---- SDRAM_CLK_O : out std_logic; +---- SDRAM_CSN_O : out std_logic; +---- SDRAM_CKE_O : out std_logic; +---- SDRAM_RASN_O : out std_logic; +---- SDRAM_CASN_O : out std_logic; +---- SDRAM_WEN_O : out std_logic; +---- SDRAM_DQM_O : out std_logic_vector(01 downto 0); +---- SDRAM_BA_O : out std_logic_vector(01 downto 0); +---- SDRAM_ADR_O : out std_logic_vector(11 downto 0); +---- SDRAM_DAT_IO : inout std_logic_vector(15 downto 0) -- ); --end component; -- --component neo430 -- generic ( -- -- general configuration -- --- CLOCK_SPEED : natural := 100000000; -- main clock in Hz --- IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB) --- DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB) +-- CLOCK_SPEED : natural := 100000000; -- main clock in Hz +-- IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB) +-- DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB) -- -- additional configuration -- --- USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code +-- USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code -- -- module configuration -- --- DADD_USE : boolean := true; -- implement DADD instruction? (default=true) --- MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true) --- WB32_USE : boolean := false;-- implement WB32 unit? (default=true) --- WDT_USE : boolean := true; -- implement WDT? (default=true) --- GPIO_USE : boolean := true; -- implement GPIO unit? (default=true) --- TIMER_USE : boolean := true; -- implement timer? (default=true) --- UART_USE : boolean := true; -- implement UART? (default=true) --- CRC_USE : boolean := true; -- implement CRC unit? (default=true) --- CFU_USE : boolean := true; -- implement custom functions unit? (default=false) --- PWM_USE : boolean := true; -- implement PWM controller? --- TWI_USE : boolean := true; -- implement two wire serial interface? (default=true) --- SPI_USE : boolean := true; -- implement SPI? (default=true) +-- DADD_USE : boolean := true; -- implement DADD instruction? (default=true) +-- MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true) +-- WB32_USE : boolean := false;-- implement WB32 unit? (default=true) +-- WDT_USE : boolean := true; -- implement WDT? (default=true) +-- GPIO_USE : boolean := true; -- implement GPIO unit? (default=true) +-- TIMER_USE : boolean := true; -- implement timer? (default=true) +-- UART_USE : boolean := true; -- implement UART? (default=true) +-- CRC_USE : boolean := true; -- implement CRC unit? (default=true) +-- CFU_USE : boolean := true; -- implement custom functions unit? (default=false) +-- PWM_USE : boolean := true; -- implement PWM controller? +-- TWI_USE : boolean := true; -- implement two wire serial interface? (default=true) +-- SPI_USE : boolean := true; -- implement SPI? (default=true) -- -- boot configuration -- --- BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true) --- IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false) +-- BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true) +-- IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false) -- ); -- port ( -- -- global control -- --- clk_i : in std_logic; -- global clock, rising edge --- rst_i : in std_logic; -- global reset, async, low-active +-- clk_i : in std_logic; -- global clock, rising edge +-- rst_i : in std_logic; -- global reset, async, low-active -- -- gpio -- --- gpio_o : out std_logic_vector(15 downto 0); -- parallel output --- gpio_i : in std_logic_vector(15 downto 0); -- parallel input +-- gpio_o : out std_logic_vector(15 downto 0); -- parallel output +-- gpio_i : in std_logic_vector(15 downto 0); -- parallel input -- -- pwm channels -- --- pwm_o : out std_logic_vector(02 downto 0); -- pwm channels +-- pwm_o : out std_logic_vector(02 downto 0); -- pwm channels -- -- serial com -- --- uart_txd_o : out std_logic; -- UART send data --- uart_rxd_i : in std_logic; -- UART receive data --- spi_sclk_o : out std_logic; -- serial clock line --- spi_mosi_o : out std_logic; -- serial data line out --- spi_miso_i : in std_logic; -- serial data line in --- spi_cs_o : out std_logic_vector(07 downto 0); -- SPI CS 0..7 --- twi_sda_io : inout std_logic; -- twi serial data line --- twi_scl_io : inout std_logic; -- twi serial clock line +-- uart_txd_o : out std_logic; -- UART send data +-- uart_rxd_i : in std_logic; -- UART receive data +-- spi_sclk_o : out std_logic; -- serial clock line +-- spi_mosi_o : out std_logic; -- serial data line out +-- spi_miso_i : in std_logic; -- serial data line in +-- spi_cs_o : out std_logic_vector(07 downto 0); -- SPI CS 0..7 +-- twi_sda_io : inout std_logic; -- twi serial data line +-- twi_scl_io : inout std_logic; -- twi serial clock line -- -- IOCTL Bus -- --- ioctl_download : out std_logic; -- Downloading to FPGA. --- ioctl_upload : out std_logic; -- Uploading from FPGA. --- ioctl_clk : out std_logic; -- I/O Clock. --- ioctl_wr : out std_logic; -- Write Enable to FPGA. --- ioctl_rd : out std_logic; -- Read Enable from FPGA. --- ioctl_sense : in std_logic; -- Sense to see if HPS accessing ioctl bus. --- ioctl_select : out std_logic; -- Enable CFU control over ioctl bus. --- ioctl_addr : out std_logic_vector(24 downto 0); -- Address in FPGA to write into. --- ioctl_dout : out std_logic_vector(31 downto 0); -- Data to be written into FPGA. --- ioctl_din : in std_logic_vector(31 downto 0); -- Data to be read into HPS. +-- ioctl_download : out std_logic; -- Downloading to FPGA. +-- ioctl_upload : out std_logic; -- Uploading from FPGA. +-- ioctl_clk : out std_logic; -- I/O Clock. +-- ioctl_wr : out std_logic; -- Write Enable to FPGA. +-- ioctl_rd : out std_logic; -- Read Enable from FPGA. +-- ioctl_sense : in std_logic; -- Sense to see if HPS accessing ioctl bus. +-- ioctl_select : out std_logic; -- Enable CFU control over ioctl bus. +-- ioctl_addr : out std_logic_vector(24 downto 0); -- Address in FPGA to write into. +-- ioctl_dout : out std_logic_vector(31 downto 0); -- Data to be written into FPGA. +-- ioctl_din : in std_logic_vector(31 downto 0); -- Data to be read into HPS. -- -- 32-bit wishbone interface -- --- wb_adr_o : out std_logic_vector(31 downto 0); -- address --- wb_dat_i : in std_logic_vector(31 downto 0); -- read data --- wb_dat_o : out std_logic_vector(31 downto 0); -- write data --- wb_we_o : out std_logic; -- read/write --- wb_sel_o : out std_logic_vector(03 downto 0); -- byte enable --- wb_stb_o : out std_logic; -- strobe --- wb_cyc_o : out std_logic; -- valid cycle --- wb_ack_i : in std_logic; -- transfer acknowledge +-- wb_adr_o : out std_logic_vector(31 downto 0); -- address +-- wb_dat_i : in std_logic_vector(31 downto 0); -- read data +-- wb_dat_o : out std_logic_vector(31 downto 0); -- write data +-- wb_we_o : out std_logic; -- read/write +-- wb_sel_o : out std_logic_vector(03 downto 0); -- byte enable +-- wb_stb_o : out std_logic; -- strobe +-- wb_cyc_o : out std_logic; -- valid cycle +-- wb_ack_i : in std_logic; -- transfer acknowledge -- -- interrupts -- --- irq_i : in std_logic; -- external interrupt request line --- irq_ack_o : out std_logic -- external interrupt request acknowledge +-- irq_i : in std_logic; -- external interrupt request line +-- irq_ack_o : out std_logic -- external interrupt request acknowledge -- ); --end component; begin + -- + -- Instantiate a local PLL for the I/O Processor and memory. + -- + IOPCLK : entity work.Clock_50to100 + port map + ( + inclk0 => CON_CLKMASTER, + c0 => CON_CLKIOP, + c1 => CON_CLKIOPMEM, + locked => CON_PLL_LOCKED + ); + -- -- Instantiation -- @@ -326,7 +452,6 @@ begin CLKMASTER => CON_CLKMASTER, -- Master Clock(50MHz) CLKSYS => CON_CLKSYS, -- System clock. CLKVID => CON_CLKVID, -- Pixel base clock of video. - CLKIOP => CON_CLKIOP, -- IO Processor Clock. -------------------- ---------------------------- COLD_RESET => CON_COLD_RESET, WARM_RESET => CON_WARM_RESET, @@ -356,6 +481,94 @@ begin IOCTL_DIN => CON_IOCTL_DIN -- Data to be read into HPS. ); + + -- If enabled, instantiate the local ZPU IO processor to provide IO and user interface services. + -- + ZPU_ENABLED: if ZPU_ENABLE = 1 generate + ZPU_0: zpu_soc + generic map ( + SYSCLK_FREQUENCY => SYSCLK_DE10_MISTER_FREQ + ) + port map ( + -- Global Control -- + SYSCLK => CON_CLKIOP, -- System clock, running at frequency indicated in SYSCLK_FREQUENCY + MEMCLK => CON_CLKIOPMEM, -- Memory clock, running at twice frequency indicated in SYSCLK_FREQUENCY + RESET_IN => (not CON_COLD_RESET and not CON_WARM_RESET) and CON_PLL_LOCKED, + + -- UART 0 & 1 + UART_RX_0 => CON_UART_RX_0, + UART_TX_0 => CON_UART_TX_0, + UART_RX_1 => CON_UART_RX_1, + UART_TX_1 => CON_UART_TX_1, + + -- SPI signals + SPI_MISO => '0', -- Allow the SPI interface not to be plumbed in. + SPI_MOSI => open, + SPI_CLK => open, + SPI_CS => open, + + -- SD Card (SPI) signals + SDCARD_MISO => CON_SPI_MISO, + SDCARD_MOSI => CON_SPI_MOSI, + SDCARD_CLK => CON_SPI_SCLK, + SDCARD_CS => CON_SPI_CS, + + -- PS/2 signals + PS2K_CLK_IN => '1', + PS2K_DAT_IN => '1', + PS2K_CLK_OUT => open, + PS2K_DAT_OUT => open, + PS2M_CLK_IN => '1', + PS2M_DAT_IN => '1', + PS2M_CLK_OUT => open, + PS2M_DAT_OUT => open, + + -- I²C signals + I2C_SCL_IO => open, + I2C_SDA_IO => open, + + -- IOCTL Bus + IOCTL_DOWNLOAD => IOP_IOCTL_DOWNLOAD, -- Downloading to FPGA. + IOCTL_UPLOAD => IOP_IOCTL_UPLOAD, -- Uploading from FPGA. + IOCTL_CLK => IOP_IOCTL_CLK, -- I/O Clock. + IOCTL_WR => IOP_IOCTL_WR, -- Write Enable to FPGA. + IOCTL_RD => IOP_IOCTL_RD, -- Read Enable from FPGA. + IOCTL_SENSE => IOP_IOCTL_SENSE, -- Sense to see if HPS accessing ioctl bus. + IOCTL_SELECT => IOP_IOCTL_SELECT, -- Enable IOP control over ioctl bus. + IOCTL_ADDR => IOP_IOCTL_ADDR, -- Address in FPGA to write into. + IOCTL_DOUT => IOP_IOCTL_DOUT, -- Data to be written into FPGA. + IOCTL_DIN => IOP_IOCTL_DIN, -- Data to be read into HPS. + + -- SDRAM signals + SDRAM_CLK => sdram_clk, -- sdram is accessed at 100MHz + SDRAM_CKE => sdram_cke, -- clock enable. + SDRAM_DQ => sdram_dq, -- 16 bit bidirectional data bus + SDRAM_ADDR => sdram_addr, -- 12 bit multiplexed address bus + SDRAM_DQM => CON_SDRAM_DQM, -- two byte masks + SDRAM_BA => sdram_ba, -- two banks + SDRAM_CS_n => sdram_cs_n, -- a single chip select + SDRAM_WE_n => sdram_we_n, -- write enable + SDRAM_RAS_n => sdram_ras_n, -- row address select + SDRAM_CAS_n => sdram_cas_n, -- columns address select + SDRAM_READY => open -- sd ready. + + -- DDR2 DRAM + --DDR2_ADDR => open, -- 14 bit multiplexed address bus + --DDR2_DQ => open, -- 64 bit bidirectional data bus + --DDR2_DQS => open, -- 8 bit bidirectional data bus + --DDR2_DQM => open, -- eight byte masks + --DDR2_ODT => open, -- 14 bit multiplexed address bus + --DDR2_BA => open, -- 8 banks + --DDR2_CS => open, -- 2 chip selects. + --DDR2_WE => open, -- write enable + --DDR2_RAS => open, -- row address select + --DDR2_CAS => open, -- columns address select + --DDR2_CKE => open, -- 2 clock enable. + --DDR2_CLK => open -- 2 clocks. + ); + end generate; + + -- -- If enabled, instantiate the local STORM IO processor to provide IO and user interface services. -- -- -- STORM_ENABLED: if STORM_ENABLE = 1 generate @@ -505,7 +718,7 @@ begin -- -- If the IO Processor is disabled, set the signals to inactive. -- -- --- IOP_DISABLED: if NEO_ENABLE = 0 and STORM_ENABLE = 0 generate + IOP_DISABLED: if ZPU_ENABLE = 0 and NEO_ENABLE = 0 and STORM_ENABLE = 0 generate IOP_IOCTL_DOWNLOAD <= '0'; IOP_IOCTL_UPLOAD <= '0'; IOP_IOCTL_CLK <= '0'; @@ -516,7 +729,7 @@ begin --IOP_IOCTL_DIN => open; --IOP_IOCTL_SENSE => open; IOP_IOCTL_SELECT <= '0'; --- end generate; + end generate; -- Assign signals from the emu onto local wires. -- @@ -536,14 +749,21 @@ begin vga_b_o <= CON_VGA_B_O; audio_l_o <= CON_AUDIO_L_O; audio_r_o <= CON_AUDIO_R_O; - - uart_tx <= CON_UART_TX; - CON_UART_RX <= uart_rx; - sd_sck <= CON_SPI_SCLK; - sd_mosi <= CON_SPI_MOSI; - CON_SPI_MISO <= sd_miso; - sd_cs <= CON_SPI_CS(0); -- + sdram_dqmh <= CON_SDRAM_DQM(1); + sdram_dqml <= CON_SDRAM_DQM(0); + + uart_tx_0 <= CON_UART_TX_0; + CON_UART_RX_0 <= uart_rx_0; + uart_tx_1 <= CON_UART_TX_1; + CON_UART_RX_1 <= uart_rx_1; + + sd_sck <= CON_SPI_SCLK(0); + sd_mosi <= CON_SPI_MOSI(0); + CON_SPI_MISO(0) <= sd_miso; + sd_cs <= CON_SPI_CS(0); + CON_SPI_MISO(SOC_SD_DEVICES-1 downto 1) <= (others => '1'); + -- Multiplexer, default IO control to the HPS unless the IOP is enabled and selects. -- The IOP first senses to ensure there is no activity on the bus, then takes control -- diff --git a/build_id.v b/build_id.v index c8e54ad..87f2989 100644 --- a/build_id.v +++ b/build_id.v @@ -1,2 +1,2 @@ -`define BUILD_DATE "200430" -`define BUILD_TIME "002036" +`define BUILD_DATE "200505" +`define BUILD_TIME "234608" diff --git a/common/clkgen.vhd b/common/clkgen.vhd index ae7eeef..4fdf8cc 100644 --- a/common/clkgen.vhd +++ b/common/clkgen.vhd @@ -56,7 +56,7 @@ package clkgen_pkg is -- Clock bus, various clocks on a single bus construct. -- - subtype CLKBUS_WIDTH is integer range 8 downto 0; + subtype CLKBUS_WIDTH is integer range 7 downto 0; -- Indexes to the various clocks on the bus. -- @@ -65,10 +65,9 @@ package clkgen_pkg is constant CKRTC : integer := 2; -- RTC clock. constant CKENVIDEO : integer := 3; -- Video clock enable. constant CKVIDEO : integer := 4; -- Video clock. - constant CKIOP : integer := 5; - constant CKENCPU : integer := 6; -- CPU clock enable. - constant CKENLEDS : integer := 7; -- LEDS display clock enable. - constant CKENPERIPH : integer := 8; -- Peripheral clock enable. + constant CKENCPU : integer := 5; -- CPU clock enable. + constant CKENLEDS : integer := 6; -- LEDS display clock enable. + constant CKENPERIPH : integer := 7; -- Peripheral clock enable. end clkgen_pkg; library IEEE; @@ -143,7 +142,6 @@ signal CK0_1i : std_logic; -- 0.1H signal CKSOUNDi : std_logic; -- Sound clock 50/50 Duty cycle. signal CKRTCi : std_logic; -- RTC clock 50/50 Duty cycle. signal CKVIDEOi : std_logic; -- Video clock 50/50 Duty cycle. -signal CKIOPi : std_logic; -- IO Processor clock. -- -- Enable signals for target clocks. -- @@ -212,7 +210,7 @@ begin outclk_0 => CK448Mi, -- 448MHz outclk_1 => CK112Mi, -- 112MHz outclk_2 => CK64Mi, -- 64MHz - outclk_3 => CK32Mi, -- 328MHz + outclk_3 => CK32Mi, -- 32MHz outclk_4 => CK16Mi, -- 16MHz outclk_5 => CK8Mi, -- 8MHz outclk_6 => CK4Mi, -- 4MHz @@ -789,6 +787,5 @@ begin CLKBUS(CKENCPU) <= CKENCPUi; -- Enable signal for CPU base clock. CLKBUS(CKENLEDS) <= CKENLEDSi; -- Enable signal for LEDS base clock. CLKBUS(CKENPERIPH) <= CKENPERi; -- Enable signal for Peripheral base clock. - CLKBUS(CKIOP) <= CK64Mi; end RTL; diff --git a/common/config_pkg.vhd b/common/config_pkg.vhd index afdaca0..fd844a4 100644 --- a/common/config_pkg.vhd +++ b/common/config_pkg.vhd @@ -9,6 +9,12 @@ -- Copyright: (c) 2018 Philip Smart -- -- History: September 2018 - Initial module written. +-- April 2020 - Started to blend in ZPU developments after giving up on the +-- STORM processor (very nice but I hit a cache bug and it wasnt a +-- quick fix, the STORM is no longer maintained). I moved onto the +-- Neo430 from the same designer which is very nice but a little +-- underpowered for what I need in this emulator, hence settling on +-- my own version of the ZPU which I can customise as necessary. -- --------------------------------------------------------------------------------------------------------- -- This source file is free software: you can redistribute it and-or modify @@ -28,6 +34,7 @@ package config_pkg is constant DEBUG_ENABLE : integer := 1; -- Enable debug logic, + constant ZPU_ENABLE : integer := 1; -- Enable local ZPU IO processor, constant NEO_ENABLE : integer := 0; -- Enable local NEO430 IO processor, constant STORM_ENABLE : integer := 0; -- Enable local STORM IO processor, diff --git a/common/dpram.vhd b/common/dpram.vhd index e61f2ac..95c3fc6 100644 --- a/common/dpram.vhd +++ b/common/dpram.vhd @@ -6,7 +6,8 @@ -- Description: Dual Port RAM as provided by Altera in the Megafunctions suite. -- -- Credits: --- Copyright: (c) 2018 Philip Smart +-- Copyright: (c) Altera/Intel +-- (c) 2018 Philip Smart -- -- History: July 2018 - Initial module written. -- diff --git a/emu.sv b/emu.sv index 02530d3..7e8e6f6 100644 --- a/emu.sv +++ b/emu.sv @@ -97,23 +97,26 @@ module emu output DDRAM_WE, //SDRAM interface with lower latency -// ,output SDRAM_CLK, -// output SDRAM_CKE, -// output [12:0] SDRAM_A, -// output [1:0] SDRAM_BA, -// inout [15:0] SDRAM_DQ, -// output SDRAM_DQML, -// output SDRAM_DQMH, -// output SDRAM_nCS, -// output SDRAM_nCAS, -// output SDRAM_nRAS, -// output SDRAM_nWE - input UART_RX, - output UART_TX + output SDRAM_CLK, + output SDRAM_CKE, + output [12:0] SDRAM_A, + output [1:0] SDRAM_BA, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nCS, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nWE, + + input UART_RX_0, + output UART_TX_0, + input UART_RX_1, + output UART_TX_1 ); //assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; -//assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; +//assign {DRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0; assign LED_USER = ioctl_download; @@ -275,14 +278,32 @@ bridge sharp_mz .audio_l_o(audio_l_emu), .audio_r_o(audio_r_emu), - .uart_rx(UART_RX), - .uart_tx(UART_TX), + // ZPU UART for Console and Debug channels. + .uart_rx_0(UART_RX_0), + .uart_tx_0(UART_TX_0), + .uart_rx_1(UART_RX_1), + .uart_tx_1(UART_TX_1), + + // SD Card on daughter board. .sd_sck(SD_SCK), .sd_mosi(SD_MOSI), .sd_miso(SD_MISO), .sd_cs(SD_CS), .sd_cd(SD_CD), + // SDRAM + .sdram_clk(SDRAM_CLK), + .sdram_cke(SDRAM_CKE), + .sdram_addr(SDRAM_A[12:0]), + .sdram_ba(SDRAM_BA), + .sdram_dq(SDRAM_DQ), + .sdram_dqml(SDRAM_DQML), + .sdram_dqmh(SDRAM_DQMH), + .sdram_cs_n(SDRAM_nCS), + .sdram_cas_n(SDRAM_nCAS), + .sdram_ras_n(SDRAM_nRAS), + .sdram_we_n(SDRAM_nWE), + // HPS Interface .ioctl_download(ioctl_download), // HPS Downloading to FPGA. .ioctl_upload(ioctl_upload), // HPS Uploading from FPGA. diff --git a/sharpmz-lite.qsf b/sharpmz-lite.qsf index 0c98c50..280e24a 100755 --- a/sharpmz-lite.qsf +++ b/sharpmz-lite.qsf @@ -1,41 +1,41 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition -# Date created = 01:53:32 April 20, 2017 -# -# -------------------------------------------------------------------------- # - +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 01:53:32 April 20, 2017 +# +# -------------------------------------------------------------------------- # + set_global_assignment -name VERILOG_MACRO "LITE=1" - + set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CSEBA6U23I7 -set_global_assignment -name TOP_LEVEL_ENTITY sys_top -#set_global_assignment -name TOP_LEVEL_ENTITY emu +set_global_assignment -name TOP_LEVEL_ENTITY sys_top +#set_global_assignment -name TOP_LEVEL_ENTITY emu set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 - + set_global_assignment -name GENERATE_RBF_FILE ON set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL @@ -54,54 +54,60 @@ set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name OPTIMIZATION_MODE "HIGH POWER EFFORT" set_global_assignment -name SEED 1 -#set_global_assignment -name SDC_FILE sharpmz.sdc +#set_global_assignment -name SDC_FILE sharpmz.sdc set_global_assignment -name SDC_FILE "sharpmz-lite.sdc" - -#============================================================ -# ADC -#============================================================ -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO -#set_location_assignment PIN_U9 -to ADC_CONVST -#set_location_assignment PIN_V10 -to ADC_SCK -#set_location_assignment PIN_AC4 -to ADC_SDI -#set_location_assignment PIN_AD4 -to ADC_SDO - -#============================================================ -# ARDUINO -#============================================================ -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] -#set_location_assignment PIN_AG9 -to ARDUINO_IO[3] -#set_location_assignment PIN_U14 -to ARDUINO_IO[4] -#set_location_assignment PIN_U13 -to ARDUINO_IO[5] -#set_location_assignment PIN_AG8 -to ARDUINO_IO[6] -#set_location_assignment PIN_AH8 -to ARDUINO_IO[7] -#set_location_assignment PIN_AF17 -to ARDUINO_IO[8] -#set_location_assignment PIN_AE15 -to ARDUINO_IO[9] -#set_location_assignment PIN_AF15 -to ARDUINO_IO[10] -#set_location_assignment PIN_AG16 -to ARDUINO_IO[11] -#set_location_assignment PIN_AH11 -to ARDUINO_IO[12] -#set_location_assignment PIN_AH12 -to ARDUINO_IO[13] -#set_location_assignment PIN_AH9 -to ARDUINO_IO[14] -#set_location_assignment PIN_AG11 -to ARDUINO_IO[15] - -#============================================================ -# SDIO -#============================================================ +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON +set_global_assignment -name ALLOW_REGISTER_RETIMING ON + + +#============================================================ +# ADC +#============================================================ +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO +#set_location_assignment PIN_U9 -to ADC_CONVST +#set_location_assignment PIN_V10 -to ADC_SCK +#set_location_assignment PIN_AC4 -to ADC_SDI +#set_location_assignment PIN_AD4 -to ADC_SDO + +#============================================================ +# ARDUINO +#============================================================ +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +#set_location_assignment PIN_AG9 -to ARDUINO_IO[3] +#set_location_assignment PIN_U14 -to ARDUINO_IO[4] +#set_location_assignment PIN_U13 -to ARDUINO_IO[5] +#set_location_assignment PIN_AG8 -to ARDUINO_IO[6] +#set_location_assignment PIN_AH8 -to ARDUINO_IO[7] +#set_location_assignment PIN_AF17 -to ARDUINO_IO[8] +#set_location_assignment PIN_AE15 -to ARDUINO_IO[9] +#set_location_assignment PIN_AF15 -to ARDUINO_IO[10] +#set_location_assignment PIN_AG16 -to ARDUINO_IO[11] +#set_location_assignment PIN_AH11 -to ARDUINO_IO[12] +#set_location_assignment PIN_AH12 -to ARDUINO_IO[13] +#set_location_assignment PIN_AH9 -to ARDUINO_IO[14] +#set_location_assignment PIN_AG11 -to ARDUINO_IO[15] + +#============================================================ +# SDIO +#============================================================ set_location_assignment PIN_AF25 -to SDIO_DAT[0] set_location_assignment PIN_AF23 -to SDIO_DAT[1] set_location_assignment PIN_AD26 -to SDIO_DAT[2] @@ -109,222 +115,222 @@ set_location_assignment PIN_AF28 -to SDIO_DAT[3] set_location_assignment PIN_AF27 -to SDIO_CMD set_location_assignment PIN_AH26 -to SDIO_CLK set_location_assignment PIN_AH7 -to SDIO_CD -# +# set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* -# +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_* set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*] set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD - -#============================================================ -# VGA -#============================================================ + +#============================================================ +# VGA +#============================================================ set_location_assignment PIN_AE17 -to VGA_R[0] set_location_assignment PIN_AE20 -to VGA_R[1] set_location_assignment PIN_AF20 -to VGA_R[2] set_location_assignment PIN_AH18 -to VGA_R[3] set_location_assignment PIN_AH19 -to VGA_R[4] set_location_assignment PIN_AF21 -to VGA_R[5] - + set_location_assignment PIN_AE19 -to VGA_G[0] set_location_assignment PIN_AG15 -to VGA_G[1] set_location_assignment PIN_AF18 -to VGA_G[2] set_location_assignment PIN_AG18 -to VGA_G[3] set_location_assignment PIN_AG19 -to VGA_G[4] set_location_assignment PIN_AG20 -to VGA_G[5] - + set_location_assignment PIN_AG21 -to VGA_B[0] set_location_assignment PIN_AA20 -to VGA_B[1] set_location_assignment PIN_AE22 -to VGA_B[2] set_location_assignment PIN_AF22 -to VGA_B[3] set_location_assignment PIN_AH23 -to VGA_B[4] set_location_assignment PIN_AH21 -to VGA_B[5] - + set_location_assignment PIN_AH22 -to VGA_HS set_location_assignment PIN_AG24 -to VGA_VS - + set_location_assignment PIN_AH27 -to VGA_EN set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN - + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_* - -#============================================================ -# AUDIO -#============================================================ + +#============================================================ +# AUDIO +#============================================================ set_location_assignment PIN_AC24 -to AUDIO_L set_location_assignment PIN_AE25 -to AUDIO_R -set_location_assignment PIN_AG26 -to AUDIO_SPDIF +#set_location_assignment PIN_AG26 -to AUDIO_SPDIF set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_* set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_* - -#============================================================ -# SDRAM -#============================================================ -#set_location_assignment PIN_Y11 -to SDRAM_A[0] -#set_location_assignment PIN_AA26 -to SDRAM_A[1] -#set_location_assignment PIN_AA13 -to SDRAM_A[2] -#set_location_assignment PIN_AA11 -to SDRAM_A[3] -#set_location_assignment PIN_W11 -to SDRAM_A[4] -#set_location_assignment PIN_Y19 -to SDRAM_A[5] -#set_location_assignment PIN_AB23 -to SDRAM_A[6] -#set_location_assignment PIN_AC23 -to SDRAM_A[7] -#set_location_assignment PIN_AC22 -to SDRAM_A[8] -#set_location_assignment PIN_C12 -to SDRAM_A[9] -#set_location_assignment PIN_AB26 -to SDRAM_A[10] -#set_location_assignment PIN_AD17 -to SDRAM_A[11] -#set_location_assignment PIN_D12 -to SDRAM_A[12] -#set_location_assignment PIN_Y17 -to SDRAM_BA[0] -#set_location_assignment PIN_AB25 -to SDRAM_BA[1] - -#set_location_assignment PIN_E8 -to SDRAM_DQ[0] -#set_location_assignment PIN_V12 -to SDRAM_DQ[1] -#set_location_assignment PIN_D11 -to SDRAM_DQ[2] -#set_location_assignment PIN_W12 -to SDRAM_DQ[3] -#set_location_assignment PIN_AH13 -to SDRAM_DQ[4] -#set_location_assignment PIN_D8 -to SDRAM_DQ[5] -#set_location_assignment PIN_AH14 -to SDRAM_DQ[6] -#set_location_assignment PIN_AF7 -to SDRAM_DQ[7] -#set_location_assignment PIN_AE24 -to SDRAM_DQ[8] -#set_location_assignment PIN_AD23 -to SDRAM_DQ[9] -#set_location_assignment PIN_AE6 -to SDRAM_DQ[10] -#set_location_assignment PIN_AE23 -to SDRAM_DQ[11] -#set_location_assignment PIN_AG14 -to SDRAM_DQ[12] -#set_location_assignment PIN_AD5 -to SDRAM_DQ[13] -#set_location_assignment PIN_AF4 -to SDRAM_DQ[14] -#set_location_assignment PIN_AH3 -to SDRAM_DQ[15] -#set_location_assignment PIN_AG13 -to SDRAM_DQML -#set_location_assignment PIN_AF13 -to SDRAM_DQMH - -#set_location_assignment PIN_AD20 -to SDRAM_CLK -#set_location_assignment PIN_AG10 -to SDRAM_CKE - -#set_location_assignment PIN_AA19 -to SDRAM_nWE -#set_location_assignment PIN_AA18 -to SDRAM_nCAS -#set_location_assignment PIN_Y18 -to SDRAM_nCS -#set_location_assignment PIN_W14 -to SDRAM_nRAS - -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* -#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* -#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A* -#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA* -#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] -#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM* -#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n* -#set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] -#set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* - -#============================================================ -# I/O -#============================================================ -set_location_assignment PIN_Y15 -to LED_USER -set_location_assignment PIN_AA15 -to LED_HDD -set_location_assignment PIN_AG28 -to LED_POWER - + +#============================================================ +# SDRAM +#============================================================ +set_location_assignment PIN_Y11 -to SDRAM_A[0] +set_location_assignment PIN_AA26 -to SDRAM_A[1] +set_location_assignment PIN_AA13 -to SDRAM_A[2] +set_location_assignment PIN_AA11 -to SDRAM_A[3] +set_location_assignment PIN_W11 -to SDRAM_A[4] +set_location_assignment PIN_Y19 -to SDRAM_A[5] +set_location_assignment PIN_AB23 -to SDRAM_A[6] +set_location_assignment PIN_AC23 -to SDRAM_A[7] +set_location_assignment PIN_AC22 -to SDRAM_A[8] +set_location_assignment PIN_C12 -to SDRAM_A[9] +set_location_assignment PIN_AB26 -to SDRAM_A[10] +set_location_assignment PIN_AD17 -to SDRAM_A[11] +set_location_assignment PIN_D12 -to SDRAM_A[12] +set_location_assignment PIN_Y17 -to SDRAM_BA[0] +set_location_assignment PIN_AB25 -to SDRAM_BA[1] + +set_location_assignment PIN_E8 -to SDRAM_DQ[0] +set_location_assignment PIN_V12 -to SDRAM_DQ[1] +set_location_assignment PIN_D11 -to SDRAM_DQ[2] +set_location_assignment PIN_W12 -to SDRAM_DQ[3] +set_location_assignment PIN_AH13 -to SDRAM_DQ[4] +set_location_assignment PIN_D8 -to SDRAM_DQ[5] +set_location_assignment PIN_AH14 -to SDRAM_DQ[6] +set_location_assignment PIN_AF7 -to SDRAM_DQ[7] +set_location_assignment PIN_AE24 -to SDRAM_DQ[8] +set_location_assignment PIN_AD23 -to SDRAM_DQ[9] +set_location_assignment PIN_AE6 -to SDRAM_DQ[10] +set_location_assignment PIN_AE23 -to SDRAM_DQ[11] +set_location_assignment PIN_AG14 -to SDRAM_DQ[12] +set_location_assignment PIN_AD5 -to SDRAM_DQ[13] +set_location_assignment PIN_AF4 -to SDRAM_DQ[14] +set_location_assignment PIN_AH3 -to SDRAM_DQ[15] +set_location_assignment PIN_AG13 -to SDRAM_DQML +set_location_assignment PIN_AF13 -to SDRAM_DQMH + +set_location_assignment PIN_AD20 -to SDRAM_CLK +set_location_assignment PIN_AG10 -to SDRAM_CKE + +set_location_assignment PIN_AA19 -to SDRAM_nWE +set_location_assignment PIN_AA18 -to SDRAM_nCAS +set_location_assignment PIN_Y18 -to SDRAM_nCS +set_location_assignment PIN_W14 -to SDRAM_nRAS + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n* +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* + +#============================================================ +# I/O +#============================================================ +#set_location_assignment PIN_Y15 -to LED_USER +#set_location_assignment PIN_AA15 -to LED_HDD +#set_location_assignment PIN_AG28 -to LED_POWER + set_location_assignment PIN_AH24 -to BTN_USER set_location_assignment PIN_AG25 -to BTN_OSD set_location_assignment PIN_AG23 -to BTN_RESET - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* + +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_* - -#============================================================ -# CLOCK -#============================================================ + +#============================================================ +# CLOCK +#============================================================ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 set_location_assignment PIN_V11 -to FPGA_CLK1_50 set_location_assignment PIN_Y13 -to FPGA_CLK2_50 set_location_assignment PIN_E11 -to FPGA_CLK3_50 - -#============================================================ -# HDMI -#============================================================ -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS -#set_location_assignment PIN_U10 -to HDMI_I2C_SCL -#set_location_assignment PIN_AA4 -to HDMI_I2C_SDA -#set_location_assignment PIN_T13 -to HDMI_I2S -#set_location_assignment PIN_T11 -to HDMI_LRCLK -#set_location_assignment PIN_U11 -to HDMI_MCLK -#set_location_assignment PIN_T12 -to HDMI_SCLK -#set_location_assignment PIN_AG5 -to HDMI_TX_CLK -#set_location_assignment PIN_AD19 -to HDMI_TX_DE -#set_location_assignment PIN_AD12 -to HDMI_TX_D[0] -#set_location_assignment PIN_AE12 -to HDMI_TX_D[1] -#set_location_assignment PIN_W8 -to HDMI_TX_D[2] -#set_location_assignment PIN_Y8 -to HDMI_TX_D[3] -#set_location_assignment PIN_AD11 -to HDMI_TX_D[4] -#set_location_assignment PIN_AD10 -to HDMI_TX_D[5] -#set_location_assignment PIN_AE11 -to HDMI_TX_D[6] -#set_location_assignment PIN_Y5 -to HDMI_TX_D[7] -#set_location_assignment PIN_AF10 -to HDMI_TX_D[8] -#set_location_assignment PIN_Y4 -to HDMI_TX_D[9] -#set_location_assignment PIN_AE9 -to HDMI_TX_D[10] -#set_location_assignment PIN_AB4 -to HDMI_TX_D[11] -#set_location_assignment PIN_AE7 -to HDMI_TX_D[12] -#set_location_assignment PIN_AF6 -to HDMI_TX_D[13] -#set_location_assignment PIN_AF8 -to HDMI_TX_D[14] -#set_location_assignment PIN_AF5 -to HDMI_TX_D[15] -#set_location_assignment PIN_AE4 -to HDMI_TX_D[16] -#set_location_assignment PIN_AH2 -to HDMI_TX_D[17] -#set_location_assignment PIN_AH4 -to HDMI_TX_D[18] -#set_location_assignment PIN_AH5 -to HDMI_TX_D[19] -#set_location_assignment PIN_AH6 -to HDMI_TX_D[20] -#set_location_assignment PIN_AG6 -to HDMI_TX_D[21] -#set_location_assignment PIN_AF9 -to HDMI_TX_D[22] -#set_location_assignment PIN_AE8 -to HDMI_TX_D[23] -#set_location_assignment PIN_T8 -to HDMI_TX_HS -#set_location_assignment PIN_AF11 -to HDMI_TX_INT -#set_location_assignment PIN_V13 -to HDMI_TX_VS - -#============================================================ -# KEY -#============================================================ + +#============================================================ +# HDMI +#============================================================ +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS +#set_location_assignment PIN_U10 -to HDMI_I2C_SCL +#set_location_assignment PIN_AA4 -to HDMI_I2C_SDA +#set_location_assignment PIN_T13 -to HDMI_I2S +#set_location_assignment PIN_T11 -to HDMI_LRCLK +#set_location_assignment PIN_U11 -to HDMI_MCLK +#set_location_assignment PIN_T12 -to HDMI_SCLK +#set_location_assignment PIN_AG5 -to HDMI_TX_CLK +#set_location_assignment PIN_AD19 -to HDMI_TX_DE +#set_location_assignment PIN_AD12 -to HDMI_TX_D[0] +#set_location_assignment PIN_AE12 -to HDMI_TX_D[1] +#set_location_assignment PIN_W8 -to HDMI_TX_D[2] +#set_location_assignment PIN_Y8 -to HDMI_TX_D[3] +#set_location_assignment PIN_AD11 -to HDMI_TX_D[4] +#set_location_assignment PIN_AD10 -to HDMI_TX_D[5] +#set_location_assignment PIN_AE11 -to HDMI_TX_D[6] +#set_location_assignment PIN_Y5 -to HDMI_TX_D[7] +#set_location_assignment PIN_AF10 -to HDMI_TX_D[8] +#set_location_assignment PIN_Y4 -to HDMI_TX_D[9] +#set_location_assignment PIN_AE9 -to HDMI_TX_D[10] +#set_location_assignment PIN_AB4 -to HDMI_TX_D[11] +#set_location_assignment PIN_AE7 -to HDMI_TX_D[12] +#set_location_assignment PIN_AF6 -to HDMI_TX_D[13] +#set_location_assignment PIN_AF8 -to HDMI_TX_D[14] +#set_location_assignment PIN_AF5 -to HDMI_TX_D[15] +#set_location_assignment PIN_AE4 -to HDMI_TX_D[16] +#set_location_assignment PIN_AH2 -to HDMI_TX_D[17] +#set_location_assignment PIN_AH4 -to HDMI_TX_D[18] +#set_location_assignment PIN_AH5 -to HDMI_TX_D[19] +#set_location_assignment PIN_AH6 -to HDMI_TX_D[20] +#set_location_assignment PIN_AG6 -to HDMI_TX_D[21] +#set_location_assignment PIN_AF9 -to HDMI_TX_D[22] +#set_location_assignment PIN_AE8 -to HDMI_TX_D[23] +#set_location_assignment PIN_T8 -to HDMI_TX_HS +#set_location_assignment PIN_AF11 -to HDMI_TX_INT +#set_location_assignment PIN_V13 -to HDMI_TX_VS + +#============================================================ +# KEY +#============================================================ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] set_location_assignment PIN_AH17 -to KEY[0] set_location_assignment PIN_AH16 -to KEY[1] - -#============================================================ -# LED -#============================================================ + +#============================================================ +# LED +#============================================================ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] @@ -341,21 +347,37 @@ set_location_assignment PIN_AF26 -to LED[4] set_location_assignment PIN_AE26 -to LED[5] set_location_assignment PIN_Y16 -to LED[6] set_location_assignment PIN_AA23 -to LED[7] - -#============================================================ -# SW -#============================================================ -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] -#set_location_assignment PIN_Y24 -to SW[0] -#set_location_assignment PIN_W24 -to SW[1] -#set_location_assignment PIN_W21 -to SW[2] -#set_location_assignment PIN_W20 -to SW[3] - + +#============================================================ +# UART +#============================================================ +set_location_assignment PIN_Y15 -to UART_TX_0 +# Enable LEDs when not debugging. +set_location_assignment PIN_AA15 -to UART_RX_0 +set_location_assignment PIN_AG28 -to UART_TX_1 +set_location_assignment PIN_AG26 -to UART_RX_1 +# Enable audio spdif when not debugging. +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1 + +#============================================================ +# SW +#============================================================ +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +#set_location_assignment PIN_Y24 -to SW[0] +#set_location_assignment PIN_W24 -to SW[1] +#set_location_assignment PIN_W21 -to SW[2] +#set_location_assignment PIN_W20 -to SW[3] + set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" - + set_global_assignment -name CDF_FILE jtag.cdf set_global_assignment -name QIP_FILE sys/sys.qip set_global_assignment -name VHDL_FILE jtag_uart_0.vhd @@ -363,10 +385,10 @@ set_global_assignment -name SYSTEMVERILOG_FILE emu.sv set_global_assignment -name VHDL_FILE common/config_pkg.vhd set_global_assignment -name VHDL_FILE bridge.vhd set_global_assignment -name VHDL_FILE sharpmz.vhd - -#============================================================ -# Latest T80 CPU -#============================================================ + +#============================================================ +# Latest T80 CPU +#============================================================ set_global_assignment -name VHDL_FILE common/T80/T80.vhd set_global_assignment -name VHDL_FILE common/T80/T8080se.vhd set_global_assignment -name VHDL_FILE common/T80/T80_ALU.vhd @@ -376,33 +398,75 @@ set_global_assignment -name VHDL_FILE common/T80/T80_Reg.vhd set_global_assignment -name VHDL_FILE common/T80/T80a.vhd set_global_assignment -name VHDL_FILE common/T80/T80se.vhd set_global_assignment -name VHDL_FILE common/T80/T80sed.vhd - -#============================================================ -# i8253 Programmable Interval Timer -#============================================================ + +#============================================================ +# i8253 Programmable Interval Timer +#============================================================ set_global_assignment -name VHDL_FILE common/i8254/i8254_counter.vhd set_global_assignment -name VHDL_FILE common/i8254/i8254.vhd - -#============================================================ -# i8255 Programmable Peripheral Interface -#============================================================ + +#============================================================ +# i8255 Programmable Peripheral Interface +#============================================================ set_global_assignment -name VHDL_FILE common/i8255/i8255.vhd -#set_global_assignment -name VHDL_FILE mz80b/i8255/i8255.vhd - -#============================================================ -# MZ80C specific modules. -#============================================================ +#set_global_assignment -name VHDL_FILE mz80b/i8255/i8255.vhd + +#============================================================ +# MZ80C specific modules. +#============================================================ set_global_assignment -name VHDL_FILE mz80c/mz80c.vhd - -#============================================================ -# MZ80B specific modules. -#============================================================ -#set_global_assignment -name VHDL_FILE mz80b/mz80b_dummy.vhd + +#============================================================ +# MZ80B specific modules. +#============================================================ +#set_global_assignment -name VHDL_FILE mz80b/mz80b_dummy.vhd set_global_assignment -name VHDL_FILE mz80b/mz80b.vhd - -#============================================================ -# NEO430 -#============================================================ + +#============================================================ +# ZPU Evo +#============================================================ +set_global_assignment -name QIP_FILE zpu/build/Clock_50to100.qip +set_global_assignment -name VHDL_FILE zpu/cpu/zpu_core_flex.vhd +set_global_assignment -name VHDL_FILE zpu/cpu/zpu_pkg.vhd +set_global_assignment -name VHDL_FILE zpu/cpu/zpu_core_small.vhd +set_global_assignment -name VHDL_FILE zpu/cpu/zpu_core_medium.vhd +set_global_assignment -name VHDL_FILE zpu/cpu/zpu_core_evo.vhd +set_global_assignment -name VHDL_FILE zpu/cpu/zpu_core_evo_L2.vhd +set_global_assignment -name VHDL_FILE zpu/cpu/zpu_uart_debug.vhd +set_global_assignment -name VHDL_FILE zpu/zpu_soc_pkg.vhd +set_global_assignment -name VHDL_FILE zpu/zpu_soc.vhd +#set_global_assignment -name VHDL_FILE zpu/devices/sysbus/RAM/dpram.vhd +set_global_assignment -name VHDL_FILE zpu/devices/sysbus/uart/uart.vhd +set_global_assignment -name VHDL_FILE zpu/devices/sysbus/intr/interrupt_controller.vhd +set_global_assignment -name VHDL_FILE zpu/devices/sysbus/spi/spi.vhd +set_global_assignment -name VHDL_FILE zpu/devices/sysbus/SDMMC/SDCard.vhd +set_global_assignment -name VHDL_FILE zpu/devices/sysbus/ps2/io_ps2_com.vhd +set_global_assignment -name VHDL_FILE zpu/devices/sysbus/timer/timer_controller.vhd +set_global_assignment -name VHDL_FILE zpu/devices/sysbus/BRAM/BootROM.vhd +set_global_assignment -name VHDL_FILE zpu/devices/sysbus/BRAM/DualPortBootBRAM.vhd +set_global_assignment -name VHDL_FILE zpu/devices/sysbus/BRAM/SinglePortBootBRAM.vhd +set_global_assignment -name VHDL_FILE zpu/devices/sysbus/BRAM/SinglePortBRAM.vhd +set_global_assignment -name VHDL_FILE zpu/devices/sysbus/ioctl/ioctl.vhd +#set_global_assignment -name VHDL_FILE zpu/devices/sysbus/TCPU/tcpu.vhd +#set_global_assignment -name QIP_FILE zpu/devices/sysbus/SDRAM/48LC16M16.qip +#set_global_assignment -name QIP_FILE zpu/devices/sysbus/SDRAM/48LC16M16_cached.qip +set_global_assignment -name QIP_FILE zpu/devices/sysbus/SDRAM/AS4C16M16SA.qip +#set_global_assignment -name QIP_FILE zpu/devices/sysbus/SDRAM/AS4C16M16SA_cached.qip +#set_global_assignment -name QIP_FILE zpu/devices/sysbus/SDRAM/W9864G6.qip +#set_global_assignment -name QIP_FILE zpu/devices/sysbus/SDRAM/W9864G6_cached.qip +#set_global_assignment -name VHDL_FILE zpu/devices/WishBone/I2C/i2c_master_top.vhd +#set_global_assignment -name VHDL_FILE zpu/devices/WishBone/I2C/i2c_master_byte_ctrl.vhd +#set_global_assignment -name VHDL_FILE zpu/devices/WishBone/I2C/i2c_master_bit_ctrl.vhd +#set_global_assignment -name QIP_FILE zpu/devices/WishBone/SDRAM/48LC16M16.qip +#set_global_assignment -name QIP_FILE zpu/devices/WishBone/SDRAM/48LC16M16_cached.qip +#set_global_assignment -name QIP_FILE zpu/devices/WishBone/SDRAM/W9864G6.qip +#set_global_assignment -name QIP_FILE zpu/devices/WishBone/SDRAM/W9864G6_cached.qip +#set_global_assignment -name QIP_FILE zpu/devices/WishBone/SDRAM/wbsdram.qip +#set_global_assignment -name VHDL_FILE zpu/devices/WishBone/SDRAM/wbsdram.vhd + +#============================================================ +# NEO430 +#============================================================ #set_global_assignment -name VHDL_FILE neo430/neo430.vhd #set_global_assignment -name VHDL_FILE neo430/neo430_addr_gen.vhd #set_global_assignment -name VHDL_FILE neo430/neo430_alu.vhd @@ -428,9 +492,9 @@ set_global_assignment -name VHDL_FILE mz80b/mz80b.vhd #set_global_assignment -name VHDL_FILE neo430/neo430_twi.vhd #set_global_assignment -name VHDL_FILE neo430/neo430_wb_interface.vhd #set_global_assignment -name VHDL_FILE neo430/neo430_wdt.vhd -#============================================================ -# STORM -#============================================================ +#============================================================ +# STORM +#============================================================ #set_global_assignment -name VHDL_FILE storm/STORM_SoC.vhd #set_global_assignment -name VHDL_FILE storm/CPU/ALU.vhd #set_global_assignment -name VHDL_FILE storm/CPU/BARREL_SHIFTER.vhd @@ -472,18 +536,18 @@ set_global_assignment -name VHDL_FILE mz80b/mz80b.vhd #set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_shift.v #set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/timescale.v -#============================================================ -# PLL -#============================================================ +#============================================================ +# PLL +#============================================================ set_global_assignment -name QIP_FILE common/pll.qip set_global_assignment -name VHDL_FILE common/clkgen.vhd -#set_global_assignment -name QIP_FILE common/pll_1.qip -#set_global_assignment -name QIP_FILE common/pll_2.qip -#set_global_assignment -name QIP_FILE common/pll_4.qip - -#============================================================ -# Common modules -#============================================================ +#set_global_assignment -name QIP_FILE common/pll_1.qip +#set_global_assignment -name QIP_FILE common/pll_2.qip +#set_global_assignment -name QIP_FILE common/pll_4.qip + +#============================================================ +# Common modules +#============================================================ set_global_assignment -name VHDL_FILE common/dprom.vhd set_global_assignment -name VHDL_FILE common/clk_div.vhd set_global_assignment -name VHDL_FILE common/mctrl.vhd @@ -493,44 +557,26 @@ set_global_assignment -name VHDL_FILE common/video.vhd set_global_assignment -name VHDL_FILE common/cmt.vhd set_global_assignment -name VHDL_FILE common/z8420/z8420.vhd set_global_assignment -name VHDL_FILE common/z8420/Interrupt.vhd - -#============================================================ -# Functions -#============================================================ + +#============================================================ +# Functions +#============================================================ set_global_assignment -name VHDL_FILE common/functions.vhd - -set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON -set_global_assignment -name ALLOW_REGISTER_RETIMING ON - - -set_location_assignment PIN_AA13 -to UART_TX -set_location_assignment PIN_AA11 -to UART_RX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX -# -#set_location_assignment PIN_AF25 -to SPI_MISO -#set_location_assignment PIN_AF28 -to SPI_CS[0] -#set_location_assignment PIN_AF27 -to SPI_MOSI -#set_location_assignment PIN_AH26 -to SPI_SCLK - -#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_MISO -#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_CS[0] -#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_MOSI -#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_SCLK - -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CS[0] -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCLK -#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SPI_MISO - - - - - - - - - -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + +# +#set_location_assignment PIN_AF25 -to SPI_MISO +#set_location_assignment PIN_AF28 -to SPI_CS[0] +#set_location_assignment PIN_AF27 -to SPI_MOSI +#set_location_assignment PIN_AH26 -to SPI_SCLK + +#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_MISO +#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_CS[0] +#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_MOSI +#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_SCLK + +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CS[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCLK +#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SPI_MISO diff --git a/sharpmz.vhd b/sharpmz.vhd index f0d3b24..2742c70 100644 --- a/sharpmz.vhd +++ b/sharpmz.vhd @@ -83,7 +83,6 @@ entity sharpmz is CLKMASTER : in std_logic; -- Master Clock(50MHz) CLKSYS : out std_logic; -- System clock. CLKVID : out std_logic; -- Pixel base clock of video. - CLKIOP : out std_logic; -- IO Processor Clock. -------------------- Reset ---------------------------- COLD_RESET : in std_logic; WARM_RESET : in std_logic; @@ -1090,7 +1089,6 @@ begin -- CLKSYS <= CLKBUS(CKMASTER); -- HPS clock. CLKVID <= CLKBUS(CKVIDEO); -- Video pixel clock output. - CLKIOP <= CLKBUS(CKIOP); -- IO Processor Clock. -- Multiplexer -> Signals to enabled hardware. -- diff --git a/sys/sys_top.v b/sys/sys_top.v index 9818319..ca04f29 100644 --- a/sys/sys_top.v +++ b/sys/sys_top.v @@ -59,7 +59,7 @@ module sys_top `endif //////////// SDR /////////// -`ifndef LITE +//`ifndef LITE output [12:0] SDRAM_A, inout [15:0] SDRAM_DQ, output SDRAM_DQML, @@ -71,15 +71,17 @@ module sys_top output [1:0] SDRAM_BA, output SDRAM_CLK, output SDRAM_CKE, -`else - input UART_RX, - output UART_TX, -`endif +//`else + input UART_RX_0, + output UART_TX_0, + input UART_RX_1, + output UART_TX_1, +//`endif //////////// I/O /////////// - output LED_USER, - output LED_HDD, - output LED_POWER, +// output LED_USER, +// output LED_HDD, +// output LED_POWER, input BTN_USER, input BTN_OSD, input BTN_RESET, @@ -115,9 +117,9 @@ wire led_u = ~led_user; wire [7:0] led_mb; assign LED = led_mb; -assign LED_POWER = led_p ? 1'bZ : 1'b0; -assign LED_HDD = led_d ? 1'bZ : 1'b0; -assign LED_USER = led_u ? 1'bZ : 1'b0; +//assign LED_POWER = led_p ? 1'bZ : 1'b0; +//assign LED_HDD = led_d ? 1'bZ : 1'b0; +//assign LED_USER = led_u ? 1'bZ : 1'b0; //LEDs on main board //assign LED = (led_overtake & led_state) | (~led_overtake & {3'b000, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u}); @@ -940,8 +942,6 @@ emu emu .SD_CS(SDIO_DAT[3]), .SD_CD(VGA_EN ? VGA_HS : SDIO_CD), - - .DDRAM_CLK(ram_clk), .DDRAM_ADDR(ram_address), .DDRAM_BURSTCNT(ram_burstcount), @@ -953,7 +953,7 @@ emu emu .DDRAM_BE(ram_byteenable), .DDRAM_WE(ram_write) -`ifndef LITE +//`ifndef LITE , .SDRAM_DQ(SDRAM_DQ), .SDRAM_A(SDRAM_A), @@ -965,11 +965,13 @@ emu emu .SDRAM_nRAS(SDRAM_nRAS), .SDRAM_nCAS(SDRAM_nCAS), .SDRAM_CLK(SDRAM_CLK), - .SDRAM_CKE(SDRAM_CKE) -`else - ,.UART_RX(UART_RX), - .UART_TX(UART_TX) -`endif + .SDRAM_CKE(SDRAM_CKE), +//`else + .UART_RX_0(UART_RX_0), + .UART_TX_0(UART_TX_0), + .UART_RX_1(UART_RX_1), + .UART_TX_1(UART_TX_1) +//`endif ); endmodule diff --git a/zpu/build/CYC1000_zpu.qpf b/zpu/build/CYC1000_zpu.qpf new file mode 100644 index 0000000..b4d2262 --- /dev/null +++ b/zpu/build/CYC1000_zpu.qpf @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "5.0" +DATE = "23:35:58 September 01, 2005" + + +# Revisions + +PROJECT_REVISION = "CYC1000_zpu" diff --git a/zpu/build/CYC1000_zpu.qsf b/zpu/build/CYC1000_zpu.qsf new file mode 100644 index 0000000..9cdeaa3 --- /dev/null +++ b/zpu/build/CYC1000_zpu.qsf @@ -0,0 +1,421 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition +# Date created = 11:51:50 November 03, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# cyc1000_nios_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:51:50 NOVEMBER 03, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone 10 LP" +set_global_assignment -name TOP_LEVEL_ENTITY CYC1000_zpu + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE 10CL025YU256C8G +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" + +# Assembler Assignments +# ===================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "COMPILER CONFIGURED" +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +#============================================================ +# UART +#============================================================ +set_location_assignment PIN_F13 -to UART_TX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0 +set_location_assignment PIN_F15 -to UART_RX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0 +set_location_assignment PIN_D15 -to UART_RX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1 +set_location_assignment PIN_C15 -to UART_TX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1 + +#============================================================ +# SD CARD +#============================================================ +set_location_assignment PIN_F16 -to SDCARD_MISO[0] +set_location_assignment PIN_D16 -to SDCARD_MOSI[0] +set_location_assignment PIN_B16 -to SDCARD_CLK[0] +set_location_assignment PIN_C16 -to SDCARD_CS[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0] + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_M2 -to CLOCK_12M +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_12M +set_location_assignment PIN_E15 -to CLK_X +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_X + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_N3 -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_location_assignment PIN_N5 -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_location_assignment PIN_R4 -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_location_assignment PIN_T2 -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_location_assignment PIN_R3 -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_location_assignment PIN_T3 -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_location_assignment PIN_T4 -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_location_assignment PIN_M6 -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] + +#============================================================ +# SDRAM +#============================================================ +# Data bus +set_location_assignment PIN_B10 -to SDRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0] +set_location_assignment PIN_A10 -to SDRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1] +set_location_assignment PIN_B11 -to SDRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2] +set_location_assignment PIN_A11 -to SDRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3] +set_location_assignment PIN_A12 -to SDRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4] +set_location_assignment PIN_D9 -to SDRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5] +set_location_assignment PIN_B12 -to SDRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6] +set_location_assignment PIN_C9 -to SDRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7] +set_location_assignment PIN_D11 -to SDRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8] +set_location_assignment PIN_E11 -to SDRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9] +set_location_assignment PIN_A15 -to SDRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10] +set_location_assignment PIN_E9 -to SDRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11] +set_location_assignment PIN_D14 -to SDRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12] +set_location_assignment PIN_F9 -to SDRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13] +set_location_assignment PIN_C14 -to SDRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14] +set_location_assignment PIN_A14 -to SDRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15] +# Address Bus +set_location_assignment PIN_A3 -to SDRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[0] +set_location_assignment PIN_B5 -to SDRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[1] +set_location_assignment PIN_B4 -to SDRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[2] +set_location_assignment PIN_B3 -to SDRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[3] +set_location_assignment PIN_C3 -to SDRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[4] +set_location_assignment PIN_D3 -to SDRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[5] +set_location_assignment PIN_E6 -to SDRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[6] +set_location_assignment PIN_E7 -to SDRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[7] +set_location_assignment PIN_D6 -to SDRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[8] +set_location_assignment PIN_D8 -to SDRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[9] +set_location_assignment PIN_A5 -to SDRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[10] +set_location_assignment PIN_E8 -to SDRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11] +set_location_assignment PIN_A2 -to SDRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[12] +set_location_assignment PIN_C6 -to SDRAM_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[13] +# Byte addressing +set_location_assignment PIN_A4 -to SDRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0] +set_location_assignment PIN_B6 -to SDRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1] +set_location_assignment PIN_B13 -to SDRAM_DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[0] +set_location_assignment PIN_D12 -to SDRAM_DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[1] +# Chip control. +set_location_assignment PIN_C8 -to SDRAM_CAS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS +set_location_assignment PIN_B7 -to SDRAM_RAS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS +set_location_assignment PIN_A7 -to SDRAM_WE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE +set_location_assignment PIN_A6 -to SDRAM_CS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS +# Clock and enabling. +set_location_assignment PIN_F8 -to SDRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE +set_location_assignment PIN_B14 -to SDRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK + +#============================================================ +# FT2232H +#============================================================ +# ADBUS +set_location_assignment PIN_H3 -to ADBUS_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_0 +set_location_assignment PIN_H4 -to ADBUS_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_1 +set_location_assignment PIN_J4 -to ADBUS_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_2 +set_location_assignment PIN_J5 -to ADBUS_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_3 +set_location_assignment PIN_M8 -to ADBUS_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_4 +set_location_assignment PIN_N8 -to ADBUS_7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_7 +# BDBUS +set_location_assignment PIN_R7 -to BDBUS[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[0] +set_location_assignment PIN_T7 -to BDBUS[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[1] +set_location_assignment PIN_R6 -to BDBUS[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[2] +set_location_assignment PIN_T6 -to BDBUS[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[3] +set_location_assignment PIN_R5 -to BDBUS[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[4] +set_location_assignment PIN_T5 -to BDBUS[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[5] + +#============================================================ +# Serial Configuration Memory +#============================================================ +set_location_assignment PIN_H2 -to AS_DATA0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_DATA0 +set_location_assignment PIN_C1 -to AS_ASDO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_ASDO +set_location_assignment PIN_D2 -to AS_NCS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_NCS +set_location_assignment PIN_H1 -to AS_DCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_DCLK + +#============================================================ +# PMOD IO Header PIO0 - PIO7 +#============================================================ +#set_location_assignment PIN_F13 -to PIO[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[1] +#set_location_assignment PIN_F15 -to PIO[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[2] +#set_location_assignment PIN_F16 -to PIO[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[3] +#set_location_assignment PIN_D16 -to PIO[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[4] +#set_location_assignment PIN_D15 -to PIO[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[5] +#set_location_assignment PIN_C15 -to PIO[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[6] +#set_location_assignment PIN_B16 -to PIO[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[7] +#set_location_assignment PIN_C16 -to PIO[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[8] + +#============================================================ +# GPIO14 - GPIO22 Header +#============================================================ +set_location_assignment PIN_N2 -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_location_assignment PIN_N1 -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_location_assignment PIN_P2 -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_location_assignment PIN_J1 -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_location_assignment PIN_J2 -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_location_assignment PIN_K2 -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_location_assignment PIN_L2 -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_location_assignment PIN_P1 -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_location_assignment PIN_R1 -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] + +#============================================================ +# GPIO8 - GPIO13 Header +#============================================================ +set_location_assignment PIN_N16 -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_location_assignment PIN_L15 -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_location_assignment PIN_L16 -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_location_assignment PIN_K15 -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_location_assignment PIN_K16 -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_location_assignment PIN_J14 -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_location_assignment PIN_K1 -to D11_R +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D11_R +set_location_assignment PIN_L1 -to D12_R +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D12_R + +#============================================================ +# GPIO0 - GPIO7 Header +#============================================================ +set_location_assignment PIN_T12 -to AIN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AIN +set_location_assignment PIN_P11 -to AREF +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AREF +set_location_assignment PIN_R12 -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_location_assignment PIN_T13 -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_location_assignment PIN_R13 -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_location_assignment PIN_T14 -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_location_assignment PIN_P14 -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_location_assignment PIN_R14 -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_location_assignment PIN_T15 -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_location_assignment PIN_R11 -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] + +#============================================================ +# Buttons +#============================================================ +set_location_assignment PIN_N6 -to USER_BTN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_BTN + +#============================================================ +# 3-Axis Accelerometer +#============================================================ +set_location_assignment PIN_D1 -to SEN_CS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_CS +set_location_assignment PIN_B1 -to SEN_INT1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_INT1 +set_location_assignment PIN_C2 -to SEN_INT2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_INT2 +set_location_assignment PIN_G2 -to SEN_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_SDI +set_location_assignment PIN_G1 -to SEN_SDO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_SDO +set_location_assignment PIN_F3 -to SEN_SPC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_SPC + +#============================================================ +# Modules and Files +#============================================================ +# +set_global_assignment -name VHDL_FILE ../CYC1000_zpu_Toplevel.vhd +set_global_assignment -name QIP_FILE Clock_12to100.qip +set_global_assignment -name SDC_FILE CYC1000_zpu_constraints.sdc +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd +#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip +set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" + +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/zpu/build/CYC1000_zpu_Toplevel.vhd b/zpu/build/CYC1000_zpu_Toplevel.vhd new file mode 100644 index 0000000..5b600c4 --- /dev/null +++ b/zpu/build/CYC1000_zpu_Toplevel.vhd @@ -0,0 +1,176 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.zpu_soc_pkg.all; + +entity CYC1000_zpu is + port ( + -- Clock + CLOCK_12M : in std_logic; + -- LED + LED : out std_logic_vector(7 downto 0); + -- Debounced keys +-- KEY : in std_logic_vector(1 downto 0); + -- DIP switches +-- SW : in std_logic_vector(3 downto 0); + USER_BTN : in std_logic; + + -- TDI : in std_logic; + -- TCK : in std_logic; + -- TCS : in std_logic; + -- TDO : out std_logic; + -- I2C_SDAT : inout std_logic; + -- I2C_SCLK : out std_logic; + -- GPIO_0 : inout std_logic_vector(33 downto 0); + -- GPIO_1 : inout std_logic_vector(33 downto 0); + + -- SD Card 1 + SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + + UART_RX_0 : in std_logic; + UART_TX_0 : out std_logic; + UART_RX_1 : in std_logic; + UART_TX_1 : out std_logic; + + -- SDRAM signals + SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz + SDRAM_CKE : out std_logic; -- clock enable. + SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus + SDRAM_ADDR : out std_logic_vector(11 downto 0); -- 13 bit multiplexed address bus + SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks + SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks + SDRAM_CS : out std_logic; -- a single chip select + SDRAM_WE : out std_logic; -- write enable + SDRAM_RAS : out std_logic; -- row address select + SDRAM_CAS : out std_logic -- columns address select + ); +END entity; + +architecture rtl of CYC1000_zpu is + + signal reset : std_logic; + signal sysclk : std_logic; + signal memclk : std_logic; + signal pll_locked : std_logic; + + --signal ps2m_clk_in : std_logic; + --signal ps2m_clk_out : std_logic; + --signal ps2m_dat_in : std_logic; + --signal ps2m_dat_out : std_logic; + + --signal ps2k_clk_in : std_logic; + --signal ps2k_clk_out : std_logic; + --signal ps2k_dat_in : std_logic; + --signal ps2k_dat_out : std_logic; + + --alias PS2_MDAT : std_logic is GPIO_1(19); + --alias PS2_MCLK : std_logic is GPIO_1(18); + +begin + +--I2C_SDAT <= 'Z'; +--GPIO_0(33 downto 2) <= (others => 'Z'); +--GPIO_1 <= (others => 'Z'); +--LED <= "101010" & reset & UART_RX_0; +LED <= "00000000"; + +mypll : entity work.Clock_12to100 +port map +( + inclk0 => CLOCK_12M, + c0 => sysclk, + c1 => memclk, + locked => pll_locked +); + +--reset<=(not SW(0) xor KEY(0)) and pll_locked; +reset<=(not USER_BTN) and pll_locked; + +myVirtualToplevel : entity work.zpu_soc +generic map +( + SYSCLK_FREQUENCY => SYSCLK_CYC1000_FREQ +) +port map +( + SYSCLK => sysclk, + MEMCLK => memclk, + RESET_IN => reset, + + -- RS232 + UART_RX_0 => UART_RX_0, + UART_TX_0 => UART_TX_0, + UART_RX_1 => UART_RX_1, + UART_TX_1 => UART_TX_1, + + -- SPI signals + SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in. + SPI_MOSI => open, + SPI_CLK => open, + SPI_CS => open, + + -- SD Card (SPI) signals + SDCARD_MISO => SDCARD_MISO, + SDCARD_MOSI => SDCARD_MOSI, + SDCARD_CLK => SDCARD_CLK, + SDCARD_CS => SDCARD_CS, + + -- PS/2 signals + PS2K_CLK_IN => '1', + PS2K_DAT_IN => '1', + PS2K_CLK_OUT => open, + PS2K_DAT_OUT => open, + PS2M_CLK_IN => '1', + PS2M_DAT_IN => '1', + PS2M_CLK_OUT => open, + PS2M_DAT_OUT => open, + + -- I²C signals + I2C_SCL_IO => open, + I2C_SDA_IO => open, + + -- IOCTL Bus -- + IOCTL_DOWNLOAD => open, -- Downloading to FPGA. + IOCTL_UPLOAD => open, -- Uploading from FPGA. + IOCTL_CLK => open, -- I/O Clock. + IOCTL_WR => open, -- Write Enable to FPGA. + IOCTL_RD => open, -- Read Enable from FPGA. + IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus. + IOCTL_SELECT => open, -- Enable IOP control over ioctl bus. + IOCTL_ADDR => open, -- Address in FPGA to write into. + IOCTL_DOUT => open, -- Data to be written into FPGA. + IOCTL_DIN => (others => '0'), -- Data to be read into HPS. + + -- SDRAM signals + SDRAM_CLK => SDRAM_CLK, -- sdram is accessed at 128MHz + SDRAM_CKE => SDRAM_CKE, -- clock enable. + SDRAM_DQ => SDRAM_DQ, -- 16 bit bidirectional data bus + SDRAM_ADDR => SDRAM_ADDR, -- 13 bit multiplexed address bus + SDRAM_DQM => SDRAM_DQM, -- two byte masks + SDRAM_BA => SDRAM_BA, -- two banks + SDRAM_CS_n => SDRAM_CS, -- a single chip select + SDRAM_WE_n => SDRAM_WE, -- write enable + SDRAM_RAS_n => SDRAM_RAS, -- row address select + SDRAM_CAS_n => SDRAM_CAS, -- columns address select + SDRAM_READY => open -- sd ready. + + -- DDR2 DRAM - doesnt exist on the QMV. + --DDR2_ADDR => open, -- 14 bit multiplexed address bus + --DDR2_DQ => open, -- 64 bit bidirectional data bus + --DDR2_DQS => open, -- 8 bit bidirectional data bus + --DDR2_DQM => open, -- eight byte masks + --DDR2_ODT => open, -- 14 bit multiplexed address bus + --DDR2_BA => open, -- 8 banks + --DDR2_CS => open, -- 2 chip selects. + --DDR2_WE => open, -- write enable + --DDR2_RAS => open, -- row address select + --DDR2_CAS => open, -- columns address select + --DDR2_CKE => open, -- 2 clock enable. + --DDR2_CLK => open -- 2 clocks. +); + + +end architecture; diff --git a/zpu/build/CYC1000_zpu_constraints.sdc b/zpu/build/CYC1000_zpu_constraints.sdc new file mode 100644 index 0000000..8d178e5 --- /dev/null +++ b/zpu/build/CYC1000_zpu_constraints.sdc @@ -0,0 +1,135 @@ +## Generated SDC file "E115_zpu.out.sdc" + +## Copyright (C) 2017 Intel Corporation. All rights reserved. +## Your use of Intel Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Intel Program License +## Subscription Agreement, the Intel Quartus Prime License Agreement, +## the Intel FPGA IP License Agreement, or other applicable license +## agreement, including, without limitation, that your use is for +## the sole purpose of programming logic devices manufactured by +## Intel and sold by Intel or its authorized distributors. Please +## refer to the applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus Prime" +## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition" + +## DATE "Sat Jun 22 23:32:00 2019" + +## +## DEVICE "EP4CE115F23I7" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clk_12} -period 83.333 -waveform { 0.000 0.500 } [get_ports {CLOCK_12M}] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + +create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 25 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk0}] +#create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 50 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk1}] + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +derive_clock_uncertainty +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020 +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020 + + +#************************************************************** +# Set Input Delay +#************************************************************** + +# Delays for async signals - not necessary, but might as well avoid +# having unconstrained ports in the design +#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}] +#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}] + + +#************************************************************** +# Set Output Delay +#************************************************************** + +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[0]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[1]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[2]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[3]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[4]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[5]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[6]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[7]}] + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + +set_false_path -from [get_keepers {USER_BTN*}] +#set_false_path -from [get_keepers {SW*}] +#set_false_path -from [get_cells {myVirtualToplevel|RESET_n}] + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -setup -start 1 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -hold -start 0 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 2 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/zpu/build/Clock_12to100.cmp b/zpu/build/Clock_12to100.cmp new file mode 100644 index 0000000..e521c90 --- /dev/null +++ b/zpu/build/Clock_12to100.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component Clock_12to100 + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; diff --git a/zpu/build/Clock_12to100.ppf b/zpu/build/Clock_12to100.ppf new file mode 100644 index 0000000..67075b3 --- /dev/null +++ b/zpu/build/Clock_12to100.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/zpu/build/Clock_12to100.qip b/zpu/build/Clock_12to100.qip new file mode 100644 index 0000000..a0e38e1 --- /dev/null +++ b/zpu/build/Clock_12to100.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_12to100.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_12to100.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_12to100.ppf"] diff --git a/zpu/build/Clock_12to100.vhd b/zpu/build/Clock_12to100.vhd new file mode 100644 index 0000000..4f71e80 --- /dev/null +++ b/zpu/build/Clock_12to100.vhd @@ -0,0 +1,397 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: Clock_12to100.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY Clock_12to100 IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END Clock_12to100; + + +ARCHITECTURE SYN OF clock_12to100 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + gate_lock_signal : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + invalid_lock_multiplier : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + valid_lock_multiplier : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire6_bv(0 DOWNTO 0) <= "0"; + sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + sub_wire4 <= inclk0; + sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + clk0_divide_by => 3, + clk0_duty_cycle => 50, + clk0_multiply_by => 25, + clk0_phase_shift => "0", + clk1_divide_by => 3, + clk1_duty_cycle => 50, + clk1_multiply_by => 50, + clk1_phase_shift => "0", + compensate_clock => "CLK0", + gate_lock_signal => "NO", + inclk0_input_frequency => 83333, + intended_device_family => "Cyclone II", + invalid_lock_multiplier => 5, + lpm_hint => "CBX_MODULE_PREFIX=Clock_12to100", + lpm_type => "altpll", + operation_mode => "NORMAL", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + valid_lock_multiplier => 1 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire5, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_12to100.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/zpu/build/Clock_25to100.cmp b/zpu/build/Clock_25to100.cmp new file mode 100644 index 0000000..09224bc --- /dev/null +++ b/zpu/build/Clock_25to100.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component Clock_25to100 + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; diff --git a/zpu/build/Clock_25to100.ppf b/zpu/build/Clock_25to100.ppf new file mode 100644 index 0000000..feedea5 --- /dev/null +++ b/zpu/build/Clock_25to100.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/zpu/build/Clock_25to100.qip b/zpu/build/Clock_25to100.qip new file mode 100644 index 0000000..b000805 --- /dev/null +++ b/zpu/build/Clock_25to100.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_25to100.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_25to100.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_25to100.ppf"] diff --git a/zpu/build/Clock_25to100.vhd b/zpu/build/Clock_25to100.vhd new file mode 100644 index 0000000..57699d6 --- /dev/null +++ b/zpu/build/Clock_25to100.vhd @@ -0,0 +1,397 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: Clock_25to100.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY Clock_25to100 IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END Clock_25to100; + + +ARCHITECTURE SYN OF clock_25to100 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + gate_lock_signal : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + invalid_lock_multiplier : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + valid_lock_multiplier : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire6_bv(0 DOWNTO 0) <= "0"; + sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + sub_wire4 <= inclk0; + sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 4, + clk0_phase_shift => "0", + clk1_divide_by => 1, + clk1_duty_cycle => 50, + clk1_multiply_by => 8, + clk1_phase_shift => "0", + compensate_clock => "CLK0", + gate_lock_signal => "NO", + inclk0_input_frequency => 40000, + intended_device_family => "Cyclone II", + invalid_lock_multiplier => 5, + lpm_hint => "CBX_MODULE_PREFIX=Clock_25to100", + lpm_type => "altpll", + operation_mode => "NORMAL", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + valid_lock_multiplier => 1 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire5, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_25to100.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/zpu/build/Clock_50to100.cmp b/zpu/build/Clock_50to100.cmp new file mode 100644 index 0000000..59524f7 --- /dev/null +++ b/zpu/build/Clock_50to100.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component Clock_50to100 + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; diff --git a/zpu/build/Clock_50to100.cnx b/zpu/build/Clock_50to100.cnx new file mode 100644 index 0000000..ff7e2b0 --- /dev/null +++ b/zpu/build/Clock_50to100.cnx @@ -0,0 +1,209 @@ +VERSION: WM1.0 +MODULE: altpll +PRIVATE: ACTIVECLK_CHECK STRING "0" +PRIVATE: BANDWIDTH STRING "1.000" +PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +PRIVATE: BANDWIDTH_PRESET STRING "Low" +PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +PRIVATE: CLKLOSS_CHECK STRING "0" +PRIVATE: CLKSWITCH_CHECK STRING "1" +PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +PRIVATE: CREATE_INCLK1_CHECK STRING "0" +PRIVATE: CUR_DEDICATED_CLK STRING "c0" +PRIVATE: CUR_FBIN_CLK STRING "c0" +PRIVATE: DEVICE_SPEED_GRADE STRING "7" +PRIVATE: DIV_FACTOR0 NUMERIC "1" +PRIVATE: DIV_FACTOR1 NUMERIC "1" +PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" +PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" +PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +PRIVATE: GLOCKED_MODE_CHECK STRING "0" +PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +PRIVATE: LONG_SCAN_RADIO STRING "1" +PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +PRIVATE: MIRROR_CLK0 STRING "0" +PRIVATE: MIRROR_CLK1 STRING "0" +PRIVATE: MULT_FACTOR0 NUMERIC "1" +PRIVATE: MULT_FACTOR1 NUMERIC "1" +PRIVATE: NORMAL_MODE_RADIO STRING "1" +PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +PRIVATE: PHASE_SHIFT0 STRING "-2.00000000" +PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns" +PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +PRIVATE: PLL_ARESET_CHECK STRING "1" +PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +PRIVATE: PLL_ENA_CHECK STRING "0" +PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +PRIVATE: PLL_PFDENA_CHECK STRING "0" +PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +PRIVATE: RECONFIG_FILE STRING "Clock_50to100.mif" +PRIVATE: SACN_INPUTS_CHECK STRING "0" +PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +PRIVATE: SHORT_SCAN_RADIO STRING "0" +PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +PRIVATE: SPREAD_FREQ STRING "50.000" +PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +PRIVATE: SPREAD_PERCENT STRING "0.500" +PRIVATE: SPREAD_USE STRING "0" +PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +PRIVATE: STICKY_CLK0 STRING "1" +PRIVATE: STICKY_CLK1 STRING "1" +PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +PRIVATE: USE_CLK0 STRING "1" +PRIVATE: USE_CLK1 STRING "1" +PRIVATE: USE_CLKENA0 STRING "0" +PRIVATE: USE_CLKENA1 STRING "0" +PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +PRIVATE: ZERO_DELAY_RADIO STRING "0" +LIBRARY: altera_mf altera_mf.altera_mf_components.all +CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +CONSTANT: CLK0_PHASE_SHIFT STRING "-2000" +CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +CONSTANT: CLK1_PHASE_SHIFT STRING "0" +CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +CONSTANT: LPM_TYPE STRING "altpll" +CONSTANT: OPERATION_MODE STRING "NORMAL" +CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +CONSTANT: PORT_ARESET STRING "PORT_USED" +CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +CONSTANT: PORT_INCLK0 STRING "PORT_USED" +CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +CONSTANT: PORT_LOCKED STRING "PORT_USED" +CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +CONSTANT: PORT_clk0 STRING "PORT_USED" +CONSTANT: PORT_clk1 STRING "PORT_USED" +CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +USED_PORT: areset 0 0 0 0 INPUT GND "areset" +USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE +GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE +GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE +GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE +GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE +GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE +LIB_FILE: altera_mf + +LICENSE_ID: "DEVICE_FAMILY_Cyclone 10 LP" 10915102B3011615119A +LICENSE_ID: "DEVICE_FAMILY_Cyclone IV E" 10915102A3011615119A +LICENSE_ID: "DEVICE_FAMILY_Cyclone V" 10915102T3011615119M +LICENSE_ID: "DEVICE_FAMILY_MAX V" 10915102H3011615119A +LICENSE_ID: "DEVICE_FAMILY_Arria II GX" 10915102P3011615119S +LICENSE_ID: "DEVICE_FAMILY_Cyclone IV GX" 10915102B3011615119A +LICENSE_ID: "DEVICE_FAMILY_MAX II" 10915102N3011615119S +LICENSE_ID: "DEVICE_FAMILY_MAX 10" 10915102N3011615119S +LICENSE_ID: "FEATURE_STRATIXGX_DPA" 10915102V3011615119C +LICENSE_ID: "FEATURE_STRATIXGX_BASIC" 10915102T3011615119M + + +SUPPORTED_DEVICE_FAMILY: "Cyclone 10 LP" +SUPPORTED_DEVICE_FAMILY: "Cyclone IV E" +SUPPORTED_DEVICE_FAMILY: "Arria II GX" +SUPPORTED_DEVICE_FAMILY: "Cyclone IV GX" +SUPPORTED_DEVICE_FAMILY: "MAX 10" +SUPPORTED_DEVICE_FAMILY: "Cyclone II" + +WIZARD_TITLE: "ALTPLL" +QUARTUS_VERSION: "Version 17.0" +QUARTUS_SVERSION: "17.0.2 Build 602 07/19/2017 SJ Lite Edition:07/19/2017" +QUARTUS_BUILD_DATE: "07/19/2017" +ALTERA_COPYRIGHT: "Copyright (C) 2017 Intel Corporation. All rights reserved." + + +HELP_MENU_ITEM: FALSE "IUG$altpll Megafunction User Guide$http://www.altera.com/literature/ug/ug_altpll.pdf" +HELP_MENU_ITEM: FALSE "IUG$General-Purpose PLLs in Stratix (GX) Devices$http://www.altera.com/literature/hb/stx/ch_1_vol_2.pdf" +HELP_MENU_ITEM: FALSE "IUG$PLLs in Stratix II Devices$http://www.altera.com/literature/hb/stx2/stx2_sii52001.pdf" +HELP_MENU_ITEM: FALSE "IUG$Clock Networks and PLLs in Stratix III Devices$http://www.altera.com/literature/hb/stx3/stx3_siii51006.pdf " +HELP_MENU_ITEM: FALSE "IUG$PLLs in Cyclone II Devices$http://www.altera.com/literature/hb/cyc2/cyc2_cii51007.pdf" diff --git a/zpu/build/Clock_50to100.cnxerr b/zpu/build/Clock_50to100.cnxerr new file mode 100644 index 0000000..7b911a9 --- /dev/null +++ b/zpu/build/Clock_50to100.cnxerr @@ -0,0 +1,7 @@ +******************************************* +** CNX File Error Log ** +******************************************* + +Line 0: WM1.0 + No valid wizard signature (generation mode ) found + diff --git a/zpu/build/Clock_50to100.ppf b/zpu/build/Clock_50to100.ppf new file mode 100644 index 0000000..ef75910 --- /dev/null +++ b/zpu/build/Clock_50to100.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/zpu/build/Clock_50to100.qip b/zpu/build/Clock_50to100.qip new file mode 100644 index 0000000..9ddc113 --- /dev/null +++ b/zpu/build/Clock_50to100.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_50to100.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_50to100.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_50to100.ppf"] diff --git a/zpu/build/Clock_50to100.vhd b/zpu/build/Clock_50to100.vhd new file mode 100644 index 0000000..70e444d --- /dev/null +++ b/zpu/build/Clock_50to100.vhd @@ -0,0 +1,399 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: Clock_50to100.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY Clock_50to100 IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END Clock_50to100; + + +ARCHITECTURE SYN OF clock_50to100 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + gate_lock_signal : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + invalid_lock_multiplier : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + valid_lock_multiplier : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire6_bv(0 DOWNTO 0) <= "0"; + sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + sub_wire4 <= inclk0; + sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 1, + clk1_duty_cycle => 50, + clk1_multiply_by => 2, + clk1_phase_shift => "-2500 ps", + compensate_clock => "CLK0", + gate_lock_signal => "NO", + inclk0_input_frequency => 20000, + intended_device_family => "Cyclone V", + invalid_lock_multiplier => 5, + lpm_hint => "CBX_MODULE_PREFIX=Clock_50to100", + lpm_type => "altpll", + operation_mode => "NORMAL", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + valid_lock_multiplier => 1 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire5, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_50to100.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/zpu/build/DE0_nano_zpu.qpf b/zpu/build/DE0_nano_zpu.qpf new file mode 100644 index 0000000..187422d --- /dev/null +++ b/zpu/build/DE0_nano_zpu.qpf @@ -0,0 +1,6 @@ +DATE = "14:58:03 December 18, 2014" +QUARTUS_VERSION = "14.0" + +# Revisions + +PROJECT_REVISION = "DE0_nano_zpu" diff --git a/zpu/build/DE0_nano_zpu.qsf b/zpu/build/DE0_nano_zpu.qsf new file mode 100644 index 0000000..6297314 --- /dev/null +++ b/zpu/build/DE0_nano_zpu.qsf @@ -0,0 +1,476 @@ +#============================================================ +# Build by Terasic System Builder +#============================================================ + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA4U23C6 +set_global_assignment -name TOP_LEVEL_ENTITY "DE0_nano_zpu" +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0 +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:58:03 DECEMBER 18,2014" +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 + + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_U9 -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + +#============================================================ +# ARDUINO +#============================================================ +set_location_assignment PIN_AG13 -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_location_assignment PIN_AF13 -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_location_assignment PIN_AG10 -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_location_assignment PIN_AG9 -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_location_assignment PIN_U14 -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_location_assignment PIN_U13 -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_location_assignment PIN_AG8 -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_location_assignment PIN_AH8 -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_location_assignment PIN_AF17 -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_location_assignment PIN_AE15 -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_location_assignment PIN_AF15 -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_location_assignment PIN_AG16 -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_location_assignment PIN_AH11 -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_location_assignment PIN_AH12 -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_location_assignment PIN_AH9 -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_location_assignment PIN_AG11 -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_location_assignment PIN_AH7 -to ARDUINO_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N + +#============================================================ +# CLOCK +#============================================================ +#set_location_assignment PIN_V11 -to FPGA_CLK1_50 +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 + +#set_location_assignment PIN_R8 -to CLOCK_50 +set_location_assignment PIN_V11 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 + +#============================================================ +# HPS +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_AH17 -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_W15 -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_L10 -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_location_assignment PIN_L9 -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_location_assignment PIN_H6 -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_location_assignment PIN_H5 -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] + +#============================================================ +# GPIO_0, GPIO connect to GPIO Default +#============================================================ +set_location_assignment PIN_V12 -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +set_location_assignment PIN_AF7 -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +set_location_assignment PIN_W12 -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +set_location_assignment PIN_AF8 -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +set_location_assignment PIN_Y8 -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +set_location_assignment PIN_AB4 -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +set_location_assignment PIN_W8 -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +set_location_assignment PIN_Y4 -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +set_location_assignment PIN_Y5 -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +set_location_assignment PIN_U11 -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +set_location_assignment PIN_T8 -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +set_location_assignment PIN_T12 -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +set_location_assignment PIN_AH5 -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +set_location_assignment PIN_AH6 -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +set_location_assignment PIN_AH4 -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +set_location_assignment PIN_AG5 -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +set_location_assignment PIN_AH3 -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +set_location_assignment PIN_AH2 -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +set_location_assignment PIN_AF4 -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +set_location_assignment PIN_AG6 -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +set_location_assignment PIN_AF5 -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +set_location_assignment PIN_AE4 -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +set_location_assignment PIN_T13 -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +set_location_assignment PIN_T11 -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +set_location_assignment PIN_AE7 -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +set_location_assignment PIN_AF6 -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +set_location_assignment PIN_AF9 -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +set_location_assignment PIN_AE8 -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +set_location_assignment PIN_AD10 -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +set_location_assignment PIN_AE9 -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +set_location_assignment PIN_AD11 -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +set_location_assignment PIN_AF10 -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +#set_location_assignment PIN_AD12 -to GPIO_0[32] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +#set_location_assignment PIN_AE11 -to GPIO_0[33] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] +#set_location_assignment PIN_AF11 -to GPIO_0[34] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] +#set_location_assignment PIN_AE12 -to GPIO_0[35] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] + +#============================================================ +# GPIO_1, GPIO connect to GPIO Default +#============================================================ +set_location_assignment PIN_Y15 -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +set_location_assignment PIN_AG28 -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +set_location_assignment PIN_AA15 -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +set_location_assignment PIN_AH27 -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +set_location_assignment PIN_AG26 -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +set_location_assignment PIN_AH24 -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +set_location_assignment PIN_AF23 -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +set_location_assignment PIN_AE22 -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +set_location_assignment PIN_AF21 -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +set_location_assignment PIN_AG20 -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +set_location_assignment PIN_AG19 -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +set_location_assignment PIN_AF20 -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +set_location_assignment PIN_AC23 -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +set_location_assignment PIN_AG18 -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +set_location_assignment PIN_AH26 -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +set_location_assignment PIN_AA19 -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +set_location_assignment PIN_AG24 -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +set_location_assignment PIN_AF25 -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +set_location_assignment PIN_AH23 -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +set_location_assignment PIN_AG23 -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +set_location_assignment PIN_AE19 -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +set_location_assignment PIN_AF18 -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +set_location_assignment PIN_AD19 -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +set_location_assignment PIN_AE20 -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +set_location_assignment PIN_AE24 -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +set_location_assignment PIN_AD20 -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +set_location_assignment PIN_AF22 -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +set_location_assignment PIN_AH22 -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +set_location_assignment PIN_AH19 -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +set_location_assignment PIN_AH21 -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +set_location_assignment PIN_AG21 -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +set_location_assignment PIN_AH18 -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +set_location_assignment PIN_AD23 -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +set_location_assignment PIN_AE23 -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] +set_location_assignment PIN_AA18 -to GPIO_1[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34] +set_location_assignment PIN_AC22 -to GPIO_1[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35] + + +set_location_assignment PIN_AE12 -to UART_TX_0 +set_location_assignment PIN_AE11 -to UART_RX_0 +set_location_assignment PIN_AF11 -to UART_TX_1 +set_location_assignment PIN_AD12 -to UART_RX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1 + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" + +set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ* + +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH + + +set_global_assignment -name VHDL_FILE ../DE0_nano_zpu_Toplevel.vhd +set_global_assignment -name QIP_FILE Clock_50to100.qip +set_global_assignment -name SDC_FILE DE0_nano_zpu_constraints.sdc +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd +#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd +#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/wbsdram.qip +set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/wbsdram.vhd +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" + +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/zpu/build/DE0_nano_zpu.sdc b/zpu/build/DE0_nano_zpu.sdc new file mode 100644 index 0000000..e9e1fe7 --- /dev/null +++ b/zpu/build/DE0_nano_zpu.sdc @@ -0,0 +1,92 @@ +#************************************************************** +# This .sdc file is created by Terasic Tool. +# Users are recommended to modify this file to match users logic. +#************************************************************** + +#************************************************************** +# Create Clock +#************************************************************** +create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50] +create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50] +create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50] + +# for enhancing USB BlasterII to be reliable, 25MHz +create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} +set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi] +set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms] +set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo] + +#************************************************************** +# Create Generated Clock +#************************************************************** +derive_pll_clocks + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** +derive_clock_uncertainty + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + + + +#************************************************************** +# Set Load +#************************************************************** + + + diff --git a/zpu/build/DE0_nano_zpu_Toplevel.vhd b/zpu/build/DE0_nano_zpu_Toplevel.vhd new file mode 100644 index 0000000..b127e17 --- /dev/null +++ b/zpu/build/DE0_nano_zpu_Toplevel.vhd @@ -0,0 +1,176 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.zpu_soc_pkg.all; + +entity DE0_nano_zpu is + port ( + -- Clock + CLOCK_50 : in std_logic; + -- LED + LED : out std_logic_vector(7 downto 0); + -- Debounced keys + KEY : in std_logic_vector(1 downto 0); + -- DIP switches + SW : in std_logic_vector(3 downto 0); + + TDI : out std_logic; + TCK : out std_logic; + TCS : out std_logic; + TDO : in std_logic; + -- I2C_SDAT : inout std_logic; + -- I2C_SCLK : out std_logic; + -- GPIO_0 : inout std_logic_vector(33 downto 0); + -- GPIO_1 : inout std_logic_vector(33 downto 0); + + -- SD Card 1 + SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + + -- UART Serial channels. + UART_RX_0 : in std_logic; + UART_TX_0 : out std_logic; + UART_RX_1 : in std_logic; + UART_TX_1 : out std_logic + +-- SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz +-- SDRAM_CKE : out std_logic; -- clock enable. +-- SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus +-- SDRAM_ADDR : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus +-- SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks +-- SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks +-- SDRAM_CS : out std_logic; -- a single chip select +-- SDRAM_WE : out std_logic; -- write enable +-- SDRAM_RAS : out std_logic; -- row address select +-- SDRAM_CAS : out std_logic -- columns address select + ); +END entity; + +architecture rtl of DE0_nano_zpu is + + signal reset : std_logic; + signal sysclk : std_logic; + signal memclk : std_logic; + signal pll_locked : std_logic; + + --signal ps2m_clk_in : std_logic; + --signal ps2m_clk_out : std_logic; + --signal ps2m_dat_in : std_logic; + --signal ps2m_dat_out : std_logic; + + --signal ps2k_clk_in : std_logic; + --signal ps2k_clk_out : std_logic; + --signal ps2k_dat_in : std_logic; + --signal ps2k_dat_out : std_logic; + + --alias PS2_MDAT : std_logic is GPIO_1(19); + --alias PS2_MCLK : std_logic is GPIO_1(18); + +begin + +--I2C_SDAT <= 'Z'; +--GPIO_0(33 downto 2) <= (others => 'Z'); +--GPIO_1 <= (others => 'Z'); +--LED <= "101010" & reset & UART_RX_0; +LED <= "00000000"; + +mypll : entity work.Clock_50to100 +port map +( + inclk0 => CLOCK_50, + c0 => sysclk, + c1 => memclk, + locked => pll_locked +); + +reset<=(not SW(0) xor KEY(0)) and pll_locked; + +myVirtualToplevel : entity work.zpu_soc +generic map +( + SYSCLK_FREQUENCY => SYSCLK_DE0_FREQ +) +port map +( + SYSCLK => sysclk, + MEMCLK => memclk, + RESET_IN => reset, + + -- RS232 + UART_RX_0 => UART_RX_0, + UART_TX_0 => UART_TX_0, + UART_RX_1 => UART_RX_1, + UART_TX_1 => UART_TX_1, + + -- SPI signals + SPI_MISO => TDO, -- Allow the SPI interface not to be plumbed in. + SPI_MOSI => TDI, + SPI_CLK => TCK, + SPI_CS => TCS, + + -- SD Card (SPI) signals + SDCARD_MISO => SDCARD_MISO, + SDCARD_MOSI => SDCARD_MOSI, + SDCARD_CLK => SDCARD_CLK, + SDCARD_CS => SDCARD_CS, + + + -- PS/2 signals + PS2K_CLK_IN => '1', + PS2K_DAT_IN => '1', + PS2K_CLK_OUT => open, + PS2K_DAT_OUT => open, + PS2M_CLK_IN => '1', + PS2M_DAT_IN => '1', + PS2M_CLK_OUT => open, + PS2M_DAT_OUT => open, + + -- I²C signals + I2C_SCL_IO => open, + I2C_SDA_IO => open, + + + -- IOCTL Bus -- + IOCTL_DOWNLOAD => open, -- Downloading to FPGA. + IOCTL_UPLOAD => open, -- Uploading from FPGA. + IOCTL_CLK => open, -- I/O Clock. + IOCTL_WR => open, -- Write Enable to FPGA. + IOCTL_RD => open, -- Read Enable from FPGA. + IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus. + IOCTL_SELECT => open, -- Enable IOP control over ioctl bus. + IOCTL_ADDR => open, -- Address in FPGA to write into. + IOCTL_DOUT => open, -- Data to be written into FPGA. + IOCTL_DIN => (others => '0'), -- Data to be read into HPS. + + -- SDRAM signals + SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz + SDRAM_CKE => open, --SDRAM_CKE, -- clock enable. + SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus + SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus + SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks + SDRAM_BA => open, --SDRAM_BA, -- two banks + SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select + SDRAM_WE_n => open, --SDRAM_WE, -- write enable + SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select + SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select + SDRAM_READY => open + + -- DDR2 DRAM - doesnt exist on the QMV. + --DDR2_ADDR => open, -- 14 bit multiplexed address bus + --DDR2_DQ => open, -- 64 bit bidirectional data bus + --DDR2_DQS => open, -- 8 bit bidirectional data bus + --DDR2_DQM => open, -- eight byte masks + --DDR2_ODT => open, -- 14 bit multiplexed address bus + --DDR2_BA => open, -- 8 banks + --DDR2_CS => open, -- 2 chip selects. + --DDR2_WE => open, -- write enable + --DDR2_RAS => open, -- row address select + --DDR2_CAS => open, -- columns address select + --DDR2_CKE => open, -- 2 clock enable. + --DDR2_CLK => open -- 2 clocks. +); + + +end architecture; diff --git a/zpu/build/DE0_nano_zpu_constraints.sdc b/zpu/build/DE0_nano_zpu_constraints.sdc new file mode 100644 index 0000000..a46c71d --- /dev/null +++ b/zpu/build/DE0_nano_zpu_constraints.sdc @@ -0,0 +1,137 @@ +## Generated SDC file "hello_led.out.sdc" + +## Copyright (C) 1991-2011 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition" + +## DATE "Fri Jul 06 23:05:47 2012" + +## +## DEVICE "EP3C25Q240C8" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_50}] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + +create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 12 -divide_by 2 -master_clock {clk_50} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]}] +create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 3 -master_clock {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] + +#************************************************************** +# Set Clock Latency +#************************************************************** + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 +#derive_clock_uncertainty + + +#************************************************************** +# Set Input Delay +#************************************************************** + + +# Delays for async signals - not necessary, but might as well avoid +# having unconstrained ports in the design +#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}] +#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}] + +#************************************************************** +# Set Output Delay +#************************************************************** + +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[0]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[1]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[2]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[3]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[4]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[5]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[6]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[7]}] + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + +set_false_path -from [get_keepers {KEY*}] +set_false_path -from [get_keepers {SW*}] +#set_false_path -from [get_cells {myVirtualToplevel|RESET_n}] + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +#set_multicycle_path -setup -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 1 +#set_multicycle_path -hold -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 0 + +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 2 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** diff --git a/zpu/build/DE10_nano_zpu.qpf b/zpu/build/DE10_nano_zpu.qpf new file mode 100644 index 0000000..957cc5f --- /dev/null +++ b/zpu/build/DE10_nano_zpu.qpf @@ -0,0 +1,32 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 15:48:30 August 02, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "15:48:30 August 02, 2017" + +# Revisions + +PROJECT_REVISION = "DE10_nano_zpu" +PROJECT_REVISION = "DE10_nano_zpu" diff --git a/zpu/build/DE10_nano_zpu.qsf b/zpu/build/DE10_nano_zpu.qsf new file mode 100644 index 0000000..da45b46 --- /dev/null +++ b/zpu/build/DE10_nano_zpu.qsf @@ -0,0 +1,498 @@ +#============================================================ +# Build by Terasic System Builder +#============================================================ + +set_global_assignment -name DEVICE 5CSEBA6U23I7 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TOP_LEVEL_ENTITY DE10_nano_zpu +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1 +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:22:00 FEBRUARY 21,2011" +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name GENERATE_RBF_FILE ON + + +#============================================================ +# UART +#============================================================ +set_location_assignment PIN_Y15 -to UART_TX_0 +set_location_assignment PIN_AA15 -to UART_RX_0 +set_location_assignment PIN_AG28 -to UART_TX_1 +set_location_assignment PIN_AG26 -to UART_RX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1 + +#============================================================ +# SD CARD +#============================================================ +set_location_assignment PIN_AF25 -to SDCARD_MISO[0] +set_location_assignment PIN_AF27 -to SDCARD_MOSI[0] +set_location_assignment PIN_AH26 -to SDCARD_CLK[0] +set_location_assignment PIN_AF28 -to SDCARD_CS[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0] + +#============================================================ +# CLOCK +#============================================================ +#set_location_assignment PIN_R8 -to CLOCK_50 +set_location_assignment PIN_V11 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_location_assignment PIN_AH17 -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_location_assignment PIN_Y24 -to SW[0] +set_location_assignment PIN_W24 -to SW[1] +set_location_assignment PIN_W21 -to SW[2] +set_location_assignment PIN_W20 -to SW[3] + +#============================================================ +# SDIO +#============================================================ +#set_location_assignment PIN_AF25 -to SDIO_DAT[0] +#set_location_assignment PIN_AF23 -to SDIO_DAT[1] +#set_location_assignment PIN_AD26 -to SDIO_DAT[2] +#set_location_assignment PIN_AF28 -to SDIO_DAT[3] +#set_location_assignment PIN_AF27 -to SDIO_CMD +#set_location_assignment PIN_AH26 -to SDIO_CLK +#set_location_assignment PIN_AH7 -to SDIO_CD +#set_location_assignment PIN_AF25 -to TDO +#set_location_assignment PIN_AF28 -to TCS +#set_location_assignment PIN_AF27 -to TDI +#set_location_assignment PIN_AH26 -to TCK + +#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* + +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDO +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDI +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TCK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TCS +#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TDO +#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TCS +#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TDI + +#============================================================ +# SDRAM +#============================================================ +#set_location_assignment PIN_M7 -to SDRAM_BA[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0] +#set_location_assignment PIN_M6 -to SDRAM_BA[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1] +#set_location_assignment PIN_R6 -to SDRAM_DQM[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[0] +#set_location_assignment PIN_T5 -to SDRAM_DQM[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[1] +#set_location_assignment PIN_L2 -to SDRAM_RAS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS_N +#set_location_assignment PIN_L1 -to SDRAM_CAS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS_N +#set_location_assignment PIN_L7 -to SDRAM_CKE +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE +#set_location_assignment PIN_R4 -to SDRAM_CLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK +#set_location_assignment PIN_C2 -to SDRAM_WE_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE_N +#set_location_assignment PIN_P6 -to SDRAM_CS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS_N +#set_location_assignment PIN_G2 -to SDRAM_DQ[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0] +#set_location_assignment PIN_G1 -to SDRAM_DQ[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1] +#set_location_assignment PIN_L8 -to SDRAM_DQ[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2] +#set_location_assignment PIN_K5 -to SDRAM_DQ[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3] +#set_location_assignment PIN_K2 -to SDRAM_DQ[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4] +#set_location_assignment PIN_J2 -to SDRAM_DQ[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5] +#set_location_assignment PIN_J1 -to SDRAM_DQ[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6] +#set_location_assignment PIN_R7 -to SDRAM_DQ[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7] +#set_location_assignment PIN_T4 -to SDRAM_DQ[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8] +#set_location_assignment PIN_T2 -to SDRAM_DQ[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9] +#set_location_assignment PIN_T3 -to SDRAM_DQ[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10] +#set_location_assignment PIN_R3 -to SDRAM_DQ[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11] +#set_location_assignment PIN_R5 -to SDRAM_DQ[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12] +#set_location_assignment PIN_P3 -to SDRAM_DQ[13] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13] +#set_location_assignment PIN_N3 -to SDRAM_DQ[14] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14] +#set_location_assignment PIN_K1 -to SDRAM_DQ[15] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15] +#set_location_assignment PIN_P2 -to SDRAM_ADDR[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[0] +#set_location_assignment PIN_N5 -to SDRAM_ADDR[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[1] +#set_location_assignment PIN_N6 -to SDRAM_ADDR[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[2] +#set_location_assignment PIN_M8 -to SDRAM_ADDR[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[3] +#set_location_assignment PIN_P8 -to SDRAM_ADDR[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[4] +#set_location_assignment PIN_T7 -to SDRAM_ADDR[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[5] +#set_location_assignment PIN_N8 -to SDRAM_ADDR[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[6] +#set_location_assignment PIN_T6 -to SDRAM_ADDR[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[7] +#set_location_assignment PIN_R1 -to SDRAM_ADDR[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[8] +#set_location_assignment PIN_P1 -to SDRAM_ADDR[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[9] +#set_location_assignment PIN_N2 -to SDRAM_ADDR[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[10] +#set_location_assignment PIN_N1 -to SDRAM_ADDR[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11] +#set_location_assignment PIN_L4 -to SDRAM_ADDR[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[12] + +#============================================================ +# EPCS +#============================================================ +#set_location_assignment PIN_H2 -to EPCS_DATA0 +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DATA0 +#set_location_assignment PIN_H1 -to EPCS_DCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DCLK +#set_location_assignment PIN_D2 -to EPCS_NCSO +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_NCSO +#set_location_assignment PIN_C1 -to EPCS_ASDO +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_ASDO + +#============================================================ +# Accelerometer and EEPROM +#============================================================ +#set_location_assignment PIN_F2 -to I2C_SCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +#set_location_assignment PIN_F1 -to I2C_SDAT +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT +#set_location_assignment PIN_G5 -to G_SENSOR_CS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N +#set_location_assignment PIN_M2 -to G_SENSOR_INT +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT + +#============================================================ +# ADC +#============================================================ +#set_location_assignment PIN_A10 -to ADC_CS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N +#set_location_assignment PIN_B10 -to ADC_SADDR +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR +#set_location_assignment PIN_B14 -to ADC_SCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK +#set_location_assignment PIN_A9 -to ADC_SDAT +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT + +#============================================================ +# 2x13 GPIO Header +#============================================================ +#set_location_assignment PIN_A14 -to GPIO_2[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0] +#set_location_assignment PIN_B16 -to GPIO_2[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1] +#set_location_assignment PIN_C14 -to GPIO_2[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2] +#set_location_assignment PIN_C16 -to GPIO_2[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3] +#set_location_assignment PIN_C15 -to GPIO_2[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4] +#set_location_assignment PIN_D16 -to GPIO_2[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5] +#set_location_assignment PIN_D15 -to GPIO_2[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6] +#set_location_assignment PIN_D14 -to GPIO_2[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7] +#set_location_assignment PIN_F15 -to GPIO_2[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8] +#set_location_assignment PIN_F16 -to GPIO_2[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9] +#set_location_assignment PIN_F14 -to GPIO_2[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10] +#set_location_assignment PIN_G16 -to GPIO_2[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11] +#set_location_assignment PIN_G15 -to GPIO_2[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12] +#set_location_assignment PIN_E15 -to GPIO_2_IN[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0] +#set_location_assignment PIN_E16 -to GPIO_2_IN[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1] +#set_location_assignment PIN_M16 -to GPIO_2_IN[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2] + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +#set_location_assignment PIN_A8 -to GPIO_0_IN[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0] +#set_location_assignment PIN_D3 -to GPIO_0[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +#set_location_assignment PIN_B8 -to GPIO_0_IN[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1] +#set_location_assignment PIN_C3 -to GPIO_0[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +#set_location_assignment PIN_A2 -to GPIO_0[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +#set_location_assignment PIN_A3 -to GPIO_0[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +#set_location_assignment PIN_B3 -to GPIO_0[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +#set_location_assignment PIN_B4 -to GPIO_0[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +#set_location_assignment PIN_A4 -to GPIO_0[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +#set_location_assignment PIN_B5 -to GPIO_0[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +#set_location_assignment PIN_A5 -to GPIO_0[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +#set_location_assignment PIN_D5 -to GPIO_0[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +#set_location_assignment PIN_B6 -to GPIO_0[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +#set_location_assignment PIN_A6 -to GPIO_0[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +#set_location_assignment PIN_B7 -to GPIO_0[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +#set_location_assignment PIN_D6 -to GPIO_0[13] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +#set_location_assignment PIN_A7 -to GPIO_0[14] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +#set_location_assignment PIN_C6 -to GPIO_0[15] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +#set_location_assignment PIN_C8 -to GPIO_0[16] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +#set_location_assignment PIN_E6 -to GPIO_0[17] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +#set_location_assignment PIN_E7 -to GPIO_0[18] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +#set_location_assignment PIN_D8 -to GPIO_0[19] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +#set_location_assignment PIN_E8 -to GPIO_0[20] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +#set_location_assignment PIN_F8 -to GPIO_0[21] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +#set_location_assignment PIN_F9 -to GPIO_0[22] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +#set_location_assignment PIN_E9 -to GPIO_0[23] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +#set_location_assignment PIN_C9 -to GPIO_0[24] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +#set_location_assignment PIN_D9 -to GPIO_0[25] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +#set_location_assignment PIN_E11 -to GPIO_0[26] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +#set_location_assignment PIN_E10 -to GPIO_0[27] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +#set_location_assignment PIN_C11 -to GPIO_0[28] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +#set_location_assignment PIN_B11 -to GPIO_0[29] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +#set_location_assignment PIN_A12 -to GPIO_0[30] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +#set_location_assignment PIN_D11 -to GPIO_0[31] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +#set_location_assignment PIN_D12 -to GPIO_0[32] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +#set_location_assignment PIN_B12 -to GPIO_0[33] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] + +#============================================================ +# GPIO_1, GPIO_1 connect to GPIO Default +#============================================================ +#set_location_assignment PIN_T9 -to GPIO_1_IN[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0] +#set_location_assignment PIN_F13 -to GPIO_1[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +#set_location_assignment PIN_R9 -to GPIO_1_IN[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1] +#set_location_assignment PIN_T15 -to GPIO_1[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +#set_location_assignment PIN_T14 -to GPIO_1[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +#set_location_assignment PIN_T13 -to GPIO_1[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +#set_location_assignment PIN_R13 -to GPIO_1[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +#set_location_assignment PIN_T12 -to GPIO_1[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +#set_location_assignment PIN_R12 -to GPIO_1[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +#set_location_assignment PIN_T11 -to GPIO_1[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +#set_location_assignment PIN_T10 -to GPIO_1[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +#set_location_assignment PIN_R11 -to GPIO_1[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +#set_location_assignment PIN_P11 -to GPIO_1[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +#set_location_assignment PIN_R10 -to GPIO_1[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +#set_location_assignment PIN_N12 -to GPIO_1[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +#set_location_assignment PIN_P9 -to GPIO_1[13] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +#set_location_assignment PIN_N9 -to GPIO_1[14] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +#set_location_assignment PIN_N11 -to GPIO_1[15] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +#set_location_assignment PIN_L16 -to GPIO_1[16] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +#set_location_assignment PIN_K16 -to GPIO_1[17] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +#set_location_assignment PIN_R16 -to GPIO_1[18] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +#set_location_assignment PIN_L15 -to GPIO_1[19] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +#set_location_assignment PIN_P15 -to GPIO_1[20] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +#set_location_assignment PIN_P16 -to GPIO_1[21] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +#set_location_assignment PIN_R14 -to GPIO_1[22] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +#set_location_assignment PIN_N16 -to GPIO_1[23] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +#set_location_assignment PIN_N15 -to GPIO_1[24] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +#set_location_assignment PIN_P14 -to GPIO_1[25] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +#set_location_assignment PIN_L14 -to GPIO_1[26] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +#set_location_assignment PIN_N14 -to GPIO_1[27] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +#set_location_assignment PIN_M10 -to GPIO_1[28] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +#set_location_assignment PIN_L13 -to GPIO_1[29] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +#set_location_assignment PIN_J16 -to GPIO_1[30] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +#set_location_assignment PIN_K15 -to GPIO_1[31] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +#set_location_assignment PIN_J13 -to GPIO_1[32] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +#set_location_assignment PIN_J14 -to GPIO_1[33] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQM[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CAS_N +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_RAS_N +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_WE_N + +set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ* + +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH + + +set_global_assignment -name VHDL_FILE ../DE10_nano_zpu_Toplevel.vhd +set_global_assignment -name QIP_FILE Clock_50to100.qip +set_global_assignment -name SDC_FILE DE10_nano_zpu_constraints.sdc +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd +#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip + +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/wbsdram.qip +set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/wbsdram.vhd +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" + +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/zpu/build/DE10_nano_zpu.qsf.1405 b/zpu/build/DE10_nano_zpu.qsf.1405 new file mode 100644 index 0000000..4faf2d3 --- /dev/null +++ b/zpu/build/DE10_nano_zpu.qsf.1405 @@ -0,0 +1,478 @@ +#============================================================ +# Build by Terasic System Builder +#============================================================ + +set_global_assignment -name DEVICE 5CSEBA6U23I7 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TOP_LEVEL_ENTITY DE10_nano_zpu +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1 +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:22:00 FEBRUARY 21,2011" +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name GENERATE_RBF_FILE ON + + +set_location_assignment PIN_AA13 -to UART_TX_0 +set_location_assignment PIN_AA11 -to UART_RX_0 +set_location_assignment PIN_Y11 -to UART_TX_1 +set_location_assignment PIN_AA26 -to UART_RX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1 + +#============================================================ +# CLOCK +#============================================================ +#set_location_assignment PIN_R8 -to CLOCK_50 +set_location_assignment PIN_V11 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_location_assignment PIN_AH17 -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_location_assignment PIN_Y24 -to SW[0] +set_location_assignment PIN_W24 -to SW[1] +set_location_assignment PIN_W21 -to SW[2] +set_location_assignment PIN_W20 -to SW[3] + +#============================================================ +# SDRAM +#============================================================ +#set_location_assignment PIN_M7 -to DRAM_BA[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +#set_location_assignment PIN_M6 -to DRAM_BA[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +#set_location_assignment PIN_R6 -to DRAM_DQM[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] +#set_location_assignment PIN_T5 -to DRAM_DQM[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] +#set_location_assignment PIN_L2 -to DRAM_RAS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +#set_location_assignment PIN_L1 -to DRAM_CAS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +#set_location_assignment PIN_L7 -to DRAM_CKE +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +#set_location_assignment PIN_R4 -to DRAM_CLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +#set_location_assignment PIN_C2 -to DRAM_WE_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +#set_location_assignment PIN_P6 -to DRAM_CS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +#set_location_assignment PIN_G2 -to DRAM_DQ[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +#set_location_assignment PIN_G1 -to DRAM_DQ[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +#set_location_assignment PIN_L8 -to DRAM_DQ[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +#set_location_assignment PIN_K5 -to DRAM_DQ[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +#set_location_assignment PIN_K2 -to DRAM_DQ[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +#set_location_assignment PIN_J2 -to DRAM_DQ[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +#set_location_assignment PIN_J1 -to DRAM_DQ[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +#set_location_assignment PIN_R7 -to DRAM_DQ[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +#set_location_assignment PIN_T4 -to DRAM_DQ[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +#set_location_assignment PIN_T2 -to DRAM_DQ[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +#set_location_assignment PIN_T3 -to DRAM_DQ[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +#set_location_assignment PIN_R3 -to DRAM_DQ[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +#set_location_assignment PIN_R5 -to DRAM_DQ[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +#set_location_assignment PIN_P3 -to DRAM_DQ[13] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +#set_location_assignment PIN_N3 -to DRAM_DQ[14] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +#set_location_assignment PIN_K1 -to DRAM_DQ[15] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +#set_location_assignment PIN_P2 -to DRAM_ADDR[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +#set_location_assignment PIN_N5 -to DRAM_ADDR[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +#set_location_assignment PIN_N6 -to DRAM_ADDR[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +#set_location_assignment PIN_M8 -to DRAM_ADDR[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +#set_location_assignment PIN_P8 -to DRAM_ADDR[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +#set_location_assignment PIN_T7 -to DRAM_ADDR[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +#set_location_assignment PIN_N8 -to DRAM_ADDR[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +#set_location_assignment PIN_T6 -to DRAM_ADDR[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +#set_location_assignment PIN_R1 -to DRAM_ADDR[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +#set_location_assignment PIN_P1 -to DRAM_ADDR[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +#set_location_assignment PIN_N2 -to DRAM_ADDR[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +#set_location_assignment PIN_N1 -to DRAM_ADDR[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +#set_location_assignment PIN_L4 -to DRAM_ADDR[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] + +#============================================================ +# EPCS +#============================================================ +#set_location_assignment PIN_H2 -to EPCS_DATA0 +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DATA0 +#set_location_assignment PIN_H1 -to EPCS_DCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DCLK +#set_location_assignment PIN_D2 -to EPCS_NCSO +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_NCSO +#set_location_assignment PIN_C1 -to EPCS_ASDO +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_ASDO + +#============================================================ +# Accelerometer and EEPROM +#============================================================ +#set_location_assignment PIN_F2 -to I2C_SCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +#set_location_assignment PIN_F1 -to I2C_SDAT +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT +#set_location_assignment PIN_G5 -to G_SENSOR_CS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N +#set_location_assignment PIN_M2 -to G_SENSOR_INT +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT + +#============================================================ +# ADC +#============================================================ +#set_location_assignment PIN_A10 -to ADC_CS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N +#set_location_assignment PIN_B10 -to ADC_SADDR +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR +#set_location_assignment PIN_B14 -to ADC_SCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK +#set_location_assignment PIN_A9 -to ADC_SDAT +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT + +#============================================================ +# 2x13 GPIO Header +#============================================================ +#set_location_assignment PIN_A14 -to GPIO_2[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0] +#set_location_assignment PIN_B16 -to GPIO_2[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1] +#set_location_assignment PIN_C14 -to GPIO_2[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2] +#set_location_assignment PIN_C16 -to GPIO_2[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3] +#set_location_assignment PIN_C15 -to GPIO_2[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4] +#set_location_assignment PIN_D16 -to GPIO_2[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5] +#set_location_assignment PIN_D15 -to GPIO_2[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6] +#set_location_assignment PIN_D14 -to GPIO_2[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7] +#set_location_assignment PIN_F15 -to GPIO_2[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8] +#set_location_assignment PIN_F16 -to GPIO_2[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9] +#set_location_assignment PIN_F14 -to GPIO_2[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10] +#set_location_assignment PIN_G16 -to GPIO_2[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11] +#set_location_assignment PIN_G15 -to GPIO_2[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12] +#set_location_assignment PIN_E15 -to GPIO_2_IN[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0] +#set_location_assignment PIN_E16 -to GPIO_2_IN[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1] +#set_location_assignment PIN_M16 -to GPIO_2_IN[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2] + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +#set_location_assignment PIN_A8 -to GPIO_0_IN[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0] +#set_location_assignment PIN_D3 -to GPIO_0[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +#set_location_assignment PIN_B8 -to GPIO_0_IN[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1] +#set_location_assignment PIN_C3 -to GPIO_0[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +#set_location_assignment PIN_A2 -to GPIO_0[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +#set_location_assignment PIN_A3 -to GPIO_0[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +#set_location_assignment PIN_B3 -to GPIO_0[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +#set_location_assignment PIN_B4 -to GPIO_0[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +#set_location_assignment PIN_A4 -to GPIO_0[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +#set_location_assignment PIN_B5 -to GPIO_0[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +#set_location_assignment PIN_A5 -to GPIO_0[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +#set_location_assignment PIN_D5 -to GPIO_0[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +#set_location_assignment PIN_B6 -to GPIO_0[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +#set_location_assignment PIN_A6 -to GPIO_0[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +#set_location_assignment PIN_B7 -to GPIO_0[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +#set_location_assignment PIN_D6 -to GPIO_0[13] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +#set_location_assignment PIN_A7 -to GPIO_0[14] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +#set_location_assignment PIN_C6 -to GPIO_0[15] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +#set_location_assignment PIN_C8 -to GPIO_0[16] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +#set_location_assignment PIN_E6 -to GPIO_0[17] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +#set_location_assignment PIN_E7 -to GPIO_0[18] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +#set_location_assignment PIN_D8 -to GPIO_0[19] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +#set_location_assignment PIN_E8 -to GPIO_0[20] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +#set_location_assignment PIN_F8 -to GPIO_0[21] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +#set_location_assignment PIN_F9 -to GPIO_0[22] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +#set_location_assignment PIN_E9 -to GPIO_0[23] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +#set_location_assignment PIN_C9 -to GPIO_0[24] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +#set_location_assignment PIN_D9 -to GPIO_0[25] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +#set_location_assignment PIN_E11 -to GPIO_0[26] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +#set_location_assignment PIN_E10 -to GPIO_0[27] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +#set_location_assignment PIN_C11 -to GPIO_0[28] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +#set_location_assignment PIN_B11 -to GPIO_0[29] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +#set_location_assignment PIN_A12 -to GPIO_0[30] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +#set_location_assignment PIN_D11 -to GPIO_0[31] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +#set_location_assignment PIN_D12 -to GPIO_0[32] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +#set_location_assignment PIN_B12 -to GPIO_0[33] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] + +#============================================================ +# GPIO_1, GPIO_1 connect to GPIO Default +#============================================================ +#set_location_assignment PIN_T9 -to GPIO_1_IN[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0] +#set_location_assignment PIN_F13 -to GPIO_1[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +#set_location_assignment PIN_R9 -to GPIO_1_IN[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1] +#set_location_assignment PIN_T15 -to GPIO_1[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +#set_location_assignment PIN_T14 -to GPIO_1[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +#set_location_assignment PIN_T13 -to GPIO_1[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +#set_location_assignment PIN_R13 -to GPIO_1[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +#set_location_assignment PIN_T12 -to GPIO_1[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +#set_location_assignment PIN_R12 -to GPIO_1[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +#set_location_assignment PIN_T11 -to GPIO_1[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +#set_location_assignment PIN_T10 -to GPIO_1[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +#set_location_assignment PIN_R11 -to GPIO_1[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +#set_location_assignment PIN_P11 -to GPIO_1[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +#set_location_assignment PIN_R10 -to GPIO_1[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +#set_location_assignment PIN_N12 -to GPIO_1[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +#set_location_assignment PIN_P9 -to GPIO_1[13] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +#set_location_assignment PIN_N9 -to GPIO_1[14] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +#set_location_assignment PIN_N11 -to GPIO_1[15] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +#set_location_assignment PIN_L16 -to GPIO_1[16] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +#set_location_assignment PIN_K16 -to GPIO_1[17] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +#set_location_assignment PIN_R16 -to GPIO_1[18] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +#set_location_assignment PIN_L15 -to GPIO_1[19] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +#set_location_assignment PIN_P15 -to GPIO_1[20] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +#set_location_assignment PIN_P16 -to GPIO_1[21] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +#set_location_assignment PIN_R14 -to GPIO_1[22] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +#set_location_assignment PIN_N16 -to GPIO_1[23] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +#set_location_assignment PIN_N15 -to GPIO_1[24] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +#set_location_assignment PIN_P14 -to GPIO_1[25] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +#set_location_assignment PIN_L14 -to GPIO_1[26] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +#set_location_assignment PIN_N14 -to GPIO_1[27] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +#set_location_assignment PIN_M10 -to GPIO_1[28] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +#set_location_assignment PIN_L13 -to GPIO_1[29] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +#set_location_assignment PIN_J16 -to GPIO_1[30] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +#set_location_assignment PIN_K15 -to GPIO_1[31] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +#set_location_assignment PIN_J13 -to GPIO_1[32] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +#set_location_assignment PIN_J14 -to GPIO_1[33] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQM[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CAS_N +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_RAS_N +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_WE_N + +set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ* + +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH + + +set_global_assignment -name VHDL_FILE ../DE10_nano_zpu_Toplevel.vhd +set_global_assignment -name QIP_FILE Clock_50to100.qip +#set_global_assignment -name SDC_FILE DE10_nano_zpu_constraints.sdc +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd +#set_global_assignment -name VHDL_FILE ../cpu/zpu_flex_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd +#set_global_assignment -name VHDL_FILE ../cpu/zpu_small_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_cacheL2.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd +#set_global_assignment -name VHDL_FILE ../cpu/zpu_medium_pkg.vhd +#set_global_assignment -name VHDL_FILE ../trace/trace.vhd +#set_global_assignment -name VHDL_FILE ../trace/txt_util.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc.vhd +set_global_assignment -name VHDL_FILE ../devices/RAM/dpram.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/uart_brgen.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/uart_mv_filter.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/uart_rx.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/uart_tx.vhd +set_global_assignment -name VHDL_FILE ../devices/uart/uart.vhd +set_global_assignment -name VHDL_FILE ../devices/uart/uart_debug.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/simple_uart.vhd +#set_global_assignment -name VHDL_FILE ../devices/fifo/fifo.vhd +set_global_assignment -name VHDL_FILE ../devices/intr/interrupt_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/spi/spi.vhd +set_global_assignment -name VHDL_FILE ../devices/ps2/io_ps2_com.vhd +set_global_assignment -name VHDL_FILE ../devices/timer/timer_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/BootROM.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_0.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_1.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_2.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_3.vhd +set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_0.vhd +set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_1.vhd +set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_2.vhd +set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_3.vhd +set_global_assignment -name VHDL_FILE ../devices/ioctl/ioctl.vhd +set_global_assignment -name VHDL_FILE ../devices/RAM/dualport_ram.vhd +set_global_assignment -name VHDL_FILE ../../em/common/config_pkg.vhd +#set_global_assignment -name VERILOG_FILE ../cpu/qdiv.v +#set_global_assignment -name VHDL_FILE ../devices/Peripherals/simple_uart.vhd +#set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM.vhd +#set_global_assignment -name VHDL_FILE ../devices/RAM/DualPortRAM.vhd +#set_global_assignment -name VERILOG_FILE ../devices/RAM/TwoWayCache.v +#set_global_assignment -name VHDL_FILE ../devices/RAM/sdram_cached.vhd +#set_global_assignment -name VHDL_FILE ../Toplevel_Config.vhd +#set_global_assignment -name VHDL_FILE ../DMACache_config.vhd +#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_master.vhd +#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_dither.vhd +#set_global_assignment -name VHDL_FILE ../devices/Video/vga_controller.vhd +#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache.vhd +#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache_pkg.vhd +#set_global_assignment -name VHDL_FILE ../devices/DMA/FIFO_Counter.vhd +#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACacheRAM.vhd + + + + + + + + + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/zpu/build/DE10_nano_zpu.qsf.2406 b/zpu/build/DE10_nano_zpu.qsf.2406 new file mode 100644 index 0000000..7781cd3 --- /dev/null +++ b/zpu/build/DE10_nano_zpu.qsf.2406 @@ -0,0 +1,486 @@ +#============================================================ +# Build by Terasic System Builder +#============================================================ + +set_global_assignment -name DEVICE 5CSEBA6U23I7 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TOP_LEVEL_ENTITY DE10_nano_zpu +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1 +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:22:00 FEBRUARY 21,2011" +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name GENERATE_RBF_FILE ON + + +#set_location_assignment PIN_AA13 -to UART_TX_0 +#set_location_assignment PIN_AA11 -to UART_RX_0 +#set_location_assignment PIN_Y11 -to UART_TX_1 +#set_location_assignment PIN_AA26 -to UART_RX_1 +set_location_assignment PIN_Y15 -to UART_TX_0 +set_location_assignment PIN_AA15 -to UART_RX_0 +set_location_assignment PIN_AG28 -to UART_TX_1 +set_location_assignment PIN_AG26 -to UART_RX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1 + +#============================================================ +# CLOCK +#============================================================ +#set_location_assignment PIN_R8 -to CLOCK_50 +set_location_assignment PIN_V11 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_location_assignment PIN_AH17 -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_location_assignment PIN_Y24 -to SW[0] +set_location_assignment PIN_W24 -to SW[1] +set_location_assignment PIN_W21 -to SW[2] +set_location_assignment PIN_W20 -to SW[3] + +#============================================================ +# SDRAM +#============================================================ +#set_location_assignment PIN_M7 -to DRAM_BA[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +#set_location_assignment PIN_M6 -to DRAM_BA[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +#set_location_assignment PIN_R6 -to DRAM_DQM[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] +#set_location_assignment PIN_T5 -to DRAM_DQM[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] +#set_location_assignment PIN_L2 -to DRAM_RAS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +#set_location_assignment PIN_L1 -to DRAM_CAS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +#set_location_assignment PIN_L7 -to DRAM_CKE +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +#set_location_assignment PIN_R4 -to DRAM_CLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +#set_location_assignment PIN_C2 -to DRAM_WE_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +#set_location_assignment PIN_P6 -to DRAM_CS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +#set_location_assignment PIN_G2 -to DRAM_DQ[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +#set_location_assignment PIN_G1 -to DRAM_DQ[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +#set_location_assignment PIN_L8 -to DRAM_DQ[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +#set_location_assignment PIN_K5 -to DRAM_DQ[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +#set_location_assignment PIN_K2 -to DRAM_DQ[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +#set_location_assignment PIN_J2 -to DRAM_DQ[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +#set_location_assignment PIN_J1 -to DRAM_DQ[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +#set_location_assignment PIN_R7 -to DRAM_DQ[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +#set_location_assignment PIN_T4 -to DRAM_DQ[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +#set_location_assignment PIN_T2 -to DRAM_DQ[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +#set_location_assignment PIN_T3 -to DRAM_DQ[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +#set_location_assignment PIN_R3 -to DRAM_DQ[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +#set_location_assignment PIN_R5 -to DRAM_DQ[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +#set_location_assignment PIN_P3 -to DRAM_DQ[13] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +#set_location_assignment PIN_N3 -to DRAM_DQ[14] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +#set_location_assignment PIN_K1 -to DRAM_DQ[15] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +#set_location_assignment PIN_P2 -to DRAM_ADDR[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +#set_location_assignment PIN_N5 -to DRAM_ADDR[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +#set_location_assignment PIN_N6 -to DRAM_ADDR[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +#set_location_assignment PIN_M8 -to DRAM_ADDR[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +#set_location_assignment PIN_P8 -to DRAM_ADDR[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +#set_location_assignment PIN_T7 -to DRAM_ADDR[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +#set_location_assignment PIN_N8 -to DRAM_ADDR[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +#set_location_assignment PIN_T6 -to DRAM_ADDR[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +#set_location_assignment PIN_R1 -to DRAM_ADDR[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +#set_location_assignment PIN_P1 -to DRAM_ADDR[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +#set_location_assignment PIN_N2 -to DRAM_ADDR[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +#set_location_assignment PIN_N1 -to DRAM_ADDR[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +#set_location_assignment PIN_L4 -to DRAM_ADDR[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] + +#============================================================ +# EPCS +#============================================================ +#set_location_assignment PIN_H2 -to EPCS_DATA0 +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DATA0 +#set_location_assignment PIN_H1 -to EPCS_DCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DCLK +#set_location_assignment PIN_D2 -to EPCS_NCSO +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_NCSO +#set_location_assignment PIN_C1 -to EPCS_ASDO +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_ASDO + +#============================================================ +# Accelerometer and EEPROM +#============================================================ +#set_location_assignment PIN_F2 -to I2C_SCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +#set_location_assignment PIN_F1 -to I2C_SDAT +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT +#set_location_assignment PIN_G5 -to G_SENSOR_CS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N +#set_location_assignment PIN_M2 -to G_SENSOR_INT +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT + +#============================================================ +# ADC +#============================================================ +#set_location_assignment PIN_A10 -to ADC_CS_N +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N +#set_location_assignment PIN_B10 -to ADC_SADDR +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR +#set_location_assignment PIN_B14 -to ADC_SCLK +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK +#set_location_assignment PIN_A9 -to ADC_SDAT +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT + +#============================================================ +# 2x13 GPIO Header +#============================================================ +#set_location_assignment PIN_A14 -to GPIO_2[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0] +#set_location_assignment PIN_B16 -to GPIO_2[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1] +#set_location_assignment PIN_C14 -to GPIO_2[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2] +#set_location_assignment PIN_C16 -to GPIO_2[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3] +#set_location_assignment PIN_C15 -to GPIO_2[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4] +#set_location_assignment PIN_D16 -to GPIO_2[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5] +#set_location_assignment PIN_D15 -to GPIO_2[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6] +#set_location_assignment PIN_D14 -to GPIO_2[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7] +#set_location_assignment PIN_F15 -to GPIO_2[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8] +#set_location_assignment PIN_F16 -to GPIO_2[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9] +#set_location_assignment PIN_F14 -to GPIO_2[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10] +#set_location_assignment PIN_G16 -to GPIO_2[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11] +#set_location_assignment PIN_G15 -to GPIO_2[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12] +#set_location_assignment PIN_E15 -to GPIO_2_IN[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0] +#set_location_assignment PIN_E16 -to GPIO_2_IN[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1] +#set_location_assignment PIN_M16 -to GPIO_2_IN[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2] + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +#set_location_assignment PIN_A8 -to GPIO_0_IN[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0] +#set_location_assignment PIN_D3 -to GPIO_0[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +#set_location_assignment PIN_B8 -to GPIO_0_IN[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1] +#set_location_assignment PIN_C3 -to GPIO_0[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +#set_location_assignment PIN_A2 -to GPIO_0[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +#set_location_assignment PIN_A3 -to GPIO_0[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +#set_location_assignment PIN_B3 -to GPIO_0[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +#set_location_assignment PIN_B4 -to GPIO_0[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +#set_location_assignment PIN_A4 -to GPIO_0[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +#set_location_assignment PIN_B5 -to GPIO_0[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +#set_location_assignment PIN_A5 -to GPIO_0[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +#set_location_assignment PIN_D5 -to GPIO_0[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +#set_location_assignment PIN_B6 -to GPIO_0[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +#set_location_assignment PIN_A6 -to GPIO_0[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +#set_location_assignment PIN_B7 -to GPIO_0[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +#set_location_assignment PIN_D6 -to GPIO_0[13] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +#set_location_assignment PIN_A7 -to GPIO_0[14] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +#set_location_assignment PIN_C6 -to GPIO_0[15] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +#set_location_assignment PIN_C8 -to GPIO_0[16] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +#set_location_assignment PIN_E6 -to GPIO_0[17] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +#set_location_assignment PIN_E7 -to GPIO_0[18] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +#set_location_assignment PIN_D8 -to GPIO_0[19] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +#set_location_assignment PIN_E8 -to GPIO_0[20] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +#set_location_assignment PIN_F8 -to GPIO_0[21] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +#set_location_assignment PIN_F9 -to GPIO_0[22] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +#set_location_assignment PIN_E9 -to GPIO_0[23] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +#set_location_assignment PIN_C9 -to GPIO_0[24] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +#set_location_assignment PIN_D9 -to GPIO_0[25] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +#set_location_assignment PIN_E11 -to GPIO_0[26] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +#set_location_assignment PIN_E10 -to GPIO_0[27] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +#set_location_assignment PIN_C11 -to GPIO_0[28] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +#set_location_assignment PIN_B11 -to GPIO_0[29] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +#set_location_assignment PIN_A12 -to GPIO_0[30] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +#set_location_assignment PIN_D11 -to GPIO_0[31] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +#set_location_assignment PIN_D12 -to GPIO_0[32] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +#set_location_assignment PIN_B12 -to GPIO_0[33] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] + +#============================================================ +# GPIO_1, GPIO_1 connect to GPIO Default +#============================================================ +#set_location_assignment PIN_T9 -to GPIO_1_IN[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0] +#set_location_assignment PIN_F13 -to GPIO_1[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +#set_location_assignment PIN_R9 -to GPIO_1_IN[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1] +#set_location_assignment PIN_T15 -to GPIO_1[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +#set_location_assignment PIN_T14 -to GPIO_1[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +#set_location_assignment PIN_T13 -to GPIO_1[3] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +#set_location_assignment PIN_R13 -to GPIO_1[4] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +#set_location_assignment PIN_T12 -to GPIO_1[5] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +#set_location_assignment PIN_R12 -to GPIO_1[6] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +#set_location_assignment PIN_T11 -to GPIO_1[7] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +#set_location_assignment PIN_T10 -to GPIO_1[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +#set_location_assignment PIN_R11 -to GPIO_1[9] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +#set_location_assignment PIN_P11 -to GPIO_1[10] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +#set_location_assignment PIN_R10 -to GPIO_1[11] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +#set_location_assignment PIN_N12 -to GPIO_1[12] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +#set_location_assignment PIN_P9 -to GPIO_1[13] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +#set_location_assignment PIN_N9 -to GPIO_1[14] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +#set_location_assignment PIN_N11 -to GPIO_1[15] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +#set_location_assignment PIN_L16 -to GPIO_1[16] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +#set_location_assignment PIN_K16 -to GPIO_1[17] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +#set_location_assignment PIN_R16 -to GPIO_1[18] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +#set_location_assignment PIN_L15 -to GPIO_1[19] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +#set_location_assignment PIN_P15 -to GPIO_1[20] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +#set_location_assignment PIN_P16 -to GPIO_1[21] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +#set_location_assignment PIN_R14 -to GPIO_1[22] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +#set_location_assignment PIN_N16 -to GPIO_1[23] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +#set_location_assignment PIN_N15 -to GPIO_1[24] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +#set_location_assignment PIN_P14 -to GPIO_1[25] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +#set_location_assignment PIN_L14 -to GPIO_1[26] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +#set_location_assignment PIN_N14 -to GPIO_1[27] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +#set_location_assignment PIN_M10 -to GPIO_1[28] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +#set_location_assignment PIN_L13 -to GPIO_1[29] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +#set_location_assignment PIN_J16 -to GPIO_1[30] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +#set_location_assignment PIN_K15 -to GPIO_1[31] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +#set_location_assignment PIN_J13 -to GPIO_1[32] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +#set_location_assignment PIN_J14 -to GPIO_1[33] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQM[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CAS_N +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_RAS_N +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_WE_N + +set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ* + +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH + + +set_global_assignment -name VHDL_FILE ../DE10_nano_zpu_Toplevel.vhd +set_global_assignment -name QIP_FILE Clock_50to100.qip +#set_global_assignment -name SDC_FILE DE10_nano_zpu_constraints.sdc +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd +#set_global_assignment -name VHDL_FILE ../cpu/zpu_flex_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd +#set_global_assignment -name VHDL_FILE ../cpu/zpu_small_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_cacheL2.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd +#set_global_assignment -name VHDL_FILE ../cpu/zpu_medium_pkg.vhd +#set_global_assignment -name VHDL_FILE ../trace/trace.vhd +#set_global_assignment -name VHDL_FILE ../trace/txt_util.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc.vhd +set_global_assignment -name VHDL_FILE ../devices/RAM/dpram.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/uart_brgen.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/uart_mv_filter.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/uart_rx.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/uart_tx.vhd +set_global_assignment -name VHDL_FILE ../devices/uart/uart.vhd +set_global_assignment -name VHDL_FILE ../devices/uart/uart_debug.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/simple_uart.vhd +#set_global_assignment -name VHDL_FILE ../devices/fifo/fifo.vhd +set_global_assignment -name VHDL_FILE ../devices/intr/interrupt_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/spi/spi.vhd +set_global_assignment -name VHDL_FILE ../devices/ps2/io_ps2_com.vhd +set_global_assignment -name VHDL_FILE ../devices/timer/timer_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/BootROM.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_0.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_1.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_2.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_3.vhd +set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_0.vhd +set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_1.vhd +set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_2.vhd +set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_3.vhd +set_global_assignment -name VHDL_FILE ../devices/ioctl/ioctl.vhd +set_global_assignment -name VHDL_FILE ../devices/RAM/dualport_ram.vhd +set_global_assignment -name VHDL_FILE ../../em/common/config_pkg.vhd +#set_global_assignment -name VERILOG_FILE ../cpu/qdiv.v +#set_global_assignment -name VHDL_FILE ../devices/Peripherals/simple_uart.vhd +#set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM.vhd +#set_global_assignment -name VHDL_FILE ../devices/RAM/DualPortRAM.vhd +#set_global_assignment -name VERILOG_FILE ../devices/RAM/TwoWayCache.v +#set_global_assignment -name VHDL_FILE ../devices/RAM/sdram_cached.vhd +#set_global_assignment -name VHDL_FILE ../Toplevel_Config.vhd +#set_global_assignment -name VHDL_FILE ../DMACache_config.vhd +#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_master.vhd +#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_dither.vhd +#set_global_assignment -name VHDL_FILE ../devices/Video/vga_controller.vhd +#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache.vhd +#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache_pkg.vhd +#set_global_assignment -name VHDL_FILE ../devices/DMA/FIFO_Counter.vhd +#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACacheRAM.vhd + + + + + + + + + + + + + +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/zpu/build/DE10_nano_zpu_Toplevel.vhd b/zpu/build/DE10_nano_zpu_Toplevel.vhd new file mode 100644 index 0000000..74febe2 --- /dev/null +++ b/zpu/build/DE10_nano_zpu_Toplevel.vhd @@ -0,0 +1,174 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.zpu_soc_pkg.all; + +entity DE10_nano_zpu is + port ( + -- Clock + CLOCK_50 : in std_logic; + -- LED + LED : out std_logic_vector(7 downto 0); + -- Debounced keys + KEY : in std_logic_vector(1 downto 0); + -- DIP switches + SW : in std_logic_vector(3 downto 0); + + TDI : out std_logic; + TCK : out std_logic; + TCS : out std_logic; + TDO : in std_logic; + -- I2C_SDAT : inout std_logic; + -- I2C_SCLK : out std_logic; + -- GPIO_0 : inout std_logic_vector(33 downto 0); + -- GPIO_1 : inout std_logic_vector(33 downto 0); + + -- SD Card 1 + SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + + -- UART Serial channels. + UART_RX_0 : in std_logic; + UART_TX_0 : out std_logic; + UART_RX_1 : in std_logic; + UART_TX_1 : out std_logic + +-- SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz +-- SDRAM_CKE : out std_logic; -- clock enable. +-- SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus +-- SDRAM_ADDR : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus +-- SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks +-- SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks +-- SDRAM_CS : out std_logic; -- a single chip select +-- SDRAM_WE : out std_logic; -- write enable +-- SDRAM_RAS : out std_logic; -- row address select +-- SDRAM_CAS : out std_logic -- columns address select + ); +END entity; + +architecture rtl of DE10_nano_zpu is + + signal reset : std_logic; + signal sysclk : std_logic; + signal memclk : std_logic; + signal pll_locked : std_logic; + + --signal ps2m_clk_in : std_logic; + --signal ps2m_clk_out : std_logic; + --signal ps2m_dat_in : std_logic; + --signal ps2m_dat_out : std_logic; + + --signal ps2k_clk_in : std_logic; + --signal ps2k_clk_out : std_logic; + --signal ps2k_dat_in : std_logic; + --signal ps2k_dat_out : std_logic; + + --alias PS2_MDAT : std_logic is GPIO_1(19); + --alias PS2_MCLK : std_logic is GPIO_1(18); + +begin + +--I2C_SDAT <= 'Z'; +--GPIO_0(33 downto 2) <= (others => 'Z'); +--GPIO_1 <= (others => 'Z'); +--LED <= "101010" & reset & UART_RX_0; +LED <= "00000000"; + +mypll : entity work.Clock_50to100 +port map +( + inclk0 => CLOCK_50, + c0 => sysclk, + c1 => memclk, + locked => pll_locked +); + +reset<=(not SW(0) xor KEY(0)) and pll_locked; + +myVirtualToplevel : entity work.zpu_soc +generic map +( + SYSCLK_FREQUENCY => SYSCLK_DE10_FREQ +) +port map +( + SYSCLK => sysclk, + MEMCLK => memclk, + RESET_IN => reset, + + -- RS232 + UART_RX_0 => UART_RX_0, + UART_TX_0 => UART_TX_0, + UART_RX_1 => UART_RX_1, + UART_TX_1 => UART_TX_1, + + -- SPI signals + SPI_MISO => TDO, -- Allow the SPI interface not to be plumbed in. + SPI_MOSI => TDI, + SPI_CLK => TCK, + SPI_CS => TCS, + + -- SD Card (SPI) signals + SDCARD_MISO => SDCARD_MISO, + SDCARD_MOSI => SDCARD_MOSI, + SDCARD_CLK => SDCARD_CLK, + SDCARD_CS => SDCARD_CS, + + -- PS/2 signals + PS2K_CLK_IN => '1', + PS2K_DAT_IN => '1', + PS2K_CLK_OUT => open, + PS2K_DAT_OUT => open, + PS2M_CLK_IN => '1', + PS2M_DAT_IN => '1', + PS2M_CLK_OUT => open, + PS2M_DAT_OUT => open, + + -- I²C signals + I2C_SCL_IO => open, + I2C_SDA_IO => open, + + -- IOCTL Bus -- + IOCTL_DOWNLOAD => open, -- Downloading to FPGA. + IOCTL_UPLOAD => open, -- Uploading from FPGA. + IOCTL_CLK => open, -- I/O Clock. + IOCTL_WR => open, -- Write Enable to FPGA. + IOCTL_RD => open, -- Read Enable from FPGA. + IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus. + IOCTL_SELECT => open, -- Enable IOP control over ioctl bus. + IOCTL_ADDR => open, -- Address in FPGA to write into. + IOCTL_DOUT => open, -- Data to be written into FPGA. + IOCTL_DIN => (others => '0'), -- Data to be read into HPS. + + -- SDRAM signals + SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz + SDRAM_CKE => open, --SDRAM_CKE, -- clock enable. + SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus + SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus + SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks + SDRAM_BA => open, --SDRAM_BA, -- two banks + SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select + SDRAM_WE_n => open, --SDRAM_WE, -- write enable + SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select + SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select + SDRAM_READY => open + + -- DDR2 DRAM - doesnt exist on the QMV. + --DDR2_ADDR => open, -- 14 bit multiplexed address bus + --DDR2_DQ => open, -- 64 bit bidirectional data bus + --DDR2_DQS => open, -- 8 bit bidirectional data bus + --DDR2_DQM => open, -- eight byte masks + --DDR2_ODT => open, -- 14 bit multiplexed address bus + --DDR2_BA => open, -- 8 banks + --DDR2_CS => open, -- 2 chip selects. + --DDR2_WE => open, -- write enable + --DDR2_RAS => open, -- row address select + --DDR2_CAS => open, -- columns address select + --DDR2_CKE => open, -- 2 clock enable. + --DDR2_CLK => open -- 2 clocks. +); + + +end architecture; diff --git a/zpu/build/DE10_nano_zpu_constraints.sdc b/zpu/build/DE10_nano_zpu_constraints.sdc new file mode 100644 index 0000000..3c7f513 --- /dev/null +++ b/zpu/build/DE10_nano_zpu_constraints.sdc @@ -0,0 +1,154 @@ +## Generated SDC file "hello_led.out.sdc" + +## Copyright (C) 1991-2011 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition" + +## DATE "Fri Jul 06 23:05:47 2012" + +## +## DEVICE "EP3C25Q240C8" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_50}] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + +create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_50}] -duty_cycle 50.000 -multiply_by 2 -master_clock {clk_50} [get_nets {mypll|altpll_component|auto_generated|wire_generic_pll1_outclk}] +#create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_50}] -duty_cycle 50.000 -phase 0 -multiply_by 4 -master_clock {clk_50} [get_nets {mypll|altpll_component|auto_generated|wire_generic_pll2_outclk}] + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] -setup 0.080 +#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] -hold 0.060 +#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] -setup 0.080 +#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] -hold 0.060 +#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] -setup 0.080 +#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] -hold 0.060 +#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] -setup 0.080 +#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] -hold 0.060 +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] -setup 0.080 +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] -hold 0.060 +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] -setup 0.080 +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] -hold 0.060 +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] -setup 0.080 +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] -hold 0.060 +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] -setup 0.080 +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] -hold 0.060 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] -setup 0.080 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] -hold 0.060 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] -setup 0.080 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] -hold 0.060 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] -setup 0.080 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] -hold 0.060 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] -setup 0.080 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] -hold 0.060 +derive_clock_uncertainty + + +#************************************************************** +# Set Input Delay +#************************************************************** + + +# Delays for async signals - not necessary, but might as well avoid +# having unconstrained ports in the design +#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}] +#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}] + +#************************************************************** +# Set Output Delay +#************************************************************** + +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[0]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[1]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[2]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[3]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[4]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[5]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[6]}] +#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[7]}] + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + +set_false_path -from [get_keepers {KEY*}] +set_false_path -from [get_keepers {SW*}] +#set_false_path -from [get_cells {myVirtualToplevel|RESET_n}] + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +#set_multicycle_path -setup -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 1 +#set_multicycle_path -hold -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 0 + +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 2 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** diff --git a/zpu/build/E115_zpu.cdf b/zpu/build/E115_zpu.cdf new file mode 100644 index 0000000..9d4404f --- /dev/null +++ b/zpu/build/E115_zpu.cdf @@ -0,0 +1,13 @@ +/* Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(EP4CE115F23) Path("/srv/dvlp/Projects/dev/github/zpu/build/") File("E115_zpu.sof") MfrSpec(OpMask(1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/zpu/build/E115_zpu.qpf b/zpu/build/E115_zpu.qpf new file mode 100644 index 0000000..f857ebe --- /dev/null +++ b/zpu/build/E115_zpu.qpf @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "5.0" +DATE = "23:35:58 September 01, 2005" + + +# Revisions + +PROJECT_REVISION = "E115_zpu" diff --git a/zpu/build/E115_zpu.qsf b/zpu/build/E115_zpu.qsf new file mode 100644 index 0000000..dbdc243 --- /dev/null +++ b/zpu/build/E115_zpu.qsf @@ -0,0 +1,302 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# ledwater_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2005" +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" +set_global_assignment -name CDF_FILE E115.cdf + +# Pin & Location Assignments +# ========================== + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name TOP_LEVEL_ENTITY E115_zpu + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP4CE115F23I7 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 + +# Assembler Assignments +# ===================== + +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" + +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 + + + + +#============================================================ +# UART +#============================================================ +set_location_assignment PIN_A7 -to UART_RX_0 +set_location_assignment PIN_B7 -to UART_TX_0 +set_location_assignment PIN_C6 -to UART_RX_1 +set_location_assignment PIN_D7 -to UART_TX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1 + +#============================================================ +# SD CARD +#============================================================ +set_location_assignment PIN_C8 -to SDCARD_MISO[0] +set_location_assignment PIN_C7 -to SDCARD_MOSI[0] +set_location_assignment PIN_B8 -to SDCARD_CLK[0] +set_location_assignment PIN_A8 -to SDCARD_CS[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0] + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_AB11 -to CLOCK_25 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_25 +#set_location_assignment PIN_AB11 -to clk_25M + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_location_assignment PIN_A5 -to LED[0] +set_location_assignment PIN_B5 -to LED[1] +set_location_assignment PIN_C4 -to LED[2] +set_location_assignment PIN_C3 -to LED[3] + +#============================================================ +# DDR2 DRAM +#============================================================ +#set_location_assignment PIN_AA20 -to DDR2_ADDR[13] +#set_location_assignment PIN_V8 -to DDR2_ADDR[12] +#set_location_assignment PIN_AB6 -to DDR2_ADDR[11] +#set_location_assignment PIN_K22 -to DDR2_ADDR[10] +#set_location_assignment PIN_W10 -to DDR2_ADDR[9] +#set_location_assignment PIN_T19 -to DDR2_ADDR[8] +#set_location_assignment PIN_Y14 -to DDR2_ADDR[7] +#set_location_assignment PIN_W14 -to DDR2_ADDR[6] +#set_location_assignment PIN_T20 -to DDR2_ADDR[5] +#set_location_assignment PIN_Y15 -to DDR2_ADDR[4] +#set_location_assignment PIN_L22 -to DDR2_ADDR[3] +#set_location_assignment PIN_Y17 -to DDR2_ADDR[2] +#set_location_assignment PIN_L21 -to DDR2_ADDR[1] +#set_location_assignment PIN_AB10 -to DDR2_ADDR[0] +#set_location_assignment PIN_Y6 -to DDR2_BA[2] +#set_location_assignment PIN_AB17 -to DDR2_BA[1] +#set_location_assignment PIN_K21 -to DDR2_BA[0] +#set_location_assignment PIN_J18 -to DDR2_CAS +#set_location_assignment PIN_Y4 -to DDR2_CKE[0] +#set_location_assignment PIN_AB5 -to DDR2_CKE[1] +#set_location_assignment PIN_AA19 -to DDR2_CS[0] +#set_location_assignment PIN_E21 -to DDR2_CS[1] +# +#set_location_assignment PIN_F20 -to DDR2_DM[7] +#set_location_assignment PIN_F22 -to DDR2_DM[6] +#set_location_assignment PIN_P22 -to DDR2_DM[5] +#set_location_assignment PIN_V22 -to DDR2_DM[4] +#set_location_assignment PIN_W15 -to DDR2_DM[3] +#set_location_assignment PIN_AA14 -to DDR2_DM[2] +#set_location_assignment PIN_AA8 -to DDR2_DM[1] +#set_location_assignment PIN_AA5 -to DDR2_DM[0] +# +#set_location_assignment PIN_B21 -to DDR2_DQ[63] +#set_location_assignment PIN_B22 -to DDR2_DQ[62] +#set_location_assignment PIN_C21 -to DDR2_DQ[61] +#set_location_assignment PIN_C22 -to DDR2_DQ[60] +#set_location_assignment PIN_D22 -to DDR2_DQ[59] +#set_location_assignment PIN_F19 -to DDR2_DQ[58] +#set_location_assignment PIN_F17 -to DDR2_DQ[57] +#set_location_assignment PIN_G18 -to DDR2_DQ[56] +#set_location_assignment PIN_E22 -to DDR2_DQ[55] +#set_location_assignment PIN_F21 -to DDR2_DQ[54] +#set_location_assignment PIN_H21 -to DDR2_DQ[53] +#set_location_assignment PIN_H22 -to DDR2_DQ[52] +#set_location_assignment PIN_H19 -to DDR2_DQ[51] +#set_location_assignment PIN_H20 -to DDR2_DQ[50] +#set_location_assignment PIN_K18 -to DDR2_DQ[49] +#set_location_assignment PIN_J21 -to DDR2_DQ[48] +#set_location_assignment PIN_M22 -to DDR2_DQ[47] +#set_location_assignment PIN_M21 -to DDR2_DQ[46] +#set_location_assignment PIN_R22 -to DDR2_DQ[45] +#set_location_assignment PIN_R21 -to DDR2_DQ[44] +#set_location_assignment PIN_M20 -to DDR2_DQ[43] +#set_location_assignment PIN_N20 -to DDR2_DQ[42] +#set_location_assignment PIN_P21 -to DDR2_DQ[41] +#set_location_assignment PIN_R19 -to DDR2_DQ[40] +#set_location_assignment PIN_U22 -to DDR2_DQ[39] +#set_location_assignment PIN_U21 -to DDR2_DQ[38] +#set_location_assignment PIN_V21 -to DDR2_DQ[37] +#set_location_assignment PIN_W22 -to DDR2_DQ[36] +#set_location_assignment PIN_R20 -to DDR2_DQ[35] +#set_location_assignment PIN_U20 -to DDR2_DQ[34] +#set_location_assignment PIN_Y22 -to DDR2_DQ[33] +#set_location_assignment PIN_AA21 -to DDR2_DQ[32] +#set_location_assignment PIN_AB20 -to DDR2_DQ[31] +#set_location_assignment PIN_AB18 -to DDR2_DQ[30] +#set_location_assignment PIN_AA16 -to DDR2_DQ[29] +#set_location_assignment PIN_AB16 -to DDR2_DQ[28] +#set_location_assignment PIN_W17 -to DDR2_DQ[27] +#set_location_assignment PIN_V15 -to DDR2_DQ[26] +#set_location_assignment PIN_T15 -to DDR2_DQ[25] +#set_location_assignment PIN_V14 -to DDR2_DQ[24] +#set_location_assignment PIN_AA15 -to DDR2_DQ[23] +#set_location_assignment PIN_AB15 -to DDR2_DQ[22] +#set_location_assignment PIN_AB14 -to DDR2_DQ[21] +#set_location_assignment PIN_AA13 -to DDR2_DQ[20] +#set_location_assignment PIN_W13 -to DDR2_DQ[19] +#set_location_assignment PIN_U12 -to DDR2_DQ[18] +#set_location_assignment PIN_AB13 -to DDR2_DQ[17] +#set_location_assignment PIN_AA10 -to DDR2_DQ[16] +#set_location_assignment PIN_AA9 -to DDR2_DQ[15] +#set_location_assignment PIN_AB8 -to DDR2_DQ[14] +#set_location_assignment PIN_AB7 -to DDR2_DQ[13] +#set_location_assignment PIN_AA7 -to DDR2_DQ[12] +#set_location_assignment PIN_V11 -to DDR2_DQ[11] +#set_location_assignment PIN_Y10 -to DDR2_DQ[10] +#set_location_assignment PIN_U10 -to DDR2_DQ[9] +#set_location_assignment PIN_Y8 -to DDR2_DQ[8] +#set_location_assignment PIN_W8 -to DDR2_DQ[7] +#set_location_assignment PIN_V5 -to DDR2_DQ[6] +#set_location_assignment PIN_AA4 -to DDR2_DQ[5] +#set_location_assignment PIN_Y3 -to DDR2_DQ[4] +#set_location_assignment PIN_U9 -to DDR2_DQ[3] +#set_location_assignment PIN_W7 -to DDR2_DQ[2] +#set_location_assignment PIN_Y7 -to DDR2_DQ[1] +#set_location_assignment PIN_W6 -to DDR2_DQ[0] +# +#set_location_assignment PIN_C20 -to DDR2_DQS[7] +#set_location_assignment PIN_J22 -to DDR2_DQS[6] +#set_location_assignment PIN_N18 -to DDR2_DQS[5] +#set_location_assignment PIN_W20 -to DDR2_DQS[4] +#set_location_assignment PIN_V13 -to DDR2_DQS[3] +#set_location_assignment PIN_Y13 -to DDR2_DQS[2] +#set_location_assignment PIN_AB9 -to DDR2_DQS[1] +#set_location_assignment PIN_V10 -to DDR2_DQS[0] +# +#set_location_assignment PIN_AB19 -to DDR2_ODT[0] +#set_location_assignment PIN_D21 -to DDR2_ODT[1] +#set_location_assignment PIN_AA17 -to DDR2_RAS +#set_location_assignment PIN_J20 -to DDR2_WE + +#============================================================ +# Modules and Files +#============================================================ + +set_global_assignment -name VHDL_FILE ../E115_zpu_Toplevel.vhd +set_global_assignment -name QIP_FILE Clock_25to100.qip +set_global_assignment -name SDC_FILE E115_zpu_constraints.sdc +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd +#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip +set_global_assignment -name VHDL_FILE ../devices/WishBone/SRAM/sram.vhd +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF +set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON +set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation + +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF + + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/zpu/build/E115_zpu.qsf.2406 b/zpu/build/E115_zpu.qsf.2406 new file mode 100644 index 0000000..b10429c --- /dev/null +++ b/zpu/build/E115_zpu.qsf.2406 @@ -0,0 +1,176 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# ledwater_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2005" +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" +#set_global_assignment -name VERILOG_FILE ledwater.v +set_global_assignment -name CDF_FILE E115.cdf + +# Pin & Location Assignments +# ========================== + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name TOP_LEVEL_ENTITY E115_zpu + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP4CE115F23I7 +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 + +# Assembler Assignments +# ===================== + +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH + + +#============================================================ +# UART +#============================================================ +set_location_assignment PIN_A7 -to UART_RX_0 +set_location_assignment PIN_B7 -to UART_TX_0 +set_location_assignment PIN_C6 -to UART_RX_1 +set_location_assignment PIN_D7 -to UART_TX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1 + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_AB11 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 +#set_location_assignment PIN_AB11 -to clk_25M + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_location_assignment PIN_A5 -to LED[0] +set_location_assignment PIN_B5 -to LED[1] +set_location_assignment PIN_C4 -to LED[2] +set_location_assignment PIN_C3 -to LED[3] + +#============================================================ +# Modules and Files +#============================================================ + +set_global_assignment -name VHDL_FILE ../E115_zpu_Toplevel.vhd +set_global_assignment -name QIP_FILE Clock_25to100.qip +set_global_assignment -name SDC_FILE E115_zpu_constraints.sdc +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd +#set_global_assignment -name VHDL_FILE ../cpu/zpu_flex_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd +#set_global_assignment -name VHDL_FILE ../cpu/zpu_small_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd +#set_global_assignment -name VHDL_FILE ../cpu/zpu_medium_pkg.vhd +#set_global_assignment -name VHDL_FILE ../trace/trace.vhd +#set_global_assignment -name VHDL_FILE ../trace/txt_util.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc.vhd +set_global_assignment -name VHDL_FILE ../devices/RAM/dpram.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/uart_brgen.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/uart_mv_filter.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/uart_rx.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/uart_tx.vhd +set_global_assignment -name VHDL_FILE ../devices/uart/uart.vhd +set_global_assignment -name VHDL_FILE ../devices/uart/uart_debug.vhd +#set_global_assignment -name VHDL_FILE ../devices/uart/simple_uart.vhd +#set_global_assignment -name VHDL_FILE ../devices/fifo/fifo.vhd +set_global_assignment -name VHDL_FILE ../devices/intr/interrupt_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/spi/spi.vhd +set_global_assignment -name VHDL_FILE ../devices/ps2/io_ps2_com.vhd +set_global_assignment -name VHDL_FILE ../devices/timer/timer_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/BootROM.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_0.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_1.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_2.vhd +set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_3.vhd +set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_0.vhd +set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_1.vhd +set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_2.vhd +set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_3.vhd +set_global_assignment -name VHDL_FILE ../devices/ioctl/ioctl.vhd +set_global_assignment -name VHDL_FILE ../devices/RAM/dualport_ram.vhd +set_global_assignment -name VHDL_FILE ../../em/common/config_pkg.vhd +#set_global_assignment -name VERILOG_FILE ../cpu/qdiv.v +#set_global_assignment -name VHDL_FILE ../devices/Peripherals/simple_uart.vhd +#set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM.vhd +#set_global_assignment -name VHDL_FILE ../devices/RAM/DualPortRAM.vhd +#set_global_assignment -name VERILOG_FILE ../devices/RAM/TwoWayCache.v +#set_global_assignment -name VHDL_FILE ../devices/RAM/sdram_cached.vhd +#set_global_assignment -name VHDL_FILE ../Toplevel_Config.vhd +#set_global_assignment -name VHDL_FILE ../DMACache_config.vhd +#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_master.vhd +#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_dither.vhd +#set_global_assignment -name VHDL_FILE ../devices/Video/vga_controller.vhd +#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache.vhd +#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache_pkg.vhd +#set_global_assignment -name VHDL_FILE ../devices/DMA/FIFO_Counter.vhd +#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACacheRAM.vhd +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" + + + + + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/zpu/build/E115_zpu_Toplevel.vhd b/zpu/build/E115_zpu_Toplevel.vhd new file mode 100644 index 0000000..313885a --- /dev/null +++ b/zpu/build/E115_zpu_Toplevel.vhd @@ -0,0 +1,177 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.zpu_soc_pkg.all; + +entity E115_zpu is + port ( + -- Clock + CLOCK_25 : in std_logic; + -- LED + LED : out std_logic_vector(7 downto 0); + -- Debounced keys + KEY : in std_logic_vector(1 downto 0); + -- DIP switches + SW : in std_logic_vector(3 downto 0); + + -- TDI : in std_logic; + -- TCK : in std_logic; + -- TCS : in std_logic; + -- TDO : out std_logic; + -- I2C_SDAT : inout std_logic; + -- I2C_SCLK : out std_logic; + -- GPIO_0 : inout std_logic_vector(33 downto 0); + -- GPIO_1 : inout std_logic_vector(33 downto 0); + + -- SD Card 1 + SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + + -- UART Serial channels. + UART_RX_0 : in std_logic; + UART_TX_0 : out std_logic; + UART_RX_1 : in std_logic; + UART_TX_1 : out std_logic + + -- DDR2 DRAM + --DDR2_ADDR : out std_logic_vector(13 downto 0); -- 14 bit multiplexed address bus + --DDR2_DQ : inout std_logic_vector(63 downto 0); -- 64 bit bidirectional data bus + --DDR2_DQS : inout std_logic_vector(7 downto 0); -- 8 bit bidirectional data bus + --DDR2_DQM : out std_logic_vector(17 downto 0); -- eight byte masks + --DDR2_ODT : out std_logic_vector(1 downto 0); -- 14 bit multiplexed address bus + --DDR2_BA : out std_logic_vector(2 downto 0); -- 8 banks + --DDR2_CS : out std_logic_vector(1 downto 0); -- 2 chip selects. + --DDR2_WE : out std_logic; -- write enable + --DDR2_RAS : out std_logic; -- row address select + --DDR2_CAS : out std_logic; -- columns address select + --DDR2_CKE : out std_logic_vector(1 downto 0); -- 2 clock enable. + --DDR2_CLK : out std_logic_vector(1 downto 0) -- 2 clocks. + ); +END entity; + +architecture rtl of E115_zpu is + + signal reset : std_logic; + signal sysclk : std_logic; + signal memclk : std_logic; + signal pll_locked : std_logic; + + --signal ps2m_clk_in : std_logic; + --signal ps2m_clk_out : std_logic; + --signal ps2m_dat_in : std_logic; + --signal ps2m_dat_out : std_logic; + + --signal ps2k_clk_in : std_logic; + --signal ps2k_clk_out : std_logic; + --signal ps2k_dat_in : std_logic; + --signal ps2k_dat_out : std_logic; + + --alias PS2_MDAT : std_logic is GPIO_1(19); + --alias PS2_MCLK : std_logic is GPIO_1(18); + +begin + +--I2C_SDAT <= 'Z'; +--GPIO_0(33 downto 2) <= (others => 'Z'); +--GPIO_1 <= (others => 'Z'); +--LED <= "101010" & reset & UART_RX_0; +LED <= "00000000"; + +mypll : entity work.Clock_25to100 +port map +( + inclk0 => CLOCK_25, + c0 => sysclk, + c1 => memclk, + locked => pll_locked +); + +reset<=(not SW(0) xor KEY(0)) and pll_locked; + +myVirtualToplevel : entity work.zpu_soc +generic map +( + SYSCLK_FREQUENCY => SYSCLK_E115_FREQ +) +port map +( + SYSCLK => sysclk, + MEMCLK => memclk, + RESET_IN => reset, + + -- RS232 + UART_RX_0 => UART_RX_0, + UART_TX_0 => UART_TX_0, + UART_RX_1 => UART_RX_1, + UART_TX_1 => UART_TX_1, + + -- SPI signals + SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in. + SPI_MOSI => open, + SPI_CLK => open, + SPI_CS => open, + + -- SD Card (SPI) signals + SDCARD_MISO => SDCARD_MISO, + SDCARD_MOSI => SDCARD_MOSI, + SDCARD_CLK => SDCARD_CLK, + SDCARD_CS => SDCARD_CS, + + -- PS/2 signals + PS2K_CLK_IN => '1', + PS2K_DAT_IN => '1', + PS2K_CLK_OUT => open, + PS2K_DAT_OUT => open, + PS2M_CLK_IN => '1', + PS2M_DAT_IN => '1', + PS2M_CLK_OUT => open, + PS2M_DAT_OUT => open, + + -- I²C signals + I2C_SCL_IO => open, + I2C_SDA_IO => open, + + -- IOCTL Bus -- + IOCTL_DOWNLOAD => open, -- Downloading to FPGA. + IOCTL_UPLOAD => open, -- Uploading from FPGA. + IOCTL_CLK => open, -- I/O Clock. + IOCTL_WR => open, -- Write Enable to FPGA. + IOCTL_RD => open, -- Read Enable from FPGA. + IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus. + IOCTL_SELECT => open, -- Enable IOP control over ioctl bus. + IOCTL_ADDR => open, -- Address in FPGA to write into. + IOCTL_DOUT => open, -- Data to be written into FPGA. + IOCTL_DIN => (others => '0'), -- Data to be read into HPS. + + -- SDRAM signals which do not exist on the E115 + SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz + SDRAM_CKE => open, --SDRAM_CKE, -- clock enable. + SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus + SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus + SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks + SDRAM_BA => open, --SDRAM_BA, -- two banks + SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select + SDRAM_WE_n => open, --SDRAM_WE, -- write enable + SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select + SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select + SDRAM_READY => open -- sd ready. + + -- DDR2 DRAM + --DDR2_ADDR => DDR2_ADDR, -- 14 bit multiplexed address bus + --DDR2_DQ => DDR2_DQ, -- 64 bit bidirectional data bus + --DDR2_DQS => DDR2_DQS, -- 8 bit bidirectional data bus + --DDR2_DQM => DDR2_DQM, -- eight byte masks + --DDR2_ODT => DDR2_ODT, -- 14 bit multiplexed address bus + --DDR2_BA => DDR2_BA, -- 8 banks + --DDR2_CS => DDR2_CS, -- 2 chip selects. + --DDR2_WE => DDR2_WE, -- write enable + --DDR2_RAS => DDR2_RAS, -- row address select + --DDR2_CAS => DDR2_CAS, -- columns address select + --DDR2_CKE => DDR2_CKE, -- 2 clock enable. + --DDR2_CLK => DDR2_CLK -- 2 clocks. +); + + +end architecture; diff --git a/zpu/build/E115_zpu_constraints.sdc b/zpu/build/E115_zpu_constraints.sdc new file mode 100644 index 0000000..f1a16ee --- /dev/null +++ b/zpu/build/E115_zpu_constraints.sdc @@ -0,0 +1,129 @@ +## Generated SDC file "E115_zpu.out.sdc" + +## Copyright (C) 2017 Intel Corporation. All rights reserved. +## Your use of Intel Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Intel Program License +## Subscription Agreement, the Intel Quartus Prime License Agreement, +## the Intel FPGA IP License Agreement, or other applicable license +## agreement, including, without limitation, that your use is for +## the sole purpose of programming logic devices manufactured by +## Intel and sold by Intel or its authorized distributors. Please +## refer to the applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus Prime" +## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition" + +## DATE "Sat Jun 22 23:32:00 2019" + +## +## DEVICE "EP4CE115F23I7" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clk_25} -period 40.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_25}] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + +create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_25}] -duty_cycle 50.000 -multiply_by 4 -divide_by 1 -master_clock {clk_25} [get_nets {mypll|altpll_component|_clk0}] +#create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_25}] -duty_cycle 50.000 -multiply_by 8 -divide_by 1 -master_clock {clk_25} [get_nets {mypll|altpll_component|_clk1}] + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] 0.020 +#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] 0.020 +#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] 0.020 +#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] 0.020 +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] 0.020 +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] 0.020 +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020 +#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] 0.020 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] 0.020 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020 +#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020 +derive_clock_uncertainty + + +#************************************************************** +# Set Input Delay +#************************************************************** + +# Delays for async signals - not necessary, but might as well avoid +# having unconstrained ports in the design +#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}] +#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}] + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + +set_false_path -from [get_keepers {KEY*}] +set_false_path -from [get_keepers {SW*}] + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -setup -start 1 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -hold -start 0 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/zpu/build/Makefile b/zpu/build/Makefile new file mode 100644 index 0000000..0293db1 --- /dev/null +++ b/zpu/build/Makefile @@ -0,0 +1,303 @@ +######################################################################################################### +## +## Name: Makefile +## Created: June 2019 +## Author(s): Philip Smart +## Description: ZPU Makefile +## This script builds the ZPU test images and should be used as a basis for main +## project builds. +## +## Credits: +## Copyright: (c) 2019 Philip Smart +## +## History: June 2019 - Initial script written. +## +######################################################################################################### +## This source file is free software: you can redistribute it and#or modify +## it under the terms of the GNU General Public License as published +## by the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This source file is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +######################################################################################################### + +DE10_IP = 192.168.10.1 +DE10_USER = root +DE10_PWD = 1 +ROOT = ../ + +# Build utilites +QUARTUS_SH = quartus_sh +QUARTUS_CPF = quartus_cpf +TEE = tee +ECHO = echo +MV = mv +GREP = grep +RM = rm +CC = CC $(CINCLUDES) +AR = ar +LD = ld + +# Build flags +SH_FLAGS = --flow compile +CPF_FLAGS = -c -o bitstream_compression=on +MSG_FILTER = "Error\|success" +# MSG_FILTER = "Info\|Warning\|Error\|success" +# MSG_FILTER = "Info\|Warning\|Error\|success" +# MSG_FILTER = "Info\|Warning\|Error\|success" + +SOC = $(ROOT)/zpu_soc.vhd $(ROOT)/zpu_soc_pkg.vhd +ZPU_EVO = $(ROOT)/cpu/zpu_core_evo.vhd $(ROOT)/cpu/zpu_pkg.vhd + +.PHONY: all +all: DE10_nano_SMALL DE10_nano_MEDIUM DE10_nano_FLEX DE10_nano_EVO DE10_nano_EVO_MINIMAL E115_SMALL E115_MEDIUM E115_FLEX E115_EVO E115_EVO_MINIMAL DE0_nano_SMALL DE0_nano_MEDIUM DE0_nano_FLEX DE0_nano_EVO DE0_nano_EVO_MINIMAL QMV_SMALL QMV_MEDIUM QMV_FLEX QMV_EVO QMV_EVO_MINIMAL CYC1000_SMALL CYC1000_MEDIUM CYC1000_FLEX CYC1000_EVO CYC1000_EVO_MINIMAL +DE0_nano: DE0_nano_SMALL DE0_nano_MEDIUM DE0_nano_FLEX DE0_nano_EVO DE0_nano_EVO_MINIMAL +DE10_nano: DE10_nano_SMALL DE10_nano_MEDIUM DE10_nano_FLEX DE10_nano_EVO DE10_nano_EVO_MINIMAL +E115: E115_SMALL E115_MEDIUM E115_FLEX E115_EVO E115_EVO_MINIMAL +QMV: QMV_SMALL QMV_MEDIUM QMV_FLEX QMV_EVO QMV_EVO_MINIMAL +CYC1000: CYC1000_SMALL CYC1000_MEDIUM CYC1000_FLEX CYC1000_EVO CYC1000_EVO_MINIMAL +SMALL: DE10_nano_SMALL E115_SMALL DE0_nano_SMALL QMV_SMALL CYC1000_SMALL +MEDIUM: DE10_nano_MEDIUM E115_MEDIUM DE0_nano_MEDIUM QMV_MEDIUM CYC1000_MEDIUM +FLEX: DE10_nano_FLEX E115_FLEX DE0_nano_FLEX QMV_FLEX CYC1000_FLEX +EVO: DE10_nano_EVO E115_EVO DE0_nano_EVO QMV_EVO CYC1000_EVO +EVO_MINIMAL: DE10_nano_EVO_MINIMAL E115_EVO_MINIMAL DE0_nano_EVO_MINIMAL QMV_EVO_MINIMAL CYC1000_EVO_MINIMAL + +DE10_nano_SMALL: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) DE10_nano_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +DE10_nano_MEDIUM: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) DE10_nano_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +DE10_nano_FLEX: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) DE10_nano_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +DE10_nano_EVO: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) DE10_nano_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +DE10_nano_EVO_MINIMAL: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) DE10_nano_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +DE0_nano_SMALL: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) DE0_nano_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +DE0_nano_MEDIUM: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) DE0_nano_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +DE0_nano_FLEX: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) DE0_nano_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +DE0_nano_EVO: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) DE0_nano_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +DE0_nano_EVO_MINIMAL: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) DE0_nano_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +E115_SMALL: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) E115_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +E115_MEDIUM: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) E115_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +E115_FLEX: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) E115_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +E115_EVO: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) E115_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +E115_EVO_MINIMAL: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) E115_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +QMV_SMALL: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) QMV_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +QMV_MEDIUM: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) QMV_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +QMV_FLEX: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) QMV_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +QMV_EVO: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) QMV_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +QMV_EVO_MINIMAL: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) QMV_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +CYC1000_SMALL: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) CYC1000_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +CYC1000_MEDIUM: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) CYC1000_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +CYC1000_FLEX: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) CYC1000_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +CYC1000_EVO: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) CYC1000_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +CYC1000_EVO_MINIMAL: + @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \ + > $(ROOT)/zpu_soc_pkg.vhd + @$(ECHO) "Compiling $@..." + @$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER) + @$(MV) CYC1000_zpu.sof $@.sof + @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER) + @$(ECHO) "$@.sof and $@.rbf generated..." + +clean: + @$(ECHO) "Removing all temporary files..." + @$(RM) -fr c5_pin_model_dump.txt ./db ./simulation DE0_nano_zpu.asm.rpt DE0_nano_zpu.done DE0_nano_zpu.fit.rpt DE0_nano_zpu.fit.smsg DE0_nano_zpu.fit.summary DE0_nano_zpu.flow.rpt DE0_nano_zpu.jdi DE0_nano_zpu.map.rpt DE0_nano_zpu.map.smsg DE0_nano_zpu.map.summary DE0_nano_zpu.pin DE0_nano_zpu.rbf DE0_nano_zpu.sld DE0_nano_zpu.sof DE0_nano_zpu.sta.rpt DE0_nano_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt DE0*.log DE0_nano*.rbf DE0_nano*.sof DE0_nano*.sta.smsg + @$(RM) -fr c5_pin_model_dump.txt ./db DE10_nano_zpu.asm.rpt DE10_nano_zpu.done DE10_nano_zpu.fit.rpt DE10_nano_zpu.fit.smsg DE10_nano_zpu.fit.summary DE10_nano_zpu.flow.rpt DE10_nano_zpu.jdi DE10_nano_zpu.map.rpt DE10_nano_zpu.map.smsg DE10_nano_zpu.map.summary DE10_nano_zpu.pin DE10_nano_zpu.rbf DE10_nano_zpu.sld DE10_nano_zpu.sof DE10_nano_zpu.sta.rpt DE10_nano_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt DE10*.log DE10_nano*.rbf DE10_nano*.sof DE10_nano*.sta.smsg + @$(RM) -fr c5_pin_model_dump.txt ./db E115_zpu.asm.rpt E115_zpu.done E115_zpu.fit.rpt E115_zpu.fit.smsg E115_zpu.fit.summary E115_zpu.flow.rpt E115_zpu.jdi E115_zpu.map.rpt E115_zpu.map.smsg E115_zpu.map.summary E115_zpu.pin E115_zpu.rbf E115_zpu.sld E115_zpu.sof E115_zpu.sta.rpt E115_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt E115_zpu.pof E115*.log E115*.rbf E115*.sof E115*.sta.smsg + @$(RM) -fr c5_pin_model_dump.txt ./db CYC1000_zpu.asm.rpt CYC1000_zpu.done CYC1000_zpu.fit.rpt CYC1000_zpu.fit.smsg CYC1000_zpu.fit.summary CYC1000_zpu.flow.rpt CYC1000_zpu.jdi CYC1000_zpu.map.rpt CYC1000_zpu.map.smsg CYC1000_zpu.map.summary CYC1000_zpu.pin CYC1000_zpu.rbf CYC1000_zpu.sld CYC1000_zpu.sof CYC1000_zpu.sta.rpt CYC1000_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt CYC1000_zpu.pof CYC1000*.log CYC1000*.rbf CYC1000*.sof CYC1000*.sta.smsg + @$(RM) -fr c5_pin_model_dump.txt ./db QMV_zpu.asm.rpt QMV_zpu.done QMV_zpu.fit.rpt QMV_zpu.fit.smsg QMV_zpu.fit.summary QMV_zpu.flow.rpt QMV_zpu.jdi QMV_zpu.map.rpt QMV_zpu.map.smsg QMV_zpu.map.summary QMV_zpu.pin QMV_zpu.rbf QMV_zpu.sld QMV_zpu.sof QMV_zpu.sta.rpt QMV_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt QMV_zpu.pof QMV*.log QMV*.rbf QMV*.sof QMV*.sta.smsg + @$(RM) -fr output_files diff --git a/zpu/build/QMV_zpu.cdf b/zpu/build/QMV_zpu.cdf new file mode 100644 index 0000000..81376e4 --- /dev/null +++ b/zpu/build/QMV_zpu.cdf @@ -0,0 +1,13 @@ +/* Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(5CEFA2F23) Path("/srv/dvlp/Projects/dev/github/zpu/build/") File("QMV_zpu.sof") MfrSpec(OpMask(1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/zpu/build/QMV_zpu.qpf b/zpu/build/QMV_zpu.qpf new file mode 100644 index 0000000..dcdf51c --- /dev/null +++ b/zpu/build/QMV_zpu.qpf @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "5.0" +DATE = "23:35:58 September 01, 2005" + + +# Revisions + +PROJECT_REVISION = "QMV_zpu" diff --git a/zpu/build/QMV_zpu.qsf b/zpu/build/QMV_zpu.qsf new file mode 100644 index 0000000..f28e3fa --- /dev/null +++ b/zpu/build/QMV_zpu.qsf @@ -0,0 +1,473 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# ledwater_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" +set_global_assignment -name CDF_FILE QMV.cdf + +# Pin & Location Assignments +# ========================== + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TOP_LEVEL_ENTITY QMV_zpu + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE 5CEFA2F23C8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 + +# Assembler Assignments +# ===================== +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" + +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name NUM_PARALLEL_PROCESSORS 8 + + +#============================================================ +# CLOCK2 +#============================================================ + +#============================================================ +# CLOCK3 +#============================================================ + +#============================================================ +# CLOCK4 +#============================================================ + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_M9 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 + +#============================================================ +# DRAM +#============================================================ +set_location_assignment PIN_Y9 -to SDRAM_ADDR[12] +set_location_assignment PIN_T9 -to SDRAM_ADDR[11] +set_location_assignment PIN_R6 -to SDRAM_ADDR[10] +set_location_assignment PIN_W8 -to SDRAM_ADDR[9] +set_location_assignment PIN_T8 -to SDRAM_ADDR[8] +set_location_assignment PIN_U8 -to SDRAM_ADDR[7] +set_location_assignment PIN_V6 -to SDRAM_ADDR[6] +set_location_assignment PIN_U7 -to SDRAM_ADDR[5] +set_location_assignment PIN_U6 -to SDRAM_ADDR[4] +set_location_assignment PIN_N6 -to SDRAM_ADDR[3] +set_location_assignment PIN_N8 -to SDRAM_ADDR[2] +set_location_assignment PIN_P7 -to SDRAM_ADDR[1] +set_location_assignment PIN_P8 -to SDRAM_ADDR[0] +set_location_assignment PIN_P9 -to SDRAM_BA[1] +set_location_assignment PIN_T7 -to SDRAM_BA[0] +set_location_assignment PIN_AA7 -to SDRAM_CAS +set_location_assignment PIN_V9 -to SDRAM_CKE +set_location_assignment PIN_AB11 -to SDRAM_CLK +set_location_assignment PIN_AB5 -to SDRAM_CS +set_location_assignment PIN_P12 -to SDRAM_DQ[15] +set_location_assignment PIN_R12 -to SDRAM_DQ[14] +set_location_assignment PIN_U12 -to SDRAM_DQ[13] +set_location_assignment PIN_R11 -to SDRAM_DQ[12] +set_location_assignment PIN_R10 -to SDRAM_DQ[11] +set_location_assignment PIN_U11 -to SDRAM_DQ[10] +set_location_assignment PIN_T10 -to SDRAM_DQ[9] +set_location_assignment PIN_U10 -to SDRAM_DQ[8] +set_location_assignment PIN_AA8 -to SDRAM_DQ[7] +set_location_assignment PIN_AB8 -to SDRAM_DQ[6] +set_location_assignment PIN_AA9 -to SDRAM_DQ[5] +set_location_assignment PIN_Y10 -to SDRAM_DQ[4] +set_location_assignment PIN_AB10 -to SDRAM_DQ[3] +set_location_assignment PIN_AA10 -to SDRAM_DQ[2] +set_location_assignment PIN_Y11 -to SDRAM_DQ[1] +set_location_assignment PIN_AA12 -to SDRAM_DQ[0] +set_location_assignment PIN_AB7 -to SDRAM_DQM[0] +set_location_assignment PIN_AB6 -to SDRAM_RAS +set_location_assignment PIN_V10 -to SDRAM_DQM[1] +set_location_assignment PIN_W9 -to SDRAM_WE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[15] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[0] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[1] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[2] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[3] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[4] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[5] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[6] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[7] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[8] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[9] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[10] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[11] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[12] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[13] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[14] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[13] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[0] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[1] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[2] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[3] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[4] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[5] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[6] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[7] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[8] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[9] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[10] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[11] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[12] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQM[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQM[1] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_BA[0] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_BA[1] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQM[0] +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_RAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_WE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CS +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_CAS +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_RAS +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_WE +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_CS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_CKE +set_instance_assignment -name SLEW_RATE 0 -to SDRAM_CLK + +#============================================================ +# GPIO +#============================================================ +# U8 5 - 59, odd +# +# U8 6 - 58 Even +set_location_assignment PIN_AA13 -to BANK_4A_AA13 +set_location_assignment PIN_AB15 -to BANK_4A_AB15 +set_location_assignment PIN_Y14 -to BANK_4A_Y14 +set_location_assignment PIN_AB17 -to BANK_4A_AB17 +set_location_assignment PIN_Y16 -to BANK_4A_Y16 +set_location_assignment PIN_AA17 -to BANK_4A_AA17 +set_location_assignment PIN_AA19 -to BANK_4A_AA19 +set_location_assignment PIN_Y19 -to BANK_4A_Y19 +set_location_assignment PIN_AB20 -to BANK_4A_AB20 +set_location_assignment PIN_AB22 -to BANK_4A_AB22 +set_location_assignment PIN_Y22 -to BANK_4A_Y22 +set_location_assignment PIN_W21 -to BANK_4A_W21 +set_location_assignment PIN_V21 -to BANK_4A_V21 +set_location_assignment PIN_W19 -to BANK_4A_W19 +set_location_assignment PIN_U20 -to BANK_4A_U20 +set_location_assignment PIN_T22 -to BANK_5A_T22 +set_location_assignment PIN_R21 -to BANK_5A_R21 +set_location_assignment PIN_T19 -to BANK_5A_T19 +set_location_assignment PIN_P17 -to BANK_5A_P17 +set_location_assignment PIN_N21 -to BANK_5B_N21 +set_location_assignment PIN_M20 -to BANK_5B_M20 +set_location_assignment PIN_N19 -to BANK_5B_N19 +set_location_assignment PIN_L19 -to BANK_5B_L19 +set_location_assignment PIN_L22 -to BANK_5B_L22 +set_location_assignment PIN_K17 -to BANK_5B_K17 +set_location_assignment PIN_K21 -to BANK_5B_K21 +set_location_assignment PIN_N16 -to BANK_5B_N16 +# +# U7 5 - 59 odd +#set_location_assignment PIN_AA14 -to BANK_4A_AA14 +#set_location_assignment PIN_AA15 -to BANK_4A_AA15 +#set_location_assignment PIN_Y15 -to BANK_4A_Y15 +#set_location_assignment PIN_AB18 -to BANK_4A_AB18 +set_location_assignment PIN_Y17 -to BANK_4A_Y17 +set_location_assignment PIN_AA18 -to BANK_4A_AA18 +set_location_assignment PIN_AA20 -to BANK_4A_AA20 +set_location_assignment PIN_Y20 -to BANK_4A_Y20 +set_location_assignment PIN_AB21 -to BANK_4A_AB21 +set_location_assignment PIN_AA22 -to BANK_4A_AA22 +set_location_assignment PIN_W22 -to BANK_4A_W22 +set_location_assignment PIN_Y21 -to BANK_4A_Y21 +set_location_assignment PIN_U22 -to BANK_4A_U22 +set_location_assignment PIN_V20 -to BANK_4A_V20 +set_location_assignment PIN_U21 -to BANK_4A_U21 +set_location_assignment PIN_R22 -to BANK_5A_R22 +set_location_assignment PIN_P22 -to BANK_5A_P22 +set_location_assignment PIN_T20 -to BANK_5A_T20 +set_location_assignment PIN_P16 -to BANK_5A_P16 +set_location_assignment PIN_N20 -to BANK_5B_N20 +set_location_assignment PIN_M21 -to BANK_5B_M21 +set_location_assignment PIN_M18 -to BANK_5B_M18 +set_location_assignment PIN_L18 -to BANK_5B_L18 +set_location_assignment PIN_M22 -to BANK_5B_M22 +set_location_assignment PIN_L17 -to BANK_5B_L17 +set_location_assignment PIN_K22 -to BANK_5B_K22 +set_location_assignment PIN_M16 -to BANK_5B_M16 +# +# U7 6 - 60 even +set_location_assignment PIN_AA1 -to BANK_2A_AA1 +set_location_assignment PIN_W2 -to BANK_2A_W2 +set_location_assignment PIN_U2 -to BANK_2A_U2 +set_location_assignment PIN_N2 -to BANK_2A_N2 +set_location_assignment PIN_L2 -to BANK_2A_L2 +set_location_assignment PIN_G2 -to BANK_2A_G2 +set_location_assignment PIN_D3 -to BANK_2A_D3 +set_location_assignment PIN_C2 -to BANK_2A_C2 +set_location_assignment PIN_H6 -to BANK_8A_H6 +set_location_assignment PIN_H8 -to BANK_8A_H8 +set_location_assignment PIN_E7 -to BANK_8A_E7 +set_location_assignment PIN_C6 -to BANK_8A_C6 +set_location_assignment PIN_D9 -to BANK_8A_D9 +set_location_assignment PIN_A5 -to BANK_8A_A5 +set_location_assignment PIN_B7 -to BANK_8A_B7 +set_location_assignment PIN_A8 -to BANK_8A_A8 +set_location_assignment PIN_A10 -to BANK_8A_A10 +set_location_assignment PIN_C9 -to BANK_8A_C9 +set_location_assignment PIN_F10 -to BANK_8A_F10 +set_location_assignment PIN_B11 -to BANK_7A_B11 +set_location_assignment PIN_A12 -to BANK_7A_A12 +set_location_assignment PIN_D12 -to BANK_7A_D12 +set_location_assignment PIN_C13 -to BANK_7A_C13 +set_location_assignment PIN_A13 -to BANK_7A_A13 +set_location_assignment PIN_A14 -to BANK_7A_A14 +set_location_assignment PIN_C15 -to BANK_7A_C15 +set_location_assignment PIN_B16 -to BANK_7A_B16 + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_AB13 -to KEY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY + +#============================================================ +# LEDR +#============================================================ +set_location_assignment PIN_D17 -to LEDR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR + +#============================================================ +# PS2 +#============================================================ + +#============================================================ +# RESET +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N +set_location_assignment PIN_V18 -to RESET_N + +##============================================================ +# SD CARD +#============================================================ +set_location_assignment PIN_Y17 -to SDCARD_MISO[0] +set_location_assignment PIN_AA18 -to SDCARD_MOSI[0] +set_location_assignment PIN_AA20 -to SDCARD_CLK[0] +set_location_assignment PIN_Y20 -to SDCARD_CS[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0] + +#============================================================ +# SW +#============================================================ + +##============================================================ +# UART +#============================================================ +set_location_assignment PIN_AA14 -to UART_RX_0 +set_location_assignment PIN_AA15 -to UART_TX_0 +set_location_assignment PIN_Y15 -to UART_RX_1 +set_location_assignment PIN_AB18 -to UART_TX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1 + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" + +#============================================================ +# Modules and Files +#============================================================ + +set_global_assignment -name VHDL_FILE ../QMV_zpu_Toplevel.vhd +set_global_assignment -name QIP_FILE Clock_50to100.qip +set_global_assignment -name SDC_FILE QMV_zpu_constraints.sdc +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd +#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd +set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip +#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd +set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip +set_global_assignment -name VHDL_FILE ../devices/WishBone/SRAM/sram.vhd +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF +set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON +set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF + + + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/zpu/build/QMV_zpu_Toplevel.vhd b/zpu/build/QMV_zpu_Toplevel.vhd new file mode 100644 index 0000000..3464451 --- /dev/null +++ b/zpu/build/QMV_zpu_Toplevel.vhd @@ -0,0 +1,175 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.zpu_soc_pkg.all; + +entity QMV_zpu is + port ( + -- Clock + CLOCK_50 : in std_logic; + -- RED LED + LEDR : out std_logic; + -- Debounced keys + KEY : in std_logic; + -- DIP switches + -- SW : in std_logic_vector(3 downto 0); + + -- TDI : in std_logic; + -- TCK : in std_logic; + -- TCS : in std_logic; + -- TDO : out std_logic; + -- I2C_SDAT : inout std_logic; + -- I2C_SCLK : out std_logic; + -- GPIO_0 : inout std_logic_vector(33 downto 0); + -- GPIO_1 : inout std_logic_vector(33 downto 0); + + -- SD Card 1 + SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + + -- UART Serial channels. + UART_RX_0 : in std_logic; + UART_TX_0 : out std_logic; + UART_RX_1 : in std_logic; + UART_TX_1 : out std_logic; + + SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz + SDRAM_CKE : out std_logic; -- clock enable. + SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus + SDRAM_ADDR : out std_logic_vector(11 downto 0); -- 13 bit multiplexed address bus + SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks + SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks + SDRAM_CS : out std_logic; -- a single chip select + SDRAM_WE : out std_logic; -- write enable + SDRAM_RAS : out std_logic; -- row address select + SDRAM_CAS : out std_logic -- columns address select + ); +END entity; + +architecture rtl of QMV_zpu is + + signal reset : std_logic; + signal sysclk : std_logic; + signal memclk : std_logic; + signal pll_locked : std_logic; + + --signal ps2m_clk_in : std_logic; + --signal ps2m_clk_out : std_logic; + --signal ps2m_dat_in : std_logic; + --signal ps2m_dat_out : std_logic; + + --signal ps2k_clk_in : std_logic; + --signal ps2k_clk_out : std_logic; + --signal ps2k_dat_in : std_logic; + --signal ps2k_dat_out : std_logic; + + --alias PS2_MDAT : std_logic is GPIO_1(19); + --alias PS2_MCLK : std_logic is GPIO_1(18); + +begin + +--I2C_SDAT <= 'Z'; +--GPIO_0(33 downto 2) <= (others => 'Z'); +--GPIO_1 <= (others => 'Z'); +--LED <= "101010" & reset & UART_RX_0; +LEDR <= '0'; + +mypll : entity work.Clock_50to100 +port map +( + areset => not KEY, + inclk0 => CLOCK_50, + c0 => sysclk, + c1 => memclk, + locked => pll_locked +); + +reset <= KEY and pll_locked; + +myVirtualToplevel : entity work.zpu_soc +generic map +( + SYSCLK_FREQUENCY => SYSCLK_QMV_FREQ +) +port map +( + SYSCLK => sysclk, + MEMCLK => memclk, + RESET_IN => reset, + + -- RS232 + UART_RX_0 => UART_RX_0, + UART_TX_0 => UART_TX_0, + UART_RX_1 => UART_RX_1, + UART_TX_1 => UART_TX_1, + + -- SPI signals + SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in. + SPI_MOSI => open, + SPI_CLK => open, + SPI_CS => open, + + -- SD Card (SPI) signals + SDCARD_MISO => SDCARD_MISO, + SDCARD_MOSI => SDCARD_MOSI, + SDCARD_CLK => SDCARD_CLK, + SDCARD_CS => SDCARD_CS, + + -- PS/2 signals + PS2K_CLK_IN => '1', + PS2K_DAT_IN => '1', + PS2K_CLK_OUT => open, + PS2K_DAT_OUT => open, + PS2M_CLK_IN => '1', + PS2M_DAT_IN => '1', + PS2M_CLK_OUT => open, + PS2M_DAT_OUT => open, + + -- I²C signals + I2C_SCL_IO => open, + I2C_SDA_IO => open, + + -- IOCTL Bus -- + IOCTL_DOWNLOAD => open, -- Downloading to FPGA. + IOCTL_UPLOAD => open, -- Uploading from FPGA. + IOCTL_CLK => open, -- I/O Clock. + IOCTL_WR => open, -- Write Enable to FPGA. + IOCTL_RD => open, -- Read Enable from FPGA. + IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus. + IOCTL_SELECT => open, -- Enable IOP control over ioctl bus. + IOCTL_ADDR => open, -- Address in FPGA to write into. + IOCTL_DOUT => open, -- Data to be written into FPGA. + IOCTL_DIN => (others => '0'), -- Data to be read into HPS. + + -- SDRAM signals + SDRAM_CLK => SDRAM_CLK, -- sdram is accessed at 128MHz + SDRAM_CKE => SDRAM_CKE, -- clock enable. + SDRAM_DQ => SDRAM_DQ, -- 16 bit bidirectional data bus + SDRAM_ADDR => SDRAM_ADDR, -- 13 bit multiplexed address bus + SDRAM_DQM => SDRAM_DQM, -- two byte masks + SDRAM_BA => SDRAM_BA, -- two banks + SDRAM_CS_n => SDRAM_CS, -- a single chip select + SDRAM_WE_n => SDRAM_WE, -- write enable + SDRAM_RAS_n => SDRAM_RAS, -- row address select + SDRAM_CAS_n => SDRAM_CAS, -- columns address select + SDRAM_READY => open -- sd ready. + + -- DDR2 DRAM - doesnt exist on the QMV. + --DDR2_ADDR => open, -- 14 bit multiplexed address bus + --DDR2_DQ => open, -- 64 bit bidirectional data bus + --DDR2_DQS => open, -- 8 bit bidirectional data bus + --DDR2_DQM => open, -- eight byte masks + --DDR2_ODT => open, -- 14 bit multiplexed address bus + --DDR2_BA => open, -- 8 banks + --DDR2_CS => open, -- 2 chip selects. + --DDR2_WE => open, -- write enable + --DDR2_RAS => open, -- row address select + --DDR2_CAS => open, -- columns address select + --DDR2_CKE => open, -- 2 clock enable. + --DDR2_CLK => open -- 2 clocks. +); + + +end architecture; diff --git a/zpu/build/QMV_zpu_constraints.sdc b/zpu/build/QMV_zpu_constraints.sdc new file mode 100644 index 0000000..7c53f12 --- /dev/null +++ b/zpu/build/QMV_zpu_constraints.sdc @@ -0,0 +1,121 @@ +## Generated SDC file "QMV_zpu.out.sdc" + +## Copyright (C) 2017 Intel Corporation. All rights reserved. +## Your use of Intel Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Intel Program License +## Subscription Agreement, the Intel Quartus Prime License Agreement, +## the Intel FPGA IP License Agreement, or other applicable license +## agreement, including, without limitation, that your use is for +## the sole purpose of programming logic devices manufactured by +## Intel and sold by Intel or its authorized distributors. Please +## refer to the applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus Prime" +## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition" + +## DATE "Sat Jun 22 23:32:00 2019" + +## +## DEVICE "5CEFA2F23C8" +## + + +#************************************************************** +# Time Information +#************************************************************** +set_time_format -unit ns -decimal_places 3 + +#************************************************************** +# Create Clock +#************************************************************** +create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_50}] + +#************************************************************** +# Create Generated Clock +#************************************************************** + +create_generated_clock -name {SYSCLK} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50.000 -multiply_by 2 -divide_by 1 -phase 000 -master_clock {clk_50} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] +create_generated_clock -name {MEMCLK} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50.000 -multiply_by 2 -divide_by 1 -offset -2500 -master_clock {clk_50} [get_pins {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}] + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +derive_clock_uncertainty +#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -setup 0.080 +#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -hold 0.060 +#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -setup 0.080 +#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -hold 0.060 +#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -setup 0.080 +#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -hold 0.060 +#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -setup 0.080 +#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -hold 0.060 + + +#************************************************************** +# Set Input Delay +#************************************************************** + +# Delays for async signals - not necessary, but might as well avoid +# having unconstrained ports in the design +#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}] +#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}] + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + +set_false_path -from [get_keepers {KEY*}] +#set_false_path -from [get_keepers {SW*}] + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -setup -start 1 +#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -hold -start 0 +#set_multicycle_path -setup -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 1 +#set_multicycle_path -hold -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 0 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/zpu/build/ReVerSE-U16.qpf b/zpu/build/ReVerSE-U16.qpf new file mode 100644 index 0000000..03045fb --- /dev/null +++ b/zpu/build/ReVerSE-U16.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition +# Date created = 00:31:03 November 27, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.1" +DATE = "00:31:03 November 27, 2019" + +# Revisions + +PROJECT_REVISION = "ReVerSE-U16" diff --git a/zpu/build/ReVerSE_U16.qpf b/zpu/build/ReVerSE_U16.qpf new file mode 100644 index 0000000..a2b2ab9 --- /dev/null +++ b/zpu/build/ReVerSE_U16.qpf @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "5.0" +DATE = "23:35:58 September 01, 2005" + + +# Revisions + +PROJECT_REVISION = "ReVerSE_U16" diff --git a/zpu/build/ReVerSE_U16.qsf b/zpu/build/ReVerSE_U16.qsf new file mode 100644 index 0000000..41e25c2 --- /dev/null +++ b/zpu/build/ReVerSE_U16.qsf @@ -0,0 +1,211 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# ledwater_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2005" +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" +#set_global_assignment -name VERILOG_FILE ledwater.v +set_global_assignment -name CDF_FILE E115.cdf + +# Pin & Location Assignments +# ========================== + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name TOP_LEVEL_ENTITY ReVerSE_U16 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP4CE22E22C7 +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 + +# Assembler Assignments +# ===================== + +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH + + +#============================================================ +# UART +#============================================================ +set_location_assignment PIN_72 -to UART_RX_0 +set_location_assignment PIN_71 -to UART_TX_0 +#set_location_assignment PIN_C6 -to UART_RX_1 +#set_location_assignment PIN_D7 -to UART_TX_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0 +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1 +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0 +#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1 + +#============================================================ +# SD CARD +#============================================================ +#set_location_assignment PIN_C8 -to SDCARD_MISO[0] +#set_location_assignment PIN_C7 -to SDCARD_MOSI[0] +#set_location_assignment PIN_B8 -to SDCARD_CLK[0] +#set_location_assignment PIN_A8 -to SDCARD_CS[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0] +#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0] +#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0] +#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0] + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_25 -to REVERSEU16_CLOCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to REVERSEU16_CLOCK +#set_location_assignment PIN_AB11 -to clk_25M + +#============================================================ +# LED +#============================================================ +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +#set_location_assignment PIN_A5 -to LED[0] +#set_location_assignment PIN_B5 -to LED[1] +#set_location_assignment PIN_C4 -to LED[2] +#set_location_assignment PIN_C3 -to LED[3] + + +set_location_assignment PIN_32 -to reset_button +set_location_assignment PIN_98 -to SDRAM_ADDR[0] +set_location_assignment PIN_86 -to SDRAM_ADDR[1] +set_location_assignment PIN_87 -to SDRAM_ADDR[2] +set_location_assignment PIN_105 -to SDRAM_ADDR[3] +set_location_assignment PIN_76 -to SDRAM_ADDR[4] +set_location_assignment PIN_77 -to SDRAM_ADDR[5] +set_location_assignment PIN_80 -to SDRAM_ADDR[6] +set_location_assignment PIN_83 -to SDRAM_ADDR[7] +set_location_assignment PIN_85 -to SDRAM_ADDR[8] +set_location_assignment PIN_67 -to SDRAM_ADDR[9] +set_location_assignment PIN_99 -to SDRAM_ADDR[10] +set_location_assignment PIN_69 -to SDRAM_ADDR[11] +set_location_assignment PIN_68 -to SDRAM_ADDR[12] +set_location_assignment PIN_101 -to SDRAM_BA[0] +set_location_assignment PIN_100 -to SDRAM_BA[1] +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PIN_119 -to SDRAM_DQM[0] +set_location_assignment PIN_66 -to SDRAM_DQM[1] +set_location_assignment PIN_142 -to SDRAM_DQ[0] +set_location_assignment PIN_141 -to SDRAM_DQ[1] +set_location_assignment PIN_137 -to SDRAM_DQ[2] +set_location_assignment PIN_136 -to SDRAM_DQ[3] +set_location_assignment PIN_135 -to SDRAM_DQ[4] +set_location_assignment PIN_125 -to SDRAM_DQ[5] +set_location_assignment PIN_121 -to SDRAM_DQ[6] +set_location_assignment PIN_120 -to SDRAM_DQ[7] +set_location_assignment PIN_65 -to SDRAM_DQ[8] +set_location_assignment PIN_64 -to SDRAM_DQ[9] +set_location_assignment PIN_60 -to SDRAM_DQ[10] +set_location_assignment PIN_46 -to SDRAM_DQ[11] +set_location_assignment PIN_44 -to SDRAM_DQ[12] +set_location_assignment PIN_59 -to SDRAM_DQ[13] +set_location_assignment PIN_42 -to SDRAM_DQ[14] +set_location_assignment PIN_58 -to SDRAM_DQ[15] +set_location_assignment PIN_106 -to SDRAM_nCAS +set_location_assignment PIN_103 -to SDRAM_nRAS +set_location_assignment PIN_104 -to SDRAM_nWE + +#============================================================ +# Modules and Files +#============================================================ + +set_global_assignment -name VHDL_FILE ../ReVerSE_U16_Toplevel.vhd +set_global_assignment -name QIP_FILE Clock_25to100.qip +set_global_assignment -name SDC_FILE ReVerSE_U16_constraints.sdc +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd +set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd +set_global_assignment -name VHDL_FILE ../zpu_soc.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd +set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd +#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd +set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/sdram.qip +#set_global_assignment -name VHDL_FILE ../devices/sysbus/SDRAM/sdram.vhd +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd +set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd +#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/wbsdram.qip +set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/wbsdram.vhd +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF +set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON +set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3 + +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/zpu/build/ReVerSE_U16_Toplevel.vhd b/zpu/build/ReVerSE_U16_Toplevel.vhd new file mode 100644 index 0000000..ff186ac --- /dev/null +++ b/zpu/build/ReVerSE_U16_Toplevel.vhd @@ -0,0 +1,165 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.zpu_soc_pkg.all; + +entity ReVerSE_U16 is + port ( + -- Clock + REVERSEU16_CLOCK: in std_logic; + -- + reset_button : in std_logic; + -- LED + --LED : out std_logic_vector(7 downto 0); + -- Debounced keys + --KEY : in std_logic_vector(1 downto 0); + -- DIP switches + --SW : in std_logic_vector(3 downto 0); + + -- TDI : in std_logic; + -- TCK : in std_logic; + -- TCS : in std_logic; + -- TDO : out std_logic; + -- I2C_SDAT : inout std_logic; + -- I2C_SCLK : out std_logic; + -- GPIO_0 : inout std_logic_vector(33 downto 0); + -- GPIO_1 : inout std_logic_vector(33 downto 0); + + -- SD Card 1 + SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + + -- UART Serial channels. + UART_RX_0 : in std_logic; + UART_TX_0 : out std_logic + --UART_RX_1 : in std_logic; + --UART_TX_1 : out std_logic + + -- DDR2 DRAM + --DDR2_ADDR : out std_logic_vector(13 downto 0); -- 14 bit multiplexed address bus + --DDR2_DQ : inout std_logic_vector(63 downto 0); -- 64 bit bidirectional data bus + --DDR2_DQS : inout std_logic_vector(7 downto 0); -- 8 bit bidirectional data bus + --DDR2_DQM : out std_logic_vector(17 downto 0); -- eight byte masks + --DDR2_ODT : out std_logic_vector(1 downto 0); -- 14 bit multiplexed address bus + --DDR2_BA : out std_logic_vector(2 downto 0); -- 8 banks + --DDR2_CS : out std_logic_vector(1 downto 0); -- 2 chip selects. + --DDR2_WE : out std_logic; -- write enable + --DDR2_RAS : out std_logic; -- row address select + --DDR2_CAS : out std_logic; -- columns address select + --DDR2_CKE : out std_logic_vector(1 downto 0); -- 2 clock enable. + --DDR2_CLK : out std_logic_vector(1 downto 0) -- 2 clocks. + ); +END entity; + +architecture rtl of ReVerSE_U16 is + + signal reset : std_logic; + signal sysclk : std_logic; + signal memclk : std_logic; + signal pll_locked : std_logic; + + --signal ps2m_clk_in : std_logic; + --signal ps2m_clk_out : std_logic; + --signal ps2m_dat_in : std_logic; + --signal ps2m_dat_out : std_logic; + + --signal ps2k_clk_in : std_logic; + --signal ps2k_clk_out : std_logic; + --signal ps2k_dat_in : std_logic; + --signal ps2k_dat_out : std_logic; + + --alias PS2_MDAT : std_logic is GPIO_1(19); + --alias PS2_MCLK : std_logic is GPIO_1(18); + +begin + +--I2C_SDAT <= 'Z'; +--GPIO_0(33 downto 2) <= (others => 'Z'); +--GPIO_1 <= (others => 'Z'); +--LED <= "101010" & reset & UART_RX_0; +--LED <= "00000000"; + +mypll : entity work.Clock_25to100 +port map +( + inclk0 => REVERSEU16_CLOCK, + c0 => sysclk, + c1 => memclk, + locked => pll_locked +); + +reset <= reset_button or pll_locked; + +myVirtualToplevel : entity work.zpu_soc +generic map +( + SYSCLK_FREQUENCY => SYSCLK_E115_FREQ +) +port map +( + SYSCLK => sysclk, + MEMCLK => memclk, + RESET_IN => reset, + + -- RS232 + UART_RX_0 => UART_RX_0, + UART_TX_0 => UART_TX_0, + UART_RX_1 => '0', + UART_TX_1 => open, + + -- SPI signals + SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in. + SPI_MOSI => open, + SPI_CLK => open, + SPI_CS => open, + + -- SD Card (SPI) signals + SDCARD_MISO => SDCARD_MISO, + SDCARD_MOSI => SDCARD_MOSI, + SDCARD_CLK => SDCARD_CLK, + SDCARD_CS => SDCARD_CS, + + -- PS/2 signals + PS2K_CLK_IN => '1', + PS2K_DAT_IN => '1', + PS2K_CLK_OUT => open, + PS2K_DAT_OUT => open, + PS2M_CLK_IN => '1', + PS2M_DAT_IN => '1', + PS2M_CLK_OUT => open, + PS2M_DAT_OUT => open, + + -- I²C signals + I2C_SCL_IO => open, + I2C_SDA_IO => open, + + -- IOCTL Bus -- + IOCTL_DOWNLOAD => open, -- Downloading to FPGA. + IOCTL_UPLOAD => open, -- Uploading from FPGA. + IOCTL_CLK => open, -- I/O Clock. + IOCTL_WR => open, -- Write Enable to FPGA. + IOCTL_RD => open, -- Read Enable from FPGA. + IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus. + IOCTL_SELECT => open, -- Enable IOP control over ioctl bus. + IOCTL_ADDR => open, -- Address in FPGA to write into. + IOCTL_DOUT => open, -- Data to be written into FPGA. + IOCTL_DIN => (others => '0'), -- Data to be read into HPS. + + -- SDRAM signals which do not exist on the E115 + SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz + SDRAM_CKE => open, --SDRAM_CKE, -- clock enable. + SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus + SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus + SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks + SDRAM_BA => open, --SDRAM_BA, -- two banks + SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select + SDRAM_WE_n => open, --SDRAM_WE, -- write enable + SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select + SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select + SDRAM_READY => open -- sd ready. +); + + +end architecture; diff --git a/zpu/build/clean.sh b/zpu/build/clean.sh new file mode 100755 index 0000000..7010966 --- /dev/null +++ b/zpu/build/clean.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +rm -fr c5_pin_model_dump.txt ./db DE10_nano_zpu.asm.rpt DE10_nano_zpu.done DE10_nano_zpu.fit.rpt DE10_nano_zpu.fit.smsg DE10_nano_zpu.fit.summary DE10_nano_zpu.flow.rpt DE10_nano_zpu.jdi DE10_nano_zpu.map.rpt DE10_nano_zpu.map.smsg DE10_nano_zpu.map.summary DE10_nano_zpu.pin DE10_nano_zpu.rbf DE10_nano_zpu.sld DE10_nano_zpu.sof DE10_nano_zpu.sta.rpt DE10_nano_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt +rm -fr c5_pin_model_dump.txt ./db E115_zpu.asm.rpt E115_zpu.done E115_zpu.fit.rpt E115_zpu.fit.smsg E115_zpu.fit.summary E115_zpu.flow.rpt E115_zpu.jdi E115_zpu.map.rpt E115_zpu.map.smsg E115_zpu.map.summary E115_zpu.pin E115_zpu.rbf E115_zpu.sld E115_zpu.sof E115_zpu.sta.rpt E115_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt E115_zpu.pof diff --git a/zpu/build/ddd b/zpu/build/ddd new file mode 100644 index 0000000..e0f6620 --- /dev/null +++ b/zpu/build/ddd @@ -0,0 +1,617 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: sdram.vhd +-- Created: September 2019 +-- Original Author: Stephen J. Leary 2013-2014 +-- VHDL Author: Philip Smart +-- Description: Original verilog module written by Stephen J. Leary 2013-2014 for the Archimedes +-- emulator with the MT48LC16M16 chip. +-- The verilog has been translated into VHDL and adapted for both the system bus and +-- the Wishbone bus undergoing extensive modifications to work with the ZPU EVO processor, +-- specifically parameterisation and burst tuning to enhance L2 Cache Fill performance. +-- Credits: +-- Copyright: Copyright (c) 2013-2014, Stephen J. Leary, All rights reserved. +-- VHDL translation, sysbus adaptation and enhancements (c) 2019 Philip Smart +-- +-- +-- History: September 2019 - Initial module translation to VHDL based on Stephen J. Leary's Verilog +-- source code. +-- November 2019 - Adapted for the system bus for use when no Wishbone interface is +-- instantiated in the ZPU Evo. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_soc_pkg.all; +use work.zpu_pkg.all; + +entity SDRAM is + generic ( + MAX_DATACACHE_BITS : integer := 4; -- Maximum size in addr bits of 32bit datacache for burst transactions. + SDRAM_ROWS : integer := 4096; -- Number of Rows in the SDRAM. + SDRAM_COLUMNS : integer := 256; -- Number of Columns in an SDRAM page (ie. 1 row). + SDRAM_BANKS : integer := 4; -- Number of banks in the SDRAM. + SDRAM_DATAWIDTH : integer := 16; -- Data width of SDRAM chip (ie. 16, 32). + SDRAM_CLK_FREQ : integer := 100000000; -- Frequency of the SDRAM clock in Hertz. + SDRAM_tRCD : integer := 2; -- tRCD - RAS to CAS minimum period (in ns), ie. 20ns -> 2 cycles@100MHz + SDRAM_tRP : integer := 2; -- tRP - Precharge delay, min time for a precharge command to complete (in ns), ie. 15ns -> 2 cycles@100MHz + SDRAM_tRFC : integer := 70; -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns + SDRAM_tREF : integer := 64 -- tREF - period of time a complete refresh of all rows is made within (in ms). + ); + port ( + -- SDRAM Interface + SDRAM_CLK : in std_logic; -- SDRAM is accessed at given clock, frequency specified in RAM_CLK. + SDRAM_RST : in std_logic; -- Reset the sdram controller. + SDRAM_CKE : out std_logic; -- Clock enable. + SDRAM_DQ : inout std_logic_vector(SDRAM_DATAWIDTH-1 downto 0); -- Bidirectional data bus + SDRAM_ADDR : out std_logic_vector(log2ceil(SDRAM_ROWS) - 1 downto 0); -- Multiplexed address bus + SDRAM_DQM : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of byte masks dependent on number of banks. + SDRAM_BA : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of banks in SDRAM + SDRAM_CS_n : out std_logic; -- Single chip select + SDRAM_WE_n : out std_logic; -- Write enable + SDRAM_RAS_n : out std_logic; -- Row address select + SDRAM_CAS_n : out std_logic; -- Columns address select + SDRAM_READY : out std_logic; -- SD ready. + + -- CPU Interface + CLK : in std_logic; -- System master clock + RESET : in std_logic; -- High active sync reset + ADDR : in std_logic_vector(log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS) downto 0); + DATA_IN : in std_logic_vector(WORD_32BIT_RANGE); -- Write data + DATA_OUT : out std_logic_vector(WORD_32BIT_RANGE); -- Read data + WRITE_BYTE : in std_logic; -- Write a single byte as specified in A1:A0 + WRITE_HWORD : in std_logic; -- Write a 16bit word as specified in A1 + CS : in std_logic; -- Chip Select. + WREN : in std_logic; -- Write enable. + RDEN : in std_logic; -- Read enable. + BUSY : out std_logic -- Memory is busy, hold CPU. + ); +end SDRAM; + +architecture Structure of SDRAM is + + -- Constants to define the structure of the SDRAM in bits for provisioning of signals. + constant SDRAM_ROW_BITS : integer := log2ceil(SDRAM_ROWS); + constant SDRAM_COLUMN_BITS : integer := log2ceil(SDRAM_COLUMNS); + constant SDRAM_ARRAY_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS); + constant SDRAM_BANK_BITS : integer := log2ceil(SDRAM_BANKS); + constant SDRAM_ADDR_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS); + + -- Command table for a standard SDRAM. + -- + -- Name (Function) CKE CS# RAS# CAS# WE# DQM ADDR DQ + -- COMMAND INHIBIT (NOP) H H X X X X X X + -- NO OPERATION (NOP) H L H H H X X X + -- ACTIVE (select bank and activate row) H L L H H X Bank/row X + -- READ (select bank and column, and start READ burst) H L H L H L/H Bank/col X + -- WRITE (select bank and column, and start WRITE burst) H L H L L L/H Bank/col Valid + -- BURST TERMINATE H L H H L X X Active + -- PRECHARGE (Deactivate row in bank or banks) H L L H L X Code X + -- AUTO REFRESH or SELF REFRESH (enter self refresh mode) H L L L H X X X + -- LOAD MODE REGISTER H L L L L X Op-code X + -- Write enable/output enable H X X X X L X Active + -- Write inhibit/output High-Z H X X X X H X High-Z + -- Self Refresh Entry L L L L H X X X + -- Self Refresh Exit (Device is idle) H H X X X X X X + -- Self Refresh Exit (Device is in Self Refresh state) H L H H X X X X + -- Clock suspend mode Entry L X X X X X X X + -- Clock suspend mode Exit H X X X X X X X + -- Power down mode Entry (Device is idle) L H X X X X X X + -- Power down mode Entry (Device is Active) L L H H X X X X + -- Power down mode Exit (Any state) H H X X X X X X + -- Power down mode Exit (Device is powered down) H L H H X X X X + + constant CMD_INHIBIT : std_logic_vector(4 downto 0) := "11111"; + constant CMD_NOP : std_logic_vector(4 downto 0) := "10111"; + constant CMD_ACTIVE : std_logic_vector(4 downto 0) := "10011"; + constant CMD_READ : std_logic_vector(4 downto 0) := "10101"; + constant CMD_WRITE : std_logic_vector(4 downto 0) := "10100"; + constant CMD_BURST_TERMINATE : std_logic_vector(4 downto 0) := "10110"; + constant CMD_PRECHARGE : std_logic_vector(4 downto 0) := "10010"; + constant CMD_AUTO_REFRESH : std_logic_vector(4 downto 0) := "10001"; + constant CMD_LOAD_MODE : std_logic_vector(4 downto 0) := "10000"; + constant CMD_SELF_REFRESH_START : std_logic_vector(4 downto 0) := "00001"; + constant CMD_SELF_REFRESH_END : std_logic_vector(4 downto 0) := "10110"; + constant CMD_CLOCK_SUSPEND : std_logic_vector(4 downto 0) := "00000"; + constant CMD_CLOCK_RESTORE : std_logic_vector(4 downto 0) := "10000"; + constant CMD_POWER_DOWN : std_logic_vector(4 downto 0) := "01000"; + constant CMD_POWER_RESTORE : std_logic_vector(4 downto 0) := "01100"; + + -- Load Mode Register setting for a standard SDRAM. + -- + -- xx:10 = Reserved : + -- 9 = Write Burst Mode : 0 = Programmed Burst Length, 1 = Single Location Access + -- 8:7 = Operating Mode : 00 = Standard Operation, all other values reserved. + -- 6:4 = CAS Latency : 010 = 2, 011 = 3, all other values reserved. + -- 3 = Burst Type : 0 = Sequential, 1 = Interleaved. + -- 2:0 = Burst Length : When 000 = 1, 001 = 2, 010 = 4, 011 = 8, all others reserved except 111 when BT = 0 sets full page access. + -- | A12-A10 | A9  A8-A7 | A6 A5 A4 | A3  A2 A1 A0 | + -- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len| + constant WRITE_BURST_MODE : std_logic := '1'; + constant OP_MODE : std_logic_vector(1 downto 0) := "00"; + constant CAS_LATENCY : std_logic_vector(2 downto 0) := "011"; + constant BURST_TYPE : std_logic := '0'; + constant BURST_LENGTH : std_logic_vector(2 downto 0) := "000"; + constant MODE : std_logic_vector(SDRAM_ROW_BITS-1 downto 0) := std_logic_vector(to_unsigned(to_integer(unsigned("00" & WRITE_BURST_MODE & OP_MODE & CAS_LATENCY & BURST_TYPE & BURST_LENGTH)), SDRAM_ROW_BITS)); + + -- FSM Cycle States governed in units of time, the state changes location according to the configurable parameters to ensure correct actuation at the correct time. + -- + constant CYCLE_PRECHARGE : integer := 0; -- 0 + constant CYCLE_RAS_START : integer := tRP; -- 3 + constant CYCLE_RAS_NEXT : integer := CYCLE_RAS_START + 1; -- 4 + constant CYCLE_CAS0 : integer := CYCLE_RAS_START + tRCD; -- 3 + tRCD + constant CYCLE_CAS1 : integer := CYCLE_CAS0 + 1; -- 4 + tRCD + constant CYCLE_READ0 : integer := CYCLE_CAS0 + to_integer(unsigned(CAS_LATENCY)) + 1; -- 3 + tRCD + CAS_LATENCY + constant CYCLE_READ1 : integer := CYCLE_READ0 + 1; -- 4 + tRCD + CAS_LATENCY + constant CYCLE_END : integer := CYCLE_READ1 + 1; -- 9 + tRCD + CAS_LATENCY + constant CYCLE_RFSH_START : integer := tRP; -- tRP + constant CYCLE_RFSH_END : integer := CYCLE_RFSH_START + ((tRFC/SDRAM_CLK_FREQ) * 10000000) + tRP + 1; -- tRP (start) + tRFC (min autorefresh time) + tRP (end) in clock ticks. + + -- Period in clock cycles between SDRAM refresh cycles. This equates to tREF / SDRAM_ROWS to evenly divide the time, then subtract the length of the refresh period as this is + -- the time it takes when a refresh starts to completion. + constant REFRESH_PERIOD : integer := (((tREF * SDRAM_CLK_FREQ ) / SDRAM_ROWS) - (tRFC * 1000)) / 1000; + + type BankArray is array(natural range 0 to 3) of std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + + -- Cache for holding burst reads to allow for differing speeds of WishBone Master. + type DataCacheArray is array(natural range 0 to ((2**(MAX_DATACACHE_BITS))-1)) of std_logic_vector(WORD_32BIT_RANGE); + signal readCache : DataCacheArray; + attribute ramstyle : string; + attribute ramstyle of readCache : signal is "logic"; + signal cacheReadAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0); + signal cacheWriteAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0); + + -- SDRAM domain signals. + signal sdCycle : integer range 0 to 31; + signal sdDone : std_logic; + signal sdCmd : std_logic_vector(4 downto 0); + signal sdRefreshCount : unsigned(11 downto 0); + signal sdAutoRefresh : std_logic; + signal sdResetTimer : unsigned(7 downto 0); + signal sdMuxAddr : std_logic_vector(SDRAM_ROW_BITS-1 downto 0); -- 12+ bit multiplexed address bus + signal sdDoneLast : std_logic; + signal sdInResetCounter : unsigned(7 downto 0); + signal isReady : std_logic; + signal sdDataOut : std_logic_vector(SDRAM_DATAWIDTH-1 downto 0); + signal sdDataIn : std_logic_vector(SDRAM_DATAWIDTH-1 downto 0); + signal sdActiveRow : BankArray; + signal sdActiveBank : std_logic_vector(1 downto 0); + signal cpuBank : natural range 0 to 3; + signal cpuRow : std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + signal cpuCol : std_logic_vector(SDRAM_COLUMN_BITS-1 downto 0); + signal sdDQM : std_logic_vector(1 downto 0); + + -- CPU domain signals. + signal cpuBusy : std_logic; + signal cpuDQM : std_logic_vector(3 downto 0); + signal cpuDataOut : std_logic_vector(WORD_32BIT_RANGE); + signal cpuDataIn : std_logic_vector(WORD_32BIT_RANGE); + signal cpuIsWriting : std_logic; + + signal cpuReq : std_logic; + signal cpuLastEN : std_logic; + signal sdReqLast : std_logic; + signal sdAck : std_logic; + signal cpuDoneAck : std_logic; + + type ramArray is array(natural range 0 to SDRAM_COLUMNS) of std_logic_vector(WORD_32BIT_RANGE); + type ramCtrl is array(0 downto 0) of std_logic_vector(SDRAM_ADDR_BITS downto 0); + + shared variable READRAM : ramArray := + ( + others => X"00000000" + ); + + shared variable WRITERAM : ramArray := + ( + others => X"00000000" + ); + shared variable WRITECTRL : ramCtrl := + ( + others => (others => '0') + ); + shared variable READCTRL : ramCtrl := + ( + others => (others => '0') + ); + + signal cpuReadFifoBlockAddr : std_logic_vector(SDRAM_ADDR_BITS-1 downto SDRAM_COLUMNS); + signal sdReadFifoBlockAddr : std_logic_vector(SDRAM_ADDR_BITS-1 downto SDRAM_COLUMNS); + signal fifoSdWREN : std_logic; + signal fifoCpuWREN : std_logic; + + +begin + + -- Tri-state control of the SDRAM data bus. +-- process(cpuIsWriting, SDRAM_DQ, sdDataOut) +-- begin +-- if (cpuIsWriting = '1') then +-- SDRAM_DQ <= sdDataOut; +-- sdDataIn <= SDRAM_DQ; +-- else +-- SDRAM_DQ <= (others => 'Z'); +-- sdDataIn <= SDRAM_DQ; +-- end if; +-- end process; + + -- SDRAM Side of dual port RAM. + -- For Read: sdDataOut <= FIFO(sdFifoAddr) + -- For WriteL FIFO(sdFifoAddr) <= sdDataIn +-- process(SDRAM_CLK) +-- begin +-- if rising_edge(SDRAM_CLK) then +-- if fifoSdWREN = '1' then +-- FIFO(to_integer(unsigned(sdWriteColumnAddr(SDRAM_COLUMNS-1 downto 0)))) := sdDataIn; +-- sdDataOut(WORD_32BIT_RANGE) <= sdDataIn; +-- else +-- sdDataOut(WORD_32BIT_RANGE) <= FIFO(to_integer(unsigned(sdReadColumnAddr(SDRAM_COLUMN-1 downto 0)))); +-- end if; +-- end if; +-- end process; + + -- Main FSM for SDRAM control and refresh. + process(ALL) + begin + if (cpuIsWriting = '1') then + SDRAM_DQ <= sdDataOut; + else + SDRAM_DQ <= (others => 'Z'); + end if; + sdDataIn <= SDRAM_DQ; + + if (SDRAM_RST = '1') then + sdResetTimer <= (others => '0'); -- 0 upto 127 + sdInResetCounter <= (others => '1'); -- 255 downto 0 + sdMuxAddr <= (others => '0'); + sdAutoRefresh <= '0'; + sdRefreshCount <= (others => '0'); + sdActiveBank <= (others => '0'); + sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0')); + isReady <= '0'; + sdCmd <= CMD_AUTO_REFRESH; + SDRAM_DQM <= (others => '1'); + sdCycle <= 0; + sdDone <= '0'; + cacheWriteAddr <= (others => '0'); + sdAck <= '0'; + sdReqLast <= '0'; + + elsif rising_edge(SDRAM_CLK) then + + -- If no specific command given the default is NOP. + sdCmd <= CMD_NOP; + + -- Initialisation on power up or reset. The SDRAM must be given at least 200uS to initialise and a fixed setup pattern applied. + if (isReady = '0') then + sdResetTimer <= sdResetTimer + 1; + + -- 1uS timer. + if (sdResetTimer = SDRAM_CLK_FREQ/1000000) then + sdResetTimer <= (others => '0'); + sdInResetCounter <= sdInResetCounter - 1; + end if; + + -- Every 1uS check for the next init action. + if (sdResetTimer = 0) then + + -- 200uS wait, no action as the SDRAM starts up. + -- ie. 255 downto 55 + + -- Precharge all banks + if(sdInResetCounter = 55) then + sdCmd <= CMD_PRECHARGE; + SDRAM_ADDR(10) <= '1'; + end if; + + -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after + -- the other. + if(sdInResetCounter >= 40 and sdInResetCounter <= 48) then + sdCmd <= CMD_AUTO_REFRESH; + end if; + + -- Load the Mode register with our parameters. + if(sdInResetCounter = 39) then + sdCmd <= CMD_LOAD_MODE; + SDRAM_ADDR <= MODE; + end if; + + -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after + -- the other. + if(sdInResetCounter >= 30 and sdInResetCounter <= 38) then + sdCmd <= CMD_AUTO_REFRESH; + end if; + + -- SDRAM ready. + if(sdInResetCounter = 20) then + isReady <= '1'; + end if; + end if; + + else + + -- Counter to the next auto-refresh in sdram clock ticks. + sdRefreshCount <= sdRefreshCount + 1; + + -- Store the CPU request signal state to detect a change. + sdReqLast <= cpuReq; + + -- If the CPU makes an SDRAM request and we arent already processing, acknowledge it. + -- This mechanism is used to reduce the possibility of metastability issues due to differing clocks. + if ((sdReqLast = '0' and cpuReq = '1') and sdAck = '0') then + sdAck <= '1'; + end if; + + -- If the CPU completes its request because it detects the SDRAM ACK, remove the ACK signal as it is no longer needed. + if ((sdReqLast = '1' and cpuReq = '0') and sdAck = '1') then + sdAck <= '0'; + end if; + + -- If the SDRAM has completed its transaction and the CPU has acknowledged it, remove the signals. + if (sdDone = '1' and cpuDoneAck = '1') then + sdDone <= '0'; + end if; + + -- Auto refresh. On timeout it kicks in so that ROWS auto refreshes are + -- issued in a tRFC period. Other bus operations are stalled during this period. + if (sdRefreshCount > REFRESH_PERIOD and sdCycle = 0) then + sdAutoRefresh <= '1'; + sdRefreshCount <= (others => '0'); + sdCmd <= CMD_PRECHARGE; + SDRAM_ADDR(10) <= '1'; + sdActiveBank <= (others => '0'); + sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0')); + + -- In auto refresh period. + elsif (sdAutoRefresh = '1') then + + -- while the cycle is active count. + sdCycle <= sdCycle + 1; + case (sdCycle) is + when CYCLE_RFSH_START => + sdCmd <= CMD_AUTO_REFRESH; + + when CYCLE_RFSH_END => + -- reset the count. + sdAutoRefresh <= '0'; + sdCycle <= 0; + + when others => + end case; + + -- If we are not acknowledging a CPU request (and signals to stabilize and latch), run the FSM to refresh or service a request. + elsif sdAck = '0' then +-- if sdAck = '0' then + + if ((cpuBusy = '1' and sdCycle = 0) or sdCycle /= 0) then -- or (sdCycle = 0 and CS = '1')) then + + -- while the cycle is active count. + sdCycle <= sdCycle + 1; + case (sdCycle) is + + when CYCLE_PRECHARGE => + -- If the bank is not open then no need to precharge, move onto RAS. + if (sdActiveBank(cpuBank) = '0') then + sdCycle <= CYCLE_RAS_START; + + -- If the requested row is already active, go to CAS for immediate access to this row. + elsif (sdActiveRow(cpuBank) = cpuRow) then + sdCycle <= CYCLE_CAS0; + + -- Otherwise we close out the open bank by issuing a PRECHARGE. + else + sdCmd <= CMD_PRECHARGE; + SDRAM_ADDR(10) <= '0'; + SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); + sdActiveBank(cpuBank) <= '0'; -- Store flag to indicate which bank is being made active. + end if; + + -- Open the requested row. + when CYCLE_RAS_START => + sdCmd <= CMD_ACTIVE; + SDRAM_ADDR <= cpuRow; -- Addr presented to SDRAM as row address. + SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Addr presented to SDRAM as bank select. + sdActiveRow(cpuBank) <= cpuRow; -- Store number of row being made active + sdActiveBank(cpuBank) <= '1'; -- Store flag to indicate which bank is being made active. + + when CYCLE_RAS_NEXT => + SDRAM_DQM <= "11"; -- Set DQ to tri--state. + + -- this is the first CAS cycle + when CYCLE_CAS0 => + -- Process on a 32bit boundary, this core is originally intended for a a 16bit chip so we need 2 accesses for a 32bit alignment, for a 32bit chip, remove CAS1 (TODO: Auto enable logic based on datawidth). + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge + -- SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Ensure bank is the correct one opened. + + SDRAM_DQM <= not cpuDQM(3 downto 2); + sdDataOut <= cpuDataIn((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH); -- Assign corresponding data to the SDRAM databus. + -- If writing, setup for a write with preset mask. + if (cpuIsWriting = '1') then + sdCmd <= CMD_WRITE; + else + -- Setup for a read. + sdCmd <= CMD_READ; + SDRAM_DQM <= "00"; -- For reads dont mask the data output. + end if; + + when CYCLE_CAS1 => + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '1')), SDRAM_ROW_BITS)); -- CAS address = Next address accessing second 16bit location within the 32bit external alignment with no auto precharge + -- SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Ensure bank is the correct one opened. + + SDRAM_DQM <= not cpuDQM(1 downto 0); + sdDataOut <= cpuDataIn(SDRAM_DATAWIDTH-1 downto 0); + -- If writing, setup for a write with preset mask. + if (cpuIsWriting = '1') then + sdCmd <= CMD_WRITE; + -- sdDone <= '1'; --not sdDone; + sdCycle <= CYCLE_END; + else + -- Setup for a read, change to write if flag set. + sdCmd <= CMD_READ; + SDRAM_DQM <= "00"; -- For reads dont mask the data output. + end if; + + -- Data is available CAS Latency clocks after the read request. + when CYCLE_READ0 => + -- If writing, then we are complete, exit else read the first word. + if (cpuIsWriting = '1') then + sdCycle <= CYCLE_END; + else + cpuDataOut((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH) <= sdDataIn; + end if; + + when CYCLE_READ1 => + -- If writing, then we are complete, exit else read the first word. + if (cpuIsWriting = '1') then + sdCycle <= CYCLE_END; + else + cpuDataOut(SDRAM_DATAWIDTH-1 downto 0) <= sdDataIn; + end if; + + when CYCLE_END => + sdDone <= '1'; --not sdDone; + sdCycle <= 0; + + -- Other states are wait states, waiting for the correct time slot for SDRAM access. + when others => + end case; + else + sdCycle <= 0; + end if; + end if; + end if; + end if; + end process; + + -- CPU Side of dual port RAM. + -- For Read: cpuDataOut <= FIFO(cpuFifoAddr) + -- For Write: FIFO(cpuFifoAddr) <= cpuDataIn +-- process(CLK) +-- begin +-- if rising_edge(CLK) then +-- if fifoCpuWREN = '1' then +-- FIFO(to_integer(unsigned(cpuWriteColumnAddr(SDRAM_COLUMNS-1 downto 0)))) := cpuDataIn; +-- cpuDataOut(WORD_32BIT_RANGE) <= cpuDataIn; +-- else +-- cpuDataOut(WORD_32BIT_RANGE) <= FIFO(to_integer(unsigned(cpuReadColumnAddr(SDRAM_COLUMN-1 downto 0)))); +-- end if; +-- end if; +-- end process; + + -- CPU/BUS side logic. When the CPU initiates a transaction, capture the signals and the captured values are used within the SDRAM domain. This is to prevent + -- any changes CPU side or differing signal lengths due to CPU architecture or clock being propogated into the SDRAM domain. The CPU only needs to know + -- when the transation is complete and data read. + -- + process(ALL) + begin + if (RESET = '1') then + sdDoneLast <= '0'; + cpuBusy <= '0'; + cpuBank <= 0; + cpuRow <= (others => '0'); + cpuCol <= (others => '0'); + cpuDQM <= (others => '1'); + cpuDoneAck <= '0'; + cpuReq <= '0'; + cpuLastEN <= '0'; + + -- If the SDRAM isnt ready, we can only wait. + elsif isReady = '0' then + + elsif rising_edge(CLK) then + + -- Preserve current enable state to detect activation. + cpuLastEN <= RDEN or WREN; + + -- Detect a Chip Select state change signalling access. + if cpuLastEN = '0' and (RDEN = '1' or WREN = '1') then + cpuBusy <= '1'; + cpuIsWriting <= WREN; + cpuBank <= to_integer(unsigned(ADDR(SDRAM_ADDR_BITS downto SDRAM_ARRAY_BITS+1))); + cpuRow <= std_logic_vector(to_unsigned(to_integer(unsigned(ADDR(SDRAM_ARRAY_BITS downto SDRAM_COLUMN_BITS+1))), SDRAM_ROW_BITS)); + cpuCol <= ADDR(SDRAM_COLUMN_BITS downto 2) & '0'; + cpuReq <= '1'; + + -- Preset the write selects according to the CPU signals. Let Quartus optimize as easier to read seeing all mask values. + if(WRITE_BYTE = '1') then + case ADDR(1 downto 0) is + when "00" => cpuDQM <= "1000"; + cpuDataIn <= DATA_IN(7 downto 0) & X"000000"; + when "01" => cpuDQM <= "0100"; + cpuDataIn <= X"00" & DATA_IN(7 downto 0) & X"0000"; + when "10" => cpuDQM <= "0010"; + cpuDataIn <= X"0000" & DATA_IN(7 downto 0) & X"00"; + when "11" => cpuDQM <= "0001"; + cpuDataIn <= X"000000" & DATA_IN(7 downto 0); + when others => + end case; + + elsif(WRITE_HWORD = '1') then + + case ADDR(1) is + when '0' => cpuDQM <= "1100"; + cpuDataIn <= DATA_IN(15 downto 0) & X"0000"; + when '1' => cpuDQM <= "0011"; + cpuDataIn <= X"0000" & DATA_IN(15 downto 0); + end case; + + else + -- Reads are always 32bit wide and if no part word signal is asserted, writes are 32bit. + cpuDataIn <= DATA_IN(31 downto 0); + cpuDQM <= "1111"; + end if; + end if; + + if cpuReq = '1' and sdAck = '1' then + cpuReq <= '0'; + end if; + + -- Note SDRAM activity via a previous/last signal. + sdDoneLast <= sdDone; + + -- If there has been a change in the SDRAM done activity reset the signals as initiated transaction is complete. + if (sdDoneLast = '0' and sdDone = '1') then + cpuDoneAck <= '1'; + end if; + + if (sdDoneLast = '1' and sdDone = '0' and cpuDoneAck = '1') then + cpuDoneAck <= '0'; + cpuBusy <= '0'; + end if; + + end if; + end process; + + -- Assign stored data to the CPU bus to be read. + DATA_OUT <= cpuDataOut; + + -- drive control signals according to current command + SDRAM_CKE <= sdCmd(4); + SDRAM_CS_n <= sdCmd(3); + SDRAM_RAS_n <= sdCmd(2); + SDRAM_CAS_n <= sdCmd(1); + SDRAM_WE_n <= sdCmd(0); +-- SDRAM_DQM <= sdDQM; + -- SDRAM_ADDR <= sdMuxAddr; + + -- System bus control signals. + BUSY <= '1' when (cpuLastEN = '0' and (RDEN = '1' or WREN = '1')) else cpuBusy; + SDRAM_READY <= isReady; + +end Structure; diff --git a/zpu/build/simulation/modelsim/QMV_zpu.sft b/zpu/build/simulation/modelsim/QMV_zpu.sft new file mode 100644 index 0000000..0c5034b --- /dev/null +++ b/zpu/build/simulation/modelsim/QMV_zpu.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (VHDL)" diff --git a/zpu/build/simulation/modelsim/QMV_zpu.vho b/zpu/build/simulation/modelsim/QMV_zpu.vho new file mode 100644 index 0000000..18bc2d7 --- /dev/null +++ b/zpu/build/simulation/modelsim/QMV_zpu.vho @@ -0,0 +1,465015 @@ +-- Copyright (C) 2017 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus Prime" +-- VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition" + +-- DATE "03/05/2020 08:44:57" + +-- +-- Device: Altera 5CEFA2F23C8 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY ALTERA; +LIBRARY ALTERA_LNSIM; +LIBRARY CYCLONEV; +LIBRARY IEEE; +USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL; +USE ALTERA_LNSIM.ALTERA_LNSIM_COMPONENTS.ALL; +USE CYCLONEV.CYCLONEV_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY QMV_zpu IS + PORT ( + CLOCK_50 : IN std_logic; + LEDR : OUT std_logic; + KEY : IN std_logic; + SDCARD_MISO : IN std_logic_vector(0 DOWNTO 0); + SDCARD_MOSI : OUT std_logic_vector(0 DOWNTO 0); + SDCARD_CLK : OUT std_logic_vector(0 DOWNTO 0); + SDCARD_CS : OUT std_logic_vector(0 DOWNTO 0); + UART_RX_0 : IN std_logic; + UART_TX_0 : OUT std_logic; + UART_RX_1 : IN std_logic; + UART_TX_1 : OUT std_logic; + SDRAM_CLK : OUT std_logic; + SDRAM_CKE : OUT std_logic; + SDRAM_DQ : INOUT std_logic_vector(15 DOWNTO 0); + SDRAM_ADDR : OUT std_logic_vector(11 DOWNTO 0); + SDRAM_DQM : OUT std_logic_vector(1 DOWNTO 0); + SDRAM_BA : OUT std_logic_vector(1 DOWNTO 0); + SDRAM_CS : OUT std_logic; + SDRAM_WE : OUT std_logic; + SDRAM_RAS : OUT std_logic; + SDRAM_CAS : OUT std_logic + ); +END QMV_zpu; + +-- Design Ports Information +-- UART_TX_1 => Location: PIN_AB18, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_CLK => Location: PIN_AB11, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- UART_TX_0 => Location: PIN_AA15, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDCARD_MOSI[0] => Location: PIN_AA18, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDCARD_CLK[0] => Location: PIN_AA20, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDCARD_CS[0] => Location: PIN_Y20, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_ADDR[0] => Location: PIN_P8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_ADDR[1] => Location: PIN_P7, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_ADDR[2] => Location: PIN_N8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_ADDR[3] => Location: PIN_N6, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_ADDR[4] => Location: PIN_U6, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_ADDR[5] => Location: PIN_U7, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_ADDR[6] => Location: PIN_V6, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_ADDR[7] => Location: PIN_U8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_ADDR[8] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_ADDR[9] => Location: PIN_W8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_ADDR[10] => Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_ADDR[11] => Location: PIN_T9, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQM[0] => Location: PIN_AB7, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQM[1] => Location: PIN_V10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_BA[0] => Location: PIN_T7, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_BA[1] => Location: PIN_P9, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_WE => Location: PIN_W9, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_RAS => Location: PIN_AB6, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_CAS => Location: PIN_AA7, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- LEDR => Location: PIN_D17, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_CKE => Location: PIN_V9, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_CS => Location: PIN_AB5, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[12] => Location: PIN_R11, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[13] => Location: PIN_U12, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[14] => Location: PIN_R12, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[15] => Location: PIN_P12, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[0] => Location: PIN_AA12, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[1] => Location: PIN_Y11, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[2] => Location: PIN_AA10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[3] => Location: PIN_AB10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[4] => Location: PIN_Y10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[5] => Location: PIN_AA9, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[6] => Location: PIN_AB8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[7] => Location: PIN_AA8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[8] => Location: PIN_U10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[9] => Location: PIN_T10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[10] => Location: PIN_U11, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- SDRAM_DQ[11] => Location: PIN_R10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +-- CLOCK_50 => Location: PIN_M9, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- KEY => Location: PIN_AB13, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- SDCARD_MISO[0] => Location: PIN_Y17, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- UART_RX_0 => Location: PIN_AA14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- UART_RX_1 => Location: PIN_Y15, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +ARCHITECTURE structure OF QMV_zpu IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_CLOCK_50 : std_logic; +SIGNAL ww_LEDR : std_logic; +SIGNAL ww_KEY : std_logic; +SIGNAL ww_SDCARD_MISO : std_logic_vector(0 DOWNTO 0); +SIGNAL ww_SDCARD_MOSI : std_logic_vector(0 DOWNTO 0); +SIGNAL ww_SDCARD_CLK : std_logic_vector(0 DOWNTO 0); +SIGNAL ww_SDCARD_CS : std_logic_vector(0 DOWNTO 0); +SIGNAL ww_UART_RX_0 : std_logic; +SIGNAL ww_UART_TX_0 : std_logic; +SIGNAL ww_UART_RX_1 : std_logic; +SIGNAL ww_UART_TX_1 : std_logic; +SIGNAL ww_SDRAM_CLK : std_logic; +SIGNAL ww_SDRAM_CKE : std_logic; +SIGNAL ww_SDRAM_ADDR : std_logic_vector(11 DOWNTO 0); +SIGNAL ww_SDRAM_DQM : std_logic_vector(1 DOWNTO 0); +SIGNAL ww_SDRAM_BA : std_logic_vector(1 DOWNTO 0); +SIGNAL ww_SDRAM_CS : std_logic; +SIGNAL ww_SDRAM_WE : std_logic; +SIGNAL ww_SDRAM_RAS : std_logic; +SIGNAL ww_SDRAM_CAS : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(39 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(39 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_ACLR_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_CLK_bus\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_ENA_bus\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_AX_bus\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_AY_bus\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_ACLR_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_CLK_bus\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_ENA_bus\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_AX_bus\ : std_logic_vector(13 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_AY_bus\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_BX_bus\ : std_logic_vector(13 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_BY_bus\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(39 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(39 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(39 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(39 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_CLKIN_bus\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_MHI_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_SHIFTEN_bus\ : std_logic_vector(8 DOWNTO 0); +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER_VCO0PH_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER_VCO0PH_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~40\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~41\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~43\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~44\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~45\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~47\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~48\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~49\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~51\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~52\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~53\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~55\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~56\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~57\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~59\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~60\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~61\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~63\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~64\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~65\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~67\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~68\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~69\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~71\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~387\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~388\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~389\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~390\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~391\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~392\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~393\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~394\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~395\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~396\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~397\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~398\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~399\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~400\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~401\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~402\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~403\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~404\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~405\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~406\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~407\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~408\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~409\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~410\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~411\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~412\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~413\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~414\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~415\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~416\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~417\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~418\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~419\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~420\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~421\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~422\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~423\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~424\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~425\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~426\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~427\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~428\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~429\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~430\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~431\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~432\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~433\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~434\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~435\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~436\ : std_logic; +SIGNAL \CLOCK_50~input_o\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_O_EXTSWITCHBUF\ : std_logic; +SIGNAL \KEY~input_o\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_O_CLKOUT\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI2\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI3\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI4\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI5\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI6\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI7\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_UP\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI1\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFTENM\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI0\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFT\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|fb_clkin\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_CNTNEN\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFTEN0\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_TCLK\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH0\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH1\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH2\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH3\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH4\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH5\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH6\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH7\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIGSHIFTEN2\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\ : std_logic; +SIGNAL \UART_RX_1~input_o\ : std_logic; +SIGNAL \UART_RX_0~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER_RX~3_combout\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|wire_generic_pll1_locked\ : std_logic; +SIGNAL \reset~combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~34\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER_RX~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER_RX~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~38\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER_RX~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~18\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~42\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~46\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal11~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~30\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER_RX~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~10\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~50\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER_RX~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~54\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~58\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~62\ : std_logic; +SIGNAL \myVirtualToplevel|Add1~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal11~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal11~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[0]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~62_cout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[1]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~26\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[3]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~18\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[4]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[5]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~10\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[6]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal12~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[8]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~58\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[9]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~54\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[10]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~42\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[11]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~38\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[12]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~50\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[13]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal12~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~46\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[14]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~34\ : std_logic; +SIGNAL \myVirtualToplevel|Add2~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_COUNTER[15]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal12~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_n~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_n~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RESET_n~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30_cout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM990\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1685~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1684~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1683~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1681~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1680~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1679~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]_OTERM3311\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~104_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~105_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]_OTERM3260\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]_OTERM3263\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]_OTERM3287\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]_OTERM3284\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]_OTERM3272\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]_OTERM3269\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]_OTERM3266\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~90\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~94\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~100_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~99_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divStart~1_combout\ : std_logic; +SIGNAL \~GND~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add61~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]_OTERM3299\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]_OTERM3296\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]_OTERM3290\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]_OTERM3323\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]_OTERM3308\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]_OTERM3305\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_OTERM1905\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]_OTERM1903\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]_OTERM1901\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]_OTERM1899\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]_OTERM1897\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]_OTERM1895\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]_OTERM1893\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]_OTERM1891\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]_OTERM1889\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]_OTERM1887\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]_OTERM1885\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]_OTERM1883\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]_OTERM1881\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]_OTERM1879\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]_OTERM1877\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~94\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~90\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]_OTERM1871\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]_OTERM1867\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]_OTERM1865\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]_OTERM1863\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]_OTERM1947\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]_OTERM1945\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]_OTERM1943\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]_OTERM1939\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]_OTERM1937\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]_OTERM1935\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]_OTERM1933\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]_OTERM1931\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]_OTERM1929\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]_OTERM1927\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]_OTERM1925\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]_OTERM1923\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]_OTERM1921\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]_OTERM1919\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]_OTERM1917\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]_OTERM1915\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]_OTERM1913\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]_OTERM1911\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]_OTERM1909\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~39\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~43\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~47\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~51\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~55\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~59\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~83\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~87\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~63\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~67\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~71\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~19\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~23\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~27\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~31\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~75\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~35\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~79\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~11\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619_BDD8620\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]_OTERM1907\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]_OTERM2626\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]_OTERM2629\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]_OTERM2632\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]_OTERM2635\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]_OTERM2638\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]_OTERM2641\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]_OTERM2644\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]_OTERM2647\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]_OTERM2650\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]_OTERM2653\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]_OTERM2656\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]_OTERM2659\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]_OTERM2662\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]_OTERM2668\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]_OTERM2671\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]_OTERM2674\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]_OTERM2677\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~94_cout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~95\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~90_cout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~91\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~51\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~39\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~55\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~43\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~47\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~27\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~31\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~35\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~11\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~15\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~59\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~63\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~67\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~71\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~19\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~23\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~75\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]_OTERM2680\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~79\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~83\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~35\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~39\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~23\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~43\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~27\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~47\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~71\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~75\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~79\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~83\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~87\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~31\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~11\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~15\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~51\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~19\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~55\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~59\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~63\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~67\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_RESYN12370_BDD12371\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]_OTERM2683\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_RESYN12470_BDD12471\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688_BDD12689\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690_BDD12691\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]_OTERM1875\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]_OTERM1873\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704_BDD12705\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_RESYN12706_BDD12707\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~263_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM687\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489_BDD8490\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775_BDD8776\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777_BDD8778\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145_BDD9146\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147_BDD9148\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413_BDD8414\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411_BDD8412\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771_BDD8772\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773_BDD8774\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618_BDD12619\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_BDD8960\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~3_RTM0967_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~1_RTM01049_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~1_RTM01039_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_DATA_WRITE[7]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~297_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ : std_logic; +SIGNAL \SDCARD_MISO[0]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~14\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~26\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector20~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~18\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector19~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~2\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector18~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector14~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector15~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector14~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector14~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\ : std_logic; +SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_READ_2~q\ : std_logic; +SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector15~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector15~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector11~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector12~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ : std_logic; +SIGNAL \myVirtualToplevel|SD_RESET_TIMER~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add0~26\ : std_logic; +SIGNAL \myVirtualToplevel|Add0~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_RESET_TIMER[3]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add0~18\ : std_logic; +SIGNAL \myVirtualToplevel|Add0~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_RESET_TIMER~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add0~10\ : std_logic; +SIGNAL \myVirtualToplevel|Add0~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add0~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add0~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_RESET_TIMER~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add0~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add0~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_RESET_TIMER~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add0~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add0~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_RESET_TIMER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal8~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector15~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector18~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector15~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector15~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector15~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_RD[0]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~6\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~14\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~18\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~22\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~26\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~30\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~34\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~38\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~2\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~79_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~87_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~82_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~74_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector160~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~73_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~89_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~10\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~14\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector65~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~26\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~18\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~22\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~2\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~6\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~71_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~88_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~86_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector159~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~22\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector17~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~6\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector16~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector15~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM782\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector18~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_RESYN12644_BDD12645\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid_OTERM3342\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640_BDD12641\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux74~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434_BDD12435\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux110~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ : std_logic; +SIGNAL \SDRAM_DQ[0]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]_OTERM3178\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]_OTERM3050\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]_OTERM2986\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]_OTERM3114\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]_OTERM2794\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]_OTERM2858\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]_OTERM2730\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]_OTERM2922\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal7~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]_OTERM2926\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]_OTERM2734\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]_OTERM2862\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]_OTERM2798\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]_OTERM3118\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]_OTERM3182\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]_OTERM2990\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]_OTERM3054\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][15]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux68~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1409\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM41\ : std_logic; +SIGNAL \SDRAM_DQ[7]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[4]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux94~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ : std_logic; +SIGNAL \SDRAM_DQ[13]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM87\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~DUPLICATE_q\ : std_logic; +SIGNAL \SDRAM_DQ[2]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_OTERM65\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM922\ : std_logic; +SIGNAL \SDRAM_DQ[10]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM25\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM23\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1678~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1677~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1676~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM894\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM892\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1177\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM553\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM551\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM549\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux75~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_RESYN12624_BDD12625\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_RESYN12628_BDD12629\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM5\ : std_logic; +SIGNAL \SDRAM_DQ[1]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_ENABLE_FIFO~0_combout\ : std_logic; +SIGNAL \SDRAM_DQ[5]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_OTERM75\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157_BDD9158\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_BDD9162\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809_BDD8810\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159_BDD9160\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[0]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1533\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437_BDD8438\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435_BDD8436\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1074~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1543\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1537\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783_BDD8784\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785_BDD8786\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1379\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1385\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1561\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1567\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781_BDD8782\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1259\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443_BDD8444\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1427\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445_BDD8446\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803_BDD8804\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155_BDD9156\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1283\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789_BDD8790\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791_BDD8792\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1477\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1471\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1475\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]_OTERM3048\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]_OTERM3176\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]_OTERM3112\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]_OTERM2984\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]_OTERM2920\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]_OTERM2792\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]_OTERM2728\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]_OTERM2856\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux72~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ : std_logic; +SIGNAL \SDRAM_DQ[3]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM37\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM35\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]_OTERM3329\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]_OTERM2980\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]_OTERM3172\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]_OTERM3044\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]_OTERM3108\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]_OTERM2852\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]_OTERM2724\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]_OTERM2916\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]_OTERM2788\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux70~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|INT_ENABLE[16]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Mux0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_TICK_HALT~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_TICK_HALT~q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~18\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~10\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~26\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~30\ : std_logic; +SIGNAL \myVirtualToplevel|Add3~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal13~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~13_sumout\ : std_logic; +SIGNAL \SDRAM_DQ[6]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM47\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM45\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal4~0_RESYN12606_BDD12607\ : std_logic; +SIGNAL \myVirtualToplevel|Equal4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1_CS~combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_ENABLE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_ENABLE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_ENABLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_RESET~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_RESET~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RXD_SYNC2~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RXD_SYNC~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Selector4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_STATE.start~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Selector5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Selector6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Selector7~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Selector8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Selector9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Selector10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Selector11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Selector12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_STATE.bits~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_STATE.bits~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_STATE.stop~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_STATE.start~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_STATE.start~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_STATE.idle~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_STATE.idle~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]_OTERM2722\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]_OTERM2850\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]_OTERM2786\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]_OTERM2914\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]_OTERM2978\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]_OTERM3042\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]_OTERM3106\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]_OTERM3170\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]_OTERM3174\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]_OTERM3110\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]_OTERM2982\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]_OTERM3046\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]_OTERM2726\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]_OTERM2790\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]_OTERM2918\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]_OTERM2854\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~54\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~30\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~34\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~38\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~6\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~42\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~46\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~58\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~62\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add1~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_STATE.stop~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_STATE.stop~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_STATE.stop~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_INTR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_ENABLE_FIFO~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA_READY~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA_READY~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA_READY~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|process_3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add4~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add4~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add4~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add4~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add4~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add4~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal2~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add4~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add4~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add4~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal2~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~6\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add3~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~30\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add2~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal3~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add4~6\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add4~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add4~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add4~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal2~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal2~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal3~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_BUFFER[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~24_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~17_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA[6]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_ENABLE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_ENABLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_RESET~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_RESET~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RXD_SYNC2~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RXD_SYNC~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Selector6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~54\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~30\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~34\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~38\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~6\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~42\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~46\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~58\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~62\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add1~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Selector7~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Selector8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Selector9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Selector10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Selector11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Selector12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_STATE.stop~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_STATE.stop~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_STATE.stop~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_STATE.idle~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_STATE.idle~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_STATE.start~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_STATE.start~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_STATE.bits~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_STATE.bits~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Selector4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Selector5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_INTR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add4~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add4~6\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add4~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add4~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add4~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add4~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add4~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add4~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add4~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add4~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add4~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add4~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add4~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~30\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal2~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal2~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal2~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal2~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA_READY~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA_READY~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA_READY~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|process_3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~6\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add3~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~30\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add2~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal3~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal3~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~24_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~17_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA[6]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[0]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal36~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|INTR0_CS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~26\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~30\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~10\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Equal36~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~94\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~90\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~86\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~82\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~78\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~74\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~109_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~110\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~105_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~106\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~70\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~66\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~10\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~46\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~42\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~38\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~34\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~30\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~26\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~18\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~62\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~58\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~54\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~101_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~102\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~50\ : std_logic; +SIGNAL \myVirtualToplevel|Add18~97_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal35~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal35~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal35~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal35~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal35~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal35~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SECOND_DOWN_TICK[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Equal35~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal35~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~42\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~46\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~38\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~34\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add19~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~70\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~66\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~62\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal34~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~58\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~54\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~18\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~50\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~46\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~42\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~38\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~34\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~30\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~10\ : std_logic; +SIGNAL \myVirtualToplevel|Add16~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal34~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal34~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal34~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal34~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~125_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~126\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~90\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~86\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~82\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~50\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~54\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~90\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~94\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~86\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~82\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~50\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~54\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~70\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~74\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~78\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~58\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~62\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~66\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~34\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~38\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~42\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~46\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1615\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|LessThan0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[1]~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_OTERM3217\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux81~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127_BDD9128\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125_BDD9126\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[0]~70_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~20_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA[2]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~34\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~38\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~30\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~26\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~18\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add5~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add7~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add7~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~74_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~66\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~70\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~62\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~58\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal33~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~26\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~30\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~46\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~50\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~54\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~34\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~38\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~42\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~10\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~18\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Equal33~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal33~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Equal33~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~70\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~66\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~62\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal32~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~58\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~54\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~18\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~50\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~46\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~42\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~38\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~34\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~30\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_TICK[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~10\ : std_logic; +SIGNAL \myVirtualToplevel|Add14~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal32~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal32~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal32~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal32~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add15~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~73_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[5]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[0]_OTERM1629\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~42\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[1]_OTERM1627\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|process_1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|process_1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add9~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|process_1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|process_1~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|process_1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|process_1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~46\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[2]_OTERM1755\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~75_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~42_cout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~37\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~32\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~20_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA[2]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~76_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~77_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[0]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM31\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_OTERM3214\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]_OTERM3211\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]_OTERM3223\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]_OTERM3208\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]_OTERM3205\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]_OTERM3202\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~374_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1313\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[1]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1319\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[2]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1323\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1325\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1327\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[3]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1355\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1357\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[4]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1343\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1341\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1345\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[5]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1347\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1349\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1351\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[6]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1335\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1337\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[7]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~375_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~373_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~372_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~377_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~376_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~379_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~378_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~389_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~388_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~393_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~392_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~391_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~390_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~394_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~395_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[17]~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM603\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM599\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM595\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM597\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[30]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[17]_OTERM1074\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[17]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[17]_OTERM1080\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[17]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[17]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_RESET~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_RESET~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_ENABLE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_ENABLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_OVERRUN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_ENABLE_FIFO~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add7~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add7~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add7~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add7~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add7~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add7~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add7~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add7~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add7~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add7~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add7~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add8~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add8~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add8~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add8~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add8~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add8~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add8~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal5~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add7~6\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add7~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add8~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add8~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add8~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add8~6\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add8~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal5~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal5~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal5~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_BUFFER[16]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~62\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~50\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~54\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM906\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]_OTERM2774\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]_OTERM2902\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]_OTERM2838\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]_OTERM2710\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]_OTERM3158\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]_OTERM3030\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]_OTERM2966\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]_OTERM3094\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector273~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM908\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~38\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM910\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]_OTERM3028\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]_OTERM2964\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]_OTERM3156\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]_OTERM3092\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]_OTERM2836\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]_OTERM2708\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]_OTERM2772\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]_OTERM2900\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector272~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM912\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~34\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM918\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux92~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SOCCFG[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux268~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux268~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~38\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[3]_OTERM1757\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~34\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[4]_OTERM1773\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[4]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[4]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~22_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA[4]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add5~26_cout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add5~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add5~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add5~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add5~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add5~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add5~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add5~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_INTR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add5~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add5~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_INTR~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add5~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add5~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_INTR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_INTR~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_INTR~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_INTR~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_INTR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add5~26_cout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add5~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add5~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add5~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_INTR~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add5~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add5~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add5~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add5~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add5~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add5~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_INTR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add5~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add5~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_INTR~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_INTR~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_INTR~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~22_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA[4]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[4]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739_BDD8740\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~58\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~46\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~42\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~30\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~26\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~38\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~22\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~62\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~18\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~34\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~14\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~10\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~6\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~2\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~54\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|prescaled_tick~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER_REG_REQ~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|process_0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER_REG_REQ~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_index[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~86\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~97_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~98\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~101_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~102\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~70\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~74\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~78\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~90\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~94\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~113_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~114\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~10\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~14\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~34\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~82\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~105_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~106\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~109_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~110\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~42\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~46\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~66\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~117_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~118\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~121_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~122\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~125_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~126\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~26\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM914\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_OTERM73\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[22]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_ENABLE_FIFO~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_RESET~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_RESET~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_ENABLE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_ENABLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_OVERRUN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_OVERRUN~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~30\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add7~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add6~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal6~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add7~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add7~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add7~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add7~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add7~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add7~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add7~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add7~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add7~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add7~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add7~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add7~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal5~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal5~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~38\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~30\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~50\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~54\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768_BDD12769\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux83~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux86~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SOCCFG[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~18_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA[0]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_EMPTY_V~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_EMPTY_V~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~18_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA[0]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~88_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~89_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~90_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~91_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~36_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~93_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[0]~94_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[26]~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[24]~86_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~70\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~74\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~78\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~58\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~62\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~66\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~34\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~38\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~42\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~46\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~26\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~30\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~10\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~18\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~121_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]_OTERM3036\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]_OTERM3164\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]_OTERM2972\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]_OTERM3100\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]_OTERM2716\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]_OTERM2844\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]_OTERM2908\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]_OTERM2780\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[24]~87_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux87~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector7~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][24]~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[24]~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM15\ : std_logic; +SIGNAL \SDRAM_DQ[8]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM17\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[24]~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~99\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~104\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~95\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~90\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~53\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~76\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~81\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~67\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~72\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~36\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~40\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~44\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~48\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~23\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~27\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~31\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~15\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~10_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[1]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009_BDD9010\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~122\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~109_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~110\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~113_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~114\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~117_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_RESYN8993_BDD8994\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~256_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~257_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~249_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~248_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~268_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~261_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~269_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~260_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311_BDD9312\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_BDD9316\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313_BDD9314\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]_OTERM1841\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]_OTERM1839\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~253_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~252_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~265_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~264_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~273_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~272_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~259_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~275_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~271_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~255_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~254_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~270_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~274_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~258_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~266_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~250_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~246_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~247_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~251_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~267_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~346_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~350_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~355_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~354_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~344_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~348_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~360_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~361_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~349_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~345_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~365_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~364_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~359_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~358_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~347_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]_OTERM3160\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]_OTERM3096\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]_OTERM2968\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]_OTERM3032\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]_OTERM2712\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]_OTERM2840\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]_OTERM2904\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]_OTERM2776\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[2]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[3]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[4]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[5]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]_OTERM2704\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]_OTERM2896\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]_OTERM2832\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]_OTERM2768\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]_OTERM3088\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]_OTERM3024\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]_OTERM3152\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]_OTERM2960\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[6]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux88~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][23]~q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[22]_OTERM1263\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~35_cout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~30\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~6\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[23]_OTERM1305\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~26\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~30\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~10\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[23]_OTERM1307\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[23]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[23]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[7]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~340_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~336_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]_OTERM1829\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]_OTERM1827\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~342_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~338_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~353_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~352_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~339_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~343_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~341_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~356_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~357_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~363_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~362_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_RESYN12678_BDD12679\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_RESYN12670_BDD12671\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_RESYN12778_BDD12779\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671_BDD8672\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~120_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8669_BDD8670\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~31\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~15\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~11\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~19\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~111\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~106\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~107\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~102\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~103\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~98\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~99\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~114\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~115\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~117_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~160_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~156_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675_BDD8676\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673_BDD8674\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~129_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8677_BDD8678\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~90\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466_BDD13467\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~90\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~94\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~110\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~106\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~102\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~98\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~114\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~118\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~118\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~119\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_BDD9276\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~137_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~19\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~121\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~117\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~113\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~109\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~125\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~129\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~132_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~144_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~142_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9025_BDD9026\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9027_BDD9028\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9029_BDD9030\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8685_BDD8686\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8683_BDD8684\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]_OTERM1709\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~90\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~91\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]_OTERM1711\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~94\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~95\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[2]_OTERM1713\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~87\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[3]_OTERM1715\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~83\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[4]_OTERM1717\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~51\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[5]_OTERM1719\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~55\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]_OTERM1721\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~71\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]_OTERM1723\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~75\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[8]_OTERM1725\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~79\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]_OTERM1727\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~59\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[10]_OTERM1729\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~63\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[11]_OTERM1731\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~67\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[12]_OTERM1737\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~35\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[13]_OTERM1631\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~39\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[14]_OTERM1733\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~43\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[15]_OTERM1735\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~47\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]_OTERM1753\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[17]_OTERM1743\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~23\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]_OTERM1741\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~27\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[19]_OTERM1739\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~31\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[20]_OTERM1747\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~15\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]_OTERM1751\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[22]_OTERM1749\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~11\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[23]_OTERM1745\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~19\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~125_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[24]_OTERM1693\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~126\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~127\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~121_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[25]_OTERM1695\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~122\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~123\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~109_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[26]_OTERM1697\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~110\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~111\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~117_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[27]_OTERM1699\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~118\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~119\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~113_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[28]_OTERM1701\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~114\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~115\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~101_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[29]_OTERM1703\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~102\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~103\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~105_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]_OTERM1705\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM796\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM792\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM788\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM197\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM169\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM199\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM171\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM201\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM173\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM203\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM175\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM205\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM177\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM207\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM179\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM209\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM181\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM183\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM211\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM185\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM213\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM215\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM187\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM217\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM189\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM219\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM191\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM221\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM193\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~359\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~363\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~351\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~343\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~347\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~355\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~720\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~716\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~712\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~708\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~724\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~728\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~731_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~147_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9277_BDD9278\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][28]~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[28]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[4]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM91\ : std_logic; +SIGNAL \SDRAM_DQ[12]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM93\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~79_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[28]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[28]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~14_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~366_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector298~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[27]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[3]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]_OTERM2950\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[28]_OTERM3078\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[28]_OTERM3014\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[28]_OTERM3142\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[28]_OTERM2886\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[28]_OTERM2694\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[28]_OTERM2822\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[28]_OTERM2758\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector297~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[28]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[4]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM768\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[29]_OTERM3140\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[29]_OTERM2948\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[29]_OTERM3012\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[29]_OTERM3076\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[29]_OTERM2820\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[29]_OTERM2692\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[29]_OTERM2756\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[29]_OTERM2884\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector296~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM770\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[5]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[30]_OTERM3074\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[30]_OTERM3138\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[30]_OTERM2946\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[30]_OTERM3010\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[30]_OTERM2818\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[30]_OTERM2754\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[30]_OTERM2882\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[30]_OTERM2690\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector295~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[30]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[6]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[31]_OTERM3086\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[31]_OTERM3150\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[31]_OTERM3022\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[31]_OTERM2958\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[31]_OTERM2702\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[31]_OTERM2766\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[31]_OTERM2830\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[31]_OTERM2894\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector294~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_OTERM766\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_OTERM764\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[7]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~367_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~371_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~370_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~369_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~368_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]_OTERM1823\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]_OTERM1825\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~387_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~386_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~384_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~385_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~380_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~381_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_RESYN8957_BDD8958\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8749_BDD8750\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~350_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM800\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[20]_OTERM1213\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8745_BDD8746\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN9337_BDD9338\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12594_BDD12595\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12592_BDD12593\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9335_BDD9336\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_BDD9334\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_BDD8964\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_BDD8966\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~383_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8967_BDD8968\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~242_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~243_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~235_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~234_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~239_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~230_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~231_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~238_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]_OTERM1843\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]_OTERM1845\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~223_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~222_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~218_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~219_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~227_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~244_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~228_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~224_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~240_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~237_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~233_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~221_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~217_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~241_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~225_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~245_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~229_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~232_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~220_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~236_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~216_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~90\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~91\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~94\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~95\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~87\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~83\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~51\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~55\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~71\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~75\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~79\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~59\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~63\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~67\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~35\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~39\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~43\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~47\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[16]_OTERM1239\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~287_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~278_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~279_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~286_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~291_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~298_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~299_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~290_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]_OTERM1849\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~283_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]_OTERM1847\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~282_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~295_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~303_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~294_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~302_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~280_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~276_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~292_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~281_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~293_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~289_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~305_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~301_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~285_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~300_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~304_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~288_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~284_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1183\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1181\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1185\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~47_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~319_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~311_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~327_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~335_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~310_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~326_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~318_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~435_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~436_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~334_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~323_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~331_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~315_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~307_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~322_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~314_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~330_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~306_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~316_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~312_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~313_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~317_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~320_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~325_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~321_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~308_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]_OTERM1833\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]_OTERM1831\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~329_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~332_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~333_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~328_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~43_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8709_BDD8710\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8705_BDD8706\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_RESYN9111_BDD9112\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_BDD8708\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8711_BDD8712\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8979_BDD8980\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9345_BDD9346\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9349_BDD9350\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~39_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9347_BDD9348\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_BDD8984\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_RESYN9251_BDD9252\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1187\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1189\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[12]_OTERM1241\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~35_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8977_BDD8978\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8975_BDD8976\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~418_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~411_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~419_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~410_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~396_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~405_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~397_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~404_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~413_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~421_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~412_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~420_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~402_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~403_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]_OTERM1821\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]_OTERM1819\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~406_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~408_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~424_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~422_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~399_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~415_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~417_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~401_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~423_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~407_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~409_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~425_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~398_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~414_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~416_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~400_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_RESYN12770_BDD12771\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~66_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1231\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1229\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[9]_OTERM1249\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~70_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~71_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~165_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~83_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~80_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[7]_OTERM1247\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~75_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[6]_OTERM1243\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[5]_OTERM1245\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector354~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector354~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~82_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~94_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~81_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~80_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~79_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~94\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector350~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector347~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~110\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~106\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~102\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~98\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~113_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~114\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~118\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~121_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[30]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~130_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8679_BDD8680\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~128_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~117_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8681_BDD8682\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~727_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM900\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[29]_OTERM970\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~135_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~157_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~136_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~117_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8667_BDD8668\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~112_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~113_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~113_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~124_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~121_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~113_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9263_BDD9264\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9267_BDD9268\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~723_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM798\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~122_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9269_BDD9270\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[28]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~106\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~107\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[58]_OTERM1685\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[57]_OTERM1683\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[59]_OTERM1687\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[60]_OTERM1689\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[61]_OTERM1691\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~77_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~76_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~707_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~97_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~97_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8649_BDD8650\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8651_BDD8652\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~108_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8647_BDD8648\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8997_BDD8998\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8999_BDD9000\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~97_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[27]_OTERM2952\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[27]_OTERM3016\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[27]_OTERM3144\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[27]_OTERM3080\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[27]_OTERM2888\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[27]_OTERM2824\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[27]_OTERM2696\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[27]_OTERM2760\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[27]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~118\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~94\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~97_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[29]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~98\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~101_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[30]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~102\ : std_logic; +SIGNAL \myVirtualToplevel|Add17~105_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~82_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][31]~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[31]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM79\ : std_logic; +SIGNAL \SDRAM_DQ[15]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM81\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[7]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[31]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~133\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~136_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~122\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~123\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~125_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~122\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~125_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM167\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM195\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~732\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~735_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9033_BDD9034\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]_OTERM1707\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM523\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_68\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM517\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_64\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM515\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM521\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM519\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9031_BDD9032\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~122\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~125_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_RESYN12772_BDD12773\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_RESYN12802_BDD12803\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_RESYN9011_BDD9012\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~94\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~90\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_RESYN12546_BDD12547\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~88_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~95_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~149_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_RESYN8655_BDD8656\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~150_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~96_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~101_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~112_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~101_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~91_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~97_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12774_BDD12775\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN9003_BDD9004\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12776_BDD12777\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~711_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[26]_OTERM904\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~98_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~99_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~100_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~101_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[26]_OTERM2954\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[26]_OTERM3146\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]_OTERM3018\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]_OTERM3082\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[26]_OTERM2698\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[26]_OTERM2762\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[26]_OTERM2890\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[26]_OTERM2826\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector299~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM762\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM760\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[2]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~337_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_RESYN12674_BDD12675\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8633_BDD8634\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8631_BDD8632\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~346_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[22]_OTERM1175\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~11\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~18_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM896\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM890\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9109_BDD9110\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_RESYN8969_BDD8970\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9107_BDD9108\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_BDD8636\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8973_BDD8974\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~354_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1169\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1173\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8971_BDD8972\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[23]_OTERM2974\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[23]_OTERM3166\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[23]_OTERM3102\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[23]_OTERM3038\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[23]_OTERM2782\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]_OTERM2910\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[23]_OTERM2846\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[23]_OTERM2718\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector269~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM936\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM934\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~34\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~42\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~46\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~58\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_COUNTER[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~62\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add0~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[16]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_STATE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_STATE~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal5~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA_LOADED~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA_LOADED~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~30\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Add8~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[22]_OTERM1267\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[22]_OTERM1269\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][22]~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[22]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector270~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM916\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][22]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~62\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][23]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~30\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][24]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~58\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][25]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~54\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][26]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~50\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][27]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~38\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][28]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~18\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][29]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~22\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][30]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~2\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ticks~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|INT_DONE~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_INTR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_INTR~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_INTR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_INTR~q\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|INT_ENABLE[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[4]~90_combout\ : std_logic; +SIGNAL \SDRAM_DQ[4]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM61\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[4]~131_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~23\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~27\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~342_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[21]_OTERM1215\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_RESYN8961_BDD8962\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~6_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_RESYN8629_BDD8630\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[21]_OTERM3154\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[21]_OTERM3090\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[21]_OTERM3026\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[21]_OTERM2962\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[21]_OTERM2706\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[21]_OTERM2898\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[21]_OTERM2834\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[21]_OTERM2770\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector271~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM920\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~30\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~58\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~_wirecell_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~6\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~42\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add0~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_BUFFER[8]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_STATE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_STATE~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_DATA_LOADED~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_DATA_LOADED~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add8~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~14\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~6\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~18\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~22\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~26\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal6~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~30\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add6~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal6~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Equal6~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[17]_OTERM1084\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[17]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[17]_OTERM1078\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[17]_OTERM1076\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]_OTERM67\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[17]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM593\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM601\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[1]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~382_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~22_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[17]_OTERM1237\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[17]_OTERM3162\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[17]_OTERM3098\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[17]_OTERM3034\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[17]_OTERM2970\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[17]_OTERM2714\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[17]_OTERM2778\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[17]_OTERM2906\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[17]_OTERM2842\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector17~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector275~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1617\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Equal31~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal31~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal31~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal31~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal31~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal31~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~10\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~30\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~26\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add12~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal30~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Equal30~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add13~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[5]_OTERM1771\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~6\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[6]_OTERM1763\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~2\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~6\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[6]~86_RESYN8735_BDD8736\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[6]~86_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[6]~111_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[6]_OTERM2992\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[6]_OTERM3056\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[6]_OTERM3184\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[6]_OTERM3120\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[6]_OTERM2928\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[6]_OTERM2864\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[6]_OTERM2736\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[6]_OTERM2800\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~18\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~34\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~38\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~30\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~26\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~2\ : std_logic; +SIGNAL \myVirtualToplevel|Add4~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux267~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux267~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[5]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~23_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA[5]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~23_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA[5]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_ENABLE_FIFO~q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[5]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[5]~88_RESYN8737_BDD8738\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[5]~88_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[5]~127_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[5]_OTERM2930\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[5]_OTERM2866\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[5]_OTERM2738\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[5]_OTERM2802\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[5]_OTERM2994\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[5]_OTERM3186\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[5]_OTERM3058\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[5]_OTERM3122\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[5]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux90~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[13]~72_RESYN8721_BDD8722\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[13]~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]_OTERM99\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector345~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux91~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~21_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA[3]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_OVERRUN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_OVERRUN~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_OVERRUN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_OVERRUN~q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~21_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA[3]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~71_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[3]~92_RESYN8741_BDD8742\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[3]~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[3]~99_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[3]_OTERM3190\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[3]_OTERM3062\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[3]_OTERM3126\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[3]_OTERM2998\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[3]_OTERM2742\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[3]_OTERM2934\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[3]_OTERM2806\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[3]_OTERM2870\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[3]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|INT_ENABLE[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[11]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~22\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[7]_OTERM1761\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~26\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[8]_OTERM1759\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~30\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[9]_OTERM1769\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~10\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[10]_OTERM1767\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~14\ : std_logic; +SIGNAL \myVirtualToplevel|Add11~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[11]_OTERM1765\ : std_logic; +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~104_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[11]~76_RESYN8725_BDD8726\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[11]~76_combout\ : std_logic; +SIGNAL \SDRAM_DQ[11]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM21\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]_OTERM49\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM529\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM525\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM527\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~309_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SOCCFG_CS_RESYN8753_BDD8754\ : std_logic; +SIGNAL \myVirtualToplevel|SOCCFG_CS~combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][21]~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[21]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[5]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[21]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[21]_OTERM3347\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_SELECT~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0_CS~combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_ENABLE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~19_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA[1]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FULL_V~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FULL_V~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FULL_V~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FULL_V~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~19_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA[1]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~98_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~95_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~94_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~96_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~97_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~31_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~99_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux82~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[1]~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[1]~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[8]_OTERM1221\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~73_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~74_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[8]_OTERM3004\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[8]_OTERM3132\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[8]_OTERM3196\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[8]_OTERM3068\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[8]_OTERM2940\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[8]_OTERM2812\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[8]_OTERM2748\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[8]_OTERM2876\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux75~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[0]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[8]~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux264~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[8]~100_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux94~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[8]~82_RESYN8731_BDD8732\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[8]~82_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]_OTERM39\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM547\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM545\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM543\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~186_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~190_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~206_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~202_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~207_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~203_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~191_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~187_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~195_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~199_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~211_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~215_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~214_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~210_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~198_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~194_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]_OTERM1835\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]_OTERM1837\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~193_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~192_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~213_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~205_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~204_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~212_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~201_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~200_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~209_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~188_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~189_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~197_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~196_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~26_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8703_BDD8704\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8699_BDD8700\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8701_BDD8702\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[18]_OTERM1235\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN9301_BDD9302\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12798_BDD12799\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12800_BDD12801\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_RESYN9249_BDD9250\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~30_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~362_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[19]_OTERM1233\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[19]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1401\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1399\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1179\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|BRAM_WREN~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[6]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][14]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux69~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~112_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[14]~70_RESYN8719_BDD8720\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[14]~70_combout\ : std_logic; +SIGNAL \SDRAM_DQ[14]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM85\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]_OTERM97\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER0_CS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER0_CS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[26]~84_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][26]~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[26]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[26]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[2]_OTERM2872\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[2]_OTERM2936\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[2]_OTERM2744\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[2]_OTERM2808\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[2]_OTERM3128\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[2]_OTERM3192\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[2]_OTERM3000\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[2]_OTERM3064\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector16~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector274~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM924\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][18]~q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_BUSY~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_BUSY~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUSY~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUSY~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[18]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[2]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[18]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[18]_OTERM3340\ : std_logic; +SIGNAL \myVirtualToplevel|IO_SELECT~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|INTR0_CS_RESYN8755_BDD8756\ : std_logic; +SIGNAL \myVirtualToplevel|INTR0_CS~combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SOCCFG[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][19]~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[19]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[3]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[19]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]_OTERM63\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|BRAM_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][29]~q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~80_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[29]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[5]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[29]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO~25_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_DATA[7]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO~25_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_DATA[7]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~10\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add9~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SOCCFG[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[7]~84_RESYN8733_BDD8734\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[7]~84_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[7]~107_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[7]_OTERM3198\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[7]_OTERM3134\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[7]_OTERM3006\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[7]_OTERM3070\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[7]_OTERM2878\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[7]_OTERM2942\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[7]_OTERM2750\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[7]_OTERM2814\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux76~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[7]~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[8]~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1075~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1411\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1581\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1583\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1573\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1571\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1599\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1597\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1271\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1275\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1497\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1495\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1375\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1377\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1447\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1445\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|LessThan3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[7]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[15]~68_RESYN8717_BDD8718\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[15]~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]_OTERM95\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_SELECT~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SOCCFG_CS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux73~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux73~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux93~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~108_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[10]~78_RESYN8727_BDD8728\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[10]~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]_OTERM51\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector348~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[11]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12612_BDD12613\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12614_BDD12615\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]_OTERM3336\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[0]~95_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[34]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[38]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[43]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[45]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[46]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[47]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[50]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[51]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[52]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[53]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[54]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[55]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]_OTERM3331\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[39]_OTERM3326\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[33]_OTERM1635\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[35]_OTERM1639\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[34]_OTERM1637\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[32]_OTERM1633\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[56]_OTERM1681\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[55]_OTERM1679\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[54]_OTERM1677\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[53]_OTERM1675\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]_OTERM1673\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[51]_OTERM1671\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[50]_OTERM1669\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[36]_OTERM1641\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]_OTERM1643\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[39]_OTERM1647\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[38]_OTERM1645\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[40]_OTERM1649\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[42]_OTERM1653\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[41]_OTERM1651\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[46]_OTERM1661\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[43]_OTERM1655\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[45]_OTERM1659\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[44]_OTERM1657\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[48]_OTERM1665\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[49]_OTERM1667\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[47]_OTERM1663\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9017_BDD9018\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~719_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9019_BDD9020\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8665_BDD8666\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~120_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8663_BDD8664\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~109_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~109_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8659_BDD8660\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8657_BDD8658\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8661_BDD8662\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9021_BDD9022\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~5_RESYN8715_BDD8716\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9023_BDD9024\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~109_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~110\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~105_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~161_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~105_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12554_BDD12555\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~116_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9077_RESYN9359_BDD9360\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_BDD9356\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9357_BDD9358\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_BDD9076\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12556_BDD12557\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351_BDD9352\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_BDD9016\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~152_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12542_BDD12543\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_BDD12545\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~715_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM898\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12780_BDD12781\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12782_BDD12783\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~109_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~105_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[25]_OTERM2764\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[25]_OTERM2700\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[25]_OTERM2892\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]_OTERM2828\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[25]_OTERM3148\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[25]_OTERM3020\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[25]_OTERM3084\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[25]_OTERM2956\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[25]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][25]~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[25]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[1]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~83_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM27\ : std_logic; +SIGNAL \SDRAM_DQ[9]~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM29\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[25]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector349~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[9]_OTERM3052\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[9]_OTERM3180\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[9]_OTERM3116\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[9]_OTERM2988\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[9]_OTERM2732\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[9]_OTERM2860\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[9]_OTERM2796\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[9]_OTERM2924\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux74~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[1]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[9]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux263~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[9]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[9]~80_RESYN8729_BDD8730\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[9]~80_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]_OTERM53\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_36\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]_OTERM1585\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1553\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]_OTERM1587\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1557\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1483\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1437\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]_OTERM1535\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1481\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[1]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1547\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1607\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1605\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1549\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]_OTERM1559\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector276~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM784\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][16]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|l1_w0_n0_mux_dataout~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~116_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Mux89~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[16]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]_OTERM77\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]_OTERM2912\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[16]_OTERM2720\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[16]_OTERM2848\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[16]_OTERM2784\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[16]_OTERM3104\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[16]_OTERM2976\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[16]_OTERM3168\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[16]_OTERM3040\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[16]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~296_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~103_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~87_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~106_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[1]_OTERM1223\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~83_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~84_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~86_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~85_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[1]_OTERM2810\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[1]_OTERM2938\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[1]_OTERM2746\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[1]_OTERM2874\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[1]_OTERM3130\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[1]_OTERM3066\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[1]_OTERM3002\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[1]_OTERM3194\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector15~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector15~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector19~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_DATA_REQ~q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector16~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_READ~q\ : std_logic; +SIGNAL \myVirtualToplevel|SD_DATA_VALID~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_DATA_VALID~q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector21~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_DATA_VALID~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector17~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector17~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector20~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|Selector20~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SD_OVERRUN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_OVERRUN~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_OVERRUN~q\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux77~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM559\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM555\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM557\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~226_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM948\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SD_CHANNEL~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_CHANNEL~q\ : std_logic; +SIGNAL \myVirtualToplevel|Selector0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~83_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][30]~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[30]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[6]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM83\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~81_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[30]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[30]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector344~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[15]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[3]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][27]~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[27]~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~85_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM19\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[27]~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[3]~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux78~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM565\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM561\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM563\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~351_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~52_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[4]_OTERM1225\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[4]_OTERM3060\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[4]_OTERM3124\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[4]_OTERM2996\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[4]_OTERM3188\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[4]_OTERM2932\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[4]_OTERM2740\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[4]_OTERM2804\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[4]_OTERM2868\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux79~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM571\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM567\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM569\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~208_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8491_BDD8492\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]_OTERM2880\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[0]_OTERM2752\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]_OTERM2816\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[0]_OTERM2944\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]_OTERM3200\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]_OTERM3072\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]_OTERM3136\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[0]_OTERM3008\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[0]_OTERM3220\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~324_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8985_BDD8986\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~101_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~98_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8987_BDD8988\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1205\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_40\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1601\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1603\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]_OTERM1619\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1545\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1429\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1555\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1479\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1551\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM691\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM689\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM685\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~262_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]_OTERM2688\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1489\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1493\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1491\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1501\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1505\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1419\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1395\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8495_BDD8496\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8497_BDD8498\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1511\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1457\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1459\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1461\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1455\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1595\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1593\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1297\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1301\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12404_BDD12405\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12402_BDD12403\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1303\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1465\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1467\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1463\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12408_BDD12409\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12406_BDD12407\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN12632_BDD12633\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879_BDD8880\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1469\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1515\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12412_BDD12413\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12410_BDD12411\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1519\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1577\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414_BDD12415\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416_BDD12417\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_RESYN8493_BDD8494\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12396_BDD12397\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12394_BDD12395\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1613\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1609\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1611\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1441\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1439\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1443\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12398_BDD12399\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12400_BDD12401\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585_BDD8586\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_RESYN8587_BDD8588\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_RESYN8589_BDD8590\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_RESYN8583_BDD8584\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_RESYN8571_BDD8572\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575_BDD8576\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664_BDD12665\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189_BDD9190\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195_BDD9196\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883_BDD8884\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_RESYN12642_BDD12643\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193_BDD9194\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527_BDD8528\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529_BDD8530\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513_BDD8514\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501_BDD8502\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM683\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM758\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal131~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_RESYN12504_BDD12505\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~80_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_RESYN12726_BDD12727\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~82_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_RESYN12698_BDD12699\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_RESYN12728_BDD12729\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_RESYN12732_BDD12733\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_RESYN12484_BDD12485\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_RESYN12734_BDD12735\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_RESYN12730_BDD12731\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12500_BDD12501\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12502_BDD12503\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal67~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_RESYN12742_BDD12743\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_RESYN12738_BDD12739\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_RESYN12740_BDD12741\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_RESYN12496_BDD12497\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_RESYN12490_BDD12491\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_RESYN12492_BDD12493\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~83_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_RESYN12486_BDD12487\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_RESYN12488_BDD12489\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_RESYN12736_BDD12737\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_RESYN12712_BDD12713\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_RESYN12714_BDD12715\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_RESYN12716_BDD12717\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux133~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux135~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~79_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_RESYN8929_BDD8930\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux121~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_RESYN12708_BDD12709\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_RESYN8935_BDD8936\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_RESYN12564_BDD12565\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_RESYN12710_BDD12711\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_RESYN8605_BDD8606\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_RESYN12696_BDD12697\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_RESYN12694_BDD12695\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_RESYN12700_BDD12701\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_RESYN12804_BDD12805\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_RESYN12702_BDD12703\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_RESYN9089_BDD9090\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_BDD8448\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8449_BDD8450\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9165_BDD9166\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9167_BDD9168\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8825_BDD8826\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8823_BDD8824\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8827_BDD8828\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~6_RESYN8457_BDD8458\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8833_BDD8834\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12388_BDD12389\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_RESYN12558_BDD12559\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8461_BDD8462\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_RESYN9091_BDD9092\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_BDD8460\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8831_BDD8832\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12386_BDD12387\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_RESYN8829_BDD8830\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8453_BDD8454\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8455_BDD8456\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8841_BDD8842\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8843_BDD8844\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8463_BDD8464\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8465_BDD8466\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_RESYN8837_BDD8838\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8861_BDD8862\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8473_BDD8474\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8475_BDD8476\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8859_BDD8860\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_RESYN12634_BDD12635\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12588_BDD12589\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12590_BDD12591\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_BDD8852\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8853_BDD8854\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8469_BDD8470\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_RESYN9093_BDD9094\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_BDD8468\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9179_BDD9180\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9173_BDD9174\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9177_BDD9178\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9169_BDD9170\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9171_BDD9172\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9175_BDD9176\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_RESYN9323_BDD9324\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_BDD8846\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_RESYN9325_BDD9326\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_BDD8848\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8849_BDD8850\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8867_BDD8868\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8869_BDD8870\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12638_BDD12639\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12636_BDD12637\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8873_BDD8874\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8875_BDD8876\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_RESYN8479_BDD8480\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8877_BDD8878\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux80~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM577\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM575\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM573\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~277_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tIdx~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8427_BDD8428\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8425_BDD8426\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[1]_OTERM2686\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM513\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM511\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM507\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_RESYN12692_BDD12693\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_RESYN12754_BDD12755\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_RESYN12746_BDD12747\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_RESYN12756_BDD12757\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~158_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~159_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~156_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~157_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~162_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~161_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~163_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~160_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12764_BDD12765\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12510_BDD12511\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12766_BDD12767\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12762_BDD12763\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~166_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~164_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~167_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~165_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~171_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~168_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~169_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~170_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_RESYN9207_BDD9208\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1108\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1110\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1157\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1159\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM984\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1052\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1054\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1219\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1203\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1201\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector301~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM754\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM750\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[0]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_RESYN12520_BDD12521\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~113_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_RESYN12522_BDD12523\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~112_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12750_BDD12751\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_RESYN12512_BDD12513\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_RESYN12514_BDD12515\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal46~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~102_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12526_BDD12527\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12524_BDD12525\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~434_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9247_BDD9248\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9245_BDD9246\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~122_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~125_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~124_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~123_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~117_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~114_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~115_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~116_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~118_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~121_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~120_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~119_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr160~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8639_BDD8640\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8641_BDD8642\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~71_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[11]_OTERM1227\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~94\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~90\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~101_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~98_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~102_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]_OTERM3275\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_RESYN12626_BDD12627\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_RESYN8921_BDD8922\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~166_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9237_BDD9238\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_RESYN8603_BDD8604\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9239_BDD9240\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9235_BDD9236\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~77_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9213_BDD9214\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9215_BDD9216\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_RESYN12460_BDD12461\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_RESYN9217_BDD9218\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_RESYN9307_BDD9308\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_RESYN12684_BDD12685\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9221_BDD9222\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9223_BDD9224\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_RESYN8599_BDD8600\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_RESYN12682_BDD12683\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_RESYN8597_BDD8598\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_RESYN12680_BDD12681\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_RESYN8595_BDD8596\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]_OTERM3281\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER0_CS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_OVERRUN~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|TX_OVERRUN~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|Add10~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_OVERRUN~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_OVERRUN~q\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[20]_OTERM1387\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[20]_OTERM1389\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][20]~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[20]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]_OTERM71\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[4]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[20]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~106_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~90\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~94\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~90\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~103_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~107_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_RESYN12652_BDD12653\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector899~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547_BDD8548\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545_BDD8546\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557_BDD8558\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_BDD8556\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector503~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector635~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561_BDD8562\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559_BDD8560\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12452_BDD12453\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12454_BDD12455\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector343~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~116_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~114_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~115_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~113_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~117_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~145_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~144_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~143_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~146_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~147_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~94\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~139_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~140_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~141_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~138_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~142_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~90\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~135_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~134_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~136_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~133_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~137_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]_OTERM3302\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|LessThan0~0_RESYN12604_BDD12605\ : std_logic; +SIGNAL \myVirtualToplevel|LessThan0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[4]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|Mux71~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[12]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ[12]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[12]~74_RESYN8723_BDD8724\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[12]~74_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]_OTERM101\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector346~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~96_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~95_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~94_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~93_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~97_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~90_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~89_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~91_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~88_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~120_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~119_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~121_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~118_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~122_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]_OTERM3293\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9151_BDD9152\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9149_BDD9150\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8953_BDD8954\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8955_BDD8956\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[18]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_RESYN12534_BDD12535\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8621_BDD8622\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8623_BDD8624\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12532_BDD12533\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12530_BDD12531\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~98_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~97_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~99_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~96_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~101_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~103_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~102_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~100_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~104_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~107_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~105_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~106_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~110_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~109_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~108_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~111_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM297\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM301\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1191\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1193\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1195\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1197\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1199\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_RESYN8615_BDD8616\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~129_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~127_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~128_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~126_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~85_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~132_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~133_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~131_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~130_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_RESYN8617_BDD8618\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~136_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~137_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~135_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~134_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_RESYN12752_BDD12753\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~141_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~138_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~140_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~139_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_RESYN12676_BDD12677\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~131_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~130_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~129_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~128_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~132_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]_OTERM3320\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]_OTERM3317\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pause[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pause[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~62_cout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pause[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pause[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddrPause~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_PreSetAddr~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_RESYN8613_BDD8614\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_RESYN12748_BDD12749\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~75_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~73_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~76_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~74_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~94_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_RESYN12508_BDD12509\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~71_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~70_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_RESYN12516_BDD12517\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_RESYN12518_BDD12519\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~77_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~79_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~80_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9225_BDD9226\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9229_BDD9230\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9233_BDD9234\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_RESYN12686_BDD12687\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_RESYN8601_BDD8602\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9231_BDD9232\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]_OTERM1941\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]_OTERM1869\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~94_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~93_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~91_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~83_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~85_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~86_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~84_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~82_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860_RESYN12810_BDD12811\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_OTERM1861\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~81_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~90_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~89_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~88_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~87_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~70_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~71_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_RESYN12744_BDD12745\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136_RESYN12724_BDD12725\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]_OTERM1851\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~74_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~75_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~73_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~76_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~124_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~125_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~126_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~123_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~127_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1675~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[23]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]_OTERM3345\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuLastEN~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~154_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~156_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~157_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12462_BDD12463\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12464_BDD12465\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~155_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_RESYN13460_BDD13461\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_BDD8942\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~159_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~172_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]_OTERM1855\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_RESYN12528_BDD12529\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~88_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_RESYN12758_BDD12759\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~5_RESYN12760_BDD12761\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852_RESYN12808_BDD12809\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_OTERM1853\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~173_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~178_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~181_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~179_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~180_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~185_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~183_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~182_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~184_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~174_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~177_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~175_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~176_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12718_BDD12719\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~149_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12722_BDD12723\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12720_BDD12721\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_RESYN13458_BDD13459\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_BDD8938\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8939_BDD8940\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~153_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~152_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~154_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~155_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~144_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~147_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~146_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~145_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~148_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~151_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~150_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~149_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~143_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]_OTERM1857\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]_OTERM1859\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~142_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~85_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~84_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~86_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~83_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~87_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]_OTERM3278\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_CS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_CS_RESYN9119_BDD9120\ : std_logic; +SIGNAL \myVirtualToplevel|SD_CS_RESYN9121_BDD9122\ : std_logic; +SIGNAL \myVirtualToplevel|SD_CS~combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[17]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector14~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][17]~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[17]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[17]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[17]_OTERM3334\ : std_logic; +SIGNAL \myVirtualToplevel|IO_SELECT_RESYN9117_BDD9118\ : std_logic; +SIGNAL \myVirtualToplevel|IO_SELECT_RESYN9115_BDD9116\ : std_logic; +SIGNAL \myVirtualToplevel|IO_SELECT~combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_BUSY~1_RESYN12610_BDD12611\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_READ_ENABLE_LAST~q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_BUSY~1_RESYN12608_BDD12609\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_BUSY~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add5~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12582_BDD12583\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12586_BDD12587\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12584_BDD12585\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_BDD8628\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8625_BDD8626\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM994\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM998\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr128~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM996\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM988\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM992\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]_OTERM3314\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_RESYN12620_BDD12621\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]_OTERM2665\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]_OTERM3338\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux15~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux14~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux18~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux17~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux16~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux7~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[0]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux93~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDoneLast~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~110_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~109_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~111_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~108_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~112_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9139_BDD9140\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9141_BDD9142\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9143_BDD9144\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector218~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1694~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1692~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1691~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1690~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1689~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1688~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1686~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal153~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1687~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1693~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1_RTM0883~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM882\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12538_BDD12539\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12536_BDD12537\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1659~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[16]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS_OTERM2181\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1701~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1700~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1699~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC_OTERM2183\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP_OTERM2185\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS_OTERM2179\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1377~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE_OTERM2189\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~46_cout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~47\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~42_cout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~43\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~38_cout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~39\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~34_cout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~35\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~30_cout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~31\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~26_cout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~27\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~22_cout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~23\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~18_cout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~19\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_OTERM2223\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE_OTERM2187\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3_OTERM2219\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_OTERM2175\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM349\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_RTM0364_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[0]_OTERM363\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[1]_OTERM2227\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2_OTERM2221\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4_OTERM2217\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector112~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[1]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[2]_OTERM2191\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[2]_OTERM2197\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[2]_OTERM2199\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_OTERM2193\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[0]_OTERM2211\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM605\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM615\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM607\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM611\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM609\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM613\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[0]_OTERM2213\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[0]_OTERM2215\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[1]_OTERM2201\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[1]_OTERM2209\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_OTERM2203\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[1]_OTERM2207\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector43~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector41~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~125_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~126\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~113_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~114\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~109_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~110\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~105_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~106\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~101_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~102\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~121_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~122\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~117_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~118\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~74\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~97_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~98\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~94\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~90\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~86\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~82\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~78\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[26]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[25]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector113~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~11\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_OTERM1143\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM776\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE_OTERM2171\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM872\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM780\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM772\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM874\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM870\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF_OTERM2173\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM774\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM778\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_OTERM1145\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector245~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~30\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector244~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector243~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector242~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector241~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector240~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~14\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector239~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~18\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector238~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector237~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~10\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector236~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~26\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector235~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux175~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~enfeeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux176~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux177~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~enfeeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux179~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~enfeeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux162~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~enfeeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux164~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux165~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~enfeeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux166~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~enfeeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux167~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~enfeeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux168~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~enfeeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux169~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~enfeeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux170~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~enfeeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux171~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~enfeeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux172~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~enfeeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux173~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux174~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~reg0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~enfeeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~en_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[30]_OTERM2157\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN8819_BDD8820\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_RESYN12786_BDD12787\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_RESYN9163_BDD9164\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13338_BDD13339\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_OTERM2546\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM355\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM353\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM347\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_163\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM351\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM449\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM465\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux404~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM463\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM467\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[32]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[32]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[32]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[32]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[32]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_OTERM2403\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[32]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector76~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[0]_OTERM2013\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[0]_OTERM2015\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM866\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1100\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1104\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM862\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM858\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM842\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM850\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM806\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM814\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM810\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM818\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_OTERM2498\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add40~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_OTERM2281\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM317\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM323\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM325\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN~100_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM581\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM587\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM589\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM591\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[0]~89_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_RESYN9299_BDD9300\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9047_BDD9048\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9045_BDD9046\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9049_BDD9050\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[8]_OTERM3236\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12938_BDD12939\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_OTERM2311\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_OTERM2313\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12934_BDD12935\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_OTERM2309\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_OTERM2279\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM309\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM307\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM311\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1_RTM0314~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM313\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM305\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM379\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM383\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM381\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13266_BDD13267\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_OTERM2492\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~91_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM585\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM579\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM583\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[1]_OTERM2277\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13262_BDD13263\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_OTERM2489\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~94_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_OTERM2275\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~95_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~96_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~93_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_OTERM2271\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9067_BDD9068\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9069_BDD9070\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9071_BDD9072\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[3]_OTERM3226\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13270_BDD13271\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_OTERM2495\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[3]_OTERM2273\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~97_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~98_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~99_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_OTERM2283\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_OTERM2507\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM387\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM389\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM385\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux428~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM447\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM443\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM435\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM445\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector104~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~87_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~88_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM455\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux427~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM451\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM453\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_OTERM2293\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_OTERM2501\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9057_BDD9058\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9055_BDD9056\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9059_BDD9060\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[5]_OTERM3232\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector103~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~82_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~83_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_OTERM2301\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM479\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux426~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM477\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM481\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM401\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM397\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM399\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13282_BDD13283\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_OTERM2504\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector102~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~79_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~80_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_OTERM2285\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux425~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM928\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM926\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_OTERM2510\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9061_BDD9062\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9063_BDD9064\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9065_BDD9066\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[7]_OTERM3228\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector101~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~85_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~86_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM820\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM393\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM395\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM391\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12906_BDD12907\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_OTERM2295\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12910_BDD12911\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_OTERM2297\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_OTERM2299\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM812\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12926_BDD12927\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_OTERM2305\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12922_BDD12923\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_OTERM2303\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9051_BDD9052\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9053_BDD9054\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]_OTERM3234\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_OTERM2307\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM816\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12890_BDD12891\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_OTERM2287\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12894_BDD12895\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_OTERM2289\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365_BDD9366\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9297_BDD9298\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9295_BDD9296\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_OTERM3230\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_OTERM2291\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM808\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[15]_OTERM1569\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM327\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM335\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM329\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM830\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM343\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM345\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM341\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM826\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_OTERM2329\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9035_BDD9036\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9037_BDD9038\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9039_BDD9040\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[13]_OTERM3242\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12966_BDD12967\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_OTERM2325\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12970_BDD12971\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_OTERM2327\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM822\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12946_BDD12947\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_OTERM2315\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12950_BDD12951\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_OTERM2317\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_OTERM2319\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9041_BDD9042\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9043_BDD9044\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[12]_OTERM3238\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM824\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM828\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM832\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_OTERM836\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_OTERM834\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM932\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM930\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM637\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM639\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux362~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM643\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux362~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM641\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13306_BDD13307\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_OTERM2522\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_OTERM2337\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM852\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_OTERM2331\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux417~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM888\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM886\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_OTERM2513\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM693\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux361~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM695\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux361~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM697\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM844\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM854\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM838\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM846\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_OTERM2516\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788_BDD12789\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12790_BDD12791\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794_BDD12795\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12792_BDD12793\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12796_BDD12797\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[18]_OTERM3244\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12984_BDD12985\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_OTERM2335\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_OTERM2333\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM848\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[19]_OTERM3240\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_OTERM2323\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13302_BDD13303\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_OTERM2519\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1491~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12958_BDD12959\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_OTERM2321\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM840\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12994_BDD12995\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_OTERM2341\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_OTERM2339\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_OTERM2531\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM663\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM657\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM655\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM856\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_OTERM2525\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1489~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13010_BDD13011\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_OTERM2351\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[21]_OTERM3248\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_OTERM2353\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM860\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_OTERM2361\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13028_BDD13029\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_OTERM2363\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_OTERM2528\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[22]_OTERM3252\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM864\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM705\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM701\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM707\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_OTERM2365\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13038_BDD13039\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_OTERM2369\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13034_BDD13035\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_OTERM2367\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_OTERM2357\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[25]_OTERM3250\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_OTERM2359\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1485~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_OTERM2355\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1131\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13048_BDD13049\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_OTERM2375\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8695_BDD8696\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8693_BDD8694\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8697_BDD8698\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[24]_OTERM3254\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13044_BDD13045\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_OTERM2373\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_OTERM2371\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1135\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1487~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN12998_BDD12999\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_OTERM2343\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM407\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM405\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM403\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_OTERM2534\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]_OTERM3246\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1137\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1133\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1141\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1139\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1106\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_OTERM2349\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_OTERM2347\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1483~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_OTERM2345\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM703\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM699\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1102\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM473\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM475\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[30]_OTERM2397\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1090\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_OTERM2377\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_OTERM2381\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8689_BDD8690\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8687_BDD8688\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8691_BDD8692\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[28]_OTERM3256\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_OTERM2379\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1088\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1086\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_OTERM2393\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1481~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13070_BDD13071\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_OTERM2389\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]_OTERM3258\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_OTERM2391\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1092\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1072\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1070\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[31]_OTERM2383\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM669\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM667\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM665\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM868\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[0]_OTERM1955\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[1]_OTERM1949\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[1]_OTERM2003\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[1]_OTERM2005\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM461\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux403~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM457\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM459\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_154\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]_OTERM2169\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_OTERM2395\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13326_BDD13327\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_OTERM2537\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector75~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[2]_OTERM1951\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_OTERM2009\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[2]_OTERM2007\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[2]_OTERM2011\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_OTERM2401\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_RTM0716_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1114\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_157\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~4_RTM01120_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1119\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1112\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1116\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[34]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[34]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_OTERM2399\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[34]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[34]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[34]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[34]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[34]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13330_BDD13331\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_OTERM2540\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[34]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[34]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[34]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[34]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]_OTERM1777\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[3]_OTERM2001\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[3]_OTERM1997\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_OTERM1999\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_OTERM2543\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[35]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[35]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[35]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM103\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM111\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_160\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM109\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[35]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[35]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_OTERM2387\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[35]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[35]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[35]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[35]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13062_BDD13063\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_OTERM2385\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[35]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[35]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[3]_OTERM1953\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[35]_OTERM1775\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[4]_OTERM1965\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[4]_OTERM2021\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_OTERM2019\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[4]_OTERM2017\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13094_BDD13095\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_OTERM2405\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM117\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_175\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM115\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM113\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_OTERM2407\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13350_BDD13351\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_OTERM2555\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[36]_OTERM1783\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[5]_OTERM1957\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[5]_OTERM2039\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[5]_OTERM2035\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_OTERM2037\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_OTERM2549\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_OTERM2417\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_OTERM2419\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM129\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_169\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM127\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM125\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[37]_OTERM1779\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[6]_OTERM1961\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_OTERM2049\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[6]_OTERM2051\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[6]_OTERM2047\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13346_BDD13347\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_OTERM2552\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[38]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[38]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[38]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[38]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[38]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[38]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM143\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM141\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_172\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~2_RTM0146_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM145\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM139\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM137\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[38]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[38]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_OTERM2429\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[38]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[38]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13138_BDD13139\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_OTERM2427\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[38]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[38]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]_OTERM1781\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[7]_OTERM1967\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[7]_OTERM2027\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_OTERM2025\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[7]_OTERM2023\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13354_BDD13355\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_OTERM2558\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13102_BDD13103\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_OTERM2409\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM361\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM357\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM359\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_166\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM123\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]_OTERM1785\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[8]_OTERM1971\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[8]_OTERM2063\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_OTERM2061\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[8]_OTERM2059\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM495\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM487\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM497\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~4_RTM0500_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM499\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_OTERM2441\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13158_BDD13159\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_OTERM2437\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13162_BDD13163\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_OTERM2439\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[40]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[40]_OTERM1793\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[9]_OTERM1959\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_OTERM2043\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[9]_OTERM2041\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[9]_OTERM2045\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM131\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM135\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[9]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM133\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_OTERM2425\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_OTERM2421\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13130_BDD13131\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_OTERM2423\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[41]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[41]_OTERM1791\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[10]_OTERM1963\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_OTERM2055\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[10]_OTERM2057\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[10]_OTERM2053\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_OTERM2435\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_OTERM2433\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13146_BDD13147\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_OTERM2431\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~2_RTM0152_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM151\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM149\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[42]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[42]_OTERM1789\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[11]_OTERM1969\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[11]_OTERM2029\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[11]_OTERM2033\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_OTERM2031\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[11]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_OTERM2413\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[43]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[43]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[43]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[43]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_OTERM2415\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[43]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM489\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM483\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~4_RTM0492_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM491\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[43]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[43]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13106_BDD13107\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_OTERM2411\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[43]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[43]_OTERM1787\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[12]_OTERM1981\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[12]_OTERM2069\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]_OTERM2065\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_OTERM2067\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13170_BDD13171\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_OTERM2443\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_OTERM2447\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM159\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13174_BDD13175\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_OTERM2445\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[44]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]_OTERM1799\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[13]_OTERM1973\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[13]_OTERM2083\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_OTERM2085\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[13]_OTERM2087\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[13]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13190_BDD13191\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_OTERM2453\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[45]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[45]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[45]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[45]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_OTERM2455\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[45]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13198_BDD13199\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_OTERM2457\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[45]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[45]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[45]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM165\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM163\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM161\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[45]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[45]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[45]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[45]_OTERM1795\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[14]_OTERM1977\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[14]_OTERM2095\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[14]_OTERM2099\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_OTERM2097\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM681\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM679\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[46]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[46]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[46]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM241\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM237\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM235\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[46]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[46]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[46]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[46]_OTERM1797\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[15]_OTERM2071\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_OTERM2073\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[15]_OTERM2075\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM671\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM673\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM675\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[47]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[47]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[47]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[47]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM295\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM293\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM291\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[47]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[47]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[47]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[47]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[15]_OTERM1983\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[15]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]_OTERM1801\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[16]_OTERM1987\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_OTERM2109\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[16]_OTERM2111\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[16]_OTERM2107\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[16]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM649\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM645\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM409\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM647\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~2_RTM0652_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM651\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_OTERM2570\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux390~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM429\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM421\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM433\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM431\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13214_BDD13215\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_OTERM2465\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[48]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[48]_OTERM1809\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[17]_OTERM1975\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[17]_OTERM2089\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[17]_OTERM2093\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_OTERM2561\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM427\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM425\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux389~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM423\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13202_BDD13203\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_OTERM2459\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~3_RTM0418_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM417\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM415\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM413\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM411\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[49]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_OTERM2091\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]_OTERM1807\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[18]_OTERM1979\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[18]_OTERM2105\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_OTERM2103\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[18]_OTERM2101\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM723\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM725\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~3_RTM0729_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM728\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[50]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[50]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[50]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13210_BDD13211\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_OTERM2463\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[50]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[50]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[50]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[50]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13362_BDD13363\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_OTERM2564\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[50]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[50]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13206_BDD13207\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_OTERM2461\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[50]_OTERM1805\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[19]_OTERM1985\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[19]_OTERM2081\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_OTERM2079\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[19]_OTERM2077\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13182_BDD13183\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_OTERM2449\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[51]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13186_BDD13187\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_OTERM2451\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[51]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[51]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM713\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM709\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~3_RTM0720_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM719\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[51]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[51]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_OTERM2567\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[51]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[51]_OTERM1803\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[20]_OTERM1993\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[20]_OTERM2113\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_OTERM2115\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[20]_OTERM2117\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13218_BDD13219\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_OTERM2467\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[52]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[52]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[52]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[52]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM619\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM627\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM629\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM625\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM621\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[52]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[52]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[52]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13222_BDD13223\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_OTERM2469\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[52]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_OTERM2589\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[52]_OTERM1813\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[21]_OTERM1989\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[21]_OTERM2133\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_OTERM2135\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[21]_OTERM2137\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~1_RTM0258_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM257\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM255\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM253\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[53]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[53]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[53]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13246_BDD13247\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_OTERM2481\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[53]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[53]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[53]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[53]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13250_BDD13251\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_OTERM2483\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[53]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[53]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_OTERM2576\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[53]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[53]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[53]_OTERM1811\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[22]_OTERM1991\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_OTERM2145\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[22]_OTERM2143\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[22]_OTERM2147\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_OTERM2584\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[54]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[54]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[54]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[54]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13386_BDD13387\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_OTERM2582\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[54]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM273\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM271\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[54]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[54]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[54]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_OTERM2587\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]_OTERM1817\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9283_BDD9284\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9285_BDD9286\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[6]_OTERM2259\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[30]_OTERM2159\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM289\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM283\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM287\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM285\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[62]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[62]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]_OTERM2624\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[62]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[62]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[62]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[62]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector46~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~116_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~112_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[25]_OTERM2129\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[24]_OTERM2149\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]_OTERM1995\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[23]_OTERM2127\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_OTERM2125\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[23]_OTERM2123\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13234_BDD13235\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_OTERM2475\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[55]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[55]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[55]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[55]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_OTERM2595\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[55]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[55]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[55]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13410_BDD13411\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_OTERM2598\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[55]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[55]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM247\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM245\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~1_RTM0250_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM249\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[55]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[55]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[55]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[55]_OTERM1815\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[0]_OTERM2247\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[24]_OTERM2151\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[0]_OTERM2250\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_OTERM2606\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_OTERM2603\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM743\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM741\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~3_RTM0747_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM746\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13414_BDD13415\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_OTERM2601\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[56]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[1]_OTERM2229\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[25]_OTERM2131\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_OTERM2479\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM631\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM635\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM633\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_OTERM2573\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13238_BDD13239\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_OTERM2477\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[57]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[1]_OTERM2232\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[2]_OTERM2238\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[2]_OTERM2235\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[26]_OTERM2141\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_OTERM2487\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_OTERM2579\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM263\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~1_RTM0266_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM265\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM261\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13254_BDD13255\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_OTERM2485\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[58]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[26]_OTERM2139\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[27]_OTERM2119\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[3]_OTERM2241\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[27]_OTERM2121\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_OTERM2592\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13226_BDD13227\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_OTERM2471\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13230_BDD13231\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_OTERM2473\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM732\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM734\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~3_RTM0738_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM737\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[59]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[3]_OTERM2244\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[28]_OTERM2163\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[4]_OTERM2262\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13442_BDD13443\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_OTERM2617\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~1_RTM0232_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM231\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM229\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13446_BDD13447\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_OTERM2620\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13438_BDD13439\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_OTERM2615\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[60]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[4]_OTERM2265\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[28]_OTERM2161\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[29]_OTERM2153\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[5]_OTERM2253\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[29]_OTERM2155\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[5]_OTERM2256\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13426_BDD13427\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_OTERM2608\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_OTERM2610\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13434_BDD13435\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_OTERM2613\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~1_RTM0280_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM279\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM277\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[61]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[31]_OTERM2165\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]_OTERM2268\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[31]_OTERM2167\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM369\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM373\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM367\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM371\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[63]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[63]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[63]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[63]_OTERM2622\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[63]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[63]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[63]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[63]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[63]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector45~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~108_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~104_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[7]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA[0]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal6~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|Equal6~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~25_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~17_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA[7]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[6]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~24_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA[6]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~23_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA[5]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~22_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA[4]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[3]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~21_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA[3]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[2]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~20_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA[2]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~19_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA[1]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO~18_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_DATA[0]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TXD~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TXD~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_DATA_WRITE[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[37]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[36]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[35]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[34]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[33]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[32]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[31]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[30]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[29]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[28]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[27]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[26]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[25]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[23]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[22]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[21]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[20]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[19]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[18]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[17]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[14]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[12]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SD_ADDR[0][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[10]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[8]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[2]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[7]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[43]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector172~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|cs_bo~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[4]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[5]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux28~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux92~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux91~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[1]~feeder_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_WE_n~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_RAS_n~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_CAS_n~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_index\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\ : std_logic_vector(4 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_enabled\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ticks\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pause\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|RESET_COUNTER\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|SD_WR\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|SD_HNDSHK_IN\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|SD_RESET\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\ : std_logic_vector(47 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|RX_COUNTER\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|TX_COUNTER\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|TIMER:TIMER1|prescale_counter\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \myVirtualToplevel|RTC_MICROSEC_TICK\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|SECOND_DOWN_TICK\ : std_logic_vector(27 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|MILLISEC_UP_TICK\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_TICK\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_TICK\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|SD_RESET_TIMER\ : std_logic_vector(6 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|SD_DATA_WRITE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|TX_BUFFER\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\ : std_logic_vector(10 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|IO_DATA_READ_SD\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|TX_COUNTER\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|RESET_COUNTER_RX\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|SD_RD\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\ : std_logic_vector(0 TO 24); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|TX_DATA\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\ : std_logic_vector(6 DOWNTO 0); +SIGNAL \myVirtualToplevel|IO_DATA_READ_SOCCFG\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|RX_COUNTER\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\ : std_logic_vector(4 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\ : std_logic_vector(6 DOWNTO 0); +SIGNAL \myVirtualToplevel|INT_ENABLE\ : std_logic_vector(16 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\ : std_logic_vector(16 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|RX_DATA\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|RX_DATA\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER\ : std_logic_vector(4 DOWNTO 0); +SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|IO_DATA_READ\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\ : std_logic_vector(0 TO 24); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|TX_BUFFER\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|RX_BUFFER\ : std_logic_vector(8 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|RX_BUFFER\ : std_logic_vector(8 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\ : std_logic_vector(0 TO 24); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1209~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM711~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM471~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM375~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM321~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM299~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[26]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[24]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[33]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[43]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[31]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[28]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[12]_NEW2314_RESYN12946_BDD12947\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[8]_NEW2310_RESYN12938_BDD12939\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]_NEW2308_RESYN12934_BDD12935\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]_NEW2304_RESYN12926_BDD12927\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]_NEW2302_RESYN12922_BDD12923\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]_NEW2296_RESYN12910_BDD12911\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[9]_NEW2294_RESYN12906_BDD12907\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]_NEW2288_RESYN12894_BDD12895\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[11]_NEW2286_RESYN12890_BDD12891\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]_NEW1860_RESYN12810_BDD12811\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]_NEW1852_RESYN12808_BDD12809\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~5_RESYN12804_BDD12805\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~23_RESYN12802_BDD12803\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN12800_BDD12801\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12796_BDD12797\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12794_BDD12795\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12792_BDD12793\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_RESYN12790_BDD12791\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_RESYN12788_BDD12789\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN12798_BDD12799\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_RESYN12786_BDD12787\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_RESYN12782_BDD12783\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_RESYN12780_BDD12781\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_RESYN12778_BDD12779\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12776_BDD12777\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12774_BDD12775\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~10_RESYN12772_BDD12773\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_RESYN12770_BDD12771\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_RESYN12768_BDD12769\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12766_BDD12767\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12764_BDD12765\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12762_BDD12763\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~5_RESYN12760_BDD12761\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~104_RESYN12758_BDD12759\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~5_RESYN12756_BDD12757\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~4_RESYN12754_BDD12755\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~2_RESYN12752_BDD12753\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_RESYN12750_BDD12751\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~3_RESYN12748_BDD12749\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~3_RESYN12746_BDD12747\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~7_RESYN12744_BDD12745\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~1_RESYN12742_BDD12743\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~0_RESYN12740_BDD12741\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_RESYN12738_BDD12739\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~0_RESYN12736_BDD12737\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~4_RESYN12734_BDD12735\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~2_RESYN12732_BDD12733\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~1_RESYN12730_BDD12731\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~0_RESYN12728_BDD12729\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~0_RESYN12726_BDD12727\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136_RESYN12724_BDD12725\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12722_BDD12723\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12720_BDD12721\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12718_BDD12719\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~0_RESYN12716_BDD12717\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~0_RESYN12714_BDD12715\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~0_RESYN12712_BDD12713\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~1_RESYN12710_BDD12711\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~0_RESYN12708_BDD12709\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_RESYN12706_BDD12707\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_RESYN12704_BDD12705\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~3_RESYN12702_BDD12703\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~2_RESYN12700_BDD12701\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_RESYN12698_BDD12699\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_RESYN12696_BDD12697\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~1_RESYN12694_BDD12695\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~0_RESYN12692_BDD12693\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_RESYN12690_BDD12691\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~16_RESYN12688_BDD12689\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~60_RESYN12686_BDD12687\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~43_RESYN12684_BDD12685\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~35_RESYN12682_BDD12683\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~25_RESYN12680_BDD12681\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_RESYN12678_BDD12679\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_RESYN12676_BDD12677\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_RESYN12674_BDD12675\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_RESYN12672_BDD12673\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_RESYN12670_BDD12671\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664_BDD12665\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_RESYN12652_BDD12653\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_RESYN12644_BDD12645\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~8_RESYN12642_BDD12643\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_RESYN12640_BDD12641\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_RESYN12638_BDD12639\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_RESYN12636_BDD12637\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~6_RESYN12634_BDD12635\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~4_RESYN12630_BDD12631\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_RESYN12632_BDD12633\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~7_RESYN12628_BDD12629\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_RESYN12626_BDD12627\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~1_RESYN12624_BDD12625\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_RESYN12622_BDD12623\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~13_RESYN12620_BDD12621\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_RESYN12618_BDD12619\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_RESYN12614_BDD12615\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_RESYN12612_BDD12613\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_BUSY~1_RESYN12610_BDD12611\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_BUSY~1_RESYN12608_BDD12609\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal4~0_RESYN12606_BDD12607\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_LessThan0~0_RESYN12604_BDD12605\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN12594_BDD12595\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN12592_BDD12593\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_RESYN12590_BDD12591\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_RESYN12588_BDD12589\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12586_BDD12587\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12584_BDD12585\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12582_BDD12583\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~6_RESYN12564_BDD12565\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~11_RESYN12558_BDD12559\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN12556_BDD12557\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN12554_BDD12555\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~15_RESYN12546_BDD12547\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12544_BDD12545\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12542_BDD12543\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_RESYN12538_BDD12539\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_RESYN12536_BDD12537\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~13_RESYN12534_BDD12535\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_RESYN12532_BDD12533\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_RESYN12530_BDD12531\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~3_RESYN12528_BDD12529\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_RESYN12526_BDD12527\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_RESYN12524_BDD12525\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~3_RESYN12522_BDD12523\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~1_RESYN12520_BDD12521\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~5_RESYN12518_BDD12519\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~4_RESYN12516_BDD12517\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~2_RESYN12514_BDD12515\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~1_RESYN12512_BDD12513\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_RESYN12510_BDD12511\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~4_RESYN12508_BDD12509\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~1_RESYN12504_BDD12505\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_RESYN12502_BDD12503\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_RESYN12500_BDD12501\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~90_RESYN12496_BDD12497\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~3_RESYN12492_BDD12493\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~87_RESYN12490_BDD12491\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~0_RESYN12488_BDD12489\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~1_RESYN12486_BDD12487\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~5_RESYN12484_BDD12485\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~19_RESYN12470_BDD12471\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_RESYN12464_BDD12465\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_RESYN12462_BDD12463\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~1_RESYN12460_BDD12461\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_RESYN12454_BDD12455\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_RESYN12452_BDD12453\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~2_RESYN12434_BDD12435\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~2_RESYN12432_BDD12433\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~2_RESYN12430_BDD12431\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~2_RESYN12428_BDD12429\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~2_RESYN12426_BDD12427\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~2_RESYN12424_BDD12425\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~2_RESYN12422_BDD12423\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~5_RESYN12420_BDD12421\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416_BDD12417\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414_BDD12415\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_RESYN12412_BDD12413\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_RESYN12410_BDD12411\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_RESYN12408_BDD12409\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_RESYN12406_BDD12407\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_RESYN12404_BDD12405\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_RESYN12402_BDD12403\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_RESYN12400_BDD12401\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_RESYN12398_BDD12399\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_RESYN12396_BDD12397\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_RESYN12394_BDD12395\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_RESYN12388_BDD12389\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_RESYN12386_BDD12387\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_RESYN12370_BDD12371\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365_BDD9366\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9077_RESYN9359_BDD9360\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9357_BDD9358\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9355_BDD9356\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9349_BDD9350\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9347_BDD9348\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9345_BDD9346\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN9337_BDD9338\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9335_BDD9336\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9333_BDD9334\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8847_RESYN9325_BDD9326\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8845_RESYN9323_BDD9324\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_RESYN9015_RESYN9351_BDD9352\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9315_BDD9316\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9313_BDD9314\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9311_BDD9312\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~164_RESYN9307_BDD9308\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN9301_BDD9302\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_RESYN9299_BDD9300\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_RESYN9297_BDD9298\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_RESYN9295_BDD9296\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_RESYN9285_BDD9286\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_RESYN9283_BDD9284\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9277_BDD9278\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_BDD9276\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9269_BDD9270\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9267_BDD9268\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9263_BDD9264\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~4_RESYN9251_BDD9252\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~1_RESYN9249_BDD9250\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_RESYN9247_BDD9248\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_RESYN9245_BDD9246\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9239_BDD9240\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9237_BDD9238\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9235_BDD9236\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9233_BDD9234\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9231_BDD9232\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9229_BDD9230\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9225_BDD9226\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_RESYN9223_BDD9224\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_RESYN9221_BDD9222\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_RESYN9217_BDD9218\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_RESYN9215_BDD9216\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_RESYN9213_BDD9214\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~24_RESYN9207_BDD9208\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195_BDD9196\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193_BDD9194\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189_BDD9190\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9179_BDD9180\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9177_BDD9178\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9175_BDD9176\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9173_BDD9174\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_RESYN9171_BDD9172\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_RESYN9169_BDD9170\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_RESYN9167_BDD9168\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_RESYN9165_BDD9166\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~12_RESYN9163_BDD9164\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_BDD9162\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9159_BDD9160\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9157_BDD9158\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~0_RESYN9155_BDD9156\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_RESYN9151_BDD9152\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_RESYN9149_BDD9150\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_RESYN9147_BDD9148\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_RESYN9145_BDD9146\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9143_BDD9144\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9141_BDD9142\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9139_BDD9140\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_RESYN9127_BDD9128\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_RESYN9125_BDD9126\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_CS_RESYN9121_BDD9122\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_CS_RESYN9119_BDD9120\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_SELECT_RESYN9117_BDD9118\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8707_RESYN9111_BDD9112\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_RESYN9109_BDD9110\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_RESYN9107_BDD9108\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_SELECT_RESYN9115_BDD9116\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8467_RESYN9093_BDD9094\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8459_RESYN9091_BDD9092\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8447_RESYN9089_BDD9090\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_BDD9076\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9071_BDD9072\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9069_BDD9070\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9067_BDD9068\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9065_BDD9066\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9063_BDD9064\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9061_BDD9062\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9059_BDD9060\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9057_BDD9058\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9055_BDD9056\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_RESYN9053_BDD9054\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_RESYN9051_BDD9052\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9049_BDD9050\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9047_BDD9048\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9045_BDD9046\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_RESYN9043_BDD9044\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_RESYN9041_BDD9042\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9039_BDD9040\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9037_BDD9038\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9035_BDD9036\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_RESYN9033_BDD9034\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_RESYN9031_BDD9032\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9029_BDD9030\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9027_BDD9028\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9025_BDD9026\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~3_RESYN9023_BDD9024\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~3_RESYN9021_BDD9022\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_RESYN9019_BDD9020\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_RESYN9017_BDD9018\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_RESYN9015_BDD9016\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~14_RESYN9011_BDD9012\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_RESYN9009_BDD9010\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN9003_BDD9004\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8999_BDD9000\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8997_BDD8998\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8995_BDD8996\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~9_RESYN8993_BDD8994\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_RESYN8987_BDD8988\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_RESYN8985_BDD8986\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_BDD8984\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8979_BDD8980\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_RESYN8977_BDD8978\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_RESYN8975_BDD8976\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8973_BDD8974\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8971_BDD8972\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~3_RESYN8969_BDD8970\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8967_BDD8968\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_BDD8966\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_BDD8964\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~4_RESYN8961_BDD8962\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_RESYN8959_BDD8960\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_RESYN8957_BDD8958\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_RESYN8955_BDD8956\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_RESYN8953_BDD8954\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_RESYN8941_BDD8942\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8939_BDD8940\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8937_BDD8938\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~0_RESYN8935_BDD8936\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~63_RESYN8929_BDD8930\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~24_RESYN8923_BDD8924\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_RESYN8921_BDD8922\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883_BDD8884\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879_BDD8880\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8877_BDD8878\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8875_BDD8876\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8873_BDD8874\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_RESYN8869_BDD8870\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_RESYN8867_BDD8868\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_RESYN8861_BDD8862\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_RESYN8859_BDD8860\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8853_BDD8854\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_BDD8852\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8849_BDD8850\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8847_BDD8848\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8845_BDD8846\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_RESYN8843_BDD8844\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_RESYN8841_BDD8842\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~3_RESYN8837_BDD8838\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~10_RESYN8833_BDD8834\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~10_RESYN8831_BDD8832\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~4_RESYN8829_BDD8830\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8827_BDD8828\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8825_BDD8826\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8823_BDD8824\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_RESYN8819_BDD8820\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~0_RESYN8809_BDD8810\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8803_BDD8804\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_RESYN8791_BDD8792\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~9_RESYN8789_BDD8790\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_RESYN8785_BDD8786\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_RESYN8783_BDD8784\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~6_RESYN8781_BDD8782\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_RESYN8777_BDD8778\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_RESYN8775_BDD8776\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_RESYN8773_BDD8774\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_RESYN8771_BDD8772\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_RESYN8769_BDD8770\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_RESYN8767_BDD8768\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_INTR0_CS_RESYN8755_BDD8756\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SOCCFG_CS_RESYN8753_BDD8754\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~5_RESYN8749_BDD8750\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~5_RESYN8745_BDD8746\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~92_RESYN8741_BDD8742\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~90_RESYN8739_BDD8740\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~88_RESYN8737_BDD8738\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~86_RESYN8735_BDD8736\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~84_RESYN8733_BDD8734\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~82_RESYN8731_BDD8732\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~80_RESYN8729_BDD8730\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~78_RESYN8727_BDD8728\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~76_RESYN8725_BDD8726\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~74_RESYN8723_BDD8724\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~72_RESYN8721_BDD8722\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~70_RESYN8719_BDD8720\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~68_RESYN8717_BDD8718\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~5_RESYN8715_BDD8716\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8711_BDD8712\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8709_BDD8710\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8707_BDD8708\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8705_BDD8706\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8703_BDD8704\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8701_BDD8702\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8699_BDD8700\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8697_BDD8698\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8695_BDD8696\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8693_BDD8694\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8691_BDD8692\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8689_BDD8690\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8687_BDD8688\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_RESYN8685_BDD8686\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_RESYN8683_BDD8684\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8681_BDD8682\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8679_BDD8680\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8677_BDD8678\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_RESYN8675_BDD8676\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_RESYN8673_BDD8674\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~119_RESYN8671_BDD8672\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_RESYN8669_BDD8670\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_RESYN8667_BDD8668\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_RESYN8665_BDD8666\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_RESYN8663_BDD8664\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8661_BDD8662\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8659_BDD8660\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8657_BDD8658\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~94_RESYN8655_BDD8656\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8651_BDD8652\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8649_BDD8650\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8647_BDD8648\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[21]~1_RESYN8641_BDD8642\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[21]~1_RESYN8639_BDD8640\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_BDD8636\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_RESYN8633_BDD8634\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_RESYN8631_BDD8632\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_BDD8628\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8625_BDD8626\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_RESYN8623_BDD8624\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_RESYN8621_BDD8622\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_RESYN8619_BDD8620\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~8_RESYN8629_BDD8630\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~6_RESYN8617_BDD8618\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~8_RESYN8615_BDD8616\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~2_RESYN8613_BDD8614\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~2_RESYN8605_BDD8606\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~81_RESYN8603_BDD8604\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~58_RESYN8601_BDD8602\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~48_RESYN8599_BDD8600\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~40_RESYN8597_BDD8598\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~31_RESYN8595_BDD8596\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector573~1_RESYN8589_BDD8590\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector507~1_RESYN8587_BDD8588\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585_BDD8586\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector639~1_RESYN8583_BDD8584\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575_BDD8576\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector771~2_RESYN8571_BDD8572\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561_BDD8562\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559_BDD8560\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557_BDD8558\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_BDD8556\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547_BDD8548\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545_BDD8546\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529_BDD8530\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527_BDD8528\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513_BDD8514\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501_BDD8502\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_RESYN8497_BDD8498\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_RESYN8495_BDD8496\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~4_RESYN8493_BDD8494\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_RESYN8491_BDD8492\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_RESYN8489_BDD8490\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_RESYN8487_BDD8488\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_RESYN8483_BDD8484\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~4_RESYN8479_BDD8480\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_RESYN8475_BDD8476\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_RESYN8473_BDD8474\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8469_BDD8470\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8467_BDD8468\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_RESYN8465_BDD8466\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_RESYN8463_BDD8464\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8461_BDD8462\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8459_BDD8460\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~6_RESYN8457_BDD8458\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_RESYN8455_BDD8456\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_RESYN8453_BDD8454\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8449_BDD8450\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8447_BDD8448\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~5_RESYN8445_BDD8446\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~5_RESYN8443_BDD8444\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8437_BDD8438\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8435_BDD8436\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_RESYN8429_BDD8430\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_RESYN8427_BDD8428\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_RESYN8425_BDD8426\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_RESYN8423_BDD8424\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_RESYN8413_BDD8414\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_RESYN8411_BDD8412\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_RESYN13466_BDD13467\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_RESYN13464_BDD13465\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_RESYN8959_RESYN13462_BDD13463\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_RESYN8941_RESYN13460_BDD13461\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8937_RESYN13458_BDD13459\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]_NEW2619_RESYN13446_BDD13447\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]_NEW2616_RESYN13442_BDD13443\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]_NEW2614_RESYN13438_BDD13439\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]_NEW2612_RESYN13434_BDD13435\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]_NEW2607_RESYN13426_BDD13427\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]_NEW2600_RESYN13414_BDD13415\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[55]_NEW2597_RESYN13410_BDD13411\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]_NEW2581_RESYN13386_BDD13387\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[50]_NEW2563_RESYN13362_BDD13363\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[39]_NEW2557_RESYN13354_BDD13355\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]_NEW2554_RESYN13350_BDD13351\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[38]_NEW2551_RESYN13346_BDD13347\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[32]_NEW2545_RESYN13338_BDD13339\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]_NEW2539_RESYN13330_BDD13331\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]_NEW2536_RESYN13326_BDD13327\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]_NEW2521_RESYN13306_BDD13307\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]_NEW2518_RESYN13302_BDD13303\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]_NEW2503_RESYN13282_BDD13283\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[3]_NEW2494_RESYN13270_BDD13271\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[2]_NEW2491_RESYN13266_BDD13267\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]_NEW2488_RESYN13262_BDD13263\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[58]_NEW2484_RESYN13254_BDD13255\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]_NEW2482_RESYN13250_BDD13251\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]_NEW2480_RESYN13246_BDD13247\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]_NEW2476_RESYN13238_BDD13239\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]_NEW2474_RESYN13234_BDD13235\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]_NEW2472_RESYN13230_BDD13231\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]_NEW2470_RESYN13226_BDD13227\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[52]_NEW2468_RESYN13222_BDD13223\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[52]_NEW2466_RESYN13218_BDD13219\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]_NEW2464_RESYN13214_BDD13215\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]_NEW2462_RESYN13210_BDD13211\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[50]_NEW2460_RESYN13206_BDD13207\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]_NEW2458_RESYN13202_BDD13203\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]_NEW2456_RESYN13198_BDD13199\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[45]_NEW2452_RESYN13190_BDD13191\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[51]_NEW2450_RESYN13186_BDD13187\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[51]_NEW2448_RESYN13182_BDD13183\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]_NEW2444_RESYN13174_BDD13175\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]_NEW2442_RESYN13170_BDD13171\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]_NEW2438_RESYN13162_BDD13163\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]_NEW2436_RESYN13158_BDD13159\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]_NEW2430_RESYN13146_BDD13147\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[38]_NEW2426_RESYN13138_BDD13139\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]_NEW2422_RESYN13130_BDD13131\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[43]_NEW2410_RESYN13106_BDD13107\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]_NEW2408_RESYN13102_BDD13103\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]_NEW2404_RESYN13094_BDD13095\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[29]_NEW2388_RESYN13070_BDD13071\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]_NEW2384_RESYN13062_BDD13063\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]_NEW2374_RESYN13048_BDD13049\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]_NEW2372_RESYN13044_BDD13045\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[26]_NEW2368_RESYN13038_BDD13039\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[26]_NEW2366_RESYN13034_BDD13035\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[22]_NEW2362_RESYN13028_BDD13029\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[21]_NEW2350_RESYN13010_BDD13011\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[23]_NEW2342_RESYN12998_BDD12999\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]_NEW2340_RESYN12994_BDD12995\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]_NEW2334_RESYN12984_BDD12985\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[13]_NEW2326_RESYN12970_BDD12971\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]_NEW2324_RESYN12966_BDD12967\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[19]_NEW2320_RESYN12958_BDD12959\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[12]_NEW2316_RESYN12950_BDD12951\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_CR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_SPLITSPACE~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_INT_ENABLE[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_INT_ENABLE[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_End~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_NOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_PRECR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_DATA_VALID~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_RESET_TIMER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_CLOCK~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_DATA_LOADED~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[34]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[38]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[26]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[30]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[35]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[32]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[48]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[37]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[42]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[40]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[52]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[44]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[47]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[49]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[30]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[25]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[31]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[29]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[27]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[26]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[28]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[25]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[26]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[7]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[10]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_RESET_TIMER[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[11]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[5]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[13]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[12]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[19]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[20]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[22]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount[3]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[9]~DUPLICATE_q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~131_Duplicate_173\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~111_Duplicate_170\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~127_Duplicate_167\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~107_Duplicate_164\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~95_Duplicate_161\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~99_Duplicate_158\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_155\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~65_Duplicate_152\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[0]_OTERM1619\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]_OTERM1617\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]_OTERM1615\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1613\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1611\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1609\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]_OTERM1607\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]_OTERM1605\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]_OTERM1603\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]_OTERM1601\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]_OTERM1599\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]_OTERM1597\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1595\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1593\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[1]_OTERM1587\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[1]_OTERM1585\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]_OTERM1583\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]_OTERM1581\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1577\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]_OTERM1573\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]_OTERM1571\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[15]_OTERM1569\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1567\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1565\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1563\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1561\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[1]_OTERM1559\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]_OTERM1557\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]_OTERM1555\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]_OTERM1553\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]_OTERM1551\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1549\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1547\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1545\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1543\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1541\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1539\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1537\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[1]_OTERM1535\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1533\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1531\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1529\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1527\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1519\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1515\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1511\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1505\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1501\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]_OTERM1497\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]_OTERM1495\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1493\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1491\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1489\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1485\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1483\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]_OTERM1481\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]_OTERM1479\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1477\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1475\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1473\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1471\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1469\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1467\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1465\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1463\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1461\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1459\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1457\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1455\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]_OTERM1447\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]_OTERM1445\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1443\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1441\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1439\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1437\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1435\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1433\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1431\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1429\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1427\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1425\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1423\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1421\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1419\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]_OTERM1411\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]_OTERM1409\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]_OTERM1401\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]_OTERM1399\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1395\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[20]_OTERM1389\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[20]_OTERM1387\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1385\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1383\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1381\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1379\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]_OTERM1377\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]_OTERM1375\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1357\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1355\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1353\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1351\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1349\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1347\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1345\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1343\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1341\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1339\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1337\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1335\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1333\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1331\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1329\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1327\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1325\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1323\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1321\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1319\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1317\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1315\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1313\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1309\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[23]_OTERM1307\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[23]_OTERM1305\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1303\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1301\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1297\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1283\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1281\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1279\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1277\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1275\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1271\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1269\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1267\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1265\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1263\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1261\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1259\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1255\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1253\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1251\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[9]_OTERM1249\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[7]_OTERM1247\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[5]_OTERM1245\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[6]_OTERM1243\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[12]_OTERM1241\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[16]_OTERM1239\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[17]_OTERM1237\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[18]_OTERM1235\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[19]_OTERM1233\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[10]_OTERM1231\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[10]_OTERM1229\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[11]_OTERM1227\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[4]_OTERM1225\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[1]_OTERM1223\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[8]_OTERM1221\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1219\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[21]_OTERM1215\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[20]_OTERM1213\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1209\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1205\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1203\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1201\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1199\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1197\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1195\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1193\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1191\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[13]_OTERM1189\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[13]_OTERM1187\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1185\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1183\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1181\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]_OTERM1179\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]_OTERM1177\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[22]_OTERM1175\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1173\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1169\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1159\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1157\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_END_OTERM1145\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_END_OTERM1143\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]_OTERM1141\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]_OTERM1139\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]_OTERM1137\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]_OTERM1135\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]_OTERM1133\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]_OTERM1131\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1119\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1116\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1114\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1112\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1110\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1108\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]_OTERM1106\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]_OTERM1104\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]_OTERM1102\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]_OTERM1100\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]_OTERM1092\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]_OTERM1090\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]_OTERM1088\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]_OTERM1086\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1084\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1082\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1080\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1078\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1076\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1074\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]_OTERM1072\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]_OTERM1070\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1054\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1052\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM998\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM996\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM994\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM992\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM990\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM988\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM984\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[29]_OTERM970\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM948\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]_OTERM936\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]_OTERM934\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[16]_OTERM932\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[16]_OTERM930\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[7]_OTERM928\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[7]_OTERM926\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]_OTERM924\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]_OTERM922\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]_OTERM920\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]_OTERM918\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]_OTERM916\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]_OTERM914\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]_OTERM912\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]_OTERM910\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]_OTERM908\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]_OTERM906\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[26]_OTERM904\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM902\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM900\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM898\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM896\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM894\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM892\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM890\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[17]_OTERM888\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[17]_OTERM886\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM882\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM880\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM878\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM876\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM874\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM872\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM870\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]_OTERM868\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]_OTERM866\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]_OTERM864\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]_OTERM862\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]_OTERM860\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]_OTERM858\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]_OTERM856\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]_OTERM854\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]_OTERM852\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]_OTERM850\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]_OTERM848\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]_OTERM846\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]_OTERM844\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]_OTERM842\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]_OTERM840\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]_OTERM838\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]_OTERM836\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]_OTERM834\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]_OTERM832\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]_OTERM830\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]_OTERM828\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]_OTERM826\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]_OTERM824\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]_OTERM822\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]_OTERM820\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]_OTERM818\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]_OTERM816\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]_OTERM814\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]_OTERM812\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]_OTERM810\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM808\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM806\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[28]_OTERM800\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[28]_OTERM798\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM796\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM792\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM790\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM788\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM784\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM782\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM780\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM778\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM776\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM774\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM772\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]_OTERM770\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]_OTERM768\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]_OTERM766\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]_OTERM764\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]_OTERM762\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]_OTERM760\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]_OTERM758\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]_OTERM756\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM754\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM750\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM746\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM743\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM741\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM737\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM734\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM732\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM728\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM725\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM723\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM719\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM715\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM713\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM711\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM709\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[26]_OTERM707\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[26]_OTERM705\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM703\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM701\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM699\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM697\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM695\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM693\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM691\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM689\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM687\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM685\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM683\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM681\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM679\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM677\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM675\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM673\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM671\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM669\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM667\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM665\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM663\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM661\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM659\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM657\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM655\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM651\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM649\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM647\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM645\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM643\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM641\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM639\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM637\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM635\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM633\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM631\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM629\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM627\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM625\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM623\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM621\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM619\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM617\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM615\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM613\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM611\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM609\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM607\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM605\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM603\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM601\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM599\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM597\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM595\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM593\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM591\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM589\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM587\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM585\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM583\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM581\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM579\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM577\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM575\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM573\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM571\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM569\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM567\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM565\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM563\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM561\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM559\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM557\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM555\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM553\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM551\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM549\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM547\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM545\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM543\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM541\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM539\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM537\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM535\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM533\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM531\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM529\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM527\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM525\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM523\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM521\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM519\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM517\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM515\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM513\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM511\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM507\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM499\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM497\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM495\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM491\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM489\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM487\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM485\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM483\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM481\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM479\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM477\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM475\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM473\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM471\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM469\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM467\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM465\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM463\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM461\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM459\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM457\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM455\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM453\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM451\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM449\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM447\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM445\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM443\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM437\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM435\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM433\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM431\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM429\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM427\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM425\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM423\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM421\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM417\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM415\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM413\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM411\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM409\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM407\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM405\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM403\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM401\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM399\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM397\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM395\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM393\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM391\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM389\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM387\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM385\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM383\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM381\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM379\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM377\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM375\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM373\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM371\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM369\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM367\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_SPLIT_DATA[0]_OTERM363\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM361\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM359\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM357\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM355\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM353\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM351\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM349\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM347\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM345\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM343\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM341\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM339\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM337\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM335\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM333\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM329\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM327\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM325\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM323\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM321\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM317\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM313\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM311\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM309\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM307\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM305\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM303\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM301\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM299\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM297\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM295\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM293\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM291\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM289\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM287\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM285\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM283\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM279\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM277\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM275\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM273\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM271\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM269\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM265\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM263\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM261\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM257\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM255\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM253\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM249\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM247\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM245\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM243\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM241\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM239\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM237\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM235\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM231\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM229\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM227\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM225\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM223\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM165\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM163\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM161\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM159\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM157\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM155\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]_OTERM151\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]_OTERM149\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM145\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM143\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM141\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM139\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM137\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM135\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM133\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM131\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM129\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM127\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM125\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM123\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM121\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM119\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM117\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM115\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM113\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM111\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM109\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM107\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM103\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[12]_OTERM101\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[13]_OTERM99\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[14]_OTERM97\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[15]_OTERM95\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]_OTERM93\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]_OTERM91\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]_OTERM89\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector77~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\ : std_logic_vector(63 DOWNTO 1); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux316~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux316~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux370~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux370~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux340~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux340~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux402~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux402~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux118~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux118~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux54~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux54~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux182~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux182~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux246~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux246~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux312~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux312~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux366~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux366~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux336~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux336~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux398~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux398~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux114~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux114~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux50~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux50~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux178~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux178~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux242~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux242~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\ : std_logic_vector(63 DOWNTO 1); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1455~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1455~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1391~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\ : std_logic_vector(30 DOWNTO 1); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1571~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1571~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1453~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1453~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector79~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux318~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux318~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux372~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux372~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux342~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux342~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux404~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux404~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux120~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux120~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux56~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux56~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux184~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux184~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux248~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux248~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector75~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux314~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux314~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux368~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux368~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux338~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux338~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux400~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux400~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux116~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux116~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux52~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux52~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux180~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux180~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux244~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux244~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1457~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1457~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1393~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1573~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1573~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1452~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1452~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1388~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector78~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux317~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux317~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux371~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux371~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux341~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux341~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux403~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux403~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux119~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux119~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux55~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux55~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux183~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux183~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux247~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux247~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux313~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux313~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux367~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux367~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux337~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux337~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux399~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux399~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux115~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux115~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux51~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux51~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux179~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux179~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux243~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux243~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1456~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1456~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1392~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1572~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1572~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\ : std_logic_vector(16 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\ : std_logic_vector(4 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1377~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[41]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\ : std_logic_vector(47 DOWNTO 1); +SIGNAL \myVirtualToplevel|ALT_INV_SD_DATA_WRITE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[41]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~23_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\ : std_logic_vector(24 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\ : std_logic_vector(16 DOWNTO 0); +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][20]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][19]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][18]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][14]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][17]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][22]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][24]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][25]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][26]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][16]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][15]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][27]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][23]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][21]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][29]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][28]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][31]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][30]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_TIMER_REG_REQ~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\ : std_logic_vector(16 DOWNTO 8); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector117~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector76~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux315~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux315~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux369~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux369~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux339~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux339~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux401~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux401~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux117~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux117~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux53~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux53~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux181~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux181~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux245~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux245~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1454~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1454~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux311~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux311~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux365~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux365~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux335~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux335~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux397~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux397~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux113~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux113~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux49~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux49~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux177~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux177~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux241~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux241~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1450~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1450~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1386~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1383~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1383~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux308~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux308~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux362~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux362~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux332~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux332~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux394~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux394~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux110~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux110~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux46~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux46~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux304~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux304~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux358~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux358~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux328~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux328~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux390~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux390~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux106~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux106~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux42~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux42~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux170~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux170~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux234~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux234~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux310~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux310~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux364~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux364~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux334~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux334~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux396~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux396~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux112~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux112~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux48~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux48~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux176~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux176~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux240~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux240~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\ : std_logic_vector(63 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux306~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux306~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux360~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux360~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux330~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux330~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux392~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux392~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux108~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux108~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux44~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux44~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux172~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux172~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux236~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux236~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1449~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1449~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1385~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[62]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1384~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1384~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux309~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux309~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux363~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux363~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux333~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux333~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux395~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux395~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux111~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux111~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux47~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux47~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux305~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux305~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux359~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux359~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux329~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux329~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux391~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux391~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux107~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux107~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux43~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux43~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux171~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux171~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux235~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux235~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux208~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux208~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux272~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux272~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1481~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1417~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]~81_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector99~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux140~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux140~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux76~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux76~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux204~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux204~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux268~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux268~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1477~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1535~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1535~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~79_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector102~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux79~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux79~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]~77_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector98~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux139~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux139~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux75~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux75~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux203~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux203~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux267~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux267~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1476~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1476~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1534~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1534~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1478~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1536~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1536~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]~76_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector100~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux141~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux141~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux77~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux77~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux205~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux205~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux269~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux269~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]~75_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector96~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux137~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux137~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux73~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux73~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux201~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux201~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux265~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux265~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1474~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1474~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1532~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1532~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]~74_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector93~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux134~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux134~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux70~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux70~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux198~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux198~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux262~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux262~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1471~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1471~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1529~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1529~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1585~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]~73_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector89~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux130~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux130~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux66~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux66~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux194~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux194~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux258~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux258~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1467~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1467~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector95~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux136~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux136~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux72~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux72~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux200~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux200~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux264~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux264~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1473~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1473~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1531~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1531~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]~71_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector91~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux132~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux132~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux68~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux68~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux196~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux196~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux260~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux260~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\ : std_logic_vector(33 DOWNTO 3); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1469~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1469~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]~70_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector94~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux135~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux135~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux71~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux71~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux199~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux199~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux263~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux263~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1472~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1472~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1530~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1530~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector90~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux131~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux131~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux67~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux67~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux195~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux195~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux259~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux259~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1468~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1468~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~25_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector115~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector92~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux133~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux133~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux69~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux69~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux197~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux197~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux261~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux261~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1470~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1470~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector88~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux129~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux129~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux65~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux65~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux193~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux193~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux257~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux257~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1466~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1466~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector85~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux126~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux126~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux62~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux62~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1399~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector81~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux320~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux320~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux374~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux374~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux344~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux344~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux406~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux406~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux122~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux122~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux58~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux58~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux186~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux186~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux250~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux250~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1459~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1459~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1575~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1575~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector87~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux128~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux128~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux64~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux64~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux192~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux192~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux256~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux256~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1465~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1465~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector83~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux322~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux322~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux408~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux408~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux376~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux376~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux124~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux124~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux60~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux60~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux188~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux188~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux252~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux252~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1461~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1577~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1577~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector86~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux127~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux127~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux63~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux63~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1400~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector82~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux321~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux321~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux375~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux375~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux345~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux345~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux407~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux407~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux123~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux123~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux59~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux59~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux187~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux187~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux251~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux251~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1460~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1460~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1576~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1576~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[40]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[40]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[6]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~24_q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_index\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux409~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux409~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux377~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux377~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux125~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux125~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux61~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux61~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux189~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux189~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux253~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux253~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector84~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux323~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux323~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1462~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1398~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1398~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1578~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1578~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector80~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux319~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux319~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux373~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux373~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux343~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux343~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux405~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux405~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux121~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux121~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux57~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux57~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux185~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux185~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux249~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux249~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1458~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1458~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1574~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1574~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1451~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1451~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]_OTERM87\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]_OTERM85\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]_OTERM83\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]_OTERM81\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]_OTERM79\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[16]_OTERM77\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[21]_OTERM75\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[22]_OTERM73\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[20]_OTERM71\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[23]_OTERM69\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[17]_OTERM67\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[18]_OTERM65\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[19]_OTERM63\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]_OTERM61\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]_OTERM59\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM57\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM55\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[9]_OTERM53\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[10]_OTERM51\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[11]_OTERM49\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM47\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM45\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM43\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM41\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[8]_OTERM39\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]_OTERM37\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]_OTERM35\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM33\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM31\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]_OTERM29\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]_OTERM27\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]_OTERM25\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]_OTERM23\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]_OTERM21\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]_OTERM19\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM17\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM15\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]_OTERM11\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]_OTERM9\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM5\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\ : std_logic; +SIGNAL \mypll|altpll_component|auto_generated|ALT_INV_wire_generic_pll1_locked\ : std_logic; +SIGNAL \ALT_INV_UART_RX_1~input_o\ : std_logic; +SIGNAL \ALT_INV_UART_RX_0~input_o\ : std_logic; +SIGNAL \ALT_INV_SDCARD_MISO[0]~input_o\ : std_logic; +SIGNAL \ALT_INV_KEY~input_o\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~438_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~436_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~435_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~160_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~166_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~165_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~434_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~433_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~432_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~431_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~430_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~429_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~428_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~427_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~426_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1429~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~164_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~90_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~88_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~86_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~84_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~82_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~80_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~76_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~74_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~70_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector214~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector213~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector212~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector211~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector210~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector209~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector208~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector207~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector206~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector205~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector204~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector203~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector202~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector201~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector199~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector198~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector197~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector196~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector195~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector194~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector193~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~157_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~156_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~155_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~152_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~150_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~149_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector157~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector157~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[3]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector154~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[5]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[6]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[9]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[11]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[13]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[15]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[16]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1561~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1561~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1563~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1563~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1506~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1562~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1562~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1508~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1564~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1564~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR:tInsnExec~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux428~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1560~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1560~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1501~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1501~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux425~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1557~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1557~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1497~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1497~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1503~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1559~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1559~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1499~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1499~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1437~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1437~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1502~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1440~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1440~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1558~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1558~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1498~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1498~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1500~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1500~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1496~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1496~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux282~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux282~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux154~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux154~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux90~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux90~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux218~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux218~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1491~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1427~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1495~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1495~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add40~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux284~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux284~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux156~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux156~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux92~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux92~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1493~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1429~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux283~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux283~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux155~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux155~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux91~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux91~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux219~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux219~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1548~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1548~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux93~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux93~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux285~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux285~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux157~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux157~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux221~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux221~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1494~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux418~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux418~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1550~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1550~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux153~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux153~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux89~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux89~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux217~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux217~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux281~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux281~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1546~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1546~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux150~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux150~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux86~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux86~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux214~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux214~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux278~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux278~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1487~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1599~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[3]~98_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[3]~97_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux146~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux146~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux82~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux82~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux210~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux210~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux274~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux274~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1483~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux152~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux152~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux88~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux88~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux216~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux216~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux280~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux280~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1489~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1425~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~95_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~94_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux148~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux148~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux84~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux84~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux212~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux212~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux276~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux276~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1485~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1421~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux151~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux151~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux87~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux87~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux215~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux215~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux279~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux279~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1544~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1544~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[2]~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[2]~91_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~90_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux147~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux147~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux83~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux83~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux211~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux211~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux275~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux275~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux149~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux149~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux85~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux85~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux213~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux213~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux277~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux277~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[4]~87_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector104~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux145~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux145~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux81~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux81~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux209~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux209~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux273~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux273~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[7]~85_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector101~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux142~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux142~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux78~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux78~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1415~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]~84_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector97~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux138~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux138~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux74~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux74~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux202~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux202~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux266~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux266~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1475~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1475~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1533~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1533~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[5]~82_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector103~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux144~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux144~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux80~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux80~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~22_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~19_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\ : std_logic_vector(24 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\ : std_logic_vector(8 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~19_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\ : std_logic_vector(24 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\ : std_logic_vector(8 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~18_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~18_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][31]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescaled_tick~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\ : std_logic_vector(10 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector300~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector298~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector295~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector297~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_PreSetAddr~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux307~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux307~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux361~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux361~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux331~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux331~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux393~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux393~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux109~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux109~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux45~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux45~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux173~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux173~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux237~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux237~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux303~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux303~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux357~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux357~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux327~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux327~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux389~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux389~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux105~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux105~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux41~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux41~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux169~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux169~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux233~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux233~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux350~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux350~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux290~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux290~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux382~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux382~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux296~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux296~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux98~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux98~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux34~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux34~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux162~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux162~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux226~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux226~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux300~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux300~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux354~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux354~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux324~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux324~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux386~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux386~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux102~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux102~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux38~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux38~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux166~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux166~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux230~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux230~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux352~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux352~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux292~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux292~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux384~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux384~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux298~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux298~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux100~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux100~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux36~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux36~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux164~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux164~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux228~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux228~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux302~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux302~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux356~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux356~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux326~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux326~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux388~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux388~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux104~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux104~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux40~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux40~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux168~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux168~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux232~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux232~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux351~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux351~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux291~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux291~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux383~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux383~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux297~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux297~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux99~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux99~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux35~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux35~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux163~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux163~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux227~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux227~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux301~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux301~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux355~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux355~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux325~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux325~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux387~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux387~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux103~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux103~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux39~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux39~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux167~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux167~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux231~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux231~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 1); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Decoder0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 1); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~21_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~98_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FULL_V~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FULL_V~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~97_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~96_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~95_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~94_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~147_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~144_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~142_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~137_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_EMPTY_V~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_EMPTY_V~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~91_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~90_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~89_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~88_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~135_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~130_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~129_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~128_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~122_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~121_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~120_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~119_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~113_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~112_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][24]~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[24]~86_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][27]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][26]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][25]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~99_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~98_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~97_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~96_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~95_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~94_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~91_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~88_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_TICK_HALT~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal3~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_STATE.start~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal3~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_process_3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_process_3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_ticks\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][31]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][30]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][29]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][28]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[26]~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1349~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector363~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector363~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~104_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~102_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~94_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~90_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~88_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~87_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~85_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~83_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~82_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~157_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~156_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~155_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~154_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~152_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~149_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal131~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~80_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~79_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux133~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux135~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~77_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~76_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal67~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~71_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal46~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal99~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux121~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux123~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~146_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~145_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~144_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~143_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~141_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~140_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~139_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~138_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~136_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~135_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~134_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~133_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~131_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~130_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~129_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~128_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~126_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~125_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~124_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~123_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~121_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~120_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~119_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~118_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~116_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~115_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~114_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~113_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~111_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~110_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~109_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~108_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~106_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~105_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~104_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~103_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~101_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~100_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~99_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~98_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~96_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~95_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~94_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~93_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~91_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~90_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~89_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~88_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~86_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~85_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~84_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~83_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~81_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~77_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~75_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~74_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~73_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~70_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux92~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux92~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux93~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux93~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector120~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector120~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector52~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector52~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector48~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector48~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector45~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector47~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector47~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector46~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SEPERATOR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_POST_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_POST_CRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector42~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector13~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector42~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_SP~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DECODED_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_CR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_SPLITSPACE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector111~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_NIBBLECNT~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector14~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector14~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[45]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[45]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal6~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal6~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~19_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[0]~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[1]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[1]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[1]~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[1]~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[1]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[0]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector573~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~80_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~79_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~21_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal3~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal3~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~21_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector355~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~77_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~92_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~76_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~75_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\ : std_logic_vector(17 DOWNTO 4); +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~74_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~73_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~25_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~25_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~83_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~71_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~70_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_OVERRUN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~24_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~24_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector352~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux95~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux95~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~23_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~23_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector353~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_process_1~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add9~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\ : std_logic_vector(4 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_process_1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_process_1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_process_1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_process_1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_process_1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_Add7~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add7~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal13~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal35~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal35~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal35~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal35~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal35~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal35~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal35~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal35~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal36~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal36~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_INTR~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_INTR~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_INTR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_INTR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~17_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~22_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal2~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal2~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal2~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal2~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_INTR~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_INTR~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_INTR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_INTR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~17_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~22_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal2~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal2~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal2~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal2~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector354~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_address_reg_b\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector15~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector14~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal34~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal34~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal34~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal34~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal34~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_OVERRUN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_RESET~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal33~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal33~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal33~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal33~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal32~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal32~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal32~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal32~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal32~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal31~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal31~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal31~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal31~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal31~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal31~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal30~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal30~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_MemoryFetch~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_0~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_EndAddr\ : std_logic_vector(16 DOWNTO 11); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_0~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr128~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal141~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr162~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr162~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1659~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~160_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugOutputOnce~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux254~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux254~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add59~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add61~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_INT_DONE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\ : std_logic_vector(30 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_LatchAddrPause~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_LatchAddr~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector119~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector119~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux353~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux353~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux293~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux293~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux385~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux385~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux299~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux299~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux101~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux101~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux37~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux37~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux165~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux165~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux229~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux229~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux349~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux349~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux289~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux289~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux381~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux381~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux295~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux295~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux97~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux97~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux33~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux33~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux161~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux161~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux225~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux225~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector49~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector49~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux378~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux378~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux286~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux286~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux94~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux94~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux30~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux30~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux346~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux346~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector51~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector51~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux348~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux348~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux288~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux288~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux380~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux380~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux294~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux294~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux96~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux96~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux32~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux32~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux160~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux160~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux224~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux224~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector50~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector50~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux379~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux379~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux287~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux287~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux95~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux95~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux31~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux31~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux347~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux347~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux8~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux14~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector507~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector639~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector771~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector503~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector701~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector701~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector635~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector899~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector568~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector502~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1115~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1115~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1083~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1083~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector500~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector500~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1179~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1179~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector698~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector698~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1147~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1147~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector632~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector632~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1307~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1307~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector962~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector962~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1275~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1275~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector896~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector896~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector830~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector830~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector565~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector565~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[25]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~76_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~75_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~74_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~73_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\ : std_logic_vector(20 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~70_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~69_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_OVERRUN~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_OVERRUN~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~68_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[3]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[3]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[3]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[3]~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[3]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[3]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[3]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1080~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector17~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[8]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Mux75~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[8]~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Mux264~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\ : std_logic_vector(11 DOWNTO 4); +SIGNAL \myVirtualToplevel|ALT_INV_INT_ENABLE\ : std_logic_vector(11 DOWNTO 4); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]~55_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~61_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~60_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~57_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_RESET~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_RESET~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[7]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[7]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[7]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[7]~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[7]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[7]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[7]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[7]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1076~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_OVERRUN~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[5]~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[6]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[6]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[6]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[6]~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[6]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[6]~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[6]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[6]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1077~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[11]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[11]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[11]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[11]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[11]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[11]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[11]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[11]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1072~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[10]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Mux73~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[11]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[10]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[10]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[10]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[10]~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[10]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[10]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[10]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[10]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[9]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Mux74~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[9]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Mux263~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[5]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Mux267~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Mux267~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[5]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[5]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[5]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[5]~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[5]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[5]~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[5]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[5]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM0_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Mux92~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[4]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[4]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Mux268~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Mux268~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_INTR~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_INTR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[4]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[4]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[4]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[4]~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[4]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[4]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[4]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[4]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[15]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][15]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[15]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[15]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[15]~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[15]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[15]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[15]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[15]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1068~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[14]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][14]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[14]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[14]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[14]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[14]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[14]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[14]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[14]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[13]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[13]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[13]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[13]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[13]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[13]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[13]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[13]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[13]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1070~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[12]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM1_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[12]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[12]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[12]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[12]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[12]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[12]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[12]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[12]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[12]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[19]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Mux86~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][19]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_DATA_LOADED~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[19]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[19]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[19]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[19]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[19]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[19]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[19]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[19]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1064~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[18]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][18]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_BUSY~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_BUSY~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[18]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[18]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[18]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[18]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[18]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[18]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[18]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[18]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1065~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][17]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal6~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal6~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal6~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[17]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[17]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[17]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[17]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[17]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[17]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[17]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[17]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[17]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1066~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[23]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][23]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[23]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[23]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[23]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[23]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[23]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[23]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[23]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1060~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[20]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][20]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_OVERRUN~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[20]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[20]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[20]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[20]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[20]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[20]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[20]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[20]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1063~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[22]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][22]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE_FIFO~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[22]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[22]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[22]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[22]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[22]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[22]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1061~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[21]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][21]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[21]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[21]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[21]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[21]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[21]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[21]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[21]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[21]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1062~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[16]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM2_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_LessThan3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal5~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal5~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal5~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal5~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal153~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugAllInfo~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_End~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_StartAddr\ : std_logic_vector(16 DOWNTO 16); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[16]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[16]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[16]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[16]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[16]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[16]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[16]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1067~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\ : std_logic_vector(7 DOWNTO 1); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\ : std_logic_vector(4 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_WR\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_SD_RD\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\ : std_logic_vector(6 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_RESET\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_RESET~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RESET_n~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_CLOCK~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_DATA_LOADED~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQM\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR\ : std_logic_vector(10 DOWNTO 10); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_cs_bo~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TXD~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TXD~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux28~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~147_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~143_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~139_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~135_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~119_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~115_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~103_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~65_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~116_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~108_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~104_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~116_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~112_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~108_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~104_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~165_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[44]~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~161_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1464~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1463~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1416~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1417~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1421~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1425~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1432~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1427~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA4~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA3~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~735_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~731_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~727_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~723_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~719_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~715_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~711_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][20]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][19]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][18]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][14]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][17]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][22]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][24]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][25]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][26]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][16]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][15]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][27]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][23]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][21]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][29]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][28]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][31]~q\ : std_logic; +SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][30]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~707_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM195\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM197\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM199\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM201\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM203\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM205\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM207\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM209\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM211\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM213\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM215\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM217\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM219\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM221\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~125_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~121_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~117_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~113_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~109_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~105_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~101_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux3~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux5~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux21~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux20~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux23~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux22~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux29~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux28~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux26~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux27~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux25~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux24~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux4~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~136_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~125_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~125_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~121_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~121_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~132_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~36_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~117_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~128_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~117_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~113_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~113_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~124_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\ : std_logic_vector(27 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~120_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~109_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~109_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~105_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~105_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~116_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~101_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~101_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~112_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add11~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~108_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~97_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~97_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~362_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~354_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~350_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~346_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~342_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\ : std_logic_vector(60 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\ : std_logic_vector(61 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM167\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM169\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM171\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM173\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM175\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM177\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM179\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM181\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM183\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM185\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM187\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM189\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM191\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM193\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux179~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux21~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux20~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux23~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux22~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux29~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux28~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux26~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux27~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux25~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux24~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\ : std_logic_vector(16 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~103_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~98_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~31_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add11~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~94_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add11~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add11~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add11~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~80_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add11~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~75_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add11~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~71_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add11~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~66_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add11~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add11~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_Add11~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\ : std_logic_vector(27 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add5~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add5~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add5~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add5~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add5~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add5~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add5~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add5~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add5~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add5~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add5~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add5~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~52_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector245~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS_2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_NOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector114~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector121~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector121~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTCRLF~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_PRECR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_WideOr18~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector216~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux93~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr34~combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector63~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_DATA_WRITE[7]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_DATA_VALID~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector17~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector15~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector15~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector15~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector15~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector15~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_1~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector15~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector15~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_ACMD41_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_CMD0_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~85_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr40~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[46]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_BLK~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector16~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~17_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~18_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\ : std_logic_vector(10 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\ : std_logic_vector(23 DOWNTO 1); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector18~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal6~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector203~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector204~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector198~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~26_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector199~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector193~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_LessThan0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector195~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr116~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|ALT_INV_l1_w0_n0_mux_dataout~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_INTR0_CS~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr195~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr2~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\ : std_logic_vector(10 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_READ_ENABLE_LAST~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_CS~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_CS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_UART1_CS~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_TIMER0_CS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_SELECT~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SOCCFG_CS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER[2]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[11]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDoneLast~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][11]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][11]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn[21]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~0_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_LessThan0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_BRAM_WREN~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuLastEN~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~81_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~80_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~78_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~77_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~76_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD0~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~75_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD41~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~72_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD55~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~70_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WAIT_FOR_HOST_RW~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.GET_CMD8_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~67_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~66_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_WAIT~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_STD_MATCH~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~62_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~59_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~58_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[4]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal4~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.RD_BLK~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o[3]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~54_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~52_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.START_INIT~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~51_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnData_v~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector15~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Selector20~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_DATA_VALID~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\ : std_logic_vector(6 DOWNTO 0); +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector21~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal8~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\ : std_logic_vector(6 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_IDLE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_SD_CHANNEL~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~44_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector87~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector66~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector67~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector69~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~43_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~42_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_doDeselect_v~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_process_0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal5~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal5~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal5~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal5~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_UART0_CS~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal3~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal3~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\ : std_logic; +SIGNAL \ALT_INV_reset~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RESET_n~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal12~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RESET_COUNTER\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_Equal12~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal12~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal11~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal11~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal11~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Equal11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_Equal11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\ : std_logic_vector(11 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal2~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuIsWriting~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux11~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux7~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux14~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux15~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux16~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux17~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux18~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~36_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~35_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector501~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~32_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~30_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~28_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector640~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector640~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector706~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector706~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector970~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector970~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector904~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector904~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector838~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector838~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[26]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector772~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector772~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[18]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr171~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tIdx~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_intTriggered~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inInterrupt~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~47_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~43_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~39_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~35_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~30_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~26_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~22_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~18_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~14_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~10_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~6_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\ : std_logic_vector(17 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\ : std_logic_vector(23 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux179~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_INTR~q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_INTR~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~93_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~89_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.valid~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\ : std_logic_vector(31 DOWNTO 0); +SIGNAL \myVirtualToplevel|ALT_INV_Add0~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add0~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add0~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add0~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add0~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add0~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\ : std_logic_vector(23 DOWNTO 2); +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~85_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~81_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~77_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~73_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~69_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~65_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~61_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~57_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~53_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~49_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add2~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add1~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add1~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add1~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add1~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_Add1~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~45_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~41_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~37_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~33_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~17_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~29_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~25_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~21_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~13_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~9_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~5_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~1_sumout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\ : std_logic_vector(15 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][10]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][9]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][7]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][6]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][11]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][8]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][5]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][4]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][3]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][2]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][1]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][0]~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\ : std_logic; +SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\ : std_logic_vector(9 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux14~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux17~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux17~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux12~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux12~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux9~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux9~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux15~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux15~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux18~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux18~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux13~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux13~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux10~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux10~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux16~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux16~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux19~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux19~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux1~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux1~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT[2]~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~20_q\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector357~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~64_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~63_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~87_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~106_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~86_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~85_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~49_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~48_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~84_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~83_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector358~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~101_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~47_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~46_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~41_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~25_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~24_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~23_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~22_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~21_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~20_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~19_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~40_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~39_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~18_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~17_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~16_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~15_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr160~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~38_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~20_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~20_q\ : std_logic; +SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~29_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector356~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~1_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~0_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~14_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~13_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~82_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~12_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~11_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~10_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~9_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~8_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~7_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~6_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~5_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~4_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~3_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~2_combout\ : std_logic; +SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~81_combout\ : std_logic; + +BEGIN + +ww_CLOCK_50 <= CLOCK_50; +LEDR <= ww_LEDR; +ww_KEY <= KEY; +ww_SDCARD_MISO <= SDCARD_MISO; +SDCARD_MOSI <= ww_SDCARD_MOSI; +SDCARD_CLK <= ww_SDCARD_CLK; +SDCARD_CS <= ww_SDCARD_CS; +ww_UART_RX_0 <= UART_RX_0; +UART_TX_0 <= ww_UART_TX_0; +ww_UART_RX_1 <= UART_RX_1; +UART_TX_1 <= ww_UART_TX_1; +SDRAM_CLK <= ww_SDRAM_CLK; +SDRAM_CKE <= ww_SDRAM_CKE; +SDRAM_ADDR <= ww_SDRAM_ADDR; +SDRAM_DQM <= ww_SDRAM_DQM; +SDRAM_BA <= ww_SDRAM_BA; +SDRAM_CS <= ww_SDRAM_CS; +SDRAM_WE <= ww_SDRAM_WE; +SDRAM_RAS <= ww_SDRAM_RAS; +SDRAM_CAS <= ww_SDRAM_CAS; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(0)); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0)); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0)); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[0]~0_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[0]~0_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[5]~1_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[5]~1_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[4]~3_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[4]~3_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[2]~6_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[2]~6_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[3]~7_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[3]~7_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[4]~0_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[4]~0_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[5]~1_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[5]~1_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[6]~2_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[6]~2_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[7]~3_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[7]~3_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[1]~4_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[1]~4_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[2]~5_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[2]~5_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[3]~6_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[3]~6_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[0]~7_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[0]~7_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd +& gnd & gnd & gnd & gnd & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)); + +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7) & \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(5) & +\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) & \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(2) & \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0)); + +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|UART0|Add8~5_sumout\ & \myVirtualToplevel|UART0|Add8~1_sumout\ & \myVirtualToplevel|UART0|Add8~29_sumout\ & \myVirtualToplevel|UART0|Add8~25_sumout\ +& \myVirtualToplevel|UART0|Add8~21_sumout\ & \myVirtualToplevel|UART0|Add8~17_sumout\ & \myVirtualToplevel|UART0|Add8~13_sumout\ & \myVirtualToplevel|UART0|Add8~9_sumout\); + +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1); +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2); +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3); +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4); +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5); +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6); +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(2)); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0)); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0)); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\(1); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[7]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[6]~1_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[5]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[4]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[3]~5_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[2]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[1]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[0]~4_combout\); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\ +& \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[7]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[6]~0_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[5]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[4]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[3]~3_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[2]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[1]~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[0]~2_combout\); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\ +& \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[7]~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[6]~6_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[5]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[4]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[3]~2_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[2]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[1]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[0]~1_combout\); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\ +& \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6) & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0)); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\ +& \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\ & +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\); + +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[4]~0_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[4]~0_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[5]~1_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[5]~1_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[6]~2_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[6]~2_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[7]~3_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[7]~3_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[1]~4_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[1]~4_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[2]~5_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[2]~5_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[3]~6_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[3]~6_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7_combout\; + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(8) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\(0); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(4)); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0)); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0)); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\(1); + +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_ACLR_bus\ <= (gnd & gnd); + +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_CLK_bus\ <= (gnd & gnd & \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\); + +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_ENA_bus\ <= (vcc & vcc & \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~1_combout\); + +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_AX_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\); + +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_AY_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\); + +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(1) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(2) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(3) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(4) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(5) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(6) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(7) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(8) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(9) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(10) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(11) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(12) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(13) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(14) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(15) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(16) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(17) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM193\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM191\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM189\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM187\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM185\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM183\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM181\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM179\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM177\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM175\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM173\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM171\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM169\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM167\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~40\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~41\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~42\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~43\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~44\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~45\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~46\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~47\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~48\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~49\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~50\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~51\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~52\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~53\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~54\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~55\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~56\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~57\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~58\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~59\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~60\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~61\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~62\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~63\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~64\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~65\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~66\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~67\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~68\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~69\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~70\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~71\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(63); + +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_ACLR_bus\ <= (gnd & gnd); + +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_CLK_bus\ <= (gnd & gnd & \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\); + +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_ENA_bus\ <= (vcc & vcc & \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~1_combout\); + +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_AX_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\); + +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_AY_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\); + +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_BX_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\); + +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_BY_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\); + +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM221\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM219\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM217\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM215\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM213\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM211\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM209\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM207\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM205\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM203\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM201\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM199\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM197\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM195\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~387\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~388\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~389\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~390\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~391\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~392\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~393\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~394\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~395\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~396\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~397\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~398\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~399\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~400\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~401\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~402\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~403\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~404\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~405\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~406\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~407\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~408\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~409\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~410\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~411\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~412\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~413\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~414\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~415\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~416\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~417\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~418\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~419\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~420\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~421\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~422\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~423\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~424\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~425\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~426\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~427\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~428\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~429\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~430\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~431\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~432\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~433\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~434\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~435\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~436\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(63); + +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd +& gnd & gnd & gnd & gnd & \myVirtualToplevel|UART1|RX_BUFFER\(8) & \myVirtualToplevel|UART1|RX_BUFFER\(7) & \myVirtualToplevel|UART1|RX_BUFFER\(6) & \myVirtualToplevel|UART1|RX_BUFFER[5]~DUPLICATE_q\ & +\myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\ & \myVirtualToplevel|UART1|RX_BUFFER\(3) & \myVirtualToplevel|UART1|RX_BUFFER\(2) & \myVirtualToplevel|UART1|RX_BUFFER\(1)); + +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) & +\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0)); + +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|UART1|Add3~29_sumout\ & \myVirtualToplevel|UART1|Add3~21_sumout\ & \myVirtualToplevel|UART1|Add3~25_sumout\ & \myVirtualToplevel|UART1|Add3~1_sumout\ +& \myVirtualToplevel|UART1|Add3~13_sumout\ & \myVirtualToplevel|UART1|Add3~17_sumout\ & \myVirtualToplevel|UART1|Add3~9_sumout\ & \myVirtualToplevel|UART1|Add3~5_sumout\); + +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1); +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2); +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3); +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4); +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5); +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6); +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7); + +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd +& gnd & gnd & gnd & gnd & \myVirtualToplevel|UART0|RX_BUFFER\(8) & \myVirtualToplevel|UART0|RX_BUFFER\(7) & \myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_BUFFER\(5) & +\myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_BUFFER\(1)); + +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) & +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) & \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3]~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) & \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) & +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\); + +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|UART0|Add3~21_sumout\ & \myVirtualToplevel|UART0|Add3~17_sumout\ & \myVirtualToplevel|UART0|Add3~29_sumout\ & \myVirtualToplevel|UART0|Add3~1_sumout\ +& \myVirtualToplevel|UART0|Add3~13_sumout\ & \myVirtualToplevel|UART0|Add3~25_sumout\ & \myVirtualToplevel|UART0|Add3~9_sumout\ & \myVirtualToplevel|UART0|Add3~5_sumout\); + +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1); +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2); +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3); +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4); +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5); +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6); +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(6)); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0)); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(8) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) & +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0)); + +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\(1); + +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH0\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(0); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH1\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(1); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH2\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(2); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH3\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(3); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH4\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(4); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH5\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(5); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH6\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(6); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH7\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(7); + +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI0\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(0); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI1\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(1); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI2\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(2); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI3\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(3); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI4\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(4); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI5\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(5); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI6\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(6); +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI7\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(7); + +\mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_CLKIN_bus\ <= (gnd & gnd & gnd & \CLOCK_50~input_o\); + +\mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_MHI_bus\ <= (\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI7\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI6\ & +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI5\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI4\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI3\ & +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI2\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI1\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI0\); + +\mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFTEN0\ <= \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_SHIFTEN_bus\(0); +\mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIGSHIFTEN2\ <= \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_SHIFTEN_bus\(2); + +\mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER_VCO0PH_bus\ <= (\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH7\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH6\ & +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH5\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH4\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH3\ & +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH2\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH1\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH0\); + +\mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER_VCO0PH_bus\ <= (\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH7\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH6\ & +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH5\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH4\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH3\ & +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH2\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH1\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH0\); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1209~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM711~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM471~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM375~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM321~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM299~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[26]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[24]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[33]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_STATE.start~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause[1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause[7]~DUPLICATE_q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[43]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[43]~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[31]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[28]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[28]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[20]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[12]_NEW2314_RESYN12946_BDD12947\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12946_BDD12947\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[8]_NEW2310_RESYN12938_BDD12939\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12938_BDD12939\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]_NEW2308_RESYN12934_BDD12935\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12934_BDD12935\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]_NEW2304_RESYN12926_BDD12927\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12926_BDD12927\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]_NEW2302_RESYN12922_BDD12923\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12922_BDD12923\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]_NEW2296_RESYN12910_BDD12911\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12910_BDD12911\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[9]_NEW2294_RESYN12906_BDD12907\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12906_BDD12907\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]_NEW2288_RESYN12894_BDD12895\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12894_BDD12895\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[11]_NEW2286_RESYN12890_BDD12891\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12890_BDD12891\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]_NEW1860_RESYN12810_BDD12811\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860_RESYN12810_BDD12811\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]_NEW1852_RESYN12808_BDD12809\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852_RESYN12808_BDD12809\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~5_RESYN12804_BDD12805\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_RESYN12804_BDD12805\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~23_RESYN12802_BDD12803\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_RESYN12802_BDD12803\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN12800_BDD12801\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12800_BDD12801\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12796_BDD12797\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12796_BDD12797\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12794_BDD12795\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794_BDD12795\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12792_BDD12793\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12792_BDD12793\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_RESYN12790_BDD12791\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12790_BDD12791\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_RESYN12788_BDD12789\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788_BDD12789\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN12798_BDD12799\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12798_BDD12799\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_RESYN12786_BDD12787\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_RESYN12786_BDD12787\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_RESYN12782_BDD12783\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12782_BDD12783\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_RESYN12780_BDD12781\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12780_BDD12781\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_RESYN12778_BDD12779\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_RESYN12778_BDD12779\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12776_BDD12777\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12776_BDD12777\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12774_BDD12775\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12774_BDD12775\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~10_RESYN12772_BDD12773\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_RESYN12772_BDD12773\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_RESYN12770_BDD12771\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_RESYN12770_BDD12771\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_RESYN12768_BDD12769\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768_BDD12769\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12766_BDD12767\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12766_BDD12767\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12764_BDD12765\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12764_BDD12765\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12762_BDD12763\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12762_BDD12763\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~5_RESYN12760_BDD12761\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~5_RESYN12760_BDD12761\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~104_RESYN12758_BDD12759\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_RESYN12758_BDD12759\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~5_RESYN12756_BDD12757\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_RESYN12756_BDD12757\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~4_RESYN12754_BDD12755\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_RESYN12754_BDD12755\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~2_RESYN12752_BDD12753\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_RESYN12752_BDD12753\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_RESYN12750_BDD12751\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12750_BDD12751\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~3_RESYN12748_BDD12749\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_RESYN12748_BDD12749\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~3_RESYN12746_BDD12747\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_RESYN12746_BDD12747\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~7_RESYN12744_BDD12745\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_RESYN12744_BDD12745\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~1_RESYN12742_BDD12743\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_RESYN12742_BDD12743\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~0_RESYN12740_BDD12741\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_RESYN12740_BDD12741\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_RESYN12738_BDD12739\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_RESYN12738_BDD12739\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~0_RESYN12736_BDD12737\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_RESYN12736_BDD12737\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~4_RESYN12734_BDD12735\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_RESYN12734_BDD12735\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~2_RESYN12732_BDD12733\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_RESYN12732_BDD12733\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~1_RESYN12730_BDD12731\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_RESYN12730_BDD12731\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~0_RESYN12728_BDD12729\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_RESYN12728_BDD12729\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~0_RESYN12726_BDD12727\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_RESYN12726_BDD12727\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136_RESYN12724_BDD12725\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136_RESYN12724_BDD12725\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12722_BDD12723\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12722_BDD12723\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12720_BDD12721\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12720_BDD12721\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12718_BDD12719\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12718_BDD12719\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~0_RESYN12716_BDD12717\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_RESYN12716_BDD12717\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~0_RESYN12714_BDD12715\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_RESYN12714_BDD12715\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~0_RESYN12712_BDD12713\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_RESYN12712_BDD12713\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~1_RESYN12710_BDD12711\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_RESYN12710_BDD12711\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~0_RESYN12708_BDD12709\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_RESYN12708_BDD12709\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_RESYN12706_BDD12707\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_RESYN12706_BDD12707\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_RESYN12704_BDD12705\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704_BDD12705\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~3_RESYN12702_BDD12703\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_RESYN12702_BDD12703\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~2_RESYN12700_BDD12701\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_RESYN12700_BDD12701\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_RESYN12698_BDD12699\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_RESYN12698_BDD12699\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_RESYN12696_BDD12697\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_RESYN12696_BDD12697\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~1_RESYN12694_BDD12695\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_RESYN12694_BDD12695\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~0_RESYN12692_BDD12693\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_RESYN12692_BDD12693\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_RESYN12690_BDD12691\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690_BDD12691\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~16_RESYN12688_BDD12689\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688_BDD12689\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~60_RESYN12686_BDD12687\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_RESYN12686_BDD12687\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~43_RESYN12684_BDD12685\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_RESYN12684_BDD12685\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~35_RESYN12682_BDD12683\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_RESYN12682_BDD12683\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~25_RESYN12680_BDD12681\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_RESYN12680_BDD12681\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_RESYN12678_BDD12679\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_RESYN12678_BDD12679\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_RESYN12676_BDD12677\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_RESYN12676_BDD12677\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_RESYN12674_BDD12675\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_RESYN12674_BDD12675\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_RESYN12672_BDD12673\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_RESYN12670_BDD12671\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_RESYN12670_BDD12671\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664_BDD12665\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664_BDD12665\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_RESYN12652_BDD12653\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_RESYN12652_BDD12653\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_RESYN12644_BDD12645\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_RESYN12644_BDD12645\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~8_RESYN12642_BDD12643\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_RESYN12642_BDD12643\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_RESYN12640_BDD12641\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640_BDD12641\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_RESYN12638_BDD12639\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12638_BDD12639\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_RESYN12636_BDD12637\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12636_BDD12637\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~6_RESYN12634_BDD12635\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_RESYN12634_BDD12635\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~4_RESYN12630_BDD12631\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_RESYN12632_BDD12633\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN12632_BDD12633\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~7_RESYN12628_BDD12629\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_RESYN12628_BDD12629\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_RESYN12626_BDD12627\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_RESYN12626_BDD12627\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~1_RESYN12624_BDD12625\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_RESYN12624_BDD12625\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_RESYN12622_BDD12623\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~13_RESYN12620_BDD12621\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_RESYN12620_BDD12621\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_RESYN12618_BDD12619\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618_BDD12619\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_RESYN12614_BDD12615\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12614_BDD12615\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_RESYN12612_BDD12613\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12612_BDD12613\; +\myVirtualToplevel|ALT_INV_MEM_BUSY~1_RESYN12610_BDD12611\ <= NOT \myVirtualToplevel|MEM_BUSY~1_RESYN12610_BDD12611\; +\myVirtualToplevel|ALT_INV_MEM_BUSY~1_RESYN12608_BDD12609\ <= NOT \myVirtualToplevel|MEM_BUSY~1_RESYN12608_BDD12609\; +\myVirtualToplevel|ALT_INV_Equal4~0_RESYN12606_BDD12607\ <= NOT \myVirtualToplevel|Equal4~0_RESYN12606_BDD12607\; +\myVirtualToplevel|ALT_INV_LessThan0~0_RESYN12604_BDD12605\ <= NOT \myVirtualToplevel|LessThan0~0_RESYN12604_BDD12605\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN12594_BDD12595\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12594_BDD12595\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN12592_BDD12593\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12592_BDD12593\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_RESYN12590_BDD12591\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12590_BDD12591\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_RESYN12588_BDD12589\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12588_BDD12589\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12586_BDD12587\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12586_BDD12587\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12584_BDD12585\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12584_BDD12585\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12582_BDD12583\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12582_BDD12583\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~6_RESYN12564_BDD12565\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_RESYN12564_BDD12565\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~11_RESYN12558_BDD12559\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_RESYN12558_BDD12559\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN12556_BDD12557\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12556_BDD12557\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN12554_BDD12555\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12554_BDD12555\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~15_RESYN12546_BDD12547\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_RESYN12546_BDD12547\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12544_BDD12545\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_BDD12545\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12542_BDD12543\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12542_BDD12543\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_RESYN12538_BDD12539\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12538_BDD12539\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_RESYN12536_BDD12537\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12536_BDD12537\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~13_RESYN12534_BDD12535\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_RESYN12534_BDD12535\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_RESYN12532_BDD12533\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12532_BDD12533\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_RESYN12530_BDD12531\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12530_BDD12531\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~3_RESYN12528_BDD12529\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_RESYN12528_BDD12529\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_RESYN12526_BDD12527\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12526_BDD12527\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_RESYN12524_BDD12525\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12524_BDD12525\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~3_RESYN12522_BDD12523\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_RESYN12522_BDD12523\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~1_RESYN12520_BDD12521\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_RESYN12520_BDD12521\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~5_RESYN12518_BDD12519\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_RESYN12518_BDD12519\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~4_RESYN12516_BDD12517\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_RESYN12516_BDD12517\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~2_RESYN12514_BDD12515\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_RESYN12514_BDD12515\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~1_RESYN12512_BDD12513\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_RESYN12512_BDD12513\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_RESYN12510_BDD12511\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12510_BDD12511\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~4_RESYN12508_BDD12509\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_RESYN12508_BDD12509\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~1_RESYN12504_BDD12505\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_RESYN12504_BDD12505\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_RESYN12502_BDD12503\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12502_BDD12503\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_RESYN12500_BDD12501\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12500_BDD12501\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~90_RESYN12496_BDD12497\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_RESYN12496_BDD12497\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~3_RESYN12492_BDD12493\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_RESYN12492_BDD12493\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~87_RESYN12490_BDD12491\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_RESYN12490_BDD12491\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~0_RESYN12488_BDD12489\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_RESYN12488_BDD12489\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~1_RESYN12486_BDD12487\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_RESYN12486_BDD12487\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~5_RESYN12484_BDD12485\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_RESYN12484_BDD12485\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~19_RESYN12470_BDD12471\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_RESYN12470_BDD12471\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_RESYN12464_BDD12465\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12464_BDD12465\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_RESYN12462_BDD12463\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12462_BDD12463\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~1_RESYN12460_BDD12461\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_RESYN12460_BDD12461\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_RESYN12454_BDD12455\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12454_BDD12455\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_RESYN12452_BDD12453\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12452_BDD12453\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~2_RESYN12434_BDD12435\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434_BDD12435\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~2_RESYN12432_BDD12433\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~2_RESYN12430_BDD12431\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~2_RESYN12428_BDD12429\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~2_RESYN12426_BDD12427\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~2_RESYN12424_BDD12425\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~2_RESYN12422_BDD12423\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~5_RESYN12420_BDD12421\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416_BDD12417\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416_BDD12417\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414_BDD12415\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414_BDD12415\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_RESYN12412_BDD12413\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12412_BDD12413\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_RESYN12410_BDD12411\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12410_BDD12411\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_RESYN12408_BDD12409\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12408_BDD12409\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_RESYN12406_BDD12407\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12406_BDD12407\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_RESYN12404_BDD12405\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12404_BDD12405\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_RESYN12402_BDD12403\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12402_BDD12403\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_RESYN12400_BDD12401\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12400_BDD12401\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_RESYN12398_BDD12399\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12398_BDD12399\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_RESYN12396_BDD12397\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12396_BDD12397\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_RESYN12394_BDD12395\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12394_BDD12395\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_RESYN12388_BDD12389\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12388_BDD12389\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_RESYN12386_BDD12387\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12386_BDD12387\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_RESYN12370_BDD12371\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_RESYN12370_BDD12371\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365_BDD9366\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365_BDD9366\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9077_RESYN9359_BDD9360\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9077_RESYN9359_BDD9360\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9357_BDD9358\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9357_BDD9358\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9355_BDD9356\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_BDD9356\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9349_BDD9350\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9349_BDD9350\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9347_BDD9348\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9347_BDD9348\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9345_BDD9346\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9345_BDD9346\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN9337_BDD9338\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN9337_BDD9338\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9335_BDD9336\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9335_BDD9336\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9333_BDD9334\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_BDD9334\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8847_RESYN9325_BDD9326\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_RESYN9325_BDD9326\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8845_RESYN9323_BDD9324\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_RESYN9323_BDD9324\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_RESYN9015_RESYN9351_BDD9352\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351_BDD9352\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9315_BDD9316\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_BDD9316\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9313_BDD9314\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313_BDD9314\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9311_BDD9312\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311_BDD9312\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~164_RESYN9307_BDD9308\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_RESYN9307_BDD9308\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN9301_BDD9302\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN9301_BDD9302\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_RESYN9299_BDD9300\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_RESYN9299_BDD9300\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_RESYN9297_BDD9298\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9297_BDD9298\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_RESYN9295_BDD9296\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9295_BDD9296\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_RESYN9285_BDD9286\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9285_BDD9286\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_RESYN9283_BDD9284\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9283_BDD9284\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9277_BDD9278\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9277_BDD9278\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_BDD9276\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_BDD9276\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9269_BDD9270\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9269_BDD9270\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9267_BDD9268\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9267_BDD9268\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9263_BDD9264\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9263_BDD9264\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~4_RESYN9251_BDD9252\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_RESYN9251_BDD9252\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~1_RESYN9249_BDD9250\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_RESYN9249_BDD9250\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_RESYN9247_BDD9248\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9247_BDD9248\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_RESYN9245_BDD9246\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9245_BDD9246\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9239_BDD9240\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9239_BDD9240\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9237_BDD9238\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9237_BDD9238\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9235_BDD9236\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9235_BDD9236\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9233_BDD9234\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9233_BDD9234\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9231_BDD9232\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9231_BDD9232\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9229_BDD9230\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9229_BDD9230\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9225_BDD9226\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9225_BDD9226\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_RESYN9223_BDD9224\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9223_BDD9224\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_RESYN9221_BDD9222\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9221_BDD9222\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_RESYN9217_BDD9218\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_RESYN9217_BDD9218\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_RESYN9215_BDD9216\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9215_BDD9216\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_RESYN9213_BDD9214\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9213_BDD9214\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~24_RESYN9207_BDD9208\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_RESYN9207_BDD9208\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195_BDD9196\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195_BDD9196\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193_BDD9194\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193_BDD9194\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189_BDD9190\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189_BDD9190\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9179_BDD9180\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9179_BDD9180\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9177_BDD9178\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9177_BDD9178\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9175_BDD9176\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9175_BDD9176\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9173_BDD9174\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9173_BDD9174\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_RESYN9171_BDD9172\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9171_BDD9172\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_RESYN9169_BDD9170\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9169_BDD9170\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_RESYN9167_BDD9168\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9167_BDD9168\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_RESYN9165_BDD9166\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9165_BDD9166\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~12_RESYN9163_BDD9164\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_RESYN9163_BDD9164\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_BDD9162\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_BDD9162\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9159_BDD9160\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159_BDD9160\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9157_BDD9158\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157_BDD9158\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~0_RESYN9155_BDD9156\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155_BDD9156\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_RESYN9151_BDD9152\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9151_BDD9152\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_RESYN9149_BDD9150\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9149_BDD9150\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_RESYN9147_BDD9148\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147_BDD9148\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_RESYN9145_BDD9146\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145_BDD9146\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9143_BDD9144\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9143_BDD9144\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9141_BDD9142\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9141_BDD9142\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9139_BDD9140\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9139_BDD9140\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_RESYN9127_BDD9128\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127_BDD9128\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_RESYN9125_BDD9126\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125_BDD9126\; +\myVirtualToplevel|ALT_INV_SD_CS_RESYN9121_BDD9122\ <= NOT \myVirtualToplevel|SD_CS_RESYN9121_BDD9122\; +\myVirtualToplevel|ALT_INV_SD_CS_RESYN9119_BDD9120\ <= NOT \myVirtualToplevel|SD_CS_RESYN9119_BDD9120\; +\myVirtualToplevel|ALT_INV_IO_SELECT_RESYN9117_BDD9118\ <= NOT \myVirtualToplevel|IO_SELECT_RESYN9117_BDD9118\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8707_RESYN9111_BDD9112\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_RESYN9111_BDD9112\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_RESYN9109_BDD9110\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9109_BDD9110\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_RESYN9107_BDD9108\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9107_BDD9108\; +\myVirtualToplevel|ALT_INV_IO_SELECT_RESYN9115_BDD9116\ <= NOT \myVirtualToplevel|IO_SELECT_RESYN9115_BDD9116\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8467_RESYN9093_BDD9094\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_RESYN9093_BDD9094\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8459_RESYN9091_BDD9092\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_RESYN9091_BDD9092\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8447_RESYN9089_BDD9090\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_RESYN9089_BDD9090\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_BDD9076\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_BDD9076\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9071_BDD9072\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9071_BDD9072\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9069_BDD9070\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9069_BDD9070\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9067_BDD9068\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9067_BDD9068\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9065_BDD9066\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9065_BDD9066\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9063_BDD9064\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9063_BDD9064\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9061_BDD9062\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9061_BDD9062\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9059_BDD9060\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9059_BDD9060\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9057_BDD9058\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9057_BDD9058\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9055_BDD9056\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9055_BDD9056\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_RESYN9053_BDD9054\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9053_BDD9054\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_RESYN9051_BDD9052\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9051_BDD9052\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9049_BDD9050\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9049_BDD9050\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9047_BDD9048\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9047_BDD9048\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9045_BDD9046\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9045_BDD9046\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_RESYN9043_BDD9044\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9043_BDD9044\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_RESYN9041_BDD9042\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9041_BDD9042\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9039_BDD9040\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9039_BDD9040\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9037_BDD9038\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9037_BDD9038\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9035_BDD9036\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9035_BDD9036\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_RESYN9033_BDD9034\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9033_BDD9034\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_RESYN9031_BDD9032\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9031_BDD9032\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9029_BDD9030\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9029_BDD9030\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9027_BDD9028\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9027_BDD9028\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9025_BDD9026\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9025_BDD9026\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~3_RESYN9023_BDD9024\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9023_BDD9024\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~3_RESYN9021_BDD9022\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9021_BDD9022\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_RESYN9019_BDD9020\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9019_BDD9020\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_RESYN9017_BDD9018\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9017_BDD9018\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_RESYN9015_BDD9016\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_BDD9016\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~14_RESYN9011_BDD9012\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_RESYN9011_BDD9012\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_RESYN9009_BDD9010\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009_BDD9010\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN9003_BDD9004\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN9003_BDD9004\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8999_BDD9000\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8999_BDD9000\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8997_BDD8998\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8997_BDD8998\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8995_BDD8996\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~9_RESYN8993_BDD8994\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_RESYN8993_BDD8994\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_RESYN8987_BDD8988\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8987_BDD8988\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_RESYN8985_BDD8986\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8985_BDD8986\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_BDD8984\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_BDD8984\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8979_BDD8980\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8979_BDD8980\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_RESYN8977_BDD8978\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8977_BDD8978\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_RESYN8975_BDD8976\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8975_BDD8976\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8973_BDD8974\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8973_BDD8974\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8971_BDD8972\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8971_BDD8972\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~3_RESYN8969_BDD8970\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_RESYN8969_BDD8970\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8967_BDD8968\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8967_BDD8968\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_BDD8966\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_BDD8966\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_BDD8964\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_BDD8964\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~4_RESYN8961_BDD8962\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_RESYN8961_BDD8962\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_RESYN8959_BDD8960\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_BDD8960\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_RESYN8957_BDD8958\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_RESYN8957_BDD8958\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_RESYN8955_BDD8956\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8955_BDD8956\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_RESYN8953_BDD8954\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8953_BDD8954\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_RESYN8941_BDD8942\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_BDD8942\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8939_BDD8940\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8939_BDD8940\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8937_BDD8938\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_BDD8938\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~0_RESYN8935_BDD8936\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_RESYN8935_BDD8936\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~63_RESYN8929_BDD8930\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_RESYN8929_BDD8930\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~24_RESYN8923_BDD8924\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_RESYN8921_BDD8922\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_RESYN8921_BDD8922\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883_BDD8884\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883_BDD8884\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879_BDD8880\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879_BDD8880\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8877_BDD8878\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8877_BDD8878\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8875_BDD8876\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8875_BDD8876\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8873_BDD8874\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8873_BDD8874\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_RESYN8869_BDD8870\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8869_BDD8870\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_RESYN8867_BDD8868\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8867_BDD8868\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_RESYN8861_BDD8862\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8861_BDD8862\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_RESYN8859_BDD8860\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8859_BDD8860\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8853_BDD8854\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8853_BDD8854\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_BDD8852\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_BDD8852\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8849_BDD8850\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8849_BDD8850\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8847_BDD8848\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_BDD8848\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8845_BDD8846\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_BDD8846\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_RESYN8843_BDD8844\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8843_BDD8844\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_RESYN8841_BDD8842\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8841_BDD8842\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~3_RESYN8837_BDD8838\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_RESYN8837_BDD8838\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~10_RESYN8833_BDD8834\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8833_BDD8834\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~10_RESYN8831_BDD8832\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8831_BDD8832\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~4_RESYN8829_BDD8830\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_RESYN8829_BDD8830\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8827_BDD8828\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8827_BDD8828\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8825_BDD8826\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8825_BDD8826\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8823_BDD8824\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8823_BDD8824\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_RESYN8819_BDD8820\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN8819_BDD8820\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~0_RESYN8809_BDD8810\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809_BDD8810\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8803_BDD8804\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803_BDD8804\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_RESYN8791_BDD8792\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791_BDD8792\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~9_RESYN8789_BDD8790\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789_BDD8790\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_RESYN8785_BDD8786\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785_BDD8786\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_RESYN8783_BDD8784\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783_BDD8784\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~6_RESYN8781_BDD8782\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781_BDD8782\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_RESYN8777_BDD8778\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777_BDD8778\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_RESYN8775_BDD8776\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775_BDD8776\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_RESYN8773_BDD8774\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773_BDD8774\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_RESYN8771_BDD8772\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771_BDD8772\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_RESYN8769_BDD8770\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_RESYN8767_BDD8768\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\; +\myVirtualToplevel|ALT_INV_INTR0_CS_RESYN8755_BDD8756\ <= NOT \myVirtualToplevel|INTR0_CS_RESYN8755_BDD8756\; +\myVirtualToplevel|ALT_INV_SOCCFG_CS_RESYN8753_BDD8754\ <= NOT \myVirtualToplevel|SOCCFG_CS_RESYN8753_BDD8754\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~5_RESYN8749_BDD8750\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8749_BDD8750\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~5_RESYN8745_BDD8746\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8745_BDD8746\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ <= NOT \myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~92_RESYN8741_BDD8742\ <= NOT \myVirtualToplevel|MEM_DATA_READ[3]~92_RESYN8741_BDD8742\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~90_RESYN8739_BDD8740\ <= NOT \myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739_BDD8740\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~88_RESYN8737_BDD8738\ <= NOT \myVirtualToplevel|MEM_DATA_READ[5]~88_RESYN8737_BDD8738\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~86_RESYN8735_BDD8736\ <= NOT \myVirtualToplevel|MEM_DATA_READ[6]~86_RESYN8735_BDD8736\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~84_RESYN8733_BDD8734\ <= NOT \myVirtualToplevel|MEM_DATA_READ[7]~84_RESYN8733_BDD8734\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~82_RESYN8731_BDD8732\ <= NOT \myVirtualToplevel|MEM_DATA_READ[8]~82_RESYN8731_BDD8732\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~80_RESYN8729_BDD8730\ <= NOT \myVirtualToplevel|MEM_DATA_READ[9]~80_RESYN8729_BDD8730\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~78_RESYN8727_BDD8728\ <= NOT \myVirtualToplevel|MEM_DATA_READ[10]~78_RESYN8727_BDD8728\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~76_RESYN8725_BDD8726\ <= NOT \myVirtualToplevel|MEM_DATA_READ[11]~76_RESYN8725_BDD8726\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~74_RESYN8723_BDD8724\ <= NOT \myVirtualToplevel|MEM_DATA_READ[12]~74_RESYN8723_BDD8724\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~72_RESYN8721_BDD8722\ <= NOT \myVirtualToplevel|MEM_DATA_READ[13]~72_RESYN8721_BDD8722\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~70_RESYN8719_BDD8720\ <= NOT \myVirtualToplevel|MEM_DATA_READ[14]~70_RESYN8719_BDD8720\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~68_RESYN8717_BDD8718\ <= NOT \myVirtualToplevel|MEM_DATA_READ[15]~68_RESYN8717_BDD8718\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~5_RESYN8715_BDD8716\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~5_RESYN8715_BDD8716\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8711_BDD8712\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8711_BDD8712\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8709_BDD8710\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8709_BDD8710\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8707_BDD8708\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_BDD8708\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8705_BDD8706\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8705_BDD8706\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8703_BDD8704\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8703_BDD8704\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8701_BDD8702\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8701_BDD8702\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8699_BDD8700\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8699_BDD8700\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8697_BDD8698\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8697_BDD8698\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8695_BDD8696\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8695_BDD8696\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8693_BDD8694\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8693_BDD8694\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8691_BDD8692\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8691_BDD8692\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8689_BDD8690\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8689_BDD8690\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8687_BDD8688\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8687_BDD8688\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_RESYN8685_BDD8686\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8685_BDD8686\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_RESYN8683_BDD8684\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8683_BDD8684\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8681_BDD8682\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8681_BDD8682\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8679_BDD8680\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8679_BDD8680\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8677_BDD8678\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8677_BDD8678\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_RESYN8675_BDD8676\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675_BDD8676\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_RESYN8673_BDD8674\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673_BDD8674\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~119_RESYN8671_BDD8672\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671_BDD8672\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_RESYN8669_BDD8670\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8669_BDD8670\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_RESYN8667_BDD8668\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8667_BDD8668\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_RESYN8665_BDD8666\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8665_BDD8666\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_RESYN8663_BDD8664\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8663_BDD8664\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8661_BDD8662\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8661_BDD8662\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8659_BDD8660\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8659_BDD8660\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8657_BDD8658\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8657_BDD8658\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~94_RESYN8655_BDD8656\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_RESYN8655_BDD8656\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8651_BDD8652\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8651_BDD8652\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8649_BDD8650\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8649_BDD8650\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8647_BDD8648\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8647_BDD8648\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[21]~1_RESYN8641_BDD8642\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8641_BDD8642\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[21]~1_RESYN8639_BDD8640\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8639_BDD8640\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_BDD8636\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_BDD8636\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_RESYN8633_BDD8634\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8633_BDD8634\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_RESYN8631_BDD8632\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8631_BDD8632\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_BDD8628\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_BDD8628\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8625_BDD8626\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8625_BDD8626\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_RESYN8623_BDD8624\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8623_BDD8624\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_RESYN8621_BDD8622\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8621_BDD8622\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_RESYN8619_BDD8620\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619_BDD8620\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~8_RESYN8629_BDD8630\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_RESYN8629_BDD8630\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~6_RESYN8617_BDD8618\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_RESYN8617_BDD8618\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~8_RESYN8615_BDD8616\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_RESYN8615_BDD8616\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~2_RESYN8613_BDD8614\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_RESYN8613_BDD8614\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~2_RESYN8605_BDD8606\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_RESYN8605_BDD8606\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~81_RESYN8603_BDD8604\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_RESYN8603_BDD8604\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~58_RESYN8601_BDD8602\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_RESYN8601_BDD8602\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~48_RESYN8599_BDD8600\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_RESYN8599_BDD8600\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~40_RESYN8597_BDD8598\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_RESYN8597_BDD8598\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~31_RESYN8595_BDD8596\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_RESYN8595_BDD8596\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector573~1_RESYN8589_BDD8590\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_RESYN8589_BDD8590\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector507~1_RESYN8587_BDD8588\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_RESYN8587_BDD8588\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585_BDD8586\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585_BDD8586\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector639~1_RESYN8583_BDD8584\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_RESYN8583_BDD8584\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575_BDD8576\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575_BDD8576\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector771~2_RESYN8571_BDD8572\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_RESYN8571_BDD8572\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561_BDD8562\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561_BDD8562\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559_BDD8560\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559_BDD8560\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557_BDD8558\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557_BDD8558\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_BDD8556\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_BDD8556\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547_BDD8548\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547_BDD8548\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545_BDD8546\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545_BDD8546\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529_BDD8530\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529_BDD8530\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527_BDD8528\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527_BDD8528\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513_BDD8514\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513_BDD8514\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501_BDD8502\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501_BDD8502\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_RESYN8497_BDD8498\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8497_BDD8498\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_RESYN8495_BDD8496\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8495_BDD8496\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~4_RESYN8493_BDD8494\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_RESYN8493_BDD8494\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_RESYN8491_BDD8492\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8491_BDD8492\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_RESYN8489_BDD8490\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489_BDD8490\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_RESYN8487_BDD8488\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_RESYN8483_BDD8484\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~4_RESYN8479_BDD8480\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_RESYN8479_BDD8480\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_RESYN8475_BDD8476\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8475_BDD8476\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_RESYN8473_BDD8474\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8473_BDD8474\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8469_BDD8470\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8469_BDD8470\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8467_BDD8468\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_BDD8468\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_RESYN8465_BDD8466\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8465_BDD8466\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_RESYN8463_BDD8464\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8463_BDD8464\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8461_BDD8462\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8461_BDD8462\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8459_BDD8460\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_BDD8460\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~6_RESYN8457_BDD8458\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~6_RESYN8457_BDD8458\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_RESYN8455_BDD8456\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8455_BDD8456\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_RESYN8453_BDD8454\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8453_BDD8454\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8449_BDD8450\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8449_BDD8450\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8447_BDD8448\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_BDD8448\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~5_RESYN8445_BDD8446\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445_BDD8446\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~5_RESYN8443_BDD8444\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443_BDD8444\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8437_BDD8438\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437_BDD8438\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8435_BDD8436\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435_BDD8436\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_RESYN8429_BDD8430\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_RESYN8427_BDD8428\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8427_BDD8428\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_RESYN8425_BDD8426\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8425_BDD8426\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_RESYN8423_BDD8424\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_RESYN8413_BDD8414\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413_BDD8414\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_RESYN8411_BDD8412\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411_BDD8412\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_RESYN13466_BDD13467\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466_BDD13467\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_RESYN13464_BDD13465\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_RESYN8959_RESYN13462_BDD13463\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_RESYN8941_RESYN13460_BDD13461\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_RESYN13460_BDD13461\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8937_RESYN13458_BDD13459\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_RESYN13458_BDD13459\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]_NEW2619_RESYN13446_BDD13447\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13446_BDD13447\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]_NEW2616_RESYN13442_BDD13443\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13442_BDD13443\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]_NEW2614_RESYN13438_BDD13439\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13438_BDD13439\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]_NEW2612_RESYN13434_BDD13435\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13434_BDD13435\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]_NEW2607_RESYN13426_BDD13427\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13426_BDD13427\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]_NEW2600_RESYN13414_BDD13415\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13414_BDD13415\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[55]_NEW2597_RESYN13410_BDD13411\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13410_BDD13411\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]_NEW2581_RESYN13386_BDD13387\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13386_BDD13387\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[50]_NEW2563_RESYN13362_BDD13363\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13362_BDD13363\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[39]_NEW2557_RESYN13354_BDD13355\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13354_BDD13355\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]_NEW2554_RESYN13350_BDD13351\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13350_BDD13351\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[38]_NEW2551_RESYN13346_BDD13347\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13346_BDD13347\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[32]_NEW2545_RESYN13338_BDD13339\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13338_BDD13339\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]_NEW2539_RESYN13330_BDD13331\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13330_BDD13331\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]_NEW2536_RESYN13326_BDD13327\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13326_BDD13327\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]_NEW2521_RESYN13306_BDD13307\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13306_BDD13307\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]_NEW2518_RESYN13302_BDD13303\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13302_BDD13303\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]_NEW2503_RESYN13282_BDD13283\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13282_BDD13283\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[3]_NEW2494_RESYN13270_BDD13271\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13270_BDD13271\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[2]_NEW2491_RESYN13266_BDD13267\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13266_BDD13267\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]_NEW2488_RESYN13262_BDD13263\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13262_BDD13263\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[58]_NEW2484_RESYN13254_BDD13255\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13254_BDD13255\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]_NEW2482_RESYN13250_BDD13251\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13250_BDD13251\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]_NEW2480_RESYN13246_BDD13247\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13246_BDD13247\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]_NEW2476_RESYN13238_BDD13239\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13238_BDD13239\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]_NEW2474_RESYN13234_BDD13235\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13234_BDD13235\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]_NEW2472_RESYN13230_BDD13231\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13230_BDD13231\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]_NEW2470_RESYN13226_BDD13227\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13226_BDD13227\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[52]_NEW2468_RESYN13222_BDD13223\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13222_BDD13223\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[52]_NEW2466_RESYN13218_BDD13219\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13218_BDD13219\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]_NEW2464_RESYN13214_BDD13215\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13214_BDD13215\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]_NEW2462_RESYN13210_BDD13211\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13210_BDD13211\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[50]_NEW2460_RESYN13206_BDD13207\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13206_BDD13207\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]_NEW2458_RESYN13202_BDD13203\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13202_BDD13203\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]_NEW2456_RESYN13198_BDD13199\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13198_BDD13199\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[45]_NEW2452_RESYN13190_BDD13191\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13190_BDD13191\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[51]_NEW2450_RESYN13186_BDD13187\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13186_BDD13187\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[51]_NEW2448_RESYN13182_BDD13183\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13182_BDD13183\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]_NEW2444_RESYN13174_BDD13175\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13174_BDD13175\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]_NEW2442_RESYN13170_BDD13171\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13170_BDD13171\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]_NEW2438_RESYN13162_BDD13163\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13162_BDD13163\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]_NEW2436_RESYN13158_BDD13159\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13158_BDD13159\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]_NEW2430_RESYN13146_BDD13147\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13146_BDD13147\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[38]_NEW2426_RESYN13138_BDD13139\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13138_BDD13139\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]_NEW2422_RESYN13130_BDD13131\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13130_BDD13131\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[43]_NEW2410_RESYN13106_BDD13107\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13106_BDD13107\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]_NEW2408_RESYN13102_BDD13103\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13102_BDD13103\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]_NEW2404_RESYN13094_BDD13095\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13094_BDD13095\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[29]_NEW2388_RESYN13070_BDD13071\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13070_BDD13071\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]_NEW2384_RESYN13062_BDD13063\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13062_BDD13063\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]_NEW2374_RESYN13048_BDD13049\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13048_BDD13049\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]_NEW2372_RESYN13044_BDD13045\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13044_BDD13045\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[26]_NEW2368_RESYN13038_BDD13039\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13038_BDD13039\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[26]_NEW2366_RESYN13034_BDD13035\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13034_BDD13035\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[22]_NEW2362_RESYN13028_BDD13029\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13028_BDD13029\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[21]_NEW2350_RESYN13010_BDD13011\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13010_BDD13011\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[23]_NEW2342_RESYN12998_BDD12999\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN12998_BDD12999\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]_NEW2340_RESYN12994_BDD12995\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12994_BDD12995\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]_NEW2334_RESYN12984_BDD12985\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12984_BDD12985\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[13]_NEW2326_RESYN12970_BDD12971\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12970_BDD12971\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]_NEW2324_RESYN12966_BDD12967\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12966_BDD12967\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[19]_NEW2320_RESYN12958_BDD12959\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12958_BDD12959\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[12]_NEW2316_RESYN12950_BDD12951\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12950_BDD12951\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_CR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_SPLITSPACE~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[16]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_ADDR[0][2]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_INT_ENABLE[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|INT_ENABLE[11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER[5]~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_ADDR[0][4]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_DAY_COUNTER[4]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_INT_ENABLE[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|INT_ENABLE[4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_ADDR[0][13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_ADDR[0][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_ADDR[0][16]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_End~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_NOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_PRECR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SD_DATA_VALID~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_DATA_VALID~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SD_RESET_TIMER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_CLOCK~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_DATA_LOADED~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~DUPLICATE_q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[34]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~DUPLICATE_q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[38]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[1]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[26]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_COUNTER[13]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_COUNTER[0]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[19]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[30]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[35]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[32]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[48]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[37]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[42]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[40]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[52]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[44]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[47]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[49]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[30]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[30]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[25]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER[0]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_TICK[23]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK[17]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[31]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[29]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[27]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[26]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[28]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[3]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[3]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER[8]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[8]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[7]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[6]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER[11]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER[10]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[9]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER[5]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER[5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[5]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[15]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[14]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[13]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[23]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[20]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[21]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[21]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[16]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[15]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[16]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[25]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[25]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[26]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[26]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_SD_RESET_TIMER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|TX_COUNTER[14]~DUPLICATE_q\; +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[19]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[20]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[22]~DUPLICATE_q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~DUPLICATE_q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[9]~DUPLICATE_q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3]~DUPLICATE_q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~131_Duplicate_173\ <= NOT \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~111_Duplicate_170\ <= NOT \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~127_Duplicate_167\ <= NOT \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~107_Duplicate_164\ <= NOT \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~95_Duplicate_161\ <= NOT \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~99_Duplicate_158\ <= NOT \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_155\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~65_Duplicate_152\ <= NOT \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[0]_OTERM1619\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]_OTERM1619\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]_OTERM1617\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1617\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]_OTERM1615\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1615\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1613\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1613\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1611\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1611\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1609\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1609\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]_OTERM1607\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1607\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]_OTERM1605\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1605\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]_OTERM1603\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1603\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]_OTERM1601\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1601\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]_OTERM1599\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1599\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]_OTERM1597\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1597\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1595\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1595\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1593\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1593\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[1]_OTERM1587\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]_OTERM1587\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[1]_OTERM1585\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]_OTERM1585\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]_OTERM1583\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1583\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]_OTERM1581\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1581\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1577\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1577\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]_OTERM1573\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1573\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]_OTERM1571\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1571\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[15]_OTERM1569\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[15]_OTERM1569\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1567\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1567\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1565\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1563\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1561\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1561\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[1]_OTERM1559\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]_OTERM1559\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]_OTERM1557\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1557\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]_OTERM1555\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1555\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]_OTERM1553\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1553\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]_OTERM1551\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1551\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1549\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1549\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1547\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1547\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1545\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1545\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1543\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1543\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1541\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1539\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1537\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1537\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[1]_OTERM1535\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]_OTERM1535\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1533\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1533\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1531\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1529\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1527\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1519\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1519\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1515\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1515\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1511\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1511\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1505\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1505\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1501\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1501\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]_OTERM1497\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1497\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]_OTERM1495\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1495\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1493\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1493\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1491\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1491\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1489\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1489\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1485\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1483\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1483\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]_OTERM1481\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1481\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]_OTERM1479\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1479\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1477\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1477\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1475\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1475\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1473\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1471\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1471\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1469\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1469\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1467\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1467\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1465\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1465\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1463\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1463\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1461\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1461\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1459\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1459\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1457\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1457\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1455\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1455\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]_OTERM1447\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1447\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]_OTERM1445\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1445\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1443\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1443\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1441\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1441\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1439\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1439\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1437\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1437\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1435\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1433\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1431\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1429\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1429\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1427\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1427\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1425\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1423\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1421\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1419\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1419\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]_OTERM1411\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1411\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]_OTERM1409\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1409\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]_OTERM1401\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1401\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]_OTERM1399\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1399\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1395\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1395\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[20]_OTERM1389\ <= NOT \myVirtualToplevel|IO_DATA_READ[20]_OTERM1389\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[20]_OTERM1387\ <= NOT \myVirtualToplevel|IO_DATA_READ[20]_OTERM1387\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1385\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1385\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1383\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1381\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1379\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1379\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]_OTERM1377\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1377\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]_OTERM1375\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1375\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1357\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1357\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1355\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1355\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1353\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1351\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1351\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1349\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1349\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1347\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1347\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1345\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1345\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1343\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1343\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1341\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1341\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1339\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1337\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1337\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1335\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1335\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1333\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1331\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1329\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1327\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1327\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1325\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1325\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1323\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1323\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1321\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1319\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1319\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1317\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1315\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1313\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1313\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1309\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[23]_OTERM1307\ <= NOT \myVirtualToplevel|IO_DATA_READ[23]_OTERM1307\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[23]_OTERM1305\ <= NOT \myVirtualToplevel|IO_DATA_READ[23]_OTERM1305\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1303\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1303\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1301\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1301\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1297\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1297\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1283\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1283\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1281\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1279\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1277\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1275\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1275\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1271\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1271\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1269\ <= NOT \myVirtualToplevel|IO_DATA_READ[22]_OTERM1269\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1267\ <= NOT \myVirtualToplevel|IO_DATA_READ[22]_OTERM1267\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1265\ <= NOT \myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1263\ <= NOT \myVirtualToplevel|IO_DATA_READ[22]_OTERM1263\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1261\ <= NOT \myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1259\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1259\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1255\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1253\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1251\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[9]_OTERM1249\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[9]_OTERM1249\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[7]_OTERM1247\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[7]_OTERM1247\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[5]_OTERM1245\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[5]_OTERM1245\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[6]_OTERM1243\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[6]_OTERM1243\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[12]_OTERM1241\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[12]_OTERM1241\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[16]_OTERM1239\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[16]_OTERM1239\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[17]_OTERM1237\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[17]_OTERM1237\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[18]_OTERM1235\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[18]_OTERM1235\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[19]_OTERM1233\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[19]_OTERM1233\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[10]_OTERM1231\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1231\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[10]_OTERM1229\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1229\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[11]_OTERM1227\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[11]_OTERM1227\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[4]_OTERM1225\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[4]_OTERM1225\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[1]_OTERM1223\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[1]_OTERM1223\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[8]_OTERM1221\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[8]_OTERM1221\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1219\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1219\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[21]_OTERM1215\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[21]_OTERM1215\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[20]_OTERM1213\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[20]_OTERM1213\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1209\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1205\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1205\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1203\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1203\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1201\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1201\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1199\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1199\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1197\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1197\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1195\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1195\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1193\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1193\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1191\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1191\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[13]_OTERM1189\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1189\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[13]_OTERM1187\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1187\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1185\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1185\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1183\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1183\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1181\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1181\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]_OTERM1179\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1179\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]_OTERM1177\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1177\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[22]_OTERM1175\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[22]_OTERM1175\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1173\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1173\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1169\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1169\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1159\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1159\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1157\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1157\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_END_OTERM1145\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_OTERM1145\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_END_OTERM1143\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_OTERM1143\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]_OTERM1141\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1141\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]_OTERM1139\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1139\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]_OTERM1137\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1137\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]_OTERM1135\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1135\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]_OTERM1133\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1133\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]_OTERM1131\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1131\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1119\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1119\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1116\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1116\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1114\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1114\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1112\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1112\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1110\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1110\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1108\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1108\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]_OTERM1106\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1106\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]_OTERM1104\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1104\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]_OTERM1102\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1102\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]_OTERM1100\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1100\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]_OTERM1092\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1092\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]_OTERM1090\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1090\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]_OTERM1088\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1088\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]_OTERM1086\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1086\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1084\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]_OTERM1084\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1082\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1080\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]_OTERM1080\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1078\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]_OTERM1078\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1076\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]_OTERM1076\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1074\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]_OTERM1074\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]_OTERM1072\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1072\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]_OTERM1070\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1070\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1054\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1054\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1052\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1052\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM998\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM998\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM996\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM996\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM994\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM994\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM992\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM992\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM990\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM990\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM988\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM988\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM984\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM984\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[29]_OTERM970\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[29]_OTERM970\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM948\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM948\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]_OTERM936\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM936\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]_OTERM934\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM934\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[16]_OTERM932\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM932\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[16]_OTERM930\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM930\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[7]_OTERM928\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM928\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[7]_OTERM926\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM926\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]_OTERM924\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM924\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]_OTERM922\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM922\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]_OTERM920\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM920\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]_OTERM918\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM918\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]_OTERM916\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM916\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]_OTERM914\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM914\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]_OTERM912\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM912\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]_OTERM910\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM910\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]_OTERM908\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM908\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]_OTERM906\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM906\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[26]_OTERM904\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[26]_OTERM904\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM902\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM900\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM900\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM898\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM898\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM896\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM896\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM894\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM894\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM892\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM892\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM890\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM890\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[17]_OTERM888\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM888\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[17]_OTERM886\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM886\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM882\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM882\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM880\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM878\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM876\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM874\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM874\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM872\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM872\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM870\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM870\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]_OTERM868\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM868\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]_OTERM866\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM866\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]_OTERM864\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM864\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]_OTERM862\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM862\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]_OTERM860\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM860\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]_OTERM858\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM858\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]_OTERM856\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM856\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]_OTERM854\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM854\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]_OTERM852\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM852\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]_OTERM850\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM850\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]_OTERM848\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM848\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]_OTERM846\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM846\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]_OTERM844\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM844\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]_OTERM842\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM842\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]_OTERM840\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM840\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]_OTERM838\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM838\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]_OTERM836\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_OTERM836\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]_OTERM834\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_OTERM834\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]_OTERM832\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM832\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]_OTERM830\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM830\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]_OTERM828\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM828\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]_OTERM826\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM826\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]_OTERM824\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM824\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]_OTERM822\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM822\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]_OTERM820\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM820\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]_OTERM818\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM818\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]_OTERM816\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM816\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]_OTERM814\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM814\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]_OTERM812\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM812\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]_OTERM810\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM810\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM808\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM808\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM806\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM806\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[28]_OTERM800\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM800\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[28]_OTERM798\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM798\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM796\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM796\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM792\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM792\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM790\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM788\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM788\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM784\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM784\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM782\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM782\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM780\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM780\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM778\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM778\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM776\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM776\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM774\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM774\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM772\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM772\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]_OTERM770\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM770\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]_OTERM768\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM768\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]_OTERM766\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_OTERM766\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]_OTERM764\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_OTERM764\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]_OTERM762\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM762\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]_OTERM760\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM760\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]_OTERM758\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM758\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]_OTERM756\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM754\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM754\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM750\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM750\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM746\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM746\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM743\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM743\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM741\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM741\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM737\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM737\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM734\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM734\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM732\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM732\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM728\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM728\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM725\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM725\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM723\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM723\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM719\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM719\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM715\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM713\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM713\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM711\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM709\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM709\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[26]_OTERM707\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM707\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[26]_OTERM705\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM705\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM703\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM703\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM701\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM701\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM699\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM699\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM697\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM697\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM695\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM695\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM693\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM693\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM691\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM691\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM689\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM689\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM687\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM687\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM685\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM685\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM683\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM683\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM681\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM681\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM679\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM679\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM677\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM675\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM675\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM673\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM673\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM671\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM671\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM669\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM669\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM667\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM667\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM665\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM665\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM663\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM663\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM661\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM659\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM657\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM657\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM655\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM655\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM651\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM651\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM649\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM649\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM647\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM647\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM645\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM645\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM643\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM643\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM641\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM641\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM639\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM639\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM637\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM637\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM635\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM635\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM633\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM633\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM631\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM631\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM629\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM629\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM627\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM627\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM625\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM625\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM623\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM621\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM621\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM619\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM619\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM617\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM615\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM615\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM613\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM613\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM611\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM611\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM609\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM609\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM607\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM607\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM605\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM605\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM603\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM603\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM601\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM601\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM599\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM599\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM597\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM597\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM595\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM595\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM593\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM593\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM591\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM591\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM589\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM589\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM587\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM587\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM585\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM585\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM583\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM583\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM581\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM581\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM579\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM579\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM577\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM577\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM575\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM575\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM573\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM573\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM571\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM571\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM569\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM569\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM567\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM567\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM565\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM565\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM563\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM563\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM561\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM561\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM559\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM559\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM557\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM557\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM555\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM555\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM553\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM553\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM551\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM551\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM549\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM549\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM547\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM547\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM545\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM545\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM543\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM543\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM541\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM539\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM537\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM535\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM533\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM531\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM529\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM529\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM527\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM527\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM525\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM525\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM523\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM523\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM521\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM521\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM519\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM519\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM517\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM517\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM515\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM515\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM513\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM513\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM511\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM511\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM507\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM507\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM499\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM499\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM497\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM497\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM495\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM495\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM491\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM491\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM489\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM489\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM487\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM487\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM485\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM483\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM483\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM481\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM481\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM479\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM479\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM477\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM477\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM475\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM475\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM473\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM473\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM471\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM469\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM467\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM467\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM465\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM465\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM463\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM463\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM461\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM461\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM459\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM459\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM457\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM457\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM455\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM455\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM453\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM453\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM451\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM451\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM449\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM449\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM447\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM447\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM445\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM445\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM443\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM443\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM437\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM435\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM435\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM433\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM433\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM431\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM431\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM429\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM429\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM427\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM427\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM425\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM425\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM423\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM423\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM421\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM421\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM417\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM417\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM415\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM415\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM413\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM413\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM411\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM411\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM409\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM409\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM407\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM407\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM405\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM405\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM403\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM403\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM401\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM401\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM399\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM399\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM397\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM397\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM395\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM395\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM393\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM393\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM391\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM391\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM389\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM389\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM387\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM387\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM385\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM385\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM383\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM383\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM381\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM381\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM379\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM379\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM377\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM375\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM373\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM373\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM371\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM371\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM369\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM369\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM367\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM367\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_SPLIT_DATA[0]_OTERM363\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[0]_OTERM363\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM361\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM361\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM359\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM359\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM357\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM357\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM355\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM355\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM353\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM353\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM351\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM351\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM349\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM349\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM347\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM347\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM345\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM345\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM343\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM343\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM341\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM341\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM339\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM337\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM335\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM335\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM333\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM329\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM329\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM327\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM327\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM325\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM325\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM323\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM323\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM321\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM317\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM317\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM313\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM313\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM311\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM311\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM309\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM309\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM307\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM307\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM305\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM305\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM303\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM301\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM301\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM299\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM297\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM297\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM295\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM295\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM293\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM293\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM291\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM291\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM289\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM289\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM287\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM287\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM285\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM285\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM283\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM283\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM279\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM279\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM277\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM277\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM275\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM273\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM273\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM271\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM271\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM269\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM265\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM265\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM263\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM263\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM261\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM261\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM257\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM257\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM255\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM255\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM253\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM253\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM249\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM249\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM247\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM247\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM245\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM245\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM243\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM241\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM241\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM239\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM237\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM237\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM235\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM235\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM231\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM231\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM229\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM229\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM227\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM225\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM223\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM165\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM165\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM163\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM163\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM161\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM161\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM159\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM159\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM157\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM155\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]_OTERM151\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM151\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]_OTERM149\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM149\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM145\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM145\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM143\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM143\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM141\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM141\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM139\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM139\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM137\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM137\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM135\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM135\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM133\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM133\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM131\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM131\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM129\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM129\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM127\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM127\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM125\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM125\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM123\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM123\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM121\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM119\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM117\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM117\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM115\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM115\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM113\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM113\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM111\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM111\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM109\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM109\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM107\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM103\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM103\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[12]_OTERM101\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]_OTERM101\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[13]_OTERM99\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]_OTERM99\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[14]_OTERM97\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]_OTERM97\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[15]_OTERM95\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]_OTERM95\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]_OTERM93\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM93\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]_OTERM91\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM91\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]_OTERM89\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector77~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux316~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux316~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux370~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux370~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux340~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux340~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux402~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux402~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux118~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux118~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux54~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux54~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux182~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux182~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux246~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux246~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux312~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux312~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux366~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux366~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux336~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux336~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux398~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux398~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux114~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux114~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux50~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux50~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux178~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux178~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux242~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux242~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1455~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1455~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1391~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1571~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1571~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1453~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1453~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector79~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux318~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux318~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux372~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux372~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux342~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux342~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux404~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux404~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux120~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux120~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux56~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux56~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux184~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux184~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux248~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux248~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~55_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~54_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~53_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~52_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector75~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector75~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux314~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux314~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux368~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux368~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux338~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux338~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux400~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux400~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux116~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux116~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux52~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux52~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux180~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux180~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux244~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux244~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1457~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1457~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1393~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1573~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1573~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1452~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1452~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1388~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector78~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux317~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux317~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux371~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux371~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux341~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux341~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux403~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux403~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux119~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux119~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux55~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux55~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux183~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux183~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux247~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux247~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux313~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux313~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux367~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux367~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux337~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux337~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux399~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux399~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux115~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux115~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux51~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux51~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux179~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux179~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux243~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux243~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1456~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1456~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1392~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1572~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1572~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1377~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1377~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[41]~17_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~17_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(40) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(40); +\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(1) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(1); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[41]~16_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~16_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_DATA~14_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~14_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~23_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~23_q\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(22) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(22); +\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(6) <= NOT \myVirtualToplevel|UART0|TX_DATA\(6); +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(14) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(14); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][20]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][19]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][18]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][8]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][14]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][13]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][2]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][1]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][7]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][6]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][12]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][5]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][4]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][3]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][17]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][22]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][24]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][25]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][26]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][16]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][15]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][27]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][11]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][23]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][21]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][29]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][28]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][10]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][9]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][31]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][30]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~3_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal0~3_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~2_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal0~2_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~1_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal0~1_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal0~0_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~1_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\; +\myVirtualToplevel|ALT_INV_TIMER_REG_REQ~q\ <= NOT \myVirtualToplevel|TIMER_REG_REQ~q\; +\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(11) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector117~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~47_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector76~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector76~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~45_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux315~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux315~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux369~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux369~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux339~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux339~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux401~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux401~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux117~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux117~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux53~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux53~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux181~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux181~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux245~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux245~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1454~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1454~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux311~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux311~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux365~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux365~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux335~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux335~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux397~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux397~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux113~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux113~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux49~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux49~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux177~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux177~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux241~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux241~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1450~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1450~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1386~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1383~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1383~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux308~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux308~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux362~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux362~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux332~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux332~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux394~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux394~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux110~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux110~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux46~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux46~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux304~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux304~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux358~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux358~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux328~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux328~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux390~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux390~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux106~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux106~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux42~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux42~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux170~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux170~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux234~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux234~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux310~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux310~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux364~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux364~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux334~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux334~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux396~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux396~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux112~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux112~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux48~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux48~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux176~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux176~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux240~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux240~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux306~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux306~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux360~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux360~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux330~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux330~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux392~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux392~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux108~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux108~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux44~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux44~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux172~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux172~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux236~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux236~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1449~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1449~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1385~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[62]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1384~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1384~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux309~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux309~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux363~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux363~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux333~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux333~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux395~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux395~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux111~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux111~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux47~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux47~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux305~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux305~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux359~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux359~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux329~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux329~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux391~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux391~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux107~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux107~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux43~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux43~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux171~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux171~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux235~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux235~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_SPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_CRLF~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA4~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA4~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA4~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA3~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA3~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_NOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_NOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_NOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_TOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux208~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux208~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux272~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux272~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1481~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1481~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1417~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]~81_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector99~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux140~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux140~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux76~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux76~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux204~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux204~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux268~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux268~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1477~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1535~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1535~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~79_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~79_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector102~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector102~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~78_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux79~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux79~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]~77_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector98~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux139~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux139~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux75~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux75~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux203~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux203~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux267~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux267~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1476~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1476~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1534~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1534~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~2_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(14) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1478~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1536~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1536~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]~76_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector100~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux141~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux141~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux77~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux77~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux205~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux205~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux269~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux269~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]~75_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector96~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux137~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux137~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux73~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux73~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux201~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux201~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux265~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux265~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1474~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1474~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1532~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1532~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]~74_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector93~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux134~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux134~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux70~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux70~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux198~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux198~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux262~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux262~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1471~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1471~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1529~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1529~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1585~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]~73_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector89~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux130~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux130~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux66~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux66~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux194~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux194~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux258~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux258~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1467~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1467~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]~72_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector95~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux136~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux136~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux72~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux72~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux200~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux200~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux264~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux264~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1473~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1473~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1531~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1531~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]~71_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector91~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux132~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux132~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux68~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux68~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux196~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux196~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux260~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux260~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1469~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1469~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]~70_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector94~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux135~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux135~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux71~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux71~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux199~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux199~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux263~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux263~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1472~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1472~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1530~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1530~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]~69_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector90~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux131~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux131~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux67~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux67~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux195~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux195~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux259~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux259~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1468~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1468~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~23_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(38) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(38); +\myVirtualToplevel|UART0|ALT_INV_TX_DATA~18_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~18_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~25_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~25_q\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(24) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(24); +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(16) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(16); +\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(13) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector115~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]~68_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector92~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux133~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux133~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux69~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux69~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux197~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux197~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux261~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux261~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1470~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1470~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]~67_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector88~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux129~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux129~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux65~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux65~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux193~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux193~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux257~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux257~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1466~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1466~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]~66_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector85~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux126~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux126~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux62~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux62~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1399~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]~65_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector81~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux320~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux320~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux374~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux374~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux344~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux344~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux406~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux406~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux122~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux122~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux58~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux58~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux186~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux186~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux250~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux250~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1459~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1459~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1575~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1575~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector87~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux128~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux128~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux64~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux64~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux192~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux192~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux256~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux256~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1465~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1465~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector83~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux322~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux322~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux408~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux408~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux376~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux376~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux124~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux124~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux60~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux60~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux188~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux188~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux252~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux252~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1461~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1577~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1577~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]~62_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector86~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux127~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux127~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux63~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux63~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1400~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]~61_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector82~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux321~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux321~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux375~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux375~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux345~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux345~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux407~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux407~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux123~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux123~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux59~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux59~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux187~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux187~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux251~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux251~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1460~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1460~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1576~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1576~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(16); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[40]~21_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~21_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[40]~20_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~20_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[6]~19_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal8~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal8~0_combout\; +\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(0) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(0); +\myVirtualToplevel|UART0|ALT_INV_TX_DATA~16_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~16_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~24_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~24_q\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(23) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(23); +\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(7) <= NOT \myVirtualToplevel|UART0|TX_DATA\(7); +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(15) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(15); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_index\(0) <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_index\(0); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(12) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux409~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux409~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux377~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux377~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux125~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux125~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux61~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux61~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux189~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux189~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux253~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux253~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector84~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux323~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux323~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1462~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1398~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1398~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1578~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1578~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector80~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux319~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux319~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux373~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux373~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux343~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux343~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux405~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux405~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux121~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux121~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux57~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux57~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux185~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux185~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux249~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux249~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1458~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1458~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1574~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1574~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1451~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1451~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]_OTERM87\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM87\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]_OTERM85\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM85\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]_OTERM83\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM83\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]_OTERM81\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM81\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]_OTERM79\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM79\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[16]_OTERM77\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]_OTERM77\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[21]_OTERM75\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_OTERM75\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[22]_OTERM73\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_OTERM73\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[20]_OTERM71\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]_OTERM71\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[23]_OTERM69\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[17]_OTERM67\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]_OTERM67\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[18]_OTERM65\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_OTERM65\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[19]_OTERM63\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]_OTERM63\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]_OTERM61\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM61\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]_OTERM59\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM57\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM55\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[9]_OTERM53\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]_OTERM53\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[10]_OTERM51\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]_OTERM51\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[11]_OTERM49\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]_OTERM49\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM47\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM47\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM45\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM45\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM43\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM41\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM41\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[8]_OTERM39\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]_OTERM39\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]_OTERM37\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM37\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]_OTERM35\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM35\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM33\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM31\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM31\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]_OTERM29\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM29\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]_OTERM27\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM27\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]_OTERM25\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM25\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]_OTERM23\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM23\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]_OTERM21\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM21\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]_OTERM19\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM19\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM17\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM17\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM15\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM15\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]_OTERM11\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]_OTERM9\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM7\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM7\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM5\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM5\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\; +\mypll|altpll_component|auto_generated|ALT_INV_wire_generic_pll1_locked\ <= NOT \mypll|altpll_component|auto_generated|wire_generic_pll1_locked\; +\ALT_INV_UART_RX_1~input_o\ <= NOT \UART_RX_1~input_o\; +\ALT_INV_UART_RX_0~input_o\ <= NOT \UART_RX_0~input_o\; +\ALT_INV_SDCARD_MISO[0]~input_o\ <= NOT \SDCARD_MISO[0]~input_o\; +\ALT_INV_KEY~input_o\ <= NOT \KEY~input_o\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~438_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~436_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~436_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~435_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~435_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~160_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~160_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~166_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~166_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~165_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~17_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~17_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~16_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~434_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~434_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~433_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~432_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~431_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~430_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~429_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~428_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~427_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~426_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1429~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~164_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[0]~94_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~92_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[3]~92_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~90_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[4]~90_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~88_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[5]~88_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~86_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[6]~86_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~84_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[7]~84_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~82_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[8]~82_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~80_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[9]~80_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~78_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[10]~78_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~76_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[11]~76_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~74_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[12]~74_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~72_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[13]~72_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~70_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[14]~70_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~68_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[15]~68_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector214~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector213~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector212~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector211~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector210~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector209~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector208~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector207~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector206~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector205~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector204~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector203~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector202~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector201~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector199~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector198~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector197~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector196~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector195~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector194~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector193~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~157_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~157_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~156_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~156_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~155_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~152_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~152_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~150_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~150_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~149_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~149_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~2_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector157~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector157~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(1); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[3]~41_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~41_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(2); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector154~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(3); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[5]~39_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~39_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(4); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[6]~37_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~37_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(5); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(6); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(7) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(7); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[9]~34_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~34_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(9) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(9); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[11]~32_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~32_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(11) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(11); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[13]~30_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~30_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(13) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(13); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[15]~28_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~28_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[16]~26_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~26_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(15) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(15); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(16) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1561~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1561~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1563~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1563~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1506~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1562~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1562~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1508~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1564~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1564~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR:tInsnExec~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux428~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux428~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1560~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1560~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1501~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1501~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux425~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux425~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1557~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1557~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1497~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1497~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1503~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1559~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1559~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1499~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1499~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1437~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1437~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1502~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1440~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1440~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1558~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1558~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1498~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1498~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1500~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1500~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1496~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1496~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux282~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux282~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux154~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux154~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux90~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux90~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux218~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux218~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1491~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1491~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1427~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1495~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1495~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add40~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add40~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux284~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux284~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux156~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux156~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux92~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux92~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1493~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1429~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux283~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux283~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux155~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux155~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux91~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux91~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux219~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux219~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1548~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1548~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(16) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux93~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux93~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux285~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux285~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux157~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux157~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux221~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux221~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1494~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux418~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux418~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1550~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1550~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux153~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux153~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux89~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux89~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux217~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux217~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux281~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux281~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1546~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1546~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux150~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux150~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux86~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux86~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux214~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux214~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux278~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux278~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1487~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1487~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1599~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[3]~98_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~98_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[3]~97_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~97_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux146~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux146~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux82~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux82~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux210~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux210~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux274~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux274~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1483~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1483~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux152~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux152~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux88~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux88~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux216~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux216~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux280~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux280~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1489~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1489~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1425~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~95_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~95_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~94_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~94_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux148~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux148~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux84~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux84~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux212~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux212~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux276~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux276~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1485~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1485~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1421~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux151~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux151~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux87~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux87~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux215~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux215~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux279~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux279~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1544~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1544~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[2]~92_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~92_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[2]~91_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~91_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~90_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux147~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux147~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux83~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux83~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux211~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux211~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux275~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux275~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(15) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux149~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux149~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux85~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux85~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux213~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux213~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux277~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux277~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[4]~87_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~87_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector104~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector104~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux145~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux145~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux81~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux81~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux209~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux209~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux273~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux273~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[7]~85_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~85_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector101~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector101~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux142~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux142~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux78~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux78~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1415~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]~84_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector97~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux138~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux138~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux74~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux74~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux202~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux202~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux266~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux266~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1475~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1475~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1533~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1533~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[5]~82_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~82_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector103~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector103~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux144~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux144~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux80~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux80~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_PC~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_PC~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_PC~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_PC~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_SP~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_SP~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DECODED_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_PRE_CR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~14_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~14_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~13_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~13_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(41) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(41); +\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(2) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(2); +\myVirtualToplevel|UART0|ALT_INV_TX_DATA~12_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~12_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~22_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~22_q\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(21) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(21); +\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(5) <= NOT \myVirtualToplevel|UART0|TX_DATA\(5); +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(13) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(13); +\myVirtualToplevel|UART0|ALT_INV_RX_DATA~18_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~18_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~19_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~19_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(18) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(18); +\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(2) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(2); +\myVirtualToplevel|UART1|ALT_INV_RX_DATA~18_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~18_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~19_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~19_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(18) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(18); +\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(2) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~30_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA~16_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~16_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~18_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~18_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(17) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(17); +\myVirtualToplevel|UART1|ALT_INV_RX_DATA~16_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~16_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~18_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~18_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(17) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(17); +\myVirtualToplevel|UART1|ALT_INV_Add9~39_combout\ <= NOT \myVirtualToplevel|UART1|Add9~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~25_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(14) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(14); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(0) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(0); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(15) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(13) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(13); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(12) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(12); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(6) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(6); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(5) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(5); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(4) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(4); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(3) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(3); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(2) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(2); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(1) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(1); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(11) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(11); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(10) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(10); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(9) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(9); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(8) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(8); +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(7) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(7); +\myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~2_combout\ <= NOT \myVirtualToplevel|UART0|RX_STATE.stop~2_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(1) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(1); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(14) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(14); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(0) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(0); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(15) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(15); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(13) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(13); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(12) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(12); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(6) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(6); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(5) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(5); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(4) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(4); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(3) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(3); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(2) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(2); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(1) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(1); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(11) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(11); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(10) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(10); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(9) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(9); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(8) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(8); +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(7) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(7); +\myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~2_combout\ <= NOT \myVirtualToplevel|UART1|RX_STATE.stop~2_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(1) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(1); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~8_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~7_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~7_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~6_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~6_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~5_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~5_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~4_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~4_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~3_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~3_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~2_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~2_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~1_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~1_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~0_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][31]~0_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescaled_tick~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|prescaled_tick~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled\(0) <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_enabled\(0); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector3~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(0) <= NOT \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(0); +\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(2) <= NOT \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(2); +\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(3) <= NOT \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(3); +\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(4) <= NOT \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(4); +\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(5) <= NOT \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(5); +\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(10) <= NOT \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(10); +\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(10) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[0]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\; +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending~6_combout\ <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~6_combout\; +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending~5_combout\ <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector300~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector298~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector298~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector295~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector295~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector297~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector297~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan9~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_PreSetAddr~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_PreSetAddr~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux307~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux307~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux361~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux361~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux331~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux331~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux393~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux393~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux109~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux109~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux45~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux45~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux173~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux173~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux237~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux237~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux303~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux303~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux357~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux357~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux327~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux327~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux389~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux389~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux105~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux105~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux41~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux41~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux169~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux169~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux233~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux233~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux350~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux350~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux290~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux290~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux382~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux382~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux296~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux296~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux98~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux98~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux34~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux34~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux162~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux162~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux226~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux226~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux300~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux300~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux354~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux354~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux324~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux324~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux386~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux386~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux102~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux102~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux38~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux38~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux166~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux166~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux230~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux230~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux352~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux352~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux292~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux292~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux384~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux384~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux298~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux298~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux100~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux100~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux36~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux36~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux164~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux164~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux228~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux228~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux302~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux302~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux356~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux356~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux326~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux326~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux388~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux388~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux104~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux104~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux40~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux40~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux168~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux168~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux232~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux232~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux351~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux351~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux291~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux291~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux383~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux383~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux297~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux297~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux99~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux99~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux35~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux35~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux163~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux163~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux227~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux227~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux301~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux301~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux355~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux355~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux325~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux325~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux387~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux387~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux103~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux103~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux39~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux39~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux167~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux167~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux231~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux231~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_SPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_SPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_SPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_SPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_CRLF~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA4~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA4~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA4~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA3~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA3~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA3~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA3~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_NOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_TOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_TOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_TOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_TOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_PC~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_SP~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DECODED_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DECODED_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Decoder0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_PRE_CR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_PRE_CR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~4_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~3_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~3_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~2_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(42) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(42); +\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(3) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(3); +\myVirtualToplevel|UART0|ALT_INV_TX_DATA~10_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~10_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~21_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~21_q\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(20) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(20); +\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(4) <= NOT \myVirtualToplevel|UART0|TX_DATA\(4); +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(12) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(12); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]~35_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(1); +\myVirtualToplevel|ALT_INV_SD_ADDR[0][1]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][1]~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(1) <= NOT \myVirtualToplevel|UART0|RX_DATA\(1); +\myVirtualToplevel|ALT_INV_IO_DATA_READ~98_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~98_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FULL_V~q\ <= NOT \myVirtualToplevel|UART1|RX_FULL_V~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FULL_V~q\ <= NOT \myVirtualToplevel|UART0|RX_FULL_V~q\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(1) <= NOT \myVirtualToplevel|UART1|RX_DATA\(1); +\myVirtualToplevel|ALT_INV_IO_DATA_READ~97_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~97_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~96_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~96_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~95_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~95_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~94_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~94_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~49_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~147_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~147_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~144_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~144_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~142_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~142_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~137_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~137_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]~34_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(0); +\myVirtualToplevel|ALT_INV_SD_ADDR[0][0]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][0]~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(0) <= NOT \myVirtualToplevel|UART0|RX_DATA\(0); +\myVirtualToplevel|ALT_INV_IO_DATA_READ~92_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~92_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_EMPTY_V~q\ <= NOT \myVirtualToplevel|UART1|RX_EMPTY_V~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_EMPTY_V~q\ <= NOT \myVirtualToplevel|UART0|RX_EMPTY_V~q\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(0) <= NOT \myVirtualToplevel|UART1|RX_DATA\(0); +\myVirtualToplevel|ALT_INV_IO_DATA_READ~91_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~91_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~90_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~90_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~89_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~89_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~88_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~88_combout\; +\myVirtualToplevel|UART1|ALT_INV_Add9~34_combout\ <= NOT \myVirtualToplevel|UART1|Add9~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~135_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~135_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~130_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~130_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~129_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~129_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~128_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~122_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~122_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~121_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~121_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~120_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~120_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~119_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~113_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~113_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~112_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~112_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]~33_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][24]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][24]~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(8) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8); +\myVirtualToplevel|ALT_INV_IO_DATA_READ[24]~86_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[24]~86_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~47_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][27]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][27]~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(11) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(11); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]~32_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~16_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]~31_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][26]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][26]~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(10) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~15_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][25]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][25]~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(9) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(9); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]~30_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~99_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~99_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~98_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~98_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~97_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~97_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~96_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~96_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~95_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~95_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~94_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~44_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~92_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~92_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~91_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~91_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~88_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~88_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~8_combout\; +\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~8_combout\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER~8_combout\; +\myVirtualToplevel|ALT_INV_RTC_TICK_HALT~q\ <= NOT \myVirtualToplevel|RTC_TICK_HALT~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~33_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~33_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~32_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~32_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~31_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~31_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal3~3_combout\ <= NOT \myVirtualToplevel|UART0|Equal3~3_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_STATE.start~q\ <= NOT \myVirtualToplevel|UART0|RX_STATE.start~q\; +\myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\ <= NOT \myVirtualToplevel|UART0|Equal1~4_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal1~3_combout\ <= NOT \myVirtualToplevel|UART0|Equal1~3_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(15) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(15); +\myVirtualToplevel|UART0|ALT_INV_Equal1~2_combout\ <= NOT \myVirtualToplevel|UART0|Equal1~2_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal1~1_combout\ <= NOT \myVirtualToplevel|UART0|Equal1~1_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|UART0|Equal1~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~0_combout\ <= NOT \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[0]~1_combout\ <= NOT \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\ <= NOT \myVirtualToplevel|UART0|RX_STATE.idle~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\ <= NOT \myVirtualToplevel|UART0|RX_STATE.bits~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(0) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(0); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~33_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~33_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~32_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~32_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~31_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~31_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal3~3_combout\ <= NOT \myVirtualToplevel|UART1|Equal3~3_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~q\ <= NOT \myVirtualToplevel|UART1|RX_STATE.start~q\; +\myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\ <= NOT \myVirtualToplevel|UART1|Equal1~4_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal1~3_combout\ <= NOT \myVirtualToplevel|UART1|Equal1~3_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(15) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(15); +\myVirtualToplevel|UART1|ALT_INV_Equal1~2_combout\ <= NOT \myVirtualToplevel|UART1|Equal1~2_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal1~1_combout\ <= NOT \myVirtualToplevel|UART1|Equal1~1_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal1~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~0_combout\ <= NOT \myVirtualToplevel|UART1|RX_STATE.stop~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[0]~1_combout\ <= NOT \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\ <= NOT \myVirtualToplevel|UART1|RX_STATE.idle~q\; +\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(0) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(0); +\myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\ <= NOT \myVirtualToplevel|UART1|RX_STATE.bits~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_process_3~0_combout\ <= NOT \myVirtualToplevel|UART0|process_3~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_process_3~0_combout\ <= NOT \myVirtualToplevel|UART1|process_3~0_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_ticks\(0) <= NOT \myVirtualToplevel|TIMER:TIMER1|ticks\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~29_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~29_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][31]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][31]~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(15) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~11_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][30]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][30]~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(14) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(14); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]~28_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]~27_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][29]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][29]~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(13) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~9_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][28]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][28]~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(12) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(12); +\myVirtualToplevel|ALT_INV_IO_DATA_READ[26]~78_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[26]~78_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]~26_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26_combout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~1_combout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1349~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector363~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\; +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\ <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector363~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~104_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~102_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~102_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~94_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~94_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~92_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~92_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~90_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~88_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~88_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~87_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~85_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~85_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~83_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~83_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal12~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal12~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~82_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~82_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~157_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~157_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~156_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~156_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~155_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~155_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~154_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~154_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~152_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~149_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~149_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal131~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal131~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~80_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~80_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~79_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~79_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux133~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux133~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux135~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux135~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~78_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~77_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~76_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal67~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal67~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~71_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal46~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal46~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~69_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~68_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~68_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~67_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~66_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~66_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~59_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal99~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux121~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux121~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux123~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~51_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~50_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~57_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~56_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~146_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~146_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~145_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~145_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~144_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~144_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~143_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~143_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~141_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~141_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~140_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~140_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~139_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~139_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~138_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~138_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~136_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~136_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~135_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~135_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~134_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~134_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~133_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~133_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~131_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~131_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~130_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~130_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~129_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~129_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~128_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~128_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~126_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~126_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~125_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~125_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~124_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~124_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~123_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~123_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~121_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~121_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~120_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~120_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~119_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~119_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~118_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~118_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~116_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~116_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~115_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~115_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~114_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~114_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~113_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~113_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~111_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~111_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~110_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~110_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~109_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~109_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~108_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~108_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~106_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~106_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~105_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~105_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~104_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~104_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~103_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~103_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~101_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~101_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~100_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~100_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~99_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~99_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~98_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~98_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~96_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~96_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~95_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~95_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~94_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~94_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~93_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~93_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~91_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~91_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~90_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~90_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~89_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~89_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~88_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~88_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~86_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~86_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~85_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~85_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~84_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~84_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~83_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~83_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~81_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~78_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~78_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~77_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~77_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~75_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~75_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~74_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~74_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~73_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~73_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~72_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~72_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~70_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~70_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~69_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~69_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~68_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~68_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~67_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~67_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~65_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~65_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~64_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~63_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~62_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~62_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~55_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~54_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~53_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~49_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~45_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~44_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~37_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~50_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~47_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~45_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~44_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux92~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux92~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux93~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux93~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector120~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector120~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector52~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector52~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector48~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector48~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector45~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector45~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector47~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector47~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector46~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector46~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~51_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SEPERATOR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~45_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~44_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector42~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector13~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector13~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~35_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector42~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal2~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_SPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_SPLITSPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector111~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_NIBBLECNT~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~1_combout\; +\myVirtualToplevel|ALT_INV_Selector14~1_combout\ <= NOT \myVirtualToplevel|Selector14~1_combout\; +\myVirtualToplevel|ALT_INV_Selector14~0_combout\ <= NOT \myVirtualToplevel|Selector14~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[45]~9_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~9_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(44) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(44); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[45]~8_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~8_combout\; +\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(5) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~58_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~58_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(2); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~33_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~33_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~32_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~32_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~31_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~31_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal6~4_combout\ <= NOT \myVirtualToplevel|UART0|Equal6~4_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal6~3_combout\ <= NOT \myVirtualToplevel|UART0|Equal6~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_DATA~6_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~6_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~19_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~19_q\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(18) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(18); +\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(2) <= NOT \myVirtualToplevel|UART0|TX_DATA\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25); +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(10) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]~54_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]~56_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]~58_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~65_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~65_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~58_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[0]~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]~59_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]~53_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[1]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~53_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[1]~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~55_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~57_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[1]~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]~64_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[1]~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]~57_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~58_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[1]~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~51_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[0]~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~54_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~62_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~61_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector573~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~80_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~80_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~45_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~44_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~79_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~79_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~78_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~78_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~67_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~67_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA~12_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~12_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~21_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~21_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(20) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(20); +\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(4) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(4); +\myVirtualToplevel|UART1|ALT_INV_Equal3~2_combout\ <= NOT \myVirtualToplevel|UART1|Equal3~2_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal3~1_combout\ <= NOT \myVirtualToplevel|UART1|Equal3~1_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal3~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal3~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal3~2_combout\ <= NOT \myVirtualToplevel|UART0|Equal3~2_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal3~1_combout\ <= NOT \myVirtualToplevel|UART0|Equal3~1_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal3~0_combout\ <= NOT \myVirtualToplevel|UART0|Equal3~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA~12_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~12_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~21_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~21_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(20) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(20); +\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(4) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(4); +\myVirtualToplevel|UART1|ALT_INV_Add9~28_combout\ <= NOT \myVirtualToplevel|UART1|Add9~28_combout\; +\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~5_combout\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector355~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~77_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~77_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~92_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~92_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~76_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~76_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~75_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~0_combout\; +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(8) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(8); +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~62_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~61_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[24]~61_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~60_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[24]~60_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(24) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(24); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(24) <= NOT \myVirtualToplevel|IO_DATA_READ\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~74_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~74_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~73_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~73_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~64_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~63_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA~10_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~10_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~25_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~25_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(24) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(24); +\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(8) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(8); +\myVirtualToplevel|UART1|ALT_INV_RX_DATA~10_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~10_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~25_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~25_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(24) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(24); +\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(8) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(8); +\myVirtualToplevel|UART1|ALT_INV_Add9~27_combout\ <= NOT \myVirtualToplevel|UART1|Add9~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~72_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~72_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~83_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~83_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~71_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~71_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~70_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~70_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~61_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~61_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~60_combout\; +\myVirtualToplevel|ALT_INV_SD_OVERRUN~0_combout\ <= NOT \myVirtualToplevel|SD_OVERRUN~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA~8_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~8_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~24_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~24_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(23) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(23); +\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(7) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(7); +\myVirtualToplevel|UART1|ALT_INV_RX_DATA~8_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~8_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~24_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~24_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(23) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(23); +\myVirtualToplevel|UART1|ALT_INV_Add9~26_combout\ <= NOT \myVirtualToplevel|UART1|Add9~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector352~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~69_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~69_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~78_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~78_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~37_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~68_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~68_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~58_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~57_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0_combout\; +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(11) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(11); +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~59_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~58_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[27]~58_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~57_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[27]~57_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(27) <= NOT \myVirtualToplevel|IO_DATA_READ\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~67_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~67_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~66_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~66_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~65_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~65_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~64_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~63_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~55_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~54_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux95~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux95~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0_combout\; +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(10) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(10); +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~56_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~55_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[26]~55_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~54_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[26]~54_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(26) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(26); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(26) <= NOT \myVirtualToplevel|IO_DATA_READ\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~62_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~62_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~69_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~69_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~61_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~61_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~60_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~59_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~58_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~57_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~56_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~52_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~51_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~0_combout\; +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(9) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(9); +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~53_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~52_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[25]~52_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~51_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[25]~51_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(25) <= NOT \myVirtualToplevel|IO_DATA_READ\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~55_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~64_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~54_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~53_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~52_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~51_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~50_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~49_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~49_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~48_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA~6_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~6_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~23_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~23_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(22) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(22); +\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(6) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(6); +\myVirtualToplevel|UART1|ALT_INV_RX_DATA~6_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~6_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~23_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~23_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(22) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(22); +\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(6) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(6); +\myVirtualToplevel|UART1|ALT_INV_Add9~25_combout\ <= NOT \myVirtualToplevel|UART1|Add9~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector353~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~45_combout\; +\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~2_combout\ <= NOT \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\; +\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~0_combout\ <= NOT \myVirtualToplevel|RTC_DAY_COUNTER~0_combout\; +\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\; +\myVirtualToplevel|ALT_INV_process_1~5_combout\ <= NOT \myVirtualToplevel|process_1~5_combout\; +\myVirtualToplevel|ALT_INV_Add9~1_combout\ <= NOT \myVirtualToplevel|Add9~1_combout\; +\myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER~1_combout\ <= NOT \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\; +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\; +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\; +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\; +\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\; +\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~1_combout\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\; +\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~0_combout\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\; +\myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_HOUR_COUNTER\(1); +\myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_HOUR_COUNTER\(0); +\myVirtualToplevel|ALT_INV_process_1~4_combout\ <= NOT \myVirtualToplevel|process_1~4_combout\; +\myVirtualToplevel|ALT_INV_process_1~3_combout\ <= NOT \myVirtualToplevel|process_1~3_combout\; +\myVirtualToplevel|ALT_INV_process_1~2_combout\ <= NOT \myVirtualToplevel|process_1~2_combout\; +\myVirtualToplevel|ALT_INV_Add9~0_combout\ <= NOT \myVirtualToplevel|Add9~0_combout\; +\myVirtualToplevel|ALT_INV_process_1~1_combout\ <= NOT \myVirtualToplevel|process_1~1_combout\; +\myVirtualToplevel|ALT_INV_process_1~0_combout\ <= NOT \myVirtualToplevel|process_1~0_combout\; +\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_DAY_COUNTER\(1); +\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(5) <= NOT \myVirtualToplevel|RTC_DAY_COUNTER\(5); +\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_DAY_COUNTER\(0); +\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER\(1); +\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER\(0); +\myVirtualToplevel|ALT_INV_Add7~1_combout\ <= NOT \myVirtualToplevel|Add7~1_combout\; +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\; +\myVirtualToplevel|ALT_INV_Add7~0_combout\ <= NOT \myVirtualToplevel|Add7~0_combout\; +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER\(1); +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER\(0); +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\; +\myVirtualToplevel|ALT_INV_Add6~1_combout\ <= NOT \myVirtualToplevel|Add6~1_combout\; +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\; +\myVirtualToplevel|ALT_INV_Add6~0_combout\ <= NOT \myVirtualToplevel|Add6~0_combout\; +\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER\(1); +\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER\(0); +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\; +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~2_combout\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2_combout\; +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~1_combout\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1_combout\; +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER~0_combout\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\; +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\ <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\; +\myVirtualToplevel|ALT_INV_Equal13~1_combout\ <= NOT \myVirtualToplevel|Equal13~1_combout\; +\myVirtualToplevel|ALT_INV_Equal13~0_combout\ <= NOT \myVirtualToplevel|Equal13~0_combout\; +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~1_combout\ <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~1_combout\; +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~0_combout\ <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~0_combout\; +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER~0_combout\ <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\; +\myVirtualToplevel|ALT_INV_Equal35~7_combout\ <= NOT \myVirtualToplevel|Equal35~7_combout\; +\myVirtualToplevel|ALT_INV_Equal35~6_combout\ <= NOT \myVirtualToplevel|Equal35~6_combout\; +\myVirtualToplevel|ALT_INV_Equal35~5_combout\ <= NOT \myVirtualToplevel|Equal35~5_combout\; +\myVirtualToplevel|ALT_INV_Equal35~4_combout\ <= NOT \myVirtualToplevel|Equal35~4_combout\; +\myVirtualToplevel|ALT_INV_Equal35~3_combout\ <= NOT \myVirtualToplevel|Equal35~3_combout\; +\myVirtualToplevel|ALT_INV_Equal35~2_combout\ <= NOT \myVirtualToplevel|Equal35~2_combout\; +\myVirtualToplevel|ALT_INV_Equal35~1_combout\ <= NOT \myVirtualToplevel|Equal35~1_combout\; +\myVirtualToplevel|ALT_INV_Equal35~0_combout\ <= NOT \myVirtualToplevel|Equal35~0_combout\; +\myVirtualToplevel|ALT_INV_Equal36~1_combout\ <= NOT \myVirtualToplevel|Equal36~1_combout\; +\myVirtualToplevel|ALT_INV_Equal36~0_combout\ <= NOT \myVirtualToplevel|Equal36~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_INTR~4_combout\ <= NOT \myVirtualToplevel|UART0|RX_INTR~4_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_INTR~3_combout\ <= NOT \myVirtualToplevel|UART0|RX_INTR~3_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_INTR~2_combout\ <= NOT \myVirtualToplevel|UART0|RX_INTR~2_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_INTR~1_combout\ <= NOT \myVirtualToplevel|UART0|RX_INTR~1_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA~4_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~4_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA[7]~2_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~30_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~30_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~29_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~29_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~28_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~28_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(8) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(8); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(7) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(7); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(6) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(6); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(5) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(5); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~27_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~27_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(4) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(4); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(3) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(3); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(2) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(2); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(1) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(1); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(0) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(0); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(10) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(10); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(9) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(9); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~26_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~26_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(14) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(14); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(13) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(13); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(12) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(12); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(11) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(11); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(16) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(16); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(15) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(15); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~17_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~17_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~22_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~22_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(21) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(21); +\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(5) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(5); +\myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA[7]~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\ <= NOT \myVirtualToplevel|UART0|RX_INTR~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~q\ <= NOT \myVirtualToplevel|UART0|RX_CLOCK~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~q\ <= NOT \myVirtualToplevel|UART0|RX_STATE.stop~q\; +\myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\ <= NOT \myVirtualToplevel|UART0|RXD_SYNC~q\; +\myVirtualToplevel|UART0|ALT_INV_Equal2~4_combout\ <= NOT \myVirtualToplevel|UART0|Equal2~4_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal2~3_combout\ <= NOT \myVirtualToplevel|UART0|Equal2~3_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(5) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(5) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(2) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2); +\myVirtualToplevel|UART0|ALT_INV_Equal2~2_combout\ <= NOT \myVirtualToplevel|UART0|Equal2~2_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(7) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(6) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6); +\myVirtualToplevel|UART0|ALT_INV_Equal2~1_combout\ <= NOT \myVirtualToplevel|UART0|Equal2~1_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(3) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3); +\myVirtualToplevel|UART0|ALT_INV_Equal2~0_combout\ <= NOT \myVirtualToplevel|UART0|Equal2~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(0) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(0) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(0); +\myVirtualToplevel|UART1|ALT_INV_RX_INTR~4_combout\ <= NOT \myVirtualToplevel|UART1|RX_INTR~4_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_INTR~3_combout\ <= NOT \myVirtualToplevel|UART1|RX_INTR~3_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_INTR~2_combout\ <= NOT \myVirtualToplevel|UART1|RX_INTR~2_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_INTR~1_combout\ <= NOT \myVirtualToplevel|UART1|RX_INTR~1_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA~4_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~4_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~30_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~30_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~29_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~29_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~28_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~28_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(8) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(8); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(7) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(7); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(6) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(6); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(5) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(5); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~27_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~27_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(4) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(4); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(3) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(3); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(2) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(2); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(1) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(1); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(0) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(0); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(10) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(10); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(9) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(9); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~26_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~26_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(14) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(14); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(13) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(13); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(12) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(12); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(11) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(11); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(16) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(16); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(15) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(15); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~17_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~17_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~22_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~22_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(21) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(21); +\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(5) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(5); +\myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA[0]~1_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\ <= NOT \myVirtualToplevel|UART1|RX_INTR~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK~q\ <= NOT \myVirtualToplevel|UART1|RX_CLOCK~q\; +\myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~q\ <= NOT \myVirtualToplevel|UART1|RX_STATE.stop~q\; +\myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\ <= NOT \myVirtualToplevel|UART1|RXD_SYNC~q\; +\myVirtualToplevel|UART1|ALT_INV_Equal2~4_combout\ <= NOT \myVirtualToplevel|UART1|Equal2~4_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal2~3_combout\ <= NOT \myVirtualToplevel|UART1|Equal2~3_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(7) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(5) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(5) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5); +\myVirtualToplevel|UART1|ALT_INV_Equal2~2_combout\ <= NOT \myVirtualToplevel|UART1|Equal2~2_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(6) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(2) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2); +\myVirtualToplevel|UART1|ALT_INV_Equal2~1_combout\ <= NOT \myVirtualToplevel|UART1|Equal2~1_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(3) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3); +\myVirtualToplevel|UART1|ALT_INV_Equal2~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal2~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(0) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(0); +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(4) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4); +\myVirtualToplevel|UART1|ALT_INV_Add9~24_combout\ <= NOT \myVirtualToplevel|UART1|Add9~24_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(4) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4); +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(4) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4); +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(4) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector354~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector354~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~45_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~55_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~44_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~42_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~50_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~49_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[31]~49_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~48_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[31]~48_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(31) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(31); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(31) <= NOT \myVirtualToplevel|IO_DATA_READ\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~50_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~37_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~37_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~39_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~47_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[30]~47_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~46_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[30]~46_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~45_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[30]~45_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(30) <= NOT \myVirtualToplevel|IO_DATA_READ\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~37_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~36_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~44_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~43_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[29]~43_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~42_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[29]~42_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(29) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(29); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(29) <= NOT \myVirtualToplevel|IO_DATA_READ\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~35_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~41_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[28]~41_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~40_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[28]~40_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~39_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[28]~39_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(28) <= NOT \myVirtualToplevel|IO_DATA_READ\(28); +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_address_reg_b\(0) <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector15~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_Add10~43_combout\ <= NOT \myVirtualToplevel|UART1|Add10~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~27_combout\; +\myVirtualToplevel|UART1|ALT_INV_Add10~42_combout\ <= NOT \myVirtualToplevel|UART1|Add10~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~24_combout\; +\myVirtualToplevel|UART1|ALT_INV_Add10~41_combout\ <= NOT \myVirtualToplevel|UART1|Add10~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector11~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector11~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_Add10~40_combout\ <= NOT \myVirtualToplevel|UART1|Add10~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector14~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_Add10~39_combout\ <= NOT \myVirtualToplevel|UART1|Add10~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector12~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector12~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_Add10~38_combout\ <= NOT \myVirtualToplevel|UART1|Add10~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector13~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector13~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_Add10~37_combout\ <= NOT \myVirtualToplevel|UART1|Add10~37_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\ <= NOT \myVirtualToplevel|UART1|TX_STATE~q\; +\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK~q\ <= NOT \myVirtualToplevel|UART1|TX_CLOCK~q\; +\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(8) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~9_combout\; +\myVirtualToplevel|ALT_INV_Equal34~4_combout\ <= NOT \myVirtualToplevel|Equal34~4_combout\; +\myVirtualToplevel|ALT_INV_Equal34~3_combout\ <= NOT \myVirtualToplevel|Equal34~3_combout\; +\myVirtualToplevel|ALT_INV_Equal34~2_combout\ <= NOT \myVirtualToplevel|Equal34~2_combout\; +\myVirtualToplevel|ALT_INV_Equal34~1_combout\ <= NOT \myVirtualToplevel|Equal34~1_combout\; +\myVirtualToplevel|ALT_INV_Equal34~0_combout\ <= NOT \myVirtualToplevel|Equal34~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_OVERRUN~0_combout\ <= NOT \myVirtualToplevel|UART1|TX_OVERRUN~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_RESET~q\ <= NOT \myVirtualToplevel|UART1|TX_RESET~q\; +\myVirtualToplevel|UART1|ALT_INV_Add10~32_combout\ <= NOT \myVirtualToplevel|UART1|Add10~32_combout\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER~0_combout\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\; +\myVirtualToplevel|ALT_INV_Equal33~3_combout\ <= NOT \myVirtualToplevel|Equal33~3_combout\; +\myVirtualToplevel|ALT_INV_Equal33~2_combout\ <= NOT \myVirtualToplevel|Equal33~2_combout\; +\myVirtualToplevel|ALT_INV_Equal33~1_combout\ <= NOT \myVirtualToplevel|Equal33~1_combout\; +\myVirtualToplevel|ALT_INV_Equal33~0_combout\ <= NOT \myVirtualToplevel|Equal33~0_combout\; +\myVirtualToplevel|ALT_INV_Equal32~4_combout\ <= NOT \myVirtualToplevel|Equal32~4_combout\; +\myVirtualToplevel|ALT_INV_Equal32~3_combout\ <= NOT \myVirtualToplevel|Equal32~3_combout\; +\myVirtualToplevel|ALT_INV_Equal32~2_combout\ <= NOT \myVirtualToplevel|Equal32~2_combout\; +\myVirtualToplevel|ALT_INV_Equal32~1_combout\ <= NOT \myVirtualToplevel|Equal32~1_combout\; +\myVirtualToplevel|ALT_INV_Equal32~0_combout\ <= NOT \myVirtualToplevel|Equal32~0_combout\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\; +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~0_combout\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\; +\myVirtualToplevel|ALT_INV_Equal31~5_combout\ <= NOT \myVirtualToplevel|Equal31~5_combout\; +\myVirtualToplevel|ALT_INV_Equal31~4_combout\ <= NOT \myVirtualToplevel|Equal31~4_combout\; +\myVirtualToplevel|ALT_INV_Equal31~3_combout\ <= NOT \myVirtualToplevel|Equal31~3_combout\; +\myVirtualToplevel|ALT_INV_Equal31~2_combout\ <= NOT \myVirtualToplevel|Equal31~2_combout\; +\myVirtualToplevel|ALT_INV_Equal31~1_combout\ <= NOT \myVirtualToplevel|Equal31~1_combout\; +\myVirtualToplevel|ALT_INV_Equal31~0_combout\ <= NOT \myVirtualToplevel|Equal31~0_combout\; +\myVirtualToplevel|ALT_INV_Equal30~1_combout\ <= NOT \myVirtualToplevel|Equal30~1_combout\; +\myVirtualToplevel|ALT_INV_Equal30~0_combout\ <= NOT \myVirtualToplevel|Equal30~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_MemoryFetch~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_0~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_EndAddr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_EndAddr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_0~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr128~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr128~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal141~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr162~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr162~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~8_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal0~4_combout\ <= NOT \myVirtualToplevel|UART1|Equal0~4_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal0~3_combout\ <= NOT \myVirtualToplevel|UART1|Equal0~3_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal0~2_combout\ <= NOT \myVirtualToplevel|UART1|Equal0~2_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal0~1_combout\ <= NOT \myVirtualToplevel|UART1|Equal0~1_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal0~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(9) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~63_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~62_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~62_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~53_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~62_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~62_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~61_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~61_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~60_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~59_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~58_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~57_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~56_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~55_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~54_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~53_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~52_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~51_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~50_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~49_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~47_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~45_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~44_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~37_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~35_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1659~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1659~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~160_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugOutputOnce~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux254~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux254~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add59~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add61~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add61~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~60_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~59_combout\; +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(17) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_INT_DONE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|INT_DONE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_LatchAddrPause~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddrPause~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_LatchAddr~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector119~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector119~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux353~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux353~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux293~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux293~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux385~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux385~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux299~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux299~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux101~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux101~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux37~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux37~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux165~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux165~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux229~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux229~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux349~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux349~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux289~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux289~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux381~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux381~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux295~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux295~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux97~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux97~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux33~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux33~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux161~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux161~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux225~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux225~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector49~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector49~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux378~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux378~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux286~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux286~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux94~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux94~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux30~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux30~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux346~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux346~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~37_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector51~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector51~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux348~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux348~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux288~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux288~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux380~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux380~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux294~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux294~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux96~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux96~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux32~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux32~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux160~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux160~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux224~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux224~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~35_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector50~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector50~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux379~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux379~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux287~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux287~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux95~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux95~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux31~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux31~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux347~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux347~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~60_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~58_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~57_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux11~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux11~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux8~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux8~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux14~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector507~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector639~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector771~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector503~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector503~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector701~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector701~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector635~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector635~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector899~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector899~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector568~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector502~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1115~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1115~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1083~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1083~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector500~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector500~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1179~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1179~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector698~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector698~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1147~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1147~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector632~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector632~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1307~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1307~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector962~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector962~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1275~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1275~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector896~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector896~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector830~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector830~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector565~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector565~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[25]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(0); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]~25_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(2); +\myVirtualToplevel|ALT_INV_SD_ADDR[0][2]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][2]~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(2) <= NOT \myVirtualToplevel|UART0|RX_DATA\(2); +\myVirtualToplevel|ALT_INV_IO_DATA_READ~76_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~76_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(2) <= NOT \myVirtualToplevel|UART1|RX_DATA\(2); +\myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\ <= NOT \myVirtualToplevel|UART0|RX_DATA_READY~q\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~q\ <= NOT \myVirtualToplevel|UART1|RX_DATA_READY~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~75_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~75_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~74_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~74_combout\; +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER\(2); +\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER\(2); +\myVirtualToplevel|ALT_INV_IO_DATA_READ~73_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~73_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~72_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~72_combout\; +\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER\(2); +\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_DAY_COUNTER\(2); +\myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_HOUR_COUNTER\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~55_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~53_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~49_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]~24_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(3); +\myVirtualToplevel|ALT_INV_SD_ADDR[0][3]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][3]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~70_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[0]~70_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(3) <= NOT \myVirtualToplevel|UART0|RX_DATA\(3); +\myVirtualToplevel|ALT_INV_IO_DATA_READ~69_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~69_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_OVERRUN~q\ <= NOT \myVirtualToplevel|UART1|RX_OVERRUN~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_OVERRUN~q\ <= NOT \myVirtualToplevel|UART0|RX_OVERRUN~q\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(3) <= NOT \myVirtualToplevel|UART1|RX_DATA\(3); +\myVirtualToplevel|ALT_INV_IO_DATA_READ~68_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~68_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~67_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~67_combout\; +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER\(3); +\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER\(3); +\myVirtualToplevel|ALT_INV_IO_DATA_READ~66_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~66_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~65_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~65_combout\; +\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER\(3); +\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_DAY_COUNTER\(3); +\myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_HOUR_COUNTER\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[3]~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~50_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[3]~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~52_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[3]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~53_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[3]~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~56_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~54_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[3]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~53_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[3]~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~49_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[3]~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~52_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1080~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector17~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector17~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[8]~23_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]~23_combout\; +\myVirtualToplevel|ALT_INV_Mux75~0_combout\ <= NOT \myVirtualToplevel|Mux75~0_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][8]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][8]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[8]~64_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[8]~64_combout\; +\myVirtualToplevel|ALT_INV_Mux264~0_combout\ <= NOT \myVirtualToplevel|Mux264~0_combout\; +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(8) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(8); +\myVirtualToplevel|ALT_INV_INT_ENABLE\(8) <= NOT \myVirtualToplevel|INT_ENABLE\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~49_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~51_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~52_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~55_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~52_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~51_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(8); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]~22_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(7) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(7); +\myVirtualToplevel|ALT_INV_SD_ADDR[0][7]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][7]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~62_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~62_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~61_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~61_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~60_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~60_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~59_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~59_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~58_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~58_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~57_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~57_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_RESET~q\ <= NOT \myVirtualToplevel|UART0|RX_RESET~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(7) <= NOT \myVirtualToplevel|UART0|RX_DATA\(7); +\myVirtualToplevel|ALT_INV_IO_DATA_READ~56_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~56_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_RESET~q\ <= NOT \myVirtualToplevel|UART1|RX_RESET~q\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(7) <= NOT \myVirtualToplevel|UART1|RX_DATA\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[7]~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[7]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[7]~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~49_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[7]~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~52_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[7]~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~50_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[7]~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~49_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[7]~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~45_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[7]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1076~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(7); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]~21_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\; +\myVirtualToplevel|ALT_INV_SD_OVERRUN~q\ <= NOT \myVirtualToplevel|SD_OVERRUN~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(6); +\myVirtualToplevel|ALT_INV_SD_ADDR[0][6]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][6]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~54_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~54_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~53_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~53_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~52_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~52_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~51_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~51_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~50_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~50_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[5]~49_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[5]~49_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~48_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~48_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\ <= NOT \myVirtualToplevel|UART0|RX_ENABLE~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(6) <= NOT \myVirtualToplevel|UART0|RX_DATA\(6); +\myVirtualToplevel|ALT_INV_IO_DATA_READ~47_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~47_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\ <= NOT \myVirtualToplevel|UART1|RX_ENABLE~q\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(6) <= NOT \myVirtualToplevel|UART1|RX_DATA\(6); +\myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~46_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[0]~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[6]~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~44_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[6]~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[6]~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~47_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[6]~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~50_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[6]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[6]~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~47_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[6]~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[6]~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1077~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(6); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[11]~20_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]~20_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][11]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][11]~q\; +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(11) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(11); +\myVirtualToplevel|ALT_INV_INT_ENABLE\(11) <= NOT \myVirtualToplevel|INT_ENABLE\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[11]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~44_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[11]~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~45_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[11]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[11]~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[11]~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~45_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[11]~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[11]~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~44_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1072~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(11); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[10]~19_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]~19_combout\; +\myVirtualToplevel|ALT_INV_Mux73~0_combout\ <= NOT \myVirtualToplevel|Mux73~0_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][10]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][10]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~43_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~43_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[11]~42_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[11]~42_combout\; +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(10) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(10); +\myVirtualToplevel|ALT_INV_INT_ENABLE\(10) <= NOT \myVirtualToplevel|INT_ENABLE\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[10]~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[10]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[10]~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[10]~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[10]~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[10]~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[10]~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[10]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(10); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[9]~18_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]~18_combout\; +\myVirtualToplevel|ALT_INV_Mux74~0_combout\ <= NOT \myVirtualToplevel|Mux74~0_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][9]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][9]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[9]~40_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[9]~40_combout\; +\myVirtualToplevel|ALT_INV_Mux263~0_combout\ <= NOT \myVirtualToplevel|Mux263~0_combout\; +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(9) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(9); +\myVirtualToplevel|ALT_INV_INT_ENABLE\(9) <= NOT \myVirtualToplevel|INT_ENABLE\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(9); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]~17_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(5); +\myVirtualToplevel|ALT_INV_SD_ADDR[0][5]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][5]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[5]~38_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[5]~38_combout\; +\myVirtualToplevel|ALT_INV_Mux267~1_combout\ <= NOT \myVirtualToplevel|Mux267~1_combout\; +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(5) <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER\(5); +\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(5) <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER\(5); +\myVirtualToplevel|ALT_INV_Mux267~0_combout\ <= NOT \myVirtualToplevel|Mux267~0_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~37_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~37_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~q\ <= NOT \myVirtualToplevel|UART0|RX_ENABLE_FIFO~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(5) <= NOT \myVirtualToplevel|UART0|RX_DATA\(5); +\myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\ <= NOT \myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(5) <= NOT \myVirtualToplevel|UART1|RX_DATA\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[5]~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[5]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[5]~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[5]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[5]~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[5]~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[5]~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[5]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(5); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]~16_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16_combout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM0_WREN~0_combout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(4); +\myVirtualToplevel|ALT_INV_SD_ADDR[0][4]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][4]~q\; +\myVirtualToplevel|ALT_INV_Mux92~0_combout\ <= NOT \myVirtualToplevel|Mux92~0_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[4]~35_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[4]~35_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[4]~34_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[4]~34_combout\; +\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_DAY_COUNTER\(4); +\myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_HOUR_COUNTER\(4); +\myVirtualToplevel|ALT_INV_Mux268~1_combout\ <= NOT \myVirtualToplevel|Mux268~1_combout\; +\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER\(4); +\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER\(4); +\myVirtualToplevel|ALT_INV_Mux268~0_combout\ <= NOT \myVirtualToplevel|Mux268~0_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~33_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~33_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_INTR~q\ <= NOT \myVirtualToplevel|UART0|RX_INTR~q\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(4) <= NOT \myVirtualToplevel|UART0|RX_DATA\(4); +\myVirtualToplevel|UART1|ALT_INV_RX_INTR~q\ <= NOT \myVirtualToplevel|UART1|RX_INTR~q\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(4) <= NOT \myVirtualToplevel|UART1|RX_DATA\(4); +\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(4) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(4); +\myVirtualToplevel|ALT_INV_INT_ENABLE\(4) <= NOT \myVirtualToplevel|INT_ENABLE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[4]~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[4]~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[4]~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[4]~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[4]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[4]~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[4]~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[4]~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(4); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[15]~15_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]~15_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][15]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][15]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~31_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[15]~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[15]~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~35_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[15]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[15]~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[15]~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~35_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[15]~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[15]~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1068~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(15); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[14]~14_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]~14_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][14]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][14]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[14]~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[14]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[14]~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[14]~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[14]~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[14]~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[14]~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(14); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[13]~13_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]~13_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][13]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][13]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~29_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~29_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~28_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[13]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[13]~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[13]~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[13]~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[13]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[13]~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[13]~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[13]~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1070~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(13); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[12]~12_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]~12_combout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM1_WREN~0_combout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~0_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][12]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][12]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[12]~26_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[12]~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[12]~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[12]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[12]~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[12]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[12]~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[12]~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[12]~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[12]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(12); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[19]~11_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11_combout\; +\myVirtualToplevel|ALT_INV_Mux86~0_combout\ <= NOT \myVirtualToplevel|Mux86~0_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][19]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][19]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~24_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~24_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~23_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~23_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_DATA_LOADED~q\ <= NOT \myVirtualToplevel|UART1|TX_DATA_LOADED~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[19]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[19]~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[19]~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[19]~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[19]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[19]~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[19]~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[19]~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1064~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[18]~10_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][18]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][18]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~21_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~21_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~20_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~20_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_BUSY~q\ <= NOT \myVirtualToplevel|UART0|TX_BUSY~q\; +\myVirtualToplevel|UART1|ALT_INV_TX_BUSY~q\ <= NOT \myVirtualToplevel|UART1|TX_BUSY~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[18]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[18]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[18]~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[18]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[18]~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[18]~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[18]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[18]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1065~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18); +\myVirtualToplevel|ALT_INV_SD_ADDR[0][17]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][17]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~19_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~19_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal6~4_combout\ <= NOT \myVirtualToplevel|UART1|Equal6~4_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal6~3_combout\ <= NOT \myVirtualToplevel|UART1|Equal6~3_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal6~2_combout\ <= NOT \myVirtualToplevel|UART1|Equal6~2_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal6~1_combout\ <= NOT \myVirtualToplevel|UART1|Equal6~1_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal6~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal6~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[17]~9_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[17]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[17]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[17]~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[17]~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~26_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[17]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[17]~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[17]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[17]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1066~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[23]~8_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][23]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][23]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~17_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~17_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\ <= NOT \myVirtualToplevel|UART1|TX_ENABLE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[23]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[23]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[23]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[23]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[23]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[23]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[23]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1060~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[20]~7_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]~7_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][20]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][20]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~14_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~14_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~q\ <= NOT \myVirtualToplevel|UART0|TX_OVERRUN~q\; +\myVirtualToplevel|UART1|ALT_INV_TX_OVERRUN~q\ <= NOT \myVirtualToplevel|UART1|TX_OVERRUN~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[20]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[20]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[20]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[20]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[20]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[20]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[20]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[20]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1063~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(20); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[22]~6_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][22]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][22]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~11_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~11_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_ENABLE_FIFO~q\ <= NOT \myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[22]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[22]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[22]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[22]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[22]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[22]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1061~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[21]~5_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5_combout\; +\myVirtualToplevel|ALT_INV_SD_ADDR[0][21]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][21]~q\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~7_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~7_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~6_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[21]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[21]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[21]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[21]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[21]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[21]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[21]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[21]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1062~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[16]~4_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4_combout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\; +\myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\ <= NOT \myVirtualToplevel|BRAM_WREN~1_combout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM2_WREN~0_combout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\; +\myVirtualToplevel|ALT_INV_LessThan3~0_combout\ <= NOT \myVirtualToplevel|LessThan3~0_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~0_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~3_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]~3_combout\; +\myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\ <= NOT \myVirtualToplevel|TIMER0_CS~2_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~2_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]~2_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~1_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]~1_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~0_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal5~4_combout\ <= NOT \myVirtualToplevel|UART1|Equal5~4_combout\; +\myVirtualToplevel|UART1|ALT_INV_Equal5~3_combout\ <= NOT \myVirtualToplevel|UART1|Equal5~3_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(4) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4); +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(4) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4); +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(2) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2); +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(2) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2); +\myVirtualToplevel|UART1|ALT_INV_Equal5~2_combout\ <= NOT \myVirtualToplevel|UART1|Equal5~2_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(5) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5); +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(5) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5); +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(3) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3); +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(3) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3); +\myVirtualToplevel|UART1|ALT_INV_Equal5~1_combout\ <= NOT \myVirtualToplevel|UART1|Equal5~1_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(7) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(7); +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(7) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(7); +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(6) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6); +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(6) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6); +\myVirtualToplevel|UART1|ALT_INV_Equal5~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal5~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(1) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1); +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(1) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1); +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(0) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0); +\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(0) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal153~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal153~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugAllInfo~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~35_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_End~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_StartAddr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[16]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[16]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[16]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[16]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[16]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[16]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[16]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1067~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(1); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~14_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~14_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(9) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(9); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(8) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(8); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(7) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(7); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(7) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(7); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(6) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(6); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(6) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(6); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(5) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(5); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(5) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(5); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(4); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(4); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(3); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(3); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(2); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(2); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(1); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(1); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~3_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(3); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(4); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~2_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(2); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(0); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(1); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(6) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(6); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(7) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(7); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(5) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(2); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(0); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(1); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\; +\myVirtualToplevel|ALT_INV_SD_WR\(0) <= NOT \myVirtualToplevel|SD_WR\(0); +\myVirtualToplevel|ALT_INV_SD_RD\(0) <= NOT \myVirtualToplevel|SD_RD\(0); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\; +\myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0) <= NOT \myVirtualToplevel|SD_HNDSHK_IN\(0); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(4); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(2); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(0); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(6); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(5); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(3); +\myVirtualToplevel|ALT_INV_SD_RESET\(0) <= NOT \myVirtualToplevel|SD_RESET\(0); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(7) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(47) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(47); +\myVirtualToplevel|UART0|ALT_INV_TX_RESET~q\ <= NOT \myVirtualToplevel|UART0|TX_RESET~q\; +\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK~q\ <= NOT \myVirtualToplevel|UART0|TX_CLOCK~q\; +\myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\ <= NOT \myVirtualToplevel|UART0|TX_STATE~q\; +\myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\ <= NOT \myVirtualToplevel|UART0|TX_ENABLE~q\; +\myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\ <= NOT \myVirtualToplevel|UART0|TX_DATA_LOADED~q\; +\myVirtualToplevel|ALT_INV_RESET_n~q\ <= NOT \myVirtualToplevel|RESET_n~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_CLOCK~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_DATA_LOADED~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQM\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM\(1); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQM\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM\(0); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR\(10) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(10); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_cs_bo~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|cs_bo~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~q\; +\myVirtualToplevel|UART0|ALT_INV_TXD~q\ <= NOT \myVirtualToplevel|UART0|TXD~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TXD~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux28~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux28~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~48_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~48_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~147_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~143_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~139_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~135_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~119_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~115_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~103_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~65_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~65_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~116_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~116_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~108_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~108_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ~104_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~104_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~116_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~116_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~112_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~112_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~108_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~108_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~104_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~104_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~165_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~165_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~72_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~72_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~15_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[44]~44_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~44_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~161_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~161_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1464~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1463~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1416~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1417~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1421~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1425~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1432~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1427~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(8) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(8); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(10) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(10); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(12) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(12); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(14) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(37) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(10); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(39) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50); +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(7) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(7); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(7) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(7); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(0) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(0); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(14) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(14); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(15) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(15); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(1) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(1); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(2) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(2); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(5) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(5); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(9) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(9); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(3) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(3); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(4) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(4); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(6) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(6); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(8) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(8); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(10) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(10); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(11) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(11); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(12) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(12); +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(13) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a7\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\; +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(6) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~735_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~735_sumout\; +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a1\; +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a2\; +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a3\; +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a4\; +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a5\; +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a6\; +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a7\; +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\; +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a1\; +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a2\; +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a3\; +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a4\; +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a5\; +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a6\; +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a7\; +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~731_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~731_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~727_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~727_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~723_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~723_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~719_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~719_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~715_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~715_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~711_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~711_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~61_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~61_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~57_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~57_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~49_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~49_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~45_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~45_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~41_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~41_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~37_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~37_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~33_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~33_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~29_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~29_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~25_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~25_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~21_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~21_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~17_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~17_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~13_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~13_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~9_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~9_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~5_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~5_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add1~1_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~1_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~61_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~61_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~57_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~57_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~49_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~49_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~45_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~45_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~41_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~41_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~37_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~37_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~33_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~33_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~29_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~29_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~25_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~25_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~21_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~21_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~17_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~17_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~13_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~13_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~9_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~9_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~5_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~5_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add1~1_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~1_sumout\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][20]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][19]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][18]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][8]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][14]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][13]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][2]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][1]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][7]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][6]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][0]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][12]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][5]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][4]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][3]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][17]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][22]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][22]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][24]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][24]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][25]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][25]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][26]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][26]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][16]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][15]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][27]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][27]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][11]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][23]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][23]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][21]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][29]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][29]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][28]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][28]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][10]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][9]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][31]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~q\; +\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][30]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][30]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~707_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~707_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM195\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM195\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM197\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM197\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM199\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM199\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM201\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM201\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM203\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM203\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM205\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM205\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM207\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM207\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM209\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM209\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM211\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM211\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM213\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM213\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM215\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM215\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM217\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM217\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM219\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM219\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM221\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM221\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~125_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~125_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~121_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~121_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~117_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~117_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~113_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~113_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~109_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~109_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~105_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~105_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~101_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~101_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux3~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux5~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux21~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux20~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux23~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux22~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux29~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux28~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux26~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux27~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux25~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux24~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux4~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(5) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(5); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(1) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~93_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~136_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~136_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~125_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~125_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~125_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~125_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~121_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~121_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~132_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~132_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(0) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(0); +\myVirtualToplevel|UART1|ALT_INV_Add9~36_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~36_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~117_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~117_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~128_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~128_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~117_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~117_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~113_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~113_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~113_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~113_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~124_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~124_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(24) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~120_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~120_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~109_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~109_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~109_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~109_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~105_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~105_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~105_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~105_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~116_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~116_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(27) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~65_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(26) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~61_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(25) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~101_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~101_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~101_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~101_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~112_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~112_sumout\; +\myVirtualToplevel|ALT_INV_Add11~45_sumout\ <= NOT \myVirtualToplevel|Add11~45_sumout\; +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(14) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(14); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(13) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(13); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(0) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(0); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(12) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(12); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(11) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(11); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(6) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(6); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(5) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(5); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(4) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(4); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(3) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(3); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(2) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(2); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(1) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(1); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(10) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(10); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(9) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(9); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(8) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(8); +\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(7) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(7); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(14) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(14); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(13) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(13); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(0) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(0); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(12) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(12); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(11) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(11); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(6) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(6); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(5) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(5); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(4) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(4); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(3) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(3); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(2) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(2); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(1) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(1); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(10) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(10); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(9) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(9); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(8) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(8); +\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(7) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~108_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~108_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~97_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~97_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~97_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~97_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(31) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~45_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(30) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~41_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(29) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~37_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(28) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~362_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~362_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~354_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~354_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~350_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~350_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~346_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~346_sumout\; +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(0) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(0); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(8) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(8); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(2) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(2); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(1) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(1); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(15) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(15); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(14) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(14); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(3) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(3); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(4) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(4); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(5) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(5); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(9) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(9); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(7) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(7); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(6) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(6); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(10) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(10); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(11) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(11); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(12) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(12); +\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(13) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~342_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~342_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(33); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(34); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(35); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(32); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(43); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(36); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(37); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(38); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(39); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(41); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(42); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(57); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(58); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(59); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM167\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM167\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM169\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM169\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM171\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM171\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM173\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM173\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM175\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM175\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM177\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM177\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM179\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM179\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM181\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM181\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM183\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM183\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM185\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM185\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM187\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM187\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM189\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM189\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM191\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM191\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM193\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM193\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux179~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a5\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(40); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(44); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(47); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(51); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(49); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(50); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux3~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux5~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux21~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux20~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux23~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux22~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux29~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux28~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux26~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux27~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux25~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux24~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux4~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(0); +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(4) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(25); +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(1) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~103_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~103_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~93_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~93_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~98_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~98_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(30); +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(0) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(0); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(0) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(0); +\myVirtualToplevel|UART1|ALT_INV_Add9~31_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~31_sumout\; +\myVirtualToplevel|ALT_INV_Add11~37_sumout\ <= NOT \myVirtualToplevel|Add11~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~94_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~94_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~85_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add2~29_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~29_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add2~25_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~25_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add2~17_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~17_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add2~13_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~13_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add2~9_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~9_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add2~5_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~5_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add2~1_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~1_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add2~29_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~29_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add2~25_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~25_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add2~17_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~17_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add2~13_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~13_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add2~9_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~9_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add2~5_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~5_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add2~1_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~1_sumout\; +\myVirtualToplevel|ALT_INV_Add11~33_sumout\ <= NOT \myVirtualToplevel|Add11~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~89_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(8); +\myVirtualToplevel|ALT_INV_Add11~29_sumout\ <= NOT \myVirtualToplevel|Add11~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~77_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(24) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~77_sumout\; +\myVirtualToplevel|ALT_INV_Add11~25_sumout\ <= NOT \myVirtualToplevel|Add11~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~80_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~80_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~73_sumout\; +\myVirtualToplevel|ALT_INV_Add11~21_sumout\ <= NOT \myVirtualToplevel|Add11~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~75_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~75_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(11); +\myVirtualToplevel|ALT_INV_Add11~17_sumout\ <= NOT \myVirtualToplevel|Add11~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~65_sumout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(27) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(27); +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~71_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~71_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10); +\myVirtualToplevel|ALT_INV_Add11~13_sumout\ <= NOT \myVirtualToplevel|Add11~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~61_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(26) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~66_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~66_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(9); +\myVirtualToplevel|ALT_INV_Add11~9_sumout\ <= NOT \myVirtualToplevel|Add11~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~57_sumout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(25) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(25); +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~57_sumout\; +\myVirtualToplevel|ALT_INV_Add11~5_sumout\ <= NOT \myVirtualToplevel|Add11~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~53_sumout\; +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(1); +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(0); +\myVirtualToplevel|ALT_INV_Add11~1_sumout\ <= NOT \myVirtualToplevel|Add11~1_sumout\; +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(1); +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(6) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(6); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(5) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(5); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(2) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(2); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(0) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(0); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(7) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(7); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(4) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(4); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(3) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(3); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(1) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(1); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(1); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(0); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(6) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(6); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(7) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(7); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(25) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(25); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(27) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(27); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(0) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(0); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(1) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(1); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(2) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(2); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(3) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(3); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(4) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(4); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(5) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(5); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(8) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(8); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(9) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(9); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(22) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(22); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(23) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(23); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(24) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(24); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(26) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(26); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(12) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(12); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(13) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(13); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(14) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(14); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(15) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(15); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(16) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(16); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(18) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(18); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(20) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(20); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(21) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(21); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(10) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(10); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(11) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(11); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(17) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(17); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(19) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(19); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(1) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(1); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(0) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(0); +\myVirtualToplevel|UART0|ALT_INV_Add5~21_sumout\ <= NOT \myVirtualToplevel|UART0|Add5~21_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add5~17_sumout\ <= NOT \myVirtualToplevel|UART0|Add5~17_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add5~13_sumout\ <= NOT \myVirtualToplevel|UART0|Add5~13_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add5~9_sumout\ <= NOT \myVirtualToplevel|UART0|Add5~9_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add5~5_sumout\ <= NOT \myVirtualToplevel|UART0|Add5~5_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add5~1_sumout\ <= NOT \myVirtualToplevel|UART0|Add5~1_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add5~21_sumout\ <= NOT \myVirtualToplevel|UART1|Add5~21_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add5~17_sumout\ <= NOT \myVirtualToplevel|UART1|Add5~17_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add5~13_sumout\ <= NOT \myVirtualToplevel|UART1|Add5~13_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add5~9_sumout\ <= NOT \myVirtualToplevel|UART1|Add5~9_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add5~5_sumout\ <= NOT \myVirtualToplevel|UART1|Add5~5_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add5~1_sumout\ <= NOT \myVirtualToplevel|UART1|Add5~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~52_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~52_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector245~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector245~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS_2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector114~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector121~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector121~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(56); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(60); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan3~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan3~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(61); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTCRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_PRECR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_WideOr18~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18~combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector216~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~2_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~1_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux93~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux93~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~6_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~53_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~48_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~47_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~45_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr34~combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector63~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0_combout\; +\myVirtualToplevel|ALT_INV_SD_DATA_WRITE[7]~1_combout\ <= NOT \myVirtualToplevel|SD_DATA_WRITE[7]~1_combout\; +\myVirtualToplevel|ALT_INV_SD_DATA_VALID~0_combout\ <= NOT \myVirtualToplevel|SD_DATA_VALID~0_combout\; +\myVirtualToplevel|ALT_INV_Selector17~0_combout\ <= NOT \myVirtualToplevel|Selector17~0_combout\; +\myVirtualToplevel|ALT_INV_Selector11~1_combout\ <= NOT \myVirtualToplevel|Selector11~1_combout\; +\myVirtualToplevel|ALT_INV_Selector11~0_combout\ <= NOT \myVirtualToplevel|Selector11~0_combout\; +\myVirtualToplevel|ALT_INV_Selector12~0_combout\ <= NOT \myVirtualToplevel|Selector12~0_combout\; +\myVirtualToplevel|ALT_INV_Selector15~7_combout\ <= NOT \myVirtualToplevel|Selector15~7_combout\; +\myVirtualToplevel|ALT_INV_Selector15~6_combout\ <= NOT \myVirtualToplevel|Selector15~6_combout\; +\myVirtualToplevel|ALT_INV_Selector15~5_combout\ <= NOT \myVirtualToplevel|Selector15~5_combout\; +\myVirtualToplevel|ALT_INV_Selector15~4_combout\ <= NOT \myVirtualToplevel|Selector15~4_combout\; +\myVirtualToplevel|ALT_INV_Selector15~3_combout\ <= NOT \myVirtualToplevel|Selector15~3_combout\; +\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_1~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\; +\myVirtualToplevel|ALT_INV_Selector15~2_combout\ <= NOT \myVirtualToplevel|Selector15~2_combout\; +\myVirtualToplevel|ALT_INV_Selector15~1_combout\ <= NOT \myVirtualToplevel|Selector15~1_combout\; +\myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\ <= NOT \myVirtualToplevel|UART1|Mux0~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_ACMD41_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_CMD0_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~85_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr40~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[46]~6_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~6_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(45) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(45); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~5_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\; +\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(6) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(6); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_BLK~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector16~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector16~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~4_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA[0]~4_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_DATA~3_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~3_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~2_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA[0]~2_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~1_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA[0]~1_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~30_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~30_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~29_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~29_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~28_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~28_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(8) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(8); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(7) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(7); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(6) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(6); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(5) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(5); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~27_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~27_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(4) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(4); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(3) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(3); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(2) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(2); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(1) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(1); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(0) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(0); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(10) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(10); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(9) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(9); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~26_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~26_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(14) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(14); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(13) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(13); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(12) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(12); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(11) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(11); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(16) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(16); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(15) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(15); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~17_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~17_q\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~18_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~18_q\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(17) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(17); +\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(1) <= NOT \myVirtualToplevel|UART0|TX_DATA\(1); +\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(5) <= NOT \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(5); +\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(4) <= NOT \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(4); +\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(0) <= NOT \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(0); +\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(3) <= NOT \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(3); +\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(2) <= NOT \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(2); +\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(10) <= NOT \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(10); +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(9) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector18~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector18~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~0_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~37_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~36_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~36_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~35_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~34_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(2) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(2); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(2) <= NOT \myVirtualToplevel|IO_DATA_READ\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(3) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(3); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(3) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(3); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(3) <= NOT \myVirtualToplevel|IO_DATA_READ\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(3); +\myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~1_combout\ <= NOT \myVirtualToplevel|UART0|TX_OVERRUN~1_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~0_combout\ <= NOT \myVirtualToplevel|UART0|TX_OVERRUN~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal6~2_combout\ <= NOT \myVirtualToplevel|UART0|Equal6~2_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal6~1_combout\ <= NOT \myVirtualToplevel|UART0|Equal6~1_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal6~0_combout\ <= NOT \myVirtualToplevel|UART0|Equal6~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR[0]~0_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(8) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(8); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(8) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(8); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(8) <= NOT \myVirtualToplevel|IO_DATA_READ\(8); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(8) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~0_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(7) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(7); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(7) <= NOT \myVirtualToplevel|IO_DATA_READ\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(7); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(6) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(6); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(6) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(6); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(6) <= NOT \myVirtualToplevel|IO_DATA_READ\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(6); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(11) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(11); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(11) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(11); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(11) <= NOT \myVirtualToplevel|IO_DATA_READ\(11); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(11) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(11); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(10) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(10); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(10) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(10); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(10) <= NOT \myVirtualToplevel|IO_DATA_READ\(10); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(10) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(10); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(9) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(9); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(9) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(9); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(9) <= NOT \myVirtualToplevel|IO_DATA_READ\(9); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(9) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(5) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(5); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(5) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(5); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(5) <= NOT \myVirtualToplevel|IO_DATA_READ\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(5); +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b\(0) <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(4) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(4); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(4) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(4); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(4) <= NOT \myVirtualToplevel|IO_DATA_READ\(4); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(4) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(4); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(15) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(15); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(15) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(15); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(15) <= NOT \myVirtualToplevel|IO_DATA_READ\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(15); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(14) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(14); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(14) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(14); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(14) <= NOT \myVirtualToplevel|IO_DATA_READ\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(14); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(13) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(13); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(13) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(13); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(13) <= NOT \myVirtualToplevel|IO_DATA_READ\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector203~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(13); +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b\(0) <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b\(0); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(12) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(12); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(12) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(12); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(12) <= NOT \myVirtualToplevel|IO_DATA_READ\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector204~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12); +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~33_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~32_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[19]~32_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~31_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[19]~31_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(19) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(19); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(19) <= NOT \myVirtualToplevel|IO_DATA_READ\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(19); +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~30_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~29_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[18]~29_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~28_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[18]~28_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(18) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(18); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(18) <= NOT \myVirtualToplevel|IO_DATA_READ\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector198~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(18); +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~27_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[17]~27_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~26_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[17]~26_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~25_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[17]~25_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~24_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[17]~24_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~23_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[17]~23_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~22_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~21_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[27]~21_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~20_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[30]~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector199~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(17); +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~19_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~18_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[23]~18_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~17_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[23]~17_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(23) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector193~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(23); +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~16_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~15_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[20]~15_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~14_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[20]~14_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(20) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(20); +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~13_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~12_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[22]~12_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~11_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[22]~11_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(22) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(22); +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~10_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~9_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[21]~9_combout\; +\myVirtualToplevel|ALT_INV_LessThan0~1_combout\ <= NOT \myVirtualToplevel|LessThan0~1_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~8_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[21]~8_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[18]~7_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(21) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(21); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(21) <= NOT \myVirtualToplevel|IO_DATA_READ\(21); +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector195~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr116~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~3_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[10]~1_combout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|ALT_INV_l1_w0_n0_mux_dataout~0_combout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|l1_w0_n0_mux_dataout~0_combout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0) <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0); +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~0_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[16]~0_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(16) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(16); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(16) <= NOT \myVirtualToplevel|IO_DATA_READ\(16); +\myVirtualToplevel|ALT_INV_INTR0_CS~combout\ <= NOT \myVirtualToplevel|INTR0_CS~combout\; +\myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\ <= NOT \myVirtualToplevel|INTR0_CS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr195~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr2~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~0_combout\; +\myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\ <= NOT \myVirtualToplevel|MEM_BUSY~1_combout\; +\myVirtualToplevel|ALT_INV_MEM_READ_ENABLE_LAST~q\ <= NOT \myVirtualToplevel|MEM_READ_ENABLE_LAST~q\; +\myVirtualToplevel|ALT_INV_SD_CS~combout\ <= NOT \myVirtualToplevel|SD_CS~combout\; +\myVirtualToplevel|ALT_INV_SD_CS~0_combout\ <= NOT \myVirtualToplevel|SD_CS~0_combout\; +\myVirtualToplevel|ALT_INV_UART1_CS~combout\ <= NOT \myVirtualToplevel|UART1_CS~combout\; +\myVirtualToplevel|ALT_INV_Equal4~0_combout\ <= NOT \myVirtualToplevel|Equal4~0_combout\; +\myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\ <= NOT \myVirtualToplevel|TIMER0_CS~1_combout\; +\myVirtualToplevel|ALT_INV_TIMER0_CS~0_combout\ <= NOT \myVirtualToplevel|TIMER0_CS~0_combout\; +\myVirtualToplevel|ALT_INV_IO_SELECT~combout\ <= NOT \myVirtualToplevel|IO_SELECT~combout\; +\myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\ <= NOT \myVirtualToplevel|SOCCFG_CS~combout\; +\myVirtualToplevel|ALT_INV_SOCCFG_CS~0_combout\ <= NOT \myVirtualToplevel|SOCCFG_CS~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~20_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER[2]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[11]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~2_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDoneLast~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDoneLast~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][11]~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][11]~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn[21]~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~3_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~0_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~0_q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~14_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~14_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~12_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add3~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~1_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~10_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~10_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~9_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~9_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add3~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~0_combout\; +\myVirtualToplevel|ALT_INV_LessThan0~0_combout\ <= NOT \myVirtualToplevel|LessThan0~0_combout\; +\myVirtualToplevel|ALT_INV_BRAM_WREN~0_combout\ <= NOT \myVirtualToplevel|BRAM_WREN~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuLastEN~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuLastEN~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~7_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~7_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~6_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~6_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~5_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~3_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~1_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~1_combout\; +\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\; +\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_READ~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~81_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~80_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~78_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~77_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~76_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD0~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~75_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal2~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD41~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~72_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD55~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~70_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WAIT_FOR_HOST_RW~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.GET_CMD8_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~67_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~66_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_WAIT~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_STD_MATCH~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o~3_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~64_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~63_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~62_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~62_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~59_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~58_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[4]~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(7) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal4~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.RD_BLK~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o[3]~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~54_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~54_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~52_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.START_INIT~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~51_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~49_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~48_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnData_v~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\; +\myVirtualToplevel|ALT_INV_Selector15~0_combout\ <= NOT \myVirtualToplevel|Selector15~0_combout\; +\myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\ <= NOT \myVirtualToplevel|SD_DATA_REQ~q\; +\myVirtualToplevel|ALT_INV_Selector20~0_combout\ <= NOT \myVirtualToplevel|Selector20~0_combout\; +\myVirtualToplevel|ALT_INV_SD_DATA_VALID~q\ <= NOT \myVirtualToplevel|SD_DATA_VALID~q\; +\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_READ_2~q\; +\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\; +\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(2); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector21~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\; +\myVirtualToplevel|ALT_INV_Equal8~1_combout\ <= NOT \myVirtualToplevel|Equal8~1_combout\; +\myVirtualToplevel|ALT_INV_Equal8~0_combout\ <= NOT \myVirtualToplevel|Equal8~0_combout\; +\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(1) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(1); +\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(3) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(3); +\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\; +\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_IDLE~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\; +\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\; +\myVirtualToplevel|ALT_INV_SD_CHANNEL~q\ <= NOT \myVirtualToplevel|SD_CHANNEL~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~44_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~4_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~3_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector87~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector66~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector67~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~4_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~7_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector69~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~5_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~4_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~3_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~47_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr13~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~43_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~42_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_doDeselect_v~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~41_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~40_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~40_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~3_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~3_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(46) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(46); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_process_0~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\; +\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(7) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(7); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~1_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~0_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA[0]~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(0) <= NOT \myVirtualToplevel|UART0|TX_DATA\(0); +\myVirtualToplevel|UART0|ALT_INV_Equal0~4_combout\ <= NOT \myVirtualToplevel|UART0|Equal0~4_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal0~3_combout\ <= NOT \myVirtualToplevel|UART0|Equal0~3_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal0~2_combout\ <= NOT \myVirtualToplevel|UART0|Equal0~2_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal0~1_combout\ <= NOT \myVirtualToplevel|UART0|Equal0~1_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|UART0|Equal0~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(8) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(8); +\myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal7~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal5~3_combout\ <= NOT \myVirtualToplevel|UART0|Equal5~3_combout\; +\myVirtualToplevel|UART0|ALT_INV_Equal5~2_combout\ <= NOT \myVirtualToplevel|UART0|Equal5~2_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(5) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(5); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(5) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(4) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(4) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(3) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(3) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3); +\myVirtualToplevel|UART0|ALT_INV_Equal5~1_combout\ <= NOT \myVirtualToplevel|UART0|Equal5~1_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(2) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(2); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(2) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(1) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(1) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(0) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(0) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0); +\myVirtualToplevel|UART0|ALT_INV_Equal5~0_combout\ <= NOT \myVirtualToplevel|UART0|Equal5~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(7) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(7) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(6) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6); +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(6) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6); +\myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\ <= NOT \myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\; +\myVirtualToplevel|ALT_INV_UART0_CS~combout\ <= NOT \myVirtualToplevel|UART0_CS~combout\; +\myVirtualToplevel|ALT_INV_Equal3~1_combout\ <= NOT \myVirtualToplevel|Equal3~1_combout\; +\myVirtualToplevel|ALT_INV_Equal3~0_combout\ <= NOT \myVirtualToplevel|Equal3~0_combout\; +\myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\ <= NOT \myVirtualToplevel|IO_SELECT~2_combout\; +\myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\ <= NOT \myVirtualToplevel|IO_SELECT~1_combout\; +\myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\ <= NOT \myVirtualToplevel|IO_SELECT~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\; +\ALT_INV_reset~combout\ <= NOT \reset~combout\; +\myVirtualToplevel|ALT_INV_RESET_n~0_combout\ <= NOT \myVirtualToplevel|RESET_n~0_combout\; +\myVirtualToplevel|ALT_INV_Equal12~3_combout\ <= NOT \myVirtualToplevel|Equal12~3_combout\; +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(8) <= NOT \myVirtualToplevel|RESET_COUNTER\(8); +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(9) <= NOT \myVirtualToplevel|RESET_COUNTER\(9); +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(12) <= NOT \myVirtualToplevel|RESET_COUNTER\(12); +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(13) <= NOT \myVirtualToplevel|RESET_COUNTER\(13); +\myVirtualToplevel|ALT_INV_Equal12~2_combout\ <= NOT \myVirtualToplevel|Equal12~2_combout\; +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(10) <= NOT \myVirtualToplevel|RESET_COUNTER\(10); +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(11) <= NOT \myVirtualToplevel|RESET_COUNTER\(11); +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(14) <= NOT \myVirtualToplevel|RESET_COUNTER\(14); +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(15) <= NOT \myVirtualToplevel|RESET_COUNTER\(15); +\myVirtualToplevel|ALT_INV_Equal12~1_combout\ <= NOT \myVirtualToplevel|Equal12~1_combout\; +\myVirtualToplevel|ALT_INV_Equal12~0_combout\ <= NOT \myVirtualToplevel|Equal12~0_combout\; +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(0) <= NOT \myVirtualToplevel|RESET_COUNTER\(0); +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(1) <= NOT \myVirtualToplevel|RESET_COUNTER\(1); +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(2) <= NOT \myVirtualToplevel|RESET_COUNTER\(2); +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(3) <= NOT \myVirtualToplevel|RESET_COUNTER\(3); +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(4) <= NOT \myVirtualToplevel|RESET_COUNTER\(4); +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(5) <= NOT \myVirtualToplevel|RESET_COUNTER\(5); +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(6) <= NOT \myVirtualToplevel|RESET_COUNTER\(6); +\myVirtualToplevel|ALT_INV_RESET_COUNTER\(7) <= NOT \myVirtualToplevel|RESET_COUNTER\(7); +\myVirtualToplevel|ALT_INV_Equal11~4_combout\ <= NOT \myVirtualToplevel|Equal11~4_combout\; +\myVirtualToplevel|ALT_INV_Equal11~3_combout\ <= NOT \myVirtualToplevel|Equal11~3_combout\; +\myVirtualToplevel|ALT_INV_Equal11~2_combout\ <= NOT \myVirtualToplevel|Equal11~2_combout\; +\myVirtualToplevel|ALT_INV_Equal11~1_combout\ <= NOT \myVirtualToplevel|Equal11~1_combout\; +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(10) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(10); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(12) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(12); +\myVirtualToplevel|ALT_INV_Equal11~0_combout\ <= NOT \myVirtualToplevel|Equal11~0_combout\; +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(0) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(0); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(2) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(2); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(4) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(4); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(9) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_2~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~11_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~11_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~9_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~9_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~8_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~8_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~7_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~7_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~6_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~6_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal2~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal2~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~5_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~5_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~4_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~3_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~3_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~2_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~9_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~9_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~8_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~8_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~1_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~2_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~19_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~1_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(1); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(3); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(0); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(2); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuIsWriting~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~16_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~16_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~7_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~5_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~4_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~3_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~15_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~15_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~5_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~5_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~4_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~4_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux8~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux8~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(10) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(10); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux9~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux9~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~3_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~3_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux11~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux11~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux12~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux12~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~2_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux7~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux7~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(11) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(11); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux10~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux10~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~1_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux13~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux13~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux14~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux14~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux15~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux15~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux16~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux16~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux17~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux17~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux18~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux18~0_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2_combout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector501~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector640~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector640~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector706~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector706~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector970~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector970~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector904~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector904~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector838~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector838~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[26]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector772~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector772~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[18]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~38_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr171~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tIdx~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tIdx~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_intTriggered~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inInterrupt~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~4_combout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(31) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~47_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~47_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~41_sumout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(30) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(30); +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~43_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~43_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~37_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(29) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~39_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~39_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~33_sumout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(28) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(28); +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~35_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~35_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~30_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~30_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~26_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~26_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~22_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~22_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~18_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~18_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~14_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~14_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~10_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~10_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~6_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~6_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~5_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(0) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(0); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(1) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(1); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(2) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(2); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(3) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(3); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(7) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(7); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(9) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(9); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(10) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(10); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(11) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(11); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(12) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(12); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(13) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(13); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(14) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(14); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(17) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(17); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(6) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(6); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(8) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(8); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(15) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(15); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(16) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(16); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(4) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(4); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(5) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(5); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(1) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(0) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(0); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(0) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(0); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(1) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(1); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(2) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(2); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(4) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(4); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(7) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(7); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(9) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(9); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(10) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(10); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(11) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(11); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(12) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(12); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(13) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(13); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(14) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(14); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(17) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(17); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(6) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(6); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(8) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(8); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(15) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(15); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(16) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(16); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(3) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(3); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(5) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(5); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(1) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(1); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(0) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(0); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(2) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(2); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(3) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(3); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(4) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(4); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(7) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(7); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(0) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(0); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(1) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(1); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(5) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(5); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(6) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~93_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\; +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~89_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~93_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~89_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~89_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux179~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(31); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(48); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(52); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(55); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(53); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(54); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~1_sumout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(2); +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(3) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(0); +\myVirtualToplevel|UART1|ALT_INV_Add9~21_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~21_sumout\; +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(2); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(2) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(2); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(2) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(2); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(2) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(2); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(2) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(2); +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~85_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add9~17_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~17_sumout\; +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(3); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(3); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(3) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(3); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(3) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(3); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(3) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(3); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(3) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(3); +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(8) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(8); +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(8) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(8); +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(8) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(8); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(8) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(8); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(8) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(8); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(8) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(8); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(8) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~77_sumout\; +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(7) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(7); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(7) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(7); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(7) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(7); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(7) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(7); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(7) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(7); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(7) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(7); +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(7) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(7); +\myVirtualToplevel|UART1|ALT_INV_Add9~13_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~73_sumout\; +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(6) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(6); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(6) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(6); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(6) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(6); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(6) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(6) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(6); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(6) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(6); +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(6) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(6); +\myVirtualToplevel|UART1|ALT_INV_Add9~9_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(11) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(11); +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(11) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(11); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(11) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(11); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(11) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(11); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(11) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(10) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(10); +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(10) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(10); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(10) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(10); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(10) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(10); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(10) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(9); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(9) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(9); +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(9) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(9); +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(9) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(9); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(9) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(9); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(9) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(9); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(9) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(9); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(9) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\; +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(5) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(5); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(5) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(5); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(5) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(5); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(5) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(5); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(5) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(5) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(5); +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(5) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(5); +\myVirtualToplevel|UART1|ALT_INV_Add9~5_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\; +\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(4); +\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(4); +\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(4); +\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(4) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(4); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(4) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(4); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(4) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(4) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(4); +\myVirtualToplevel|UART1|ALT_INV_Add9~1_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(15) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(15); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(15) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(15); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(15) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~45_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(14) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(14); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(14) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(14); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(14) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(13) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(13); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(13) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(13); +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(13) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~37_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(12) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(12); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(12) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(12); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(12) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(3); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(19) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(19); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(19) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(19); +\myVirtualToplevel|UART1|ALT_INV_Add10~29_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~29_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(2); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(18) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(18); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(18) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(18); +\myVirtualToplevel|UART1|ALT_INV_Add10~25_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~25_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(1); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(17) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(17); +\myVirtualToplevel|UART1|ALT_INV_Add6~29_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~29_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add6~25_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~25_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add6~21_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~21_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add6~17_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~17_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add6~13_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~13_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add6~5_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~5_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add6~1_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~1_sumout\; +\myVirtualToplevel|UART1|ALT_INV_Add10~21_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~21_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(17) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(7) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(7); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(23) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(23); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(23) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(23); +\myVirtualToplevel|UART1|ALT_INV_Add10~17_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~17_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(4); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(20) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(20); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(20) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(20); +\myVirtualToplevel|UART1|ALT_INV_Add10~13_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~13_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(6); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(22) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(22); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(22) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(22); +\myVirtualToplevel|UART1|ALT_INV_Add10~9_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~9_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(5); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(21) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(21); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(21) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(21); +\myVirtualToplevel|UART1|ALT_INV_Add10~5_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~5_sumout\; +\myVirtualToplevel|UART0|ALT_INV_TX_INTR~q\ <= NOT \myVirtualToplevel|UART0|TX_INTR~q\; +\myVirtualToplevel|UART1|ALT_INV_TX_INTR~q\ <= NOT \myVirtualToplevel|UART1|TX_INTR~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~5_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(0); +\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(16) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(16); +\myVirtualToplevel|UART1|ALT_INV_Add10~1_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~1_sumout\; +\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(16) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(16); +\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(16) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~93_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~89_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.valid~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a3\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(24); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(27); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(28); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(25); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(26); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(30); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(11) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(11); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(27) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(27); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(10) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(10); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(26) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(26); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(9) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(9); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(25) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(25); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(8) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(8); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(24) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(24); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(7) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(7); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(23) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(23); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(6) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(6); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(22) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(22); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(5) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(5); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(21) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(21); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(4); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(20) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(20); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(3); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(19) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(19); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(2); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(18) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(18); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(1); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(17) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(17); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(0); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(16) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(16); +\myVirtualToplevel|ALT_INV_Add0~21_sumout\ <= NOT \myVirtualToplevel|Add0~21_sumout\; +\myVirtualToplevel|ALT_INV_Add0~17_sumout\ <= NOT \myVirtualToplevel|Add0~17_sumout\; +\myVirtualToplevel|ALT_INV_Add0~13_sumout\ <= NOT \myVirtualToplevel|Add0~13_sumout\; +\myVirtualToplevel|ALT_INV_Add0~9_sumout\ <= NOT \myVirtualToplevel|Add0~9_sumout\; +\myVirtualToplevel|ALT_INV_Add0~5_sumout\ <= NOT \myVirtualToplevel|Add0~5_sumout\; +\myVirtualToplevel|ALT_INV_Add0~1_sumout\ <= NOT \myVirtualToplevel|Add0~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(2); +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a1\; +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a2\; +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a3\; +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a4\; +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a5\; +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a6\; +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a7\; +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0); +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(2) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(0); +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(2) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2); +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(3) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~81_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add6~29_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~29_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add6~25_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~25_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add6~17_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~17_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add6~13_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~13_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add6~9_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~9_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add6~5_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~5_sumout\; +\myVirtualToplevel|UART0|ALT_INV_Add6~1_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~1_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~77_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(7) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(7); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(7) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~73_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(6) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~69_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~65_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~61_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~57_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(5) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~53_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~49_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(15) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~45_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(14) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~41_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(13) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~37_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(12) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~33_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(19) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~29_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(18) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~25_sumout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(17) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(17); +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~21_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(23) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~17_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(20) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~13_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(22) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~9_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(21) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~5_sumout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\; +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8~portbdataout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(16) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(16); +\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(16) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~85_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~81_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~77_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~73_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~69_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~65_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~61_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~53_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~49_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~29_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(8); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(4); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(15) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(15); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(31) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(31); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(14) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(14); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(30) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(30); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(13) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(13); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(29) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(29); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(12) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(12); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(28) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(28); +\myVirtualToplevel|ALT_INV_Add2~57_sumout\ <= NOT \myVirtualToplevel|Add2~57_sumout\; +\myVirtualToplevel|ALT_INV_Add2~53_sumout\ <= NOT \myVirtualToplevel|Add2~53_sumout\; +\myVirtualToplevel|ALT_INV_Add2~49_sumout\ <= NOT \myVirtualToplevel|Add2~49_sumout\; +\myVirtualToplevel|ALT_INV_Add2~45_sumout\ <= NOT \myVirtualToplevel|Add2~45_sumout\; +\myVirtualToplevel|ALT_INV_Add2~41_sumout\ <= NOT \myVirtualToplevel|Add2~41_sumout\; +\myVirtualToplevel|ALT_INV_Add2~37_sumout\ <= NOT \myVirtualToplevel|Add2~37_sumout\; +\myVirtualToplevel|ALT_INV_Add2~33_sumout\ <= NOT \myVirtualToplevel|Add2~33_sumout\; +\myVirtualToplevel|ALT_INV_Add2~29_sumout\ <= NOT \myVirtualToplevel|Add2~29_sumout\; +\myVirtualToplevel|ALT_INV_Add2~25_sumout\ <= NOT \myVirtualToplevel|Add2~25_sumout\; +\myVirtualToplevel|ALT_INV_Add2~21_sumout\ <= NOT \myVirtualToplevel|Add2~21_sumout\; +\myVirtualToplevel|ALT_INV_Add2~17_sumout\ <= NOT \myVirtualToplevel|Add2~17_sumout\; +\myVirtualToplevel|ALT_INV_Add2~13_sumout\ <= NOT \myVirtualToplevel|Add2~13_sumout\; +\myVirtualToplevel|ALT_INV_Add2~9_sumout\ <= NOT \myVirtualToplevel|Add2~9_sumout\; +\myVirtualToplevel|ALT_INV_Add2~5_sumout\ <= NOT \myVirtualToplevel|Add2~5_sumout\; +\myVirtualToplevel|ALT_INV_Add2~1_sumout\ <= NOT \myVirtualToplevel|Add2~1_sumout\; +\myVirtualToplevel|ALT_INV_Add1~21_sumout\ <= NOT \myVirtualToplevel|Add1~21_sumout\; +\myVirtualToplevel|ALT_INV_Add1~17_sumout\ <= NOT \myVirtualToplevel|Add1~17_sumout\; +\myVirtualToplevel|ALT_INV_Add1~9_sumout\ <= NOT \myVirtualToplevel|Add1~9_sumout\; +\myVirtualToplevel|ALT_INV_Add1~5_sumout\ <= NOT \myVirtualToplevel|Add1~5_sumout\; +\myVirtualToplevel|ALT_INV_Add1~1_sumout\ <= NOT \myVirtualToplevel|Add1~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~1_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~45_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~41_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~37_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~33_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~25_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~21_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~17_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~13_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~9_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~5_sumout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~1_sumout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~25_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~25_sumout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~21_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~21_sumout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~17_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~17_sumout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~13_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~13_sumout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~9_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~9_sumout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~5_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~5_sumout\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~1_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~1_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~25_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~25_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~21_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~17_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(0); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~9_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~5_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~1_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\; +\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(0) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(0); +\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(5) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(5); +\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(2) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(2); +\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(4) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(4); +\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(6) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(6); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~29_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~25_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~21_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~13_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~9_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~5_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5_sumout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~1_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\; +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(1) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(1); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(14) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(14); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(13) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(13); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(5) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(5); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(4) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(4); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(12) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(12); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(11) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(11); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(0) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(0); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(7) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(7); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(3) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(3); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(2) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(2); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(1) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(1); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(8) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(8); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(10) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(10); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(9) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(9); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(15) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(15); +\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(6) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(19); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(18); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(17); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(20); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(22); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(21); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(7) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(7); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(6) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(6); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(5) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(5); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(3) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(3); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(14) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(14); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(13) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(13); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(11) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(11); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(8) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(8); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(1) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(1); +\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(15) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a1\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(10); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(7); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(4); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(15); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(14); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(13); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(12); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(0); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(10) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(10); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(11) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(11); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(9) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(9); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(7) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(7); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(8) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(8); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(2); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(3); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(4); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(5) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(5); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(6) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(6); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][10]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][10]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][10]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][10]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][10]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][10]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][9]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][9]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][9]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][9]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][9]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][9]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][9]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][9]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][7]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][7]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][7]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][7]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][7]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][7]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][7]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][6]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][6]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][6]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][6]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][6]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][6]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][6]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][11]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][11]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][11]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][11]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][8]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][8]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][8]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][8]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][8]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][8]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][8]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][5]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][5]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][5]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][5]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][5]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][5]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][5]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][5]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][4]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][4]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][4]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][4]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][4]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][4]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][4]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][3]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][3]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][3]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][3]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][3]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][3]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][3]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][3]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][2]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][2]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][2]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][2]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][2]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][2]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][2]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][1]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][1]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][1]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][1]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][1]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][1]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][1]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][0]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][0]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][0]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][0]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][0]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][0]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][0]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][0]~q\; +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(6) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(5) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(7) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(7); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(4); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(0); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(1); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(3); +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(8) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(8); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(7) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(7); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(6); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(5); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(4); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(3); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(2); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(9) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0); +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(1); +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(0) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux14~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux17~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux17~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(2); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux12~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux12~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux9~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux9~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux15~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux15~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux18~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux18~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux13~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux13~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux10~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux10~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux16~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux16~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux19~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux19~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux1~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_DATA_PRTMODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_DATA_PRTMODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_DATA_PRTMODE\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT[2]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~0_combout\; +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(43) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(43); +\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(4) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(4); +\myVirtualToplevel|UART0|ALT_INV_TX_DATA~8_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~8_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~20_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~20_q\; +\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(19) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(19); +\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(3) <= NOT \myVirtualToplevel|UART0|TX_DATA\(3); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~0_combout\; +\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(11) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(11); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector357~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~0_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~64_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[1]~64_combout\; +\myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~63_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[1]~63_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(1) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(1); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(1) <= NOT \myVirtualToplevel|IO_DATA_READ\(1); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~87_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~87_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~106_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~106_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~86_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~86_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~85_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~85_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~49_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~48_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~84_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~84_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~83_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~83_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector358~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~101_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~101_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~47_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~46_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~41_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~25_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~24_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~23_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~22_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~21_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~20_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~19_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~40_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~39_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~18_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~17_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~16_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~15_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(30); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~1_combout\; +\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(0) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(0); +\myVirtualToplevel|ALT_INV_IO_DATA_READ\(0) <= NOT \myVirtualToplevel|IO_DATA_READ\(0); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr160~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr160~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_DATA~14_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~14_combout\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~20_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~20_q\; +\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(19) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(19); +\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(3) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(3); +\myVirtualToplevel|UART1|ALT_INV_RX_DATA~14_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~14_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~20_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~20_q\; +\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(19) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(19); +\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(3) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(3); +\myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~0_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA_READY~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~0_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA_READY~0_combout\; +\myVirtualToplevel|UART1|ALT_INV_Add9~29_combout\ <= NOT \myVirtualToplevel|UART1|Add9~29_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector356~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~1_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~0_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~14_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~13_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~82_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~82_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~12_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~11_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(29); +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~10_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~9_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~8_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~7_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~6_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~5_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~4_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~3_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~2_combout\; +\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~81_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~81_combout\; + +-- Location: IOOBUF_X38_Y0_N36 +\UART_TX_1~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TXD~q\, + devoe => ww_devoe, + o => ww_UART_TX_1); + +-- Location: IOOBUF_X25_Y0_N36 +\SDRAM_CLK~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + devoe => ww_devoe, + o => ww_SDRAM_CLK); + +-- Location: IOOBUF_X36_Y0_N36 +\UART_TX_0~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|UART0|ALT_INV_TXD~q\, + devoe => ww_devoe, + o => ww_UART_TX_0); + +-- Location: IOOBUF_X43_Y0_N36 +\SDCARD_MOSI[0]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~q\, + devoe => ww_devoe, + o => ww_SDCARD_MOSI(0)); + +-- Location: IOOBUF_X44_Y0_N36 +\SDCARD_CLK[0]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\, + devoe => ww_devoe, + o => ww_SDCARD_CLK(0)); + +-- Location: IOOBUF_X48_Y0_N59 +\SDCARD_CS[0]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_cs_bo~q\, + devoe => ww_devoe, + o => ww_SDCARD_CS(0)); + +-- Location: IOOBUF_X18_Y0_N19 +\SDRAM_ADDR[0]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(0), + devoe => ww_devoe, + o => ww_SDRAM_ADDR(0)); + +-- Location: IOOBUF_X14_Y0_N36 +\SDRAM_ADDR[1]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(1), + devoe => ww_devoe, + o => ww_SDRAM_ADDR(1)); + +-- Location: IOOBUF_X18_Y0_N2 +\SDRAM_ADDR[2]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(2), + devoe => ww_devoe, + o => ww_SDRAM_ADDR(2)); + +-- Location: IOOBUF_X11_Y0_N2 +\SDRAM_ADDR[3]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(3), + devoe => ww_devoe, + o => ww_SDRAM_ADDR(3)); + +-- Location: IOOBUF_X12_Y0_N53 +\SDRAM_ADDR[4]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(4), + devoe => ww_devoe, + o => ww_SDRAM_ADDR(4)); + +-- Location: IOOBUF_X10_Y0_N93 +\SDRAM_ADDR[5]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(5), + devoe => ww_devoe, + o => ww_SDRAM_ADDR(5)); + +-- Location: IOOBUF_X12_Y0_N36 +\SDRAM_ADDR[6]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(6), + devoe => ww_devoe, + o => ww_SDRAM_ADDR(6)); + +-- Location: IOOBUF_X10_Y0_N76 +\SDRAM_ADDR[7]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(7), + devoe => ww_devoe, + o => ww_SDRAM_ADDR(7)); + +-- Location: IOOBUF_X12_Y0_N2 +\SDRAM_ADDR[8]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(8), + devoe => ww_devoe, + o => ww_SDRAM_ADDR(8)); + +-- Location: IOOBUF_X11_Y0_N53 +\SDRAM_ADDR[9]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(9), + devoe => ww_devoe, + o => ww_SDRAM_ADDR(9)); + +-- Location: IOOBUF_X10_Y0_N59 +\SDRAM_ADDR[10]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(10), + devoe => ww_devoe, + o => ww_SDRAM_ADDR(10)); + +-- Location: IOOBUF_X19_Y0_N19 +\SDRAM_ADDR[11]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(11), + devoe => ww_devoe, + o => ww_SDRAM_ADDR(11)); + +-- Location: IOOBUF_X18_Y0_N36 +\SDRAM_DQM[0]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQM\(0), + devoe => ww_devoe, + o => ww_SDRAM_DQM(0)); + +-- Location: IOOBUF_X16_Y0_N42 +\SDRAM_DQM[1]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQM\(1), + devoe => ww_devoe, + o => ww_SDRAM_DQM(1)); + +-- Location: IOOBUF_X12_Y0_N19 +\SDRAM_BA[0]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA\(0), + devoe => ww_devoe, + o => ww_SDRAM_BA(0)); + +-- Location: IOOBUF_X29_Y0_N19 +\SDRAM_BA[1]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA\(1), + devoe => ww_devoe, + o => ww_SDRAM_BA(1)); + +-- Location: IOOBUF_X11_Y0_N36 +\SDRAM_WE~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_WE_n~q\, + devoe => ww_devoe, + o => ww_SDRAM_WE); + +-- Location: IOOBUF_X16_Y0_N93 +\SDRAM_RAS~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_RAS_n~q\, + devoe => ww_devoe, + o => ww_SDRAM_RAS); + +-- Location: IOOBUF_X18_Y0_N53 +\SDRAM_CAS~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_CAS_n~q\, + devoe => ww_devoe, + o => ww_SDRAM_CAS); + +-- Location: IOOBUF_X50_Y45_N2 +\LEDR~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => GND, + devoe => ww_devoe, + o => ww_LEDR); + +-- Location: IOOBUF_X16_Y0_N59 +\SDRAM_CKE~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => VCC, + devoe => ww_devoe, + o => ww_SDRAM_CKE); + +-- Location: IOOBUF_X16_Y0_N76 +\SDRAM_CS~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => GND, + devoe => ww_devoe, + o => ww_SDRAM_CS); + +-- Location: IOOBUF_X25_Y0_N2 +\SDRAM_DQ[12]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(12)); + +-- Location: IOOBUF_X24_Y0_N2 +\SDRAM_DQ[13]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(13)); + +-- Location: IOOBUF_X24_Y0_N53 +\SDRAM_DQ[14]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(14)); + +-- Location: IOOBUF_X24_Y0_N36 +\SDRAM_DQ[15]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(15)); + +-- Location: IOOBUF_X29_Y0_N36 +\SDRAM_DQ[0]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(0)); + +-- Location: IOOBUF_X29_Y0_N53 +\SDRAM_DQ[1]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(1)); + +-- Location: IOOBUF_X22_Y0_N53 +\SDRAM_DQ[2]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(2)); + +-- Location: IOOBUF_X25_Y0_N53 +\SDRAM_DQ[3]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(3)); + +-- Location: IOOBUF_X23_Y0_N93 +\SDRAM_DQ[4]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(4)); + +-- Location: IOOBUF_X22_Y0_N36 +\SDRAM_DQ[5]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(5)); + +-- Location: IOOBUF_X19_Y0_N36 +\SDRAM_DQ[6]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(6)); + +-- Location: IOOBUF_X19_Y0_N53 +\SDRAM_DQ[7]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(7)); + +-- Location: IOOBUF_X19_Y0_N2 +\SDRAM_DQ[8]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(8)); + +-- Location: IOOBUF_X23_Y0_N59 +\SDRAM_DQ[9]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(9)); + +-- Location: IOOBUF_X24_Y0_N19 +\SDRAM_DQ[10]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(10)); + +-- Location: IOOBUF_X25_Y0_N19 +\SDRAM_DQ[11]~output\ : cyclonev_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false", + shift_series_termination_control => "false") +-- pragma translate_on +PORT MAP ( + i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~reg0_q\, + oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~en_q\, + devoe => ww_devoe, + o => SDRAM_DQ(11)); + +-- Location: IOIBUF_X22_Y0_N1 +\CLOCK_50~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_CLOCK_50, + o => \CLOCK_50~input_o\); + +-- Location: PLLREFCLKSELECT_X0_Y7_N0 +\mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT\ : cyclonev_pll_refclk_select +-- pragma translate_off +GENERIC MAP ( + pll_auto_clk_sw_en => "false", + pll_clk_loss_edge => "both_edges", + pll_clk_loss_sw_en => "false", + pll_clk_sw_dly => 0, + pll_clkin_0_src => "clk_0", + pll_clkin_1_src => "ref_clk1", + pll_manu_clk_sw_en => "false", + pll_sw_refclk_src => "clk_0") +-- pragma translate_on +PORT MAP ( + clkin => \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_CLKIN_bus\, + clkout => \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_O_CLKOUT\, + extswitchbuf => \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_O_EXTSWITCHBUF\); + +-- Location: IOIBUF_X33_Y0_N92 +\KEY~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_KEY, + o => \KEY~input_o\); + +-- Location: FRACTIONALPLL_X0_Y1_N0 +\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL\ : cyclonev_fractional_pll +-- pragma translate_off +GENERIC MAP ( + dsm_accumulator_reset_value => 0, + forcelock => "false", + mimic_fbclk_type => "gclk_far", + nreset_invert => "true", + output_clock_frequency => "300.0 mhz", + pll_atb => 0, + pll_bwctrl => 4000, + pll_cmp_buf_dly => "0 ps", + pll_cp_comp => "true", + pll_cp_current => 10, + pll_ctrl_override_setting => "false", + pll_dsm_dither => "disable", + pll_dsm_out_sel => "disable", + pll_dsm_reset => "false", + pll_ecn_bypass => "false", + pll_ecn_test_en => "false", + pll_enable => "true", + pll_fbclk_mux_1 => "glb", + pll_fbclk_mux_2 => "fb_1", + pll_fractional_carry_out => 32, + pll_fractional_division => 1, + pll_fractional_division_string => "'0'", + pll_fractional_value_ready => "true", + pll_lf_testen => "false", + pll_lock_fltr_cfg => 25, + pll_lock_fltr_test => "false", + pll_m_cnt_bypass_en => "false", + pll_m_cnt_coarse_dly => "0 ps", + pll_m_cnt_fine_dly => "0 ps", + pll_m_cnt_hi_div => 6, + pll_m_cnt_in_src => "ph_mux_clk", + pll_m_cnt_lo_div => 6, + pll_m_cnt_odd_div_duty_en => "false", + pll_m_cnt_ph_mux_prst => 0, + pll_m_cnt_prst => 1, + pll_n_cnt_bypass_en => "false", + pll_n_cnt_coarse_dly => "0 ps", + pll_n_cnt_fine_dly => "0 ps", + pll_n_cnt_hi_div => 1, + pll_n_cnt_lo_div => 1, + pll_n_cnt_odd_div_duty_en => "false", + pll_ref_buf_dly => "0 ps", + pll_reg_boost => 0, + pll_regulator_bypass => "false", + pll_ripplecap_ctrl => 0, + pll_slf_rst => "false", + pll_tclk_mux_en => "false", + pll_tclk_sel => "n_src", + pll_test_enable => "false", + pll_testdn_enable => "false", + pll_testup_enable => "false", + pll_unlock_fltr_cfg => 2, + pll_vco_div => 2, + pll_vco_ph0_en => "true", + pll_vco_ph1_en => "true", + pll_vco_ph2_en => "true", + pll_vco_ph3_en => "true", + pll_vco_ph4_en => "true", + pll_vco_ph5_en => "true", + pll_vco_ph6_en => "true", + pll_vco_ph7_en => "true", + pll_vctrl_test_voltage => 750, + reference_clock_frequency => "50.0 mhz", + vccd0g_atb => "disable", + vccd0g_output => 0, + vccd1g_atb => "disable", + vccd1g_output => 0, + vccm1g_tap => 2, + vccr_pd => "false", + vcodiv_override => "false", + fractional_pll_index => 0) +-- pragma translate_on +PORT MAP ( + coreclkfb => \mypll|altpll_component|auto_generated|fb_clkin\, + ecnc1test => \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_O_EXTSWITCHBUF\, + nresync => \ALT_INV_KEY~input_o\, + refclkin => \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_O_CLKOUT\, + shift => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFT\, + shiftdonein => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFT\, + shiften => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFTENM\, + up => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_UP\, + cntnen => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_CNTNEN\, + fbclk => \mypll|altpll_component|auto_generated|fb_clkin\, + lock => \mypll|altpll_component|auto_generated|wire_generic_pll1_locked\, + tclk => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_TCLK\, + vcoph => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\, + mhi => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\); + +-- Location: PLLRECONFIG_X0_Y5_N0 +\mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG\ : cyclonev_pll_reconfig +-- pragma translate_off +GENERIC MAP ( + fractional_pll_index => 0) +-- pragma translate_on +PORT MAP ( + cntnen => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_CNTNEN\, + mhi => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_MHI_bus\, + shift => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFT\, + shiftenm => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFTENM\, + up => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_UP\, + shiften => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_SHIFTEN_bus\); + +-- Location: PLLOUTPUTCOUNTER_X0_Y0_N1 +\mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER\ : cyclonev_pll_output_counter +-- pragma translate_off +GENERIC MAP ( + c_cnt_coarse_dly => "0 ps", + c_cnt_fine_dly => "0 ps", + c_cnt_in_src => "ph_mux_clk", + c_cnt_ph_mux_prst => 2, + c_cnt_prst => 3, + cnt_fpll_src => "fpll_0", + dprio0_cnt_bypass_en => "false", + dprio0_cnt_hi_div => 2, + dprio0_cnt_lo_div => 1, + dprio0_cnt_odd_div_even_duty_en => "true", + duty_cycle => 50, + output_clock_frequency => "100.0 mhz", + phase_shift => "7500 ps", + fractional_pll_index => 0, + output_counter_index => 0) +-- pragma translate_on +PORT MAP ( + nen0 => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_CNTNEN\, + shift0 => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFT\, + shiften => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFTEN0\, + tclk0 => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_TCLK\, + up0 => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_UP\, + vco0ph => \mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER_VCO0PH_bus\, + divclk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk\); + +-- Location: CLKCTRL_G2 +\mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0\ : cyclonev_clkena +-- pragma translate_off +GENERIC MAP ( + clock_type => "global clock", + disable_mode => "low", + ena_register_mode => "always enabled", + ena_register_power_up => "high", + test_syn => "high") +-- pragma translate_on +PORT MAP ( + inclk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk\, + outclk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\); + +-- Location: PLLOUTPUTCOUNTER_X0_Y2_N1 +\mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER\ : cyclonev_pll_output_counter +-- pragma translate_off +GENERIC MAP ( + c_cnt_coarse_dly => "0 ps", + c_cnt_fine_dly => "0 ps", + c_cnt_in_src => "ph_mux_clk", + c_cnt_ph_mux_prst => 0, + c_cnt_prst => 1, + cnt_fpll_src => "fpll_0", + dprio0_cnt_bypass_en => "false", + dprio0_cnt_hi_div => 2, + dprio0_cnt_lo_div => 1, + dprio0_cnt_odd_div_even_duty_en => "true", + duty_cycle => 50, + output_clock_frequency => "100.0 mhz", + phase_shift => "0 ps", + fractional_pll_index => 0, + output_counter_index => 2) +-- pragma translate_on +PORT MAP ( + nen0 => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_CNTNEN\, + shift0 => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFT\, + shiften => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIGSHIFTEN2\, + tclk0 => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_TCLK\, + up0 => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_UP\, + vco0ph => \mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER_VCO0PH_bus\, + divclk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk\); + +-- Location: CLKCTRL_G3 +\mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0\ : cyclonev_clkena +-- pragma translate_off +GENERIC MAP ( + clock_type => "global clock", + disable_mode => "low", + ena_register_mode => "always enabled", + ena_register_power_up => "high", + test_syn => "high") +-- pragma translate_on +PORT MAP ( + inclk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk\, + outclk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\); + +-- Location: IOIBUF_X36_Y0_N1 +\UART_RX_1~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_UART_RX_1, + o => \UART_RX_1~input_o\); + +-- Location: IOIBUF_X34_Y0_N52 +\UART_RX_0~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_UART_RX_0, + o => \UART_RX_0~input_o\); + +-- Location: LABCELL_X10_Y4_N45 +\myVirtualToplevel|RESET_COUNTER_RX~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER_RX~3_combout\ = ( !\myVirtualToplevel|Equal11~4_combout\ & ( (!\myVirtualToplevel|RESET_COUNTER_RX\(0) & ((!\UART_RX_1~input_o\) # (!\UART_RX_0~input_o\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111000000000111011100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \ALT_INV_UART_RX_1~input_o\, + datab => \ALT_INV_UART_RX_0~input_o\, + datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(0), + dataf => \myVirtualToplevel|ALT_INV_Equal11~4_combout\, + combout => \myVirtualToplevel|RESET_COUNTER_RX~3_combout\); + +-- Location: MLABCELL_X13_Y4_N18 +reset : cyclonev_lcell_comb +-- Equation(s): +-- \reset~combout\ = ( \mypll|altpll_component|auto_generated|wire_generic_pll1_locked\ & ( !\KEY~input_o\ ) ) # ( !\mypll|altpll_component|auto_generated|wire_generic_pll1_locked\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \ALT_INV_KEY~input_o\, + dataf => \mypll|altpll_component|auto_generated|ALT_INV_wire_generic_pll1_locked\, + combout => \reset~combout\); + +-- Location: FF_X10_Y4_N47 +\myVirtualToplevel|RESET_COUNTER_RX[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER_RX~3_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(0)); + +-- Location: MLABCELL_X9_Y4_N0 +\myVirtualToplevel|Add1~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~14\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER_RX\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(0), + cin => GND, + cout => \myVirtualToplevel|Add1~14\); + +-- Location: MLABCELL_X9_Y4_N3 +\myVirtualToplevel|Add1~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~29_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add1~14\ )) +-- \myVirtualToplevel|Add1~30\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add1~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(1), + cin => \myVirtualToplevel|Add1~14\, + sumout => \myVirtualToplevel|Add1~29_sumout\, + cout => \myVirtualToplevel|Add1~30\); + +-- Location: MLABCELL_X9_Y4_N24 +\myVirtualToplevel|Add1~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~33_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add1~62\ )) +-- \myVirtualToplevel|Add1~34\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add1~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(8), + cin => \myVirtualToplevel|Add1~62\, + sumout => \myVirtualToplevel|Add1~33_sumout\, + cout => \myVirtualToplevel|Add1~34\); + +-- Location: MLABCELL_X9_Y4_N27 +\myVirtualToplevel|Add1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~1_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER_RX\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add1~34\ )) +-- \myVirtualToplevel|Add1~2\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER_RX\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add1~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(9), + cin => \myVirtualToplevel|Add1~34\, + sumout => \myVirtualToplevel|Add1~1_sumout\, + cout => \myVirtualToplevel|Add1~2\); + +-- Location: LABCELL_X10_Y4_N27 +\myVirtualToplevel|RESET_COUNTER_RX~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER_RX~0_combout\ = ( !\myVirtualToplevel|Equal11~4_combout\ & ( (!\myVirtualToplevel|Add1~1_sumout\ & ((!\UART_RX_1~input_o\) # (!\UART_RX_0~input_o\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111000000000111011100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \ALT_INV_UART_RX_1~input_o\, + datab => \ALT_INV_UART_RX_0~input_o\, + datad => \myVirtualToplevel|ALT_INV_Add1~1_sumout\, + dataf => \myVirtualToplevel|ALT_INV_Equal11~4_combout\, + combout => \myVirtualToplevel|RESET_COUNTER_RX~0_combout\); + +-- Location: FF_X10_Y4_N29 +\myVirtualToplevel|RESET_COUNTER_RX[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER_RX~0_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(9)); + +-- Location: MLABCELL_X9_Y4_N30 +\myVirtualToplevel|Add1~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~21_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER_RX\(10) ) + ( VCC ) + ( \myVirtualToplevel|Add1~2\ )) +-- \myVirtualToplevel|Add1~22\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER_RX\(10) ) + ( VCC ) + ( \myVirtualToplevel|Add1~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(10), + cin => \myVirtualToplevel|Add1~2\, + sumout => \myVirtualToplevel|Add1~21_sumout\, + cout => \myVirtualToplevel|Add1~22\); + +-- Location: LABCELL_X10_Y4_N21 +\myVirtualToplevel|RESET_COUNTER_RX~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER_RX~5_combout\ = ( !\myVirtualToplevel|Equal11~4_combout\ & ( (!\myVirtualToplevel|Add1~21_sumout\ & ((!\UART_RX_1~input_o\) # (!\UART_RX_0~input_o\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110000011100000111000001110000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \ALT_INV_UART_RX_1~input_o\, + datab => \ALT_INV_UART_RX_0~input_o\, + datac => \myVirtualToplevel|ALT_INV_Add1~21_sumout\, + dataf => \myVirtualToplevel|ALT_INV_Equal11~4_combout\, + combout => \myVirtualToplevel|RESET_COUNTER_RX~5_combout\); + +-- Location: FF_X10_Y4_N23 +\myVirtualToplevel|RESET_COUNTER_RX[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER_RX~5_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(10)); + +-- Location: MLABCELL_X9_Y4_N33 +\myVirtualToplevel|Add1~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~37_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add1~22\ )) +-- \myVirtualToplevel|Add1~38\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add1~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(11), + cin => \myVirtualToplevel|Add1~22\, + sumout => \myVirtualToplevel|Add1~37_sumout\, + cout => \myVirtualToplevel|Add1~38\); + +-- Location: FF_X9_Y4_N35 +\myVirtualToplevel|RESET_COUNTER_RX[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add1~37_sumout\, + clrn => \ALT_INV_reset~combout\, + sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(11)); + +-- Location: MLABCELL_X9_Y4_N36 +\myVirtualToplevel|Add1~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~17_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER_RX\(12) ) + ( VCC ) + ( \myVirtualToplevel|Add1~38\ )) +-- \myVirtualToplevel|Add1~18\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER_RX\(12) ) + ( VCC ) + ( \myVirtualToplevel|Add1~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(12), + cin => \myVirtualToplevel|Add1~38\, + sumout => \myVirtualToplevel|Add1~17_sumout\, + cout => \myVirtualToplevel|Add1~18\); + +-- Location: LABCELL_X10_Y4_N18 +\myVirtualToplevel|RESET_COUNTER_RX~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER_RX~4_combout\ = ( !\myVirtualToplevel|Equal11~4_combout\ & ( (!\myVirtualToplevel|Add1~17_sumout\ & ((!\UART_RX_1~input_o\) # (!\UART_RX_0~input_o\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110000011100000111000001110000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \ALT_INV_UART_RX_1~input_o\, + datab => \ALT_INV_UART_RX_0~input_o\, + datac => \myVirtualToplevel|ALT_INV_Add1~17_sumout\, + dataf => \myVirtualToplevel|ALT_INV_Equal11~4_combout\, + combout => \myVirtualToplevel|RESET_COUNTER_RX~4_combout\); + +-- Location: FF_X10_Y4_N20 +\myVirtualToplevel|RESET_COUNTER_RX[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER_RX~4_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(12)); + +-- Location: MLABCELL_X9_Y4_N39 +\myVirtualToplevel|Add1~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~41_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(13) ) + ( VCC ) + ( \myVirtualToplevel|Add1~18\ )) +-- \myVirtualToplevel|Add1~42\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(13) ) + ( VCC ) + ( \myVirtualToplevel|Add1~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(13), + cin => \myVirtualToplevel|Add1~18\, + sumout => \myVirtualToplevel|Add1~41_sumout\, + cout => \myVirtualToplevel|Add1~42\); + +-- Location: FF_X9_Y4_N41 +\myVirtualToplevel|RESET_COUNTER_RX[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add1~41_sumout\, + clrn => \ALT_INV_reset~combout\, + sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(13)); + +-- Location: MLABCELL_X9_Y4_N42 +\myVirtualToplevel|Add1~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~45_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(14) ) + ( VCC ) + ( \myVirtualToplevel|Add1~42\ )) +-- \myVirtualToplevel|Add1~46\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(14) ) + ( VCC ) + ( \myVirtualToplevel|Add1~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(14), + cin => \myVirtualToplevel|Add1~42\, + sumout => \myVirtualToplevel|Add1~45_sumout\, + cout => \myVirtualToplevel|Add1~46\); + +-- Location: FF_X9_Y4_N44 +\myVirtualToplevel|RESET_COUNTER_RX[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add1~45_sumout\, + clrn => \ALT_INV_reset~combout\, + sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(14)); + +-- Location: MLABCELL_X9_Y4_N45 +\myVirtualToplevel|Add1~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~25_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(15) ) + ( VCC ) + ( \myVirtualToplevel|Add1~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(15), + cin => \myVirtualToplevel|Add1~46\, + sumout => \myVirtualToplevel|Add1~25_sumout\); + +-- Location: FF_X9_Y4_N47 +\myVirtualToplevel|RESET_COUNTER_RX[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add1~25_sumout\, + clrn => \ALT_INV_reset~combout\, + sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(15)); + +-- Location: MLABCELL_X9_Y4_N48 +\myVirtualToplevel|Equal11~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal11~1_combout\ = ( \myVirtualToplevel|RESET_COUNTER_RX\(12) & ( (\myVirtualToplevel|RESET_COUNTER_RX\(10) & (!\myVirtualToplevel|RESET_COUNTER_RX\(15) & !\myVirtualToplevel|RESET_COUNTER_RX\(1))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000000010000000100000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(10), + datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(15), + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(1), + dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(12), + combout => \myVirtualToplevel|Equal11~1_combout\); + +-- Location: MLABCELL_X9_Y4_N54 +\myVirtualToplevel|Equal11~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal11~3_combout\ = ( !\myVirtualToplevel|RESET_COUNTER_RX\(3) & ( (!\myVirtualToplevel|RESET_COUNTER_RX\(5) & (!\myVirtualToplevel|RESET_COUNTER_RX\(6) & !\myVirtualToplevel|RESET_COUNTER_RX\(7))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(5), + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(6), + datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(7), + dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(3), + combout => \myVirtualToplevel|Equal11~3_combout\); + +-- Location: LABCELL_X10_Y4_N15 +\myVirtualToplevel|Equal11~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal11~0_combout\ = ( \myVirtualToplevel|RESET_COUNTER_RX\(2) & ( (\myVirtualToplevel|RESET_COUNTER_RX\(9) & (\myVirtualToplevel|RESET_COUNTER_RX\(0) & \myVirtualToplevel|RESET_COUNTER_RX\(4))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000001000000010000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(9), + datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(0), + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(4), + dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(2), + combout => \myVirtualToplevel|Equal11~0_combout\); + +-- Location: LABCELL_X10_Y4_N30 +\myVirtualToplevel|RESET_COUNTER_RX[0]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\ = ( \myVirtualToplevel|Equal11~2_combout\ & ( \myVirtualToplevel|Equal11~0_combout\ & ( (!\UART_RX_1~input_o\ & (\myVirtualToplevel|Equal11~1_combout\ & (\myVirtualToplevel|Equal11~3_combout\))) # +-- (\UART_RX_1~input_o\ & (((\myVirtualToplevel|Equal11~1_combout\ & \myVirtualToplevel|Equal11~3_combout\)) # (\UART_RX_0~input_o\))) ) ) ) # ( !\myVirtualToplevel|Equal11~2_combout\ & ( \myVirtualToplevel|Equal11~0_combout\ & ( (\UART_RX_1~input_o\ & +-- \UART_RX_0~input_o\) ) ) ) # ( \myVirtualToplevel|Equal11~2_combout\ & ( !\myVirtualToplevel|Equal11~0_combout\ & ( (\UART_RX_1~input_o\ & \UART_RX_0~input_o\) ) ) ) # ( !\myVirtualToplevel|Equal11~2_combout\ & ( !\myVirtualToplevel|Equal11~0_combout\ & ( +-- (\UART_RX_1~input_o\ & \UART_RX_0~input_o\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100000000010101010000001101010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \ALT_INV_UART_RX_1~input_o\, + datab => \myVirtualToplevel|ALT_INV_Equal11~1_combout\, + datac => \myVirtualToplevel|ALT_INV_Equal11~3_combout\, + datad => \ALT_INV_UART_RX_0~input_o\, + datae => \myVirtualToplevel|ALT_INV_Equal11~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_Equal11~0_combout\, + combout => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\); + +-- Location: FF_X9_Y4_N5 +\myVirtualToplevel|RESET_COUNTER_RX[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add1~29_sumout\, + clrn => \ALT_INV_reset~combout\, + sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(1)); + +-- Location: MLABCELL_X9_Y4_N6 +\myVirtualToplevel|Add1~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~9_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER_RX\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add1~30\ )) +-- \myVirtualToplevel|Add1~10\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER_RX\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add1~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(2), + cin => \myVirtualToplevel|Add1~30\, + sumout => \myVirtualToplevel|Add1~9_sumout\, + cout => \myVirtualToplevel|Add1~10\); + +-- Location: LABCELL_X10_Y4_N24 +\myVirtualToplevel|RESET_COUNTER_RX~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER_RX~2_combout\ = ( !\myVirtualToplevel|Equal11~4_combout\ & ( (!\myVirtualToplevel|Add1~9_sumout\ & ((!\UART_RX_1~input_o\) # (!\UART_RX_0~input_o\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110000011100000111000001110000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \ALT_INV_UART_RX_1~input_o\, + datab => \ALT_INV_UART_RX_0~input_o\, + datac => \myVirtualToplevel|ALT_INV_Add1~9_sumout\, + dataf => \myVirtualToplevel|ALT_INV_Equal11~4_combout\, + combout => \myVirtualToplevel|RESET_COUNTER_RX~2_combout\); + +-- Location: FF_X10_Y4_N26 +\myVirtualToplevel|RESET_COUNTER_RX[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER_RX~2_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(2)); + +-- Location: MLABCELL_X9_Y4_N9 +\myVirtualToplevel|Add1~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~49_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add1~10\ )) +-- \myVirtualToplevel|Add1~50\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add1~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(3), + cin => \myVirtualToplevel|Add1~10\, + sumout => \myVirtualToplevel|Add1~49_sumout\, + cout => \myVirtualToplevel|Add1~50\); + +-- Location: FF_X9_Y4_N11 +\myVirtualToplevel|RESET_COUNTER_RX[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add1~49_sumout\, + clrn => \ALT_INV_reset~combout\, + sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(3)); + +-- Location: MLABCELL_X9_Y4_N12 +\myVirtualToplevel|Add1~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~5_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER_RX\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add1~50\ )) +-- \myVirtualToplevel|Add1~6\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER_RX\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add1~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(4), + cin => \myVirtualToplevel|Add1~50\, + sumout => \myVirtualToplevel|Add1~5_sumout\, + cout => \myVirtualToplevel|Add1~6\); + +-- Location: LABCELL_X10_Y4_N42 +\myVirtualToplevel|RESET_COUNTER_RX~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER_RX~1_combout\ = ( !\myVirtualToplevel|Equal11~4_combout\ & ( (!\myVirtualToplevel|Add1~5_sumout\ & ((!\UART_RX_1~input_o\) # (!\UART_RX_0~input_o\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110000011100000111000001110000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \ALT_INV_UART_RX_1~input_o\, + datab => \ALT_INV_UART_RX_0~input_o\, + datac => \myVirtualToplevel|ALT_INV_Add1~5_sumout\, + dataf => \myVirtualToplevel|ALT_INV_Equal11~4_combout\, + combout => \myVirtualToplevel|RESET_COUNTER_RX~1_combout\); + +-- Location: FF_X10_Y4_N44 +\myVirtualToplevel|RESET_COUNTER_RX[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER_RX~1_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(4)); + +-- Location: MLABCELL_X9_Y4_N15 +\myVirtualToplevel|Add1~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~53_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add1~6\ )) +-- \myVirtualToplevel|Add1~54\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add1~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(5), + cin => \myVirtualToplevel|Add1~6\, + sumout => \myVirtualToplevel|Add1~53_sumout\, + cout => \myVirtualToplevel|Add1~54\); + +-- Location: FF_X9_Y4_N17 +\myVirtualToplevel|RESET_COUNTER_RX[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add1~53_sumout\, + clrn => \ALT_INV_reset~combout\, + sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(5)); + +-- Location: MLABCELL_X9_Y4_N18 +\myVirtualToplevel|Add1~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~57_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add1~54\ )) +-- \myVirtualToplevel|Add1~58\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add1~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(6), + cin => \myVirtualToplevel|Add1~54\, + sumout => \myVirtualToplevel|Add1~57_sumout\, + cout => \myVirtualToplevel|Add1~58\); + +-- Location: FF_X9_Y4_N20 +\myVirtualToplevel|RESET_COUNTER_RX[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add1~57_sumout\, + clrn => \ALT_INV_reset~combout\, + sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(6)); + +-- Location: MLABCELL_X9_Y4_N21 +\myVirtualToplevel|Add1~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add1~61_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add1~58\ )) +-- \myVirtualToplevel|Add1~62\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add1~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(7), + cin => \myVirtualToplevel|Add1~58\, + sumout => \myVirtualToplevel|Add1~61_sumout\, + cout => \myVirtualToplevel|Add1~62\); + +-- Location: FF_X9_Y4_N23 +\myVirtualToplevel|RESET_COUNTER_RX[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add1~61_sumout\, + clrn => \ALT_INV_reset~combout\, + sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(7)); + +-- Location: FF_X9_Y4_N26 +\myVirtualToplevel|RESET_COUNTER_RX[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add1~33_sumout\, + clrn => \ALT_INV_reset~combout\, + sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER_RX\(8)); + +-- Location: MLABCELL_X9_Y4_N57 +\myVirtualToplevel|Equal11~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal11~2_combout\ = ( !\myVirtualToplevel|RESET_COUNTER_RX\(14) & ( (!\myVirtualToplevel|RESET_COUNTER_RX\(8) & (!\myVirtualToplevel|RESET_COUNTER_RX\(13) & !\myVirtualToplevel|RESET_COUNTER_RX\(11))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(8), + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(13), + datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(11), + dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(14), + combout => \myVirtualToplevel|Equal11~2_combout\); + +-- Location: LABCELL_X10_Y4_N0 +\myVirtualToplevel|Equal11~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal11~4_combout\ = ( \myVirtualToplevel|Equal11~0_combout\ & ( (\myVirtualToplevel|Equal11~2_combout\ & (\myVirtualToplevel|Equal11~3_combout\ & \myVirtualToplevel|Equal11~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_Equal11~2_combout\, + datac => \myVirtualToplevel|ALT_INV_Equal11~3_combout\, + datad => \myVirtualToplevel|ALT_INV_Equal11~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_Equal11~0_combout\, + combout => \myVirtualToplevel|Equal11~4_combout\); + +-- Location: MLABCELL_X9_Y4_N51 +\myVirtualToplevel|RESET_COUNTER[0]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[0]~7_combout\ = !\myVirtualToplevel|RESET_COUNTER\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(0), + combout => \myVirtualToplevel|RESET_COUNTER[0]~7_combout\); + +-- Location: FF_X9_Y4_N52 +\myVirtualToplevel|RESET_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[0]~7_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(0)); + +-- Location: LABCELL_X12_Y4_N0 +\myVirtualToplevel|Add2~62\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~62_cout\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(0), + cin => GND, + cout => \myVirtualToplevel|Add2~62_cout\); + +-- Location: LABCELL_X12_Y4_N3 +\myVirtualToplevel|Add2~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~25_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add2~62_cout\ )) +-- \myVirtualToplevel|Add2~26\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add2~62_cout\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(1), + cin => \myVirtualToplevel|Add2~62_cout\, + sumout => \myVirtualToplevel|Add2~25_sumout\, + cout => \myVirtualToplevel|Add2~26\); + +-- Location: LABCELL_X12_Y4_N51 +\myVirtualToplevel|RESET_COUNTER[1]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[1]~6_combout\ = !\myVirtualToplevel|Add2~25_sumout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Add2~25_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[1]~6_combout\); + +-- Location: FF_X12_Y4_N53 +\myVirtualToplevel|RESET_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[1]~6_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(1)); + +-- Location: LABCELL_X12_Y4_N6 +\myVirtualToplevel|Add2~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~21_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add2~26\ )) +-- \myVirtualToplevel|Add2~22\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add2~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(2), + cin => \myVirtualToplevel|Add2~26\, + sumout => \myVirtualToplevel|Add2~21_sumout\, + cout => \myVirtualToplevel|Add2~22\); + +-- Location: LABCELL_X12_Y4_N54 +\myVirtualToplevel|RESET_COUNTER[2]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[2]~5_combout\ = ( !\myVirtualToplevel|Add2~21_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_Add2~21_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[2]~5_combout\); + +-- Location: FF_X12_Y4_N56 +\myVirtualToplevel|RESET_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[2]~5_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(2)); + +-- Location: LABCELL_X12_Y4_N9 +\myVirtualToplevel|Add2~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~17_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add2~22\ )) +-- \myVirtualToplevel|Add2~18\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add2~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(3), + cin => \myVirtualToplevel|Add2~22\, + sumout => \myVirtualToplevel|Add2~17_sumout\, + cout => \myVirtualToplevel|Add2~18\); + +-- Location: LABCELL_X12_Y4_N48 +\myVirtualToplevel|RESET_COUNTER[3]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[3]~4_combout\ = ( !\myVirtualToplevel|Add2~17_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_Add2~17_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[3]~4_combout\); + +-- Location: FF_X12_Y4_N50 +\myVirtualToplevel|RESET_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[3]~4_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(3)); + +-- Location: LABCELL_X12_Y4_N12 +\myVirtualToplevel|Add2~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~13_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add2~18\ )) +-- \myVirtualToplevel|Add2~14\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add2~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(4), + cin => \myVirtualToplevel|Add2~18\, + sumout => \myVirtualToplevel|Add2~13_sumout\, + cout => \myVirtualToplevel|Add2~14\); + +-- Location: MLABCELL_X13_Y4_N39 +\myVirtualToplevel|RESET_COUNTER[4]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[4]~3_combout\ = !\myVirtualToplevel|Add2~13_sumout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Add2~13_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[4]~3_combout\); + +-- Location: FF_X13_Y4_N41 +\myVirtualToplevel|RESET_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[4]~3_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(4)); + +-- Location: LABCELL_X12_Y4_N15 +\myVirtualToplevel|Add2~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~9_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add2~14\ )) +-- \myVirtualToplevel|Add2~10\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add2~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(5), + cin => \myVirtualToplevel|Add2~14\, + sumout => \myVirtualToplevel|Add2~9_sumout\, + cout => \myVirtualToplevel|Add2~10\); + +-- Location: MLABCELL_X13_Y4_N36 +\myVirtualToplevel|RESET_COUNTER[5]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[5]~2_combout\ = ( !\myVirtualToplevel|Add2~9_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_Add2~9_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[5]~2_combout\); + +-- Location: FF_X13_Y4_N38 +\myVirtualToplevel|RESET_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[5]~2_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(5)); + +-- Location: LABCELL_X12_Y4_N18 +\myVirtualToplevel|Add2~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~5_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add2~10\ )) +-- \myVirtualToplevel|Add2~6\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add2~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(6), + cin => \myVirtualToplevel|Add2~10\, + sumout => \myVirtualToplevel|Add2~5_sumout\, + cout => \myVirtualToplevel|Add2~6\); + +-- Location: MLABCELL_X13_Y4_N6 +\myVirtualToplevel|RESET_COUNTER[6]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[6]~1_combout\ = ( !\myVirtualToplevel|Add2~5_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_Add2~5_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[6]~1_combout\); + +-- Location: FF_X13_Y4_N8 +\myVirtualToplevel|RESET_COUNTER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[6]~1_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(6)); + +-- Location: LABCELL_X12_Y4_N57 +\myVirtualToplevel|Equal12~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal12~0_combout\ = ( \myVirtualToplevel|RESET_COUNTER\(1) & ( (\myVirtualToplevel|RESET_COUNTER\(3) & (\myVirtualToplevel|RESET_COUNTER\(0) & \myVirtualToplevel|RESET_COUNTER\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(3), + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(0), + datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(2), + dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(1), + combout => \myVirtualToplevel|Equal12~0_combout\); + +-- Location: LABCELL_X12_Y4_N21 +\myVirtualToplevel|Add2~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~1_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add2~6\ )) +-- \myVirtualToplevel|Add2~2\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add2~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(7), + cin => \myVirtualToplevel|Add2~6\, + sumout => \myVirtualToplevel|Add2~1_sumout\, + cout => \myVirtualToplevel|Add2~2\); + +-- Location: MLABCELL_X13_Y4_N12 +\myVirtualToplevel|RESET_COUNTER[7]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[7]~0_combout\ = !\myVirtualToplevel|Add2~1_sumout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_Add2~1_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[7]~0_combout\); + +-- Location: FF_X13_Y4_N14 +\myVirtualToplevel|RESET_COUNTER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[7]~0_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(7)); + +-- Location: MLABCELL_X13_Y4_N15 +\myVirtualToplevel|Equal12~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal12~1_combout\ = ( \myVirtualToplevel|RESET_COUNTER\(7) & ( (\myVirtualToplevel|RESET_COUNTER\(5) & (\myVirtualToplevel|RESET_COUNTER\(6) & (\myVirtualToplevel|RESET_COUNTER\(4) & \myVirtualToplevel|Equal12~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000010000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(5), + datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(6), + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(4), + datad => \myVirtualToplevel|ALT_INV_Equal12~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(7), + combout => \myVirtualToplevel|Equal12~1_combout\); + +-- Location: LABCELL_X12_Y4_N24 +\myVirtualToplevel|Add2~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~57_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add2~2\ )) +-- \myVirtualToplevel|Add2~58\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add2~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(8), + cin => \myVirtualToplevel|Add2~2\, + sumout => \myVirtualToplevel|Add2~57_sumout\, + cout => \myVirtualToplevel|Add2~58\); + +-- Location: MLABCELL_X13_Y4_N33 +\myVirtualToplevel|RESET_COUNTER[8]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[8]~15_combout\ = ( !\myVirtualToplevel|Add2~57_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_Add2~57_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[8]~15_combout\); + +-- Location: FF_X13_Y4_N35 +\myVirtualToplevel|RESET_COUNTER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[8]~15_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(8)); + +-- Location: LABCELL_X12_Y4_N27 +\myVirtualToplevel|Add2~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~53_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add2~58\ )) +-- \myVirtualToplevel|Add2~54\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add2~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(9), + cin => \myVirtualToplevel|Add2~58\, + sumout => \myVirtualToplevel|Add2~53_sumout\, + cout => \myVirtualToplevel|Add2~54\); + +-- Location: MLABCELL_X13_Y4_N0 +\myVirtualToplevel|RESET_COUNTER[9]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[9]~14_combout\ = !\myVirtualToplevel|Add2~53_sumout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_Add2~53_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[9]~14_combout\); + +-- Location: FF_X13_Y4_N2 +\myVirtualToplevel|RESET_COUNTER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[9]~14_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(9)); + +-- Location: LABCELL_X12_Y4_N30 +\myVirtualToplevel|Add2~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~41_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|Add2~54\ )) +-- \myVirtualToplevel|Add2~42\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|Add2~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(10), + cin => \myVirtualToplevel|Add2~54\, + sumout => \myVirtualToplevel|Add2~41_sumout\, + cout => \myVirtualToplevel|Add2~42\); + +-- Location: MLABCELL_X13_Y4_N54 +\myVirtualToplevel|RESET_COUNTER[10]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[10]~11_combout\ = ( !\myVirtualToplevel|Add2~41_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_Add2~41_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[10]~11_combout\); + +-- Location: FF_X13_Y4_N56 +\myVirtualToplevel|RESET_COUNTER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[10]~11_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(10)); + +-- Location: LABCELL_X12_Y4_N33 +\myVirtualToplevel|Add2~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~37_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add2~42\ )) +-- \myVirtualToplevel|Add2~38\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add2~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(11), + cin => \myVirtualToplevel|Add2~42\, + sumout => \myVirtualToplevel|Add2~37_sumout\, + cout => \myVirtualToplevel|Add2~38\); + +-- Location: MLABCELL_X13_Y4_N45 +\myVirtualToplevel|RESET_COUNTER[11]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[11]~10_combout\ = !\myVirtualToplevel|Add2~37_sumout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_Add2~37_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[11]~10_combout\); + +-- Location: FF_X13_Y4_N46 +\myVirtualToplevel|RESET_COUNTER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[11]~10_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(11)); + +-- Location: LABCELL_X12_Y4_N36 +\myVirtualToplevel|Add2~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~49_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|Add2~38\ )) +-- \myVirtualToplevel|Add2~50\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|Add2~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(12), + cin => \myVirtualToplevel|Add2~38\, + sumout => \myVirtualToplevel|Add2~49_sumout\, + cout => \myVirtualToplevel|Add2~50\); + +-- Location: MLABCELL_X13_Y4_N30 +\myVirtualToplevel|RESET_COUNTER[12]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[12]~13_combout\ = ( !\myVirtualToplevel|Add2~49_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_Add2~49_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[12]~13_combout\); + +-- Location: FF_X13_Y4_N32 +\myVirtualToplevel|RESET_COUNTER[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[12]~13_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(12)); + +-- Location: LABCELL_X12_Y4_N39 +\myVirtualToplevel|Add2~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~45_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|Add2~50\ )) +-- \myVirtualToplevel|Add2~46\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|Add2~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(13), + cin => \myVirtualToplevel|Add2~50\, + sumout => \myVirtualToplevel|Add2~45_sumout\, + cout => \myVirtualToplevel|Add2~46\); + +-- Location: MLABCELL_X13_Y4_N48 +\myVirtualToplevel|RESET_COUNTER[13]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[13]~12_combout\ = ( !\myVirtualToplevel|Add2~45_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_Add2~45_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[13]~12_combout\); + +-- Location: FF_X13_Y4_N50 +\myVirtualToplevel|RESET_COUNTER[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[13]~12_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(13)); + +-- Location: MLABCELL_X13_Y4_N3 +\myVirtualToplevel|Equal12~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal12~3_combout\ = ( \myVirtualToplevel|RESET_COUNTER\(8) & ( (\myVirtualToplevel|RESET_COUNTER\(13) & (\myVirtualToplevel|RESET_COUNTER\(12) & \myVirtualToplevel|RESET_COUNTER\(9))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(13), + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(12), + datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(9), + dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(8), + combout => \myVirtualToplevel|Equal12~3_combout\); + +-- Location: LABCELL_X12_Y4_N42 +\myVirtualToplevel|Add2~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~33_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(14) ) + ( VCC ) + ( \myVirtualToplevel|Add2~46\ )) +-- \myVirtualToplevel|Add2~34\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(14) ) + ( VCC ) + ( \myVirtualToplevel|Add2~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(14), + cin => \myVirtualToplevel|Add2~46\, + sumout => \myVirtualToplevel|Add2~33_sumout\, + cout => \myVirtualToplevel|Add2~34\); + +-- Location: MLABCELL_X13_Y4_N27 +\myVirtualToplevel|RESET_COUNTER[14]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[14]~9_combout\ = !\myVirtualToplevel|Add2~33_sumout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_Add2~33_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[14]~9_combout\); + +-- Location: FF_X13_Y4_N29 +\myVirtualToplevel|RESET_COUNTER[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[14]~9_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(14)); + +-- Location: LABCELL_X12_Y4_N45 +\myVirtualToplevel|Add2~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add2~29_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(15) ) + ( VCC ) + ( \myVirtualToplevel|Add2~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(15), + cin => \myVirtualToplevel|Add2~34\, + sumout => \myVirtualToplevel|Add2~29_sumout\); + +-- Location: MLABCELL_X13_Y4_N57 +\myVirtualToplevel|RESET_COUNTER[15]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_COUNTER[15]~8_combout\ = ( !\myVirtualToplevel|Add2~29_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_Add2~29_sumout\, + combout => \myVirtualToplevel|RESET_COUNTER[15]~8_combout\); + +-- Location: FF_X13_Y4_N58 +\myVirtualToplevel|RESET_COUNTER[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_COUNTER[15]~8_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_COUNTER\(15)); + +-- Location: MLABCELL_X13_Y4_N42 +\myVirtualToplevel|Equal12~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal12~2_combout\ = ( \myVirtualToplevel|RESET_COUNTER\(15) & ( (\myVirtualToplevel|RESET_COUNTER\(10) & (\myVirtualToplevel|RESET_COUNTER\(11) & \myVirtualToplevel|RESET_COUNTER\(14))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000001000000010000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(10), + datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(11), + datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(14), + dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(15), + combout => \myVirtualToplevel|Equal12~2_combout\); + +-- Location: MLABCELL_X13_Y4_N24 +\myVirtualToplevel|RESET_n~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_n~0_combout\ = ( \myVirtualToplevel|Equal12~2_combout\ & ( (!\myVirtualToplevel|Equal11~4_combout\ & (((\myVirtualToplevel|Equal12~1_combout\ & \myVirtualToplevel|Equal12~3_combout\)) # (\myVirtualToplevel|RESET_n~q\))) # +-- (\myVirtualToplevel|Equal11~4_combout\ & (\myVirtualToplevel|Equal12~1_combout\ & (\myVirtualToplevel|Equal12~3_combout\))) ) ) # ( !\myVirtualToplevel|Equal12~2_combout\ & ( (!\myVirtualToplevel|Equal11~4_combout\ & \myVirtualToplevel|RESET_n~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101000000011101010110000001110101011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal11~4_combout\, + datab => \myVirtualToplevel|ALT_INV_Equal12~1_combout\, + datac => \myVirtualToplevel|ALT_INV_Equal12~3_combout\, + datad => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ALT_INV_Equal12~2_combout\, + combout => \myVirtualToplevel|RESET_n~0_combout\); + +-- Location: LABCELL_X25_Y14_N12 +\myVirtualToplevel|RESET_n~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RESET_n~feeder_combout\ = ( \myVirtualToplevel|RESET_n~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_RESET_n~0_combout\, + combout => \myVirtualToplevel|RESET_n~feeder_combout\); + +-- Location: FF_X25_Y14_N14 +\myVirtualToplevel|RESET_n\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RESET_n~feeder_combout\, + clrn => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RESET_n~q\); + +-- Location: FF_X42_Y18_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)); + +-- Location: MLABCELL_X42_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0_combout\); + +-- Location: FF_X42_Y18_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\); + +-- Location: FF_X42_Y18_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\); + +-- Location: LABCELL_X36_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_0~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~54_combout\); + +-- Location: FF_X36_Y24_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~54_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0~q\); + +-- Location: LABCELL_X19_Y6_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~9_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~10\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(0), + cin => GND, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~9_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~10\); + +-- Location: LABCELL_X19_Y6_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\ = (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6) & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000100000000000000010000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(5), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(6), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(2), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\); + +-- Location: FF_X19_Y6_N2 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(0)); + +-- Location: LABCELL_X19_Y6_N3 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~5_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(1) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~10\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~6\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(1) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(1), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~10\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~5_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~6\); + +-- Location: FF_X19_Y6_N5 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(1)); + +-- Location: LABCELL_X19_Y6_N6 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~21_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~6\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~22\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(2), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~6\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~21_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~22\); + +-- Location: FF_X19_Y6_N7 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2)); + +-- Location: LABCELL_X19_Y6_N9 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~1_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~22\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~2\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(3), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~22\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~1_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~2\); + +-- Location: FF_X19_Y6_N11 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(3)); + +-- Location: LABCELL_X19_Y6_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~13_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~2\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~14\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(4), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~2\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~13_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~14\); + +-- Location: FF_X19_Y6_N14 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(4)); + +-- Location: LABCELL_X19_Y6_N15 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~25_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~14\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~26\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(5), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~14\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~25_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~26\); + +-- Location: FF_X19_Y6_N17 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5)); + +-- Location: LABCELL_X19_Y6_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~29_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~26\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~30\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(6), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~26\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~29_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~30\); + +-- Location: FF_X19_Y6_N20 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6)); + +-- Location: LABCELL_X19_Y6_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~17_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(7), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~30\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~17_sumout\); + +-- Location: FF_X19_Y6_N23 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(7)); + +-- Location: LABCELL_X19_Y6_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(3) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(7) & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(4) & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(0) & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000100000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(7), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(4), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(0), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(1), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(3), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\); + +-- Location: LABCELL_X19_Y6_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5) & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(5), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(2), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(6), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\); + +-- Location: LABCELL_X20_Y6_N15 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~5_combout\ = !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~5_combout\); + +-- Location: LABCELL_X19_Y6_N45 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5) +-- & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000100000000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(5), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(2), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(6), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\); + +-- Location: FF_X20_Y6_N17 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(0)); + +-- Location: LABCELL_X20_Y6_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30_cout\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(0), + cin => GND, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30_cout\); + +-- Location: LABCELL_X20_Y6_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~13_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(1) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30_cout\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~14\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(1) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30_cout\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(1), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30_cout\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~13_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~14\); + +-- Location: LABCELL_X20_Y6_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]~4_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~13_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~13_sumout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]~4_combout\); + +-- Location: FF_X20_Y6_N20 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(1)); + +-- Location: LABCELL_X20_Y6_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~21_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~14\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~22\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter[2]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~14\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~21_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~22\); + +-- Location: LABCELL_X20_Y6_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7_combout\ = !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~21_sumout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~21_sumout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7_combout\); + +-- Location: FF_X20_Y6_N22 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y6_N39 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~22\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~18\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(3), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~22\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~17_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~18\); + +-- Location: LABCELL_X20_Y6_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]~6_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~17_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~17_sumout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]~6_combout\); + +-- Location: FF_X20_Y6_N14 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3)); + +-- Location: LABCELL_X20_Y6_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~25_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~18\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~26\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(4), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~18\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~25_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~26\); + +-- Location: LABCELL_X20_Y6_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]~8_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~25_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~25_sumout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]~8_combout\); + +-- Location: FF_X20_Y6_N28 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]~8_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4)); + +-- Location: LABCELL_X20_Y6_N45 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~26\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~2\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(5), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~26\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~1_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~2\); + +-- Location: LABCELL_X20_Y6_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]~1_combout\ = !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~1_sumout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~1_sumout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]~1_combout\); + +-- Location: FF_X20_Y6_N26 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5)); + +-- Location: LABCELL_X20_Y6_N9 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(1) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(0) +-- & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010000000100000001000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(1), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(0), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(4), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(5), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0_combout\); + +-- Location: LABCELL_X20_Y6_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(6) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~2\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~10\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(6) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(6), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~2\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~9_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~10\); + +-- Location: LABCELL_X20_Y6_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]~3_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~9_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~9_sumout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]~3_combout\); + +-- Location: FF_X20_Y6_N56 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(6)); + +-- Location: LABCELL_X20_Y6_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(7) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(7), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~10\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~5_sumout\); + +-- Location: LABCELL_X20_Y6_N57 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]~2_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~5_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~5_sumout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]~2_combout\); + +-- Location: FF_X20_Y6_N59 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(7)); + +-- Location: FF_X20_Y6_N23 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(2)); + +-- Location: LABCELL_X20_Y6_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(6) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(7) & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010000000100000001000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(6), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(7), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(2), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(3), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~1_combout\); + +-- Location: LABCELL_X19_Y6_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~0_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~1_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1_combout\); + +-- Location: MLABCELL_X23_Y14_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~feeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~1_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~feeder_combout\); + +-- Location: FF_X23_Y14_N53 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~feeder_combout\, + asdata => VCC, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\); + +-- Location: MLABCELL_X23_Y14_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( \myVirtualToplevel|RESET_n~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\); + +-- Location: MLABCELL_X23_Y14_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\ & ( \myVirtualToplevel|RESET_n~q\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\ & \myVirtualToplevel|RESET_n~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~3_combout\, + datad => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~1_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\); + +-- Location: LABCELL_X20_Y4_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~45_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~46\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(0), + cin => GND, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~45_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~46\); + +-- Location: LABCELL_X21_Y8_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~feeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~feeder_combout\); + +-- Location: MLABCELL_X23_Y11_N15 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0_combout\ = ( \myVirtualToplevel|RESET_n~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0_combout\); + +-- Location: FF_X21_Y8_N25 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~feeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\); + +-- Location: FF_X18_Y6_N50 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~13_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(4)); + +-- Location: MLABCELL_X18_Y6_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(4) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(4), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12_combout\); + +-- Location: FF_X20_Y4_N10 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(3)); + +-- Location: LABCELL_X20_Y4_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(4) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(6) & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(3)) # +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(5)) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(2))))) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(4) & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111000001111000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(3), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(5), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(6), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(2), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(4), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\); + +-- Location: LABCELL_X20_Y4_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(8) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(7) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(7), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(8), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\); + +-- Location: LABCELL_X19_Y4_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\ & +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111010100011111111101010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~5_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~3_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~4_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\); + +-- Location: FF_X18_Y6_N56 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~15_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(3)); + +-- Location: FF_X18_Y6_N14 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y6_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(3)) # ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101111000000001111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(3), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\); + +-- Location: LABCELL_X20_Y4_N45 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\ = (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100001101000011010000110100001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~3_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~4_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~5_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\); + +-- Location: MLABCELL_X18_Y9_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001111111111001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~0_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~1_combout\); + +-- Location: FF_X20_Y8_N26 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\); + +-- Location: LABCELL_X20_Y8_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16_combout\); + +-- Location: FF_X21_Y18_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_NEW_REG989\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM990\); + +-- Location: LABCELL_X10_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~5_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~5_combout\); + +-- Location: LABCELL_X24_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~6\); + +-- Location: LABCELL_X24_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~10\); + +-- Location: MLABCELL_X23_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~20_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~20_combout\); + +-- Location: FF_X25_Y19_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]_OTERM3317\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~14\); + +-- Location: FF_X10_Y37_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|state~31_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\); + +-- Location: FF_X10_Y37_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|state~25_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~q\); + +-- Location: LABCELL_X10_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|state~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|state~25_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010111111111010101011111111101010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~25_combout\); + +-- Location: FF_X10_Y37_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|state~25_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y37_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|state~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|state~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010111111111010101011111111100000000101010100000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~31_combout\); + +-- Location: FF_X10_Y37_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|state~31_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\); + +-- Location: MLABCELL_X34_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001011111111001000100000000000000000111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr195~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\); + +-- Location: LABCELL_X20_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ = ( \myVirtualToplevel|RESET_n~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\); + +-- Location: MLABCELL_X34_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\); + +-- Location: FF_X34_Y19_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1684~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(14)); + +-- Location: LABCELL_X35_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~34\); + +-- Location: LABCELL_X35_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~38\); + +-- Location: FF_X34_Y19_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1685~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\); + +-- Location: LABCELL_X35_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~62\); + +-- Location: LABCELL_X35_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~66\); + +-- Location: LABCELL_X35_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~34\); + +-- Location: LABCELL_X35_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~38\); + +-- Location: MLABCELL_X34_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1685~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1685~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~37_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add56~37_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~37_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add56~37_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~37_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~37_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1685~0_combout\); + +-- Location: FF_X34_Y19_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1685~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(13)); + +-- Location: LABCELL_X35_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(14), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~42\); + +-- Location: LABCELL_X35_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~42\); + +-- Location: MLABCELL_X34_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1684~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1684~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~41_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~41_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111111111111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~41_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~41_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1684~0_combout\); + +-- Location: FF_X34_Y19_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1684~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\); + +-- Location: LABCELL_X35_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~46\); + +-- Location: LABCELL_X35_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~46\); + +-- Location: LABCELL_X35_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1683~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1683~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~45_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~45_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add44~45_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~45_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1683~0_combout\); + +-- Location: FF_X35_Y20_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1683~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15)); + +-- Location: LABCELL_X35_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~2\); + +-- Location: MLABCELL_X34_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~1_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~1_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000011000011110000001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~0_combout\); + +-- Location: LABCELL_X35_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~2\); + +-- Location: MLABCELL_X34_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]~feeder_combout\ = VCC + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]~feeder_combout\); + +-- Location: MLABCELL_X34_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]~feeder_combout\ = VCC + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]~feeder_combout\); + +-- Location: FF_X34_Y19_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(16)); + +-- Location: MLABCELL_X34_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]~feeder_combout\ = VCC + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]~feeder_combout\); + +-- Location: FF_X34_Y19_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(11)); + +-- Location: MLABCELL_X34_Y19_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(16) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_EndAddr\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_EndAddr\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0_combout\); + +-- Location: FF_X34_Y20_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr\(16)); + +-- Location: MLABCELL_X34_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr\(16)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100110011001111110011001100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_StartAddr\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2_combout\); + +-- Location: MLABCELL_X34_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Add56~1_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101011111010101010101111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~3_combout\); + +-- Location: FF_X34_Y20_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~3_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16)); + +-- Location: LABCELL_X35_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~22\); + +-- Location: FF_X35_Y20_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1681~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE_q\); + +-- Location: LABCELL_X35_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[17]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~22\); + +-- Location: LABCELL_X35_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1681~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1681~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~21_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add44~21_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~21_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1681~0_combout\); + +-- Location: FF_X35_Y20_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1681~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(17)); + +-- Location: LABCELL_X35_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[18]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~26\); + +-- Location: FF_X35_Y20_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1680~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(18)); + +-- Location: LABCELL_X35_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~26\); + +-- Location: LABCELL_X35_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1680~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1680~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~25_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add44~25_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1680~0_combout\); + +-- Location: FF_X35_Y20_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1680~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE_q\); + +-- Location: LABCELL_X35_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~30\); + +-- Location: LABCELL_X35_Y19_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~30\); + +-- Location: MLABCELL_X34_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1679~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1679~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~29_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~29_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010001110111011101110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~29_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1679~0_combout\); + +-- Location: FF_X34_Y19_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1679~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19)); + +-- Location: FF_X17_Y17_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~58_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~q\); + +-- Location: LABCELL_X17_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~57_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) # +-- (\myVirtualToplevel|MEM_BUSY~1_combout\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011011111111111111101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~57_combout\); + +-- Location: FF_X25_Y19_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]_OTERM3311\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23)); + +-- Location: MLABCELL_X28_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[22]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~10\); + +-- Location: MLABCELL_X28_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(23), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\); + +-- Location: LABCELL_X25_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]_NEW3310\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]_OTERM3311\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000110111001101110000010011000100111101111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]_OTERM3311\); + +-- Location: FF_X25_Y19_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]_OTERM3311\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~90\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~86\); + +-- Location: LABCELL_X24_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~62\); + +-- Location: LABCELL_X21_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~104\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~104_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010100000101000000000000000000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~104_combout\); + +-- Location: LABCELL_X25_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~105\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~105_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010000000000000101000000000010111110000000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~61_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~105_combout\); + +-- Location: FF_X17_Y18_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\); + +-- Location: FF_X16_Y13_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]_OTERM3345\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23)); + +-- Location: MLABCELL_X18_Y14_N33 +\myVirtualToplevel|MEM_DATA_READ[2]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) & !\myVirtualToplevel|LessThan0~0_combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(23), + datad => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\); + +-- Location: FF_X28_Y26_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~34_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)); + +-- Location: FF_X25_Y26_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~2\); + +-- Location: LABCELL_X24_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~42\); + +-- Location: LABCELL_X29_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\); + +-- Location: LABCELL_X25_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011101000000000001110111111111000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~41_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\); + +-- Location: FF_X25_Y24_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]_OTERM3278\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\); + +-- Location: FF_X26_Y26_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]_OTERM3281\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(9)); + +-- Location: FF_X26_Y26_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]_OTERM3263\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(3)); + +-- Location: LABCELL_X17_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & +-- !\myVirtualToplevel|MEM_BUSY~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000100000001000000000000000000000001000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\); + +-- Location: FF_X16_Y15_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\); + +-- Location: LABCELL_X16_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\); + +-- Location: LABCELL_X16_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001110000001100110111011100000000000000000011001101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~1_combout\); + +-- Location: FF_X16_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~q\); + +-- Location: LABCELL_X26_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]_NEW3259\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]_OTERM3260\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2)))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011011111000000101101111100010011110011100001001111001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]_OTERM3260\); + +-- Location: FF_X26_Y26_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]_OTERM3260\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2)); + +-- Location: MLABCELL_X28_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~q\ ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2), + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~86\); + +-- Location: MLABCELL_X28_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~82\); + +-- Location: LABCELL_X26_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]_NEW3262\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]_OTERM3263\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(3))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add3~81_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]_OTERM3263\); + +-- Location: FF_X26_Y26_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]_OTERM3263\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~50\); + +-- Location: FF_X26_Y26_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]_OTERM3287\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(4)); + +-- Location: LABCELL_X26_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]_NEW3286\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]_OTERM3287\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(4))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~49_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add3~49_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~49_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]_OTERM3287\); + +-- Location: FF_X26_Y26_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]_OTERM3287\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~54\); + +-- Location: FF_X25_Y22_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]_OTERM3284\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5)); + +-- Location: LABCELL_X25_Y22_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]_NEW3283\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]_OTERM3284\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~53_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~53_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~53_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]_OTERM3284\); + +-- Location: FF_X25_Y22_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]_OTERM3284\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(6), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~70\); + +-- Location: LABCELL_X26_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]_NEW3271\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]_OTERM3272\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add3~69_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~69_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]_OTERM3272\); + +-- Location: FF_X26_Y26_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]_OTERM3272\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6)); + +-- Location: MLABCELL_X28_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~74\); + +-- Location: LABCELL_X26_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]_NEW3268\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]_OTERM3269\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~73_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add3~73_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111110001000000011111000100001011111110110000101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~73_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]_OTERM3269\); + +-- Location: FF_X26_Y26_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]_OTERM3269\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)); + +-- Location: MLABCELL_X28_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~78\); + +-- Location: LABCELL_X26_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]_NEW3265\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]_OTERM3266\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add3~77_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~77_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]_OTERM3266\); + +-- Location: FF_X26_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]_OTERM3266\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8)); + +-- Location: FF_X26_Y26_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]_OTERM3269\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\); + +-- Location: FF_X26_Y26_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]_OTERM3272\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\); + +-- Location: FF_X25_Y26_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5)); + +-- Location: FF_X26_Y26_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]_OTERM3260\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~42\); + +-- Location: LABCELL_X26_Y26_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~46\); + +-- Location: LABCELL_X26_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[2]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~50\); + +-- Location: LABCELL_X26_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~38\); + +-- Location: LABCELL_X26_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(4) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~30\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(4) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~30\); + +-- Location: LABCELL_X26_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~34\); + +-- Location: LABCELL_X26_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~89_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~90\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~89_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~90\); + +-- Location: LABCELL_X26_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~93_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~94\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~90\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~93_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~94\); + +-- Location: LABCELL_X26_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~94\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~94\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~94\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~74\); + +-- Location: LABCELL_X26_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(9) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(9) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~78\); + +-- Location: LABCELL_X26_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~82\); + +-- Location: FF_X25_Y24_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]_OTERM3275\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~58\); + +-- Location: MLABCELL_X28_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~62\); + +-- Location: MLABCELL_X28_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~66\); + +-- Location: LABCELL_X21_Y26_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\); + +-- Location: MLABCELL_X18_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111011111111111111111111111111111111111011111101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\); + +-- Location: MLABCELL_X18_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100100000000000000000000000001000000001010010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\); + +-- Location: LABCELL_X21_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100001100111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\); + +-- Location: LABCELL_X21_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100110011000000110001001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~24_RESYN8923_BDD8924\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\); + +-- Location: FF_X23_Y25_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~102_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11)); + +-- Location: LABCELL_X24_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~26\); + +-- Location: LABCELL_X24_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~46\); + +-- Location: FF_X23_Y23_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~87_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10)); + +-- Location: LABCELL_X24_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~58\); + +-- Location: MLABCELL_X23_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~100\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~100_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\))) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100000001000000010000000111000001110000011100000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~57_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~100_combout\); + +-- Location: MLABCELL_X23_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~99\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~99_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001010000010100001111000011110000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~57_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~99_combout\); + +-- Location: LABCELL_X17_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000000000000000000000000000000000000000000000000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\); + +-- Location: LABCELL_X20_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~feeder_combout\); + +-- Location: LABCELL_X7_Y18_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~1_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100100010001100110010001000110011001000100011001100100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~1_combout\); + +-- Location: FF_X12_Y35_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1152\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\); + +-- Location: LABCELL_X16_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\); + +-- Location: LABCELL_X16_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000000000000000000000000000000000000000000000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\); + +-- Location: MLABCELL_X4_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111111111111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\); + +-- Location: FF_X4_Y33_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1)); + +-- Location: FF_X4_Y33_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(3)); + +-- Location: LABCELL_X19_Y37_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\); + +-- Location: LABCELL_X16_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|divStart~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divStart~1_combout\); + +-- Location: LABCELL_X14_Y10_N0 +\~GND\ : cyclonev_lcell_comb +-- Equation(s): +-- \~GND~combout\ = GND + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + combout => \~GND~combout\); + +-- Location: FF_X16_Y29_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|divStart\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divStart~1_combout\, + asdata => \~GND~combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\); + +-- Location: LABCELL_X2_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\); + +-- Location: FF_X4_Y33_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2)); + +-- Location: MLABCELL_X4_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000111111000000000011111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\); + +-- Location: FF_X14_Y32_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|divComplete\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\); + +-- Location: MLABCELL_X4_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\ & \myVirtualToplevel|RESET_n~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000010100000101000000000000011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~2_combout\, + datac => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\); + +-- Location: FF_X4_Y33_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(0)); + +-- Location: MLABCELL_X4_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101011110000000010101111000000001111111101010000111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~5_combout\); + +-- Location: FF_X4_Y33_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0)); + +-- Location: FF_X4_Y33_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\); + +-- Location: MLABCELL_X4_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1))))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110111110111000011011111011100001000111100100000100011110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]~4_combout\); + +-- Location: FF_X4_Y33_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1)); + +-- Location: MLABCELL_X4_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\); + +-- Location: MLABCELL_X4_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010001010100111111101010111000000001010100011111101110101011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]~7_combout\); + +-- Location: FF_X4_Y33_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2)); + +-- Location: MLABCELL_X4_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add59~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011101110111011101110111011110001000100010001000100010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\); + +-- Location: MLABCELL_X4_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000011100000010111111011111100000000101000000001111111111111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add59~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]~6_combout\); + +-- Location: FF_X4_Y33_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3)); + +-- Location: MLABCELL_X4_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\); + +-- Location: MLABCELL_X4_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000111111111111000000000111000000001111110111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~3_combout\); + +-- Location: FF_X4_Y33_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4)); + +-- Location: MLABCELL_X4_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add61~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add61~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add61~0_combout\); + +-- Location: MLABCELL_X4_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add61~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5) & !\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add61~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5) +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101011101010011010101110101001101011011010100110101101101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add61~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]~2_combout\); + +-- Location: FF_X4_Y33_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5)); + +-- Location: MLABCELL_X4_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5) & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\)) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010000000000000101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\); + +-- Location: LABCELL_X14_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110011000000001111001111111111111100111111111111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~1_combout\); + +-- Location: FF_X14_Y32_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\); + +-- Location: LABCELL_X10_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000000000000000000000000000000000000000000000000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27_combout\); + +-- Location: LABCELL_X10_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|state~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|state~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010000000100000000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~27_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~26_combout\); + +-- Location: LABCELL_X10_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|state~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|state~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|state~26_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111101011111010100110011001100111111011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~27_combout\); + +-- Location: FF_X10_Y33_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|state~27_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\); + +-- Location: FF_X25_Y29_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~76_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)); + +-- Location: FF_X26_Y23_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]_OTERM3314\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~74\); + +-- Location: LABCELL_X24_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~70\); + +-- Location: FF_X26_Y21_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~117_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\); + +-- Location: FF_X24_Y21_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~92_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)); + +-- Location: MLABCELL_X28_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~34\); + +-- Location: FF_X25_Y24_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]_OTERM3299\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12)); + +-- Location: LABCELL_X25_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]_NEW3298\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]_OTERM3299\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~33_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]_OTERM3299\); + +-- Location: FF_X25_Y24_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]_OTERM3299\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~38\); + +-- Location: LABCELL_X25_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]_NEW3295\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]_OTERM3296\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~37_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~37_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~37_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]_OTERM3296\); + +-- Location: FF_X25_Y24_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]_OTERM3296\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)); + +-- Location: MLABCELL_X28_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~42\); + +-- Location: MLABCELL_X28_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~46\); + +-- Location: LABCELL_X26_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]_NEW3289\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]_OTERM3290\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~45_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~45_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~45_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]_OTERM3290\); + +-- Location: FF_X26_Y24_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]_OTERM3290\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)); + +-- Location: MLABCELL_X28_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~2\); + +-- Location: LABCELL_X26_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]_NEW3322\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]_OTERM3323\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~1_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~1_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]_OTERM3323\); + +-- Location: FF_X26_Y24_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]_OTERM3323\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)); + +-- Location: MLABCELL_X28_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~22\); + +-- Location: FF_X26_Y23_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]_OTERM3308\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17)); + +-- Location: LABCELL_X26_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]_NEW3307\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]_OTERM3308\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~21_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~21_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~21_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]_OTERM3308\); + +-- Location: FF_X26_Y23_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]_OTERM3308\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~26\); + +-- Location: FF_X26_Y23_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]_OTERM3305\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18)); + +-- Location: FF_X25_Y20_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~142_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]_NEW3304\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]_OTERM3305\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add3~25_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~25_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]_OTERM3305\); + +-- Location: FF_X26_Y23_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]_OTERM3305\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~66\); + +-- Location: FF_X25_Y21_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~112_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\); + +-- Location: FF_X28_Y23_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]_OTERM1879\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15)); + +-- Location: FF_X29_Y24_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]_OTERM1897\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6)); + +-- Location: FF_X29_Y24_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]_OTERM1901\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4)); + +-- Location: MLABCELL_X28_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111111111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\); + +-- Location: LABCELL_X29_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_OTERM1905\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100011000100000010001100010000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_OTERM1905\); + +-- Location: FF_X29_Y24_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_OTERM1905\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2)); + +-- Location: MLABCELL_X28_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(2), + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~18\); + +-- Location: MLABCELL_X28_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~22\); + +-- Location: FF_X29_Y24_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]_OTERM1903\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3)); + +-- Location: LABCELL_X29_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]_NEW1902\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]_OTERM1903\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add15~21_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~21_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~21_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]_OTERM1903\); + +-- Location: FF_X29_Y24_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]_OTERM1903\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~26\); + +-- Location: LABCELL_X29_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]_NEW1900\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]_OTERM1901\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~25_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]_OTERM1901\); + +-- Location: FF_X29_Y24_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]_OTERM1901\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~30\); + +-- Location: FF_X29_Y25_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]_OTERM1899\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5)); + +-- Location: LABCELL_X29_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]_NEW1898\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]_OTERM1899\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~29_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~29_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]_OTERM1899\); + +-- Location: FF_X29_Y25_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]_OTERM1899\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~2\); + +-- Location: LABCELL_X29_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]_NEW1896\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]_OTERM1897\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~1_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]_OTERM1897\); + +-- Location: FF_X29_Y24_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]_OTERM1897\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~6\); + +-- Location: LABCELL_X29_Y24_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]_NEW1894\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]_OTERM1895\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~5_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]_OTERM1895\); + +-- Location: FF_X29_Y24_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]_OTERM1895\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7)); + +-- Location: MLABCELL_X28_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~10\); + +-- Location: MLABCELL_X28_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]_NEW1892\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]_OTERM1893\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~9_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]_OTERM1893\); + +-- Location: FF_X28_Y24_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]_OTERM1893\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8)); + +-- Location: MLABCELL_X28_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~14\); + +-- Location: LABCELL_X29_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]_NEW1890\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]_OTERM1891\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~13_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]_OTERM1891\); + +-- Location: FF_X29_Y24_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]_OTERM1891\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9)); + +-- Location: MLABCELL_X28_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~34\); + +-- Location: LABCELL_X29_Y24_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]_NEW1888\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]_OTERM1889\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~33_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~33_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]_OTERM1889\); + +-- Location: FF_X29_Y24_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]_OTERM1889\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10)); + +-- Location: MLABCELL_X28_Y24_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~38\); + +-- Location: LABCELL_X29_Y24_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]_NEW1886\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]_OTERM1887\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~37_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~37_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~37_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]_OTERM1887\); + +-- Location: FF_X29_Y24_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]_OTERM1887\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11)); + +-- Location: MLABCELL_X28_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(12), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~54\); + +-- Location: LABCELL_X29_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]_NEW1884\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]_OTERM1885\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add15~53_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~53_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~53_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]_OTERM1885\); + +-- Location: FF_X29_Y24_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]_OTERM1885\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12)); + +-- Location: MLABCELL_X28_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~58\); + +-- Location: MLABCELL_X28_Y23_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]_NEW1882\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]_OTERM1883\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add15~57_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~57_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~57_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]_OTERM1883\); + +-- Location: FF_X28_Y23_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]_OTERM1883\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13)); + +-- Location: MLABCELL_X28_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(14), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~42\); + +-- Location: MLABCELL_X28_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]_NEW1880\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]_OTERM1881\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~41_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~41_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~41_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]_OTERM1881\); + +-- Location: FF_X28_Y23_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]_OTERM1881\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14)); + +-- Location: MLABCELL_X28_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[15]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~46\); + +-- Location: MLABCELL_X28_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]_NEW1878\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]_OTERM1879\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~45_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]_OTERM1879\); + +-- Location: FF_X28_Y23_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]_OTERM1879\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~50\); + +-- Location: MLABCELL_X28_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]_NEW1876\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]_OTERM1877\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~49_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~49_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~49_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]_OTERM1877\); + +-- Location: FF_X28_Y23_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]_OTERM1877\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16)); + +-- Location: FF_X28_Y23_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]_OTERM1881\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\); + +-- Location: FF_X29_Y24_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]_OTERM1885\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~54\); + +-- Location: FF_X24_Y21_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~97_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\); + +-- Location: FF_X29_Y24_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]_OTERM1887\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\); + +-- Location: FF_X29_Y24_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]_OTERM1889\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\); + +-- Location: FF_X29_Y24_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]_OTERM1891\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\); + +-- Location: FF_X28_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~42_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(8)); + +-- Location: FF_X31_Y26_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~50_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)); + +-- Location: MLABCELL_X28_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~93_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~94\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~93_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~94\); + +-- Location: MLABCELL_X28_Y26_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~94\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~90\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~94\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~94\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~90\); + +-- Location: MLABCELL_X28_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~2\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~90\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~2\); + +-- Location: MLABCELL_X28_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~46\); + +-- Location: MLABCELL_X28_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~74\); + +-- Location: MLABCELL_X28_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~78\); + +-- Location: MLABCELL_X28_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~82\); + +-- Location: MLABCELL_X28_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~86\); + +-- Location: MLABCELL_X28_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(8) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(8) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~38\); + +-- Location: MLABCELL_X28_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~26\); + +-- Location: MLABCELL_X28_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~42\); + +-- Location: MLABCELL_X28_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~30\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~30\); + +-- Location: MLABCELL_X28_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~34\); + +-- Location: MLABCELL_X28_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~62\); + +-- Location: MLABCELL_X28_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~66\); + +-- Location: MLABCELL_X28_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[15]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~70\); + +-- Location: MLABCELL_X28_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~50\); + +-- Location: FF_X25_Y24_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~147_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\); + +-- Location: FF_X28_Y23_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]_OTERM1875\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~54\); + +-- Location: FF_X28_Y24_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]_OTERM1873\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~58\); + +-- Location: MLABCELL_X28_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~53_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~49_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~65_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~61_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~69_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~49_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~61_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~69_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~53_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\); + +-- Location: FF_X25_Y23_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]_OTERM1867\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21)); + +-- Location: FF_X28_Y24_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]_OTERM1869\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~82\); + +-- Location: MLABCELL_X28_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~86\); + +-- Location: LABCELL_X29_Y21_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]_NEW1870\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]_OTERM1871\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~85_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~85_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~85_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]_OTERM1871\); + +-- Location: FF_X29_Y21_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]_OTERM1871\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19)); + +-- Location: MLABCELL_X28_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~66\); + +-- Location: MLABCELL_X28_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~70\); + +-- Location: LABCELL_X25_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]_NEW1866\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]_OTERM1867\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~69_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~69_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]_OTERM1867\); + +-- Location: FF_X25_Y23_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]_OTERM1867\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(22), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~74\); + +-- Location: MLABCELL_X28_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]_NEW1864\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]_OTERM1865\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~73_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~73_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~73_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]_OTERM1865\); + +-- Location: FF_X28_Y23_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]_OTERM1865\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22)); + +-- Location: MLABCELL_X28_Y23_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~77_sumout\); + +-- Location: FF_X25_Y23_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]_OTERM1863\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23)); + +-- Location: LABCELL_X25_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]_NEW1862\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]_OTERM1863\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add15~77_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~77_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~77_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]_OTERM1863\); + +-- Location: FF_X25_Y23_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]_OTERM1863\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~22\); + +-- Location: MLABCELL_X28_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~10\); + +-- Location: MLABCELL_X28_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~14\); + +-- Location: MLABCELL_X28_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(22), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~18\); + +-- Location: MLABCELL_X28_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add17~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\); + +-- Location: MLABCELL_X28_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~73_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~85_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~81_sumout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~77_sumout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~85_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~81_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~77_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~73_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\); + +-- Location: LABCELL_X29_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~0_combout\); + +-- Location: LABCELL_X29_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~41_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~37_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~45_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~2_combout\); + +-- Location: LABCELL_X29_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~3_combout\); + +-- Location: LABCELL_X29_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\); + +-- Location: FF_X28_Y23_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]_OTERM1865\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\); + +-- Location: FF_X28_Y21_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]_OTERM1923\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15)); + +-- Location: FF_X29_Y22_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]_OTERM1947\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3)); + +-- Location: LABCELL_X29_Y22_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]_NEW1946\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]_OTERM1947\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111111110101111101010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]_OTERM1947\); + +-- Location: FF_X29_Y22_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]_OTERM1947\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[3]~DUPLICATE_q\, + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~18\); + +-- Location: LABCELL_X31_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~22\); + +-- Location: LABCELL_X26_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]_NEW1944\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]_OTERM1945\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~21_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]_OTERM1945\); + +-- Location: FF_X26_Y22_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]_OTERM1945\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4)); + +-- Location: LABCELL_X31_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~26\); + +-- Location: LABCELL_X26_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]_NEW1942\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]_OTERM1943\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~25_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]_OTERM1943\); + +-- Location: FF_X26_Y21_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]_OTERM1943\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5)); + +-- Location: LABCELL_X31_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~2\); + +-- Location: LABCELL_X31_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~6\); + +-- Location: FF_X26_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]_OTERM1939\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7)); + +-- Location: LABCELL_X26_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]_NEW1938\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]_OTERM1939\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~5_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~5_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]_OTERM1939\); + +-- Location: FF_X26_Y20_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]_OTERM1939\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y21_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~10\); + +-- Location: LABCELL_X26_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]_NEW1936\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]_OTERM1937\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add16~9_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]_OTERM1937\); + +-- Location: FF_X26_Y22_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]_OTERM1937\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)); + +-- Location: LABCELL_X31_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~14\); + +-- Location: LABCELL_X26_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]_NEW1934\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]_OTERM1935\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~13_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~13_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~13_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]_OTERM1935\); + +-- Location: FF_X26_Y22_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]_OTERM1935\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9)); + +-- Location: LABCELL_X31_Y21_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[10]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~30\); + +-- Location: FF_X28_Y21_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]_OTERM1933\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10)); + +-- Location: MLABCELL_X28_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]_NEW1932\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]_OTERM1933\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~29_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~29_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]_OTERM1933\); + +-- Location: FF_X28_Y21_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]_OTERM1933\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~34\); + +-- Location: FF_X28_Y21_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]_OTERM1931\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(11)); + +-- Location: MLABCELL_X28_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]_NEW1930\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]_OTERM1931\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(11))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~33_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(11))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~33_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]_OTERM1931\); + +-- Location: FF_X28_Y21_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]_OTERM1931\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~50\); + +-- Location: FF_X28_Y21_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]_OTERM1929\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12)); + +-- Location: MLABCELL_X28_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]_NEW1928\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]_OTERM1929\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~49_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~49_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~49_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]_OTERM1929\); + +-- Location: FF_X28_Y21_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]_OTERM1929\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~54\); + +-- Location: MLABCELL_X28_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]_NEW1926\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]_OTERM1927\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add16~53_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~53_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]_OTERM1927\); + +-- Location: FF_X28_Y21_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]_OTERM1927\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13)); + +-- Location: LABCELL_X31_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~38\); + +-- Location: FF_X25_Y21_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~122_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14)); + +-- Location: MLABCELL_X28_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]_NEW1924\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]_OTERM1925\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~37_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~37_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~37_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]_OTERM1925\); + +-- Location: FF_X28_Y21_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]_OTERM1925\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14)); + +-- Location: LABCELL_X31_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~42\); + +-- Location: MLABCELL_X28_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]_NEW1922\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]_OTERM1923\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~41_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add16~41_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~41_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]_OTERM1923\); + +-- Location: FF_X28_Y21_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]_OTERM1923\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[16]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~46\); + +-- Location: FF_X28_Y21_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]_OTERM1921\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)); + +-- Location: MLABCELL_X28_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]_NEW1920\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]_OTERM1921\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~45_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~45_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~45_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]_OTERM1921\); + +-- Location: FF_X28_Y21_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]_OTERM1921\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~58\); + +-- Location: MLABCELL_X28_Y22_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]_NEW1918\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]_OTERM1919\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add16~57_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]_OTERM1919\); + +-- Location: FF_X28_Y22_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]_OTERM1919\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17)); + +-- Location: LABCELL_X31_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~62\); + +-- Location: MLABCELL_X28_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]_NEW1916\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]_OTERM1917\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~61_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~61_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101111101011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~61_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]_OTERM1917\); + +-- Location: FF_X28_Y22_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]_OTERM1917\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18)); + +-- Location: LABCELL_X31_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~78\); + +-- Location: MLABCELL_X28_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]_NEW1914\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]_OTERM1915\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~77_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~77_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~77_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]_OTERM1915\); + +-- Location: FF_X28_Y22_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]_OTERM1915\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19)); + +-- Location: LABCELL_X31_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~82\); + +-- Location: LABCELL_X29_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]_NEW1912\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]_OTERM1913\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~81_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~81_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111100111111001100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~81_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]_OTERM1913\); + +-- Location: FF_X29_Y21_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]_OTERM1913\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20)); + +-- Location: LABCELL_X31_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(21), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~66\); + +-- Location: LABCELL_X29_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]_NEW1910\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]_OTERM1911\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~65_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~65_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~65_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]_OTERM1911\); + +-- Location: FF_X29_Y21_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]_OTERM1911\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21)); + +-- Location: LABCELL_X31_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(22), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~70\); + +-- Location: MLABCELL_X28_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]_NEW1908\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]_OTERM1909\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~69_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~69_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~69_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]_OTERM1909\); + +-- Location: FF_X28_Y22_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]_OTERM1909\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)); + +-- Location: FF_X29_Y21_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]_OTERM1911\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\); + +-- Location: FF_X28_Y21_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]_OTERM1927\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\); + +-- Location: FF_X29_Y24_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_OTERM1905\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y24_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]~1_combout\); + +-- Location: FF_X26_Y24_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)); + +-- Location: LABCELL_X31_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)) ) + ( !VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)) ) + ( !VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~39\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110011001100000000000000000011001111001100", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2), + cin => GND, + sharein => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~38\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~39\); + +-- Location: LABCELL_X31_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~39\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~39\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~43\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~38\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~39\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~42\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~43\); + +-- Location: LABCELL_X31_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~43\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~47\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~42\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~43\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~46\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~47\); + +-- Location: LABCELL_X31_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~47\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~47\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~51\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~46\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~47\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~50\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~51\); + +-- Location: LABCELL_X31_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~51\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~51\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~55\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~50\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~51\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~54\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~55\); + +-- Location: LABCELL_X31_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~55\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~55\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~59\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~54\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~55\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~58\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~59\); + +-- Location: LABCELL_X31_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~59\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~83\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~58\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~59\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~82\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~83\); + +-- Location: LABCELL_X31_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~85_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~83\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~86\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~83\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~87\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010000000000000000000000001010101001010101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~82\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~83\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~86\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~87\); + +-- Location: LABCELL_X31_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~87\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~87\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~63\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[10]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~86\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~87\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~62\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~63\); + +-- Location: LABCELL_X31_Y24_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~63\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~63\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~67\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~62\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~63\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~66\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~67\); + +-- Location: LABCELL_X31_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~67\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~67\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~71\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~66\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~67\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~70\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~71\); + +-- Location: LABCELL_X31_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~71\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~18\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~71\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~19\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~70\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~71\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~18\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~19\); + +-- Location: LABCELL_X31_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~21_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~19\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~22\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~19\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~18\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~23\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(14), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~18\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~19\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~22\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~23\); + +-- Location: LABCELL_X31_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~25_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~23\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~26\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~23\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~27\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~22\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~23\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~26\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~27\); + +-- Location: LABCELL_X31_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~29_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~27\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~30\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~27\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~31\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010000000000000000000000001010101001010101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[16]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~26\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~27\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~30\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~31\); + +-- Location: LABCELL_X31_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~31\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~31\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~75\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~30\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~31\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~74\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~75\); + +-- Location: LABCELL_X31_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~75\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~75\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~35\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~74\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~75\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~34\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~35\); + +-- Location: LABCELL_X31_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~35\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~35\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~34\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~79\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~34\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~35\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~78\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~79\); + +-- Location: LABCELL_X31_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(20) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~79\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~2\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(20) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~79\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~78\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~3\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(20) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~78\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~79\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~2\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~3\); + +-- Location: LABCELL_X31_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~3\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~6\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~3\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~7\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000101000000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~2\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~3\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~6\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~7\); + +-- Location: LABCELL_X31_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~7\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~10\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~7\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~11\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[22]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(22), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~6\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~7\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~10\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~11\); + +-- Location: LABCELL_X31_Y23_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add18~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~11\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~10\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~11\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\); + +-- Location: LABCELL_X29_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619_BDD8620\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~9_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619_BDD8620\); + +-- Location: LABCELL_X31_Y24_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~85_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~81_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~81_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~85_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~2_combout\); + +-- Location: LABCELL_X31_Y23_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~77_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~65_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~73_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~69_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~77_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~73_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~69_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~61_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\); + +-- Location: LABCELL_X31_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~57_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~41_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~37_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~45_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add18~49_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~41_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~37_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~45_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~49_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~57_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~53_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~0_combout\); + +-- Location: LABCELL_X31_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~33_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~29_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~17_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~21_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000100000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~33_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~29_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~17_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~21_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\); + +-- Location: LABCELL_X29_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619_BDD8620\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619_BDD8620\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000001100000000000000000000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_RESYN8619_BDD8620\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\); + +-- Location: LABCELL_X31_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add16~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~73_sumout\); + +-- Location: FF_X28_Y22_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]_OTERM1907\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23)); + +-- Location: MLABCELL_X28_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]_NEW1906\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]_OTERM1907\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~73_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~73_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~73_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]_OTERM1907\); + +-- Location: FF_X28_Y22_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]_OTERM1907\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\); + +-- Location: FF_X25_Y22_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~107_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(20)); + +-- Location: FF_X25_Y20_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]_OTERM2668\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18)); + +-- Location: FF_X25_Y20_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]_OTERM2665\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\); + +-- Location: FF_X25_Y21_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]_OTERM2656\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14)); + +-- Location: FF_X26_Y20_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]_OTERM2632\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6)); + +-- Location: LABCELL_X24_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]_NEW2625\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]_OTERM2626\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100111111001100000011111100110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]_OTERM2626\); + +-- Location: FF_X24_Y23_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]_OTERM2626\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)); + +-- Location: LABCELL_X26_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4), + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~22\); + +-- Location: LABCELL_X26_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~26\); + +-- Location: LABCELL_X25_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]_NEW2628\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]_OTERM2629\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001111100011111000100001011000010111111101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]_OTERM2629\); + +-- Location: FF_X25_Y18_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]_OTERM2629\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5)); + +-- Location: LABCELL_X26_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~18\); + +-- Location: LABCELL_X26_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]_NEW2631\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]_OTERM2632\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100111111110000110000000000001111111111111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]_OTERM2632\); + +-- Location: FF_X26_Y20_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]_OTERM2632\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~14\); + +-- Location: FF_X26_Y20_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]_OTERM2635\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7)); + +-- Location: LABCELL_X26_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]_NEW2634\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]_OTERM2635\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101111100001111010100001111000001011111111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~13_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]_OTERM2635\); + +-- Location: FF_X26_Y20_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]_OTERM2635\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~10\); + +-- Location: FF_X25_Y18_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]_OTERM2638\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8)); + +-- Location: LABCELL_X25_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]_NEW2637\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]_OTERM2638\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~9_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~9_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111100001111111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]_OTERM2638\); + +-- Location: FF_X25_Y18_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]_OTERM2638\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y18_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~6\); + +-- Location: FF_X25_Y18_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]_OTERM2641\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9)); + +-- Location: LABCELL_X25_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]_NEW2640\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]_OTERM2641\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001111100011111000100001101000011011111110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]_OTERM2641\); + +-- Location: FF_X25_Y18_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]_OTERM2641\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~30\); + +-- Location: LABCELL_X24_Y23_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]_NEW2643\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]_OTERM2644\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~29_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~29_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]_OTERM2644\); + +-- Location: FF_X24_Y23_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]_OTERM2644\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10)); + +-- Location: LABCELL_X26_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~42\); + +-- Location: FF_X24_Y21_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]_OTERM2647\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11)); + +-- Location: LABCELL_X24_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]_NEW2646\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]_OTERM2647\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~41_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~41_sumout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~41_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]_OTERM2647\); + +-- Location: FF_X24_Y21_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]_OTERM2647\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~38\); + +-- Location: FF_X24_Y21_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]_OTERM2650\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12)); + +-- Location: LABCELL_X24_Y21_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]_NEW2649\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]_OTERM2650\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~37_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~37_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]_OTERM2650\); + +-- Location: FF_X24_Y21_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]_OTERM2650\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~34\); + +-- Location: LABCELL_X24_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]_NEW2652\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]_OTERM2653\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~33_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]_OTERM2653\); + +-- Location: FF_X24_Y23_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]_OTERM2653\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13)); + +-- Location: LABCELL_X26_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~58\); + +-- Location: LABCELL_X25_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]_NEW2655\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]_OTERM2656\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add9~57_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]_OTERM2656\); + +-- Location: FF_X25_Y21_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]_OTERM2656\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y18_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~54\); + +-- Location: FF_X25_Y21_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]_OTERM2659\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15)); + +-- Location: LABCELL_X25_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]_NEW2658\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]_OTERM2659\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~53_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~53_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~53_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]_OTERM2659\); + +-- Location: FF_X25_Y21_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]_OTERM2659\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~50\); + +-- Location: FF_X25_Y21_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]_OTERM2662\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16)); + +-- Location: LABCELL_X25_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]_NEW2661\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]_OTERM2662\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~49_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~49_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]_OTERM2662\); + +-- Location: FF_X25_Y21_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]_OTERM2662\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~78\); + +-- Location: LABCELL_X26_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~74\); + +-- Location: LABCELL_X25_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]_NEW2667\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]_OTERM2668\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~73_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add9~73_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~73_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]_OTERM2668\); + +-- Location: FF_X25_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]_OTERM2668\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~70\); + +-- Location: LABCELL_X25_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]_NEW2670\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]_OTERM2671\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~69_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~69_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]_OTERM2671\); + +-- Location: FF_X25_Y20_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]_OTERM2671\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19)); + +-- Location: LABCELL_X26_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~46\); + +-- Location: LABCELL_X25_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]_NEW2673\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]_OTERM2674\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~45_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~45_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]_OTERM2674\); + +-- Location: FF_X25_Y20_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]_OTERM2674\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20)); + +-- Location: LABCELL_X26_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~66\); + +-- Location: LABCELL_X25_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]_NEW2676\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]_OTERM2677\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add9~65_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011110010000000101111001000000111111101110000011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]_OTERM2677\); + +-- Location: FF_X25_Y23_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]_OTERM2677\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)); + +-- Location: FF_X25_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]_OTERM2629\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\); + +-- Location: FF_X25_Y18_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\); + +-- Location: FF_X25_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2)); + +-- Location: LABCELL_X24_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~94\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~94_cout\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( !VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~95\ = SHARE(VCC) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + cin => GND, + sharein => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~94_cout\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~95\); + +-- Location: LABCELL_X24_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~90\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~90_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~95\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~94_cout\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~91\ = SHARE(\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111100000000000000001111111100000000", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~94_cout\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~95\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~90_cout\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~91\); + +-- Location: LABCELL_X24_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~91\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~90_cout\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~91\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~90_cout\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~51\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~90_cout\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~91\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~50\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~51\); + +-- Location: LABCELL_X24_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~51\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~51\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~39\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~50\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~51\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~38\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~39\); + +-- Location: LABCELL_X24_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~39\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~38\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~39\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~55\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~38\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~39\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~54\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~55\); + +-- Location: LABCELL_X24_Y19_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~54\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~43\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~54\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~55\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~42\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~43\); + +-- Location: LABCELL_X24_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~43\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~43\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~47\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001100110000000000000000001100110000110011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~42\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~43\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~46\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~47\); + +-- Location: LABCELL_X24_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~25_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~46\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~26\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~27\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~46\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~47\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~26\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~27\); + +-- Location: LABCELL_X24_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~29_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~27\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~30\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~27\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~31\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~26\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~27\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~30\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~31\); + +-- Location: LABCELL_X24_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~31\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~31\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~35\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~30\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~31\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~34\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~35\); + +-- Location: LABCELL_X24_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~35\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~34\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~10\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~35\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~11\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~34\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~35\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~10\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~11\); + +-- Location: LABCELL_X24_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~13_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~11\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~14\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~11\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~15\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000101000000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~10\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~11\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~14\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~15\); + +-- Location: LABCELL_X24_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~15\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~15\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~59\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~14\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~15\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~58\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~59\); + +-- Location: LABCELL_X24_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~63\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~58\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~59\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~62\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~63\); + +-- Location: LABCELL_X24_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~63\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~2\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~63\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~3\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110000000000000000000000001100110000110011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~62\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~63\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~2\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~3\); + +-- Location: LABCELL_X24_Y18_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~3\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~2\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~3\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~67\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~2\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~3\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~66\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~67\); + +-- Location: LABCELL_X24_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~67\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~6\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~67\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~7\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~66\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~67\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~6\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~7\); + +-- Location: LABCELL_X24_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~7\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~7\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~71\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17) & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010100000101000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~6\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~7\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~70\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~71\); + +-- Location: LABCELL_X24_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~71\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~18\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~71\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~19\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~70\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~71\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~18\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~19\); + +-- Location: LABCELL_X24_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~21_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~19\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~18\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~22\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~19\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~23\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010000000000000000000000001010101001010101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~18\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~19\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~22\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~23\); + +-- Location: LABCELL_X24_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~23\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~22\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~23\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~75\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~22\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~23\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~74\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~75\); + +-- Location: LABCELL_X24_Y18_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~75\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~74\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~75\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~79\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~74\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~75\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~78\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~79\); + +-- Location: FF_X25_Y23_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]_OTERM2680\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22)); + +-- Location: LABCELL_X26_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(22), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~62\); + +-- Location: LABCELL_X25_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]_NEW2679\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]_OTERM2680\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add9~61_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]_OTERM2680\); + +-- Location: FF_X25_Y23_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]_OTERM2680\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~79\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~78\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~79\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~83\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(22))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~78\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~79\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~82\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~83\); + +-- Location: LABCELL_X24_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add8~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~85_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~83\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~82\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~83\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~85_sumout\); + +-- Location: LABCELL_X24_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~81_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~73_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~77_sumout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~85_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~77_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~85_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~81_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~73_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~11_combout\); + +-- Location: LABCELL_X24_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~14_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~37_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~53_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~49_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~53_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~49_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~41_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~37_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~14_combout\); + +-- Location: LABCELL_X24_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~15_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~25_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~33_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~45_sumout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~45_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~15_combout\); + +-- Location: LABCELL_X24_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~61_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~57_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~13_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~15_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~61_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~57_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000000000100011000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~13_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~61_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~57_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~13_combout\); + +-- Location: LABCELL_X24_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~21_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~5_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~65_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~69_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~13_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~69_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~21_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~0_combout\); + +-- Location: MLABCELL_X23_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010101011111010111100000000000000001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~9_combout\); + +-- Location: MLABCELL_X28_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000000010100000000000011110101111100001111010111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~9_combout\); + +-- Location: FF_X25_Y20_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]_OTERM2671\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\); + +-- Location: FF_X25_Y20_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]_OTERM2674\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010010100000000101001010000000000000000101001010000000010100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[19]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[20]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~1_combout\); + +-- Location: LABCELL_X25_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000000000001111000000001111000000000000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\); + +-- Location: LABCELL_X25_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2_combout\); + +-- Location: LABCELL_X26_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111100000000101011110000000000000000101011110000000010101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~3_combout\); + +-- Location: MLABCELL_X28_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\); + +-- Location: LABCELL_X29_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000000000000000001100110000110011000000000000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\); + +-- Location: MLABCELL_X28_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000000001100000000000011110011111100001111001111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\); + +-- Location: MLABCELL_X28_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000100000000001111110100000000010000000000000011011100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8_combout\); + +-- Location: LABCELL_X32_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\)))) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011001100111100001111111101000000010001001101000011011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\); + +-- Location: MLABCELL_X28_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000011001111000011001100111100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11_combout\); + +-- Location: MLABCELL_X28_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000001010000101000000101000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~10_combout\); + +-- Location: LABCELL_X24_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101010000000011110101111100001111010111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13_combout\); + +-- Location: MLABCELL_X28_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111001111111111000000001111001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\); + +-- Location: FF_X25_Y18_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110011000000111111001100000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\); + +-- Location: MLABCELL_X28_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5)) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001000000110111001101110011000100110001001111110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\); + +-- Location: LABCELL_X24_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000001010101000000000101001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\); + +-- Location: MLABCELL_X28_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001010000010100000100000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\); + +-- Location: MLABCELL_X28_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000111100001111000011110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~18_combout\); + +-- Location: LABCELL_X25_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111100001111010111110000111100000101000000000000010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\); + +-- Location: LABCELL_X26_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010101100101011001010110010101100100010001000100010001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\); + +-- Location: LABCELL_X25_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000010101111000000000000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8_combout\); + +-- Location: LABCELL_X31_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010001000000000001000100010101010111011101010101011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4_combout\); + +-- Location: LABCELL_X31_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001000000000000000000001001000010011001000000000000000010011001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~2_combout\); + +-- Location: LABCELL_X26_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001100000000110000110000000000000000110000110000000011000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~0_combout\); + +-- Location: LABCELL_X25_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000000011110000000000000000111100000000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\); + +-- Location: LABCELL_X32_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001010101001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1_combout\); + +-- Location: LABCELL_X26_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111101010101001111110001010100110011000100010000001100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\); + +-- Location: LABCELL_X29_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14)) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000111111111100111100111111111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~4_combout\); + +-- Location: FF_X26_Y26_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]_OTERM3266\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\); + +-- Location: LABCELL_X32_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011111110111010101010111010100010001010100010000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~9_combout\); + +-- Location: LABCELL_X29_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010111111110010001010111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12_combout\); + +-- Location: LABCELL_X25_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)))) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000001010000010100000101000001001000001010000010100000101000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\); + +-- Location: LABCELL_X31_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011010000000011011101000000001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~10_combout\); + +-- Location: LABCELL_X25_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001111110011001100111111001100000000001100000000000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5_combout\); + +-- Location: LABCELL_X25_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010010100000000101001010000000000000000101001010000000010100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7_combout\); + +-- Location: LABCELL_X32_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111001101010001111100110101000101010001000000001111001101010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5_combout\); + +-- Location: LABCELL_X32_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000011110101111100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6_combout\); + +-- Location: LABCELL_X31_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111000111010001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8_combout\); + +-- Location: LABCELL_X31_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010100011100000101010001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11_combout\); + +-- Location: LABCELL_X31_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000100110001001100110011001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13_combout\); + +-- Location: FF_X26_Y23_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]_OTERM3302\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(19)); + +-- Location: LABCELL_X26_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(19)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(19) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110011001111000011001100111100000000110011000000000011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2_combout\); + +-- Location: LABCELL_X25_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011100110011011101110011001100010001000000000001000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1_combout\); + +-- Location: LABCELL_X26_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(21) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(21) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2_combout\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011010100000000001101010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3_combout\); + +-- Location: LABCELL_X31_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~4_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111000111110101111101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5_combout\); + +-- Location: MLABCELL_X28_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~18_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000011110011111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\); + +-- Location: FF_X25_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(3)); + +-- Location: LABCELL_X25_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) ) + ( !VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) ) + ( !VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~35\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000111100000000000000000000111111110000", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[2]~DUPLICATE_q\, + cin => GND, + sharein => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~34\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~35\); + +-- Location: LABCELL_X25_Y18_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(3) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~35\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(3) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~35\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~39\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001010101000000000000000001010101001010101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~34\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~35\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~38\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~39\); + +-- Location: LABCELL_X25_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~21_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~39\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~22\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~39\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~23\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~38\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~39\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~22\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~23\); + +-- Location: LABCELL_X25_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~23\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~23\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~43\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010001000100010000000000000000001001100110011001", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~22\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~23\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~42\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~43\); + +-- Location: LABCELL_X25_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~25_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~43\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~26\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~43\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~27\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~42\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~43\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~26\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~27\); + +-- Location: LABCELL_X25_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~27\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~26\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~27\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~47\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010100000101000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~26\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~27\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~46\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~47\); + +-- Location: LABCELL_X25_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~46\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~71\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010100000101000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~46\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~47\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~70\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~71\); + +-- Location: LABCELL_X25_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~71\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~71\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~75\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~70\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~71\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~74\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~75\); + +-- Location: LABCELL_X25_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~75\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~75\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~79\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010100000101000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~74\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~75\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~78\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~79\); + +-- Location: LABCELL_X25_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~79\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~79\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~83\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~78\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~79\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~82\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~83\); + +-- Location: LABCELL_X25_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~85_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~83\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~86\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~83\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~87\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010100000101000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~82\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~83\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~86\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~87\); + +-- Location: LABCELL_X25_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~87\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~86\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~6\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~87\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~7\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~86\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~87\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~6\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~7\); + +-- Location: LABCELL_X25_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~29_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~7\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~30\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~7\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~31\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001010101000000000000000001010101001010101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~6\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~7\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~30\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~31\); + +-- Location: LABCELL_X25_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~31\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~10\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~31\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~11\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~30\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~31\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~10\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~11\); + +-- Location: LABCELL_X25_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~13_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~11\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~14\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~11\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~15\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000101000000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~10\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~11\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~14\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~15\); + +-- Location: LABCELL_X25_Y17_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~15\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~15\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~51\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~14\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~15\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~50\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~51\); + +-- Location: LABCELL_X25_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~51\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~18\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~51\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~19\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~50\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~51\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~18\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~19\); + +-- Location: LABCELL_X25_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~19\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~19\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~55\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010000000000000000000000001010101001010101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~18\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~19\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~54\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~55\); + +-- Location: LABCELL_X25_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~55\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~55\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~59\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~54\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~55\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~58\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~59\); + +-- Location: LABCELL_X25_Y17_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~59\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~59\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~63\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~58\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~59\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~62\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~63\); + +-- Location: LABCELL_X25_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~63\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~63\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~67\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[22]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~62\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~63\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~66\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~67\); + +-- Location: LABCELL_X25_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~67\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~66\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~67\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\); + +-- Location: LABCELL_X25_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~77_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~85_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~73_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~81_sumout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~69_sumout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~73_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~81_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~69_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~77_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~85_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1_combout\); + +-- Location: LABCELL_X26_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_RESYN12370\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_RESYN12370_BDD12371\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~29_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~41_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~45_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~37_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~41_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~21_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~45_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~37_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_RESYN12370_BDD12371\); + +-- Location: LABCELL_X25_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_RESYN12370_BDD12371\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~17_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~9_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~33_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~13_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~13_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_RESYN12370_BDD12371\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\); + +-- Location: LABCELL_X25_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~5_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~49_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100000000000100010000000000010001000000000001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~49_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~5_combout\); + +-- Location: LABCELL_X25_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~53_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~65_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~61_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~53_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~57_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~61_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\); + +-- Location: LABCELL_X25_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~11_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101010101111111111111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\); + +-- Location: LABCELL_X26_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add9~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~1_sumout\); + +-- Location: LABCELL_X25_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]_NEW2682\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]_OTERM2683\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~1_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~1_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]_OTERM2683\); + +-- Location: FF_X25_Y23_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]_OTERM2683\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23)); + +-- Location: LABCELL_X25_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111110000000011111111000000001111111100000000111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\); + +-- Location: FF_X28_Y22_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]_OTERM1917\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000001000000000010000000010000100000000100000000001000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1_combout\); + +-- Location: LABCELL_X26_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18)))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100110111111111000000000100110101000100111111110000000001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~2_combout\); + +-- Location: LABCELL_X25_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101111111111111010111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\); + +-- Location: LABCELL_X24_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111001111110011011100010111000101110001011100010011000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\); + +-- Location: LABCELL_X24_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_RESYN12470\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_RESYN12470_BDD12471\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111111111111110011111111111100000000110011110000000011001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_RESYN12470_BDD12471\); + +-- Location: LABCELL_X24_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\); + +-- Location: LABCELL_X24_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_RESYN12470_BDD12471\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001000001001000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~19_RESYN12470_BDD12471\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_combout\); + +-- Location: LABCELL_X25_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111111111100001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\); + +-- Location: LABCELL_X24_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000000000001010000011110000111110101111000011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10_combout\); + +-- Location: LABCELL_X24_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9_combout\); + +-- Location: LABCELL_X29_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15)) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000000000111111110100000011011100000000001111111111011100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11_combout\); + +-- Location: LABCELL_X24_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010000000000000000010000000101010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\); + +-- Location: LABCELL_X26_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) +-- $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010010110100101000000000000000000000000000000001010010110100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14_combout\); + +-- Location: LABCELL_X26_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688_BDD12689\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110111011101010001000100010011111111111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688_BDD12689\); + +-- Location: LABCELL_X26_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688_BDD12689\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688_BDD12689\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110111111101110101000101010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~16_RESYN12688_BDD12689\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_combout\); + +-- Location: LABCELL_X26_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4)) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111000100000000111111110111000100110000000000001111111100110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13_combout\); + +-- Location: LABCELL_X25_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111001100000000000000001111001111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\); + +-- Location: LABCELL_X24_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000110000110000000011000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~5_combout\); + +-- Location: LABCELL_X29_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011101111111111000000000011101100000010111111110000000000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~6_combout\); + +-- Location: LABCELL_X24_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001010010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\); + +-- Location: LABCELL_X24_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690_BDD12691\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000011001000110000001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~19_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690_BDD12691\); + +-- Location: LABCELL_X24_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690_BDD12691\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & (!\myVirtualToplevel|MEM_BUSY~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~4_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_RESYN12690_BDD12691\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\); + +-- Location: MLABCELL_X28_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000111111111111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\); + +-- Location: MLABCELL_X28_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add15~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~62\); + +-- Location: MLABCELL_X28_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]_NEW1874\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]_OTERM1875\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~61_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]_OTERM1875\); + +-- Location: FF_X28_Y23_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]_OTERM1875\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(17)); + +-- Location: MLABCELL_X28_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]_NEW1872\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]_OTERM1873\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add15~81_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~81_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]_OTERM1873\); + +-- Location: FF_X28_Y24_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]_OTERM1873\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18)); + +-- Location: FF_X28_Y23_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]_OTERM1877\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\); + +-- Location: LABCELL_X29_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~50\); + +-- Location: LABCELL_X29_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~46\); + +-- Location: LABCELL_X29_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~42\); + +-- Location: LABCELL_X29_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(6), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~38\); + +-- Location: LABCELL_X29_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~62\); + +-- Location: LABCELL_X29_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~58\); + +-- Location: LABCELL_X29_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~54\); + +-- Location: LABCELL_X29_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~70\); + +-- Location: LABCELL_X29_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~66\); + +-- Location: LABCELL_X29_Y24_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(12), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~34\); + +-- Location: LABCELL_X29_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~30\); + +-- Location: LABCELL_X29_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~82\); + +-- Location: LABCELL_X29_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~78\); + +-- Location: LABCELL_X29_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[16]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~74\); + +-- Location: LABCELL_X29_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~26\); + +-- Location: LABCELL_X29_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~22\); + +-- Location: LABCELL_X29_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~18\); + +-- Location: LABCELL_X29_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~14\); + +-- Location: LABCELL_X29_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111111101110111000100110001000100110111001100110000000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~21_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\); + +-- Location: LABCELL_X29_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & \myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & \myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010001010100010001000001010001011110011111100110011000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~73_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~77_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\); + +-- Location: LABCELL_X29_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000110000110000000011000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~77_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~73_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\); + +-- Location: LABCELL_X29_Y23_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111101010000000011110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~81_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\); + +-- Location: LABCELL_X29_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~10\); + +-- Location: LABCELL_X29_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(22), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~6\); + +-- Location: LABCELL_X29_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add11~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\); + +-- Location: LABCELL_X29_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111001111111111001100110111001100010000001100110000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~9_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[22]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\); + +-- Location: LABCELL_X29_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704_BDD12705\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ +-- $ (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010010100000000101001010000000000000000101001010000000010100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~21_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704_BDD12705\); + +-- Location: LABCELL_X29_Y22_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704_BDD12705\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704_BDD12705\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000010100000000111100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~25_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~17_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_RESYN12704_BDD12705\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\); + +-- Location: LABCELL_X29_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\); + +-- Location: LABCELL_X29_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000000011000000110000110000001100000000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[22]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\); + +-- Location: LABCELL_X29_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\); + +-- Location: FF_X25_Y24_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]_OTERM3296\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100110011001111110011001100000011000000000000001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~69_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13_combout\); + +-- Location: MLABCELL_X28_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111010100010000011101010001000011110111010100011111011101010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\); + +-- Location: MLABCELL_X28_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111010111111111000100001111111100000000011101010000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~61_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~57_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~53_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10_combout\); + +-- Location: MLABCELL_X28_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100011111100111111101111100000000000000010000100100001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\); + +-- Location: MLABCELL_X28_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000001000000000010000010000000000000000100000100000000001000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~61_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~57_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~53_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8_combout\); + +-- Location: MLABCELL_X28_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~37_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~37_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000101011000000001111111100101011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~41_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~37_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9_combout\); + +-- Location: MLABCELL_X28_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_RESYN12706\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_RESYN12706_BDD12707\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~69_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_RESYN12706_BDD12707\); + +-- Location: MLABCELL_X28_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_RESYN12706_BDD12707\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000010010000011000001001000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_RESYN12706_BDD12707\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\); + +-- Location: LABCELL_X29_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111111111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\); + +-- Location: MLABCELL_X28_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000101010101010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~24_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\); + +-- Location: LABCELL_X29_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000101000000010000011110000111100001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~19_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~25_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\); + +-- Location: LABCELL_X29_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\); + +-- Location: LABCELL_X31_Y24_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000001111111100000000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~41_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~5_combout\); + +-- Location: LABCELL_X31_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~57_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add18~49_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~45_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~53_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~49_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~45_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~53_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~57_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~6_combout\); + +-- Location: LABCELL_X31_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~25_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~21_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000000110000001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~21_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~5_combout\); + +-- Location: LABCELL_X31_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~85_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~81_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~61_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~65_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000100000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~85_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~81_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~61_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~65_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~69_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~7_combout\); + +-- Location: LABCELL_X31_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~77_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~73_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~1_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~77_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~73_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8_combout\); + +-- Location: LABCELL_X26_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~49_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9_combout\); + +-- Location: LABCELL_X26_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~85_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~86\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~86\); + +-- Location: LABCELL_X26_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~14\); + +-- Location: LABCELL_X26_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~18\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~18\); + +-- Location: LABCELL_X26_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~22\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~22\); + +-- Location: LABCELL_X26_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~26\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~26\); + +-- Location: LABCELL_X26_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~10\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~10\); + +-- Location: LABCELL_X26_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~13_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~17_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\); + +-- Location: LABCELL_X24_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010001100000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~37_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~29_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~21_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_RESYN8423_BDD8424\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\); + +-- Location: LABCELL_X25_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100000000010100000000000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4_combout\); + +-- Location: LABCELL_X25_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add18~33_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add18~29_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~29_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~13_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\); + +-- Location: LABCELL_X19_Y37_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\); + +-- Location: MLABCELL_X18_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~0_combout\); + +-- Location: MLABCELL_X18_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000101001001110000010100100010000000000010001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\); + +-- Location: LABCELL_X16_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100000000000000010000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\); + +-- Location: MLABCELL_X18_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|state~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|state~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000000001111100010000000111110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~30_combout\); + +-- Location: FF_X18_Y33_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|state~30_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\); + +-- Location: LABCELL_X12_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\); + +-- Location: LABCELL_X14_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\); + +-- Location: MLABCELL_X18_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2_combout\); + +-- Location: MLABCELL_X18_Y36_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000000000001010000010100000101000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\); + +-- Location: LABCELL_X17_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000001000000000000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\); + +-- Location: LABCELL_X12_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ ((((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001100101011001010000111101011010011000001000000010110000011100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\); + +-- Location: LABCELL_X31_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\); + +-- Location: MLABCELL_X9_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\); + +-- Location: LABCELL_X12_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\); + +-- Location: LABCELL_X12_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder_combout\); + +-- Location: FF_X12_Y16_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\); + +-- Location: FF_X35_Y21_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(2)); + +-- Location: LABCELL_X35_Y21_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100111111001100001100000011001111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr195~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~5_combout\); + +-- Location: FF_X35_Y21_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100000000000000010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\); + +-- Location: LABCELL_X14_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111110101111111111111010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\); + +-- Location: LABCELL_X10_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756~feeder_combout\); + +-- Location: FF_X10_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_NEW_REG755\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756\); + +-- Location: FF_X10_Y32_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add5~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2)); + +-- Location: FF_X5_Y34_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_NEW_REG1486\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\); + +-- Location: LABCELL_X5_Y35_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\); + +-- Location: LABCELL_X5_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\); + +-- Location: LABCELL_X19_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001100000000000000110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\); + +-- Location: MLABCELL_X13_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\))) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100001000000000000101110101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_RESYN12622_BDD12623\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\); + +-- Location: LABCELL_X17_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000001100000000000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\); + +-- Location: MLABCELL_X23_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~263\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~263_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~263_combout\); + +-- Location: FF_X23_Y35_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~263_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~q\); + +-- Location: LABCELL_X25_Y17_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~53_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~65_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~61_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~53_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~61_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~57_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~49_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\); + +-- Location: LABCELL_X17_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001010100010001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~1_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~1_combout\); + +-- Location: FF_X17_Y15_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG686\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM687\); + +-- Location: FF_X20_Y39_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1430\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\); + +-- Location: LABCELL_X29_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~18\); + +-- Location: LABCELL_X29_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~22\); + +-- Location: LABCELL_X29_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~10\); + +-- Location: LABCELL_X29_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~14\); + +-- Location: LABCELL_X29_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~6\); + +-- Location: LABCELL_X29_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\); + +-- Location: FF_X24_Y34_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~324_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~q\); + +-- Location: FF_X10_Y32_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add5~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\); + +-- Location: MLABCELL_X13_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100000000001000000000001000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\); + +-- Location: FF_X31_Y26_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\); + +-- Location: LABCELL_X16_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\); + +-- Location: LABCELL_X16_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000001000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\); + +-- Location: MLABCELL_X13_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110111111111111111111111111111111111111111111111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\); + +-- Location: MLABCELL_X13_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000000000000000000000111011000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\); + +-- Location: MLABCELL_X9_Y36_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010000000000000000010101010101010100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\); + +-- Location: LABCELL_X12_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\); + +-- Location: LABCELL_X10_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489_BDD8490\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000111100000000000000001100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489_BDD8490\); + +-- Location: FF_X16_Y30_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]_OTERM2688\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\); + +-- Location: LABCELL_X16_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\); + +-- Location: LABCELL_X10_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder_combout\); + +-- Location: FF_X10_Y16_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\); + +-- Location: LABCELL_X19_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\); + +-- Location: FF_X26_Y21_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]_OTERM1941\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6)); + +-- Location: FF_X26_Y22_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]_OTERM1935\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775_BDD8776\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000101000001000100010101000101011101111101011101110111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775_BDD8776\); + +-- Location: LABCELL_X26_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777_BDD8778\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101011111111000010101111111100001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777_BDD8778\); + +-- Location: LABCELL_X26_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775_BDD8776\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777_BDD8778\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775_BDD8776\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777_BDD8778\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111111101110100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_RESYN8775_BDD8776\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_RESYN8777_BDD8778\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_combout\); + +-- Location: LABCELL_X26_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000001000000000000000001000001001000001000000000000000001000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\); + +-- Location: LABCELL_X26_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~2_combout\); + +-- Location: LABCELL_X25_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111101011111010101010101010100000101000001010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\); + +-- Location: LABCELL_X26_Y22_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111001111000011111100111100000000000011000000000000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\); + +-- Location: LABCELL_X26_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000100100001001000010010000100100001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~4_combout\); + +-- Location: LABCELL_X26_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145_BDD9146\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000010000000000000000001000010000100001000000000000000000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[21]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145_BDD9146\); + +-- Location: FF_X28_Y22_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]_OTERM1915\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\); + +-- Location: FF_X28_Y22_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]_OTERM1909\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y22_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147_BDD9148\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ +-- $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000001010101000000000101001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[22]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147_BDD9148\); + +-- Location: LABCELL_X26_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147_BDD9148\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145_BDD9146\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147_BDD9148\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145_BDD9146\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001001000000000000000000001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_RESYN9145_BDD9146\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_RESYN9147_BDD9148\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_combout\); + +-- Location: MLABCELL_X28_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000010100000101000000001010000010100000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8_combout\); + +-- Location: MLABCELL_X28_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000100000000010000000001001000000000100000000010000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\); + +-- Location: LABCELL_X26_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001001000000001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~9_combout\); + +-- Location: FF_X25_Y22_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~137_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(19)); + +-- Location: MLABCELL_X28_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011100110011011101110011001100010001000000000001000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[19]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~1_combout\); + +-- Location: MLABCELL_X28_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111101011111000011110000111100000101000001010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[18]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~2_combout\); + +-- Location: MLABCELL_X28_Y22_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010010100000000101001010000000000000000101001010000000010100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~15_combout\); + +-- Location: MLABCELL_X28_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\))))) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111111100011111010111110000111100000111000000010000010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[22]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0_combout\); + +-- Location: MLABCELL_X28_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000001000000001000000001000000001000000001000000001000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[22]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14_combout\); + +-- Location: MLABCELL_X28_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~15_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000011001100110000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3_combout\); + +-- Location: MLABCELL_X28_Y21_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111100000101010111110000010100001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11_combout\); + +-- Location: MLABCELL_X28_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111010111111111010101010111010100010000010101010000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10_combout\); + +-- Location: MLABCELL_X28_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000011111111001100001111111100000000001100000000000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12_combout\); + +-- Location: MLABCELL_X28_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000000000000000000011111010111100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13_combout\); + +-- Location: LABCELL_X26_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~9_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111111110100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\); + +-- Location: LABCELL_X25_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111001101110011011100110111001100010000000100000001000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~5_combout\); + +-- Location: LABCELL_X25_Y23_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\); + +-- Location: LABCELL_X25_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)) +-- # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111100000101000011110000000011011111000011010100111100000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\); + +-- Location: LABCELL_X25_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000001001000001100000100100000100000000000000001000001001000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\); + +-- Location: LABCELL_X25_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413_BDD8414\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111101010101111111110101010111011111010001010101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[20]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413_BDD8414\); + +-- Location: FF_X25_Y23_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]_OTERM2683\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411_BDD8412\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010001011111011000000000000000010100010111110111010001011111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[23]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411_BDD8412\); + +-- Location: LABCELL_X25_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413_BDD8414\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411_BDD8412\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(20)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413_BDD8414\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411_BDD8412\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(20))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111111001111101011111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[20]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_RESYN8413_BDD8414\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_RESYN8411_BDD8412\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\); + +-- Location: LABCELL_X25_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000100000010000000001000000001000000000100000010000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[22]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14_combout\); + +-- Location: LABCELL_X25_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111010101010101111101111111010100010000000000000101000101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[22]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17_combout\); + +-- Location: LABCELL_X24_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17)))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000100000101000100010000010111010101110101111101110111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[18]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18_combout\); + +-- Location: LABCELL_X24_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110101000000000000000011110101111100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\); + +-- Location: LABCELL_X25_Y24_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000001010000101000000101000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8_combout\); + +-- Location: LABCELL_X24_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000010000000000001000010000000000000000100001000000000000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[14]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[15]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\); + +-- Location: LABCELL_X24_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001000010000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\); + +-- Location: LABCELL_X24_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771_BDD8772\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000001001000001000000000000000000000000000000001000001001000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771_BDD8772\); + +-- Location: LABCELL_X25_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773_BDD8774\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001100000000110000110000000000000000110000110000000011000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[22]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773_BDD8774\); + +-- Location: LABCELL_X24_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773_BDD8774\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771_BDD8772\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773_BDD8774\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771_BDD8772\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000001000000000000000001000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_RESYN8771_BDD8772\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_RESYN8773_BDD8774\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\); + +-- Location: LABCELL_X24_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100000011001111110000001100001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~12_combout\); + +-- Location: LABCELL_X25_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000001000000010000000100011001110110011101100111011001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11_combout\); + +-- Location: LABCELL_X25_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000000000110011111100110010001100000010001110111111001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[15]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10_combout\); + +-- Location: LABCELL_X24_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~12_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111010101010101010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\); + +-- Location: MLABCELL_X28_Y24_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000001010001010100000001011111111101011111011111110101011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\); + +-- Location: LABCELL_X31_Y24_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000010101010111110101010101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\); + +-- Location: MLABCELL_X28_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001110000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_RESYN8767_BDD8768\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_RESYN8769_BDD8770\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\); + +-- Location: LABCELL_X29_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~2_combout\); + +-- Location: LABCELL_X29_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000001000001000000000001001000000000001000001000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\); + +-- Location: LABCELL_X29_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010111111111000000001111111100000000010101010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\); + +-- Location: LABCELL_X29_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100000011001111110000001100001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\); + +-- Location: LABCELL_X29_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000100100000000100110010000000010011001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\); + +-- Location: LABCELL_X24_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010100010100000101010101010000010101000101000001010100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~19_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\); + +-- Location: LABCELL_X24_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100010001100110011101110111100000000100010001100110011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9_combout\); + +-- Location: LABCELL_X24_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000001000001000000000001001000000000001000001000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7_combout\); + +-- Location: LABCELL_X24_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000001100001111000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10_combout\); + +-- Location: MLABCELL_X23_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618_BDD12619\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000000000010101010000000000000000101010100000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618_BDD12619\); + +-- Location: LABCELL_X24_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618_BDD12619\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618_BDD12619\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000000001100000000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_RESYN12618_BDD12619\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_combout\); + +-- Location: LABCELL_X24_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110011110000111111001111000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~4_combout\); + +-- Location: LABCELL_X24_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ +-- & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000100000010000000001000000001000000000100000010000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\); + +-- Location: LABCELL_X24_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) $ (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000000011100011000010001100000000000000000000100000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~3_combout\); + +-- Location: LABCELL_X24_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100010001010000000001000100010101110111011111010101011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\); + +-- Location: LABCELL_X24_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\); + +-- Location: LABCELL_X25_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110011110000000011111111000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\); + +-- Location: LABCELL_X24_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000110011000000000011101100000000001100110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6_combout\); + +-- Location: LABCELL_X25_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000001000001000000000001001000000000001000001000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(14), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11_combout\); + +-- Location: LABCELL_X25_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000011000000000000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[20]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\); + +-- Location: LABCELL_X24_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010111010101110101011101010111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\); + +-- Location: MLABCELL_X23_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_BDD8960\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110101011111111111011101111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_RESYN8959_RESYN13462_BDD13463\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_BDD8960\); + +-- Location: FF_X35_Y21_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\); + +-- Location: MLABCELL_X4_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~86\); + +-- Location: MLABCELL_X4_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~82\); + +-- Location: LABCELL_X6_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~86\); + +-- Location: LABCELL_X6_Y26_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~82\); + +-- Location: FF_X9_Y25_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~38_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(14)); + +-- Location: FF_X9_Y32_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG939\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\); + +-- Location: FF_X7_Y35_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1001\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\); + +-- Location: LABCELL_X12_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101000000000101010100000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\); + +-- Location: LABCELL_X12_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\); + +-- Location: LABCELL_X12_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\); + +-- Location: LABCELL_X7_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18_combout\); + +-- Location: MLABCELL_X13_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010100000010100101000100010000100011101110110011001101110111001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\); + +-- Location: MLABCELL_X9_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\); + +-- Location: MLABCELL_X9_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101000001010000000000000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2_combout\); + +-- Location: LABCELL_X10_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001010000000000101000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1_combout\); + +-- Location: LABCELL_X12_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100001000000000001000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\); + +-- Location: LABCELL_X12_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000000000000000000011000000110000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\); + +-- Location: MLABCELL_X9_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010101010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\); + +-- Location: LABCELL_X16_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001001111000011100000000000000000100001000101000000000111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\); + +-- Location: LABCELL_X16_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100010000000000010001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\); + +-- Location: LABCELL_X6_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\); + +-- Location: LABCELL_X7_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector706~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~0_combout\); + +-- Location: LABCELL_X12_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\); + +-- Location: LABCELL_X7_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111111001100110011111100110000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\); + +-- Location: LABCELL_X7_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111000000000000001101010111010101110101010001010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector706~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~19_combout\); + +-- Location: LABCELL_X6_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100001111111111110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\); + +-- Location: LABCELL_X6_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\); + +-- Location: LABCELL_X6_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000000110011010100000011001101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~20_combout\); + +-- Location: LABCELL_X10_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000000000000010000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\); + +-- Location: LABCELL_X7_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector706~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~20_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~19_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100100000000000110010000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector706~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~19_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21_combout\); + +-- Location: LABCELL_X7_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001000110010001100100011001000110011001101110011001100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~18_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~21_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~22_combout\); + +-- Location: FF_X7_Y33_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1005\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~22_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\); + +-- Location: LABCELL_X6_Y35_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100111111111100110001010101000000000101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\); + +-- Location: FF_X7_Y35_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1007\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\); + +-- Location: FF_X7_Y35_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG999\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\); + +-- Location: FF_X7_Y35_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\); + +-- Location: LABCELL_X7_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000111111111111111100010000000100001011101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\); + +-- Location: LABCELL_X14_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\); + +-- Location: LABCELL_X6_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010000000001010101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\); + +-- Location: LABCELL_X16_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\); + +-- Location: LABCELL_X6_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1_combout\); + +-- Location: LABCELL_X6_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100000001000000011111000100000001111100010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14_combout\); + +-- Location: LABCELL_X16_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000000000001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\); + +-- Location: LABCELL_X16_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\); + +-- Location: LABCELL_X7_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000011111111101000001111111110100000101000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\); + +-- Location: LABCELL_X6_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010101110111000001010000010001000101011101110000010100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3_combout\); + +-- Location: LABCELL_X6_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011100000111100001110000011000000110000001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\); + +-- Location: LABCELL_X6_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001000110010001100110011001000110010001100100011011100110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~16_combout\); + +-- Location: FF_X6_Y33_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_NEW_REG1023\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~16_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\); + +-- Location: LABCELL_X6_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111100010100001111110001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~0_combout\); + +-- Location: FF_X6_Y35_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_NEW_REG1025\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\); + +-- Location: FF_X7_Y35_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_NEW_REG1021\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\); + +-- Location: LABCELL_X7_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000001010101111111111111111100010000010101011011101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\); + +-- Location: FF_X9_Y32_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y36_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\); + +-- Location: LABCELL_X12_Y35_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\); + +-- Location: LABCELL_X16_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\); + +-- Location: LABCELL_X7_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector640~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000000000010000000000000001010101000000000101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~0_combout\); + +-- Location: LABCELL_X7_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110111000001000011011100000100000001000000010000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3_combout\); + +-- Location: LABCELL_X12_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010000000000000000000000000000000010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\); + +-- Location: LABCELL_X7_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010011001111010001001100111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1_combout\); + +-- Location: LABCELL_X7_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector640~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110000000000000000000000000011110000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector640~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector640~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4_combout\); + +-- Location: LABCELL_X7_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000010000000000000001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~5_combout\); + +-- Location: FF_X7_Y34_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1128\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\); + +-- Location: LABCELL_X6_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111001111110000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\); + +-- Location: FF_X7_Y34_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1126\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\); + +-- Location: FF_X7_Y34_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1122\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\); + +-- Location: MLABCELL_X9_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101000000010001000100000101010101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~1_combout\); + +-- Location: FF_X9_Y33_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1124\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\); + +-- Location: LABCELL_X7_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001111111111011111101010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\); + +-- Location: LABCELL_X12_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\); + +-- Location: LABCELL_X5_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000111111111111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~4_combout\); + +-- Location: FF_X5_Y33_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG959\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\); + +-- Location: MLABCELL_X9_Y36_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111111111111111011111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\); + +-- Location: LABCELL_X5_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\); + +-- Location: LABCELL_X5_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111110101111111111111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~8_combout\); + +-- Location: FF_X5_Y33_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG963\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\); + +-- Location: LABCELL_X14_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\); + +-- Location: LABCELL_X7_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010101000000000001010100000000000101111000011110010111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~7_combout\); + +-- Location: MLABCELL_X13_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000100001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\); + +-- Location: LABCELL_X7_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010101000000110101010100000011000000000000001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5_combout\); + +-- Location: LABCELL_X7_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000001000000000000000110000001100000011000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6_combout\); + +-- Location: LABCELL_X7_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~7_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101000000000000000000000000010101010000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6_combout\); + +-- Location: LABCELL_X7_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001111111111111100111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~7_combout\); + +-- Location: FF_X7_Y33_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG961\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\); + +-- Location: FF_X9_Y33_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG955\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\); + +-- Location: LABCELL_X7_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~3_combout\); + +-- Location: FF_X7_Y33_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG957\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\); + +-- Location: LABCELL_X5_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~3_RTM0967\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~3_RTM0967_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010111111111111111011111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~3_RTM0967_combout\); + +-- Location: FF_X5_Y33_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG965\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~3_RTM0967_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\); + +-- Location: LABCELL_X5_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010111011101110111111101111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\); + +-- Location: LABCELL_X7_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\))) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011010001010110011110001001101010111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\); + +-- Location: LABCELL_X17_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\); + +-- Location: LABCELL_X5_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101011111010101010101111101010100000111100001010000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\); + +-- Location: LABCELL_X5_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010000010101010101000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~7_combout\); + +-- Location: FF_X5_Y33_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1045\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\); + +-- Location: LABCELL_X10_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\); + +-- Location: LABCELL_X5_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000111111111111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~2_combout\); + +-- Location: FF_X5_Y33_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1041\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\); + +-- Location: LABCELL_X14_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\); + +-- Location: LABCELL_X5_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector904~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000000000010000000000000001000100010001000100010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~0_combout\); + +-- Location: LABCELL_X16_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000010000100000000001000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\); + +-- Location: MLABCELL_X13_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\); + +-- Location: LABCELL_X5_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000000000100111001000100010011100100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4_combout\); + +-- Location: LABCELL_X5_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001111000000000000111110101010101011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1_combout\); + +-- Location: LABCELL_X5_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector904~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110000000000000111000000000000011000000000000001100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector904~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector904~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5_combout\); + +-- Location: LABCELL_X5_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001111111111111100111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~6_combout\); + +-- Location: FF_X5_Y33_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1043\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\); + +-- Location: LABCELL_X5_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~1_RTM01049\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~1_RTM01049_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010111111111101111111111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~1_RTM01049_combout\); + +-- Location: FF_X5_Y33_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1047\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~1_RTM01049_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\); + +-- Location: LABCELL_X5_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011011101110111011111110111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\); + +-- Location: LABCELL_X16_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\); + +-- Location: LABCELL_X16_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\); + +-- Location: LABCELL_X6_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) +-- # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100111011101110111010001000100010001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\); + +-- Location: FF_X6_Y35_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_NEW_REG1150\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\); + +-- Location: LABCELL_X14_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\); + +-- Location: LABCELL_X6_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010000000001010101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2_combout\); + +-- Location: LABCELL_X6_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0_combout\); + +-- Location: LABCELL_X12_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000000000000000000000000000000010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\); + +-- Location: LABCELL_X6_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000000000110000000001010011010100000101001101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3_combout\); + +-- Location: LABCELL_X6_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111111001100110011111100110000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\); + +-- Location: LABCELL_X6_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100000100000001000000010000111111001101110011011100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector772~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4_combout\); + +-- Location: LABCELL_X6_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000010000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector772~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[18]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5_combout\); + +-- Location: LABCELL_X6_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001010000011110000101000001111000111110000111100011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~6_combout\); + +-- Location: FF_X6_Y33_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_NEW_REG1148\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\); + +-- Location: FF_X7_Y35_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1003\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\); + +-- Location: FF_X7_Y35_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_NEW_REG1146\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\); + +-- Location: LABCELL_X7_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111101110100110000001100001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\); + +-- Location: LABCELL_X14_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\); + +-- Location: LABCELL_X7_Y34_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector838~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000000000000001100000000000000111011100000000011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~0_combout\); + +-- Location: LABCELL_X7_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010101000000110101010100000011000000000000001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2_combout\); + +-- Location: LABCELL_X7_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100001101000000010001110100010001000111010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1_combout\); + +-- Location: LABCELL_X12_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001000000000000000000000000000000000100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\); + +-- Location: LABCELL_X7_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector838~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101000000000101010100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector838~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector838~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[26]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3_combout\); + +-- Location: LABCELL_X7_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000001000000000000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~4_combout\); + +-- Location: FF_X7_Y34_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1166\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\); + +-- Location: MLABCELL_X9_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) +-- # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101000000010001000100000101010101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~0_combout\); + +-- Location: FF_X9_Y33_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1162\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\); + +-- Location: LABCELL_X6_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\); + +-- Location: FF_X7_Y34_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1164\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\); + +-- Location: FF_X7_Y34_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1160\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\); + +-- Location: LABCELL_X7_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000011100000111111111111111111100000111000001111111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\); + +-- Location: LABCELL_X14_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\); + +-- Location: LABCELL_X10_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100111111111100110100000000000000000000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~2_combout\); + +-- Location: FF_X10_Y37_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1031\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\); + +-- Location: LABCELL_X5_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010111110101111101000000000000000001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\); + +-- Location: LABCELL_X10_Y37_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~1_RTM01039\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~1_RTM01039_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000111111011111110111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~1_RTM01039_combout\); + +-- Location: FF_X10_Y37_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1037\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~1_RTM01039_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\); + +-- Location: FF_X10_Y37_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1027\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\); + +-- Location: LABCELL_X7_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100000001000000010000110111000001000011011100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4_combout\); + +-- Location: LABCELL_X14_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010000000000000000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\); + +-- Location: LABCELL_X7_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector970~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1))))) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010000000000010101000000000001010111000000000101011100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~1_combout\); + +-- Location: LABCELL_X7_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000000000000001000000000000000110011000000000011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0_combout\); + +-- Location: LABCELL_X7_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector970~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101010101000000010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector970~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector970~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3_combout\); + +-- Location: LABCELL_X7_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011000011110000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~5_combout\); + +-- Location: FF_X7_Y33_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1033\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\); + +-- Location: LABCELL_X10_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111100111111001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~6_combout\); + +-- Location: FF_X10_Y37_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1035\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\); + +-- Location: FF_X19_Y39_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1029\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\); + +-- Location: LABCELL_X10_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001100110011001100100011001000100011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\); + +-- Location: LABCELL_X7_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100001111110100010000001100011101110011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\); + +-- Location: MLABCELL_X9_Y15_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\); + +-- Location: FF_X10_Y35_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG941\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\); + +-- Location: MLABCELL_X18_Y38_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\); + +-- Location: LABCELL_X14_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111010000000000000000000000000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\); + +-- Location: FF_X12_Y35_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG943\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\); + +-- Location: LABCELL_X6_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111000000000111011100000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\); + +-- Location: FF_X6_Y35_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1095\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\); + +-- Location: FF_X9_Y35_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1093\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\); + +-- Location: LABCELL_X16_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000000000000001000100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\); + +-- Location: LABCELL_X16_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\); + +-- Location: LABCELL_X14_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101000110010111110100011001000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2_combout\); + +-- Location: LABCELL_X12_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\); + +-- Location: MLABCELL_X13_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111101010101010100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\); + +-- Location: LABCELL_X14_Y35_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\); + +-- Location: LABCELL_X10_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\); + +-- Location: MLABCELL_X13_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111100110000000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\); + +-- Location: LABCELL_X14_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\)))) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001001111010001000100111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~2_combout\); + +-- Location: LABCELL_X14_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101111111111111010111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\); + +-- Location: LABCELL_X16_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\); + +-- Location: LABCELL_X16_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100000001000000110011000100000011001100010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~24_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\); + +-- Location: LABCELL_X16_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\); + +-- Location: LABCELL_X10_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\); + +-- Location: LABCELL_X14_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001101000000001100110100000000110011110000000011001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\); + +-- Location: FF_X14_Y35_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1097\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\); + +-- Location: MLABCELL_X9_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110001010101111111010000000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\); + +-- Location: LABCELL_X14_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\); + +-- Location: MLABCELL_X9_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101011111000000000000111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~2_combout\); + +-- Location: MLABCELL_X9_Y35_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110101111111111111010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\); + +-- Location: MLABCELL_X13_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011100000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\); + +-- Location: LABCELL_X10_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1_combout\); + +-- Location: MLABCELL_X13_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\); + +-- Location: LABCELL_X14_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000000100000000000000000001000000000000000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\); + +-- Location: MLABCELL_X13_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010101000101000001010100010100000000010001000000000001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\); + +-- Location: LABCELL_X10_Y35_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000001110000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\); + +-- Location: FF_X10_Y35_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG951\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\); + +-- Location: LABCELL_X10_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010100010101000101010001010100010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\); + +-- Location: FF_X9_Y35_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG953\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\); + +-- Location: FF_X9_Y35_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG949\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\); + +-- Location: MLABCELL_X9_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000001010000010101111111111001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\); + +-- Location: FF_X9_Y35_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1057\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\); + +-- Location: MLABCELL_X13_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\); + +-- Location: MLABCELL_X9_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001110011010100000111001100000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~2_combout\); + +-- Location: MLABCELL_X9_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111111111110101111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\); + +-- Location: MLABCELL_X13_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\); + +-- Location: LABCELL_X16_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001001100010001000100110001000100000011000000000000001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\); + +-- Location: LABCELL_X14_Y37_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100000000010001010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\); + +-- Location: MLABCELL_X9_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\); + +-- Location: MLABCELL_X9_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101000001011000011110000101100001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\); + +-- Location: FF_X9_Y35_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1061\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\); + +-- Location: MLABCELL_X9_Y35_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111111101111111011111110111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\); + +-- Location: FF_X9_Y35_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1059\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\); + +-- Location: MLABCELL_X9_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010001010101111101010100010011110100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\); + +-- Location: MLABCELL_X9_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111100111111111111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\); + +-- Location: FF_X9_Y35_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1017\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\); + +-- Location: LABCELL_X14_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100000100000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\); + +-- Location: LABCELL_X10_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~1_combout\); + +-- Location: LABCELL_X16_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000001000000000000000000000001000000000000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\); + +-- Location: MLABCELL_X13_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000101000000000100010101010101010101010000000001000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\); + +-- Location: LABCELL_X16_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\); + +-- Location: MLABCELL_X13_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000000000000010100000000000111011001100110011101100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~2_combout\); + +-- Location: LABCELL_X10_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001111111111111100111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3_combout\); + +-- Location: LABCELL_X10_Y35_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~1_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110001001100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~4_combout\); + +-- Location: FF_X10_Y35_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1019\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\); + +-- Location: FF_X9_Y35_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1015\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\); + +-- Location: MLABCELL_X9_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\)) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\)))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000000000011001100111111011100110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\); + +-- Location: LABCELL_X7_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux7~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) +-- & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) +-- & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000011010001001100111101110111000000110111011111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~0_combout\); + +-- Location: LABCELL_X10_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000010100001111000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\); + +-- Location: FF_X10_Y35_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG973\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\); + +-- Location: FF_X10_Y35_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG971\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\); + +-- Location: MLABCELL_X13_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\); + +-- Location: LABCELL_X14_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011011100000101001101110000010100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~2_combout\); + +-- Location: LABCELL_X14_Y35_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001111111111111100111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\); + +-- Location: LABCELL_X16_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111101100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\); + +-- Location: LABCELL_X14_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\); + +-- Location: LABCELL_X16_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) $ (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000000100000010000000010000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\); + +-- Location: LABCELL_X17_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\); + +-- Location: LABCELL_X17_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110000001010000011100000101000001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~36_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\); + +-- Location: LABCELL_X14_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000001001100110000000100110011000000110011001100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\); + +-- Location: FF_X14_Y35_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG975\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\); + +-- Location: LABCELL_X10_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011101010101111101100000000000000001010101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\); + +-- Location: LABCELL_X6_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\); + +-- Location: LABCELL_X6_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001100000011110000110000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\); + +-- Location: FF_X10_Y35_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1011\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\); + +-- Location: FF_X10_Y35_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1009\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\); + +-- Location: MLABCELL_X13_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\); + +-- Location: LABCELL_X14_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001000000000000000010000000100000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\); + +-- Location: MLABCELL_X13_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000101000001010101000000000101010101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~32_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\); + +-- Location: MLABCELL_X9_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\); + +-- Location: LABCELL_X10_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111110001000100011111000100010001000100010001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~7_combout\); + +-- Location: LABCELL_X10_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111111111110101111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\); + +-- Location: LABCELL_X12_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\); + +-- Location: LABCELL_X10_Y35_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\); + +-- Location: LABCELL_X10_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000001000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector501~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~3_combout\); + +-- Location: FF_X10_Y35_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1013\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\); + +-- Location: LABCELL_X10_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\)) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\)))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011101110111010101100000000000000001011101110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\); + +-- Location: LABCELL_X12_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\); + +-- Location: LABCELL_X12_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2_combout\); + +-- Location: LABCELL_X12_Y35_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101010111011111110101111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\); + +-- Location: LABCELL_X16_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000001000010000000000100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\); + +-- Location: LABCELL_X16_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\); + +-- Location: LABCELL_X16_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000000000100010000000001010001010100000101000101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~38_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\); + +-- Location: LABCELL_X16_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000001010100000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\); + +-- Location: LABCELL_X12_Y35_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\); + +-- Location: LABCELL_X12_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001000100010001000100011001000110011001100100011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~4_combout\); + +-- Location: FF_X12_Y35_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1067\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\); + +-- Location: FF_X7_Y35_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1063\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\); + +-- Location: LABCELL_X6_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111110011111100111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\); + +-- Location: FF_X7_Y35_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\); + +-- Location: LABCELL_X7_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\)) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100111100001111111100000000010001001111000011110100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\); + +-- Location: LABCELL_X16_Y10_N3 +\myVirtualToplevel|SD_DATA_WRITE[7]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_DATA_WRITE[7]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SD_CS~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000010100000000000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_SD_CS~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + combout => \myVirtualToplevel|SD_DATA_WRITE[7]~1_combout\); + +-- Location: LABCELL_X10_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~feeder_combout\); + +-- Location: LABCELL_X12_Y17_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\); + +-- Location: LABCELL_X10_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\); + +-- Location: LABCELL_X10_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & (\myVirtualToplevel|RESET_n~q\ & !\myVirtualToplevel|MEM_BUSY~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datac => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\); + +-- Location: FF_X10_Y15_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)); + +-- Location: LABCELL_X12_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\); + +-- Location: LABCELL_X12_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ = ( \myVirtualToplevel|RESET_n~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001000000010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datae => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\); + +-- Location: LABCELL_X12_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000000000010000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\); + +-- Location: LABCELL_X12_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100001111000001010000111100000101000000000000010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\); + +-- Location: LABCELL_X10_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ +-- & (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010011000100010001001100010011000100110001000100010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\); + +-- Location: LABCELL_X29_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000100000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~45_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~41_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~37_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8_combout\); + +-- Location: LABCELL_X29_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~89_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~17_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~33_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~1_combout\); + +-- Location: LABCELL_X29_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\); + +-- Location: LABCELL_X31_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\); + +-- Location: LABCELL_X25_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~297\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~297_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~297_combout\); + +-- Location: FF_X25_Y32_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~297_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\); + +-- Location: LABCELL_X10_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000000000000000110011001100110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\); + +-- Location: MLABCELL_X28_Y6_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\ = ( !\myVirtualToplevel|SD_RESET\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\); + +-- Location: MLABCELL_X23_Y5_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & !\myVirtualToplevel|SD_HNDSHK_IN\(0))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ +-- & !\myVirtualToplevel|SD_HNDSHK_IN\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000110000001100000001000000010000000100000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1_combout\); + +-- Location: MLABCELL_X28_Y5_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\))) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101000000000111110100000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\); + +-- Location: IOIBUF_X40_Y0_N41 +\SDCARD_MISO[0]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_SDCARD_MISO(0), + o => \SDCARD_MISO[0]~input_o\); + +-- Location: FF_X24_Y7_N23 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\); + +-- Location: LABCELL_X24_Y7_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SD_HNDSHK_IN\(0) & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111110000001111111111000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\); + +-- Location: LABCELL_X24_Y7_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ = ( !\myVirtualToplevel|SD_RESET\(0) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\ & +-- !\myVirtualToplevel|SD_HNDSHK_IN\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011001100111011101100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0), + dataf => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\); + +-- Location: LABCELL_X25_Y7_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\); + +-- Location: FF_X23_Y5_N26 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0_combout\, + asdata => VCC, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(0)); + +-- Location: MLABCELL_X23_Y5_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(0), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0_combout\); + +-- Location: MLABCELL_X28_Y5_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~6_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(0))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010111010000100001011101000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector21~0_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~6_combout\); + +-- Location: FF_X28_Y5_N26 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(0)); + +-- Location: MLABCELL_X28_Y5_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~14\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(0), + cin => GND, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~14\); + +-- Location: MLABCELL_X28_Y5_N33 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~25_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(1) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~14\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~26\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(1) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(1), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~14\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~25_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~26\); + +-- Location: MLABCELL_X28_Y5_N27 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v~9_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~25_sumout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~25_sumout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v~9_combout\); + +-- Location: FF_X28_Y5_N29 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v~9_combout\, + sclr => \myVirtualToplevel|SD_RESET\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(1)); + +-- Location: MLABCELL_X28_Y5_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(2) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~26\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~18\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(2) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(2), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~26\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~18\); + +-- Location: MLABCELL_X23_Y5_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector20~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector20~0_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(2))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011101110110011001110111011001100111011101100110011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(2), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector20~0_combout\); + +-- Location: FF_X23_Y5_N1 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector20~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(2)); + +-- Location: MLABCELL_X28_Y5_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]~7_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(2) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17_sumout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17_sumout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100000000111100000000000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~17_sumout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(2), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]~7_combout\); + +-- Location: FF_X28_Y5_N14 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(2)); + +-- Location: MLABCELL_X28_Y5_N39 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(3) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~18\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~2\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(3) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(3), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~18\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~2\); + +-- Location: MLABCELL_X23_Y5_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector19~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector19~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111111111100001111111111110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(3), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector19~0_combout\); + +-- Location: FF_X23_Y5_N53 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector19~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3)); + +-- Location: MLABCELL_X28_Y5_N9 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]~3_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3) & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000001100100010001000010001000000000011001100100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~1_sumout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(3), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]~3_combout\); + +-- Location: FF_X28_Y5_N11 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(3)); + +-- Location: MLABCELL_X28_Y5_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(4) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~2\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~22\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(4) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(4), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~2\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~22\); + +-- Location: MLABCELL_X23_Y5_N3 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector18~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector18~0_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011101110110011001110111011001100111011101100110011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(4), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector18~0_combout\); + +-- Location: FF_X23_Y5_N5 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector18~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4)); + +-- Location: MLABCELL_X28_Y5_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]~8_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4) & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000001100100010001000010000000100000011001000110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~21_sumout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(4), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]~8_combout\); + +-- Location: FF_X28_Y5_N2 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(4)); + +-- Location: MLABCELL_X28_Y5_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(0) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(2) & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(1) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(4))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(2), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(1), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(4), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(0), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\); + +-- Location: LABCELL_X26_Y6_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\ = ( \SDCARD_MISO[0]~input_o\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\) ) ) # ( +-- !\SDCARD_MISO[0]~input_o\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001001100010011000100110001001100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\, + dataf => \ALT_INV_SDCARD_MISO[0]~input_o\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\); + +-- Location: LABCELL_X26_Y6_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]~6_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ +-- & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111000000000000000011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]~6_combout\); + +-- Location: FF_X26_Y6_N20 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1)); + +-- Location: LABCELL_X26_Y6_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]~5_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ +-- & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111000000000000000011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(2), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]~5_combout\); + +-- Location: FF_X26_Y6_N50 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2)); + +-- Location: LABCELL_X26_Y6_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ +-- & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111000000000000000011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(3), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(2), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]~2_combout\); + +-- Location: FF_X26_Y6_N8 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3)); + +-- Location: LABCELL_X26_Y6_N9 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]~7_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111000000000000000011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(4), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(3), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]~7_combout\); + +-- Location: FF_X26_Y6_N11 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4)); + +-- Location: LABCELL_X26_Y6_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]~3_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111000000000000000011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(5), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(4), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]~3_combout\); + +-- Location: FF_X26_Y6_N53 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5)); + +-- Location: LABCELL_X26_Y6_N21 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]~4_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6) & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111000000000000000011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(6), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(5), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]~4_combout\); + +-- Location: FF_X26_Y6_N23 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6)); + +-- Location: LABCELL_X26_Y6_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]~8_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) ) +-- ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000011111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(6), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(7), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]~8_combout\); + +-- Location: FF_X26_Y6_N26 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7)); + +-- Location: LABCELL_X26_Y6_N39 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000001000000010000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(7), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(4), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(2), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~0_combout\); + +-- Location: LABCELL_X26_Y6_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000001000000010000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(6), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(3), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(5), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\); + +-- Location: LABCELL_X26_Y7_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~1_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~2\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0), + cin => GND, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~1_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~2\); + +-- Location: FF_X21_Y10_N44 +\myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector16~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y10_N39 +\myVirtualToplevel|Selector14~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector14~0_combout\ = (\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\) # +-- (\myVirtualToplevel|SD_DATA_REQ~q\)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000101000000000100010100000000010001010000000001000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_1~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\, + combout => \myVirtualToplevel|Selector14~0_combout\); + +-- Location: LABCELL_X20_Y10_N12 +\myVirtualToplevel|Selector15~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector15~8_combout\ = ( !\myVirtualToplevel|SD_DATA_REQ~q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & (((!\myVirtualToplevel|Selector15~2_combout\ & +-- \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\)) # (\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\)))) ) ) # ( \myVirtualToplevel|SD_DATA_REQ~q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & (!\myVirtualToplevel|Selector15~2_combout\ & \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001000000010000000000000000000100010000000100000001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\, + datad => \myVirtualToplevel|ALT_INV_Selector15~2_combout\, + datae => \myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\, + datag => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_1~q\, + combout => \myVirtualToplevel|Selector15~8_combout\); + +-- Location: FF_X20_Y10_N14 +\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector15~8_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\); + +-- Location: LABCELL_X20_Y10_N30 +\myVirtualToplevel|Selector14~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector14~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\)) # (\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100111111001100110011111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\, + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + combout => \myVirtualToplevel|Selector14~1_combout\); + +-- Location: LABCELL_X20_Y10_N48 +\myVirtualToplevel|Selector14~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector14~2_combout\ = ( \myVirtualToplevel|Selector14~1_combout\ & ( !\myVirtualToplevel|Selector17~0_combout\ ) ) # ( !\myVirtualToplevel|Selector14~1_combout\ & ( (!\myVirtualToplevel|Selector17~0_combout\ & +-- (!\myVirtualToplevel|Selector15~2_combout\ & \myVirtualToplevel|Selector14~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010001000000000001000100010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Selector17~0_combout\, + datab => \myVirtualToplevel|ALT_INV_Selector15~2_combout\, + datad => \myVirtualToplevel|ALT_INV_Selector14~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_Selector14~1_combout\, + combout => \myVirtualToplevel|Selector14~2_combout\); + +-- Location: FF_X20_Y10_N49 +\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector14~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\); + +-- Location: FF_X20_Y10_N7 +\myVirtualToplevel|SD_STATE.SD_STATE_READ_2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector18~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_STATE.SD_STATE_READ_2~q\); + +-- Location: FF_X21_Y10_N38 +\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector13~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y10_N0 +\myVirtualToplevel|Selector15~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector15~0_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & !\myVirtualToplevel|SD_DATA_REQ~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011000000000011001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\, + combout => \myVirtualToplevel|Selector15~0_combout\); + +-- Location: LABCELL_X21_Y10_N12 +\myVirtualToplevel|Selector15~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector15~6_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & (!\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & !\myVirtualToplevel|Selector15~0_combout\)) ) +-- ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & (!\myVirtualToplevel|Selector15~0_combout\ & ((!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100010000000000110001000000000001000100000000000100010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\, + datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_IDLE~q\, + datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_Selector15~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~DUPLICATE_q\, + combout => \myVirtualToplevel|Selector15~6_combout\); + +-- Location: LABCELL_X21_Y10_N45 +\myVirtualToplevel|Selector11~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector11~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( (!\myVirtualToplevel|Selector11~1_combout\) # ((!\myVirtualToplevel|Selector15~2_combout\) # (\myVirtualToplevel|Selector15~5_combout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111101011111111111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Selector11~1_combout\, + datac => \myVirtualToplevel|ALT_INV_Selector15~5_combout\, + datad => \myVirtualToplevel|ALT_INV_Selector15~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + combout => \myVirtualToplevel|Selector11~2_combout\); + +-- Location: FF_X21_Y10_N47 +\myVirtualToplevel|SD_STATE.SD_STATE_RESET\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector11~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\); + +-- Location: LABCELL_X21_Y10_N9 +\myVirtualToplevel|Selector12~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector12~1_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\ & ( (!\myVirtualToplevel|Equal8~1_combout\ & (!\myVirtualToplevel|Selector12~0_combout\ & +-- !\myVirtualToplevel|Selector15~2_combout\)) ) ) ) # ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ( !\myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\ & ( !\myVirtualToplevel|Selector12~0_combout\ ) ) ) # ( +-- !\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ( !\myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\ & ( !\myVirtualToplevel|Selector12~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000000000000000001000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal8~1_combout\, + datab => \myVirtualToplevel|ALT_INV_Selector12~0_combout\, + datac => \myVirtualToplevel|ALT_INV_Selector15~2_combout\, + datae => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~q\, + combout => \myVirtualToplevel|Selector12~1_combout\); + +-- Location: FF_X21_Y10_N11 +\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector12~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\); + +-- Location: LABCELL_X24_Y10_N57 +\myVirtualToplevel|SD_RESET_TIMER~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_RESET_TIMER~5_combout\ = ( !\myVirtualToplevel|SD_RESET_TIMER\(0) & ( !\myVirtualToplevel|Equal8~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010000000000000000010101010101010100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal8~1_combout\, + datae => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(0), + combout => \myVirtualToplevel|SD_RESET_TIMER~5_combout\); + +-- Location: FF_X21_Y10_N46 +\myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector11~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y10_N33 +\myVirtualToplevel|Selector3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector3~0_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\ & ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ ) ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~DUPLICATE_q\, + combout => \myVirtualToplevel|Selector3~0_combout\); + +-- Location: FF_X24_Y10_N59 +\myVirtualToplevel|SD_RESET_TIMER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_RESET_TIMER~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + ena => \myVirtualToplevel|Selector3~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_RESET_TIMER\(0)); + +-- Location: LABCELL_X24_Y10_N0 +\myVirtualToplevel|Add0~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add0~26\ = CARRY(( \myVirtualToplevel|SD_RESET_TIMER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(0), + cin => GND, + cout => \myVirtualToplevel|Add0~26\); + +-- Location: LABCELL_X24_Y10_N3 +\myVirtualToplevel|Add0~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add0~17_sumout\ = SUM(( \myVirtualToplevel|SD_RESET_TIMER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add0~26\ )) +-- \myVirtualToplevel|Add0~18\ = CARRY(( \myVirtualToplevel|SD_RESET_TIMER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add0~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(1), + cin => \myVirtualToplevel|Add0~26\, + sumout => \myVirtualToplevel|Add0~17_sumout\, + cout => \myVirtualToplevel|Add0~18\); + +-- Location: LABCELL_X24_Y10_N30 +\myVirtualToplevel|Selector8~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector8~0_combout\ = (!\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\) # (\myVirtualToplevel|Add0~17_sumout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111111001111110011111100111111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + datac => \myVirtualToplevel|ALT_INV_Add0~17_sumout\, + combout => \myVirtualToplevel|Selector8~0_combout\); + +-- Location: LABCELL_X24_Y10_N39 +\myVirtualToplevel|SD_RESET_TIMER[3]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_RESET_TIMER[3]~3_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\ & ( (!\myVirtualToplevel|Equal8~1_combout\ & \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\) ) ) # ( +-- !\myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\ & ( (!\myVirtualToplevel|Equal8~1_combout\) # (!\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010111110101111101000001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal8~1_combout\, + datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~DUPLICATE_q\, + combout => \myVirtualToplevel|SD_RESET_TIMER[3]~3_combout\); + +-- Location: FF_X24_Y10_N32 +\myVirtualToplevel|SD_RESET_TIMER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector8~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|SD_RESET_TIMER[3]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_RESET_TIMER\(1)); + +-- Location: LABCELL_X24_Y10_N6 +\myVirtualToplevel|Add0~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add0~9_sumout\ = SUM(( \myVirtualToplevel|SD_RESET_TIMER\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add0~18\ )) +-- \myVirtualToplevel|Add0~10\ = CARRY(( \myVirtualToplevel|SD_RESET_TIMER\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add0~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(2), + cin => \myVirtualToplevel|Add0~18\, + sumout => \myVirtualToplevel|Add0~9_sumout\, + cout => \myVirtualToplevel|Add0~10\); + +-- Location: LABCELL_X24_Y10_N24 +\myVirtualToplevel|SD_RESET_TIMER~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_RESET_TIMER~2_combout\ = ( \myVirtualToplevel|Add0~9_sumout\ & ( !\myVirtualToplevel|Equal8~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_Equal8~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_Add0~9_sumout\, + combout => \myVirtualToplevel|SD_RESET_TIMER~2_combout\); + +-- Location: FF_X24_Y10_N26 +\myVirtualToplevel|SD_RESET_TIMER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_RESET_TIMER~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + ena => \myVirtualToplevel|Selector3~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_RESET_TIMER\(2)); + +-- Location: FF_X24_Y10_N46 +\myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_RESET_TIMER~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + ena => \myVirtualToplevel|Selector3~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y10_N9 +\myVirtualToplevel|Add0~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add0~13_sumout\ = SUM(( \myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add0~10\ )) +-- \myVirtualToplevel|Add0~14\ = CARRY(( \myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add0~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add0~10\, + sumout => \myVirtualToplevel|Add0~13_sumout\, + cout => \myVirtualToplevel|Add0~14\); + +-- Location: LABCELL_X24_Y10_N51 +\myVirtualToplevel|Selector6~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector6~0_combout\ = ( \myVirtualToplevel|Add0~13_sumout\ ) # ( !\myVirtualToplevel|Add0~13_sumout\ & ( !\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + dataf => \myVirtualToplevel|ALT_INV_Add0~13_sumout\, + combout => \myVirtualToplevel|Selector6~0_combout\); + +-- Location: FF_X24_Y10_N52 +\myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector6~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|SD_RESET_TIMER[3]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y10_N12 +\myVirtualToplevel|Add0~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add0~5_sumout\ = SUM(( \myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add0~14\ )) +-- \myVirtualToplevel|Add0~6\ = CARRY(( \myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add0~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER[4]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add0~14\, + sumout => \myVirtualToplevel|Add0~5_sumout\, + cout => \myVirtualToplevel|Add0~6\); + +-- Location: LABCELL_X24_Y10_N45 +\myVirtualToplevel|SD_RESET_TIMER~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_RESET_TIMER~1_combout\ = ( \myVirtualToplevel|Add0~5_sumout\ & ( !\myVirtualToplevel|Equal8~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal8~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_Add0~5_sumout\, + combout => \myVirtualToplevel|SD_RESET_TIMER~1_combout\); + +-- Location: FF_X24_Y10_N47 +\myVirtualToplevel|SD_RESET_TIMER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_RESET_TIMER~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + ena => \myVirtualToplevel|Selector3~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_RESET_TIMER\(4)); + +-- Location: LABCELL_X24_Y10_N15 +\myVirtualToplevel|Add0~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add0~21_sumout\ = SUM(( \myVirtualToplevel|SD_RESET_TIMER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add0~6\ )) +-- \myVirtualToplevel|Add0~22\ = CARRY(( \myVirtualToplevel|SD_RESET_TIMER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add0~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(5), + cin => \myVirtualToplevel|Add0~6\, + sumout => \myVirtualToplevel|Add0~21_sumout\, + cout => \myVirtualToplevel|Add0~22\); + +-- Location: LABCELL_X24_Y10_N42 +\myVirtualToplevel|SD_RESET_TIMER~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_RESET_TIMER~4_combout\ = ( \myVirtualToplevel|Add0~21_sumout\ & ( !\myVirtualToplevel|Equal8~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal8~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_Add0~21_sumout\, + combout => \myVirtualToplevel|SD_RESET_TIMER~4_combout\); + +-- Location: FF_X24_Y10_N44 +\myVirtualToplevel|SD_RESET_TIMER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_RESET_TIMER~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + ena => \myVirtualToplevel|Selector3~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_RESET_TIMER\(5)); + +-- Location: LABCELL_X24_Y10_N18 +\myVirtualToplevel|Add0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add0~1_sumout\ = SUM(( \myVirtualToplevel|SD_RESET_TIMER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add0~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(6), + cin => \myVirtualToplevel|Add0~22\, + sumout => \myVirtualToplevel|Add0~1_sumout\); + +-- Location: LABCELL_X24_Y10_N36 +\myVirtualToplevel|SD_RESET_TIMER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_RESET_TIMER~0_combout\ = ( \myVirtualToplevel|Add0~1_sumout\ & ( !\myVirtualToplevel|Equal8~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal8~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_Add0~1_sumout\, + combout => \myVirtualToplevel|SD_RESET_TIMER~0_combout\); + +-- Location: FF_X24_Y10_N37 +\myVirtualToplevel|SD_RESET_TIMER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_RESET_TIMER~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + ena => \myVirtualToplevel|Selector3~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_RESET_TIMER\(6)); + +-- Location: FF_X24_Y10_N53 +\myVirtualToplevel|SD_RESET_TIMER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector6~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|SD_RESET_TIMER[3]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_RESET_TIMER\(3)); + +-- Location: LABCELL_X24_Y10_N48 +\myVirtualToplevel|Equal8~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal8~0_combout\ = ( !\myVirtualToplevel|SD_RESET_TIMER\(1) & ( (!\myVirtualToplevel|SD_RESET_TIMER\(5) & (!\myVirtualToplevel|SD_RESET_TIMER\(3) & !\myVirtualToplevel|SD_RESET_TIMER\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(5), + datac => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(3), + datad => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(0), + dataf => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(1), + combout => \myVirtualToplevel|Equal8~0_combout\); + +-- Location: LABCELL_X24_Y10_N27 +\myVirtualToplevel|Equal8~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal8~1_combout\ = ( \myVirtualToplevel|Equal8~0_combout\ & ( (!\myVirtualToplevel|SD_RESET_TIMER\(2) & (!\myVirtualToplevel|SD_RESET_TIMER\(4) & !\myVirtualToplevel|SD_RESET_TIMER\(6))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(2), + datac => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(4), + datad => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(6), + dataf => \myVirtualToplevel|ALT_INV_Equal8~0_combout\, + combout => \myVirtualToplevel|Equal8~1_combout\); + +-- Location: LABCELL_X21_Y10_N57 +\myVirtualToplevel|Selector15~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector15~7_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ( (\myVirtualToplevel|Selector15~6_combout\ & ((\myVirtualToplevel|Equal8~1_combout\) # (\myVirtualToplevel|Selector15~4_combout\))) ) ) # ( +-- !\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ( (\myVirtualToplevel|Selector15~6_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\) # (\myVirtualToplevel|Selector15~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101100000011000011110000001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\, + datab => \myVirtualToplevel|ALT_INV_Selector15~4_combout\, + datac => \myVirtualToplevel|ALT_INV_Selector15~6_combout\, + datad => \myVirtualToplevel|ALT_INV_Equal8~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + combout => \myVirtualToplevel|Selector15~7_combout\); + +-- Location: LABCELL_X20_Y10_N6 +\myVirtualToplevel|Selector18~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector18~0_combout\ = ( \myVirtualToplevel|Selector15~7_combout\ & ( (\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|Selector15~7_combout\ & ( (!\myVirtualToplevel|Selector15~2_combout\ & (((\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~q\)))) # (\myVirtualToplevel|Selector15~2_combout\ & (\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\, + datab => \myVirtualToplevel|ALT_INV_Selector15~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~q\, + dataf => \myVirtualToplevel|ALT_INV_Selector15~7_combout\, + combout => \myVirtualToplevel|Selector18~0_combout\); + +-- Location: FF_X20_Y10_N8 +\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector18~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y10_N18 +\myVirtualToplevel|Selector15~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector15~3_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & +-- !\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\)) ) ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ((!\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|SD_DATA_VALID~DUPLICATE_q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110110000000000111011000000000000001100000000000000110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_DATA_VALID~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~DUPLICATE_q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\, + combout => \myVirtualToplevel|Selector15~3_combout\); + +-- Location: LABCELL_X20_Y10_N36 +\myVirtualToplevel|Selector15~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector15~4_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\ & ( (\myVirtualToplevel|Selector15~3_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & +-- (!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ((!\myVirtualToplevel|SD_DATA_REQ~q\))))) ) ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\ & ( +-- (\myVirtualToplevel|Selector15~3_combout\ & ((!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & !\myVirtualToplevel|SD_DATA_REQ~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001010000010110000101000001011000010000000101100001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_1~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_Selector15~3_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\, + combout => \myVirtualToplevel|Selector15~4_combout\); + +-- Location: LABCELL_X21_Y10_N54 +\myVirtualToplevel|Selector15~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector15~5_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ( (!\myVirtualToplevel|Selector15~4_combout\ & \myVirtualToplevel|Equal8~1_combout\) ) ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & !\myVirtualToplevel|Selector15~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100010001000100010001000100000001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\, + datab => \myVirtualToplevel|ALT_INV_Selector15~4_combout\, + datac => \myVirtualToplevel|ALT_INV_Equal8~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + combout => \myVirtualToplevel|Selector15~5_combout\); + +-- Location: LABCELL_X21_Y10_N24 +\myVirtualToplevel|Selector10~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector10~0_combout\ = ( \myVirtualToplevel|Selector11~0_combout\ & ( ((!\myVirtualToplevel|Selector15~2_combout\ & \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\)) # (\myVirtualToplevel|Selector15~5_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101111101010101010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Selector15~5_combout\, + datac => \myVirtualToplevel|ALT_INV_Selector15~2_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_IDLE~q\, + dataf => \myVirtualToplevel|ALT_INV_Selector11~0_combout\, + combout => \myVirtualToplevel|Selector10~0_combout\); + +-- Location: FF_X21_Y10_N25 +\myVirtualToplevel|SD_STATE.SD_STATE_IDLE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector10~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\); + +-- Location: LABCELL_X21_Y10_N30 +\myVirtualToplevel|Selector2~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector2~0_combout\ = ( \myVirtualToplevel|SD_RD\(0) & ( \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (\myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\) # +-- (\myVirtualToplevel|SD_CHANNEL~q\))) ) ) ) # ( !\myVirtualToplevel|SD_RD\(0) & ( \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (!\myVirtualToplevel|SD_CHANNEL~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & +-- \myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|SD_RD\(0) & ( !\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\) # +-- (!\myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\)) # (\myVirtualToplevel|SD_CHANNEL~q\) ) ) ) # ( !\myVirtualToplevel|SD_RD\(0) & ( !\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (!\myVirtualToplevel|SD_CHANNEL~q\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & \myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000111111111111010100000000101000000000000011110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_CHANNEL~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\, + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~DUPLICATE_q\, + datae => \myVirtualToplevel|ALT_INV_SD_RD\(0), + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_IDLE~q\, + combout => \myVirtualToplevel|Selector2~0_combout\); + +-- Location: FF_X21_Y10_N31 +\myVirtualToplevel|SD_RD[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector2~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_RD\(0)); + +-- Location: LABCELL_X26_Y8_N12 +\myVirtualToplevel|SD_RD[0]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_RD[0]~_wirecell_combout\ = ( !\myVirtualToplevel|SD_RD\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_SD_RD\(0), + combout => \myVirtualToplevel|SD_RD[0]~_wirecell_combout\); + +-- Location: FF_X26_Y7_N7 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~13_sumout\, + asdata => \myVirtualToplevel|SD_RD[0]~_wirecell_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(2)); + +-- Location: LABCELL_X26_Y7_N3 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~5_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~2\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~6\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~2\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~5_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~6\); + +-- Location: LABCELL_X26_Y7_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~13_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(2) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~6\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~14\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(2) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(2), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~6\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~13_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~14\); + +-- Location: FF_X26_Y7_N8 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~13_sumout\, + asdata => \myVirtualToplevel|SD_RD[0]~_wirecell_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\); + +-- Location: FF_X26_Y7_N28 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~9_sumout\, + asdata => VCC, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9)); + +-- Location: LABCELL_X26_Y7_N9 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~17_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(3) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~14\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~18\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(3) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(3), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~14\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~17_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~18\); + +-- Location: FF_X26_Y7_N11 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~17_sumout\, + asdata => \~GND~combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(3)); + +-- Location: LABCELL_X26_Y7_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~21_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(4) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~18\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~22\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(4) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(4), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~18\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~21_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~22\); + +-- Location: FF_X26_Y7_N14 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~21_sumout\, + asdata => \~GND~combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(4)); + +-- Location: LABCELL_X26_Y7_N15 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~25_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(5) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~22\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~26\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(5) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(5), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~22\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~25_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~26\); + +-- Location: FF_X26_Y7_N17 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~25_sumout\, + asdata => \~GND~combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(5)); + +-- Location: LABCELL_X26_Y7_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~29_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(6) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~26\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~30\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(6) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(6), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~26\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~29_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~30\); + +-- Location: FF_X26_Y7_N20 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~29_sumout\, + asdata => \~GND~combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(6)); + +-- Location: LABCELL_X26_Y7_N21 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~33_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(7) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~30\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~34\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(7) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(7), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~30\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~33_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~34\); + +-- Location: FF_X26_Y7_N23 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~33_sumout\, + asdata => \~GND~combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(7)); + +-- Location: LABCELL_X26_Y7_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~37_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(8) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~34\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~38\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(8) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(8), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~34\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~37_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~38\); + +-- Location: FF_X26_Y7_N26 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~37_sumout\, + asdata => \~GND~combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(8)); + +-- Location: LABCELL_X26_Y7_N27 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~9_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(9), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~38\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~9_sumout\); + +-- Location: FF_X26_Y7_N29 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~9_sumout\, + asdata => VCC, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y7_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(7) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(3) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(6) & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(5) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(8) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(4)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(6), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(5), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(8), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(4), + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(7), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(3), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\); + +-- Location: LABCELL_X26_Y7_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1)) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111101111111111111110111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\); + +-- Location: LABCELL_X24_Y6_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0))))) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\) # +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101111000000001110111100000000001000110000000000100011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~1_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal4~0_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0_combout\); + +-- Location: LABCELL_X25_Y7_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\)))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001111111010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[4]~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\); + +-- Location: FF_X26_Y7_N2 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~1_sumout\, + asdata => VCC, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0)); + +-- Location: FF_X26_Y7_N5 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~5_sumout\, + asdata => \myVirtualToplevel|SD_RD\(0), + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1)); + +-- Location: LABCELL_X26_Y7_N39 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100000000000000010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(9), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\); + +-- Location: LABCELL_X24_Y6_N9 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~62\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~62_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010111110101111101011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal4~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~62_combout\); + +-- Location: LABCELL_X26_Y7_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100000000000000010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(9), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\); + +-- Location: LABCELL_X24_Y6_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # (\SDCARD_MISO[0]~input_o\)))) +-- ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # (\SDCARD_MISO[0]~input_o\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # (\SDCARD_MISO[0]~input_o\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101100000000111110110000000011111011000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datab => \ALT_INV_SDCARD_MISO[0]~input_o\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64_combout\); + +-- Location: LABCELL_X26_Y6_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(2), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(5), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(6), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(7), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~0_combout\); + +-- Location: LABCELL_X26_Y6_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000000000000001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(3), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(4), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\); + +-- Location: LABCELL_X21_Y6_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\ = (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000100010001000100010001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\); + +-- Location: LABCELL_X24_Y7_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & \myVirtualToplevel|SD_HNDSHK_IN\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\); + +-- Location: MLABCELL_X23_Y6_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~57_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\ & ( +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # (\myVirtualToplevel|SD_RESET\(0)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & !\myVirtualToplevel|SD_RESET\(0))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\ +-- ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & !\myVirtualToplevel|SD_RESET\(0))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000000111111111111111100110000000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD0~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~57_combout\); + +-- Location: FF_X23_Y6_N1 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~57_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\); + +-- Location: LABCELL_X25_Y6_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ $ (!\SDCARD_MISO[0]~input_o\)))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & !\SDCARD_MISO[0]~input_o\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000101010001000100010101000100000000010000010000000001000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datad => \ALT_INV_SDCARD_MISO[0]~input_o\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\); + +-- Location: LABCELL_X25_Y6_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000110011111100000011001100000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76_combout\); + +-- Location: LABCELL_X25_Y6_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101010000000000000101000000000000010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~52_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~76_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77_combout\); + +-- Location: LABCELL_X25_Y6_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000111000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~49_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~77_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\); + +-- Location: LABCELL_X25_Y6_N15 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000111000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~49_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\); + +-- Location: LABCELL_X21_Y6_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~79\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~79_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ & (!\myVirtualToplevel|SD_RESET\(0) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\)) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ & (!\myVirtualToplevel|SD_RESET\(0) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\)) ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\ & (!\myVirtualToplevel|SD_RESET\(0) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000111100001010000000110000000000000011000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal2~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD0~q\, + datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~78_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~75_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~79_combout\); + +-- Location: FF_X21_Y6_N38 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~79_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\); + +-- Location: MLABCELL_X23_Y6_N9 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~60\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~60_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (!\myVirtualToplevel|SD_RESET\(0) & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\) # (\myVirtualToplevel|SD_RESET\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111011111111111100110000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_CMD0_RESPONSE~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~60_combout\); + +-- Location: FF_X23_Y6_N10 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~60_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\); + +-- Location: MLABCELL_X23_Y6_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~87\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~87_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ & ( +-- (!\myVirtualToplevel|SD_RESET\(0) & (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\))) ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010000000000000000000101010101010100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_CMD0_RESPONSE~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~87_combout\); + +-- Location: FF_X23_Y6_N20 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~87_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\); + +-- Location: LABCELL_X21_Y6_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80_combout\); + +-- Location: LABCELL_X26_Y6_N15 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~77_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81_combout\); + +-- Location: LABCELL_X21_Y6_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~82\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~82_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\ & (!\myVirtualToplevel|SD_RESET\(0) & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000010000001100000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal2~0_combout\, + datab => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~80_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~81_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~82_combout\); + +-- Location: FF_X21_Y6_N20 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~82_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\); + +-- Location: MLABCELL_X23_Y6_N39 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~55_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (!\myVirtualToplevel|SD_RESET\(0) & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\) # (\myVirtualToplevel|SD_RESET\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111011111111111100110000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD55~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~55_combout\); + +-- Location: FF_X23_Y6_N40 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~55_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\); + +-- Location: MLABCELL_X23_Y6_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~56_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & !\myVirtualToplevel|SD_RESET\(0))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # ((\myVirtualToplevel|SD_RESET\(0)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111011111111111100110000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD41~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~56_combout\); + +-- Location: FF_X23_Y6_N7 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~56_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\); + +-- Location: MLABCELL_X23_Y6_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~74\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~74_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010000000000000000000101010101010100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD41~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~74_combout\); + +-- Location: FF_X23_Y6_N59 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~74_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\); + +-- Location: LABCELL_X20_Y7_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000101000001010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\); + +-- Location: LABCELL_X24_Y7_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector160~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector160~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\) # +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111111101111101011111110111110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr40~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_doDeselect_v~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector160~0_combout\); + +-- Location: FF_X24_Y7_N49 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector160~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\); + +-- Location: LABCELL_X25_Y6_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\ & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001111110011001100111111001100000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_doDeselect_v~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\); + +-- Location: LABCELL_X25_Y6_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~47_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\); + +-- Location: LABCELL_X21_Y6_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ & +-- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0)))) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100000101001101110000010100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD55~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~66_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72_combout\); + +-- Location: LABCELL_X21_Y6_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~73_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010001000000000001000100000100010101010100010001010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~72_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~73_combout\); + +-- Location: FF_X21_Y6_N1 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~73_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\); + +-- Location: LABCELL_X20_Y7_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\); + +-- Location: LABCELL_X25_Y5_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011010000000000001101000000000000110000000000000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(4), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\); + +-- Location: LABCELL_X24_Y5_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\); + +-- Location: LABCELL_X24_Y7_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~40_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & +-- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(2))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1)))) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100010011001100110001001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(2), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(9), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~40_combout\); + +-- Location: LABCELL_X21_Y6_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~89_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & ((!\myVirtualToplevel|SD_RESET\(0)))))) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\) # (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~40_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000111100001111110011111110111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~40_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + dataf => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datag => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~89_combout\); + +-- Location: FF_X21_Y6_N7 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~89_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\); + +-- Location: LABCELL_X25_Y7_N39 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\); + +-- Location: LABCELL_X25_Y7_N3 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\); + +-- Location: LABCELL_X21_Y6_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000000000101010100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\); + +-- Location: LABCELL_X24_Y5_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( \SDCARD_MISO[0]~input_o\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( !\SDCARD_MISO[0]~input_o\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( !\SDCARD_MISO[0]~input_o\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010001000000000000000100000000000100010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr13~0_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + dataf => \ALT_INV_SDCARD_MISO[0]~input_o\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\); + +-- Location: LABCELL_X21_Y6_N3 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\); + +-- Location: FF_X26_Y5_N26 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~3_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~q\); + +-- Location: LABCELL_X26_Y5_N39 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\) # +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000011111111110000001100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\); + +-- Location: LABCELL_X24_Y5_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44_combout\ = (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ((!\SDCARD_MISO[0]~input_o\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001010000011110000101000001111000010100000111100001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \ALT_INV_SDCARD_MISO[0]~input_o\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44_combout\); + +-- Location: LABCELL_X26_Y5_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) # (\SDCARD_MISO[0]~input_o\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) # (\SDCARD_MISO[0]~input_o\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000000000000000000011111111001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\, + datab => \ALT_INV_SDCARD_MISO[0]~input_o\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\); + +-- Location: LABCELL_X24_Y5_N3 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & !\SDCARD_MISO[0]~input_o\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000100110000001100010011000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr13~0_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + datad => \ALT_INV_SDCARD_MISO[0]~input_o\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\); + +-- Location: LABCELL_X25_Y5_N21 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001101000000000000110100000000000011000000000000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(5), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\); + +-- Location: LABCELL_X25_Y5_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~6\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~10\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(4), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~6\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~10\); + +-- Location: LABCELL_X25_Y5_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~10\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~14\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(5), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~10\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~14\); + +-- Location: LABCELL_X26_Y5_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # (\SDCARD_MISO[0]~input_o\))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # (\SDCARD_MISO[0]~input_o\)))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101000001000000010101000100010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\, + datad => \ALT_INV_SDCARD_MISO[0]~input_o\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\); + +-- Location: LABCELL_X25_Y5_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\) # +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13_sumout\))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111111111111101111111111110000111100001111111011111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~7_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector66~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~13_sumout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(5), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~4_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~1_combout\); + +-- Location: FF_X25_Y5_N14 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~1_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5)); + +-- Location: LABCELL_X25_Y5_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~14\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~26\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(6), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~14\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~26\); + +-- Location: LABCELL_X25_Y5_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector65~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector65~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\) # (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44_combout\)) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000101111111011101100001111000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~44_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~25_sumout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~4_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(6), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector65~0_combout\); + +-- Location: FF_X25_Y5_N2 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector65~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6)); + +-- Location: LABCELL_X26_Y5_N3 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111001111110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\); + +-- Location: LABCELL_X26_Y5_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~1_combout\ = (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111000001110000011100000111000001110000011100000111000001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~1_combout\); + +-- Location: LABCELL_X21_Y7_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\); + +-- Location: LABCELL_X26_Y5_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000000000000001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4_combout\); + +-- Location: LABCELL_X26_Y5_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111011000000000011101100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~4_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\); + +-- Location: LABCELL_X26_Y5_N9 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\)))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111011101110000011101110111000001100110011000000110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\); + +-- Location: LABCELL_X26_Y5_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000110011001100110000001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(0), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~1_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~5_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~3_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\); + +-- Location: LABCELL_X25_Y5_N27 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]~8_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\) # +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111011111111111100010000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~2_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~1_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]~8_combout\); + +-- Location: FF_X25_Y5_N29 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0)); + +-- Location: LABCELL_X25_Y5_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(7), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~26\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\); + +-- Location: LABCELL_X24_Y5_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\ ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\ ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & !\SDCARD_MISO[0]~input_o\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100110001000100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~29_sumout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datad => \ALT_INV_SDCARD_MISO[0]~input_o\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\); + +-- Location: LABCELL_X24_Y5_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011111111111111101111111111001100111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~7_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~1_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(7), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~2_combout\); + +-- Location: FF_X24_Y5_N50 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~2_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7)); + +-- Location: MLABCELL_X23_Y5_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3_combout\); + +-- Location: MLABCELL_X23_Y6_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\); + +-- Location: LABCELL_X24_Y5_N27 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2_combout\); + +-- Location: MLABCELL_X23_Y5_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # (!\SDCARD_MISO[0]~input_o\)))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3_combout\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~3_combout\, + datac => \ALT_INV_SDCARD_MISO[0]~input_o\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector87~0_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\); + +-- Location: LABCELL_X25_Y5_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~18\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(0), + cin => GND, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~18\); + +-- Location: LABCELL_X25_Y5_N33 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~18\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~22\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(1), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~18\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~22\); + +-- Location: LABCELL_X24_Y5_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21_sumout\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21_sumout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & !\SDCARD_MISO[0]~input_o\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000011111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + datad => \ALT_INV_SDCARD_MISO[0]~input_o\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~21_sumout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\); + +-- Location: LABCELL_X24_Y5_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~5_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\) # (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\)) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101110111011111111111011111110111011101110111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~4_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~1_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~0_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(1), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~5_combout\); + +-- Location: FF_X24_Y5_N32 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~5_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1)); + +-- Location: LABCELL_X25_Y5_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0) & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(6), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(7), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(1), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\); + +-- Location: LABCELL_X24_Y5_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\ = ( \SDCARD_MISO[0]~input_o\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & +-- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\)))) ) ) ) # ( !\SDCARD_MISO[0]~input_o\ & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) ) ) ) # ( \SDCARD_MISO[0]~input_o\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) ) ) ) # ( !\SDCARD_MISO[0]~input_o\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000010100000101000001111001111110000101000111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~0_combout\, + datae => \ALT_INV_SDCARD_MISO[0]~input_o\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~47_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\); + +-- Location: LABCELL_X25_Y5_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~22\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~2\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(2), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~22\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~2\); + +-- Location: LABCELL_X26_Y5_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\)))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\) # +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\) # +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100110101011000000010010001111001101111011110100010101100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~5_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~3_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~1_sumout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\); + +-- Location: LABCELL_X25_Y5_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~6_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\))) ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\) # +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111011111111111100010000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~1_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~2_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(2), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector69~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~6_combout\); + +-- Location: FF_X25_Y5_N26 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2)); + +-- Location: LABCELL_X25_Y5_N39 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~2\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~6\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(3), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~2\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~6\); + +-- Location: LABCELL_X24_Y5_N9 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5_sumout\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5_sumout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & !\SDCARD_MISO[0]~input_o\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010000111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + datac => \ALT_INV_SDCARD_MISO[0]~input_o\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~5_sumout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\); + +-- Location: LABCELL_X24_Y5_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~3_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\) # (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\)) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101110111011111111111111101110111011101110111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~2_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~7_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~0_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(3), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~3_combout\); + +-- Location: FF_X24_Y5_N38 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~3_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3)); + +-- Location: LABCELL_X25_Y5_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\) # +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9_sumout\)) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101110111011111111111111101110101010101010101111111111111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector67~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~9_sumout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~7_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(4), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~4_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~1_combout\); + +-- Location: FF_X25_Y5_N8 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~1_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4)); + +-- Location: LABCELL_X25_Y5_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(4), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(5), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(2), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(3), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\); + +-- Location: LABCELL_X26_Y5_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\); + +-- Location: LABCELL_X25_Y7_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\); + +-- Location: LABCELL_X24_Y6_N15 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & !\myVirtualToplevel|SD_RESET\(0))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & +-- !\myVirtualToplevel|SD_RESET\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001010000000000000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\, + datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\); + +-- Location: LABCELL_X24_Y6_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~65_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\ ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~62_combout\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000000000000010100000001011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~62_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~64_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~63_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~65_combout\); + +-- Location: FF_X24_Y6_N26 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~65_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\); + +-- Location: MLABCELL_X23_Y5_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & ( +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\))) # (\SDCARD_MISO[0]~input_o\) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & ( (\SDCARD_MISO[0]~input_o\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000011111110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \ALT_INV_SDCARD_MISO[0]~input_o\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~0_combout\); + +-- Location: FF_X23_Y5_N38 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0)); + +-- Location: LABCELL_X21_Y6_N27 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111011101111111111101110100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~1_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\); + +-- Location: LABCELL_X24_Y6_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\ = ( \myVirtualToplevel|SD_WR\(0) & ( \myVirtualToplevel|SD_RD\(0) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # (!\SDCARD_MISO[0]~input_o\))) ) ) ) # ( !\myVirtualToplevel|SD_WR\(0) & ( \myVirtualToplevel|SD_RD\(0) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # (!\SDCARD_MISO[0]~input_o\))) ) ) ) # ( \myVirtualToplevel|SD_WR\(0) & ( !\myVirtualToplevel|SD_RD\(0) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # (!\SDCARD_MISO[0]~input_o\))) ) ) ) # ( !\myVirtualToplevel|SD_WR\(0) & ( !\myVirtualToplevel|SD_RD\(0) & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # (!\SDCARD_MISO[0]~input_o\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100101111001100110010001000110011001000100011001100100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datad => \ALT_INV_SDCARD_MISO[0]~input_o\, + datae => \myVirtualToplevel|ALT_INV_SD_WR\(0), + dataf => \myVirtualToplevel|ALT_INV_SD_RD\(0), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\); + +-- Location: LABCELL_X24_Y7_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\); + +-- Location: MLABCELL_X23_Y5_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr13~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\); + +-- Location: LABCELL_X24_Y6_N33 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110011111100111111001111110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\); + +-- Location: MLABCELL_X23_Y6_N33 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~54_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\))) ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\ & ( (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111011100000000000010001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~47_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr34~combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WAIT_FOR_HOST_RW~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~53_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~54_combout\); + +-- Location: FF_X23_Y6_N34 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~54_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\); + +-- Location: LABCELL_X21_Y6_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~71\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~71_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & ( +-- (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\ & (!\myVirtualToplevel|SD_RESET\(0) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000111100001010000000000000101100001111000010110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~70_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~66_combout\, + datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WAIT_FOR_HOST_RW~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~71_combout\); + +-- Location: FF_X21_Y6_N32 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~71_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\); + +-- Location: LABCELL_X21_Y6_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & +-- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & +-- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\) # +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111011111110000011101111111000000010111100100000001011110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~0_combout\); + +-- Location: FF_X21_Y6_N13 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~0_combout\, + asdata => VCC, + sload => \myVirtualToplevel|SD_RESET\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\); + +-- Location: LABCELL_X21_Y10_N51 +\myVirtualToplevel|Selector1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector1~0_combout\ = ( \myVirtualToplevel|SD_WR\(0) & ( \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\) # +-- (\myVirtualToplevel|SD_CHANNEL~q\))) ) ) ) # ( !\myVirtualToplevel|SD_WR\(0) & ( \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (!\myVirtualToplevel|SD_CHANNEL~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & +-- \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|SD_WR\(0) & ( !\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\) # +-- (!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\)) # (\myVirtualToplevel|SD_CHANNEL~q\) ) ) ) # ( !\myVirtualToplevel|SD_WR\(0) & ( !\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (!\myVirtualToplevel|SD_CHANNEL~q\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000111111111111010100000000101000000000000011110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_CHANNEL~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\, + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~DUPLICATE_q\, + datae => \myVirtualToplevel|ALT_INV_SD_WR\(0), + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_IDLE~q\, + combout => \myVirtualToplevel|Selector1~0_combout\); + +-- Location: FF_X21_Y10_N52 +\myVirtualToplevel|SD_WR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector1~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_WR\(0)); + +-- Location: LABCELL_X25_Y7_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ = ( !\myVirtualToplevel|SD_RD\(0) & ( !\myVirtualToplevel|SD_WR\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_WR\(0), + dataf => \myVirtualToplevel|ALT_INV_SD_RD\(0), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\); + +-- Location: LABCELL_X21_Y6_N15 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\); + +-- Location: MLABCELL_X23_Y5_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (\SDCARD_MISO[0]~input_o\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000101010100000000000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datac => \ALT_INV_SDCARD_MISO[0]~input_o\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr13~0_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\); + +-- Location: MLABCELL_X23_Y6_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~61_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & !\myVirtualToplevel|SD_RESET\(0))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # ((\myVirtualToplevel|SD_RESET\(0)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111011111111111100110000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_ACMD41_RESPONSE~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~61_combout\); + +-- Location: FF_X23_Y6_N43 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~61_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\); + +-- Location: MLABCELL_X23_Y6_N21 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~88\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~88_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ & ( +-- (!\myVirtualToplevel|SD_RESET\(0) & (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\))) ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010000000000000000000101010101010100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_ACMD41_RESPONSE~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~88_combout\); + +-- Location: FF_X23_Y6_N23 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~88_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\); + +-- Location: LABCELL_X26_Y6_N3 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000000000000000100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(2), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(4), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(3), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\); + +-- Location: LABCELL_X26_Y7_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\); + +-- Location: LABCELL_X26_Y6_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_STD_MATCH~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o~3_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\); + +-- Location: LABCELL_X24_Y6_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110011111111111111001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal4~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\); + +-- Location: LABCELL_X21_Y6_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~86\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~86_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & (!\myVirtualToplevel|SD_RESET\(0) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & !\myVirtualToplevel|SD_RESET\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000111100001111000000010000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~1_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~85_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~86_combout\); + +-- Location: FF_X21_Y6_N50 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~86_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\); + +-- Location: LABCELL_X25_Y6_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & \SDCARD_MISO[0]~input_o\)))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & !\SDCARD_MISO[0]~input_o\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000101110001100000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datad => \ALT_INV_SDCARD_MISO[0]~input_o\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~48_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\); + +-- Location: MLABCELL_X23_Y6_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~52_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & !\myVirtualToplevel|SD_RESET\(0))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # ((\myVirtualToplevel|SD_RESET\(0)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111011111111111100110000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.GET_CMD8_RESPONSE~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~52_combout\); + +-- Location: FF_X23_Y6_N37 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~52_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\); + +-- Location: MLABCELL_X23_Y6_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~69_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ & ( +-- (!\myVirtualToplevel|SD_RESET\(0) & (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\))) ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010000000000000000000101010101010100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.GET_CMD8_RESPONSE~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~69_combout\); + +-- Location: FF_X23_Y6_N56 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~69_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\); + +-- Location: LABCELL_X24_Y7_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector159~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector159~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000110000000000000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector159~0_combout\); + +-- Location: FF_X24_Y7_N7 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector159~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\); + +-- Location: MLABCELL_X28_Y5_N21 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\); + +-- Location: MLABCELL_X28_Y5_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(5) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~22\ )) +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~6\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(5) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(5), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~22\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\, + cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~6\); + +-- Location: MLABCELL_X23_Y5_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector17~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector17~0_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011101110110011001110111011001100111011101100110011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(5), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector17~0_combout\); + +-- Location: FF_X23_Y5_N44 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector17~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5)); + +-- Location: MLABCELL_X28_Y5_N3 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]~4_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5) & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000001100100010001000010001000000000011001100100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~5_sumout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(5), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]~4_combout\); + +-- Location: FF_X28_Y5_N5 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(5)); + +-- Location: MLABCELL_X28_Y5_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(6) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(6), + cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~6\, + sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\); + +-- Location: MLABCELL_X23_Y5_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector16~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector16~0_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011101110110011001110111011001100111011101100110011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(6), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector16~0_combout\); + +-- Location: FF_X23_Y5_N46 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector16~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6)); + +-- Location: MLABCELL_X28_Y5_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]~5_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6) & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000001100100010001000010000000100000011001000110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~9_sumout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(6), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]~5_combout\); + +-- Location: FF_X28_Y5_N8 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(6)); + +-- Location: MLABCELL_X28_Y5_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(3) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(6) & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(5)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(6), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(5), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(3), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\); + +-- Location: LABCELL_X26_Y6_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\); + +-- Location: LABCELL_X24_Y6_N21 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\); + +-- Location: LABCELL_X24_Y6_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~46_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\)))) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011110000000100001111000000010000101100000001000010110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~46_combout\); + +-- Location: FF_X24_Y6_N19 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~46_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\); + +-- Location: LABCELL_X25_Y6_N21 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & !\myVirtualToplevel|SD_RESET\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59_combout\); + +-- Location: LABCELL_X25_Y6_N27 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( !\myVirtualToplevel|SD_RESET\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\); + +-- Location: LABCELL_X25_Y6_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~60\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~60_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & ( +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59_combout\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\)))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000101011111111111010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~59_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~58_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~49_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~60_combout\); + +-- Location: FF_X25_Y6_N32 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~60_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\); + +-- Location: LABCELL_X26_Y5_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000000000000001000000000000000100000000000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\); + +-- Location: LABCELL_X26_Y5_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1_combout\ = ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100111111111111110011111111111111001111111111111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1_combout\); + +-- Location: LABCELL_X26_Y5_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~3_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & +-- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1_combout\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ & +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\))))) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0011001100110011001100110011001100000000010100000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~2_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datag => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~3_combout\); + +-- Location: FF_X26_Y5_N25 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~3_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y6_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~50_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\))) ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\ & ( (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111011100000000000010001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~47_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr34~combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_WAIT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector87~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~50_combout\); + +-- Location: FF_X23_Y6_N32 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~50_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\); + +-- Location: LABCELL_X26_Y6_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001000000010000000100000001111111110000000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o~3_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_STD_MATCH~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_WAIT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~66_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\); + +-- Location: LABCELL_X24_Y6_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~68\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~68_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & !\myVirtualToplevel|SD_RESET\(0)) ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\) # (!\SDCARD_MISO[0]~input_o\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001110000000110000001100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datad => \ALT_INV_SDCARD_MISO[0]~input_o\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~67_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~68_combout\); + +-- Location: FF_X24_Y6_N44 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~68_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\); + +-- Location: LABCELL_X25_Y6_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_doDeselect_v~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\); + +-- Location: LABCELL_X25_Y6_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~42_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\); + +-- Location: LABCELL_X25_Y6_N3 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\)))) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010101010100000101010101000000010001000100000001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~52_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\); + +-- Location: LABCELL_X24_Y6_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ((\myVirtualToplevel|SD_RD\(0)))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\, + datac => \myVirtualToplevel|ALT_INV_SD_RD\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\); + +-- Location: MLABCELL_X23_Y6_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~49_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\))) ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\ & ( (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111011100000000000010001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~47_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr34~combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.RD_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~48_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~49_combout\); + +-- Location: FF_X23_Y6_N25 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~49_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\); + +-- Location: MLABCELL_X23_Y6_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~57_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010000000000000000000101010101010100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.RD_BLK~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~57_combout\); + +-- Location: FF_X23_Y6_N50 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~57_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\); + +-- Location: MLABCELL_X23_Y6_N15 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\)))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110011001100000011001100110000000000110001000000000011000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + datab => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\); + +-- Location: LABCELL_X24_Y5_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\ = ( \SDCARD_MISO[0]~input_o\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & +-- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\))) ) ) ) # ( !\SDCARD_MISO[0]~input_o\ & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\)) ) ) ) # ( \SDCARD_MISO[0]~input_o\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001010000010100000000000100010000010100010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~0_combout\, + datae => \ALT_INV_SDCARD_MISO[0]~input_o\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~42_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\); + +-- Location: LABCELL_X24_Y6_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~44_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\ & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\ ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\ & ( ((!\myVirtualToplevel|SD_RESET\(0) & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001011110000111100001111000011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~41_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~43_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~44_combout\); + +-- Location: FF_X24_Y6_N2 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~44_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\); + +-- Location: LABCELL_X25_Y6_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~61_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\)))) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010101010000000101010101000000010101000100000001010100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~61_combout\); + +-- Location: FF_X25_Y6_N25 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~61_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\); + +-- Location: LABCELL_X26_Y5_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000110000001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\); + +-- Location: LABCELL_X25_Y6_N9 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\); + +-- Location: MLABCELL_X23_Y5_N15 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr34~combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45_combout\); + +-- Location: MLABCELL_X23_Y5_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~46_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( (\SDCARD_MISO[0]~input_o\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) # ((\SDCARD_MISO[0]~input_o\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110001111111111111111100000000000000011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \ALT_INV_SDCARD_MISO[0]~input_o\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~45_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.START_INIT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~46_combout\); + +-- Location: FF_X23_Y5_N7 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~46_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\); + +-- Location: LABCELL_X24_Y6_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~54_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.START_INIT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~54_combout\); + +-- Location: LABCELL_X24_Y7_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ & ((!\myVirtualToplevel|SD_HNDSHK_IN\(0)) +-- # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100100010001100110010001000110011000000000011001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\); + +-- Location: LABCELL_X25_Y6_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~55_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~54_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\ ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101000100011101010111010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~51_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~48_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~54_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o[3]~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~49_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~55_combout\); + +-- Location: FF_X25_Y6_N38 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~55_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\); + +-- Location: LABCELL_X24_Y9_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector15~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector15~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector15~0_combout\); + +-- Location: FF_X24_Y9_N2 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector15~0_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0), + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(0)); + +-- Location: MLABCELL_X18_Y9_N39 +\myVirtualToplevel|IO_DATA_READ_SD[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[16]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(0), + combout => \myVirtualToplevel|IO_DATA_READ_SD[16]~feeder_combout\); + +-- Location: MLABCELL_X9_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\); + +-- Location: FF_X9_Y15_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_NEW_REG785\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\); + +-- Location: FF_X10_Y16_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG504\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\); + +-- Location: FF_X10_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_NEW_REG781\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM782\); + +-- Location: LABCELL_X10_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector18~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector18~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000000000000000110011111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector18~0_combout\); + +-- Location: FF_X20_Y39_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1434\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\); + +-- Location: LABCELL_X12_Y17_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # ((\myVirtualToplevel|MEM_BUSY~1_combout\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011011111111111111101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\); + +-- Location: LABCELL_X16_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\); + +-- Location: MLABCELL_X13_Y38_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000000000110011000000000011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\); + +-- Location: LABCELL_X16_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111011111110111100000000000000001100110011101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~38_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~0_combout\); + +-- Location: LABCELL_X16_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000010000000000000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\); + +-- Location: LABCELL_X14_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_RESYN12644\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_RESYN12644_BDD12645\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111001100110011001111110000111100000011000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_RESYN12644_BDD12645\); + +-- Location: LABCELL_X14_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_RESYN12644_BDD12645\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011010000010100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_RESYN12644_BDD12645\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\); + +-- Location: LABCELL_X16_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\); + +-- Location: LABCELL_X16_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\); + +-- Location: LABCELL_X14_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\); + +-- Location: LABCELL_X16_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010001010100010001001111111101010000010100000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1_combout\); + +-- Location: LABCELL_X16_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000000000000001010100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2_combout\); + +-- Location: LABCELL_X16_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111101001111010001010101000000001111010111110100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~1_combout\); + +-- Location: FF_X16_Y35_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\); + +-- Location: LABCELL_X14_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\); + +-- Location: LABCELL_X21_Y22_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\); + +-- Location: LABCELL_X16_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1_combout\); + +-- Location: LABCELL_X16_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~1_combout\); + +-- Location: LABCELL_X16_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010010100010111000011011110010000000010011110110000101011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\); + +-- Location: LABCELL_X17_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001110000000001100111000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr171~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2_combout\); + +-- Location: LABCELL_X16_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~1_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111010100000000011101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector363~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\); + +-- Location: LABCELL_X16_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid_NEW3341\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid_OTERM3342\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110001001100110011000100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid_OTERM3342\); + +-- Location: FF_X16_Y29_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid_OTERM3342\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100000000000001010000000100000001000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\); + +-- Location: LABCELL_X12_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\); + +-- Location: LABCELL_X12_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000000000010000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\); + +-- Location: FF_X13_Y36_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\); + +-- Location: MLABCELL_X13_Y36_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111110001010110011111000101011001111100010101111111110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\); + +-- Location: MLABCELL_X13_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110100000000001111010000000000111111000000000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\); + +-- Location: MLABCELL_X13_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111011001110111000000000000000001111110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\); + +-- Location: MLABCELL_X13_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000000010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector502~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\); + +-- Location: MLABCELL_X13_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111110111001111111100000000000000001101110011011100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4_combout\); + +-- Location: FF_X13_Y36_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\); + +-- Location: LABCELL_X17_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101100000000001110111000000000111111000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\); + +-- Location: LABCELL_X16_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001000111111001100000011111100100010001011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\); + +-- Location: LABCELL_X17_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\); + +-- Location: LABCELL_X17_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101111111110100010100000000000000001111111101000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~1_combout\); + +-- Location: FF_X17_Y34_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\); + +-- Location: MLABCELL_X9_Y37_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\); + +-- Location: LABCELL_X6_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011001000110010001100001111000011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\); + +-- Location: LABCELL_X16_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000000010000010100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\); + +-- Location: LABCELL_X14_Y38_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000010101010001100000000000000110000111111110011000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~56_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\); + +-- Location: LABCELL_X14_Y38_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001110000011000000110000001100000011100000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~56_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\); + +-- Location: LABCELL_X17_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111000001100000011100000111000001111000011000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0_combout\); + +-- Location: LABCELL_X14_Y38_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111110001000111111111000100011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\); + +-- Location: LABCELL_X14_Y36_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\); + +-- Location: LABCELL_X14_Y38_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001101000111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\); + +-- Location: LABCELL_X14_Y38_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\); + +-- Location: LABCELL_X14_Y38_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000001000100010000000100010001000100010001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\); + +-- Location: LABCELL_X14_Y38_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111011101110100000000111111111111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector568~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_combout\); + +-- Location: FF_X14_Y38_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\); + +-- Location: LABCELL_X14_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1_combout\); + +-- Location: LABCELL_X16_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\); + +-- Location: LABCELL_X16_Y36_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101011100000011010101110000001100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\); + +-- Location: LABCELL_X16_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000000000111100000111000001110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\); + +-- Location: LABCELL_X16_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\); + +-- Location: LABCELL_X16_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100001111111111110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\); + +-- Location: LABCELL_X16_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640_BDD12641\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640_BDD12641\); + +-- Location: LABCELL_X16_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640_BDD12641\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640_BDD12641\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010111011000010110011001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_RESYN12640_BDD12641\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\); + +-- Location: LABCELL_X16_Y36_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111101111111111111110111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\); + +-- Location: LABCELL_X16_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011111111110010001100110011001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_combout\); + +-- Location: FF_X16_Y36_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\); + +-- Location: LABCELL_X10_Y36_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111111111100001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\); + +-- Location: LABCELL_X14_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001100000011110000111100001101000011000000110100001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~28_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0_combout\); + +-- Location: FF_X14_Y34_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000010100000000000111011001100110011101100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1_combout\); + +-- Location: LABCELL_X14_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ +-- & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000000000111000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\); + +-- Location: LABCELL_X14_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001111101011111000100000000000000001111010111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0_combout\); + +-- Location: FF_X14_Y34_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\); + +-- Location: FF_X14_Y37_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\); + +-- Location: LABCELL_X10_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\); + +-- Location: MLABCELL_X13_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001101110000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\); + +-- Location: LABCELL_X14_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001100101010001111110010101000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\); + +-- Location: MLABCELL_X13_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\); + +-- Location: LABCELL_X14_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000000000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\); + +-- Location: LABCELL_X14_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110111111101111111011111110111111101111111010000000011111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\); + +-- Location: LABCELL_X14_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000000111111111111111100110000000000000011001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3_combout\); + +-- Location: FF_X14_Y37_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\); + +-- Location: MLABCELL_X9_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\); + +-- Location: FF_X13_Y39_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\); + +-- Location: MLABCELL_X13_Y39_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011101110111111111010111010101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\); + +-- Location: MLABCELL_X13_Y39_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\)) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111111011000000111111001100000011101010110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1_combout\); + +-- Location: MLABCELL_X13_Y39_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000000000010000010100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\); + +-- Location: MLABCELL_X13_Y39_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111110011101100111100000000000000001100111011001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0_combout\); + +-- Location: FF_X13_Y39_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\)))) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100111111000001010011000011110101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0_combout\); + +-- Location: MLABCELL_X13_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2_combout\); + +-- Location: LABCELL_X12_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & !\myVirtualToplevel|MEM_BUSY~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\); + +-- Location: LABCELL_X12_Y17_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111011001111111111101100111111111110110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~54_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~53_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~55_combout\); + +-- Location: FF_X12_Y17_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~55_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\); + +-- Location: LABCELL_X17_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000000000000011000000000000111111000000000011111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\); + +-- Location: LABCELL_X20_Y10_N9 +\myVirtualToplevel|Mux74~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux74~0_combout\ = ( !\myVirtualToplevel|SD_STATE.SD_STATE_READ~q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & (!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\ & !\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\, + datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~q\, + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~q\, + combout => \myVirtualToplevel|Mux74~0_combout\); + +-- Location: FF_X10_Y32_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\); + +-- Location: FF_X10_Y34_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_NEW_REG1404\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\); + +-- Location: FF_X10_Y34_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_NEW_REG1402\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\); + +-- Location: LABCELL_X14_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001000000000010000100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\); + +-- Location: LABCELL_X14_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000000000001000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\); + +-- Location: LABCELL_X14_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011110000110000001111000010000000101000001000000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\); + +-- Location: LABCELL_X14_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000110011001000000011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\); + +-- Location: LABCELL_X16_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\); + +-- Location: LABCELL_X16_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\); + +-- Location: LABCELL_X10_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\)) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000000010100000000000001010000010100000101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0_combout\); + +-- Location: MLABCELL_X13_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\); + +-- Location: LABCELL_X12_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\); + +-- Location: MLABCELL_X9_Y34_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010111011101000001011000010101010111111111010000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~54_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~2_RESYN12428_BDD12429\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_combout\); + +-- Location: LABCELL_X10_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010110000000000001011000000000000101000000000000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~0_combout\); + +-- Location: FF_X10_Y34_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_NEW_REG1406\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\); + +-- Location: LABCELL_X10_Y34_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100101111111100110000001100000011001000110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\); + +-- Location: LABCELL_X14_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\); + +-- Location: MLABCELL_X9_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434_BDD12435\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434_BDD12435\); + +-- Location: MLABCELL_X9_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434_BDD12435\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434_BDD12435\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000101111111001100110011000000000001001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~51_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~2_RESYN12434_BDD12435\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_combout\); + +-- Location: LABCELL_X16_Y35_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100000001000000110011000100000011001100010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~35_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\); + +-- Location: LABCELL_X10_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000000001100000000000000110000001100000011000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~0_combout\); + +-- Location: MLABCELL_X9_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000010000011110000001000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~0_combout\); + +-- Location: FF_X9_Y34_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_NEW_REG1360\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\); + +-- Location: MLABCELL_X9_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110101111101011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\); + +-- Location: FF_X9_Y34_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_NEW_REG1362\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\); + +-- Location: FF_X9_Y34_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_NEW_REG1358\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\); + +-- Location: FF_X9_Y34_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\); + +-- Location: MLABCELL_X9_Y34_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110101000001000100010001001111111101010100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\); + +-- Location: MLABCELL_X13_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\); + +-- Location: MLABCELL_X9_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\); + +-- Location: MLABCELL_X9_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010100000101110111011000010101010101000001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~2_RESYN12432_BDD12433\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_combout\); + +-- Location: LABCELL_X10_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000000010100000000000001010000010100000101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector501~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~0_combout\); + +-- Location: LABCELL_X10_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001010000010110000101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~0_combout\); + +-- Location: FF_X10_Y34_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_NEW_REG1366\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\); + +-- Location: FF_X9_Y34_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_NEW_REG1292\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\); + +-- Location: FF_X10_Y34_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_NEW_REG1364\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\); + +-- Location: MLABCELL_X13_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\); + +-- Location: FF_X13_Y34_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_NEW_REG1368\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\); + +-- Location: LABCELL_X10_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011111111000000100011001100000010111111110000001000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\); + +-- Location: FF_X10_Y34_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_NEW_REG1284\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\); + +-- Location: FF_X10_Y34_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_NEW_REG1286\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\); + +-- Location: LABCELL_X17_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\)) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000000010100000000000001010000010100000101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~0_combout\); + +-- Location: LABCELL_X14_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\); + +-- Location: LABCELL_X12_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000110000001100000011000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\); + +-- Location: LABCELL_X17_Y35_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010111011101000001011000010101010111111111010000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~2_RESYN12430_BDD12431\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~44_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_combout\); + +-- Location: LABCELL_X17_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010111010000000001011101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~3_combout\); + +-- Location: FF_X17_Y35_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_NEW_REG1288\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\); + +-- Location: LABCELL_X10_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001100010111010101110100001101000011000000110100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\); + +-- Location: LABCELL_X10_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001000110100010101100111000010011010101111001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1_combout\); + +-- Location: FF_X12_Y34_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1055\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\); + +-- Location: FF_X12_Y34_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_NEW_REG1370\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\); + +-- Location: LABCELL_X12_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\); + +-- Location: LABCELL_X17_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\); + +-- Location: LABCELL_X17_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000101000001010000011110011111111111010001010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~47_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~2_RESYN12424_BDD12425\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_combout\); + +-- Location: LABCELL_X17_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000000010100000000000001010000010100000101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~0_combout\); + +-- Location: LABCELL_X17_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001010000010110000101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~0_combout\); + +-- Location: FF_X17_Y35_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_NEW_REG1372\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\); + +-- Location: LABCELL_X12_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011101110111010101100000000000000001011101110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\); + +-- Location: FF_X10_Y33_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_NEW_REG1620\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\); + +-- Location: LABCELL_X16_Y36_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100110011111111110011001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\); + +-- Location: FF_X16_Y36_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_NEW_REG1622\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\); + +-- Location: LABCELL_X14_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\); + +-- Location: LABCELL_X17_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\); + +-- Location: LABCELL_X17_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010100000000010111111101111111011111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~40_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~5_RESYN12420_BDD12421\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_combout\); + +-- Location: LABCELL_X17_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000000010100000000000001010000010100000101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~3_combout\); + +-- Location: LABCELL_X17_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111010000000001011101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~0_combout\); + +-- Location: FF_X17_Y32_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_NEW_REG1624\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\); + +-- Location: LABCELL_X10_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001110101111000000111010101100000000101011110000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\); + +-- Location: FF_X9_Y34_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG985\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\); + +-- Location: LABCELL_X14_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\); + +-- Location: MLABCELL_X9_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\); + +-- Location: MLABCELL_X9_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010111111111010101000000000000000000011111100101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~2_RESYN12426_BDD12427\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_combout\); + +-- Location: MLABCELL_X9_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000000010100000000000001010101000000000101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~0_combout\); + +-- Location: MLABCELL_X9_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001010000010110000101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~3_combout\); + +-- Location: FF_X9_Y34_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_NEW_REG1294\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\); + +-- Location: FF_X9_Y34_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_NEW_REG1290\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\); + +-- Location: MLABCELL_X9_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110011111111111111110000101000001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\); + +-- Location: LABCELL_X14_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\); + +-- Location: LABCELL_X10_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\); + +-- Location: LABCELL_X10_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010001000101011111000110010101111100011001010111110001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~41_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~2_RESYN12422_BDD12423\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_combout\); + +-- Location: LABCELL_X10_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000111100001010000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0_combout\); + +-- Location: LABCELL_X10_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000000010000000000000001000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~0_combout\); + +-- Location: FF_X10_Y34_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_NEW_REG1450\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\); + +-- Location: MLABCELL_X13_Y38_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\); + +-- Location: FF_X13_Y38_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_NEW_REG1452\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\); + +-- Location: FF_X10_Y34_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_NEW_REG1448\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\); + +-- Location: LABCELL_X10_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010001000100010011111111010100001111111101010100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\); + +-- Location: LABCELL_X10_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100111101001100011100110111000001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0_combout\); + +-- Location: LABCELL_X10_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2_combout\); + +-- Location: LABCELL_X10_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~60\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~60_combout\ = ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\))) ) ) ) # ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000000000000000000000000100000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~60_combout\); + +-- Location: LABCELL_X17_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~59_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) # +-- (\myVirtualToplevel|MEM_BUSY~1_combout\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101111111111111110111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~59_combout\); + +-- Location: LABCELL_X17_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~61_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~60_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~59_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101111110011000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~60_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~59_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~61_combout\); + +-- Location: FF_X17_Y17_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~61_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\); + +-- Location: LABCELL_X24_Y9_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector6~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector6~0_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(9))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001110001011000000111000101100000011100010110000001110001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector3~1_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(9), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector6~0_combout\); + +-- Location: FF_X24_Y9_N49 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector6~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(9)); + +-- Location: LABCELL_X21_Y9_N15 +\myVirtualToplevel|IO_DATA_READ_SD[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[25]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(9) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(9), + combout => \myVirtualToplevel|IO_DATA_READ_SD[25]~feeder_combout\); + +-- Location: LABCELL_X10_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\); + +-- Location: LABCELL_X16_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~53_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]~feeder_combout\); + +-- Location: FF_X16_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(25)); + +-- Location: LABCELL_X16_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[25]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[25]~feeder_combout\); + +-- Location: MLABCELL_X4_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\); + +-- Location: LABCELL_X7_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\); + +-- Location: LABCELL_X19_Y4_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & \myVirtualToplevel|RESET_n~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datad => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0_combout\); + +-- Location: LABCELL_X19_Y11_N6 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~3_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010111010101010101011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~3_combout\); + +-- Location: FF_X19_Y11_N7 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\); + +-- Location: FF_X19_Y12_N50 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_NEW_REG8\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\); + +-- Location: LABCELL_X19_Y12_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux110~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux110~0_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100000000000000000000000000000001000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux110~0_combout\); + +-- Location: FF_X19_Y12_N2 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux110~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\); + +-- Location: IOIBUF_X29_Y0_N35 +\SDRAM_DQ[0]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(0), + o => \SDRAM_DQ[0]~input_o\); + +-- Location: DDIOINCELL_X29_Y0_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_NEW_REG10\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[0]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\); + +-- Location: LABCELL_X19_Y12_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\ ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111000000000000111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]_OTERM9\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]_OTERM11\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\); + +-- Location: FF_X9_Y25_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~35_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\); + +-- Location: FF_X10_Y25_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~32_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(12)); + +-- Location: LABCELL_X17_Y14_N27 +\myVirtualToplevel|MEM_DATA_READ[10]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ = ( \myVirtualToplevel|LessThan0~0_combout\ ) # ( !\myVirtualToplevel|LessThan0~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(23), + dataf => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\); + +-- Location: LABCELL_X20_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~feeder_combout\); + +-- Location: FF_X20_Y18_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE_q\); + +-- Location: FF_X20_Y18_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(10)); + +-- Location: LABCELL_X20_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\); + +-- Location: LABCELL_X12_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000101010001010100011111001100000000000000000000000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\); + +-- Location: LABCELL_X12_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000100000001000010011000100010001001100010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[18]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_RESYN8483_BDD8484\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\); + +-- Location: LABCELL_X12_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]_NEW3177\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]_OTERM3178\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]_OTERM3178\); + +-- Location: FF_X12_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]_OTERM3178\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10)); + +-- Location: LABCELL_X12_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\); + +-- Location: LABCELL_X12_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101011111010101010101111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\); + +-- Location: LABCELL_X12_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\))) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100110001000100010011000100110001001100010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\); + +-- Location: LABCELL_X12_Y23_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]_NEW3049\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]_OTERM3050\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(10))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]_OTERM3050\); + +-- Location: FF_X12_Y23_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]_OTERM3050\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(10)); + +-- Location: MLABCELL_X13_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011011100110111001101110011011100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\); + +-- Location: MLABCELL_X13_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000111111001100000011000000111010001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\); + +-- Location: LABCELL_X12_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]_NEW2985\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]_OTERM2986\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101000100011010111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]_OTERM2986\); + +-- Location: FF_X12_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]_OTERM2986\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10)); + +-- Location: LABCELL_X12_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ +-- & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000011100000111011100000000000000000100000001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\); + +-- Location: LABCELL_X12_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000010001000010001001100010001000100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[26]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_RESYN8487_BDD8488\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\); + +-- Location: LABCELL_X12_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]_NEW3113\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]_OTERM3114\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]_OTERM3114\); + +-- Location: FF_X12_Y20_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]_OTERM3114\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10)); + +-- Location: LABCELL_X12_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(10)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(10)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0_combout\); + +-- Location: LABCELL_X10_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]_NEW2793\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]_OTERM2794\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]_OTERM2794\); + +-- Location: FF_X10_Y21_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]_OTERM2794\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10)); + +-- Location: MLABCELL_X9_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]_NEW2857\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]_OTERM2858\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]_OTERM2858\); + +-- Location: FF_X9_Y22_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]_OTERM2858\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10)); + +-- Location: LABCELL_X12_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101011111000011110101111100000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~1_combout\); + +-- Location: LABCELL_X12_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100011011000100010001000100010001101110110001000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\); + +-- Location: LABCELL_X6_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]_NEW2729\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]_OTERM2730\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001001100011100110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]_OTERM2730\); + +-- Location: FF_X6_Y21_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]_OTERM2730\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10)); + +-- Location: LABCELL_X12_Y25_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\); + +-- Location: LABCELL_X12_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000111010001110100011101000100010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\); + +-- Location: LABCELL_X6_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]_NEW2921\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]_OTERM2922\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]_OTERM2922\); + +-- Location: FF_X6_Y21_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]_OTERM2922\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10)); + +-- Location: LABCELL_X6_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100110001000011010011110111000001111100011100110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1_combout\); + +-- Location: MLABCELL_X9_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux95~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux95~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux95~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~2_combout\); + +-- Location: MLABCELL_X9_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\); + +-- Location: FF_X9_Y14_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~2_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10)); + +-- Location: MLABCELL_X13_Y10_N3 +\myVirtualToplevel|UART1|Equal7~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal7~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|UART1|Equal7~0_combout\); + +-- Location: LABCELL_X19_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~feeder_combout\); + +-- Location: FF_X19_Y17_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE_q\); + +-- Location: FF_X20_Y15_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(15)); + +-- Location: LABCELL_X19_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[15]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\); + +-- Location: LABCELL_X6_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]_NEW2925\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]_OTERM2926\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010100111111111101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]_OTERM2926\); + +-- Location: FF_X6_Y21_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]_OTERM2926\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15)); + +-- Location: LABCELL_X6_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]_NEW2733\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]_OTERM2734\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101000000111111010111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]_OTERM2734\); + +-- Location: FF_X6_Y21_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]_OTERM2734\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15)); + +-- Location: MLABCELL_X9_Y22_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]_NEW2861\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]_OTERM2862\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(15))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]_OTERM2862\); + +-- Location: FF_X9_Y22_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]_OTERM2862\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(15)); + +-- Location: MLABCELL_X9_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]_NEW2797\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]_OTERM2798\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]_OTERM2798\); + +-- Location: FF_X9_Y22_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]_OTERM2798\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15)); + +-- Location: LABCELL_X6_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(15)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(15)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011000000001111000001010011010100110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\); + +-- Location: LABCELL_X7_Y22_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]_NEW3117\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]_OTERM3118\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]_OTERM3118\); + +-- Location: FF_X7_Y22_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]_OTERM3118\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15)); + +-- Location: LABCELL_X7_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]_NEW3181\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]_OTERM3182\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]_OTERM3182\); + +-- Location: FF_X7_Y22_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]_OTERM3182\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15)); + +-- Location: LABCELL_X7_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]_NEW2989\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]_OTERM2990\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000100111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]_OTERM2990\); + +-- Location: FF_X7_Y22_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]_OTERM2990\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15)); + +-- Location: LABCELL_X12_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]_NEW3053\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]_OTERM3054\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101111101011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]_OTERM3054\); + +-- Location: FF_X12_Y24_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]_OTERM3054\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15)); + +-- Location: LABCELL_X7_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010100010000001111010011101010010111100100101011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\); + +-- Location: LABCELL_X7_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2_combout\); + +-- Location: MLABCELL_X9_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]~feeder_combout\); + +-- Location: FF_X9_Y14_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15)); + +-- Location: MLABCELL_X18_Y9_N48 +\myVirtualToplevel|SD_ADDR[0][15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(15), + combout => \myVirtualToplevel|SD_ADDR[0][15]~feeder_combout\); + +-- Location: FF_X18_Y9_N49 +\myVirtualToplevel|SD_ADDR[0][15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][15]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][15]~q\); + +-- Location: LABCELL_X19_Y9_N39 +\myVirtualToplevel|Mux68~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux68~0_combout\ = ( \myVirtualToplevel|SD_ADDR[0][15]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|SD_RESET\(0))) ) ) # ( !\myVirtualToplevel|SD_ADDR[0][15]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- \myVirtualToplevel|SD_RESET\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001000000010000000110001001100010011000100110001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + dataf => \myVirtualToplevel|ALT_INV_SD_ADDR[0][15]~q\, + combout => \myVirtualToplevel|Mux68~0_combout\); + +-- Location: LABCELL_X21_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\ & ( (((\myVirtualToplevel|MEM_BUSY~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & !\myVirtualToplevel|MEM_BUSY~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000000000000010000000000001111111111111110111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\); + +-- Location: LABCELL_X21_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr2~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\); + +-- Location: LABCELL_X21_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000000000000000000010100000101000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\); + +-- Location: LABCELL_X21_Y15_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) # (\myVirtualToplevel|MEM_BUSY~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\ & +-- (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\)) # (\myVirtualToplevel|MEM_BUSY~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000100110011001100110011001100110001000100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~1_combout\); + +-- Location: FF_X21_Y15_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\); + +-- Location: LABCELL_X19_Y9_N27 +\myVirtualToplevel|IO_DATA_READ_SD[31]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (\myVirtualToplevel|RESET_n~q\ & \myVirtualToplevel|SD_CS~combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100000000000000010000000000000001000000000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datac => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datad => \myVirtualToplevel|ALT_INV_SD_CS~combout\, + combout => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\); + +-- Location: FF_X19_Y9_N40 +\myVirtualToplevel|IO_DATA_READ_SD[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux68~0_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(15)); + +-- Location: FF_X10_Y32_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_NEW_REG1408\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1409\); + +-- Location: LABCELL_X17_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000000000000000110011001100110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\); + +-- Location: LABCELL_X17_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101010000000001010101000000000101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\); + +-- Location: LABCELL_X17_Y16_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111100001111010111110000111101011111000000000101111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\); + +-- Location: FF_X19_Y12_N5 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_NEW_REG40\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM41\); + +-- Location: IOIBUF_X19_Y0_N52 +\SDRAM_DQ[7]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(7), + o => \SDRAM_DQ[7]~input_o\); + +-- Location: DDIOINCELL_X19_Y0_N65 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_NEW_REG42\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[7]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\); + +-- Location: LABCELL_X19_Y12_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM41\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM41\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000001011111111100000000111110100000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM41\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM43\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\); + +-- Location: FF_X13_Y14_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1)); + +-- Location: MLABCELL_X13_Y14_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111101010000000000000101000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1_combout\); + +-- Location: MLABCELL_X13_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100011111000100010001111100010001000100010001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr116~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~2_combout\); + +-- Location: FF_X13_Y14_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\); + +-- Location: FF_X6_Y26_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~59_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(6)); + +-- Location: FF_X10_Y25_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~47_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(5)); + +-- Location: LABCELL_X7_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001100000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~50\); + +-- Location: MLABCELL_X4_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~50\); + +-- Location: LABCELL_X10_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~49_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~42_combout\); + +-- Location: LABCELL_X6_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~50\); + +-- Location: MLABCELL_X9_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\); + +-- Location: LABCELL_X10_Y25_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111101011111111111110101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\); + +-- Location: LABCELL_X10_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000000000000010100000000000001000000000000000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\); + +-- Location: LABCELL_X10_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~49_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~49_sumout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp~42_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add21~49_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp~42_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add21~49_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~49_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~42_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~49_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\); + +-- Location: LABCELL_X10_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[4]~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[4]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111111111111100000000000000001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~43_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[4]~44_combout\); + +-- Location: FF_X10_Y24_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[4]~44_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)); + +-- Location: MLABCELL_X4_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~54\); + +-- Location: MLABCELL_X4_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~53_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~45_combout\); + +-- Location: LABCELL_X6_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~54\); + +-- Location: LABCELL_X7_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~54\); + +-- Location: LABCELL_X19_Y12_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux94~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux94~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux94~0_combout\); + +-- Location: FF_X19_Y12_N13 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_NEW_REG12\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux94~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\); + +-- Location: IOIBUF_X24_Y0_N1 +\SDRAM_DQ[13]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(13), + o => \SDRAM_DQ[13]~input_o\); + +-- Location: DDIOINCELL_X24_Y0_N14 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_NEW_REG88\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[13]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\); + +-- Location: FF_X21_Y13_N59 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_NEW_REG86\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM87\); + +-- Location: LABCELL_X21_Y13_N6 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM87\ ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM87\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM87\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000110000001111111100111111001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]_OTERM89\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]_OTERM87\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27_combout\); + +-- Location: FF_X16_Y14_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]_OTERM3336\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~DUPLICATE_q\); + +-- Location: IOIBUF_X22_Y0_N52 +\SDRAM_DQ[2]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(2), + o => \SDRAM_DQ[2]~input_o\); + +-- Location: DDIOINCELL_X22_Y0_N65 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_NEW_REG32\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[2]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\); + +-- Location: FF_X21_Y12_N19 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_NEW_REG64\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_OTERM65\); + +-- Location: LABCELL_X21_Y12_N15 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_OTERM65\ ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_OTERM65\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\) # +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_OTERM65\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000110000001111111100111111001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM33\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[18]_OTERM65\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10_combout\); + +-- Location: LABCELL_X24_Y9_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector13~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector13~0_combout\ = (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(2)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(2), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector13~0_combout\); + +-- Location: FF_X24_Y9_N14 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector13~0_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2), + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(2)); + +-- Location: MLABCELL_X18_Y9_N30 +\myVirtualToplevel|IO_DATA_READ_SD[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[18]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(2) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(2), + combout => \myVirtualToplevel|IO_DATA_READ_SD[18]~feeder_combout\); + +-- Location: FF_X10_Y15_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_NEW_REG921\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM922\); + +-- Location: IOIBUF_X24_Y0_N18 +\SDRAM_DQ[10]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(10), + o => \SDRAM_DQ[10]~input_o\); + +-- Location: DDIOINCELL_X24_Y0_N31 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_NEW_REG24\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[10]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM25\); + +-- Location: FF_X20_Y12_N52 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_NEW_REG22\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM23\); + +-- Location: LABCELL_X20_Y12_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM23\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\) # +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM25\)) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM23\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM25\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010001000000000001000111101110111111111110111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]_OTERM25\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]_OTERM23\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31_combout\); + +-- Location: FF_X34_Y19_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1692~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(6)); + +-- Location: LABCELL_X35_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~14\); + +-- Location: LABCELL_X35_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~14\); + +-- Location: MLABCELL_X34_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1678~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1678~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add56~13_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add56~13_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1678~0_combout\); + +-- Location: FF_X34_Y19_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1678~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20)); + +-- Location: LABCELL_X35_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(21), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~6\); + +-- Location: LABCELL_X35_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(21), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~6\); + +-- Location: LABCELL_X35_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1677~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1677~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~5_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add44~5_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1677~0_combout\); + +-- Location: FF_X35_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1677~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21)); + +-- Location: LABCELL_X35_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(22), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~10\); + +-- Location: FF_X35_Y20_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1676~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE_q\); + +-- Location: LABCELL_X35_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[22]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~10\); + +-- Location: LABCELL_X35_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1676~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1676~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add56~9_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add56~9_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1676~0_combout\); + +-- Location: FF_X35_Y20_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1676~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(22)); + +-- Location: FF_X10_Y25_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_NEW_REG893\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM894\); + +-- Location: FF_X6_Y25_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_NEW_REG891\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM892\); + +-- Location: FF_X5_Y25_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_NEW_REG1176\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1177\); + +-- Location: LABCELL_X17_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\); + +-- Location: FF_X20_Y17_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(19)); + +-- Location: FF_X20_Y17_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(19)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(19)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[19]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\); + +-- Location: FF_X20_Y17_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18)); + +-- Location: LABCELL_X20_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~feeder_combout\); + +-- Location: LABCELL_X20_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101010101010000010101010101000001010101010100000101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\); + +-- Location: FF_X19_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~25_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(18)); + +-- Location: LABCELL_X12_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~29_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) # ( +-- !\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~107_Duplicate_164\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~29_combout\); + +-- Location: FF_X12_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_NEW_REG552\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~29_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM553\); + +-- Location: LABCELL_X12_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\)))) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000110011000010100000101001011111001100110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~107_Duplicate_164\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~28_combout\); + +-- Location: FF_X12_Y15_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_NEW_REG550\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~28_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM551\); + +-- Location: FF_X12_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_NEW_REG548\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM549\); + +-- Location: FF_X12_Y16_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG508\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\); + +-- Location: LABCELL_X12_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM549\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM549\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM551\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM553\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM549\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM551\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM553\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011111111110001101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM553\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM551\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM549\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\); + +-- Location: LABCELL_X21_Y10_N21 +\myVirtualToplevel|Mux75~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux75~0_combout\ = ( !\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & ( (\myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\ & (!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\ & !\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000000010100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~q\, + datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\, + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\, + combout => \myVirtualToplevel|Mux75~0_combout\); + +-- Location: LABCELL_X20_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~feeder_combout\); + +-- Location: LABCELL_X16_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\); + +-- Location: LABCELL_X20_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\)))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "1111111111111111111111111111111101010001010101010101000101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~0_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\); + +-- Location: LABCELL_X29_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\); + +-- Location: LABCELL_X25_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\); + +-- Location: LABCELL_X26_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_RESYN12624\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_RESYN12624_BDD12625\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110000010100000101000001010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~37_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~45_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~29_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~49_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_RESYN12624_BDD12625\); + +-- Location: LABCELL_X26_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_RESYN12624_BDD12625\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~13_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~9_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~1_RESYN12624_BDD12625\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\); + +-- Location: LABCELL_X26_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~62\); + +-- Location: LABCELL_X26_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~66\); + +-- Location: LABCELL_X26_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~70\); + +-- Location: LABCELL_X26_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~54\); + +-- Location: LABCELL_X26_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~58\); + +-- Location: LABCELL_X26_Y24_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~53_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~65_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~65_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~53_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~5_combout\); + +-- Location: LABCELL_X26_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_RESYN12628\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_RESYN12628_BDD12629\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~69_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~61_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~93_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~93_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~69_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_RESYN12628_BDD12629\); + +-- Location: LABCELL_X26_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~77_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_RESYN12628_BDD12629\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~85_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~73_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~89_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~81_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~85_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~73_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~89_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~81_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~77_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~7_RESYN12628_BDD12629\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_combout\); + +-- Location: LABCELL_X26_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~57_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~1_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~57_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\); + +-- Location: LABCELL_X12_Y24_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~1_combout\); + +-- Location: FF_X18_Y14_N32 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG4\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM5\); + +-- Location: IOIBUF_X29_Y0_N52 +\SDRAM_DQ[1]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(1), + o => \SDRAM_DQ[1]~input_o\); + +-- Location: DDIOINCELL_X29_Y0_N65 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG6\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[1]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM7\); + +-- Location: MLABCELL_X18_Y14_N39 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM7\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM5\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM7\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM5\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001010000011110000101000001111010111110000111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM5\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM7\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\); + +-- Location: LABCELL_X12_Y9_N3 +\myVirtualToplevel|UART0|RX_ENABLE_FIFO~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_ENABLE_FIFO~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + combout => \myVirtualToplevel|UART0|RX_ENABLE_FIFO~0_combout\); + +-- Location: IOIBUF_X22_Y0_N35 +\SDRAM_DQ[5]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(5), + o => \SDRAM_DQ[5]~input_o\); + +-- Location: DDIOINCELL_X22_Y0_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_NEW_REG56\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[5]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\); + +-- Location: FF_X20_Y12_N43 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_NEW_REG74\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_OTERM75\); + +-- Location: LABCELL_X21_Y12_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_OTERM75\ ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_OTERM75\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\) # +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_OTERM75\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000110000001111111100111111001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM57\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[21]_OTERM75\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5_combout\); + +-- Location: LABCELL_X12_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000000000000000000000000001000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\); + +-- Location: MLABCELL_X9_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010001111100010101000111110001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\); + +-- Location: LABCELL_X14_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111110100000000011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\); + +-- Location: LABCELL_X12_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110000000000010111010000000001011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~3_combout\); + +-- Location: LABCELL_X14_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|state~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000011111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\); + +-- Location: LABCELL_X17_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000100000000000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\); + +-- Location: LABCELL_X12_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157_BDD9158\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111100110010101111101011111010111110001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157_BDD9158\); + +-- Location: LABCELL_X14_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001000000000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\); + +-- Location: LABCELL_X12_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) +-- # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000111111111111000000110011001100000011001100110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\); + +-- Location: LABCELL_X12_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100001111111111110000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\); + +-- Location: LABCELL_X12_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_BDD9162\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000001110000111100001111000011111111011101111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_BDD9162\); + +-- Location: LABCELL_X14_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010000110001000010000001001011001000000101101111000000110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\); + +-- Location: MLABCELL_X13_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000010000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\); + +-- Location: MLABCELL_X13_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809_BDD8810\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111110000000011111111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809_BDD8810\); + +-- Location: MLABCELL_X13_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809_BDD8810\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809_BDD8810\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001111000000100000001000000000000011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~0_RESYN8809_BDD8810\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\); + +-- Location: MLABCELL_X13_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159_BDD9160\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011100000111011100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159_BDD9160\); + +-- Location: LABCELL_X12_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_BDD9162\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159_BDD9160\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157_BDD9158\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\)))) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000010001000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9157_BDD9158\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~38_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_BDD9162\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9159_BDD9160\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_combout\); + +-- Location: LABCELL_X12_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000011111111001100001111111100110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\); + +-- Location: MLABCELL_X4_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101011111010111110101111101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\); + +-- Location: FF_X6_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~50_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(9)); + +-- Location: LABCELL_X6_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~78\); + +-- Location: LABCELL_X6_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(9) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(9) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~58\); + +-- Location: LABCELL_X7_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~70\); + +-- Location: LABCELL_X7_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~74\); + +-- Location: LABCELL_X7_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~78\); + +-- Location: LABCELL_X7_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~58\); + +-- Location: MLABCELL_X4_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~74\); + +-- Location: MLABCELL_X4_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~78\); + +-- Location: MLABCELL_X4_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~58\); + +-- Location: MLABCELL_X4_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~57_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~48_combout\); + +-- Location: LABCELL_X6_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~57_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~48_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~57_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~49_combout\); + +-- Location: LABCELL_X6_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~49_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(9) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\))) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~49_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(9)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111111111000000111111111100000000111111000000000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~49_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~50_combout\); + +-- Location: FF_X6_Y26_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~50_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\); + +-- Location: LABCELL_X7_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~62\); + +-- Location: LABCELL_X7_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~66\); + +-- Location: LABCELL_X12_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011011111000000001101111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\); + +-- Location: LABCELL_X12_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000000001100000000000000110011000000110011001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\); + +-- Location: MLABCELL_X13_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100110000001000000000000000000001001100000010000100110000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\); + +-- Location: LABCELL_X7_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000100010001001100010001000100110000000100010011000000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0_combout\); + +-- Location: FF_X9_Y24_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_NEW_REG1330\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\); + +-- Location: LABCELL_X10_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101000110110000111100010001000000000001000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\); + +-- Location: FF_X10_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_NEW_REG751\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\); + +-- Location: FF_X7_Y16_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\); + +-- Location: FF_X6_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_NEW_REG1332\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\); + +-- Location: LABCELL_X12_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~103_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329~feeder_combout\); + +-- Location: FF_X12_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_NEW_REG1328\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\); + +-- Location: LABCELL_X6_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000111110111111101000000001000001011111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1331\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1333\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1329\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\); + +-- Location: LABCELL_X6_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[0]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[0]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110011000000001111001100001100111111110000110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[0]~2_combout\); + +-- Location: LABCELL_X12_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~33_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) +-- # ( !\myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~33_combout\); + +-- Location: FF_X12_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_NEW_REG540\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~33_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\); + +-- Location: FF_X12_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_NEW_REG536\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\); + +-- Location: FF_X10_Y30_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1526\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\); + +-- Location: LABCELL_X12_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000101011111010000010101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\); + +-- Location: MLABCELL_X9_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~58\); + +-- Location: MLABCELL_X13_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000000001100110000000010100000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\); + +-- Location: LABCELL_X10_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~41_combout\); + +-- Location: FF_X10_Y30_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1532\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~41_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1533\); + +-- Location: MLABCELL_X13_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000000000110000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2_combout\); + +-- Location: MLABCELL_X13_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437_BDD8438\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100010101000001010001010100001111000111110000111100011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437_BDD8438\); + +-- Location: LABCELL_X12_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111101011111010111001100111111111100010011110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\); + +-- Location: LABCELL_X12_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111100000000110011100000000000001111000011110000111000001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~4_RESYN12630_BDD12631\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_combout\); + +-- Location: LABCELL_X10_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435_BDD8436\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010000000100000001000000010000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435_BDD8436\); + +-- Location: LABCELL_X16_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001010000010100000011000011110000011100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7_combout\); + +-- Location: LABCELL_X10_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435_BDD8436\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111111111100001111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8435_BDD8436\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\); + +-- Location: LABCELL_X10_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437_BDD8438\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001000100010001000101111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8437_BDD8438\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8439_BDD8440\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\); + +-- Location: FF_X10_Y28_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1528\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\); + +-- Location: LABCELL_X7_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1074~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1074~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101011111111111111111010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1074~0_combout\); + +-- Location: FF_X7_Y32_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1074~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101110000011101010111000001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\); + +-- Location: FF_X12_Y29_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1530\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\); + +-- Location: LABCELL_X10_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1533\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010100000101111101010101010101010101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1527\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1533\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1529\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1531\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\); + +-- Location: LABCELL_X12_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101111000001011010111100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\); + +-- Location: LABCELL_X14_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111001000000000011100100000000000000000000000000111001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\); + +-- Location: LABCELL_X10_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~37_combout\); + +-- Location: FF_X10_Y30_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1542\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~37_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1543\); + +-- Location: FF_X10_Y30_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1536\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1537\); + +-- Location: LABCELL_X12_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011010101110001001101010111000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\); + +-- Location: FF_X12_Y29_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1540\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\); + +-- Location: LABCELL_X14_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100000000001100110010001000100010000000000010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\); + +-- Location: LABCELL_X14_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010100001010000000001001001000000100000110100000001000011100110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\); + +-- Location: LABCELL_X14_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000101010001000100010101000100010001010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~0_combout\); + +-- Location: LABCELL_X14_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000001000000010000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\); + +-- Location: LABCELL_X14_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000100110000001100010011000100110001001100010011000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3_combout\); + +-- Location: LABCELL_X14_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000000000110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\); + +-- Location: LABCELL_X14_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783_BDD8784\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100101010001010100011111100000000001010100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~41_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783_BDD8784\); + +-- Location: LABCELL_X14_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785_BDD8786\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111010100000111011101010000011101110101010101110111010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785_BDD8786\); + +-- Location: LABCELL_X14_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783_BDD8784\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785_BDD8786\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783_BDD8784\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785_BDD8786\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101000100000000000000000000000001111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_RESYN8783_BDD8784\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_RESYN8785_BDD8786\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_combout\); + +-- Location: LABCELL_X14_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110111011101110111011101110100000000110100000000000011010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\); + +-- Location: FF_X14_Y29_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1538\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\); + +-- Location: LABCELL_X10_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1537\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1537\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1543\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1537\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000001011111010100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1543\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1537\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1541\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1539\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\); + +-- Location: FF_X10_Y30_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1378\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1379\); + +-- Location: LABCELL_X12_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001100000011001000110000001100100010000000100010001000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\); + +-- Location: FF_X12_Y29_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1382\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\); + +-- Location: MLABCELL_X13_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100111000000000000000000000000001001110010011100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\); + +-- Location: MLABCELL_X13_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110011000000111111001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\); + +-- Location: LABCELL_X10_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~42_combout\); + +-- Location: FF_X10_Y30_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1384\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~42_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1385\); + +-- Location: MLABCELL_X13_Y31_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000001111010111110000111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~3_combout\); + +-- Location: MLABCELL_X13_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111000000000010101000101010001010100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~6_combout\); + +-- Location: MLABCELL_X13_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001011100110100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~4_combout\); + +-- Location: LABCELL_X12_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~5_combout\); + +-- Location: MLABCELL_X13_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000010000000000000000000000000001000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\); + +-- Location: MLABCELL_X13_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001011100110100001111000011110000111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~8_combout\); + +-- Location: MLABCELL_X13_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~6_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~5_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000001000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\); + +-- Location: MLABCELL_X13_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101011111111111111110000101000001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\); + +-- Location: FF_X13_Y31_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1380\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\); + +-- Location: LABCELL_X10_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1385\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1379\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1379\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1379\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1379\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1383\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1385\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1381\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\); + +-- Location: FF_X10_Y30_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1560\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1561\); + +-- Location: LABCELL_X12_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110101000001011111010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\); + +-- Location: MLABCELL_X13_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000100000001100000011000010100000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\); + +-- Location: LABCELL_X10_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~40_combout\); + +-- Location: FF_X10_Y30_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1566\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~40_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1567\); + +-- Location: LABCELL_X12_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001100000011001000110000001100100010000000100010001000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\); + +-- Location: FF_X12_Y29_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1564\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\); + +-- Location: LABCELL_X14_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000010000000000000010100000001000100000000010001001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\); + +-- Location: LABCELL_X16_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781_BDD8782\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781_BDD8782\); + +-- Location: LABCELL_X14_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781_BDD8782\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781_BDD8782\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101010101000000000101010100010000000100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~6_RESYN8781_BDD8782\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_combout\); + +-- Location: LABCELL_X14_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011001000111110101100100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~40_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~7_combout\); + +-- Location: LABCELL_X14_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000000000000000000000001000000000001001100010110000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\); + +-- Location: LABCELL_X14_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~1_combout\); + +-- Location: LABCELL_X14_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110001000111111111000100011111010100010001111101010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\); + +-- Location: LABCELL_X14_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111001111110011111100000000001111110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\); + +-- Location: LABCELL_X14_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111000001110101000000000000000001110000011101010111000001110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_RESYN8431_BDD8432\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_RESYN8429_BDD8430\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\); + +-- Location: LABCELL_X14_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~7_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101110111011000000000000000010111011101110110000101100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\); + +-- Location: FF_X13_Y29_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1562\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\); + +-- Location: LABCELL_X10_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1561\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1561\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1567\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1561\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110011001101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1561\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1567\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1565\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1563\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\); + +-- Location: LABCELL_X10_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000100110000101010011011110001100101011101001110110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]~42_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]~38_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]~43_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]~41_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0_combout\); + +-- Location: FF_X7_Y32_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1256\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1074~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\); + +-- Location: LABCELL_X12_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000101011111010000010101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\); + +-- Location: MLABCELL_X13_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001000000010001000100010011000000000000001100110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\); + +-- Location: LABCELL_X6_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000101110000011000010111000011101001111110001110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~41_combout\); + +-- Location: FF_X6_Y32_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1258\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~41_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1259\); + +-- Location: FF_X6_Y32_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1250\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\); + +-- Location: LABCELL_X14_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110111001100110011011100000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\); + +-- Location: LABCELL_X10_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000011110000111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1_combout\); + +-- Location: LABCELL_X12_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010000000000000101000001010101010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~2_combout\); + +-- Location: LABCELL_X12_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443_BDD8444\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443_BDD8444\); + +-- Location: LABCELL_X12_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443_BDD8444\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443_BDD8444\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100111011101111111100001100000011000000111000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~5_RESYN8443_BDD8444\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_combout\); + +-- Location: LABCELL_X12_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111101000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~35_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\); + +-- Location: LABCELL_X14_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\); + +-- Location: LABCELL_X14_Y31_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000001010101010100000101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6_combout\); + +-- Location: LABCELL_X14_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000001100110011000000110011111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\); + +-- Location: LABCELL_X10_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)))) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010001000101010101000100010101010100010001010101010101000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_RESYN8801_BDD8802\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_RESYN8799_BDD8800\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\); + +-- Location: FF_X10_Y31_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1252\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\); + +-- Location: LABCELL_X12_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101110000011101010111000001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\); + +-- Location: FF_X12_Y29_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1254\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\); + +-- Location: LABCELL_X6_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1259\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000000001111111100000011111100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1259\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1251\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1253\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1255\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\); + +-- Location: LABCELL_X12_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010000011111010101000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\); + +-- Location: MLABCELL_X13_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000000010001000100010011000000000000001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\); + +-- Location: LABCELL_X6_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000101110000011000010111000011101001111110001110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~40_combout\); + +-- Location: FF_X6_Y32_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1426\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~40_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1427\); + +-- Location: FF_X6_Y32_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1420\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\); + +-- Location: LABCELL_X14_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111000000010000111100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\); + +-- Location: LABCELL_X7_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445_BDD8446\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111100111111001111111111111100001111001111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445_BDD8446\); + +-- Location: LABCELL_X7_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445_BDD8446\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445_BDD8446\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111100111111001111110001010100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~5_RESYN8445_BDD8446\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_combout\); + +-- Location: LABCELL_X14_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803_BDD8804\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110010101000111111001010100011001100100010001100110010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803_BDD8804\); + +-- Location: LABCELL_X14_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155_BDD9156\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155_BDD9156\); + +-- Location: LABCELL_X14_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155_BDD9156\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155_BDD9156\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100001101000001010000010100000000000000110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~0_RESYN9155_BDD9156\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_combout\); + +-- Location: MLABCELL_X13_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803_BDD8804\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8803_BDD8804\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\); + +-- Location: MLABCELL_X13_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001100110000000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3_combout\); + +-- Location: MLABCELL_X13_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010110010001111101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~44_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\); + +-- Location: LABCELL_X7_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_combout\))) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010100000101010101010000010101010101000001010101010100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8805_BDD8806\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8807_BDD8808\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\); + +-- Location: FF_X7_Y31_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1422\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\); + +-- Location: LABCELL_X12_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001100000011001000110000001100100010000000100010001000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\); + +-- Location: FF_X12_Y29_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1424\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\); + +-- Location: LABCELL_X6_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1427\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000011110000111100011011000110110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1427\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1421\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1423\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1425\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\); + +-- Location: FF_X6_Y32_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1276\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\); + +-- Location: LABCELL_X12_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010001100111010101000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\); + +-- Location: MLABCELL_X13_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000011001000000000000000000001000000110010000100000011001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\); + +-- Location: LABCELL_X6_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010100000101000000110011001100110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~44_combout\); + +-- Location: FF_X6_Y32_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1282\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~44_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1283\); + +-- Location: LABCELL_X7_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789_BDD8790\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789_BDD8790\); + +-- Location: LABCELL_X7_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789_BDD8790\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789_BDD8790\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011111000000000000111100000000001000100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~9_RESYN8789_BDD8790\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_combout\); + +-- Location: LABCELL_X14_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000000110011000000010011001100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\); + +-- Location: MLABCELL_X13_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791_BDD8792\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111011111110111111111111111000000000111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791_BDD8792\); + +-- Location: LABCELL_X7_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000000000000000000000111111110000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~5_combout\); + +-- Location: LABCELL_X7_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791_BDD8792\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111000001100000011100000110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_RESYN8791_BDD8792\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\); + +-- Location: MLABCELL_X13_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110001010100111111000101010000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\); + +-- Location: MLABCELL_X13_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010100010101000111111001010100010101000000000001111110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~8_RESYN8441_BDD8442\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\); + +-- Location: LABCELL_X7_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\))) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011000000110011001100000011001100110000001100110011001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_RESYN8795_BDD8796\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\); + +-- Location: FF_X7_Y30_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1278\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\); + +-- Location: LABCELL_X12_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001100000011001000110000001100100010000000100010001000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\); + +-- Location: FF_X12_Y29_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1280\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\); + +-- Location: LABCELL_X6_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1283\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001100110011001100110000001111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1277\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1283\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1279\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1281\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\); + +-- Location: LABCELL_X6_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110000000000001111010101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~38_combout\); + +-- Location: FF_X6_Y32_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1476\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~38_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1477\); + +-- Location: FF_X7_Y32_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1470\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1471\); + +-- Location: FF_X9_Y31_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1474\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1475\); + +-- Location: FF_X12_Y28_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1472\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\); + +-- Location: LABCELL_X7_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1475\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1475\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1477\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1471\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1471\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1471\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1477\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1471\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1475\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1473\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\); + +-- Location: LABCELL_X6_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011100010101001101101000110010101111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]~42_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]~41_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]~45_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]~39_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1_combout\); + +-- Location: MLABCELL_X13_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\); + +-- Location: LABCELL_X12_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\)))) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001011101000011000000110000101010011111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~32_combout\); + +-- Location: FF_X12_Y15_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_NEW_REG538\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~32_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\); + +-- Location: LABCELL_X12_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100111111110011011100000000110001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM541\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM537\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM539\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\); + +-- Location: LABCELL_X16_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & ( \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & ( +-- \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & ( !\myVirtualToplevel|MEM_DATA_READ[10]~119_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~119_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~35_combout\); + +-- Location: FF_X16_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_NEW_REG534\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~35_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\); + +-- Location: FF_X14_Y14_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_NEW_REG530\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\); + +-- Location: MLABCELL_X4_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~62\); + +-- Location: MLABCELL_X4_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000000000000011111111111111111100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\); + +-- Location: MLABCELL_X9_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~62\); + +-- Location: LABCELL_X12_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42_combout\); + +-- Location: LABCELL_X12_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(10) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010011110111001101111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[10]~42_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~43_combout\); + +-- Location: FF_X12_Y27_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~43_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(10)); + +-- Location: LABCELL_X12_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000101110000011000010111000011101001111110001110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40_combout\); + +-- Location: LABCELL_X12_Y28_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(10) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[10]~40_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~41_combout\); + +-- Location: FF_X12_Y28_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~41_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(10)); + +-- Location: LABCELL_X5_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46_combout\); + +-- Location: LABCELL_X5_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(10) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101101110111010111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[10]~46_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~47_combout\); + +-- Location: FF_X5_Y30_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~47_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(10)); + +-- Location: LABCELL_X5_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010100000101000000000000111111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\); + +-- Location: LABCELL_X6_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101110101111111100010101000000001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[10]~43_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~44_combout\); + +-- Location: FF_X6_Y31_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~44_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10)); + +-- Location: LABCELL_X12_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(10) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(10) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(10) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1_combout\); + +-- Location: LABCELL_X12_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43_combout\); + +-- Location: LABCELL_X12_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(10) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[10]~43_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~44_combout\); + +-- Location: FF_X12_Y27_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~44_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(10)); + +-- Location: LABCELL_X12_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39_combout\); + +-- Location: LABCELL_X12_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(10) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100010001110011111101110100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[10]~39_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~40_combout\); + +-- Location: FF_X12_Y27_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~40_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(10)); + +-- Location: LABCELL_X12_Y27_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42_combout\); + +-- Location: LABCELL_X12_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(10) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010011110111001101111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[10]~42_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~43_combout\); + +-- Location: FF_X12_Y27_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~43_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(10)); + +-- Location: LABCELL_X12_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44_combout\); + +-- Location: LABCELL_X12_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(10) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[10]~44_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~45_combout\); + +-- Location: FF_X12_Y27_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~45_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(10)); + +-- Location: LABCELL_X12_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(10) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(10) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(10) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(10) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0_combout\); + +-- Location: LABCELL_X12_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\); + +-- Location: LABCELL_X14_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|MEM_DATA_READ[10]~119_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- (\myVirtualToplevel|MEM_DATA_READ[10]~119_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|MEM_DATA_READ[10]~119_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101000011110000111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~119_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~34_combout\); + +-- Location: FF_X14_Y14_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_NEW_REG532\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\); + +-- Location: LABCELL_X14_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000110011111101111100100000001100001110111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM535\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM531\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM533\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\); + +-- Location: MLABCELL_X13_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]_NEW3047\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]_OTERM3048\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]_OTERM3048\); + +-- Location: FF_X13_Y23_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]_OTERM3048\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(11)); + +-- Location: LABCELL_X7_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]_NEW3175\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]_OTERM3176\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(11) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]_OTERM3176\); + +-- Location: FF_X7_Y25_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]_OTERM3176\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(11)); + +-- Location: LABCELL_X7_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]_NEW3111\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]_OTERM3112\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(11) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]_OTERM3112\); + +-- Location: FF_X7_Y25_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]_OTERM3112\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(11)); + +-- Location: LABCELL_X7_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]_NEW2983\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]_OTERM2984\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]_OTERM2984\); + +-- Location: FF_X7_Y25_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]_OTERM2984\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(11)); + +-- Location: LABCELL_X7_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(11) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(11) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(11) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(11) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0_combout\); + +-- Location: LABCELL_X7_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]_NEW2919\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]_OTERM2920\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000011011111000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]_OTERM2920\); + +-- Location: FF_X7_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]_OTERM2920\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11)); + +-- Location: LABCELL_X7_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]_NEW2791\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]_OTERM2792\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(11) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]_OTERM2792\); + +-- Location: FF_X7_Y20_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]_OTERM2792\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(11)); + +-- Location: LABCELL_X7_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]_NEW2727\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]_OTERM2728\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]_OTERM2728\); + +-- Location: FF_X7_Y20_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]_OTERM2728\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11)); + +-- Location: MLABCELL_X9_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]_NEW2855\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]_OTERM2856\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]_OTERM2856\); + +-- Location: FF_X9_Y20_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]_OTERM2856\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11)); + +-- Location: LABCELL_X6_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111000001010000010100100010011101111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1_combout\); + +-- Location: LABCELL_X6_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2_combout\); + +-- Location: MLABCELL_X9_Y14_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]~feeder_combout\); + +-- Location: FF_X9_Y14_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11)); + +-- Location: MLABCELL_X18_Y9_N24 +\myVirtualToplevel|SD_ADDR[0][11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(11), + combout => \myVirtualToplevel|SD_ADDR[0][11]~feeder_combout\); + +-- Location: FF_X18_Y9_N25 +\myVirtualToplevel|SD_ADDR[0][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][11]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][11]~q\); + +-- Location: LABCELL_X19_Y9_N9 +\myVirtualToplevel|Mux72~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux72~0_combout\ = ( \myVirtualToplevel|SD_ADDR[0][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) # ( !\myVirtualToplevel|SD_ADDR[0][11]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010110101010000001011010101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_SD_ADDR[0][11]~q\, + combout => \myVirtualToplevel|Mux72~0_combout\); + +-- Location: FF_X19_Y9_N11 +\myVirtualToplevel|IO_DATA_READ_SD[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux72~0_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(11)); + +-- Location: MLABCELL_X9_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\); + +-- Location: LABCELL_X10_Y14_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\ & ( (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\)) # (\myVirtualToplevel|MEM_BUSY~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\ & ( (!\myVirtualToplevel|MEM_BUSY~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) +-- # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\)) # (\myVirtualToplevel|MEM_BUSY~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010111111111111100100000000000000111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~0_combout\); + +-- Location: FF_X10_Y14_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\); + +-- Location: MLABCELL_X9_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\ & ( (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) # +-- (\myVirtualToplevel|MEM_BUSY~1_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & (!\myVirtualToplevel|MEM_BUSY~1_combout\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) # +-- (\myVirtualToplevel|MEM_BUSY~1_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001111111111111101000000000000000111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~0_combout\); + +-- Location: FF_X9_Y15_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\); + +-- Location: FF_X19_Y12_N1 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux110~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\); + +-- Location: IOIBUF_X25_Y0_N52 +\SDRAM_DQ[3]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(3), + o => \SDRAM_DQ[3]~input_o\); + +-- Location: DDIOINCELL_X25_Y0_N65 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_NEW_REG36\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[3]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM37\); + +-- Location: FF_X18_Y13_N35 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_NEW_REG34\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM35\); + +-- Location: MLABCELL_X18_Y13_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM35\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\) # +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM37\)) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM35\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM37\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011000000000000001111111100111111111111110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]_OTERM37\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]_OTERM35\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\); + +-- Location: MLABCELL_X9_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111111001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~49_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\); + +-- Location: MLABCELL_X9_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~50\); + +-- Location: LABCELL_X5_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0110011001100110011001100110011000000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33_combout\); + +-- Location: LABCELL_X5_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010011110111001101111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[4]~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~34_combout\); + +-- Location: FF_X5_Y28_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(4)); + +-- Location: MLABCELL_X4_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101101001011010010110100101101000110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36_combout\); + +-- Location: LABCELL_X5_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010101101110101011111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[4]~36_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~37_combout\); + +-- Location: FF_X5_Y29_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~37_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(4)); + +-- Location: MLABCELL_X9_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) +-- $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001111001100001100111100110001010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\); + +-- Location: MLABCELL_X9_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000111110111111101000000001000001011111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[4]~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~38_combout\); + +-- Location: FF_X9_Y27_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~38_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4)); + +-- Location: MLABCELL_X4_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111110000001100110011001100001111111100000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38_combout\); + +-- Location: MLABCELL_X4_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[4]~38_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~39_combout\); + +-- Location: FF_X4_Y29_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~39_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(4)); + +-- Location: MLABCELL_X4_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(4) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(4) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(4) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\); + +-- Location: MLABCELL_X4_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010110101010001100110011001101010101101010100000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\); + +-- Location: MLABCELL_X4_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000111111110100111100000000011100001111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[4]~40_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~41_combout\); + +-- Location: FF_X4_Y29_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~41_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4)); + +-- Location: MLABCELL_X4_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101101001011010001100110011001101011010010110100000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37_combout\); + +-- Location: MLABCELL_X4_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(4) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000111111101001111011100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[4]~37_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~38_combout\); + +-- Location: FF_X4_Y29_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~38_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(4)); + +-- Location: MLABCELL_X9_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111111111110000000001000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36_combout\); + +-- Location: MLABCELL_X9_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010011111111110101001100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[4]~36_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~37_combout\); + +-- Location: FF_X9_Y30_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~37_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(4)); + +-- Location: LABCELL_X6_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010110101010010101011010101000110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34_combout\); + +-- Location: LABCELL_X6_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001001100011100110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[4]~34_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~35_combout\); + +-- Location: FF_X6_Y27_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~35_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(4)); + +-- Location: MLABCELL_X4_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(4) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(4) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(4) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\); + +-- Location: MLABCELL_X4_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\); + +-- Location: LABCELL_X14_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~2_combout\, + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~86\); + +-- Location: LABCELL_X14_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~82\); + +-- Location: LABCELL_X14_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~50\); + +-- Location: LABCELL_X14_Y16_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add6~49_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add6~49_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000001111000000100000111111010010110111111101001011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~49_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\); + +-- Location: LABCELL_X16_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector212~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000101011111111111100010000101100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector212~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~0_combout\); + +-- Location: FF_X16_Y14_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(4)); + +-- Location: MLABCELL_X4_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110011111111110011001111111111001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~53_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\); + +-- Location: MLABCELL_X9_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(5) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(5) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~54\); + +-- Location: LABCELL_X5_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35_combout\); + +-- Location: LABCELL_X5_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010011110111001101111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[5]~35_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~36_combout\); + +-- Location: FF_X5_Y30_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~36_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(5)); + +-- Location: LABCELL_X5_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000101110000011000010111000011101001111110001110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38_combout\); + +-- Location: LABCELL_X5_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101101011101011111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[5]~38_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~39_combout\); + +-- Location: FF_X5_Y29_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~39_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(5)); + +-- Location: LABCELL_X10_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100100010011101110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39_combout\); + +-- Location: LABCELL_X10_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001001000111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[5]~39_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~40_combout\); + +-- Location: FF_X10_Y28_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~40_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(5)); + +-- Location: LABCELL_X5_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40_combout\); + +-- Location: LABCELL_X5_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[5]~40_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~41_combout\); + +-- Location: FF_X5_Y31_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~41_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(5)); + +-- Location: LABCELL_X5_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(5) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(5) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(5) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(5) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0_combout\); + +-- Location: LABCELL_X6_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38_combout\); + +-- Location: LABCELL_X6_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010101101110101011111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[5]~38_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~39_combout\); + +-- Location: FF_X6_Y30_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~39_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(5)); + +-- Location: LABCELL_X5_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42_combout\); + +-- Location: LABCELL_X5_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(5) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111111111110100011100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[5]~42_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~43_combout\); + +-- Location: FF_X5_Y30_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~43_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(5)); + +-- Location: LABCELL_X6_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36_combout\); + +-- Location: LABCELL_X6_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[5]~36_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~37_combout\); + +-- Location: FF_X6_Y30_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~37_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(5)); + +-- Location: LABCELL_X5_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\); + +-- Location: LABCELL_X5_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101110101111111100010101000000001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[5]~39_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~40_combout\); + +-- Location: FF_X5_Y31_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~40_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5)); + +-- Location: LABCELL_X5_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(5) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(5) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(5) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1_combout\); + +-- Location: LABCELL_X5_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\); + +-- Location: LABCELL_X14_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~54\); + +-- Location: LABCELL_X14_Y16_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~53_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101101000100000010110100010000001011111111110000101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~53_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\); + +-- Location: LABCELL_X16_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector211~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010111101011111111100000010101000100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector211~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~0_combout\); + +-- Location: FF_X16_Y14_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)); + +-- Location: FF_X14_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]_OTERM3329\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(12)); + +-- Location: MLABCELL_X4_Y26_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~66\); + +-- Location: MLABCELL_X4_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~34\); + +-- Location: LABCELL_X10_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(12)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(12) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000011111111111100001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~33_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\); + +-- Location: LABCELL_X7_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~34\); + +-- Location: MLABCELL_X9_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~66\); + +-- Location: MLABCELL_X9_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~34\); + +-- Location: MLABCELL_X9_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001000100010001000001111000011110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28_combout\); + +-- Location: MLABCELL_X9_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000011110111011100111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[12]~28_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~29_combout\); + +-- Location: FF_X9_Y31_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~29_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12)); + +-- Location: MLABCELL_X9_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111000000110011001100110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\); + +-- Location: MLABCELL_X9_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100111111111111010000000000000001111111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[12]~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~31_combout\); + +-- Location: FF_X9_Y31_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~31_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12)); + +-- Location: MLABCELL_X9_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25_combout\); + +-- Location: MLABCELL_X9_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011110011011110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[12]~25_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~26_combout\); + +-- Location: FF_X9_Y31_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~26_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12)); + +-- Location: LABCELL_X10_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\); + +-- Location: LABCELL_X10_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000111111111101110000000000000100111111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[12]~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~30_combout\); + +-- Location: FF_X10_Y28_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~30_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12)); + +-- Location: LABCELL_X12_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111000000000011001101010101000011111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\); + +-- Location: LABCELL_X6_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\); + +-- Location: LABCELL_X6_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000000111100101111111100000111000000001111011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[12]~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~33_combout\); + +-- Location: FF_X6_Y30_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~33_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12)); + +-- Location: LABCELL_X6_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001001110000010100100111000011011010111110001101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\); + +-- Location: LABCELL_X6_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101110101111111100010101000000001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[12]~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~29_combout\); + +-- Location: FF_X6_Y31_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~29_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12)); + +-- Location: LABCELL_X6_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100000011000001010101010101010011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29_combout\); + +-- Location: LABCELL_X7_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(12) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100010001101011111011101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[12]~29_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~30_combout\); + +-- Location: FF_X7_Y30_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~30_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(12)); + +-- Location: LABCELL_X6_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26_combout\); + +-- Location: LABCELL_X6_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(12) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001001000111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[12]~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~27_combout\); + +-- Location: FF_X6_Y30_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~27_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(12)); + +-- Location: LABCELL_X6_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(12) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(12) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\); + +-- Location: LABCELL_X10_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\); + +-- Location: LABCELL_X14_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~70\); + +-- Location: LABCELL_X14_Y16_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~74\); + +-- Location: LABCELL_X14_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~78\); + +-- Location: LABCELL_X14_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~58\); + +-- Location: LABCELL_X14_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~62\); + +-- Location: LABCELL_X14_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~66\); + +-- Location: LABCELL_X14_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~34\); + +-- Location: LABCELL_X14_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add6~33_sumout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add6~33_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111101000110010101110100011001010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~33_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\); + +-- Location: LABCELL_X14_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100111111110011111100001100010001000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector204~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0_combout\); + +-- Location: LABCELL_X14_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]_NEW3328\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]_OTERM3329\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(12))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # ((\myVirtualToplevel|MEM_DATA_READ[12]~147_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- (\myVirtualToplevel|MEM_DATA_READ[12]~147_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~1_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~147_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector204~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]_OTERM3329\); + +-- Location: FF_X14_Y15_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]_OTERM3329\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\); + +-- Location: MLABCELL_X4_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~38\); + +-- Location: MLABCELL_X4_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~42\); + +-- Location: MLABCELL_X9_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000011111010111110101111101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[14]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~41_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\); + +-- Location: LABCELL_X7_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(14), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~42\); + +-- Location: MLABCELL_X9_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~38\); + +-- Location: MLABCELL_X9_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(14), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~42\); + +-- Location: LABCELL_X6_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32_combout\); + +-- Location: LABCELL_X6_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(14) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000011110111011100111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~32_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~33_combout\); + +-- Location: FF_X6_Y27_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~33_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(14)); + +-- Location: LABCELL_X7_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34_combout\); + +-- Location: LABCELL_X7_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(14) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[14]~34_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~35_combout\); + +-- Location: FF_X7_Y27_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~35_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(14)); + +-- Location: LABCELL_X7_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33_combout\); + +-- Location: LABCELL_X7_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(14) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000101011010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[14]~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~34_combout\); + +-- Location: FF_X7_Y27_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(14)); + +-- Location: LABCELL_X6_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29_combout\); + +-- Location: LABCELL_X6_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(14) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000011110111011100111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[14]~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~30_combout\); + +-- Location: FF_X6_Y27_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~30_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(14)); + +-- Location: LABCELL_X7_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(14) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(14) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(14) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(14) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(14), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0_combout\); + +-- Location: LABCELL_X6_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30_combout\); + +-- Location: LABCELL_X6_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(14) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[14]~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~31_combout\); + +-- Location: FF_X6_Y27_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~31_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(14)); + +-- Location: LABCELL_X7_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32_combout\); + +-- Location: LABCELL_X7_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(14) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000011111101011111001100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[14]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~33_combout\); + +-- Location: FF_X7_Y27_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~33_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(14)); + +-- Location: LABCELL_X7_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36_combout\); + +-- Location: LABCELL_X7_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(14) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101101010111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[14]~36_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~37_combout\); + +-- Location: FF_X7_Y27_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~37_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(14)); + +-- Location: MLABCELL_X9_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000000000110011001100110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33_combout\); + +-- Location: MLABCELL_X9_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(14) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101101011101011111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[14]~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~34_combout\); + +-- Location: FF_X9_Y28_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(14)); + +-- Location: LABCELL_X7_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(14) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(14) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(14) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(14) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(14), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1_combout\); + +-- Location: LABCELL_X7_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\); + +-- Location: MLABCELL_X4_Y25_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~37_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111110101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~37_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\); + +-- Location: FF_X20_Y18_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(13)); + +-- Location: LABCELL_X20_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]~feeder_combout\); + +-- Location: FF_X20_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(13)); + +-- Location: LABCELL_X20_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(13)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(13) & \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\); + +-- Location: LABCELL_X12_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]_NEW2979\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]_OTERM2980\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]_OTERM2980\); + +-- Location: FF_X12_Y22_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]_OTERM2980\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13)); + +-- Location: MLABCELL_X13_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]_NEW3171\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]_OTERM3172\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]_OTERM3172\); + +-- Location: FF_X13_Y22_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]_OTERM3172\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(13)); + +-- Location: LABCELL_X12_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]_NEW3043\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]_OTERM3044\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(13) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]_OTERM3044\); + +-- Location: FF_X12_Y22_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]_OTERM3044\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(13)); + +-- Location: LABCELL_X12_Y22_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]_NEW3107\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]_OTERM3108\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]_OTERM3108\); + +-- Location: FF_X12_Y22_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]_OTERM3108\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13)); + +-- Location: LABCELL_X12_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(13)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(13)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0_combout\); + +-- Location: LABCELL_X12_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]_NEW2851\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]_OTERM2852\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(13) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]_OTERM2852\); + +-- Location: FF_X12_Y22_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]_OTERM2852\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(13)); + +-- Location: LABCELL_X12_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]_NEW2723\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]_OTERM2724\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]_OTERM2724\); + +-- Location: FF_X12_Y22_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]_OTERM2724\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13)); + +-- Location: LABCELL_X12_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]_NEW2915\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]_OTERM2916\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000001111111001011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]_OTERM2916\); + +-- Location: FF_X12_Y22_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]_OTERM2916\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13)); + +-- Location: LABCELL_X12_Y22_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]_NEW2787\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]_OTERM2788\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]_OTERM2788\); + +-- Location: FF_X12_Y22_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]_OTERM2788\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13)); + +-- Location: LABCELL_X12_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(13) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1_combout\); + +-- Location: MLABCELL_X9_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux92~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux92~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux92~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~2_combout\); + +-- Location: FF_X9_Y14_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~2_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13)); + +-- Location: MLABCELL_X18_Y9_N18 +\myVirtualToplevel|SD_ADDR[0][13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(13), + combout => \myVirtualToplevel|SD_ADDR[0][13]~feeder_combout\); + +-- Location: FF_X18_Y9_N20 +\myVirtualToplevel|SD_ADDR[0][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][13]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][13]~q\); + +-- Location: MLABCELL_X18_Y9_N12 +\myVirtualToplevel|Mux70~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux70~0_combout\ = ( \myVirtualToplevel|SD_RD\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SD_ADDR[0][13]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) # ( !\myVirtualToplevel|SD_RD\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SD_ADDR[0][13]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000000000000011000000000000001100001100110000110000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_SD_RD\(0), + combout => \myVirtualToplevel|Mux70~0_combout\); + +-- Location: FF_X18_Y9_N13 +\myVirtualToplevel|IO_DATA_READ_SD[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux70~0_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(13)); + +-- Location: LABCELL_X19_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~feeder_combout\); + +-- Location: FF_X19_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~DUPLICATE_q\); + +-- Location: LABCELL_X21_Y11_N57 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55~feeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]~17_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55~feeder_combout\); + +-- Location: FF_X21_Y11_N58 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_NEW_REG54\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55\); + +-- Location: LABCELL_X21_Y11_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55\ ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000011001111111111110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM57\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM55\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\); + +-- Location: FF_X16_Y14_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\); + +-- Location: FF_X16_Y14_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\); + +-- Location: FF_X16_Y14_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11)); + +-- Location: M10K_X22_Y18_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 5, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 5, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\); + +-- Location: FF_X18_Y14_N7 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y14_N54 +\myVirtualToplevel|INT_ENABLE[16]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INT_ENABLE[16]~0_combout\ = (\myVirtualToplevel|INTR0_CS~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010100000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + combout => \myVirtualToplevel|INT_ENABLE[16]~0_combout\); + +-- Location: FF_X17_Y14_N10 +\myVirtualToplevel|INT_ENABLE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(5)); + +-- Location: LABCELL_X16_Y14_N51 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\ = ( \myVirtualToplevel|INTR0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\, + dataf => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + combout => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\); + +-- Location: FF_X20_Y14_N56 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INT_ENABLE\(5), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(5)); + +-- Location: MLABCELL_X9_Y12_N30 +\myVirtualToplevel|Add4~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add4~33_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|Add4~34\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(0), + cin => GND, + sumout => \myVirtualToplevel|Add4~33_sumout\, + cout => \myVirtualToplevel|Add4~34\); + +-- Location: LABCELL_X10_Y15_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]~feeder_combout\); + +-- Location: FF_X10_Y15_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2)); + +-- Location: LABCELL_X10_Y11_N0 +\myVirtualToplevel|Add3~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add3~17_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|Add3~18\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(0), + cin => GND, + sumout => \myVirtualToplevel|Add3~17_sumout\, + cout => \myVirtualToplevel|Add3~18\); + +-- Location: LABCELL_X10_Y11_N45 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ = ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101000000000101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + combout => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\); + +-- Location: MLABCELL_X13_Y10_N36 +\myVirtualToplevel|UART1|Mux0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Mux0~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|UART1|Mux0~0_combout\); + +-- Location: LABCELL_X10_Y11_N24 +\myVirtualToplevel|RTC_TICK_HALT~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_TICK_HALT~0_combout\ = ( \myVirtualToplevel|RTC_TICK_HALT~q\ & ( \myVirtualToplevel|UART1|Mux0~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\) # ((!\myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|RTC_TICK_HALT~q\ & ( \myVirtualToplevel|UART1|Mux0~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|RTC_TICK_HALT~q\ & ( !\myVirtualToplevel|UART1|Mux0~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[5]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\, + datae => \myVirtualToplevel|ALT_INV_RTC_TICK_HALT~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\, + combout => \myVirtualToplevel|RTC_TICK_HALT~0_combout\); + +-- Location: FF_X10_Y11_N26 +\myVirtualToplevel|RTC_TICK_HALT\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_TICK_HALT~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_TICK_HALT~q\); + +-- Location: LABCELL_X10_Y11_N51 +\myVirtualToplevel|RTC_MICROSEC_TICK[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\ = ( \myVirtualToplevel|RTC_TICK_HALT~q\ ) # ( !\myVirtualToplevel|RTC_TICK_HALT~q\ & ( !\myVirtualToplevel|Equal13~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal13~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_TICK_HALT~q\, + combout => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\); + +-- Location: LABCELL_X10_Y11_N54 +\myVirtualToplevel|RTC_MICROSEC_TICK[1]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|Equal13~1_combout\) # ((!\myVirtualToplevel|RTC_TICK_HALT~q\) # (\myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\)) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|Equal13~1_combout\) # (!\myVirtualToplevel|RTC_TICK_HALT~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010111110101111101011111010111111111111101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal13~1_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_TICK_HALT~q\, + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\); + +-- Location: FF_X10_Y11_N38 +\myVirtualToplevel|RTC_MICROSEC_TICK[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Add3~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_TICK\(0)); + +-- Location: LABCELL_X10_Y11_N3 +\myVirtualToplevel|Add3~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add3~1_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add3~18\ )) +-- \myVirtualToplevel|Add3~2\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add3~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(1), + cin => \myVirtualToplevel|Add3~18\, + sumout => \myVirtualToplevel|Add3~1_sumout\, + cout => \myVirtualToplevel|Add3~2\); + +-- Location: FF_X10_Y11_N5 +\myVirtualToplevel|RTC_MICROSEC_TICK[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add3~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_TICK\(1)); + +-- Location: LABCELL_X10_Y11_N6 +\myVirtualToplevel|Add3~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add3~21_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add3~2\ )) +-- \myVirtualToplevel|Add3~22\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add3~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(2), + cin => \myVirtualToplevel|Add3~2\, + sumout => \myVirtualToplevel|Add3~21_sumout\, + cout => \myVirtualToplevel|Add3~22\); + +-- Location: FF_X10_Y11_N8 +\myVirtualToplevel|RTC_MICROSEC_TICK[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add3~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_TICK\(2)); + +-- Location: LABCELL_X10_Y11_N9 +\myVirtualToplevel|Add3~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add3~5_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add3~22\ )) +-- \myVirtualToplevel|Add3~6\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add3~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(3), + cin => \myVirtualToplevel|Add3~22\, + sumout => \myVirtualToplevel|Add3~5_sumout\, + cout => \myVirtualToplevel|Add3~6\); + +-- Location: FF_X10_Y11_N11 +\myVirtualToplevel|RTC_MICROSEC_TICK[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add3~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_TICK\(3)); + +-- Location: LABCELL_X10_Y11_N12 +\myVirtualToplevel|Add3~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add3~9_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add3~6\ )) +-- \myVirtualToplevel|Add3~10\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add3~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(4), + cin => \myVirtualToplevel|Add3~6\, + sumout => \myVirtualToplevel|Add3~9_sumout\, + cout => \myVirtualToplevel|Add3~10\); + +-- Location: FF_X10_Y11_N14 +\myVirtualToplevel|RTC_MICROSEC_TICK[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add3~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_TICK\(4)); + +-- Location: LABCELL_X10_Y11_N15 +\myVirtualToplevel|Add3~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add3~25_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add3~10\ )) +-- \myVirtualToplevel|Add3~26\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add3~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(5), + cin => \myVirtualToplevel|Add3~10\, + sumout => \myVirtualToplevel|Add3~25_sumout\, + cout => \myVirtualToplevel|Add3~26\); + +-- Location: FF_X10_Y11_N17 +\myVirtualToplevel|RTC_MICROSEC_TICK[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add3~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_TICK\(5)); + +-- Location: LABCELL_X10_Y11_N18 +\myVirtualToplevel|Add3~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add3~29_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add3~26\ )) +-- \myVirtualToplevel|Add3~30\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add3~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(6), + cin => \myVirtualToplevel|Add3~26\, + sumout => \myVirtualToplevel|Add3~29_sumout\, + cout => \myVirtualToplevel|Add3~30\); + +-- Location: FF_X10_Y11_N20 +\myVirtualToplevel|RTC_MICROSEC_TICK[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add3~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_TICK\(6)); + +-- Location: LABCELL_X10_Y11_N21 +\myVirtualToplevel|Add3~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add3~13_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add3~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(7), + cin => \myVirtualToplevel|Add3~30\, + sumout => \myVirtualToplevel|Add3~13_sumout\); + +-- Location: FF_X10_Y11_N23 +\myVirtualToplevel|RTC_MICROSEC_TICK[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add3~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_TICK\(7)); + +-- Location: LABCELL_X10_Y11_N48 +\myVirtualToplevel|Equal13~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal13~0_combout\ = ( \myVirtualToplevel|RTC_MICROSEC_TICK\(5) & ( (!\myVirtualToplevel|RTC_MICROSEC_TICK\(2) & (\myVirtualToplevel|RTC_MICROSEC_TICK\(6) & \myVirtualToplevel|RTC_MICROSEC_TICK\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011000000000000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(2), + datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(6), + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(0), + dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(5), + combout => \myVirtualToplevel|Equal13~0_combout\); + +-- Location: LABCELL_X10_Y11_N33 +\myVirtualToplevel|Equal13~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal13~1_combout\ = ( \myVirtualToplevel|RTC_MICROSEC_TICK\(1) & ( \myVirtualToplevel|RTC_MICROSEC_TICK\(3) ) ) # ( !\myVirtualToplevel|RTC_MICROSEC_TICK\(1) & ( \myVirtualToplevel|RTC_MICROSEC_TICK\(3) ) ) # ( +-- \myVirtualToplevel|RTC_MICROSEC_TICK\(1) & ( !\myVirtualToplevel|RTC_MICROSEC_TICK\(3) & ( ((!\myVirtualToplevel|Equal13~0_combout\) # (\myVirtualToplevel|RTC_MICROSEC_TICK\(4))) # (\myVirtualToplevel|RTC_MICROSEC_TICK\(7)) ) ) ) # ( +-- !\myVirtualToplevel|RTC_MICROSEC_TICK\(1) & ( !\myVirtualToplevel|RTC_MICROSEC_TICK\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111110101111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(7), + datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(4), + datad => \myVirtualToplevel|ALT_INV_Equal13~0_combout\, + datae => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(1), + dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(3), + combout => \myVirtualToplevel|Equal13~1_combout\); + +-- Location: LABCELL_X16_Y11_N48 +\myVirtualToplevel|RTC_MILLISEC_COUNTER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110000000000000011000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + combout => \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\); + +-- Location: MLABCELL_X9_Y12_N27 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\ = ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( (!\myVirtualToplevel|Equal13~1_combout\) # ((\myVirtualToplevel|UART1|Equal7~0_combout\ & \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\)) ) ) # ( +-- !\myVirtualToplevel|TIMER0_CS~2_combout\ & ( !\myVirtualToplevel|Equal13~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011001100110011111100110011001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_Equal13~1_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + combout => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\); + +-- Location: FF_X9_Y12_N38 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add4~29_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\, + sload => \myVirtualToplevel|Equal13~1_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\); + +-- Location: MLABCELL_X9_Y12_N21 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~1_combout\ = ( !\myVirtualToplevel|RTC_MICROSEC_COUNTER\(3) & ( (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(1) & (!\myVirtualToplevel|RTC_MICROSEC_COUNTER\(4) & +-- \myVirtualToplevel|RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(1), + datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(4), + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(3), + combout => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~1_combout\); + +-- Location: MLABCELL_X9_Y12_N45 +\myVirtualToplevel|Add4~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add4~5_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(5) ) + ( GND ) + ( \myVirtualToplevel|Add4~2\ )) +-- \myVirtualToplevel|Add4~6\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(5) ) + ( GND ) + ( \myVirtualToplevel|Add4~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(5), + cin => \myVirtualToplevel|Add4~2\, + sumout => \myVirtualToplevel|Add4~5_sumout\, + cout => \myVirtualToplevel|Add4~6\); + +-- Location: MLABCELL_X9_Y12_N48 +\myVirtualToplevel|Add4~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add4~13_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(6) ) + ( GND ) + ( \myVirtualToplevel|Add4~6\ )) +-- \myVirtualToplevel|Add4~14\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(6) ) + ( GND ) + ( \myVirtualToplevel|Add4~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(6), + cin => \myVirtualToplevel|Add4~6\, + sumout => \myVirtualToplevel|Add4~13_sumout\, + cout => \myVirtualToplevel|Add4~14\); + +-- Location: IOIBUF_X19_Y0_N35 +\SDRAM_DQ[6]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(6), + o => \SDRAM_DQ[6]~input_o\); + +-- Location: DDIOINCELL_X19_Y0_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_NEW_REG46\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[6]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM47\); + +-- Location: FF_X20_Y14_N25 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_NEW_REG44\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM45\); + +-- Location: LABCELL_X20_Y14_N15 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM45\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM47\)) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM45\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM47\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010111111010111111111111101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM47\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM45\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\); + +-- Location: M10K_X11_Y17_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 6, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 6, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\); + +-- Location: FF_X13_Y12_N58 +\myVirtualToplevel|INT_ENABLE[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(6)); + +-- Location: FF_X20_Y14_N2 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INT_ENABLE\(6), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(6)); + +-- Location: LABCELL_X16_Y14_N30 +\myVirtualToplevel|Equal4~0_RESYN12606\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal4~0_RESYN12606_BDD12607\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|Equal4~0_RESYN12606_BDD12607\); + +-- Location: LABCELL_X17_Y13_N24 +\myVirtualToplevel|Equal4~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal4~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & ( \myVirtualToplevel|Equal4~0_RESYN12606_BDD12607\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_Equal4~0_RESYN12606_BDD12607\, + combout => \myVirtualToplevel|Equal4~0_combout\); + +-- Location: LABCELL_X16_Y8_N24 +\myVirtualToplevel|UART1_CS\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1_CS~combout\ = ( \myVirtualToplevel|IO_SELECT~combout\ & ( \myVirtualToplevel|Equal4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + combout => \myVirtualToplevel|UART1_CS~combout\); + +-- Location: LABCELL_X14_Y7_N6 +\myVirtualToplevel|UART1|RX_ENABLE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_ENABLE~0_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + combout => \myVirtualToplevel|UART1|RX_ENABLE~0_combout\); + +-- Location: LABCELL_X14_Y9_N30 +\myVirtualToplevel|UART1|TX_ENABLE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_ENABLE~0_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010000000100000001000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|TX_ENABLE~0_combout\); + +-- Location: FF_X14_Y7_N8 +\myVirtualToplevel|UART1|RX_ENABLE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_ENABLE~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_ENABLE~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_ENABLE~q\); + +-- Location: LABCELL_X16_Y8_N3 +\myVirtualToplevel|UART1|RX_RESET~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_RESET~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|UART1_CS~combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|UART1_CS~combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|UART1_CS~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111111111111100011111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|RX_RESET~0_combout\); + +-- Location: FF_X16_Y8_N5 +\myVirtualToplevel|UART1|RX_RESET\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_RESET~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_RESET~q\); + +-- Location: LABCELL_X14_Y5_N3 +\myVirtualToplevel|UART1|RX_DATA[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ = ( !\myVirtualToplevel|UART1|RX_ENABLE~q\ & ( \myVirtualToplevel|UART1|RX_RESET~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_RESET~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + combout => \myVirtualToplevel|UART1|RX_DATA[0]~1_combout\); + +-- Location: FF_X16_Y6_N23 +\myVirtualToplevel|UART1|RXD_SYNC2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \UART_RX_1~input_o\, + sload => VCC, + ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RXD_SYNC2~q\); + +-- Location: FF_X16_Y6_N38 +\myVirtualToplevel|UART1|RXD_SYNC\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RXD_SYNC2~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RXD_SYNC~q\); + +-- Location: LABCELL_X14_Y6_N18 +\myVirtualToplevel|UART1|Selector4~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Selector4~0_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ & ( \myVirtualToplevel|UART1|RXD_SYNC~q\ ) ) # ( !\myVirtualToplevel|UART1|RX_STATE.bits~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\, + combout => \myVirtualToplevel|UART1|Selector4~0_combout\); + +-- Location: FF_X16_Y6_N10 +\myVirtualToplevel|UART1|RX_STATE.start~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_STATE.start~0_combout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_STATE.start~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y6_N21 +\myVirtualToplevel|UART1|RX_BUFFER[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\ = ( \myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & ( (\myVirtualToplevel|UART1|RX_CLOCK~q\ & (((!\myVirtualToplevel|UART1|RXD_SYNC~q\ & \myVirtualToplevel|UART1|RX_STATE.start~DUPLICATE_q\)) # +-- (\myVirtualToplevel|UART1|RX_STATE.bits~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010111010000000001011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\, + datab => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~DUPLICATE_q\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\, + combout => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\); + +-- Location: FF_X14_Y6_N19 +\myVirtualToplevel|UART1|RX_BUFFER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Selector4~0_combout\, + ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_BUFFER\(8)); + +-- Location: LABCELL_X14_Y6_N9 +\myVirtualToplevel|UART1|Selector5~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Selector5~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(8) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(8), + combout => \myVirtualToplevel|UART1|Selector5~0_combout\); + +-- Location: FF_X14_Y6_N11 +\myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Selector5~0_combout\, + ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y6_N6 +\myVirtualToplevel|UART1|Selector6~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Selector6~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\ & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[7]~DUPLICATE_q\, + combout => \myVirtualToplevel|UART1|Selector6~0_combout\); + +-- Location: FF_X14_Y6_N7 +\myVirtualToplevel|UART1|RX_BUFFER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Selector6~0_combout\, + ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_BUFFER\(6)); + +-- Location: LABCELL_X14_Y6_N3 +\myVirtualToplevel|UART1|Selector7~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Selector7~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(6) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(6), + combout => \myVirtualToplevel|UART1|Selector7~0_combout\); + +-- Location: FF_X14_Y6_N5 +\myVirtualToplevel|UART1|RX_BUFFER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Selector7~0_combout\, + ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_BUFFER\(5)); + +-- Location: LABCELL_X14_Y6_N0 +\myVirtualToplevel|UART1|Selector8~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Selector8~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(5) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(5), + combout => \myVirtualToplevel|UART1|Selector8~0_combout\); + +-- Location: FF_X14_Y6_N1 +\myVirtualToplevel|UART1|RX_BUFFER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Selector8~0_combout\, + ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_BUFFER\(4)); + +-- Location: LABCELL_X14_Y6_N39 +\myVirtualToplevel|UART1|Selector9~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Selector9~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(4) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(4), + combout => \myVirtualToplevel|UART1|Selector9~0_combout\); + +-- Location: FF_X14_Y6_N40 +\myVirtualToplevel|UART1|RX_BUFFER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Selector9~0_combout\, + ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_BUFFER\(3)); + +-- Location: LABCELL_X14_Y6_N36 +\myVirtualToplevel|UART1|Selector10~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Selector10~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(3) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(3), + combout => \myVirtualToplevel|UART1|Selector10~0_combout\); + +-- Location: FF_X14_Y6_N38 +\myVirtualToplevel|UART1|RX_BUFFER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Selector10~0_combout\, + ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_BUFFER\(2)); + +-- Location: LABCELL_X14_Y6_N51 +\myVirtualToplevel|UART1|Selector11~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Selector11~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(2) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(2), + combout => \myVirtualToplevel|UART1|Selector11~0_combout\); + +-- Location: FF_X14_Y6_N53 +\myVirtualToplevel|UART1|RX_BUFFER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Selector11~0_combout\, + ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_BUFFER\(1)); + +-- Location: LABCELL_X14_Y6_N48 +\myVirtualToplevel|UART1|Selector12~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Selector12~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(1) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(1), + combout => \myVirtualToplevel|UART1|Selector12~0_combout\); + +-- Location: FF_X14_Y6_N49 +\myVirtualToplevel|UART1|RX_BUFFER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Selector12~0_combout\, + ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_BUFFER\(0)); + +-- Location: LABCELL_X16_Y6_N24 +\myVirtualToplevel|UART1|RX_STATE.bits~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_STATE.bits~0_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ & ( \myVirtualToplevel|UART1|RXD_SYNC~q\ & ( (!\myVirtualToplevel|UART1|RX_BUFFER\(0)) # (\myVirtualToplevel|UART1|RX_ENABLE~q\) ) ) ) # ( +-- \myVirtualToplevel|UART1|RX_STATE.bits~q\ & ( !\myVirtualToplevel|UART1|RXD_SYNC~q\ & ( (!\myVirtualToplevel|UART1|RX_BUFFER\(0)) # ((\myVirtualToplevel|UART1|RX_STATE.start~q\) # (\myVirtualToplevel|UART1|RX_ENABLE~q\)) ) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_STATE.bits~q\ & ( !\myVirtualToplevel|UART1|RXD_SYNC~q\ & ( (\myVirtualToplevel|UART1|RX_STATE.stop~0_combout\ & \myVirtualToplevel|UART1|RX_STATE.start~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101110011111111111100000000000000001100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~0_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(0), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~q\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\, + combout => \myVirtualToplevel|UART1|RX_STATE.bits~0_combout\); + +-- Location: FF_X16_Y6_N25 +\myVirtualToplevel|UART1|RX_STATE.bits\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_STATE.bits~0_combout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_STATE.bits~q\); + +-- Location: LABCELL_X16_Y6_N57 +\myVirtualToplevel|UART1|RX_STATE.stop~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_STATE.stop~2_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.stop~0_combout\ & ( (!\myVirtualToplevel|UART1|RX_STATE.bits~q\) # ((!\myVirtualToplevel|UART1|RX_ENABLE~q\ & \myVirtualToplevel|UART1|RX_BUFFER\(0))) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_STATE.stop~0_combout\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE~q\ & (\myVirtualToplevel|UART1|RX_STATE.bits~q\ & \myVirtualToplevel|UART1|RX_BUFFER\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010000000000000101011110000111110101111000011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(0), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~0_combout\, + combout => \myVirtualToplevel|UART1|RX_STATE.stop~2_combout\); + +-- Location: LABCELL_X16_Y6_N9 +\myVirtualToplevel|UART1|RX_STATE.start~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_STATE.start~0_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.stop~2_combout\ & ( !\myVirtualToplevel|UART1|RX_STATE.idle~q\ ) ) # ( !\myVirtualToplevel|UART1|RX_STATE.stop~2_combout\ & ( +-- \myVirtualToplevel|UART1|RX_STATE.start~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~2_combout\, + combout => \myVirtualToplevel|UART1|RX_STATE.start~0_combout\); + +-- Location: FF_X16_Y6_N11 +\myVirtualToplevel|UART1|RX_STATE.start\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_STATE.start~0_combout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_STATE.start~q\); + +-- Location: LABCELL_X16_Y6_N6 +\myVirtualToplevel|UART1|RX_STATE.idle~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_STATE.idle~0_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.stop~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_STATE.start~q\ & (!\myVirtualToplevel|UART1|RX_STATE.stop~q\)) # (\myVirtualToplevel|UART1|RX_STATE.start~q\ & +-- ((!\myVirtualToplevel|UART1|RXD_SYNC~q\))) ) ) # ( !\myVirtualToplevel|UART1|RX_STATE.stop~2_combout\ & ( \myVirtualToplevel|UART1|RX_STATE.idle~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111110111000101110001011100010111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~q\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~2_combout\, + combout => \myVirtualToplevel|UART1|RX_STATE.idle~0_combout\); + +-- Location: FF_X16_Y6_N8 +\myVirtualToplevel|UART1|RX_STATE.idle\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_STATE.idle~0_combout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_STATE.idle~q\); + +-- Location: LABCELL_X19_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]~feeder_combout\); + +-- Location: FF_X19_Y18_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(14)); + +-- Location: FF_X19_Y18_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(14)); + +-- Location: LABCELL_X19_Y18_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(14) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(14) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\); + +-- Location: LABCELL_X6_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]_NEW2721\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]_OTERM2722\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]_OTERM2722\); + +-- Location: FF_X6_Y21_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]_OTERM2722\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14)); + +-- Location: LABCELL_X10_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]_NEW2849\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]_OTERM2850\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(14) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]_OTERM2850\); + +-- Location: FF_X10_Y22_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]_OTERM2850\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(14)); + +-- Location: LABCELL_X10_Y22_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]_NEW2785\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]_OTERM2786\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(14) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]_OTERM2786\); + +-- Location: FF_X10_Y22_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]_OTERM2786\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(14)); + +-- Location: LABCELL_X6_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]_NEW2913\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]_OTERM2914\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]_OTERM2914\); + +-- Location: FF_X6_Y21_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]_OTERM2914\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14)); + +-- Location: LABCELL_X5_Y21_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(14)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(14)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(14)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(14)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101101011111010111100100010011101110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1_combout\); + +-- Location: MLABCELL_X13_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]_NEW2977\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]_OTERM2978\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101000100011010111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]_OTERM2978\); + +-- Location: FF_X13_Y22_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]_OTERM2978\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14)); + +-- Location: MLABCELL_X13_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]_NEW3041\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]_OTERM3042\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(14) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]_OTERM3042\); + +-- Location: FF_X13_Y22_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]_OTERM3042\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(14)); + +-- Location: MLABCELL_X13_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]_NEW3105\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]_OTERM3106\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]_OTERM3106\); + +-- Location: FF_X13_Y22_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]_OTERM3106\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14)); + +-- Location: MLABCELL_X13_Y22_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]_NEW3169\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]_OTERM3170\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]_OTERM3170\); + +-- Location: FF_X13_Y22_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]_OTERM3170\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14)); + +-- Location: MLABCELL_X13_Y22_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(14)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(14)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101101011111010111100010001101110110001000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0_combout\); + +-- Location: LABCELL_X6_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101010000000001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2_combout\); + +-- Location: MLABCELL_X9_Y14_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~feeder_combout\); + +-- Location: FF_X9_Y14_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\); + +-- Location: LABCELL_X16_Y8_N12 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( \myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\); + +-- Location: FF_X16_Y7_N50 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(14)); + +-- Location: LABCELL_X14_Y7_N3 +\myVirtualToplevel|UART1|RX_COUNTER[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.idle~q\ & ( !\myVirtualToplevel|UART1|RX_ENABLE~q\ ) ) # ( !\myVirtualToplevel|UART1|RX_STATE.idle~q\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE~q\ & +-- !\myVirtualToplevel|UART1|RXD_SYNC~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + combout => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\); + +-- Location: FF_X16_Y7_N4 +\myVirtualToplevel|UART1|RX_COUNTER[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~16_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(14), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(13)); + +-- Location: FF_X20_Y18_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(12)); + +-- Location: LABCELL_X20_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~147_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]~feeder_combout\); + +-- Location: FF_X20_Y16_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(12)); + +-- Location: LABCELL_X20_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(12) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(12)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(12)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\); + +-- Location: MLABCELL_X9_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]_NEW3173\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]_OTERM3174\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]_OTERM3174\); + +-- Location: FF_X9_Y20_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]_OTERM3174\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(12)); + +-- Location: MLABCELL_X9_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]_NEW3109\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]_OTERM3110\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]_OTERM3110\); + +-- Location: FF_X9_Y20_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]_OTERM3110\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(12)); + +-- Location: MLABCELL_X9_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]_NEW2981\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]_OTERM2982\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]_OTERM2982\); + +-- Location: FF_X9_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]_OTERM2982\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(12)); + +-- Location: MLABCELL_X9_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]_NEW3045\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]_OTERM3046\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]_OTERM3046\); + +-- Location: FF_X9_Y20_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]_OTERM3046\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(12)); + +-- Location: MLABCELL_X9_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(12) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(12) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(12) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(12) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0_combout\); + +-- Location: MLABCELL_X9_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]_NEW2725\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]_OTERM2726\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101000100011010111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]_OTERM2726\); + +-- Location: FF_X9_Y20_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]_OTERM2726\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(12)); + +-- Location: MLABCELL_X9_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]_NEW2789\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]_OTERM2790\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(12) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]_OTERM2790\); + +-- Location: FF_X9_Y20_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]_OTERM2790\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(12)); + +-- Location: MLABCELL_X9_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]_NEW2917\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]_OTERM2918\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]_OTERM2918\); + +-- Location: FF_X9_Y20_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]_OTERM2918\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(12)); + +-- Location: LABCELL_X10_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]_NEW2853\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]_OTERM2854\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(12))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]_OTERM2854\); + +-- Location: FF_X10_Y22_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]_OTERM2854\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(12)); + +-- Location: MLABCELL_X9_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(12) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(12) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(12) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(12) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1_combout\); + +-- Location: MLABCELL_X9_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux93~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux93~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux93~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~2_combout\); + +-- Location: FF_X9_Y14_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~2_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12)); + +-- Location: FF_X14_Y7_N35 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(12)); + +-- Location: FF_X16_Y7_N8 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(11)); + +-- Location: LABCELL_X14_Y7_N39 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(10), + combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~0_combout\); + +-- Location: FF_X14_Y7_N41 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(10)); + +-- Location: LABCELL_X14_Y7_N36 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~4_combout\); + +-- Location: FF_X14_Y7_N37 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(5)); + +-- Location: LABCELL_X14_Y7_N21 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~1_combout\); + +-- Location: FF_X14_Y7_N22 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(2)); + +-- Location: FF_X16_Y8_N58 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(1)); + +-- Location: LABCELL_X14_Y7_N48 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]~5_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]~5_combout\); + +-- Location: FF_X14_Y7_N50 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(0)); + +-- Location: LABCELL_X16_Y7_N0 +\myVirtualToplevel|UART1|RX_COUNTER~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~15_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & ((!\myVirtualToplevel|UART1|RX_COUNTER\(0)))) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & (!\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(0))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110000110000111111000011000011111100001100001111110000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(0), + datad => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(0), + combout => \myVirtualToplevel|UART1|RX_COUNTER~15_combout\); + +-- Location: FF_X16_Y7_N1 +\myVirtualToplevel|UART1|RX_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~15_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(1), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(0)); + +-- Location: LABCELL_X17_Y7_N0 +\myVirtualToplevel|UART1|Add1~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~54\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(0), + cin => GND, + cout => \myVirtualToplevel|UART1|Add1~54\); + +-- Location: LABCELL_X17_Y7_N3 +\myVirtualToplevel|UART1|Add1~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~17_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~54\ )) +-- \myVirtualToplevel|UART1|Add1~18\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(1), + cin => \myVirtualToplevel|UART1|Add1~54\, + sumout => \myVirtualToplevel|UART1|Add1~17_sumout\, + cout => \myVirtualToplevel|UART1|Add1~18\); + +-- Location: LABCELL_X16_Y7_N18 +\myVirtualToplevel|UART1|RX_COUNTER~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~6_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & ((\myVirtualToplevel|UART1|Add1~17_sumout\))) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & (\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(1))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(1), + datad => \myVirtualToplevel|UART1|ALT_INV_Add1~17_sumout\, + combout => \myVirtualToplevel|UART1|RX_COUNTER~6_combout\); + +-- Location: LABCELL_X14_Y7_N18 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~_wirecell_combout\ = ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(2), + combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~_wirecell_combout\); + +-- Location: FF_X16_Y7_N19 +\myVirtualToplevel|UART1|RX_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~6_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~_wirecell_combout\, + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(1)); + +-- Location: LABCELL_X17_Y7_N6 +\myVirtualToplevel|UART1|Add1~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~21_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~18\ )) +-- \myVirtualToplevel|UART1|Add1~22\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(2), + cin => \myVirtualToplevel|UART1|Add1~18\, + sumout => \myVirtualToplevel|UART1|Add1~21_sumout\, + cout => \myVirtualToplevel|UART1|Add1~22\); + +-- Location: LABCELL_X17_Y7_N51 +\myVirtualToplevel|UART1|RX_COUNTER~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~7_combout\ = ( \myVirtualToplevel|UART1|Equal1~4_combout\ & ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(2) ) ) # ( !\myVirtualToplevel|UART1|Equal1~4_combout\ & ( \myVirtualToplevel|UART1|Add1~21_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111110101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(2), + datac => \myVirtualToplevel|UART1|ALT_INV_Add1~21_sumout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + combout => \myVirtualToplevel|UART1|RX_COUNTER~7_combout\); + +-- Location: LABCELL_X14_Y7_N51 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~2_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~2_combout\); + +-- Location: FF_X14_Y7_N52 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(3)); + +-- Location: LABCELL_X16_Y7_N42 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~_wirecell_combout\ = !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(3) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(3), + combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~_wirecell_combout\); + +-- Location: FF_X17_Y7_N53 +\myVirtualToplevel|UART1|RX_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~7_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~_wirecell_combout\, + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(2)); + +-- Location: LABCELL_X17_Y7_N9 +\myVirtualToplevel|UART1|Add1~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~25_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~22\ )) +-- \myVirtualToplevel|UART1|Add1~26\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(3), + cin => \myVirtualToplevel|UART1|Add1~22\, + sumout => \myVirtualToplevel|UART1|Add1~25_sumout\, + cout => \myVirtualToplevel|UART1|Add1~26\); + +-- Location: LABCELL_X16_Y7_N33 +\myVirtualToplevel|UART1|RX_COUNTER~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~8_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & (\myVirtualToplevel|UART1|Add1~25_sumout\)) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & ((!\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(3)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111010001110100011101000111010001110100011101000111010001110100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_Add1~25_sumout\, + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(3), + combout => \myVirtualToplevel|UART1|RX_COUNTER~8_combout\); + +-- Location: LABCELL_X14_Y7_N30 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~3_combout\); + +-- Location: FF_X16_Y7_N46 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(4)); + +-- Location: LABCELL_X16_Y7_N45 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~_wirecell_combout\ = !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(4) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(4), + combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~_wirecell_combout\); + +-- Location: FF_X16_Y7_N34 +\myVirtualToplevel|UART1|RX_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~8_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~_wirecell_combout\, + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(3)); + +-- Location: LABCELL_X17_Y7_N12 +\myVirtualToplevel|UART1|Add1~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~29_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~26\ )) +-- \myVirtualToplevel|UART1|Add1~30\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(4), + cin => \myVirtualToplevel|UART1|Add1~26\, + sumout => \myVirtualToplevel|UART1|Add1~29_sumout\, + cout => \myVirtualToplevel|UART1|Add1~30\); + +-- Location: LABCELL_X16_Y7_N30 +\myVirtualToplevel|UART1|RX_COUNTER~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~9_combout\ = ( \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(4) & ( (!\myVirtualToplevel|UART1|Equal1~4_combout\ & \myVirtualToplevel|UART1|Add1~29_sumout\) ) ) # ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(4) & ( +-- (\myVirtualToplevel|UART1|Add1~29_sumout\) # (\myVirtualToplevel|UART1|Equal1~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111001111110011111100001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Add1~29_sumout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(4), + combout => \myVirtualToplevel|UART1|RX_COUNTER~9_combout\); + +-- Location: LABCELL_X16_Y7_N51 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~_wirecell_combout\ = ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(5), + combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~_wirecell_combout\); + +-- Location: FF_X16_Y7_N31 +\myVirtualToplevel|UART1|RX_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~9_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~_wirecell_combout\, + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(4)); + +-- Location: LABCELL_X17_Y7_N15 +\myVirtualToplevel|UART1|Add1~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~33_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~30\ )) +-- \myVirtualToplevel|UART1|Add1~34\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(5), + cin => \myVirtualToplevel|UART1|Add1~30\, + sumout => \myVirtualToplevel|UART1|Add1~33_sumout\, + cout => \myVirtualToplevel|UART1|Add1~34\); + +-- Location: LABCELL_X16_Y7_N15 +\myVirtualToplevel|UART1|RX_COUNTER~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~10_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & ((\myVirtualToplevel|UART1|Add1~33_sumout\))) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & (!\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(5))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010111000101110001011100010111000101110001011100010111000101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(5), + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Add1~33_sumout\, + combout => \myVirtualToplevel|UART1|RX_COUNTER~10_combout\); + +-- Location: FF_X14_Y7_N55 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(6)); + +-- Location: FF_X16_Y7_N16 +\myVirtualToplevel|UART1|RX_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~10_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(6), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(5)); + +-- Location: LABCELL_X17_Y7_N18 +\myVirtualToplevel|UART1|Add1~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~37_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~34\ )) +-- \myVirtualToplevel|UART1|Add1~38\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(6), + cin => \myVirtualToplevel|UART1|Add1~34\, + sumout => \myVirtualToplevel|UART1|Add1~37_sumout\, + cout => \myVirtualToplevel|UART1|Add1~38\); + +-- Location: LABCELL_X16_Y7_N36 +\myVirtualToplevel|UART1|RX_COUNTER~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~11_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & (\myVirtualToplevel|UART1|Add1~37_sumout\)) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & ((\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(6)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Add1~37_sumout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(6), + combout => \myVirtualToplevel|UART1|RX_COUNTER~11_combout\); + +-- Location: FF_X16_Y7_N11 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(7)); + +-- Location: FF_X16_Y7_N37 +\myVirtualToplevel|UART1|RX_COUNTER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~11_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(7), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(6)); + +-- Location: LABCELL_X17_Y7_N21 +\myVirtualToplevel|UART1|Add1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~1_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~38\ )) +-- \myVirtualToplevel|UART1|Add1~2\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|UART1|Add1~38\, + sumout => \myVirtualToplevel|UART1|Add1~1_sumout\, + cout => \myVirtualToplevel|UART1|Add1~2\); + +-- Location: LABCELL_X16_Y7_N24 +\myVirtualToplevel|UART1|RX_COUNTER~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~2_combout\ = ( \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(7) & ( (\myVirtualToplevel|UART1|Add1~1_sumout\) # (\myVirtualToplevel|UART1|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(7) & ( +-- (!\myVirtualToplevel|UART1|Equal1~4_combout\ & \myVirtualToplevel|UART1|Add1~1_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Add1~1_sumout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(7), + combout => \myVirtualToplevel|UART1|RX_COUNTER~2_combout\); + +-- Location: LABCELL_X14_Y7_N57 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(8), + combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]~feeder_combout\); + +-- Location: FF_X14_Y7_N58 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(8)); + +-- Location: FF_X16_Y7_N25 +\myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~2_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(8), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y7_N24 +\myVirtualToplevel|UART1|Add1~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~5_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~2\ )) +-- \myVirtualToplevel|UART1|Add1~6\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(8), + cin => \myVirtualToplevel|UART1|Add1~2\, + sumout => \myVirtualToplevel|UART1|Add1~5_sumout\, + cout => \myVirtualToplevel|UART1|Add1~6\); + +-- Location: LABCELL_X16_Y7_N27 +\myVirtualToplevel|UART1|RX_COUNTER~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~3_combout\ = ( \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(8) & ( (\myVirtualToplevel|UART1|Add1~5_sumout\) # (\myVirtualToplevel|UART1|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(8) & ( +-- (!\myVirtualToplevel|UART1|Equal1~4_combout\ & \myVirtualToplevel|UART1|Add1~5_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Add1~5_sumout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(8), + combout => \myVirtualToplevel|UART1|RX_COUNTER~3_combout\); + +-- Location: FF_X16_Y8_N16 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(9)); + +-- Location: FF_X16_Y7_N28 +\myVirtualToplevel|UART1|RX_COUNTER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~3_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(9), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(8)); + +-- Location: LABCELL_X17_Y7_N27 +\myVirtualToplevel|UART1|Add1~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~9_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~6\ )) +-- \myVirtualToplevel|UART1|Add1~10\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(9), + cin => \myVirtualToplevel|UART1|Add1~6\, + sumout => \myVirtualToplevel|UART1|Add1~9_sumout\, + cout => \myVirtualToplevel|UART1|Add1~10\); + +-- Location: LABCELL_X16_Y7_N21 +\myVirtualToplevel|UART1|RX_COUNTER~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~4_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & (\myVirtualToplevel|UART1|Add1~9_sumout\)) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & ((\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(9)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_Add1~9_sumout\, + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(9), + combout => \myVirtualToplevel|UART1|RX_COUNTER~4_combout\); + +-- Location: LABCELL_X16_Y7_N6 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~_wirecell_combout\ = ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(10), + combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~_wirecell_combout\); + +-- Location: FF_X16_Y7_N22 +\myVirtualToplevel|UART1|RX_COUNTER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~4_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~_wirecell_combout\, + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(9)); + +-- Location: LABCELL_X17_Y7_N30 +\myVirtualToplevel|UART1|Add1~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~13_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~10\ )) +-- \myVirtualToplevel|UART1|Add1~14\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[10]~DUPLICATE_q\, + cin => \myVirtualToplevel|UART1|Add1~10\, + sumout => \myVirtualToplevel|UART1|Add1~13_sumout\, + cout => \myVirtualToplevel|UART1|Add1~14\); + +-- Location: LABCELL_X16_Y7_N12 +\myVirtualToplevel|UART1|RX_COUNTER~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~5_combout\ = ( \myVirtualToplevel|UART1|Add1~13_sumout\ & ( (!\myVirtualToplevel|UART1|Equal1~4_combout\) # (!\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(10)) ) ) # ( !\myVirtualToplevel|UART1|Add1~13_sumout\ & ( +-- (\myVirtualToplevel|UART1|Equal1~4_combout\ & !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(10)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000011111100111111001111110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(10), + dataf => \myVirtualToplevel|UART1|ALT_INV_Add1~13_sumout\, + combout => \myVirtualToplevel|UART1|RX_COUNTER~5_combout\); + +-- Location: FF_X16_Y7_N13 +\myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~5_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(11), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y7_N33 +\myVirtualToplevel|UART1|Add1~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~41_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~14\ )) +-- \myVirtualToplevel|UART1|Add1~42\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(11), + cin => \myVirtualToplevel|UART1|Add1~14\, + sumout => \myVirtualToplevel|UART1|Add1~41_sumout\, + cout => \myVirtualToplevel|UART1|Add1~42\); + +-- Location: LABCELL_X16_Y7_N39 +\myVirtualToplevel|UART1|RX_COUNTER~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~12_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & ((\myVirtualToplevel|UART1|Add1~41_sumout\))) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & (\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(11))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(11), + datad => \myVirtualToplevel|UART1|ALT_INV_Add1~41_sumout\, + combout => \myVirtualToplevel|UART1|RX_COUNTER~12_combout\); + +-- Location: FF_X16_Y7_N40 +\myVirtualToplevel|UART1|RX_COUNTER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~12_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(12), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(11)); + +-- Location: LABCELL_X17_Y7_N36 +\myVirtualToplevel|UART1|Add1~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~45_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~42\ )) +-- \myVirtualToplevel|UART1|Add1~46\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(12), + cin => \myVirtualToplevel|UART1|Add1~42\, + sumout => \myVirtualToplevel|UART1|Add1~45_sumout\, + cout => \myVirtualToplevel|UART1|Add1~46\); + +-- Location: LABCELL_X16_Y7_N54 +\myVirtualToplevel|UART1|RX_COUNTER~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~13_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & ((\myVirtualToplevel|UART1|Add1~45_sumout\))) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & (\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(12))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(12), + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Add1~45_sumout\, + combout => \myVirtualToplevel|UART1|RX_COUNTER~13_combout\); + +-- Location: FF_X16_Y7_N53 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(13)); + +-- Location: FF_X16_Y7_N55 +\myVirtualToplevel|UART1|RX_COUNTER[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~13_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(13), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(12)); + +-- Location: LABCELL_X17_Y7_N39 +\myVirtualToplevel|UART1|Add1~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~57_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~46\ )) +-- \myVirtualToplevel|UART1|Add1~58\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(13), + cin => \myVirtualToplevel|UART1|Add1~46\, + sumout => \myVirtualToplevel|UART1|Add1~57_sumout\, + cout => \myVirtualToplevel|UART1|Add1~58\); + +-- Location: LABCELL_X16_Y7_N3 +\myVirtualToplevel|UART1|RX_COUNTER~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~16_combout\ = ( \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(13) & ( (\myVirtualToplevel|UART1|Add1~57_sumout\) # (\myVirtualToplevel|UART1|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(13) & ( +-- (!\myVirtualToplevel|UART1|Equal1~4_combout\ & \myVirtualToplevel|UART1|Add1~57_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Add1~57_sumout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(13), + combout => \myVirtualToplevel|UART1|RX_COUNTER~16_combout\); + +-- Location: FF_X16_Y7_N5 +\myVirtualToplevel|UART1|RX_COUNTER[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~16_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(14), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER[13]~DUPLICATE_q\); + +-- Location: FF_X14_Y7_N46 +\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(15)); + +-- Location: FF_X16_Y7_N58 +\myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~17_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(15), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y7_N42 +\myVirtualToplevel|UART1|Add1~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~61_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~58\ )) +-- \myVirtualToplevel|UART1|Add1~62\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|UART1|Add1~58\, + sumout => \myVirtualToplevel|UART1|Add1~61_sumout\, + cout => \myVirtualToplevel|UART1|Add1~62\); + +-- Location: LABCELL_X16_Y7_N57 +\myVirtualToplevel|UART1|RX_COUNTER~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~17_combout\ = ( \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(14) & ( (\myVirtualToplevel|UART1|Add1~61_sumout\) # (\myVirtualToplevel|UART1|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(14) & ( +-- (!\myVirtualToplevel|UART1|Equal1~4_combout\ & \myVirtualToplevel|UART1|Add1~61_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Add1~61_sumout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(14), + combout => \myVirtualToplevel|UART1|RX_COUNTER~17_combout\); + +-- Location: FF_X16_Y7_N59 +\myVirtualToplevel|UART1|RX_COUNTER[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~17_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(15), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(14)); + +-- Location: FF_X16_Y7_N2 +\myVirtualToplevel|UART1|RX_COUNTER[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~15_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(1), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER[0]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y7_N45 +\myVirtualToplevel|UART1|Add1~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add1~49_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(15) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(15), + cin => \myVirtualToplevel|UART1|Add1~62\, + sumout => \myVirtualToplevel|UART1|Add1~49_sumout\); + +-- Location: LABCELL_X12_Y7_N36 +\myVirtualToplevel|UART1|RX_COUNTER~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_COUNTER~14_combout\ = ( \myVirtualToplevel|UART1|RX_COUNTER\(15) & ( \myVirtualToplevel|UART1|Equal1~4_combout\ & ( (!\myVirtualToplevel|UART1|RX_STATE.idle~q\ & ((\myVirtualToplevel|UART1|RXD_SYNC~q\))) # +-- (\myVirtualToplevel|UART1|RX_STATE.idle~q\ & (\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(15))) ) ) ) # ( !\myVirtualToplevel|UART1|RX_COUNTER\(15) & ( \myVirtualToplevel|UART1|Equal1~4_combout\ & ( (\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(15) & +-- \myVirtualToplevel|UART1|RX_STATE.idle~q\) ) ) ) # ( \myVirtualToplevel|UART1|RX_COUNTER\(15) & ( !\myVirtualToplevel|UART1|Equal1~4_combout\ & ( (!\myVirtualToplevel|UART1|RX_STATE.idle~q\ & ((\myVirtualToplevel|UART1|RXD_SYNC~q\))) # +-- (\myVirtualToplevel|UART1|RX_STATE.idle~q\ & (\myVirtualToplevel|UART1|Add1~49_sumout\)) ) ) ) # ( !\myVirtualToplevel|UART1|RX_COUNTER\(15) & ( !\myVirtualToplevel|UART1|Equal1~4_combout\ & ( (\myVirtualToplevel|UART1|Add1~49_sumout\ & +-- \myVirtualToplevel|UART1|RX_STATE.idle~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000111111001100000101000001010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(15), + datab => \myVirtualToplevel|UART1|ALT_INV_Add1~49_sumout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(15), + dataf => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + combout => \myVirtualToplevel|UART1|RX_COUNTER~14_combout\); + +-- Location: FF_X12_Y7_N37 +\myVirtualToplevel|UART1|RX_COUNTER[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~14_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(15)); + +-- Location: LABCELL_X16_Y7_N48 +\myVirtualToplevel|UART1|Equal1~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal1~3_combout\ = ( !\myVirtualToplevel|UART1|RX_COUNTER\(15) & ( (!\myVirtualToplevel|UART1|RX_COUNTER[13]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_COUNTER\(14) & !\myVirtualToplevel|UART1|RX_COUNTER[0]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000010000000100000001000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[13]~DUPLICATE_q\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(14), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(15), + combout => \myVirtualToplevel|UART1|Equal1~3_combout\); + +-- Location: LABCELL_X17_Y7_N48 +\myVirtualToplevel|UART1|Equal1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal1~1_combout\ = ( !\myVirtualToplevel|UART1|RX_COUNTER\(2) & ( (!\myVirtualToplevel|UART1|RX_COUNTER\(1) & (!\myVirtualToplevel|UART1|RX_COUNTER\(4) & !\myVirtualToplevel|UART1|RX_COUNTER\(3))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(1), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(4), + datad => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(3), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(2), + combout => \myVirtualToplevel|UART1|Equal1~1_combout\); + +-- Location: LABCELL_X17_Y7_N57 +\myVirtualToplevel|UART1|Equal1~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal1~2_combout\ = ( !\myVirtualToplevel|UART1|RX_COUNTER\(12) & ( (!\myVirtualToplevel|UART1|RX_COUNTER\(11) & (!\myVirtualToplevel|UART1|RX_COUNTER\(5) & !\myVirtualToplevel|UART1|RX_COUNTER\(6))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(11), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(5), + datad => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(6), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(12), + combout => \myVirtualToplevel|UART1|Equal1~2_combout\); + +-- Location: FF_X16_Y7_N26 +\myVirtualToplevel|UART1|RX_COUNTER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~2_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(8), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(7)); + +-- Location: FF_X16_Y7_N14 +\myVirtualToplevel|UART1|RX_COUNTER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_COUNTER~5_combout\, + asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(11), + sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_COUNTER\(10)); + +-- Location: LABCELL_X16_Y7_N9 +\myVirtualToplevel|UART1|Equal1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal1~0_combout\ = ( !\myVirtualToplevel|UART1|RX_COUNTER\(9) & ( (!\myVirtualToplevel|UART1|RX_COUNTER\(7) & (!\myVirtualToplevel|UART1|RX_COUNTER\(8) & !\myVirtualToplevel|UART1|RX_COUNTER\(10))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000010000000100000001000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(7), + datab => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(8), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(10), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(9), + combout => \myVirtualToplevel|UART1|Equal1~0_combout\); + +-- Location: LABCELL_X17_Y7_N54 +\myVirtualToplevel|UART1|Equal1~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal1~4_combout\ = ( \myVirtualToplevel|UART1|Equal1~0_combout\ & ( (\myVirtualToplevel|UART1|Equal1~3_combout\ & (\myVirtualToplevel|UART1|Equal1~1_combout\ & \myVirtualToplevel|UART1|Equal1~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~3_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Equal1~1_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_Equal1~2_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Equal1~0_combout\, + combout => \myVirtualToplevel|UART1|Equal1~4_combout\); + +-- Location: LABCELL_X12_Y7_N18 +\myVirtualToplevel|UART1|RX_CLOCK~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_CLOCK~0_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.idle~q\ & ( \myVirtualToplevel|UART1|Equal1~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\, + combout => \myVirtualToplevel|UART1|RX_CLOCK~0_combout\); + +-- Location: FF_X12_Y7_N19 +\myVirtualToplevel|UART1|RX_CLOCK\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_CLOCK~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_CLOCK~q\); + +-- Location: LABCELL_X14_Y7_N42 +\myVirtualToplevel|UART1|RX_STATE.stop~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_STATE.stop~0_combout\ = ( \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\ & ( \myVirtualToplevel|UART1|RX_STATE.idle~q\ & ( \myVirtualToplevel|UART1|RX_CLOCK~q\ ) ) ) # ( \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\ & ( +-- !\myVirtualToplevel|UART1|RX_STATE.idle~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK~q\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[0]~1_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\, + combout => \myVirtualToplevel|UART1|RX_STATE.stop~0_combout\); + +-- Location: LABCELL_X16_Y6_N39 +\myVirtualToplevel|UART1|RX_STATE.stop~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_STATE.stop~1_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.stop~q\ & ( (!\myVirtualToplevel|UART1|RX_STATE.stop~0_combout\) # (\myVirtualToplevel|UART1|RX_STATE.bits~q\) ) ) # ( !\myVirtualToplevel|UART1|RX_STATE.stop~q\ & ( +-- (\myVirtualToplevel|UART1|RX_STATE.bits~q\ & (\myVirtualToplevel|UART1|RX_BUFFER\(0) & !\myVirtualToplevel|UART1|RX_ENABLE~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000000000110000000010111011101110111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~0_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(0), + datad => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~q\, + combout => \myVirtualToplevel|UART1|RX_STATE.stop~1_combout\); + +-- Location: FF_X12_Y6_N37 +\myVirtualToplevel|UART1|RX_STATE.stop\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_STATE.stop~1_combout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_STATE.stop~q\); + +-- Location: LABCELL_X16_Y6_N33 +\myVirtualToplevel|UART1|RX_INTR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_INTR~0_combout\ = ( \myVirtualToplevel|UART1|RXD_SYNC~q\ & ( (\myVirtualToplevel|UART1|RX_STATE.stop~q\ & \myVirtualToplevel|UART1|RX_CLOCK~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\, + combout => \myVirtualToplevel|UART1|RX_INTR~0_combout\); + +-- Location: LABCELL_X14_Y7_N9 +\myVirtualToplevel|UART1|RX_ENABLE_FIFO~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_ENABLE_FIFO~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + combout => \myVirtualToplevel|UART1|RX_ENABLE_FIFO~0_combout\); + +-- Location: FF_X14_Y7_N10 +\myVirtualToplevel|UART1|RX_ENABLE_FIFO\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_ENABLE_FIFO~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_ENABLE~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\); + +-- Location: MLABCELL_X13_Y5_N57 +\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~1_combout\ = !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0), + combout => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~1_combout\); + +-- Location: MLABCELL_X13_Y7_N30 +\myVirtualToplevel|UART1|Add3~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add3~5_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|UART1|Add3~6\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(0), + cin => GND, + sumout => \myVirtualToplevel|UART1|Add3~5_sumout\, + cout => \myVirtualToplevel|UART1|Add3~6\); + +-- Location: MLABCELL_X13_Y9_N6 +\myVirtualToplevel|UART1|RX_DATA_READY~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA_READY~0_combout\ = ( \myVirtualToplevel|UART1|Equal7~0_combout\ & ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\, + datae => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|RX_DATA_READY~0_combout\); + +-- Location: LABCELL_X16_Y6_N42 +\myVirtualToplevel|UART1|RX_DATA_READY~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA_READY~1_combout\ = ( \myVirtualToplevel|UART1|RX_DATA_READY~0_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA_READY~q\ & ((!\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ & ((!\myVirtualToplevel|UART1|Equal2~4_combout\))) # +-- (\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ & (\myVirtualToplevel|UART1|RX_INTR~0_combout\)))) ) ) # ( !\myVirtualToplevel|UART1|RX_DATA_READY~0_combout\ & ( ((!\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ & ((!\myVirtualToplevel|UART1|Equal2~4_combout\))) +-- # (\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ & (\myVirtualToplevel|UART1|RX_INTR~0_combout\))) # (\myVirtualToplevel|UART1|RX_DATA_READY~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101000111111111110100011111111111010001000000001101000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_Equal2~4_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~0_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA_READY~1_combout\); + +-- Location: FF_X16_Y6_N44 +\myVirtualToplevel|UART1|RX_DATA_READY\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_DATA_READY~1_combout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_DATA_READY~q\); + +-- Location: LABCELL_X16_Y6_N30 +\myVirtualToplevel|UART1|process_3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|process_3~0_combout\ = ( !\myVirtualToplevel|UART1|RX_DATA_READY~q\ & ( !\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~q\, + combout => \myVirtualToplevel|UART1|process_3~0_combout\); + +-- Location: MLABCELL_X13_Y5_N36 +\myVirtualToplevel|UART1|Add4~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add4~9_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~14\ )) +-- \myVirtualToplevel|UART1|Add4~10\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3), + cin => \myVirtualToplevel|UART1|Add4~14\, + sumout => \myVirtualToplevel|UART1|Add4~9_sumout\, + cout => \myVirtualToplevel|UART1|Add4~10\); + +-- Location: MLABCELL_X13_Y5_N39 +\myVirtualToplevel|UART1|Add4~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add4~1_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~10\ )) +-- \myVirtualToplevel|UART1|Add4~2\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(4), + cin => \myVirtualToplevel|UART1|Add4~10\, + sumout => \myVirtualToplevel|UART1|Add4~1_sumout\, + cout => \myVirtualToplevel|UART1|Add4~2\); + +-- Location: FF_X13_Y5_N41 +\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add4~1_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4)); + +-- Location: MLABCELL_X13_Y5_N42 +\myVirtualToplevel|UART1|Add4~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add4~21_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~2\ )) +-- \myVirtualToplevel|UART1|Add4~22\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(5), + cin => \myVirtualToplevel|UART1|Add4~2\, + sumout => \myVirtualToplevel|UART1|Add4~21_sumout\, + cout => \myVirtualToplevel|UART1|Add4~22\); + +-- Location: FF_X13_Y5_N43 +\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add4~21_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5)); + +-- Location: MLABCELL_X13_Y5_N45 +\myVirtualToplevel|UART1|Add4~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add4~17_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~22\ )) +-- \myVirtualToplevel|UART1|Add4~18\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6), + cin => \myVirtualToplevel|UART1|Add4~22\, + sumout => \myVirtualToplevel|UART1|Add4~17_sumout\, + cout => \myVirtualToplevel|UART1|Add4~18\); + +-- Location: FF_X13_Y5_N46 +\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add4~17_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6)); + +-- Location: MLABCELL_X13_Y7_N45 +\myVirtualToplevel|UART1|Add3~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add3~25_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~2\ )) +-- \myVirtualToplevel|UART1|Add3~26\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(5), + cin => \myVirtualToplevel|UART1|Add3~2\, + sumout => \myVirtualToplevel|UART1|Add3~25_sumout\, + cout => \myVirtualToplevel|UART1|Add3~26\); + +-- Location: MLABCELL_X13_Y7_N48 +\myVirtualToplevel|UART1|Add3~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add3~21_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~26\ )) +-- \myVirtualToplevel|UART1|Add3~22\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(6), + cin => \myVirtualToplevel|UART1|Add3~26\, + sumout => \myVirtualToplevel|UART1|Add3~21_sumout\, + cout => \myVirtualToplevel|UART1|Add3~22\); + +-- Location: FF_X13_Y7_N50 +\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add3~21_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6)); + +-- Location: LABCELL_X16_Y5_N12 +\myVirtualToplevel|UART1|Equal2~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal2~2_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & ( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) & ( (\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6)) ) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & ( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) & ( (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6)) ) ) ) # ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & ( +-- !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) & ( (\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) & !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6)) ) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & ( !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) & ( +-- (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) & !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000010100000101000000001010000010100000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6), + datae => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(6), + combout => \myVirtualToplevel|UART1|Equal2~2_combout\); + +-- Location: MLABCELL_X13_Y5_N30 +\myVirtualToplevel|UART1|Add4~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add4~5_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) ) + ( !VCC )) +-- \myVirtualToplevel|UART1|Add4~6\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0), + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1), + cin => GND, + sumout => \myVirtualToplevel|UART1|Add4~5_sumout\, + cout => \myVirtualToplevel|UART1|Add4~6\); + +-- Location: FF_X13_Y5_N31 +\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add4~5_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1)); + +-- Location: FF_X13_Y7_N28 +\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|Add3~5_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y5_N54 +\myVirtualToplevel|UART1|Equal2~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal2~0_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( (\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1)))) ) +-- ) # ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001100000000110000110000000000000000110000110000000011000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1), + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0), + combout => \myVirtualToplevel|UART1|Equal2~0_combout\); + +-- Location: MLABCELL_X13_Y7_N51 +\myVirtualToplevel|UART1|Add3~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add3~29_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(7), + cin => \myVirtualToplevel|UART1|Add3~22\, + sumout => \myVirtualToplevel|UART1|Add3~29_sumout\); + +-- Location: FF_X13_Y7_N53 +\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add3~29_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7)); + +-- Location: MLABCELL_X13_Y5_N48 +\myVirtualToplevel|UART1|Add4~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add4~25_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7), + cin => \myVirtualToplevel|UART1|Add4~18\, + sumout => \myVirtualToplevel|UART1|Add4~25_sumout\); + +-- Location: FF_X14_Y5_N19 +\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|Add4~25_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7)); + +-- Location: LABCELL_X16_Y5_N54 +\myVirtualToplevel|UART1|Equal2~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal2~3_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) & ( (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) & \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7)) ) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) & \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7)) ) ) ) # ( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) & ( +-- !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) & ( (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) & !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7)) ) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) & ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) & ( +-- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) & !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000010100000101000000001010000010100000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(5), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(7), + datae => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(5), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7), + combout => \myVirtualToplevel|UART1|Equal2~3_combout\); + +-- Location: LABCELL_X16_Y6_N18 +\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\ = ( \myVirtualToplevel|UART1|Equal2~0_combout\ & ( \myVirtualToplevel|UART1|Equal2~3_combout\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE~q\ & (\myVirtualToplevel|UART1|process_3~0_combout\ & +-- ((!\myVirtualToplevel|UART1|Equal2~2_combout\) # (!\myVirtualToplevel|UART1|Equal2~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|UART1|Equal2~0_combout\ & ( \myVirtualToplevel|UART1|Equal2~3_combout\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE~q\ & +-- \myVirtualToplevel|UART1|process_3~0_combout\) ) ) ) # ( \myVirtualToplevel|UART1|Equal2~0_combout\ & ( !\myVirtualToplevel|UART1|Equal2~3_combout\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE~q\ & \myVirtualToplevel|UART1|process_3~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|UART1|Equal2~0_combout\ & ( !\myVirtualToplevel|UART1|Equal2~3_combout\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE~q\ & \myVirtualToplevel|UART1|process_3~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001000100010001000100010001000100010001000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + datab => \myVirtualToplevel|UART1|ALT_INV_process_3~0_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Equal2~2_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_Equal2~1_combout\, + datae => \myVirtualToplevel|UART1|ALT_INV_Equal2~0_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Equal2~3_combout\, + combout => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\); + +-- Location: FF_X13_Y7_N29 +\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|Add3~5_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(0)); + +-- Location: MLABCELL_X13_Y7_N33 +\myVirtualToplevel|UART1|Add3~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add3~9_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~6\ )) +-- \myVirtualToplevel|UART1|Add3~10\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1), + cin => \myVirtualToplevel|UART1|Add3~6\, + sumout => \myVirtualToplevel|UART1|Add3~9_sumout\, + cout => \myVirtualToplevel|UART1|Add3~10\); + +-- Location: FF_X13_Y7_N59 +\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|Add3~9_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1)); + +-- Location: MLABCELL_X13_Y7_N36 +\myVirtualToplevel|UART1|Add3~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add3~17_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~10\ )) +-- \myVirtualToplevel|UART1|Add3~18\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|UART1|Add3~10\, + sumout => \myVirtualToplevel|UART1|Add3~17_sumout\, + cout => \myVirtualToplevel|UART1|Add3~18\); + +-- Location: FF_X13_Y7_N38 +\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add3~17_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2)); + +-- Location: MLABCELL_X13_Y7_N39 +\myVirtualToplevel|UART1|Add3~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add3~13_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~18\ )) +-- \myVirtualToplevel|UART1|Add3~14\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|UART1|Add3~18\, + sumout => \myVirtualToplevel|UART1|Add3~13_sumout\, + cout => \myVirtualToplevel|UART1|Add3~14\); + +-- Location: FF_X13_Y7_N41 +\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add3~13_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3)); + +-- Location: MLABCELL_X13_Y7_N42 +\myVirtualToplevel|UART1|Add3~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add3~1_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~14\ )) +-- \myVirtualToplevel|UART1|Add3~2\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|UART1|Add3~14\, + sumout => \myVirtualToplevel|UART1|Add3~1_sumout\, + cout => \myVirtualToplevel|UART1|Add3~2\); + +-- Location: FF_X13_Y7_N44 +\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add3~1_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4)); + +-- Location: FF_X13_Y7_N47 +\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add3~25_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5)); + +-- Location: LABCELL_X14_Y5_N30 +\myVirtualToplevel|UART1|Add2~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add2~22\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\, + cin => GND, + cout => \myVirtualToplevel|UART1|Add2~22\); + +-- Location: LABCELL_X14_Y5_N33 +\myVirtualToplevel|UART1|Add2~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add2~25_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~22\ )) +-- \myVirtualToplevel|UART1|Add2~26\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1), + cin => \myVirtualToplevel|UART1|Add2~22\, + sumout => \myVirtualToplevel|UART1|Add2~25_sumout\, + cout => \myVirtualToplevel|UART1|Add2~26\); + +-- Location: LABCELL_X14_Y5_N36 +\myVirtualToplevel|UART1|Add2~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add2~29_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~26\ )) +-- \myVirtualToplevel|UART1|Add2~30\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|UART1|Add2~26\, + sumout => \myVirtualToplevel|UART1|Add2~29_sumout\, + cout => \myVirtualToplevel|UART1|Add2~30\); + +-- Location: LABCELL_X14_Y5_N39 +\myVirtualToplevel|UART1|Add2~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add2~9_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~30\ )) +-- \myVirtualToplevel|UART1|Add2~10\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|UART1|Add2~30\, + sumout => \myVirtualToplevel|UART1|Add2~9_sumout\, + cout => \myVirtualToplevel|UART1|Add2~10\); + +-- Location: LABCELL_X14_Y5_N42 +\myVirtualToplevel|UART1|Add2~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add2~13_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~10\ )) +-- \myVirtualToplevel|UART1|Add2~14\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|UART1|Add2~10\, + sumout => \myVirtualToplevel|UART1|Add2~13_sumout\, + cout => \myVirtualToplevel|UART1|Add2~14\); + +-- Location: LABCELL_X14_Y5_N45 +\myVirtualToplevel|UART1|Add2~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add2~17_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~14\ )) +-- \myVirtualToplevel|UART1|Add2~18\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(5), + cin => \myVirtualToplevel|UART1|Add2~14\, + sumout => \myVirtualToplevel|UART1|Add2~17_sumout\, + cout => \myVirtualToplevel|UART1|Add2~18\); + +-- Location: FF_X13_Y5_N44 +\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add4~21_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\); + +-- Location: MLABCELL_X13_Y5_N24 +\myVirtualToplevel|UART1|Equal3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal3~0_combout\ = ( \myVirtualToplevel|UART1|Add2~13_sumout\ & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) & ( (!\myVirtualToplevel|UART1|Add2~17_sumout\ & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|UART1|Add2~9_sumout\ $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3))))) # (\myVirtualToplevel|UART1|Add2~17_sumout\ & (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|Add2~9_sumout\ $ +-- (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3))))) ) ) ) # ( !\myVirtualToplevel|UART1|Add2~13_sumout\ & ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) & ( (!\myVirtualToplevel|UART1|Add2~17_sumout\ & +-- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|Add2~9_sumout\ $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3))))) # (\myVirtualToplevel|UART1|Add2~17_sumout\ & +-- (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|Add2~9_sumout\ $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001000000001001000000000000000000000000000000001001000000001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_Add2~17_sumout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|UART1|ALT_INV_Add2~9_sumout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3), + datae => \myVirtualToplevel|UART1|ALT_INV_Add2~13_sumout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(4), + combout => \myVirtualToplevel|UART1|Equal3~0_combout\); + +-- Location: LABCELL_X14_Y5_N48 +\myVirtualToplevel|UART1|Add2~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add2~1_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~18\ )) +-- \myVirtualToplevel|UART1|Add2~2\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(6), + cin => \myVirtualToplevel|UART1|Add2~18\, + sumout => \myVirtualToplevel|UART1|Add2~1_sumout\, + cout => \myVirtualToplevel|UART1|Add2~2\); + +-- Location: LABCELL_X14_Y5_N51 +\myVirtualToplevel|UART1|Add2~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add2~5_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(7), + cin => \myVirtualToplevel|UART1|Add2~2\, + sumout => \myVirtualToplevel|UART1|Add2~5_sumout\); + +-- Location: LABCELL_X14_Y5_N21 +\myVirtualToplevel|UART1|Equal3~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal3~1_combout\ = ( \myVirtualToplevel|UART1|Add2~29_sumout\ & ( \myVirtualToplevel|UART1|Add2~25_sumout\ & ( (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) & (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & +-- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|UART1|Add2~29_sumout\ & ( \myVirtualToplevel|UART1|Add2~25_sumout\ & ( +-- (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|UART1|Add2~29_sumout\ & ( !\myVirtualToplevel|UART1|Add2~25_sumout\ & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) & (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) $ +-- (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|UART1|Add2~29_sumout\ & ( !\myVirtualToplevel|UART1|Add2~25_sumout\ & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) & +-- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000010000000000000100000100000010000010000000000000100000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1), + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2), + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|UART1|ALT_INV_Add2~29_sumout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add2~25_sumout\, + combout => \myVirtualToplevel|UART1|Equal3~1_combout\); + +-- Location: MLABCELL_X13_Y5_N18 +\myVirtualToplevel|UART1|Equal3~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal3~2_combout\ = ( \myVirtualToplevel|UART1|Equal3~1_combout\ & ( \myVirtualToplevel|UART1|Add2~1_sumout\ & ( (\myVirtualToplevel|UART1|Equal3~0_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) & +-- (!\myVirtualToplevel|UART1|Add2~5_sumout\ $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7))))) ) ) ) # ( \myVirtualToplevel|UART1|Equal3~1_combout\ & ( !\myVirtualToplevel|UART1|Add2~1_sumout\ & ( (\myVirtualToplevel|UART1|Equal3~0_combout\ & +-- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART1|Add2~5_sumout\ $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010000000000010000000000000000000001000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_Equal3~0_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6), + datac => \myVirtualToplevel|UART1|ALT_INV_Add2~5_sumout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7), + datae => \myVirtualToplevel|UART1|ALT_INV_Equal3~1_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add2~1_sumout\, + combout => \myVirtualToplevel|UART1|Equal3~2_combout\); + +-- Location: LABCELL_X14_Y5_N27 +\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\ = ( \myVirtualToplevel|UART1|RX_INTR~0_combout\ & ( (!\myVirtualToplevel|UART1|Equal3~2_combout\ & (!\myVirtualToplevel|UART1|RX_ENABLE~q\ & !\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000000000000001100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal3~2_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\, + combout => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\); + +-- Location: FF_X13_Y5_N52 +\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~1_combout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0)); + +-- Location: MLABCELL_X13_Y5_N33 +\myVirtualToplevel|UART1|Add4~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add4~13_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~6\ )) +-- \myVirtualToplevel|UART1|Add4~14\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2), + cin => \myVirtualToplevel|UART1|Add4~6\, + sumout => \myVirtualToplevel|UART1|Add4~13_sumout\, + cout => \myVirtualToplevel|UART1|Add4~14\); + +-- Location: FF_X13_Y5_N34 +\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add4~13_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2)); + +-- Location: FF_X13_Y5_N37 +\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add4~9_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3)); + +-- Location: FF_X13_Y5_N40 +\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add4~1_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y5_N24 +\myVirtualToplevel|UART1|Equal2~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal2~1_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) & ( (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\ $ (\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4)))) ) +-- ) # ( !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\ $ (\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000001010101000000000101001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(4), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(3), + combout => \myVirtualToplevel|UART1|Equal2~1_combout\); + +-- Location: LABCELL_X16_Y6_N54 +\myVirtualToplevel|UART1|Equal2~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal2~4_combout\ = ( \myVirtualToplevel|UART1|Equal2~3_combout\ & ( (\myVirtualToplevel|UART1|Equal2~1_combout\ & (\myVirtualToplevel|UART1|Equal2~2_combout\ & \myVirtualToplevel|UART1|Equal2~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal2~1_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Equal2~2_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_Equal2~0_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Equal2~3_combout\, + combout => \myVirtualToplevel|UART1|Equal2~4_combout\); + +-- Location: LABCELL_X16_Y6_N15 +\myVirtualToplevel|UART1|RX_DATA[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ = ( !\myVirtualToplevel|UART1|RX_DATA_READY~q\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ & ((!\myVirtualToplevel|UART1|Equal2~4_combout\))) # (\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ & +-- (\myVirtualToplevel|UART1|RX_INTR~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110100010001110111010001000100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_Equal2~4_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~q\, + combout => \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\); + +-- Location: MLABCELL_X13_Y7_N54 +\myVirtualToplevel|UART1|RX_FIFO~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO~31_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.stop~q\ & ( \myVirtualToplevel|UART1|RXD_SYNC~q\ & ( (\myVirtualToplevel|UART1|RX_CLOCK~q\ & (\myVirtualToplevel|UART1|RX_RESET~q\ & (!\myVirtualToplevel|UART1|RX_ENABLE~q\ +-- & !\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000001000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK~q\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_RESET~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\, + combout => \myVirtualToplevel|UART1|RX_FIFO~31_combout\); + +-- Location: MLABCELL_X13_Y5_N15 +\myVirtualToplevel|UART1|Equal3~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal3~3_combout\ = ( \myVirtualToplevel|UART1|Add2~1_sumout\ & ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) ) ) # ( !\myVirtualToplevel|UART1|Add2~1_sumout\ & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111111110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6), + dataf => \myVirtualToplevel|UART1|ALT_INV_Add2~1_sumout\, + combout => \myVirtualToplevel|UART1|Equal3~3_combout\); + +-- Location: MLABCELL_X13_Y5_N6 +\myVirtualToplevel|UART1|RX_FIFO~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO~32_combout\ = ( \myVirtualToplevel|UART1|Equal3~1_combout\ & ( \myVirtualToplevel|UART1|Add2~5_sumout\ & ( (\myVirtualToplevel|UART1|RX_FIFO~31_combout\ & ((!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7)) # +-- ((!\myVirtualToplevel|UART1|Equal3~0_combout\) # (\myVirtualToplevel|UART1|Equal3~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|UART1|Equal3~1_combout\ & ( \myVirtualToplevel|UART1|Add2~5_sumout\ & ( \myVirtualToplevel|UART1|RX_FIFO~31_combout\ ) ) ) # ( +-- \myVirtualToplevel|UART1|Equal3~1_combout\ & ( !\myVirtualToplevel|UART1|Add2~5_sumout\ & ( (\myVirtualToplevel|UART1|RX_FIFO~31_combout\ & (((!\myVirtualToplevel|UART1|Equal3~0_combout\) # (\myVirtualToplevel|UART1|Equal3~3_combout\)) # +-- (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7)))) ) ) ) # ( !\myVirtualToplevel|UART1|Equal3~1_combout\ & ( !\myVirtualToplevel|UART1|Add2~5_sumout\ & ( \myVirtualToplevel|UART1|RX_FIFO~31_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010100010101010101010101010101010101010001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~31_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7), + datac => \myVirtualToplevel|UART1|ALT_INV_Equal3~0_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_Equal3~3_combout\, + datae => \myVirtualToplevel|UART1|ALT_INV_Equal3~1_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add2~5_sumout\, + combout => \myVirtualToplevel|UART1|RX_FIFO~32_combout\); + +-- Location: FF_X14_Y6_N2 +\myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Selector8~0_combout\, + ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\); + +-- Location: FF_X14_Y6_N4 +\myVirtualToplevel|UART1|RX_BUFFER[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Selector7~0_combout\, + ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_BUFFER[5]~DUPLICATE_q\); + +-- Location: FF_X14_Y6_N10 +\myVirtualToplevel|UART1|RX_BUFFER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Selector5~0_combout\, + ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_BUFFER\(7)); + +-- Location: M10K_X11_Y6_N0 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + logical_ram_name => "zpu_soc:myVirtualToplevel|uart:UART1|altsyncram:RX_FIFO_rtl_0|altsyncram_1jo1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 8, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 40, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 255, + port_a_logical_ram_depth => 256, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 8, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 40, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 255, + port_b_logical_ram_depth => 256, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|UART1|RX_FIFO~32_combout\, + portbre => VCC, + portbaddrstall => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X14_Y6_N27 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]~feeder_combout\ = \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[7]~DUPLICATE_q\, + combout => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]~feeder_combout\); + +-- Location: FF_X14_Y6_N28 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(23)); + +-- Location: FF_X16_Y5_N46 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(15)); + +-- Location: FF_X16_Y5_N20 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(13)); + +-- Location: FF_X16_Y5_N17 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(11)); + +-- Location: FF_X16_Y5_N5 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|Add3~21_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(14)); + +-- Location: FF_X16_Y5_N53 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|Add3~25_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(12)); + +-- Location: LABCELL_X16_Y5_N3 +\myVirtualToplevel|UART1|RX_FIFO~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO~26_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(12) & ( (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(11) & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(13) $ +-- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(14)))) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(12) & ( (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(11) & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(13) $ +-- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(14)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000001010000101000000101000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(13), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(11), + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(14), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(12), + combout => \myVirtualToplevel|UART1|RX_FIFO~26_combout\); + +-- Location: FF_X16_Y5_N2 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|Add3~29_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(16)); + +-- Location: FF_X14_Y5_N7 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(9)); + +-- Location: FF_X13_Y5_N5 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_FIFO~32_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(0)); + +-- Location: FF_X13_Y5_N28 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|Add3~5_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(2)); + +-- Location: FF_X13_Y5_N23 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|Add3~9_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(4)); + +-- Location: FF_X13_Y5_N2 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(3)); + +-- Location: FF_X13_Y5_N11 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(1)); + +-- Location: MLABCELL_X13_Y5_N0 +\myVirtualToplevel|UART1|RX_FIFO~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO~27_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(3) & ( \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(1) & ( (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(0) & +-- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(2) & \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(4))) ) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(3) & ( \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(1) & ( +-- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(0) & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(2) & !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(4))) ) ) ) # ( \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(3) & ( +-- !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(1) & ( (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(0) & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(2) & \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(4))) ) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(3) & ( !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(1) & ( (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(0) & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(2) & +-- !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(4))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001000000000001000000010000010000000100000000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(0), + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(2), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(4), + datae => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(3), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(1), + combout => \myVirtualToplevel|UART1|RX_FIFO~27_combout\); + +-- Location: FF_X14_Y5_N59 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|Add3~1_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(10)); + +-- Location: FF_X16_Y5_N59 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(7)); + +-- Location: FF_X16_Y5_N28 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|Add3~17_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(6)); + +-- Location: FF_X16_Y5_N11 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|Add3~13_sumout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(8)); + +-- Location: FF_X16_Y5_N14 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(5)); + +-- Location: LABCELL_X16_Y5_N9 +\myVirtualToplevel|UART1|RX_FIFO~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO~28_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(5) & ( (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(6) & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(7) $ +-- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(8)))) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(5) & ( (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(6) & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(7) $ +-- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(8)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000110000110000000011000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(7), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(6), + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(8), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(5), + combout => \myVirtualToplevel|UART1|RX_FIFO~28_combout\); + +-- Location: LABCELL_X14_Y5_N57 +\myVirtualToplevel|UART1|RX_FIFO~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO~29_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO~28_combout\ & ( (\myVirtualToplevel|UART1|RX_FIFO~27_combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(9) $ (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(10)))) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(9), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~27_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(10), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~28_combout\, + combout => \myVirtualToplevel|UART1|RX_FIFO~29_combout\); + +-- Location: LABCELL_X16_Y5_N0 +\myVirtualToplevel|UART1|RX_FIFO~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO~30_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO~29_combout\ & ( (\myVirtualToplevel|UART1|RX_FIFO~26_combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(15) $ (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(16)))) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(15), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~26_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(16), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~29_combout\, + combout => \myVirtualToplevel|UART1|RX_FIFO~30_combout\); + +-- Location: FF_X16_Y6_N43 +\myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_DATA_READY~1_combout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\); + +-- Location: LABCELL_X16_Y6_N3 +\myVirtualToplevel|UART1|RX_DATA[0]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ = ( \myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ & ( !\myVirtualToplevel|UART1|RX_FIFO~30_combout\ ) ) # ( !\myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|UART1|RX_FIFO~30_combout\ & ((!\myVirtualToplevel|UART1|RX_INTR~0_combout\) # (!\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000010100000111100001010000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~30_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~DUPLICATE_q\, + combout => \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\); + +-- Location: MLABCELL_X13_Y5_N12 +\myVirtualToplevel|UART1|RX_FIFO~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO~33_combout\ = ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & +-- !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2), + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(4), + combout => \myVirtualToplevel|UART1|RX_FIFO~33_combout\); + +-- Location: MLABCELL_X13_Y6_N48 +\myVirtualToplevel|UART1|RX_FIFO~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO~34_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO~32_combout\ & ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & (\myVirtualToplevel|UART1|RX_FIFO~33_combout\ & +-- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) & !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0), + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~33_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7), + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1), + datae => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~32_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6), + combout => \myVirtualToplevel|UART1|RX_FIFO~34_combout\); + +-- Location: FF_X14_Y6_N13 +\myVirtualToplevel|UART1|RX_FIFO~24\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO~24_q\); + +-- Location: LABCELL_X16_Y6_N48 +\myVirtualToplevel|UART1|RX_FIFO~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO~35_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\ ) # ( !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\ & ( \myVirtualToplevel|UART1|RX_FIFO~17_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~17_q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\, + combout => \myVirtualToplevel|UART1|RX_FIFO~35_combout\); + +-- Location: FF_X16_Y6_N49 +\myVirtualToplevel|UART1|RX_FIFO~17\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_FIFO~35_combout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO~17_q\); + +-- Location: LABCELL_X16_Y6_N51 +\myVirtualToplevel|UART1|RX_DATA[0]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ = ( \myVirtualToplevel|UART1|RX_INTR~0_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ & (((!\myVirtualToplevel|UART1|RX_FIFO~17_q\ & !\myVirtualToplevel|UART1|RX_FIFO~30_combout\)) # +-- (\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\))) # (\myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_FIFO~17_q\ & (!\myVirtualToplevel|UART1|RX_FIFO~30_combout\))) ) ) # ( !\myVirtualToplevel|UART1|RX_INTR~0_combout\ & ( +-- (!\myVirtualToplevel|UART1|RX_FIFO~17_q\ & !\myVirtualToplevel|UART1|RX_FIFO~30_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000110000001100000011000000111010101100000011101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~DUPLICATE_q\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~17_q\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~30_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\); + +-- Location: LABCELL_X14_Y6_N12 +\myVirtualToplevel|UART1|RX_DATA~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA~8_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\ & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) # (\myVirtualToplevel|UART1|RX_FIFO~24_q\) ) ) ) # +-- ( !\myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\ & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & \myVirtualToplevel|UART1|RX_FIFO~24_q\) ) ) ) # ( +-- \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(23)))) # +-- (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a6\)) ) ) ) # ( !\myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( +-- (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(23)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a6\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(23), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~24_q\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA~8_combout\); + +-- Location: MLABCELL_X13_Y6_N36 +\myVirtualToplevel|UART1|RX_DATA[6]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA[6]~9_combout\ = ( \myVirtualToplevel|UART1|RX_DATA~8_combout\ & ( ((\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\)) # (\myVirtualToplevel|UART1|RX_DATA\(6)) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_DATA~8_combout\ & ( (\myVirtualToplevel|UART1|RX_DATA\(6) & ((!\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\) # (!\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(6), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA~8_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA[6]~9_combout\); + +-- Location: FF_X13_Y6_N37 +\myVirtualToplevel|UART1|RX_DATA[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_DATA[6]~9_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_DATA\(6)); + +-- Location: LABCELL_X14_Y10_N39 +\myVirtualToplevel|IO_DATA_READ~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~47_combout\ = ( \myVirtualToplevel|UART1|RX_DATA\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (!\myVirtualToplevel|UART1|RX_ENABLE~q\))) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_DATA\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & !\myVirtualToplevel|UART1|RX_ENABLE~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000000000000010100000000010101010101000001010101010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(6), + combout => \myVirtualToplevel|IO_DATA_READ~47_combout\); + +-- Location: LABCELL_X12_Y9_N0 +\myVirtualToplevel|UART0|RX_ENABLE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_ENABLE~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + combout => \myVirtualToplevel|UART0|RX_ENABLE~0_combout\); + +-- Location: FF_X12_Y9_N2 +\myVirtualToplevel|UART0|RX_ENABLE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_ENABLE~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_ENABLE~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_ENABLE~q\); + +-- Location: LABCELL_X12_Y9_N54 +\myVirtualToplevel|UART0|RX_RESET~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_RESET~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( \myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( \myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( !\myVirtualToplevel|UART0_CS~combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( !\myVirtualToplevel|UART0_CS~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111110101111101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\, + combout => \myVirtualToplevel|UART0|RX_RESET~0_combout\); + +-- Location: FF_X12_Y9_N56 +\myVirtualToplevel|UART0|RX_RESET\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_RESET~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_RESET~q\); + +-- Location: LABCELL_X10_Y6_N15 +\myVirtualToplevel|UART0|RX_DATA[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ = ( !\myVirtualToplevel|UART0|RX_ENABLE~q\ & ( \myVirtualToplevel|UART0|RX_RESET~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_RESET~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + combout => \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\); + +-- Location: FF_X9_Y5_N29 +\myVirtualToplevel|UART0|RXD_SYNC2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \UART_RX_0~input_o\, + sload => VCC, + ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RXD_SYNC2~q\); + +-- Location: FF_X9_Y5_N11 +\myVirtualToplevel|UART0|RXD_SYNC\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RXD_SYNC2~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RXD_SYNC~q\); + +-- Location: LABCELL_X10_Y4_N51 +\myVirtualToplevel|UART0|Selector6~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Selector6~0_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(7) & ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(7), + combout => \myVirtualToplevel|UART0|Selector6~0_combout\); + +-- Location: LABCELL_X7_Y7_N30 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]~5_combout\); + +-- Location: LABCELL_X12_Y9_N39 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\ = ( \myVirtualToplevel|UART0_CS~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000001000000010000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\, + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\); + +-- Location: FF_X7_Y7_N31 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(0)); + +-- Location: LABCELL_X7_Y7_N12 +\myVirtualToplevel|UART0|RX_COUNTER~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~15_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(0) & ( (!\myVirtualToplevel|UART0|Equal1~4_combout\ & !\myVirtualToplevel|UART0|RX_COUNTER\(0)) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(0) & ( +-- (!\myVirtualToplevel|UART0|RX_COUNTER\(0)) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100110011111111110011001111001100000000001100110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(0), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(0), + combout => \myVirtualToplevel|UART0|RX_COUNTER~15_combout\); + +-- Location: FF_X7_Y7_N35 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(1)); + +-- Location: MLABCELL_X9_Y5_N33 +\myVirtualToplevel|UART0|RX_COUNTER[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\ = ( \myVirtualToplevel|UART0|RXD_SYNC~q\ & ( (!\myVirtualToplevel|UART0|RX_ENABLE~q\ & \myVirtualToplevel|UART0|RX_STATE.idle~q\) ) ) # ( !\myVirtualToplevel|UART0|RXD_SYNC~q\ & ( +-- !\myVirtualToplevel|UART0|RX_ENABLE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101000001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\, + combout => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\); + +-- Location: FF_X7_Y7_N13 +\myVirtualToplevel|UART0|RX_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~15_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(1), + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(0)); + +-- Location: MLABCELL_X9_Y7_N0 +\myVirtualToplevel|UART0|Add1~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~54\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(0), + cin => GND, + cout => \myVirtualToplevel|UART0|Add1~54\); + +-- Location: MLABCELL_X9_Y7_N3 +\myVirtualToplevel|UART0|Add1~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~17_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~54\ )) +-- \myVirtualToplevel|UART0|Add1~18\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(1), + cin => \myVirtualToplevel|UART0|Add1~54\, + sumout => \myVirtualToplevel|UART0|Add1~17_sumout\, + cout => \myVirtualToplevel|UART0|Add1~18\); + +-- Location: LABCELL_X7_Y7_N15 +\myVirtualToplevel|UART0|RX_COUNTER~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~6_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(1) & ( (\myVirtualToplevel|UART0|Equal1~4_combout\) # (\myVirtualToplevel|UART0|Add1~17_sumout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(1) & ( +-- (\myVirtualToplevel|UART0|Add1~17_sumout\ & !\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010001110111011101110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Add1~17_sumout\, + datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(1), + combout => \myVirtualToplevel|UART0|RX_COUNTER~6_combout\); + +-- Location: LABCELL_X7_Y7_N27 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~1_combout\); + +-- Location: FF_X7_Y7_N28 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(2)); + +-- Location: LABCELL_X7_Y7_N42 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~_wirecell_combout\ = !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(2) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(2), + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~_wirecell_combout\); + +-- Location: FF_X7_Y7_N16 +\myVirtualToplevel|UART0|RX_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~6_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~_wirecell_combout\, + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(1)); + +-- Location: MLABCELL_X9_Y7_N6 +\myVirtualToplevel|UART0|Add1~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~21_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~18\ )) +-- \myVirtualToplevel|UART0|Add1~22\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(2), + cin => \myVirtualToplevel|UART0|Add1~18\, + sumout => \myVirtualToplevel|UART0|Add1~21_sumout\, + cout => \myVirtualToplevel|UART0|Add1~22\); + +-- Location: LABCELL_X7_Y7_N45 +\myVirtualToplevel|UART0|RX_COUNTER~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~7_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(2) & ( (\myVirtualToplevel|UART0|Add1~21_sumout\ & !\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(2) & ( +-- (\myVirtualToplevel|UART0|Equal1~4_combout\) # (\myVirtualToplevel|UART0|Add1~21_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111101011111010111110101111101010000010100000101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Add1~21_sumout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(2), + combout => \myVirtualToplevel|UART0|RX_COUNTER~7_combout\); + +-- Location: LABCELL_X7_Y7_N54 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~2_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~2_combout\); + +-- Location: FF_X7_Y7_N55 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(3)); + +-- Location: LABCELL_X7_Y7_N3 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~_wirecell_combout\ = !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(3) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(3), + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~_wirecell_combout\); + +-- Location: FF_X7_Y7_N46 +\myVirtualToplevel|UART0|RX_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~7_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~_wirecell_combout\, + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(2)); + +-- Location: MLABCELL_X9_Y7_N9 +\myVirtualToplevel|UART0|Add1~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~25_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~22\ )) +-- \myVirtualToplevel|UART0|Add1~26\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(3), + cin => \myVirtualToplevel|UART0|Add1~22\, + sumout => \myVirtualToplevel|UART0|Add1~25_sumout\, + cout => \myVirtualToplevel|UART0|Add1~26\); + +-- Location: LABCELL_X7_Y7_N0 +\myVirtualToplevel|UART0|RX_COUNTER~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~8_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(3) & ( (\myVirtualToplevel|UART0|Add1~25_sumout\ & !\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(3) & ( +-- (\myVirtualToplevel|UART0|Equal1~4_combout\) # (\myVirtualToplevel|UART0|Add1~25_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111111111000011111111111100001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_Add1~25_sumout\, + datad => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(3), + combout => \myVirtualToplevel|UART0|RX_COUNTER~8_combout\); + +-- Location: LABCELL_X7_Y7_N57 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~3_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~3_combout\); + +-- Location: FF_X7_Y7_N59 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(4)); + +-- Location: LABCELL_X7_Y7_N9 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~_wirecell_combout\ = !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(4) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(4), + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~_wirecell_combout\); + +-- Location: FF_X7_Y7_N1 +\myVirtualToplevel|UART0|RX_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~8_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~_wirecell_combout\, + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(3)); + +-- Location: MLABCELL_X9_Y7_N12 +\myVirtualToplevel|UART0|Add1~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~29_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~26\ )) +-- \myVirtualToplevel|UART0|Add1~30\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(4), + cin => \myVirtualToplevel|UART0|Add1~26\, + sumout => \myVirtualToplevel|UART0|Add1~29_sumout\, + cout => \myVirtualToplevel|UART0|Add1~30\); + +-- Location: LABCELL_X7_Y7_N6 +\myVirtualToplevel|UART0|RX_COUNTER~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~9_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(4) & ( (\myVirtualToplevel|UART0|Add1~29_sumout\ & !\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(4) & ( +-- (\myVirtualToplevel|UART0|Equal1~4_combout\) # (\myVirtualToplevel|UART0|Add1~29_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111111111000011111111111100001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_Add1~29_sumout\, + datad => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(4), + combout => \myVirtualToplevel|UART0|RX_COUNTER~9_combout\); + +-- Location: LABCELL_X10_Y7_N24 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~4_combout\); + +-- Location: FF_X10_Y7_N25 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(5)); + +-- Location: LABCELL_X7_Y7_N24 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~_wirecell_combout\ = ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(5), + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~_wirecell_combout\); + +-- Location: FF_X7_Y7_N8 +\myVirtualToplevel|UART0|RX_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~9_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~_wirecell_combout\, + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(4)); + +-- Location: MLABCELL_X9_Y7_N48 +\myVirtualToplevel|UART0|Equal1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal1~1_combout\ = ( !\myVirtualToplevel|UART0|RX_COUNTER\(1) & ( (!\myVirtualToplevel|UART0|RX_COUNTER\(3) & (!\myVirtualToplevel|UART0|RX_COUNTER\(4) & !\myVirtualToplevel|UART0|RX_COUNTER\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(3), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(4), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(2), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(1), + combout => \myVirtualToplevel|UART0|Equal1~1_combout\); + +-- Location: FF_X10_Y7_N11 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(9)); + +-- Location: FF_X10_Y7_N14 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(7)); + +-- Location: MLABCELL_X9_Y7_N15 +\myVirtualToplevel|UART0|Add1~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~33_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~30\ )) +-- \myVirtualToplevel|UART0|Add1~34\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(5), + cin => \myVirtualToplevel|UART0|Add1~30\, + sumout => \myVirtualToplevel|UART0|Add1~33_sumout\, + cout => \myVirtualToplevel|UART0|Add1~34\); + +-- Location: LABCELL_X10_Y7_N21 +\myVirtualToplevel|UART0|RX_COUNTER~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~10_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(5) & ( (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~33_sumout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(5) & ( +-- (\myVirtualToplevel|UART0|Add1~33_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111001111110011111100001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Add1~33_sumout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(5), + combout => \myVirtualToplevel|UART0|RX_COUNTER~10_combout\); + +-- Location: FF_X10_Y7_N16 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(6)); + +-- Location: FF_X10_Y7_N23 +\myVirtualToplevel|UART0|RX_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~10_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(6), + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(5)); + +-- Location: MLABCELL_X9_Y7_N18 +\myVirtualToplevel|UART0|Add1~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~37_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~34\ )) +-- \myVirtualToplevel|UART0|Add1~38\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(6), + cin => \myVirtualToplevel|UART0|Add1~34\, + sumout => \myVirtualToplevel|UART0|Add1~37_sumout\, + cout => \myVirtualToplevel|UART0|Add1~38\); + +-- Location: LABCELL_X10_Y7_N18 +\myVirtualToplevel|UART0|RX_COUNTER~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~11_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(6) & ( (\myVirtualToplevel|UART0|Add1~37_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(6) & ( +-- (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~37_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Add1~37_sumout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(6), + combout => \myVirtualToplevel|UART0|RX_COUNTER~11_combout\); + +-- Location: FF_X10_Y7_N20 +\myVirtualToplevel|UART0|RX_COUNTER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~11_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(7), + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(6)); + +-- Location: MLABCELL_X9_Y7_N21 +\myVirtualToplevel|UART0|Add1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~1_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~38\ )) +-- \myVirtualToplevel|UART0|Add1~2\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|UART0|Add1~38\, + sumout => \myVirtualToplevel|UART0|Add1~1_sumout\, + cout => \myVirtualToplevel|UART0|Add1~2\); + +-- Location: LABCELL_X10_Y7_N39 +\myVirtualToplevel|UART0|RX_COUNTER~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~2_combout\ = (!\myVirtualToplevel|UART0|Equal1~4_combout\ & ((\myVirtualToplevel|UART0|Add1~1_sumout\))) # (\myVirtualToplevel|UART0|Equal1~4_combout\ & (\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(7))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(7), + datad => \myVirtualToplevel|UART0|ALT_INV_Add1~1_sumout\, + combout => \myVirtualToplevel|UART0|RX_COUNTER~2_combout\); + +-- Location: FF_X10_Y7_N7 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(8)); + +-- Location: FF_X10_Y7_N40 +\myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~2_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(8), + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE_q\); + +-- Location: MLABCELL_X9_Y7_N24 +\myVirtualToplevel|UART0|Add1~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~5_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~2\ )) +-- \myVirtualToplevel|UART0|Add1~6\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(8), + cin => \myVirtualToplevel|UART0|Add1~2\, + sumout => \myVirtualToplevel|UART0|Add1~5_sumout\, + cout => \myVirtualToplevel|UART0|Add1~6\); + +-- Location: LABCELL_X10_Y7_N36 +\myVirtualToplevel|UART0|RX_COUNTER~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~3_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(8) & ( (\myVirtualToplevel|UART0|Add1~5_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(8) & ( +-- (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~5_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Add1~5_sumout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(8), + combout => \myVirtualToplevel|UART0|RX_COUNTER~3_combout\); + +-- Location: FF_X10_Y7_N38 +\myVirtualToplevel|UART0|RX_COUNTER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~3_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(9), + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(8)); + +-- Location: MLABCELL_X9_Y7_N27 +\myVirtualToplevel|UART0|Add1~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~9_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~6\ )) +-- \myVirtualToplevel|UART0|Add1~10\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(9), + cin => \myVirtualToplevel|UART0|Add1~6\, + sumout => \myVirtualToplevel|UART0|Add1~9_sumout\, + cout => \myVirtualToplevel|UART0|Add1~10\); + +-- Location: LABCELL_X10_Y7_N54 +\myVirtualToplevel|UART0|RX_COUNTER~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~4_combout\ = (!\myVirtualToplevel|UART0|Equal1~4_combout\ & ((\myVirtualToplevel|UART0|Add1~9_sumout\))) # (\myVirtualToplevel|UART0|Equal1~4_combout\ & (\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(9))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(9), + datac => \myVirtualToplevel|UART0|ALT_INV_Add1~9_sumout\, + datad => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + combout => \myVirtualToplevel|UART0|RX_COUNTER~4_combout\); + +-- Location: LABCELL_X10_Y7_N27 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~0_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(10), + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~0_combout\); + +-- Location: FF_X10_Y7_N28 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(10)); + +-- Location: LABCELL_X10_Y7_N9 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~_wirecell_combout\ = !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(10) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(10), + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~_wirecell_combout\); + +-- Location: FF_X10_Y7_N56 +\myVirtualToplevel|UART0|RX_COUNTER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~4_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~_wirecell_combout\, + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(9)); + +-- Location: MLABCELL_X9_Y7_N30 +\myVirtualToplevel|UART0|Add1~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~13_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~10\ )) +-- \myVirtualToplevel|UART0|Add1~14\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[10]~DUPLICATE_q\, + cin => \myVirtualToplevel|UART0|Add1~10\, + sumout => \myVirtualToplevel|UART0|Add1~13_sumout\, + cout => \myVirtualToplevel|UART0|Add1~14\); + +-- Location: LABCELL_X10_Y7_N3 +\myVirtualToplevel|UART0|RX_COUNTER~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~5_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(10) & ( (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~13_sumout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(10) & ( +-- (\myVirtualToplevel|UART0|Add1~13_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111001111110011111100001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Add1~13_sumout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(10), + combout => \myVirtualToplevel|UART0|RX_COUNTER~5_combout\); + +-- Location: LABCELL_X10_Y7_N42 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(11), + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]~feeder_combout\); + +-- Location: FF_X10_Y7_N43 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(11)); + +-- Location: FF_X10_Y7_N4 +\myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~5_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(11), + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE_q\); + +-- Location: MLABCELL_X9_Y7_N33 +\myVirtualToplevel|UART0|Add1~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~41_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~14\ )) +-- \myVirtualToplevel|UART0|Add1~42\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(11), + cin => \myVirtualToplevel|UART0|Add1~14\, + sumout => \myVirtualToplevel|UART0|Add1~41_sumout\, + cout => \myVirtualToplevel|UART0|Add1~42\); + +-- Location: LABCELL_X10_Y7_N0 +\myVirtualToplevel|UART0|RX_COUNTER~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~12_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(11) & ( (\myVirtualToplevel|UART0|Add1~41_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(11) & ( +-- (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~41_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Add1~41_sumout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(11), + combout => \myVirtualToplevel|UART0|RX_COUNTER~12_combout\); + +-- Location: LABCELL_X10_Y7_N45 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(12), + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder_combout\); + +-- Location: FF_X10_Y7_N47 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~DUPLICATE_q\); + +-- Location: FF_X10_Y7_N2 +\myVirtualToplevel|UART0|RX_COUNTER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~12_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~DUPLICATE_q\, + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(11)); + +-- Location: MLABCELL_X9_Y7_N36 +\myVirtualToplevel|UART0|Add1~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~45_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~42\ )) +-- \myVirtualToplevel|UART0|Add1~46\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(12), + cin => \myVirtualToplevel|UART0|Add1~42\, + sumout => \myVirtualToplevel|UART0|Add1~45_sumout\, + cout => \myVirtualToplevel|UART0|Add1~46\); + +-- Location: FF_X10_Y7_N46 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(12)); + +-- Location: LABCELL_X10_Y7_N51 +\myVirtualToplevel|UART0|RX_COUNTER~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~13_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(12) & ( (\myVirtualToplevel|UART0|Equal1~4_combout\) # (\myVirtualToplevel|UART0|Add1~45_sumout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(12) & ( +-- (\myVirtualToplevel|UART0|Add1~45_sumout\ & !\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_Add1~45_sumout\, + datad => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(12), + combout => \myVirtualToplevel|UART0|RX_COUNTER~13_combout\); + +-- Location: FF_X7_Y7_N49 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13]~DUPLICATE_q\); + +-- Location: FF_X10_Y7_N53 +\myVirtualToplevel|UART0|RX_COUNTER[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~13_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13]~DUPLICATE_q\, + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(12)); + +-- Location: MLABCELL_X9_Y7_N39 +\myVirtualToplevel|UART0|Add1~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~57_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~46\ )) +-- \myVirtualToplevel|UART0|Add1~58\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(13), + cin => \myVirtualToplevel|UART0|Add1~46\, + sumout => \myVirtualToplevel|UART0|Add1~57_sumout\, + cout => \myVirtualToplevel|UART0|Add1~58\); + +-- Location: FF_X7_Y7_N50 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(13)); + +-- Location: LABCELL_X7_Y7_N36 +\myVirtualToplevel|UART0|RX_COUNTER~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~16_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(13) & ( (\myVirtualToplevel|UART0|Add1~57_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(13) & ( +-- (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~57_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_Add1~57_sumout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(13), + combout => \myVirtualToplevel|UART0|RX_COUNTER~16_combout\); + +-- Location: LABCELL_X7_Y7_N18 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[14]~DUPLICATE_q\, + combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]~feeder_combout\); + +-- Location: FF_X7_Y7_N19 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(14)); + +-- Location: FF_X7_Y7_N37 +\myVirtualToplevel|UART0|RX_COUNTER[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~16_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(14), + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(13)); + +-- Location: MLABCELL_X9_Y7_N42 +\myVirtualToplevel|UART0|Add1~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~61_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(14) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~58\ )) +-- \myVirtualToplevel|UART0|Add1~62\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(14) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(14), + cin => \myVirtualToplevel|UART0|Add1~58\, + sumout => \myVirtualToplevel|UART0|Add1~61_sumout\, + cout => \myVirtualToplevel|UART0|Add1~62\); + +-- Location: LABCELL_X7_Y7_N39 +\myVirtualToplevel|UART0|RX_COUNTER~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~17_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(14) & ( (\myVirtualToplevel|UART0|Add1~61_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(14) & ( +-- (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~61_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Add1~61_sumout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(14), + combout => \myVirtualToplevel|UART0|RX_COUNTER~17_combout\); + +-- Location: FF_X7_Y7_N52 +\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15)); + +-- Location: FF_X7_Y7_N40 +\myVirtualToplevel|UART0|RX_COUNTER[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~17_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15), + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(14)); + +-- Location: MLABCELL_X9_Y7_N45 +\myVirtualToplevel|UART0|Add1~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add1~49_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(15) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(15), + cin => \myVirtualToplevel|UART0|Add1~62\, + sumout => \myVirtualToplevel|UART0|Add1~49_sumout\); + +-- Location: MLABCELL_X9_Y5_N6 +\myVirtualToplevel|UART0|RX_COUNTER~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_COUNTER~14_combout\ = ( \myVirtualToplevel|UART0|RX_COUNTER\(15) & ( \myVirtualToplevel|UART0|RXD_SYNC~q\ & ( (!\myVirtualToplevel|UART0|RX_STATE.idle~q\) # ((!\myVirtualToplevel|UART0|Equal1~4_combout\ & +-- (\myVirtualToplevel|UART0|Add1~49_sumout\)) # (\myVirtualToplevel|UART0|Equal1~4_combout\ & ((\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15))))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_COUNTER\(15) & ( \myVirtualToplevel|UART0|RXD_SYNC~q\ & ( +-- (\myVirtualToplevel|UART0|RX_STATE.idle~q\ & ((!\myVirtualToplevel|UART0|Equal1~4_combout\ & (\myVirtualToplevel|UART0|Add1~49_sumout\)) # (\myVirtualToplevel|UART0|Equal1~4_combout\ & ((\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15)))))) ) ) ) # ( +-- \myVirtualToplevel|UART0|RX_COUNTER\(15) & ( !\myVirtualToplevel|UART0|RXD_SYNC~q\ & ( (\myVirtualToplevel|UART0|RX_STATE.idle~q\ & ((!\myVirtualToplevel|UART0|Equal1~4_combout\ & (\myVirtualToplevel|UART0|Add1~49_sumout\)) # +-- (\myVirtualToplevel|UART0|Equal1~4_combout\ & ((\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15)))))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_COUNTER\(15) & ( !\myVirtualToplevel|UART0|RXD_SYNC~q\ & ( (\myVirtualToplevel|UART0|RX_STATE.idle~q\ & +-- ((!\myVirtualToplevel|UART0|Equal1~4_combout\ & (\myVirtualToplevel|UART0|Add1~49_sumout\)) # (\myVirtualToplevel|UART0|Equal1~4_combout\ & ((\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111000000000100011100000000010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Add1~49_sumout\, + datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(15), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + datae => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(15), + dataf => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\, + combout => \myVirtualToplevel|UART0|RX_COUNTER~14_combout\); + +-- Location: FF_X9_Y5_N7 +\myVirtualToplevel|UART0|RX_COUNTER[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~14_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(15)); + +-- Location: MLABCELL_X9_Y7_N57 +\myVirtualToplevel|UART0|Equal1~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal1~3_combout\ = ( !\myVirtualToplevel|UART0|RX_COUNTER\(14) & ( (!\myVirtualToplevel|UART0|RX_COUNTER\(0) & (!\myVirtualToplevel|UART0|RX_COUNTER\(15) & !\myVirtualToplevel|UART0|RX_COUNTER\(13))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(0), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(15), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(13), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(14), + combout => \myVirtualToplevel|UART0|Equal1~3_combout\); + +-- Location: MLABCELL_X9_Y7_N54 +\myVirtualToplevel|UART0|Equal1~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal1~2_combout\ = ( !\myVirtualToplevel|UART0|RX_COUNTER\(12) & ( (!\myVirtualToplevel|UART0|RX_COUNTER\(6) & (!\myVirtualToplevel|UART0|RX_COUNTER\(11) & !\myVirtualToplevel|UART0|RX_COUNTER\(5))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(6), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(11), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(5), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(12), + combout => \myVirtualToplevel|UART0|Equal1~2_combout\); + +-- Location: FF_X10_Y7_N41 +\myVirtualToplevel|UART0|RX_COUNTER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~2_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(8), + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(7)); + +-- Location: FF_X10_Y7_N5 +\myVirtualToplevel|UART0|RX_COUNTER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_COUNTER~5_combout\, + asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(11), + sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_COUNTER\(10)); + +-- Location: LABCELL_X10_Y7_N48 +\myVirtualToplevel|UART0|Equal1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal1~0_combout\ = (!\myVirtualToplevel|UART0|RX_COUNTER\(9) & (!\myVirtualToplevel|UART0|RX_COUNTER\(7) & (!\myVirtualToplevel|UART0|RX_COUNTER\(8) & !\myVirtualToplevel|UART0|RX_COUNTER\(10)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000100000000000000010000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(9), + datab => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(7), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(8), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(10), + combout => \myVirtualToplevel|UART0|Equal1~0_combout\); + +-- Location: MLABCELL_X9_Y7_N51 +\myVirtualToplevel|UART0|Equal1~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal1~4_combout\ = ( \myVirtualToplevel|UART0|Equal1~0_combout\ & ( (\myVirtualToplevel|UART0|Equal1~1_combout\ & (\myVirtualToplevel|UART0|Equal1~3_combout\ & \myVirtualToplevel|UART0|Equal1~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Equal1~1_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Equal1~3_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_Equal1~2_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_Equal1~0_combout\, + combout => \myVirtualToplevel|UART0|Equal1~4_combout\); + +-- Location: MLABCELL_X9_Y5_N30 +\myVirtualToplevel|UART0|RX_CLOCK~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_CLOCK~0_combout\ = (\myVirtualToplevel|UART0|RX_STATE.idle~q\ & \myVirtualToplevel|UART0|Equal1~4_combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\, + combout => \myVirtualToplevel|UART0|RX_CLOCK~0_combout\); + +-- Location: FF_X9_Y5_N32 +\myVirtualToplevel|UART0|RX_CLOCK\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_CLOCK~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK~q\); + +-- Location: MLABCELL_X9_Y5_N15 +\myVirtualToplevel|UART0|RX_BUFFER[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK~q\ & ( (\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|RX_STATE.start~q\ & !\myVirtualToplevel|UART0|RXD_SYNC~q\)) # +-- (\myVirtualToplevel|UART0|RX_STATE.bits~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100000011110000010000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.start~q\, + datab => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~q\, + combout => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\); + +-- Location: FF_X10_Y4_N53 +\myVirtualToplevel|UART0|RX_BUFFER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Selector6~0_combout\, + ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_BUFFER\(6)); + +-- Location: LABCELL_X10_Y4_N48 +\myVirtualToplevel|UART0|Selector7~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Selector7~0_combout\ = (\myVirtualToplevel|UART0|RX_STATE.bits~q\ & \myVirtualToplevel|UART0|RX_BUFFER\(6)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(6), + combout => \myVirtualToplevel|UART0|Selector7~0_combout\); + +-- Location: FF_X10_Y4_N50 +\myVirtualToplevel|UART0|RX_BUFFER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Selector7~0_combout\, + ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_BUFFER\(5)); + +-- Location: LABCELL_X10_Y4_N6 +\myVirtualToplevel|UART0|Selector8~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Selector8~0_combout\ = (\myVirtualToplevel|UART0|RX_STATE.bits~q\ & \myVirtualToplevel|UART0|RX_BUFFER\(5)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(5), + combout => \myVirtualToplevel|UART0|Selector8~0_combout\); + +-- Location: FF_X10_Y4_N8 +\myVirtualToplevel|UART0|RX_BUFFER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Selector8~0_combout\, + ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_BUFFER\(4)); + +-- Location: LABCELL_X10_Y4_N9 +\myVirtualToplevel|UART0|Selector9~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Selector9~0_combout\ = (\myVirtualToplevel|UART0|RX_STATE.bits~q\ & \myVirtualToplevel|UART0|RX_BUFFER\(4)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(4), + combout => \myVirtualToplevel|UART0|Selector9~0_combout\); + +-- Location: FF_X10_Y4_N10 +\myVirtualToplevel|UART0|RX_BUFFER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Selector9~0_combout\, + ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_BUFFER\(3)); + +-- Location: LABCELL_X10_Y4_N12 +\myVirtualToplevel|UART0|Selector10~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Selector10~0_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(3) & ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(3), + combout => \myVirtualToplevel|UART0|Selector10~0_combout\); + +-- Location: FF_X10_Y4_N13 +\myVirtualToplevel|UART0|RX_BUFFER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Selector10~0_combout\, + ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_BUFFER\(2)); + +-- Location: LABCELL_X10_Y4_N3 +\myVirtualToplevel|UART0|Selector11~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Selector11~0_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(2) & ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(2), + combout => \myVirtualToplevel|UART0|Selector11~0_combout\); + +-- Location: FF_X10_Y4_N4 +\myVirtualToplevel|UART0|RX_BUFFER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Selector11~0_combout\, + ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_BUFFER\(1)); + +-- Location: LABCELL_X10_Y4_N36 +\myVirtualToplevel|UART0|Selector12~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Selector12~0_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(1) & ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(1), + combout => \myVirtualToplevel|UART0|Selector12~0_combout\); + +-- Location: FF_X10_Y4_N38 +\myVirtualToplevel|UART0|RX_BUFFER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Selector12~0_combout\, + ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_BUFFER\(0)); + +-- Location: FF_X9_Y5_N31 +\myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_CLOCK~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE_q\); + +-- Location: MLABCELL_X9_Y5_N18 +\myVirtualToplevel|UART0|RX_STATE.stop~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE_q\ & ( \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\ ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|UART0|RX_STATE.idle~q\ & \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[0]~1_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~DUPLICATE_q\, + combout => \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\); + +-- Location: MLABCELL_X9_Y5_N48 +\myVirtualToplevel|UART0|RX_STATE.stop~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_STATE.stop~1_combout\ = ( \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( (\myVirtualToplevel|UART0|RX_STATE.bits~q\ & (((\myVirtualToplevel|UART0|RX_BUFFER\(0) & !\myVirtualToplevel|UART0|RX_ENABLE~q\)) # +-- (\myVirtualToplevel|UART0|RX_STATE.stop~q\))) ) ) # ( !\myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( ((\myVirtualToplevel|UART0|RX_STATE.bits~q\ & (\myVirtualToplevel|UART0|RX_BUFFER\(0) & !\myVirtualToplevel|UART0|RX_ENABLE~q\))) # +-- (\myVirtualToplevel|UART0|RX_STATE.stop~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011111111000100001111111100010000010101010001000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(0), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~0_combout\, + combout => \myVirtualToplevel|UART0|RX_STATE.stop~1_combout\); + +-- Location: FF_X9_Y5_N50 +\myVirtualToplevel|UART0|RX_STATE.stop\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_STATE.stop~1_combout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_STATE.stop~q\); + +-- Location: MLABCELL_X9_Y5_N51 +\myVirtualToplevel|UART0|RX_STATE.stop~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_STATE.stop~2_combout\ = ( \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( (!\myVirtualToplevel|UART0|RX_STATE.bits~q\) # ((\myVirtualToplevel|UART0|RX_BUFFER\(0) & !\myVirtualToplevel|UART0|RX_ENABLE~q\)) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( (\myVirtualToplevel|UART0|RX_STATE.bits~q\ & (\myVirtualToplevel|UART0|RX_BUFFER\(0) & !\myVirtualToplevel|UART0|RX_ENABLE~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000000000100010000000010111011101010101011101110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(0), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~0_combout\, + combout => \myVirtualToplevel|UART0|RX_STATE.stop~2_combout\); + +-- Location: MLABCELL_X9_Y5_N12 +\myVirtualToplevel|UART0|RX_STATE.idle~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_STATE.idle~0_combout\ = ( \myVirtualToplevel|UART0|RX_STATE.stop~2_combout\ & ( (!\myVirtualToplevel|UART0|RX_STATE.start~q\ & ((!\myVirtualToplevel|UART0|RX_STATE.stop~q\))) # (\myVirtualToplevel|UART0|RX_STATE.start~q\ & +-- (!\myVirtualToplevel|UART0|RXD_SYNC~q\)) ) ) # ( !\myVirtualToplevel|UART0|RX_STATE.stop~2_combout\ & ( \myVirtualToplevel|UART0|RX_STATE.idle~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111100100111001001110010011100100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.start~q\, + datab => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~2_combout\, + combout => \myVirtualToplevel|UART0|RX_STATE.idle~0_combout\); + +-- Location: FF_X9_Y5_N14 +\myVirtualToplevel|UART0|RX_STATE.idle\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_STATE.idle~0_combout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_STATE.idle~q\); + +-- Location: MLABCELL_X9_Y5_N21 +\myVirtualToplevel|UART0|RX_STATE.start~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_STATE.start~0_combout\ = ( \myVirtualToplevel|UART0|RX_STATE.stop~2_combout\ & ( !\myVirtualToplevel|UART0|RX_STATE.idle~q\ ) ) # ( !\myVirtualToplevel|UART0|RX_STATE.stop~2_combout\ & ( +-- \myVirtualToplevel|UART0|RX_STATE.start~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.start~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~2_combout\, + combout => \myVirtualToplevel|UART0|RX_STATE.start~0_combout\); + +-- Location: FF_X9_Y5_N23 +\myVirtualToplevel|UART0|RX_STATE.start\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_STATE.start~0_combout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_STATE.start~q\); + +-- Location: MLABCELL_X9_Y5_N54 +\myVirtualToplevel|UART0|RX_STATE.bits~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_STATE.bits~0_combout\ = ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ & ( \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( ((!\myVirtualToplevel|UART0|RX_BUFFER\(0)) # ((!\myVirtualToplevel|UART0|RXD_SYNC~q\ & +-- \myVirtualToplevel|UART0|RX_STATE.start~q\))) # (\myVirtualToplevel|UART0|RX_ENABLE~q\) ) ) ) # ( !\myVirtualToplevel|UART0|RX_STATE.bits~q\ & ( \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( (!\myVirtualToplevel|UART0|RXD_SYNC~q\ & +-- \myVirtualToplevel|UART0|RX_STATE.start~q\) ) ) ) # ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ & ( !\myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( ((!\myVirtualToplevel|UART0|RX_BUFFER\(0)) # ((!\myVirtualToplevel|UART0|RXD_SYNC~q\ & +-- \myVirtualToplevel|UART0|RX_STATE.start~q\))) # (\myVirtualToplevel|UART0|RX_ENABLE~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110101110100001100000011001111111101011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + datab => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.start~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(0), + datae => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~0_combout\, + combout => \myVirtualToplevel|UART0|RX_STATE.bits~0_combout\); + +-- Location: FF_X9_Y5_N56 +\myVirtualToplevel|UART0|RX_STATE.bits\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_STATE.bits~0_combout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_STATE.bits~q\); + +-- Location: LABCELL_X10_Y4_N39 +\myVirtualToplevel|UART0|Selector4~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Selector4~0_combout\ = (!\myVirtualToplevel|UART0|RX_STATE.bits~q\) # (\myVirtualToplevel|UART0|RXD_SYNC~q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011111111110011001111111111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\, + combout => \myVirtualToplevel|UART0|Selector4~0_combout\); + +-- Location: FF_X10_Y4_N40 +\myVirtualToplevel|UART0|RX_BUFFER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Selector4~0_combout\, + ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_BUFFER\(8)); + +-- Location: LABCELL_X10_Y4_N57 +\myVirtualToplevel|UART0|Selector5~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Selector5~0_combout\ = ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ & ( \myVirtualToplevel|UART0|RX_BUFFER\(8) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(8), + combout => \myVirtualToplevel|UART0|Selector5~0_combout\); + +-- Location: FF_X10_Y4_N58 +\myVirtualToplevel|UART0|RX_BUFFER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Selector5~0_combout\, + ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_BUFFER\(7)); + +-- Location: FF_X10_Y5_N2 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER\(7), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(23)); + +-- Location: LABCELL_X12_Y5_N24 +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1_combout\ = !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(0), + combout => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1_combout\); + +-- Location: MLABCELL_X9_Y5_N45 +\myVirtualToplevel|UART0|RX_INTR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_INTR~0_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE_q\ & ( (\myVirtualToplevel|UART0|RX_STATE.stop~q\ & \myVirtualToplevel|UART0|RXD_SYNC~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~DUPLICATE_q\, + combout => \myVirtualToplevel|UART0|RX_INTR~0_combout\); + +-- Location: LABCELL_X12_Y5_N0 +\myVirtualToplevel|UART0|Add3~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add3~5_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|UART0|Add3~6\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\, + cin => GND, + sumout => \myVirtualToplevel|UART0|Add3~5_sumout\, + cout => \myVirtualToplevel|UART0|Add3~6\); + +-- Location: LABCELL_X12_Y5_N30 +\myVirtualToplevel|UART0|Add4~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add4~5_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(0) ) + ( !VCC )) +-- \myVirtualToplevel|UART0|Add4~6\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(0) ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(0), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1), + cin => GND, + sumout => \myVirtualToplevel|UART0|Add4~5_sumout\, + cout => \myVirtualToplevel|UART0|Add4~6\); + +-- Location: FF_X12_Y5_N32 +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add4~5_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1)); + +-- Location: LABCELL_X12_Y5_N33 +\myVirtualToplevel|UART0|Add4~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add4~21_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~6\ )) +-- \myVirtualToplevel|UART0|Add4~22\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2), + cin => \myVirtualToplevel|UART0|Add4~6\, + sumout => \myVirtualToplevel|UART0|Add4~21_sumout\, + cout => \myVirtualToplevel|UART0|Add4~22\); + +-- Location: FF_X12_Y5_N35 +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add4~21_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2)); + +-- Location: LABCELL_X12_Y5_N36 +\myVirtualToplevel|UART0|Add4~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add4~9_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~22\ )) +-- \myVirtualToplevel|UART0|Add4~10\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3), + cin => \myVirtualToplevel|UART0|Add4~22\, + sumout => \myVirtualToplevel|UART0|Add4~9_sumout\, + cout => \myVirtualToplevel|UART0|Add4~10\); + +-- Location: FF_X12_Y5_N38 +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add4~9_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3)); + +-- Location: LABCELL_X12_Y5_N39 +\myVirtualToplevel|UART0|Add4~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add4~1_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~10\ )) +-- \myVirtualToplevel|UART0|Add4~2\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4), + cin => \myVirtualToplevel|UART0|Add4~10\, + sumout => \myVirtualToplevel|UART0|Add4~1_sumout\, + cout => \myVirtualToplevel|UART0|Add4~2\); + +-- Location: FF_X12_Y5_N40 +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add4~1_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4)); + +-- Location: LABCELL_X12_Y5_N42 +\myVirtualToplevel|UART0|Add4~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add4~25_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~2\ )) +-- \myVirtualToplevel|UART0|Add4~26\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(5), + cin => \myVirtualToplevel|UART0|Add4~2\, + sumout => \myVirtualToplevel|UART0|Add4~25_sumout\, + cout => \myVirtualToplevel|UART0|Add4~26\); + +-- Location: FF_X12_Y5_N44 +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add4~25_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5)); + +-- Location: LABCELL_X12_Y5_N45 +\myVirtualToplevel|UART0|Add4~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add4~13_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~26\ )) +-- \myVirtualToplevel|UART0|Add4~14\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6), + cin => \myVirtualToplevel|UART0|Add4~26\, + sumout => \myVirtualToplevel|UART0|Add4~13_sumout\, + cout => \myVirtualToplevel|UART0|Add4~14\); + +-- Location: FF_X12_Y5_N47 +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add4~13_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6)); + +-- Location: LABCELL_X12_Y5_N48 +\myVirtualToplevel|UART0|Add4~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add4~17_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7), + cin => \myVirtualToplevel|UART0|Add4~14\, + sumout => \myVirtualToplevel|UART0|Add4~17_sumout\); + +-- Location: FF_X12_Y5_N49 +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add4~17_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7)); + +-- Location: LABCELL_X12_Y5_N3 +\myVirtualToplevel|UART0|Add3~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add3~9_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~6\ )) +-- \myVirtualToplevel|UART0|Add3~10\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1), + cin => \myVirtualToplevel|UART0|Add3~6\, + sumout => \myVirtualToplevel|UART0|Add3~9_sumout\, + cout => \myVirtualToplevel|UART0|Add3~10\); + +-- Location: LABCELL_X12_Y5_N6 +\myVirtualToplevel|UART0|Add3~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add3~25_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~10\ )) +-- \myVirtualToplevel|UART0|Add3~26\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|UART0|Add3~10\, + sumout => \myVirtualToplevel|UART0|Add3~25_sumout\, + cout => \myVirtualToplevel|UART0|Add3~26\); + +-- Location: FF_X12_Y5_N8 +\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add3~25_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2)); + +-- Location: LABCELL_X12_Y5_N9 +\myVirtualToplevel|UART0|Add3~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add3~13_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~26\ )) +-- \myVirtualToplevel|UART0|Add3~14\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|UART0|Add3~26\, + sumout => \myVirtualToplevel|UART0|Add3~13_sumout\, + cout => \myVirtualToplevel|UART0|Add3~14\); + +-- Location: FF_X12_Y5_N11 +\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add3~13_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3)); + +-- Location: LABCELL_X12_Y5_N12 +\myVirtualToplevel|UART0|Add3~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add3~1_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~14\ )) +-- \myVirtualToplevel|UART0|Add3~2\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|UART0|Add3~14\, + sumout => \myVirtualToplevel|UART0|Add3~1_sumout\, + cout => \myVirtualToplevel|UART0|Add3~2\); + +-- Location: FF_X10_Y6_N19 +\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add3~1_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4)); + +-- Location: LABCELL_X12_Y5_N15 +\myVirtualToplevel|UART0|Add3~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add3~29_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~2\ )) +-- \myVirtualToplevel|UART0|Add3~30\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(5), + cin => \myVirtualToplevel|UART0|Add3~2\, + sumout => \myVirtualToplevel|UART0|Add3~29_sumout\, + cout => \myVirtualToplevel|UART0|Add3~30\); + +-- Location: FF_X12_Y5_N17 +\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add3~29_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5)); + +-- Location: LABCELL_X12_Y5_N18 +\myVirtualToplevel|UART0|Add3~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add3~17_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~30\ )) +-- \myVirtualToplevel|UART0|Add3~18\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(6), + cin => \myVirtualToplevel|UART0|Add3~30\, + sumout => \myVirtualToplevel|UART0|Add3~17_sumout\, + cout => \myVirtualToplevel|UART0|Add3~18\); + +-- Location: FF_X12_Y5_N20 +\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add3~17_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6)); + +-- Location: LABCELL_X12_Y5_N21 +\myVirtualToplevel|UART0|Add3~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add3~21_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(7), + cin => \myVirtualToplevel|UART0|Add3~18\, + sumout => \myVirtualToplevel|UART0|Add3~21_sumout\); + +-- Location: FF_X12_Y5_N23 +\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add3~21_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7)); + +-- Location: LABCELL_X10_Y6_N54 +\myVirtualToplevel|UART0|Equal2~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal2~2_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & ( (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) $ (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7)))) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & ( (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) $ (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000110000110000000011000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(6), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(7), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6), + combout => \myVirtualToplevel|UART0|Equal2~2_combout\); + +-- Location: LABCELL_X12_Y6_N45 +\myVirtualToplevel|UART0|Equal2~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal2~1_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & ( (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4)))) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & ( (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010010100000000101001010000000000000000101001010000000010100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(4), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(3), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3), + combout => \myVirtualToplevel|UART0|Equal2~1_combout\); + +-- Location: FF_X12_Y5_N58 +\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add3~5_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0)); + +-- Location: FF_X12_Y5_N25 +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1_combout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y6_N42 +\myVirtualToplevel|UART0|Equal2~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal2~0_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1)))) ) +-- ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001100000000110000110000000000000000110000110000000011000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(0), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|UART0|Equal2~0_combout\); + +-- Location: LABCELL_X10_Y6_N6 +\myVirtualToplevel|UART0|Equal2~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal2~3_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) & ( (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) $ (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5)))) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) & ( (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) $ (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000001010000010100000101000001001000001010000010100000101000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2), + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(5), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(5), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(2), + combout => \myVirtualToplevel|UART0|Equal2~3_combout\); + +-- Location: LABCELL_X10_Y6_N3 +\myVirtualToplevel|UART0|Equal2~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal2~4_combout\ = (\myVirtualToplevel|UART0|Equal2~2_combout\ & (\myVirtualToplevel|UART0|Equal2~1_combout\ & (\myVirtualToplevel|UART0|Equal2~0_combout\ & \myVirtualToplevel|UART0|Equal2~3_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000100000000000000010000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Equal2~2_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_Equal2~1_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Equal2~0_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_Equal2~3_combout\, + combout => \myVirtualToplevel|UART0|Equal2~4_combout\); + +-- Location: MLABCELL_X13_Y9_N24 +\myVirtualToplevel|UART0|RX_DATA_READY~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA_READY~0_combout\ = ( \myVirtualToplevel|UART0_CS~combout\ & ( (\myVirtualToplevel|UART1|Equal7~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\, + dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\, + combout => \myVirtualToplevel|UART0|RX_DATA_READY~0_combout\); + +-- Location: MLABCELL_X9_Y6_N27 +\myVirtualToplevel|UART0|RX_DATA_READY~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA_READY~1_combout\ = ( \myVirtualToplevel|UART0|RX_DATA_READY~0_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA_READY~q\ & ((!\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & +-- (!\myVirtualToplevel|UART0|Equal2~4_combout\)) # (\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & ((\myVirtualToplevel|UART0|RX_INTR~0_combout\))))) ) ) # ( !\myVirtualToplevel|UART0|RX_DATA_READY~0_combout\ & ( +-- ((!\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & (!\myVirtualToplevel|UART0|Equal2~4_combout\)) # (\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & ((\myVirtualToplevel|UART0|RX_INTR~0_combout\)))) # +-- (\myVirtualToplevel|UART0|RX_DATA_READY~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000101111111111100010111111111110001011000000001000101100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Equal2~4_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~0_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA_READY~1_combout\); + +-- Location: FF_X9_Y6_N28 +\myVirtualToplevel|UART0|RX_DATA_READY\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_DATA_READY~1_combout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_DATA_READY~q\); + +-- Location: MLABCELL_X9_Y6_N57 +\myVirtualToplevel|UART0|process_3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|process_3~0_combout\ = ( !\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & ( !\myVirtualToplevel|UART0|RX_DATA_READY~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\, + combout => \myVirtualToplevel|UART0|process_3~0_combout\); + +-- Location: LABCELL_X10_Y6_N21 +\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\ = ( \myVirtualToplevel|UART0|Equal2~0_combout\ & ( \myVirtualToplevel|UART0|Equal2~1_combout\ & ( (\myVirtualToplevel|UART0|process_3~0_combout\ & (!\myVirtualToplevel|UART0|RX_ENABLE~q\ & +-- ((!\myVirtualToplevel|UART0|Equal2~2_combout\) # (!\myVirtualToplevel|UART0|Equal2~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|UART0|Equal2~0_combout\ & ( \myVirtualToplevel|UART0|Equal2~1_combout\ & ( (\myVirtualToplevel|UART0|process_3~0_combout\ & +-- !\myVirtualToplevel|UART0|RX_ENABLE~q\) ) ) ) # ( \myVirtualToplevel|UART0|Equal2~0_combout\ & ( !\myVirtualToplevel|UART0|Equal2~1_combout\ & ( (\myVirtualToplevel|UART0|process_3~0_combout\ & !\myVirtualToplevel|UART0|RX_ENABLE~q\) ) ) ) # ( +-- !\myVirtualToplevel|UART0|Equal2~0_combout\ & ( !\myVirtualToplevel|UART0|Equal2~1_combout\ & ( (\myVirtualToplevel|UART0|process_3~0_combout\ & !\myVirtualToplevel|UART0|RX_ENABLE~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000110000001100000011000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Equal2~2_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_process_3~0_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_Equal2~3_combout\, + datae => \myVirtualToplevel|UART0|ALT_INV_Equal2~0_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_Equal2~1_combout\, + combout => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\); + +-- Location: FF_X12_Y5_N59 +\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add3~5_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\); + +-- Location: FF_X10_Y6_N28 +\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add3~9_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1)); + +-- Location: LABCELL_X12_Y6_N0 +\myVirtualToplevel|UART0|Add2~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add2~22\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(0), + cin => GND, + cout => \myVirtualToplevel|UART0|Add2~22\); + +-- Location: LABCELL_X12_Y6_N3 +\myVirtualToplevel|UART0|Add2~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add2~25_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~22\ )) +-- \myVirtualToplevel|UART0|Add2~26\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1), + cin => \myVirtualToplevel|UART0|Add2~22\, + sumout => \myVirtualToplevel|UART0|Add2~25_sumout\, + cout => \myVirtualToplevel|UART0|Add2~26\); + +-- Location: LABCELL_X12_Y6_N6 +\myVirtualToplevel|UART0|Add2~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add2~29_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~26\ )) +-- \myVirtualToplevel|UART0|Add2~30\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|UART0|Add2~26\, + sumout => \myVirtualToplevel|UART0|Add2~29_sumout\, + cout => \myVirtualToplevel|UART0|Add2~30\); + +-- Location: LABCELL_X12_Y6_N24 +\myVirtualToplevel|UART0|Equal3~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal3~1_combout\ = ( !\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) & ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|Add2~25_sumout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) & +-- (!\myVirtualToplevel|UART0|Add2~29_sumout\ $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2))))) # (\myVirtualToplevel|UART0|Add2~25_sumout\ & (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART0|Add2~29_sumout\ $ +-- (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2))))) ) ) ) # ( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) & ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|Add2~25_sumout\ & +-- (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART0|Add2~29_sumout\ $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2))))) # (\myVirtualToplevel|UART0|Add2~25_sumout\ & (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) & +-- (!\myVirtualToplevel|UART0|Add2~29_sumout\ $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000100001000010000110000100001000010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Add2~25_sumout\, + datab => \myVirtualToplevel|UART0|ALT_INV_Add2~29_sumout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2), + datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(0), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|UART0|Equal3~1_combout\); + +-- Location: LABCELL_X12_Y6_N9 +\myVirtualToplevel|UART0|Add2~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add2~9_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~30\ )) +-- \myVirtualToplevel|UART0|Add2~10\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|UART0|Add2~30\, + sumout => \myVirtualToplevel|UART0|Add2~9_sumout\, + cout => \myVirtualToplevel|UART0|Add2~10\); + +-- Location: LABCELL_X12_Y6_N12 +\myVirtualToplevel|UART0|Add2~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add2~13_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~10\ )) +-- \myVirtualToplevel|UART0|Add2~14\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|UART0|Add2~10\, + sumout => \myVirtualToplevel|UART0|Add2~13_sumout\, + cout => \myVirtualToplevel|UART0|Add2~14\); + +-- Location: LABCELL_X12_Y6_N15 +\myVirtualToplevel|UART0|Add2~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add2~17_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~14\ )) +-- \myVirtualToplevel|UART0|Add2~18\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(5), + cin => \myVirtualToplevel|UART0|Add2~14\, + sumout => \myVirtualToplevel|UART0|Add2~17_sumout\, + cout => \myVirtualToplevel|UART0|Add2~18\); + +-- Location: LABCELL_X12_Y6_N18 +\myVirtualToplevel|UART0|Add2~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add2~1_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~18\ )) +-- \myVirtualToplevel|UART0|Add2~2\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(6), + cin => \myVirtualToplevel|UART0|Add2~18\, + sumout => \myVirtualToplevel|UART0|Add2~1_sumout\, + cout => \myVirtualToplevel|UART0|Add2~2\); + +-- Location: LABCELL_X12_Y6_N21 +\myVirtualToplevel|UART0|Add2~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add2~5_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(7), + cin => \myVirtualToplevel|UART0|Add2~2\, + sumout => \myVirtualToplevel|UART0|Add2~5_sumout\); + +-- Location: LABCELL_X12_Y6_N39 +\myVirtualToplevel|UART0|Equal3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal3~0_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) & ( \myVirtualToplevel|UART0|Add2~13_sumout\ & ( (\myVirtualToplevel|UART0|Add2~17_sumout\ & (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) & +-- (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) $ (\myVirtualToplevel|UART0|Add2~9_sumout\)))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) & ( \myVirtualToplevel|UART0|Add2~13_sumout\ & ( (!\myVirtualToplevel|UART0|Add2~17_sumout\ & +-- (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) $ (\myVirtualToplevel|UART0|Add2~9_sumout\)))) ) ) ) # ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) & ( !\myVirtualToplevel|UART0|Add2~13_sumout\ & ( +-- (\myVirtualToplevel|UART0|Add2~17_sumout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) $ (\myVirtualToplevel|UART0|Add2~9_sumout\)))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) & ( +-- !\myVirtualToplevel|UART0|Add2~13_sumout\ & ( (!\myVirtualToplevel|UART0|Add2~17_sumout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) $ (\myVirtualToplevel|UART0|Add2~9_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001000000000000000010010000000000000000100100000000000000001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3), + datab => \myVirtualToplevel|UART0|ALT_INV_Add2~9_sumout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Add2~17_sumout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4), + datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(5), + dataf => \myVirtualToplevel|UART0|ALT_INV_Add2~13_sumout\, + combout => \myVirtualToplevel|UART0|Equal3~0_combout\); + +-- Location: LABCELL_X12_Y6_N54 +\myVirtualToplevel|UART0|Equal3~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal3~2_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & ( \myVirtualToplevel|UART0|Add2~1_sumout\ & ( (\myVirtualToplevel|UART0|Equal3~1_combout\ & (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & +-- (\myVirtualToplevel|UART0|Add2~5_sumout\ & \myVirtualToplevel|UART0|Equal3~0_combout\))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & ( \myVirtualToplevel|UART0|Add2~1_sumout\ & ( (\myVirtualToplevel|UART0|Equal3~1_combout\ & +-- (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART0|Add2~5_sumout\ & \myVirtualToplevel|UART0|Equal3~0_combout\))) ) ) ) # ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & ( !\myVirtualToplevel|UART0|Add2~1_sumout\ & ( +-- (\myVirtualToplevel|UART0|Equal3~1_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & (\myVirtualToplevel|UART0|Add2~5_sumout\ & \myVirtualToplevel|UART0|Equal3~0_combout\))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & ( +-- !\myVirtualToplevel|UART0|Add2~1_sumout\ & ( (\myVirtualToplevel|UART0|Equal3~1_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART0|Add2~5_sumout\ & \myVirtualToplevel|UART0|Equal3~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000000000000000010000000000000100000000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Equal3~1_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6), + datac => \myVirtualToplevel|UART0|ALT_INV_Add2~5_sumout\, + datad => \myVirtualToplevel|UART0|ALT_INV_Equal3~0_combout\, + datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7), + dataf => \myVirtualToplevel|UART0|ALT_INV_Add2~1_sumout\, + combout => \myVirtualToplevel|UART0|Equal3~2_combout\); + +-- Location: LABCELL_X12_Y5_N27 +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\ = ( !\myVirtualToplevel|UART0|Equal3~2_combout\ & ( (!\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & (\myVirtualToplevel|UART0|RX_INTR~0_combout\ & !\myVirtualToplevel|UART0|RX_ENABLE~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000100000001000000010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_Equal3~2_combout\, + combout => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\); + +-- Location: FF_X12_Y5_N26 +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1_combout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(0)); + +-- Location: LABCELL_X10_Y6_N9 +\myVirtualToplevel|UART0|RX_FIFO~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO~33_combout\ = (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000100000000000000010000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2), + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(5), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4), + combout => \myVirtualToplevel|UART0|RX_FIFO~33_combout\); + +-- Location: MLABCELL_X9_Y5_N24 +\myVirtualToplevel|UART0|RX_FIFO~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO~31_combout\ = ( \myVirtualToplevel|UART0|RX_RESET~q\ & ( !\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|RX_ENABLE~q\ & (\myVirtualToplevel|UART0|RX_CLOCK~q\ & +-- (\myVirtualToplevel|UART0|RX_STATE.stop~q\ & \myVirtualToplevel|UART0|RXD_SYNC~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000001000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\, + datae => \myVirtualToplevel|UART0|ALT_INV_RX_RESET~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\, + combout => \myVirtualToplevel|UART0|RX_FIFO~31_combout\); + +-- Location: LABCELL_X12_Y6_N48 +\myVirtualToplevel|UART0|Equal3~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal3~3_combout\ = ( \myVirtualToplevel|UART0|Add2~1_sumout\ & ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) ) ) # ( !\myVirtualToplevel|UART0|Add2~1_sumout\ & ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001111001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6), + dataf => \myVirtualToplevel|UART0|ALT_INV_Add2~1_sumout\, + combout => \myVirtualToplevel|UART0|Equal3~3_combout\); + +-- Location: LABCELL_X12_Y6_N30 +\myVirtualToplevel|UART0|RX_FIFO~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO~32_combout\ = ( \myVirtualToplevel|UART0|Add2~5_sumout\ & ( \myVirtualToplevel|UART0|Equal3~3_combout\ & ( \myVirtualToplevel|UART0|RX_FIFO~31_combout\ ) ) ) # ( !\myVirtualToplevel|UART0|Add2~5_sumout\ & ( +-- \myVirtualToplevel|UART0|Equal3~3_combout\ & ( \myVirtualToplevel|UART0|RX_FIFO~31_combout\ ) ) ) # ( \myVirtualToplevel|UART0|Add2~5_sumout\ & ( !\myVirtualToplevel|UART0|Equal3~3_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO~31_combout\ & +-- ((!\myVirtualToplevel|UART0|Equal3~0_combout\) # ((!\myVirtualToplevel|UART0|Equal3~1_combout\) # (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7))))) ) ) ) # ( !\myVirtualToplevel|UART0|Add2~5_sumout\ & ( !\myVirtualToplevel|UART0|Equal3~3_combout\ & ( +-- (\myVirtualToplevel|UART0|RX_FIFO~31_combout\ & ((!\myVirtualToplevel|UART0|Equal3~0_combout\) # ((!\myVirtualToplevel|UART0|Equal3~1_combout\) # (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010001010101010101010101010001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~31_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_Equal3~0_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Equal3~1_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7), + datae => \myVirtualToplevel|UART0|ALT_INV_Add2~5_sumout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_Equal3~3_combout\, + combout => \myVirtualToplevel|UART0|RX_FIFO~32_combout\); + +-- Location: LABCELL_X10_Y6_N24 +\myVirtualToplevel|UART0|RX_FIFO~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO~34_combout\ = ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & ( \myVirtualToplevel|UART0|RX_FIFO~32_combout\ & ( (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(0) & (\myVirtualToplevel|UART0|RX_FIFO~33_combout\ & +-- (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(0), + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~33_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1), + datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~32_combout\, + combout => \myVirtualToplevel|UART0|RX_FIFO~34_combout\); + +-- Location: FF_X10_Y5_N25 +\myVirtualToplevel|UART0|RX_FIFO~24\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER\(7), + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO~24_q\); + +-- Location: LABCELL_X10_Y6_N0 +\myVirtualToplevel|UART0|RX_FIFO~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO~35_combout\ = (\myVirtualToplevel|UART0|RX_FIFO~17_q\) # (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111111111000011111111111100001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~17_q\, + combout => \myVirtualToplevel|UART0|RX_FIFO~35_combout\); + +-- Location: FF_X10_Y6_N2 +\myVirtualToplevel|UART0|RX_FIFO~17\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_FIFO~35_combout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO~17_q\); + +-- Location: FF_X10_Y6_N41 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(15)); + +-- Location: FF_X10_Y6_N38 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(13)); + +-- Location: FF_X9_Y6_N14 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(11)); + +-- Location: FF_X10_Y6_N35 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add3~17_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(14)); + +-- Location: FF_X12_Y5_N55 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add3~29_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(12)); + +-- Location: LABCELL_X10_Y6_N33 +\myVirtualToplevel|UART0|RX_FIFO~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO~26_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(12) & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(11) & (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(13) $ +-- (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(14)))) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(12) & ( (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(11) & (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(13) $ +-- (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(14)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000001010000101000000101000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(13), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(11), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(14), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(12), + combout => \myVirtualToplevel|UART0|RX_FIFO~26_combout\); + +-- Location: FF_X10_Y6_N32 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add3~21_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(16)); + +-- Location: FF_X10_Y6_N50 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add3~9_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(4)); + +-- Location: FF_X10_Y6_N8 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add3~5_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(2)); + +-- Location: FF_X12_Y6_N34 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(1)); + +-- Location: FF_X10_Y6_N44 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(3)); + +-- Location: FF_X12_Y6_N28 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_FIFO~32_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(0)); + +-- Location: LABCELL_X10_Y6_N42 +\myVirtualToplevel|UART0|RX_FIFO~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO~27_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(0) & ( (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(4) & (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(3) & +-- (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(2) $ (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(1))))) # (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(4) & (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(3) & +-- (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(2) $ (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(1))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000010010000011000001001000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(4), + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(2), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(1), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(3), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(0), + combout => \myVirtualToplevel|UART0|RX_FIFO~27_combout\); + +-- Location: FF_X9_Y6_N58 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(9)); + +-- Location: FF_X10_Y6_N53 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add3~1_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(10)); + +-- Location: FF_X12_Y5_N14 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add3~13_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(8)); + +-- Location: FF_X12_Y5_N5 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add3~25_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(6)); + +-- Location: FF_X9_Y6_N52 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(5)); + +-- Location: FF_X9_Y6_N22 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(7)); + +-- Location: LABCELL_X12_Y5_N54 +\myVirtualToplevel|UART0|RX_FIFO~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO~28_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(5) & ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(7) & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(8) & +-- \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(6)) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(5) & ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(7) & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(8) & +-- !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(6)) ) ) ) # ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(5) & ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(7) & ( (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(8) & +-- \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(6)) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(5) & ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(7) & ( (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(8) & +-- !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(6)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000000011000000110000110000001100000000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(8), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(6), + datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(5), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(7), + combout => \myVirtualToplevel|UART0|RX_FIFO~28_combout\); + +-- Location: LABCELL_X10_Y6_N51 +\myVirtualToplevel|UART0|RX_FIFO~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO~29_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(10) & ( \myVirtualToplevel|UART0|RX_FIFO~28_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO~27_combout\ & \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(9)) ) ) +-- ) # ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(10) & ( \myVirtualToplevel|UART0|RX_FIFO~28_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO~27_combout\ & !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(9)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110000001100000000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~27_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(9), + datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(10), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~28_combout\, + combout => \myVirtualToplevel|UART0|RX_FIFO~29_combout\); + +-- Location: LABCELL_X10_Y6_N30 +\myVirtualToplevel|UART0|RX_FIFO~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO~30_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO~29_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO~26_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(15) $ (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(16)))) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(15), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~26_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(16), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~29_combout\, + combout => \myVirtualToplevel|UART0|RX_FIFO~30_combout\); + +-- Location: MLABCELL_X9_Y6_N42 +\myVirtualToplevel|UART0|RX_DATA[7]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO~30_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA_READY~q\ & (\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_INTR~0_combout\)) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_FIFO~30_combout\ & ( (!\myVirtualToplevel|UART0|RX_FIFO~17_q\) # ((!\myVirtualToplevel|UART0|RX_DATA_READY~q\ & (\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_INTR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110010111100001111001000000000001000100000000000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~17_q\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~30_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA[7]~2_combout\); + +-- Location: FF_X12_Y5_N37 +\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add4~9_sumout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3]~DUPLICATE_q\); + +-- Location: FF_X10_Y4_N14 +\myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Selector10~0_combout\, + ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE_q\); + +-- Location: FF_X10_Y4_N11 +\myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Selector9~0_combout\, + ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\); + +-- Location: FF_X10_Y4_N7 +\myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Selector8~0_combout\, + ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\); + +-- Location: FF_X10_Y4_N52 +\myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Selector6~0_combout\, + ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE_q\); + +-- Location: M10K_X11_Y5_N0 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + logical_ram_name => "zpu_soc:myVirtualToplevel|uart:UART0|altsyncram:RX_FIFO_rtl_0|altsyncram_1jo1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 8, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 40, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 255, + port_a_logical_ram_depth => 256, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 8, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 40, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 255, + port_b_logical_ram_depth => 256, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|UART0|RX_FIFO~32_combout\, + portbre => VCC, + portbaddrstall => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X9_Y6_N45 +\myVirtualToplevel|UART0|RX_DATA[7]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ = ( !\myVirtualToplevel|UART0|RX_FIFO~30_combout\ & ( (!\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\) # ((!\myVirtualToplevel|UART0|RX_INTR~0_combout\) # (\myVirtualToplevel|UART0|RX_DATA_READY~q\)) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001111111111111100111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~30_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\); + +-- Location: LABCELL_X10_Y5_N24 +\myVirtualToplevel|UART0|RX_DATA~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA~8_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(7) & ( \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & +-- ((\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a6\))) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (\myVirtualToplevel|UART0|RX_FIFO~24_q\)) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(7) & ( +-- \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ((\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a6\))) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & +-- (\myVirtualToplevel|UART0|RX_FIFO~24_q\)) ) ) ) # ( \myVirtualToplevel|UART0|RX_BUFFER\(7) & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) # (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(23)) ) ) +-- ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(7) & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(23) & !\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(23), + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~24_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\, + datad => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(7), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA~8_combout\); + +-- Location: MLABCELL_X9_Y5_N42 +\myVirtualToplevel|UART0|RX_DATA[6]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA[6]~9_combout\ = ( \myVirtualToplevel|UART0|RX_DATA~8_combout\ & ( ((\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ & \myVirtualToplevel|UART0|RX_DATA[7]~0_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(6)) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_DATA~8_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA\(6) & ((!\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\) # (!\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111100000000001111110000000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(6), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA~8_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA[6]~9_combout\); + +-- Location: FF_X9_Y5_N43 +\myVirtualToplevel|UART0|RX_DATA[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_DATA[6]~9_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_DATA\(6)); + +-- Location: LABCELL_X12_Y9_N45 +\myVirtualToplevel|IO_DATA_READ~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~48_combout\ = ( \myVirtualToplevel|UART0|RX_DATA\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|UART0|RX_ENABLE~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_DATA\(6) & ( (!\myVirtualToplevel|UART0|RX_ENABLE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000100000001000000010000011100000111000001110000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(6), + combout => \myVirtualToplevel|IO_DATA_READ~48_combout\); + +-- Location: LABCELL_X14_Y9_N21 +\myVirtualToplevel|IO_DATA_READ[0]~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[0]~46_combout\ = ( !\myVirtualToplevel|TIMER0_CS~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100001111111111110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + combout => \myVirtualToplevel|IO_DATA_READ[0]~46_combout\); + +-- Location: MLABCELL_X9_Y12_N9 +\myVirtualToplevel|IO_DATA_READ~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~50_combout\ = ( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(6) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|UART1|Equal7~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100000001000000010000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(6), + combout => \myVirtualToplevel|IO_DATA_READ~50_combout\); + +-- Location: LABCELL_X12_Y12_N0 +\myVirtualToplevel|Add19~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add19~41_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|Add19~42\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(0), + cin => GND, + sumout => \myVirtualToplevel|Add19~41_sumout\, + cout => \myVirtualToplevel|Add19~42\); + +-- Location: LABCELL_X12_Y12_N36 +\myVirtualToplevel|Equal36~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal36~1_combout\ = ( !\myVirtualToplevel|SECOND_DOWN_COUNTER\(2) & ( !\myVirtualToplevel|SECOND_DOWN_COUNTER\(4) & ( (!\myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE_q\ & !\myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE_q\) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(2), + dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(4), + combout => \myVirtualToplevel|Equal36~1_combout\); + +-- Location: LABCELL_X12_Y12_N18 +\myVirtualToplevel|Add19~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add19~21_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add19~6\ )) +-- \myVirtualToplevel|Add19~22\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add19~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(6), + cin => \myVirtualToplevel|Add19~6\, + sumout => \myVirtualToplevel|Add19~21_sumout\, + cout => \myVirtualToplevel|Add19~22\); + +-- Location: LABCELL_X12_Y12_N21 +\myVirtualToplevel|Add19~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add19~25_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add19~22\ )) +-- \myVirtualToplevel|Add19~26\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add19~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(7), + cin => \myVirtualToplevel|Add19~22\, + sumout => \myVirtualToplevel|Add19~25_sumout\, + cout => \myVirtualToplevel|Add19~26\); + +-- Location: LABCELL_X16_Y13_N54 +\myVirtualToplevel|INTR0_CS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTR0_CS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + combout => \myVirtualToplevel|INTR0_CS~0_combout\); + +-- Location: LABCELL_X12_Y12_N48 +\myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\ = ( \myVirtualToplevel|INTR0_CS~0_combout\ & ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( (!\myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) ) # ( !\myVirtualToplevel|INTR0_CS~0_combout\ & ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( !\myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\ ) ) ) +-- # ( \myVirtualToplevel|INTR0_CS~0_combout\ & ( !\myVirtualToplevel|TIMER0_CS~2_combout\ & ( !\myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\ ) ) ) # ( !\myVirtualToplevel|INTR0_CS~0_combout\ & ( !\myVirtualToplevel|TIMER0_CS~2_combout\ & ( +-- !\myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111000000001111111100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER~0_combout\, + datae => \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + combout => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\); + +-- Location: FF_X12_Y12_N22 +\myVirtualToplevel|SECOND_DOWN_COUNTER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~25_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(7)); + +-- Location: LABCELL_X12_Y12_N24 +\myVirtualToplevel|Add19~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add19~29_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add19~26\ )) +-- \myVirtualToplevel|Add19~30\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add19~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(8), + cin => \myVirtualToplevel|Add19~26\, + sumout => \myVirtualToplevel|Add19~29_sumout\, + cout => \myVirtualToplevel|Add19~30\); + +-- Location: FF_X12_Y12_N26 +\myVirtualToplevel|SECOND_DOWN_COUNTER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~29_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(8)); + +-- Location: LABCELL_X12_Y12_N27 +\myVirtualToplevel|Add19~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add19~9_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add19~30\ )) +-- \myVirtualToplevel|Add19~10\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add19~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(9), + cin => \myVirtualToplevel|Add19~30\, + sumout => \myVirtualToplevel|Add19~9_sumout\, + cout => \myVirtualToplevel|Add19~10\); + +-- Location: FF_X12_Y12_N29 +\myVirtualToplevel|SECOND_DOWN_COUNTER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~9_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(9)); + +-- Location: LABCELL_X12_Y12_N30 +\myVirtualToplevel|Add19~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add19~13_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~10\ )) +-- \myVirtualToplevel|Add19~14\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[10]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add19~10\, + sumout => \myVirtualToplevel|Add19~13_sumout\, + cout => \myVirtualToplevel|Add19~14\); + +-- Location: FF_X12_Y12_N32 +\myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~13_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y12_N33 +\myVirtualToplevel|Add19~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add19~17_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add19~14\, + sumout => \myVirtualToplevel|Add19~17_sumout\); + +-- Location: FF_X12_Y12_N35 +\myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~17_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y12_N54 +\myVirtualToplevel|Equal36~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal36~0_combout\ = ( !\myVirtualToplevel|SECOND_DOWN_COUNTER\(9) & ( !\myVirtualToplevel|SECOND_DOWN_COUNTER\(8) & ( (!\myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE_q\ & (!\myVirtualToplevel|SECOND_DOWN_COUNTER\(7) & +-- (!\myVirtualToplevel|SECOND_DOWN_COUNTER\(0) & !\myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(7), + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(0), + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(9), + dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(8), + combout => \myVirtualToplevel|Equal36~0_combout\); + +-- Location: MLABCELL_X18_Y40_N0 +\myVirtualToplevel|Add18~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~93_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|Add18~94\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(0), + cin => GND, + sumout => \myVirtualToplevel|Add18~93_sumout\, + cout => \myVirtualToplevel|Add18~94\); + +-- Location: FF_X18_Y40_N2 +\myVirtualToplevel|SECOND_DOWN_TICK[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~93_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(0)); + +-- Location: MLABCELL_X18_Y40_N3 +\myVirtualToplevel|Add18~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~89_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add18~94\ )) +-- \myVirtualToplevel|Add18~90\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add18~94\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(1), + cin => \myVirtualToplevel|Add18~94\, + sumout => \myVirtualToplevel|Add18~89_sumout\, + cout => \myVirtualToplevel|Add18~90\); + +-- Location: FF_X18_Y40_N5 +\myVirtualToplevel|SECOND_DOWN_TICK[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~89_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(1)); + +-- Location: MLABCELL_X18_Y40_N6 +\myVirtualToplevel|Add18~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~85_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add18~90\ )) +-- \myVirtualToplevel|Add18~86\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add18~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(2), + cin => \myVirtualToplevel|Add18~90\, + sumout => \myVirtualToplevel|Add18~85_sumout\, + cout => \myVirtualToplevel|Add18~86\); + +-- Location: FF_X18_Y40_N8 +\myVirtualToplevel|SECOND_DOWN_TICK[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~85_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(2)); + +-- Location: MLABCELL_X18_Y40_N9 +\myVirtualToplevel|Add18~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~81_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add18~86\ )) +-- \myVirtualToplevel|Add18~82\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add18~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(3), + cin => \myVirtualToplevel|Add18~86\, + sumout => \myVirtualToplevel|Add18~81_sumout\, + cout => \myVirtualToplevel|Add18~82\); + +-- Location: FF_X18_Y40_N11 +\myVirtualToplevel|SECOND_DOWN_TICK[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~81_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(3)); + +-- Location: MLABCELL_X18_Y40_N12 +\myVirtualToplevel|Add18~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~77_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add18~82\ )) +-- \myVirtualToplevel|Add18~78\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add18~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(4), + cin => \myVirtualToplevel|Add18~82\, + sumout => \myVirtualToplevel|Add18~77_sumout\, + cout => \myVirtualToplevel|Add18~78\); + +-- Location: FF_X18_Y40_N14 +\myVirtualToplevel|SECOND_DOWN_TICK[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~77_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(4)); + +-- Location: MLABCELL_X18_Y40_N15 +\myVirtualToplevel|Add18~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~73_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add18~78\ )) +-- \myVirtualToplevel|Add18~74\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add18~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(5), + cin => \myVirtualToplevel|Add18~78\, + sumout => \myVirtualToplevel|Add18~73_sumout\, + cout => \myVirtualToplevel|Add18~74\); + +-- Location: FF_X18_Y40_N17 +\myVirtualToplevel|SECOND_DOWN_TICK[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~73_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(5)); + +-- Location: MLABCELL_X18_Y40_N18 +\myVirtualToplevel|Add18~109\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~109_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add18~74\ )) +-- \myVirtualToplevel|Add18~110\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add18~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(6), + cin => \myVirtualToplevel|Add18~74\, + sumout => \myVirtualToplevel|Add18~109_sumout\, + cout => \myVirtualToplevel|Add18~110\); + +-- Location: FF_X18_Y40_N20 +\myVirtualToplevel|SECOND_DOWN_TICK[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~109_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(6)); + +-- Location: MLABCELL_X18_Y40_N21 +\myVirtualToplevel|Add18~105\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~105_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add18~110\ )) +-- \myVirtualToplevel|Add18~106\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add18~110\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(7), + cin => \myVirtualToplevel|Add18~110\, + sumout => \myVirtualToplevel|Add18~105_sumout\, + cout => \myVirtualToplevel|Add18~106\); + +-- Location: FF_X18_Y40_N23 +\myVirtualToplevel|SECOND_DOWN_TICK[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~105_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(7)); + +-- Location: MLABCELL_X18_Y40_N24 +\myVirtualToplevel|Add18~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~69_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(8) ) + ( GND ) + ( \myVirtualToplevel|Add18~106\ )) +-- \myVirtualToplevel|Add18~70\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(8) ) + ( GND ) + ( \myVirtualToplevel|Add18~106\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(8), + cin => \myVirtualToplevel|Add18~106\, + sumout => \myVirtualToplevel|Add18~69_sumout\, + cout => \myVirtualToplevel|Add18~70\); + +-- Location: FF_X18_Y40_N26 +\myVirtualToplevel|SECOND_DOWN_TICK[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~69_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(8)); + +-- Location: MLABCELL_X18_Y40_N27 +\myVirtualToplevel|Add18~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~65_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(9) ) + ( GND ) + ( \myVirtualToplevel|Add18~70\ )) +-- \myVirtualToplevel|Add18~66\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(9) ) + ( GND ) + ( \myVirtualToplevel|Add18~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(9), + cin => \myVirtualToplevel|Add18~70\, + sumout => \myVirtualToplevel|Add18~65_sumout\, + cout => \myVirtualToplevel|Add18~66\); + +-- Location: FF_X18_Y40_N29 +\myVirtualToplevel|SECOND_DOWN_TICK[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~65_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(9)); + +-- Location: MLABCELL_X18_Y39_N0 +\myVirtualToplevel|Add18~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~13_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(10) ) + ( GND ) + ( \myVirtualToplevel|Add18~66\ )) +-- \myVirtualToplevel|Add18~14\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(10) ) + ( GND ) + ( \myVirtualToplevel|Add18~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(10), + cin => \myVirtualToplevel|Add18~66\, + sumout => \myVirtualToplevel|Add18~13_sumout\, + cout => \myVirtualToplevel|Add18~14\); + +-- Location: FF_X18_Y39_N1 +\myVirtualToplevel|SECOND_DOWN_TICK[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(10)); + +-- Location: MLABCELL_X18_Y39_N3 +\myVirtualToplevel|Add18~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~9_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(11) ) + ( GND ) + ( \myVirtualToplevel|Add18~14\ )) +-- \myVirtualToplevel|Add18~10\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(11) ) + ( GND ) + ( \myVirtualToplevel|Add18~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(11), + cin => \myVirtualToplevel|Add18~14\, + sumout => \myVirtualToplevel|Add18~9_sumout\, + cout => \myVirtualToplevel|Add18~10\); + +-- Location: FF_X18_Y39_N4 +\myVirtualToplevel|SECOND_DOWN_TICK[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(11)); + +-- Location: MLABCELL_X18_Y39_N6 +\myVirtualToplevel|Add18~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~45_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add18~10\ )) +-- \myVirtualToplevel|Add18~46\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add18~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add18~10\, + sumout => \myVirtualToplevel|Add18~45_sumout\, + cout => \myVirtualToplevel|Add18~46\); + +-- Location: FF_X18_Y39_N8 +\myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~45_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y39_N9 +\myVirtualToplevel|Add18~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~41_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(13) ) + ( GND ) + ( \myVirtualToplevel|Add18~46\ )) +-- \myVirtualToplevel|Add18~42\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(13) ) + ( GND ) + ( \myVirtualToplevel|Add18~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(13), + cin => \myVirtualToplevel|Add18~46\, + sumout => \myVirtualToplevel|Add18~41_sumout\, + cout => \myVirtualToplevel|Add18~42\); + +-- Location: FF_X18_Y39_N11 +\myVirtualToplevel|SECOND_DOWN_TICK[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~41_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(13)); + +-- Location: MLABCELL_X18_Y39_N12 +\myVirtualToplevel|Add18~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~37_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(14) ) + ( GND ) + ( \myVirtualToplevel|Add18~42\ )) +-- \myVirtualToplevel|Add18~38\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(14) ) + ( GND ) + ( \myVirtualToplevel|Add18~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(14), + cin => \myVirtualToplevel|Add18~42\, + sumout => \myVirtualToplevel|Add18~37_sumout\, + cout => \myVirtualToplevel|Add18~38\); + +-- Location: FF_X18_Y39_N14 +\myVirtualToplevel|SECOND_DOWN_TICK[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~37_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(14)); + +-- Location: MLABCELL_X18_Y39_N15 +\myVirtualToplevel|Add18~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~33_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add18~38\ )) +-- \myVirtualToplevel|Add18~34\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add18~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[15]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add18~38\, + sumout => \myVirtualToplevel|Add18~33_sumout\, + cout => \myVirtualToplevel|Add18~34\); + +-- Location: FF_X18_Y39_N17 +\myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~33_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y39_N18 +\myVirtualToplevel|Add18~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~29_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add18~34\ )) +-- \myVirtualToplevel|Add18~30\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add18~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[16]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add18~34\, + sumout => \myVirtualToplevel|Add18~29_sumout\, + cout => \myVirtualToplevel|Add18~30\); + +-- Location: FF_X18_Y39_N20 +\myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y39_N21 +\myVirtualToplevel|Add18~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~5_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(17) ) + ( GND ) + ( \myVirtualToplevel|Add18~30\ )) +-- \myVirtualToplevel|Add18~6\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(17) ) + ( GND ) + ( \myVirtualToplevel|Add18~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(17), + cin => \myVirtualToplevel|Add18~30\, + sumout => \myVirtualToplevel|Add18~5_sumout\, + cout => \myVirtualToplevel|Add18~6\); + +-- Location: FF_X18_Y39_N22 +\myVirtualToplevel|SECOND_DOWN_TICK[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(17)); + +-- Location: MLABCELL_X18_Y39_N24 +\myVirtualToplevel|Add18~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~25_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(18) ) + ( GND ) + ( \myVirtualToplevel|Add18~6\ )) +-- \myVirtualToplevel|Add18~26\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(18) ) + ( GND ) + ( \myVirtualToplevel|Add18~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(18), + cin => \myVirtualToplevel|Add18~6\, + sumout => \myVirtualToplevel|Add18~25_sumout\, + cout => \myVirtualToplevel|Add18~26\); + +-- Location: FF_X18_Y39_N26 +\myVirtualToplevel|SECOND_DOWN_TICK[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(18)); + +-- Location: MLABCELL_X18_Y39_N27 +\myVirtualToplevel|Add18~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~1_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(19) ) + ( GND ) + ( \myVirtualToplevel|Add18~26\ )) +-- \myVirtualToplevel|Add18~2\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(19) ) + ( GND ) + ( \myVirtualToplevel|Add18~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(19), + cin => \myVirtualToplevel|Add18~26\, + sumout => \myVirtualToplevel|Add18~1_sumout\, + cout => \myVirtualToplevel|Add18~2\); + +-- Location: FF_X18_Y39_N28 +\myVirtualToplevel|SECOND_DOWN_TICK[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(19)); + +-- Location: MLABCELL_X18_Y39_N30 +\myVirtualToplevel|Add18~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~21_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(20) ) + ( GND ) + ( \myVirtualToplevel|Add18~2\ )) +-- \myVirtualToplevel|Add18~22\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(20) ) + ( GND ) + ( \myVirtualToplevel|Add18~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(20), + cin => \myVirtualToplevel|Add18~2\, + sumout => \myVirtualToplevel|Add18~21_sumout\, + cout => \myVirtualToplevel|Add18~22\); + +-- Location: FF_X18_Y39_N32 +\myVirtualToplevel|SECOND_DOWN_TICK[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(20)); + +-- Location: MLABCELL_X18_Y39_N33 +\myVirtualToplevel|Add18~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~17_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(21) ) + ( GND ) + ( \myVirtualToplevel|Add18~22\ )) +-- \myVirtualToplevel|Add18~18\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(21) ) + ( GND ) + ( \myVirtualToplevel|Add18~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(21), + cin => \myVirtualToplevel|Add18~22\, + sumout => \myVirtualToplevel|Add18~17_sumout\, + cout => \myVirtualToplevel|Add18~18\); + +-- Location: FF_X18_Y39_N35 +\myVirtualToplevel|SECOND_DOWN_TICK[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(21)); + +-- Location: MLABCELL_X18_Y39_N36 +\myVirtualToplevel|Add18~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~61_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(22) ) + ( GND ) + ( \myVirtualToplevel|Add18~18\ )) +-- \myVirtualToplevel|Add18~62\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(22) ) + ( GND ) + ( \myVirtualToplevel|Add18~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(22), + cin => \myVirtualToplevel|Add18~18\, + sumout => \myVirtualToplevel|Add18~61_sumout\, + cout => \myVirtualToplevel|Add18~62\); + +-- Location: FF_X18_Y39_N37 +\myVirtualToplevel|SECOND_DOWN_TICK[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~61_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(22)); + +-- Location: MLABCELL_X18_Y39_N39 +\myVirtualToplevel|Add18~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~57_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(23) ) + ( GND ) + ( \myVirtualToplevel|Add18~62\ )) +-- \myVirtualToplevel|Add18~58\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(23) ) + ( GND ) + ( \myVirtualToplevel|Add18~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(23), + cin => \myVirtualToplevel|Add18~62\, + sumout => \myVirtualToplevel|Add18~57_sumout\, + cout => \myVirtualToplevel|Add18~58\); + +-- Location: FF_X18_Y39_N41 +\myVirtualToplevel|SECOND_DOWN_TICK[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~57_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(23)); + +-- Location: MLABCELL_X18_Y39_N42 +\myVirtualToplevel|Add18~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~53_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(24) ) + ( GND ) + ( \myVirtualToplevel|Add18~58\ )) +-- \myVirtualToplevel|Add18~54\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(24) ) + ( GND ) + ( \myVirtualToplevel|Add18~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(24), + cin => \myVirtualToplevel|Add18~58\, + sumout => \myVirtualToplevel|Add18~53_sumout\, + cout => \myVirtualToplevel|Add18~54\); + +-- Location: FF_X18_Y39_N44 +\myVirtualToplevel|SECOND_DOWN_TICK[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~53_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(24)); + +-- Location: MLABCELL_X18_Y39_N45 +\myVirtualToplevel|Add18~101\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~101_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(25) ) + ( GND ) + ( \myVirtualToplevel|Add18~54\ )) +-- \myVirtualToplevel|Add18~102\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(25) ) + ( GND ) + ( \myVirtualToplevel|Add18~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(25), + cin => \myVirtualToplevel|Add18~54\, + sumout => \myVirtualToplevel|Add18~101_sumout\, + cout => \myVirtualToplevel|Add18~102\); + +-- Location: FF_X18_Y39_N46 +\myVirtualToplevel|SECOND_DOWN_TICK[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~101_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(25)); + +-- Location: MLABCELL_X18_Y39_N48 +\myVirtualToplevel|Add18~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~49_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(26) ) + ( GND ) + ( \myVirtualToplevel|Add18~102\ )) +-- \myVirtualToplevel|Add18~50\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(26) ) + ( GND ) + ( \myVirtualToplevel|Add18~102\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(26), + cin => \myVirtualToplevel|Add18~102\, + sumout => \myVirtualToplevel|Add18~49_sumout\, + cout => \myVirtualToplevel|Add18~50\); + +-- Location: FF_X18_Y39_N49 +\myVirtualToplevel|SECOND_DOWN_TICK[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~49_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(26)); + +-- Location: MLABCELL_X18_Y39_N51 +\myVirtualToplevel|Add18~97\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add18~97_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(27) ) + ( GND ) + ( \myVirtualToplevel|Add18~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(27), + cin => \myVirtualToplevel|Add18~50\, + sumout => \myVirtualToplevel|Add18~97_sumout\); + +-- Location: FF_X18_Y39_N53 +\myVirtualToplevel|SECOND_DOWN_TICK[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~97_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(27)); + +-- Location: MLABCELL_X18_Y40_N30 +\myVirtualToplevel|Equal35~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal35~6_combout\ = ( !\myVirtualToplevel|SECOND_DOWN_TICK\(25) & ( (!\myVirtualToplevel|SECOND_DOWN_TICK\(27) & (\myVirtualToplevel|SECOND_DOWN_TICK\(6) & \myVirtualToplevel|SECOND_DOWN_TICK\(7))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(27), + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(6), + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(7), + dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(25), + combout => \myVirtualToplevel|Equal35~6_combout\); + +-- Location: FF_X18_Y39_N7 +\myVirtualToplevel|SECOND_DOWN_TICK[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~45_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(12)); + +-- Location: FF_X18_Y39_N16 +\myVirtualToplevel|SECOND_DOWN_TICK[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~33_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(15)); + +-- Location: MLABCELL_X18_Y39_N54 +\myVirtualToplevel|Equal35~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal35~1_combout\ = ( \myVirtualToplevel|SECOND_DOWN_TICK\(13) & ( (\myVirtualToplevel|SECOND_DOWN_TICK\(14) & (!\myVirtualToplevel|SECOND_DOWN_TICK\(12) & \myVirtualToplevel|SECOND_DOWN_TICK\(15))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000001100000000000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(14), + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(12), + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(15), + dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(13), + combout => \myVirtualToplevel|Equal35~1_combout\); + +-- Location: FF_X18_Y39_N19 +\myVirtualToplevel|SECOND_DOWN_TICK[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK\(16)); + +-- Location: MLABCELL_X18_Y39_N57 +\myVirtualToplevel|Equal35~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal35~0_combout\ = ( \myVirtualToplevel|SECOND_DOWN_TICK\(21) & ( (\myVirtualToplevel|SECOND_DOWN_TICK\(18) & (\myVirtualToplevel|SECOND_DOWN_TICK\(20) & \myVirtualToplevel|SECOND_DOWN_TICK\(16))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(18), + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(20), + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(16), + dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(21), + combout => \myVirtualToplevel|Equal35~0_combout\); + +-- Location: LABCELL_X17_Y39_N27 +\myVirtualToplevel|Equal35~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal35~2_combout\ = ( \myVirtualToplevel|Equal35~0_combout\ & ( !\myVirtualToplevel|SECOND_DOWN_TICK\(10) & ( (!\myVirtualToplevel|SECOND_DOWN_TICK\(19) & (\myVirtualToplevel|Equal35~1_combout\ & +-- (!\myVirtualToplevel|SECOND_DOWN_TICK\(17) & !\myVirtualToplevel|SECOND_DOWN_TICK\(11)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(19), + datab => \myVirtualToplevel|ALT_INV_Equal35~1_combout\, + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(17), + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(11), + datae => \myVirtualToplevel|ALT_INV_Equal35~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(10), + combout => \myVirtualToplevel|Equal35~2_combout\); + +-- Location: MLABCELL_X18_Y40_N39 +\myVirtualToplevel|Equal35~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal35~4_combout\ = ( \myVirtualToplevel|SECOND_DOWN_TICK\(5) & ( (!\myVirtualToplevel|SECOND_DOWN_TICK\(8) & (\myVirtualToplevel|SECOND_DOWN_TICK\(4) & !\myVirtualToplevel|SECOND_DOWN_TICK\(9))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010000000000000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(8), + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(4), + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(9), + dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(5), + combout => \myVirtualToplevel|Equal35~4_combout\); + +-- Location: MLABCELL_X18_Y40_N36 +\myVirtualToplevel|Equal35~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal35~5_combout\ = ( \myVirtualToplevel|SECOND_DOWN_TICK\(2) & ( (\myVirtualToplevel|SECOND_DOWN_TICK\(3) & (\myVirtualToplevel|SECOND_DOWN_TICK\(0) & \myVirtualToplevel|SECOND_DOWN_TICK\(1))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(3), + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(0), + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(1), + dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(2), + combout => \myVirtualToplevel|Equal35~5_combout\); + +-- Location: FF_X18_Y39_N40 +\myVirtualToplevel|SECOND_DOWN_TICK[23]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add18~57_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal35~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_TICK[23]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y40_N33 +\myVirtualToplevel|Equal35~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal35~3_combout\ = ( \myVirtualToplevel|SECOND_DOWN_TICK\(24) & ( (\myVirtualToplevel|SECOND_DOWN_TICK\(22) & (\myVirtualToplevel|SECOND_DOWN_TICK[23]~DUPLICATE_q\ & \myVirtualToplevel|SECOND_DOWN_TICK\(26))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(22), + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[23]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(26), + dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(24), + combout => \myVirtualToplevel|Equal35~3_combout\); + +-- Location: MLABCELL_X18_Y40_N54 +\myVirtualToplevel|Equal35~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal35~7_combout\ = ( \myVirtualToplevel|Equal35~5_combout\ & ( \myVirtualToplevel|Equal35~3_combout\ & ( (\myVirtualToplevel|Equal35~6_combout\ & (\myVirtualToplevel|Equal35~2_combout\ & \myVirtualToplevel|Equal35~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_Equal35~6_combout\, + datac => \myVirtualToplevel|ALT_INV_Equal35~2_combout\, + datad => \myVirtualToplevel|ALT_INV_Equal35~4_combout\, + datae => \myVirtualToplevel|ALT_INV_Equal35~5_combout\, + dataf => \myVirtualToplevel|ALT_INV_Equal35~3_combout\, + combout => \myVirtualToplevel|Equal35~7_combout\); + +-- Location: LABCELL_X12_Y12_N42 +\myVirtualToplevel|SECOND_DOWN_COUNTER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\ = ( \myVirtualToplevel|Equal36~0_combout\ & ( \myVirtualToplevel|Equal35~7_combout\ & ( (!\myVirtualToplevel|SECOND_DOWN_COUNTER\(6) & (!\myVirtualToplevel|SECOND_DOWN_COUNTER\(5) & +-- \myVirtualToplevel|Equal36~1_combout\)) ) ) ) # ( \myVirtualToplevel|Equal36~0_combout\ & ( !\myVirtualToplevel|Equal35~7_combout\ ) ) # ( !\myVirtualToplevel|Equal36~0_combout\ & ( !\myVirtualToplevel|Equal35~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000100000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(6), + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(5), + datac => \myVirtualToplevel|ALT_INV_Equal36~1_combout\, + datae => \myVirtualToplevel|ALT_INV_Equal36~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_Equal35~7_combout\, + combout => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\); + +-- Location: FF_X12_Y12_N2 +\myVirtualToplevel|SECOND_DOWN_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~41_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(0)); + +-- Location: LABCELL_X12_Y12_N3 +\myVirtualToplevel|Add19~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add19~45_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~42\ )) +-- \myVirtualToplevel|Add19~46\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[1]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add19~42\, + sumout => \myVirtualToplevel|Add19~45_sumout\, + cout => \myVirtualToplevel|Add19~46\); + +-- Location: FF_X12_Y12_N5 +\myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~45_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y12_N6 +\myVirtualToplevel|Add19~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add19~37_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add19~46\ )) +-- \myVirtualToplevel|Add19~38\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add19~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(2), + cin => \myVirtualToplevel|Add19~46\, + sumout => \myVirtualToplevel|Add19~37_sumout\, + cout => \myVirtualToplevel|Add19~38\); + +-- Location: FF_X12_Y12_N7 +\myVirtualToplevel|SECOND_DOWN_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~37_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(2)); + +-- Location: LABCELL_X12_Y12_N9 +\myVirtualToplevel|Add19~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add19~33_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~38\ )) +-- \myVirtualToplevel|Add19~34\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add19~38\, + sumout => \myVirtualToplevel|Add19~33_sumout\, + cout => \myVirtualToplevel|Add19~34\); + +-- Location: FF_X12_Y12_N11 +\myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~33_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y12_N12 +\myVirtualToplevel|Add19~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add19~1_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add19~34\ )) +-- \myVirtualToplevel|Add19~2\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add19~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(4), + cin => \myVirtualToplevel|Add19~34\, + sumout => \myVirtualToplevel|Add19~1_sumout\, + cout => \myVirtualToplevel|Add19~2\); + +-- Location: FF_X12_Y12_N13 +\myVirtualToplevel|SECOND_DOWN_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~1_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(4)); + +-- Location: LABCELL_X12_Y12_N15 +\myVirtualToplevel|Add19~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add19~5_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add19~2\ )) +-- \myVirtualToplevel|Add19~6\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add19~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(5), + cin => \myVirtualToplevel|Add19~2\, + sumout => \myVirtualToplevel|Add19~5_sumout\, + cout => \myVirtualToplevel|Add19~6\); + +-- Location: FF_X12_Y12_N17 +\myVirtualToplevel|SECOND_DOWN_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~5_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(5)); + +-- Location: FF_X12_Y12_N20 +\myVirtualToplevel|SECOND_DOWN_COUNTER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~21_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(6)); + +-- Location: MLABCELL_X18_Y10_N0 +\myVirtualToplevel|Add16~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~69_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|Add16~70\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(0), + cin => GND, + sumout => \myVirtualToplevel|Add16~69_sumout\, + cout => \myVirtualToplevel|Add16~70\); + +-- Location: FF_X18_Y10_N1 +\myVirtualToplevel|MILLISEC_UP_TICK[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~69_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(0)); + +-- Location: FF_X18_Y10_N11 +\myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~57_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y10_N3 +\myVirtualToplevel|Add16~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~65_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add16~70\ )) +-- \myVirtualToplevel|Add16~66\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add16~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[1]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add16~70\, + sumout => \myVirtualToplevel|Add16~65_sumout\, + cout => \myVirtualToplevel|Add16~66\); + +-- Location: FF_X18_Y10_N5 +\myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~65_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y10_N6 +\myVirtualToplevel|Add16~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~61_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add16~66\ )) +-- \myVirtualToplevel|Add16~62\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add16~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(2), + cin => \myVirtualToplevel|Add16~66\, + sumout => \myVirtualToplevel|Add16~61_sumout\, + cout => \myVirtualToplevel|Add16~62\); + +-- Location: FF_X18_Y10_N7 +\myVirtualToplevel|MILLISEC_UP_TICK[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~61_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(2)); + +-- Location: MLABCELL_X18_Y10_N9 +\myVirtualToplevel|Add16~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~57_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add16~62\ )) +-- \myVirtualToplevel|Add16~58\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add16~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add16~62\, + sumout => \myVirtualToplevel|Add16~57_sumout\, + cout => \myVirtualToplevel|Add16~58\); + +-- Location: FF_X18_Y10_N10 +\myVirtualToplevel|MILLISEC_UP_TICK[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~57_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(3)); + +-- Location: FF_X18_Y10_N4 +\myVirtualToplevel|MILLISEC_UP_TICK[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~65_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(1)); + +-- Location: LABCELL_X19_Y10_N33 +\myVirtualToplevel|Equal34~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal34~3_combout\ = ( \myVirtualToplevel|MILLISEC_UP_TICK\(1) & ( (\myVirtualToplevel|MILLISEC_UP_TICK\(0) & (\myVirtualToplevel|MILLISEC_UP_TICK\(3) & \myVirtualToplevel|MILLISEC_UP_TICK\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(0), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(3), + datad => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(2), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(1), + combout => \myVirtualToplevel|Equal34~3_combout\); + +-- Location: MLABCELL_X18_Y10_N12 +\myVirtualToplevel|Add16~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~5_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add16~58\ )) +-- \myVirtualToplevel|Add16~6\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add16~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(4), + cin => \myVirtualToplevel|Add16~58\, + sumout => \myVirtualToplevel|Add16~5_sumout\, + cout => \myVirtualToplevel|Add16~6\); + +-- Location: FF_X18_Y10_N13 +\myVirtualToplevel|MILLISEC_UP_TICK[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(4)); + +-- Location: MLABCELL_X18_Y10_N15 +\myVirtualToplevel|Add16~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~1_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add16~6\ )) +-- \myVirtualToplevel|Add16~2\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add16~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add16~6\, + sumout => \myVirtualToplevel|Add16~1_sumout\, + cout => \myVirtualToplevel|Add16~2\); + +-- Location: FF_X18_Y10_N17 +\myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y10_N18 +\myVirtualToplevel|Add16~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~21_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add16~2\ )) +-- \myVirtualToplevel|Add16~22\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add16~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(6), + cin => \myVirtualToplevel|Add16~2\, + sumout => \myVirtualToplevel|Add16~21_sumout\, + cout => \myVirtualToplevel|Add16~22\); + +-- Location: FF_X18_Y10_N19 +\myVirtualToplevel|MILLISEC_UP_TICK[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(6)); + +-- Location: MLABCELL_X18_Y10_N21 +\myVirtualToplevel|Add16~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~53_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add16~22\ )) +-- \myVirtualToplevel|Add16~54\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add16~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(7), + cin => \myVirtualToplevel|Add16~22\, + sumout => \myVirtualToplevel|Add16~53_sumout\, + cout => \myVirtualToplevel|Add16~54\); + +-- Location: FF_X18_Y10_N23 +\myVirtualToplevel|MILLISEC_UP_TICK[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~53_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(7)); + +-- Location: MLABCELL_X18_Y10_N24 +\myVirtualToplevel|Add16~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~17_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(8) ) + ( GND ) + ( \myVirtualToplevel|Add16~54\ )) +-- \myVirtualToplevel|Add16~18\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(8) ) + ( GND ) + ( \myVirtualToplevel|Add16~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(8), + cin => \myVirtualToplevel|Add16~54\, + sumout => \myVirtualToplevel|Add16~17_sumout\, + cout => \myVirtualToplevel|Add16~18\); + +-- Location: FF_X18_Y10_N25 +\myVirtualToplevel|MILLISEC_UP_TICK[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(8)); + +-- Location: MLABCELL_X18_Y10_N27 +\myVirtualToplevel|Add16~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~49_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(9) ) + ( GND ) + ( \myVirtualToplevel|Add16~18\ )) +-- \myVirtualToplevel|Add16~50\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(9) ) + ( GND ) + ( \myVirtualToplevel|Add16~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(9), + cin => \myVirtualToplevel|Add16~18\, + sumout => \myVirtualToplevel|Add16~49_sumout\, + cout => \myVirtualToplevel|Add16~50\); + +-- Location: FF_X18_Y10_N29 +\myVirtualToplevel|MILLISEC_UP_TICK[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~49_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(9)); + +-- Location: MLABCELL_X18_Y10_N30 +\myVirtualToplevel|Add16~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~45_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(10) ) + ( GND ) + ( \myVirtualToplevel|Add16~50\ )) +-- \myVirtualToplevel|Add16~46\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(10) ) + ( GND ) + ( \myVirtualToplevel|Add16~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(10), + cin => \myVirtualToplevel|Add16~50\, + sumout => \myVirtualToplevel|Add16~45_sumout\, + cout => \myVirtualToplevel|Add16~46\); + +-- Location: FF_X18_Y10_N32 +\myVirtualToplevel|MILLISEC_UP_TICK[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~45_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(10)); + +-- Location: MLABCELL_X18_Y10_N33 +\myVirtualToplevel|Add16~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~41_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(11) ) + ( GND ) + ( \myVirtualToplevel|Add16~46\ )) +-- \myVirtualToplevel|Add16~42\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(11) ) + ( GND ) + ( \myVirtualToplevel|Add16~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(11), + cin => \myVirtualToplevel|Add16~46\, + sumout => \myVirtualToplevel|Add16~41_sumout\, + cout => \myVirtualToplevel|Add16~42\); + +-- Location: FF_X18_Y10_N35 +\myVirtualToplevel|MILLISEC_UP_TICK[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~41_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(11)); + +-- Location: MLABCELL_X18_Y10_N36 +\myVirtualToplevel|Add16~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~37_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(12) ) + ( GND ) + ( \myVirtualToplevel|Add16~42\ )) +-- \myVirtualToplevel|Add16~38\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(12) ) + ( GND ) + ( \myVirtualToplevel|Add16~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(12), + cin => \myVirtualToplevel|Add16~42\, + sumout => \myVirtualToplevel|Add16~37_sumout\, + cout => \myVirtualToplevel|Add16~38\); + +-- Location: FF_X18_Y10_N38 +\myVirtualToplevel|MILLISEC_UP_TICK[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~37_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(12)); + +-- Location: MLABCELL_X18_Y10_N39 +\myVirtualToplevel|Add16~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~33_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(13) ) + ( GND ) + ( \myVirtualToplevel|Add16~38\ )) +-- \myVirtualToplevel|Add16~34\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(13) ) + ( GND ) + ( \myVirtualToplevel|Add16~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(13), + cin => \myVirtualToplevel|Add16~38\, + sumout => \myVirtualToplevel|Add16~33_sumout\, + cout => \myVirtualToplevel|Add16~34\); + +-- Location: FF_X18_Y10_N41 +\myVirtualToplevel|MILLISEC_UP_TICK[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~33_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(13)); + +-- Location: MLABCELL_X18_Y10_N42 +\myVirtualToplevel|Add16~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~29_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(14) ) + ( GND ) + ( \myVirtualToplevel|Add16~34\ )) +-- \myVirtualToplevel|Add16~30\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(14) ) + ( GND ) + ( \myVirtualToplevel|Add16~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(14), + cin => \myVirtualToplevel|Add16~34\, + sumout => \myVirtualToplevel|Add16~29_sumout\, + cout => \myVirtualToplevel|Add16~30\); + +-- Location: FF_X18_Y10_N44 +\myVirtualToplevel|MILLISEC_UP_TICK[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(14)); + +-- Location: MLABCELL_X18_Y10_N45 +\myVirtualToplevel|Add16~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~13_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(15) ) + ( GND ) + ( \myVirtualToplevel|Add16~30\ )) +-- \myVirtualToplevel|Add16~14\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(15) ) + ( GND ) + ( \myVirtualToplevel|Add16~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(15), + cin => \myVirtualToplevel|Add16~30\, + sumout => \myVirtualToplevel|Add16~13_sumout\, + cout => \myVirtualToplevel|Add16~14\); + +-- Location: FF_X18_Y10_N46 +\myVirtualToplevel|MILLISEC_UP_TICK[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(15)); + +-- Location: MLABCELL_X18_Y10_N48 +\myVirtualToplevel|Add16~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~9_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(16) ) + ( GND ) + ( \myVirtualToplevel|Add16~14\ )) +-- \myVirtualToplevel|Add16~10\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(16) ) + ( GND ) + ( \myVirtualToplevel|Add16~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(16), + cin => \myVirtualToplevel|Add16~14\, + sumout => \myVirtualToplevel|Add16~9_sumout\, + cout => \myVirtualToplevel|Add16~10\); + +-- Location: FF_X18_Y10_N49 +\myVirtualToplevel|MILLISEC_UP_TICK[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(16)); + +-- Location: MLABCELL_X18_Y10_N51 +\myVirtualToplevel|Add16~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add16~25_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(17) ) + ( GND ) + ( \myVirtualToplevel|Add16~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(17), + cin => \myVirtualToplevel|Add16~10\, + sumout => \myVirtualToplevel|Add16~25_sumout\); + +-- Location: FF_X18_Y10_N53 +\myVirtualToplevel|MILLISEC_UP_TICK[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(17)); + +-- Location: MLABCELL_X18_Y10_N54 +\myVirtualToplevel|Equal34~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal34~0_combout\ = ( !\myVirtualToplevel|MILLISEC_UP_TICK\(13) & ( (!\myVirtualToplevel|MILLISEC_UP_TICK\(14) & (!\myVirtualToplevel|MILLISEC_UP_TICK\(17) & !\myVirtualToplevel|MILLISEC_UP_TICK\(12))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(14), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(17), + datad => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(12), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(13), + combout => \myVirtualToplevel|Equal34~0_combout\); + +-- Location: MLABCELL_X18_Y10_N57 +\myVirtualToplevel|Equal34~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal34~1_combout\ = ( !\myVirtualToplevel|MILLISEC_UP_TICK\(11) & ( (\myVirtualToplevel|MILLISEC_UP_TICK\(9) & (\myVirtualToplevel|MILLISEC_UP_TICK\(10) & \myVirtualToplevel|MILLISEC_UP_TICK\(7))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(9), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(10), + datad => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(7), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(11), + combout => \myVirtualToplevel|Equal34~1_combout\); + +-- Location: LABCELL_X19_Y10_N24 +\myVirtualToplevel|Equal34~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal34~2_combout\ = ( !\myVirtualToplevel|MILLISEC_UP_TICK\(8) & ( \myVirtualToplevel|MILLISEC_UP_TICK\(15) & ( (\myVirtualToplevel|Equal34~0_combout\ & (!\myVirtualToplevel|MILLISEC_UP_TICK\(6) & +-- (\myVirtualToplevel|MILLISEC_UP_TICK\(16) & \myVirtualToplevel|Equal34~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal34~0_combout\, + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(6), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(16), + datad => \myVirtualToplevel|ALT_INV_Equal34~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(8), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(15), + combout => \myVirtualToplevel|Equal34~2_combout\); + +-- Location: FF_X18_Y10_N16 +\myVirtualToplevel|MILLISEC_UP_TICK[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add16~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal34~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_TICK\(5)); + +-- Location: LABCELL_X19_Y10_N30 +\myVirtualToplevel|Equal34~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal34~4_combout\ = ( !\myVirtualToplevel|MILLISEC_UP_TICK\(5) & ( (\myVirtualToplevel|Equal34~3_combout\ & (\myVirtualToplevel|Equal34~2_combout\ & \myVirtualToplevel|MILLISEC_UP_TICK\(4))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal34~3_combout\, + datac => \myVirtualToplevel|ALT_INV_Equal34~2_combout\, + datad => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(4), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(5), + combout => \myVirtualToplevel|Equal34~4_combout\); + +-- Location: LABCELL_X16_Y13_N27 +\myVirtualToplevel|Equal3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal3~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + combout => \myVirtualToplevel|Equal3~0_combout\); + +-- Location: LABCELL_X12_Y11_N0 +\myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\ = ( \myVirtualToplevel|Equal34~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) ) # ( \myVirtualToplevel|Equal34~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) ) # ( +-- !\myVirtualToplevel|Equal34~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (\myVirtualToplevel|Equal3~0_combout\ & (\myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011111111111111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datae => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + combout => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\); + +-- Location: FF_X17_Y11_N20 +\myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~69_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y11_N0 +\myVirtualToplevel|Add17~125\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~125_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|Add17~126\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(0), + cin => GND, + sumout => \myVirtualToplevel|Add17~125_sumout\, + cout => \myVirtualToplevel|Add17~126\); + +-- Location: FF_X17_Y11_N2 +\myVirtualToplevel|MILLISEC_UP_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~125_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(0)); + +-- Location: LABCELL_X17_Y11_N3 +\myVirtualToplevel|Add17~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~89_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add17~126\ )) +-- \myVirtualToplevel|Add17~90\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add17~126\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(1), + cin => \myVirtualToplevel|Add17~126\, + sumout => \myVirtualToplevel|Add17~89_sumout\, + cout => \myVirtualToplevel|Add17~90\); + +-- Location: FF_X17_Y11_N5 +\myVirtualToplevel|MILLISEC_UP_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~89_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(1)); + +-- Location: LABCELL_X17_Y11_N6 +\myVirtualToplevel|Add17~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~85_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add17~90\ )) +-- \myVirtualToplevel|Add17~86\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add17~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(2), + cin => \myVirtualToplevel|Add17~90\, + sumout => \myVirtualToplevel|Add17~85_sumout\, + cout => \myVirtualToplevel|Add17~86\); + +-- Location: FF_X17_Y11_N8 +\myVirtualToplevel|MILLISEC_UP_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~85_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(2)); + +-- Location: LABCELL_X17_Y11_N9 +\myVirtualToplevel|Add17~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~81_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(3) ) + ( GND ) + ( \myVirtualToplevel|Add17~86\ )) +-- \myVirtualToplevel|Add17~82\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(3) ) + ( GND ) + ( \myVirtualToplevel|Add17~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(3), + cin => \myVirtualToplevel|Add17~86\, + sumout => \myVirtualToplevel|Add17~81_sumout\, + cout => \myVirtualToplevel|Add17~82\); + +-- Location: FF_X17_Y11_N11 +\myVirtualToplevel|MILLISEC_UP_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~81_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(3)); + +-- Location: LABCELL_X17_Y11_N12 +\myVirtualToplevel|Add17~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~49_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~82\ )) +-- \myVirtualToplevel|Add17~50\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[4]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add17~82\, + sumout => \myVirtualToplevel|Add17~49_sumout\, + cout => \myVirtualToplevel|Add17~50\); + +-- Location: FF_X17_Y11_N14 +\myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~49_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y11_N15 +\myVirtualToplevel|Add17~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~53_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(5) ) + ( GND ) + ( \myVirtualToplevel|Add17~50\ )) +-- \myVirtualToplevel|Add17~54\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(5) ) + ( GND ) + ( \myVirtualToplevel|Add17~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(5), + cin => \myVirtualToplevel|Add17~50\, + sumout => \myVirtualToplevel|Add17~53_sumout\, + cout => \myVirtualToplevel|Add17~54\); + +-- Location: FF_X17_Y11_N17 +\myVirtualToplevel|MILLISEC_UP_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~53_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(5)); + +-- Location: LABCELL_X17_Y11_N18 +\myVirtualToplevel|Add17~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~69_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~54\ )) +-- \myVirtualToplevel|Add17~70\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add17~54\, + sumout => \myVirtualToplevel|Add17~69_sumout\, + cout => \myVirtualToplevel|Add17~70\); + +-- Location: FF_X17_Y11_N19 +\myVirtualToplevel|MILLISEC_UP_COUNTER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~69_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(6)); + +-- Location: MLABCELL_X13_Y12_N0 +\myVirtualToplevel|Add13~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~89_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|Add13~90\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(0), + cin => GND, + sumout => \myVirtualToplevel|Add13~89_sumout\, + cout => \myVirtualToplevel|Add13~90\); + +-- Location: LABCELL_X12_Y11_N27 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\ = ( \myVirtualToplevel|Equal3~0_combout\ & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ & ( (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\) # +-- (\myVirtualToplevel|UART1|Equal7~0_combout\) ) ) ) # ( !\myVirtualToplevel|Equal3~0_combout\ & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ & ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\ ) ) ) # ( \myVirtualToplevel|Equal3~0_combout\ & +-- ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ & ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\ ) ) ) # ( !\myVirtualToplevel|Equal3~0_combout\ & ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ & ( +-- !\myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101010101010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~0_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\, + datae => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\, + combout => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\); + +-- Location: FF_X13_Y12_N2 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~89_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(0)); + +-- Location: MLABCELL_X13_Y12_N3 +\myVirtualToplevel|Add13~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~93_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add13~90\ )) +-- \myVirtualToplevel|Add13~94\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add13~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(1), + cin => \myVirtualToplevel|Add13~90\, + sumout => \myVirtualToplevel|Add13~93_sumout\, + cout => \myVirtualToplevel|Add13~94\); + +-- Location: FF_X13_Y12_N5 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~93_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(1)); + +-- Location: MLABCELL_X13_Y12_N6 +\myVirtualToplevel|Add13~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~85_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~94\ )) +-- \myVirtualToplevel|Add13~86\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~94\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add13~94\, + sumout => \myVirtualToplevel|Add13~85_sumout\, + cout => \myVirtualToplevel|Add13~86\); + +-- Location: FF_X13_Y12_N8 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~85_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\); + +-- Location: MLABCELL_X13_Y12_N9 +\myVirtualToplevel|Add13~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~81_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add13~86\ )) +-- \myVirtualToplevel|Add13~82\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add13~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(3), + cin => \myVirtualToplevel|Add13~86\, + sumout => \myVirtualToplevel|Add13~81_sumout\, + cout => \myVirtualToplevel|Add13~82\); + +-- Location: FF_X13_Y12_N11 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~81_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(3)); + +-- Location: MLABCELL_X13_Y12_N12 +\myVirtualToplevel|Add13~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~49_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add13~82\ )) +-- \myVirtualToplevel|Add13~50\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add13~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(4), + cin => \myVirtualToplevel|Add13~82\, + sumout => \myVirtualToplevel|Add13~49_sumout\, + cout => \myVirtualToplevel|Add13~50\); + +-- Location: FF_X13_Y12_N14 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~49_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(4)); + +-- Location: MLABCELL_X13_Y12_N15 +\myVirtualToplevel|Add13~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~53_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add13~50\ )) +-- \myVirtualToplevel|Add13~54\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add13~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(5), + cin => \myVirtualToplevel|Add13~50\, + sumout => \myVirtualToplevel|Add13~53_sumout\, + cout => \myVirtualToplevel|Add13~54\); + +-- Location: FF_X13_Y12_N17 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~53_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(5)); + +-- Location: MLABCELL_X13_Y12_N18 +\myVirtualToplevel|Add13~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~69_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add13~54\ )) +-- \myVirtualToplevel|Add13~70\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add13~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(6), + cin => \myVirtualToplevel|Add13~54\, + sumout => \myVirtualToplevel|Add13~69_sumout\, + cout => \myVirtualToplevel|Add13~70\); + +-- Location: MLABCELL_X13_Y12_N21 +\myVirtualToplevel|Add13~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~73_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add13~70\ )) +-- \myVirtualToplevel|Add13~74\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add13~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(7), + cin => \myVirtualToplevel|Add13~70\, + sumout => \myVirtualToplevel|Add13~73_sumout\, + cout => \myVirtualToplevel|Add13~74\); + +-- Location: FF_X13_Y12_N22 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~73_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(7)); + +-- Location: MLABCELL_X13_Y12_N24 +\myVirtualToplevel|Add13~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~77_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add13~74\ )) +-- \myVirtualToplevel|Add13~78\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add13~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(8), + cin => \myVirtualToplevel|Add13~74\, + sumout => \myVirtualToplevel|Add13~77_sumout\, + cout => \myVirtualToplevel|Add13~78\); + +-- Location: FF_X13_Y12_N26 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~77_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(8)); + +-- Location: MLABCELL_X13_Y12_N27 +\myVirtualToplevel|Add13~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~57_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add13~78\ )) +-- \myVirtualToplevel|Add13~58\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add13~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(9), + cin => \myVirtualToplevel|Add13~78\, + sumout => \myVirtualToplevel|Add13~57_sumout\, + cout => \myVirtualToplevel|Add13~58\); + +-- Location: FF_X13_Y12_N28 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~57_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(9)); + +-- Location: MLABCELL_X13_Y11_N0 +\myVirtualToplevel|Add13~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~61_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~58\ )) +-- \myVirtualToplevel|Add13~62\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add13~58\, + sumout => \myVirtualToplevel|Add13~61_sumout\, + cout => \myVirtualToplevel|Add13~62\); + +-- Location: FF_X13_Y11_N2 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~61_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\); + +-- Location: MLABCELL_X13_Y11_N3 +\myVirtualToplevel|Add13~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~65_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add13~62\ )) +-- \myVirtualToplevel|Add13~66\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add13~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(11), + cin => \myVirtualToplevel|Add13~62\, + sumout => \myVirtualToplevel|Add13~65_sumout\, + cout => \myVirtualToplevel|Add13~66\); + +-- Location: FF_X13_Y11_N5 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~65_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(11)); + +-- Location: MLABCELL_X13_Y11_N6 +\myVirtualToplevel|Add13~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~33_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~66\ )) +-- \myVirtualToplevel|Add13~34\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add13~66\, + sumout => \myVirtualToplevel|Add13~33_sumout\, + cout => \myVirtualToplevel|Add13~34\); + +-- Location: FF_X13_Y11_N8 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~33_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\); + +-- Location: MLABCELL_X13_Y11_N9 +\myVirtualToplevel|Add13~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~37_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~34\ )) +-- \myVirtualToplevel|Add13~38\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add13~34\, + sumout => \myVirtualToplevel|Add13~37_sumout\, + cout => \myVirtualToplevel|Add13~38\); + +-- Location: FF_X13_Y11_N11 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~37_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\); + +-- Location: MLABCELL_X13_Y11_N12 +\myVirtualToplevel|Add13~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~41_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~38\ )) +-- \myVirtualToplevel|Add13~42\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add13~38\, + sumout => \myVirtualToplevel|Add13~41_sumout\, + cout => \myVirtualToplevel|Add13~42\); + +-- Location: FF_X13_Y11_N14 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~41_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\); + +-- Location: MLABCELL_X13_Y11_N15 +\myVirtualToplevel|Add13~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~45_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(15) ) + ( VCC ) + ( \myVirtualToplevel|Add13~42\ )) +-- \myVirtualToplevel|Add13~46\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(15) ) + ( VCC ) + ( \myVirtualToplevel|Add13~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(15), + cin => \myVirtualToplevel|Add13~42\, + sumout => \myVirtualToplevel|Add13~45_sumout\, + cout => \myVirtualToplevel|Add13~46\); + +-- Location: FF_X13_Y11_N17 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~45_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(15)); + +-- Location: MLABCELL_X13_Y11_N18 +\myVirtualToplevel|Add13~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~1_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(16) ) + ( VCC ) + ( \myVirtualToplevel|Add13~46\ )) +-- \myVirtualToplevel|Add13~2\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(16) ) + ( VCC ) + ( \myVirtualToplevel|Add13~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(16), + cin => \myVirtualToplevel|Add13~46\, + sumout => \myVirtualToplevel|Add13~1_sumout\, + cout => \myVirtualToplevel|Add13~2\); + +-- Location: FF_X13_Y11_N20 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~1_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(16)); + +-- Location: MLABCELL_X13_Y11_N21 +\myVirtualToplevel|Add13~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~21_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~2\ )) +-- \myVirtualToplevel|Add13~22\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add13~2\, + sumout => \myVirtualToplevel|Add13~21_sumout\, + cout => \myVirtualToplevel|Add13~22\); + +-- Location: FF_X9_Y18_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_NEW_REG1614\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1615\); + +-- Location: LABCELL_X24_Y24_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\); + +-- Location: LABCELL_X29_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\); + +-- Location: FF_X35_Y21_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1694~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y28_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\); + +-- Location: LABCELL_X29_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\); + +-- Location: MLABCELL_X28_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\); + +-- Location: LABCELL_X32_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\); + +-- Location: MLABCELL_X23_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\); + +-- Location: LABCELL_X32_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000000000000000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\); + +-- Location: LABCELL_X21_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\); + +-- Location: MLABCELL_X23_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\); + +-- Location: FF_X18_Y14_N8 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0)); + +-- Location: LABCELL_X17_Y14_N18 +\myVirtualToplevel|LessThan0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|LessThan0~1_combout\ = ( \myVirtualToplevel|LessThan0~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(23), + dataf => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\, + combout => \myVirtualToplevel|LessThan0~1_combout\); + +-- Location: FF_X13_Y14_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~1_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0)); + +-- Location: MLABCELL_X13_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector216~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~0_combout\); + +-- Location: MLABCELL_X13_Y14_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector216~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector216~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110111000001010011011100000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector216~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr116~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~1_combout\); + +-- Location: FF_X13_Y14_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~1_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\); + +-- Location: MLABCELL_X13_Y14_N39 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101011111010101010101111101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0_combout\); + +-- Location: MLABCELL_X23_Y14_N21 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node[0]\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0) = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0_combout\ & ( (\myVirtualToplevel|BRAM_WREN~1_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) # ((\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & \myVirtualToplevel|LessThan3~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000001000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\, + datab => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\, + datac => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM0_WREN~0_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0)); + +-- Location: FF_X16_Y14_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(8)); + +-- Location: M10K_X22_Y14_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011513680414814204E7226F0380A08C0442000835B00000020039320000000301590824C1042810A509248008A96310001001040FFFFFFDB0056A404000E00000C4014494C540A40207840488102440900770955330A72AB2A610F3A2CE60602924497424964143AE0AA43138BAA", + mem_init2 => "067C11C0022E13C9C7909383CDA54530B03ECE3C90CE0EB89C200CF84E380400A4B550F11813B42D093DA85123AB907D5B24182C819D05BE046103E40504821FDA8A304554AA8304AA554182D0147066090D2C05618A1380C81C0BD4AE9277CD5835D5C924840801817518498DE378790655D46E856FFD63E92E767F7A7599C6D9F28E65410BC01DEE8090C31CB7481CB71421E1D686425928A2001A700088A41A309B44CB16A902A3146042B4CF32D54A462254C80D2A4A38A9034C1480CFE470C17ECA249404F0830033F4804CE050001CAC810D9749009393EDA8A4800008C22513011809A56345234F48440AF1A8809E408882195C2CF03A36960110670A", + mem_init1 => "42298895DB70147596E26AEC0C8CC2001FE0707AC90A74BAE41C84A383532880785073896BE24E8408566692213641D9D449A6A419ACB025A348D23A1ACD45D504E040461B5B49E2D7198A874B968C53BD558BF0500381141C293FD176985E14854B0A420DEBC5F282EC8CDDD484B7175ABB4C926A388293C0130841D50181419F9F91E3BAC1238144D8A04D8F06F2138F49427F6194C128C2C9434C341EA6E883565D1C36AD2353BF43D091BA443C9E13C604900D000190136B184CA9AA98151F941F1511200012328D84C369B857FC1B00517C52A001533E0CB39ADD3650ACB118329E73D5C32A8423566E050D3C1C427252E307F6125DE404504020EF8905", + mem_init0 => "9044D120477E118C6003627BBF12C62904064C842110961A819E29470AF0D8590054080050881A4EEF2AE8EB180808DDBCB089B525BA0B607BA66A4F48EED4043CE058A26A5C12102C041B302417440118C8E49257039BAEF5C3870E1C30E1F8433080CB98C219730843AE64C6130984CA0C81E8060BCCC810D1760341408377BA1795567610A41095553F6DB71B68D4A081F0EC01C1E66F7A285C0A1002D110A09809610BA0000040880055448008881100A420468CB2802B00340000000000000000000000000002C005000B003600FFFFFFFFFFFA4924936DB6DA492492FEFD000300010000162A000414180300000C0C1A0707010100032E031E7A180001", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 1, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 1, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\); + +-- Location: M10K_X11_Y14_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 1, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 1, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X18_Y14_N51 +\myVirtualToplevel|MEM_DATA_READ[1]~64\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[1]~64_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\ & ( (\myVirtualToplevel|LessThan0~1_combout\ & +-- ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0)))) ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\ & ( (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0) & (\myVirtualToplevel|LessThan0~1_combout\ & +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110000000011000011110000001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datac => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[1]~64_combout\); + +-- Location: MLABCELL_X18_Y14_N30 +\myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\ = ( \myVirtualToplevel|MEM_DATA_READ[1]~63_combout\ & ( (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ & \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\)) # +-- (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[1]~64_combout\) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[1]~63_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[1]~64_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101110111010101010111011101011111011111110101111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~64_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]~35_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~63_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\); + +-- Location: LABCELL_X10_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( \myVirtualToplevel|MEM_BUSY~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & +-- ( \myVirtualToplevel|MEM_BUSY~1_combout\ ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( !\myVirtualToplevel|MEM_BUSY~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( +-- !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( (!\myVirtualToplevel|RESET_n~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\); + +-- Location: MLABCELL_X9_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_OTERM3217\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000111000000000100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~65_Duplicate_152\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_OTERM3217\); + +-- Location: FF_X9_Y18_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_OTERM3217\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1)); + +-- Location: LABCELL_X21_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\ = ( \myVirtualToplevel|MEM_BUSY~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) # ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & ( ((!\myVirtualToplevel|RESET_n~q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) ) ) ) # ( +-- \myVirtualToplevel|MEM_BUSY~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) # ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111011111110111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datab => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\); + +-- Location: FF_X16_Y14_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6)); + +-- Location: M10K_X11_Y16_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 2, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 2, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X23_Y9_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]~feeder_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]~feeder_combout\); + +-- Location: LABCELL_X26_Y7_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0) & (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0) & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\ & (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010111001011111010100000000000000001100010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[9]~DUPLICATE_q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0), + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0_combout\); + +-- Location: LABCELL_X25_Y7_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\ & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100111111111100100011001000110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector63~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnData_v~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~1_combout\); + +-- Location: FF_X25_Y7_N55 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~1_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\); + +-- Location: LABCELL_X24_Y7_N3 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnData_v~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o[3]~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\); + +-- Location: FF_X23_Y9_N13 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]~feeder_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(2)); + +-- Location: FF_X18_Y9_N44 +\myVirtualToplevel|SD_ADDR[0][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][2]~q\); + +-- Location: MLABCELL_X18_Y9_N57 +\myVirtualToplevel|Mux81~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux81~0_combout\ = ( \myVirtualToplevel|SD_ADDR[0][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\)))) ) ) # ( +-- !\myVirtualToplevel|SD_ADDR[0][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000101000000110000010111110011000001011111001100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_SD_ADDR[0][2]~q\, + combout => \myVirtualToplevel|Mux81~0_combout\); + +-- Location: FF_X18_Y9_N58 +\myVirtualToplevel|IO_DATA_READ_SD[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux81~0_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(2)); + +-- Location: LABCELL_X16_Y14_N0 +\myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127_BDD9128\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(11), + combout => \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127_BDD9128\); + +-- Location: LABCELL_X16_Y14_N18 +\myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125_BDD9126\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9)) # (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011111111111111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125_BDD9126\); + +-- Location: LABCELL_X17_Y14_N30 +\myVirtualToplevel|MEM_DATA_READ[2]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ = ( \myVirtualToplevel|IO_SELECT~2_combout\ & ( \myVirtualToplevel|SD_CS~0_combout\ & ( ((!\myVirtualToplevel|IO_SELECT~0_combout\) # (!\myVirtualToplevel|IO_SELECT~1_combout\)) # +-- (\myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127_BDD9128\) ) ) ) # ( !\myVirtualToplevel|IO_SELECT~2_combout\ & ( \myVirtualToplevel|SD_CS~0_combout\ ) ) # ( \myVirtualToplevel|IO_SELECT~2_combout\ & ( !\myVirtualToplevel|SD_CS~0_combout\ & ( +-- ((!\myVirtualToplevel|IO_SELECT~0_combout\) # ((!\myVirtualToplevel|IO_SELECT~1_combout\) # (\myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125_BDD9126\))) # (\myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127_BDD9128\) ) ) ) # ( +-- !\myVirtualToplevel|IO_SELECT~2_combout\ & ( !\myVirtualToplevel|SD_CS~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111011111111111111111111111111111110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_RESYN9127_BDD9128\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_RESYN9125_BDD9126\, + datae => \myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_SD_CS~0_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[2]~34_combout\); + +-- Location: LABCELL_X14_Y9_N18 +\myVirtualToplevel|IO_DATA_READ[0]~70\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[0]~70_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (!\myVirtualToplevel|TIMER0_CS~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) # ( +-- !\myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & !\myVirtualToplevel|TIMER0_CS~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100010001000100010001000100000001000000010000000100000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|IO_DATA_READ[0]~70_combout\); + +-- Location: FF_X10_Y5_N52 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(19)); + +-- Location: FF_X10_Y5_N19 +\myVirtualToplevel|UART0|RX_FIFO~20\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO~20_q\); + +-- Location: LABCELL_X10_Y5_N18 +\myVirtualToplevel|UART0|RX_DATA~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA~14_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\ & ( \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & +-- (\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ((\myVirtualToplevel|UART0|RX_FIFO~20_q\))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & +-- ((\myVirtualToplevel|UART0|RX_FIFO~20_q\))) ) ) ) # ( \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(19)) # +-- (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & +-- \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(19)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(19), + datac => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~20_q\, + datae => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA~14_combout\); + +-- Location: MLABCELL_X9_Y5_N0 +\myVirtualToplevel|UART0|RX_DATA[2]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA[2]~15_combout\ = ( \myVirtualToplevel|UART0|RX_DATA~14_combout\ & ( ((\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\ & \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(2)) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_DATA~14_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA\(2) & ((!\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\) # (!\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(2), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA~14_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA[2]~15_combout\); + +-- Location: FF_X9_Y5_N1 +\myVirtualToplevel|UART0|RX_DATA[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_DATA[2]~15_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_DATA\(2)); + +-- Location: LABCELL_X10_Y12_N0 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\ = ( \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\ ) # ( !\myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\ & \myVirtualToplevel|TIMER0_CS~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100000000000000010011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER~0_combout\, + datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + combout => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\); + +-- Location: FF_X10_Y12_N59 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~9_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(9)); + +-- Location: LABCELL_X10_Y12_N30 +\myVirtualToplevel|Add5~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add5~33_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|Add5~34\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(0), + cin => GND, + sumout => \myVirtualToplevel|Add5~33_sumout\, + cout => \myVirtualToplevel|Add5~34\); + +-- Location: FF_X10_Y12_N32 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~33_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0)); + +-- Location: LABCELL_X10_Y12_N33 +\myVirtualToplevel|Add5~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add5~37_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add5~34\ )) +-- \myVirtualToplevel|Add5~38\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add5~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(1), + cin => \myVirtualToplevel|Add5~34\, + sumout => \myVirtualToplevel|Add5~37_sumout\, + cout => \myVirtualToplevel|Add5~38\); + +-- Location: FF_X10_Y12_N34 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~37_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(1)); + +-- Location: LABCELL_X10_Y12_N36 +\myVirtualToplevel|Add5~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add5~29_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add5~38\ )) +-- \myVirtualToplevel|Add5~30\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add5~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(2), + cin => \myVirtualToplevel|Add5~38\, + sumout => \myVirtualToplevel|Add5~29_sumout\, + cout => \myVirtualToplevel|Add5~30\); + +-- Location: FF_X10_Y12_N38 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~29_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2)); + +-- Location: LABCELL_X10_Y12_N39 +\myVirtualToplevel|Add5~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add5~25_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(3) ) + ( GND ) + ( \myVirtualToplevel|Add5~30\ )) +-- \myVirtualToplevel|Add5~26\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(3) ) + ( GND ) + ( \myVirtualToplevel|Add5~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(3), + cin => \myVirtualToplevel|Add5~30\, + sumout => \myVirtualToplevel|Add5~25_sumout\, + cout => \myVirtualToplevel|Add5~26\); + +-- Location: FF_X10_Y12_N41 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~25_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(3)); + +-- Location: LABCELL_X10_Y12_N42 +\myVirtualToplevel|Add5~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add5~1_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) ) + ( GND ) + ( \myVirtualToplevel|Add5~26\ )) +-- \myVirtualToplevel|Add5~2\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) ) + ( GND ) + ( \myVirtualToplevel|Add5~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(4), + cin => \myVirtualToplevel|Add5~26\, + sumout => \myVirtualToplevel|Add5~1_sumout\, + cout => \myVirtualToplevel|Add5~2\); + +-- Location: FF_X10_Y12_N44 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~1_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(4)); + +-- Location: LABCELL_X10_Y12_N45 +\myVirtualToplevel|Add5~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add5~5_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(5) ) + ( GND ) + ( \myVirtualToplevel|Add5~2\ )) +-- \myVirtualToplevel|Add5~6\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(5) ) + ( GND ) + ( \myVirtualToplevel|Add5~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(5), + cin => \myVirtualToplevel|Add5~2\, + sumout => \myVirtualToplevel|Add5~5_sumout\, + cout => \myVirtualToplevel|Add5~6\); + +-- Location: LABCELL_X10_Y12_N48 +\myVirtualToplevel|Add5~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add5~13_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(6) ) + ( GND ) + ( \myVirtualToplevel|Add5~6\ )) +-- \myVirtualToplevel|Add5~14\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(6) ) + ( GND ) + ( \myVirtualToplevel|Add5~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(6), + cin => \myVirtualToplevel|Add5~6\, + sumout => \myVirtualToplevel|Add5~13_sumout\, + cout => \myVirtualToplevel|Add5~14\); + +-- Location: FF_X10_Y12_N49 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~13_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(6)); + +-- Location: LABCELL_X10_Y12_N51 +\myVirtualToplevel|Add5~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add5~17_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(7) ) + ( GND ) + ( \myVirtualToplevel|Add5~14\ )) +-- \myVirtualToplevel|Add5~18\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(7) ) + ( GND ) + ( \myVirtualToplevel|Add5~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(7), + cin => \myVirtualToplevel|Add5~14\, + sumout => \myVirtualToplevel|Add5~17_sumout\, + cout => \myVirtualToplevel|Add5~18\); + +-- Location: FF_X10_Y12_N52 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~17_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(7)); + +-- Location: LABCELL_X10_Y12_N54 +\myVirtualToplevel|Add5~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add5~21_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(8) ) + ( GND ) + ( \myVirtualToplevel|Add5~18\ )) +-- \myVirtualToplevel|Add5~22\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(8) ) + ( GND ) + ( \myVirtualToplevel|Add5~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(8), + cin => \myVirtualToplevel|Add5~18\, + sumout => \myVirtualToplevel|Add5~21_sumout\, + cout => \myVirtualToplevel|Add5~22\); + +-- Location: FF_X10_Y12_N56 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~21_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(8)); + +-- Location: LABCELL_X10_Y12_N57 +\myVirtualToplevel|Add5~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add5~9_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(9) ) + ( GND ) + ( \myVirtualToplevel|Add5~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(9), + cin => \myVirtualToplevel|Add5~22\, + sumout => \myVirtualToplevel|Add5~9_sumout\); + +-- Location: FF_X10_Y12_N58 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~9_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\); + +-- Location: FF_X10_Y12_N35 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~37_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y12_N21 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2_combout\ = ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) & ( (\myVirtualToplevel|RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\ & (!\myVirtualToplevel|RTC_MILLISEC_COUNTER\(3) & +-- \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(3), + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(2), + dataf => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(4), + combout => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2_combout\); + +-- Location: LABCELL_X10_Y12_N12 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ = ( \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2_combout\ & ( \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\ & ( (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1_combout\ & +-- (\myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\ & \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~1_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(0), + datae => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + combout => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\); + +-- Location: FF_X10_Y12_N46 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~5_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(5)); + +-- Location: FF_X10_Y12_N47 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~5_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\); + +-- Location: FF_X10_Y12_N50 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add5~13_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\, + sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y12_N18 +\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1_combout\ = ( \myVirtualToplevel|RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\ & (\myVirtualToplevel|RTC_MILLISEC_COUNTER\(8) & +-- \myVirtualToplevel|RTC_MILLISEC_COUNTER\(7))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(8), + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(7), + dataf => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1_combout\); + +-- Location: LABCELL_X10_Y10_N57 +\myVirtualToplevel|RTC_SECOND_COUNTER~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_SECOND_COUNTER~5_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & !\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\) ) ) # ( +-- !\myVirtualToplevel|RTC_SECOND_COUNTER\(0) & ( (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010111111111010101010000000001010101111111110101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\, + datae => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(0), + combout => \myVirtualToplevel|RTC_SECOND_COUNTER~5_combout\); + +-- Location: MLABCELL_X13_Y10_N15 +\myVirtualToplevel|RTC_SECOND_COUNTER[3]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\ = ( \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\ & ( \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ ) ) # ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\ & ( +-- \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ ) ) # ( \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\ & ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|TIMER0_CS~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + datae => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\, + combout => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\); + +-- Location: FF_X10_Y10_N59 +\myVirtualToplevel|RTC_SECOND_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_SECOND_COUNTER~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_SECOND_COUNTER\(0)); + +-- Location: FF_X10_Y10_N58 +\myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_SECOND_COUNTER~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y10_N0 +\myVirtualToplevel|RTC_SECOND_COUNTER~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_SECOND_COUNTER~6_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))) # +-- (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & ((!\myVirtualToplevel|RTC_SECOND_COUNTER\(1)))) ) ) # ( !\myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & ((\myVirtualToplevel|RTC_SECOND_COUNTER\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100111111001100000011111100110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(1), + dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|RTC_SECOND_COUNTER~6_combout\); + +-- Location: FF_X10_Y10_N1 +\myVirtualToplevel|RTC_SECOND_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_SECOND_COUNTER~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_SECOND_COUNTER\(1)); + +-- Location: LABCELL_X10_Y10_N3 +\myVirtualToplevel|Add6~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add6~0_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER\(1) & ( \myVirtualToplevel|RTC_SECOND_COUNTER\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(0), + dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(1), + combout => \myVirtualToplevel|Add6~0_combout\); + +-- Location: LABCELL_X10_Y10_N15 +\myVirtualToplevel|RTC_SECOND_COUNTER~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_SECOND_COUNTER~4_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & !\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\) ) ) # ( +-- !\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & +-- (!\myVirtualToplevel|Add6~0_combout\ $ ((!\myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101100110000011110110011000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Add6~0_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\, + combout => \myVirtualToplevel|RTC_SECOND_COUNTER~4_combout\); + +-- Location: FF_X10_Y10_N17 +\myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_SECOND_COUNTER~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\); + +-- Location: FF_X10_Y10_N16 +\myVirtualToplevel|RTC_SECOND_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_SECOND_COUNTER~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_SECOND_COUNTER\(2)); + +-- Location: LABCELL_X10_Y10_N30 +\myVirtualToplevel|RTC_SECOND_COUNTER~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_SECOND_COUNTER~3_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER\(3) & ( \myVirtualToplevel|RTC_SECOND_COUNTER\(2) & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # +-- (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (((!\myVirtualToplevel|Add6~0_combout\ & !\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|RTC_SECOND_COUNTER\(3) & ( \myVirtualToplevel|RTC_SECOND_COUNTER\(2) & ( +-- (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (((\myVirtualToplevel|Add6~0_combout\ & +-- !\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\)))) ) ) ) # ( \myVirtualToplevel|RTC_SECOND_COUNTER\(3) & ( !\myVirtualToplevel|RTC_SECOND_COUNTER\(2) & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & ((!\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\))) ) ) ) # ( !\myVirtualToplevel|RTC_SECOND_COUNTER\(3) & ( +-- !\myVirtualToplevel|RTC_SECOND_COUNTER\(2) & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110010001000100111001000100111001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + datac => \myVirtualToplevel|ALT_INV_Add6~0_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\, + datae => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(3), + dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(2), + combout => \myVirtualToplevel|RTC_SECOND_COUNTER~3_combout\); + +-- Location: FF_X10_Y10_N31 +\myVirtualToplevel|RTC_SECOND_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_SECOND_COUNTER~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_SECOND_COUNTER\(3)); + +-- Location: LABCELL_X10_Y10_N27 +\myVirtualToplevel|Add6~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add6~1_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER\(3) & ( (\myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ & \myVirtualToplevel|Add6~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_Add6~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(3), + combout => \myVirtualToplevel|Add6~1_combout\); + +-- Location: FF_X10_Y10_N26 +\myVirtualToplevel|RTC_SECOND_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_SECOND_COUNTER~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_SECOND_COUNTER\(4)); + +-- Location: LABCELL_X10_Y10_N24 +\myVirtualToplevel|RTC_SECOND_COUNTER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_SECOND_COUNTER~0_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4)) ) ) # ( +-- !\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & +-- ((!\myVirtualToplevel|Add6~1_combout\ $ (!\myVirtualToplevel|RTC_SECOND_COUNTER\(4))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011101110010001001110111001000100010001000100010001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + datac => \myVirtualToplevel|ALT_INV_Add6~1_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(4), + dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\, + combout => \myVirtualToplevel|RTC_SECOND_COUNTER~0_combout\); + +-- Location: FF_X10_Y10_N25 +\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_SECOND_COUNTER~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y10_N18 +\myVirtualToplevel|RTC_SECOND_COUNTER~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_SECOND_COUNTER~2_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER\(5) & ( \myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5))))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (!\myVirtualToplevel|Add6~1_combout\ & ((!\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|RTC_SECOND_COUNTER\(5) & ( \myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5))))) # +-- (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (\myVirtualToplevel|Add6~1_combout\ & ((!\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\)))) ) ) ) # ( \myVirtualToplevel|RTC_SECOND_COUNTER\(5) & ( +-- !\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & +-- ((!\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\))) ) ) ) # ( !\myVirtualToplevel|RTC_SECOND_COUNTER\(5) & ( !\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) & +-- !\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011000000110101001100000011101000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Add6~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\, + datae => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(5), + dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|RTC_SECOND_COUNTER~2_combout\); + +-- Location: FF_X10_Y10_N19 +\myVirtualToplevel|RTC_SECOND_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_SECOND_COUNTER~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_SECOND_COUNTER\(5)); + +-- Location: LABCELL_X10_Y10_N12 +\myVirtualToplevel|RTC_MINUTE_COUNTER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER\(4) & ( (\myVirtualToplevel|Add6~0_combout\ & (!\myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ & (\myVirtualToplevel|RTC_SECOND_COUNTER\(3) & +-- \myVirtualToplevel|RTC_SECOND_COUNTER\(5)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001000000000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Add6~0_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(3), + datad => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(5), + dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(4), + combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\); + +-- Location: LABCELL_X10_Y12_N6 +\myVirtualToplevel|RTC_MINUTE_COUNTER~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ & ( \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\ & ( (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1_combout\ & +-- (\myVirtualToplevel|RTC_MILLISEC_COUNTER\(9) & (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2_combout\ & \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~1_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(9), + datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~2_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(0), + datae => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\, + combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\); + +-- Location: MLABCELL_X9_Y11_N45 +\myVirtualToplevel|RTC_MINUTE_COUNTER~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MINUTE_COUNTER~8_combout\ = (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & +-- ((!\myVirtualToplevel|RTC_MINUTE_COUNTER\(0)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100001100001111110000110000111111000011000011111100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(0), + combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~8_combout\); + +-- Location: LABCELL_X10_Y11_N39 +\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\ = ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( ((\myVirtualToplevel|UART1|Mux0~0_combout\ & \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\)) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\) ) ) +-- # ( !\myVirtualToplevel|TIMER0_CS~2_combout\ & ( \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111010111110000111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + combout => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\); + +-- Location: FF_X9_Y11_N46 +\myVirtualToplevel|RTC_MINUTE_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MINUTE_COUNTER~8_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MINUTE_COUNTER\(0)); + +-- Location: FF_X9_Y11_N47 +\myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MINUTE_COUNTER~8_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE_q\); + +-- Location: MLABCELL_X9_Y11_N24 +\myVirtualToplevel|RTC_MINUTE_COUNTER~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MINUTE_COUNTER~9_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))) # +-- (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ((!\myVirtualToplevel|RTC_MINUTE_COUNTER\(1)))) ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ((\myVirtualToplevel|RTC_MINUTE_COUNTER\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100111111000011000011111100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(1), + dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~9_combout\); + +-- Location: FF_X9_Y11_N26 +\myVirtualToplevel|RTC_MINUTE_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MINUTE_COUNTER~9_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MINUTE_COUNTER\(1)); + +-- Location: MLABCELL_X9_Y11_N21 +\myVirtualToplevel|Add7~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add7~0_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(1) & ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(0), + dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(1), + combout => \myVirtualToplevel|Add7~0_combout\); + +-- Location: FF_X9_Y11_N4 +\myVirtualToplevel|RTC_MINUTE_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MINUTE_COUNTER~7_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MINUTE_COUNTER\(2)); + +-- Location: MLABCELL_X9_Y11_N48 +\myVirtualToplevel|RTC_MINUTE_COUNTER~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MINUTE_COUNTER~6_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(3) & ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(2) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))))) # +-- (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ & ((!\myVirtualToplevel|Add7~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER\(3) & ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(2) & ( +-- (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ & +-- ((\myVirtualToplevel|Add7~0_combout\)))) ) ) ) # ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(3) & ( !\myVirtualToplevel|RTC_MINUTE_COUNTER\(2) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3)))) # +-- (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\)) ) ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER\(3) & ( !\myVirtualToplevel|RTC_MINUTE_COUNTER\(2) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & !\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100111010101000110011000010100011001110100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + datac => \myVirtualToplevel|ALT_INV_Add7~0_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\, + datae => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(3), + dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(2), + combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~6_combout\); + +-- Location: FF_X9_Y11_N50 +\myVirtualToplevel|RTC_MINUTE_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MINUTE_COUNTER~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MINUTE_COUNTER\(3)); + +-- Location: MLABCELL_X9_Y11_N39 +\myVirtualToplevel|Add7~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add7~1_combout\ = !\myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ $ (((!\myVirtualToplevel|RTC_MINUTE_COUNTER\(3)) # ((!\myVirtualToplevel|Add7~0_combout\) # (!\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100011110000011110001111000001111000111100000111100011110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(3), + datab => \myVirtualToplevel|ALT_INV_Add7~0_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|Add7~1_combout\); + +-- Location: MLABCELL_X9_Y11_N0 +\myVirtualToplevel|RTC_MINUTE_COUNTER~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MINUTE_COUNTER~3_combout\ = ( \myVirtualToplevel|Add7~1_combout\ & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4)))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & +-- (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\)) ) ) # ( !\myVirtualToplevel|Add7~1_combout\ & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000101110001011100010111000101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + dataf => \myVirtualToplevel|ALT_INV_Add7~1_combout\, + combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~3_combout\); + +-- Location: FF_X9_Y11_N1 +\myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MINUTE_COUNTER~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\); + +-- Location: FF_X9_Y11_N2 +\myVirtualToplevel|RTC_MINUTE_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MINUTE_COUNTER~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MINUTE_COUNTER\(4)); + +-- Location: FF_X9_Y11_N32 +\myVirtualToplevel|RTC_MINUTE_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MINUTE_COUNTER~10_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MINUTE_COUNTER\(5)); + +-- Location: MLABCELL_X9_Y11_N30 +\myVirtualToplevel|RTC_MINUTE_COUNTER~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MINUTE_COUNTER~10_combout\ = ( !\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5)))) ) ) # ( \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ( +-- (!\myVirtualToplevel|RTC_MINUTE_COUNTER\(4) & (\myVirtualToplevel|RTC_MINUTE_COUNTER\(5))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER\(4) & ((!\myVirtualToplevel|RTC_MINUTE_COUNTER\(5) & (\myVirtualToplevel|Add7~0_combout\ & +-- (\myVirtualToplevel|RTC_MINUTE_COUNTER\(3) & \myVirtualToplevel|RTC_MINUTE_COUNTER\(2)))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER\(5) & ((!\myVirtualToplevel|Add7~0_combout\) # ((!\myVirtualToplevel|RTC_MINUTE_COUNTER\(3))))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000111100001111001100110011001000001111000011110011001100110110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(4), + datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(5), + datac => \myVirtualToplevel|ALT_INV_Add7~0_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(3), + datae => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(2), + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~10_combout\); + +-- Location: FF_X9_Y11_N31 +\myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MINUTE_COUNTER~10_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE_q\); + +-- Location: MLABCELL_X9_Y11_N36 +\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|RTC_MINUTE_COUNTER\(3) & (\myVirtualToplevel|Add7~0_combout\ & (!\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000100000000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(3), + datab => \myVirtualToplevel|ALT_INV_Add7~0_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\); + +-- Location: MLABCELL_X9_Y11_N3 +\myVirtualToplevel|RTC_MINUTE_COUNTER~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MINUTE_COUNTER~7_combout\ = ( \myVirtualToplevel|Add7~0_combout\ & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & +-- (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ & ((!\myVirtualToplevel|RTC_MINUTE_COUNTER\(2))))) ) ) # ( !\myVirtualToplevel|Add7~0_combout\ & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ & ((\myVirtualToplevel|RTC_MINUTE_COUNTER\(2))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000101110000011000010111000101110000011000010111000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(2), + dataf => \myVirtualToplevel|ALT_INV_Add7~0_combout\, + combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~7_combout\); + +-- Location: FF_X9_Y11_N5 +\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MINUTE_COUNTER~7_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y10_N6 +\myVirtualToplevel|IO_DATA_READ~74\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~74_combout\ = ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2) & ( \myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # +-- (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(2) & ( \myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) ) ) ) # ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2) & ( +-- !\myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(2) & ( !\myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000010001001111110001000100001100110111010011111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datae => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(2), + dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|IO_DATA_READ~74_combout\); + +-- Location: LABCELL_X14_Y12_N0 +\myVirtualToplevel|Add15~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~65_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|Add15~66\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(0), + cin => GND, + sumout => \myVirtualToplevel|Add15~65_sumout\, + cout => \myVirtualToplevel|Add15~66\); + +-- Location: LABCELL_X16_Y12_N54 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & +-- (\myVirtualToplevel|TIMER0_CS~2_combout\ & (\myVirtualToplevel|INTR0_CS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datab => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + datac => \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER~0_combout\, + combout => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\); + +-- Location: FF_X14_Y12_N1 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~65_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(0)); + +-- Location: LABCELL_X14_Y12_N3 +\myVirtualToplevel|Add15~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~69_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add15~66\ )) +-- \myVirtualToplevel|Add15~70\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add15~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(1), + cin => \myVirtualToplevel|Add15~66\, + sumout => \myVirtualToplevel|Add15~69_sumout\, + cout => \myVirtualToplevel|Add15~70\); + +-- Location: FF_X14_Y12_N5 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~69_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1)); + +-- Location: LABCELL_X14_Y12_N6 +\myVirtualToplevel|Add15~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~61_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~70\ )) +-- \myVirtualToplevel|Add15~62\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add15~70\, + sumout => \myVirtualToplevel|Add15~61_sumout\, + cout => \myVirtualToplevel|Add15~62\); + +-- Location: LABCELL_X14_Y12_N9 +\myVirtualToplevel|Add15~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~57_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add15~62\ )) +-- \myVirtualToplevel|Add15~58\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add15~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(3), + cin => \myVirtualToplevel|Add15~62\, + sumout => \myVirtualToplevel|Add15~57_sumout\, + cout => \myVirtualToplevel|Add15~58\); + +-- Location: FF_X14_Y12_N11 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~57_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(3)); + +-- Location: LABCELL_X14_Y12_N12 +\myVirtualToplevel|Add15~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~25_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add15~58\ )) +-- \myVirtualToplevel|Add15~26\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add15~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(4), + cin => \myVirtualToplevel|Add15~58\, + sumout => \myVirtualToplevel|Add15~25_sumout\, + cout => \myVirtualToplevel|Add15~26\); + +-- Location: FF_X14_Y12_N14 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~25_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4)); + +-- Location: MLABCELL_X13_Y12_N39 +\myVirtualToplevel|Equal33~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal33~3_combout\ = ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) & ( (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(3) & (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(2) & !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(3), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(2), + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(1), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(4), + combout => \myVirtualToplevel|Equal33~3_combout\); + +-- Location: LABCELL_X14_Y12_N15 +\myVirtualToplevel|Add15~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~29_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add15~26\ )) +-- \myVirtualToplevel|Add15~30\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add15~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(5), + cin => \myVirtualToplevel|Add15~26\, + sumout => \myVirtualToplevel|Add15~29_sumout\, + cout => \myVirtualToplevel|Add15~30\); + +-- Location: FF_X14_Y12_N16 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~29_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5)); + +-- Location: LABCELL_X14_Y12_N18 +\myVirtualToplevel|Add15~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~45_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add15~30\ )) +-- \myVirtualToplevel|Add15~46\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add15~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(6), + cin => \myVirtualToplevel|Add15~30\, + sumout => \myVirtualToplevel|Add15~45_sumout\, + cout => \myVirtualToplevel|Add15~46\); + +-- Location: FF_X14_Y12_N20 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~45_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6)); + +-- Location: LABCELL_X14_Y12_N21 +\myVirtualToplevel|Add15~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~49_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~46\ )) +-- \myVirtualToplevel|Add15~50\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add15~46\, + sumout => \myVirtualToplevel|Add15~49_sumout\, + cout => \myVirtualToplevel|Add15~50\); + +-- Location: FF_X14_Y12_N23 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~49_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y12_N24 +\myVirtualToplevel|Add15~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~53_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~50\ )) +-- \myVirtualToplevel|Add15~54\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add15~50\, + sumout => \myVirtualToplevel|Add15~53_sumout\, + cout => \myVirtualToplevel|Add15~54\); + +-- Location: FF_X14_Y12_N26 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~53_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y12_N27 +\myVirtualToplevel|Add15~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~33_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~54\ )) +-- \myVirtualToplevel|Add15~34\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add15~54\, + sumout => \myVirtualToplevel|Add15~33_sumout\, + cout => \myVirtualToplevel|Add15~34\); + +-- Location: FF_X14_Y12_N29 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~33_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y12_N30 +\myVirtualToplevel|Add15~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~37_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|Add15~34\ )) +-- \myVirtualToplevel|Add15~38\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|Add15~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(10), + cin => \myVirtualToplevel|Add15~34\, + sumout => \myVirtualToplevel|Add15~37_sumout\, + cout => \myVirtualToplevel|Add15~38\); + +-- Location: FF_X14_Y12_N32 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~37_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(10)); + +-- Location: LABCELL_X14_Y12_N33 +\myVirtualToplevel|Add15~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~41_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add15~38\ )) +-- \myVirtualToplevel|Add15~42\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add15~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(11), + cin => \myVirtualToplevel|Add15~38\, + sumout => \myVirtualToplevel|Add15~41_sumout\, + cout => \myVirtualToplevel|Add15~42\); + +-- Location: FF_X14_Y12_N35 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~41_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(11)); + +-- Location: LABCELL_X14_Y12_N36 +\myVirtualToplevel|Add15~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~9_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|Add15~42\ )) +-- \myVirtualToplevel|Add15~10\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|Add15~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(12), + cin => \myVirtualToplevel|Add15~42\, + sumout => \myVirtualToplevel|Add15~9_sumout\, + cout => \myVirtualToplevel|Add15~10\); + +-- Location: FF_X14_Y12_N37 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~9_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(12)); + +-- Location: LABCELL_X14_Y12_N39 +\myVirtualToplevel|Add15~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~13_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~10\ )) +-- \myVirtualToplevel|Add15~14\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add15~10\, + sumout => \myVirtualToplevel|Add15~13_sumout\, + cout => \myVirtualToplevel|Add15~14\); + +-- Location: FF_X14_Y12_N41 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~13_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y12_N42 +\myVirtualToplevel|Add15~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~17_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~14\ )) +-- \myVirtualToplevel|Add15~18\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add15~14\, + sumout => \myVirtualToplevel|Add15~17_sumout\, + cout => \myVirtualToplevel|Add15~18\); + +-- Location: FF_X14_Y12_N44 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~17_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y12_N45 +\myVirtualToplevel|Add15~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~21_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~18\ )) +-- \myVirtualToplevel|Add15~22\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add15~18\, + sumout => \myVirtualToplevel|Add15~21_sumout\, + cout => \myVirtualToplevel|Add15~22\); + +-- Location: FF_X14_Y12_N47 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~21_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y12_N48 +\myVirtualToplevel|Add15~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~1_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~22\ )) +-- \myVirtualToplevel|Add15~2\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add15~22\, + sumout => \myVirtualToplevel|Add15~1_sumout\, + cout => \myVirtualToplevel|Add15~2\); + +-- Location: FF_X14_Y12_N50 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~1_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y12_N57 +\myVirtualToplevel|Equal33~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal33~0_combout\ = ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\ & ( (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\ & (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\ & +-- !\myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|Equal33~0_combout\); + +-- Location: LABCELL_X14_Y12_N51 +\myVirtualToplevel|Add15~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add15~5_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(17) ) + ( VCC ) + ( \myVirtualToplevel|Add15~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(17), + cin => \myVirtualToplevel|Add15~2\, + sumout => \myVirtualToplevel|Add15~5_sumout\); + +-- Location: FF_X14_Y12_N52 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~5_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(17)); + +-- Location: LABCELL_X14_Y12_N54 +\myVirtualToplevel|Equal33~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal33~1_combout\ = ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(10) & (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\ & +-- !\myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(10), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|Equal33~1_combout\); + +-- Location: FF_X14_Y12_N34 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~41_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y12_N15 +\myVirtualToplevel|Equal33~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal33~2_combout\ = ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\ & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(12) & ( (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(0) & (\myVirtualToplevel|Equal33~0_combout\ & +-- (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(17) & \myVirtualToplevel|Equal33~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(0), + datab => \myVirtualToplevel|ALT_INV_Equal33~0_combout\, + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(17), + datad => \myVirtualToplevel|ALT_INV_Equal33~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(12), + combout => \myVirtualToplevel|Equal33~2_combout\); + +-- Location: LABCELL_X19_Y40_N0 +\myVirtualToplevel|Add14~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~69_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|Add14~70\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(0), + cin => GND, + sumout => \myVirtualToplevel|Add14~69_sumout\, + cout => \myVirtualToplevel|Add14~70\); + +-- Location: FF_X19_Y40_N2 +\myVirtualToplevel|MILLISEC_DOWN_TICK[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~69_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(0)); + +-- Location: LABCELL_X19_Y40_N3 +\myVirtualToplevel|Add14~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~65_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add14~70\ )) +-- \myVirtualToplevel|Add14~66\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add14~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(1), + cin => \myVirtualToplevel|Add14~70\, + sumout => \myVirtualToplevel|Add14~65_sumout\, + cout => \myVirtualToplevel|Add14~66\); + +-- Location: FF_X19_Y40_N5 +\myVirtualToplevel|MILLISEC_DOWN_TICK[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~65_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(1)); + +-- Location: LABCELL_X19_Y40_N6 +\myVirtualToplevel|Add14~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~61_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add14~66\ )) +-- \myVirtualToplevel|Add14~62\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add14~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(2), + cin => \myVirtualToplevel|Add14~66\, + sumout => \myVirtualToplevel|Add14~61_sumout\, + cout => \myVirtualToplevel|Add14~62\); + +-- Location: FF_X19_Y40_N8 +\myVirtualToplevel|MILLISEC_DOWN_TICK[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~61_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(2)); + +-- Location: LABCELL_X19_Y40_N9 +\myVirtualToplevel|Add14~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~5_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add14~62\ )) +-- \myVirtualToplevel|Add14~6\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add14~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(3), + cin => \myVirtualToplevel|Add14~62\, + sumout => \myVirtualToplevel|Add14~5_sumout\, + cout => \myVirtualToplevel|Add14~6\); + +-- Location: FF_X19_Y40_N11 +\myVirtualToplevel|MILLISEC_DOWN_TICK[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(3)); + +-- Location: LABCELL_X19_Y40_N12 +\myVirtualToplevel|Add14~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~57_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add14~6\ )) +-- \myVirtualToplevel|Add14~58\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add14~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(4), + cin => \myVirtualToplevel|Add14~6\, + sumout => \myVirtualToplevel|Add14~57_sumout\, + cout => \myVirtualToplevel|Add14~58\); + +-- Location: FF_X19_Y40_N14 +\myVirtualToplevel|MILLISEC_DOWN_TICK[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~57_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(4)); + +-- Location: LABCELL_X19_Y40_N54 +\myVirtualToplevel|Equal32~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal32~3_combout\ = ( \myVirtualToplevel|MILLISEC_DOWN_TICK\(4) & ( (\myVirtualToplevel|MILLISEC_DOWN_TICK\(2) & (\myVirtualToplevel|MILLISEC_DOWN_TICK\(0) & \myVirtualToplevel|MILLISEC_DOWN_TICK\(1))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(2), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(0), + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(1), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(4), + combout => \myVirtualToplevel|Equal32~3_combout\); + +-- Location: FF_X19_Y40_N50 +\myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y40_N15 +\myVirtualToplevel|Add14~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~1_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add14~58\ )) +-- \myVirtualToplevel|Add14~2\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add14~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(5), + cin => \myVirtualToplevel|Add14~58\, + sumout => \myVirtualToplevel|Add14~1_sumout\, + cout => \myVirtualToplevel|Add14~2\); + +-- Location: FF_X19_Y40_N17 +\myVirtualToplevel|MILLISEC_DOWN_TICK[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(5)); + +-- Location: LABCELL_X19_Y40_N18 +\myVirtualToplevel|Add14~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~21_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add14~2\ )) +-- \myVirtualToplevel|Add14~22\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add14~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(6), + cin => \myVirtualToplevel|Add14~2\, + sumout => \myVirtualToplevel|Add14~21_sumout\, + cout => \myVirtualToplevel|Add14~22\); + +-- Location: FF_X19_Y40_N20 +\myVirtualToplevel|MILLISEC_DOWN_TICK[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(6)); + +-- Location: LABCELL_X19_Y40_N21 +\myVirtualToplevel|Add14~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~53_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add14~22\ )) +-- \myVirtualToplevel|Add14~54\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add14~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(7), + cin => \myVirtualToplevel|Add14~22\, + sumout => \myVirtualToplevel|Add14~53_sumout\, + cout => \myVirtualToplevel|Add14~54\); + +-- Location: FF_X19_Y40_N22 +\myVirtualToplevel|MILLISEC_DOWN_TICK[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~53_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(7)); + +-- Location: LABCELL_X19_Y40_N24 +\myVirtualToplevel|Add14~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~17_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(8) ) + ( GND ) + ( \myVirtualToplevel|Add14~54\ )) +-- \myVirtualToplevel|Add14~18\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(8) ) + ( GND ) + ( \myVirtualToplevel|Add14~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(8), + cin => \myVirtualToplevel|Add14~54\, + sumout => \myVirtualToplevel|Add14~17_sumout\, + cout => \myVirtualToplevel|Add14~18\); + +-- Location: FF_X19_Y40_N26 +\myVirtualToplevel|MILLISEC_DOWN_TICK[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(8)); + +-- Location: LABCELL_X19_Y40_N27 +\myVirtualToplevel|Add14~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~49_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(9) ) + ( GND ) + ( \myVirtualToplevel|Add14~18\ )) +-- \myVirtualToplevel|Add14~50\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(9) ) + ( GND ) + ( \myVirtualToplevel|Add14~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(9), + cin => \myVirtualToplevel|Add14~18\, + sumout => \myVirtualToplevel|Add14~49_sumout\, + cout => \myVirtualToplevel|Add14~50\); + +-- Location: FF_X19_Y40_N28 +\myVirtualToplevel|MILLISEC_DOWN_TICK[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~49_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(9)); + +-- Location: LABCELL_X19_Y40_N30 +\myVirtualToplevel|Add14~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~45_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(10) ) + ( GND ) + ( \myVirtualToplevel|Add14~50\ )) +-- \myVirtualToplevel|Add14~46\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(10) ) + ( GND ) + ( \myVirtualToplevel|Add14~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(10), + cin => \myVirtualToplevel|Add14~50\, + sumout => \myVirtualToplevel|Add14~45_sumout\, + cout => \myVirtualToplevel|Add14~46\); + +-- Location: FF_X19_Y40_N32 +\myVirtualToplevel|MILLISEC_DOWN_TICK[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~45_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(10)); + +-- Location: LABCELL_X19_Y40_N33 +\myVirtualToplevel|Add14~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~41_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(11) ) + ( GND ) + ( \myVirtualToplevel|Add14~46\ )) +-- \myVirtualToplevel|Add14~42\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(11) ) + ( GND ) + ( \myVirtualToplevel|Add14~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(11), + cin => \myVirtualToplevel|Add14~46\, + sumout => \myVirtualToplevel|Add14~41_sumout\, + cout => \myVirtualToplevel|Add14~42\); + +-- Location: FF_X19_Y40_N35 +\myVirtualToplevel|MILLISEC_DOWN_TICK[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~41_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(11)); + +-- Location: LABCELL_X19_Y40_N36 +\myVirtualToplevel|Add14~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~37_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~42\ )) +-- \myVirtualToplevel|Add14~38\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add14~42\, + sumout => \myVirtualToplevel|Add14~37_sumout\, + cout => \myVirtualToplevel|Add14~38\); + +-- Location: FF_X19_Y40_N37 +\myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~37_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y40_N39 +\myVirtualToplevel|Add14~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~33_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~38\ )) +-- \myVirtualToplevel|Add14~34\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add14~38\, + sumout => \myVirtualToplevel|Add14~33_sumout\, + cout => \myVirtualToplevel|Add14~34\); + +-- Location: FF_X19_Y40_N41 +\myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~33_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y40_N42 +\myVirtualToplevel|Add14~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~29_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~34\ )) +-- \myVirtualToplevel|Add14~30\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add14~34\, + sumout => \myVirtualToplevel|Add14~29_sumout\, + cout => \myVirtualToplevel|Add14~30\); + +-- Location: FF_X19_Y40_N43 +\myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y40_N45 +\myVirtualToplevel|Add14~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~13_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(15) ) + ( GND ) + ( \myVirtualToplevel|Add14~30\ )) +-- \myVirtualToplevel|Add14~14\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(15) ) + ( GND ) + ( \myVirtualToplevel|Add14~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(15), + cin => \myVirtualToplevel|Add14~30\, + sumout => \myVirtualToplevel|Add14~13_sumout\, + cout => \myVirtualToplevel|Add14~14\); + +-- Location: FF_X19_Y40_N47 +\myVirtualToplevel|MILLISEC_DOWN_TICK[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(15)); + +-- Location: LABCELL_X19_Y40_N48 +\myVirtualToplevel|Add14~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~9_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~14\ )) +-- \myVirtualToplevel|Add14~10\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[16]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add14~14\, + sumout => \myVirtualToplevel|Add14~9_sumout\, + cout => \myVirtualToplevel|Add14~10\); + +-- Location: FF_X19_Y40_N49 +\myVirtualToplevel|MILLISEC_DOWN_TICK[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(16)); + +-- Location: FF_X19_Y40_N40 +\myVirtualToplevel|MILLISEC_DOWN_TICK[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~33_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(13)); + +-- Location: FF_X19_Y40_N38 +\myVirtualToplevel|MILLISEC_DOWN_TICK[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~37_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(12)); + +-- Location: FF_X19_Y40_N44 +\myVirtualToplevel|MILLISEC_DOWN_TICK[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(14)); + +-- Location: FF_X19_Y40_N53 +\myVirtualToplevel|MILLISEC_DOWN_TICK[17]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK[17]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y40_N51 +\myVirtualToplevel|Add14~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add14~25_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[17]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add14~10\, + sumout => \myVirtualToplevel|Add14~25_sumout\); + +-- Location: FF_X19_Y40_N52 +\myVirtualToplevel|MILLISEC_DOWN_TICK[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add14~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal32~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(17)); + +-- Location: MLABCELL_X18_Y40_N45 +\myVirtualToplevel|Equal32~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal32~0_combout\ = ( !\myVirtualToplevel|MILLISEC_DOWN_TICK\(17) & ( (!\myVirtualToplevel|MILLISEC_DOWN_TICK\(13) & (!\myVirtualToplevel|MILLISEC_DOWN_TICK\(12) & !\myVirtualToplevel|MILLISEC_DOWN_TICK\(14))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(13), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(12), + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(14), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(17), + combout => \myVirtualToplevel|Equal32~0_combout\); + +-- Location: MLABCELL_X18_Y40_N42 +\myVirtualToplevel|Equal32~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal32~1_combout\ = ( \myVirtualToplevel|MILLISEC_DOWN_TICK\(7) & ( (!\myVirtualToplevel|MILLISEC_DOWN_TICK\(11) & (\myVirtualToplevel|MILLISEC_DOWN_TICK\(10) & \myVirtualToplevel|MILLISEC_DOWN_TICK\(9))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000010100000000000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(11), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(10), + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(9), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(7), + combout => \myVirtualToplevel|Equal32~1_combout\); + +-- Location: MLABCELL_X18_Y40_N48 +\myVirtualToplevel|Equal32~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal32~2_combout\ = ( \myVirtualToplevel|Equal32~0_combout\ & ( \myVirtualToplevel|Equal32~1_combout\ & ( (\myVirtualToplevel|MILLISEC_DOWN_TICK\(16) & (!\myVirtualToplevel|MILLISEC_DOWN_TICK\(6) & +-- (\myVirtualToplevel|MILLISEC_DOWN_TICK\(15) & !\myVirtualToplevel|MILLISEC_DOWN_TICK\(8)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(16), + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(6), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(15), + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(8), + datae => \myVirtualToplevel|ALT_INV_Equal32~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_Equal32~1_combout\, + combout => \myVirtualToplevel|Equal32~2_combout\); + +-- Location: LABCELL_X19_Y40_N57 +\myVirtualToplevel|Equal32~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal32~4_combout\ = ( !\myVirtualToplevel|MILLISEC_DOWN_TICK\(5) & ( (\myVirtualToplevel|Equal32~3_combout\ & (\myVirtualToplevel|MILLISEC_DOWN_TICK\(3) & \myVirtualToplevel|Equal32~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal32~3_combout\, + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(3), + datad => \myVirtualToplevel|ALT_INV_Equal32~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(5), + combout => \myVirtualToplevel|Equal32~4_combout\); + +-- Location: LABCELL_X16_Y12_N48 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\ = ( !\myVirtualToplevel|Equal32~4_combout\ & ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5) ) ) # ( \myVirtualToplevel|Equal32~4_combout\ & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5) & ( +-- (\myVirtualToplevel|Equal33~3_combout\ & (\myVirtualToplevel|Equal33~2_combout\ & !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6))) ) ) ) # ( !\myVirtualToplevel|Equal32~4_combout\ & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000110000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_Equal33~3_combout\, + datac => \myVirtualToplevel|ALT_INV_Equal33~2_combout\, + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(6), + datae => \myVirtualToplevel|ALT_INV_Equal32~4_combout\, + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(5), + combout => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\); + +-- Location: FF_X14_Y12_N7 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~61_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\); + +-- Location: FF_X14_Y12_N8 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~61_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(2)); + +-- Location: MLABCELL_X13_Y12_N54 +\myVirtualToplevel|IO_DATA_READ~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~73_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(2))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SECOND_DOWN_COUNTER\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SECOND_DOWN_COUNTER\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( +-- !\myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011010001110100011111001100111111110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(2), + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|IO_DATA_READ~73_combout\); + +-- Location: LABCELL_X14_Y11_N51 +\myVirtualToplevel|RTC_HOUR_COUNTER~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ = ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001000000000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + combout => \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\); + +-- Location: LABCELL_X12_Y11_N15 +\myVirtualToplevel|RTC_MONTH_COUNTER~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER~1_combout\, + combout => \myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\); + +-- Location: LABCELL_X12_Y11_N45 +\myVirtualToplevel|RTC_MONTH_COUNTER[3]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\ ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\ & ( \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~5_combout\, + combout => \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\); + +-- Location: FF_X9_Y11_N19 +\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MONTH_COUNTER~10_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\); + +-- Location: LABCELL_X7_Y11_N54 +\myVirtualToplevel|RTC_MONTH_COUNTER~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MONTH_COUNTER~7_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER\(2) & ( \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & ( ((!\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & !\myVirtualToplevel|RTC_MONTH_COUNTER\(3))) # +-- (\myVirtualToplevel|RTC_MONTH_COUNTER\(0)) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(2) & ( \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & ( (\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & !\myVirtualToplevel|RTC_MONTH_COUNTER\(0)) ) ) ) +-- # ( \myVirtualToplevel|RTC_MONTH_COUNTER\(2) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(2) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010000010100001000111110001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3), + datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + datae => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(2), + dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\, + combout => \myVirtualToplevel|RTC_MONTH_COUNTER~7_combout\); + +-- Location: FF_X7_Y11_N56 +\myVirtualToplevel|RTC_MONTH_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MONTH_COUNTER~7_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MONTH_COUNTER\(2)); + +-- Location: MLABCELL_X9_Y11_N57 +\myVirtualToplevel|RTC_MONTH_COUNTER~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MONTH_COUNTER~4_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER\(3) & ( \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER\(2)) # (\myVirtualToplevel|RTC_MONTH_COUNTER\(0)) ) ) ) # ( +-- !\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & ( \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & (\myVirtualToplevel|RTC_MONTH_COUNTER\(2) & \myVirtualToplevel|RTC_MONTH_COUNTER\(1))) ) ) ) # ( +-- \myVirtualToplevel|RTC_MONTH_COUNTER\(3) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000001000101101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0), + datab => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(1), + datae => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3), + dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\, + combout => \myVirtualToplevel|RTC_MONTH_COUNTER~4_combout\); + +-- Location: FF_X9_Y11_N58 +\myVirtualToplevel|RTC_MONTH_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MONTH_COUNTER~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MONTH_COUNTER\(3)); + +-- Location: MLABCELL_X9_Y11_N27 +\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ( \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\, + combout => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\); + +-- Location: LABCELL_X7_Y11_N18 +\myVirtualToplevel|RTC_HOUR_COUNTER~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_HOUR_COUNTER~5_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(0) ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + datad => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(0), + dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\, + combout => \myVirtualToplevel|RTC_HOUR_COUNTER~5_combout\); + +-- Location: LABCELL_X12_Y11_N30 +\myVirtualToplevel|RTC_HOUR_COUNTER[2]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ( \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ( +-- \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ & ( \myVirtualToplevel|UART1|Equal7~0_combout\ ) ) ) # ( \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ( !\myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\, + datae => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER~1_combout\, + combout => \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\); + +-- Location: FF_X7_Y11_N20 +\myVirtualToplevel|RTC_HOUR_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_HOUR_COUNTER~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_HOUR_COUNTER\(0)); + +-- Location: LABCELL_X7_Y11_N12 +\myVirtualToplevel|RTC_HOUR_COUNTER~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_HOUR_COUNTER~6_combout\ = ( \myVirtualToplevel|RTC_HOUR_COUNTER\(0) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))) # +-- (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ((!\myVirtualToplevel|RTC_HOUR_COUNTER\(1)))) ) ) # ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(0) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ((\myVirtualToplevel|RTC_HOUR_COUNTER\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100111111000011000011111100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + datad => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(1), + dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(0), + combout => \myVirtualToplevel|RTC_HOUR_COUNTER~6_combout\); + +-- Location: FF_X7_Y11_N14 +\myVirtualToplevel|RTC_HOUR_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_HOUR_COUNTER~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_HOUR_COUNTER\(1)); + +-- Location: LABCELL_X7_Y11_N15 +\myVirtualToplevel|RTC_HOUR_COUNTER~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_HOUR_COUNTER~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\) # (!\myVirtualToplevel|RTC_HOUR_COUNTER\(2) $ (((!\myVirtualToplevel|RTC_HOUR_COUNTER\(0)) # +-- (!\myVirtualToplevel|RTC_HOUR_COUNTER\(1))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (!\myVirtualToplevel|RTC_HOUR_COUNTER\(2) $ (((!\myVirtualToplevel|RTC_HOUR_COUNTER\(0)) # +-- (!\myVirtualToplevel|RTC_HOUR_COUNTER\(1)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100110010000000010011001011001101111111101100110111111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(0), + datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(1), + datad => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + combout => \myVirtualToplevel|RTC_HOUR_COUNTER~4_combout\); + +-- Location: FF_X7_Y11_N17 +\myVirtualToplevel|RTC_HOUR_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_HOUR_COUNTER~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_HOUR_COUNTER\(2)); + +-- Location: LABCELL_X7_Y11_N9 +\myVirtualToplevel|RTC_MONTH_COUNTER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\ = ( \myVirtualToplevel|RTC_HOUR_COUNTER\(0) & ( (\myVirtualToplevel|RTC_HOUR_COUNTER\(2) & \myVirtualToplevel|RTC_HOUR_COUNTER\(1)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(2), + datac => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(1), + dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(0), + combout => \myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\); + +-- Location: LABCELL_X7_Y11_N30 +\myVirtualToplevel|RTC_HOUR_COUNTER~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_HOUR_COUNTER~3_combout\ = ( \myVirtualToplevel|RTC_HOUR_COUNTER\(3) & ( \myVirtualToplevel|RTC_HOUR_COUNTER\(4) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # +-- (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ((!\myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\))) ) ) ) # ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(3) & ( \myVirtualToplevel|RTC_HOUR_COUNTER\(4) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & !\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\) ) ) ) # ( \myVirtualToplevel|RTC_HOUR_COUNTER\(3) & ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(4) & ( +-- (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ((!\myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|RTC_HOUR_COUNTER\(3) & ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(4) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & +-- ((\myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010111110101000001010000010100000101111101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + datac => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~0_combout\, + datae => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(3), + dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(4), + combout => \myVirtualToplevel|RTC_HOUR_COUNTER~3_combout\); + +-- Location: FF_X7_Y11_N31 +\myVirtualToplevel|RTC_HOUR_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_HOUR_COUNTER~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_HOUR_COUNTER\(3)); + +-- Location: LABCELL_X7_Y11_N21 +\myVirtualToplevel|RTC_HOUR_COUNTER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_HOUR_COUNTER~0_combout\ = ( \myVirtualToplevel|RTC_HOUR_COUNTER\(3) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4))) # +-- (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ((!\myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\ $ (!\myVirtualToplevel|RTC_HOUR_COUNTER\(4))))) ) ) # ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(3) & ( +-- (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (((!\myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\ & +-- \myVirtualToplevel|RTC_HOUR_COUNTER\(4))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110100010001000111010001000111011101000100011101110100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~0_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(4), + dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(3), + combout => \myVirtualToplevel|RTC_HOUR_COUNTER~0_combout\); + +-- Location: FF_X7_Y11_N22 +\myVirtualToplevel|RTC_HOUR_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_HOUR_COUNTER~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_HOUR_COUNTER\(4)); + +-- Location: LABCELL_X7_Y11_N39 +\myVirtualToplevel|RTC_MONTH_COUNTER~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\ = ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(3) & ( (\myVirtualToplevel|RTC_HOUR_COUNTER\(4) & \myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(4), + datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(3), + combout => \myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\); + +-- Location: MLABCELL_X9_Y11_N9 +\myVirtualToplevel|RTC_MONTH_COUNTER~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ( (\myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\ & \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~1_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\, + combout => \myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\); + +-- Location: FF_X5_Y11_N40 +\myVirtualToplevel|RTC_DAY_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_DAY_COUNTER~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_DAY_COUNTER\(0)); + +-- Location: LABCELL_X12_Y11_N39 +\myVirtualToplevel|RTC_DAY_COUNTER~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ = ( \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER~1_combout\, + combout => \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\); + +-- Location: LABCELL_X5_Y11_N39 +\myVirtualToplevel|RTC_DAY_COUNTER~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_DAY_COUNTER~6_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER\(0) & ( \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)) ) ) ) # ( +-- !\myVirtualToplevel|RTC_DAY_COUNTER\(0) & ( \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & +-- (!\myVirtualToplevel|process_1~4_combout\)) ) ) ) # ( \myVirtualToplevel|RTC_DAY_COUNTER\(0) & ( !\myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ & ( !\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ ) ) ) # ( !\myVirtualToplevel|RTC_DAY_COUNTER\(0) & ( +-- !\myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ & ( (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & !\myVirtualToplevel|process_1~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100101010101010101011100100111001001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\, + datab => \myVirtualToplevel|ALT_INV_process_1~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + datae => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(0), + dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~2_combout\, + combout => \myVirtualToplevel|RTC_DAY_COUNTER~6_combout\); + +-- Location: FF_X5_Y11_N41 +\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_DAY_COUNTER~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y11_N36 +\myVirtualToplevel|IO_DATA_READ[5]~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[5]~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|UART1|Mux0~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010001000100010001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|IO_DATA_READ[5]~49_combout\); + +-- Location: LABCELL_X10_Y11_N42 +\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ = (!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\) # ((\myVirtualToplevel|IO_DATA_READ[5]~49_combout\ & \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110011111100001111001111110000111100111111000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ[5]~49_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\, + combout => \myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\); + +-- Location: MLABCELL_X9_Y11_N12 +\myVirtualToplevel|RTC_YEAR_COUNTER[0]_NEW1628\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER[0]_OTERM1629\ = ( \myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & ((\myVirtualToplevel|RTC_YEAR_COUNTER\(0)))) # +-- (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0))) ) ) # ( !\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & ( !\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ $ +-- (!\myVirtualToplevel|RTC_YEAR_COUNTER\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010110101010010101011010101000000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(0), + dataf => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + combout => \myVirtualToplevel|RTC_YEAR_COUNTER[0]_OTERM1629\); + +-- Location: FF_X9_Y11_N13 +\myVirtualToplevel|RTC_YEAR_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[0]_OTERM1629\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER\(0)); + +-- Location: LABCELL_X6_Y11_N0 +\myVirtualToplevel|Add11~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add11~42\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(0), + cin => GND, + cout => \myVirtualToplevel|Add11~42\); + +-- Location: LABCELL_X6_Y11_N3 +\myVirtualToplevel|Add11~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add11~45_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add11~42\ )) +-- \myVirtualToplevel|Add11~46\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add11~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(1), + cin => \myVirtualToplevel|Add11~42\, + sumout => \myVirtualToplevel|Add11~45_sumout\, + cout => \myVirtualToplevel|Add11~46\); + +-- Location: LABCELL_X6_Y11_N51 +\myVirtualToplevel|RTC_YEAR_COUNTER[1]_NEW1626\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER[1]_OTERM1627\ = ( \myVirtualToplevel|Add11~45_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(1))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & +-- ((!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))))) ) ) # ( !\myVirtualToplevel|Add11~45_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & +-- (((\myVirtualToplevel|RTC_YEAR_COUNTER\(1))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(1), + dataf => \myVirtualToplevel|ALT_INV_Add11~45_sumout\, + combout => \myVirtualToplevel|RTC_YEAR_COUNTER[1]_OTERM1627\); + +-- Location: FF_X6_Y11_N52 +\myVirtualToplevel|RTC_YEAR_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[1]_OTERM1627\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER\(1)); + +-- Location: LABCELL_X5_Y11_N48 +\myVirtualToplevel|RTC_DAY_COUNTER~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_DAY_COUNTER~8_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))))) # +-- (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (\myVirtualToplevel|process_1~5_combout\ & ((\myVirtualToplevel|RTC_DAY_COUNTER\(1))))) ) ) # ( !\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (\myVirtualToplevel|process_1~5_combout\ & ((!\myVirtualToplevel|RTC_DAY_COUNTER\(1))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100001010000110110000101000001010000110110000101000011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\, + datab => \myVirtualToplevel|ALT_INV_process_1~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(1), + dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|RTC_DAY_COUNTER~8_combout\); + +-- Location: LABCELL_X5_Y11_N51 +\myVirtualToplevel|RTC_DAY_COUNTER[4]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ ) # ( !\myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ & ( \myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~2_combout\, + combout => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\); + +-- Location: FF_X5_Y11_N49 +\myVirtualToplevel|RTC_DAY_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_DAY_COUNTER~8_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_DAY_COUNTER\(1)); + +-- Location: LABCELL_X7_Y11_N6 +\myVirtualToplevel|process_1~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|process_1~2_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER\(1) & ( (\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & (!\myVirtualToplevel|RTC_YEAR_COUNTER\(1) & !\myVirtualToplevel|RTC_YEAR_COUNTER\(0))) ) ) # ( +-- !\myVirtualToplevel|RTC_DAY_COUNTER\(1) & ( (!\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & ((\myVirtualToplevel|RTC_YEAR_COUNTER\(0)) # (\myVirtualToplevel|RTC_YEAR_COUNTER\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101010101010000010101010101001010000000000000101000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(1), + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(0), + dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(1), + combout => \myVirtualToplevel|process_1~2_combout\); + +-- Location: LABCELL_X5_Y11_N57 +\myVirtualToplevel|Add9~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add9~0_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER\(1) & ( !\myVirtualToplevel|RTC_DAY_COUNTER\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(1), + dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(0), + combout => \myVirtualToplevel|Add9~0_combout\); + +-- Location: FF_X7_Y11_N55 +\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MONTH_COUNTER~7_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\); + +-- Location: LABCELL_X5_Y11_N0 +\myVirtualToplevel|process_1~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|process_1~3_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( \myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & ((!\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|process_1~2_combout\)) # (\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ((\myVirtualToplevel|Add9~0_combout\))))) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( \myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|Add9~0_combout\ & (\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & !\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|Add9~0_combout\ & (!\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|Add9~0_combout\ & (\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & !\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000000000000011000000000011000000000101000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_process_1~2_combout\, + datab => \myVirtualToplevel|ALT_INV_Add9~0_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3), + datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0), + dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|process_1~3_combout\); + +-- Location: FF_X5_Y11_N25 +\myVirtualToplevel|RTC_DAY_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_DAY_COUNTER~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_DAY_COUNTER\(4)); + +-- Location: FF_X5_Y11_N29 +\myVirtualToplevel|RTC_DAY_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_DAY_COUNTER~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_DAY_COUNTER\(2)); + +-- Location: LABCELL_X5_Y11_N27 +\myVirtualToplevel|RTC_DAY_COUNTER~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_DAY_COUNTER~5_combout\ = ( \myVirtualToplevel|process_1~5_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & +-- (!\myVirtualToplevel|Add9~0_combout\ $ (((!\myVirtualToplevel|RTC_DAY_COUNTER\(2)))))) ) ) # ( !\myVirtualToplevel|process_1~5_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101000011011010011100001101101001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\, + datab => \myVirtualToplevel|ALT_INV_Add9~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(2), + dataf => \myVirtualToplevel|ALT_INV_process_1~5_combout\, + combout => \myVirtualToplevel|RTC_DAY_COUNTER~5_combout\); + +-- Location: FF_X5_Y11_N28 +\myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_DAY_COUNTER~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\); + +-- Location: LABCELL_X5_Y11_N30 +\myVirtualToplevel|RTC_DAY_COUNTER~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_DAY_COUNTER~4_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER\(3) & ( \myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # +-- (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (((\myVirtualToplevel|process_1~5_combout\ & !\myVirtualToplevel|Add9~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|RTC_DAY_COUNTER\(3) & ( \myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (((\myVirtualToplevel|process_1~5_combout\ & \myVirtualToplevel|Add9~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|RTC_DAY_COUNTER\(3) & ( !\myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & +-- ((\myVirtualToplevel|process_1~5_combout\))) ) ) ) # ( !\myVirtualToplevel|RTC_DAY_COUNTER\(3) & ( !\myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & !\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100110101001101010000010100110101001101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + datab => \myVirtualToplevel|ALT_INV_process_1~5_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\, + datad => \myVirtualToplevel|ALT_INV_Add9~0_combout\, + datae => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(3), + dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|RTC_DAY_COUNTER~4_combout\); + +-- Location: FF_X5_Y11_N32 +\myVirtualToplevel|RTC_DAY_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_DAY_COUNTER~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_DAY_COUNTER\(3)); + +-- Location: LABCELL_X5_Y11_N21 +\myVirtualToplevel|Add9~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add9~1_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER\(3) & ( (\myVirtualToplevel|Add9~0_combout\ & \myVirtualToplevel|RTC_DAY_COUNTER\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_Add9~0_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(2), + dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(3), + combout => \myVirtualToplevel|Add9~1_combout\); + +-- Location: LABCELL_X5_Y11_N6 +\myVirtualToplevel|RTC_DAY_COUNTER~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_DAY_COUNTER~7_combout\ = ( \myVirtualToplevel|Add9~1_combout\ & ( (\myVirtualToplevel|RTC_DAY_COUNTER~0_combout\ & (!\myVirtualToplevel|RTC_DAY_COUNTER\(4) $ (!\myVirtualToplevel|RTC_DAY_COUNTER\(5)))) ) ) # ( +-- !\myVirtualToplevel|Add9~1_combout\ & ( (\myVirtualToplevel|RTC_DAY_COUNTER~0_combout\ & \myVirtualToplevel|RTC_DAY_COUNTER\(5)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000011000011000000001100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(4), + datac => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~0_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(5), + dataf => \myVirtualToplevel|ALT_INV_Add9~1_combout\, + combout => \myVirtualToplevel|RTC_DAY_COUNTER~7_combout\); + +-- Location: FF_X5_Y11_N8 +\myVirtualToplevel|RTC_DAY_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_DAY_COUNTER~7_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_DAY_COUNTER\(5)); + +-- Location: LABCELL_X5_Y11_N9 +\myVirtualToplevel|process_1~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|process_1~4_combout\ = ( !\myVirtualToplevel|RTC_DAY_COUNTER\(5) & ( (\myVirtualToplevel|process_1~3_combout\ & (\myVirtualToplevel|RTC_DAY_COUNTER\(4) & (\myVirtualToplevel|RTC_DAY_COUNTER\(3) & +-- \myVirtualToplevel|RTC_DAY_COUNTER\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_process_1~3_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(4), + datac => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(3), + datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(2), + dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(5), + combout => \myVirtualToplevel|process_1~4_combout\); + +-- Location: LABCELL_X5_Y11_N42 +\myVirtualToplevel|process_1~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|process_1~5_combout\ = ( !\myVirtualToplevel|process_1~1_combout\ & ( !\myVirtualToplevel|process_1~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_process_1~4_combout\, + dataf => \myVirtualToplevel|ALT_INV_process_1~1_combout\, + combout => \myVirtualToplevel|process_1~5_combout\); + +-- Location: LABCELL_X5_Y11_N18 +\myVirtualToplevel|RTC_DAY_COUNTER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_DAY_COUNTER~0_combout\ = ( \myVirtualToplevel|process_1~5_combout\ & ( \myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\, + dataf => \myVirtualToplevel|ALT_INV_process_1~5_combout\, + combout => \myVirtualToplevel|RTC_DAY_COUNTER~0_combout\); + +-- Location: LABCELL_X5_Y11_N24 +\myVirtualToplevel|RTC_DAY_COUNTER~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_DAY_COUNTER~1_combout\ = ( \myVirtualToplevel|Add9~1_combout\ & ( (\myVirtualToplevel|RTC_DAY_COUNTER~0_combout\ & !\myVirtualToplevel|RTC_DAY_COUNTER\(4)) ) ) # ( !\myVirtualToplevel|Add9~1_combout\ & ( +-- (\myVirtualToplevel|RTC_DAY_COUNTER~0_combout\ & \myVirtualToplevel|RTC_DAY_COUNTER\(4)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~0_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(4), + dataf => \myVirtualToplevel|ALT_INV_Add9~1_combout\, + combout => \myVirtualToplevel|RTC_DAY_COUNTER~1_combout\); + +-- Location: FF_X5_Y11_N26 +\myVirtualToplevel|RTC_DAY_COUNTER[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_DAY_COUNTER~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_DAY_COUNTER[4]~DUPLICATE_q\); + +-- Location: FF_X5_Y11_N31 +\myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_DAY_COUNTER~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE_q\); + +-- Location: LABCELL_X5_Y11_N45 +\myVirtualToplevel|process_1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|process_1~0_combout\ = ( !\myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_DAY_COUNTER[4]~DUPLICATE_q\ & (!\myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\ & !\myVirtualToplevel|RTC_DAY_COUNTER\(1))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(1), + dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|process_1~0_combout\); + +-- Location: LABCELL_X5_Y11_N12 +\myVirtualToplevel|process_1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|process_1~1_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & (\myVirtualToplevel|process_1~0_combout\ & +-- (\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & \myVirtualToplevel|RTC_DAY_COUNTER\(5)))) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|process_1~0_combout\ & +-- (\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & \myVirtualToplevel|RTC_DAY_COUNTER\(5))) ) ) ) # ( \myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|process_1~0_combout\ & +-- (\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & \myVirtualToplevel|RTC_DAY_COUNTER\(5))) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & +-- (\myVirtualToplevel|process_1~0_combout\ & (\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & \myVirtualToplevel|RTC_DAY_COUNTER\(5)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000010000000000000001100000000000000110000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3), + datab => \myVirtualToplevel|ALT_INV_process_1~0_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(5), + datae => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0), + dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|process_1~1_combout\); + +-- Location: MLABCELL_X9_Y11_N42 +\myVirtualToplevel|RTC_MONTH_COUNTER~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ = ( \myVirtualToplevel|process_1~4_combout\ & ( (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ & \myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\)) ) +-- ) # ( !\myVirtualToplevel|process_1~4_combout\ & ( (\myVirtualToplevel|process_1~1_combout\ & (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ & \myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000100000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_process_1~1_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_process_1~4_combout\, + combout => \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\); + +-- Location: LABCELL_X10_Y11_N57 +\myVirtualToplevel|RTC_MONTH_COUNTER~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MONTH_COUNTER~8_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & \myVirtualToplevel|RTC_MONTH_COUNTER\(3)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3), + dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|RTC_MONTH_COUNTER~8_combout\); + +-- Location: LABCELL_X12_Y11_N42 +\myVirtualToplevel|RTC_MONTH_COUNTER~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MONTH_COUNTER~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & (!\myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\ & ((\myVirtualToplevel|RTC_MONTH_COUNTER\(0))))) +-- # (\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & (((!\myVirtualToplevel|RTC_MONTH_COUNTER~8_combout\ & !\myVirtualToplevel|RTC_MONTH_COUNTER\(0))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( +-- (!\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & (((\myVirtualToplevel|RTC_MONTH_COUNTER\(0))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & +-- (((!\myVirtualToplevel|RTC_MONTH_COUNTER~8_combout\ & !\myVirtualToplevel|RTC_MONTH_COUNTER\(0))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111001010101010011100101010101001010000100010000101000010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~5_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~8_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + combout => \myVirtualToplevel|RTC_MONTH_COUNTER~9_combout\); + +-- Location: FF_X12_Y11_N43 +\myVirtualToplevel|RTC_MONTH_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MONTH_COUNTER~9_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MONTH_COUNTER\(0)); + +-- Location: MLABCELL_X9_Y11_N18 +\myVirtualToplevel|RTC_MONTH_COUNTER~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MONTH_COUNTER~10_combout\ = ( \myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))))) # +-- (\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & (!\myVirtualToplevel|RTC_MONTH_COUNTER\(0) $ (((\myVirtualToplevel|RTC_MONTH_COUNTER\(1)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000101110000111010010111000011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0), + datab => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(1), + dataf => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + combout => \myVirtualToplevel|RTC_MONTH_COUNTER~10_combout\); + +-- Location: FF_X9_Y11_N20 +\myVirtualToplevel|RTC_MONTH_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_MONTH_COUNTER~10_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MONTH_COUNTER\(1)); + +-- Location: MLABCELL_X9_Y11_N6 +\myVirtualToplevel|RTC_YEAR_COUNTER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER\(3) & ( ((!\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\) # ((!\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\) # (\myVirtualToplevel|RTC_MONTH_COUNTER\(0)))) # +-- (\myVirtualToplevel|RTC_MONTH_COUNTER\(1)) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111110111111111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(1), + datab => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0), + datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3), + combout => \myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\); + +-- Location: LABCELL_X6_Y11_N6 +\myVirtualToplevel|Add11~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add11~37_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add11~46\ )) +-- \myVirtualToplevel|Add11~38\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add11~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(2), + cin => \myVirtualToplevel|Add11~46\, + sumout => \myVirtualToplevel|Add11~37_sumout\, + cout => \myVirtualToplevel|Add11~38\); + +-- Location: LABCELL_X7_Y11_N0 +\myVirtualToplevel|RTC_YEAR_COUNTER[2]_NEW1754\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER[2]_OTERM1755\ = ( \myVirtualToplevel|Add11~37_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(2))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & +-- ((!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) ) ) # ( !\myVirtualToplevel|Add11~37_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & +-- (((\myVirtualToplevel|RTC_YEAR_COUNTER\(2))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(2), + dataf => \myVirtualToplevel|ALT_INV_Add11~37_sumout\, + combout => \myVirtualToplevel|RTC_YEAR_COUNTER[2]_OTERM1755\); + +-- Location: FF_X7_Y11_N2 +\myVirtualToplevel|RTC_YEAR_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[2]_OTERM1755\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER\(2)); + +-- Location: LABCELL_X7_Y11_N48 +\myVirtualToplevel|IO_DATA_READ~72\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~72_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ((\myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_YEAR_COUNTER\(2))) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_YEAR_COUNTER\(2))) ) ) ) # ( +-- \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # (\myVirtualToplevel|RTC_HOUR_COUNTER\(2)) ) ) ) # ( +-- !\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (\myVirtualToplevel|RTC_HOUR_COUNTER\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(2), + datab => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + combout => \myVirtualToplevel|IO_DATA_READ~72_combout\); + +-- Location: LABCELL_X10_Y10_N51 +\myVirtualToplevel|IO_DATA_READ~75\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~75_combout\ = ( \myVirtualToplevel|IO_DATA_READ~72_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ((\myVirtualToplevel|IO_DATA_READ~73_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (\myVirtualToplevel|IO_DATA_READ~74_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))) ) ) # ( +-- !\myVirtualToplevel|IO_DATA_READ~72_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ((\myVirtualToplevel|IO_DATA_READ~73_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +-- (\myVirtualToplevel|IO_DATA_READ~74_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000000101000101000010011100110110001001110011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ~74_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ~73_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~72_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~75_combout\); + +-- Location: LABCELL_X12_Y7_N33 +\myVirtualToplevel|UART1|Add9~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~29_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & ( \myVirtualToplevel|UART1_CS~combout\ ) ) # ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( +-- \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) ) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2), + datae => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|Add9~29_combout\); + +-- Location: LABCELL_X14_Y7_N0 +\myVirtualToplevel|UART1|Add9~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~34_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|Add9~34_combout\); + +-- Location: LABCELL_X12_Y7_N3 +\myVirtualToplevel|UART1|Add9~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~39_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( \myVirtualToplevel|UART1_CS~combout\ ) ) # ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( +-- \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|Add9~39_combout\); + +-- Location: MLABCELL_X13_Y7_N0 +\myVirtualToplevel|UART1|Add9~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~42_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + cin => GND, + cout => \myVirtualToplevel|UART1|Add9~42_cout\); + +-- Location: MLABCELL_X13_Y7_N3 +\myVirtualToplevel|UART1|Add9~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~36_sumout\ = SUM(( \myVirtualToplevel|UART1|Add9~39_combout\ ) + ( (!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|IO_SELECT~combout\ & +-- ((!\myVirtualToplevel|Equal4~0_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|Equal4~0_combout\ & ((!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\))))) ) + ( \myVirtualToplevel|UART1|Add9~42_cout\ )) +-- \myVirtualToplevel|UART1|Add9~37\ = CARRY(( \myVirtualToplevel|UART1|Add9~39_combout\ ) + ( (!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|IO_SELECT~combout\ & +-- ((!\myVirtualToplevel|Equal4~0_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|Equal4~0_combout\ & ((!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\))))) ) + ( \myVirtualToplevel|UART1|Add9~42_cout\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101001100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_Add9~39_combout\, + dataf => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + cin => \myVirtualToplevel|UART1|Add9~42_cout\, + sumout => \myVirtualToplevel|UART1|Add9~36_sumout\, + cout => \myVirtualToplevel|UART1|Add9~37\); + +-- Location: MLABCELL_X13_Y7_N6 +\myVirtualToplevel|UART1|Add9~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~31_sumout\ = SUM(( \myVirtualToplevel|UART1|Add9~34_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1))))) ) + ( \myVirtualToplevel|UART1|Add9~37\ )) +-- \myVirtualToplevel|UART1|Add9~32\ = CARRY(( \myVirtualToplevel|UART1|Add9~34_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1))))) ) + ( \myVirtualToplevel|UART1|Add9~37\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000011110111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|UART1|ALT_INV_Add9~34_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1), + cin => \myVirtualToplevel|UART1|Add9~37\, + sumout => \myVirtualToplevel|UART1|Add9~31_sumout\, + cout => \myVirtualToplevel|UART1|Add9~32\); + +-- Location: MLABCELL_X13_Y7_N9 +\myVirtualToplevel|UART1|Add9~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~21_sumout\ = SUM(( \myVirtualToplevel|UART1|Add9~29_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2))))) ) + ( \myVirtualToplevel|UART1|Add9~32\ )) +-- \myVirtualToplevel|UART1|Add9~22\ = CARRY(( \myVirtualToplevel|UART1|Add9~29_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2))))) ) + ( \myVirtualToplevel|UART1|Add9~32\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000011110111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|UART1|ALT_INV_Add9~29_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|UART1|Add9~32\, + sumout => \myVirtualToplevel|UART1|Add9~21_sumout\, + cout => \myVirtualToplevel|UART1|Add9~22\); + +-- Location: FF_X14_Y6_N55 +\myVirtualToplevel|UART1|RX_FIFO~20\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER\(3), + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO~20_q\); + +-- Location: LABCELL_X14_Y6_N24 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]~feeder_combout\ = \myVirtualToplevel|UART1|RX_BUFFER\(3) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(3), + combout => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]~feeder_combout\); + +-- Location: FF_X14_Y6_N25 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(19)); + +-- Location: LABCELL_X14_Y6_N54 +\myVirtualToplevel|UART1|RX_DATA~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA~14_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(3) & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) # (\myVirtualToplevel|UART1|RX_FIFO~20_q\) ) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_BUFFER\(3) & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & \myVirtualToplevel|UART1|RX_FIFO~20_q\) ) ) ) # ( \myVirtualToplevel|UART1|RX_BUFFER\(3) & ( +-- !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(19)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & +-- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a2\)) ) ) ) # ( !\myVirtualToplevel|UART1|RX_BUFFER\(3) & ( !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & +-- ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(19)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a2\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~20_q\, + datac => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(19), + datae => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(3), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA~14_combout\); + +-- Location: LABCELL_X16_Y6_N0 +\myVirtualToplevel|UART1|RX_DATA[2]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA[2]~15_combout\ = ( \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & ((\myVirtualToplevel|UART1|RX_DATA\(2)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & +-- (\myVirtualToplevel|UART1|RX_DATA~14_combout\)) ) ) # ( !\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ & ( \myVirtualToplevel|UART1|RX_DATA\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA~14_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(2), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA[2]~15_combout\); + +-- Location: FF_X16_Y6_N1 +\myVirtualToplevel|UART1|RX_DATA[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_DATA[2]~15_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_DATA\(2)); + +-- Location: LABCELL_X14_Y9_N48 +\myVirtualToplevel|IO_DATA_READ~76\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~76_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART1|RX_DATA\(2)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|RX_DATA_READY~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000000000000000110101001101010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~DUPLICATE_q\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|IO_DATA_READ~76_combout\); + +-- Location: LABCELL_X14_Y9_N54 +\myVirtualToplevel|IO_DATA_READ~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~77_combout\ = ( \myVirtualToplevel|UART1|Add9~21_sumout\ & ( \myVirtualToplevel|IO_DATA_READ~76_combout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (((\myVirtualToplevel|IO_DATA_READ~75_combout\) # +-- (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\)))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (((!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(2)))) ) ) ) # ( !\myVirtualToplevel|UART1|Add9~21_sumout\ & ( +-- \myVirtualToplevel|IO_DATA_READ~76_combout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (((\myVirtualToplevel|IO_DATA_READ~75_combout\) # (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\)))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & +-- (\myVirtualToplevel|UART0|RX_DATA\(2) & (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\))) ) ) ) # ( \myVirtualToplevel|UART1|Add9~21_sumout\ & ( !\myVirtualToplevel|IO_DATA_READ~76_combout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & +-- (((!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & \myVirtualToplevel|IO_DATA_READ~75_combout\)))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (((!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(2)))) ) ) ) +-- # ( !\myVirtualToplevel|UART1|Add9~21_sumout\ & ( !\myVirtualToplevel|IO_DATA_READ~76_combout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (((!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & \myVirtualToplevel|IO_DATA_READ~75_combout\)))) # +-- (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|UART0|RX_DATA\(2) & (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110100001010100011111000100001011101010110101101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~70_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(2), + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~46_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ~75_combout\, + datae => \myVirtualToplevel|UART1|ALT_INV_Add9~21_sumout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~76_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~77_combout\); + +-- Location: LABCELL_X16_Y10_N57 +\myVirtualToplevel|IO_DATA_READ[0]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[0]~5_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|RESET_n~q\ ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|RESET_n~q\ & ((\myVirtualToplevel|UART0_CS~combout\) # +-- (\myVirtualToplevel|TIMER0_CS~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001011111000000001111111100000000010111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datac => \myVirtualToplevel|ALT_INV_UART0_CS~combout\, + datad => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datae => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\); + +-- Location: FF_X14_Y9_N55 +\myVirtualToplevel|IO_DATA_READ[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~77_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(2)); + +-- Location: FF_X17_Y14_N25 +\myVirtualToplevel|INT_ENABLE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(2)); + +-- Location: FF_X17_Y14_N44 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INT_ENABLE\(2), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(2)); + +-- Location: LABCELL_X16_Y14_N33 +\myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ = ( \myVirtualToplevel|IO_SELECT~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|IO_SELECT~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111100001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\); + +-- Location: LABCELL_X17_Y14_N0 +\myVirtualToplevel|MEM_DATA_READ[2]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~22_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ & ( \myVirtualToplevel|IO_SELECT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) $ (!\myVirtualToplevel|LessThan0~0_combout\) ) ) +-- ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ & ( \myVirtualToplevel|IO_SELECT~1_combout\ & ( (!\myVirtualToplevel|IO_SELECT~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) $ ((!\myVirtualToplevel|LessThan0~0_combout\)))) +-- # (\myVirtualToplevel|IO_SELECT~0_combout\ & (!\myVirtualToplevel|SD_CS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) $ (!\myVirtualToplevel|LessThan0~0_combout\)))) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ & ( +-- !\myVirtualToplevel|IO_SELECT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) $ (!\myVirtualToplevel|LessThan0~0_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ & ( !\myVirtualToplevel|IO_SELECT~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) $ (!\myVirtualToplevel|LessThan0~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101101001011010010110100101101001011010010010000101101001011010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(23), + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\, + datac => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_CS~0_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_RESYN12616_BDD12617\, + dataf => \myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[2]~22_combout\); + +-- Location: LABCELL_X17_Y14_N21 +\myVirtualToplevel|MEM_DATA_READ[2]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ = ( \myVirtualToplevel|INTR0_CS~combout\ & ( (\myVirtualToplevel|SD_CS~combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\) # ((\myVirtualToplevel|IO_SELECT~combout\ & +-- !\myVirtualToplevel|SOCCFG_CS~combout\)))) ) ) # ( !\myVirtualToplevel|INTR0_CS~combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\) # ((\myVirtualToplevel|IO_SELECT~combout\ & !\myVirtualToplevel|SOCCFG_CS~combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100110000111111110011000001010101000100000101010100010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_CS~combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_combout\, + dataf => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\); + +-- Location: LABCELL_X17_Y14_N42 +\myVirtualToplevel|MEM_DATA_READ[2]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~36_combout\ = ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(2) & ( \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(2))) # +-- (\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ & ((\myVirtualToplevel|IO_DATA_READ\(2)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(2) & ( \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ & +-- (\myVirtualToplevel|IO_DATA_READ_SD\(2))) # (\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ & ((\myVirtualToplevel|IO_DATA_READ\(2)))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(2) & ( !\myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\) # (!\myVirtualToplevel|SOCCFG_CS~combout\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(2) & ( !\myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ & ( (\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ +-- & !\myVirtualToplevel|SOCCFG_CS~combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000111111111100110001000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(2), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(2), + datad => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(2), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~35_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[2]~36_combout\); + +-- Location: FF_X14_Y15_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]_OTERM3338\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE_q\); + +-- Location: M10K_X22_Y15_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110101010000000000001151E6CB3128578D4C211C31904064C575010AE570AD6B5AD790C9934050000FD524A3A16728E452361345D88A2185520054000555555577005290E50231042092200210B42B100811C1A9A040A142063E0536CCF0C672AB572979AAECA4117675DD01C259661039757AE2F25AA9", + mem_init2 => "004803C9013403C996925323881744253A38AC3496AC0ECCD1A000900F920270929526F450128E438904A64D43BBE07D39A4994C4938D0F6A0016C58AB74CA7F92C06A5D50B24146A95920D251F053EB49E92E27E1B29D06092D88D49790D2CD31C314530D04100CC16E3B4889462F2E0894CD665ECAB4C94F67C689E20A930C5099292CEA8BC193C8CCAA214D3B0C4D3B0615C10E242A58A2021025B944788758B1B361E94362BA2C19694B32FE22D93E5723DC08F9844878C6424294C7A6B497E0F50C337480709614B12C85692D1024FC85C81430E1818231AF23ADB0150AC32DA84B57730CE36469481C65CAF1EC208F4AA156E19DCC802B35F5D3AC710E", + mem_init1 => "5AE806C59E38593E160277C0A20FC416B9D05378E1427083C411C63DC1AC30CC2EC37E813D42623D1ADAF2A276365919F6419729808683BBEBA49AB2D8E344F315D45193065F0824AA8168B4298AE7A929F14E516482048F89F419573EFD6A37856E73A00DD36BE23BC90C9C12778C17577F848459F0018BC8E348CAE20B61A3989A95C11F33E038A6A8C3E40863765BDF8D345DA816D284E8810005010304A5E9F342C3C9A94F559F5580978BB029E493D20499BDC015315A27D343B10D0903062ED00D91A74CBB3B8880C26978D7980B1067655E2011DFFA3CFE154A2B55AC861C14EEBC81F13A1A2FBBCD25C29034765A7E4517709C1DA6D343909812C61E", + mem_init0 => "D1E401225B361008058DAB4C9B14040047AAE9600136A3F075582A2150E43E076B3E8841304C0832E94380CBD0C067C8A8F0E0BA3393D15791961C41084F3B43B040283C4BF9D1A02BAD96330D3B4E683808A09265A00A805000000000082DD108000209004241A0084824144251289463A583640422485800D734C3208A9ED69B3660F9F067195D3000340010C2DB5C1018F34C2D934D02958DDC16FA35C893E3B8D5E7D3E04281F5DF9AF7FC303C3EBBF0172A98A36A00BB5B76B77777777777777777777777776E96DDADAB5B76B6FFFFFFFFFFFC924925B6DB6DB6DB6DFEFD000000000001243C060206040700010D050409050200000022001D30040C00", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 2, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 2, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\); + +-- Location: FF_X18_Y14_N23 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_NEW_REG30\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM31\); + +-- Location: MLABCELL_X18_Y14_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM31\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM31\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111101000000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM31\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM33\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\); + +-- Location: MLABCELL_X18_Y14_N57 +\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ & ( ((\myVirtualToplevel|LessThan0~1_combout\ & +-- (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\))) # (\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ & ( (\myVirtualToplevel|LessThan0~1_combout\ & (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0) & +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000000000000011000001010101011101010101010101110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datab => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]~25_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\); + +-- Location: MLABCELL_X18_Y14_N18 +\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\ = ( \myVirtualToplevel|MEM_DATA_READ[2]~36_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~36_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ ) ) # ( \myVirtualToplevel|MEM_DATA_READ[2]~36_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ & ( +-- ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|LessThan0~1_combout\))) # +-- (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~36_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ & ( +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|LessThan0~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010001000011110001111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\, + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + datad => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~36_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\, + combout => \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\); + +-- Location: LABCELL_X10_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_OTERM3214\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000000011100000100111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_155\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_OTERM3214\); + +-- Location: FF_X10_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_OTERM3214\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2)); + +-- Location: LABCELL_X10_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|MEM_BUSY~1_combout\ & +-- (\myVirtualToplevel|RESET_n~q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000001000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datab => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\); + +-- Location: LABCELL_X10_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]_NEW3210\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]_OTERM3211\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~99_Duplicate_158\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]_OTERM3211\); + +-- Location: FF_X10_Y17_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]_OTERM3211\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3)); + +-- Location: MLABCELL_X9_Y16_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]_NEW3222\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]_OTERM3223\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & +-- ((\myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~2_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~131_Duplicate_173\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]_OTERM3223\); + +-- Location: FF_X9_Y16_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]_OTERM3223\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4)); + +-- Location: MLABCELL_X9_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]_NEW3207\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]_OTERM3208\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & +-- ((\myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~2_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~127_Duplicate_167\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]_OTERM3208\); + +-- Location: FF_X9_Y18_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]_OTERM3208\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5)); + +-- Location: LABCELL_X7_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]_NEW3204\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]_OTERM3205\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~111_Duplicate_170\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]_OTERM3205\); + +-- Location: FF_X7_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]_OTERM3205\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6)); + +-- Location: MLABCELL_X9_Y16_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]_NEW3201\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]_OTERM3202\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~2_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~107_Duplicate_164\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]_OTERM3202\); + +-- Location: FF_X9_Y16_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]_OTERM3202\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7)); + +-- Location: M10K_X3_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init4 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + clk0_core_clock_enable => "ena0", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_evo_L2cache_a612c956.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|evo_L2cache:CACHEL2|altsyncram:RAM0_rtl_0|altsyncram_bnn1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "dont_care", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 10, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 10, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 1023, + port_a_logical_ram_depth => 1024, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock1", + port_b_address_width => 10, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 10, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 1023, + port_b_logical_ram_depth => 1024, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock1", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_WREN~0_combout\, + portbre => VCC, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + clk1 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + ena0 => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_WREN~0_combout\, + portadatain => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X28_Y35_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~374\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~374_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001110111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~374_combout\); + +-- Location: FF_X28_Y35_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~374_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\); + +-- Location: LABCELL_X12_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309~feeder_combout\); + +-- Location: FF_X12_Y16_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1308\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309\); + +-- Location: FF_X7_Y16_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1312\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1313\); + +-- Location: FF_X7_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1314\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\); + +-- Location: FF_X7_Y16_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1310\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\); + +-- Location: LABCELL_X7_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1313\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1313\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011111111111100111100000000000100011111111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1309\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1313\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1315\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\); + +-- Location: MLABCELL_X9_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[1]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[1]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000000000011111111001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[1]~5_combout\); + +-- Location: LABCELL_X14_Y14_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~119_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317~feeder_combout\); + +-- Location: FF_X14_Y14_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_NEW_REG1316\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317\); + +-- Location: FF_X9_Y16_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_NEW_REG1318\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1319\); + +-- Location: FF_X7_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_NEW_REG1320\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\); + +-- Location: LABCELL_X7_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1319\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1319\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011111111111111001100000000000001011111111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1317\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1319\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1321\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\); + +-- Location: LABCELL_X7_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[2]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[2]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000000000000000011110101111101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[2]~4_combout\); + +-- Location: FF_X14_Y14_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_NEW_REG1322\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1323\); + +-- Location: FF_X6_Y18_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_NEW_REG1324\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1325\); + +-- Location: FF_X6_Y18_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_NEW_REG1326\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1327\); + +-- Location: LABCELL_X6_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1327\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1325\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1323\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1327\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1325\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1323\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1327\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001010001011010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1323\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1325\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1327\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\); + +-- Location: LABCELL_X7_Y18_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[3]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[3]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100000001000000010011110111111101111111011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[3]~3_combout\); + +-- Location: LABCELL_X10_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~147_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353~feeder_combout\); + +-- Location: FF_X10_Y16_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_NEW_REG1352\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353\); + +-- Location: FF_X9_Y20_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_NEW_REG1354\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1355\); + +-- Location: FF_X6_Y18_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_NEW_REG1356\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1357\); + +-- Location: LABCELL_X6_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1357\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1355\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1357\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1355\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1357\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000001011111001111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1353\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1355\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1357\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\); + +-- Location: LABCELL_X7_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[4]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[4]~7_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010111111000001001011111100000100101111110000010010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[4]~7_combout\); + +-- Location: FF_X9_Y20_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_NEW_REG1342\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1343\); + +-- Location: FF_X7_Y18_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_NEW_REG1340\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1341\); + +-- Location: FF_X6_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_NEW_REG1344\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1345\); + +-- Location: LABCELL_X6_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1345\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1343\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1341\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1345\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1343\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1341\))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1345\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101000000111111010111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1343\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1341\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1345\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\); + +-- Location: LABCELL_X6_Y18_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[5]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[5]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110011110011111111111111001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[5]~1_combout\); + +-- Location: FF_X18_Y16_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_NEW_REG1346\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1347\); + +-- Location: FF_X6_Y18_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_NEW_REG1348\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1349\); + +-- Location: FF_X6_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_NEW_REG1350\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1351\); + +-- Location: LABCELL_X6_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1351\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1349\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1347\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1351\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1349\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1347\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1351\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101000100011010111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1347\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1349\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1351\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\); + +-- Location: LABCELL_X7_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[6]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[6]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100000000000100010010111011111111111011101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[6]~0_combout\); + +-- Location: FF_X17_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_NEW_REG1334\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1335\); + +-- Location: FF_X7_Y16_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_NEW_REG1336\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1337\); + +-- Location: FF_X7_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_NEW_REG1338\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\); + +-- Location: LABCELL_X7_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1335\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1335\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1337\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1337\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011111111111100111100000000000100011111111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1335\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1337\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1339\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\); + +-- Location: LABCELL_X7_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[7]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[7]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100000000000100010010111011111111111011101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[7]~6_combout\); + +-- Location: M10K_X22_Y38_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init4 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + clk0_core_clock_enable => "ena0", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_evo_L2cache_a612c956.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|evo_L2cache:CACHEL2|altsyncram:RAM1_rtl_0|altsyncram_cnn1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "dont_care", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 10, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 10, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 1023, + port_a_logical_ram_depth => 1024, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock1", + port_b_address_width => 10, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 10, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 1023, + port_b_logical_ram_depth => 1024, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock1", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0_combout\, + portbre => VCC, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + clk1 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + ena0 => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0_combout\, + portadatain => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X26_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~375\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~375_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~375_combout\); + +-- Location: FF_X26_Y35_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~375_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\); + +-- Location: LABCELL_X26_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\); + +-- Location: LABCELL_X29_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\); + +-- Location: LABCELL_X26_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~373\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~373_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~373_combout\); + +-- Location: FF_X26_Y35_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~373_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\); + +-- Location: FF_X26_Y35_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~372_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\); + +-- Location: LABCELL_X26_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~372\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~372_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~372_combout\); + +-- Location: FF_X26_Y35_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~372_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y36_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\); + +-- Location: LABCELL_X29_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000101000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\); + +-- Location: FF_X29_Y35_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~377_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\); + +-- Location: LABCELL_X29_Y35_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~377\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~377_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~377_combout\); + +-- Location: FF_X29_Y35_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~377_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\); + +-- Location: FF_X26_Y35_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~376_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\); + +-- Location: LABCELL_X26_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~376\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~376_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111110100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~376_combout\); + +-- Location: FF_X26_Y35_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~376_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\); + +-- Location: LABCELL_X29_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\); + +-- Location: LABCELL_X32_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\); + +-- Location: LABCELL_X32_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~379\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~379_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~379_combout\); + +-- Location: FF_X32_Y29_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~379_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\); + +-- Location: LABCELL_X25_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~378\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~378_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~378_combout\); + +-- Location: FF_X25_Y34_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~378_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\); + +-- Location: LABCELL_X32_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\); + +-- Location: LABCELL_X26_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010010001101100111000010011100110110101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9_combout\); + +-- Location: LABCELL_X25_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~389\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~389_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~389_combout\); + +-- Location: FF_X25_Y35_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~389_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\); + +-- Location: MLABCELL_X28_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~388\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~388_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~388_combout\); + +-- Location: FF_X28_Y35_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~388_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\); + +-- Location: LABCELL_X24_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\); + +-- Location: LABCELL_X29_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\); + +-- Location: LABCELL_X26_Y35_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~393\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~393_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~393_combout\); + +-- Location: FF_X26_Y35_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~393_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\); + +-- Location: LABCELL_X26_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~392\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~392_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ +-- & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~392_combout\); + +-- Location: FF_X26_Y35_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~392_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\); + +-- Location: LABCELL_X26_Y35_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\); + +-- Location: LABCELL_X29_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~391\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~391_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~391_combout\); + +-- Location: FF_X29_Y35_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~391_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\); + +-- Location: LABCELL_X20_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~390\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~390_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~390_combout\); + +-- Location: FF_X20_Y33_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~390_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\); + +-- Location: LABCELL_X26_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000000000000000111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\); + +-- Location: MLABCELL_X28_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~394\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~394_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~394_combout\); + +-- Location: FF_X28_Y35_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~394_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\); + +-- Location: MLABCELL_X28_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~395\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~395_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~395_combout\); + +-- Location: FF_X28_Y30_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~395_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\); + +-- Location: LABCELL_X21_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\); + +-- Location: LABCELL_X26_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111001100110000000001010101000011110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19_combout\); + +-- Location: FF_X28_Y35_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~382_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\); + +-- Location: MLABCELL_X13_Y14_N48 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001111000010100000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\); + +-- Location: MLABCELL_X23_Y14_N54 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node[1]\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1) = ( \myVirtualToplevel|BRAM_WREN~1_combout\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) # ((\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & \myVirtualToplevel|LessThan3~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001000100010001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\, + datad => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\, + datae => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM2_WREN~0_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1)); + +-- Location: MLABCELL_X23_Y14_N24 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\ = ( \myVirtualToplevel|BRAM_WREN~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16) & ((!\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\) # +-- (!\myVirtualToplevel|LessThan3~0_combout\)))) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\) ) ) # ( !\myVirtualToplevel|BRAM_WREN~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100001111111011110000111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\, + datab => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM2_WREN~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + dataf => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\); + +-- Location: LABCELL_X20_Y11_N15 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\); + +-- Location: LABCELL_X20_Y11_N27 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\ & ( (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]~6_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5_combout\); + +-- Location: M10K_X30_Y10_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 1, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 1, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X23_Y14_N18 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node[0]\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0) = ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|BRAM_WREN~1_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) # ((\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & \myVirtualToplevel|LessThan3~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110001000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\, + datab => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + datad => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\, + datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM2_WREN~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0)); + +-- Location: M10K_X38_Y14_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020220000002200000200200010029CD263F98326811812002008A88E01040414CA48421094F8005113000039BD582A64B42A41915E0803E3BA65C12181300001E00000062010D1EF815B28C5180020A00000305B321A02D20428D02362C3A4000000D612E2B1AC201385000CE3B829443C8D0A4EA82413408019", + mem_init2 => "380600A47C02E4C0ACC0E140C43915AA950C0562070552CA01D9700B9208F803808307AA6414240907184181248888931444502A205448A144B686050400919C1419C60D874D56AA83A6AB551DD062749EA80066118A077F34332B0424869C06A0A55C00000000921E0410314DFECBB7374A3172E4AC2E49F7F686D8FA97191689DC5D3E7C70ADE208AA08E513C60913C6653F073553390456B3204CF89E71F1C3962C0DAAC10D9C7C100237430C82A00D6A2E1B62CADE8C953E16548342B940C104D092758953015CC3A068E24F4EC0D61B0050A4FC314E24900E2466510A41435B7BA00201F13A0C008C0D716E1102A41A421608531847CE63900F0011B594", + mem_init1 => "543370ED6B131707C8083292E55010E9528000C7D88C5E8269A06A480CAA4164362666A69A6472A110BA3491580B042C8063016B4C800B17A4D313DA39669360AB5E808AF7409C85922F955EC048431DDA9701D28AA40024231008587993C278130CFCACBC0EC6846F493CAE0A5C826AEA1129A7E11E556880640D345245C42B4101825826750071E82F2B249851725043BC56980E9231120E968081E0A01D188508B010E4801301C17CC1A8AB84183760E0481D83DABC1598EF124121144E6862124310CFA042524805100010000037445F81F25232A2D11E1D3516322B3B0387A816DADA68650E18706C858384C8C201D4417E31E71540520C298A258B7885", + mem_init0 => "4646420A9082C010A25A51844168005E18653EE960C25D86200A81000A11034819E29470AF0D859C1F8A09049D1640B4F7A514C2E0A2408052650A5841F04334A11B090D32562749A65089120088D0CA13C40B24C70703BD779F3E7CF9F3C48B08086610867CC210CF9842384261309864C77E4120950D77BA1418121065B19021A1981FF5242AA44AAAB49255460212CCD0B9012C902DE8024C0BF500002228000500111000A028400AA00140450108015140608C63A4000036002AAEEAEAEAEEEEEAAAEEAAEEEEC005801A00340068FFFFFFFFFFF924924DB6DB69249249FEF80000000000015024040416120601000000321B05030100032303147E1A0001", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 1, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 1, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\); + +-- Location: FF_X21_Y12_N38 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0)); + +-- Location: LABCELL_X14_Y14_N42 +\myVirtualToplevel|MEM_DATA_READ[17]~66\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[17]~66_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[17]~26_combout\ & ((!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9~portbdataout\) # (!\myVirtualToplevel|LessThan0~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~26_combout\ & +-- ((!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9~portbdataout\) # (!\myVirtualToplevel|LessThan0~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ & ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~26_combout\ & !\myVirtualToplevel|LessThan0~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & ( !\myVirtualToplevel|MEM_DATA_READ[17]~26_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100000000000011110000101000001111000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~26_combout\, + datad => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + combout => \myVirtualToplevel|MEM_DATA_READ[17]~66_combout\); + +-- Location: FF_X14_Y14_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG602\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[17]~66_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM603\); + +-- Location: FF_X9_Y18_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG598\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM599\); + +-- Location: FF_X9_Y18_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG594\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM595\); + +-- Location: FF_X9_Y18_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG596\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~2_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM597\); + +-- Location: MLABCELL_X18_Y14_N54 +\myVirtualToplevel|MEM_DATA_READ[30]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[30]~20_combout\ = ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( !\myVirtualToplevel|INTR0_CS~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[30]~20_combout\); + +-- Location: MLABCELL_X18_Y14_N0 +\myVirtualToplevel|MEM_DATA_READ[27]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ = ( \myVirtualToplevel|LessThan0~0_combout\ & ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ & \myVirtualToplevel|SD_CS~combout\) ) ) ) # ( +-- !\myVirtualToplevel|LessThan0~0_combout\ & ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|LessThan0~0_combout\ & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ & \myVirtualToplevel|SD_CS~combout\) ) ) ) # ( !\myVirtualToplevel|LessThan0~0_combout\ & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|IO_SELECT~combout\) # (\myVirtualToplevel|SD_CS~combout\)) # (\myVirtualToplevel|INTR0_CS~combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000101010101000000001010101001010101010101010000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datad => \myVirtualToplevel|ALT_INV_SD_CS~combout\, + datae => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[27]~21_combout\); + +-- Location: MLABCELL_X18_Y14_N36 +\myVirtualToplevel|MEM_DATA_READ[17]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ = ( \myVirtualToplevel|SD_CS~combout\ & ( !\myVirtualToplevel|LessThan0~0_combout\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|SD_CS~combout\ & ( +-- (\myVirtualToplevel|LessThan0~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000111100001111000011110000111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_SD_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[17]~23_combout\); + +-- Location: FF_X13_Y11_N22 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~21_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(17)); + +-- Location: FF_X16_Y10_N35 +\myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1073\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(17), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[17]_OTERM1074\); + +-- Location: LABCELL_X16_Y10_N36 +\myVirtualToplevel|IO_DATA_READ[17]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[17]~2_combout\ = ( \myVirtualToplevel|Equal3~0_combout\ & ( (\myVirtualToplevel|TIMER0_CS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000010100000010100001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + combout => \myVirtualToplevel|IO_DATA_READ[17]~2_combout\); + +-- Location: FF_X16_Y10_N37 +\myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1079\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ[17]~2_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[17]_OTERM1080\); + +-- Location: LABCELL_X16_Y10_N9 +\myVirtualToplevel|IO_DATA_READ[17]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[17]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( ((\myVirtualToplevel|TIMER0_CS~1_combout\ & !\myVirtualToplevel|Equal3~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( ((!\myVirtualToplevel|TIMER0_CS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ & (!\myVirtualToplevel|Equal3~0_combout\))) # +-- (\myVirtualToplevel|UART1_CS~combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110010011111111111001001111111101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datab => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|IO_DATA_READ[17]~1_combout\); + +-- Location: LABCELL_X16_Y10_N6 +\myVirtualToplevel|IO_DATA_READ[17]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[17]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( ((\myVirtualToplevel|TIMER0_CS~1_combout\ & !\myVirtualToplevel|Equal3~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|UART1_CS~combout\) # ((!\myVirtualToplevel|TIMER0_CS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ & +-- (!\myVirtualToplevel|Equal3~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111100100111111111110010001001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datab => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|IO_DATA_READ[17]~0_combout\); + +-- Location: LABCELL_X14_Y8_N36 +\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~1_combout\ = !\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(0), + combout => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~1_combout\); + +-- Location: MLABCELL_X13_Y10_N48 +\myVirtualToplevel|UART1|TX_RESET~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_RESET~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( \myVirtualToplevel|UART1_CS~combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( !\myVirtualToplevel|UART1_CS~combout\ ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( !\myVirtualToplevel|UART1_CS~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111111111111100011111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|TX_RESET~0_combout\); + +-- Location: FF_X13_Y10_N50 +\myVirtualToplevel|UART1|TX_RESET\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_RESET~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_RESET~q\); + +-- Location: LABCELL_X14_Y7_N24 +\myVirtualToplevel|UART1|TX_ENABLE~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_ENABLE~1_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\, + combout => \myVirtualToplevel|UART1|TX_ENABLE~1_combout\); + +-- Location: FF_X14_Y7_N26 +\myVirtualToplevel|UART1|TX_ENABLE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_ENABLE~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_ENABLE~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_ENABLE~q\); + +-- Location: MLABCELL_X13_Y9_N51 +\myVirtualToplevel|UART1|TX_OVERRUN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_OVERRUN~0_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|UART1|TX_ENABLE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & \myVirtualToplevel|UART1|Equal7~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011000000000000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|TX_OVERRUN~0_combout\); + +-- Location: LABCELL_X14_Y7_N27 +\myVirtualToplevel|UART1|TX_ENABLE_FIFO~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_ENABLE_FIFO~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]~6_combout\, + combout => \myVirtualToplevel|UART1|TX_ENABLE_FIFO~0_combout\); + +-- Location: FF_X14_Y7_N28 +\myVirtualToplevel|UART1|TX_ENABLE_FIFO\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_ENABLE_FIFO~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_ENABLE~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\); + +-- Location: MLABCELL_X13_Y9_N0 +\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\ = ( !\myVirtualToplevel|UART1|Equal6~4_combout\ & ( (\myVirtualToplevel|UART1|TX_OVERRUN~0_combout\ & !\myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_OVERRUN~0_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE_FIFO~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Equal6~4_combout\, + combout => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\); + +-- Location: FF_X14_Y8_N38 +\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~1_combout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0)); + +-- Location: LABCELL_X14_Y8_N0 +\myVirtualToplevel|UART1|Add7~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add7~1_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0) ) + ( !VCC )) +-- \myVirtualToplevel|UART1|Add7~2\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0) ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(0), + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(1), + cin => GND, + sumout => \myVirtualToplevel|UART1|Add7~1_sumout\, + cout => \myVirtualToplevel|UART1|Add7~2\); + +-- Location: FF_X14_Y8_N1 +\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add7~1_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1)); + +-- Location: LABCELL_X14_Y8_N3 +\myVirtualToplevel|UART1|Add7~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add7~21_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~2\ )) +-- \myVirtualToplevel|UART1|Add7~22\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(2), + cin => \myVirtualToplevel|UART1|Add7~2\, + sumout => \myVirtualToplevel|UART1|Add7~21_sumout\, + cout => \myVirtualToplevel|UART1|Add7~22\); + +-- Location: FF_X14_Y8_N5 +\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add7~21_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2)); + +-- Location: LABCELL_X14_Y8_N6 +\myVirtualToplevel|UART1|Add7~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add7~13_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~22\ )) +-- \myVirtualToplevel|UART1|Add7~14\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(3), + cin => \myVirtualToplevel|UART1|Add7~22\, + sumout => \myVirtualToplevel|UART1|Add7~13_sumout\, + cout => \myVirtualToplevel|UART1|Add7~14\); + +-- Location: FF_X14_Y8_N7 +\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add7~13_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3)); + +-- Location: LABCELL_X14_Y8_N9 +\myVirtualToplevel|UART1|Add7~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add7~25_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~14\ )) +-- \myVirtualToplevel|UART1|Add7~26\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(4), + cin => \myVirtualToplevel|UART1|Add7~14\, + sumout => \myVirtualToplevel|UART1|Add7~25_sumout\, + cout => \myVirtualToplevel|UART1|Add7~26\); + +-- Location: FF_X14_Y8_N11 +\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add7~25_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4)); + +-- Location: LABCELL_X14_Y8_N12 +\myVirtualToplevel|UART1|Add7~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add7~17_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~26\ )) +-- \myVirtualToplevel|UART1|Add7~18\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(5), + cin => \myVirtualToplevel|UART1|Add7~26\, + sumout => \myVirtualToplevel|UART1|Add7~17_sumout\, + cout => \myVirtualToplevel|UART1|Add7~18\); + +-- Location: FF_X14_Y8_N14 +\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add7~17_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5)); + +-- Location: LABCELL_X14_Y8_N15 +\myVirtualToplevel|UART1|Add7~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add7~5_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~18\ )) +-- \myVirtualToplevel|UART1|Add7~6\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(6), + cin => \myVirtualToplevel|UART1|Add7~18\, + sumout => \myVirtualToplevel|UART1|Add7~5_sumout\, + cout => \myVirtualToplevel|UART1|Add7~6\); + +-- Location: FF_X14_Y8_N16 +\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add7~5_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6)); + +-- Location: MLABCELL_X13_Y8_N24 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1_combout\ = ( !\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1_combout\); + +-- Location: FF_X13_Y8_N25 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1_combout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0)); + +-- Location: FF_X13_Y8_N26 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1_combout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE_q\); + +-- Location: MLABCELL_X13_Y8_N30 +\myVirtualToplevel|UART1|Add8~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add8~1_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1) ) + ( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE_q\ ) + ( !VCC )) +-- \myVirtualToplevel|UART1|Add8~2\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1) ) + ( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE_q\ ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(1), + cin => GND, + sumout => \myVirtualToplevel|UART1|Add8~1_sumout\, + cout => \myVirtualToplevel|UART1|Add8~2\); + +-- Location: FF_X13_Y8_N31 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add8~1_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1)); + +-- Location: LABCELL_X14_Y8_N45 +\myVirtualToplevel|UART1|Equal5~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal5~0_combout\ = ( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0) $ (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0)))) ) ) # ( +-- !\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0) $ (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001100100000000100110010000000000000000100110010000000010011001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(0), + datab => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(1), + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|UART1|Equal5~0_combout\); + +-- Location: MLABCELL_X13_Y8_N33 +\myVirtualToplevel|UART1|Add8~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add8~21_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~2\ )) +-- \myVirtualToplevel|UART1|Add8~22\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|UART1|Add8~2\, + sumout => \myVirtualToplevel|UART1|Add8~21_sumout\, + cout => \myVirtualToplevel|UART1|Add8~22\); + +-- Location: FF_X13_Y8_N34 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add8~21_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2)); + +-- Location: MLABCELL_X13_Y8_N36 +\myVirtualToplevel|UART1|Add8~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add8~13_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~22\ )) +-- \myVirtualToplevel|UART1|Add8~14\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|UART1|Add8~22\, + sumout => \myVirtualToplevel|UART1|Add8~13_sumout\, + cout => \myVirtualToplevel|UART1|Add8~14\); + +-- Location: FF_X13_Y8_N37 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add8~13_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3)); + +-- Location: MLABCELL_X13_Y8_N39 +\myVirtualToplevel|UART1|Add8~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add8~25_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~14\ )) +-- \myVirtualToplevel|UART1|Add8~26\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|UART1|Add8~14\, + sumout => \myVirtualToplevel|UART1|Add8~25_sumout\, + cout => \myVirtualToplevel|UART1|Add8~26\); + +-- Location: FF_X13_Y8_N40 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add8~25_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4)); + +-- Location: LABCELL_X14_Y8_N57 +\myVirtualToplevel|UART1|Equal5~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal5~3_combout\ = ( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4) & ( (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2) $ (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2)))) ) ) # ( +-- !\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4) & ( (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2) $ (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000001010000101000000101000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(2), + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(4), + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(4), + combout => \myVirtualToplevel|UART1|Equal5~3_combout\); + +-- Location: LABCELL_X14_Y8_N18 +\myVirtualToplevel|UART1|Add7~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add7~9_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(7), + cin => \myVirtualToplevel|UART1|Add7~6\, + sumout => \myVirtualToplevel|UART1|Add7~9_sumout\); + +-- Location: FF_X14_Y8_N19 +\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add7~9_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(7)); + +-- Location: MLABCELL_X13_Y8_N42 +\myVirtualToplevel|UART1|Add8~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add8~17_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~26\ )) +-- \myVirtualToplevel|UART1|Add8~18\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(5), + cin => \myVirtualToplevel|UART1|Add8~26\, + sumout => \myVirtualToplevel|UART1|Add8~17_sumout\, + cout => \myVirtualToplevel|UART1|Add8~18\); + +-- Location: FF_X13_Y8_N43 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add8~17_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5)); + +-- Location: MLABCELL_X13_Y8_N45 +\myVirtualToplevel|UART1|Add8~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add8~5_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~18\ )) +-- \myVirtualToplevel|UART1|Add8~6\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(6), + cin => \myVirtualToplevel|UART1|Add8~18\, + sumout => \myVirtualToplevel|UART1|Add8~5_sumout\, + cout => \myVirtualToplevel|UART1|Add8~6\); + +-- Location: MLABCELL_X13_Y8_N48 +\myVirtualToplevel|UART1|Add8~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add8~9_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(7), + cin => \myVirtualToplevel|UART1|Add8~6\, + sumout => \myVirtualToplevel|UART1|Add8~9_sumout\); + +-- Location: FF_X13_Y8_N49 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add8~9_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(7)); + +-- Location: LABCELL_X16_Y8_N18 +\myVirtualToplevel|UART1|Equal5~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal5~1_combout\ = ( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6) & ( (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(7) $ (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(7)))) ) ) # ( +-- !\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6) & ( (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(7) $ (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(7)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001100000000110000110000000000000000110000110000000011000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(7), + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(7), + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(6), + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(6), + combout => \myVirtualToplevel|UART1|Equal5~1_combout\); + +-- Location: LABCELL_X14_Y8_N24 +\myVirtualToplevel|UART1|Equal5~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal5~2_combout\ = ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5) & ( (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5) & (!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3) $ (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3)))) ) ) # ( +-- !\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5) & ( (!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5) & (!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3) $ (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010010100000000101001010000000000000000101001010000000010100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(3), + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(3), + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(5), + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(5), + combout => \myVirtualToplevel|UART1|Equal5~2_combout\); + +-- Location: LABCELL_X14_Y8_N27 +\myVirtualToplevel|UART1|Equal5~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal5~4_combout\ = ( \myVirtualToplevel|UART1|Equal5~2_combout\ & ( (\myVirtualToplevel|UART1|Equal5~0_combout\ & (\myVirtualToplevel|UART1|Equal5~3_combout\ & \myVirtualToplevel|UART1|Equal5~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal5~0_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Equal5~3_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_Equal5~1_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Equal5~2_combout\, + combout => \myVirtualToplevel|UART1|Equal5~4_combout\); + +-- Location: LABCELL_X12_Y7_N57 +\myVirtualToplevel|UART1|TX_BUFFER[16]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_BUFFER[16]~9_combout\ = !\myVirtualToplevel|UART1|TX_STATE~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + combout => \myVirtualToplevel|UART1|TX_BUFFER[16]~9_combout\); + +-- Location: MLABCELL_X9_Y13_N0 +\myVirtualToplevel|UART1|Add0~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~61_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|UART1|Add0~62\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(0), + cin => GND, + sumout => \myVirtualToplevel|UART1|Add0~61_sumout\, + cout => \myVirtualToplevel|UART1|Add0~62\); + +-- Location: LABCELL_X14_Y7_N12 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~6_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\, + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~6_combout\); + +-- Location: FF_X14_Y7_N14 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(0)); + +-- Location: LABCELL_X14_Y7_N15 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~_wirecell_combout\ = ( !\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(0), + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~_wirecell_combout\); + +-- Location: MLABCELL_X13_Y9_N39 +\myVirtualToplevel|UART1|TX_COUNTER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_COUNTER~0_combout\ = ( \myVirtualToplevel|UART1|Equal0~4_combout\ ) # ( !\myVirtualToplevel|UART1|Equal0~4_combout\ & ( !\myVirtualToplevel|UART1|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Equal0~4_combout\, + combout => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\); + +-- Location: FF_X9_Y13_N2 +\myVirtualToplevel|UART1|TX_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~61_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~_wirecell_combout\, + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(0)); + +-- Location: MLABCELL_X9_Y13_N3 +\myVirtualToplevel|UART1|Add0~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~49_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~62\ )) +-- \myVirtualToplevel|UART1|Add0~50\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(1), + cin => \myVirtualToplevel|UART1|Add0~62\, + sumout => \myVirtualToplevel|UART1|Add0~49_sumout\, + cout => \myVirtualToplevel|UART1|Add0~50\); + +-- Location: FF_X10_Y13_N13 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(1)); + +-- Location: FF_X9_Y13_N5 +\myVirtualToplevel|UART1|TX_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~49_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(1), + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(1)); + +-- Location: MLABCELL_X9_Y13_N6 +\myVirtualToplevel|UART1|Add0~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~53_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~50\ )) +-- \myVirtualToplevel|UART1|Add0~54\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(2), + cin => \myVirtualToplevel|UART1|Add0~50\, + sumout => \myVirtualToplevel|UART1|Add0~53_sumout\, + cout => \myVirtualToplevel|UART1|Add0~54\); + +-- Location: LABCELL_X10_Y13_N33 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~5_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\, + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~5_combout\); + +-- Location: FF_X10_Y13_N35 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(2)); + +-- Location: LABCELL_X10_Y13_N42 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~_wirecell_combout\ = !\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(2) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(2), + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~_wirecell_combout\); + +-- Location: FF_X9_Y13_N8 +\myVirtualToplevel|UART1|TX_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~53_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~_wirecell_combout\, + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(2)); + +-- Location: MLABCELL_X9_Y13_N9 +\myVirtualToplevel|UART1|Add0~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~37_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~54\ )) +-- \myVirtualToplevel|UART1|Add0~38\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(3), + cin => \myVirtualToplevel|UART1|Add0~54\, + sumout => \myVirtualToplevel|UART1|Add0~37_sumout\, + cout => \myVirtualToplevel|UART1|Add0~38\); + +-- Location: FF_X12_Y18_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_NEW_REG905\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM906\); + +-- Location: LABCELL_X7_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]_NEW2773\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]_OTERM2774\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(19) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]_OTERM2774\); + +-- Location: FF_X7_Y20_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]_OTERM2774\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(19)); + +-- Location: LABCELL_X7_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]_NEW2901\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]_OTERM2902\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101000000111111010111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]_OTERM2902\); + +-- Location: FF_X7_Y20_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]_OTERM2902\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19)); + +-- Location: LABCELL_X7_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]_NEW2837\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]_OTERM2838\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]_OTERM2838\); + +-- Location: FF_X7_Y20_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]_OTERM2838\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19)); + +-- Location: LABCELL_X7_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]_NEW2709\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]_OTERM2710\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010100111111111101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]_OTERM2710\); + +-- Location: FF_X7_Y20_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]_OTERM2710\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19)); + +-- Location: LABCELL_X7_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(19))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(19))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1_combout\); + +-- Location: LABCELL_X7_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]_NEW3157\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]_OTERM3158\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(19) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]_OTERM3158\); + +-- Location: FF_X7_Y25_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]_OTERM3158\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(19)); + +-- Location: LABCELL_X7_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]_NEW3029\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]_OTERM3030\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(19) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]_OTERM3030\); + +-- Location: FF_X7_Y25_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]_OTERM3030\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(19)); + +-- Location: LABCELL_X7_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]_NEW2965\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]_OTERM2966\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]_OTERM2966\); + +-- Location: FF_X7_Y25_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]_OTERM2966\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(19)); + +-- Location: LABCELL_X7_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]_NEW3093\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]_OTERM3094\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(19))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(19))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]_OTERM3094\); + +-- Location: FF_X7_Y25_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]_OTERM3094\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(19)); + +-- Location: LABCELL_X7_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(19) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(19) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(19) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(19) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0_combout\); + +-- Location: LABCELL_X7_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\); + +-- Location: LABCELL_X12_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111110000111100111111000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\); + +-- Location: LABCELL_X12_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector273~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector273~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\) ) ) ) # ( +-- !\myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010011101110000101000100010010111110111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector15~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector273~0_combout\); + +-- Location: FF_X12_Y18_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_NEW_REG907\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector273~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM908\); + +-- Location: LABCELL_X12_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM906\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM908\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM906\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM908\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM906\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM908\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011111010111101010000010100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]_OTERM906\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]_OTERM908\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\); + +-- Location: LABCELL_X10_Y13_N6 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\, + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~4_combout\); + +-- Location: FF_X10_Y13_N8 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(3)); + +-- Location: LABCELL_X10_Y13_N9 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~_wirecell_combout\ = ( !\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(3), + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~_wirecell_combout\); + +-- Location: FF_X9_Y13_N11 +\myVirtualToplevel|UART1|TX_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~37_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~_wirecell_combout\, + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(3)); + +-- Location: MLABCELL_X9_Y13_N12 +\myVirtualToplevel|UART1|Add0~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~33_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~38\ )) +-- \myVirtualToplevel|UART1|Add0~34\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(4), + cin => \myVirtualToplevel|UART1|Add0~38\, + sumout => \myVirtualToplevel|UART1|Add0~33_sumout\, + cout => \myVirtualToplevel|UART1|Add0~34\); + +-- Location: FF_X10_Y15_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_NEW_REG909\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM910\); + +-- Location: FF_X19_Y17_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(20)); + +-- Location: FF_X19_Y17_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(20)); + +-- Location: LABCELL_X19_Y17_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(20) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(20)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(20)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\); + +-- Location: LABCELL_X6_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]_NEW3027\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]_OTERM3028\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]_OTERM3028\); + +-- Location: FF_X6_Y23_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]_OTERM3028\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20)); + +-- Location: LABCELL_X6_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]_NEW2963\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]_OTERM2964\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]_OTERM2964\); + +-- Location: FF_X6_Y23_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]_OTERM2964\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20)); + +-- Location: LABCELL_X6_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]_NEW3155\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]_OTERM3156\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]_OTERM3156\); + +-- Location: FF_X6_Y23_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]_OTERM3156\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20)); + +-- Location: LABCELL_X6_Y23_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]_NEW3091\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]_OTERM3092\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]_OTERM3092\); + +-- Location: FF_X6_Y23_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]_OTERM3092\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20)); + +-- Location: LABCELL_X6_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010011111100000101001100001111010100111111111101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0_combout\); + +-- Location: MLABCELL_X9_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]_NEW2835\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]_OTERM2836\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(20) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]_OTERM2836\); + +-- Location: FF_X9_Y21_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]_OTERM2836\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(20)); + +-- Location: MLABCELL_X9_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]_NEW2707\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]_OTERM2708\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]_OTERM2708\); + +-- Location: FF_X9_Y21_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]_OTERM2708\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(20)); + +-- Location: MLABCELL_X9_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]_NEW2771\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]_OTERM2772\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(20) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]_OTERM2772\); + +-- Location: FF_X9_Y21_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]_OTERM2772\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(20)); + +-- Location: MLABCELL_X9_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]_NEW2899\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]_OTERM2900\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000001111111001011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]_OTERM2900\); + +-- Location: FF_X9_Y21_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]_OTERM2900\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(20)); + +-- Location: MLABCELL_X9_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(20) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(20) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(20) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(20) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\); + +-- Location: MLABCELL_X13_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\); + +-- Location: LABCELL_X10_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111110000111100001111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\); + +-- Location: LABCELL_X10_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector272~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector272~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\))) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\))) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000010001001111110001000100001100110111010011111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector14~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector272~0_combout\); + +-- Location: FF_X10_Y15_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_NEW_REG911\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector272~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM912\); + +-- Location: LABCELL_X10_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM910\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM912\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM910\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM912\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM910\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM912\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011111010111101010000010100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]_OTERM910\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]_OTERM912\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\); + +-- Location: LABCELL_X10_Y13_N0 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]~17_combout\, + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~3_combout\); + +-- Location: FF_X10_Y13_N2 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(4)); + +-- Location: LABCELL_X10_Y13_N3 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~_wirecell_combout\ = !\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(4) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(4), + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~_wirecell_combout\); + +-- Location: FF_X9_Y13_N14 +\myVirtualToplevel|UART1|TX_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~33_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~_wirecell_combout\, + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(4)); + +-- Location: MLABCELL_X9_Y13_N15 +\myVirtualToplevel|UART1|Add0~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~29_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~34\ )) +-- \myVirtualToplevel|UART1|Add0~30\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(5), + cin => \myVirtualToplevel|UART1|Add0~34\, + sumout => \myVirtualToplevel|UART1|Add0~29_sumout\, + cout => \myVirtualToplevel|UART1|Add0~30\); + +-- Location: FF_X10_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_NEW_REG917\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM918\); + +-- Location: FF_X19_Y14_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~5_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(21)); + +-- Location: LABCELL_X19_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]~feeder_combout\); + +-- Location: FF_X19_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(4)); + +-- Location: M10K_X30_Y13_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 4, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 4, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X21_Y13_N42 +\myVirtualToplevel|Mux92~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux92~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + combout => \myVirtualToplevel|Mux92~0_combout\); + +-- Location: LABCELL_X21_Y13_N36 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SOCCFG[4]~feeder_combout\ = ( \myVirtualToplevel|Mux92~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_Mux92~0_combout\, + combout => \myVirtualToplevel|IO_DATA_READ_SOCCFG[4]~feeder_combout\); + +-- Location: FF_X21_Y13_N38 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SOCCFG[4]~feeder_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(4)); + +-- Location: FF_X17_Y11_N13 +\myVirtualToplevel|MILLISEC_UP_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~49_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(4)); + +-- Location: MLABCELL_X13_Y12_N30 +\myVirtualToplevel|Mux268~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux268~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(4))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SECOND_DOWN_COUNTER\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # +-- (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(4)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(4))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SECOND_DOWN_COUNTER\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) & ( (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(4) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000010101010000111100110011111111110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(4), + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(4), + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(4), + combout => \myVirtualToplevel|Mux268~0_combout\); + +-- Location: MLABCELL_X9_Y12_N0 +\myVirtualToplevel|Mux268~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux268~1_combout\ = ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) & ( \myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(4)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) & ( +-- \myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) ) ) ) # ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) & ( +-- !\myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) ) ) ) # ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) & ( +-- !\myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001111110101000000110000010111110011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datae => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(4), + dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|Mux268~1_combout\); + +-- Location: FF_X6_Y11_N43 +\myVirtualToplevel|RTC_YEAR_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[3]_OTERM1757\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER\(3)); + +-- Location: LABCELL_X6_Y11_N9 +\myVirtualToplevel|Add11~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add11~33_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add11~38\ )) +-- \myVirtualToplevel|Add11~34\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add11~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add11~38\, + sumout => \myVirtualToplevel|Add11~33_sumout\, + cout => \myVirtualToplevel|Add11~34\); + +-- Location: LABCELL_X6_Y11_N42 +\myVirtualToplevel|RTC_YEAR_COUNTER[3]_NEW1756\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER[3]_OTERM1757\ = ( \myVirtualToplevel|Add11~33_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(3))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & +-- ((!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))))) ) ) # ( !\myVirtualToplevel|Add11~33_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & +-- (((\myVirtualToplevel|RTC_YEAR_COUNTER\(3))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(3), + dataf => \myVirtualToplevel|ALT_INV_Add11~33_sumout\, + combout => \myVirtualToplevel|RTC_YEAR_COUNTER[3]_OTERM1757\); + +-- Location: FF_X6_Y11_N44 +\myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[3]_OTERM1757\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE_q\); + +-- Location: LABCELL_X6_Y11_N12 +\myVirtualToplevel|Add11~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add11~1_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER\(4) ) + ( GND ) + ( \myVirtualToplevel|Add11~34\ )) +-- \myVirtualToplevel|Add11~2\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER\(4) ) + ( GND ) + ( \myVirtualToplevel|Add11~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(4), + cin => \myVirtualToplevel|Add11~34\, + sumout => \myVirtualToplevel|Add11~1_sumout\, + cout => \myVirtualToplevel|Add11~2\); + +-- Location: LABCELL_X7_Y11_N3 +\myVirtualToplevel|RTC_YEAR_COUNTER[4]_NEW1772\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER[4]_OTERM1773\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(4))))) # +-- (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|Add11~1_sumout\)) # (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( +-- (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(4))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|Add11~1_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\, + datac => \myVirtualToplevel|ALT_INV_Add11~1_sumout\, + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + combout => \myVirtualToplevel|RTC_YEAR_COUNTER[4]_OTERM1773\); + +-- Location: FF_X7_Y11_N5 +\myVirtualToplevel|RTC_YEAR_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[4]_OTERM1773\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER\(4)); + +-- Location: LABCELL_X7_Y11_N36 +\myVirtualToplevel|IO_DATA_READ[4]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[4]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_DAY_COUNTER\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (\myVirtualToplevel|RTC_YEAR_COUNTER\(4))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|RTC_HOUR_COUNTER\(4)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001000100010001000000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(4), + datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(4), + datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + combout => \myVirtualToplevel|IO_DATA_READ[4]~34_combout\); + +-- Location: MLABCELL_X9_Y12_N6 +\myVirtualToplevel|IO_DATA_READ[4]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[4]~35_combout\ = ( \myVirtualToplevel|IO_DATA_READ[4]~34_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|Mux268~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (((\myVirtualToplevel|Mux268~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|IO_DATA_READ[4]~34_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (\myVirtualToplevel|Mux268~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ((\myVirtualToplevel|Mux268~1_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000010000100110000011001010111010001100101011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_Mux268~0_combout\, + datad => \myVirtualToplevel|ALT_INV_Mux268~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ[4]~34_combout\, + combout => \myVirtualToplevel|IO_DATA_READ[4]~35_combout\); + +-- Location: FF_X13_Y6_N53 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER\(5), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(21)); + +-- Location: FF_X13_Y6_N7 +\myVirtualToplevel|UART1|RX_FIFO~22\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER\(5), + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO~22_q\); + +-- Location: MLABCELL_X13_Y6_N6 +\myVirtualToplevel|UART1|RX_DATA~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA~4_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(5) & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) # (\myVirtualToplevel|UART1|RX_FIFO~22_q\) ) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_BUFFER\(5) & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (\myVirtualToplevel|UART1|RX_FIFO~22_q\ & \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) ) ) ) # ( \myVirtualToplevel|UART1|RX_BUFFER\(5) & ( +-- !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(21))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & +-- ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a4\))) ) ) ) # ( !\myVirtualToplevel|UART1|RX_BUFFER\(5) & ( !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & +-- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(21))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a4\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(21), + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~22_q\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\, + datad => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(5), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA~4_combout\); + +-- Location: MLABCELL_X13_Y6_N3 +\myVirtualToplevel|UART1|RX_DATA[4]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA[4]~5_combout\ = ( \myVirtualToplevel|UART1|RX_DATA\(4) & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\) # ((!\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\) # (\myVirtualToplevel|UART1|RX_DATA~4_combout\)) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_DATA\(4) & ( (\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & (\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ & \myVirtualToplevel|UART1|RX_DATA~4_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001111011111110111100000001000000011110111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA~4_combout\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(4), + combout => \myVirtualToplevel|UART1|RX_DATA[4]~5_combout\); + +-- Location: FF_X13_Y6_N4 +\myVirtualToplevel|UART1|RX_DATA[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_DATA[4]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_DATA\(4)); + +-- Location: LABCELL_X16_Y5_N30 +\myVirtualToplevel|UART1|Add5~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add5~26_cout\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1), + cin => GND, + cout => \myVirtualToplevel|UART1|Add5~26_cout\); + +-- Location: LABCELL_X16_Y5_N33 +\myVirtualToplevel|UART1|Add5~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add5~17_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~26_cout\ )) +-- \myVirtualToplevel|UART1|Add5~18\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~26_cout\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|UART1|Add5~26_cout\, + sumout => \myVirtualToplevel|UART1|Add5~17_sumout\, + cout => \myVirtualToplevel|UART1|Add5~18\); + +-- Location: LABCELL_X16_Y5_N36 +\myVirtualToplevel|UART1|Add5~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add5~21_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~18\ )) +-- \myVirtualToplevel|UART1|Add5~22\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|UART1|Add5~18\, + sumout => \myVirtualToplevel|UART1|Add5~21_sumout\, + cout => \myVirtualToplevel|UART1|Add5~22\); + +-- Location: LABCELL_X16_Y5_N39 +\myVirtualToplevel|UART1|Add5~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add5~9_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~22\ )) +-- \myVirtualToplevel|UART1|Add5~10\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|UART1|Add5~22\, + sumout => \myVirtualToplevel|UART1|Add5~9_sumout\, + cout => \myVirtualToplevel|UART1|Add5~10\); + +-- Location: LABCELL_X16_Y5_N42 +\myVirtualToplevel|UART1|Add5~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add5~13_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~10\ )) +-- \myVirtualToplevel|UART1|Add5~14\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(5), + cin => \myVirtualToplevel|UART1|Add5~10\, + sumout => \myVirtualToplevel|UART1|Add5~13_sumout\, + cout => \myVirtualToplevel|UART1|Add5~14\); + +-- Location: LABCELL_X16_Y5_N45 +\myVirtualToplevel|UART1|Add5~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add5~1_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~14\ )) +-- \myVirtualToplevel|UART1|Add5~2\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(6), + cin => \myVirtualToplevel|UART1|Add5~14\, + sumout => \myVirtualToplevel|UART1|Add5~1_sumout\, + cout => \myVirtualToplevel|UART1|Add5~2\); + +-- Location: LABCELL_X16_Y5_N48 +\myVirtualToplevel|UART1|Add5~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add5~5_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(7), + cin => \myVirtualToplevel|UART1|Add5~2\, + sumout => \myVirtualToplevel|UART1|Add5~5_sumout\); + +-- Location: LABCELL_X14_Y5_N0 +\myVirtualToplevel|UART1|RX_INTR~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_INTR~2_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( (\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) $ (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1)))) +-- ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) $ (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010100000101000001010000010100000010100000101000001010000010100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0), + combout => \myVirtualToplevel|UART1|RX_INTR~2_combout\); + +-- Location: LABCELL_X16_Y5_N21 +\myVirtualToplevel|UART1|RX_INTR~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_INTR~3_combout\ = ( \myVirtualToplevel|UART1|Add5~21_sumout\ & ( (\myVirtualToplevel|UART1|RX_INTR~2_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) $ +-- (\myVirtualToplevel|UART1|Add5~17_sumout\)))) ) ) # ( !\myVirtualToplevel|UART1|Add5~21_sumout\ & ( (\myVirtualToplevel|UART1|RX_INTR~2_combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) $ +-- (\myVirtualToplevel|UART1|Add5~17_sumout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000010000000000100000000100100000000100000000001000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2), + datab => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~2_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3), + datad => \myVirtualToplevel|UART1|ALT_INV_Add5~17_sumout\, + datae => \myVirtualToplevel|UART1|ALT_INV_Add5~21_sumout\, + combout => \myVirtualToplevel|UART1|RX_INTR~3_combout\); + +-- Location: LABCELL_X16_Y5_N6 +\myVirtualToplevel|UART1|RX_INTR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_INTR~1_combout\ = ( \myVirtualToplevel|UART1|Add5~9_sumout\ & ( (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) $ (\myVirtualToplevel|UART1|Add5~13_sumout\))) ) ) # ( +-- !\myVirtualToplevel|UART1|Add5~9_sumout\ & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) $ (\myVirtualToplevel|UART1|Add5~13_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000001010101000000000101001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(4), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(5), + datad => \myVirtualToplevel|UART1|ALT_INV_Add5~13_sumout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add5~9_sumout\, + combout => \myVirtualToplevel|UART1|RX_INTR~1_combout\); + +-- Location: LABCELL_X16_Y5_N24 +\myVirtualToplevel|UART1|RX_INTR~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_INTR~4_combout\ = ( \myVirtualToplevel|UART1|RX_INTR~3_combout\ & ( \myVirtualToplevel|UART1|RX_INTR~1_combout\ & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART1|Add5~1_sumout\ & +-- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) $ (\myVirtualToplevel|UART1|Add5~5_sumout\)))) # (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) & (\myVirtualToplevel|UART1|Add5~1_sumout\ & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) $ +-- (\myVirtualToplevel|UART1|Add5~5_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001000001001000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6), + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7), + datac => \myVirtualToplevel|UART1|ALT_INV_Add5~5_sumout\, + datad => \myVirtualToplevel|UART1|ALT_INV_Add5~1_sumout\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~3_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~1_combout\, + combout => \myVirtualToplevel|UART1|RX_INTR~4_combout\); + +-- Location: LABCELL_X16_Y6_N12 +\myVirtualToplevel|UART1|RX_INTR~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_INTR~5_combout\ = ( \myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ & ( (\myVirtualToplevel|UART1|RX_INTR~0_combout\ & ((\myVirtualToplevel|UART1|RX_INTR~4_combout\) # (\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\))) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ & ( (\myVirtualToplevel|UART1|RX_INTR~0_combout\ & (((\myVirtualToplevel|UART1|RX_INTR~4_combout\) # (\myVirtualToplevel|UART1|Equal2~4_combout\)) # (\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001010101010101000101010101010100010001010101010001000101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_Equal2~4_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~4_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~DUPLICATE_q\, + combout => \myVirtualToplevel|UART1|RX_INTR~5_combout\); + +-- Location: FF_X16_Y6_N13 +\myVirtualToplevel|UART1|RX_INTR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_INTR~5_combout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_INTR~q\); + +-- Location: LABCELL_X12_Y6_N51 +\myVirtualToplevel|UART0|RX_INTR~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_INTR~2_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) $ (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1)))) +-- ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) $ (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101101000000000010110100000000000000000010110100000000001011010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(0), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|UART0|RX_INTR~2_combout\); + +-- Location: MLABCELL_X9_Y6_N0 +\myVirtualToplevel|UART0|Add5~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add5~26_cout\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1), + cin => GND, + cout => \myVirtualToplevel|UART0|Add5~26_cout\); + +-- Location: MLABCELL_X9_Y6_N3 +\myVirtualToplevel|UART0|Add5~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add5~17_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~26_cout\ )) +-- \myVirtualToplevel|UART0|Add5~18\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~26_cout\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|UART0|Add5~26_cout\, + sumout => \myVirtualToplevel|UART0|Add5~17_sumout\, + cout => \myVirtualToplevel|UART0|Add5~18\); + +-- Location: MLABCELL_X9_Y6_N6 +\myVirtualToplevel|UART0|Add5~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add5~21_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~18\ )) +-- \myVirtualToplevel|UART0|Add5~22\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|UART0|Add5~18\, + sumout => \myVirtualToplevel|UART0|Add5~21_sumout\, + cout => \myVirtualToplevel|UART0|Add5~22\); + +-- Location: MLABCELL_X9_Y6_N54 +\myVirtualToplevel|UART0|RX_INTR~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_INTR~3_combout\ = ( \myVirtualToplevel|UART0|Add5~21_sumout\ & ( (\myVirtualToplevel|UART0|RX_INTR~2_combout\ & (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) $ +-- (\myVirtualToplevel|UART0|Add5~17_sumout\)))) ) ) # ( !\myVirtualToplevel|UART0|Add5~21_sumout\ & ( (\myVirtualToplevel|UART0|RX_INTR~2_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) $ +-- (\myVirtualToplevel|UART0|Add5~17_sumout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000010000010000000001000000000100000000010000010000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~2_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3), + datad => \myVirtualToplevel|UART0|ALT_INV_Add5~17_sumout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_Add5~21_sumout\, + combout => \myVirtualToplevel|UART0|RX_INTR~3_combout\); + +-- Location: MLABCELL_X9_Y6_N9 +\myVirtualToplevel|UART0|Add5~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add5~9_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~22\ )) +-- \myVirtualToplevel|UART0|Add5~10\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|UART0|Add5~22\, + sumout => \myVirtualToplevel|UART0|Add5~9_sumout\, + cout => \myVirtualToplevel|UART0|Add5~10\); + +-- Location: MLABCELL_X9_Y6_N12 +\myVirtualToplevel|UART0|Add5~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add5~13_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~10\ )) +-- \myVirtualToplevel|UART0|Add5~14\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(5), + cin => \myVirtualToplevel|UART0|Add5~10\, + sumout => \myVirtualToplevel|UART0|Add5~13_sumout\, + cout => \myVirtualToplevel|UART0|Add5~14\); + +-- Location: MLABCELL_X9_Y6_N15 +\myVirtualToplevel|UART0|Add5~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add5~1_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~14\ )) +-- \myVirtualToplevel|UART0|Add5~2\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(6), + cin => \myVirtualToplevel|UART0|Add5~14\, + sumout => \myVirtualToplevel|UART0|Add5~1_sumout\, + cout => \myVirtualToplevel|UART0|Add5~2\); + +-- Location: MLABCELL_X9_Y6_N36 +\myVirtualToplevel|UART0|RX_INTR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_INTR~1_combout\ = ( \myVirtualToplevel|UART0|Add5~9_sumout\ & ( (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART0|Add5~13_sumout\ $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5)))) ) ) # ( +-- !\myVirtualToplevel|UART0|Add5~9_sumout\ & ( (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART0|Add5~13_sumout\ $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001100000000110000110000000000000000110000110000000011000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_Add5~13_sumout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(5), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4), + dataf => \myVirtualToplevel|UART0|ALT_INV_Add5~9_sumout\, + combout => \myVirtualToplevel|UART0|RX_INTR~1_combout\); + +-- Location: MLABCELL_X9_Y6_N18 +\myVirtualToplevel|UART0|Add5~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add5~5_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(7), + cin => \myVirtualToplevel|UART0|Add5~2\, + sumout => \myVirtualToplevel|UART0|Add5~5_sumout\); + +-- Location: MLABCELL_X9_Y6_N48 +\myVirtualToplevel|UART0|RX_INTR~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_INTR~4_combout\ = ( \myVirtualToplevel|UART0|RX_INTR~1_combout\ & ( \myVirtualToplevel|UART0|Add5~5_sumout\ & ( (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & (\myVirtualToplevel|UART0|RX_INTR~3_combout\ & +-- (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) $ (\myVirtualToplevel|UART0|Add5~1_sumout\)))) ) ) ) # ( \myVirtualToplevel|UART0|RX_INTR~1_combout\ & ( !\myVirtualToplevel|UART0|Add5~5_sumout\ & ( (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & +-- (\myVirtualToplevel|UART0|RX_INTR~3_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) $ (\myVirtualToplevel|UART0|Add5~1_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010000000010000000000000000000000001000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6), + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~3_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_Add5~1_sumout\, + datae => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~1_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_Add5~5_sumout\, + combout => \myVirtualToplevel|UART0|RX_INTR~4_combout\); + +-- Location: MLABCELL_X9_Y6_N24 +\myVirtualToplevel|UART0|RX_INTR~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_INTR~5_combout\ = ( \myVirtualToplevel|UART0|RX_DATA_READY~q\ & ( (\myVirtualToplevel|UART0|RX_INTR~0_combout\ & ((\myVirtualToplevel|UART0|RX_INTR~4_combout\) # (\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\))) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_DATA_READY~q\ & ( (\myVirtualToplevel|UART0|RX_INTR~0_combout\ & (((\myVirtualToplevel|UART0|RX_INTR~4_combout\) # (\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\)) # (\myVirtualToplevel|UART0|Equal2~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001111111000000000111111100000000001111110000000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Equal2~4_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~4_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\, + combout => \myVirtualToplevel|UART0|RX_INTR~5_combout\); + +-- Location: FF_X9_Y6_N26 +\myVirtualToplevel|UART0|RX_INTR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_INTR~5_combout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_INTR~q\); + +-- Location: FF_X10_Y5_N5 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER\(5), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(21)); + +-- Location: FF_X10_Y5_N32 +\myVirtualToplevel|UART0|RX_FIFO~22\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER\(5), + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO~22_q\); + +-- Location: LABCELL_X10_Y5_N30 +\myVirtualToplevel|UART0|RX_DATA~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA~4_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(5) & ( \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & +-- ((\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a4\))) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (\myVirtualToplevel|UART0|RX_FIFO~22_q\)) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(5) & ( +-- \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ((\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a4\))) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & +-- (\myVirtualToplevel|UART0|RX_FIFO~22_q\)) ) ) ) # ( \myVirtualToplevel|UART0|RX_BUFFER\(5) & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) # (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(21)) ) ) +-- ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(5) & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(21) & !\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(21), + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~22_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\, + datad => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datae => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(5), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA~4_combout\); + +-- Location: MLABCELL_X9_Y5_N36 +\myVirtualToplevel|UART0|RX_DATA[4]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA[4]~5_combout\ = ( \myVirtualToplevel|UART0|RX_DATA~4_combout\ & ( ((\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\ & \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(4)) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_DATA~4_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA\(4) & ((!\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\) # (!\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(4), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA~4_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA[4]~5_combout\); + +-- Location: FF_X9_Y5_N37 +\myVirtualToplevel|UART0|RX_DATA[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_DATA[4]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_DATA\(4)); + +-- Location: LABCELL_X12_Y9_N9 +\myVirtualToplevel|IO_DATA_READ~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~33_combout\ = ( \myVirtualToplevel|UART0|RX_DATA\(4) & ( \myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|UART0|RX_INTR~q\) ) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_DATA\(4) & ( \myVirtualToplevel|UART0_CS~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|UART0|RX_INTR~q\) ) ) ) # ( \myVirtualToplevel|UART0|RX_DATA\(4) & ( !\myVirtualToplevel|UART0_CS~combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|UART1|RX_DATA\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART1|RX_INTR~q\))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_DATA\(4) & ( +-- !\myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|UART1|RX_DATA\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART1|RX_INTR~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(4), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~q\, + datae => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(4), + dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\, + combout => \myVirtualToplevel|IO_DATA_READ~33_combout\); + +-- Location: LABCELL_X10_Y7_N33 +\myVirtualToplevel|UART1|Add9~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~24_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(4), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|Add9~24_combout\); + +-- Location: LABCELL_X12_Y7_N27 +\myVirtualToplevel|UART1|Add9~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~28_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & ( +-- \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) ) ) ) # ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & ( !\myVirtualToplevel|UART1_CS~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3), + datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|Add9~28_combout\); + +-- Location: MLABCELL_X13_Y7_N12 +\myVirtualToplevel|UART1|Add9~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~17_sumout\ = SUM(( \myVirtualToplevel|UART1|Add9~28_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3))))) ) + ( \myVirtualToplevel|UART1|Add9~22\ )) +-- \myVirtualToplevel|UART1|Add9~18\ = CARRY(( \myVirtualToplevel|UART1|Add9~28_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3))))) ) + ( \myVirtualToplevel|UART1|Add9~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000011110111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(3), + datad => \myVirtualToplevel|UART1|ALT_INV_Add9~28_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|UART1|Add9~22\, + sumout => \myVirtualToplevel|UART1|Add9~17_sumout\, + cout => \myVirtualToplevel|UART1|Add9~18\); + +-- Location: MLABCELL_X13_Y7_N15 +\myVirtualToplevel|UART1|Add9~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~1_sumout\ = SUM(( \myVirtualToplevel|UART1|Add9~24_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4))))) ) + ( \myVirtualToplevel|UART1|Add9~18\ )) +-- \myVirtualToplevel|UART1|Add9~2\ = CARRY(( \myVirtualToplevel|UART1|Add9~24_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4))))) ) + ( \myVirtualToplevel|UART1|Add9~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000011110111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(4), + datad => \myVirtualToplevel|UART1|ALT_INV_Add9~24_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|UART1|Add9~18\, + sumout => \myVirtualToplevel|UART1|Add9~1_sumout\, + cout => \myVirtualToplevel|UART1|Add9~2\); + +-- Location: LABCELL_X12_Y10_N30 +\myVirtualToplevel|IO_DATA_READ[4]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[4]~36_combout\ = ( \myVirtualToplevel|IO_DATA_READ~33_combout\ & ( \myVirtualToplevel|UART1|Add9~1_sumout\ & ( (!\myVirtualToplevel|TIMER0_CS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ & (((\myVirtualToplevel|IO_DATA_READ[4]~35_combout\)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~33_combout\ & ( \myVirtualToplevel|UART1|Add9~1_sumout\ & ( +-- (!\myVirtualToplevel|TIMER0_CS~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ & (((\myVirtualToplevel|IO_DATA_READ[4]~35_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|IO_DATA_READ~33_combout\ & ( !\myVirtualToplevel|UART1|Add9~1_sumout\ & ( (!\myVirtualToplevel|TIMER0_CS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ & +-- ((\myVirtualToplevel|IO_DATA_READ[4]~35_combout\))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~33_combout\ & ( !\myVirtualToplevel|UART1|Add9~1_sumout\ & ( (\myVirtualToplevel|TIMER0_CS~1_combout\ & \myVirtualToplevel|IO_DATA_READ[4]~35_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111101000001010111101000000010011111110000011101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ[4]~35_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ~33_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add9~1_sumout\, + combout => \myVirtualToplevel|IO_DATA_READ[4]~36_combout\); + +-- Location: FF_X12_Y10_N31 +\myVirtualToplevel|IO_DATA_READ[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ[4]~36_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(4)); + +-- Location: LABCELL_X20_Y13_N57 +\myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739_BDD8740\ = ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(4) ) ) # ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(4) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(4), + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(4), + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739_BDD8740\); + +-- Location: LABCELL_X25_Y9_N0 +\myVirtualToplevel|TIMER:TIMER1|Add0~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~57_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~58\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(0), + cin => GND, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~57_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~58\); + +-- Location: FF_X25_Y9_N2 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~57_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(0)); + +-- Location: LABCELL_X25_Y9_N3 +\myVirtualToplevel|TIMER:TIMER1|Add0~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~45_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(1) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~58\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~46\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(1) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(1), + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~58\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~45_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~46\); + +-- Location: FF_X25_Y9_N5 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~45_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(1)); + +-- Location: LABCELL_X25_Y9_N6 +\myVirtualToplevel|TIMER:TIMER1|Add0~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~41_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(2) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~46\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~42\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(2) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(2), + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~46\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~41_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~42\); + +-- Location: FF_X25_Y9_N8 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~41_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(2)); + +-- Location: LABCELL_X25_Y9_N9 +\myVirtualToplevel|TIMER:TIMER1|Add0~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~29_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~42\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~30\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~42\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~29_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~30\); + +-- Location: FF_X25_Y9_N11 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y9_N12 +\myVirtualToplevel|TIMER:TIMER1|Add0~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~25_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(4) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~30\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~26\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(4) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(4), + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~30\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~25_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~26\); + +-- Location: FF_X25_Y9_N14 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(4)); + +-- Location: LABCELL_X25_Y9_N15 +\myVirtualToplevel|TIMER:TIMER1|Add0~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~37_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(5) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~26\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~38\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(5) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(5), + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~26\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~37_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~38\); + +-- Location: FF_X25_Y9_N17 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~37_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(5)); + +-- Location: LABCELL_X25_Y9_N18 +\myVirtualToplevel|TIMER:TIMER1|Add0~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~21_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(6) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~38\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~22\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(6) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(6), + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~38\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~21_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~22\); + +-- Location: FF_X25_Y9_N20 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(6)); + +-- Location: LABCELL_X25_Y9_N21 +\myVirtualToplevel|TIMER:TIMER1|Add0~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~61_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(7) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~22\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~62\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(7) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(7), + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~22\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~61_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~62\); + +-- Location: FF_X25_Y9_N23 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~61_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(7)); + +-- Location: LABCELL_X25_Y9_N24 +\myVirtualToplevel|TIMER:TIMER1|Add0~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~17_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(8) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~62\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~18\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(8) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(8), + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~62\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~17_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~18\); + +-- Location: FF_X25_Y9_N26 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(8)); + +-- Location: LABCELL_X25_Y9_N27 +\myVirtualToplevel|TIMER:TIMER1|Add0~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~33_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(9) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~18\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~34\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(9) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(9), + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~18\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~33_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~34\); + +-- Location: FF_X25_Y9_N29 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~33_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(9)); + +-- Location: LABCELL_X25_Y9_N30 +\myVirtualToplevel|TIMER:TIMER1|Add0~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~13_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~34\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~14\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[10]~DUPLICATE_q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~34\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~13_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~14\); + +-- Location: FF_X25_Y9_N32 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y9_N33 +\myVirtualToplevel|TIMER:TIMER1|Add0~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~9_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(11) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~14\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~10\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(11) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(11), + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~14\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~9_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~10\); + +-- Location: FF_X25_Y9_N35 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(11)); + +-- Location: LABCELL_X25_Y9_N36 +\myVirtualToplevel|TIMER:TIMER1|Add0~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~5_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(12) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~10\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~6\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(12) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(12), + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~10\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~5_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~6\); + +-- Location: FF_X25_Y9_N37 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(12)); + +-- Location: LABCELL_X25_Y9_N39 +\myVirtualToplevel|TIMER:TIMER1|Add0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~1_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(13) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~6\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~2\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(13) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(13), + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~6\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~1_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~2\); + +-- Location: FF_X25_Y9_N41 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(13)); + +-- Location: LABCELL_X25_Y9_N42 +\myVirtualToplevel|TIMER:TIMER1|Add0~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~53_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(14) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~2\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add0~54\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(14) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(14), + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~2\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~53_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add0~54\); + +-- Location: FF_X25_Y9_N44 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~53_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(14)); + +-- Location: LABCELL_X25_Y9_N45 +\myVirtualToplevel|TIMER:TIMER1|Add0~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add0~49_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(15) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(15), + cin => \myVirtualToplevel|TIMER:TIMER1|Add0~54\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~49_sumout\); + +-- Location: FF_X25_Y9_N47 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~49_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(15)); + +-- Location: LABCELL_X25_Y9_N57 +\myVirtualToplevel|TIMER:TIMER1|Equal0~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal0~3_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(14) & ( (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(0) & (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(15) & +-- !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(7))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(0), + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(15), + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(7), + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(14), + combout => \myVirtualToplevel|TIMER:TIMER1|Equal0~3_combout\); + +-- Location: FF_X25_Y9_N10 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(3)); + +-- Location: LABCELL_X25_Y9_N51 +\myVirtualToplevel|TIMER:TIMER1|Equal0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal0~1_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(8) & ( (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(6) & (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(4) & +-- !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(3))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(6), + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(4), + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(3), + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(8), + combout => \myVirtualToplevel|TIMER:TIMER1|Equal0~1_combout\); + +-- Location: LABCELL_X25_Y9_N54 +\myVirtualToplevel|TIMER:TIMER1|Equal0~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal0~2_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(2) & ( (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(5) & (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(9) & +-- !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(1))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(5), + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(9), + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(1), + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(2), + combout => \myVirtualToplevel|TIMER:TIMER1|Equal0~2_combout\); + +-- Location: FF_X25_Y9_N31 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(10)); + +-- Location: FF_X25_Y9_N40 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]~DUPLICATE_q\); + +-- Location: FF_X25_Y9_N34 +\myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add0~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y9_N12 +\myVirtualToplevel|TIMER:TIMER1|Equal0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal0~0_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]~DUPLICATE_q\ & ( !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(12) & ( (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(10) & +-- !\myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(10), + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[13]~DUPLICATE_q\, + datae => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(12), + combout => \myVirtualToplevel|TIMER:TIMER1|Equal0~0_combout\); + +-- Location: LABCELL_X25_Y9_N48 +\myVirtualToplevel|TIMER:TIMER1|Equal0~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Equal0~0_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|Equal0~3_combout\ & (\myVirtualToplevel|TIMER:TIMER1|Equal0~1_combout\ & +-- \myVirtualToplevel|TIMER:TIMER1|Equal0~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~3_combout\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~1_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~2_combout\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~0_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\); + +-- Location: FF_X25_Y9_N49 +\myVirtualToplevel|TIMER:TIMER1|prescaled_tick\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|prescaled_tick~q\); + +-- Location: LABCELL_X21_Y11_N18 +\myVirtualToplevel|TIMER_REG_REQ~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER_REG_REQ~feeder_combout\ = VCC + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + combout => \myVirtualToplevel|TIMER_REG_REQ~feeder_combout\); + +-- Location: LABCELL_X16_Y11_N45 +\myVirtualToplevel|process_0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|process_0~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( (\myVirtualToplevel|TIMER0_CS~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + combout => \myVirtualToplevel|process_0~0_combout\); + +-- Location: FF_X21_Y11_N19 +\myVirtualToplevel|TIMER_REG_REQ\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER_REG_REQ~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER_REG_REQ~q\); + +-- Location: LABCELL_X14_Y11_N42 +\myVirtualToplevel|TIMER:TIMER1|Mux2~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\); + +-- Location: LABCELL_X14_Y11_N0 +\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~1_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|timer_enabled\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) ) ) # ( \myVirtualToplevel|TIMER:TIMER1|timer_enabled\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|TIMER_REG_REQ~q\) # ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|TIMER:TIMER1|timer_enabled\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (\myVirtualToplevel|TIMER_REG_REQ~q\ & (\myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000111011111111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_TIMER_REG_REQ~q\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~1_combout\); + +-- Location: FF_X14_Y11_N1 +\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_enabled\(0)); + +-- Location: LABCELL_X20_Y11_N6 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|timer_enabled\(0) & ( \myVirtualToplevel|TIMER:TIMER1|prescaled_tick~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescaled_tick~q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled\(0), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\); + +-- Location: LABCELL_X19_Y8_N0 +\myVirtualToplevel|TIMER:TIMER1|Add1~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~85_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~86\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][0]~DUPLICATE_q\, + cin => GND, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~85_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~86\); + +-- Location: MLABCELL_X18_Y11_N54 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ = ( \myVirtualToplevel|RESET_n~q\ & ( \myVirtualToplevel|TIMER_REG_REQ~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ALT_INV_TIMER_REG_REQ~q\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\); + +-- Location: LABCELL_X14_Y11_N54 +\myVirtualToplevel|TIMER:TIMER1|timer_index[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_index[0]~0_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|timer_index\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) ) ) # ( \myVirtualToplevel|TIMER:TIMER1|timer_index\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)))) ) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|timer_index\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & +-- (\myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_index\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_index[0]~0_combout\); + +-- Location: FF_X14_Y11_N55 +\myVirtualToplevel|TIMER:TIMER1|timer_index[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_index[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_index\(0)); + +-- Location: MLABCELL_X18_Y9_N45 +\myVirtualToplevel|TIMER:TIMER1|Mux2~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\); + +-- Location: MLABCELL_X18_Y9_N6 +\myVirtualToplevel|TIMER:TIMER1|Mux2~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\ & !\myVirtualToplevel|TIMER:TIMER1|timer_index\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000000000000000011000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~1_combout\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_index\(0), + datae => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~0_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\); + +-- Location: MLABCELL_X18_Y7_N9 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~22_combout\); + +-- Location: FF_X18_Y7_N10 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~22_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~q\); + +-- Location: FF_X19_Y8_N2 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~85_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y8_N3 +\myVirtualToplevel|TIMER:TIMER1|Add1~97\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~97_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~86\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~98\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][1]~DUPLICATE_q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~86\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~97_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~98\); + +-- Location: MLABCELL_X18_Y8_N45 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~25_combout\); + +-- Location: FF_X18_Y8_N46 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~q\); + +-- Location: FF_X19_Y8_N5 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~97_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y8_N6 +\myVirtualToplevel|TIMER:TIMER1|Add1~101\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~101_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~98\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~102\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~98\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][2]~DUPLICATE_q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~98\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~101_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~102\); + +-- Location: LABCELL_X17_Y8_N6 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~26_combout\ = (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & (((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~q\)))) # (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & +-- ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~q\))) # (\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111101111000000011110111100000001111011110000000111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][2]~q\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~26_combout\); + +-- Location: FF_X17_Y8_N7 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~26_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~q\); + +-- Location: FF_X19_Y8_N8 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~101_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y8_N9 +\myVirtualToplevel|TIMER:TIMER1|Add1~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~69_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~102\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~70\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~102\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][3]~DUPLICATE_q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~102\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~69_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~70\); + +-- Location: MLABCELL_X18_Y7_N18 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~18_combout\); + +-- Location: FF_X18_Y7_N19 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~18_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~q\); + +-- Location: FF_X19_Y8_N11 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~69_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y8_N12 +\myVirtualToplevel|TIMER:TIMER1|Add1~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~73_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~70\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~74\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][4]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~70\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~73_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~74\); + +-- Location: MLABCELL_X18_Y8_N12 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~19_combout\ = (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & (((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~q\)))) # (\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & +-- ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~q\))) # (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111101111000000011110111100000001111011110000000111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][4]~q\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~19_combout\); + +-- Location: FF_X18_Y8_N13 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~19_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~q\); + +-- Location: FF_X19_Y8_N14 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~73_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]~q\); + +-- Location: LABCELL_X19_Y8_N15 +\myVirtualToplevel|TIMER:TIMER1|Add1~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~77_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~74\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~78\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][5]~DUPLICATE_q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~74\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~77_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~78\); + +-- Location: LABCELL_X20_Y8_N33 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~20_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\ & ( \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5)) ) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\ & ( \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5)) ) ) ) # ( \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\ & ( !\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + datae => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][5]~q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~20_combout\); + +-- Location: FF_X20_Y8_N35 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\); + +-- Location: FF_X19_Y8_N17 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~77_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y8_N18 +\myVirtualToplevel|TIMER:TIMER1|Add1~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~89_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~78\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~90\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][6]~DUPLICATE_q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~78\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~89_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~90\); + +-- Location: MLABCELL_X18_Y8_N3 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~23_combout\); + +-- Location: FF_X18_Y8_N4 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~23_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~q\); + +-- Location: FF_X19_Y8_N20 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~89_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y8_N21 +\myVirtualToplevel|TIMER:TIMER1|Add1~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~93_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~90\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~94\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][7]~DUPLICATE_q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~90\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~93_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~94\); + +-- Location: MLABCELL_X18_Y8_N9 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~24_combout\); + +-- Location: FF_X18_Y8_N10 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~q\); + +-- Location: FF_X19_Y8_N23 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~93_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y8_N24 +\myVirtualToplevel|TIMER:TIMER1|Add1~113\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~113_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~94\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~114\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~94\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][8]~DUPLICATE_q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~94\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~113_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~114\); + +-- Location: MLABCELL_X18_Y8_N6 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(8), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~29_combout\); + +-- Location: FF_X18_Y8_N7 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~29_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~q\); + +-- Location: FF_X19_Y8_N26 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~113_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y8_N27 +\myVirtualToplevel|TIMER:TIMER1|Add1~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~9_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~114\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~10\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~114\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][9]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~114\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~9_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~10\); + +-- Location: MLABCELL_X18_Y7_N36 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\ & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[9]~DUPLICATE_q\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~3_combout\); + +-- Location: FF_X18_Y7_N37 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~q\); + +-- Location: FF_X19_Y8_N29 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~9_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]~q\); + +-- Location: LABCELL_X19_Y8_N30 +\myVirtualToplevel|TIMER:TIMER1|Add1~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~13_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~10\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~14\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][10]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~10\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~13_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~14\); + +-- Location: MLABCELL_X18_Y7_N21 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(10), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~4_combout\); + +-- Location: FF_X18_Y7_N22 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~q\); + +-- Location: FF_X19_Y8_N31 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~13_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]~q\); + +-- Location: LABCELL_X19_Y8_N33 +\myVirtualToplevel|TIMER:TIMER1|Add1~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~33_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~14\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~34\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][11]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~14\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~33_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~34\); + +-- Location: MLABCELL_X18_Y8_N33 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~9_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~q\))) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11))) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(11), + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][11]~q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~9_combout\); + +-- Location: FF_X18_Y8_N34 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~9_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~q\); + +-- Location: FF_X19_Y8_N35 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~33_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]~q\); + +-- Location: LABCELL_X19_Y8_N36 +\myVirtualToplevel|TIMER:TIMER1|Add1~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~81_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~34\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~82\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][12]~DUPLICATE_q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~34\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~81_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~82\); + +-- Location: MLABCELL_X18_Y8_N42 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(12), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~21_combout\); + +-- Location: FF_X18_Y8_N43 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~21_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~q\); + +-- Location: FF_X19_Y8_N38 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~81_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y8_N39 +\myVirtualToplevel|TIMER:TIMER1|Add1~105\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~105_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~82\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~106\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][13]~DUPLICATE_q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~82\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~105_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~106\); + +-- Location: MLABCELL_X18_Y8_N30 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(13), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~27_combout\); + +-- Location: FF_X18_Y8_N31 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~27_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~q\); + +-- Location: FF_X19_Y8_N41 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~105_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y8_N42 +\myVirtualToplevel|TIMER:TIMER1|Add1~109\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~109_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~106\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~110\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~106\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][14]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~106\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~109_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~110\); + +-- Location: MLABCELL_X18_Y8_N0 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~28_combout\ = (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & (((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~q\)))) # (\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & +-- ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~q\))) # (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111101111000000011110111100000001111011110000000111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][14]~q\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~28_combout\); + +-- Location: FF_X18_Y8_N1 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~28_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~q\); + +-- Location: FF_X19_Y8_N43 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~109_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]~q\); + +-- Location: LABCELL_X19_Y8_N45 +\myVirtualToplevel|TIMER:TIMER1|Add1~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~41_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~110\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~42\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~110\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][15]~DUPLICATE_q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~110\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~41_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~42\); + +-- Location: MLABCELL_X18_Y8_N15 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][15]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(15), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~11_combout\); + +-- Location: FF_X18_Y8_N16 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~11_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~q\); + +-- Location: FF_X19_Y8_N47 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~41_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y8_N48 +\myVirtualToplevel|TIMER:TIMER1|Add1~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~45_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~42\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~46\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][16]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~42\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~45_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~46\); + +-- Location: LABCELL_X20_Y8_N12 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111101000000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][16]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~12_combout\); + +-- Location: FF_X20_Y8_N13 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~q\); + +-- Location: FF_X19_Y8_N50 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~45_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]~q\); + +-- Location: LABCELL_X19_Y8_N51 +\myVirtualToplevel|TIMER:TIMER1|Add1~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~65_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~46\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~66\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][17]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~46\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~65_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~66\); + +-- Location: LABCELL_X20_Y8_N15 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~17_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~q\))) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\)) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]~6_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][17]~q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~17_combout\); + +-- Location: FF_X20_Y8_N17 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~q\); + +-- Location: FF_X19_Y8_N52 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~65_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]~q\); + +-- Location: LABCELL_X19_Y8_N54 +\myVirtualToplevel|TIMER:TIMER1|Add1~117\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~117_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~66\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~118\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][18]~DUPLICATE_q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~66\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~117_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~118\); + +-- Location: LABCELL_X17_Y8_N9 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][18]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~30_combout\); + +-- Location: FF_X17_Y8_N10 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~30_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~q\); + +-- Location: FF_X19_Y8_N56 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~117_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y8_N57 +\myVirtualToplevel|TIMER:TIMER1|Add1~121\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~121_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~118\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~122\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~118\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][19]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~118\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~121_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~122\); + +-- Location: LABCELL_X20_Y8_N0 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~31_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~q\))) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\)) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][19]~q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~31_combout\); + +-- Location: FF_X20_Y8_N1 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~31_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~q\); + +-- Location: FF_X19_Y8_N59 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~121_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~q\); + +-- Location: LABCELL_X19_Y7_N0 +\myVirtualToplevel|TIMER:TIMER1|Add1~125\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~125_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~122\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~126\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~122\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][20]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~122\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~125_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~126\); + +-- Location: MLABCELL_X18_Y7_N12 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][20]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]~17_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~32_combout\); + +-- Location: FF_X18_Y7_N13 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~32_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~q\); + +-- Location: FF_X19_Y7_N1 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~125_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]~q\); + +-- Location: LABCELL_X19_Y7_N3 +\myVirtualToplevel|TIMER:TIMER1|Add1~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~25_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~126\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~26\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~126\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][21]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~126\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~25_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~26\); + +-- Location: MLABCELL_X18_Y7_N54 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][21]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]~15_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~7_combout\); + +-- Location: FF_X18_Y7_N55 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~q\); + +-- Location: FF_X19_Y7_N5 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~25_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]~q\); + +-- Location: LABCELL_X19_Y7_N6 +\myVirtualToplevel|TIMER:TIMER1|Add1~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~61_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][22]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~26\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~62\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][22]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][22]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~26\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~61_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~62\); + +-- Location: FF_X9_Y18_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_NEW_REG913\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM914\); + +-- Location: FF_X18_Y12_N5 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_NEW_REG72\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_OTERM73\); + +-- Location: FF_X19_Y12_N14 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux94~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y12_N57 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM47\ ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_OTERM73\ ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_OTERM73\ ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_OTERM73\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[22]_OTERM73\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM47\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6_combout\); + +-- Location: LABCELL_X20_Y10_N45 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]~16_combout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2_combout\); + +-- Location: M10K_X22_Y12_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 6, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 6, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\); + +-- Location: M10K_X30_Y12_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002222222222200000000E1001F6FB3DEFDB8F177BBED818006E75B773EF6779FDEF7BDEBB5E99025400399DBEBBEF7F7AF77BD75F7DDEEEF7F57BFD7574005FFFE025C0B5B71FBA9F90D21E0190E87E1D9A4B38D848D81020C08334E7D2000000D6FD51EF4D2A70E7110E71D851261CBDC7869B07013CAA1F", + mem_init2 => "208E646650468C2063EAE0D8293EFE990D82433E5743716891D9411A211CA0A7EB73C79B3AB6326CB2BC58B4B84A498AC2C291410208A41395AEA5228C948F9C0E414263D6C2AAADEBA15556F74C105E1E442532849E064A583ACE4624B04F4AE27494010465C9907827BE450CC9381B667B61B1D6A25BDE4C9796A454CF0709875E849A8089D01C2D6EE6441D50B51D50848538F5D2601258EED828E6A1F1614C125C6BC18B2D1C234A13FBC825CA048AD0F5CF4E8EA88B9F22E75417D25C0555356E9A7419D12D4B447A0A45654D14F51D0F18BA6974C25EA02688C2275BCA467C23D54390C62AAC4AA650A54C74848FF35E1C9453CC6DEC61D60E80A3A21D", + mem_init1 => "13204000B01B4A0C528919E5C41C56A0D4DA13C909832EA93F314E481B0A69C4043525653286C2A468A2923A4C38FF6440630C4100A8BF11A6C214C7FA28C3312090CCCD42491E0202E792DF18928C3774166203EE886C56BE3049591180C03C5A48A14D4927C8852201EA28F09D2382FA8420540310B3A85046222C0F0CC884C7B2DBDC37E49A811485D0051D417F0E191E3451591BB905290D144B30582D802112101880A97215245B518CAEE72E25B2D14C4F03FA4D048AC40261251C4354982B99D4C7BE6288F28C2222804651C2850819410A1AA38528E18D4ADC95CCA88419C0504BF530201472B88C460A342BE2D712E100F504655B0CE75663088565", + mem_init0 => "4B72C463C1AF521006BF82D0D7A1080A4C38DAC0394EF01A290C784C22008029D163F2618509059E3E80A93D999E54FAFDBF088A5662B8D05F854E0C015234E2A952414E7A70555304D48B01009197CB8A0CBF2496382B22643871E3C3862611F9D0A2416A34482D4689059400C0603010E22463CD652F24518B286745598306BA458C1038C6304500002A4924840E35D17181722FB97B6297424E090AA02AAC100504109894B0280042B4556265054008595140D8F2E000015402AAEAAAAEEEAAAAAAAAEEAEEEEE805500AA017402E8FFFFFFFFFFF8000000000000000000FEFB00000000000118684040051106010010000105010200000141012003110000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 6, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 6, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X18_Y12_N0 +\myVirtualToplevel|MEM_DATA_READ[22]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[22]~12_combout\ = ( \myVirtualToplevel|LessThan0~1_combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14~portbdataout\) ) ) ) # ( \myVirtualToplevel|LessThan0~1_combout\ & ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6~portbdataout\ & ( (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14~portbdataout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000111100000000000000001111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\, + datae => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[22]~12_combout\); + +-- Location: LABCELL_X12_Y9_N15 +\myVirtualToplevel|UART0|TX_ENABLE_FIFO~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_ENABLE_FIFO~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]~6_combout\, + combout => \myVirtualToplevel|UART0|TX_ENABLE_FIFO~0_combout\); + +-- Location: FF_X12_Y9_N17 +\myVirtualToplevel|UART0|TX_ENABLE_FIFO\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_ENABLE_FIFO~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_ENABLE~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\); + +-- Location: LABCELL_X10_Y8_N30 +\myVirtualToplevel|UART0|Add8~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add8~9_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|UART0|Add8~10\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(0), + cin => GND, + sumout => \myVirtualToplevel|UART0|Add8~9_sumout\, + cout => \myVirtualToplevel|UART0|Add8~10\); + +-- Location: LABCELL_X12_Y9_N21 +\myVirtualToplevel|UART0|TX_RESET~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_RESET~0_combout\ = ( \myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\))) ) ) # ( !\myVirtualToplevel|UART0_CS~combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111010101111111111101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\, + combout => \myVirtualToplevel|UART0|TX_RESET~0_combout\); + +-- Location: FF_X12_Y9_N23 +\myVirtualToplevel|UART0|TX_RESET\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_RESET~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_RESET~q\); + +-- Location: LABCELL_X10_Y8_N24 +\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~1_combout\ = !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(0), + combout => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~1_combout\); + +-- Location: LABCELL_X17_Y13_N6 +\myVirtualToplevel|Equal3~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal3~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9), + combout => \myVirtualToplevel|Equal3~1_combout\); + +-- Location: LABCELL_X12_Y9_N12 +\myVirtualToplevel|UART0|TX_ENABLE~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_ENABLE~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\, + combout => \myVirtualToplevel|UART0|TX_ENABLE~1_combout\); + +-- Location: FF_X12_Y9_N14 +\myVirtualToplevel|UART0|TX_ENABLE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_ENABLE~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_ENABLE~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_ENABLE~q\); + +-- Location: LABCELL_X12_Y9_N36 +\myVirtualToplevel|UART0|TX_OVERRUN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_OVERRUN~0_combout\ = ( !\myVirtualToplevel|UART0|TX_ENABLE~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000000010001000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + combout => \myVirtualToplevel|UART0|TX_OVERRUN~0_combout\); + +-- Location: LABCELL_X14_Y13_N0 +\myVirtualToplevel|UART0|TX_OVERRUN~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_OVERRUN~1_combout\ = ( \myVirtualToplevel|Equal3~1_combout\ & ( \myVirtualToplevel|UART0|TX_OVERRUN~0_combout\ & ( (\myVirtualToplevel|IO_SELECT~0_combout\ & (\myVirtualToplevel|Equal3~0_combout\ & +-- (\myVirtualToplevel|IO_SELECT~2_combout\ & \myVirtualToplevel|IO_SELECT~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\, + datab => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\, + datae => \myVirtualToplevel|ALT_INV_Equal3~1_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~0_combout\, + combout => \myVirtualToplevel|UART0|TX_OVERRUN~1_combout\); + +-- Location: LABCELL_X12_Y8_N30 +\myVirtualToplevel|UART0|Add6~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add6~22\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(0), + cin => GND, + cout => \myVirtualToplevel|UART0|Add6~22\); + +-- Location: LABCELL_X12_Y8_N33 +\myVirtualToplevel|UART0|Add6~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add6~25_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~22\ )) +-- \myVirtualToplevel|UART0|Add6~26\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(1), + cin => \myVirtualToplevel|UART0|Add6~22\, + sumout => \myVirtualToplevel|UART0|Add6~25_sumout\, + cout => \myVirtualToplevel|UART0|Add6~26\); + +-- Location: LABCELL_X12_Y8_N36 +\myVirtualToplevel|UART0|Add6~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add6~29_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~26\ )) +-- \myVirtualToplevel|UART0|Add6~30\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|UART0|Add6~26\, + sumout => \myVirtualToplevel|UART0|Add6~29_sumout\, + cout => \myVirtualToplevel|UART0|Add6~30\); + +-- Location: LABCELL_X12_Y8_N39 +\myVirtualToplevel|UART0|Add6~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add6~9_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~30\ )) +-- \myVirtualToplevel|UART0|Add6~10\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|UART0|Add6~30\, + sumout => \myVirtualToplevel|UART0|Add6~9_sumout\, + cout => \myVirtualToplevel|UART0|Add6~10\); + +-- Location: LABCELL_X12_Y8_N42 +\myVirtualToplevel|UART0|Add6~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add6~13_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~10\ )) +-- \myVirtualToplevel|UART0|Add6~14\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|UART0|Add6~10\, + sumout => \myVirtualToplevel|UART0|Add6~13_sumout\, + cout => \myVirtualToplevel|UART0|Add6~14\); + +-- Location: LABCELL_X12_Y8_N45 +\myVirtualToplevel|UART0|Add6~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add6~17_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~14\ )) +-- \myVirtualToplevel|UART0|Add6~18\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(5), + cin => \myVirtualToplevel|UART0|Add6~14\, + sumout => \myVirtualToplevel|UART0|Add6~17_sumout\, + cout => \myVirtualToplevel|UART0|Add6~18\); + +-- Location: LABCELL_X12_Y8_N48 +\myVirtualToplevel|UART0|Add6~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add6~1_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~18\ )) +-- \myVirtualToplevel|UART0|Add6~2\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(6), + cin => \myVirtualToplevel|UART0|Add6~18\, + sumout => \myVirtualToplevel|UART0|Add6~1_sumout\, + cout => \myVirtualToplevel|UART0|Add6~2\); + +-- Location: LABCELL_X10_Y8_N48 +\myVirtualToplevel|UART0|Add8~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add8~1_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~30\ )) +-- \myVirtualToplevel|UART0|Add8~2\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(6), + cin => \myVirtualToplevel|UART0|Add8~30\, + sumout => \myVirtualToplevel|UART0|Add8~1_sumout\, + cout => \myVirtualToplevel|UART0|Add8~2\); + +-- Location: LABCELL_X10_Y8_N51 +\myVirtualToplevel|UART0|Add8~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add8~5_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(7), + cin => \myVirtualToplevel|UART0|Add8~2\, + sumout => \myVirtualToplevel|UART0|Add8~5_sumout\); + +-- Location: FF_X10_Y8_N53 +\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add8~5_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7)); + +-- Location: LABCELL_X12_Y8_N51 +\myVirtualToplevel|UART0|Add6~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add6~5_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(7), + cin => \myVirtualToplevel|UART0|Add6~2\, + sumout => \myVirtualToplevel|UART0|Add6~5_sumout\); + +-- Location: FF_X7_Y8_N4 +\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add7~13_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\); + +-- Location: LABCELL_X7_Y8_N0 +\myVirtualToplevel|UART0|Add7~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add7~9_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) ) + ( !VCC )) +-- \myVirtualToplevel|UART0|Add7~10\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(0), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(1), + cin => GND, + sumout => \myVirtualToplevel|UART0|Add7~9_sumout\, + cout => \myVirtualToplevel|UART0|Add7~10\); + +-- Location: FF_X7_Y8_N1 +\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add7~9_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1)); + +-- Location: LABCELL_X12_Y8_N54 +\myVirtualToplevel|UART0|Equal6~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal6~1_combout\ = ( \myVirtualToplevel|UART0|Add6~29_sumout\ & ( \myVirtualToplevel|UART0|Add6~25_sumout\ & ( (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & +-- (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|UART0|Add6~29_sumout\ & ( \myVirtualToplevel|UART0|Add6~25_sumout\ & ( +-- (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- \myVirtualToplevel|UART0|Add6~29_sumout\ & ( !\myVirtualToplevel|UART0|Add6~25_sumout\ & ( (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) $ +-- (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|UART0|Add6~29_sumout\ & ( !\myVirtualToplevel|UART0|Add6~25_sumout\ & ( (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0110000000000000000001100000000000000000011000000000000000000110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(0), + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(1), + datae => \myVirtualToplevel|UART0|ALT_INV_Add6~29_sumout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_Add6~25_sumout\, + combout => \myVirtualToplevel|UART0|Equal6~1_combout\); + +-- Location: FF_X7_Y8_N13 +\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add7~25_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y8_N24 +\myVirtualToplevel|UART0|Equal6~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal6~0_combout\ = ( \myVirtualToplevel|UART0|Add6~17_sumout\ & ( \myVirtualToplevel|UART0|Add6~9_sumout\ & ( (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) $ (\myVirtualToplevel|UART0|Add6~13_sumout\)))) ) ) ) # ( !\myVirtualToplevel|UART0|Add6~17_sumout\ & ( \myVirtualToplevel|UART0|Add6~9_sumout\ & ( (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & +-- (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) $ (\myVirtualToplevel|UART0|Add6~13_sumout\)))) ) ) ) # ( \myVirtualToplevel|UART0|Add6~17_sumout\ & ( !\myVirtualToplevel|UART0|Add6~9_sumout\ & ( +-- (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) $ (\myVirtualToplevel|UART0|Add6~13_sumout\)))) ) ) ) # ( !\myVirtualToplevel|UART0|Add6~17_sumout\ +-- & ( !\myVirtualToplevel|UART0|Add6~9_sumout\ & ( (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) $ (\myVirtualToplevel|UART0|Add6~13_sumout\)))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000001000001000000000001001000000000001000001000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(3), + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(4), + datad => \myVirtualToplevel|UART0|ALT_INV_Add6~13_sumout\, + datae => \myVirtualToplevel|UART0|ALT_INV_Add6~17_sumout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_Add6~9_sumout\, + combout => \myVirtualToplevel|UART0|Equal6~0_combout\); + +-- Location: LABCELL_X12_Y8_N0 +\myVirtualToplevel|UART0|Equal6~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal6~2_combout\ = ( \myVirtualToplevel|UART0|Equal6~1_combout\ & ( \myVirtualToplevel|UART0|Equal6~0_combout\ & ( (!\myVirtualToplevel|UART0|Add6~1_sumout\ & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) & +-- (!\myVirtualToplevel|UART0|Add6~5_sumout\ $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7))))) # (\myVirtualToplevel|UART0|Add6~1_sumout\ & (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART0|Add6~5_sumout\ $ +-- (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001001000000001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Add6~1_sumout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(6), + datac => \myVirtualToplevel|UART0|ALT_INV_Add6~5_sumout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(7), + datae => \myVirtualToplevel|UART0|ALT_INV_Equal6~1_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_Equal6~0_combout\, + combout => \myVirtualToplevel|UART0|Equal6~2_combout\); + +-- Location: MLABCELL_X9_Y8_N18 +\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\ = ( !\myVirtualToplevel|UART0|Equal6~2_combout\ & ( (\myVirtualToplevel|UART0|TX_OVERRUN~1_combout\ & !\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~1_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_Equal6~2_combout\, + combout => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\); + +-- Location: FF_X10_Y8_N25 +\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~1_combout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0)); + +-- Location: LABCELL_X7_Y8_N3 +\myVirtualToplevel|UART0|Add7~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add7~13_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~10\ )) +-- \myVirtualToplevel|UART0|Add7~14\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(2), + cin => \myVirtualToplevel|UART0|Add7~10\, + sumout => \myVirtualToplevel|UART0|Add7~13_sumout\, + cout => \myVirtualToplevel|UART0|Add7~14\); + +-- Location: FF_X7_Y8_N5 +\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add7~13_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(2)); + +-- Location: LABCELL_X7_Y8_N6 +\myVirtualToplevel|UART0|Add7~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add7~17_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~14\ )) +-- \myVirtualToplevel|UART0|Add7~18\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(3), + cin => \myVirtualToplevel|UART0|Add7~14\, + sumout => \myVirtualToplevel|UART0|Add7~17_sumout\, + cout => \myVirtualToplevel|UART0|Add7~18\); + +-- Location: FF_X7_Y8_N7 +\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add7~17_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3)); + +-- Location: LABCELL_X7_Y8_N9 +\myVirtualToplevel|UART0|Add7~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add7~21_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~18\ )) +-- \myVirtualToplevel|UART0|Add7~22\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(4), + cin => \myVirtualToplevel|UART0|Add7~18\, + sumout => \myVirtualToplevel|UART0|Add7~21_sumout\, + cout => \myVirtualToplevel|UART0|Add7~22\); + +-- Location: FF_X7_Y8_N10 +\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add7~21_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4)); + +-- Location: LABCELL_X7_Y8_N12 +\myVirtualToplevel|UART0|Add7~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add7~25_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~22\ )) +-- \myVirtualToplevel|UART0|Add7~26\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(5), + cin => \myVirtualToplevel|UART0|Add7~22\, + sumout => \myVirtualToplevel|UART0|Add7~25_sumout\, + cout => \myVirtualToplevel|UART0|Add7~26\); + +-- Location: FF_X7_Y8_N14 +\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add7~25_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(5)); + +-- Location: LABCELL_X7_Y8_N15 +\myVirtualToplevel|UART0|Add7~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add7~1_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~26\ )) +-- \myVirtualToplevel|UART0|Add7~2\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(6), + cin => \myVirtualToplevel|UART0|Add7~26\, + sumout => \myVirtualToplevel|UART0|Add7~1_sumout\, + cout => \myVirtualToplevel|UART0|Add7~2\); + +-- Location: FF_X7_Y8_N17 +\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add7~1_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6)); + +-- Location: LABCELL_X7_Y8_N18 +\myVirtualToplevel|UART0|Add7~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add7~5_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(7), + cin => \myVirtualToplevel|UART0|Add7~2\, + sumout => \myVirtualToplevel|UART0|Add7~5_sumout\); + +-- Location: FF_X7_Y8_N19 +\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add7~5_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7)); + +-- Location: MLABCELL_X9_Y8_N27 +\myVirtualToplevel|UART0|Equal5~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal5~0_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7) & ( (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7) & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) $ (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6)))) ) ) # ( +-- !\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7) & ( (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7) & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) $ (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000001010101000000000101001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(7), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(6), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(6), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(7), + combout => \myVirtualToplevel|UART0|Equal5~0_combout\); + +-- Location: LABCELL_X10_Y8_N54 +\myVirtualToplevel|UART0|Equal5~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal5~1_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) & +-- (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0) $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0) $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0))))) ) ) ) # ( +-- \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0) +-- $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & +-- (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0) $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000100000000010000000001001000000000100000000010000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(1), + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(0), + datae => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|UART0|Equal5~1_combout\); + +-- Location: LABCELL_X10_Y8_N0 +\myVirtualToplevel|UART0|Equal5~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal5~2_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) & (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) & +-- (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4))))) ) ) ) # ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4))))) ) ) ) # ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & ( +-- !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) & (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) $ +-- (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4))))) ) ) ) # ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) & +-- (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000010000000000000000001000010000100001000000000000000000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(4), + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(5), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(4), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(3), + datae => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(3), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|UART0|Equal5~2_combout\); + +-- Location: LABCELL_X10_Y9_N0 +\myVirtualToplevel|UART0|Add0~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~37_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|UART0|Add0~38\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(0), + cin => GND, + sumout => \myVirtualToplevel|UART0|Add0~37_sumout\, + cout => \myVirtualToplevel|UART0|Add0~38\); + +-- Location: LABCELL_X12_Y9_N27 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\, + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~4_combout\); + +-- Location: FF_X12_Y9_N29 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(0)); + +-- Location: LABCELL_X12_Y9_N24 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~_wirecell_combout\ = !\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(0), + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~_wirecell_combout\); + +-- Location: LABCELL_X5_Y8_N51 +\myVirtualToplevel|UART0|TX_COUNTER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_COUNTER~0_combout\ = ( \myVirtualToplevel|UART0|Equal0~4_combout\ & ( \myVirtualToplevel|UART0|TX_STATE~q\ ) ) # ( \myVirtualToplevel|UART0|Equal0~4_combout\ & ( !\myVirtualToplevel|UART0|TX_STATE~q\ ) ) # ( +-- !\myVirtualToplevel|UART0|Equal0~4_combout\ & ( !\myVirtualToplevel|UART0|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|UART0|ALT_INV_Equal0~4_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + combout => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\); + +-- Location: FF_X10_Y9_N2 +\myVirtualToplevel|UART0|TX_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~37_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~_wirecell_combout\, + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(0)); + +-- Location: LABCELL_X10_Y9_N3 +\myVirtualToplevel|UART0|Add0~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~21_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~38\ )) +-- \myVirtualToplevel|UART0|Add0~22\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(1), + cin => \myVirtualToplevel|UART0|Add0~38\, + sumout => \myVirtualToplevel|UART0|Add0~21_sumout\, + cout => \myVirtualToplevel|UART0|Add0~22\); + +-- Location: FF_X12_Y9_N52 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(1)); + +-- Location: FF_X10_Y9_N5 +\myVirtualToplevel|UART0|TX_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~21_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(1), + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(1)); + +-- Location: LABCELL_X10_Y9_N6 +\myVirtualToplevel|UART0|Add0~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~25_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~22\ )) +-- \myVirtualToplevel|UART0|Add0~26\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(2), + cin => \myVirtualToplevel|UART0|Add0~22\, + sumout => \myVirtualToplevel|UART0|Add0~25_sumout\, + cout => \myVirtualToplevel|UART0|Add0~26\); + +-- Location: LABCELL_X12_Y9_N33 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~2_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\, + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~2_combout\); + +-- Location: FF_X12_Y9_N35 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(2)); + +-- Location: LABCELL_X12_Y9_N30 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~_wirecell_combout\ = ( !\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(2), + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~_wirecell_combout\); + +-- Location: FF_X10_Y9_N8 +\myVirtualToplevel|UART0|TX_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~25_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~_wirecell_combout\, + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(2)); + +-- Location: LABCELL_X10_Y9_N9 +\myVirtualToplevel|UART0|Add0~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~29_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~26\ )) +-- \myVirtualToplevel|UART0|Add0~30\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|UART0|Add0~26\, + sumout => \myVirtualToplevel|UART0|Add0~29_sumout\, + cout => \myVirtualToplevel|UART0|Add0~30\); + +-- Location: MLABCELL_X9_Y9_N18 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~3_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\, + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~3_combout\); + +-- Location: FF_X9_Y9_N20 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(3)); + +-- Location: MLABCELL_X9_Y9_N21 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~_wirecell_combout\ = ( !\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(3), + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~_wirecell_combout\); + +-- Location: FF_X10_Y9_N11 +\myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~29_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~_wirecell_combout\, + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y9_N12 +\myVirtualToplevel|UART0|Add0~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~49_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~30\ )) +-- \myVirtualToplevel|UART0|Add0~50\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(4), + cin => \myVirtualToplevel|UART0|Add0~30\, + sumout => \myVirtualToplevel|UART0|Add0~49_sumout\, + cout => \myVirtualToplevel|UART0|Add0~50\); + +-- Location: MLABCELL_X9_Y9_N9 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]~17_combout\, + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~5_combout\); + +-- Location: FF_X9_Y9_N11 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(4)); + +-- Location: MLABCELL_X9_Y9_N6 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~_wirecell_combout\ = ( !\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(4), + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~_wirecell_combout\); + +-- Location: FF_X10_Y9_N14 +\myVirtualToplevel|UART0|TX_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~49_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~_wirecell_combout\, + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(4)); + +-- Location: LABCELL_X10_Y9_N15 +\myVirtualToplevel|UART0|Add0~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~53_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~50\ )) +-- \myVirtualToplevel|UART0|Add0~54\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(5), + cin => \myVirtualToplevel|UART0|Add0~50\, + sumout => \myVirtualToplevel|UART0|Add0~53_sumout\, + cout => \myVirtualToplevel|UART0|Add0~54\); + +-- Location: MLABCELL_X9_Y9_N39 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]~15_combout\, + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~6_combout\); + +-- Location: FF_X9_Y9_N41 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(5)); + +-- Location: MLABCELL_X9_Y9_N36 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~_wirecell_combout\ = ( !\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(5), + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~_wirecell_combout\); + +-- Location: FF_X10_Y9_N17 +\myVirtualToplevel|UART0|TX_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~53_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~_wirecell_combout\, + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(5)); + +-- Location: LABCELL_X10_Y9_N18 +\myVirtualToplevel|UART0|Add0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~1_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~54\ )) +-- \myVirtualToplevel|UART0|Add0~2\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(6), + cin => \myVirtualToplevel|UART0|Add0~54\, + sumout => \myVirtualToplevel|UART0|Add0~1_sumout\, + cout => \myVirtualToplevel|UART0|Add0~2\); + +-- Location: FF_X9_Y9_N55 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(6)); + +-- Location: FF_X10_Y9_N20 +\myVirtualToplevel|UART0|TX_COUNTER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~1_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(6), + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(6)); + +-- Location: LABCELL_X10_Y9_N21 +\myVirtualToplevel|UART0|Add0~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~33_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~2\ )) +-- \myVirtualToplevel|UART0|Add0~34\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(7), + cin => \myVirtualToplevel|UART0|Add0~2\, + sumout => \myVirtualToplevel|UART0|Add0~33_sumout\, + cout => \myVirtualToplevel|UART0|Add0~34\); + +-- Location: LABCELL_X19_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[23]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[23]~feeder_combout\); + +-- Location: LABCELL_X16_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000010000000000000001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\); + +-- Location: LABCELL_X17_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000011000000000000001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\); + +-- Location: LABCELL_X17_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000100000000000000000000000000000000000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\); + +-- Location: LABCELL_X17_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000010000000000000001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\); + +-- Location: LABCELL_X17_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100001001110010101111001111001100001100001001010100001111000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\); + +-- Location: LABCELL_X16_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768_BDD12769\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000100010000000000000000010101010001000000000001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768_BDD12769\); + +-- Location: LABCELL_X16_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768_BDD12769\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768_BDD12769\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011100000110000001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_RESYN12768_BDD12769\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\); + +-- Location: LABCELL_X17_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000010110000000000001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~7_combout\); + +-- Location: MLABCELL_X18_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000101000000000000010001000000100000000000000011000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\); + +-- Location: LABCELL_X17_Y24_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101000000000101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~9_combout\); + +-- Location: MLABCELL_X18_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001000000000000101000000000000010111000000000000100000000101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\); + +-- Location: LABCELL_X17_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~8_combout\); + +-- Location: LABCELL_X17_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100000000000000010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\); + +-- Location: LABCELL_X17_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal141~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\); + +-- Location: MLABCELL_X18_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010000000000000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\); + +-- Location: LABCELL_X16_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111000011110000111101011111010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~12_combout\); + +-- Location: LABCELL_X19_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]~feeder_combout\); + +-- Location: FF_X19_Y17_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(22)); + +-- Location: FF_X18_Y17_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(22)); + +-- Location: LABCELL_X19_Y17_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(22) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(22) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\); + +-- Location: LABCELL_X21_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000000000000011000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~4_combout\); + +-- Location: MLABCELL_X18_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010000000000000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\); + +-- Location: LABCELL_X16_Y9_N0 +\myVirtualToplevel|SD_ADDR[0][0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + combout => \myVirtualToplevel|SD_ADDR[0][0]~feeder_combout\); + +-- Location: FF_X16_Y9_N1 +\myVirtualToplevel|SD_ADDR[0][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][0]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][0]~q\); + +-- Location: FF_X24_Y5_N16 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \SDCARD_MISO[0]~input_o\, + sload => VCC, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(0)); + +-- Location: LABCELL_X19_Y9_N6 +\myVirtualToplevel|Mux83~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux83~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(0) & ( (\myVirtualToplevel|SD_ADDR[0][0]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|SD_ADDR[0][0]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][0]~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(0), + combout => \myVirtualToplevel|Mux83~0_combout\); + +-- Location: FF_X19_Y9_N7 +\myVirtualToplevel|IO_DATA_READ_SD[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux83~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(0)); + +-- Location: FF_X13_Y12_N46 +\myVirtualToplevel|INT_ENABLE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(0)); + +-- Location: FF_X20_Y13_N14 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INT_ENABLE\(0), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(0)); + +-- Location: LABCELL_X21_Y12_N36 +\myVirtualToplevel|Mux86~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux86~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|Mux86~0_combout\); + +-- Location: LABCELL_X21_Y13_N48 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SOCCFG[0]~feeder_combout\ = ( \myVirtualToplevel|Mux86~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_Mux86~0_combout\, + combout => \myVirtualToplevel|IO_DATA_READ_SOCCFG[0]~feeder_combout\); + +-- Location: FF_X21_Y13_N50 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SOCCFG[0]~feeder_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(0)); + +-- Location: LABCELL_X10_Y5_N0 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]~feeder_combout\ = \myVirtualToplevel|UART0|RX_BUFFER\(1) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(1), + combout => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]~feeder_combout\); + +-- Location: FF_X10_Y5_N1 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(17)); + +-- Location: FF_X10_Y5_N14 +\myVirtualToplevel|UART0|RX_FIFO~18\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER\(1), + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO~18_q\); + +-- Location: LABCELL_X10_Y5_N12 +\myVirtualToplevel|UART0|RX_DATA~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA~16_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(1) & ( \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & +-- (\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\)) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ((\myVirtualToplevel|UART0|RX_FIFO~18_q\))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(1) & ( +-- \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\)) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & +-- ((\myVirtualToplevel|UART0|RX_FIFO~18_q\))) ) ) ) # ( \myVirtualToplevel|UART0|RX_BUFFER\(1) & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(17)) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) ) +-- ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(1) & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(17)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(17), + datac => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~18_q\, + datae => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(1), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA~16_combout\); + +-- Location: MLABCELL_X9_Y5_N3 +\myVirtualToplevel|UART0|RX_DATA[0]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA[0]~17_combout\ = ( \myVirtualToplevel|UART0|RX_DATA~16_combout\ & ( ((\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ & \myVirtualToplevel|UART0|RX_DATA[7]~0_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(0)) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_DATA~16_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA\(0) & ((!\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\) # (!\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111100000000001111110000000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(0), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA~16_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA[0]~17_combout\); + +-- Location: FF_X9_Y5_N5 +\myVirtualToplevel|UART0|RX_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_DATA[0]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_DATA\(0)); + +-- Location: FF_X10_Y6_N13 +\myVirtualToplevel|UART0|RX_EMPTY_V\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Equal2~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_EMPTY_V~q\); + +-- Location: FF_X16_Y6_N56 +\myVirtualToplevel|UART1|RX_EMPTY_V\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Equal2~4_combout\, + ena => \myVirtualToplevel|UART1|RX_DATA[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_EMPTY_V~q\); + +-- Location: FF_X14_Y6_N29 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER\(1), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(17)); + +-- Location: FF_X14_Y6_N44 +\myVirtualToplevel|UART1|RX_FIFO~18\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER\(1), + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO~18_q\); + +-- Location: LABCELL_X14_Y6_N42 +\myVirtualToplevel|UART1|RX_DATA~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA~16_combout\ = ( \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ( \myVirtualToplevel|UART1|RX_BUFFER\(1) & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & +-- ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\))) # (\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART1|RX_FIFO~18_q\)) ) ) ) # ( !\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ( +-- \myVirtualToplevel|UART1|RX_BUFFER\(1) & ( (\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\) # (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(17)) ) ) ) # ( \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ( !\myVirtualToplevel|UART1|RX_BUFFER\(1) & ( +-- (!\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\))) # (\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART1|RX_FIFO~18_q\)) ) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ( !\myVirtualToplevel|UART1|RX_BUFFER\(1) & ( (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(17) & !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000000011110011001101010101111111110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(17), + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~18_q\, + datac => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(1), + combout => \myVirtualToplevel|UART1|RX_DATA~16_combout\); + +-- Location: MLABCELL_X13_Y6_N45 +\myVirtualToplevel|UART1|RX_DATA[0]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA[0]~17_combout\ = (!\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART1|RX_DATA\(0))))) # (\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & ((!\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ & +-- ((\myVirtualToplevel|UART1|RX_DATA\(0)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ & (\myVirtualToplevel|UART1|RX_DATA~16_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111101111000000011110111100000001111011110000000111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA~16_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(0), + combout => \myVirtualToplevel|UART1|RX_DATA[0]~17_combout\); + +-- Location: FF_X13_Y6_N46 +\myVirtualToplevel|UART1|RX_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_DATA[0]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_DATA\(0)); + +-- Location: LABCELL_X14_Y9_N42 +\myVirtualToplevel|IO_DATA_READ~92\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~92_combout\ = ( \myVirtualToplevel|UART1|RX_DATA\(0) & ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # +-- (\myVirtualToplevel|UART1|RX_EMPTY_V~q\))) ) ) ) # ( !\myVirtualToplevel|UART1|RX_DATA\(0) & ( \myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|UART1|RX_EMPTY_V~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) # ( \myVirtualToplevel|UART1|RX_DATA\(0) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|UART0|RX_EMPTY_V~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_DATA\(0) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|UART0|RX_EMPTY_V~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101010000000000000011000000001111001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_EMPTY_V~q\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_EMPTY_V~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datae => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(0), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|IO_DATA_READ~92_combout\); + +-- Location: LABCELL_X7_Y11_N24 +\myVirtualToplevel|IO_DATA_READ~88\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~88_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( (\myVirtualToplevel|RTC_YEAR_COUNTER\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|RTC_HOUR_COUNTER\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (!\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|RTC_YEAR_COUNTER\(0)) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|RTC_HOUR_COUNTER\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (!\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000011111100110111011101110100110000111111000001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0), + combout => \myVirtualToplevel|IO_DATA_READ~88_combout\); + +-- Location: FF_X13_Y12_N1 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~89_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\); + +-- Location: FF_X12_Y12_N1 +\myVirtualToplevel|SECOND_DOWN_COUNTER[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~41_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER[0]~DUPLICATE_q\); + +-- Location: LABCELL_X16_Y11_N33 +\myVirtualToplevel|IO_DATA_READ~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~89_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|SECOND_DOWN_COUNTER[0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(0) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(0) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(0), + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + combout => \myVirtualToplevel|IO_DATA_READ~89_combout\); + +-- Location: LABCELL_X10_Y12_N24 +\myVirtualToplevel|IO_DATA_READ~90\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~90_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(0) & ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER\(0) & ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0) +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ((\myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) # ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(0) & ( +-- !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ((\myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER\(0) & ( +-- !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ((\myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010000110010011101101001100011011100101110101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(0), + datad => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(0), + dataf => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(0), + combout => \myVirtualToplevel|IO_DATA_READ~90_combout\); + +-- Location: LABCELL_X14_Y11_N18 +\myVirtualToplevel|IO_DATA_READ~91\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~91_combout\ = ( \myVirtualToplevel|IO_DATA_READ~90_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)) # (\myVirtualToplevel|IO_DATA_READ~89_combout\)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|IO_DATA_READ~88_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))))) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~90_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (((\myVirtualToplevel|IO_DATA_READ~89_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|IO_DATA_READ~88_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000010001000011000001000100001100110111010000110011011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ~88_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ~89_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~90_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~91_combout\); + +-- Location: LABCELL_X14_Y9_N36 +\myVirtualToplevel|IO_DATA_READ~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~93_combout\ = ( \myVirtualToplevel|IO_DATA_READ~91_combout\ & ( \myVirtualToplevel|UART1|Add9~36_sumout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\) # ((!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & +-- ((\myVirtualToplevel|IO_DATA_READ~92_combout\))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|UART0|RX_DATA\(0)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~91_combout\ & ( \myVirtualToplevel|UART1|Add9~36_sumout\ & ( +-- (!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & (((\myVirtualToplevel|IO_DATA_READ[0]~70_combout\)))) # (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ((!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & +-- ((\myVirtualToplevel|IO_DATA_READ~92_combout\))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|UART0|RX_DATA\(0))))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ~91_combout\ & ( !\myVirtualToplevel|UART1|Add9~36_sumout\ & ( +-- (!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & (((!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\)))) # (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ((!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & +-- ((\myVirtualToplevel|IO_DATA_READ~92_combout\))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|UART0|RX_DATA\(0))))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~91_combout\ & ( !\myVirtualToplevel|UART1|Add9~36_sumout\ & ( +-- (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ((!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & ((\myVirtualToplevel|IO_DATA_READ~92_combout\))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|UART0|RX_DATA\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101010001101000011111000100001011010110111010101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~46_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(0), + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~70_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ~92_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ~91_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add9~36_sumout\, + combout => \myVirtualToplevel|IO_DATA_READ~93_combout\); + +-- Location: FF_X14_Y9_N37 +\myVirtualToplevel|IO_DATA_READ[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~93_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(0)); + +-- Location: LABCELL_X20_Y13_N51 +\myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ = ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(0) ) ) # ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(0), + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(0), + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\); + +-- Location: LABCELL_X20_Y13_N12 +\myVirtualToplevel|MEM_DATA_READ[0]~94\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[0]~94_combout\ = ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(0) & ( \myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(0) & ( \myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((!\myVirtualToplevel|INTR0_CS~combout\) # ((!\myVirtualToplevel|IO_SELECT~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(0) & ( !\myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\)) # (\myVirtualToplevel|INTR0_CS~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(0) & ( !\myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((!\myVirtualToplevel|IO_SELECT~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000110011111101010011001111111010001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(0), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_RESYN8743_BDD8744\, + combout => \myVirtualToplevel|MEM_DATA_READ[0]~94_combout\); + +-- Location: M10K_X22_Y19_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E01150A0426087860C0AA494890000246582636303300842108410401308000015508E71653D19FB292449355A00509140015554007FFFFFFFA00034C1083D04909C201208CC33100130A088C840A182873EE413FF557F7354AA0A17ABD572128F79FE54806CFC2A4282A7451EB34F", + mem_init2 => "47567802628B140805C870046E1F3E134040F02E53F210D86CE98E6C516CC56EF269E39313622A9AB5F13C7AC63962CDE388416981100703C08DE3038A8E9468C3541359E8534C13F429F60979BBF3A94DED9F8902AA40530B07C25FEDB9B92F9BB6B7EDB6F4E9C2E3109F331BA0C0FC2AE7BDAD05E857C1A9BDBC2A6AA5F09C7CA21BF70F4C09E72B894E7250094290096A7308E3D104C0BD3FC42E564008E953952661A151C383EAE800E7A635E34FEA9A63DC07B7AE6402037392B0C856506175288C32E6ED86D6C67CAB55353D603D60ED874FD91E1C7A00164733B3ADD2012EBA6E3048A9881DBDF6AA912312E067ED760FC8F1AB14E5312284C221950C", + mem_init1 => "B1C888705767256D982A1DF0888FA7A0663822622E948625171286A2020E30C2461C81BAB4E22C38706E15008528BC64205195447F4A0194AA6BC265F50546998B625061D865C917C6691BA4644032202F6871F18686A2125BCE228E48AA54453B177DE4C4203B433181E500799583EADE6449760028781C1112519959C5EC7990B5C05A0DF4E5F5E27CA8E00BA19A8FC84E676AE7AEE84AD45D254CF81E84A1F2AF138A24004C805133D0875775961A687C0421A9D8E45048BABE108E2E10C80B80C06C190F635029CB133081A64082001E5E3C022761D4D8CCE0A409CAD3C02A11C625C4AF0600E96D2A6E61105288F2638DB9C44283A219C2F99319259FFB", + mem_init0 => "C4051351F98A3EA90243245DC529548AEAA2896C0C9811ED099B282F1B55C4C6D246AB48D0817207390A4490D0CE671397E9E6F82739C318529DB38A91C2B5078D26C401A5D6B3EB53121A22B609C386C8D49B925B1BDDADB5A3468F1E3ED1400638D18C1D103183A2063066941A0D068244106B0581BD4228336302B220BC1D540DF04AAC04215295543124D7DAAD9AAB58D8E1BBC682BC84392E87A5434451492802A2254A0840833100A68900129066263920279B1C8011A223444444444444444444444444444468885100A22145FFFFFFFFFFFB6DA4936DA4936DA492FEFF0000000000006D450606120600030101092F1906010000035103036E0E0000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X19_Y16_N0 +\myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ = ( !\myVirtualToplevel|MEM_DATA_READ[0]~94_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(0) & +-- (((\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\)))))) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[0]~94_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))) # (\myVirtualToplevel|IO_DATA_READ_SD\(0)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ +-- & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000010100100010101011110010001000000101011101111010111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(0), + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]~34_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\); + +-- Location: MLABCELL_X18_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\) # ((\myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\)) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ & ( (\myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111100001111001100000000001100111111000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~5_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~95_Duplicate_161\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\); + +-- Location: LABCELL_X17_Y12_N30 +\myVirtualToplevel|IO_DATA_READ[26]~78\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[26]~78_combout\ = ( \myVirtualToplevel|INTR0_CS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|TIMER0_CS~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010100000000000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\, + combout => \myVirtualToplevel|IO_DATA_READ[26]~78_combout\); + +-- Location: LABCELL_X14_Y10_N6 +\myVirtualToplevel|IO_DATA_READ[24]~86\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[24]~86_combout\ = ( \myVirtualToplevel|UART0_CS~combout\ & ( !\myVirtualToplevel|TIMER0_CS~1_combout\ & ( (!\myVirtualToplevel|UART0|TX_RESET~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # ( +-- !\myVirtualToplevel|UART0_CS~combout\ & ( !\myVirtualToplevel|TIMER0_CS~1_combout\ & ( (!\myVirtualToplevel|UART1|TX_RESET~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_RESET~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_TX_RESET~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ALT_INV_UART0_CS~combout\, + dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + combout => \myVirtualToplevel|IO_DATA_READ[24]~86_combout\); + +-- Location: LABCELL_X17_Y11_N21 +\myVirtualToplevel|Add17~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~73_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(7) ) + ( GND ) + ( \myVirtualToplevel|Add17~70\ )) +-- \myVirtualToplevel|Add17~74\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(7) ) + ( GND ) + ( \myVirtualToplevel|Add17~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(7), + cin => \myVirtualToplevel|Add17~70\, + sumout => \myVirtualToplevel|Add17~73_sumout\, + cout => \myVirtualToplevel|Add17~74\); + +-- Location: FF_X17_Y11_N23 +\myVirtualToplevel|MILLISEC_UP_COUNTER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~73_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(7)); + +-- Location: LABCELL_X17_Y11_N24 +\myVirtualToplevel|Add17~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~77_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~74\ )) +-- \myVirtualToplevel|Add17~78\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add17~74\, + sumout => \myVirtualToplevel|Add17~77_sumout\, + cout => \myVirtualToplevel|Add17~78\); + +-- Location: FF_X17_Y11_N26 +\myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~77_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y11_N27 +\myVirtualToplevel|Add17~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~57_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(9) ) + ( GND ) + ( \myVirtualToplevel|Add17~78\ )) +-- \myVirtualToplevel|Add17~58\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(9) ) + ( GND ) + ( \myVirtualToplevel|Add17~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(9), + cin => \myVirtualToplevel|Add17~78\, + sumout => \myVirtualToplevel|Add17~57_sumout\, + cout => \myVirtualToplevel|Add17~58\); + +-- Location: FF_X17_Y11_N29 +\myVirtualToplevel|MILLISEC_UP_COUNTER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~57_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(9)); + +-- Location: LABCELL_X17_Y11_N30 +\myVirtualToplevel|Add17~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~61_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(10) ) + ( GND ) + ( \myVirtualToplevel|Add17~58\ )) +-- \myVirtualToplevel|Add17~62\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(10) ) + ( GND ) + ( \myVirtualToplevel|Add17~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(10), + cin => \myVirtualToplevel|Add17~58\, + sumout => \myVirtualToplevel|Add17~61_sumout\, + cout => \myVirtualToplevel|Add17~62\); + +-- Location: FF_X17_Y11_N32 +\myVirtualToplevel|MILLISEC_UP_COUNTER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~61_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(10)); + +-- Location: LABCELL_X17_Y11_N33 +\myVirtualToplevel|Add17~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~65_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(11) ) + ( GND ) + ( \myVirtualToplevel|Add17~62\ )) +-- \myVirtualToplevel|Add17~66\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(11) ) + ( GND ) + ( \myVirtualToplevel|Add17~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(11), + cin => \myVirtualToplevel|Add17~62\, + sumout => \myVirtualToplevel|Add17~65_sumout\, + cout => \myVirtualToplevel|Add17~66\); + +-- Location: FF_X17_Y11_N35 +\myVirtualToplevel|MILLISEC_UP_COUNTER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~65_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(11)); + +-- Location: LABCELL_X17_Y11_N36 +\myVirtualToplevel|Add17~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~33_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~66\ )) +-- \myVirtualToplevel|Add17~34\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add17~66\, + sumout => \myVirtualToplevel|Add17~33_sumout\, + cout => \myVirtualToplevel|Add17~34\); + +-- Location: FF_X17_Y11_N38 +\myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~33_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y11_N39 +\myVirtualToplevel|Add17~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~37_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(13) ) + ( GND ) + ( \myVirtualToplevel|Add17~34\ )) +-- \myVirtualToplevel|Add17~38\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(13) ) + ( GND ) + ( \myVirtualToplevel|Add17~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(13), + cin => \myVirtualToplevel|Add17~34\, + sumout => \myVirtualToplevel|Add17~37_sumout\, + cout => \myVirtualToplevel|Add17~38\); + +-- Location: FF_X17_Y11_N41 +\myVirtualToplevel|MILLISEC_UP_COUNTER[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~37_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(13)); + +-- Location: LABCELL_X17_Y11_N42 +\myVirtualToplevel|Add17~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~41_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(14) ) + ( GND ) + ( \myVirtualToplevel|Add17~38\ )) +-- \myVirtualToplevel|Add17~42\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(14) ) + ( GND ) + ( \myVirtualToplevel|Add17~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(14), + cin => \myVirtualToplevel|Add17~38\, + sumout => \myVirtualToplevel|Add17~41_sumout\, + cout => \myVirtualToplevel|Add17~42\); + +-- Location: FF_X17_Y11_N44 +\myVirtualToplevel|MILLISEC_UP_COUNTER[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~41_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(14)); + +-- Location: LABCELL_X17_Y11_N45 +\myVirtualToplevel|Add17~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~45_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~42\ )) +-- \myVirtualToplevel|Add17~46\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[15]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add17~42\, + sumout => \myVirtualToplevel|Add17~45_sumout\, + cout => \myVirtualToplevel|Add17~46\); + +-- Location: FF_X17_Y11_N47 +\myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~45_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y11_N48 +\myVirtualToplevel|Add17~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~1_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(16) ) + ( GND ) + ( \myVirtualToplevel|Add17~46\ )) +-- \myVirtualToplevel|Add17~2\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(16) ) + ( GND ) + ( \myVirtualToplevel|Add17~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(16), + cin => \myVirtualToplevel|Add17~46\, + sumout => \myVirtualToplevel|Add17~1_sumout\, + cout => \myVirtualToplevel|Add17~2\); + +-- Location: FF_X17_Y11_N50 +\myVirtualToplevel|MILLISEC_UP_COUNTER[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~1_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(16)); + +-- Location: LABCELL_X17_Y11_N51 +\myVirtualToplevel|Add17~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~21_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(17) ) + ( GND ) + ( \myVirtualToplevel|Add17~2\ )) +-- \myVirtualToplevel|Add17~22\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(17) ) + ( GND ) + ( \myVirtualToplevel|Add17~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(17), + cin => \myVirtualToplevel|Add17~2\, + sumout => \myVirtualToplevel|Add17~21_sumout\, + cout => \myVirtualToplevel|Add17~22\); + +-- Location: FF_X17_Y11_N52 +\myVirtualToplevel|MILLISEC_UP_COUNTER[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~21_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(17)); + +-- Location: LABCELL_X17_Y11_N54 +\myVirtualToplevel|Add17~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~25_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~22\ )) +-- \myVirtualToplevel|Add17~26\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[18]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add17~22\, + sumout => \myVirtualToplevel|Add17~25_sumout\, + cout => \myVirtualToplevel|Add17~26\); + +-- Location: FF_X17_Y11_N56 +\myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~25_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y11_N57 +\myVirtualToplevel|Add17~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~29_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~26\ )) +-- \myVirtualToplevel|Add17~30\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[19]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add17~26\, + sumout => \myVirtualToplevel|Add17~29_sumout\, + cout => \myVirtualToplevel|Add17~30\); + +-- Location: FF_X17_Y11_N59 +\myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~29_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y10_N0 +\myVirtualToplevel|Add17~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~13_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~30\ )) +-- \myVirtualToplevel|Add17~14\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[20]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add17~30\, + sumout => \myVirtualToplevel|Add17~13_sumout\, + cout => \myVirtualToplevel|Add17~14\); + +-- Location: FF_X17_Y10_N2 +\myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~13_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y10_N3 +\myVirtualToplevel|Add17~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~5_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~14\ )) +-- \myVirtualToplevel|Add17~6\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add17~14\, + sumout => \myVirtualToplevel|Add17~5_sumout\, + cout => \myVirtualToplevel|Add17~6\); + +-- Location: FF_X17_Y10_N5 +\myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~5_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y10_N6 +\myVirtualToplevel|Add17~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~9_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(22) ) + ( GND ) + ( \myVirtualToplevel|Add17~6\ )) +-- \myVirtualToplevel|Add17~10\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(22) ) + ( GND ) + ( \myVirtualToplevel|Add17~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(22), + cin => \myVirtualToplevel|Add17~6\, + sumout => \myVirtualToplevel|Add17~9_sumout\, + cout => \myVirtualToplevel|Add17~10\); + +-- Location: FF_X17_Y10_N7 +\myVirtualToplevel|MILLISEC_UP_COUNTER[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~9_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(22)); + +-- Location: LABCELL_X17_Y10_N9 +\myVirtualToplevel|Add17~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~17_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(23) ) + ( GND ) + ( \myVirtualToplevel|Add17~10\ )) +-- \myVirtualToplevel|Add17~18\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(23) ) + ( GND ) + ( \myVirtualToplevel|Add17~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(23), + cin => \myVirtualToplevel|Add17~10\, + sumout => \myVirtualToplevel|Add17~17_sumout\, + cout => \myVirtualToplevel|Add17~18\); + +-- Location: FF_X17_Y10_N11 +\myVirtualToplevel|MILLISEC_UP_COUNTER[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~17_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(23)); + +-- Location: LABCELL_X17_Y10_N12 +\myVirtualToplevel|Add17~121\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~121_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(24) ) + ( GND ) + ( \myVirtualToplevel|Add17~18\ )) +-- \myVirtualToplevel|Add17~122\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(24) ) + ( GND ) + ( \myVirtualToplevel|Add17~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(24), + cin => \myVirtualToplevel|Add17~18\, + sumout => \myVirtualToplevel|Add17~121_sumout\, + cout => \myVirtualToplevel|Add17~122\); + +-- Location: FF_X18_Y16_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(24)); + +-- Location: FF_X19_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(24)); + +-- Location: LABCELL_X19_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(24) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(24) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\); + +-- Location: LABCELL_X6_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]_NEW3035\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]_OTERM3036\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]_OTERM3036\); + +-- Location: FF_X6_Y22_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]_OTERM3036\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24)); + +-- Location: LABCELL_X6_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]_NEW3163\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]_OTERM3164\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]_OTERM3164\); + +-- Location: FF_X6_Y22_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]_OTERM3164\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24)); + +-- Location: LABCELL_X12_Y22_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]_NEW2971\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]_OTERM2972\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]_OTERM2972\); + +-- Location: FF_X12_Y22_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]_OTERM2972\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24)); + +-- Location: LABCELL_X6_Y22_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]_NEW3099\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]_OTERM3100\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]_OTERM3100\); + +-- Location: FF_X6_Y22_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]_OTERM3100\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24)); + +-- Location: LABCELL_X6_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux18~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100000011000111011100111111010001000011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(24), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~0_combout\); + +-- Location: LABCELL_X6_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]_NEW2715\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]_OTERM2716\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]_OTERM2716\); + +-- Location: FF_X6_Y22_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]_OTERM2716\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24)); + +-- Location: LABCELL_X6_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]_NEW2843\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]_OTERM2844\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(24) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]_OTERM2844\); + +-- Location: FF_X6_Y22_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]_OTERM2844\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(24)); + +-- Location: LABCELL_X12_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]_NEW2907\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]_OTERM2908\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]_OTERM2908\); + +-- Location: FF_X12_Y22_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]_OTERM2908\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24)); + +-- Location: LABCELL_X6_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]_NEW2779\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]_OTERM2780\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]_OTERM2780\); + +-- Location: FF_X6_Y22_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]_OTERM2780\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24)); + +-- Location: LABCELL_X6_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux18~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(24)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(24) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101001100110000000000001111010101010011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(24), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~1_combout\); + +-- Location: LABCELL_X6_Y22_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\); + +-- Location: LABCELL_X10_Y14_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110011000000001111001100000101111101110000010111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]~22_combout\); + +-- Location: FF_X10_Y14_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]~22_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24)); + +-- Location: FF_X17_Y10_N14 +\myVirtualToplevel|MILLISEC_UP_COUNTER[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~121_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(24)); + +-- Location: LABCELL_X17_Y10_N57 +\myVirtualToplevel|IO_DATA_READ[24]~87\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[24]~87_combout\ = ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(24) & ( (((!\myVirtualToplevel|TIMER0_CS~1_combout\ & \myVirtualToplevel|UART1|Mux0~0_combout\)) # (\myVirtualToplevel|IO_DATA_READ[24]~86_combout\)) # +-- (\myVirtualToplevel|IO_DATA_READ[26]~78_combout\) ) ) # ( !\myVirtualToplevel|MILLISEC_UP_COUNTER\(24) & ( ((!\myVirtualToplevel|TIMER0_CS~1_combout\ & \myVirtualToplevel|UART1|Mux0~0_combout\)) # (\myVirtualToplevel|IO_DATA_READ[24]~86_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111001111000011111100111101011111110111110101111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[26]~78_combout\, + datab => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ[24]~86_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(24), + combout => \myVirtualToplevel|IO_DATA_READ[24]~87_combout\); + +-- Location: FF_X17_Y10_N58 +\myVirtualToplevel|IO_DATA_READ[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ[24]~87_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(24)); + +-- Location: LABCELL_X21_Y12_N27 +\myVirtualToplevel|Mux87~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux87~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000011000000001100001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|Mux87~0_combout\); + +-- Location: FF_X18_Y12_N14 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux87~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(24)); + +-- Location: LABCELL_X24_Y9_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector7~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector7~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8) & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0)) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(8), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector3~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector7~0_combout\); + +-- Location: FF_X24_Y9_N7 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector7~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8)); + +-- Location: LABCELL_X21_Y9_N45 +\myVirtualToplevel|IO_DATA_READ_SD[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[24]~feeder_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(8), + combout => \myVirtualToplevel|IO_DATA_READ_SD[24]~feeder_combout\); + +-- Location: LABCELL_X16_Y9_N57 +\myVirtualToplevel|SD_ADDR[0][24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(24), + combout => \myVirtualToplevel|SD_ADDR[0][24]~feeder_combout\); + +-- Location: FF_X16_Y9_N58 +\myVirtualToplevel|SD_ADDR[0][24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][24]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][24]~q\); + +-- Location: FF_X21_Y9_N46 +\myVirtualToplevel|IO_DATA_READ_SD[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[24]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][24]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(24)); + +-- Location: LABCELL_X20_Y12_N9 +\myVirtualToplevel|MEM_DATA_READ[18]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ = ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( !\myVirtualToplevel|SD_CS~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_CS~combout\, + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\); + +-- Location: MLABCELL_X18_Y12_N42 +\myVirtualToplevel|MEM_DATA_READ[24]~60\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[24]~60_combout\ = ( \myVirtualToplevel|IO_DATA_READ_SD\(24) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((!\myVirtualToplevel|INTR0_CS~combout\))) # +-- (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ\(24))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SD\(24) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & +-- ((!\myVirtualToplevel|INTR0_CS~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ\(24))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_SD\(24) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( +-- (\myVirtualToplevel|IO_DATA_READ_SOCCFG\(24)) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SD\(24) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ +-- & \myVirtualToplevel|IO_DATA_READ_SOCCFG\(24)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111111000101110001011100010111000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(24), + datab => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(24), + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(24), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[24]~60_combout\); + +-- Location: FF_X18_Y12_N49 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_NEW_REG14\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM15\); + +-- Location: IOIBUF_X19_Y0_N1 +\SDRAM_DQ[8]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(8), + o => \SDRAM_DQ[8]~input_o\); + +-- Location: DDIOINCELL_X19_Y0_N14 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_NEW_REG16\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[8]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM17\); + +-- Location: MLABCELL_X18_Y12_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM15\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM17\))) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM15\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM15\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM17\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\); + +-- Location: MLABCELL_X13_Y14_N42 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000011100000111000001110000011101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(0), + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\); + +-- Location: MLABCELL_X23_Y14_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node[1]\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(1) = ( \myVirtualToplevel|BRAM_WREN~1_combout\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) # ((\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & \myVirtualToplevel|LessThan3~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001000100010001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\, + datad => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\, + datae => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~1_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(1)); + +-- Location: MLABCELL_X23_Y14_N48 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & ( ((!\myVirtualToplevel|BRAM_WREN~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16) & +-- !\myVirtualToplevel|LessThan3~0_combout\))) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & ( ((!\myVirtualToplevel|BRAM_WREN~1_combout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111011111110111111101111111011111110111111100111111011111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~1_combout\, + datac => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\, + datad => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\); + +-- Location: MLABCELL_X9_Y14_N12 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000110011000010100011001101011111001100110101111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7_combout\); + +-- Location: M10K_X11_Y11_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X23_Y14_N6 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node[0]\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(0) = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\ & ( (\myVirtualToplevel|BRAM_WREN~1_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) # ((\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & \myVirtualToplevel|LessThan3~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100011000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + datab => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\, + datad => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~1_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(0)); + +-- Location: M10K_X3_Y16_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002222222222222222222225EE180094DF70AC92870E1012A0B9298830E70349C349EB5A5294920530228084B31D8412A832522A0165C851C24404C1221D7800126000006D80A5701F9A248070260110F80604BA090B8BC3DB060D59B129E7D2000000E71451DA8C61D10239DCE7B92932949D02063D191B899C11", + mem_init2 => "E6CC54F457669496FB05EDE4887C72BF1E09D7D96FD7929873D1D59E1098A2C510D22F3E3C746398EFA266C484B8D493024C4221831044B5CDF79DAA18B1B9DD030D46BCA69961EA53ECB1F5229C0F3A9D807D0480174C211443546B67F139B7BB2C4BFEDFB870DB946F948380DCA7C7251CDC1091C42C38D92E2F8C5C568F13DEDE75AC775782D29A1915C4B10280B10276536607BD6E38FE1100D6926061B835A772D963C4161746009690E8E987F016EC2637C0E291E236A88E2BF3F63E230CCE493CFFDD19A38C598BB8A88A328957DDD716A472E0670E3A0A2EE4A00204416A29B8D66546B7001A8BA973EE912A8076B710E1871EE1EAE08B9E227570B8", + mem_init1 => "5DA568E101D611104934107CE4BB82DF2D1F3A3244904E404A7F5E5A2290F3FC006C449524CE6130341226441BC0D508A997038520227061B772CC8C8947F14F7265C59C1B2C3C010907C9DF5501834E6341042AC8AD9D87378AEAFC5180D87C30911C2EA291298E154104EC0F4C4AA2F0A000B227C85B882C4E8895569704F11407CC0E17012B3E5B1DEF421A60BAC4609F0603CB5C0262BA8E29C848724D35FA0AFFB3C418F80808D891F79AC56AE964C54E0623110B55D64A7921249E4EF062903A7587285AA5F2172804FEAD048628106CD5801493A99943B91286230A138BA6809A1244744EA7DA8298FD4D00CE02CC99820493465839BCE004B2B2CA72", + mem_init0 => "8122000836C14C0875058DAB6082051DEA783602010C6FCBA077048581E4078D34E78C1BF1D3D614DB0C6041192233A7C201827B28B0809FD5ACD9233C34EA4EFEAFCD0D638FA4A436E6B056DACFD81A82A5EFB6E378B1A8B53875E3D78E1C6198510206207440C40E8818B440D0683402F130314061CF132D0199A11419F8159105DBDFF4631A354AA89049361EB405BC64034A54D3A119EE1EA7BD5540B328208508507228A8A840A2A008045509001455626390E72F002014446EAEEEEAAAEEEEEEEEAAEAAAAA880D110A20344468FFFFFFFFFFFFFEDB6DB6DB6DB6DB6FFEFB0000000100018E760C0C03150602011414510E0E0001000667063CFF1D0001", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X18_Y12_N15 +\myVirtualToplevel|MEM_DATA_READ[24]~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[24]~61_combout\ = ( \myVirtualToplevel|LessThan0~1_combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8~portbdataout\) ) ) ) # ( \myVirtualToplevel|LessThan0~1_combout\ & ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0) & +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8~portbdataout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000101010100000000000000001010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\, + datae => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[24]~61_combout\); + +-- Location: MLABCELL_X18_Y12_N27 +\myVirtualToplevel|MEM_DATA_READ[24]~62\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[24]~61_combout\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[24]~61_combout\ ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[24]~61_combout\ & ( ((\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[24]~60_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[24]~61_combout\ & ( +-- (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & \myVirtualToplevel|MEM_DATA_READ[24]~60_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100011111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~60_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]~33_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~61_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\); + +-- Location: MLABCELL_X18_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector358~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ & ( ((\myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ & ( (\myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000111100001111000000001111010111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~103_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector358~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~62_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~1_combout\); + +-- Location: FF_X20_Y22_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~4_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~89_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\)) ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~90\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\)) ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~95_Duplicate_161\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[0]~DUPLICATE_q\, + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~89_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~90\); + +-- Location: FF_X18_Y16_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~1_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~89_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\); + +-- Location: LABCELL_X19_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~98\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~98_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~99\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110000001100000000000000000000000011111111000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~98_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~99\); + +-- Location: LABCELL_X19_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~103\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~103_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +-- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~99\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~104\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~99\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~99\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~103_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~104\); + +-- Location: LABCELL_X19_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~94\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~94_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~104\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~95\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~104\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~104\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~94_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~95\); + +-- Location: LABCELL_X19_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~89_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~95\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~90\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~95\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~95\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~89_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~90\); + +-- Location: LABCELL_X19_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~52_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~53\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~90\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~52_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~53\); + +-- Location: LABCELL_X19_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~53\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~53\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~53\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~58\); + +-- Location: LABCELL_X19_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~75\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~75_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~76\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~75_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~76\); + +-- Location: LABCELL_X19_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~80\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~80_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~76\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~81\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~76\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~76\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~80_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~81\); + +-- Location: LABCELL_X19_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~85_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~81\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~86\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~81\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~81\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~86\); + +-- Location: LABCELL_X19_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~62\); + +-- Location: LABCELL_X19_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~66\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~66_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +-- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~67\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~66_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~67\); + +-- Location: LABCELL_X19_Y23_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~71\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~71_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +-- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~67\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~72\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~67\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~67\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~71_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~72\); + +-- Location: LABCELL_X19_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~35_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~72\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~36\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~72\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~72\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~35_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~36\); + +-- Location: LABCELL_X19_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~39_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~36\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~40\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~36\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~36\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~39_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~40\); + +-- Location: LABCELL_X19_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~43_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +-- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~40\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~44\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~40\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~40\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~43_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~44\); + +-- Location: LABCELL_X19_Y23_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~47_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +-- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~44\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~48\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~44\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~44\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~47_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~48\); + +-- Location: LABCELL_X19_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~48\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~2\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~48\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~48\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~2\); + +-- Location: LABCELL_X19_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~22_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~23\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~22_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~23\); + +-- Location: LABCELL_X19_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~26_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~23\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~27\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~23\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~23\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~26_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~27\); + +-- Location: LABCELL_X19_Y23_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~30_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~27\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~31\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~27\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~27\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~30_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~31\); + +-- Location: LABCELL_X19_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~14_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~31\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~15\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~31\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011110011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~31\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~14_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~15\); + +-- Location: LABCELL_X19_Y22_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~6_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~15\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~7\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~15\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011110011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~15\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~6_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~7\); + +-- Location: LABCELL_X19_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~10_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~7\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~11\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~7\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011110011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~7\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~10_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~11\); + +-- Location: LABCELL_X21_Y23_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000000000110000000000000011000011110000001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~77_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5_combout\); + +-- Location: FF_X6_Y25_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~17_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\); + +-- Location: FF_X6_Y25_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~23_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17)); + +-- Location: FF_X9_Y25_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~8_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\); + +-- Location: MLABCELL_X4_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~46\); + +-- Location: MLABCELL_X4_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[16]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~2\); + +-- Location: MLABCELL_X4_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~22\); + +-- Location: LABCELL_X6_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~21_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~21_combout\); + +-- Location: LABCELL_X6_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~38\); + +-- Location: LABCELL_X6_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(14), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~42\); + +-- Location: LABCELL_X6_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~46\); + +-- Location: LABCELL_X6_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~2\); + +-- Location: LABCELL_X6_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~22\); + +-- Location: LABCELL_X7_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~2\); + +-- Location: LABCELL_X7_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[17]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~22\); + +-- Location: LABCELL_X6_Y25_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~21_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~21_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~21_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~21_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~22_combout\); + +-- Location: LABCELL_X6_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~22_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(17)) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111101000000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~23_combout\); + +-- Location: FF_X6_Y25_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~23_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\); + +-- Location: FF_X10_Y24_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~53_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y38_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001000100010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56_combout\); + +-- Location: FF_X10_Y26_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp~68_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\ ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\ ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~86\); + +-- Location: LABCELL_X14_Y26_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~82\); + +-- Location: LABCELL_X14_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~50\); + +-- Location: LABCELL_X14_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~54\); + +-- Location: LABCELL_X14_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~70\); + +-- Location: LABCELL_X14_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~74\); + +-- Location: LABCELL_X14_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~78\); + +-- Location: LABCELL_X14_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~58\); + +-- Location: LABCELL_X14_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~62\); + +-- Location: LABCELL_X14_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~66\); + +-- Location: LABCELL_X14_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~34\); + +-- Location: LABCELL_X14_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~38\); + +-- Location: LABCELL_X14_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~42\); + +-- Location: LABCELL_X14_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~46\); + +-- Location: LABCELL_X14_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~2\); + +-- Location: LABCELL_X14_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[17]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~22\); + +-- Location: LABCELL_X14_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~26\); + +-- Location: LABCELL_X14_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~30\); + +-- Location: LABCELL_X14_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[20]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~14\); + +-- Location: LABCELL_X14_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~6\); + +-- Location: LABCELL_X14_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~10\); + +-- Location: LABCELL_X21_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010111100001010000011001100100010001100000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6_combout\); + +-- Location: LABCELL_X21_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~10_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~10_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010000000000000000000011111111111100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~10_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~7_combout\); + +-- Location: LABCELL_X21_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000100110011001100100001111000011111001111110011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~8_combout\); + +-- Location: LABCELL_X21_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~8_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~9_combout\); + +-- Location: LABCELL_X21_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111111100001111000000001111000011111111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1_combout\); + +-- Location: LABCELL_X17_Y25_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\); + +-- Location: LABCELL_X19_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000001000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\); + +-- Location: LABCELL_X17_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000000000000000000000100000000000000000000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\); + +-- Location: LABCELL_X20_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111101010101010111110101010101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0_combout\); + +-- Location: LABCELL_X20_Y21_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000101010101010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~1_combout\); + +-- Location: FF_X29_Y30_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~337_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\); + +-- Location: MLABCELL_X13_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2_combout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[25]~53_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110101010100000000101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~53_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0_combout\); + +-- Location: MLABCELL_X9_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111101000000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector300~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]~18_combout\); + +-- Location: FF_X9_Y16_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]~18_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25)); + +-- Location: LABCELL_X7_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[1]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[1]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000000001100001111000000111111000011110011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[1]~7_combout\); + +-- Location: LABCELL_X20_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~feeder_combout\); + +-- Location: LABCELL_X19_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000010011000100100000000000000010000000000101000000000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~8_combout\); + +-- Location: LABCELL_X19_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000100000001000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\); + +-- Location: LABCELL_X14_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\); + +-- Location: MLABCELL_X13_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009_BDD9010\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000010100000111100001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009_BDD9010\); + +-- Location: MLABCELL_X18_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001010000000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\); + +-- Location: MLABCELL_X18_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~feeder_combout\); + +-- Location: LABCELL_X17_Y10_N15 +\myVirtualToplevel|Add17~109\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~109_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(25) ) + ( GND ) + ( \myVirtualToplevel|Add17~122\ )) +-- \myVirtualToplevel|Add17~110\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(25) ) + ( GND ) + ( \myVirtualToplevel|Add17~122\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(25), + cin => \myVirtualToplevel|Add17~122\, + sumout => \myVirtualToplevel|Add17~109_sumout\, + cout => \myVirtualToplevel|Add17~110\); + +-- Location: FF_X17_Y10_N17 +\myVirtualToplevel|MILLISEC_UP_COUNTER[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~109_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(25)); + +-- Location: LABCELL_X17_Y10_N18 +\myVirtualToplevel|Add17~113\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~113_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~110\ )) +-- \myVirtualToplevel|Add17~114\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~110\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[26]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add17~110\, + sumout => \myVirtualToplevel|Add17~113_sumout\, + cout => \myVirtualToplevel|Add17~114\); + +-- Location: LABCELL_X10_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux16~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101001101110000010100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]~21_combout\); + +-- Location: FF_X10_Y14_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]~21_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26)); + +-- Location: FF_X17_Y10_N20 +\myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~113_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y10_N21 +\myVirtualToplevel|Add17~117\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~117_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(27) ) + ( GND ) + ( \myVirtualToplevel|Add17~114\ )) +-- \myVirtualToplevel|Add17~118\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(27) ) + ( GND ) + ( \myVirtualToplevel|Add17~114\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(27), + cin => \myVirtualToplevel|Add17~114\, + sumout => \myVirtualToplevel|Add17~117_sumout\, + cout => \myVirtualToplevel|Add17~118\); + +-- Location: LABCELL_X16_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010101010101000001010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\); + +-- Location: FF_X18_Y17_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(27)); + +-- Location: MLABCELL_X18_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~feeder_combout\); + +-- Location: FF_X18_Y17_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(27) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[27]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\); + +-- Location: LABCELL_X16_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_RESYN8993\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_RESYN8993_BDD8994\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101111111111111111101010101111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_RESYN8993_BDD8994\); + +-- Location: LABCELL_X17_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100000000000000000000000000000000000001000000000000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\); + +-- Location: MLABCELL_X18_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000000001000001000000000000000001000001000000000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\); + +-- Location: MLABCELL_X13_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101010101010101010101010101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0_combout\); + +-- Location: LABCELL_X16_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010001010100010101000101010001010100010101100001010001010110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\); + +-- Location: LABCELL_X16_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_RESYN8993_BDD8994\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000011111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~9_RESYN8993_BDD8994\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_combout\); + +-- Location: MLABCELL_X13_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010110100101101000001111000011110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~7_combout\); + +-- Location: MLABCELL_X28_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~256\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~256_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~256_combout\); + +-- Location: FF_X28_Y33_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~256_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\); + +-- Location: MLABCELL_X28_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~257\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~257_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~257_combout\); + +-- Location: FF_X28_Y33_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~257_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\); + +-- Location: MLABCELL_X28_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~249\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~249_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~249_combout\); + +-- Location: FF_X28_Y32_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~249_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\); + +-- Location: MLABCELL_X28_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~248\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~248_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~248_combout\); + +-- Location: FF_X28_Y32_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~248_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\); + +-- Location: LABCELL_X29_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\); + +-- Location: LABCELL_X26_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~268\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~268_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~268_combout\); + +-- Location: FF_X26_Y33_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~268_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\); + +-- Location: FF_X23_Y35_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~261_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\); + +-- Location: MLABCELL_X23_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~261\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~261_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~261_combout\); + +-- Location: FF_X23_Y35_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~261_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\); + +-- Location: FF_X26_Y33_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~269_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\); + +-- Location: LABCELL_X26_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~269\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~269_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~269_combout\); + +-- Location: FF_X26_Y33_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~269_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~260\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~260_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~260_combout\); + +-- Location: FF_X23_Y35_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~260_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\); + +-- Location: LABCELL_X31_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\); + +-- Location: FF_X28_Y32_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]_OTERM1841\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~q\); + +-- Location: LABCELL_X32_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438_combout\); + +-- Location: LABCELL_X31_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & \myVirtualToplevel|RESET_n~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datac => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\); + +-- Location: MLABCELL_X23_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311_BDD9312\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100010011000000000000000000000011000100110000001100010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~18_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311_BDD9312\); + +-- Location: FF_X26_Y24_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]_OTERM3293\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(14)); + +-- Location: LABCELL_X24_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(14) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\); + +-- Location: MLABCELL_X23_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_BDD9316\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111111111111111111111001111110111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~18_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_BDD9316\); + +-- Location: MLABCELL_X23_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313_BDD9314\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111111111110000101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313_BDD9314\); + +-- Location: MLABCELL_X23_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_BDD9316\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313_BDD9314\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311_BDD9312\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_BDD9316\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313_BDD9314\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311_BDD9312\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000010000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9311_BDD9312\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~25_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9315_BDD9316\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9313_BDD9314\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_combout\); + +-- Location: MLABCELL_X23_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~13_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~9_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~438_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\); + +-- Location: MLABCELL_X28_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]_NEW1840\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]_OTERM1841\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]_OTERM1841\); + +-- Location: FF_X28_Y32_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]_OTERM1841\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]_NEW1838\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]_OTERM1839\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]_OTERM1839\); + +-- Location: FF_X28_Y32_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]_OTERM1839\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\); + +-- Location: FF_X28_Y33_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~253_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\); + +-- Location: MLABCELL_X28_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~253\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~253_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~253_combout\); + +-- Location: FF_X28_Y33_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~253_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~252\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~252_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~252_combout\); + +-- Location: FF_X28_Y33_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~252_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\); + +-- Location: MLABCELL_X28_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\); + +-- Location: FF_X23_Y35_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~265_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\); + +-- Location: MLABCELL_X23_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~265\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~265_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~265_combout\); + +-- Location: FF_X23_Y35_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~265_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~264\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~264_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~264_combout\); + +-- Location: FF_X23_Y35_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~264_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\); + +-- Location: LABCELL_X26_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~273\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~273_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~273_combout\); + +-- Location: FF_X26_Y33_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~273_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\); + +-- Location: LABCELL_X26_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~272\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~272_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~272_combout\); + +-- Location: FF_X26_Y33_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~272_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\); + +-- Location: LABCELL_X31_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\); + +-- Location: LABCELL_X29_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101000100110011110100010000000011011101111100111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\); + +-- Location: MLABCELL_X28_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~259\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~259_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~259_combout\); + +-- Location: FF_X28_Y33_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~259_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\); + +-- Location: LABCELL_X26_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~275\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~275_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~275_combout\); + +-- Location: FF_X26_Y33_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~275_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\); + +-- Location: LABCELL_X26_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~271\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~271_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~271_combout\); + +-- Location: FF_X26_Y33_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~271_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\); + +-- Location: MLABCELL_X28_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~255\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~255_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~255_combout\); + +-- Location: FF_X28_Y33_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~255_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\); + +-- Location: LABCELL_X32_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\); + +-- Location: FF_X28_Y33_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~254_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\); + +-- Location: MLABCELL_X28_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~254\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~254_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~254_combout\); + +-- Location: FF_X28_Y33_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~254_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~270\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~270_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~270_combout\); + +-- Location: FF_X26_Y33_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~270_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\); + +-- Location: LABCELL_X26_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~274\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~274_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~274_combout\); + +-- Location: FF_X26_Y33_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~274_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\); + +-- Location: MLABCELL_X28_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~258\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~258_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~258_combout\); + +-- Location: FF_X28_Y33_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~258_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\); + +-- Location: LABCELL_X29_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000001100110000111101010101111111110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\); + +-- Location: MLABCELL_X23_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~266\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~266_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~266_combout\); + +-- Location: FF_X23_Y35_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~266_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\); + +-- Location: MLABCELL_X28_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~250\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~250_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~250_combout\); + +-- Location: FF_X28_Y32_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~250_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\); + +-- Location: FF_X28_Y32_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~246_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\); + +-- Location: MLABCELL_X28_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~246\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~246_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~246_combout\); + +-- Location: FF_X28_Y32_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~246_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\); + +-- Location: FF_X23_Y35_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~262_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\); + +-- Location: LABCELL_X32_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\); + +-- Location: FF_X23_Y35_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~263_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\); + +-- Location: FF_X28_Y32_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~247_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\); + +-- Location: MLABCELL_X28_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~247\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~247_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~247_combout\); + +-- Location: FF_X28_Y32_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~247_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~251\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~251_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~251_combout\); + +-- Location: FF_X28_Y32_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~251_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\); + +-- Location: MLABCELL_X23_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~267\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~267_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~267_combout\); + +-- Location: FF_X23_Y35_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~267_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\); + +-- Location: LABCELL_X32_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\); + +-- Location: LABCELL_X29_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101100010011100110100100011011001111010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\); + +-- Location: LABCELL_X29_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\); + +-- Location: LABCELL_X29_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111100000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~89_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~33_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~17_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~1_combout\); + +-- Location: LABCELL_X29_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~2_combout\); + +-- Location: LABCELL_X29_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\); + +-- Location: LABCELL_X24_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011000000000000001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\); + +-- Location: FF_X26_Y33_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~275_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE_q\); + +-- Location: FF_X26_Y33_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~274_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\); + +-- Location: FF_X28_Y33_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~256_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\); + +-- Location: FF_X28_Y33_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~259_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\); + +-- Location: FF_X26_Y33_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~273_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\); + +-- Location: LABCELL_X29_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~14\); + +-- Location: LABCELL_X29_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~18\); + +-- Location: LABCELL_X29_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~6\); + +-- Location: LABCELL_X29_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~10\); + +-- Location: MLABCELL_X28_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~18_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~17_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3_combout\); + +-- Location: MLABCELL_X23_Y35_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\); + +-- Location: MLABCELL_X28_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\); + +-- Location: MLABCELL_X23_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\); + +-- Location: FF_X28_Y32_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~249_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\); + +-- Location: MLABCELL_X28_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2_combout\); + +-- Location: MLABCELL_X28_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\); + +-- Location: FF_X26_Y33_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~270_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE_q\); + +-- Location: FF_X26_Y33_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~271_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\); + +-- Location: LABCELL_X26_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\); + +-- Location: MLABCELL_X28_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\); + +-- Location: MLABCELL_X28_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1_combout\); + +-- Location: MLABCELL_X23_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\); + +-- Location: FF_X28_Y32_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]_OTERM1839\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\); + +-- Location: MLABCELL_X28_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\); + +-- Location: MLABCELL_X28_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\); + +-- Location: MLABCELL_X28_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010001001110010011101010101111111110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\); + +-- Location: LABCELL_X31_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8_combout\); + +-- Location: LABCELL_X31_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7_combout\); + +-- Location: LABCELL_X29_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111101000100011101110100010001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6_combout\); + +-- Location: MLABCELL_X28_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111100111111001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\); + +-- Location: LABCELL_X32_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000011110101010111111111001100110000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9_combout\); + +-- Location: LABCELL_X32_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\); + +-- Location: LABCELL_X32_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\); + +-- Location: LABCELL_X32_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\); + +-- Location: LABCELL_X32_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\); + +-- Location: LABCELL_X31_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001000110100010101100111000010011010101111001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4_combout\); + +-- Location: LABCELL_X31_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\); + +-- Location: LABCELL_X26_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~346\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~346_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~346_combout\); + +-- Location: FF_X26_Y29_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~346_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\); + +-- Location: FF_X26_Y29_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~350_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\); + +-- Location: LABCELL_X26_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~350\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~350_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~350_combout\); + +-- Location: FF_X26_Y29_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~350_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~11_combout\); + +-- Location: MLABCELL_X23_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~355\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~355_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~355_combout\); + +-- Location: FF_X23_Y30_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~355_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\); + +-- Location: MLABCELL_X23_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~354\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~354_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001110111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~354_combout\); + +-- Location: FF_X23_Y30_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~354_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\); + +-- Location: MLABCELL_X23_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~9_combout\); + +-- Location: FF_X31_Y30_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~344_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\); + +-- Location: LABCELL_X31_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~344\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~344_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~344_combout\); + +-- Location: FF_X31_Y30_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~344_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~348\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~348_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~348_combout\); + +-- Location: FF_X31_Y30_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~348_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\); + +-- Location: LABCELL_X31_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~10_combout\); + +-- Location: LABCELL_X26_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~360\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~360_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~360_combout\); + +-- Location: FF_X26_Y30_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~360_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\); + +-- Location: LABCELL_X26_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~361\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~361_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~361_combout\); + +-- Location: FF_X26_Y30_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~361_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\); + +-- Location: LABCELL_X26_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~8_combout\); + +-- Location: LABCELL_X29_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~11_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~10_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~9_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~8_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\); + +-- Location: FF_X26_Y31_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~349_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\); + +-- Location: LABCELL_X26_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~349\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~349_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~349_combout\); + +-- Location: FF_X26_Y31_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~349_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~345\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~345_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~345_combout\); + +-- Location: FF_X26_Y31_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~345_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\); + +-- Location: LABCELL_X26_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~18_combout\); + +-- Location: FF_X26_Y30_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~365_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\); + +-- Location: LABCELL_X26_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~365\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~365_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~365_combout\); + +-- Location: FF_X26_Y30_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~365_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~364\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~364_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~364_combout\); + +-- Location: FF_X26_Y30_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~364_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\); + +-- Location: LABCELL_X26_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\ ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~16_combout\); + +-- Location: LABCELL_X26_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~359\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~359_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~359_combout\); + +-- Location: FF_X26_Y31_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~359_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\); + +-- Location: FF_X23_Y30_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~358_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\); + +-- Location: MLABCELL_X23_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~358\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~358_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001110111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~358_combout\); + +-- Location: FF_X23_Y30_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~358_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~17_combout\); + +-- Location: LABCELL_X26_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~347\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~347_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~347_combout\); + +-- Location: FF_X26_Y31_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~347_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\); + +-- Location: LABCELL_X26_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~19_combout\); + +-- Location: LABCELL_X29_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~19_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~18_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~17_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~16_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~18_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~17_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~19_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\); + +-- Location: MLABCELL_X9_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]_NEW3159\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]_OTERM3160\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(18) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]_OTERM3160\); + +-- Location: FF_X9_Y23_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]_OTERM3160\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(18)); + +-- Location: MLABCELL_X9_Y23_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]_NEW3095\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]_OTERM3096\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(18) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]_OTERM3096\); + +-- Location: FF_X9_Y23_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]_OTERM3096\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(18)); + +-- Location: MLABCELL_X9_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]_NEW2967\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]_OTERM2968\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001001100011100110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]_OTERM2968\); + +-- Location: FF_X9_Y23_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]_OTERM2968\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18)); + +-- Location: MLABCELL_X9_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]_NEW3031\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]_OTERM3032\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]_OTERM3032\); + +-- Location: FF_X9_Y23_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]_OTERM3032\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18)); + +-- Location: MLABCELL_X9_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(18)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(18)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0_combout\); + +-- Location: MLABCELL_X9_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]_NEW2711\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]_OTERM2712\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]_OTERM2712\); + +-- Location: FF_X9_Y23_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]_OTERM2712\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(18)); + +-- Location: MLABCELL_X9_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]_NEW2839\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]_OTERM2840\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(18) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]_OTERM2840\); + +-- Location: FF_X9_Y23_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]_OTERM2840\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(18)); + +-- Location: MLABCELL_X9_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]_NEW2903\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]_OTERM2904\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001001100011100110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]_OTERM2904\); + +-- Location: FF_X9_Y23_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]_OTERM2904\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(18)); + +-- Location: MLABCELL_X9_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]_NEW2775\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]_OTERM2776\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(18) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]_OTERM2776\); + +-- Location: FF_X9_Y23_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]_OTERM2776\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(18)); + +-- Location: MLABCELL_X9_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(18) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(18) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(18) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(18) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1_combout\); + +-- Location: MLABCELL_X9_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\); + +-- Location: LABCELL_X10_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[18]~30_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[18]~30_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]~23_combout\); + +-- Location: FF_X10_Y15_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]~23_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18)); + +-- Location: LABCELL_X7_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[2]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[2]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100001111000000110000111111001111000011111100111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[2]~3_combout\); + +-- Location: LABCELL_X10_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[19]~33_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[19]~33_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~2_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~33_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]~22_combout\); + +-- Location: FF_X10_Y17_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]~22_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19)); + +-- Location: LABCELL_X7_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[3]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[3]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001010100010101000101010001010111010101110101011101010111010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[3]~2_combout\); + +-- Location: MLABCELL_X9_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|MEM_DATA_READ[20]~16_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|MEM_DATA_READ[20]~16_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001010001011010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]~20_combout\); + +-- Location: FF_X9_Y16_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(20)); + +-- Location: MLABCELL_X9_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[4]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[4]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(20) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[4]~0_combout\); + +-- Location: LABCELL_X10_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21) & ( \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21) & ( +-- \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21) & ( !\myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21) & ( +-- !\myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000010111111111100111000000000000100111111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(21), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]~27_combout\); + +-- Location: FF_X10_Y17_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]~27_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21)); + +-- Location: MLABCELL_X9_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[5]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[5]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100001111000000110000111111001111000011111100111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[5]~7_combout\); + +-- Location: LABCELL_X10_Y23_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]_NEW2703\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]_OTERM2704\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001001100011100110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]_OTERM2704\); + +-- Location: FF_X10_Y23_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]_OTERM2704\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22)); + +-- Location: LABCELL_X10_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]_NEW2895\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]_OTERM2896\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]_OTERM2896\); + +-- Location: FF_X10_Y23_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]_OTERM2896\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22)); + +-- Location: LABCELL_X10_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]_NEW2831\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]_OTERM2832\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(22) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]_OTERM2832\); + +-- Location: FF_X10_Y23_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]_OTERM2832\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(22)); + +-- Location: LABCELL_X10_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]_NEW2767\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]_OTERM2768\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]_OTERM2768\); + +-- Location: FF_X10_Y23_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]_OTERM2768\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22)); + +-- Location: LABCELL_X10_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(22)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(22)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101000000001111000000110101001101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1_combout\); + +-- Location: LABCELL_X10_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]_NEW3087\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]_OTERM3088\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(22))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(22))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111110001000000011111000100001101111111010000110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]_OTERM3088\); + +-- Location: FF_X10_Y23_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]_OTERM3088\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(22)); + +-- Location: LABCELL_X10_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]_NEW3023\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]_OTERM3024\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(22) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]_OTERM3024\); + +-- Location: FF_X10_Y23_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]_OTERM3024\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(22)); + +-- Location: LABCELL_X10_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]_NEW3151\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]_OTERM3152\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(22) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]_OTERM3152\); + +-- Location: FF_X10_Y23_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]_OTERM3152\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(22)); + +-- Location: LABCELL_X10_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]_NEW2959\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]_OTERM2960\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]_OTERM2960\); + +-- Location: FF_X10_Y23_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]_OTERM2960\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22)); + +-- Location: LABCELL_X10_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(22) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(22))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(22)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(22))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0_combout\); + +-- Location: LABCELL_X10_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\); + +-- Location: LABCELL_X10_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|MEM_DATA_READ[22]~13_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|MEM_DATA_READ[22]~13_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]~26_combout\); + +-- Location: FF_X10_Y17_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]~26_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(22)); + +-- Location: LABCELL_X7_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[6]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[6]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111000011110000111100100111001001110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[6]~6_combout\); + +-- Location: LABCELL_X17_Y12_N0 +\myVirtualToplevel|Mux88~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux88~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000101000001010000010100000101000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|Mux88~0_combout\); + +-- Location: FF_X17_Y12_N2 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux88~0_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(23)); + +-- Location: LABCELL_X24_Y9_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector8~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector8~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(7) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(7), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector8~0_combout\); + +-- Location: FF_X24_Y9_N25 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector8~0_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7), + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(7)); + +-- Location: LABCELL_X21_Y9_N0 +\myVirtualToplevel|IO_DATA_READ_SD[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[23]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(7) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(7), + combout => \myVirtualToplevel|IO_DATA_READ_SD[23]~feeder_combout\); + +-- Location: FF_X16_Y9_N4 +\myVirtualToplevel|SD_ADDR[0][23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\, + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][23]~q\); + +-- Location: FF_X21_Y9_N2 +\myVirtualToplevel|IO_DATA_READ_SD[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[23]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][23]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(23)); + +-- Location: FF_X16_Y11_N17 +\myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1262\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Equal3~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[22]_OTERM1263\); + +-- Location: LABCELL_X16_Y8_N9 +\myVirtualToplevel|UART1|Add10~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~40_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(7) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(7), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(7), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|Add10~40_combout\); + +-- Location: LABCELL_X16_Y8_N6 +\myVirtualToplevel|UART1|Add10~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~38_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) & ( (!\myVirtualToplevel|UART1_CS~combout\) # (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6)) ) ) # ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) & ( +-- (\myVirtualToplevel|UART1_CS~combout\ & \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(6), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(6), + combout => \myVirtualToplevel|UART1|Add10~38_combout\); + +-- Location: MLABCELL_X13_Y8_N54 +\myVirtualToplevel|UART1|Add10~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~37_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(5), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|Add10~37_combout\); + +-- Location: MLABCELL_X13_Y8_N57 +\myVirtualToplevel|UART1|Add10~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~39_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(4), + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(4), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|Add10~39_combout\); + +-- Location: LABCELL_X16_Y8_N21 +\myVirtualToplevel|UART1|Add10~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~43_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(3), + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|Add10~43_combout\); + +-- Location: LABCELL_X14_Y8_N54 +\myVirtualToplevel|UART1|Add10~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~42_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(2), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|Add10~42_combout\); + +-- Location: LABCELL_X16_Y8_N27 +\myVirtualToplevel|UART1|Add10~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~41_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(1), + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(1), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|Add10~41_combout\); + +-- Location: LABCELL_X14_Y8_N39 +\myVirtualToplevel|UART1|Add10~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~32_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(0), + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(0), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|Add10~32_combout\); + +-- Location: LABCELL_X16_Y8_N30 +\myVirtualToplevel|UART1|Add10~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~35_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + cin => GND, + cout => \myVirtualToplevel|UART1|Add10~35_cout\); + +-- Location: LABCELL_X16_Y8_N33 +\myVirtualToplevel|UART1|Add10~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~1_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~32_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0))))) ) + ( \myVirtualToplevel|UART1|Add10~35_cout\ )) +-- \myVirtualToplevel|UART1|Add10~2\ = CARRY(( \myVirtualToplevel|UART1|Add10~32_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0))))) ) + ( \myVirtualToplevel|UART1|Add10~35_cout\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000011111101100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_Add10~32_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(0), + cin => \myVirtualToplevel|UART1|Add10~35_cout\, + sumout => \myVirtualToplevel|UART1|Add10~1_sumout\, + cout => \myVirtualToplevel|UART1|Add10~2\); + +-- Location: LABCELL_X16_Y8_N36 +\myVirtualToplevel|UART1|Add10~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~21_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~41_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1)))))) ) + ( \myVirtualToplevel|UART1|Add10~2\ )) +-- \myVirtualToplevel|UART1|Add10~22\ = CARRY(( \myVirtualToplevel|UART1|Add10~41_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1)))))) ) + ( \myVirtualToplevel|UART1|Add10~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011100001111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|UART1|ALT_INV_Add10~41_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(1), + cin => \myVirtualToplevel|UART1|Add10~2\, + sumout => \myVirtualToplevel|UART1|Add10~21_sumout\, + cout => \myVirtualToplevel|UART1|Add10~22\); + +-- Location: LABCELL_X16_Y8_N39 +\myVirtualToplevel|UART1|Add10~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~25_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~42_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2)))))) ) + ( \myVirtualToplevel|UART1|Add10~22\ )) +-- \myVirtualToplevel|UART1|Add10~26\ = CARRY(( \myVirtualToplevel|UART1|Add10~42_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2)))))) ) + ( \myVirtualToplevel|UART1|Add10~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011100001111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|UART1|ALT_INV_Add10~42_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|UART1|Add10~22\, + sumout => \myVirtualToplevel|UART1|Add10~25_sumout\, + cout => \myVirtualToplevel|UART1|Add10~26\); + +-- Location: LABCELL_X16_Y8_N42 +\myVirtualToplevel|UART1|Add10~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~29_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~43_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3)))))) ) + ( \myVirtualToplevel|UART1|Add10~26\ )) +-- \myVirtualToplevel|UART1|Add10~30\ = CARRY(( \myVirtualToplevel|UART1|Add10~43_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3)))))) ) + ( \myVirtualToplevel|UART1|Add10~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011100001111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(3), + datad => \myVirtualToplevel|UART1|ALT_INV_Add10~43_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|UART1|Add10~26\, + sumout => \myVirtualToplevel|UART1|Add10~29_sumout\, + cout => \myVirtualToplevel|UART1|Add10~30\); + +-- Location: LABCELL_X16_Y8_N45 +\myVirtualToplevel|UART1|Add10~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~13_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~39_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4)))))) ) + ( \myVirtualToplevel|UART1|Add10~30\ )) +-- \myVirtualToplevel|UART1|Add10~14\ = CARRY(( \myVirtualToplevel|UART1|Add10~39_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4)))))) ) + ( \myVirtualToplevel|UART1|Add10~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011100001111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(4), + datad => \myVirtualToplevel|UART1|ALT_INV_Add10~39_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|UART1|Add10~30\, + sumout => \myVirtualToplevel|UART1|Add10~13_sumout\, + cout => \myVirtualToplevel|UART1|Add10~14\); + +-- Location: LABCELL_X16_Y8_N48 +\myVirtualToplevel|UART1|Add10~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~5_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~37_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5)))))) ) + ( \myVirtualToplevel|UART1|Add10~14\ )) +-- \myVirtualToplevel|UART1|Add10~6\ = CARRY(( \myVirtualToplevel|UART1|Add10~37_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5)))))) ) + ( \myVirtualToplevel|UART1|Add10~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011100001111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(5), + datad => \myVirtualToplevel|UART1|ALT_INV_Add10~37_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(5), + cin => \myVirtualToplevel|UART1|Add10~14\, + sumout => \myVirtualToplevel|UART1|Add10~5_sumout\, + cout => \myVirtualToplevel|UART1|Add10~6\); + +-- Location: LABCELL_X16_Y8_N51 +\myVirtualToplevel|UART1|Add10~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~9_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~38_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6)))))) ) + ( \myVirtualToplevel|UART1|Add10~6\ )) +-- \myVirtualToplevel|UART1|Add10~10\ = CARRY(( \myVirtualToplevel|UART1|Add10~38_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6)))))) ) + ( \myVirtualToplevel|UART1|Add10~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011100001111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(6), + datad => \myVirtualToplevel|UART1|ALT_INV_Add10~38_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(6), + cin => \myVirtualToplevel|UART1|Add10~6\, + sumout => \myVirtualToplevel|UART1|Add10~9_sumout\, + cout => \myVirtualToplevel|UART1|Add10~10\); + +-- Location: LABCELL_X16_Y8_N54 +\myVirtualToplevel|UART1|Add10~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add10~17_sumout\ = SUM(( (!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|Equal4~0_combout\ & +-- (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7))) # (\myVirtualToplevel|Equal4~0_combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(7)))))) ) + ( \myVirtualToplevel|UART1|Add10~40_combout\ ) + ( \myVirtualToplevel|UART1|Add10~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000000000000000000000001010101110101000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(7), + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(7), + dataf => \myVirtualToplevel|UART1|ALT_INV_Add10~40_combout\, + cin => \myVirtualToplevel|UART1|Add10~10\, + sumout => \myVirtualToplevel|UART1|Add10~17_sumout\); + +-- Location: LABCELL_X14_Y9_N6 +\myVirtualToplevel|IO_DATA_READ~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~15_combout\ = ( \myVirtualToplevel|UART0|TX_ENABLE~q\ & ( \myVirtualToplevel|UART1|Add10~17_sumout\ & ( ((!\myVirtualToplevel|UART1|TX_ENABLE~q\ & (\myVirtualToplevel|UART1_CS~combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( !\myVirtualToplevel|UART0|TX_ENABLE~q\ & ( \myVirtualToplevel|UART1|Add10~17_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- ((!\myVirtualToplevel|UART1|TX_ENABLE~q\) # (!\myVirtualToplevel|UART1_CS~combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( \myVirtualToplevel|UART0|TX_ENABLE~q\ & ( !\myVirtualToplevel|UART1|Add10~17_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((!\myVirtualToplevel|UART1|TX_ENABLE~q\ & \myVirtualToplevel|UART1_CS~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) ) # ( !\myVirtualToplevel|UART0|TX_ENABLE~q\ & ( +-- !\myVirtualToplevel|UART1|Add10~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|UART1|TX_ENABLE~q\) # ((!\myVirtualToplevel|UART1_CS~combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111011000000000011101100110011111110110011001100111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add10~17_sumout\, + combout => \myVirtualToplevel|IO_DATA_READ~15_combout\); + +-- Location: FF_X14_Y9_N7 +\myVirtualToplevel|IO_DATA_READ[23]_NEW_REG1304\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~15_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[23]_OTERM1305\); + +-- Location: FF_X16_Y11_N59 +\myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1260\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\); + +-- Location: FF_X13_Y11_N41 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~17_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\); + +-- Location: MLABCELL_X13_Y11_N24 +\myVirtualToplevel|Add13~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~25_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~22\ )) +-- \myVirtualToplevel|Add13~26\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add13~22\, + sumout => \myVirtualToplevel|Add13~25_sumout\, + cout => \myVirtualToplevel|Add13~26\); + +-- Location: MLABCELL_X13_Y11_N27 +\myVirtualToplevel|Add13~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~29_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(19) ) + ( VCC ) + ( \myVirtualToplevel|Add13~26\ )) +-- \myVirtualToplevel|Add13~30\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(19) ) + ( VCC ) + ( \myVirtualToplevel|Add13~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(19), + cin => \myVirtualToplevel|Add13~26\, + sumout => \myVirtualToplevel|Add13~29_sumout\, + cout => \myVirtualToplevel|Add13~30\); + +-- Location: FF_X13_Y11_N29 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~29_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(19)); + +-- Location: MLABCELL_X13_Y11_N30 +\myVirtualToplevel|Add13~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~13_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~30\ )) +-- \myVirtualToplevel|Add13~14\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add13~30\, + sumout => \myVirtualToplevel|Add13~13_sumout\, + cout => \myVirtualToplevel|Add13~14\); + +-- Location: FF_X13_Y11_N32 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~13_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\); + +-- Location: MLABCELL_X13_Y11_N33 +\myVirtualToplevel|Add13~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~5_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(21) ) + ( VCC ) + ( \myVirtualToplevel|Add13~14\ )) +-- \myVirtualToplevel|Add13~6\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(21) ) + ( VCC ) + ( \myVirtualToplevel|Add13~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(21), + cin => \myVirtualToplevel|Add13~14\, + sumout => \myVirtualToplevel|Add13~5_sumout\, + cout => \myVirtualToplevel|Add13~6\); + +-- Location: FF_X13_Y11_N35 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~5_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(21)); + +-- Location: MLABCELL_X13_Y11_N36 +\myVirtualToplevel|Add13~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~9_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~6\ )) +-- \myVirtualToplevel|Add13~10\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add13~6\, + sumout => \myVirtualToplevel|Add13~9_sumout\, + cout => \myVirtualToplevel|Add13~10\); + +-- Location: FF_X13_Y11_N38 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~9_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\); + +-- Location: MLABCELL_X13_Y11_N39 +\myVirtualToplevel|Add13~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add13~17_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add13~10\, + sumout => \myVirtualToplevel|Add13~17_sumout\); + +-- Location: FF_X13_Y11_N40 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~17_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(23)); + +-- Location: LABCELL_X16_Y11_N39 +\myVirtualToplevel|IO_DATA_READ~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(23) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(23) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(23), + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + combout => \myVirtualToplevel|IO_DATA_READ~16_combout\); + +-- Location: FF_X16_Y11_N41 +\myVirtualToplevel|IO_DATA_READ[23]_NEW_REG1306\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~16_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[23]_OTERM1307\); + +-- Location: LABCELL_X16_Y11_N54 +\myVirtualToplevel|IO_DATA_READ~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~17_combout\ = ( \myVirtualToplevel|IO_DATA_READ[23]_OTERM1307\ & ( (!\myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\ & (((\myVirtualToplevel|IO_DATA_READ[23]_OTERM1305\)))) # (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\ & +-- ((!\myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\ & (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1263\)) # (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\ & ((\myVirtualToplevel|IO_DATA_READ[23]_OTERM1305\))))) ) ) # ( +-- !\myVirtualToplevel|IO_DATA_READ[23]_OTERM1307\ & ( (\myVirtualToplevel|IO_DATA_READ[23]_OTERM1305\ & ((!\myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\) # (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001111000010100000111100011011000011110001101100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1265\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1263\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ[23]_OTERM1305\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1261\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ[23]_OTERM1307\, + combout => \myVirtualToplevel|IO_DATA_READ~17_combout\); + +-- Location: LABCELL_X17_Y12_N18 +\myVirtualToplevel|MEM_DATA_READ[23]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[23]~17_combout\ = ( \myVirtualToplevel|IO_DATA_READ~17_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|INTR0_CS~combout\) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) ) ) ) # ( +-- !\myVirtualToplevel|IO_DATA_READ~17_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & !\myVirtualToplevel|INTR0_CS~combout\) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ~17_combout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ_SOCCFG\(23))) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((\myVirtualToplevel|IO_DATA_READ_SD\(23)))) ) ) ) +-- # ( !\myVirtualToplevel|IO_DATA_READ~17_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ_SOCCFG\(23))) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ +-- & ((\myVirtualToplevel|IO_DATA_READ_SD\(23)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011111001100000000001111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(23), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(23), + datad => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ~17_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[23]~17_combout\); + +-- Location: FF_X19_Y12_N19 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_NEW_REG68\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\); + +-- Location: LABCELL_X19_Y12_N9 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[23]_OTERM69\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM43\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\); + +-- Location: LABCELL_X17_Y8_N30 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4_combout\ = (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7))) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7), + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]~18_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4_combout\); + +-- Location: M10K_X30_Y8_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 7, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 7, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\); + +-- Location: M10K_X11_Y9_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022220000000000000000000E040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001FFFFFDA200010000000000000000000000000000000000000000000000000000000D7FFFED6A6F77090667FFFFFD4095FFFC1CB83FFE799D19E", + mem_init2 => "E345FA0DF1A38C8004B3E01C84FD9E8081C820259F20721E4FD7C68E338BE35FE833DF82B3E6F0BC3FDA7AF45C9C2393DCE7198E6CD63A2B6EA7041E7065FC0A83223081CBF603F0E5FB01F873FF8C305A7394119C6326151AEE003DF1F11837840C40FFFFF9F3EA439943FFF26F17160C9C16580BD0048EE36C9DB550CEE1E8E15574653A2C0B601811010DB0091E70092B318342E083C16F0C8EC880826F8E521A00998A309116D1C083BC02CA339F497DC6313FC62BC069C17E3123A22B72882C81F9EA0DD60BA9A8845218A3320BFE8BA51D971CA47A7642608C618F7BA53CE037E09278418EB2142241470F84651FECB13E123F424189E0890DE8430C79", + mem_init1 => "0C0C084841BCC4C8791000001978502800140080213B1C481EF23C0E6007E7A7873B046FE01E990050030D8C708002E22A6F6230494451C0BE0428001713D8445B23C09B8221F9982CE768DC23196848E14860639E705301EC03840001C5F89E69908A91F610B69E5403F22044EECFD575604A617CC631482A7FE3C7ABFA7C78004826AE4C3C143D2949A35278C803C8281B2906040504285020A9008B00CDC48601806080108008822C47A0D2BBCE39DC3E7C41D337EA5E84116491A819E386222CE1C9371B9C3568B30A3C00810CA904A6208887DDEF480B07914000801010D0E1020000000BC3400048F00839F727BCE721121C0A44848400198100400F02", + mem_init0 => "85AD6B55811928ACD904E4E08C945661014E1C725CB4240C340006D580A200903057DCAA0010401A28024630F7EDE0A0204003422819011014120197998A88000084B68C28484FBE00CDC491FF41F73F06237FFFE3F8D1E23C58B162C58E24C51E465BBC25637784AC6EF09E73F9FCFE4C8DAB93522B24DD1434C628AA8AC0E040BB007016739CA76AAB4C9249E60902A21C0920A4162088402940124AFE2AAE1E45F71CD816BFAB3E67BF0833756567CCFD52FECAD0060001FFC3FFFFFFFFFFFFFFFFFFFFFFFFFFF87FF0FFE1FFC3FEFFFFFFFFFFFC924924924924924924FEF8000100010001042020202113000000000800020200000000040000AB130000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 7, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 7, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X18_Y12_N39 +\myVirtualToplevel|MEM_DATA_READ[23]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[23]~18_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7~portbdataout\ & ( +-- \myVirtualToplevel|LessThan0~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|LessThan0~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15~portbdataout\ & ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7~portbdataout\ & ( (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|LessThan0~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000101010100000000101010100000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datad => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[23]~18_combout\); + +-- Location: MLABCELL_X18_Y12_N51 +\myVirtualToplevel|MEM_DATA_READ[23]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[23]~18_combout\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[23]~18_combout\ ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[23]~18_combout\ & ( ((\myVirtualToplevel|MEM_DATA_READ[23]~17_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[23]~18_combout\ & ( +-- (\myVirtualToplevel|MEM_DATA_READ[23]~17_combout\ & \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011010101010111011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~17_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[23]~8_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~18_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\); + +-- Location: MLABCELL_X9_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[23]~19_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[23]~19_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~19_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]~25_combout\); + +-- Location: FF_X9_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23)); + +-- Location: MLABCELL_X9_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[7]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[7]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000000000000000000001011111010111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[7]~5_combout\); + +-- Location: M10K_X22_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init4 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + clk0_core_clock_enable => "ena0", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_evo_L2cache_a612c956.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|evo_L2cache:CACHEL2|altsyncram:RAM2_rtl_0|altsyncram_dnn1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "dont_care", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 10, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 10, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 1023, + port_a_logical_ram_depth => 1024, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock1", + port_b_address_width => 10, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 10, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 1023, + port_b_logical_ram_depth => 1024, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock1", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_WREN~0_combout\, + portbre => VCC, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + clk1 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + ena0 => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_WREN~0_combout\, + portadatain => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X31_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~340\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~340_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~340_combout\); + +-- Location: FF_X31_Y30_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~340_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\); + +-- Location: LABCELL_X31_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~336\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~336_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~336_combout\); + +-- Location: FF_X31_Y30_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~336_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\); + +-- Location: LABCELL_X31_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111111111001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~6_combout\); + +-- Location: LABCELL_X26_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]_NEW1828\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]_OTERM1829\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]_OTERM1829\); + +-- Location: FF_X26_Y29_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]_OTERM1829\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~q\); + +-- Location: FF_X26_Y29_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]_OTERM1827\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\); + +-- Location: LABCELL_X26_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]_NEW1826\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]_OTERM1827\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]_OTERM1827\); + +-- Location: FF_X26_Y29_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]_OTERM1827\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~4_combout\); + +-- Location: LABCELL_X26_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~342\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~342_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~342_combout\); + +-- Location: FF_X26_Y29_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~342_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\); + +-- Location: LABCELL_X26_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~338\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~338_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~338_combout\); + +-- Location: FF_X26_Y29_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~338_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\); + +-- Location: LABCELL_X26_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~7_combout\); + +-- Location: FF_X23_Y30_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~353_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\); + +-- Location: MLABCELL_X23_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~353\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~353_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~353_combout\); + +-- Location: FF_X23_Y30_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~353_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~352\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~352_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~352_combout\); + +-- Location: FF_X23_Y30_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~352_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\); + +-- Location: MLABCELL_X23_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~5_combout\); + +-- Location: LABCELL_X29_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~7_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~6_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~5_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~4_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\); + +-- Location: LABCELL_X26_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~339\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~339_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~339_combout\); + +-- Location: FF_X26_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~339_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\); + +-- Location: LABCELL_X26_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~343\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~343_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~343_combout\); + +-- Location: FF_X26_Y31_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~343_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\); + +-- Location: LABCELL_X26_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~15_combout\); + +-- Location: LABCELL_X29_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~341\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~341_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~341_combout\); + +-- Location: FF_X29_Y30_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~341_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\); + +-- Location: LABCELL_X29_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~14_combout\); + +-- Location: FF_X26_Y31_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~356_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\); + +-- Location: LABCELL_X26_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~356\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~356_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~356_combout\); + +-- Location: FF_X26_Y31_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~356_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~357\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~357_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~357_combout\); + +-- Location: FF_X26_Y29_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~357_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\); + +-- Location: MLABCELL_X28_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~13_combout\); + +-- Location: FF_X26_Y30_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~363_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\); + +-- Location: LABCELL_X26_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~363\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~363_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~363_combout\); + +-- Location: FF_X26_Y30_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~363_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\); + +-- Location: FF_X26_Y30_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~362_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\); + +-- Location: LABCELL_X26_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~362\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~362_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~362_combout\); + +-- Location: FF_X26_Y30_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~362_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\); + +-- Location: LABCELL_X29_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~12_combout\); + +-- Location: LABCELL_X29_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~15_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~14_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~13_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~12_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\); + +-- Location: LABCELL_X29_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100001010100110111000011001010111010011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\); + +-- Location: FF_X26_Y31_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~359_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\); + +-- Location: FF_X26_Y30_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~364_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101111101011111010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\); + +-- Location: FF_X26_Y29_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]_OTERM1829\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\); + +-- Location: FF_X26_Y30_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~360_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\); + +-- Location: FF_X23_Y30_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~354_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\); + +-- Location: FF_X23_Y30_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~352_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\); + +-- Location: FF_X23_Y30_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~355_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\); + +-- Location: LABCELL_X25_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011100010011010101101000101011001111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\); + +-- Location: FF_X26_Y31_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~351_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\); + +-- Location: LABCELL_X25_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\); + +-- Location: FF_X26_Y31_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~345_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\); + +-- Location: FF_X26_Y29_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~346_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\); + +-- Location: FF_X26_Y29_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~342_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\); + +-- Location: FF_X31_Y30_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~336_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\); + +-- Location: LABCELL_X25_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111110011000100011100110011010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\); + +-- Location: LABCELL_X25_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\); + +-- Location: MLABCELL_X28_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_RESYN12678\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_RESYN12678_BDD12679\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~69_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~61_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~61_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~69_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_RESYN12678_BDD12679\); + +-- Location: MLABCELL_X28_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_RESYN12678_BDD12679\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~65_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~49_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~53_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~57_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000100000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~65_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~49_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~53_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~57_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_RESYN12678_BDD12679\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_combout\); + +-- Location: MLABCELL_X28_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_RESYN12670\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_RESYN12670_BDD12671\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000100000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~25_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~45_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~21_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~17_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_RESYN12670_BDD12671\); + +-- Location: MLABCELL_X28_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_RESYN12670_BDD12671\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~41_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~13_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~37_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_RESYN12670_BDD12671\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\); + +-- Location: LABCELL_X25_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000110000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~89_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\); + +-- Location: LABCELL_X24_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000011000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\); + +-- Location: LABCELL_X25_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000110110000000000011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\); + +-- Location: LABCELL_X25_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\); + +-- Location: LABCELL_X24_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\); + +-- Location: LABCELL_X26_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\); + +-- Location: LABCELL_X25_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\); + +-- Location: LABCELL_X24_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110100110001001111010000000111001101111100011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\); + +-- Location: FF_X26_Y31_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~339_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~DUPLICATE_q\); + +-- Location: FF_X26_Y29_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~338_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\); + +-- Location: LABCELL_X29_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\); + +-- Location: FF_X29_Y30_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~341_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\); + +-- Location: FF_X31_Y30_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~340_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\); + +-- Location: LABCELL_X29_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\); + +-- Location: LABCELL_X24_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\); + +-- Location: FF_X26_Y31_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~347_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\); + +-- Location: LABCELL_X24_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010010001101100111000010011100110110101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\); + +-- Location: LABCELL_X29_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100001111111111110000111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\); + +-- Location: LABCELL_X25_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101011110000101010101111000010001000110000001010101011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_RESYN12672_BDD12673\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\); + +-- Location: LABCELL_X24_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\); + +-- Location: LABCELL_X19_Y26_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100101110111000100011110000110000001011000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~1_combout\); + +-- Location: LABCELL_X20_Y14_N12 +\myVirtualToplevel|MEM_DATA_READ[2]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\ & ( (\myVirtualToplevel|LessThan0~1_combout\ & +-- ((!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\ & ( (\myVirtualToplevel|LessThan0~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011000000000000001100110000001100110011000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\); + +-- Location: MLABCELL_X18_Y15_N36 +\myVirtualToplevel|MEM_DATA_READ[2]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~38_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ ) ) # ( \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[2]~36_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ & \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000011110011111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]~25_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~36_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~37_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[2]~38_combout\); + +-- Location: FF_X18_Y15_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[2]~38_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(2)); + +-- Location: FF_X19_Y18_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(2)); + +-- Location: LABCELL_X19_Y18_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\); + +-- Location: DSP_X8_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8\ : cyclonev_mac +-- pragma translate_off +GENERIC MAP ( + accumulate_clock => "none", + ax_clock => "none", + ax_width => 18, + ay_scan_in_clock => "none", + ay_scan_in_width => 18, + ay_use_scan_in => "false", + az_clock => "none", + bx_clock => "none", + by_clock => "none", + by_use_scan_in => "false", + bz_clock => "none", + coef_a_0 => 0, + coef_a_1 => 0, + coef_a_2 => 0, + coef_a_3 => 0, + coef_a_4 => 0, + coef_a_5 => 0, + coef_a_6 => 0, + coef_a_7 => 0, + coef_b_0 => 0, + coef_b_1 => 0, + coef_b_2 => 0, + coef_b_3 => 0, + coef_b_4 => 0, + coef_b_5 => 0, + coef_b_6 => 0, + coef_b_7 => 0, + coef_sel_a_clock => "none", + coef_sel_b_clock => "none", + delay_scan_out_ay => "false", + delay_scan_out_by => "false", + enable_double_accum => "false", + load_const_clock => "none", + load_const_value => 0, + mode_sub_location => 0, + negate_clock => "none", + operand_source_max => "input", + operand_source_may => "input", + operand_source_mbx => "input", + operand_source_mby => "input", + operation_mode => "m18x18_full", + output_clock => "0", + preadder_subtract_a => "false", + preadder_subtract_b => "false", + result_a_width => 64, + signed_max => "false", + signed_may => "false", + signed_mbx => "false", + signed_mby => "false", + sub_clock => "none", + use_chainadder => "false") +-- pragma translate_on +PORT MAP ( + sub => GND, + negate => GND, + aclr => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_ACLR_bus\, + clk => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_CLK_bus\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_ENA_bus\, + ax => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_AX_bus\, + ay => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_AY_bus\, + resulta => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\); + +-- Location: LABCELL_X1_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10_combout\); + +-- Location: MLABCELL_X18_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~feeder_combout\); + +-- Location: LABCELL_X14_Y24_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\); + +-- Location: LABCELL_X14_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_RESYN12778\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_RESYN12778_BDD12779\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111100111111111111110010101010101010001010101010101000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_RESYN12778_BDD12779\); + +-- Location: LABCELL_X14_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~90\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_RESYN12778_BDD12779\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000100010001000000010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_RESYN12778_BDD12779\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\); + +-- Location: LABCELL_X19_Y24_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671_BDD8672\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ $ +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000111111111111000010011001100100001001100110010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671_BDD8672\); + +-- Location: LABCELL_X19_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~119\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671_BDD8672\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671_BDD8672\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001010101000000000000000001100000010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~119_RESYN8671_BDD8672\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_combout\); + +-- Location: LABCELL_X19_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~120\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~120_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101111101011101010111110101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~119_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~120_combout\); + +-- Location: MLABCELL_X23_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\); + +-- Location: LABCELL_X19_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8669\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8669_BDD8670\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100001111111111110000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8669_BDD8670\); + +-- Location: FF_X18_Y17_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(29)); + +-- Location: MLABCELL_X18_Y17_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~feeder_combout\); + +-- Location: MLABCELL_X18_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~29_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~27\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~30\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~27\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~31\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010000000000000000000000001010101001010101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~26\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~27\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~30\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~31\); + +-- Location: MLABCELL_X18_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~13_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~31\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~14\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~31\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~15\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001100110000000000000000001100110000110011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~30\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~31\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~14\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~15\); + +-- Location: MLABCELL_X18_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~15\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~6\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~15\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~7\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~14\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~15\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~6\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~7\); + +-- Location: MLABCELL_X18_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~7\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~10\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~7\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~11\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~6\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~7\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~10\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~11\); + +-- Location: MLABCELL_X18_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~11\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~18\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~11\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~19\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010000000000000000000000001010101001010101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~10\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~11\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~18\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~19\); + +-- Location: MLABCELL_X18_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~109\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~109_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~19\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~110\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~19\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~111\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~18\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~19\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~109_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~110\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~111\); + +-- Location: MLABCELL_X18_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~105\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~105_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~111\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~110\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~106\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~111\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~110\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~107\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~110\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~111\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~105_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~106\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~107\); + +-- Location: MLABCELL_X18_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~101\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~101_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~107\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~106\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~102\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~107\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~106\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~103\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~106\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~107\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~101_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~102\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~103\); + +-- Location: MLABCELL_X18_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~97\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~97_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~103\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~102\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~98\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~103\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~102\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~99\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000101000000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~102\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~103\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~97_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~98\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~99\); + +-- Location: MLABCELL_X18_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~113\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~113_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~99\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~98\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~114\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~99\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~98\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~115\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~98\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~99\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~113_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~114\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~115\); + +-- Location: MLABCELL_X18_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~117\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~117_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~115\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~114\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~118\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~115\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~114\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~119\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~114\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~115\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~117_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~118\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~119\); + +-- Location: LABCELL_X12_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~160\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~160_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~160_combout\); + +-- Location: MLABCELL_X13_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~155\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~160_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~160_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100000001000000000101000101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~160_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\); + +-- Location: MLABCELL_X13_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~156\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~156_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111111110011001011110000111100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~155_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~156_combout\); + +-- Location: LABCELL_X16_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675_BDD8676\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000111111111111000000110011001100000011001100110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675_BDD8676\); + +-- Location: LABCELL_X16_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673_BDD8674\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $ +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010111110101111101011001000001100101100100000110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673_BDD8674\); + +-- Location: LABCELL_X17_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\); + +-- Location: LABCELL_X16_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~127\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673_BDD8674\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675_BDD8676\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673_BDD8674\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675_BDD8676\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011010000110000000000000000000000111100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_RESYN8675_BDD8676\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_RESYN8673_BDD8674\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_combout\); + +-- Location: LABCELL_X14_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111100001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\); + +-- Location: LABCELL_X19_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000111010001110111001100111111110001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\); + +-- Location: LABCELL_X14_Y24_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\); + +-- Location: MLABCELL_X13_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000000011110101010100110011111111110000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\); + +-- Location: LABCELL_X14_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\); + +-- Location: LABCELL_X17_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\); + +-- Location: LABCELL_X17_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\); + +-- Location: MLABCELL_X18_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011010101010001101110101010000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\); + +-- Location: LABCELL_X14_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~128\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000000111111001111110101111101010000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\); + +-- Location: LABCELL_X19_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011010000101010001111110110000101110101011010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\); + +-- Location: MLABCELL_X18_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001010100111101000100101011101010010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\); + +-- Location: MLABCELL_X18_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000000000000010100000000001011111000000000101111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\); + +-- Location: LABCELL_X16_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\); + +-- Location: LABCELL_X17_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000101010001001010010111101110000011110100111010101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\); + +-- Location: LABCELL_X14_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~129\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~129_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011101001100110001110111001100000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~45_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~128_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~129_combout\); + +-- Location: LABCELL_X14_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8677\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8677_BDD8678\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~129_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~129_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~129_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8677_BDD8678\); + +-- Location: FF_X18_Y22_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~4_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~93_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~94\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~65_Duplicate_152\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[1]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~90\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~93_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~94\); + +-- Location: FF_X17_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~1_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~93_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(1)); + +-- Location: LABCELL_X17_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(1) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(1) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010110011000000000000000000000000001100110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\); + +-- Location: LABCELL_X16_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010111110101111101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\); + +-- Location: LABCELL_X14_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110101111101011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\); + +-- Location: MLABCELL_X23_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[30]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[30]~feeder_combout\); + +-- Location: LABCELL_X20_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466_BDD13467\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111100001111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466_BDD13467\); + +-- Location: LABCELL_X19_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~90\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~90\); + +-- Location: LABCELL_X19_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~93_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~94\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~90\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~93_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~94\); + +-- Location: LABCELL_X19_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~94\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~94\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~94\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~86\); + +-- Location: LABCELL_X19_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~82\); + +-- Location: LABCELL_X19_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~50\); + +-- Location: LABCELL_X19_Y21_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~54\); + +-- Location: LABCELL_X19_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~70\); + +-- Location: LABCELL_X19_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~74\); + +-- Location: LABCELL_X19_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~78\); + +-- Location: LABCELL_X19_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~58\); + +-- Location: LABCELL_X19_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~62\); + +-- Location: LABCELL_X19_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~66\); + +-- Location: LABCELL_X19_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~34\); + +-- Location: LABCELL_X19_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~38\); + +-- Location: LABCELL_X19_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~42\); + +-- Location: LABCELL_X19_Y21_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~46\); + +-- Location: LABCELL_X19_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~2\); + +-- Location: LABCELL_X19_Y21_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~22\); + +-- Location: LABCELL_X19_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~26\); + +-- Location: LABCELL_X19_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~30\); + +-- Location: LABCELL_X19_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~14\); + +-- Location: LABCELL_X19_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~6\); + +-- Location: LABCELL_X19_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~10\); + +-- Location: LABCELL_X19_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~18\); + +-- Location: LABCELL_X19_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~109\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~109_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~110\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~109_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~110\); + +-- Location: LABCELL_X19_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~105\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~105_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~110\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~106\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~110\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~110\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~105_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~106\); + +-- Location: LABCELL_X19_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~101\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~101_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~106\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~102\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~106\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~106\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~101_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~102\); + +-- Location: LABCELL_X19_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~97\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~97_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~102\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~98\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~102\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~102\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~97_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~98\); + +-- Location: LABCELL_X19_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~113\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~113_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~98\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~114\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~98\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~98\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~113_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~114\); + +-- Location: LABCELL_X19_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~117\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~117_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~114\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~118\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~114\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~114\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~117_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~118\); + +-- Location: LABCELL_X19_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~121\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~118\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~122\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~118\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~118\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~122\); + +-- Location: MLABCELL_X18_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~121\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~119\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~118\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~122\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~119\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~118\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~123\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~118\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~119\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~122\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~123\); + +-- Location: LABCELL_X20_Y24_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100001111000011110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~121_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~121_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\); + +-- Location: LABCELL_X20_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_BDD9276\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466_BDD13467\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100100011011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_RESYN13466_BDD13467\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_RESYN13464_BDD13465\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_BDD9276\); + +-- Location: LABCELL_X20_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~137\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~137_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~137_combout\); + +-- Location: LABCELL_X19_Y22_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~18_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~11\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~19\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~11\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000110011010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~11\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~18_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~19\); + +-- Location: LABCELL_X19_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~120\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~120_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) +-- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~19\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~121\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~19\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~19\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~120_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~121\); + +-- Location: LABCELL_X19_Y22_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~116\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~116_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) +-- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~121\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~117\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~121\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111011110001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~121\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~116_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~117\); + +-- Location: LABCELL_X19_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~112\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~112_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +-- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~117\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~113\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~117\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011111111000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~117\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~112_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~113\); + +-- Location: LABCELL_X19_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~108\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~108_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) +-- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~113\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~109\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~113\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~113\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~108_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~109\); + +-- Location: LABCELL_X19_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~124\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~124_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +-- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~109\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~125\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~109\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011111111000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~109\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~124_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~125\); + +-- Location: LABCELL_X19_Y22_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~128\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~128_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) +-- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~125\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~129\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~125\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101111110100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~125\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~128_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~129\); + +-- Location: LABCELL_X19_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~132\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~132_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) +-- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~129\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~133\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~129\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~129\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~132_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~133\); + +-- Location: LABCELL_X14_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~144\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~144_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~144_combout\); + +-- Location: LABCELL_X16_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\); + +-- Location: LABCELL_X16_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111101010000010100000101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\); + +-- Location: LABCELL_X16_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101101011111010111100100010011101110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\); + +-- Location: LABCELL_X19_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011010000101010001111110110000101110101011010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\); + +-- Location: MLABCELL_X13_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\)))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101100011001001110100100110001101111010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36_combout\); + +-- Location: MLABCELL_X13_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001000011010011000100111101110000011100110111110001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\); + +-- Location: LABCELL_X14_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~142\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~142_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~142_combout\); + +-- Location: LABCELL_X16_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\); + +-- Location: MLABCELL_X13_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000000110000001100000101111101011111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~44_combout\); + +-- Location: LABCELL_X14_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9025\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9025_BDD9026\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~44_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010111111111010101001010000010100000101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~21_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~44_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9025_BDD9026\); + +-- Location: LABCELL_X14_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9027\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9027_BDD9028\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9025_BDD9026\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9025_BDD9026\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~144_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9025_BDD9026\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~142_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9025_BDD9026\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~144_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100111100000000000011001100110011001010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~36_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~144_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~142_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9025_BDD9026\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9027_BDD9028\); + +-- Location: LABCELL_X20_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9029\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9029_BDD9030\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9027_BDD9028\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~144_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9027_BDD9028\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9027_BDD9028\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~144_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110011111111111111110000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~144_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9027_BDD9028\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9029_BDD9030\); + +-- Location: LABCELL_X20_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~146\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9029_BDD9030\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~132_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9029_BDD9030\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~132_sumout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9029_BDD9030\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~132_sumout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9029_BDD9030\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~132_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110000000000101010000000000011111100111111001010100010101000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~132_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~17_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9029_BDD9030\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_combout\); + +-- Location: LABCELL_X16_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8685\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8685_BDD8686\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000111111111111000000110011001100000011001100110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8685_BDD8686\); + +-- Location: LABCELL_X16_Y24_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8683\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8683_BDD8684\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011110011111111001111001110101000101000101010100010100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8683_BDD8684\); + +-- Location: LABCELL_X16_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~141\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8683_BDD8684\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8685_BDD8686\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8683_BDD8684\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8685_BDD8686\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011010000110000000000000000000000111100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_RESYN8685_BDD8686\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_RESYN8683_BDD8684\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_combout\); + +-- Location: FF_X2_Y26_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]_OTERM1705\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE_q\); + +-- Location: LABCELL_X2_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ & +-- \myVirtualToplevel|RESET_n~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & ( \myVirtualToplevel|RESET_n~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ & \myVirtualToplevel|RESET_n~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000011110000111100000101000001010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~q\, + datac => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\); + +-- Location: FF_X1_Y31_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(27), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(26)); + +-- Location: FF_X1_Y31_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(26), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(25)); + +-- Location: FF_X1_Y31_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(25), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(24)); + +-- Location: FF_X1_Y31_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(24), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(23)); + +-- Location: FF_X1_Y31_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(23), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(22)); + +-- Location: FF_X1_Y31_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(22), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(21)); + +-- Location: LABCELL_X2_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & \myVirtualToplevel|RESET_n~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100000000111100110000000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~63_combout\, + datad => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\); + +-- Location: FF_X2_Y31_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]_OTERM1751\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(21)); + +-- Location: FF_X2_Y28_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(21), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(20)); + +-- Location: FF_X2_Y28_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(20), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(19)); + +-- Location: FF_X2_Y28_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]_OTERM1741\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(18)); + +-- Location: FF_X2_Y28_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[19]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(20), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[19]~DUPLICATE_q\); + +-- Location: LABCELL_X2_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[19]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[19]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[18]~feeder_combout\); + +-- Location: FF_X2_Y28_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[18]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(18)); + +-- Location: FF_X2_Y28_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(18), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(17)); + +-- Location: FF_X2_Y28_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(17), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(16)); + +-- Location: FF_X2_Y28_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(16), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(15)); + +-- Location: LABCELL_X2_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~feeder_combout\); + +-- Location: FF_X2_Y30_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(14)); + +-- Location: FF_X2_Y30_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE_q\); + +-- Location: LABCELL_X2_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[13]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[14]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[13]~feeder_combout\); + +-- Location: FF_X2_Y30_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[13]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(13)); + +-- Location: FF_X2_Y30_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(13), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(12)); + +-- Location: FF_X2_Y30_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(12), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[11]~DUPLICATE_q\); + +-- Location: FF_X2_Y30_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(12), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(11)); + +-- Location: FF_X2_Y30_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(11), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(10)); + +-- Location: FF_X6_Y32_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(10), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(9)); + +-- Location: FF_X6_Y32_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]_OTERM1727\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(9)); + +-- Location: FF_X6_Y32_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(9), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(8)); + +-- Location: LABCELL_X2_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[7]~feeder_combout\); + +-- Location: FF_X2_Y32_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[7]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7)); + +-- Location: FF_X1_Y30_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]_OTERM1723\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7)); + +-- Location: FF_X2_Y32_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6)); + +-- Location: FF_X1_Y30_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5)); + +-- Location: FF_X1_Y31_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(4)); + +-- Location: FF_X1_Y32_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(4), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(3)); + +-- Location: FF_X2_Y32_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(3), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(2)); + +-- Location: LABCELL_X2_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[1]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(2) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[1]~feeder_combout\); + +-- Location: FF_X2_Y32_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[1]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(1)); + +-- Location: FF_X2_Y32_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(1), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(0)); + +-- Location: FF_X2_Y32_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]_OTERM1709\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(0)); + +-- Location: LABCELL_X2_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]_NEW1708\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]_OTERM1709\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(0) $ +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(0)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011101000110101001110100011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]_OTERM1709\); + +-- Location: FF_X2_Y32_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]_OTERM1709\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]~DUPLICATE_q\); + +-- Location: LABCELL_X1_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~90\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(0)) ) + ( !VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~91\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000111100000000000000000000111111110000", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(0), + cin => GND, + sharein => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~90\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~91\); + +-- Location: LABCELL_X1_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~93_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(1) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(1)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~91\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~94\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(1) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(1)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~91\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~95\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(1))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(1), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~90\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~91\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~93_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~94\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~95\); + +-- Location: LABCELL_X2_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]_NEW1710\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]_OTERM1711\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~93_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~93_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~93_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]_OTERM1711\); + +-- Location: FF_X2_Y32_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]_OTERM1711\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(1)); + +-- Location: LABCELL_X1_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~85_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(2)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~95\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~94\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~86\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(2)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~95\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~94\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~87\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(2))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(2), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~94\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~95\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~86\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~87\); + +-- Location: LABCELL_X2_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[2]_NEW1712\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[2]_OTERM1713\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~85_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~85_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~85_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[2]_OTERM1713\); + +-- Location: FF_X2_Y32_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[2]_OTERM1713\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2)); + +-- Location: LABCELL_X1_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(3) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(3)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~87\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(3) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(3)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~87\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~83\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(3))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~86\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~87\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~82\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~83\); + +-- Location: MLABCELL_X4_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[3]_NEW1714\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[3]_OTERM1715\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~81_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~81_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[3]_OTERM1715\); + +-- Location: FF_X4_Y30_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[3]_OTERM1715\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(3)); + +-- Location: LABCELL_X1_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(4)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~83\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(4)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~83\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~51\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(4))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001100110000000000000000001100110000110011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~82\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~83\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~50\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~51\); + +-- Location: LABCELL_X1_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[4]_NEW1716\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[4]_OTERM1717\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(4))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~49_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~49_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~49_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[4]_OTERM1717\); + +-- Location: FF_X1_Y30_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[4]_OTERM1717\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(4)); + +-- Location: LABCELL_X1_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~55\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~50\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~51\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~54\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~55\); + +-- Location: LABCELL_X2_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[5]_NEW1718\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[5]_OTERM1719\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~53_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~53_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~53_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[5]_OTERM1719\); + +-- Location: FF_X2_Y31_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[5]_OTERM1719\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5)); + +-- Location: LABCELL_X1_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(6)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(6)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~71\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(6))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001100110000000000000000001100110000110011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(6), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~54\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~55\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~70\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~71\); + +-- Location: LABCELL_X1_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]_NEW1720\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]_OTERM1721\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(6))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~69_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~69_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~69_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]_OTERM1721\); + +-- Location: FF_X1_Y30_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]_OTERM1721\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(6)); + +-- Location: LABCELL_X1_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~71\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~71\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~75\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~70\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~71\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~74\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~75\); + +-- Location: LABCELL_X1_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]_NEW1722\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]_OTERM1723\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~73_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~73_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~73_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]_OTERM1723\); + +-- Location: FF_X1_Y30_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]_OTERM1723\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]~DUPLICATE_q\); + +-- Location: LABCELL_X1_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~75\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~75\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~79\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(8) & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~74\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~75\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~78\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~79\); + +-- Location: LABCELL_X6_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[8]_NEW1724\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[8]_OTERM1725\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~77_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~77_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[8]_OTERM1725\); + +-- Location: FF_X6_Y32_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[8]_OTERM1725\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8)); + +-- Location: LABCELL_X1_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(9) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~79\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(9) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~79\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~59\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~78\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~79\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~58\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~59\); + +-- Location: LABCELL_X6_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]_NEW1726\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]_OTERM1727\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~57_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(9) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~57_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]_OTERM1727\); + +-- Location: FF_X6_Y32_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]_OTERM1727\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]~DUPLICATE_q\); + +-- Location: LABCELL_X1_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(10)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(10)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~63\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(10))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~58\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~59\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~62\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~63\); + +-- Location: LABCELL_X2_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[10]_NEW1728\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[10]_OTERM1729\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~61_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[10]_OTERM1729\); + +-- Location: FF_X2_Y30_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[10]_OTERM1729\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10)); + +-- Location: LABCELL_X1_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~63\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~63\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~67\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[11]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000101000000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~62\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~63\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~66\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~67\); + +-- Location: LABCELL_X2_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[11]_NEW1730\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[11]_OTERM1731\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~65_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[11]_OTERM1731\); + +-- Location: FF_X2_Y30_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[11]_OTERM1731\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11)); + +-- Location: LABCELL_X1_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(12)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~67\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(12)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~67\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~35\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(12))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000101000000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(12), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~66\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~67\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~34\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~35\); + +-- Location: LABCELL_X2_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[12]_NEW1736\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[12]_OTERM1737\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~33_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~33_sumout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001100010101010000110001010101001111110101010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[12]_OTERM1737\); + +-- Location: FF_X2_Y30_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[12]_OTERM1737\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12)); + +-- Location: LABCELL_X1_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~35\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~35\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~39\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(13) & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(13))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~34\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~35\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~38\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~39\); + +-- Location: LABCELL_X2_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[13]_NEW1630\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[13]_OTERM1631\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~37_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~37_sumout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001010001100110000101000110011010111110011001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~37_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[13]_OTERM1631\); + +-- Location: FF_X2_Y30_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[13]_OTERM1631\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(13)); + +-- Location: LABCELL_X1_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(14)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~39\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(14)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~39\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~43\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(14))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(14), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~38\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~39\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~42\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~43\); + +-- Location: LABCELL_X1_Y27_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[14]_NEW1732\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[14]_OTERM1733\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~41_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~41_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~41_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[14]_OTERM1733\); + +-- Location: FF_X1_Y27_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[14]_OTERM1733\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14)); + +-- Location: LABCELL_X1_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(15)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(15)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~47\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(15))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~42\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~43\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~46\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~47\); + +-- Location: LABCELL_X1_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[15]_NEW1734\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[15]_OTERM1735\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~45_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~45_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~45_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[15]_OTERM1735\); + +-- Location: FF_X1_Y30_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[15]_OTERM1735\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15)); + +-- Location: LABCELL_X1_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(16)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~47\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~2\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(16)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~47\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~3\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(16))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~46\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~47\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~2\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~3\); + +-- Location: FF_X2_Y28_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]_OTERM1753\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16)); + +-- Location: LABCELL_X2_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]_NEW1752\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]_OTERM1753\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~1_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~1_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]_OTERM1753\); + +-- Location: FF_X2_Y28_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]_OTERM1753\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]~DUPLICATE_q\); + +-- Location: LABCELL_X1_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~21_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~3\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~22\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~3\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~23\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(17))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000101000000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~2\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~3\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~22\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~23\); + +-- Location: LABCELL_X1_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[17]_NEW1742\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[17]_OTERM1743\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~21_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[17]_OTERM1743\); + +-- Location: FF_X1_Y30_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[17]_OTERM1743\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17)); + +-- Location: LABCELL_X1_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~25_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(18)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~23\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~26\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(18)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~23\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~27\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(18))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~22\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~23\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~26\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~27\); + +-- Location: LABCELL_X2_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]_NEW1740\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]_OTERM1741\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~25_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(18) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~25_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]_OTERM1741\); + +-- Location: FF_X2_Y28_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]_OTERM1741\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]~DUPLICATE_q\); + +-- Location: LABCELL_X1_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~29_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~27\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~30\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~27\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~31\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(19) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(19))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010000000000000000000000001010101001010101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~26\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~27\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~30\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~31\); + +-- Location: LABCELL_X1_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[19]_NEW1738\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[19]_OTERM1739\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(19))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(19))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~29_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~29_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[19]_OTERM1739\); + +-- Location: FF_X1_Y30_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[19]_OTERM1739\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(19)); + +-- Location: LABCELL_X1_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~13_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(20) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~31\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~14\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(20) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~31\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~15\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(20) & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~30\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~31\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~14\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~15\); + +-- Location: LABCELL_X1_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[20]_NEW1746\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[20]_OTERM1747\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~13_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[20]_OTERM1747\); + +-- Location: FF_X1_Y29_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[20]_OTERM1747\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20)); + +-- Location: LABCELL_X1_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~15\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~6\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~15\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~7\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(21) & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010100000101000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~14\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~15\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~6\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~7\); + +-- Location: LABCELL_X2_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]_NEW1750\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]_OTERM1751\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(21))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~5_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]_OTERM1751\); + +-- Location: FF_X2_Y31_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]_OTERM1751\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE_q\); + +-- Location: LABCELL_X1_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(22)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~7\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~10\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(22)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~7\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~11\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(22))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000101000000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(22), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~6\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~7\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~10\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~11\); + +-- Location: LABCELL_X1_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[22]_NEW1748\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[22]_OTERM1749\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~9_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~9_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[22]_OTERM1749\); + +-- Location: FF_X1_Y28_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[22]_OTERM1749\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22)); + +-- Location: LABCELL_X1_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(23)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~11\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~18\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(23)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~11\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~19\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(23))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(23), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~10\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~11\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~18\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~19\); + +-- Location: MLABCELL_X4_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[23]_NEW1744\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[23]_OTERM1745\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~17_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~17_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~17_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[23]_OTERM1745\); + +-- Location: FF_X4_Y30_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[23]_OTERM1745\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23)); + +-- Location: LABCELL_X1_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~125\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~125_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(24)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~19\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~126\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(24)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~19\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~127\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(24))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000101000000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(24), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~18\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~19\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~125_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~126\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~127\); + +-- Location: LABCELL_X1_Y27_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[24]_NEW1692\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[24]_OTERM1693\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~125_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~125_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~125_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[24]_OTERM1693\); + +-- Location: FF_X1_Y27_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[24]_OTERM1693\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24)); + +-- Location: LABCELL_X1_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~121\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~121_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(25)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~127\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~126\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~122\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(25)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~127\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~126\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~123\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(25))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(25), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~126\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~127\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~121_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~122\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~123\); + +-- Location: LABCELL_X2_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[25]_NEW1694\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[25]_OTERM1695\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~121_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~121_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~121_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[25]_OTERM1695\); + +-- Location: FF_X2_Y26_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[25]_OTERM1695\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25)); + +-- Location: LABCELL_X1_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~109\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~109_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(26) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~123\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~122\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~110\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(26) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~123\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~122\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~111\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(26) & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(26), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~122\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~123\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~109_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~110\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~111\); + +-- Location: LABCELL_X1_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[26]_NEW1696\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[26]_OTERM1697\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~109_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~109_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~109_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[26]_OTERM1697\); + +-- Location: FF_X1_Y27_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[26]_OTERM1697\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26)); + +-- Location: LABCELL_X1_Y31_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~117\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~117_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(27)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~111\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~110\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~118\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(27)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~111\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~110\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~119\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(27))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010000000000000000000000001010101001010101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(27), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~110\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~111\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~117_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~118\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~119\); + +-- Location: LABCELL_X1_Y28_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[27]_NEW1698\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[27]_OTERM1699\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~117_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~117_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~117_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[27]_OTERM1699\); + +-- Location: FF_X1_Y28_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[27]_OTERM1699\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27)); + +-- Location: LABCELL_X1_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~113\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~113_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(28)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~119\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~118\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~114\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(28)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~119\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~118\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~115\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(28))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(28), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~118\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~119\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~113_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~114\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~115\); + +-- Location: LABCELL_X1_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[28]_NEW1700\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[28]_OTERM1701\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~113_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~113_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~113_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[28]_OTERM1701\); + +-- Location: FF_X1_Y27_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[28]_OTERM1701\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28)); + +-- Location: LABCELL_X1_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~101\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~101_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(29) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~115\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~114\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~102\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(29) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~115\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~114\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~103\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(29) & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001010101000000000000000001010101001010101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(29), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(29), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~114\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~115\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~101_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~102\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~103\); + +-- Location: LABCELL_X2_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[29]_NEW1702\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[29]_OTERM1703\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~101_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~101_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~101_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[29]_OTERM1703\); + +-- Location: FF_X2_Y25_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[29]_OTERM1703\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29)); + +-- Location: LABCELL_X1_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~105\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~105_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(30) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(30)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~103\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~102\ +-- )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~106\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(30) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(30)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~103\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~102\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~107\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(30) & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(30))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(30), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(30), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~102\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~103\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~105_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~106\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~107\); + +-- Location: LABCELL_X2_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]_NEW1704\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]_OTERM1705\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add60~105_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE_q\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[30]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~105_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]_OTERM1705\); + +-- Location: FF_X2_Y26_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]_OTERM1705\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(30)); + +-- Location: LABCELL_X1_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~8_combout\); + +-- Location: LABCELL_X1_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~9_combout\); + +-- Location: FF_X1_Y33_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_NEW_REG795\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~9_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM796\); + +-- Location: LABCELL_X1_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~63_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~3_combout\); + +-- Location: FF_X1_Y33_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_NEW_REG793\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\); + +-- Location: FF_X2_Y34_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_NEW_REG791\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM792\); + +-- Location: FF_X2_Y34_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_NEW_REG787\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~30_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM788\); + +-- Location: FF_X2_Y34_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_NEW_REG789\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\); + +-- Location: LABCELL_X2_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM788\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM788\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM796\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM792\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM788\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM796\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM792\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM788\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM790\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~30_combout\); + +-- Location: DSP_X8_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373\ : cyclonev_mac +-- pragma translate_off +GENERIC MAP ( + accumulate_clock => "none", + ax_clock => "none", + ax_width => 14, + ay_scan_in_clock => "none", + ay_scan_in_width => 18, + ay_use_scan_in => "false", + az_clock => "none", + bx_clock => "none", + bx_width => 14, + by_clock => "none", + by_use_scan_in => "false", + by_width => 18, + bz_clock => "none", + coef_a_0 => 0, + coef_a_1 => 0, + coef_a_2 => 0, + coef_a_3 => 0, + coef_a_4 => 0, + coef_a_5 => 0, + coef_a_6 => 0, + coef_a_7 => 0, + coef_b_0 => 0, + coef_b_1 => 0, + coef_b_2 => 0, + coef_b_3 => 0, + coef_b_4 => 0, + coef_b_5 => 0, + coef_b_6 => 0, + coef_b_7 => 0, + coef_sel_a_clock => "none", + coef_sel_b_clock => "none", + delay_scan_out_ay => "false", + delay_scan_out_by => "false", + enable_double_accum => "false", + load_const_clock => "none", + load_const_value => 0, + mode_sub_location => 0, + negate_clock => "none", + operand_source_max => "input", + operand_source_may => "input", + operand_source_mbx => "input", + operand_source_mby => "input", + operation_mode => "m18x18_sumof2", + output_clock => "0", + preadder_subtract_a => "false", + preadder_subtract_b => "false", + result_a_width => 64, + signed_max => "false", + signed_may => "false", + signed_mbx => "false", + signed_mby => "false", + sub_clock => "none", + use_chainadder => "false") +-- pragma translate_on +PORT MAP ( + sub => GND, + negate => GND, + aclr => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_ACLR_bus\, + clk => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_CLK_bus\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_ENA_bus\, + ax => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_AX_bus\, + ay => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_AY_bus\, + bx => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_BX_bus\, + by => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_BY_bus\, + resulta => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\); + +-- Location: LABCELL_X7_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~358\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~359\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM193\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM221\ ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM221\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM193\, + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~359\); + +-- Location: LABCELL_X7_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~362\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~362_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM191\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM219\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~359\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~363\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM191\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM219\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~359\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM219\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM191\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~359\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~362_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~363\); + +-- Location: LABCELL_X7_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~350\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~350_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM189\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM217\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~363\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~351\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM189\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM217\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~363\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM217\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM189\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~363\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~350_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~351\); + +-- Location: LABCELL_X7_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~342\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~342_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM187\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM215\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~351\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~343\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM187\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM215\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~351\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM215\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM187\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~351\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~342_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~343\); + +-- Location: LABCELL_X7_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~346\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~346_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM213\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM185\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~343\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~347\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM213\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM185\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~343\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM185\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM213\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~343\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~346_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~347\); + +-- Location: LABCELL_X7_Y21_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~354\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~354_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM211\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM183\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~347\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~355\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM211\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM183\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~347\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM183\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM211\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~347\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~354_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~355\); + +-- Location: LABCELL_X7_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~719\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~719_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM181\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM209\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~355\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~720\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM181\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM209\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~355\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM209\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM181\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~355\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~719_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~720\); + +-- Location: LABCELL_X7_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~715\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~715_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM207\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM179\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~720\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~716\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM207\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM179\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~720\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM207\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM179\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~720\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~715_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~716\); + +-- Location: LABCELL_X7_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~711\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~711_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM205\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM177\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~716\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~712\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM205\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM177\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~716\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM205\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM177\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~716\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~711_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~712\); + +-- Location: LABCELL_X7_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~707\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~707_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM175\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM203\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~712\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~708\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM175\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM203\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~712\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM203\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM175\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~712\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~707_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~708\); + +-- Location: LABCELL_X7_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~723\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~723_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM201\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM173\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~708\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~724\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM201\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM173\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~708\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM201\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM173\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~708\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~723_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~724\); + +-- Location: LABCELL_X7_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~727\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~727_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM171\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM199\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~724\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~728\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM171\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM199\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~724\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM199\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM171\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~724\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~727_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~728\); + +-- Location: LABCELL_X7_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~731\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~731_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM197\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM169\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~728\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~732\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM197\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM169\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~728\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM197\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM169\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~728\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~731_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~732\); + +-- Location: LABCELL_X7_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~147\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~147_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~731_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(30))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~731_sumout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(30))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~731_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(30)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~731_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(30) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000101100001011000000011111000111111011111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(30), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~731_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~147_combout\); + +-- Location: LABCELL_X20_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9277\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9277_BDD9278\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~147_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~147_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~147_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~147_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100000011000011111111111111111111110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~147_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9277_BDD9278\); + +-- Location: LABCELL_X20_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9277_BDD9278\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9277_BDD9278\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9277_BDD9278\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~137_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_BDD9276\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9277_BDD9278\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000110011001101010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_BDD9276\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~137_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9277_BDD9278\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_combout\); + +-- Location: FF_X20_Y24_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(30)); + +-- Location: FF_X19_Y14_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~121_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[30]~47_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(30)); + +-- Location: LABCELL_X26_Y6_N33 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(12) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) +-- # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(12) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(12) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & +-- ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001111110001110100000000001100110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_STD_MATCH~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o~3_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(12), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(4), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~0_combout\); + +-- Location: FF_X26_Y6_N35 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(12)); + +-- Location: LABCELL_X21_Y9_N39 +\myVirtualToplevel|IO_DATA_READ_SD[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[28]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(12) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(12), + combout => \myVirtualToplevel|IO_DATA_READ_SD[28]~feeder_combout\); + +-- Location: FF_X21_Y9_N11 +\myVirtualToplevel|SD_ADDR[0][28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28), + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][28]~q\); + +-- Location: FF_X21_Y9_N40 +\myVirtualToplevel|IO_DATA_READ_SD[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[28]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][28]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(28)); + +-- Location: LABCELL_X21_Y14_N45 +\myVirtualToplevel|MEM_DATA_READ[28]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[28]~40_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[17]~25_combout\ & ( \myVirtualToplevel|IO_DATA_READ_SD\(28) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(28), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~25_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[28]~40_combout\); + +-- Location: MLABCELL_X9_Y14_N3 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[4]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[4]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111000001010000010100100111001001111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(28), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[4]~0_combout\); + +-- Location: M10K_X30_Y4_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001020444024210448420C30C8C40440400601000B39CE7086BC6AC7858020224AA08000902240002C04080000104D00080A803DE1E1E1E000069D413A0B0162240A4095853224308009808910204891E0080000000E23B0035CC6222AD287FFFFF83546D6E58F78C0E2BD5EE8E", + mem_init2 => "8EC9D6B9C5743F943FF5E86E877B75AF16ED51FFCF41BF78DBC715D0FC938EDCF7B1CF8E9FCB71FD79AE3C7C8BDCC179EA20EC655ABC96FE6FC9233158F5FB169BC877C57FF783EABFFB01F550F71C2B0F9D6FB68DF8839EAB776D5EF5DF5765706DD77FFF9B3643F3F7E4FFBEE5667F8CE777EBDFD317DEEDAF1FE37626C78576EEC7B5937DD97E9FFE5DEABD38863D7CAE30BFF2A068DBABDB8A717F50FAEF2D28F565C6B79E6BB5DA01CECC6F710CE6B8A2571D85057957D7EB33A4A4DE62CEEDF42EAC14ADAEA7487F5AC96FB24E3E1EE7EB6DF36CB47AE8ED98A7AE51274AB9D47CD1E5A707229EAFFFEBD37CEBDABAAFCFFC65CE24E0A34D8530772D29", + mem_init1 => "0A35A26882BADA9511B79BDEDDADEEA9DEE803DD8B71246B245BD5943A6CBAA2811B72DAA5CB59C6AF6DBA56AFEBF5EE59C5EFF7F9FE7065DBFCE6CFAF2F7805C6B57307D759AF08E9F11836132975E4B01EC6FD6661D7948E36E9F1D49A616670E9ABA3B3316A8B3B4FD68C975677D51DFCB8F936C57292292BA97AEB949EF5E6BB79543B49AE3D18FCE3F3AA99BDD7D34D6F5DD99EDAE7FB4FAFFB2B9666A8E5135DB6161CE0CD0F549AD76FCABD94DAFB964E7D7563F34619D5AC5BEF25E9F2D7369DE99C9B2BB69F7636A92448DAC8BD61C3DD4F55B62D8A93DB3BB50898074F1ED9DAED63609783F65AEDE29C49CE7B63E5A8C403FDEE6EB6B3492AAB46", + mem_init0 => "BE9315B5F7BD5DDED3232A6BDEB6EE75EA32CE164DCAD7188B8BAB87CCBDC0D1FFB54CDCCD8E67CFEAFEDC6F320CBF9F5BE5A2BCCC7BE893D396E9E9A859FFA77B44F5875C5FC873440F75C2DA166A398C89E6DB65E332CC5922468D1A2091D48637A9AD1AA535A354E6B446381A0F064A51AF2A964EEB1D15453F4BEFB361DCF2F60D6FE739CF704BFD34FF4323FF1533650CDAE8ADDBBFBD29CB880AD48CD0101A56402A155A8014414A0803800602882830AB6A3497FFA96012C0000000000000000000000000025005B009601280FFFFFFFFFFFA000000000000000490FEF9000200010000A119020A2D0B03010313136103010102000743072B21130202", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 4, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 4, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\); + +-- Location: M10K_X30_Y5_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 4, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 4, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\); + +-- Location: FF_X19_Y11_N8 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\); + +-- Location: FF_X19_Y13_N53 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_NEW_REG90\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM91\); + +-- Location: IOIBUF_X25_Y0_N1 +\SDRAM_DQ[12]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(12), + o => \SDRAM_DQ[12]~input_o\); + +-- Location: DDIOINCELL_X25_Y0_N14 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_NEW_REG92\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[12]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM93\); + +-- Location: LABCELL_X19_Y13_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM93\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM91\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM93\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM91\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111101000000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]_OTERM91\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]_OTERM93\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26_combout\); + +-- Location: LABCELL_X17_Y10_N39 +\myVirtualToplevel|IO_DATA_READ~79\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~79_combout\ = ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(28) & ( \myVirtualToplevel|IO_DATA_READ[26]~78_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[26]~78_combout\, + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(28), + combout => \myVirtualToplevel|IO_DATA_READ~79_combout\); + +-- Location: FF_X17_Y10_N41 +\myVirtualToplevel|IO_DATA_READ[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~79_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(28)); + +-- Location: LABCELL_X21_Y14_N12 +\myVirtualToplevel|MEM_DATA_READ[28]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[28]~39_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26_combout\ & ( \myVirtualToplevel|IO_DATA_READ\(28) & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\) # (\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26_combout\ & ( \myVirtualToplevel|IO_DATA_READ\(28) & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & (\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & +-- ((\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26_combout\ & ( !\myVirtualToplevel|IO_DATA_READ\(28) & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & (!\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26_combout\ & ( !\myVirtualToplevel|IO_DATA_READ\(28) & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & (\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[27]~21_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010100010000000101000100010000010101010101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~23_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~20_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~21_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]~26_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(28), + combout => \myVirtualToplevel|MEM_DATA_READ[28]~39_combout\); + +-- Location: LABCELL_X21_Y14_N27 +\myVirtualToplevel|MEM_DATA_READ[28]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[28]~41_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12~portbdataout\ & ( \myVirtualToplevel|MEM_DATA_READ[28]~39_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12~portbdataout\ & ( \myVirtualToplevel|MEM_DATA_READ[28]~39_combout\ ) ) # ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12~portbdataout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[28]~39_combout\ & ( ((\myVirtualToplevel|LessThan0~1_combout\ & ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4~portbdataout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0))))) # (\myVirtualToplevel|MEM_DATA_READ[28]~40_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12~portbdataout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[28]~39_combout\ & ( ((!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0) & (\myVirtualToplevel|LessThan0~1_combout\ & +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4~portbdataout\))) # (\myVirtualToplevel|MEM_DATA_READ[28]~40_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100111011001101110011111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~40_combout\, + datac => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\, + datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~39_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[28]~41_combout\); + +-- Location: LABCELL_X16_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector985~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~14_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~14_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~14_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~14_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010001110110011101100000101000001010011011100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~14_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~8_combout\); + +-- Location: MLABCELL_X28_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~366\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~366_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~366_combout\); + +-- Location: FF_X28_Y35_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~366_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~q\); + +-- Location: LABCELL_X10_Y14_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector298~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector298~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux15~2_combout\) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[27]~59_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux15~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010101010100000101010101011111010101010101111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~59_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector298~0_combout\); + +-- Location: LABCELL_X10_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[27]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[27]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(27)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector298~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(27) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector298~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[27]~14_combout\); + +-- Location: FF_X10_Y14_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[27]~14_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(27)); + +-- Location: LABCELL_X7_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[3]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[3]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(27)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000001001000110000110111101111110011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[3]~5_combout\); + +-- Location: LABCELL_X7_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]_NEW2949\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]_OTERM2950\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001001100011100110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]_OTERM2950\); + +-- Location: FF_X7_Y25_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]_OTERM2950\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(28)); + +-- Location: LABCELL_X7_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[28]_NEW3077\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[28]_OTERM3078\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(28))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(28))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[28]_OTERM3078\); + +-- Location: FF_X7_Y25_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[28]_OTERM3078\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(28)); + +-- Location: LABCELL_X7_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[28]_NEW3013\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[28]_OTERM3014\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(28) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[28]_OTERM3014\); + +-- Location: FF_X7_Y25_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[28]_OTERM3014\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(28)); + +-- Location: LABCELL_X7_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[28]_NEW3141\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[28]_OTERM3142\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(28) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[28]_OTERM3142\); + +-- Location: FF_X7_Y25_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[28]_OTERM3142\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(28)); + +-- Location: LABCELL_X7_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux14~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(28) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(28) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(28) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(28) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(28), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(28), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~0_combout\); + +-- Location: LABCELL_X10_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[28]_NEW2885\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[28]_OTERM2886\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000100111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[28]_OTERM2886\); + +-- Location: FF_X10_Y21_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[28]_OTERM2886\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(28)); + +-- Location: LABCELL_X6_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[28]_NEW2693\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[28]_OTERM2694\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000001011011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[28]_OTERM2694\); + +-- Location: FF_X6_Y21_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[28]_OTERM2694\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(28)); + +-- Location: MLABCELL_X9_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[28]_NEW2821\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[28]_OTERM2822\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(28))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(28))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[28]_OTERM2822\); + +-- Location: FF_X9_Y22_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[28]_OTERM2822\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(28)); + +-- Location: MLABCELL_X9_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[28]_NEW2757\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[28]_OTERM2758\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(28))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(28))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[28]_OTERM2758\); + +-- Location: FF_X9_Y22_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[28]_OTERM2758\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(28)); + +-- Location: LABCELL_X5_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux14~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(28) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(28)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(28)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(28) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(28) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(28)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011000011110000000001010101001100110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(28), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~1_combout\); + +-- Location: LABCELL_X5_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux14~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~0_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~1_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux14~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~2_combout\); + +-- Location: LABCELL_X10_Y14_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector297~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector297~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[28]~41_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux14~2_combout\) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[28]~41_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux14~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001111000000001100111100110000111111110011000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~41_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector297~0_combout\); + +-- Location: LABCELL_X10_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[28]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[28]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(28)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector297~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(28) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector297~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[28]~3_combout\); + +-- Location: FF_X10_Y14_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[28]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(28)); + +-- Location: LABCELL_X7_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[4]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[4]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(28) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101000111000000110100011110001011110011111000101111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[4]~0_combout\); + +-- Location: FF_X6_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_NEW_REG767\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM768\); + +-- Location: LABCELL_X10_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[29]_NEW3139\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[29]_OTERM3140\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(29) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[29]_OTERM3140\); + +-- Location: FF_X10_Y20_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[29]_OTERM3140\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(29)); + +-- Location: LABCELL_X10_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[29]_NEW2947\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[29]_OTERM2948\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(29) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[29]_OTERM2948\); + +-- Location: FF_X10_Y20_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[29]_OTERM2948\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(29)); + +-- Location: LABCELL_X10_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[29]_NEW3011\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[29]_OTERM3012\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(29) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[29]_OTERM3012\); + +-- Location: FF_X10_Y20_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[29]_OTERM3012\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(29)); + +-- Location: LABCELL_X12_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[29]_NEW3075\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[29]_OTERM3076\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(29) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[29]_OTERM3076\); + +-- Location: FF_X12_Y21_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[29]_OTERM3076\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(29)); + +-- Location: LABCELL_X10_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux13~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(29) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(29) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(29) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(29) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(29), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(29), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~0_combout\); + +-- Location: LABCELL_X10_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[29]_NEW2819\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[29]_OTERM2820\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(29) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[29]_OTERM2820\); + +-- Location: FF_X10_Y20_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[29]_OTERM2820\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(29)); + +-- Location: LABCELL_X12_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[29]_NEW2691\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[29]_OTERM2692\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(29) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[29]_OTERM2692\); + +-- Location: FF_X12_Y21_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[29]_OTERM2692\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(29)); + +-- Location: LABCELL_X10_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[29]_NEW2755\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[29]_OTERM2756\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(29) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[29]_OTERM2756\); + +-- Location: FF_X10_Y20_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[29]_OTERM2756\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(29)); + +-- Location: LABCELL_X12_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[29]_NEW2883\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[29]_OTERM2884\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(29) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[29]_OTERM2884\); + +-- Location: FF_X12_Y21_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[29]_OTERM2884\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(29)); + +-- Location: LABCELL_X10_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux13~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(29)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(29)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(29)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(29) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(29)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101001000100111011110101111101011110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(29), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~1_combout\); + +-- Location: LABCELL_X10_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux13~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux13~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux13~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux13~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~2_combout\); + +-- Location: LABCELL_X10_Y14_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector296~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector296~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux13~2_combout\) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[29]~44_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux13~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001111000011000000111100111111000011110011111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~44_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector296~0_combout\); + +-- Location: FF_X10_Y14_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_NEW_REG769\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector296~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM770\); + +-- Location: LABCELL_X6_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM770\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM768\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM770\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM768\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111101000000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]_OTERM768\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]_OTERM770\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~8_combout\); + +-- Location: LABCELL_X6_Y18_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[5]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[5]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~8_combout\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010000010000010101001011101011111110101110101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[5]~2_combout\); + +-- Location: LABCELL_X10_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[30]_NEW3073\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[30]_OTERM3074\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(30) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[30]_OTERM3074\); + +-- Location: FF_X10_Y20_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[30]_OTERM3074\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(30)); + +-- Location: LABCELL_X10_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[30]_NEW3137\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[30]_OTERM3138\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(30) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[30]_OTERM3138\); + +-- Location: FF_X10_Y20_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[30]_OTERM3138\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(30)); + +-- Location: LABCELL_X10_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[30]_NEW2945\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[30]_OTERM2946\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(30) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001001000111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[30]_OTERM2946\); + +-- Location: FF_X10_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[30]_OTERM2946\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(30)); + +-- Location: LABCELL_X10_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[30]_NEW3009\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[30]_OTERM3010\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(30) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[30]_OTERM3010\); + +-- Location: FF_X10_Y20_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[30]_OTERM3010\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(30)); + +-- Location: LABCELL_X10_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux12~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(30)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(30)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(30))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(30) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(30))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(30), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(30), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(30), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~0_combout\); + +-- Location: MLABCELL_X9_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[30]_NEW2817\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[30]_OTERM2818\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(30))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(30))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[30]_OTERM2818\); + +-- Location: FF_X9_Y22_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[30]_OTERM2818\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(30)); + +-- Location: MLABCELL_X9_Y22_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[30]_NEW2753\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[30]_OTERM2754\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(30))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(30))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[30]_OTERM2754\); + +-- Location: FF_X9_Y22_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[30]_OTERM2754\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(30)); + +-- Location: LABCELL_X10_Y21_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[30]_NEW2881\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[30]_OTERM2882\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(30) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000010111111000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[30]_OTERM2882\); + +-- Location: FF_X10_Y21_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[30]_OTERM2882\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(30)); + +-- Location: LABCELL_X10_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[30]_NEW2689\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[30]_OTERM2690\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(30) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[30]_OTERM2690\); + +-- Location: FF_X10_Y21_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[30]_OTERM2690\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(30)); + +-- Location: LABCELL_X5_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux12~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(30)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(30) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(30))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(30) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(30))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(30), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(30), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(30), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~1_combout\); + +-- Location: LABCELL_X10_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux12~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux12~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux12~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux12~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~2_combout\); + +-- Location: LABCELL_X10_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector295~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector295~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|MEM_DATA_READ[30]~47_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux12~2_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~2_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~47_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector295~0_combout\); + +-- Location: LABCELL_X10_Y14_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[30]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[30]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(30)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector295~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(30) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector295~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[30]~6_combout\); + +-- Location: FF_X10_Y14_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[30]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(30)); + +-- Location: LABCELL_X7_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[6]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[6]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(30))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(30))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000010000100110000111011011111110011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(30), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[6]~1_combout\); + +-- Location: LABCELL_X12_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[31]_NEW3085\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[31]_OTERM3086\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(31) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[31]_OTERM3086\); + +-- Location: FF_X12_Y22_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[31]_OTERM3086\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(31)); + +-- Location: LABCELL_X12_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[31]_NEW3149\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[31]_OTERM3150\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(31) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[31]_OTERM3150\); + +-- Location: FF_X12_Y22_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[31]_OTERM3150\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(31)); + +-- Location: LABCELL_X12_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[31]_NEW3021\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[31]_OTERM3022\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(31) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[31]_OTERM3022\); + +-- Location: FF_X12_Y22_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[31]_OTERM3022\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(31)); + +-- Location: LABCELL_X7_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[31]_NEW2957\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[31]_OTERM2958\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(31) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[31]_OTERM2958\); + +-- Location: FF_X7_Y27_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[31]_OTERM2958\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(31)); + +-- Location: LABCELL_X6_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux11~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(31)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(31)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(31))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(31)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(31))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(31)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(31), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(31), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~0_combout\); + +-- Location: MLABCELL_X9_Y22_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[31]_NEW2701\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[31]_OTERM2702\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(31) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000001011111001111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[31]_OTERM2702\); + +-- Location: FF_X9_Y22_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[31]_OTERM2702\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(31)); + +-- Location: MLABCELL_X9_Y22_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[31]_NEW2765\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[31]_OTERM2766\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(31))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(31))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[31]_OTERM2766\); + +-- Location: FF_X9_Y22_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[31]_OTERM2766\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(31)); + +-- Location: LABCELL_X6_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[31]_NEW2829\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[31]_OTERM2830\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(31) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[31]_OTERM2830\); + +-- Location: FF_X6_Y22_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[31]_OTERM2830\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(31)); + +-- Location: MLABCELL_X9_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[31]_NEW2893\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[31]_OTERM2894\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(31) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[31]_OTERM2894\); + +-- Location: FF_X9_Y22_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[31]_OTERM2894\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(31)); + +-- Location: LABCELL_X6_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux11~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(31))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(31)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(31))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(31) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(31)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000001011010111110111011101110110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(31), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(31), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~1_combout\); + +-- Location: LABCELL_X6_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux11~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux11~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2_combout\); + +-- Location: LABCELL_X10_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector294~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector294~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ( \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ( \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ( !\myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010101010101010101011111010111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~50_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector294~0_combout\); + +-- Location: FF_X10_Y16_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_NEW_REG765\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector294~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_OTERM766\); + +-- Location: FF_X6_Y18_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_NEW_REG763\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_OTERM764\); + +-- Location: LABCELL_X6_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_OTERM764\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_OTERM766\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_OTERM764\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]_OTERM766\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]_OTERM764\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]~10_combout\); + +-- Location: LABCELL_X7_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[7]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[7]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000010000100110000111011011111110011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[7]~3_combout\); + +-- Location: M10K_X22_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init4 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + clk0_core_clock_enable => "ena0", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_evo_L2cache_a612c956.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|evo_L2cache:CACHEL2|altsyncram:RAM3_rtl_0|altsyncram_enn1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "dont_care", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 10, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 10, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 1023, + port_a_logical_ram_depth => 1024, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock1", + port_b_address_width => 10, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 10, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 1023, + port_b_logical_ram_depth => 1024, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock1", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_WREN~0_combout\, + portbre => VCC, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + clk1 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + ena0 => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_WREN~0_combout\, + portadatain => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X28_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~367\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~367_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~367_combout\); + +-- Location: FF_X28_Y35_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~367_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~q\); + +-- Location: MLABCELL_X28_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\); + +-- Location: LABCELL_X32_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~371\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~371_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~371_combout\); + +-- Location: FF_X32_Y29_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~371_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\); + +-- Location: LABCELL_X31_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~370\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~370_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~370_combout\); + +-- Location: FF_X31_Y32_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~370_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\); + +-- Location: LABCELL_X32_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\); + +-- Location: LABCELL_X29_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~2_combout\); + +-- Location: FF_X29_Y35_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~369_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~q\); + +-- Location: LABCELL_X29_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~369\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~369_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~369_combout\); + +-- Location: FF_X29_Y35_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~369_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE_q\); + +-- Location: FF_X29_Y35_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~368_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~q\); + +-- Location: LABCELL_X29_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~368\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~368_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~368_combout\); + +-- Location: FF_X29_Y35_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~368_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE_q\); + +-- Location: LABCELL_X29_Y35_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\); + +-- Location: FF_X32_Y34_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]_OTERM1823\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\); + +-- Location: LABCELL_X32_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]_NEW1822\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]_OTERM1823\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]_OTERM1823\); + +-- Location: FF_X32_Y34_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]_OTERM1823\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~DUPLICATE_q\); + +-- Location: FF_X32_Y34_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]_OTERM1825\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\); + +-- Location: LABCELL_X32_Y34_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]_NEW1824\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]_OTERM1825\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]_OTERM1825\); + +-- Location: FF_X32_Y34_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]_OTERM1825\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~DUPLICATE_q\); + +-- Location: LABCELL_X32_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\); + +-- Location: LABCELL_X29_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~0_combout\); + +-- Location: MLABCELL_X28_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~387\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~387_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~387_combout\); + +-- Location: FF_X28_Y34_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~387_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\); + +-- Location: LABCELL_X29_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~386\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~386_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~386_combout\); + +-- Location: FF_X29_Y35_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~386_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~q\); + +-- Location: MLABCELL_X28_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\); + +-- Location: LABCELL_X29_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~3_combout\); + +-- Location: FF_X29_Y35_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~384_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~q\); + +-- Location: LABCELL_X29_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~384\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~384_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~384_combout\); + +-- Location: FF_X29_Y35_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~384_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE_q\); + +-- Location: FF_X26_Y29_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~385_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\); + +-- Location: LABCELL_X26_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~385\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~385_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~385_combout\); + +-- Location: FF_X26_Y29_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~385_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\); + +-- Location: FF_X28_Y35_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~380_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~q\); + +-- Location: MLABCELL_X28_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~380\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~380_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~q\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~380_combout\); + +-- Location: FF_X28_Y35_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~380_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~381\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~381_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~381_combout\); + +-- Location: FF_X28_Y30_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~381_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\); + +-- Location: MLABCELL_X28_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\); + +-- Location: LABCELL_X29_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~1_combout\); + +-- Location: MLABCELL_X28_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010100010000001111010011101010010111100100101011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\); + +-- Location: MLABCELL_X23_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_RESYN8957\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_RESYN8957_BDD8958\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000110000000000000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_RESYN8957_BDD8958\); + +-- Location: MLABCELL_X23_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_RESYN8957_BDD8958\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_RESYN8957_BDD8958\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_RESYN8957_BDD8958\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\); + +-- Location: LABCELL_X16_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8749\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8749_BDD8750\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector985~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~8_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~8_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~8_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8749_BDD8750\); + +-- Location: LABCELL_X16_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~6_combout\); + +-- Location: LABCELL_X1_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~4_combout\); + +-- Location: FF_X1_Y33_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_NEW_REG799\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM800\); + +-- Location: FF_X2_Y31_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[20]_NEW_REG1212\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[20]_OTERM1213\); + +-- Location: LABCELL_X2_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~5_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101000001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~5_combout\); + +-- Location: FF_X2_Y31_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\); + +-- Location: LABCELL_X2_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM800\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[20]_OTERM1213\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[20]_OTERM1213\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[28]_OTERM800\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[20]_OTERM1213\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~3_combout\); + +-- Location: LABCELL_X2_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111101010101010101010101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~0_combout\); + +-- Location: LABCELL_X5_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~350_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~350_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~350_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111001100110011001100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~350_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~1_combout\); + +-- Location: LABCELL_X16_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000010100000111100001010000011110000101000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~2_combout\); + +-- Location: LABCELL_X17_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8745\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8745_BDD8746\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110011111111000011001111111111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8745_BDD8746\); + +-- Location: LABCELL_X16_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN9337\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN9337_BDD9338\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000001110011010100000111001101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN9337_BDD9338\); + +-- Location: LABCELL_X16_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12594\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12594_BDD12595\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN9337_BDD9338\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8745_BDD8746\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8745_BDD8746\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN9337_BDD9338\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8745_BDD8746\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100010101000001010001010100000101001101110000010100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~5_RESYN8745_BDD8746\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN9337_BDD9338\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12594_BDD12595\); + +-- Location: LABCELL_X16_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector985~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~61_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~7_combout\); + +-- Location: LABCELL_X16_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector985~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~13_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001101010101011101110101010101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~5_combout\); + +-- Location: LABCELL_X16_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12592\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12592_BDD12593\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~7_combout\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector985~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~7_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector985~5_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector985~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101011101010111010101010101010111111111111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12592_BDD12593\); + +-- Location: LABCELL_X16_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9335\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9335_BDD9336\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100001111001111110000111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[20]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9335_BDD9336\); + +-- Location: MLABCELL_X13_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100010001110100011100110011111111110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\); + +-- Location: LABCELL_X14_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011010001110100011111001100111111110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\); + +-- Location: MLABCELL_X13_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000011011101110000001101000100110011110111011111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~14_combout\); + +-- Location: LABCELL_X14_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\)))) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001010010000000100101001010100010111100101010001011110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5_combout\); + +-- Location: LABCELL_X16_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~14_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~14_combout\)))) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000110001000000000011110100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~14_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~14_combout\); + +-- Location: MLABCELL_X18_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101111101011111010100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\); + +-- Location: LABCELL_X16_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111001101010011010111110000111111110011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\); + +-- Location: LABCELL_X17_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\); + +-- Location: MLABCELL_X18_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000010100101111110111011101110110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\); + +-- Location: MLABCELL_X18_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010001000100101111101110111000010100111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~21_combout\); + +-- Location: MLABCELL_X18_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111001100000011000001010000010111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\); + +-- Location: MLABCELL_X18_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\); + +-- Location: LABCELL_X17_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000000000000010100000000001011111000000000101111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~23_combout\); + +-- Location: LABCELL_X17_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~23_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~21_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~23_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~21_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101111110001010110111111000101011010000100000001101000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~21_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~23_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~15_combout\); + +-- Location: LABCELL_X16_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~15_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~16_combout\); + +-- Location: LABCELL_X16_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_RESYN13470\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~13_sumout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~13_sumout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100001010000001010000101000000101000010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\); + +-- Location: LABCELL_X16_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_BDD9334\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~13_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~13_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_BDD9334\); + +-- Location: LABCELL_X16_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_BDD8964\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_BDD9334\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~16_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_BDD9334\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_BDD9334\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9335_BDD9336\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~16_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_BDD9334\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~14_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9335_BDD9336\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101011101010111010111110101111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9335_BDD9336\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9333_BDD9334\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_BDD8964\); + +-- Location: LABCELL_X16_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_BDD8966\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12592_BDD12593\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_BDD8964\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12592_BDD12593\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_BDD8964\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12594_BDD12595\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12592_BDD12593\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_BDD8964\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12592_BDD12593\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_BDD8964\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12594_BDD12595\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011101010101111111111111111101111111010111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN12594_BDD12595\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN12592_BDD12593\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_BDD8964\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_BDD8966\); + +-- Location: LABCELL_X31_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~5_combout\); + +-- Location: FF_X26_Y35_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~392_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~DUPLICATE_q\); + +-- Location: FF_X26_Y35_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~393_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~6_combout\); + +-- Location: LABCELL_X29_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~8_combout\); + +-- Location: LABCELL_X32_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~7_combout\); + +-- Location: LABCELL_X31_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~5_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000011110011001111111111010101010000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~9_combout\); + +-- Location: FF_X29_Y35_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~386_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\); + +-- Location: FF_X28_Y35_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~366_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~1_combout\); + +-- Location: LABCELL_X32_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~2_combout\); + +-- Location: LABCELL_X32_Y35_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~3_combout\); + +-- Location: FF_X28_Y35_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~367_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~383\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~383_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~383_combout\); + +-- Location: FF_X28_Y35_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~383_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\); + +-- Location: LABCELL_X31_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~0_combout\); + +-- Location: LABCELL_X31_Y35_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000011001010011000101110100101010001110110110111001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~4_combout\); + +-- Location: LABCELL_X31_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~9_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\); + +-- Location: LABCELL_X16_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector985~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001100000011110011111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~0_combout\); + +-- Location: LABCELL_X16_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8967\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8967_BDD8968\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_BDD8964\) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector985~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_BDD8964\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_BDD8964\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8967_BDD8968\); + +-- Location: LABCELL_X16_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_BDD8966\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8967_BDD8968\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~2_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_BDD8966\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8967_BDD8968\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8749_BDD8750\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_BDD8966\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8967_BDD8968\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_BDD8966\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8967_BDD8968\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8749_BDD8750\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100010001111111110101010111111111000111111111111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~5_RESYN8749_BDD8750\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_BDD8966\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8967_BDD8968\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_combout\); + +-- Location: FF_X16_Y22_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(20)); + +-- Location: LABCELL_X14_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110100000111111111010000011001100100000001100110010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~7_combout\); + +-- Location: MLABCELL_X18_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~4_combout\); + +-- Location: LABCELL_X19_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~6_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~6_combout\); + +-- Location: MLABCELL_X18_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~4_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~4_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100101010001010100011111100000000001010100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~8_combout\); + +-- Location: LABCELL_X21_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~8_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~7_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~8_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~8_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111110000000000001111010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~9_combout\); + +-- Location: LABCELL_X19_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101010000010001000011000000010010001000100101011100100000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5_combout\); + +-- Location: LABCELL_X20_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\); + +-- Location: LABCELL_X21_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~13_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~9_combout\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~9_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0011001100100000001100110010001111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~9_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~13_combout\); + +-- Location: LABCELL_X25_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000001000000010000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\); + +-- Location: LABCELL_X31_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~242\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~242_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~242_combout\); + +-- Location: FF_X31_Y32_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~242_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\); + +-- Location: LABCELL_X31_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~243\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~243_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~243_combout\); + +-- Location: FF_X31_Y32_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~243_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\); + +-- Location: LABCELL_X29_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~235\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~235_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~235_combout\); + +-- Location: FF_X29_Y32_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~235_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~q\); + +-- Location: FF_X29_Y32_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~234_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\); + +-- Location: LABCELL_X29_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~234\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~234_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~234_combout\); + +-- Location: FF_X29_Y32_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~234_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\); + +-- Location: LABCELL_X29_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~6_combout\); + +-- Location: LABCELL_X31_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~239\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~239_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~239_combout\); + +-- Location: FF_X31_Y32_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~239_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\); + +-- Location: LABCELL_X29_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~230\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~230_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~230_combout\); + +-- Location: FF_X29_Y32_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~230_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\); + +-- Location: LABCELL_X29_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~231\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~231_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~231_combout\); + +-- Location: FF_X29_Y32_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~231_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\); + +-- Location: LABCELL_X31_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~238\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~238_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~238_combout\); + +-- Location: FF_X31_Y32_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~238_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\); + +-- Location: LABCELL_X29_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~8_combout\); + +-- Location: FF_X28_Y32_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]_OTERM1843\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~q\); + +-- Location: MLABCELL_X28_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]_NEW1842\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]_OTERM1843\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]_OTERM1843\); + +-- Location: FF_X28_Y32_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]_OTERM1843\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]_NEW1844\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]_OTERM1845\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]_OTERM1845\); + +-- Location: FF_X23_Y32_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]_OTERM1845\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~q\); + +-- Location: FF_X23_Y32_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~223_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\); + +-- Location: MLABCELL_X23_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~223\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~223_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~223_combout\); + +-- Location: FF_X23_Y32_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~223_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE_q\); + +-- Location: FF_X23_Y32_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~222_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~q\); + +-- Location: MLABCELL_X23_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~222\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~222_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~222_combout\); + +-- Location: FF_X23_Y32_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~222_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~7_combout\); + +-- Location: FF_X24_Y32_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~218_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\); + +-- Location: LABCELL_X24_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~218\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~218_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~218_combout\); + +-- Location: FF_X24_Y32_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~218_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE_q\); + +-- Location: FF_X24_Y32_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~219_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\); + +-- Location: LABCELL_X24_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~219\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~219_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~219_combout\); + +-- Location: FF_X24_Y32_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~219_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE_q\); + +-- Location: FF_X23_Y32_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~227_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\); + +-- Location: MLABCELL_X23_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~227\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~227_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~227_combout\); + +-- Location: FF_X23_Y32_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~227_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE_q\); + +-- Location: FF_X23_Y32_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~226_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\); + +-- Location: LABCELL_X24_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~5_combout\); + +-- Location: LABCELL_X29_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~6_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~8_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~6_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~5_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~6_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000101111100110000010100000011111101011111001111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~9_combout\); + +-- Location: LABCELL_X31_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~244\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~244_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~244_combout\); + +-- Location: FF_X31_Y32_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~244_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\); + +-- Location: MLABCELL_X23_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~228\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~228_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~228_combout\); + +-- Location: FF_X23_Y32_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~228_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\); + +-- Location: FF_X23_Y32_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~224_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~q\); + +-- Location: MLABCELL_X23_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~224\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~224_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~224_combout\); + +-- Location: FF_X23_Y32_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~224_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\); + +-- Location: FF_X31_Y32_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~240_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~q\); + +-- Location: LABCELL_X31_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~240\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~240_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111110100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~240_combout\); + +-- Location: FF_X31_Y32_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~240_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\); + +-- Location: LABCELL_X29_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~3_combout\); + +-- Location: LABCELL_X29_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~237\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~237_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~237_combout\); + +-- Location: FF_X29_Y32_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~237_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\); + +-- Location: FF_X24_Y32_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~233_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~q\); + +-- Location: LABCELL_X24_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~233\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~233_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~233_combout\); + +-- Location: FF_X24_Y32_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~233_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE_q\); + +-- Location: FF_X24_Y32_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~221_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~q\); + +-- Location: LABCELL_X24_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~221\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~221_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~221_combout\); + +-- Location: FF_X24_Y32_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~221_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE_q\); + +-- Location: FF_X24_Y32_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~217_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\); + +-- Location: LABCELL_X24_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~217\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~217_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~217_combout\); + +-- Location: FF_X24_Y32_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~217_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~DUPLICATE_q\); + +-- Location: LABCELL_X29_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~0_combout\); + +-- Location: FF_X31_Y32_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~241_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~q\); + +-- Location: LABCELL_X31_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~241\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~241_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~241_combout\); + +-- Location: FF_X31_Y32_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~241_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\); + +-- Location: FF_X23_Y32_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~225_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~q\); + +-- Location: MLABCELL_X23_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~225\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~225_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~225_combout\); + +-- Location: FF_X23_Y32_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~225_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~245\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~245_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~245_combout\); + +-- Location: FF_X31_Y32_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~245_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~q\); + +-- Location: MLABCELL_X23_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~229\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~229_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~229_combout\); + +-- Location: FF_X23_Y32_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~229_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\); + +-- Location: LABCELL_X29_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~2_combout\); + +-- Location: FF_X24_Y32_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~232_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\); + +-- Location: LABCELL_X24_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~232\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~232_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~232_combout\); + +-- Location: FF_X24_Y32_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~232_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~220\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~220_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~220_combout\); + +-- Location: FF_X25_Y32_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~220_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\); + +-- Location: LABCELL_X29_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~236\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~236_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~236_combout\); + +-- Location: FF_X29_Y32_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~236_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\); + +-- Location: LABCELL_X25_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~216\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~216_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~216_combout\); + +-- Location: FF_X25_Y32_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~216_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\); + +-- Location: LABCELL_X24_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~1_combout\); + +-- Location: LABCELL_X29_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001100000100010011111111011101000011001101110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~4_combout\); + +-- Location: LABCELL_X29_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~9_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\); + +-- Location: LABCELL_X21_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010001110111010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~2_combout\); + +-- Location: FF_X20_Y17_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(16)); + +-- Location: LABCELL_X20_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(16))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(16)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(16)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ $ +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(16)))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(16)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111100110101001010101100101011010101100111111000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~0_combout\); + +-- Location: LABCELL_X17_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111000000000010101000101010001010100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~0_combout\); + +-- Location: LABCELL_X24_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~q\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\); + +-- Location: LABCELL_X24_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\); + +-- Location: MLABCELL_X23_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\); + +-- Location: LABCELL_X31_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\); + +-- Location: MLABCELL_X28_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~2_combout\); + +-- Location: MLABCELL_X23_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\); + +-- Location: LABCELL_X29_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\); + +-- Location: MLABCELL_X23_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111110011111100111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\); + +-- Location: FF_X31_Y32_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~239_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~DUPLICATE_q\); + +-- Location: FF_X31_Y32_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~238_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\); + +-- Location: MLABCELL_X28_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~0_combout\); + +-- Location: LABCELL_X24_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\); + +-- Location: LABCELL_X29_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~q\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\); + +-- Location: FF_X31_Y32_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~243_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\); + +-- Location: MLABCELL_X28_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~1_combout\); + +-- Location: FF_X29_Y32_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~237_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~DUPLICATE_q\); + +-- Location: LABCELL_X29_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\); + +-- Location: FF_X23_Y32_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~228_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~DUPLICATE_q\); + +-- Location: FF_X23_Y32_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~229_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\); + +-- Location: LABCELL_X24_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\); + +-- Location: FF_X31_Y32_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~244_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~DUPLICATE_q\); + +-- Location: FF_X31_Y32_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~245_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\); + +-- Location: MLABCELL_X28_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~3_combout\); + +-- Location: MLABCELL_X28_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\); + +-- Location: MLABCELL_X18_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000100110000101010011011110001100101011101001110110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~4_combout\); + +-- Location: MLABCELL_X18_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000001000111111111101011110000000000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~4_combout\); + +-- Location: LABCELL_X20_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100000011000111011100111111010001000011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\); + +-- Location: LABCELL_X14_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010100010000001111010011101010010111100100101011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4_combout\); + +-- Location: LABCELL_X20_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000000011000010101111001101011111000000110101111111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~5_combout\); + +-- Location: LABCELL_X20_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~1_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~1_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~1_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~1_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000101010101010000011001100110000001000100010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~12_combout\); + +-- Location: MLABCELL_X18_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~90\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\) ) + ( !VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~91\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111111100000000000000000000111111110000", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + cin => GND, + sharein => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~90\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~91\); + +-- Location: MLABCELL_X18_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~93_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~91\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~94\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~91\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~95\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~90\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~91\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~93_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~94\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~95\); + +-- Location: MLABCELL_X18_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~85_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~95\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~94\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~86\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~95\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~94\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~87\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~94\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~95\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~86\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~87\); + +-- Location: MLABCELL_X18_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~87\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~87\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~83\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~86\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~87\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~82\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~83\); + +-- Location: MLABCELL_X18_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~83\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~83\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~51\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~82\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~83\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~50\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~51\); + +-- Location: MLABCELL_X18_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~51\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~51\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~55\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~50\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~51\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~54\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~55\); + +-- Location: MLABCELL_X18_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~55\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~55\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~71\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~54\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~55\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~70\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~71\); + +-- Location: MLABCELL_X18_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~71\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~71\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~75\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~70\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~71\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~74\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~75\); + +-- Location: MLABCELL_X18_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~75\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~75\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~79\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~74\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~75\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~78\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~79\); + +-- Location: MLABCELL_X18_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~79\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~79\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~59\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001010101000000000000000001010101001010101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~78\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~79\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~58\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~59\); + +-- Location: MLABCELL_X18_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~59\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~59\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~63\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~58\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~59\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~62\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~63\); + +-- Location: MLABCELL_X18_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~63\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~63\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~67\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000101000000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~62\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~63\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~66\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~67\); + +-- Location: MLABCELL_X18_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~67\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~67\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~35\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~66\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~67\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~34\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~35\); + +-- Location: MLABCELL_X18_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~35\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~35\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~39\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~34\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~35\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~38\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~39\); + +-- Location: MLABCELL_X18_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~39\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~39\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~43\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~38\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~39\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~42\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~43\); + +-- Location: MLABCELL_X18_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~43\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~43\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~47\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~42\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~43\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~46\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~47\); + +-- Location: MLABCELL_X18_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~47\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~2\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~47\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~3\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~46\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~47\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~2\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~3\); + +-- Location: LABCELL_X21_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~12_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~1_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~12_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~12_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101000000000000010001000000000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~1_combout\); + +-- Location: FF_X2_Y31_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[16]_NEW_REG1238\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[16]_OTERM1239\); + +-- Location: FF_X2_Y33_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE_q\); + +-- Location: LABCELL_X2_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM800\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[16]_OTERM1239\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[16]_OTERM1239\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[28]_OTERM800\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[16]_OTERM1239\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~0_combout\); + +-- Location: LABCELL_X2_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100000000001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~2_combout\); + +-- Location: MLABCELL_X4_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(16) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111110000111100001111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~3_combout\); + +-- Location: LABCELL_X21_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100111100001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~4_combout\); + +-- Location: LABCELL_X21_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~13_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100010011000100110000001100010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~5_combout\); + +-- Location: FF_X21_Y25_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~5_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(16)); + +-- Location: LABCELL_X20_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\); + +-- Location: FF_X20_Y15_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector343~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~45_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~45_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~1_combout\); + +-- Location: FF_X25_Y33_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~287_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\); + +-- Location: LABCELL_X25_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~287\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~287_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~287_combout\); + +-- Location: FF_X25_Y33_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~287_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~278\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~278_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~278_combout\); + +-- Location: FF_X25_Y34_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~278_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\); + +-- Location: LABCELL_X25_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~279\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~279_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001110111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~279_combout\); + +-- Location: FF_X25_Y35_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~279_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\); + +-- Location: FF_X25_Y33_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~286_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~q\); + +-- Location: LABCELL_X25_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~286\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~286_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~286_combout\); + +-- Location: FF_X25_Y33_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~286_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\); + +-- Location: LABCELL_X25_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~291\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~291_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~291_combout\); + +-- Location: FF_X25_Y35_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~291_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~q\); + +-- Location: LABCELL_X25_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~298\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~298_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~298_combout\); + +-- Location: FF_X25_Y35_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~298_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\); + +-- Location: FF_X25_Y35_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~299_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\); + +-- Location: LABCELL_X25_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~299\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~299_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~299_combout\); + +-- Location: FF_X25_Y35_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~299_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y35_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~290\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~290_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~290_combout\); + +-- Location: FF_X25_Y35_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~290_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\); + +-- Location: LABCELL_X25_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111111110101010100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\); + +-- Location: LABCELL_X25_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]_NEW1848\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]_OTERM1849\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]_OTERM1849\); + +-- Location: FF_X25_Y33_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]_OTERM1849\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\); + +-- Location: FF_X25_Y33_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~283_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~q\); + +-- Location: LABCELL_X25_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~283\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~283_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~283_combout\); + +-- Location: FF_X25_Y33_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~283_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]_NEW1846\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]_OTERM1847\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]_OTERM1847\); + +-- Location: FF_X25_Y33_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]_OTERM1847\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\); + +-- Location: LABCELL_X25_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~282\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~282_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~282_combout\); + +-- Location: FF_X25_Y33_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~282_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\); + +-- Location: LABCELL_X25_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\); + +-- Location: LABCELL_X25_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~295\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~295_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~295_combout\); + +-- Location: FF_X25_Y33_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~295_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\); + +-- Location: LABCELL_X25_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~303\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~303_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~303_combout\); + +-- Location: FF_X25_Y33_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~303_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~q\); + +-- Location: LABCELL_X25_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~294\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~294_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~294_combout\); + +-- Location: FF_X25_Y33_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~294_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~q\); + +-- Location: LABCELL_X25_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~302\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~302_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~302_combout\); + +-- Location: FF_X25_Y33_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~302_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\); + +-- Location: LABCELL_X25_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\); + +-- Location: LABCELL_X24_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000100110100011001010111000010101001101111001110110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~9_combout\); + +-- Location: FF_X25_Y32_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~280_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~q\); + +-- Location: LABCELL_X25_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~280\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~280_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~280_combout\); + +-- Location: FF_X25_Y32_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~280_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\); + +-- Location: FF_X25_Y32_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~276_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\); + +-- Location: LABCELL_X25_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~276\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~276_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~276_combout\); + +-- Location: FF_X25_Y32_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~276_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\); + +-- Location: FF_X25_Y32_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~292_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\); + +-- Location: LABCELL_X25_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~292\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~292_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~292_combout\); + +-- Location: FF_X25_Y32_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~292_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE_q\); + +-- Location: LABCELL_X29_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~1_combout\); + +-- Location: LABCELL_X25_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~281\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~281_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~281_combout\); + +-- Location: FF_X25_Y32_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~281_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~q\); + +-- Location: FF_X25_Y32_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~293_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~q\); + +-- Location: LABCELL_X25_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~293\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~293_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~293_combout\); + +-- Location: FF_X25_Y32_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~293_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~0_combout\); + +-- Location: MLABCELL_X28_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~289\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~289_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~289_combout\); + +-- Location: FF_X28_Y32_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~289_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\); + +-- Location: MLABCELL_X28_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~305\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~305_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~305_combout\); + +-- Location: FF_X28_Y31_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~305_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\); + +-- Location: LABCELL_X26_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~301\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~301_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~301_combout\); + +-- Location: FF_X26_Y33_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~301_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\); + +-- Location: MLABCELL_X28_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~285\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~285_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~285_combout\); + +-- Location: FF_X28_Y31_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~285_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\); + +-- Location: MLABCELL_X28_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~2_combout\); + +-- Location: MLABCELL_X28_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~300\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~300_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~300_combout\); + +-- Location: FF_X28_Y31_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~300_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\); + +-- Location: FF_X28_Y31_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~304_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\); + +-- Location: MLABCELL_X28_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~304\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~304_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~304_combout\); + +-- Location: FF_X28_Y31_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~304_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~288\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~288_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ +-- & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~288_combout\); + +-- Location: FF_X28_Y32_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~288_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\); + +-- Location: MLABCELL_X28_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~284\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~284_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~284_combout\); + +-- Location: FF_X28_Y31_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~284_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\); + +-- Location: MLABCELL_X28_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~3_combout\); + +-- Location: MLABCELL_X28_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~0_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000110010101110100101010011011100011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4_combout\); + +-- Location: LABCELL_X25_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~9_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\); + +-- Location: LABCELL_X24_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101111100000000001100000000000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~3_combout\); + +-- Location: FF_X2_Y33_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_NEW_REG1182\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1183\); + +-- Location: FF_X2_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_NEW_REG1180\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~11_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1181\); + +-- Location: LABCELL_X2_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~12_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~12_combout\); + +-- Location: FF_X2_Y31_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_NEW_REG1184\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~12_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1185\); + +-- Location: LABCELL_X2_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1185\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1183\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1181\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1185\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1181\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1183\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1181\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1185\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~11_combout\); + +-- Location: LABCELL_X2_Y31_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~11_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111101010101010111110101010101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~0_combout\); + +-- Location: LABCELL_X5_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(15) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(15) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(15) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111111111111111110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~1_combout\); + +-- Location: MLABCELL_X23_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010000000000000000011001000110010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~2_combout\); + +-- Location: FF_X19_Y17_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(15)); + +-- Location: LABCELL_X20_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(15)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(15)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ $ +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(15)))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(15))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(15)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111011001100011110010011001110000111010101011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~5_combout\); + +-- Location: LABCELL_X20_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~5_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001100000000111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~2_combout\); + +-- Location: LABCELL_X20_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~45_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~2_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010111100001010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~45_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~4_combout\); + +-- Location: FF_X25_Y32_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~281_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\); + +-- Location: LABCELL_X26_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010111111111010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\); + +-- Location: LABCELL_X25_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\); + +-- Location: LABCELL_X31_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~2_combout\); + +-- Location: LABCELL_X25_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\); + +-- Location: FF_X25_Y35_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~290_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~DUPLICATE_q\); + +-- Location: FF_X25_Y35_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~291_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\); + +-- Location: LABCELL_X26_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\); + +-- Location: LABCELL_X31_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111001100000011000001010000010111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~0_combout\); + +-- Location: LABCELL_X26_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~q\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111111111001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\); + +-- Location: FF_X28_Y31_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~285_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\); + +-- Location: LABCELL_X25_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\); + +-- Location: FF_X28_Y31_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~300_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\); + +-- Location: LABCELL_X31_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~1_combout\); + +-- Location: LABCELL_X26_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\); + +-- Location: FF_X25_Y33_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~302_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\); + +-- Location: FF_X25_Y33_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~303_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\); + +-- Location: MLABCELL_X28_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\); + +-- Location: MLABCELL_X28_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\); + +-- Location: LABCELL_X31_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~3_combout\); + +-- Location: LABCELL_X31_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~2_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~2_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~2_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011100010011010101101000101011001111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\); + +-- Location: MLABCELL_X18_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~4_combout\); + +-- Location: MLABCELL_X18_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~45_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000110011001100000010101010101000001000100010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~5_combout\); + +-- Location: MLABCELL_X18_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~50_combout\); + +-- Location: LABCELL_X24_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~69_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~40_combout\); + +-- Location: MLABCELL_X18_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~40_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~47_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~50_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~47_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~50_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~40_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~50_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~50_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010110011001000100011110000101000001100000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~50_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~40_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~47_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~6_combout\); + +-- Location: MLABCELL_X18_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~6_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~5_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~4_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111110011001100111111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~7_combout\); + +-- Location: MLABCELL_X18_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~7_combout\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~7_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101010100000100010101010100010111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~7_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~8_combout\); + +-- Location: LABCELL_X16_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\); + +-- Location: LABCELL_X19_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000010110000000101011011010100011010101110100001111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\); + +-- Location: MLABCELL_X13_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\); + +-- Location: LABCELL_X16_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111110011000100011100110011010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\); + +-- Location: MLABCELL_X13_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011100010011010101101000101011001111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~27_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~25_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~37_combout\); + +-- Location: MLABCELL_X13_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111110000111100000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~39_combout\); + +-- Location: LABCELL_X14_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\); + +-- Location: MLABCELL_X13_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\); + +-- Location: MLABCELL_X13_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100010001000000111101110111001111000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\); + +-- Location: LABCELL_X14_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111010100110101001111110000111111110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\); + +-- Location: LABCELL_X14_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000000001011111010100111111001111110000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\); + +-- Location: LABCELL_X14_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~19_combout\); + +-- Location: LABCELL_X16_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000111010001110100110011111111110001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\); + +-- Location: MLABCELL_X13_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~19_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100001101110011011110001100100011001011111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~19_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~27_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~37_combout\); + +-- Location: MLABCELL_X13_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~37_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~37_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~37_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011100000111011101110000000000000111000000000000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~32_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~37_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~38_combout\); + +-- Location: LABCELL_X14_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~39_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~38_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~39_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~38_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~39_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~38_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~39_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~38_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001011000011100000111100000000000000010000010000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~39_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~38_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~0_combout\); + +-- Location: MLABCELL_X23_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111101010100000000000000000011111111000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~5_combout\); + +-- Location: MLABCELL_X23_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector990~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000001111111111111111111111110000000000010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~3_combout\); + +-- Location: FF_X23_Y26_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(15)); + +-- Location: FF_X20_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector344~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[14]~DUPLICATE_q\); + +-- Location: LABCELL_X2_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~12_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divResult\(14)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(14) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000010111111110000001011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~63_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~10_combout\); + +-- Location: FF_X2_Y31_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~10_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(14)); + +-- Location: LABCELL_X2_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100001111000011110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~0_combout\); + +-- Location: LABCELL_X5_Y22_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(14)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(14) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111110000111100001111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~1_combout\); + +-- Location: MLABCELL_X23_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110010001000110011001000100011000000100000001100000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~2_combout\); + +-- Location: FF_X24_Y34_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~319_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~q\); + +-- Location: LABCELL_X24_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~319\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~319_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~319_combout\); + +-- Location: FF_X24_Y34_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~319_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE_q\); + +-- Location: FF_X23_Y34_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~311_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~q\); + +-- Location: MLABCELL_X23_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~311\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~311_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~311_combout\); + +-- Location: FF_X23_Y34_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~311_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~327\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~327_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~327_combout\); + +-- Location: FF_X23_Y34_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~327_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\); + +-- Location: MLABCELL_X28_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~335\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~335_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~335_combout\); + +-- Location: FF_X28_Y34_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~335_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~q\); + +-- Location: MLABCELL_X28_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~2_combout\); + +-- Location: MLABCELL_X23_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~310\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~310_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~310_combout\); + +-- Location: FF_X23_Y34_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~310_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\); + +-- Location: FF_X23_Y34_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~326_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~q\); + +-- Location: MLABCELL_X23_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~326\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~326_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001110111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~326_combout\); + +-- Location: FF_X23_Y34_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~326_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~318\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~318_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~318_combout\); + +-- Location: FF_X24_Y34_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~318_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\); + +-- Location: LABCELL_X24_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000011110111000000001111001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~19_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\); + +-- Location: FF_X28_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~334_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~q\); + +-- Location: LABCELL_X32_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~435\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~435_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ & \myVirtualToplevel|RESET_n~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\) # (!\myVirtualToplevel|RESET_n~q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011100000111100011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~435_combout\); + +-- Location: MLABCELL_X28_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~436\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~436_combout\ = ( \myVirtualToplevel|MEM_BUSY~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~q\ ) ) # ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~q\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~435_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\)) +-- ) ) ) # ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~435_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000000000000000000010111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~435_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~436_combout\); + +-- Location: MLABCELL_X28_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~334\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~334_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~436_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~436_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~436_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000011111111111111110000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~436_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~334_combout\); + +-- Location: FF_X28_Y20_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~334_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~3_combout\); + +-- Location: MLABCELL_X23_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~323\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~323_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~323_combout\); + +-- Location: FF_X23_Y34_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~323_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\); + +-- Location: LABCELL_X25_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~331\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~331_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~331_combout\); + +-- Location: FF_X25_Y31_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~331_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\); + +-- Location: FF_X24_Y34_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~315_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\); + +-- Location: LABCELL_X24_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~315\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~315_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~315_combout\); + +-- Location: FF_X24_Y34_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~315_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~307\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~307_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~307_combout\); + +-- Location: FF_X24_Y34_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~307_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\); + +-- Location: MLABCELL_X28_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~0_combout\); + +-- Location: MLABCELL_X23_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~322\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~322_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~322_combout\); + +-- Location: FF_X23_Y34_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~322_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\); + +-- Location: FF_X24_Y34_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~314_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~q\); + +-- Location: LABCELL_X24_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~314\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~314_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~314_combout\); + +-- Location: FF_X24_Y34_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~314_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~330\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~330_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111110100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~330_combout\); + +-- Location: FF_X26_Y34_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~330_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\); + +-- Location: LABCELL_X24_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~306\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~306_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~306_combout\); + +-- Location: FF_X24_Y34_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~306_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\); + +-- Location: MLABCELL_X28_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~1_combout\); + +-- Location: MLABCELL_X28_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~2_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~2_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101001100010011110111000001110011011111000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\); + +-- Location: LABCELL_X25_Y34_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~316\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~316_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~316_combout\); + +-- Location: FF_X25_Y34_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~316_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~q\); + +-- Location: LABCELL_X25_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~312\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~312_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~312_combout\); + +-- Location: FF_X25_Y34_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~312_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\); + +-- Location: LABCELL_X25_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~313\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~313_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~313_combout\); + +-- Location: FF_X25_Y34_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~313_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~q\); + +-- Location: LABCELL_X25_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~317\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~317_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001110111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~317_combout\); + +-- Location: FF_X25_Y34_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~317_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~q\); + +-- Location: LABCELL_X26_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\); + +-- Location: FF_X26_Y34_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~320_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~q\); + +-- Location: LABCELL_X26_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~320\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~320_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~320_combout\); + +-- Location: FF_X26_Y34_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~320_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\); + +-- Location: FF_X24_Y34_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~325_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~q\); + +-- Location: LABCELL_X24_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~325\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~325_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~325_combout\); + +-- Location: FF_X24_Y34_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~325_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\); + +-- Location: FF_X26_Y34_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~321_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~q\); + +-- Location: LABCELL_X26_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~321\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~321_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~321_combout\); + +-- Location: FF_X26_Y34_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~321_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\)) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\); + +-- Location: MLABCELL_X23_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~308\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~308_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001110111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~308_combout\); + +-- Location: FF_X23_Y34_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~308_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\); + +-- Location: LABCELL_X24_Y34_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]_NEW1832\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]_OTERM1833\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]_OTERM1833\); + +-- Location: FF_X24_Y34_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]_OTERM1833\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\); + +-- Location: LABCELL_X24_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]_NEW1830\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]_OTERM1831\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]_OTERM1831\); + +-- Location: FF_X24_Y34_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]_OTERM1831\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\); + +-- Location: MLABCELL_X28_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\); + +-- Location: FF_X25_Y34_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~329_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~q\); + +-- Location: LABCELL_X25_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~329\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~329_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~329_combout\); + +-- Location: FF_X25_Y34_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~329_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~332\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~332_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~332_combout\); + +-- Location: FF_X25_Y34_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~332_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\); + +-- Location: FF_X25_Y34_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~333_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~q\); + +-- Location: LABCELL_X25_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~333\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~333_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~333_combout\); + +-- Location: FF_X25_Y34_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~333_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~328\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~328_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~328_combout\); + +-- Location: FF_X25_Y34_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~328_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\); + +-- Location: MLABCELL_X28_Y34_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001110111011101110100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\); + +-- Location: LABCELL_X29_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000100110100011001010111000010101001101111001110110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~9_combout\); + +-- Location: LABCELL_X29_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~9_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~9_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\); + +-- Location: MLABCELL_X23_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000101111100000000000000000011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~7_combout\); + +-- Location: MLABCELL_X23_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000111011100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~73_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~9_combout\); + +-- Location: LABCELL_X19_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~8_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000101010101010000010101010101000001010101010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~8_combout\); + +-- Location: MLABCELL_X18_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~41_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~41_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~41_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~41_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100101010001010100011111100000000001010100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~41_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~10_combout\); + +-- Location: MLABCELL_X18_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~43_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~43_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~43_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~43_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000101010100000000010101010000000001011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~43_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~11_combout\); + +-- Location: MLABCELL_X18_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~12_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100101010001111110010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~12_combout\); + +-- Location: MLABCELL_X23_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~9_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~12_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~9_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000101000001111000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~13_combout\); + +-- Location: FF_X25_Y34_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~328_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y34_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\); + +-- Location: MLABCELL_X23_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\); + +-- Location: MLABCELL_X23_Y34_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~q\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\); + +-- Location: FF_X25_Y34_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~332_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\); + +-- Location: LABCELL_X25_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~1_combout\); + +-- Location: MLABCELL_X23_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\); + +-- Location: MLABCELL_X23_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\); + +-- Location: LABCELL_X24_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~DUPLICATE_q\ ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\); + +-- Location: LABCELL_X24_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\); + +-- Location: LABCELL_X25_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~2_combout\); + +-- Location: MLABCELL_X23_Y34_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\); + +-- Location: LABCELL_X25_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010111111111010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][0]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\); + +-- Location: MLABCELL_X23_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\); + +-- Location: FF_X28_Y34_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~335_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\); + +-- Location: LABCELL_X25_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~3_combout\); + +-- Location: FF_X25_Y34_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~312_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\); + +-- Location: LABCELL_X24_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\); + +-- Location: FF_X25_Y34_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~317_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\); + +-- Location: FF_X25_Y34_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~316_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\); + +-- Location: LABCELL_X25_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~0_combout\); + +-- Location: LABCELL_X25_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101001000100111011110101111101011110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4_combout\); + +-- Location: MLABCELL_X23_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001101011010010110100111101101111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~4_combout\); + +-- Location: MLABCELL_X23_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~4_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010000011110000101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~5_combout\); + +-- Location: LABCELL_X14_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8709\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8709_BDD8710\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\) +-- # (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000111111111111000000110011111100000011001111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8709_BDD8710\); + +-- Location: MLABCELL_X18_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000010100000111100001010000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\); + +-- Location: MLABCELL_X13_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111000000110000001101010000010111111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\); + +-- Location: LABCELL_X19_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111010100110101001111110000111111110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\); + +-- Location: LABCELL_X17_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000000011110011001101010101111111110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\); + +-- Location: MLABCELL_X13_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000011010001001100111101110111000000110111011111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\); + +-- Location: LABCELL_X14_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~25_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~26_combout\); + +-- Location: LABCELL_X14_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8705\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8705_BDD8706\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111011111110111111101111111000110010011101100011001001110110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8705_BDD8706\); + +-- Location: LABCELL_X14_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~30_combout\); + +-- Location: MLABCELL_X13_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\); + +-- Location: LABCELL_X14_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_RESYN9111\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_RESYN9111_BDD9112\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_RESYN9111_BDD9112\); + +-- Location: LABCELL_X14_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_BDD8708\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_RESYN9111_BDD9112\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~30_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_RESYN9111_BDD9112\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~30_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~26_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100000001000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8707_RESYN9111_BDD9112\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_BDD8708\); + +-- Location: LABCELL_X14_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8711\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8711_BDD8712\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_BDD8708\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8709_BDD8710\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8705_BDD8706\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111111100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8709_BDD8710\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8705_BDD8706\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8707_BDD8708\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8711_BDD8712\); + +-- Location: MLABCELL_X23_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8711_BDD8712\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~41_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8711_BDD8712\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~41_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8711_BDD8712\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~41_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010000000000000000011111010111110101111101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~41_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8711_BDD8712\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_combout\); + +-- Location: MLABCELL_X23_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add34~41_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add34~41_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000010100000110000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~41_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~6_combout\); + +-- Location: MLABCELL_X23_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~13_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~13_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector991~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111010111110101111100011111000111110101111101011111000011110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~3_combout\); + +-- Location: FF_X23_Y22_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(14)); + +-- Location: LABCELL_X14_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8979\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8979_BDD8980\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100110101001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~49_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8979_BDD8980\); + +-- Location: LABCELL_X14_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9345\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9345_BDD9346\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\)))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000000000110000001100111010001111110000101100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9345_BDD9346\); + +-- Location: LABCELL_X14_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9349\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9349_BDD9350\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add35~37_sumout\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add35~37_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111101010101010111110101010101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~37_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9349_BDD9350\); + +-- Location: MLABCELL_X13_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9347\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9347_BDD9348\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add36~39_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~39_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000001010101010101010111010101110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~39_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9347_BDD9348\); + +-- Location: LABCELL_X14_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_BDD8984\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9347_BDD9348\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9347_BDD9348\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9349_BDD9350\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9345_BDD9346\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9347_BDD9348\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9347_BDD9348\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9349_BDD9350\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9345_BDD9346\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011101100111011111111111111111100111011111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9345_BDD9346\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9349_BDD9350\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9347_BDD9348\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_BDD8984\); + +-- Location: LABCELL_X14_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_RESYN9251\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_RESYN9251_BDD9252\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_BDD8984\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_BDD8984\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8979_BDD8980\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_BDD8984\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_BDD8984\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8979_BDD8980\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010011000000000011001100000000000000110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8979_BDD8980\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_BDD8984\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_RESYN9251_BDD9252\); + +-- Location: LABCELL_X17_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~2_combout\); + +-- Location: LABCELL_X14_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~37_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ $ +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add33~37_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add33~37_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111101100110011011110110011001101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~37_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~9_combout\); + +-- Location: LABCELL_X17_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111110000001100111111000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~35_combout\); + +-- Location: LABCELL_X14_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~35_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001000100010111100100010111111110010001000101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~10_combout\); + +-- Location: LABCELL_X17_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011111000100000001111110110000101111111011000010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\); + +-- Location: MLABCELL_X18_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010000111100110101000000000011010111111111001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\); + +-- Location: LABCELL_X16_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111001100110101010111111111000011110011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\); + +-- Location: LABCELL_X19_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110000111101010011000000000101001111111111010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\); + +-- Location: MLABCELL_X18_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101111101011111010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\); + +-- Location: LABCELL_X14_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110111010101000011011010101010001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~24_combout\); + +-- Location: LABCELL_X14_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~24_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~24_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~24_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~24_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111000000000000001100101011000000110010101100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~24_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~32_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~36_combout\); + +-- Location: LABCELL_X14_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~36_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~10_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~36_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~10_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~10_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011100100111010101010000010100100111001001110000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~11_combout\); + +-- Location: LABCELL_X14_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add34~37_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~37_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~3_combout\); + +-- Location: LABCELL_X32_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~2_combout\); + +-- Location: LABCELL_X31_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~1_combout\); + +-- Location: LABCELL_X32_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~3_combout\); + +-- Location: LABCELL_X31_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~0_combout\); + +-- Location: LABCELL_X32_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~2_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110100001000010111010101101010001111100010101101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~4_combout\); + +-- Location: LABCELL_X35_Y35_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~5_combout\); + +-- Location: LABCELL_X35_Y35_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~7_combout\); + +-- Location: LABCELL_X29_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~6_combout\); + +-- Location: LABCELL_X35_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~8_combout\); + +-- Location: LABCELL_X35_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~8_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~7_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~7_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~7_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010010011000110111000011001001110110101110101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~9_combout\); + +-- Location: LABCELL_X32_Y35_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~10_combout\); + +-- Location: LABCELL_X14_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~0_combout\); + +-- Location: FF_X2_Y30_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_NEW_REG1186\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~9_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1187\); + +-- Location: LABCELL_X2_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~6_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~6_combout\); + +-- Location: FF_X2_Y33_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_NEW_REG1188\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1189\); + +-- Location: LABCELL_X2_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1189\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1185\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1187\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1189\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1187\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1185\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[13]_OTERM1187\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[13]_OTERM1189\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~9_combout\); + +-- Location: LABCELL_X2_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(13)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divResult~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100110011001111110011001100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~0_combout\); + +-- Location: LABCELL_X5_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111001100110011001100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~1_combout\); + +-- Location: LABCELL_X14_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110000001100000010001000100010001000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~2_combout\); + +-- Location: MLABCELL_X18_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000001010000010100000011000000110000011100000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~1_combout\); + +-- Location: LABCELL_X14_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_RESYN9251_BDD9252\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~1_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_RESYN9251_BDD9252\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector992~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111011100110111011111111111111111110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~4_RESYN9251_BDD9252\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_combout\); + +-- Location: FF_X14_Y23_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(13)); + +-- Location: FF_X2_Y30_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[12]_NEW_REG1240\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~8_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[12]_OTERM1241\); + +-- Location: FF_X2_Y33_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209~DUPLICATE_q\); + +-- Location: LABCELL_X2_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1185\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[12]_OTERM1241\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[12]_OTERM1241\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1185\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[12]_OTERM1241\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1209~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~8_combout\); + +-- Location: LABCELL_X2_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divResult~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111101010101010111110101010101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~0_combout\); + +-- Location: LABCELL_X7_Y21_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000001010101010101011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~1_combout\); + +-- Location: MLABCELL_X23_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010100010001000100010100000101000001000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~2_combout\); + +-- Location: LABCELL_X19_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~35_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~35_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~35_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110000111100001100000000111111111100001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~35_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~10_combout\); + +-- Location: LABCELL_X20_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8977\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8977_BDD8978\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~10_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~10_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~10_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010110000101111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8977_BDD8978\); + +-- Location: LABCELL_X19_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100010000000000010001000000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~53_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~8_combout\); + +-- Location: MLABCELL_X23_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~33_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~33_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000110011001100000010101010101000001000100010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~9_combout\); + +-- Location: MLABCELL_X23_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8975\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8975_BDD8976\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~8_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111110101111000011110000111110111111101111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8975_BDD8976\); + +-- Location: MLABCELL_X23_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8975_BDD8976\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8975_BDD8976\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8977_BDD8978\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8975_BDD8976\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8975_BDD8976\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8977_BDD8978\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100010001000100010001000100000000000100010001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_RESYN8977_BDD8978\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_RESYN8975_BDD8976\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_combout\); + +-- Location: MLABCELL_X28_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~418\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~418_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~418_combout\); + +-- Location: FF_X28_Y30_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~418_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\); + +-- Location: LABCELL_X32_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~411\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~411_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~411_combout\); + +-- Location: FF_X32_Y29_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~411_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\); + +-- Location: MLABCELL_X28_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~419\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~419_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~419_combout\); + +-- Location: FF_X28_Y30_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~419_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\); + +-- Location: LABCELL_X31_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~410\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~410_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~410_combout\); + +-- Location: FF_X31_Y30_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~410_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\); + +-- Location: LABCELL_X31_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~6_combout\); + +-- Location: MLABCELL_X28_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~396\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~396_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~396_combout\); + +-- Location: FF_X28_Y30_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~396_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\); + +-- Location: MLABCELL_X28_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~405\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~405_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~405_combout\); + +-- Location: FF_X28_Y30_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~405_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\); + +-- Location: LABCELL_X29_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~397\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~397_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~397_combout\); + +-- Location: FF_X29_Y29_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~397_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\); + +-- Location: MLABCELL_X28_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~404\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~404_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~404_combout\); + +-- Location: FF_X28_Y30_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~404_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\); + +-- Location: LABCELL_X31_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~7_combout\); + +-- Location: MLABCELL_X28_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~413\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~413_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~413_combout\); + +-- Location: FF_X28_Y30_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~413_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\); + +-- Location: LABCELL_X31_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~421\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~421_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~421_combout\); + +-- Location: FF_X31_Y31_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~421_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\); + +-- Location: FF_X31_Y30_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~412_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\); + +-- Location: LABCELL_X31_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~412\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~412_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~412_combout\); + +-- Location: FF_X31_Y30_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~412_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~420\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~420_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~420_combout\); + +-- Location: FF_X31_Y31_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~420_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\); + +-- Location: LABCELL_X31_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~8_combout\); + +-- Location: LABCELL_X31_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~402\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~402_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~402_combout\); + +-- Location: FF_X31_Y31_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~402_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\); + +-- Location: FF_X31_Y31_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~403_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\); + +-- Location: LABCELL_X31_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~403\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~403_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~403_combout\); + +-- Location: FF_X31_Y31_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~403_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~DUPLICATE_q\); + +-- Location: MLABCELL_X34_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]_NEW1820\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]_OTERM1821\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]_OTERM1821\); + +-- Location: FF_X34_Y29_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]_OTERM1821\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\); + +-- Location: MLABCELL_X34_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]_NEW1818\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]_OTERM1819\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]_OTERM1819\); + +-- Location: FF_X34_Y29_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]_OTERM1819\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\); + +-- Location: LABCELL_X31_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~5_combout\); + +-- Location: LABCELL_X32_Y31_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~7_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011010101010000111111111111001100110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~9_combout\); + +-- Location: FF_X34_Y31_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~406_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~q\); + +-- Location: MLABCELL_X34_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~406\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~406_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~406_combout\); + +-- Location: FF_X34_Y31_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~406_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~408\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~408_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~408_combout\); + +-- Location: FF_X25_Y31_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~408_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\); + +-- Location: MLABCELL_X34_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~424\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~424_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~424_combout\); + +-- Location: FF_X34_Y31_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~424_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~q\); + +-- Location: LABCELL_X25_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~422\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~422_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~422_combout\); + +-- Location: FF_X25_Y31_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~422_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\); + +-- Location: MLABCELL_X34_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~3_combout\); + +-- Location: LABCELL_X25_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~399\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~399_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~399_combout\); + +-- Location: FF_X25_Y31_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~399_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\); + +-- Location: LABCELL_X32_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~415\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~415_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~415_combout\); + +-- Location: FF_X32_Y29_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~415_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\); + +-- Location: LABCELL_X32_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~417\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~417_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~417_combout\); + +-- Location: FF_X32_Y29_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~417_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\); + +-- Location: MLABCELL_X28_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~401\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~401_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~401_combout\); + +-- Location: FF_X28_Y30_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~401_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\); + +-- Location: LABCELL_X32_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~0_combout\); + +-- Location: MLABCELL_X34_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~423\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~423_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~423_combout\); + +-- Location: FF_X34_Y31_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~423_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\); + +-- Location: MLABCELL_X34_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~407\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~407_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~407_combout\); + +-- Location: FF_X34_Y31_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~407_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~q\); + +-- Location: MLABCELL_X28_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~409\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~409_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001110111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~409_combout\); + +-- Location: FF_X28_Y35_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~409_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\); + +-- Location: MLABCELL_X34_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~425\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~425_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~425_combout\); + +-- Location: FF_X34_Y31_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~425_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~q\); + +-- Location: MLABCELL_X34_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~2_combout\); + +-- Location: LABCELL_X32_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~398\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~398_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~398_combout\); + +-- Location: FF_X32_Y29_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~398_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\); + +-- Location: MLABCELL_X34_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~414\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~414_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~414_combout\); + +-- Location: FF_X34_Y29_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~414_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\); + +-- Location: MLABCELL_X28_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~416\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~416_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~416_combout\); + +-- Location: FF_X28_Y30_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~416_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\); + +-- Location: MLABCELL_X28_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~400\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~400_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~400_combout\); + +-- Location: FF_X28_Y30_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~400_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\); + +-- Location: MLABCELL_X34_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~1_combout\); + +-- Location: LABCELL_X31_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000100110000101010011011110001100101011101001110110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~4_combout\); + +-- Location: LABCELL_X31_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~9_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10_combout\); + +-- Location: MLABCELL_X23_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000001111111100001100111111111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~12_combout\); + +-- Location: MLABCELL_X23_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100000000111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~1_combout\); + +-- Location: LABCELL_X17_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\)))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\))))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010101000110100001111110110000101101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~22_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~34_combout\); + +-- Location: LABCELL_X14_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~34_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111110000111100000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~34_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~31_combout\); + +-- Location: LABCELL_X19_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000001010000010100000011111100111111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\); + +-- Location: LABCELL_X14_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101101010101111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~22_combout\); + +-- Location: LABCELL_X14_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~22_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~22_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~22_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~32_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~33_combout\); + +-- Location: LABCELL_X14_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~33_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~33_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~31_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~33_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~31_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110100000000110111010000000011001111000000001100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~31_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~34_combout\); + +-- Location: MLABCELL_X23_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~13_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~34_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~33_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~34_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~33_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100000000000000000011110000110000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~34_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~13_combout\); + +-- Location: MLABCELL_X23_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add34~33_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add34~33_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011101110000000001110000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~33_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~2_combout\); + +-- Location: LABCELL_X32_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\); + +-- Location: MLABCELL_X34_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\); + +-- Location: FF_X34_Y31_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~425_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE_q\); + +-- Location: FF_X34_Y31_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~424_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\); + +-- Location: MLABCELL_X34_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18_combout\); + +-- Location: LABCELL_X31_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\); + +-- Location: LABCELL_X32_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~19_combout\); + +-- Location: LABCELL_X31_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\); + +-- Location: LABCELL_X35_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\); + +-- Location: FF_X34_Y31_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~407_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE_q\); + +-- Location: MLABCELL_X34_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\); + +-- Location: LABCELL_X32_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\); + +-- Location: LABCELL_X32_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~9_combout\); + +-- Location: MLABCELL_X34_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\); + +-- Location: MLABCELL_X34_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\); + +-- Location: MLABCELL_X34_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\); + +-- Location: MLABCELL_X34_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\); + +-- Location: LABCELL_X32_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~4_combout\); + +-- Location: LABCELL_X32_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\); + +-- Location: MLABCELL_X34_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\); + +-- Location: MLABCELL_X34_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\); + +-- Location: LABCELL_X35_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\); + +-- Location: LABCELL_X32_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~14_combout\); + +-- Location: LABCELL_X32_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~14_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~19_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~14_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~19_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111010100000101000000110000001111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~19_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\); + +-- Location: LABCELL_X31_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~8_combout\); + +-- Location: LABCELL_X31_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~7_combout\); + +-- Location: LABCELL_X31_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~6_combout\); + +-- Location: LABCELL_X31_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~5_combout\); + +-- Location: LABCELL_X32_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~8_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000100111001101101000110110011100101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~9_combout\); + +-- Location: LABCELL_X35_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~3_combout\); + +-- Location: MLABCELL_X34_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~2_combout\); + +-- Location: LABCELL_X35_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~0_combout\); + +-- Location: LABCELL_X35_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~1_combout\); + +-- Location: LABCELL_X35_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~2_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~2_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011010001100101011110001010100110111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~4_combout\); + +-- Location: LABCELL_X35_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~9_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\); + +-- Location: MLABCELL_X23_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~3_combout\); + +-- Location: MLABCELL_X34_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100010001000001011011101110101111000100011010111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~0_combout\); + +-- Location: LABCELL_X32_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011010001100101011110001010100110111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~2_combout\); + +-- Location: LABCELL_X32_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101110000011100110100110001001111011111000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~1_combout\); + +-- Location: LABCELL_X32_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000001100000011111101011111010111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~3_combout\); + +-- Location: LABCELL_X31_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~2_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~2_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~2_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000101010011100000111101000100101001011110111010101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\); + +-- Location: MLABCELL_X23_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000001000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~4_combout\); + +-- Location: LABCELL_X24_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_RESYN12770\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_RESYN12770_BDD12771\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111111111100001111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_RESYN12770_BDD12771\); + +-- Location: LABCELL_X24_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_RESYN12770_BDD12771\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_RESYN12770_BDD12771\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_RESYN12770_BDD12771\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_RESYN12770_BDD12771\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110110000000000111111110000000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_RESYN12770_BDD12771\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\); + +-- Location: MLABCELL_X23_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011000000001011101100000000101110110000000010111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~6_combout\); + +-- Location: MLABCELL_X23_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~2_combout\) # +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~2_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~2_combout\) # +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111111011111110011111100111111001111110111111100111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~4_combout\); + +-- Location: FF_X23_Y21_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~4_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(12)); + +-- Location: LABCELL_X16_Y27_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~61_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011001000111110101100100011111010110010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~6_combout\); + +-- Location: LABCELL_X21_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~62\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~62_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101010000000001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~62_combout\); + +-- Location: LABCELL_X21_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~69_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~69_combout\); + +-- Location: LABCELL_X21_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~69_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~66_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~62_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~69_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~66_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~62_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~69_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~62_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~69_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~62_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010110010001100100011111010000000001100100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~62_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~66_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~69_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~7_combout\); + +-- Location: LABCELL_X21_Y27_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000101010100000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~5_combout\); + +-- Location: LABCELL_X21_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110001000111111111111111111111111100011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~8_combout\); + +-- Location: LABCELL_X21_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~8_combout\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~8_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0011001100000010001100110010001111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~8_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~11_combout\); + +-- Location: MLABCELL_X23_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~3_combout\); + +-- Location: LABCELL_X21_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~2_combout\); + +-- Location: LABCELL_X21_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001010100111111100000000000000001010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~4_combout\); + +-- Location: MLABCELL_X18_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000011001100110011000001111000011110110111101101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~9_combout\); + +-- Location: LABCELL_X19_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~61_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~61_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000111111001100110011111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~10_combout\); + +-- Location: LABCELL_X19_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add34~61_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add34~61_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110010101000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~61_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~0_combout\); + +-- Location: LABCELL_X16_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111100001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~34_combout\); + +-- Location: LABCELL_X14_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~34_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~25_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~34_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~56_combout\); + +-- Location: LABCELL_X14_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~11_combout\); + +-- Location: LABCELL_X14_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~10_combout\); + +-- Location: LABCELL_X14_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~57_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~56_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~11_combout\))))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~56_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~11_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~56_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~11_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~56_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~11_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001010100111101000100000011100000010000001110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~56_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~57_combout\); + +-- Location: LABCELL_X14_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\))))) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000010000100110000101010011011100010101001101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~39_combout\); + +-- Location: LABCELL_X14_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~59_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~39_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~39_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111110000001100111111000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~39_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~59_combout\); + +-- Location: LABCELL_X14_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~60\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~60_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~59_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~59_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~60_combout\); + +-- Location: LABCELL_X14_Y21_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~13_combout\); + +-- Location: LABCELL_X16_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101000000000101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\); + +-- Location: LABCELL_X14_Y21_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~58_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~13_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001011111111111110101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~47_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~58_combout\); + +-- Location: LABCELL_X14_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~61_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~58_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~60_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~58_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~60_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~57_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111011100000000111101110000000001010101000000000101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~57_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~60_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~58_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~61_combout\); + +-- Location: LABCELL_X20_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~61_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~61_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~61_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~61_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000000000001111000011110000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~61_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~1_combout\); + +-- Location: LABCELL_X2_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~13_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~13_combout\); + +-- Location: FF_X2_Y34_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_NEW_REG901\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~13_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\); + +-- Location: FF_X1_Y33_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_NEW_REG1230\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~8_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1231\); + +-- Location: FF_X2_Y33_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_NEW_REG1228\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~15_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1229\); + +-- Location: FF_X1_Y33_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\); + +-- Location: LABCELL_X2_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1229\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1231\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1229\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111111000000011111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM902\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[10]_OTERM1231\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[10]_OTERM1229\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~15_combout\); + +-- Location: LABCELL_X2_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~15_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100000101000001011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~0_combout\); + +-- Location: LABCELL_X5_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(10)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010111111111111111110000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~1_combout\); + +-- Location: LABCELL_X21_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100111100001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~2_combout\); + +-- Location: LABCELL_X21_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~11_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~11_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector995~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000111000001110000010100000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~3_combout\); + +-- Location: FF_X21_Y27_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(10)); + +-- Location: FF_X20_Y16_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector349~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(9)); + +-- Location: FF_X2_Y33_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[9]_NEW_REG1248\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~14_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[9]_OTERM1249\); + +-- Location: LABCELL_X2_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[9]_OTERM1249\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1189\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[9]_OTERM1249\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[9]_OTERM1249\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[9]_OTERM1249\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[9]_OTERM1249\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM902\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[13]_OTERM1189\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~14_combout\); + +-- Location: MLABCELL_X4_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~14_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~14_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000000001010101010111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~1_combout\); + +-- Location: MLABCELL_X13_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(9)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(9)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011101110111000001110000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~2_combout\); + +-- Location: LABCELL_X16_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~57_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~57_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~57_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~57_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010110010001100100011111010000000001100100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~57_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~7_combout\); + +-- Location: MLABCELL_X18_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~5_combout\); + +-- Location: MLABCELL_X18_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000000000000000011000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~6_combout\); + +-- Location: LABCELL_X19_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~55_combout\); + +-- Location: LABCELL_X17_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~64\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~64_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~64_combout\); + +-- Location: LABCELL_X17_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~61_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~64_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~55_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~61_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~55_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~64_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~55_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~55_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100111100001100000010101010100010001010000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~61_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~55_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~64_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~9_combout\); + +-- Location: LABCELL_X17_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100010001000100010001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal141~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~8_combout\); + +-- Location: LABCELL_X17_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~5_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~7_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010000001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~10_combout\); + +-- Location: LABCELL_X19_Y22_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~3_combout\); + +-- Location: LABCELL_X17_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~4_combout\); + +-- Location: LABCELL_X17_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~2_combout\) # +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~10_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~2_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110011011101110111001111111111011100110111001101110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~3_combout\); + +-- Location: LABCELL_X17_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ $ +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100111100011111010011110001111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~11_combout\); + +-- Location: LABCELL_X17_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~12_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~12_combout\); + +-- Location: LABCELL_X17_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~57_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~11_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~12_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~57_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~11_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~12_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~57_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~11_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~57_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~11_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~12_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000110000000000000010100000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~57_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~1_combout\); + +-- Location: LABCELL_X24_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~7_combout\); + +-- Location: MLABCELL_X23_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~5_combout\); + +-- Location: LABCELL_X29_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~8_combout\); + +-- Location: LABCELL_X29_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~6_combout\); + +-- Location: LABCELL_X24_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~7_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~7_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000100111001101101000110110011100101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~9_combout\); + +-- Location: LABCELL_X29_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~3_combout\); + +-- Location: LABCELL_X29_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~2_combout\); + +-- Location: LABCELL_X24_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~1_combout\); + +-- Location: LABCELL_X29_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~0_combout\); + +-- Location: LABCELL_X29_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~2_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~2_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~2_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101101110110000010100010001101011111011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~4_combout\); + +-- Location: LABCELL_X29_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~9_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10_combout\); + +-- Location: LABCELL_X17_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ +-- & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010101000001010101001010000010110101111000011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38_combout\); + +-- Location: LABCELL_X17_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111110000111100000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~38_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~53_combout\); + +-- Location: LABCELL_X16_Y21_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS~53_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~53_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~54_combout\); + +-- Location: LABCELL_X17_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~7_combout\); + +-- Location: LABCELL_X16_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~50_combout\); + +-- Location: LABCELL_X16_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\); + +-- Location: LABCELL_X16_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\)))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000111001101000011011111000100110001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~23_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~49_combout\); + +-- Location: LABCELL_X17_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~9_combout\); + +-- Location: LABCELL_X16_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~51_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~51_combout\); + +-- Location: LABCELL_X16_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~51_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~49_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~50_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~49_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100100011001000110010001100100001010000111110100101000011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~50_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~49_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~51_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~52_combout\); + +-- Location: LABCELL_X16_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~54_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~52_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~54_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~52_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57_sumout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~54_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~52_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~54_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~52_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001001111010101010101111100000000000011110101010101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~57_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~54_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~52_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~2_combout\); + +-- Location: LABCELL_X17_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~2_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101011111010111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~0_combout\); + +-- Location: LABCELL_X24_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector996~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111111111111111100001111010111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~0_combout\); + +-- Location: MLABCELL_X18_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~3_combout\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~3_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000111111111000000011111111101010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~0_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~4_combout\); + +-- Location: FF_X18_Y23_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~4_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(9)); + +-- Location: LABCELL_X17_Y24_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~73_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~73_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000100011111000111110001111100011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~73_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~1_combout\); + +-- Location: LABCELL_X17_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\)) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110110011101100000000001110110011100010111000100000000011100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~2_combout\); + +-- Location: LABCELL_X14_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111100000000101011110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\); + +-- Location: LABCELL_X17_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~70\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~70_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010100001010000011110000101000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~29_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~70_combout\); + +-- Location: MLABCELL_X18_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~71\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~71_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~70_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~70_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011100010111011101110001000100010001000100010001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~70_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~71_combout\); + +-- Location: LABCELL_X14_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000000000011010101010101011000000001010101110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~6_combout\); + +-- Location: LABCELL_X16_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101001100000011111111110101111101010011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38_combout\); + +-- Location: LABCELL_X16_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\); + +-- Location: MLABCELL_X13_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38_combout\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100000000111100111101110111011101110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~38_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~19_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~35_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~27_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~39_combout\); + +-- Location: LABCELL_X14_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~165\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~165_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~39_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~6_combout\))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\ & ( +-- ((((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~19_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000110011111111110101111111110000001100111111111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~19_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~47_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~39_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~165_combout\); + +-- Location: MLABCELL_X18_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~71_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~165_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~71_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~165_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~71_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~165_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~71_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~165_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100011111000100010001000100010001111111110001000111110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~73_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~71_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~165_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~3_combout\); + +-- Location: MLABCELL_X18_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~1_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110111011101111111111111111111011111110111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~0_combout\); + +-- Location: LABCELL_X14_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~73_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~73_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~73_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~73_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111000000000010101000101010001010100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~73_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~8_combout\); + +-- Location: MLABCELL_X18_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~7_combout\); + +-- Location: MLABCELL_X18_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110000000011000011110000001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal141~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~9_combout\); + +-- Location: LABCELL_X12_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~83\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~83_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~83_combout\); + +-- Location: LABCELL_X12_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~72\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~72_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~33_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~33_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~72_combout\); + +-- Location: LABCELL_X12_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~83_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~80_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~72_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~83_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~72_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~80_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~72_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~72_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111000000000010101000101010001010100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~83_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~72_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~80_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~10_combout\); + +-- Location: MLABCELL_X18_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~6_combout\); + +-- Location: MLABCELL_X18_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~7_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000011100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~11_combout\); + +-- Location: LABCELL_X17_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~4_combout\); + +-- Location: LABCELL_X17_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000001000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~5_combout\); + +-- Location: FF_X2_Y33_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[7]_NEW_REG1246\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~18_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[7]_OTERM1247\); + +-- Location: FF_X1_Y33_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_NEW_REG1206\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207\); + +-- Location: LABCELL_X2_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[7]_OTERM1247\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1183\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[7]_OTERM1247\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111111000000011111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1183\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[7]_OTERM1247\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~18_combout\); + +-- Location: LABCELL_X1_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~18_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~18_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000000000000001111001111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~1_combout\); + +-- Location: LABCELL_X21_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(7) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(7) & (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011001000111110101100100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~2_combout\); + +-- Location: MLABCELL_X18_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~11_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~11_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~5_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100001011000010100011101100111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~3_combout\); + +-- Location: LABCELL_X24_Y27_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector998~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111111111111100001111001111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~0_combout\); + +-- Location: MLABCELL_X18_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~3_combout\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~3_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000101010101000000010101010111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~3_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~4_combout\); + +-- Location: FF_X18_Y24_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~4_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(7)); + +-- Location: LABCELL_X26_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~22\); + +-- Location: LABCELL_X26_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~26\); + +-- Location: LABCELL_X26_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\ +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~18_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~3_combout\); + +-- Location: LABCELL_X26_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101101010101111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~2_combout\); + +-- Location: LABCELL_X26_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~30\); + +-- Location: LABCELL_X29_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111101000100011101110100010001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~0_combout\); + +-- Location: LABCELL_X29_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~1_combout\); + +-- Location: LABCELL_X26_Y36_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~3_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~3_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110101111100000011010100001111001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~4_combout\); + +-- Location: LABCELL_X20_Y24_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~0_combout\); + +-- Location: MLABCELL_X18_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~10_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~10_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100101010101000100011110000110000001010101010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~1_combout\); + +-- Location: LABCELL_X17_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~7_combout\); + +-- Location: LABCELL_X17_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~8_combout\); + +-- Location: LABCELL_X17_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~69_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~69_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000110011001100000010101010101000001000100010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~69_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~11_combout\); + +-- Location: LABCELL_X24_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~38\); + +-- Location: MLABCELL_X18_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~69_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~37_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~37_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~37_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~69_combout\); + +-- Location: MLABCELL_X18_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~78\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~78_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001111000011110000111100001111000011110000111100001111000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~78_combout\); + +-- Location: MLABCELL_X18_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~75_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~78_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~69_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~75_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~69_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~78_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~69_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~69_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011101110111011100000000011100000111000001110000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~69_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~75_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~78_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~13_combout\); + +-- Location: MLABCELL_X18_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000101010100000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~9_combout\); + +-- Location: LABCELL_X17_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010000000000000101000000000010111110000000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal141~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~12_combout\); + +-- Location: MLABCELL_X18_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~10_combout\); + +-- Location: MLABCELL_X18_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~14_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~13_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~11_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000011100000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~14_combout\); + +-- Location: FF_X1_Y30_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]_OTERM1721\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\); + +-- Location: FF_X2_Y33_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[6]_NEW_REG1242\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~17_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[6]_OTERM1243\); + +-- Location: LABCELL_X2_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[6]_OTERM1243\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1231\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[6]_OTERM1243\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111111000000011111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[10]_OTERM1231\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[6]_OTERM1243\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~17_combout\); + +-- Location: LABCELL_X1_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~17_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~17_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000000000000000000011111000111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~0_combout\); + +-- Location: MLABCELL_X13_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(6)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(6)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000101010101010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~1_combout\); + +-- Location: MLABCELL_X18_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~14_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~14_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001100111011111000100010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~2_combout\); + +-- Location: LABCELL_X24_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010011000000000001000100000000000000110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\); + +-- Location: LABCELL_X17_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~68\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~68_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000111010101100000011010101110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~68_combout\); + +-- Location: MLABCELL_X18_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~68_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~68_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~68_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~68_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000101010101010101010101010100010001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~68_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~3_combout\); + +-- Location: LABCELL_X17_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000001111000000000000000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~4_combout\); + +-- Location: LABCELL_X16_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000011000001011111001111110101000000111111010111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36_combout\); + +-- Location: MLABCELL_X13_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~34_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~34_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000111010001110111001100111111110001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~18_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~34_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~25_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~37_combout\); + +-- Location: LABCELL_X14_Y21_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001011101000011010101101010001010110111111000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~13_combout\); + +-- Location: LABCELL_X17_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\)))) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000001001000110000100110101011100010011010101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~4_combout\); + +-- Location: LABCELL_X17_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~15_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~37_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~4_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~13_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0010000001110101101011111010111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~47_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~15_combout\); + +-- Location: MLABCELL_X13_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110111011101110100001101000011011101000000001101000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~69_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~2_combout\); + +-- Location: LABCELL_X17_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~69_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~15_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~69_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011101110000000001110000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~69_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~5_combout\); + +-- Location: LABCELL_X24_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~19_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~19_combout\); + +-- Location: LABCELL_X24_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~19_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010011000100010001001100000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~19_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\); + +-- Location: MLABCELL_X18_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111010111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~6_combout\); + +-- Location: MLABCELL_X18_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~6_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector999~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111010101010101010111111111111111110001010100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~3_combout\); + +-- Location: FF_X18_Y23_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(6)); + +-- Location: LABCELL_X17_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010110010001100100011111010000000001111101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~1_combout\); + +-- Location: LABCELL_X32_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~1_combout\); + +-- Location: LABCELL_X32_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~0_combout\); + +-- Location: LABCELL_X32_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~3_combout\); + +-- Location: LABCELL_X32_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~2_combout\); + +-- Location: LABCELL_X32_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011010001010110011110001001101010111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~4_combout\); + +-- Location: LABCELL_X14_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~0_combout\); + +-- Location: LABCELL_X17_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~53_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~53_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100010101010100010011110000110000000101000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~53_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~2_combout\); + +-- Location: LABCELL_X17_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101010000000000110101111100000011010111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~2_combout\); + +-- Location: LABCELL_X17_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\)) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000100010001000100000011110011111101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~9_combout\); + +-- Location: LABCELL_X16_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000100011101110100111111001111110001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\); + +-- Location: LABCELL_X16_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100000000000111010011001100011101110011000001110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~23_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~31_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~33_combout\); + +-- Location: LABCELL_X17_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~15_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~33_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~9_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001000111010001110011111100111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~47_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~15_combout\); + +-- Location: LABCELL_X17_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111101011111010101010101111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~4_combout\); + +-- Location: LABCELL_X17_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010000000000000101010100000101010101010000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\); + +-- Location: LABCELL_X17_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111110011000000111100000000000010101000100000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~46_combout\); + +-- Location: LABCELL_X17_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~46_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~46_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~46_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~3_combout\); + +-- Location: LABCELL_X17_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~15_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~53_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~53_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111000001110000000000000000000001110000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~53_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~5_combout\); + +-- Location: LABCELL_X17_Y26_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~5_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111000001111000011100000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~6_combout\); + +-- Location: LABCELL_X17_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~10_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~10_combout\); + +-- Location: LABCELL_X17_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add36~57_sumout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010011001000000001001100100001111100111110000111110011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~57_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~12_combout\); + +-- Location: LABCELL_X17_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~53_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~53_sumout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~53_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~53_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111000000000010101000101010001010100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~53_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~11_combout\); + +-- Location: LABCELL_X17_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~9_combout\); + +-- Location: LABCELL_X17_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~41_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~48_combout\); + +-- Location: LABCELL_X16_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~48_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~48_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS~48_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100011111111100010001000111110001000100011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal141~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~13_combout\); + +-- Location: LABCELL_X17_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~14_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~11_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100010001000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~14_combout\); + +-- Location: LABCELL_X16_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~7_combout\); + +-- Location: LABCELL_X16_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000000000000010000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~8_combout\); + +-- Location: FF_X2_Y33_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[5]_NEW_REG1244\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~13_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[5]_OTERM1245\); + +-- Location: LABCELL_X2_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[5]_OTERM1245\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1189\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[5]_OTERM1245\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111111000000011111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[13]_OTERM1189\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[5]_OTERM1245\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~13_combout\); + +-- Location: LABCELL_X1_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~13_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110000000000000011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~0_combout\); + +-- Location: LABCELL_X12_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010111110100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~1_combout\); + +-- Location: LABCELL_X17_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~14_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~14_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~1_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~14_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111100010001001111110001010100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~14_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~2_combout\); + +-- Location: LABCELL_X17_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~2_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111101010101010101010001000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~3_combout\); + +-- Location: FF_X17_Y26_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(5)); + +-- Location: LABCELL_X17_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector354~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector354~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\ & ( \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\ & ( \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ ) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\ & ( !\myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000001111000011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~5_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~131_Duplicate_173\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector354~0_combout\); + +-- Location: LABCELL_X17_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector354~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector354~1_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector354~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & (((\myVirtualToplevel|MEM_DATA_READ[28]~41_combout\)))) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[12]~147_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector354~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & (\myVirtualToplevel|MEM_DATA_READ[28]~41_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101011111001100110101111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~41_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector354~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~4_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~147_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector354~1_combout\); + +-- Location: LABCELL_X16_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~7_combout\); + +-- Location: LABCELL_X16_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~7_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~8_combout\); + +-- Location: LABCELL_X16_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~9_combout\); + +-- Location: LABCELL_X16_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~82\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~82_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~82_combout\); + +-- Location: LABCELL_X16_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~82_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~82_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101001100110111011100000101000001010011011100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~82_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal141~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~13_combout\); + +-- Location: LABCELL_X16_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~10_combout\); + +-- Location: LABCELL_X16_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~85_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~85_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~85_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~85_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010111100001010000011001100100010001100000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~85_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~11_combout\); + +-- Location: LABCELL_X16_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~94_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~94_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~94_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001110100101101001011011011110110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~94_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~12_combout\); + +-- Location: LABCELL_X16_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~9_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~10_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~12_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~14_combout\); + +-- Location: LABCELL_X1_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~14_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divResult\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~8_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~21_combout\); + +-- Location: FF_X1_Y33_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~21_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(2)); + +-- Location: LABCELL_X1_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100000001000000010000111100000001000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~0_combout\); + +-- Location: LABCELL_X12_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100101010001010100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~1_combout\); + +-- Location: LABCELL_X16_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~14_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~14_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000110100000000000000001100110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~2_combout\); + +-- Location: MLABCELL_X28_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~0_combout\); + +-- Location: MLABCELL_X28_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~1_combout\); + +-- Location: MLABCELL_X28_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~2_combout\); + +-- Location: LABCELL_X31_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~3_combout\); + +-- Location: MLABCELL_X28_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~1_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~1_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011100010101001101101000110010101111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~4_combout\); + +-- Location: LABCELL_X14_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~0_combout\); + +-- Location: LABCELL_X16_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000110011001100000010101111101000001000110010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~1_combout\); + +-- Location: LABCELL_X17_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011111111000001010101010101010101111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~4_combout\); + +-- Location: LABCELL_X17_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~85_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~85_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~85_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100110011001100110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~85_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~3_combout\); + +-- Location: LABCELL_X17_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000010100000111100001010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~5_combout\); + +-- Location: LABCELL_X16_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ +-- & (((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001010000011111100101011110000110010100000000011001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~23_combout\); + +-- Location: LABCELL_X16_Y19_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~81_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~23_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111010000000001111101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~81_combout\); + +-- Location: LABCELL_X20_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010100010000001111010011101010010111100100101011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~44_combout\); + +-- Location: LABCELL_X16_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~44_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~34_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~44_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~34_combout\)) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~34_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~36_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~44_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~25_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~45_combout\); + +-- Location: LABCELL_X16_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000110010101110100101010011011100011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\); + +-- Location: LABCELL_X16_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~80\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~80_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~45_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~45_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~45_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~45_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100111111111100000011000011000000000000001100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~45_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~80_combout\); + +-- Location: LABCELL_X16_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~78\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~78_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000000000000100000000000000010001000100000001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~78_combout\); + +-- Location: LABCELL_X16_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~79\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~79_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~78_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~78_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~79_combout\); + +-- Location: LABCELL_X16_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~80_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~79_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Add33~85_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~80_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~79_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add33~85_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~80_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~79_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add33~85_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~80_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~79_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~85_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~81_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add33~85_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS~81_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110111000001010000010100110111001101110011011100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~85_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~81_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~80_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~79_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~2_combout\); + +-- Location: LABCELL_X16_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~5_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010001010101000000000000000001010101010101010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~6_combout\); + +-- Location: LABCELL_X16_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111111001111110011111100111111001101110011111100110011001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~3_combout\); + +-- Location: FF_X16_Y26_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(2)); + +-- Location: LABCELL_X19_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~85_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(2)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(2))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~94\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~86\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(2)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(2))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~94\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(2), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_155\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(2), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~94\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~86\); + +-- Location: LABCELL_X19_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~81_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(3))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(3)))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~82\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(3))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(3)))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110110001101100000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(3), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~99_Duplicate_158\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~82\); + +-- Location: FF_X18_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~1_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~81_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(3)); + +-- Location: LABCELL_X19_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~49_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(4)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(4))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~50\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(4)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(4))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(4), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~131_Duplicate_173\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~50\); + +-- Location: FF_X17_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector354~1_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~49_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(4)); + +-- Location: LABCELL_X19_Y16_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~53_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(5)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[5]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~54\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(5)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[5]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111001001110010000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(5), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~127_Duplicate_167\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~54\); + +-- Location: FF_X18_Y16_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~1_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~53_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[5]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~69_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(6)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(6))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~70\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(6)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(6))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(6), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~111_Duplicate_170\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(6), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~70\); + +-- Location: LABCELL_X19_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~73_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(7)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(7))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~74\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(7)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(7))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(7), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~107_Duplicate_164\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~74\); + +-- Location: LABCELL_X19_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~77_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(8)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(8))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~78\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(8)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(8))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(8), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~103_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~78\); + +-- Location: LABCELL_X20_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector350~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector350~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~77_sumout\ & ( ((\myVirtualToplevel|MEM_DATA_READ[8]~103_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~77_sumout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add7~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & ((\myVirtualToplevel|MEM_DATA_READ[8]~103_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add7~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000000010101010101001010101111101010101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~1_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~103_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~62_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~77_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector350~0_combout\); + +-- Location: FF_X20_Y16_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector350~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(8)); + +-- Location: LABCELL_X19_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~57_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(9)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(9))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~58\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(9)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(9))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(9), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~58\); + +-- Location: LABCELL_X19_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~61_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(10)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(10))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~62\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(10))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111011100100010000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(10), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~119_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~62\); + +-- Location: LABCELL_X19_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~65_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(11)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(11))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~66\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(11))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(11), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~115_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~66\); + +-- Location: LABCELL_X20_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector347~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector347~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~65_sumout\ & ( \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\)) # (\myVirtualToplevel|MEM_DATA_READ[11]~115_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add7~65_sumout\ & ( \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\) # (\myVirtualToplevel|MEM_DATA_READ[11]~115_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~65_sumout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[27]~59_combout\ & ( ((\myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add7~65_sumout\ & ( !\myVirtualToplevel|MEM_DATA_READ[27]~59_combout\ & ( (\myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000000011101110011001101000100110011000111011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~115_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~65_sumout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~59_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector347~0_combout\); + +-- Location: FF_X20_Y15_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector347~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(11)); + +-- Location: LABCELL_X19_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~33_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(12)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(12))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~34\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(12))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(12), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~147_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(12), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~34\); + +-- Location: LABCELL_X19_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~37_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(13)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[13]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~38\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[13]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~143_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~38\); + +-- Location: LABCELL_X19_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~41_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(14)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[14]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~42\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[14]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~139_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(14), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~42\); + +-- Location: LABCELL_X19_Y15_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~45_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(15)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~46\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~135_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~46\); + +-- Location: LABCELL_X19_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~1_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(16)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[16]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~2\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(16)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[16]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111000011000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~2\); + +-- Location: LABCELL_X19_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~21_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[17]~27_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(17)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(17))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~22\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[17]~27_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(17)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(17))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111011100010001000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~27_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~22\); + +-- Location: LABCELL_X19_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~25_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(18)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(18))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~26\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(18))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(18), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~26\); + +-- Location: LABCELL_X19_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~29_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(19)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(19))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~30\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(19))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(19), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~30\); + +-- Location: LABCELL_X19_Y14_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~13_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(20)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[20]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~14\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[20]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111000011000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[20]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~14\); + +-- Location: LABCELL_X19_Y14_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~5_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[21]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(21))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~6\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[21]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(21))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111011100010001000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~6\); + +-- Location: LABCELL_X19_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~9_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(22)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(22))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~10\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(22))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111000011000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(22), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(22), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~10\); + +-- Location: LABCELL_X19_Y14_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~17_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(23)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(23))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~18\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(23))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111000011000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(23), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(23), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~18\); + +-- Location: FF_X19_Y14_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~17_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(23)); + +-- Location: LABCELL_X19_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~109\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~109_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(24)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(24))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~110\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(24))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111001001110010000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(24), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~62_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~109_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~110\); + +-- Location: LABCELL_X19_Y14_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~105\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~105_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(25)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~110\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~106\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~110\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[25]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~53_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(25), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~110\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~105_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~106\); + +-- Location: LABCELL_X19_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~101\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~101_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(26)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(26))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~106\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~102\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(26))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~106\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(26), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~56_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(26), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~106\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~101_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~102\); + +-- Location: LABCELL_X19_Y14_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~97\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~97_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(27)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(27))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~102\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~98\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(27))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~102\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111001001110010000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(27), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~59_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~102\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~97_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~98\); + +-- Location: LABCELL_X19_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~113\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~113_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[28]~41_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(28)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(28))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~98\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~114\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[28]~41_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(28))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~98\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(28), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~41_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(28), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~98\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~113_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~114\); + +-- Location: FF_X19_Y14_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~113_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[28]~41_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(28)); + +-- Location: LABCELL_X19_Y14_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~117\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~117_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(29)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(29))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~114\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~118\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(29))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~114\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(29), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~44_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(29), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~114\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~117_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~118\); + +-- Location: LABCELL_X19_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~121\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~121_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[30]~47_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(30)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(30))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~118\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~122\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[30]~47_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(30))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~118\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111011100100010000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(30), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~47_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(30), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~118\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~121_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~122\); + +-- Location: FF_X19_Y14_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[30]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~121_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[30]~47_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[30]~DUPLICATE_q\); + +-- Location: LABCELL_X21_Y17_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[30]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(30)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[30]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(30)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[30]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\); + +-- Location: FF_X23_Y18_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[30]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(30)); + +-- Location: MLABCELL_X23_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[30]~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[30]~47_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~47_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[30]~feeder_combout\); + +-- Location: FF_X23_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[30]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(30)); + +-- Location: MLABCELL_X23_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(30) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(30)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(30) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(30) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(30), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\); + +-- Location: LABCELL_X17_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011010000100000001101010110000101110101011000010111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\); + +-- Location: LABCELL_X16_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~75\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\); + +-- Location: LABCELL_X14_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~130\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~130_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~75_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~130_combout\); + +-- Location: LABCELL_X14_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8679\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8679_BDD8680\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~130_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~130_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~130_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~130_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~130_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111111111111001111111101010001111111000000000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~130_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8679_BDD8680\); + +-- Location: LABCELL_X14_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8681\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8681_BDD8682\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~117_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~128_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~117_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~128_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000111111111111000010101010101000001010101010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~128_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~117_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8681_BDD8682\); + +-- Location: LABCELL_X14_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~134\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8679_BDD8680\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8681_BDD8682\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8677_BDD8678\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8677_BDD8678\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8679_BDD8680\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8681_BDD8682\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001000110010001100100011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8677_BDD8678\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8679_BDD8680\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8681_BDD8682\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_combout\); + +-- Location: LABCELL_X1_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~7_combout\); + +-- Location: FF_X1_Y33_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_NEW_REG899\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~7_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM900\); + +-- Location: FF_X2_Y34_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[29]_NEW_REG969\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~29_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[29]_OTERM970\); + +-- Location: LABCELL_X2_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[29]_OTERM970\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[29]_OTERM970\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM900\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM792\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult[29]_OTERM970\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM900\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM792\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[29]_OTERM970\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM790\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~29_combout\); + +-- Location: LABCELL_X7_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~135\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~135_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~727_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~727_sumout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~727_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~29_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~727_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101001001110010011110101111101011110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~727_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~135_combout\); + +-- Location: MLABCELL_X13_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~157\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~157_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~135_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~135_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001111110011001100111100000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~135_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~157_combout\); + +-- Location: MLABCELL_X13_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~136\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~136_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~156_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~157_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add34~117_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~156_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~157_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~156_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~157_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~156_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~157_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000011110000111111110000111111110000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~117_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~156_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~157_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~136_combout\); + +-- Location: FF_X13_Y24_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~136_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(29)); + +-- Location: FF_X19_Y14_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~117_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(29)); + +-- Location: LABCELL_X17_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(29)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(29) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(29)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\); + +-- Location: FF_X18_Y17_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(29)); + +-- Location: MLABCELL_X18_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(29) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(29) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\); + +-- Location: LABCELL_X14_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101000000000000111100110101001101011111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\); + +-- Location: LABCELL_X17_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8667\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8667_BDD8668\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110010101000111111001111110000000000010101000000000001010100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~75_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8667_BDD8668\); + +-- Location: MLABCELL_X13_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111010101010011001111111111000011110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46_combout\); + +-- Location: LABCELL_X17_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~112\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~112_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~112_combout\); + +-- Location: LABCELL_X14_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~113\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~113_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~112_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~112_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~112_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~34_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~112_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~34_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~21_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~34_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~46_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~112_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~113_combout\); + +-- Location: LABCELL_X19_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~116\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~113_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8667_BDD8668\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~113_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8667_BDD8668\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~113_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8669_BDD8670\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8667_BDD8668\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~113_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8669_BDD8670\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8667_BDD8668\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100010101010101010001000111111111001111111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_RESYN8669_BDD8670\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_RESYN8667_BDD8668\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~17_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~113_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_combout\); + +-- Location: LABCELL_X19_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~121\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~121_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Add36~124_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add36~124_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~124_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~121_combout\); + +-- Location: LABCELL_X19_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9263\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9263_BDD9264\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~121_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~113_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~121_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~113_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add33~113_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~121_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~113_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~121_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~113_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add33~113_sumout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110101111111111111111111110011111101111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~113_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~121_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~113_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9263_BDD9264\); + +-- Location: LABCELL_X19_Y24_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9267\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9267_BDD9268\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9263_BDD9264\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9263_BDD9264\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010101010101000001010101010111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9263_BDD9264\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9267_BDD9268\); + +-- Location: FF_X2_Y34_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_NEW_REG797\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~28_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM798\); + +-- Location: LABCELL_X2_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM798\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM798\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM800\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM792\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM798\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[28]_OTERM800\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM792\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[28]_OTERM798\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM790\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~28_combout\); + +-- Location: LABCELL_X7_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~122\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~122_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~723_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~28_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~723_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~28_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~723_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~28_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28) & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~723_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28) & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000111110001111111010000110100001101111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~723_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~122_combout\); + +-- Location: LABCELL_X19_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9269\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9269_BDD9270\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~122_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9263_BDD9264\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~122_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~122_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9263_BDD9264\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~122_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000100110001001111111111111111111101111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9263_BDD9264\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~122_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9269_BDD9270\); + +-- Location: LABCELL_X19_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~123\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9267_BDD9268\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9269_BDD9270\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9267_BDD9268\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9269_BDD9270\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~120_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9267_BDD9268\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9269_BDD9270\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ +-- & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~120_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\)))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9267_BDD9268\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9269_BDD9270\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~120_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111010001100000011101000111111001110100011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~120_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9267_BDD9268\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9269_BDD9270\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_combout\); + +-- Location: FF_X19_Y24_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(28)); + +-- Location: LABCELL_X21_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(28) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(28) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\); + +-- Location: FF_X18_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~DUPLICATE_q\); + +-- Location: FF_X18_Y17_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[28]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[28]~41_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[28]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[28]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[28]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[28]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\); + +-- Location: LABCELL_X2_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[58]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[59]~feeder_combout\); + +-- Location: LABCELL_X2_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110101111101000000000000000001111101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy~0_combout\); + +-- Location: FF_X2_Y29_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy~0_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(60)); + +-- Location: FF_X2_Y25_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[59]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(60), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(59)); + +-- Location: FF_X2_Y25_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[58]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(59), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(58)); + +-- Location: LABCELL_X1_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ = SUM(( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~107\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~106\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~106\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~107\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\); + +-- Location: LABCELL_X2_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[58]_NEW1684\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[58]_OTERM1685\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(58) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000100010001000100010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[58]_OTERM1685\); + +-- Location: FF_X2_Y29_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[58]_OTERM1685\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(58)); + +-- Location: LABCELL_X1_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[57]~feeder_combout\); + +-- Location: FF_X1_Y28_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[57]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(58), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(57)); + +-- Location: LABCELL_X2_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[57]_NEW1682\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[57]_OTERM1683\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(57) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000100010001000100010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[57]_OTERM1683\); + +-- Location: FF_X2_Y29_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[57]_OTERM1683\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(57)); + +-- Location: LABCELL_X2_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(57) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(58) & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(58)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(58) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(58) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(57))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(58) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(58)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(57)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010011011101010001001101110101000100010001000100010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(58), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(58), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~1_combout\); + +-- Location: LABCELL_X2_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[59]_NEW1686\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[59]_OTERM1687\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(59) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000100010001000100010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[59]_OTERM1687\); + +-- Location: FF_X2_Y29_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[59]_OTERM1687\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(59)); + +-- Location: LABCELL_X2_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[60]_NEW1688\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[60]_OTERM1689\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(60) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000100010001000100010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[60]_OTERM1689\); + +-- Location: FF_X2_Y29_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[60]_OTERM1689\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(60)); + +-- Location: LABCELL_X2_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[61]_NEW1690\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[61]_OTERM1691\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(61) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000100010001000100010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[61]_OTERM1691\); + +-- Location: FF_X2_Y29_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[61]_OTERM1691\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(61)); + +-- Location: LABCELL_X2_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(60) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(61) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(60) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(59) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(59)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(60) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(61) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(60) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(59) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(59)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000001010000010010000010100000100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(60), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(59), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(59), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~0_combout\); + +-- Location: LABCELL_X2_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(60) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(59) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(59) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(60))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(60) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(61) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(59) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(59))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(60)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101011111111000000000000101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(59), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(59), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(60), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~0_combout\); + +-- Location: LABCELL_X2_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001110111000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\); + +-- Location: LABCELL_X1_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000101000000000000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~63_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~14_combout\); + +-- Location: LABCELL_X1_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~14_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divResult\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~20_combout\); + +-- Location: FF_X1_Y33_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~20_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(3)); + +-- Location: LABCELL_X2_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(3))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult\(3)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110111000001010011011100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~0_combout\); + +-- Location: LABCELL_X12_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010111100001010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~1_combout\); + +-- Location: LABCELL_X16_Y27_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~7_combout\); + +-- Location: LABCELL_X16_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~8_combout\); + +-- Location: LABCELL_X19_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011000000000011001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~10_combout\); + +-- Location: LABCELL_X19_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~9_combout\); + +-- Location: LABCELL_X19_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~77_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~77_combout\); + +-- Location: LABCELL_X19_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~92\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~92_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000000011110000111111110000111100000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~92_combout\); + +-- Location: LABCELL_X19_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~89_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~92_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~77_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~89_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~77_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~92_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~77_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~77_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011101110111011100000000011100000111000001110000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~77_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~89_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~92_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~13_combout\); + +-- Location: MLABCELL_X18_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~81_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~81_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~81_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~81_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010110010001100100011111010000000001100100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~81_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~11_combout\); + +-- Location: LABCELL_X17_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000000000000011000000000011001100110000001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal141~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~12_combout\); + +-- Location: LABCELL_X19_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~13_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~12_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~13_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001000000000001000100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~14_combout\); + +-- Location: LABCELL_X19_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~14_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~14_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~14_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010001010100000000000000000001010100010101000101000001010100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~2_combout\); + +-- Location: MLABCELL_X28_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~0_combout\); + +-- Location: MLABCELL_X28_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~2_combout\); + +-- Location: LABCELL_X29_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~18_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~3_combout\); + +-- Location: LABCELL_X29_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010010111110101111100100010011101110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~1_combout\); + +-- Location: LABCELL_X29_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~2_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000000001001110101010100100111101010100010011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~4_combout\); + +-- Location: LABCELL_X20_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000010000000100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~0_combout\); + +-- Location: LABCELL_X20_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111111110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\); + +-- Location: LABCELL_X20_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~81_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111110001010110011111000101011001111100010100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~4_combout\); + +-- Location: LABCELL_X17_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~3_combout\); + +-- Location: LABCELL_X16_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~76\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~76_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100001111000011110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~75_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~76_combout\); + +-- Location: MLABCELL_X18_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~76_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101111111100000000000000001010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~76_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~2_combout\); + +-- Location: LABCELL_X16_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001101110111011101100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~42_combout\); + +-- Location: LABCELL_X16_Y18_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~42_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~42_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~42_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~42_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010010001101100111000010011100110110101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~35_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~42_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~38_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~27_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~43_combout\); + +-- Location: MLABCELL_X13_Y21_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\)))) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001000110100010101100111000010011010101111001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~20_combout\); + +-- Location: MLABCELL_X13_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\))) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000100110100011001010111000010101001101111001110110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~15_combout\); + +-- Location: LABCELL_X16_Y21_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~15_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~43_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~15_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~20_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0010000001110101101011111010111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~43_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~47_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~15_combout\); + +-- Location: LABCELL_X19_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~81_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~81_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~81_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111000000000000011100000000000001110000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~81_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~5_combout\); + +-- Location: LABCELL_X19_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~5_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011101111111011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~6_combout\); + +-- Location: LABCELL_X19_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111101010101111111110101010111111111000100001111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~3_combout\); + +-- Location: FF_X19_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(3)); + +-- Location: LABCELL_X16_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(3) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(2))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(3) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110010001000100111001000100010010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\); + +-- Location: LABCELL_X16_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\); + +-- Location: MLABCELL_X13_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~16_combout\); + +-- Location: MLABCELL_X13_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101010111010101110101011101010111010000000001011101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~5_combout\); + +-- Location: MLABCELL_X13_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001110000000001000111110011000100011111001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~27_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40_combout\); + +-- Location: MLABCELL_X13_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000011000000110000010001110111010011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\); + +-- Location: LABCELL_X14_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111001100110000000001010101000011110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\); + +-- Location: LABCELL_X16_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011000011110000000001010101001100110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\); + +-- Location: MLABCELL_X13_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100110001110000011111000100001101001111011100110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~25_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~24_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~42_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~43_combout\); + +-- Location: MLABCELL_X13_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~43_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~43_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~43_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000010100000000000000101000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~40_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~43_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~4_combout\); + +-- Location: MLABCELL_X13_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101011111010111110101100101011001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~3_combout\); + +-- Location: MLABCELL_X13_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~6_combout\); + +-- Location: MLABCELL_X13_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000000000000000000010101010101000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~8_combout\); + +-- Location: LABCELL_X1_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~11_combout\); + +-- Location: LABCELL_X1_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult\(27) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~63_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~24_combout\); + +-- Location: FF_X1_Y33_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~24_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(27)); + +-- Location: MLABCELL_X4_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111101010101010101010101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~1_combout\); + +-- Location: LABCELL_X16_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010101000101010001010100010101000101010001010100010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~0_combout\); + +-- Location: LABCELL_X16_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~707_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~707_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100110011111100000011000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~707_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~2_combout\); + +-- Location: LABCELL_X17_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8649\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8649_BDD8650\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011111111111011101111111111100000111111111110000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8649_BDD8650\); + +-- Location: MLABCELL_X18_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8651\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8651_BDD8652\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8651_BDD8652\); + +-- Location: MLABCELL_X18_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8647\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8647_BDD8648\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~108_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~108_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~108_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~108_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100001111111111111111000010101010000010101010101010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~108_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8647_BDD8648\); + +-- Location: LABCELL_X17_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8647_BDD8648\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8649_BDD8650\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8647_BDD8648\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8649_BDD8650\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8651_BDD8652\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000001000101010101000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8649_BDD8650\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8651_BDD8652\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8647_BDD8648\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_combout\); + +-- Location: LABCELL_X16_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~97_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add33~97_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~97_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add33~97_sumout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~97_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~97_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000110001000100010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~97_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~97_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\); + +-- Location: LABCELL_X16_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8997\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8997_BDD8998\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~8_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000001010000010111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8995_BDD8996\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8997_BDD8998\); + +-- Location: LABCELL_X16_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8999\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8999_BDD9000\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\ ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8995_BDD8996\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8999_BDD9000\); + +-- Location: LABCELL_X16_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8997_BDD8998\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8999_BDD9000\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~2_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8997_BDD8998\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8999_BDD9000\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8997_BDD8998\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8999_BDD9000\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8997_BDD8998\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8999_BDD9000\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000101111111110000110111111111000001011111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8997_BDD8998\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8999_BDD9000\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_combout\); + +-- Location: FF_X16_Y28_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(27)); + +-- Location: FF_X19_Y14_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~97_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(27)); + +-- Location: LABCELL_X17_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(27)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(27) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(27)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\); + +-- Location: LABCELL_X12_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[27]_NEW2951\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[27]_OTERM2952\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(27) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[27]_OTERM2952\); + +-- Location: FF_X12_Y20_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[27]_OTERM2952\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(27)); + +-- Location: LABCELL_X12_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[27]_NEW3015\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[27]_OTERM3016\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(27))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(27))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[27]_OTERM3016\); + +-- Location: FF_X12_Y23_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[27]_OTERM3016\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(27)); + +-- Location: LABCELL_X12_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[27]_NEW3143\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[27]_OTERM3144\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(27) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[27]_OTERM3144\); + +-- Location: FF_X12_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[27]_OTERM3144\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(27)); + +-- Location: LABCELL_X12_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[27]_NEW3079\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[27]_OTERM3080\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(27) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[27]_OTERM3080\); + +-- Location: FF_X12_Y20_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[27]_OTERM3080\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(27)); + +-- Location: LABCELL_X12_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux15~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(27)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(27) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(27))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(27) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(27))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(27), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(27), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~0_combout\); + +-- Location: LABCELL_X12_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[27]_NEW2887\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[27]_OTERM2888\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(27) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[27]_OTERM2888\); + +-- Location: FF_X12_Y20_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[27]_OTERM2888\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(27)); + +-- Location: MLABCELL_X9_Y22_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[27]_NEW2823\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[27]_OTERM2824\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(27))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(27))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[27]_OTERM2824\); + +-- Location: FF_X9_Y22_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[27]_OTERM2824\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(27)); + +-- Location: LABCELL_X12_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[27]_NEW2695\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[27]_OTERM2696\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(27) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[27]_OTERM2696\); + +-- Location: FF_X12_Y20_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[27]_OTERM2696\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(27)); + +-- Location: MLABCELL_X9_Y22_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[27]_NEW2759\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[27]_OTERM2760\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(27))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(27))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[27]_OTERM2760\); + +-- Location: FF_X9_Y22_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[27]_OTERM2760\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(27)); + +-- Location: LABCELL_X12_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux15~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(27)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(27) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(27)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(27))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(27)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(27), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~1_combout\); + +-- Location: LABCELL_X12_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux15~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux15~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux15~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux15~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~2_combout\); + +-- Location: LABCELL_X10_Y14_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[27]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[27]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux15~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101001101110000010100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[27]~23_combout\); + +-- Location: FF_X10_Y14_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[27]~23_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27)); + +-- Location: FF_X17_Y10_N23 +\myVirtualToplevel|MILLISEC_UP_COUNTER[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~117_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(27)); + +-- Location: LABCELL_X17_Y10_N24 +\myVirtualToplevel|Add17~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~93_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(28) ) + ( GND ) + ( \myVirtualToplevel|Add17~118\ )) +-- \myVirtualToplevel|Add17~94\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(28) ) + ( GND ) + ( \myVirtualToplevel|Add17~118\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(28), + cin => \myVirtualToplevel|Add17~118\, + sumout => \myVirtualToplevel|Add17~93_sumout\, + cout => \myVirtualToplevel|Add17~94\); + +-- Location: FF_X17_Y10_N26 +\myVirtualToplevel|MILLISEC_UP_COUNTER[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~93_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(28)); + +-- Location: LABCELL_X17_Y10_N27 +\myVirtualToplevel|Add17~97\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~97_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(29) ) + ( GND ) + ( \myVirtualToplevel|Add17~94\ )) +-- \myVirtualToplevel|Add17~98\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(29) ) + ( GND ) + ( \myVirtualToplevel|Add17~94\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(29), + cin => \myVirtualToplevel|Add17~94\, + sumout => \myVirtualToplevel|Add17~97_sumout\, + cout => \myVirtualToplevel|Add17~98\); + +-- Location: LABCELL_X10_Y14_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[29]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[29]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(29)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(29))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux13~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101100000001111111110000000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[29]~12_combout\); + +-- Location: FF_X10_Y14_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[29]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(29)); + +-- Location: FF_X17_Y10_N28 +\myVirtualToplevel|MILLISEC_UP_COUNTER[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~97_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(29), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(29)); + +-- Location: LABCELL_X17_Y10_N30 +\myVirtualToplevel|Add17~101\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~101_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(30) ) + ( GND ) + ( \myVirtualToplevel|Add17~98\ )) +-- \myVirtualToplevel|Add17~102\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(30) ) + ( GND ) + ( \myVirtualToplevel|Add17~98\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(30), + cin => \myVirtualToplevel|Add17~98\, + sumout => \myVirtualToplevel|Add17~101_sumout\, + cout => \myVirtualToplevel|Add17~102\); + +-- Location: LABCELL_X10_Y14_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[30]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[30]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux12~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux12~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100010001000111110001000100011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[30]~13_combout\); + +-- Location: FF_X10_Y14_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[30]~13_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30)); + +-- Location: FF_X17_Y10_N32 +\myVirtualToplevel|MILLISEC_UP_COUNTER[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~101_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(30)); + +-- Location: LABCELL_X17_Y10_N33 +\myVirtualToplevel|Add17~105\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add17~105_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(31) ) + ( GND ) + ( \myVirtualToplevel|Add17~102\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(31), + cin => \myVirtualToplevel|Add17~102\, + sumout => \myVirtualToplevel|Add17~105_sumout\); + +-- Location: LABCELL_X10_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110011000000001111001100000101111101110000010111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~14_combout\); + +-- Location: FF_X10_Y14_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~14_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31)); + +-- Location: FF_X17_Y10_N35 +\myVirtualToplevel|MILLISEC_UP_COUNTER[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~105_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(31)); + +-- Location: LABCELL_X17_Y10_N45 +\myVirtualToplevel|IO_DATA_READ~82\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~82_combout\ = ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(31) & ( \myVirtualToplevel|IO_DATA_READ[26]~78_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[26]~78_combout\, + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(31), + combout => \myVirtualToplevel|IO_DATA_READ~82_combout\); + +-- Location: FF_X17_Y10_N46 +\myVirtualToplevel|IO_DATA_READ[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~82_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(31)); + +-- Location: LABCELL_X24_Y9_N33 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector0~0_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(15))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001110001011000000111000101100000011100010110000001110001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector3~1_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(7), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(15), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector0~0_combout\); + +-- Location: FF_X24_Y9_N34 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector0~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(15)); + +-- Location: MLABCELL_X18_Y9_N33 +\myVirtualToplevel|IO_DATA_READ_SD[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[31]~feeder_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(15), + combout => \myVirtualToplevel|IO_DATA_READ_SD[31]~feeder_combout\); + +-- Location: FF_X18_Y9_N10 +\myVirtualToplevel|SD_ADDR[0][31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31), + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][31]~q\); + +-- Location: FF_X18_Y9_N34 +\myVirtualToplevel|IO_DATA_READ_SD[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[31]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][31]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(31)); + +-- Location: FF_X21_Y12_N32 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux86~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(31)); + +-- Location: LABCELL_X21_Y12_N30 +\myVirtualToplevel|MEM_DATA_READ[31]~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[31]~48_combout\ = ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(31) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((!\myVirtualToplevel|INTR0_CS~combout\))) # +-- (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ\(31))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(31) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & +-- ((!\myVirtualToplevel|INTR0_CS~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ\(31))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(31) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) # (\myVirtualToplevel|IO_DATA_READ_SD\(31)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(31) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (\myVirtualToplevel|IO_DATA_READ_SD\(31) & +-- \myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111110011001111110000010101011111000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(31), + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(31), + datac => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(31), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[31]~48_combout\); + +-- Location: FF_X19_Y11_N26 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_NEW_REG78\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~29_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM79\); + +-- Location: IOIBUF_X24_Y0_N35 +\SDRAM_DQ[15]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(15), + o => \SDRAM_DQ[15]~input_o\); + +-- Location: DDIOINCELL_X24_Y0_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_NEW_REG80\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[15]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM81\); + +-- Location: LABCELL_X19_Y11_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~29_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM79\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM81\))) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM79\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]_OTERM79\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]_OTERM81\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~29_combout\); + +-- Location: LABCELL_X17_Y9_N9 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[7]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[7]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100100111000001010010011110001101101011111000110110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(31), + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[7]~3_combout\); + +-- Location: M10K_X3_Y5_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001FFFFFD6600010000000000000000000000000000000000000000000000000000000E5FFDEC65216F5880E821044FAD29BF16CF0E5FFFC7E05FE", + mem_init2 => "BE34719C5F1AFF7B94F4172F72000EE472F79CA7A09CBD8120317C6BFC68BE07F03FE0E466EF1D275FD9FDFF2F6199EFF1DE7738913161C78077DE87060C0C21721D890FE1CBF603F0E5FB01FA1FE095B10B425D67025C603D0DB4BD8A30F88F88C328C924E7CF844C4008441319D0B0B71C8856089D64A717F0B07CFBD9B85ED9F11D7E459E20838000008602E64C82E6544B604F45362CF41DE81B880C01B0E0E72A083D4443764D757FBD219006673C72CE20CE17F8D48028648E4B0F808823220394402FF2999D9300FFA438F420F02191FCD69E1F47551DB9F17C47DF9085406BE22E136870F1217845008E0F140AC050BD199271D31E5EA0F8060B5393", + mem_init1 => "E45317B7064C710BDC42E60A229240D62912B4325745CD1EDE2C89398472511C78F9DE654824A44B821E61004046027994921088B61308206C19133013C684CAA948A3A9BC85106590FE05C9C4741B904BE0F59F9F0A4068B04822A2AB3B8F59E8261409C08881E685FDE3F74B8813AAE01395EEC1397D2F85C43E041FC909413005020A84030142C21B0C88916482780EB2F2A0A26167528292419454EB191B18A8A203EDC605E25888692081830FE3F110C9F00E3058A5F122B80776705F85057C00E21E784242458543A15F38A314761182B4703CB230501921F403EA2243A811BDAFB400C40EAAC4078511BDEEA7838FC408E3103E060073000884353188", + mem_init0 => "31285259A95884872054F988AC4A4398108F310986252A2BE257006A73411702000AB3253E61907B350900B2011C0045020876078184063FA878946677270018543B0839AC846412F0E4C0AB2421978F73F07F249A3F8D3FA7DFBF7EFDFFFD2F186F1E12B1BBC256377848FF9CFE7F3FA78A548F70B934A2AA2801B8102EC539054923905A52955DB5558924961D8888CC827785C450A00C209061E02A81EEF951BF04F33D55F07CC152E0A2CACF97982A5FD841F9C10800FFFC3FFFFFFFFFFFFFFFFFFFFFFFFFFF87FF0FFE1FFC3FF8FFFFFFFFFFFA492492492492492492FEF800000000000000041B1B2414000000040428080000020000000000861C0B02", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 7, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 7, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\); + +-- Location: M10K_X3_Y6_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 7, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 7, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X20_Y12_N6 +\myVirtualToplevel|MEM_DATA_READ[31]~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[31]~49_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15~portbdataout\ & ( (\myVirtualToplevel|LessThan0~1_combout\ & +-- ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7~portbdataout\) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0)))) ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15~portbdataout\ & ( (\myVirtualToplevel|LessThan0~1_combout\ & (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0) & +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7~portbdataout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100000000000100010000010001010101010001000101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[31]~49_combout\); + +-- Location: LABCELL_X20_Y12_N18 +\myVirtualToplevel|MEM_DATA_READ[31]~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[31]~49_combout\ ) # ( !\myVirtualToplevel|MEM_DATA_READ[31]~49_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & +-- (\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~29_combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & (((\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~29_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[31]~48_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110111000001010011011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~48_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~29_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~49_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\); + +-- Location: LABCELL_X14_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~5_combout\); + +-- Location: LABCELL_X14_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000011110000111100001111000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~6_combout\); + +-- Location: LABCELL_X14_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001010101000001010000010100000101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~8_combout\); + +-- Location: LABCELL_X14_Y22_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000000000001111000011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~7_combout\); + +-- Location: LABCELL_X14_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~7_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~6_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~7_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000010000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~9_combout\); + +-- Location: LABCELL_X19_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~136\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~136_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) +-- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~133\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000111100001111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~133\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~136_sumout\); + +-- Location: MLABCELL_X13_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1_combout\); + +-- Location: LABCELL_X14_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~136_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~5_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~136_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~5_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~136_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~136_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~9_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001000100000000000111111000000000010101000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~136_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~10_combout\); + +-- Location: MLABCELL_X18_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~125\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~125_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~123\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~122\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~122\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~123\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~125_sumout\); + +-- Location: LABCELL_X14_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100010001101011110001000100000101101110111010111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~48_combout\); + +-- Location: MLABCELL_X13_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\)))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~48_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010101000110100001111110110000101101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~24_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~42_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~48_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~49_combout\); + +-- Location: MLABCELL_X13_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~49_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~37_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~49_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~49_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~37_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111110101010101010100000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~37_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~49_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~2_combout\); + +-- Location: MLABCELL_X13_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~12_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~2_combout\)))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000000000000000000000000000000000001101110101010100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~12_combout\); + +-- Location: MLABCELL_X18_Y17_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111111110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\); + +-- Location: LABCELL_X19_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add33~125\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~125_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~122\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~122\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~125_sumout\); + +-- Location: LABCELL_X14_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~125_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~125_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~125_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~125_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010111110100000000011001000110010001100100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~125_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~11_combout\); + +-- Location: LABCELL_X14_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add34~125_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111010110010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~125_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~3_combout\); + +-- Location: LABCELL_X14_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~4_combout\); + +-- Location: LABCELL_X7_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~735\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~735_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM195\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM167\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~732\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM167\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM195\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~732\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~735_sumout\); + +-- Location: LABCELL_X5_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9033\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9033_BDD9034\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~735_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~735_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~735_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~735_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100101010001010100011111111111111111010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~735_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9033_BDD9034\); + +-- Location: LABCELL_X2_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]_NEW1706\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]_OTERM1707\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(31))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011110010000000101111001000000010111100100000001011110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]_OTERM1707\); + +-- Location: FF_X2_Y26_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]_OTERM1707\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(31)); + +-- Location: LABCELL_X2_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~11_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000010000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~31_combout\); + +-- Location: FF_X2_Y31_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_NEW_REG522\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~31_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM523\); + +-- Location: LABCELL_X19_Y14_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_67\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_68\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(31) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(31)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(31)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_68\); + +-- Location: FF_X19_Y14_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_NEW_REG516\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_68\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM517\); + +-- Location: FF_X18_Y17_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_63\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_64\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[31]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[31]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_64\); + +-- Location: FF_X18_Y17_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_NEW_REG514\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_64\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM515\); + +-- Location: FF_X2_Y24_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_NEW_REG520\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~32_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM521\); + +-- Location: FF_X2_Y24_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_NEW_REG518\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM519\); + +-- Location: LABCELL_X2_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM521\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM519\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM517\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM515\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM523\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM521\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM519\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM517\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM515\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM523\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM521\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM519\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM521\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM519\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM523\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101111111111111111101111101011111010111110101111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM523\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM517\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM515\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM521\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM519\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~32_combout\); + +-- Location: LABCELL_X2_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9031\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9031_BDD9032\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~32_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(31)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~32_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~32_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(31)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011101110111111111111111111100000111000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(31), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9031_BDD9032\); + +-- Location: LABCELL_X14_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9031_BDD9032\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9033_BDD9034\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9031_BDD9032\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9033_BDD9034\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001100000011000000111000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_RESYN9033_BDD9034\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_RESYN9031_BDD9032\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_combout\); + +-- Location: LABCELL_X14_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~3_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111101010001010100000101000101010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~3_combout\); + +-- Location: FF_X14_Y22_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(31)); + +-- Location: LABCELL_X19_Y14_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add7~125\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~125_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(31)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(31))) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~122\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110100101000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(31), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~50_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(31), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~122\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~125_sumout\); + +-- Location: FF_X19_Y14_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~125_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(31)); + +-- Location: LABCELL_X19_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(31)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(31) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(31)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\); + +-- Location: FF_X18_Y17_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~DUPLICATE_q\); + +-- Location: FF_X18_Y17_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(31)); + +-- Location: MLABCELL_X18_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(31) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[31]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\); + +-- Location: LABCELL_X17_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\); + +-- Location: MLABCELL_X13_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_RESYN12772\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_RESYN12772_BDD12773\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000001010000111100000101000011110001010000001111000101000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_RESYN12772_BDD12773\); + +-- Location: MLABCELL_X13_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_RESYN12772_BDD12773\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_RESYN12772_BDD12773\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110111111101111111011111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~10_RESYN12772_BDD12773\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_combout\); + +-- Location: MLABCELL_X13_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_RESYN12802\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_RESYN12802_BDD12803\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_RESYN12802_BDD12803\); + +-- Location: MLABCELL_X13_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_RESYN12802_BDD12803\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_RESYN12802_BDD12803\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000000000000000000010101000101000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~23_RESYN12802_BDD12803\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_combout\); + +-- Location: MLABCELL_X13_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009_BDD9010\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009_BDD9010\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009_BDD9010\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009_BDD9010\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000000000110011000000000011001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~22_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_RESYN9009_BDD9010\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~23_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\); + +-- Location: LABCELL_X31_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_RESYN9011\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_RESYN9011_BDD9012\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_RESYN9011_BDD9012\); + +-- Location: LABCELL_X29_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_RESYN9011_BDD9012\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_RESYN9011_BDD9012\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000100000001000000000000000000011001100000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~14_RESYN9011_BDD9012\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_combout\); + +-- Location: LABCELL_X24_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~94\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~94\); + +-- Location: LABCELL_X24_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~94\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~90\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~94\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~94\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~90\); + +-- Location: LABCELL_X24_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~90\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~30\); + +-- Location: LABCELL_X24_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000110000111111000111010001110100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~93_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25_combout\); + +-- Location: LABCELL_X24_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000010100000101000001010000010110111011101110111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~25_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~8_combout\); + +-- Location: LABCELL_X24_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~6\); + +-- Location: LABCELL_X24_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~10\); + +-- Location: LABCELL_X26_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\)))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000111101010101000011110011001100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~93_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29_combout\); + +-- Location: LABCELL_X26_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~12_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000001111000000000000111111111111010101011111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~29_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~12_combout\); + +-- Location: LABCELL_X26_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\)))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000111100110011000011110101010100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~93_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17_combout\); + +-- Location: LABCELL_X26_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000010100000101000001010000010110111011101110111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~17_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~0_combout\); + +-- Location: MLABCELL_X23_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\)))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000111100110011000011110101010100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~93_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21_combout\); + +-- Location: MLABCELL_X23_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000010100000101000001010000010110111011101110111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~21_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~4_combout\); + +-- Location: MLABCELL_X23_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~12_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~12_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~12_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~12_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010011110100001101001100011100000111111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~16_combout\); + +-- Location: LABCELL_X29_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_RESYN12546\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_RESYN12546_BDD12547\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~16_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111110111111111111111011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_RESYN12546_BDD12547\); + +-- Location: MLABCELL_X23_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\); + +-- Location: LABCELL_X29_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_RESYN12546_BDD12547\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101010101010001010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~15_RESYN12546_BDD12547\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\); + +-- Location: LABCELL_X29_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~88\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~88_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~88_combout\); + +-- Location: LABCELL_X12_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~95\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~95_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011001100000011000011111111111111110011000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~95_combout\); + +-- Location: MLABCELL_X13_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~149\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~149_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010100011101100000000000000001010101010111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~149_combout\); + +-- Location: MLABCELL_X13_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_RESYN8655\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_RESYN8655_BDD8656\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~44_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~44_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~44_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~44_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000011000011111111011101110111010000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~44_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_RESYN8655_BDD8656\); + +-- Location: MLABCELL_X13_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~94\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~39_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_RESYN8655_BDD8656\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~39_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_RESYN8655_BDD8656\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000100000000000000000001111111101001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~94_RESYN8655_BDD8656\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~39_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_combout\); + +-- Location: LABCELL_X14_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ $ ((((\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000010000000100000001000000010000000011111111000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16_combout\); + +-- Location: LABCELL_X14_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~92\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~92_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~10_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~13_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~92_combout\); + +-- Location: MLABCELL_X13_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~150\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~150_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~92_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~149_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_combout\) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~92_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~149_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~92_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~149_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~92_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~149_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100010000000100010000000000010101010101000001010101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~149_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~94_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~92_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~150_combout\); + +-- Location: MLABCELL_X13_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~96\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~96_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001100001111000011110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~96_combout\); + +-- Location: MLABCELL_X13_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~91\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~91_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~112_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~101_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~112_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~101_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~112_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~101_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~112_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~101_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010111100001010000011001100100010001100000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~112_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~101_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~91_combout\); + +-- Location: MLABCELL_X13_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~97\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~97_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~101_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~91_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~95_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~150_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~96_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~101_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~91_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~95_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~150_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~96_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010000000000000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~95_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~150_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~96_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~101_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~91_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~97_combout\); + +-- Location: LABCELL_X16_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12774\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12774_BDD12775\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110110011001100110011001100110011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12774_BDD12775\); + +-- Location: LABCELL_X16_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN9003\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN9003_BDD9004\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111111111000011111111111100001100110011000000110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN9003_BDD9004\); + +-- Location: LABCELL_X16_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12776\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12776_BDD12777\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN9003_BDD9004\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN9003_BDD9004\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000100000000000000011000000000000001100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN9003_BDD9004\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12776_BDD12777\); + +-- Location: LABCELL_X16_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12776_BDD12777\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12774_BDD12775\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12776_BDD12777\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12774_BDD12775\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000001000100000000000000000000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12774_BDD12775\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~22_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12776_BDD12777\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_combout\); + +-- Location: FF_X2_Y34_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[26]_NEW_REG903\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~25_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[26]_OTERM904\); + +-- Location: LABCELL_X2_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[26]_OTERM904\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[26]_OTERM904\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM796\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[26]_OTERM904\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM796\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[26]_OTERM904\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM902\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~25_combout\); + +-- Location: LABCELL_X7_Y24_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~98\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~98_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~711_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~25_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~711_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~25_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~711_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~25_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~711_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~25_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001011111111110101111000000001010111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(26), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~711_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~25_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~98_combout\); + +-- Location: MLABCELL_X13_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~99\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~99_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~98_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~98_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\)))) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~98_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~98_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000101000011110000000000001111100011010000111111001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~98_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~99_combout\); + +-- Location: MLABCELL_X13_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~100\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~100_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~97_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~99_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~97_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~99_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~97_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~99_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS~88_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~97_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~99_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000000000000111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~88_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~97_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~99_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~100_combout\); + +-- Location: FF_X13_Y26_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~100_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(26)); + +-- Location: FF_X19_Y14_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~101_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(26)); + +-- Location: MLABCELL_X18_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(26) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\); + +-- Location: FF_X20_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(26)); + +-- Location: FF_X20_Y18_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(26)); + +-- Location: LABCELL_X20_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(26) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(26)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(26) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(26) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\); + +-- Location: LABCELL_X7_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[26]_NEW2953\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[26]_OTERM2954\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[26]_OTERM2954\); + +-- Location: FF_X7_Y23_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[26]_OTERM2954\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(26)); + +-- Location: LABCELL_X7_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[26]_NEW3145\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[26]_OTERM3146\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(26) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[26]_OTERM3146\); + +-- Location: FF_X7_Y23_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[26]_OTERM3146\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(26)); + +-- Location: LABCELL_X12_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]_NEW3017\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]_OTERM3018\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]_OTERM3018\); + +-- Location: FF_X12_Y23_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]_OTERM3018\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(26)); + +-- Location: LABCELL_X12_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]_NEW3081\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]_OTERM3082\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]_OTERM3082\); + +-- Location: FF_X12_Y23_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]_OTERM3082\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(26)); + +-- Location: LABCELL_X7_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux16~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(26) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(26) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(26) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(26) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(26), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(26), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(26), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~0_combout\); + +-- Location: LABCELL_X7_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[26]_NEW2697\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[26]_OTERM2698\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[26]_OTERM2698\); + +-- Location: FF_X7_Y23_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[26]_OTERM2698\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(26)); + +-- Location: LABCELL_X7_Y23_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[26]_NEW2761\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[26]_OTERM2762\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(26) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[26]_OTERM2762\); + +-- Location: FF_X7_Y23_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[26]_OTERM2762\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(26)); + +-- Location: LABCELL_X10_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[26]_NEW2889\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[26]_OTERM2890\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101000000111111010111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[26]_OTERM2890\); + +-- Location: FF_X10_Y21_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[26]_OTERM2890\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(26)); + +-- Location: LABCELL_X10_Y22_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[26]_NEW2825\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[26]_OTERM2826\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(26))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(26))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[26]_OTERM2826\); + +-- Location: FF_X10_Y22_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[26]_OTERM2826\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(26)); + +-- Location: LABCELL_X7_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux16~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(26))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(26))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(26) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(26))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(26) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(26) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(26))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(26)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010011111100000101001100001111010100111111111101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(26), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~1_combout\); + +-- Location: LABCELL_X7_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux16~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux16~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux16~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~2_combout\); + +-- Location: LABCELL_X10_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector299~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector299~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux16~2_combout\) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[26]~56_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux16~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001111000011000000111100111111000011110011111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~56_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector299~0_combout\); + +-- Location: FF_X10_Y14_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_NEW_REG761\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector299~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM762\); + +-- Location: FF_X7_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_NEW_REG759\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]~16_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM760\); + +-- Location: LABCELL_X7_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM760\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM762\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM760\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM762\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM760\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]_OTERM762\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]_OTERM760\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]~16_combout\); + +-- Location: LABCELL_X7_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[2]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[2]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]~16_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]~16_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]~16_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000001000001010100010101001011101010111010111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[2]~6_combout\); + +-- Location: LABCELL_X29_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~337\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~337_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~337_combout\); + +-- Location: FF_X29_Y30_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~337_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~20_combout\); + +-- Location: LABCELL_X26_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~27_combout\); + +-- Location: LABCELL_X26_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~28_combout\); + +-- Location: LABCELL_X25_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~29_combout\); + +-- Location: LABCELL_X24_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~31_combout\); + +-- Location: LABCELL_X26_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~30_combout\); + +-- Location: LABCELL_X25_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~30_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~28_combout\)))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~31_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~29_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000111101010101000011110011001100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~28_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~29_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~31_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~21_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4_combout\); + +-- Location: LABCELL_X31_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~22_combout\); + +-- Location: LABCELL_X25_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~22_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~20_combout\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~27_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~21_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000001111000000000000111111111111001100111111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~21_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~27_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux179~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0_combout\); + +-- Location: LABCELL_X25_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_RESYN12674\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_RESYN12674_BDD12675\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010000000000000101000000101000011110000010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_RESYN12674_BDD12675\); + +-- Location: LABCELL_X24_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_RESYN12674_BDD12675\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_RESYN12674_BDD12675\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000010000000000000000000000000000000101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_RESYN12674_BDD12675\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\); + +-- Location: LABCELL_X21_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8633\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8633_BDD8634\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111100001100001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8633_BDD8634\); + +-- Location: LABCELL_X17_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100000000001100000000000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~10_combout\); + +-- Location: LABCELL_X17_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000000000000001000000001000000110000000100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~12_combout\); + +-- Location: LABCELL_X16_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000100110000101010011011110001100101011101001110110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~17_combout\); + +-- Location: LABCELL_X17_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~12_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110110011100000111011001110000001001100010000000100110001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~13_combout\); + +-- Location: LABCELL_X17_Y21_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~11_combout\); + +-- Location: LABCELL_X17_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS~11_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS~11_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~13_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~13_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010001110100011101000111010001100001111101011110000000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~2_combout\); + +-- Location: MLABCELL_X18_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8631\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8631_BDD8632\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~9_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~9_sumout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~9_sumout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~9_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011000000100010001000000011111111111100001010101010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~9_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8631_BDD8632\); + +-- Location: LABCELL_X21_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8631_BDD8632\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8633_BDD8634\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8631_BDD8632\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8633_BDD8634\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001000110010001100000000000000000010001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_RESYN8633_BDD8634\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_RESYN8631_BDD8632\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_combout\); + +-- Location: FF_X2_Y33_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[22]_NEW_REG1174\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[22]_OTERM1175\); + +-- Location: LABCELL_X2_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM796\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[22]_OTERM1175\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM796\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[22]_OTERM1175\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[22]_OTERM1175\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM796\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~2_combout\); + +-- Location: LABCELL_X2_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100001111001111110000111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~0_combout\); + +-- Location: LABCELL_X7_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~346_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~346_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111001100110011001100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~346_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~1_combout\); + +-- Location: LABCELL_X21_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011001000111110101100100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~2_combout\); + +-- Location: LABCELL_X21_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100110011000100110011001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~3_combout\); + +-- Location: FF_X21_Y23_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(22)); + +-- Location: FF_X19_Y14_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~9_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(22)); + +-- Location: LABCELL_X19_Y14_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(22) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(22) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(22) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\); + +-- Location: LABCELL_X19_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add36~18_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add36~18_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100000001001111111100000111000001110000011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~18_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~11_combout\); + +-- Location: LABCELL_X6_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~6\); + +-- Location: LABCELL_X6_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~10\); + +-- Location: LABCELL_X6_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~20_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~17_sumout\); + +-- Location: MLABCELL_X4_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~10\); + +-- Location: MLABCELL_X4_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~20_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~17_sumout\); + +-- Location: MLABCELL_X9_Y25_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~18_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add19~17_sumout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~17_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~18_combout\); + +-- Location: LABCELL_X7_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~26\); + +-- Location: LABCELL_X7_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~30\); + +-- Location: LABCELL_X7_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~14\); + +-- Location: LABCELL_X7_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~6\); + +-- Location: LABCELL_X7_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~10\); + +-- Location: LABCELL_X7_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~20_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\); + +-- Location: LABCELL_X10_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|sp~18_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add21~17_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|sp~18_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add21~17_sumout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~17_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~19_combout\); + +-- Location: FF_X10_Y25_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_NEW_REG895\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp~19_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM896\); + +-- Location: FF_X6_Y25_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_NEW_REG889\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM890\); + +-- Location: LABCELL_X6_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM892\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM894\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM890\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM894\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM896\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM892\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM890\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM896\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM894\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM890\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM892\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\); + +-- Location: LABCELL_X14_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add35~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~20_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~17_sumout\); + +-- Location: LABCELL_X16_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~10_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~17_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110010101000111111001010100011111100101010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~10_combout\); + +-- Location: LABCELL_X16_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~13_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~9_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~10_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~12_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000000000000000000000000011000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~13_combout\); + +-- Location: LABCELL_X17_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110000111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~14_combout\); + +-- Location: LABCELL_X17_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~2_combout\); + +-- Location: LABCELL_X17_Y22_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9109\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9109_BDD9110\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~2_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9109_BDD9110\); + +-- Location: LABCELL_X14_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_RESYN8969\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_RESYN8969_BDD8970\ = (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_RESYN8969_BDD8970\); + +-- Location: LABCELL_X14_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_RESYN8969_BDD8970\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_RESYN8969_BDD8970\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000100000001000001010000011110000001000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~3_RESYN8969_BDD8970\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_combout\); + +-- Location: MLABCELL_X13_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000100000001000000000000000001000101010001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~29_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~17_combout\); + +-- Location: MLABCELL_X13_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\)))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111110011000100011100110011010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~25_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~27_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~24_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~28_combout\); + +-- Location: MLABCELL_X13_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~28_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~17_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~28_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~17_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~28_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~17_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~28_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~17_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101000001010000000101010001010100010000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~18_combout\); + +-- Location: LABCELL_X14_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000010000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~2_combout\); + +-- Location: LABCELL_X14_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~18_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~18_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001111110000001100111111000011111111010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~4_combout\); + +-- Location: LABCELL_X17_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9107\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9107_BDD9108\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~17_sumout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~17_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~17_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~17_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~17_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001011111111100110111001101110011011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~17_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9107_BDD9108\); + +-- Location: LABCELL_X17_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_BDD8636\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9107_BDD9108\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9107_BDD9108\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9107_BDD9108\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9109_BDD9110\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9107_BDD9108\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9109_BDD9110\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101110111001111110111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_RESYN9109_BDD9110\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_RESYN9107_BDD9108\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_BDD8636\); + +-- Location: LABCELL_X17_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8973\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8973_BDD8974\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_BDD8636\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~14_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_BDD8636\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_BDD8636\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~14_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_BDD8636\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011111111111101010101111111110101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_BDD8636\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8973_BDD8974\); + +-- Location: FF_X2_Y31_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_NEW_REG1170\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171\); + +-- Location: FF_X2_Y31_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_NEW_REG1168\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1169\); + +-- Location: FF_X2_Y31_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_NEW_REG1172\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~11_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1173\); + +-- Location: LABCELL_X2_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1173\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1169\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1173\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1169\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1169\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1173\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~4_combout\); + +-- Location: LABCELL_X2_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~4_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000100010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~1_combout\); + +-- Location: LABCELL_X5_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~354_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~354_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111001100110011001100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~354_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~2_combout\); + +-- Location: LABCELL_X17_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8971\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8971_BDD8972\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~2_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011010101110101011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8971_BDD8972\); + +-- Location: LABCELL_X17_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8973_BDD8974\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8971_BDD8972\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8973_BDD8974\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8971_BDD8972\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8973_BDD8974\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8971_BDD8972\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8973_BDD8974\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8971_BDD8972\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~7_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110101000000001111011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8973_BDD8974\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8971_BDD8972\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_combout\); + +-- Location: FF_X17_Y22_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(23)); + +-- Location: FF_X19_Y14_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[23]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~17_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[23]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[23]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[23]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(23)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\); + +-- Location: FF_X19_Y17_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[23]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(23)); + +-- Location: FF_X19_Y17_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(23)); + +-- Location: LABCELL_X19_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(23)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\); + +-- Location: MLABCELL_X13_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[23]_NEW2973\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[23]_OTERM2974\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[23]_OTERM2974\); + +-- Location: FF_X13_Y22_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[23]_OTERM2974\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(23)); + +-- Location: MLABCELL_X13_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[23]_NEW3165\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[23]_OTERM3166\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(23))))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[23]_OTERM3166\); + +-- Location: FF_X13_Y22_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[23]_OTERM3166\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(23)); + +-- Location: MLABCELL_X13_Y22_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[23]_NEW3101\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[23]_OTERM3102\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(23) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[23]_OTERM3102\); + +-- Location: FF_X13_Y22_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[23]_OTERM3102\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(23)); + +-- Location: MLABCELL_X13_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[23]_NEW3037\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[23]_OTERM3038\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(23) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[23]_OTERM3038\); + +-- Location: FF_X13_Y22_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[23]_OTERM3038\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(23)); + +-- Location: MLABCELL_X13_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(23)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(23)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000100010001000100001010010111111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~0_combout\); + +-- Location: MLABCELL_X9_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[23]_NEW2781\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[23]_OTERM2782\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(23) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[23]_OTERM2782\); + +-- Location: FF_X9_Y22_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[23]_OTERM2782\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(23)); + +-- Location: MLABCELL_X9_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]_NEW2909\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]_OTERM2910\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]_OTERM2910\); + +-- Location: FF_X9_Y22_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]_OTERM2910\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(23)); + +-- Location: MLABCELL_X9_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[23]_NEW2845\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[23]_OTERM2846\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(23) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[23]_OTERM2846\); + +-- Location: FF_X9_Y22_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[23]_OTERM2846\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(23)); + +-- Location: LABCELL_X12_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[23]_NEW2717\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[23]_OTERM2718\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001001100011100110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[23]_OTERM2718\); + +-- Location: FF_X12_Y25_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[23]_OTERM2718\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(23)); + +-- Location: LABCELL_X10_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(23)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(23)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(23) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(23) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000101001100001111010100111111000001010011111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~1_combout\); + +-- Location: LABCELL_X10_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\); + +-- Location: MLABCELL_X9_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector11~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector11~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111111111000000111111111100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector11~0_combout\); + +-- Location: MLABCELL_X9_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector269~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector269~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector11~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector11~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector11~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2_combout\)))) ) ) ) # +-- ( !\myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector11~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111010101010010011110101010001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector11~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector269~0_combout\); + +-- Location: FF_X9_Y16_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_NEW_REG935\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector269~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM936\); + +-- Location: FF_X9_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_NEW_REG933\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM934\); + +-- Location: MLABCELL_X9_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM934\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM936\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM934\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM936\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM934\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]_OTERM936\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]_OTERM934\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\); + +-- Location: MLABCELL_X9_Y9_N57 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]~18_combout\, + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~feeder_combout\); + +-- Location: FF_X9_Y9_N58 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(7)); + +-- Location: FF_X10_Y9_N23 +\myVirtualToplevel|UART0|TX_COUNTER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~33_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(7), + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(7)); + +-- Location: LABCELL_X10_Y9_N24 +\myVirtualToplevel|UART0|Add0~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~17_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~34\ )) +-- \myVirtualToplevel|UART0|Add0~18\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(8), + cin => \myVirtualToplevel|UART0|Add0~34\, + sumout => \myVirtualToplevel|UART0|Add0~17_sumout\, + cout => \myVirtualToplevel|UART0|Add0~18\); + +-- Location: MLABCELL_X9_Y9_N0 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(24), + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[8]~feeder_combout\); + +-- Location: FF_X9_Y9_N1 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[8]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(8)); + +-- Location: FF_X10_Y9_N26 +\myVirtualToplevel|UART0|TX_COUNTER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~17_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(8), + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(8)); + +-- Location: LABCELL_X10_Y9_N27 +\myVirtualToplevel|UART0|Add0~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~9_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~18\ )) +-- \myVirtualToplevel|UART0|Add0~10\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(9), + cin => \myVirtualToplevel|UART0|Add0~18\, + sumout => \myVirtualToplevel|UART0|Add0~9_sumout\, + cout => \myVirtualToplevel|UART0|Add0~10\); + +-- Location: FF_X9_Y9_N25 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(9)); + +-- Location: FF_X10_Y9_N29 +\myVirtualToplevel|UART0|TX_COUNTER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~9_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(9), + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(9)); + +-- Location: LABCELL_X10_Y9_N30 +\myVirtualToplevel|UART0|Add0~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~13_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~10\ )) +-- \myVirtualToplevel|UART0|Add0~14\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(10), + cin => \myVirtualToplevel|UART0|Add0~10\, + sumout => \myVirtualToplevel|UART0|Add0~13_sumout\, + cout => \myVirtualToplevel|UART0|Add0~14\); + +-- Location: MLABCELL_X9_Y9_N30 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(26), + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~1_combout\); + +-- Location: FF_X9_Y9_N32 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(10)); + +-- Location: MLABCELL_X9_Y9_N33 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~_wirecell_combout\ = ( !\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(10), + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~_wirecell_combout\); + +-- Location: FF_X10_Y9_N32 +\myVirtualToplevel|UART0|TX_COUNTER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~13_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~_wirecell_combout\, + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(10)); + +-- Location: LABCELL_X10_Y9_N33 +\myVirtualToplevel|UART0|Add0~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~41_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~14\ )) +-- \myVirtualToplevel|UART0|Add0~42\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(11), + cin => \myVirtualToplevel|UART0|Add0~14\, + sumout => \myVirtualToplevel|UART0|Add0~41_sumout\, + cout => \myVirtualToplevel|UART0|Add0~42\); + +-- Location: MLABCELL_X9_Y9_N12 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(27), + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[11]~feeder_combout\); + +-- Location: FF_X9_Y9_N13 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[11]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(11)); + +-- Location: FF_X10_Y9_N35 +\myVirtualToplevel|UART0|TX_COUNTER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~41_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(11), + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(11)); + +-- Location: LABCELL_X10_Y9_N36 +\myVirtualToplevel|UART0|Add0~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~45_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~42\ )) +-- \myVirtualToplevel|UART0|Add0~46\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(12), + cin => \myVirtualToplevel|UART0|Add0~42\, + sumout => \myVirtualToplevel|UART0|Add0~45_sumout\, + cout => \myVirtualToplevel|UART0|Add0~46\); + +-- Location: MLABCELL_X9_Y9_N15 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(28), + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[12]~feeder_combout\); + +-- Location: FF_X9_Y9_N16 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[12]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(12)); + +-- Location: FF_X10_Y9_N38 +\myVirtualToplevel|UART0|TX_COUNTER[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~45_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(12), + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(12)); + +-- Location: LABCELL_X10_Y9_N48 +\myVirtualToplevel|UART0|Equal0~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal0~2_combout\ = ( !\myVirtualToplevel|UART0|TX_COUNTER\(11) & ( (!\myVirtualToplevel|UART0|TX_COUNTER\(12) & (!\myVirtualToplevel|UART0|TX_COUNTER\(0) & !\myVirtualToplevel|UART0|TX_COUNTER\(7))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(12), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(0), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(7), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(11), + combout => \myVirtualToplevel|UART0|Equal0~2_combout\); + +-- Location: LABCELL_X10_Y9_N39 +\myVirtualToplevel|UART0|Add0~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~57_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~46\ )) +-- \myVirtualToplevel|UART0|Add0~58\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(13), + cin => \myVirtualToplevel|UART0|Add0~46\, + sumout => \myVirtualToplevel|UART0|Add0~57_sumout\, + cout => \myVirtualToplevel|UART0|Add0~58\); + +-- Location: FF_X12_Y9_N46 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(29), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(13)); + +-- Location: FF_X10_Y9_N41 +\myVirtualToplevel|UART0|TX_COUNTER[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~57_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(13), + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(13)); + +-- Location: LABCELL_X10_Y9_N42 +\myVirtualToplevel|UART0|Add0~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~61_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~58\ )) +-- \myVirtualToplevel|UART0|Add0~62\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|UART0|Add0~58\, + sumout => \myVirtualToplevel|UART0|Add0~61_sumout\, + cout => \myVirtualToplevel|UART0|Add0~62\); + +-- Location: MLABCELL_X9_Y9_N27 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(30), + combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[14]~feeder_combout\); + +-- Location: FF_X9_Y9_N28 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[14]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(14)); + +-- Location: FF_X10_Y9_N44 +\myVirtualToplevel|UART0|TX_COUNTER[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~61_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(14), + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER[14]~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y9_N45 +\myVirtualToplevel|UART0|Add0~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add0~5_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(15) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(15), + cin => \myVirtualToplevel|UART0|Add0~62\, + sumout => \myVirtualToplevel|UART0|Add0~5_sumout\); + +-- Location: FF_X12_Y9_N7 +\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(15)); + +-- Location: FF_X10_Y9_N47 +\myVirtualToplevel|UART0|TX_COUNTER[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~5_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(15), + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(15)); + +-- Location: LABCELL_X10_Y9_N51 +\myVirtualToplevel|UART0|Equal0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal0~0_combout\ = ( !\myVirtualToplevel|UART0|TX_COUNTER\(6) & ( (!\myVirtualToplevel|UART0|TX_COUNTER\(15) & (!\myVirtualToplevel|UART0|TX_COUNTER\(10) & !\myVirtualToplevel|UART0|TX_COUNTER\(9))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(15), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(10), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(9), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(6), + combout => \myVirtualToplevel|UART0|Equal0~0_combout\); + +-- Location: FF_X10_Y9_N43 +\myVirtualToplevel|UART0|TX_COUNTER[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~61_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(14), + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(14)); + +-- Location: LABCELL_X10_Y9_N57 +\myVirtualToplevel|UART0|Equal0~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal0~3_combout\ = ( !\myVirtualToplevel|UART0|TX_COUNTER\(13) & ( (!\myVirtualToplevel|UART0|TX_COUNTER\(5) & (!\myVirtualToplevel|UART0|TX_COUNTER\(4) & !\myVirtualToplevel|UART0|TX_COUNTER\(14))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(5), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(4), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(14), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(13), + combout => \myVirtualToplevel|UART0|Equal0~3_combout\); + +-- Location: FF_X10_Y9_N10 +\myVirtualToplevel|UART0|TX_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add0~29_sumout\, + asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~_wirecell_combout\, + sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_COUNTER\(3)); + +-- Location: LABCELL_X10_Y9_N54 +\myVirtualToplevel|UART0|Equal0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal0~1_combout\ = ( !\myVirtualToplevel|UART0|TX_COUNTER\(2) & ( (!\myVirtualToplevel|UART0|TX_COUNTER\(1) & (!\myVirtualToplevel|UART0|TX_COUNTER\(8) & !\myVirtualToplevel|UART0|TX_COUNTER\(3))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(1), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(8), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(3), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(2), + combout => \myVirtualToplevel|UART0|Equal0~1_combout\); + +-- Location: MLABCELL_X9_Y9_N48 +\myVirtualToplevel|UART0|Equal0~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal0~4_combout\ = ( \myVirtualToplevel|UART0|Equal0~3_combout\ & ( \myVirtualToplevel|UART0|Equal0~1_combout\ & ( (\myVirtualToplevel|UART0|Equal0~2_combout\ & \myVirtualToplevel|UART0|Equal0~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_Equal0~2_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Equal0~0_combout\, + datae => \myVirtualToplevel|UART0|ALT_INV_Equal0~3_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_Equal0~1_combout\, + combout => \myVirtualToplevel|UART0|Equal0~4_combout\); + +-- Location: LABCELL_X5_Y8_N54 +\myVirtualToplevel|UART0|TX_CLOCK~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_CLOCK~0_combout\ = ( \myVirtualToplevel|UART0|Equal0~4_combout\ & ( \myVirtualToplevel|UART0|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|UART0|ALT_INV_Equal0~4_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + combout => \myVirtualToplevel|UART0|TX_CLOCK~0_combout\); + +-- Location: FF_X5_Y8_N56 +\myVirtualToplevel|UART0|TX_CLOCK\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_CLOCK~0_combout\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_CLOCK~q\); + +-- Location: LABCELL_X5_Y8_N18 +\myVirtualToplevel|UART0|TX_BUFFER[16]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER[16]~9_combout\ = ( !\myVirtualToplevel|UART0|TX_STATE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + combout => \myVirtualToplevel|UART0|TX_BUFFER[16]~9_combout\); + +-- Location: MLABCELL_X9_Y8_N33 +\myVirtualToplevel|UART0|TX_DATA[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA[0]~0_combout\ = (\myVirtualToplevel|UART0|TX_RESET~q\ & !\myVirtualToplevel|UART0|TX_ENABLE~q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_RESET~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + combout => \myVirtualToplevel|UART0|TX_DATA[0]~0_combout\); + +-- Location: LABCELL_X5_Y8_N30 +\myVirtualToplevel|UART0|TX_BUFFER[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\ = ( \myVirtualToplevel|UART0|TX_DATA[0]~0_combout\ & ( (!\myVirtualToplevel|UART0|TX_STATE~q\ & ((\myVirtualToplevel|UART0|TX_DATA_LOADED~q\))) # (\myVirtualToplevel|UART0|TX_STATE~q\ & +-- (\myVirtualToplevel|UART0|TX_CLOCK~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001101010011010100000000000000000011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK~q\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + datae => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~0_combout\, + combout => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\); + +-- Location: FF_X5_Y8_N20 +\myVirtualToplevel|UART0|TX_BUFFER[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER[16]~9_combout\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(16)); + +-- Location: LABCELL_X5_Y8_N45 +\myVirtualToplevel|UART0|TX_BUFFER~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER~8_combout\ = ( \myVirtualToplevel|UART0|TX_BUFFER\(16) ) # ( !\myVirtualToplevel|UART0|TX_BUFFER\(16) & ( !\myVirtualToplevel|UART0|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(16), + combout => \myVirtualToplevel|UART0|TX_BUFFER~8_combout\); + +-- Location: FF_X5_Y8_N47 +\myVirtualToplevel|UART0|TX_BUFFER[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER~8_combout\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(15)); + +-- Location: LABCELL_X5_Y8_N42 +\myVirtualToplevel|UART0|TX_BUFFER~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER~7_combout\ = ( \myVirtualToplevel|UART0|TX_BUFFER\(15) ) # ( !\myVirtualToplevel|UART0|TX_BUFFER\(15) & ( !\myVirtualToplevel|UART0|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(15), + combout => \myVirtualToplevel|UART0|TX_BUFFER~7_combout\); + +-- Location: FF_X5_Y8_N43 +\myVirtualToplevel|UART0|TX_BUFFER[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER~7_combout\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(14)); + +-- Location: LABCELL_X5_Y8_N27 +\myVirtualToplevel|UART0|TX_BUFFER~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER~6_combout\ = ( \myVirtualToplevel|UART0|TX_BUFFER\(14) ) # ( !\myVirtualToplevel|UART0|TX_BUFFER\(14) & ( !\myVirtualToplevel|UART0|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(14), + combout => \myVirtualToplevel|UART0|TX_BUFFER~6_combout\); + +-- Location: FF_X5_Y8_N28 +\myVirtualToplevel|UART0|TX_BUFFER[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER~6_combout\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(13)); + +-- Location: LABCELL_X5_Y8_N24 +\myVirtualToplevel|UART0|TX_BUFFER~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER~5_combout\ = ( \myVirtualToplevel|UART0|TX_BUFFER\(13) ) # ( !\myVirtualToplevel|UART0|TX_BUFFER\(13) & ( !\myVirtualToplevel|UART0|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(13), + combout => \myVirtualToplevel|UART0|TX_BUFFER~5_combout\); + +-- Location: FF_X5_Y8_N26 +\myVirtualToplevel|UART0|TX_BUFFER[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER~5_combout\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(12)); + +-- Location: LABCELL_X5_Y8_N9 +\myVirtualToplevel|UART0|TX_BUFFER~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER~4_combout\ = ( \myVirtualToplevel|UART0|TX_BUFFER\(12) ) # ( !\myVirtualToplevel|UART0|TX_BUFFER\(12) & ( !\myVirtualToplevel|UART0|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(12), + combout => \myVirtualToplevel|UART0|TX_BUFFER~4_combout\); + +-- Location: FF_X5_Y8_N11 +\myVirtualToplevel|UART0|TX_BUFFER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER~4_combout\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(11)); + +-- Location: LABCELL_X5_Y8_N6 +\myVirtualToplevel|UART0|TX_BUFFER~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER~3_combout\ = ( \myVirtualToplevel|UART0|TX_BUFFER\(11) ) # ( !\myVirtualToplevel|UART0|TX_BUFFER\(11) & ( !\myVirtualToplevel|UART0|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(11), + combout => \myVirtualToplevel|UART0|TX_BUFFER~3_combout\); + +-- Location: FF_X5_Y8_N7 +\myVirtualToplevel|UART0|TX_BUFFER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER~3_combout\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(10)); + +-- Location: LABCELL_X5_Y8_N39 +\myVirtualToplevel|UART0|TX_BUFFER~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER~2_combout\ = ( \myVirtualToplevel|UART0|TX_BUFFER\(10) ) # ( !\myVirtualToplevel|UART0|TX_BUFFER\(10) & ( !\myVirtualToplevel|UART0|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(10), + combout => \myVirtualToplevel|UART0|TX_BUFFER~2_combout\); + +-- Location: FF_X5_Y8_N41 +\myVirtualToplevel|UART0|TX_BUFFER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER~2_combout\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(9)); + +-- Location: LABCELL_X5_Y8_N36 +\myVirtualToplevel|UART0|TX_BUFFER~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER~1_combout\ = ( \myVirtualToplevel|UART0|TX_BUFFER\(9) ) # ( !\myVirtualToplevel|UART0|TX_BUFFER\(9) & ( !\myVirtualToplevel|UART0|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(9), + combout => \myVirtualToplevel|UART0|TX_BUFFER~1_combout\); + +-- Location: FF_X5_Y8_N37 +\myVirtualToplevel|UART0|TX_BUFFER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER~1_combout\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(8)); + +-- Location: MLABCELL_X9_Y8_N21 +\myVirtualToplevel|UART0|TX_STATE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_STATE~0_combout\ = ( \myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ( (!\myVirtualToplevel|UART0|TX_ENABLE~q\ & ((!\myVirtualToplevel|UART0|TX_CLOCK~q\) # ((!\myVirtualToplevel|UART0|TX_STATE~q\) # +-- (\myVirtualToplevel|UART0|TX_BUFFER\(8))))) # (\myVirtualToplevel|UART0|TX_ENABLE~q\ & (((\myVirtualToplevel|UART0|TX_STATE~q\)))) ) ) # ( !\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ( (\myVirtualToplevel|UART0|TX_STATE~q\ & +-- (((!\myVirtualToplevel|UART0|TX_CLOCK~q\) # (\myVirtualToplevel|UART0|TX_BUFFER\(8))) # (\myVirtualToplevel|UART0|TX_ENABLE~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011011111000000001101111110101010110111111010101011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(8), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\, + combout => \myVirtualToplevel|UART0|TX_STATE~0_combout\); + +-- Location: FF_X9_Y8_N23 +\myVirtualToplevel|UART0|TX_STATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_STATE~0_combout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_STATE~q\); + +-- Location: MLABCELL_X9_Y8_N51 +\myVirtualToplevel|UART0|Equal5~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal5~3_combout\ = ( \myVirtualToplevel|UART0|Equal5~2_combout\ & ( (\myVirtualToplevel|UART0|Equal5~0_combout\ & \myVirtualToplevel|UART0|Equal5~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001010000010100000000000000000000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Equal5~0_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Equal5~1_combout\, + datae => \myVirtualToplevel|UART0|ALT_INV_Equal5~2_combout\, + combout => \myVirtualToplevel|UART0|Equal5~3_combout\); + +-- Location: MLABCELL_X9_Y8_N42 +\myVirtualToplevel|UART0|TX_DATA_LOADED~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA_LOADED~0_combout\ = ( !\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ & ( (!\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & (((!\myVirtualToplevel|UART0|Equal5~3_combout\)))) # (\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & +-- ((((\myVirtualToplevel|UART0|TX_STATE~q\))))) ) ) # ( \myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ & ( (!\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (\myVirtualToplevel|UART0_CS~combout\ & +-- (\myVirtualToplevel|UART1|Equal7~0_combout\)))) # (\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ((((\myVirtualToplevel|UART0|TX_STATE~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "1010000010100000000000000000001011110101111101010101010101010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datac => \myVirtualToplevel|ALT_INV_UART0_CS~combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\, + datae => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + datag => \myVirtualToplevel|UART0|ALT_INV_Equal5~3_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA_LOADED~0_combout\); + +-- Location: FF_X9_Y8_N44 +\myVirtualToplevel|UART0|TX_DATA_LOADED\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_DATA_LOADED~0_combout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_DATA_LOADED~q\); + +-- Location: MLABCELL_X9_Y8_N12 +\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\ = ( !\myVirtualToplevel|UART0|TX_ENABLE~q\ & ( !\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ( (!\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ & ((!\myVirtualToplevel|UART0|Equal5~0_combout\) # +-- ((!\myVirtualToplevel|UART0|Equal5~1_combout\) # (!\myVirtualToplevel|UART0|Equal5~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Equal5~0_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_Equal5~1_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Equal5~2_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\, + datae => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\, + combout => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\); + +-- Location: FF_X10_Y8_N32 +\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add8~9_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0)); + +-- Location: LABCELL_X10_Y8_N33 +\myVirtualToplevel|UART0|Add8~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add8~13_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~10\ )) +-- \myVirtualToplevel|UART0|Add8~14\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(1), + cin => \myVirtualToplevel|UART0|Add8~10\, + sumout => \myVirtualToplevel|UART0|Add8~13_sumout\, + cout => \myVirtualToplevel|UART0|Add8~14\); + +-- Location: FF_X10_Y8_N35 +\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add8~13_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1)); + +-- Location: LABCELL_X10_Y8_N36 +\myVirtualToplevel|UART0|Add8~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add8~17_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~14\ )) +-- \myVirtualToplevel|UART0|Add8~18\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|UART0|Add8~14\, + sumout => \myVirtualToplevel|UART0|Add8~17_sumout\, + cout => \myVirtualToplevel|UART0|Add8~18\); + +-- Location: FF_X10_Y8_N38 +\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add8~17_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2)); + +-- Location: LABCELL_X10_Y8_N39 +\myVirtualToplevel|UART0|Add8~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add8~21_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~18\ )) +-- \myVirtualToplevel|UART0|Add8~22\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|UART0|Add8~18\, + sumout => \myVirtualToplevel|UART0|Add8~21_sumout\, + cout => \myVirtualToplevel|UART0|Add8~22\); + +-- Location: FF_X10_Y8_N41 +\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add8~21_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3)); + +-- Location: LABCELL_X10_Y8_N42 +\myVirtualToplevel|UART0|Add8~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add8~25_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~22\ )) +-- \myVirtualToplevel|UART0|Add8~26\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|UART0|Add8~22\, + sumout => \myVirtualToplevel|UART0|Add8~25_sumout\, + cout => \myVirtualToplevel|UART0|Add8~26\); + +-- Location: FF_X10_Y8_N44 +\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add8~25_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4)); + +-- Location: LABCELL_X10_Y8_N45 +\myVirtualToplevel|UART0|Add8~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Add8~29_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~26\ )) +-- \myVirtualToplevel|UART0|Add8~30\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(5), + cin => \myVirtualToplevel|UART0|Add8~26\, + sumout => \myVirtualToplevel|UART0|Add8~29_sumout\, + cout => \myVirtualToplevel|UART0|Add8~30\); + +-- Location: FF_X10_Y8_N47 +\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add8~29_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5)); + +-- Location: FF_X10_Y8_N50 +\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|Add8~1_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6)); + +-- Location: LABCELL_X14_Y9_N12 +\myVirtualToplevel|IO_DATA_READ~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~9_combout\ = ( \myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\ & ( \myVirtualToplevel|UART1|Add10~9_sumout\ & ( ((!\myVirtualToplevel|UART1_CS~combout\ & (!\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( !\myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\ & ( \myVirtualToplevel|UART1|Add10~9_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- ((!\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\) # (\myVirtualToplevel|UART1_CS~combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( \myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\ & ( !\myVirtualToplevel|UART1|Add10~9_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((!\myVirtualToplevel|UART1_CS~combout\ & !\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) ) # ( !\myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\ & ( +-- !\myVirtualToplevel|UART1|Add10~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((!\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) # (\myVirtualToplevel|UART1_CS~combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110111000000001011001100110011111101110011001110110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE_FIFO~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add10~9_sumout\, + combout => \myVirtualToplevel|IO_DATA_READ~9_combout\); + +-- Location: FF_X14_Y9_N13 +\myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1266\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~9_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[22]_OTERM1267\); + +-- Location: FF_X13_Y11_N37 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~9_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(22)); + +-- Location: MLABCELL_X18_Y11_N3 +\myVirtualToplevel|IO_DATA_READ~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~10_combout\ = ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # (\myVirtualToplevel|MILLISEC_UP_COUNTER\(22)))) ) ) # ( +-- !\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100010000000000010001010101010001000101010101000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(22), + combout => \myVirtualToplevel|IO_DATA_READ~10_combout\); + +-- Location: FF_X18_Y11_N49 +\myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1268\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|IO_DATA_READ~10_combout\, + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[22]_OTERM1269\); + +-- Location: LABCELL_X16_Y11_N42 +\myVirtualToplevel|IO_DATA_READ~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~11_combout\ = ( \myVirtualToplevel|IO_DATA_READ[22]_OTERM1269\ & ( (!\myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\ & (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1267\)) # (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\ & +-- ((!\myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\ & ((\myVirtualToplevel|IO_DATA_READ[22]_OTERM1263\))) # (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\ & (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1267\)))) ) ) # ( +-- !\myVirtualToplevel|IO_DATA_READ[22]_OTERM1269\ & ( (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1267\ & ((!\myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\) # (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010101010100000101010101010011010101010101001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1267\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1263\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1265\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1261\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1269\, + combout => \myVirtualToplevel|IO_DATA_READ~11_combout\); + +-- Location: LABCELL_X24_Y9_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector9~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector9~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(6) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(6), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector9~0_combout\); + +-- Location: FF_X24_Y9_N37 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector9~0_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6), + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(6)); + +-- Location: LABCELL_X21_Y9_N30 +\myVirtualToplevel|IO_DATA_READ_SD[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[22]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(6) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(6), + combout => \myVirtualToplevel|IO_DATA_READ_SD[22]~feeder_combout\); + +-- Location: LABCELL_X21_Y9_N54 +\myVirtualToplevel|SD_ADDR[0][22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]~16_combout\, + combout => \myVirtualToplevel|SD_ADDR[0][22]~feeder_combout\); + +-- Location: FF_X21_Y9_N56 +\myVirtualToplevel|SD_ADDR[0][22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][22]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][22]~q\); + +-- Location: FF_X21_Y9_N31 +\myVirtualToplevel|IO_DATA_READ_SD[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[22]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][22]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(22)); + +-- Location: FF_X18_Y12_N11 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux87~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(22)); + +-- Location: MLABCELL_X18_Y12_N9 +\myVirtualToplevel|MEM_DATA_READ[22]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[22]~11_combout\ = ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(22) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((!\myVirtualToplevel|INTR0_CS~combout\))) # +-- (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ~11_combout\)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(22) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((!\myVirtualToplevel|INTR0_CS~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ~11_combout\)) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(22) & ( +-- !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) # (\myVirtualToplevel|IO_DATA_READ_SD\(22)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(22) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ +-- & ( (\myVirtualToplevel|IO_DATA_READ_SD\(22) & \myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111111001100010101011100110001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ~11_combout\, + datab => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(22), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(22), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[22]~11_combout\); + +-- Location: MLABCELL_X18_Y12_N21 +\myVirtualToplevel|MEM_DATA_READ[22]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[22]~12_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[22]~11_combout\ ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[22]~12_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[22]~11_combout\ & ( ((\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\) ) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[22]~12_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[22]~11_combout\ ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[22]~12_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[22]~11_combout\ & ( +-- (\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001111111111111111100010001111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[22]~6_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~12_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~11_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\); + +-- Location: MLABCELL_X9_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector12~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector12~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000111111001100110011111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector12~0_combout\); + +-- Location: MLABCELL_X9_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector270~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector270~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector12~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|MEM_DATA_READ[22]~13_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector12~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|MEM_DATA_READ[22]~13_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector12~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|MEM_DATA_READ[22]~13_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector12~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (\myVirtualToplevel|MEM_DATA_READ[22]~13_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001100000101111100111111010100000011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector12~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector270~0_combout\); + +-- Location: FF_X9_Y18_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_NEW_REG915\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector270~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM916\); + +-- Location: MLABCELL_X9_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM916\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM914\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM916\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM914\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101111000000001010111101010000111111110101000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]_OTERM914\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]_OTERM916\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\); + +-- Location: MLABCELL_X18_Y7_N6 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\ & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][22]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]~16_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~16_combout\); + +-- Location: FF_X18_Y7_N7 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~16_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~q\); + +-- Location: FF_X19_Y7_N8 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~61_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][22]~q\); + +-- Location: LABCELL_X19_Y7_N9 +\myVirtualToplevel|TIMER:TIMER1|Add1~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~29_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][23]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~62\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~30\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][23]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][23]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~62\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~29_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~30\); + +-- Location: MLABCELL_X18_Y7_N45 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\ & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][23]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]~18_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~8_combout\); + +-- Location: FF_X18_Y7_N46 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~q\); + +-- Location: FF_X19_Y7_N11 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~29_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][23]~q\); + +-- Location: LABCELL_X19_Y7_N12 +\myVirtualToplevel|TIMER:TIMER1|Add1~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~57_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][24]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~30\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~58\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][24]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][24]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~30\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~57_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~58\); + +-- Location: MLABCELL_X18_Y7_N0 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24) & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][24]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(24), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~15_combout\); + +-- Location: FF_X18_Y7_N1 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~15_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~q\); + +-- Location: FF_X19_Y7_N14 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~57_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][24]~q\); + +-- Location: LABCELL_X19_Y7_N15 +\myVirtualToplevel|TIMER:TIMER1|Add1~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~53_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][25]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~58\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~54\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][25]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][25]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~58\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~53_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~54\); + +-- Location: MLABCELL_X18_Y7_N15 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25) & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][25]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(25), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~14_combout\); + +-- Location: FF_X18_Y7_N16 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~14_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~q\); + +-- Location: FF_X19_Y7_N16 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~53_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][25]~q\); + +-- Location: LABCELL_X19_Y7_N18 +\myVirtualToplevel|TIMER:TIMER1|Add1~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~49_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][26]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~54\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~50\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][26]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][26]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~54\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~49_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~50\); + +-- Location: MLABCELL_X18_Y7_N39 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~13_combout\ = (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & (((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~q\)))) # (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ +-- & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~q\))) # (\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111101111000000011110111100000001111011110000000111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(26), + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][26]~q\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~13_combout\); + +-- Location: FF_X18_Y7_N40 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~13_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~q\); + +-- Location: FF_X19_Y7_N20 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~49_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][26]~q\); + +-- Location: LABCELL_X19_Y7_N21 +\myVirtualToplevel|TIMER:TIMER1|Add1~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~37_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][27]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~50\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~38\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][27]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][27]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~50\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~37_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~38\); + +-- Location: MLABCELL_X18_Y7_N57 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~10_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~q\))) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27))) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(27), + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][27]~q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~10_combout\); + +-- Location: FF_X18_Y7_N58 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~q\); + +-- Location: FF_X19_Y7_N23 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~37_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][27]~q\); + +-- Location: LABCELL_X19_Y7_N24 +\myVirtualToplevel|TIMER:TIMER1|Add1~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~17_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][28]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~38\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~18\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][28]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][28]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~38\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~17_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~18\); + +-- Location: LABCELL_X19_Y7_N57 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][28]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(28), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~5_combout\); + +-- Location: FF_X19_Y7_N59 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~q\); + +-- Location: FF_X19_Y7_N26 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~17_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][28]~q\); + +-- Location: LABCELL_X19_Y7_N27 +\myVirtualToplevel|TIMER:TIMER1|Add1~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~21_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][29]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~18\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~22\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][29]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][29]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~18\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~21_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~22\); + +-- Location: MLABCELL_X18_Y7_N3 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(29) & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(29) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][29]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(29), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~6_combout\); + +-- Location: FF_X18_Y7_N4 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~q\); + +-- Location: FF_X19_Y7_N29 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~21_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][29]~q\); + +-- Location: LABCELL_X19_Y7_N30 +\myVirtualToplevel|TIMER:TIMER1|Add1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~1_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][30]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~22\ )) +-- \myVirtualToplevel|TIMER:TIMER1|Add1~2\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][30]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][30]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~22\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~1_sumout\, + cout => \myVirtualToplevel|TIMER:TIMER1|Add1~2\); + +-- Location: LABCELL_X19_Y7_N54 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][30]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(30), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~1_combout\); + +-- Location: FF_X19_Y7_N56 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~q\); + +-- Location: FF_X19_Y7_N32 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~1_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][30]~q\); + +-- Location: LABCELL_X19_Y7_N33 +\myVirtualToplevel|TIMER:TIMER1|Add1~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Add1~5_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][31]~q\, + cin => \myVirtualToplevel|TIMER:TIMER1|Add1~2\, + sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~5_sumout\); + +-- Location: MLABCELL_X18_Y7_N42 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31) & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) # +-- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # +-- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][31]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(31), + combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~2_combout\); + +-- Location: FF_X18_Y7_N43 +\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~q\); + +-- Location: FF_X19_Y7_N35 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~5_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~q\); + +-- Location: LABCELL_X19_Y7_N48 +\myVirtualToplevel|TIMER:TIMER1|Equal1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal1~0_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]~q\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][30]~q\ & (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~q\ & +-- !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][30]~q\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][31]~q\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][10]~q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][9]~q\, + combout => \myVirtualToplevel|TIMER:TIMER1|Equal1~0_combout\); + +-- Location: LABCELL_X19_Y7_N45 +\myVirtualToplevel|TIMER:TIMER1|Equal1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal1~1_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][28]~q\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]~q\ & (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][23]~q\ & +-- !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][29]~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][21]~q\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][23]~q\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][29]~q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][28]~q\, + combout => \myVirtualToplevel|TIMER:TIMER1|Equal1~1_combout\); + +-- Location: LABCELL_X19_Y7_N42 +\myVirtualToplevel|TIMER:TIMER1|Equal1~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal1~2_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][22]~q\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][24]~q\ & (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][26]~q\ & +-- !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][25]~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][24]~q\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][26]~q\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][25]~q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][22]~q\, + combout => \myVirtualToplevel|TIMER:TIMER1|Equal1~2_combout\); + +-- Location: FF_X19_Y8_N46 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~41_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~q\); + +-- Location: FF_X19_Y8_N16 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~77_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~q\); + +-- Location: FF_X19_Y8_N10 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~69_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~q\); + +-- Location: LABCELL_X20_Y8_N54 +\myVirtualToplevel|TIMER:TIMER1|Equal1~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal1~3_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~q\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~q\ & (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]~q\ & +-- !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][5]~q\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][17]~q\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][4]~q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][3]~q\, + combout => \myVirtualToplevel|TIMER:TIMER1|Equal1~3_combout\); + +-- Location: LABCELL_X19_Y7_N36 +\myVirtualToplevel|TIMER:TIMER1|Equal1~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal1~4_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]~q\ & ( \myVirtualToplevel|TIMER:TIMER1|Equal1~3_combout\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][27]~q\ & +-- (\myVirtualToplevel|TIMER:TIMER1|Equal1~2_combout\ & (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]~q\ & !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][27]~q\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~2_combout\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][16]~q\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][15]~q\, + datae => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][11]~q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|Equal1~4_combout\); + +-- Location: FF_X19_Y8_N22 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~93_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~q\); + +-- Location: FF_X19_Y8_N19 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~89_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~q\); + +-- Location: FF_X19_Y8_N37 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~81_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~q\); + +-- Location: FF_X19_Y8_N40 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~105_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~q\); + +-- Location: FF_X19_Y8_N7 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~101_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~q\); + +-- Location: FF_X19_Y8_N4 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~97_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~q\); + +-- Location: LABCELL_X20_Y8_N57 +\myVirtualToplevel|TIMER:TIMER1|Equal1~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal1~5_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~q\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~q\ & (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]~q\ & +-- !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][13]~q\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][14]~q\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][2]~q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][1]~q\, + combout => \myVirtualToplevel|TIMER:TIMER1|Equal1~5_combout\); + +-- Location: FF_X19_Y8_N58 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~121_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~DUPLICATE_q\); + +-- Location: FF_X19_Y8_N25 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~113_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~q\); + +-- Location: FF_X19_Y8_N55 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~117_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~q\); + +-- Location: LABCELL_X20_Y8_N3 +\myVirtualToplevel|TIMER:TIMER1|Equal1~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal1~6_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~q\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]~q\ & (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~DUPLICATE_q\ & +-- !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][20]~q\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][19]~DUPLICATE_q\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][8]~q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][18]~q\, + combout => \myVirtualToplevel|TIMER:TIMER1|Equal1~6_combout\); + +-- Location: FF_X19_Y8_N1 +\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|Add1~85_sumout\, + asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\, + ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~q\); + +-- Location: LABCELL_X20_Y8_N6 +\myVirtualToplevel|TIMER:TIMER1|Equal1~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal1~7_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Equal1~6_combout\ & ( !\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~q\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~q\ & +-- (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~q\ & (!\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~q\ & \myVirtualToplevel|TIMER:TIMER1|Equal1~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][7]~q\, + datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][6]~q\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][12]~q\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~5_combout\, + datae => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~6_combout\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][0]~q\, + combout => \myVirtualToplevel|TIMER:TIMER1|Equal1~7_combout\); + +-- Location: LABCELL_X19_Y7_N51 +\myVirtualToplevel|TIMER:TIMER1|Equal1~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Equal1~7_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|Equal1~0_combout\ & (\myVirtualToplevel|TIMER:TIMER1|Equal1~1_combout\ & +-- \myVirtualToplevel|TIMER:TIMER1|Equal1~4_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~0_combout\, + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~1_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~4_combout\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~7_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\); + +-- Location: LABCELL_X17_Y8_N39 +\myVirtualToplevel|TIMER:TIMER1|ticks~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|ticks~0_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\ & ( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][31]~0_combout\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~8_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|ticks~0_combout\); + +-- Location: FF_X17_Y8_N41 +\myVirtualToplevel|TIMER:TIMER1|ticks[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|TIMER:TIMER1|ticks~0_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|TIMER:TIMER1|ticks\(0)); + +-- Location: FF_X12_Y11_N26 +\myVirtualToplevel|INT_ENABLE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(4)); + +-- Location: LABCELL_X16_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\); + +-- Location: FF_X31_Y18_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(20)); + +-- Location: FF_X31_Y18_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(23)); + +-- Location: LABCELL_X31_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(20)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(20)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001000010010000000010010000100110010000100100000000100100001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~9_combout\); + +-- Location: FF_X31_Y18_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(18)); + +-- Location: FF_X31_Y18_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(19)); + +-- Location: LABCELL_X31_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(19) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(19) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000001010101000000000101001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~10_combout\); + +-- Location: FF_X31_Y18_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(22), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(22)); + +-- Location: FF_X31_Y18_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(21), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(21)); + +-- Location: LABCELL_X31_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(21))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(21) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(21))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(21))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(22) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(21))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000000000001010000000000000000010100000000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~11_combout\); + +-- Location: FF_X32_Y20_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(2)); + +-- Location: LABCELL_X32_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[3]~feeder_combout\); + +-- Location: FF_X32_Y20_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[3]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(3)); + +-- Location: FF_X32_Y20_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(4)); + +-- Location: LABCELL_X32_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(4) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(3)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(3)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010010100000000101001010000000000000000101001010000000010100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~1_combout\); + +-- Location: FF_X32_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(5)); + +-- Location: LABCELL_X32_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[0]~feeder_combout\); + +-- Location: FF_X32_Y20_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[0]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(0)); + +-- Location: FF_X32_Y20_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(1)); + +-- Location: LABCELL_X32_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(1) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(1) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~0_combout\); + +-- Location: LABCELL_X32_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(5) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(5) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100000000000000000001000000000000100000000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~2_combout\); + +-- Location: FF_X31_Y18_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(13)); + +-- Location: FF_X31_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(8)); + +-- Location: FF_X31_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(12)); + +-- Location: FF_X31_Y18_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(14)); + +-- Location: LABCELL_X31_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(14) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(12)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(12)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010010100000000101001010000000000000000101001010000000010100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~7_combout\); + +-- Location: FF_X32_Y20_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(6)); + +-- Location: FF_X32_Y20_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(7)); + +-- Location: LABCELL_X32_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(6) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(6) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(7)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(6) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(6) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(7)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000000010100000101001010000010100000000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~6_combout\); + +-- Location: LABCELL_X31_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(13) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(8) & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(13) & (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(8) & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(13) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(8) & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(8) & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001000000000000000010000000000000000100000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~8_combout\); + +-- Location: LABCELL_X31_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[11]~feeder_combout\); + +-- Location: FF_X31_Y18_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[11]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(11)); + +-- Location: FF_X31_Y18_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(16)); + +-- Location: LABCELL_X31_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[15]~feeder_combout\); + +-- Location: FF_X31_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[15]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(15)); + +-- Location: LABCELL_X31_Y18_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(16) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(16) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000110000110000000011000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~4_combout\); + +-- Location: FF_X31_Y18_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(17)); + +-- Location: FF_X31_Y18_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(9)); + +-- Location: FF_X31_Y18_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(10)); + +-- Location: LABCELL_X31_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(9)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(9)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001100000000110000110000000000000000110000110000000011000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~3_combout\); + +-- Location: LABCELL_X31_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(17) & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(11) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(17) & (!\myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(11) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100000000100000000001000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~5_combout\); + +-- Location: LABCELL_X31_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~8_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000100000000000000000000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~12_combout\); + +-- Location: LABCELL_X36_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~12_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~12_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal138~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001111111111111111100000001000000010000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inInterrupt~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~0_combout\); + +-- Location: FF_X36_Y26_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~q\); + +-- Location: LABCELL_X36_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~12_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inInterrupt~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~24_combout\); + +-- Location: FF_X36_Y26_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|INT_DONE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~24_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|INT_DONE~q\); + +-- Location: FF_X12_Y11_N35 +\myVirtualToplevel|INT_ENABLE[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(11)); + +-- Location: FF_X12_Y11_N32 +\myVirtualToplevel|INT_ENABLE[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(8)); + +-- Location: MLABCELL_X13_Y9_N12 +\myVirtualToplevel|UART1|TX_INTR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_INTR~0_combout\ = ( \myVirtualToplevel|UART1|TX_CLOCK~q\ & ( (!\myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & !\myVirtualToplevel|UART1|TX_BUFFER\(8)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000000110000001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_DATA_LOADED~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(8), + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK~q\, + combout => \myVirtualToplevel|UART1|TX_INTR~0_combout\); + +-- Location: FF_X13_Y9_N13 +\myVirtualToplevel|UART1|TX_INTR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_INTR~0_combout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + sclr => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_INTR~q\); + +-- Location: MLABCELL_X9_Y8_N24 +\myVirtualToplevel|UART0|TX_INTR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_INTR~0_combout\ = ( !\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ( (\myVirtualToplevel|UART0|TX_CLOCK~q\ & !\myVirtualToplevel|UART0|TX_BUFFER\(8)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(8), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\, + combout => \myVirtualToplevel|UART0|TX_INTR~0_combout\); + +-- Location: FF_X9_Y8_N25 +\myVirtualToplevel|UART0|TX_INTR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_INTR~0_combout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + sclr => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_INTR~q\); + +-- Location: FF_X13_Y12_N52 +\myVirtualToplevel|INT_ENABLE[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(9)); + +-- Location: FF_X12_Y12_N52 +\myVirtualToplevel|INT_ENABLE[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(10)); + +-- Location: MLABCELL_X13_Y9_N27 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~6_combout\ = ( \myVirtualToplevel|INT_ENABLE\(10) & ( ((\myVirtualToplevel|UART0|TX_INTR~q\ & \myVirtualToplevel|INT_ENABLE\(9))) # (\myVirtualToplevel|UART1|RX_INTR~q\) ) ) # ( +-- !\myVirtualToplevel|INT_ENABLE\(10) & ( (\myVirtualToplevel|UART0|TX_INTR~q\ & \myVirtualToplevel|INT_ENABLE\(9)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111101010101010111110101010101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_INTR~q\, + datad => \myVirtualToplevel|ALT_INV_INT_ENABLE\(9), + dataf => \myVirtualToplevel|ALT_INV_INT_ENABLE\(10), + combout => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~6_combout\); + +-- Location: FF_X12_Y11_N25 +\myVirtualToplevel|INT_ENABLE[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE[4]~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y11_N57 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~5_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|ticks\(0) & ( ((\myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ & \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(17))) # +-- (\myVirtualToplevel|INT_ENABLE[4]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|ticks\(0) & ( (\myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ & \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(17)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000100010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\, + datab => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(17), + datad => \myVirtualToplevel|ALT_INV_INT_ENABLE[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_ticks\(0), + combout => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~5_combout\); + +-- Location: LABCELL_X12_Y11_N18 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~7_combout\ = ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~6_combout\ & ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~5_combout\ ) ) # ( +-- !\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~6_combout\ & ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~5_combout\ ) ) # ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~6_combout\ & ( +-- !\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~5_combout\ ) ) # ( !\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~6_combout\ & ( !\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~5_combout\ & ( (!\myVirtualToplevel|INT_ENABLE\(11) & +-- (\myVirtualToplevel|INT_ENABLE\(8) & (\myVirtualToplevel|UART0|RX_INTR~q\))) # (\myVirtualToplevel|INT_ENABLE\(11) & (((\myVirtualToplevel|INT_ENABLE\(8) & \myVirtualToplevel|UART0|RX_INTR~q\)) # (\myVirtualToplevel|UART1|TX_INTR~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_INT_ENABLE\(11), + datab => \myVirtualToplevel|ALT_INV_INT_ENABLE\(8), + datac => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_TX_INTR~q\, + datae => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending~6_combout\, + dataf => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending~5_combout\, + combout => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~7_combout\); + +-- Location: FF_X12_Y11_N20 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~7_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(17)); + +-- Location: LABCELL_X12_Y11_N54 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|int~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~0_combout\ = ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|INT_DONE~q\) # (!\myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\) ) ) # ( +-- !\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|INT_DONE~q\ & \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000011111111111100001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_INT_DONE~q\, + datad => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\, + dataf => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(17), + combout => \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~0_combout\); + +-- Location: FF_X12_Y11_N56 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|int\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\); + +-- Location: LABCELL_X12_Y11_N48 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~0_combout\ = ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ & ( ((\myVirtualToplevel|TIMER:TIMER1|ticks\(0) & \myVirtualToplevel|INT_ENABLE\(4))) # (\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(4)) +-- ) ) # ( !\myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ & ( (\myVirtualToplevel|TIMER:TIMER1|ticks\(0) & \myVirtualToplevel|INT_ENABLE\(4)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_ticks\(0), + datac => \myVirtualToplevel|ALT_INV_INT_ENABLE\(4), + datad => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(4), + dataf => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\, + combout => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~0_combout\); + +-- Location: FF_X12_Y11_N49 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~0_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(4)); + +-- Location: FF_X14_Y11_N38 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|status[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(4)); + +-- Location: LABCELL_X14_Y11_N24 +\myVirtualToplevel|IO_DATA_READ_INTRCTL~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_INTRCTL~1_combout\ = ( \myVirtualToplevel|INT_ENABLE[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) # ( +-- !\myVirtualToplevel|INT_ENABLE[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(4)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(4), + dataf => \myVirtualToplevel|ALT_INV_INT_ENABLE[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|IO_DATA_READ_INTRCTL~1_combout\); + +-- Location: FF_X20_Y13_N47 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|IO_DATA_READ_INTRCTL~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(4)); + +-- Location: LABCELL_X20_Y13_N45 +\myVirtualToplevel|MEM_DATA_READ[4]~90\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[4]~90_combout\ = ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(4) & ( \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(4) & ( \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(4) & ( +-- !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( (!\myVirtualToplevel|IO_SELECT~combout\) # ((\myVirtualToplevel|INTR0_CS~combout\) # (\myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739_BDD8740\)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(4) & +-- ( !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( (!\myVirtualToplevel|IO_SELECT~combout\) # ((\myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739_BDD8740\ & !\myVirtualToplevel|INTR0_CS~combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111110101010101011111111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~90_RESYN8739_BDD8740\, + datad => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(4), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[4]~90_combout\); + +-- Location: IOIBUF_X23_Y0_N92 +\SDRAM_DQ[4]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(4), + o => \SDRAM_DQ[4]~input_o\); + +-- Location: DDIOINCELL_X23_Y0_N105 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_NEW_REG60\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[4]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM61\); + +-- Location: MLABCELL_X23_Y13_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59~feeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]~16_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59~feeder_combout\); + +-- Location: FF_X23_Y13_N28 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_NEW_REG58\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59\); + +-- Location: MLABCELL_X23_Y13_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM61\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59\ ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM61\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\) # +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM61\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000110000001111111100111111001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]_OTERM61\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]_OTERM59\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16_combout\); + +-- Location: M10K_X30_Y15_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000111100011001100001150C00950004100204218C20B6342002103004401AF7BDEF6A102855840849EC03010A000205010728018002022241000000001BE1E1E3C020424C02042088102000050581408082098E08183060C19003208719CF872AB106D7AB4A6E28F22D344BCF92D7E9F3E3F0B071F60AF", + mem_init2 => "1C5743F24E3B73B8EDD631D3BEACAF785D3B97EEB197CE802D6D38EDCEAC9C44F555F1BF1C1BBDE76996BF7933B19475E45384E2B4426AEBE7F5E0838E188AFDF28AD95FEABFFB01F55FFDA0F85C65E7CD0C1DF5F5FD83EBEDBDE7969BD7BD1FF9B36B5100B274E99DDB7C448D661F2F19F78EEBFEBF3FE579BE86CEF0E9D8AEF0CB6C37BABA6D3387587210034DDC034D971D4C07F79D85BF02393867EEDCF7F2F56EE3FDFDE90B7D5D294B67BD397D26B13B6EE97DFE62C3F783CED4E1E4CC97A2C18B38F6AB92D765A53CA329FF76A974D78AD7BC993103E88B3FBD64854BE5B1BE5B11BF3E31ED2D4AC3B0E3B9FAC8BD26AAB6B1DC3EF63A77971214DDCE", + mem_init1 => "58EB5FC75F5B55FBB26FBFE3FFCDCBDBEF65BFF7FFF27793E59D67848E362CE3305773D7BF133E7D7DFAE77BB61A6ECC87E1FC07C6D3BC3DEBA217F3766A72FA972E706077BD0D62BB1196A7E0AAFBB8B5EAD0D955F409FB0CEF2A8716F873A79146AF747C8F0B63E8ED38D3DEF6A25F5FBB969BF3CE8FD2C42308B662650B1375B5B0CEEDC7B5ACE86ED7E4CEB4B771FAEEFFC4D9A996DF7D6E56EB30BE36ED5C0F2C5E4DEF2FF6BB87BCEF4786D992B111A7983DCA04D9593F939CFE6D0D714DBA163F39F4611AB90F5C895AEAB1D96D1DDF3F7C8B59CFFC7CF718A233B4EFC3BE59C719A3F2BF0EBF1E4EB1BB7D45437ABE65F5FE93B877FEDA4DFEEF597E", + mem_init0 => "9C5162C66248F685BCA14969246B42D6B8C4EE0DEC88067B1D92FA345B52D15F59EBC373DA85B34ECAFF2EE33A2A8BBFB9E69BF793ACAF1FFFFB778A848546941FBB7AC63BF59A54F11011330C06EE8B51CCED9343AF11BCB7870E1C3873C6EDBD5E9B46A94D68D529AD1AA0D70341E0F0597AA2F5794E97DF673B3B9E5ECFA575A97A482A319DF34FFF436DBB1BB190ED63E86F6BFABBDD6A778DFFBA82C080A09A004102B4501442D8415546028C085B0AB520035C80FF2B00960000000000000000000000000016C02D805A00B400FFFFFFFFFFF9249248000000000000FEFF0003000100005C501E1E0010000200020A311104000100035C030222100001", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 4, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 4, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X20_Y13_N6 +\myVirtualToplevel|MEM_DATA_READ[4]~131\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[4]~131_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[4]~90_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(4) & (((\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))))) +-- # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16_combout\)))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[4]~90_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))) # +-- (\myVirtualToplevel|IO_DATA_READ_SD\(4)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12~portbdataout\)) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001101000100110011110100010000000011011101111100111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(4), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~90_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]~16_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[4]~131_combout\); + +-- Location: FF_X19_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[4]~131_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(4)); + +-- Location: LABCELL_X19_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(4) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(4)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\); + +-- Location: MLABCELL_X18_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~21_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~3\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~22\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~3\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~23\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~2\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~3\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~22\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~23\); + +-- Location: MLABCELL_X18_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add34~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~25_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~23\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~26\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~23\ ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~27\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~22\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~23\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~26\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~27\); + +-- Location: FF_X2_Y31_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[21]_NEW_REG1214\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[21]_OTERM1215\); + +-- Location: LABCELL_X2_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM900\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[21]_OTERM1215\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[21]_OTERM1215\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM900\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[21]_OTERM1215\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~1_combout\); + +-- Location: LABCELL_X2_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(21) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(21) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~0_combout\); + +-- Location: LABCELL_X5_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~342_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~342_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~342_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111111111000000001111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~342_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~1_combout\); + +-- Location: LABCELL_X17_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011101110000000000000000011101110000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~2_combout\); + +-- Location: LABCELL_X16_Y27_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_RESYN8961\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_RESYN8961_BDD8962\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_RESYN8961_BDD8962\); + +-- Location: LABCELL_X16_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_RESYN8961_BDD8962\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000011111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~4_RESYN8961_BDD8962\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_combout\); + +-- Location: LABCELL_X17_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ $ ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~81_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~81_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000000000101010111000111110001111100001111010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~81_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~7_combout\); + +-- Location: LABCELL_X14_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000110011001100000010101010101000001000100010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~5_combout\); + +-- Location: MLABCELL_X18_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_RESYN8629\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_RESYN8629_BDD8630\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~6_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~6_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~6_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~6_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111111101111101011111010111111101111000000001010111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~6_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_RESYN8629_BDD8630\); + +-- Location: LABCELL_X17_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_RESYN8629_BDD8630\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~7_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_RESYN8629_BDD8630\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110000001000001111000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~8_RESYN8629_BDD8630\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_combout\); + +-- Location: LABCELL_X16_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000011110000000000011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~5_combout\); + +-- Location: LABCELL_X17_Y22_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100000011111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~0_combout\); + +-- Location: MLABCELL_X18_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111101011010010110100101101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~1_combout\); + +-- Location: MLABCELL_X18_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100001111000011110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~2_combout\); + +-- Location: LABCELL_X17_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~9_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~7_combout\); + +-- Location: LABCELL_X17_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\)))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) +-- # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\)))) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\)))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011010001100101011110001010100110111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~9_combout\); + +-- Location: MLABCELL_X18_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~9_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\))) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010111100001010000001011111000010100101000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~8_combout\); + +-- Location: MLABCELL_X18_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~8_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001111000000111100111100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~9_combout\); + +-- Location: MLABCELL_X18_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~2_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000110100000000000011000000000000001100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~3_combout\); + +-- Location: LABCELL_X17_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector984~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~5_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~5_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111010111110101111101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~4_combout\); + +-- Location: LABCELL_X16_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add34~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111111111111111111111111110000111100011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~3_combout\); + +-- Location: FF_X16_Y25_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[21]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[21]~DUPLICATE_q\); + +-- Location: FF_X19_Y14_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[21]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~5_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[21]~DUPLICATE_q\); + +-- Location: FF_X16_Y25_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(21)); + +-- Location: LABCELL_X16_Y25_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[21]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(21) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[21]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\); + +-- Location: FF_X19_Y17_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(21)); + +-- Location: FF_X20_Y17_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(21)); + +-- Location: LABCELL_X19_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(21)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\); + +-- Location: LABCELL_X7_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[21]_NEW3153\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[21]_OTERM3154\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(21) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[21]_OTERM3154\); + +-- Location: FF_X7_Y22_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[21]_OTERM3154\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(21)); + +-- Location: LABCELL_X7_Y22_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[21]_NEW3089\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[21]_OTERM3090\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(21) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[21]_OTERM3090\); + +-- Location: FF_X7_Y22_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[21]_OTERM3090\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(21)); + +-- Location: LABCELL_X12_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[21]_NEW3025\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[21]_OTERM3026\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[21]_OTERM3026\); + +-- Location: FF_X12_Y24_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[21]_OTERM3026\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(21)); + +-- Location: LABCELL_X7_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[21]_NEW2961\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[21]_OTERM2962\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[21]_OTERM2962\); + +-- Location: FF_X7_Y22_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[21]_OTERM2962\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(21)); + +-- Location: LABCELL_X7_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux21~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(21) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(21))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(21) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(21))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(21) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(21))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(21)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100111111000001010011000011110101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~0_combout\); + +-- Location: MLABCELL_X9_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[21]_NEW2705\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[21]_OTERM2706\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[21]_OTERM2706\); + +-- Location: FF_X9_Y23_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[21]_OTERM2706\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(21)); + +-- Location: MLABCELL_X9_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[21]_NEW2897\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[21]_OTERM2898\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[21]_OTERM2898\); + +-- Location: FF_X9_Y23_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[21]_OTERM2898\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(21)); + +-- Location: MLABCELL_X9_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[21]_NEW2833\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[21]_OTERM2834\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(21) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[21]_OTERM2834\); + +-- Location: FF_X9_Y23_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[21]_OTERM2834\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(21)); + +-- Location: MLABCELL_X9_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[21]_NEW2769\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[21]_OTERM2770\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(21) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[21]_OTERM2770\); + +-- Location: FF_X9_Y23_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[21]_OTERM2770\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(21)); + +-- Location: MLABCELL_X9_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux21~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(21) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(21) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(21) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(21) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~1_combout\); + +-- Location: LABCELL_X7_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\); + +-- Location: LABCELL_X10_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector13~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector13~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111110101010101011111010101010101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector13~0_combout\); + +-- Location: LABCELL_X10_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector271~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector271~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector13~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector13~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000000001011111010100111111001111110000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector13~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector271~0_combout\); + +-- Location: FF_X10_Y18_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_NEW_REG919\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector271~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM920\); + +-- Location: LABCELL_X10_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM918\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM920\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM918\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM920\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM918\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM920\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111101011111010100001010000010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]_OTERM918\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]_OTERM920\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\); + +-- Location: LABCELL_X10_Y13_N30 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]~15_combout\, + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~2_combout\); + +-- Location: FF_X10_Y13_N32 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(5)); + +-- Location: LABCELL_X10_Y13_N12 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~_wirecell_combout\ = ( !\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(5), + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~_wirecell_combout\); + +-- Location: FF_X9_Y13_N17 +\myVirtualToplevel|UART1|TX_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~29_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~_wirecell_combout\, + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(5)); + +-- Location: MLABCELL_X9_Y13_N18 +\myVirtualToplevel|UART1|Add0~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~17_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~30\ )) +-- \myVirtualToplevel|UART1|Add0~18\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(6), + cin => \myVirtualToplevel|UART1|Add0~30\, + sumout => \myVirtualToplevel|UART1|Add0~17_sumout\, + cout => \myVirtualToplevel|UART1|Add0~18\); + +-- Location: FF_X10_Y13_N58 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(6)); + +-- Location: FF_X9_Y13_N20 +\myVirtualToplevel|UART1|TX_COUNTER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~17_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(6), + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(6)); + +-- Location: MLABCELL_X9_Y13_N21 +\myVirtualToplevel|UART1|Add0~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~21_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~18\ )) +-- \myVirtualToplevel|UART1|Add0~22\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(7), + cin => \myVirtualToplevel|UART1|Add0~18\, + sumout => \myVirtualToplevel|UART1|Add0~21_sumout\, + cout => \myVirtualToplevel|UART1|Add0~22\); + +-- Location: FF_X10_Y13_N25 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(7)); + +-- Location: FF_X9_Y13_N23 +\myVirtualToplevel|UART1|TX_COUNTER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~21_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(7), + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(7)); + +-- Location: MLABCELL_X9_Y13_N24 +\myVirtualToplevel|UART1|Add0~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~57_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~22\ )) +-- \myVirtualToplevel|UART1|Add0~58\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(8), + cin => \myVirtualToplevel|UART1|Add0~22\, + sumout => \myVirtualToplevel|UART1|Add0~57_sumout\, + cout => \myVirtualToplevel|UART1|Add0~58\); + +-- Location: FF_X10_Y13_N47 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(8)); + +-- Location: FF_X9_Y13_N26 +\myVirtualToplevel|UART1|TX_COUNTER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~57_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(8), + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(8)); + +-- Location: MLABCELL_X9_Y13_N27 +\myVirtualToplevel|UART1|Add0~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~25_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~58\ )) +-- \myVirtualToplevel|UART1|Add0~26\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(9), + cin => \myVirtualToplevel|UART1|Add0~58\, + sumout => \myVirtualToplevel|UART1|Add0~25_sumout\, + cout => \myVirtualToplevel|UART1|Add0~26\); + +-- Location: FF_X10_Y13_N28 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(9)); + +-- Location: FF_X9_Y13_N29 +\myVirtualToplevel|UART1|TX_COUNTER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~25_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(9), + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(9)); + +-- Location: MLABCELL_X9_Y13_N54 +\myVirtualToplevel|UART1|Equal0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal0~1_combout\ = ( !\myVirtualToplevel|UART1|TX_COUNTER\(5) & ( (!\myVirtualToplevel|UART1|TX_COUNTER\(9) & (!\myVirtualToplevel|UART1|TX_COUNTER\(6) & !\myVirtualToplevel|UART1|TX_COUNTER\(7))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(9), + datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(6), + datad => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(7), + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(5), + combout => \myVirtualToplevel|UART1|Equal0~1_combout\); + +-- Location: MLABCELL_X9_Y13_N30 +\myVirtualToplevel|UART1|Add0~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~13_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~26\ )) +-- \myVirtualToplevel|UART1|Add0~14\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(10), + cin => \myVirtualToplevel|UART1|Add0~26\, + sumout => \myVirtualToplevel|UART1|Add0~13_sumout\, + cout => \myVirtualToplevel|UART1|Add0~14\); + +-- Location: LABCELL_X10_Y13_N51 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(26), + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~1_combout\); + +-- Location: FF_X10_Y13_N53 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(10)); + +-- Location: LABCELL_X10_Y13_N54 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~_wirecell\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~_wirecell_combout\ = ( !\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(10), + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~_wirecell_combout\); + +-- Location: FF_X9_Y13_N32 +\myVirtualToplevel|UART1|TX_COUNTER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~13_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~_wirecell_combout\, + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(10)); + +-- Location: MLABCELL_X9_Y13_N33 +\myVirtualToplevel|UART1|Add0~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~9_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~14\ )) +-- \myVirtualToplevel|UART1|Add0~10\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(11), + cin => \myVirtualToplevel|UART1|Add0~14\, + sumout => \myVirtualToplevel|UART1|Add0~9_sumout\, + cout => \myVirtualToplevel|UART1|Add0~10\); + +-- Location: FF_X10_Y13_N50 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(11)); + +-- Location: FF_X9_Y13_N35 +\myVirtualToplevel|UART1|TX_COUNTER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~9_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(11), + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(11)); + +-- Location: MLABCELL_X9_Y13_N36 +\myVirtualToplevel|UART1|Add0~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~5_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~10\ )) +-- \myVirtualToplevel|UART1|Add0~6\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(12), + cin => \myVirtualToplevel|UART1|Add0~10\, + sumout => \myVirtualToplevel|UART1|Add0~5_sumout\, + cout => \myVirtualToplevel|UART1|Add0~6\); + +-- Location: LABCELL_X10_Y13_N21 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(28), + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[12]~feeder_combout\); + +-- Location: FF_X10_Y13_N23 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[12]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(12)); + +-- Location: FF_X9_Y13_N38 +\myVirtualToplevel|UART1|TX_COUNTER[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~5_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(12), + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(12)); + +-- Location: MLABCELL_X9_Y13_N39 +\myVirtualToplevel|UART1|Add0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~1_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~6\ )) +-- \myVirtualToplevel|UART1|Add0~2\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(13), + cin => \myVirtualToplevel|UART1|Add0~6\, + sumout => \myVirtualToplevel|UART1|Add0~1_sumout\, + cout => \myVirtualToplevel|UART1|Add0~2\); + +-- Location: FF_X10_Y13_N20 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(29), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(13)); + +-- Location: FF_X9_Y13_N41 +\myVirtualToplevel|UART1|TX_COUNTER[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~1_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(13), + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(13)); + +-- Location: MLABCELL_X9_Y13_N42 +\myVirtualToplevel|UART1|Add0~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~41_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(14) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~2\ )) +-- \myVirtualToplevel|UART1|Add0~42\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(14) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(14), + cin => \myVirtualToplevel|UART1|Add0~2\, + sumout => \myVirtualToplevel|UART1|Add0~41_sumout\, + cout => \myVirtualToplevel|UART1|Add0~42\); + +-- Location: LABCELL_X10_Y13_N36 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(30), + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[14]~feeder_combout\); + +-- Location: FF_X10_Y13_N37 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[14]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(14)); + +-- Location: FF_X9_Y13_N44 +\myVirtualToplevel|UART1|TX_COUNTER[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~41_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(14), + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(14)); + +-- Location: MLABCELL_X9_Y13_N45 +\myVirtualToplevel|UART1|Add0~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add0~45_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(15) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(15), + cin => \myVirtualToplevel|UART1|Add0~42\, + sumout => \myVirtualToplevel|UART1|Add0~45_sumout\); + +-- Location: LABCELL_X10_Y13_N39 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(31), + combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[15]~feeder_combout\); + +-- Location: FF_X10_Y13_N41 +\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[15]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(15)); + +-- Location: FF_X9_Y13_N47 +\myVirtualToplevel|UART1|TX_COUNTER[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add0~45_sumout\, + asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(15), + sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_COUNTER\(15)); + +-- Location: MLABCELL_X9_Y13_N57 +\myVirtualToplevel|UART1|Equal0~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal0~2_combout\ = ( !\myVirtualToplevel|UART1|TX_COUNTER\(14) & ( (!\myVirtualToplevel|UART1|TX_COUNTER\(3) & (!\myVirtualToplevel|UART1|TX_COUNTER\(4) & !\myVirtualToplevel|UART1|TX_COUNTER\(15))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(3), + datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(4), + datad => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(15), + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(14), + combout => \myVirtualToplevel|UART1|Equal0~2_combout\); + +-- Location: MLABCELL_X9_Y13_N48 +\myVirtualToplevel|UART1|Equal0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal0~0_combout\ = ( !\myVirtualToplevel|UART1|TX_COUNTER\(10) & ( (!\myVirtualToplevel|UART1|TX_COUNTER\(13) & (!\myVirtualToplevel|UART1|TX_COUNTER\(11) & !\myVirtualToplevel|UART1|TX_COUNTER\(12))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(13), + datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(11), + datad => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(12), + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(10), + combout => \myVirtualToplevel|UART1|Equal0~0_combout\); + +-- Location: MLABCELL_X9_Y13_N51 +\myVirtualToplevel|UART1|Equal0~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal0~3_combout\ = ( !\myVirtualToplevel|UART1|TX_COUNTER\(8) & ( (!\myVirtualToplevel|UART1|TX_COUNTER\(1) & (!\myVirtualToplevel|UART1|TX_COUNTER\(2) & !\myVirtualToplevel|UART1|TX_COUNTER\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(1), + datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(2), + datad => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(0), + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(8), + combout => \myVirtualToplevel|UART1|Equal0~3_combout\); + +-- Location: LABCELL_X10_Y13_N15 +\myVirtualToplevel|UART1|Equal0~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal0~4_combout\ = ( \myVirtualToplevel|UART1|Equal0~3_combout\ & ( (\myVirtualToplevel|UART1|Equal0~1_combout\ & (\myVirtualToplevel|UART1|Equal0~2_combout\ & \myVirtualToplevel|UART1|Equal0~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000001000000010000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_Equal0~1_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_Equal0~2_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Equal0~0_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Equal0~3_combout\, + combout => \myVirtualToplevel|UART1|Equal0~4_combout\); + +-- Location: MLABCELL_X13_Y9_N18 +\myVirtualToplevel|UART1|TX_CLOCK~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_CLOCK~0_combout\ = ( \myVirtualToplevel|UART1|TX_STATE~q\ & ( \myVirtualToplevel|UART1|Equal0~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_Equal0~4_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + combout => \myVirtualToplevel|UART1|TX_CLOCK~0_combout\); + +-- Location: FF_X13_Y9_N19 +\myVirtualToplevel|UART1|TX_CLOCK\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_CLOCK~0_combout\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_CLOCK~q\); + +-- Location: MLABCELL_X13_Y9_N57 +\myVirtualToplevel|UART1|TX_BUFFER[8]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_BUFFER[8]~1_combout\ = ( \myVirtualToplevel|UART1|TX_RESET~q\ & ( \myVirtualToplevel|UART1|TX_CLOCK~q\ & ( (!\myVirtualToplevel|UART1|TX_ENABLE~q\ & ((\myVirtualToplevel|UART1|TX_DATA_LOADED~q\) # +-- (\myVirtualToplevel|UART1|TX_STATE~q\))) ) ) ) # ( \myVirtualToplevel|UART1|TX_RESET~q\ & ( !\myVirtualToplevel|UART1|TX_CLOCK~q\ & ( (!\myVirtualToplevel|UART1|TX_STATE~q\ & (\myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & +-- !\myVirtualToplevel|UART1|TX_ENABLE~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001000000010000000000000000000000111000001110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + datab => \myVirtualToplevel|UART1|ALT_INV_TX_DATA_LOADED~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + datae => \myVirtualToplevel|UART1|ALT_INV_TX_RESET~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK~q\, + combout => \myVirtualToplevel|UART1|TX_BUFFER[8]~1_combout\); + +-- Location: FF_X12_Y7_N59 +\myVirtualToplevel|UART1|TX_BUFFER[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_BUFFER[16]~9_combout\, + ena => \myVirtualToplevel|UART1|TX_BUFFER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_BUFFER\(16)); + +-- Location: LABCELL_X12_Y7_N54 +\myVirtualToplevel|UART1|TX_BUFFER~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_BUFFER~8_combout\ = ( \myVirtualToplevel|UART1|TX_BUFFER\(16) ) # ( !\myVirtualToplevel|UART1|TX_BUFFER\(16) & ( !\myVirtualToplevel|UART1|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(16), + combout => \myVirtualToplevel|UART1|TX_BUFFER~8_combout\); + +-- Location: FF_X12_Y7_N55 +\myVirtualToplevel|UART1|TX_BUFFER[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_BUFFER~8_combout\, + ena => \myVirtualToplevel|UART1|TX_BUFFER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_BUFFER\(15)); + +-- Location: LABCELL_X12_Y7_N51 +\myVirtualToplevel|UART1|TX_BUFFER~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_BUFFER~7_combout\ = ( \myVirtualToplevel|UART1|TX_BUFFER\(15) ) # ( !\myVirtualToplevel|UART1|TX_BUFFER\(15) & ( !\myVirtualToplevel|UART1|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(15), + combout => \myVirtualToplevel|UART1|TX_BUFFER~7_combout\); + +-- Location: FF_X12_Y7_N53 +\myVirtualToplevel|UART1|TX_BUFFER[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_BUFFER~7_combout\, + ena => \myVirtualToplevel|UART1|TX_BUFFER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_BUFFER\(14)); + +-- Location: LABCELL_X12_Y7_N48 +\myVirtualToplevel|UART1|TX_BUFFER~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_BUFFER~6_combout\ = (!\myVirtualToplevel|UART1|TX_STATE~q\) # (\myVirtualToplevel|UART1|TX_BUFFER\(14)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111111001111110011111100111111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(14), + combout => \myVirtualToplevel|UART1|TX_BUFFER~6_combout\); + +-- Location: FF_X12_Y7_N50 +\myVirtualToplevel|UART1|TX_BUFFER[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_BUFFER~6_combout\, + ena => \myVirtualToplevel|UART1|TX_BUFFER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_BUFFER\(13)); + +-- Location: LABCELL_X12_Y7_N6 +\myVirtualToplevel|UART1|TX_BUFFER~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_BUFFER~5_combout\ = ( \myVirtualToplevel|UART1|TX_BUFFER\(13) ) # ( !\myVirtualToplevel|UART1|TX_BUFFER\(13) & ( !\myVirtualToplevel|UART1|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(13), + combout => \myVirtualToplevel|UART1|TX_BUFFER~5_combout\); + +-- Location: FF_X12_Y7_N8 +\myVirtualToplevel|UART1|TX_BUFFER[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_BUFFER~5_combout\, + ena => \myVirtualToplevel|UART1|TX_BUFFER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_BUFFER\(12)); + +-- Location: LABCELL_X12_Y7_N9 +\myVirtualToplevel|UART1|TX_BUFFER~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_BUFFER~4_combout\ = (!\myVirtualToplevel|UART1|TX_STATE~q\) # (\myVirtualToplevel|UART1|TX_BUFFER\(12)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111111001111110011111100111111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(12), + combout => \myVirtualToplevel|UART1|TX_BUFFER~4_combout\); + +-- Location: FF_X12_Y7_N11 +\myVirtualToplevel|UART1|TX_BUFFER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_BUFFER~4_combout\, + ena => \myVirtualToplevel|UART1|TX_BUFFER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_BUFFER\(11)); + +-- Location: LABCELL_X12_Y7_N42 +\myVirtualToplevel|UART1|TX_BUFFER~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_BUFFER~3_combout\ = ( \myVirtualToplevel|UART1|TX_STATE~q\ & ( \myVirtualToplevel|UART1|TX_BUFFER\(11) ) ) # ( !\myVirtualToplevel|UART1|TX_STATE~q\ & ( \myVirtualToplevel|UART1|TX_BUFFER\(11) ) ) # ( +-- !\myVirtualToplevel|UART1|TX_STATE~q\ & ( !\myVirtualToplevel|UART1|TX_BUFFER\(11) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(11), + combout => \myVirtualToplevel|UART1|TX_BUFFER~3_combout\); + +-- Location: FF_X12_Y7_N44 +\myVirtualToplevel|UART1|TX_BUFFER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_BUFFER~3_combout\, + ena => \myVirtualToplevel|UART1|TX_BUFFER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_BUFFER\(10)); + +-- Location: LABCELL_X12_Y7_N15 +\myVirtualToplevel|UART1|TX_BUFFER~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_BUFFER~2_combout\ = (!\myVirtualToplevel|UART1|TX_STATE~q\) # (\myVirtualToplevel|UART1|TX_BUFFER\(10)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111111001111110011111100111111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(10), + combout => \myVirtualToplevel|UART1|TX_BUFFER~2_combout\); + +-- Location: FF_X12_Y7_N17 +\myVirtualToplevel|UART1|TX_BUFFER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_BUFFER~2_combout\, + ena => \myVirtualToplevel|UART1|TX_BUFFER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_BUFFER\(9)); + +-- Location: LABCELL_X12_Y7_N12 +\myVirtualToplevel|UART1|TX_BUFFER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_BUFFER~0_combout\ = ( \myVirtualToplevel|UART1|TX_BUFFER\(9) ) # ( !\myVirtualToplevel|UART1|TX_BUFFER\(9) & ( !\myVirtualToplevel|UART1|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(9), + combout => \myVirtualToplevel|UART1|TX_BUFFER~0_combout\); + +-- Location: FF_X12_Y7_N13 +\myVirtualToplevel|UART1|TX_BUFFER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_BUFFER~0_combout\, + ena => \myVirtualToplevel|UART1|TX_BUFFER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_BUFFER\(8)); + +-- Location: MLABCELL_X13_Y9_N36 +\myVirtualToplevel|UART1|TX_STATE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_STATE~0_combout\ = ( \myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & ( (!\myVirtualToplevel|UART1|TX_ENABLE~q\ & (((!\myVirtualToplevel|UART1|TX_CLOCK~q\) # (!\myVirtualToplevel|UART1|TX_STATE~q\)) # +-- (\myVirtualToplevel|UART1|TX_BUFFER\(8)))) # (\myVirtualToplevel|UART1|TX_ENABLE~q\ & (((\myVirtualToplevel|UART1|TX_STATE~q\)))) ) ) # ( !\myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & ( (\myVirtualToplevel|UART1|TX_STATE~q\ & +-- (((!\myVirtualToplevel|UART1|TX_CLOCK~q\) # (\myVirtualToplevel|UART1|TX_ENABLE~q\)) # (\myVirtualToplevel|UART1|TX_BUFFER\(8)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110111000000001111011111001100111101111100110011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(8), + datab => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_DATA_LOADED~q\, + combout => \myVirtualToplevel|UART1|TX_STATE~0_combout\); + +-- Location: FF_X13_Y9_N38 +\myVirtualToplevel|UART1|TX_STATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_STATE~0_combout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_STATE~q\); + +-- Location: MLABCELL_X13_Y9_N42 +\myVirtualToplevel|UART1|TX_DATA_LOADED~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_DATA_LOADED~0_combout\ = ( !\myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\ & ( ((!\myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & (!\myVirtualToplevel|UART1|Equal5~4_combout\)) # (\myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & +-- (((\myVirtualToplevel|UART1|TX_STATE~q\))))) ) ) # ( \myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\ & ( (!\myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & (\myVirtualToplevel|UART1_CS~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & +-- (\myVirtualToplevel|UART1|Equal7~0_combout\)))) # (\myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & ((((\myVirtualToplevel|UART1|TX_STATE~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "1100000011000000000000000000010011110011111100110011001100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_TX_DATA_LOADED~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\, + datae => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE_FIFO~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + datag => \myVirtualToplevel|UART1|ALT_INV_Equal5~4_combout\, + combout => \myVirtualToplevel|UART1|TX_DATA_LOADED~0_combout\); + +-- Location: FF_X13_Y9_N44 +\myVirtualToplevel|UART1|TX_DATA_LOADED\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_DATA_LOADED~0_combout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_DATA_LOADED~q\); + +-- Location: MLABCELL_X13_Y9_N48 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\ = ( !\myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & ( (!\myVirtualToplevel|UART1|TX_ENABLE~q\ & (!\myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\ & !\myVirtualToplevel|UART1|Equal5~4_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE_FIFO~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_Equal5~4_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_DATA_LOADED~q\, + combout => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\); + +-- Location: FF_X13_Y8_N46 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add8~5_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6)); + +-- Location: FF_X13_Y8_N47 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add8~5_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\); + +-- Location: FF_X13_Y8_N44 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add8~17_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5]~DUPLICATE_q\); + +-- Location: FF_X13_Y8_N38 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add8~13_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3]~DUPLICATE_q\); + +-- Location: FF_X13_Y8_N35 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add8~21_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2]~DUPLICATE_q\); + +-- Location: FF_X13_Y8_N32 +\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|Add8~1_sumout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1]~DUPLICATE_q\); + +-- Location: MLABCELL_X13_Y8_N0 +\myVirtualToplevel|UART1|Add6~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add6~10\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[0]~DUPLICATE_q\, + cin => GND, + cout => \myVirtualToplevel|UART1|Add6~10\); + +-- Location: MLABCELL_X13_Y8_N3 +\myVirtualToplevel|UART1|Add6~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add6~13_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add6~10\ )) +-- \myVirtualToplevel|UART1|Add6~14\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add6~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[1]~DUPLICATE_q\, + cin => \myVirtualToplevel|UART1|Add6~10\, + sumout => \myVirtualToplevel|UART1|Add6~13_sumout\, + cout => \myVirtualToplevel|UART1|Add6~14\); + +-- Location: MLABCELL_X13_Y8_N6 +\myVirtualToplevel|UART1|Add6~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add6~5_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add6~14\ )) +-- \myVirtualToplevel|UART1|Add6~6\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add6~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[2]~DUPLICATE_q\, + cin => \myVirtualToplevel|UART1|Add6~14\, + sumout => \myVirtualToplevel|UART1|Add6~5_sumout\, + cout => \myVirtualToplevel|UART1|Add6~6\); + +-- Location: MLABCELL_X13_Y8_N9 +\myVirtualToplevel|UART1|Add6~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add6~17_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add6~6\ )) +-- \myVirtualToplevel|UART1|Add6~18\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add6~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|UART1|Add6~6\, + sumout => \myVirtualToplevel|UART1|Add6~17_sumout\, + cout => \myVirtualToplevel|UART1|Add6~18\); + +-- Location: MLABCELL_X13_Y8_N12 +\myVirtualToplevel|UART1|Add6~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add6~21_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add6~18\ )) +-- \myVirtualToplevel|UART1|Add6~22\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add6~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|UART1|Add6~18\, + sumout => \myVirtualToplevel|UART1|Add6~21_sumout\, + cout => \myVirtualToplevel|UART1|Add6~22\); + +-- Location: MLABCELL_X13_Y8_N15 +\myVirtualToplevel|UART1|Add6~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add6~25_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add6~22\ )) +-- \myVirtualToplevel|UART1|Add6~26\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add6~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|UART1|Add6~22\, + sumout => \myVirtualToplevel|UART1|Add6~25_sumout\, + cout => \myVirtualToplevel|UART1|Add6~26\); + +-- Location: MLABCELL_X13_Y8_N18 +\myVirtualToplevel|UART1|Add6~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add6~29_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add6~26\ )) +-- \myVirtualToplevel|UART1|Add6~30\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add6~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|UART1|Add6~26\, + sumout => \myVirtualToplevel|UART1|Add6~29_sumout\, + cout => \myVirtualToplevel|UART1|Add6~30\); + +-- Location: LABCELL_X14_Y8_N48 +\myVirtualToplevel|UART1|Equal6~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal6~3_combout\ = ( \myVirtualToplevel|UART1|Add6~25_sumout\ & ( (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6) $ (\myVirtualToplevel|UART1|Add6~29_sumout\))) ) ) # ( +-- !\myVirtualToplevel|UART1|Add6~25_sumout\ & ( (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6) $ (\myVirtualToplevel|UART1|Add6~29_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(5), + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(6), + datad => \myVirtualToplevel|UART1|ALT_INV_Add6~29_sumout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add6~25_sumout\, + combout => \myVirtualToplevel|UART1|Equal6~3_combout\); + +-- Location: MLABCELL_X13_Y8_N21 +\myVirtualToplevel|UART1|Add6~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add6~1_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add6~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(7), + cin => \myVirtualToplevel|UART1|Add6~30\, + sumout => \myVirtualToplevel|UART1|Add6~1_sumout\); + +-- Location: LABCELL_X14_Y8_N42 +\myVirtualToplevel|UART1|Equal6~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal6~0_combout\ = ( \myVirtualToplevel|UART1|Add6~13_sumout\ & ( (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0)))) ) ) # ( +-- !\myVirtualToplevel|UART1|Add6~13_sumout\ & ( (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0110000001100000011000000110000000000110000001100000011000000110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(0), + datab => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(1), + dataf => \myVirtualToplevel|UART1|ALT_INV_Add6~13_sumout\, + combout => \myVirtualToplevel|UART1|Equal6~0_combout\); + +-- Location: LABCELL_X14_Y8_N51 +\myVirtualToplevel|UART1|Equal6~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal6~1_combout\ = ( \myVirtualToplevel|UART1|Add6~17_sumout\ & ( (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4) $ (\myVirtualToplevel|UART1|Add6~21_sumout\))) ) ) # ( +-- !\myVirtualToplevel|UART1|Add6~17_sumout\ & ( (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4) $ (\myVirtualToplevel|UART1|Add6~21_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000001010101000000000101001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(3), + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(4), + datad => \myVirtualToplevel|UART1|ALT_INV_Add6~21_sumout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add6~17_sumout\, + combout => \myVirtualToplevel|UART1|Equal6~1_combout\); + +-- Location: LABCELL_X14_Y8_N30 +\myVirtualToplevel|UART1|Equal6~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal6~2_combout\ = ( \myVirtualToplevel|UART1|Equal6~1_combout\ & ( (\myVirtualToplevel|UART1|Equal6~0_combout\ & (!\myVirtualToplevel|UART1|Add6~5_sumout\ $ (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_Equal6~0_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Add6~5_sumout\, + datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(2), + dataf => \myVirtualToplevel|UART1|ALT_INV_Equal6~1_combout\, + combout => \myVirtualToplevel|UART1|Equal6~2_combout\); + +-- Location: LABCELL_X14_Y8_N33 +\myVirtualToplevel|UART1|Equal6~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Equal6~4_combout\ = ( \myVirtualToplevel|UART1|Equal6~2_combout\ & ( (\myVirtualToplevel|UART1|Equal6~3_combout\ & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(7) $ (\myVirtualToplevel|UART1|Add6~1_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_Equal6~3_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(7), + datad => \myVirtualToplevel|UART1|ALT_INV_Add6~1_sumout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Equal6~2_combout\, + combout => \myVirtualToplevel|UART1|Equal6~4_combout\); + +-- Location: LABCELL_X16_Y10_N48 +\myVirtualToplevel|IO_DATA_READ~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~18_combout\ = ( \myVirtualToplevel|UART0|Equal6~2_combout\ & ( \myVirtualToplevel|UART1|Add10~21_sumout\ & ( (!\myVirtualToplevel|IO_DATA_READ[17]~1_combout\) # ((!\myVirtualToplevel|IO_DATA_READ[17]~0_combout\ & +-- \myVirtualToplevel|UART1|Equal6~4_combout\)) ) ) ) # ( !\myVirtualToplevel|UART0|Equal6~2_combout\ & ( \myVirtualToplevel|UART1|Add10~21_sumout\ & ( (!\myVirtualToplevel|IO_DATA_READ[17]~0_combout\ & ((!\myVirtualToplevel|IO_DATA_READ[17]~1_combout\) # +-- (\myVirtualToplevel|UART1|Equal6~4_combout\))) ) ) ) # ( \myVirtualToplevel|UART0|Equal6~2_combout\ & ( !\myVirtualToplevel|UART1|Add10~21_sumout\ & ( (!\myVirtualToplevel|IO_DATA_READ[17]~1_combout\ & (\myVirtualToplevel|IO_DATA_READ[17]~0_combout\)) # +-- (\myVirtualToplevel|IO_DATA_READ[17]~1_combout\ & (!\myVirtualToplevel|IO_DATA_READ[17]~0_combout\ & \myVirtualToplevel|UART1|Equal6~4_combout\)) ) ) ) # ( !\myVirtualToplevel|UART0|Equal6~2_combout\ & ( !\myVirtualToplevel|UART1|Add10~21_sumout\ & ( +-- (\myVirtualToplevel|IO_DATA_READ[17]~1_combout\ & (!\myVirtualToplevel|IO_DATA_READ[17]~0_combout\ & \myVirtualToplevel|UART1|Equal6~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100001001100010011010001100100011001010111010101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~1_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~0_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Equal6~4_combout\, + datae => \myVirtualToplevel|UART0|ALT_INV_Equal6~2_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add10~21_sumout\, + combout => \myVirtualToplevel|IO_DATA_READ~18_combout\); + +-- Location: FF_X16_Y10_N50 +\myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1083\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~18_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[17]_OTERM1084\); + +-- Location: LABCELL_X16_Y10_N39 +\myVirtualToplevel|IO_DATA_READ[17]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[17]~3_combout\ = ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|INTR0_CS~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000101010100000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + combout => \myVirtualToplevel|IO_DATA_READ[17]~3_combout\); + +-- Location: FF_X16_Y10_N41 +\myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1081\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ[17]~3_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\); + +-- Location: FF_X16_Y10_N32 +\myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1077\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MILLISEC_UP_COUNTER\(17), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[17]_OTERM1078\); + +-- Location: FF_X17_Y12_N20 +\myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1075\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(17), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[17]_OTERM1076\); + +-- Location: LABCELL_X16_Y10_N30 +\myVirtualToplevel|IO_DATA_READ~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~19_combout\ = ( \myVirtualToplevel|IO_DATA_READ[17]_OTERM1078\ & ( \myVirtualToplevel|IO_DATA_READ[17]_OTERM1076\ & ( ((!\myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\ & ((\myVirtualToplevel|IO_DATA_READ[17]_OTERM1084\))) # +-- (\myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\ & (\myVirtualToplevel|IO_DATA_READ[17]_OTERM1074\))) # (\myVirtualToplevel|IO_DATA_READ[17]_OTERM1080\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ[17]_OTERM1078\ & ( +-- \myVirtualToplevel|IO_DATA_READ[17]_OTERM1076\ & ( (!\myVirtualToplevel|IO_DATA_READ[17]_OTERM1080\ & ((!\myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\ & ((\myVirtualToplevel|IO_DATA_READ[17]_OTERM1084\))) # (\myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\ +-- & (\myVirtualToplevel|IO_DATA_READ[17]_OTERM1074\)))) # (\myVirtualToplevel|IO_DATA_READ[17]_OTERM1080\ & (((\myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\)))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ[17]_OTERM1078\ & ( +-- !\myVirtualToplevel|IO_DATA_READ[17]_OTERM1076\ & ( (!\myVirtualToplevel|IO_DATA_READ[17]_OTERM1080\ & ((!\myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\ & ((\myVirtualToplevel|IO_DATA_READ[17]_OTERM1084\))) # +-- (\myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\ & (\myVirtualToplevel|IO_DATA_READ[17]_OTERM1074\)))) # (\myVirtualToplevel|IO_DATA_READ[17]_OTERM1080\ & (((!\myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\)))) ) ) ) # ( +-- !\myVirtualToplevel|IO_DATA_READ[17]_OTERM1078\ & ( !\myVirtualToplevel|IO_DATA_READ[17]_OTERM1076\ & ( (!\myVirtualToplevel|IO_DATA_READ[17]_OTERM1080\ & ((!\myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\ & +-- ((\myVirtualToplevel|IO_DATA_READ[17]_OTERM1084\))) # (\myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\ & (\myVirtualToplevel|IO_DATA_READ[17]_OTERM1074\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100001111110100010000001100011101110011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1074\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1080\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1084\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1082\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1078\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1076\, + combout => \myVirtualToplevel|IO_DATA_READ~19_combout\); + +-- Location: FF_X18_Y14_N5 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]_NEW_REG66\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]_OTERM67\); + +-- Location: MLABCELL_X18_Y14_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM7\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]_OTERM67\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM7\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]_OTERM67\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100100010001100110010001000110011011101110011001101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[17]_OTERM67\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM7\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9_combout\); + +-- Location: MLABCELL_X18_Y14_N12 +\myVirtualToplevel|MEM_DATA_READ[17]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[17]~24_combout\ = ( \myVirtualToplevel|IO_DATA_READ~19_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\) # (\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~19_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\))) # (\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & +-- (\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\)))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ~19_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\))) # (\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & (\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|IO_DATA_READ~19_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9_combout\ & ( (\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\ & (\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & +-- !\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000001101010000000011000101000000001111010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~20_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~21_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~23_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ~19_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[17]~9_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[17]~24_combout\); + +-- Location: FF_X9_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG592\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[17]~24_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM593\); + +-- Location: FF_X10_Y17_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG600\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM601\); + +-- Location: MLABCELL_X9_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM593\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM601\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM597\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM595\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM593\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM601\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM595\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM597\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM595\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM603\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM593\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM601\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM599\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM593\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM601\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM599\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001010111110100000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM603\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM599\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM595\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM597\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM593\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM601\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24_combout\); + +-- Location: MLABCELL_X9_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[1]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[1]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011001100110011001111111111001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]~24_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[1]~4_combout\); + +-- Location: MLABCELL_X28_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~382\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~382_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~382_combout\); + +-- Location: FF_X28_Y35_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~382_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE_q\); + +-- Location: FF_X28_Y35_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~383_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\); + +-- Location: LABCELL_X29_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000000000011001100011101000111011100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~14_combout\); + +-- Location: LABCELL_X29_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001000110100010101100111000010011010101111001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~4_combout\); + +-- Location: LABCELL_X26_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010101000110100001111110110000101101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~19_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\); + +-- Location: LABCELL_X20_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110101001101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~3_combout\); + +-- Location: LABCELL_X20_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~93_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~5_combout\); + +-- Location: LABCELL_X20_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~4_combout\); + +-- Location: LABCELL_X20_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~22_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~22_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000011000000001100001101010101110101110101010111010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~22_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~7_combout\); + +-- Location: LABCELL_X14_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~21_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100101010001010100011111100000000001010100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~6_combout\); + +-- Location: LABCELL_X20_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~7_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~7_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000111111110000000000001100000000001100110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~8_combout\); + +-- Location: LABCELL_X20_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001100000000001100110011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~9_combout\); + +-- Location: FF_X20_Y17_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[17]~27_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(17) $ +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE_q\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(17) $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE_q\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011101010101100110001011010001111000101101000111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[17]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~3_combout\); + +-- Location: LABCELL_X20_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100110011001111110011001100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[17]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~0_combout\); + +-- Location: LABCELL_X20_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000101010101010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~1_combout\); + +-- Location: LABCELL_X17_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111001100000011000001010000010111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~31_combout\); + +-- Location: LABCELL_X19_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~31_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\)) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~31_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~31_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000100010001101110101010101010101011000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~22_combout\); + +-- Location: LABCELL_X20_Y23_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS~22_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~22_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~10_combout\); + +-- Location: LABCELL_X17_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~9_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110111110101110111011111010110001000101000001000100010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~20_combout\); + +-- Location: LABCELL_X17_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~7_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001000000111000000101111011111110010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~8_combout\); + +-- Location: LABCELL_X17_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~8_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111010111110101111101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~21_combout\); + +-- Location: LABCELL_X20_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~21_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~21_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~10_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~21_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~21_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~21_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~21_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~21_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~21_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~21_sumout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000101010101010000011011101110100001000100010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~21_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~21_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~11_combout\); + +-- Location: LABCELL_X20_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add34~21_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add34~21_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001110111000000000000000000000000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~2_combout\); + +-- Location: FF_X2_Y31_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[17]_NEW_REG1236\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[17]_OTERM1237\); + +-- Location: LABCELL_X2_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM900\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[17]_OTERM1237\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[17]_OTERM1237\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM900\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[17]_OTERM1237\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~5_combout\); + +-- Location: LABCELL_X2_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~5_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111101010101010111110101010101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~0_combout\); + +-- Location: LABCELL_X5_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(17) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(17) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(17) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010111111111111111110000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~1_combout\); + +-- Location: LABCELL_X20_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~1_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100101010001010100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~2_combout\); + +-- Location: LABCELL_X20_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~9_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector988~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000110011110000000011001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~3_combout\); + +-- Location: FF_X20_Y23_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(17)); + +-- Location: FF_X19_Y15_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~21_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[17]~27_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(17)); + +-- Location: LABCELL_X19_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(17)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(17) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(17)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\); + +-- Location: FF_X20_Y17_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(17)); + +-- Location: LABCELL_X20_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(17)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(17)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[17]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\); + +-- Location: MLABCELL_X9_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[17]_NEW3161\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[17]_OTERM3162\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(17) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[17]_OTERM3162\); + +-- Location: FF_X9_Y21_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[17]_OTERM3162\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(17)); + +-- Location: MLABCELL_X9_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[17]_NEW3097\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[17]_OTERM3098\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(17) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[17]_OTERM3098\); + +-- Location: FF_X9_Y21_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[17]_OTERM3098\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(17)); + +-- Location: MLABCELL_X9_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[17]_NEW3033\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[17]_OTERM3034\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(17) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[17]_OTERM3034\); + +-- Location: FF_X9_Y21_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[17]_OTERM3034\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(17)); + +-- Location: MLABCELL_X9_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[17]_NEW2969\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[17]_OTERM2970\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[17]_OTERM2970\); + +-- Location: FF_X9_Y21_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[17]_OTERM2970\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(17)); + +-- Location: MLABCELL_X9_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux25~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(17)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(17)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(17)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(17))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(17)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(17), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~0_combout\); + +-- Location: MLABCELL_X9_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[17]_NEW2713\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[17]_OTERM2714\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[17]_OTERM2714\); + +-- Location: FF_X9_Y21_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[17]_OTERM2714\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(17)); + +-- Location: MLABCELL_X9_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[17]_NEW2777\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[17]_OTERM2778\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(17) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[17]_OTERM2778\); + +-- Location: FF_X9_Y21_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[17]_OTERM2778\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(17)); + +-- Location: MLABCELL_X9_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[17]_NEW2905\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[17]_OTERM2906\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[17]_OTERM2906\); + +-- Location: FF_X9_Y21_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[17]_OTERM2906\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(17)); + +-- Location: MLABCELL_X9_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[17]_NEW2841\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[17]_OTERM2842\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(17) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[17]_OTERM2842\); + +-- Location: FF_X9_Y21_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[17]_OTERM2842\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(17)); + +-- Location: MLABCELL_X9_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux25~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(17)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(17)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(17))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(17))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(17), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~1_combout\); + +-- Location: MLABCELL_X9_Y21_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux25~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux25~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux25~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux25~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~2_combout\); + +-- Location: MLABCELL_X9_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector17~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector17~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux25~2_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000001100111111110000110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector17~0_combout\); + +-- Location: MLABCELL_X9_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector275~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector275~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & +-- ((\myVirtualToplevel|MEM_DATA_READ[17]~27_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector17~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[17]~27_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector17~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux25~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector17~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux25~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~27_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector17~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector275~0_combout\); + +-- Location: FF_X9_Y18_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_NEW_REG1616\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector275~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1617\); + +-- Location: MLABCELL_X9_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1617\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1615\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1617\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1615\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101111000000001010111101010000111111110101000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]_OTERM1615\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]_OTERM1617\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\); + +-- Location: FF_X13_Y11_N23 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~21_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\); + +-- Location: FF_X13_Y11_N26 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~25_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\); + +-- Location: FF_X13_Y12_N16 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~53_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\); + +-- Location: MLABCELL_X13_Y11_N45 +\myVirtualToplevel|Equal31~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal31~3_combout\ = ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\ & (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\ & +-- !\myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|Equal31~3_combout\); + +-- Location: FF_X13_Y11_N10 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~37_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(13)); + +-- Location: MLABCELL_X13_Y11_N42 +\myVirtualToplevel|Equal31~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal31~4_combout\ = ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\ & ( (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(15) & (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(16) & !\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(13))) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(15), + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(16), + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(13), + dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\, + combout => \myVirtualToplevel|Equal31~4_combout\); + +-- Location: MLABCELL_X13_Y11_N48 +\myVirtualToplevel|Equal31~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal31~0_combout\ = ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\ & ( (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\ & (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(21) & +-- !\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(19))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(21), + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(19), + dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\, + combout => \myVirtualToplevel|Equal31~0_combout\); + +-- Location: MLABCELL_X13_Y11_N51 +\myVirtualToplevel|Equal31~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal31~1_combout\ = ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(7) & ( (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(8) & (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(9) & !\myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(8), + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(9), + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(7), + combout => \myVirtualToplevel|Equal31~1_combout\); + +-- Location: MLABCELL_X13_Y11_N57 +\myVirtualToplevel|Equal31~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal31~2_combout\ = ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\ & ( \myVirtualToplevel|Equal31~1_combout\ & ( (\myVirtualToplevel|Equal31~0_combout\ & (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\ & !\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(11)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal31~0_combout\, + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(11), + datae => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_Equal31~1_combout\, + combout => \myVirtualToplevel|Equal31~2_combout\); + +-- Location: FF_X13_Y12_N7 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~85_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(2)); + +-- Location: MLABCELL_X13_Y12_N36 +\myVirtualToplevel|Equal31~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal31~5_combout\ = ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(4) & ( (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(3) & (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(1) & !\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(3), + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(1), + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(2), + dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(4), + combout => \myVirtualToplevel|Equal31~5_combout\); + +-- Location: LABCELL_X19_Y10_N0 +\myVirtualToplevel|Add12~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add12~13_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|Add12~14\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(0), + cin => GND, + sumout => \myVirtualToplevel|Add12~13_sumout\, + cout => \myVirtualToplevel|Add12~14\); + +-- Location: FF_X19_Y10_N2 +\myVirtualToplevel|MICROSEC_DOWN_TICK[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add12~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal30~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_TICK\(0)); + +-- Location: LABCELL_X19_Y10_N3 +\myVirtualToplevel|Add12~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add12~9_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add12~14\ )) +-- \myVirtualToplevel|Add12~10\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add12~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(1), + cin => \myVirtualToplevel|Add12~14\, + sumout => \myVirtualToplevel|Add12~9_sumout\, + cout => \myVirtualToplevel|Add12~10\); + +-- Location: FF_X19_Y10_N5 +\myVirtualToplevel|MICROSEC_DOWN_TICK[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add12~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal30~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_TICK\(1)); + +-- Location: LABCELL_X19_Y10_N6 +\myVirtualToplevel|Add12~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add12~29_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add12~10\ )) +-- \myVirtualToplevel|Add12~30\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add12~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(2), + cin => \myVirtualToplevel|Add12~10\, + sumout => \myVirtualToplevel|Add12~29_sumout\, + cout => \myVirtualToplevel|Add12~30\); + +-- Location: FF_X19_Y10_N8 +\myVirtualToplevel|MICROSEC_DOWN_TICK[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add12~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal30~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_TICK\(2)); + +-- Location: LABCELL_X19_Y10_N9 +\myVirtualToplevel|Add12~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add12~25_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add12~30\ )) +-- \myVirtualToplevel|Add12~26\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add12~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(3), + cin => \myVirtualToplevel|Add12~30\, + sumout => \myVirtualToplevel|Add12~25_sumout\, + cout => \myVirtualToplevel|Add12~26\); + +-- Location: FF_X19_Y10_N10 +\myVirtualToplevel|MICROSEC_DOWN_TICK[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add12~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal30~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_TICK\(3)); + +-- Location: LABCELL_X19_Y10_N12 +\myVirtualToplevel|Add12~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add12~21_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add12~26\ )) +-- \myVirtualToplevel|Add12~22\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add12~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(4), + cin => \myVirtualToplevel|Add12~26\, + sumout => \myVirtualToplevel|Add12~21_sumout\, + cout => \myVirtualToplevel|Add12~22\); + +-- Location: FF_X19_Y10_N14 +\myVirtualToplevel|MICROSEC_DOWN_TICK[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add12~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal30~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_TICK\(4)); + +-- Location: LABCELL_X19_Y10_N15 +\myVirtualToplevel|Add12~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add12~5_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add12~22\ )) +-- \myVirtualToplevel|Add12~6\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add12~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(5), + cin => \myVirtualToplevel|Add12~22\, + sumout => \myVirtualToplevel|Add12~5_sumout\, + cout => \myVirtualToplevel|Add12~6\); + +-- Location: FF_X19_Y10_N17 +\myVirtualToplevel|MICROSEC_DOWN_TICK[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add12~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal30~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_TICK\(5)); + +-- Location: LABCELL_X19_Y10_N18 +\myVirtualToplevel|Add12~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add12~1_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add12~6\ )) +-- \myVirtualToplevel|Add12~2\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add12~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(6), + cin => \myVirtualToplevel|Add12~6\, + sumout => \myVirtualToplevel|Add12~1_sumout\, + cout => \myVirtualToplevel|Add12~2\); + +-- Location: FF_X19_Y10_N20 +\myVirtualToplevel|MICROSEC_DOWN_TICK[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add12~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal30~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_TICK\(6)); + +-- Location: LABCELL_X19_Y10_N21 +\myVirtualToplevel|Add12~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add12~17_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add12~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(7), + cin => \myVirtualToplevel|Add12~2\, + sumout => \myVirtualToplevel|Add12~17_sumout\); + +-- Location: FF_X19_Y10_N23 +\myVirtualToplevel|MICROSEC_DOWN_TICK[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add12~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|Equal30~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_TICK\(7)); + +-- Location: LABCELL_X19_Y10_N42 +\myVirtualToplevel|Equal30~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal30~0_combout\ = ( !\myVirtualToplevel|MICROSEC_DOWN_TICK\(4) & ( (!\myVirtualToplevel|MICROSEC_DOWN_TICK\(2) & (!\myVirtualToplevel|MICROSEC_DOWN_TICK\(7) & !\myVirtualToplevel|MICROSEC_DOWN_TICK\(3))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(2), + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(7), + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(3), + dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(4), + combout => \myVirtualToplevel|Equal30~0_combout\); + +-- Location: LABCELL_X19_Y10_N54 +\myVirtualToplevel|Equal30~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Equal30~1_combout\ = ( \myVirtualToplevel|MICROSEC_DOWN_TICK\(1) & ( \myVirtualToplevel|Equal30~0_combout\ & ( (\myVirtualToplevel|MICROSEC_DOWN_TICK\(0) & (\myVirtualToplevel|MICROSEC_DOWN_TICK\(5) & +-- \myVirtualToplevel|MICROSEC_DOWN_TICK\(6))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(0), + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(5), + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(6), + datae => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(1), + dataf => \myVirtualToplevel|ALT_INV_Equal30~0_combout\, + combout => \myVirtualToplevel|Equal30~1_combout\); + +-- Location: LABCELL_X14_Y11_N30 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\ = ( \myVirtualToplevel|Equal30~1_combout\ & ( (\myVirtualToplevel|Equal31~3_combout\ & (\myVirtualToplevel|Equal31~4_combout\ & (\myVirtualToplevel|Equal31~2_combout\ & +-- \myVirtualToplevel|Equal31~5_combout\))) ) ) # ( !\myVirtualToplevel|Equal30~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000010000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal31~3_combout\, + datab => \myVirtualToplevel|ALT_INV_Equal31~4_combout\, + datac => \myVirtualToplevel|ALT_INV_Equal31~2_combout\, + datad => \myVirtualToplevel|ALT_INV_Equal31~5_combout\, + dataf => \myVirtualToplevel|ALT_INV_Equal30~1_combout\, + combout => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\); + +-- Location: FF_X13_Y12_N20 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~69_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(6)); + +-- Location: FF_X13_Y12_N19 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~69_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\); + +-- Location: LABCELL_X16_Y12_N0 +\myVirtualToplevel|IO_DATA_READ~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~51_combout\ = ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\ & ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- ((\myVirtualToplevel|MILLISEC_UP_COUNTER\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|SECOND_DOWN_COUNTER\(6)))) ) ) ) # ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|MILLISEC_UP_COUNTER\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # ((\myVirtualToplevel|SECOND_DOWN_COUNTER\(6))))) ) ) ) # ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\ & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # ((\myVirtualToplevel|MILLISEC_UP_COUNTER\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (\myVirtualToplevel|SECOND_DOWN_COUNTER\(6)))) ) ) ) # ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\ & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|MILLISEC_UP_COUNTER\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|SECOND_DOWN_COUNTER\(6))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011100010011010101101000101011001111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(6), + datad => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(6), + datae => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(6), + combout => \myVirtualToplevel|IO_DATA_READ~51_combout\); + +-- Location: LABCELL_X16_Y12_N6 +\myVirtualToplevel|IO_DATA_READ~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(6) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +-- (\myVirtualToplevel|IO_DATA_READ~51_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(6) & ( (\myVirtualToplevel|IO_DATA_READ~51_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000000000000000000001010000010111000000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ~51_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(6), + combout => \myVirtualToplevel|IO_DATA_READ~52_combout\); + +-- Location: FF_X6_Y11_N37 +\myVirtualToplevel|RTC_YEAR_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[5]_OTERM1771\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER\(5)); + +-- Location: LABCELL_X6_Y11_N15 +\myVirtualToplevel|Add11~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add11~5_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add11~2\ )) +-- \myVirtualToplevel|Add11~6\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add11~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add11~2\, + sumout => \myVirtualToplevel|Add11~5_sumout\, + cout => \myVirtualToplevel|Add11~6\); + +-- Location: LABCELL_X6_Y11_N36 +\myVirtualToplevel|RTC_YEAR_COUNTER[5]_NEW1770\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER[5]_OTERM1771\ = ( \myVirtualToplevel|Add11~5_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(5))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & +-- ((!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5))))) ) ) # ( !\myVirtualToplevel|Add11~5_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(5))))) +-- # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(5), + dataf => \myVirtualToplevel|ALT_INV_Add11~5_sumout\, + combout => \myVirtualToplevel|RTC_YEAR_COUNTER[5]_OTERM1771\); + +-- Location: FF_X6_Y11_N38 +\myVirtualToplevel|RTC_YEAR_COUNTER[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[5]_OTERM1771\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER[5]~DUPLICATE_q\); + +-- Location: LABCELL_X6_Y11_N18 +\myVirtualToplevel|Add11~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add11~21_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER\(6) ) + ( GND ) + ( \myVirtualToplevel|Add11~6\ )) +-- \myVirtualToplevel|Add11~22\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER\(6) ) + ( GND ) + ( \myVirtualToplevel|Add11~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(6), + cin => \myVirtualToplevel|Add11~6\, + sumout => \myVirtualToplevel|Add11~21_sumout\, + cout => \myVirtualToplevel|Add11~22\); + +-- Location: LABCELL_X6_Y11_N39 +\myVirtualToplevel|RTC_YEAR_COUNTER[6]_NEW1762\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER[6]_OTERM1763\ = ( \myVirtualToplevel|Add11~21_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(6))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & +-- ((!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6))))) ) ) # ( !\myVirtualToplevel|Add11~21_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & +-- (((\myVirtualToplevel|RTC_YEAR_COUNTER\(6))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6), + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(6), + dataf => \myVirtualToplevel|ALT_INV_Add11~21_sumout\, + combout => \myVirtualToplevel|RTC_YEAR_COUNTER[6]_OTERM1763\); + +-- Location: FF_X6_Y11_N41 +\myVirtualToplevel|RTC_YEAR_COUNTER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[6]_OTERM1763\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER\(6)); + +-- Location: LABCELL_X14_Y10_N24 +\myVirtualToplevel|IO_DATA_READ~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~53_combout\ = ( \myVirtualToplevel|RTC_YEAR_COUNTER\(6) & ( \myVirtualToplevel|IO_DATA_READ[5]~49_combout\ & ( \myVirtualToplevel|TIMER0_CS~1_combout\ ) ) ) # ( \myVirtualToplevel|RTC_YEAR_COUNTER\(6) & ( +-- !\myVirtualToplevel|IO_DATA_READ[5]~49_combout\ & ( (\myVirtualToplevel|TIMER0_CS~1_combout\ & ((\myVirtualToplevel|IO_DATA_READ~52_combout\) # (\myVirtualToplevel|IO_DATA_READ~50_combout\))) ) ) ) # ( !\myVirtualToplevel|RTC_YEAR_COUNTER\(6) & ( +-- !\myVirtualToplevel|IO_DATA_READ[5]~49_combout\ & ( (\myVirtualToplevel|TIMER0_CS~1_combout\ & ((\myVirtualToplevel|IO_DATA_READ~52_combout\) # (\myVirtualToplevel|IO_DATA_READ~50_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000111111000000000011111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ~50_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ~52_combout\, + datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datae => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(6), + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ[5]~49_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~53_combout\); + +-- Location: LABCELL_X14_Y10_N57 +\myVirtualToplevel|IO_DATA_READ~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~54_combout\ = ( \myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ( !\myVirtualToplevel|IO_DATA_READ~53_combout\ & ( (!\myVirtualToplevel|UART1_CS~combout\ & ((!\myVirtualToplevel|IO_DATA_READ~48_combout\))) # +-- (\myVirtualToplevel|UART1_CS~combout\ & (!\myVirtualToplevel|IO_DATA_READ~47_combout\)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ( !\myVirtualToplevel|IO_DATA_READ~53_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111110100101000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ~47_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ~48_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~46_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~53_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~54_combout\); + +-- Location: MLABCELL_X13_Y6_N15 +\myVirtualToplevel|UART1|Add9~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~26_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) & ( (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6)) # (\myVirtualToplevel|UART1_CS~combout\) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) & ( +-- (!\myVirtualToplevel|UART1_CS~combout\ & \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6), + combout => \myVirtualToplevel|UART1|Add9~26_combout\); + +-- Location: LABCELL_X16_Y6_N45 +\myVirtualToplevel|UART1|Add9~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~25_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(5), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(5), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|UART1|Add9~25_combout\); + +-- Location: MLABCELL_X13_Y7_N18 +\myVirtualToplevel|UART1|Add9~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~5_sumout\ = SUM(( \myVirtualToplevel|UART1|Add9~25_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5))))) ) + ( \myVirtualToplevel|UART1|Add9~2\ )) +-- \myVirtualToplevel|UART1|Add9~6\ = CARRY(( \myVirtualToplevel|UART1|Add9~25_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5))))) ) + ( \myVirtualToplevel|UART1|Add9~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000011110111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(5), + datad => \myVirtualToplevel|UART1|ALT_INV_Add9~25_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(5), + cin => \myVirtualToplevel|UART1|Add9~2\, + sumout => \myVirtualToplevel|UART1|Add9~5_sumout\, + cout => \myVirtualToplevel|UART1|Add9~6\); + +-- Location: MLABCELL_X13_Y7_N21 +\myVirtualToplevel|UART1|Add9~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~9_sumout\ = SUM(( \myVirtualToplevel|UART1|Add9~26_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6))))) ) + ( \myVirtualToplevel|UART1|Add9~6\ )) +-- \myVirtualToplevel|UART1|Add9~10\ = CARRY(( \myVirtualToplevel|UART1|Add9~26_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6))))) # (\myVirtualToplevel|Equal4~0_combout\ & +-- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6))))) ) + ( \myVirtualToplevel|UART1|Add9~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000011110111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(6), + datad => \myVirtualToplevel|UART1|ALT_INV_Add9~26_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(6), + cin => \myVirtualToplevel|UART1|Add9~6\, + sumout => \myVirtualToplevel|UART1|Add9~9_sumout\, + cout => \myVirtualToplevel|UART1|Add9~10\); + +-- Location: LABCELL_X14_Y10_N36 +\myVirtualToplevel|IO_DATA_READ~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~55_combout\ = ( \myVirtualToplevel|UART1|Add9~9_sumout\ & ( (!\myVirtualToplevel|IO_DATA_READ~54_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- !\myVirtualToplevel|TIMER0_CS~1_combout\))) ) ) # ( !\myVirtualToplevel|UART1|Add9~9_sumout\ & ( !\myVirtualToplevel|IO_DATA_READ~54_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111010000001111111101000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ~54_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add9~9_sumout\, + combout => \myVirtualToplevel|IO_DATA_READ~55_combout\); + +-- Location: FF_X14_Y10_N37 +\myVirtualToplevel|IO_DATA_READ[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~55_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(6)); + +-- Location: FF_X19_Y13_N7 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux92~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(6)); + +-- Location: LABCELL_X19_Y13_N48 +\myVirtualToplevel|MEM_DATA_READ[6]~86_RESYN8735\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[6]~86_RESYN8735_BDD8736\ = ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(6) ) ) # ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(6), + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(6), + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[6]~86_RESYN8735_BDD8736\); + +-- Location: LABCELL_X20_Y14_N0 +\myVirtualToplevel|MEM_DATA_READ[6]~86\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[6]~86_combout\ = ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(6) & ( \myVirtualToplevel|MEM_DATA_READ[6]~86_RESYN8735_BDD8736\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(6) & ( \myVirtualToplevel|MEM_DATA_READ[6]~86_RESYN8735_BDD8736\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\) # (!\myVirtualToplevel|INTR0_CS~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(6) & ( !\myVirtualToplevel|MEM_DATA_READ[6]~86_RESYN8735_BDD8736\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\) # (\myVirtualToplevel|INTR0_CS~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(6) & ( !\myVirtualToplevel|MEM_DATA_READ[6]~86_RESYN8735_BDD8736\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((!\myVirtualToplevel|IO_SELECT~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101000111010001110100011101110111011101110100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datad => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(6), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~86_RESYN8735_BDD8736\, + combout => \myVirtualToplevel|MEM_DATA_READ[6]~86_combout\); + +-- Location: M10K_X22_Y17_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111000000000001110001150F24950E7C7851EF79EFA99216661F3236BE739AF7BDEF7B1CB830050849ED4BE71E57D39FF7976CB3DDAAA73B552015554091FFFE026A252B0852A9F90B21E0010587C1F1809397969690224C8933EF7247FE01F70AB00695AD466E27768C20094F071121E3EBC0917ABA1A6", + mem_init2 => "0E5053F8472833BEF0578DE3BE403BBE5E3BD782B8578FF42A011CA0CE208E6465F4DC3D8C19F725C8A79A3123B99074C14280E1030026EDAFE4E09AD679EA9CDA8A4046A8ADEB415456F5A0A84C6067451C1827A975D38381DC831291D22D8AFA3BC34241264CA189C35CC1AD12382D08D3AF6ADE9D2BFD469A874E70F0590E20C94C1B3A820B83966A7608AD275C3D2756154345B7A9A09B421B9241165A6570B90E63FC603C497515294A82AC38593735316FD90D2F260303C9EED4298847FCCA41228892A38075550434CC0DD11AA91453CAC3CC098101A88D389F28857DCD913C53D111A4276A0C0E83A341397890A9C2AAE6A49938509B3F93327499A6", + mem_init1 => "68292FC1D34A9D8993EB2AA332A5880DA4453BE2AD8276F3F54DD0A4AA348A23B9567317860937C51D4CB60420134A8DC644B00D80C2F671492086BA546222F20415266057BD252A811882A260AF79D215E850D9556690DB042FC8011619032091A246404E8C0B69A0ED28D19600F27F4BB3949B740C8B92F5288C1652551B1255C1B0CE4DC9A4A8682C556EA62537595B8477445909968F7D0F6A6B2816604814890CAA56BDE25EB9933A47458C9990B01192986C8D16915F2592149027095040BA343B78F4D01A193D5C874ACBB95C69FD59315FEA14CF25DE5319A030B4F5811E18C739E1F0560E331A5AA09B6C454A0AB2A5A9845198572E5A4D66AE1146", + mem_init0 => "9401404A624852C73CA1192B242163822891A61E8E880E131D163F26185090594863C2611004014EC2A820E32A2A995651400B671BE8BB1FDABA474A00C146C40A1078E63A159854701835614002ACAB5CCB6D4138AB140C8983060C1832C26EA51F9D468905A8D120B51A21BC860301904838A29F4C4E835D23390E9A53C32451881A282B18C7520001A24932393198E9E5E86961B83FDC62758CBD5A94C082A298504542B4528154CC4A5D56102C2A998AB68A135C80802A0174000000000000000000000000002E805D00AA015402FFFFFFFFFFF8000000000000000000FEFF0003000100005C500A0A0210000200020A311100000000034C030222100000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 6, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 6, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X23_Y18_N0 +\myVirtualToplevel|MEM_DATA_READ[6]~111\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[6]~111_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[6]~86_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6~portbdataout\ & +-- ((\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|IO_DATA_READ_SD\(6)))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[6]~86_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14~portbdataout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|IO_DATA_READ_SD\(6)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000001010101101010101111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]~21_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(6), + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~86_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[6]~111_combout\); + +-- Location: FF_X23_Y18_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[6]~111_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[6]~DUPLICATE_q\); + +-- Location: FF_X19_Y18_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(6)); + +-- Location: LABCELL_X19_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[6]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\); + +-- Location: MLABCELL_X13_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[6]_NEW2991\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[6]_OTERM2992\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[6]_OTERM2992\); + +-- Location: FF_X13_Y22_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[6]_OTERM2992\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(6)); + +-- Location: MLABCELL_X13_Y22_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[6]_NEW3055\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[6]_OTERM3056\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[6]_OTERM3056\); + +-- Location: FF_X13_Y22_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[6]_OTERM3056\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(6)); + +-- Location: MLABCELL_X9_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[6]_NEW3183\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[6]_OTERM3184\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[6]_OTERM3184\); + +-- Location: FF_X9_Y19_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[6]_OTERM3184\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(6)); + +-- Location: MLABCELL_X13_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[6]_NEW3119\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[6]_OTERM3120\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[6]_OTERM3120\); + +-- Location: FF_X13_Y22_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[6]_OTERM3120\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(6)); + +-- Location: LABCELL_X5_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux81~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(6))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(6))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(6)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(6)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010010101011111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~0_combout\); + +-- Location: MLABCELL_X9_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[6]_NEW2927\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[6]_OTERM2928\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[6]_OTERM2928\); + +-- Location: FF_X9_Y19_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[6]_OTERM2928\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(6)); + +-- Location: LABCELL_X10_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[6]_NEW2863\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[6]_OTERM2864\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(6))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[6]_OTERM2864\); + +-- Location: FF_X10_Y22_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[6]_OTERM2864\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(6)); + +-- Location: MLABCELL_X9_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[6]_NEW2735\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[6]_OTERM2736\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[6]_OTERM2736\); + +-- Location: FF_X9_Y19_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[6]_OTERM2736\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(6)); + +-- Location: LABCELL_X10_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[6]_NEW2799\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[6]_OTERM2800\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(6))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[6]_OTERM2800\); + +-- Location: FF_X10_Y22_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[6]_OTERM2800\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(6)); + +-- Location: MLABCELL_X9_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux81~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(6) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(6)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(6)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(6) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(6)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011000011110000000001010101001100110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~1_combout\); + +-- Location: MLABCELL_X9_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux81~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux81~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2_combout\); + +-- Location: FF_X9_Y17_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6)); + +-- Location: FF_X9_Y12_N50 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add4~13_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\, + sload => \myVirtualToplevel|Equal13~1_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_COUNTER\(6)); + +-- Location: MLABCELL_X9_Y12_N51 +\myVirtualToplevel|Add4~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add4~17_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(7) ) + ( GND ) + ( \myVirtualToplevel|Add4~14\ )) +-- \myVirtualToplevel|Add4~18\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(7) ) + ( GND ) + ( \myVirtualToplevel|Add4~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(7), + cin => \myVirtualToplevel|Add4~14\, + sumout => \myVirtualToplevel|Add4~17_sumout\, + cout => \myVirtualToplevel|Add4~18\); + +-- Location: FF_X9_Y12_N53 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add4~17_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\, + sload => \myVirtualToplevel|Equal13~1_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_COUNTER\(7)); + +-- Location: MLABCELL_X9_Y12_N54 +\myVirtualToplevel|Add4~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add4~21_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(8) ) + ( GND ) + ( \myVirtualToplevel|Add4~18\ )) +-- \myVirtualToplevel|Add4~22\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(8) ) + ( GND ) + ( \myVirtualToplevel|Add4~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(8), + cin => \myVirtualToplevel|Add4~18\, + sumout => \myVirtualToplevel|Add4~21_sumout\, + cout => \myVirtualToplevel|Add4~22\); + +-- Location: FF_X9_Y12_N55 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add4~21_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\, + sload => \myVirtualToplevel|Equal13~1_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_COUNTER\(8)); + +-- Location: FF_X9_Y12_N47 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add4~5_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\, + sload => \myVirtualToplevel|Equal13~1_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_COUNTER[5]~DUPLICATE_q\); + +-- Location: MLABCELL_X9_Y12_N18 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~0_combout\ = ( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(7) & ( (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(8) & (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(6) & +-- \myVirtualToplevel|RTC_MICROSEC_COUNTER[5]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(8), + datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(6), + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(7), + combout => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~0_combout\); + +-- Location: MLABCELL_X9_Y12_N57 +\myVirtualToplevel|Add4~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add4~9_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(9) ) + ( GND ) + ( \myVirtualToplevel|Add4~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(9), + cin => \myVirtualToplevel|Add4~22\, + sumout => \myVirtualToplevel|Add4~9_sumout\); + +-- Location: FF_X9_Y12_N59 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add4~9_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\, + sload => \myVirtualToplevel|Equal13~1_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_COUNTER\(9)); + +-- Location: FF_X9_Y12_N32 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add4~33_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\, + sload => \myVirtualToplevel|Equal13~1_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_COUNTER[0]~DUPLICATE_q\); + +-- Location: MLABCELL_X9_Y12_N24 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\ = ( \myVirtualToplevel|RTC_MICROSEC_COUNTER[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~1_combout\ & (!\myVirtualToplevel|Equal13~1_combout\ & +-- (\myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~0_combout\ & \myVirtualToplevel|RTC_MICROSEC_COUNTER\(9)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001000000000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~1_combout\, + datab => \myVirtualToplevel|ALT_INV_Equal13~1_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~0_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(9), + dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\); + +-- Location: FF_X9_Y12_N31 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add4~33_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\, + sload => \myVirtualToplevel|Equal13~1_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_COUNTER\(0)); + +-- Location: MLABCELL_X9_Y12_N33 +\myVirtualToplevel|Add4~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add4~37_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add4~34\ )) +-- \myVirtualToplevel|Add4~38\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add4~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(1), + cin => \myVirtualToplevel|Add4~34\, + sumout => \myVirtualToplevel|Add4~37_sumout\, + cout => \myVirtualToplevel|Add4~38\); + +-- Location: FF_X9_Y12_N35 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add4~37_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\, + sload => \myVirtualToplevel|Equal13~1_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_COUNTER\(1)); + +-- Location: MLABCELL_X9_Y12_N36 +\myVirtualToplevel|Add4~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add4~29_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add4~38\ )) +-- \myVirtualToplevel|Add4~30\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add4~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(2), + cin => \myVirtualToplevel|Add4~38\, + sumout => \myVirtualToplevel|Add4~29_sumout\, + cout => \myVirtualToplevel|Add4~30\); + +-- Location: FF_X9_Y12_N37 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add4~29_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\, + sload => \myVirtualToplevel|Equal13~1_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_COUNTER\(2)); + +-- Location: MLABCELL_X9_Y12_N39 +\myVirtualToplevel|Add4~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add4~25_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(3) ) + ( GND ) + ( \myVirtualToplevel|Add4~30\ )) +-- \myVirtualToplevel|Add4~26\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(3) ) + ( GND ) + ( \myVirtualToplevel|Add4~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(3), + cin => \myVirtualToplevel|Add4~30\, + sumout => \myVirtualToplevel|Add4~25_sumout\, + cout => \myVirtualToplevel|Add4~26\); + +-- Location: FF_X9_Y12_N41 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add4~25_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\, + sload => \myVirtualToplevel|Equal13~1_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_COUNTER\(3)); + +-- Location: MLABCELL_X9_Y12_N42 +\myVirtualToplevel|Add4~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add4~1_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(4) ) + ( GND ) + ( \myVirtualToplevel|Add4~26\ )) +-- \myVirtualToplevel|Add4~2\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(4) ) + ( GND ) + ( \myVirtualToplevel|Add4~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(4), + cin => \myVirtualToplevel|Add4~26\, + sumout => \myVirtualToplevel|Add4~1_sumout\, + cout => \myVirtualToplevel|Add4~2\); + +-- Location: FF_X9_Y12_N44 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add4~1_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\, + sload => \myVirtualToplevel|Equal13~1_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_COUNTER\(4)); + +-- Location: FF_X9_Y12_N46 +\myVirtualToplevel|RTC_MICROSEC_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add4~5_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\, + sload => \myVirtualToplevel|Equal13~1_combout\, + ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_MICROSEC_COUNTER\(5)); + +-- Location: FF_X10_Y10_N20 +\myVirtualToplevel|RTC_SECOND_COUNTER[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_SECOND_COUNTER~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_SECOND_COUNTER[5]~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y10_N36 +\myVirtualToplevel|Mux267~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux267~1_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|RTC_SECOND_COUNTER[5]~DUPLICATE_q\) ) ) +-- ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (\myVirtualToplevel|RTC_SECOND_COUNTER[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # ( +-- \myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- ((\myVirtualToplevel|RTC_MILLISEC_COUNTER\(5)))) ) ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|RTC_MILLISEC_COUNTER\(5)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(5), + datab => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(5), + datac => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|Mux267~1_combout\); + +-- Location: LABCELL_X12_Y11_N9 +\myVirtualToplevel|Mux267~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux267~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|SECOND_DOWN_COUNTER\(5)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- ((\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|MILLISEC_UP_COUNTER\(5) & ( (\myVirtualToplevel|SECOND_DOWN_COUNTER\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|MILLISEC_UP_COUNTER\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- ((\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111000000110000001101010000010111111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(5), + combout => \myVirtualToplevel|Mux267~0_combout\); + +-- Location: LABCELL_X12_Y10_N42 +\myVirtualToplevel|IO_DATA_READ[5]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[5]~38_combout\ = ( \myVirtualToplevel|UART1|Mux0~0_combout\ & ( \myVirtualToplevel|Mux267~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)) # +-- ((\myVirtualToplevel|Mux267~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ((\myVirtualToplevel|RTC_YEAR_COUNTER\(5))))) ) ) ) # ( !\myVirtualToplevel|UART1|Mux0~0_combout\ & ( +-- \myVirtualToplevel|Mux267~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)) # (\myVirtualToplevel|Mux267~1_combout\))) ) ) ) # ( \myVirtualToplevel|UART1|Mux0~0_combout\ & ( +-- !\myVirtualToplevel|Mux267~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|Mux267~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|RTC_YEAR_COUNTER\(5)))))) ) ) ) # ( !\myVirtualToplevel|UART1|Mux0~0_combout\ & ( !\myVirtualToplevel|Mux267~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +-- \myVirtualToplevel|Mux267~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010000000100001001110001010100010101000101010011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datac => \myVirtualToplevel|ALT_INV_Mux267~1_combout\, + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(5), + datae => \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_Mux267~0_combout\, + combout => \myVirtualToplevel|IO_DATA_READ[5]~38_combout\); + +-- Location: FF_X14_Y6_N32 +\myVirtualToplevel|UART1|RX_FIFO~23\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER\(6), + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO~23_q\); + +-- Location: FF_X14_Y6_N26 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER\(6), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(22)); + +-- Location: LABCELL_X14_Y6_N30 +\myVirtualToplevel|UART1|RX_DATA~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA~6_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(6) & ( \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(22) & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) # ((!\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & +-- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a5\)) # (\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO~23_q\)))) ) ) ) # ( !\myVirtualToplevel|UART1|RX_BUFFER\(6) & ( +-- \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(22) & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (((!\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & +-- ((!\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a5\)) # (\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO~23_q\))))) ) ) ) # ( +-- \myVirtualToplevel|UART1|RX_BUFFER\(6) & ( !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(22) & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (((\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & +-- ((!\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a5\)) # (\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO~23_q\))))) ) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_BUFFER\(6) & ( !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(22) & ( (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ((!\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & +-- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a5\)) # (\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO~23_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000011000001011111001111110101000000111111010111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~23_q\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(6), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(22), + combout => \myVirtualToplevel|UART1|RX_DATA~6_combout\); + +-- Location: MLABCELL_X13_Y6_N54 +\myVirtualToplevel|UART1|RX_DATA[5]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA[5]~7_combout\ = ( \myVirtualToplevel|UART1|RX_DATA~6_combout\ & ( ((\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\)) # (\myVirtualToplevel|UART1|RX_DATA\(5)) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_DATA~6_combout\ & ( (\myVirtualToplevel|UART1|RX_DATA\(5) & ((!\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\) # (!\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(5), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA~6_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA[5]~7_combout\); + +-- Location: FF_X13_Y6_N55 +\myVirtualToplevel|UART1|RX_DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_DATA[5]~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_DATA\(5)); + +-- Location: LABCELL_X10_Y5_N36 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[22]~feeder_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[22]~feeder_combout\); + +-- Location: FF_X10_Y5_N37 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[22]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(22)); + +-- Location: FF_X10_Y5_N56 +\myVirtualToplevel|UART0|RX_FIFO~23\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO~23_q\); + +-- Location: LABCELL_X10_Y5_N54 +\myVirtualToplevel|UART0|RX_DATA~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA~6_combout\ = ( \myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ( \myVirtualToplevel|UART0|RX_FIFO~23_q\ & ( (\myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE_q\) # (\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\) ) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ( \myVirtualToplevel|UART0|RX_FIFO~23_q\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(22))) # (\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & +-- ((\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a5\))) ) ) ) # ( \myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ( !\myVirtualToplevel|UART0|RX_FIFO~23_q\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & +-- \myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ( !\myVirtualToplevel|UART0|RX_FIFO~23_q\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & +-- (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(22))) # (\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ((\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a5\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111000000001010101000100111001001110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(22), + datac => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[6]~DUPLICATE_q\, + datae => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~23_q\, + combout => \myVirtualToplevel|UART0|RX_DATA~6_combout\); + +-- Location: LABCELL_X10_Y6_N39 +\myVirtualToplevel|UART0|RX_DATA[5]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA[5]~7_combout\ = (!\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\ & (((\myVirtualToplevel|UART0|RX_DATA\(5))))) # (\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\ & ((!\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ & +-- ((\myVirtualToplevel|UART0|RX_DATA\(5)))) # (\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ & (\myVirtualToplevel|UART0|RX_DATA~6_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111101111000000011110111100000001111011110000000111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA~6_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(5), + combout => \myVirtualToplevel|UART0|RX_DATA[5]~7_combout\); + +-- Location: FF_X10_Y6_N40 +\myVirtualToplevel|UART0|RX_DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_DATA[5]~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_DATA\(5)); + +-- Location: FF_X12_Y9_N5 +\myVirtualToplevel|UART0|RX_ENABLE_FIFO\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_ENABLE_FIFO~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_ENABLE~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_ENABLE_FIFO~q\); + +-- Location: LABCELL_X12_Y9_N48 +\myVirtualToplevel|IO_DATA_READ~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~37_combout\ = ( \myVirtualToplevel|UART0|RX_ENABLE_FIFO~q\ & ( \myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|UART0|RX_DATA\(5)) ) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_ENABLE_FIFO~q\ & ( \myVirtualToplevel|UART0_CS~combout\ & ( (\myVirtualToplevel|UART0|RX_DATA\(5)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # ( \myVirtualToplevel|UART0|RX_ENABLE_FIFO~q\ & ( +-- !\myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART1|RX_DATA\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (!\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\)) ) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_ENABLE_FIFO~q\ & ( !\myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART1|RX_DATA\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (!\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011101000111010001110100011101000001111111111110000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(5), + datae => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~q\, + dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\, + combout => \myVirtualToplevel|IO_DATA_READ~37_combout\); + +-- Location: LABCELL_X12_Y10_N12 +\myVirtualToplevel|IO_DATA_READ[5]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[5]~39_combout\ = ( \myVirtualToplevel|IO_DATA_READ~37_combout\ & ( \myVirtualToplevel|UART1|Add9~5_sumout\ & ( (!\myVirtualToplevel|TIMER0_CS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ & (((\myVirtualToplevel|IO_DATA_READ[5]~38_combout\)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~37_combout\ & ( \myVirtualToplevel|UART1|Add9~5_sumout\ & ( +-- (!\myVirtualToplevel|TIMER0_CS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ & (((\myVirtualToplevel|IO_DATA_READ[5]~38_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|IO_DATA_READ~37_combout\ & ( !\myVirtualToplevel|UART1|Add9~5_sumout\ & ( (!\myVirtualToplevel|TIMER0_CS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ & +-- ((\myVirtualToplevel|IO_DATA_READ[5]~38_combout\))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~37_combout\ & ( !\myVirtualToplevel|UART1|Add9~5_sumout\ & ( (\myVirtualToplevel|TIMER0_CS~1_combout\ & \myVirtualToplevel|IO_DATA_READ[5]~38_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111110000001100111100100000001011111110000011101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ[5]~38_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ~37_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add9~5_sumout\, + combout => \myVirtualToplevel|IO_DATA_READ[5]~39_combout\); + +-- Location: FF_X12_Y10_N13 +\myVirtualToplevel|IO_DATA_READ[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ[5]~39_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(5)); + +-- Location: FF_X19_Y13_N11 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux92~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(5)); + +-- Location: LABCELL_X19_Y13_N9 +\myVirtualToplevel|MEM_DATA_READ[5]~88_RESYN8737\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[5]~88_RESYN8737_BDD8738\ = ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(5) ) ) # ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(5) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(5), + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(5), + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[5]~88_RESYN8737_BDD8738\); + +-- Location: LABCELL_X20_Y14_N54 +\myVirtualToplevel|MEM_DATA_READ[5]~88\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[5]~88_combout\ = ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(5) & ( \myVirtualToplevel|MEM_DATA_READ[5]~88_RESYN8737_BDD8738\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(5) & ( \myVirtualToplevel|MEM_DATA_READ[5]~88_RESYN8737_BDD8738\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\) # (!\myVirtualToplevel|INTR0_CS~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(5) & ( !\myVirtualToplevel|MEM_DATA_READ[5]~88_RESYN8737_BDD8738\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\) # (\myVirtualToplevel|INTR0_CS~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(5) & ( !\myVirtualToplevel|MEM_DATA_READ[5]~88_RESYN8737_BDD8738\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((!\myVirtualToplevel|IO_SELECT~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101000111010001110100011101110111011101110100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datad => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(5), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~88_RESYN8737_BDD8738\, + combout => \myVirtualToplevel|MEM_DATA_READ[5]~88_combout\); + +-- Location: M10K_X22_Y16_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000111111100001110001151F6E261EFDF9F6EF79EFB9A4266E5F773FFE779EC6318C639CF3E5B10301FDDBEFBE77F39FF7BF7DF7DDEEE73B55201555501FFE01FC000A504652A79CFE9FB3FD3FCF73FD92485C5D5D4F9D3274CBED7BE7E1F1F72AB00611294E6E4986AD655BD195D68853DDE0A06F4EB89", + mem_init2 => "182E00730C1763EF7B961EF3EA24ECDCAF3ECBDCB4CBCF7D912C305D8E9E180095F134DF1C1AAB8AE935274813DD04792C734CA6BC4AF962471120198A6882ECAA0AD11F56A6BB01AB535DA0D01049A8CC042D6104F3D2E8CCACE954BC57105D0B868B42249038609C7468018D14272B19B464E03E1804F5476683896608962D5698E8A43BB12D3901E297810F90951F90C10D8B1A22FB942282392A44060C92D8D0914798B3C14A724840434DD90B794B213A7620357A5AD555C31040C961484546828930640A208231822827402EA6836C97C09430C0300249020329740013A6B8B6067128135120020483800258E6288620A06251C122E630418500202ECE", + mem_init1 => "3ACB0C42533104CDB423C0C159498ADF16AC336B19721520909067251E5A24C3080233852013DCF95960C70B172463111661AC0FC2210211CB024783188763F1B0AC726436D10F828D090686E028AC6EBDD683C810B2887C08C20DD602815884016A0215350C4AC26280100BF4C4843C18821289E2E687C4112284EEB02103A077C29546F6C4A2A4E0DAC6414E9DF12A7D6CE9D5D1B3C419B1EFA1EA34BA84849D944C8252420CE5A4D59CD72A0028940282A6080DA2005902751004972D043013BE0E083180211ABA0B4C0821D0A2D5424DCE7B6C0149DDCC3CDE0BB6153085C5B6495D0AD5A2971E1CC2409282114401606C85768E833913FAC84CDE21185A", + mem_init0 => "8810E0E4222CD20114200A43166100973880C80389089C6A1D98AE9301A2D51610E54913CA88A64A49BC8E881000133751065B25B36669101E7569C38CA20190267B126451D09240C1081523091266104984809B670603B877060C1830618615EC060B01000D602001AC04000100C00030606820B6594A05D7013B1B4D164D04A2816E682C631952000164001903D0BD4C63C8626BE9D29A72598DF9AA805180000809200014101400504000020284004A08112001C49000100222044444444444444444444444444000808101022204FFFFFFFFFFF8000000000000000000FEFD0001000000001C10020200080000000202180300010000011C010222000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 5, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 5, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X20_Y14_N42 +\myVirtualToplevel|MEM_DATA_READ[5]~127\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[5]~127_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[5]~88_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5~portbdataout\ & +-- \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(5))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\)))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[5]~88_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13~portbdataout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(5))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000001010101111111110101010100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(5), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]~17_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~88_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[5]~127_combout\); + +-- Location: FF_X20_Y14_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[5]~127_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(5)); + +-- Location: LABCELL_X19_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(5) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(5) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\); + +-- Location: LABCELL_X10_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[5]_NEW2929\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[5]_OTERM2930\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[5]_OTERM2930\); + +-- Location: FF_X10_Y23_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[5]_OTERM2930\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(5)); + +-- Location: LABCELL_X10_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[5]_NEW2865\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[5]_OTERM2866\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[5]_OTERM2866\); + +-- Location: FF_X10_Y23_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[5]_OTERM2866\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(5)); + +-- Location: LABCELL_X10_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[5]_NEW2737\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[5]_OTERM2738\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000001011111001111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[5]_OTERM2738\); + +-- Location: FF_X10_Y23_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[5]_OTERM2738\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(5)); + +-- Location: MLABCELL_X9_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[5]_NEW2801\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[5]_OTERM2802\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[5]_OTERM2802\); + +-- Location: FF_X9_Y19_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[5]_OTERM2802\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(5)); + +-- Location: LABCELL_X10_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux82~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(5) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(5)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(5)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(5) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(5) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(5)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111001100000011000001010000010111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~1_combout\); + +-- Location: LABCELL_X6_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[5]_NEW2993\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[5]_OTERM2994\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[5]_OTERM2994\); + +-- Location: FF_X6_Y23_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[5]_OTERM2994\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(5)); + +-- Location: LABCELL_X6_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[5]_NEW3185\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[5]_OTERM3186\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(5))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(5))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[5]_OTERM3186\); + +-- Location: FF_X6_Y23_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[5]_OTERM3186\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(5)); + +-- Location: LABCELL_X6_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[5]_NEW3057\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[5]_OTERM3058\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(5) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[5]_OTERM3058\); + +-- Location: FF_X6_Y23_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[5]_OTERM3058\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(5)); + +-- Location: LABCELL_X6_Y23_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[5]_NEW3121\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[5]_OTERM3122\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(5) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[5]_OTERM3122\); + +-- Location: FF_X6_Y23_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[5]_OTERM3122\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(5)); + +-- Location: LABCELL_X6_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux82~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(5))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(5) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(5)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(5))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(5) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(5) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000000001011111010100111111001111110000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~0_combout\); + +-- Location: LABCELL_X10_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux82~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux82~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2_combout\); + +-- Location: FF_X10_Y18_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5)); + +-- Location: MLABCELL_X18_Y8_N18 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[5]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[5]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000000011110101111111111111010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(13), + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[5]~1_combout\); + +-- Location: M10K_X22_Y7_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 5, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 5, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\); + +-- Location: FF_X20_Y12_N1 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\); + +-- Location: FF_X12_Y11_N4 +\myVirtualToplevel|INT_ENABLE[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(13)); + +-- Location: FF_X19_Y11_N5 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INT_ENABLE\(13), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(13)); + +-- Location: LABCELL_X17_Y12_N45 +\myVirtualToplevel|IO_DATA_READ~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~28_combout\ = ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( !\myVirtualToplevel|Equal3~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(6), + datae => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~28_combout\); + +-- Location: FF_X14_Y12_N40 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~13_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(13)); + +-- Location: LABCELL_X17_Y12_N51 +\myVirtualToplevel|IO_DATA_READ~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~29_combout\ = ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(13) & ( (\myVirtualToplevel|Equal3~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # +-- (\myVirtualToplevel|MILLISEC_UP_COUNTER\(13))))) ) ) # ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|Equal3~0_combout\ & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(13) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000000000010000000000100011000000000010001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(13), + combout => \myVirtualToplevel|IO_DATA_READ~29_combout\); + +-- Location: LABCELL_X17_Y12_N36 +\myVirtualToplevel|IO_DATA_READ~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~30_combout\ = ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(13) & ( \myVirtualToplevel|IO_DATA_READ~29_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) # +-- (\myVirtualToplevel|TIMER0_CS~1_combout\) ) ) ) # ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(13) & ( \myVirtualToplevel|IO_DATA_READ~29_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) # +-- (\myVirtualToplevel|TIMER0_CS~1_combout\) ) ) ) # ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(13) & ( !\myVirtualToplevel|IO_DATA_READ~29_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (!\myVirtualToplevel|IO_DATA_READ~28_combout\ & \myVirtualToplevel|TIMER0_CS~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|TIMER0_CS~1_combout\))))) ) ) ) # ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(13) & ( +-- !\myVirtualToplevel|IO_DATA_READ~29_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & !\myVirtualToplevel|TIMER0_CS~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000100000000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(13), + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~29_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~30_combout\); + +-- Location: FF_X17_Y12_N37 +\myVirtualToplevel|IO_DATA_READ[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~30_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(13)); + +-- Location: LABCELL_X19_Y11_N9 +\myVirtualToplevel|Mux90~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux90~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111110000000011111111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|Mux90~0_combout\); + +-- Location: FF_X19_Y11_N53 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux90~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(13)); + +-- Location: LABCELL_X19_Y11_N51 +\myVirtualToplevel|MEM_DATA_READ[13]~72_RESYN8721\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[13]~72_RESYN8721_BDD8722\ = ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(13) ) ) # ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(13) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(13), + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(13), + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[13]~72_RESYN8721_BDD8722\); + +-- Location: LABCELL_X19_Y11_N3 +\myVirtualToplevel|MEM_DATA_READ[13]~72\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[13]~72_combout\ = ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(13) & ( \myVirtualToplevel|MEM_DATA_READ[13]~72_RESYN8721_BDD8722\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(13) & ( \myVirtualToplevel|MEM_DATA_READ[13]~72_RESYN8721_BDD8722\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\) # (!\myVirtualToplevel|INTR0_CS~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(13) & ( !\myVirtualToplevel|MEM_DATA_READ[13]~72_RESYN8721_BDD8722\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\) # (\myVirtualToplevel|INTR0_CS~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(13) & ( !\myVirtualToplevel|MEM_DATA_READ[13]~72_RESYN8721_BDD8722\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((!\myVirtualToplevel|IO_SELECT~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011000110110001101100011011101110111011101100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datad => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(13), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~72_RESYN8721_BDD8722\, + combout => \myVirtualToplevel|MEM_DATA_READ[13]~72_combout\); + +-- Location: FF_X19_Y11_N20 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]_NEW_REG98\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]~13_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]_OTERM99\); + +-- Location: LABCELL_X19_Y11_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]~13_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]_OTERM99\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]_OTERM99\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\) ) ) ) # ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]_OTERM99\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]_OTERM89\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[13]_OTERM99\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]~13_combout\); + +-- Location: MLABCELL_X13_Y14_N18 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000011000011110000001111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~0_combout\); + +-- Location: MLABCELL_X23_Y14_N9 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node[0]\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(0) = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~0_combout\ & ( (\myVirtualToplevel|BRAM_WREN~1_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) # ((\myVirtualToplevel|LessThan3~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100011000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + datab => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\, + datac => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM1_WREN~0_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(0)); + +-- Location: M10K_X22_Y6_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111111111111100E9151F6E959EFDFBF7EF7BEFBBB6B6EF5F773FFE77BEC6318C63BDE3E5B10B6BFDDBEFBEF7F7BFF7BF7DF7DDEEEF7B57BFD555401BFE01FC003DEC06C2A7DCFC9FF3F53ECFD3D596585E5F5ED6AD52B55BCF73E000000B75620420082D598980CE3B876B6D6FC0C4A9C1705748F01", + mem_init2 => "6182EC74F0C004E27766E4F4E2BD549E4E4E53FF3753920B4DD3C3001201C18E1C20379F502AAB4AD5482648848A529034EF339870B7A23E545881A4AC82DCCACD2730B64354A6BBE1AA535DD5E4912D6168D88000C3C115E6AA95EF4E205E7F5B54D6A49240A1972A506B385210E0906677DDC1C9D7728238B0A050CC43254B1D34539638A45D702F30381114D9B0D4D9B8E32881498549B4144400062320EACA149982B8280203460A1CA46CCBCF9A69CB5833C3A28210CEF4101B20204A288096164A286663A0C2DB18CC1143EE03988AD506ACA2303801C801033081A8C1048225201040020A99D08133499808A405491C674B28000211200727DC9D8A8A", + mem_init1 => "0C88C8606177068C0850DD5C15CB3A2952B2B61107DA1700131F650000950C20468E023562C29092982847B8603C32A102D967E02106238388431C21950714C709020400EA7C411101209184B578493123403428924929C0499208A4204440123B010ABE8422B693BC024425210180828428762548575C611C1040448C8D6D6DF47CCB32F4F45872BA5C2C4101C098A218EB29E93485EFE9B3C02436914834118434AA58404A58059260C422867102026A620003801A811023A12C60080194ED8F29C776400B46D88C4F6C0BAE84C0A3B6062CE0028669698084B88009015B0AFC04A600800A152AE3D8A0293429892CB051999302348252B988EFE77301B650", + mem_init0 => "0AD65D64AC8E0D2857480B6A471694290380A5E8284202470EFD065924A866BC755C38A3E5EA66091D035512DCD770D5B6A927E0640521B81EDCACB6339F889842549706950B21A90543C28492A945DC61049F248070600010100000C18405000200608006B01008D6020000006030000816CD0002821A6D3458064128A0494D14D242101084200030000C9254D0262B431A003032499A9D495B2E518142000008600982004A0800821101A0080090104224000000912200802020400000404000404004000444440008881010222044FFFFFFFFFFFC104104104104104020FEF8000000000000211D0202000001000000000209000100000101010A22080000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 5, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 5, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X19_Y11_N30 +\myVirtualToplevel|MEM_DATA_READ[13]~143\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[13]~72_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(13) & +-- (((\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]~13_combout\)))))) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[13]~72_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))) # (\myVirtualToplevel|IO_DATA_READ_SD\(13)))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]~13_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001101000100110011110100010000000011011101111100111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(13), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~72_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[13]~13_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\); + +-- Location: LABCELL_X20_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector345~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector345~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~37_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\) # +-- (\myVirtualToplevel|MEM_DATA_READ[29]~44_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~37_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\) # +-- (\myVirtualToplevel|MEM_DATA_READ[13]~143_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add7~37_sumout\ & ( (\myVirtualToplevel|MEM_DATA_READ[29]~44_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add7~37_sumout\ & ( (\myVirtualToplevel|MEM_DATA_READ[13]~143_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000000011110000000001010101111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~143_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~44_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~37_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector345~0_combout\); + +-- Location: FF_X20_Y15_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector345~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[13]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[13]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[13]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[13]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\); + +-- Location: LABCELL_X7_Y26_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~38\); + +-- Location: MLABCELL_X9_Y27_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~37_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~37_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~27_combout\); + +-- Location: MLABCELL_X9_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~27_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(13) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~27_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000111111100101111011100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1070~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[13]~27_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~28_combout\); + +-- Location: FF_X9_Y27_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~28_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(13)); + +-- Location: MLABCELL_X9_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~37_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~37_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~32_combout\); + +-- Location: MLABCELL_X9_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~32_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~32_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(13) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000001011011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1070~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[13]~32_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~33_combout\); + +-- Location: FF_X9_Y27_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~33_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(13)); + +-- Location: MLABCELL_X9_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~37_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~37_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~30_combout\); + +-- Location: MLABCELL_X9_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~30_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(13) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~30_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101101110111010111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1070~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[13]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~31_combout\); + +-- Location: FF_X9_Y27_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~31_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(13)); + +-- Location: MLABCELL_X9_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~37_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~37_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~31_combout\); + +-- Location: MLABCELL_X9_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~31_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~31_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(13) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1070~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[13]~31_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~32_combout\); + +-- Location: FF_X9_Y27_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~32_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(13)); + +-- Location: MLABCELL_X9_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(13) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(13) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(13) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(13) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~0_combout\); + +-- Location: LABCELL_X12_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~37_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~37_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~28_combout\); + +-- Location: LABCELL_X12_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~28_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~28_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~28_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~28_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000010111111111111001000000000000001111111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1070~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[13]~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~29_combout\); + +-- Location: FF_X12_Y28_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~29_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(13)); + +-- Location: LABCELL_X6_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~37_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~37_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~30_combout\); + +-- Location: LABCELL_X6_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~30_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~30_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101111111010111100010000010100001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1070~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[13]~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~31_combout\); + +-- Location: FF_X6_Y28_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~31_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(13)); + +-- Location: LABCELL_X5_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~37_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~37_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~31_combout\); + +-- Location: LABCELL_X6_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~31_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~31_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~31_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~31_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000101110111111101100000100010001001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1070~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[13]~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~32_combout\); + +-- Location: FF_X6_Y31_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~32_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(13)); + +-- Location: LABCELL_X6_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~37_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~37_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~34_combout\); + +-- Location: LABCELL_X6_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~34_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(13) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~34_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101101011101011111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1070~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[13]~34_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~35_combout\); + +-- Location: FF_X6_Y28_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~35_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(13)); + +-- Location: LABCELL_X6_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(13) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(13) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(13) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(13) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~1_combout\); + +-- Location: MLABCELL_X9_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\); + +-- Location: LABCELL_X14_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~38\); + +-- Location: LABCELL_X14_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~42\); + +-- Location: LABCELL_X16_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector202~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~41_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~41_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000100110000011000010011000111111001101110011111100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~41_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~1_combout\); + +-- Location: LABCELL_X16_Y15_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector202~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector202~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector202~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000010100110000000011110101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[14]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector202~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~0_combout\); + +-- Location: FF_X16_Y15_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\); + +-- Location: M10K_X22_Y13_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 3, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 3, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\); + +-- Location: FF_X12_Y11_N13 +\myVirtualToplevel|INT_ENABLE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(3)); + +-- Location: FF_X18_Y11_N8 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INT_ENABLE\(3), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(3)); + +-- Location: LABCELL_X20_Y11_N36 +\myVirtualToplevel|Mux91~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux91~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001100000011000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + combout => \myVirtualToplevel|Mux91~0_combout\); + +-- Location: FF_X18_Y11_N5 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux91~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(3)); + +-- Location: LABCELL_X7_Y10_N24 +\myVirtualToplevel|IO_DATA_READ~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~65_combout\ = ( \myVirtualToplevel|RTC_YEAR_COUNTER\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|RTC_MONTH_COUNTER\(3)) ) ) ) # ( +-- !\myVirtualToplevel|RTC_YEAR_COUNTER\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # ( \myVirtualToplevel|RTC_YEAR_COUNTER\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|RTC_HOUR_COUNTER\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|RTC_YEAR_COUNTER\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|RTC_HOUR_COUNTER\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- ((\myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(3), + datab => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3), + datac => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|IO_DATA_READ~65_combout\); + +-- Location: FF_X17_Y11_N10 +\myVirtualToplevel|MILLISEC_UP_COUNTER[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~81_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER[3]~DUPLICATE_q\); + +-- Location: FF_X12_Y12_N10 +\myVirtualToplevel|SECOND_DOWN_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~33_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(3)); + +-- Location: MLABCELL_X13_Y12_N48 +\myVirtualToplevel|IO_DATA_READ~66\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~66_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_UP_COUNTER[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SECOND_DOWN_COUNTER\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # +-- (\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(3)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (\myVirtualToplevel|MILLISEC_UP_COUNTER[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SECOND_DOWN_COUNTER\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( +-- !\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011010001000111011111001111110011110100010001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(3), + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(3), + combout => \myVirtualToplevel|IO_DATA_READ~66_combout\); + +-- Location: LABCELL_X7_Y10_N42 +\myVirtualToplevel|IO_DATA_READ~67\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~67_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|RTC_SECOND_COUNTER\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_MILLISEC_COUNTER\(3))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_MINUTE_COUNTER\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|RTC_SECOND_COUNTER\(3) & ( (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(3)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|RTC_SECOND_COUNTER\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_MILLISEC_COUNTER\(3))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_MINUTE_COUNTER\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|RTC_SECOND_COUNTER\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- \myVirtualToplevel|RTC_MICROSEC_COUNTER\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000010100110101001100001111111111110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(3), + datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(3), + combout => \myVirtualToplevel|IO_DATA_READ~67_combout\); + +-- Location: LABCELL_X7_Y10_N0 +\myVirtualToplevel|IO_DATA_READ~68\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~68_combout\ = ( \myVirtualToplevel|IO_DATA_READ~66_combout\ & ( \myVirtualToplevel|IO_DATA_READ~67_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\) # ((\myVirtualToplevel|IO_DATA_READ~65_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~66_combout\ & ( \myVirtualToplevel|IO_DATA_READ~67_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\) # (\myVirtualToplevel|IO_DATA_READ~65_combout\))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ~66_combout\ & ( !\myVirtualToplevel|IO_DATA_READ~67_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (\myVirtualToplevel|IO_DATA_READ~65_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~66_combout\ & ( !\myVirtualToplevel|IO_DATA_READ~67_combout\ & ( (\myVirtualToplevel|IO_DATA_READ~65_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001110000011100000100110001001100011111000111110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ~65_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ~66_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~67_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~68_combout\); + +-- Location: FF_X13_Y6_N35 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(20)); + +-- Location: FF_X13_Y6_N11 +\myVirtualToplevel|UART1|RX_FIFO~21\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO~21_q\); + +-- Location: MLABCELL_X13_Y6_N33 +\myVirtualToplevel|UART1|RX_DATA~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA~12_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\ & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) # (\myVirtualToplevel|UART1|RX_FIFO~21_q\) ) ) ) # +-- ( !\myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\ & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (\myVirtualToplevel|UART1|RX_FIFO~21_q\ & \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) ) ) ) # ( +-- \myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(20))) # +-- (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( !\myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( +-- (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(20))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a3\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(20), + datab => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~21_q\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA~12_combout\); + +-- Location: MLABCELL_X13_Y6_N42 +\myVirtualToplevel|UART1|RX_DATA[3]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA[3]~13_combout\ = ( \myVirtualToplevel|UART1|RX_DATA~12_combout\ & ( ((\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\)) # (\myVirtualToplevel|UART1|RX_DATA\(3)) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_DATA~12_combout\ & ( (\myVirtualToplevel|UART1|RX_DATA\(3) & ((!\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\) # (!\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(3), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA~12_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA[3]~13_combout\); + +-- Location: FF_X13_Y6_N44 +\myVirtualToplevel|UART1|RX_DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_DATA[3]~13_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_DATA\(3)); + +-- Location: LABCELL_X14_Y5_N12 +\myVirtualToplevel|UART1|RX_OVERRUN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_OVERRUN~0_combout\ = ( \myVirtualToplevel|UART1|RX_OVERRUN~q\ & ( \myVirtualToplevel|UART1|RX_ENABLE~q\ ) ) # ( \myVirtualToplevel|UART1|RX_OVERRUN~q\ & ( !\myVirtualToplevel|UART1|RX_ENABLE~q\ ) ) # ( +-- !\myVirtualToplevel|UART1|RX_OVERRUN~q\ & ( !\myVirtualToplevel|UART1|RX_ENABLE~q\ & ( (\myVirtualToplevel|UART1|RX_INTR~0_combout\ & ((!\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ & (\myVirtualToplevel|UART1|Equal3~2_combout\)) # +-- (\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ & ((\myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000111111111111111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\, + datab => \myVirtualToplevel|UART1|ALT_INV_Equal3~2_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~DUPLICATE_q\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_OVERRUN~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\, + combout => \myVirtualToplevel|UART1|RX_OVERRUN~0_combout\); + +-- Location: FF_X14_Y5_N13 +\myVirtualToplevel|UART1|RX_OVERRUN\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_OVERRUN~0_combout\, + clrn => \myVirtualToplevel|UART1|RX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_OVERRUN~q\); + +-- Location: MLABCELL_X9_Y6_N30 +\myVirtualToplevel|UART0|RX_OVERRUN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_OVERRUN~0_combout\ = ( \myVirtualToplevel|UART0|RX_OVERRUN~q\ & ( \myVirtualToplevel|UART0|RX_DATA_READY~q\ ) ) # ( !\myVirtualToplevel|UART0|RX_OVERRUN~q\ & ( \myVirtualToplevel|UART0|RX_DATA_READY~q\ & ( +-- (!\myVirtualToplevel|UART0|RX_ENABLE~q\ & (\myVirtualToplevel|UART0|RX_INTR~0_combout\ & ((\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\) # (\myVirtualToplevel|UART0|Equal3~2_combout\)))) ) ) ) # ( \myVirtualToplevel|UART0|RX_OVERRUN~q\ & ( +-- !\myVirtualToplevel|UART0|RX_DATA_READY~q\ ) ) # ( !\myVirtualToplevel|UART0|RX_OVERRUN~q\ & ( !\myVirtualToplevel|UART0|RX_DATA_READY~q\ & ( (\myVirtualToplevel|UART0|Equal3~2_combout\ & (!\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & +-- (!\myVirtualToplevel|UART0|RX_ENABLE~q\ & \myVirtualToplevel|UART0|RX_INTR~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000111111111111111100000000011100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Equal3~2_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\, + datae => \myVirtualToplevel|UART0|ALT_INV_RX_OVERRUN~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\, + combout => \myVirtualToplevel|UART0|RX_OVERRUN~0_combout\); + +-- Location: FF_X9_Y6_N31 +\myVirtualToplevel|UART0|RX_OVERRUN\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_OVERRUN~0_combout\, + clrn => \myVirtualToplevel|UART0|RX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_OVERRUN~q\); + +-- Location: LABCELL_X14_Y9_N0 +\myVirtualToplevel|IO_DATA_READ~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~69_combout\ = ( \myVirtualToplevel|UART0|RX_OVERRUN~q\ & ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (\myVirtualToplevel|UART1|RX_DATA\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART1|RX_OVERRUN~q\))))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_OVERRUN~q\ & ( \myVirtualToplevel|UART1_CS~combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|UART1|RX_DATA\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART1|RX_OVERRUN~q\))))) ) ) ) # ( +-- \myVirtualToplevel|UART0|RX_OVERRUN~q\ & ( !\myVirtualToplevel|UART1_CS~combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000001010000001100000101000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(3), + datab => \myVirtualToplevel|UART1|ALT_INV_RX_OVERRUN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|UART0|ALT_INV_RX_OVERRUN~q\, + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|IO_DATA_READ~69_combout\); + +-- Location: FF_X10_Y5_N50 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(20)); + +-- Location: FF_X10_Y5_N29 +\myVirtualToplevel|UART0|RX_FIFO~21\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO~21_q\); + +-- Location: LABCELL_X10_Y5_N48 +\myVirtualToplevel|UART0|RX_DATA~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA~12_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\ & ( \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & +-- ((\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (\myVirtualToplevel|UART0|RX_FIFO~21_q\)) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ((\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & +-- (\myVirtualToplevel|UART0|RX_FIFO~21_q\)) ) ) ) # ( \myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) # +-- (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(20)) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(20) & +-- !\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(20), + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~21_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\, + datad => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA~12_combout\); + +-- Location: MLABCELL_X9_Y5_N39 +\myVirtualToplevel|UART0|RX_DATA[3]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA[3]~13_combout\ = ( \myVirtualToplevel|UART0|RX_DATA~12_combout\ & ( ((\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ & \myVirtualToplevel|UART0|RX_DATA[7]~0_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(3)) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_DATA~12_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA\(3) & ((!\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\) # (!\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111100000000001111110000000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(3), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA~12_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA[3]~13_combout\); + +-- Location: FF_X9_Y5_N40 +\myVirtualToplevel|UART0|RX_DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_DATA[3]~13_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_DATA\(3)); + +-- Location: LABCELL_X14_Y9_N24 +\myVirtualToplevel|IO_DATA_READ~71\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~71_combout\ = ( \myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ( \myVirtualToplevel|UART1|Add9~17_sumout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|IO_DATA_READ~69_combout\)) # +-- (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & ((\myVirtualToplevel|UART0|RX_DATA\(3)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ( \myVirtualToplevel|UART1|Add9~17_sumout\ & ( (\myVirtualToplevel|IO_DATA_READ~68_combout\) # +-- (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ( !\myVirtualToplevel|UART1|Add9~17_sumout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|IO_DATA_READ~69_combout\)) # +-- (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & ((\myVirtualToplevel|UART0|RX_DATA\(3)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ( !\myVirtualToplevel|UART1|Add9~17_sumout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & +-- \myVirtualToplevel|IO_DATA_READ~68_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010000010100101111101110111011101110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~70_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ~68_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ~69_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(3), + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~46_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add9~17_sumout\, + combout => \myVirtualToplevel|IO_DATA_READ~71_combout\); + +-- Location: FF_X14_Y9_N25 +\myVirtualToplevel|IO_DATA_READ[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~71_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(3)); + +-- Location: MLABCELL_X18_Y11_N48 +\myVirtualToplevel|MEM_DATA_READ[3]~92_RESYN8741\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[3]~92_RESYN8741_BDD8742\ = ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(3) ) ) # ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(3), + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(3), + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[3]~92_RESYN8741_BDD8742\); + +-- Location: MLABCELL_X18_Y11_N6 +\myVirtualToplevel|MEM_DATA_READ[3]~92\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[3]~92_combout\ = ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(3) & ( \myVirtualToplevel|MEM_DATA_READ[3]~92_RESYN8741_BDD8742\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(3) & ( \myVirtualToplevel|MEM_DATA_READ[3]~92_RESYN8741_BDD8742\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\) # (!\myVirtualToplevel|INTR0_CS~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(3) & ( !\myVirtualToplevel|MEM_DATA_READ[3]~92_RESYN8741_BDD8742\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\) # (\myVirtualToplevel|INTR0_CS~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(3) & ( !\myVirtualToplevel|MEM_DATA_READ[3]~92_RESYN8741_BDD8742\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((!\myVirtualToplevel|IO_SELECT~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110001010101110011110101010111111100010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(3), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~92_RESYN8741_BDD8742\, + combout => \myVirtualToplevel|MEM_DATA_READ[3]~92_combout\); + +-- Location: M10K_X30_Y14_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101010011001101010101000115106C9118E9CA16C842032B3292C80562240A16202108400029120020084A01508D30C0A4BBC0A005270008895110200404481F999999B801090E52A889022084004010440024108C0808183264C1A188409695A9472AB6DA10C20E6E20018C601BDF96D6B9B3E6ADA83357CB9", + mem_init2 => "BC3BC1A7DE1DF3D9EE9083D39E00FC787D3D9F74841F4E4AFC1B7877CEF5BC3D9D57347B3C1FAD836B04E7CD93DB84733DF71D8E255E69E2D19F4619A0608278BC00813D56A21120AB5108B0519065DA9C6625C43594447C3E146814B0B5127531C58B5A0D942850DEAE4F088D28604B1DCC07332C2A146539220208E10791ECD986896CDBBB2C7B80B9E686062E84862EBD08201E4355B46482213280065D98F87654BD0C8668167218625341581D2112842E64207D52CA18B9865207CA840C31470A1970FD1A2198200AA8F3CF2E75C2799EB08C51717206418F37E4C002187678809112855678814209839026D1DBC08E29F800031A4D8F6BF53DC0022058", + mem_init1 => "5BE60193129118027694229A415949E40089BCE9107049A278B06F29D41065C466E3648464B746BC6647BC69C18303DBFDE36C9ED631859FF787E5180ED8FBDA4088F0BE21011F647197645E80068C23781603023994C2653AF0017F5590CF8C810B10953598606647EC16CA300DB420B0418210800204468C4688608823E25112B0A950A277230508DBB0555F9460B02E3898310830445490A4519107A63D9003107D50BBEB1EF51E49E5FA3A30202706836F9B9300084E90784095475A7E2E7841C9024F732D37E2024288121893C32F0DB702FA19CB41E891821B1C3440EA42E779DF1B95EC81008EA0808886114335C44E00838C946901C0C1A01802261C", + mem_init0 => "0BB8A0A40120F400CD0F02C0906A007491C05A674167F0702964A85A85AA27BF1480231AAA6AE150CD96C6C9D5E1E3320524528085BB041786C108C5CC604844414FFECA43D89584A541D0A620827230136800F7FD450ED6DADDBB76EDD140D040308015184802231900C478C763B1F8CCB044382410E8048201F15365840E048240F4482A9285F5EAAA48001CC6D214069AE1D23D81401800800D42F0BCFBAEB69DF55DD2B4A7AF7EDFBE5574F5E9EFDBF1577E8C0014002B17562EEEEEEEEEEEEEEEEEEEEEEEEEEEC5DD0BBB17762EFFFFFFFFFFFA4924936DB6DB6DB6DBFEFD00000000000006022121190B00000000000807060100000001000061030D00", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 3, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 3, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X19_Y13_N12 +\myVirtualToplevel|MEM_DATA_READ[3]~99\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[3]~99_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[3]~92_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((((\myVirtualToplevel|IO_DATA_READ_SD\(3) & \myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))))) +-- # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3~portbdataout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[3]~92_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\) # +-- (\myVirtualToplevel|IO_DATA_READ_SD\(3)))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11~portbdataout\))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001100000011110011111100111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]~24_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(3), + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~92_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[3]~99_combout\); + +-- Location: FF_X19_Y18_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[3]~99_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(3)); + +-- Location: FF_X19_Y18_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(3)); + +-- Location: LABCELL_X19_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(3) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\); + +-- Location: LABCELL_X12_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[3]_NEW3189\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[3]_OTERM3190\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[3]_OTERM3190\); + +-- Location: FF_X12_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[3]_OTERM3190\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(3)); + +-- Location: LABCELL_X12_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[3]_NEW3061\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[3]_OTERM3062\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[3]_OTERM3062\); + +-- Location: FF_X12_Y23_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[3]_OTERM3062\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(3)); + +-- Location: LABCELL_X12_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[3]_NEW3125\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[3]_OTERM3126\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[3]_OTERM3126\); + +-- Location: FF_X12_Y19_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[3]_OTERM3126\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(3)); + +-- Location: LABCELL_X12_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[3]_NEW2997\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[3]_OTERM2998\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[3]_OTERM2998\); + +-- Location: FF_X12_Y19_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[3]_OTERM2998\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(3)); + +-- Location: LABCELL_X12_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux84~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(3) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(3) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(3) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(3) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~0_combout\); + +-- Location: LABCELL_X12_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[3]_NEW2741\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[3]_OTERM2742\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001001100011100110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[3]_OTERM2742\); + +-- Location: FF_X12_Y19_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[3]_OTERM2742\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(3)); + +-- Location: LABCELL_X12_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[3]_NEW2933\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[3]_OTERM2934\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000001111111001011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[3]_OTERM2934\); + +-- Location: FF_X12_Y19_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[3]_OTERM2934\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(3)); + +-- Location: MLABCELL_X13_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[3]_NEW2805\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[3]_OTERM2806\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[3]_OTERM2806\); + +-- Location: FF_X13_Y19_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[3]_OTERM2806\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(3)); + +-- Location: LABCELL_X10_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[3]_NEW2869\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[3]_OTERM2870\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(3))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[3]_OTERM2870\); + +-- Location: FF_X10_Y22_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[3]_OTERM2870\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(3)); + +-- Location: LABCELL_X12_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux84~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(3)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(3)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111101000100011101110100010001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~1_combout\); + +-- Location: MLABCELL_X13_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux84~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux84~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\); + +-- Location: LABCELL_X10_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[3]~feeder_combout\); + +-- Location: FF_X10_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3)); + +-- Location: LABCELL_X14_Y14_N54 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[3]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[3]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001111111100110011111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[3]~6_combout\); + +-- Location: M10K_X3_Y8_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 3, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 3, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\); + +-- Location: FF_X12_Y11_N34 +\myVirtualToplevel|INT_ENABLE[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE[11]~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y11_N36 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~3_combout\ = ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ & ( ((\myVirtualToplevel|UART1|TX_INTR~q\ & \myVirtualToplevel|INT_ENABLE\(11))) # (\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(11)) ) ) +-- # ( !\myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ & ( (\myVirtualToplevel|UART1|TX_INTR~q\ & \myVirtualToplevel|INT_ENABLE\(11)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_INTR~q\, + datac => \myVirtualToplevel|ALT_INV_INT_ENABLE\(11), + datad => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(11), + dataf => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\, + combout => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~3_combout\); + +-- Location: FF_X12_Y11_N37 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~3_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(11)); + +-- Location: FF_X14_Y11_N46 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|status[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(11), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(11)); + +-- Location: LABCELL_X14_Y11_N48 +\myVirtualToplevel|IO_DATA_READ_INTRCTL~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_INTRCTL~4_combout\ = ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|INT_ENABLE[11]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(11) & ( (\myVirtualToplevel|INT_ENABLE[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_INT_ENABLE[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(11), + combout => \myVirtualToplevel|IO_DATA_READ_INTRCTL~4_combout\); + +-- Location: FF_X14_Y11_N49 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_INTRCTL~4_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(11)); + +-- Location: FF_X18_Y12_N7 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux92~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(11)); + +-- Location: LABCELL_X17_Y12_N54 +\myVirtualToplevel|IO_DATA_READ~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000000000110011000000000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|IO_DATA_READ~43_combout\); + +-- Location: LABCELL_X17_Y12_N57 +\myVirtualToplevel|IO_DATA_READ[11]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[11]~42_combout\ = ( \myVirtualToplevel|TIMER0_CS~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001000000000010000100000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + combout => \myVirtualToplevel|IO_DATA_READ[11]~42_combout\); + +-- Location: FF_X6_Y11_N50 +\myVirtualToplevel|RTC_YEAR_COUNTER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[11]_OTERM1765\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER\(11)); + +-- Location: FF_X6_Y11_N58 +\myVirtualToplevel|RTC_YEAR_COUNTER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[8]_OTERM1759\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER\(8)); + +-- Location: LABCELL_X6_Y11_N21 +\myVirtualToplevel|Add11~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add11~25_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER\(7) ) + ( GND ) + ( \myVirtualToplevel|Add11~22\ )) +-- \myVirtualToplevel|Add11~26\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER\(7) ) + ( GND ) + ( \myVirtualToplevel|Add11~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(7), + cin => \myVirtualToplevel|Add11~22\, + sumout => \myVirtualToplevel|Add11~25_sumout\, + cout => \myVirtualToplevel|Add11~26\); + +-- Location: LABCELL_X6_Y11_N54 +\myVirtualToplevel|RTC_YEAR_COUNTER[7]_NEW1760\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER[7]_OTERM1761\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(7))))) # +-- (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|Add11~25_sumout\)) # (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) & ( +-- (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(7))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|Add11~25_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\, + datac => \myVirtualToplevel|ALT_INV_Add11~25_sumout\, + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7), + combout => \myVirtualToplevel|RTC_YEAR_COUNTER[7]_OTERM1761\); + +-- Location: FF_X6_Y11_N55 +\myVirtualToplevel|RTC_YEAR_COUNTER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[7]_OTERM1761\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER\(7)); + +-- Location: LABCELL_X6_Y11_N24 +\myVirtualToplevel|Add11~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add11~29_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add11~26\ )) +-- \myVirtualToplevel|Add11~30\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add11~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add11~26\, + sumout => \myVirtualToplevel|Add11~29_sumout\, + cout => \myVirtualToplevel|Add11~30\); + +-- Location: LABCELL_X6_Y11_N57 +\myVirtualToplevel|RTC_YEAR_COUNTER[8]_NEW1758\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER[8]_OTERM1759\ = ( \myVirtualToplevel|Add11~29_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(8))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & +-- ((!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8))))) ) ) # ( !\myVirtualToplevel|Add11~29_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & +-- (((\myVirtualToplevel|RTC_YEAR_COUNTER\(8))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(8), + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(8), + dataf => \myVirtualToplevel|ALT_INV_Add11~29_sumout\, + combout => \myVirtualToplevel|RTC_YEAR_COUNTER[8]_OTERM1759\); + +-- Location: FF_X6_Y11_N59 +\myVirtualToplevel|RTC_YEAR_COUNTER[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[8]_OTERM1759\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER[8]~DUPLICATE_q\); + +-- Location: LABCELL_X6_Y11_N27 +\myVirtualToplevel|Add11~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add11~9_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER\(9) ) + ( GND ) + ( \myVirtualToplevel|Add11~30\ )) +-- \myVirtualToplevel|Add11~10\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER\(9) ) + ( GND ) + ( \myVirtualToplevel|Add11~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(9), + cin => \myVirtualToplevel|Add11~30\, + sumout => \myVirtualToplevel|Add11~9_sumout\, + cout => \myVirtualToplevel|Add11~10\); + +-- Location: FF_X9_Y14_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(9)); + +-- Location: MLABCELL_X9_Y11_N15 +\myVirtualToplevel|RTC_YEAR_COUNTER[9]_NEW1768\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER[9]_OTERM1769\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(9) & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(9))))) # +-- (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|Add11~9_sumout\)) # (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(9) & ( +-- (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(9))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|Add11~9_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + datac => \myVirtualToplevel|ALT_INV_Add11~9_sumout\, + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(9), + combout => \myVirtualToplevel|RTC_YEAR_COUNTER[9]_OTERM1769\); + +-- Location: FF_X9_Y11_N16 +\myVirtualToplevel|RTC_YEAR_COUNTER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[9]_OTERM1769\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER\(9)); + +-- Location: LABCELL_X6_Y11_N30 +\myVirtualToplevel|Add11~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add11~13_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER[10]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add11~10\ )) +-- \myVirtualToplevel|Add11~14\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER[10]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add11~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[10]~DUPLICATE_q\, + cin => \myVirtualToplevel|Add11~10\, + sumout => \myVirtualToplevel|Add11~13_sumout\, + cout => \myVirtualToplevel|Add11~14\); + +-- Location: FF_X6_Y11_N46 +\myVirtualToplevel|RTC_YEAR_COUNTER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[10]_OTERM1767\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER\(10)); + +-- Location: LABCELL_X6_Y11_N45 +\myVirtualToplevel|RTC_YEAR_COUNTER[10]_NEW1766\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER[10]_OTERM1767\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(10))))) # +-- (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|Add11~13_sumout\)) # (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) & ( +-- (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(10))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|Add11~13_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\, + datac => \myVirtualToplevel|ALT_INV_Add11~13_sumout\, + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(10), + combout => \myVirtualToplevel|RTC_YEAR_COUNTER[10]_OTERM1767\); + +-- Location: FF_X6_Y11_N47 +\myVirtualToplevel|RTC_YEAR_COUNTER[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[10]_OTERM1767\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER[10]~DUPLICATE_q\); + +-- Location: LABCELL_X6_Y11_N33 +\myVirtualToplevel|Add11~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Add11~17_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER\(11) ) + ( GND ) + ( \myVirtualToplevel|Add11~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(11), + cin => \myVirtualToplevel|Add11~14\, + sumout => \myVirtualToplevel|Add11~17_sumout\); + +-- Location: LABCELL_X6_Y11_N48 +\myVirtualToplevel|RTC_YEAR_COUNTER[11]_NEW1764\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|RTC_YEAR_COUNTER[11]_OTERM1765\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11) & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(11))))) # +-- (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|Add11~17_sumout\)) # (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11) & ( +-- (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(11))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|Add11~17_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\, + datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\, + datac => \myVirtualToplevel|ALT_INV_Add11~17_sumout\, + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(11), + combout => \myVirtualToplevel|RTC_YEAR_COUNTER[11]_OTERM1765\); + +-- Location: FF_X6_Y11_N49 +\myVirtualToplevel|RTC_YEAR_COUNTER[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|RTC_YEAR_COUNTER[11]_OTERM1765\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|RTC_YEAR_COUNTER[11]~DUPLICATE_q\); + +-- Location: FF_X12_Y12_N34 +\myVirtualToplevel|SECOND_DOWN_COUNTER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~17_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(11)); + +-- Location: LABCELL_X16_Y12_N24 +\myVirtualToplevel|IO_DATA_READ~104\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~104_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (\myVirtualToplevel|INTR0_CS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(11) & +-- (\myVirtualToplevel|TIMER0_CS~2_combout\)))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (\myVirtualToplevel|INTR0_CS~0_combout\ & (\myVirtualToplevel|TIMER0_CS~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ((\myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SECOND_DOWN_COUNTER\(11)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000000100000000000000000100000000000001000000000001000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(11), + datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\, + datag => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(11), + combout => \myVirtualToplevel|IO_DATA_READ~104_combout\); + +-- Location: LABCELL_X17_Y12_N9 +\myVirtualToplevel|IO_DATA_READ~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~45_combout\ = ( \myVirtualToplevel|IO_DATA_READ~104_combout\ ) # ( !\myVirtualToplevel|IO_DATA_READ~104_combout\ & ( (\myVirtualToplevel|IO_DATA_READ[11]~42_combout\ & ((!\myVirtualToplevel|IO_DATA_READ~43_combout\ & +-- (\myVirtualToplevel|MILLISEC_UP_COUNTER\(11))) # (\myVirtualToplevel|IO_DATA_READ~43_combout\ & ((\myVirtualToplevel|RTC_YEAR_COUNTER[11]~DUPLICATE_q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011000000100001001111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ~43_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ[11]~42_combout\, + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(11), + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~104_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~45_combout\); + +-- Location: FF_X17_Y12_N10 +\myVirtualToplevel|IO_DATA_READ[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~45_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(11)); + +-- Location: MLABCELL_X18_Y12_N30 +\myVirtualToplevel|MEM_DATA_READ[11]~76_RESYN8725\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[11]~76_RESYN8725_BDD8726\ = ( \myVirtualToplevel|IO_DATA_READ\(11) & ( (!\myVirtualToplevel|SOCCFG_CS~combout\) # (\myVirtualToplevel|IO_DATA_READ_SOCCFG\(11)) ) ) # ( !\myVirtualToplevel|IO_DATA_READ\(11) & ( +-- (\myVirtualToplevel|IO_DATA_READ_SOCCFG\(11) & \myVirtualToplevel|SOCCFG_CS~combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(11), + datad => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(11), + combout => \myVirtualToplevel|MEM_DATA_READ[11]~76_RESYN8725_BDD8726\); + +-- Location: LABCELL_X19_Y12_N21 +\myVirtualToplevel|MEM_DATA_READ[11]~76\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[11]~76_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|INTR0_CS~combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|INTR0_CS~combout\ & ( (!\myVirtualToplevel|IO_SELECT~combout\) # (\myVirtualToplevel|IO_DATA_READ_INTRCTL\(11)) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( +-- !\myVirtualToplevel|INTR0_CS~combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( !\myVirtualToplevel|INTR0_CS~combout\ & ( +-- (!\myVirtualToplevel|IO_SELECT~combout\) # (\myVirtualToplevel|MEM_DATA_READ[11]~76_RESYN8725_BDD8726\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111111001100110011001111110101111101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(11), + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~76_RESYN8725_BDD8726\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[11]~76_combout\); + +-- Location: IOIBUF_X25_Y0_N18 +\SDRAM_DQ[11]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(11), + o => \SDRAM_DQ[11]~input_o\); + +-- Location: DDIOINCELL_X25_Y0_N31 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_NEW_REG20\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[11]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM21\); + +-- Location: FF_X19_Y12_N56 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]_NEW_REG48\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]~20_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]_OTERM49\); + +-- Location: LABCELL_X19_Y12_N57 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]~20_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]_OTERM49\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM21\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]_OTERM49\ ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]_OTERM49\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM21\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000110000001111111111111111111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]_OTERM21\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[11]_OTERM49\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]~20_combout\); + +-- Location: M10K_X11_Y10_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022220000000000000000000091526A4B392A12B145280C33B129AAD4D30311A07214A5294A00C928490800BCEC101AC9014240303A012F1950A4400208155401F99999B9400020ED80811042004004010444220212622A63D78F1E3C480552000000B757A34E44E5D7DA683086215EB5D2B265CD9E3765BD4508", + mem_init2 => "DBC3BE77ADE1ECE47FE3C8FCE1F454DE0FCE23BB1E23B20357DEF785B2877BDA8DE01E9FC27ACB22F5480040DCDA639011EF77BAF1B3AA3B5A08991DF06594EAA93223970556A21120AB5108B5E093A4C07283504CC0195D0AFA812D64244830E25CC8A4927081A0463247FD7241601200361EC189F7768A79B4B4914CC864396D1033B62C6C4B70331E0BC8A149D66149B821044942E745144D87870C4FE6CAC75C10B48A3C92E3CB4A01AC619201FE4159C2233F96131048937A33207C4203C8280861AA66C608E3F8214E18622A0FB8EA650DA83C0C0C50002782308F79A58C802560DC64280EF6102167470A0EE69FC0BAAF122C418081A009C5E8634821", + mem_init1 => "1CDA1E40435CC489B99E154E126B583B90048590036F16681752F3703425A239971B187D3928913037894E8665242EE3174C7FB4C1054DD2180E4B21771E1945DB234B15C6052918ACE960902119D92081E0600196DC5103C3828004828660D069C3AAB9BF0DBE183C02DA320016E18004484161CC0634887198E060A9987658025A0622457E1030A84EA2D2A850B0202801B02106400408101C6904C70740A801038877041CCD6DC6604AAA823B06C2DA389041CC37C3F80443B586D8618597646CE9C0081B943708B9033E01A128BB66A7FAC0C3CF245BC326906650CC3218D42D032806AC09E346188778252084E5B8435DBAEA804864A083898110300718", + mem_init0 => "603C4B55950C0C2C593D431486161638103429720C3000C4C40084400181808EB17810328201E16A21074E30E6EDF0C0B009134038100B3358D48392958888006E7EC6760D0849BE113C0C00DB09E77723013A6F23DC50702E082020808518451A424A8C240111848062309E31B8DC660B24891E8243A14D96108581209038400093C5D05EF7BD190001490008E00802023E06202000018952014011CAD66EFB5B6F57B67857FAF995776BAA93DFB722AEEFD28BC4992200817562EAEEAEAAEAEEAEEAEEEAEEAAAEAC5DD0BBA17762EFFFFFFFFFFFFF6DB6DB6DB6DB7FFEDBFEF80000000000003004252510000201000606200D010001000018000476080B01", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 3, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 3, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X19_Y12_N36 +\myVirtualToplevel|MEM_DATA_READ[11]~115\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[11]~76_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(11) & +-- (((\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]~20_combout\)))))) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[11]~76_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))) # (\myVirtualToplevel|IO_DATA_READ_SD\(11)))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]~20_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000010100100010101011110010001000000101011101111010111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(11), + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~76_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[11]~20_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\); + +-- Location: LABCELL_X14_Y14_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~37_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010110101010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~115_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~37_combout\); + +-- Location: FF_X14_Y14_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_NEW_REG528\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~37_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM529\); + +-- Location: FF_X14_Y14_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_NEW_REG524\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM525\); + +-- Location: LABCELL_X14_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|MEM_DATA_READ[11]~115_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|MEM_DATA_READ[11]~115_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- ((\myVirtualToplevel|MEM_DATA_READ[11]~115_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- ((\myVirtualToplevel|MEM_DATA_READ[11]~115_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010010111010111111100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~2_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~115_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~36_combout\); + +-- Location: FF_X14_Y14_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_NEW_REG526\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~36_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM527\); + +-- Location: LABCELL_X14_Y14_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM525\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM527\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM529\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM525\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM527\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM529\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM525\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM527\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM529\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM525\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM527\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM529\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000010111111110101011100000000101000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM529\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM525\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM527\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\); + +-- Location: MLABCELL_X23_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~309\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~309_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~309_combout\); + +-- Location: FF_X23_Y34_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~309_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\); + +-- Location: MLABCELL_X23_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\); + +-- Location: MLABCELL_X23_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000101011001110100100110101011100011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\); + +-- Location: LABCELL_X24_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000010001000011001101110100111111000100010011111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\); + +-- Location: MLABCELL_X23_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000100110000101010011011110001100101011101001110110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\); + +-- Location: LABCELL_X25_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010010011000110111000011001001110110101110101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\); + +-- Location: LABCELL_X21_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100001010100110111000011001010111010011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\); + +-- Location: MLABCELL_X9_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~86\); + +-- Location: MLABCELL_X9_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~82\); + +-- Location: MLABCELL_X9_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~70\); + +-- Location: MLABCELL_X9_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~74\); + +-- Location: MLABCELL_X9_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~78\); + +-- Location: MLABCELL_X13_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010000001100110101000000110011010111110011001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~42_combout\); + +-- Location: MLABCELL_X13_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~42_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~42_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~42_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~42_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100111110101111111000000001000001011111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1072~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[11]~42_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~43_combout\); + +-- Location: FF_X13_Y28_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~43_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(11)); + +-- Location: LABCELL_X7_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~65_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~44_combout\); + +-- Location: LABCELL_X7_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~44_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~44_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~44_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~44_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000101011111110111100010000010100001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1072~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~44_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~45_combout\); + +-- Location: FF_X7_Y31_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~45_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(11)); + +-- Location: LABCELL_X5_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001001110000010100100111000011011010111110001101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~65_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~45_combout\); + +-- Location: LABCELL_X5_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~45_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~45_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~45_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~45_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000110111001111111100010011000000001101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1072~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[11]~45_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~46_combout\); + +-- Location: FF_X5_Y31_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~46_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(11)); + +-- Location: LABCELL_X5_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~65_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~48_combout\); + +-- Location: LABCELL_X5_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~48_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(11) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~48_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000011110111011100111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1072~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[11]~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~49_combout\); + +-- Location: FF_X5_Y30_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~49_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(11)); + +-- Location: LABCELL_X10_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(11))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(11)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(11))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(11) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000000111100111111011101110111010000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~1_combout\); + +-- Location: MLABCELL_X13_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~65_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~45_combout\); + +-- Location: MLABCELL_X13_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~45_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~45_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(11) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1072~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[11]~45_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~46_combout\); + +-- Location: FF_X13_Y28_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~46_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(11)); + +-- Location: MLABCELL_X13_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~65_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~41_combout\); + +-- Location: MLABCELL_X13_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~41_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~41_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100111111110111011100000000000011001111111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1072~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[11]~41_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~42_combout\); + +-- Location: FF_X13_Y28_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~42_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(11)); + +-- Location: MLABCELL_X13_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110000001101010011000000110101001111110011010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~44_combout\); + +-- Location: MLABCELL_X13_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~44_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~44_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~44_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~44_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000110111111100111100010000001100001101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1072~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[11]~44_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~45_combout\); + +-- Location: FF_X13_Y28_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~45_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(11)); + +-- Location: MLABCELL_X13_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111000001010101010101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~46_combout\); + +-- Location: MLABCELL_X13_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~46_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~46_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(11) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1072~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[11]~46_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~47_combout\); + +-- Location: FF_X13_Y28_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~47_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(11)); + +-- Location: LABCELL_X14_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(11) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(11) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(11) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(11) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~0_combout\); + +-- Location: LABCELL_X10_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\); + +-- Location: LABCELL_X14_Y16_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector205~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~65_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~65_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~65_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~65_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000001111010111110000111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~65_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~1_combout\); + +-- Location: LABCELL_X16_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector205~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector205~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector205~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010111101011111111100000010101000100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector205~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~0_combout\); + +-- Location: FF_X16_Y14_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y13_N33 +\myVirtualToplevel|SOCCFG_CS_RESYN8753\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SOCCFG_CS_RESYN8753_BDD8754\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9), + combout => \myVirtualToplevel|SOCCFG_CS_RESYN8753_BDD8754\); + +-- Location: LABCELL_X17_Y13_N42 +\myVirtualToplevel|SOCCFG_CS\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SOCCFG_CS~combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & ( \myVirtualToplevel|SOCCFG_CS_RESYN8753_BDD8754\ & ( (\myVirtualToplevel|IO_SELECT~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ +-- & (\myVirtualToplevel|IO_SELECT~2_combout\ & \myVirtualToplevel|IO_SELECT~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS_RESYN8753_BDD8754\, + combout => \myVirtualToplevel|SOCCFG_CS~combout\); + +-- Location: MLABCELL_X18_Y13_N57 +\myVirtualToplevel|MEM_DATA_READ[18]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ = ( \myVirtualToplevel|LessThan0~0_combout\ & ( \myVirtualToplevel|IO_SELECT~combout\ & ( (!\myVirtualToplevel|SOCCFG_CS~combout\ & ((!\myVirtualToplevel|INTR0_CS~combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|LessThan0~0_combout\ & ( \myVirtualToplevel|IO_SELECT~combout\ & ( (!\myVirtualToplevel|SOCCFG_CS~combout\ & ((!\myVirtualToplevel|INTR0_CS~combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|LessThan0~0_combout\ & ( !\myVirtualToplevel|IO_SELECT~combout\ & ( (!\myVirtualToplevel|SOCCFG_CS~combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|LessThan0~0_combout\ & ( !\myVirtualToplevel|IO_SELECT~combout\ & ( (!\myVirtualToplevel|SOCCFG_CS~combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000000000001111000011110000101000001010000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datac => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\, + datae => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[18]~7_combout\); + +-- Location: FF_X17_Y10_N4 +\myVirtualToplevel|MILLISEC_UP_COUNTER[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~5_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(21)); + +-- Location: LABCELL_X16_Y10_N0 +\myVirtualToplevel|IO_DATA_READ~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~7_combout\ = ( \myVirtualToplevel|Equal3~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(21)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(21))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100100011000000010010001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(21), + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(21), + dataf => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~7_combout\); + +-- Location: LABCELL_X16_Y9_N51 +\myVirtualToplevel|IO_DATA_READ~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~6_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|Add10~5_sumout\ & ( ((\myVirtualToplevel|UART1|TX_INTR~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|Add10~5_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|UART0|TX_INTR~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( \myVirtualToplevel|UART1_CS~combout\ & ( !\myVirtualToplevel|UART1|Add10~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART1|TX_INTR~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( !\myVirtualToplevel|UART1|Add10~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART0|TX_INTR~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100001111000001110000011101010101010111110101011101010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|UART1|ALT_INV_TX_INTR~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_INTR~q\, + datae => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add10~5_sumout\, + combout => \myVirtualToplevel|IO_DATA_READ~6_combout\); + +-- Location: LABCELL_X16_Y9_N15 +\myVirtualToplevel|IO_DATA_READ~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~8_combout\ = ( \myVirtualToplevel|IO_DATA_READ~7_combout\ & ( \myVirtualToplevel|IO_DATA_READ~6_combout\ ) ) # ( !\myVirtualToplevel|IO_DATA_READ~7_combout\ & ( \myVirtualToplevel|IO_DATA_READ~6_combout\ & ( +-- (!\myVirtualToplevel|TIMER0_CS~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ~7_combout\ & ( !\myVirtualToplevel|IO_DATA_READ~6_combout\ & ( (\myVirtualToplevel|TIMER0_CS~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000011001111110011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ~7_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~6_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~8_combout\); + +-- Location: FF_X16_Y9_N17 +\myVirtualToplevel|IO_DATA_READ[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~8_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(21)); + +-- Location: FF_X21_Y12_N43 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux87~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(21)); + +-- Location: LABCELL_X24_Y9_N21 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector10~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector10~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(5) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(5), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector10~0_combout\); + +-- Location: FF_X24_Y9_N22 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector10~0_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5), + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(5)); + +-- Location: LABCELL_X21_Y9_N3 +\myVirtualToplevel|IO_DATA_READ_SD[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[21]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(5) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(5), + combout => \myVirtualToplevel|IO_DATA_READ_SD[21]~feeder_combout\); + +-- Location: MLABCELL_X18_Y9_N0 +\myVirtualToplevel|SD_ADDR[0][21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]~15_combout\, + combout => \myVirtualToplevel|SD_ADDR[0][21]~feeder_combout\); + +-- Location: FF_X18_Y9_N1 +\myVirtualToplevel|SD_ADDR[0][21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][21]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][21]~q\); + +-- Location: FF_X21_Y9_N4 +\myVirtualToplevel|IO_DATA_READ_SD[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[21]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][21]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(21)); + +-- Location: LABCELL_X20_Y12_N3 +\myVirtualToplevel|MEM_DATA_READ[21]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[21]~8_combout\ = ( \myVirtualToplevel|INTR0_CS~combout\ & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & \myVirtualToplevel|IO_DATA_READ\(21)) ) ) ) # ( +-- !\myVirtualToplevel|INTR0_CS~combout\ & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) # (\myVirtualToplevel|IO_DATA_READ\(21)) ) ) ) # ( \myVirtualToplevel|INTR0_CS~combout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ_SOCCFG\(21))) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((\myVirtualToplevel|IO_DATA_READ_SD\(21)))) ) ) ) +-- # ( !\myVirtualToplevel|INTR0_CS~combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ_SOCCFG\(21))) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & +-- ((\myVirtualToplevel|IO_DATA_READ_SD\(21)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111110111011101110110001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(21), + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(21), + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(21), + datae => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[21]~8_combout\); + +-- Location: LABCELL_X17_Y8_N57 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[5]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[5]~1_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]~15_combout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[5]~1_combout\); + +-- Location: M10K_X30_Y9_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002200000000022200000E1003FEFB79EFDFB77FFFBEFBBFEFCAF5F77BFFF77BFEF7BDEF33DF3E7B16B6BFFDBEFBEF7F7BFF7BFF9F7FDFFEF7D57BFD757401BFE01FC0014A51EE3AE9DFEBEF7F57FDDD77792487E7F7E7EFDF3F7CFDB7FE000000D3E8812B4C22C52D080C63BCAB52ACEC994E26160F52AEAE", + mem_init2 => "9E1800900E0C74D29A96E530D93ABDA7D34D54F53754D2F9B1C03C31D3305C00FBA5E7A6588AB50D69EC9D3914A88494F39AF6F9D339C4A695CC3A87020A9A9112D48F2D778356A6BB01AB5359436041AE4C6A6601129B08EB393DE52E84A7C0028528C03682050418652E014CC2584B9520E8E2369521DA5007A6831926EB1ACB7C97248593A41E8FAAB6221E34F01E34904B6D329D5436ACC2611B76D2C081ED352603A487066B64973CE4639146619A425BE7828A765D1B14111A440C988040043D4401162A9094927304C34FA0811C9CC2260594E98501148930B6408480021AC2341D81920A01234A280D9B590600731C010DC8958E500B40D486106306", + mem_init1 => "4322A0D1D55018160055A2DC440E3C29F98AB6DDB2447413600C05B08DD930981C4858910940C02460AAB01909FBF50CC8F0098A12381B2120E1615FA86C055B0D8C4764A8DC042500017592AC480D043B77B7147224047E4E3823F97C120A70A828F140C09749A30A4904BA381012EAD80505388021058201820A2C42CA4981F286434A92A5937186BAC9A00A75EF168A28E2F9BA32EF778313029750AB04A165B00103240012834CD1E0802EE43AC60BC0049B11D29001414A2856230F04A9D5298E44A18E0100B7414481CE28C0C2205E89C21A2031E92874B59B7535E083AF0010D25AD54A0EBAD2AB03C90E50E06549922C01010B43294F233A6DB1A4E5", + mem_init0 => "781090A0806D941202781A4036C20914D401C8C51B039818C21CA922795114C9D98AE9301A2D516C0FD59859909044AC6B95B63A82C6346F954C9C6866E770FEF1448434F2D22141B0340A02243908005DE612000C17861FC3C70F1C3C7DF83060B980035808006B01000D4000180C022320602DA4D01704A28131D34534820BAE00A59FBB18C618000031B48098829CD3B2B69223D9FD26B55223450020800488900040A080080400001410202080C0000400010192A000222004004000044400000000440444440080811102220444FFFFFFFFFFF8000000000000000000FEFB00000000000118200808251102010000001105010000000301030093190400", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 5, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 5, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\); + +-- Location: M10K_X30_Y7_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 5, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 5, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X21_Y12_N24 +\myVirtualToplevel|MEM_DATA_READ[21]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[21]~9_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13~portbdataout\ & ( (\myVirtualToplevel|LessThan0~1_combout\ & +-- ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5~portbdataout\) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0)))) ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13~portbdataout\ & ( (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5~portbdataout\ & \myVirtualToplevel|LessThan0~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010000000000000101000000000010111110000000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[21]~9_combout\); + +-- Location: LABCELL_X20_Y12_N57 +\myVirtualToplevel|MEM_DATA_READ[21]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[21]~8_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[21]~9_combout\ ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[21]~8_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[21]~9_combout\ ) ) # ( \myVirtualToplevel|MEM_DATA_READ[21]~8_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[21]~9_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[21]~8_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[21]~9_combout\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5_combout\ & \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001011111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[21]~5_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~8_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~9_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\); + +-- Location: MLABCELL_X4_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~26\); + +-- Location: MLABCELL_X4_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~30\); + +-- Location: MLABCELL_X4_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~14\); + +-- Location: MLABCELL_X4_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~6\); + +-- Location: LABCELL_X5_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~5_sumout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111111111111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\); + +-- Location: MLABCELL_X9_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~46\); + +-- Location: MLABCELL_X9_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~2\); + +-- Location: MLABCELL_X9_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~22\); + +-- Location: MLABCELL_X9_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~26\); + +-- Location: MLABCELL_X9_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~30\); + +-- Location: MLABCELL_X9_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~14\); + +-- Location: MLABCELL_X9_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~6\); + +-- Location: LABCELL_X7_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011000000110000000000111111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~14_combout\); + +-- Location: LABCELL_X7_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~14_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~14_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~14_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~14_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000000111101001111111100000111000000001111011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1062~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[21]~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~15_combout\); + +-- Location: FF_X7_Y28_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~15_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(21)); + +-- Location: LABCELL_X7_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000101110000011000010111000011101001111110001110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~12_combout\); + +-- Location: LABCELL_X7_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~12_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~12_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(21) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1062~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[21]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~13_combout\); + +-- Location: FF_X7_Y28_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~13_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(21)); + +-- Location: LABCELL_X7_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000101110000011000010111000011101001111110001110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~18_combout\); + +-- Location: LABCELL_X7_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~18_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~18_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001000111100111111101100000100000011001111011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1062~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[21]~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~19_combout\); + +-- Location: FF_X7_Y30_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~19_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(21)); + +-- Location: LABCELL_X7_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010000000000001111000011110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~15_combout\); + +-- Location: LABCELL_X7_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~15_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~15_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~15_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000110111111100111100010000001100001101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1062~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[21]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~16_combout\); + +-- Location: FF_X7_Y28_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~16_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(21)); + +-- Location: LABCELL_X7_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(21) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(21) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(21) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(21) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~1_combout\); + +-- Location: LABCELL_X5_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~11_combout\); + +-- Location: LABCELL_X5_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~11_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~11_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101110101111111100010101000000001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1062~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[21]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~12_combout\); + +-- Location: FF_X5_Y28_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(21)); + +-- Location: LABCELL_X5_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~15_combout\); + +-- Location: LABCELL_X5_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~15_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000010111111111111001000000000000001111111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1062~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[21]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~16_combout\); + +-- Location: FF_X5_Y28_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~16_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(21)); + +-- Location: LABCELL_X5_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~16_combout\); + +-- Location: LABCELL_X5_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~16_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~16_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(21) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1062~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[21]~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~17_combout\); + +-- Location: FF_X5_Y28_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(21)); + +-- Location: LABCELL_X5_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~14_combout\); + +-- Location: LABCELL_X5_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~14_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(21) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~14_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101101110111010111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1062~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[21]~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~15_combout\); + +-- Location: FF_X5_Y29_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~15_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(21)); + +-- Location: MLABCELL_X4_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(21) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(21) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(21) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(21) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~0_combout\); + +-- Location: LABCELL_X6_Y17_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\); + +-- Location: MLABCELL_X4_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(20)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp\(20)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\); + +-- Location: LABCELL_X10_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010000010100110101000001010011010111110101001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~13_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~19_combout\); + +-- Location: LABCELL_X10_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~19_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~19_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~19_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~19_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000111111111101110000000000000100111111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1063~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[20]~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~20_combout\); + +-- Location: FF_X10_Y28_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(20)); + +-- Location: LABCELL_X10_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010000010100110101000001010011010111110101001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~13_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~18_combout\); + +-- Location: LABCELL_X10_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~18_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~18_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101111111010111100010000010100001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1063~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[20]~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~19_combout\); + +-- Location: FF_X10_Y27_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~19_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(20)); + +-- Location: LABCELL_X10_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001000100010001000001111000011110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~13_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~15_combout\); + +-- Location: LABCELL_X10_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~15_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~15_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~15_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~15_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000101011111110111100010000010100001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1063~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[20]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~16_combout\); + +-- Location: FF_X10_Y27_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~16_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(20)); + +-- Location: LABCELL_X10_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~13_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~13_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~20_combout\); + +-- Location: LABCELL_X10_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~20_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~20_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(20) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1063~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[20]~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~21_combout\); + +-- Location: FF_X10_Y27_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~21_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(20)); + +-- Location: LABCELL_X10_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(20) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(20)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(20))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(20)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~0_combout\); + +-- Location: LABCELL_X6_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~13_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~19_combout\); + +-- Location: LABCELL_X6_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~19_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(20) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~19_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000011110111011100111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1063~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[20]~19_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~20_combout\); + +-- Location: FF_X6_Y29_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(20)); + +-- Location: LABCELL_X6_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~13_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~18_combout\); + +-- Location: LABCELL_X6_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~18_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~18_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000110111001111111100010011000000001101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1063~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[20]~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~19_combout\); + +-- Location: FF_X6_Y29_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~19_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(20)); + +-- Location: LABCELL_X6_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~22_combout\); + +-- Location: LABCELL_X6_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~22_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~22_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000111111110111001100000000010011001111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1063~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[20]~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~23_combout\); + +-- Location: FF_X6_Y30_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~23_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(20)); + +-- Location: MLABCELL_X13_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111000101110001010011010100110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~13_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~16_combout\); + +-- Location: MLABCELL_X13_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~16_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~16_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~16_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~16_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100111110101111111000000001000001011111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1063~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[20]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~17_combout\); + +-- Location: FF_X13_Y28_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(20)); + +-- Location: LABCELL_X6_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(20) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(20))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(20))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~1_combout\); + +-- Location: MLABCELL_X9_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\); + +-- Location: MLABCELL_X9_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~29_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\); + +-- Location: LABCELL_X12_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~29_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~29_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~27_combout\); + +-- Location: LABCELL_X12_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~27_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~27_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~27_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~27_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000111111111011101000000000000101011111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1064~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[19]~27_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~28_combout\); + +-- Location: FF_X12_Y30_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~28_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(19)); + +-- Location: LABCELL_X12_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110000010101010011000001010101001111110101010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~29_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~23_combout\); + +-- Location: LABCELL_X12_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~23_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~23_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~23_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~23_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100000110011111110111100010000001100001101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1064~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[19]~23_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~24_combout\); + +-- Location: FF_X12_Y30_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(19)); + +-- Location: LABCELL_X12_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110000010101010011000001010101001111110101010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~29_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~26_combout\); + +-- Location: LABCELL_X12_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~26_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~26_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101111111010111100010000010100001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1064~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[19]~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~27_combout\); + +-- Location: FF_X12_Y30_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~27_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(19)); + +-- Location: LABCELL_X12_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~29_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~29_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~28_combout\); + +-- Location: LABCELL_X12_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~28_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~28_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~28_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000111111011111110000000001000000111111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1064~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[19]~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~29_combout\); + +-- Location: FF_X12_Y30_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~29_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(19)); + +-- Location: LABCELL_X12_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(19) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(19) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(19) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(19) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~0_combout\); + +-- Location: LABCELL_X12_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101000001010000010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~29_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~24_combout\); + +-- Location: LABCELL_X12_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~24_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~24_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~24_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~24_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000010111111001111111000000001000000111111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1064~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[19]~24_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~25_combout\); + +-- Location: FF_X12_Y28_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(19)); + +-- Location: LABCELL_X10_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~29_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~30_combout\); + +-- Location: LABCELL_X7_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~30_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~30_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101110101111111100010101000000001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1064~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[19]~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~31_combout\); + +-- Location: FF_X7_Y30_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~31_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(19)); + +-- Location: LABCELL_X10_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~29_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~26_combout\); + +-- Location: MLABCELL_X9_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~26_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~26_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000110111111100111100010000001100001101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1064~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[19]~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~27_combout\); + +-- Location: FF_X9_Y30_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~27_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(19)); + +-- Location: LABCELL_X10_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000011011000010100001101101001110010111110100111001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~29_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~27_combout\); + +-- Location: MLABCELL_X9_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~27_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~27_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~27_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~27_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000000110111111101110100000010001000101101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1064~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[19]~27_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~28_combout\); + +-- Location: FF_X9_Y31_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~28_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(19)); + +-- Location: MLABCELL_X4_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(19) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(19) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(19) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(19) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~1_combout\); + +-- Location: MLABCELL_X9_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\); + +-- Location: LABCELL_X14_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~46\); + +-- Location: LABCELL_X14_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~2\); + +-- Location: LABCELL_X14_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~22\); + +-- Location: LABCELL_X14_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~26\); + +-- Location: LABCELL_X14_Y15_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~30\); + +-- Location: LABCELL_X14_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~14\); + +-- Location: LABCELL_X14_Y15_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~6\); + +-- Location: LABCELL_X16_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector195~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~5_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000100110000011000010011000111111001101110011111100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~1_combout\); + +-- Location: LABCELL_X16_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector195~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector195~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector195~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000010000000111000011011111110111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector195~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~0_combout\); + +-- Location: LABCELL_X16_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[21]_NEW3346\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[21]_OTERM3347\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(21))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # ((\myVirtualToplevel|MEM_DATA_READ[21]~10_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector195~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- (\myVirtualToplevel|MEM_DATA_READ[21]~10_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~1_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector195~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[21]_OTERM3347\); + +-- Location: FF_X16_Y13_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[21]_OTERM3347\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(21)); + +-- Location: LABCELL_X16_Y13_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector196~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~13_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000100110000011000010011000111111001101110011111100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~1_combout\); + +-- Location: LABCELL_X16_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector196~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector196~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector196~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000001100000101000011111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector196~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~0_combout\); + +-- Location: FF_X16_Y13_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[20]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[20]~DUPLICATE_q\); + +-- Location: LABCELL_X16_Y13_N24 +\myVirtualToplevel|IO_SELECT~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_SELECT~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(21) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(22) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[20]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[20]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~DUPLICATE_q\, + combout => \myVirtualToplevel|IO_SELECT~0_combout\); + +-- Location: LABCELL_X17_Y13_N36 +\myVirtualToplevel|UART0_CS\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0_CS~combout\ = ( \myVirtualToplevel|Equal3~1_combout\ & ( (\myVirtualToplevel|IO_SELECT~2_combout\ & (\myVirtualToplevel|IO_SELECT~0_combout\ & (\myVirtualToplevel|IO_SELECT~1_combout\ & \myVirtualToplevel|Equal3~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000010000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\, + datad => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_Equal3~1_combout\, + combout => \myVirtualToplevel|UART0_CS~combout\); + +-- Location: LABCELL_X12_Y9_N18 +\myVirtualToplevel|UART0|TX_ENABLE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_ENABLE~0_combout\ = ( \myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011000000000000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\, + combout => \myVirtualToplevel|UART0|TX_ENABLE~0_combout\); + +-- Location: FF_X12_Y9_N4 +\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_ENABLE_FIFO~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|UART0|TX_ENABLE~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\); + +-- Location: MLABCELL_X9_Y6_N39 +\myVirtualToplevel|UART0|RX_DATA[7]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA[7]~0_combout\ = ( !\myVirtualToplevel|UART0|RX_DATA_READY~q\ & ( (!\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & ((!\myVirtualToplevel|UART0|Equal2~4_combout\))) # +-- (\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & (\myVirtualToplevel|UART0|RX_INTR~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111100000101101011110000010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_Equal2~4_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\, + combout => \myVirtualToplevel|UART0|RX_DATA[7]~0_combout\); + +-- Location: FF_X10_Y5_N44 +\myVirtualToplevel|UART0|RX_FIFO~19\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO~19_q\); + +-- Location: FF_X10_Y5_N38 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE_q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(18)); + +-- Location: LABCELL_X10_Y5_N42 +\myVirtualToplevel|UART0|RX_DATA~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA~18_combout\ = ( \myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & +-- ((\myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE_q\))) # (\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & (\myVirtualToplevel|UART0|RX_FIFO~19_q\)) ) ) ) # ( !\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ( +-- \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(18)) # (\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\) ) ) ) # ( \myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ( +-- !\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ((\myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE_q\))) # (\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & +-- (\myVirtualToplevel|UART0|RX_FIFO~19_q\)) ) ) ) # ( !\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & +-- \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(18)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000100011011101101011111010111110001000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~19_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(18), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\, + dataf => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|UART0|RX_DATA~18_combout\); + +-- Location: LABCELL_X10_Y6_N36 +\myVirtualToplevel|UART0|RX_DATA[1]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA[1]~19_combout\ = ( \myVirtualToplevel|UART0|RX_DATA~18_combout\ & ( ((\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\ & \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(1)) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_DATA~18_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA\(1) & ((!\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\) # (!\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(1), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA~18_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA[1]~19_combout\); + +-- Location: FF_X10_Y6_N37 +\myVirtualToplevel|UART0|RX_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_DATA[1]~19_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_DATA\(1)); + +-- Location: LABCELL_X10_Y6_N45 +\myVirtualToplevel|UART0|RX_FULL_V~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_FULL_V~0_combout\ = ( \myVirtualToplevel|UART0|Equal3~2_combout\ & ( (\myVirtualToplevel|UART0|RX_FULL_V~q\) # (\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\) ) ) # ( !\myVirtualToplevel|UART0|Equal3~2_combout\ & ( +-- (!\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ & \myVirtualToplevel|UART0|RX_FULL_V~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FULL_V~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_Equal3~2_combout\, + combout => \myVirtualToplevel|UART0|RX_FULL_V~0_combout\); + +-- Location: FF_X10_Y6_N46 +\myVirtualToplevel|UART0|RX_FULL_V\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_FULL_V~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FULL_V~q\); + +-- Location: MLABCELL_X13_Y5_N54 +\myVirtualToplevel|UART1|RX_FULL_V~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_FULL_V~0_combout\ = ( \myVirtualToplevel|UART1|Equal3~2_combout\ & ( (\myVirtualToplevel|UART1|RX_FULL_V~q\) # (\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\) ) ) # ( !\myVirtualToplevel|UART1|Equal3~2_combout\ & ( +-- (!\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & \myVirtualToplevel|UART1|RX_FULL_V~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FULL_V~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Equal3~2_combout\, + combout => \myVirtualToplevel|UART1|RX_FULL_V~0_combout\); + +-- Location: FF_X13_Y5_N55 +\myVirtualToplevel|UART1|RX_FULL_V\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_FULL_V~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FULL_V~q\); + +-- Location: FF_X13_Y6_N20 +\myVirtualToplevel|UART1|RX_FIFO~19\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER\(2), + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO~19_q\); + +-- Location: FF_X13_Y6_N1 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER\(2), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(18)); + +-- Location: MLABCELL_X13_Y6_N18 +\myVirtualToplevel|UART1|RX_DATA~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA~18_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(2) & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) # (\myVirtualToplevel|UART1|RX_FIFO~19_q\) ) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_BUFFER\(2) & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (\myVirtualToplevel|UART1|RX_FIFO~19_q\ & \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) ) ) ) # ( \myVirtualToplevel|UART1|RX_BUFFER\(2) & ( +-- !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(18)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & +-- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a1\)) ) ) ) # ( !\myVirtualToplevel|UART1|RX_BUFFER\(2) & ( !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & +-- ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(18)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a1\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~19_q\, + datab => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(18), + datae => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(2), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA~18_combout\); + +-- Location: MLABCELL_X13_Y6_N57 +\myVirtualToplevel|UART1|RX_DATA[1]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA[1]~19_combout\ = ( \myVirtualToplevel|UART1|RX_DATA~18_combout\ & ( ((\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\)) # (\myVirtualToplevel|UART1|RX_DATA\(1)) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_DATA~18_combout\ & ( (\myVirtualToplevel|UART1|RX_DATA\(1) & ((!\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\) # (!\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(1), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA~18_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA[1]~19_combout\); + +-- Location: FF_X13_Y6_N58 +\myVirtualToplevel|UART1|RX_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_DATA[1]~19_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_DATA\(1)); + +-- Location: MLABCELL_X13_Y10_N6 +\myVirtualToplevel|IO_DATA_READ~98\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~98_combout\ = ( \myVirtualToplevel|UART1|RX_DATA\(1) & ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # +-- (\myVirtualToplevel|UART1|RX_FULL_V~q\))) ) ) ) # ( !\myVirtualToplevel|UART1|RX_DATA\(1) & ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|UART1|RX_FULL_V~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) ) ) # ( \myVirtualToplevel|UART1|RX_DATA\(1) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|UART0|RX_FULL_V~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_DATA\(1) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|UART0|RX_FULL_V~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010000000000000011001100110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FULL_V~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FULL_V~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(1), + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|IO_DATA_READ~98_combout\); + +-- Location: FF_X17_Y11_N4 +\myVirtualToplevel|MILLISEC_UP_COUNTER[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~89_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER[1]~DUPLICATE_q\); + +-- Location: FF_X12_Y12_N4 +\myVirtualToplevel|SECOND_DOWN_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~45_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(1)); + +-- Location: MLABCELL_X13_Y12_N42 +\myVirtualToplevel|IO_DATA_READ~95\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~95_combout\ = ( \myVirtualToplevel|MILLISEC_UP_COUNTER[1]~DUPLICATE_q\ & ( \myVirtualToplevel|SECOND_DOWN_COUNTER\(1) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( !\myVirtualToplevel|MILLISEC_UP_COUNTER[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|SECOND_DOWN_COUNTER\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) # (\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1)))) ) ) ) # ( \myVirtualToplevel|MILLISEC_UP_COUNTER[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|SECOND_DOWN_COUNTER\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) ) ) ) # ( !\myVirtualToplevel|MILLISEC_UP_COUNTER[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|SECOND_DOWN_COUNTER\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100000000000111011100110000011101001100110001110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datae => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(1), + combout => \myVirtualToplevel|IO_DATA_READ~95_combout\); + +-- Location: LABCELL_X7_Y11_N42 +\myVirtualToplevel|IO_DATA_READ~94\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~94_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|RTC_DAY_COUNTER\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|RTC_YEAR_COUNTER\(1)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|RTC_DAY_COUNTER\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # +-- (\myVirtualToplevel|RTC_HOUR_COUNTER\(1)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|RTC_DAY_COUNTER\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|RTC_YEAR_COUNTER\(1)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|RTC_DAY_COUNTER\(1) & ( (\myVirtualToplevel|RTC_HOUR_COUNTER\(1) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000010101010000111100110011111111110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(1), + datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(1), + combout => \myVirtualToplevel|IO_DATA_READ~94_combout\); + +-- Location: LABCELL_X10_Y10_N42 +\myVirtualToplevel|IO_DATA_READ~96\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~96_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # (\myVirtualToplevel|RTC_MINUTE_COUNTER\(1)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (\myVirtualToplevel|RTC_SECOND_COUNTER\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|RTC_MINUTE_COUNTER\(1)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (\myVirtualToplevel|RTC_SECOND_COUNTER\(1))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000001010000010100010001101110111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(1), + datac => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(1), + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(1), + combout => \myVirtualToplevel|IO_DATA_READ~96_combout\); + +-- Location: LABCELL_X10_Y10_N48 +\myVirtualToplevel|IO_DATA_READ~97\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~97_combout\ = ( \myVirtualToplevel|IO_DATA_READ~96_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (((\myVirtualToplevel|IO_DATA_READ~95_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ((\myVirtualToplevel|IO_DATA_READ~94_combout\)))) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~96_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (\myVirtualToplevel|IO_DATA_READ~95_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ((\myVirtualToplevel|IO_DATA_READ~94_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000011001000010000001100100101010001110110010101000111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ~95_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ~94_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~96_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~97_combout\); + +-- Location: LABCELL_X14_Y10_N12 +\myVirtualToplevel|IO_DATA_READ~99\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~99_combout\ = ( \myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ( \myVirtualToplevel|UART1|Add9~31_sumout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & ((\myVirtualToplevel|IO_DATA_READ~98_combout\))) # +-- (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|UART0|RX_DATA\(1))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ( \myVirtualToplevel|UART1|Add9~31_sumout\ & ( (\myVirtualToplevel|IO_DATA_READ~97_combout\) # +-- (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ( !\myVirtualToplevel|UART1|Add9~31_sumout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & ((\myVirtualToplevel|IO_DATA_READ~98_combout\))) +-- # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|UART0|RX_DATA\(1))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ( !\myVirtualToplevel|UART1|Add9~31_sumout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & +-- \myVirtualToplevel|IO_DATA_READ~97_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000111010001110100110011111111110001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(1), + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~70_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ~98_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ~97_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~46_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add9~31_sumout\, + combout => \myVirtualToplevel|IO_DATA_READ~99_combout\); + +-- Location: FF_X14_Y10_N13 +\myVirtualToplevel|IO_DATA_READ[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~99_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(1)); + +-- Location: LABCELL_X19_Y9_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[1]~feeder_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[1]~feeder_combout\); + +-- Location: FF_X19_Y9_N20 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[1]~feeder_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(1)); + +-- Location: FF_X20_Y7_N26 +\myVirtualToplevel|SD_ADDR[0][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][1]~q\); + +-- Location: LABCELL_X19_Y9_N36 +\myVirtualToplevel|Mux82~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux82~0_combout\ = ( \myVirtualToplevel|SD_ADDR[0][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\))))) ) ) # ( +-- !\myVirtualToplevel|SD_ADDR[0][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101000001000001010110001100100111011000110010011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(1), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_ADDR[0][1]~q\, + combout => \myVirtualToplevel|Mux82~0_combout\); + +-- Location: FF_X19_Y9_N37 +\myVirtualToplevel|IO_DATA_READ_SD[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux82~0_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(1)); + +-- Location: FF_X17_Y14_N59 +\myVirtualToplevel|INT_ENABLE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(1)); + +-- Location: FF_X17_Y14_N38 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INT_ENABLE\(1), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(1)); + +-- Location: LABCELL_X17_Y14_N36 +\myVirtualToplevel|MEM_DATA_READ[1]~63\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[1]~63_combout\ = ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(1) & ( \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ & ((\myVirtualToplevel|IO_DATA_READ_SD\(1)))) # +-- (\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ & (\myVirtualToplevel|IO_DATA_READ\(1))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(1) & ( \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ & +-- ((\myVirtualToplevel|IO_DATA_READ_SD\(1)))) # (\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ & (\myVirtualToplevel|IO_DATA_READ\(1))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(1) & ( !\myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\) # (!\myVirtualToplevel|SOCCFG_CS~combout\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(1) & ( !\myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ & ( (\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ +-- & !\myVirtualToplevel|SOCCFG_CS~combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000111111111100110000011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(1), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(1), + datad => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(1), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~35_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[1]~63_combout\); + +-- Location: LABCELL_X24_Y17_N30 +\myVirtualToplevel|MEM_DATA_READ[1]~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[1]~65_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ & \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\)) # +-- (\myVirtualToplevel|MEM_DATA_READ[1]~64_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[1]~63_combout\) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[1]~64_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101011111001111110111111100001111010111110011111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]~35_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~63_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~64_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[1]~65_combout\); + +-- Location: FF_X24_Y17_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[1]~65_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(1)); + +-- Location: LABCELL_X24_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[1]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[1]~feeder_combout\); + +-- Location: FF_X24_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[1]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(1)); + +-- Location: LABCELL_X24_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(1)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\); + +-- Location: FF_X2_Y33_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_NEW_REG1208\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209\); + +-- Location: FF_X2_Y33_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[8]_NEW_REG1220\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~19_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[8]_OTERM1221\); + +-- Location: LABCELL_X2_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[8]_OTERM1221\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[8]_OTERM1221\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111111000000011111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM902\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1209\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[8]_OTERM1221\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~19_combout\); + +-- Location: MLABCELL_X4_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~19_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100001111000011110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~0_combout\); + +-- Location: LABCELL_X20_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(8))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(8)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111001100110011111100110011001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~1_combout\); + +-- Location: LABCELL_X21_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010000000000000000011110000101000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~2_combout\); + +-- Location: LABCELL_X21_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100000000000000001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~0_combout\); + +-- Location: LABCELL_X14_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40_combout\); + +-- Location: LABCELL_X17_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\); + +-- Location: LABCELL_X14_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011010101100001011101000010101000111111011010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~29_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~41_combout\); + +-- Location: LABCELL_X20_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~73_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~41_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~41_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~41_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~41_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000000100010101000100001010111011101111101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~40_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~41_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~73_combout\); + +-- Location: LABCELL_X17_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000101010001000000010101001110000011110100111000001111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~41_combout\); + +-- Location: LABCELL_X17_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~74\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~74_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~41_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~41_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~74_combout\); + +-- Location: LABCELL_X21_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~17_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~73_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~74_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~0_combout\) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~73_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000111111111000000011111111100100011111111110010001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~73_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~74_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~17_combout\); + +-- Location: MLABCELL_X18_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001100000000111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~1_combout\); + +-- Location: MLABCELL_X18_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add34~77_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111111001111100010101000101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~77_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~2_combout\); + +-- Location: LABCELL_X25_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101111101011111010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~7_combout\); + +-- Location: LABCELL_X25_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~8_combout\); + +-- Location: LABCELL_X25_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~5_combout\); + +-- Location: LABCELL_X25_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~6_combout\); + +-- Location: MLABCELL_X28_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~8_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~8_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~8_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~8_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011100010101001101101000110010101111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~9_combout\); + +-- Location: MLABCELL_X28_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~3_combout\); + +-- Location: LABCELL_X29_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~1_combout\); + +-- Location: LABCELL_X25_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~0_combout\); + +-- Location: LABCELL_X32_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~2_combout\); + +-- Location: LABCELL_X29_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~3_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110111010101000011011010101010001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~4_combout\); + +-- Location: MLABCELL_X28_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~9_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\); + +-- Location: LABCELL_X21_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~17_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~77_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~17_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~77_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~17_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~77_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001000000011000000100000001100000010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~77_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~3_combout\); + +-- Location: MLABCELL_X18_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~5_combout\); + +-- Location: MLABCELL_X18_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000000000101010101010000010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal141~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~7_combout\); + +-- Location: MLABCELL_X18_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~4_combout\); + +-- Location: MLABCELL_X18_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~85_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ $ +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add36~85_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add36~85_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001110101011010101111010101101010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~85_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~8_combout\); + +-- Location: LABCELL_X17_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~77_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~77_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010111100001010000011001100100010001100000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~77_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~6_combout\); + +-- Location: MLABCELL_X18_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~6_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~5_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~5_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011111111111111111111111111111100111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~9_combout\); + +-- Location: MLABCELL_X18_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~13_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~9_combout\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~9_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0011001111111111001100111111111100000010111111110010001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~13_combout\); + +-- Location: LABCELL_X21_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000010000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~11_combout\); + +-- Location: LABCELL_X21_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~10_combout\); + +-- Location: LABCELL_X21_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~11_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100010001010101010001000101010101000100010101010100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~12_combout\); + +-- Location: LABCELL_X21_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~12_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~12_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~12_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~2_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector997~3_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110011011100110111001111111111011101110111011101110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~3_combout\); + +-- Location: FF_X21_Y24_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(8)); + +-- Location: FF_X20_Y16_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector350~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[8]~DUPLICATE_q\); + +-- Location: LABCELL_X21_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[8]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(8) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[8]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(8) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\); + +-- Location: FF_X20_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~DUPLICATE_q\); + +-- Location: FF_X19_Y16_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(8)); + +-- Location: LABCELL_X20_Y18_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(8) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\); + +-- Location: MLABCELL_X9_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[8]_NEW3003\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[8]_OTERM3004\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000001011011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[8]_OTERM3004\); + +-- Location: FF_X9_Y24_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[8]_OTERM3004\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(8)); + +-- Location: MLABCELL_X9_Y24_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[8]_NEW3131\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[8]_OTERM3132\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(8) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[8]_OTERM3132\); + +-- Location: FF_X9_Y24_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[8]_OTERM3132\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(8)); + +-- Location: LABCELL_X12_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[8]_NEW3195\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[8]_OTERM3196\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[8]_OTERM3196\); + +-- Location: FF_X12_Y24_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[8]_OTERM3196\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(8)); + +-- Location: MLABCELL_X9_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[8]_NEW3067\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[8]_OTERM3068\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(8) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[8]_OTERM3068\); + +-- Location: FF_X9_Y24_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[8]_OTERM3068\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(8)); + +-- Location: MLABCELL_X9_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux97~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(8))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(8) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(8) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(8))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000000000101010100001111001100111111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~0_combout\); + +-- Location: MLABCELL_X9_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[8]_NEW2939\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[8]_OTERM2940\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000010111111000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[8]_OTERM2940\); + +-- Location: FF_X9_Y24_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[8]_OTERM2940\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(8)); + +-- Location: MLABCELL_X9_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[8]_NEW2811\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[8]_OTERM2812\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(8) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[8]_OTERM2812\); + +-- Location: FF_X9_Y24_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[8]_OTERM2812\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(8)); + +-- Location: MLABCELL_X9_Y24_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[8]_NEW2747\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[8]_OTERM2748\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[8]_OTERM2748\); + +-- Location: FF_X9_Y24_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[8]_OTERM2748\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(8)); + +-- Location: MLABCELL_X9_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[8]_NEW2875\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[8]_OTERM2876\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[8]_OTERM2876\); + +-- Location: FF_X9_Y24_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[8]_OTERM2876\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(8)); + +-- Location: MLABCELL_X9_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux97~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(8))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(8))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(8))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(8))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000011001010011000101110100101010001110110110111001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~1_combout\); + +-- Location: MLABCELL_X9_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux97~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux97~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux97~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux97~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~2_combout\); + +-- Location: MLABCELL_X9_Y14_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~feeder_combout\); + +-- Location: FF_X9_Y14_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8)); + +-- Location: FF_X20_Y7_N29 +\myVirtualToplevel|SD_ADDR[0][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8), + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][8]~q\); + +-- Location: LABCELL_X16_Y10_N18 +\myVirtualToplevel|Mux75~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux75~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (!\myVirtualToplevel|Mux75~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( +-- (\myVirtualToplevel|SD_ADDR[0][8]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Mux75~0_combout\, + datab => \myVirtualToplevel|ALT_INV_SD_ADDR[0][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + combout => \myVirtualToplevel|Mux75~1_combout\); + +-- Location: FF_X16_Y10_N20 +\myVirtualToplevel|IO_DATA_READ_SD[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux75~1_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(8)); + +-- Location: LABCELL_X20_Y11_N18 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[0]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[0]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[0]~7_combout\); + +-- Location: M10K_X22_Y10_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X12_Y11_N51 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~4_combout\ = ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ & ( ((\myVirtualToplevel|UART0|RX_INTR~q\ & \myVirtualToplevel|INT_ENABLE\(8))) # (\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(8)) ) ) # +-- ( !\myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ & ( (\myVirtualToplevel|UART0|RX_INTR~q\ & \myVirtualToplevel|INT_ENABLE\(8)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~q\, + datac => \myVirtualToplevel|ALT_INV_INT_ENABLE\(8), + datad => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(8), + dataf => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\, + combout => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~4_combout\); + +-- Location: FF_X12_Y11_N52 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~4_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(8)); + +-- Location: FF_X14_Y11_N10 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|status[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(8)); + +-- Location: LABCELL_X14_Y11_N21 +\myVirtualToplevel|IO_DATA_READ_INTRCTL~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_INTRCTL~5_combout\ = ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|INT_ENABLE\(8)) ) ) # ( +-- !\myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(8) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|INT_ENABLE\(8)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ALT_INV_INT_ENABLE\(8), + dataf => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(8), + combout => \myVirtualToplevel|IO_DATA_READ_INTRCTL~5_combout\); + +-- Location: FF_X14_Y11_N22 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_INTRCTL~5_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(8)); + +-- Location: FF_X20_Y12_N2 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b\(0)); + +-- Location: LABCELL_X10_Y12_N3 +\myVirtualToplevel|IO_DATA_READ[8]~64\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[8]~64_combout\ = ( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) +-- # (\myVirtualToplevel|RTC_MILLISEC_COUNTER\(8))))) ) ) # ( !\myVirtualToplevel|RTC_MICROSEC_COUNTER\(8) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|RTC_MILLISEC_COUNTER\(8)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000000000000100000010000000110000001000000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(8), + dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(8), + combout => \myVirtualToplevel|IO_DATA_READ[8]~64_combout\); + +-- Location: FF_X14_Y12_N25 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~53_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(8)); + +-- Location: FF_X17_Y11_N25 +\myVirtualToplevel|MILLISEC_UP_COUNTER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~77_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(8)); + +-- Location: LABCELL_X12_Y10_N54 +\myVirtualToplevel|Mux264~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux264~0_combout\ = ( \myVirtualToplevel|SECOND_DOWN_COUNTER\(8) & ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(8) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(8))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(8))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( !\myVirtualToplevel|SECOND_DOWN_COUNTER\(8) & ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(8) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(8)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))))) ) ) ) # ( \myVirtualToplevel|SECOND_DOWN_COUNTER\(8) & ( !\myVirtualToplevel|MILLISEC_UP_COUNTER\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(8)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))))) ) ) ) # ( !\myVirtualToplevel|SECOND_DOWN_COUNTER\(8) & ( !\myVirtualToplevel|MILLISEC_UP_COUNTER\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(8)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011111101011111001100000101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(8), + datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(8), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(8), + combout => \myVirtualToplevel|Mux264~0_combout\); + +-- Location: LABCELL_X12_Y10_N0 +\myVirtualToplevel|IO_DATA_READ[8]~100\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[8]~100_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ( (!\myVirtualToplevel|TIMER0_CS~1_combout\ & (((\myVirtualToplevel|UART1|Mux0~0_combout\)))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (((\myVirtualToplevel|Mux264~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (((\myVirtualToplevel|IO_DATA_READ[8]~64_combout\)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ( (!\myVirtualToplevel|TIMER0_CS~1_combout\ & (((\myVirtualToplevel|UART1|Mux0~0_combout\)))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|UART1|Mux0~0_combout\ & \myVirtualToplevel|RTC_YEAR_COUNTER\(8)))) # (\myVirtualToplevel|IO_DATA_READ[8]~64_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0011001100110011001100110011001100001010010111110000000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\, + datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(8), + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ[8]~64_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datag => \myVirtualToplevel|ALT_INV_Mux264~0_combout\, + combout => \myVirtualToplevel|IO_DATA_READ[8]~100_combout\); + +-- Location: FF_X12_Y10_N1 +\myVirtualToplevel|IO_DATA_READ[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ[8]~100_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(8)); + +-- Location: LABCELL_X21_Y12_N48 +\myVirtualToplevel|Mux94~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux94~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000010100000010100001010000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|Mux94~0_combout\); + +-- Location: FF_X21_Y12_N49 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux94~0_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(8)); + +-- Location: LABCELL_X20_Y12_N45 +\myVirtualToplevel|MEM_DATA_READ[8]~82_RESYN8731\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[8]~82_RESYN8731_BDD8732\ = ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(8) ) ) # ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(8) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(8), + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(8), + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[8]~82_RESYN8731_BDD8732\); + +-- Location: LABCELL_X20_Y12_N24 +\myVirtualToplevel|MEM_DATA_READ[8]~82\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[8]~82_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[8]~82_RESYN8731_BDD8732\ & ( \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b\(0) ) ) ) # +-- ( !\myVirtualToplevel|MEM_DATA_READ[8]~82_RESYN8731_BDD8732\ & ( \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b\(0) ) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[8]~82_RESYN8731_BDD8732\ & ( !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( ((!\myVirtualToplevel|IO_SELECT~combout\) # (!\myVirtualToplevel|INTR0_CS~combout\)) # (\myVirtualToplevel|IO_DATA_READ_INTRCTL\(8)) ) ) ) # +-- ( !\myVirtualToplevel|MEM_DATA_READ[8]~82_RESYN8731_BDD8732\ & ( !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( (!\myVirtualToplevel|IO_SELECT~combout\) # ((\myVirtualToplevel|IO_DATA_READ_INTRCTL\(8) & \myVirtualToplevel|INTR0_CS~combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011011101111111111101110100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(8), + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datad => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~82_RESYN8731_BDD8732\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[8]~82_combout\); + +-- Location: FF_X20_Y12_N29 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]_NEW_REG38\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]~23_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]_OTERM39\); + +-- Location: LABCELL_X20_Y12_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]~23_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM17\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]_OTERM39\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM17\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]_OTERM39\) ) ) ) # ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM17\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]_OTERM39\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM17\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]_OTERM39\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[8]_OTERM39\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM17\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]~23_combout\); + +-- Location: M10K_X22_Y9_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011113333331111113333306E11511440444055020E53A23818086E25D12023A62940000030A0C18C0850001A85B08B6661007058D38641508C7114515041100140000024E02520A5A2C898E30A0090984615920828804840102040021C06A7FFFFE0B7FE8A6319896F6718118B3252403BCA9B7D22BC5746A7AF", + mem_init2 => "4C73628B662B77DC81701917DD24A0E0917D340BA4345EF5202598E9DEA2CC54F135E02241B0B49539DFBD7DD7BDF4F5EA034C20A502D0E00701397C03F0CED3735CEC4161EA53ECB1F529865DC6F2EA2B6D14E7E1E57BAA0DAF777DF1F362000FF532FDB7CB873515B7F7391F02187A510128633E5EF0E31F64649B64A0F4BD659E1B8C56C6C11DECF8ECB304723B4472014C7914974C2C88671D2B15A140356D24F1548C402169FE9C28C77B563A0B3AEC5ACE034BD47106230042DCEDE3549501DE8B2E506EF482A5A9F1E45E50D31AB22187D358A9848218883E8F218CCB51289A271D99847291CACF08614A039CC06B51464431378CA60F57F5C30591CA", + mem_init1 => "E8E181DD9045190226D077286C8D0744C101EC657544E687E3000774D90628B83E4ED9AFA48222658054F38B6933380CC821412016A297831263C15880755F104A644B0689AE8BA4312160241EAAE2882843397882C52E8005703C251C1B0354B509DC488D502BA101FC49F7B241A082836B91A28B889A32CFA21D12A48E6EB30B9BBCC5A8F1A824963A94B441D7B439A2893F20A3047D52EE91B1104AF3B4557DE0018336A12E304C935482CF3532C24942049F91182540724C40D6028B1C84BB13C864312B69C0850EF9D10E4E3381AB1C11013C04202638109EB8E076E0ED8750DBD7188963B6034FAB0DA8B2F3D0B709A7CC11C298A2372393983C737EE4", + mem_init0 => "08C2D58AA8421CC2248B3958213E6116C403496FA25946B9D34E78C1BF1D3D6103B8242C0F203C698BC322C5DCC768CACBDEE81D53F982787974DFA1E639662E2E0361F512F513C83A282445B6A925EC386C920138B1B556A2C58B162C5C7A6AA819840EC81881D103103A21AD0683419340947C0D0E820AC88BED8755037F1B2D02F79AB18C62580110A44511C201507118EE133B891A3A30E7192F34689104A490A249A2A00D026AB914556520C8CD5724251516214A003A221440000040404000000400444004028885100A221440FFFFFFFFFFFB6DB6DB6DB6DFFFFFFFFEFB000300010001706C06061E040603010F071F1C030201000267021F7E000001", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X20_Y12_N12 +\myVirtualToplevel|MEM_DATA_READ[8]~103\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[8]~82_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(8))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]~23_combout\)))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[8]~82_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8~portbdataout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(8))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]~23_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001000100001100110111010000110000010001001111111101110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(8), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~82_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[8]~23_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\); + +-- Location: LABCELL_X12_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~31_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) # ( +-- !\myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(8), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~103_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~31_combout\); + +-- Location: FF_X12_Y15_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_NEW_REG546\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~31_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM547\); + +-- Location: LABCELL_X12_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\)))) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000001111010001000100010001110111000011110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~103_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~30_combout\); + +-- Location: FF_X12_Y15_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_NEW_REG544\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~30_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM545\); + +-- Location: FF_X12_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_NEW_REG542\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM543\); + +-- Location: LABCELL_X12_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM543\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM547\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM543\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM547\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM543\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM545\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM543\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM545\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100111111110011111100000000010001001111111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM547\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM545\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM543\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\); + +-- Location: LABCELL_X25_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~186\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~186_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~186_combout\); + +-- Location: FF_X25_Y31_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~186_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\); + +-- Location: MLABCELL_X23_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~190\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~190_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~190_combout\); + +-- Location: FF_X23_Y33_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~190_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~q\); + +-- Location: LABCELL_X20_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~206\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~206_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~206_combout\); + +-- Location: FF_X20_Y33_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~206_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\); + +-- Location: LABCELL_X21_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~202\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~202_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~202_combout\); + +-- Location: FF_X21_Y34_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~202_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\); + +-- Location: MLABCELL_X23_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~1_combout\); + +-- Location: LABCELL_X21_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~207\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~207_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~207_combout\); + +-- Location: FF_X21_Y33_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~207_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\); + +-- Location: LABCELL_X20_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~203\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~203_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~203_combout\); + +-- Location: FF_X20_Y32_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~203_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\); + +-- Location: FF_X23_Y33_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~191_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\); + +-- Location: MLABCELL_X23_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~191\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~191_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~191_combout\); + +-- Location: FF_X23_Y33_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~191_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~DUPLICATE_q\); + +-- Location: FF_X21_Y33_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~187_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\); + +-- Location: LABCELL_X21_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~187\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~187_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~187_combout\); + +-- Location: FF_X21_Y33_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~187_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~0_combout\); + +-- Location: LABCELL_X20_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~195\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~195_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~195_combout\); + +-- Location: FF_X20_Y33_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~195_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\); + +-- Location: LABCELL_X24_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~199\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~199_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~199_combout\); + +-- Location: FF_X24_Y33_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~199_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\); + +-- Location: FF_X21_Y34_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~211_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~q\); + +-- Location: LABCELL_X21_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~211\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~211_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~211_combout\); + +-- Location: FF_X21_Y34_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~211_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~215\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~215_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~215_combout\); + +-- Location: FF_X24_Y33_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~215_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\); + +-- Location: MLABCELL_X23_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~2_combout\); + +-- Location: LABCELL_X24_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~214\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~214_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~214_combout\); + +-- Location: FF_X24_Y33_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~214_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\); + +-- Location: LABCELL_X21_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~210\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~210_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~210_combout\); + +-- Location: FF_X21_Y34_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~210_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\); + +-- Location: FF_X24_Y33_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~198_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~q\); + +-- Location: LABCELL_X24_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~198\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~198_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~198_combout\); + +-- Location: FF_X24_Y33_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~198_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~194\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~194_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~194_combout\); + +-- Location: FF_X24_Y33_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~194_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\); + +-- Location: LABCELL_X24_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~3_combout\); + +-- Location: MLABCELL_X23_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~2_combout\) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~2_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~4_combout\); + +-- Location: LABCELL_X20_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]_NEW1834\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]_OTERM1835\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]_OTERM1835\); + +-- Location: FF_X20_Y32_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]_OTERM1835\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\); + +-- Location: LABCELL_X20_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]_NEW1836\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]_OTERM1837\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]_OTERM1837\); + +-- Location: FF_X20_Y32_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]_OTERM1837\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\); + +-- Location: LABCELL_X21_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~193\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~193_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~193_combout\); + +-- Location: FF_X21_Y33_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~193_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\); + +-- Location: LABCELL_X21_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~192\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~192_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~192_combout\); + +-- Location: FF_X21_Y33_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~192_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\); + +-- Location: LABCELL_X24_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~7_combout\); + +-- Location: FF_X24_Y35_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~213_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\); + +-- Location: LABCELL_X24_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~213\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~213_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~213_combout\); + +-- Location: FF_X24_Y35_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~213_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~205\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~205_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~205_combout\); + +-- Location: FF_X20_Y32_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~205_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\); + +-- Location: LABCELL_X20_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~204\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~204_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~204_combout\); + +-- Location: FF_X20_Y32_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~204_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\); + +-- Location: FF_X24_Y35_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~212_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\); + +-- Location: LABCELL_X24_Y35_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~212\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~212_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~212_combout\); + +-- Location: FF_X24_Y35_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~212_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~6_combout\); + +-- Location: LABCELL_X24_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~201\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~201_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~201_combout\); + +-- Location: FF_X24_Y32_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~201_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\); + +-- Location: LABCELL_X24_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~200\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~200_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~200_combout\); + +-- Location: FF_X24_Y32_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~200_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\); + +-- Location: LABCELL_X21_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~209\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~209_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~209_combout\); + +-- Location: FF_X21_Y34_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~209_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\); + +-- Location: FF_X21_Y34_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~208_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\); + +-- Location: LABCELL_X24_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~8_combout\); + +-- Location: LABCELL_X24_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~188\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~188_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~188_combout\); + +-- Location: FF_X24_Y32_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~188_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\); + +-- Location: LABCELL_X20_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~189\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~189_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111110100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~189_combout\); + +-- Location: FF_X20_Y32_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~189_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\); + +-- Location: FF_X21_Y34_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~197_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~q\); + +-- Location: LABCELL_X21_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~197\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~197_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~197_combout\); + +-- Location: FF_X21_Y34_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~197_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\); + +-- Location: LABCELL_X21_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~196\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~196_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~196_combout\); + +-- Location: FF_X21_Y34_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~196_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\); + +-- Location: LABCELL_X24_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~5_combout\); + +-- Location: LABCELL_X24_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~6_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~6_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101011101110000010100100010101011110111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~9_combout\); + +-- Location: MLABCELL_X23_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\); + +-- Location: LABCELL_X21_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110101001101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~3_combout\); + +-- Location: LABCELL_X21_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~4_combout\); + +-- Location: LABCELL_X21_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100101111100000000000000000000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~89_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~5_combout\); + +-- Location: MLABCELL_X18_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~26_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~26_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~26_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110000111100001101010101010101011101011111010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~26_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~7_combout\); + +-- Location: LABCELL_X14_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~25_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add35~25_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100101010101000100011110000110000001010000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~25_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~6_combout\); + +-- Location: MLABCELL_X18_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~7_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000100000001100000010000011110000101000001111000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~8_combout\); + +-- Location: LABCELL_X21_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010000000001111101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~9_combout\); + +-- Location: LABCELL_X21_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\); + +-- Location: LABCELL_X24_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\); + +-- Location: MLABCELL_X23_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\); + +-- Location: LABCELL_X24_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\); + +-- Location: LABCELL_X21_Y36_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~18_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~3_combout\); + +-- Location: LABCELL_X21_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\); + +-- Location: LABCELL_X21_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\); + +-- Location: LABCELL_X21_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000000000000000000000111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\); + +-- Location: LABCELL_X21_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\); + +-- Location: LABCELL_X21_Y36_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~2_combout\); + +-- Location: LABCELL_X24_Y35_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\); + +-- Location: LABCELL_X21_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\); + +-- Location: LABCELL_X21_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\); + +-- Location: LABCELL_X21_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\); + +-- Location: LABCELL_X21_Y36_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~1_combout\); + +-- Location: LABCELL_X21_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\); + +-- Location: LABCELL_X21_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\); + +-- Location: LABCELL_X21_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\); + +-- Location: LABCELL_X21_Y36_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111111110101010100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~0_combout\); + +-- Location: LABCELL_X21_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~3_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101010001000010110101101110100001111100011010101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\); + +-- Location: LABCELL_X20_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8703\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8703_BDD8704\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~25_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8703_BDD8704\); + +-- Location: LABCELL_X16_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\)) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~14_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~19_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~32_combout\); + +-- Location: LABCELL_X16_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8699\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8699_BDD8700\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~32_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~32_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\) +-- # ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111101111110101111100001010111010101010101001001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8699_BDD8700\); + +-- Location: LABCELL_X21_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8701\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8701_BDD8702\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8699_BDD8700\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8699_BDD8700\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111110101111100011011000110101110111001000100111011100100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8699_BDD8700\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8701_BDD8702\); + +-- Location: LABCELL_X21_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8703_BDD8704\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8701_BDD8702\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~23_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8703_BDD8704\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8701_BDD8702\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~23_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8703_BDD8704\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8701_BDD8702\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_combout\); + +-- Location: LABCELL_X20_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(18) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ $ (((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110110111101011100011011111010001101100000101011000110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[18]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[18]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\); + +-- Location: LABCELL_X20_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100001111000011110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~0_combout\); + +-- Location: LABCELL_X20_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(18)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(18)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010000000000000000011001000110010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~1_combout\); + +-- Location: LABCELL_X21_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add34~25_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add34~25_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001110111000000000000000000000000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~2_combout\); + +-- Location: FF_X2_Y31_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[18]_NEW_REG1234\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[18]_OTERM1235\); + +-- Location: LABCELL_X2_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM796\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[18]_OTERM1235\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM796\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[18]_OTERM1235\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[18]_OTERM1235\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM796\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~6_combout\); + +-- Location: LABCELL_X2_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~6_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111101010101010111110101010101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~0_combout\); + +-- Location: LABCELL_X7_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM193\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM221\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM193\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM221\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM193\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM221\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM193\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM221\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101010100000101000011001101110011011101110011011100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM221\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM193\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~1_combout\); + +-- Location: LABCELL_X21_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111100000000000010101010000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~2_combout\); + +-- Location: LABCELL_X21_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~9_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector987~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100110011000100010011001100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~3_combout\); + +-- Location: FF_X21_Y21_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(18)); + +-- Location: FF_X19_Y15_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~25_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(18) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\); + +-- Location: FF_X20_Y17_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[18]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\); + +-- Location: LABCELL_X17_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN9301\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN9301_BDD9302\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011100000111011101110000011101110000011101110111000001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN9301_BDD9302\); + +-- Location: LABCELL_X16_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000010110000000101011011010100011010101110100001111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~27_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~25_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~33_combout\); + +-- Location: LABCELL_X17_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~33_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~33_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011000000000101001111110000111100111111000001010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~29_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~33_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~27_combout\); + +-- Location: LABCELL_X17_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~20_combout\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~20_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001000100000001000100011110000111110001111000011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~26_combout\); + +-- Location: MLABCELL_X18_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~27_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~27_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000001010000010110101010111111111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~27_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~28_combout\); + +-- Location: LABCELL_X19_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12798\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12798_BDD12799\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~29_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100101010001010100011111100000000001010100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12798_BDD12799\); + +-- Location: LABCELL_X19_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12800\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12800_BDD12801\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12798_BDD12799\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN9301_BDD9302\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12798_BDD12799\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN9301_BDD9302\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN9301_BDD9302\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~28_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN12798_BDD12799\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12800_BDD12801\); + +-- Location: LABCELL_X19_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12800_BDD12801\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12800_BDD12801\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN12800_BDD12801\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_combout\); + +-- Location: LABCELL_X25_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_RESYN9249\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_RESYN9249_BDD9250\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010100110101010101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_RESYN9249_BDD9250\); + +-- Location: LABCELL_X19_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_RESYN9249_BDD9250\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_RESYN9249_BDD9250\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110000010101010011111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~1_RESYN9249_BDD9250\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_combout\); + +-- Location: MLABCELL_X18_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~29_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011001000111110101100100011111010110010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~2_combout\); + +-- Location: MLABCELL_X18_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~33_combout\); + +-- Location: LABCELL_X24_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~85_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~29_combout\); + +-- Location: MLABCELL_X18_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~33_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~30_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~33_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~29_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~33_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~30_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~33_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~33_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~30_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~33_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110010101000111111001010100011111100101010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~33_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~30_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~3_combout\); + +-- Location: MLABCELL_X18_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110001000111111111000100011111111100011111111111110001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~4_combout\); + +-- Location: LABCELL_X19_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~4_combout\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101010101000000010101010100010111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~5_combout\); + +-- Location: LABCELL_X19_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector986~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011111111110011001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~5_combout\); + +-- Location: FF_X2_Y31_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[19]_NEW_REG1232\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~7_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[19]_OTERM1233\); + +-- Location: LABCELL_X2_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1173\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[19]_OTERM1233\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1173\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[19]_OTERM1233\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[19]_OTERM1233\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1173\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~7_combout\); + +-- Location: LABCELL_X2_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~7_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(19))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(19)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~0_combout\); + +-- Location: LABCELL_X5_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~362_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~362_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~362_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111111001100110011001100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~362_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~1_combout\); + +-- Location: LABCELL_X20_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~1_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000110011001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~2_combout\); + +-- Location: LABCELL_X19_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add34~29_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~2_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100110011001100110000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~29_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~3_combout\); + +-- Location: FF_X19_Y25_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(19)); + +-- Location: FF_X19_Y15_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~29_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(19)); + +-- Location: LABCELL_X19_Y15_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(19) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(19) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\); + +-- Location: MLABCELL_X9_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add19~29_sumout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add19~29_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111110011111100111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~29_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~27_combout\); + +-- Location: LABCELL_X6_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~26\); + +-- Location: LABCELL_X6_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~30\); + +-- Location: MLABCELL_X9_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~29_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~27_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~29_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~27_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~29_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~28_combout\); + +-- Location: MLABCELL_X9_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[19]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[19]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~28_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(19)) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111100000000001111110000000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[19]~29_combout\); + +-- Location: FF_X9_Y25_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[19]~29_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19)); + +-- Location: LABCELL_X6_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(20) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(20) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~14\); + +-- Location: MLABCELL_X4_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(20)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~13_sumout\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(20) & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~15_combout\); + +-- Location: LABCELL_X6_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~13_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~15_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~13_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~13_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~16_combout\); + +-- Location: LABCELL_X6_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~16_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(20)) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(20) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~17_combout\); + +-- Location: FF_X6_Y25_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~17_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(20)); + +-- Location: MLABCELL_X4_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~9_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add19~5_sumout\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~9_combout\); + +-- Location: LABCELL_X5_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|sp~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add21~5_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|sp~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add21~5_sumout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~10_combout\); + +-- Location: FF_X5_Y25_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_NEW_REG1400\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp~10_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1401\); + +-- Location: FF_X5_Y25_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_NEW_REG1398\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1399\); + +-- Location: LABCELL_X5_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1399\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM892\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM894\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1401\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1399\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM892\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM894\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1401\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1399\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM892\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM894\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]_OTERM1401\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]_OTERM1399\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM892\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\); + +-- Location: MLABCELL_X4_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101010000000001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~12_combout\); + +-- Location: LABCELL_X5_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add21~9_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add21~9_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~9_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~13_combout\); + +-- Location: FF_X5_Y25_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_NEW_REG1178\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp~13_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1179\); + +-- Location: LABCELL_X5_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1177\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1179\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1177\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1179\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM894\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM892\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1177\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1179\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM894\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM892\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111000000000000000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM894\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM892\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]_OTERM1177\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]_OTERM1179\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\); + +-- Location: MLABCELL_X4_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\); + +-- Location: MLABCELL_X9_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~10\); + +-- Location: LABCELL_X10_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~16_combout\); + +-- Location: LABCELL_X10_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~16_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~16_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~16_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000110111111100111100010000001100001101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1061~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[22]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~17_combout\); + +-- Location: FF_X10_Y29_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(22)); + +-- Location: LABCELL_X10_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~14_combout\); + +-- Location: LABCELL_X10_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~14_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~14_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(22) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1061~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[22]~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~15_combout\); + +-- Location: FF_X10_Y29_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~15_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(22)); + +-- Location: LABCELL_X10_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~20_combout\); + +-- Location: LABCELL_X10_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~20_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~20_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~20_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~20_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000000110011101111111100010011000000001101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1061~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~21_combout\); + +-- Location: FF_X10_Y29_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~21_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(22)); + +-- Location: LABCELL_X10_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~17_combout\); + +-- Location: LABCELL_X10_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~17_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~17_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~17_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~17_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000101011111110111100010000010100001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1061~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~18_combout\); + +-- Location: FF_X10_Y29_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~18_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(22)); + +-- Location: MLABCELL_X9_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(22))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(22))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(22)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(22)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~1_combout\); + +-- Location: MLABCELL_X9_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~17_combout\); + +-- Location: MLABCELL_X9_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~17_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~17_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~17_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~17_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ +-- & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100111111111111010000000000000001111111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1061~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[22]~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~18_combout\); + +-- Location: FF_X9_Y28_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~18_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(22)); + +-- Location: MLABCELL_X9_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~9_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~13_combout\); + +-- Location: MLABCELL_X9_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~13_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~13_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~13_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000110111111100111100010000001100001101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1061~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[22]~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~14_combout\); + +-- Location: FF_X9_Y28_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~14_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(22)); + +-- Location: LABCELL_X10_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110000000000001111001100110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~9_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~18_combout\); + +-- Location: LABCELL_X10_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~18_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~18_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000111111011111110000000001000000111111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1061~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[22]~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~19_combout\); + +-- Location: FF_X10_Y29_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~19_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(22)); + +-- Location: LABCELL_X10_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000000001010101010101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~16_combout\); + +-- Location: LABCELL_X10_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~16_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~16_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~16_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000110111111100111100010000001100001101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1061~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[22]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~17_combout\); + +-- Location: FF_X10_Y29_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(22)); + +-- Location: LABCELL_X6_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(22) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(22) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(22) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(22) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~0_combout\); + +-- Location: LABCELL_X6_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000000000000000111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\); + +-- Location: LABCELL_X14_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~10\); + +-- Location: LABCELL_X14_Y13_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector194~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~9_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~9_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~9_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000001011010101000001111111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~1_combout\); + +-- Location: LABCELL_X16_Y13_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector194~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector194~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector194~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010000000001010101011110111111101110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector194~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~0_combout\); + +-- Location: FF_X16_Y13_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(22)); + +-- Location: LABCELL_X16_Y13_N21 +\myVirtualToplevel|BRAM_WREN~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|BRAM_WREN~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(22) & \myVirtualToplevel|BRAM_WREN~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000101000000000000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(22), + datad => \myVirtualToplevel|ALT_INV_BRAM_WREN~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + combout => \myVirtualToplevel|BRAM_WREN~1_combout\); + +-- Location: MLABCELL_X23_Y14_N15 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & ( (!\myVirtualToplevel|BRAM_WREN~1_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16) & +-- !\myVirtualToplevel|LessThan3~0_combout\)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~0_combout\)) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & ( ((!\myVirtualToplevel|BRAM_WREN~1_combout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110111111111110111011111111111011100111111111101110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + datab => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\, + datac => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\, + datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM1_WREN~0_combout\, + dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\); + +-- Location: FF_X9_Y14_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(14)); + +-- Location: MLABCELL_X9_Y14_N15 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[6]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[6]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(14) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000000010101111111111111010111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(14), + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[6]~2_combout\); + +-- Location: M10K_X3_Y10_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 6, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 6, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\); + +-- Location: FF_X16_Y9_N25 +\myVirtualToplevel|SD_ADDR[0][14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][14]~q\); + +-- Location: LABCELL_X16_Y9_N36 +\myVirtualToplevel|Mux69~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux69~0_combout\ = ( \myVirtualToplevel|SD_WR\(0) & ( \myVirtualToplevel|SD_ADDR[0][14]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( !\myVirtualToplevel|SD_WR\(0) & ( +-- \myVirtualToplevel|SD_ADDR[0][14]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( \myVirtualToplevel|SD_WR\(0) & ( !\myVirtualToplevel|SD_ADDR[0][14]~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000110000001111000000110000001100001111000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datae => \myVirtualToplevel|ALT_INV_SD_WR\(0), + dataf => \myVirtualToplevel|ALT_INV_SD_ADDR[0][14]~q\, + combout => \myVirtualToplevel|Mux69~0_combout\); + +-- Location: FF_X16_Y9_N37 +\myVirtualToplevel|IO_DATA_READ_SD[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux69~0_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(14)); + +-- Location: FF_X17_Y14_N5 +\myVirtualToplevel|INT_ENABLE[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(14)); + +-- Location: FF_X17_Y14_N46 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INT_ENABLE\(14), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(14)); + +-- Location: FF_X14_Y12_N43 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~17_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(14)); + +-- Location: FF_X13_Y11_N13 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~41_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(14)); + +-- Location: LABCELL_X16_Y11_N12 +\myVirtualToplevel|IO_DATA_READ~112\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~112_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (\myVirtualToplevel|TIMER0_CS~1_combout\ & (\myVirtualToplevel|Equal3~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ((\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(14)))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (((\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(14) & (\myVirtualToplevel|TIMER0_CS~1_combout\ & \myVirtualToplevel|Equal3~0_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((((!\myVirtualToplevel|TIMER0_CS~1_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000000000010101010000000000000000000110110101010100001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(14), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(14), + datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + datag => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(14), + combout => \myVirtualToplevel|IO_DATA_READ~112_combout\); + +-- Location: FF_X16_Y11_N13 +\myVirtualToplevel|IO_DATA_READ[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~112_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(14)); + +-- Location: FF_X19_Y11_N56 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux90~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(14)); + +-- Location: LABCELL_X19_Y11_N54 +\myVirtualToplevel|MEM_DATA_READ[14]~70_RESYN8719\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[14]~70_RESYN8719_BDD8720\ = ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(14) & ( \myVirtualToplevel|SOCCFG_CS~combout\ ) ) # ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(14) & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( +-- \myVirtualToplevel|IO_DATA_READ\(14) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(14) & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(14) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(14), + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(14), + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[14]~70_RESYN8719_BDD8720\); + +-- Location: MLABCELL_X18_Y13_N6 +\myVirtualToplevel|MEM_DATA_READ[14]~70\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[14]~70_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[14]~70_RESYN8719_BDD8720\ & ( +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[14]~70_RESYN8719_BDD8720\ & ( +-- (!\myVirtualToplevel|INTR0_CS~combout\) # ((!\myVirtualToplevel|IO_SELECT~combout\) # (\myVirtualToplevel|IO_DATA_READ_INTRCTL\(14))) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[14]~70_RESYN8719_BDD8720\ +-- & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[14]~70_RESYN8719_BDD8720\ & ( +-- (!\myVirtualToplevel|IO_SELECT~combout\) # ((\myVirtualToplevel|INTR0_CS~combout\ & \myVirtualToplevel|IO_DATA_READ_INTRCTL\(14))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110101001100110011001111111010111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(14), + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~70_RESYN8719_BDD8720\, + combout => \myVirtualToplevel|MEM_DATA_READ[14]~70_combout\); + +-- Location: IOIBUF_X24_Y0_N52 +\SDRAM_DQ[14]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(14), + o => \SDRAM_DQ[14]~input_o\); + +-- Location: DDIOINCELL_X24_Y0_N65 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_NEW_REG84\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[14]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM85\); + +-- Location: FF_X19_Y13_N20 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]_NEW_REG96\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]~14_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]_OTERM97\); + +-- Location: LABCELL_X19_Y13_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]~14_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]_OTERM97\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\) # +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM85\)) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]_OTERM97\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM85\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010111111111101011111111111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]_OTERM85\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[14]_OTERM97\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]~14_combout\); + +-- Location: M10K_X3_Y9_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111111111111100E9151F6E22CE6C7970EF7BEFA18006E61D773AFA7396F7BDEF7B3DF830050000EDDB6FBE76F297E7BF79F7D5ECC73B57BFD5554005FFFE024A221268DAA9B90F21A4094F9765F9A0838D848509122C48A3E9789FFFFE0B0A840A12778A74AF8FB5D5782BFA15F2C371E0903F8EED0", + mem_init2 => "08E506710473236E715DFCF36978FD5E4E36B38EEFB3CC7D0BE411CC8CCA08D1055B0F1FFDDF63D8CB2760C6C31E606200282A141821185CAB63C5BADCF363C20C0D747602AAADEB015556F5A45B5D1D3E1D4BAB5AAE878AB16493D09E5B581AF35EF65B6D9972BD24429C82ADA8702D6AEBE9B1D68F7675B8B22B682E4016A7CEB80BD2524053303B44595DB9D411B9D410C61B812B0C08F23312F0C52117610C8EDD28E2481E1F36A80E526C474F098CC2251A9061ADB2C47E8F2A931350534E985237E64B31A76A7648254854E00C434542D2606042C22FC055567B2882668976589CE302C1050B409532EA5E2A929018AA514D06AE6378D58E2E34F49176", + mem_init1 => "A181C008A062AB0441E8DDB821772A1F16E5AD338AF0AA65A9F9794C3A90DF8789A4A510269F21D10C2CD3AE0E25E805409785E50808665247A184AF4025A6230045ECCA5954B60B01178B6A56C1A1F7568014D2691D3E912A94C8AC2188C99813C1181A0720028E29341544A72FE014389AAE962E59C278386C9752C4141327B53D5D10A1CC88C4D23558237D88900D71DD44AC61C85042AEE9CC7C305C6D039C2C08B89B18D80D310A974A03481133224B7B2E438D2B4C87941821809E42584B933618D784DA88757E75173E07C840A2A85C512D53CEA385C3C8A889510E1C2D0CAC4988283570A6B800D9F4CA2B4A4884B8850A8DC7126BBCA66AF58DA013", + mem_init0 => "0AD2342444864701A2C90BF2433380CB2BF0BE92E04244423BFB5299CCBAE67C0C9C0C0E65E6269519BD33062B229857972B6CA54E648AA84AE4EAA12A1F461D5E30534B85073C44454BC6956DE878A2CAB5C949638AB16B2D62C58B1628A7C98D08236482D468905A8D1210630180C050D3B650118A183A694E8E491462099D1566483FD08421A65AAA5400063726291847195936618A5509DE2AA5C514222A022550965140A2A99416AAA81855313282D142EA80E562000017402AEAEEEAEAEEAEEAAEEAAAAAAAA805500AA017402AFFFFFFFFFFFC804804804804804900FEFA000000000000695D1A1A000005020000000318000300000041000A22000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 6, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 6, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X19_Y13_N36 +\myVirtualToplevel|MEM_DATA_READ[14]~139\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[14]~70_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6~portbdataout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((\myVirtualToplevel|IO_DATA_READ_SD\(14))))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]~14_combout\)))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[14]~70_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) # ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14~portbdataout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ +-- & (((\myVirtualToplevel|IO_DATA_READ_SD\(14))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]~14_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001001000110100010101100111000010011010101111001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(14), + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~70_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[14]~14_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\); + +-- Location: MLABCELL_X18_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector352~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ & \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\)) # +-- (\myVirtualToplevel|MEM_DATA_READ[22]~13_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ & \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000001100111111110000110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~0_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~111_Duplicate_170\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~0_combout\); + +-- Location: MLABCELL_X18_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector352~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\) # (\myVirtualToplevel|MEM_DATA_READ[30]~47_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector352~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\ & (\myVirtualToplevel|MEM_DATA_READ[14]~139_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & (((\myVirtualToplevel|MEM_DATA_READ[30]~47_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011111000100000001111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~139_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~4_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~47_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector352~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~1_combout\); + +-- Location: FF_X18_Y16_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~1_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~69_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(6)); + +-- Location: FF_X18_Y23_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[6]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(6) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(6) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[6]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\); + +-- Location: MLABCELL_X9_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~69_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~69_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~50_combout\); + +-- Location: MLABCELL_X4_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add19~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~70\); + +-- Location: MLABCELL_X4_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add19~69_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001110101010001100111010101000110011101010100011001110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~69_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\); + +-- Location: MLABCELL_X9_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~50_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(6) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~50_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100010001101011111011101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[6]~50_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1077~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~51_combout\); + +-- Location: FF_X9_Y28_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~51_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(6)); + +-- Location: MLABCELL_X9_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~69_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~69_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~44_combout\); + +-- Location: LABCELL_X12_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~44_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~44_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1077~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[6]~44_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~45_combout\); + +-- Location: FF_X12_Y28_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~45_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(6)); + +-- Location: LABCELL_X6_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001001110000010100100111000011011010111110001101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~69_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~69_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~46_combout\); + +-- Location: LABCELL_X6_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~46_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~46_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~46_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~46_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101110101111111100010101000000001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1077~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[6]~46_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~47_combout\); + +-- Location: FF_X6_Y31_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~47_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(6)); + +-- Location: LABCELL_X6_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~69_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~69_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~47_combout\); + +-- Location: LABCELL_X6_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~47_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(6) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~47_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000111111100101111011100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1077~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[6]~47_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~48_combout\); + +-- Location: FF_X6_Y31_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~48_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(6)); + +-- Location: LABCELL_X12_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(6) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(6)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(6)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(6)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001001100010000110100111101110000011111000111001101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~1_combout\); + +-- Location: MLABCELL_X9_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~69_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~69_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~47_combout\); + +-- Location: MLABCELL_X9_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~47_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~47_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000001011111001111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[6]~47_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1077~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~48_combout\); + +-- Location: FF_X9_Y28_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~48_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(6)); + +-- Location: LABCELL_X6_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~69_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~69_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~48_combout\); + +-- Location: LABCELL_X6_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~48_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~48_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1077~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[6]~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~49_combout\); + +-- Location: FF_X6_Y31_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~49_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(6)); + +-- Location: MLABCELL_X9_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~69_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~69_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~43_combout\); + +-- Location: MLABCELL_X9_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~43_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~43_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101101010111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[6]~43_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1077~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~44_combout\); + +-- Location: FF_X9_Y28_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~44_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(6)); + +-- Location: LABCELL_X6_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001001110000010100100111000011011010111110001101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~69_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~69_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~46_combout\); + +-- Location: LABCELL_X6_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~46_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~46_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010011110111001101111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1077~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[6]~46_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~47_combout\); + +-- Location: FF_X6_Y27_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~47_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(6)); + +-- Location: LABCELL_X7_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(6) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(6) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(6) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(6) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~0_combout\); + +-- Location: MLABCELL_X13_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\); + +-- Location: MLABCELL_X13_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector210~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~69_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~69_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~69_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~69_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100110100001101000011011100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~69_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~1_combout\); + +-- Location: LABCELL_X16_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector210~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector210~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(6)))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector210~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(6))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000101111111011111100100000011100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector210~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~0_combout\); + +-- Location: FF_X16_Y14_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y13_N48 +\myVirtualToplevel|TIMER0_CS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER0_CS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7), + combout => \myVirtualToplevel|TIMER0_CS~0_combout\); + +-- Location: LABCELL_X16_Y11_N9 +\myVirtualToplevel|TIMER0_CS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER0_CS~1_combout\ = ( \myVirtualToplevel|TIMER0_CS~0_combout\ & ( \myVirtualToplevel|IO_SELECT~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ALT_INV_TIMER0_CS~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + combout => \myVirtualToplevel|TIMER0_CS~1_combout\); + +-- Location: FF_X17_Y10_N19 +\myVirtualToplevel|MILLISEC_UP_COUNTER[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~113_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(26)); + +-- Location: LABCELL_X17_Y10_N54 +\myVirtualToplevel|IO_DATA_READ[26]~84\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[26]~84_combout\ = ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(26) & ( ((!\myVirtualToplevel|TIMER0_CS~1_combout\ & \myVirtualToplevel|UART1|Mux0~0_combout\)) # (\myVirtualToplevel|IO_DATA_READ[26]~78_combout\) ) ) # ( +-- !\myVirtualToplevel|MILLISEC_UP_COUNTER\(26) & ( (!\myVirtualToplevel|TIMER0_CS~1_combout\ & \myVirtualToplevel|UART1|Mux0~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000001111110011110000111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ[26]~78_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(26), + combout => \myVirtualToplevel|IO_DATA_READ[26]~84_combout\); + +-- Location: FF_X17_Y10_N55 +\myVirtualToplevel|IO_DATA_READ[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ[26]~84_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(26)); + +-- Location: LABCELL_X24_Y9_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector5~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector5~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(10))) +-- # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(10))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010001000000000001000100000110011101110110011001110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector3~1_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(10), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(2), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector5~0_combout\); + +-- Location: FF_X24_Y9_N53 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector5~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(10)); + +-- Location: LABCELL_X21_Y9_N42 +\myVirtualToplevel|IO_DATA_READ_SD[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[26]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(10) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(10), + combout => \myVirtualToplevel|IO_DATA_READ_SD[26]~feeder_combout\); + +-- Location: MLABCELL_X9_Y9_N42 +\myVirtualToplevel|SD_ADDR[0][26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(26), + combout => \myVirtualToplevel|SD_ADDR[0][26]~feeder_combout\); + +-- Location: FF_X9_Y9_N43 +\myVirtualToplevel|SD_ADDR[0][26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][26]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][26]~q\); + +-- Location: FF_X21_Y9_N44 +\myVirtualToplevel|IO_DATA_READ_SD[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[26]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][26]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(26)); + +-- Location: FF_X21_Y12_N2 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux87~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(26)); + +-- Location: LABCELL_X21_Y12_N0 +\myVirtualToplevel|MEM_DATA_READ[26]~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[26]~54_combout\ = ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(26) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (!\myVirtualToplevel|INTR0_CS~combout\)) # +-- (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((\myVirtualToplevel|IO_DATA_READ\(26)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(26) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & +-- (!\myVirtualToplevel|INTR0_CS~combout\)) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((\myVirtualToplevel|IO_DATA_READ\(26)))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(26) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) # (\myVirtualToplevel|IO_DATA_READ_SD\(26)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(26) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (\myVirtualToplevel|IO_DATA_READ_SD\(26) & +-- \myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111110101010001100111010101000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(26), + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(26), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(26), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[26]~54_combout\); + +-- Location: LABCELL_X17_Y9_N6 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[2]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[2]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001010111000000100101011110001010110111111000101011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(26), + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[2]~5_combout\); + +-- Location: M10K_X38_Y10_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E0002B81B33991E209FBC96E8A1298A9B702582E6DA894A52A5435616420884B11D54DA4DD3499F8A7C15173DBA9454801D57FC03D5555550C010C78DBCC898E30C0010801402101109A109C10205091365E876000000E9873946EA5358F63F55AEAB04391AE8C9DC17922615052F", + mem_init2 => "0100085824913D6AD4A530B87248A4B44BC706A40916E5B202401200F2404D00FC35C91607B253B4E9C8BC7D19128301F54322A2257308A2090109551F4501CC51EE5C3564834D50B24144A953B3236A6079FA91851719174A7E267FC90350956BA99F8000020835F32437F62695E674C6655DC3D998AD378369796379259A2658494E64B81F40425A802382A50956A5092BF426C2B081192A798874732B98E00A20C5F3C1841C2B934F3D887401E597773DD39A1EEFC1520CC46838D04050C30CE8822493D6AF4881F669F2002B718937D2E98B6432451CDA58A88EB40775842A8E9058E14D040530282BF352224D2B8FB0044CFB845F8A50000E53DF7E6025", + mem_init1 => "739DFE18714C445031E2910E420FD92079837C0109FF506804559360A8A88A521E5511F805A941747AEC0F360F2211E818E426C6CB8471D4481CC8008F17132180913171D17B20A3AAD10A0124C1A4C68433CC89F7F7DD9ECD84981DEE4D0BC246CB20FB0BFF7EAB4B0F9ED42721630800A056E964A6F06228086260CBD06B7D795180E1C17C58AC2A741083209F5C5AB0012A980E3042EE66328BB1E1A05229C0C25C333218BA0DA123285306F20C80D35092D1F0A1C2C944C39120C8C085A94090EBC4901386FD8E9FBAE5A4AD0063A8324DEB100B446DA5E03F55EF8CFD1051EF4E2B95327341C399B4108CF8DF51BE1BB937C00D883C53E74FA432B80D35", + mem_init0 => "13243DAB6F1A26610CCE900F8D03309283A90164A017A2C59592FDB1150EDC3DB7E8084AD1823EABE0AB232FCECBE3B1F6A72FF96AB10725371A991042B18059504486379BE5F99E3B907AE5258E07011489C20024015208C082070A1C1C62845162484824030906802120839E8F47A39304044E592CF348401A52AC006B1A190454C380414A51CB044445042BC93A6F0039A6F453E9C25862D3F595DF81DD93792A0C862E7F105181F500EA8E8A3E303EA8BF0165006000756B6A911111111111111111111111116D52DAB5B56B6AD7FFFFFFFFFFFA012492492492012010FEFA0004010201017AE260681020040600000026300800020000A0001008301800", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 2, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 2, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\); + +-- Location: M10K_X30_Y6_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 2, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 2, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X21_Y12_N51 +\myVirtualToplevel|MEM_DATA_READ[26]~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[26]~55_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10~portbdataout\ & ( (\myVirtualToplevel|LessThan0~1_combout\ & +-- ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2~portbdataout\) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0)))) ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10~portbdataout\ & ( (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0) & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2~portbdataout\ & \myVirtualToplevel|LessThan0~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110000000000001111110000000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[26]~55_combout\); + +-- Location: LABCELL_X20_Y12_N21 +\myVirtualToplevel|MEM_DATA_READ[26]~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[26]~55_combout\ ) # ( !\myVirtualToplevel|MEM_DATA_READ[26]~55_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & +-- (\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31_combout\))) # (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & (((\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[26]~54_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010111000000110101011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]~31_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~54_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~55_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\); + +-- Location: LABCELL_X17_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector356~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[10]~119_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[10]~119_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[18]~30_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~119_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[18]~30_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\ & ((!\myVirtualToplevel|MEM_DATA_READ[10]~119_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110010001000111111111010101011000000100000001111000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~119_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_155\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~0_combout\); + +-- Location: LABCELL_X17_Y16_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector356~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector356~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\) # (\myVirtualToplevel|MEM_DATA_READ[26]~56_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101011111111101010101111111100000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~4_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~56_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector356~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~1_combout\); + +-- Location: FF_X17_Y16_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~1_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~85_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(2)); + +-- Location: LABCELL_X16_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\); + +-- Location: MLABCELL_X9_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[2]_NEW2871\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[2]_OTERM2872\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[2]_OTERM2872\); + +-- Location: FF_X9_Y22_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[2]_OTERM2872\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(2)); + +-- Location: LABCELL_X12_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[2]_NEW2935\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[2]_OTERM2936\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101000100011010111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[2]_OTERM2936\); + +-- Location: FF_X12_Y21_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[2]_OTERM2936\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(2)); + +-- Location: LABCELL_X10_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[2]_NEW2743\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[2]_OTERM2744\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000001011111001111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[2]_OTERM2744\); + +-- Location: FF_X10_Y21_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[2]_OTERM2744\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(2)); + +-- Location: LABCELL_X7_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[2]_NEW2807\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[2]_OTERM2808\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[2]_OTERM2808\); + +-- Location: FF_X7_Y20_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[2]_OTERM2808\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(2)); + +-- Location: LABCELL_X6_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux85~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(2) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(2) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(2) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~1_combout\); + +-- Location: LABCELL_X10_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[2]_NEW3127\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[2]_OTERM3128\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[2]_OTERM3128\); + +-- Location: FF_X10_Y21_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[2]_OTERM3128\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(2)); + +-- Location: LABCELL_X12_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[2]_NEW3191\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[2]_OTERM3192\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[2]_OTERM3192\); + +-- Location: FF_X12_Y21_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[2]_OTERM3192\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(2)); + +-- Location: LABCELL_X10_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[2]_NEW2999\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[2]_OTERM3000\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000001011111001111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[2]_OTERM3000\); + +-- Location: FF_X10_Y21_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[2]_OTERM3000\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(2)); + +-- Location: LABCELL_X12_Y21_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[2]_NEW3063\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[2]_OTERM3064\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[2]_OTERM3064\); + +-- Location: FF_X12_Y21_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[2]_OTERM3064\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(2)); + +-- Location: LABCELL_X12_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux85~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(2))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(2))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101000000000000111100110101001101011111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~0_combout\); + +-- Location: LABCELL_X6_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux85~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux85~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\); + +-- Location: LABCELL_X10_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector16~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector16~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111111111000000001111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector16~0_combout\); + +-- Location: LABCELL_X10_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector274~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector274~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector16~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\)) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[18]~30_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector16~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\)) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[18]~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector16~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector274~0_combout\); + +-- Location: FF_X10_Y15_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_NEW_REG923\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector274~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM924\); + +-- Location: LABCELL_X10_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM922\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM924\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM922\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM924\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM922\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM924\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100111111001100001100000011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]_OTERM922\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]_OTERM924\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\); + +-- Location: FF_X14_Y9_N4 +\myVirtualToplevel|SD_ADDR[0][18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][18]~q\); + +-- Location: FF_X18_Y9_N31 +\myVirtualToplevel|IO_DATA_READ_SD[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[18]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][18]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(18)); + +-- Location: FF_X17_Y11_N55 +\myVirtualToplevel|MILLISEC_UP_COUNTER[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~25_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(18)); + +-- Location: FF_X13_Y11_N25 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~25_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(18)); + +-- Location: LABCELL_X16_Y9_N30 +\myVirtualToplevel|IO_DATA_READ~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~21_combout\ = ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # (\myVirtualToplevel|MILLISEC_UP_COUNTER\(18)))) ) ) # ( +-- !\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(18) & ( (\myVirtualToplevel|MILLISEC_UP_COUNTER\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100110001001100010000000100000001001100010011000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datae => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(18), + combout => \myVirtualToplevel|IO_DATA_READ~21_combout\); + +-- Location: MLABCELL_X13_Y9_N30 +\myVirtualToplevel|UART1|TX_BUSY~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_BUSY~0_combout\ = ( \myVirtualToplevel|UART1|TX_BUSY~q\ & ( \myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & ( (((!\myVirtualToplevel|UART1|TX_STATE~q\) # (!\myVirtualToplevel|UART1|TX_CLOCK~q\)) # +-- (\myVirtualToplevel|UART1|TX_ENABLE~q\)) # (\myVirtualToplevel|UART1|TX_BUFFER\(8)) ) ) ) # ( !\myVirtualToplevel|UART1|TX_BUSY~q\ & ( \myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & ( (!\myVirtualToplevel|UART1|TX_ENABLE~q\ & +-- !\myVirtualToplevel|UART1|TX_STATE~q\) ) ) ) # ( \myVirtualToplevel|UART1|TX_BUSY~q\ & ( !\myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & ( (((!\myVirtualToplevel|UART1|TX_STATE~q\) # (!\myVirtualToplevel|UART1|TX_CLOCK~q\)) # +-- (\myVirtualToplevel|UART1|TX_ENABLE~q\)) # (\myVirtualToplevel|UART1|TX_BUFFER\(8)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111011111000000110000001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(8), + datab => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\, + datad => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK~q\, + datae => \myVirtualToplevel|UART1|ALT_INV_TX_BUSY~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_DATA_LOADED~q\, + combout => \myVirtualToplevel|UART1|TX_BUSY~0_combout\); + +-- Location: FF_X13_Y9_N32 +\myVirtualToplevel|UART1|TX_BUSY\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_BUSY~0_combout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_BUSY~q\); + +-- Location: MLABCELL_X9_Y8_N54 +\myVirtualToplevel|UART0|TX_BUSY~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUSY~0_combout\ = ( \myVirtualToplevel|UART0|TX_BUSY~q\ & ( \myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ( ((!\myVirtualToplevel|UART0|TX_CLOCK~q\) # ((!\myVirtualToplevel|UART0|TX_STATE~q\) # +-- (\myVirtualToplevel|UART0|TX_BUFFER\(8)))) # (\myVirtualToplevel|UART0|TX_ENABLE~q\) ) ) ) # ( !\myVirtualToplevel|UART0|TX_BUSY~q\ & ( \myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ( (!\myVirtualToplevel|UART0|TX_ENABLE~q\ & +-- !\myVirtualToplevel|UART0|TX_STATE~q\) ) ) ) # ( \myVirtualToplevel|UART0|TX_BUSY~q\ & ( !\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ( ((!\myVirtualToplevel|UART0|TX_CLOCK~q\) # ((!\myVirtualToplevel|UART0|TX_STATE~q\) # +-- (\myVirtualToplevel|UART0|TX_BUFFER\(8)))) # (\myVirtualToplevel|UART0|TX_ENABLE~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111011111111110100000101000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(8), + datae => \myVirtualToplevel|UART0|ALT_INV_TX_BUSY~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\, + combout => \myVirtualToplevel|UART0|TX_BUSY~0_combout\); + +-- Location: FF_X9_Y8_N55 +\myVirtualToplevel|UART0|TX_BUSY\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUSY~0_combout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUSY~q\); + +-- Location: LABCELL_X16_Y9_N18 +\myVirtualToplevel|IO_DATA_READ~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~20_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|Add10~25_sumout\ & ( ((\myVirtualToplevel|UART1|TX_BUSY~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|Add10~25_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|UART0|TX_BUSY~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( \myVirtualToplevel|UART1_CS~combout\ & ( !\myVirtualToplevel|UART1|Add10~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # +-- (\myVirtualToplevel|UART1|TX_BUSY~q\))) ) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( !\myVirtualToplevel|UART1|Add10~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART0|TX_BUSY~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100110011000100110001001100001111001111110001111100011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_BUSY~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_BUSY~q\, + datae => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add10~25_sumout\, + combout => \myVirtualToplevel|IO_DATA_READ~20_combout\); + +-- Location: LABCELL_X16_Y9_N45 +\myVirtualToplevel|IO_DATA_READ~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & ( \myVirtualToplevel|IO_DATA_READ~20_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|IO_DATA_READ~20_combout\ & ( (!\myVirtualToplevel|TIMER0_CS~2_combout\) # ((\myVirtualToplevel|Equal3~0_combout\ & \myVirtualToplevel|IO_DATA_READ~21_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|IO_DATA_READ~20_combout\ & ( (\myVirtualToplevel|Equal3~0_combout\ & (\myVirtualToplevel|IO_DATA_READ~21_combout\ & \myVirtualToplevel|TIMER0_CS~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001000000000000000011110001111100011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ~21_combout\, + datac => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~20_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~22_combout\); + +-- Location: FF_X16_Y9_N46 +\myVirtualToplevel|IO_DATA_READ[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~22_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(18)); + +-- Location: FF_X21_Y12_N56 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux87~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(18)); + +-- Location: LABCELL_X21_Y12_N54 +\myVirtualToplevel|MEM_DATA_READ[18]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[18]~28_combout\ = ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(18) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (!\myVirtualToplevel|INTR0_CS~combout\)) # +-- (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((\myVirtualToplevel|IO_DATA_READ\(18)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(18) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & +-- (!\myVirtualToplevel|INTR0_CS~combout\)) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((\myVirtualToplevel|IO_DATA_READ\(18)))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(18) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) # (\myVirtualToplevel|IO_DATA_READ_SD\(18)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(18) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (\myVirtualToplevel|IO_DATA_READ_SD\(18) & +-- \myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111111110101010111001100000011111100110000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(18), + datab => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(18), + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(18), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[18]~28_combout\); + +-- Location: MLABCELL_X18_Y9_N54 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[2]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[2]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ & ( (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[2]~6_combout\); + +-- Location: M10K_X22_Y8_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 2, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 2, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\); + +-- Location: M10K_X38_Y12_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022000022000002020022000E10031EC951A95826355B22512ECEC6B0A50261412B70842118911200101C00046CA4A9EC7678F371094C6303FE23A5599C4520813555555480B5F19FBAFD1C139C610248C4350808128A424A040850A030A7FE000000D65F65D8A52E3250090E619878501D6D186A2456A551819A", + mem_init2 => "90006092090046CC9DAAF932C23D9424932C84C84784DA8801E020011B049227ACD3472474EF250972404191168894524453442A449060E715FE5E2700889FE0589AC25C83CD50B24144A95969D931D29B280646B1D27FA315352447A1B6810D5F954F2982008081BC31C2210EDEDCC33FE9419A688420FE512C84B618E62B1A9A5E0701D4313CA20D8AA4D517D131D7D0449C2FB610389E68F36D13CEE1D1B0CF966C5DC1430277641212F04F2D0AA1ACE96EF181B9F284953A155C831E9D4452D766944C7D1A219C8119F0B709A112546D5A969F93A14E2D280833C6700A8A15E8BCA12F81F63A10488BB2010D710264511E55EC0391E18B42C6CD988C1E90", + mem_init1 => "62DF96211B151B0FC2092A83A69BBAF6C45213EE524E7883483809BC5E03511C1E2A5F3089A632DD6A8FBA790A2AB60CC3636C5B00889817F4578FD7B86ED12165D8BFDCB1401C044717447DD23A458049C403CA993BA0E07CE0040F87DEEB5A000BC54A00385886956F28C31E9806FAF199D596C01ACFE807C44E101E81A6DA4000DA0A4431C823F083871413187A5ED33EB4092301219C341E52A466F39F6A5C0E3F4BEC253E40650C5987C0B08AF34A40481B3E0218A5806CB1676019C63418130122EF2163DBC901300010468054C155AEFF5A348318CE81551F1A3C538C92061CBBD68B7E324C6E1B8371AFB88A03C54C2A2110AC181A9743249A7E463A", + mem_init0 => "40000DD0EE05A8D4A43801CB06CC625491C03B255C108A65ED67D108260981075582A2150E43E07EC97E046445C1638F4A2BF1D796E0D80015616754542003010D6D0F3F2345B788A12470FEA607D1409D4E60000015A01402E54B952E5F78880021001090680212090042494A2512896F8D728D2018CED69B3411D010078EB001ACE3D058A940FCDFFF060242C53001848B2765F530261908AC856BAEA06EF8180FA438BF35E97E00D2E04026CFC7401A73F545E2D10900BB54B6AAAEAAAAEAEEAAEAAAEEEEAEEAD6DD2DAA5B56B6A8FFFFFFFFFFFA492496DB6DB6DB6DB6FEFC000100000001E02C2828211500020206166A1E080002000602060687150C02", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 2, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 2, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X21_Y12_N45 +\myVirtualToplevel|MEM_DATA_READ[18]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[18]~29_combout\ = ( \myVirtualToplevel|LessThan0~1_combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10~portbdataout\) ) ) ) # ( \myVirtualToplevel|LessThan0~1_combout\ & ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2~portbdataout\ & ( (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10~portbdataout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001010000010100000000000000001010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\, + datae => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[18]~29_combout\); + +-- Location: LABCELL_X20_Y12_N39 +\myVirtualToplevel|MEM_DATA_READ[18]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[18]~28_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[18]~29_combout\ ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[18]~28_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[18]~29_combout\ ) ) # ( \myVirtualToplevel|MEM_DATA_READ[18]~28_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[18]~29_combout\ & ( ((\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[18]~28_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[18]~29_combout\ & ( +-- (\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111010101010101111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[18]~10_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~28_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~29_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\); + +-- Location: LABCELL_X14_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector198~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~25_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~25_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~25_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010010100100101001001110111011101110101011101010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~1_combout\); + +-- Location: LABCELL_X14_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector198~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector198~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(18))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector198~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(18) & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010000000101010001011110101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector198~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~0_combout\); + +-- Location: LABCELL_X16_Y13_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[18]_NEW3339\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[18]_OTERM3340\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(18))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # ((\myVirtualToplevel|MEM_DATA_READ[18]~30_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector198~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(18))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- (\myVirtualToplevel|MEM_DATA_READ[18]~30_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~1_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector198~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[18]_OTERM3340\); + +-- Location: FF_X16_Y13_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[18]_OTERM3340\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(18)); + +-- Location: LABCELL_X17_Y13_N21 +\myVirtualToplevel|IO_SELECT~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_SELECT~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[19]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[19]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(17), + combout => \myVirtualToplevel|IO_SELECT~1_combout\); + +-- Location: LABCELL_X17_Y13_N57 +\myVirtualToplevel|INTR0_CS_RESYN8755\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTR0_CS_RESYN8755_BDD8756\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7))) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010000000000000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9), + combout => \myVirtualToplevel|INTR0_CS_RESYN8755_BDD8756\); + +-- Location: LABCELL_X17_Y13_N45 +\myVirtualToplevel|INTR0_CS\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTR0_CS~combout\ = ( \myVirtualToplevel|INTR0_CS_RESYN8755_BDD8756\ & ( \myVirtualToplevel|INTR0_CS~0_combout\ & ( (\myVirtualToplevel|IO_SELECT~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & +-- (\myVirtualToplevel|IO_SELECT~0_combout\ & \myVirtualToplevel|IO_SELECT~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\, + datae => \myVirtualToplevel|ALT_INV_INTR0_CS_RESYN8755_BDD8756\, + dataf => \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\, + combout => \myVirtualToplevel|INTR0_CS~combout\); + +-- Location: FF_X17_Y11_N58 +\myVirtualToplevel|MILLISEC_UP_COUNTER[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~29_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(19)); + +-- Location: LABCELL_X14_Y11_N6 +\myVirtualToplevel|IO_DATA_READ~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~24_combout\ = ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(19) & ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( (\myVirtualToplevel|INTR0_CS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # (\myVirtualToplevel|MILLISEC_UP_COUNTER\(19))))) ) ) ) # ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(19) & ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( (\myVirtualToplevel|MILLISEC_UP_COUNTER\(19) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|INTR0_CS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000001000000000000110100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(19), + dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~24_combout\); + +-- Location: MLABCELL_X13_Y9_N15 +\myVirtualToplevel|IO_DATA_READ~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~23_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_DATA_LOADED~q\ ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_DATA_LOADED~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART1|ALT_INV_TX_DATA_LOADED~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\, + dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + combout => \myVirtualToplevel|IO_DATA_READ~23_combout\); + +-- Location: LABCELL_X16_Y12_N39 +\myVirtualToplevel|IO_DATA_READ~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~25_combout\ = ( \myVirtualToplevel|UART1|Add10~29_sumout\ & ( \myVirtualToplevel|IO_DATA_READ~23_combout\ & ( ((!\myVirtualToplevel|TIMER0_CS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))))) # (\myVirtualToplevel|IO_DATA_READ~24_combout\) ) ) ) # ( !\myVirtualToplevel|UART1|Add10~29_sumout\ & ( \myVirtualToplevel|IO_DATA_READ~23_combout\ & ( ((!\myVirtualToplevel|TIMER0_CS~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) # (\myVirtualToplevel|IO_DATA_READ~24_combout\) ) ) ) # ( \myVirtualToplevel|UART1|Add10~29_sumout\ & ( !\myVirtualToplevel|IO_DATA_READ~23_combout\ & ( +-- ((!\myVirtualToplevel|TIMER0_CS~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) # (\myVirtualToplevel|IO_DATA_READ~24_combout\) ) ) ) # ( !\myVirtualToplevel|UART1|Add10~29_sumout\ & ( +-- !\myVirtualToplevel|IO_DATA_READ~23_combout\ & ( \myVirtualToplevel|IO_DATA_READ~24_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001110110011001100110011101100110011101110110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ~24_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|UART1|ALT_INV_Add10~29_sumout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~23_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~25_combout\); + +-- Location: FF_X16_Y12_N40 +\myVirtualToplevel|IO_DATA_READ[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~25_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(19)); + +-- Location: LABCELL_X21_Y13_N39 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SOCCFG[19]~feeder_combout\ = ( \myVirtualToplevel|Mux86~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_Mux86~0_combout\, + combout => \myVirtualToplevel|IO_DATA_READ_SOCCFG[19]~feeder_combout\); + +-- Location: FF_X21_Y13_N41 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SOCCFG[19]~feeder_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(19)); + +-- Location: LABCELL_X24_Y9_N15 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector12~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector12~0_combout\ = (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(3)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(3), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector12~0_combout\); + +-- Location: FF_X24_Y9_N16 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector12~0_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3), + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(3)); + +-- Location: LABCELL_X21_Y9_N21 +\myVirtualToplevel|IO_DATA_READ_SD[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[19]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(3) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(3), + combout => \myVirtualToplevel|IO_DATA_READ_SD[19]~feeder_combout\); + +-- Location: LABCELL_X21_Y9_N57 +\myVirtualToplevel|SD_ADDR[0][19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\, + combout => \myVirtualToplevel|SD_ADDR[0][19]~feeder_combout\); + +-- Location: FF_X21_Y9_N59 +\myVirtualToplevel|SD_ADDR[0][19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][19]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][19]~q\); + +-- Location: FF_X21_Y9_N22 +\myVirtualToplevel|IO_DATA_READ_SD[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[19]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][19]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(19)); + +-- Location: LABCELL_X20_Y13_N36 +\myVirtualToplevel|MEM_DATA_READ[19]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[19]~31_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( \myVirtualToplevel|IO_DATA_READ\(19) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & +-- ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( !\myVirtualToplevel|INTR0_CS~combout\ ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( \myVirtualToplevel|IO_DATA_READ_SD\(19) ) ) ) # +-- ( !\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(19) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111110101010101010100011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(19), + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(19), + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(19), + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[19]~31_combout\); + +-- Location: MLABCELL_X18_Y11_N36 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[3]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[3]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ & ( (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[3]~7_combout\); + +-- Location: M10K_X22_Y5_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 3, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 3, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\); + +-- Location: M10K_X38_Y11_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002200000000020200000010027CC04AB8003683398E1B348CC4EB0166A2129B44210852D04049390C000024402927F52A07DB881F072FBEB1910860017401799999BD2031D1E6336DAC058E203601886020181A8A4A02850A542877B1A4000000D112E0C01420DC5C880E63B8BFD4967D384264131D5AAFF6", + mem_init2 => "F7BC2D943BDED4579224EF2058397A64F2055CB4275C8089B1D0EB7B41787583D46FE766686CBD0F723DD7AF142B8286B7CBF2F9D339ED8615CF5EC1030088213034892C238156A21160AB510943A091FE4E67EC634A1E9539A510B16AB8B2C16687234090038585825579190B4A502AD58C8876068DE44B5366E6DDFB563B56B8F40D0035C6481DE800C0271A23D91A22904B530885D420CA02287B818CC181E177A399AC0E6B761C356E103119C65219634EB1839050B50900949E4B3F888820C480DE402B72D51C924005821B90275CAB847000886BC78595D9717C40AE11C07443AE0E07484BD1A15B82B1EE2BBD04004051EBB231D1985EA1F8D705411E", + mem_init1 => "CD4601D7C4D0342A4C62E66C001B91282B70E4D03B46C916EA2D0D798C55599C7CE8DC246C07842ACF7A7848E85ECD9F95F2B28CB613183CA58D017464F6BE0AC80ADBB82C8E13E5D10E15F8A44403086A60BD162A6180B8664E32A20137865DAC25900280D221E720DB41B2A40D12587A0B45088021151FC1C458040200630938440009C157E153821B4998942686F00EF2422082E156DA9AD3C03044A70BC184E14CC7B74205B2588A21FB02E00AE34100CBB6A2029817F102490F3EF17E0785E1C14406C300017E01C1C1EF3833823A1CDA003230B367721DB1B0056234633A5EF1863100C00CEB954F8121741092318D960BC3053E1A0143010904352488", + mem_init0 => "300C5858864DCDE7064218D326C6FB8432A118019E210028E2900463554D5C2A964A85A85AA27BF9C10104C3918C4BA42280344283A4072FB448907072251048DA164078A4C1A50AF862B06B2627100677520BB68A3DC5B6B6DD3A76EDD17D23080806120088C2401118C83F8C6E331BAF90600D2091D404824211900024E409040111903C94255CB55589B4C09EF0C8809077A80450A41D2819B1523F89BBAD7DB5ACDBBF7CAD2AE9D3B4A2AE455DDD3A517855CD50000077562EEEEAAAAEAEEEAEAEAAEAAEAEAEC5DD0BAB17742EA8FFFFFFFFFFF924924DB6DB6DB6DB6DFEFC00000000000103333F3F131101000109011402040101000220021953190F01", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 3, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 3, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X21_Y13_N3 +\myVirtualToplevel|MEM_DATA_READ[19]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[19]~32_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3~portbdataout\ & ( +-- \myVirtualToplevel|LessThan0~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|LessThan0~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11~portbdataout\ & ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3~portbdataout\ & ( (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|LessThan0~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001010000010100001010000010100000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datac => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[19]~32_combout\); + +-- Location: FF_X20_Y13_N26 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]_NEW_REG62\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]_OTERM63\); + +-- Location: LABCELL_X21_Y13_N45 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]_OTERM63\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\) # +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM37\)) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]_OTERM63\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM37\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010111111010111111111111101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]_OTERM37\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[19]_OTERM63\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11_combout\); + +-- Location: LABCELL_X20_Y13_N33 +\myVirtualToplevel|MEM_DATA_READ[19]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[19]~32_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11_combout\ ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[19]~32_combout\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11_combout\ & ( ((\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & \myVirtualToplevel|MEM_DATA_READ[19]~31_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) ) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[19]~32_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11_combout\ ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[19]~32_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11_combout\ & ( +-- (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & \myVirtualToplevel|MEM_DATA_READ[19]~31_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111111111111100110011001111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~31_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~32_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[19]~11_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\); + +-- Location: FF_X17_Y13_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[19]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[19]~DUPLICATE_q\); + +-- Location: FF_X16_Y13_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(20)); + +-- Location: LABCELL_X16_Y13_N57 +\myVirtualToplevel|BRAM_WREN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|BRAM_WREN~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[19]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(20) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(21)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000100000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[19]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(17), + combout => \myVirtualToplevel|BRAM_WREN~0_combout\); + +-- Location: LABCELL_X16_Y13_N42 +\myVirtualToplevel|MEM_DATA_READ[2]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~DUPLICATE_q\ & \myVirtualToplevel|BRAM_WREN~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101001011010101010100101101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_BRAM_WREN~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(22), + combout => \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\); + +-- Location: LABCELL_X24_Y7_N9 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector2~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector2~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(13)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(5), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector3~1_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(13), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector2~0_combout\); + +-- Location: FF_X24_Y7_N10 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector2~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(13)); + +-- Location: LABCELL_X21_Y9_N18 +\myVirtualToplevel|IO_DATA_READ_SD[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[29]~feeder_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(13), + combout => \myVirtualToplevel|IO_DATA_READ_SD[29]~feeder_combout\); + +-- Location: FF_X20_Y7_N35 +\myVirtualToplevel|SD_ADDR[0][29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(29), + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][29]~q\); + +-- Location: FF_X21_Y9_N20 +\myVirtualToplevel|IO_DATA_READ_SD[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[29]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][29]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(29)); + +-- Location: LABCELL_X17_Y10_N36 +\myVirtualToplevel|IO_DATA_READ~80\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~80_combout\ = ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(29) & ( \myVirtualToplevel|IO_DATA_READ[26]~78_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[26]~78_combout\, + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(29), + combout => \myVirtualToplevel|IO_DATA_READ~80_combout\); + +-- Location: FF_X17_Y10_N37 +\myVirtualToplevel|IO_DATA_READ[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~80_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(29)); + +-- Location: FF_X21_Y13_N23 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux86~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(29)); + +-- Location: LABCELL_X21_Y13_N21 +\myVirtualToplevel|MEM_DATA_READ[29]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[29]~42_combout\ = ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(29) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (!\myVirtualToplevel|INTR0_CS~combout\)) # +-- (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((\myVirtualToplevel|IO_DATA_READ\(29)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(29) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & +-- (!\myVirtualToplevel|INTR0_CS~combout\)) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((\myVirtualToplevel|IO_DATA_READ\(29)))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(29) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) # (\myVirtualToplevel|IO_DATA_READ_SD\(29)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(29) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (\myVirtualToplevel|IO_DATA_READ_SD\(29) & +-- \myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001110111011101110111000000111100111100000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(29), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\, + datac => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(29), + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(29), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[29]~42_combout\); + +-- Location: LABCELL_X20_Y11_N51 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[5]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[5]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(29), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[5]~1_combout\); + +-- Location: M10K_X22_Y3_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 5, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 5, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\); + +-- Location: M10K_X22_Y4_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ECDF7BDF9F3EFDEF3CF3B36BCCDFE66FFFD7F3DEF7BDCE73963F7A1EB6BFB97CF3CEFE73FEF3EF9E7BBDDCE765FBFFFFFC037FE01FC0014A59EA15FB7F4FFD7E67B5F97E7126A7D7E7E7EFDEBE7CFFFE7E000000E5C4800808405A932814A2A806597AE89B74A4160693210E", + mem_init2 => "01E18E9982E007D41DE52D379F4BE5A5437D44EF4950DF12CA460B801CC305D8EBE1C986842B55D451083A7993F44671EF21AAD76FDFDAF2290921715BF1140B815EABC14D764354A6BBA1AA58F0240A619088A08820D39CCA41EB8C434E57F51069FB12490C1C0BA396648A00866E648C87360BE3869E11852869591314B2084348D5352374C96E57BA18A02C19C12C19AB30BD3298C9CB299502464602E8EF250854A5423290C2529A1086946A789AE52552060083845B59940123B418D3A24CC9AC0204040162A67856D0C94A7648061089602DB35124A8C04708218820246091841CE9E107040217C783DA331022D5288C406A209D0C7002498139604C82", + mem_init1 => "400D080945F2949421C508E49D01B529EA2B5E0C80221272410640E429440812910A30000C2019401064A4162B0A38A240702AB60B7C726548F7CEC1C50E0C04423036065B1A85082C00C8122F291464100C3A60C23197914616D6A02C022102848883B432C816A351431084134246550DE5D0A916E642D231204D5AA20C92CAEA487025D848171B2ECC23F3001A29D7E04529ED12A6E3E9555A6D424B26420024610D262898C08E07A41003A4CD9A94482B00924054A31B461D148C4806A4F19105254D888C9E11081DD4578088482B00B220820546004A25081307320C189057EE1E39D68D4941D400E65808248818CE11C1C269C803DBAC663AD30922C842", + mem_init0 => "84852984B69D0578D300080F4E92BC746600829A48C011048EAB87147CBD4CC0EFD065924A866BC8C27CFE412204B7E96BD8C32CA82B69505D93A1B988C8BBFB8304F7E5009FA8E12C0A3440486609308005C20030C1780100010200081010C0060051AC040035808006B00068060000CA348B280602C14D14D13502EB8020DA68B2050044210B10DFFE47FF4B21775233240468E04409BCC535B39000140450089A12402203400014004A08018002028000208122148600220040400000000000000000000000000888111022204440FFFFFFFFFFF8082082082082082080FEF900000001000021190000050303010103032103010102000303030B31130000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 5, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 5, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X21_Y13_N12 +\myVirtualToplevel|MEM_DATA_READ[29]~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[29]~43_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5~portbdataout\ & ( +-- \myVirtualToplevel|LessThan0~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|LessThan0~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13~portbdataout\ & ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5~portbdataout\ & ( (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|LessThan0~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000100010001000100100010001000100011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datab => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[29]~43_combout\); + +-- Location: LABCELL_X20_Y13_N48 +\myVirtualToplevel|MEM_DATA_READ[29]~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[29]~43_combout\ ) # ( !\myVirtualToplevel|MEM_DATA_READ[29]~43_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27_combout\ & +-- (((\myVirtualToplevel|MEM_DATA_READ[29]~42_combout\ & \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\)))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27_combout\ & (((\myVirtualToplevel|MEM_DATA_READ[29]~42_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100011111000100010001111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]~27_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~42_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~43_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\); + +-- Location: LABCELL_X17_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector353~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\ & ( (\myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[13]~143_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000001011111010111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~127_Duplicate_167\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~143_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~0_combout\); + +-- Location: MLABCELL_X18_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector353~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector353~0_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector353~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~5_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~44_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector353~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~1_combout\); + +-- Location: FF_X18_Y16_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~1_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~53_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(5)); + +-- Location: MLABCELL_X18_Y16_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(5) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111111111111000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\); + +-- Location: LABCELL_X10_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~53_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~45_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~45_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~53_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~46_combout\); + +-- Location: LABCELL_X10_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~46_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(5) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\))) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~46_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(5)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111111111000100011111111100000000111011100000000011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~46_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~47_combout\); + +-- Location: FF_X10_Y25_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~47_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\); + +-- Location: LABCELL_X6_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(6) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(6) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(6), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~70\); + +-- Location: MLABCELL_X4_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~57_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~69_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~69_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~57_combout\); + +-- Location: LABCELL_X6_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~58_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~69_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~57_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~69_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~69_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~57_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~58_combout\); + +-- Location: LABCELL_X6_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~59_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~58_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(6) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\))) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~58_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(6)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111111111000100011111111100000000111011100000000011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~58_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~59_combout\); + +-- Location: FF_X6_Y26_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~59_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\); + +-- Location: MLABCELL_X4_Y26_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add19~73_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add19~73_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111001111110011111100001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~73_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\); + +-- Location: LABCELL_X10_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~73_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~73_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~49_combout\); + +-- Location: LABCELL_X10_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~49_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~49_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(7) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1076~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[7]~49_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~50_combout\); + +-- Location: FF_X10_Y31_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~50_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(7)); + +-- Location: LABCELL_X10_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~73_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~73_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~48_combout\); + +-- Location: LABCELL_X10_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~48_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~48_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101101110111010111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1076~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[7]~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~49_combout\); + +-- Location: FF_X10_Y31_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~49_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(7)); + +-- Location: LABCELL_X10_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010000000000110011001100110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~73_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~73_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~45_combout\); + +-- Location: LABCELL_X10_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~45_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~45_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000011110111011100111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1076~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[7]~45_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~46_combout\); + +-- Location: FF_X10_Y27_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~46_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(7)); + +-- Location: LABCELL_X5_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~73_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~73_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~50_combout\); + +-- Location: LABCELL_X5_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~50_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~50_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1076~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[7]~50_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~51_combout\); + +-- Location: FF_X5_Y31_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~51_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(7)); + +-- Location: LABCELL_X10_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(7) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(7))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(7))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010010111110010001000001010011101110101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~0_combout\); + +-- Location: MLABCELL_X9_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111000001010101010101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~73_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~73_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~48_combout\); + +-- Location: LABCELL_X7_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~48_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~48_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111111111110100011100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1076~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[7]~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~49_combout\); + +-- Location: FF_X7_Y31_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~49_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(7)); + +-- Location: LABCELL_X10_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~73_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~73_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~46_combout\); + +-- Location: LABCELL_X10_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~46_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~46_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000001011011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1076~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[7]~46_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~47_combout\); + +-- Location: FF_X10_Y31_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~47_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(7)); + +-- Location: LABCELL_X10_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~73_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~73_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~49_combout\); + +-- Location: LABCELL_X10_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~49_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(7) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~49_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101101010111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[7]~49_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1076~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~50_combout\); + +-- Location: FF_X10_Y31_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~50_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(7)); + +-- Location: LABCELL_X12_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010100000101000000000000111111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~73_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~73_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~52_combout\); + +-- Location: LABCELL_X7_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~52_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(7) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~52_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000111111101001111011100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1076~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[7]~52_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~53_combout\); + +-- Location: FF_X7_Y30_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~53_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(7)); + +-- Location: LABCELL_X10_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(7))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(7)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(7))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(7)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000100011101110111001111110011110001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~1_combout\); + +-- Location: LABCELL_X10_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\); + +-- Location: LABCELL_X14_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector209~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add6~73_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add6~73_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000001111000000100000111111010010110111111101001011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~73_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~1_combout\); + +-- Location: LABCELL_X16_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector209~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector209~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector209~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100010000010100010001011111111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector209~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~0_combout\); + +-- Location: FF_X16_Y15_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7)); + +-- Location: LABCELL_X14_Y11_N39 +\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|INTR0_CS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\, + combout => \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\); + +-- Location: MLABCELL_X23_Y14_N27 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0_combout\ ) # ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0_combout\ & ( (!\myVirtualToplevel|BRAM_WREN~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16) & ((!\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\) # (!\myVirtualToplevel|LessThan3~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111110111100001111111011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\, + datab => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\, + datac => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM0_WREN~0_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\); + +-- Location: M10K_X11_Y18_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 7, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 7, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\); + +-- Location: FF_X17_Y14_N52 +\myVirtualToplevel|INT_ENABLE[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(7)); + +-- Location: FF_X20_Y14_N38 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INT_ENABLE\(7), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(7)); + +-- Location: FF_X10_Y5_N8 +\myVirtualToplevel|UART0|RX_FIFO~25\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER\(8), + sload => VCC, + ena => \myVirtualToplevel|UART0|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO~25_q\); + +-- Location: FF_X10_Y5_N41 +\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|RX_BUFFER\(8), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(24)); + +-- Location: LABCELL_X10_Y5_N6 +\myVirtualToplevel|UART0|RX_DATA~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA~10_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(8) & ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & +-- (((\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(24)) # (\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\)))) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (((!\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\)) # +-- (\myVirtualToplevel|UART0|RX_FIFO~25_q\))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(8) & ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & +-- (((\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(24)) # (\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\)))) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (\myVirtualToplevel|UART0|RX_FIFO~25_q\ & (\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\))) ) +-- ) ) # ( \myVirtualToplevel|UART0|RX_BUFFER\(8) & ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (((!\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & +-- \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(24))))) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (((!\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\)) # (\myVirtualToplevel|UART0|RX_FIFO~25_q\))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(8) +-- & ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (((!\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(24))))) # +-- (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (\myVirtualToplevel|UART0|RX_FIFO~25_q\ & (\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110100001010100011111000100001011101010110101101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~25_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(24), + datae => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(8), + dataf => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|UART0|RX_DATA~10_combout\); + +-- Location: LABCELL_X10_Y6_N57 +\myVirtualToplevel|UART0|RX_DATA[7]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|RX_DATA[7]~11_combout\ = ( \myVirtualToplevel|UART0|RX_DATA~10_combout\ & ( ((\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\ & \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(7)) ) ) # ( +-- !\myVirtualToplevel|UART0|RX_DATA~10_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA\(7) & ((!\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\) # (!\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111101000000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(7), + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA~10_combout\, + combout => \myVirtualToplevel|UART0|RX_DATA[7]~11_combout\); + +-- Location: FF_X10_Y6_N58 +\myVirtualToplevel|UART0|RX_DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|RX_DATA[7]~11_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|RX_DATA\(7)); + +-- Location: LABCELL_X10_Y6_N12 +\myVirtualToplevel|IO_DATA_READ~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~57_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART0|RX_DATA\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (!\myVirtualToplevel|UART0|RX_RESET~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100111001001110010011100100111000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|UART0|ALT_INV_RX_RESET~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|IO_DATA_READ~57_combout\); + +-- Location: FF_X13_Y6_N32 +\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER\(8), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(24)); + +-- Location: FF_X13_Y6_N26 +\myVirtualToplevel|UART1|RX_FIFO~25\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART1|RX_BUFFER\(8), + sload => VCC, + ena => \myVirtualToplevel|UART1|RX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_FIFO~25_q\); + +-- Location: MLABCELL_X13_Y6_N24 +\myVirtualToplevel|UART1|RX_DATA~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA~10_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(8) & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) # (\myVirtualToplevel|UART1|RX_FIFO~25_q\) ) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_BUFFER\(8) & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & \myVirtualToplevel|UART1|RX_FIFO~25_q\) ) ) ) # ( \myVirtualToplevel|UART1|RX_BUFFER\(8) & ( +-- !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(24))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & +-- ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a7\))) ) ) ) # ( !\myVirtualToplevel|UART1|RX_BUFFER\(8) & ( !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & +-- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(24))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a7\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(24), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~25_q\, + datad => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datae => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(8), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA~10_combout\); + +-- Location: MLABCELL_X13_Y6_N39 +\myVirtualToplevel|UART1|RX_DATA[7]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|RX_DATA[7]~11_combout\ = ( \myVirtualToplevel|UART1|RX_DATA~10_combout\ & ( ((\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\)) # (\myVirtualToplevel|UART1|RX_DATA\(7)) ) ) # ( +-- !\myVirtualToplevel|UART1|RX_DATA~10_combout\ & ( (\myVirtualToplevel|UART1|RX_DATA\(7) & ((!\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\) # (!\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(7), + dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA~10_combout\, + combout => \myVirtualToplevel|UART1|RX_DATA[7]~11_combout\); + +-- Location: FF_X13_Y6_N40 +\myVirtualToplevel|UART1|RX_DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|RX_DATA[7]~11_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|RX_DATA\(7)); + +-- Location: LABCELL_X14_Y10_N42 +\myVirtualToplevel|IO_DATA_READ~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~56_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|UART1|RX_DATA\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- ((!\myVirtualToplevel|UART1|RX_RESET~q\))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010101000001000001010100000100000101010000010000010101000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(7), + datad => \myVirtualToplevel|UART1|ALT_INV_RX_RESET~q\, + combout => \myVirtualToplevel|IO_DATA_READ~56_combout\); + +-- Location: LABCELL_X12_Y10_N36 +\myVirtualToplevel|IO_DATA_READ~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~58_combout\ = ( \myVirtualToplevel|UART1|Equal7~0_combout\ & ( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datae => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(7), + combout => \myVirtualToplevel|IO_DATA_READ~58_combout\); + +-- Location: FF_X17_Y11_N22 +\myVirtualToplevel|MILLISEC_UP_COUNTER[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~73_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER[7]~DUPLICATE_q\); + +-- Location: FF_X14_Y12_N22 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~49_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(7)); + +-- Location: LABCELL_X16_Y12_N12 +\myVirtualToplevel|IO_DATA_READ~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~59_combout\ = ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_UP_COUNTER[7]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SECOND_DOWN_COUNTER\(7)))) ) ) ) # ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (\myVirtualToplevel|MILLISEC_UP_COUNTER[7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SECOND_DOWN_COUNTER\(7)))) ) ) ) # ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(7)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(7), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(7), + datae => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|IO_DATA_READ~59_combout\); + +-- Location: LABCELL_X16_Y12_N21 +\myVirtualToplevel|IO_DATA_READ~60\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~60_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (((\myVirtualToplevel|IO_DATA_READ~59_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|RTC_MILLISEC_COUNTER\(7) & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|IO_DATA_READ~59_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +-- ((\myVirtualToplevel|IO_DATA_READ~59_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (\myVirtualToplevel|RTC_MILLISEC_COUNTER\(7))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|IO_DATA_READ~59_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000000000000010100010001000001010000000000000101000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(7), + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ~59_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|IO_DATA_READ~60_combout\); + +-- Location: LABCELL_X14_Y10_N51 +\myVirtualToplevel|IO_DATA_READ~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~61_combout\ = ( \myVirtualToplevel|IO_DATA_READ~60_combout\ & ( \myVirtualToplevel|IO_DATA_READ[5]~49_combout\ & ( (\myVirtualToplevel|RTC_YEAR_COUNTER\(7) & \myVirtualToplevel|TIMER0_CS~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|IO_DATA_READ~60_combout\ & ( \myVirtualToplevel|IO_DATA_READ[5]~49_combout\ & ( (\myVirtualToplevel|RTC_YEAR_COUNTER\(7) & \myVirtualToplevel|TIMER0_CS~1_combout\) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ~60_combout\ & ( +-- !\myVirtualToplevel|IO_DATA_READ[5]~49_combout\ & ( \myVirtualToplevel|TIMER0_CS~1_combout\ ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~60_combout\ & ( !\myVirtualToplevel|IO_DATA_READ[5]~49_combout\ & ( (\myVirtualToplevel|TIMER0_CS~1_combout\ & +-- \myVirtualToplevel|IO_DATA_READ~58_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000011110000111100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(7), + datac => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ~58_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ~60_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ[5]~49_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~61_combout\); + +-- Location: LABCELL_X14_Y10_N30 +\myVirtualToplevel|IO_DATA_READ~62\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~62_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( !\myVirtualToplevel|IO_DATA_READ~61_combout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\) # (!\myVirtualToplevel|IO_DATA_READ~56_combout\) ) ) ) # ( +-- !\myVirtualToplevel|UART1_CS~combout\ & ( !\myVirtualToplevel|IO_DATA_READ~61_combout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\) # (!\myVirtualToplevel|IO_DATA_READ~57_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111111100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~46_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ~57_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ~56_combout\, + datae => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~61_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~62_combout\); + +-- Location: MLABCELL_X13_Y6_N12 +\myVirtualToplevel|UART1|Add9~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~27_combout\ = (!\myVirtualToplevel|UART1_CS~combout\ & ((\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7)))) # (\myVirtualToplevel|UART1_CS~combout\ & (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7), + datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7), + combout => \myVirtualToplevel|UART1|Add9~27_combout\); + +-- Location: MLABCELL_X13_Y7_N24 +\myVirtualToplevel|UART1|Add9~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|Add9~13_sumout\ = SUM(( \myVirtualToplevel|UART1|Add9~27_combout\ ) + ( (!\myVirtualToplevel|IO_SELECT~combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7))))) # (\myVirtualToplevel|IO_SELECT~combout\ & +-- ((!\myVirtualToplevel|Equal4~0_combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7)))) # (\myVirtualToplevel|Equal4~0_combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7))))) ) + ( \myVirtualToplevel|UART1|Add9~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000011111110100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(7), + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_Add9~27_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(7), + cin => \myVirtualToplevel|UART1|Add9~10\, + sumout => \myVirtualToplevel|UART1|Add9~13_sumout\); + +-- Location: LABCELL_X14_Y10_N45 +\myVirtualToplevel|IO_DATA_READ~63\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~63_combout\ = ( \myVirtualToplevel|UART1|Add9~13_sumout\ & ( (!\myVirtualToplevel|IO_DATA_READ~62_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- !\myVirtualToplevel|TIMER0_CS~1_combout\))) ) ) # ( !\myVirtualToplevel|UART1|Add9~13_sumout\ & ( !\myVirtualToplevel|IO_DATA_READ~62_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110100111100001111010011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ~62_combout\, + datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + dataf => \myVirtualToplevel|UART1|ALT_INV_Add9~13_sumout\, + combout => \myVirtualToplevel|IO_DATA_READ~63_combout\); + +-- Location: FF_X14_Y10_N46 +\myVirtualToplevel|IO_DATA_READ[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~63_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(7)); + +-- Location: LABCELL_X21_Y13_N51 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SOCCFG[7]~feeder_combout\ = ( \myVirtualToplevel|Mux92~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_Mux92~0_combout\, + combout => \myVirtualToplevel|IO_DATA_READ_SOCCFG[7]~feeder_combout\); + +-- Location: FF_X21_Y13_N52 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SOCCFG[7]~feeder_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(7)); + +-- Location: LABCELL_X20_Y14_N30 +\myVirtualToplevel|MEM_DATA_READ[7]~84_RESYN8733\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[7]~84_RESYN8733_BDD8734\ = ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(7) & ( \myVirtualToplevel|SOCCFG_CS~combout\ ) ) # ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(7) & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( +-- \myVirtualToplevel|IO_DATA_READ\(7) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(7) & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(7) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(7), + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(7), + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[7]~84_RESYN8733_BDD8734\); + +-- Location: LABCELL_X20_Y14_N36 +\myVirtualToplevel|MEM_DATA_READ[7]~84\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[7]~84_combout\ = ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(7) & ( \myVirtualToplevel|MEM_DATA_READ[7]~84_RESYN8733_BDD8734\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(7) & ( \myVirtualToplevel|MEM_DATA_READ[7]~84_RESYN8733_BDD8734\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\) # (!\myVirtualToplevel|INTR0_CS~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(7) & ( !\myVirtualToplevel|MEM_DATA_READ[7]~84_RESYN8733_BDD8734\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\) # (\myVirtualToplevel|INTR0_CS~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(7) & ( !\myVirtualToplevel|MEM_DATA_READ[7]~84_RESYN8733_BDD8734\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((!\myVirtualToplevel|IO_SELECT~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101000111010001110100011101110111011101110100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datad => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(7), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~84_RESYN8733_BDD8734\, + combout => \myVirtualToplevel|MEM_DATA_READ[7]~84_combout\); + +-- Location: M10K_X30_Y18_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111111111111000000115000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001FFFFFD940000000000000000000000000000000000000000000000000000180002075FF9337AD6B753978BB5D774274C38676FB3D3C7FE2D0E0", + mem_init2 => "C5F1AFF1A2F81FF8F43B91EFF8E5503C1EFF87A1DC87BFCF47268BE07EE345FA089C1CBDC3F8E759DC4682078FFFCBFC138CF379D3B544F03E80313CFAE3F7189935068603F0E5FB01F872FD8663FC422215C01E7F98210420669439F0F862A0046DB5FFFFCF9F2EE00AE8BF7BC1A09EE6401527055A504BCE443CB96F12371597A41BC8C5CC5397B8850148B42A77F42A48E234AC482043047FC7E00AB92A02173C508083097800A2FAB4E60808C487D388E045164B01152C8838F12C30D807BE7C0A208D90442C328A48A3ECBD00FC139A20A52062678C7806FCF4868B78BE480FC02FF84385A693D0BDF40B10978C17D4D4843D047E0C208F3D112CEB0221", + mem_init1 => "ED30F0A9B214FA021B9033DC0420F00440061064004DE0EF62421142B0C08231E94BE0E804A88786828470264E47902DE0DC44C8290CE85000D9883C816414942B5308038801E23D20E001111747C0A78A02A524A24AFF01C220C009B41F1760EBF2D08B87A0BE7805FEC7E01901F9AA8461E96406317023B218FF813599144D10F0C670A009B8529358284F2149189E0B0000228E40692482919D11C540701202A0A6F01BB9C25C5A31C229904B460A4C2C11FC5037F32136A82CE000C2988CA84021C4C0689ED2047821BE940D1D249DEA21805BE4246021B20EF92BF06AF83A039ACF79C9E460E9C2A039D6E782A88801039A0D81704E8800642201422085", + mem_init0 => "61661D198383197AC354B411C184BD69026B40167215681403057DCAA0010401A00036AC05100481F58255D5263591C667AB44806DD110B00880807C7370886840800903861AF82F248A3C7DFF672374BC7B924938D1FC4788E1C3870E1C71C232D1E4AC6EF0958DDE1231A7EF9FCFE7EA1703714EA47970205DB02720A922DD14341027E1CE72A15AAAB89254201C3B1884F440A186042801026E025FD6CCC2BAD85F4567BF0AC156EC0B5D57982E2ADD841E8B380000007FE1FFC00000000000000000000000003FF87FF0FFE1FFC3FFFFFFFFFFF9249249249249249249FEFD0000000000000501343402000001000000020104000100000000002C080201", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 7, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 7, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X23_Y18_N6 +\myVirtualToplevel|MEM_DATA_READ[7]~107\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[7]~107_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[7]~84_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7~portbdataout\ & +-- ((\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|IO_DATA_READ_SD\(7)))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[7]~84_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15~portbdataout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|IO_DATA_READ_SD\(7)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000001010101101010101111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]~22_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(7), + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~84_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[7]~107_combout\); + +-- Location: FF_X23_Y18_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[7]~107_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(7)); + +-- Location: FF_X19_Y18_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(7)); + +-- Location: LABCELL_X19_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(7) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(7) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\); + +-- Location: LABCELL_X7_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[7]_NEW3197\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[7]_OTERM3198\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(7) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[7]_OTERM3198\); + +-- Location: FF_X7_Y22_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[7]_OTERM3198\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(7)); + +-- Location: LABCELL_X7_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[7]_NEW3133\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[7]_OTERM3134\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[7]_OTERM3134\); + +-- Location: FF_X7_Y22_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[7]_OTERM3134\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(7)); + +-- Location: LABCELL_X7_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[7]_NEW3005\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[7]_OTERM3006\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[7]_OTERM3006\); + +-- Location: FF_X7_Y22_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[7]_OTERM3006\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(7)); + +-- Location: LABCELL_X12_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[7]_NEW3069\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[7]_OTERM3070\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[7]_OTERM3070\); + +-- Location: FF_X12_Y23_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[7]_OTERM3070\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(7)); + +-- Location: LABCELL_X7_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux80~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(7)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(7)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011000000000000111101010011010100111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~0_combout\); + +-- Location: LABCELL_X6_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[7]_NEW2877\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[7]_OTERM2878\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(7) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[7]_OTERM2878\); + +-- Location: FF_X6_Y22_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[7]_OTERM2878\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(7)); + +-- Location: LABCELL_X10_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[7]_NEW2941\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[7]_OTERM2942\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[7]_OTERM2942\); + +-- Location: FF_X10_Y21_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[7]_OTERM2942\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(7)); + +-- Location: LABCELL_X10_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[7]_NEW2749\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[7]_OTERM2750\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[7]_OTERM2750\); + +-- Location: FF_X10_Y21_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[7]_OTERM2750\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(7)); + +-- Location: LABCELL_X6_Y22_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[7]_NEW2813\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[7]_OTERM2814\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(7) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[7]_OTERM2814\); + +-- Location: FF_X6_Y22_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[7]_OTERM2814\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(7)); + +-- Location: LABCELL_X12_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux80~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(7)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(7))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(7))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101000000001111000000110101001101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~1_combout\); + +-- Location: LABCELL_X7_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux80~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux80~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2_combout\); + +-- Location: FF_X10_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7)); + +-- Location: FF_X20_Y7_N55 +\myVirtualToplevel|SD_ADDR[0][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][7]~q\); + +-- Location: FF_X19_Y9_N22 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6), + sload => VCC, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(7)); + +-- Location: LABCELL_X19_Y9_N15 +\myVirtualToplevel|Mux76~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux76~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(7) & ( (\myVirtualToplevel|SD_ADDR[0][7]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|SD_ADDR[0][7]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][7]~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(7), + combout => \myVirtualToplevel|Mux76~0_combout\); + +-- Location: FF_X19_Y9_N16 +\myVirtualToplevel|IO_DATA_READ_SD[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux76~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(7)); + +-- Location: LABCELL_X20_Y14_N6 +\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ = ( !\myVirtualToplevel|MEM_DATA_READ[7]~84_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(7) & +-- (((\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\)))))) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[7]~84_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))) # (\myVirtualToplevel|IO_DATA_READ_SD\(7)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ +-- & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001101000100110011110100010000000011011101111100111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(7), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~84_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]~22_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\); + +-- Location: MLABCELL_X18_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~1_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\))) ) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[15]~135_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\))) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[15]~135_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111001111110011101000101010001011110011000000001010001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~0_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~107_Duplicate_164\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~19_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~135_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~1_combout\); + +-- Location: MLABCELL_X18_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~1_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~1_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~1_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000000000000000000011111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~50_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~2_combout\); + +-- Location: FF_X18_Y16_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~2_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~73_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(7)); + +-- Location: LABCELL_X17_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(7)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\); + +-- Location: LABCELL_X6_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~60\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~60_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add19~73_sumout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add19~73_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111111111100001111111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~73_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~60_combout\); + +-- Location: LABCELL_X6_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~74\); + +-- Location: LABCELL_X6_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~61_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~73_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~60_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~60_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~73_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~73_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~61_combout\); + +-- Location: LABCELL_X6_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[7]~62\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[7]~62_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp~61_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010000111110100101000011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~61_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[7]~62_combout\); + +-- Location: FF_X6_Y26_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[7]~62_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(7)); + +-- Location: MLABCELL_X9_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~63\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~63_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~77_sumout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000011111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~77_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~63_combout\); + +-- Location: LABCELL_X10_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~64\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~64_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|sp~63_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add21~77_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|sp~63_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add21~77_sumout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~77_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~77_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~63_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~64_combout\); + +-- Location: LABCELL_X10_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[8]~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[8]~65_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~64_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~64_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~64_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111111111111100000000000000001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~64_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[8]~65_combout\); + +-- Location: FF_X10_Y24_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[8]~65_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(8)); + +-- Location: LABCELL_X7_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1075~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1075~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000011111111111100001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~77_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1075~0_combout\); + +-- Location: FF_X7_Y32_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1075~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~77_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~77_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~52_combout\); + +-- Location: FF_X10_Y32_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_NEW_REG1410\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~52_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1411\); + +-- Location: FF_X13_Y31_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1409\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1411\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1409\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1409\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1409\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010011001101010101010101010101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]_OTERM1409\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]_OTERM1411\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1383\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53_combout\); + +-- Location: FF_X10_Y32_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_NEW_REG1580\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~52_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1581\); + +-- Location: FF_X10_Y28_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~77_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~77_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~51_combout\); + +-- Location: FF_X10_Y32_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_NEW_REG1582\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~51_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1583\); + +-- Location: LABCELL_X10_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1581\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1581\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1583\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1581\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1581\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1583\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1581\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1581\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001000110010001101110011011100110010001101110011001000110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]_OTERM1581\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]_OTERM1583\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1531\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~52_combout\); + +-- Location: LABCELL_X10_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~77_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~77_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~47_combout\); + +-- Location: FF_X10_Y32_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_NEW_REG1572\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~47_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1573\); + +-- Location: FF_X10_Y32_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_NEW_REG1570\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~48_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1571\); + +-- Location: LABCELL_X10_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1571\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1571\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1571\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1573\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1571\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110101010100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]_OTERM1573\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]_OTERM1571\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1541\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1539\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~48_combout\); + +-- Location: LABCELL_X10_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~77_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~77_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~50_combout\); + +-- Location: FF_X10_Y32_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_NEW_REG1598\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~50_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1599\); + +-- Location: FF_X10_Y32_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_NEW_REG1596\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~51_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1597\); + +-- Location: LABCELL_X10_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1597\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1597\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1599\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1597\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1597\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110000111100001111001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]_OTERM1599\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]_OTERM1597\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1563\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1565\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~51_combout\); + +-- Location: LABCELL_X10_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~48_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~51_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~52_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~48_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~51_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~52_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~48_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~51_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~52_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~48_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~51_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~52_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101001000110110011110001001110011011010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]~53_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]~52_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]~51_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~0_combout\); + +-- Location: FF_X7_Y32_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_NEW_REG1270\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~52_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1271\); + +-- Location: FF_X7_Y32_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_NEW_REG1272\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1075~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273\); + +-- Location: LABCELL_X6_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000101110000011000010111000011101001111110001110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~77_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~77_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~51_combout\); + +-- Location: FF_X6_Y32_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_NEW_REG1274\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~51_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1275\); + +-- Location: LABCELL_X7_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1275\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1271\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1271\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1271\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1271\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110101010101010101010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1271\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1275\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1253\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1255\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~52_combout\); + +-- Location: LABCELL_X7_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110000010101010011000001010101001111110101010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~77_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~77_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~48_combout\); + +-- Location: FF_X7_Y32_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_NEW_REG1496\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~48_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1497\); + +-- Location: FF_X7_Y32_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_NEW_REG1494\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~49_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1495\); + +-- Location: LABCELL_X7_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1475\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1475\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1497\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1495\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1495\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1495\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111111110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1475\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]_OTERM1497\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]_OTERM1495\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1473\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~49_combout\); + +-- Location: FF_X7_Y32_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_NEW_REG1374\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~55_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1375\); + +-- Location: LABCELL_X7_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000010100000101000000000111111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~77_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~77_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~54_combout\); + +-- Location: FF_X7_Y32_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_NEW_REG1376\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~54_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1377\); + +-- Location: LABCELL_X7_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1377\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1375\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1375\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1375\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1375\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001101010011010101010101010101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]_OTERM1375\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1279\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]_OTERM1377\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1281\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~55_combout\); + +-- Location: LABCELL_X6_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000101110000011000010111000011101001111110001110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~77_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~77_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~50_combout\); + +-- Location: FF_X6_Y32_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_NEW_REG1446\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~50_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1447\); + +-- Location: FF_X7_Y32_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_NEW_REG1444\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~51_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1445\); + +-- Location: LABCELL_X7_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1447\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1445\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1445\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1445\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1445\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001000100111011100000000111111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1423\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]_OTERM1447\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]_OTERM1445\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1425\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~51_combout\); + +-- Location: LABCELL_X7_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~55_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~51_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~49_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~52_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~55_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~51_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~49_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~52_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~55_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~51_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~49_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~52_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~55_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~51_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~49_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~52_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001100110111010000110000010001001111111101110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]~52_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]~49_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]~55_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]~51_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~1_combout\); + +-- Location: LABCELL_X14_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\); + +-- Location: LABCELL_X14_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~77_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011010010000000101101001000001111110111110000111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~77_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1_combout\); + +-- Location: LABCELL_X16_Y14_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector208~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001101100011001100110111001100000011010000111011001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector208~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~0_combout\); + +-- Location: FF_X16_Y14_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y13_N18 +\myVirtualToplevel|LessThan3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|LessThan3~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & (\myVirtualToplevel|IO_SELECT~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000000000000010000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9), + combout => \myVirtualToplevel|LessThan3~0_combout\); + +-- Location: MLABCELL_X23_Y14_N3 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node[1]\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(1) = ( \myVirtualToplevel|BRAM_WREN~1_combout\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) # ((\myVirtualToplevel|LessThan3~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001000100010001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\, + datae => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM1_WREN~0_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(1)); + +-- Location: MLABCELL_X18_Y8_N39 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[7]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[7]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100000001000000010010111111101111111011111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(15), + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[7]~3_combout\); + +-- Location: M10K_X11_Y7_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 7, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 7, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\); + +-- Location: FF_X12_Y11_N7 +\myVirtualToplevel|INT_ENABLE[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(15)); + +-- Location: FF_X19_Y11_N47 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INT_ENABLE\(15), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(15)); + +-- Location: FF_X14_Y12_N46 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~21_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(15)); + +-- Location: FF_X17_Y11_N46 +\myVirtualToplevel|MILLISEC_UP_COUNTER[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~45_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(15)); + +-- Location: FF_X13_Y11_N16 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[15]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~45_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[15]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y12_N48 +\myVirtualToplevel|IO_DATA_READ~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~31_combout\ = ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|Equal3~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # +-- (\myVirtualToplevel|MILLISEC_UP_COUNTER\(15))))) ) ) # ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|Equal3~0_combout\ & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(15) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000000000010000000000100011000000000010001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[15]~DUPLICATE_q\, + combout => \myVirtualToplevel|IO_DATA_READ~31_combout\); + +-- Location: LABCELL_X17_Y12_N39 +\myVirtualToplevel|IO_DATA_READ~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~32_combout\ = ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(15) & ( \myVirtualToplevel|IO_DATA_READ~31_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) # +-- (\myVirtualToplevel|TIMER0_CS~1_combout\) ) ) ) # ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(15) & ( \myVirtualToplevel|IO_DATA_READ~31_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) # +-- (\myVirtualToplevel|TIMER0_CS~1_combout\) ) ) ) # ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(15) & ( !\myVirtualToplevel|IO_DATA_READ~31_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- (!\myVirtualToplevel|IO_DATA_READ~28_combout\ & \myVirtualToplevel|TIMER0_CS~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|TIMER0_CS~1_combout\))))) ) ) ) # ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(15) & ( +-- !\myVirtualToplevel|IO_DATA_READ~31_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (!\myVirtualToplevel|TIMER0_CS~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101100000001111010111110000111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ~28_combout\, + datac => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(15), + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~31_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~32_combout\); + +-- Location: FF_X17_Y12_N40 +\myVirtualToplevel|IO_DATA_READ[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~32_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(15)); + +-- Location: FF_X19_Y11_N41 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux90~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(15)); + +-- Location: LABCELL_X19_Y11_N39 +\myVirtualToplevel|MEM_DATA_READ[15]~68_RESYN8717\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[15]~68_RESYN8717_BDD8718\ = ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(15) & ( \myVirtualToplevel|SOCCFG_CS~combout\ ) ) # ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(15) & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( +-- \myVirtualToplevel|IO_DATA_READ\(15) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(15) & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(15) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(15), + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(15), + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[15]~68_RESYN8717_BDD8718\); + +-- Location: LABCELL_X19_Y11_N45 +\myVirtualToplevel|MEM_DATA_READ[15]~68\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[15]~68_combout\ = ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(15) & ( \myVirtualToplevel|MEM_DATA_READ[15]~68_RESYN8717_BDD8718\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(15) & ( \myVirtualToplevel|MEM_DATA_READ[15]~68_RESYN8717_BDD8718\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\) # (!\myVirtualToplevel|INTR0_CS~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(15) & ( !\myVirtualToplevel|MEM_DATA_READ[15]~68_RESYN8717_BDD8718\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\) # (\myVirtualToplevel|INTR0_CS~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(15) & ( !\myVirtualToplevel|MEM_DATA_READ[15]~68_RESYN8717_BDD8718\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((!\myVirtualToplevel|IO_SELECT~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011000110110001101100011011101110111011101100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datad => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(15), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~68_RESYN8717_BDD8718\, + combout => \myVirtualToplevel|MEM_DATA_READ[15]~68_combout\); + +-- Location: FF_X19_Y11_N23 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]_NEW_REG94\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]~15_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]_OTERM95\); + +-- Location: LABCELL_X19_Y11_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]~15_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM81\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]_OTERM95\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM81\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]_OTERM95\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM81\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]_OTERM95\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM81\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]_OTERM95\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[15]_OTERM95\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]_OTERM81\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]~15_combout\); + +-- Location: M10K_X3_Y7_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001FFFFFDB400010000000000000000000000000000000000000000000000000000000B2007C90AC6488247F3C659929790C7F97037FC399FEC039", + mem_init2 => "345F03F71A2FD071FA81E3F0707A967D3F072FD40F2FC18CB3DC68BF41BE347192872F7FF00E6FCBE302E5C9F06DE40F2F31CC67AF4ADD9B6EB3275BDB69E07738C0A91FF603F0E5FB01F872FE583FD298922744399005685C61E80630C5F8D781EDC812493E7CE81426008120687046910C001F20A79C087F6D448685778DE14C1680AD9133E7BFD88088AFF222D03222C508C41E0474B660C023A4B0508790A06F324C85877A960A1D6211F172016812400EC570B851CC10100EF447C2CCBF3D0D043DF2FD1853BE203308AF092FFC45798C300C91397386718A23E458063E6A698083C2855E76062B480853AE418A7002E01180C71049AEEAFC1C23606078", + mem_init1 => "52E220971C01903267843701C17A05C0291CC40D507049F248F43F89B508F7C5B1604480795E47BC601060DF854E05198127092A56B1E06C8612517028CCC1182499D0AC2082386C52071C4D88078622E8370B020892182D39E8F3575DF1EEBF85ED68343FC34BEE42C8189A183EF428320D02088F22044EF04F8868903090800A9E0441124F63058483808F7AB75030A63B98118832029400261E8100A06FA061D25134A4FBEFBE0CD927942A08202701827C9063451F4DDE5A032947184E21140028004760B100E23A80C640791B850BF087063171DF04F993AA13742621FA42B0719633D7C1E91A0E149E070D31120BDC0EC00978D42120C080101802403C", + mem_init0 => "B938A28E1871B4528006D0C438DA2954D44D5917532DB9F02000AB3253E6190712B803539A08B81089558AC933209668881490189D825447ADC910C9CC6C3143314B0A0A43F00C04BBC8A5524958F062374BC9FFFF8D1FF4FE9D3A74E9D344F378F18637784AC6EF0918DDF9EFE7F3F9E4A9C2B06C37009C82A5B437450D1EA2AA2B7470314A52E5EFFEE76DA82EC0D404866186AD804403BC001148F015B32BE3B550D752E0A2ADD59EAAFFDC55B9BAB3D167EA91C1AA007E1FFC3FFFFFFFFFFFFFFFFFFFFFFFFFFF87FF0FFE1FFC3FFFFFFFFFFFFC924924924924924924FEF800000000000020040101060400000109010C08050000000022001122040F00", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 7, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 7, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X19_Y11_N12 +\myVirtualToplevel|MEM_DATA_READ[15]~135\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[15]~68_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(15) & +-- (((\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]~15_combout\)))))) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[15]~68_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))) # (\myVirtualToplevel|IO_DATA_READ_SD\(15)))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]~15_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001101000100110011110100010000000011011101111100111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(15), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~68_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[15]~15_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\); + +-- Location: FF_X14_Y13_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(15)); + +-- Location: LABCELL_X17_Y13_N51 +\myVirtualToplevel|IO_SELECT~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_SELECT~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|IO_SELECT~2_combout\); + +-- Location: LABCELL_X17_Y13_N39 +\myVirtualToplevel|SOCCFG_CS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SOCCFG_CS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|IO_SELECT~2_combout\ & (\myVirtualToplevel|IO_SELECT~0_combout\ & (\myVirtualToplevel|IO_SELECT~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000010000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|SOCCFG_CS~0_combout\); + +-- Location: MLABCELL_X13_Y10_N57 +\myVirtualToplevel|SD_ADDR[0][0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][0]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( \myVirtualToplevel|SD_CS~0_combout\ & ( (\myVirtualToplevel|UART1|Equal7~0_combout\ & (\myVirtualToplevel|SOCCFG_CS~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000001000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\, + datab => \myVirtualToplevel|ALT_INV_SOCCFG_CS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_CS~0_combout\, + combout => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\); + +-- Location: FF_X16_Y9_N49 +\myVirtualToplevel|SD_ADDR[0][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10), + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][10]~q\); + +-- Location: LABCELL_X20_Y10_N33 +\myVirtualToplevel|Mux73~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux73~0_combout\ = ( !\myVirtualToplevel|SD_STATE.SD_STATE_READ~q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\ & (!\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & !\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\, + datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\, + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_1~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~q\, + combout => \myVirtualToplevel|Mux73~0_combout\); + +-- Location: LABCELL_X19_Y10_N45 +\myVirtualToplevel|Mux73~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux73~1_combout\ = ( \myVirtualToplevel|Mux73~0_combout\ & ( (\myVirtualToplevel|SD_ADDR[0][10]~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) ) # ( +-- !\myVirtualToplevel|Mux73~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SD_ADDR[0][10]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000001111010100000000111101010000000000000101000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_ADDR[0][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_Mux73~0_combout\, + combout => \myVirtualToplevel|Mux73~1_combout\); + +-- Location: FF_X19_Y10_N47 +\myVirtualToplevel|IO_DATA_READ_SD[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux73~1_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(10)); + +-- Location: MLABCELL_X9_Y14_N48 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[2]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[2]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100110011001100111111001111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[2]~5_combout\); + +-- Location: M10K_X11_Y12_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 2, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 2, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X17_Y8_N36 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~2_combout\ = ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ & ( ((\myVirtualToplevel|UART1|RX_INTR~q\ & \myVirtualToplevel|INT_ENABLE\(10))) # (\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(10)) ) ) +-- # ( !\myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ & ( (\myVirtualToplevel|UART1|RX_INTR~q\ & \myVirtualToplevel|INT_ENABLE\(10)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~q\, + datac => \myVirtualToplevel|ALT_INV_INT_ENABLE\(10), + datad => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(10), + dataf => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\, + combout => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~2_combout\); + +-- Location: FF_X17_Y8_N37 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~2_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(10)); + +-- Location: LABCELL_X14_Y11_N12 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|status[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[10]~feeder_combout\ = ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(10), + combout => \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[10]~feeder_combout\); + +-- Location: FF_X14_Y11_N14 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|status[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[10]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(10)); + +-- Location: LABCELL_X14_Y11_N33 +\myVirtualToplevel|IO_DATA_READ_INTRCTL~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_INTRCTL~3_combout\ = ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|INT_ENABLE\(10)) ) ) # ( +-- !\myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|INT_ENABLE\(10)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ALT_INV_INT_ENABLE\(10), + dataf => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(10), + combout => \myVirtualToplevel|IO_DATA_READ_INTRCTL~3_combout\); + +-- Location: FF_X14_Y11_N34 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_INTRCTL~3_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(10)); + +-- Location: LABCELL_X17_Y12_N24 +\myVirtualToplevel|Mux93~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux93~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|Mux93~0_combout\); + +-- Location: FF_X17_Y12_N26 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux93~0_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(10)); + +-- Location: FF_X12_Y12_N31 +\myVirtualToplevel|SECOND_DOWN_COUNTER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add19~13_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(10)); + +-- Location: FF_X13_Y11_N1 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~61_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(10)); + +-- Location: LABCELL_X16_Y12_N30 +\myVirtualToplevel|IO_DATA_READ~108\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~108_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (\myVirtualToplevel|INTR0_CS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(10) & +-- (\myVirtualToplevel|TIMER0_CS~2_combout\)))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (\myVirtualToplevel|INTR0_CS~0_combout\ & (\myVirtualToplevel|TIMER0_CS~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ((\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SECOND_DOWN_COUNTER\(10)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000000100000000000000000100000000000001000000000001000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(10), + datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(10), + datag => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(10), + combout => \myVirtualToplevel|IO_DATA_READ~108_combout\); + +-- Location: LABCELL_X17_Y12_N6 +\myVirtualToplevel|IO_DATA_READ~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~44_combout\ = ( \myVirtualToplevel|IO_DATA_READ~108_combout\ ) # ( !\myVirtualToplevel|IO_DATA_READ~108_combout\ & ( (\myVirtualToplevel|IO_DATA_READ[11]~42_combout\ & ((!\myVirtualToplevel|IO_DATA_READ~43_combout\ & +-- (\myVirtualToplevel|MILLISEC_UP_COUNTER\(10))) # (\myVirtualToplevel|IO_DATA_READ~43_combout\ & ((\myVirtualToplevel|RTC_YEAR_COUNTER\(10)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011000000100001001111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ~43_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ[11]~42_combout\, + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(10), + datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(10), + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~108_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~44_combout\); + +-- Location: FF_X17_Y12_N8 +\myVirtualToplevel|IO_DATA_READ[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~44_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(10)); + +-- Location: LABCELL_X17_Y12_N27 +\myVirtualToplevel|MEM_DATA_READ[10]~78_RESYN8727\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[10]~78_RESYN8727_BDD8728\ = ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(10) ) ) # ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(10) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(10), + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(10), + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[10]~78_RESYN8727_BDD8728\); + +-- Location: LABCELL_X19_Y12_N27 +\myVirtualToplevel|MEM_DATA_READ[10]~78\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[10]~78_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[10]~78_RESYN8727_BDD8728\ & ( +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[10]~78_RESYN8727_BDD8728\ & ( +-- (!\myVirtualToplevel|INTR0_CS~combout\) # ((!\myVirtualToplevel|IO_SELECT~combout\) # (\myVirtualToplevel|IO_DATA_READ_INTRCTL\(10))) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[10]~78_RESYN8727_BDD8728\ +-- & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[10]~78_RESYN8727_BDD8728\ & ( +-- (!\myVirtualToplevel|IO_SELECT~combout\) # ((\myVirtualToplevel|INTR0_CS~combout\ & \myVirtualToplevel|IO_DATA_READ_INTRCTL\(10))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011011101000011110000111111101110111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(10), + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~78_RESYN8727_BDD8728\, + combout => \myVirtualToplevel|MEM_DATA_READ[10]~78_combout\); + +-- Location: FF_X20_Y12_N40 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]_NEW_REG50\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]~19_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]_OTERM51\); + +-- Location: LABCELL_X20_Y12_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]~19_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]_OTERM51\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM25\)) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]_OTERM51\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM25\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011000000000000001111111100111111111111110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]_OTERM25\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[10]_OTERM51\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]~19_combout\); + +-- Location: M10K_X3_Y12_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111133333333333311111000115066E26DEE83A742A50C83200866E40653B4035366218862324C8448400434481459894B436873679D1C1E8CE48123F051540175555575E2212649A8C3188300008060260E8800305848101000000032932E00001FB5571552946EC50178E000008831C24025481D51BD381105", + mem_init2 => "0004807C901384E07AA120F4E4C9235C8F4EC39108C3D31C4752000C124120085221BC1D95AAF3CCD09A1768D4D46091AD844922C5860A317E0D9987FC0165068A0533CF4950B24106A95960F7A19D0C22F854A88ACB397C0E48A6E503A4433E97C89780000060AAEBF9F3823276EFB6EEC3B5415B16739A5B612990DC48A4091579B480D380735439CF4F49F61CB9361CAAF832A1B11C499B257AFB6B8D9E6F38DCDD054004176A462ADC86626EB70A4C66681B1322AD03B1FC8A31B82D75DA88FEE5AF9E406B06A2BCC65118D3550F1C8891069E12F21028E3524828E984A7B82452249D5E118E5ABC96D6D2898891106CAC07399429B437A00DC5F6F5C72A", + mem_init1 => "891611220EB7A07581A395468C22E0F644DFBE23A9E0854482C337376632B279C78A3B279A1A09032AEA40E69CC450012CDD09E76BCC7FDE22F135A2C005062F004D47429D60EADA832806204781C00E240834F08261D9F10C4586088201541521972CD2DE3C0A98401178104CF5CAFFD5BE0CA0BEE197DD3BBB90834ADF712002183D880978478A43F89363683C1FE37107CB0F612C71F0E8287CC82F17E6219A0A2633401AC08837442685D2BDCADE64471125DC5F266225004E56766A34C091C2FA5DA80BFB088036480DBC210C8212A00C3923C5450101CAAD804F01AD1300E38410809211ED03E56B310F35E008BD71A0051C2FE85CA5D75384B279079B", + mem_init0 => "4C09223CC70004DA411A5C2580326D3119850DF102A01140DB7E8084AD1823E8AC97ED88A876E1FB67014404EEF7EF26C2C23082C82D841800924885810BDC2C0585A5B229C9CBA511F0BA6A495B89D6E48392A2C15208B8270A142850A498035AC514802120D0042412019D08F47A3D2300818F6A36750C822A4FB5A6CD9540401E05B79D294B183541F6FEC0F0BB08865C861E481328719620E446E03E666E476DF99CF500EFEBBE073F88B07D7377C0E553BF8A832600C5B56B6EEAEEEEAAAAAAEEEEEAEEAEAEAD6D5ADAB5B76B6FFFFFFFFFFFFC024924924924804804FFFD0003000100012E26737329130000001008300A0300000003040320AB130100", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 2, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 2, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X19_Y12_N42 +\myVirtualToplevel|MEM_DATA_READ[10]~119\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[10]~78_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(10) & +-- (((\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]~19_combout\)))))) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[10]~78_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))) # (\myVirtualToplevel|IO_DATA_READ_SD\(10)))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]~19_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000010100100010101011110010001000000101011101111010111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(10), + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~78_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[10]~19_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\); + +-- Location: LABCELL_X20_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector348~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector348~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~61_sumout\ & ( (\myVirtualToplevel|MEM_DATA_READ[26]~56_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~61_sumout\ & ( (\myVirtualToplevel|MEM_DATA_READ[10]~119_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add7~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & +-- \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add7~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & +-- \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000000001100110000111111001111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~119_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~56_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector348~0_combout\); + +-- Location: FF_X20_Y15_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector348~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(10)); + +-- Location: LABCELL_X20_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(10)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(10)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\); + +-- Location: LABCELL_X6_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~62\); + +-- Location: LABCELL_X10_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011111111110011001111111100000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~61_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~51_combout\); + +-- Location: LABCELL_X10_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|sp~51_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add21~61_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|sp~51_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add21~61_sumout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~61_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~51_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~52_combout\); + +-- Location: LABCELL_X10_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~52_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~52_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~52_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111111111111100000000000000001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~52_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~53_combout\); + +-- Location: FF_X10_Y24_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~53_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(10)); + +-- Location: MLABCELL_X4_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~65_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~54_combout\); + +-- Location: LABCELL_X6_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~66\); + +-- Location: LABCELL_X10_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~65_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~54_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~54_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~65_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~65_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~55_combout\); + +-- Location: LABCELL_X10_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[11]~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[11]~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~55_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\))) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~55_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111111111000000111111111100000000111111000000000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~55_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[11]~56_combout\); + +-- Location: FF_X10_Y25_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[11]~56_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(11)); + +-- Location: LABCELL_X6_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add21~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~34\); + +-- Location: LABCELL_X10_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111110101111101011111010111100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~33_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~30_combout\); + +-- Location: LABCELL_X10_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~33_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~30_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~33_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~31_combout\); + +-- Location: LABCELL_X10_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~31_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(12) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\))) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~31_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(12)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111111111000100011111111100000000111011100000000011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~32_combout\); + +-- Location: FF_X10_Y25_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~32_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\); + +-- Location: MLABCELL_X9_Y26_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~37_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~37_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(13) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~37_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(13) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000000000000000000011110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~37_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~33_combout\); + +-- Location: MLABCELL_X9_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~37_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~33_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~37_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~37_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~33_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~34_combout\); + +-- Location: MLABCELL_X9_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~34_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(13) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\))) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~34_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(13)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111111111000000111111111100000000111111000000000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~34_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~35_combout\); + +-- Location: FF_X9_Y25_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~35_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(13)); + +-- Location: LABCELL_X7_Y26_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add20~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~46\); + +-- Location: LABCELL_X5_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~1_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(16)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~1_sumout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~4_combout\); + +-- Location: MLABCELL_X9_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~1_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~4_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~7_combout\); + +-- Location: MLABCELL_X9_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~7_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(16)) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111100000000001111110000000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~8_combout\); + +-- Location: FF_X9_Y25_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~8_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16)); + +-- Location: LABCELL_X5_Y24_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~1_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\); + +-- Location: LABCELL_X7_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~12_combout\); + +-- Location: LABCELL_X6_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~12_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~12_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~12_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~12_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101110101111111100010101000000001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1067~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[16]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~13_combout\); + +-- Location: FF_X6_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~13_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(16)); + +-- Location: LABCELL_X7_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~16_combout\); + +-- Location: LABCELL_X7_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~16_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(16) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~16_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101010001101010111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[16]~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1067~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~17_combout\); + +-- Location: FF_X7_Y29_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(16)); + +-- Location: LABCELL_X7_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~13_combout\); + +-- Location: LABCELL_X7_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~13_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~13_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~13_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~13_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101111111010111100010000010100001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1067~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[16]~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~14_combout\); + +-- Location: FF_X7_Y31_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~14_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(16)); + +-- Location: LABCELL_X7_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~10_combout\); + +-- Location: LABCELL_X7_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~10_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(16) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001010001011010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[16]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1067~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~11_combout\); + +-- Location: FF_X7_Y28_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~11_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(16)); + +-- Location: LABCELL_X7_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(16) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(16) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(16) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(16) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~1_combout\); + +-- Location: LABCELL_X7_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~13_combout\); + +-- Location: LABCELL_X7_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~13_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~13_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(16) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000001011011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1067~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~14_combout\); + +-- Location: FF_X7_Y29_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~14_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(16)); + +-- Location: LABCELL_X7_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~14_combout\); + +-- Location: LABCELL_X7_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~14_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~14_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(16) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1067~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[16]~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~15_combout\); + +-- Location: FF_X7_Y29_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~15_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(16)); + +-- Location: LABCELL_X7_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~12_combout\); + +-- Location: LABCELL_X7_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~12_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~12_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~12_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~12_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000101011111110111100010000010100001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1067~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[16]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~13_combout\); + +-- Location: FF_X7_Y29_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~13_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(16)); + +-- Location: LABCELL_X7_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~9_combout\); + +-- Location: LABCELL_X7_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~9_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~9_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101111111010111100010000010100001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1067~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[16]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~10_combout\); + +-- Location: FF_X7_Y29_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(16)); + +-- Location: LABCELL_X7_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(16) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(16) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(16) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(16) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~0_combout\); + +-- Location: LABCELL_X7_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\); + +-- Location: LABCELL_X12_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12612\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12612_BDD12613\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111011101110111011100001100001111110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12612_BDD12613\); + +-- Location: LABCELL_X16_Y14_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12614\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12614_BDD12615\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~1_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12614_BDD12615\); + +-- Location: LABCELL_X16_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12612_BDD12613\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12614_BDD12615\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12614_BDD12615\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12612_BDD12613\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12614_BDD12615\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000010111111000100001011111100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_RESYN12612_BDD12613\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_RESYN12614_BDD12615\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_combout\); + +-- Location: LABCELL_X16_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]_NEW3335\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]_OTERM3336\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\) # (\myVirtualToplevel|MEM_DATA_READ[16]~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # (\myVirtualToplevel|MEM_DATA_READ[16]~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101111111110000010100000000101011111111111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]_OTERM3336\); + +-- Location: FF_X16_Y14_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]_OTERM3336\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)); + +-- Location: MLABCELL_X23_Y14_N57 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node[1]\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1) = ( \myVirtualToplevel|BRAM_WREN~1_combout\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) # ((\myVirtualToplevel|LessThan3~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001000100010001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\, + datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\, + datae => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM0_WREN~0_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1)); + +-- Location: M10K_X11_Y19_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X19_Y16_N12 +\myVirtualToplevel|MEM_DATA_READ[0]~95\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[0]~95_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[0]~94_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- ((\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|IO_DATA_READ_SD\(0)))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[0]~94_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8~portbdataout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|IO_DATA_READ_SD\(0)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000110011110011001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]~34_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(0), + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[0]~95_combout\); + +-- Location: FF_X19_Y16_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[0]~95_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(0)); + +-- Location: FF_X19_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(0)); + +-- Location: LABCELL_X19_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(0) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\); + +-- Location: LABCELL_X1_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[30]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[30]~feeder_combout\); + +-- Location: LABCELL_X1_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[31]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[31]~feeder_combout\); + +-- Location: LABCELL_X1_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~feeder_combout\); + +-- Location: LABCELL_X1_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[33]~feeder_combout\); + +-- Location: LABCELL_X1_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[34]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[34]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[34]~feeder_combout\); + +-- Location: LABCELL_X1_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~feeder_combout\); + +-- Location: LABCELL_X1_Y26_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[36]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[36]~feeder_combout\); + +-- Location: LABCELL_X1_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[37]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[37]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[38]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[38]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[38]~feeder_combout\); + +-- Location: LABCELL_X1_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~feeder_combout\); + +-- Location: LABCELL_X1_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[41]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[41]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[43]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[43]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[43]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[44]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[44]~feeder_combout\); + +-- Location: LABCELL_X1_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[45]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[45]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[45]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[46]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[46]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[46]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[47]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[47]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[47]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[49]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[50]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[50]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[50]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[51]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[51]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[51]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[52]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[52]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[52]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[53]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[53]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[53]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[54]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[54]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[54]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[55]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[55]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[55]~feeder_combout\); + +-- Location: LABCELL_X2_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[56]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[56]~feeder_combout\); + +-- Location: FF_X2_Y25_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[56]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(57), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56)); + +-- Location: FF_X2_Y25_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[55]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(55)); + +-- Location: FF_X2_Y25_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[54]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(55), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(54)); + +-- Location: FF_X2_Y25_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[53]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(54), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(53)); + +-- Location: FF_X2_Y25_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[52]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(53), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(52)); + +-- Location: FF_X2_Y25_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[51]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(52), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(51)); + +-- Location: FF_X2_Y25_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[50]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(51), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(50)); + +-- Location: FF_X2_Y25_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[49]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(50), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49)); + +-- Location: FF_X2_Y25_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(48)); + +-- Location: FF_X2_Y25_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[47]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(48), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(47)); + +-- Location: FF_X2_Y25_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[46]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(47), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(46)); + +-- Location: FF_X1_Y26_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[45]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(46), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(45)); + +-- Location: FF_X2_Y25_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[44]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(45), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(44)); + +-- Location: FF_X2_Y25_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[43]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(44), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(43)); + +-- Location: LABCELL_X1_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]_NEW3330\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]_OTERM3331\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(42) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(42) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(43), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[0]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]_OTERM3331\); + +-- Location: FF_X1_Y26_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]_OTERM3331\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(42)); + +-- Location: FF_X1_Y26_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[41]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(42), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(41)); + +-- Location: FF_X1_Y26_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(41), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(40)); + +-- Location: LABCELL_X1_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[39]_NEW3325\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[39]_OTERM3326\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(40))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(39) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(40))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(40), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[0]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[39]_OTERM3326\); + +-- Location: FF_X1_Y26_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[39]_OTERM3326\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(39)); + +-- Location: FF_X2_Y25_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[38]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(39), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(38)); + +-- Location: FF_X1_Y26_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[37]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(38), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(37)); + +-- Location: FF_X1_Y26_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[36]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(37), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(36)); + +-- Location: FF_X1_Y26_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(36), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(35)); + +-- Location: FF_X1_Y26_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[34]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(35), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(34)); + +-- Location: FF_X1_Y26_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[33]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(34), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(33)); + +-- Location: FF_X1_Y26_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(33), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(32)); + +-- Location: FF_X1_Y26_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[31]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(32), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(31)); + +-- Location: FF_X1_Y26_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[30]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(31), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(30)); + +-- Location: FF_X2_Y26_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(30), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(29)); + +-- Location: FF_X1_Y31_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(29), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(28)); + +-- Location: FF_X1_Y31_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(28), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(27)); + +-- Location: LABCELL_X1_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(28) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(27) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(28) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(27) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001100000000110000110000000000000000110000110000000011000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~54_combout\); + +-- Location: LABCELL_X1_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(24) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(25)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(25)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000110000110000000011000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~55_combout\); + +-- Location: LABCELL_X1_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(26) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~54_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~55_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(26) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~54_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~55_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~54_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(26), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~55_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~56_combout\); + +-- Location: FF_X2_Y26_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]_OTERM1707\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~DUPLICATE_q\); + +-- Location: LABCELL_X2_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(29)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(30) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(29) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(29))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(30) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(29) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000111100000010000011110010111100001111111111110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(29), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[30]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~20_combout\); + +-- Location: FF_X1_Y26_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(33), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~DUPLICATE_q\); + +-- Location: LABCELL_X2_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[33]_NEW1634\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[33]_OTERM1635\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(33) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100010001000100010001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[33]_OTERM1635\); + +-- Location: FF_X2_Y26_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[33]_OTERM1635\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(33)); + +-- Location: LABCELL_X2_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[35]_NEW1638\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[35]_OTERM1639\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(35) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100010001000100010001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(35), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[35]_OTERM1639\); + +-- Location: FF_X2_Y26_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[35]_OTERM1639\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(35)); + +-- Location: FF_X1_Y26_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(36), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE_q\); + +-- Location: LABCELL_X2_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[34]_NEW1636\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[34]_OTERM1637\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(34))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011110010000000101111001000000010111100100000001011110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[34]_OTERM1637\); + +-- Location: FF_X2_Y26_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[34]_OTERM1637\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(34)); + +-- Location: LABCELL_X2_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(34) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(35) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(34) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(33) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(33))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(35) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(34) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(33) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(33))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(34) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(35) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(34) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(33) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(33))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(35) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(34) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(33) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(33))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000010000000000001000010000000000000000100001000000000000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(33), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(35), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(33), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(34), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[35]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~16_combout\); + +-- Location: LABCELL_X2_Y26_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[32]_NEW1632\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[32]_OTERM1633\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(32) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(32) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010111100101111001000000010000000101111001011110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(32), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[32]_OTERM1633\); + +-- Location: FF_X2_Y26_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[32]_OTERM1633\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(32)); + +-- Location: LABCELL_X2_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(35)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(33) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(33) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(34)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(33) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(35) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(33) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(34)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(35)) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(33) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(33))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(34))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(35) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(33) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(33))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(34)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100011001100110011101111111100000000000010001100110011001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(33), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(35), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(33), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(34), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[35]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~19_combout\); + +-- Location: LABCELL_X2_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~20_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~16_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~19_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~16_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~20_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111100011111000111111101111111000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[32]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(32), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~21_combout\); + +-- Location: LABCELL_X1_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~61_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(23))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(23)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110011000000111111001100000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~61_combout\); + +-- Location: LABCELL_X1_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~59_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(25)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(24) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(25))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(24) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(25)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000011110101010100001111010100000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~59_combout\); + +-- Location: LABCELL_X1_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~58_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(28)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28) & ((\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(28)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(27)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(27) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(28))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101010101111000010101010111100000000101010100000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(28), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~58_combout\); + +-- Location: LABCELL_X1_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~60\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~60_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~58_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~54_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~59_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(26))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~59_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(26))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101110111010111110111011101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~54_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~59_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~58_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~60_combout\); + +-- Location: LABCELL_X1_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~62\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~62_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~60_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~56_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~61_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011000000111100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~56_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~61_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~60_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~62_combout\); + +-- Location: LABCELL_X2_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(57) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(57) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(58) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(58)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(57) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(58) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(58)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001000010010000100100001001000000001001000010010000100100001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(58), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(58), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~1_combout\); + +-- Location: LABCELL_X1_Y25_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[56]_NEW1680\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[56]_OTERM1681\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000100010111011100010001011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(56), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[56]_OTERM1681\); + +-- Location: FF_X1_Y25_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[56]_OTERM1681\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56)); + +-- Location: LABCELL_X1_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[55]_NEW1678\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[55]_OTERM1679\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[55]_OTERM1679\); + +-- Location: FF_X1_Y27_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[55]_OTERM1679\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55)); + +-- Location: LABCELL_X1_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[54]_NEW1676\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[54]_OTERM1677\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(54)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(54)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000100010111011100010001011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[54]_OTERM1677\); + +-- Location: FF_X1_Y25_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[54]_OTERM1677\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(54)); + +-- Location: LABCELL_X1_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(55) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(54) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(54) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(54) & (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(55) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(54) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(54) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(54) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001000000000000000010010000000000000000100100000000000000001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(56), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(56), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(54), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(55), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(55), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~2_combout\); + +-- Location: LABCELL_X1_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[53]_NEW1674\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[53]_OTERM1675\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(53))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(53) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000111111001100000011111100110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(53), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[53]_OTERM1675\); + +-- Location: FF_X1_Y25_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[53]_OTERM1675\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(53)); + +-- Location: LABCELL_X1_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56) & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56)) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(54))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(54))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(54) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(55) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56) & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(54) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(54) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(54) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100110101000100010001000100010011011101010011011101110101000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(56), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(56), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(54), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(55), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(55), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~5_combout\); + +-- Location: FF_X1_Y25_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]_OTERM1673\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(52)); + +-- Location: LABCELL_X1_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]_NEW1672\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]_OTERM1673\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(52)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(52)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110000111111000011000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]_OTERM1673\); + +-- Location: FF_X1_Y25_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]_OTERM1673\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE_q\); + +-- Location: LABCELL_X1_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[51]_NEW1670\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[51]_OTERM1671\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(51)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(51)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000100010111011100010001011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(51), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[51]_OTERM1671\); + +-- Location: FF_X1_Y25_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[51]_OTERM1671\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(51)); + +-- Location: LABCELL_X1_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[50]_NEW1668\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[50]_OTERM1669\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(50)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(50)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001010111110100000101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[50]_OTERM1669\); + +-- Location: FF_X1_Y25_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[50]_OTERM1669\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(50)); + +-- Location: LABCELL_X1_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(52) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(51)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(50))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(52) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(51)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(50))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(50) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(52) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(51))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(52) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(51)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(52) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(51) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(50)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(52) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(51) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(50))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(50) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(51) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(52) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100110101000100010011010100110101001101110111010100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(52), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[52]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(51), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(50), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~6_combout\); + +-- Location: LABCELL_X1_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(53) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(53))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(53)) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(53))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000010110000111100001011000010110000101000001011000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(53), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~7_combout\); + +-- Location: LABCELL_X1_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(52) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(52) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(51) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(51)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(52) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(52) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(51) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(51)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010010100000000101001010000000000000000101001010000000010100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(51), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(51), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(52), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~3_combout\); + +-- Location: LABCELL_X1_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(53) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(50) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(50))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(53) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(53) & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(50) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(50))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001000000001000000001000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(50), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(53), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(50), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~4_combout\); + +-- Location: LABCELL_X1_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000000000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~8_combout\); + +-- Location: LABCELL_X1_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[36]_NEW1640\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[36]_OTERM1641\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(36)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(36)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000100010111011100010001011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[36]_OTERM1641\); + +-- Location: FF_X1_Y29_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[36]_OTERM1641\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(36)); + +-- Location: FF_X1_Y29_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]_OTERM1643\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(37)); + +-- Location: LABCELL_X1_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]_NEW1642\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]_OTERM1643\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(37)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(37)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110000111111000011000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]_OTERM1643\); + +-- Location: FF_X1_Y29_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]_OTERM1643\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]~DUPLICATE_q\); + +-- Location: LABCELL_X1_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(37) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(36) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(36)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(37) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(36) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(36)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010010100000000101001010000000000000000101001010000000010100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(36), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(36), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[37]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~12_combout\); + +-- Location: FF_X1_Y26_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(41), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~DUPLICATE_q\); + +-- Location: LABCELL_X1_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[39]_NEW1646\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[39]_OTERM1647\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(39) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[39]_OTERM1647\); + +-- Location: FF_X1_Y25_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[39]_OTERM1647\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(39)); + +-- Location: LABCELL_X1_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[38]_NEW1644\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[38]_OTERM1645\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(38)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(38)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000100010111011100010001011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[38]_OTERM1645\); + +-- Location: FF_X1_Y25_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[38]_OTERM1645\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(38)); + +-- Location: LABCELL_X1_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(38) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(38) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(39) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(39)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(38) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(38) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(39) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(39)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001100000000110000110000000000000000110000110000000011000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(39), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(39), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~10_combout\); + +-- Location: LABCELL_X1_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[40]_NEW1648\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[40]_OTERM1649\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(40)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(40)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000100010111011100010001011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[40]_OTERM1649\); + +-- Location: FF_X1_Y29_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[40]_OTERM1649\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(40)); + +-- Location: FF_X1_Y26_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]_OTERM3331\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]~DUPLICATE_q\); + +-- Location: LABCELL_X1_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[42]_NEW1652\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[42]_OTERM1653\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(42)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(42)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000100010111011100010001011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[42]_OTERM1653\); + +-- Location: FF_X1_Y29_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[42]_OTERM1653\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(42)); + +-- Location: LABCELL_X1_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[41]_NEW1650\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[41]_OTERM1651\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(41)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(41)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110000111111000011000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[41]_OTERM1651\); + +-- Location: FF_X1_Y29_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[41]_OTERM1651\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(41)); + +-- Location: LABCELL_X1_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(41) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(41) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(42)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(41) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(41) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(42)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010010100000000101001010000000000000000101001010000000010100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[42]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(42), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(41), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~9_combout\); + +-- Location: LABCELL_X1_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(40)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[40]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~11_combout\); + +-- Location: LABCELL_X2_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(31) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(31) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(30)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(31) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(30)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000001010000101000000101000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[30]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~17_combout\); + +-- Location: LABCELL_X2_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(29) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~17_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(32) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~16_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(29) & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~17_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(32) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010000000010000000000000000000000001000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(32), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~17_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[32]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~18_combout\); + +-- Location: LABCELL_X2_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[46]_NEW1660\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[46]_OTERM1661\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(46) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(46) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(46) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110000001100001111110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(46), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[46]_OTERM1661\); + +-- Location: FF_X2_Y27_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[46]_OTERM1661\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(46)); + +-- Location: LABCELL_X2_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[43]_NEW1654\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[43]_OTERM1655\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(43)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(43)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000100010111011100010001011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[43]_OTERM1655\); + +-- Location: FF_X2_Y27_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[43]_OTERM1655\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(43)); + +-- Location: LABCELL_X2_Y27_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[45]_NEW1658\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[45]_OTERM1659\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(45)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(45)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001010111110100000101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[45]_OTERM1659\); + +-- Location: FF_X2_Y27_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[45]_OTERM1659\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(45)); + +-- Location: LABCELL_X2_Y27_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[44]_NEW1656\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[44]_OTERM1657\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(44)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(44)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001010111110100000101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[44]_OTERM1657\); + +-- Location: FF_X2_Y27_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[44]_OTERM1657\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(44)); + +-- Location: LABCELL_X2_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(44) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(44) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(45) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(45)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(44) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(44) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(45) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(45)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001100000000110000110000000000000000110000110000000011000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(45), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(45), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(44), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~14_combout\); + +-- Location: LABCELL_X2_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[48]_NEW1664\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[48]_OTERM1665\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110000001100001111110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(48), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[48]_OTERM1665\); + +-- Location: FF_X2_Y27_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[48]_OTERM1665\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48)); + +-- Location: LABCELL_X2_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[49]_NEW1666\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[49]_OTERM1667\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001010111110100000101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(49), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[49]_OTERM1667\); + +-- Location: FF_X2_Y27_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[49]_OTERM1667\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49)); + +-- Location: FF_X2_Y25_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\); + +-- Location: LABCELL_X2_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[47]_NEW1662\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[47]_OTERM1663\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(47)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(47)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000100010111011100010001011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(47), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[47]_OTERM1663\); + +-- Location: FF_X2_Y27_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[47]_OTERM1663\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(47)); + +-- Location: LABCELL_X2_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(47) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(47) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(47) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(47) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000010000100001000000000000000000000000000000001000010000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(48), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(49), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[48]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(49), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(47), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(47), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~13_combout\); + +-- Location: LABCELL_X2_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(46) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(46) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(43) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(43))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(46) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(46) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(43) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(43))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001000010000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(46), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(43), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(46), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(43), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~15_combout\); + +-- Location: LABCELL_X1_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~12_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~12_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~21_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~11_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000001100000000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~22_combout\); + +-- Location: LABCELL_X1_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(37) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(36) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(37) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(37) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(37)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(36) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(36))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110000101100100011000010110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(36), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(37), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(37), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~26_combout\); + +-- Location: LABCELL_X1_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(41) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(41) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(42)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(41) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(42))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(41) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(42)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000010101111000010101010111100001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(41), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[42]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(41), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~23_combout\); + +-- Location: LABCELL_X1_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(39) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(39)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(38) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(38))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(39) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(39) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(38) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(38))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000000000000001100000011001100111111001100110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(39), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(38), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(39), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~24_combout\); + +-- Location: LABCELL_X1_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~24_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~23_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~9_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(40))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~24_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~23_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(40))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110000011110000111000001111000011000000111000001100000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[40]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~24_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~25_combout\); + +-- Location: LABCELL_X2_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(47) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(47) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(47) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(47) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(47) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(47) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(47) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(47) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100011001110000010001100111010001100111011110000100011001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(48), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(49), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[48]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(49), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(47), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(47), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~27_combout\); + +-- Location: LABCELL_X2_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(45) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(45)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(44) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(43)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(44)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(44) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(43) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(44)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(45) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(45)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(44) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(44))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(43) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(45) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(45) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(44) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(43)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(44)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(44) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(43) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(44))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(43) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(45) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(45) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(44) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(44))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010001000100000001010100010101010111011101110101011111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(45), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(44), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(43), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(44), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(45), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~28_combout\); + +-- Location: LABCELL_X2_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~27_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(46) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(46) & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~28_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(46) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(46)) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~28_combout\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~27_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011000100010000001100010001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(46), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~27_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(46), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~28_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~29_combout\); + +-- Location: LABCELL_X1_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~25_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~7_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~29_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~7_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~25_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~30_combout\); + +-- Location: LABCELL_X1_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~57_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(22) & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~56_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(23))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(22) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~56_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23) $ (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(23))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000000010000010000000001000000100000000010000010000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~56_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~57_combout\); + +-- Location: LABCELL_X2_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(21) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(21) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000001010000101000000101000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[21]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~45_combout\); + +-- Location: LABCELL_X2_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(18) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(17)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(17)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~46_combout\); + +-- Location: LABCELL_X2_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~46_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~45_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[19]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(19)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000110000110000000011000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~45_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~46_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~47_combout\); + +-- Location: LABCELL_X2_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~48_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(15) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(16) & (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(15) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001000000001001100100000000100110010000000010011001000000001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~48_combout\); + +-- Location: LABCELL_X2_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(16) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010011010100110101001101010011010100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~52_combout\); + +-- Location: LABCELL_X2_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(21) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(20)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000000000000000011111111111111110000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[21]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~49_combout\); + +-- Location: LABCELL_X2_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(18) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(18)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(18) & ((\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(17)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(18)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(18) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(18) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(17))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110011001111000011001100111100001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~50_combout\); + +-- Location: LABCELL_X2_Y28_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~50_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~49_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~45_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(19) & !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[19]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~50_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~49_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[19]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~45_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(19)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011010000111100001101000011110000010000001111000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~49_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~45_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~50_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~51_combout\); + +-- Location: LABCELL_X2_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(11)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(11)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000001010000101000000101000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~37_combout\); + +-- Location: LABCELL_X2_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000110000110000000011000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[14]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36_combout\); + +-- Location: LABCELL_X2_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~37_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(12) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~37_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(12) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~36_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~38_combout\); + +-- Location: LABCELL_X6_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(8) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(8) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000001010101000000000101001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~39_combout\); + +-- Location: LABCELL_X1_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7)) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100110000000100110111111100110100001100000000001100111111001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~34_combout\); + +-- Location: LABCELL_X1_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5) $ (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7) & (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000010000000000000000001000010000100001000000000000000000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~31_combout\); + +-- Location: FF_X2_Y32_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]_OTERM1711\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]~DUPLICATE_q\); + +-- Location: LABCELL_X2_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(1))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(1)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000011111111010100001111111100000000010100000000000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~32_combout\); + +-- Location: LABCELL_X2_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~32_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(3) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~32_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~32_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(3))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~32_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000011111111000000000011000011110011111111110000000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~33_combout\); + +-- Location: LABCELL_X1_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~34_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~31_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~34_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~31_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(4)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~34_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~31_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~33_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~34_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010100010101000101010001010100010101000100010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~34_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~31_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~35_combout\); + +-- Location: LABCELL_X6_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(9)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(8))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8) & (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(9) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(8))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000000000000001100000011110000111111001111000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~43_combout\); + +-- Location: LABCELL_X2_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(13) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(13) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111100000101010111110000010100001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~40_combout\); + +-- Location: LABCELL_X2_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10) & (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(11) & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(11) & !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000011001111000011001100111100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~41_combout\); + +-- Location: LABCELL_X2_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~40_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(12)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~41_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~40_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~40_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(12) & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~41_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~40_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010100000001000000010101010101010101010100010101000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~40_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~41_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~36_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~42_combout\); + +-- Location: LABCELL_X2_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~43_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~42_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~38_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~43_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~42_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~38_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~39_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~35_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111100111111111100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~38_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~39_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~35_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~43_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~42_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~44_combout\); + +-- Location: LABCELL_X2_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~51_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~44_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~47_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~52_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~51_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~44_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~47_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~48_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~52_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111010101110101000000000000000001111101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~47_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~52_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~51_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~44_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~53_combout\); + +-- Location: LABCELL_X1_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~57_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~53_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~30_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~62_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~22_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~57_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~53_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~30_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~62_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~22_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~57_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~53_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~22_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~57_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~53_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~30_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~62_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~22_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000010001100110000001100110011000000100011001100000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~62_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~22_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~57_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~53_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63_combout\); + +-- Location: LABCELL_X1_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~4_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~13_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divResult\(24)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(24) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000010111111110000001011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~63_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~27_combout\); + +-- Location: FF_X1_Y33_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~27_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(24)); + +-- Location: LABCELL_X1_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9017\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9017_BDD9018\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|divResult\(24))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|divResult\(24)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101111111011111110111111101111111011001100111111101100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9017_BDD9018\); + +-- Location: LABCELL_X5_Y23_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9019\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9019_BDD9020\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~719_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\) # (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~719_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~719_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~719_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111101110111011101111110000111100001011000010110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~719_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9019_BDD9020\); + +-- Location: MLABCELL_X13_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9019_BDD9020\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9017_BDD9018\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9019_BDD9020\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9017_BDD9018\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110000001100000011001000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_RESYN9017_BDD9018\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_RESYN9019_BDD9020\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_combout\); + +-- Location: LABCELL_X16_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8665\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8665_BDD8666\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111100111111001101100110011001100110001001100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8665_BDD8666\); + +-- Location: LABCELL_X16_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8663\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8663_BDD8664\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~120_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~120_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~120_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110101011111111111010101111111111101010111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~120_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8663_BDD8664\); + +-- Location: LABCELL_X16_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8663_BDD8664\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8665_BDD8666\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8663_BDD8664\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8665_BDD8666\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010100010101000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_RESYN8665_BDD8666\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_RESYN8663_BDD8664\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_combout\); + +-- Location: LABCELL_X16_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000110000001111111011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~7_combout\); + +-- Location: MLABCELL_X13_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8659\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8659_BDD8660\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111011111110111111111111000000001110111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~40_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8659_BDD8660\); + +-- Location: LABCELL_X17_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ +-- & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001010010101000101111001000000111010101111010011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~46_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~47_combout\); + +-- Location: LABCELL_X17_Y18_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8657\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8657_BDD8658\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~41_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~47_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~41_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101000001010111110100000101011001000110010001100100011001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~41_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~47_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8657_BDD8658\); + +-- Location: LABCELL_X16_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8661\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8661_BDD8662\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8657_BDD8658\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8657_BDD8658\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8657_BDD8658\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8657_BDD8658\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111100101111111011111111111111111111001011111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8657_BDD8658\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8661_BDD8662\); + +-- Location: LABCELL_X16_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8659_BDD8660\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8661_BDD8662\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)))) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001110111011010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8659_BDD8660\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8661_BDD8662\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_combout\); + +-- Location: LABCELL_X16_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9021\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9021_BDD9022\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~109_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~109_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~109_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add34~109_sumout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~109_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~109_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000010101010000111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~109_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~109_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9021_BDD9022\); + +-- Location: LABCELL_X21_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~5_RESYN8715\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~5_RESYN8715_BDD8716\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011100010111000101111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~5_RESYN8715_BDD8716\); + +-- Location: LABCELL_X20_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9023\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9023_BDD9024\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~5_RESYN8715_BDD8716\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~5_RESYN8715_BDD8716\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111111110000111100001111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~5_RESYN8715_BDD8716\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9023_BDD9024\); + +-- Location: LABCELL_X16_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9021_BDD9022\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9023_BDD9024\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_combout\) +-- # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9021_BDD9022\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9023_BDD9024\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9021_BDD9022\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9023_BDD9024\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9021_BDD9022\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9023_BDD9024\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector981~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101011111010101010101111101110101010111110111010101011111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~3_RESYN9021_BDD9022\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~3_RESYN9023_BDD9024\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_combout\); + +-- Location: FF_X16_Y23_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(24)); + +-- Location: FF_X19_Y14_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~109_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(24)); + +-- Location: LABCELL_X19_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(24)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(24) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(24) & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\); + +-- Location: LABCELL_X19_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~161\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~161_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ & +-- ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000111101011111000011111010111100111111011111110011111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~161_combout\); + +-- Location: MLABCELL_X23_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12554\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12554_BDD12555\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~105_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~105_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~105_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111110101111111011111010111111101111101011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~105_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12554_BDD12555\); + +-- Location: LABCELL_X19_Y22_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9077_RESYN9359\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9077_RESYN9359_BDD9360\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~116_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~116_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111011111110111111101111111011111110000000001111111000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~116_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9077_RESYN9359_BDD9360\); + +-- Location: LABCELL_X14_Y19_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_RESYN12602\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010111111110000000001010101101010100101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~45_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\); + +-- Location: LABCELL_X14_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_BDD9356\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111100001111111011111110111101010000000000001110000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~38_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_BDD9356\); + +-- Location: LABCELL_X14_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9357\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9357_BDD9358\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111110101111101011111010000010100000101011111010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9357_BDD9358\); + +-- Location: LABCELL_X14_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_BDD9076\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_BDD9356\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9357_BDD9358\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_BDD9356\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~9_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100010101010101010100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9355_BDD9356\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9357_BDD9358\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_BDD9076\); + +-- Location: LABCELL_X14_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12556\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12556_BDD12557\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_BDD9076\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_BDD9076\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_BDD9076\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111001111110000000000000000001111110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_BDD9076\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12556_BDD12557\); + +-- Location: MLABCELL_X23_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~151\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12556_BDD12557\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~161_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12554_BDD12555\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9077_RESYN9359_BDD9360\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12556_BDD12557\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~161_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12554_BDD12555\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9077_RESYN9359_BDD9360\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000010000000000000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~161_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN12554_BDD12555\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9077_RESYN9359_BDD9360\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN12556_BDD12557\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_combout\); + +-- Location: MLABCELL_X23_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351_BDD9352\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~4_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~4_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000011000001010000001111110101111100111111010111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351_BDD9352\); + +-- Location: MLABCELL_X23_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_BDD9016\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351_BDD9352\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351_BDD9352\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351_BDD9352\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351_BDD9352\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351_BDD9352\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001001110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_RESYN9015_RESYN9351_BDD9352\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_BDD9016\); + +-- Location: MLABCELL_X23_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~101\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_BDD9016\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_BDD9016\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000110110001101100000000111111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_RESYN9015_BDD9016\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_combout\); + +-- Location: MLABCELL_X23_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~152\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~152_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~152_combout\); + +-- Location: MLABCELL_X23_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12542\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12542_BDD12543\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010001000000000000000000010100000100000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12542_BDD12543\); + +-- Location: MLABCELL_X13_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_RESYN13472\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011101110101010101010101000001010101010100000101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\); + +-- Location: MLABCELL_X13_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_BDD12545\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010000000000000000011111111101010101111110110101000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_BDD12545\); + +-- Location: FF_X2_Y34_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_NEW_REG897\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~26_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM898\); + +-- Location: LABCELL_X2_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM898\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM898\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM900\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM898\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM900\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM898\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM902\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~26_combout\); + +-- Location: LABCELL_X7_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12780\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12780_BDD12781\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~715_sumout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~715_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~715_sumout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~715_sumout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010001000000010101010100000101010100010000000101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~715_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12780_BDD12781\); + +-- Location: MLABCELL_X23_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12782\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12782_BDD12783\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12780_BDD12781\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12780_BDD12781\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12780_BDD12781\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12780_BDD12781\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000101000011111010111100001111000000010000111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_RESYN12780_BDD12781\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12782_BDD12783\); + +-- Location: MLABCELL_X23_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~108\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12782_BDD12783\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) # +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12542_BDD12543\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_BDD12545\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12782_BDD12783\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12782_BDD12783\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12542_BDD12543\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_BDD12545\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12782_BDD12783\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000010111011101110111011101110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12542_BDD12543\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12544_BDD12545\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_RESYN12782_BDD12783\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_combout\); + +-- Location: MLABCELL_X23_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~109\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~109_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~152_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~152_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~152_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add34~105_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~152_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000000000111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~105_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~152_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~109_combout\); + +-- Location: FF_X23_Y24_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~109_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(25)); + +-- Location: FF_X19_Y14_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~105_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y14_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(25) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(25) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[25]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\); + +-- Location: FF_X16_Y16_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[25]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(25)); + +-- Location: LABCELL_X16_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(25) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(25) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(25), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\); + +-- Location: LABCELL_X7_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[25]_NEW2763\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[25]_OTERM2764\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(25) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[25]_OTERM2764\); + +-- Location: FF_X7_Y20_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[25]_OTERM2764\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(25)); + +-- Location: LABCELL_X7_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[25]_NEW2699\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[25]_OTERM2700\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(25) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[25]_OTERM2700\); + +-- Location: FF_X7_Y20_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[25]_OTERM2700\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(25)); + +-- Location: LABCELL_X7_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[25]_NEW2891\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[25]_OTERM2892\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(25) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[25]_OTERM2892\); + +-- Location: FF_X7_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[25]_OTERM2892\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(25)); + +-- Location: LABCELL_X7_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]_NEW2827\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]_OTERM2828\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(25) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]_OTERM2828\); + +-- Location: FF_X7_Y20_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]_OTERM2828\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(25)); + +-- Location: LABCELL_X7_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux17~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(25) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(25) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(25) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(25) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(25), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(25), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~1_combout\); + +-- Location: LABCELL_X12_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[25]_NEW3147\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[25]_OTERM3148\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(25) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[25]_OTERM3148\); + +-- Location: FF_X12_Y23_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[25]_OTERM3148\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(25)); + +-- Location: LABCELL_X12_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[25]_NEW3019\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[25]_OTERM3020\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(25) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[25]_OTERM3020\); + +-- Location: FF_X12_Y23_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[25]_OTERM3020\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(25)); + +-- Location: LABCELL_X12_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[25]_NEW3083\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[25]_OTERM3084\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(25) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[25]_OTERM3084\); + +-- Location: FF_X12_Y23_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[25]_OTERM3084\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(25)); + +-- Location: LABCELL_X12_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[25]_NEW2955\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[25]_OTERM2956\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(25) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000001011011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[25]_OTERM2956\); + +-- Location: FF_X12_Y23_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[25]_OTERM2956\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(25)); + +-- Location: LABCELL_X12_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux17~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(25)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(25) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(25)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(25))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(25)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(25), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~0_combout\); + +-- Location: MLABCELL_X13_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2_combout\); + +-- Location: LABCELL_X10_Y14_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[25]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[25]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101001101110000010100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[25]~20_combout\); + +-- Location: FF_X10_Y14_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[25]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25)); + +-- Location: MLABCELL_X18_Y9_N51 +\myVirtualToplevel|SD_ADDR[0][25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(25), + combout => \myVirtualToplevel|SD_ADDR[0][25]~feeder_combout\); + +-- Location: FF_X18_Y9_N52 +\myVirtualToplevel|SD_ADDR[0][25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][25]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][25]~q\); + +-- Location: FF_X21_Y9_N16 +\myVirtualToplevel|IO_DATA_READ_SD[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[25]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][25]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(25)); + +-- Location: LABCELL_X21_Y14_N6 +\myVirtualToplevel|MEM_DATA_READ[25]~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[25]~52_combout\ = ( \myVirtualToplevel|IO_DATA_READ_SD\(25) & ( \myVirtualToplevel|MEM_DATA_READ[17]~25_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~25_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(25), + combout => \myVirtualToplevel|MEM_DATA_READ[25]~52_combout\); + +-- Location: MLABCELL_X9_Y14_N33 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[1]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[1]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(9))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(9)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(9))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(9)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001011010111110101111101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(25), + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[1]~4_combout\); + +-- Location: M10K_X3_Y17_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020B644FBD60A589090134380828E65C9CC8A482200000002080EC595002026AF946419A2BA3C400E1C4B8AA05405A000D4002200000004010BEF82301A0D40200A0184A15A20358009008102000810FE980000000E53F913D0842EEDC28529264A31D99EACB8525020A71432E", + mem_init2 => "CB805C9047C01C4010A5403C5A50E406C38464A46A64F05622819F0460008B84EAF5EAA60FC271FC49AEBE75D8327701F41B3212A472482A0B01186D11A57A1D9AAA428D55074D56AA83A6AB5A943C22459C921605DFE1830870768C5D3892951C890CC92002040460452076A9B3432DD767C5E32CB3B6F2AFAA7B487705C6F364D82DACA80A1200D08060A2A58125A581179460C244A528347B88C00172B0AA0B014787D9041AC2674221CC766D0CD71571E39ECF0491400A20E821003C75B2892A32000C04826885AD839A002EB30EAA1492EC2412CCADD30828B02287750762041040982484052032A051828A3CC2CF90602F1E00538070890CD53D5F2083", + mem_init1 => "482DC845E1DE4E103150A368C520750120CFDE01287B7059744A51D0B9481838015109C2C10901841D431E161DE38D6C0030424244A060253856688C6B6602A61D801701D2A722024DE1CB3129B1406D8760F82D063050009A28DD41100700B0F6A028B51AC0FD82E721DA3DA34147820408D3D44692F2C02701E400478B094B29E355B5F001F3D22E187FC322B210D1230423E09600948BBF3B8DC3E02272B4215053A14410E088A277B004CDCF2F4093B3024E1030C31947AC5C6222828559E3911982E01C0698189D8AE628890063AC0A4081180C10CE01303748C291DD1850F9424889562861CE831719CC433559CA2BA39F018E4206CA2E2A504860D140", + mem_init0 => "793428A7B16B37E01097A208B5A7F136647A4E002204271DC78254B1C6EAD89026CD00921222780E205D4721322C38B33493AB512E486570D78D01110E214B8520504315C8A64A130CA74192003023191CE1244920717044098303061C387A34514BE8432E610865CC210E8650984C261224807AC9A02B404193D8E40868601A0A0413BFD04212394AAA736D9B3048620060AE204B20134F59067BBA0A80088018000400481612800040000802100480080C100A6918A600214006C0000000000000000000000000005800A003400280FFFFFFFFFFFFBEDB6DB6DB6FBEFBEDFEFC0001000000005151040432020701021B0B1C13050301000318033BF61A0001", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 1, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 1, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\); + +-- Location: M10K_X3_Y14_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 1, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 1, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X17_Y10_N51 +\myVirtualToplevel|IO_DATA_READ~83\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~83_combout\ = ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(25) & ( \myVirtualToplevel|IO_DATA_READ[26]~78_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[26]~78_combout\, + dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(25), + combout => \myVirtualToplevel|IO_DATA_READ~83_combout\); + +-- Location: FF_X17_Y10_N52 +\myVirtualToplevel|IO_DATA_READ[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~83_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(25)); + +-- Location: FF_X18_Y14_N50 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_NEW_REG26\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM27\); + +-- Location: IOIBUF_X23_Y0_N58 +\SDRAM_DQ[9]~input\ : cyclonev_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => SDRAM_DQ(9), + o => \SDRAM_DQ[9]~input_o\); + +-- Location: DDIOINCELL_X23_Y0_N71 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_NEW_REG28\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \SDRAM_DQ[9]~input_o\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM29\); + +-- Location: MLABCELL_X18_Y14_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM29\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM27\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM29\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM27\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111101000000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]_OTERM27\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]_OTERM29\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30_combout\); + +-- Location: MLABCELL_X18_Y14_N15 +\myVirtualToplevel|MEM_DATA_READ[25]~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[25]~51_combout\ = ( \myVirtualToplevel|IO_DATA_READ\(25) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\) # (\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ\(25) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\))) # (\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & +-- (\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\)))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ\(25) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\))) # (\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & (\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|IO_DATA_READ\(25) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30_combout\ & ( (\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\ & (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[27]~21_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000001100000101000011000000010100001111000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~20_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~23_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~21_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(25), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]~30_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[25]~51_combout\); + +-- Location: MLABCELL_X18_Y14_N9 +\myVirtualToplevel|MEM_DATA_READ[25]~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9~portbdataout\ & ( \myVirtualToplevel|MEM_DATA_READ[25]~51_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9~portbdataout\ & ( \myVirtualToplevel|MEM_DATA_READ[25]~51_combout\ ) ) # ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9~portbdataout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[25]~51_combout\ & ( ((\myVirtualToplevel|LessThan0~1_combout\ & ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1~portbdataout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0))))) # (\myVirtualToplevel|MEM_DATA_READ[25]~52_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9~portbdataout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[25]~51_combout\ & ( ((!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0) & (\myVirtualToplevel|LessThan0~1_combout\ & +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1~portbdataout\))) # (\myVirtualToplevel|MEM_DATA_READ[25]~52_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100111011001101110011111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~52_combout\, + datac => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\, + datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~51_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\); + +-- Location: LABCELL_X20_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector349~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector349~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~57_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[9]~123_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & (\myVirtualToplevel|MEM_DATA_READ[25]~53_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add7~57_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[9]~123_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & +-- (\myVirtualToplevel|MEM_DATA_READ[25]~53_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000000101000101001010111110111110101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~1_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~53_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector349~0_combout\); + +-- Location: FF_X20_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector349~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[9]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y16_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[9]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(9) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[9]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111111111111111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\); + +-- Location: FF_X20_Y18_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(9)); + +-- Location: FF_X19_Y16_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(9)); + +-- Location: LABCELL_X20_Y18_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(9)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(9)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\); + +-- Location: LABCELL_X6_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[9]_NEW3051\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[9]_OTERM3052\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(9) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[9]_OTERM3052\); + +-- Location: FF_X6_Y23_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[9]_OTERM3052\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(9)); + +-- Location: LABCELL_X6_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[9]_NEW3179\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[9]_OTERM3180\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(9))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[9]_OTERM3180\); + +-- Location: FF_X6_Y23_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[9]_OTERM3180\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(9)); + +-- Location: LABCELL_X6_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[9]_NEW3115\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[9]_OTERM3116\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(9) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[9]_OTERM3116\); + +-- Location: FF_X6_Y23_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[9]_OTERM3116\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(9)); + +-- Location: LABCELL_X6_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[9]_NEW2987\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[9]_OTERM2988\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[9]_OTERM2988\); + +-- Location: FF_X6_Y21_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[9]_OTERM2988\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(9)); + +-- Location: LABCELL_X6_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux96~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(9)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(9))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(9) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(9))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101000011110000000000110011010101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~0_combout\); + +-- Location: LABCELL_X6_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[9]_NEW2731\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[9]_OTERM2732\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101000000111111010111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[9]_OTERM2732\); + +-- Location: FF_X6_Y21_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[9]_OTERM2732\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(9)); + +-- Location: LABCELL_X10_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[9]_NEW2859\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[9]_OTERM2860\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(9) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[9]_OTERM2860\); + +-- Location: FF_X10_Y21_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[9]_OTERM2860\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(9)); + +-- Location: LABCELL_X10_Y21_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[9]_NEW2795\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[9]_OTERM2796\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(9) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[9]_OTERM2796\); + +-- Location: FF_X10_Y21_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[9]_OTERM2796\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(9)); + +-- Location: LABCELL_X6_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[9]_NEW2923\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[9]_OTERM2924\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[9]_OTERM2924\); + +-- Location: FF_X6_Y21_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[9]_OTERM2924\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(9)); + +-- Location: LABCELL_X6_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux96~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(9)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(9)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(9)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(9) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101001100000011111111110101111101010011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~1_combout\); + +-- Location: LABCELL_X7_Y16_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux96~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux96~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux96~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010110101010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~2_combout\); + +-- Location: MLABCELL_X9_Y14_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~feeder_combout\); + +-- Location: FF_X9_Y14_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\); + +-- Location: FF_X16_Y10_N55 +\myVirtualToplevel|SD_ADDR[0][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][9]~q\); + +-- Location: LABCELL_X16_Y10_N15 +\myVirtualToplevel|Mux74~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux74~1_combout\ = ( \myVirtualToplevel|Mux74~0_combout\ & ( \myVirtualToplevel|SD_ADDR[0][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # ( +-- !\myVirtualToplevel|Mux74~0_combout\ & ( \myVirtualToplevel|SD_ADDR[0][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) $ (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # ( !\myVirtualToplevel|Mux74~0_combout\ & ( +-- !\myVirtualToplevel|SD_ADDR[0][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000000000000000010100101101001011010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ALT_INV_Mux74~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_SD_ADDR[0][9]~q\, + combout => \myVirtualToplevel|Mux74~1_combout\); + +-- Location: FF_X16_Y10_N16 +\myVirtualToplevel|IO_DATA_READ_SD[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux74~1_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(9)); + +-- Location: MLABCELL_X9_Y14_N9 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[1]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[1]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(9))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(9) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000001011010111100001111000011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[1]~4_combout\); + +-- Location: M10K_X11_Y13_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 1, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 1, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X17_Y8_N33 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~1_combout\ = ( \myVirtualToplevel|UART0|TX_INTR~q\ & ( ((\myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ & \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(9))) # (\myVirtualToplevel|INT_ENABLE\(9)) ) ) # +-- ( !\myVirtualToplevel|UART0|TX_INTR~q\ & ( (\myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ & \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(9)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100001111010111110000111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\, + datac => \myVirtualToplevel|ALT_INV_INT_ENABLE\(9), + datad => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(9), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_INTR~q\, + combout => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~1_combout\); + +-- Location: FF_X17_Y8_N35 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|pending[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~1_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(9)); + +-- Location: LABCELL_X14_Y11_N15 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|status[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[9]~feeder_combout\ = ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(9) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(9), + combout => \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[9]~feeder_combout\); + +-- Location: FF_X14_Y11_N16 +\myVirtualToplevel|INTRCTL:INTCONTROLLER|status[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[9]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(9)); + +-- Location: LABCELL_X14_Y11_N27 +\myVirtualToplevel|IO_DATA_READ_INTRCTL~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_INTRCTL~2_combout\ = ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|INT_ENABLE\(9)) ) ) # ( +-- !\myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|INT_ENABLE\(9)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ALT_INV_INT_ENABLE\(9), + dataf => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(9), + combout => \myVirtualToplevel|IO_DATA_READ_INTRCTL~2_combout\); + +-- Location: FF_X14_Y11_N28 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_INTRCTL~2_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(9)); + +-- Location: MLABCELL_X9_Y12_N12 +\myVirtualToplevel|IO_DATA_READ[9]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[9]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|RTC_YEAR_COUNTER\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) +-- & ( \myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|RTC_MICROSEC_COUNTER\(9))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\ & ( (\myVirtualToplevel|RTC_YEAR_COUNTER\(9) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|RTC_MICROSEC_COUNTER\(9))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000000000000010000000100000000110000001100000111000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\, + combout => \myVirtualToplevel|IO_DATA_READ[9]~40_combout\); + +-- Location: FF_X14_Y12_N28 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~33_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(9)); + +-- Location: LABCELL_X16_Y12_N45 +\myVirtualToplevel|Mux263~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux263~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|SECOND_DOWN_COUNTER\(9) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(9) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(9) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(9) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(9), + datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(9), + datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(9), + datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|Mux263~0_combout\); + +-- Location: LABCELL_X16_Y11_N18 +\myVirtualToplevel|IO_DATA_READ[9]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[9]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ( \myVirtualToplevel|Mux263~0_combout\ & ( (\myVirtualToplevel|IO_DATA_READ[9]~40_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & +-- \myVirtualToplevel|TIMER0_CS~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ( \myVirtualToplevel|Mux263~0_combout\ & ( (\myVirtualToplevel|TIMER0_CS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)) # +-- (\myVirtualToplevel|IO_DATA_READ[9]~40_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|Mux263~0_combout\ & ( (\myVirtualToplevel|IO_DATA_READ[9]~40_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & \myVirtualToplevel|TIMER0_CS~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|Mux263~0_combout\ & ( (\myVirtualToplevel|IO_DATA_READ[9]~40_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & \myVirtualToplevel|TIMER0_CS~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011000000000000001100000000111100110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ[9]~40_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_Mux263~0_combout\, + combout => \myVirtualToplevel|IO_DATA_READ[9]~41_combout\); + +-- Location: FF_X16_Y11_N19 +\myVirtualToplevel|IO_DATA_READ[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ[9]~41_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(9)); + +-- Location: FF_X18_Y11_N23 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux91~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(9)); + +-- Location: MLABCELL_X18_Y11_N21 +\myVirtualToplevel|MEM_DATA_READ[9]~80_RESYN8729\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[9]~80_RESYN8729_BDD8730\ = ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(9) & ( \myVirtualToplevel|SOCCFG_CS~combout\ ) ) # ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(9) & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( +-- \myVirtualToplevel|IO_DATA_READ\(9) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(9) & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(9) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(9), + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(9), + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[9]~80_RESYN8729_BDD8730\); + +-- Location: MLABCELL_X18_Y13_N0 +\myVirtualToplevel|MEM_DATA_READ[9]~80\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[9]~80_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[9]~80_RESYN8729_BDD8730\ & ( +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[9]~80_RESYN8729_BDD8730\ & ( +-- (!\myVirtualToplevel|INTR0_CS~combout\) # ((!\myVirtualToplevel|IO_SELECT~combout\) # (\myVirtualToplevel|IO_DATA_READ_INTRCTL\(9))) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[9]~80_RESYN8729_BDD8730\ & +-- ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[9]~80_RESYN8729_BDD8730\ & ( +-- (!\myVirtualToplevel|IO_SELECT~combout\) # ((\myVirtualToplevel|INTR0_CS~combout\ & \myVirtualToplevel|IO_DATA_READ_INTRCTL\(9))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110101001100110011001111111010111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(9), + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~80_RESYN8729_BDD8730\, + combout => \myVirtualToplevel|MEM_DATA_READ[9]~80_combout\); + +-- Location: FF_X18_Y13_N5 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]_NEW_REG52\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]~18_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]_OTERM53\); + +-- Location: LABCELL_X19_Y13_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]~18_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM29\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]_OTERM53\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM29\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]_OTERM53\ ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM29\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]_OTERM53\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM29\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]_OTERM53\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100000011000000110011001100110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[9]_OTERM53\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]_OTERM29\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]~18_combout\); + +-- Location: M10K_X3_Y13_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111331111111111333110001153EE091908462249ACBC492008A0D100210A00525DFF7FFF891A22590880303DB2D8AE206A5C39AA88424310B67550150154119FFFFFFB420420AD801980701A0010905017304A1BC303020408D0A04491D3FFFFFFB756AA4217F1400778F31C4783B042042C521CB05421BB41", + mem_init2 => "0067C271C020056072A980E562E3085D0E5633956C3395244E2700C0148F805C14683C1DD8A94318D12B070AC5147CA021950506C5C2D8103F9D013DF0E92D42E808E5960954AA8304AA55118666920C071100090AA8429502D8D465386FC7203ACE8A924800002B13081482B6A667115F825445F91633AEDD970EB357A16EE9A751D6F2819223451281C868BF1DB23F1DAF74663931B64793E503C007201E5AB8DD1724D131D802DE8A8C84283A284AE6C2510912627971E7888933281047120B08272197046FA0A6B92DC01BC06328134CA767CC1428010A6E0204218984E628900438E05A019F1BDC1420C72AF2921055854441A48E1445944C24206D8CE6", + mem_init1 => "1145C008301582C42141D5C455ED2A294CC4A4008D408664035253423E548A03910C812D608B19E080FA82AD3284BC81204D87A949CF6042E3E521E5A40460B436196010E0406F982F30640715252351100CA00CE3213F0109C182A42080583633999A94B6300B18D1815507C405EA97DEDA3AB5BE351F60641B03A76EDA1883E6199908004C2D08996EC5D36DB007E430211A23200939704A008D902164F696060800A00D108C8D164412C29D8D6B0A660437044097060A2EA40CC0288430E0EA163A77D08C91C01430200CFA054CCA92E01E0907C55CA05F9ACB80CA02EC9D29E4C314008131D5B3D42031487CC300CC613C001E0BC140F3088201588490D3", + mem_init0 => "0F8121AEEC84464B55809C18403325B63199A11B029622A1026CD009212227823C12A58E3756C48C192947002A24921694E578C70A380092AA3604A0AF1ACA2442EECC02B04C282447892440004D213C40119648127030212024489122440043374517CC210CF98421DF30812984C2610800A9513A16960D05028C5DEE85FC484196EE39B18843020414A6B37223A200FF459842E87EB0323099018C401600020240530440000A8114340B081110202284840A8A040F0E00000160004040400044040400444400042800D001B0016006FFFFFFFFFFFF7DB6DB6DB6DBEFBEFBFFFA00000000000026161414151701020000081B1B050101000358020A631F0001", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 1, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 1, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X18_Y13_N39 +\myVirtualToplevel|MEM_DATA_READ[9]~123\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[9]~80_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1~portbdataout\ & +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(9))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]~18_combout\)))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[9]~80_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9~portbdataout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(9))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]~18_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001000100001100110111010000110000010001001111111101110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(9), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~80_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[9]~18_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\); + +-- Location: LABCELL_X17_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector357~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~65_Duplicate_152\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~0_combout\); + +-- Location: LABCELL_X17_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector357~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[17]~27_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector357~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\ & ((((\myVirtualToplevel|MEM_DATA_READ[25]~53_combout\))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ & (((\myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ & (((\myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[17]~27_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector357~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001000100001111000100010001111111111111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~5_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~27_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector357~0_combout\, + datag => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~53_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~1_combout\); + +-- Location: FF_X17_Y16_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~1_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~93_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y37_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_36\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_36\); + +-- Location: FF_X19_Y37_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_NEW_REG1484\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_36\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\); + +-- Location: FF_X19_Y39_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]_NEW_REG1584\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~53_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]_OTERM1585\); + +-- Location: LABCELL_X19_Y35_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000000000000000010100000000000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\); + +-- Location: LABCELL_X19_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\); + +-- Location: LABCELL_X19_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000000110000001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~60_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\); + +-- Location: MLABCELL_X18_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100000000000100010011000000110001001100000011000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~62_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~61_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~60_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~52_combout\); + +-- Location: FF_X18_Y35_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_NEW_REG1552\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~52_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1553\); + +-- Location: LABCELL_X19_Y39_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]_OTERM1585\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1553\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]_OTERM1585\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1553\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]_OTERM1585\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1553\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1431\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1435\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1485\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[1]_OTERM1585\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]_OTERM1553\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~53_combout\); + +-- Location: FF_X19_Y39_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]_NEW_REG1586\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~55_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]_OTERM1587\); + +-- Location: LABCELL_X19_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~54_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000111011000010100011101100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~60_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~62_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~61_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~54_combout\); + +-- Location: FF_X19_Y35_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_NEW_REG1556\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~54_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1557\); + +-- Location: LABCELL_X19_Y39_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]_OTERM1587\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1557\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]_OTERM1587\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1557\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]_OTERM1587\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1557\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1431\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1485\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1435\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[1]_OTERM1587\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]_OTERM1557\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~55_combout\); + +-- Location: FF_X19_Y39_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_NEW_REG1482\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~57_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1483\); + +-- Location: LABCELL_X19_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110010001000100011001000100010001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~60_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~61_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~62_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~56_combout\); + +-- Location: FF_X19_Y35_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1436\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~56_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1437\); + +-- Location: LABCELL_X19_Y39_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~57_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1483\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1437\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1483\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1437\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1483\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1437\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1431\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1485\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1435\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1483\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1437\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~57_combout\); + +-- Location: FF_X19_Y39_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]_NEW_REG1534\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]~64_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]_OTERM1535\); + +-- Location: LABCELL_X19_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~63\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~63_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110010001000100011001000100010001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~60_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~61_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~62_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~63_combout\); + +-- Location: FF_X19_Y35_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_NEW_REG1480\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~63_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1481\); + +-- Location: LABCELL_X19_Y39_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]~64\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]~64_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]_OTERM1535\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1481\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]_OTERM1535\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1481\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]_OTERM1535\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1481\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1431\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1435\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1485\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[1]_OTERM1535\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]_OTERM1481\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]~64_combout\); + +-- Location: LABCELL_X19_Y39_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]~64_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~57_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~55_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]~64_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~53_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]~64_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~57_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~55_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]~64_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~53_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000011110011001111111111010101010000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[1]~53_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[1]~55_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~57_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[1]~64_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~1_combout\); + +-- Location: LABCELL_X19_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110010001000100011001000100010001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~60_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~61_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~62_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~51_combout\); + +-- Location: LABCELL_X20_Y39_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~51_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~51_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~51_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[1]~51_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~52_combout\); + +-- Location: FF_X20_Y39_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~52_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(1)); + +-- Location: LABCELL_X19_Y35_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~54_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001110101011000000111010101100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~60_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~62_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~61_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~54_combout\); + +-- Location: LABCELL_X20_Y39_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[1]~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[1]~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~54_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~54_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~54_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[0]~54_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[1]~55_combout\); + +-- Location: FF_X20_Y39_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[1]~55_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(1)); + +-- Location: LABCELL_X20_Y39_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~57_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56_combout\ & ( \myVirtualToplevel|RESET_n~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]~56_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~57_combout\); + +-- Location: FF_X20_Y39_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_NEW_REG1546\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~57_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1547\); + +-- Location: MLABCELL_X18_Y35_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100000001000000010011001100000001001100110000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~62_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~61_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~60_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~55_combout\); + +-- Location: FF_X18_Y35_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_NEW_REG1606\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~55_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1607\); + +-- Location: FF_X19_Y39_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_NEW_REG1604\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~58_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1605\); + +-- Location: LABCELL_X19_Y39_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~58_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1547\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1605\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1547\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1607\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1605\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1607\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1605\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000001111110110000000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1547\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1485\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]_OTERM1607\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]_OTERM1605\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~58_combout\); + +-- Location: LABCELL_X19_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110010001000100011001000100010001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~60_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~61_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~62_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~56_combout\); + +-- Location: FF_X19_Y35_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_NEW_REG1548\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~56_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1549\); + +-- Location: FF_X19_Y39_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]_NEW_REG1558\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]~57_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]_OTERM1559\); + +-- Location: LABCELL_X19_Y39_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]~57_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1547\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]_OTERM1559\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1547\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1549\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]_OTERM1559\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1549\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]_OTERM1559\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000001111110110000000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1547\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1485\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1549\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[1]_OTERM1559\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]~57_combout\); + +-- Location: LABCELL_X19_Y39_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]~57_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~58_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]~57_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]~57_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~58_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]~57_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(1))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101000000001111000000110101001101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]~58_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[1]~57_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~0_combout\); + +-- Location: LABCELL_X16_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\); + +-- Location: LABCELL_X16_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011001100110000001100110011000000110000001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\); + +-- Location: LABCELL_X10_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector276~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector276~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector18~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector18~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010000001011010111101110111011101110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector18~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector276~0_combout\); + +-- Location: FF_X10_Y18_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_NEW_REG783\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector276~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM784\); + +-- Location: LABCELL_X10_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM784\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM782\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM784\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM782\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110011000000001111001100001100111111110000110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM782\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM784\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\); + +-- Location: MLABCELL_X18_Y9_N27 +\myVirtualToplevel|SD_ADDR[0][16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\, + combout => \myVirtualToplevel|SD_ADDR[0][16]~feeder_combout\); + +-- Location: FF_X18_Y9_N29 +\myVirtualToplevel|SD_ADDR[0][16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][16]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][16]~q\); + +-- Location: FF_X18_Y9_N41 +\myVirtualToplevel|IO_DATA_READ_SD[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[16]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][16]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(16)); + +-- Location: LABCELL_X20_Y11_N45 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[0]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[0]~0_combout\); + +-- Location: M10K_X38_Y13_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\); + +-- Location: M10K_X3_Y11_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002220022020202200020000EE1680627229A54885316A8C490ECE26551671CE211125294A52895A107A18003549BEB9870F2A172A84113CDCAA92345A7D1454445FFFFFFDC03187C81A2F84408E201280FC39104A185058801000000005638C000000D0C4A37AA140CAD6F9B4A6A95579265A1C3D3C325CF65301", + mem_init2 => "2CC74EF51662A3F8F9A511E3F245E43E1E3FC7CD28C7CFE6123CD98A8E8AECD219A0083D882B4751D53E0209B3F6DC782883309A242200F53ECC3B5BDD79F286DC016E4E1825E853EC13F4298C14BC2D0358238419AE5A55285BC12372E4F84A9AC9E3B6DB6E9DEBA18ACB8B35627A2304343283D1CEB8BD79644DFDBD961D078CD64D8838805F085745C599AD8230AD832390A1B0338008010052FB741F6A8D521874453CA9936AFE18A0A496CF334A28676293F1830F4AA1159A7C108CE8279FDEDEAC8D040640A604ACD8CDCDC49B8D9E3481F0E22130AB6A8830063808AC2A126701ED81328EC60C098873EAB144F107E8836D541180A4AB19C765F02120", + mem_init1 => "6B086655B4309090219D332212A780B7149569E9A77040E27058D176AACA92B9BD005BA82AC8C347503EA6BE77033688B6654E267450E262EAA9D41BAD43538010056F2402426B0A1038821324ABDFBA049F881801A798050019D119E29452100FD68A348F6EB689444B3CA5C514EA55C201FC207E800080B589C9F7CE31102E4D783F7B4B595C8901305523A03336D54206F81F6D180004C40FFC4D985B740E1B533E7364B9D34D84709A0732DC79DC0E6F10174C1707201EC02246680788048028317BC880B0423B3CB04604059DF841F131371BC035941F16C91CF03ABC3CF11618E31C9875F1C042A359D587185C0A7043961D6359F92433F6C0A0336CC4", + mem_init0 => "FA91582A2EA44A3098A0160B563D104A0851C75A401A4615DA48D5691A102E4099B282F1B55C4C68DB16A54DEEB1B3F4F7C06BC25880C6AFFE82202CA158570D9DE424F472E3AA0C2C7AB452DB5FE9265EC390FFF7BB1B6D6D9B366CD9B6DEC38D00C7440C60E8818C1D10306341A0D05341A21D8D03CC1D540EEDC6CB40A284506793FFB90002F84AAAAEDB3A333573F1563E90239E39D2138C960C4054C4528A1A502562014AD554054A0C519AA22A80A6A2AB1CB04E002223444440000440400404404040044028805110A2214402FFFFFFFFFFFDB6924DB6924DB69249FEFF00000001000177734C4C16160702011F0F1D12060201000045002BF31F0401", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X19_Y13_N57 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|l1_w0_n0_mux_dataout~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|l1_w0_n0_mux_dataout~0_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8~portbdataout\ & ( +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8~portbdataout\ & ( +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) ) ) ) # ( +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8~portbdataout\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|l1_w0_n0_mux_dataout~0_combout\); + +-- Location: FF_X17_Y14_N16 +\myVirtualToplevel|INT_ENABLE[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(16)); + +-- Location: FF_X17_Y14_N40 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INT_ENABLE\(16), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(16)); + +-- Location: FF_X14_Y12_N49 +\myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add15~1_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(16)); + +-- Location: LABCELL_X16_Y10_N24 +\myVirtualToplevel|IO_DATA_READ~116\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~116_combout\ = ( !\myVirtualToplevel|IO_DATA_READ[17]~1_combout\ & ( (((!\myVirtualToplevel|IO_DATA_READ[17]~0_combout\ & (\myVirtualToplevel|UART1|Add10~1_sumout\)) # (\myVirtualToplevel|IO_DATA_READ[17]~0_combout\ & +-- ((\myVirtualToplevel|UART0|Equal5~3_combout\))))) ) ) # ( \myVirtualToplevel|IO_DATA_READ[17]~1_combout\ & ( ((!\myVirtualToplevel|IO_DATA_READ[17]~0_combout\ & (((\myVirtualToplevel|UART1|Equal5~4_combout\)))) # +-- (\myVirtualToplevel|IO_DATA_READ[17]~0_combout\ & (!\myVirtualToplevel|TIMER0_CS~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000111100001111001100110011001100000000111111110000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + datab => \myVirtualToplevel|UART1|ALT_INV_Equal5~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|UART0|ALT_INV_Equal5~3_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~1_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~0_combout\, + datag => \myVirtualToplevel|UART1|ALT_INV_Add10~1_sumout\, + combout => \myVirtualToplevel|IO_DATA_READ~116_combout\); + +-- Location: LABCELL_X16_Y10_N42 +\myVirtualToplevel|IO_DATA_READ~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~4_combout\ = ( \myVirtualToplevel|IO_DATA_READ[17]~2_combout\ & ( \myVirtualToplevel|IO_DATA_READ~116_combout\ & ( (!\myVirtualToplevel|IO_DATA_READ[17]~3_combout\ & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(16))) # +-- (\myVirtualToplevel|IO_DATA_READ[17]~3_combout\ & ((\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(16)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ[17]~2_combout\ & ( \myVirtualToplevel|IO_DATA_READ~116_combout\ & ( +-- (!\myVirtualToplevel|IO_DATA_READ[17]~3_combout\) # (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(16)) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ[17]~2_combout\ & ( !\myVirtualToplevel|IO_DATA_READ~116_combout\ & ( +-- (!\myVirtualToplevel|IO_DATA_READ[17]~3_combout\ & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(16))) # (\myVirtualToplevel|IO_DATA_READ[17]~3_combout\ & ((\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(16)))) ) ) ) # ( +-- !\myVirtualToplevel|IO_DATA_READ[17]~2_combout\ & ( !\myVirtualToplevel|IO_DATA_READ~116_combout\ & ( (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(16) & \myVirtualToplevel|IO_DATA_READ[17]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011010100000101111111110011111100110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(16), + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(16), + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~3_combout\, + datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(16), + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~116_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~4_combout\); + +-- Location: FF_X16_Y10_N44 +\myVirtualToplevel|IO_DATA_READ[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~4_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(16)); + +-- Location: LABCELL_X20_Y11_N30 +\myVirtualToplevel|Mux89~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux89~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0110000001100000110000001100000000000000000000000010000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + combout => \myVirtualToplevel|Mux89~0_combout\); + +-- Location: FF_X18_Y12_N37 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux89~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(16)); + +-- Location: MLABCELL_X18_Y13_N18 +\myVirtualToplevel|MEM_DATA_READ[16]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[16]~0_combout\ = ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(16) & ( \myVirtualToplevel|IO_SELECT~combout\ & ( (!\myVirtualToplevel|INTR0_CS~combout\ & (((!\myVirtualToplevel|SOCCFG_CS~combout\ & +-- !\myVirtualToplevel|IO_DATA_READ\(16))))) # (\myVirtualToplevel|INTR0_CS~combout\ & (!\myVirtualToplevel|IO_DATA_READ_INTRCTL\(16))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(16) & ( \myVirtualToplevel|IO_SELECT~combout\ & ( +-- (!\myVirtualToplevel|INTR0_CS~combout\ & (((!\myVirtualToplevel|IO_DATA_READ\(16)) # (\myVirtualToplevel|SOCCFG_CS~combout\)))) # (\myVirtualToplevel|INTR0_CS~combout\ & (!\myVirtualToplevel|IO_DATA_READ_INTRCTL\(16))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111010001110101100101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(16), + datab => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + datac => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(16), + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(16), + dataf => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[16]~0_combout\); + +-- Location: FF_X19_Y13_N55 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]_NEW_REG76\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]_OTERM77\); + +-- Location: LABCELL_X19_Y13_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]_OTERM77\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]_OTERM77\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100100010001100110010001000110011011101110011001101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[16]_OTERM77\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]_OTERM11\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4_combout\); + +-- Location: LABCELL_X19_Y13_N24 +\myVirtualToplevel|MEM_DATA_READ[16]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4_combout\ & ( (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|l1_w0_n0_mux_dataout~0_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[16]~0_combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(16))) ) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4_combout\ & ( (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|l1_w0_n0_mux_dataout~0_combout\ & +-- !\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[16]~0_combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(16))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111010100000101001100000011000011110101000001010011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(16), + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|ALT_INV_l1_w0_n0_mux_dataout~0_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~0_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[16]~4_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\); + +-- Location: FF_X19_Y15_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~1_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[16]~DUPLICATE_q\); + +-- Location: FF_X19_Y15_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~1_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(16)); + +-- Location: LABCELL_X20_Y15_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(16) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(16) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(16) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\); + +-- Location: FF_X20_Y17_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(16)); + +-- Location: FF_X20_Y17_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[16]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[16]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(16)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[16]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\); + +-- Location: MLABCELL_X9_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]_NEW2911\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]_OTERM2912\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]_OTERM2912\); + +-- Location: FF_X9_Y24_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]_OTERM2912\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(16)); + +-- Location: MLABCELL_X9_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[16]_NEW2719\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[16]_OTERM2720\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[16]_OTERM2720\); + +-- Location: FF_X9_Y24_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[16]_OTERM2720\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(16)); + +-- Location: MLABCELL_X9_Y24_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[16]_NEW2847\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[16]_OTERM2848\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(16) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[16]_OTERM2848\); + +-- Location: FF_X9_Y24_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[16]_OTERM2848\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(16)); + +-- Location: LABCELL_X7_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[16]_NEW2783\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[16]_OTERM2784\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(16) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[16]_OTERM2784\); + +-- Location: FF_X7_Y23_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[16]_OTERM2784\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(16)); + +-- Location: MLABCELL_X9_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux26~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(16)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(16)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(16)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(16))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(16)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~1_combout\); + +-- Location: LABCELL_X7_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[16]_NEW3103\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[16]_OTERM3104\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[16]_OTERM3104\); + +-- Location: FF_X7_Y23_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[16]_OTERM3104\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(16)); + +-- Location: LABCELL_X7_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[16]_NEW2975\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[16]_OTERM2976\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[16]_OTERM2976\); + +-- Location: FF_X7_Y23_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[16]_OTERM2976\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(16)); + +-- Location: LABCELL_X7_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[16]_NEW3167\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[16]_OTERM3168\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[16]_OTERM3168\); + +-- Location: FF_X7_Y23_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[16]_OTERM3168\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(16)); + +-- Location: LABCELL_X7_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[16]_NEW3039\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[16]_OTERM3040\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(16) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[16]_OTERM3040\); + +-- Location: FF_X7_Y23_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[16]_OTERM3040\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(16)); + +-- Location: LABCELL_X7_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux26~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(16)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(16) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(16)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(16)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010001001110010011101010101111111110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~0_combout\); + +-- Location: LABCELL_X7_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux26~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux26~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\); + +-- Location: LABCELL_X10_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[16]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[16]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[16]~3_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[16]~3_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000100111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~2_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[16]~21_combout\); + +-- Location: FF_X10_Y18_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[16]~21_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(16)); + +-- Location: MLABCELL_X9_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[0]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(16) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(16) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100001111000000110000111111001111000011111100111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[0]~1_combout\); + +-- Location: LABCELL_X25_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~296\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~296_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~296_combout\); + +-- Location: FF_X25_Y32_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~296_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\); + +-- Location: LABCELL_X26_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\); + +-- Location: LABCELL_X31_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux177~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~1_combout\); + +-- Location: LABCELL_X31_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux177~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~3_combout\); + +-- Location: LABCELL_X32_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux177~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000100010001000100000101101011111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~0_combout\); + +-- Location: LABCELL_X32_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux177~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011000000000000111101010011010100111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~2_combout\); + +-- Location: LABCELL_X32_Y36_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux177~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux177~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux177~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux177~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux177~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux177~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux177~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux177~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000010100110101001100001111111111110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~4_combout\); + +-- Location: LABCELL_X19_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~0_combout\); + +-- Location: MLABCELL_X18_Y22_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~10_combout\); + +-- Location: MLABCELL_X13_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001100110001000100010001000100010011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~9_combout\); + +-- Location: LABCELL_X21_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~87\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~87_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000000000000001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~87_combout\); + +-- Location: LABCELL_X21_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~106\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~106_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~106_combout\); + +-- Location: MLABCELL_X18_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~103_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~87_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~106_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~103_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~106_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~87_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~106_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~106_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000110011001100000010101010101000001000100010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~103_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~87_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~106_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~11_combout\); + +-- Location: MLABCELL_X18_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~9_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~9_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010100000000000000000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~12_combout\); + +-- Location: FF_X2_Y33_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[1]_NEW_REG1222\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~23_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[1]_OTERM1223\); + +-- Location: LABCELL_X2_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1189\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[1]_OTERM1223\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult[1]_OTERM1223\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100010000111111110001000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[13]_OTERM1189\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[1]_OTERM1223\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~23_combout\); + +-- Location: LABCELL_X2_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~23_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~23_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~23_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~23_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100010000000000010001000000000001000101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~23_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~1_combout\); + +-- Location: LABCELL_X20_Y25_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(1)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(1)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000110011001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~2_combout\); + +-- Location: MLABCELL_X18_Y22_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~7_combout\); + +-- Location: MLABCELL_X18_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~7_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~8_combout\); + +-- Location: MLABCELL_X18_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~8_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~12_combout\))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~12_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100001100000011010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~3_combout\); + +-- Location: MLABCELL_X18_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100101010101000100011110000110011001010000010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~1_combout\); + +-- Location: MLABCELL_X18_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add34~93_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~93_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100001111000011110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~93_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~4_combout\); + +-- Location: MLABCELL_X18_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~93_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011001000111110101100100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~93_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~5_combout\); + +-- Location: LABCELL_X17_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111111100000000111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~2_combout\); + +-- Location: LABCELL_X17_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~83\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~83_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~75_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~83_combout\); + +-- Location: LABCELL_X17_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~84\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~84_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~83_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~83_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001110000111110000111000011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~83_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~84_combout\); + +-- Location: LABCELL_X17_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~86\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~86_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~20_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111000001111000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~86_combout\); + +-- Location: LABCELL_X12_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~48_combout\); + +-- Location: LABCELL_X16_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~48_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~48_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~48_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~48_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100000011000111011100111111010001000011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~31_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~49_combout\); + +-- Location: LABCELL_X17_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~85_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~49_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~8_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~49_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~8_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111100011001000111110001100100000001000110010000000100011001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~49_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~85_combout\); + +-- Location: LABCELL_X17_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~85_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~84_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~85_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~85_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~84_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~86_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~85_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110000000000000011001100110011001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~84_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~86_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~85_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~3_combout\); + +-- Location: MLABCELL_X18_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010100000000000101010100000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~6_combout\); + +-- Location: MLABCELL_X18_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~3_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111001111110011111100111111001111110001111100111111000111110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~4_combout\); + +-- Location: FF_X18_Y22_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~4_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(1)); + +-- Location: MLABCELL_X18_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(1) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(1) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\); + +-- Location: LABCELL_X10_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[1]_NEW2809\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[1]_OTERM2810\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[1]_OTERM2810\); + +-- Location: FF_X10_Y22_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[1]_OTERM2810\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(1)); + +-- Location: LABCELL_X12_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[1]_NEW2937\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[1]_OTERM2938\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000001011011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[1]_OTERM2938\); + +-- Location: FF_X12_Y19_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[1]_OTERM2938\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(1)); + +-- Location: LABCELL_X12_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[1]_NEW2745\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[1]_OTERM2746\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[1]_OTERM2746\); + +-- Location: FF_X12_Y19_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[1]_OTERM2746\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(1)); + +-- Location: LABCELL_X10_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[1]_NEW2873\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[1]_OTERM2874\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[1]_OTERM2874\); + +-- Location: FF_X10_Y22_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[1]_OTERM2874\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(1)); + +-- Location: LABCELL_X12_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux86~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(1))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(1) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~1_combout\); + +-- Location: LABCELL_X12_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[1]_NEW3129\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[1]_OTERM3130\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[1]_OTERM3130\); + +-- Location: FF_X12_Y19_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[1]_OTERM3130\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(1)); + +-- Location: MLABCELL_X13_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[1]_NEW3065\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[1]_OTERM3066\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[1]_OTERM3066\); + +-- Location: FF_X13_Y23_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[1]_OTERM3066\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(1)); + +-- Location: LABCELL_X12_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[1]_NEW3001\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[1]_OTERM3002\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[1]_OTERM3002\); + +-- Location: FF_X12_Y26_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[1]_OTERM3002\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(1)); + +-- Location: LABCELL_X12_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[1]_NEW3193\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[1]_OTERM3194\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[1]_OTERM3194\); + +-- Location: FF_X12_Y19_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[1]_OTERM3194\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(1)); + +-- Location: LABCELL_X12_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux86~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(1)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001110111011101110100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~0_combout\); + +-- Location: LABCELL_X12_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux86~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux86~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2_combout\); + +-- Location: FF_X9_Y14_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1)); + +-- Location: LABCELL_X19_Y10_N51 +\myVirtualToplevel|Selector15~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector15~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + combout => \myVirtualToplevel|Selector15~1_combout\); + +-- Location: LABCELL_X19_Y10_N48 +\myVirtualToplevel|Selector15~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector15~2_combout\ = ( !\myVirtualToplevel|Selector15~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (\myVirtualToplevel|SD_CS~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datab => \myVirtualToplevel|ALT_INV_SD_CS~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_Selector15~1_combout\, + combout => \myVirtualToplevel|Selector15~2_combout\); + +-- Location: LABCELL_X21_Y10_N36 +\myVirtualToplevel|Selector13~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector13~0_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\ & ( !\myVirtualToplevel|Selector15~7_combout\ & ( (\myVirtualToplevel|Selector11~0_combout\ & ((!\myVirtualToplevel|Selector15~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))))) ) ) ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\ & ( !\myVirtualToplevel|Selector15~7_combout\ & ( (\myVirtualToplevel|Selector11~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & (\myVirtualToplevel|Selector15~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100010100000101010000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Selector11~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + datac => \myVirtualToplevel|ALT_INV_Selector15~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + datae => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~q\, + dataf => \myVirtualToplevel|ALT_INV_Selector15~7_combout\, + combout => \myVirtualToplevel|Selector13~0_combout\); + +-- Location: FF_X21_Y10_N37 +\myVirtualToplevel|SD_STATE.SD_STATE_WRITE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector13~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\); + +-- Location: LABCELL_X20_Y10_N42 +\myVirtualToplevel|Selector19~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector19~0_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\ & ( (!\myVirtualToplevel|SD_DATA_REQ~q\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\))) # (\myVirtualToplevel|SD_DATA_REQ~q\ & +-- (!\myVirtualToplevel|SD_DATA_WRITE[7]~1_combout\)) ) ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\ & ( (!\myVirtualToplevel|SD_DATA_WRITE[7]~1_combout\ & (!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\ & \myVirtualToplevel|SD_DATA_REQ~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010001000000000001000100000001111101010100000111110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_DATA_WRITE[7]~1_combout\, + datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_1~q\, + combout => \myVirtualToplevel|Selector19~0_combout\); + +-- Location: FF_X20_Y10_N43 +\myVirtualToplevel|SD_DATA_REQ\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector19~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_DATA_REQ~q\); + +-- Location: LABCELL_X20_Y10_N3 +\myVirtualToplevel|Selector12~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector12~0_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & (!\myVirtualToplevel|SD_DATA_REQ~q\ & \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000000000000011000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\, + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_1~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\, + combout => \myVirtualToplevel|Selector12~0_combout\); + +-- Location: LABCELL_X21_Y10_N18 +\myVirtualToplevel|Selector11~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector11~0_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\ & ( !\myVirtualToplevel|Selector12~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_Selector12~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~DUPLICATE_q\, + combout => \myVirtualToplevel|Selector11~0_combout\); + +-- Location: LABCELL_X21_Y10_N27 +\myVirtualToplevel|Selector11~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector11~1_combout\ = ( !\myVirtualToplevel|Selector15~7_combout\ & ( \myVirtualToplevel|Selector11~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_Selector11~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_Selector15~7_combout\, + combout => \myVirtualToplevel|Selector11~1_combout\); + +-- Location: LABCELL_X21_Y10_N42 +\myVirtualToplevel|Selector16~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector16~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) & ( (\myVirtualToplevel|Selector11~1_combout\ & (!\myVirtualToplevel|Selector15~2_combout\ & \myVirtualToplevel|SD_STATE.SD_STATE_READ~q\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) & ( (\myVirtualToplevel|Selector11~1_combout\ & ((!\myVirtualToplevel|Selector15~2_combout\ & ((\myVirtualToplevel|SD_STATE.SD_STATE_READ~q\))) # (\myVirtualToplevel|Selector15~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000001010100000100000101010000000000010001000000000001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Selector11~1_combout\, + datab => \myVirtualToplevel|ALT_INV_Selector15~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + combout => \myVirtualToplevel|Selector16~0_combout\); + +-- Location: FF_X21_Y10_N43 +\myVirtualToplevel|SD_STATE.SD_STATE_READ\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector16~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_STATE.SD_STATE_READ~q\); + +-- Location: LABCELL_X19_Y9_N12 +\myVirtualToplevel|SD_DATA_VALID~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_DATA_VALID~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|SD_CS~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000000000010000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|ALT_INV_SD_CS~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + combout => \myVirtualToplevel|SD_DATA_VALID~0_combout\); + +-- Location: FF_X20_Y10_N25 +\myVirtualToplevel|SD_DATA_VALID\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector21~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_DATA_VALID~q\); + +-- Location: LABCELL_X20_Y10_N24 +\myVirtualToplevel|Selector21~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector21~0_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & ( ((!\myVirtualToplevel|SD_DATA_VALID~0_combout\ & \myVirtualToplevel|SD_DATA_VALID~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\) ) +-- ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_READ~q\ & (!\myVirtualToplevel|SD_DATA_VALID~0_combout\ & \myVirtualToplevel|SD_DATA_VALID~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000000000001010000000110011111100110011001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_SD_DATA_VALID~0_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_DATA_VALID~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\, + combout => \myVirtualToplevel|Selector21~0_combout\); + +-- Location: FF_X20_Y10_N26 +\myVirtualToplevel|SD_DATA_VALID~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector21~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_DATA_VALID~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y10_N21 +\myVirtualToplevel|Selector17~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector17~0_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_READ~q\ & ( ((!\myVirtualToplevel|SD_DATA_VALID~DUPLICATE_q\ & (\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\) ) ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_READ~q\ & ( (!\myVirtualToplevel|SD_DATA_VALID~DUPLICATE_q\ & +-- (\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000100000001000000010000000100000111111110010000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_DATA_VALID~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~DUPLICATE_q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~q\, + combout => \myVirtualToplevel|Selector17~0_combout\); + +-- Location: LABCELL_X20_Y10_N51 +\myVirtualToplevel|Selector17~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector17~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & ( ((!\myVirtualToplevel|Selector15~2_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & +-- \myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\))) # (\myVirtualToplevel|Selector17~0_combout\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & ( \myVirtualToplevel|Selector17~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101110101010101010111010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_Selector17~0_combout\, + datab => \myVirtualToplevel|ALT_INV_Selector15~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\, + combout => \myVirtualToplevel|Selector17~1_combout\); + +-- Location: FF_X20_Y10_N53 +\myVirtualToplevel|SD_STATE.SD_STATE_READ_1\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector17~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\); + +-- Location: LABCELL_X20_Y10_N27 +\myVirtualToplevel|Selector20~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector20~0_combout\ = ( \myVirtualToplevel|SD_DATA_VALID~DUPLICATE_q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\) # (\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~q\) ) ) # ( !\myVirtualToplevel|SD_DATA_VALID~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\ & !\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000011110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\, + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_DATA_VALID~DUPLICATE_q\, + combout => \myVirtualToplevel|Selector20~0_combout\); + +-- Location: LABCELL_X20_Y10_N54 +\myVirtualToplevel|Selector20~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector20~1_combout\ = ( \myVirtualToplevel|SD_HNDSHK_IN\(0) & ( \myVirtualToplevel|Selector20~0_combout\ ) ) # ( !\myVirtualToplevel|SD_HNDSHK_IN\(0) & ( \myVirtualToplevel|Selector20~0_combout\ & ( (!\myVirtualToplevel|SD_CHANNEL~q\ +-- & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & \myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\)) # (\myVirtualToplevel|Selector15~0_combout\))) ) ) ) # ( \myVirtualToplevel|SD_HNDSHK_IN\(0) & ( +-- !\myVirtualToplevel|Selector20~0_combout\ & ( (((\myVirtualToplevel|Selector15~0_combout\) # (\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\)) # (\myVirtualToplevel|SD_CHANNEL~q\) ) ) +-- ) # ( !\myVirtualToplevel|SD_HNDSHK_IN\(0) & ( !\myVirtualToplevel|Selector20~0_combout\ & ( (!\myVirtualToplevel|SD_CHANNEL~q\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & \myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\)) # +-- (\myVirtualToplevel|Selector15~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010101010011111111111111100000010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_CHANNEL~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\, + datad => \myVirtualToplevel|ALT_INV_Selector15~0_combout\, + datae => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0), + dataf => \myVirtualToplevel|ALT_INV_Selector20~0_combout\, + combout => \myVirtualToplevel|Selector20~1_combout\); + +-- Location: FF_X20_Y10_N55 +\myVirtualToplevel|SD_HNDSHK_IN[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector20~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_HNDSHK_IN\(0)); + +-- Location: LABCELL_X26_Y7_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000010110000101100001011000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(9), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~0_combout\); + +-- Location: LABCELL_X25_Y7_N15 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~0_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\)) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001010000010111001100110011001100110111001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~0_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnData_v~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~1_combout\); + +-- Location: LABCELL_X24_Y7_N21 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ & +-- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ & (!\myVirtualToplevel|SD_HNDSHK_IN\(0) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\))) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~1_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\) # ((!\myVirtualToplevel|SD_HNDSHK_IN\(0) & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001110000000001100111000000010110011100000001011001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~2_combout\); + +-- Location: FF_X24_Y7_N22 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y9_N24 +\myVirtualToplevel|SD_OVERRUN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_OVERRUN~0_combout\ = ( \myVirtualToplevel|SD_CS~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001000000000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_SD_CS~combout\, + combout => \myVirtualToplevel|SD_OVERRUN~0_combout\); + +-- Location: LABCELL_X19_Y9_N48 +\myVirtualToplevel|SD_OVERRUN~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_OVERRUN~1_combout\ = ( !\myVirtualToplevel|SD_OVERRUN~q\ & ( \myVirtualToplevel|SD_OVERRUN~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & (\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & \myVirtualToplevel|SD_DATA_VALID~q\))) ) ) ) # ( \myVirtualToplevel|SD_OVERRUN~q\ & ( !\myVirtualToplevel|SD_OVERRUN~0_combout\ ) ) # ( !\myVirtualToplevel|SD_OVERRUN~q\ & ( +-- !\myVirtualToplevel|SD_OVERRUN~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & (\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & +-- \myVirtualToplevel|SD_DATA_VALID~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000010111111111111111100000000000000100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\, + datad => \myVirtualToplevel|ALT_INV_SD_DATA_VALID~q\, + datae => \myVirtualToplevel|ALT_INV_SD_OVERRUN~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_OVERRUN~0_combout\, + combout => \myVirtualToplevel|SD_OVERRUN~1_combout\); + +-- Location: FF_X19_Y9_N50 +\myVirtualToplevel|SD_OVERRUN\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_OVERRUN~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_OVERRUN~q\); + +-- Location: FF_X20_Y7_N49 +\myVirtualToplevel|SD_ADDR[0][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][6]~q\); + +-- Location: FF_X19_Y9_N25 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5), + sload => VCC, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(6)); + +-- Location: LABCELL_X19_Y9_N0 +\myVirtualToplevel|Mux77~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux77~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # (\myVirtualToplevel|SD_OVERRUN~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|SD_ADDR[0][6]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(6) & ( (\myVirtualToplevel|SD_OVERRUN~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(6) +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|SD_ADDR[0][6]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000100010001000100001100000011001101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_OVERRUN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(6), + combout => \myVirtualToplevel|Mux77~0_combout\); + +-- Location: FF_X19_Y9_N1 +\myVirtualToplevel|IO_DATA_READ_SD[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux77~0_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(6)); + +-- Location: LABCELL_X20_Y14_N18 +\myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\ = ( !\myVirtualToplevel|MEM_DATA_READ[6]~86_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(6) & +-- (((\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\)))))) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[6]~86_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))) # (\myVirtualToplevel|IO_DATA_READ_SD\(6)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ +-- & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001101000100110011110100010000000011011101111100111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(6), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~86_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]~21_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\); + +-- Location: LABCELL_X7_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~27_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~111_Duplicate_170\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~27_combout\); + +-- Location: FF_X7_Y17_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_NEW_REG558\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~27_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM559\); + +-- Location: FF_X7_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_NEW_REG554\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM555\); + +-- Location: LABCELL_X7_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- (\myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~111_Duplicate_170\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~26_combout\); + +-- Location: FF_X7_Y17_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_NEW_REG556\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~26_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM557\); + +-- Location: LABCELL_X7_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM555\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM557\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM559\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM555\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM557\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM559\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM555\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM557\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM559\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM555\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM557\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM559\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100111111110011011100000000110001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM559\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM555\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM557\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\); + +-- Location: MLABCELL_X23_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~226\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~226_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~226_combout\); + +-- Location: FF_X23_Y32_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~226_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\); + +-- Location: MLABCELL_X23_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000011111101010000001100000101111100111111010111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\); + +-- Location: MLABCELL_X23_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100000011000111011100111111010001000011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4_combout\); + +-- Location: LABCELL_X29_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110100001010100011111000100001011101010110101101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14_combout\); + +-- Location: LABCELL_X31_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19_combout\); + +-- Location: LABCELL_X17_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000111001101110000010011110100110001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\); + +-- Location: LABCELL_X16_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100010101010101010001010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\); + +-- Location: MLABCELL_X13_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000110010001100100011001000110000000000000000001000110010001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~35_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~1_combout\); + +-- Location: MLABCELL_X13_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000100000000001100010000000000110000000000000011000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~2_combout\); + +-- Location: MLABCELL_X13_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000101010101111101000000000010100000000000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~3_combout\); + +-- Location: MLABCELL_X13_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001101111111111100110100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~4_combout\); + +-- Location: MLABCELL_X13_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010001000101010001000100010101000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~5_combout\); + +-- Location: FF_X13_Y33_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG947\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM948\); + +-- Location: FF_X7_Y35_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG937\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\); + +-- Location: LABCELL_X6_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111000001110000011100000111000001110000011100000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\); + +-- Location: FF_X6_Y35_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG945\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\); + +-- Location: LABCELL_X7_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM948\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM948\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM948\)) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000101110111011101100000011000000001010101110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM948\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\); + +-- Location: LABCELL_X7_Y35_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux7~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) +-- & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111000001000011011100110100110001111100010011110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~1_combout\); + +-- Location: MLABCELL_X9_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux7~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux7~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\); + +-- Location: MLABCELL_X9_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux8~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\); + +-- Location: MLABCELL_X9_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100000011000000110011001100110011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr2~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~0_combout\); + +-- Location: MLABCELL_X9_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~0_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) # +-- (\myVirtualToplevel|MEM_BUSY~1_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~0_combout\ & ( +-- (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) # (\myVirtualToplevel|MEM_BUSY~1_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & +-- (!\myVirtualToplevel|MEM_BUSY~1_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000000000011111111111111100000000000000000011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~1_combout\); + +-- Location: FF_X9_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\); + +-- Location: LABCELL_X19_Y10_N36 +\myVirtualToplevel|SD_CHANNEL~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_CHANNEL~0_combout\ = ( \myVirtualToplevel|SD_CHANNEL~q\ & ( \myVirtualToplevel|SD_CS~combout\ & ( (!\myVirtualToplevel|RESET_n~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) # +-- ((!\myVirtualToplevel|UART1|Mux0~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|SD_CHANNEL~q\ & ( \myVirtualToplevel|SD_CS~combout\ & ( (\myVirtualToplevel|RESET_n~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (\myVirtualToplevel|UART1|Mux0~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|SD_CHANNEL~q\ & ( !\myVirtualToplevel|SD_CS~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000011111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datac => \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ALT_INV_SD_CHANNEL~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_CS~combout\, + combout => \myVirtualToplevel|SD_CHANNEL~0_combout\); + +-- Location: FF_X19_Y10_N37 +\myVirtualToplevel|SD_CHANNEL\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_CHANNEL~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_CHANNEL~q\); + +-- Location: LABCELL_X21_Y10_N0 +\myVirtualToplevel|Selector0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Selector0~0_combout\ = ( \myVirtualToplevel|SD_RESET\(0) & ( \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\) # ((\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & +-- ((!\myVirtualToplevel|Equal8~1_combout\) # (\myVirtualToplevel|SD_CHANNEL~q\)))) ) ) ) # ( !\myVirtualToplevel|SD_RESET\(0) & ( \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (!\myVirtualToplevel|SD_CHANNEL~q\ & +-- !\myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\) ) ) ) # ( \myVirtualToplevel|SD_RESET\(0) & ( !\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( ((!\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\) # ((!\myVirtualToplevel|Equal8~1_combout\) # +-- (!\myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\))) # (\myVirtualToplevel|SD_CHANNEL~q\) ) ) ) # ( !\myVirtualToplevel|SD_RESET\(0) & ( !\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (!\myVirtualToplevel|SD_CHANNEL~q\ & +-- !\myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000000000111111111111110110101010000000001111111100110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_CHANNEL~q\, + datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\, + datac => \myVirtualToplevel|ALT_INV_Equal8~1_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~q\, + datae => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_IDLE~q\, + combout => \myVirtualToplevel|Selector0~0_combout\); + +-- Location: FF_X21_Y10_N2 +\myVirtualToplevel|SD_RESET[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Selector0~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_RESET\(0)); + +-- Location: LABCELL_X24_Y6_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~58_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & (!\myVirtualToplevel|SD_RD\(0))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000011110011110000001111001111000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datac => \myVirtualToplevel|ALT_INV_SD_RD\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~58_combout\); + +-- Location: MLABCELL_X23_Y6_N27 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~59_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~58_combout\ ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~58_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\))) ) ) ) # ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~58_combout\ & ( (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111011100000000000010001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~47_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr34~combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~58_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~59_combout\); + +-- Location: FF_X23_Y6_N28 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~59_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK~q\); + +-- Location: MLABCELL_X23_Y6_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~83\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~83_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010000000000000000000101010101010100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_BLK~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~83_combout\); + +-- Location: FF_X23_Y6_N53 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~83_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\); + +-- Location: LABCELL_X24_Y7_N15 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000110000001100000011000000110000001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\); + +-- Location: LABCELL_X24_Y9_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector1~0_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(14))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001110001011000000111000101100000011100010110000001110001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector3~1_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(6), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(14), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector1~0_combout\); + +-- Location: FF_X24_Y9_N31 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector1~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(14)); + +-- Location: LABCELL_X21_Y9_N36 +\myVirtualToplevel|IO_DATA_READ_SD[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[30]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(14) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(14), + combout => \myVirtualToplevel|IO_DATA_READ_SD[30]~feeder_combout\); + +-- Location: FF_X21_Y9_N8 +\myVirtualToplevel|SD_ADDR[0][30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30), + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][30]~q\); + +-- Location: FF_X21_Y9_N38 +\myVirtualToplevel|IO_DATA_READ_SD[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[30]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][30]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(30)); + +-- Location: LABCELL_X21_Y14_N9 +\myVirtualToplevel|MEM_DATA_READ[30]~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[30]~46_combout\ = (\myVirtualToplevel|IO_DATA_READ_SD\(30) & \myVirtualToplevel|MEM_DATA_READ[17]~25_combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000100010001000100010001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(30), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~25_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[30]~46_combout\); + +-- Location: LABCELL_X20_Y11_N9 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[6]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[6]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100001101000000011111110111110001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[14]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[6]~2_combout\); + +-- Location: M10K_X38_Y6_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001B6E44DAFCE875FBDB6F93C84CA6DF733EBE359F9CE73BDFBDFA440D800333DBEDAED7B7BBF4B7FDD57DFFE95D5FBFFFFFC029FFFE02980B5B71FBF6DA8F52E0190F85E17BA5918E8D8D8102141837DEFA4000000E77F04779426F085006B5D5781C4FFE676F3E05E8552CBCE", + mem_init2 => "CA08D188E5053F050FF0CB0F443515E320F40C7F860C3DEC51839414FE11CA0CF6F9E6C01FE3386F39AF3E7F0B099561C9286C2448B417DA468973040C24FF36ABCC7BC95BD7C2A8ADEBA154503778AE0E9F2D9A47D8D1968A27615CB49F522578A6BC6DB697264272E324F5AD652E4B84475527F5C21F4D65A736E01002C98260464434917D68530EF0DBE0954D56154D3A30B6EA2A8859235B88262200AAEB09405464C0A14CCAA76F794ACC5E510544BCB3511F14054104D4EA93A8B94E48A225E82AA834C71E83D82C17003D3227382EAE0DEDB126B45AE936E1AAAFD193CAA8946218628C42301C3C53E9524EF3DAD2264E94656334A0BF25A53023282B", + mem_init1 => "CA650152809E7A9014957E44D52C6F215EE10D058931E72DA75754E11A0CAAB05199F06FAC8A54CD28497A1223A4D1F5884566E641C526659A75E0268FE7500500917E01D3592B4008E1D81411046120A01A6029A6604184887609533CB24465E0002AA1B0206AEB33BFD3CC87141780152FB8F9308470971D0BB6708B9C9E64441A3910AB4B8C3C1A4CE26928910CFBC7492D18C99C40A49847851921960681E1131116054A64A513540284CECB3E80D2F215EE4131415162091C2C090B15E1A20734C4615C8209B28F7722881C22C2B23C23C3380F45864C8A83E92AF108480349374CA868E1200286B60040229401CE73266102442366E66E1633492E0B0C", + mem_init0 => "0C1B17A5C1B94D4A51224274DCB6A535EA244C9A09E2843881938181CCBCC4D3BFB5299CCBAE67CF28FE54EF320C9C1712A5C2B885D9C8900296E9614C39EF3F2A44A4E15CCE4833600F0501B6106B996CF8A6DB556382CB59C3870A1438B0508231A0B51A2416A34482D44D2430180C0E59A98A8246299D15641F41AE914474D29E096064210A30600025B643234D0502644C5AE8E153AFBD2963882AD10CD151AA04822D555A80815140A28A8016102A2818AB4234870075402A8000000000000000000000000005500AA017402A80FFFFFFFFFFFA402402402402402400FEF9000000010000A1190808050303010313136103010100000743072B21130002", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 6, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 6, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\); + +-- Location: M10K_X38_Y7_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 6, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 6, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\); + +-- Location: FF_X21_Y14_N38 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_NEW_REG82\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM83\); + +-- Location: LABCELL_X21_Y14_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM85\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM83\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM85\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM83\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111100000000001111110000000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]_OTERM83\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]_OTERM85\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28_combout\); + +-- Location: LABCELL_X17_Y10_N42 +\myVirtualToplevel|IO_DATA_READ~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~81_combout\ = (\myVirtualToplevel|IO_DATA_READ[26]~78_combout\ & \myVirtualToplevel|MILLISEC_UP_COUNTER\(30)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000100010001000100010001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[26]~78_combout\, + datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(30), + combout => \myVirtualToplevel|IO_DATA_READ~81_combout\); + +-- Location: FF_X17_Y10_N44 +\myVirtualToplevel|IO_DATA_READ[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~81_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(30)); + +-- Location: LABCELL_X21_Y14_N15 +\myVirtualToplevel|MEM_DATA_READ[30]~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[30]~45_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28_combout\ & ( \myVirtualToplevel|IO_DATA_READ\(30) & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\) # (\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28_combout\ & ( \myVirtualToplevel|IO_DATA_READ\(30) & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & (\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & +-- ((\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28_combout\ & ( !\myVirtualToplevel|IO_DATA_READ\(30) & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & (!\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28_combout\ & ( !\myVirtualToplevel|IO_DATA_READ\(30) & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & (\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[30]~20_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010100000001000101000100000001010101010000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~23_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~21_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~20_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]~28_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(30), + combout => \myVirtualToplevel|MEM_DATA_READ[30]~45_combout\); + +-- Location: LABCELL_X21_Y14_N3 +\myVirtualToplevel|MEM_DATA_READ[30]~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[30]~47_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14~portbdataout\ & ( \myVirtualToplevel|MEM_DATA_READ[30]~45_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14~portbdataout\ & ( \myVirtualToplevel|MEM_DATA_READ[30]~45_combout\ ) ) # ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14~portbdataout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[30]~45_combout\ & ( ((\myVirtualToplevel|LessThan0~1_combout\ & ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6~portbdataout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0))))) # (\myVirtualToplevel|MEM_DATA_READ[30]~46_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14~portbdataout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[30]~45_combout\ & ( ((!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0) & (\myVirtualToplevel|LessThan0~1_combout\ & +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6~portbdataout\))) # (\myVirtualToplevel|MEM_DATA_READ[30]~46_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100111011001101110011111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~46_combout\, + datac => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\, + datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~45_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[30]~47_combout\); + +-- Location: LABCELL_X20_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector344~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector344~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~41_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[14]~139_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & (\myVirtualToplevel|MEM_DATA_READ[30]~47_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add7~41_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[14]~139_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & +-- (\myVirtualToplevel|MEM_DATA_READ[30]~47_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100000011000100010000111111011101110011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~47_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~139_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~41_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector344~0_combout\); + +-- Location: FF_X20_Y15_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector344~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(14)); + +-- Location: LABCELL_X20_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(14) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(14) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\); + +-- Location: MLABCELL_X9_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100001111111111110000111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~41_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[14]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~36_combout\); + +-- Location: MLABCELL_X9_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~41_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~36_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~36_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~41_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~37_combout\); + +-- Location: MLABCELL_X9_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~37_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\))) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~37_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111111111000000111111111100000000111111000000000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~38_combout\); + +-- Location: FF_X9_Y25_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~38_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\); + +-- Location: LABCELL_X5_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~45_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~45_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~45_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010000000000000000010101010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~39_combout\); + +-- Location: LABCELL_X10_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~45_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add21~45_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~45_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp~39_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add21~45_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp~39_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100111111111100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~39_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~45_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~45_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~40_combout\); + +-- Location: LABCELL_X10_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[15]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[15]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~40_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~40_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~40_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111111111111100000000000000001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~40_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[15]~41_combout\); + +-- Location: FF_X10_Y24_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[15]~41_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(15)); + +-- Location: LABCELL_X5_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101011111010111110101111101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\); + +-- Location: LABCELL_X6_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~45_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~45_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~32_combout\); + +-- Location: LABCELL_X6_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~32_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~32_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(15) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1068~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~32_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~33_combout\); + +-- Location: FF_X6_Y29_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~33_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(15)); + +-- Location: LABCELL_X6_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000000001010101010101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~45_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~38_combout\); + +-- Location: LABCELL_X7_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~38_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~38_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~38_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~38_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000101110111111101100000100010001001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1068~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[15]~38_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~39_combout\); + +-- Location: FF_X7_Y30_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~39_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(15)); + +-- Location: LABCELL_X7_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000010100000101000110011001100110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~45_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~35_combout\); + +-- Location: LABCELL_X7_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~35_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~35_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~35_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~35_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101110101111111100010101000000001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1068~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[15]~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~36_combout\); + +-- Location: FF_X7_Y31_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~36_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(15)); + +-- Location: LABCELL_X6_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~45_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~45_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~34_combout\); + +-- Location: LABCELL_X6_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~34_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(15) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~34_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010101101110101011111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1068~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[15]~34_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~35_combout\); + +-- Location: FF_X6_Y29_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~35_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(15)); + +-- Location: LABCELL_X6_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(15) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(15) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(15) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(15) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~1_combout\); + +-- Location: LABCELL_X14_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110000010101010011000001010101001111110101010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~45_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~35_combout\); + +-- Location: LABCELL_X14_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~35_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~35_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(15) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1068~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[15]~35_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~36_combout\); + +-- Location: FF_X14_Y28_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~36_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(15)); + +-- Location: LABCELL_X14_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110000010101010011000001010101001111110101010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~45_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~36_combout\); + +-- Location: LABCELL_X14_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~36_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~36_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(15) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000100111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1068~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[15]~36_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~37_combout\); + +-- Location: FF_X14_Y28_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~37_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(15)); + +-- Location: LABCELL_X14_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010000010100110101000001010011010111110101001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~45_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~31_combout\); + +-- Location: LABCELL_X14_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~31_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~31_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~31_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~31_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000110111111100111100010000001100001101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1068~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[15]~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~32_combout\); + +-- Location: FF_X14_Y28_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~32_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(15)); + +-- Location: LABCELL_X14_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~45_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~45_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~34_combout\); + +-- Location: LABCELL_X14_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~34_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~34_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~34_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~34_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000000101111111011101100000100010001001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1068~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[15]~34_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~35_combout\); + +-- Location: FF_X14_Y28_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~35_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(15)); + +-- Location: LABCELL_X14_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(15) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(15) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(15) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(15) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~0_combout\); + +-- Location: LABCELL_X7_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\); + +-- Location: LABCELL_X14_Y13_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector201~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~45_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~45_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~45_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~45_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000001011010101000001111111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~1_combout\); + +-- Location: LABCELL_X14_Y13_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector201~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector201~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector201~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15) & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010000000101010001011110101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector201~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~0_combout\); + +-- Location: FF_X14_Y13_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\); + +-- Location: FF_X19_Y12_N25 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0)); + +-- Location: LABCELL_X14_Y14_N39 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[3]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[3]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010001100110011001101011111010111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(27), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[3]~6_combout\); + +-- Location: M10K_X30_Y16_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 3, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 3, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X26_Y6_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector4~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector4~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(11) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) +-- # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(11) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(11) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & +-- ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100011111110100000011000000110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_STD_MATCH~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o~3_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(11), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(3), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector4~0_combout\); + +-- Location: FF_X26_Y6_N31 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector4~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(11)); + +-- Location: LABCELL_X21_Y9_N48 +\myVirtualToplevel|IO_DATA_READ_SD[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[27]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(11) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(11), + combout => \myVirtualToplevel|IO_DATA_READ_SD[27]~feeder_combout\); + +-- Location: LABCELL_X21_Y9_N27 +\myVirtualToplevel|SD_ADDR[0][27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(27), + combout => \myVirtualToplevel|SD_ADDR[0][27]~feeder_combout\); + +-- Location: FF_X21_Y9_N29 +\myVirtualToplevel|SD_ADDR[0][27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][27]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][27]~q\); + +-- Location: FF_X21_Y9_N49 +\myVirtualToplevel|IO_DATA_READ_SD[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[27]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][27]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(27)); + +-- Location: LABCELL_X21_Y14_N57 +\myVirtualToplevel|MEM_DATA_READ[27]~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[27]~58_combout\ = (\myVirtualToplevel|MEM_DATA_READ[17]~25_combout\ & \myVirtualToplevel|IO_DATA_READ_SD\(27)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~25_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(27), + combout => \myVirtualToplevel|MEM_DATA_READ[27]~58_combout\); + +-- Location: M10K_X30_Y17_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022D0007992022C0200505048C2883CB8D838493400000319018C2014802004A55D6A4D2019387413880362604C109FF500003F999999D401091CA0D0820640801B01004000018426A42020409512002EA00000000E4FB284E69CB7CB4E036B2EC814D5FE8D1A4029A06D53F8E", + mem_init2 => "875BDA8BC3AC1AB28BDB211FB3CBA40311FA045FB9047A13DE6F0EF079F7877CE781F98386CBF4FC318838781AB49355FF63B84FEFFEDC7E39C912C9F3070CC0160A003944238156A21160AB54D4230B42A08134BD281A8869C13C8C4964356563586312490C100DC05E454E538341348C863A4B0BB7B693892859CA5534960746486EAD026E9F7CF35F01D16874E76874B141A952C3CCCAAC999FF604DFC6A735187021721BB8224DC1858C90100C6F8437D343EEEE02587B33F16A2018B0065CF9244300C6E0CEE72190B65FE2785926D0900CAD97CC04F18E62BE311771EC3011405DC489338C6EE06BC3A6C3A500EFAFAA8C7B48DD08410A598049C2C5C7", + mem_init1 => "019914805A69D665B30808A10A43EF088107FDDC014356CA078461C6E1110411821358651A100B704DC0A0FFBA5B64E277389C901018D09B09D2805B275E2C9C562630471C83C49843D830122E0B00ED10A4FAD1E419F6019591B22C2A583000F592D15DA6D600B2A149C2051332CBD50ECDECE40C73606264B0679323A6AACB28051C01C2D5310325B00496C622E15D5140728F82A05ACA8256BFB04EA1C05E06642C6A24359AD84CA00E0FB197CFDCDD1CA0D684FEE6334D301AD6932525131D1341DB80953F0208F5D27F4B4A1C1901D53C8847CC0871830651D212A010B65E0F141AD2A908D9F0B84F722AA58411D20B9B409C2BC09D01A20848342141B3", + mem_init0 => "C0C4A811871C58358A28046B8E241AD1E5C08D28D61012C9D62F020650403C2C40084400181808CAE2088A20446D238D4B50021898AE195C111912F8A2657416998012658B15F0DA6B143A576C66026D0067740028A3DC0E814082040010100C24AF4900546120088C2403061B1D8FC74224021A0400E0400094A10241005A9B2C20F38FE7BDEFE214150004824138D231081420D0068C182044F181CAAF4CD7D77AB7EEEED75553AF7857FFBBBA74F5EF0ABF15650A40007562EAC00000000000000000000000005DD0BBA17542EAC4FFFFFFFFFFFFB6DB6DB6DB6DFFFB6DFEF800000000000004007D7D02000000000808300406020300001C000450100D03", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 3, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 3, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X17_Y12_N33 +\myVirtualToplevel|IO_DATA_READ~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~85_combout\ = ( \myVirtualToplevel|IO_DATA_READ[26]~78_combout\ & ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(27) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(27), + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ[26]~78_combout\, + combout => \myVirtualToplevel|IO_DATA_READ~85_combout\); + +-- Location: FF_X17_Y12_N34 +\myVirtualToplevel|IO_DATA_READ[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~85_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(27)); + +-- Location: FF_X21_Y14_N44 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_NEW_REG18\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM19\); + +-- Location: LABCELL_X21_Y14_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM21\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM19\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM21\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM19\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111100000000001111110000000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]_OTERM19\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]_OTERM21\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32_combout\); + +-- Location: LABCELL_X21_Y14_N33 +\myVirtualToplevel|MEM_DATA_READ[27]~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[27]~57_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[2]~22_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & (\myVirtualToplevel|IO_DATA_READ\(27))) # (\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\) # +-- (\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\))) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[2]~22_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & (\myVirtualToplevel|IO_DATA_READ\(27))) # (\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[30]~20_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ & (\myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[30]~20_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100010000000100110011000000110011000100000001001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(27), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~23_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~21_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~20_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]~32_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[27]~57_combout\); + +-- Location: LABCELL_X21_Y14_N48 +\myVirtualToplevel|MEM_DATA_READ[27]~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3~portbdataout\ & ( \myVirtualToplevel|MEM_DATA_READ[27]~57_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3~portbdataout\ & ( \myVirtualToplevel|MEM_DATA_READ[27]~57_combout\ ) ) # ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3~portbdataout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[27]~57_combout\ & ( ((\myVirtualToplevel|LessThan0~1_combout\ & ((!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0)) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11~portbdataout\)))) # (\myVirtualToplevel|MEM_DATA_READ[27]~58_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3~portbdataout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[27]~57_combout\ & ( ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0) & (\myVirtualToplevel|LessThan0~1_combout\ & +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11~portbdataout\))) # (\myVirtualToplevel|MEM_DATA_READ[27]~58_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111111001000111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datab => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~58_combout\, + datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~57_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\); + +-- Location: MLABCELL_X18_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector355~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111111110000111100001111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~5_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~33_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~99_Duplicate_158\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~0_combout\); + +-- Location: MLABCELL_X18_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector355~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~1_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\) # +-- (\myVirtualToplevel|MEM_DATA_READ[27]~59_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\) # +-- (\myVirtualToplevel|MEM_DATA_READ[27]~59_combout\) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector355~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & (\myVirtualToplevel|MEM_DATA_READ[27]~59_combout\)) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector355~0_combout\ & ( (\myVirtualToplevel|MEM_DATA_READ[27]~59_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000111111001111110011111100111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~59_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~115_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector355~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~1_combout\); + +-- Location: FF_X18_Y16_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~1_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~81_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[3]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(3) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\); + +-- Location: LABCELL_X10_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~72\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~72_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add19~81_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)))))) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add21~81_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "1100010111000101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~81_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~81_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~72_combout\); + +-- Location: LABCELL_X10_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[3]~66\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[3]~66_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~72_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\))) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~72_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111111111000000111111111100000000111111000000000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~72_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[3]~66_combout\); + +-- Location: FF_X10_Y25_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[3]~66_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)); + +-- Location: LABCELL_X10_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000011111111111100001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\); + +-- Location: MLABCELL_X4_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~81_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~50_combout\); + +-- Location: MLABCELL_X4_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~50_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~50_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000001011011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1080~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[3]~50_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~51_combout\); + +-- Location: FF_X4_Y30_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~51_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(3)); + +-- Location: MLABCELL_X4_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~81_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~56_combout\); + +-- Location: MLABCELL_X4_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~57_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~56_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(3) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~56_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101101010111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[3]~56_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1080~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~57_combout\); + +-- Location: FF_X4_Y30_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~57_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(3)); + +-- Location: LABCELL_X5_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~81_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~52_combout\); + +-- Location: LABCELL_X6_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~52_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~52_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~52_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~52_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101111111010111100010000010100001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1080~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[3]~52_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~53_combout\); + +-- Location: FF_X6_Y31_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~53_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(3)); + +-- Location: LABCELL_X5_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001001110000010100100111000011011010111110001101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~53_combout\); + +-- Location: LABCELL_X5_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~53_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~53_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~53_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~53_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101110101111111100010101000000001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1080~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[3]~53_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~54_combout\); + +-- Location: FF_X5_Y31_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~54_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(3)); + +-- Location: MLABCELL_X4_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(3)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(3) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~1_combout\); + +-- Location: LABCELL_X10_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~81_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~53_combout\); + +-- Location: LABCELL_X10_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~53_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~53_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~53_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~53_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000010111111001111111000000001000000111111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1080~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[3]~53_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~54_combout\); + +-- Location: FF_X10_Y28_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~54_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(3)); + +-- Location: LABCELL_X6_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001001110000010100100111000011011010111110001101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~52_combout\); + +-- Location: LABCELL_X6_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~52_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~52_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101101011101011111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1080~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[3]~52_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~53_combout\); + +-- Location: FF_X6_Y27_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~53_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(3)); + +-- Location: LABCELL_X10_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~81_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~49_combout\); + +-- Location: LABCELL_X10_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~49_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~49_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111111111110100011100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1080~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[3]~49_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~50_combout\); + +-- Location: FF_X10_Y27_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~50_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(3)); + +-- Location: MLABCELL_X9_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000000000111100110011001100111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~81_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~54_combout\); + +-- Location: MLABCELL_X9_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~54_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~54_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~54_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~54_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100111111111111010000000000000001111111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1080~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~54_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~55_combout\); + +-- Location: FF_X9_Y31_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~55_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(3)); + +-- Location: MLABCELL_X4_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(3) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(3)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~0_combout\); + +-- Location: MLABCELL_X4_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\); + +-- Location: MLABCELL_X13_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~81_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000100110000011000010011000111111001101110011111100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\); + +-- Location: MLABCELL_X13_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector213~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010100000011111100110000001111110101000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector213~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~0_combout\); + +-- Location: FF_X13_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)); + +-- Location: FF_X20_Y7_N59 +\myVirtualToplevel|SD_ADDR[0][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5), + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][5]~q\); + +-- Location: FF_X19_Y9_N47 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4), + sload => VCC, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(5)); + +-- Location: LABCELL_X19_Y9_N33 +\myVirtualToplevel|Mux78~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux78~0_combout\ = ( \myVirtualToplevel|SD_DATA_VALID~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SD_ADDR[0][5]~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) # ( !\myVirtualToplevel|SD_DATA_VALID~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|SD_ADDR[0][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(5)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000010000100110000011001010111010001100101011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][5]~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(5), + dataf => \myVirtualToplevel|ALT_INV_SD_DATA_VALID~q\, + combout => \myVirtualToplevel|Mux78~0_combout\); + +-- Location: FF_X19_Y9_N34 +\myVirtualToplevel|IO_DATA_READ_SD[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux78~0_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(5)); + +-- Location: LABCELL_X20_Y14_N48 +\myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\ = ( !\myVirtualToplevel|MEM_DATA_READ[5]~88_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(5) & +-- (((\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\)))))) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[5]~88_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))) # (\myVirtualToplevel|IO_DATA_READ_SD\(5)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ +-- & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001101000100110011110100010000000011011101111100111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(5), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~88_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]~17_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\); + +-- Location: LABCELL_X7_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # +-- (\myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~127_Duplicate_167\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~25_combout\); + +-- Location: FF_X7_Y17_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_NEW_REG564\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM565\); + +-- Location: FF_X7_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_NEW_REG560\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM561\); + +-- Location: LABCELL_X7_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- (\myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~127_Duplicate_167\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~24_combout\); + +-- Location: FF_X7_Y17_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_NEW_REG562\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM563\); + +-- Location: LABCELL_X7_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM561\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM563\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM565\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM561\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM563\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM565\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM561\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM563\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM565\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM561\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM563\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM565\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000110011011111111100110001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM565\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM561\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM563\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\); + +-- Location: LABCELL_X26_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~351\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~351_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~351_combout\); + +-- Location: FF_X26_Y31_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~351_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~21_combout\); + +-- Location: LABCELL_X25_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~30_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~28_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~31_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~29_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000110001110111000011000011001100001100011101110000110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~28_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~31_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~29_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\); + +-- Location: LABCELL_X25_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~22_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~20_combout\)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~27_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~21_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000010100000101000001010000010110101010111111111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~21_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~27_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~23_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\); + +-- Location: MLABCELL_X23_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux150~16_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\); + +-- Location: MLABCELL_X23_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_BDD8960\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_BDD8960\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000101010001010100010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_RESYN8959_BDD8960\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\); + +-- Location: LABCELL_X17_Y27_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~6_combout\); + +-- Location: LABCELL_X16_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~7_combout\); + +-- Location: LABCELL_X5_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~55_combout\); + +-- Location: LABCELL_X17_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~45_combout\); + +-- Location: LABCELL_X17_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~52_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~55_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~45_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~52_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~45_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~52_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~55_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~45_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add36~52_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~45_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100111100001100000010101010100010001010000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~55_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~45_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~52_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~10_combout\); + +-- Location: MLABCELL_X18_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101000000000101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~9_combout\); + +-- Location: LABCELL_X17_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~49_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000110011001100000010101010101000001000100010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~49_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~8_combout\); + +-- Location: LABCELL_X17_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~9_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~9_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~10_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~9_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000000011110000000000000010000000000000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~11_combout\); + +-- Location: FF_X2_Y33_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[4]_NEW_REG1224\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~12_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[4]_OTERM1225\); + +-- Location: LABCELL_X2_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[4]_OTERM1225\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[4]_OTERM1225\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[4]_OTERM1225\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101111111111111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1209\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[4]_OTERM1225\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~12_combout\); + +-- Location: LABCELL_X1_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~12_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~12_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(4)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000000001010101010111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~0_combout\); + +-- Location: LABCELL_X20_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(4)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100111100001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~1_combout\); + +-- Location: LABCELL_X16_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~7_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~11_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111010000000001111101010111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~2_combout\); + +-- Location: LABCELL_X21_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~2_combout\); + +-- Location: LABCELL_X21_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~1_combout\); + +-- Location: LABCELL_X21_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~18_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~3_combout\); + +-- Location: LABCELL_X21_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011110011111100111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~0_combout\); + +-- Location: LABCELL_X21_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010000100010101111110111011000010101011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~4_combout\); + +-- Location: LABCELL_X17_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~0_combout\); + +-- Location: LABCELL_X16_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~49_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~49_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~49_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) +-- # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110110111100000111011011110000011101101111000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~49_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~3_combout\); + +-- Location: LABCELL_X14_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~2_combout\); + +-- Location: LABCELL_X17_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000100000000111011100000000011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~42_combout\); + +-- Location: LABCELL_X16_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000000001001110101010100100111101010100010011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\); + +-- Location: LABCELL_X14_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010000100010101111110111011000010101011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~21_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~30_combout\); + +-- Location: LABCELL_X16_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~23_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~30_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~23_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010000000100010001000011011101110111001101110111011100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~23_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~41_combout\); + +-- Location: LABCELL_X16_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001001000000011100100100000101110011010000010111001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~43_combout\); + +-- Location: LABCELL_X16_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~44_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~43_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~42_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~43_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~41_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~42_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~43_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~41_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~42_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101000001010111110100000101011111010111110100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~42_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~41_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~43_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~44_combout\); + +-- Location: LABCELL_X16_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~44_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~49_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~44_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add33~49_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001000000000000000000000001111000011000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~49_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~44_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~4_combout\); + +-- Location: LABCELL_X16_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111000001111000011100000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~5_combout\); + +-- Location: LABCELL_X24_Y35_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~7_combout\); + +-- Location: LABCELL_X24_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~8_combout\); + +-- Location: LABCELL_X24_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~6_combout\); + +-- Location: LABCELL_X24_Y35_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~5_combout\); + +-- Location: LABCELL_X24_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011010001110100011111001100111111110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~9_combout\); + +-- Location: MLABCELL_X23_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~0_combout\); + +-- Location: LABCELL_X24_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~3_combout\); + +-- Location: MLABCELL_X23_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~1_combout\); + +-- Location: MLABCELL_X23_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~2_combout\); + +-- Location: MLABCELL_X23_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ +-- & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001000110100010101100111000010011010101111001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~4_combout\); + +-- Location: LABCELL_X24_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~9_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10_combout\); + +-- Location: LABCELL_X21_Y27_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000101010101111000011001100110000001000100011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~1_combout\); + +-- Location: LABCELL_X16_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111010111110101111100011111010111110101111101011111000011110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~3_combout\); + +-- Location: FF_X16_Y25_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(4)); + +-- Location: LABCELL_X16_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(4) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(4) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\); + +-- Location: LABCELL_X12_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[4]_NEW3059\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[4]_OTERM3060\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(4) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[4]_OTERM3060\); + +-- Location: FF_X12_Y21_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[4]_OTERM3060\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(4)); + +-- Location: LABCELL_X12_Y23_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[4]_NEW3123\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[4]_OTERM3124\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[4]_OTERM3124\); + +-- Location: FF_X12_Y23_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[4]_OTERM3124\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(4)); + +-- Location: LABCELL_X10_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[4]_NEW2995\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[4]_OTERM2996\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010100111111111101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[4]_OTERM2996\); + +-- Location: FF_X10_Y21_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[4]_OTERM2996\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(4)); + +-- Location: LABCELL_X12_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[4]_NEW3187\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[4]_OTERM3188\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(4) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[4]_OTERM3188\); + +-- Location: FF_X12_Y21_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[4]_OTERM3188\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(4)); + +-- Location: LABCELL_X12_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(4) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(4) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(4) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(4) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~0_combout\); + +-- Location: LABCELL_X10_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[4]_NEW2931\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[4]_OTERM2932\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101000000111111010111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[4]_OTERM2932\); + +-- Location: FF_X10_Y21_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[4]_OTERM2932\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(4)); + +-- Location: LABCELL_X12_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[4]_NEW2739\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[4]_OTERM2740\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[4]_OTERM2740\); + +-- Location: FF_X12_Y21_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[4]_OTERM2740\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(4)); + +-- Location: MLABCELL_X9_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[4]_NEW2803\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[4]_OTERM2804\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(4))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[4]_OTERM2804\); + +-- Location: FF_X9_Y22_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[4]_OTERM2804\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(4)); + +-- Location: MLABCELL_X9_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[4]_NEW2867\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[4]_OTERM2868\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(4))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[4]_OTERM2868\); + +-- Location: FF_X9_Y22_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[4]_OTERM2868\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(4)); + +-- Location: LABCELL_X12_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(4) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(4)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(4)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(4)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011111101011111001100000101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~1_combout\); + +-- Location: LABCELL_X12_Y21_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\); + +-- Location: LABCELL_X10_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[4]~feeder_combout\); + +-- Location: FF_X10_Y15_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4)); + +-- Location: MLABCELL_X18_Y9_N21 +\myVirtualToplevel|SD_ADDR[0][4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + combout => \myVirtualToplevel|SD_ADDR[0][4]~feeder_combout\); + +-- Location: FF_X18_Y9_N23 +\myVirtualToplevel|SD_ADDR[0][4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][4]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][4]~DUPLICATE_q\); + +-- Location: FF_X24_Y8_N4 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3), + sload => VCC, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(4)); + +-- Location: MLABCELL_X18_Y9_N15 +\myVirtualToplevel|Mux79~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux79~0_combout\ = ( \myVirtualToplevel|SD_DATA_REQ~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|SD_ADDR[0][4]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(4)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))))) ) ) # ( !\myVirtualToplevel|SD_DATA_REQ~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|SD_ADDR[0][4]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(4)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000001100010001000000110001000100001111110100010000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_ADDR[0][4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + dataf => \myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\, + combout => \myVirtualToplevel|Mux79~0_combout\); + +-- Location: FF_X16_Y9_N23 +\myVirtualToplevel|IO_DATA_READ_SD[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux79~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(4)); + +-- Location: LABCELL_X20_Y13_N24 +\myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\ = ( !\myVirtualToplevel|MEM_DATA_READ[4]~90_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4~portbdataout\ & (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ +-- & (\myVirtualToplevel|IO_DATA_READ_SD\(4))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16_combout\)))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[4]~90_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12~portbdataout\)))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(4))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001000100001100110111010000110000010001001111111101110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(4), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~90_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]~16_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\); + +-- Location: LABCELL_X7_Y17_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ( \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~131_Duplicate_173\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~23_combout\); + +-- Location: FF_X7_Y17_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_NEW_REG570\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~23_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM571\); + +-- Location: FF_X7_Y17_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_NEW_REG566\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM567\); + +-- Location: LABCELL_X7_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~22_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\)) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ +-- & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010101001111110101010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~131_Duplicate_173\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~22_combout\); + +-- Location: FF_X7_Y17_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_NEW_REG568\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~22_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM569\); + +-- Location: LABCELL_X7_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM567\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM569\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM571\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM567\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM569\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM571\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM567\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM569\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM571\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM567\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM569\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM571\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000110011111101111100100000001100001110111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM571\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM567\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM569\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\); + +-- Location: LABCELL_X21_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~208\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~208_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~208_combout\); + +-- Location: FF_X21_Y34_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~208_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~DUPLICATE_q\); + +-- Location: FF_X21_Y34_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~209_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~DUPLICATE_q\); + +-- Location: LABCELL_X21_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\); + +-- Location: LABCELL_X21_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\)))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000011001001010100011101101001100010111010110111001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~19_combout\); + +-- Location: LABCELL_X21_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~4_combout\); + +-- Location: LABCELL_X21_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010001000100101111101110111000010100111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~9_combout\); + +-- Location: LABCELL_X21_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010010001101100111000010011100110110101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~14_combout\); + +-- Location: LABCELL_X21_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~19_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~14_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~9_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~4_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~19_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\); + +-- Location: LABCELL_X17_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\); + +-- Location: LABCELL_X10_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000000000000000000100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\); + +-- Location: LABCELL_X10_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8491\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8491_BDD8492\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111000000000000111111110000000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[25]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8491_BDD8492\); + +-- Location: LABCELL_X10_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8491_BDD8492\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489_BDD8490\))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8491_BDD8492\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489_BDD8490\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000011100110100010001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_RESYN8489_BDD8490\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[25]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_RESYN8491_BDD8492\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\); + +-- Location: MLABCELL_X9_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]_NEW2879\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]_OTERM2880\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]_OTERM2880\); + +-- Location: FF_X9_Y22_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]_OTERM2880\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(0)); + +-- Location: MLABCELL_X9_Y19_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[0]_NEW2751\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[0]_OTERM2752\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[0]_OTERM2752\); + +-- Location: FF_X9_Y19_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[0]_OTERM2752\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(0)); + +-- Location: MLABCELL_X9_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]_NEW2815\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]_OTERM2816\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]_OTERM2816\); + +-- Location: FF_X9_Y19_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]_OTERM2816\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(0)); + +-- Location: MLABCELL_X9_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[0]_NEW2943\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[0]_OTERM2944\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[0]_OTERM2944\); + +-- Location: FF_X9_Y19_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[0]_OTERM2944\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(0)); + +-- Location: MLABCELL_X9_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux87~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001000110000100110101011110001010110011101001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~1_combout\); + +-- Location: MLABCELL_X9_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]_NEW3199\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]_OTERM3200\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]_OTERM3200\); + +-- Location: FF_X9_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]_OTERM3200\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(0)); + +-- Location: MLABCELL_X9_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]_NEW3071\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]_OTERM3072\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]_OTERM3072\); + +-- Location: FF_X9_Y20_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]_OTERM3072\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(0)); + +-- Location: MLABCELL_X9_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]_NEW3135\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]_OTERM3136\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]_OTERM3136\); + +-- Location: FF_X9_Y19_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]_OTERM3136\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(0)); + +-- Location: MLABCELL_X9_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[0]_NEW3007\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[0]_OTERM3008\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[0]_OTERM3008\); + +-- Location: FF_X9_Y19_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[0]_OTERM3008\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(0)); + +-- Location: MLABCELL_X9_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux87~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(0) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(0)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(0)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(0)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001001100011100000111110001000011010011110111001101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~0_combout\); + +-- Location: MLABCELL_X9_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux87~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux87~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux87~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2_combout\); + +-- Location: MLABCELL_X9_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[0]_NEW3219\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[0]_OTERM3220\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & +-- ((\myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~2_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~95_Duplicate_161\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[0]_OTERM3220\); + +-- Location: FF_X9_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[0]_OTERM3220\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0)); + +-- Location: LABCELL_X24_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~324\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~324_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~324_combout\); + +-- Location: FF_X24_Y34_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~324_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~7_combout\); + +-- Location: LABCELL_X26_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001101110111011101100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~5_combout\); + +-- Location: LABCELL_X25_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~8_combout\); + +-- Location: FF_X25_Y34_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~313_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y36_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010010111110101111100010001101110110001000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~6_combout\); + +-- Location: LABCELL_X26_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~7_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~7_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010100010000001111010011101010010111100100101011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~9_combout\); + +-- Location: MLABCELL_X28_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~2_combout\); + +-- Location: MLABCELL_X28_Y34_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~3_combout\); + +-- Location: MLABCELL_X28_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~1_combout\); + +-- Location: MLABCELL_X28_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~0_combout\); + +-- Location: LABCELL_X26_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011100010011010101101000101011001111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~4_combout\); + +-- Location: LABCELL_X26_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~9_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10_combout\); + +-- Location: MLABCELL_X18_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~10_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010000000000000000000010000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~10_combout\); + +-- Location: MLABCELL_X18_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000011001100010000001100110000000000010000000000000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~24_combout\); + +-- Location: LABCELL_X21_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000001111000000000000000000000000000000001111000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~0_combout\); + +-- Location: LABCELL_X21_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000011111111010100001111111100000000010100000000000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~8_combout\); + +-- Location: LABCELL_X21_Y16_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000001010101000000000101001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\); + +-- Location: LABCELL_X21_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~8_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~8_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100100000001100000011001100110011001100100011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~9_combout\); + +-- Location: LABCELL_X21_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011101010101011101110101010100010001000000000001000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~7_combout\); + +-- Location: LABCELL_X21_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111010011110100111111011111110100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~10_combout\); + +-- Location: LABCELL_X20_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100110011111100111100001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~12_combout\); + +-- Location: LABCELL_X21_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~12_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~12_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001010111011101110111011101100100010001000100010001010111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~13_combout\); + +-- Location: LABCELL_X20_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000110000110000000011000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~5_combout\); + +-- Location: LABCELL_X20_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010101100101011001010110010101100100010001000100010001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~11_combout\); + +-- Location: LABCELL_X21_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000001000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~1_combout\); + +-- Location: LABCELL_X20_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ +-- $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000110000110000000011000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~2_combout\); + +-- Location: LABCELL_X21_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~1_combout\); + +-- Location: LABCELL_X20_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ +-- $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001111000011000000000000000000000000000000001100001111000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~4_combout\); + +-- Location: LABCELL_X21_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~5_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\); + +-- Location: LABCELL_X21_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3_combout\); + +-- Location: LABCELL_X20_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000000000000000000011111111111111110011000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~14_combout\); + +-- Location: LABCELL_X20_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000001010000101000000101000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~4_combout\); + +-- Location: LABCELL_X20_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~14_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~14_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~14_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~14_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001000100010101010111011101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~15_combout\); + +-- Location: LABCELL_X21_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~15_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~13_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~15_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~13_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~13_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~11_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~15_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000100010001111100000000111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~16_combout\); + +-- Location: LABCELL_X17_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111001100110011111101111111001100010000000000000011000100110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~17_combout\); + +-- Location: LABCELL_X19_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101010001110100011101000111010001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~18_combout\); + +-- Location: LABCELL_X21_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100111100000100110111110000110100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~19_combout\); + +-- Location: LABCELL_X20_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100110101001101010011010100110101000100010001000100010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~20_combout\); + +-- Location: LABCELL_X20_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~20_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~20_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~20_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~20_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010101000000010001010100000001010111111101010111011111110101011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~21_combout\); + +-- Location: LABCELL_X21_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~22_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~21_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~17_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~21_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100011001100000000000000000010000000110000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~21_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~22_combout\); + +-- Location: MLABCELL_X18_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000010000100001100001000010000100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0_combout\); + +-- Location: LABCELL_X17_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000010000000000001000010000000000000000100001000000000000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~2_combout\); + +-- Location: LABCELL_X21_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~16_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000000000000000000000000000001000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~16_combout\); + +-- Location: LABCELL_X21_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~17_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~16_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~23_combout\); + +-- Location: LABCELL_X21_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~23_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~24_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~16_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~22_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~23_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~24_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~23_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~24_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~23_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~24_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010001000100010001010101010101010100000000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~24_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~22_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~23_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~25_combout\); + +-- Location: MLABCELL_X18_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~46_combout\); + +-- Location: LABCELL_X19_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~46_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\)))) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~46_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~46_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~46_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011100010101001101101000110010101111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~46_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~47_combout\); + +-- Location: LABCELL_X19_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~13_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~47_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~47_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~47_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000000000000011000000000011000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~47_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~13_combout\); + +-- Location: MLABCELL_X18_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000000000100010000000000010000000000000001111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~22_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~12_combout\); + +-- Location: LABCELL_X19_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~12_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~13_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~12_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000100000001101010100000000000000001010000011110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~14_combout\); + +-- Location: LABCELL_X19_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~41_combout\); + +-- Location: LABCELL_X19_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~41_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~41_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~41_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\)) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~41_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100000000000100010000001111010011111111000011110100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~41_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~11_combout\); + +-- Location: LABCELL_X20_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~15_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~10_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~25_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111110001100000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~25_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~15_combout\); + +-- Location: LABCELL_X17_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~40_combout\); + +-- Location: LABCELL_X17_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~39_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~39_combout\); + +-- Location: LABCELL_X17_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~39_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~40_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~40_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~39_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~40_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100010001001100110001000100111011000111110011101100011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~40_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~39_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~8_combout\); + +-- Location: MLABCELL_X18_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\))) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000000000000001000000011000000110010001100000011001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~4_combout\); + +-- Location: LABCELL_X20_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101010101111101011110000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~10_combout\); + +-- Location: LABCELL_X21_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100000011000011110000000011111111000011110011111100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~11_combout\); + +-- Location: LABCELL_X21_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001110001010100001111010101110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~12_combout\); + +-- Location: LABCELL_X17_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000000000110111000000000011111111010000001111111111011100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~6_combout\); + +-- Location: LABCELL_X20_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~17_combout\); + +-- Location: LABCELL_X21_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000011110011111100110011000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~2_combout\); + +-- Location: LABCELL_X21_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111011111110011111100110100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~3_combout\); + +-- Location: LABCELL_X21_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000001000000010000000100010101110101011101010111010101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~1_combout\); + +-- Location: LABCELL_X21_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011111110101011101111111010101100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~4_combout\); + +-- Location: LABCELL_X20_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111001111000011111100111100000000000011000000000000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~13_combout\); + +-- Location: LABCELL_X19_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~13_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000000000110011000000110011001111110011001111111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~14_combout\); + +-- Location: LABCELL_X20_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~14_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100001101010000000000000000001101010011110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~15_combout\); + +-- Location: LABCELL_X19_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110011000000111111001100000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~7_combout\); + +-- Location: LABCELL_X20_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000000101000001010100010000000101000001010100010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~8_combout\); + +-- Location: LABCELL_X20_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010011110100111100000000000000000000010000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~5_combout\); + +-- Location: LABCELL_X20_Y17_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011000000000000101100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~9_combout\); + +-- Location: LABCELL_X20_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~17_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~12_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~17_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000000000111111000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~17_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~18_combout\); + +-- Location: LABCELL_X20_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000110000110000000011000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~3_combout\); + +-- Location: LABCELL_X20_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110000000000000000000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~5_combout\); + +-- Location: LABCELL_X20_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000010000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~6_combout\); + +-- Location: LABCELL_X20_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000000001100000000000000000000000011000000000000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~22_combout\); + +-- Location: LABCELL_X19_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~5_combout\); + +-- Location: LABCELL_X20_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~6_combout\); + +-- Location: LABCELL_X20_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~22_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~39_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~22_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~6_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~39_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110101111110101111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~39_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~22_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~7_combout\); + +-- Location: LABCELL_X20_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110011111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~9_combout\); + +-- Location: LABCELL_X25_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011000011110000000001010101001100110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~3_combout\); + +-- Location: LABCELL_X25_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111111110101010100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~0_combout\); + +-- Location: LABCELL_X25_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011010101010000000000001111001100110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~2_combout\); + +-- Location: LABCELL_X25_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011110011111100111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~1_combout\); + +-- Location: LABCELL_X25_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000101001100001111010100111111000001010011111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~4_combout\); + +-- Location: LABCELL_X20_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000001000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~3_combout\); + +-- Location: LABCELL_X20_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~15_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~16_combout\); + +-- Location: LABCELL_X20_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000101000000010000000100000001000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~1_combout\); + +-- Location: MLABCELL_X18_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~22_combout\); + +-- Location: LABCELL_X19_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011111100111111001100110011001100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~17_combout\); + +-- Location: LABCELL_X19_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8985\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8985_BDD8986\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~22_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~22_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~22_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~22_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011011101110111011100110011111111110111011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~22_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8985_BDD8986\); + +-- Location: LABCELL_X19_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add36~101\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~101_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000000011110000111111110000111100000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~101_combout\); + +-- Location: LABCELL_X19_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~20_combout\); + +-- Location: LABCELL_X19_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~101_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~98_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~98_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~20_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~101_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~20_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~20_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100101010001010100011111100000000001010100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~101_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~98_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~21_combout\); + +-- Location: LABCELL_X19_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ $ +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101100101011001010110010101100101011001010110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~18_combout\); + +-- Location: LABCELL_X19_Y28_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8987\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8987_BDD8988\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~18_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~21_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~18_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~18_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000111010011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8987_BDD8988\); + +-- Location: LABCELL_X20_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8987_BDD8988\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8987_BDD8988\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8985_BDD8986\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001000101010100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_RESYN8985_BDD8986\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_RESYN8987_BDD8988\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_combout\); + +-- Location: LABCELL_X21_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000001100000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~2_combout\); + +-- Location: FF_X2_Y33_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_NEW_REG1210\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211\); + +-- Location: FF_X2_Y33_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_NEW_REG1204\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~22_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1205\); + +-- Location: LABCELL_X2_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1205\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1205\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1205\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001111111111111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1209\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1205\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~22_combout\); + +-- Location: LABCELL_X2_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~22_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001101010111010101110101011101010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~0_combout\); + +-- Location: LABCELL_X5_Y22_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111110000111100001111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~1_combout\); + +-- Location: LABCELL_X21_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~2_combout\); + +-- Location: LABCELL_X20_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~16_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100100011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~4_combout\); + +-- Location: FF_X20_Y22_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~4_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(0)); + +-- Location: LABCELL_X19_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_40\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(0) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(0) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000000000000000000000111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_40\); + +-- Location: FF_X19_Y39_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1432\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_40\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\); + +-- Location: FF_X20_Y39_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_NEW_REG1600\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]~53_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1601\); + +-- Location: FF_X19_Y35_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_NEW_REG1602\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~51_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1603\); + +-- Location: LABCELL_X20_Y39_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1603\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1601\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1601\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1603\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1601\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1603\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1601\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1603\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1601\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1431\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1433\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]_OTERM1601\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1435\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]_OTERM1603\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]~53_combout\); + +-- Location: LABCELL_X19_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~54_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~54_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[0]~54_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~56_combout\); + +-- Location: FF_X19_Y35_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~56_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(0)); + +-- Location: FF_X19_Y39_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]_NEW_REG1618\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]~59_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]_OTERM1619\); + +-- Location: LABCELL_X19_Y39_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]~59_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1547\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]_OTERM1619\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1547\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1607\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]_OTERM1619\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1607\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]_OTERM1619\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000001111110110000000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1547\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1433\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]_OTERM1607\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[0]_OTERM1619\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]~59_combout\); + +-- Location: FF_X19_Y39_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_NEW_REG1544\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~58_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1545\); + +-- Location: LABCELL_X19_Y39_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~58_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1547\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1545\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1547\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1549\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1545\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1549\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1545\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000001111110110000000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1547\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1433\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1549\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1545\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~58_combout\); + +-- Location: LABCELL_X19_Y39_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~58_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]~53_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]~59_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(0) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]~53_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[0]~59_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]~58_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~0_combout\); + +-- Location: FF_X19_Y39_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1428\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]~58_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1429\); + +-- Location: LABCELL_X19_Y39_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]~58_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1429\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1437\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1429\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1437\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1429\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1437\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1433\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1435\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1431\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1429\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1437\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]~58_combout\); + +-- Location: FF_X19_Y39_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_NEW_REG1554\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]~56_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1555\); + +-- Location: LABCELL_X19_Y39_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1555\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1557\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1555\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1557\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1555\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1557\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1433\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1431\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1435\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]_OTERM1555\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]_OTERM1557\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]~56_combout\); + +-- Location: FF_X19_Y39_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_NEW_REG1478\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~65_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1479\); + +-- Location: LABCELL_X19_Y39_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~65_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1479\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1481\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1479\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1481\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1479\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1481\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1433\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1431\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1435\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]_OTERM1479\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]_OTERM1481\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~65_combout\); + +-- Location: FF_X19_Y39_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_NEW_REG1550\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]~54_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1551\); + +-- Location: LABCELL_X19_Y39_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1551\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1553\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1551\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1553\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1551\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1553\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1433\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1431\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1435\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]_OTERM1551\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]_OTERM1553\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]~54_combout\); + +-- Location: LABCELL_X19_Y39_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]~54_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]~58_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]~56_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]~54_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]~58_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]~56_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]~54_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~65_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]~54_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~65_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]~58_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]~56_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~65_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]~54_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~1_combout\); + +-- Location: LABCELL_X16_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010110101010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\); + +-- Location: LABCELL_X12_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000000000000011000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~95_Duplicate_161\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~18_combout\); + +-- Location: LABCELL_X12_Y16_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~18_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001010000000000000101000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~19_combout\); + +-- Location: FF_X12_Y16_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG690\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~19_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM691\); + +-- Location: FF_X12_Y16_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG688\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~18_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM689\); + +-- Location: FF_X10_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG684\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM685\); + +-- Location: LABCELL_X10_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM685\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM683\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM691\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM689\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM685\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM683\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM689\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM691\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM685\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM683\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM691\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM689\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM687\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM685\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM683\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM687\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM689\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM691\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001000110111111101110100001111000011001100111111001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM687\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM691\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM689\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM685\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM683\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\); + +-- Location: LABCELL_X7_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_WREN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_WREN~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010111111100010001011111110001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_WREN~0_combout\); + +-- Location: MLABCELL_X23_Y35_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~262\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~262_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~262_combout\); + +-- Location: FF_X23_Y35_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~262_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~q\); + +-- Location: MLABCELL_X23_Y35_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\); + +-- Location: MLABCELL_X23_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001010010000001110101011110100010111100101010011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\); + +-- Location: MLABCELL_X28_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000001100011101110000110001000100001111110111011100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4_combout\); + +-- Location: LABCELL_X26_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000110010101110100101010011011100011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~17_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19_combout\); + +-- Location: MLABCELL_X28_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100000011000111011100111111010001000011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9_combout\); + +-- Location: LABCELL_X17_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000101011001110100100110101011100011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\); + +-- Location: LABCELL_X17_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\); + +-- Location: LABCELL_X10_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\); + +-- Location: LABCELL_X16_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000000000000010000000000000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\); + +-- Location: LABCELL_X16_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101011111010111001010000010100011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~1_combout\); + +-- Location: MLABCELL_X18_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~3_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~3_combout\); + +-- Location: LABCELL_X16_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000011110000111110001101100011011000111110001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~2_combout\); + +-- Location: LABCELL_X16_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000000000000000000110000000000000000000000101000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~4_combout\); + +-- Location: LABCELL_X16_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~4_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~5_combout\); + +-- Location: LABCELL_X14_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ $ +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101001111100010000110011100011100000010110001101001101100100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~6_combout\); + +-- Location: LABCELL_X16_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011011100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~7_combout\); + +-- Location: LABCELL_X16_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~5_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0011000100110001000000000001001100110001001100010000001100010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~7_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9_combout\); + +-- Location: LABCELL_X16_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]_NEW2687\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]_OTERM2688\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]_OTERM2688\); + +-- Location: FF_X16_Y30_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]_OTERM2688\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)); + +-- Location: MLABCELL_X18_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\); + +-- Location: LABCELL_X5_Y36_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000001111110011100000111111001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~1_combout\); + +-- Location: LABCELL_X5_Y36_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~0_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000000110011000000000011001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~0_combout\); + +-- Location: LABCELL_X5_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110001000000110011000000000011001100010001001100110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1115~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1115~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~2_combout\); + +-- Location: FF_X5_Y36_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_NEW_REG1488\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1489\); + +-- Location: LABCELL_X12_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010000010000000010100000000000001000000100000000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\); + +-- Location: LABCELL_X7_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector566~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000000000000010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~3_combout\); + +-- Location: LABCELL_X7_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector566~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector566~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector566~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111111101010100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~4_combout\); + +-- Location: FF_X7_Y34_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_NEW_REG1492\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1493\); + +-- Location: MLABCELL_X9_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\); + +-- Location: MLABCELL_X9_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector566~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110011111111110011001111111111001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~0_combout\); + +-- Location: MLABCELL_X9_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector566~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector566~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector566~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000010100000001000001010000000110000111100000011000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~51_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~1_combout\); + +-- Location: MLABCELL_X9_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector566~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010001000000000001000100000000000101010100000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[25]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~2_combout\); + +-- Location: FF_X9_Y33_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_NEW_REG1490\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1491\); + +-- Location: LABCELL_X5_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1489\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1493\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1491\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1489\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101110011001100110001010101010101011111110111111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1489\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1493\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1491\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\); + +-- Location: FF_X5_Y34_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_NEW_REG1498\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\); + +-- Location: MLABCELL_X9_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector500~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101011111111101010101111111110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~0_combout\); + +-- Location: MLABCELL_X9_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector500~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector500~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001110101111001000111010111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector500~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~1_combout\); + +-- Location: MLABCELL_X9_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector500~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector500~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~2_combout\); + +-- Location: FF_X9_Y33_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_NEW_REG1500\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1501\); + +-- Location: LABCELL_X6_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector500~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000011101000111000001110100011100110111011101110000011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~3_combout\); + +-- Location: FF_X6_Y36_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_NEW_REG1504\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1505\); + +-- Location: LABCELL_X5_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~0_combout\); + +-- Location: LABCELL_X5_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000001100111111100000110011111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~1_combout\); + +-- Location: LABCELL_X5_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000000000111011000000000011001100000000001110111000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1083~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1083~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~2_combout\); + +-- Location: FF_X5_Y36_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_NEW_REG1502\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\); + +-- Location: LABCELL_X5_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1501\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1505\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010111111111010101010000000001010101111111110101010101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1501\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1505\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\); + +-- Location: LABCELL_X5_Y36_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~0_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101000001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~0_combout\); + +-- Location: LABCELL_X5_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010001000100111111100100010011111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~1_combout\); + +-- Location: LABCELL_X5_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~1_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000000010000000000011111111000000000000110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1147~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1147~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~2_combout\); + +-- Location: FF_X5_Y36_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_NEW_REG1416\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\); + +-- Location: LABCELL_X6_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector632~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000011110000001101110011011100110111111101110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~3_combout\); + +-- Location: FF_X6_Y34_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_NEW_REG1418\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1419\); + +-- Location: MLABCELL_X9_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector632~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000011111111111100001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~0_combout\); + +-- Location: MLABCELL_X9_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector632~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector632~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010101000111111001010100011111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~54_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector632~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~1_combout\); + +-- Location: MLABCELL_X9_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector632~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010001010100010101000101010001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector632~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~2_combout\); + +-- Location: FF_X9_Y33_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_NEW_REG1414\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\); + +-- Location: FF_X5_Y34_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_NEW_REG1412\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\); + +-- Location: LABCELL_X5_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1419\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1419\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1419\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010001010100000101000111111011111110111111101011111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1419\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\); + +-- Location: LABCELL_X6_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector698~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010101010101000001010000010100101111011111110010111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~3_combout\); + +-- Location: FF_X6_Y36_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_NEW_REG1394\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1395\); + +-- Location: LABCELL_X12_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~0_combout\); + +-- Location: LABCELL_X6_Y36_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111111111000000101111111100000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~1_combout\); + +-- Location: LABCELL_X6_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000001000000000000000100000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1179~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~2_combout\); + +-- Location: FF_X6_Y36_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_NEW_REG1396\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\); + +-- Location: MLABCELL_X9_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector698~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001010000011110000101010101111101010101010111110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~0_combout\); + +-- Location: MLABCELL_X9_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector698~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector698~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector698~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001100000000001000110000000010101111000000001010111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~44_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector698~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~1_combout\); + +-- Location: MLABCELL_X9_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector698~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector698~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector698~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000000000000011000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector698~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~2_combout\); + +-- Location: FF_X9_Y33_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_NEW_REG1392\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\); + +-- Location: FF_X6_Y36_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_NEW_REG1390\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\); + +-- Location: LABCELL_X6_Y36_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1395\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1395\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1395\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001101000000001100110111111111110011111111111111001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1395\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\); + +-- Location: LABCELL_X5_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux2~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100001101001111010000000111110001110011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~1_combout\); + +-- Location: FF_X6_Y34_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\); + +-- Location: LABCELL_X6_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100001111000000110000001101110011011111110111001101110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READNOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~5_combout\); + +-- Location: LABCELL_X6_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8495\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8495_BDD8496\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100110011000001010000000100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~40_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8495_BDD8496\); + +-- Location: LABCELL_X6_Y34_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8497\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8497_BDD8498\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8497_BDD8498\); + +-- Location: LABCELL_X6_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8497_BDD8498\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8495_BDD8496\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8497_BDD8498\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8495_BDD8496\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000110000111100000000000000000000000100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_RESYN8495_BDD8496\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_RESYN8497_BDD8498\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_combout\); + +-- Location: LABCELL_X6_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~1_combout\); + +-- Location: LABCELL_X6_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000111111001111110011001000110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~2_combout\); + +-- Location: LABCELL_X6_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110011001100000000000000000011011101110011000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~3_combout\); + +-- Location: LABCELL_X6_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~5_combout\)))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~3_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111111111111111111100000001000000011111001111110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READNOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~0_combout\); + +-- Location: FF_X6_Y34_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\); + +-- Location: LABCELL_X5_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011011100110111001101110011011100000101000001000000010100000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~1_combout\); + +-- Location: LABCELL_X5_Y36_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~0_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~0_combout\); + +-- Location: LABCELL_X5_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000111000001100000011000000110000001111000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1275~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1275~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~2_combout\); + +-- Location: FF_X5_Y36_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_NEW_REG1512\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\); + +-- Location: LABCELL_X5_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector896~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001001100010011000101010101110111010111010111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~3_combout\); + +-- Location: FF_X5_Y34_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_NEW_REG1510\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1511\); + +-- Location: LABCELL_X6_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector896~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110000001100110011000011111111001100001111111100110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~0_combout\); + +-- Location: LABCELL_X6_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector896~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector896~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector896~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001010000010000000101000011000000111100001100000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector896~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~47_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~1_combout\); + +-- Location: LABCELL_X6_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector896~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101111000000001010111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector896~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~2_combout\); + +-- Location: FF_X6_Y34_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_NEW_REG1508\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\); + +-- Location: FF_X5_Y34_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_NEW_REG1506\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\); + +-- Location: LABCELL_X5_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1511\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1511\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1511\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101011000000001010101111111111101110111111111110101011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1511\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\); + +-- Location: LABCELL_X6_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector962~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111100000000001111110011001100111111001100110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~0_combout\); + +-- Location: LABCELL_X6_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector962~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector962~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100010101001111110001010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector962~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~1_combout\); + +-- Location: LABCELL_X6_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector962~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000111100001010000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector962~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~2_combout\); + +-- Location: FF_X6_Y34_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_NEW_REG1456\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1457\); + +-- Location: LABCELL_X5_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector962~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000101010101000000000101010100011011111111110000101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~3_combout\); + +-- Location: FF_X5_Y34_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_NEW_REG1458\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1459\); + +-- Location: LABCELL_X5_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010001001111010011100100111101001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~1_combout\); + +-- Location: LABCELL_X5_Y36_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~0_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101000001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~0_combout\); + +-- Location: LABCELL_X5_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000111000001100000011000000110000001111000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1307~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1307~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~2_combout\); + +-- Location: FF_X5_Y36_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_NEW_REG1460\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1461\); + +-- Location: FF_X5_Y34_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_NEW_REG1454\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1455\); + +-- Location: LABCELL_X5_Y34_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1455\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1461\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1457\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1459\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1455\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1455\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1461\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1459\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000001111111111111111111111111100001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1457\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1459\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1461\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1455\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\); + +-- Location: LABCELL_X6_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector830~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010101010101000001010000010100101111011111110010111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~3_combout\); + +-- Location: FF_X6_Y36_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_NEW_REG1594\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1595\); + +-- Location: LABCELL_X6_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111111111000000101111111100000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~4_combout\); + +-- Location: LABCELL_X6_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~3_combout\); + +-- Location: LABCELL_X6_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~4_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~4_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101000001000000000000000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~5_combout\); + +-- Location: FF_X6_Y36_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_NEW_REG1590\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\); + +-- Location: LABCELL_X7_Y37_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector830~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111001111110011001100110011001111110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~0_combout\); + +-- Location: LABCELL_X7_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector830~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector830~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector830~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010101000101110011111100111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~41_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector830~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~1_combout\); + +-- Location: LABCELL_X7_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector830~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[26]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector830~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~2_combout\); + +-- Location: FF_X7_Y37_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_NEW_REG1592\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1593\); + +-- Location: FF_X6_Y36_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_NEW_REG1588\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\); + +-- Location: LABCELL_X6_Y36_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1593\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1595\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1595\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001101110111111111110011001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1595\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1593\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\); + +-- Location: LABCELL_X5_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux2~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001110011001101000111110011000100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~0_combout\); + +-- Location: LABCELL_X5_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux2~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux2~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~0_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux2~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~2_combout\); + +-- Location: FF_X9_Y32_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_NEW_REG1296\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1297\); + +-- Location: FF_X9_Y32_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\); + +-- Location: FF_X9_Y32_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_NEW_REG1300\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1301\); + +-- Location: MLABCELL_X9_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\); + +-- Location: MLABCELL_X9_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100000000000100010000000000011111111000000001000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~0_combout\); + +-- Location: LABCELL_X12_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector631~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100001111010111110000111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~54_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~38_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~0_combout\); + +-- Location: LABCELL_X12_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector631~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector631~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111111111111110011111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~1_combout\); + +-- Location: LABCELL_X12_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12404\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12404_BDD12405\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111011101111111011111110111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12404_BDD12405\); + +-- Location: MLABCELL_X13_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\); + +-- Location: MLABCELL_X13_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12402\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12402_BDD12403\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000111111111111111100000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~54_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12402_BDD12403\); + +-- Location: LABCELL_X12_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12402_BDD12403\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12402_BDD12403\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12402_BDD12403\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12404_BDD12405\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12402_BDD12403\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12404_BDD12405\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011010000111100000101000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_RESYN12404_BDD12405\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~59_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_RESYN12402_BDD12403\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_combout\); + +-- Location: LABCELL_X12_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector631~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~0_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000100110001001100010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~1_combout\); + +-- Location: FF_X12_Y35_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_NEW_REG1302\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1303\); + +-- Location: MLABCELL_X9_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1301\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1303\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1297\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1301\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1303\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1297\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101011111010101011111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1297\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1301\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1303\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\); + +-- Location: LABCELL_X6_Y35_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~0_combout\); + +-- Location: FF_X6_Y35_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_NEW_REG1464\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1465\); + +-- Location: LABCELL_X6_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111000001110000010100000101000001110011011100110101000101010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~1_combout\); + +-- Location: FF_X6_Y35_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_NEW_REG1466\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1467\); + +-- Location: FF_X9_Y35_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_NEW_REG1462\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1463\); + +-- Location: MLABCELL_X13_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12408\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12408_BDD12409\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000110000001100000010000000100000001000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12408_BDD12409\); + +-- Location: LABCELL_X14_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12406\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12406_BDD12407\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111010100000000111101010000000011110101111101011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~44_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12406_BDD12407\); + +-- Location: LABCELL_X14_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12408_BDD12409\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12406_BDD12407\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12408_BDD12409\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12406_BDD12407\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000100000000000100010000000000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_RESYN12408_BDD12409\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_RESYN12406_BDD12407\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~59_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_combout\); + +-- Location: LABCELL_X14_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector697~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~44_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~36_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~3_combout\); + +-- Location: LABCELL_X24_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN12632\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN12632_BDD12633\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000000000000000000010101010000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~37_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~29_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN12632_BDD12633\); + +-- Location: LABCELL_X24_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN12632_BDD12633\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~21_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~13_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~25_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_RESYN12632_BDD12633\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\); + +-- Location: LABCELL_X17_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879_BDD8880\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879_BDD8880\); + +-- Location: LABCELL_X17_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879_BDD8880\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879_BDD8880\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\); + +-- Location: LABCELL_X14_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector697~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011010000110000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~3_combout\); + +-- Location: FF_X14_Y35_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_NEW_REG1468\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1469\); + +-- Location: MLABCELL_X9_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1463\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1469\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1463\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1469\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1465\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1467\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000000010111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1465\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1467\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1463\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1469\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4_combout\); + +-- Location: FF_X12_Y32_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_NEW_REG1514\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1515\); + +-- Location: LABCELL_X12_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517~feeder_combout\); + +-- Location: FF_X12_Y32_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_NEW_REG1516\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517\); + +-- Location: LABCELL_X5_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110011001100000011001100110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~1_combout\); + +-- Location: MLABCELL_X13_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100110011000000000011111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~1_combout\); + +-- Location: LABCELL_X14_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000001011111010111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~5_combout\); + +-- Location: LABCELL_X12_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12412\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12412_BDD12413\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010000010101010101000011111111111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12412_BDD12413\); + +-- Location: MLABCELL_X13_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12410\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12410_BDD12411\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110011111111000011001111111100001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12410_BDD12411\); + +-- Location: MLABCELL_X13_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12410_BDD12411\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12410_BDD12411\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12410_BDD12411\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12412_BDD12413\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12410_BDD12411\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12412_BDD12413\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011000100110001001100010011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_RESYN12412_BDD12413\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~59_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_RESYN12410_BDD12411\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_combout\); + +-- Location: MLABCELL_X13_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000001111010100000000010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~2_combout\); + +-- Location: FF_X13_Y33_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_NEW_REG1518\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1519\); + +-- Location: LABCELL_X12_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1519\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1515\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1519\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1515\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000000000000000111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1515\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1519\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\); + +-- Location: FF_X9_Y32_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_NEW_REG1576\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1577\); + +-- Location: FF_X9_Y32_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_NEW_REG1574\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\); + +-- Location: MLABCELL_X13_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector565~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100001111001111110000111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~51_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~0_combout\); + +-- Location: LABCELL_X12_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector565~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010111011101010101011101100000000001100110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~2_combout\); + +-- Location: LABCELL_X14_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000011111111001100001111111100010000000100010001000000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0_combout\); + +-- Location: MLABCELL_X9_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414_BDD12415\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100001010000010101111111100001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~51_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414_BDD12415\); + +-- Location: MLABCELL_X9_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416_BDD12417\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector565~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414_BDD12415\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector565~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414_BDD12415\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101111111111111110111111111111111010111111111111101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~59_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector565~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414_BDD12415\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416_BDD12417\); + +-- Location: MLABCELL_X9_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\); + +-- Location: MLABCELL_X9_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416_BDD12417\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector565~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011111000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector565~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416_BDD12417\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_combout\); + +-- Location: FF_X9_Y32_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_NEW_REG1578\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\); + +-- Location: FF_X9_Y32_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_NEW_REG1298\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\); + +-- Location: MLABCELL_X9_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1577\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1577\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101110111001100000111000000110011111111110011000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1577\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2_combout\); + +-- Location: MLABCELL_X9_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111011000010101011101100010101010110110000000000011011000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~1_combout\); + +-- Location: LABCELL_X12_Y36_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_RESYN8493\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_RESYN8493_BDD8494\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111101010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_RESYN8493_BDD8494\); + +-- Location: LABCELL_X12_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_RESYN8493_BDD8494\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_RESYN8493_BDD8494\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_RESYN8493_BDD8494\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_RESYN8493_BDD8494\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001100110000000000101011110000000010001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~4_RESYN8493_BDD8494\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~41_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_combout\); + +-- Location: LABCELL_X12_Y36_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector829~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011011101110011001101110100000000010100000000000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~0_combout\); + +-- Location: LABCELL_X12_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector829~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001101110000000000110010000000000011011000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~1_combout\); + +-- Location: LABCELL_X12_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector829~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector829~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector829~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector829~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector829~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010000000000000101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~41_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~59_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~2_combout\); + +-- Location: LABCELL_X10_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011101100000000001110110000000000111011000010110011101100001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~0_combout\); + +-- Location: LABCELL_X12_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector829~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000000000101010100000000011101110111011001110111011101100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~1_combout\); + +-- Location: LABCELL_X12_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000011100000111111111111111111100000111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~2_combout\); + +-- Location: FF_X12_Y36_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\); + +-- Location: LABCELL_X14_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2_combout\); + +-- Location: LABCELL_X14_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100011001000100010001100100000000000110000000000000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~1_combout\); + +-- Location: LABCELL_X16_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12396\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12396_BDD12397\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111101000000001111110111111100111111011111110011111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12396_BDD12397\); + +-- Location: LABCELL_X14_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12394\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12394_BDD12395\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010111110101010101011111010100000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~40_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12394_BDD12395\); + +-- Location: LABCELL_X16_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12394_BDD12395\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12394_BDD12395\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12394_BDD12395\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12396_BDD12397\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12394_BDD12395\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12396_BDD12397\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111100000000110011110000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~59_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_RESYN12396_BDD12397\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_RESYN12394_BDD12395\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_combout\); + +-- Location: LABCELL_X16_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100001111001111110000111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~40_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~24_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~0_combout\); + +-- Location: LABCELL_X16_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000001010101010100000101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~1_combout\); + +-- Location: LABCELL_X16_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~1_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector763~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100001111000011110000001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~2_combout\); + +-- Location: FF_X16_Y31_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_NEW_REG1612\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1613\); + +-- Location: FF_X13_Y32_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_NEW_REG1608\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1609\); + +-- Location: FF_X13_Y32_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_NEW_REG1610\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1611\); + +-- Location: MLABCELL_X13_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1613\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1611\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1609\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1613\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1609\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001000100010001000101010101010100010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1613\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1609\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1611\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\); + +-- Location: FF_X9_Y32_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_NEW_REG1440\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1441\); + +-- Location: FF_X9_Y32_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_NEW_REG1438\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1439\); + +-- Location: MLABCELL_X13_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector895~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100001111010111110000111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~47_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~0_combout\); + +-- Location: MLABCELL_X13_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector895~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector895~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector895~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010101010101000001010101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~1_combout\); + +-- Location: MLABCELL_X9_Y36_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100000000000100010000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\); + +-- Location: MLABCELL_X13_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011001100000000101100110000000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~0_combout\); + +-- Location: LABCELL_X16_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector895~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000101000001010000010110011101100001011001110110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~2_combout\); + +-- Location: MLABCELL_X13_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector895~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector895~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector895~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010001000000000101000100000000111100110000000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~47_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~3_combout\); + +-- Location: MLABCELL_X13_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector895~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector895~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector895~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100000000000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~59_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~4_combout\); + +-- Location: MLABCELL_X13_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector895~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector895~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010101000101000001010100010100000101010101010000010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~1_combout\); + +-- Location: FF_X13_Y32_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_NEW_REG1442\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1443\); + +-- Location: MLABCELL_X9_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1443\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1441\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1439\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000011111111111000001111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1441\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1439\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1443\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\); + +-- Location: LABCELL_X10_Y36_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011101100000000001110110000000000111011000010110011101100001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~0_combout\); + +-- Location: LABCELL_X12_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12398\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12398_BDD12399\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000011110000111100000000010001000000000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12398_BDD12399\); + +-- Location: LABCELL_X12_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12400\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12400_BDD12401\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011011101110011001101110111000000110100001100000011010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12400_BDD12401\); + +-- Location: LABCELL_X12_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12400_BDD12401\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12398_BDD12399\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12400_BDD12401\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12398_BDD12399\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\)) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000100011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_RESYN12398_BDD12399\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~59_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_RESYN12400_BDD12401\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_combout\); + +-- Location: LABCELL_X12_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector961~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000100011111000111110001111100011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~0_combout\); + +-- Location: LABCELL_X12_Y36_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector961~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector961~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111010111111111111101011111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~1_combout\); + +-- Location: LABCELL_X12_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector961~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100010001000100010001000100011111111101010001111111110101000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~1_combout\); + +-- Location: FF_X12_Y36_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_NEW_REG1524\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\); + +-- Location: FF_X9_Y32_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_NEW_REG1520\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\); + +-- Location: FF_X9_Y32_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_NEW_REG1522\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\); + +-- Location: MLABCELL_X9_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000100111111111100110001010101010001001111111111001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\); + +-- Location: MLABCELL_X9_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111100101111111000110010001111101100001011001110000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~0_combout\); + +-- Location: MLABCELL_X9_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux1~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux1~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux1~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux1~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~2_combout\); + +-- Location: LABCELL_X17_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585_BDD8586\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000100000000001100010000000011110101000000001111010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585_BDD8586\); + +-- Location: LABCELL_X17_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585_BDD8586\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000001110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585_BDD8586\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\); + +-- Location: LABCELL_X17_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111111111110100111100000000000000001111111101000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~1_combout\); + +-- Location: FF_X17_Y34_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\); + +-- Location: FF_X13_Y34_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\); + +-- Location: MLABCELL_X13_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_RESYN8587\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_RESYN8587_BDD8588\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011100000111011101110000011100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_RESYN8587_BDD8588\); + +-- Location: MLABCELL_X13_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_RESYN8587_BDD8588\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ +-- & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_RESYN8587_BDD8588\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_RESYN8587_BDD8588\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000001011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector501~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector507~1_RESYN8587_BDD8588\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_combout\); + +-- Location: MLABCELL_X13_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111111110010001100000000000000001111111100100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector507~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~1_combout\); + +-- Location: FF_X13_Y34_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\); + +-- Location: FF_X17_Y35_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\); + +-- Location: LABCELL_X17_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_RESYN8589\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_RESYN8589_BDD8590\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111101010000000011110101000000001111010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_RESYN8589_BDD8590\); + +-- Location: LABCELL_X17_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_RESYN8589_BDD8590\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ +-- & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_RESYN8589_BDD8590\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_RESYN8589_BDD8590\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000001001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector573~1_RESYN8589_BDD8590\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_combout\); + +-- Location: LABCELL_X17_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111101001111010100000000000000001111010011110100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector573~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~1_combout\); + +-- Location: FF_X17_Y35_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\); + +-- Location: FF_X16_Y34_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\); + +-- Location: LABCELL_X16_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_RESYN8583\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_RESYN8583_BDD8584\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011101100000000001110110000000010111011000000001011101100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_RESYN8583_BDD8584\); + +-- Location: LABCELL_X16_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_RESYN8583_BDD8584\ +-- & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000001001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector639~1_RESYN8583_BDD8584\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_combout\); + +-- Location: LABCELL_X16_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111111110000101100000000000000001111111100001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector639~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~0_combout\); + +-- Location: FF_X16_Y34_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux9~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~1_combout\); + +-- Location: FF_X16_Y35_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\); + +-- Location: LABCELL_X16_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_RESYN8571\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_RESYN8571_BDD8572\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001110111000001110111011100000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_RESYN8571_BDD8572\); + +-- Location: LABCELL_X16_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_RESYN8571_BDD8572\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_RESYN8571_BDD8572\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000111000000000000001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector771~2_RESYN8571_BDD8572\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_combout\); + +-- Location: LABCELL_X16_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111101001111010100000000000000001111010011110100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector771~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~1_combout\); + +-- Location: FF_X16_Y35_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\); + +-- Location: FF_X13_Y38_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\); + +-- Location: MLABCELL_X13_Y38_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000111110011010100011111001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\); + +-- Location: MLABCELL_X13_Y38_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\); + +-- Location: MLABCELL_X13_Y38_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111100101111001100000000000000001111001011110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~1_combout\); + +-- Location: FF_X13_Y38_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575_BDD8576\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111100010011010111110001001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575_BDD8576\); + +-- Location: LABCELL_X14_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575_BDD8576\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575_BDD8576\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000001110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575_BDD8576\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\); + +-- Location: LABCELL_X14_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001111111110101000100000000000000001111111101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~1_combout\); + +-- Location: FF_X14_Y34_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\); + +-- Location: MLABCELL_X13_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000000000000000001111110000000001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\); + +-- Location: MLABCELL_X13_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664_BDD12665\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111110100010101000101010001010100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664_BDD12665\); + +-- Location: MLABCELL_X13_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010101000000000001010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\); + +-- Location: MLABCELL_X13_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011111111110000001111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\); + +-- Location: MLABCELL_X13_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\ & !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101110011011100110111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\); + +-- Location: MLABCELL_X13_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664_BDD12665\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110101010101010101011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664_BDD12665\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_combout\); + +-- Location: FF_X13_Y34_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\); + +-- Location: LABCELL_X14_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux9~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~0_combout\); + +-- Location: MLABCELL_X13_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux9~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux9~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux9~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~2_combout\); + +-- Location: LABCELL_X17_Y37_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189_BDD9190\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000011011100010100001101110001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector568~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189_BDD9190\); + +-- Location: LABCELL_X5_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100100011001000110000001111000011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~3_combout\); + +-- Location: MLABCELL_X9_Y37_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000100010001000100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~4_combout\); + +-- Location: FF_X17_Y37_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~q\); + +-- Location: LABCELL_X17_Y37_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector567~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100110101001111110011010100111010000000000011101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~1_combout\); + +-- Location: LABCELL_X16_Y37_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\); + +-- Location: LABCELL_X17_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector567~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000011111111001100001111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\); + +-- Location: LABCELL_X17_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195_BDD9196\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~56_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195_BDD9196\); + +-- Location: LABCELL_X12_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883_BDD8884\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101000001010000000000000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883_BDD8884\); + +-- Location: LABCELL_X16_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883_BDD8884\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883_BDD8884\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001100111000000000000000000000000011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883_BDD8884\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\); + +-- Location: LABCELL_X17_Y37_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_RESYN12642\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_RESYN12642_BDD12643\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110101010101011111010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_RESYN12642_BDD12643\); + +-- Location: LABCELL_X16_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_RESYN12642_BDD12643\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_RESYN12642_BDD12643\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010100010001000000000000000001010000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~8_RESYN12642_BDD12643\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_combout\); + +-- Location: LABCELL_X17_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193_BDD9194\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193_BDD9194\); + +-- Location: LABCELL_X17_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193_BDD9194\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195_BDD9196\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193_BDD9194\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195_BDD9196\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111010100001111111101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195_BDD9196\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193_BDD9194\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\); + +-- Location: LABCELL_X17_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\ ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189_BDD9190\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111111000100011111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189_BDD9190\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_combout\); + +-- Location: FF_X17_Y37_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y37_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010101001100000101010100110000011101010011000001110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\); + +-- Location: LABCELL_X12_Y37_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000001111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\); + +-- Location: FF_X17_Y37_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\); + +-- Location: LABCELL_X17_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector699~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111111111000000011110111100010000111111100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~1_combout\); + +-- Location: LABCELL_X17_Y37_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~1_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector699~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000011001100010100001100110011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\); + +-- Location: LABCELL_X17_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011111111111100001111110111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\); + +-- Location: LABCELL_X17_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111110011111110111100001111000011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_combout\); + +-- Location: FF_X17_Y37_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y36_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001010100000101000111110000111101010101010101010101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~1_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\); + +-- Location: FF_X13_Y36_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~q\); + +-- Location: LABCELL_X10_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527_BDD8528\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100000000011100010000000111110111011000000111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527_BDD8528\); + +-- Location: MLABCELL_X13_Y36_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529_BDD8530\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527_BDD8528\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\) +-- # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110100111111001111010011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527_BDD8528\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529_BDD8530\); + +-- Location: MLABCELL_X13_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529_BDD8530\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529_BDD8530\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000011100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector501~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529_BDD8530\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\); + +-- Location: MLABCELL_X13_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000101010101111100011111010100010001000100011111000111110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~1_combout\); + +-- Location: FF_X13_Y36_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y37_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000110011000000000011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\); + +-- Location: MLABCELL_X9_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111110100010001001111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\); + +-- Location: LABCELL_X10_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000011110000111100000101000001010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\); + +-- Location: MLABCELL_X9_Y37_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011011100111111001100100011101000110111001101010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~2_combout\); + +-- Location: LABCELL_X10_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011110000110000001111000001000000011100000100000001110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~3_combout\); + +-- Location: LABCELL_X10_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111111111000011111111111111101111111111111010111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\); + +-- Location: LABCELL_X10_Y37_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111101010101111111110101010111111111111101011111111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\); + +-- Location: LABCELL_X10_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010101000101111111110100010101000101010001011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_combout\); + +-- Location: FF_X10_Y37_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\); + +-- Location: LABCELL_X12_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux3~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~1_combout\); + +-- Location: LABCELL_X12_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101000111110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\); + +-- Location: MLABCELL_X13_Y37_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011000000000000001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~1_combout\); + +-- Location: MLABCELL_X13_Y37_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010111111111010101011111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\); + +-- Location: LABCELL_X12_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111101111111001111110010101000001100010111010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~3_combout\); + +-- Location: MLABCELL_X13_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513_BDD8514\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~3_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~3_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111001011111111011100101111111101110000111111110111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513_BDD8514\); + +-- Location: MLABCELL_X13_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513_BDD8514\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513_BDD8514\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111110001111111111111111111100001111110011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513_BDD8514\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\); + +-- Location: MLABCELL_X13_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000110011111110111100001111111111111100111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_combout\); + +-- Location: FF_X13_Y37_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\); + +-- Location: LABCELL_X12_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\)))) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000101001001110000010100110111000001010011011100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~2_combout\); + +-- Location: MLABCELL_X13_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011000000111100001100000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\); + +-- Location: LABCELL_X12_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101110111001100110111001000110011001001110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~1_combout\); + +-- Location: MLABCELL_X13_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000101100000000100010100000000011001111000000001000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~0_combout\); + +-- Location: MLABCELL_X13_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000001110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\); + +-- Location: MLABCELL_X13_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001100100011111111110010001100100010001000101111111100100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~4_combout\); + +-- Location: FF_X13_Y37_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\); + +-- Location: FF_X16_Y37_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\); + +-- Location: LABCELL_X12_Y38_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\); + +-- Location: MLABCELL_X9_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011101011101011111100000000001100110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\); + +-- Location: LABCELL_X16_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111001111110011111111111111101111111111111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\); + +-- Location: LABCELL_X16_Y39_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101111111010101010111000001010101010011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~2_combout\); + +-- Location: LABCELL_X16_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111001101010101111100110101010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~3_combout\); + +-- Location: LABCELL_X16_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010011000100010001001100010011000100110001001100010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\); + +-- Location: LABCELL_X16_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100001111111111110000111111111111101011111111111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\); + +-- Location: LABCELL_X16_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110101110011001111110100000000111101011100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_combout\); + +-- Location: FF_X16_Y37_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\); + +-- Location: FF_X16_Y37_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~q\); + +-- Location: LABCELL_X14_Y39_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001011101000011100101111100000000010101010000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\); + +-- Location: LABCELL_X12_Y37_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\); + +-- Location: LABCELL_X14_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000011110000111100000101000011010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\); + +-- Location: LABCELL_X16_Y37_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501_BDD8502\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501_BDD8502\); + +-- Location: LABCELL_X16_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\) +-- # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0011011100110111011101110111001000110010000000000111011101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~9_combout\); + +-- Location: LABCELL_X16_Y37_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~9_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~9_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111000001010000011100000101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\); + +-- Location: LABCELL_X16_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111001111110011111111111111111111110111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\); + +-- Location: LABCELL_X16_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501_BDD8502\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111101001111010101010101010101011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501_BDD8502\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_combout\); + +-- Location: FF_X16_Y37_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\); + +-- Location: LABCELL_X12_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~0_combout\); + +-- Location: LABCELL_X12_Y37_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux3~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux3~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux3~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~2_combout\); + +-- Location: MLABCELL_X13_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux5~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux9~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux3~2_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~1_combout\); + +-- Location: LABCELL_X10_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux2~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux1~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000101000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\); + +-- Location: LABCELL_X10_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\); + +-- Location: LABCELL_X10_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\); + +-- Location: FF_X10_Y17_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG682\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM683\); + +-- Location: LABCELL_X17_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~40_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~40_combout\); + +-- Location: LABCELL_X20_Y14_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~38_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\ & ( ((\myVirtualToplevel|LessThan0~1_combout\ +-- & ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\ & ( +-- (\myVirtualToplevel|LessThan0~1_combout\ & ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\ & ( ((!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|LessThan0~1_combout\ & \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\) ) ) ) # ( +-- !\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\ & ( (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|LessThan0~1_combout\ & \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010000000101111111100010011000100110001001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]~35_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~38_combout\); + +-- Location: LABCELL_X17_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~39_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[1]~63_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (!\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~38_combout\))) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[1]~63_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~38_combout\)) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110000001100111110000000100011111100000011001111100000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~38_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~63_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~39_combout\); + +-- Location: LABCELL_X17_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~39_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~40_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~39_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~40_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~39_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~40_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~39_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~40_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110000011100000111000001110000011100000111100001110000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~40_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~39_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~2_combout\); + +-- Location: FF_X17_Y15_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_NEW_REG757\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM758\); + +-- Location: LABCELL_X10_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM687\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM758\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM683\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM687\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM758\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM687\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM758\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM683\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM687\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM758\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100010001010101010101000101010101110111010101010101011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]_OTERM756\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM683\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM687\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]_OTERM758\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\); + +-- Location: LABCELL_X7_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_WREN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_WREN~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001010001010000000101000101000000010101010100000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_WREN~0_combout\); + +-- Location: LABCELL_X2_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111111111111010111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\); + +-- Location: LABCELL_X2_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal131~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal131~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000000010100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal131~0_combout\); + +-- Location: LABCELL_X2_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010000000000000101000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\); + +-- Location: LABCELL_X1_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal131~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\)))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000100000001001000000000010000000001000100010010000000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~78_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal131~0_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~76_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~4_combout\); + +-- Location: LABCELL_X2_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_RESYN12504\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_RESYN12504_BDD12505\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111111110101101011111111010111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_RESYN12504_BDD12505\); + +-- Location: LABCELL_X2_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_RESYN12504_BDD12505\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_RESYN12504_BDD12505\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_RESYN12504_BDD12505\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_RESYN12504_BDD12505\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011111111111111111111111111111011111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~1_RESYN12504_BDD12505\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_combout\); + +-- Location: LABCELL_X2_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\); + +-- Location: LABCELL_X2_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~92\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~92_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~77_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~92_combout\); + +-- Location: LABCELL_X1_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\) # (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000000000000000000000000010000000000001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~76_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~77_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~2_combout\); + +-- Location: LABCELL_X2_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~80\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~80_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111001100000000001100110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~80_combout\); + +-- Location: LABCELL_X2_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~0_combout\); + +-- Location: MLABCELL_X4_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100000000000000000000000000000100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~1_combout\); + +-- Location: LABCELL_X2_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~80_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~1_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~80_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~80_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010011011100001111000011110000111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~80_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~77_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~2_combout\); + +-- Location: LABCELL_X1_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000000000001010000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~78_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~1_combout\); + +-- Location: LABCELL_X1_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~92_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~92_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\); + +-- Location: LABCELL_X20_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~49_combout\); + +-- Location: FF_X20_Y31_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~49_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\); + +-- Location: LABCELL_X20_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000010111111111111111000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~47_combout\); + +-- Location: FF_X20_Y31_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~47_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\); + +-- Location: MLABCELL_X18_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001000001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~48_combout\); + +-- Location: FF_X18_Y28_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~48_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\); + +-- Location: LABCELL_X25_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~50_combout\); + +-- Location: FF_X25_Y31_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~50_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\); + +-- Location: LABCELL_X17_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101000011110000000000110011010101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~3_combout\); + +-- Location: LABCELL_X20_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_RESYN12726\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_RESYN12726_BDD12727\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000001010000000000000101000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_RESYN12726_BDD12727\); + +-- Location: LABCELL_X20_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_RESYN12726_BDD12727\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~0_RESYN12726_BDD12727\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_combout\); + +-- Location: LABCELL_X25_Y37_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~82\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~82_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~82_combout\); + +-- Location: LABCELL_X20_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_RESYN12698\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_RESYN12698_BDD12699\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000110000000101000011000000000000011000100100000001100010010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_RESYN12698_BDD12699\); + +-- Location: LABCELL_X20_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_RESYN12698_BDD12699\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110000000000000011000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_RESYN12698_BDD12699\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\); + +-- Location: LABCELL_X21_Y39_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~51_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~51_combout\); + +-- Location: LABCELL_X20_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~51_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~51_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~51_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4_combout\); + +-- Location: LABCELL_X20_Y37_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~82_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011000000110011001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~82_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\); + +-- Location: LABCELL_X24_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_RESYN12728\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_RESYN12728_BDD12729\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_RESYN12728_BDD12729\); + +-- Location: LABCELL_X24_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_RESYN12728_BDD12729\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~0_RESYN12728_BDD12729\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\); + +-- Location: LABCELL_X21_Y39_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_RESYN12732\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_RESYN12732_BDD12733\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_RESYN12732_BDD12733\); + +-- Location: LABCELL_X21_Y39_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_RESYN12732_BDD12733\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000010000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~2_RESYN12732_BDD12733\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_combout\); + +-- Location: LABCELL_X20_Y37_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_RESYN12484\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_RESYN12484_BDD12485\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101000000000101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_RESYN12484_BDD12485\); + +-- Location: LABCELL_X20_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_RESYN12484_BDD12485\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~5_RESYN12484_BDD12485\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_combout\); + +-- Location: LABCELL_X24_Y37_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_RESYN12734\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_RESYN12734_BDD12735\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000011110000111100000000000000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_RESYN12734_BDD12735\); + +-- Location: LABCELL_X24_Y37_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_RESYN12734_BDD12735\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000110000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~4_RESYN12734_BDD12735\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_combout\); + +-- Location: LABCELL_X24_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal12~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal12~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal12~0_combout\); + +-- Location: LABCELL_X21_Y39_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110000001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~3_combout\); + +-- Location: LABCELL_X24_Y37_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~3_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal12~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal12~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001111111111000000000000000000111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal12~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~3_combout\); + +-- Location: LABCELL_X21_Y39_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_RESYN12730\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_RESYN12730_BDD12731\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_RESYN12730_BDD12731\); + +-- Location: LABCELL_X21_Y39_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_RESYN12730_BDD12731\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~1_RESYN12730_BDD12731\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_combout\); + +-- Location: LABCELL_X20_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\); + +-- Location: LABCELL_X26_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18) $ (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18) $ (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000110000110000000011000011001100001100111100110000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~25_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~21_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~5_combout\); + +-- Location: LABCELL_X26_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100000100010100010000010001001000100000100010100010000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~17_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~3_combout\); + +-- Location: LABCELL_X29_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~17_combout\); + +-- Location: LABCELL_X31_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~65_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~69_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~11_combout\); + +-- Location: MLABCELL_X28_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111101010101010111110101010100000101000000000000010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~33_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~12_combout\); + +-- Location: MLABCELL_X28_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000001010101000000000101001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~33_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~6_combout\); + +-- Location: MLABCELL_X28_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~14_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~11_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~12_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000011001000100010000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~14_combout\); + +-- Location: LABCELL_X21_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~17_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~14_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011010000111100001100000011110000110100001111000011010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~19_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\); + +-- Location: LABCELL_X21_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000001000101010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\); + +-- Location: LABCELL_X21_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000101010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~426_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~35_combout\); + +-- Location: FF_X21_Y29_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~35_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\); + +-- Location: LABCELL_X21_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\); + +-- Location: LABCELL_X21_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000101010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~427_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~36_combout\); + +-- Location: FF_X21_Y29_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~36_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~q\); + +-- Location: LABCELL_X21_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\); + +-- Location: LABCELL_X21_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010000010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~428_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~37_combout\); + +-- Location: FF_X21_Y29_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~37_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~q\); + +-- Location: LABCELL_X21_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000001000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\); + +-- Location: LABCELL_X21_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010000010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~429_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~38_combout\); + +-- Location: FF_X21_Y29_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~38_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~q\); + +-- Location: LABCELL_X21_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~0_combout\); + +-- Location: LABCELL_X20_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12500\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12500_BDD12501\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010001011111111101010001111111110100010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12500_BDD12501\); + +-- Location: LABCELL_X20_Y36_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12502\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12502_BDD12503\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110011110000111111111111001111111111111111001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12502_BDD12503\); + +-- Location: LABCELL_X21_Y38_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\); + +-- Location: LABCELL_X20_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12502_BDD12503\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12500_BDD12501\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12502_BDD12503\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12500_BDD12501\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12500_BDD12501\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12500_BDD12501\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101110111011001110110011101100000000101110110000000000111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_RESYN12500_BDD12501\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_RESYN12502_BDD12503\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~69_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\); + +-- Location: MLABCELL_X23_Y37_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal67~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal67~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000000000101010100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal67~0_combout\); + +-- Location: MLABCELL_X23_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal67~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal67~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100000000000000000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal67~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~2_combout\); + +-- Location: LABCELL_X21_Y37_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_RESYN12742\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_RESYN12742_BDD12743\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000000011111111000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_RESYN12742_BDD12743\); + +-- Location: LABCELL_X21_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_RESYN12742_BDD12743\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~1_RESYN12742_BDD12743\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_combout\); + +-- Location: LABCELL_X21_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_RESYN12738\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_RESYN12738_BDD12739\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010000000000000101000001010000000000000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_RESYN12738_BDD12739\); + +-- Location: LABCELL_X21_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_RESYN12738_BDD12739\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_RESYN12738_BDD12739\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_RESYN12738_BDD12739\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\); + +-- Location: LABCELL_X21_Y38_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_RESYN12740\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_RESYN12740_BDD12741\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000110000110000000011000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_RESYN12740_BDD12741\); + +-- Location: LABCELL_X21_Y38_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_RESYN12740_BDD12741\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_RESYN12740_BDD12741\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000100000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~0_RESYN12740_BDD12741\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_combout\); + +-- Location: LABCELL_X21_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_RESYN12496\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_RESYN12496_BDD12497\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_RESYN12496_BDD12497\); + +-- Location: LABCELL_X21_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_RESYN12496_BDD12497\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~90_RESYN12496_BDD12497\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_combout\); + +-- Location: MLABCELL_X23_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000101000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~69_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~3_combout\); + +-- Location: LABCELL_X21_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~90_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\); + +-- Location: LABCELL_X21_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~429_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~46_combout\); + +-- Location: FF_X21_Y30_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~46_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~q\); + +-- Location: LABCELL_X21_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000110010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~428_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~45_combout\); + +-- Location: FF_X21_Y30_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~45_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~q\); + +-- Location: LABCELL_X21_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001100000010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~426_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~43_combout\); + +-- Location: FF_X21_Y30_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~43_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\); + +-- Location: LABCELL_X21_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110010000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~427_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~44_combout\); + +-- Location: FF_X21_Y30_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~44_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\); + +-- Location: MLABCELL_X18_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~2_combout\); + +-- Location: MLABCELL_X23_Y40_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_RESYN12490\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_RESYN12490_BDD12491\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_RESYN12490_BDD12491\); + +-- Location: MLABCELL_X23_Y40_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_RESYN12490_BDD12491\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~87_RESYN12490_BDD12491\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_combout\); + +-- Location: MLABCELL_X23_Y38_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\); + +-- Location: MLABCELL_X23_Y40_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_RESYN12492\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_RESYN12492_BDD12493\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\))) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101010001010000010101000101000001010001010100000101000101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_RESYN12492_BDD12493\); + +-- Location: MLABCELL_X23_Y40_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_RESYN12492_BDD12493\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_RESYN12492_BDD12493\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010111111110000100011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~3_RESYN12492_BDD12493\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_combout\); + +-- Location: MLABCELL_X23_Y40_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~83\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~83_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~83_combout\); + +-- Location: MLABCELL_X23_Y38_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111111111111001111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\); + +-- Location: MLABCELL_X23_Y40_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\); + +-- Location: MLABCELL_X23_Y40_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000000000000000000000010010000100100001001000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~64_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~67_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~4_combout\); + +-- Location: MLABCELL_X23_Y39_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0_combout\); + +-- Location: MLABCELL_X23_Y40_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~83_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000000000000000000010100000100000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~87_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~83_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\); + +-- Location: MLABCELL_X23_Y40_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_RESYN12486\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_RESYN12486_BDD12487\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000000000000000000011110000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_RESYN12486_BDD12487\); + +-- Location: MLABCELL_X23_Y40_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_RESYN12486_BDD12487\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_RESYN12486_BDD12487\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000001000000000000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~1_RESYN12486_BDD12487\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_combout\); + +-- Location: LABCELL_X19_Y38_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_RESYN12488\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_RESYN12488_BDD12489\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000001000000010000000100000001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_RESYN12488_BDD12489\); + +-- Location: LABCELL_X19_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_RESYN12488_BDD12489\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_RESYN12488_BDD12489\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001000000000000000001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~0_RESYN12488_BDD12489\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_combout\); + +-- Location: LABCELL_X19_Y38_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_RESYN12736\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_RESYN12736_BDD12737\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000000000000011000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_RESYN12736_BDD12737\); + +-- Location: LABCELL_X19_Y38_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_RESYN12736_BDD12737\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_RESYN12736_BDD12737\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001000000000000000000000000000000000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~0_RESYN12736_BDD12737\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_combout\); + +-- Location: MLABCELL_X23_Y40_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100000000000000000000000000001001100000000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~64_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~67_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~1_combout\); + +-- Location: LABCELL_X19_Y38_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\); + +-- Location: MLABCELL_X18_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000101010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~427_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~40_combout\); + +-- Location: FF_X18_Y30_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~40_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\); + +-- Location: MLABCELL_X18_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010000010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~428_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~41_combout\); + +-- Location: FF_X18_Y30_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~41_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~q\); + +-- Location: MLABCELL_X18_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000101010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~429_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~42_combout\); + +-- Location: FF_X18_Y30_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~42_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~q\); + +-- Location: MLABCELL_X18_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010000010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~426_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~39_combout\); + +-- Location: FF_X18_Y30_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~39_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\); + +-- Location: MLABCELL_X18_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~1_combout\); + +-- Location: LABCELL_X17_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~0_combout\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~3_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110001001010001011100110100100011101010110110011111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\); + +-- Location: MLABCELL_X4_Y23_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_RESYN12712\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_RESYN12712_BDD12713\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_RESYN12712_BDD12713\); + +-- Location: MLABCELL_X4_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_RESYN12712_BDD12713\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_RESYN12712_BDD12713\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000100000000000000010000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~0_RESYN12712_BDD12713\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_combout\); + +-- Location: MLABCELL_X4_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000010011101000000001001110000101000101001000010100010100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~0_combout\); + +-- Location: MLABCELL_X4_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000100000000000100010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~1_combout\); + +-- Location: MLABCELL_X4_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_RESYN12714\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_RESYN12714_BDD12715\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100010001000000000001000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_RESYN12714_BDD12715\); + +-- Location: MLABCELL_X4_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_RESYN12714_BDD12715\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001000100000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~0_RESYN12714_BDD12715\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_combout\); + +-- Location: MLABCELL_X4_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\); + +-- Location: MLABCELL_X4_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_RESYN12716\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_RESYN12716_BDD12717\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011100000111000001110000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_RESYN12716_BDD12717\); + +-- Location: MLABCELL_X4_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_RESYN12716_BDD12717\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\)) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_RESYN12716_BDD12717\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000010001000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~0_RESYN12716_BDD12717\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_combout\); + +-- Location: LABCELL_X5_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~0_combout\); + +-- Location: MLABCELL_X4_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal131~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal131~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal131~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000000000000000000001010101111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~76_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal131~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~1_combout\); + +-- Location: MLABCELL_X4_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101010101010101000101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~76_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~1_combout\); + +-- Location: LABCELL_X2_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux133~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux133~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000011110000000000001111001100000000111100110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux133~0_combout\); + +-- Location: MLABCELL_X4_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux135~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux135~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux135~0_combout\); + +-- Location: MLABCELL_X4_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~79\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~79_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux133~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux135~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\)))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000100011000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux133~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux135~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~79_combout\); + +-- Location: MLABCELL_X4_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\)))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000000000000000000000000000000000000010000000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~76_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~3_combout\); + +-- Location: MLABCELL_X4_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~79_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~79_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\); + +-- Location: MLABCELL_X18_Y31_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000101010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~427_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~15_combout\); + +-- Location: FF_X18_Y31_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~15_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~q\); + +-- Location: LABCELL_X17_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000101010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~429_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~17_combout\); + +-- Location: FF_X17_Y31_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\); + +-- Location: MLABCELL_X18_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010000010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~428_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~16_combout\); + +-- Location: FF_X18_Y31_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~16_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~q\); + +-- Location: LABCELL_X17_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001100000010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~426_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~14_combout\); + +-- Location: FF_X17_Y31_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~14_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\); + +-- Location: MLABCELL_X18_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~3_combout\); + +-- Location: MLABCELL_X23_Y38_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~66\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~66_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~66_combout\); + +-- Location: MLABCELL_X23_Y38_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~66_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~66_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100000000000000010000000000000010000000000000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~66_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~1_combout\); + +-- Location: MLABCELL_X23_Y38_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_RESYN8929\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_RESYN8929_BDD8930\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001100000001001000110000000100100001000000100010000100000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_RESYN8929_BDD8930\); + +-- Location: MLABCELL_X23_Y38_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_RESYN8929_BDD8930\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000100010011000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~63_RESYN8929_BDD8930\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_combout\); + +-- Location: MLABCELL_X23_Y38_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~68\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~68_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000101000000000000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~68_combout\); + +-- Location: MLABCELL_X23_Y38_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~68_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000010000000110000001000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~68_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~3_combout\); + +-- Location: MLABCELL_X23_Y38_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001000000000000000000011110000000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~64_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~67_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~2_combout\); + +-- Location: MLABCELL_X23_Y38_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~59_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001000000000000000100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~59_combout\); + +-- Location: MLABCELL_X23_Y38_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~66_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~59_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~66_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101000001010101010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~59_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~66_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~0_combout\); + +-- Location: MLABCELL_X23_Y38_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~14_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "1111111111111101111111111100111111111111111111111100111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~64_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~14_combout\); + +-- Location: MLABCELL_X23_Y38_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~63_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\); + +-- Location: LABCELL_X19_Y38_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000000000000001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0_combout\); + +-- Location: LABCELL_X19_Y38_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000001011110011111100111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal99~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~0_combout\); + +-- Location: LABCELL_X19_Y38_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux121~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux121~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000001010101010100000101000000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux121~0_combout\); + +-- Location: MLABCELL_X23_Y38_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\); + +-- Location: LABCELL_X19_Y38_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~0_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux121~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\)))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110000001100000111000001110000011100000111000001110000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux121~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux123~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal99~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\); + +-- Location: MLABCELL_X18_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000111000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~427_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~7_combout\); + +-- Location: FF_X18_Y31_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\); + +-- Location: FF_X18_Y31_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~9_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\); + +-- Location: MLABCELL_X18_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000111000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~429_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~9_combout\); + +-- Location: FF_X18_Y31_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~9_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001110000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~428_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~8_combout\); + +-- Location: FF_X18_Y31_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~q\); + +-- Location: MLABCELL_X18_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001110000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~426_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~6_combout\); + +-- Location: FF_X18_Y31_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~q\); + +-- Location: MLABCELL_X18_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~1_combout\); + +-- Location: MLABCELL_X23_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_RESYN12708\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_RESYN12708_BDD12709\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110000001100000000000000110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_RESYN12708_BDD12709\); + +-- Location: MLABCELL_X23_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_RESYN12708_BDD12709\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_RESYN12708_BDD12709\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000010000000000000100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~0_RESYN12708_BDD12709\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_combout\); + +-- Location: MLABCELL_X23_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_RESYN8935\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_RESYN8935_BDD8936\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101011111110101111110111111011111011111111111110101010101011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_RESYN8935_BDD8936\); + +-- Location: MLABCELL_X23_Y37_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_RESYN8935_BDD8936\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111111111000011111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~0_RESYN8935_BDD8936\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_combout\); + +-- Location: LABCELL_X20_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~0_combout\); + +-- Location: MLABCELL_X23_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~0_combout\))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal67~0_combout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000000000000001110000111110000000100000000000011100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal67~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~0_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~2_combout\); + +-- Location: MLABCELL_X23_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_RESYN12564\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_RESYN12564_BDD12565\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000101000000000100010100000000000000010001000010000001000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_RESYN12564_BDD12565\); + +-- Location: MLABCELL_X23_Y37_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_RESYN12564_BDD12565\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\)) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_RESYN12564_BDD12565\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000000000000101000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~6_RESYN12564_BDD12565\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_combout\); + +-- Location: LABCELL_X21_Y37_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_RESYN12710\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_RESYN12710_BDD12711\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_RESYN12710_BDD12711\); + +-- Location: LABCELL_X21_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_RESYN12710_BDD12711\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_RESYN12710_BDD12711\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_RESYN12710_BDD12711\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_RESYN12710_BDD12711\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101000011110000111100001111000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~1_RESYN12710_BDD12711\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_combout\); + +-- Location: MLABCELL_X23_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000010010001010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~69_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~1_combout\); + +-- Location: MLABCELL_X23_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~1_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111110111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\); + +-- Location: LABCELL_X21_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~12_combout\); + +-- Location: FF_X21_Y31_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\); + +-- Location: LABCELL_X21_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~11_combout\); + +-- Location: FF_X21_Y31_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~11_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\); + +-- Location: LABCELL_X25_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~13_combout\); + +-- Location: FF_X25_Y31_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~13_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\); + +-- Location: LABCELL_X25_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~10_combout\); + +-- Location: FF_X25_Y31_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\); + +-- Location: MLABCELL_X18_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~2_combout\); + +-- Location: LABCELL_X24_Y37_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_RESYN8605\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_RESYN8605_BDD8606\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000111111111111111111111111000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_RESYN8605_BDD8606\); + +-- Location: LABCELL_X25_Y37_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_RESYN12696\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_RESYN12696_BDD12697\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ +-- & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011110000110011001111000011111111111100001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_RESYN12696_BDD12697\); + +-- Location: LABCELL_X25_Y37_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_RESYN12694\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_RESYN12694_BDD12695\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111111100000000111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_RESYN12694_BDD12695\); + +-- Location: LABCELL_X25_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_RESYN12694_BDD12695\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010000001000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~1_RESYN12694_BDD12695\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_combout\); + +-- Location: LABCELL_X25_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_RESYN8605_BDD8606\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_RESYN12696_BDD12697\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010101000001010000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~2_RESYN8605_BDD8606\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_RESYN12696_BDD12697\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\); + +-- Location: LABCELL_X20_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010000000000000101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\); + +-- Location: LABCELL_X20_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000000001000100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\); + +-- Location: LABCELL_X20_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000010000000000000000011000100000000101100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~47_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~54_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~1_combout\); + +-- Location: LABCELL_X21_Y39_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_RESYN12700\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_RESYN12700_BDD12701\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111110100000000011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_RESYN12700_BDD12701\); + +-- Location: LABCELL_X21_Y39_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_RESYN12700_BDD12701\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~2_RESYN12700_BDD12701\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_combout\); + +-- Location: LABCELL_X21_Y39_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_RESYN12804\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_RESYN12804_BDD12805\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100010001000100010001000100000011100000111000001110000011100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_RESYN12804_BDD12805\); + +-- Location: LABCELL_X21_Y39_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_RESYN12804_BDD12805\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~5_RESYN12804_BDD12805\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_combout\); + +-- Location: LABCELL_X21_Y39_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_RESYN12702\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_RESYN12702_BDD12703\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_RESYN12702_BDD12703\); + +-- Location: LABCELL_X21_Y39_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_RESYN12702_BDD12703\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\)) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_RESYN12702_BDD12703\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000000000000000000001000000010000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~3_RESYN12702_BDD12703\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_combout\); + +-- Location: LABCELL_X20_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\); + +-- Location: MLABCELL_X18_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000101010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~428_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~4_combout\); + +-- Location: FF_X18_Y31_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~q\); + +-- Location: MLABCELL_X18_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000101010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~427_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~3_combout\); + +-- Location: FF_X18_Y31_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~q\); + +-- Location: MLABCELL_X18_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010000010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~426_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~2_combout\); + +-- Location: FF_X18_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\); + +-- Location: MLABCELL_X18_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010000010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~429_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~5_combout\); + +-- Location: FF_X18_Y31_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\); + +-- Location: MLABCELL_X18_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~0_combout\); + +-- Location: MLABCELL_X18_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101001000110110011110001001110011011010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\); + +-- Location: LABCELL_X17_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000011001100001100000011000000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\); + +-- Location: MLABCELL_X13_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010100000000000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\); + +-- Location: MLABCELL_X9_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector442~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111110011000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~0_combout\); + +-- Location: MLABCELL_X9_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector442~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001010000010111001100110011001100110111001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~3_combout\); + +-- Location: MLABCELL_X9_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector442~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000001111000000001111000011111111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~2_combout\); + +-- Location: LABCELL_X16_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector442~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011110000000000001111000000000000111100001111000011110000111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector363~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~1_combout\); + +-- Location: LABCELL_X10_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~67\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~67_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector442~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector442~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector442~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector442~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector442~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector442~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100001111000011110000111100110011111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~67_combout\); + +-- Location: LABCELL_X10_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000100000001000000010010000000001000001100100000101001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~0_combout\); + +-- Location: LABCELL_X10_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000001000001100001101001100000000000000010011000010000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~1_combout\); + +-- Location: LABCELL_X10_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~1_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101111111011101111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr162~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr162~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~2_combout\); + +-- Location: LABCELL_X10_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~68\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~68_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector442~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp~67_combout\)) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add21~85_sumout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001010100010101010101010000111111111111111111110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~85_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~67_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~68_combout\); + +-- Location: FF_X10_Y26_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp~68_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)); + +-- Location: LABCELL_X14_Y39_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~0_combout\); + +-- Location: LABCELL_X14_Y39_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000101010001010100010101000101010000010100000111001101110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~6_combout\); + +-- Location: LABCELL_X14_Y39_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110011001100000000001100110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~5_combout\); + +-- Location: LABCELL_X14_Y39_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101000000000111110100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~7_combout\); + +-- Location: LABCELL_X14_Y39_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101011111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~4_combout\); + +-- Location: FF_X18_Y35_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~8_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2)); + +-- Location: LABCELL_X19_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_RESYN9089\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_RESYN9089_BDD9090\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101100011011000110110001101100011111010010100001111101001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_RESYN9089_BDD9090\); + +-- Location: LABCELL_X19_Y35_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_BDD8448\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_RESYN9089_BDD9090\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_RESYN9089_BDD9090\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110111111111111111011111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8447_RESYN9089_BDD9090\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_BDD8448\); + +-- Location: LABCELL_X19_Y37_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~1_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~1_combout\); + +-- Location: MLABCELL_X18_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8449\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8449_BDD8450\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111001111110011110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8449_BDD8450\); + +-- Location: MLABCELL_X18_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8449_BDD8450\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_BDD8448\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8449_BDD8450\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_BDD8448\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001110000011100000111000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8447_BDD8448\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8449_BDD8450\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_combout\); + +-- Location: MLABCELL_X18_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001000000100000001111000011110000011100001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~3_combout\); + +-- Location: MLABCELL_X18_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9165\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9165_BDD9166\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9165_BDD9166\); + +-- Location: LABCELL_X19_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9167\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9167_BDD9168\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9165_BDD9166\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9165_BDD9166\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9165_BDD9166\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111001100110011001100111010001110100011001000110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_RESYN9165_BDD9166\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9167_BDD9168\); + +-- Location: MLABCELL_X18_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9167_BDD9168\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9167_BDD9168\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001110010011100100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_RESYN9167_BDD9168\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_combout\); + +-- Location: LABCELL_X17_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\); + +-- Location: MLABCELL_X18_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8825\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8825_BDD8826\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~3_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000011000011110000001111111111111100110000111100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8825_BDD8826\); + +-- Location: LABCELL_X14_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~2_combout\); + +-- Location: MLABCELL_X18_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000110000000000000011000001111000001100000111100000110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~0_combout\); + +-- Location: LABCELL_X19_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111010101111111100010101111111111111110101101010100100111100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\); + +-- Location: MLABCELL_X18_Y35_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8823\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8823_BDD8824\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000011000011000000001100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~40_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8823_BDD8824\); + +-- Location: MLABCELL_X18_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000001100000000000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~40_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~1_combout\); + +-- Location: MLABCELL_X18_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8827\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8827_BDD8828\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8823_BDD8824\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8823_BDD8824\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101001111111111111111111111001111010011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8823_BDD8824\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8827_BDD8828\); + +-- Location: MLABCELL_X18_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8827_BDD8828\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8827_BDD8828\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8827_BDD8828\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8827_BDD8828\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8825_BDD8826\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011000000110000001100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8825_BDD8826\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8827_BDD8828\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_combout\); + +-- Location: MLABCELL_X18_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~7_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~4_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~7_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010111011101110101011101110111011101110111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~8_combout\); + +-- Location: FF_X18_Y35_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~8_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~1_combout\); + +-- Location: FF_X17_Y33_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~5_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110111001100110011011100000011000001010000001100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~3_combout\); + +-- Location: LABCELL_X10_Y36_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000011111111111100001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~3_combout\); + +-- Location: MLABCELL_X9_Y36_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101010100000101000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~2_combout\); + +-- Location: LABCELL_X10_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~3_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011000000111100001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~4_combout\); + +-- Location: LABCELL_X17_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000000011110101111111111111010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~2_combout\); + +-- Location: LABCELL_X17_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000110000000000000011000001111000001100000111100000110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~3_combout\); + +-- Location: LABCELL_X17_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~3_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|addr~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101001111000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~4_combout\); + +-- Location: LABCELL_X17_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~4_combout\); + +-- Location: LABCELL_X17_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~6_RESYN8457\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~6_RESYN8457_BDD8458\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~4_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~4_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011101110111011101110111011001100111000001100110011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~6_RESYN8457_BDD8458\); + +-- Location: LABCELL_X17_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8833\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8833_BDD8834\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011101100110011001110110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8833_BDD8834\); + +-- Location: LABCELL_X17_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12388\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12388_BDD12389\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~6_RESYN8457_BDD8458\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8833_BDD8834\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~6_RESYN8457_BDD8458\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8833_BDD8834\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~6_RESYN8457_BDD8458\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8833_BDD8834\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~6_RESYN8457_BDD8458\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8833_BDD8834\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111101011111010100001111000011110000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~6_RESYN8457_BDD8458\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~10_RESYN8833_BDD8834\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12388_BDD12389\); + +-- Location: LABCELL_X16_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_RESYN12558\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_RESYN12558_BDD12559\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~47_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_RESYN12558_BDD12559\); + +-- Location: LABCELL_X16_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_RESYN12558_BDD12559\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_RESYN12558_BDD12559\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000101000000000000000000000000000010100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~11_RESYN12558_BDD12559\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_combout\); + +-- Location: LABCELL_X17_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8461\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8461_BDD8462\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8461_BDD8462\); + +-- Location: LABCELL_X12_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_RESYN9091\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_RESYN9091_BDD9092\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010110011001100110011110000111100001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_RESYN9091_BDD9092\); + +-- Location: LABCELL_X12_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_BDD8460\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_RESYN9091_BDD9092\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_RESYN9091_BDD9092\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_RESYN9091_BDD9092\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_RESYN9091_BDD9092\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111100111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8459_RESYN9091_BDD9092\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_BDD8460\); + +-- Location: LABCELL_X16_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_BDD8460\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~4_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8461_BDD8462\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|addr~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8461_BDD8462\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_BDD8460\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8461_BDD8462\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110011001100000000000000001010111100100011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8461_BDD8462\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8459_BDD8460\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_combout\); + +-- Location: LABCELL_X16_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8831\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8831_BDD8832\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111110000000011111110111111101010111000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8831_BDD8832\); + +-- Location: LABCELL_X17_Y36_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~0_combout\); + +-- Location: LABCELL_X16_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12386\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12386_BDD12387\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~0_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8831_BDD8832\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110011111111111111001111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~10_RESYN8831_BDD8832\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12386_BDD12387\); + +-- Location: LABCELL_X14_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000011000000110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~47_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~1_combout\); + +-- Location: LABCELL_X17_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12386_BDD12387\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12386_BDD12387\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12386_BDD12387\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12386_BDD12387\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12388_BDD12389\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector860~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000101000001010000010100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_RESYN12388_BDD12389\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_RESYN12386_BDD12387\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_combout\); + +-- Location: LABCELL_X17_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~1_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~4_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~4_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011011111110111111111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~5_combout\); + +-- Location: FF_X17_Y33_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~5_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2)); + +-- Location: MLABCELL_X18_Y38_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_RESYN8829\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_RESYN8829_BDD8830\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000101010101000100010101010111110001111101011111000111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_RESYN8829_BDD8830\); + +-- Location: LABCELL_X17_Y38_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_RESYN8829_BDD8830\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_RESYN8829_BDD8830\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_RESYN8829_BDD8830\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_RESYN8829_BDD8830\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001010000000110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~4_RESYN8829_BDD8830\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_combout\); + +-- Location: FF_X17_Y38_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~8_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2)); + +-- Location: LABCELL_X17_Y38_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~2_combout\); + +-- Location: LABCELL_X17_Y38_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|addr~2_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001100001111101010100011111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~9_combout\); + +-- Location: LABCELL_X17_Y38_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100000011100000010000001110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~3_combout\); + +-- Location: LABCELL_X17_Y38_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111111100000000111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2_combout\); + +-- Location: LABCELL_X16_Y39_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~46_combout\); + +-- Location: LABCELL_X17_Y38_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8453\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8453_BDD8454\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~46_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~9_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~46_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~46_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~9_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000010000000000000000000000011000000100000001100000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~41_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~46_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8453_BDD8454\); + +-- Location: LABCELL_X17_Y38_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000010100000111100001010000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~0_combout\); + +-- Location: LABCELL_X17_Y38_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000011000000000000001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~41_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~1_combout\); + +-- Location: LABCELL_X17_Y38_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~2_combout\); + +-- Location: LABCELL_X17_Y38_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001100000011000001111000011110000011000000110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~0_combout\); + +-- Location: LABCELL_X16_Y38_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|addr~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001001110111001000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~5_combout\); + +-- Location: LABCELL_X19_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000100000000000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\); + +-- Location: LABCELL_X17_Y38_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|addr~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100110101001111110011010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~6_combout\); + +-- Location: MLABCELL_X18_Y38_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000001110100001110000111110000111000011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~4_combout\); + +-- Location: LABCELL_X17_Y38_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8455\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8455_BDD8456\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~5_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~6_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~6_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010110010100000101000001010000011111100111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8455_BDD8456\); + +-- Location: LABCELL_X17_Y38_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8455_BDD8456\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8453_BDD8454\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector794~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000000000000000100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_RESYN8453_BDD8454\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_RESYN8455_BDD8456\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_combout\); + +-- Location: LABCELL_X14_Y39_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001111110011000000111111001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~5_combout\); + +-- Location: LABCELL_X14_Y39_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000011001100110000001100110111000001010011011100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~6_combout\); + +-- Location: LABCELL_X14_Y39_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111001111110011111100110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~7_combout\); + +-- Location: LABCELL_X17_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000101000101010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~8_combout\); + +-- Location: FF_X17_Y38_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~8_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\); + +-- Location: FF_X16_Y38_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~5_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\); + +-- Location: LABCELL_X16_Y38_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110000001111000011000000111100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~0_combout\); + +-- Location: LABCELL_X10_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000010001111111010001000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~3_combout\); + +-- Location: LABCELL_X10_Y36_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~5_combout\); + +-- Location: LABCELL_X10_Y36_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000011101111001000001110111100100000111011110010000011101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~2_combout\); + +-- Location: LABCELL_X10_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|addr~5_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|addr~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~3_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101000001010000000100010001000100010000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~4_combout\); + +-- Location: LABCELL_X16_Y38_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~0_combout\); + +-- Location: LABCELL_X16_Y38_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~8_combout\); + +-- Location: LABCELL_X16_Y38_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8841\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8841_BDD8842\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100000000001111000000000000111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8841_BDD8842\); + +-- Location: LABCELL_X12_Y38_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~5_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000011001100001111000011110101010101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~10_combout\); + +-- Location: LABCELL_X12_Y38_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~6_combout\); + +-- Location: LABCELL_X16_Y38_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|addr~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000000000000011000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~6_combout\); + +-- Location: LABCELL_X16_Y38_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~5_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|addr~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100110101110000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~7_combout\); + +-- Location: LABCELL_X16_Y38_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8843\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8843_BDD8844\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~7_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~10_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100001111000000110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8843_BDD8844\); + +-- Location: LABCELL_X16_Y38_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8463\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8463_BDD8464\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~5_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111110000000011101011111010111110101100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8463_BDD8464\); + +-- Location: LABCELL_X12_Y38_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~49_combout\); + +-- Location: LABCELL_X16_Y38_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8465\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8465_BDD8466\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~49_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~49_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100111111111100110000001111000011000000111100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~49_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8465_BDD8466\); + +-- Location: LABCELL_X12_Y38_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_RESYN8837\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_RESYN8837_BDD8838\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_RESYN8837_BDD8838\); + +-- Location: LABCELL_X12_Y38_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_RESYN8837_BDD8838\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_RESYN8837_BDD8838\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~49_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~49_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101110001000000010110000100011111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~49_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~3_RESYN8837_BDD8838\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_combout\); + +-- Location: LABCELL_X16_Y38_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8463_BDD8464\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8465_BDD8466\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8463_BDD8464\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8465_BDD8466\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_combout\))) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8463_BDD8464\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8465_BDD8466\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8463_BDD8464\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8465_BDD8466\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011000000000000001100000000000000010000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_RESYN8463_BDD8464\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_RESYN8465_BDD8466\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_combout\); + +-- Location: LABCELL_X16_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8843_BDD8844\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8841_BDD8842\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~0_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100000000000000000001010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_RESYN8841_BDD8842\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_RESYN8843_BDD8844\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_combout\); + +-- Location: LABCELL_X16_Y38_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~4_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~4_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110111001101110011111100110111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~5_combout\); + +-- Location: FF_X16_Y38_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~5_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(2)); + +-- Location: LABCELL_X16_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111001100110000000001010101000011110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~0_combout\); + +-- Location: MLABCELL_X18_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010000000000000101000001111000010100000111100001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~1_combout\); + +-- Location: LABCELL_X19_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111111111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\); + +-- Location: LABCELL_X19_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~2_combout\); + +-- Location: LABCELL_X19_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100110011001100100011001100100010001000100010001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~3_combout\); + +-- Location: MLABCELL_X18_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000010100000111100001010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~4_combout\); + +-- Location: FF_X18_Y34_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~5_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010101010100000101010101011111010101010101111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~2_combout\); + +-- Location: MLABCELL_X18_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8861\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8861_BDD8862\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000110000000000000011000001111000001100000111100000110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8861_BDD8862\); + +-- Location: MLABCELL_X18_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111010100001111111101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~51_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~1_combout\); + +-- Location: MLABCELL_X18_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~11_combout\); + +-- Location: LABCELL_X14_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8473\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8473_BDD8474\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111001010100011111111111111111111111110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8473_BDD8474\); + +-- Location: LABCELL_X14_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8475\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8475_BDD8476\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8473_BDD8474\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8473_BDD8474\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111110011110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_RESYN8473_BDD8474\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8475_BDD8476\); + +-- Location: MLABCELL_X18_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8475_BDD8476\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~11_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8475_BDD8476\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8475_BDD8476\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8475_BDD8476\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001100100011111010111110101100100011001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_RESYN8475_BDD8476\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_combout\); + +-- Location: MLABCELL_X18_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000000000110000000011001111000000001100111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~0_combout\); + +-- Location: MLABCELL_X18_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111101010100000111110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~9_combout\); + +-- Location: MLABCELL_X18_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8859\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8859_BDD8860\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011111110111111101111111011111110111111111111111011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~51_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8859_BDD8860\); + +-- Location: MLABCELL_X18_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_RESYN12634\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_RESYN12634_BDD12635\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~11_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~11_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~11_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100111111001111110011001100101010001100110010101000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_RESYN12634_BDD12635\); + +-- Location: MLABCELL_X18_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_RESYN12634_BDD12635\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111010111111001111101011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~6_RESYN12634_BDD12635\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_combout\); + +-- Location: MLABCELL_X18_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100010000010001010101010000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~4_combout\); + +-- Location: MLABCELL_X18_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~4_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~4_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010111001111010101011100111100000000110011110000000011001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~6_combout\); + +-- Location: MLABCELL_X18_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8859_BDD8860\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8859_BDD8860\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8859_BDD8860\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8859_BDD8860\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector530~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8861_BDD8862\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000111000000000000111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_RESYN8861_BDD8862\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_RESYN8859_BDD8860\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_combout\); + +-- Location: MLABCELL_X18_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~4_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~4_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000101111111110000110111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~5_combout\); + +-- Location: FF_X18_Y34_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~5_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2)); + +-- Location: FF_X18_Y36_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2)); + +-- Location: LABCELL_X19_Y36_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\)) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000000011110101000000001111010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~5_combout\); + +-- Location: MLABCELL_X9_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\); + +-- Location: LABCELL_X19_Y36_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12588\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12588_BDD12589\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100111110101111101011111111001100111111101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12588_BDD12589\); + +-- Location: LABCELL_X19_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12590\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12590_BDD12591\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111001000000001111100100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12590_BDD12591\); + +-- Location: LABCELL_X19_Y36_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_BDD8852\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12590_BDD12591\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12590_BDD12591\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12590_BDD12591\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12590_BDD12591\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12588_BDD12589\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111001110101111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_RESYN12588_BDD12589\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_RESYN12590_BDD12591\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_BDD8852\); + +-- Location: MLABCELL_X18_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8853\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8853_BDD8854\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8853_BDD8854\); + +-- Location: MLABCELL_X18_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_BDD8852\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8853_BDD8854\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_BDD8852\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8853_BDD8854\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_BDD8852\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8853_BDD8854\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_BDD8852\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8853_BDD8854\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010101000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_BDD8852\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8853_BDD8854\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_combout\); + +-- Location: LABCELL_X19_Y36_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8469\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8469_BDD8470\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000110011101010100011001110101010001100111010101000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8469_BDD8470\); + +-- Location: LABCELL_X19_Y36_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\); + +-- Location: LABCELL_X19_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_RESYN9093\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_RESYN9093_BDD9094\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111111001111101011111100111110100000110000001010000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_RESYN9093_BDD9094\); + +-- Location: LABCELL_X19_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_BDD8468\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_RESYN9093_BDD9094\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_RESYN9093_BDD9094\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110111111111111111011111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8467_RESYN9093_BDD9094\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_BDD8468\); + +-- Location: LABCELL_X19_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_BDD8468\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8469_BDD8470\ +-- & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8469_BDD8470\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_BDD8468\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8469_BDD8470\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011011101110111011101110100001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8469_BDD8470\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8467_BDD8468\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_combout\); + +-- Location: MLABCELL_X18_Y36_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000010100000000000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~6_combout\); + +-- Location: MLABCELL_X18_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9179\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9179_BDD9180\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~6_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~5_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110101111111111111010111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9179_BDD9180\); + +-- Location: MLABCELL_X9_Y36_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000110111011101110111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\); + +-- Location: MLABCELL_X9_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000100000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~0_combout\); + +-- Location: MLABCELL_X9_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111001100110011111100110011001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~1_combout\); + +-- Location: MLABCELL_X9_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000101010100000000000001100000000000000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~2_combout\); + +-- Location: LABCELL_X10_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001010100000101000000010001000100010101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~4_combout\); + +-- Location: MLABCELL_X18_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9173\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9173_BDD9174\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~4_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~4_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101110101011101010111010101110111011101010111011101110101011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9173_BDD9174\); + +-- Location: MLABCELL_X18_Y36_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9177\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9177_BDD9178\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9177_BDD9178\); + +-- Location: MLABCELL_X9_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9169\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9169_BDD9170\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110001101100001111000011110000111101001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9169_BDD9170\); + +-- Location: MLABCELL_X9_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9171\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9171_BDD9172\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\ +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000011110001111000011110000111110001111000001110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9171_BDD9172\); + +-- Location: LABCELL_X17_Y36_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9169_BDD9170\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9171_BDD9172\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9169_BDD9170\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9171_BDD9172\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9169_BDD9170\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9171_BDD9172\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9169_BDD9170\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9171_BDD9172\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111101010100010011101010101001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_RESYN9169_BDD9170\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_RESYN9171_BDD9172\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_combout\); + +-- Location: MLABCELL_X18_Y36_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9175\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9175_BDD9176\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9175_BDD9176\); + +-- Location: LABCELL_X19_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_RESYN9323\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_RESYN9323_BDD9324\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111110110001111111111111111000000001101100011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_RESYN9323_BDD9324\); + +-- Location: LABCELL_X19_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_BDD8846\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_RESYN9323_BDD9324\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_RESYN9323_BDD9324\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\) +-- # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_RESYN9323_BDD9324\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_RESYN9323_BDD9324\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111010111111111111111111111111011110100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8845_RESYN9323_BDD9324\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_BDD8846\); + +-- Location: LABCELL_X19_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_RESYN9325\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_RESYN9325_BDD9326\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_RESYN9325_BDD9326\); + +-- Location: LABCELL_X19_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_BDD8848\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_RESYN9325_BDD9326\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_RESYN9325_BDD9326\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_RESYN9325_BDD9326\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_RESYN9325_BDD9326\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111010111111111111111111111110111111111111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8847_RESYN9325_BDD9326\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_BDD8848\); + +-- Location: LABCELL_X19_Y37_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8849\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8849_BDD8850\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011111111111111111111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8849_BDD8850\); + +-- Location: MLABCELL_X18_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~85_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_BDD8846\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_BDD8848\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8849_BDD8850\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~85_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_BDD8846\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_BDD8848\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8849_BDD8850\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~85_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_BDD8846\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_BDD8848\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8849_BDD8850\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~85_sumout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_BDD8846\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8849_BDD8850\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_BDD8848\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000011000000000000001100000010000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8845_BDD8846\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8847_BDD8848\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8849_BDD8850\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~85_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_combout\); + +-- Location: MLABCELL_X18_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9175_BDD9176\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9177_BDD9178\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9179_BDD9180\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9173_BDD9174\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9175_BDD9176\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9179_BDD9180\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9177_BDD9178\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9173_BDD9174\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9175_BDD9176\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9177_BDD9178\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9179_BDD9180\)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9173_BDD9174\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9175_BDD9176\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9177_BDD9178\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9179_BDD9180\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9173_BDD9174\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011011100111111001101110011111100110111001101110011011100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9179_BDD9180\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9173_BDD9174\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9177_BDD9178\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9175_BDD9176\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_combout\); + +-- Location: FF_X18_Y36_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~0_combout\); + +-- Location: MLABCELL_X9_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111110011110000101100001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~1_combout\); + +-- Location: LABCELL_X17_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\); + +-- Location: LABCELL_X17_Y36_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000101000001010000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~2_combout\); + +-- Location: LABCELL_X19_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101111100000101010111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~5_combout\); + +-- Location: FF_X18_Y36_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~6_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(2)); + +-- Location: LABCELL_X19_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000001010101010101010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~0_combout\); + +-- Location: LABCELL_X19_Y36_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101111100000101010111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~7_combout\); + +-- Location: MLABCELL_X18_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8867\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8867_BDD8868\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~7_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~7_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111111111000000111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~44_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8867_BDD8868\); + +-- Location: LABCELL_X17_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~2_combout\); + +-- Location: LABCELL_X17_Y36_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~53_combout\); + +-- Location: LABCELL_X17_Y36_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~13_combout\); + +-- Location: LABCELL_X17_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~13_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~53_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~13_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~53_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110000011100000111000000000000011101110111011101110111000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~53_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~6_combout\); + +-- Location: LABCELL_X17_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8869\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8869_BDD8870\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000011010100111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8869_BDD8870\); + +-- Location: MLABCELL_X18_Y36_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000011001111111100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~44_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~1_combout\); + +-- Location: MLABCELL_X18_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000100100000000000111111110000000001111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~3_combout\); + +-- Location: LABCELL_X17_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12638\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12638_BDD12639\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111111111100001111111111110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12638_BDD12639\); + +-- Location: LABCELL_X17_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12636\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12636_BDD12637\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~13_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111001100111100001100110011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12636_BDD12637\); + +-- Location: LABCELL_X17_Y36_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12638_BDD12639\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12636_BDD12637\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~13_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12636_BDD12637\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~13_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111101000000000001100100000000000110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_RESYN12638_BDD12639\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_RESYN12636_BDD12637\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_combout\); + +-- Location: MLABCELL_X18_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~3_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(2) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~3_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000011001100110000001110111011100010111011101110001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~7_combout\); + +-- Location: MLABCELL_X18_Y36_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector662~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8869_BDD8870\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8867_BDD8868\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010011000000000011001100000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_RESYN8867_BDD8868\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_RESYN8869_BDD8870\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_combout\); + +-- Location: MLABCELL_X18_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~5_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~5_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010111011101110101011101110111011101110111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~6_combout\); + +-- Location: FF_X18_Y36_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~6_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y37_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~1_combout\); + +-- Location: FF_X18_Y37_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~5_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000101000000000000010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~54_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~0_combout\); + +-- Location: MLABCELL_X18_Y37_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8873\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8873_BDD8874\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8873_BDD8874\); + +-- Location: MLABCELL_X18_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8875\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8875_BDD8876\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8873_BDD8874\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8873_BDD8874\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000010000000010000001000001101000011100000110100001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8873_BDD8874\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8875_BDD8876\); + +-- Location: LABCELL_X16_Y39_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|addr~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000011111111111111111111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\); + +-- Location: MLABCELL_X18_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ $ ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000011110110011001101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~54_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~5_combout\); + +-- Location: MLABCELL_X18_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010100010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~1_combout\); + +-- Location: MLABCELL_X18_Y37_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010111111111010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~55_combout\); + +-- Location: MLABCELL_X18_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010000000000000101000001111000010100000111100001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~2_combout\); + +-- Location: LABCELL_X16_Y39_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_RESYN8479\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_RESYN8479_BDD8480\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011111111110011001111111111001100000000001100110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_RESYN8479_BDD8480\); + +-- Location: LABCELL_X19_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~55_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_RESYN8479_BDD8480\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~55_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_RESYN8479_BDD8480\)))) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~55_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_RESYN8479_BDD8480\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~55_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_RESYN8479_BDD8480\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_RESYN8479_BDD8480\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111000001110111111110000111100100010000000101111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~4_RESYN8479_BDD8480\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~55_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_combout\); + +-- Location: MLABCELL_X18_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~5_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~55_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000000010000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~55_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~6_combout\); + +-- Location: MLABCELL_X18_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010000100110000001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~7_combout\); + +-- Location: LABCELL_X19_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010001110111010000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~14_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~8_combout\); + +-- Location: MLABCELL_X18_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011001100111100111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~11_combout\); + +-- Location: MLABCELL_X18_Y37_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8877\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8877_BDD8878\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~7_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000111111000000000011111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8877_BDD8878\); + +-- Location: MLABCELL_X18_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8877_BDD8878\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8877_BDD8878\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8877_BDD8878\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8875_BDD8876\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector596~6_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8877_BDD8878\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000000010000010100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8875_BDD8876\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8877_BDD8878\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_combout\); + +-- Location: LABCELL_X16_Y39_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000011001111110011111100111111000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~3_combout\); + +-- Location: LABCELL_X16_Y39_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111110011001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~2_combout\); + +-- Location: LABCELL_X16_Y39_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~3_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000101000001010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~4_combout\); + +-- Location: MLABCELL_X18_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~4_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~4_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~4_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100010101111111110101010111111111000101011111111100010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~5_combout\); + +-- Location: FF_X18_Y37_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~5_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2)); + +-- Location: LABCELL_X17_Y36_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~1_combout\); + +-- Location: LABCELL_X14_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111111111111000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\); + +-- Location: LABCELL_X12_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector214~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011110011001100110000110011001100110011110000111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~1_combout\); + +-- Location: MLABCELL_X13_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector214~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector214~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector214~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010111101011111111100000010101000100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector214~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~0_combout\); + +-- Location: FF_X13_Y16_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)); + +-- Location: FF_X20_Y7_N32 +\myVirtualToplevel|SD_ADDR[0][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3), + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][3]~q\); + +-- Location: FF_X24_Y5_N47 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2), + sload => VCC, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(3)); + +-- Location: LABCELL_X19_Y9_N30 +\myVirtualToplevel|Mux80~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux80~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|SD_ADDR[0][3]~q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # ((\myVirtualToplevel|SD_HNDSHK_IN\(0))))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|SD_ADDR[0][3]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SD_HNDSHK_IN\(0)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110001001000000011000100101000101110011010100010111001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datac => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0), + datad => \myVirtualToplevel|ALT_INV_SD_ADDR[0][3]~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(3), + combout => \myVirtualToplevel|Mux80~0_combout\); + +-- Location: FF_X19_Y9_N31 +\myVirtualToplevel|IO_DATA_READ_SD[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux80~0_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(3)); + +-- Location: MLABCELL_X18_Y13_N33 +\myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ = ( !\myVirtualToplevel|MEM_DATA_READ[3]~92_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3~portbdataout\ & (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ +-- & (\myVirtualToplevel|IO_DATA_READ_SD\(3))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\)))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[3]~92_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11~portbdataout\)))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(3))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001000100001100110111010000110000010001001111111101110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(3), + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~92_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]~24_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\); + +-- Location: MLABCELL_X13_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~21_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\) +-- ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~99_Duplicate_158\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~21_combout\); + +-- Location: FF_X13_Y17_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_NEW_REG576\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~21_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM577\); + +-- Location: LABCELL_X7_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~20_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110011010111110011001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~99_Duplicate_158\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~20_combout\); + +-- Location: FF_X7_Y17_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_NEW_REG574\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM575\); + +-- Location: FF_X7_Y17_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_NEW_REG572\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM573\); + +-- Location: LABCELL_X7_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM573\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM577\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM573\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM577\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM573\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM575\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM573\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM575\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010111111110101111100000000001000101111111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM577\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM575\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM573\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\); + +-- Location: LABCELL_X25_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~277\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~277_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~277_combout\); + +-- Location: FF_X25_Y32_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~277_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\); + +-- Location: LABCELL_X26_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\); + +-- Location: LABCELL_X26_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000101011001110100100110101011100011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~4_combout\); + +-- Location: LABCELL_X26_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111000001010000010100100010011101111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~14_combout\); + +-- Location: LABCELL_X26_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100001111110100010000001100011101110011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~19_combout\); + +-- Location: LABCELL_X26_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010010001101100111000010011100110110101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~9_combout\); + +-- Location: LABCELL_X26_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~19_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~14_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~9_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~4_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~19_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\); + +-- Location: LABCELL_X17_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|tIdx~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tIdx~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000000000000000000000100010000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tIdx~0_combout\); + +-- Location: MLABCELL_X18_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tIdx~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tIdx~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100010101000001010001010100011011000010100001101100001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tIdx~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~0_combout\); + +-- Location: MLABCELL_X18_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001100000011110000110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~2_combout\); + +-- Location: LABCELL_X17_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8427\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8427_BDD8428\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100010101000000000001010100010001000111111000000000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8427_BDD8428\); + +-- Location: LABCELL_X17_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8425\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8425_BDD8426\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000110000001100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr171~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8425_BDD8426\); + +-- Location: MLABCELL_X18_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8425_BDD8426\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8427_BDD8428\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000100000000000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_RESYN8427_BDD8428\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_RESYN8425_BDD8426\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_combout\); + +-- Location: MLABCELL_X18_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000001100000000000000000000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~1_combout\); + +-- Location: MLABCELL_X18_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011011101111111111111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~3_combout\); + +-- Location: FF_X18_Y33_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)); + +-- Location: LABCELL_X16_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[1]_NEW2685\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[1]_OTERM2686\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101111111001010101000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[1]_OTERM2686\); + +-- Location: FF_X16_Y30_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[1]_OTERM2686\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)); + +-- Location: LABCELL_X14_Y28_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000001000010000000000010000100000000000100001000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\); + +-- Location: LABCELL_X17_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~5_combout\); + +-- Location: LABCELL_X25_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~49_sumout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~53_sumout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000100000000000100010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~49_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~53_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~4_combout\); + +-- Location: LABCELL_X25_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~5_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~5_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add0~65_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add0~61_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~5_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000000111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~61_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\); + +-- Location: FF_X25_Y17_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG502\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\); + +-- Location: MLABCELL_X18_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[2]~36_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\))) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111100101010001010100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~36_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]~25_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15_combout\); + +-- Location: LABCELL_X12_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2)) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111001111110011111100001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~17_combout\); + +-- Location: FF_X12_Y15_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG512\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM513\); + +-- Location: LABCELL_X12_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15_combout\))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100110001000000010111110101000001111111011100110101111101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~16_combout\); + +-- Location: FF_X12_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG510\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~16_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM511\); + +-- Location: FF_X12_Y15_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG506\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM507\); + +-- Location: LABCELL_X12_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM507\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM507\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM511\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM513\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM507\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM511\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM513\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011111111110001101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM513\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM511\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM507\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\); + +-- Location: LABCELL_X25_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_RESYN12692\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_RESYN12692_BDD12693\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000100000001000000010000001000000010000000100000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_RESYN12692_BDD12693\); + +-- Location: LABCELL_X25_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_RESYN12692_BDD12693\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000010000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~0_RESYN12692_BDD12693\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_combout\); + +-- Location: LABCELL_X25_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_RESYN12754\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_RESYN12754_BDD12755\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000001100110011000000110000111100000011000011110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_RESYN12754_BDD12755\); + +-- Location: LABCELL_X25_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_RESYN12754_BDD12755\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000000111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~4_RESYN12754_BDD12755\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_combout\); + +-- Location: LABCELL_X25_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_RESYN12746\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_RESYN12746_BDD12747\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_RESYN12746_BDD12747\); + +-- Location: LABCELL_X25_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_RESYN12746_BDD12747\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000001000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~3_RESYN12746_BDD12747\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_combout\); + +-- Location: LABCELL_X25_Y37_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_RESYN12756\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_RESYN12756_BDD12757\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100100001001000010010000100110000000100000001000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_RESYN12756_BDD12757\); + +-- Location: LABCELL_X25_Y37_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_RESYN12756_BDD12757\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~5_RESYN12756_BDD12757\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_combout\); + +-- Location: LABCELL_X25_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111111111111111011111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\); + +-- Location: MLABCELL_X23_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~158\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~158_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~158_combout\); + +-- Location: FF_X23_Y29_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~158_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\); + +-- Location: LABCELL_X20_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~159\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~159_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~159_combout\); + +-- Location: FF_X20_Y30_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~159_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\); + +-- Location: FF_X23_Y29_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~156_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\); + +-- Location: MLABCELL_X23_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~156\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~156_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~156_combout\); + +-- Location: FF_X23_Y29_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~156_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~157\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~157_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~157_combout\); + +-- Location: FF_X20_Y30_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~157_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\); + +-- Location: LABCELL_X19_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~0_combout\); + +-- Location: MLABCELL_X23_Y39_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~5_combout\); + +-- Location: MLABCELL_X23_Y40_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~4_combout\); + +-- Location: MLABCELL_X23_Y39_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000001000000000000100100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~2_combout\); + +-- Location: MLABCELL_X23_Y39_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000010010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~6_combout\); + +-- Location: MLABCELL_X23_Y39_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011110000000000000000000000000000000000000011000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~64_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~3_combout\); + +-- Location: MLABCELL_X23_Y39_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\); + +-- Location: MLABCELL_X23_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~162\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~162_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000000001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~162_combout\); + +-- Location: FF_X23_Y29_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~162_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\); + +-- Location: MLABCELL_X23_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~161\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~161_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010000001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~161_combout\); + +-- Location: FF_X23_Y29_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~161_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~q\); + +-- Location: MLABCELL_X23_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~163\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~163_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010000001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~163_combout\); + +-- Location: FF_X23_Y29_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~163_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\); + +-- Location: MLABCELL_X23_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~160\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~160_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000000001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~160_combout\); + +-- Location: FF_X23_Y29_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~160_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\); + +-- Location: MLABCELL_X23_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011110011111100111101000100011101110100010001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~1_combout\); + +-- Location: LABCELL_X21_Y38_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12764\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12764_BDD12765\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\)) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101000000000000000001111111100000000000011010000000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12764_BDD12765\); + +-- Location: LABCELL_X21_Y37_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71_combout\); + +-- Location: LABCELL_X21_Y38_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12510\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12510_BDD12511\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12510_BDD12511\); + +-- Location: LABCELL_X21_Y38_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12766\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12766_BDD12767\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12510_BDD12511\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12510_BDD12511\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111000000000110011100000000011101110000000001110111000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_RESYN12510_BDD12511\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12766_BDD12767\); + +-- Location: LABCELL_X21_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12762\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12762_BDD12763\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000000000000000000000000000110000111100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~71_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12762_BDD12763\); + +-- Location: LABCELL_X21_Y38_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12766_BDD12767\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12762_BDD12763\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) # (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12766_BDD12767\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12762_BDD12763\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12766_BDD12767\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12762_BDD12763\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12764_BDD12765\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100111111111101011111010111110101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~69_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12764_BDD12765\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~71_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12766_BDD12767\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12762_BDD12763\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\); + +-- Location: LABCELL_X20_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~166\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~166_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~166_combout\); + +-- Location: FF_X20_Y31_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~166_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\); + +-- Location: LABCELL_X20_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~164\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~164_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111101111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~164_combout\); + +-- Location: FF_X20_Y33_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~164_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\); + +-- Location: LABCELL_X25_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~167\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~167_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~167_combout\); + +-- Location: FF_X25_Y31_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~167_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~q\); + +-- Location: LABCELL_X20_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~165\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~165_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111110100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~165_combout\); + +-- Location: FF_X20_Y33_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~165_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\); + +-- Location: LABCELL_X19_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~q\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000100111001101101000110110011100101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~2_combout\); + +-- Location: LABCELL_X1_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100000000010000010000000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~76_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~6_combout\); + +-- Location: LABCELL_X2_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~5_combout\); + +-- Location: LABCELL_X1_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000101010100000000000000100000000000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~76_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~77_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~3_combout\); + +-- Location: LABCELL_X1_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0110000000000000011000000000000000000010000000000000001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~78_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~4_combout\); + +-- Location: LABCELL_X1_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\); + +-- Location: LABCELL_X20_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~171\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~171_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~171_combout\); + +-- Location: FF_X20_Y30_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~171_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\); + +-- Location: FF_X20_Y30_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~168_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\); + +-- Location: LABCELL_X20_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~168\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~168_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~168_combout\); + +-- Location: FF_X20_Y30_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~168_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~DUPLICATE_q\); + +-- Location: FF_X20_Y30_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~169_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\); + +-- Location: LABCELL_X20_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~169\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~169_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~169_combout\); + +-- Location: FF_X20_Y30_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~169_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~DUPLICATE_q\); + +-- Location: FF_X20_Y30_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~170_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\); + +-- Location: LABCELL_X20_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~170\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~170_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~170_combout\); + +-- Location: FF_X20_Y30_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~170_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~3_combout\); + +-- Location: LABCELL_X19_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~1_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~1_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~1_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010010011000110111000011001001110110101110101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\); + +-- Location: LABCELL_X20_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_RESYN9207\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_RESYN9207_BDD9208\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000000001100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_RESYN9207_BDD9208\); + +-- Location: LABCELL_X20_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_RESYN9207_BDD9208\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_RESYN9207_BDD9208\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_RESYN9207_BDD9208\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000000000000000000000010101110101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~24_RESYN9207_BDD9208\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_combout\); + +-- Location: LABCELL_X20_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|state~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|state~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~24_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~28_combout\); + +-- Location: LABCELL_X20_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|state~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|state~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|state~28_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101100001111101111110000111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~28_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~29_combout\); + +-- Location: FF_X20_Y32_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|state~29_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\); + +-- Location: MLABCELL_X4_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\); + +-- Location: MLABCELL_X18_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\); + +-- Location: MLABCELL_X18_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|state~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|state~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000100000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~23_combout\); + +-- Location: MLABCELL_X18_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|state~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|state~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state~23_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|state~23_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|state~23_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100000000000000001100000000001111110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~23_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~24_combout\); + +-- Location: FF_X18_Y33_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|state~24_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\); + +-- Location: LABCELL_X17_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101010000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\); + +-- Location: LABCELL_X16_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\); + +-- Location: LABCELL_X16_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\); + +-- Location: FF_X10_Y35_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\); + +-- Location: FF_X7_Y35_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1065\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066\); + +-- Location: MLABCELL_X13_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000110011000000000011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\); + +-- Location: LABCELL_X16_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000111111111000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\); + +-- Location: LABCELL_X17_Y34_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector638~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~0_combout\); + +-- Location: LABCELL_X12_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\); + +-- Location: MLABCELL_X13_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\); + +-- Location: LABCELL_X16_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector638~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011011100000101001101110000010100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~1_combout\); + +-- Location: LABCELL_X16_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector638~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector638~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111111111111001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~2_combout\); + +-- Location: LABCELL_X16_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector638~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector638~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000001011111111100001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~3_combout\); + +-- Location: FF_X16_Y34_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1154\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\); + +-- Location: LABCELL_X12_Y35_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101010000000001110111011100110101010101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\); + +-- Location: FF_X7_Y35_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG977\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\); + +-- Location: LABCELL_X17_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector572~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~0_combout\); + +-- Location: LABCELL_X14_Y35_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector572~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000000000000000001010111110100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~1_combout\); + +-- Location: LABCELL_X17_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector572~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector572~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101011111111111010101100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~2_combout\); + +-- Location: LABCELL_X17_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector572~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~2_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector572~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001100110011001101111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~3_combout\); + +-- Location: FF_X17_Y35_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG979\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\); + +-- Location: LABCELL_X7_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\)) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\ +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101011111000000000101110100001111000011110000000000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\); + +-- Location: FF_X10_Y35_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1107\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1108\); + +-- Location: MLABCELL_X13_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001111100010001000111110001000100010001000100010001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~4_combout\); + +-- Location: MLABCELL_X13_Y35_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111111111110101111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~5_combout\); + +-- Location: MLABCELL_X13_Y35_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~3_combout\); + +-- Location: MLABCELL_X13_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~5_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~5_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100010011001100110000001100000011000100110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector501~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~6_combout\); + +-- Location: FF_X13_Y35_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1109\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1110\); + +-- Location: LABCELL_X10_Y35_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1108\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1110\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\)) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1108\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1110\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\)))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1108\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1110\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011101110101011101100000000000000001011101010111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1108\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1110\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\); + +-- Location: FF_X10_Y35_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1156\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1157\); + +-- Location: LABCELL_X16_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector704~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~0_combout\); + +-- Location: LABCELL_X16_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector704~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)))) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000101111001000100010111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~1_combout\); + +-- Location: LABCELL_X16_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector704~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector704~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111111111110101111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~2_combout\); + +-- Location: LABCELL_X16_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~0_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector704~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001101110011111100110111001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\); + +-- Location: FF_X16_Y34_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1158\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1159\); + +-- Location: LABCELL_X10_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1157\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1159\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1157\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1159\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1157\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1159\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011101011111010101100000000000000001010111110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1157\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1159\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\); + +-- Location: LABCELL_X12_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux8~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101000100110011110100010000000011011101111100111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~1_combout\); + +-- Location: MLABCELL_X13_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector968~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001110101011000000111010101100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~1_combout\); + +-- Location: MLABCELL_X13_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector968~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector968~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110101111111111111010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~2_combout\); + +-- Location: LABCELL_X12_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector968~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~0_combout\); + +-- Location: LABCELL_X12_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector968~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector968~2_combout\ +-- & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~2_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector968~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000000000000000010101000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~3_combout\); + +-- Location: FF_X12_Y34_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG983\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM984\); + +-- Location: FF_X9_Y34_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\); + +-- Location: FF_X12_Y34_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG981\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\); + +-- Location: LABCELL_X12_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM984\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM984\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM984\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010000000100000001011111111000011111111111100000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM984\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\); + +-- Location: FF_X12_Y34_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1051\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1052\); + +-- Location: MLABCELL_X13_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector902~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\)))) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001001111010001000100111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~1_combout\); + +-- Location: MLABCELL_X13_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector902~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector902~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101111111111111010111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~2_combout\); + +-- Location: LABCELL_X14_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector902~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~0_combout\); + +-- Location: MLABCELL_X13_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector902~2_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector902~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector902~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector902~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector902~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector902~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000110001001100110011000100110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\); + +-- Location: FF_X13_Y35_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1053\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1054\); + +-- Location: LABCELL_X12_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1052\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1054\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1052\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1054\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1052\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1054\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011101110101011101100000000000000001011101010111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1052\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1054\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\); + +-- Location: LABCELL_X16_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector770~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~0_combout\); + +-- Location: LABCELL_X12_Y34_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector770~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\)))) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000101111001000100010111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~1_combout\); + +-- Location: LABCELL_X12_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector770~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector770~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector770~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011011101000000001101110100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~2_combout\); + +-- Location: LABCELL_X12_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector770~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector770~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector770~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector770~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~2_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000100110000000000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~3_combout\); + +-- Location: FF_X12_Y34_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1218\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1219\); + +-- Location: FF_X12_Y34_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1216\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\); + +-- Location: LABCELL_X12_Y34_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1219\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1219\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1219\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000000000000011000011111111111111110000000010111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1219\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\); + +-- Location: MLABCELL_X13_Y35_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector836~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~0_combout\); + +-- Location: MLABCELL_X13_Y35_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector836~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000111011000010100011101100000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~1_combout\); + +-- Location: MLABCELL_X13_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector836~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector836~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector836~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000010100000111100001010000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~2_combout\); + +-- Location: MLABCELL_X13_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~0_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector836~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001101110011111100110111001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\); + +-- Location: FF_X13_Y35_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1202\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1203\); + +-- Location: FF_X9_Y35_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1200\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1201\); + +-- Location: MLABCELL_X9_Y35_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1203\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1201\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\)) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1203\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1201\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\)))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1203\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1201\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000000000000000011001111110011011100111111001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1203\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1201\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\); + +-- Location: LABCELL_X12_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux8~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\))) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011101010100001101101010101000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~0_combout\); + +-- Location: LABCELL_X12_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux8~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux8~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux8~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux8~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~2_combout\); + +-- Location: MLABCELL_X9_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|Mux8~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\); + +-- Location: LABCELL_X10_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111010011110000111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~2_combout\); + +-- Location: FF_X10_Y17_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~2_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\); + +-- Location: LABCELL_X7_Y16_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector301~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector301~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001111000010100000111101011111000011110101111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~62_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector301~0_combout\); + +-- Location: FF_X7_Y16_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_NEW_REG753\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector301~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM754\); + +-- Location: FF_X6_Y18_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_NEW_REG749\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM750\); + +-- Location: LABCELL_X6_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM750\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM754\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM750\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM754\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM750\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]~12_combout\); + +-- Location: LABCELL_X6_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[0]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[0]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001010111000000100101011110001010110111111000101011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[0]~4_combout\); + +-- Location: LABCELL_X20_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~48_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100000000000100010000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~48_combout\); + +-- Location: LABCELL_X20_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011101100000010101110110000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~48_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\); + +-- Location: LABCELL_X20_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_RESYN12520\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_RESYN12520_BDD12521\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000011001100110000001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_RESYN12520_BDD12521\); + +-- Location: LABCELL_X20_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_RESYN12520_BDD12521\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_RESYN12520_BDD12521\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001110101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~1_RESYN12520_BDD12521\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_combout\); + +-- Location: LABCELL_X20_Y35_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010001000000000001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~2_combout\); + +-- Location: LABCELL_X20_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~50_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100000001000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~50_combout\); + +-- Location: LABCELL_X20_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~50_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000100000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~50_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~47_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\); + +-- Location: LABCELL_X19_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~3_combout\); + +-- Location: FF_X19_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~3_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\); + +-- Location: LABCELL_X2_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000100000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~5_combout\); + +-- Location: LABCELL_X1_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~5_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "1111111011111110111111111111110110101010101010100111011101110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~76_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~5_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~77_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~7_combout\); + +-- Location: LABCELL_X2_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux135~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux135~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux135~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux135~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux133~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000000011110000000010100000000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux133~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux135~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~3_combout\); + +-- Location: LABCELL_X1_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100000000000000010000000100100001000000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~76_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~78_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~4_combout\); + +-- Location: LABCELL_X1_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\); + +-- Location: LABCELL_X19_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~113\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~113_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100111111111111111000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~113_combout\); + +-- Location: FF_X19_Y31_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~113_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\); + +-- Location: MLABCELL_X23_Y39_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000001100000001000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~4_combout\); + +-- Location: LABCELL_X19_Y38_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_RESYN12522\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_RESYN12522_BDD12523\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101101000000101010110100000010100001010000000000000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_RESYN12522_BDD12523\); + +-- Location: LABCELL_X19_Y38_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_RESYN12522_BDD12523\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_RESYN12522_BDD12523\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000010000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~3_RESYN12522_BDD12523\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_combout\); + +-- Location: LABCELL_X19_Y38_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux121~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux121~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux121~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\))))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux121~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100100000000000110010000000000011001000000000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux123~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux121~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~2_combout\); + +-- Location: LABCELL_X19_Y38_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\); + +-- Location: LABCELL_X19_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~112\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~112_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000111111111111111100000000000000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~112_combout\); + +-- Location: FF_X19_Y31_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~112_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\); + +-- Location: LABCELL_X20_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12750\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12750_BDD12751\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001000100010001000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12750_BDD12751\); + +-- Location: LABCELL_X20_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12750_BDD12751\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12750_BDD12751\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100000000000000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_RESYN12750_BDD12751\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_combout\); + +-- Location: LABCELL_X20_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_RESYN12512\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_RESYN12512_BDD12513\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000000000110000000000000000110000000000000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_RESYN12512_BDD12513\); + +-- Location: LABCELL_X20_Y34_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_RESYN12512_BDD12513\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_RESYN12512_BDD12513\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000010000000000000100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~1_RESYN12512_BDD12513\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_combout\); + +-- Location: LABCELL_X20_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_RESYN12514\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_RESYN12514_BDD12515\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100010001000100010001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_RESYN12514_BDD12515\); + +-- Location: LABCELL_X20_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_RESYN12514_BDD12515\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_RESYN12514_BDD12515\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000100000000010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~2_RESYN12514_BDD12515\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_combout\); + +-- Location: LABCELL_X20_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\); + +-- Location: LABCELL_X21_Y38_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal46~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal46~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal46~0_combout\); + +-- Location: LABCELL_X21_Y38_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~102\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~102_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal46~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001000000000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~69_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal46~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~102_combout\); + +-- Location: LABCELL_X21_Y38_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011101010001100001110101000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~71_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~7_combout\); + +-- Location: LABCELL_X21_Y38_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~102_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\)))) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111100000000111011110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~102_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\); + +-- Location: LABCELL_X21_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12526\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12526_BDD12527\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000110011000000000011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12526_BDD12527\); + +-- Location: LABCELL_X21_Y38_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12524\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12524_BDD12525\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101111111111111111100001111000011111101111111111111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12524_BDD12525\); + +-- Location: LABCELL_X21_Y38_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12524_BDD12525\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal46~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12526_BDD12527\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12524_BDD12525\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12524_BDD12525\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal46~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12526_BDD12527\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12524_BDD12525\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12526_BDD12527\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000111110110000000011111111000000001111111000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal46~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_RESYN12526_BDD12527\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~69_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_RESYN12524_BDD12525\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\); + +-- Location: MLABCELL_X18_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111111111111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~6_combout\); + +-- Location: FF_X18_Y32_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~6_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\); + +-- Location: LABCELL_X19_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~5_combout\); + +-- Location: LABCELL_X20_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~434\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~434_combout\ = ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~0_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~434_combout\); + +-- Location: MLABCELL_X28_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9247\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9247_BDD9248\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000001111111110000000111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9247_BDD9248\); + +-- Location: LABCELL_X29_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9245\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9245_BDD9246\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000101010101010100010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~19_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9245_BDD9246\); + +-- Location: MLABCELL_X28_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9245_BDD9246\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9247_BDD9248\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9245_BDD9246\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9247_BDD9248\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111010111110001111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_RESYN9247_BDD9248\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~24_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_RESYN9245_BDD9246\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_combout\); + +-- Location: LABCELL_X19_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~434_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~434_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000000000000000000000000000010100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~434_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\); + +-- Location: LABCELL_X19_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~122\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~122_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010100010101011111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~122_combout\); + +-- Location: FF_X19_Y30_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~122_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\); + +-- Location: LABCELL_X19_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~125\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~125_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000111111111111111100000000000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~125_combout\); + +-- Location: FF_X19_Y30_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~125_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\); + +-- Location: LABCELL_X19_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~124\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~124_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101010101001111111111111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~124_combout\); + +-- Location: FF_X19_Y30_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~124_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~q\); + +-- Location: LABCELL_X19_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~123\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~123_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000111111111111111100000000000000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~123_combout\); + +-- Location: FF_X19_Y30_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~123_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\); + +-- Location: LABCELL_X19_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~8_combout\); + +-- Location: MLABCELL_X18_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~117\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~117_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000111111111111111100000000000000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~117_combout\); + +-- Location: FF_X18_Y32_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~117_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\); + +-- Location: MLABCELL_X18_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~114\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~114_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000111110111111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~114_combout\); + +-- Location: FF_X18_Y32_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~114_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\); + +-- Location: MLABCELL_X18_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~115\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~115_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000111111111111111100000000000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~115_combout\); + +-- Location: FF_X18_Y32_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~115_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\); + +-- Location: MLABCELL_X18_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~116\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~116_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011001100101111111111111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~116_combout\); + +-- Location: FF_X18_Y32_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~116_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~q\); + +-- Location: MLABCELL_X18_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~6_combout\); + +-- Location: MLABCELL_X18_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~118\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~118_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101010100011111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~118_combout\); + +-- Location: FF_X18_Y32_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~118_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\); + +-- Location: MLABCELL_X18_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~121\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~121_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000111111111111111100000000000000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~121_combout\); + +-- Location: FF_X18_Y32_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~121_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\); + +-- Location: MLABCELL_X18_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~120\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~120_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101010101001111111111111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~120_combout\); + +-- Location: FF_X18_Y32_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~120_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~q\); + +-- Location: MLABCELL_X18_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~119\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~119_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000111111111111111100000000000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~119_combout\); + +-- Location: FF_X18_Y32_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~119_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~q\); + +-- Location: MLABCELL_X18_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~7_combout\); + +-- Location: MLABCELL_X18_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~5_combout\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~8_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~8_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~5_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000011001010011000101110100101010001110110110111001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\); + +-- Location: MLABCELL_X18_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101100001010000110110000101000010001000000000001000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\); + +-- Location: MLABCELL_X28_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000011000000000000001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\); + +-- Location: MLABCELL_X28_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr160~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr160~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101001000000100001000000000000000001001000010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr160~0_combout\); + +-- Location: MLABCELL_X28_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8639\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8639_BDD8640\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr160~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr160~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001010000010100000000000000000000110100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~38_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr160~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8639_BDD8640\); + +-- Location: LABCELL_X19_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8641\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8641_BDD8642\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8641_BDD8642\); + +-- Location: LABCELL_X19_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8641_BDD8642\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8639_BDD8640\ +-- & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8641_BDD8642\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8639_BDD8640\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8641_BDD8642\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8639_BDD8640\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000001000000101000001010000110100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[21]~1_RESYN8639_BDD8640\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[21]~1_RESYN8641_BDD8642\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\); + +-- Location: FF_X20_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~DUPLICATE_q\); + +-- Location: FF_X20_Y18_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(11)); + +-- Location: LABCELL_X20_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\); + +-- Location: MLABCELL_X18_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~8_combout\); + +-- Location: MLABCELL_X18_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111000000000100011101000100010001110100010001000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~57_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~9_combout\); + +-- Location: MLABCELL_X18_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~65_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~65_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~65_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~65_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111001100111100001100000010101010100010001010000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~65_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~10_combout\); + +-- Location: MLABCELL_X18_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add36~71_sumout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100100001001000010010000100100001001111111110000100111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~71_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~11_combout\); + +-- Location: MLABCELL_X18_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111001010100010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~12_combout\); + +-- Location: MLABCELL_X18_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~12_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~8_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~12_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000000000000001100000000000000111000000000000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~13_combout\); + +-- Location: FF_X2_Y33_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult[11]_NEW_REG1226\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~16_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|divResult[11]_OTERM1227\); + +-- Location: LABCELL_X2_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|divResult~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divResult~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult[11]_OTERM1227\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1183\ & \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|divResult[11]_OTERM1227\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111111000000011111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1183\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM902\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[11]_OTERM1227\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divResult~16_combout\); + +-- Location: LABCELL_X2_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divResult~16_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divResult~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~0_combout\); + +-- Location: LABCELL_X5_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(11) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111110000111100001111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~1_combout\); + +-- Location: LABCELL_X21_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010110010001100100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~2_combout\); + +-- Location: LABCELL_X16_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001101011010010110100111101101111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~5_combout\); + +-- Location: LABCELL_X16_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~5_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011111010001100100011001000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~6_combout\); + +-- Location: LABCELL_X20_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Add33~65_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add34~65_sumout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add33~65_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100001111001111110000111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~65_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~4_combout\); + +-- Location: MLABCELL_X13_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~67\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~67_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~40_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~67_combout\); + +-- Location: MLABCELL_X13_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~63\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~63_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000111111111111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~32_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~63_combout\); + +-- Location: MLABCELL_X13_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~65_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~65_combout\); + +-- Location: MLABCELL_X13_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~64\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~64_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100001101001111010000000111110001110011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~27_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~35_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~64_combout\); + +-- Location: MLABCELL_X13_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~66\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~66_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~64_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~65_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~63_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~64_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS~65_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~63_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000110011111100000011001110100000001000101010000000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~63_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~65_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~64_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~66_combout\); + +-- Location: MLABCELL_X13_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~66_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~66_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~67_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~66_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~66_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~67_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010100000111100000001000000010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~67_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~66_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~3_combout\); + +-- Location: LABCELL_X21_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001000000010100000100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~7_combout\); + +-- Location: LABCELL_X21_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~0_combout\); + +-- Location: LABCELL_X21_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~1_combout\); + +-- Location: LABCELL_X21_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101000011010000110100001101000011010000110100001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~2_combout\); + +-- Location: LABCELL_X21_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~7_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~13_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector994~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100001011111111110000101011111111000010111111111100001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~3_combout\); + +-- Location: FF_X21_Y22_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~3_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(11)); + +-- Location: LABCELL_X21_Y22_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(11) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(11) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(11) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\); + +-- Location: LABCELL_X20_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~23_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~23_combout\); + +-- Location: MLABCELL_X23_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~23_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\)))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~23_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111101011111111110010101100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\); + +-- Location: LABCELL_X21_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~93_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~94\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~93_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~94\); + +-- Location: LABCELL_X21_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~89_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~94\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~90\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~94\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~94\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~89_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~90\); + +-- Location: LABCELL_X21_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~90\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~22\); + +-- Location: LABCELL_X21_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~26\); + +-- Location: LABCELL_X21_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~30\); + +-- Location: LABCELL_X21_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~34\); + +-- Location: LABCELL_X21_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~18\); + +-- Location: LABCELL_X21_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~14\); + +-- Location: LABCELL_X21_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~10\); + +-- Location: LABCELL_X21_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~6\); + +-- Location: LABCELL_X21_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~38\); + +-- Location: LABCELL_X21_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~50\); + +-- Location: MLABCELL_X23_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~101\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~101_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~49_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~49_sumout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~49_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~49_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010111111111111111110000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~49_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~101_combout\); + +-- Location: LABCELL_X26_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~34\); + +-- Location: LABCELL_X26_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~18\); + +-- Location: LABCELL_X26_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~14\); + +-- Location: LABCELL_X26_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~10\); + +-- Location: LABCELL_X26_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~6\); + +-- Location: LABCELL_X26_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~38\); + +-- Location: LABCELL_X26_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~50\); + +-- Location: LABCELL_X29_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~42\); + +-- Location: LABCELL_X29_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~38\); + +-- Location: LABCELL_X29_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~34\); + +-- Location: LABCELL_X29_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~30\); + +-- Location: LABCELL_X29_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~26\); + +-- Location: LABCELL_X29_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~46\); + +-- Location: LABCELL_X29_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~58\); + +-- Location: LABCELL_X24_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~34\); + +-- Location: LABCELL_X24_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~26\); + +-- Location: LABCELL_X24_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~22\); + +-- Location: LABCELL_X24_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~18\); + +-- Location: LABCELL_X24_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~14\); + +-- Location: LABCELL_X24_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~38\); + +-- Location: LABCELL_X24_Y28_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~50\); + +-- Location: LABCELL_X29_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~38\); + +-- Location: LABCELL_X29_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~34\); + +-- Location: LABCELL_X29_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~30\); + +-- Location: LABCELL_X29_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~26\); + +-- Location: LABCELL_X29_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~22\); + +-- Location: LABCELL_X29_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~42\); + +-- Location: LABCELL_X29_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~54\); + +-- Location: LABCELL_X25_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001000000000000000000000001000100010000000000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\); + +-- Location: MLABCELL_X23_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~98\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~98_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~49_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~57_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~49_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~53_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~49_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~57_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~49_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~53_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~98_combout\); + +-- Location: MLABCELL_X23_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~102\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~102_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~101_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~98_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~101_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~98_combout\ & +-- ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~99_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~100_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~101_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~98_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~101_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~98_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~99_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~100_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111111111111111111111111100111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~100_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~99_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~101_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~98_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~102_combout\); + +-- Location: FF_X23_Y25_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~102_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]_NEW3274\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]_OTERM3275\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~65_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~65_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]_OTERM3275\); + +-- Location: FF_X25_Y24_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]_OTERM3275\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11)); + +-- Location: LABCELL_X26_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_RESYN12626\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_RESYN12626_BDD12627\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~69_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~93_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~73_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~65_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~89_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~93_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~73_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~65_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~89_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~69_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_RESYN12626_BDD12627\); + +-- Location: LABCELL_X26_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_RESYN12626_BDD12627\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~81_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~77_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~85_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~53_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~81_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~77_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~85_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~53_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~61_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_RESYN12626_BDD12627\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\); + +-- Location: LABCELL_X21_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_RESYN8921\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_RESYN8921_BDD8922\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_RESYN8921_BDD8922\); + +-- Location: LABCELL_X21_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_RESYN8921_BDD8922\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_RESYN8921_BDD8922\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111100110101010101010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_RESYN8921_BDD8922\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\); + +-- Location: LABCELL_X25_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~166\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~166_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101000100010101010100010011010101110001001101010111000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~165_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~166_combout\); + +-- Location: LABCELL_X25_Y26_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9237\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9237_BDD9238\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~166_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~166_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~41_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~166_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9237_BDD9238\); + +-- Location: LABCELL_X21_Y28_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~78\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~78_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000000000000000000010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~41_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~78_combout\); + +-- Location: LABCELL_X20_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~23_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~23_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\); + +-- Location: LABCELL_X20_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_RESYN8603\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_RESYN8603_BDD8604\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5)))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111101010101111000011001100110011001000100011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~41_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_RESYN8603_BDD8604\); + +-- Location: LABCELL_X20_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_RESYN8603_BDD8604\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add32~33_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_RESYN8603_BDD8604\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add32~33_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add32~33_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011100000111011101110000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~81_RESYN8603_BDD8604\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_combout\); + +-- Location: LABCELL_X21_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9239\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9239_BDD9240\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~78_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~165_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~78_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~81_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9239_BDD9240\); + +-- Location: LABCELL_X20_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9235\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9235_BDD9236\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~78_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111100000000010111110000000001010111000000000101111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~165_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~78_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~23_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~81_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9235_BDD9236\); + +-- Location: LABCELL_X25_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~77_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~33_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~33_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~41_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~37_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~37_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~41_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~77_combout\); + +-- Location: LABCELL_X20_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~5_combout\); + +-- Location: LABCELL_X21_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~6_combout\); + +-- Location: LABCELL_X19_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~7_combout\); + +-- Location: LABCELL_X20_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~4_combout\); + +-- Location: LABCELL_X20_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~7_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~8_combout\); + +-- Location: LABCELL_X20_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(19) & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(1) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[18]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~9_combout\); + +-- Location: LABCELL_X19_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~14_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(2) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(3))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100000000000100010000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~14_combout\); + +-- Location: LABCELL_X19_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9213\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9213_BDD9214\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(13) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(6) & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(7)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9213_BDD9214\); + +-- Location: LABCELL_X19_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(17) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(14))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[15]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~8_combout\); + +-- Location: LABCELL_X20_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~13_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~13_combout\); + +-- Location: FF_X18_Y17_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(31)); + +-- Location: FF_X18_Y17_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~DUPLICATE_q\); + +-- Location: FF_X18_Y17_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(27)); + +-- Location: FF_X18_Y17_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(28)); + +-- Location: FF_X20_Y18_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~10_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(27) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(28))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[29]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[26]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~10_combout\); + +-- Location: LABCELL_X19_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(22) & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(20) & !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(23))) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~11_combout\); + +-- Location: LABCELL_X19_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~12_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(31) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(25) & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(24) & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000100000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(31), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~12_combout\); + +-- Location: LABCELL_X19_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9215\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9215_BDD9216\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9213_BDD9214\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~13_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_RESYN9213_BDD9214\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9215_BDD9216\); + +-- Location: LABCELL_X20_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9215_BDD9216\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9215_BDD9216\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000010000000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_RESYN9215_BDD9216\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_combout\); + +-- Location: LABCELL_X19_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~2_combout\); + +-- Location: LABCELL_X20_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_RESYN12460\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_RESYN12460_BDD12461\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_RESYN12460_BDD12461\); + +-- Location: LABCELL_X20_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_RESYN12460_BDD12461\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ +-- & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000100000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~1_RESYN12460_BDD12461\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_combout\); + +-- Location: LABCELL_X20_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_RESYN9217\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_RESYN9217_BDD9218\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_RESYN9217_BDD9218\); + +-- Location: LABCELL_X20_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_RESYN9217_BDD9218\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_RESYN9217_BDD9218\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_RESYN9217_BDD9218\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_RESYN9217_BDD9218\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000000000110011000000000010001000000000001000110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_RESYN9217_BDD9218\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~24_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\); + +-- Location: MLABCELL_X23_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_RESYN9307\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_RESYN9307_BDD9308\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111110111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_RESYN9307_BDD9308\); + +-- Location: MLABCELL_X23_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_RESYN9307_BDD9308\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000000001111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~164_RESYN9307_BDD9308\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_combout\); + +-- Location: LABCELL_X24_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000100010101010101010001010101010001000101010101000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~17_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~164_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51_combout\); + +-- Location: LABCELL_X25_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~77_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9237_BDD9238\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~77_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9237_BDD9238\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~77_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~166_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9235_BDD9236\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~77_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9239_BDD9240\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9235_BDD9236\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~166_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111111111000011111111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9237_BDD9238\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9239_BDD9240\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9235_BDD9236\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~166_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~77_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~51_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_combout\); + +-- Location: FF_X25_Y26_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~34\); + +-- Location: LABCELL_X31_Y26_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_RESYN12684\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_RESYN12684_BDD12685\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001010000011110000101000001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_RESYN12684_BDD12685\); + +-- Location: LABCELL_X31_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_RESYN12684_BDD12685\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_RESYN12684_BDD12685\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110111111101100000000000000001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~43_RESYN12684_BDD12685\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_combout\); + +-- Location: MLABCELL_X28_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9221\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9221_BDD9222\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010101010101000001010101010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9221_BDD9222\); + +-- Location: LABCELL_X24_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9223\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9223_BDD9224\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110111001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9223_BDD9224\); + +-- Location: MLABCELL_X28_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9223_BDD9224\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9221_BDD9222\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9223_BDD9224\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9221_BDD9222\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9223_BDD9224\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9221_BDD9222\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9223_BDD9224\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9221_BDD9222\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000101000001010000010100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_RESYN9221_BDD9222\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_RESYN9223_BDD9224\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_combout\); + +-- Location: LABCELL_X25_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~19_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111000000000000011110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~19_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\); + +-- Location: LABCELL_X25_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011001000110000001100100011000000110000001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\); + +-- Location: LABCELL_X31_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_RESYN8599\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_RESYN8599_BDD8600\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~33_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~33_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111110011001010101011110000111100001100000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_RESYN8599_BDD8600\); + +-- Location: LABCELL_X31_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_RESYN8599_BDD8600\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add32~13_sumout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_RESYN8599_BDD8600\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add32~13_sumout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111110101100000011001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~13_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~48_RESYN8599_BDD8600\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_combout\); + +-- Location: LABCELL_X31_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~33_sumout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~45_combout\); + +-- Location: LABCELL_X31_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~13_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~33_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~21_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~29_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~13_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~29_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~44_combout\); + +-- Location: LABCELL_X31_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~44_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~45_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~44_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~45_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101110101010101110111010101010110000101000001011000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~45_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~44_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~49_combout\); + +-- Location: LABCELL_X31_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~49_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~49_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add37~33_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~49_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~49_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~33_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001111111111111000011111111111100011111000111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~43_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~26_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~49_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~50_combout\); + +-- Location: FF_X31_Y26_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~50_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~30\); + +-- Location: LABCELL_X21_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_RESYN12682\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_RESYN12682_BDD12683\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001000000010000000100000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_RESYN12682_BDD12683\); + +-- Location: LABCELL_X21_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_RESYN12682_BDD12683\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_RESYN12682_BDD12683\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111100111111111111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~35_RESYN12682_BDD12683\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_combout\); + +-- Location: MLABCELL_X23_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~29_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~37_combout\); + +-- Location: MLABCELL_X23_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_RESYN8597\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_RESYN8597_BDD8598\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~29_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111110000000011011000110110001101100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~29_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_RESYN8597_BDD8598\); + +-- Location: MLABCELL_X23_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_RESYN8597_BDD8598\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_RESYN8597_BDD8598\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_RESYN8597_BDD8598\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_RESYN8597_BDD8598\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001000100010001000000000001100000000000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~40_RESYN8597_BDD8598\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_combout\); + +-- Location: MLABCELL_X23_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~9_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~29_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~17_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~25_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~29_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~25_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~36_combout\); + +-- Location: MLABCELL_X23_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~36_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~37_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~37_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~37_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~40_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~36_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~41_combout\); + +-- Location: MLABCELL_X28_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~41_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~41_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~29_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~41_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~41_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~29_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001111111111111000011111111111100011111000111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~29_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~35_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~26_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~41_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~42_combout\); + +-- Location: FF_X28_Y26_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~42_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_RESYN12680\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_RESYN12680_BDD12681\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100000011000000110011001100110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_RESYN12680_BDD12681\); + +-- Location: LABCELL_X21_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_RESYN12680_BDD12681\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_RESYN12680_BDD12681\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111110011111111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~25_RESYN12680_BDD12681\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_combout\); + +-- Location: LABCELL_X26_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~28_combout\); + +-- Location: LABCELL_X20_Y27_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_RESYN8595\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_RESYN8595_BDD8596\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000111111111111000011101110111000000100010001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_RESYN8595_BDD8596\); + +-- Location: LABCELL_X20_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_RESYN8595_BDD8596\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_RESYN8595_BDD8596\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111010101000000000000000000000110000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~31_RESYN8595_BDD8596\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_combout\); + +-- Location: LABCELL_X26_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~5_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~25_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~13_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~21_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~21_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~25_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~13_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~27_combout\); + +-- Location: MLABCELL_X28_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~27_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~28_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~27_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~28_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000000000110000000000000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~28_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~31_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~27_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~32_combout\); + +-- Location: MLABCELL_X28_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~32_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~32_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~32_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~32_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001111111111111000011111111111100011111000111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~25_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~25_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~26_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~34_combout\); + +-- Location: FF_X28_Y26_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~34_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y26_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]_NEW3280\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]_OTERM3281\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(9))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add3~57_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]_OTERM3281\); + +-- Location: FF_X26_Y26_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]_OTERM3281\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector207~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~57_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010110100000001001011010000001111101111110000111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~1_combout\); + +-- Location: LABCELL_X16_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector207~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector207~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector207~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010000000101010001011110101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector207~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~0_combout\); + +-- Location: FF_X16_Y15_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9)); + +-- Location: LABCELL_X16_Y11_N51 +\myVirtualToplevel|TIMER0_CS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|TIMER0_CS~2_combout\ = ( \myVirtualToplevel|IO_SELECT~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & \myVirtualToplevel|TIMER0_CS~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010100000000000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9), + datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + combout => \myVirtualToplevel|TIMER0_CS~2_combout\); + +-- Location: FF_X16_Y11_N29 +\myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1264\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|TIMER0_CS~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\); + +-- Location: MLABCELL_X13_Y9_N3 +\myVirtualToplevel|UART1|TX_OVERRUN~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART1|TX_OVERRUN~1_combout\ = ( \myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & ( ((\myVirtualToplevel|UART1|TX_OVERRUN~0_combout\ & ((\myVirtualToplevel|UART1|Equal6~4_combout\) # (\myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\)))) # +-- (\myVirtualToplevel|UART1|TX_OVERRUN~q\) ) ) # ( !\myVirtualToplevel|UART1|TX_DATA_LOADED~q\ & ( ((!\myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\ & (\myVirtualToplevel|UART1|TX_OVERRUN~0_combout\ & \myVirtualToplevel|UART1|Equal6~4_combout\))) # +-- (\myVirtualToplevel|UART1|TX_OVERRUN~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011111111000000101111111100010011111111110001001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE_FIFO~q\, + datab => \myVirtualToplevel|UART1|ALT_INV_TX_OVERRUN~0_combout\, + datac => \myVirtualToplevel|UART1|ALT_INV_Equal6~4_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_TX_OVERRUN~q\, + dataf => \myVirtualToplevel|UART1|ALT_INV_TX_DATA_LOADED~q\, + combout => \myVirtualToplevel|UART1|TX_OVERRUN~1_combout\); + +-- Location: FF_X13_Y9_N4 +\myVirtualToplevel|UART1|TX_OVERRUN\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART1|TX_OVERRUN~1_combout\, + clrn => \myVirtualToplevel|UART1|TX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART1|TX_OVERRUN~q\); + +-- Location: MLABCELL_X9_Y8_N9 +\myVirtualToplevel|UART0|TX_OVERRUN~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_OVERRUN~2_combout\ = ( \myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ( ((\myVirtualToplevel|UART0|TX_OVERRUN~1_combout\ & ((\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\) # (\myVirtualToplevel|UART0|Equal6~2_combout\)))) # +-- (\myVirtualToplevel|UART0|TX_OVERRUN~q\) ) ) # ( !\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ( ((\myVirtualToplevel|UART0|TX_OVERRUN~1_combout\ & (\myVirtualToplevel|UART0|Equal6~2_combout\ & !\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\))) # +-- (\myVirtualToplevel|UART0|TX_OVERRUN~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011111111000100001111111100010101111111110001010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~1_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_Equal6~2_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\, + combout => \myVirtualToplevel|UART0|TX_OVERRUN~2_combout\); + +-- Location: FF_X9_Y8_N10 +\myVirtualToplevel|UART0|TX_OVERRUN\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_OVERRUN~2_combout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_OVERRUN~q\); + +-- Location: LABCELL_X16_Y9_N9 +\myVirtualToplevel|IO_DATA_READ~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~12_combout\ = ( \myVirtualToplevel|UART1|Add10~13_sumout\ & ( \myVirtualToplevel|UART0|TX_OVERRUN~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|UART1_CS~combout\) # +-- (\myVirtualToplevel|UART1|TX_OVERRUN~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( !\myVirtualToplevel|UART1|Add10~13_sumout\ & ( \myVirtualToplevel|UART0|TX_OVERRUN~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & +-- (((!\myVirtualToplevel|UART1_CS~combout\) # (\myVirtualToplevel|UART1|TX_OVERRUN~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) ) # ( \myVirtualToplevel|UART1|Add10~13_sumout\ & ( !\myVirtualToplevel|UART0|TX_OVERRUN~q\ & ( +-- ((\myVirtualToplevel|UART1_CS~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|UART1|TX_OVERRUN~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( !\myVirtualToplevel|UART1|Add10~13_sumout\ & ( +-- !\myVirtualToplevel|UART0|TX_OVERRUN~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|UART1_CS~combout\ & \myVirtualToplevel|UART1|TX_OVERRUN~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000111010101010101011100001101000011110101110101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ALT_INV_UART1_CS~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datad => \myVirtualToplevel|UART1|ALT_INV_TX_OVERRUN~q\, + datae => \myVirtualToplevel|UART1|ALT_INV_Add10~13_sumout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~q\, + combout => \myVirtualToplevel|IO_DATA_READ~12_combout\); + +-- Location: FF_X16_Y9_N11 +\myVirtualToplevel|IO_DATA_READ[20]_NEW_REG1386\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~12_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[20]_OTERM1387\); + +-- Location: FF_X13_Y11_N31 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~13_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(20)); + +-- Location: FF_X17_Y10_N1 +\myVirtualToplevel|MILLISEC_UP_COUNTER[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~13_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(20)); + +-- Location: LABCELL_X16_Y11_N24 +\myVirtualToplevel|IO_DATA_READ~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~13_combout\ = ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(20)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) # ( +-- !\myVirtualToplevel|MILLISEC_UP_COUNTER\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(20))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000001000010011000100110000001000000010000100110001001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(20), + datae => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(20), + combout => \myVirtualToplevel|IO_DATA_READ~13_combout\); + +-- Location: FF_X16_Y11_N26 +\myVirtualToplevel|IO_DATA_READ[20]_NEW_REG1388\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ~13_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ[20]_OTERM1389\); + +-- Location: LABCELL_X16_Y11_N57 +\myVirtualToplevel|IO_DATA_READ~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ~14_combout\ = ( \myVirtualToplevel|IO_DATA_READ[20]_OTERM1389\ & ( (!\myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\ & (((\myVirtualToplevel|IO_DATA_READ[20]_OTERM1387\)))) # (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\ & +-- ((!\myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\ & (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1263\)) # (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\ & ((\myVirtualToplevel|IO_DATA_READ[20]_OTERM1387\))))) ) ) # ( +-- !\myVirtualToplevel|IO_DATA_READ[20]_OTERM1389\ & ( (\myVirtualToplevel|IO_DATA_READ[20]_OTERM1387\ & ((!\myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\) # (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001111000010100000111100011011000011110001101100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1265\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1263\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ[20]_OTERM1387\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1261\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ[20]_OTERM1389\, + combout => \myVirtualToplevel|IO_DATA_READ~14_combout\); + +-- Location: LABCELL_X24_Y9_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector11~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector11~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(4) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(4), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector11~0_combout\); + +-- Location: FF_X24_Y9_N46 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector11~0_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4), + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(4)); + +-- Location: LABCELL_X21_Y9_N33 +\myVirtualToplevel|IO_DATA_READ_SD[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[20]~feeder_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(4), + combout => \myVirtualToplevel|IO_DATA_READ_SD[20]~feeder_combout\); + +-- Location: FF_X18_Y9_N4 +\myVirtualToplevel|SD_ADDR[0][20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\, + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][20]~q\); + +-- Location: FF_X21_Y9_N34 +\myVirtualToplevel|IO_DATA_READ_SD[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[20]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][20]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(20)); + +-- Location: FF_X21_Y13_N26 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux87~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(20)); + +-- Location: LABCELL_X21_Y13_N24 +\myVirtualToplevel|MEM_DATA_READ[20]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[20]~14_combout\ = ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(20) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((!\myVirtualToplevel|INTR0_CS~combout\))) # +-- (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ~14_combout\)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(20) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((!\myVirtualToplevel|INTR0_CS~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ~14_combout\)) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(20) & ( +-- !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) # (\myVirtualToplevel|IO_DATA_READ_SD\(20)) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(20) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ +-- & ( (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & \myVirtualToplevel|IO_DATA_READ_SD\(20)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011110011111100111111011101000100011101110100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ~14_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\, + datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(20), + datad => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(20), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[20]~14_combout\); + +-- Location: FF_X21_Y13_N17 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]_NEW_REG70\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]~7_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]_OTERM71\); + +-- Location: LABCELL_X21_Y13_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]~7_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM61\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]_OTERM71\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM61\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]_OTERM71\ ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM61\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]_OTERM71\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM61\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]_OTERM71\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100000011000000110011001100110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[20]_OTERM71\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]_OTERM61\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]~7_combout\); + +-- Location: MLABCELL_X18_Y11_N45 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[4]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[4]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]~17_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\, + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[4]~3_combout\); + +-- Location: M10K_X30_Y11_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002222220000022020000E10018212244283100642308281290A10800015136098C6318C2A04996A44849119880200021020001300408040C44020012001095E1E1E1A208411C980220480826086A98A64B240010111D183260C1A400400000000D023E5EB4DAEA56F198CE1FC0376A7558F5A3E4D896EAF3C", + mem_init2 => "AC9C54F4774EB1F2F6CCE5F1F83DFE3DDF5F57966757C789F1D1D93AC738AE87FA57A73F38BCB74DE7E4DCB9B1EAC0BEF388A359D3A9A6B7D5EEBFA38E92879D5FC54F6FF703EABFFB41F55FFD4A305F3E6FEBA6819E9EDFD8BBDFC72E92EFEAF2F5940582A7CF163867BB011D5AF0EBE66FC9B3C6EF7E5D5DB626EA7D277F07BFF6AF9A91C3501CAB5AF8C75DF0F11DF194C56935BC653ADCE65833FEFFF1616CB37E4BD59FAE7D061F3E776CBCCE41BAE0757FC38884DB972E955E57FEDE85D5177E567D1F39B5CED57B3CC40DED96C51DD932FFF7F9C30DA48F30F620864A564E03954FA9E62A4D6BCE3DBDFF79A581734F978DE31DEF7C6BD6DA86A9E29E", + mem_init1 => "5334FE71BED31E7DCADFBBEFCE962FADFFCBBF9BEEC06EB3693D8BF8DBFD597C1C6C7FB39BE44AA6EAABBA3A4DFBFF2EDCF33CD1B2BAB9BF36EF7EDFF87AC7FBB5B4CBFC4CDC1E228A2E92DF1C8ADD334577B6064AEC2C5E7E386BF9979CC33CBA6AA16C09AF49A5A66D48DDB11D32C2FA95B41C03318BAA51C44C284EC7C9C4F7B7DBFCB3E5CBB336BD75B59F65FEDFD3D434F1D9FBFF45A9CF765B2653397971BE331BECAD72D72CDBB90CEDE5B9E523C1CC9F1FDA8DA6CBE5EA67377F62D39D4B9D36EFAE67EEF64C6483DFEE51D2E51B3965DA1293B528E19F9FFD3DCFA8AD58D0F25FF77622B6F2BF8FC7B6F86E66DDD2F7E1F50F637B6FEF766B389465", + mem_init0 => "7A5A9662C0EF563206BA4AD073AB190ACC24DA4C336BD012EB3D786E7B50B669D92FA345B52D15F61FEBB92D999A547FDFBFAAFF76EEBEFFEF9DFE2C225574FEF952C17AFAF2775334708B0232B999CC9ECE92249E23AF2DE5BBF7EFDFB4FE35E9B3AA535A354E6B46A94D580078301C1FEA24ED8D451FA575AB29C74551832FBECDADDFB88CE45C20012BFFF49E86BDD971A7F66FF9FBE6F7522E8D0060A22C80950050B082A8280002B455606501C00051414199EEF0FF00B6016EAEEEAEEEAAAAAAAAEEAEEAEAC025004B00B60128FFFFFFFFFFFC924920000000000000FEFB000200000001186840400D1906010010000107010200000159012003110000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 4, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 4, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\); + +-- Location: M10K_X22_Y11_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 4, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 4, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X21_Y13_N54 +\myVirtualToplevel|MEM_DATA_READ[20]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[20]~15_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12~portbdataout\ & ( +-- \myVirtualToplevel|LessThan0~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12~portbdataout\ & ( +-- (\myVirtualToplevel|LessThan0~1_combout\ & \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0)) ) ) ) # ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4~portbdataout\ & ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12~portbdataout\ & ( (\myVirtualToplevel|LessThan0~1_combout\ & !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000011000000110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\, + dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[20]~15_combout\); + +-- Location: LABCELL_X20_Y13_N54 +\myVirtualToplevel|MEM_DATA_READ[20]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[20]~15_combout\ ) # ( !\myVirtualToplevel|MEM_DATA_READ[20]~15_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & +-- (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]~7_combout\ & \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]~7_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[20]~14_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100011111000100010001111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~14_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[20]~7_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~15_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\); + +-- Location: FF_X19_Y14_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[20]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~13_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[20]~DUPLICATE_q\); + +-- Location: FF_X19_Y14_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~13_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(20)); + +-- Location: LABCELL_X16_Y22_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(20)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(20) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(20) & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\); + +-- Location: LABCELL_X21_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~46\); + +-- Location: LABCELL_X21_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~42\); + +-- Location: LABCELL_X21_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~66\); + +-- Location: LABCELL_X21_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~62\); + +-- Location: LABCELL_X21_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~58\); + +-- Location: LABCELL_X21_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~86\); + +-- Location: LABCELL_X21_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~82\); + +-- Location: LABCELL_X21_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~78\); + +-- Location: LABCELL_X21_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~54\); + +-- Location: LABCELL_X24_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~106\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~106_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add32~53_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~53_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000111111001111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~53_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~106_combout\); + +-- Location: LABCELL_X29_Y27_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~50\); + +-- Location: LABCELL_X29_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~46\); + +-- Location: LABCELL_X29_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~70\); + +-- Location: LABCELL_X29_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~66\); + +-- Location: LABCELL_X29_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~62\); + +-- Location: LABCELL_X29_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~89_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~90\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~89_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~90\); + +-- Location: LABCELL_X29_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~90\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~86\); + +-- Location: LABCELL_X29_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~82\); + +-- Location: LABCELL_X29_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~58\); + +-- Location: LABCELL_X24_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~46\); + +-- Location: LABCELL_X24_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~42\); + +-- Location: LABCELL_X24_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~66\); + +-- Location: LABCELL_X24_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~62\); + +-- Location: LABCELL_X24_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~58\); + +-- Location: LABCELL_X24_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~86\); + +-- Location: LABCELL_X24_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~82\); + +-- Location: LABCELL_X24_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~78\); + +-- Location: LABCELL_X24_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~54\); + +-- Location: LABCELL_X29_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~54\); + +-- Location: LABCELL_X29_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~50\); + +-- Location: LABCELL_X29_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~74\); + +-- Location: LABCELL_X29_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~70\); + +-- Location: LABCELL_X29_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~66\); + +-- Location: LABCELL_X29_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~93_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~94\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~93_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~94\); + +-- Location: LABCELL_X29_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~89_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~94\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~90\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~94\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~94\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~89_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~90\); + +-- Location: LABCELL_X29_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~90\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~86\); + +-- Location: LABCELL_X29_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~62\); + +-- Location: LABCELL_X26_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~46\); + +-- Location: LABCELL_X26_Y27_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~42\); + +-- Location: LABCELL_X26_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~66\); + +-- Location: LABCELL_X26_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~62\); + +-- Location: LABCELL_X26_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~58\); + +-- Location: LABCELL_X26_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~86\); + +-- Location: LABCELL_X26_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~82\); + +-- Location: LABCELL_X26_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~78\); + +-- Location: LABCELL_X26_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~54\); + +-- Location: LABCELL_X24_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~103\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~103_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~53_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~61_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~53_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~57_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~57_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~53_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~61_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~53_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~103_combout\); + +-- Location: LABCELL_X25_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~107\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~107_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~106_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~103_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~106_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~103_combout\ +-- & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~105_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~104_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~106_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~103_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~106_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~103_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~105_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~104_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111111111111111111111111100111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~104_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~105_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~106_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~103_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~107_combout\); + +-- Location: FF_X25_Y22_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~107_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~82\); + +-- Location: FF_X25_Y23_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~132_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~81_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~78\); + +-- Location: FF_X25_Y23_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~127_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)); + +-- Location: LABCELL_X26_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~2\); + +-- Location: LABCELL_X26_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\); + +-- Location: LABCELL_X24_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010100000101000000000000000000000101000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\); + +-- Location: FF_X14_Y38_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\); + +-- Location: LABCELL_X16_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111101011111111111110101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\); + +-- Location: LABCELL_X14_Y38_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)))))) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000010111010000000001011000000000000111110100000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\); + +-- Location: LABCELL_X14_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_RESYN12652\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_RESYN12652_BDD12653\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000011110000111111111111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_RESYN12652_BDD12653\); + +-- Location: LABCELL_X14_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_RESYN12652_BDD12653\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011010101000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_RESYN12652_BDD12653\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\); + +-- Location: LABCELL_X12_Y38_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & ( +-- (!\myVirtualToplevel|RESET_n~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)))) # (\myVirtualToplevel|RESET_n~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100000101000000110011000000000111001101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\); + +-- Location: LABCELL_X12_Y38_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ & ( +-- (\myVirtualToplevel|RESET_n~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\); + +-- Location: LABCELL_X14_Y38_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110000111111111111111100110000001100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\); + +-- Location: LABCELL_X14_Y38_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\) # (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000010111110000000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\); + +-- Location: LABCELL_X14_Y38_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100000001000011111111101100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_combout\); + +-- Location: FF_X14_Y38_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector899~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector899~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001001111000000000000111101010101010011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector899~0_combout\); + +-- Location: LABCELL_X14_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector899~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector899~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000000010000001100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector899~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\); + +-- Location: LABCELL_X14_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111101001111010100000000000000001111010011110100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~1_combout\); + +-- Location: FF_X14_Y36_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\); + +-- Location: FF_X16_Y36_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\); + +-- Location: LABCELL_X16_Y36_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0_combout\); + +-- Location: LABCELL_X16_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000111110001000100011111000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~4_combout\); + +-- Location: LABCELL_X16_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100110011000000010011001100000011000000110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\); + +-- Location: LABCELL_X16_Y36_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547_BDD8548\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000101000001010000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547_BDD8548\); + +-- Location: LABCELL_X16_Y36_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545_BDD8546\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545_BDD8546\); + +-- Location: LABCELL_X16_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545_BDD8546\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111101111111111111110111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545_BDD8546\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\); + +-- Location: LABCELL_X16_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547_BDD8548\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011111111110010001100110011001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547_BDD8548\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_combout\); + +-- Location: FF_X16_Y36_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\); + +-- Location: FF_X14_Y37_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\); + +-- Location: LABCELL_X14_Y37_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111011101111111111101110111111111110111010000111100001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0_combout\); + +-- Location: LABCELL_X14_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557_BDD8558\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557_BDD8558\); + +-- Location: LABCELL_X14_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\); + +-- Location: LABCELL_X14_Y37_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001000100010001000100010000000000010001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\); + +-- Location: LABCELL_X14_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_BDD8556\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001110000000001100111000000000110011000000000011001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_BDD8556\); + +-- Location: LABCELL_X14_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_BDD8556\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557_BDD8558\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_BDD8556\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557_BDD8558\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000101010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557_BDD8558\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_BDD8556\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\); + +-- Location: LABCELL_X14_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000101110111011101000000000000000001011101110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~3_combout\); + +-- Location: FF_X14_Y37_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux5~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~0_combout\); + +-- Location: LABCELL_X12_Y38_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector503~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector503~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001000000010000000100000001000000010000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector503~0_combout\); + +-- Location: MLABCELL_X13_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector503~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110101100101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector503~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0_combout\); + +-- Location: MLABCELL_X13_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000001010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector502~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1_combout\); + +-- Location: LABCELL_X12_Y38_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000101000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\); + +-- Location: MLABCELL_X13_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011111100110010101010101010101110111111101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~3_combout\); + +-- Location: FF_X13_Y36_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\); + +-- Location: LABCELL_X17_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector701~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001110010111010101111100000000000010100101010101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~0_combout\); + +-- Location: LABCELL_X17_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector701~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector701~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector701~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000000000010000010100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector701~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~1_combout\); + +-- Location: LABCELL_X17_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector701~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector701~1_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector701~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000111111111111111100010000000100000101010100010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector701~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~0_combout\); + +-- Location: FF_X17_Y34_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\); + +-- Location: MLABCELL_X13_Y38_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111100000000001110110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\); + +-- Location: FF_X13_Y38_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\); + +-- Location: MLABCELL_X13_Y38_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\); + +-- Location: MLABCELL_X13_Y38_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector635~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector635~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001110101001100000111010100000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector635~3_combout\); + +-- Location: MLABCELL_X13_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector635~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector635~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector635~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector635~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010101000000000101010100000101000101010000010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector635~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\); + +-- Location: MLABCELL_X13_Y38_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561_BDD8562\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000000000101010100000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561_BDD8562\); + +-- Location: MLABCELL_X13_Y38_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559_BDD8560\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559_BDD8560\); + +-- Location: MLABCELL_X13_Y38_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559_BDD8560\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector635~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111101111111011111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector635~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559_BDD8560\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\); + +-- Location: MLABCELL_X13_Y38_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561_BDD8562\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\ ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101111101011111000101010101010101011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561_BDD8562\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_combout\); + +-- Location: FF_X13_Y38_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\); + +-- Location: LABCELL_X10_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~56_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0_combout\); + +-- Location: LABCELL_X14_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12452\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12452_BDD12453\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110011111111101010001010101011001100110011001000100010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~56_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12452_BDD12453\); + +-- Location: LABCELL_X14_Y36_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12454\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12454_BDD12455\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100001111000001010000111101010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12454_BDD12455\); + +-- Location: LABCELL_X14_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12454_BDD12455\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12452_BDD12453\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12454_BDD12455\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12452_BDD12453\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12454_BDD12455\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12452_BDD12453\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000001100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_RESYN12452_BDD12453\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_RESYN12454_BDD12455\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_combout\); + +-- Location: LABCELL_X14_Y36_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101111111110100010100000000000000001111111101000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~1_combout\); + +-- Location: FF_X14_Y36_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\); + +-- Location: LABCELL_X14_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux5~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~1_combout\); + +-- Location: MLABCELL_X13_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux5~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux5~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux5~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux5~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~2_combout\); + +-- Location: LABCELL_X17_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( (!\myVirtualToplevel|MEM_BUSY~1_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~56_combout\); + +-- Location: LABCELL_X17_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~58_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~56_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~56_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~56_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~57_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~56_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~57_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001000100010001100110011001111111010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~57_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~56_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~58_combout\); + +-- Location: FF_X17_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~58_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\); + +-- Location: LABCELL_X16_Y16_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\); + +-- Location: LABCELL_X20_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector343~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector343~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~45_sumout\ & ( ((\myVirtualToplevel|MEM_DATA_READ[15]~135_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~45_sumout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add7~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & ((\myVirtualToplevel|MEM_DATA_READ[15]~135_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add7~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & +-- \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000001000010011000100110000111011001110110111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~135_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~50_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector343~0_combout\); + +-- Location: FF_X20_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector343~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(15)); + +-- Location: LABCELL_X20_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(15) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(15) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(15) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111111111111111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\); + +-- Location: MLABCELL_X23_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~116\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~116_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~61_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111110000111100001111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~116_combout\); + +-- Location: LABCELL_X26_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~114\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~114_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000110000001100000000000000001111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~69_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~114_combout\); + +-- Location: LABCELL_X26_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~115\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~115_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000000011000000110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~69_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~115_combout\); + +-- Location: LABCELL_X25_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~113\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~113_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~61_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~69_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~61_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~65_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~69_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~61_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~65_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~61_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~113_combout\); + +-- Location: LABCELL_X26_Y21_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~117\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~117_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~113_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|pc~115_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~114_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~116_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~113_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~115_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~114_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~116_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011111111111011101111111111101111111111111110111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~116_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~114_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~115_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~113_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~117_combout\); + +-- Location: FF_X26_Y21_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~117_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)); + +-- Location: LABCELL_X24_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~94\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~94\); + +-- Location: LABCELL_X25_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~145\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~145_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000000011000000110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~93_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~145_combout\); + +-- Location: LABCELL_X21_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~144\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~144_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000000000000000000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~93_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~144_combout\); + +-- Location: LABCELL_X25_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~143\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~143_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~85_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~93_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~85_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~89_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~85_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~89_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~85_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~93_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~143_combout\); + +-- Location: LABCELL_X24_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~146\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~146_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~85_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~85_sumout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~85_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~85_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010111111111111111110000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~85_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~146_combout\); + +-- Location: LABCELL_X25_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~147\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~147_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~146_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~146_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~146_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~143_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~144_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~145_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~146_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~144_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~145_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011101110111011111110111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~145_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~144_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~143_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~146_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~147_combout\); + +-- Location: FF_X25_Y24_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~147_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17)); + +-- Location: LABCELL_X24_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~94\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~90\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~94\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~94\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~90\); + +-- Location: LABCELL_X25_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~139\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~139_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\))) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011000000000000001100001100000011110000110000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~89_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~139_combout\); + +-- Location: MLABCELL_X23_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~140\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~140_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001010000010100001010000010100000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~89_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~140_combout\); + +-- Location: LABCELL_X24_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~141\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~141_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010111111111000001011111111100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~141_combout\); + +-- Location: LABCELL_X24_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~138\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~138_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~81_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~89_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~81_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~85_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~81_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~85_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~89_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~81_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~138_combout\); + +-- Location: LABCELL_X25_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~142\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~142_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~138_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|pc~141_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~140_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~139_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~138_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~141_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~140_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~139_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111111111111001111111111111101111111111111110111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~139_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~140_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~141_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~138_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~142_combout\); + +-- Location: FF_X25_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~142_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(18)); + +-- Location: LABCELL_X25_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~135\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~135_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(19) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110000000000001111110000000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~85_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~135_combout\); + +-- Location: LABCELL_X24_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~134\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~134_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19) & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000101010100000000101010100000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~85_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~134_combout\); + +-- Location: LABCELL_X24_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~136\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~136_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add32~77_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~77_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000111111001111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~77_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~136_combout\); + +-- Location: LABCELL_X24_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~133\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~133_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~77_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~85_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~77_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~81_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~77_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~81_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~85_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~77_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~133_combout\); + +-- Location: LABCELL_X25_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~137\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~137_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~136_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~133_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~136_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~133_combout\ +-- & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~134_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~135_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~136_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~133_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~136_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~133_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~134_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~135_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011101110111111111111111111101110111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~135_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~134_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~136_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~133_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~137_combout\); + +-- Location: FF_X25_Y22_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~137_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~30\); + +-- Location: LABCELL_X26_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]_NEW3301\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]_OTERM3302\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~29_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(19) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~29_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]_OTERM3302\); + +-- Location: FF_X26_Y23_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]_OTERM3302\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector197~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~29_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~29_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~29_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010010100100101001001110111011101110101011101010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~1_combout\); + +-- Location: LABCELL_X17_Y13_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector197~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector197~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector197~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100001101000011001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector197~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~0_combout\); + +-- Location: FF_X17_Y13_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(19)); + +-- Location: FF_X16_Y13_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[22]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[22]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y14_N24 +\myVirtualToplevel|LessThan0~0_RESYN12604\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|LessThan0~0_RESYN12604_BDD12605\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[22]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[22]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(21), + combout => \myVirtualToplevel|LessThan0~0_RESYN12604_BDD12605\); + +-- Location: LABCELL_X17_Y14_N48 +\myVirtualToplevel|LessThan0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|LessThan0~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(20) & ( \myVirtualToplevel|LessThan0~0_RESYN12604_BDD12605\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(19) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(17) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(18)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(20), + dataf => \myVirtualToplevel|ALT_INV_LessThan0~0_RESYN12604_BDD12605\, + combout => \myVirtualToplevel|LessThan0~0_combout\); + +-- Location: MLABCELL_X18_Y13_N42 +\myVirtualToplevel|MEM_DATA_READ[10]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ = ( \myVirtualToplevel|LessThan0~0_combout\ & ( \myVirtualToplevel|SOCCFG_CS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|LessThan0~0_combout\ & ( +-- \myVirtualToplevel|SOCCFG_CS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\) # (\myVirtualToplevel|SD_CS~0_combout\) ) ) ) # ( \myVirtualToplevel|LessThan0~0_combout\ & ( !\myVirtualToplevel|SOCCFG_CS~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|LessThan0~0_combout\ & ( !\myVirtualToplevel|SOCCFG_CS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000000011110000111111110000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_SD_CS~0_combout\, + datae => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~0_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[10]~1_combout\); + +-- Location: MLABCELL_X9_Y14_N21 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[4]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[4]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000011110000111101011111010111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[4]~0_combout\); + +-- Location: M10K_X11_Y15_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 4, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 4, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(1), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\); + +-- Location: MLABCELL_X13_Y10_N30 +\myVirtualToplevel|SD_ADDR[0][12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_ADDR[0][12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(12), + combout => \myVirtualToplevel|SD_ADDR[0][12]~feeder_combout\); + +-- Location: FF_X13_Y10_N32 +\myVirtualToplevel|SD_ADDR[0][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][12]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][12]~q\); + +-- Location: MLABCELL_X13_Y10_N45 +\myVirtualToplevel|Mux71~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|Mux71~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|SD_ADDR[0][12]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + combout => \myVirtualToplevel|Mux71~0_combout\); + +-- Location: FF_X13_Y10_N46 +\myVirtualToplevel|IO_DATA_READ_SD[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Mux71~0_combout\, + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(12)); + +-- Location: FF_X13_Y11_N55 +\myVirtualToplevel|INT_ENABLE[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|INT_ENABLE\(12)); + +-- Location: FF_X18_Y11_N14 +\myVirtualToplevel|IO_DATA_READ_INTRCTL[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|INT_ENABLE\(12), + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + sload => VCC, + ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(12)); + +-- Location: FF_X13_Y11_N7 +\myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add13~33_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\, + ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(12)); + +-- Location: FF_X17_Y11_N37 +\myVirtualToplevel|MILLISEC_UP_COUNTER[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|Add17~33_sumout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\, + ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(12)); + +-- Location: LABCELL_X16_Y11_N0 +\myVirtualToplevel|IO_DATA_READ[12]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[12]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(12) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|MILLISEC_UP_COUNTER\(12)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(12), + datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + datad => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + combout => \myVirtualToplevel|IO_DATA_READ[12]~26_combout\); + +-- Location: LABCELL_X16_Y11_N3 +\myVirtualToplevel|IO_DATA_READ[12]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ[12]~27_combout\ = ( \myVirtualToplevel|TIMER0_CS~1_combout\ & ( (\myVirtualToplevel|Equal3~0_combout\ & \myVirtualToplevel|IO_DATA_READ[12]~26_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_Equal3~0_combout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ[12]~26_combout\, + dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\, + combout => \myVirtualToplevel|IO_DATA_READ[12]~27_combout\); + +-- Location: FF_X16_Y11_N4 +\myVirtualToplevel|IO_DATA_READ[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ[12]~27_combout\, + ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ\(12)); + +-- Location: FF_X18_Y11_N26 +\myVirtualToplevel|IO_DATA_READ_SOCCFG[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|Mux91~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(12)); + +-- Location: MLABCELL_X18_Y11_N24 +\myVirtualToplevel|MEM_DATA_READ[12]~74_RESYN8723\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[12]~74_RESYN8723_BDD8724\ = ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(12) & ( \myVirtualToplevel|SOCCFG_CS~combout\ ) ) # ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(12) & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( +-- \myVirtualToplevel|IO_DATA_READ\(12) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SOCCFG\(12) & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(12) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(12), + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(12), + dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[12]~74_RESYN8723_BDD8724\); + +-- Location: MLABCELL_X18_Y11_N12 +\myVirtualToplevel|MEM_DATA_READ[12]~74\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[12]~74_combout\ = ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(12) & ( \myVirtualToplevel|MEM_DATA_READ[12]~74_RESYN8723_BDD8724\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(12) & ( \myVirtualToplevel|MEM_DATA_READ[12]~74_RESYN8723_BDD8724\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((!\myVirtualToplevel|INTR0_CS~combout\) # ((!\myVirtualToplevel|IO_SELECT~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(12) & ( !\myVirtualToplevel|MEM_DATA_READ[12]~74_RESYN8723_BDD8724\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\)) # (\myVirtualToplevel|INTR0_CS~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(12) & ( !\myVirtualToplevel|MEM_DATA_READ[12]~74_RESYN8723_BDD8724\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((!\myVirtualToplevel|IO_SELECT~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000110011111101010011001111111010001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\, + datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(12), + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~74_RESYN8723_BDD8724\, + combout => \myVirtualToplevel|MEM_DATA_READ[12]~74_combout\); + +-- Location: FF_X19_Y13_N22 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]_NEW_REG100\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]~12_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]_OTERM101\); + +-- Location: LABCELL_X19_Y13_N6 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]~12_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]_OTERM101\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\) # +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM93\)) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]_OTERM101\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM93\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001000000010000000111111011111110111111101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]_OTERM93\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[12]_OTERM101\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]~12_combout\); + +-- Location: M10K_X3_Y15_N0 +\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000809151800B3484C0102000B0C9836B081500208A01002B5AD6A53B1683104084889106A2220E281209848860028812B478114400015E1E1E1E000456C000108010124094B152539040299901018306CC98200211FFFFFFB7FE7063035AF7DAE87FFFFFF6BDB39E257F9F1F86E5E583", + mem_init2 => "69C76E7564E227E47DFBC8E7E1745FDE0F7E43AFDF439E7F0395938A9E8EE9D6BD716F9ECDF9CBD2DD2E0C5E879E52F9747A329A1031217E6F6181BCDCF3FFCE4C2F747703EABFFB41F55FFDA7D7DF2CE77DCBAB4AEEC38AA97E93F9DF7A511CEB5AB6FFFFE993952951D7BBFFD4E7BF49F7ABE1DEDF77FFD896AFFE6EE9F64DFFBAFBD67A745B303F6E7B59B9D411B9D410CB52816B0D08363752D045637A65CE8CDDB7EAD89E0972A814E72D87EE9BADEB7138B3D3AF72CF6F9B3A90717D4ACF1ED26C9E02632662E7C8E14A17C00B9BEEDBC6F57BF2B829C855543B69A8E59D167938F1AA99079B61D533EBD93AF595599B660F0CAE2270954B27FCD5D5AE", + mem_init1 => "AD8DC86EEDE6AF7C297CDDB8A9EF3A9F96E7BFF39FEAB66533C877447E9192638F8EA337F699A9DBDDEDDFF5DABDEA274AB4E5F52E1A65DF59A7BDAF513F7E6B59673852DB5CAECB1D31F3B276F9E9CE17C134D8F3CC3ED14296CCAE202C29123BC1394AC735BE8B2D366564E7D7E0D5089AFCB66EDBDA383C2A571644DF7F7FF77BDB36E5F8D8F2F23CFE3265C8BD6F79E764EC75C9DC4BFFE9ECDEBADCC2779C2FAAEC5B12D90DB126D66AE57993126A69332FC0DDA35207857928C48FA4FE4BBBFF79F08FDFFD3D7F75173E87C869A6AE7CFF8D472CEB85E658A88B517F1DFDECAD49C8AA3FF6E6B84459FCFAFA6CFC71B9B71ABFC3927BBC6FEEF78DBE53", + mem_init0 => "0BE65CE4EC8ECFA12ECDAB384777D08B2BBAA57AA84666CF1FFB54CDCCD8E67C5C5D5C3E65EE069D1FAB3116EFF7F8D7B76B6FA56A64ABBC5EB7EF33329B469DDE30534F95073DCDC78B4685B6A989ECE8B51B368332F12B356EFDDB376EA3499D486354A6B46A94D68D528021E0C078107EB45051AA1AEE797ACE695D6A591D15464E1FD4E73903100018001FF1262B795D187B326D9ADD49DE2FB5C55500020A205086414A0A8594150AA81810B03282A402AA003572FF800B60115551551555151155555511556C02D804B00B4012FFFFFFFFFFF8924924924924924800FEFA000000000000695D1A1A000805020000000318050300000041000A22000400", + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + init_file => "db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif", + init_file_layout => "port_a", + logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM1_rtl_0|altsyncram_e902:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 13, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 1, + port_a_first_address => 0, + port_a_first_bit_number => 4, + port_a_last_address => 8191, + port_a_logical_ram_depth => 16384, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 13, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 1, + port_b_first_address => 0, + port_b_first_bit_number => 4, + port_b_last_address => 8191, + port_b_logical_ram_depth => 16384, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\(0), + portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X19_Y13_N0 +\myVirtualToplevel|MEM_DATA_READ[12]~147\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\ = ( !\myVirtualToplevel|MEM_DATA_READ[12]~74_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4~portbdataout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((\myVirtualToplevel|IO_DATA_READ_SD\(12))))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]~12_combout\)))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[12]~74_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) # ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12~portbdataout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ +-- & (((\myVirtualToplevel|IO_DATA_READ_SD\(12))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]~12_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001001000110100010101100111000010011010101111001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(12), + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~74_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[12]~12_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\); + +-- Location: LABCELL_X20_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector346~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector346~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~33_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & (\myVirtualToplevel|MEM_DATA_READ[12]~147_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[28]~41_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add7~33_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & (\myVirtualToplevel|MEM_DATA_READ[12]~147_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ & +-- ((\myVirtualToplevel|MEM_DATA_READ[28]~41_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001001100010000000100110001110011011111110111001101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~147_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~1_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~41_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~33_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector346~0_combout\); + +-- Location: FF_X20_Y15_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector346~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(12)); + +-- Location: LABCELL_X20_Y15_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(12)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(12) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(12) & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\); + +-- Location: MLABCELL_X23_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~96\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~96_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~45_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~45_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111111111000000001111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~96_combout\); + +-- Location: LABCELL_X24_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~95\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~95_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000000000000010111110000000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~53_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~95_combout\); + +-- Location: LABCELL_X24_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~94\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~94_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010100000000111101010000000011110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~53_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~94_combout\); + +-- Location: LABCELL_X24_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~93_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~45_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~53_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~45_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~49_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~53_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~45_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~45_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~49_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~93_combout\); + +-- Location: LABCELL_X24_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~97\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~97_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~94_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~93_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~94_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~93_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~95_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~96_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~94_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~93_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~94_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~93_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~95_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~96_combout\) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011101110111111111111111111101110111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~96_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~95_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~94_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~93_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~97_combout\); + +-- Location: FF_X24_Y21_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~97_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12)); + +-- Location: LABCELL_X24_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~50\); + +-- Location: LABCELL_X24_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~90\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~90_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000000000000010111110000000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~49_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~90_combout\); + +-- Location: LABCELL_X24_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~89_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010100000000111101010000000011110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~49_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~89_combout\); + +-- Location: MLABCELL_X23_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~91\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~91_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~41_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111111111111100000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~41_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~91_combout\); + +-- Location: LABCELL_X24_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~88\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~88_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~41_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~49_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~41_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~45_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~49_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~41_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~45_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~41_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~88_combout\); + +-- Location: LABCELL_X24_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~92\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~92_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~91_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~88_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~91_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~88_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~89_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~90_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~91_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~88_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~91_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~88_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~89_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~90_combout\) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011101110111111111111111111101110111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~90_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~89_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~91_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~88_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~92_combout\); + +-- Location: FF_X24_Y21_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~92_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~120\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~120_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110000000000001111110000000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~73_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~120_combout\); + +-- Location: LABCELL_X24_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~119\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~119_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~73_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~119_combout\); + +-- Location: MLABCELL_X23_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~121\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~121_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~65_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~65_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111110000111100001111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~121_combout\); + +-- Location: LABCELL_X25_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~118\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~118_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~65_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~73_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~65_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~69_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~65_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~73_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~69_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~65_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~118_combout\); + +-- Location: LABCELL_X25_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~122\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~122_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~121_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~118_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~121_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~118_combout\ +-- & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~119_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~120_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~121_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~118_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~121_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~118_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~119_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~120_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111111111111111111101111111011111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~120_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~119_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~121_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~118_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~122_combout\); + +-- Location: FF_X25_Y21_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~122_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]_NEW3292\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]_OTERM3293\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~41_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(14) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~41_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]_OTERM3293\); + +-- Location: FF_X26_Y24_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]_OTERM3293\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9151\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9151_BDD9152\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9151_BDD9152\); + +-- Location: LABCELL_X25_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9149\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9149_BDD9150\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011011100111111001111110011111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~49_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~29_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~37_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~45_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9149_BDD9150\); + +-- Location: LABCELL_X25_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9151_BDD9152\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9149_BDD9150\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9151_BDD9152\) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9151_BDD9152\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9151_BDD9152\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000001100000011000000010000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_RESYN9151_BDD9152\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_RESYN9149_BDD9150\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_RESYN8423_BDD8424\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\); + +-- Location: MLABCELL_X9_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8953\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8953_BDD8954\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8953_BDD8954\); + +-- Location: LABCELL_X10_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8955\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8955_BDD8956\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111101010101000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr162~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr162~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8955_BDD8956\); + +-- Location: LABCELL_X10_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8953_BDD8954\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8955_BDD8956\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8953_BDD8954\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8955_BDD8956\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8953_BDD8954\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8955_BDD8956\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8953_BDD8954\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8955_BDD8956\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100000000011100110101000001110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_RESYN8953_BDD8954\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_RESYN8955_BDD8956\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\); + +-- Location: LABCELL_X5_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~25_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~24_combout\); + +-- Location: MLABCELL_X9_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|sp~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~25_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp~24_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~24_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~25_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~25_combout\); + +-- Location: MLABCELL_X9_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[18]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|sp[18]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~25_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(18)) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~25_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~25_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[18]~26_combout\); + +-- Location: FF_X9_Y25_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|sp[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[18]~26_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18)); + +-- Location: LABCELL_X5_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~25_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~25_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\); + +-- Location: LABCELL_X10_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~25_combout\); + +-- Location: MLABCELL_X9_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~25_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~25_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~25_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~25_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000110111001111111100010011000000001101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1065~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[18]~25_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~26_combout\); + +-- Location: FF_X9_Y30_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~26_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(18)); + +-- Location: LABCELL_X6_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100000011000000000000111111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~25_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~22_combout\); + +-- Location: LABCELL_X6_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~22_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~22_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(18) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1065~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[18]~22_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~23_combout\); + +-- Location: FF_X6_Y28_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~23_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(18)); + +-- Location: LABCELL_X6_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110000010101010011000001010101001111110101010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~25_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~28_combout\); + +-- Location: LABCELL_X6_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~28_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(18) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~28_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101101110111010111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1065~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[18]~28_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~29_combout\); + +-- Location: FF_X6_Y28_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~29_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(18)); + +-- Location: LABCELL_X14_Y27_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010100000101000000110011001100110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~24_combout\); + +-- Location: MLABCELL_X13_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~24_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(18) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~24_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010101101110101011111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1065~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[18]~24_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~25_combout\); + +-- Location: FF_X13_Y27_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(18)); + +-- Location: LABCELL_X6_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(18) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(18))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(18) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(18))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011010100000101000000000011111100110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~1_combout\); + +-- Location: LABCELL_X14_Y27_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101000100000011110100010000001111011101110000111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~25_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~24_combout\); + +-- Location: LABCELL_X14_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~24_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~24_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~24_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~24_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000110111001111111100010011000000001101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1065~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[18]~24_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~25_combout\); + +-- Location: FF_X14_Y27_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(18)); + +-- Location: LABCELL_X14_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010000001100110101000000110011010111110011001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~26_combout\); + +-- Location: LABCELL_X14_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~26_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~26_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000010111111111100111000000000000100111111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1065~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[18]~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~27_combout\); + +-- Location: FF_X14_Y27_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~27_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(18)); + +-- Location: LABCELL_X14_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~25_combout\); + +-- Location: LABCELL_X14_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~25_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~25_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(18) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000100111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1065~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[18]~25_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~26_combout\); + +-- Location: FF_X14_Y27_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~26_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(18)); + +-- Location: LABCELL_X14_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010100000101000000000000111111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~25_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~21_combout\); + +-- Location: LABCELL_X14_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~21_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~21_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~21_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~21_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001000111111110011101100000000010011001111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1065~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[18]~21_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~22_combout\); + +-- Location: FF_X14_Y27_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~22_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(18)); + +-- Location: LABCELL_X14_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(18) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(18) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(18) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(18) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~0_combout\); + +-- Location: MLABCELL_X9_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\); + +-- Location: MLABCELL_X9_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000001010000101000000101000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~0_combout\); + +-- Location: MLABCELL_X9_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~4_combout\); + +-- Location: MLABCELL_X9_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000100001000000000000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~5_combout\); + +-- Location: MLABCELL_X4_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\); + +-- Location: MLABCELL_X9_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add27~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~20_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\); + +-- Location: LABCELL_X7_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001001110000010100100111000011011010111110001101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~17_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~20_combout\); + +-- Location: LABCELL_X7_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~20_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~20_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~20_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~20_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001000111101011111110100000010000010101111011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1060~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[23]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~21_combout\); + +-- Location: FF_X7_Y31_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~21_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(23)); + +-- Location: LABCELL_X5_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100000011000001010101010101010011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~24_combout\); + +-- Location: LABCELL_X5_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~24_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~24_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~24_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~24_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000000101011101111111100010101000000001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1060~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[23]~24_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~25_combout\); + +-- Location: FF_X5_Y29_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(23)); + +-- Location: LABCELL_X5_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110000010101010011000001010101001111110101010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~21_combout\); + +-- Location: LABCELL_X5_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~21_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(23) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~21_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101101011101011111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1060~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[23]~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~22_combout\); + +-- Location: FF_X5_Y28_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~22_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(23)); + +-- Location: MLABCELL_X13_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000000001111000000000101111101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~17_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~18_combout\); + +-- Location: MLABCELL_X13_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~18_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~18_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100111111111111010000000000000001111111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1060~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[23]~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~19_combout\); + +-- Location: FF_X13_Y27_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~19_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(23)); + +-- Location: LABCELL_X6_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(23)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(23)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(23) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(23) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000101001100001111010100111111000001010011111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~1_combout\); + +-- Location: LABCELL_X5_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000010100000101000000000111111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~17_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~17_combout\); + +-- Location: LABCELL_X5_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~17_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~17_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~17_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~17_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000000101011101111111100010101000000001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1060~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~18_combout\); + +-- Location: FF_X5_Y29_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~18_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(23)); + +-- Location: LABCELL_X5_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000101110000011000010111000011101001111110001110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~17_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~20_combout\); + +-- Location: LABCELL_X5_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~20_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~20_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~20_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~20_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000101111111010111100010000010100001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1060~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[23]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~21_combout\); + +-- Location: FF_X5_Y29_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~21_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(23)); + +-- Location: LABCELL_X10_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~17_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~21_combout\); + +-- Location: LABCELL_X10_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~21_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~21_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~21_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~21_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000010111111111100111000000000000100111111111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1060~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[23]~21_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~22_combout\); + +-- Location: FF_X10_Y28_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~22_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(23)); + +-- Location: LABCELL_X5_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~17_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~22_combout\); + +-- Location: LABCELL_X5_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~22_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~22_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(23) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1060~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[23]~22_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~23_combout\); + +-- Location: FF_X5_Y28_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~23_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(23)); + +-- Location: MLABCELL_X4_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(23) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(23) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(23) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(23) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~0_combout\); + +-- Location: LABCELL_X6_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~0_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux0~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000000000000000111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\); + +-- Location: LABCELL_X6_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101101010101010101001010101010101011010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~0_combout\); + +-- Location: LABCELL_X7_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001111000011000000000000000000000000000000001100001111000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~1_combout\); + +-- Location: LABCELL_X10_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000001010101000000000101001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~3_combout\); + +-- Location: LABCELL_X10_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_RESYN12534\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_RESYN12534_BDD12535\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_RESYN12534_BDD12535\); + +-- Location: LABCELL_X10_Y19_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_RESYN12534_BDD12535\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000100010000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~13_RESYN12534_BDD12535\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_combout\); + +-- Location: MLABCELL_X9_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8621\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8621_BDD8622\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111111100000111001111110000001100011111000000010000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8621_BDD8622\); + +-- Location: MLABCELL_X9_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8623\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8623_BDD8624\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011101100000010101111110010001100110011000000001011101100100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8623_BDD8624\); + +-- Location: MLABCELL_X9_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8623_BDD8624\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22)) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8623_BDD8624\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8621_BDD8622\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8621_BDD8622\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010101011000000101010101110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_RESYN8621_BDD8622\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_RESYN8623_BDD8624\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_combout\); + +-- Location: MLABCELL_X13_Y17_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110011001111000011001100111100000000110011000000000011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~10_combout\); + +-- Location: MLABCELL_X13_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111101011111000001010000010100001111000011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~7_combout\); + +-- Location: MLABCELL_X13_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001000010010000100100001001000000001001000010010000100100001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~8_combout\); + +-- Location: MLABCELL_X13_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~7_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000101111000000101011111100001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~9_combout\); + +-- Location: MLABCELL_X13_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~10_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000010101000111010101111111000000000100010001010101011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~11_combout\); + +-- Location: LABCELL_X10_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12532\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12532_BDD12533\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110111111111010001000101010111111101111111111111010011110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12532_BDD12533\); + +-- Location: LABCELL_X10_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12530\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12530_BDD12531\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000001000000110011001100010011111100110111001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12530_BDD12531\); + +-- Location: LABCELL_X7_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000000000000000011111111111111110000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~2_combout\); + +-- Location: LABCELL_X10_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12530_BDD12531\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12532_BDD12533\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111110101011101011111010101100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_RESYN12532_BDD12533\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_RESYN12530_BDD12531\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_combout\); + +-- Location: LABCELL_X10_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~11_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~5_combout\))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010011001100010001001100110000000100110011000000000011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\); + +-- Location: LABCELL_X7_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101000000000101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~1_combout\); + +-- Location: LABCELL_X10_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111010011110000111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~2_combout\); + +-- Location: FF_X10_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~2_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\); + +-- Location: LABCELL_X7_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_WREN~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_WREN~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001000000011110000100000001011000010000000101100001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_WREN~0_combout\); + +-- Location: LABCELL_X20_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ $ ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ((((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~48_combout\))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "1111110111110111111111001111111111111101101000101110110011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~54_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~48_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~47_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\); + +-- Location: LABCELL_X19_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~98\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~98_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001110000011111111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~98_combout\); + +-- Location: FF_X19_Y30_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~98_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~q\); + +-- Location: LABCELL_X19_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~97\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~97_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110010001100111111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~97_combout\); + +-- Location: FF_X19_Y30_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~97_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~q\); + +-- Location: LABCELL_X19_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~99\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~99_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011001000111111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~99_combout\); + +-- Location: FF_X19_Y30_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~99_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\); + +-- Location: LABCELL_X19_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~96\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~96_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000111011111111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~96_combout\); + +-- Location: FF_X19_Y30_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~96_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~q\); + +-- Location: MLABCELL_X18_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~q\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000011000011111111011101110111010000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~0_combout\); + +-- Location: LABCELL_X19_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~101\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~101_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~101_combout\); + +-- Location: FF_X19_Y31_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~101_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~q\); + +-- Location: LABCELL_X19_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~103\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~103_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~103_combout\); + +-- Location: FF_X19_Y31_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~103_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\); + +-- Location: LABCELL_X19_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~102\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~102_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~102_combout\); + +-- Location: FF_X19_Y31_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~102_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~q\); + +-- Location: FF_X19_Y31_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~100_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\); + +-- Location: LABCELL_X19_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~100\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~100_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~100_combout\); + +-- Location: FF_X19_Y31_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~100_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~1_combout\); + +-- Location: LABCELL_X19_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~104\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~104_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000111111101111111111111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~104_combout\); + +-- Location: FF_X19_Y30_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~104_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~q\); + +-- Location: LABCELL_X19_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~107\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~107_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011001100101111111111111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~107_combout\); + +-- Location: FF_X19_Y30_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~107_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\); + +-- Location: LABCELL_X19_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~105\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~105_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011001100101111111111111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~105_combout\); + +-- Location: FF_X19_Y30_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~105_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~q\); + +-- Location: LABCELL_X19_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~106\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~106_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011101111111111111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~106_combout\); + +-- Location: FF_X19_Y30_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~106_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~q\); + +-- Location: LABCELL_X19_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~2_combout\); + +-- Location: LABCELL_X19_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~110\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~110_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~110_combout\); + +-- Location: FF_X19_Y32_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~110_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~q\); + +-- Location: LABCELL_X19_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~109\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~109_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~109_combout\); + +-- Location: FF_X19_Y32_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~109_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\); + +-- Location: LABCELL_X19_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~108\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~108_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~108_combout\); + +-- Location: FF_X19_Y32_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~108_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~q\); + +-- Location: FF_X19_Y32_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~111_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\); + +-- Location: LABCELL_X19_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~111\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~111_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~111_combout\); + +-- Location: FF_X19_Y32_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~111_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~3_combout\); + +-- Location: MLABCELL_X18_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~1_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~1_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~1_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001001100011100000111110001000011010011110111001101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\); + +-- Location: MLABCELL_X18_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110110001000100011011000100000000101000000000000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\); + +-- Location: MLABCELL_X28_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001000000000010000100000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\); + +-- Location: LABCELL_X31_Y22_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~31_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~31_combout\); + +-- Location: LABCELL_X31_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~33_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~33_combout\); + +-- Location: LABCELL_X31_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010000000000000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~32_combout\); + +-- Location: LABCELL_X31_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~34_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~33_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~32_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~33_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~34_combout\); + +-- Location: LABCELL_X31_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~0_combout\); + +-- Location: LABCELL_X31_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~0_combout\) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~1_combout\); + +-- Location: LABCELL_X32_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~31_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000010001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~31_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~34_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~35_combout\); + +-- Location: LABCELL_X32_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000010001000000000000000000010001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~35_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~36_combout\); + +-- Location: LABCELL_X32_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111001111110000111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_0~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~51_combout\); + +-- Location: FF_X32_Y19_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~51_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\); + +-- Location: LABCELL_X36_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_0~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~46_combout\); + +-- Location: LABCELL_X36_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~35_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~46_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~46_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~46_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000000000010101000100000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~35_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~46_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~47_combout\); + +-- Location: FF_X36_Y26_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~47_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299~DUPLICATE_q\); + +-- Location: FF_X36_Y24_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_NEW_REG296\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~53_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM297\); + +-- Location: LABCELL_X32_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\); + +-- Location: FF_X36_Y24_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_NEW_REG300\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM301\); + +-- Location: LABCELL_X36_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM297\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM301\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM297\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM301\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM297\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM301\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM299~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM297\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM301\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~53_combout\); + +-- Location: LABCELL_X40_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_2~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~49_combout\); + +-- Location: FF_X40_Y29_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~49_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_2~q\); + +-- Location: LABCELL_X36_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_2~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~39_combout\); + +-- Location: FF_X36_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1190\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1191\); + +-- Location: FF_X36_Y26_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1192\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1193\); + +-- Location: FF_X36_Y26_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_NEW_REG298\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~47_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299\); + +-- Location: FF_X36_Y26_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1194\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1195\); + +-- Location: FF_X36_Y26_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1196\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1197\); + +-- Location: FF_X36_Y26_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1198\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1199\); + +-- Location: LABCELL_X36_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1197\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1199\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1193\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1195\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1197\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1199\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1193\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1195\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1197\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1199\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1193\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1191\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1193\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1195\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1197\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1199\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1193\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1191\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1193\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1195\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001000111110111111100000000000000011001111000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1191\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1193\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM299\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1195\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1197\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1199\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\); + +-- Location: FF_X36_Y24_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~55_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~q\); + +-- Location: LABCELL_X36_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101111111111111111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugAllInfo~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_End~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~0_combout\); + +-- Location: FF_X36_Y24_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\); + +-- Location: LABCELL_X36_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~55_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~DUPLICATE_q\))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~53_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~39_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~41_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~53_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000111100001111000111111111111100001111000011110001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~53_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~41_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~39_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugAllInfo~q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_End~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~55_combout\); + +-- Location: FF_X36_Y24_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~55_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~DUPLICATE_q\); + +-- Location: LABCELL_X32_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~36_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111000000110011001100001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~36_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_End~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~37_combout\); + +-- Location: FF_X32_Y24_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~37_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\); + +-- Location: LABCELL_X31_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000101010100000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\); + +-- Location: FF_X23_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~159_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)); + +-- Location: LABCELL_X24_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_RESYN8615\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_RESYN8615_BDD8616\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101110101011111111111111111101111101011111010111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_RESYN8615_BDD8616\); + +-- Location: LABCELL_X24_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_RESYN8615_BDD8616\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_RESYN8615_BDD8616\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_RESYN8615_BDD8616\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_RESYN8615_BDD8616\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0110111111001101111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~8_RESYN8615_BDD8616\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_combout\); + +-- Location: LABCELL_X24_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_RESYN8605_BDD8606\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_RESYN8605_BDD8606\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_RESYN8605_BDD8606\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_RESYN8605_BDD8606\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010001010100010101010100000000010101010101010101010101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~2_RESYN8605_BDD8606\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_combout\); + +-- Location: LABCELL_X20_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~82_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111100111111011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~82_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\); + +-- Location: LABCELL_X20_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~129\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~129_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~129_combout\); + +-- Location: FF_X20_Y29_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~129_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\); + +-- Location: LABCELL_X20_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~127\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~127_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~127_combout\); + +-- Location: FF_X20_Y29_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~127_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~q\); + +-- Location: MLABCELL_X23_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~128\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~128_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~128_combout\); + +-- Location: FF_X23_Y29_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~128_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\); + +-- Location: LABCELL_X21_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~126\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~126_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~126_combout\); + +-- Location: FF_X21_Y33_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~126_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\); + +-- Location: LABCELL_X20_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\)) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000111010001110111001100111111110001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~0_combout\); + +-- Location: LABCELL_X25_Y38_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~85_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~85_combout\); + +-- Location: LABCELL_X25_Y38_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000001100110011001100110011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~3_combout\); + +-- Location: LABCELL_X25_Y38_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011000110110001000100010001000100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~1_combout\); + +-- Location: LABCELL_X25_Y38_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~2_combout\); + +-- Location: LABCELL_X25_Y38_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~59_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~85_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~3_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~59_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~85_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~59_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~59_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111001111110011111100110000000010100010101000101010001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~85_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~59_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~4_combout\); + +-- Location: LABCELL_X25_Y38_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100000000000001000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~2_combout\); + +-- Location: MLABCELL_X23_Y39_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~10_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) # ((((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "1111111111111111101111111111111111110111111111111011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~64_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~10_combout\); + +-- Location: LABCELL_X24_Y38_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~14_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~14_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~87_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\); + +-- Location: LABCELL_X20_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~132\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~132_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~132_combout\); + +-- Location: FF_X20_Y29_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~132_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\); + +-- Location: LABCELL_X20_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~133\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~133_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~133_combout\); + +-- Location: FF_X20_Y29_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~133_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~q\); + +-- Location: LABCELL_X20_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~131\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~131_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~131_combout\); + +-- Location: FF_X20_Y29_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~131_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~q\); + +-- Location: LABCELL_X20_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~130\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~130_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~130_combout\); + +-- Location: FF_X20_Y29_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~130_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~q\); + +-- Location: LABCELL_X20_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~q\)) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000011110011001111111111010101010000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~1_combout\); + +-- Location: LABCELL_X20_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_RESYN8617\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_RESYN8617_BDD8618\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\)))) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111001111111101111100111111110101011111111101110101111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_RESYN8617_BDD8618\); + +-- Location: LABCELL_X21_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_RESYN8617_BDD8618\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\) # +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_RESYN8617_BDD8618\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101110111111111111111111111101111111011111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~6_RESYN8617_BDD8618\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_combout\); + +-- Location: LABCELL_X21_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~3_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~3_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~3_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111111111111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~90_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\); + +-- Location: MLABCELL_X23_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~136\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~136_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~136_combout\); + +-- Location: FF_X23_Y29_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~136_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~q\); + +-- Location: MLABCELL_X23_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~137\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~137_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~137_combout\); + +-- Location: FF_X23_Y29_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~137_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\); + +-- Location: LABCELL_X26_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~135\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~135_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001110111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~135_combout\); + +-- Location: FF_X26_Y29_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~135_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\); + +-- Location: LABCELL_X29_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~134\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~134_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~134_combout\); + +-- Location: FF_X29_Y29_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~134_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\); + +-- Location: LABCELL_X20_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\)) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000011110011001111111111010101010000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~2_combout\); + +-- Location: MLABCELL_X4_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000100011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~3_combout\); + +-- Location: LABCELL_X2_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110000000000000001010000000000001100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~78_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~77_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~4_combout\); + +-- Location: MLABCELL_X4_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_RESYN12752\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_RESYN12752_BDD12753\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010101010101000001010101001010000000000000101000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_RESYN12752_BDD12753\); + +-- Location: MLABCELL_X4_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_RESYN12752_BDD12753\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_RESYN12752_BDD12753\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000100000000000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~2_RESYN12752_BDD12753\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_combout\); + +-- Location: MLABCELL_X4_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~92_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~92_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\); + +-- Location: LABCELL_X21_Y31_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~141\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~141_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~141_combout\); + +-- Location: FF_X21_Y31_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~141_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\); + +-- Location: LABCELL_X21_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~138\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~138_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~138_combout\); + +-- Location: FF_X21_Y31_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~138_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~q\); + +-- Location: FF_X21_Y31_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~140_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~q\); + +-- Location: LABCELL_X21_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~140\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~140_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~140_combout\); + +-- Location: FF_X21_Y31_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~140_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\); + +-- Location: LABCELL_X21_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~139\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~139_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~139_combout\); + +-- Location: FF_X21_Y31_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~139_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~q\); + +-- Location: LABCELL_X21_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~3_combout\); + +-- Location: LABCELL_X20_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~0_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~1_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100001010100110111000011001010111010011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\); + +-- Location: LABCELL_X20_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_RESYN12676\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_RESYN12676_BDD12677\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000000000000010100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_RESYN12676_BDD12677\); + +-- Location: LABCELL_X20_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_RESYN12676_BDD12677\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_RESYN12676_BDD12677\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_RESYN12676_BDD12677\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010000000000000010101010101010101110101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_RESYN12676_BDD12677\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\); + +-- Location: LABCELL_X20_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~22_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000001000000010000000100000001000111111110000100011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\); + +-- Location: LABCELL_X21_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~74\); + +-- Location: LABCELL_X24_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~131\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~131_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~73_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~73_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010111110000111101011111000011110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~73_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~131_combout\); + +-- Location: LABCELL_X25_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~130\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~130_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~81_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~81_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~130_combout\); + +-- Location: MLABCELL_X23_Y23_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~129\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~129_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(21)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000000110000000000000000000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~129_combout\); + +-- Location: LABCELL_X29_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~82\); + +-- Location: LABCELL_X24_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~74\); + +-- Location: LABCELL_X29_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~78\); + +-- Location: LABCELL_X26_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~74\); + +-- Location: LABCELL_X26_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~128\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~128_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~73_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~73_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~81_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~77_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~81_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~73_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~77_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~73_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~128_combout\); + +-- Location: LABCELL_X25_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~132\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~132_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~128_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|pc~129_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~130_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~131_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~128_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~129_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~130_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~131_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111111111111001111111111111101111111111111110111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~131_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~130_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~129_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~128_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~132_combout\); + +-- Location: FF_X25_Y23_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~132_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~81_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(21)); + +-- Location: MLABCELL_X28_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~14\); + +-- Location: MLABCELL_X28_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add3~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~6\); + +-- Location: LABCELL_X26_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]_NEW3319\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]_OTERM3320\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(21))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~5_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]_OTERM3320\); + +-- Location: FF_X26_Y23_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]_OTERM3320\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]_NEW3316\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]_OTERM3317\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add3~9_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~9_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]_OTERM3317\); + +-- Location: FF_X25_Y19_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]_OTERM3317\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22)); + +-- Location: LABCELL_X25_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000000000101010100000000010101010000000000010101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\); + +-- Location: FF_X1_Y34_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~41_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(1)); + +-- Location: LABCELL_X2_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal6~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pause\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pause\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~2_combout\); + +-- Location: FF_X1_Y34_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~37_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause[2]~DUPLICATE_q\); + +-- Location: FF_X1_Y34_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(7)); + +-- Location: LABCELL_X1_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal6~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pause\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pause\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pause\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|pause\(7))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~0_combout\); + +-- Location: LABCELL_X1_Y34_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(9) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(9) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~54\); + +-- Location: LABCELL_X1_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(10) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(10) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~30\); + +-- Location: FF_X1_Y34_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(10)); + +-- Location: LABCELL_X1_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(11) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(11) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~26\); + +-- Location: FF_X1_Y34_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(11)); + +-- Location: LABCELL_X1_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(12) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(12) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(12), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~22\); + +-- Location: FF_X1_Y34_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(12)); + +-- Location: LABCELL_X1_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(13) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(13) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~18\); + +-- Location: FF_X1_Y34_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(13)); + +-- Location: LABCELL_X1_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal6~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pause\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal6~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pause\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pause\(11) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pause\(12)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000000000010000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~1_combout\); + +-- Location: LABCELL_X2_Y34_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal6~2_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal6~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pause[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pause\(3))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal6~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111011111111111111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\); + +-- Location: LABCELL_X1_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pause[0]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pause\(0) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pause\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan9~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pause[0]~0_combout\); + +-- Location: FF_X1_Y34_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pause[0]~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(0)); + +-- Location: LABCELL_X1_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~62\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~62_cout\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(0), + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~62_cout\); + +-- Location: LABCELL_X1_Y34_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause[1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~62_cout\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause[1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~62_cout\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[1]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~62_cout\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~42\); + +-- Location: FF_X1_Y34_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~41_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause[1]~DUPLICATE_q\); + +-- Location: LABCELL_X1_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(2) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(2) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(2), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~38\); + +-- Location: FF_X1_Y34_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~37_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(2)); + +-- Location: LABCELL_X1_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~34\); + +-- Location: FF_X1_Y34_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~33_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(3)); + +-- Location: LABCELL_X1_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~14\); + +-- Location: FF_X1_Y34_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(4)); + +-- Location: LABCELL_X1_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~10\); + +-- Location: FF_X1_Y34_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(5)); + +-- Location: LABCELL_X1_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(6) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(6) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(6), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~6\); + +-- Location: FF_X1_Y34_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(6)); + +-- Location: LABCELL_X1_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[7]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~2\); + +-- Location: FF_X1_Y34_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause[7]~DUPLICATE_q\); + +-- Location: LABCELL_X1_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(8) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(8) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~58\); + +-- Location: FF_X1_Y34_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~57_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(8)); + +-- Location: FF_X1_Y34_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~53_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(9)); + +-- Location: LABCELL_X1_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(14) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(14) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(14), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~50\); + +-- Location: FF_X1_Y34_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~49_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(14)); + +-- Location: LABCELL_X1_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add10~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add10~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pause\(15) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add10~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~45_sumout\); + +-- Location: FF_X1_Y34_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|pause[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add10~45_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pause\(15)); + +-- Location: LABCELL_X1_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal6~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pause\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pause\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pause\(14) & !\myVirtualToplevel|ZPUEVO:ZPU0|pause\(15))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~3_combout\); + +-- Location: LABCELL_X2_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal6~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pause[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal6~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pause\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100000001000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~4_combout\); + +-- Location: LABCELL_X26_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~24_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~4_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ & (!\myVirtualToplevel|MEM_BUSY~1_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~24_combout\); + +-- Location: LABCELL_X26_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddrPause~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddrPause~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddrPause~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|l1State~24_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddrPause~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111111111011111111100000000111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~24_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_LatchAddrPause~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~16_combout\); + +-- Location: FF_X26_Y19_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddrPause\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~16_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddrPause~q\); + +-- Location: LABCELL_X26_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~23_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & ( !\myVirtualToplevel|MEM_BUSY~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~23_combout\); + +-- Location: MLABCELL_X28_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~25_combout\ = ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~20_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~25_combout\); + +-- Location: MLABCELL_X28_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_PreSetAddr~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|l1State~25_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_PreSetAddr~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~25_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_PreSetAddr~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|l1State~25_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_PreSetAddr~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|l1State~25_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111111111111111111101001100111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_PreSetAddr~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~25_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~17_combout\); + +-- Location: FF_X28_Y21_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_PreSetAddr\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~17_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_PreSetAddr~q\); + +-- Location: LABCELL_X26_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~21_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( (!\myVirtualToplevel|MEM_BUSY~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_PreSetAddr~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_PreSetAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~21_combout\); + +-- Location: LABCELL_X26_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|l1State~21_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr~q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr~q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|l1State~21_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001000000000000011111111111111111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_LatchAddr~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~22_combout\); + +-- Location: LABCELL_X26_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|l1State~22_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|l1State~23_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|l1State~22_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000001111110000000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~23_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~22_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_LatchAddr~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~15_combout\); + +-- Location: FF_X26_Y19_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~15_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr~q\); + +-- Location: LABCELL_X26_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~18_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddrPause~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr~q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal6~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr~q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000000000000000000000000000000100000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_LatchAddrPause~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_LatchAddr~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~18_combout\); + +-- Location: LABCELL_X26_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|l1State~18_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\) # (\myVirtualToplevel|MEM_BUSY~1_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|l1State~18_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- (!\myVirtualToplevel|MEM_BUSY~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100000000000000000000011101111111011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~18_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~19_combout\); + +-- Location: LABCELL_X26_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|l1State~19_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|l1State~20_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|l1State~19_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000001111110000000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~19_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~14_combout\); + +-- Location: FF_X26_Y19_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~14_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\); + +-- Location: LABCELL_X26_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~0_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ & \myVirtualToplevel|RESET_n~q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\, + datad => \myVirtualToplevel|ALT_INV_RESET_n~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~0_combout\); + +-- Location: LABCELL_X25_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\); + +-- Location: LABCELL_X20_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_RESYN8613\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_RESYN8613_BDD8614\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101011111010101010101111101010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_RESYN8613_BDD8614\); + +-- Location: LABCELL_X20_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_RESYN8613_BDD8614\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_RESYN8613_BDD8614\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010000001000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~2_RESYN8613_BDD8614\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_combout\); + +-- Location: LABCELL_X20_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_RESYN12748\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_RESYN12748_BDD12749\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ $ +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011000011001100110011001111111100110000110000001100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_RESYN12748_BDD12749\); + +-- Location: LABCELL_X20_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_RESYN12748_BDD12749\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100010000000000010001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~3_RESYN12748_BDD12749\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_combout\); + +-- Location: LABCELL_X20_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111111111111111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\); + +-- Location: MLABCELL_X23_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~75\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~75_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~75_combout\); + +-- Location: FF_X23_Y29_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~75_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\); + +-- Location: FF_X23_Y29_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~73_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\); + +-- Location: MLABCELL_X23_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~73_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~73_combout\); + +-- Location: FF_X23_Y29_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~73_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~76\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~76_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001000000001111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~76_combout\); + +-- Location: FF_X19_Y32_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~76_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\); + +-- Location: MLABCELL_X23_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~74\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~74_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~74_combout\); + +-- Location: FF_X23_Y29_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~74_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\); + +-- Location: MLABCELL_X18_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100111101001100011100110111000001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~2_combout\); + +-- Location: LABCELL_X20_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110100000000000000000010000010001101001000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~47_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~54_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~1_combout\); + +-- Location: LABCELL_X21_Y39_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~0_combout\); + +-- Location: LABCELL_X20_Y37_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~94\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~94_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~94_combout\); + +-- Location: LABCELL_X20_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal12~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~94_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111110000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~94_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal12~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0_combout\); + +-- Location: LABCELL_X20_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000000000000000000011000000000000001100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\); + +-- Location: LABCELL_X21_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~66\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~66_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000111000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~427_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~66_combout\); + +-- Location: FF_X21_Y29_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~66_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\); + +-- Location: LABCELL_X21_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~67\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~67_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000111000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~428_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~67_combout\); + +-- Location: FF_X21_Y29_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~67_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\); + +-- Location: LABCELL_X21_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~65_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001110000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~426_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~65_combout\); + +-- Location: FF_X21_Y29_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~65_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~q\); + +-- Location: LABCELL_X21_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~68\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~68_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001110000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~429_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~68_combout\); + +-- Location: FF_X21_Y29_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~68_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~q\); + +-- Location: LABCELL_X21_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~0_combout\); + +-- Location: MLABCELL_X23_Y39_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) # +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "1111111111111111101111111111111111110001110101011011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~64_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\); + +-- Location: MLABCELL_X23_Y38_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_RESYN12508\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_RESYN12508_BDD12509\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001111100000000000111110000000001100000000000000110000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_RESYN12508_BDD12509\); + +-- Location: MLABCELL_X23_Y39_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_RESYN12508_BDD12509\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_RESYN12508_BDD12509\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101110111010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~4_RESYN12508_BDD12509\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_combout\); + +-- Location: MLABCELL_X23_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000000000000001100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~63_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\); + +-- Location: LABCELL_X21_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~72\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~72_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~429_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~72_combout\); + +-- Location: FF_X21_Y29_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~72_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~q\); + +-- Location: LABCELL_X21_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~71\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~71_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110010000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~428_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~71_combout\); + +-- Location: FF_X21_Y29_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~71_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\); + +-- Location: LABCELL_X21_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~69_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~426_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~69_combout\); + +-- Location: FF_X21_Y29_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~69_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~q\); + +-- Location: LABCELL_X21_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~70\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~70_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110010000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~427_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~70_combout\); + +-- Location: FF_X21_Y29_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~70_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\); + +-- Location: LABCELL_X21_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~1_combout\); + +-- Location: MLABCELL_X4_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_RESYN12516\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_RESYN12516_BDD12517\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001000000001001000100001001000100010000100100010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_RESYN12516_BDD12517\); + +-- Location: MLABCELL_X4_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_RESYN12516_BDD12517\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_RESYN12516_BDD12517\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010111010101010101010101110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~4_RESYN12516_BDD12517\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_combout\); + +-- Location: MLABCELL_X4_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_RESYN12518\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_RESYN12518_BDD12519\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100001111111100000000111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_RESYN12518_BDD12519\); + +-- Location: MLABCELL_X4_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_RESYN12518_BDD12519\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~5_RESYN12518_BDD12519\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_combout\); + +-- Location: MLABCELL_X4_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\); + +-- Location: LABCELL_X19_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~78\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~78_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~78_combout\); + +-- Location: FF_X19_Y32_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~78_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~q\); + +-- Location: LABCELL_X19_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~77_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~77_combout\); + +-- Location: FF_X19_Y32_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~77_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\); + +-- Location: LABCELL_X19_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~79\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~79_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~79_combout\); + +-- Location: FF_X19_Y32_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~79_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\); + +-- Location: LABCELL_X19_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~80\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~80_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~80_combout\); + +-- Location: FF_X19_Y32_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~80_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~q\); + +-- Location: LABCELL_X19_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~3_combout\); + +-- Location: MLABCELL_X18_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~0_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010010111110010001000001010011101110101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\); + +-- Location: MLABCELL_X18_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\); + +-- Location: LABCELL_X20_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000001010000001000000010100000000000010100010000000010100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\); + +-- Location: LABCELL_X21_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000000000101010100000000000100010000000001010001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23_combout\); + +-- Location: LABCELL_X20_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~37_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~37_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~53_combout\); + +-- Location: LABCELL_X25_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9225\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9225_BDD9226\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~53_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~53_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~53_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001000100010001000100010111111110010001000101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~53_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9225_BDD9226\); + +-- Location: LABCELL_X25_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9229\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9229_BDD9230\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9225_BDD9226\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9225_BDD9226\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9225_BDD9226\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9229_BDD9230\); + +-- Location: LABCELL_X25_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9233\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9233_BDD9234\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~53_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~53_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~53_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9233_BDD9234\); + +-- Location: LABCELL_X24_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~37_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~37_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~55_combout\); + +-- Location: LABCELL_X21_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_RESYN12686\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_RESYN12686_BDD12687\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000000000000000000000000000000100000000000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_RESYN12686_BDD12687\); + +-- Location: LABCELL_X21_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_RESYN12686_BDD12687\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_RESYN12686_BDD12687\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010101000000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~60_RESYN12686_BDD12687\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_combout\); + +-- Location: LABCELL_X20_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_RESYN8601\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_RESYN8601_BDD8602\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~37_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~37_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111101010101010101011111100001100001010100000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~37_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_RESYN8601_BDD8602\); + +-- Location: LABCELL_X20_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_RESYN8601_BDD8602\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_RESYN8601_BDD8602\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_RESYN8601_BDD8602\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_RESYN8601_BDD8602\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001000100010001000000000001100000000000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~58_RESYN8601_BDD8602\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_combout\); + +-- Location: LABCELL_X25_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~37_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add24~17_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~25_sumout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~37_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add24~17_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~33_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~25_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011010001110100011111001100111111110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~37_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~17_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~25_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~33_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~54_combout\); + +-- Location: LABCELL_X25_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9231\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9231_BDD9232\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~54_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~55_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9225_BDD9226\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~54_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~54_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~55_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9225_BDD9226\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~54_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000000111011100000000111111110000000001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9225_BDD9226\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~55_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~60_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~58_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~54_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9231_BDD9232\); + +-- Location: LABCELL_X25_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9231_BDD9232\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9233_BDD9234\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9229_BDD9230\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9231_BDD9232\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9233_BDD9234\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9229_BDD9230\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9231_BDD9232\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9233_BDD9234\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9229_BDD9230\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9231_BDD9232\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9233_BDD9234\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9229_BDD9230\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011011100110111001111110011111111111111001101111111111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9229_BDD9230\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9233_BDD9234\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~51_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9231_BDD9232\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_combout\); + +-- Location: FF_X25_Y26_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6)); + +-- Location: LABCELL_X26_Y21_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]_NEW1940\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]_OTERM1941\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~1_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~1_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]_OTERM1941\); + +-- Location: FF_X26_Y21_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]_OTERM1941\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\); + +-- Location: FF_X29_Y24_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]_OTERM1895\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE_q\); + +-- Location: LABCELL_X26_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000100000010000000001000000001000000000100000010000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~1_combout\); + +-- Location: LABCELL_X25_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000001000001000000000001001000000000001000001000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~0_combout\); + +-- Location: LABCELL_X25_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000000010100000101001010000010100000000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~2_combout\); + +-- Location: LABCELL_X25_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000000000001111000000001111000000000000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~3_combout\); + +-- Location: LABCELL_X24_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010010000000010011001000000001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~4_combout\); + +-- Location: MLABCELL_X28_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010010100000000101001010000000000000000101001010000000010100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[18]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~8_combout\); + +-- Location: LABCELL_X29_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000100000010000000001000000001000000000100000010000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[16]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~7_combout\); + +-- Location: LABCELL_X29_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(20) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(20) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[21]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~5_combout\); + +-- Location: LABCELL_X29_Y22_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010010000000010011001000000001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[22]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~6_combout\); + +-- Location: MLABCELL_X28_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~8_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(17)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000100100001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~9_combout\); + +-- Location: LABCELL_X25_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\); + +-- Location: LABCELL_X25_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101000001010000010101010101010101010000010101000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\); + +-- Location: MLABCELL_X28_Y24_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]_NEW1868\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]_OTERM1869\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(20))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~65_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(20))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]_OTERM1869\); + +-- Location: FF_X28_Y24_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]_OTERM1869\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(20)); + +-- Location: LABCELL_X31_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~1_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~9_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\); + +-- Location: LABCELL_X21_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000001100000000000000010000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\); + +-- Location: LABCELL_X21_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~92\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~92_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100100010001000001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~431_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~92_combout\); + +-- Location: FF_X21_Y30_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~92_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\); + +-- Location: LABCELL_X19_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~94\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~94_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000111111111111111000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~94_combout\); + +-- Location: FF_X19_Y31_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~94_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\); + +-- Location: MLABCELL_X23_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~93_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~93_combout\); + +-- Location: FF_X23_Y29_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~93_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\); + +-- Location: LABCELL_X19_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~91\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~91_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000101010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~431_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~91_combout\); + +-- Location: FF_X19_Y31_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~91_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\); + +-- Location: MLABCELL_X18_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~8_combout\); + +-- Location: LABCELL_X21_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000001010100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\); + +-- Location: LABCELL_X19_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~83\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~83_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~433_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~83_combout\); + +-- Location: FF_X19_Y33_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~83_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~q\); + +-- Location: LABCELL_X19_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~85_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000100001110111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~85_combout\); + +-- Location: FF_X19_Y33_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~85_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~q\); + +-- Location: LABCELL_X19_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~86\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~86_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~86_combout\); + +-- Location: FF_X19_Y33_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~86_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~q\); + +-- Location: LABCELL_X21_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~84\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~84_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110010000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~433_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~84_combout\); + +-- Location: FF_X21_Y30_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~84_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\); + +-- Location: LABCELL_X19_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~6_combout\); + +-- Location: LABCELL_X20_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111011111111111111111111111111111110111011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~3_combout\); + +-- Location: FF_X19_Y31_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\); + +-- Location: LABCELL_X19_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~82\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~82_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000111111111111111100000000000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~82_combout\); + +-- Location: FF_X19_Y31_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~82_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~q\); + +-- Location: LABCELL_X20_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860_RESYN12810\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860_RESYN12810_BDD12811\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011101110111011101110111011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860_RESYN12810_BDD12811\); + +-- Location: LABCELL_X20_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_OTERM1861\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860_RESYN12810_BDD12811\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860_RESYN12810_BDD12811\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101111111111111110111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]_NEW1860_RESYN12810_BDD12811\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_OTERM1861\); + +-- Location: FF_X20_Y31_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_OTERM1861\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\); + +-- Location: LABCELL_X21_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000001000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\); + +-- Location: LABCELL_X21_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~81_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~432_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~81_combout\); + +-- Location: FF_X21_Y30_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~81_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\); + +-- Location: LABCELL_X19_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~5_combout\); + +-- Location: LABCELL_X19_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~90\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~90_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~90_combout\); + +-- Location: FF_X19_Y33_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~90_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~q\); + +-- Location: LABCELL_X19_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~89_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111111101100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~89_combout\); + +-- Location: FF_X19_Y33_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~89_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~q\); + +-- Location: LABCELL_X21_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000001000100000000000000010000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\); + +-- Location: LABCELL_X19_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~88\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~88_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~430_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~88_combout\); + +-- Location: FF_X19_Y33_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~88_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~q\); + +-- Location: LABCELL_X19_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~87\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~87_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110010000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~430_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~87_combout\); + +-- Location: FF_X19_Y33_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~87_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~q\); + +-- Location: LABCELL_X19_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~7_combout\); + +-- Location: MLABCELL_X18_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~8_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~6_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101100010011100110100100011011001111010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\); + +-- Location: MLABCELL_X18_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100010000000000010001000000101001001110000010100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\); + +-- Location: LABCELL_X19_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100000000000000010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\); + +-- Location: LABCELL_X19_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~25_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\); + +-- Location: LABCELL_X25_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011001100110011101110110011001110111011001100111011101100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~17_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\); + +-- Location: FF_X20_Y29_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~71_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~69_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~69_combout\); + +-- Location: LABCELL_X21_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~70\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~70_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~25_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~25_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111111111111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~70_combout\); + +-- Location: LABCELL_X25_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~68\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~68_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000000000000101000011110000010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~68_combout\); + +-- Location: LABCELL_X21_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~67\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~67_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~67_combout\); + +-- Location: LABCELL_X20_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~71\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~71_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~67_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|pc~68_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~70_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~69_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~67_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~68_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~70_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~69_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111111111111001111111111111101111111111111110111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~69_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~70_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~68_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~67_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~71_combout\); + +-- Location: FF_X20_Y29_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~71_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)); + +-- Location: LABCELL_X20_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~61_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100100010001000001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~431_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~61_combout\); + +-- Location: FF_X20_Y31_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~61_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\); + +-- Location: LABCELL_X20_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~64\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~64_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~64_combout\); + +-- Location: FF_X20_Y31_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~64_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~q\); + +-- Location: LABCELL_X20_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~62\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~62_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100100010001000001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~431_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~62_combout\); + +-- Location: FF_X20_Y31_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~62_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~q\); + +-- Location: LABCELL_X20_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~63\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~63_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000101010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~431_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~63_combout\); + +-- Location: FF_X20_Y31_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~63_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\); + +-- Location: LABCELL_X20_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~8_combout\); + +-- Location: MLABCELL_X18_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000111000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~433_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~53_combout\); + +-- Location: FF_X18_Y30_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~53_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~q\); + +-- Location: MLABCELL_X18_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000010000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~56_combout\); + +-- Location: FF_X18_Y30_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~56_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~q\); + +-- Location: FF_X21_Y30_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~55_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\); + +-- Location: LABCELL_X21_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110010000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~433_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~55_combout\); + +-- Location: FF_X21_Y30_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~55_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000101010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~433_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~54_combout\); + +-- Location: FF_X18_Y30_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~54_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~q\); + +-- Location: MLABCELL_X18_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~6_combout\); + +-- Location: LABCELL_X17_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~7_combout\); + +-- Location: FF_X18_Y30_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\); + +-- Location: LABCELL_X20_Y37_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_RESYN12744\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_RESYN12744_BDD12745\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~82_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001111100011111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~82_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_RESYN12744_BDD12745\); + +-- Location: MLABCELL_X18_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_RESYN12744_BDD12745\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111111111111111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~7_RESYN12744_BDD12745\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_combout\); + +-- Location: FF_X18_Y30_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~q\); + +-- Location: MLABCELL_X18_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010000010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~432_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~51_combout\); + +-- Location: FF_X18_Y30_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~51_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~q\); + +-- Location: MLABCELL_X18_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~52_combout\); + +-- Location: FF_X18_Y30_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~52_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\); + +-- Location: MLABCELL_X18_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~5_combout\); + +-- Location: LABCELL_X20_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~57_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100100010001000001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~430_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~57_combout\); + +-- Location: FF_X20_Y31_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~57_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\); + +-- Location: LABCELL_X20_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~58_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100100010001000001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~430_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~58_combout\); + +-- Location: FF_X20_Y31_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~58_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\); + +-- Location: LABCELL_X20_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~59_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010000010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~430_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~59_combout\); + +-- Location: FF_X20_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~59_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\); + +-- Location: LABCELL_X25_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~60\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~60_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~60_combout\); + +-- Location: FF_X25_Y31_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~60_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\); + +-- Location: LABCELL_X20_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~7_combout\); + +-- Location: LABCELL_X17_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~8_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101100010011100110100100011011001111010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9_combout\); + +-- Location: LABCELL_X17_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\); + +-- Location: LABCELL_X17_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000000000010000100000000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\); + +-- Location: LABCELL_X20_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\); + +-- Location: FF_X24_Y29_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~66_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010000010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~433_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~26_combout\); + +-- Location: FF_X17_Y31_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~26_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\); + +-- Location: LABCELL_X17_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000110010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~433_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~24_combout\); + +-- Location: FF_X17_Y31_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\); + +-- Location: LABCELL_X17_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001110000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~433_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~23_combout\); + +-- Location: FF_X17_Y31_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~23_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~q\); + +-- Location: LABCELL_X21_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111101111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~25_combout\); + +-- Location: FF_X21_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~q\); + +-- Location: LABCELL_X17_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000000000101010100001111001100111111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~6_combout\); + +-- Location: LABCELL_X17_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001110000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~431_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~31_combout\); + +-- Location: FF_X17_Y31_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~31_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~q\); + +-- Location: LABCELL_X16_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~33_combout\); + +-- Location: FF_X16_Y31_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~33_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\); + +-- Location: LABCELL_X17_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000110010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~431_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~34_combout\); + +-- Location: FF_X17_Y31_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~q\); + +-- Location: FF_X17_Y31_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~32_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~q\); + +-- Location: LABCELL_X17_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001100000010001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~431_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~32_combout\); + +-- Location: FF_X17_Y31_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~32_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~8_combout\); + +-- Location: LABCELL_X17_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001110000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~430_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~30_combout\); + +-- Location: FF_X17_Y31_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~30_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~q\); + +-- Location: LABCELL_X17_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000111000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~430_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~27_combout\); + +-- Location: FF_X17_Y31_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~27_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~q\); + +-- Location: LABCELL_X21_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001111111111110111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~29_combout\); + +-- Location: FF_X21_Y31_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~29_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\); + +-- Location: LABCELL_X17_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001110000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~430_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~28_combout\); + +-- Location: FF_X17_Y31_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~28_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\); + +-- Location: LABCELL_X17_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~7_combout\); + +-- Location: MLABCELL_X23_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000100010000001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~432_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~22_combout\); + +-- Location: FF_X23_Y28_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~22_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~q\); + +-- Location: LABCELL_X20_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136_RESYN12724\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136_RESYN12724_BDD12725\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111111111000011111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136_RESYN12724_BDD12725\); + +-- Location: MLABCELL_X23_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136_RESYN12724_BDD12725\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136_RESYN12724_BDD12725\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136_RESYN12724_BDD12725\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136_RESYN12724_BDD12725\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111101111111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136_RESYN12724_BDD12725\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~combout\); + +-- Location: FF_X23_Y28_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\); + +-- Location: MLABCELL_X23_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]_NEW1850\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]_OTERM1851\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]_OTERM1851\); + +-- Location: FF_X23_Y28_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]_OTERM1851\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~q\); + +-- Location: MLABCELL_X23_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010000010001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~432_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~21_combout\); + +-- Location: FF_X23_Y28_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~21_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~q\); + +-- Location: MLABCELL_X23_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~5_combout\); + +-- Location: LABCELL_X17_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~7_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~8_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~8_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~8_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101001001100011011110001100100111011010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\); + +-- Location: LABCELL_X17_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\); + +-- Location: LABCELL_X17_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100000000000000010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\); + +-- Location: LABCELL_X25_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~74\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~74_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001010101000000000010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~74_combout\); + +-- Location: LABCELL_X24_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~75\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~75_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add32~29_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100111111000011110011111100000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~29_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~75_combout\); + +-- Location: LABCELL_X25_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~73_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000110000001100110000001100000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~73_combout\); + +-- Location: LABCELL_X25_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~72\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~72_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~72_combout\); + +-- Location: LABCELL_X25_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~76\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~76_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~72_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|pc~73_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~75_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~74_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~72_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~73_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~75_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~74_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111111111111001111111111111101111111111111110111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~74_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~75_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~73_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~72_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~76_combout\); + +-- Location: FF_X25_Y29_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~76_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\); + +-- Location: LABCELL_X21_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010001011001010110111001000101000010100010011101101011101011010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\); + +-- Location: LABCELL_X25_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~124\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~124_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~77_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~124_combout\); + +-- Location: LABCELL_X24_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~125\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~125_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010001000000000001000100000000101110110000000010111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~77_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~125_combout\); + +-- Location: LABCELL_X21_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~70\); + +-- Location: LABCELL_X24_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~126\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~126_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~69_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111111111000000111111111100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~69_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~126_combout\); + +-- Location: LABCELL_X26_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~70\); + +-- Location: LABCELL_X29_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~78\); + +-- Location: LABCELL_X29_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~74\); + +-- Location: LABCELL_X24_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~70\); + +-- Location: LABCELL_X24_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~123\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~123_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~69_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add23~77_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~69_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~69_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add23~77_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~69_sumout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~69_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~73_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~69_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~73_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~69_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~77_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~73_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~69_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~123_combout\); + +-- Location: LABCELL_X25_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~127\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~127_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~123_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|pc~126_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~125_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~124_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~123_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~126_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~125_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~124_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011111111111011101111111111101111111111111110111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~124_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~125_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~126_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~123_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~127_combout\); + +-- Location: FF_X25_Y23_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~127_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\); + +-- Location: FF_X26_Y27_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~12_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23)); + +-- Location: LABCELL_X25_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23)) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~21_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~7_combout\); + +-- Location: LABCELL_X26_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~21_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~5_combout\); + +-- Location: LABCELL_X29_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add22~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~1_sumout\); + +-- Location: LABCELL_X24_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add25~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add25~1_sumout\); + +-- Location: LABCELL_X26_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add24~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add24~1_sumout\); + +-- Location: LABCELL_X29_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add23~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~1_sumout\); + +-- Location: LABCELL_X26_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~1_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~1_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~1_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~1_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~1_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~1_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~3_combout\); + +-- Location: LABCELL_X21_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add32~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add32~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add32~1_sumout\); + +-- Location: MLABCELL_X23_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111000000001111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~11_combout\); + +-- Location: LABCELL_X26_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~11_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~11_combout\ ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~11_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~7_combout\) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111101011111011111110111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~12_combout\); + +-- Location: FF_X26_Y27_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~12_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y23_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE_q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\); + +-- Location: LABCELL_X24_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010000000000000000010101010101010101010101000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\); + +-- Location: LABCELL_X12_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # ((\myVirtualToplevel|MEM_BUSY~1_combout\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011011111111111111101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~42_combout\); + +-- Location: LABCELL_X12_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|MEM_BUSY~1_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~41_combout\); + +-- Location: LABCELL_X12_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~42_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~41_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~42_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~41_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~42_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~41_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110111111001111111011111100111111101111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~42_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~41_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~43_combout\); + +-- Location: FF_X12_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~43_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\); + +-- Location: LABCELL_X16_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\); + +-- Location: LABCELL_X17_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr195~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~3_combout\); + +-- Location: LABCELL_X17_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~3_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010001000101010101000100010101010100010001010101000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr116~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~0_combout\); + +-- Location: LABCELL_X17_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & +-- (\myVirtualToplevel|RESET_n~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & !\myVirtualToplevel|MEM_BUSY~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000010000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\); + +-- Location: LABCELL_X35_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(23) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(23), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~17_sumout\); + +-- Location: LABCELL_X35_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(23) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(23), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~17_sumout\); + +-- Location: LABCELL_X35_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1675~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1675~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add56~17_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add56~17_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~17_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1675~0_combout\); + +-- Location: MLABCELL_X34_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[23]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[23]~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\ & ( \myVirtualToplevel|RESET_n~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[23]~2_combout\); + +-- Location: FF_X35_Y20_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1675~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[23]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(23)); + +-- Location: LABCELL_X14_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add6~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~2_combout\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~17_sumout\); + +-- Location: LABCELL_X16_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector193~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~17_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~17_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ $ +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~17_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000110011000011110000110011001100111111111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~1_combout\); + +-- Location: LABCELL_X16_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector193~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector193~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(23)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector193~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(23))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000010000000111000011011111110111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector193~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~0_combout\); + +-- Location: LABCELL_X16_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]_NEW3344\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]_OTERM3345\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # (\myVirtualToplevel|MEM_DATA_READ[23]~19_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector193~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000111010001000100011101110100011101110111010001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~19_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector193~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]_OTERM3345\); + +-- Location: FF_X16_Y13_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]_OTERM3345\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y14_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~0_combout\ = ( \myVirtualToplevel|LessThan0~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\))) ) ) # ( !\myVirtualToplevel|LessThan0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000011110000001100001111000000000011000011110000001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + dataf => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~0_combout\); + +-- Location: FF_X23_Y14_N32 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuLastEN\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuLastEN~q\); + +-- Location: MLABCELL_X23_Y14_N39 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ = ( \myVirtualToplevel|LessThan0~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuLastEN~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\)))) ) ) # ( !\myVirtualToplevel|LessThan0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuLastEN~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000010100000001000001010000000010000010100000001000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuLastEN~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + dataf => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\); + +-- Location: FF_X17_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~49_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~48_combout\ = ( \myVirtualToplevel|MEM_BUSY~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011011111110111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_NOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~48_combout\); + +-- Location: LABCELL_X17_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( (!\myVirtualToplevel|MEM_BUSY~1_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~47_combout\); + +-- Location: LABCELL_X17_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~47_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~47_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~47_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~48_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~47_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~48_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010000000101010111111111111111111100000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~47_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~49_combout\); + +-- Location: FF_X17_Y17_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~49_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~q\); + +-- Location: LABCELL_X12_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~50_combout\ = ( \myVirtualToplevel|MEM_BUSY~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2~q\ ) ) # ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\))) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2~q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000000000000000000000011011111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS_2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~50_combout\); + +-- Location: LABCELL_X12_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~50_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~50_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101010000000001110101000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~50_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~51_combout\); + +-- Location: FF_X12_Y17_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~51_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2~q\); + +-- Location: LABCELL_X12_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\ = ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000011100000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_NOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS_2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\); + +-- Location: FF_X19_Y18_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\); + +-- Location: LABCELL_X16_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|NOS~1_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111111111000011111111111100001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS~1_combout\); + +-- Location: LABCELL_X17_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001000000010100000101000001010000010000000101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~1_combout\); + +-- Location: MLABCELL_X18_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000000000000000000000000000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~0_combout\); + +-- Location: LABCELL_X17_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000000111100001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~2_combout\); + +-- Location: LABCELL_X17_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr171~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~3_combout\); + +-- Location: LABCELL_X17_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~3_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000001111110011111100001111000000000011111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1349~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~1_combout\); + +-- Location: FF_X17_Y33_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~1_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|NOS~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\); + +-- Location: FF_X16_Y29_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid_OTERM3342\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~q\); + +-- Location: LABCELL_X16_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~q\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010101010101000001010101010100001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\); + +-- Location: LABCELL_X24_Y31_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~154\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~154_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111101010101010111110101010101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~154_combout\); + +-- Location: LABCELL_X24_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|TOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~0_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~0_combout\); + +-- Location: LABCELL_X24_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~156\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~156_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000101110100001100110011000000110011011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~25_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~156_combout\); + +-- Location: LABCELL_X24_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~157\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~157_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~156_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~156_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111001000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~156_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~157_combout\); + +-- Location: LABCELL_X20_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12462\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12462_BDD12463\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~6_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~2_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111110111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12462_BDD12463\); + +-- Location: LABCELL_X20_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12464\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12464_BDD12465\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12462_BDD12463\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12462_BDD12463\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~4_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12462_BDD12463\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12462_BDD12463\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111110101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_RESYN12462_BDD12463\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12464_BDD12465\); + +-- Location: LABCELL_X20_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12464_BDD12465\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_RESYN12464_BDD12465\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_combout\); + +-- Location: LABCELL_X20_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector387~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100110011000000110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~0_combout\); + +-- Location: LABCELL_X20_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector387~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100000000110011000000000011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~1_combout\); + +-- Location: LABCELL_X20_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector387~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000011110000111100001111000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~2_combout\); + +-- Location: LABCELL_X20_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~155\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~155_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector387~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector387~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add32~93_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector387~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector387~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector387~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add32~93_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector387~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111000000000111000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~93_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~155_combout\); + +-- Location: LABCELL_X24_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_RESYN13460\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_RESYN13460_BDD13461\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_RESYN13460_BDD13461\); + +-- Location: LABCELL_X24_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_BDD8942\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_RESYN13460_BDD13461\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_RESYN13460_BDD13461\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_RESYN13460_BDD13461\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_RESYN13460_BDD13461\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001111101000000000101110110000000011111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_RESYN8941_RESYN13460_BDD13461\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_BDD8942\); + +-- Location: LABCELL_X24_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~158\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_BDD8942\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_BDD8942\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000011000100111111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_RESYN8941_BDD8942\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_combout\); + +-- Location: MLABCELL_X23_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~159\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~159_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~154_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~154_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~158_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~154_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~157_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~155_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~158_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~154_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~157_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~155_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010000010101010101000101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~154_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~157_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~155_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~159_combout\); + +-- Location: FF_X23_Y31_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~159_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~18\); + +-- Location: LABCELL_X25_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~64\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~64_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010100000101000000101000001010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~64_combout\); + +-- Location: MLABCELL_X23_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~65_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add32~21_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~21_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010111110101111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~21_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~65_combout\); + +-- Location: LABCELL_X25_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~63\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~63_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000111100000000111100000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~63_combout\); + +-- Location: LABCELL_X24_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~62\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~62_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111111111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~62_combout\); + +-- Location: LABCELL_X24_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~66\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~66_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~62_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~63_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~65_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~64_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~62_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~63_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~65_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~64_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111111101111111011111110111111101111111111111110111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~64_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~65_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~63_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~62_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~66_combout\); + +-- Location: FF_X24_Y29_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~66_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)); + +-- Location: LABCELL_X20_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~172\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~172_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~172_combout\); + +-- Location: FF_X20_Y30_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~172_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\); + +-- Location: MLABCELL_X23_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]_NEW1854\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]_OTERM1855\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]_OTERM1855\); + +-- Location: FF_X23_Y28_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]_OTERM1855\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\); + +-- Location: LABCELL_X20_Y36_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_RESYN12528\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_RESYN12528_BDD12529\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)))) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001000100000000100100010000000000101000100000000010100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_RESYN12528_BDD12529\); + +-- Location: LABCELL_X20_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_RESYN12528_BDD12529\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_RESYN12528_BDD12529\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000000000000001000000000000000000010000000000000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~3_RESYN12528_BDD12529\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_combout\); + +-- Location: LABCELL_X20_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~88\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~88_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000000000000010000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~88_combout\); + +-- Location: LABCELL_X20_Y36_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~88_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~88_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000000010001000000000011001100000000001100110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~88_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~4_combout\); + +-- Location: LABCELL_X20_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_RESYN12758\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_RESYN12758_BDD12759\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000100010001000100010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_RESYN12758_BDD12759\); + +-- Location: LABCELL_X20_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_RESYN12758_BDD12759\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~104_RESYN12758_BDD12759\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_combout\); + +-- Location: LABCELL_X20_Y36_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~5_RESYN12760\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~5_RESYN12760_BDD12761\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010010001000010001001000100000010001000000000001000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~5_RESYN12760_BDD12761\); + +-- Location: LABCELL_X20_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852_RESYN12808\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852_RESYN12808_BDD12809\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~5_RESYN12760_BDD12761\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~5_RESYN12760_BDD12761\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~5_RESYN12760_BDD12761\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~5_RESYN12760_BDD12761\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010111010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~104_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~5_RESYN12760_BDD12761\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852_RESYN12808_BDD12809\); + +-- Location: FF_X19_Y28_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_OTERM1853\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\); + +-- Location: LABCELL_X19_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_OTERM1853\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852_RESYN12808_BDD12809\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852_RESYN12808_BDD12809\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_combout\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101111111111111110111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]_NEW1852_RESYN12808_BDD12809\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_OTERM1853\); + +-- Location: FF_X19_Y28_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_OTERM1853\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~173\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~173_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~173_combout\); + +-- Location: FF_X20_Y30_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~173_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~q\); + +-- Location: LABCELL_X19_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~5_combout\); + +-- Location: MLABCELL_X23_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~178\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~178_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000001001111101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~178_combout\); + +-- Location: FF_X23_Y29_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~178_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~q\); + +-- Location: LABCELL_X20_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~181\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~181_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~181_combout\); + +-- Location: FF_X20_Y30_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~181_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~q\); + +-- Location: LABCELL_X20_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~179\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~179_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~179_combout\); + +-- Location: FF_X20_Y30_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~179_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\); + +-- Location: LABCELL_X20_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~180\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~180_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~180_combout\); + +-- Location: FF_X20_Y30_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~180_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~q\); + +-- Location: LABCELL_X19_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~7_combout\); + +-- Location: LABCELL_X20_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~185\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~185_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100111111111111111100000000000000001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~185_combout\); + +-- Location: FF_X20_Y30_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~185_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\); + +-- Location: LABCELL_X20_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~183\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~183_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100111111111111111100000000000000001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~183_combout\); + +-- Location: FF_X20_Y30_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~183_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\); + +-- Location: MLABCELL_X23_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~182\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~182_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~182_combout\); + +-- Location: FF_X23_Y29_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~182_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~q\); + +-- Location: LABCELL_X20_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~184\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~184_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000101111111111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~184_combout\); + +-- Location: FF_X20_Y30_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~184_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\); + +-- Location: LABCELL_X19_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~8_combout\); + +-- Location: LABCELL_X20_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~174\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~174_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~174_combout\); + +-- Location: FF_X20_Y30_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~174_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\); + +-- Location: LABCELL_X20_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~177\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~177_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010000001111111111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~177_combout\); + +-- Location: FF_X20_Y30_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~177_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\); + +-- Location: LABCELL_X21_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~175\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~175_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100111111111111111000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~175_combout\); + +-- Location: FF_X21_Y30_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~175_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\); + +-- Location: LABCELL_X20_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~176\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~176_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111101100000000000001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~176_combout\); + +-- Location: FF_X20_Y30_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~176_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\); + +-- Location: LABCELL_X19_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~6_combout\); + +-- Location: LABCELL_X19_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~7_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~7_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~7_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000101010001001010010111101110000011110100111010101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\); + +-- Location: LABCELL_X19_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\); + +-- Location: LABCELL_X17_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector363~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000011000000000001000010000101011001101011010010110100001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~0_combout\); + +-- Location: LABCELL_X31_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector363~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector363~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111110101010000011111011101100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector363~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~0_combout\); + +-- Location: LABCELL_X31_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111111110111111100000000010101011111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~1_combout\); + +-- Location: FF_X31_Y26_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\); + +-- Location: LABCELL_X36_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( (\myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111111111111111111100001111000010101111111110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_intTriggered~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~0_combout\); + +-- Location: FF_X36_Y26_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|intTriggered\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~0_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~q\); + +-- Location: LABCELL_X35_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inInterrupt~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_intTriggered~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\); + +-- Location: MLABCELL_X28_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111010111111111111111110111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\); + +-- Location: MLABCELL_X18_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\ +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010111111111111111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~2_combout\); + +-- Location: FF_X18_Y33_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|inBreak\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\); + +-- Location: FF_X23_Y31_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12718\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12718_BDD12719\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add32~89_sumout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector387~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001000000010000000100000001111111110000000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~89_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12718_BDD12719\); + +-- Location: LABCELL_X24_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~152\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\); + +-- Location: MLABCELL_X23_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~149\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~149_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011101110111111001110111011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~149_combout\); + +-- Location: LABCELL_X20_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000110101011100000000010101010101011101010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~25_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~3_combout\); + +-- Location: LABCELL_X20_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~10_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~3_combout\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~3_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000111011000001011011111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~3_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~10_combout\); + +-- Location: MLABCELL_X23_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12722\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12722_BDD12723\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~10_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~10_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~149_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~149_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~149_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000001000101111001000000000111111110010001011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~149_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~152_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12722_BDD12723\); + +-- Location: MLABCELL_X23_Y31_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12720\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12720_BDD12721\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12720_BDD12721\); + +-- Location: MLABCELL_X23_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_RESYN13458\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_RESYN13458_BDD13459\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_RESYN13458_BDD13459\); + +-- Location: MLABCELL_X23_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_BDD8938\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_RESYN13458_BDD13459\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_RESYN13458_BDD13459\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101000011000000000101000000000011000000110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8937_RESYN13458_BDD13459\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_BDD8938\); + +-- Location: MLABCELL_X23_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8939\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8939_BDD8940\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8939_BDD8940\); + +-- Location: MLABCELL_X23_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~151\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8939_BDD8940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8939_BDD8940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8939_BDD8940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8939_BDD8940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_BDD8938\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011000000000011001100000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8937_BDD8938\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8939_BDD8940\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_combout\); + +-- Location: MLABCELL_X23_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~153\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12720_BDD12721\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12722_BDD12723\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12720_BDD12721\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12722_BDD12723\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12720_BDD12721\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~151_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12718_BDD12719\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12722_BDD12723\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12720_BDD12721\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~151_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12718_BDD12719\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12722_BDD12723\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001111100011111001111110001111100111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12718_BDD12719\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~152_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12722_BDD12723\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12720_BDD12721\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_combout\); + +-- Location: FF_X23_Y31_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)); + +-- Location: MLABCELL_X23_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~153\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~153_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000010000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~153_combout\); + +-- Location: FF_X23_Y31_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~153_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~q\); + +-- Location: MLABCELL_X23_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~152\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~152_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~152_combout\); + +-- Location: FF_X23_Y31_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~152_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~q\); + +-- Location: MLABCELL_X23_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~154\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~154_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~154_combout\); + +-- Location: FF_X23_Y31_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~154_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\); + +-- Location: LABCELL_X24_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~155\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~155_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000111111111111111000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~155_combout\); + +-- Location: FF_X24_Y31_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~155_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\); + +-- Location: MLABCELL_X23_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~q\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~8_combout\); + +-- Location: MLABCELL_X23_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~144\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~144_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111101111111100000001000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~144_combout\); + +-- Location: FF_X23_Y31_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~144_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\); + +-- Location: FF_X23_Y31_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~147_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\); + +-- Location: MLABCELL_X23_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~147\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~147_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000111111111111111100000000000000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~147_combout\); + +-- Location: FF_X23_Y31_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~147_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~146\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~146_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111110111100000000000100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~146_combout\); + +-- Location: FF_X23_Y31_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~146_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~q\); + +-- Location: MLABCELL_X23_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~145\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~145_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000111111111111111100000000000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~145_combout\); + +-- Location: FF_X23_Y31_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~145_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~q\); + +-- Location: MLABCELL_X23_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~DUPLICATE_q\) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111000001010000010100100010011101111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~6_combout\); + +-- Location: LABCELL_X21_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~148\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~148_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~148_combout\); + +-- Location: FF_X21_Y33_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~148_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~q\); + +-- Location: LABCELL_X21_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~151\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~151_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000111111111111111000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~151_combout\); + +-- Location: FF_X21_Y33_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~151_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~q\); + +-- Location: LABCELL_X21_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~150\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~150_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111110100000000000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~150_combout\); + +-- Location: FF_X21_Y33_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~150_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~q\); + +-- Location: LABCELL_X21_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~149\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~149_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000100111111111111111000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~149_combout\); + +-- Location: FF_X21_Y33_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~149_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\); + +-- Location: LABCELL_X21_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~7_combout\); + +-- Location: LABCELL_X21_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~143\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~143_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000111111111111111100000000000000001111111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~143_combout\); + +-- Location: FF_X21_Y33_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~143_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~q\); + +-- Location: LABCELL_X21_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]_NEW1856\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]_OTERM1857\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]_OTERM1857\); + +-- Location: FF_X21_Y33_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]_OTERM1857\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\); + +-- Location: LABCELL_X21_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]_NEW1858\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]_OTERM1859\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]_OTERM1859\); + +-- Location: FF_X21_Y33_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]_OTERM1859\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\); + +-- Location: LABCELL_X21_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~142\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~142_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010000111111111111111100000000000000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~142_combout\); + +-- Location: FF_X21_Y33_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~142_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~q\); + +-- Location: LABCELL_X21_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~5_combout\); + +-- Location: LABCELL_X20_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~7_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011101001100110001110111001100000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\); + +-- Location: LABCELL_X20_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\); + +-- Location: LABCELL_X26_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101100001000010000000000010000000000000000000000100000001000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\); + +-- Location: MLABCELL_X23_Y23_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~85_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~45_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~85_combout\); + +-- Location: MLABCELL_X23_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~84\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~84_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000110000001100000000000000001100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~45_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~84_combout\); + +-- Location: MLABCELL_X23_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~86\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~86_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add32~37_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~37_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~37_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~86_combout\); + +-- Location: MLABCELL_X23_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~83\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~83_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~37_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~45_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~37_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~41_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~37_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~41_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~37_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~45_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~83_combout\); + +-- Location: MLABCELL_X23_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~87\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~87_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~86_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~83_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~86_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~83_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~84_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~85_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~86_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~83_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~86_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~83_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~84_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~85_combout\) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010111111111111111111111111101011111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~85_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~84_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~86_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~83_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~87_combout\); + +-- Location: FF_X23_Y23_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~87_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y24_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]_NEW3277\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]_OTERM3278\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~61_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~61_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]_OTERM3278\); + +-- Location: FF_X25_Y24_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]_OTERM3278\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10)); + +-- Location: LABCELL_X14_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector206~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ $ (((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~61_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~61_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000000011110000111111000011111100001100111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~61_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~1_combout\); + +-- Location: LABCELL_X16_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector206~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector206~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector206~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000010100000011000011111111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector206~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~0_combout\); + +-- Location: FF_X16_Y15_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10)); + +-- Location: LABCELL_X17_Y13_N54 +\myVirtualToplevel|SD_CS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_CS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9), + combout => \myVirtualToplevel|SD_CS~0_combout\); + +-- Location: LABCELL_X16_Y13_N6 +\myVirtualToplevel|SD_CS_RESYN9119\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_CS_RESYN9119_BDD9120\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[19]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[20]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(22)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[19]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[20]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|SD_CS_RESYN9119_BDD9120\); + +-- Location: LABCELL_X16_Y13_N45 +\myVirtualToplevel|SD_CS_RESYN9121\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_CS_RESYN9121_BDD9122\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(18) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(21)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000000000000100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(13), + combout => \myVirtualToplevel|SD_CS_RESYN9121_BDD9122\); + +-- Location: LABCELL_X17_Y13_N12 +\myVirtualToplevel|SD_CS\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_CS~combout\ = ( \myVirtualToplevel|SD_CS_RESYN9119_BDD9120\ & ( \myVirtualToplevel|SD_CS_RESYN9121_BDD9122\ & ( (\myVirtualToplevel|SD_CS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(17)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_CS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(17), + datae => \myVirtualToplevel|ALT_INV_SD_CS_RESYN9119_BDD9120\, + dataf => \myVirtualToplevel|ALT_INV_SD_CS_RESYN9121_BDD9122\, + combout => \myVirtualToplevel|SD_CS~combout\); + +-- Location: LABCELL_X21_Y14_N39 +\myVirtualToplevel|MEM_DATA_READ[17]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[17]~25_combout\ = (\myVirtualToplevel|SD_CS~combout\ & (!\myVirtualToplevel|LessThan0~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000000000000010100000000000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_CS~combout\, + datac => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|MEM_DATA_READ[17]~25_combout\); + +-- Location: LABCELL_X24_Y9_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector14~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector14~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(1) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(1), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector14~0_combout\); + +-- Location: FF_X24_Y9_N59 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector14~0_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1), + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(1)); + +-- Location: LABCELL_X21_Y9_N12 +\myVirtualToplevel|IO_DATA_READ_SD[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_DATA_READ_SD[17]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(1) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(1), + combout => \myVirtualToplevel|IO_DATA_READ_SD[17]~feeder_combout\); + +-- Location: FF_X21_Y9_N26 +\myVirtualToplevel|SD_ADDR[0][17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\, + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][17]~q\); + +-- Location: FF_X21_Y9_N13 +\myVirtualToplevel|IO_DATA_READ_SD[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|IO_DATA_READ_SD[17]~feeder_combout\, + asdata => \myVirtualToplevel|SD_ADDR[0][17]~q\, + sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|IO_DATA_READ_SD\(17)); + +-- Location: LABCELL_X21_Y14_N54 +\myVirtualToplevel|MEM_DATA_READ[17]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[17]~26_combout\ = ( \myVirtualToplevel|IO_DATA_READ_SD\(17) & ( \myVirtualToplevel|MEM_DATA_READ[17]~25_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~25_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(17), + combout => \myVirtualToplevel|MEM_DATA_READ[17]~26_combout\); + +-- Location: MLABCELL_X18_Y14_N45 +\myVirtualToplevel|MEM_DATA_READ[17]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[17]~27_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ & ( \myVirtualToplevel|MEM_DATA_READ[17]~24_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ & ( \myVirtualToplevel|MEM_DATA_READ[17]~24_combout\ ) ) # ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[17]~24_combout\ & ( ((\myVirtualToplevel|LessThan0~1_combout\ & ((!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0)) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9~portbdataout\)))) # (\myVirtualToplevel|MEM_DATA_READ[17]~26_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ & ( +-- !\myVirtualToplevel|MEM_DATA_READ[17]~24_combout\ & ( ((\myVirtualToplevel|LessThan0~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9~portbdataout\ & +-- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0)))) # (\myVirtualToplevel|MEM_DATA_READ[17]~26_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010111011101110101011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~26_combout\, + datab => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\, + datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0), + datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~24_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[17]~27_combout\); + +-- Location: LABCELL_X14_Y13_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector199~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~21_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~21_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~21_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000001011010101000001111111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~1_combout\); + +-- Location: LABCELL_X14_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector199~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector199~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector199~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100010000010100000101011111111011101110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[17]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector199~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~0_combout\); + +-- Location: LABCELL_X14_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[17]_NEW3333\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[17]_OTERM3334\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[17]~27_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # (\myVirtualToplevel|MEM_DATA_READ[17]~27_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector199~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\) # ((\myVirtualToplevel|MEM_DATA_READ[17]~27_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector199~0_combout\ & ( (\myVirtualToplevel|MEM_DATA_READ[17]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101111111110000010100000000111101011111111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~27_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector199~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[17]_OTERM3334\); + +-- Location: FF_X14_Y13_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[17]_OTERM3334\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(17)); + +-- Location: LABCELL_X17_Y14_N57 +\myVirtualToplevel|IO_SELECT_RESYN9117\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_SELECT_RESYN9117_BDD9118\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(18) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(21), + combout => \myVirtualToplevel|IO_SELECT_RESYN9117_BDD9118\); + +-- Location: FF_X16_Y15_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~0_combout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(14)); + +-- Location: LABCELL_X17_Y14_N12 +\myVirtualToplevel|IO_SELECT_RESYN9115\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_SELECT_RESYN9115_BDD9116\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[22]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(14)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[22]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(19), + combout => \myVirtualToplevel|IO_SELECT_RESYN9115_BDD9116\); + +-- Location: LABCELL_X17_Y14_N6 +\myVirtualToplevel|IO_SELECT\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|IO_SELECT~combout\ = ( \myVirtualToplevel|IO_SELECT_RESYN9117_BDD9118\ & ( \myVirtualToplevel|IO_SELECT_RESYN9115_BDD9116\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(17) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(12)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(12), + datae => \myVirtualToplevel|ALT_INV_IO_SELECT_RESYN9117_BDD9118\, + dataf => \myVirtualToplevel|ALT_INV_IO_SELECT_RESYN9115_BDD9116\, + combout => \myVirtualToplevel|IO_SELECT~combout\); + +-- Location: LABCELL_X17_Y13_N30 +\myVirtualToplevel|MEM_BUSY~1_RESYN12610\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_BUSY~1_RESYN12610_BDD12611\ = ( \myVirtualToplevel|Equal4~0_combout\ ) # ( !\myVirtualToplevel|Equal4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & +-- (\myVirtualToplevel|TIMER0_CS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000000000001000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9), + datac => \myVirtualToplevel|ALT_INV_TIMER0_CS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ALT_INV_Equal4~0_combout\, + combout => \myVirtualToplevel|MEM_BUSY~1_RESYN12610_BDD12611\); + +-- Location: FF_X18_Y13_N14 +\myVirtualToplevel|MEM_READ_ENABLE_LAST\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\, + sload => VCC, + ena => \ALT_INV_reset~combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|MEM_READ_ENABLE_LAST~q\); + +-- Location: MLABCELL_X18_Y13_N15 +\myVirtualToplevel|MEM_BUSY~1_RESYN12608\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_BUSY~1_RESYN12608_BDD12609\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\ & ( !\myVirtualToplevel|MEM_READ_ENABLE_LAST~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_MEM_READ_ENABLE_LAST~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\, + combout => \myVirtualToplevel|MEM_BUSY~1_RESYN12608_BDD12609\); + +-- Location: MLABCELL_X18_Y13_N24 +\myVirtualToplevel|MEM_BUSY~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_BUSY~1_combout\ = ( \myVirtualToplevel|SD_CS~combout\ & ( \myVirtualToplevel|UART0_CS~combout\ & ( \myVirtualToplevel|MEM_BUSY~1_RESYN12608_BDD12609\ ) ) ) # ( !\myVirtualToplevel|SD_CS~combout\ & ( +-- \myVirtualToplevel|UART0_CS~combout\ & ( \myVirtualToplevel|MEM_BUSY~1_RESYN12608_BDD12609\ ) ) ) # ( \myVirtualToplevel|SD_CS~combout\ & ( !\myVirtualToplevel|UART0_CS~combout\ & ( \myVirtualToplevel|MEM_BUSY~1_RESYN12608_BDD12609\ ) ) ) # ( +-- !\myVirtualToplevel|SD_CS~combout\ & ( !\myVirtualToplevel|UART0_CS~combout\ & ( (\myVirtualToplevel|MEM_BUSY~1_RESYN12608_BDD12609\ & (((\myVirtualToplevel|IO_SELECT~combout\ & \myVirtualToplevel|MEM_BUSY~1_RESYN12610_BDD12611\)) # +-- (\myVirtualToplevel|SOCCFG_CS~combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110111000000001111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\, + datab => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_RESYN12610_BDD12611\, + datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_RESYN12608_BDD12609\, + datae => \myVirtualToplevel|ALT_INV_SD_CS~combout\, + dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\, + combout => \myVirtualToplevel|MEM_BUSY~1_combout\); + +-- Location: LABCELL_X16_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS_2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~2_combout\); + +-- Location: MLABCELL_X13_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~2_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110011111100111111000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~3_combout\); + +-- Location: MLABCELL_X13_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & !\myVirtualToplevel|MEM_BUSY~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000100000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4_combout\); + +-- Location: FF_X10_Y32_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)); + +-- Location: LABCELL_X10_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add5~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add5~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add5~0_combout\); + +-- Location: FF_X10_Y32_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add5~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1)); + +-- Location: LABCELL_X10_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add5~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add5~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011001100111100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add5~1_combout\); + +-- Location: FF_X10_Y32_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add5~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\); + +-- Location: MLABCELL_X4_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(17)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\); + +-- Location: MLABCELL_X9_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~21_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~23_combout\); + +-- Location: LABCELL_X10_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~23_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~23_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(17) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1066~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[17]~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~24_combout\); + +-- Location: FF_X10_Y28_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(17)); + +-- Location: MLABCELL_X13_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010000010100110101000001010011010111110101001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~19_combout\); + +-- Location: MLABCELL_X13_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~19_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~19_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~19_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~19_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001000111111110011101100000000010011001111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1066~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[17]~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~20_combout\); + +-- Location: FF_X13_Y27_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(17)); + +-- Location: MLABCELL_X13_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000000001010101010101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~24_combout\); + +-- Location: MLABCELL_X13_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~24_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~24_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~24_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~24_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000111111011111110000000001000000111111110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1066~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[17]~24_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~25_combout\); + +-- Location: FF_X13_Y27_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(17)); + +-- Location: MLABCELL_X13_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110000010101010011000001010101001111110101010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~22_combout\); + +-- Location: MLABCELL_X13_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~22_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~22_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~22_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000000111101001111111100000111000000001111011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1066~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[17]~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~23_combout\); + +-- Location: FF_X13_Y27_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~23_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(17)); + +-- Location: LABCELL_X12_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(17)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(17)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(17)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(17) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~0_combout\); + +-- Location: LABCELL_X7_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000101110000011000010111000011101001111110001110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~26_combout\); + +-- Location: LABCELL_X7_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~26_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~26_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~26_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000000101111111011101100000100010001001011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1066~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[17]~26_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~27_combout\); + +-- Location: FF_X7_Y30_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~27_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(17)); + +-- Location: MLABCELL_X4_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100000011000001010101010101010011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~23_combout\); + +-- Location: MLABCELL_X4_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~23_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(17) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~23_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101101110111010111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1066~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[17]~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~24_combout\); + +-- Location: FF_X4_Y30_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(17)); + +-- Location: MLABCELL_X9_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~21_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~22_combout\); + +-- Location: MLABCELL_X9_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~22_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(17) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~22_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010011110111001101111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1066~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[17]~22_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~23_combout\); + +-- Location: FF_X9_Y29_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~23_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(17)); + +-- Location: MLABCELL_X13_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100000101000001010011010100110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~20_combout\); + +-- Location: MLABCELL_X13_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~20_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~20_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(17) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010000000100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1066~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[17]~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~21_combout\); + +-- Location: FF_X13_Y27_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~21_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(17)); + +-- Location: MLABCELL_X4_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(17)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(17) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(17)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(17)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(17) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(17) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000001100110000111101010101111111110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~1_combout\); + +-- Location: MLABCELL_X9_Y17_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\); + +-- Location: MLABCELL_X9_Y17_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ +-- $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001000000000000000000001001000000001001000000000000000000001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~0_combout\); + +-- Location: LABCELL_X6_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22)))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111111101010111000101010000000101011111010101010000010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~1_combout\); + +-- Location: MLABCELL_X9_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111111101110111000101010001000101010111010101010000000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~2_combout\); + +-- Location: MLABCELL_X9_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011010000111100001101000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~11_combout\); + +-- Location: LABCELL_X7_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000001000110011101100111010001100000010001110111111001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~9_combout\); + +-- Location: MLABCELL_X9_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~10_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000011001100000000001100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~10_combout\); + +-- Location: LABCELL_X10_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~3_combout\); + +-- Location: LABCELL_X10_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000100000000001000010000000000001000010000000000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~12_combout\); + +-- Location: LABCELL_X6_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000101010101111101010000000101010001110101011111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~7_combout\); + +-- Location: LABCELL_X6_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~8_combout\); + +-- Location: LABCELL_X7_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12582\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12582_BDD12583\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\))))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111001111110111000100000011000101110011011100110001000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12582_BDD12583\); + +-- Location: LABCELL_X10_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12586\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12586_BDD12587\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000010101111000010101010111100001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12586_BDD12587\); + +-- Location: LABCELL_X10_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12584\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12584_BDD12585\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101010101111000010101010111100001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12584_BDD12585\); + +-- Location: LABCELL_X10_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_BDD8628\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12584_BDD12585\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12586_BDD12587\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12582_BDD12583\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12584_BDD12585\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12586_BDD12587\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12582_BDD12583\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111001111110011111100111111111111110011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12582_BDD12583\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12586_BDD12587\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12584_BDD12585\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_BDD8628\); + +-- Location: MLABCELL_X13_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110011001111000011001100111100000000110011000000000011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~10_combout\); + +-- Location: MLABCELL_X13_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111100000101010111110000010100001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~7_combout\); + +-- Location: MLABCELL_X13_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000110000110000000011000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~8_combout\); + +-- Location: MLABCELL_X13_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~7_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001110000111101110001000011110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~9_combout\); + +-- Location: MLABCELL_X13_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8625\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8625_BDD8626\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~10_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~10_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~10_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111000101010000111101010101000011110101011100011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8625_BDD8626\); + +-- Location: LABCELL_X10_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_BDD8628\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8625_BDD8626\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~11_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~10_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_BDD8628\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8625_BDD8626\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~11_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~12_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_BDD8628\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8625_BDD8626\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~11_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_BDD8628\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8625_BDD8626\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001011101100000000101010110000000010111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_BDD8628\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8625_BDD8626\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\); + +-- Location: LABCELL_X10_Y17_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~1_combout\); + +-- Location: FF_X10_Y17_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_NEW_REG993\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM994\); + +-- Location: LABCELL_X7_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~1_combout\); + +-- Location: FF_X7_Y18_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_NEW_REG997\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM998\); + +-- Location: LABCELL_X10_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr128~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr128~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr128~0_combout\); + +-- Location: LABCELL_X10_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~0_combout\ = ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr128~0_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000001000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr128~0_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~0_combout\); + +-- Location: FF_X10_Y16_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_NEW_REG995\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM996\); + +-- Location: FF_X7_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_NEW_REG987\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM988\); + +-- Location: FF_X10_Y17_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_NEW_REG991\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM992\); + +-- Location: LABCELL_X7_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM988\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM992\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM990\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM996\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM998\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM988\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM992\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM990\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM996\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM998\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM988\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM992\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM990\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM994\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM996\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM998\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM988\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM992\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM990\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM998\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010100010100000101010101010000010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM990\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM994\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM998\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM996\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM988\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM992\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\); + +-- Location: LABCELL_X25_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\); + +-- Location: LABCELL_X26_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]_NEW3313\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]_OTERM3314\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add3~13_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~13_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]_OTERM3314\); + +-- Location: FF_X26_Y23_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]_OTERM3314\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20)); + +-- Location: LABCELL_X26_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(19) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(19) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(19)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(19)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111111101010111011101110101010100010101000000010001000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~3_combout\); + +-- Location: FF_X26_Y23_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]_OTERM3320\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(21)); + +-- Location: LABCELL_X25_Y23_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~0_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(21)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111110000000011111111000000001111111100000000111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~0_combout\); + +-- Location: LABCELL_X25_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011111110111001100110111001100010001001100010000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~2_combout\); + +-- Location: LABCELL_X24_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~3_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000010110010111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4_combout\); + +-- Location: LABCELL_X26_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000100000000010000000001001000000000100000000010000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~18_combout\); + +-- Location: LABCELL_X26_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~18_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~18_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100010000000000000000000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~10_combout\); + +-- Location: LABCELL_X26_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000001000010000000000010000100000000000100001000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~16_combout\); + +-- Location: LABCELL_X25_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_RESYN12620\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_RESYN12620_BDD12621\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000001010000010100000101000001001000001010000010100000101000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_RESYN12620_BDD12621\); + +-- Location: LABCELL_X25_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_RESYN12620_BDD12621\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010010000000010011001000000001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~13_RESYN12620_BDD12621\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_combout\); + +-- Location: LABCELL_X25_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000010100000111110101010000011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~14_combout\); + +-- Location: LABCELL_X25_Y24_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111100011111010111111101111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~14_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~15_combout\); + +-- Location: LABCELL_X31_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010000000111100001111100011000000111000001111110011111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~10_combout\); + +-- Location: LABCELL_X31_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001000000000000000010010000000000000000100100000000000000001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8_combout\); + +-- Location: LABCELL_X31_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~10_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~10_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000010100001111000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~11_combout\); + +-- Location: LABCELL_X25_Y22_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001111110011001100111111001100000000001100000000000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~7_combout\); + +-- Location: LABCELL_X25_Y22_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000001010000101000000101000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~6_combout\); + +-- Location: LABCELL_X24_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010001000001000100000100000000010100010000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~9_combout\); + +-- Location: LABCELL_X24_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~17_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~16_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~15_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~11_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~16_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~15_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~17_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~16_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~15_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~16_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~15_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100011001000100010001100110010001000110010001000100011001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~17_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~9_combout\); + +-- Location: LABCELL_X24_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000011000011110000001100001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~3_combout\); + +-- Location: LABCELL_X24_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~10_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010101000111111001010100010101000100010001100110010001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\); + +-- Location: LABCELL_X25_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\); + +-- Location: LABCELL_X25_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]_NEW2664\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]_OTERM2665\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~77_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~77_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~77_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]_OTERM2665\); + +-- Location: FF_X25_Y20_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]_OTERM2665\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17)); + +-- Location: FF_X24_Y23_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]_OTERM2653\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE_q\); + +-- Location: LABCELL_X32_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000000000001100110000000000000000110011000000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~10_combout\); + +-- Location: LABCELL_X26_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~9_combout\); + +-- Location: LABCELL_X31_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000110000110000000011000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~11_combout\); + +-- Location: LABCELL_X25_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100001000100100010000100010000100010000100010010001000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~8_combout\); + +-- Location: LABCELL_X31_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000001010101000000000101001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~7_combout\); + +-- Location: LABCELL_X31_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000010100000101000000001010000010100000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~0_combout\); + +-- Location: LABCELL_X31_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000000011000000110000110000001100000000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~1_combout\); + +-- Location: LABCELL_X31_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000000000000010000000000000000000000100000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~2_combout\); + +-- Location: LABCELL_X35_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000000000001111000000001111000000000000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~4_combout\); + +-- Location: LABCELL_X35_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000000011110000000000000000111100000000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~5_combout\); + +-- Location: LABCELL_X35_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101001010101000000000000000000000000000000001010101001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~3_combout\); + +-- Location: LABCELL_X35_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000010100101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~6_combout\); + +-- Location: LABCELL_X31_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000010000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\); + +-- Location: LABCELL_X12_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & !\myVirtualToplevel|MEM_BUSY~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~38_combout\); + +-- Location: LABCELL_X12_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~39_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # (\myVirtualToplevel|MEM_BUSY~1_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011011111000000001101111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~39_combout\); + +-- Location: LABCELL_X12_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~38_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~39_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~38_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~39_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~38_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~39_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110111011101111111011101110111111101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~38_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~39_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~40_combout\); + +-- Location: FF_X12_Y17_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~40_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\); + +-- Location: LABCELL_X14_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector203~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~37_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~37_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010100110000001001010011001010101111101110101010111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~37_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~1_combout\); + +-- Location: LABCELL_X14_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector203~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector203~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector203~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000111111110101111101010000001100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector203~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~0_combout\); + +-- Location: LABCELL_X14_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]_NEW3337\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]_OTERM3338\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # ((\myVirtualToplevel|MEM_DATA_READ[13]~143_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector203~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & +-- (\myVirtualToplevel|MEM_DATA_READ[13]~143_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~1_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~143_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector203~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]_OTERM3338\); + +-- Location: FF_X14_Y15_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]_OTERM3338\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13)); + +-- Location: MLABCELL_X18_Y7_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\); + +-- Location: FF_X17_Y5_N16 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(4)); + +-- Location: FF_X17_Y5_N10 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(5)); + +-- Location: MLABCELL_X18_Y6_N9 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(3) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(4) & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(4), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(3), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\); + +-- Location: FF_X17_Y6_N25 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(21), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y5_N3 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0_combout\ = (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100010001000100010001000100010001000100010001000100010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0_combout\); + +-- Location: FF_X17_Y9_N19 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[22]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1)); + +-- Location: LABCELL_X19_Y5_N45 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\)))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000000000001000000000000000100000000000000010100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~1_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][11]~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\); + +-- Location: FF_X20_Y5_N5 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][5]~q\); + +-- Location: LABCELL_X19_Y5_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ +-- & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101000001000000000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~1_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][11]~0_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\); + +-- Location: FF_X19_Y5_N49 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][5]~q\); + +-- Location: LABCELL_X19_Y5_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2_combout\ = (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010001000100010001000100010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2_combout\); + +-- Location: LABCELL_X19_Y5_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2_combout\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000001000000000000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][11]~2_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~1_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\); + +-- Location: FF_X18_Y5_N31 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][5]~q\); + +-- Location: LABCELL_X19_Y5_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\)))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000000000000000100000000000000010000000000000001010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~1_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][11]~2_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\); + +-- Location: FF_X20_Y5_N56 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][5]~q\); + +-- Location: LABCELL_X20_Y5_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux13~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux13~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][5]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][5]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][5]~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][5]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][5]~q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ +-- & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][5]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][5]~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][5]~q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][5]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][5]~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][5]~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][5]~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][5]~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux13~0_combout\); + +-- Location: FF_X17_Y5_N34 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(3)); + +-- Location: FF_X19_Y5_N40 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][3]~q\); + +-- Location: FF_X18_Y5_N16 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][3]~q\); + +-- Location: FF_X20_Y5_N50 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][3]~q\); + +-- Location: FF_X17_Y6_N26 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(21), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0)); + +-- Location: FF_X20_Y5_N8 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][3]~q\); + +-- Location: LABCELL_X20_Y5_N6 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux15~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux15~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][3]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][3]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][3]~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0)) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][3]~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][3]~q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0) & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][3]~q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][3]~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][3]~q\)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0) & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][3]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][3]~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][3]~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][3]~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(0), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][3]~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux15~0_combout\); + +-- Location: FF_X18_Y5_N13 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][4]~q\); + +-- Location: FF_X19_Y5_N11 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][4]~q\); + +-- Location: FF_X19_Y5_N26 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][4]~q\); + +-- Location: LABCELL_X20_Y5_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~feeder_combout\ = \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(4) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(4), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~feeder_combout\); + +-- Location: FF_X20_Y5_N1 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~q\); + +-- Location: LABCELL_X19_Y5_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux14~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux14~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][4]~q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][4]~q\))) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][4]~q\))) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][4]~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][4]~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][4]~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][4]~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux14~0_combout\); + +-- Location: LABCELL_X20_Y5_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(3) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux14~0_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(4) & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux15~0_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(5) $ (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux13~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(3) & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux14~0_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(4) & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux15~0_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(5) $ +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux13~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(3) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux14~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(4) & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux15~0_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(5) $ (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux13~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(3) & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux14~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(4) & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux15~0_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(5) $ +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux13~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000001000000000000000001000001001000001000000000000000001000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(4), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(5), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux13~0_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux15~0_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(3), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux14~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~1_combout\); + +-- Location: FF_X17_Y6_N58 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(18), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(9)); + +-- Location: FF_X19_Y5_N35 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(9), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][9]~q\); + +-- Location: FF_X20_Y5_N52 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(9), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][9]~q\); + +-- Location: FF_X19_Y5_N23 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(9), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][9]~q\); + +-- Location: FF_X18_Y5_N38 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(9), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][9]~q\); + +-- Location: MLABCELL_X18_Y5_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux9~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux9~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][9]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][9]~q\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][9]~q\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][9]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][9]~q\))) +-- # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][9]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][9]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][9]~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][9]~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][9]~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][9]~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][9]~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][9]~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][9]~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux9~0_combout\); + +-- Location: FF_X17_Y5_N43 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[19]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(10)); + +-- Location: LABCELL_X20_Y5_N3 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~feeder_combout\ = \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(10) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(10), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~feeder_combout\); + +-- Location: FF_X20_Y5_N4 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~q\); + +-- Location: FF_X19_Y5_N38 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(10), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][10]~q\); + +-- Location: MLABCELL_X18_Y5_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~feeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(10), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~feeder_combout\); + +-- Location: FF_X18_Y5_N22 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~q\); + +-- Location: FF_X19_Y5_N8 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(10), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][10]~q\); + +-- Location: LABCELL_X19_Y5_N6 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux8~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux8~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][10]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~q\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][10]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][10]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][10]~q\)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][10]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][10]~q\)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][10]~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][10]~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][10]~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][10]~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux8~0_combout\); + +-- Location: MLABCELL_X18_Y5_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~4_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux8~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(10) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(9) $ +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux9~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux8~0_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(10) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(9) $ +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux9~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001111000011000000000000000000000000000000001100001111000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(9), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux9~0_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux8~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(10), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~4_combout\); + +-- Location: LABCELL_X17_Y9_N39 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[6]~feeder_combout\); + +-- Location: FF_X17_Y9_N40 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[6]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(6)); + +-- Location: FF_X20_Y5_N2 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][6]~q\); + +-- Location: FF_X19_Y5_N16 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][6]~q\); + +-- Location: MLABCELL_X18_Y5_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~feeder_combout\ = \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(6) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(6), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~feeder_combout\); + +-- Location: FF_X18_Y5_N34 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~q\); + +-- Location: FF_X20_Y5_N26 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(6), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][6]~q\); + +-- Location: LABCELL_X20_Y5_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux12~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux12~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][6]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][6]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][6]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][6]~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0)) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][6]~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][6]~q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0) & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][6]~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][6]~q\)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0) & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][6]~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][6]~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][6]~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(0), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][6]~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux12~0_combout\); + +-- Location: FF_X17_Y9_N37 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(7)); + +-- Location: FF_X19_Y5_N14 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][7]~q\); + +-- Location: FF_X20_Y5_N34 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][7]~q\); + +-- Location: MLABCELL_X18_Y5_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~feeder_combout\ = \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(7) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(7), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~feeder_combout\); + +-- Location: FF_X18_Y5_N19 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~q\); + +-- Location: FF_X19_Y5_N56 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][7]~q\); + +-- Location: LABCELL_X19_Y5_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux11~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux11~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][7]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][7]~q\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][7]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][7]~q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][7]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][7]~q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ +-- & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][7]~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][7]~q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][7]~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][7]~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][7]~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][7]~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux11~0_combout\); + +-- Location: LABCELL_X19_Y5_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~3_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(7) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(6) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux12~0_combout\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux11~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(7) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(6) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux12~0_combout\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux11~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(7) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(6) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux12~0_combout\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux11~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(7) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(6) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux12~0_combout\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux11~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000000011000000110000110000001100000000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux12~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux11~0_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(7), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(6), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~3_combout\); + +-- Location: FF_X19_Y4_N22 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(0)); + +-- Location: FF_X18_Y5_N4 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][0]~q\); + +-- Location: FF_X20_Y5_N41 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][0]~q\); + +-- Location: FF_X20_Y4_N52 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][0]~q\); + +-- Location: FF_X20_Y5_N20 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][0]~q\); + +-- Location: LABCELL_X20_Y5_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux18~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux18~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][0]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][0]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][0]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][0]~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][0]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][0]~q\))) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][0]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][0]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][0]~q\))) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][0]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][0]~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][0]~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][0]~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][0]~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux18~0_combout\); + +-- Location: FF_X19_Y4_N29 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(1)); + +-- Location: FF_X20_Y5_N38 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][1]~q\); + +-- Location: MLABCELL_X18_Y5_N6 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~feeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~feeder_combout\); + +-- Location: FF_X18_Y5_N7 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~q\); + +-- Location: FF_X20_Y4_N58 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][1]~q\); + +-- Location: FF_X20_Y5_N14 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(1), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][1]~q\); + +-- Location: LABCELL_X20_Y5_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux17~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux17~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][1]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][1]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][1]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][1]~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][1]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][1]~q\))) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][1]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][1]~q\))) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][1]~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][1]~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][1]~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][1]~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux17~0_combout\); + +-- Location: LABCELL_X17_Y5_N39 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(11), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[2]~feeder_combout\); + +-- Location: FF_X17_Y5_N40 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[2]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(2)); + +-- Location: MLABCELL_X18_Y5_N9 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~feeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(2), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~feeder_combout\); + +-- Location: FF_X18_Y5_N11 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~q\); + +-- Location: FF_X19_Y5_N32 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][2]~q\); + +-- Location: FF_X20_Y5_N31 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][2]~q\); + +-- Location: FF_X19_Y5_N29 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][2]~q\); + +-- Location: LABCELL_X19_Y5_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux16~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux16~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][2]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][2]~q\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][2]~q\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][2]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][2]~q\))) +-- # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][2]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][2]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][2]~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111111110101010100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][2]~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][2]~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][2]~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][2]~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux16~0_combout\); + +-- Location: LABCELL_X20_Y5_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux16~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux17~0_combout\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(2) & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux18~0_combout\ $ (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux16~0_combout\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux17~0_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(2) & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux18~0_combout\ $ +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux16~0_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux17~0_combout\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(2) & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux18~0_combout\ $ (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux16~0_combout\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux17~0_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(2) & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux18~0_combout\ $ +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000010000000000000000001000010000100001000000000000000000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux18~0_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux17~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(0), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(2), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux16~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~0_combout\); + +-- Location: LABCELL_X17_Y6_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(20) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(20), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[11]~feeder_combout\); + +-- Location: FF_X17_Y6_N22 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[11]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(11)); + +-- Location: FF_X17_Y5_N4 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(17), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(8)); + +-- Location: FF_X19_Y5_N52 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(11), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~q\); + +-- Location: FF_X18_Y5_N52 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(11), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~q\); + +-- Location: LABCELL_X20_Y5_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~feeder_combout\ = \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(11) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(11), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~feeder_combout\); + +-- Location: FF_X20_Y5_N37 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~q\); + +-- Location: FF_X19_Y5_N59 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(11), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~q\); + +-- Location: LABCELL_X19_Y5_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux7~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux7~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~q\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~q\)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~q\)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][11]~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][11]~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][11]~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][11]~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux7~0_combout\); + +-- Location: LABCELL_X20_Y5_N39 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~feeder_combout\ = \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(8) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(8), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~feeder_combout\); + +-- Location: FF_X20_Y5_N40 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~q\); + +-- Location: FF_X19_Y5_N20 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][8]~q\); + +-- Location: FF_X19_Y5_N2 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][8]~q\); + +-- Location: FF_X18_Y5_N50 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][8]~q\); + +-- Location: MLABCELL_X18_Y5_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux10~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux10~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][8]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][8]~q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][8]~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~q\)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][8]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][8]~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][8]~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][8]~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][8]~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100111111111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][8]~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][8]~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][8]~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][8]~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux10~0_combout\); + +-- Location: MLABCELL_X18_Y5_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~2_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux7~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux10~0_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(11) & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux7~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux10~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(11) & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(8)) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux7~0_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux10~0_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(11) & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux7~0_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux10~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(11) & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(8)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000010100000101000000001010000010100000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(11), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(8), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux7~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux10~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~2_combout\); + +-- Location: LABCELL_X17_Y5_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~5_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~2_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~1_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~3_combout\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~0_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000010000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~1_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~3_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~0_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~4_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~2_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~5_combout\); + +-- Location: MLABCELL_X18_Y4_N6 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(1) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(1) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(1) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ & +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~5_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001011000000000000010100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~5_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~7_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~1_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\(1), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~0_combout\); + +-- Location: MLABCELL_X18_Y4_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & +-- (((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\)))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\)))) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011111100000000000000000000001100111111000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~1_combout\); + +-- Location: FF_X18_Y4_N8 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(1)); + +-- Location: MLABCELL_X18_Y4_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[0]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[0]~2_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(0) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ & +-- (((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~5_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110100001111000000100000001000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~1_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~7_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~5_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\(0), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[0]~2_combout\); + +-- Location: FF_X18_Y4_N37 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[0]~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(0)); + +-- Location: MLABCELL_X18_Y4_N45 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(0) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(1)) ) +-- ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(0) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(1) & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\(1), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2_combout\); + +-- Location: LABCELL_X17_Y5_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~3_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2_combout\ & +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~1_combout\) # ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~4_combout\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~3_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~0_combout\ & +-- ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~3_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~0_combout\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~3_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~1_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~4_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~2_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~2_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~3_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\); + +-- Location: LABCELL_X17_Y5_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~17_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~1_combout\) # +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111100001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~1_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~19_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~2_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~17_combout\); + +-- Location: LABCELL_X17_Y5_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~14_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16_combout\ & (((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~17_combout\))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~17_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010101010101000000000000000000000101010001010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~16_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~17_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~7_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~14_combout\); + +-- Location: FF_X18_Y6_N20 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~11_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(2)); + +-- Location: MLABCELL_X18_Y6_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\); + +-- Location: MLABCELL_X18_Y6_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~15_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(3) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\ & ( ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\) # +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(2)))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~14_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(3) & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(2))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~14_combout\) ) ) ) # +-- ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(3) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\ & ( ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~14_combout\)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(3) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~14_combout\ +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011111111110111011100110111001101111111111101110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~5_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~14_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(2), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(3), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add3~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~15_combout\); + +-- Location: FF_X18_Y6_N55 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~15_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\); + +-- Location: LABCELL_X21_Y8_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~2_combout\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuIsWriting~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~2_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~0_combout\); + +-- Location: FF_X21_Y8_N55 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\); + +-- Location: LABCELL_X20_Y8_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000001000000000000000000000010000000010000000010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuIsWriting~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2_combout\); + +-- Location: MLABCELL_X18_Y6_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\ & ( +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2_combout\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~1_combout\)))) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\ & ( +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010101111111100000000000000000000101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~2_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~1_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~2_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~0_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~19_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\); + +-- Location: MLABCELL_X18_Y4_N3 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~9_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(0))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(1)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\(0), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\(1), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~9_combout\); + +-- Location: LABCELL_X19_Y4_N3 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~10_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001100110100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~9_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~10_combout\); + +-- Location: MLABCELL_X18_Y6_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~11_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(2) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\) # +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~10_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(2) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\ & +-- ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~10_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(2) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\ & ( ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~10_combout\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(2) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\ +-- & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~10_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111101011111011101010101011101111111000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~5_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~10_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~3_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(2), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add3~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~11_combout\); + +-- Location: FF_X18_Y6_N19 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~11_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\); + +-- Location: LABCELL_X17_Y4_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~1_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~1_combout\); + +-- Location: LABCELL_X17_Y5_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~1_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2_combout\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~1_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~5_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~2_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~2_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\); + +-- Location: MLABCELL_X18_Y6_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(4) $ (((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(3))))) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(4) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101100101010101010110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(4), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(3), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~1_combout\); + +-- Location: MLABCELL_X18_Y6_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~13_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~1_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~1_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~1_combout\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010111010101010101011101110101010101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~12_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~3_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add3~1_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~2_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~13_combout\); + +-- Location: FF_X18_Y6_N49 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~13_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y4_N39 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000100000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\); + +-- Location: MLABCELL_X18_Y6_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\))) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000110000001100000011010000110100001101000011010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2_combout\); + +-- Location: MLABCELL_X18_Y6_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~4_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ ) +-- ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000100010110011001100110000000000001000101100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~7_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~2_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~0_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~3_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~4_combout\); + +-- Location: FF_X18_Y6_N13 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)); + +-- Location: MLABCELL_X18_Y4_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~6_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(0))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(1)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010110000000000101011000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\(0), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\(1), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~6_combout\); + +-- Location: LABCELL_X19_Y4_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~7_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001100000011010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~6_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~7_combout\); + +-- Location: FF_X18_Y4_N32 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~8_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(1)); + +-- Location: MLABCELL_X18_Y4_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~8_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(1) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)) # +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(1) & +-- ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~7_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)) ) +-- ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(1) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~7_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(1) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111111110000001101010111010101111111111110101011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~3_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~7_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(1), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~5_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~8_combout\); + +-- Location: FF_X18_Y4_N31 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~8_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\); + +-- Location: MLABCELL_X18_Y4_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\); + +-- Location: FF_X20_Y4_N2 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~45_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(0)); + +-- Location: LABCELL_X20_Y4_N3 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~41_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(1) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~46\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~42\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(1) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(1), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~46\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~41_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~42\); + +-- Location: FF_X20_Y4_N5 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~41_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(1)); + +-- Location: LABCELL_X20_Y4_N6 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~17_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~42\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~18\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(2), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~42\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~17_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~18\); + +-- Location: FF_X20_Y4_N7 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(2)); + +-- Location: LABCELL_X20_Y4_N9 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~13_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~18\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~14\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount[3]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~18\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~13_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~14\); + +-- Location: FF_X20_Y4_N11 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y4_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~9_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~14\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~10\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(4), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~14\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~9_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~10\); + +-- Location: FF_X20_Y4_N14 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(4)); + +-- Location: LABCELL_X20_Y4_N15 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~5_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~10\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~6\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(5), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~10\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~5_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~6\); + +-- Location: FF_X20_Y4_N17 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(5)); + +-- Location: LABCELL_X20_Y4_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~1_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~6\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~2\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(6), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~6\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~1_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~2\); + +-- Location: FF_X20_Y4_N20 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(6)); + +-- Location: LABCELL_X20_Y4_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~25_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~2\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~26\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(7), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~2\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~25_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~26\); + +-- Location: FF_X20_Y4_N23 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(7)); + +-- Location: LABCELL_X20_Y4_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~21_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~26\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~22\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(8), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~26\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~21_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~22\); + +-- Location: FF_X20_Y4_N25 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(8)); + +-- Location: LABCELL_X20_Y4_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~29_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~22\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~30\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~22\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~29_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~30\); + +-- Location: FF_X20_Y4_N28 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[9]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y4_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~37_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~30\ )) +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~38\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(10), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~30\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~37_sumout\, + cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~38\); + +-- Location: FF_X20_Y4_N32 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~37_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(10)); + +-- Location: FF_X20_Y4_N29 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(9)); + +-- Location: LABCELL_X20_Y4_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~33_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(11), + cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~38\, + sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~33_sumout\); + +-- Location: FF_X20_Y4_N35 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~33_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(11)); + +-- Location: LABCELL_X20_Y4_N39 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(11) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(10) & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(9)) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(10), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(9), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(11), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\); + +-- Location: LABCELL_X19_Y4_N45 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux93~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux93~0_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000011001000000000001100100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux93~0_combout\); + +-- Location: LABCELL_X19_Y4_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4_combout\); + +-- Location: LABCELL_X19_Y4_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux93~0_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux93~0_combout\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux93~0_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux93~0_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000001000000010000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~5_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux93~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~4_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~3_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~4_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~0_combout\); + +-- Location: LABCELL_X19_Y4_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~1_combout\ = (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~1_combout\); + +-- Location: LABCELL_X19_Y4_N6 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~2_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~1_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~q\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~1_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000010101000000000101010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuIsWriting~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~1_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~2_combout\); + +-- Location: LABCELL_X19_Y4_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~3_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~0_combout\) # +-- (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~q\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~0_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~0_combout\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~2_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\)) ) ) +-- ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~0_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101101110111111111100000000010101011011101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~0_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~2_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~3_combout\); + +-- Location: FF_X20_Y5_N46 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~q\); + +-- Location: FF_X20_Y8_N19 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDoneLast\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDoneLast~q\); + +-- Location: LABCELL_X20_Y8_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~2_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDoneLast~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDoneLast~q\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDoneLast~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~2_combout\); + +-- Location: MLABCELL_X23_Y14_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~5_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\ $ (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~2_combout\) ) +-- ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\ $ (((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) # +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101100110010101010110011001010101101010100101010110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~1_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~2_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~5_combout\); + +-- Location: MLABCELL_X23_Y14_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~6_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\ ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\ & ( !\myVirtualToplevel|RESET_n~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~3_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~6_combout\); + +-- Location: FF_X23_Y14_N44 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~5_combout\, + clrn => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~0_q\); + +-- Location: MLABCELL_X23_Y14_N45 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\ & ( \myVirtualToplevel|RESET_n~q\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\ & ( +-- (\myVirtualToplevel|RESET_n~q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\ $ (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~0_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001011010000000000101101000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~1_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~0_q\, + datad => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~3_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\); + +-- Location: LABCELL_X12_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & (!\myVirtualToplevel|MEM_BUSY~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~44_combout\); + +-- Location: FF_X12_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~46_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~q\); + +-- Location: LABCELL_X12_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # ((\myVirtualToplevel|MEM_BUSY~1_combout\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011011111111111111101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~45_combout\); + +-- Location: LABCELL_X12_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~44_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~45_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~44_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~45_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~44_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~45_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110111011101111111011101110111111101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~44_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~45_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~46_combout\); + +-- Location: FF_X12_Y17_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~46_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000010000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~0_combout\); + +-- Location: LABCELL_X17_Y17_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & +-- (!\myVirtualToplevel|MEM_BUSY~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000100000000000000000000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\); + +-- Location: FF_X17_Y18_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\); + +-- Location: LABCELL_X14_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\); + +-- Location: LABCELL_X25_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~110\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~110_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100000000000000110000000000001111110000000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~65_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~110_combout\); + +-- Location: LABCELL_X25_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~109\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~109_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~65_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~109_combout\); + +-- Location: LABCELL_X24_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~111\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~111_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add32~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add32~57_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010111001100110111011100110011011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~111_combout\); + +-- Location: LABCELL_X25_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~108\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~108_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~57_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~65_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~57_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~61_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~65_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~57_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~57_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~61_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~108_combout\); + +-- Location: LABCELL_X25_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~112\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~112_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~108_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|pc~111_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~109_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~110_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~108_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~111_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~109_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~110_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111011111111111011101111111111101111111111111110111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~110_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~109_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~111_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~108_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~112_combout\); + +-- Location: FF_X25_Y21_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~112_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)); + +-- Location: LABCELL_X26_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)) +-- # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(14) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(14) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(14) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000101110101010101010101010001000001111111110111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~17_combout\); + +-- Location: LABCELL_X25_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9139\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9139_BDD9140\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010111110111111101111111011111100000010000010110000101100001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9139_BDD9140\); + +-- Location: LABCELL_X25_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9141\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9141_BDD9142\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111000101110001111101010111000101010000010100000111000101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9141_BDD9142\); + +-- Location: LABCELL_X25_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9143\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9143_BDD9144\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000011001100110000000001010101000000010001000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9143_BDD9144\); + +-- Location: LABCELL_X25_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9139_BDD9140\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9143_BDD9144\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9141_BDD9142\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~10_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111100000000000000000011011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9139_BDD9140\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9141_BDD9142\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9143_BDD9144\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_combout\); + +-- Location: LABCELL_X25_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~17_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~16_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~15_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~10_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111010001010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\); + +-- Location: LABCELL_X21_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~63\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~63_combout\ = ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\))) ) ) ) # ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000000000000000000000000010000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~63_combout\); + +-- Location: MLABCELL_X23_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~62\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~62_combout\ = ( \myVirtualToplevel|MEM_BUSY~1_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch~q\ ) ) ) # ( +-- !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch~q\ ) ) ) # ( \myVirtualToplevel|MEM_BUSY~1_combout\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch~q\ ) ) ) # ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000001010101010101010101010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_MemoryFetch~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~62_combout\); + +-- Location: LABCELL_X17_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~64\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~64_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~63_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~62_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110110011000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~63_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~62_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~64_combout\); + +-- Location: FF_X17_Y17_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~64_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch~q\); + +-- Location: MLABCELL_X23_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector218~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector218~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101111111111111111100000101000001010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_MemoryFetch~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector218~0_combout\); + +-- Location: FF_X23_Y15_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector218~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\); + +-- Location: LABCELL_X35_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000011111111001100001111111100110000000000000011000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr195~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\); + +-- Location: LABCELL_X35_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(2) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(2), + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~86\); + +-- Location: LABCELL_X35_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~82\); + +-- Location: LABCELL_X35_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(3))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000010010101110000001001010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr195~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~4_combout\); + +-- Location: FF_X35_Y21_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(3)); + +-- Location: LABCELL_X35_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~50\); + +-- Location: LABCELL_X35_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1694~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1694~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~49_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~49_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101010000000011111111101010101111111110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~49_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1694~0_combout\); + +-- Location: FF_X35_Y21_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1694~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4)); + +-- Location: LABCELL_X35_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~54\); + +-- Location: LABCELL_X35_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~70\); + +-- Location: LABCELL_X35_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~50\); + +-- Location: LABCELL_X35_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~54\); + +-- Location: LABCELL_X35_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~70\); + +-- Location: MLABCELL_X34_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1692~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1692~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~69_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~69_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~69_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~69_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~69_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~69_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1692~0_combout\); + +-- Location: FF_X34_Y19_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1692~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\); + +-- Location: LABCELL_X35_Y21_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~74\); + +-- Location: LABCELL_X35_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~74\); + +-- Location: MLABCELL_X34_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1691~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1691~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~73_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~73_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~73_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~73_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~73_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~73_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~73_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1691~0_combout\); + +-- Location: FF_X34_Y21_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1691~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7)); + +-- Location: LABCELL_X35_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~78\); + +-- Location: FF_X35_Y21_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1690~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(8)); + +-- Location: LABCELL_X35_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~78\); + +-- Location: LABCELL_X35_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1690~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1690~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add56~77_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~77_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add56~77_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~77_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~77_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1690~0_combout\); + +-- Location: FF_X35_Y21_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1690~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\); + +-- Location: LABCELL_X35_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~58\); + +-- Location: LABCELL_X35_Y21_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add44~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~58\); + +-- Location: LABCELL_X35_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1689~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1689~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add56~57_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~57_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add56~57_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~57_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~57_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1689~0_combout\); + +-- Location: FF_X35_Y21_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1689~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9)); + +-- Location: LABCELL_X35_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~62\); + +-- Location: MLABCELL_X34_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1688~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1688~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~61_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~61_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~61_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~61_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~61_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~61_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1688~0_combout\); + +-- Location: FF_X34_Y19_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1688~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10)); + +-- Location: LABCELL_X35_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add56~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~66\); + +-- Location: MLABCELL_X34_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1686~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1686~0_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add44~33_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add56~33_sumout\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1686~0_combout\); + +-- Location: FF_X34_Y19_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1686~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\); + +-- Location: LABCELL_X35_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal148~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[18]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~0_combout\); + +-- Location: LABCELL_X35_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal148~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(17) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(23))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[22]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~1_combout\); + +-- Location: MLABCELL_X34_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal149~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000010000000100000001000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[14]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~0_combout\); + +-- Location: MLABCELL_X34_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal149~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000100000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~1_combout\); + +-- Location: MLABCELL_X34_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal149~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal148~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal148~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~2_combout\); + +-- Location: LABCELL_X31_Y19_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal153~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal153~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal149~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal149~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000000000010000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal153~0_combout\); + +-- Location: LABCELL_X36_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal153~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal153~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_2~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001001111011111000100111101111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_0~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal153~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~45_combout\); + +-- Location: FF_X36_Y24_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~45_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\); + +-- Location: LABCELL_X36_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_2~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~50_combout\); + +-- Location: FF_X36_Y32_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~50_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_2~q\); + +-- Location: LABCELL_X36_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal153~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_2~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal153~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~41_combout\); + +-- Location: LABCELL_X36_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~41_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~41_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugAllInfo~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~42_combout\); + +-- Location: FF_X36_Y24_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~42_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\); + +-- Location: FF_X36_Y24_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~38_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~q\); + +-- Location: LABCELL_X36_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~38_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~38_combout\); + +-- Location: FF_X36_Y24_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~38_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~DUPLICATE_q\); + +-- Location: FF_X36_Y24_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~43_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\); + +-- Location: LABCELL_X36_Y24_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111010101110101011101010111010111110101111101011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\); + +-- Location: FF_X35_Y21_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1687~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(11)); + +-- Location: LABCELL_X35_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1687~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1687~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~65_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~65_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add44~65_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~65_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~65_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1687~0_combout\); + +-- Location: FF_X35_Y21_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1687~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal149~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~3_combout\); + +-- Location: LABCELL_X31_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal149~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal149~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010000000000000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~4_combout\); + +-- Location: LABCELL_X36_Y24_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal149~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_2~q\)) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal149~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_2~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010111100101111001000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~43_combout\); + +-- Location: FF_X36_Y24_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~43_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\); + +-- Location: LABCELL_X35_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1693~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1693~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add56~53_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~53_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add56~53_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~53_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~53_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1693~0_combout\); + +-- Location: FF_X35_Y21_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1693~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5)); + +-- Location: FF_X34_Y19_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1686~0_combout\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(12)); + +-- Location: MLABCELL_X34_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16))) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000101000000000000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_EndAddr\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~0_combout\); + +-- Location: MLABCELL_X34_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5) & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(11) $ (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001000000000100000100000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_EndAddr\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\); + +-- Location: LABCELL_X32_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~53_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~53_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~53_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~53_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010111111111100111000000000110011101111111111001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~53_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_0~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~44_combout\); + +-- Location: FF_X32_Y19_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~44_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\); + +-- Location: LABCELL_X35_Y24_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1_RTM0883\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1_RTM0883~combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1_RTM0883~combout\); + +-- Location: FF_X35_Y24_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_NEW_REG881\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1_RTM0883~combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM882\); + +-- Location: LABCELL_X31_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~1_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~1_combout\); + +-- Location: LABCELL_X31_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~0_combout\); + +-- Location: FF_X31_Y22_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~q\); + +-- Location: LABCELL_X31_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101000101010101010100010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugOutputOnce~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\); + +-- Location: LABCELL_X31_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~160\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101000000000101010100000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\); + +-- Location: LABCELL_X24_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~161\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000000000101010100010001010101010000000001010101000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~160_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\); + +-- Location: MLABCELL_X28_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000101000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\); + +-- Location: MLABCELL_X28_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001100011100000001101100100010000010110010000100101000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~0_combout\); + +-- Location: MLABCELL_X28_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111111111111110111111111111100001111111111111100111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~25_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\); + +-- Location: LABCELL_X31_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\); + +-- Location: MLABCELL_X28_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\); + +-- Location: LABCELL_X25_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux254~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000000000001111110000000000001100111111110011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~0_combout\); + +-- Location: MLABCELL_X28_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux254~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux254~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux254~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000000101000101001010111110111110101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux254~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~2_combout\); + +-- Location: MLABCELL_X28_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000000000001111110011001100001100110011000011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~1_combout\); + +-- Location: MLABCELL_X28_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000000101000101001010111110111110101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~3_combout\); + +-- Location: MLABCELL_X28_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux254~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux254~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux254~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000000010001000000000000000100000100110000010000010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~89_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux254~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\); + +-- Location: LABCELL_X25_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12538\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12538_BDD12539\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111111110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12538_BDD12539\); + +-- Location: MLABCELL_X28_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12536\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12536_BDD12537\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux254~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux254~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12536_BDD12537\); + +-- Location: MLABCELL_X28_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12536_BDD12537\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12538_BDD12539\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12538_BDD12539\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12536_BDD12537\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12538_BDD12539\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12536_BDD12537\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12538_BDD12539\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12536_BDD12537\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12538_BDD12539\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001011111000000000101110010100000111111111010000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_RESYN12538_BDD12539\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_RESYN12536_BDD12537\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\); + +-- Location: LABCELL_X29_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001110011000000000111011100000000011101110000000001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\); + +-- Location: LABCELL_X35_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111111001111110011001100111111001111110011111100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~0_combout\); + +-- Location: LABCELL_X35_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878~feeder_combout\); + +-- Location: FF_X35_Y24_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_NEW_REG877\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878\); + +-- Location: LABCELL_X35_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876~feeder_combout\); + +-- Location: FF_X35_Y24_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_NEW_REG875\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876\); + +-- Location: LABCELL_X35_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100000000000000000011001100110011000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\); + +-- Location: LABCELL_X35_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\); + +-- Location: LABCELL_X35_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880~feeder_combout\); + +-- Location: FF_X35_Y24_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_NEW_REG879\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880\); + +-- Location: LABCELL_X35_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1659~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1659~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM882\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM882\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101111111111111111101010000010100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM882\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM878\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM876\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM880\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1659~0_combout\); + +-- Location: MLABCELL_X42_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(2) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(2) $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1659~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111110000000011111111000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1659~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal1~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~2_combout\); + +-- Location: FF_X42_Y18_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(2)); + +-- Location: FF_X41_Y9_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\); + +-- Location: FF_X41_Y9_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y9_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001000000000000000000001001000000001001000000000000000000001001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~1_combout\); + +-- Location: LABCELL_X39_Y8_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(0) ) + ( VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(0), + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~22\); + +-- Location: LABCELL_X40_Y8_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~4_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\); + +-- Location: FF_X39_Y8_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(0)); + +-- Location: LABCELL_X39_Y8_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(1), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~26\); + +-- Location: FF_X39_Y8_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(1)); + +-- Location: LABCELL_X39_Y8_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~13_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~14\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(2), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~14\); + +-- Location: LABCELL_X40_Y8_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~13_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~4_combout\); + +-- Location: FF_X40_Y8_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(2)); + +-- Location: LABCELL_X39_Y8_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~30\); + +-- Location: FF_X39_Y8_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(3)); + +-- Location: LABCELL_X39_Y8_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~50\); + +-- Location: FF_X39_Y8_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~49_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(4)); + +-- Location: LABCELL_X39_Y8_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~10\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~10\); + +-- Location: LABCELL_X40_Y8_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~9_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~3_combout\); + +-- Location: FF_X40_Y8_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(5)); + +-- Location: LABCELL_X39_Y8_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~6\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(6), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~6\); + +-- Location: LABCELL_X40_Y8_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~5_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~2_combout\); + +-- Location: FF_X40_Y8_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(6)); + +-- Location: LABCELL_X39_Y8_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~54\); + +-- Location: FF_X39_Y8_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~53_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(7)); + +-- Location: LABCELL_X39_Y8_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~2\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~2\); + +-- Location: LABCELL_X40_Y8_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~1_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~1_combout\); + +-- Location: FF_X40_Y8_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(8)); + +-- Location: LABCELL_X39_Y8_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~18\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~18\); + +-- Location: LABCELL_X39_Y8_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~17_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~17_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~5_combout\); + +-- Location: FF_X39_Y8_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(9)); + +-- Location: LABCELL_X39_Y8_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~58\); + +-- Location: FF_X39_Y8_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~57_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(10)); + +-- Location: LABCELL_X39_Y8_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~62\); + +-- Location: FF_X39_Y8_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~61_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(11)); + +-- Location: LABCELL_X39_Y8_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(11) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(7))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~3_combout\); + +-- Location: LABCELL_X39_Y8_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(12), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~34\); + +-- Location: FF_X39_Y8_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~33_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(12)); + +-- Location: LABCELL_X39_Y8_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~38\); + +-- Location: FF_X39_Y8_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~37_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(13)); + +-- Location: LABCELL_X39_Y8_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(14) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(14) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(14), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~42\); + +-- Location: FF_X39_Y8_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~41_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(14)); + +-- Location: LABCELL_X39_Y8_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(15) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(15), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~45_sumout\); + +-- Location: FF_X39_Y8_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~45_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(15)); + +-- Location: LABCELL_X39_Y8_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(13) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(12) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(15))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~2_combout\); + +-- Location: LABCELL_X39_Y8_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(3) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000000000000001100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~1_combout\); + +-- Location: LABCELL_X40_Y8_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(8) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(6) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~0_combout\); + +-- Location: LABCELL_X40_Y8_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~4_combout\); + +-- Location: LABCELL_X40_Y8_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~0_combout\); + +-- Location: FF_X40_Y8_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~q\); + +-- Location: LABCELL_X41_Y8_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[16]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[16]~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[16]~9_combout\); + +-- Location: FF_X40_Y8_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~DUPLICATE_q\); + +-- Location: FF_X40_Y8_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\); + +-- Location: LABCELL_X40_Y8_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\ & ( (\myVirtualToplevel|RESET_n~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\ & ( \myVirtualToplevel|RESET_n~q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\ & ( (\myVirtualToplevel|RESET_n~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000111100001111000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_CLOCK~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_DATA_LOADED~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\); + +-- Location: FF_X41_Y8_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[16]~9_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(16)); + +-- Location: LABCELL_X41_Y8_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(16) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~8_combout\); + +-- Location: FF_X41_Y8_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~8_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(15)); + +-- Location: LABCELL_X41_Y8_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(15) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~7_combout\); + +-- Location: FF_X41_Y8_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~7_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(14)); + +-- Location: LABCELL_X41_Y8_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(14) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~6_combout\); + +-- Location: FF_X41_Y8_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~6_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(13)); + +-- Location: LABCELL_X41_Y8_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(13) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~5_combout\); + +-- Location: FF_X41_Y8_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~5_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(12)); + +-- Location: LABCELL_X41_Y8_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(12) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~4_combout\); + +-- Location: FF_X41_Y8_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~4_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(11)); + +-- Location: LABCELL_X41_Y8_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(11) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~3_combout\); + +-- Location: FF_X41_Y8_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~3_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(10)); + +-- Location: LABCELL_X41_Y8_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(10) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~2_combout\); + +-- Location: FF_X41_Y8_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(9)); + +-- Location: LABCELL_X41_Y8_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(9) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~1_combout\); + +-- Location: FF_X41_Y8_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~1_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(8)); + +-- Location: LABCELL_X40_Y8_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(8) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_CLOCK~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~0_combout\); + +-- Location: FF_X40_Y8_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~0_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\); + +-- Location: LABCELL_X40_Y8_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011111111111100001111000011110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_2~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_DATA_LOADED~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~0_combout\); + +-- Location: FF_X40_Y8_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y9_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(1), + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~2\); + +-- Location: FF_X41_Y9_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1)); + +-- Location: FF_X41_Y9_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y9_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0) ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0) ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(1), + cin => GND, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~2\); + +-- Location: FF_X43_Y9_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~1_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1)); + +-- Location: MLABCELL_X42_Y9_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000010000000000001000010000000000000000100001000000000000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~0_combout\); + +-- Location: LABCELL_X43_Y9_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~34\); + +-- Location: LABCELL_X43_Y9_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~22\); + +-- Location: FF_X43_Y9_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y9_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~38\); + +-- Location: FF_X43_Y9_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~37_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y9_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~42\); + +-- Location: FF_X43_Y9_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~41_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10)); + +-- Location: MLABCELL_X42_Y9_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~4_combout\); + +-- Location: LABCELL_X43_Y9_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000001010000101000000101000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~3_combout\); + +-- Location: FF_X41_Y9_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y9_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~25_sumout\); + +-- Location: FF_X43_Y9_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11)); + +-- Location: LABCELL_X43_Y9_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000001010000101000000101000000001010000001010000101000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~2_combout\); + +-- Location: LABCELL_X43_Y9_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~4_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011001100110011001100110011001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_DATA_LOADED~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\); + +-- Location: LABCELL_X43_Y9_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[0]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_2~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[0]~0_combout\); + +-- Location: FF_X43_Y9_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[0]~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0)); + +-- Location: LABCELL_X43_Y9_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~6\); + +-- Location: FF_X43_Y9_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2)); + +-- Location: LABCELL_X43_Y9_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~10\); + +-- Location: FF_X43_Y9_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3)); + +-- Location: LABCELL_X43_Y9_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~14\); + +-- Location: FF_X43_Y9_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4)); + +-- Location: LABCELL_X43_Y9_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~18\); + +-- Location: FF_X43_Y9_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5)); + +-- Location: LABCELL_X43_Y9_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~30\); + +-- Location: FF_X43_Y9_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\); + +-- Location: FF_X43_Y9_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~33_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7)); + +-- Location: LABCELL_X40_Y9_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(0), + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~30\); + +-- Location: LABCELL_X40_Y9_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(1), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~34\); + +-- Location: LABCELL_X40_Y9_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~22\); + +-- Location: LABCELL_X40_Y9_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~26\); + +-- Location: LABCELL_X40_Y9_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~38\); + +-- Location: LABCELL_X40_Y9_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~42\); + +-- Location: LABCELL_X40_Y9_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~14\); + +-- Location: LABCELL_X40_Y9_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~18\); + +-- Location: LABCELL_X40_Y9_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~17_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~13_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~17_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000001010101000000000101001010000000001010101000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~17_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~2_combout\); + +-- Location: LABCELL_X40_Y9_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~46\); + +-- Location: LABCELL_X41_Y9_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~45_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(8) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~37_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(5) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~41_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~45_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(8) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~37_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(5) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~41_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~45_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(8) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~37_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(5) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~41_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~45_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(8) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~37_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(5) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~41_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000100000000010000000001001000000000100000000010000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~37_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~41_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~45_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~5_combout\); + +-- Location: LABCELL_X40_Y9_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~6\); + +-- Location: LABCELL_X40_Y9_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~10\); + +-- Location: LABCELL_X40_Y9_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~1_sumout\); + +-- Location: LABCELL_X40_Y9_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111111110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~0_combout\); + +-- Location: LABCELL_X41_Y9_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~5_sumout\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~9_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~5_sumout\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~1_combout\); + +-- Location: MLABCELL_X34_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\); + +-- Location: LABCELL_X35_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\); + +-- Location: MLABCELL_X28_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux255~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000010001000100011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux254~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\); + +-- Location: MLABCELL_X28_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~162\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101000100010101010101010001000100010001000100010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\); + +-- Location: LABCELL_X31_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001100100011001000100010001100100011001000110010001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\); + +-- Location: MLABCELL_X37_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS_NEW2180\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS_OTERM2181\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_TOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS_OTERM2181\); + +-- Location: FF_X37_Y25_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS_OTERM2181\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\); + +-- Location: LABCELL_X41_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1659~0_combout\ & ( \myVirtualToplevel|RESET_n~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal1~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1659~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\); + +-- Location: MLABCELL_X42_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000110000000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\); + +-- Location: FF_X48_Y10_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_TOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_TOS~q\); + +-- Location: FF_X42_Y18_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)); + +-- Location: FF_X42_Y18_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\); + +-- Location: LABCELL_X40_Y14_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(0))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000000000110000000000000011000000000000001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0_combout\); + +-- Location: LABCELL_X40_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Decoder0~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\); + +-- Location: FF_X49_Y14_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_TOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_TOS~q\); + +-- Location: MLABCELL_X42_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000010000000100000001000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\); + +-- Location: FF_X48_Y10_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_TOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_TOS~q\); + +-- Location: FF_X42_Y18_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)); + +-- Location: LABCELL_X48_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_TOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~feeder_combout\); + +-- Location: MLABCELL_X42_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100000001000000010000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\); + +-- Location: FF_X48_Y17_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~q\); + +-- Location: MLABCELL_X49_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_TOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~feeder_combout\); + +-- Location: MLABCELL_X42_Y18_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000000010000000100000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\); + +-- Location: FF_X49_Y17_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~q\); + +-- Location: MLABCELL_X42_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010000000100000001000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\); + +-- Location: FF_X48_Y17_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_TOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_TOS~q\); + +-- Location: LABCELL_X48_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_TOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~feeder_combout\); + +-- Location: MLABCELL_X42_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(2) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\); + +-- Location: FF_X48_Y17_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~q\); + +-- Location: LABCELL_X48_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_TOS~q\)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000101000001010000010100000101001110111011101110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_STACK_TOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_STACK_TOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_STACK_TOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_STACK_TOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4_combout\); + +-- Location: MLABCELL_X42_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001100000000000000110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\); + +-- Location: FF_X48_Y10_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_TOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_TOS~q\); + +-- Location: LABCELL_X48_Y10_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_TOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_TOS~q\)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_TOS~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_TOS~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001100000011000000110000001111001100111111111101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_STACK_TOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_STACK_TOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_STACK_TOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux28~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_STACK_TOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~0_combout\); + +-- Location: FF_X36_Y11_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~16_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~q\); + +-- Location: LABCELL_X32_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\); + +-- Location: LABCELL_X32_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~1_combout\); + +-- Location: MLABCELL_X34_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\); + +-- Location: MLABCELL_X34_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal148~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~3_combout\); + +-- Location: MLABCELL_X34_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal148~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(12) & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000000000001000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[14]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~4_combout\); + +-- Location: MLABCELL_X34_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal148~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~2_combout\); + +-- Location: MLABCELL_X34_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Equal148~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal148~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal148~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100000000000000010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~5_combout\); + +-- Location: LABCELL_X32_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1701~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1701~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(2)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(2))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000001010111100000000101011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1701~0_combout\); + +-- Location: FF_X32_Y19_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1701~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(2)); + +-- Location: LABCELL_X32_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1700~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1700~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(2))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(2))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000001000101110111011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1700~0_combout\); + +-- Location: FF_X32_Y19_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1700~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(3)); + +-- Location: LABCELL_X32_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~0_combout\); + +-- Location: LABCELL_X32_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1699~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1699~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000010100001111111110100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1699~0_combout\); + +-- Location: FF_X32_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1699~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(4)); + +-- Location: FF_X32_Y19_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1700~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[3]~DUPLICATE_q\); + +-- Location: LABCELL_X32_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(4)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000101000001010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~0_combout\); + +-- Location: LABCELL_X32_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Equal148~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~1_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000111110001010100011111000101011011111110110101101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~2_combout\); + +-- Location: LABCELL_X32_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC_NEW2182\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC_OTERM2183\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~2_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC_OTERM2183\); + +-- Location: FF_X32_Y19_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC_OTERM2183\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\); + +-- Location: FF_X45_Y16_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_PC\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_PC~q\); + +-- Location: MLABCELL_X45_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~feeder_combout\); + +-- Location: FF_X45_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~q\); + +-- Location: MLABCELL_X45_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~feeder_combout\); + +-- Location: FF_X45_Y16_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~q\); + +-- Location: FF_X47_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_PC\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_PC~q\); + +-- Location: FF_X47_Y16_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_PC\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_PC~q\); + +-- Location: FF_X43_Y13_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_PC\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_PC~q\); + +-- Location: FF_X47_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_PC\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_PC~q\); + +-- Location: LABCELL_X47_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_PC~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_PC~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_PC~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_PC~q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000111100000000000011110000000000110011111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_PC~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_PC~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_PC~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_PC~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4_combout\); + +-- Location: MLABCELL_X45_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~feeder_combout\); + +-- Location: FF_X45_Y17_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~q\); + +-- Location: MLABCELL_X45_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~q\)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_PC~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001100000011000000110000001111001100111111111101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_PC~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_PC~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_PC~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux26~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_PC~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~0_combout\); + +-- Location: MLABCELL_X42_Y11_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101111101011111010100000101000001011100010011000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux26~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~14_combout\); + +-- Location: FF_X42_Y11_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~14_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\); + +-- Location: MLABCELL_X37_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP_NEW2184\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP_OTERM2185\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_SP~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP_OTERM2185\); + +-- Location: FF_X37_Y25_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP_OTERM2185\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\); + +-- Location: LABCELL_X47_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_SP~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~feeder_combout\); + +-- Location: FF_X47_Y17_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~q\); + +-- Location: FF_X47_Y17_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_SP\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_SP~q\); + +-- Location: LABCELL_X47_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_SP~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~feeder_combout\); + +-- Location: FF_X47_Y17_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~q\); + +-- Location: FF_X48_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_SP\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_SP~q\); + +-- Location: FF_X49_Y18_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_SP\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_SP~q\); + +-- Location: LABCELL_X48_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_SP~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~feeder_combout\); + +-- Location: FF_X48_Y17_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~q\); + +-- Location: LABCELL_X48_Y17_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_SP~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~feeder_combout\); + +-- Location: FF_X48_Y17_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~q\); + +-- Location: LABCELL_X48_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~q\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_SP~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_SP~q\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000101000001010000010100000101001010101111111110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_SP~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_SP~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_SP~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_SP~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4_combout\); + +-- Location: LABCELL_X47_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_SP~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~feeder_combout\); + +-- Location: FF_X47_Y19_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~q\); + +-- Location: LABCELL_X47_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~q\))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_SP~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000001111000000000000111111111111010101011111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_SP~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_SP~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_SP~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux27~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_SP~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~0_combout\); + +-- Location: LABCELL_X36_Y11_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111110110000000000000000111111111111101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_SP~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux27~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~13_combout\); + +-- Location: FF_X36_Y11_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~13_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\); + +-- Location: LABCELL_X36_Y11_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000100010000000000010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_SP~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~15_combout\); + +-- Location: LABCELL_X36_Y11_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~15_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100000101000000000000010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux28~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~16_combout\); + +-- Location: FF_X36_Y11_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~16_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\); + +-- Location: LABCELL_X36_Y11_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000000000110011000000000011001100000000001100110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_SP~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\); + +-- Location: MLABCELL_X37_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS_NEW2178\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS_OTERM2179\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_NOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS_OTERM2179\); + +-- Location: FF_X37_Y25_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS_OTERM2179\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\); + +-- Location: MLABCELL_X45_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_NOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~feeder_combout\); + +-- Location: FF_X45_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~q\); + +-- Location: MLABCELL_X45_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_NOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~feeder_combout\); + +-- Location: FF_X45_Y16_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~q\); + +-- Location: FF_X45_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_NOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_NOS~q\); + +-- Location: FF_X50_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_NOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_NOS~q\); + +-- Location: FF_X49_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_NOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_NOS~q\); + +-- Location: FF_X50_Y16_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_NOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_NOS~q\); + +-- Location: MLABCELL_X49_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_NOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~feeder_combout\); + +-- Location: FF_X49_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~q\); + +-- Location: MLABCELL_X49_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_NOS~q\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_NOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_NOS~q\)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001100100011001000110010011101100111011001110110001100100111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_STACK_NOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_STACK_NOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_STACK_NOS~q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_STACK_NOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4_combout\); + +-- Location: MLABCELL_X49_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_NOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~feeder_combout\); + +-- Location: FF_X49_Y16_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~q\); + +-- Location: MLABCELL_X45_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~q\))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_NOS~q\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001100000011000000110000001111011101110111011100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_STACK_NOS~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_STACK_NOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_STACK_NOS~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux29~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_STACK_NOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~0_combout\); + +-- Location: LABCELL_X36_Y11_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100000101001000110000010100100011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux29~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~17_combout\); + +-- Location: FF_X36_Y11_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~17_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\); + +-- Location: LABCELL_X36_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~0_combout\); + +-- Location: MLABCELL_X37_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1377~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1377~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1377~0_combout\); + +-- Location: MLABCELL_X37_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE_NEW2188\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE_OTERM2189\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1377~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1377~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_OPCODE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE_OTERM2189\); + +-- Location: FF_X37_Y25_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE_OTERM2189\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\); + +-- Location: FF_X49_Y14_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_OPCODE~q\); + +-- Location: MLABCELL_X49_Y14_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~feeder_combout\); + +-- Location: FF_X49_Y14_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~q\); + +-- Location: FF_X49_Y14_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_OPCODE~q\); + +-- Location: LABCELL_X48_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~feeder_combout\); + +-- Location: FF_X48_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~q\); + +-- Location: MLABCELL_X49_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~feeder_combout\); + +-- Location: FF_X49_Y17_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~q\); + +-- Location: FF_X48_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_OPCODE~q\); + +-- Location: LABCELL_X48_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~feeder_combout\); + +-- Location: FF_X48_Y17_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~q\); + +-- Location: LABCELL_X48_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_OPCODE~q\)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000101001110111000010100101010100001010011101110000101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_OPCODE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_OPCODE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_OPCODE~q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4_combout\); + +-- Location: LABCELL_X48_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~feeder_combout\); + +-- Location: FF_X48_Y18_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~q\); + +-- Location: MLABCELL_X49_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_OPCODE~q\)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_OPCODE~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000010100000101000001010000010110101010111111111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_OPCODE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_OPCODE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_OPCODE~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux24~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~0_combout\); + +-- Location: MLABCELL_X42_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101101011111010111100000101000001011000110010001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux24~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~11_combout\); + +-- Location: FF_X42_Y11_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~11_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\); + +-- Location: LABCELL_X39_Y10_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110011111100001111001111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DECODED_OPCODE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~0_combout\); + +-- Location: MLABCELL_X42_Y9_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~46_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0)) ) + ( !VCC ) + ( !VCC )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~47\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111101011111010100000000000000000101101001011010", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(0), + cin => GND, + sharein => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~46_cout\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~47\); + +-- Location: MLABCELL_X42_Y9_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~42_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1)) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~46_cout\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~43\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(1), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~46_cout\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~47\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~42_cout\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~43\); + +-- Location: MLABCELL_X42_Y9_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~38_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2)) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~42_cout\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~39\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(2), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~42_cout\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~43\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~38_cout\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~39\); + +-- Location: MLABCELL_X42_Y9_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~34_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3)) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~39\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~38_cout\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~35\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010000000000000000000000001010101001010101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~38_cout\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~39\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~34_cout\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~35\); + +-- Location: MLABCELL_X42_Y9_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~30_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4)) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~35\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~34_cout\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~31\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~34_cout\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~35\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~30_cout\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~31\); + +-- Location: MLABCELL_X42_Y9_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~26_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~31\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~30_cout\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~27\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~30_cout\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~31\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~26_cout\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~27\); + +-- Location: MLABCELL_X42_Y9_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~22_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~27\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~26_cout\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~23\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~26_cout\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~27\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~22_cout\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~23\); + +-- Location: MLABCELL_X42_Y9_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~18_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7)) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~23\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~22_cout\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~19\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~22_cout\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~23\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~18_cout\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~19\); + +-- Location: MLABCELL_X42_Y9_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~19\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~18_cout\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~2\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~19\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~18_cout\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~3\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~18_cout\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~19\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~2\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~3\); + +-- Location: MLABCELL_X42_Y9_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~3\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~6\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~3\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~7\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000000000000001100001111000011", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[9]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~2\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~3\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~6\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~7\); + +-- Location: MLABCELL_X42_Y9_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10)) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~7\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~10\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10)) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~7\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~11\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000000000000000000000001111000000001111", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~6\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~7\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~10\, + shareout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~11\); + +-- Location: MLABCELL_X42_Y9_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1_sumout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~13_sumout\) # ((!\myVirtualToplevel|RESET_n~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~9_sumout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~13_sumout\, + datab => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~9_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~2_combout\); + +-- Location: LABCELL_X41_Y10_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~1_combout\); + +-- Location: FF_X39_Y10_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~q\); + +-- Location: LABCELL_X41_Y10_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_SPACE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_SPACE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000000000000000001100110001001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SPACE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_SPACE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~3_combout\); + +-- Location: FF_X41_Y10_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_SPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~3_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_SPACE~q\); + +-- Location: MLABCELL_X34_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222_RESYN12864\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\); + +-- Location: MLABCELL_X34_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_OTERM2223\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001111110001111100001111000011110011111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_OTERM2223\); + +-- Location: FF_X34_Y23_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_OTERM2223\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\); + +-- Location: FF_X42_Y14_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_PRE_CR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_PRE_CR~q\); + +-- Location: FF_X40_Y14_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_PRE_CR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_PRE_CR~q\); + +-- Location: MLABCELL_X42_Y14_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~feeder_combout\); + +-- Location: FF_X42_Y14_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~q\); + +-- Location: LABCELL_X36_Y13_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~feeder_combout\); + +-- Location: FF_X36_Y13_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~q\); + +-- Location: LABCELL_X40_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~feeder_combout\); + +-- Location: FF_X40_Y18_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~q\); + +-- Location: FF_X36_Y13_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_PRE_CR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_PRE_CR~q\); + +-- Location: MLABCELL_X37_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~feeder_combout\); + +-- Location: FF_X37_Y13_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~q\); + +-- Location: LABCELL_X36_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2))))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~q\))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_PRE_CR~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001110100011101000011000011111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_PRE_CR~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_PRE_CR~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_PRE_CR~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_PRE_CR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4_combout\); + +-- Location: MLABCELL_X42_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~feeder_combout\); + +-- Location: FF_X42_Y17_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~q\); + +-- Location: MLABCELL_X42_Y14_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~q\)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_PRE_CR~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_PRE_CR~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001100000011000000110000001111001100111111111101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_PRE_CR~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_PRE_CR~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_PRE_CR~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux4~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_PRE_CR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~0_combout\); + +-- Location: FF_X41_Y10_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~1_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~q\); + +-- Location: LABCELL_X41_Y10_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~32_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~q\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~32_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000001111000011100000111100001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_CR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~1_combout\); + +-- Location: FF_X41_Y10_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~1_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y10_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_SPACE~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_SPACE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SPACE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_CR~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~1_combout\); + +-- Location: MLABCELL_X42_Y9_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000000000000010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~3_combout\); + +-- Location: FF_X42_Y9_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~q\); + +-- Location: LABCELL_X41_Y10_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~32_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_SPACE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000000000000010100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SPACE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_SPACE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~32_combout\); + +-- Location: LABCELL_X41_Y10_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~32_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~32_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_CR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\); + +-- Location: FF_X36_Y11_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~17_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~DUPLICATE_q\); + +-- Location: LABCELL_X36_Y11_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0_combout\); + +-- Location: LABCELL_X36_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector42~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_SP~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\); + +-- Location: MLABCELL_X42_Y11_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~3_combout\); + +-- Location: MLABCELL_X37_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE_NEW2186\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE_OTERM2187\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1377~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1377~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DECODED_OPCODE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE_OTERM2187\); + +-- Location: FF_X37_Y25_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE_OTERM2187\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\); + +-- Location: FF_X47_Y17_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DECODED_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DECODED_OPCODE~q\); + +-- Location: LABCELL_X47_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DECODED_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~feeder_combout\); + +-- Location: FF_X47_Y17_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~q\); + +-- Location: MLABCELL_X49_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DECODED_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~feeder_combout\); + +-- Location: FF_X49_Y17_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~q\); + +-- Location: FF_X48_Y17_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DECODED_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DECODED_OPCODE~q\); + +-- Location: LABCELL_X48_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DECODED_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~feeder_combout\); + +-- Location: FF_X48_Y17_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~q\); + +-- Location: LABCELL_X48_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DECODED_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~feeder_combout\); + +-- Location: FF_X48_Y17_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~q\); + +-- Location: LABCELL_X48_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~q\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DECODED_OPCODE~q\)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001100100011001000110010011101100111011001110110001100100111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DECODED_OPCODE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DECODED_OPCODE~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DECODED_OPCODE~q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DECODED_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4_combout\); + +-- Location: LABCELL_X47_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DECODED_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~feeder_combout\); + +-- Location: FF_X47_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~q\); + +-- Location: FF_X50_Y14_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DECODED_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DECODED_OPCODE~q\); + +-- Location: LABCELL_X47_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DECODED_OPCODE~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~q\)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DECODED_OPCODE~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001111001100000000111101110100000011111111110000001111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DECODED_OPCODE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DECODED_OPCODE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux25~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DECODED_OPCODE~q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DECODED_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~0_combout\); + +-- Location: MLABCELL_X42_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111000001110111000000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux25~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DECODED_OPCODE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~12_combout\); + +-- Location: FF_X42_Y11_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~12_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\); + +-- Location: MLABCELL_X42_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011000000110000001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DECODED_OPCODE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\); + +-- Location: MLABCELL_X42_Y11_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\); + +-- Location: LABCELL_X32_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111111111100001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\); + +-- Location: LABCELL_X32_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\ ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101011111111000000001111111110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\); + +-- Location: LABCELL_X31_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3_NEW2218\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3_OTERM2219\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001100111111000000110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA3~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3_OTERM2219\); + +-- Location: FF_X31_Y25_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3_OTERM2219\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\); + +-- Location: LABCELL_X44_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA3~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~feeder_combout\); + +-- Location: FF_X44_Y24_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~q\); + +-- Location: LABCELL_X48_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA3~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~feeder_combout\); + +-- Location: FF_X48_Y17_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~q\); + +-- Location: FF_X48_Y17_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA3\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA3~q\); + +-- Location: FF_X48_Y17_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA3\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA3~q\); + +-- Location: LABCELL_X48_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA3~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~q\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA3~q\)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001100100111011000110010001100100011001001110110011101100111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA3~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA3~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA3~q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA3~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~4_combout\); + +-- Location: FF_X47_Y17_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA3\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA3~q\); + +-- Location: FF_X47_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA3\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA3~q\); + +-- Location: FF_X47_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA3\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA3~q\); + +-- Location: FF_X45_Y17_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA3\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA3~q\); + +-- Location: LABCELL_X47_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA3~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~4_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA3~q\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA3~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA3~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0100011001000110010001100101011101010111010101110100011001010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux22~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA3~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA3~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA3~q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA3~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~0_combout\); + +-- Location: FF_X34_Y23_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_OTERM2175\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~q\); + +-- Location: MLABCELL_X34_Y23_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174_RESYN12858\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~q\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\); + +-- Location: MLABCELL_X34_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_OTERM2175\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111010011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_OTERM2175\); + +-- Location: FF_X34_Y23_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_OTERM2175\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE_q\); + +-- Location: LABCELL_X47_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~feeder_combout\); + +-- Location: FF_X47_Y17_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~q\); + +-- Location: FF_X47_Y17_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA~q\); + +-- Location: LABCELL_X47_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~feeder_combout\); + +-- Location: FF_X47_Y17_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~q\); + +-- Location: FF_X50_Y21_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA~q\); + +-- Location: LABCELL_X47_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~feeder_combout\); + +-- Location: FF_X47_Y21_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~q\); + +-- Location: LABCELL_X50_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~feeder_combout\); + +-- Location: FF_X50_Y21_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~q\); + +-- Location: LABCELL_X47_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~feeder_combout\); + +-- Location: FF_X47_Y23_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~q\); + +-- Location: LABCELL_X50_Y21_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA~q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000110000110011000011000111011100001100111111110000110001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA~q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4_combout\); + +-- Location: LABCELL_X50_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~feeder_combout\); + +-- Location: FF_X50_Y17_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~q\); + +-- Location: LABCELL_X47_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~q\))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000001111000000000000111111111111010101011111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux20~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~0_combout\); + +-- Location: MLABCELL_X42_Y10_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal2~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\); + +-- Location: FF_X32_Y25_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG348\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM349\); + +-- Location: LABCELL_X32_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239~feeder_combout\); + +-- Location: FF_X32_Y25_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG238\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239\); + +-- Location: LABCELL_X32_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_RTM0364\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_RTM0364_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_RTM0364_combout\); + +-- Location: FF_X32_Y25_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[0]_NEW_REG362\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_RTM0364_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[0]_OTERM363\); + +-- Location: LABCELL_X32_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[0]_OTERM363\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[0]_OTERM363\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM349\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101111101011111010111110101111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM349\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM239\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_SPLIT_DATA[0]_OTERM363\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\); + +-- Location: LABCELL_X48_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[0]~feeder_combout\); + +-- Location: FF_X48_Y22_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA\(0)); + +-- Location: LABCELL_X48_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[0]~feeder_combout\); + +-- Location: FF_X48_Y22_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA\(0)); + +-- Location: FF_X49_Y22_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA\(0)); + +-- Location: FF_X49_Y22_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\(0)); + +-- Location: MLABCELL_X49_Y22_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_SPLIT_DATA\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_SPLIT_DATA\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_SPLIT_DATA\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_SPLIT_DATA\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~9_combout\); + +-- Location: LABCELL_X44_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[0]~feeder_combout\); + +-- Location: FF_X44_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\(0)); + +-- Location: LABCELL_X44_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[0]~feeder_combout\); + +-- Location: FF_X44_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\(0)); + +-- Location: LABCELL_X44_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[0]~feeder_combout\); + +-- Location: FF_X44_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\(0)); + +-- Location: FF_X44_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(0)); + +-- Location: LABCELL_X44_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\(0))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\(0))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_SPLIT_DATA\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_SPLIT_DATA\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_SPLIT_DATA\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_SPLIT_DATA\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~8_combout\); + +-- Location: LABCELL_X44_Y10_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~9_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111000000000000011100000000000001110111011100000111011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~10_combout\); + +-- Location: LABCELL_X44_Y10_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1]~0_combout\ = ( \myVirtualToplevel|RESET_n~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~37_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + dataf => \myVirtualToplevel|ALT_INV_RESET_n~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1]~0_combout\); + +-- Location: FF_X44_Y10_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~10_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA\(0)); + +-- Location: MLABCELL_X37_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010100000101010001010000010101000101010001010100010101000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~1_combout\); + +-- Location: MLABCELL_X37_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[1]_NEW2226\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[1]_OTERM2227\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\(1)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_SPLIT_DATA\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[1]_OTERM2227\); + +-- Location: FF_X37_Y25_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[1]_OTERM2227\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\(1)); + +-- Location: MLABCELL_X49_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_SPLIT_DATA\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~feeder_combout\); + +-- Location: FF_X49_Y29_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\(1)); + +-- Location: FF_X47_Y29_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\(1)); + +-- Location: FF_X49_Y29_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(1)); + +-- Location: FF_X43_Y29_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\(1)); + +-- Location: MLABCELL_X49_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\(1) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(1) +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_SPLIT_DATA\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_SPLIT_DATA\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_SPLIT_DATA\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_SPLIT_DATA\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~4_combout\); + +-- Location: LABCELL_X50_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_SPLIT_DATA\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~feeder_combout\); + +-- Location: FF_X50_Y30_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\(1)); + +-- Location: FF_X49_Y30_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA\(1)); + +-- Location: MLABCELL_X49_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA\(1) & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000000000000000000010100000101000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_SPLIT_DATA\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_SPLIT_DATA\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~5_combout\); + +-- Location: FF_X49_Y30_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA\(1)); + +-- Location: FF_X49_Y30_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA\(1)); + +-- Location: MLABCELL_X49_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA\(1)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010000000000000101000001010101010100000000000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_SPLIT_DATA\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_SPLIT_DATA\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~6_combout\); + +-- Location: LABCELL_X44_Y10_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~4_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~5_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111100000101000001010000010110001100000001000000010000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~7_combout\); + +-- Location: FF_X44_Y10_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~7_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA\(1)); + +-- Location: LABCELL_X44_Y10_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_SPLIT_DATA\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_SPLIT_DATA\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\); + +-- Location: LABCELL_X44_Y11_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal2~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~40_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\); + +-- Location: LABCELL_X44_Y14_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~21_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111100111111001100000011000000110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux20~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~21_combout\); + +-- Location: FF_X44_Y14_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~21_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\); + +-- Location: LABCELL_X31_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2_NEW2220\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2_OTERM2221\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001100111111000000110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2_OTERM2221\); + +-- Location: FF_X31_Y25_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2_OTERM2221\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\); + +-- Location: MLABCELL_X45_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~feeder_combout\); + +-- Location: FF_X45_Y16_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~q\); + +-- Location: FF_X47_Y20_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA2~q\); + +-- Location: FF_X48_Y17_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA2~q\); + +-- Location: FF_X48_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA2~q\); + +-- Location: LABCELL_X48_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~feeder_combout\); + +-- Location: FF_X48_Y19_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~q\); + +-- Location: LABCELL_X48_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA2~q\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA2~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA2~q\)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001100100111011000110010001100100011001001110110011101100111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA2~q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~4_combout\); + +-- Location: MLABCELL_X45_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~feeder_combout\); + +-- Location: FF_X45_Y16_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~q\); + +-- Location: FF_X45_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA2~q\); + +-- Location: LABCELL_X48_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~feeder_combout\); + +-- Location: FF_X48_Y19_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~q\); + +-- Location: MLABCELL_X45_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~4_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2))))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~4_combout\ & +-- ((((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~q\))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~4_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA2~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0011001100110011001100110011001100011101000111010000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux21~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA2~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~0_combout\); + +-- Location: LABCELL_X44_Y14_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001101110110000000000010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux21~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~22_combout\); + +-- Location: FF_X44_Y14_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~22_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\); + +-- Location: LABCELL_X43_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\); + +-- Location: LABCELL_X44_Y14_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001110111011101110100010001000100011101000011010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux22~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~19_combout\); + +-- Location: FF_X44_Y14_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~19_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\); + +-- Location: LABCELL_X31_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4_NEW2216\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4_OTERM2217\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001100111111000000110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA4~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4_OTERM2217\); + +-- Location: FF_X31_Y25_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4_OTERM2217\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\); + +-- Location: FF_X49_Y14_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA4\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA4~q\); + +-- Location: FF_X49_Y14_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA4\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA4~q\); + +-- Location: FF_X49_Y14_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA4\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA4~q\); + +-- Location: FF_X48_Y16_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA4\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA4~q\); + +-- Location: FF_X48_Y16_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA4\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA4~q\); + +-- Location: FF_X49_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA4\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA4~q\); + +-- Location: MLABCELL_X49_Y16_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA4~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~feeder_combout\); + +-- Location: FF_X49_Y16_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~q\); + +-- Location: MLABCELL_X49_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA4~q\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA4~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA4~q\)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001100100111011000110010001100100011001001110110011101100111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA4~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA4~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA4~q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA4~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4_combout\); + +-- Location: LABCELL_X44_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA4~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~feeder_combout\); + +-- Location: FF_X44_Y14_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~q\); + +-- Location: MLABCELL_X49_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA4~q\)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA4~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA4~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000010100000101000001010000010110101010111111111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA4~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA4~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA4~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux23~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA4~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~0_combout\); + +-- Location: LABCELL_X44_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111111000101010000000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux23~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA4~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~20_combout\); + +-- Location: FF_X44_Y14_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~20_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4~q\); + +-- Location: LABCELL_X44_Y14_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA4~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal2~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\); + +-- Location: FF_X43_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_DATA_PRTMODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_DATA_PRTMODE\(0)); + +-- Location: LABCELL_X44_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE[0]~feeder_combout\); + +-- Location: FF_X44_Y16_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE\(0)); + +-- Location: LABCELL_X44_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE[0]~feeder_combout\); + +-- Location: FF_X44_Y16_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE\(0)); + +-- Location: FF_X43_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_DATA_PRTMODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_DATA_PRTMODE\(0)); + +-- Location: LABCELL_X43_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_DATA_PRTMODE\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_DATA_PRTMODE\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_DATA_PRTMODE\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_DATA_PRTMODE\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_DATA_PRTMODE\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_DATA_PRTMODE\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_DATA_PRTMODE\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_DATA_PRTMODE\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_DATA_PRTMODE\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_DATA_PRTMODE\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~0_combout\); + +-- Location: MLABCELL_X42_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE[0]~feeder_combout\); + +-- Location: FF_X42_Y22_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE\(0)); + +-- Location: LABCELL_X48_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE[0]~feeder_combout\); + +-- Location: FF_X48_Y22_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE\(0)); + +-- Location: FF_X48_Y22_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_DATA_PRTMODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_DATA_PRTMODE\(0)); + +-- Location: LABCELL_X48_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE[0]~feeder_combout\); + +-- Location: FF_X48_Y22_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE\(0)); + +-- Location: LABCELL_X48_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_DATA_PRTMODE\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE\(0) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_DATA_PRTMODE\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_DATA_PRTMODE\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_DATA_PRTMODE\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100111101001100011100110111000001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_DATA_PRTMODE\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_DATA_PRTMODE\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_DATA_PRTMODE\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_DATA_PRTMODE\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~1_combout\); + +-- Location: MLABCELL_X42_Y22_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux1~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux1~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~2_combout\); + +-- Location: LABCELL_X44_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\ = ( \myVirtualToplevel|RESET_n~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\); + +-- Location: FF_X42_Y22_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE\(0)); + +-- Location: MLABCELL_X42_Y10_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE\(0)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE\(0)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101110100001100010111010000110001010101000000000101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal2~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_DATA_PRTMODE\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~41_combout\); + +-- Location: LABCELL_X44_Y10_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~41_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~41_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~41_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~41_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010001111100001111000100000000000100010000000000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~40_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~41_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~42_combout\); + +-- Location: FF_X44_Y10_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~42_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\); + +-- Location: LABCELL_X44_Y10_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_SPLIT_DATA\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~1_combout\); + +-- Location: FF_X44_Y10_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~1_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(0)); + +-- Location: LABCELL_X44_Y10_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector112~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector112~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(1)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(1)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010101010101000000000101010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector111~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector112~0_combout\); + +-- Location: FF_X44_Y10_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~42_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y9_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ = ( \myVirtualToplevel|RESET_n~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~13_sumout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~9_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111101111111111111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~13_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~9_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~1_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~5_sumout\, + dataf => \myVirtualToplevel|ALT_INV_RESET_n~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\); + +-- Location: MLABCELL_X42_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001101010101011101110101010101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~40_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\); + +-- Location: LABCELL_X44_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111111111111111100000011000000111111110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~4_combout\); + +-- Location: FF_X44_Y11_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0)); + +-- Location: LABCELL_X44_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[1]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[1]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(1) $ +-- ((((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(1)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111111111000000111111111100000010111111010000001011111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[1]~3_combout\); + +-- Location: FF_X44_Y11_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[1]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(1)); + +-- Location: LABCELL_X44_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[2]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[2]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(1)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000010111111101111111100000010000000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[2]~2_combout\); + +-- Location: FF_X44_Y11_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[2]~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(2)); + +-- Location: LABCELL_X44_Y11_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(1)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\); + +-- Location: MLABCELL_X45_Y10_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_NIBBLECNT~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~1_combout\); + +-- Location: FF_X44_Y10_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~36_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\); + +-- Location: LABCELL_X44_Y10_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~0_combout\); + +-- Location: FF_X45_Y10_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\); + +-- Location: MLABCELL_X42_Y10_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110001001100010011000100110001001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_NIBBLECNT~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~3_combout\); + +-- Location: MLABCELL_X42_Y10_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~2_combout\); + +-- Location: MLABCELL_X42_Y10_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000111000000000000011100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\); + +-- Location: FF_X43_Y12_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~101_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[8]~DUPLICATE_q\); + +-- Location: LABCELL_X36_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[2]_NEW2190\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[2]_OTERM2191\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001010000010101111101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[2]_OTERM2191\); + +-- Location: FF_X36_Y25_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[2]_OTERM2191\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2)); + +-- Location: FF_X37_Y18_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(2)); + +-- Location: FF_X32_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(2)); + +-- Location: FF_X32_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(2)); + +-- Location: FF_X32_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(2)); + +-- Location: LABCELL_X32_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(2))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(2))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2_BYTECNT\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2_BYTECNT\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2_BYTECNT\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2_BYTECNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~0_combout\); + +-- Location: FF_X32_Y20_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(2)); + +-- Location: MLABCELL_X37_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[2]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[2]~feeder_combout\); + +-- Location: FF_X37_Y20_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(2)); + +-- Location: FF_X37_Y20_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(2)); + +-- Location: FF_X36_Y20_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(2)); + +-- Location: MLABCELL_X37_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(2) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(2))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100000001111100011100110100111101000011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2_BYTECNT\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2_BYTECNT\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2_BYTECNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2_BYTECNT\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~1_combout\); + +-- Location: MLABCELL_X37_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux11~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux11~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~2_combout\); + +-- Location: FF_X37_Y20_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(2)); + +-- Location: FF_X44_Y14_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~19_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y14_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\); + +-- Location: MLABCELL_X34_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[2]_NEW2196\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[2]_OTERM2197\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[2]_OTERM2197\); + +-- Location: FF_X34_Y25_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[2]_OTERM2197\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(2)); + +-- Location: FF_X34_Y16_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(2)); + +-- Location: FF_X40_Y16_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(2)); + +-- Location: FF_X34_Y16_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(2)); + +-- Location: FF_X34_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(2)); + +-- Location: MLABCELL_X34_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(2)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(2)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3_BYTECNT\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3_BYTECNT\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3_BYTECNT\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3_BYTECNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~0_combout\); + +-- Location: LABCELL_X39_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[2]~feeder_combout\); + +-- Location: FF_X39_Y20_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(2)); + +-- Location: FF_X37_Y17_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(2)); + +-- Location: FF_X37_Y17_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(2)); + +-- Location: MLABCELL_X34_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[2]~feeder_combout\); + +-- Location: FF_X34_Y17_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(2)); + +-- Location: MLABCELL_X37_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(2) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(2))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000100111001101101000110110011100101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3_BYTECNT\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3_BYTECNT\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3_BYTECNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3_BYTECNT\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~1_combout\); + +-- Location: MLABCELL_X37_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux14~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux14~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~2_combout\); + +-- Location: FF_X37_Y17_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(2)); + +-- Location: LABCELL_X32_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[2]_NEW2198\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[2]_OTERM2199\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001010000010101111101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[2]_OTERM2199\); + +-- Location: FF_X32_Y22_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[2]_OTERM2199\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2)); + +-- Location: FF_X35_Y13_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(2)); + +-- Location: MLABCELL_X34_Y13_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[2]~feeder_combout\); + +-- Location: FF_X34_Y13_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(2)); + +-- Location: FF_X36_Y13_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(2)); + +-- Location: FF_X36_Y13_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(2)); + +-- Location: LABCELL_X36_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(2)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(2))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(2))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4_BYTECNT\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4_BYTECNT\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4_BYTECNT\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4_BYTECNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~1_combout\); + +-- Location: MLABCELL_X34_Y11_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[2]~feeder_combout\); + +-- Location: FF_X34_Y11_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(2)); + +-- Location: MLABCELL_X34_Y11_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[2]~feeder_combout\); + +-- Location: FF_X34_Y11_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(2)); + +-- Location: FF_X34_Y11_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(2)); + +-- Location: FF_X35_Y13_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(2)); + +-- Location: MLABCELL_X34_Y11_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(2) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(2)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(2) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(2))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000010110000000110101011101000010101101101010001111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4_BYTECNT\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4_BYTECNT\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4_BYTECNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~0_combout\); + +-- Location: LABCELL_X39_Y13_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux17~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux17~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~2_combout\); + +-- Location: FF_X39_Y13_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(2)); + +-- Location: FF_X34_Y23_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_OTERM2193\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(2)); + +-- Location: MLABCELL_X34_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010100000000010001010000000011111111101110101111111110111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\); + +-- Location: MLABCELL_X34_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_OTERM2193\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\))) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101000101010101010111010101010101010001000101010101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_OTERM2193\); + +-- Location: FF_X34_Y23_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_OTERM2193\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE_q\); + +-- Location: LABCELL_X32_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[2]~feeder_combout\); + +-- Location: FF_X32_Y18_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(2)); + +-- Location: LABCELL_X32_Y18_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[2]~feeder_combout\); + +-- Location: FF_X32_Y18_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(2)); + +-- Location: LABCELL_X36_Y17_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[2]~feeder_combout\); + +-- Location: FF_X36_Y17_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(2)); + +-- Location: FF_X32_Y18_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(2)); + +-- Location: LABCELL_X32_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(2)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA_BYTECNT\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA_BYTECNT\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA_BYTECNT\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA_BYTECNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~0_combout\); + +-- Location: MLABCELL_X42_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[2]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[2]~feeder_combout\); + +-- Location: FF_X42_Y19_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(2)); + +-- Location: MLABCELL_X37_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[2]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[2]~feeder_combout\); + +-- Location: FF_X37_Y20_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(2)); + +-- Location: FF_X37_Y20_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(2)); + +-- Location: MLABCELL_X42_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[2]~feeder_combout\); + +-- Location: FF_X42_Y19_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(2)); + +-- Location: MLABCELL_X37_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(2) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(2) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(2)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(2))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110110101010100011011101010100001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA_BYTECNT\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA_BYTECNT\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA_BYTECNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA_BYTECNT\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~1_combout\); + +-- Location: MLABCELL_X37_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux8~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux8~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~2_combout\); + +-- Location: FF_X37_Y20_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(2)); + +-- Location: MLABCELL_X37_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(2))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(2))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001110111011101110100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2_BYTECNT\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3_BYTECNT\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4_BYTECNT\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA_BYTECNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~3_combout\); + +-- Location: LABCELL_X44_Y11_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000000000000010100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~0_combout\); + +-- Location: LABCELL_X41_Y11_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_NIBBLECNT~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector13~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~1_combout\); + +-- Location: FF_X42_Y11_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(0)); + +-- Location: MLABCELL_X42_Y11_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\); + +-- Location: MLABCELL_X42_Y10_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000110010001100100011001000110000000000100011000000000010001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_NIBBLECNT~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~2_combout\); + +-- Location: LABCELL_X41_Y11_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101011111111101010101111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~4_combout\); + +-- Location: MLABCELL_X42_Y11_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(0) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(0) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(0) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010101000101010001010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~5_combout\); + +-- Location: LABCELL_X31_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[0]_NEW2210\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[0]_OTERM2211\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001100111111000000110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[0]_OTERM2211\); + +-- Location: FF_X31_Y25_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[0]_OTERM2211\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(0)); + +-- Location: LABCELL_X43_Y13_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X43_Y13_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(0)); + +-- Location: LABCELL_X44_Y13_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X44_Y13_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(0)); + +-- Location: FF_X44_Y13_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(0)); + +-- Location: FF_X44_Y13_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(0)); + +-- Location: LABCELL_X44_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2_BYTECNT\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2_BYTECNT\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2_BYTECNT\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~1_combout\); + +-- Location: FF_X41_Y14_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(0)); + +-- Location: LABCELL_X40_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X40_Y14_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(0)); + +-- Location: LABCELL_X40_Y14_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X40_Y14_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(0)); + +-- Location: FF_X41_Y14_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(0)); + +-- Location: LABCELL_X41_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2_BYTECNT\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2_BYTECNT\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2_BYTECNT\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~0_combout\); + +-- Location: LABCELL_X43_Y14_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000000000000001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux13~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux13~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~2_combout\); + +-- Location: FF_X43_Y14_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(0)); + +-- Location: FF_X17_Y33_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG604\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM605\); + +-- Location: LABCELL_X29_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000110000001100000000001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~1_combout\); + +-- Location: FF_X29_Y29_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG614\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM615\); + +-- Location: FF_X32_Y26_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG606\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM607\); + +-- Location: FF_X34_Y33_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG610\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM611\); + +-- Location: FF_X34_Y33_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG608\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM609\); + +-- Location: MLABCELL_X28_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr160~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100111111111111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr160~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\); + +-- Location: FF_X34_Y33_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG612\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM613\); + +-- Location: MLABCELL_X34_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM609\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM613\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM607\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM611\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM615\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM609\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM613\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM611\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM615\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM609\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM613\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM605\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM607\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM611\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM615\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM609\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM613\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM611\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM615\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001111111111101100111111111100110011111111111111001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM605\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM615\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM607\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM611\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM609\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM613\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\); + +-- Location: MLABCELL_X49_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X49_Y19_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(0)); + +-- Location: MLABCELL_X49_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X49_Y19_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(0)); + +-- Location: LABCELL_X50_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X50_Y19_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(0)); + +-- Location: FF_X49_Y19_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(0)); + +-- Location: MLABCELL_X49_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(0))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(0))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA_BYTECNT\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA_BYTECNT\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA_BYTECNT\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~1_combout\); + +-- Location: FF_X49_Y14_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(0)); + +-- Location: LABCELL_X50_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X50_Y14_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(0)); + +-- Location: FF_X49_Y14_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(0)); + +-- Location: FF_X49_Y14_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(0)); + +-- Location: MLABCELL_X49_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA_BYTECNT\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA_BYTECNT\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA_BYTECNT\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~0_combout\); + +-- Location: LABCELL_X43_Y14_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux10~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux10~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~2_combout\); + +-- Location: FF_X43_Y14_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(0)); + +-- Location: LABCELL_X43_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(0) & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000011111111010100001111111101010000000000000101000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2_BYTECNT\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~5_combout\); + +-- Location: MLABCELL_X42_Y11_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000001010000111100000101000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DECODED_OPCODE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~7_combout\); + +-- Location: LABCELL_X31_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[0]_NEW2212\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[0]_OTERM2213\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001100111111000000110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[0]_OTERM2213\); + +-- Location: FF_X31_Y25_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[0]_OTERM2213\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(0)); + +-- Location: LABCELL_X48_Y14_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X48_Y14_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(0)); + +-- Location: MLABCELL_X49_Y14_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[0]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X49_Y14_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(0)); + +-- Location: MLABCELL_X49_Y14_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[0]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X49_Y14_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(0)); + +-- Location: FF_X49_Y14_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(0)); + +-- Location: MLABCELL_X49_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3_BYTECNT\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3_BYTECNT\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3_BYTECNT\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~0_combout\); + +-- Location: MLABCELL_X49_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[0]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X49_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(0)); + +-- Location: FF_X48_Y17_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(0)); + +-- Location: MLABCELL_X49_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X49_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(0)); + +-- Location: FF_X49_Y17_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(0)); + +-- Location: MLABCELL_X49_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3_BYTECNT\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3_BYTECNT\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3_BYTECNT\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~1_combout\); + +-- Location: LABCELL_X43_Y14_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux16~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux16~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~2_combout\); + +-- Location: FF_X43_Y14_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(0)); + +-- Location: LABCELL_X31_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[0]_NEW2214\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[0]_OTERM2215\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001100111111000000110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[0]_OTERM2215\); + +-- Location: FF_X31_Y25_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[0]_OTERM2215\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(0)); + +-- Location: FF_X44_Y13_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(0)); + +-- Location: FF_X44_Y13_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(0)); + +-- Location: FF_X44_Y13_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(0)); + +-- Location: LABCELL_X43_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X43_Y13_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(0)); + +-- Location: LABCELL_X44_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110000000001010011111111110101001100001111010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4_BYTECNT\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4_BYTECNT\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~1_combout\); + +-- Location: FF_X45_Y13_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(0)); + +-- Location: FF_X45_Y13_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(0)); + +-- Location: FF_X45_Y13_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(0)); + +-- Location: LABCELL_X48_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[0]~feeder_combout\); + +-- Location: FF_X48_Y13_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(0)); + +-- Location: MLABCELL_X45_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(0) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(0) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100000000000111011100110000011101001100110001110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4_BYTECNT\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4_BYTECNT\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~0_combout\); + +-- Location: MLABCELL_X45_Y13_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux19~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux19~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~2_combout\); + +-- Location: FF_X43_Y14_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(0)); + +-- Location: LABCELL_X43_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(0))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010001010100000001000101010000000100000001000000010000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3_BYTECNT\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA4~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~6_combout\); + +-- Location: LABCELL_X43_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~7_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~7_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111100000000001111110000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal2~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~8_combout\); + +-- Location: MLABCELL_X42_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~8_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~5_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~8_combout\ & ( +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~3_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111111100111111011111110011111101011111000011110101111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~6_combout\); + +-- Location: FF_X42_Y11_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[0]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y12_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[0]~DUPLICATE_q\, + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~18\); + +-- Location: LABCELL_X43_Y12_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(1) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(1) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(1), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~14\); + +-- Location: LABCELL_X32_Y22_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[1]_NEW2200\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[1]_OTERM2201\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000000000000000101010101111111110101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[1]_OTERM2201\); + +-- Location: FF_X32_Y22_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[1]_OTERM2201\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1)); + +-- Location: LABCELL_X39_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[1]~feeder_combout\); + +-- Location: FF_X39_Y13_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(1)); + +-- Location: LABCELL_X36_Y13_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[1]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[1]~feeder_combout\); + +-- Location: FF_X36_Y13_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(1)); + +-- Location: FF_X36_Y13_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(1)); + +-- Location: FF_X35_Y13_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(1)); + +-- Location: LABCELL_X36_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(1) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(1)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(1)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(1)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010001000100101111101110111000010100111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2_BYTECNT\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2_BYTECNT\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2_BYTECNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2_BYTECNT\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~1_combout\); + +-- Location: FF_X40_Y13_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(1)); + +-- Location: FF_X35_Y13_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(1)); + +-- Location: FF_X40_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(1)); + +-- Location: FF_X40_Y13_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(1)); + +-- Location: LABCELL_X40_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(1))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(1)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000111001101000011011111000100110001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2_BYTECNT\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2_BYTECNT\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2_BYTECNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2_BYTECNT\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~0_combout\); + +-- Location: LABCELL_X39_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux12~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux12~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~2_combout\); + +-- Location: FF_X39_Y13_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(1)); + +-- Location: LABCELL_X31_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[1]_NEW2208\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[1]_OTERM2209\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(1)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001100111111000000110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[1]_OTERM2209\); + +-- Location: FF_X31_Y25_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[1]_OTERM2209\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(1)); + +-- Location: FF_X43_Y13_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(1)); + +-- Location: FF_X44_Y13_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(1)); + +-- Location: FF_X43_Y13_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(1)); + +-- Location: FF_X44_Y13_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(1)); + +-- Location: LABCELL_X44_Y13_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(1))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(1))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4_BYTECNT\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4_BYTECNT\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4_BYTECNT\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4_BYTECNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~1_combout\); + +-- Location: MLABCELL_X42_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[1]~feeder_combout\); + +-- Location: FF_X42_Y13_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(1)); + +-- Location: FF_X45_Y13_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(1)); + +-- Location: FF_X45_Y13_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(1)); + +-- Location: FF_X45_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(1)); + +-- Location: MLABCELL_X45_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(1))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(1)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010010101011111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4_BYTECNT\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4_BYTECNT\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4_BYTECNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~0_combout\); + +-- Location: LABCELL_X39_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux18~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux18~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~2_combout\); + +-- Location: FF_X39_Y13_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(1)); + +-- Location: MLABCELL_X34_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(1) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\); + +-- Location: MLABCELL_X34_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_OTERM2203\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000010011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_OTERM2203\); + +-- Location: FF_X34_Y23_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_OTERM2203\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(1)); + +-- Location: LABCELL_X39_Y13_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[1]~feeder_combout\); + +-- Location: FF_X39_Y13_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(1)); + +-- Location: FF_X35_Y13_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(1)); + +-- Location: FF_X36_Y13_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(1)); + +-- Location: FF_X36_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(1)); + +-- Location: LABCELL_X36_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(1)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA_BYTECNT\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA_BYTECNT\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA_BYTECNT\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA_BYTECNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~1_combout\); + +-- Location: FF_X40_Y13_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(1)); + +-- Location: FF_X35_Y13_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(1)); + +-- Location: FF_X40_Y13_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(1)); + +-- Location: FF_X40_Y13_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(1)); + +-- Location: LABCELL_X40_Y13_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(1))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(1)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000111001101000011011111000100110001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA_BYTECNT\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA_BYTECNT\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA_BYTECNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA_BYTECNT\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~0_combout\); + +-- Location: LABCELL_X39_Y13_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux9~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux9~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~2_combout\); + +-- Location: FF_X39_Y13_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(1)); + +-- Location: LABCELL_X31_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[1]_NEW2206\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[1]_OTERM2207\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(1)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001100111111000000110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[1]_OTERM2207\); + +-- Location: FF_X31_Y25_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[1]_OTERM2207\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(1)); + +-- Location: LABCELL_X44_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[1]~feeder_combout\); + +-- Location: FF_X44_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(1)); + +-- Location: FF_X44_Y13_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(1)); + +-- Location: FF_X43_Y13_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(1)); + +-- Location: FF_X44_Y13_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(1)); + +-- Location: LABCELL_X44_Y13_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(1))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(1))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3_BYTECNT\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3_BYTECNT\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3_BYTECNT\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3_BYTECNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~1_combout\); + +-- Location: FF_X45_Y13_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(1)); + +-- Location: FF_X39_Y13_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(1)); + +-- Location: FF_X45_Y13_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(1)); + +-- Location: FF_X45_Y13_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(1)); + +-- Location: MLABCELL_X45_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(1))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3_BYTECNT\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3_BYTECNT\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3_BYTECNT\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3_BYTECNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~0_combout\); + +-- Location: LABCELL_X39_Y13_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux15~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux15~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~2_combout\); + +-- Location: FF_X39_Y13_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(1)); + +-- Location: LABCELL_X39_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(1))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(1))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2_BYTECNT\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4_BYTECNT\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA_BYTECNT\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3_BYTECNT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2_combout\); + +-- Location: LABCELL_X43_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(0) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010010001101100111000010011100110110101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2_BYTECNT\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA_BYTECNT\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4_BYTECNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3_BYTECNT\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\); + +-- Location: LABCELL_X43_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector43~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector43~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~13_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~13_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~13_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~13_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001001110010011100100111001001110010001000100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~13_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector43~0_combout\); + +-- Location: FF_X43_Y14_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector43~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(1)); + +-- Location: LABCELL_X43_Y12_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[2]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~10\); + +-- Location: LABCELL_X43_Y14_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000011000000111111110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~1_combout\); + +-- Location: LABCELL_X44_Y12_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~9_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~9_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~9_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~9_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~9_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector42~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~2_combout\); + +-- Location: FF_X44_Y12_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[2]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y12_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~6\); + +-- Location: LABCELL_X43_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector41~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector41~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~5_sumout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~5_sumout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000000000000000110011001100110000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector41~0_combout\); + +-- Location: FF_X43_Y14_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector41~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(3)); + +-- Location: LABCELL_X43_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~125\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~125_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~126\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~125_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~126\); + +-- Location: FF_X43_Y12_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~125_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(4)); + +-- Location: LABCELL_X43_Y12_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~113\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~113_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~126\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~114\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~126\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~126\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~113_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~114\); + +-- Location: FF_X43_Y12_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~113_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(5)); + +-- Location: LABCELL_X43_Y12_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~109\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~109_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[6]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~114\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~110\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[6]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~114\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[6]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~114\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~109_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~110\); + +-- Location: FF_X43_Y12_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~109_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[6]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y12_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~105\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~105_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(7) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~110\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~106\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(7) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~110\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~110\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~105_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~106\); + +-- Location: FF_X43_Y12_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~105_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(7)); + +-- Location: LABCELL_X43_Y12_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~101\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~101_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[8]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~106\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~102\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[8]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~106\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[8]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~106\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~101_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~102\); + +-- Location: FF_X43_Y12_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~101_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(8)); + +-- Location: FF_X43_Y12_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~109_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(6)); + +-- Location: FF_X43_Y12_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~105_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[7]~DUPLICATE_q\); + +-- Location: FF_X43_Y12_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~113_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[5]~DUPLICATE_q\); + +-- Location: LABCELL_X44_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[5]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(8) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(6)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~6_combout\); + +-- Location: LABCELL_X43_Y12_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~121\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~121_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(9) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~102\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~122\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(9) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~102\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~102\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~121_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~122\); + +-- Location: FF_X43_Y12_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~121_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(9)); + +-- Location: LABCELL_X43_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~117\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~117_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(10) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~122\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~118\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(10) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~122\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~122\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~117_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~118\); + +-- Location: FF_X43_Y12_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~117_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(10)); + +-- Location: FF_X43_Y12_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~125_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[4]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y12_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[11]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~118\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[11]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~118\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[11]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~118\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~73_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~74\); + +-- Location: FF_X43_Y12_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~73_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[11]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y12_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[12]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~74\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[12]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~74\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[12]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~74\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~69_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~70\); + +-- Location: FF_X43_Y12_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~69_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[12]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y12_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(13) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~70\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(13) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~70\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(13), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~70\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~57_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~58\); + +-- Location: FF_X43_Y12_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~57_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(13)); + +-- Location: LABCELL_X43_Y12_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(14) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~58\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(14) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~58\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(14), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~58\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~53_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~54\); + +-- Location: FF_X43_Y12_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~53_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(14)); + +-- Location: LABCELL_X43_Y12_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[15]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~54\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[15]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~54\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[15]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~54\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~65_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~66\); + +-- Location: FF_X43_Y12_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[15]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~65_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[15]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y12_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[16]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~66\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[16]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~66\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[16]~DUPLICATE_q\, + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~66\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~61_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~62\); + +-- Location: FF_X43_Y12_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~61_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[16]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y12_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~97\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~97_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(17) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~62\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~98\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(17) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~62\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(17), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~62\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~97_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~98\); + +-- Location: FF_X43_Y12_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~97_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(17)); + +-- Location: LABCELL_X43_Y12_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~93_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(18) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~98\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~94\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(18) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~98\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(18), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~98\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~93_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~94\); + +-- Location: FF_X43_Y12_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~93_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(18)); + +-- Location: LABCELL_X43_Y12_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~89_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(19) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~94\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~90\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(19) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~94\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(19), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~94\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~89_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~90\); + +-- Location: FF_X43_Y12_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~89_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(19)); + +-- Location: LABCELL_X43_Y11_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(20) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~90\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(20) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~90\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(20), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~90\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~85_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~86\); + +-- Location: FF_X43_Y11_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~85_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(20)); + +-- Location: LABCELL_X43_Y11_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(21) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~86\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(21) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~86\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(21), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~86\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~81_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~82\); + +-- Location: FF_X43_Y11_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~81_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(21)); + +-- Location: LABCELL_X43_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(22) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~82\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(22) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~82\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(22), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~82\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~77_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~78\); + +-- Location: FF_X43_Y11_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~77_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(22)); + +-- Location: LABCELL_X43_Y11_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(23) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~78\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(23) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~78\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(23), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~78\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~49_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~50\); + +-- Location: FF_X43_Y11_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~49_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(23)); + +-- Location: LABCELL_X43_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(24) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~50\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(24) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~50\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(24), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~50\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~45_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~46\); + +-- Location: FF_X43_Y11_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~45_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(24)); + +-- Location: LABCELL_X43_Y11_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(25) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~46\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(25) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~46\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(25), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~46\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~34\); + +-- Location: FF_X43_Y11_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~33_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(25)); + +-- Location: LABCELL_X43_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(26) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(26) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(26), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~30\); + +-- Location: FF_X43_Y11_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(26)); + +-- Location: LABCELL_X43_Y11_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(27) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(27) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(27), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~42\); + +-- Location: FF_X43_Y11_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~41_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(27)); + +-- Location: LABCELL_X43_Y11_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(28) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(28) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(28), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~38\); + +-- Location: FF_X43_Y11_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~37_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(28)); + +-- Location: LABCELL_X43_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(24) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(28) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(27))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~1_combout\); + +-- Location: FF_X43_Y11_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[26]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[26]~DUPLICATE_q\); + +-- Location: FF_X44_Y12_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(2)); + +-- Location: LABCELL_X43_Y11_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(29) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(29) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(29), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~26\); + +-- Location: FF_X43_Y11_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(29)); + +-- Location: LABCELL_X43_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(30) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~26\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(30) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(30), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~22\); + +-- Location: FF_X43_Y11_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(30)); + +-- Location: LABCELL_X44_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(29) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(2) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(3)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~0_combout\); + +-- Location: FF_X43_Y11_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[25]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~33_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[25]~DUPLICATE_q\); + +-- Location: FF_X43_Y12_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~65_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(15)); + +-- Location: FF_X43_Y12_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~73_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(11)); + +-- Location: FF_X43_Y12_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~61_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(16)); + +-- Location: FF_X43_Y12_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~69_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(12)); + +-- Location: LABCELL_X44_Y12_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(15) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(11)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~2_combout\); + +-- Location: LABCELL_X43_Y11_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(21) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(20))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~3_combout\); + +-- Location: LABCELL_X44_Y12_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(17) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(18) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~4_combout\); + +-- Location: LABCELL_X44_Y11_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[26]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[25]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000100000000000000010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[26]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[25]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~5_combout\); + +-- Location: LABCELL_X44_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~5_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(9))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\); + +-- Location: LABCELL_X44_Y11_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(31)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_NIBBLECNT~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~0_combout\); + +-- Location: LABCELL_X44_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000011101010110000001110101011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~40_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT[2]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~1_combout\); + +-- Location: FF_X44_Y10_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector112~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(1)); + +-- Location: LABCELL_X44_Y10_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(0) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(2)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100010001010001000001000101000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector111~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~1_combout\); + +-- Location: FF_X44_Y10_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(2)); + +-- Location: LABCELL_X44_Y10_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010001000100010001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~37_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_SPLIT_DATA\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~0_combout\); + +-- Location: FF_X44_Y10_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~0_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(1)); + +-- Location: LABCELL_X44_Y10_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector113~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector113~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(0)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110111111111000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_SPLIT_DATA\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_SPLIT_DATA\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector113~0_combout\); + +-- Location: FF_X44_Y10_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector113~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(0)); + +-- Location: LABCELL_X44_Y10_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(0)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(0) $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(0))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(0)) # +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(0))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101111111111111100000000000000001101111010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_SPLIT_DATA\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_SPLIT_DATA\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0_combout\); + +-- Location: MLABCELL_X42_Y10_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100011111111100010001111111100001000000011110000100000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_NIBBLECNT~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~44_combout\); + +-- Location: LABCELL_X44_Y10_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001110000000000000111000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal2~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~40_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~45_combout\); + +-- Location: FF_X43_Y10_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~47_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y10_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~45_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~44_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001111000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector111~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~44_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~45_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\); + +-- Location: LABCELL_X41_Y10_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000000000000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_SPLITSPACE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~46_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~55_combout\); + +-- Location: FF_X41_Y10_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~55_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~q\); + +-- Location: MLABCELL_X42_Y10_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE\(0)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110111011000000000000000000001111111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal2~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_DATA_PRTMODE\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~34_combout\); + +-- Location: LABCELL_X41_Y10_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~34_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~34_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000111111000000000011111100000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_SPLITSPACE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~34_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~35_combout\); + +-- Location: LABCELL_X44_Y10_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~35_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~35_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111110101111000011111010111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~35_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~36_combout\); + +-- Location: FF_X44_Y10_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~36_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\); + +-- Location: LABCELL_X47_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\); + +-- Location: MLABCELL_X42_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~2_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000100000001100000010000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~1_combout\); + +-- Location: LABCELL_X43_Y11_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(31) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(31), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~1_sumout\); + +-- Location: MLABCELL_X42_Y11_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~1_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(31))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~1_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(31)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000001111110011110000111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector13~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~2_combout\); + +-- Location: FF_X42_Y11_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(31)); + +-- Location: LABCELL_X44_Y11_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(31) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\); + +-- Location: LABCELL_X43_Y10_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~30_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~30_combout\); + +-- Location: LABCELL_X43_Y10_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~38_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~37_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~38_combout\); + +-- Location: LABCELL_X44_Y10_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~38_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~30_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~38_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101000000000000010100000000000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~38_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~39_combout\); + +-- Location: FF_X44_Y10_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~39_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\); + +-- Location: LABCELL_X44_Y10_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100000000000100010000000000000001000000000000000100000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_NIBBLECNT~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector111~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~29_combout\); + +-- Location: FF_X41_Y10_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~53_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~q\); + +-- Location: LABCELL_X41_Y10_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010001000000000001000100000000101100011010000010110001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~46_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_CR~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_PRECR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~32_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~53_combout\); + +-- Location: FF_X41_Y10_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~53_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y10_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~60\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~60_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_SPACE~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000111111000000000011111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_SPACE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SPACE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~60_combout\); + +-- Location: LABCELL_X41_Y10_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~61_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~60_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SPACE~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~60_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SPACE~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000000000001010000001010101111101010101010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~46_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SPACE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~60_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~61_combout\); + +-- Location: FF_X41_Y10_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~61_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SPACE~q\); + +-- Location: LABCELL_X41_Y10_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~59_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010001000000000001000100000000101100011010000010110001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~46_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SEPERATOR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~59_combout\); + +-- Location: FF_X41_Y10_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~59_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\); + +-- Location: MLABCELL_X42_Y10_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SPACE~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001111111000000000111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_PRECR~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SPACE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SEPERATOR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~51_combout\); + +-- Location: LABCELL_X43_Y10_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~38_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~29_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~51_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~38_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~51_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111111111111001111111111111100111011101110110011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~29_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~51_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~38_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~52_combout\); + +-- Location: FF_X43_Y10_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~52_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\); + +-- Location: LABCELL_X43_Y10_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18~combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010000000001010101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~50_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18~combout\); + +-- Location: MLABCELL_X42_Y10_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18~combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010100001111000001010000111100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_WideOr18~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~1_combout\); + +-- Location: FF_X42_Y10_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~q\); + +-- Location: LABCELL_X41_Y9_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~33_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~33_sumout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101010100000000010101010000000000101010100000000010101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~33_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~3_combout\); + +-- Location: LABCELL_X41_Y9_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(2) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~25_sumout\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(3))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~25_sumout\ $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(3))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000010010000011000001001000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~21_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~4_combout\); + +-- Location: LABCELL_X40_Y9_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000001111111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\); + +-- Location: LABCELL_X41_Y9_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[0]~1_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111110000000011111111000000001111111100000000111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[11]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[0]~1_combout\); + +-- Location: FF_X41_Y9_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[0]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0)); + +-- Location: LABCELL_X41_Y9_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(2), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~6\); + +-- Location: FF_X41_Y9_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~5_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(2)); + +-- Location: LABCELL_X41_Y9_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~10\); + +-- Location: FF_X41_Y9_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~9_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(3)); + +-- Location: LABCELL_X41_Y9_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~14\); + +-- Location: FF_X41_Y9_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~13_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4)); + +-- Location: LABCELL_X41_Y9_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~18\); + +-- Location: FF_X41_Y9_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~17_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(5)); + +-- Location: LABCELL_X41_Y9_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(6), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~29_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~30\); + +-- Location: FF_X41_Y9_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6)); + +-- Location: LABCELL_X41_Y9_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~34\); + +-- Location: FF_X41_Y9_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~33_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7)); + +-- Location: LABCELL_X41_Y9_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~21_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~22\); + +-- Location: FF_X41_Y9_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(8)); + +-- Location: LABCELL_X41_Y9_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~22\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~22\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~22\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~38\); + +-- Location: FF_X41_Y9_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~37_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9)); + +-- Location: LABCELL_X41_Y9_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~42\); + +-- Location: FF_X41_Y9_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~41_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10)); + +-- Location: LABCELL_X41_Y9_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~25_sumout\); + +-- Location: FF_X41_Y9_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~25_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11)); + +-- Location: MLABCELL_X42_Y9_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~13_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11)) ) + ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~11\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000001010010110100101", + shared_arith => "on") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(11), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~10\, + sharein => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~11\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~13_sumout\); + +-- Location: MLABCELL_X42_Y9_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~13_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~9_sumout\) # ((!\myVirtualToplevel|RESET_n~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1_sumout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111111101111111111111110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~13_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~9_sumout\, + datac => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\); + +-- Location: LABCELL_X43_Y10_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~30_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31_combout\); + +-- Location: FF_X43_Y10_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_NEW_REG1142\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_OTERM1143\); + +-- Location: FF_X43_Y10_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG775\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM776\); + +-- Location: MLABCELL_X37_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE_NEW2170\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE_OTERM2171\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_SPACE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE_OTERM2171\); + +-- Location: FF_X37_Y25_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE_OTERM2171\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\); + +-- Location: FF_X52_Y28_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_SPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_SPACE~q\); + +-- Location: FF_X52_Y28_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_SPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_SPACE~q\); + +-- Location: FF_X43_Y28_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_SPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_SPACE~q\); + +-- Location: FF_X48_Y24_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_SPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_SPACE~q\); + +-- Location: LABCELL_X48_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_SPACE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~feeder_combout\); + +-- Location: FF_X48_Y24_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~q\); + +-- Location: LABCELL_X48_Y24_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_SPACE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~feeder_combout\); + +-- Location: FF_X48_Y24_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~q\); + +-- Location: LABCELL_X43_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_SPACE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~feeder_combout\); + +-- Location: FF_X43_Y27_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~q\); + +-- Location: LABCELL_X48_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~q\))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_SPACE~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000101001011111000110110001101101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_POST_SPACE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_POST_SPACE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_POST_SPACE~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_POST_SPACE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4_combout\); + +-- Location: FF_X43_Y28_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_SPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_SPACE~q\); + +-- Location: LABCELL_X52_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_SPACE~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_SPACE~q\))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_SPACE~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_SPACE~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000001111000000000000111111111111001100111111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_POST_SPACE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_POST_SPACE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_POST_SPACE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux3~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_POST_SPACE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~0_combout\); + +-- Location: FF_X43_Y10_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~24_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~q\); + +-- Location: LABCELL_X43_Y10_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~q\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100000101100011000000010110001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux3~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_POST_SPACE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~50_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~24_combout\); + +-- Location: FF_X43_Y10_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~24_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~DUPLICATE_q\); + +-- Location: FF_X43_Y10_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_NEW_REG871\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM872\); + +-- Location: LABCELL_X43_Y10_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~30_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000110000000000000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~56_combout\); + +-- Location: FF_X43_Y10_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG779\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~56_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM780\); + +-- Location: FF_X43_Y10_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG771\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM772\); + +-- Location: FF_X43_Y10_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_NEW_REG873\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~57_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM874\); + +-- Location: FF_X43_Y10_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_NEW_REG869\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM870\); + +-- Location: LABCELL_X43_Y10_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~57_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM874\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM870\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM872\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM776\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM780\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM872\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM776\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM780\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM772\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM874\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM870\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM872\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM772\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM874\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM870\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM776\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM780\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110000001100000000000000010101011100000011010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM872\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM776\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM780\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM772\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM874\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM870\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~57_combout\); + +-- Location: LABCELL_X32_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~2_combout\); + +-- Location: LABCELL_X32_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~1_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(4)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101000000000111110100000000011111010000000001111101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~1_combout\); + +-- Location: LABCELL_X31_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~3_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000100000000000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~3_combout\); + +-- Location: LABCELL_X32_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal149~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal149~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000111111110011001101010101111101011111111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~4_combout\); + +-- Location: LABCELL_X32_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF_NEW2172\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF_OTERM2173\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_CRLF~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF_OTERM2173\); + +-- Location: FF_X32_Y19_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF_OTERM2173\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\); + +-- Location: FF_X47_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_CRLF\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_CRLF~q\); + +-- Location: LABCELL_X48_Y16_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_CRLF~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~feeder_combout\); + +-- Location: FF_X48_Y16_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~q\); + +-- Location: LABCELL_X48_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_CRLF~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~feeder_combout\); + +-- Location: FF_X48_Y16_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~q\); + +-- Location: LABCELL_X47_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_CRLF~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~feeder_combout\); + +-- Location: FF_X47_Y16_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~q\); + +-- Location: LABCELL_X47_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2))))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~q\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2))))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_CRLF~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000101001011111000110110001101101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_POST_CRLF~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_POST_CRLF~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_POST_CRLF~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_POST_CRLF~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~4_combout\); + +-- Location: MLABCELL_X45_Y16_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_CRLF~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~feeder_combout\); + +-- Location: FF_X45_Y16_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~q\); + +-- Location: MLABCELL_X45_Y16_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_CRLF~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~feeder_combout\); + +-- Location: FF_X45_Y16_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~q\); + +-- Location: MLABCELL_X42_Y16_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_CRLF~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~feeder_combout\); + +-- Location: FF_X42_Y16_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~q\); + +-- Location: FF_X45_Y18_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_CRLF\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_CRLF~q\); + +-- Location: MLABCELL_X45_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~4_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_CRLF~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2))))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~4_combout\ & +-- ((((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~q\))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2))))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~4_combout\ & ((((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101010101010101010101010101010100011011000110110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux5~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_POST_CRLF~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_POST_CRLF~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_POST_CRLF~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_POST_CRLF~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~0_combout\); + +-- Location: LABCELL_X43_Y10_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF~q\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100000101100011000000010110001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux5~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_POST_CRLF~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~43_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~23_combout\); + +-- Location: FF_X43_Y10_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~23_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF~q\); + +-- Location: LABCELL_X43_Y10_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000000000000001100000000000101110001010000010111000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_POST_CRLF~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~46_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTCRLF~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~43_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~54_combout\); + +-- Location: FF_X43_Y10_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~54_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF~q\); + +-- Location: FF_X43_Y10_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG773\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM774\); + +-- Location: FF_X43_Y10_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG777\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~58_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM778\); + +-- Location: LABCELL_X43_Y10_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~58_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM772\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM780\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM776\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM778\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM774\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM772\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM780\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM776\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM778\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000000000001010000000110011101100110011001110110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM780\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM774\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM776\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM778\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM772\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~58_combout\); + +-- Location: LABCELL_X43_Y10_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000110000001100000011000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal2~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~50_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~48_combout\); + +-- Location: LABCELL_X43_Y10_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~57_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~58_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~57_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~58_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000101000000000100010100000000010101010000000001010101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~57_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~40_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~58_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~48_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~49_combout\); + +-- Location: FF_X43_Y10_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_NEW_REG1144\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~49_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_OTERM1145\); + +-- Location: LABCELL_X43_Y10_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM772\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_OTERM1145\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_OTERM1143\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM776\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM870\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM772\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_OTERM1143\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM776\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM870\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010001000000000001000100011110000111110001111000011111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_END_OTERM1143\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM776\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_END_OTERM1145\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM870\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM772\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50_combout\); + +-- Location: LABCELL_X43_Y10_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~50_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_POST_SPACE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43_combout\); + +-- Location: LABCELL_X43_Y10_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~1_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~q\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010110011111100101011001111110010101110111111111010111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~43_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~46_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_POST_CRLF~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~47_combout\); + +-- Location: FF_X43_Y10_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~47_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~q\); + +-- Location: LABCELL_X44_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~2_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000000000000011000000000000001100000000000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~2_combout\); + +-- Location: MLABCELL_X42_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111011110000000011101111000000001111111100010000111111110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~3_combout\); + +-- Location: FF_X42_Y18_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(2) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010110101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0_combout\); + +-- Location: MLABCELL_X42_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1001000010010000000010010000100100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~1_combout\); + +-- Location: LABCELL_X43_Y10_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\); + +-- Location: MLABCELL_X42_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110011110011000011001111001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~1_combout\); + +-- Location: FF_X42_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010100001001000010000010000000100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0_combout\); + +-- Location: MLABCELL_X42_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1659~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal1~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1659~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\); + +-- Location: FF_X42_Y18_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(0)); + +-- Location: MLABCELL_X42_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~3_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~3_combout\); + +-- Location: FF_X42_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1) $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1659~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111111100000000111111110000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1659~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal1~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~1_combout\); + +-- Location: FF_X42_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1)); + +-- Location: MLABCELL_X42_Y18_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\)))) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ $ +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001010010010001000101001001001000100000001000100010000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\); + +-- Location: LABCELL_X36_Y22_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ = ( !\myVirtualToplevel|RESET_n~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ ) ) # ( \myVirtualToplevel|RESET_n~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ ) +-- ) # ( !\myVirtualToplevel|RESET_n~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\); + +-- Location: LABCELL_X36_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~39_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~39_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugAllInfo~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~40_combout\); + +-- Location: FF_X36_Y24_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~40_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\); + +-- Location: LABCELL_X36_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000101000001010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\); + +-- Location: LABCELL_X17_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr195~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\); + +-- Location: LABCELL_X17_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\); + +-- Location: LABCELL_X21_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110000001100110000010000000100011101000011011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~52_combout\); + +-- Location: FF_X21_Y15_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~52_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\); + +-- Location: LABCELL_X12_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\); + +-- Location: LABCELL_X21_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~65_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "1111110111111100011101010011000011011101110011000111010100110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~65_combout\); + +-- Location: LABCELL_X21_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~65_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~65_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~0_combout\); + +-- Location: FF_X21_Y15_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\); + +-- Location: LABCELL_X12_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000000000010000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOS~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_NOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS_2~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\); + +-- Location: LABCELL_X17_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011001100110011000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr195~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\); + +-- Location: MLABCELL_X9_Y15_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7_combout\); + +-- Location: MLABCELL_X9_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector245~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector245~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010000000000000000010100000101000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr2~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector245~0_combout\); + +-- Location: MLABCELL_X9_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector245~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector245~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector245~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector245~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011101100111011001100000011000000111011001110110011101100110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector245~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~8_combout\); + +-- Location: FF_X9_Y15_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~8_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(0)); + +-- Location: LABCELL_X6_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Add2~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(0) ) + ( VCC ) + ( !VCC )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(0), + cin => GND, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~30\); + +-- Location: LABCELL_X6_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Add2~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(1) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~30\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(1) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~30\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(1), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~30\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~41_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~42\); + +-- Location: LABCELL_X7_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~41_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~11_combout\); + +-- Location: LABCELL_X5_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector244~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector244~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101011101010100000000000000000101010111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector244~0_combout\); + +-- Location: FF_X5_Y19_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector244~0_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~11_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(1)); + +-- Location: LABCELL_X6_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Add2~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(2) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~42\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(2) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~42\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(2), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~42\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~37_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~38\); + +-- Location: LABCELL_X6_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~37_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~37_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~10_combout\); + +-- Location: LABCELL_X5_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector243~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector243~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101011101010100000000000000000101010111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector243~0_combout\); + +-- Location: FF_X5_Y19_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector243~0_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~10_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(2)); + +-- Location: LABCELL_X6_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Add2~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~38\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~38\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(3), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~38\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~5_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~6\); + +-- Location: LABCELL_X7_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~1_combout\); + +-- Location: LABCELL_X5_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector242~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector242~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101011101010100000000000000000101010111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector242~0_combout\); + +-- Location: FF_X5_Y19_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector242~0_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(3)); + +-- Location: LABCELL_X6_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add2~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~6\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~6\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(4), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~6\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~1_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~2\); + +-- Location: LABCELL_X6_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~1_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~0_combout\); + +-- Location: LABCELL_X5_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector241~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector241~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101011101010100000000000000000101010111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector241~1_combout\); + +-- Location: FF_X5_Y19_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector241~1_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(4)); + +-- Location: LABCELL_X6_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Add2~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~2\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~2\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(5), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~2\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~13_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~14\); + +-- Location: LABCELL_X7_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~13_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~13_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~3_combout\); + +-- Location: LABCELL_X5_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector240~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector240~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101011101010100000000000000000101010111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector240~0_combout\); + +-- Location: FF_X5_Y19_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector240~0_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(5)); + +-- Location: LABCELL_X6_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Add2~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(6) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~14\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(6) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~14\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(6), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~14\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~17_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~18\); + +-- Location: LABCELL_X6_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~17_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~4_combout\); + +-- Location: LABCELL_X5_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector239~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector239~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101011101010100000000000000000101010111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector239~0_combout\); + +-- Location: FF_X5_Y19_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector239~0_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(6)); + +-- Location: LABCELL_X6_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Add2~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(7) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~18\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(7) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~18\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(7), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~18\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~33_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~34\); + +-- Location: LABCELL_X6_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~33_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~33_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~9_combout\); + +-- Location: LABCELL_X5_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector238~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector238~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101011101010100000000000000000101010111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector238~0_combout\); + +-- Location: FF_X5_Y19_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector238~0_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~9_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(7)); + +-- Location: LABCELL_X6_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Add2~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(8) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~34\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(8) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~34\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(8), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~34\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~9_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~10\); + +-- Location: LABCELL_X6_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~2_combout\); + +-- Location: LABCELL_X5_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector237~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector237~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101011101010100000000000000000101010111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector237~0_combout\); + +-- Location: FF_X5_Y19_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector237~0_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(8)); + +-- Location: LABCELL_X6_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Add2~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(9) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~10\ )) +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(9) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~10\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(9), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~10\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~25_sumout\, + cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~26\); + +-- Location: LABCELL_X7_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~25_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~25_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~6_combout\); + +-- Location: LABCELL_X5_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector236~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector236~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101011101010100000000000000000101010111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector236~0_combout\); + +-- Location: FF_X5_Y19_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector236~0_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(9)); + +-- Location: LABCELL_X6_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Add2~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add2~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(10) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~26\ )) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(10), + cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~26\, + sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add2~21_sumout\); + +-- Location: LABCELL_X7_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add2~21_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~5_combout\); + +-- Location: LABCELL_X5_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector235~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector235~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101011101010100000000000000000101010111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector235~0_combout\); + +-- Location: FF_X5_Y19_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector235~0_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(10)); + +-- Location: LABCELL_X6_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(6) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(5))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~0_combout\); + +-- Location: LABCELL_X6_Y19_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(7) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(1) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~1_combout\); + +-- Location: LABCELL_X6_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(8) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(4)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000000100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\); + +-- Location: LABCELL_X10_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\); + +-- Location: LABCELL_X10_Y14_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux14~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux14~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux14~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101101010101010111100000000000001011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~10_combout\); + +-- Location: FF_X10_Y14_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28)); + +-- Location: LABCELL_X20_Y11_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~2_combout\); + +-- Location: LABCELL_X17_Y9_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011001100110011001100001111000011110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2_combout\); + +-- Location: MLABCELL_X23_Y11_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn[21]~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\); + +-- Location: FF_X20_Y11_N25 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~2_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(28)); + +-- Location: MLABCELL_X18_Y8_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[12]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[12]~feeder_combout\); + +-- Location: LABCELL_X17_Y9_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110011001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4_combout\); + +-- Location: FF_X18_Y8_N37 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[12]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12), + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(12)); + +-- Location: LABCELL_X24_Y4_N3 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux175~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux175~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(12) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(28) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(28), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(12), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux175~0_combout\); + +-- Location: LABCELL_X20_Y8_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~20_combout\ = (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001010000010100000101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~20_combout\); + +-- Location: LABCELL_X20_Y8_N45 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~2_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~2_combout\); + +-- Location: LABCELL_X20_Y8_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~20_combout\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & \myVirtualToplevel|RESET_n~q\))) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\ & ( \myVirtualToplevel|RESET_n~q\ ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\ & ( \myVirtualToplevel|RESET_n~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000000000000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~20_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~2_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + datad => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuIsWriting~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\); + +-- Location: FF_X24_Y4_N5 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux175~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~reg0_q\); + +-- Location: LABCELL_X20_Y8_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~14_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000000000001010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~14_combout\); + +-- Location: LABCELL_X20_Y8_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~20_combout\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~14_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~20_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~14_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuIsWriting~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\); + +-- Location: LABCELL_X24_Y1_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~enfeeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~enfeeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~enfeeder_combout\); + +-- Location: FF_X24_Y1_N50 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~enfeeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~en_q\); + +-- Location: MLABCELL_X18_Y8_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[13]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[13]~feeder_combout\); + +-- Location: FF_X18_Y8_N22 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[13]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13), + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(13)); + +-- Location: LABCELL_X20_Y11_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~5_combout\); + +-- Location: FF_X20_Y11_N56 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~5_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(29)); + +-- Location: LABCELL_X24_Y4_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux176~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux176~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(13) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(29) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(13), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(29), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux176~0_combout\); + +-- Location: FF_X24_Y4_N23 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux176~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~reg0_q\); + +-- Location: FF_X24_Y1_N20 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~en_q\); + +-- Location: MLABCELL_X18_Y8_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[14]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[14]~feeder_combout\); + +-- Location: FF_X18_Y8_N49 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[14]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(14)); + +-- Location: LABCELL_X20_Y11_N3 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001110111011101110100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[14]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~6_combout\); + +-- Location: FF_X20_Y11_N4 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~6_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(30)); + +-- Location: LABCELL_X24_Y4_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux177~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux177~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(14) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(30) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(14), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(30), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux177~0_combout\); + +-- Location: FF_X24_Y4_N29 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux177~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~reg0_q\); + +-- Location: LABCELL_X24_Y1_N39 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~enfeeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~enfeeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~enfeeder_combout\); + +-- Location: FF_X24_Y1_N41 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~enfeeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~en_q\); + +-- Location: MLABCELL_X18_Y8_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[15]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[15]~feeder_combout\); + +-- Location: FF_X18_Y8_N52 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[15]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15), + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(15)); + +-- Location: MLABCELL_X13_Y14_N15 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001011101000010000101110100101010011111110010101001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(15), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~7_combout\); + +-- Location: FF_X13_Y14_N16 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~7_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(31)); + +-- Location: MLABCELL_X13_Y14_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux179~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux179~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(31) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(15)) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(31) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(15)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(15), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(31), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux179~0_combout\); + +-- Location: FF_X13_Y14_N23 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux179~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~reg0_q\); + +-- Location: LABCELL_X24_Y1_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~enfeeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~enfeeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~enfeeder_combout\); + +-- Location: FF_X24_Y1_N35 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~enfeeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~en_q\); + +-- Location: LABCELL_X17_Y9_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111110011111100111100001100000011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8_combout\); + +-- Location: FF_X23_Y11_N49 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(0)); + +-- Location: LABCELL_X17_Y8_N15 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[16]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[16]~feeder_combout\); + +-- Location: LABCELL_X17_Y9_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111110011111100111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1_combout\); + +-- Location: FF_X17_Y8_N16 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[16]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1_combout\, + sload => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(16)); + +-- Location: LABCELL_X24_Y4_N9 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux162~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux162~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(0) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(16) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(0), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(16), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux162~0_combout\); + +-- Location: FF_X24_Y4_N11 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux162~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~reg0_q\); + +-- Location: LABCELL_X24_Y1_N15 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~enfeeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~enfeeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~enfeeder_combout\); + +-- Location: FF_X24_Y1_N17 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~enfeeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~en_q\); + +-- Location: LABCELL_X17_Y8_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[17]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[17]~feeder_combout\); + +-- Location: FF_X17_Y8_N55 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[17]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1_combout\, + sload => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(17)); + +-- Location: MLABCELL_X23_Y11_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[1]~feeder_combout\); + +-- Location: FF_X23_Y11_N55 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[1]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(1)); + +-- Location: LABCELL_X24_Y4_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux164~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux164~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(1) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(17) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(17), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(1), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux164~0_combout\); + +-- Location: FF_X24_Y4_N53 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux164~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~reg0_q\); + +-- Location: FF_X24_Y4_N44 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~en_q\); + +-- Location: LABCELL_X17_Y8_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[18]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[18]~feeder_combout\); + +-- Location: FF_X17_Y8_N52 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[18]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1_combout\, + sload => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(18)); + +-- Location: MLABCELL_X23_Y11_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[2]~feeder_combout\); + +-- Location: FF_X23_Y11_N29 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[2]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(2)); + +-- Location: LABCELL_X24_Y4_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux165~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux165~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(2) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(18) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(18), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(2), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux165~0_combout\); + +-- Location: FF_X24_Y4_N37 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux165~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~reg0_q\); + +-- Location: LABCELL_X24_Y1_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~enfeeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~enfeeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~enfeeder_combout\); + +-- Location: FF_X24_Y1_N43 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~enfeeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~en_q\); + +-- Location: MLABCELL_X23_Y11_N9 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[3]~feeder_combout\); + +-- Location: FF_X23_Y11_N10 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[3]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(3)); + +-- Location: LABCELL_X17_Y8_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[19]~feeder_combout\); + +-- Location: FF_X17_Y8_N43 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[19]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1_combout\, + sload => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(19)); + +-- Location: LABCELL_X24_Y4_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux166~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux166~0_combout\ = (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(19)))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(3))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(3), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(19), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux166~0_combout\); + +-- Location: FF_X24_Y4_N32 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux166~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~reg0_q\); + +-- Location: LABCELL_X24_Y1_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~enfeeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~enfeeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~enfeeder_combout\); + +-- Location: FF_X24_Y1_N23 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~enfeeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~en_q\); + +-- Location: LABCELL_X17_Y8_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~feeder_combout\); + +-- Location: FF_X17_Y8_N1 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1_combout\, + sload => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(20)); + +-- Location: MLABCELL_X23_Y11_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[4]~feeder_combout\); + +-- Location: FF_X23_Y11_N1 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[4]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(4)); + +-- Location: LABCELL_X24_Y4_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux167~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux167~0_combout\ = (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(20))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(4)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100100010011101110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(20), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(4), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux167~0_combout\); + +-- Location: FF_X24_Y4_N35 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux167~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~reg0_q\); + +-- Location: LABCELL_X24_Y1_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~enfeeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~enfeeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~enfeeder_combout\); + +-- Location: FF_X24_Y1_N2 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~enfeeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~en_q\); + +-- Location: MLABCELL_X23_Y11_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[5]~feeder_combout\); + +-- Location: FF_X23_Y11_N22 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[5]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(5)); + +-- Location: LABCELL_X17_Y8_N21 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~feeder_combout\); + +-- Location: FF_X17_Y8_N22 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1_combout\, + sload => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(21)); + +-- Location: LABCELL_X24_Y4_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux168~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux168~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(5) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(21) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(5), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(21), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux168~0_combout\); + +-- Location: FF_X24_Y4_N13 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux168~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~reg0_q\); + +-- Location: LABCELL_X24_Y1_N9 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~enfeeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~enfeeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~enfeeder_combout\); + +-- Location: FF_X24_Y1_N10 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~enfeeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~en_q\); + +-- Location: MLABCELL_X23_Y11_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[6]~feeder_combout\); + +-- Location: FF_X23_Y11_N37 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[6]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(6)); + +-- Location: LABCELL_X17_Y8_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[22]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[22]~feeder_combout\); + +-- Location: FF_X17_Y8_N25 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[22]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1_combout\, + sload => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(22)); + +-- Location: MLABCELL_X18_Y8_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux169~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux169~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(22) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(6)) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(22) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(6)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(6), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(22), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux169~0_combout\); + +-- Location: FF_X18_Y8_N26 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux169~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~reg0_q\); + +-- Location: LABCELL_X19_Y1_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~enfeeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~enfeeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~enfeeder_combout\); + +-- Location: FF_X19_Y1_N14 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~enfeeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~en_q\); + +-- Location: MLABCELL_X23_Y11_N45 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[7]~feeder_combout\); + +-- Location: FF_X23_Y11_N46 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[7]~feeder_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(7)); + +-- Location: LABCELL_X17_Y8_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[23]~feeder_combout\); + +-- Location: FF_X17_Y8_N28 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[23]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1_combout\, + sload => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(23)); + +-- Location: MLABCELL_X18_Y8_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux170~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux170~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(23) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(7)) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(23) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(7)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(7), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(23), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux170~0_combout\); + +-- Location: FF_X18_Y8_N29 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux170~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~reg0_q\); + +-- Location: LABCELL_X19_Y1_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~enfeeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~enfeeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~enfeeder_combout\); + +-- Location: FF_X19_Y1_N56 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~enfeeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~en_q\); + +-- Location: MLABCELL_X13_Y14_N45 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110001101000001011000110100100111101011110010011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(8), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~9_combout\); + +-- Location: FF_X13_Y14_N46 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~9_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(24)); + +-- Location: LABCELL_X14_Y14_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~feeder_combout\); + +-- Location: FF_X14_Y14_N52 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8), + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(8)); + +-- Location: MLABCELL_X13_Y14_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux171~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux171~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(8) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(24)) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(8) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(24) & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(24), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(8), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux171~0_combout\); + +-- Location: FF_X13_Y14_N53 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux171~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~reg0_q\); + +-- Location: LABCELL_X19_Y1_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~enfeeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~enfeeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~enfeeder_combout\); + +-- Location: FF_X19_Y1_N53 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~enfeeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~en_q\); + +-- Location: MLABCELL_X18_Y8_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[9]~feeder_combout\); + +-- Location: FF_X18_Y8_N55 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[9]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(9)); + +-- Location: MLABCELL_X13_Y14_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001010111000000100101011110001010110111111000101011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(25), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~10_combout\); + +-- Location: FF_X13_Y14_N13 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~10_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(25)); + +-- Location: MLABCELL_X13_Y14_N57 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux172~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux172~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(25) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(9) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(25) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(25) & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(9) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111111111111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(9), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(25), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux172~0_combout\); + +-- Location: FF_X13_Y14_N59 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux172~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~reg0_q\); + +-- Location: LABCELL_X24_Y1_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~enfeeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~enfeeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~enfeeder_combout\); + +-- Location: FF_X24_Y1_N28 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~enfeeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~en_q\); + +-- Location: MLABCELL_X13_Y14_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110001101000001011000110100100111101011110010011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(10), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~11_combout\); + +-- Location: FF_X13_Y14_N1 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~11_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(26)); + +-- Location: MLABCELL_X18_Y8_N57 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[10]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[10]~feeder_combout\); + +-- Location: FF_X18_Y8_N58 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[10]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10), + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(10)); + +-- Location: MLABCELL_X13_Y14_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux173~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux173~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(10) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(26)) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(10) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(26) & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(26), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(10), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux173~0_combout\); + +-- Location: FF_X13_Y14_N26 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux173~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~reg0_q\); + +-- Location: FF_X24_Y1_N14 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~en_q\); + +-- Location: LABCELL_X14_Y14_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[11]~feeder_combout\); + +-- Location: FF_X14_Y14_N50 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[11]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11), + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(11)); + +-- Location: MLABCELL_X13_Y14_N3 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010000010000010101001011101011111110101110101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~12_combout\); + +-- Location: FF_X13_Y14_N4 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~12_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(27)); + +-- Location: MLABCELL_X13_Y14_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux174~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux174~0_combout\ = (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(27)))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(11))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(11), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(27), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux174~0_combout\); + +-- Location: FF_X13_Y14_N29 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux174~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~reg0_q\); + +-- Location: LABCELL_X24_Y1_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~enfeeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~enfeeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~enfeeder_combout\); + +-- Location: FF_X24_Y1_N56 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~enfeeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~en_q\); + +-- Location: LABCELL_X41_Y9_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~25_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~21_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~25_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~21_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000010010000100100001001000010000100001001000010010000100100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~21_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~6_combout\); + +-- Location: LABCELL_X40_Y9_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~13_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) $ +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~13_sumout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000100001000000000000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~13_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~17_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~7_combout\); + +-- Location: LABCELL_X40_Y9_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~1_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~1_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~1_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~1_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011000000110000001100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~0_combout\, + datab => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO~21_combout\); + +-- Location: LABCELL_X43_Y9_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA[0]~0_combout\ = ( \myVirtualToplevel|RESET_n~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_2~0_combout\, + dataf => \myVirtualToplevel|ALT_INV_RESET_n~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA[0]~0_combout\); + +-- Location: MLABCELL_X42_Y10_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_WideOr18~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\); + +-- Location: MLABCELL_X23_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100110011000100010001001100010001001100110001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\); + +-- Location: LABCELL_X21_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[30]_NEW2156\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[30]_OTERM2157\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[30]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[30]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[30]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(30), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[30]_OTERM2157\); + +-- Location: FF_X21_Y17_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[30]_OTERM2157\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30)); + +-- Location: LABCELL_X25_Y12_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[30]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[30]~feeder_combout\); + +-- Location: FF_X25_Y12_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(30)); + +-- Location: FF_X24_Y12_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(30)); + +-- Location: FF_X24_Y12_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(30)); + +-- Location: LABCELL_X24_Y12_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[30]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[30]~feeder_combout\); + +-- Location: FF_X24_Y12_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(30)); + +-- Location: LABCELL_X24_Y12_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(30) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(30))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(30))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(30) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(30) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(30))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(30)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(30) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(30) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(30))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(30)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(30) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(30) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(30))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(30)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011111101011111001100000101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(30), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(30), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~1_combout\); + +-- Location: FF_X26_Y10_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(30)); + +-- Location: LABCELL_X26_Y10_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[30]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[30]~feeder_combout\); + +-- Location: FF_X26_Y10_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(30)); + +-- Location: LABCELL_X25_Y10_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[30]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[30]~feeder_combout\); + +-- Location: FF_X25_Y10_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(30)); + +-- Location: FF_X26_Y10_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(30)); + +-- Location: LABCELL_X26_Y10_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(30))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(30)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(30))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(30)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(30)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(30) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(30)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(30), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(30), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(30), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~0_combout\); + +-- Location: LABCELL_X29_Y10_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux347~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux347~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~2_combout\); + +-- Location: FF_X29_Y10_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(30)); + +-- Location: LABCELL_X43_Y11_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(31) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000101000001010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(31), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~2_combout\); + +-- Location: MLABCELL_X42_Y11_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100001111111111110000011100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DECODED_OPCODE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31_combout\); + +-- Location: LABCELL_X36_Y11_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~31_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\); + +-- Location: LABCELL_X40_Y11_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\); + +-- Location: LABCELL_X24_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN8819\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN8819_BDD8820\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~17_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~13_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~21_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN8819_BDD8820\); + +-- Location: LABCELL_X26_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_RESYN12786\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_RESYN12786_BDD12787\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~37_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~9_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~29_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~33_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_RESYN12786_BDD12787\); + +-- Location: LABCELL_X31_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|pc~163\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN8819_BDD8820\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_RESYN12786_BDD12787\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN8819_BDD8820\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_RESYN12786_BDD12787\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN8819_BDD8820\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_RESYN12786_BDD12787\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN8819_BDD8820\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_RESYN12786_BDD12787\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001010000011110000101000001111000010100000111100001011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~160_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_RESYN8819_BDD8820\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_RESYN12786_BDD12787\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\); + +-- Location: LABCELL_X32_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111111111100001111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~1_combout\); + +-- Location: LABCELL_X26_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_RESYN9163\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_RESYN9163_BDD9164\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~49_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_RESYN9163_BDD9164\); + +-- Location: LABCELL_X26_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_RESYN9163_BDD9164\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_RESYN9163_BDD9164\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110010000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~45_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~33_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~37_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~13_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~12_RESYN9163_BDD9164\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_combout\); + +-- Location: LABCELL_X25_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~21_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~17_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~21_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~9_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~21_combout\); + +-- Location: LABCELL_X31_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~21_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~21_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\)) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~21_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~21_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~1_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001000000010000000100000001000000010000000100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~21_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\); + +-- Location: LABCELL_X31_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011000000110000001100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\); + +-- Location: LABCELL_X39_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001111001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\); + +-- Location: LABCELL_X39_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~1_combout\); + +-- Location: LABCELL_X41_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110100000001110011011111000100111101001100011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][0]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~0_combout\); + +-- Location: MLABCELL_X34_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13338\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13338_BDD13339\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011000000100001001111001110110111111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1536~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1536~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13338_BDD13339\); + +-- Location: MLABCELL_X34_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13340\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13338_BDD13339\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13338_BDD13339\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100101111001011110010111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[32]_NEW2545_RESYN13338_BDD13339\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(32), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\); + +-- Location: MLABCELL_X34_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_OTERM2546\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(32), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_OTERM2546\); + +-- Location: FF_X34_Y34_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_OTERM2546\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32)); + +-- Location: FF_X49_Y27_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(32)); + +-- Location: LABCELL_X41_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0_combout\ & ( (\myVirtualToplevel|RESET_n~q\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1659~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000001010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1659~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal1~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Decoder0~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\); + +-- Location: FF_X44_Y26_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(32)); + +-- Location: FF_X44_Y26_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(32)); + +-- Location: FF_X44_Y26_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(32)); + +-- Location: LABCELL_X44_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(32)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(32))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(32)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(32))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(32)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(32) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(32)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(32), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(32), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(32), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(32), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~0_combout\); + +-- Location: FF_X48_Y27_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(32)); + +-- Location: FF_X49_Y27_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(32)); + +-- Location: FF_X48_Y27_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(32)); + +-- Location: FF_X49_Y27_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(32)); + +-- Location: LABCELL_X48_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(32) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(32))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(32))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(32) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(32) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(32)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(32) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(32) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(32) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(32))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(32) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(32))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(32)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000000001001110101010100100111101010100010011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(32), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(32), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(32), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(32), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~1_combout\); + +-- Location: LABCELL_X48_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux189~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux189~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~2_combout\); + +-- Location: FF_X48_Y27_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(32)); + +-- Location: LABCELL_X39_Y36_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~0_combout\); + +-- Location: LABCELL_X40_Y37_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~2_combout\); + +-- Location: LABCELL_X32_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011100000110000001110000011010001111100011100000011100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~3_combout\); + +-- Location: LABCELL_X32_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010001000100010011001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~4_combout\); + +-- Location: FF_X32_Y23_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG354\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM355\); + +-- Location: FF_X32_Y23_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG352\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM353\); + +-- Location: FF_X32_Y23_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG224\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\); + +-- Location: FF_X32_Y23_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG346\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM347\); + +-- Location: LABCELL_X20_Y13_N0 +\myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_162\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_163\ = ( !\myVirtualToplevel|MEM_DATA_READ[0]~94_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ +-- & ((\myVirtualToplevel|IO_DATA_READ_SD\(0)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[0]~94_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8~portbdataout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ +-- & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|IO_DATA_READ_SD\(0)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000011101110011000001110100110011000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]~34_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_combout\, + dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(0), + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_163\); + +-- Location: MLABCELL_X23_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\ = ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch~q\ & +-- (\myVirtualToplevel|RESET_n~q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000010000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_MemoryFetch~q\, + datab => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\); + +-- Location: FF_X20_Y13_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_163\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(0)); + +-- Location: FF_X31_Y25_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG350\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(0), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM351\); + +-- Location: LABCELL_X32_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM347\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM351\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM347\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM351\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM355\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM349\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM353\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM347\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM351\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM355\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM347\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM351\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM355\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM349\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM353\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010001010101000000000101010101010100010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM355\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM349\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM353\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM225\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM347\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM351\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1_combout\); + +-- Location: FF_X36_Y20_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(32)); + +-- Location: FF_X37_Y18_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(32)); + +-- Location: FF_X36_Y20_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(32)); + +-- Location: FF_X36_Y20_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(32)); + +-- Location: LABCELL_X36_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(32)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(32) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(32) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(32))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(32)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(32))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(32)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(32), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(32), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(32), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(32), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~1_combout\); + +-- Location: FF_X39_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(32)); + +-- Location: FF_X39_Y16_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(32)); + +-- Location: FF_X40_Y16_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(32)); + +-- Location: FF_X39_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(32)); + +-- Location: LABCELL_X39_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(32)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(32) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(32)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(32))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(32)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(32))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(32)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(32), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(32), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(32), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(32), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~0_combout\); + +-- Location: MLABCELL_X42_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux61~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux61~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~2_combout\); + +-- Location: FF_X42_Y23_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(32)); + +-- Location: FF_X34_Y26_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG318\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\); + +-- Location: LABCELL_X35_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111111100000000111111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\); + +-- Location: FF_X36_Y33_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_NEW_REG448\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM449\); + +-- Location: LABCELL_X32_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011111111111111111100001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\); + +-- Location: LABCELL_X35_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\))))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000100010001000001010001000100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1478~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~0_combout\); + +-- Location: FF_X35_Y26_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_NEW_REG464\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM465\); + +-- Location: LABCELL_X36_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111111111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\); + +-- Location: LABCELL_X40_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux404~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux404~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux404~0_combout\); + +-- Location: FF_X40_Y37_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_NEW_REG462\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux404~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM463\); + +-- Location: LABCELL_X40_Y37_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~1_combout\); + +-- Location: FF_X40_Y37_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_NEW_REG466\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM467\); + +-- Location: LABCELL_X43_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM463\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM467\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM465\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM463\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM467\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM449\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM465\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM463\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM467\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM449\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM465\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM463\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM467\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM465\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000111110001111101001111010011110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM449\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM465\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM463\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM467\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\); + +-- Location: FF_X47_Y23_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(32)); + +-- Location: MLABCELL_X49_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[32]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[32]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1478~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[32]~feeder_combout\); + +-- Location: FF_X49_Y22_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[32]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(32)); + +-- Location: LABCELL_X52_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[32]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[32]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1478~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[32]~feeder_combout\); + +-- Location: FF_X52_Y21_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[32]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(32)); + +-- Location: FF_X47_Y23_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(32)); + +-- Location: LABCELL_X47_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(32)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(32) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(32) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(32))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(32)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(32))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(32)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(32), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(32), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(32), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(32), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~1_combout\); + +-- Location: LABCELL_X52_Y21_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[32]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[32]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1478~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[32]~feeder_combout\); + +-- Location: FF_X52_Y21_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[32]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(32)); + +-- Location: LABCELL_X43_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[32]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[32]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1478~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[32]~feeder_combout\); + +-- Location: FF_X43_Y23_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[32]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(32)); + +-- Location: MLABCELL_X45_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[32]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[32]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1478~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[32]~feeder_combout\); + +-- Location: FF_X45_Y22_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[32]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(32)); + +-- Location: FF_X42_Y23_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(32)); + +-- Location: MLABCELL_X42_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(32))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(32)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(32))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(32)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(32)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(32) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(32) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(32), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(32), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(32), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(32), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~0_combout\); + +-- Location: MLABCELL_X42_Y23_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux125~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux125~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~2_combout\); + +-- Location: FF_X42_Y23_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(32)); + +-- Location: LABCELL_X36_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001111001100001100111100110011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\); + +-- Location: MLABCELL_X34_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010110101010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\); + +-- Location: LABCELL_X25_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000000011111111111111111111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\); + +-- Location: LABCELL_X36_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\); + +-- Location: LABCELL_X29_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\); + +-- Location: LABCELL_X41_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011110011111100111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~6_combout\); + +-- Location: LABCELL_X36_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000011111111111111111111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\); + +-- Location: LABCELL_X41_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~7_combout\); + +-- Location: LABCELL_X41_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~8_combout\); + +-- Location: LABCELL_X41_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~5_combout\); + +-- Location: MLABCELL_X42_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~6_combout\))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~6_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~6_combout\)))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101010001101000011111000100001011010110111010101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~9_combout\); + +-- Location: LABCELL_X41_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~2_combout\); + +-- Location: LABCELL_X41_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~0_combout\); + +-- Location: LABCELL_X41_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~1_combout\); + +-- Location: LABCELL_X41_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~3_combout\); + +-- Location: LABCELL_X41_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13090\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~0_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~2_combout\)))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101100010011100110100100011011001111010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\); + +-- Location: MLABCELL_X42_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13092\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000101010100011101001010101001101011111111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(32), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\); + +-- Location: MLABCELL_X42_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_OTERM2403\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(32), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_OTERM2403\); + +-- Location: FF_X42_Y27_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_OTERM2403\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32)); + +-- Location: FF_X42_Y24_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(32)); + +-- Location: FF_X42_Y24_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(32)); + +-- Location: FF_X43_Y24_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(32)); + +-- Location: FF_X42_Y24_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(32)); + +-- Location: MLABCELL_X42_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(32)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(32) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(32)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(32)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(32))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(32)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(32))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(32), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(32), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(32), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(32), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~1_combout\); + +-- Location: LABCELL_X43_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[32]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[32]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(32), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[32]~feeder_combout\); + +-- Location: FF_X43_Y25_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[32]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(32)); + +-- Location: FF_X43_Y23_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(32)); + +-- Location: FF_X43_Y23_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(32)); + +-- Location: FF_X42_Y23_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(32)); + +-- Location: MLABCELL_X42_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(32) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(32)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(32) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(32) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(32)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(32))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(32) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(32)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(32))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(32), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(32), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(32), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(32), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~0_combout\); + +-- Location: MLABCELL_X42_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux253~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux253~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~2_combout\); + +-- Location: FF_X42_Y23_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(32)); + +-- Location: MLABCELL_X42_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector76~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector76~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(32) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(32) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(32) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(32) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(32), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(32), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(32), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(32), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector76~0_combout\); + +-- Location: MLABCELL_X23_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[0]_NEW2012\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[0]_OTERM2013\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(0)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[0]_OTERM2013\); + +-- Location: FF_X23_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[0]_OTERM2013\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(0)); + +-- Location: FF_X25_Y12_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(0)); + +-- Location: LABCELL_X24_Y12_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[0]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[0]~feeder_combout\); + +-- Location: FF_X24_Y12_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(0)); + +-- Location: FF_X24_Y12_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(0)); + +-- Location: FF_X24_Y12_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(0)); + +-- Location: LABCELL_X24_Y12_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(0) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(0)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(0)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(0)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000101010001001010010111101110000011110100111010101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~1_combout\); + +-- Location: LABCELL_X25_Y12_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[0]~feeder_combout\); + +-- Location: FF_X25_Y12_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(0)); + +-- Location: LABCELL_X26_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[0]~feeder_combout\); + +-- Location: FF_X26_Y11_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(0)); + +-- Location: FF_X26_Y11_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(0)); + +-- Location: FF_X24_Y14_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(0)); + +-- Location: LABCELL_X26_Y11_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(0) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000010001001111110001000100001100110111010011111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~0_combout\); + +-- Location: LABCELL_X29_Y10_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux409~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux409~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~2_combout\); + +-- Location: FF_X29_Y10_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(0)); + +-- Location: FF_X18_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~1_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~89_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(0)); + +-- Location: LABCELL_X20_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[0]_NEW2014\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[0]_OTERM2015\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[0]_OTERM2015\); + +-- Location: FF_X20_Y16_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[0]_OTERM2015\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0)); + +-- Location: FF_X25_Y12_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(0)); + +-- Location: LABCELL_X24_Y12_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[0]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[0]~feeder_combout\); + +-- Location: FF_X24_Y12_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(0)); + +-- Location: FF_X25_Y12_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(0)); + +-- Location: FF_X24_Y12_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(0)); + +-- Location: LABCELL_X25_Y12_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(0) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(0)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001001010111010100101010011110100010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~1_combout\); + +-- Location: FF_X26_Y11_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(0)); + +-- Location: FF_X28_Y10_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(0)); + +-- Location: LABCELL_X25_Y12_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[0]~feeder_combout\); + +-- Location: FF_X25_Y12_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(0)); + +-- Location: FF_X28_Y10_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(0)); + +-- Location: MLABCELL_X28_Y10_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~0_combout\); + +-- Location: LABCELL_X29_Y10_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux377~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux377~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~2_combout\); + +-- Location: FF_X29_Y10_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(0)); + +-- Location: LABCELL_X29_Y10_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~46\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(0) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~46_combout\); + +-- Location: LABCELL_X36_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~47\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~47_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~46_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector76~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~46_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector76~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111100101111000000000000000011101110001000100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector76~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector42~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_SP~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~46_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~47_combout\); + +-- Location: FF_X45_Y11_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\); + +-- Location: LABCELL_X44_Y11_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~50\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(31)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101010100000000110101010000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(31), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~50_combout\); + +-- Location: FF_X44_Y11_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_NEW_REG803\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~50_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\); + +-- Location: FF_X50_Y11_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_NEW_REG865\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM866\); + +-- Location: FF_X50_Y11_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_NEW_REG1099\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1100\); + +-- Location: FF_X45_Y11_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_NEW_REG801\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802\); + +-- Location: FF_X45_Y11_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_NEW_REG1103\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1104\); + +-- Location: FF_X49_Y11_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_NEW_REG861\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM862\); + +-- Location: FF_X49_Y11_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_NEW_REG857\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM858\); + +-- Location: FF_X50_Y11_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_NEW_REG841\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM842\); + +-- Location: FF_X50_Y11_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_NEW_REG849\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM850\); + +-- Location: FF_X48_Y11_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_NEW_REG805\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM806\); + +-- Location: FF_X47_Y11_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_NEW_REG813\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM814\); + +-- Location: FF_X48_Y11_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_NEW_REG809\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM810\); + +-- Location: FF_X48_Y11_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_NEW_REG817\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM818\); + +-- Location: LABCELL_X41_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000101001100001111010100111111000001010011111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~1_combout\); + +-- Location: LABCELL_X41_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111111110101010100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~0_combout\); + +-- Location: LABCELL_X41_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13274\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~1_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100000101010001010110101110101011101011111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1564~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1564~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\); + +-- Location: FF_X40_Y35_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_OTERM2498\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(0)); + +-- Location: LABCELL_X40_Y35_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13276\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(0) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101111111101010101000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\); + +-- Location: LABCELL_X40_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_OTERM2498\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011110111001111111100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_OTERM2498\); + +-- Location: FF_X40_Y35_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_OTERM2498\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y16_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[0]~feeder_combout\); + +-- Location: FF_X43_Y16_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(0)); + +-- Location: LABCELL_X43_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[0]~feeder_combout\); + +-- Location: FF_X43_Y16_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(0)); + +-- Location: FF_X43_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(0)); + +-- Location: MLABCELL_X45_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[0]~feeder_combout\); + +-- Location: FF_X45_Y24_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(0)); + +-- Location: LABCELL_X43_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(0) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(0)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000000001001111010101000100111010101010010011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~0_combout\); + +-- Location: FF_X50_Y29_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(0)); + +-- Location: MLABCELL_X45_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[0]~feeder_combout\); + +-- Location: FF_X45_Y24_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(0)); + +-- Location: FF_X50_Y29_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(0)); + +-- Location: FF_X50_Y29_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(0)); + +-- Location: LABCELL_X50_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(0))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(0))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~1_combout\); + +-- Location: LABCELL_X50_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux221~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux221~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~2_combout\); + +-- Location: FF_X50_Y17_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(0)); + +-- Location: MLABCELL_X37_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110010001001110111001000100111001001110010011100100111001001110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\); + +-- Location: LABCELL_X36_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\); + +-- Location: LABCELL_X39_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000011110000111100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\); + +-- Location: LABCELL_X41_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~8_combout\); + +-- Location: LABCELL_X41_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\))) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~7_combout\); + +-- Location: LABCELL_X41_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~6_combout\); + +-- Location: MLABCELL_X37_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111110111110101111101011111010100101000101000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\); + +-- Location: LABCELL_X41_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110111010101000011011010101010001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~5_combout\); + +-- Location: LABCELL_X41_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~7_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~6_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~7_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111000000000101010100100111001001111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~9_combout\); + +-- Location: LABCELL_X21_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add40~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add40~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add40~0_combout\); + +-- Location: LABCELL_X24_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Add40~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) $ +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add40~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101010100000000010101010000001011111111101010101111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add40~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\); + +-- Location: LABCELL_X41_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~2_combout\); + +-- Location: LABCELL_X41_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~3_combout\); + +-- Location: LABCELL_X41_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~1_combout\); + +-- Location: LABCELL_X41_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~0_combout\); + +-- Location: LABCELL_X41_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12878\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001111110101000000110000010111110011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\); + +-- Location: MLABCELL_X37_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12880\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~9_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~9_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010101000000110000000001010011010101011111001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\); + +-- Location: MLABCELL_X37_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_OTERM2281\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011110111001111111100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_OTERM2281\); + +-- Location: FF_X37_Y31_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_OTERM2281\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0)); + +-- Location: LABCELL_X53_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[0]~feeder_combout\); + +-- Location: FF_X53_Y15_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(0)); + +-- Location: FF_X53_Y19_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(0)); + +-- Location: FF_X53_Y19_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(0)); + +-- Location: FF_X53_Y19_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(0)); + +-- Location: LABCELL_X53_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~0_combout\); + +-- Location: FF_X49_Y19_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(0)); + +-- Location: LABCELL_X53_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[0]~feeder_combout\); + +-- Location: FF_X53_Y15_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(0)); + +-- Location: FF_X49_Y19_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(0)); + +-- Location: FF_X49_Y19_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(0)); + +-- Location: MLABCELL_X49_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(0))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(0))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~1_combout\); + +-- Location: LABCELL_X50_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux285~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux285~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~2_combout\); + +-- Location: FF_X50_Y17_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(0)); + +-- Location: MLABCELL_X34_Y22_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101010101010100000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~0_combout\); + +-- Location: FF_X34_Y22_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321~DUPLICATE_q\); + +-- Location: FF_X35_Y22_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG316\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM317\); + +-- Location: FF_X37_Y26_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG322\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM323\); + +-- Location: LABCELL_X41_Y36_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux432~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~2_combout\); + +-- Location: LABCELL_X41_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux432~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~3_combout\); + +-- Location: LABCELL_X41_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux432~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~1_combout\); + +-- Location: LABCELL_X41_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux432~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~0_combout\); + +-- Location: LABCELL_X40_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux432~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~3_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~4_combout\); + +-- Location: FF_X40_Y36_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG324\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM325\); + +-- Location: MLABCELL_X37_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM323\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM325\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM317\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM323\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM325\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM317\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM323\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM325\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM317\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM323\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM325\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM317\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000001000010011000100110000111011001110110111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM321~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM317\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM323\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM325\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\); + +-- Location: LABCELL_X52_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[0]~feeder_combout\); + +-- Location: FF_X52_Y18_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(0)); + +-- Location: LABCELL_X50_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[0]~feeder_combout\); + +-- Location: FF_X50_Y18_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(0)); + +-- Location: FF_X45_Y19_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(0)); + +-- Location: FF_X50_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(0)); + +-- Location: LABCELL_X50_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~0_combout\); + +-- Location: LABCELL_X47_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[0]~feeder_combout\); + +-- Location: FF_X47_Y21_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(0)); + +-- Location: LABCELL_X39_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[0]~feeder_combout\); + +-- Location: FF_X39_Y26_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(0)); + +-- Location: FF_X44_Y21_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(0)); + +-- Location: LABCELL_X50_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1508~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[0]~feeder_combout\); + +-- Location: FF_X50_Y18_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(0)); + +-- Location: LABCELL_X44_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(0) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(0) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100111101001100011100110111000001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~1_combout\); + +-- Location: LABCELL_X50_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111111111111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux157~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux157~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~2_combout\); + +-- Location: FF_X50_Y17_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(0)); + +-- Location: LABCELL_X50_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN~100\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN~100_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(0)))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(0)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001101100000000000110110000000000011011111111110001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA2~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA4~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(0), + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN~100_combout\); + +-- Location: LABCELL_X32_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~feeder_combout\); + +-- Location: FF_X32_Y26_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG438\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\); + +-- Location: FF_X31_Y27_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_NEW_REG580\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM581\); + +-- Location: FF_X28_Y26_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_NEW_REG586\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~93_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM587\); + +-- Location: FF_X35_Y24_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG332\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\); + +-- Location: FF_X41_Y26_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_NEW_REG588\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM589\); + +-- Location: LABCELL_X41_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000011000001011111001111110101000000111111010111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][0]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~2_combout\); + +-- Location: LABCELL_X41_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~0_combout\); + +-- Location: LABCELL_X40_Y36_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000101010101010101000000000101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~3_combout\); + +-- Location: FF_X40_Y36_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_NEW_REG590\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM591\); + +-- Location: LABCELL_X41_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM589\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM591\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM589\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM591\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM589\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM591\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM581\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM587\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM589\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM591\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM581\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM587\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000000000000010101010111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM581\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM587\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM333\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM589\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM591\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\); + +-- Location: LABCELL_X47_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[0]~feeder_combout\); + +-- Location: FF_X47_Y19_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(0)); + +-- Location: FF_X50_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(0)); + +-- Location: FF_X45_Y20_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(0)); + +-- Location: FF_X50_Y20_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(0)); + +-- Location: LABCELL_X50_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~0_combout\); + +-- Location: FF_X45_Y15_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(0)); + +-- Location: FF_X50_Y15_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(0)); + +-- Location: LABCELL_X47_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[0]~feeder_combout\); + +-- Location: FF_X47_Y19_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(0)); + +-- Location: FF_X50_Y15_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(0)); + +-- Location: LABCELL_X50_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~1_combout\); + +-- Location: LABCELL_X50_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux93~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux93~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~2_combout\); + +-- Location: FF_X50_Y17_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(0)); + +-- Location: LABCELL_X43_Y11_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[0]~89\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[0]~89_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000001000000010000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~40_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal2~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[0]~89_combout\); + +-- Location: FF_X50_Y17_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN~100_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(0), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[0]~89_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(0)); + +-- Location: LABCELL_X29_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\); + +-- Location: LABCELL_X29_Y27_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111110000000001111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\); + +-- Location: LABCELL_X31_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000101010101000100010100000101000001000100010001000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\); + +-- Location: LABCELL_X31_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101100001010000010100000101100001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\); + +-- Location: MLABCELL_X34_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_RESYN9299\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_RESYN9299_BDD9300\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_RESYN9299_BDD9300\); + +-- Location: MLABCELL_X34_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_RESYN9299_BDD9300\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_RESYN9299_BDD9300\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001110101011101110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_RESYN9299_BDD9300\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\); + +-- Location: FF_X17_Y31_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~30_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\); + +-- Location: FF_X17_Y31_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\); + +-- Location: FF_X23_Y28_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~22_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\); + +-- Location: LABCELL_X44_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9047\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9047_BDD9048\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000011110011001111111111010101010000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9047_BDD9048\); + +-- Location: FF_X18_Y31_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~15_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\); + +-- Location: FF_X18_Y31_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~16_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\); + +-- Location: LABCELL_X36_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9045\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9045_BDD9046\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100110101011100010011010101111001101111011111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9045_BDD9046\); + +-- Location: LABCELL_X36_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9049\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9049_BDD9050\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9045_BDD9046\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9047_BDD9048\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9045_BDD9046\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9047_BDD9048\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9045_BDD9046\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9047_BDD9048\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9045_BDD9046\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9047_BDD9048\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000001111111011100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9047_BDD9048\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9045_BDD9046\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9049_BDD9050\); + +-- Location: LABCELL_X35_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9049_BDD9050\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9049_BDD9050\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9049_BDD9050\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9049_BDD9050\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100000000001100110000110011011101110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9049_BDD9050\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_combout\); + +-- Location: LABCELL_X35_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[8]_NEW3235\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[8]_OTERM3236\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011111100001111001100001111000000111111111111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~37_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[8]_OTERM3236\); + +-- Location: FF_X35_Y27_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[8]_OTERM3236\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8)); + +-- Location: LABCELL_X47_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[8]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[8]~feeder_combout\); + +-- Location: FF_X47_Y16_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(8)); + +-- Location: FF_X48_Y12_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(8)); + +-- Location: FF_X48_Y12_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(8)); + +-- Location: FF_X48_Y12_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(8)); + +-- Location: LABCELL_X48_Y12_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(8)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(8)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(8)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~1_combout\); + +-- Location: LABCELL_X53_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[8]~feeder_combout\); + +-- Location: FF_X53_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(8)); + +-- Location: LABCELL_X47_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[8]~feeder_combout\); + +-- Location: FF_X47_Y19_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(8)); + +-- Location: LABCELL_X53_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[8]~feeder_combout\); + +-- Location: FF_X53_Y17_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(8)); + +-- Location: FF_X53_Y17_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(8)); + +-- Location: LABCELL_X53_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(8)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(8)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(8)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111101000100011101110100010001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~0_combout\); + +-- Location: LABCELL_X52_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux85~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux85~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~2_combout\); + +-- Location: FF_X52_Y17_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(8)); + +-- Location: MLABCELL_X42_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010111110101111101011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\); + +-- Location: LABCELL_X36_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111111001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\); + +-- Location: MLABCELL_X42_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~3_combout\); + +-- Location: LABCELL_X40_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\); + +-- Location: FF_X18_Y31_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\); + +-- Location: FF_X18_Y31_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~0_combout\); + +-- Location: LABCELL_X40_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\); + +-- Location: FF_X18_Y31_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\); + +-- Location: FF_X18_Y31_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~2_combout\); + +-- Location: MLABCELL_X42_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~1_combout\); + +-- Location: MLABCELL_X42_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~1_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~2_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000011011101110000001101000100110011110111011111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~4_combout\); + +-- Location: FF_X17_Y31_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~31_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~6_combout\); + +-- Location: FF_X17_Y31_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~27_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~5_combout\); + +-- Location: FF_X21_Y31_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\); + +-- Location: FF_X17_Y31_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~23_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\); + +-- Location: LABCELL_X44_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~7_combout\); + +-- Location: FF_X23_Y28_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~21_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\); + +-- Location: FF_X23_Y28_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]_OTERM1851\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~8_combout\); + +-- Location: MLABCELL_X42_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~6_combout\))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\) +-- # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~6_combout\))) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~6_combout\)))) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~6_combout\)))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011010001010110011110001001101010111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~9_combout\); + +-- Location: MLABCELL_X42_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12938\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12938_BDD12939\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010011000000000101001110101100111111111010110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12938_BDD12939\); + +-- Location: LABCELL_X41_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12940\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12938_BDD12939\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12938_BDD12939\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[8]_NEW2310_RESYN12938_BDD12939\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\); + +-- Location: LABCELL_X41_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_OTERM2311\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8) +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_OTERM2311\); + +-- Location: FF_X41_Y27_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_OTERM2311\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8)); + +-- Location: FF_X49_Y25_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(8)); + +-- Location: FF_X49_Y25_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(8)); + +-- Location: FF_X47_Y25_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(8)); + +-- Location: FF_X49_Y25_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(8)); + +-- Location: MLABCELL_X49_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(8) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(8))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(8))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~1_combout\); + +-- Location: FF_X47_Y25_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(8)); + +-- Location: LABCELL_X52_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[8]~feeder_combout\); + +-- Location: FF_X52_Y26_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(8)); + +-- Location: LABCELL_X52_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[8]~feeder_combout\); + +-- Location: FF_X52_Y26_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(8)); + +-- Location: FF_X52_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(8)); + +-- Location: LABCELL_X52_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(8)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(8))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(8))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~0_combout\); + +-- Location: LABCELL_X52_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux213~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux213~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~2_combout\); + +-- Location: FF_X52_Y25_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(8)); + +-- Location: LABCELL_X44_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~6_combout\); + +-- Location: LABCELL_X44_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~7_combout\); + +-- Location: LABCELL_X43_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~8_combout\); + +-- Location: LABCELL_X43_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~5_combout\); + +-- Location: LABCELL_X44_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~7_combout\)) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~8_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~7_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~9_combout\); + +-- Location: LABCELL_X40_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~2_combout\); + +-- Location: LABCELL_X40_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~0_combout\); + +-- Location: MLABCELL_X37_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010101110110000101000010001010111111011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~1_combout\); + +-- Location: LABCELL_X40_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~3_combout\); + +-- Location: LABCELL_X40_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12942\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~3_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~0_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010011000011110101001111110000010100111111111101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\); + +-- Location: LABCELL_X43_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12944\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~9_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001011101000011000000110000101010011111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\); + +-- Location: LABCELL_X43_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_OTERM2313\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8) +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101110101001010101000101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_OTERM2313\); + +-- Location: FF_X43_Y28_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_OTERM2313\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8)); + +-- Location: LABCELL_X47_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[8]~feeder_combout\); + +-- Location: FF_X47_Y24_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(8)); + +-- Location: FF_X48_Y24_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(8)); + +-- Location: FF_X48_Y24_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(8)); + +-- Location: LABCELL_X48_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[8]~feeder_combout\); + +-- Location: FF_X48_Y24_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(8)); + +-- Location: LABCELL_X48_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(8) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(8))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(8) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(8) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(8) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(8))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(8)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100110000111101010011111100000101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~1_combout\); + +-- Location: FF_X48_Y23_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(8)); + +-- Location: FF_X49_Y23_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(8)); + +-- Location: FF_X48_Y23_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(8)); + +-- Location: FF_X49_Y23_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(8)); + +-- Location: LABCELL_X48_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(8) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(8))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(8))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(8))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(8)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(8))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(8)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(8) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(8)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010011000111000001111111010000110100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~0_combout\); + +-- Location: LABCELL_X48_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000000000000001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux277~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux277~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~2_combout\); + +-- Location: FF_X48_Y23_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(8)); + +-- Location: LABCELL_X43_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~1_combout\); + +-- Location: LABCELL_X39_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000000011110011001101010101111111110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~0_combout\); + +-- Location: LABCELL_X40_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12934\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12934_BDD12935\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011010100000101001100001100000011110101110001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1500~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1500~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12934_BDD12935\); + +-- Location: FF_X40_Y35_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_OTERM2309\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(8)); + +-- Location: LABCELL_X40_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12936\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(8) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12934_BDD12935\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(8) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12934_BDD12935\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000101000011110000010100001111101011110000111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]_NEW2308_RESYN12934_BDD12935\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\); + +-- Location: LABCELL_X40_Y35_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_OTERM2309\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000001101110111111101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_OTERM2309\); + +-- Location: FF_X40_Y35_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_OTERM2309\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE_q\); + +-- Location: LABCELL_X48_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[8]~feeder_combout\); + +-- Location: FF_X48_Y26_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(8)); + +-- Location: MLABCELL_X49_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[8]~feeder_combout\); + +-- Location: FF_X49_Y29_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(8)); + +-- Location: MLABCELL_X49_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[8]~feeder_combout\); + +-- Location: FF_X49_Y29_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(8)); + +-- Location: FF_X49_Y29_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(8)); + +-- Location: MLABCELL_X49_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(8)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(8)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(8)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~0_combout\); + +-- Location: LABCELL_X50_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[8]~feeder_combout\); + +-- Location: FF_X50_Y29_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(8)); + +-- Location: LABCELL_X50_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[8]~feeder_combout\); + +-- Location: FF_X50_Y30_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(8)); + +-- Location: LABCELL_X50_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[8]~feeder_combout\); + +-- Location: FF_X50_Y29_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(8)); + +-- Location: FF_X50_Y29_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(8)); + +-- Location: LABCELL_X50_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(8) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(8)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(8)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~1_combout\); + +-- Location: LABCELL_X52_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux149~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux149~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~2_combout\); + +-- Location: FF_X52_Y25_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(8)); + +-- Location: LABCELL_X52_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(8))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(8))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(8)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~0_combout\); + +-- Location: LABCELL_X43_Y11_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(31) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(31) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111000001110000011100001111111100000000000000000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~40_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\); + +-- Location: FF_X23_Y32_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]_OTERM1845\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\); + +-- Location: MLABCELL_X34_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~q\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001111110101000000110000010111110011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~8_combout\); + +-- Location: MLABCELL_X34_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~7_combout\); + +-- Location: FF_X29_Y32_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~235_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\); + +-- Location: MLABCELL_X34_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~6_combout\); + +-- Location: MLABCELL_X34_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~5_combout\); + +-- Location: MLABCELL_X34_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~7_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~7_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~7_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001001100010000110100111101110000011111000111001101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~9_combout\); + +-- Location: LABCELL_X31_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~DUPLICATE_q\) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111100001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~3_combout\); + +-- Location: LABCELL_X35_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~1_combout\); + +-- Location: LABCELL_X35_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~2_combout\); + +-- Location: LABCELL_X35_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~0_combout\); + +-- Location: LABCELL_X32_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12874\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~1_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~0_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~1_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~1_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010010011000110111000011001001110110101110101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\); + +-- Location: LABCELL_X35_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12876\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~9_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~9_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011110111000001000000010000000100111101111111011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\); + +-- Location: LABCELL_X35_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_OTERM2279\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011111111110111001100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_OTERM2279\); + +-- Location: FF_X35_Y29_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_OTERM2279\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2)); + +-- Location: FF_X48_Y26_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(2)); + +-- Location: FF_X47_Y26_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(2)); + +-- Location: FF_X47_Y26_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(2)); + +-- Location: FF_X47_Y26_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(2)); + +-- Location: LABCELL_X47_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(2)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~0_combout\); + +-- Location: LABCELL_X53_Y26_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[2]~feeder_combout\); + +-- Location: FF_X53_Y26_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(2)); + +-- Location: MLABCELL_X49_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[2]~feeder_combout\); + +-- Location: FF_X49_Y25_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(2)); + +-- Location: FF_X50_Y25_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(2)); + +-- Location: FF_X53_Y26_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(2)); + +-- Location: LABCELL_X53_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(2)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~1_combout\); + +-- Location: LABCELL_X53_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux283~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux283~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~2_combout\); + +-- Location: FF_X53_Y26_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(2)); + +-- Location: FF_X29_Y31_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~q\); + +-- Location: LABCELL_X29_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111001111110011111100110111001111110011011100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\); + +-- Location: LABCELL_X29_Y31_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101110011001100110101001100110011011100110011001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR:tInsnExec~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~2_combout\); + +-- Location: LABCELL_X32_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001101000000001100110100000000110111010000000011011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\); + +-- Location: FF_X29_Y31_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG308\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM309\); + +-- Location: LABCELL_X35_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303~feeder_combout\); + +-- Location: FF_X35_Y28_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG302\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303\); + +-- Location: LABCELL_X32_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~0_combout\); + +-- Location: FF_X32_Y31_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG306\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM307\); + +-- Location: LABCELL_X35_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000101001111110000010100110000111101010011111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~1_combout\); + +-- Location: FF_X35_Y28_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG310\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM311\); + +-- Location: LABCELL_X35_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1_RTM0314\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1_RTM0314~combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1_RTM0314~combout\); + +-- Location: FF_X35_Y28_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG312\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1_RTM0314~combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM313\); + +-- Location: FF_X35_Y28_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG304\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM305\); + +-- Location: LABCELL_X35_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM313\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM305\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM309\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM313\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM305\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM307\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM313\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM305\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM309\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM313\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM305\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM311\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111110111011101110100001111000011111101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM309\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM303\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM307\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM311\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM313\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM305\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\); + +-- Location: FF_X45_Y26_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(2)); + +-- Location: FF_X45_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(2)); + +-- Location: LABCELL_X44_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[2]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1506~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[2]~feeder_combout\); + +-- Location: FF_X44_Y26_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(2)); + +-- Location: FF_X45_Y26_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(2)); + +-- Location: MLABCELL_X45_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(2)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~0_combout\); + +-- Location: FF_X44_Y27_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(2)); + +-- Location: FF_X36_Y27_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(2)); + +-- Location: LABCELL_X48_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1506~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[2]~feeder_combout\); + +-- Location: FF_X48_Y27_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(2)); + +-- Location: FF_X48_Y27_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(2)); + +-- Location: LABCELL_X48_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(2))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(2))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~1_combout\); + +-- Location: LABCELL_X47_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux155~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux155~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~2_combout\); + +-- Location: FF_X47_Y24_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(2)); + +-- Location: LABCELL_X32_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0_combout\); + +-- Location: MLABCELL_X28_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\)))) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110010000000001111001000000000111100100000000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\); + +-- Location: FF_X34_Y28_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG376\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\); + +-- Location: FF_X34_Y28_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG374\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375\); + +-- Location: LABCELL_X32_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~0_combout\); + +-- Location: FF_X34_Y28_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG378\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM379\); + +-- Location: MLABCELL_X28_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110000111111111111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~2_combout\); + +-- Location: MLABCELL_X28_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001101100011011000100010001101110110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~3_combout\); + +-- Location: FF_X28_Y29_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG382\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM383\); + +-- Location: MLABCELL_X34_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101011101110000010100100010101011110111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~1_combout\); + +-- Location: FF_X34_Y28_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG380\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM381\); + +-- Location: MLABCELL_X34_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM381\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM383\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM379\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM381\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM383\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM379\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM377\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM375\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM379\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM383\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM381\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\); + +-- Location: LABCELL_X52_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[2]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[2]~feeder_combout\); + +-- Location: FF_X52_Y28_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(2)); + +-- Location: LABCELL_X52_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[2]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[2]~feeder_combout\); + +-- Location: FF_X52_Y28_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(2)); + +-- Location: LABCELL_X52_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[2]~feeder_combout\); + +-- Location: FF_X52_Y29_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(2)); + +-- Location: FF_X52_Y28_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(2)); + +-- Location: LABCELL_X52_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(2)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~0_combout\); + +-- Location: FF_X49_Y27_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(2)); + +-- Location: LABCELL_X48_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[2]~feeder_combout\); + +-- Location: FF_X48_Y27_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(2)); + +-- Location: FF_X48_Y27_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(2)); + +-- Location: LABCELL_X36_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[2]~feeder_combout\); + +-- Location: FF_X36_Y27_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(2)); + +-- Location: LABCELL_X48_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(2) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(2) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(2)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(2))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101010000111100110101111100000011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~1_combout\); + +-- Location: LABCELL_X48_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux91~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux91~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~2_combout\); + +-- Location: FF_X48_Y27_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(2)); + +-- Location: LABCELL_X35_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000000111111001111110101111101010000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~1_combout\); + +-- Location: LABCELL_X32_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100111111111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~0_combout\); + +-- Location: MLABCELL_X34_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13266\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13266_BDD13267\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011000000100001001111001110110111111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1562~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1562~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13266_BDD13267\); + +-- Location: MLABCELL_X34_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13268\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13266_BDD13267\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13266_BDD13267\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011011101000000001101110100100010111111110010001011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[2]_NEW2491_RESYN13266_BDD13267\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\); + +-- Location: MLABCELL_X34_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_OTERM2492\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2) +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_OTERM2492\); + +-- Location: FF_X34_Y34_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_OTERM2492\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2)); + +-- Location: FF_X47_Y26_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(2)); + +-- Location: FF_X47_Y26_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(2)); + +-- Location: FF_X48_Y26_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(2)); + +-- Location: FF_X47_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(2)); + +-- Location: LABCELL_X47_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(2))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(2))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~0_combout\); + +-- Location: LABCELL_X52_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[2]~feeder_combout\); + +-- Location: FF_X52_Y25_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(2)); + +-- Location: LABCELL_X50_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[2]~feeder_combout\); + +-- Location: FF_X50_Y25_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(2)); + +-- Location: FF_X50_Y25_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(2)); + +-- Location: LABCELL_X50_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[2]~feeder_combout\); + +-- Location: FF_X50_Y25_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(2)); + +-- Location: LABCELL_X50_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(2) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(2)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(2)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(2)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010000110010011101101001100011011100101110101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~1_combout\); + +-- Location: LABCELL_X50_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010110101010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux219~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux219~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~2_combout\); + +-- Location: FF_X50_Y22_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(2)); + +-- Location: LABCELL_X50_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~91\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~91_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(2) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(2) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(2))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011010001110100011111001111110011110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA2~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~91_combout\); + +-- Location: MLABCELL_X28_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000110110001101101010101111111110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~2_combout\); + +-- Location: MLABCELL_X42_Y35_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101000011110000000000110011010101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~0_combout\); + +-- Location: LABCELL_X41_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000110000001100110000001100000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~3_combout\); + +-- Location: FF_X41_Y26_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_NEW_REG584\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM585\); + +-- Location: FF_X31_Y26_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_NEW_REG578\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM579\); + +-- Location: FF_X41_Y26_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_NEW_REG582\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM583\); + +-- Location: LABCELL_X41_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM583\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM585\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM583\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM585\ +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM583\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM579\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM581\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM585\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM583\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM579\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM581\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM585\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110111001100110011011100110011001100110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM585\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM579\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM581\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM583\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM333\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\); + +-- Location: MLABCELL_X49_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[1]~feeder_combout\); + +-- Location: FF_X49_Y19_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(1)); + +-- Location: MLABCELL_X49_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[1]~feeder_combout\); + +-- Location: FF_X49_Y19_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(1)); + +-- Location: LABCELL_X48_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[1]~feeder_combout\); + +-- Location: FF_X48_Y19_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(1)); + +-- Location: FF_X48_Y19_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(1)); + +-- Location: LABCELL_X48_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(1))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(1))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~1_combout\); + +-- Location: LABCELL_X48_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[1]~feeder_combout\); + +-- Location: FF_X48_Y19_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(1)); + +-- Location: FF_X53_Y19_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(1)); + +-- Location: FF_X53_Y19_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(1)); + +-- Location: FF_X53_Y19_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(1)); + +-- Location: LABCELL_X53_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(1)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~0_combout\); + +-- Location: LABCELL_X48_Y15_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux92~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux92~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~2_combout\); + +-- Location: FF_X48_Y15_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(1)); + +-- Location: MLABCELL_X37_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101001100000011111111110101111101010011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~1_combout\); + +-- Location: LABCELL_X35_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010001110111011101110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\); + +-- Location: MLABCELL_X42_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001001100010000110100111101110000011111000111001101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~0_combout\); + +-- Location: LABCELL_X36_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ +-- & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111000001001100011111000100001101110011010011110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~2_combout\); + +-- Location: LABCELL_X36_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[1]_NEW2276\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[1]_OTERM2277\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[62]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[1]_OTERM2277\); + +-- Location: FF_X36_Y23_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[1]_OTERM2277\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(1)); + +-- Location: FF_X41_Y12_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(1)); + +-- Location: LABCELL_X43_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[1]~feeder_combout\); + +-- Location: FF_X43_Y13_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(1)); + +-- Location: FF_X41_Y12_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(1)); + +-- Location: FF_X41_Y12_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(1)); + +-- Location: LABCELL_X41_Y12_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(1))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(1))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~1_combout\); + +-- Location: FF_X48_Y14_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(1)); + +-- Location: MLABCELL_X42_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[1]~feeder_combout\); + +-- Location: FF_X42_Y14_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(1)); + +-- Location: FF_X47_Y14_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(1)); + +-- Location: FF_X47_Y14_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(1)); + +-- Location: LABCELL_X47_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(1))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000011010001001100111101110111000000110111011111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~0_combout\); + +-- Location: LABCELL_X43_Y14_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000000000000001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux156~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux156~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~2_combout\); + +-- Location: FF_X43_Y14_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(1)); + +-- Location: MLABCELL_X37_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101001100000011000000000101111101010011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~0_combout\); + +-- Location: MLABCELL_X42_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111000001010000010100110000001111111111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~1_combout\); + +-- Location: LABCELL_X41_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13262\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13262_BDD13263\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~0_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110101000000000011010111111111001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1563~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1563~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13262_BDD13263\); + +-- Location: FF_X40_Y35_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_OTERM2489\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(1)); + +-- Location: LABCELL_X40_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13264\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(1) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13262_BDD13263\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13262_BDD13263\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110101000000001111010100001010111111110000101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]_NEW2488_RESYN13262_BDD13263\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\); + +-- Location: LABCELL_X40_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_OTERM2489\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001011111101001111111100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_OTERM2489\); + +-- Location: FF_X40_Y35_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_OTERM2489\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE_q\); + +-- Location: LABCELL_X53_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[1]~feeder_combout\); + +-- Location: FF_X53_Y28_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(1)); + +-- Location: LABCELL_X52_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[1]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[1]~feeder_combout\); + +-- Location: FF_X52_Y28_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(1)); + +-- Location: LABCELL_X52_Y28_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[1]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[1]~feeder_combout\); + +-- Location: FF_X52_Y28_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(1)); + +-- Location: FF_X52_Y28_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(1)); + +-- Location: LABCELL_X52_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(1))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(1))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~0_combout\); + +-- Location: FF_X48_Y27_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(1)); + +-- Location: MLABCELL_X49_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[1]~feeder_combout\); + +-- Location: FF_X49_Y25_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(1)); + +-- Location: MLABCELL_X49_Y25_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[1]~feeder_combout\); + +-- Location: FF_X49_Y25_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(1)); + +-- Location: FF_X49_Y25_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(1)); + +-- Location: MLABCELL_X49_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(1)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~1_combout\); + +-- Location: LABCELL_X48_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~2_combout\); + +-- Location: LABCELL_X48_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[1]~feeder_combout\); + +-- Location: FF_X48_Y23_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(1)); + +-- Location: LABCELL_X47_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~94\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~94_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(1))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(1))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010011000000110101001110100011111100111010001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~94_combout\); + +-- Location: FF_X37_Y34_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_OTERM2275\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(1)); + +-- Location: MLABCELL_X37_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000010101010011001100001111111111110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~8_combout\); + +-- Location: FF_X25_Y33_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~294_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\); + +-- Location: MLABCELL_X37_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~6_combout\); + +-- Location: MLABCELL_X37_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~5_combout\); + +-- Location: MLABCELL_X37_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~7_combout\); + +-- Location: MLABCELL_X37_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~6_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~7_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~8_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~5_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~6_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000011011101110000001101000100110011110111011111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~9_combout\); + +-- Location: MLABCELL_X37_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~3_combout\); + +-- Location: MLABCELL_X37_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~2_combout\); + +-- Location: LABCELL_X35_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~1_combout\); + +-- Location: LABCELL_X39_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~0_combout\); + +-- Location: MLABCELL_X37_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12870\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~2_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~2_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~2_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010111110011000001010000001111110101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\); + +-- Location: MLABCELL_X37_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12872\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(1))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(1))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111010001000000001111000000011101110111010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\); + +-- Location: MLABCELL_X37_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_OTERM2275\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001101111111011101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_OTERM2275\); + +-- Location: FF_X37_Y34_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_OTERM2275\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE_q\); + +-- Location: FF_X48_Y22_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(1)); + +-- Location: FF_X49_Y22_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(1)); + +-- Location: FF_X49_Y22_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(1)); + +-- Location: FF_X48_Y22_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(1)); + +-- Location: MLABCELL_X49_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(1) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(1) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110111010101000011011010101010001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~1_combout\); + +-- Location: FF_X43_Y25_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(1)); + +-- Location: FF_X45_Y23_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(1)); + +-- Location: FF_X48_Y23_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(1)); + +-- Location: LABCELL_X48_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[1]~feeder_combout\); + +-- Location: FF_X48_Y23_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(1)); + +-- Location: LABCELL_X48_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(1)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(1)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110100001010100011111000100001011101010110101101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~0_combout\); + +-- Location: LABCELL_X48_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux284~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux284~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~2_combout\); + +-- Location: FF_X48_Y23_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(1)); + +-- Location: MLABCELL_X45_Y12_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100000000000000000011001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90_combout\); + +-- Location: LABCELL_X47_Y11_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~95\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~95_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~94_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~94_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~90_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~95_combout\); + +-- Location: LABCELL_X44_Y11_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~96\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~96_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~95_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~95_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~95_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~96_combout\); + +-- Location: FF_X44_Y11_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~96_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(1)); + +-- Location: LABCELL_X47_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~92\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~92_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~91_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(2))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[2]~91_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~90_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~92_combout\); + +-- Location: LABCELL_X47_Y11_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~93\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~93_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~92_combout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[2]~92_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~93_combout\); + +-- Location: FF_X47_Y11_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~93_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2)); + +-- Location: LABCELL_X31_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101101011111010111100010001101110110001000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~5_combout\); + +-- Location: MLABCELL_X28_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~8_combout\); + +-- Location: LABCELL_X31_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101101010101111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~6_combout\); + +-- Location: MLABCELL_X28_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111110011001100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~7_combout\); + +-- Location: LABCELL_X32_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~5_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000100111001101101000110110011100101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~9_combout\); + +-- Location: FF_X35_Y29_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_OTERM2271\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(3)); + +-- Location: LABCELL_X32_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~2_combout\); + +-- Location: LABCELL_X32_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~1_combout\); + +-- Location: LABCELL_X32_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~3_combout\); + +-- Location: LABCELL_X35_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~0_combout\); + +-- Location: LABCELL_X35_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12866\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\))) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) +-- # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~1_combout\)))) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001000110100010101100111000010011010101111001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\); + +-- Location: LABCELL_X35_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12868\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(3))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~9_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(3))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110101001100000011000000101010011111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\); + +-- Location: LABCELL_X35_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_OTERM2271\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011111101111111001100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_OTERM2271\); + +-- Location: FF_X35_Y29_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_OTERM2271\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE_q\); + +-- Location: LABCELL_X53_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[3]~feeder_combout\); + +-- Location: FF_X53_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(3)); + +-- Location: LABCELL_X53_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[3]~feeder_combout\); + +-- Location: FF_X53_Y18_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(3)); + +-- Location: LABCELL_X53_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[3]~feeder_combout\); + +-- Location: FF_X53_Y20_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(3)); + +-- Location: FF_X53_Y18_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(3)); + +-- Location: LABCELL_X53_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(3))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(3))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(3)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010010101011111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~0_combout\); + +-- Location: FF_X49_Y19_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(3)); + +-- Location: LABCELL_X48_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[3]~feeder_combout\); + +-- Location: FF_X48_Y22_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(3)); + +-- Location: FF_X49_Y19_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(3)); + +-- Location: FF_X49_Y19_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(3)); + +-- Location: MLABCELL_X49_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(3)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(3))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(3))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~1_combout\); + +-- Location: LABCELL_X52_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux282~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux282~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~2_combout\); + +-- Location: FF_X52_Y17_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(3)); + +-- Location: LABCELL_X26_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9067\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9067_BDD9068\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101011111111101010101111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9067_BDD9068\); + +-- Location: LABCELL_X26_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9069\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9069_BDD9070\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9069_BDD9070\); + +-- Location: LABCELL_X24_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9071\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9071_BDD9072\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9067_BDD9068\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9069_BDD9070\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9067_BDD9068\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9069_BDD9070\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9067_BDD9068\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9069_BDD9070\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000111111111111111000000001111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9067_BDD9068\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9069_BDD9070\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9071_BDD9072\); + +-- Location: LABCELL_X35_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9071_BDD9072\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9071_BDD9072\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9071_BDD9072\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9071_BDD9072\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100010001000100010000110111001101110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9071_BDD9072\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_combout\); + +-- Location: LABCELL_X35_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[3]_NEW3225\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[3]_OTERM3226\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(3))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~45_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[3]_OTERM3226\); + +-- Location: FF_X35_Y27_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[3]_OTERM3226\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(3)); + +-- Location: LABCELL_X52_Y18_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[3]~feeder_combout\); + +-- Location: FF_X52_Y18_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(3)); + +-- Location: LABCELL_X53_Y18_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[3]~feeder_combout\); + +-- Location: FF_X53_Y18_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(3)); + +-- Location: FF_X53_Y18_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(3)); + +-- Location: FF_X53_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(3)); + +-- Location: LABCELL_X53_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(3))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(3))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~0_combout\); + +-- Location: LABCELL_X52_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[3]~feeder_combout\); + +-- Location: FF_X52_Y18_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(3)); + +-- Location: FF_X52_Y19_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(3)); + +-- Location: MLABCELL_X49_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[3]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(3) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[3]~feeder_combout\); + +-- Location: FF_X49_Y19_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(3)); + +-- Location: FF_X52_Y19_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(3)); + +-- Location: LABCELL_X52_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(3)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(3)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(3)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~1_combout\); + +-- Location: LABCELL_X52_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux90~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux90~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~2_combout\); + +-- Location: FF_X52_Y19_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(3)); + +-- Location: LABCELL_X31_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~1_combout\); + +-- Location: LABCELL_X32_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000000000111111001101011111010111110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~0_combout\); + +-- Location: LABCELL_X31_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13270\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13270_BDD13271\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111000000000010011111111111001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1561~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1561~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13270_BDD13271\); + +-- Location: MLABCELL_X42_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13272\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13270_BDD13271\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13270_BDD13271\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110011000000001111001100001100111111110000110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[3]_NEW2494_RESYN13270_BDD13271\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\); + +-- Location: MLABCELL_X42_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_OTERM2495\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011111101111111001100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_OTERM2495\); + +-- Location: FF_X42_Y27_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_OTERM2495\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3)); + +-- Location: FF_X47_Y28_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(3)); + +-- Location: LABCELL_X48_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[3]~feeder_combout\); + +-- Location: FF_X48_Y28_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(3)); + +-- Location: LABCELL_X47_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[3]~feeder_combout\); + +-- Location: FF_X47_Y28_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(3)); + +-- Location: FF_X47_Y28_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(3)); + +-- Location: LABCELL_X47_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(3)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~0_combout\); + +-- Location: FF_X44_Y28_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(3)); + +-- Location: FF_X44_Y28_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(3)); + +-- Location: FF_X44_Y28_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(3)); + +-- Location: FF_X45_Y28_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(3)); + +-- Location: MLABCELL_X45_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(3))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(3))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~1_combout\); + +-- Location: MLABCELL_X45_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux218~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux218~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~2_combout\); + +-- Location: FF_X45_Y28_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(3)); + +-- Location: LABCELL_X32_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111000001010000010100100010011101111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~1_combout\); + +-- Location: LABCELL_X31_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010001000100101111101110111000010100111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~0_combout\); + +-- Location: LABCELL_X36_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~0_combout\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011010001110100011111001100111111110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~2_combout\); + +-- Location: LABCELL_X36_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[3]_NEW2272\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[3]_OTERM2273\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[62]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[3]_OTERM2273\); + +-- Location: FF_X36_Y23_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[3]_OTERM2273\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(3)); + +-- Location: LABCELL_X47_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[3]~feeder_combout\); + +-- Location: FF_X47_Y15_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(3)); + +-- Location: LABCELL_X47_Y13_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[3]~feeder_combout\); + +-- Location: FF_X47_Y13_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(3)); + +-- Location: FF_X47_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(3)); + +-- Location: FF_X47_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(3)); + +-- Location: LABCELL_X47_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(3)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(3)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~1_combout\); + +-- Location: LABCELL_X47_Y13_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[3]~feeder_combout\); + +-- Location: FF_X47_Y13_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(3)); + +-- Location: FF_X47_Y13_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(3)); + +-- Location: FF_X45_Y14_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(3)); + +-- Location: MLABCELL_X45_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[3]~feeder_combout\); + +-- Location: FF_X45_Y14_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(3)); + +-- Location: MLABCELL_X45_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(3) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(3))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(3)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(3))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100001001101010111000010101100111010011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~0_combout\); + +-- Location: MLABCELL_X45_Y14_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux154~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux154~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~2_combout\); + +-- Location: FF_X45_Y14_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(3)); + +-- Location: LABCELL_X44_Y14_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~97\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~97_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(3)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011101000111010001101010011010100111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA2~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~97_combout\); + +-- Location: LABCELL_X47_Y11_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~98\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~98_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~97_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~97_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~97_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[3]~97_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~90_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~98_combout\); + +-- Location: LABCELL_X47_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~99\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~99_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~98_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~98_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~98_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111001111110000000011000000111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[3]~98_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~99_combout\); + +-- Location: FF_X47_Y11_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~99_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3)); + +-- Location: MLABCELL_X37_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100111111111100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~7_combout\); + +-- Location: MLABCELL_X37_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101000000001111000000110101001101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~5_combout\); + +-- Location: MLABCELL_X37_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~6_combout\); + +-- Location: MLABCELL_X37_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~8_combout\); + +-- Location: LABCELL_X36_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011110011111100111101000100011101110100010001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~9_combout\); + +-- Location: LABCELL_X32_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~2_combout\); + +-- Location: FF_X24_Y33_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~214_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~DUPLICATE_q\); + +-- Location: LABCELL_X32_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~3_combout\); + +-- Location: LABCELL_X32_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~0_combout\); + +-- Location: FF_X23_Y33_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~190_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\); + +-- Location: LABCELL_X32_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~1_combout\); + +-- Location: LABCELL_X32_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12882\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~1_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ +-- & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ +-- & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~1_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000010110000000101011011010100011010101110100001111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\); + +-- Location: LABCELL_X32_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12884\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~9_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~9_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000100111011000000000000101000110001001110111111010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\); + +-- Location: LABCELL_X32_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_OTERM2283\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4) +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_OTERM2283\); + +-- Location: FF_X32_Y37_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_OTERM2283\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4)); + +-- Location: FF_X45_Y26_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(4)); + +-- Location: LABCELL_X44_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[4]~feeder_combout\); + +-- Location: FF_X44_Y26_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(4)); + +-- Location: LABCELL_X44_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[4]~feeder_combout\); + +-- Location: FF_X44_Y26_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(4)); + +-- Location: FF_X44_Y26_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(4)); + +-- Location: LABCELL_X44_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(4))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(4))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(4)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~0_combout\); + +-- Location: MLABCELL_X49_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[4]~feeder_combout\); + +-- Location: FF_X49_Y25_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(4)); + +-- Location: LABCELL_X47_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[4]~feeder_combout\); + +-- Location: FF_X47_Y13_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(4)); + +-- Location: MLABCELL_X49_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[4]~feeder_combout\); + +-- Location: FF_X49_Y25_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(4)); + +-- Location: FF_X49_Y25_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(4)); + +-- Location: MLABCELL_X49_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(4)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(4))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(4))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~1_combout\); + +-- Location: LABCELL_X48_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux281~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux281~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~2_combout\); + +-- Location: FF_X48_Y25_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(4)); + +-- Location: LABCELL_X24_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~0_combout\); + +-- Location: LABCELL_X21_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~1_combout\); + +-- Location: LABCELL_X24_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13286\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1560~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1560~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\); + +-- Location: MLABCELL_X37_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13288\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111101011111010100001010000010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\); + +-- Location: MLABCELL_X37_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_OTERM2507\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4) +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011101010101001010001010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_OTERM2507\); + +-- Location: FF_X37_Y35_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_OTERM2507\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4)); + +-- Location: FF_X45_Y27_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(4)); + +-- Location: FF_X44_Y27_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(4)); + +-- Location: FF_X50_Y27_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(4)); + +-- Location: FF_X44_Y28_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(4)); + +-- Location: LABCELL_X50_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(4))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(4))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(4))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(4)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(4))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001000110000100110101011110001010110011101001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~1_combout\); + +-- Location: FF_X48_Y26_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(4)); + +-- Location: FF_X43_Y26_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(4)); + +-- Location: LABCELL_X48_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[4]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[4]~feeder_combout\); + +-- Location: FF_X48_Y26_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(4)); + +-- Location: FF_X43_Y26_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(4)); + +-- Location: LABCELL_X43_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(4)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(4)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(4)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~0_combout\); + +-- Location: LABCELL_X50_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux217~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux217~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~2_combout\); + +-- Location: FF_X50_Y26_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(4)); + +-- Location: FF_X34_Y28_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE_q\); + +-- Location: LABCELL_X21_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~1_combout\); + +-- Location: FF_X28_Y34_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_NEW_REG386\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM387\); + +-- Location: MLABCELL_X28_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111110101010111111111010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~2_combout\); + +-- Location: MLABCELL_X28_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add17~73_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101110001011100010100000101111101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~73_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~3_combout\); + +-- Location: FF_X28_Y29_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_NEW_REG388\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM389\); + +-- Location: LABCELL_X24_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011010001010110011110001001101010111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~0_combout\); + +-- Location: FF_X24_Y33_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_NEW_REG384\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM385\); + +-- Location: MLABCELL_X34_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM389\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM385\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM387\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM389\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM385\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM387\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM389\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM385\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM387\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM389\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM385\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM387\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010111111110000101000000000010111111111111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM375~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM387\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM377\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM389\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM385\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\); + +-- Location: LABCELL_X43_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[4]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[4]~feeder_combout\); + +-- Location: FF_X43_Y26_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(4)); + +-- Location: FF_X44_Y26_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(4)); + +-- Location: LABCELL_X43_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[4]~feeder_combout\); + +-- Location: FF_X43_Y26_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(4)); + +-- Location: FF_X43_Y26_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(4)); + +-- Location: LABCELL_X43_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(4)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(4)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~0_combout\); + +-- Location: MLABCELL_X42_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[4]~feeder_combout\); + +-- Location: FF_X42_Y24_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(4)); + +-- Location: FF_X43_Y24_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(4)); + +-- Location: LABCELL_X21_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[4]~feeder_combout\); + +-- Location: FF_X21_Y25_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(4)); + +-- Location: FF_X43_Y24_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(4)); + +-- Location: LABCELL_X43_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(4)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(4)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(4)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~1_combout\); + +-- Location: LABCELL_X50_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux89~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux89~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~2_combout\); + +-- Location: FF_X50_Y26_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(4)); + +-- Location: LABCELL_X21_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~0_combout\); + +-- Location: LABCELL_X24_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux428~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux428~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux428~0_combout\); + +-- Location: LABCELL_X32_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\)))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux428~0_combout\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux428~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101010101000111000011000001000101010101010001110011111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux428~0_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~6_combout\); + +-- Location: LABCELL_X35_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011010101010111011100000000001100110101000001110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~1_combout\); + +-- Location: FF_X35_Y22_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG446\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM447\); + +-- Location: FF_X34_Y22_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG436\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\); + +-- Location: FF_X29_Y27_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG442\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM443\); + +-- Location: FF_X32_Y26_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE_q\); + +-- Location: FF_X29_Y22_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG434\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM435\); + +-- Location: LABCELL_X35_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~feeder_combout\); + +-- Location: FF_X35_Y22_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~DUPLICATE_q\); + +-- Location: FF_X29_Y31_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~DUPLICATE_q\); + +-- Location: FF_X35_Y22_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG444\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM445\); + +-- Location: LABCELL_X35_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM435\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM445\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM447\) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM435\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM443\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM447\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101010101010101010101010101010101010101010101110101010101010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM447\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM437\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM443\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM435\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441~DUPLICATE_q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM445\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\); + +-- Location: FF_X45_Y15_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(4)); + +-- Location: FF_X45_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(4)); + +-- Location: FF_X45_Y15_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(4)); + +-- Location: FF_X35_Y22_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(4)); + +-- Location: MLABCELL_X45_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(4) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(4))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(4))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(4))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000100111001101101000110110011100101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~1_combout\); + +-- Location: FF_X45_Y19_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(4)); + +-- Location: MLABCELL_X45_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[4]~feeder_combout\); + +-- Location: FF_X45_Y18_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(4)); + +-- Location: FF_X45_Y19_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(4)); + +-- Location: FF_X45_Y19_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(4)); + +-- Location: MLABCELL_X45_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(4) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(4) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(4)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(4))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(4))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110111010101000011011010101010001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~0_combout\); + +-- Location: LABCELL_X44_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux153~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux153~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~2_combout\); + +-- Location: FF_X44_Y21_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(4)); + +-- Location: LABCELL_X50_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector104~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector104~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(4)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(4) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector104~0_combout\); + +-- Location: LABCELL_X48_Y11_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~87\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~87_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector104~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector104~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(0)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector104~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector104~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000011110000111110101010111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector104~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~87_combout\); + +-- Location: LABCELL_X48_Y11_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~88\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~88_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~87_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(4)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~87_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110000001100110011000000110011001111110011001100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~78_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[4]~87_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~88_combout\); + +-- Location: FF_X48_Y11_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~88_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(4)); + +-- Location: FF_X48_Y11_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~86_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(7)); + +-- Location: LABCELL_X32_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~1_combout\); + +-- Location: FF_X32_Y32_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_NEW_REG454\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM455\); + +-- Location: MLABCELL_X34_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux427~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux427~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000000001001110101010100100111101010100010011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux427~0_combout\); + +-- Location: FF_X34_Y31_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_NEW_REG450\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux427~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM451\); + +-- Location: LABCELL_X35_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100000101000100010000010100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1503~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~0_combout\); + +-- Location: FF_X35_Y26_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_NEW_REG452\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM453\); + +-- Location: LABCELL_X36_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM453\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM453\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM449\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM455\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM449\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM451\))))) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101000001000001010111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM449\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM455\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM451\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM453\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\); + +-- Location: LABCELL_X48_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1503~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[5]~feeder_combout\); + +-- Location: FF_X48_Y21_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(5)); + +-- Location: FF_X45_Y21_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(5)); + +-- Location: FF_X45_Y21_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(5)); + +-- Location: FF_X45_Y21_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(5)); + +-- Location: MLABCELL_X45_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(5))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(5))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(5)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(5)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~0_combout\); + +-- Location: LABCELL_X44_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1503~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[5]~feeder_combout\); + +-- Location: FF_X44_Y24_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(5)); + +-- Location: LABCELL_X47_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1503~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[5]~feeder_combout\); + +-- Location: FF_X47_Y24_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(5)); + +-- Location: LABCELL_X48_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1503~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[5]~feeder_combout\); + +-- Location: FF_X48_Y21_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(5)); + +-- Location: FF_X44_Y24_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(5)); + +-- Location: LABCELL_X44_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(5)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(5)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(5))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(5))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~1_combout\); + +-- Location: LABCELL_X44_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux152~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux152~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~2_combout\); + +-- Location: FF_X44_Y24_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(5)); + +-- Location: MLABCELL_X34_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~3_combout\); + +-- Location: LABCELL_X35_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~1_combout\); + +-- Location: MLABCELL_X34_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~2_combout\); + +-- Location: LABCELL_X35_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~0_combout\); + +-- Location: LABCELL_X35_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12902\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~1_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~1_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~1_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000001100011101110000110001000100001111110111011100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\); + +-- Location: LABCELL_X35_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~5_combout\); + +-- Location: LABCELL_X32_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~8_combout\); + +-- Location: LABCELL_X32_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\)))) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000000001001111010101000100111010101010010011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~6_combout\); + +-- Location: LABCELL_X35_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111100001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~7_combout\); + +-- Location: LABCELL_X35_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\))) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~7_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~8_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~5_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000010110000000101011011010100011010101110100001111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~9_combout\); + +-- Location: LABCELL_X35_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12904\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000000000110110000111110111011111111110001101100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\); + +-- Location: LABCELL_X35_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_OTERM2293\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000001110111011111110100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_OTERM2293\); + +-- Location: FF_X35_Y29_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_OTERM2293\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5)); + +-- Location: LABCELL_X48_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[5]~feeder_combout\); + +-- Location: FF_X48_Y26_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(5)); + +-- Location: MLABCELL_X49_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[5]~feeder_combout\); + +-- Location: FF_X49_Y26_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(5)); + +-- Location: MLABCELL_X49_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[5]~feeder_combout\); + +-- Location: FF_X49_Y26_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(5)); + +-- Location: FF_X49_Y26_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(5)); + +-- Location: MLABCELL_X49_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(5)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(5)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(5)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(5) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~0_combout\); + +-- Location: FF_X49_Y30_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(5)); + +-- Location: FF_X49_Y30_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(5)); + +-- Location: FF_X49_Y30_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(5)); + +-- Location: LABCELL_X44_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[5]~feeder_combout\); + +-- Location: FF_X44_Y28_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(5)); + +-- Location: MLABCELL_X49_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(5) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(5))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(5))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(5))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001100000101111100111111010100000011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~1_combout\); + +-- Location: LABCELL_X52_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux280~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux280~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~2_combout\); + +-- Location: FF_X52_Y24_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(5)); + +-- Location: MLABCELL_X34_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101101011111010111100100010011101110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~0_combout\); + +-- Location: LABCELL_X32_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~1_combout\); + +-- Location: LABCELL_X36_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13278\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101010101010000010110101010101011111111111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1559~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1559~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\); + +-- Location: FF_X40_Y35_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_OTERM2501\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(5)); + +-- Location: LABCELL_X40_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13280\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(5) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111101011111010100001010000010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\); + +-- Location: LABCELL_X40_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_OTERM2501\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011110111111100111100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_OTERM2501\); + +-- Location: FF_X40_Y35_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_OTERM2501\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE_q\); + +-- Location: FF_X49_Y30_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(5)); + +-- Location: FF_X49_Y30_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(5)); + +-- Location: LABCELL_X50_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[5]~feeder_combout\); + +-- Location: FF_X50_Y30_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(5)); + +-- Location: FF_X49_Y30_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(5)); + +-- Location: MLABCELL_X49_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(5)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(5)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(5))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(5))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~1_combout\); + +-- Location: FF_X49_Y26_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(5)); + +-- Location: LABCELL_X52_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[5]~feeder_combout\); + +-- Location: FF_X52_Y26_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(5)); + +-- Location: FF_X49_Y26_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(5)); + +-- Location: FF_X49_Y26_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(5)); + +-- Location: MLABCELL_X49_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(5))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(5))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(5)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(5)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~0_combout\); + +-- Location: LABCELL_X50_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000000000000000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux216~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux216~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~2_combout\); + +-- Location: FF_X50_Y26_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(5)); + +-- Location: LABCELL_X32_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9057\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9057_BDD9058\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9057_BDD9058\); + +-- Location: MLABCELL_X34_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9055\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9055_BDD9056\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101011111111101010101111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9055_BDD9056\); + +-- Location: LABCELL_X35_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9059\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9059_BDD9060\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9057_BDD9058\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9055_BDD9056\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9057_BDD9058\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9055_BDD9056\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9057_BDD9058\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9055_BDD9056\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000111000011111111011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9057_BDD9058\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9055_BDD9056\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9059_BDD9060\); + +-- Location: LABCELL_X35_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9059_BDD9060\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9059_BDD9060\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110111000001000011011100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9059_BDD9060\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_combout\); + +-- Location: LABCELL_X35_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[5]_NEW3231\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[5]_OTERM3232\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(5))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add17~77_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(5))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~77_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~77_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[5]_OTERM3232\); + +-- Location: FF_X35_Y27_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[5]_OTERM3232\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(5)); + +-- Location: FF_X41_Y11_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(5)); + +-- Location: LABCELL_X48_Y12_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[5]~feeder_combout\); + +-- Location: FF_X48_Y12_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(5)); + +-- Location: FF_X41_Y11_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(5)); + +-- Location: FF_X41_Y11_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(5)); + +-- Location: LABCELL_X41_Y11_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(5)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(5)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(5)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(5)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~1_combout\); + +-- Location: FF_X48_Y13_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(5)); + +-- Location: FF_X50_Y13_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(5)); + +-- Location: FF_X49_Y13_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(5)); + +-- Location: FF_X49_Y13_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(5)); + +-- Location: MLABCELL_X49_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(5) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(5))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(5)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(5))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(5) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(5) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(5)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(5) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(5) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(5) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000010001010111110001000100001010101110110101111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~0_combout\); + +-- Location: MLABCELL_X49_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux88~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux88~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~2_combout\); + +-- Location: FF_X49_Y13_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(5)); + +-- Location: LABCELL_X52_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector103~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector103~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(5) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(5) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(5) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(5) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector103~0_combout\); + +-- Location: LABCELL_X48_Y11_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~82\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~82_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector103~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(4))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector103~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(4))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010011000000110101001110100011111100111010001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector103~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~82_combout\); + +-- Location: LABCELL_X48_Y11_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~83\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~83_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~82_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~82_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111100000000001111110000000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~78_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[5]~82_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~83_combout\); + +-- Location: FF_X48_Y11_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~83_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5)); + +-- Location: LABCELL_X31_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~0_combout\); + +-- Location: LABCELL_X31_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~1_combout\); + +-- Location: LABCELL_X32_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~2_combout\); + +-- Location: LABCELL_X32_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~3_combout\); + +-- Location: LABCELL_X35_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12918\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~0_combout\)))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101010001000010110101101110100001111100011010101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\); + +-- Location: LABCELL_X35_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~6_combout\); + +-- Location: LABCELL_X35_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~8_combout\); + +-- Location: LABCELL_X35_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~5_combout\); + +-- Location: LABCELL_X29_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~7_combout\); + +-- Location: LABCELL_X35_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~5_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000100010001000100001100001111111101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~9_combout\); + +-- Location: LABCELL_X35_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12920\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000000000110110000111110110001111100001011101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\); + +-- Location: LABCELL_X35_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_OTERM2301\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011111111110111001100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_OTERM2301\); + +-- Location: FF_X35_Y29_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_OTERM2301\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6)); + +-- Location: LABCELL_X47_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[6]~feeder_combout\); + +-- Location: FF_X47_Y25_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(6)); + +-- Location: FF_X50_Y25_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(6)); + +-- Location: FF_X50_Y25_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(6)); + +-- Location: FF_X50_Y25_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(6)); + +-- Location: LABCELL_X50_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(6) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(6) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(6) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(6))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(6)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100110000111101010011111100000101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~1_combout\); + +-- Location: FF_X48_Y26_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(6)); + +-- Location: MLABCELL_X45_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[6]~feeder_combout\); + +-- Location: FF_X45_Y26_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(6)); + +-- Location: FF_X48_Y26_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(6)); + +-- Location: MLABCELL_X45_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[6]~feeder_combout\); + +-- Location: FF_X45_Y26_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(6)); + +-- Location: LABCELL_X48_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(6))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(6))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(6))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(6)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(6))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(6)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(6) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(6)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000011000100011100111111011101000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~0_combout\); + +-- Location: LABCELL_X48_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux279~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux279~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~2_combout\); + +-- Location: FF_X48_Y25_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(6)); + +-- Location: MLABCELL_X34_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000011110000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1502~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~0_combout\); + +-- Location: FF_X34_Y22_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_NEW_REG478\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM479\); + +-- Location: LABCELL_X32_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux426~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux426~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001111110101000000110000010111110011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux426~0_combout\); + +-- Location: FF_X32_Y35_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_NEW_REG476\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux426~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM477\); + +-- Location: LABCELL_X26_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000000001100110000011101000111010011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~1_combout\); + +-- Location: FF_X26_Y35_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_NEW_REG480\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM481\); + +-- Location: LABCELL_X36_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM481\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM449\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM477\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM479\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM481\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM449\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM477\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM479\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100011111000011110001111101001111010111110100111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM449\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM479\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM477\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM481\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\); + +-- Location: FF_X42_Y26_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(6)); + +-- Location: FF_X49_Y27_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(6)); + +-- Location: FF_X42_Y26_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(6)); + +-- Location: FF_X42_Y26_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(6)); + +-- Location: MLABCELL_X42_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(6))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(6))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(6) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(6) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(6))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(6) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(6)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111010101010010011110101010001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~0_combout\); + +-- Location: FF_X53_Y27_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(6)); + +-- Location: FF_X53_Y27_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(6)); + +-- Location: FF_X49_Y27_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(6)); + +-- Location: FF_X53_Y27_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(6)); + +-- Location: LABCELL_X53_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(6)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(6)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(6)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~1_combout\); + +-- Location: LABCELL_X48_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux151~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux151~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~2_combout\); + +-- Location: FF_X48_Y25_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(6)); + +-- Location: MLABCELL_X34_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000010100000101000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1440~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~2_combout\); + +-- Location: MLABCELL_X34_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~81_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101001000100111011110100000111101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~81_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1440~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~3_combout\); + +-- Location: FF_X34_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_NEW_REG400\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM401\); + +-- Location: LABCELL_X32_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~0_combout\); + +-- Location: FF_X31_Y35_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_NEW_REG396\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM397\); + +-- Location: LABCELL_X26_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010000001011010111101110111011101110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~1_combout\); + +-- Location: FF_X26_Y35_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_NEW_REG398\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM399\); + +-- Location: MLABCELL_X34_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM399\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM401\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM397\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM399\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM401\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM397\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000011011000010100001101101001110010111110100111001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM377\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM375\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM401\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM397\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM399\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\); + +-- Location: FF_X43_Y24_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(6)); + +-- Location: LABCELL_X39_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1440~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[6]~feeder_combout\); + +-- Location: FF_X39_Y24_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(6)); + +-- Location: FF_X43_Y24_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(6)); + +-- Location: FF_X43_Y24_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(6)); + +-- Location: LABCELL_X43_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(6) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(6) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(6) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(6) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~1_combout\); + +-- Location: FF_X48_Y29_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(6)); + +-- Location: FF_X42_Y29_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(6)); + +-- Location: FF_X48_Y29_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(6)); + +-- Location: FF_X48_Y29_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(6)); + +-- Location: LABCELL_X48_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(6)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(6)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(6)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(6)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~0_combout\); + +-- Location: LABCELL_X48_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux87~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux87~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~2_combout\); + +-- Location: FF_X48_Y25_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(6)); + +-- Location: LABCELL_X26_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~1_combout\); + +-- Location: LABCELL_X32_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001100000100010011111111011101000011001101110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~0_combout\); + +-- Location: LABCELL_X32_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13282\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13282_BDD13283\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux165~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1558~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1558~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13282_BDD13283\); + +-- Location: FF_X40_Y35_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_OTERM2504\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(6)); + +-- Location: LABCELL_X40_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13284\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(6) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13282_BDD13283\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(6) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13282_BDD13283\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011011101000000001101110100100010111111110010001011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]_NEW2503_RESYN13282_BDD13283\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\); + +-- Location: LABCELL_X40_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_OTERM2504\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000001101011111110111100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_OTERM2504\); + +-- Location: FF_X40_Y35_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_OTERM2504\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE_q\); + +-- Location: LABCELL_X50_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[6]~feeder_combout\); + +-- Location: FF_X50_Y30_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(6)); + +-- Location: LABCELL_X44_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[6]~feeder_combout\); + +-- Location: FF_X44_Y28_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(6)); + +-- Location: FF_X45_Y28_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(6)); + +-- Location: LABCELL_X44_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[6]~feeder_combout\); + +-- Location: FF_X44_Y28_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(6)); + +-- Location: MLABCELL_X45_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(6))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(6)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(6) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(6) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(6)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(6) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001100000100010011111111011101000011001101110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~1_combout\); + +-- Location: FF_X48_Y26_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(6)); + +-- Location: FF_X48_Y26_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(6)); + +-- Location: FF_X48_Y28_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(6)); + +-- Location: FF_X48_Y28_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(6)); + +-- Location: LABCELL_X48_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(6) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(6) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(6))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(6)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(6)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100111111000001010011000011110101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~0_combout\); + +-- Location: LABCELL_X48_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux215~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux215~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~2_combout\); + +-- Location: FF_X48_Y25_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(6)); + +-- Location: LABCELL_X48_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector102~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector102~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(6) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(6)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(6)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(6))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(6)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(6))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111001000100010001000000101101011110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector102~0_combout\); + +-- Location: LABCELL_X47_Y11_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~79\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~79_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector102~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector102~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector102~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector102~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000011110101111111110000010100001111111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector102~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~79_combout\); + +-- Location: LABCELL_X47_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~80\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~80_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~79_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(6)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~79_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(6) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~78_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~79_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~80_combout\); + +-- Location: FF_X47_Y11_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~80_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(6)); + +-- Location: LABCELL_X36_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~5_combout\); + +-- Location: LABCELL_X36_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~6_combout\); + +-- Location: LABCELL_X36_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~8_combout\); + +-- Location: LABCELL_X36_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~7_combout\); + +-- Location: LABCELL_X36_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~6_combout\)))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~5_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~6_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~7_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~6_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111101010100010011101010101001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~9_combout\); + +-- Location: LABCELL_X36_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~2_combout\); + +-- Location: LABCELL_X36_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~3_combout\); + +-- Location: LABCELL_X35_Y37_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~1_combout\); + +-- Location: LABCELL_X31_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~0_combout\); + +-- Location: LABCELL_X36_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12886\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001111110101000000110000010111110011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\); + +-- Location: MLABCELL_X37_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12888\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7) & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000101000111010101001010011010101011111001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\); + +-- Location: MLABCELL_X37_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_OTERM2285\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011110111001111111100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_OTERM2285\); + +-- Location: FF_X37_Y31_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_OTERM2285\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7)); + +-- Location: LABCELL_X50_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[7]~feeder_combout\); + +-- Location: FF_X50_Y20_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(7)); + +-- Location: FF_X50_Y18_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(7)); + +-- Location: FF_X50_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(7)); + +-- Location: LABCELL_X50_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[7]~feeder_combout\); + +-- Location: FF_X50_Y20_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(7)); + +-- Location: LABCELL_X50_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(7) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(7)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(7)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(7)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010111110011000001010000001111110101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~0_combout\); + +-- Location: FF_X47_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(7)); + +-- Location: LABCELL_X47_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[7]~feeder_combout\); + +-- Location: FF_X47_Y19_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(7)); + +-- Location: FF_X47_Y18_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(7)); + +-- Location: LABCELL_X47_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[7]~feeder_combout\); + +-- Location: FF_X47_Y20_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(7)); + +-- Location: LABCELL_X47_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(7) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(7))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(7))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(7)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(7)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000110010101110100101010011011100011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~1_combout\); + +-- Location: LABCELL_X47_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux278~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux278~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~2_combout\); + +-- Location: FF_X47_Y18_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(7)); + +-- Location: FF_X35_Y22_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG440\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441\); + +-- Location: LABCELL_X36_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux425~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux425~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux425~0_combout\); + +-- Location: LABCELL_X40_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101001001100011011110001100100111011010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~0_combout\); + +-- Location: LABCELL_X36_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux425~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux425~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111100000000010101010000000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux425~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1501~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~1_combout\); + +-- Location: FF_X36_Y37_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_NEW_REG927\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM928\); + +-- Location: FF_X35_Y22_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_NEW_REG925\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM926\); + +-- Location: LABCELL_X35_Y22_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM926\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM928\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM926\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM928\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100111111000011110011111100001111001011110000111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[7]_OTERM928\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[7]_OTERM926\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM437\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\); + +-- Location: FF_X52_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(7)); + +-- Location: LABCELL_X52_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1501~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[7]~feeder_combout\); + +-- Location: FF_X52_Y16_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(7)); + +-- Location: FF_X52_Y20_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(7)); + +-- Location: FF_X52_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(7)); + +-- Location: LABCELL_X52_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(7))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(7))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~0_combout\); + +-- Location: LABCELL_X50_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1501~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[7]~feeder_combout\); + +-- Location: FF_X50_Y16_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(7)); + +-- Location: LABCELL_X52_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1501~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[7]~feeder_combout\); + +-- Location: FF_X52_Y21_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(7)); + +-- Location: FF_X47_Y18_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(7)); + +-- Location: FF_X47_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(7)); + +-- Location: LABCELL_X47_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(7))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(7))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~1_combout\); + +-- Location: LABCELL_X47_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux150~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux150~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~2_combout\); + +-- Location: FF_X47_Y18_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(7)); + +-- Location: FF_X36_Y37_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_OTERM2510\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(7)); + +-- Location: LABCELL_X40_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100111111000001010011000011110101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~1_combout\); + +-- Location: LABCELL_X36_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101000100011010111110111011000001011011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~0_combout\); + +-- Location: LABCELL_X35_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13290\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000000110000001111011101110111011100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1557~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1557~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\); + +-- Location: LABCELL_X36_Y37_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13292\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(7) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110101010100000000101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\); + +-- Location: LABCELL_X36_Y37_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_OTERM2510\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(7) +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_OTERM2510\); + +-- Location: FF_X36_Y37_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_OTERM2510\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE_q\); + +-- Location: LABCELL_X52_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[7]~feeder_combout\); + +-- Location: FF_X52_Y28_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(7)); + +-- Location: LABCELL_X52_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[7]~feeder_combout\); + +-- Location: FF_X52_Y28_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(7)); + +-- Location: FF_X53_Y28_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(7)); + +-- Location: LABCELL_X53_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[7]~feeder_combout\); + +-- Location: FF_X53_Y28_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(7)); + +-- Location: LABCELL_X53_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(7)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(7))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(7) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(7))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(7))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(7) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(7))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000100101001010100010111101110000011101010111101001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~0_combout\); + +-- Location: LABCELL_X53_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[7]~feeder_combout\); + +-- Location: FF_X53_Y28_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(7)); + +-- Location: LABCELL_X53_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[7]~feeder_combout\); + +-- Location: FF_X53_Y27_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(7)); + +-- Location: LABCELL_X53_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[7]~feeder_combout\); + +-- Location: FF_X53_Y27_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(7)); + +-- Location: FF_X53_Y27_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(7)); + +-- Location: LABCELL_X53_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(7))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(7))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~1_combout\); + +-- Location: LABCELL_X53_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux214~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux214~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~2_combout\); + +-- Location: FF_X53_Y26_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(7)); + +-- Location: LABCELL_X36_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9061\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9061_BDD9062\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100111111001111110011111100111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9061_BDD9062\); + +-- Location: LABCELL_X40_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9063\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9063_BDD9064\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101011101110000010100100010101011110111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9063_BDD9064\); + +-- Location: LABCELL_X35_Y37_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9065\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9065_BDD9066\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9063_BDD9064\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9061_BDD9062\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9063_BDD9064\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9061_BDD9062\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9063_BDD9064\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9061_BDD9062\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9063_BDD9064\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9061_BDD9062\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100010001000100010001000110101011101110111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9061_BDD9062\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9063_BDD9064\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9065_BDD9066\); + +-- Location: LABCELL_X35_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9065_BDD9066\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9065_BDD9066\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9065_BDD9066\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9065_BDD9066\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111010101010000111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9065_BDD9066\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_combout\); + +-- Location: LABCELL_X35_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[7]_NEW3227\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[7]_OTERM3228\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(7))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add17~85_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~85_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~85_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[7]_OTERM3228\); + +-- Location: FF_X35_Y27_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[7]_OTERM3228\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(7)); + +-- Location: LABCELL_X50_Y13_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[7]~feeder_combout\); + +-- Location: FF_X50_Y13_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(7)); + +-- Location: FF_X52_Y16_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(7)); + +-- Location: FF_X50_Y13_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(7)); + +-- Location: LABCELL_X52_Y13_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[7]~feeder_combout\); + +-- Location: FF_X52_Y13_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(7)); + +-- Location: LABCELL_X50_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(7)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(7))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(7) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(7))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(7) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(7) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101001000101010111101110111000001010111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~0_combout\); + +-- Location: FF_X47_Y15_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(7)); + +-- Location: FF_X45_Y15_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(7)); + +-- Location: FF_X47_Y15_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(7)); + +-- Location: LABCELL_X47_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[7]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(7) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[7]~feeder_combout\); + +-- Location: FF_X47_Y15_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(7)); + +-- Location: LABCELL_X47_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(7) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(7))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(7))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(7))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001100000101111100111111010100000011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~1_combout\); + +-- Location: LABCELL_X47_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux86~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux86~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~2_combout\); + +-- Location: FF_X47_Y18_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(7)); + +-- Location: LABCELL_X47_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector101~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector101~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(7))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(7))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(7))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(7)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(7))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001000110000100110101011110001010110011101001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector101~0_combout\); + +-- Location: LABCELL_X47_Y11_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~85\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~85_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector101~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(6)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector101~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(6))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector101~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(6))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector101~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(6)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000110110001101110110001101100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector101~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~85_combout\); + +-- Location: LABCELL_X48_Y11_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~86\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~86_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~85_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(7)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~85_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(7) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111100000000001111110000000011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~78_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[7]~85_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~86_combout\); + +-- Location: FF_X48_Y11_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~86_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE_q\); + +-- Location: LABCELL_X48_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~0_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010011111100000101001100001111010100111111111101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector100~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~1_combout\); + +-- Location: FF_X48_Y11_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_NEW_REG819\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM820\); + +-- Location: LABCELL_X48_Y11_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM820\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM818\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM820\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM818\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110101000000001111010100001010111111110000101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]_OTERM818\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]_OTERM820\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\); + +-- Location: FF_X18_Y30_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~56_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\); + +-- Location: FF_X20_Y31_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~64_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\); + +-- Location: MLABCELL_X34_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~1_combout\); + +-- Location: FF_X34_Y36_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_NEW_REG392\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM393\); + +-- Location: MLABCELL_X34_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110011000000110000001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1437~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~2_combout\); + +-- Location: MLABCELL_X34_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & +-- ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110101000001010011010111110101010101010000010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1437~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~3_combout\); + +-- Location: FF_X34_Y26_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_NEW_REG394\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM395\); + +-- Location: MLABCELL_X34_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~0_combout\); + +-- Location: FF_X34_Y36_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_NEW_REG390\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM391\); + +-- Location: MLABCELL_X34_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM395\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM391\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM393\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM395\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM391\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM393\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM395\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM391\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM393\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM395\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM391\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM393\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010111111110000101000000000010111111111111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM375~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM393\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM377\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM395\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM391\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\); + +-- Location: FF_X44_Y26_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(9)); + +-- Location: FF_X43_Y26_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(9)); + +-- Location: FF_X42_Y26_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(9)); + +-- Location: FF_X43_Y26_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(9)); + +-- Location: LABCELL_X43_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(9)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(9))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(9))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~0_combout\); + +-- Location: FF_X45_Y27_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(9)); + +-- Location: FF_X43_Y24_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(9)); + +-- Location: LABCELL_X44_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1437~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[9]~feeder_combout\); + +-- Location: FF_X44_Y24_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(9)); + +-- Location: FF_X43_Y24_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(9)); + +-- Location: LABCELL_X43_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(9)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(9) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(9))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(9))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~1_combout\); + +-- Location: LABCELL_X53_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux84~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux84~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~2_combout\); + +-- Location: FF_X53_Y26_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(9)); + +-- Location: MLABCELL_X34_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~0_combout\); + +-- Location: MLABCELL_X34_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~1_combout\); + +-- Location: MLABCELL_X34_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12906\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12906_BDD12907\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000001010000010100010001101110110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1499~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1499~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12906_BDD12907\); + +-- Location: LABCELL_X35_Y36_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12908\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12906_BDD12907\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12906_BDD12907\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[9]_NEW2294_RESYN12906_BDD12907\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\); + +-- Location: LABCELL_X35_Y36_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_OTERM2295\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011110111001111111100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_OTERM2295\); + +-- Location: FF_X35_Y36_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_OTERM2295\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9)); + +-- Location: FF_X49_Y26_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(9)); + +-- Location: FF_X49_Y26_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(9)); + +-- Location: MLABCELL_X45_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[9]~feeder_combout\); + +-- Location: FF_X45_Y26_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(9)); + +-- Location: FF_X49_Y26_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(9)); + +-- Location: MLABCELL_X49_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(9))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(9))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(9)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(9)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~0_combout\); + +-- Location: FF_X50_Y30_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(9)); + +-- Location: FF_X53_Y26_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(9)); + +-- Location: FF_X53_Y26_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(9)); + +-- Location: FF_X50_Y30_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(9)); + +-- Location: LABCELL_X53_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(9) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(9))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(9))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(9))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001100000101111100111111010100000011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~1_combout\); + +-- Location: LABCELL_X53_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux148~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux148~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~2_combout\); + +-- Location: FF_X53_Y26_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(9)); + +-- Location: FF_X41_Y27_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_OTERM2297\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(9)); + +-- Location: FF_X18_Y30_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~53_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\); + +-- Location: FF_X18_Y30_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~54_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\); + +-- Location: LABCELL_X40_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~7_combout\); + +-- Location: FF_X18_Y30_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\); + +-- Location: FF_X18_Y30_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~51_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\); + +-- Location: LABCELL_X39_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~8_combout\); + +-- Location: LABCELL_X39_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~5_combout\); + +-- Location: FF_X20_Y31_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~62_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\); + +-- Location: LABCELL_X39_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~6_combout\); + +-- Location: LABCELL_X40_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~8_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~7_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~7_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110111010101000011011010101010001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~9_combout\); + +-- Location: FF_X21_Y29_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~36_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\); + +-- Location: FF_X21_Y29_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~37_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\); + +-- Location: FF_X21_Y29_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~38_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\); + +-- Location: LABCELL_X40_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~0_combout\); + +-- Location: FF_X18_Y30_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~42_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\); + +-- Location: FF_X18_Y30_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~41_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\); + +-- Location: LABCELL_X39_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~2_combout\); + +-- Location: LABCELL_X39_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~3_combout\); + +-- Location: FF_X21_Y30_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~45_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\); + +-- Location: FF_X21_Y30_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~46_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\); + +-- Location: LABCELL_X39_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~1_combout\); + +-- Location: LABCELL_X40_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~0_combout\))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101100010011100110100100011011001111010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~4_combout\); + +-- Location: LABCELL_X40_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12910\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12910_BDD12911\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~4_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100111100000000001100001111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12910_BDD12911\); + +-- Location: LABCELL_X41_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12912\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12910_BDD12911\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(9)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12910_BDD12911\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(9))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100000001000000010010111111101111111011111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]_NEW2296_RESYN12910_BDD12911\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\); + +-- Location: LABCELL_X41_Y27_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_OTERM2297\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(9) +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_OTERM2297\); + +-- Location: FF_X41_Y27_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_OTERM2297\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE_q\); + +-- Location: LABCELL_X52_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[9]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[9]~feeder_combout\); + +-- Location: FF_X52_Y28_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(9)); + +-- Location: LABCELL_X52_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[9]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[9]~feeder_combout\); + +-- Location: FF_X52_Y28_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(9)); + +-- Location: FF_X53_Y28_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(9)); + +-- Location: FF_X53_Y28_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(9)); + +-- Location: LABCELL_X53_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(9))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(9))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(9)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(9)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~0_combout\); + +-- Location: LABCELL_X52_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[9]~feeder_combout\); + +-- Location: FF_X52_Y31_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(9)); + +-- Location: FF_X50_Y31_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(9)); + +-- Location: LABCELL_X52_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[9]~feeder_combout\); + +-- Location: FF_X52_Y31_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(9)); + +-- Location: FF_X52_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(9)); + +-- Location: LABCELL_X52_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(9)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(9) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(9)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(9)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~1_combout\); + +-- Location: LABCELL_X53_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux212~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux212~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~2_combout\); + +-- Location: FF_X53_Y26_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(9)); + +-- Location: LABCELL_X39_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~5_combout\); + +-- Location: LABCELL_X39_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~8_combout\); + +-- Location: LABCELL_X39_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~6_combout\); + +-- Location: LABCELL_X40_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~7_combout\); + +-- Location: LABCELL_X40_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~5_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100000011000111011100111111010001000011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~9_combout\); + +-- Location: LABCELL_X39_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~2_combout\); + +-- Location: LABCELL_X39_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~3_combout\); + +-- Location: LABCELL_X40_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~1_combout\); + +-- Location: LABCELL_X40_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~0_combout\); + +-- Location: LABCELL_X39_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12914\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010010111110010001000001010011101110101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\); + +-- Location: LABCELL_X43_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12916\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~9_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9) & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~9_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010101000000110000000001010011010101011111001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\); + +-- Location: LABCELL_X43_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_OTERM2299\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9) +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011101010101001010001010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_OTERM2299\); + +-- Location: FF_X43_Y28_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_OTERM2299\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9)); + +-- Location: FF_X47_Y27_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(9)); + +-- Location: FF_X49_Y29_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(9)); + +-- Location: FF_X49_Y29_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(9)); + +-- Location: FF_X49_Y29_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(9)); + +-- Location: MLABCELL_X49_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(9))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(9))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(9)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(9)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~0_combout\); + +-- Location: FF_X49_Y28_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(9)); + +-- Location: FF_X49_Y28_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(9)); + +-- Location: FF_X53_Y26_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(9)); + +-- Location: FF_X49_Y28_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(9)); + +-- Location: LABCELL_X53_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(9) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(9))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(9)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(9) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(9) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(9)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(9) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(9) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001100000100010011111111011101000011001101110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~1_combout\); + +-- Location: LABCELL_X53_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux276~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux276~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~2_combout\); + +-- Location: FF_X53_Y26_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(9)); + +-- Location: LABCELL_X53_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(9) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(9)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(9)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(9)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000101010001001010010111101110000011110100111010101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~0_combout\); + +-- Location: LABCELL_X48_Y11_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000000111111001111110101111101010000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]~76_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector99~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~1_combout\); + +-- Location: FF_X48_Y11_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_NEW_REG811\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM812\); + +-- Location: LABCELL_X48_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM812\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM810\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM812\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM810\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110101000000001111010100001010111111110000101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]_OTERM810\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]_OTERM812\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81_combout\); + +-- Location: FF_X43_Y30_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_OTERM2305\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(10)); + +-- Location: FF_X19_Y32_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~108_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\); + +-- Location: FF_X19_Y32_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~110_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\); + +-- Location: MLABCELL_X37_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~3_combout\); + +-- Location: FF_X19_Y30_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~105_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\); + +-- Location: FF_X19_Y30_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~106_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\); + +-- Location: FF_X19_Y30_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~104_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\); + +-- Location: MLABCELL_X37_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~1_combout\); + +-- Location: FF_X19_Y31_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~101_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\); + +-- Location: FF_X19_Y31_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~102_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\); + +-- Location: LABCELL_X36_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~2_combout\); + +-- Location: FF_X19_Y30_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~98_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\); + +-- Location: FF_X19_Y30_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~96_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\); + +-- Location: FF_X19_Y30_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~97_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\); + +-- Location: MLABCELL_X37_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~0_combout\); + +-- Location: MLABCELL_X37_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\))) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~1_combout\))))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100001010100110111000011001010111010011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~4_combout\); + +-- Location: LABCELL_X41_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~8_combout\); + +-- Location: FF_X18_Y32_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~119_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\); + +-- Location: FF_X18_Y32_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~120_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~5_combout\); + +-- Location: FF_X19_Y30_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~124_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~6_combout\); + +-- Location: FF_X18_Y32_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~116_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~7_combout\); + +-- Location: MLABCELL_X42_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~5_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~5_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~5_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010000110010011101101001100011011100101110101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~9_combout\); + +-- Location: LABCELL_X43_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12926\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12926_BDD12927\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~9_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010001110100011110111000101110001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12926_BDD12927\); + +-- Location: LABCELL_X43_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12928\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(10) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12926_BDD12927\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(10) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12926_BDD12927\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]_NEW2304_RESYN12926_BDD12927\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\); + +-- Location: LABCELL_X43_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_OTERM2305\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_OTERM2305\); + +-- Location: FF_X43_Y30_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_OTERM2305\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE_q\); + +-- Location: MLABCELL_X49_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[10]~feeder_combout\); + +-- Location: FF_X49_Y20_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(10)); + +-- Location: FF_X48_Y20_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(10)); + +-- Location: FF_X50_Y13_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(10)); + +-- Location: FF_X50_Y13_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(10)); + +-- Location: LABCELL_X50_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(10) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(10)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(10)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(10) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(10) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(10))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(10)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(10))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001011010100010101101110100001101010111111000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~0_combout\); + +-- Location: LABCELL_X50_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[10]~feeder_combout\); + +-- Location: FF_X50_Y16_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(10)); + +-- Location: FF_X50_Y15_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(10)); + +-- Location: LABCELL_X50_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[10]~feeder_combout\); + +-- Location: FF_X50_Y16_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(10)); + +-- Location: FF_X50_Y15_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(10)); + +-- Location: LABCELL_X50_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(10)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(10)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(10))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(10))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~1_combout\); + +-- Location: LABCELL_X50_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux211~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux211~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~2_combout\); + +-- Location: FF_X50_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(10)); + +-- Location: MLABCELL_X37_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~1_combout\); + +-- Location: MLABCELL_X37_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~0_combout\); + +-- Location: LABCELL_X35_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12922\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12922_BDD12923\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000001010000010100110000001111110011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1498~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1498~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12922_BDD12923\); + +-- Location: FF_X34_Y34_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_OTERM2303\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]~DUPLICATE_q\); + +-- Location: MLABCELL_X34_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12924\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12922_BDD12923\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12922_BDD12923\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000011001100110000001100110011111100110011001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]_NEW2302_RESYN12922_BDD12923\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\); + +-- Location: MLABCELL_X34_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_OTERM2303\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_OTERM2303\); + +-- Location: FF_X34_Y34_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_OTERM2303\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10)); + +-- Location: LABCELL_X43_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[10]~feeder_combout\); + +-- Location: FF_X43_Y23_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(10)); + +-- Location: LABCELL_X43_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[10]~feeder_combout\); + +-- Location: FF_X43_Y23_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(10)); + +-- Location: LABCELL_X43_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[10]~feeder_combout\); + +-- Location: FF_X43_Y25_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(10)); + +-- Location: FF_X43_Y25_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(10)); + +-- Location: LABCELL_X43_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(10)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(10)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~0_combout\); + +-- Location: FF_X44_Y23_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(10)); + +-- Location: LABCELL_X43_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[10]~feeder_combout\); + +-- Location: FF_X43_Y23_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(10)); + +-- Location: FF_X44_Y23_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(10)); + +-- Location: FF_X44_Y24_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(10)); + +-- Location: LABCELL_X44_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(10) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(10)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(10) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(10) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(10))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(10)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(10))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100111101001100011100110111000001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~1_combout\); + +-- Location: LABCELL_X44_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux147~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux147~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~2_combout\); + +-- Location: FF_X44_Y23_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(10)); + +-- Location: MLABCELL_X37_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9051\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9051_BDD9052\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000110110001101110101010111111110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9051_BDD9052\); + +-- Location: MLABCELL_X37_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~1_combout\); + +-- Location: MLABCELL_X37_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9053\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9053_BDD9054\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9051_BDD9052\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9051_BDD9052\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_RESYN9051_BDD9052\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9053_BDD9054\); + +-- Location: MLABCELL_X34_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9053_BDD9054\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9053_BDD9054\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9053_BDD9054\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9053_BDD9054\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101100001111001100110000111100010001000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_RESYN9053_BDD9054\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_combout\); + +-- Location: MLABCELL_X34_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]_NEW3233\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]_OTERM3234\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(10))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100110001111111010011000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~41_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]_OTERM3234\); + +-- Location: FF_X34_Y27_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]_OTERM3234\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(10)); + +-- Location: LABCELL_X47_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[10]~feeder_combout\); + +-- Location: FF_X47_Y15_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(10)); + +-- Location: MLABCELL_X45_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[10]~feeder_combout\); + +-- Location: FF_X45_Y15_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(10)); + +-- Location: LABCELL_X47_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[10]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(10) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[10]~feeder_combout\); + +-- Location: FF_X47_Y15_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(10)); + +-- Location: FF_X47_Y15_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(10)); + +-- Location: LABCELL_X47_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(10)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(10)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(10)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(10)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~1_combout\); + +-- Location: LABCELL_X50_Y13_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[10]~feeder_combout\); + +-- Location: FF_X50_Y13_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(10)); + +-- Location: LABCELL_X50_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[10]~feeder_combout\); + +-- Location: FF_X50_Y13_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(10)); + +-- Location: FF_X50_Y13_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(10)); + +-- Location: FF_X49_Y13_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(10)); + +-- Location: LABCELL_X50_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(10) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(10)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(10))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(10) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(10))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(10) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(10) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(10) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101001000101010111101110111000001010111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~0_combout\); + +-- Location: LABCELL_X50_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux83~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux83~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~2_combout\); + +-- Location: FF_X50_Y15_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(10)); + +-- Location: FF_X41_Y27_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_OTERM2307\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(10)); + +-- Location: MLABCELL_X37_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~3_combout\); + +-- Location: MLABCELL_X37_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~0_combout\); + +-- Location: LABCELL_X36_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101000000000000111100110011010101011111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~2_combout\); + +-- Location: LABCELL_X36_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000100010001000100000011110011111101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~1_combout\); + +-- Location: LABCELL_X36_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12930\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ +-- & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~1_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101001000101010111101110111000001010111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\); + +-- Location: MLABCELL_X42_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~5_combout\); + +-- Location: MLABCELL_X42_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~6_combout\); + +-- Location: LABCELL_X41_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~7_combout\); + +-- Location: LABCELL_X41_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~8_combout\); + +-- Location: MLABCELL_X42_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~5_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~7_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~8_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000011110011001111111111010101010000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~9_combout\); + +-- Location: LABCELL_X41_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12932\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(10))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(10))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010011000000000101010110100011111100111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\); + +-- Location: LABCELL_X41_Y27_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_OTERM2307\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_OTERM2307\); + +-- Location: FF_X41_Y27_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_OTERM2307\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE_q\); + +-- Location: FF_X43_Y26_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(10)); + +-- Location: FF_X43_Y26_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(10)); + +-- Location: FF_X42_Y26_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(10)); + +-- Location: FF_X42_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(10)); + +-- Location: MLABCELL_X42_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(10))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(10))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~0_combout\); + +-- Location: MLABCELL_X49_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[10]~feeder_combout\); + +-- Location: FF_X49_Y27_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(10)); + +-- Location: FF_X50_Y27_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(10)); + +-- Location: LABCELL_X48_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[10]~feeder_combout\); + +-- Location: FF_X48_Y30_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(10)); + +-- Location: FF_X50_Y27_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(10)); + +-- Location: LABCELL_X50_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(10))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(10))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~1_combout\); + +-- Location: LABCELL_X50_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux275~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux275~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~2_combout\); + +-- Location: FF_X50_Y27_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(10)); + +-- Location: LABCELL_X50_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(10) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(10)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(10))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(10)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(10))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000100010001000100000101101011111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~0_combout\); + +-- Location: LABCELL_X47_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(6)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(6)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010001001110010011101010101111111110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]~81_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector98~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~1_combout\); + +-- Location: FF_X47_Y11_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_NEW_REG815\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM816\); + +-- Location: LABCELL_X47_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM814\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM816\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM814\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM816\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM814\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM816\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111011101110100100010001000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]_OTERM814\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]_OTERM816\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\); + +-- Location: FF_X19_Y33_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~90_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\); + +-- Location: FF_X19_Y31_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~82_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\); + +-- Location: FF_X19_Y33_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~86_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\); + +-- Location: LABCELL_X39_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~0_combout\); + +-- Location: FF_X19_Y32_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~78_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\); + +-- Location: FF_X19_Y32_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~80_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\); + +-- Location: LABCELL_X39_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~1_combout\); + +-- Location: LABCELL_X39_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12890\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12890_BDD12891\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011000011111101010101010101010000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1497~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1497~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12890_BDD12891\); + +-- Location: LABCELL_X35_Y36_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12892\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12890_BDD12891\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12890_BDD12891\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[11]_NEW2286_RESYN12890_BDD12891\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\); + +-- Location: LABCELL_X35_Y36_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_OTERM2287\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_OTERM2287\); + +-- Location: FF_X35_Y36_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_OTERM2287\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11)); + +-- Location: FF_X43_Y16_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(11)); + +-- Location: FF_X43_Y16_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(11)); + +-- Location: LABCELL_X44_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[11]~feeder_combout\); + +-- Location: FF_X44_Y16_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(11)); + +-- Location: FF_X43_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(11)); + +-- Location: LABCELL_X43_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(11)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(11)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(11)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~0_combout\); + +-- Location: FF_X48_Y24_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(11)); + +-- Location: FF_X48_Y24_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(11)); + +-- Location: FF_X48_Y24_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(11)); + +-- Location: LABCELL_X50_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[11]~feeder_combout\); + +-- Location: FF_X50_Y29_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(11)); + +-- Location: LABCELL_X48_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(11) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(11))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(11)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(11))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(11) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(11) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(11)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(11) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(11) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110000000001010011111111110101001100001111010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~1_combout\); + +-- Location: LABCELL_X52_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux146~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux146~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~2_combout\); + +-- Location: FF_X52_Y24_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(11)); + +-- Location: FF_X41_Y27_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_OTERM2289\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(11)); + +-- Location: FF_X21_Y29_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~65_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\); + +-- Location: FF_X21_Y29_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~68_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~0_combout\); + +-- Location: FF_X21_Y29_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~71_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\); + +-- Location: FF_X21_Y29_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~69_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\); + +-- Location: FF_X21_Y29_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~72_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~2_combout\); + +-- Location: LABCELL_X41_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~1_combout\); + +-- Location: LABCELL_X41_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~3_combout\); + +-- Location: LABCELL_X41_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~0_combout\))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~2_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101001000110110011110001001110011011010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~4_combout\); + +-- Location: LABCELL_X41_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~6_combout\); + +-- Location: FF_X19_Y33_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~83_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\); + +-- Location: FF_X19_Y33_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~85_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~7_combout\); + +-- Location: LABCELL_X40_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~8_combout\); + +-- Location: FF_X19_Y33_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~89_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\); + +-- Location: FF_X19_Y33_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~88_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\); + +-- Location: FF_X19_Y33_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~87_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\); + +-- Location: LABCELL_X40_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~5_combout\); + +-- Location: LABCELL_X41_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~6_combout\))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~5_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~6_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011101010100001101101010101000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~9_combout\); + +-- Location: LABCELL_X40_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12894\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12894_BDD12895\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101000000010000110111101111001011111110111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12894_BDD12895\); + +-- Location: LABCELL_X41_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12896\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(11) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12894_BDD12895\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(11) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12894_BDD12895\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]_NEW2288_RESYN12894_BDD12895\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\); + +-- Location: LABCELL_X41_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_OTERM2289\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_OTERM2289\); + +-- Location: FF_X41_Y27_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_OTERM2289\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE_q\); + +-- Location: LABCELL_X48_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[11]~feeder_combout\); + +-- Location: FF_X48_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(11)); + +-- Location: FF_X47_Y26_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(11)); + +-- Location: FF_X48_Y26_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(11)); + +-- Location: LABCELL_X48_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[11]~feeder_combout\); + +-- Location: FF_X48_Y26_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(11)); + +-- Location: LABCELL_X48_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(11) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(11)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(11))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(11) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(11))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(11) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(11) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(11) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000011010001001100111101110111000000110111011111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~0_combout\); + +-- Location: LABCELL_X50_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[11]~feeder_combout\); + +-- Location: FF_X50_Y25_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(11)); + +-- Location: LABCELL_X47_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[11]~feeder_combout\); + +-- Location: FF_X47_Y25_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(11)); + +-- Location: FF_X50_Y25_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(11)); + +-- Location: LABCELL_X50_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[11]~feeder_combout\); + +-- Location: FF_X50_Y25_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(11)); + +-- Location: LABCELL_X50_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(11) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(11))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(11))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(11))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100000001111100011100110100111101000011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~1_combout\); + +-- Location: LABCELL_X52_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux210~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux210~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~2_combout\); + +-- Location: FF_X52_Y24_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(11)); + +-- Location: MLABCELL_X34_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~18_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110010001000100111001000100010011100100010001001110010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~18_combout\); + +-- Location: LABCELL_X39_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101000100110011110100010000000011011101111100111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\); + +-- Location: LABCELL_X41_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111100110000000000001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\); + +-- Location: MLABCELL_X34_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001000000000000001100000001111111011111110011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~29_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\); + +-- Location: LABCELL_X39_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365_BDD9366\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110000000001010011111111110101001100001111010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365_BDD9366\); + +-- Location: MLABCELL_X34_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000100010001000100010001000100011001100110011001100000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\); + +-- Location: MLABCELL_X34_Y27_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9297\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9297_BDD9298\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100001111111111110000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9297_BDD9298\); + +-- Location: MLABCELL_X34_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9295\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9295_BDD9296\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101100010001101110110001000110110001000100011011000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9295_BDD9296\); + +-- Location: MLABCELL_X34_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9295_BDD9296\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9297_BDD9298\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9295_BDD9296\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9297_BDD9298\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111001110111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_RESYN9297_BDD9298\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_RESYN9295_BDD9296\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_combout\); + +-- Location: MLABCELL_X34_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365_BDD9366\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365_BDD9366\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000001111111111101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365_BDD9366\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\); + +-- Location: MLABCELL_X34_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_OTERM3230\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~18_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~18_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~18_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~18_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110001110011001111110100000010001100111100111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~18_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_OTERM3230\); + +-- Location: FF_X34_Y27_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_OTERM3230\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11)); + +-- Location: FF_X47_Y15_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(11)); + +-- Location: LABCELL_X48_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[11]~feeder_combout\); + +-- Location: FF_X48_Y15_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(11)); + +-- Location: LABCELL_X43_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[11]~feeder_combout\); + +-- Location: FF_X43_Y18_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(11)); + +-- Location: FF_X48_Y15_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(11)); + +-- Location: LABCELL_X48_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(11) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(11))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(11))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~1_combout\); + +-- Location: LABCELL_X53_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[11]~feeder_combout\); + +-- Location: FF_X53_Y17_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(11)); + +-- Location: FF_X53_Y15_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(11)); + +-- Location: LABCELL_X53_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[11]~feeder_combout\); + +-- Location: FF_X53_Y17_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(11)); + +-- Location: FF_X53_Y17_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(11)); + +-- Location: LABCELL_X53_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(11))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(11))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(11)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(11)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~0_combout\); + +-- Location: LABCELL_X52_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux82~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux82~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~2_combout\); + +-- Location: FF_X52_Y17_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(11)); + +-- Location: LABCELL_X41_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~1_combout\); + +-- Location: LABCELL_X41_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~2_combout\); + +-- Location: LABCELL_X41_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~3_combout\); + +-- Location: LABCELL_X36_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~0_combout\); + +-- Location: LABCELL_X40_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12898\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~2_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101000100110011110100010000000011011101111100111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\); + +-- Location: LABCELL_X41_Y33_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~7_combout\); + +-- Location: LABCELL_X41_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~6_combout\); + +-- Location: LABCELL_X40_Y33_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~5_combout\); + +-- Location: LABCELL_X40_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~8_combout\); + +-- Location: MLABCELL_X42_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~5_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~8_combout\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111010101010011001111111111000011110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~9_combout\); + +-- Location: LABCELL_X41_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12900\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~9_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11) & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000010100110101010110100011101010101111001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\); + +-- Location: LABCELL_X41_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_OTERM2291\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_OTERM2291\); + +-- Location: FF_X41_Y27_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_OTERM2291\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11)); + +-- Location: LABCELL_X53_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[11]~feeder_combout\); + +-- Location: FF_X53_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(11)); + +-- Location: LABCELL_X48_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[11]~feeder_combout\); + +-- Location: FF_X48_Y19_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(11)); + +-- Location: LABCELL_X53_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[11]~feeder_combout\); + +-- Location: FF_X53_Y19_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(11)); + +-- Location: FF_X53_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(11)); + +-- Location: LABCELL_X53_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(11)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(11)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(11)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~0_combout\); + +-- Location: MLABCELL_X49_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[11]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[11]~feeder_combout\); + +-- Location: FF_X49_Y19_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(11)); + +-- Location: FF_X49_Y19_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(11)); + +-- Location: LABCELL_X48_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[11]~feeder_combout\); + +-- Location: FF_X48_Y19_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(11)); + +-- Location: FF_X48_Y19_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(11)); + +-- Location: LABCELL_X48_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(11) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(11))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(11))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~1_combout\); + +-- Location: LABCELL_X50_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux274~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux274~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~2_combout\); + +-- Location: FF_X50_Y21_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(11)); + +-- Location: LABCELL_X52_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(11)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(11))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(11))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~0_combout\); + +-- Location: LABCELL_X48_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(7)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100010001110100011100110011111111110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]~77_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector97~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~1_combout\); + +-- Location: FF_X48_Y11_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_NEW_REG807\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM808\); + +-- Location: LABCELL_X48_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM808\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM806\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM808\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM806\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001111000000001100111100110000111111110011000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM806\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM808\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\); + +-- Location: FF_X32_Y26_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\); + +-- Location: FF_X35_Y22_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[15]_NEW_REG1568\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[15]_OTERM1569\); + +-- Location: LABCELL_X35_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[15]_OTERM1569\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM435\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[15]_OTERM1569\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM435\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[15]_OTERM1569\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM435\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101000001000000000000000001000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM437\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[15]_OTERM1569\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM435\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\); + +-- Location: FF_X42_Y12_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(15)); + +-- Location: FF_X41_Y12_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(15)); + +-- Location: LABCELL_X43_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[15]~feeder_combout\); + +-- Location: FF_X43_Y18_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(15)); + +-- Location: FF_X42_Y12_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(15)); + +-- Location: MLABCELL_X42_Y12_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(15)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(15)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(15))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(15))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~1_combout\); + +-- Location: LABCELL_X50_Y13_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[15]~feeder_combout\); + +-- Location: FF_X50_Y13_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(15)); + +-- Location: FF_X49_Y13_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(15)); + +-- Location: FF_X49_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(15)); + +-- Location: LABCELL_X44_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[15]~feeder_combout\); + +-- Location: FF_X44_Y16_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(15)); + +-- Location: MLABCELL_X49_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(15)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(15)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(15)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(15))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(15))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(15))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011010001010110011110001001101010111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~0_combout\); + +-- Location: MLABCELL_X49_Y13_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux142~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux142~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~2_combout\); + +-- Location: FF_X49_Y13_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(15)); + +-- Location: FF_X32_Y26_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG326\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM327\); + +-- Location: FF_X32_Y26_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG330\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\); + +-- Location: LABCELL_X31_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~2_combout\); + +-- Location: LABCELL_X31_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~2_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000001001100110011001100110011000000000011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~0_combout\); + +-- Location: FF_X31_Y34_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG336\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\); + +-- Location: FF_X32_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG334\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM335\); + +-- Location: FF_X31_Y26_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG328\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~69_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM329\); + +-- Location: LABCELL_X32_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM335\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM329\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM327\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM335\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM329\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM327\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM327\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\))) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM335\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM329\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM327\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM327\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM335\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM329\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM327\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001111100010001111100010001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM327\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM333\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM337\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM335\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM329\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\); + +-- Location: LABCELL_X41_Y12_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[15]~feeder_combout\); + +-- Location: FF_X41_Y12_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(15)); + +-- Location: LABCELL_X41_Y12_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[15]~feeder_combout\); + +-- Location: FF_X41_Y12_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(15)); + +-- Location: FF_X41_Y12_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(15)); + +-- Location: MLABCELL_X37_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[15]~feeder_combout\); + +-- Location: FF_X37_Y18_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(15)); + +-- Location: LABCELL_X41_Y12_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(15))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(15)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(15) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(15) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(15)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(15) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(15) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010000100010101111110111011000010101011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~1_combout\); + +-- Location: MLABCELL_X42_Y13_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[15]~feeder_combout\); + +-- Location: FF_X42_Y13_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(15)); + +-- Location: MLABCELL_X49_Y13_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[15]~feeder_combout\); + +-- Location: FF_X49_Y13_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(15)); + +-- Location: MLABCELL_X42_Y13_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[15]~feeder_combout\); + +-- Location: FF_X42_Y13_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(15)); + +-- Location: FF_X49_Y13_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(15)); + +-- Location: MLABCELL_X49_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(15)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(15)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(15)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(15) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~0_combout\); + +-- Location: LABCELL_X48_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux78~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux78~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~2_combout\); + +-- Location: FF_X48_Y13_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(15)); + +-- Location: MLABCELL_X49_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(15) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(15)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110001000100010001000100010001000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~0_combout\); + +-- Location: FF_X49_Y11_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_NEW_REG829\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM830\); + +-- Location: FF_X32_Y26_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_NEW_REG342\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM343\); + +-- Location: LABCELL_X32_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339~feeder_combout\); + +-- Location: FF_X32_Y26_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_NEW_REG338\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339\); + +-- Location: LABCELL_X32_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011001100110011001100000011000000110011001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~0_combout\); + +-- Location: FF_X32_Y26_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_NEW_REG344\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM345\); + +-- Location: FF_X31_Y26_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_NEW_REG340\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~65_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM341\); + +-- Location: LABCELL_X32_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM341\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM345\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM343\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000010100110111000001010011011111111111111111110000010100110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM337\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM343\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM339\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM333\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM345\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM341\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\); + +-- Location: MLABCELL_X42_Y12_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1432~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[14]~feeder_combout\); + +-- Location: FF_X42_Y12_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[14]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(14)); + +-- Location: LABCELL_X40_Y12_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1432~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[14]~feeder_combout\); + +-- Location: FF_X40_Y12_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[14]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(14)); + +-- Location: LABCELL_X39_Y12_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1432~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[14]~feeder_combout\); + +-- Location: FF_X39_Y12_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[14]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(14)); + +-- Location: FF_X42_Y12_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(14)); + +-- Location: MLABCELL_X42_Y12_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(14)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(14)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(14))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(14))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(14), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~1_combout\); + +-- Location: LABCELL_X40_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1432~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[14]~feeder_combout\); + +-- Location: FF_X40_Y12_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[14]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(14)); + +-- Location: MLABCELL_X42_Y12_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1432~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[14]~feeder_combout\); + +-- Location: FF_X42_Y12_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[14]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(14)); + +-- Location: LABCELL_X40_Y12_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1432~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[14]~feeder_combout\); + +-- Location: FF_X40_Y12_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[14]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(14)); + +-- Location: FF_X45_Y12_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(14)); + +-- Location: MLABCELL_X45_Y12_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(14)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(14) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(14))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(14))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(14), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~0_combout\); + +-- Location: MLABCELL_X45_Y12_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux79~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux79~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~2_combout\); + +-- Location: FF_X45_Y12_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(14)); + +-- Location: MLABCELL_X45_Y12_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~0_combout\); + +-- Location: FF_X47_Y11_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_NEW_REG825\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM826\); + +-- Location: LABCELL_X40_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~7_combout\); + +-- Location: FF_X20_Y30_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~173_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\); + +-- Location: LABCELL_X40_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~8_combout\); + +-- Location: FF_X23_Y29_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~182_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~6_combout\); + +-- Location: FF_X20_Y30_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~180_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\); + +-- Location: FF_X23_Y29_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~178_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\); + +-- Location: FF_X20_Y30_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~181_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~5_combout\); + +-- Location: MLABCELL_X37_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010001000100111011101011111010111110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~9_combout\); + +-- Location: FF_X43_Y28_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_OTERM2329\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(13)); + +-- Location: FF_X25_Y31_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~167_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~1_combout\); + +-- Location: FF_X23_Y29_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~161_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~2_combout\); + +-- Location: MLABCELL_X42_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111100111111001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~3_combout\); + +-- Location: MLABCELL_X42_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~0_combout\); + +-- Location: LABCELL_X41_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12974\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010101110110000101000010001010111111011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\); + +-- Location: LABCELL_X43_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12976\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(13))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~9_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(13))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110101001100000011000000101010011111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\); + +-- Location: LABCELL_X43_Y28_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_OTERM2329\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000001101110111111101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_OTERM2329\); + +-- Location: FF_X43_Y28_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_OTERM2329\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE_q\); + +-- Location: FF_X45_Y28_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(13)); + +-- Location: FF_X47_Y28_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(13)); + +-- Location: FF_X49_Y29_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(13)); + +-- Location: FF_X50_Y28_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(13)); + +-- Location: LABCELL_X50_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(13) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(13)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(13)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~0_combout\); + +-- Location: MLABCELL_X49_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[13]~feeder_combout\); + +-- Location: FF_X49_Y28_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(13)); + +-- Location: MLABCELL_X49_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[13]~feeder_combout\); + +-- Location: FF_X49_Y28_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(13)); + +-- Location: MLABCELL_X49_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[13]~feeder_combout\); + +-- Location: FF_X49_Y28_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(13)); + +-- Location: FF_X50_Y28_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(13)); + +-- Location: LABCELL_X50_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(13) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(13)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(13)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~1_combout\); + +-- Location: LABCELL_X50_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111111111111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux272~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux272~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~2_combout\); + +-- Location: FF_X50_Y28_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(13)); + +-- Location: MLABCELL_X42_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9035\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9035_BDD9036\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010000100011011101111111111111111110001000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9035_BDD9036\); + +-- Location: LABCELL_X39_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9037\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9037_BDD9038\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000011000011111111011101110111010000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9037_BDD9038\); + +-- Location: MLABCELL_X42_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9039\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9039_BDD9040\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9037_BDD9038\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9035_BDD9036\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9037_BDD9038\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9035_BDD9036\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9037_BDD9038\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9035_BDD9036\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9037_BDD9038\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9035_BDD9036\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000111000000000000111111111111000001111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9035_BDD9036\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9037_BDD9038\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9039_BDD9040\); + +-- Location: LABCELL_X35_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9039_BDD9040\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9039_BDD9040\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000001100000001000000110000110111001111110011011100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9039_BDD9040\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_combout\); + +-- Location: MLABCELL_X34_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[13]_NEW3241\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[13]_OTERM3242\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~61_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(13) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~61_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[13]_OTERM3242\); + +-- Location: FF_X34_Y27_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[13]_OTERM3242\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(13)); + +-- Location: LABCELL_X50_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[13]~feeder_combout\); + +-- Location: FF_X50_Y19_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(13)); + +-- Location: FF_X49_Y19_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(13)); + +-- Location: FF_X50_Y19_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(13)); + +-- Location: LABCELL_X50_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[13]~feeder_combout\); + +-- Location: FF_X50_Y19_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(13)); + +-- Location: LABCELL_X50_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(13) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(13) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(13) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(13))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(13)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001110011001101000111110011000100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~1_combout\); + +-- Location: LABCELL_X53_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[13]~feeder_combout\); + +-- Location: FF_X53_Y19_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(13)); + +-- Location: LABCELL_X53_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[13]~feeder_combout\); + +-- Location: FF_X53_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(13)); + +-- Location: FF_X53_Y19_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(13)); + +-- Location: LABCELL_X53_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[13]~feeder_combout\); + +-- Location: FF_X53_Y20_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(13)); + +-- Location: LABCELL_X53_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(13))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(13))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(13) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(13) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(13))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(13)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111001100110100011111001100010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~0_combout\); + +-- Location: LABCELL_X50_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux80~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux80~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~2_combout\); + +-- Location: FF_X50_Y22_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(13)); + +-- Location: MLABCELL_X42_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~1_combout\); + +-- Location: LABCELL_X39_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~0_combout\); + +-- Location: LABCELL_X39_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12966\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12966_BDD12967\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001000000011111000100001011000010110000101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1495~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1495~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12966_BDD12967\); + +-- Location: FF_X40_Y35_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_OTERM2325\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(13)); + +-- Location: LABCELL_X40_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12968\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(13) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12966_BDD12967\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(13) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12966_BDD12967\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100101111001011110010111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]_NEW2324_RESYN12966_BDD12967\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\); + +-- Location: LABCELL_X40_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_OTERM2325\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011110111111100111100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_OTERM2325\); + +-- Location: FF_X40_Y35_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_OTERM2325\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE_q\); + +-- Location: LABCELL_X40_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[13]~feeder_combout\); + +-- Location: FF_X40_Y22_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(13)); + +-- Location: MLABCELL_X49_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[13]~feeder_combout\); + +-- Location: FF_X49_Y23_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(13)); + +-- Location: MLABCELL_X49_Y23_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[13]~feeder_combout\); + +-- Location: FF_X49_Y23_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(13)); + +-- Location: FF_X49_Y23_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(13)); + +-- Location: MLABCELL_X49_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(13)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(13))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(13))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~0_combout\); + +-- Location: FF_X50_Y22_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(13)); + +-- Location: MLABCELL_X49_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[13]~feeder_combout\); + +-- Location: FF_X49_Y22_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(13)); + +-- Location: MLABCELL_X49_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[13]~feeder_combout\); + +-- Location: FF_X49_Y22_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(13)); + +-- Location: FF_X50_Y22_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(13)); + +-- Location: LABCELL_X50_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(13) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(13))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(13))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~1_combout\); + +-- Location: LABCELL_X50_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux144~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux144~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~2_combout\); + +-- Location: FF_X50_Y22_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(13)); + +-- Location: MLABCELL_X42_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~3_combout\); + +-- Location: LABCELL_X41_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~1_combout\); + +-- Location: MLABCELL_X42_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~2_combout\); + +-- Location: MLABCELL_X42_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~0_combout\); + +-- Location: MLABCELL_X42_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\))) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~1_combout\))))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100001010100110111000011001010111010011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~4_combout\); + +-- Location: LABCELL_X40_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~8_combout\); + +-- Location: LABCELL_X40_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011110011001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~7_combout\); + +-- Location: LABCELL_X41_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~6_combout\); + +-- Location: LABCELL_X41_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~5_combout\); + +-- Location: LABCELL_X39_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~7_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~7_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000110010101110100101010011011100011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~9_combout\); + +-- Location: LABCELL_X41_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12970\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12970_BDD12971\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101000000010000110111101111001011111110111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12970_BDD12971\); + +-- Location: LABCELL_X41_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12972\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12970_BDD12971\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12970_BDD12971\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[13]_NEW2326_RESYN12970_BDD12971\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\); + +-- Location: LABCELL_X41_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_OTERM2327\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_OTERM2327\); + +-- Location: FF_X41_Y27_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_OTERM2327\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13)); + +-- Location: FF_X42_Y24_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(13)); + +-- Location: MLABCELL_X42_Y24_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[13]~feeder_combout\); + +-- Location: FF_X42_Y24_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(13)); + +-- Location: FF_X43_Y24_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(13)); + +-- Location: FF_X43_Y24_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(13)); + +-- Location: LABCELL_X43_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(13)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(13)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(13))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(13) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(13)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(13) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(13))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001010010000001110101011110100010111100101010011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~1_combout\); + +-- Location: FF_X45_Y20_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(13)); + +-- Location: LABCELL_X48_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[13]~feeder_combout\); + +-- Location: FF_X48_Y20_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(13)); + +-- Location: FF_X48_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(13)); + +-- Location: LABCELL_X48_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[13]~feeder_combout\); + +-- Location: FF_X48_Y20_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(13)); + +-- Location: LABCELL_X48_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(13)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(13)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(13)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(13)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(13) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(13) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111000001000011011100110100110001111100010011110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~0_combout\); + +-- Location: LABCELL_X50_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux208~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux208~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~2_combout\); + +-- Location: FF_X50_Y22_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(13)); + +-- Location: LABCELL_X50_Y22_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(13)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(13)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(13)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(13)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~0_combout\); + +-- Location: FF_X48_Y11_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_NEW_REG821\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM822\); + +-- Location: FF_X21_Y31_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~139_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\); + +-- Location: FF_X21_Y31_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~138_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\); + +-- Location: LABCELL_X25_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~1_combout\); + +-- Location: FF_X21_Y33_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~143_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\); + +-- Location: FF_X21_Y33_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~151_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\); + +-- Location: LABCELL_X21_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~0_combout\); + +-- Location: LABCELL_X29_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12946\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12946_BDD12947\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~1_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010000100010001101101000100010011100101010101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1496~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1496~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12946_BDD12947\); + +-- Location: LABCELL_X35_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12948\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12946_BDD12947\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12946_BDD12947\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[12]_NEW2314_RESYN12946_BDD12947\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\); + +-- Location: LABCELL_X35_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_OTERM2315\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_OTERM2315\); + +-- Location: FF_X35_Y36_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_OTERM2315\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12)); + +-- Location: FF_X49_Y29_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(12)); + +-- Location: MLABCELL_X49_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[12]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[12]~feeder_combout\); + +-- Location: FF_X49_Y29_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(12)); + +-- Location: LABCELL_X48_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[12]~feeder_combout\); + +-- Location: FF_X48_Y29_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(12)); + +-- Location: FF_X49_Y29_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(12)); + +-- Location: MLABCELL_X49_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(12))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(12))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(12)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(12)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010010101011111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~0_combout\); + +-- Location: FF_X48_Y30_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(12)); + +-- Location: FF_X48_Y30_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(12)); + +-- Location: FF_X49_Y30_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(12)); + +-- Location: FF_X49_Y30_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(12)); + +-- Location: MLABCELL_X49_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(12) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(12))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(12))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(12))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010100010000001111010011101010010111100100101011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~1_combout\); + +-- Location: LABCELL_X50_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux145~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux145~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~2_combout\); + +-- Location: FF_X50_Y23_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(12)); + +-- Location: FF_X21_Y33_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~142_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~8_combout\); + +-- Location: FF_X23_Y31_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~145_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\); + +-- Location: FF_X23_Y31_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~146_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~7_combout\); + +-- Location: FF_X24_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~155_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\); + +-- Location: FF_X23_Y31_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~152_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\); + +-- Location: FF_X23_Y31_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~153_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~6_combout\); + +-- Location: FF_X21_Y33_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~148_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\); + +-- Location: FF_X21_Y33_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~150_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~5_combout\); + +-- Location: MLABCELL_X42_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~7_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\)))) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~7_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~7_combout\))))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000000001001110101010100100111101010100010011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~9_combout\); + +-- Location: FF_X23_Y29_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~136_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~1_combout\); + +-- Location: FF_X20_Y29_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~127_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~0_combout\); + +-- Location: MLABCELL_X42_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~3_combout\); + +-- Location: FF_X20_Y29_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~133_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\); + +-- Location: FF_X20_Y29_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~130_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\); + +-- Location: FF_X20_Y29_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~131_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~2_combout\); + +-- Location: LABCELL_X41_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~0_combout\)))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~0_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111110011000100011100110011010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~4_combout\); + +-- Location: LABCELL_X41_Y27_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12950\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12950_BDD12951\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~4_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~9_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111000000010000011100000001000011111110111110001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12950_BDD12951\); + +-- Location: LABCELL_X41_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12952\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12950_BDD12951\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12950_BDD12951\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[12]_NEW2316_RESYN12950_BDD12951\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\); + +-- Location: LABCELL_X41_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_OTERM2317\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_OTERM2317\); + +-- Location: FF_X41_Y27_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_OTERM2317\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12)); + +-- Location: LABCELL_X48_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[12]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[12]~feeder_combout\); + +-- Location: FF_X48_Y24_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(12)); + +-- Location: LABCELL_X48_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[12]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[12]~feeder_combout\); + +-- Location: FF_X48_Y24_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(12)); + +-- Location: FF_X48_Y24_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(12)); + +-- Location: FF_X49_Y24_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(12)); + +-- Location: LABCELL_X48_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(12))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(12)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(12)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(12))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011100000100110001111111010000110111001101001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~1_combout\); + +-- Location: FF_X50_Y23_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(12)); + +-- Location: MLABCELL_X49_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[12]~feeder_combout\); + +-- Location: FF_X49_Y23_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(12)); + +-- Location: MLABCELL_X49_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[12]~feeder_combout\); + +-- Location: FF_X49_Y23_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(12)); + +-- Location: FF_X49_Y23_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(12)); + +-- Location: MLABCELL_X49_Y23_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(12)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(12)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(12))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(12))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~0_combout\); + +-- Location: LABCELL_X50_Y23_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux209~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux209~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~2_combout\); + +-- Location: FF_X50_Y23_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(12)); + +-- Location: FF_X43_Y28_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_OTERM2319\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(12)); + +-- Location: MLABCELL_X42_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~3_combout\); + +-- Location: LABCELL_X41_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~0_combout\); + +-- Location: LABCELL_X41_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~1_combout\); + +-- Location: MLABCELL_X42_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~2_combout\); + +-- Location: LABCELL_X41_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12954\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ +-- & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~2_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~1_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000011011101110000001101000100110011110111011111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\); + +-- Location: MLABCELL_X42_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~8_combout\); + +-- Location: LABCELL_X43_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~6_combout\); + +-- Location: MLABCELL_X42_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~7_combout\); + +-- Location: LABCELL_X43_Y31_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~5_combout\); + +-- Location: LABCELL_X43_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~7_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~9_combout\); + +-- Location: LABCELL_X43_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12956\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~9_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(12)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(12))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(12))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100000011110100011111110000011101001111111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\); + +-- Location: LABCELL_X43_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_OTERM2319\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011101010101001010001010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_OTERM2319\); + +-- Location: FF_X43_Y28_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_OTERM2319\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE_q\); + +-- Location: FF_X49_Y19_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(12)); + +-- Location: MLABCELL_X49_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[12]~feeder_combout\); + +-- Location: FF_X49_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(12)); + +-- Location: LABCELL_X52_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[12]~feeder_combout\); + +-- Location: FF_X52_Y18_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(12)); + +-- Location: FF_X49_Y19_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(12)); + +-- Location: MLABCELL_X49_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(12)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(12)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(12))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(12))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~1_combout\); + +-- Location: FF_X50_Y23_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(12)); + +-- Location: FF_X49_Y23_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(12)); + +-- Location: FF_X50_Y23_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(12)); + +-- Location: FF_X44_Y14_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(12)); + +-- Location: LABCELL_X50_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(12))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(12))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(12) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(12) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(12))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(12) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(12)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111010101010010011110101010001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~0_combout\); + +-- Location: LABCELL_X50_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux273~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux273~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~2_combout\); + +-- Location: FF_X50_Y23_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(12)); + +-- Location: MLABCELL_X42_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000000000101010100011011000110111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~1_combout\); + +-- Location: LABCELL_X43_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9041\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9041_BDD9042\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000011001010011000101110100101010001110110110111001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9041_BDD9042\); + +-- Location: LABCELL_X43_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9043\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9043_BDD9044\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9041_BDD9042\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~1_combout\) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9041_BDD9042\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_RESYN9041_BDD9042\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9043_BDD9044\); + +-- Location: LABCELL_X35_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9043_BDD9044\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9043_BDD9044\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9043_BDD9044\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9043_BDD9044\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001110011000000000011001101001100011111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_RESYN9043_BDD9044\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_combout\); + +-- Location: LABCELL_X35_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[12]_NEW3237\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[12]_OTERM3238\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(12))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~33_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[12]_OTERM3238\); + +-- Location: FF_X35_Y27_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[12]_OTERM3238\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(12)); + +-- Location: LABCELL_X47_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[12]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(12) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[12]~feeder_combout\); + +-- Location: FF_X47_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(12)); + +-- Location: FF_X47_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(12)); + +-- Location: FF_X41_Y15_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(12)); + +-- Location: FF_X47_Y15_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(12)); + +-- Location: LABCELL_X47_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(12)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(12)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(12))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(12))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~1_combout\); + +-- Location: FF_X50_Y13_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(12)); + +-- Location: FF_X49_Y13_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(12)); + +-- Location: FF_X50_Y13_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(12)); + +-- Location: FF_X48_Y13_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(12)); + +-- Location: LABCELL_X50_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(12) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(12) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(12))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(12)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(12) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(12)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100111111000001010011000011110101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~0_combout\); + +-- Location: LABCELL_X50_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux81~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux81~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~2_combout\); + +-- Location: FF_X50_Y15_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(12)); + +-- Location: LABCELL_X50_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(12))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(12)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(12)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(12))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(12) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(12)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000001011010111110111011101110110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~0_combout\); + +-- Location: LABCELL_X48_Y11_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(4) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111001100110000000001010101000011110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]~76_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]~84_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector96~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~1_combout\); + +-- Location: FF_X48_Y11_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_NEW_REG823\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~1_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM824\); + +-- Location: LABCELL_X48_Y11_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM824\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM822\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM824\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM822\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011011101000000001101110100100010111111110010001011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]_OTERM822\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]_OTERM824\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\); + +-- Location: LABCELL_X48_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100000000111100111101110111011101110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]~81_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector95~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]~75_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~1_combout\); + +-- Location: FF_X48_Y11_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_NEW_REG827\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM828\); + +-- Location: LABCELL_X47_Y11_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM826\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM828\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM826\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM828\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM826\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM828\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111111100001111000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]_OTERM826\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]_OTERM828\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\); + +-- Location: FF_X47_Y11_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~80_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~DUPLICATE_q\); + +-- Location: LABCELL_X47_Y11_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110100001010100011111000100001011101010110101101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector94~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]~77_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]~72_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~1_combout\); + +-- Location: FF_X47_Y11_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_NEW_REG831\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM832\); + +-- Location: MLABCELL_X49_Y11_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM830\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM832\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM830\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM832\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM830\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM832\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110111011101101000100010001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]_OTERM830\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]_OTERM832\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\); + +-- Location: MLABCELL_X49_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000011010111110000001101010000111100110101111111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]~84_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector93~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]~70_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~1_combout\); + +-- Location: FF_X49_Y11_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_NEW_REG835\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_OTERM836\); + +-- Location: FF_X49_Y11_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_NEW_REG833\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_OTERM834\); + +-- Location: MLABCELL_X49_Y11_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_OTERM834\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_OTERM836\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_OTERM834\))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010111111000001001011111100000100101111110000010010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]_OTERM836\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]_OTERM834\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\); + +-- Location: LABCELL_X36_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux418~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~0_combout\); + +-- Location: MLABCELL_X42_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux418~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~1_combout\); + +-- Location: LABCELL_X35_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux418~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux418~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100000011000000000011000000110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux418~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux418~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~0_combout\); + +-- Location: FF_X35_Y22_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_NEW_REG931\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM932\); + +-- Location: FF_X35_Y22_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_NEW_REG929\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM930\); + +-- Location: LABCELL_X35_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM930\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM932\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM930\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM932\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100111111000011110011111100001111001011110000111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[16]_OTERM932\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[16]_OTERM930\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM437\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\); + +-- Location: FF_X40_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(16)); + +-- Location: FF_X40_Y17_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(16)); + +-- Location: FF_X40_Y17_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(16)); + +-- Location: FF_X41_Y17_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(16)); + +-- Location: LABCELL_X40_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(16) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(16)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(16)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(16)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(16))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(16)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(16))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(16) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(16))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000101000000111111010111110011000001011111001111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~0_combout\); + +-- Location: LABCELL_X41_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1494~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[16]~feeder_combout\); + +-- Location: FF_X41_Y15_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(16)); + +-- Location: LABCELL_X40_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1494~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[16]~feeder_combout\); + +-- Location: FF_X40_Y15_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(16)); + +-- Location: FF_X41_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(16)); + +-- Location: LABCELL_X40_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1494~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[16]~feeder_combout\); + +-- Location: FF_X40_Y15_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(16)); + +-- Location: LABCELL_X41_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(16) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(16))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(16))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(16) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(16)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001001010111010100101010011110100010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~1_combout\); + +-- Location: LABCELL_X40_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux141~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux141~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~2_combout\); + +-- Location: FF_X40_Y18_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(16)); + +-- Location: FF_X34_Y31_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_NEW_REG636\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM637\); + +-- Location: MLABCELL_X34_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100000001000000010000000100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~38_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~1_combout\); + +-- Location: MLABCELL_X34_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101000001010011010100110101001101010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~2_combout\); + +-- Location: MLABCELL_X34_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000010101010101000000000101010100000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~3_combout\); + +-- Location: FF_X34_Y33_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_NEW_REG638\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM639\); + +-- Location: MLABCELL_X34_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux362~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux362~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110110101010100011011101010100001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux362~1_combout\); + +-- Location: FF_X34_Y34_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_NEW_REG642\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux362~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM643\); + +-- Location: LABCELL_X36_Y36_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux362~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux362~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux362~0_combout\); + +-- Location: FF_X34_Y33_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_NEW_REG640\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux362~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM641\); + +-- Location: MLABCELL_X34_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM641\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM643\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM639\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM637\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM641\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM637\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM643\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM639\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM641\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM639\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM641\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM639\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100111011001110110111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM637\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM639\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM643\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM641\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\); + +-- Location: LABCELL_X53_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[16]~feeder_combout\); + +-- Location: FF_X53_Y28_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(16)); + +-- Location: LABCELL_X44_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[16]~feeder_combout\); + +-- Location: FF_X44_Y25_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(16)); + +-- Location: LABCELL_X44_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[16]~feeder_combout\); + +-- Location: FF_X44_Y25_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(16)); + +-- Location: FF_X44_Y25_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(16)); + +-- Location: LABCELL_X44_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(16)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(16))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(16))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~1_combout\); + +-- Location: FF_X45_Y19_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(16)); + +-- Location: FF_X45_Y19_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(16)); + +-- Location: FF_X45_Y19_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(16)); + +-- Location: LABCELL_X47_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[16]~feeder_combout\); + +-- Location: FF_X47_Y19_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(16)); + +-- Location: MLABCELL_X45_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(16) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(16)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(16)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(16))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(16) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(16) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(16))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(16)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(16) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(16))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101001100010011110111000001110011011111000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~0_combout\); + +-- Location: LABCELL_X50_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux77~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux77~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~2_combout\); + +-- Location: FF_X50_Y23_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(16)); + +-- Location: FF_X35_Y36_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_OTERM2522\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(16)); + +-- Location: LABCELL_X36_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~0_combout\); + +-- Location: MLABCELL_X42_Y36_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~1_combout\); + +-- Location: LABCELL_X35_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13306\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13306_BDD13307\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~0_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101000000010100010110101011111011111010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1550~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1550~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13306_BDD13307\); + +-- Location: LABCELL_X35_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13308\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(16) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13306_BDD13307\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(16) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13306_BDD13307\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]_NEW2521_RESYN13306_BDD13307\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\); + +-- Location: LABCELL_X35_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_OTERM2522\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_OTERM2522\); + +-- Location: FF_X35_Y36_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_OTERM2522\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE_q\); + +-- Location: LABCELL_X48_Y27_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[16]~feeder_combout\); + +-- Location: FF_X48_Y27_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(16)); + +-- Location: FF_X52_Y27_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(16)); + +-- Location: FF_X52_Y27_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(16)); + +-- Location: FF_X52_Y27_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(16)); + +-- Location: LABCELL_X52_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(16)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(16)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(16)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~1_combout\); + +-- Location: MLABCELL_X49_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[16]~feeder_combout\); + +-- Location: FF_X49_Y23_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(16)); + +-- Location: LABCELL_X44_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[16]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[16]~feeder_combout\); + +-- Location: FF_X44_Y26_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(16)); + +-- Location: FF_X50_Y23_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(16)); + +-- Location: FF_X50_Y23_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(16)); + +-- Location: LABCELL_X50_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(16) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(16))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(16)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(16))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(16) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(16) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(16)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(16) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(16) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000101001111110000010100110000111101010011111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~0_combout\); + +-- Location: LABCELL_X50_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux205~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux205~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~2_combout\); + +-- Location: FF_X50_Y23_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(16)); + +-- Location: LABCELL_X36_Y36_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~0_combout\); + +-- Location: MLABCELL_X42_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~1_combout\); + +-- Location: LABCELL_X20_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000001111111100000000111111110000000011111111000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\); + +-- Location: LABCELL_X25_Y36_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~2_combout\); + +-- Location: LABCELL_X26_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101101011110000010110101111000001011010111100000101101011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\); + +-- Location: LABCELL_X25_Y36_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~3_combout\); + +-- Location: LABCELL_X25_Y36_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~5_combout\); + +-- Location: LABCELL_X32_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001011111000000000101111111111111101000001111111110100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\); + +-- Location: LABCELL_X25_Y36_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~4_combout\); + +-- Location: LABCELL_X26_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~5_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111010001000100010000001100001111110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~6_combout\); + +-- Location: LABCELL_X36_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12988\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~1_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~1_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011000000100001001111001110110111111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\); + +-- Location: FF_X35_Y36_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_OTERM2337\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]~DUPLICATE_q\); + +-- Location: LABCELL_X35_Y36_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12990\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]~DUPLICATE_q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011111010111101010000010100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\); + +-- Location: LABCELL_X35_Y36_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_OTERM2337\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001011111101001111111100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_OTERM2337\); + +-- Location: FF_X35_Y36_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_OTERM2337\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16)); + +-- Location: LABCELL_X48_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[16]~feeder_combout\); + +-- Location: FF_X48_Y30_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(16)); + +-- Location: LABCELL_X48_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[16]~feeder_combout\); + +-- Location: FF_X48_Y30_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(16)); + +-- Location: LABCELL_X48_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[16]~feeder_combout\); + +-- Location: FF_X48_Y30_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(16)); + +-- Location: FF_X49_Y30_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(16)); + +-- Location: MLABCELL_X49_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(16))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(16))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~1_combout\); + +-- Location: FF_X52_Y28_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(16)); + +-- Location: FF_X53_Y28_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(16)); + +-- Location: FF_X52_Y28_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(16)); + +-- Location: FF_X52_Y28_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(16)); + +-- Location: LABCELL_X52_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(16) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(16))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(16)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(16)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(16)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010011101110000101000100010010111110111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~0_combout\); + +-- Location: LABCELL_X50_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux269~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux269~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~2_combout\); + +-- Location: FF_X50_Y23_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(16)); + +-- Location: LABCELL_X50_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(16) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(16)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(16))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(16) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(16)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(16))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000000000101010100011011000110111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~0_combout\); + +-- Location: MLABCELL_X49_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000101011001110100100110101011100011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]~74_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]~75_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector92~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]~76_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~1_combout\); + +-- Location: FF_X49_Y11_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_NEW_REG851\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM852\); + +-- Location: LABCELL_X50_Y11_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM852\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM850\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM852\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM850\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]_OTERM850\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]_OTERM852\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\); + +-- Location: MLABCELL_X37_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~0_combout\); + +-- Location: LABCELL_X36_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~1_combout\); + +-- Location: MLABCELL_X37_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~3_combout\); + +-- Location: MLABCELL_X37_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111111111111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~2_combout\); + +-- Location: MLABCELL_X37_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~2_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~3_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~4_combout\); + +-- Location: LABCELL_X32_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~6_combout\); + +-- Location: LABCELL_X31_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~17_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~8_combout\); + +-- Location: LABCELL_X32_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~5_combout\); + +-- Location: LABCELL_X31_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110101111100000011010100001111001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~18_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~7_combout\); + +-- Location: LABCELL_X32_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12978\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~6_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~8_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~8_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001110000010011000111110001000011011100110100111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\); + +-- Location: MLABCELL_X37_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12980\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~4_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~4_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101101011111010111100110011000001010011001110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\); + +-- Location: MLABCELL_X37_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_OTERM2331\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101110101001010101000101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_OTERM2331\); + +-- Location: FF_X37_Y34_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_OTERM2331\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17)); + +-- Location: LABCELL_X47_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[17]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[17]~feeder_combout\); + +-- Location: FF_X47_Y28_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(17)); + +-- Location: LABCELL_X48_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[17]~feeder_combout\); + +-- Location: FF_X48_Y28_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(17)); + +-- Location: LABCELL_X47_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[17]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[17]~feeder_combout\); + +-- Location: FF_X47_Y28_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(17)); + +-- Location: FF_X50_Y28_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(17)); + +-- Location: LABCELL_X50_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(17)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(17) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(17)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(17)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~0_combout\); + +-- Location: MLABCELL_X49_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[17]~feeder_combout\); + +-- Location: FF_X49_Y28_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(17)); + +-- Location: MLABCELL_X49_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[17]~feeder_combout\); + +-- Location: FF_X49_Y28_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(17)); + +-- Location: MLABCELL_X49_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[17]~feeder_combout\); + +-- Location: FF_X49_Y28_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(17)); + +-- Location: FF_X50_Y28_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(17)); + +-- Location: LABCELL_X50_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(17)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(17) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(17)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(17)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~1_combout\); + +-- Location: LABCELL_X50_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010110101010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux268~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux268~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~2_combout\); + +-- Location: FF_X50_Y28_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(17)); + +-- Location: MLABCELL_X37_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux417~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux417~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~3_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~1_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~2_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux417~0_combout\); + +-- Location: FF_X37_Y34_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_NEW_REG887\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux417~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM888\); + +-- Location: FF_X35_Y22_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_NEW_REG885\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM886\); + +-- Location: LABCELL_X35_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM886\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM888\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM886\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM888\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM886\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM888\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM886\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM888\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001101100011011000100010001000100011011000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[17]_OTERM888\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[17]_OTERM886\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM437\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\); + +-- Location: LABCELL_X41_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1493~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[17]~feeder_combout\); + +-- Location: FF_X41_Y25_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(17)); + +-- Location: LABCELL_X41_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1493~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[17]~feeder_combout\); + +-- Location: FF_X41_Y25_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(17)); + +-- Location: FF_X41_Y25_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(17)); + +-- Location: LABCELL_X41_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1493~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[17]~feeder_combout\); + +-- Location: FF_X41_Y21_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(17)); + +-- Location: LABCELL_X41_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(17) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(17))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100000011000111011100111111010001000011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~1_combout\); + +-- Location: LABCELL_X41_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1493~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[17]~feeder_combout\); + +-- Location: FF_X41_Y21_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(17)); + +-- Location: LABCELL_X41_Y18_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1493~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[17]~feeder_combout\); + +-- Location: FF_X41_Y18_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(17)); + +-- Location: FF_X41_Y21_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(17)); + +-- Location: FF_X42_Y21_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(17)); + +-- Location: LABCELL_X41_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(17)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(17) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(17) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(17)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(17) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(17) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000101001111110000010100110000111101010011111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~0_combout\); + +-- Location: LABCELL_X52_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux140~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux140~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~2_combout\); + +-- Location: FF_X52_Y24_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(17)); + +-- Location: MLABCELL_X37_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~3_combout\); + +-- Location: MLABCELL_X37_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~2_combout\); + +-- Location: LABCELL_X36_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~1_combout\); + +-- Location: MLABCELL_X37_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~0_combout\); + +-- Location: MLABCELL_X37_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13294\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~2_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~2_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111101010100010011101010101001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\); + +-- Location: FF_X44_Y27_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_OTERM2513\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(17)); + +-- Location: LABCELL_X44_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13296\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(17) & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(17) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010001101000101111001100001100010111011010111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\); + +-- Location: LABCELL_X44_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_OTERM2513\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000101111101111111010100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_OTERM2513\); + +-- Location: FF_X44_Y27_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_OTERM2513\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE_q\); + +-- Location: LABCELL_X47_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[17]~feeder_combout\); + +-- Location: FF_X47_Y28_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(17)); + +-- Location: FF_X47_Y28_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(17)); + +-- Location: LABCELL_X48_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[17]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[17]~feeder_combout\); + +-- Location: FF_X48_Y28_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(17)); + +-- Location: FF_X47_Y28_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(17)); + +-- Location: LABCELL_X47_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(17)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(17)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(17)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(17) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~0_combout\); + +-- Location: MLABCELL_X49_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[17]~feeder_combout\); + +-- Location: FF_X49_Y28_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(17)); + +-- Location: MLABCELL_X49_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[17]~feeder_combout\); + +-- Location: FF_X49_Y28_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(17)); + +-- Location: FF_X50_Y28_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(17)); + +-- Location: MLABCELL_X49_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[17]~feeder_combout\); + +-- Location: FF_X49_Y28_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(17)); + +-- Location: LABCELL_X50_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(17) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(17) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(17) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(17))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(17)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001110011001101000111110011000100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~1_combout\); + +-- Location: LABCELL_X50_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux204~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux204~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~2_combout\); + +-- Location: FF_X50_Y28_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(17)); + +-- Location: LABCELL_X29_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101000000000000000000001010101111111010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1429~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~1_combout\); + +-- Location: LABCELL_X29_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~1_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000011111101000000001101111100000000111111010000000011011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1429~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~22_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~2_combout\); + +-- Location: FF_X29_Y29_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_NEW_REG692\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM693\); + +-- Location: LABCELL_X32_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux361~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux361~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011010100000101111111110011111100110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux361~0_combout\); + +-- Location: FF_X32_Y29_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_NEW_REG694\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux361~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM695\); + +-- Location: LABCELL_X32_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux361~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux361~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111010001000100010000000011110011110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux361~1_combout\); + +-- Location: FF_X32_Y29_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_NEW_REG696\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux361~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM697\); + +-- Location: LABCELL_X32_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM637\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM697\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM695\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM693\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM637\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM697\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM693\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM637\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM697\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM695\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM693\) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM637\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM697\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM693\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101110101011101011111010111110101011101010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM693\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM695\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM637\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM697\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\); + +-- Location: LABCELL_X48_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1429~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[17]~feeder_combout\); + +-- Location: FF_X48_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(17)); + +-- Location: LABCELL_X48_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1429~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[17]~feeder_combout\); + +-- Location: FF_X48_Y18_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(17)); + +-- Location: FF_X48_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(17)); + +-- Location: LABCELL_X48_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1429~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[17]~feeder_combout\); + +-- Location: FF_X48_Y20_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(17)); + +-- Location: LABCELL_X48_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(17)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(17) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(17)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(17) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(17) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(17) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000010001000011001101110100111111000100010011111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~0_combout\); + +-- Location: FF_X52_Y22_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(17)); + +-- Location: FF_X52_Y22_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(17)); + +-- Location: FF_X52_Y22_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(17)); + +-- Location: FF_X36_Y27_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(17)); + +-- Location: LABCELL_X52_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(17) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(17) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(17) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(17)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(17))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101010000111100110101111100000011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~1_combout\); + +-- Location: LABCELL_X52_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux76~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux76~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~2_combout\); + +-- Location: FF_X52_Y24_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(17)); + +-- Location: LABCELL_X52_Y24_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(17) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(17) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(17) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(17) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(17), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~0_combout\); + +-- Location: LABCELL_X50_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101101010101111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]~68_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector91~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]~81_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]~72_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~1_combout\); + +-- Location: FF_X50_Y11_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_NEW_REG843\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM844\); + +-- Location: LABCELL_X50_Y11_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM844\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM842\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM844\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM842\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]_OTERM842\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]_OTERM844\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\); + +-- Location: FF_X50_Y11_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_NEW_REG853\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM854\); + +-- Location: FF_X49_Y11_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_NEW_REG837\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM838\); + +-- Location: FF_X49_Y11_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_NEW_REG845\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM846\); + +-- Location: LABCELL_X36_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~1_combout\); + +-- Location: LABCELL_X36_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~0_combout\); + +-- Location: LABCELL_X36_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13298\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010000100110001001111001110110011101101111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1548~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1548~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\); + +-- Location: FF_X37_Y35_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_OTERM2516\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(18)); + +-- Location: MLABCELL_X37_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13300\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(18) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(18) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000000101010100000000111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\); + +-- Location: MLABCELL_X37_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_OTERM2516\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000001101110111111101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_OTERM2516\); + +-- Location: FF_X37_Y35_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_OTERM2516\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE_q\); + +-- Location: FF_X52_Y28_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(18)); + +-- Location: FF_X52_Y28_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(18)); + +-- Location: FF_X52_Y28_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(18)); + +-- Location: LABCELL_X52_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[18]~feeder_combout\); + +-- Location: FF_X52_Y29_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(18)); + +-- Location: LABCELL_X52_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(18) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(18))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(18)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(18))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(18) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(18) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(18)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(18) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(18) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000010001001111110001000100001100110111010011111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~0_combout\); + +-- Location: FF_X50_Y25_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(18)); + +-- Location: FF_X50_Y25_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(18)); + +-- Location: FF_X50_Y25_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(18)); + +-- Location: LABCELL_X52_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[18]~feeder_combout\); + +-- Location: FF_X52_Y29_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(18)); + +-- Location: LABCELL_X50_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(18) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(18))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(18))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(18)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(18))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(18))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(18) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(18))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(18)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000100110000101010011011110001100101011101001110110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~1_combout\); + +-- Location: LABCELL_X52_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux203~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux203~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~2_combout\); + +-- Location: FF_X52_Y24_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(18)); + +-- Location: LABCELL_X31_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788_BDD12789\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111110011111111111111001110101010111100111010101011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788_BDD12789\); + +-- Location: LABCELL_X31_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12790\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12790_BDD12791\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101000000000111110100000000011111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12790_BDD12791\); + +-- Location: LABCELL_X31_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12790_BDD12791\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788_BDD12789\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12790_BDD12791\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788_BDD12789\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788_BDD12789\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12790_BDD12791\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788_BDD12789\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12790_BDD12791\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788_BDD12789\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001110001000111110110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_RESYN12788_BDD12789\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_RESYN12790_BDD12791\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\); + +-- Location: LABCELL_X36_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~1_combout\); + +-- Location: LABCELL_X36_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~0_combout\); + +-- Location: LABCELL_X36_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100010001110100011100110011111111110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~2_combout\); + +-- Location: LABCELL_X32_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794_BDD12795\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111001011110010000000100000001011110010111100101111001011110010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794_BDD12795\); + +-- Location: LABCELL_X32_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12792\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12792_BDD12793\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111111111000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12792_BDD12793\); + +-- Location: LABCELL_X32_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12796\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12796_BDD12797\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12796_BDD12797\); + +-- Location: LABCELL_X32_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12796_BDD12797\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794_BDD12795\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12796_BDD12797\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794_BDD12795\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12796_BDD12797\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794_BDD12795\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12792_BDD12793\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794_BDD12795\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12796_BDD12797\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794_BDD12795\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011100010111000111100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12794_BDD12795\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12792_BDD12793\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12796_BDD12797\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\); + +-- Location: LABCELL_X32_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~2_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001000110111011000100011011101100001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~3_combout\); + +-- Location: LABCELL_X32_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000111100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\); + +-- Location: LABCELL_X32_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[18]_NEW3243\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[18]_OTERM3244\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(18)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~3_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[18]_OTERM3244\); + +-- Location: FF_X32_Y27_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[18]_OTERM3244\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(18)); + +-- Location: LABCELL_X52_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[18]~feeder_combout\); + +-- Location: FF_X52_Y15_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(18)); + +-- Location: FF_X50_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(18)); + +-- Location: LABCELL_X52_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[18]~feeder_combout\); + +-- Location: FF_X52_Y16_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(18)); + +-- Location: FF_X50_Y18_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(18)); + +-- Location: LABCELL_X50_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(18)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(18)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(18)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~0_combout\); + +-- Location: FF_X50_Y19_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(18)); + +-- Location: FF_X50_Y19_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(18)); + +-- Location: MLABCELL_X49_Y17_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[18]~feeder_combout\); + +-- Location: FF_X49_Y17_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(18)); + +-- Location: FF_X50_Y19_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(18)); + +-- Location: LABCELL_X50_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(18)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(18)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(18))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(18))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~1_combout\); + +-- Location: LABCELL_X52_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux75~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux75~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~2_combout\); + +-- Location: FF_X52_Y19_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(18)); + +-- Location: FF_X37_Y35_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_OTERM2335\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(18)); + +-- Location: LABCELL_X36_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000011011101110000001101000100110011110111011111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~1_combout\); + +-- Location: LABCELL_X36_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~0_combout\); + +-- Location: MLABCELL_X28_Y36_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~3_combout\); + +-- Location: MLABCELL_X28_Y36_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~5_combout\); + +-- Location: MLABCELL_X28_Y36_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~4_combout\); + +-- Location: MLABCELL_X28_Y36_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~2_combout\); + +-- Location: LABCELL_X29_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~5_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011000000000000111101010011010100111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~6_combout\); + +-- Location: LABCELL_X36_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12984\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12984_BDD12985\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~1_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~6_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001010001010100010110101011101010111110111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12984_BDD12985\); + +-- Location: MLABCELL_X37_Y35_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12986\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(18) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12984_BDD12985\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(18) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12984_BDD12985\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000101000011110000010100001111101011110000111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]_NEW2334_RESYN12984_BDD12985\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\); + +-- Location: MLABCELL_X37_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_OTERM2335\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101110101001010101000101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_OTERM2335\); + +-- Location: FF_X37_Y35_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_OTERM2335\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE_q\); + +-- Location: MLABCELL_X49_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[18]~feeder_combout\); + +-- Location: FF_X49_Y19_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(18)); + +-- Location: FF_X49_Y19_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(18)); + +-- Location: FF_X52_Y18_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(18)); + +-- Location: FF_X49_Y19_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(18)); + +-- Location: MLABCELL_X49_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(18))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(18))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~1_combout\); + +-- Location: FF_X52_Y18_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(18)); + +-- Location: LABCELL_X53_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[18]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[18]~feeder_combout\); + +-- Location: FF_X53_Y18_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(18)); + +-- Location: FF_X53_Y18_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(18)); + +-- Location: FF_X53_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(18)); + +-- Location: LABCELL_X53_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(18)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(18)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~0_combout\); + +-- Location: LABCELL_X52_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux267~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux267~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~2_combout\); + +-- Location: FF_X52_Y19_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(18)); + +-- Location: LABCELL_X36_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~0_combout\); + +-- Location: LABCELL_X36_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~1_combout\); + +-- Location: LABCELL_X36_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~1_combout\)))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~1_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000101001001110000010100100111000011011010111110001101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~1_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~2_combout\); + +-- Location: FF_X45_Y27_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_OTERM2333\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]~DUPLICATE_q\); + +-- Location: MLABCELL_X45_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332_RESYN12982\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]~DUPLICATE_q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001111111100110011000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\); + +-- Location: MLABCELL_X45_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_OTERM2333\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110001110011101111111100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_OTERM2333\); + +-- Location: FF_X45_Y27_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_OTERM2333\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18)); + +-- Location: LABCELL_X52_Y18_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[18]~feeder_combout\); + +-- Location: FF_X52_Y18_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(18)); + +-- Location: LABCELL_X52_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[18]~feeder_combout\); + +-- Location: FF_X52_Y18_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(18)); + +-- Location: FF_X53_Y18_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(18)); + +-- Location: FF_X53_Y18_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(18)); + +-- Location: LABCELL_X53_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(18) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(18))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(18)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(18) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(18)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(18))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000010110000000110101011101000010101101101010001111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~0_combout\); + +-- Location: FF_X50_Y19_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(18)); + +-- Location: MLABCELL_X49_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[18]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[18]~feeder_combout\); + +-- Location: FF_X49_Y19_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(18)); + +-- Location: FF_X52_Y19_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(18)); + +-- Location: FF_X52_Y19_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(18)); + +-- Location: LABCELL_X52_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(18)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(18)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~1_combout\); + +-- Location: LABCELL_X52_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010110101010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux139~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux139~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~2_combout\); + +-- Location: FF_X52_Y19_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(18)); + +-- Location: LABCELL_X52_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(18) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(18)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(18)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~0_combout\); + +-- Location: MLABCELL_X49_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010000111100110101000000000011010111111111001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]~77_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]~71_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]~70_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector90~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~1_combout\); + +-- Location: FF_X49_Y11_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_NEW_REG847\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM848\); + +-- Location: MLABCELL_X49_Y11_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM848\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM846\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM848\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM846\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]_OTERM846\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]_OTERM848\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\); + +-- Location: LABCELL_X26_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111110011111100111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1_combout\); + +-- Location: LABCELL_X25_Y38_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0_combout\); + +-- Location: LABCELL_X26_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE_q\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\); + +-- Location: LABCELL_X26_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000010100000101000000111111001111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~0_combout\); + +-- Location: LABCELL_X32_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~0_combout\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~0_combout\)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101010100001111010101010000111100110011000000000011001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1427~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~1_combout\); + +-- Location: LABCELL_X32_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[19]_NEW3239\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[19]_OTERM3240\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(19))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(19))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111110001000000011111000100001101111111010000110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1427~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[19]_OTERM3240\); + +-- Location: FF_X32_Y28_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[19]_OTERM3240\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(19)); + +-- Location: FF_X40_Y12_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(19)); + +-- Location: FF_X41_Y12_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(19)); + +-- Location: FF_X45_Y12_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(19)); + +-- Location: FF_X41_Y12_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(19)); + +-- Location: MLABCELL_X45_Y12_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(19) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(19))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(19)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(19)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(19)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000101010001001010010111101110000011110100111010101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~1_combout\); + +-- Location: FF_X43_Y12_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(19)); + +-- Location: FF_X40_Y12_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(19)); + +-- Location: FF_X40_Y12_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(19)); + +-- Location: FF_X45_Y12_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(19)); + +-- Location: MLABCELL_X45_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(19))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(19))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(19)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(19) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~0_combout\); + +-- Location: MLABCELL_X45_Y12_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux74~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux74~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~2_combout\); + +-- Location: FF_X45_Y12_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(19)); + +-- Location: LABCELL_X36_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1_combout\); + +-- Location: LABCELL_X32_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000000000000000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3_combout\); + +-- Location: LABCELL_X32_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2_combout\); + +-- Location: LABCELL_X25_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\); + +-- Location: LABCELL_X36_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111000000000011001101000111010001111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~4_combout\); + +-- Location: MLABCELL_X28_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~6_combout\); + +-- Location: LABCELL_X29_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~5_combout\); + +-- Location: MLABCELL_X28_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110100110001001111010000000111001101111100011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~17_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~8_combout\); + +-- Location: LABCELL_X29_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111100111111001100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~16_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~7_combout\); + +-- Location: LABCELL_X29_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12962\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~6_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~5_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~5_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100111111000001010011000011110101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\); + +-- Location: LABCELL_X43_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12964\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~4_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000011000001110111111111010101010011111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\); + +-- Location: LABCELL_X43_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_OTERM2323\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_OTERM2323\); + +-- Location: FF_X43_Y30_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_OTERM2323\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19)); + +-- Location: LABCELL_X41_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[19]~feeder_combout\); + +-- Location: FF_X41_Y11_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(19)); + +-- Location: LABCELL_X41_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[19]~feeder_combout\); + +-- Location: FF_X41_Y11_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(19)); + +-- Location: FF_X43_Y11_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(19)); + +-- Location: FF_X41_Y11_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(19)); + +-- Location: LABCELL_X41_Y11_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(19)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(19) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(19)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(19)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~1_combout\); + +-- Location: LABCELL_X48_Y14_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[19]~feeder_combout\); + +-- Location: FF_X48_Y14_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(19)); + +-- Location: LABCELL_X47_Y13_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[19]~feeder_combout\); + +-- Location: FF_X47_Y13_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(19)); + +-- Location: FF_X45_Y12_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(19)); + +-- Location: LABCELL_X47_Y13_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[19]~feeder_combout\); + +-- Location: FF_X47_Y13_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(19)); + +-- Location: MLABCELL_X45_Y12_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(19) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(19))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(19)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(19))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(19) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(19) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(19)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(19) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(19) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(19) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000010001010111110001000100001010101110110101111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~0_combout\); + +-- Location: MLABCELL_X45_Y12_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux266~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux266~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~2_combout\); + +-- Location: FF_X45_Y12_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(19)); + +-- Location: FF_X39_Y27_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_OTERM2519\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(19)); + +-- Location: LABCELL_X32_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~2_combout\); + +-- Location: LABCELL_X26_Y38_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13302\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13302_BDD13303\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100001101001111010000000111110001110011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13302_BDD13303\); + +-- Location: LABCELL_X39_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13304\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(19) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13302_BDD13303\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(19) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(19) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13302_BDD13303\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(19) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001100100011000000001010111101110011011100110101000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]_NEW2518_RESYN13302_BDD13303\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\); + +-- Location: LABCELL_X39_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_OTERM2519\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_OTERM2519\); + +-- Location: FF_X39_Y27_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_OTERM2519\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE_q\); + +-- Location: FF_X43_Y21_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(19)); + +-- Location: FF_X41_Y20_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(19)); + +-- Location: FF_X43_Y21_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(19)); + +-- Location: FF_X43_Y21_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(19)); + +-- Location: LABCELL_X43_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(19) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(19))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(19))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(19))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(19)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(19))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(19)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(19) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(19)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101001001100011011110001100100111011010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~0_combout\); + +-- Location: FF_X39_Y20_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(19)); + +-- Location: MLABCELL_X42_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[19]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[19]~feeder_combout\); + +-- Location: FF_X42_Y20_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(19)); + +-- Location: LABCELL_X41_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[19]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[19]~feeder_combout\); + +-- Location: FF_X41_Y20_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(19)); + +-- Location: FF_X39_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(19)); + +-- Location: LABCELL_X39_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(19)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(19) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(19))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(19))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~1_combout\); + +-- Location: LABCELL_X40_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux202~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux202~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~2_combout\); + +-- Location: FF_X40_Y20_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(19)); + +-- Location: LABCELL_X36_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1491~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1491~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101001100010011110111000001110011011111000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1491~0_combout\); + +-- Location: MLABCELL_X37_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12958\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12958_BDD12959\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1491~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1491~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1491~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1491~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001000000011100000111000001001111010011110111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1491~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12958_BDD12959\); + +-- Location: MLABCELL_X37_Y23_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12960\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12958_BDD12959\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12958_BDD12959\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100101111001011110010111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[19]_NEW2320_RESYN12958_BDD12959\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\); + +-- Location: MLABCELL_X37_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_OTERM2321\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_OTERM2321\); + +-- Location: FF_X37_Y23_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_OTERM2321\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19)); + +-- Location: FF_X42_Y20_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(19)); + +-- Location: LABCELL_X43_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[19]~feeder_combout\); + +-- Location: FF_X43_Y18_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(19)); + +-- Location: FF_X43_Y18_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(19)); + +-- Location: FF_X42_Y20_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(19)); + +-- Location: LABCELL_X43_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(19) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(19))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(19))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(19))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100000001111100011100110100111101000011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~1_combout\); + +-- Location: FF_X40_Y17_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(19)); + +-- Location: FF_X40_Y17_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(19)); + +-- Location: FF_X40_Y17_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(19)); + +-- Location: MLABCELL_X42_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[19]~feeder_combout\); + +-- Location: FF_X42_Y17_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(19)); + +-- Location: LABCELL_X40_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(19) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(19)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(19)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(19))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(19) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(19) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(19))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(19)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(19) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(19))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101001100010011110111000001110011011111000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~0_combout\); + +-- Location: MLABCELL_X45_Y12_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux138~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux138~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~2_combout\); + +-- Location: FF_X45_Y12_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(19)); + +-- Location: MLABCELL_X45_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(19) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(19) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(19) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(19) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~0_combout\); + +-- Location: MLABCELL_X49_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010000111100110101000000000011010111111111001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]~84_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]~69_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]~74_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector89~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~1_combout\); + +-- Location: FF_X49_Y11_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_NEW_REG839\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM840\); + +-- Location: MLABCELL_X49_Y11_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM840\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM838\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM840\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM838\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]_OTERM838\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]_OTERM840\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\); + +-- Location: LABCELL_X21_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~17_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~5_combout\); + +-- Location: LABCELL_X21_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~18_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~4_combout\); + +-- Location: LABCELL_X20_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111000001010000010100110000001111111111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~3_combout\); + +-- Location: LABCELL_X21_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~2_combout\); + +-- Location: LABCELL_X32_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~4_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~5_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~4_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~4_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111101010100010011101010101001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~6_combout\); + +-- Location: LABCELL_X36_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110111010101000011011010101010001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~0_combout\); + +-- Location: LABCELL_X36_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~1_combout\); + +-- Location: MLABCELL_X34_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12994\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12994_BDD12995\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~1_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000010101111101000000101111101010000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12994_BDD12995\); + +-- Location: FF_X37_Y35_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_OTERM2341\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(20)); + +-- Location: MLABCELL_X37_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12996\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(20) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12994_BDD12995\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(20) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12994_BDD12995\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110101000000001111010100001010111111110000101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]_NEW2340_RESYN12994_BDD12995\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\); + +-- Location: MLABCELL_X37_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_OTERM2341\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000101111101111111010100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_OTERM2341\); + +-- Location: FF_X37_Y35_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_OTERM2341\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE_q\); + +-- Location: LABCELL_X53_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[20]~feeder_combout\); + +-- Location: FF_X53_Y28_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(20)); + +-- Location: FF_X52_Y28_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(20)); + +-- Location: FF_X52_Y28_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(20)); + +-- Location: FF_X52_Y28_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(20)); + +-- Location: LABCELL_X52_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(20) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(20))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(20))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(20))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100001111110100010000001100011101110011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~0_combout\); + +-- Location: FF_X53_Y27_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(20)); + +-- Location: FF_X53_Y27_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(20)); + +-- Location: LABCELL_X53_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[20]~feeder_combout\); + +-- Location: FF_X53_Y28_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(20)); + +-- Location: FF_X53_Y27_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(20)); + +-- Location: LABCELL_X53_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(20) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(20)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(20)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~1_combout\); + +-- Location: LABCELL_X52_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux265~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux265~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~2_combout\); + +-- Location: FF_X52_Y23_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(20)); + +-- Location: LABCELL_X36_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~0_combout\); + +-- Location: LABCELL_X36_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~1_combout\); + +-- Location: LABCELL_X35_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~1_combout\)))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~1_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000111100100010000011110010001000001111011101110000111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~1_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~2_combout\); + +-- Location: FF_X44_Y29_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_OTERM2339\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(20)); + +-- Location: LABCELL_X44_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338_RESYN12992\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(20) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111011101110100100010001000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\); + +-- Location: LABCELL_X44_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_OTERM2339\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000001101110111111101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_OTERM2339\); + +-- Location: FF_X44_Y29_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_OTERM2339\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE_q\); + +-- Location: LABCELL_X50_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[20]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[20]~feeder_combout\); + +-- Location: FF_X50_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(20)); + +-- Location: FF_X48_Y18_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(20)); + +-- Location: MLABCELL_X49_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[20]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[20]~feeder_combout\); + +-- Location: FF_X49_Y18_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(20)); + +-- Location: FF_X50_Y18_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(20)); + +-- Location: LABCELL_X50_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(20) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(20))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(20))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~0_combout\); + +-- Location: FF_X50_Y19_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(20)); + +-- Location: LABCELL_X50_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[20]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[20]~feeder_combout\); + +-- Location: FF_X50_Y18_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(20)); + +-- Location: FF_X50_Y19_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(20)); + +-- Location: FF_X50_Y19_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(20)); + +-- Location: LABCELL_X50_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(20)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(20)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(20)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(20)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~1_combout\); + +-- Location: LABCELL_X52_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux137~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux137~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~2_combout\); + +-- Location: FF_X52_Y19_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(20)); + +-- Location: LABCELL_X36_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~0_combout\); + +-- Location: LABCELL_X36_Y36_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~1_combout\); + +-- Location: LABCELL_X35_Y36_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13318\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~0_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101000000010100010110101011111011111010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1546~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1546~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\); + +-- Location: LABCELL_X35_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13320\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111101011111010100001010000010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\); + +-- Location: LABCELL_X35_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_OTERM2531\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_OTERM2531\); + +-- Location: FF_X35_Y34_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_OTERM2531\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20)); + +-- Location: MLABCELL_X49_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[20]~feeder_combout\); + +-- Location: FF_X49_Y18_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(20)); + +-- Location: LABCELL_X52_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[20]~feeder_combout\); + +-- Location: FF_X52_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(20)); + +-- Location: FF_X47_Y20_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(20)); + +-- Location: FF_X52_Y20_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(20)); + +-- Location: LABCELL_X52_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(20)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(20)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(20)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~0_combout\); + +-- Location: MLABCELL_X49_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[20]~feeder_combout\); + +-- Location: FF_X49_Y18_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(20)); + +-- Location: FF_X47_Y20_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(20)); + +-- Location: MLABCELL_X49_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[20]~feeder_combout\); + +-- Location: FF_X49_Y22_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(20)); + +-- Location: FF_X49_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(20)); + +-- Location: MLABCELL_X49_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(20)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(20)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(20))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(20))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~1_combout\); + +-- Location: LABCELL_X52_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux201~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux201~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~2_combout\); + +-- Location: FF_X52_Y23_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(20)); + +-- Location: MLABCELL_X34_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000110000001100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~1_combout\); + +-- Location: FF_X34_Y26_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG660\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\); + +-- Location: MLABCELL_X34_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0_combout\); + +-- Location: MLABCELL_X34_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100000011001100110000001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~3_combout\); + +-- Location: FF_X34_Y28_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG662\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM663\); + +-- Location: LABCELL_X36_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111010001000100010000000011110011110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~0_combout\); + +-- Location: LABCELL_X36_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000010101010000111100110011111111110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~1_combout\); + +-- Location: MLABCELL_X34_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~0_combout\)))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~0_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000101000011011000010100001101101001110010111110100111001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~1_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~4_combout\); + +-- Location: FF_X34_Y28_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG656\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM657\); + +-- Location: FF_X34_Y28_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG654\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM655\); + +-- Location: FF_X34_Y28_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG658\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\); + +-- Location: MLABCELL_X34_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM655\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM663\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM657\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM655\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM663\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM657\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM655\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM663\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM657\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM655\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM663\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM657\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110011111111001011101111111100001100111111110000110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM377\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM661\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM663\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM657\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM655\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM659\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\); + +-- Location: LABCELL_X44_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[20]~feeder_combout\); + +-- Location: FF_X44_Y24_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(20)); + +-- Location: FF_X43_Y24_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(20)); + +-- Location: FF_X43_Y24_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(20)); + +-- Location: FF_X35_Y27_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(20)); + +-- Location: LABCELL_X43_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(20) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(20))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(20)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(20))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(20))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(20) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(20))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(20)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110001001010001011100110100100011101010110110011111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~1_combout\); + +-- Location: LABCELL_X43_Y26_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[20]~feeder_combout\); + +-- Location: FF_X43_Y26_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(20)); + +-- Location: LABCELL_X44_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[20]~feeder_combout\); + +-- Location: FF_X44_Y26_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(20)); + +-- Location: LABCELL_X43_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[20]~feeder_combout\); + +-- Location: FF_X43_Y26_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(20)); + +-- Location: FF_X43_Y26_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(20)); + +-- Location: LABCELL_X43_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(20) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(20)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(20)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~0_combout\); + +-- Location: LABCELL_X52_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux73~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux73~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~2_combout\); + +-- Location: FF_X52_Y24_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(20)); + +-- Location: LABCELL_X52_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(20) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(20) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(20) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(20) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~0_combout\); + +-- Location: LABCELL_X50_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110100000001110011011111000100111101001100011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]~75_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]~73_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector88~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]~68_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~1_combout\); + +-- Location: FF_X50_Y11_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_NEW_REG855\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM856\); + +-- Location: LABCELL_X50_Y11_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM856\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM854\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM856\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM854\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]_OTERM854\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]_OTERM856\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\); + +-- Location: LABCELL_X43_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3_combout\); + +-- Location: LABCELL_X43_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1_combout\); + +-- Location: FF_X34_Y31_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~423_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~2_combout\); + +-- Location: LABCELL_X43_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0_combout\); + +-- Location: LABCELL_X43_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100111101001100011100110111000001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\); + +-- Location: FF_X47_Y27_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_OTERM2525\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(21)); + +-- Location: LABCELL_X47_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13312\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(21) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) +-- # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000101110001001111010100110111000001011111011111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\); + +-- Location: LABCELL_X47_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_OTERM2525\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011111111110111001100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_OTERM2525\); + +-- Location: FF_X47_Y27_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_OTERM2525\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE_q\); + +-- Location: LABCELL_X47_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[21]~feeder_combout\); + +-- Location: FF_X47_Y28_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(21)); + +-- Location: LABCELL_X47_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[21]~feeder_combout\); + +-- Location: FF_X47_Y28_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(21)); + +-- Location: FF_X48_Y28_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(21)); + +-- Location: FF_X48_Y28_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(21)); + +-- Location: LABCELL_X48_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(21) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(21) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(21)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(21) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(21))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(21) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(21))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110111010101000011011010101010001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~0_combout\); + +-- Location: FF_X49_Y28_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(21)); + +-- Location: FF_X49_Y28_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(21)); + +-- Location: FF_X49_Y28_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(21)); + +-- Location: FF_X50_Y28_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(21)); + +-- Location: LABCELL_X50_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(21)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(21) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(21))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(21))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~1_combout\); + +-- Location: LABCELL_X52_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux200~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux200~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~2_combout\); + +-- Location: FF_X52_Y25_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(21)); + +-- Location: LABCELL_X43_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\); + +-- Location: LABCELL_X43_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\); + +-- Location: LABCELL_X43_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\); + +-- Location: LABCELL_X43_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\); + +-- Location: LABCELL_X43_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1489~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1489~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011010000101010001111110110000101110101011010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1489~0_combout\); + +-- Location: MLABCELL_X37_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13010\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13010_BDD13011\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1489~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1489~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1489~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1489~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000001000010011000100110000111011001110110111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1489~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13010_BDD13011\); + +-- Location: MLABCELL_X37_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13012\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13010_BDD13011\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13010_BDD13011\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[21]_NEW2350_RESYN13010_BDD13011\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\); + +-- Location: MLABCELL_X37_Y31_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_OTERM2351\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000101111101111111010100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_OTERM2351\); + +-- Location: FF_X37_Y31_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_OTERM2351\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21)); + +-- Location: FF_X48_Y25_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(21)); + +-- Location: LABCELL_X47_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[21]~feeder_combout\); + +-- Location: FF_X47_Y25_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(21)); + +-- Location: FF_X52_Y26_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(21)); + +-- Location: FF_X48_Y25_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(21)); + +-- Location: LABCELL_X48_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(21))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(21))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(21)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~0_combout\); + +-- Location: LABCELL_X47_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[21]~feeder_combout\); + +-- Location: FF_X47_Y25_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(21)); + +-- Location: MLABCELL_X49_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[21]~feeder_combout\); + +-- Location: FF_X49_Y25_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(21)); + +-- Location: MLABCELL_X49_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[21]~feeder_combout\); + +-- Location: FF_X49_Y25_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(21)); + +-- Location: FF_X49_Y25_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(21)); + +-- Location: MLABCELL_X49_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(21)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(21))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(21)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(21))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(21)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~1_combout\); + +-- Location: LABCELL_X48_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000110111011101110111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux136~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux136~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~2_combout\); + +-- Location: FF_X48_Y25_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(21)); + +-- Location: LABCELL_X43_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001010111000000100101011110100010111101111010001011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~0_combout\); + +-- Location: LABCELL_X32_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~0_combout\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~0_combout\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101010100001111010101010000111100110011000000000011001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1425~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~1_combout\); + +-- Location: LABCELL_X32_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[21]_NEW3247\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[21]_OTERM3248\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(21))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~1_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101010001111110110101000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1425~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[21]_OTERM3248\); + +-- Location: FF_X32_Y28_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[21]_OTERM3248\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(21)); + +-- Location: LABCELL_X47_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(21) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[21]~feeder_combout\); + +-- Location: FF_X47_Y21_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(21)); + +-- Location: LABCELL_X47_Y21_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(21) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[21]~feeder_combout\); + +-- Location: FF_X47_Y21_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(21)); + +-- Location: FF_X44_Y21_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(21)); + +-- Location: LABCELL_X44_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(21) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[21]~feeder_combout\); + +-- Location: FF_X44_Y28_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(21)); + +-- Location: LABCELL_X44_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(21) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(21))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(21)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(21) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(21) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(21)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(21) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(21) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(21) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110000000001010011111111110101001100001111010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~1_combout\); + +-- Location: FF_X43_Y21_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(21)); + +-- Location: FF_X43_Y21_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(21)); + +-- Location: FF_X43_Y21_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(21)); + +-- Location: FF_X44_Y21_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(21)); + +-- Location: LABCELL_X43_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(21) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(21))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(21))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(21))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100001111110100010000001100011101110011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~0_combout\); + +-- Location: LABCELL_X44_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux72~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux72~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~2_combout\); + +-- Location: FF_X44_Y21_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(21)); + +-- Location: LABCELL_X43_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000100101001010100010111101110000011101010111101001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~4_combout\); + +-- Location: MLABCELL_X34_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~5_combout\); + +-- Location: MLABCELL_X34_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011100010011010101101000101011001111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~16_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~8_combout\); + +-- Location: MLABCELL_X34_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110001001010001011100110100100011101010110110011111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~6_combout\); + +-- Location: MLABCELL_X34_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111000000110000001101010000010111111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~18_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~7_combout\); + +-- Location: MLABCELL_X34_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13014\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~5_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010101110110000101000010001010111111011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\); + +-- Location: LABCELL_X44_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13016\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100011011000000000000111110110001101110111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\); + +-- Location: LABCELL_X44_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_OTERM2353\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011110111111100111100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_OTERM2353\); + +-- Location: FF_X44_Y27_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_OTERM2353\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21)); + +-- Location: MLABCELL_X49_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[21]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[21]~feeder_combout\); + +-- Location: FF_X49_Y25_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(21)); + +-- Location: FF_X50_Y25_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(21)); + +-- Location: FF_X50_Y25_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(21)); + +-- Location: FF_X47_Y25_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(21)); + +-- Location: LABCELL_X50_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(21) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(21))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(21)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(21) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(21) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(21)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(21) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(21) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(21) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010000100010101111110111011000010101011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~1_combout\); + +-- Location: FF_X47_Y25_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(21)); + +-- Location: FF_X48_Y25_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(21)); + +-- Location: FF_X47_Y25_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(21)); + +-- Location: FF_X48_Y25_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(21)); + +-- Location: LABCELL_X48_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(21))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(21)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(21))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(21)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(21)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~0_combout\); + +-- Location: LABCELL_X48_Y25_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux264~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux264~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~2_combout\); + +-- Location: FF_X48_Y25_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(21)); + +-- Location: LABCELL_X48_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(21) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(21)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(21)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(21))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(21) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(21))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000001010000010100000011111100111111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~0_combout\); + +-- Location: LABCELL_X50_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011000000001111000001010011010100110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]~71_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]~72_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]~67_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector87~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~1_combout\); + +-- Location: FF_X50_Y11_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_NEW_REG859\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM860\); + +-- Location: MLABCELL_X49_Y11_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM860\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM858\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM860\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM858\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101111000000001010111101010000111111110101000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]_OTERM858\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]_OTERM860\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\); + +-- Location: MLABCELL_X42_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~0_combout\); + +-- Location: MLABCELL_X42_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000000001011111010100111111001111110000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~1_combout\); + +-- Location: LABCELL_X43_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~1_combout\)))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~1_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001110100001100000111010000110000011101001111110001110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~1_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~2_combout\); + +-- Location: LABCELL_X44_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360_RESYN13026\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110111011101101000100010001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\); + +-- Location: LABCELL_X44_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_OTERM2361\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000101111101111111010100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_OTERM2361\); + +-- Location: FF_X44_Y27_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_OTERM2361\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22)); + +-- Location: FF_X49_Y23_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(22)); + +-- Location: FF_X49_Y23_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(22)); + +-- Location: FF_X50_Y23_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(22)); + +-- Location: FF_X49_Y23_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(22)); + +-- Location: MLABCELL_X49_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(22)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(22)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(22)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~0_combout\); + +-- Location: MLABCELL_X49_Y22_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[22]~feeder_combout\); + +-- Location: FF_X49_Y22_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(22)); + +-- Location: LABCELL_X50_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[22]~feeder_combout\); + +-- Location: FF_X50_Y22_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(22)); + +-- Location: MLABCELL_X49_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[22]~feeder_combout\); + +-- Location: FF_X49_Y22_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(22)); + +-- Location: FF_X50_Y22_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(22)); + +-- Location: LABCELL_X50_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(22)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(22)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~1_combout\); + +-- Location: LABCELL_X52_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux135~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux135~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~2_combout\); + +-- Location: FF_X52_Y23_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(22)); + +-- Location: FF_X35_Y36_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_OTERM2363\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(22)); + +-- Location: LABCELL_X29_Y36_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~2_combout\); + +-- Location: LABCELL_X29_Y36_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~16_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~18_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~4_combout\); + +-- Location: LABCELL_X29_Y36_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~3_combout\); + +-- Location: LABCELL_X29_Y36_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~17_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~5_combout\); + +-- Location: LABCELL_X29_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~4_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~4_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~4_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~4_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000111101000101010011101010010010101111111001011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~6_combout\); + +-- Location: MLABCELL_X42_Y36_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~1_combout\); + +-- Location: MLABCELL_X42_Y36_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000000000111111001101011111010111110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~0_combout\); + +-- Location: LABCELL_X36_Y36_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13028\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13028_BDD13029\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~1_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~1_combout\)))) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000011101000011000001110100101110001111110010111000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13028_BDD13029\); + +-- Location: LABCELL_X35_Y36_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13030\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(22) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13028_BDD13029\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(22) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13028_BDD13029\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[22]_NEW2362_RESYN13028_BDD13029\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\); + +-- Location: LABCELL_X35_Y36_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_OTERM2363\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_OTERM2363\); + +-- Location: FF_X35_Y36_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_OTERM2363\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE_q\); + +-- Location: FF_X43_Y19_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(22)); + +-- Location: FF_X48_Y11_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(22)); + +-- Location: FF_X48_Y25_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(22)); + +-- Location: FF_X48_Y25_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(22)); + +-- Location: LABCELL_X48_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(22)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(22)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~0_combout\); + +-- Location: FF_X48_Y11_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(22)); + +-- Location: FF_X49_Y25_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(22)); + +-- Location: FF_X49_Y25_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(22)); + +-- Location: FF_X49_Y25_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(22)); + +-- Location: MLABCELL_X49_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(22)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(22)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~1_combout\); + +-- Location: LABCELL_X48_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux263~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux263~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~2_combout\); + +-- Location: FF_X48_Y25_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(22)); + +-- Location: MLABCELL_X42_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111010100000101000000110000001111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~1_combout\); + +-- Location: MLABCELL_X42_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~0_combout\); + +-- Location: LABCELL_X41_Y36_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13314\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111000000000010011111111111001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1544~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1544~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\); + +-- Location: MLABCELL_X42_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13316\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100111111001100001100000011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\); + +-- Location: MLABCELL_X42_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_OTERM2528\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001101111111011101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_OTERM2528\); + +-- Location: FF_X42_Y27_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_OTERM2528\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22)); + +-- Location: FF_X49_Y30_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(22)); + +-- Location: FF_X49_Y30_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(22)); + +-- Location: FF_X48_Y30_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(22)); + +-- Location: FF_X49_Y30_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(22)); + +-- Location: MLABCELL_X49_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(22)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(22)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(22))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(22))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~1_combout\); + +-- Location: LABCELL_X47_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[22]~feeder_combout\); + +-- Location: FF_X47_Y28_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(22)); + +-- Location: FF_X48_Y28_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(22)); + +-- Location: FF_X48_Y28_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(22)); + +-- Location: LABCELL_X47_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[22]~feeder_combout\); + +-- Location: FF_X47_Y28_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(22)); + +-- Location: LABCELL_X48_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(22) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(22))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(22))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(22))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(22)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(22))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(22)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(22) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(22)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101000100011010111110111011000001011011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~0_combout\); + +-- Location: LABCELL_X50_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux199~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux199~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~2_combout\); + +-- Location: FF_X50_Y26_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(22)); + +-- Location: MLABCELL_X42_Y36_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~0_combout\); + +-- Location: MLABCELL_X42_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~1_combout\); + +-- Location: MLABCELL_X42_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111000000000101010100110011000011111111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~2_combout\); + +-- Location: LABCELL_X32_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~2_combout\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~2_combout\)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101010100001111010101010000111100110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~3_combout\); + +-- Location: LABCELL_X32_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[22]_NEW3251\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[22]_OTERM3252\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~3_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011111100001111001100001111000000111111111111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[22]_OTERM3252\); + +-- Location: FF_X32_Y28_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[22]_OTERM3252\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22)); + +-- Location: FF_X53_Y18_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(22)); + +-- Location: LABCELL_X53_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[22]~feeder_combout\); + +-- Location: FF_X53_Y20_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(22)); + +-- Location: FF_X53_Y18_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(22)); + +-- Location: FF_X53_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(22)); + +-- Location: LABCELL_X53_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(22))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(22))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(22)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(22)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~0_combout\); + +-- Location: FF_X50_Y19_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(22)); + +-- Location: MLABCELL_X49_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[22]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[22]~feeder_combout\); + +-- Location: FF_X49_Y19_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(22)); + +-- Location: FF_X50_Y19_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(22)); + +-- Location: FF_X50_Y19_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(22)); + +-- Location: LABCELL_X50_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(22) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(22))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(22)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(22))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(22) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(22))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(22)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(22) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(22))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(22) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011010000101010001111110110000101110101011010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~1_combout\); + +-- Location: LABCELL_X52_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux71~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux71~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~2_combout\); + +-- Location: FF_X52_Y19_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(22)); + +-- Location: LABCELL_X52_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(22)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(22)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(22)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001101110111011101100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~0_combout\); + +-- Location: MLABCELL_X49_Y11_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100001001101010111000010101100111010011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]~64_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]~69_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]~70_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector86~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~1_combout\); + +-- Location: FF_X49_Y11_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_NEW_REG863\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM864\); + +-- Location: MLABCELL_X49_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM864\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM862\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM864\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM862\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]_OTERM862\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]_OTERM864\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\); + +-- Location: LABCELL_X19_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~1_combout\); + +-- Location: LABCELL_X24_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~0_combout\); + +-- Location: LABCELL_X25_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~0_combout\)))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~0_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000110000101110000011000010111000011101001111110001110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~0_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~4_combout\); + +-- Location: FF_X25_Y30_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_NEW_REG704\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM705\); + +-- Location: FF_X34_Y28_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_NEW_REG700\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM701\); + +-- Location: MLABCELL_X34_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011001100110000001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~38_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~3_combout\); + +-- Location: FF_X34_Y28_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_NEW_REG706\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM707\); + +-- Location: MLABCELL_X34_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM701\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM707\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM705\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM701\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM707\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM705\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM701\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM707\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM705\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM701\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM707\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM705\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001111111000000000101111111001100111111111100110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM377\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM661\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM659\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[26]_OTERM705\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM701\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[26]_OTERM707\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\); + +-- Location: LABCELL_X43_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[26]~feeder_combout\); + +-- Location: FF_X43_Y26_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(26)); + +-- Location: LABCELL_X43_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[26]~feeder_combout\); + +-- Location: FF_X43_Y26_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(26)); + +-- Location: FF_X43_Y26_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(26)); + +-- Location: LABCELL_X44_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[26]~feeder_combout\); + +-- Location: FF_X44_Y26_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(26)); + +-- Location: LABCELL_X43_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(26) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(26)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(26)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(26))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(26) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(26) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(26) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(26)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(26) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(26))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110101000011110011010111110000001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(26), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~0_combout\); + +-- Location: LABCELL_X53_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[26]~feeder_combout\); + +-- Location: FF_X53_Y27_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(26)); + +-- Location: FF_X50_Y26_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(26)); + +-- Location: FF_X50_Y26_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(26)); + +-- Location: FF_X40_Y26_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(26)); + +-- Location: LABCELL_X50_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(26) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(26))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(26))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(26))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(26), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~1_combout\); + +-- Location: LABCELL_X50_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux67~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux67~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~2_combout\); + +-- Location: FF_X50_Y26_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(26)); + +-- Location: FF_X34_Y35_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_OTERM2365\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(26)); + +-- Location: LABCELL_X36_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000000000101010100011011000110111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~1_combout\); + +-- Location: LABCELL_X36_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111010100000101000000110000001111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~0_combout\); + +-- Location: LABCELL_X35_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~1_combout\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~0_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~1_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000101000011011000010100001101101011111000110110101111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~0_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~2_combout\); + +-- Location: MLABCELL_X34_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364_RESYN13032\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~2_combout\)))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101101001111000010110100111100001011010011110000101101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\); + +-- Location: MLABCELL_X34_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_OTERM2365\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011101010101001010001010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_OTERM2365\); + +-- Location: FF_X34_Y35_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_OTERM2365\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE_q\); + +-- Location: FF_X47_Y15_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(26)); + +-- Location: FF_X47_Y15_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(26)); + +-- Location: LABCELL_X44_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[26]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[26]~feeder_combout\); + +-- Location: FF_X44_Y14_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(26)); + +-- Location: FF_X47_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(26)); + +-- Location: LABCELL_X47_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(26)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(26) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(26))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(26))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(26), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(26), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~1_combout\); + +-- Location: FF_X47_Y14_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(26)); + +-- Location: FF_X52_Y16_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(26)); + +-- Location: LABCELL_X53_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[26]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[26]~feeder_combout\); + +-- Location: FF_X53_Y16_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(26)); + +-- Location: FF_X52_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(26)); + +-- Location: LABCELL_X52_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(26))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(26)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(26))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(26)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(26)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(26)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(26), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(26), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(26), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~0_combout\); + +-- Location: LABCELL_X50_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux131~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux131~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~2_combout\); + +-- Location: FF_X50_Y15_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(26)); + +-- Location: LABCELL_X36_Y34_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~1_combout\); + +-- Location: LABCELL_X41_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8_combout\); + +-- Location: LABCELL_X41_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~2_combout\); + +-- Location: LABCELL_X41_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~0_combout\); + +-- Location: LABCELL_X41_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\); + +-- Location: LABCELL_X40_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~3_combout\); + +-- Location: LABCELL_X41_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6_combout\); + +-- Location: MLABCELL_X42_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12_combout\); + +-- Location: LABCELL_X41_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000111011101110111011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4_combout\); + +-- Location: MLABCELL_X42_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\); + +-- Location: LABCELL_X40_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~5_combout\); + +-- Location: LABCELL_X39_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\); + +-- Location: LABCELL_X39_Y34_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7_combout\); + +-- Location: LABCELL_X39_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13_combout\); + +-- Location: LABCELL_X36_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\); + +-- Location: LABCELL_X40_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~4_combout\); + +-- Location: LABCELL_X39_Y34_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~3_combout\); + +-- Location: LABCELL_X39_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~1_combout\); + +-- Location: LABCELL_X36_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\); + +-- Location: LABCELL_X44_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\); + +-- Location: LABCELL_X40_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~2_combout\); + +-- Location: LABCELL_X40_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~5_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~5_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001001010111010100101010011110100010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~6_combout\); + +-- Location: LABCELL_X36_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000011000011111111011101110111010000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~0_combout\); + +-- Location: LABCELL_X39_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13038\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13038_BDD13039\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~1_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~1_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010001101010101011101101000100010101011110111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13038_BDD13039\); + +-- Location: FF_X37_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_OTERM2369\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(26)); + +-- Location: MLABCELL_X37_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13040\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(26) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13038_BDD13039\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(26) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13038_BDD13039\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[26]_NEW2368_RESYN13038_BDD13039\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\); + +-- Location: MLABCELL_X37_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_OTERM2369\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000001110111011111110100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_OTERM2369\); + +-- Location: FF_X37_Y31_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_OTERM2369\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE_q\); + +-- Location: FF_X47_Y28_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(26)); + +-- Location: FF_X48_Y28_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(26)); + +-- Location: FF_X47_Y28_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(26)); + +-- Location: FF_X47_Y28_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(26)); + +-- Location: LABCELL_X47_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(26)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(26)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(26))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(26)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(26))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(26)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(26), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(26), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~0_combout\); + +-- Location: FF_X48_Y30_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(26)); + +-- Location: FF_X50_Y26_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(26)); + +-- Location: FF_X50_Y26_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(26)); + +-- Location: FF_X48_Y30_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(26)); + +-- Location: LABCELL_X50_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(26) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(26))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(26))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(26))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(26), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~1_combout\); + +-- Location: LABCELL_X50_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux259~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux259~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~2_combout\); + +-- Location: FF_X50_Y26_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(26)); + +-- Location: LABCELL_X36_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~1_combout\); + +-- Location: LABCELL_X36_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~0_combout\); + +-- Location: LABCELL_X40_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~4_combout\); + +-- Location: LABCELL_X40_Y34_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~3_combout\); + +-- Location: LABCELL_X40_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~5_combout\); + +-- Location: LABCELL_X40_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~2_combout\); + +-- Location: LABCELL_X39_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~3_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~5_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101110101111111010111010101110101011101011111110111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~5_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~7_combout\); + +-- Location: MLABCELL_X37_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13034\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13034_BDD13035\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101110101111111010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13034_BDD13035\); + +-- Location: MLABCELL_X37_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13036\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13034_BDD13035\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13034_BDD13035\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000011000011110000001100001111110011110000111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[26]_NEW2366_RESYN13034_BDD13035\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\); + +-- Location: MLABCELL_X37_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_OTERM2367\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011101010101001010001010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_OTERM2367\); + +-- Location: FF_X37_Y34_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_OTERM2367\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26)); + +-- Location: LABCELL_X52_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[26]~feeder_combout\); + +-- Location: FF_X52_Y26_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(26)); + +-- Location: LABCELL_X53_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[26]~feeder_combout\); + +-- Location: FF_X53_Y28_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(26)); + +-- Location: LABCELL_X52_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[26]~feeder_combout\); + +-- Location: FF_X52_Y26_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(26)); + +-- Location: FF_X52_Y26_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(26)); + +-- Location: LABCELL_X52_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(26))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(26))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(26)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(26)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(26), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(26), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~0_combout\); + +-- Location: FF_X50_Y25_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(26)); + +-- Location: MLABCELL_X49_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[26]~feeder_combout\); + +-- Location: FF_X49_Y25_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(26)); + +-- Location: FF_X50_Y26_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(26)); + +-- Location: FF_X50_Y26_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(26)); + +-- Location: LABCELL_X50_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(26)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(26)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(26))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(26))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(26), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(26), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(26), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~1_combout\); + +-- Location: LABCELL_X50_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux195~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux195~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~2_combout\); + +-- Location: FF_X50_Y26_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(26)); + +-- Location: LABCELL_X50_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(26)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(26)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(26))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(26)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(26))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(26)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(26), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(26), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~0_combout\); + +-- Location: LABCELL_X39_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~2_combout\); + +-- Location: LABCELL_X39_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\); + +-- Location: LABCELL_X40_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\); + +-- Location: LABCELL_X39_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\); + +-- Location: LABCELL_X39_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110001001001000111010101101000101110011010110011111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~4_combout\); + +-- Location: LABCELL_X40_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~9_combout\); + +-- Location: LABCELL_X40_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~8_combout\); + +-- Location: LABCELL_X47_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~1_combout\); + +-- Location: LABCELL_X39_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~0_combout\); + +-- Location: LABCELL_X44_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~8_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~9_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~5_combout\); + +-- Location: LABCELL_X39_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5_combout\); + +-- Location: LABCELL_X40_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4_combout\); + +-- Location: LABCELL_X40_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\); + +-- Location: LABCELL_X39_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\); + +-- Location: LABCELL_X44_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~8_combout\); + +-- Location: LABCELL_X40_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6_combout\); + +-- Location: LABCELL_X39_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\); + +-- Location: LABCELL_X40_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14_combout\); + +-- Location: LABCELL_X39_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\); + +-- Location: LABCELL_X44_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~9_combout\); + +-- Location: LABCELL_X47_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111100111111001100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~2_combout\); + +-- Location: LABCELL_X39_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~3_combout\); + +-- Location: LABCELL_X41_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10_combout\); + +-- Location: LABCELL_X39_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\); + +-- Location: LABCELL_X44_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~6_combout\); + +-- Location: LABCELL_X44_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12572\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~8_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~8_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000110010101110100101010011011100011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\); + +-- Location: LABCELL_X47_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12574\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~4_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101001100110000010111110101111101010011001111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\); + +-- Location: LABCELL_X47_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_OTERM2357\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001110111111101110100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_OTERM2357\); + +-- Location: FF_X47_Y27_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_OTERM2357\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25)); + +-- Location: FF_X44_Y26_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(25)); + +-- Location: MLABCELL_X45_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[25]~feeder_combout\); + +-- Location: FF_X45_Y26_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(25)); + +-- Location: FF_X44_Y26_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(25)); + +-- Location: FF_X44_Y26_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(25)); + +-- Location: LABCELL_X44_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(25) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(25)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(25))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(25) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(25) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(25) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(25))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(25) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(25) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(25) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101011101110000010100100010101011110111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~0_combout\); + +-- Location: MLABCELL_X49_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[25]~feeder_combout\); + +-- Location: FF_X49_Y22_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(25)); + +-- Location: FF_X50_Y22_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(25)); + +-- Location: MLABCELL_X49_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[25]~feeder_combout\); + +-- Location: FF_X49_Y22_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(25)); + +-- Location: FF_X50_Y22_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(25)); + +-- Location: LABCELL_X50_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(25)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(25) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(25) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(25))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(25))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(25), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~1_combout\); + +-- Location: LABCELL_X50_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux196~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux196~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~2_combout\); + +-- Location: FF_X50_Y22_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(25)); + +-- Location: LABCELL_X39_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001110111010001000100010001110111011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~0_combout\); + +-- Location: LABCELL_X32_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~0_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~0_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0011001100001111001100110000111101010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1421~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~1_combout\); + +-- Location: LABCELL_X32_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[25]_NEW3249\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[25]_OTERM3250\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~1_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101111111110000010100000000111101011111111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1421~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[25]_OTERM3250\); + +-- Location: FF_X32_Y28_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[25]_OTERM3250\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25)); + +-- Location: LABCELL_X40_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[25]~feeder_combout\); + +-- Location: FF_X40_Y11_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(25)); + +-- Location: FF_X41_Y12_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(25)); + +-- Location: FF_X41_Y12_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(25)); + +-- Location: LABCELL_X43_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[25]~feeder_combout\); + +-- Location: FF_X43_Y18_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(25)); + +-- Location: LABCELL_X47_Y12_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(25) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(25) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(25) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(25) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(25), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(25), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~1_combout\); + +-- Location: LABCELL_X40_Y11_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[25]~feeder_combout\); + +-- Location: FF_X40_Y11_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(25)); + +-- Location: FF_X47_Y12_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(25)); + +-- Location: LABCELL_X40_Y11_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[25]~feeder_combout\); + +-- Location: FF_X40_Y11_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(25)); + +-- Location: FF_X47_Y12_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(25)); + +-- Location: LABCELL_X47_Y12_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(25)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(25) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(25)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(25)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(25)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(25), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(25), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~0_combout\); + +-- Location: LABCELL_X47_Y12_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux68~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux68~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~2_combout\); + +-- Location: FF_X47_Y12_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(25)); + +-- Location: LABCELL_X39_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3_combout\); + +-- Location: LABCELL_X40_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0_combout\); + +-- Location: LABCELL_X39_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\); + +-- Location: LABCELL_X39_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1_combout\); + +-- Location: LABCELL_X39_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110100000001110011011111000100111101001100011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~4_combout\); + +-- Location: LABCELL_X44_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~7_combout\); + +-- Location: LABCELL_X44_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~12_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~5_combout\); + +-- Location: LABCELL_X44_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~8_combout\); + +-- Location: LABCELL_X44_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~8_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~9_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~6_combout\); + +-- Location: MLABCELL_X45_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13022\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~7_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~7_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~7_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011010101010001101110101010000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\); + +-- Location: LABCELL_X43_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13024\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100000001001011111110111111000001001011111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\); + +-- Location: LABCELL_X43_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_OTERM2359\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101110101001010101000101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_OTERM2359\); + +-- Location: FF_X43_Y28_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_OTERM2359\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25)); + +-- Location: LABCELL_X52_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[25]~feeder_combout\); + +-- Location: FF_X52_Y26_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(25)); + +-- Location: LABCELL_X52_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[25]~feeder_combout\); + +-- Location: FF_X52_Y26_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(25)); + +-- Location: FF_X49_Y26_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(25)); + +-- Location: FF_X52_Y26_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(25)); + +-- Location: LABCELL_X52_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(25)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(25) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(25) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(25)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(25)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(25), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(25), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~0_combout\); + +-- Location: FF_X52_Y25_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(25)); + +-- Location: LABCELL_X53_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[25]~feeder_combout\); + +-- Location: FF_X53_Y24_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(25)); + +-- Location: LABCELL_X53_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[25]~feeder_combout\); + +-- Location: FF_X53_Y24_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(25)); + +-- Location: FF_X52_Y25_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(25)); + +-- Location: LABCELL_X52_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(25)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(25) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(25)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(25)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(25)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(25), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(25), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~1_combout\); + +-- Location: LABCELL_X52_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010111110101111101011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux260~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux260~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~2_combout\); + +-- Location: FF_X52_Y25_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(25)); + +-- Location: LABCELL_X39_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1485~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1485~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1485~0_combout\); + +-- Location: LABCELL_X35_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13018\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1485~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1485~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1485~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1485~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000000010101010101001010101111101010101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1485~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\); + +-- Location: FF_X40_Y29_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_OTERM2355\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]~DUPLICATE_q\); + +-- Location: LABCELL_X40_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13020\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]~DUPLICATE_q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011111010111101010000010100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\); + +-- Location: LABCELL_X40_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_OTERM2355\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011111111110111001100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_OTERM2355\); + +-- Location: FF_X40_Y29_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_OTERM2355\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25)); + +-- Location: FF_X44_Y22_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(25)); + +-- Location: LABCELL_X47_Y22_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[25]~feeder_combout\); + +-- Location: FF_X47_Y22_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(25)); + +-- Location: MLABCELL_X49_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[25]~feeder_combout\); + +-- Location: FF_X49_Y20_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(25)); + +-- Location: FF_X47_Y22_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(25)); + +-- Location: LABCELL_X47_Y22_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(25)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(25)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(25)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(25) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(25)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010010111110101111100100010011101110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(25), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~0_combout\); + +-- Location: LABCELL_X47_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[25]~feeder_combout\); + +-- Location: FF_X47_Y22_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(25)); + +-- Location: MLABCELL_X49_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[25]~feeder_combout\); + +-- Location: FF_X49_Y24_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(25)); + +-- Location: FF_X49_Y24_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(25)); + +-- Location: MLABCELL_X49_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[25]~feeder_combout\); + +-- Location: FF_X49_Y20_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(25)); + +-- Location: MLABCELL_X49_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(25) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(25) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(25))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(25)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(25) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(25))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(25))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000101011001110100100110101011100011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(25), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~1_combout\); + +-- Location: MLABCELL_X49_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux132~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux132~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~2_combout\); + +-- Location: FF_X49_Y24_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(25)); + +-- Location: LABCELL_X50_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(25) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(25) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(25) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(25) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(25), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(25), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~0_combout\); + +-- Location: FF_X50_Y11_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_NEW_REG1130\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1131\); + +-- Location: MLABCELL_X37_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~1_combout\); + +-- Location: LABCELL_X39_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~0_combout\); + +-- Location: LABCELL_X44_Y31_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111111111111000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12_combout\); + +-- Location: LABCELL_X36_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4_combout\); + +-- Location: LABCELL_X44_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6_combout\); + +-- Location: LABCELL_X44_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\); + +-- Location: MLABCELL_X45_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~5_combout\); + +-- Location: MLABCELL_X42_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13_combout\); + +-- Location: MLABCELL_X42_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\); + +-- Location: MLABCELL_X42_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5_combout\); + +-- Location: LABCELL_X40_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000000000000000000000111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\); + +-- Location: MLABCELL_X45_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~4_combout\); + +-- Location: LABCELL_X44_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2_combout\); + +-- Location: LABCELL_X43_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0_combout\); + +-- Location: LABCELL_X43_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8_combout\); + +-- Location: LABCELL_X44_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111111111111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\); + +-- Location: MLABCELL_X45_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~3_combout\); + +-- Location: MLABCELL_X42_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9_combout\); + +-- Location: MLABCELL_X42_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\); + +-- Location: MLABCELL_X42_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000110111011101110111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1_combout\); + +-- Location: LABCELL_X40_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\); + +-- Location: MLABCELL_X45_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~2_combout\); + +-- Location: MLABCELL_X45_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~4_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~4_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~5_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~4_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~4_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000011110111010000001100010001110011111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~6_combout\); + +-- Location: MLABCELL_X42_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13048\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13048_BDD13049\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~1_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011000000010010001111001101111011111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13048_BDD13049\); + +-- Location: FF_X42_Y28_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_OTERM2375\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13050\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13048_BDD13049\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13048_BDD13049\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]_NEW2374_RESYN13048_BDD13049\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\); + +-- Location: MLABCELL_X42_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_OTERM2375\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_OTERM2375\); + +-- Location: FF_X42_Y28_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_OTERM2375\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24)); + +-- Location: MLABCELL_X49_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[24]~feeder_combout\); + +-- Location: FF_X49_Y28_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(24)); + +-- Location: MLABCELL_X49_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[24]~feeder_combout\); + +-- Location: FF_X49_Y28_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(24)); + +-- Location: MLABCELL_X49_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[24]~feeder_combout\); + +-- Location: FF_X49_Y28_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(24)); + +-- Location: FF_X45_Y28_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(24)); + +-- Location: MLABCELL_X45_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(24)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(24) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(24) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(24)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(24)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(24), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~1_combout\); + +-- Location: FF_X47_Y28_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(24)); + +-- Location: FF_X47_Y28_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(24)); + +-- Location: FF_X45_Y28_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(24)); + +-- Location: FF_X47_Y28_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(24)); + +-- Location: LABCELL_X47_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(24)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(24)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(24)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(24) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(24) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(24), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(24), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~0_combout\); + +-- Location: MLABCELL_X45_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux261~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux261~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~2_combout\); + +-- Location: FF_X45_Y28_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(24)); + +-- Location: MLABCELL_X45_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8695\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8695_BDD8696\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111000000000101010100100111001001111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8695_BDD8696\); + +-- Location: MLABCELL_X18_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8693\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8693_BDD8694\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8693_BDD8694\); + +-- Location: MLABCELL_X42_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8697\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8697_BDD8698\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8693_BDD8694\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8693_BDD8694\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8695_BDD8696\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8693_BDD8694\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8695_BDD8696\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8695_BDD8696\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8693_BDD8694\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8697_BDD8698\); + +-- Location: LABCELL_X32_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8697_BDD8698\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8697_BDD8698\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100010111000101000000001111111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8697_BDD8698\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_combout\); + +-- Location: LABCELL_X32_Y27_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[24]_NEW3253\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[24]_OTERM3254\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(24))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(24))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[24]_OTERM3254\); + +-- Location: FF_X32_Y27_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[24]_OTERM3254\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(24)); + +-- Location: MLABCELL_X45_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[24]~feeder_combout\); + +-- Location: FF_X45_Y25_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(24)); + +-- Location: MLABCELL_X45_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[24]~feeder_combout\); + +-- Location: FF_X45_Y25_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(24)); + +-- Location: FF_X45_Y29_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(24)); + +-- Location: FF_X45_Y25_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(24)); + +-- Location: MLABCELL_X45_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(24)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(24) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(24)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(24)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(24)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(24), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~1_combout\); + +-- Location: LABCELL_X41_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[24]~feeder_combout\); + +-- Location: FF_X41_Y24_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(24)); + +-- Location: LABCELL_X41_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[24]~feeder_combout\); + +-- Location: FF_X41_Y24_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(24)); + +-- Location: FF_X41_Y24_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(24)); + +-- Location: FF_X45_Y26_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(24)); + +-- Location: LABCELL_X41_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(24) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(24))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(24) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(24) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(24))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(24) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(24)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(24) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(24)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001111100110001000111001100110100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(24), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~0_combout\); + +-- Location: MLABCELL_X49_Y24_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux69~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux69~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~2_combout\); + +-- Location: FF_X49_Y24_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(24)); + +-- Location: LABCELL_X39_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~0_combout\); + +-- Location: MLABCELL_X37_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011101110011000001110100110011000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~1_combout\); + +-- Location: MLABCELL_X45_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~3_combout\); + +-- Location: MLABCELL_X45_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~4_combout\); + +-- Location: MLABCELL_X45_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~5_combout\); + +-- Location: MLABCELL_X45_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~2_combout\); + +-- Location: LABCELL_X44_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~5_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101111101110111010111110101010101011111011101110101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~5_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~7_combout\); + +-- Location: MLABCELL_X37_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13044\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13044_BDD13045\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101011111011111010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13044_BDD13045\); + +-- Location: FF_X37_Y34_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_OTERM2373\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(24)); + +-- Location: MLABCELL_X37_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13046\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(24) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13044_BDD13045\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(24) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13044_BDD13045\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101111000000001010111101010000111111110101000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]_NEW2372_RESYN13044_BDD13045\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\); + +-- Location: MLABCELL_X37_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_OTERM2373\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(24) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000101101110101111111100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_OTERM2373\); + +-- Location: FF_X37_Y34_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_OTERM2373\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE_q\); + +-- Location: LABCELL_X47_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[24]~feeder_combout\); + +-- Location: FF_X47_Y26_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(24)); + +-- Location: LABCELL_X48_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[24]~feeder_combout\); + +-- Location: FF_X48_Y26_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(24)); + +-- Location: FF_X48_Y26_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(24)); + +-- Location: LABCELL_X48_Y26_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[24]~feeder_combout\); + +-- Location: FF_X48_Y26_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(24)); + +-- Location: LABCELL_X48_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(24) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(24)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(24)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(24) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(24))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(24) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(24) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(24) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(24)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(24) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(24))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110101000011110011010111110000001101011111111100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(24), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~0_combout\); + +-- Location: MLABCELL_X49_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[24]~feeder_combout\); + +-- Location: FF_X49_Y30_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(24)); + +-- Location: FF_X44_Y28_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(24)); + +-- Location: FF_X48_Y28_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(24)); + +-- Location: MLABCELL_X49_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[24]~feeder_combout\); + +-- Location: FF_X49_Y30_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(24)); + +-- Location: LABCELL_X48_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(24) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(24))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(24)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(24))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(24) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(24) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(24) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(24)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(24) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(24) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(24) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010000100010101111110111011000010101011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~1_combout\); + +-- Location: MLABCELL_X45_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux197~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux197~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~2_combout\); + +-- Location: FF_X45_Y28_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(24)); + +-- Location: MLABCELL_X37_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~1_combout\); + +-- Location: LABCELL_X39_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~0_combout\); + +-- Location: MLABCELL_X37_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~1_combout\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~0_combout\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~1_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000101000011011000010100001101101011111000110110101111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~0_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~2_combout\); + +-- Location: FF_X40_Y27_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_OTERM2371\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]~DUPLICATE_q\); + +-- Location: LABCELL_X40_Y27_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370_RESYN13042\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~2_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001111000010100000111101011111000011110101111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[24]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\); + +-- Location: LABCELL_X40_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_OTERM2371\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011111111110111001100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_OTERM2371\); + +-- Location: FF_X40_Y27_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_OTERM2371\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24)); + +-- Location: LABCELL_X48_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[24]~feeder_combout\); + +-- Location: FF_X48_Y16_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(24)); + +-- Location: MLABCELL_X49_Y16_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[24]~feeder_combout\); + +-- Location: FF_X49_Y16_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(24)); + +-- Location: FF_X48_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(24)); + +-- Location: LABCELL_X48_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[24]~feeder_combout\); + +-- Location: FF_X48_Y16_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(24)); + +-- Location: LABCELL_X48_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(24) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(24) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(24))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(24) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(24))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(24) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(24))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000100111001101101000110110011100101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(24), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~1_combout\); + +-- Location: MLABCELL_X49_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[24]~feeder_combout\); + +-- Location: FF_X49_Y16_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(24)); + +-- Location: FF_X52_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(24)); + +-- Location: FF_X53_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(24)); + +-- Location: FF_X52_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(24)); + +-- Location: LABCELL_X52_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(24))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(24))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(24)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(24) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(24)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(24), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~0_combout\); + +-- Location: LABCELL_X52_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux133~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux133~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~2_combout\); + +-- Location: FF_X52_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(24)); + +-- Location: MLABCELL_X45_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(24)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(24)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(24)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(24) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(24) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(24), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(24), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~0_combout\); + +-- Location: FF_X49_Y11_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_NEW_REG1134\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1135\); + +-- Location: LABCELL_X40_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1_combout\); + +-- Location: LABCELL_X40_Y36_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0_combout\); + +-- Location: LABCELL_X40_Y36_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\); + +-- Location: LABCELL_X40_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2_combout\); + +-- Location: LABCELL_X40_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1487~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1487~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100111101001100011100110111000001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1487~0_combout\); + +-- Location: LABCELL_X36_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN12998\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN12998_BDD12999\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1487~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1487~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1487~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1487~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001010101010100000101001010101010111111111111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1487~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN12998_BDD12999\); + +-- Location: MLABCELL_X37_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN13000\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN12998_BDD12999\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN12998_BDD12999\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[23]_NEW2342_RESYN12998_BDD12999\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\); + +-- Location: MLABCELL_X37_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_OTERM2343\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001101111111011101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_OTERM2343\); + +-- Location: FF_X37_Y24_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_OTERM2343\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23)); + +-- Location: FF_X41_Y12_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(23)); + +-- Location: FF_X41_Y12_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(23)); + +-- Location: FF_X41_Y12_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(23)); + +-- Location: FF_X37_Y13_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(23)); + +-- Location: LABCELL_X41_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(23)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(23))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(23) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(23))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(23) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010000000000110101111111110011010100001111001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~1_combout\); + +-- Location: FF_X37_Y13_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(23)); + +-- Location: MLABCELL_X37_Y14_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[23]~feeder_combout\); + +-- Location: FF_X37_Y14_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(23)); + +-- Location: MLABCELL_X37_Y11_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[23]~feeder_combout\); + +-- Location: FF_X37_Y11_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(23)); + +-- Location: FF_X37_Y13_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(23)); + +-- Location: MLABCELL_X37_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(23)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(23)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(23)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~0_combout\); + +-- Location: MLABCELL_X42_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux134~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux134~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~2_combout\); + +-- Location: FF_X42_Y15_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(23)); + +-- Location: LABCELL_X31_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001101101010101000010100101010100011011010101010101111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29_combout\); + +-- Location: MLABCELL_X28_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~12_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\)))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001100000011000000110000001111001100111111111101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~29_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~12_combout\); + +-- Location: MLABCELL_X23_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001110100110011000011000011001100011101001100110011111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~DUPLICATE_q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21_combout\); + +-- Location: MLABCELL_X23_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000010100000101000001010000010110111011101110111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~21_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~4_combout\); + +-- Location: LABCELL_X26_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~17_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000111100000000000011110000000001010101111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0), + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~17_combout\); + +-- Location: LABCELL_X26_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~17_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~17_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\)))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~17_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~17_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000011111111000000001111111100001111001100110000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~17_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~0_combout\); + +-- Location: LABCELL_X31_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~25_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000111100000000000011110000000001010101111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~25_combout\); + +-- Location: LABCELL_X26_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~25_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~25_combout\ & ((((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE_q\))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~25_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~25_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0011001100110011001100110011001100011101000111010000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~25_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~8_combout\); + +-- Location: LABCELL_X26_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~12_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~12_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~12_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux299~12_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011100010011010101101000101011001111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~16_combout\); + +-- Location: FF_X26_Y31_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_NEW_REG406\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~16_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM407\); + +-- Location: LABCELL_X40_Y36_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~4_combout\); + +-- Location: FF_X34_Y22_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_NEW_REG404\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM405\); + +-- Location: FF_X34_Y22_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_NEW_REG402\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM403\); + +-- Location: FF_X34_Y22_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG320\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321\); + +-- Location: MLABCELL_X34_Y22_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM403\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM405\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM403\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM405\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM403\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM407\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM405\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM403\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM407\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM405\))) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM407\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM405\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM403\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM321\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\); + +-- Location: FF_X39_Y15_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(23)); + +-- Location: LABCELL_X36_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1599~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[23]~feeder_combout\); + +-- Location: FF_X36_Y15_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(23)); + +-- Location: LABCELL_X36_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1599~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[23]~feeder_combout\); + +-- Location: FF_X36_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(23)); + +-- Location: FF_X36_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(23)); + +-- Location: LABCELL_X36_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(23) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(23)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(23)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~0_combout\); + +-- Location: LABCELL_X40_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1599~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[23]~feeder_combout\); + +-- Location: FF_X40_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(23)); + +-- Location: LABCELL_X41_Y15_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1599~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[23]~feeder_combout\); + +-- Location: FF_X41_Y15_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(23)); + +-- Location: FF_X40_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(23)); + +-- Location: FF_X40_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(23)); + +-- Location: LABCELL_X40_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(23) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(23))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(23))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(23))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001100000101111100111111010100000011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~1_combout\); + +-- Location: LABCELL_X39_Y15_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux262~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux262~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~2_combout\); + +-- Location: FF_X39_Y15_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(23)); + +-- Location: LABCELL_X40_Y36_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~3_combout\); + +-- Location: LABCELL_X40_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~2_combout\); + +-- Location: LABCELL_X40_Y36_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~1_combout\); + +-- Location: LABCELL_X40_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~0_combout\); + +-- Location: LABCELL_X41_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13322\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~2_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\); + +-- Location: LABCELL_X40_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13324\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000101100010101100111100110000011101011011101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\); + +-- Location: LABCELL_X40_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_OTERM2534\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_OTERM2534\); + +-- Location: FF_X40_Y26_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_OTERM2534\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23)); + +-- Location: FF_X42_Y19_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(23)); + +-- Location: MLABCELL_X42_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[23]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[23]~feeder_combout\); + +-- Location: FF_X42_Y19_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(23)); + +-- Location: FF_X41_Y20_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(23)); + +-- Location: FF_X42_Y19_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(23)); + +-- Location: MLABCELL_X42_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(23))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(23))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~1_combout\); + +-- Location: LABCELL_X39_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[23]~feeder_combout\); + +-- Location: FF_X39_Y15_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(23)); + +-- Location: LABCELL_X41_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[23]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[23]~feeder_combout\); + +-- Location: FF_X41_Y17_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(23)); + +-- Location: FF_X43_Y15_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(23)); + +-- Location: FF_X43_Y15_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(23)); + +-- Location: LABCELL_X43_Y15_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(23)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(23)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(23)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(23) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(23))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(23) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110100001000010111010101101010001111100010101101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~0_combout\); + +-- Location: MLABCELL_X42_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux198~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux198~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~2_combout\); + +-- Location: FF_X42_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(23)); + +-- Location: LABCELL_X40_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~0_combout\); + +-- Location: LABCELL_X40_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100100010011101110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~1_combout\); + +-- Location: LABCELL_X32_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~1_combout\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~1_combout\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101010100001111010101010000111100110011000000000011001100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~2_combout\); + +-- Location: LABCELL_X32_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]_NEW3245\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]_OTERM3246\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(23))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111110001000000011111000100001101111111010000110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]_OTERM3246\); + +-- Location: FF_X32_Y28_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]_OTERM3246\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(23)); + +-- Location: MLABCELL_X42_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(23) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[23]~feeder_combout\); + +-- Location: FF_X42_Y17_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(23)); + +-- Location: FF_X39_Y15_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(23)); + +-- Location: FF_X42_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(23)); + +-- Location: FF_X42_Y15_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(23)); + +-- Location: MLABCELL_X42_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(23))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(23))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(23))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(23))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(23)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(23))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000011001001010100011101101001100010111010110111001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~0_combout\); + +-- Location: LABCELL_X41_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(23) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[23]~feeder_combout\); + +-- Location: FF_X41_Y15_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(23)); + +-- Location: LABCELL_X40_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[23]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(23) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[23]~feeder_combout\); + +-- Location: FF_X40_Y15_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(23)); + +-- Location: LABCELL_X40_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[23]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(23) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[23]~feeder_combout\); + +-- Location: FF_X40_Y15_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(23)); + +-- Location: FF_X41_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(23)); + +-- Location: LABCELL_X41_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(23)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(23)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(23)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~1_combout\); + +-- Location: MLABCELL_X42_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux70~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux70~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~2_combout\); + +-- Location: FF_X42_Y15_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(23)); + +-- Location: MLABCELL_X42_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(23)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(23))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(23) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(23)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(23) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(23))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110100000001110011011111000100111101001100011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~0_combout\); + +-- Location: MLABCELL_X49_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100111101001100011100110111000001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]~74_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]~73_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector85~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]~62_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~1_combout\); + +-- Location: FF_X49_Y11_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_NEW_REG1136\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1137\); + +-- Location: MLABCELL_X49_Y11_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1137\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1135\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1137\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1135\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]_OTERM1135\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]_OTERM1137\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\); + +-- Location: LABCELL_X50_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111100111111001100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector84~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]~68_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]~66_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]~67_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~1_combout\); + +-- Location: FF_X50_Y11_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_NEW_REG1132\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1133\); + +-- Location: LABCELL_X50_Y11_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1133\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1131\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1133\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1131\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101111000000001010111101010000111111110101000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]_OTERM1131\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]_OTERM1133\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\); + +-- Location: MLABCELL_X45_Y11_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector83~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]~64_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]~71_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]~60_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~1_combout\); + +-- Location: FF_X45_Y11_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_NEW_REG1140\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1141\); + +-- Location: FF_X45_Y11_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_NEW_REG1138\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1139\); + +-- Location: MLABCELL_X45_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1139\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1141\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1139\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1141\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1139\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]_OTERM1141\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]_OTERM1139\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\); + +-- Location: MLABCELL_X45_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]~62_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector82~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]~63_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]~69_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~1_combout\); + +-- Location: FF_X45_Y11_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_NEW_REG1105\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1106\); + +-- Location: MLABCELL_X45_Y11_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1106\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1104\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1106\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1104\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]_OTERM1104\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]_OTERM1106\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\); + +-- Location: LABCELL_X39_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~0_combout\); + +-- Location: LABCELL_X39_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~2_combout\); + +-- Location: LABCELL_X39_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~1_combout\); + +-- Location: LABCELL_X39_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\); + +-- Location: LABCELL_X39_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4_combout\); + +-- Location: LABCELL_X43_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6_combout\); + +-- Location: LABCELL_X43_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~12_combout\); + +-- Location: LABCELL_X43_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~4_combout\); + +-- Location: LABCELL_X43_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~14_combout\); + +-- Location: LABCELL_X44_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~14_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~4_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~12_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~5_combout\); + +-- Location: LABCELL_X40_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\); + +-- Location: LABCELL_X41_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3_combout\); + +-- Location: LABCELL_X40_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9_combout\); + +-- Location: LABCELL_X41_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\); + +-- Location: LABCELL_X44_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~8_combout\); + +-- Location: LABCELL_X43_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~15_combout\); + +-- Location: LABCELL_X43_Y33_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13_combout\); + +-- Location: LABCELL_X41_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~7_combout\); + +-- Location: LABCELL_X40_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~5_combout\); + +-- Location: LABCELL_X44_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~7_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~15_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~5_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~7_combout\); + +-- Location: LABCELL_X43_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2_combout\); + +-- Location: LABCELL_X40_Y33_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0_combout\); + +-- Location: LABCELL_X40_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8_combout\); + +-- Location: LABCELL_X41_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\); + +-- Location: LABCELL_X44_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~6_combout\); + +-- Location: MLABCELL_X45_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13006\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~5_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000010100101111110111011101110110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\); + +-- Location: LABCELL_X47_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13008\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011010101110000001110001010110011111101111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\); + +-- Location: FF_X47_Y27_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_OTERM2349\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(27)); + +-- Location: LABCELL_X47_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_OTERM2349\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(27) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011111111110111001100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_OTERM2349\); + +-- Location: FF_X47_Y27_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_OTERM2349\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\); + +-- Location: LABCELL_X48_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[27]~feeder_combout\); + +-- Location: FF_X48_Y30_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(27)); + +-- Location: LABCELL_X48_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[27]~feeder_combout\); + +-- Location: FF_X48_Y30_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(27)); + +-- Location: FF_X48_Y28_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(27)); + +-- Location: LABCELL_X48_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[27]~feeder_combout\); + +-- Location: FF_X48_Y30_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(27)); + +-- Location: LABCELL_X48_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(27) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(27) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(27))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(27) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(27))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(27) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(27))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~1_combout\); + +-- Location: FF_X47_Y27_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(27)); + +-- Location: LABCELL_X48_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[27]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[27]~feeder_combout\); + +-- Location: FF_X48_Y28_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(27)); + +-- Location: FF_X48_Y28_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(27)); + +-- Location: FF_X48_Y26_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(27)); + +-- Location: LABCELL_X48_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(27) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(27))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(27))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(27) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(27))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(27))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(27) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(27)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(27))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000011001001010100011101101001100010111010110111001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(27), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~0_combout\); + +-- Location: MLABCELL_X45_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux258~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux258~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~2_combout\); + +-- Location: FF_X45_Y28_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(27)); + +-- Location: LABCELL_X43_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~3_combout\); + +-- Location: LABCELL_X39_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~2_combout\); + +-- Location: LABCELL_X40_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~0_combout\); + +-- Location: LABCELL_X43_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~1_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~1_combout\); + +-- Location: LABCELL_X43_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111010100110101001111110000111111110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~4_combout\); + +-- Location: LABCELL_X44_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~5_combout\); + +-- Location: LABCELL_X44_Y33_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~14_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~4_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~12_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~8_combout\); + +-- Location: LABCELL_X44_Y33_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~7_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~15_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~5_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~15_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~13_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~9_combout\); + +-- Location: LABCELL_X44_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~6_combout\); + +-- Location: LABCELL_X44_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12568\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~5_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~8_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~8_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100110000111101010011111100000101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\); + +-- Location: MLABCELL_X42_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12570\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27) & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000010100110101010110100011101010101111001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\); + +-- Location: MLABCELL_X42_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_OTERM2347\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_OTERM2347\); + +-- Location: FF_X42_Y28_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_OTERM2347\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27)); + +-- Location: MLABCELL_X49_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[27]~feeder_combout\); + +-- Location: FF_X49_Y28_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(27)); + +-- Location: MLABCELL_X49_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[27]~feeder_combout\); + +-- Location: FF_X49_Y28_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(27)); + +-- Location: FF_X48_Y28_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(27)); + +-- Location: MLABCELL_X49_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[27]~feeder_combout\); + +-- Location: FF_X49_Y28_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(27)); + +-- Location: LABCELL_X48_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(27) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(27) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(27))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(27) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(27) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(27) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(27)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(27))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101010000111100110101111100000011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(27), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~1_combout\); + +-- Location: FF_X47_Y28_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(27)); + +-- Location: LABCELL_X47_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[27]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[27]~feeder_combout\); + +-- Location: FF_X47_Y28_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(27)); + +-- Location: FF_X48_Y28_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(27)); + +-- Location: FF_X47_Y28_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(27)); + +-- Location: LABCELL_X47_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(27)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(27) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(27)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(27)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(27)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(27), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~0_combout\); + +-- Location: MLABCELL_X45_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux194~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux194~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~2_combout\); + +-- Location: FF_X45_Y28_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(27)); + +-- Location: LABCELL_X39_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1483~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1483~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1483~0_combout\); + +-- Location: LABCELL_X35_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13002\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1483~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1483~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1483~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1483~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001000000011100000111000001001111010011110111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1483~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\); + +-- Location: FF_X44_Y27_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_OTERM2345\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]~DUPLICATE_q\); + +-- Location: LABCELL_X44_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13004\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000011110000111101011111010111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\); + +-- Location: LABCELL_X44_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_OTERM2345\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_OTERM2345\); + +-- Location: FF_X44_Y27_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_OTERM2345\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27)); + +-- Location: FF_X52_Y31_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(27)); + +-- Location: LABCELL_X52_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[27]~feeder_combout\); + +-- Location: FF_X52_Y30_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(27)); + +-- Location: FF_X52_Y31_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(27)); + +-- Location: FF_X52_Y31_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(27)); + +-- Location: LABCELL_X52_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(27)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(27) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(27) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(27)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(27)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(27), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(27), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~1_combout\); + +-- Location: FF_X49_Y26_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(27)); + +-- Location: LABCELL_X48_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[27]~feeder_combout\); + +-- Location: FF_X48_Y26_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(27)); + +-- Location: FF_X48_Y26_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(27)); + +-- Location: LABCELL_X48_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[27]~feeder_combout\); + +-- Location: FF_X48_Y26_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(27)); + +-- Location: LABCELL_X48_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(27) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(27)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(27)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(27) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(27))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(27) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(27) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(27) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(27)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(27) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(27))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011101001100110001110111001100000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(27), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~0_combout\); + +-- Location: MLABCELL_X45_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux130~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux130~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~2_combout\); + +-- Location: FF_X45_Y28_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(27)); + +-- Location: MLABCELL_X34_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011001100110000001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~4_combout\); + +-- Location: FF_X34_Y28_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_NEW_REG702\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM703\); + +-- Location: LABCELL_X19_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~1_combout\); + +-- Location: LABCELL_X19_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~2_combout\); + +-- Location: LABCELL_X24_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(11))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~1_combout\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~1_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000110000011101000011000001110100111111000111010011111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~2_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~5_combout\); + +-- Location: FF_X24_Y28_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_NEW_REG698\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM699\); + +-- Location: MLABCELL_X34_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM699\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM701\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM699\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM703\) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM699\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM703\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000000000000001011111111111111100111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM703\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM701\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM659\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM377\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM661\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM699\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\); + +-- Location: FF_X36_Y27_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(27)); + +-- Location: LABCELL_X48_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[27]~feeder_combout\); + +-- Location: FF_X48_Y27_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(27)); + +-- Location: MLABCELL_X49_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[27]~feeder_combout\); + +-- Location: FF_X49_Y27_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(27)); + +-- Location: FF_X48_Y27_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(27)); + +-- Location: LABCELL_X48_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(27)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(27) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(27) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(27)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(27)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(27), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~1_combout\); + +-- Location: FF_X44_Y26_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(27)); + +-- Location: LABCELL_X43_Y26_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[27]~feeder_combout\); + +-- Location: FF_X43_Y26_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(27)); + +-- Location: FF_X43_Y26_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(27)); + +-- Location: LABCELL_X43_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[27]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[27]~feeder_combout\); + +-- Location: FF_X43_Y26_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(27)); + +-- Location: LABCELL_X43_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(27) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(27))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(27) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(27) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(27))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(27) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(27)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(27) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(27)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001111100110001000111001100110100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(27), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~0_combout\); + +-- Location: MLABCELL_X45_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux66~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux66~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~2_combout\); + +-- Location: FF_X45_Y28_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(27)); + +-- Location: MLABCELL_X45_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(27) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(27) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(27) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(27) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(27), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(27), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~0_combout\); + +-- Location: LABCELL_X50_Y11_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111010100000101000000110000001111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]~61_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]~66_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]~73_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector81~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~1_combout\); + +-- Location: FF_X50_Y11_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_NEW_REG1101\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1102\); + +-- Location: LABCELL_X50_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1102\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1100\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1102\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1100\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]_OTERM1100\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]_OTERM1102\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\); + +-- Location: FF_X32_Y26_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_NEW_REG472\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM473\); + +-- Location: LABCELL_X29_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111111111111111111100111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~0_combout\); + +-- Location: FF_X29_Y29_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_NEW_REG474\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM475\); + +-- Location: LABCELL_X32_Y26_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469~feeder_combout\); + +-- Location: FF_X32_Y26_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_NEW_REG468\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469\); + +-- Location: LABCELL_X32_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101110001011100000011110000111101011100010111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~3_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~3_combout\); + +-- Location: FF_X32_Y26_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_NEW_REG470\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471\); + +-- Location: LABCELL_X32_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM473\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM473\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM475\))))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101000001010000000011110000111101010000001100000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM473\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM475\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM469\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM437\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM471\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\); + +-- Location: LABCELL_X48_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[30]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1416~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[30]~feeder_combout\); + +-- Location: FF_X48_Y16_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(30)); + +-- Location: LABCELL_X39_Y18_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[30]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1416~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[30]~feeder_combout\); + +-- Location: FF_X39_Y18_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(30)); + +-- Location: FF_X39_Y18_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(30)); + +-- Location: LABCELL_X39_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[30]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1416~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[30]~feeder_combout\); + +-- Location: FF_X39_Y18_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(30)); + +-- Location: LABCELL_X39_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(30) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(30))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(30)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(30) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(30))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(30) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(30) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(30) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(30))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(30)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(30) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(30))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(30) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011010000101010001111110110000101110101011010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(30), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(30), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~1_combout\); + +-- Location: FF_X44_Y16_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(30)); + +-- Location: LABCELL_X50_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[30]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1416~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[30]~feeder_combout\); + +-- Location: FF_X50_Y14_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(30)); + +-- Location: LABCELL_X50_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[30]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1416~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[30]~feeder_combout\); + +-- Location: FF_X50_Y14_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(30)); + +-- Location: FF_X50_Y14_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(30)); + +-- Location: LABCELL_X50_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(30)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(30) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(30) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(30))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(30)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(30))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(30)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(30), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(30), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(30), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~0_combout\); + +-- Location: LABCELL_X47_Y14_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux63~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux63~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~2_combout\); + +-- Location: FF_X47_Y14_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(30)); + +-- Location: LABCELL_X35_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[30]_NEW2396\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[30]_OTERM2397\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100100000011101010010000001110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[62]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[30]_OTERM2397\); + +-- Location: FF_X35_Y23_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[30]_OTERM2397\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30)); + +-- Location: LABCELL_X41_Y12_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[30]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[30]~feeder_combout\); + +-- Location: FF_X41_Y12_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(30)); + +-- Location: LABCELL_X41_Y12_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[30]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[30]~feeder_combout\); + +-- Location: FF_X41_Y12_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(30)); + +-- Location: FF_X41_Y12_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(30)); + +-- Location: FF_X40_Y12_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(30)); + +-- Location: LABCELL_X41_Y12_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(30) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(30)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(30)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(30) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(30))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(30) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(30) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(30) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(30)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(30) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(30) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(30))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110100000001110011011111000100111101001100011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(30), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(30), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~1_combout\); + +-- Location: FF_X41_Y14_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(30)); + +-- Location: FF_X40_Y12_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(30)); + +-- Location: FF_X41_Y14_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(30)); + +-- Location: FF_X41_Y14_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(30)); + +-- Location: LABCELL_X41_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(30)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(30) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(30) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(30))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(30))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(30), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(30), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(30), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~0_combout\); + +-- Location: LABCELL_X41_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux127~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux127~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~2_combout\); + +-- Location: FF_X41_Y13_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(30)); + +-- Location: LABCELL_X47_Y14_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(30))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(30)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(30), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~0_combout\); + +-- Location: FF_X45_Y11_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_NEW_REG1089\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1090\); + +-- Location: MLABCELL_X45_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~1_combout\); + +-- Location: MLABCELL_X45_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~0_combout\); + +-- Location: LABCELL_X40_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~1_combout\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~1_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000101000011011000010100001101101011111000110110101111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~0_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~2_combout\); + +-- Location: LABCELL_X40_Y26_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376_RESYN13052\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~2_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\); + +-- Location: LABCELL_X40_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_OTERM2377\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001110111111101110100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_OTERM2377\); + +-- Location: FF_X40_Y26_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_OTERM2377\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28)); + +-- Location: LABCELL_X41_Y12_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[28]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[28]~feeder_combout\); + +-- Location: FF_X41_Y12_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(28)); + +-- Location: FF_X39_Y12_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(28)); + +-- Location: LABCELL_X40_Y12_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[28]~feeder_combout\); + +-- Location: FF_X40_Y12_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(28)); + +-- Location: FF_X39_Y12_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(28)); + +-- Location: LABCELL_X39_Y12_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(28)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(28) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(28) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(28))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(28))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(28), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(28), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~1_combout\); + +-- Location: LABCELL_X40_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[28]~feeder_combout\); + +-- Location: FF_X40_Y12_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(28)); + +-- Location: LABCELL_X40_Y12_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[28]~feeder_combout\); + +-- Location: FF_X40_Y12_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(28)); + +-- Location: LABCELL_X39_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[28]~feeder_combout\); + +-- Location: FF_X39_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(28)); + +-- Location: FF_X39_Y12_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(28)); + +-- Location: LABCELL_X39_Y12_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(28)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(28) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(28)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(28))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(28))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(28), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~0_combout\); + +-- Location: MLABCELL_X45_Y14_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux129~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux129~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~2_combout\); + +-- Location: FF_X45_Y14_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(28)); + +-- Location: MLABCELL_X45_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~1_combout\); + +-- Location: LABCELL_X43_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~12_combout\); + +-- Location: LABCELL_X43_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~14_combout\); + +-- Location: LABCELL_X43_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~6_combout\); + +-- Location: MLABCELL_X42_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~4_combout\); + +-- Location: LABCELL_X43_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~6_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~14_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~4_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~12_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~5_combout\); + +-- Location: MLABCELL_X42_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~13_combout\); + +-- Location: MLABCELL_X42_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~15_combout\); + +-- Location: LABCELL_X41_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~5_combout\); + +-- Location: LABCELL_X41_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~7_combout\); + +-- Location: LABCELL_X43_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~7_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~15_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~5_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~13_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~4_combout\); + +-- Location: MLABCELL_X42_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8_combout\); + +-- Location: MLABCELL_X42_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0_combout\); + +-- Location: MLABCELL_X42_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2_combout\); + +-- Location: MLABCELL_X42_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\); + +-- Location: MLABCELL_X42_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~3_combout\); + +-- Location: MLABCELL_X42_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\); + +-- Location: LABCELL_X41_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\); + +-- Location: LABCELL_X41_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1_combout\); + +-- Location: MLABCELL_X42_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\); + +-- Location: LABCELL_X43_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~2_combout\); + +-- Location: LABCELL_X43_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~4_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~5_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~3_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~6_combout\); + +-- Location: MLABCELL_X45_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~0_combout\); + +-- Location: MLABCELL_X45_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13058\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~1_combout\)))) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\); + +-- Location: FF_X44_Y29_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_OTERM2381\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(28)); + +-- Location: LABCELL_X44_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13060\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(28) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(28) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000110000001100001111000011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\); + +-- Location: LABCELL_X44_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_OTERM2381\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000101101111111010111100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_OTERM2381\); + +-- Location: FF_X44_Y29_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_OTERM2381\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE_q\); + +-- Location: FF_X47_Y23_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(28)); + +-- Location: FF_X44_Y29_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(28)); + +-- Location: FF_X47_Y23_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(28)); + +-- Location: FF_X47_Y23_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(28)); + +-- Location: LABCELL_X47_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(28)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(28) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(28) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(28)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(28)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(28), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(28), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~1_combout\); + +-- Location: FF_X48_Y14_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(28)); + +-- Location: FF_X50_Y16_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(28)); + +-- Location: FF_X47_Y14_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(28)); + +-- Location: LABCELL_X47_Y14_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[28]~feeder_combout\); + +-- Location: FF_X47_Y14_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(28)); + +-- Location: LABCELL_X47_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(28) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(28)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(28))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(28) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(28) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(28))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(28) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(28) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(28) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000011011101110000001101000100110011110111011111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~0_combout\); + +-- Location: LABCELL_X47_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux257~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux257~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~2_combout\); + +-- Location: FF_X47_Y14_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(28)); + +-- Location: MLABCELL_X45_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8689\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8689_BDD8690\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8689_BDD8690\); + +-- Location: MLABCELL_X45_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8687\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8687_BDD8688\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100000011000111011100111111010001000011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8687_BDD8688\); + +-- Location: MLABCELL_X45_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8691\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8691_BDD8692\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8687_BDD8688\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8689_BDD8690\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8687_BDD8688\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8689_BDD8690\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8689_BDD8690\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8687_BDD8688\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8691_BDD8692\); + +-- Location: LABCELL_X35_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8691_BDD8692\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8691_BDD8692\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8691_BDD8692\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8691_BDD8692\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001111101110110000111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8691_BDD8692\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_combout\); + +-- Location: LABCELL_X35_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[28]_NEW3255\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[28]_OTERM3256\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111100001111111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[28]_OTERM3256\); + +-- Location: FF_X35_Y27_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[28]_OTERM3256\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28)); + +-- Location: LABCELL_X39_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[28]~feeder_combout\); + +-- Location: FF_X39_Y14_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(28)); + +-- Location: LABCELL_X41_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[28]~feeder_combout\); + +-- Location: FF_X41_Y12_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(28)); + +-- Location: LABCELL_X39_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[28]~feeder_combout\); + +-- Location: FF_X39_Y14_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(28)); + +-- Location: FF_X41_Y12_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(28)); + +-- Location: LABCELL_X41_Y12_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(28)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(28) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(28) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(28))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(28))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(28), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~1_combout\); + +-- Location: FF_X47_Y13_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(28)); + +-- Location: FF_X47_Y13_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(28)); + +-- Location: LABCELL_X48_Y13_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[28]~feeder_combout\); + +-- Location: FF_X48_Y13_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(28)); + +-- Location: FF_X48_Y13_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(28)); + +-- Location: LABCELL_X48_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(28)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(28)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(28)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(28) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(28), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~0_combout\); + +-- Location: LABCELL_X47_Y14_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux65~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux65~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~2_combout\); + +-- Location: FF_X47_Y14_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(28)); + +-- Location: MLABCELL_X45_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~0_combout\); + +-- Location: MLABCELL_X45_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101010001101000011111000100001011010110111010101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~1_combout\); + +-- Location: LABCELL_X43_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~4_combout\); + +-- Location: LABCELL_X43_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~6_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~14_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~4_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~12_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~3_combout\); + +-- Location: LABCELL_X43_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~7_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~15_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~5_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~13_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~5_combout\); + +-- Location: MLABCELL_X42_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~2_combout\); + +-- Location: LABCELL_X44_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~3_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~5_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0101110101111111010111010101110101011101011111110111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~5_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~7_combout\); + +-- Location: MLABCELL_X45_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13054\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001101111011111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\); + +-- Location: LABCELL_X43_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13056\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110111011101101000100010001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\); + +-- Location: LABCELL_X43_Y30_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_OTERM2379\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_OTERM2379\); + +-- Location: FF_X43_Y30_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_OTERM2379\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28)); + +-- Location: FF_X44_Y25_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(28)); + +-- Location: FF_X44_Y25_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(28)); + +-- Location: FF_X41_Y25_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(28)); + +-- Location: FF_X44_Y25_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(28)); + +-- Location: LABCELL_X44_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(28)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(28) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(28) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(28)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(28)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(28), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~1_combout\); + +-- Location: FF_X41_Y21_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(28)); + +-- Location: LABCELL_X43_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[28]~feeder_combout\); + +-- Location: FF_X43_Y16_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(28)); + +-- Location: FF_X47_Y14_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(28)); + +-- Location: FF_X47_Y14_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(28)); + +-- Location: LABCELL_X47_Y14_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(28) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(28))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(28)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(28))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(28) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(28) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(28)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(28) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(28) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(28) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000010001001111110001000100001100110111010011111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~0_combout\); + +-- Location: LABCELL_X47_Y14_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux193~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux193~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~2_combout\); + +-- Location: FF_X47_Y14_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(28)); + +-- Location: LABCELL_X47_Y14_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(28) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(28) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(28) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(28) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(28), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(28), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~0_combout\); + +-- Location: LABCELL_X50_Y11_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector80~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]~67_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]~65_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]~60_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~1_combout\); + +-- Location: FF_X50_Y11_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_NEW_REG1087\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1088\); + +-- Location: FF_X45_Y11_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_NEW_REG1085\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1086\); + +-- Location: MLABCELL_X45_Y11_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1086\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1088\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1086\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1088\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1086\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]_OTERM1088\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]_OTERM1086\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\); + +-- Location: LABCELL_X39_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~2_combout\); + +-- Location: LABCELL_X39_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~1_combout\); + +-- Location: LABCELL_X39_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~3_combout\); + +-- Location: LABCELL_X39_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\); + +-- Location: LABCELL_X39_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~2_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~4_combout\); + +-- Location: LABCELL_X40_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0_combout\); + +-- Location: LABCELL_X40_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~8_combout\); + +-- Location: LABCELL_X40_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\); + +-- Location: LABCELL_X43_Y33_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\); + +-- Location: MLABCELL_X45_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~6_combout\); + +-- Location: LABCELL_X41_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6_combout\); + +-- Location: LABCELL_X40_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~10_combout\); + +-- Location: MLABCELL_X42_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\); + +-- Location: LABCELL_X39_Y28_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\); + +-- Location: MLABCELL_X45_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~10_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~8_combout\); + +-- Location: LABCELL_X41_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1_combout\); + +-- Location: LABCELL_X41_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~9_combout\); + +-- Location: MLABCELL_X42_Y30_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5_combout\); + +-- Location: MLABCELL_X42_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000000000000000000000111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\); + +-- Location: MLABCELL_X45_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~9_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~5_combout\); + +-- Location: LABCELL_X41_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3_combout\); + +-- Location: LABCELL_X41_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~11_combout\); + +-- Location: MLABCELL_X42_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7_combout\); + +-- Location: MLABCELL_X42_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\); + +-- Location: MLABCELL_X45_Y30_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~11_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~7_combout\); + +-- Location: MLABCELL_X45_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13074\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~5_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111001100110000000001010101000011110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\); + +-- Location: MLABCELL_X45_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13076\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110111000001010000010110001100101111111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\); + +-- Location: LABCELL_X47_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_OTERM2393\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000101111111110111010100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_OTERM2393\); + +-- Location: FF_X47_Y27_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_OTERM2393\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29)); + +-- Location: FF_X49_Y20_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(29)); + +-- Location: LABCELL_X47_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[29]~feeder_combout\); + +-- Location: FF_X47_Y20_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(29)); + +-- Location: FF_X49_Y20_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(29)); + +-- Location: FF_X49_Y24_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(29)); + +-- Location: MLABCELL_X49_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(29) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(29))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(29))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(29))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(29) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(29))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(29) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(29)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(29))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001000110000100110101011110001010110011101001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(29), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~1_combout\); + +-- Location: LABCELL_X47_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[29]~feeder_combout\); + +-- Location: FF_X47_Y20_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(29)); + +-- Location: LABCELL_X52_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[29]~feeder_combout\); + +-- Location: FF_X52_Y20_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(29)); + +-- Location: LABCELL_X52_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[29]~feeder_combout\); + +-- Location: FF_X52_Y20_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(29)); + +-- Location: FF_X52_Y20_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(29)); + +-- Location: LABCELL_X52_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(29))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(29))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(29)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(29) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(29)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(29), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(29), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~0_combout\); + +-- Location: LABCELL_X50_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux256~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux256~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~2_combout\); + +-- Location: FF_X50_Y15_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(29)); + +-- Location: LABCELL_X39_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1481~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1481~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1481~0_combout\); + +-- Location: LABCELL_X35_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13070\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13070_BDD13071\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1481~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1481~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000001001000110000110111101111110011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[13]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1481~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13070_BDD13071\); + +-- Location: MLABCELL_X34_Y35_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13072\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13070_BDD13071\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13070_BDD13071\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[29]_NEW2388_RESYN13070_BDD13071\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\); + +-- Location: MLABCELL_X34_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_OTERM2389\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101110101001010101000101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_OTERM2389\); + +-- Location: FF_X34_Y35_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_OTERM2389\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29)); + +-- Location: MLABCELL_X42_Y12_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[29]~feeder_combout\); + +-- Location: FF_X42_Y12_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(29)); + +-- Location: FF_X41_Y12_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(29)); + +-- Location: LABCELL_X47_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[29]~feeder_combout\); + +-- Location: FF_X47_Y13_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(29)); + +-- Location: FF_X42_Y12_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(29)); + +-- Location: MLABCELL_X42_Y12_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(29)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(29) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(29)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(29))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(29))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(29), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(29), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~1_combout\); + +-- Location: LABCELL_X47_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[29]~feeder_combout\); + +-- Location: FF_X47_Y13_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(29)); + +-- Location: FF_X52_Y13_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(29)); + +-- Location: LABCELL_X47_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[29]~feeder_combout\); + +-- Location: FF_X47_Y13_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(29)); + +-- Location: FF_X49_Y13_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(29)); + +-- Location: MLABCELL_X49_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(29)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(29)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(29)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(29) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(29)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010010101011111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(29), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~0_combout\); + +-- Location: MLABCELL_X49_Y13_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux128~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux128~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~2_combout\); + +-- Location: FF_X49_Y13_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(29)); + +-- Location: LABCELL_X39_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~1_combout\); + +-- Location: LABCELL_X39_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~0_combout\); + +-- Location: LABCELL_X39_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~3_combout\); + +-- Location: LABCELL_X39_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~3_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~1_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~0_combout\); + +-- Location: LABCELL_X32_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & +-- ((((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ & ((((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0010001001110111001000100111011100001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1417~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~1_combout\); + +-- Location: LABCELL_X32_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]_NEW3257\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]_OTERM3258\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(29))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~1_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(29))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1417~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]_OTERM3258\); + +-- Location: FF_X32_Y27_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]_OTERM3258\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(29)); + +-- Location: LABCELL_X47_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[29]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(29) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[29]~feeder_combout\); + +-- Location: FF_X47_Y15_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(29)); + +-- Location: LABCELL_X47_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[29]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(29) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[29]~feeder_combout\); + +-- Location: FF_X47_Y15_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(29)); + +-- Location: FF_X47_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(29)); + +-- Location: FF_X43_Y15_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(29)); + +-- Location: LABCELL_X47_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(29) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(29)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(29))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(29) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(29) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(29) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(29))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(29) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(29) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(29) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010000000000110101111111110011010100001111001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(29), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~1_combout\); + +-- Location: LABCELL_X53_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[29]~feeder_combout\); + +-- Location: FF_X53_Y16_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(29)); + +-- Location: FF_X49_Y13_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(29)); + +-- Location: MLABCELL_X42_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[29]~feeder_combout\); + +-- Location: FF_X42_Y12_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(29)); + +-- Location: FF_X49_Y13_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(29)); + +-- Location: MLABCELL_X49_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(29)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(29)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(29)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(29) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(29) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(29), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~0_combout\); + +-- Location: LABCELL_X50_Y15_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux64~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux64~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~2_combout\); + +-- Location: FF_X50_Y15_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(29)); + +-- Location: LABCELL_X39_Y28_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~2_combout\); + +-- Location: LABCELL_X39_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~4_combout\); + +-- Location: MLABCELL_X45_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~10_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~10_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~6_combout\); + +-- Location: MLABCELL_X45_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~9_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~8_combout\); + +-- Location: MLABCELL_X45_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~8_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~5_combout\); + +-- Location: MLABCELL_X45_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~11_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~11_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~9_combout\); + +-- Location: LABCELL_X47_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12576\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~6_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~6_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011100110100001101110000010011000111111101001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\); + +-- Location: LABCELL_X44_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12578\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~4_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~4_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~4_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111001000100010011111111111000011110111011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\); + +-- Location: LABCELL_X44_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_OTERM2391\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000001101110111111101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_OTERM2391\); + +-- Location: FF_X44_Y29_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_OTERM2391\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29)); + +-- Location: MLABCELL_X49_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[29]~feeder_combout\); + +-- Location: FF_X49_Y20_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(29)); + +-- Location: FF_X49_Y18_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(29)); + +-- Location: FF_X49_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(29)); + +-- Location: MLABCELL_X37_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[29]~feeder_combout\); + +-- Location: FF_X37_Y18_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(29)); + +-- Location: MLABCELL_X49_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(29) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(29))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(29)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(29))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(29) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(29) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(29) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(29)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(29) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(29) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(29) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110000000001010011111111110101001100001111010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(29), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~1_combout\); + +-- Location: FF_X50_Y17_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(29)); + +-- Location: MLABCELL_X49_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[29]~feeder_combout\); + +-- Location: FF_X49_Y20_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(29)); + +-- Location: FF_X50_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(29)); + +-- Location: FF_X50_Y18_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(29)); + +-- Location: LABCELL_X50_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(29)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(29) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(29) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(29)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(29)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(29), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~0_combout\); + +-- Location: LABCELL_X44_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux192~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux192~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~2_combout\); + +-- Location: FF_X44_Y18_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(29)); + +-- Location: LABCELL_X50_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(29) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(29)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(29)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(29))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(29)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(29))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000011000000110000010001110111010011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(29), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(29), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~0_combout\); + +-- Location: MLABCELL_X45_Y11_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000111001101110000010011110100110001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]~59_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]~63_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]~64_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector79~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~1_combout\); + +-- Location: FF_X45_Y11_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_NEW_REG1091\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1092\); + +-- Location: MLABCELL_X45_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1092\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1090\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1092\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1090\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110011000000001111001100001100111111110000110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]_OTERM1090\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]_OTERM1092\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\); + +-- Location: MLABCELL_X45_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111001100110101010111111111000011110011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector78~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]~62_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]~57_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]~61_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~1_combout\); + +-- Location: FF_X45_Y11_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_NEW_REG1071\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1072\); + +-- Location: FF_X45_Y11_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_NEW_REG1069\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1070\); + +-- Location: MLABCELL_X45_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1070\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1072\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1070\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1072\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1070\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]_OTERM1072\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]_OTERM1070\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\); + +-- Location: LABCELL_X35_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[31]_NEW2382\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[31]_OTERM2383\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010001111111110001000100000000110100011111111111010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[62]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[31]_OTERM2383\); + +-- Location: FF_X35_Y23_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[31]_OTERM2383\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31)); + +-- Location: LABCELL_X41_Y12_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[31]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[31]~feeder_combout\); + +-- Location: FF_X41_Y12_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(31)); + +-- Location: LABCELL_X47_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[31]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[31]~feeder_combout\); + +-- Location: FF_X47_Y13_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(31)); + +-- Location: LABCELL_X41_Y12_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[31]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[31]~feeder_combout\); + +-- Location: FF_X41_Y12_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(31)); + +-- Location: FF_X41_Y13_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(31)); + +-- Location: LABCELL_X41_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(31)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(31) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(31) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(31))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(31)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(31))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(31)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(31), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(31), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~1_combout\); + +-- Location: LABCELL_X47_Y13_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[31]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[31]~feeder_combout\); + +-- Location: FF_X47_Y13_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(31)); + +-- Location: LABCELL_X41_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[31]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[31]~feeder_combout\); + +-- Location: FF_X41_Y14_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(31)); + +-- Location: FF_X41_Y14_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(31)); + +-- Location: LABCELL_X47_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[31]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[31]~feeder_combout\); + +-- Location: FF_X47_Y13_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(31)); + +-- Location: LABCELL_X41_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(31) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(31))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(31))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(31) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(31))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(31)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(31) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(31))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(31)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(31) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(31) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(31))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(31)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000011000100011100111111011101000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(31), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~0_combout\); + +-- Location: LABCELL_X41_Y13_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux126~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux126~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~2_combout\); + +-- Location: FF_X41_Y13_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(31)); + +-- Location: LABCELL_X32_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010000010100000101000001010011010100000101001101010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1415~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~1_combout\); + +-- Location: FF_X32_Y26_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_NEW_REG668\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM669\); + +-- Location: FF_X32_Y26_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471~DUPLICATE_q\); + +-- Location: FF_X32_Y26_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_NEW_REG666\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM667\); + +-- Location: FF_X31_Y26_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_NEW_REG664\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM665\); + +-- Location: LABCELL_X32_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM667\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM665\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM669\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM667\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM665\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM669\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM667\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM665\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM669\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM667\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM665\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM669\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000001111010100110011001101110011001111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM669\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM471~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM667\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM665\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\); + +-- Location: FF_X39_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(31)); + +-- Location: LABCELL_X39_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[31]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1415~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[31]~feeder_combout\); + +-- Location: FF_X39_Y11_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(31)); + +-- Location: LABCELL_X39_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[31]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1415~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[31]~feeder_combout\); + +-- Location: FF_X39_Y11_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(31)); + +-- Location: FF_X39_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(31)); + +-- Location: LABCELL_X39_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(31)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(31) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(31) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(31))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(31))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(31), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(31), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~0_combout\); + +-- Location: LABCELL_X39_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[31]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1415~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[31]~feeder_combout\); + +-- Location: FF_X39_Y11_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(31)); + +-- Location: FF_X40_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(31)); + +-- Location: FF_X40_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(31)); + +-- Location: FF_X40_Y15_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(31)); + +-- Location: LABCELL_X40_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(31) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(31))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(31))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(31) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(31))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(31)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(31) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(31))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(31)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(31) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(31))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(31)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000101010001001010010111101110000011110100111010101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(31), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(31), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~1_combout\); + +-- Location: LABCELL_X39_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111111111001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux62~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux62~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~2_combout\); + +-- Location: FF_X39_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(31)); + +-- Location: LABCELL_X39_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(31))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(31), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~0_combout\); + +-- Location: LABCELL_X50_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100111111000001010011000011110101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]~65_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]~66_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]~51_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector77~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~1_combout\); + +-- Location: FF_X50_Y11_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_NEW_REG867\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM868\); + +-- Location: LABCELL_X50_Y11_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM868\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM866\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM868\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM866\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101111000000001010111101010000111111110101000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]_OTERM866\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]_OTERM868\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\); + +-- Location: LABCELL_X32_Y19_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal148~5_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal148~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101011110000111110101111000011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~1_combout\); + +-- Location: LABCELL_X29_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\)))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010001010000000001010101000000000100010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\); + +-- Location: LABCELL_X29_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[0]_NEW1954\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[0]_OTERM1955\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010000010100000101000001010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[0]_OTERM1955\); + +-- Location: FF_X29_Y19_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[0]_OTERM1955\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0)); + +-- Location: FF_X49_Y16_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(0)); + +-- Location: FF_X48_Y15_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(0)); + +-- Location: FF_X49_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(0)); + +-- Location: FF_X49_Y18_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(0)); + +-- Location: MLABCELL_X49_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~1_combout\); + +-- Location: FF_X49_Y12_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(0)); + +-- Location: FF_X49_Y12_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(0)); + +-- Location: FF_X49_Y14_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(0)); + +-- Location: FF_X49_Y12_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(0)); + +-- Location: MLABCELL_X49_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010010111110101111100100010011101110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~0_combout\); + +-- Location: LABCELL_X47_Y12_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux323~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux323~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~2_combout\); + +-- Location: FF_X47_Y12_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(0)); + +-- Location: MLABCELL_X45_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~45\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(0)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000010101010101010100110011111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]~59_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]~60_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~45_combout\); + +-- Location: LABCELL_X36_Y11_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~45_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~47_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~45_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~47_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~45_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~47_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~45_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~47_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000000000000011100110000000011001100100011001111111110001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~47_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]~58_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~45_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~48_combout\); + +-- Location: LABCELL_X36_Y11_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~49\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~48_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(32)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~48_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(32) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~31_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(32), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~48_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~49_combout\); + +-- Location: FF_X36_Y11_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~49_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(32)); + +-- Location: LABCELL_X29_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[1]_NEW1948\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[1]_OTERM1949\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000110011000000000011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[1]_OTERM1949\); + +-- Location: FF_X29_Y19_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[1]_OTERM1949\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1)); + +-- Location: LABCELL_X43_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[1]~feeder_combout\); + +-- Location: FF_X43_Y13_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(1)); + +-- Location: FF_X44_Y13_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(1)); + +-- Location: FF_X44_Y13_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(1)); + +-- Location: FF_X44_Y13_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(1)); + +-- Location: LABCELL_X44_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(1)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~1_combout\); + +-- Location: LABCELL_X40_Y13_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[1]~feeder_combout\); + +-- Location: FF_X40_Y13_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(1)); + +-- Location: LABCELL_X40_Y13_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[1]~feeder_combout\); + +-- Location: FF_X40_Y13_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(1)); + +-- Location: FF_X48_Y13_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(1)); + +-- Location: FF_X48_Y13_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(1)); + +-- Location: LABCELL_X48_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(1) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(1)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001111100110001000111001100110100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~0_combout\); + +-- Location: LABCELL_X48_Y13_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux322~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux322~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~2_combout\); + +-- Location: FF_X48_Y13_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(1)); + +-- Location: MLABCELL_X45_Y11_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~54\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(1)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]~63_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]~57_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~54_combout\); + +-- Location: LABCELL_X36_Y11_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~55\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~54_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(32))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~54_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(32)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001110001100101111111000110010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(32), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~54_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~55_combout\); + +-- Location: FF_X24_Y17_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[1]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[1]~65_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[1]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[1]_NEW2002\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[1]_OTERM2003\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[1]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[1]_OTERM2003\); + +-- Location: FF_X24_Y17_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[1]_OTERM2003\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1)); + +-- Location: FF_X25_Y11_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(1)); + +-- Location: FF_X24_Y11_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(1)); + +-- Location: FF_X24_Y11_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(1)); + +-- Location: FF_X24_Y11_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(1)); + +-- Location: LABCELL_X24_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(1)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~1_combout\); + +-- Location: FF_X26_Y11_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(1)); + +-- Location: FF_X25_Y11_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(1)); + +-- Location: FF_X25_Y11_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(1)); + +-- Location: FF_X26_Y11_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(1)); + +-- Location: LABCELL_X26_Y11_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(1))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~0_combout\); + +-- Location: LABCELL_X26_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux408~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux408~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~2_combout\); + +-- Location: FF_X26_Y11_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(1)); + +-- Location: LABCELL_X21_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[1]_NEW2004\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[1]_OTERM2005\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[1]_OTERM2005\); + +-- Location: FF_X21_Y17_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[1]_OTERM2005\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1)); + +-- Location: FF_X24_Y11_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(1)); + +-- Location: LABCELL_X25_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[1]~feeder_combout\); + +-- Location: FF_X25_Y11_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(1)); + +-- Location: FF_X24_Y11_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(1)); + +-- Location: FF_X24_Y11_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(1)); + +-- Location: LABCELL_X24_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(1)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~1_combout\); + +-- Location: LABCELL_X25_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[1]~feeder_combout\); + +-- Location: FF_X25_Y11_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(1)); + +-- Location: LABCELL_X25_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[1]~feeder_combout\); + +-- Location: FF_X25_Y11_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(1)); + +-- Location: FF_X26_Y11_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(1)); + +-- Location: FF_X26_Y11_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(1)); + +-- Location: LABCELL_X26_Y11_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(1)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(1)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(1)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101001001100011011110001100100111011010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~0_combout\); + +-- Location: LABCELL_X26_Y11_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux376~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux376~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~2_combout\); + +-- Location: FF_X26_Y11_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(1)); + +-- Location: LABCELL_X26_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011010101100001011101000010101000111111011010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~1_combout\); + +-- Location: FF_X26_Y37_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_NEW_REG460\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM461\); + +-- Location: LABCELL_X25_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux403~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux403~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101001000101010111101110111000001010111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux403~0_combout\); + +-- Location: FF_X25_Y32_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_NEW_REG456\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux403~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM457\); + +-- Location: MLABCELL_X34_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000001100110011001100110011001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1477~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~0_combout\); + +-- Location: FF_X34_Y22_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_NEW_REG458\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM459\); + +-- Location: MLABCELL_X34_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM457\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM459\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM457\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM459\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM457\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM459\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM461\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM449\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM457\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM459\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM449\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM461\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000000000110011001111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM449\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM461\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM457\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM459\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\); + +-- Location: FF_X40_Y20_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(33)); + +-- Location: FF_X40_Y22_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(33)); + +-- Location: FF_X40_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(33)); + +-- Location: FF_X43_Y20_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(33)); + +-- Location: LABCELL_X40_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(33) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(33)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(33)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(33) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(33) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(33))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(33) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(33) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(33))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(33)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(33) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(33)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(33))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101001100010011110111000001110011011111000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(33), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(33), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(33), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~0_combout\); + +-- Location: LABCELL_X41_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1477~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[33]~feeder_combout\); + +-- Location: FF_X41_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(33)); + +-- Location: MLABCELL_X42_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1477~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[33]~feeder_combout\); + +-- Location: FF_X42_Y20_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(33)); + +-- Location: FF_X41_Y20_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(33)); + +-- Location: MLABCELL_X42_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1477~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[33]~feeder_combout\); + +-- Location: FF_X42_Y22_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(33)); + +-- Location: LABCELL_X41_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(33) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(33))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(33))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(33) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(33) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(33))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(33)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(33) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(33) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(33))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(33)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(33) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(33) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(33))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(33)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010001000100101111101110111000010100111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(33), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(33), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(33), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~1_combout\); + +-- Location: LABCELL_X40_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux124~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux124~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~2_combout\); + +-- Location: FF_X40_Y20_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(33)); + +-- Location: LABCELL_X26_Y17_N24 +\myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_153\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_154\ = ( \myVirtualToplevel|MEM_DATA_READ[1]~64_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[1]~64_combout\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ & ( ((\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & \myVirtualToplevel|MEM_DATA_READ[1]~63_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) ) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[1]~64_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[1]~64_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ & ( +-- (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & \myVirtualToplevel|MEM_DATA_READ[1]~63_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001111111111111111100011111000111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~63_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~64_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]~35_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_154\); + +-- Location: FF_X26_Y17_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_154\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(1)); + +-- Location: LABCELL_X26_Y37_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~1_combout\); + +-- Location: LABCELL_X25_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011000000001111000001010011010100110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~0_combout\); + +-- Location: MLABCELL_X28_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000010000100110000111011011111110011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~2_combout\); + +-- Location: LABCELL_X32_Y21_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001101010011010100111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~3_combout\); + +-- Location: LABCELL_X31_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]_NEW2168\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]_OTERM2169\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~3_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(33) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]_OTERM2169\); + +-- Location: FF_X31_Y21_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]_OTERM2169\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(33)); + +-- Location: LABCELL_X31_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(33) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(33), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[33]~feeder_combout\); + +-- Location: FF_X31_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(33)); + +-- Location: FF_X31_Y17_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(33), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(33)); + +-- Location: FF_X31_Y21_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]_OTERM2169\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE_q\); + +-- Location: FF_X37_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(33)); + +-- Location: FF_X37_Y19_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(33)); + +-- Location: MLABCELL_X37_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(33)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(33) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(33) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(33))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(33)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(33))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(33)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(33), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(33), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(33), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~0_combout\); + +-- Location: FF_X37_Y19_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(33)); + +-- Location: FF_X39_Y19_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(33)); + +-- Location: FF_X39_Y19_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(33)); + +-- Location: MLABCELL_X34_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[33]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[33]~feeder_combout\); + +-- Location: FF_X34_Y21_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(33)); + +-- Location: LABCELL_X39_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(33) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(33))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(33))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(33) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(33) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(33)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(33) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(33) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(33) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(33))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(33) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(33))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(33)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001110011001101000111110011000100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(33), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(33), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(33), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~1_combout\); + +-- Location: LABCELL_X39_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux60~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux60~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~2_combout\); + +-- Location: FF_X39_Y19_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(33)); + +-- Location: MLABCELL_X37_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~3_combout\); + +-- Location: MLABCELL_X37_Y33_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~2_combout\); + +-- Location: MLABCELL_X37_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~0_combout\); + +-- Location: LABCELL_X35_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~1_combout\); + +-- Location: MLABCELL_X37_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13078\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\) +-- # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~2_combout\))))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011010001100101011110001010100110111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\); + +-- Location: MLABCELL_X37_Y36_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~8_combout\); + +-- Location: MLABCELL_X37_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~7_combout\); + +-- Location: MLABCELL_X37_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~6_combout\); + +-- Location: MLABCELL_X37_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~5_combout\); + +-- Location: MLABCELL_X37_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010000010100101111101110111011101110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~9_combout\); + +-- Location: LABCELL_X40_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13080\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~9_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100010000011010010111111010000111100101101110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(33), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\); + +-- Location: LABCELL_X40_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_OTERM2395\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011110111001111111100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_OTERM2395\); + +-- Location: FF_X40_Y27_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_OTERM2395\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33)); + +-- Location: FF_X45_Y15_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(33)); + +-- Location: FF_X45_Y15_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(33)); + +-- Location: FF_X45_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(33)); + +-- Location: MLABCELL_X45_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(33), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[33]~feeder_combout\); + +-- Location: FF_X45_Y17_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(33)); + +-- Location: MLABCELL_X45_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(33) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(33)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(33)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(33) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(33) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(33)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(33) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(33) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(33))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(33)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(33) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(33)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(33))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000010110000000101011011010100011010101110100001111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(33), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(33), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(33), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~1_combout\); + +-- Location: LABCELL_X48_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(33), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[33]~feeder_combout\); + +-- Location: FF_X48_Y18_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(33)); + +-- Location: FF_X53_Y16_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(33)); + +-- Location: FF_X48_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(33)); + +-- Location: LABCELL_X48_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(33), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[33]~feeder_combout\); + +-- Location: FF_X48_Y18_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(33)); + +-- Location: LABCELL_X48_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(33) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(33)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(33)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(33) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(33) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(33))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(33) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(33) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(33) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(33)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(33) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(33)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(33))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011101001100110001110111001100000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(33), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(33), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(33), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~0_combout\); + +-- Location: LABCELL_X44_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux252~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux252~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~2_combout\); + +-- Location: FF_X44_Y20_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(33)); + +-- Location: FF_X35_Y34_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_OTERM2537\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(33)); + +-- Location: LABCELL_X26_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001010010000001110101011110100010111100101010011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~1_combout\); + +-- Location: LABCELL_X25_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\)))) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010011111100000101001100001111010100111111111101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~0_combout\); + +-- Location: LABCELL_X26_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13326\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13326_BDD13327\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000011000100010000001111011101110011111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1535~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1535~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13326_BDD13327\); + +-- Location: LABCELL_X35_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13328\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(33) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13326_BDD13327\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(33) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13326_BDD13327\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110101000000001111010100001010111111110000101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]_NEW2536_RESYN13326_BDD13327\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(33), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\); + +-- Location: LABCELL_X35_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_OTERM2537\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(33) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_OTERM2537\); + +-- Location: FF_X35_Y34_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_OTERM2537\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE_q\); + +-- Location: MLABCELL_X45_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[33]~feeder_combout\); + +-- Location: FF_X45_Y22_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(33)); + +-- Location: MLABCELL_X45_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[33]~feeder_combout\); + +-- Location: FF_X45_Y22_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(33)); + +-- Location: LABCELL_X41_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[33]~feeder_combout\); + +-- Location: FF_X41_Y22_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(33)); + +-- Location: FF_X44_Y22_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(33)); + +-- Location: LABCELL_X44_Y22_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(33)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(33))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(33)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(33))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(33)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(33) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(33) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100111111111100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(33), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(33), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(33), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~0_combout\); + +-- Location: LABCELL_X43_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[33]~feeder_combout\); + +-- Location: FF_X43_Y22_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(33)); + +-- Location: LABCELL_X43_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[33]~feeder_combout\); + +-- Location: FF_X43_Y22_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(33)); + +-- Location: FF_X44_Y22_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(33)); + +-- Location: MLABCELL_X49_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[33]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[33]~feeder_combout\); + +-- Location: FF_X49_Y18_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[33]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(33)); + +-- Location: LABCELL_X44_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(33) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(33)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(33)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(33) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(33) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(33))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(33) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(33) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(33) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(33)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(33) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(33)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(33))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101010000111100110101111100000011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(33), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(33), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(33), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~1_combout\); + +-- Location: LABCELL_X44_Y22_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux188~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux188~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~2_combout\); + +-- Location: FF_X44_Y22_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(33)); + +-- Location: LABCELL_X40_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector75~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector75~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(33) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(33) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(33) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(33) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(33), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(33), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(33), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(33), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector75~0_combout\); + +-- Location: LABCELL_X36_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~52\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~52_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector75~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(1))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector75~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(1))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101000111000000110100011111001111010001111100111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector75~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~52_combout\); + +-- Location: LABCELL_X36_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~53\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~53_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~52_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000000000001000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~52_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_SP~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~53_combout\); + +-- Location: LABCELL_X36_Y11_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~56\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~53_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~53_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~55_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011110111000001001111011100001100111111110000110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~55_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~31_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~53_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~56_combout\); + +-- Location: FF_X36_Y11_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~56_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33)); + +-- Location: FF_X35_Y13_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]_OTERM1777\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(34)); + +-- Location: LABCELL_X39_Y11_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\); + +-- Location: LABCELL_X29_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[2]_NEW1950\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[2]_OTERM1951\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[2]_OTERM1951\); + +-- Location: FF_X29_Y19_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[2]_OTERM1951\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(2)); + +-- Location: LABCELL_X40_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[2]~feeder_combout\); + +-- Location: FF_X40_Y13_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(2)); + +-- Location: FF_X42_Y13_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(2)); + +-- Location: LABCELL_X40_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[2]~feeder_combout\); + +-- Location: FF_X40_Y13_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(2)); + +-- Location: FF_X42_Y13_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(2)); + +-- Location: MLABCELL_X42_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(2))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(2))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~0_combout\); + +-- Location: LABCELL_X35_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[2]~feeder_combout\); + +-- Location: FF_X35_Y15_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(2)); + +-- Location: FF_X43_Y13_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(2)); + +-- Location: FF_X43_Y13_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(2)); + +-- Location: FF_X35_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(2)); + +-- Location: LABCELL_X35_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(2))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(2))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~1_combout\); + +-- Location: LABCELL_X35_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux321~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux321~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~2_combout\); + +-- Location: FF_X35_Y15_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(2)); + +-- Location: MLABCELL_X34_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008_RESYN12816\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111101111000000011110111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\); + +-- Location: MLABCELL_X34_Y23_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_OTERM2009\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010100000001011110101111111011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_OTERM2009\); + +-- Location: FF_X34_Y23_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_OTERM2009\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2)); + +-- Location: LABCELL_X32_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[2]~feeder_combout\); + +-- Location: FF_X32_Y18_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(2)); + +-- Location: LABCELL_X32_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[2]~feeder_combout\); + +-- Location: FF_X32_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(2)); + +-- Location: FF_X35_Y12_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(2)); + +-- Location: FF_X32_Y18_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(2)); + +-- Location: LABCELL_X32_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(2)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~0_combout\); + +-- Location: FF_X35_Y19_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(2)); + +-- Location: FF_X35_Y15_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(2)); + +-- Location: MLABCELL_X37_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[2]~feeder_combout\); + +-- Location: FF_X37_Y17_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(2)); + +-- Location: FF_X35_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(2)); + +-- Location: LABCELL_X35_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(2))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(2))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~1_combout\); + +-- Location: LABCELL_X35_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux345~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux345~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~2_combout\); + +-- Location: FF_X35_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(2)); + +-- Location: MLABCELL_X23_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[2]_NEW2006\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[2]_OTERM2007\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(2))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(2))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[2]_OTERM2007\); + +-- Location: FF_X23_Y17_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[2]_OTERM2007\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2)); + +-- Location: LABCELL_X25_Y11_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[2]~feeder_combout\); + +-- Location: FF_X25_Y11_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(2)); + +-- Location: FF_X24_Y11_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(2)); + +-- Location: FF_X24_Y11_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(2)); + +-- Location: FF_X24_Y11_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(2)); + +-- Location: LABCELL_X24_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(2)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~1_combout\); + +-- Location: LABCELL_X25_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[2]~feeder_combout\); + +-- Location: FF_X25_Y11_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(2)); + +-- Location: FF_X26_Y13_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(2)); + +-- Location: FF_X26_Y11_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(2)); + +-- Location: FF_X26_Y11_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(2)); + +-- Location: LABCELL_X26_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(2))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(2))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~0_combout\); + +-- Location: LABCELL_X29_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux375~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux375~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~2_combout\); + +-- Location: FF_X29_Y11_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(2)); + +-- Location: MLABCELL_X23_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[2]_NEW2010\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[2]_OTERM2011\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(2) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(2)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[2]_OTERM2011\); + +-- Location: FF_X23_Y17_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[2]_OTERM2011\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(2)); + +-- Location: MLABCELL_X34_Y13_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[2]~feeder_combout\); + +-- Location: FF_X34_Y13_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(2)); + +-- Location: LABCELL_X35_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[2]~feeder_combout\); + +-- Location: FF_X35_Y11_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(2)); + +-- Location: LABCELL_X31_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[2]~feeder_combout\); + +-- Location: FF_X31_Y17_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(2)); + +-- Location: FF_X31_Y17_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(2)); + +-- Location: LABCELL_X35_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(2)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~0_combout\); + +-- Location: LABCELL_X35_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[2]~feeder_combout\); + +-- Location: FF_X35_Y18_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(2)); + +-- Location: LABCELL_X36_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[2]~feeder_combout\); + +-- Location: FF_X36_Y21_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(2)); + +-- Location: LABCELL_X36_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[2]~feeder_combout\); + +-- Location: FF_X36_Y21_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(2)); + +-- Location: FF_X36_Y21_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(2)); + +-- Location: LABCELL_X36_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(2)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~1_combout\); + +-- Location: LABCELL_X35_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux407~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux407~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~2_combout\); + +-- Location: FF_X35_Y15_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(2)); + +-- Location: LABCELL_X35_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000000000000000000011110000111100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_SP~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector42~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\); + +-- Location: LABCELL_X35_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~0_combout\); + +-- Location: LABCELL_X35_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~1_combout\); + +-- Location: LABCELL_X35_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~2_combout\); + +-- Location: LABCELL_X32_Y31_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~3_combout\); + +-- Location: LABCELL_X35_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13086\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~3_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\); + +-- Location: MLABCELL_X34_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~8_combout\); + +-- Location: MLABCELL_X34_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~5_combout\); + +-- Location: MLABCELL_X34_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~7_combout\); + +-- Location: MLABCELL_X34_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~6_combout\); + +-- Location: MLABCELL_X34_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~7_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~7_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111001100110000000001010101000011110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~9_combout\); + +-- Location: LABCELL_X35_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13088\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~9_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34) & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100010000011110010011111110000011100101111111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(34), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\); + +-- Location: LABCELL_X35_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_OTERM2401\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000001111101011111110100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(34), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_OTERM2401\); + +-- Location: FF_X35_Y34_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_OTERM2401\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34)); + +-- Location: FF_X40_Y19_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(34)); + +-- Location: FF_X43_Y22_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(34)); + +-- Location: FF_X43_Y22_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(34)); + +-- Location: FF_X43_Y22_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(34)); + +-- Location: LABCELL_X43_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(34)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(34) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(34) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(34) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(34))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(34) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(34))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(34), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(34), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(34), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(34), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~1_combout\); + +-- Location: FF_X40_Y19_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(34)); + +-- Location: FF_X45_Y19_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(34)); + +-- Location: FF_X45_Y19_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(34)); + +-- Location: FF_X45_Y19_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(34)); + +-- Location: MLABCELL_X45_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(34)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(34) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(34)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(34) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(34))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(34)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(34) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(34))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(34)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(34), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(34), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(34), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(34), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~0_combout\); + +-- Location: LABCELL_X44_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux251~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux251~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~2_combout\); + +-- Location: FF_X44_Y19_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(34)); + +-- Location: LABCELL_X35_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_RTM0716\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_RTM0716_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_RTM0716_combout\); + +-- Location: LABCELL_X32_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101110111000000000000000001010101011101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\); + +-- Location: FF_X35_Y25_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG714\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_RTM0716_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\); + +-- Location: FF_X32_Y27_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_NEW_REG1113\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1114\); + +-- Location: LABCELL_X35_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~2_combout\); + +-- Location: LABCELL_X35_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111001100110000000001010101000011110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~1_combout\); + +-- Location: MLABCELL_X18_Y15_N42 +\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_156\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_157\ = ( \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( +-- \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ ) ) # ( \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ & +-- \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[2]~36_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ & \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000011110011111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]~25_combout\, + datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~36_combout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~37_combout\, + combout => \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_157\); + +-- Location: FF_X18_Y15_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_157\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(2)); + +-- Location: LABCELL_X36_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(2))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001101010111010101110101011101010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~3_combout\); + +-- Location: LABCELL_X36_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~4_RTM01120\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~4_RTM01120_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~3_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~3_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100000001110000011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~4_RTM01120_combout\); + +-- Location: FF_X36_Y27_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_NEW_REG1118\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~4_RTM01120_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1119\); + +-- Location: FF_X35_Y25_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_NEW_REG1111\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1112\); + +-- Location: FF_X35_Y25_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG484\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\); + +-- Location: LABCELL_X39_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000110000001100000011000000000000001100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~38_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~0_combout\); + +-- Location: FF_X39_Y25_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_NEW_REG1115\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1116\); + +-- Location: LABCELL_X39_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1116\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1112\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1119\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1116\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1114\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1112\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1119\) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1116\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1114\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1112\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1119\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1116\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1114\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1112\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1119\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100111101011111010011111111111100001111000111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM715\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1114\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1119\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1112\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM485\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1116\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\); + +-- Location: LABCELL_X41_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[34]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[34]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[34]~feeder_combout\); + +-- Location: FF_X41_Y19_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[34]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(34)); + +-- Location: LABCELL_X41_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[34]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[34]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[34]~feeder_combout\); + +-- Location: FF_X41_Y19_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[34]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(34)); + +-- Location: FF_X42_Y18_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(34)); + +-- Location: FF_X41_Y19_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(34)); + +-- Location: LABCELL_X41_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(34)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(34) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(34)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(34) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(34))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(34) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(34))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(34), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(34), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(34), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(34), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~1_combout\); + +-- Location: FF_X42_Y16_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(34)); + +-- Location: FF_X42_Y15_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(34)); + +-- Location: FF_X42_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(34)); + +-- Location: FF_X44_Y15_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(34)); + +-- Location: MLABCELL_X42_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(34) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(34)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(34)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(34) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(34)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(34))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(34) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(34)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(34))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(34) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(34) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(34))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101001000110110011110001001110011011010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(34), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(34), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(34), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~0_combout\); + +-- Location: MLABCELL_X42_Y15_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux59~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux59~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~2_combout\); + +-- Location: FF_X42_Y15_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(34)); + +-- Location: FF_X37_Y23_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_OTERM2399\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(34)); + +-- Location: LABCELL_X35_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~0_combout\); + +-- Location: LABCELL_X35_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~1_combout\); + +-- Location: MLABCELL_X37_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13082\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~0_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1476~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1476~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\); + +-- Location: MLABCELL_X37_Y23_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13084\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(34) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(34) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111101011111010100001010000010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\); + +-- Location: MLABCELL_X37_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_OTERM2399\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(34) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(34), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_OTERM2399\); + +-- Location: FF_X37_Y23_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_OTERM2399\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[34]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[34]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[34]~feeder_combout\); + +-- Location: FF_X41_Y20_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[34]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(34)); + +-- Location: LABCELL_X40_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[34]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[34]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[34]~feeder_combout\); + +-- Location: FF_X40_Y19_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[34]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(34)); + +-- Location: FF_X41_Y20_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(34)); + +-- Location: MLABCELL_X42_Y19_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[34]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[34]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[34]~feeder_combout\); + +-- Location: FF_X42_Y19_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[34]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(34)); + +-- Location: LABCELL_X41_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(34) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(34))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(34))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(34) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(34))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(34)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(34) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(34))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(34)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(34) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(34))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(34)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010001000100101111101110111000010100111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(34), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(34), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(34), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~1_combout\); + +-- Location: FF_X42_Y15_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(34)); + +-- Location: LABCELL_X41_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[34]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[34]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[34]~feeder_combout\); + +-- Location: FF_X41_Y17_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[34]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(34)); + +-- Location: FF_X42_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(34)); + +-- Location: LABCELL_X41_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[34]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[34]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[34]~feeder_combout\); + +-- Location: FF_X41_Y20_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[34]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(34)); + +-- Location: MLABCELL_X42_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(34) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(34) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(34) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(34)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(34) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(34) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(34))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(34) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(34) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(34))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101011111000000110101000011110011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(34), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(34), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(34), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~0_combout\); + +-- Location: MLABCELL_X42_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux123~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux123~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~2_combout\); + +-- Location: FF_X42_Y15_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(34)); + +-- Location: LABCELL_X35_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111000000000011001101010101000011111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][2]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~0_combout\); + +-- Location: LABCELL_X35_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010010101011111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~1_combout\); + +-- Location: LABCELL_X35_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13330\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13330_BDD13331\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011000000000001101111111111000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1534~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1534~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13330_BDD13331\); + +-- Location: FF_X35_Y34_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_OTERM2540\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]~DUPLICATE_q\); + +-- Location: LABCELL_X35_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13332\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13330_BDD13331\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13330_BDD13331\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001111000000001100111100110000111111110011000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]_NEW2539_RESYN13330_BDD13331\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\); + +-- Location: LABCELL_X35_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_OTERM2540\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000001110111011111110100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(34), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_OTERM2540\); + +-- Location: FF_X35_Y34_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_OTERM2540\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34)); + +-- Location: LABCELL_X41_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[34]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[34]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[34]~feeder_combout\); + +-- Location: FF_X41_Y21_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[34]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(34)); + +-- Location: FF_X41_Y22_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(34)); + +-- Location: FF_X41_Y21_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(34)); + +-- Location: FF_X40_Y21_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(34)); + +-- Location: LABCELL_X41_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(34) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(34)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(34)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(34) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(34))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(34) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(34) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(34) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(34) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(34)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(34) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(34) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(34))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011010101010001101110101010000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(34), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(34), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(34), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~0_combout\); + +-- Location: LABCELL_X41_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[34]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[34]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[34]~feeder_combout\); + +-- Location: FF_X41_Y23_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[34]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(34)); + +-- Location: LABCELL_X41_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[34]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[34]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[34]~feeder_combout\); + +-- Location: FF_X41_Y23_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[34]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(34)); + +-- Location: FF_X41_Y23_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(34)); + +-- Location: LABCELL_X41_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[34]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[34]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[34]~feeder_combout\); + +-- Location: FF_X41_Y21_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[34]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(34)); + +-- Location: LABCELL_X41_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(34) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(34) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(34))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(34) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(34))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(34) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(34))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100000001111100011100110100111101000011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(34), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(34), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(34), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~1_combout\); + +-- Location: MLABCELL_X42_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111110011111100111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux187~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux187~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~2_combout\); + +-- Location: FF_X42_Y23_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(34)); + +-- Location: MLABCELL_X42_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(34) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(34) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(34) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(34))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(34) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(34))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(34) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(34) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(34))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100001111110100010000001100011101110011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(34), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(34), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(34), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(34), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~0_combout\); + +-- Location: LABCELL_X35_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(2))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010000010100101111101110111011101110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~1_combout\); + +-- Location: LABCELL_X35_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(2)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000100010001000100001010010111111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]~51_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]~61_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~2_combout\); + +-- Location: LABCELL_X35_Y13_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]_NEW1776\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]_OTERM1777\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(34))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(34))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(33), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(34), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]_OTERM1777\); + +-- Location: FF_X35_Y13_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]_OTERM1777\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[3]_NEW2000\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[3]_OTERM2001\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(3)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[3]_OTERM2001\); + +-- Location: FF_X24_Y17_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[3]_OTERM2001\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3)); + +-- Location: MLABCELL_X37_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[3]~feeder_combout\); + +-- Location: FF_X37_Y19_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(3)); + +-- Location: LABCELL_X36_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[3]~feeder_combout\); + +-- Location: FF_X36_Y21_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(3)); + +-- Location: LABCELL_X36_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[3]~feeder_combout\); + +-- Location: FF_X36_Y21_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(3)); + +-- Location: FF_X36_Y21_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(3)); + +-- Location: LABCELL_X36_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(3)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(3)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(3)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~1_combout\); + +-- Location: FF_X29_Y16_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(3)); + +-- Location: LABCELL_X29_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[3]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[3]~feeder_combout\); + +-- Location: FF_X29_Y16_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(3)); + +-- Location: FF_X29_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(3)); + +-- Location: FF_X29_Y17_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(3)); + +-- Location: LABCELL_X29_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(3))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(3)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(3) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000010001010111110001000100001010101110110101111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~0_combout\); + +-- Location: LABCELL_X31_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux406~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux406~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~2_combout\); + +-- Location: FF_X31_Y16_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(3)); + +-- Location: MLABCELL_X23_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[3]_NEW1996\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[3]_OTERM1997\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(3)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[3]_OTERM1997\); + +-- Location: FF_X23_Y17_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[3]_OTERM1997\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3)); + +-- Location: LABCELL_X29_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[3]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[3]~feeder_combout\); + +-- Location: FF_X29_Y14_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(3)); + +-- Location: FF_X31_Y14_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(3)); + +-- Location: LABCELL_X31_Y14_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[3]~feeder_combout\); + +-- Location: FF_X31_Y14_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(3)); + +-- Location: FF_X31_Y14_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(3)); + +-- Location: LABCELL_X31_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(3)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(3)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~0_combout\); + +-- Location: FF_X31_Y13_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(3)); + +-- Location: FF_X31_Y13_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(3)); + +-- Location: FF_X32_Y13_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(3)); + +-- Location: FF_X32_Y13_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(3)); + +-- Location: LABCELL_X32_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(3))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(3))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~1_combout\); + +-- Location: MLABCELL_X34_Y12_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux374~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux374~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~2_combout\); + +-- Location: FF_X34_Y12_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(3)); + +-- Location: MLABCELL_X34_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998_RESYN12814\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011111110000100001111111000110000111111000011000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\); + +-- Location: MLABCELL_X34_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_OTERM1999\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010100000001011110101111111011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_OTERM1999\); + +-- Location: FF_X34_Y23_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_OTERM1999\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3)); + +-- Location: FF_X32_Y14_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(3)); + +-- Location: MLABCELL_X34_Y14_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[3]~feeder_combout\); + +-- Location: FF_X34_Y14_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(3)); + +-- Location: MLABCELL_X34_Y14_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[3]~feeder_combout\); + +-- Location: FF_X34_Y14_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(3)); + +-- Location: FF_X34_Y14_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(3)); + +-- Location: MLABCELL_X34_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(3))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(3))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~1_combout\); + +-- Location: MLABCELL_X34_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[3]~feeder_combout\); + +-- Location: FF_X34_Y16_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(3)); + +-- Location: LABCELL_X32_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[3]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[3]~feeder_combout\); + +-- Location: FF_X32_Y18_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(3)); + +-- Location: LABCELL_X32_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[3]~feeder_combout\); + +-- Location: FF_X32_Y18_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(3)); + +-- Location: FF_X32_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(3)); + +-- Location: LABCELL_X32_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(3)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~0_combout\); + +-- Location: MLABCELL_X34_Y12_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux344~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux344~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~2_combout\); + +-- Location: FF_X34_Y12_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(3)); + +-- Location: MLABCELL_X23_Y35_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~1_combout\); + +-- Location: LABCELL_X32_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001111110101000000110000010111110011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~0_combout\); + +-- Location: MLABCELL_X34_Y34_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13334\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011000000100001001111001110110111111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1533~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1533~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\); + +-- Location: MLABCELL_X34_Y34_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13336\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111101011111010100001010000010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(35), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\); + +-- Location: MLABCELL_X34_Y34_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_OTERM2543\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(35), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_OTERM2543\); + +-- Location: FF_X34_Y34_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_OTERM2543\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35)); + +-- Location: FF_X45_Y26_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(35)); + +-- Location: LABCELL_X53_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[35]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[35]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(35), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[35]~feeder_combout\); + +-- Location: FF_X53_Y28_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[35]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(35)); + +-- Location: FF_X45_Y26_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(35)); + +-- Location: FF_X45_Y26_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(35)); + +-- Location: MLABCELL_X45_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(35)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(35) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(35) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(35) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(35)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(35))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(35) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(35)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(35))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(35), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(35), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(35), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(35), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~0_combout\); + +-- Location: LABCELL_X52_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[35]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[35]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(35), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[35]~feeder_combout\); + +-- Location: FF_X52_Y27_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[35]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(35)); + +-- Location: FF_X48_Y27_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(35)); + +-- Location: LABCELL_X52_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[35]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[35]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(35), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[35]~feeder_combout\); + +-- Location: FF_X52_Y27_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[35]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(35)); + +-- Location: FF_X48_Y27_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(35)); + +-- Location: LABCELL_X48_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(35)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(35) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(35) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(35) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(35))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(35)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(35) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(35))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(35)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(35), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(35), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(35), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(35), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~1_combout\); + +-- Location: LABCELL_X48_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux186~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux186~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~2_combout\); + +-- Location: FF_X48_Y27_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(35)); + +-- Location: LABCELL_X31_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\)))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100001100000011000000110100001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\); + +-- Location: FF_X29_Y27_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG102\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM103\); + +-- Location: LABCELL_X32_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~0_combout\); + +-- Location: MLABCELL_X23_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~3_combout\); + +-- Location: LABCELL_X36_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001110100011101110100011101000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~4_combout\); + +-- Location: MLABCELL_X37_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110000001100110011000000110000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\); + +-- Location: MLABCELL_X37_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~4_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~4_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~4_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000000001100000011000000110000001100000011000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~1_combout\); + +-- Location: FF_X37_Y27_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG110\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM111\); + +-- Location: FF_X31_Y28_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\); + +-- Location: LABCELL_X19_Y13_N42 +\myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_159\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_160\ = ( !\myVirtualToplevel|MEM_DATA_READ[3]~92_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3~portbdataout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((\myVirtualToplevel|IO_DATA_READ_SD\(3))))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\)))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[3]~92_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) # ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11~portbdataout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ +-- & (((\myVirtualToplevel|IO_DATA_READ_SD\(3))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001001000110100010101100111000010011010101111001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(3), + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~92_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]~24_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_160\); + +-- Location: FF_X19_Y13_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_160\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(3)); + +-- Location: FF_X31_Y27_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG108\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM109\); + +-- Location: FF_X31_Y28_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG106\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\); + +-- Location: LABCELL_X41_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM109\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM109\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM111\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM109\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ +-- & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM103\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM111\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM109\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM103\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM111\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101110111001100110111011100110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM103\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM111\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM109\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM107\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\); + +-- Location: FF_X41_Y25_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(35)); + +-- Location: FF_X41_Y25_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(35)); + +-- Location: FF_X41_Y21_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(35)); + +-- Location: FF_X41_Y25_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(35)); + +-- Location: LABCELL_X41_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(35)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(35) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(35)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(35) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(35)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(35))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(35) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(35)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(35))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(35), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(35), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(35), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(35), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~1_combout\); + +-- Location: FF_X41_Y21_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(35)); + +-- Location: LABCELL_X43_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[35]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[35]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[35]~feeder_combout\); + +-- Location: FF_X43_Y21_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[35]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(35)); + +-- Location: FF_X41_Y21_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(35)); + +-- Location: LABCELL_X43_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[35]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[35]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[35]~feeder_combout\); + +-- Location: FF_X43_Y21_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[35]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(35)); + +-- Location: LABCELL_X41_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(35) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(35)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(35)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(35) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(35) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(35))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(35) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(35) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(35) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(35))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(35)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(35) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(35) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(35)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(35))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001011010100010101101110100001101010111111000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(35), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(35), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(35), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(35), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~0_combout\); + +-- Location: LABCELL_X40_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000000000000001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux58~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux58~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~2_combout\); + +-- Location: FF_X40_Y21_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(35)); + +-- Location: FF_X34_Y33_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_OTERM2387\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(35)); + +-- Location: MLABCELL_X28_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~8_combout\); + +-- Location: LABCELL_X31_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~6_combout\); + +-- Location: LABCELL_X29_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~7_combout\); + +-- Location: LABCELL_X31_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~5_combout\); + +-- Location: MLABCELL_X34_Y33_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~6_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~5_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~6_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~6_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101001000101010111101110111000001010111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~9_combout\); + +-- Location: LABCELL_X32_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~3_combout\); + +-- Location: LABCELL_X32_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~2_combout\); + +-- Location: LABCELL_X32_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~1_combout\); + +-- Location: LABCELL_X35_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~0_combout\); + +-- Location: LABCELL_X35_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13066\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~2_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000111101000101010011101010010010101111111001011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\); + +-- Location: MLABCELL_X34_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13068\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(35))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(35))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~9_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~9_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100010100000101110000110011111111110101001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(35), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\); + +-- Location: MLABCELL_X34_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_OTERM2387\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(35) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(35) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001101111111011101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(35), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_OTERM2387\); + +-- Location: FF_X34_Y33_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_OTERM2387\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE_q\); + +-- Location: MLABCELL_X45_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[35]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[35]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[35]~feeder_combout\); + +-- Location: FF_X45_Y22_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[35]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(35)); + +-- Location: LABCELL_X44_Y22_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[35]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[35]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[35]~feeder_combout\); + +-- Location: FF_X44_Y22_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[35]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(35)); + +-- Location: FF_X45_Y22_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(35)); + +-- Location: MLABCELL_X45_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[35]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[35]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[35]~feeder_combout\); + +-- Location: FF_X45_Y22_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[35]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(35)); + +-- Location: MLABCELL_X45_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(35) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(35)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(35)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(35) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(35) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(35)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(35))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(35) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(35) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(35)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(35))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(35) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(35) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(35)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(35))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100110001000011010011110111000001111100011100110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(35), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(35), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(35), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(35), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~0_combout\); + +-- Location: LABCELL_X47_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[35]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[35]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[35]~feeder_combout\); + +-- Location: FF_X47_Y22_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[35]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(35)); + +-- Location: FF_X43_Y22_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(35)); + +-- Location: FF_X43_Y22_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(35)); + +-- Location: FF_X43_Y22_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(35)); + +-- Location: LABCELL_X43_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(35) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(35)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(35)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(35) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(35) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(35)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(35))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(35) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(35) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(35)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(35))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(35) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(35) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(35)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(35))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000100111001101101000110110011100101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(35), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(35), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(35), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(35), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~1_combout\); + +-- Location: LABCELL_X44_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux250~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux250~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~2_combout\); + +-- Location: FF_X44_Y22_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(35)); + +-- Location: FF_X37_Y23_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_OTERM2385\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(35)); + +-- Location: LABCELL_X32_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~1_combout\); + +-- Location: MLABCELL_X23_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~0_combout\); + +-- Location: MLABCELL_X34_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13062\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13062_BDD13063\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~1_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111110011000100011100110011010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1475~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1475~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13062_BDD13063\); + +-- Location: MLABCELL_X37_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13064\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(35) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13062_BDD13063\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(35) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13062_BDD13063\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100101111001011110010111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]_NEW2384_RESYN13062_BDD13063\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(35), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\); + +-- Location: MLABCELL_X37_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_OTERM2385\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(35) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(35), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_OTERM2385\); + +-- Location: FF_X37_Y23_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_OTERM2385\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[35]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[35]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[35]~feeder_combout\); + +-- Location: FF_X41_Y17_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[35]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(35)); + +-- Location: FF_X41_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(35)); + +-- Location: FF_X41_Y17_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(35)); + +-- Location: LABCELL_X41_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[35]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[35]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[35]~feeder_combout\); + +-- Location: FF_X41_Y17_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[35]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(35)); + +-- Location: LABCELL_X41_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(35) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(35)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(35)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(35) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(35) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(35)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(35))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(35) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(35) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(35)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(35))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(35) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(35) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(35)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(35))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100010001000001011011101110101111000100011010111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(35), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(35), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(35), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(35), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~0_combout\); + +-- Location: FF_X40_Y18_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(35)); + +-- Location: FF_X42_Y18_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(35)); + +-- Location: FF_X43_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(35)); + +-- Location: FF_X43_Y18_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(35)); + +-- Location: LABCELL_X43_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(35) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(35))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(35)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(35) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(35))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(35) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(35) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(35) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(35))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(35)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(35) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(35) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(35))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(35) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011100000100110001111111010000110111001101001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(35), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(35), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(35), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(35), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~1_combout\); + +-- Location: MLABCELL_X42_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux122~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux122~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~2_combout\); + +-- Location: FF_X42_Y21_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(35)); + +-- Location: MLABCELL_X42_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(35) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(35) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(35) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(35) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(35), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(35), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(35), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(35), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~0_combout\); + +-- Location: MLABCELL_X34_Y12_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(3)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(3)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(3))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(3)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(3))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(3) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(3))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000101111100110000010100000011111101011111001111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~1_combout\); + +-- Location: LABCELL_X31_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[3]_NEW1952\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[3]_OTERM1953\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[3]_OTERM1953\); + +-- Location: FF_X31_Y19_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[3]_OTERM1953\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3)); + +-- Location: MLABCELL_X42_Y12_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[3]~feeder_combout\); + +-- Location: FF_X42_Y12_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(3)); + +-- Location: FF_X37_Y12_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(3)); + +-- Location: FF_X37_Y12_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(3)); + +-- Location: FF_X42_Y12_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(3)); + +-- Location: MLABCELL_X42_Y12_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(3)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(3))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(3))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~1_combout\); + +-- Location: FF_X42_Y13_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(3)); + +-- Location: FF_X41_Y13_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(3)); + +-- Location: FF_X42_Y13_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(3)); + +-- Location: FF_X42_Y13_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(3)); + +-- Location: MLABCELL_X42_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(3)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(3) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(3)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(3))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011101001100110001110111001100000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~0_combout\); + +-- Location: MLABCELL_X34_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux320~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux320~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~2_combout\); + +-- Location: FF_X34_Y12_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(3)); + +-- Location: MLABCELL_X34_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(3) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100000000000111011100110000011101001100110001110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]~65_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]~58_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~2_combout\); + +-- Location: MLABCELL_X34_Y12_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[35]_NEW1774\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[35]_OTERM1775\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~2_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101111100001111010100001111000001011111111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[34]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(35), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[35]_OTERM1775\); + +-- Location: FF_X34_Y12_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[35]_OTERM1775\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35)); + +-- Location: LABCELL_X31_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[4]_NEW1964\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[4]_OTERM1965\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(4) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[4]_OTERM1965\); + +-- Location: FF_X31_Y19_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[4]_OTERM1965\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(4)); + +-- Location: LABCELL_X43_Y13_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[4]~feeder_combout\); + +-- Location: FF_X43_Y13_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(4)); + +-- Location: LABCELL_X43_Y13_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[4]~feeder_combout\); + +-- Location: FF_X43_Y13_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(4)); + +-- Location: FF_X41_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(4)); + +-- Location: LABCELL_X43_Y13_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[4]~feeder_combout\); + +-- Location: FF_X43_Y13_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(4)); + +-- Location: LABCELL_X41_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(4))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(4)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(4) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001100000100010011111111011101000011001101110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~1_combout\); + +-- Location: FF_X42_Y13_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(4)); + +-- Location: FF_X42_Y13_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(4)); + +-- Location: FF_X42_Y13_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(4)); + +-- Location: FF_X44_Y11_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(4)); + +-- Location: MLABCELL_X42_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(4)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(4))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(4))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(4) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(4))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(4))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001000011011100000111001101001100010011110111110001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~0_combout\); + +-- Location: LABCELL_X41_Y13_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux319~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux319~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~2_combout\); + +-- Location: FF_X41_Y13_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(4)); + +-- Location: LABCELL_X24_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[4]_NEW2020\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[4]_OTERM2021\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(4))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(4))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[4]_OTERM2021\); + +-- Location: FF_X24_Y17_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[4]_OTERM2021\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4)); + +-- Location: FF_X29_Y14_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(4)); + +-- Location: FF_X28_Y14_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(4)); + +-- Location: LABCELL_X24_Y14_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[4]~feeder_combout\); + +-- Location: FF_X24_Y14_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(4)); + +-- Location: FF_X28_Y14_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(4)); + +-- Location: MLABCELL_X28_Y14_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(4)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(4)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~0_combout\); + +-- Location: LABCELL_X31_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[4]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[4]~feeder_combout\); + +-- Location: FF_X31_Y13_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(4)); + +-- Location: FF_X32_Y13_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(4)); + +-- Location: FF_X32_Y13_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(4)); + +-- Location: FF_X32_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(4)); + +-- Location: LABCELL_X32_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(4)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(4))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(4))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~1_combout\); + +-- Location: LABCELL_X32_Y12_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux405~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux405~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~2_combout\); + +-- Location: FF_X32_Y12_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(4)); + +-- Location: MLABCELL_X23_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018_RESYN12818\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000011100000000000001110000000011111111111110001111111111111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\); + +-- Location: MLABCELL_X23_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_OTERM2019\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010000000100010010111111101110111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_OTERM2019\); + +-- Location: FF_X23_Y20_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_OTERM2019\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4)); + +-- Location: MLABCELL_X34_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[4]~feeder_combout\); + +-- Location: FF_X34_Y17_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(4)); + +-- Location: FF_X34_Y16_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(4)); + +-- Location: FF_X34_Y16_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(4)); + +-- Location: FF_X34_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(4)); + +-- Location: MLABCELL_X34_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(4))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(4))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~0_combout\); + +-- Location: LABCELL_X35_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[4]~feeder_combout\); + +-- Location: FF_X35_Y14_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(4)); + +-- Location: FF_X34_Y14_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(4)); + +-- Location: FF_X34_Y14_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(4)); + +-- Location: FF_X34_Y14_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(4)); + +-- Location: MLABCELL_X34_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(4)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(4))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(4))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~1_combout\); + +-- Location: MLABCELL_X34_Y12_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux343~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux343~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~2_combout\); + +-- Location: FF_X34_Y12_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(4)); + +-- Location: LABCELL_X21_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[4]_NEW2016\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[4]_OTERM2017\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(4)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[4]_OTERM2017\); + +-- Location: FF_X21_Y17_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[4]_OTERM2017\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4)); + +-- Location: LABCELL_X31_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[4]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[4]~feeder_combout\); + +-- Location: FF_X31_Y14_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(4)); + +-- Location: LABCELL_X29_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[4]~feeder_combout\); + +-- Location: FF_X29_Y14_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(4)); + +-- Location: FF_X31_Y14_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(4)); + +-- Location: FF_X31_Y14_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(4)); + +-- Location: LABCELL_X31_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(4)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(4)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~0_combout\); + +-- Location: LABCELL_X31_Y12_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[4]~feeder_combout\); + +-- Location: FF_X31_Y12_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(4)); + +-- Location: FF_X31_Y13_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(4)); + +-- Location: FF_X31_Y12_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(4)); + +-- Location: FF_X31_Y13_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(4)); + +-- Location: LABCELL_X31_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(4) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(4)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(4)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(4)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001001100010000110100111101110000011111000111001101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~1_combout\); + +-- Location: LABCELL_X31_Y12_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010110101010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux373~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux373~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~2_combout\); + +-- Location: FF_X31_Y12_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(4)); + +-- Location: FF_X37_Y24_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_OTERM2405\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(36)); + +-- Location: MLABCELL_X34_Y38_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~1_combout\); + +-- Location: LABCELL_X20_Y38_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~0_combout\); + +-- Location: MLABCELL_X37_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13094\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13094_BDD13095\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101010000111100110101111100000011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[20]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1474~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1474~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13094_BDD13095\); + +-- Location: MLABCELL_X37_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13096\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(36) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13094_BDD13095\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(36) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13094_BDD13095\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]_NEW2404_RESYN13094_BDD13095\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(36), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\); + +-- Location: MLABCELL_X37_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_OTERM2405\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(36) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110100000000000000101111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_OTERM2405\); + +-- Location: FF_X37_Y24_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_OTERM2405\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE_q\); + +-- Location: FF_X37_Y23_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(36)); + +-- Location: FF_X39_Y21_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(36)); + +-- Location: FF_X37_Y24_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(36)); + +-- Location: FF_X39_Y23_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(36)); + +-- Location: LABCELL_X39_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(36)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(36) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(36) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(36))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(36)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(36))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(36)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(36), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(36), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(36), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~1_combout\); + +-- Location: FF_X39_Y21_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(36)); + +-- Location: LABCELL_X39_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[36]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[36]~feeder_combout\); + +-- Location: FF_X39_Y15_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[36]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(36)); + +-- Location: FF_X37_Y14_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(36)); + +-- Location: FF_X39_Y23_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(36)); + +-- Location: LABCELL_X39_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(36)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(36) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(36) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(36))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(36)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(36))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(36)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(36), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(36), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(36), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~0_combout\); + +-- Location: LABCELL_X39_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux121~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux121~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~2_combout\); + +-- Location: FF_X39_Y23_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(36)); + +-- Location: MLABCELL_X37_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101100011001001110100100110001101111010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~3_combout\); + +-- Location: MLABCELL_X34_Y38_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111100111111001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~0_combout\); + +-- Location: MLABCELL_X37_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~3_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110100010001000111010001000111011101110100011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~4_combout\); + +-- Location: MLABCELL_X37_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~4_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000001000000010100000101000001010000010100000101000001010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~1_combout\); + +-- Location: FF_X37_Y27_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_NEW_REG116\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM117\); + +-- Location: LABCELL_X20_Y13_N18 +\myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_174\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_175\ = ( !\myVirtualToplevel|MEM_DATA_READ[4]~90_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4~portbdataout\ & \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ +-- & (\myVirtualToplevel|IO_DATA_READ_SD\(4))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16_combout\)))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[4]~90_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12~portbdataout\))))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(4))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000001010101111111110101010100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(4), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]~16_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~90_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_175\); + +-- Location: FF_X20_Y13_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_175\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(4)); + +-- Location: FF_X37_Y27_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_NEW_REG114\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(4), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM115\); + +-- Location: FF_X29_Y27_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_NEW_REG112\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM113\); + +-- Location: MLABCELL_X37_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM113\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM115\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM117\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM113\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM115\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM117\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101011111000011110101111100101111011111110010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM107\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM117\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM115\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM113\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\); + +-- Location: FF_X37_Y23_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(36)); + +-- Location: FF_X39_Y24_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(36)); + +-- Location: LABCELL_X40_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[36]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[36]~feeder_combout\); + +-- Location: FF_X40_Y23_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[36]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(36)); + +-- Location: FF_X39_Y23_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(36)); + +-- Location: LABCELL_X39_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(36)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(36) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(36)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(36))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(36))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(36), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(36), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(36), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~0_combout\); + +-- Location: LABCELL_X40_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[36]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[36]~feeder_combout\); + +-- Location: FF_X40_Y23_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[36]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(36)); + +-- Location: FF_X39_Y25_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(36)); + +-- Location: LABCELL_X40_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[36]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[36]~feeder_combout\); + +-- Location: FF_X40_Y23_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[36]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(36)); + +-- Location: FF_X39_Y23_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(36)); + +-- Location: LABCELL_X39_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(36)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(36) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(36)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(36))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(36))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(36), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(36), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(36), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~1_combout\); + +-- Location: LABCELL_X39_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux57~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux57~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~2_combout\); + +-- Location: FF_X39_Y23_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(36)); + +-- Location: FF_X32_Y37_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_OTERM2407\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(36)); + +-- Location: LABCELL_X32_Y37_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~2_combout\); + +-- Location: LABCELL_X32_Y37_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~0_combout\); + +-- Location: LABCELL_X32_Y37_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~3_combout\); + +-- Location: LABCELL_X32_Y37_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~1_combout\); + +-- Location: LABCELL_X32_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13098\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~1_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001011010100010101101110100001101010111111000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\); + +-- Location: MLABCELL_X37_Y37_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000001010000010100000011111100111111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~6_combout\); + +-- Location: MLABCELL_X37_Y37_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000001100000011111101011111010111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~5_combout\); + +-- Location: MLABCELL_X37_Y37_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000000111111001111110101111101010000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~7_combout\); + +-- Location: MLABCELL_X37_Y37_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000010100000101111100111111001111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~8_combout\); + +-- Location: MLABCELL_X37_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~6_combout\))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\))) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~6_combout\))) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~6_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001011010100010101101110100001101010111111000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~9_combout\); + +-- Location: LABCELL_X32_Y37_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13100\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(36))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(36))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(36))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(36) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100001011111110111111000100001011111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(36), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\); + +-- Location: LABCELL_X32_Y37_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_OTERM2407\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(36) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_OTERM2407\); + +-- Location: FF_X32_Y37_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_OTERM2407\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE_q\); + +-- Location: FF_X50_Y21_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(36)); + +-- Location: LABCELL_X52_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[36]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[36]~feeder_combout\); + +-- Location: FF_X52_Y21_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[36]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(36)); + +-- Location: FF_X50_Y21_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(36)); + +-- Location: LABCELL_X52_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[36]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[36]~feeder_combout\); + +-- Location: FF_X52_Y21_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[36]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(36)); + +-- Location: LABCELL_X50_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(36) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(36) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(36) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(36))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(36)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(36) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(36))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(36))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(36) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(36))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000101011001110100100110101011100011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(36), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(36), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(36), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~1_combout\); + +-- Location: FF_X52_Y17_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(36)); + +-- Location: FF_X50_Y17_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(36)); + +-- Location: LABCELL_X52_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[36]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[36]~feeder_combout\); + +-- Location: FF_X52_Y21_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[36]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(36)); + +-- Location: FF_X52_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(36)); + +-- Location: LABCELL_X52_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(36))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(36))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(36)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(36) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(36) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(36), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(36), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(36), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~0_combout\); + +-- Location: LABCELL_X50_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux249~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux249~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~2_combout\); + +-- Location: FF_X50_Y21_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(36)); + +-- Location: MLABCELL_X34_Y38_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001101110111011101100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~0_combout\); + +-- Location: LABCELL_X20_Y38_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111100111111001100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~1_combout\); + +-- Location: MLABCELL_X34_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13350\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13350_BDD13351\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001000011010000110111110001111100011111110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1532~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1532~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13350_BDD13351\); + +-- Location: FF_X35_Y36_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_OTERM2555\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]~DUPLICATE_q\); + +-- Location: LABCELL_X35_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13352\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13350_BDD13351\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13350_BDD13351\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]_NEW2554_RESYN13350_BDD13351\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\); + +-- Location: LABCELL_X35_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_OTERM2555\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001110111111101110100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_OTERM2555\); + +-- Location: FF_X35_Y36_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_OTERM2555\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36)); + +-- Location: LABCELL_X50_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[36]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(36), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[36]~feeder_combout\); + +-- Location: FF_X50_Y31_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[36]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(36)); + +-- Location: LABCELL_X48_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[36]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(36), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[36]~feeder_combout\); + +-- Location: FF_X48_Y29_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[36]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(36)); + +-- Location: LABCELL_X47_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[36]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(36), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[36]~feeder_combout\); + +-- Location: FF_X47_Y29_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[36]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(36)); + +-- Location: FF_X48_Y29_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(36)); + +-- Location: LABCELL_X48_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(36)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(36) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(36)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(36))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(36))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(36), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(36), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(36), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~0_combout\); + +-- Location: LABCELL_X52_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[36]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(36), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[36]~feeder_combout\); + +-- Location: FF_X52_Y27_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[36]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(36)); + +-- Location: FF_X50_Y27_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(36)); + +-- Location: FF_X50_Y27_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(36)); + +-- Location: LABCELL_X50_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[36]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(36), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[36]~feeder_combout\); + +-- Location: FF_X50_Y31_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[36]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(36)); + +-- Location: LABCELL_X50_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(36) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(36)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(36)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(36) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(36))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(36) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(36) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(36) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(36)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(36) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(36) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(36))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110100000001110011011111000100111101001100011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(36), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(36), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(36), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~1_combout\); + +-- Location: LABCELL_X50_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux185~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux185~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~2_combout\); + +-- Location: FF_X50_Y27_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(36)); + +-- Location: LABCELL_X39_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(36) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(36) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(36) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(36) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(36), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(36), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(36), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(36), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~0_combout\); + +-- Location: MLABCELL_X34_Y12_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(4))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(4)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(4) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(4) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000101001111110000010100110000111101010011111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~1_combout\); + +-- Location: MLABCELL_X34_Y12_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(32)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(32)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100010001110100011100110011111111110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]~59_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(32), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~2_combout\); + +-- Location: MLABCELL_X34_Y12_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[36]_NEW1782\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[36]_OTERM1783\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011111111110000001100000000110011111111111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(35), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(36), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[36]_OTERM1783\); + +-- Location: FF_X34_Y12_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[36]_OTERM1783\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36)); + +-- Location: LABCELL_X31_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[5]_NEW1956\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[5]_OTERM1957\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(5) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[5]_OTERM1957\); + +-- Location: FF_X31_Y19_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[5]_OTERM1957\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(5)); + +-- Location: FF_X36_Y13_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(5)); + +-- Location: FF_X41_Y19_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(5)); + +-- Location: LABCELL_X39_Y14_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[5]~feeder_combout\); + +-- Location: FF_X39_Y14_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(5)); + +-- Location: FF_X41_Y13_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(5)); + +-- Location: LABCELL_X41_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(5)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(5) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(5)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(5)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~1_combout\); + +-- Location: FF_X42_Y13_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(5)); + +-- Location: LABCELL_X41_Y13_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[5]~feeder_combout\); + +-- Location: FF_X41_Y13_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(5)); + +-- Location: FF_X42_Y13_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(5)); + +-- Location: FF_X42_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(5)); + +-- Location: MLABCELL_X42_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(5)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(5)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(5)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(5)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~0_combout\); + +-- Location: LABCELL_X41_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux318~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux318~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~2_combout\); + +-- Location: FF_X41_Y13_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(5)); + +-- Location: FF_X19_Y18_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(5)); + +-- Location: MLABCELL_X23_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[5]_NEW2038\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[5]_OTERM2039\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(5))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(5) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(5))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(5)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[5]_OTERM2039\); + +-- Location: FF_X23_Y17_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[5]_OTERM2039\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(5)); + +-- Location: FF_X31_Y14_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(5)); + +-- Location: FF_X31_Y14_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(5)); + +-- Location: LABCELL_X29_Y14_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[5]~feeder_combout\); + +-- Location: FF_X29_Y14_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(5)); + +-- Location: FF_X31_Y14_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(5)); + +-- Location: LABCELL_X31_Y14_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(5)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(5)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(5))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(5))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~0_combout\); + +-- Location: FF_X28_Y15_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(5)); + +-- Location: LABCELL_X29_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[5]~feeder_combout\); + +-- Location: FF_X29_Y18_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(5)); + +-- Location: FF_X24_Y16_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(5)); + +-- Location: FF_X28_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(5)); + +-- Location: MLABCELL_X28_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(5)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(5)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(5)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(5)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~1_combout\); + +-- Location: MLABCELL_X28_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux404~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux404~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~2_combout\); + +-- Location: FF_X28_Y15_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(5)); + +-- Location: MLABCELL_X23_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[5]_NEW2034\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[5]_OTERM2035\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[5]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[5]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[5]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[5]_OTERM2035\); + +-- Location: FF_X23_Y16_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[5]_OTERM2035\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5)); + +-- Location: LABCELL_X29_Y16_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[5]~feeder_combout\); + +-- Location: FF_X29_Y16_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(5)); + +-- Location: MLABCELL_X34_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[5]~feeder_combout\); + +-- Location: FF_X34_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(5)); + +-- Location: LABCELL_X29_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[5]~feeder_combout\); + +-- Location: FF_X29_Y16_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(5)); + +-- Location: FF_X29_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(5)); + +-- Location: LABCELL_X29_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(5)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(5)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(5)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(5)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~0_combout\); + +-- Location: FF_X28_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(5)); + +-- Location: LABCELL_X25_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[5]~feeder_combout\); + +-- Location: FF_X25_Y15_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(5)); + +-- Location: LABCELL_X24_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[5]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[5]~feeder_combout\); + +-- Location: FF_X24_Y16_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(5)); + +-- Location: FF_X28_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(5)); + +-- Location: MLABCELL_X28_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(5)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(5)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(5)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(5)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~1_combout\); + +-- Location: MLABCELL_X28_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux372~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux372~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~2_combout\); + +-- Location: FF_X28_Y15_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(5)); + +-- Location: FF_X29_Y20_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_OTERM2037\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(5)); + +-- Location: LABCELL_X29_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036_RESYN12824\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(5) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(5)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001111100111111000111110011111100001110000011000000111000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\); + +-- Location: LABCELL_X29_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_OTERM2037\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010000000110011110111111100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_OTERM2037\); + +-- Location: FF_X29_Y20_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_OTERM2037\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE_q\); + +-- Location: MLABCELL_X37_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[5]~feeder_combout\); + +-- Location: FF_X37_Y18_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(5)); + +-- Location: LABCELL_X31_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[5]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[5]~feeder_combout\); + +-- Location: FF_X31_Y14_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(5)); + +-- Location: LABCELL_X31_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[5]~feeder_combout\); + +-- Location: FF_X31_Y16_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(5)); + +-- Location: FF_X31_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(5)); + +-- Location: LABCELL_X31_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(5)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(5)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(5)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~0_combout\); + +-- Location: MLABCELL_X34_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[5]~feeder_combout\); + +-- Location: FF_X34_Y15_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(5)); + +-- Location: MLABCELL_X37_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[5]~feeder_combout\); + +-- Location: FF_X37_Y18_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(5)); + +-- Location: FF_X34_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(5)); + +-- Location: MLABCELL_X34_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[5]~feeder_combout\); + +-- Location: FF_X34_Y15_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(5)); + +-- Location: MLABCELL_X34_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(5) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(5))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(5))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(5))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~1_combout\); + +-- Location: LABCELL_X31_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux342~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux342~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~2_combout\); + +-- Location: FF_X31_Y15_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(5)); + +-- Location: LABCELL_X35_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~1_combout\); + +-- Location: LABCELL_X35_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~0_combout\); + +-- Location: LABCELL_X35_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13342\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010101010110101111101010101010111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1531~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1531~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\); + +-- Location: LABCELL_X47_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13344\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011111100111100110000001100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\); + +-- Location: LABCELL_X47_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_OTERM2549\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011110111001111111100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_OTERM2549\); + +-- Location: FF_X47_Y27_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_OTERM2549\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37)); + +-- Location: FF_X45_Y22_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(37)); + +-- Location: FF_X45_Y22_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(37)); + +-- Location: LABCELL_X44_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[37]~feeder_combout\); + +-- Location: FF_X44_Y22_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(37)); + +-- Location: FF_X45_Y22_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(37)); + +-- Location: MLABCELL_X45_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(37)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(37) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(37)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(37))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(37)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(37))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(37)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(37), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(37), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(37), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~0_combout\); + +-- Location: FF_X42_Y25_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(37)); + +-- Location: LABCELL_X44_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[37]~feeder_combout\); + +-- Location: FF_X44_Y25_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(37)); + +-- Location: FF_X42_Y25_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(37)); + +-- Location: LABCELL_X47_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[37]~feeder_combout\); + +-- Location: FF_X47_Y23_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(37)); + +-- Location: MLABCELL_X42_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(37) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(37)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(37))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(37) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(37) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(37) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(37) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(37) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(37))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(37) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(37) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(37) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010000000000110101111111110011010100001111001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(37), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(37), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~1_combout\); + +-- Location: MLABCELL_X42_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux184~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux184~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~2_combout\); + +-- Location: FF_X42_Y25_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(37)); + +-- Location: LABCELL_X35_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000011110101010111111111001100110000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~0_combout\); + +-- Location: LABCELL_X35_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~1_combout\); + +-- Location: MLABCELL_X37_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13118\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100000011000111011100111111010001000011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1473~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1473~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\); + +-- Location: FF_X47_Y27_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_OTERM2417\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]~DUPLICATE_q\); + +-- Location: LABCELL_X47_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13120\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]~DUPLICATE_q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110000111100000000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\); + +-- Location: LABCELL_X47_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_OTERM2417\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011110111111100111100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_OTERM2417\); + +-- Location: FF_X47_Y27_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_OTERM2417\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37)); + +-- Location: MLABCELL_X45_Y21_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[37]~feeder_combout\); + +-- Location: FF_X45_Y21_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(37)); + +-- Location: MLABCELL_X45_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[37]~feeder_combout\); + +-- Location: FF_X45_Y21_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(37)); + +-- Location: FF_X45_Y21_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(37)); + +-- Location: FF_X47_Y27_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(37)); + +-- Location: MLABCELL_X45_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(37) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(37) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(37) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(37))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(37) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(37) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(37))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(37) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(37) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(37))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100001111110100010000001100011101110011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(37), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(37), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~0_combout\); + +-- Location: FF_X44_Y25_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(37)); + +-- Location: MLABCELL_X45_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[37]~feeder_combout\); + +-- Location: FF_X45_Y23_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(37)); + +-- Location: MLABCELL_X42_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[37]~feeder_combout\); + +-- Location: FF_X42_Y25_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(37)); + +-- Location: FF_X42_Y25_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(37)); + +-- Location: MLABCELL_X42_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(37)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(37) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(37) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(37))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(37)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(37))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(37)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(37), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(37), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(37), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~1_combout\); + +-- Location: MLABCELL_X42_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux120~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux120~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~2_combout\); + +-- Location: FF_X42_Y25_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(37)); + +-- Location: LABCELL_X35_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~3_combout\); + +-- Location: LABCELL_X35_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~1_combout\); + +-- Location: MLABCELL_X34_Y31_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~2_combout\); + +-- Location: LABCELL_X35_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~0_combout\); + +-- Location: LABCELL_X35_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13122\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~3_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100000001111100011100110100111101000011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\); + +-- Location: LABCELL_X31_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~8_combout\); + +-- Location: LABCELL_X31_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~7_combout\); + +-- Location: LABCELL_X32_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~6_combout\); + +-- Location: LABCELL_X35_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~5_combout\); + +-- Location: MLABCELL_X37_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~7_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~7_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~7_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011111101011111001100000101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~9_combout\); + +-- Location: MLABCELL_X37_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13124\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~9_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37) & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000010100110101010110100011101010101111001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(37), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\); + +-- Location: MLABCELL_X37_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_OTERM2419\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011111101111111001100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_OTERM2419\); + +-- Location: FF_X37_Y31_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_OTERM2419\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37)); + +-- Location: FF_X43_Y25_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(37)); + +-- Location: MLABCELL_X42_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[37]~feeder_combout\); + +-- Location: FF_X42_Y26_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(37)); + +-- Location: LABCELL_X52_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[37]~feeder_combout\); + +-- Location: FF_X52_Y29_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(37)); + +-- Location: FF_X43_Y25_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(37)); + +-- Location: LABCELL_X43_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(37))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(37))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(37)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(37) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(37)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010010111110101111100010001101110110001000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(37), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(37), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(37), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~0_combout\); + +-- Location: LABCELL_X39_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[37]~feeder_combout\); + +-- Location: FF_X39_Y26_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(37)); + +-- Location: LABCELL_X39_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[37]~feeder_combout\); + +-- Location: FF_X39_Y26_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(37)); + +-- Location: FF_X42_Y25_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(37)); + +-- Location: FF_X42_Y25_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(37)); + +-- Location: MLABCELL_X42_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(37)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(37) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(37)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(37))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(37)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(37))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(37)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(37), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(37), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(37), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~1_combout\); + +-- Location: MLABCELL_X42_Y25_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux248~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux248~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~2_combout\); + +-- Location: FF_X42_Y25_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(37)); + +-- Location: LABCELL_X35_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~3_combout\); + +-- Location: MLABCELL_X34_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][5]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~0_combout\); + +-- Location: MLABCELL_X37_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~3_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110000110000001100001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~4_combout\); + +-- Location: MLABCELL_X37_Y27_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~4_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010100000000000001010101000000000101010100000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~1_combout\); + +-- Location: FF_X37_Y27_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_NEW_REG128\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM129\); + +-- Location: LABCELL_X21_Y14_N18 +\myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_168\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_169\ = ( !\myVirtualToplevel|MEM_DATA_READ[5]~88_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(5) & +-- (((\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5~portbdataout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\))))) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[5]~88_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))) # (\myVirtualToplevel|IO_DATA_READ_SD\(5)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ +-- & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13~portbdataout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000001111111111110000111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(5), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]~17_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~88_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_169\); + +-- Location: FF_X21_Y14_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_169\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(5)); + +-- Location: FF_X31_Y27_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_NEW_REG126\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(5), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM127\); + +-- Location: FF_X31_Y27_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_NEW_REG124\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM125\); + +-- Location: MLABCELL_X37_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM125\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM127\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM129\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM125\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM127\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM129\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101011111000011110101111100101111011111110010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM107\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM129\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM127\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM125\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\); + +-- Location: LABCELL_X41_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[37]~feeder_combout\); + +-- Location: FF_X41_Y21_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(37)); + +-- Location: LABCELL_X41_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[37]~feeder_combout\); + +-- Location: FF_X41_Y24_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(37)); + +-- Location: FF_X41_Y24_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(37)); + +-- Location: LABCELL_X41_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[37]~feeder_combout\); + +-- Location: FF_X41_Y24_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(37)); + +-- Location: LABCELL_X41_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(37) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(37)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(37)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(37) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(37) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(37)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(37))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(37) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(37) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(37)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(37))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(37) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(37) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(37))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100010001000000111101110111001111000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(37), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(37), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(37), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~0_combout\); + +-- Location: FF_X41_Y27_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(37)); + +-- Location: FF_X42_Y25_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(37)); + +-- Location: LABCELL_X41_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[37]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[37]~feeder_combout\); + +-- Location: FF_X41_Y23_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[37]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(37)); + +-- Location: FF_X42_Y25_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(37)); + +-- Location: MLABCELL_X42_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(37)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(37) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(37) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(37))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(37))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(37), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(37), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(37), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~1_combout\); + +-- Location: MLABCELL_X42_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux56~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux56~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~2_combout\); + +-- Location: FF_X42_Y25_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(37)); + +-- Location: MLABCELL_X42_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(37))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(37)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(37))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(37) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(37)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(37) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(37)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011110011111100111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(37), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(37), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(37), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~0_combout\); + +-- Location: LABCELL_X29_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(5)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(5)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(5))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(5))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000000000101010100001111001100111111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~1_combout\); + +-- Location: LABCELL_X35_Y13_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(5)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(5)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(5) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(5))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101110000011100110100110001001111011111000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]~57_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(33), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~2_combout\); + +-- Location: LABCELL_X35_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[37]_NEW1778\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[37]_OTERM1779\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(37))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(37))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(36), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[37]_OTERM1779\); + +-- Location: FF_X35_Y13_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[37]_OTERM1779\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(37)); + +-- Location: FF_X35_Y13_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]_OTERM1781\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(38)); + +-- Location: LABCELL_X31_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[6]_NEW1960\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[6]_OTERM1961\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(6))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[6]_OTERM1961\); + +-- Location: FF_X31_Y19_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[6]_OTERM1961\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(6)); + +-- Location: FF_X41_Y11_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(6)); + +-- Location: FF_X29_Y11_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(6)); + +-- Location: FF_X41_Y11_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(6)); + +-- Location: FF_X29_Y11_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(6)); + +-- Location: LABCELL_X29_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(6)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(6)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(6)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~1_combout\); + +-- Location: MLABCELL_X45_Y13_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[6]~feeder_combout\); + +-- Location: FF_X45_Y13_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(6)); + +-- Location: FF_X48_Y13_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(6)); + +-- Location: MLABCELL_X45_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[6]~feeder_combout\); + +-- Location: FF_X45_Y13_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(6)); + +-- Location: FF_X45_Y13_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(6)); + +-- Location: MLABCELL_X45_Y13_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(6))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(6))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(6)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~0_combout\); + +-- Location: LABCELL_X35_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000000000000000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux317~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux317~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~2_combout\); + +-- Location: FF_X35_Y11_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(6)); + +-- Location: MLABCELL_X34_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048_RESYN12828\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001001111111111000100111111111100000000111011000000000011101100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\); + +-- Location: MLABCELL_X34_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_OTERM2049\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001010001011111111010111011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_OTERM2049\); + +-- Location: FF_X34_Y23_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_OTERM2049\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6)); + +-- Location: FF_X32_Y15_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(6)); + +-- Location: FF_X31_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(6)); + +-- Location: FF_X31_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(6)); + +-- Location: FF_X34_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(6)); + +-- Location: LABCELL_X31_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(6) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(6))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(6)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(6))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(6))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000101011001110100100110101011100011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~1_combout\); + +-- Location: MLABCELL_X34_Y16_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[6]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[6]~feeder_combout\); + +-- Location: FF_X34_Y16_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(6)); + +-- Location: MLABCELL_X34_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[6]~feeder_combout\); + +-- Location: FF_X34_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(6)); + +-- Location: FF_X36_Y16_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(6)); + +-- Location: FF_X34_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(6)); + +-- Location: MLABCELL_X34_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(6)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(6))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(6))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~0_combout\); + +-- Location: LABCELL_X31_Y16_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux341~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux341~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~2_combout\); + +-- Location: FF_X31_Y16_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(6)); + +-- Location: FF_X23_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[6]~111_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(6)); + +-- Location: MLABCELL_X23_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[6]_NEW2050\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[6]_OTERM2051\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(6)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(6)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[6]_OTERM2051\); + +-- Location: FF_X23_Y18_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[6]_OTERM2051\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6)); + +-- Location: FF_X28_Y16_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(6)); + +-- Location: LABCELL_X26_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[6]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[6]~feeder_combout\); + +-- Location: FF_X26_Y16_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(6)); + +-- Location: FF_X28_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(6)); + +-- Location: FF_X28_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(6)); + +-- Location: MLABCELL_X28_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(6)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(6)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(6) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(6)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(6) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(6))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011010101010001101110101010000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~0_combout\); + +-- Location: FF_X25_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(6)); + +-- Location: LABCELL_X25_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[6]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[6]~feeder_combout\); + +-- Location: FF_X25_Y15_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(6)); + +-- Location: FF_X24_Y16_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(6)); + +-- Location: FF_X25_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(6)); + +-- Location: LABCELL_X25_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(6)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(6)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(6))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(6))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~1_combout\); + +-- Location: MLABCELL_X28_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux403~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux403~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~2_combout\); + +-- Location: FF_X28_Y15_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(6)); + +-- Location: LABCELL_X21_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[6]_NEW2046\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[6]_OTERM2047\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(6)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(6)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[6]_OTERM2047\); + +-- Location: FF_X21_Y17_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[6]_OTERM2047\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6)); + +-- Location: LABCELL_X31_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[6]~feeder_combout\); + +-- Location: FF_X31_Y13_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(6)); + +-- Location: LABCELL_X31_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[6]~feeder_combout\); + +-- Location: FF_X31_Y13_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(6)); + +-- Location: LABCELL_X32_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[6]~feeder_combout\); + +-- Location: FF_X32_Y13_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(6)); + +-- Location: FF_X31_Y13_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(6)); + +-- Location: LABCELL_X31_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(6)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(6)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(6))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(6))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~1_combout\); + +-- Location: MLABCELL_X28_Y14_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[6]~feeder_combout\); + +-- Location: FF_X28_Y14_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(6)); + +-- Location: MLABCELL_X28_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[6]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[6]~feeder_combout\); + +-- Location: FF_X28_Y14_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(6)); + +-- Location: FF_X29_Y14_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(6)); + +-- Location: FF_X28_Y14_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(6)); + +-- Location: MLABCELL_X28_Y14_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(6)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(6)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(6)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(6) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(6)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~0_combout\); + +-- Location: LABCELL_X29_Y12_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux371~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux371~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~2_combout\); + +-- Location: FF_X29_Y12_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(6)); + +-- Location: LABCELL_X29_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000000110000001100010001110111011100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~1_combout\); + +-- Location: LABCELL_X26_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~0_combout\); + +-- Location: MLABCELL_X34_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13346\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13346_BDD13347\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011000000100001001111001110110111111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1530~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1530~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13346_BDD13347\); + +-- Location: MLABCELL_X34_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13348\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13346_BDD13347\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13346_BDD13347\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100101111001011110010111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[38]_NEW2551_RESYN13346_BDD13347\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\); + +-- Location: MLABCELL_X34_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_OTERM2552\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_OTERM2552\); + +-- Location: FF_X34_Y34_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_OTERM2552\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38)); + +-- Location: LABCELL_X40_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[38]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[38]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[38]~feeder_combout\); + +-- Location: FF_X40_Y19_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[38]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(38)); + +-- Location: LABCELL_X48_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[38]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[38]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[38]~feeder_combout\); + +-- Location: FF_X48_Y21_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[38]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(38)); + +-- Location: FF_X44_Y23_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(38)); + +-- Location: LABCELL_X44_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[38]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[38]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[38]~feeder_combout\); + +-- Location: FF_X44_Y23_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[38]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(38)); + +-- Location: LABCELL_X44_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(38) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(38))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(38) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(38) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(38)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(38))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(38) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(38) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(38) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(38)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(38) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(38) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(38)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001001010111010100101010011110100010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(38), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(38), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~1_combout\); + +-- Location: LABCELL_X53_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[38]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[38]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[38]~feeder_combout\); + +-- Location: FF_X53_Y19_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[38]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(38)); + +-- Location: LABCELL_X53_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[38]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[38]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[38]~feeder_combout\); + +-- Location: FF_X53_Y19_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[38]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(38)); + +-- Location: FF_X53_Y19_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(38)); + +-- Location: MLABCELL_X49_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[38]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[38]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[38]~feeder_combout\); + +-- Location: FF_X49_Y23_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[38]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(38)); + +-- Location: LABCELL_X53_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(38) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(38)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(38)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(38) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(38) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(38))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(38) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(38) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(38) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(38) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(38)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(38) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(38) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(38)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(38))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011101001100110001110111001100000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(38), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(38), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~0_combout\); + +-- Location: LABCELL_X44_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux183~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux183~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~2_combout\); + +-- Location: FF_X44_Y23_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(38)); + +-- Location: LABCELL_X31_Y27_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101011100000011010101110000001100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~10_combout\); + +-- Location: FF_X31_Y27_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG142\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~10_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM143\); + +-- Location: LABCELL_X31_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101110100001100010111010000110000001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~9_combout\); + +-- Location: FF_X31_Y27_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG140\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~9_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM141\); + +-- Location: MLABCELL_X23_Y18_N21 +\myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_171\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_172\ = ( !\myVirtualToplevel|MEM_DATA_READ[6]~86_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6~portbdataout\ & (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ +-- & (\myVirtualToplevel|IO_DATA_READ_SD\(6))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\)))))) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[6]~86_combout\ & ( +-- (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14~portbdataout\)))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(6))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001000100001010101110110000101000010001010111111011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(6), + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~86_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]~21_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_172\); + +-- Location: FF_X23_Y18_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_172\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(6)); + +-- Location: LABCELL_X31_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~0_combout\); + +-- Location: LABCELL_X31_Y35_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~1_combout\); + +-- Location: LABCELL_X36_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(6))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(6))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(6)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000001010011011101010000011100110101010101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~4_combout\); + +-- Location: LABCELL_X36_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~5_combout\); + +-- Location: LABCELL_X31_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~2_RTM0146\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~2_RTM0146_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~5_combout\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~4_combout\) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~5_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0111001111111111000000001111111100110011111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~2_RTM0146_combout\); + +-- Location: FF_X31_Y27_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG144\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~2_RTM0146_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM145\); + +-- Location: FF_X31_Y27_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG138\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM139\); + +-- Location: FF_X31_Y27_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG136\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM137\); + +-- Location: LABCELL_X48_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM139\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM137\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM145\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM139\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM137\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM143\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM141\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM145\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM139\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM137\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM145\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM139\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM137\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM145\ +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111110001111100011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM143\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM141\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM145\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM139\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM137\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\); + +-- Location: LABCELL_X52_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[38]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[38]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[38]~feeder_combout\); + +-- Location: FF_X52_Y21_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[38]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(38)); + +-- Location: FF_X49_Y21_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(38)); + +-- Location: FF_X49_Y21_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(38)); + +-- Location: FF_X49_Y17_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(38)); + +-- Location: MLABCELL_X49_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(38) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(38))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(38) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(38) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(38)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(38) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(38) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(38)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(38) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(38) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(38)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000001100010001000011111101110111000011000111011100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(38), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(38), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~1_combout\); + +-- Location: LABCELL_X52_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[38]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[38]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[38]~feeder_combout\); + +-- Location: FF_X52_Y26_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[38]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(38)); + +-- Location: FF_X49_Y31_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(38)); + +-- Location: FF_X49_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(38)); + +-- Location: FF_X49_Y31_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(38)); + +-- Location: MLABCELL_X49_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(38)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(38) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(38)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(38) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(38)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(38) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(38)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(38), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(38), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(38), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~0_combout\); + +-- Location: LABCELL_X44_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux55~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux55~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~2_combout\); + +-- Location: FF_X44_Y23_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(38)); + +-- Location: LABCELL_X32_Y35_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~3_combout\); + +-- Location: LABCELL_X32_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~2_combout\); + +-- Location: LABCELL_X31_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~0_combout\); + +-- Location: LABCELL_X31_Y35_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~1_combout\); + +-- Location: LABCELL_X32_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13142\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\) +-- # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~2_combout\))))) ) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011010001100101011110001010100110111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\); + +-- Location: LABCELL_X35_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~8_combout\); + +-- Location: LABCELL_X29_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~7_combout\); + +-- Location: LABCELL_X35_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~6_combout\); + +-- Location: LABCELL_X35_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~5_combout\); + +-- Location: LABCELL_X35_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~7_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~7_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~7_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010000110010011101101001100011011100101110101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~9_combout\); + +-- Location: MLABCELL_X42_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13144\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~9_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110000010101010011010110101010001110101111111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(38), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\); + +-- Location: MLABCELL_X42_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_OTERM2429\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001101111111011101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_OTERM2429\); + +-- Location: FF_X42_Y27_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_OTERM2429\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38)); + +-- Location: FF_X48_Y20_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(38)); + +-- Location: FF_X48_Y20_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(38)); + +-- Location: FF_X48_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(38)); + +-- Location: MLABCELL_X49_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[38]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[38]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[38]~feeder_combout\); + +-- Location: FF_X49_Y20_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[38]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(38)); + +-- Location: LABCELL_X48_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(38) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(38))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(38) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(38) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(38) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(38))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(38) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(38) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(38)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(38) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(38) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(38) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(38)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001111100110001000111001100110100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(38), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(38), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~0_combout\); + +-- Location: FF_X42_Y27_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(38)); + +-- Location: FF_X44_Y23_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(38)); + +-- Location: FF_X44_Y23_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(38)); + +-- Location: MLABCELL_X45_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[38]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[38]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[38]~feeder_combout\); + +-- Location: FF_X45_Y23_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[38]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(38)); + +-- Location: LABCELL_X44_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(38) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(38))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(38) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(38) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(38)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(38) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(38) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(38)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(38) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(38) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(38))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(38)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000101010001001010010111101110000011110100111010101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(38), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(38), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~1_combout\); + +-- Location: LABCELL_X44_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux247~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux247~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~2_combout\); + +-- Location: FF_X44_Y23_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(38)); + +-- Location: LABCELL_X29_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~0_combout\); + +-- Location: LABCELL_X29_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111100111111001100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~1_combout\); + +-- Location: MLABCELL_X42_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13138\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13138_BDD13139\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1472~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1472~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13138_BDD13139\); + +-- Location: MLABCELL_X37_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13140\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13138_BDD13139\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13138_BDD13139\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000101000011110000010100001111101011110000111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[38]_NEW2426_RESYN13138_BDD13139\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\); + +-- Location: MLABCELL_X37_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_OTERM2427\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000101111111110111010100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_OTERM2427\); + +-- Location: FF_X37_Y35_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_OTERM2427\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38)); + +-- Location: LABCELL_X53_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[38]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[38]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[38]~feeder_combout\); + +-- Location: FF_X53_Y27_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[38]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(38)); + +-- Location: FF_X53_Y28_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(38)); + +-- Location: LABCELL_X53_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[38]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[38]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(38), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[38]~feeder_combout\); + +-- Location: FF_X53_Y27_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[38]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(38)); + +-- Location: FF_X53_Y27_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(38)); + +-- Location: LABCELL_X53_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(38)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(38) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(38)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(38) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(38)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(38))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(38) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(38)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(38))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(38), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(38), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(38), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~1_combout\); + +-- Location: FF_X52_Y28_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(38)); + +-- Location: FF_X52_Y28_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(38)); + +-- Location: FF_X53_Y28_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(38)); + +-- Location: FF_X53_Y28_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(38)); + +-- Location: LABCELL_X53_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(38)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(38))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(38)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(38))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(38) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(38)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(38) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(38)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(38), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(38), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(38), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~0_combout\); + +-- Location: LABCELL_X50_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux119~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux119~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~2_combout\); + +-- Location: FF_X50_Y27_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(38)); + +-- Location: LABCELL_X44_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(38) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(38) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(38) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(38) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(38), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(38), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(38), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(38), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~0_combout\); + +-- Location: LABCELL_X29_Y12_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(6))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(6))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(6)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(6), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~1_combout\); + +-- Location: LABCELL_X35_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(34))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(6)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(34) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(6)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(34))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(6) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(34) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(6) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000101001100001111010100111111000001010011111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(34), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]~51_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~2_combout\); + +-- Location: LABCELL_X35_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]_NEW1780\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]_OTERM1781\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(38))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(37))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(38))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(37)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(37), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]_OTERM1781\); + +-- Location: FF_X35_Y13_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]_OTERM1781\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[7]_NEW1966\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[7]_OTERM1967\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[7]_OTERM1967\); + +-- Location: FF_X31_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[7]_OTERM1967\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7)); + +-- Location: LABCELL_X25_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[7]~feeder_combout\); + +-- Location: FF_X25_Y13_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(7)); + +-- Location: LABCELL_X25_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[7]~feeder_combout\); + +-- Location: FF_X25_Y13_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(7)); + +-- Location: FF_X25_Y13_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(7)); + +-- Location: LABCELL_X26_Y13_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[7]~feeder_combout\); + +-- Location: FF_X26_Y13_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(7)); + +-- Location: LABCELL_X25_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(7))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(7)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(7) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(7) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(7)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(7) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010000100010101111110111011000010101011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~1_combout\); + +-- Location: FF_X29_Y13_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(7)); + +-- Location: FF_X29_Y13_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(7)); + +-- Location: FF_X29_Y13_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(7)); + +-- Location: FF_X28_Y13_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(7)); + +-- Location: LABCELL_X29_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(7) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(7) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(7)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(7))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(7) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(7))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100000000000111011100110000011101001100110001110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~0_combout\); + +-- Location: LABCELL_X31_Y12_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux316~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux316~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~2_combout\); + +-- Location: FF_X31_Y12_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(7)); + +-- Location: LABCELL_X24_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[7]_NEW2026\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[7]_OTERM2027\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(7))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(7))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[7]_OTERM2027\); + +-- Location: FF_X24_Y17_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[7]_OTERM2027\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7)); + +-- Location: FF_X31_Y17_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(7)); + +-- Location: MLABCELL_X34_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[7]~feeder_combout\); + +-- Location: FF_X34_Y16_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(7)); + +-- Location: LABCELL_X31_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[7]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[7]~feeder_combout\); + +-- Location: FF_X31_Y17_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(7)); + +-- Location: FF_X31_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(7)); + +-- Location: LABCELL_X31_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(7))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(7))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~0_combout\); + +-- Location: LABCELL_X32_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[7]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[7]~feeder_combout\); + +-- Location: FF_X32_Y16_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(7)); + +-- Location: LABCELL_X24_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[7]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[7]~feeder_combout\); + +-- Location: FF_X24_Y16_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(7)); + +-- Location: FF_X32_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(7)); + +-- Location: LABCELL_X24_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[7]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[7]~feeder_combout\); + +-- Location: FF_X24_Y16_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(7)); + +-- Location: LABCELL_X32_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(7) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(7))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(7) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(7)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001110000010000110111001101001100011111000100111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~1_combout\); + +-- Location: LABCELL_X32_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux402~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux402~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~2_combout\); + +-- Location: FF_X32_Y16_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(7)); + +-- Location: MLABCELL_X23_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024_RESYN12820\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001110000000000000111000011111111111110001111111111111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\); + +-- Location: MLABCELL_X23_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_OTERM2025\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010000000100010010111111101110111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_OTERM2025\); + +-- Location: FF_X23_Y20_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_OTERM2025\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7)); + +-- Location: LABCELL_X32_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[7]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[7]~feeder_combout\); + +-- Location: FF_X32_Y18_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(7)); + +-- Location: FF_X32_Y18_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(7)); + +-- Location: MLABCELL_X34_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[7]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[7]~feeder_combout\); + +-- Location: FF_X34_Y16_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(7)); + +-- Location: FF_X32_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(7)); + +-- Location: LABCELL_X32_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(7))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(7))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(7)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010010101011111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~0_combout\); + +-- Location: FF_X32_Y16_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(7)); + +-- Location: FF_X35_Y16_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(7)); + +-- Location: FF_X32_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(7)); + +-- Location: FF_X26_Y14_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(7)); + +-- Location: LABCELL_X32_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(7) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(7) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(7) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(7))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(7)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000000001001110101010100100111101010100010011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~1_combout\); + +-- Location: LABCELL_X32_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux340~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux340~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~2_combout\); + +-- Location: FF_X32_Y16_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(7)); + +-- Location: LABCELL_X21_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[7]_NEW2022\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[7]_OTERM2023\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(7)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(7))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(7) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[7]_OTERM2023\); + +-- Location: FF_X21_Y17_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[7]_OTERM2023\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(7)); + +-- Location: FF_X32_Y18_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(7)); + +-- Location: LABCELL_X31_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[7]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(7) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[7]~feeder_combout\); + +-- Location: FF_X31_Y17_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(7)); + +-- Location: FF_X31_Y17_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(7)); + +-- Location: FF_X31_Y17_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(7)); + +-- Location: LABCELL_X31_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(7)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(7)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~0_combout\); + +-- Location: FF_X24_Y16_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(7)); + +-- Location: FF_X32_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(7)); + +-- Location: FF_X32_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(7)); + +-- Location: LABCELL_X24_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[7]~feeder_combout\); + +-- Location: FF_X24_Y16_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(7)); + +-- Location: LABCELL_X32_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(7) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(7))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(7))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(7))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100000001111100011100110100111101000011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~1_combout\); + +-- Location: LABCELL_X32_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux370~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux370~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~2_combout\); + +-- Location: FF_X32_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(7)); + +-- Location: LABCELL_X35_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000001100000011111101011111010111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~0_combout\); + +-- Location: LABCELL_X35_Y37_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~1_combout\); + +-- Location: LABCELL_X35_Y37_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13354\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13354_BDD13355\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000001010000010111110011111100111111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1529~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1529~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13354_BDD13355\); + +-- Location: LABCELL_X35_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13356\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13354_BDD13355\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13354_BDD13355\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011011101000000001101110100100010111111110010001011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[39]_NEW2557_RESYN13354_BDD13355\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(39), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\); + +-- Location: LABCELL_X35_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_OTERM2558\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011111111110111001100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_OTERM2558\); + +-- Location: FF_X35_Y34_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_OTERM2558\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39)); + +-- Location: LABCELL_X47_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(39), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[39]~feeder_combout\); + +-- Location: FF_X47_Y22_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(39)); + +-- Location: FF_X43_Y22_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(39)); + +-- Location: FF_X43_Y22_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(39)); + +-- Location: FF_X43_Y22_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(39)); + +-- Location: LABCELL_X43_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(39)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(39) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(39) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(39))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(39))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(39), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(39), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(39), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~1_combout\); + +-- Location: LABCELL_X52_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(39), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[39]~feeder_combout\); + +-- Location: FF_X52_Y18_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(39)); + +-- Location: FF_X44_Y19_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(39)); + +-- Location: FF_X44_Y18_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(39)); + +-- Location: FF_X44_Y18_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(39)); + +-- Location: LABCELL_X44_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(39))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(39)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(39))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(39)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(39)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(39) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(39) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(39), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(39), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(39), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~0_combout\); + +-- Location: LABCELL_X44_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000000000000001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux182~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux182~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~2_combout\); + +-- Location: FF_X44_Y18_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(39)); + +-- Location: FF_X34_Y35_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_OTERM2409\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(39)); + +-- Location: LABCELL_X36_Y35_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~1_combout\); + +-- Location: LABCELL_X36_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000111110001001100011100110100001101111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~0_combout\); + +-- Location: LABCELL_X36_Y31_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13102\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13102_BDD13103\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~1_combout\))) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1471~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1471~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13102_BDD13103\); + +-- Location: MLABCELL_X34_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13104\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(39) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13102_BDD13103\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(39) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13102_BDD13103\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]_NEW2408_RESYN13102_BDD13103\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(39), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\); + +-- Location: MLABCELL_X34_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_OTERM2409\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(39) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011101010101001010001010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_OTERM2409\); + +-- Location: FF_X34_Y35_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_OTERM2409\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y11_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[39]~feeder_combout\); + +-- Location: FF_X41_Y11_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(39)); + +-- Location: LABCELL_X41_Y11_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[39]~feeder_combout\); + +-- Location: FF_X41_Y11_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(39)); + +-- Location: FF_X41_Y11_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(39)); + +-- Location: FF_X47_Y15_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(39)); + +-- Location: LABCELL_X41_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(39) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(39) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(39) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(39))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(39) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(39) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(39))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(39) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(39) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(39))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000100111001101101000110110011100101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(39), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(39), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(39), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~1_combout\); + +-- Location: MLABCELL_X45_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[39]~feeder_combout\); + +-- Location: FF_X45_Y14_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(39)); + +-- Location: LABCELL_X47_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[39]~feeder_combout\); + +-- Location: FF_X47_Y14_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(39)); + +-- Location: FF_X44_Y14_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(39)); + +-- Location: FF_X45_Y14_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(39)); + +-- Location: MLABCELL_X45_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(39))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(39))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(39)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(39) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(39)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(39), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(39), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(39), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~0_combout\); + +-- Location: MLABCELL_X45_Y14_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000000000000001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux118~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux118~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~2_combout\); + +-- Location: FF_X45_Y14_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(39)); + +-- Location: LABCELL_X35_Y37_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~0_combout\); + +-- Location: LABCELL_X24_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~2_combout\); + +-- Location: LABCELL_X35_Y37_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010111110101111101011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~3_combout\); + +-- Location: LABCELL_X19_Y37_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111110011111100111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~1_combout\); + +-- Location: LABCELL_X26_Y37_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~2_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux509~2_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000111001101000011011111000100110001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~4_combout\); + +-- Location: FF_X26_Y37_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_NEW_REG360\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM361\); + +-- Location: FF_X23_Y26_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_NEW_REG356\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~16_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM357\); + +-- Location: FF_X34_Y22_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_NEW_REG358\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM359\); + +-- Location: MLABCELL_X34_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM359\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM361\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM359\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM361\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM359\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM357\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM361\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM359\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM357\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM361\)) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM361\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM357\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM359\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM321\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\); + +-- Location: LABCELL_X53_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1585~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[39]~feeder_combout\); + +-- Location: FF_X53_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(39)); + +-- Location: LABCELL_X53_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1585~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[39]~feeder_combout\); + +-- Location: FF_X53_Y20_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(39)); + +-- Location: FF_X53_Y20_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(39)); + +-- Location: LABCELL_X47_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1585~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[39]~feeder_combout\); + +-- Location: FF_X47_Y19_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(39)); + +-- Location: LABCELL_X53_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(39) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(39))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(39))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(39) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(39) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(39))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(39) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(39))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(39))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(39) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(39))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(39)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100001010100110111000011001010111010011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(39), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(39), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(39), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~0_combout\); + +-- Location: LABCELL_X47_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1585~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[39]~feeder_combout\); + +-- Location: FF_X47_Y19_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(39)); + +-- Location: LABCELL_X52_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1585~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[39]~feeder_combout\); + +-- Location: FF_X52_Y21_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(39)); + +-- Location: FF_X49_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(39)); + +-- Location: MLABCELL_X49_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1585~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[39]~feeder_combout\); + +-- Location: FF_X49_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(39)); + +-- Location: MLABCELL_X49_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(39) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(39) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(39) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(39))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(39)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(39) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(39))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(39))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(39) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(39))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000101011001110100100110101011100011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(39), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(39), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(39), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~1_combout\); + +-- Location: LABCELL_X44_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux246~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux246~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~2_combout\); + +-- Location: FF_X44_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(39)); + +-- Location: MLABCELL_X23_Y18_N36 +\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_165\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_166\ = ( !\myVirtualToplevel|MEM_DATA_READ[7]~84_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7~portbdataout\ & ((\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & +-- (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|IO_DATA_READ_SD\(7)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\))))) ) ) # ( +-- \myVirtualToplevel|MEM_DATA_READ[7]~84_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\)) # +-- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15~portbdataout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((\myVirtualToplevel|IO_DATA_READ_SD\(7)))) # +-- (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000001010101101010101111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]~22_combout\, + datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\, + datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(7), + datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~84_combout\, + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\, + datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\, + combout => \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_166\); + +-- Location: FF_X23_Y18_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_166\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(7)); + +-- Location: LABCELL_X31_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121~feeder_combout\); + +-- Location: FF_X31_Y28_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_NEW_REG120\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121\); + +-- Location: LABCELL_X36_Y35_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011010001110100011111001100111111110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~3_combout\); + +-- Location: LABCELL_X35_Y37_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101001001110010011110101010111111110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~0_combout\); + +-- Location: LABCELL_X31_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~4_combout\); + +-- Location: LABCELL_X31_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~4_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000000000101000000000101010100000000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~1_combout\); + +-- Location: FF_X31_Y28_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_NEW_REG122\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM123\); + +-- Location: FF_X31_Y28_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG104\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105\); + +-- Location: LABCELL_X31_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119~feeder_combout\); + +-- Location: FF_X31_Y28_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_NEW_REG118\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119\); + +-- Location: LABCELL_X31_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM123\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119\ +-- & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM123\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011011100110111001101110011011100110111111101110011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM121\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM123\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM107\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM119\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\); + +-- Location: FF_X35_Y27_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(39)); + +-- Location: LABCELL_X41_Y23_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[39]~feeder_combout\); + +-- Location: FF_X41_Y23_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(39)); + +-- Location: LABCELL_X44_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[39]~feeder_combout\); + +-- Location: FF_X44_Y25_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(39)); + +-- Location: FF_X44_Y25_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(39)); + +-- Location: LABCELL_X44_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(39)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(39) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(39) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(39))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(39)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(39))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(39)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(39), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(39), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(39), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~1_combout\); + +-- Location: LABCELL_X43_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[39]~feeder_combout\); + +-- Location: FF_X43_Y19_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(39)); + +-- Location: LABCELL_X44_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[39]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[39]~feeder_combout\); + +-- Location: FF_X44_Y19_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[39]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(39)); + +-- Location: FF_X44_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(39)); + +-- Location: FF_X44_Y18_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(39)); + +-- Location: LABCELL_X44_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(39) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(39))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(39))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(39) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(39) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(39) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(39))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(39) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(39)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(39) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(39) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(39))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(39)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000000001001111010101000100111010101010010011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(39), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(39), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(39), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~0_combout\); + +-- Location: LABCELL_X44_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux54~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux54~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~2_combout\); + +-- Location: FF_X44_Y18_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(39)); + +-- Location: LABCELL_X44_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(39))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(39) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(39)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(39))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(39) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(39)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(39) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(39)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011110011001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(39), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(39), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(39), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~0_combout\); + +-- Location: LABCELL_X32_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(7))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(7)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(7)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111000000000101010100110011000011111111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~1_combout\); + +-- Location: MLABCELL_X34_Y12_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(7)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101000000000000111100110101001101011111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]~58_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(35), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~2_combout\); + +-- Location: LABCELL_X35_Y12_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]_NEW1784\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]_OTERM1785\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(39))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(39))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[38]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(39), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]_OTERM1785\); + +-- Location: FF_X35_Y12_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]_OTERM1785\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(39)); + +-- Location: LABCELL_X29_Y19_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[8]_NEW1970\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[8]_OTERM1971\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(8))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(8))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[8]_OTERM1971\); + +-- Location: FF_X29_Y19_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[8]_OTERM1971\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(8)); + +-- Location: LABCELL_X31_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[8]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(8) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[8]~feeder_combout\); + +-- Location: FF_X31_Y14_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(8)); + +-- Location: LABCELL_X36_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[8]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(8) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[8]~feeder_combout\); + +-- Location: FF_X36_Y17_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(8)); + +-- Location: FF_X36_Y17_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(8)); + +-- Location: FF_X36_Y17_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(8)); + +-- Location: LABCELL_X36_Y17_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(8) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(8))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(8))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~0_combout\); + +-- Location: MLABCELL_X34_Y14_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[8]~feeder_combout\); + +-- Location: FF_X34_Y14_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(8)); + +-- Location: MLABCELL_X34_Y14_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[8]~feeder_combout\); + +-- Location: FF_X34_Y14_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(8)); + +-- Location: FF_X35_Y14_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(8)); + +-- Location: FF_X35_Y14_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(8)); + +-- Location: LABCELL_X35_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(8) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(8)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(8)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~1_combout\); + +-- Location: LABCELL_X35_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux315~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux315~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~2_combout\); + +-- Location: FF_X35_Y14_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(8)); + +-- Location: FF_X20_Y18_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(8)); + +-- Location: MLABCELL_X23_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[8]_NEW2062\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[8]_OTERM2063\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(8))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(8) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(8))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(8)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[8]_OTERM2063\); + +-- Location: FF_X23_Y17_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[8]_OTERM2063\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(8)); + +-- Location: FF_X28_Y16_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(8)); + +-- Location: LABCELL_X24_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[8]~feeder_combout\); + +-- Location: FF_X24_Y14_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(8)); + +-- Location: FF_X28_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(8)); + +-- Location: MLABCELL_X28_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[8]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(8) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[8]~feeder_combout\); + +-- Location: FF_X28_Y16_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(8)); + +-- Location: MLABCELL_X28_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(8) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(8)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(8)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(8) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(8))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(8) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(8) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(8) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(8)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(8) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(8))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011101001100110001110111001100000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~0_combout\); + +-- Location: FF_X24_Y16_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(8)); + +-- Location: LABCELL_X25_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[8]~feeder_combout\); + +-- Location: FF_X25_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(8)); + +-- Location: LABCELL_X24_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[8]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(8) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[8]~feeder_combout\); + +-- Location: FF_X24_Y16_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(8)); + +-- Location: FF_X24_Y16_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(8)); + +-- Location: LABCELL_X24_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(8) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(8)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(8)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~1_combout\); + +-- Location: LABCELL_X35_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux401~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux401~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~2_combout\); + +-- Location: FF_X35_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(8)); + +-- Location: MLABCELL_X34_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060_RESYN12832\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011111110000100001111111000110000111111000011000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\); + +-- Location: MLABCELL_X34_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_OTERM2061\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001010001011111111010111011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_OTERM2061\); + +-- Location: FF_X34_Y23_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_OTERM2061\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8)); + +-- Location: FF_X35_Y19_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(8)); + +-- Location: MLABCELL_X37_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[8]~feeder_combout\); + +-- Location: FF_X37_Y15_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(8)); + +-- Location: LABCELL_X39_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[8]~feeder_combout\); + +-- Location: FF_X39_Y19_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(8)); + +-- Location: FF_X39_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(8)); + +-- Location: LABCELL_X39_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(8) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(8)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(8)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~1_combout\); + +-- Location: MLABCELL_X34_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[8]~feeder_combout\); + +-- Location: FF_X34_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(8)); + +-- Location: MLABCELL_X34_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[8]~feeder_combout\); + +-- Location: FF_X34_Y16_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(8)); + +-- Location: LABCELL_X35_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[8]~feeder_combout\); + +-- Location: FF_X35_Y16_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(8)); + +-- Location: FF_X34_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(8)); + +-- Location: MLABCELL_X34_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(8) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(8))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(8))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~0_combout\); + +-- Location: LABCELL_X35_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux339~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux339~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~2_combout\); + +-- Location: FF_X35_Y16_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(8)); + +-- Location: LABCELL_X20_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[8]_NEW2058\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[8]_OTERM2059\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(8)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(8)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[8]_OTERM2059\); + +-- Location: FF_X20_Y16_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[8]_OTERM2059\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8)); + +-- Location: LABCELL_X24_Y16_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[8]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[8]~feeder_combout\); + +-- Location: FF_X24_Y16_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(8)); + +-- Location: LABCELL_X25_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(8), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[8]~feeder_combout\); + +-- Location: FF_X25_Y16_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[8]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(8)); + +-- Location: FF_X24_Y16_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(8)); + +-- Location: FF_X24_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(8)); + +-- Location: LABCELL_X24_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(8)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(8)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(8)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~1_combout\); + +-- Location: FF_X29_Y16_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(8)); + +-- Location: FF_X29_Y16_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(8)); + +-- Location: FF_X34_Y16_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(8)); + +-- Location: FF_X29_Y16_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(8)); + +-- Location: LABCELL_X29_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(8) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(8) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(8) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(8) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(8), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~0_combout\); + +-- Location: LABCELL_X35_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux369~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux369~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~2_combout\); + +-- Location: FF_X35_Y16_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(8)); + +-- Location: FF_X32_Y25_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_NEW_REG494\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM495\); + +-- Location: LABCELL_X32_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]~4_combout\); + +-- Location: FF_X32_Y25_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG486\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM487\); + +-- Location: LABCELL_X35_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~0_combout\); + +-- Location: LABCELL_X39_Y25_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000000000000110000000000000111000000000000011100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~0_combout\); + +-- Location: FF_X39_Y25_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_NEW_REG496\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM497\); + +-- Location: LABCELL_X36_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111001100110101010111111111000011110011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~2_combout\); + +-- Location: MLABCELL_X37_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110000111101010011000000000101001111111111010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~1_combout\); + +-- Location: FF_X28_Y17_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(8)); + +-- Location: MLABCELL_X28_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(8) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(8) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100001111000011110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(8), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~3_combout\); + +-- Location: LABCELL_X39_Y25_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~4_RTM0500\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~4_RTM0500_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~3_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~1_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111000000000010011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~4_RTM0500_combout\); + +-- Location: FF_X39_Y25_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_NEW_REG498\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~4_RTM0500_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM499\); + +-- Location: LABCELL_X39_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM499\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM499\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM499\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM497\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM495\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM499\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM495\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM487\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM497\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001111100011111010111110101111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM495\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM487\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM497\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM485\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM499\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\); + +-- Location: FF_X40_Y22_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(40)); + +-- Location: LABCELL_X40_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[40]~feeder_combout\); + +-- Location: FF_X40_Y23_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(40)); + +-- Location: FF_X40_Y22_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(40)); + +-- Location: FF_X40_Y22_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(40)); + +-- Location: LABCELL_X40_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(40)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(40))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(40)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(40))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(40)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(40) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(40)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(40), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(40), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(40), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~0_combout\); + +-- Location: FF_X39_Y25_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(40)); + +-- Location: LABCELL_X41_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[40]~feeder_combout\); + +-- Location: FF_X41_Y19_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(40)); + +-- Location: LABCELL_X41_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[40]~feeder_combout\); + +-- Location: FF_X41_Y19_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(40)); + +-- Location: FF_X41_Y19_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(40)); + +-- Location: LABCELL_X41_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(40)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(40) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(40) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(40))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(40)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(40))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(40)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(40), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(40), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(40), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~1_combout\); + +-- Location: LABCELL_X44_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux53~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux53~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~2_combout\); + +-- Location: FF_X44_Y20_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(40)); + +-- Location: FF_X42_Y28_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_OTERM2441\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(40)); + +-- Location: LABCELL_X40_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~2_combout\); + +-- Location: MLABCELL_X37_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~1_combout\); + +-- Location: LABCELL_X40_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~3_combout\); + +-- Location: LABCELL_X40_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~0_combout\); + +-- Location: LABCELL_X39_Y31_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13166\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ +-- & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~0_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~2_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000010001000011001101110100111111000100010011111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\); + +-- Location: LABCELL_X43_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~5_combout\); + +-- Location: LABCELL_X43_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~8_combout\); + +-- Location: LABCELL_X43_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~6_combout\); + +-- Location: LABCELL_X44_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~7_combout\); + +-- Location: LABCELL_X44_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)))) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~8_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~5_combout\)))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101010000111100110101111100000011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~9_combout\); + +-- Location: MLABCELL_X42_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13168\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(40))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(40))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(40))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(40) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100001011111110111111000100001011111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(40), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\); + +-- Location: MLABCELL_X42_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_OTERM2441\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(40) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_OTERM2441\); + +-- Location: FF_X42_Y28_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_OTERM2441\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE_q\); + +-- Location: LABCELL_X48_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[40]~feeder_combout\); + +-- Location: FF_X48_Y18_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(40)); + +-- Location: FF_X48_Y20_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(40)); + +-- Location: FF_X48_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(40)); + +-- Location: LABCELL_X48_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[40]~feeder_combout\); + +-- Location: FF_X48_Y18_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(40)); + +-- Location: LABCELL_X48_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(40) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(40)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(40)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(40) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(40) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(40))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(40) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(40) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(40) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(40)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(40) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(40)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(40))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011101001100110001110111001100000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(40), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(40), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(40), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~0_combout\); + +-- Location: LABCELL_X43_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[40]~feeder_combout\); + +-- Location: FF_X43_Y22_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(40)); + +-- Location: LABCELL_X43_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[40]~feeder_combout\); + +-- Location: FF_X43_Y22_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(40)); + +-- Location: FF_X44_Y20_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(40)); + +-- Location: FF_X44_Y20_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(40)); + +-- Location: LABCELL_X44_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(40) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(40)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(40)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(40) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(40) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(40))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(40) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(40) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(40) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(40)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(40) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(40)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(40))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100000000000111010011001100011101110011000001110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(40), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(40), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(40), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~1_combout\); + +-- Location: LABCELL_X44_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux245~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux245~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~2_combout\); + +-- Location: FF_X44_Y20_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(40)); + +-- Location: LABCELL_X36_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~0_combout\); + +-- Location: MLABCELL_X37_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000010100000101000010001101110110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~1_combout\); + +-- Location: MLABCELL_X37_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13158\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13158_BDD13159\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011010101010000000000000011000000110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1470~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1470~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13158_BDD13159\); + +-- Location: FF_X43_Y30_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_OTERM2437\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13160\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13158_BDD13159\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13158_BDD13159\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110011000000001111001100001100111111110000110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]_NEW2436_RESYN13158_BDD13159\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\); + +-- Location: LABCELL_X43_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_OTERM2437\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000001110111011111110100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_OTERM2437\); + +-- Location: FF_X43_Y30_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_OTERM2437\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40)); + +-- Location: LABCELL_X50_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(40), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[40]~feeder_combout\); + +-- Location: FF_X50_Y20_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(40)); + +-- Location: LABCELL_X50_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(40), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[40]~feeder_combout\); + +-- Location: FF_X50_Y20_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(40)); + +-- Location: LABCELL_X44_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(40), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[40]~feeder_combout\); + +-- Location: FF_X44_Y22_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(40)); + +-- Location: FF_X50_Y20_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(40)); + +-- Location: LABCELL_X50_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(40)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(40) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(40) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(40))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(40)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(40))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(40)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(40), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(40), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(40), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~0_combout\); + +-- Location: MLABCELL_X49_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(40), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[40]~feeder_combout\); + +-- Location: FF_X49_Y20_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(40)); + +-- Location: LABCELL_X47_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(40), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[40]~feeder_combout\); + +-- Location: FF_X47_Y23_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(40)); + +-- Location: FF_X44_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(40)); + +-- Location: FF_X44_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(40)); + +-- Location: LABCELL_X44_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(40) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(40)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(40)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(40) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(40) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(40))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(40) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(40) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(40) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(40)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(40) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(40)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(40))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100000000000111010011001100011101110011000001110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(40), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(40), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(40), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~1_combout\); + +-- Location: LABCELL_X44_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux117~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux117~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~2_combout\); + +-- Location: FF_X44_Y20_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(40)); + +-- Location: FF_X42_Y28_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_OTERM2439\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(40)); + +-- Location: LABCELL_X40_Y30_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010101010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\); + +-- Location: LABCELL_X39_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\); + +-- Location: LABCELL_X43_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~6_combout\); + +-- Location: LABCELL_X44_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~7_combout\); + +-- Location: LABCELL_X39_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000011111111111111111111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\); + +-- Location: LABCELL_X43_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~5_combout\); + +-- Location: LABCELL_X39_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\); + +-- Location: LABCELL_X43_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~8_combout\); + +-- Location: LABCELL_X43_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~5_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~7_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~8_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111001101010011010111110000111111110011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~9_combout\); + +-- Location: MLABCELL_X42_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~2_combout\); + +-- Location: MLABCELL_X42_Y32_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][8]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~1_combout\); + +-- Location: MLABCELL_X42_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~0_combout\); + +-- Location: MLABCELL_X42_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][8]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~3_combout\); + +-- Location: LABCELL_X43_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~3_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~2_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~2_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110001001010001011100110100100011101010110110011111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~4_combout\); + +-- Location: MLABCELL_X42_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13162\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13162_BDD13163\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~4_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~9_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101100000000001010110001010011111111110101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13162_BDD13163\); + +-- Location: MLABCELL_X42_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13164\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13162_BDD13163\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(40)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13162_BDD13163\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(40))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000100000000000100010010111011111111111011101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]_NEW2438_RESYN13162_BDD13163\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\); + +-- Location: MLABCELL_X42_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_OTERM2439\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(40) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_OTERM2439\); + +-- Location: FF_X42_Y28_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_OTERM2439\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE_q\); + +-- Location: MLABCELL_X45_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[40]~feeder_combout\); + +-- Location: FF_X45_Y22_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(40)); + +-- Location: MLABCELL_X45_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[40]~feeder_combout\); + +-- Location: FF_X45_Y22_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(40)); + +-- Location: FF_X45_Y22_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(40)); + +-- Location: LABCELL_X43_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[40]~feeder_combout\); + +-- Location: FF_X43_Y27_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(40)); + +-- Location: MLABCELL_X45_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(40) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(40)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(40))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(40) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(40)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(40) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(40) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(40) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(40) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(40))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(40) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(40) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(40) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(40) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000011010111110000001101010000111100110101111111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(40), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(40), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(40), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~0_combout\); + +-- Location: LABCELL_X48_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[40]~feeder_combout\); + +-- Location: FF_X48_Y21_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(40)); + +-- Location: LABCELL_X43_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[40]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[40]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[40]~feeder_combout\); + +-- Location: FF_X43_Y27_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[40]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(40)); + +-- Location: FF_X44_Y20_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(40)); + +-- Location: FF_X44_Y20_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(40)); + +-- Location: LABCELL_X44_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(40) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(40) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(40)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(40)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(40) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(40) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(40))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(40) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(40) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(40) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(40)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(40) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(40) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(40)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(40))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101010000111100110101111100000011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(40), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(40), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(40), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~1_combout\); + +-- Location: LABCELL_X44_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000110111011101110111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux181~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux181~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~2_combout\); + +-- Location: FF_X44_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(40)); + +-- Location: LABCELL_X44_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(40) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(40) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(40) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(40) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(40), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(40), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(40), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(40), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~0_combout\); + +-- Location: LABCELL_X35_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(8)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(8) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(8)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(8)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(8), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(8), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~1_combout\); + +-- Location: LABCELL_X35_Y12_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(32) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(8))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(32) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(8))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(32) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(8))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(32) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(8))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000100101001010100010111101110000011101010111101001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(36), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(8), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(32), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~2_combout\); + +-- Location: LABCELL_X35_Y12_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[40]_NEW1792\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[40]_OTERM1793\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(40))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(39))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(40))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(39)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(39), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(40), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[40]_OTERM1793\); + +-- Location: FF_X35_Y12_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[40]_OTERM1793\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(40)); + +-- Location: LABCELL_X29_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[9]_NEW1958\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[9]_OTERM1959\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(9))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[9]_OTERM1959\); + +-- Location: FF_X29_Y19_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[9]_OTERM1959\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(9)); + +-- Location: LABCELL_X29_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(9) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[9]~feeder_combout\); + +-- Location: FF_X29_Y13_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(9)); + +-- Location: FF_X28_Y13_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(9)); + +-- Location: FF_X29_Y13_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(9)); + +-- Location: LABCELL_X29_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(9) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[9]~feeder_combout\); + +-- Location: FF_X29_Y13_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(9)); + +-- Location: LABCELL_X29_Y13_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(9) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(9))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(9))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(9) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(9) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(9) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(9))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(9)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010011000011110101001111110000010100111111111101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~0_combout\); + +-- Location: MLABCELL_X34_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(9) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[9]~feeder_combout\); + +-- Location: FF_X34_Y14_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(9)); + +-- Location: LABCELL_X32_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(9) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[9]~feeder_combout\); + +-- Location: FF_X32_Y14_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(9)); + +-- Location: MLABCELL_X34_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(9) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[9]~feeder_combout\); + +-- Location: FF_X34_Y14_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(9)); + +-- Location: FF_X34_Y14_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(9)); + +-- Location: MLABCELL_X34_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(9)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(9)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(9)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(9)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~1_combout\); + +-- Location: MLABCELL_X34_Y13_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010111110101111101011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux314~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux314~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~2_combout\); + +-- Location: FF_X34_Y13_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(9)); + +-- Location: LABCELL_X29_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042_RESYN12826\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011111110000100001111111000110000111111000011000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\); + +-- Location: LABCELL_X29_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_OTERM2043\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001000110011111111011100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_OTERM2043\); + +-- Location: FF_X29_Y20_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_OTERM2043\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9)); + +-- Location: LABCELL_X35_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[9]~feeder_combout\); + +-- Location: FF_X35_Y18_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(9)); + +-- Location: FF_X29_Y15_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(9)); + +-- Location: FF_X29_Y15_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(9)); + +-- Location: FF_X29_Y15_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(9)); + +-- Location: LABCELL_X29_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(9)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(9)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(9)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(9)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~1_combout\); + +-- Location: FF_X34_Y16_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(9)); + +-- Location: FF_X31_Y16_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(9)); + +-- Location: FF_X34_Y18_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(9)); + +-- Location: FF_X31_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(9)); + +-- Location: LABCELL_X31_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(9)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(9)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(9)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(9)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~0_combout\); + +-- Location: LABCELL_X31_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux338~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux338~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~2_combout\); + +-- Location: FF_X31_Y16_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(9)); + +-- Location: MLABCELL_X23_Y16_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[9]_NEW2040\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[9]_OTERM2041\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(9)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(9)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[9]_OTERM2041\); + +-- Location: FF_X23_Y16_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[9]_OTERM2041\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9)); + +-- Location: LABCELL_X31_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[9]~feeder_combout\); + +-- Location: FF_X31_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(9)); + +-- Location: FF_X28_Y16_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(9)); + +-- Location: FF_X31_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(9)); + +-- Location: MLABCELL_X28_Y14_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[9]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[9]~feeder_combout\); + +-- Location: FF_X28_Y14_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(9)); + +-- Location: LABCELL_X31_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(9) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(9) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(9)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(9) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(9))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(9) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(9))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101011111000000110101000011110011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~0_combout\); + +-- Location: FF_X29_Y15_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(9)); + +-- Location: FF_X28_Y15_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(9)); + +-- Location: FF_X29_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(9)); + +-- Location: FF_X29_Y15_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(9)); + +-- Location: LABCELL_X29_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(9)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(9) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(9)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(9)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~1_combout\); + +-- Location: LABCELL_X32_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux368~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux368~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~2_combout\); + +-- Location: FF_X32_Y17_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(9)); + +-- Location: MLABCELL_X23_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[9]_NEW2044\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[9]_OTERM2045\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(9))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(9))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(9) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(9)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[9]_OTERM2045\); + +-- Location: FF_X23_Y17_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[9]_OTERM2045\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(9)); + +-- Location: FF_X35_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(9)); + +-- Location: FF_X24_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(9)); + +-- Location: FF_X35_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(9)); + +-- Location: LABCELL_X35_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[9]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(9) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[9]~feeder_combout\); + +-- Location: FF_X35_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(9)); + +-- Location: LABCELL_X35_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(9) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(9)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(9))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(9) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(9)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(9)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001001010111010100101010011110100010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(9), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~1_combout\); + +-- Location: FF_X24_Y14_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(9)); + +-- Location: FF_X29_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(9)); + +-- Location: FF_X29_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(9)); + +-- Location: FF_X29_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(9), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(9)); + +-- Location: LABCELL_X29_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(9)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(9)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(9)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(9)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010010101011111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(9), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~0_combout\); + +-- Location: LABCELL_X32_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux400~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux400~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~2_combout\); + +-- Location: FF_X32_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(9)); + +-- Location: FF_X29_Y27_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_NEW_REG130\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM131\); + +-- Location: LABCELL_X31_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111000000001010101000100111001001110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~3_combout\); + +-- Location: LABCELL_X40_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~0_combout\); + +-- Location: MLABCELL_X28_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~3_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011100010100000101110001010011010111110101001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(9), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~4_combout\); + +-- Location: LABCELL_X31_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011110000000000000000000000001111111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~1_combout\); + +-- Location: FF_X31_Y27_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_NEW_REG134\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM135\); + +-- Location: LABCELL_X26_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[9]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[9]~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[9]~feeder_combout\); + +-- Location: FF_X26_Y17_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[9]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(9)); + +-- Location: FF_X35_Y27_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_NEW_REG132\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(9), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM133\); + +-- Location: LABCELL_X41_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM133\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM135\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM131\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM133\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM135\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM133\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM131\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM135\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM133\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM135\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010011110100111100111111001111110111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM131\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM107\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM135\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM133\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\); + +-- Location: LABCELL_X47_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[41]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[41]~feeder_combout\); + +-- Location: FF_X47_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[41]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(41)); + +-- Location: LABCELL_X47_Y31_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[41]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[41]~feeder_combout\); + +-- Location: FF_X47_Y31_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[41]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(41)); + +-- Location: LABCELL_X52_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[41]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[41]~feeder_combout\); + +-- Location: FF_X52_Y26_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[41]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(41)); + +-- Location: FF_X47_Y31_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(41)); + +-- Location: LABCELL_X47_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(41)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(41) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(41) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(41)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(41))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(41)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(41))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(41), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(41), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(41), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~0_combout\); + +-- Location: FF_X45_Y29_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(41)); + +-- Location: LABCELL_X41_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[41]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[41]~feeder_combout\); + +-- Location: FF_X41_Y25_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[41]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(41)); + +-- Location: FF_X41_Y25_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(41)); + +-- Location: FF_X41_Y25_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(41)); + +-- Location: LABCELL_X41_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(41)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(41) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(41) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(41)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(41))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(41)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(41))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(41), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(41), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(41), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~1_combout\); + +-- Location: MLABCELL_X42_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux52~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux52~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~2_combout\); + +-- Location: FF_X42_Y25_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(41)); + +-- Location: FF_X43_Y30_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_OTERM2425\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(41)); + +-- Location: LABCELL_X40_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~0_combout\); + +-- Location: LABCELL_X39_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~3_combout\); + +-- Location: LABCELL_X39_Y30_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~1_combout\); + +-- Location: LABCELL_X39_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001110111011101110100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~2_combout\); + +-- Location: LABCELL_X39_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13134\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~3_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010101110110000101000010001010111111011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\); + +-- Location: LABCELL_X39_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~8_combout\); + +-- Location: LABCELL_X39_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~6_combout\); + +-- Location: LABCELL_X39_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~5_combout\); + +-- Location: LABCELL_X40_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~7_combout\); + +-- Location: LABCELL_X39_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~8_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100000000111100111101110111011101110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~9_combout\); + +-- Location: LABCELL_X43_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13136\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(41))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(41))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(41))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(41) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100001011111110111111000100001011111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(41), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\); + +-- Location: LABCELL_X43_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_OTERM2425\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(41) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001110111111101110100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_OTERM2425\); + +-- Location: FF_X43_Y30_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_OTERM2425\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE_q\); + +-- Location: LABCELL_X47_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[41]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[41]~feeder_combout\); + +-- Location: FF_X47_Y16_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[41]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(41)); + +-- Location: LABCELL_X48_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[41]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[41]~feeder_combout\); + +-- Location: FF_X48_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[41]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(41)); + +-- Location: LABCELL_X48_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[41]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[41]~feeder_combout\); + +-- Location: FF_X48_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[41]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(41)); + +-- Location: FF_X48_Y16_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(41)); + +-- Location: LABCELL_X48_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(41)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(41) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(41)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(41))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(41)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(41))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(41)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(41), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(41), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(41), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~1_combout\); + +-- Location: MLABCELL_X42_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[41]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[41]~feeder_combout\); + +-- Location: FF_X42_Y21_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[41]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(41)); + +-- Location: FF_X48_Y21_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(41)); + +-- Location: FF_X42_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(41)); + +-- Location: FF_X42_Y21_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(41)); + +-- Location: MLABCELL_X42_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(41))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(41)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(41))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(41)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(41)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(41) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(41) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(41), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(41), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(41), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~0_combout\); + +-- Location: MLABCELL_X42_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux244~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux244~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~2_combout\); + +-- Location: FF_X42_Y21_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(41)); + +-- Location: LABCELL_X31_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~0_combout\); + +-- Location: LABCELL_X40_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~1_combout\); + +-- Location: LABCELL_X31_Y34_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13126\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~1_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110101000000000011000000000101001101010000111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1469~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1469~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\); + +-- Location: LABCELL_X31_Y34_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13128\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000110000001100001111000011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(41), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\); + +-- Location: LABCELL_X31_Y34_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_OTERM2421\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000001101110111111101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_OTERM2421\); + +-- Location: FF_X31_Y34_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_OTERM2421\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41)); + +-- Location: MLABCELL_X42_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[41]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(41), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[41]~feeder_combout\); + +-- Location: FF_X42_Y20_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[41]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(41)); + +-- Location: FF_X41_Y20_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(41)); + +-- Location: FF_X42_Y20_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(41)); + +-- Location: FF_X42_Y20_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(41)); + +-- Location: MLABCELL_X42_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(41)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(41) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(41) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(41))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(41)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(41))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(41)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(41), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(41), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(41), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~1_combout\); + +-- Location: FF_X42_Y21_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(41)); + +-- Location: LABCELL_X41_Y18_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[41]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(41), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[41]~feeder_combout\); + +-- Location: FF_X41_Y18_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[41]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(41)); + +-- Location: FF_X42_Y21_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(41)); + +-- Location: MLABCELL_X37_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[41]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(41), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[41]~feeder_combout\); + +-- Location: FF_X37_Y22_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[41]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(41)); + +-- Location: MLABCELL_X42_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(41) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(41)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(41)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(41) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(41) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(41)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(41))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(41) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(41) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(41)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(41))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(41) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(41) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(41)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(41))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100001101001111010000000111110001110011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(41), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(41), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(41), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~0_combout\); + +-- Location: MLABCELL_X42_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux116~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux116~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~2_combout\); + +-- Location: FF_X42_Y21_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(41)); + +-- Location: LABCELL_X40_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~0_combout\); + +-- Location: LABCELL_X39_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~2_combout\); + +-- Location: LABCELL_X40_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~1_combout\); + +-- Location: LABCELL_X39_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~3_combout\); + +-- Location: LABCELL_X40_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~2_combout\)))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~2_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~0_combout\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~2_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~3_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~2_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101100011001001110100100110001101111010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~4_combout\); + +-- Location: LABCELL_X39_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~5_combout\); + +-- Location: LABCELL_X39_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~8_combout\); + +-- Location: LABCELL_X39_Y32_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][9]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~6_combout\); + +-- Location: LABCELL_X40_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~7_combout\); + +-- Location: LABCELL_X39_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~5_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~9_combout\); + +-- Location: LABCELL_X40_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13130\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13130_BDD13131\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000111000000100000011111011111100011111101111110001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13130_BDD13131\); + +-- Location: FF_X40_Y26_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_OTERM2423\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(41)); + +-- Location: LABCELL_X40_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13132\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(41) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13130_BDD13131\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(41) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13130_BDD13131\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]_NEW2422_RESYN13130_BDD13131\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(41), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\); + +-- Location: LABCELL_X40_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_OTERM2423\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(41) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011110111111100111100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_OTERM2423\); + +-- Location: FF_X40_Y26_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_OTERM2423\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[41]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[41]~feeder_combout\); + +-- Location: FF_X41_Y25_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[41]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(41)); + +-- Location: FF_X41_Y25_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(41)); + +-- Location: FF_X41_Y25_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(41)); + +-- Location: FF_X42_Y22_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(41)); + +-- Location: LABCELL_X41_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(41) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(41))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(41))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(41) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(41) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(41)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(41) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(41) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(41) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(41))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(41) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(41))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(41)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000000001001110101010100100111101010100010011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(41), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(41), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(41), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~1_combout\); + +-- Location: FF_X42_Y21_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(41)); + +-- Location: FF_X44_Y21_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(41)); + +-- Location: LABCELL_X43_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[41]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[41]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[41]~feeder_combout\); + +-- Location: FF_X43_Y21_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[41]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(41)); + +-- Location: FF_X42_Y21_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(41)); + +-- Location: MLABCELL_X42_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(41))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(41)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(41))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(41)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(41)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(41) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(41)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(41), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(41), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(41), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~0_combout\); + +-- Location: MLABCELL_X42_Y21_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux180~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux180~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~2_combout\); + +-- Location: FF_X42_Y21_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(41)); + +-- Location: MLABCELL_X42_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(41) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(41) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(41) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(41) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(41), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(41), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(41), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(41), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~0_combout\); + +-- Location: LABCELL_X32_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(9) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(9)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(9)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(9) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(9)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010001000100101111101110111000010100111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(9), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(9), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~1_combout\); + +-- Location: LABCELL_X35_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(37) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(9))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(37) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(9)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(37) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(9)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(37) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(9)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101101110110000010100010001101011111011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(33), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(9), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(37), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~2_combout\); + +-- Location: LABCELL_X35_Y13_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[41]_NEW1790\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[41]_OTERM1791\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(41))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(40))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(41))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(40)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(40), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[41]_OTERM1791\); + +-- Location: FF_X35_Y13_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[41]_OTERM1791\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(41)); + +-- Location: LABCELL_X29_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[10]_NEW1962\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[10]_OTERM1963\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(10))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[10]_OTERM1963\); + +-- Location: FF_X29_Y19_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[10]_OTERM1963\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(10)); + +-- Location: MLABCELL_X28_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[10]~feeder_combout\); + +-- Location: FF_X28_Y13_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(10)); + +-- Location: FF_X29_Y13_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(10)); + +-- Location: FF_X29_Y13_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(10)); + +-- Location: FF_X29_Y13_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(10)); + +-- Location: LABCELL_X29_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(10))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(10))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~0_combout\); + +-- Location: LABCELL_X36_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[10]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(10) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[10]~feeder_combout\); + +-- Location: FF_X36_Y13_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(10)); + +-- Location: MLABCELL_X37_Y15_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[10]~feeder_combout\); + +-- Location: FF_X37_Y15_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(10)); + +-- Location: LABCELL_X31_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[10]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(10) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[10]~feeder_combout\); + +-- Location: FF_X31_Y13_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(10)); + +-- Location: FF_X36_Y13_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(10)); + +-- Location: LABCELL_X36_Y13_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(10)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(10)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(10)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(10)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~1_combout\); + +-- Location: MLABCELL_X34_Y13_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux313~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux313~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~2_combout\); + +-- Location: FF_X34_Y13_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(10)); + +-- Location: LABCELL_X29_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054_RESYN12830\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001001111111111000100111111111100000000111011000000000011101100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\); + +-- Location: LABCELL_X29_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_OTERM2055\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001000110011111111011100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_OTERM2055\); + +-- Location: FF_X29_Y20_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_OTERM2055\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10)); + +-- Location: MLABCELL_X34_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[10]~feeder_combout\); + +-- Location: FF_X34_Y16_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(10)); + +-- Location: FF_X32_Y18_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(10)); + +-- Location: MLABCELL_X34_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[10]~feeder_combout\); + +-- Location: FF_X34_Y18_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(10)); + +-- Location: FF_X32_Y18_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(10)); + +-- Location: LABCELL_X32_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(10)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(10)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~0_combout\); + +-- Location: LABCELL_X35_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[10]~feeder_combout\); + +-- Location: FF_X35_Y15_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(10)); + +-- Location: FF_X29_Y15_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(10)); + +-- Location: MLABCELL_X37_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[10]~feeder_combout\); + +-- Location: FF_X37_Y15_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(10)); + +-- Location: FF_X35_Y15_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(10)); + +-- Location: LABCELL_X35_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(10))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(10))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~1_combout\); + +-- Location: LABCELL_X32_Y15_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux337~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux337~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~2_combout\); + +-- Location: FF_X32_Y15_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(10)); + +-- Location: FF_X20_Y18_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(10)); + +-- Location: LABCELL_X24_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[10]_NEW2056\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[10]_OTERM2057\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(10))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(10) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(10)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[10]_OTERM2057\); + +-- Location: FF_X24_Y17_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[10]_OTERM2057\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(10)); + +-- Location: LABCELL_X26_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[10]~feeder_combout\); + +-- Location: FF_X26_Y15_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(10)); + +-- Location: FF_X26_Y15_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(10)); + +-- Location: FF_X25_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(10)); + +-- Location: FF_X25_Y15_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(10)); + +-- Location: LABCELL_X25_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(10)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(10)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(10))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(10))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~1_combout\); + +-- Location: MLABCELL_X28_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[10]~feeder_combout\); + +-- Location: FF_X28_Y16_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(10)); + +-- Location: LABCELL_X26_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[10]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(10) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[10]~feeder_combout\); + +-- Location: FF_X26_Y16_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(10)); + +-- Location: MLABCELL_X28_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[10]~feeder_combout\); + +-- Location: FF_X28_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(10)); + +-- Location: FF_X28_Y16_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(10)); + +-- Location: MLABCELL_X28_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(10)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(10)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~0_combout\); + +-- Location: LABCELL_X31_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux399~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux399~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~2_combout\); + +-- Location: FF_X31_Y15_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(10)); + +-- Location: MLABCELL_X23_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[10]_NEW2052\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[10]_OTERM2053\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(10))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(10))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[10]_OTERM2053\); + +-- Location: FF_X23_Y15_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[10]_OTERM2053\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10)); + +-- Location: FF_X31_Y13_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(10)); + +-- Location: LABCELL_X32_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[10]~feeder_combout\); + +-- Location: FF_X32_Y13_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(10)); + +-- Location: LABCELL_X31_Y13_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[10]~feeder_combout\); + +-- Location: FF_X31_Y13_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[10]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(10)); + +-- Location: FF_X32_Y13_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(10)); + +-- Location: LABCELL_X32_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(10))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(10))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~1_combout\); + +-- Location: FF_X28_Y14_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(10)); + +-- Location: FF_X28_Y14_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(10)); + +-- Location: FF_X29_Y14_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(10)); + +-- Location: FF_X29_Y14_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(10)); + +-- Location: LABCELL_X29_Y14_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(10)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(10)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(10)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(10)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~0_combout\); + +-- Location: LABCELL_X32_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux367~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux367~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~2_combout\); + +-- Location: FF_X32_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(10)); + +-- Location: LABCELL_X36_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~2_combout\); + +-- Location: MLABCELL_X37_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~0_combout\); + +-- Location: MLABCELL_X37_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~3_combout\); + +-- Location: LABCELL_X36_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~1_combout\); + +-- Location: LABCELL_X36_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13154\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~2_combout\)))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101001000110110011110001001110011011010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\); + +-- Location: LABCELL_X41_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~8_combout\); + +-- Location: LABCELL_X41_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~7_combout\); + +-- Location: MLABCELL_X42_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~5_combout\); + +-- Location: MLABCELL_X42_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~6_combout\); + +-- Location: LABCELL_X36_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~7_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~7_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~7_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010011101110000101000100010010111110111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~9_combout\); + +-- Location: LABCELL_X36_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13156\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100001011111110111111000100001011111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(42), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\); + +-- Location: LABCELL_X36_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_OTERM2435\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011110111001111111100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_OTERM2435\); + +-- Location: FF_X36_Y30_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_OTERM2435\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42)); + +-- Location: MLABCELL_X42_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[42]~feeder_combout\); + +-- Location: FF_X42_Y20_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(42)); + +-- Location: LABCELL_X43_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[42]~feeder_combout\); + +-- Location: FF_X43_Y18_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(42)); + +-- Location: FF_X43_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(42)); + +-- Location: FF_X42_Y20_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(42)); + +-- Location: LABCELL_X43_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(42) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(42) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(42))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(42)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(42) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(42) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(42))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(42))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(42) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(42))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000101011001110100100110101011100011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(42), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(42), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~1_combout\); + +-- Location: MLABCELL_X45_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[42]~feeder_combout\); + +-- Location: FF_X45_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(42)); + +-- Location: LABCELL_X43_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[42]~feeder_combout\); + +-- Location: FF_X43_Y18_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(42)); + +-- Location: MLABCELL_X45_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[42]~feeder_combout\); + +-- Location: FF_X45_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(42)); + +-- Location: FF_X45_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(42)); + +-- Location: MLABCELL_X45_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(42))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(42))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(42) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(42)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(42) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(42), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(42), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(42), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~0_combout\); + +-- Location: MLABCELL_X42_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux243~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux243~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~2_combout\); + +-- Location: FF_X42_Y15_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(42)); + +-- Location: MLABCELL_X42_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\)) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~5_combout\); + +-- Location: MLABCELL_X42_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~6_combout\); + +-- Location: LABCELL_X41_Y32_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~8_combout\); + +-- Location: LABCELL_X41_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~7_combout\); + +-- Location: MLABCELL_X42_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~5_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~6_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~8_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~5_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000001010000010100010001101110111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~9_combout\); + +-- Location: MLABCELL_X37_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~1_combout\); + +-- Location: MLABCELL_X37_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~3_combout\); + +-- Location: LABCELL_X36_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~2_combout\); + +-- Location: MLABCELL_X37_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~0_combout\); + +-- Location: MLABCELL_X37_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~3_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~3_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~3_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010001000100101111101110111000010100111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~4_combout\); + +-- Location: LABCELL_X43_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13150\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~4_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110010101100101000110101001101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\); + +-- Location: LABCELL_X44_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13152\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110111011101101000100010001001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\); + +-- Location: LABCELL_X44_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_OTERM2433\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_OTERM2433\); + +-- Location: FF_X44_Y27_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_OTERM2433\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42)); + +-- Location: LABCELL_X40_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[42]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[42]~feeder_combout\); + +-- Location: FF_X40_Y15_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(42)); + +-- Location: LABCELL_X41_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[42]~feeder_combout\); + +-- Location: FF_X41_Y15_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(42)); + +-- Location: FF_X41_Y15_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(42)); + +-- Location: LABCELL_X40_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[42]~feeder_combout\); + +-- Location: FF_X40_Y15_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(42)); + +-- Location: LABCELL_X41_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(42) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(42) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(42))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(42))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(42))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100000001111100011100110100111101000011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(42), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(42), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~1_combout\); + +-- Location: LABCELL_X43_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[42]~feeder_combout\); + +-- Location: FF_X43_Y17_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(42)); + +-- Location: FF_X43_Y15_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(42)); + +-- Location: FF_X43_Y15_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(42)); + +-- Location: LABCELL_X44_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[42]~feeder_combout\); + +-- Location: FF_X44_Y15_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(42)); + +-- Location: LABCELL_X43_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(42) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(42)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(42)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(42) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(42)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(42))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(42)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(42))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(42) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(42))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101010001000010110101101110100001111100011010101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(42), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(42), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~0_combout\); + +-- Location: MLABCELL_X42_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux179~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux179~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~2_combout\); + +-- Location: FF_X42_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(42)); + +-- Location: LABCELL_X36_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100110000111101010011111100000101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~1_combout\); + +-- Location: LABCELL_X41_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000011110101010111111111001100110000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~0_combout\); + +-- Location: LABCELL_X36_Y23_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13146\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13146_BDD13147\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~1_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~1_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~1_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101001001100011011110001100100111011010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1468~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1468~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13146_BDD13147\); + +-- Location: FF_X36_Y23_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_OTERM2431\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(42)); + +-- Location: LABCELL_X36_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13148\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(42) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13146_BDD13147\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(42) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13146_BDD13147\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110101000000001111010100001010111111110000101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]_NEW2430_RESYN13146_BDD13147\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\); + +-- Location: LABCELL_X36_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_OTERM2431\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(42) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000101111101111111010100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_OTERM2431\); + +-- Location: FF_X36_Y23_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_OTERM2431\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[42]~feeder_combout\); + +-- Location: FF_X41_Y15_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(42)); + +-- Location: LABCELL_X40_Y15_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[42]~feeder_combout\); + +-- Location: FF_X40_Y15_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(42)); + +-- Location: FF_X41_Y15_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(42)); + +-- Location: FF_X40_Y15_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(42)); + +-- Location: LABCELL_X41_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(42) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(42))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(42))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(42) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(42))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(42)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(42))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(42)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(42))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(42)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010001000100101111101110111000010100111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(42), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(42), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~1_combout\); + +-- Location: LABCELL_X39_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[42]~feeder_combout\); + +-- Location: FF_X39_Y11_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(42)); + +-- Location: LABCELL_X40_Y13_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[42]~feeder_combout\); + +-- Location: FF_X40_Y13_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(42)); + +-- Location: FF_X39_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(42)); + +-- Location: FF_X39_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(42)); + +-- Location: LABCELL_X39_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(42) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(42) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(42))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(42))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(42))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001111110101000000110000010111110011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(42), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(42), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~0_combout\); + +-- Location: LABCELL_X39_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux115~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux115~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~2_combout\); + +-- Location: FF_X39_Y15_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(42)); + +-- Location: FF_X36_Y31_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(10)); + +-- Location: LABCELL_X36_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(10) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(10) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010000000000000101000000001111010111110000111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(10), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~5_combout\); + +-- Location: LABCELL_X41_Y32_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\)))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\)))) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111101010100010011101010101001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~1_combout\); + +-- Location: LABCELL_X36_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100010001000000111101110111001111000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~0_combout\); + +-- Location: LABCELL_X36_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(10) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~0_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~0_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~0_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010101000100000001010100010000000101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~4_combout\); + +-- Location: MLABCELL_X37_Y27_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~2_RTM0152\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~2_RTM0152_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~5_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~5_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010111110101111000011111010111100001111101011110000111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~2_RTM0152_combout\); + +-- Location: FF_X37_Y27_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_NEW_REG150\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~2_RTM0152_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM151\); + +-- Location: FF_X31_Y27_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_NEW_REG148\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM149\); + +-- Location: LABCELL_X48_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM139\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM149\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM151\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM139\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM149\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM143\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM141\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM151\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM139\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM149\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM151\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM139\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM149\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM151\ +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001111110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]_OTERM151\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM143\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM141\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM139\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]_OTERM149\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\); + +-- Location: FF_X41_Y23_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(42)); + +-- Location: FF_X41_Y23_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(42)); + +-- Location: FF_X41_Y23_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(42)); + +-- Location: LABCELL_X48_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[42]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[42]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[42]~feeder_combout\); + +-- Location: FF_X48_Y31_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[42]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(42)); + +-- Location: LABCELL_X41_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(42) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(42) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(42))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(42))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(42))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100000001111100011100110100111101000011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(42), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(42), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~1_combout\); + +-- Location: FF_X41_Y18_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(42)); + +-- Location: FF_X41_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(42)); + +-- Location: FF_X41_Y18_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(42)); + +-- Location: FF_X44_Y18_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(42)); + +-- Location: LABCELL_X41_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(42) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(42) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(42) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(42)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(42) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(42) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(42))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(42) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(42) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(42) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(42))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100000000000111011100110000011101001100110001110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(42), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(42), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(42), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~0_combout\); + +-- Location: MLABCELL_X42_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux51~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux51~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~2_combout\); + +-- Location: FF_X42_Y15_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(42)); + +-- Location: MLABCELL_X42_Y15_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(42))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(42)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(42))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(42)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(42) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(42)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(42)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011110011001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(42), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(42), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(42), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~0_combout\); + +-- Location: LABCELL_X32_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(10))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(10)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(10)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111000000000011001101010101000011111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(10), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~1_combout\); + +-- Location: LABCELL_X35_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(38) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(34)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(10)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(38) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(34)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(10))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(38) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(34)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(10))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(38) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(34)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(10))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000101111100110000010100000011111101011111001111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(10), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(34), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(38), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~2_combout\); + +-- Location: LABCELL_X35_Y13_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[42]_NEW1788\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[42]_OTERM1789\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(41))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(41)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(41), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[42]_OTERM1789\); + +-- Location: FF_X35_Y13_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[42]_OTERM1789\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42)); + +-- Location: LABCELL_X29_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[11]_NEW1968\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[11]_OTERM1969\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(11))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(11))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[11]_OTERM1969\); + +-- Location: FF_X29_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[11]_OTERM1969\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(11)); + +-- Location: LABCELL_X32_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[11]~feeder_combout\); + +-- Location: FF_X32_Y11_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(11)); + +-- Location: MLABCELL_X42_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[11]~feeder_combout\); + +-- Location: FF_X42_Y13_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(11)); + +-- Location: FF_X34_Y11_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(11)); + +-- Location: FF_X34_Y11_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(11)); + +-- Location: MLABCELL_X34_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(11)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(11)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~0_combout\); + +-- Location: FF_X29_Y11_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(11)); + +-- Location: LABCELL_X32_Y11_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[11]~feeder_combout\); + +-- Location: FF_X32_Y11_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(11)); + +-- Location: FF_X31_Y11_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(11)); + +-- Location: FF_X29_Y11_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(11)); + +-- Location: LABCELL_X29_Y11_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(11) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(11)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(11)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~1_combout\); + +-- Location: LABCELL_X29_Y11_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux312~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux312~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~2_combout\); + +-- Location: FF_X29_Y11_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(11)); + +-- Location: MLABCELL_X23_Y16_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[11]_NEW2028\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[11]_OTERM2029\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(11)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(11)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[11]_OTERM2029\); + +-- Location: FF_X23_Y16_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[11]_OTERM2029\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11)); + +-- Location: FF_X28_Y14_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(11)); + +-- Location: FF_X28_Y14_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(11)); + +-- Location: FF_X29_Y14_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(11)); + +-- Location: FF_X29_Y14_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(11)); + +-- Location: LABCELL_X29_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(11) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(11))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(11))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(11))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(11)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(11))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(11)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(11)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010101000110100001111110110000101101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~0_combout\); + +-- Location: LABCELL_X26_Y14_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[11]~feeder_combout\); + +-- Location: FF_X26_Y14_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(11)); + +-- Location: LABCELL_X26_Y14_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[11]~feeder_combout\); + +-- Location: FF_X26_Y14_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(11)); + +-- Location: FF_X29_Y14_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(11)); + +-- Location: FF_X26_Y14_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(11)); + +-- Location: LABCELL_X26_Y14_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(11) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(11))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(11))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~1_combout\); + +-- Location: LABCELL_X32_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux366~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux366~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~2_combout\); + +-- Location: FF_X32_Y16_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(11)); + +-- Location: FF_X20_Y18_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(11)); + +-- Location: MLABCELL_X23_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[11]_NEW2032\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[11]_OTERM2033\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(11))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(11))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(11) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(11))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(11)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[11]_OTERM2033\); + +-- Location: FF_X23_Y17_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[11]_OTERM2033\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(11)); + +-- Location: FF_X31_Y13_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(11)); + +-- Location: FF_X31_Y13_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(11)); + +-- Location: LABCELL_X32_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[11]~feeder_combout\); + +-- Location: FF_X32_Y13_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(11)); + +-- Location: FF_X32_Y13_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(11)); + +-- Location: LABCELL_X32_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(11) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(11))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(11))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~1_combout\); + +-- Location: LABCELL_X29_Y14_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[11]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(11) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[11]~feeder_combout\); + +-- Location: FF_X29_Y14_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(11)); + +-- Location: FF_X28_Y14_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(11)); + +-- Location: FF_X29_Y14_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(11)); + +-- Location: LABCELL_X24_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[11]~feeder_combout\); + +-- Location: FF_X24_Y14_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(11)); + +-- Location: LABCELL_X29_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(11) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(11)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(11))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(11) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(11))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(11) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(11) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101011101110000010100100010101011110111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~0_combout\); + +-- Location: LABCELL_X32_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux398~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux398~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~2_combout\); + +-- Location: FF_X32_Y16_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(11)); + +-- Location: MLABCELL_X23_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030_RESYN12822\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001110000000000000111000011111111111110001111111111111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\); + +-- Location: MLABCELL_X23_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_OTERM2031\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010001000000010010111011111110111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_OTERM2031\); + +-- Location: FF_X23_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_OTERM2031\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11)); + +-- Location: FF_X34_Y14_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(11)); + +-- Location: FF_X34_Y14_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(11)); + +-- Location: LABCELL_X32_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[11]~feeder_combout\); + +-- Location: FF_X32_Y14_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(11)); + +-- Location: FF_X34_Y14_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(11)); + +-- Location: MLABCELL_X34_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(11)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(11)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(11))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(11))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~1_combout\); + +-- Location: LABCELL_X32_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[11]~feeder_combout\); + +-- Location: FF_X32_Y14_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(11)); + +-- Location: LABCELL_X31_Y14_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[11]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[11]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(11), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[11]~feeder_combout\); + +-- Location: FF_X31_Y14_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[11]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(11)); + +-- Location: FF_X31_Y14_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(11)); + +-- Location: FF_X31_Y14_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(11)); + +-- Location: LABCELL_X31_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(11)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(11)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(11)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(11), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(11), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~0_combout\); + +-- Location: LABCELL_X32_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux336~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux336~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~2_combout\); + +-- Location: FF_X32_Y16_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(11)); + +-- Location: LABCELL_X41_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~1_combout\); + +-- Location: LABCELL_X41_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~0_combout\); + +-- Location: LABCELL_X41_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~3_combout\); + +-- Location: LABCELL_X41_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~2_combout\); + +-- Location: LABCELL_X41_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~0_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~0_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~2_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~0_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010010011000110111000011001001110110101110101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~4_combout\); + +-- Location: LABCELL_X40_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~8_combout\); + +-- Location: LABCELL_X40_Y33_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~5_combout\); + +-- Location: LABCELL_X41_Y33_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~6_combout\); + +-- Location: LABCELL_X41_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~7_combout\); + +-- Location: LABCELL_X41_Y33_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~6_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~7_combout\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~5_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~8_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~9_combout\); + +-- Location: MLABCELL_X42_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13110\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~9_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000111010001110111100010111000101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\); + +-- Location: FF_X43_Y28_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_OTERM2413\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(43)); + +-- Location: LABCELL_X43_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13112\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(43) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(43) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(43) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011110000111100111111001111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(43), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\); + +-- Location: LABCELL_X43_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_OTERM2413\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(43) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(43) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010001101011101111111100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_OTERM2413\); + +-- Location: FF_X43_Y28_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_OTERM2413\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[43]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[43]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[43]~feeder_combout\); + +-- Location: FF_X42_Y26_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[43]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(43)); + +-- Location: MLABCELL_X42_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[43]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[43]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[43]~feeder_combout\); + +-- Location: FF_X42_Y26_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[43]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(43)); + +-- Location: FF_X41_Y26_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(43)); + +-- Location: FF_X42_Y26_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(43)); + +-- Location: MLABCELL_X42_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(43)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(43) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(43) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(43) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(43)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(43) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(43)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(43), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(43), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(43), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~0_combout\); + +-- Location: FF_X48_Y24_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(43)); + +-- Location: LABCELL_X48_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[43]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[43]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[43]~feeder_combout\); + +-- Location: FF_X48_Y24_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[43]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(43)); + +-- Location: FF_X49_Y24_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(43)); + +-- Location: MLABCELL_X49_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[43]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[43]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[43]~feeder_combout\); + +-- Location: FF_X49_Y24_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[43]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(43)); + +-- Location: MLABCELL_X49_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(43) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(43)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(43))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(43) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(43)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(43) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(43) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(43) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(43) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(43))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(43) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(43) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(43) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(43) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100100010000001010111011110101111001000101010111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(43), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(43), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(43), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~1_combout\); + +-- Location: MLABCELL_X49_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux178~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux178~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~2_combout\); + +-- Location: FF_X49_Y24_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(43)); + +-- Location: LABCELL_X40_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~5_combout\); + +-- Location: LABCELL_X40_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~8_combout\); + +-- Location: LABCELL_X41_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~6_combout\); + +-- Location: LABCELL_X41_Y33_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~7_combout\); + +-- Location: LABCELL_X40_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\))) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~7_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~8_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~5_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100111101001100011100110111000001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~9_combout\); + +-- Location: LABCELL_X41_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~1_combout\); + +-- Location: LABCELL_X41_Y31_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~3_combout\); + +-- Location: LABCELL_X41_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~2_combout\); + +-- Location: LABCELL_X36_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~0_combout\); + +-- Location: LABCELL_X41_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13114\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~3_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~0_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~3_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001110011001101000111110011000100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\); + +-- Location: LABCELL_X43_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13116\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~9_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111000101000000001100110000110101111101010011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(43), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\); + +-- Location: LABCELL_X43_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_OTERM2415\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_OTERM2415\); + +-- Location: FF_X43_Y30_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_OTERM2415\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43)); + +-- Location: FF_X49_Y16_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(43)); + +-- Location: FF_X48_Y16_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(43)); + +-- Location: FF_X48_Y16_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(43)); + +-- Location: FF_X48_Y16_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(43)); + +-- Location: LABCELL_X48_Y16_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(43) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(43))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(43) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(43) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(43)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(43) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(43) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(43)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(43) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(43) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(43)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011111101011111001100000101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(43), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(43), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(43), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~1_combout\); + +-- Location: LABCELL_X53_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[43]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[43]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(43), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[43]~feeder_combout\); + +-- Location: FF_X53_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[43]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(43)); + +-- Location: FF_X53_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(43)); + +-- Location: FF_X53_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(43)); + +-- Location: FF_X53_Y20_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(43)); + +-- Location: LABCELL_X53_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(43)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(43))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(43)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(43))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(43) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(43)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(43) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(43) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(43), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(43), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(43), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~0_combout\); + +-- Location: LABCELL_X43_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux242~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux242~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~2_combout\); + +-- Location: FF_X43_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(43)); + +-- Location: LABCELL_X39_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000111000000110000011100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~38_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~0_combout\); + +-- Location: FF_X39_Y25_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG488\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM489\); + +-- Location: FF_X35_Y25_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG482\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM483\); + +-- Location: LABCELL_X40_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~2_combout\); + +-- Location: LABCELL_X43_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011010001010110011110001001101010111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][11]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~1_combout\); + +-- Location: FF_X28_Y17_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(11)); + +-- Location: MLABCELL_X28_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(11) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100001111000011110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~3_combout\); + +-- Location: LABCELL_X39_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~4_RTM0492\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~4_RTM0492_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~3_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~3_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010000001110000011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~4_RTM0492_combout\); + +-- Location: FF_X39_Y25_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG490\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~4_RTM0492_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM491\); + +-- Location: LABCELL_X39_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM491\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM491\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM483\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM487\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM489\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101111111000011110111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM485\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM487\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM489\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM483\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM491\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\); + +-- Location: FF_X39_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(43)); + +-- Location: FF_X39_Y18_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(43)); + +-- Location: FF_X39_Y25_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(43)); + +-- Location: FF_X39_Y18_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(43)); + +-- Location: LABCELL_X39_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(43)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(43) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(43) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(43) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(43)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(43))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(43) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(43)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(43))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(43), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(43), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(43), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~1_combout\); + +-- Location: FF_X43_Y17_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(43)); + +-- Location: LABCELL_X44_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[43]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[43]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[43]~feeder_combout\); + +-- Location: FF_X44_Y17_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[43]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(43)); + +-- Location: FF_X44_Y17_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(43)); + +-- Location: LABCELL_X44_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[43]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[43]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[43]~feeder_combout\); + +-- Location: FF_X44_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[43]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(43)); + +-- Location: LABCELL_X44_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(43) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(43))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(43))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(43) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(43) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(43))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(43)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(43) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(43) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(43))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(43)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(43) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(43) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(43)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010011000111000001111111010000110100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(43), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(43), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(43), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~0_combout\); + +-- Location: LABCELL_X43_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux50~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux50~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~2_combout\); + +-- Location: FF_X43_Y20_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(43)); + +-- Location: LABCELL_X40_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~0_combout\); + +-- Location: LABCELL_X43_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~1_combout\); + +-- Location: MLABCELL_X37_Y23_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13106\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13106_BDD13107\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~1_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010010011000110111000011001001110110101110101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1467~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1467~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13106_BDD13107\); + +-- Location: MLABCELL_X37_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13108\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13106_BDD13107\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13106_BDD13107\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000010000000100000001011011111110111111101111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[43]_NEW2410_RESYN13106_BDD13107\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\); + +-- Location: LABCELL_X36_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_OTERM2411\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000101101110101111111100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_OTERM2411\); + +-- Location: FF_X36_Y23_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_OTERM2411\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43)); + +-- Location: FF_X45_Y18_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(43)); + +-- Location: MLABCELL_X37_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[43]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[43]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(43), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[43]~feeder_combout\); + +-- Location: FF_X37_Y22_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[43]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(43)); + +-- Location: FF_X45_Y18_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(43)); + +-- Location: FF_X45_Y18_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(43)); + +-- Location: MLABCELL_X45_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(43)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(43)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(43) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(43)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(43) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(43) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(43), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(43), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(43), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~0_combout\); + +-- Location: FF_X42_Y20_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(43)); + +-- Location: FF_X41_Y20_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(43)); + +-- Location: FF_X42_Y20_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(43)); + +-- Location: FF_X42_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(43)); + +-- Location: MLABCELL_X42_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(43)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(43) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(43)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(43) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(43)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(43))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(43) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(43)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(43))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(43), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(43), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(43), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~1_combout\); + +-- Location: LABCELL_X43_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux114~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux114~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~2_combout\); + +-- Location: FF_X43_Y20_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(43)); + +-- Location: LABCELL_X43_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(43)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(43))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(43) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(43)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(43))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(43) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(43)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(43) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(43) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(43), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(43), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(43), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~0_combout\); + +-- Location: LABCELL_X32_Y16_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(11))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(11))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(11) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(11) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(11))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(11)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(11)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111110011000100011100110011010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(11), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(11), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~1_combout\); + +-- Location: MLABCELL_X34_Y12_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(39) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(11))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(39) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(39) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(11))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(39) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000011110101010111111111001100110000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(11), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(35), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(39), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~2_combout\); + +-- Location: LABCELL_X35_Y12_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[43]_NEW1786\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[43]_OTERM1787\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(43))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(43))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(42), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(43), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[43]_OTERM1787\); + +-- Location: FF_X35_Y12_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[43]_OTERM1787\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(43)); + +-- Location: FF_X35_Y12_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]_OTERM1799\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(44)); + +-- Location: LABCELL_X31_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[12]_NEW1980\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[12]_OTERM1981\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(12))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[12]_OTERM1981\); + +-- Location: FF_X31_Y19_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[12]_OTERM1981\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(12)); + +-- Location: MLABCELL_X28_Y13_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[12]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(12) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[12]~feeder_combout\); + +-- Location: FF_X28_Y13_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(12)); + +-- Location: LABCELL_X29_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(12) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[12]~feeder_combout\); + +-- Location: FF_X29_Y13_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(12)); + +-- Location: LABCELL_X29_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(12) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[12]~feeder_combout\); + +-- Location: FF_X29_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(12)); + +-- Location: FF_X29_Y13_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(12)); + +-- Location: LABCELL_X29_Y13_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(12)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(12) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(12))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(12))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~0_combout\); + +-- Location: FF_X25_Y13_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(12)); + +-- Location: LABCELL_X25_Y13_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[12]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(12) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[12]~feeder_combout\); + +-- Location: FF_X25_Y13_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(12)); + +-- Location: LABCELL_X26_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(12) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[12]~feeder_combout\); + +-- Location: FF_X26_Y13_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(12)); + +-- Location: FF_X25_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(12)); + +-- Location: LABCELL_X25_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(12)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(12) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(12))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(12))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~1_combout\); + +-- Location: MLABCELL_X34_Y13_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux311~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux311~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~2_combout\); + +-- Location: FF_X34_Y13_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(12)); + +-- Location: MLABCELL_X23_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[12]_NEW2068\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[12]_OTERM2069\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(12))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(12)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[12]_OTERM2069\); + +-- Location: FF_X23_Y17_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[12]_OTERM2069\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(12)); + +-- Location: FF_X28_Y16_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(12)); + +-- Location: MLABCELL_X28_Y16_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[12]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(12) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[12]~feeder_combout\); + +-- Location: FF_X28_Y16_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(12)); + +-- Location: FF_X28_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(12)); + +-- Location: FF_X24_Y14_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(12)); + +-- Location: MLABCELL_X28_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(12)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(12))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(12) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(12) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(12))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(12) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(12) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101011101110000010100100010101011110111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~0_combout\); + +-- Location: LABCELL_X26_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(12) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[12]~feeder_combout\); + +-- Location: FF_X26_Y15_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(12)); + +-- Location: LABCELL_X25_Y15_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(12) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[12]~feeder_combout\); + +-- Location: FF_X25_Y15_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(12)); + +-- Location: LABCELL_X25_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(12) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[12]~feeder_combout\); + +-- Location: FF_X25_Y15_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(12)); + +-- Location: FF_X25_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(12)); + +-- Location: LABCELL_X25_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(12)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(12)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(12))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(12))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~1_combout\); + +-- Location: MLABCELL_X28_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000111011101110111011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux397~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux397~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~2_combout\); + +-- Location: FF_X28_Y15_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(12)); + +-- Location: FF_X24_Y15_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]_OTERM2065\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(12)); + +-- Location: LABCELL_X24_Y15_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]_NEW2064\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]_OTERM2065\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(12))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(12))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(12), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]_OTERM2065\); + +-- Location: FF_X24_Y15_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]_OTERM2065\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE_q\); + +-- Location: MLABCELL_X28_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[12]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[12]~feeder_combout\); + +-- Location: FF_X28_Y14_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(12)); + +-- Location: FF_X28_Y14_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(12)); + +-- Location: FF_X28_Y14_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(12)); + +-- Location: MLABCELL_X28_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[12]~feeder_combout\); + +-- Location: FF_X28_Y16_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(12)); + +-- Location: MLABCELL_X28_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(12) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(12))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(12))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(12))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(12)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(12))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(12)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(12) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(12)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010101000110100001111110110000101101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~0_combout\); + +-- Location: FF_X24_Y15_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(12)); + +-- Location: MLABCELL_X28_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[12]~feeder_combout\); + +-- Location: FF_X28_Y15_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(12)); + +-- Location: FF_X26_Y15_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(12)); + +-- Location: FF_X28_Y15_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(12)); + +-- Location: MLABCELL_X28_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(12)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(12)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(12))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(12))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~1_combout\); + +-- Location: MLABCELL_X28_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux365~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux365~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~2_combout\); + +-- Location: FF_X28_Y15_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(12)); + +-- Location: LABCELL_X29_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066_RESYN12834\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\) +-- # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001001100000000000100110000000011111111111011001111111111101100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\); + +-- Location: LABCELL_X29_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_OTERM2067\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001000110011111111011100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_OTERM2067\); + +-- Location: FF_X29_Y20_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_OTERM2067\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12)); + +-- Location: FF_X31_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(12)); + +-- Location: LABCELL_X31_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[12]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[12]~feeder_combout\); + +-- Location: FF_X31_Y17_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(12)); + +-- Location: FF_X35_Y17_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(12)); + +-- Location: FF_X31_Y17_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(12)); + +-- Location: LABCELL_X31_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(12))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(12))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(12)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(12)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~0_combout\); + +-- Location: LABCELL_X35_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[12]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[12]~feeder_combout\); + +-- Location: FF_X35_Y18_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(12)); + +-- Location: MLABCELL_X34_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[12]~feeder_combout\); + +-- Location: FF_X34_Y18_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[12]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(12)); + +-- Location: FF_X35_Y19_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(12)); + +-- Location: FF_X35_Y18_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(12)); + +-- Location: LABCELL_X35_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(12)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(12)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(12)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(12)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~1_combout\); + +-- Location: LABCELL_X31_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux335~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux335~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~2_combout\); + +-- Location: FF_X31_Y15_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(12)); + +-- Location: FF_X37_Y23_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_OTERM2443\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(44)); + +-- Location: LABCELL_X39_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~0_combout\); + +-- Location: LABCELL_X41_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001110000010011000111110001000011011100110100111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~1_combout\); + +-- Location: LABCELL_X35_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13170\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13170_BDD13171\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1466~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1466~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13170_BDD13171\); + +-- Location: MLABCELL_X37_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13172\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(44) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13170_BDD13171\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(44) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13170_BDD13171\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100101111001011110010111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]_NEW2442_RESYN13170_BDD13171\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(44), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\); + +-- Location: MLABCELL_X37_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_OTERM2443\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(44) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_OTERM2443\); + +-- Location: FF_X37_Y23_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_OTERM2443\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE_q\); + +-- Location: LABCELL_X40_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[44]~feeder_combout\); + +-- Location: FF_X40_Y20_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(44)); + +-- Location: LABCELL_X43_Y21_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[44]~feeder_combout\); + +-- Location: FF_X43_Y21_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(44)); + +-- Location: FF_X43_Y21_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(44)); + +-- Location: LABCELL_X43_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[44]~feeder_combout\); + +-- Location: FF_X43_Y21_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(44)); + +-- Location: LABCELL_X43_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(44) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(44)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(44)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(44) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(44) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(44)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(44))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(44) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(44) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(44)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(44))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(44) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(44) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(44)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(44))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101001000110110011110001001110011011010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(44), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(44), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(44), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~0_combout\); + +-- Location: FF_X37_Y23_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(44)); + +-- Location: MLABCELL_X42_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[44]~feeder_combout\); + +-- Location: FF_X42_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(44)); + +-- Location: MLABCELL_X42_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[44]~feeder_combout\); + +-- Location: FF_X42_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(44)); + +-- Location: FF_X42_Y20_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(44)); + +-- Location: MLABCELL_X42_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(44)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(44) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(44)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(44) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(44)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(44) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(44)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(44), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(44), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(44), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~1_combout\); + +-- Location: LABCELL_X43_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux113~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux113~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~2_combout\); + +-- Location: FF_X43_Y20_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(44)); + +-- Location: MLABCELL_X42_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~7_combout\); + +-- Location: LABCELL_X43_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~6_combout\); + +-- Location: LABCELL_X43_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~5_combout\); + +-- Location: MLABCELL_X42_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~8_combout\); + +-- Location: MLABCELL_X42_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~6_combout\)))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~6_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~6_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~8_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~6_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101001001100011011110001100100111011010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~9_combout\); + +-- Location: MLABCELL_X42_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~2_combout\); + +-- Location: LABCELL_X41_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~0_combout\); + +-- Location: LABCELL_X41_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~1_combout\); + +-- Location: MLABCELL_X42_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~3_combout\); + +-- Location: LABCELL_X41_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13178\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~2_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~3_combout\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~1_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011101010100001101101010101000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\); + +-- Location: MLABCELL_X42_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13180\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100101010100010111001010101000111011111111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(44), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\); + +-- Location: MLABCELL_X42_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_OTERM2447\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001101111111011101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_OTERM2447\); + +-- Location: FF_X42_Y27_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_OTERM2447\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44)); + +-- Location: MLABCELL_X49_Y24_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(44), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[44]~feeder_combout\); + +-- Location: FF_X49_Y24_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(44)); + +-- Location: LABCELL_X53_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(44), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[44]~feeder_combout\); + +-- Location: FF_X53_Y24_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(44)); + +-- Location: FF_X49_Y24_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(44)); + +-- Location: LABCELL_X53_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(44), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[44]~feeder_combout\); + +-- Location: FF_X53_Y24_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(44)); + +-- Location: MLABCELL_X49_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(44) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(44))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(44) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(44) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(44)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(44) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(44) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(44)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(44) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(44) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(44)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010001000100101111101110111000010100111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(44), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(44), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(44), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~1_combout\); + +-- Location: MLABCELL_X45_Y22_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(44), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[44]~feeder_combout\); + +-- Location: FF_X45_Y22_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(44)); + +-- Location: FF_X45_Y23_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(44)); + +-- Location: FF_X45_Y22_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(44)); + +-- Location: MLABCELL_X45_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(44), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[44]~feeder_combout\); + +-- Location: FF_X45_Y22_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(44)); + +-- Location: MLABCELL_X45_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(44) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(44))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(44) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(44) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(44)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(44) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(44) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(44)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(44) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(44) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(44)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010111110011000001010000001111110101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(44), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(44), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(44), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~0_combout\); + +-- Location: LABCELL_X44_Y22_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux241~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux241~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~2_combout\); + +-- Location: FF_X44_Y22_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(44)); + +-- Location: LABCELL_X31_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155~feeder_combout\); + +-- Location: FF_X31_Y28_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_NEW_REG154\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155\); + +-- Location: FF_X19_Y13_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(12)); + +-- Location: LABCELL_X31_Y28_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(12) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(12), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157~feeder_combout\); + +-- Location: FF_X31_Y28_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_NEW_REG156\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157\); + +-- Location: LABCELL_X41_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~0_combout\); + +-- Location: LABCELL_X39_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111010101010011001111111111000011110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~3_combout\); + +-- Location: LABCELL_X31_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~4_combout\); + +-- Location: LABCELL_X31_Y28_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~4_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010111111000001001011111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~1_combout\); + +-- Location: FF_X31_Y28_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_NEW_REG158\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM159\); + +-- Location: LABCELL_X31_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM159\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM159\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001010111000000100101011110001010110111111000101011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM107\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM155\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM157\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM159\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\); + +-- Location: FF_X49_Y21_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(44)); + +-- Location: MLABCELL_X49_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[44]~feeder_combout\); + +-- Location: FF_X49_Y20_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(44)); + +-- Location: FF_X49_Y21_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(44)); + +-- Location: LABCELL_X52_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[44]~feeder_combout\); + +-- Location: FF_X52_Y21_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(44)); + +-- Location: MLABCELL_X49_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(44) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(44))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(44)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(44) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(44))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(44) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(44) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(44) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(44) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(44)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(44) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(44) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(44) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(44) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110000000001010011111111110101001100001111010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(44), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(44), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(44), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~1_combout\); + +-- Location: FF_X45_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(44)); + +-- Location: FF_X45_Y20_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(44)); + +-- Location: FF_X45_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(44)); + +-- Location: FF_X49_Y21_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(44)); + +-- Location: MLABCELL_X45_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(44) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(44)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(44)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(44) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(44) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(44)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(44))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(44) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(44) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(44)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(44))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(44) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(44) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(44)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(44))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100110001000011010011110111000001111100011100110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(44), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(44), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(44), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~0_combout\); + +-- Location: LABCELL_X44_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux49~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux49~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~2_combout\); + +-- Location: FF_X44_Y20_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(44)); + +-- Location: FF_X41_Y27_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_OTERM2445\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(44)); + +-- Location: LABCELL_X41_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~0_combout\); + +-- Location: LABCELL_X41_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~1_combout\); + +-- Location: MLABCELL_X42_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~3_combout\); + +-- Location: MLABCELL_X42_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~2_combout\); + +-- Location: MLABCELL_X42_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~2_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010010001101100111000010011100110110101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~4_combout\); + +-- Location: MLABCELL_X42_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~8_combout\); + +-- Location: MLABCELL_X42_Y31_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\ ) ) ) # +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~7_combout\); + +-- Location: LABCELL_X43_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~6_combout\); + +-- Location: LABCELL_X43_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~5_combout\); + +-- Location: LABCELL_X43_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~8_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~7_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~7_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~5_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~7_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000110010101110100101010011011100011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~5_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~9_combout\); + +-- Location: MLABCELL_X42_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13174\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13174_BDD13175\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011000000010010001111111011011100111111101101110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13174_BDD13175\); + +-- Location: LABCELL_X41_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13176\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(44) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13174_BDD13175\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(44) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13174_BDD13175\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]_NEW2444_RESYN13174_BDD13175\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(44), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\); + +-- Location: LABCELL_X41_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_OTERM2445\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(44) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_OTERM2445\); + +-- Location: FF_X41_Y27_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_OTERM2445\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE_q\); + +-- Location: FF_X48_Y20_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(44)); + +-- Location: FF_X44_Y18_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(44)); + +-- Location: FF_X48_Y20_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(44)); + +-- Location: FF_X48_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(44)); + +-- Location: LABCELL_X48_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(44)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(44) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(44)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(44) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(44)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(44) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(44)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(44), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(44), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(44), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~0_combout\); + +-- Location: LABCELL_X48_Y22_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[44]~feeder_combout\); + +-- Location: FF_X48_Y22_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(44)); + +-- Location: MLABCELL_X49_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[44]~feeder_combout\); + +-- Location: FF_X49_Y22_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(44)); + +-- Location: LABCELL_X48_Y22_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[44]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[44]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[44]~feeder_combout\); + +-- Location: FF_X48_Y22_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[44]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(44)); + +-- Location: FF_X48_Y22_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(44)); + +-- Location: LABCELL_X48_Y22_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(44)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(44) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(44)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(44) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(44)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(44) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(44))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(44)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(44), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(44), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(44), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~1_combout\); + +-- Location: LABCELL_X43_Y20_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux177~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux177~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~2_combout\); + +-- Location: FF_X43_Y20_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(44)); + +-- Location: LABCELL_X43_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(44) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(44)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(44) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(44) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(44) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(44)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(44))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(44) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(44)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(44))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(44), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(44), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(44), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~0_combout\); + +-- Location: LABCELL_X31_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(12)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(12))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(12)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(12)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(12))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(12)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000110110001101101010101111111110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(12), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(12), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(12), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~1_combout\); + +-- Location: LABCELL_X35_Y12_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~1_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(40))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(12) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(40))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(40))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(12) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(40))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000101010001001010010111101110000011110100111010101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(40), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(36), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(12), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~2_combout\); + +-- Location: LABCELL_X35_Y12_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]_NEW1798\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]_OTERM1799\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(44))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(43))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(44))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(43)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(43), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(44), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]_OTERM1799\); + +-- Location: FF_X35_Y12_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]_OTERM1799\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE_q\); + +-- Location: LABCELL_X29_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[13]_NEW1972\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[13]_OTERM1973\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[13]_OTERM1973\); + +-- Location: FF_X29_Y19_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[13]_OTERM1973\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(13)); + +-- Location: LABCELL_X24_Y13_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[13]~feeder_combout\); + +-- Location: FF_X24_Y13_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(13)); + +-- Location: FF_X25_Y13_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(13)); + +-- Location: FF_X25_Y13_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(13)); + +-- Location: MLABCELL_X34_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[13]~feeder_combout\); + +-- Location: FF_X34_Y13_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(13)); + +-- Location: LABCELL_X25_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(13)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(13) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(13) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(13)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(13) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(13) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010000100010101111110111011000010101011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~1_combout\); + +-- Location: LABCELL_X35_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[13]~feeder_combout\); + +-- Location: FF_X35_Y17_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(13)); + +-- Location: FF_X35_Y12_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(13)); + +-- Location: FF_X28_Y13_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(13)); + +-- Location: MLABCELL_X28_Y13_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[13]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(13) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[13]~feeder_combout\); + +-- Location: FF_X28_Y13_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(13)); + +-- Location: MLABCELL_X28_Y13_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(13) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(13)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(13)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(13))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000111001101110000010011110100110001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~0_combout\); + +-- Location: MLABCELL_X28_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux310~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux310~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~2_combout\); + +-- Location: FF_X28_Y13_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(13)); + +-- Location: FF_X20_Y15_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector345~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(13)); + +-- Location: MLABCELL_X23_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[13]_NEW2082\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[13]_OTERM2083\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(13))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(13))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001101110110001000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[13]_OTERM2083\); + +-- Location: FF_X23_Y15_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[13]_OTERM2083\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13)); + +-- Location: FF_X29_Y14_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(13)); + +-- Location: MLABCELL_X28_Y14_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[13]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[13]~feeder_combout\); + +-- Location: FF_X28_Y14_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(13)); + +-- Location: FF_X29_Y14_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(13)); + +-- Location: FF_X24_Y14_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(13)); + +-- Location: LABCELL_X29_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(13)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(13))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(13))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(13))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(13))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001000011010011000100111101110000011100110111110001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~0_combout\); + +-- Location: LABCELL_X31_Y13_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[13]~feeder_combout\); + +-- Location: FF_X31_Y13_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(13)); + +-- Location: LABCELL_X31_Y13_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[13]~feeder_combout\); + +-- Location: FF_X31_Y13_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(13)); + +-- Location: FF_X31_Y13_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(13)); + +-- Location: FF_X29_Y14_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(13)); + +-- Location: LABCELL_X31_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(13)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(13))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(13) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(13) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(13))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(13) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(13) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010000000000110101111111110011010100001111001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~1_combout\); + +-- Location: LABCELL_X32_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux364~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux364~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~2_combout\); + +-- Location: FF_X32_Y17_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(13)); + +-- Location: FF_X29_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_OTERM2085\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(13)); + +-- Location: LABCELL_X29_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084_RESYN12840\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\) +-- # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(13) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000110000000100000011000011111110111111001111111011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\); + +-- Location: LABCELL_X29_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_OTERM2085\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010000000110011110111111100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_OTERM2085\); + +-- Location: FF_X29_Y20_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_OTERM2085\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE_q\); + +-- Location: LABCELL_X39_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[13]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[13]~feeder_combout\); + +-- Location: FF_X39_Y18_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(13)); + +-- Location: FF_X36_Y18_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(13)); + +-- Location: FF_X36_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(13)); + +-- Location: FF_X37_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(13)); + +-- Location: LABCELL_X36_Y18_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(13)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(13) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(13) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(13)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(13) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(13) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110000000001010011111111110101001100001111010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~1_combout\); + +-- Location: FF_X42_Y16_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(13)); + +-- Location: LABCELL_X36_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[13]~feeder_combout\); + +-- Location: FF_X36_Y17_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(13)); + +-- Location: FF_X36_Y17_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(13)); + +-- Location: LABCELL_X31_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[13]~feeder_combout\); + +-- Location: FF_X31_Y20_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(13)); + +-- Location: LABCELL_X36_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(13)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(13)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(13)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(13)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(13) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(13) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110100001000010111010101101010001111100010101101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~0_combout\); + +-- Location: LABCELL_X32_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux334~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux334~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~2_combout\); + +-- Location: FF_X32_Y17_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(13)); + +-- Location: MLABCELL_X23_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[13]_NEW2086\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[13]_OTERM2087\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(13))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(13) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(13)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[13]_OTERM2087\); + +-- Location: FF_X23_Y17_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[13]_OTERM2087\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(13)); + +-- Location: LABCELL_X36_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[13]~feeder_combout\); + +-- Location: FF_X36_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(13)); + +-- Location: LABCELL_X36_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[13]~feeder_combout\); + +-- Location: FF_X36_Y18_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(13)); + +-- Location: LABCELL_X35_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[13]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(13) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[13]~feeder_combout\); + +-- Location: FF_X35_Y18_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(13)); + +-- Location: FF_X36_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(13)); + +-- Location: LABCELL_X36_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(13) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(13))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(13))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~1_combout\); + +-- Location: FF_X31_Y16_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(13)); + +-- Location: FF_X29_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(13)); + +-- Location: FF_X29_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(13), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(13)); + +-- Location: MLABCELL_X34_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[13]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(13) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[13]~feeder_combout\); + +-- Location: FF_X34_Y17_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[13]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(13)); + +-- Location: LABCELL_X29_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(13) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(13) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(13))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010010001101100111000010011100110110101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~0_combout\); + +-- Location: LABCELL_X32_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux396~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux396~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~2_combout\); + +-- Location: FF_X32_Y17_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(13)); + +-- Location: MLABCELL_X37_Y38_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~0_combout\); + +-- Location: LABCELL_X41_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~1_combout\); + +-- Location: MLABCELL_X37_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13190\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13190_BDD13191\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111000000001100110001000111010001110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1465~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1465~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13190_BDD13191\); + +-- Location: MLABCELL_X37_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13192\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13190_BDD13191\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13190_BDD13191\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000101010001010100010101000101011101010111010101110101011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[45]_NEW2452_RESYN13190_BDD13191\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(45), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\); + +-- Location: MLABCELL_X37_Y24_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_OTERM2453\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111101001111000000001011000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_OTERM2453\); + +-- Location: FF_X37_Y24_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_OTERM2453\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45)); + +-- Location: LABCELL_X43_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[45]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[45]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(45), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[45]~feeder_combout\); + +-- Location: FF_X43_Y15_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[45]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(45)); + +-- Location: FF_X34_Y17_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(45)); + +-- Location: FF_X42_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(45)); + +-- Location: FF_X42_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(45)); + +-- Location: MLABCELL_X42_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(45) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(45))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(45))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(45) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(45) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(45)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(45) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(45) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(45) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(45))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(45) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(45))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(45)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111001100110100011111001100010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(45), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(45), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(45), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~0_combout\); + +-- Location: MLABCELL_X42_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[45]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[45]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(45), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[45]~feeder_combout\); + +-- Location: FF_X42_Y20_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[45]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(45)); + +-- Location: MLABCELL_X42_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[45]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[45]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(45), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[45]~feeder_combout\); + +-- Location: FF_X42_Y20_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[45]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(45)); + +-- Location: FF_X41_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(45)); + +-- Location: LABCELL_X41_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[45]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[45]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(45), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[45]~feeder_combout\); + +-- Location: FF_X41_Y20_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[45]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(45)); + +-- Location: LABCELL_X41_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(45) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(45)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(45))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(45) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(45)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(45) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(45) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(45) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(45) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(45))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(45) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(45) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(45) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010000000000110101111111110011010100001111001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(45), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(45), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(45), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~1_combout\); + +-- Location: LABCELL_X40_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux112~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux112~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~2_combout\); + +-- Location: FF_X40_Y21_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(45)); + +-- Location: LABCELL_X40_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~8_combout\); + +-- Location: LABCELL_X40_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~7_combout\); + +-- Location: LABCELL_X41_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~5_combout\); + +-- Location: LABCELL_X41_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~6_combout\); + +-- Location: LABCELL_X41_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~7_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~7_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~7_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010111110011000001010000001111110101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~9_combout\); + +-- Location: MLABCELL_X42_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~3_combout\); + +-- Location: LABCELL_X41_Y30_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~1_combout\); + +-- Location: MLABCELL_X42_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~2_combout\); + +-- Location: MLABCELL_X42_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~0_combout\); + +-- Location: MLABCELL_X42_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~3_combout\))) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000101011001110100100110101011100011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~4_combout\); + +-- Location: MLABCELL_X42_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13194\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~4_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110001011100001000111010001111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\); + +-- Location: FF_X42_Y28_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_OTERM2455\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13196\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]~DUPLICATE_q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001111111100110011000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\); + +-- Location: MLABCELL_X42_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_OTERM2455\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011111111110111001100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_OTERM2455\); + +-- Location: FF_X42_Y28_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_OTERM2455\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45)); + +-- Location: FF_X41_Y25_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(45)); + +-- Location: FF_X41_Y25_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(45)); + +-- Location: FF_X40_Y23_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(45)); + +-- Location: FF_X41_Y25_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(45)); + +-- Location: LABCELL_X41_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(45)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(45) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(45)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(45)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(45))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(45)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(45))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(45), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(45), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(45), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~1_combout\); + +-- Location: FF_X40_Y21_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(45)); + +-- Location: FF_X40_Y25_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(45)); + +-- Location: LABCELL_X41_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[45]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[45]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(45), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[45]~feeder_combout\); + +-- Location: FF_X41_Y21_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[45]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(45)); + +-- Location: FF_X40_Y21_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(45)); + +-- Location: LABCELL_X40_Y21_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(45))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(45)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(45))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(45)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(45)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(45) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(45) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(45), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(45), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(45), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~0_combout\); + +-- Location: LABCELL_X40_Y21_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux176~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux176~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~2_combout\); + +-- Location: FF_X40_Y21_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(45)); + +-- Location: FF_X40_Y27_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_OTERM2457\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(45)); + +-- Location: LABCELL_X40_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~8_combout\); + +-- Location: LABCELL_X40_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~7_combout\); + +-- Location: LABCELL_X41_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~5_combout\); + +-- Location: LABCELL_X41_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~6_combout\); + +-- Location: LABCELL_X40_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~8_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~7_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~7_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~6_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~7_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001111100110001000111001100110100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~9_combout\); + +-- Location: LABCELL_X41_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\ ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~1_combout\); + +-- Location: MLABCELL_X42_Y30_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~3_combout\); + +-- Location: MLABCELL_X42_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~2_combout\); + +-- Location: MLABCELL_X42_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~0_combout\); + +-- Location: MLABCELL_X42_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13198\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13198_BDD13199\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~3_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ +-- & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~0_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~3_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001110011001101000111110011000100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13198_BDD13199\); + +-- Location: LABCELL_X40_Y27_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13200\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13198_BDD13199\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13198_BDD13199\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(45))) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~9_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(45))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000011110000111100010001110111010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(45), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]_NEW2456_RESYN13198_BDD13199\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\); + +-- Location: LABCELL_X40_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_OTERM2457\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(45) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011111101111111001100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_OTERM2457\); + +-- Location: FF_X40_Y27_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_OTERM2457\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE_q\); + +-- Location: LABCELL_X44_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[45]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[45]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[45]~feeder_combout\); + +-- Location: FF_X44_Y25_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[45]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(45)); + +-- Location: MLABCELL_X42_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[45]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[45]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[45]~feeder_combout\); + +-- Location: FF_X42_Y24_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[45]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(45)); + +-- Location: MLABCELL_X42_Y24_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[45]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[45]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[45]~feeder_combout\); + +-- Location: FF_X42_Y24_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[45]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(45)); + +-- Location: FF_X42_Y24_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(45)); + +-- Location: MLABCELL_X42_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(45)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(45) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(45) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(45))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(45)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(45))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(45)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(45), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(45), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(45), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~1_combout\); + +-- Location: FF_X42_Y21_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(45)); + +-- Location: FF_X40_Y21_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(45)); + +-- Location: FF_X40_Y21_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(45)); + +-- Location: FF_X43_Y25_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(45)); + +-- Location: LABCELL_X40_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(45) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(45)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(45)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(45) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(45) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(45) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(45)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(45) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(45))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(45) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(45) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(45)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(45))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100000000000111011100110000011101001100110001110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(45), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(45), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(45), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~0_combout\); + +-- Location: LABCELL_X40_Y21_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux240~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux240~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~2_combout\); + +-- Location: FF_X40_Y21_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(45)); + +-- Location: MLABCELL_X37_Y38_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011101110011000001110100110011000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~3_combout\); + +-- Location: LABCELL_X41_Y30_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~0_combout\); + +-- Location: LABCELL_X31_Y28_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~3_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001001110000010100100111000011011010111110001101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~4_combout\); + +-- Location: LABCELL_X31_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010110000000000001011000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~1_combout\); + +-- Location: FF_X31_Y28_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_NEW_REG164\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM165\); + +-- Location: FF_X17_Y16_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(13)); + +-- Location: FF_X31_Y28_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_NEW_REG162\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(13), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM163\); + +-- Location: FF_X31_Y28_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_NEW_REG160\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM161\); + +-- Location: LABCELL_X31_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM161\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM163\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM165\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM161\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM163\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM165\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101011111000011110101111100101111011111110010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM107\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM165\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM163\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM161\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\); + +-- Location: LABCELL_X40_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[45]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[45]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[45]~feeder_combout\); + +-- Location: FF_X40_Y21_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[45]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(45)); + +-- Location: FF_X42_Y21_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(45)); + +-- Location: FF_X40_Y21_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(45)); + +-- Location: LABCELL_X41_Y21_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[45]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[45]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[45]~feeder_combout\); + +-- Location: FF_X41_Y21_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[45]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(45)); + +-- Location: LABCELL_X40_Y21_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(45) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(45))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(45))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(45) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(45) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(45))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(45)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(45) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(45) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(45))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(45)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(45) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(45) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(45))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(45)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000001100011101110000110001000100001111110111011100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(45), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(45), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(45), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~0_combout\); + +-- Location: FF_X37_Y21_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(45)); + +-- Location: LABCELL_X40_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[45]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[45]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[45]~feeder_combout\); + +-- Location: FF_X40_Y23_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[45]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(45)); + +-- Location: FF_X39_Y21_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(45)); + +-- Location: FF_X39_Y21_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(45)); + +-- Location: LABCELL_X39_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(45) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(45)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(45)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(45) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(45))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(45)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(45) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(45) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(45)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(45) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(45) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(45))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(45) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111000001000011011100110100110001111100010011110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(45), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(45), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(45), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~1_combout\); + +-- Location: LABCELL_X40_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux48~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux48~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~2_combout\); + +-- Location: FF_X40_Y21_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(45)); + +-- Location: LABCELL_X40_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(45) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(45) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(45) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(45) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(45), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(45), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(45), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(45), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~0_combout\); + +-- Location: LABCELL_X32_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(13) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(13)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(13) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(13))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(13)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(13))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100111101001100011100110111000001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(13), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~1_combout\); + +-- Location: LABCELL_X35_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(41)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(37))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(13)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(41)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(37))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101000000000000111100110101001101011111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(37), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(41), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(13), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~2_combout\); + +-- Location: LABCELL_X35_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[45]_NEW1794\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[45]_OTERM1795\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[44]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[45]_OTERM1795\); + +-- Location: FF_X35_Y13_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[45]_OTERM1795\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45)); + +-- Location: LABCELL_X29_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[14]_NEW1976\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[14]_OTERM1977\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(14))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[14]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[14]_OTERM1977\); + +-- Location: FF_X29_Y19_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[14]_OTERM1977\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(14)); + +-- Location: LABCELL_X31_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(14) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[14]~feeder_combout\); + +-- Location: FF_X31_Y15_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[14]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(14)); + +-- Location: MLABCELL_X34_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[14]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(14) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[14]~feeder_combout\); + +-- Location: FF_X34_Y15_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[14]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(14)); + +-- Location: FF_X34_Y15_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(14)); + +-- Location: FF_X34_Y15_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(14)); + +-- Location: MLABCELL_X34_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(14) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(14) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(14) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(14))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(14)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100110000111101010011111100000101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(14), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~1_combout\); + +-- Location: FF_X29_Y14_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(14)); + +-- Location: FF_X32_Y12_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(14)); + +-- Location: FF_X32_Y12_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(14)); + +-- Location: FF_X31_Y14_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(14)); + +-- Location: LABCELL_X32_Y12_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(14) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(14) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(14)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(14)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(14))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(14)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001010100111101000100101011101010010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~0_combout\); + +-- Location: LABCELL_X32_Y12_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux309~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux309~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~2_combout\); + +-- Location: FF_X32_Y12_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(14)); + +-- Location: LABCELL_X24_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[14]_NEW2094\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[14]_OTERM2095\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[14]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[14]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[14]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[14]_OTERM2095\); + +-- Location: FF_X24_Y15_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[14]_OTERM2095\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14)); + +-- Location: FF_X24_Y12_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(14)); + +-- Location: FF_X24_Y12_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(14)); + +-- Location: FF_X29_Y12_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(14)); + +-- Location: LABCELL_X25_Y12_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[14]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[14]~feeder_combout\); + +-- Location: FF_X25_Y12_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[14]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(14)); + +-- Location: LABCELL_X29_Y12_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(14))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(14)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(14)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(14))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011010000101010001111110110000101110101011010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~1_combout\); + +-- Location: FF_X28_Y12_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(14)); + +-- Location: FF_X28_Y12_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(14)); + +-- Location: FF_X29_Y12_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(14)); + +-- Location: FF_X26_Y11_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(14)); + +-- Location: LABCELL_X29_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(14))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(14))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(14))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(14)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(14))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(14)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(14) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(14)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101000100011010111110111011000001011011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~0_combout\); + +-- Location: LABCELL_X29_Y12_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux363~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux363~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~2_combout\); + +-- Location: FF_X29_Y12_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(14)); + +-- Location: LABCELL_X24_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[14]_NEW2098\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[14]_OTERM2099\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(14)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(14)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[14]_OTERM2099\); + +-- Location: FF_X24_Y17_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[14]_OTERM2099\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14)); + +-- Location: LABCELL_X24_Y12_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[14]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[14]~feeder_combout\); + +-- Location: FF_X24_Y12_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[14]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(14)); + +-- Location: FF_X24_Y12_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(14)); + +-- Location: FF_X29_Y12_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(14)); + +-- Location: FF_X25_Y12_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(14)); + +-- Location: LABCELL_X29_Y12_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(14))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(14)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(14)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(14))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011100000100110001111111010000110111001101001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(14), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~1_combout\); + +-- Location: LABCELL_X26_Y11_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[14]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[14]~feeder_combout\); + +-- Location: FF_X26_Y11_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[14]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(14)); + +-- Location: FF_X28_Y12_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(14)); + +-- Location: FF_X29_Y12_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(14)); + +-- Location: FF_X28_Y12_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(14)); + +-- Location: LABCELL_X29_Y12_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(14) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(14) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(14))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(14)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(14) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(14)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100111111000001010011000011110101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(14), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~0_combout\); + +-- Location: LABCELL_X29_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux395~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux395~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~2_combout\); + +-- Location: FF_X29_Y12_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(14)); + +-- Location: FF_X23_Y20_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_OTERM2097\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(14)); + +-- Location: MLABCELL_X23_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096_RESYN12844\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001110000000000000111000011111111111110001111111111111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\); + +-- Location: MLABCELL_X23_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_OTERM2097\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(14) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010001000000010010111011111110111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_OTERM2097\); + +-- Location: FF_X23_Y20_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_OTERM2097\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE_q\); + +-- Location: FF_X34_Y15_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(14)); + +-- Location: FF_X34_Y15_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(14)); + +-- Location: FF_X34_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(14)); + +-- Location: FF_X31_Y15_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(14)); + +-- Location: MLABCELL_X34_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(14)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(14)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(14))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(14) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(14)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(14) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(14))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110100000001110011011111000100111101001100011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(14), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~1_combout\); + +-- Location: FF_X31_Y14_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(14)); + +-- Location: FF_X34_Y12_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(14)); + +-- Location: FF_X32_Y12_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(14)); + +-- Location: FF_X32_Y12_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(14)); + +-- Location: LABCELL_X32_Y12_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(14)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(14)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(14)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(14) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(14) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(14)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(14) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(14))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(14) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110100001010100011111000100001011101010110101101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(14), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(14), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~0_combout\); + +-- Location: LABCELL_X32_Y12_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100110000000000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux333~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux333~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~2_combout\); + +-- Location: FF_X32_Y12_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(14)); + +-- Location: FF_X35_Y22_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_NEW_REG680\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM681\); + +-- Location: FF_X35_Y22_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_NEW_REG678\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM679\); + +-- Location: LABCELL_X36_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677~feeder_combout\); + +-- Location: FF_X36_Y22_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_NEW_REG676\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677\); + +-- Location: LABCELL_X35_Y22_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM681\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM681\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677\))))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM679\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0011000000110000000011110000111100100000011100000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM681\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM679\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM677\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM437\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\); + +-- Location: FF_X35_Y19_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(46)); + +-- Location: LABCELL_X36_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[46]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[46]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1464~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[46]~feeder_combout\); + +-- Location: FF_X36_Y19_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[46]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(46)); + +-- Location: FF_X36_Y19_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(46)); + +-- Location: LABCELL_X36_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[46]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[46]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1464~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[46]~feeder_combout\); + +-- Location: FF_X36_Y19_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[46]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(46)); + +-- Location: LABCELL_X36_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(46) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(46) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(46))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(46))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(46) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(46) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(46))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(46))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(46) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(46) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(46)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(46))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(46) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(46) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(46)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(46))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000011001010011000101110100101010001110110110111001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(46), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(46), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(46), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(46), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~0_combout\); + +-- Location: FF_X37_Y22_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(46)); + +-- Location: FF_X37_Y20_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(46)); + +-- Location: LABCELL_X36_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[46]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[46]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1464~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[46]~feeder_combout\); + +-- Location: FF_X36_Y20_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[46]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(46)); + +-- Location: FF_X37_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(46)); + +-- Location: MLABCELL_X37_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(46) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(46)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(46) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(46) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(46) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(46))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(46)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(46) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(46))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(46)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(46), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(46), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(46), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(46), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~1_combout\); + +-- Location: MLABCELL_X37_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux111~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux111~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~2_combout\); + +-- Location: FF_X37_Y17_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(46)); + +-- Location: LABCELL_X26_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[14]~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~139_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[14]~feeder_combout\); + +-- Location: FF_X26_Y17_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[14]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(14)); + +-- Location: FF_X31_Y21_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG240\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(14), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM241\); + +-- Location: LABCELL_X32_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000001110000111100000111000001110000011100000111000001110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]~7_combout\); + +-- Location: FF_X32_Y23_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG242\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]~7_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\); + +-- Location: FF_X32_Y25_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG236\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM237\); + +-- Location: FF_X31_Y25_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG234\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM235\); + +-- Location: MLABCELL_X37_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM235\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM241\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM237\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM235\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\) ) +-- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM235\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM241\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM237\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM235\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100010100000101111111111100111111000101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM241\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM225\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM243\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM237\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM239\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM235\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\); + +-- Location: FF_X41_Y16_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(46)); + +-- Location: LABCELL_X40_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[46]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[46]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1400~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[46]~feeder_combout\); + +-- Location: FF_X40_Y16_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[46]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(46)); + +-- Location: FF_X41_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(46)); + +-- Location: FF_X41_Y16_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(46)); + +-- Location: LABCELL_X41_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(46) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(46) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(46))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(46))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(46) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(46) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(46))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(46)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(46) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(46) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(46))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(46)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(46) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(46) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(46))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(46)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101001001100011011110001100100111011010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(46), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(46), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(46), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(46), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~0_combout\); + +-- Location: FF_X37_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(46)); + +-- Location: LABCELL_X39_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[46]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[46]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1400~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[46]~feeder_combout\); + +-- Location: FF_X39_Y19_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[46]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(46)); + +-- Location: LABCELL_X36_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[46]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[46]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1400~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[46]~feeder_combout\); + +-- Location: FF_X36_Y20_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[46]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(46)); + +-- Location: FF_X37_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(46)); + +-- Location: MLABCELL_X37_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(46) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(46)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(46) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(46)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(46) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(46))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(46)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(46) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(46))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(46)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(46), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(46), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(46), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(46), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~1_combout\); + +-- Location: MLABCELL_X37_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux47~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux47~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~2_combout\); + +-- Location: FF_X37_Y17_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(46)); + +-- Location: MLABCELL_X37_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(46)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(46))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(46), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(46), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~0_combout\); + +-- Location: LABCELL_X29_Y12_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(14)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(14)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(14))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(14) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(14))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000000000011001100001111010101011111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(14), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(14), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(14), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~1_combout\); + +-- Location: LABCELL_X35_Y12_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(14))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(14)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(14)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(14)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010101101100001011010100011010000111111011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[38]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(14), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(42), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~2_combout\); + +-- Location: LABCELL_X36_Y12_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[46]_NEW1796\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[46]_OTERM1797\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(45), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(46), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[46]_OTERM1797\); + +-- Location: FF_X36_Y12_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[46]_OTERM1797\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46)); + +-- Location: LABCELL_X20_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[15]_NEW2070\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[15]_OTERM2071\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(15))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(15)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(15) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[15]_OTERM2071\); + +-- Location: FF_X20_Y15_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[15]_OTERM2071\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(15)); + +-- Location: FF_X28_Y14_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(15)); + +-- Location: MLABCELL_X28_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[15]~feeder_combout\); + +-- Location: FF_X28_Y14_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(15)); + +-- Location: FF_X28_Y14_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(15)); + +-- Location: LABCELL_X26_Y10_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[15]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(15) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[15]~feeder_combout\); + +-- Location: FF_X26_Y10_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(15)); + +-- Location: MLABCELL_X28_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(15))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(15))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(15))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(15)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(15))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(15)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(15)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101000100011010111110111011000001011011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~0_combout\); + +-- Location: LABCELL_X31_Y13_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[15]~feeder_combout\); + +-- Location: FF_X31_Y13_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(15)); + +-- Location: LABCELL_X31_Y13_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[15]~feeder_combout\); + +-- Location: FF_X31_Y13_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(15)); + +-- Location: FF_X31_Y13_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(15)); + +-- Location: FF_X36_Y12_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(15)); + +-- Location: LABCELL_X31_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(15)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(15))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(15) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(15) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(15))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(15) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(15) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100100010000001010111011110101111001000101010111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~1_combout\); + +-- Location: LABCELL_X36_Y14_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux362~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux362~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~2_combout\); + +-- Location: FF_X36_Y14_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(15)); + +-- Location: MLABCELL_X23_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072_RESYN12836\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001110000000000000111000011111111111110001111111111111000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\); + +-- Location: MLABCELL_X23_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_OTERM2073\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010000000100010010111111101110111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_OTERM2073\); + +-- Location: FF_X23_Y20_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_OTERM2073\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15)); + +-- Location: LABCELL_X26_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[15]~feeder_combout\); + +-- Location: FF_X26_Y14_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(15)); + +-- Location: LABCELL_X26_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[15]~feeder_combout\); + +-- Location: FF_X26_Y14_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(15)); + +-- Location: FF_X26_Y14_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(15)); + +-- Location: LABCELL_X31_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[15]~feeder_combout\); + +-- Location: FF_X31_Y12_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(15)); + +-- Location: LABCELL_X26_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(15))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(15)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(15) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(15) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(15)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(15) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(15) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001100000100010011111111011101000011001101110100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~1_combout\); + +-- Location: LABCELL_X35_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[15]~feeder_combout\); + +-- Location: FF_X35_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(15)); + +-- Location: FF_X36_Y17_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(15)); + +-- Location: FF_X36_Y17_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(15)); + +-- Location: FF_X36_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(15)); + +-- Location: LABCELL_X36_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(15))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(15))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(15) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(15) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(15))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(15)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111001100110100011111001100010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~0_combout\); + +-- Location: LABCELL_X36_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux332~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux332~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~2_combout\); + +-- Location: FF_X36_Y16_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(15)); + +-- Location: LABCELL_X19_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[15]_NEW2074\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[15]_OTERM2075\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(15))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(15) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[15]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[15]_OTERM2075\); + +-- Location: FF_X19_Y17_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[15]_OTERM2075\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(15)); + +-- Location: FF_X28_Y14_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(15)); + +-- Location: MLABCELL_X28_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[15]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(15) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[15]~feeder_combout\); + +-- Location: FF_X28_Y16_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(15)); + +-- Location: FF_X28_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(15)); + +-- Location: FF_X28_Y14_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(15)); + +-- Location: MLABCELL_X28_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(15))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(15)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(15) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(15) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(15)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(15) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(15) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000101001111110000010100110000111101010011111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~0_combout\); + +-- Location: FF_X26_Y15_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(15)); + +-- Location: FF_X26_Y15_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(15)); + +-- Location: FF_X28_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(15)); + +-- Location: MLABCELL_X28_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[15]~feeder_combout\); + +-- Location: FF_X28_Y15_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(15)); + +-- Location: MLABCELL_X28_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(15)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(15))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(15) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(15) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(15))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(15) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(15) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010000000000110101111111110011010100001111001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~1_combout\); + +-- Location: LABCELL_X35_Y16_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111111111111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux394~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux394~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~2_combout\); + +-- Location: FF_X35_Y16_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(15)); + +-- Location: FF_X35_Y22_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_NEW_REG670\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM671\); + +-- Location: FF_X35_Y22_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_NEW_REG672\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM673\); + +-- Location: FF_X35_Y22_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_NEW_REG674\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM675\); + +-- Location: LABCELL_X35_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM675\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM675\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM671\)))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM673\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000011110000000011110000111100010000101100000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM671\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM673\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM675\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM437\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\); + +-- Location: LABCELL_X39_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[47]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[47]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1463~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[47]~feeder_combout\); + +-- Location: FF_X39_Y18_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[47]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(47)); + +-- Location: LABCELL_X39_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[47]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[47]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1463~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[47]~feeder_combout\); + +-- Location: FF_X39_Y19_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[47]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(47)); + +-- Location: FF_X35_Y19_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(47)); + +-- Location: FF_X39_Y19_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(47)); + +-- Location: LABCELL_X39_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(47) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(47)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(47) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(47)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(47) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(47))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(47)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(47) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(47))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(47)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(47), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(47), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(47), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(47), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~1_combout\); + +-- Location: FF_X37_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(47)); + +-- Location: LABCELL_X39_Y16_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[47]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[47]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1463~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[47]~feeder_combout\); + +-- Location: FF_X39_Y16_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[47]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(47)); + +-- Location: FF_X37_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(47)); + +-- Location: LABCELL_X39_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[47]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[47]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1463~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[47]~feeder_combout\); + +-- Location: FF_X39_Y16_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[47]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(47)); + +-- Location: MLABCELL_X37_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(47) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(47) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(47)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(47)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(47) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(47) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(47))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(47) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(47) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(47) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(47) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(47)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(47) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(47) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(47)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(47))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011010101010001101110101010000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(47), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(47), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(47), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(47), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~0_combout\); + +-- Location: MLABCELL_X37_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux110~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux110~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~2_combout\); + +-- Location: FF_X37_Y16_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(47)); + +-- Location: MLABCELL_X23_Y13_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[15]~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~135_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[15]~feeder_combout\); + +-- Location: FF_X23_Y13_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(15)); + +-- Location: FF_X34_Y25_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_NEW_REG294\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(15), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM295\); + +-- Location: FF_X31_Y25_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_NEW_REG292\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM293\); + +-- Location: FF_X31_Y21_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_NEW_REG290\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM291\); + +-- Location: MLABCELL_X37_Y21_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM291\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM295\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM293\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM291\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM291\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM295\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM293\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010100110101001111110000111100000101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM295\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM293\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM243\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM239\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM291\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\); + +-- Location: FF_X36_Y20_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(47)); + +-- Location: FF_X36_Y20_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(47)); + +-- Location: MLABCELL_X37_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[47]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[47]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1399~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[47]~feeder_combout\); + +-- Location: FF_X37_Y20_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[47]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(47)); + +-- Location: FF_X36_Y20_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(47)); + +-- Location: LABCELL_X36_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(47) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(47)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(47) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(47) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(47) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(47)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(47))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(47) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(47)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(47))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(47), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(47), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(47), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(47), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~1_combout\); + +-- Location: LABCELL_X36_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[47]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[47]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1399~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[47]~feeder_combout\); + +-- Location: FF_X36_Y15_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[47]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(47)); + +-- Location: LABCELL_X41_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[47]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[47]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1399~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[47]~feeder_combout\); + +-- Location: FF_X41_Y16_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[47]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(47)); + +-- Location: FF_X37_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(47)); + +-- Location: MLABCELL_X37_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[47]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[47]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1399~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[47]~feeder_combout\); + +-- Location: FF_X37_Y16_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[47]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(47)); + +-- Location: MLABCELL_X37_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(47) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(47) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(47)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(47)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(47) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(47) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(47)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(47))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(47) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(47) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(47)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(47))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(47) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(47) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(47)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(47))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010010001101100111000010011100110110101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(47), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(47), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(47), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(47), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~0_combout\); + +-- Location: MLABCELL_X37_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux46~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux46~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~2_combout\); + +-- Location: FF_X37_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(47)); + +-- Location: MLABCELL_X37_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(47) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(47) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000001010101010101010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(47), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(47), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~0_combout\); + +-- Location: LABCELL_X36_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(15)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(15)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(15))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(15)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(15)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100010001000111011100111111001111110100010001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~1_combout\); + +-- Location: LABCELL_X29_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[15]_NEW1982\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[15]_OTERM1983\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(15))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[15]_OTERM1983\); + +-- Location: FF_X29_Y19_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[15]_OTERM1983\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(15)); + +-- Location: LABCELL_X26_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[15]~feeder_combout\); + +-- Location: FF_X26_Y14_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(15)); + +-- Location: LABCELL_X26_Y14_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[15]~feeder_combout\); + +-- Location: FF_X26_Y14_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(15)); + +-- Location: FF_X31_Y12_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(15)); + +-- Location: FF_X31_Y12_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(15)); + +-- Location: LABCELL_X31_Y12_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(15)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(15)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(15))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(15) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(15) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(15)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(15) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(15))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110100000001110011011111000100111101001100011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~1_combout\); + +-- Location: FF_X29_Y13_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(15)); + +-- Location: LABCELL_X32_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[15]~feeder_combout\); + +-- Location: FF_X32_Y12_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(15)); + +-- Location: FF_X32_Y12_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(15), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(15)); + +-- Location: LABCELL_X31_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[15]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(15) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[15]~feeder_combout\); + +-- Location: FF_X31_Y14_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[15]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(15)); + +-- Location: LABCELL_X32_Y12_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(15) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(15) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(15)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(15) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(15)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(15))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(15)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001010100111101000100101011101010010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(15), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(15), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(15), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~0_combout\); + +-- Location: LABCELL_X32_Y12_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux308~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux308~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~2_combout\); + +-- Location: FF_X32_Y12_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(15)); + +-- Location: LABCELL_X35_Y12_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(39)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(15) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(39) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(39), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(43), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(15), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~2_combout\); + +-- Location: LABCELL_X35_Y12_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]_NEW1800\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]_OTERM1801\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(47))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(47))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(46), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(47), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]_OTERM1801\); + +-- Location: FF_X35_Y12_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]_OTERM1801\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(47)); + +-- Location: LABCELL_X31_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[16]_NEW1986\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[16]_OTERM1987\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000100011101110100010001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[16]_OTERM1987\); + +-- Location: FF_X31_Y19_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[16]_OTERM1987\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16)); + +-- Location: FF_X25_Y13_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(16)); + +-- Location: FF_X25_Y13_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(16)); + +-- Location: LABCELL_X26_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[16]~feeder_combout\); + +-- Location: FF_X26_Y13_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(16)); + +-- Location: FF_X25_Y13_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(16)); + +-- Location: LABCELL_X25_Y13_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(16))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(16))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~1_combout\); + +-- Location: LABCELL_X26_Y13_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[16]~feeder_combout\); + +-- Location: FF_X26_Y13_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(16)); + +-- Location: LABCELL_X26_Y13_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[16]~feeder_combout\); + +-- Location: FF_X26_Y13_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(16)); + +-- Location: FF_X28_Y13_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(16)); + +-- Location: FF_X28_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(16)); + +-- Location: MLABCELL_X28_Y13_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(16) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(16))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(16)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(16)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(16)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000001100011101110000110001000100001111110111011100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~0_combout\); + +-- Location: MLABCELL_X28_Y13_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux307~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux307~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~2_combout\); + +-- Location: FF_X28_Y13_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(16)); + +-- Location: FF_X29_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_OTERM2109\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(16)); + +-- Location: LABCELL_X29_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108_RESYN12848\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(16) +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010011000000000001001111101100111111111110110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[16]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\); + +-- Location: LABCELL_X29_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_OTERM2109\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010000000110011110111111100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_OTERM2109\); + +-- Location: FF_X29_Y20_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_OTERM2109\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE_q\); + +-- Location: FF_X34_Y15_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(16)); + +-- Location: FF_X34_Y15_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(16)); + +-- Location: FF_X34_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(16)); + +-- Location: LABCELL_X31_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[16]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[16]~feeder_combout\); + +-- Location: FF_X31_Y15_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(16)); + +-- Location: MLABCELL_X34_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(16) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(16))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(16)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(16))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(16))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(16)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(16) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(16))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011100000100110001111111010000110111001101001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~1_combout\); + +-- Location: FF_X31_Y17_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(16)); + +-- Location: FF_X31_Y16_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(16)); + +-- Location: FF_X31_Y17_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(16)); + +-- Location: FF_X31_Y17_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(16)); + +-- Location: LABCELL_X31_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(16)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(16)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~0_combout\); + +-- Location: LABCELL_X35_Y17_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux331~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux331~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~2_combout\); + +-- Location: FF_X35_Y17_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(16)); + +-- Location: LABCELL_X20_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[16]_NEW2110\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[16]_OTERM2111\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(16))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[16]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(16) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[16]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[16]_OTERM2111\); + +-- Location: FF_X20_Y17_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[16]_OTERM2111\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(16)); + +-- Location: LABCELL_X24_Y16_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[16]~feeder_combout\); + +-- Location: FF_X24_Y16_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(16)); + +-- Location: FF_X24_Y16_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(16)); + +-- Location: LABCELL_X25_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[16]~feeder_combout\); + +-- Location: FF_X25_Y16_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(16)); + +-- Location: FF_X24_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(16)); + +-- Location: LABCELL_X24_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(16)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(16))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(16))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~1_combout\); + +-- Location: LABCELL_X25_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[16]~feeder_combout\); + +-- Location: FF_X25_Y16_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(16)); + +-- Location: LABCELL_X26_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[16]~feeder_combout\); + +-- Location: FF_X26_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(16)); + +-- Location: FF_X26_Y16_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(16)); + +-- Location: FF_X26_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(16)); + +-- Location: LABCELL_X26_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(16))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(16))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(16) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~0_combout\); + +-- Location: LABCELL_X35_Y17_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux393~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux393~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~2_combout\); + +-- Location: FF_X35_Y17_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(16)); + +-- Location: LABCELL_X20_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[16]_NEW2106\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[16]_OTERM2107\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(16))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(16)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(16) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[16]_OTERM2107\); + +-- Location: FF_X20_Y17_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[16]_OTERM2107\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(16)); + +-- Location: MLABCELL_X28_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[16]~feeder_combout\); + +-- Location: FF_X28_Y16_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(16)); + +-- Location: LABCELL_X26_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[16]~feeder_combout\); + +-- Location: FF_X26_Y16_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(16)); + +-- Location: FF_X26_Y16_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(16)); + +-- Location: FF_X26_Y16_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(16)); + +-- Location: LABCELL_X26_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(16) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(16)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(16)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~0_combout\); + +-- Location: LABCELL_X29_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[16]~feeder_combout\); + +-- Location: FF_X29_Y15_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(16)); + +-- Location: LABCELL_X25_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[16]~feeder_combout\); + +-- Location: FF_X25_Y15_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(16)); + +-- Location: LABCELL_X25_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[16]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[16]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(16) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(16), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[16]~feeder_combout\); + +-- Location: FF_X25_Y15_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[16]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(16)); + +-- Location: FF_X25_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(16), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(16)); + +-- Location: LABCELL_X25_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(16) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(16))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(16))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(16), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~1_combout\); + +-- Location: LABCELL_X32_Y17_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux361~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux361~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~2_combout\); + +-- Location: FF_X32_Y17_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(16)); + +-- Location: MLABCELL_X34_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~0_combout\); + +-- Location: FF_X34_Y26_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_NEW_REG648\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM649\); + +-- Location: LABCELL_X29_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "1111101011111010101010101111111011111010111110101010101011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~2_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~4_combout\); + +-- Location: FF_X29_Y29_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_NEW_REG644\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM645\); + +-- Location: FF_X34_Y26_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG408\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM409\); + +-- Location: FF_X28_Y38_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_NEW_REG646\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM647\); + +-- Location: LABCELL_X24_Y38_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][0]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0_combout\); + +-- Location: LABCELL_X24_Y38_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1_combout\); + +-- Location: FF_X23_Y34_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~323_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE_q\); + +-- Location: LABCELL_X24_Y38_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][0]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3_combout\); + +-- Location: MLABCELL_X34_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100000000000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\); + +-- Location: LABCELL_X24_Y38_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1_combout\))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011111101011111001100000101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~4_combout\); + +-- Location: FF_X35_Y24_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(16)); + +-- Location: LABCELL_X35_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000100010001000100100010001000100011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(16), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1398~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~1_combout\); + +-- Location: MLABCELL_X28_Y38_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~2_RTM0652\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~2_RTM0652_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~1_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~1_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000011110011111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1398~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~2_RTM0652_combout\); + +-- Location: FF_X28_Y38_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_NEW_REG650\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~2_RTM0652_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM651\); + +-- Location: MLABCELL_X28_Y38_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM647\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM651\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM647\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM651\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM647\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM651\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM409\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM645\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM649\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM647\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM651\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM649\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM409\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001110000011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM649\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM645\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM409\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM647\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM651\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\); + +-- Location: MLABCELL_X37_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1398~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[48]~feeder_combout\); + +-- Location: FF_X37_Y21_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(48)); + +-- Location: MLABCELL_X37_Y21_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1398~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[48]~feeder_combout\); + +-- Location: FF_X37_Y21_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(48)); + +-- Location: FF_X37_Y21_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(48)); + +-- Location: MLABCELL_X37_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1398~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[48]~feeder_combout\); + +-- Location: FF_X37_Y19_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(48)); + +-- Location: MLABCELL_X37_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(48) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(48))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(48)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(48) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(48))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(48) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(48) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(48) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(48))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(48)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(48) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(48) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(48))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(48) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011100000100110001111111010000110111001101001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(48), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(48), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(48), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(48), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~1_combout\); + +-- Location: FF_X41_Y16_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(48)); + +-- Location: FF_X41_Y16_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(48)); + +-- Location: FF_X42_Y16_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(48)); + +-- Location: FF_X41_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(48)); + +-- Location: LABCELL_X41_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(48)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(48) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(48)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(48) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(48))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(48) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(48))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(48), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(48), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(48), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(48), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~0_combout\); + +-- Location: LABCELL_X35_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux45~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~2_combout\); + +-- Location: FF_X35_Y17_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(48)); + +-- Location: LABCELL_X24_Y38_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13370\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111010001000100010000000011110011110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\); + +-- Location: LABCELL_X26_Y37_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13372\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001111001000100010001001110111000011110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(48), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\); + +-- Location: LABCELL_X31_Y34_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_OTERM2570\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001110110000110011000100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(48), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_OTERM2570\); + +-- Location: FF_X31_Y34_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_OTERM2570\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48)); + +-- Location: MLABCELL_X34_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[48]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(48), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[48]~feeder_combout\); + +-- Location: FF_X34_Y17_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(48)); + +-- Location: MLABCELL_X37_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(48), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[48]~feeder_combout\); + +-- Location: FF_X37_Y15_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(48)); + +-- Location: FF_X37_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(48)); + +-- Location: FF_X34_Y17_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(48)); + +-- Location: MLABCELL_X37_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(48) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(48) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(48) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(48))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(48) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(48) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(48))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(48) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(48) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(48))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(48), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(48), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(48), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(48), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~1_combout\); + +-- Location: LABCELL_X40_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(48), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[48]~feeder_combout\); + +-- Location: FF_X40_Y17_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(48)); + +-- Location: LABCELL_X40_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(48), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[48]~feeder_combout\); + +-- Location: FF_X40_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(48)); + +-- Location: FF_X40_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(48)); + +-- Location: MLABCELL_X37_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(48), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[48]~feeder_combout\); + +-- Location: FF_X37_Y15_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(48)); + +-- Location: LABCELL_X40_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(48) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(48)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(48)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(48) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(48) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(48)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(48))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(48) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(48) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(48)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(48))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(48) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(48) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(48))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101001000110110011110001001110011011010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(48), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(48), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(48), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(48), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~0_combout\); + +-- Location: LABCELL_X35_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux173~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux173~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~2_combout\); + +-- Location: FF_X35_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(48)); + +-- Location: LABCELL_X39_Y35_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux390~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux390~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][0]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux390~0_combout\); + +-- Location: FF_X39_Y35_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_NEW_REG428\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux390~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM429\); + +-- Location: FF_X35_Y23_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_NEW_REG420\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~49_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM421\); + +-- Location: LABCELL_X39_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) +-- # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000100110011001000110011001100100011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1462~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~1_combout\); + +-- Location: FF_X39_Y27_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_NEW_REG432\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM433\); + +-- Location: LABCELL_X24_Y38_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~0_combout\); + +-- Location: FF_X24_Y38_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_NEW_REG430\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM431\); + +-- Location: LABCELL_X39_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM433\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM431\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM433\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM431\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM421\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM429\))) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM433\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM431\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM433\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM431\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM429\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM421\)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001111111111111111101010001010100011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM429\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM421\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM433\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM431\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\); + +-- Location: LABCELL_X39_Y16_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1462~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[48]~feeder_combout\); + +-- Location: FF_X39_Y16_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(48)); + +-- Location: LABCELL_X48_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1462~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[48]~feeder_combout\); + +-- Location: FF_X48_Y14_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(48)); + +-- Location: FF_X39_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(48)); + +-- Location: LABCELL_X40_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1462~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[48]~feeder_combout\); + +-- Location: FF_X40_Y16_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(48)); + +-- Location: LABCELL_X39_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(48) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(48) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(48) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(48))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(48)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(48) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(48) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(48)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(48) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(48) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(48) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(48))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000010110000000110101011101000010101101101010001111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(48), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(48), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(48), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(48), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~0_combout\); + +-- Location: LABCELL_X39_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1462~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[48]~feeder_combout\); + +-- Location: FF_X39_Y18_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(48)); + +-- Location: LABCELL_X39_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1462~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[48]~feeder_combout\); + +-- Location: FF_X39_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(48)); + +-- Location: FF_X39_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(48)); + +-- Location: LABCELL_X39_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1462~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[48]~feeder_combout\); + +-- Location: FF_X39_Y21_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(48)); + +-- Location: LABCELL_X39_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(48) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(48))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(48))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(48) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(48) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(48))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(48)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(48) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(48) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(48))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(48)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(48) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(48) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(48))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(48)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011111101011111001100000101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(48), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(48), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(48), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(48), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~1_combout\); + +-- Location: LABCELL_X40_Y18_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux109~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux109~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~2_combout\); + +-- Location: FF_X40_Y18_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(48)); + +-- Location: FF_X34_Y35_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_OTERM2465\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(48)); + +-- Location: LABCELL_X24_Y38_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][0]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~1_combout\); + +-- Location: LABCELL_X24_Y38_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][0]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][0]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~0_combout\); + +-- Location: MLABCELL_X34_Y35_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13214\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13214_BDD13215\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux178~4_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~1_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001001110000010100100111000011011010111110001101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1578~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1578~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13214_BDD13215\); + +-- Location: MLABCELL_X34_Y35_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13216\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(48) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13214_BDD13215\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(48) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13214_BDD13215\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]_NEW2464_RESYN13214_BDD13215\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(48), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\); + +-- Location: MLABCELL_X34_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_OTERM2465\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(48) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011101010101001010001010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(48), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_OTERM2465\); + +-- Location: FF_X34_Y35_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_OTERM2465\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE_q\); + +-- Location: FF_X41_Y17_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(48)); + +-- Location: FF_X43_Y17_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(48)); + +-- Location: FF_X41_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(48)); + +-- Location: FF_X41_Y17_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(48)); + +-- Location: LABCELL_X41_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(48) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(48)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(48)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(48) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(48) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(48))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(48) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(48) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(48) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(48))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(48)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(48) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(48) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(48))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101001100010011110111000001110011011111000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(48), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(48), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(48), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(48), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~0_combout\); + +-- Location: MLABCELL_X42_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[48]~feeder_combout\); + +-- Location: FF_X42_Y19_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(48)); + +-- Location: LABCELL_X44_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[48]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[48]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[48]~feeder_combout\); + +-- Location: FF_X44_Y19_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[48]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(48)); + +-- Location: FF_X42_Y19_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(48)); + +-- Location: FF_X42_Y19_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(48)); + +-- Location: MLABCELL_X42_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(48) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(48)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(48) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(48)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(48) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(48))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(48) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(48))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(48), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(48), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(48), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(48), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~1_combout\); + +-- Location: LABCELL_X35_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux237~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux237~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~2_combout\); + +-- Location: FF_X35_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(48)); + +-- Location: LABCELL_X35_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(48) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(48) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(48) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(48) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(48), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(48), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(48), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(48), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~0_combout\); + +-- Location: LABCELL_X35_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(16))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(16))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(16), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~1_combout\); + +-- Location: LABCELL_X35_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(44)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(40))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(16)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(44)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(40))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000001010000010100010001101110111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(40), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(16), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(44), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~2_combout\); + +-- Location: LABCELL_X35_Y12_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[48]_NEW1808\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[48]_OTERM1809\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(48))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(47))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(48))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(47)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(47), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(48), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[48]_OTERM1809\); + +-- Location: FF_X35_Y12_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[48]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[48]_OTERM1809\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(48)); + +-- Location: LABCELL_X29_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[17]_NEW1974\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[17]_OTERM1975\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[17]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[17]_OTERM1975\); + +-- Location: FF_X29_Y19_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[17]_OTERM1975\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(17)); + +-- Location: LABCELL_X31_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(17) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[17]~feeder_combout\); + +-- Location: FF_X31_Y14_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(17)); + +-- Location: LABCELL_X29_Y14_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(17) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[17]~feeder_combout\); + +-- Location: FF_X29_Y14_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(17)); + +-- Location: LABCELL_X31_Y14_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[17]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(17) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[17]~feeder_combout\); + +-- Location: FF_X31_Y14_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(17)); + +-- Location: FF_X31_Y14_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(17)); + +-- Location: LABCELL_X31_Y14_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(17)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(17) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(17))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(17))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~0_combout\); + +-- Location: FF_X31_Y15_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(17)); + +-- Location: FF_X29_Y15_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(17)); + +-- Location: FF_X31_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(17)); + +-- Location: FF_X32_Y15_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(17)); + +-- Location: LABCELL_X31_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(17) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(17))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(17) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(17)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(17)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001110000010000110111001101001100011111000100111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(17), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~1_combout\); + +-- Location: LABCELL_X31_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux306~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux306~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~2_combout\); + +-- Location: FF_X31_Y15_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(17)); + +-- Location: LABCELL_X24_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[17]_NEW2088\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[17]_OTERM2089\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(17))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(17))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(17), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[17]_OTERM2089\); + +-- Location: FF_X24_Y15_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[17]_OTERM2089\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17)); + +-- Location: FF_X29_Y16_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(17)); + +-- Location: FF_X29_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(17)); + +-- Location: LABCELL_X26_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[17]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[17]~feeder_combout\); + +-- Location: FF_X26_Y16_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(17)); + +-- Location: FF_X29_Y16_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(17)); + +-- Location: LABCELL_X29_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(17))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(17))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(17)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(17) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~0_combout\); + +-- Location: FF_X26_Y15_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(17)); + +-- Location: MLABCELL_X28_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[17]~feeder_combout\); + +-- Location: FF_X28_Y17_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(17)); + +-- Location: FF_X32_Y17_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(17)); + +-- Location: FF_X32_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(17)); + +-- Location: LABCELL_X32_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(17)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(17)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(17))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(17))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(17), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~1_combout\); + +-- Location: LABCELL_X32_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux360~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux360~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~2_combout\); + +-- Location: FF_X32_Y17_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(17)); + +-- Location: FF_X20_Y17_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[17]~27_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(17)); + +-- Location: LABCELL_X20_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[17]_NEW2092\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[17]_OTERM2093\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(17)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(17))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(17) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[17]_OTERM2093\); + +-- Location: FF_X20_Y17_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[17]_OTERM2093\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(17)); + +-- Location: FF_X37_Y18_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(17)); + +-- Location: FF_X36_Y18_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(17)); + +-- Location: FF_X36_Y18_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(17)); + +-- Location: FF_X36_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(17)); + +-- Location: LABCELL_X36_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(17)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(17)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(17)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(17)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(17), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~1_combout\); + +-- Location: FF_X29_Y17_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(17)); + +-- Location: FF_X28_Y17_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(17)); + +-- Location: FF_X29_Y17_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(17)); + +-- Location: FF_X29_Y17_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(17)); + +-- Location: LABCELL_X29_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(17)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(17) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(17)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(17)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~0_combout\); + +-- Location: LABCELL_X32_Y17_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux392~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux392~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~2_combout\); + +-- Location: FF_X32_Y17_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(17)); + +-- Location: LABCELL_X24_Y36_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3_combout\); + +-- Location: LABCELL_X24_Y36_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1_combout\); + +-- Location: LABCELL_X24_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][1]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0_combout\); + +-- Location: LABCELL_X39_Y35_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][1]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\); + +-- Location: LABCELL_X24_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13358\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\); + +-- Location: LABCELL_X39_Y27_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13360\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100000000001011110010001000001101110111010010111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(49), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\); + +-- Location: LABCELL_X39_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_OTERM2561\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(49), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_OTERM2561\); + +-- Location: FF_X39_Y27_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_OTERM2561\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49)); + +-- Location: FF_X39_Y22_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(49)); + +-- Location: FF_X39_Y22_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(49)); + +-- Location: FF_X39_Y22_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(49)); + +-- Location: FF_X39_Y27_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(49)); + +-- Location: LABCELL_X39_Y22_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(49) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(49))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(49)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(49) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(49))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(49) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(49) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(49) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(49) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(49)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(49) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(49) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(49) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(49) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010000100010101111110111011000010101011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(49), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(49), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(49), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(49), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~1_combout\); + +-- Location: LABCELL_X43_Y23_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(49), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[49]~feeder_combout\); + +-- Location: FF_X43_Y23_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(49)); + +-- Location: LABCELL_X40_Y22_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(49), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[49]~feeder_combout\); + +-- Location: FF_X40_Y22_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(49)); + +-- Location: LABCELL_X40_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(49), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[49]~feeder_combout\); + +-- Location: FF_X40_Y22_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(49)); + +-- Location: FF_X40_Y22_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(49)); + +-- Location: LABCELL_X40_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(49))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(49)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(49))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(49)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(49) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(49)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(49) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(49) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(49), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(49), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(49), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(49), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~0_combout\); + +-- Location: LABCELL_X40_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux172~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux172~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~2_combout\); + +-- Location: FF_X40_Y18_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(49)); + +-- Location: LABCELL_X39_Y27_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) +-- # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000100110011001000110011001100100011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1461~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~1_combout\); + +-- Location: FF_X39_Y27_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_NEW_REG426\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM427\); + +-- Location: LABCELL_X24_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][1]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~0_combout\); + +-- Location: FF_X24_Y36_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_NEW_REG424\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM425\); + +-- Location: LABCELL_X39_Y35_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux389~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux389~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux389~0_combout\); + +-- Location: FF_X39_Y35_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_NEW_REG422\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux389~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM423\); + +-- Location: LABCELL_X39_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM423\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM421\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM427\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM423\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM421\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM427\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM423\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM421\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM425\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM427\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM423\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM421\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM425\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM427\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101110111010101010111011101010101010101010101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM427\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM425\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM423\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM421\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\); + +-- Location: LABCELL_X39_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1461~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[49]~feeder_combout\); + +-- Location: FF_X39_Y16_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(49)); + +-- Location: LABCELL_X39_Y16_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1461~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[49]~feeder_combout\); + +-- Location: FF_X39_Y16_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(49)); + +-- Location: FF_X40_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(49)); + +-- Location: FF_X39_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(49)); + +-- Location: LABCELL_X39_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(49)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(49) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(49)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(49) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(49)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(49))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(49) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(49)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(49))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(49), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(49), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(49), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(49), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~0_combout\); + +-- Location: LABCELL_X40_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1461~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[49]~feeder_combout\); + +-- Location: FF_X40_Y18_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(49)); + +-- Location: FF_X39_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(49)); + +-- Location: LABCELL_X39_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1461~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[49]~feeder_combout\); + +-- Location: FF_X39_Y20_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(49)); + +-- Location: FF_X39_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(49)); + +-- Location: LABCELL_X39_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(49)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(49) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(49) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(49) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(49)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(49))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(49) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(49)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(49))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(49), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(49), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(49), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(49), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~1_combout\); + +-- Location: LABCELL_X40_Y18_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux108~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux108~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~2_combout\); + +-- Location: FF_X40_Y18_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(49)); + +-- Location: FF_X34_Y35_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_OTERM2459\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(49)); + +-- Location: LABCELL_X39_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111000000000011001101010101000011111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~0_combout\); + +-- Location: LABCELL_X24_Y36_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][1]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][1]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][1]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~1_combout\); + +-- Location: MLABCELL_X34_Y35_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13202\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13202_BDD13203\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~0_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux177~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101000101000000010100010110101011111011111010101111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1577~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1577~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13202_BDD13203\); + +-- Location: MLABCELL_X34_Y35_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13204\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(49) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13202_BDD13203\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(49) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13202_BDD13203\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]_NEW2458_RESYN13202_BDD13203\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(49), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\); + +-- Location: MLABCELL_X34_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_OTERM2459\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(49) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011101010101001010001010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(49), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_OTERM2459\); + +-- Location: FF_X34_Y35_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_OTERM2459\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[49]~feeder_combout\); + +-- Location: FF_X42_Y19_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(49)); + +-- Location: MLABCELL_X42_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[49]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[49]~feeder_combout\); + +-- Location: FF_X42_Y19_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(49)); + +-- Location: FF_X41_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(49)); + +-- Location: LABCELL_X41_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[49]~feeder_combout\); + +-- Location: FF_X41_Y20_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(49)); + +-- Location: LABCELL_X41_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(49) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(49))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(49)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(49) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(49))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(49) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(49) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(49) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(49) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(49)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(49) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(49) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(49) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(49) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110000000001010011111111110101001100001111010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(49), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(49), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(49), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(49), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~1_combout\); + +-- Location: MLABCELL_X45_Y18_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[49]~feeder_combout\); + +-- Location: FF_X45_Y18_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(49)); + +-- Location: LABCELL_X40_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[49]~feeder_combout\); + +-- Location: FF_X40_Y17_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(49)); + +-- Location: FF_X40_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(49)); + +-- Location: MLABCELL_X42_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[49]~feeder_combout\); + +-- Location: FF_X42_Y17_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(49)); + +-- Location: LABCELL_X40_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(49) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(49))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(49))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(49) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(49) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(49))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(49)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(49) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(49) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(49))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(49)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(49) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(49) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(49))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(49)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000011000100011100111111011101000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(49), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(49), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(49), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(49), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~0_combout\); + +-- Location: LABCELL_X40_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux236~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux236~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~2_combout\); + +-- Location: FF_X40_Y18_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(49)); + +-- Location: LABCELL_X24_Y36_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100001001101010111000010101100111010011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~4_combout\); + +-- Location: FF_X18_Y14_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|MEM_DATA_READ[17]~27_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(17)); + +-- Location: MLABCELL_X37_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(17)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(17)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000100010001000101010101010101010001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(17), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~2_combout\); + +-- Location: MLABCELL_X28_Y38_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~3_RTM0418\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~3_RTM0418_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~2_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~2_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~4_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101001101110011011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~3_RTM0418_combout\); + +-- Location: FF_X28_Y38_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG416\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~3_RTM0418_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM417\); + +-- Location: MLABCELL_X34_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000000101010101010101010101010011001101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~0_combout\); + +-- Location: MLABCELL_X34_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000000000001100000000000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~1_combout\); + +-- Location: FF_X34_Y26_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG414\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM415\); + +-- Location: FF_X34_Y26_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG412\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM413\); + +-- Location: FF_X34_Y26_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG410\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM411\); + +-- Location: MLABCELL_X34_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM413\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM411\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM409\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM415\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM417\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM413\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM411\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM409\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM415\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM417\) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM413\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM411\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM409\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM417\) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM413\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM411\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM409\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM415\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM417\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101011111010111110101111101010101010111110101010101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM417\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM409\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM415\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM413\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM411\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\); + +-- Location: MLABCELL_X37_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[49]~feeder_combout\); + +-- Location: FF_X37_Y18_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(49)); + +-- Location: LABCELL_X40_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[49]~feeder_combout\); + +-- Location: FF_X40_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(49)); + +-- Location: FF_X40_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(49)); + +-- Location: LABCELL_X40_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[49]~feeder_combout\); + +-- Location: FF_X40_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(49)); + +-- Location: LABCELL_X40_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(49) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(49))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(49))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(49) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(49) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(49) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(49)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(49) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(49) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(49)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(49))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(49) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(49) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(49))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(49)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001010100111101000100101011101010010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(49), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(49), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(49), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(49), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~0_combout\); + +-- Location: FF_X40_Y18_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(49)); + +-- Location: MLABCELL_X37_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[49]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[49]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[49]~feeder_combout\); + +-- Location: FF_X37_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[49]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(49)); + +-- Location: FF_X37_Y18_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(49)); + +-- Location: FF_X35_Y19_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(49)); + +-- Location: MLABCELL_X37_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(49) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(49) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(49)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(49)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(49) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(49) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(49)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(49))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(49) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(49) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(49)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(49))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(49) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(49) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(49)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(49))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(49), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(49), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(49), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(49), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~1_combout\); + +-- Location: LABCELL_X40_Y18_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux44~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux44~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~2_combout\); + +-- Location: FF_X40_Y18_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(49)); + +-- Location: LABCELL_X40_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(49) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(49) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(49) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(49) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(49), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(49), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(49), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(49), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~0_combout\); + +-- Location: LABCELL_X29_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090_RESYN12842\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17) +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000011000000010000001111101111110011111110111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[17]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\); + +-- Location: LABCELL_X29_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_OTERM2091\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010000000110011110111111100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_OTERM2091\); + +-- Location: FF_X29_Y20_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_OTERM2091\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17)); + +-- Location: FF_X36_Y18_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(17)); + +-- Location: FF_X36_Y18_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(17)); + +-- Location: FF_X36_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(17)); + +-- Location: FF_X35_Y18_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(17)); + +-- Location: LABCELL_X36_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(17)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(17) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(17) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(17)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(17) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011100000100110001111111010000110111001101001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(17), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~1_combout\); + +-- Location: LABCELL_X31_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[17]~feeder_combout\); + +-- Location: FF_X31_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(17)); + +-- Location: LABCELL_X29_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[17]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[17]~feeder_combout\); + +-- Location: FF_X29_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(17)); + +-- Location: FF_X31_Y17_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(17)); + +-- Location: LABCELL_X31_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[17]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[17]~feeder_combout\); + +-- Location: FF_X31_Y17_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[17]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(17)); + +-- Location: LABCELL_X31_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(17)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(17)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(17) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(17)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(17))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(17))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(17) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(17))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011010001010110011110001001101010111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(17), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(17), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~0_combout\); + +-- Location: LABCELL_X32_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux330~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux330~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~2_combout\); + +-- Location: FF_X32_Y17_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(17)); + +-- Location: LABCELL_X32_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(17))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(17))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(17)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(17) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(17) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(17) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(17))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(17) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(17)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111010101010010011110101010001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(17), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(17), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(17), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~1_combout\); + +-- Location: LABCELL_X35_Y13_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(17)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(41) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(17) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(41) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(17)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(41) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(17) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000000101001111110000010100110000111101010011111111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(17), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(45), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(41), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~2_combout\); + +-- Location: LABCELL_X36_Y12_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]_NEW1806\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]_OTERM1807\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(49))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(48))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(49))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(48)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(48), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(49), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]_OTERM1807\); + +-- Location: FF_X36_Y12_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]_OTERM1807\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(49)); + +-- Location: LABCELL_X29_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[18]_NEW1978\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[18]_OTERM1979\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(18))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(18) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(18))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[18]_OTERM1979\); + +-- Location: FF_X29_Y19_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[18]_OTERM1979\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(18)); + +-- Location: LABCELL_X25_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[18]~feeder_combout\); + +-- Location: FF_X25_Y11_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(18)); + +-- Location: LABCELL_X25_Y11_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[18]~feeder_combout\); + +-- Location: FF_X25_Y11_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(18)); + +-- Location: LABCELL_X26_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[18]~feeder_combout\); + +-- Location: FF_X26_Y11_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(18)); + +-- Location: FF_X26_Y11_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(18)); + +-- Location: LABCELL_X26_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(18)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(18)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~0_combout\); + +-- Location: LABCELL_X24_Y11_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[18]~feeder_combout\); + +-- Location: FF_X24_Y11_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(18)); + +-- Location: MLABCELL_X28_Y12_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[18]~feeder_combout\); + +-- Location: FF_X28_Y12_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(18)); + +-- Location: LABCELL_X24_Y11_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[18]~feeder_combout\); + +-- Location: FF_X24_Y11_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(18)); + +-- Location: FF_X29_Y12_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(18)); + +-- Location: LABCELL_X29_Y12_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(18))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(18))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~1_combout\); + +-- Location: LABCELL_X29_Y12_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux305~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux305~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~2_combout\); + +-- Location: FF_X29_Y12_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(18)); + +-- Location: FF_X20_Y17_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(18)); + +-- Location: MLABCELL_X23_Y17_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[18]_NEW2104\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[18]_OTERM2105\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(18))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(18))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(18)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[18]_OTERM2105\); + +-- Location: FF_X23_Y17_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[18]_OTERM2105\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(18)); + +-- Location: FF_X35_Y16_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(18)); + +-- Location: FF_X29_Y17_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(18)); + +-- Location: LABCELL_X29_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[18]~feeder_combout\); + +-- Location: FF_X29_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(18)); + +-- Location: FF_X29_Y17_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(18)); + +-- Location: LABCELL_X29_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(18) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(18)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(18)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~0_combout\); + +-- Location: LABCELL_X35_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[18]~feeder_combout\); + +-- Location: FF_X35_Y18_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(18)); + +-- Location: LABCELL_X36_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[18]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(18) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[18]~feeder_combout\); + +-- Location: FF_X36_Y18_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(18)); + +-- Location: FF_X36_Y18_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(18)); + +-- Location: FF_X36_Y18_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(18)); + +-- Location: LABCELL_X36_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(18)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(18)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~1_combout\); + +-- Location: LABCELL_X32_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux391~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux391~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~2_combout\); + +-- Location: FF_X32_Y15_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(18)); + +-- Location: FF_X29_Y20_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_OTERM2103\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(18)); + +-- Location: LABCELL_X29_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102_RESYN12846\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(18) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(18))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(18) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000011000000010000001111101111110011111110111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\); + +-- Location: LABCELL_X29_Y20_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_OTERM2103\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001000110011111111011100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_OTERM2103\); + +-- Location: FF_X29_Y20_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_OTERM2103\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE_q\); + +-- Location: FF_X31_Y14_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(18)); + +-- Location: LABCELL_X31_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[18]~feeder_combout\); + +-- Location: FF_X31_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(18)); + +-- Location: LABCELL_X29_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[18]~feeder_combout\); + +-- Location: FF_X29_Y17_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(18)); + +-- Location: FF_X31_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(18)); + +-- Location: LABCELL_X31_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(18) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(18))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(18))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~0_combout\); + +-- Location: LABCELL_X24_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[18]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[18]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[18]~feeder_combout\); + +-- Location: FF_X24_Y16_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(18)); + +-- Location: FF_X25_Y15_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(18)); + +-- Location: FF_X24_Y16_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(18)); + +-- Location: FF_X25_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(18)); + +-- Location: LABCELL_X25_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(18)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(18)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~1_combout\); + +-- Location: LABCELL_X31_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111111111111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux329~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux329~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~2_combout\); + +-- Location: FF_X31_Y15_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(18)); + +-- Location: MLABCELL_X23_Y16_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[18]_NEW2100\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[18]_OTERM2101\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[18]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[18]_OTERM2101\); + +-- Location: FF_X23_Y16_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[18]_OTERM2101\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18)); + +-- Location: LABCELL_X24_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[18]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[18]~feeder_combout\); + +-- Location: FF_X24_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(18)); + +-- Location: FF_X25_Y16_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(18)); + +-- Location: LABCELL_X24_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[18]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[18]~feeder_combout\); + +-- Location: FF_X24_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(18)); + +-- Location: FF_X24_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(18)); + +-- Location: LABCELL_X24_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(18)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(18)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~1_combout\); + +-- Location: FF_X25_Y16_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(18)); + +-- Location: LABCELL_X26_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[18]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[18]~feeder_combout\); + +-- Location: FF_X26_Y16_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(18)); + +-- Location: LABCELL_X26_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[18]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(18), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[18]~feeder_combout\); + +-- Location: FF_X26_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[18]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(18)); + +-- Location: FF_X26_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(18)); + +-- Location: LABCELL_X26_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(18))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(18)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(18))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(18) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100111111111100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(18), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~0_combout\); + +-- Location: LABCELL_X31_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux359~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux359~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~2_combout\); + +-- Location: FF_X31_Y16_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(18)); + +-- Location: FF_X35_Y25_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_NEW_REG722\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM723\); + +-- Location: LABCELL_X39_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~38_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~0_combout\); + +-- Location: FF_X39_Y25_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_NEW_REG724\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM725\); + +-- Location: FF_X35_Y25_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711~DUPLICATE_q\); + +-- Location: FF_X23_Y13_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(18)); + +-- Location: LABCELL_X36_Y28_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0_combout\); + +-- Location: LABCELL_X36_Y28_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\); + +-- Location: MLABCELL_X34_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2_combout\); + +-- Location: LABCELL_X35_Y32_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011110000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3_combout\); + +-- Location: MLABCELL_X37_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000000001001111010101000100111010101010010011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~1_combout\); + +-- Location: LABCELL_X36_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010100000000111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~2_combout\); + +-- Location: LABCELL_X35_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~3_RTM0729\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~3_RTM0729_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~2_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(18) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(18) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100011111000100010001111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~3_RTM0729_combout\); + +-- Location: FF_X35_Y25_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_NEW_REG727\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~3_RTM0729_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM728\); + +-- Location: FF_X35_Y26_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG622\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\); + +-- Location: LABCELL_X39_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM728\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM723\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM728\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM725\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM728\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711~DUPLICATE_q\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM728\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111110011111111111100000000111111110101111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM723\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM725\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM711~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM728\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM715\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM623\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\); + +-- Location: LABCELL_X40_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[50]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[50]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[50]~feeder_combout\); + +-- Location: FF_X40_Y16_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[50]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(50)); + +-- Location: LABCELL_X40_Y16_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[50]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[50]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[50]~feeder_combout\); + +-- Location: FF_X40_Y16_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[50]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(50)); + +-- Location: FF_X40_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(50)); + +-- Location: FF_X40_Y25_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(50)); + +-- Location: LABCELL_X40_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(50) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(50)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(50)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(50) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(50) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(50)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(50))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(50) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(50)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(50))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(50) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(50)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(50))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101010001000010110101101110100001111100011010101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(50), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(50), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(50), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~0_combout\); + +-- Location: LABCELL_X40_Y19_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[50]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[50]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[50]~feeder_combout\); + +-- Location: FF_X40_Y19_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[50]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(50)); + +-- Location: FF_X39_Y25_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(50)); + +-- Location: FF_X39_Y19_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(50)); + +-- Location: FF_X39_Y19_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(50)); + +-- Location: LABCELL_X39_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(50) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(50))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(50))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(50) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(50) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(50))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(50)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(50) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(50))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(50)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(50) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(50))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(50)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010001000100101111101110111000010100111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(50), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(50), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(50), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~1_combout\); + +-- Location: LABCELL_X39_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux43~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux43~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~2_combout\); + +-- Location: FF_X39_Y19_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(50)); + +-- Location: FF_X34_Y35_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_OTERM2463\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(50)); + +-- Location: LABCELL_X36_Y28_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000011010111110000001101010000111100110101111111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~1_combout\); + +-- Location: LABCELL_X35_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~0_combout\); + +-- Location: MLABCELL_X34_Y35_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13210\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13210_BDD13211\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux176~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101000001000001010110101110101111111010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1576~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1576~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13210_BDD13211\); + +-- Location: MLABCELL_X34_Y35_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13212\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(50) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13210_BDD13211\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(50) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13210_BDD13211\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]_NEW2462_RESYN13210_BDD13211\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(50), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\); + +-- Location: MLABCELL_X34_Y35_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_OTERM2463\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101110101001010101000101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_OTERM2463\); + +-- Location: FF_X34_Y35_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_OTERM2463\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE_q\); + +-- Location: LABCELL_X41_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[50]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[50]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[50]~feeder_combout\); + +-- Location: FF_X41_Y20_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[50]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(50)); + +-- Location: LABCELL_X39_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[50]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[50]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[50]~feeder_combout\); + +-- Location: FF_X39_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[50]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(50)); + +-- Location: FF_X39_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(50)); + +-- Location: FF_X42_Y20_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(50)); + +-- Location: LABCELL_X39_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(50) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(50))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(50))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(50) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(50) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(50))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(50)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(50) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(50))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(50)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(50) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(50))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(50)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011111101011111001100000101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(50), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(50), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(50), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~1_combout\); + +-- Location: FF_X41_Y21_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(50)); + +-- Location: LABCELL_X41_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[50]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[50]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[50]~feeder_combout\); + +-- Location: FF_X41_Y22_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[50]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(50)); + +-- Location: FF_X41_Y22_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(50)); + +-- Location: LABCELL_X41_Y22_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[50]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[50]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[50]~feeder_combout\); + +-- Location: FF_X41_Y22_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[50]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(50)); + +-- Location: LABCELL_X41_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(50) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(50)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(50)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(50) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(50) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(50)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(50))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(50) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(50)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(50))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(50) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(50)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(50))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101010001000010110101101110100001111100011010101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(50), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(50), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(50), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~0_combout\); + +-- Location: LABCELL_X39_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux235~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux235~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~2_combout\); + +-- Location: FF_X39_Y20_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(50)); + +-- Location: MLABCELL_X37_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13362\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13362_BDD13363\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111100111111001101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13362_BDD13363\); + +-- Location: MLABCELL_X37_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13364\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ +-- & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13362_BDD13363\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\) ) ) +-- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13362_BDD13363\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001111010001000101010100111111000011110111011101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[50]_NEW2563_RESYN13362_BDD13363\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(50), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\); + +-- Location: MLABCELL_X37_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_OTERM2564\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000001101011111110111100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_OTERM2564\); + +-- Location: FF_X37_Y26_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_OTERM2564\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50)); + +-- Location: FF_X39_Y22_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(50)); + +-- Location: FF_X39_Y22_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(50)); + +-- Location: FF_X39_Y14_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(50)); + +-- Location: FF_X39_Y22_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(50)); + +-- Location: LABCELL_X39_Y22_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(50)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(50) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(50)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(50) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(50)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(50))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(50) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(50)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(50))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(50), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(50), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(50), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~1_combout\); + +-- Location: FF_X40_Y20_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(50)); + +-- Location: MLABCELL_X37_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[50]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[50]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(50), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[50]~feeder_combout\); + +-- Location: FF_X37_Y18_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[50]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(50)); + +-- Location: FF_X40_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(50)); + +-- Location: MLABCELL_X37_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[50]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[50]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(50), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[50]~feeder_combout\); + +-- Location: FF_X37_Y22_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[50]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(50)); + +-- Location: LABCELL_X40_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(50) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(50))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(50)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(50) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(50) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(50)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(50) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(50))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(50) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(50) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(50) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(50) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(50) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000010001000011001101110100111111000100010011111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(50), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(50), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(50), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~0_combout\); + +-- Location: LABCELL_X40_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux171~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux171~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~2_combout\); + +-- Location: FF_X40_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(50)); + +-- Location: LABCELL_X36_Y28_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100001111110100010000001100011101110011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][2]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~0_combout\); + +-- Location: LABCELL_X35_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~49_sumout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add44~49_sumout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~49_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\); + +-- Location: LABCELL_X35_Y32_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~1_combout\); + +-- Location: LABCELL_X39_Y27_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13206\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13206_BDD13207\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011010100000101000000000011111100110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1460~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1460~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13206_BDD13207\); + +-- Location: LABCELL_X39_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13208\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13206_BDD13207\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13206_BDD13207\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001111000000001100111100110000111111110011000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[50]_NEW2460_RESYN13206_BDD13207\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(50), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\); + +-- Location: LABCELL_X39_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_OTERM2461\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_OTERM2461\); + +-- Location: FF_X39_Y27_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_OTERM2461\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50)); + +-- Location: FF_X39_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(50)); + +-- Location: FF_X41_Y20_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(50)); + +-- Location: FF_X42_Y20_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(50)); + +-- Location: FF_X39_Y20_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(50)); + +-- Location: LABCELL_X39_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(50)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(50) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(50) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(50) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(50))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(50)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(50) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(50))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(50)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(50), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(50), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(50), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~1_combout\); + +-- Location: FF_X40_Y20_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(50)); + +-- Location: FF_X40_Y21_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(50)); + +-- Location: FF_X40_Y22_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(50)); + +-- Location: FF_X40_Y20_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(50)); + +-- Location: LABCELL_X40_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(50)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(50))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(50) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(50)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(50))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(50) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(50)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(50) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(50)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(50), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(50), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(50), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~0_combout\); + +-- Location: LABCELL_X40_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux107~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux107~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~2_combout\); + +-- Location: FF_X40_Y20_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(50)); + +-- Location: LABCELL_X40_Y20_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(50) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(50) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(50) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(50) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(50), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(50), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(50), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(50), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~0_combout\); + +-- Location: LABCELL_X32_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(18))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(18)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(18) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(18)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111000001010000010100110000001111111111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(18), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(18), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(18), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~1_combout\); + +-- Location: LABCELL_X35_Y12_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~1_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(18) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(18) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010100010000001111010011101010010111100100101011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(42), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(46), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(18), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~2_combout\); + +-- Location: LABCELL_X36_Y12_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[50]_NEW1804\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[50]_OTERM1805\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(50))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(49))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(50))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(49)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(49), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(50), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[50]_OTERM1805\); + +-- Location: FF_X36_Y12_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[50]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[50]_OTERM1805\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(50)); + +-- Location: FF_X35_Y12_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]_OTERM1801\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]~DUPLICATE_q\); + +-- Location: LABCELL_X29_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[19]_NEW1984\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[19]_OTERM1985\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(19))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(19))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[19]_OTERM1985\); + +-- Location: FF_X29_Y19_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[19]_OTERM1985\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(19)); + +-- Location: LABCELL_X32_Y11_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(19) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[19]~feeder_combout\); + +-- Location: FF_X32_Y11_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(19)); + +-- Location: LABCELL_X24_Y11_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[19]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(19) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[19]~feeder_combout\); + +-- Location: FF_X24_Y11_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(19)); + +-- Location: FF_X24_Y11_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(19)); + +-- Location: FF_X29_Y11_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(19)); + +-- Location: LABCELL_X29_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(19)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(19) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(19)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(19)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~1_combout\); + +-- Location: MLABCELL_X28_Y12_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(19) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[19]~feeder_combout\); + +-- Location: FF_X28_Y12_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(19)); + +-- Location: LABCELL_X32_Y11_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(19) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[19]~feeder_combout\); + +-- Location: FF_X32_Y11_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(19)); + +-- Location: FF_X32_Y11_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(19)); + +-- Location: MLABCELL_X28_Y12_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(19) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[19]~feeder_combout\); + +-- Location: FF_X28_Y12_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(19)); + +-- Location: LABCELL_X32_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(19) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(19) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(19)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(19) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(19))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(19) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(19))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110111010101000011011010101010001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~0_combout\); + +-- Location: LABCELL_X29_Y11_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000000000000001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux304~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux304~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~2_combout\); + +-- Location: FF_X29_Y11_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(19)); + +-- Location: FF_X20_Y17_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(19)); + +-- Location: LABCELL_X20_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[19]_NEW2080\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[19]_OTERM2081\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(19))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(19)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(19) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[19]_OTERM2081\); + +-- Location: FF_X20_Y17_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[19]_OTERM2081\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(19)); + +-- Location: FF_X28_Y17_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(19)); + +-- Location: FF_X29_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(19)); + +-- Location: FF_X29_Y17_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(19)); + +-- Location: FF_X29_Y17_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(19)); + +-- Location: LABCELL_X29_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(19)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(19) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(19)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(19)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~0_combout\); + +-- Location: FF_X24_Y16_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(19)); + +-- Location: FF_X24_Y16_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(19)); + +-- Location: FF_X25_Y16_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(19)); + +-- Location: FF_X24_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(19)); + +-- Location: LABCELL_X24_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(19)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(19)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(19))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(19))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~1_combout\); + +-- Location: LABCELL_X31_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux390~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux390~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~2_combout\); + +-- Location: FF_X31_Y15_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(19)); + +-- Location: LABCELL_X29_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078_RESYN12838\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(19))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000011000000010000001111101111110011111110111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\); + +-- Location: LABCELL_X29_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_OTERM2079\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000010000000110011110111111100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_OTERM2079\); + +-- Location: FF_X29_Y20_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_OTERM2079\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19)); + +-- Location: LABCELL_X29_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[19]~feeder_combout\); + +-- Location: FF_X29_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(19)); + +-- Location: LABCELL_X29_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[19]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[19]~feeder_combout\); + +-- Location: FF_X29_Y15_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(19)); + +-- Location: FF_X32_Y16_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(19)); + +-- Location: FF_X29_Y15_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(19)); + +-- Location: LABCELL_X29_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(19)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(19) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(19))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(19))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~1_combout\); + +-- Location: FF_X29_Y17_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(19)); + +-- Location: FF_X31_Y17_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(19)); + +-- Location: LABCELL_X29_Y17_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[19]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(19), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[19]~feeder_combout\); + +-- Location: FF_X29_Y17_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(19)); + +-- Location: FF_X29_Y17_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(19)); + +-- Location: LABCELL_X29_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(19))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(19))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(19)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(19) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(19)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~0_combout\); + +-- Location: LABCELL_X32_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux328~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux328~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~2_combout\); + +-- Location: FF_X32_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(19)); + +-- Location: LABCELL_X19_Y15_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[19]_NEW2076\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[19]_OTERM2077\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(19)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(19)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[19]_OTERM2077\); + +-- Location: FF_X19_Y15_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[19]_OTERM2077\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19)); + +-- Location: FF_X26_Y15_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(19)); + +-- Location: FF_X25_Y15_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(19)); + +-- Location: FF_X26_Y15_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(19)); + +-- Location: FF_X26_Y15_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(19)); + +-- Location: LABCELL_X26_Y15_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(19)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(19)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(19)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(19)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(19), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~1_combout\); + +-- Location: FF_X28_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(19)); + +-- Location: FF_X26_Y16_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(19)); + +-- Location: FF_X28_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(19)); + +-- Location: FF_X28_Y16_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(19)); + +-- Location: MLABCELL_X28_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(19)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(19) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(19) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(19))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(19))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(19), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~0_combout\); + +-- Location: LABCELL_X32_Y15_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux358~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux358~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~2_combout\); + +-- Location: FF_X32_Y15_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(19)); + +-- Location: LABCELL_X35_Y33_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~1_combout\); + +-- Location: LABCELL_X35_Y38_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111110011001100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~0_combout\); + +-- Location: LABCELL_X36_Y26_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13182\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13182_BDD13183\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(3))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~0_combout\ +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100010001000111011100111111001111110100010001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1459~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1459~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13182_BDD13183\); + +-- Location: LABCELL_X35_Y26_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13184\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13182_BDD13183\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13182_BDD13183\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[51]_NEW2448_RESYN13182_BDD13183\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\); + +-- Location: LABCELL_X35_Y26_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_OTERM2449\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100101111000000001101000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(51), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_OTERM2449\); + +-- Location: FF_X35_Y26_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_OTERM2449\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51)); + +-- Location: FF_X37_Y23_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(51)); + +-- Location: FF_X37_Y21_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(51)); + +-- Location: FF_X37_Y21_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(51)); + +-- Location: FF_X37_Y21_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(51)); + +-- Location: MLABCELL_X37_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(51) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(51))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(51))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(51) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(51))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(51)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(51) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(51))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(51)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(51) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(51))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(51)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001001100010000110100111101110000011111000111001101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(51), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(51), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(51), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~1_combout\); + +-- Location: FF_X43_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(51)); + +-- Location: FF_X43_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(51)); + +-- Location: FF_X43_Y17_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(51)); + +-- Location: LABCELL_X47_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[51]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[51]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[51]~feeder_combout\); + +-- Location: FF_X47_Y19_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[51]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(51)); + +-- Location: LABCELL_X43_Y17_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(51) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(51))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(51))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(51) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(51)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(51) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(51) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(51) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(51) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(51))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(51) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(51) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(51))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(51)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111010101010010011110101010001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(51), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(51), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(51), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~0_combout\); + +-- Location: LABCELL_X43_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux106~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux106~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~2_combout\); + +-- Location: FF_X43_Y19_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(51)); + +-- Location: LABCELL_X35_Y38_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010010111110010001000001010011101110101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~1_combout\); + +-- Location: LABCELL_X35_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001111100110001000111001100110100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~0_combout\); + +-- Location: MLABCELL_X34_Y35_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13186\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13186_BDD13187\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~0_combout\)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux175~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101000001000001010110101110101111111010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1575~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1575~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13186_BDD13187\); + +-- Location: MLABCELL_X34_Y35_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13188\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13186_BDD13187\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13186_BDD13187\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[51]_NEW2450_RESYN13186_BDD13187\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\); + +-- Location: MLABCELL_X34_Y35_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_OTERM2451\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101110101001010101000101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(51), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_OTERM2451\); + +-- Location: FF_X34_Y35_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_OTERM2451\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51)); + +-- Location: FF_X44_Y19_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(51)); + +-- Location: FF_X42_Y20_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(51)); + +-- Location: FF_X42_Y20_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(51)); + +-- Location: FF_X42_Y20_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(51)); + +-- Location: MLABCELL_X42_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(51) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(51))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(51))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(51) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(51))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(51)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(51) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(51))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(51)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(51) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(51))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(51)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000101010001001010010111101110000011110100111010101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(51), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(51), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(51), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~1_combout\); + +-- Location: MLABCELL_X37_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[51]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[51]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[51]~feeder_combout\); + +-- Location: FF_X37_Y22_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[51]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(51)); + +-- Location: FF_X43_Y27_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(51)); + +-- Location: FF_X43_Y19_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(51)); + +-- Location: LABCELL_X43_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[51]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[51]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[51]~feeder_combout\); + +-- Location: FF_X43_Y19_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[51]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(51)); + +-- Location: LABCELL_X43_Y19_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(51) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(51))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(51))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(51) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(51))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(51)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(51) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(51))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(51)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(51) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(51) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(51))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(51)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000011000001011111001111110101000000111111010111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(51), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(51), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(51), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~0_combout\); + +-- Location: LABCELL_X43_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux234~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux234~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~2_combout\); + +-- Location: FF_X43_Y19_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(51)); + +-- Location: LABCELL_X35_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000011110000111100000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~38_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~0_combout\); + +-- Location: FF_X35_Y25_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG712\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM713\); + +-- Location: FF_X35_Y25_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG710\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711\); + +-- Location: FF_X35_Y25_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG708\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM709\); + +-- Location: MLABCELL_X23_Y13_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[19]~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~33_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[19]~feeder_combout\); + +-- Location: FF_X23_Y13_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[19]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(19)); + +-- Location: LABCELL_X35_Y33_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111111111111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~3_combout\); + +-- Location: LABCELL_X35_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~2_combout\); + +-- Location: LABCELL_X35_Y38_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~0_combout\); + +-- Location: LABCELL_X35_Y38_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~1_combout\); + +-- Location: MLABCELL_X37_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~3_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~3_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~3_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux331~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011100010011010101101000101011001111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~1_combout\); + +-- Location: MLABCELL_X34_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~2_combout\); + +-- Location: LABCELL_X35_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~3_RTM0720\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~3_RTM0720_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~2_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(19) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~2_combout\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(19) & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011010101010111011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~3_RTM0720_combout\); + +-- Location: FF_X35_Y25_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG718\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~3_RTM0720_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM719\); + +-- Location: LABCELL_X35_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM709\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM719\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM709\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM719\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM709\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM719\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM713\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM709\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM719\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM713\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000110011001000110011001111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM713\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM715\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM623\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM711\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM709\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM719\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\); + +-- Location: FF_X37_Y21_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(51)); + +-- Location: FF_X37_Y23_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(51)); + +-- Location: FF_X37_Y21_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(51)); + +-- Location: FF_X37_Y21_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(51)); + +-- Location: MLABCELL_X37_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(51) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(51)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(51)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(51) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(51))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(51) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(51) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(51) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(51) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(51)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(51) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(51)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(51))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110110101010100011011101010100001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(51), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(51), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(51), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~1_combout\); + +-- Location: LABCELL_X50_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[51]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[51]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[51]~feeder_combout\); + +-- Location: FF_X50_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[51]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(51)); + +-- Location: FF_X44_Y17_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(51)); + +-- Location: LABCELL_X41_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[51]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[51]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[51]~feeder_combout\); + +-- Location: FF_X41_Y24_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[51]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(51)); + +-- Location: FF_X44_Y17_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(51)); + +-- Location: LABCELL_X44_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(51)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(51) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(51) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(51) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(51))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(51)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(51) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(51))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(51)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(51), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(51), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(51), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(51), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~0_combout\); + +-- Location: LABCELL_X43_Y19_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux42~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux42~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~2_combout\); + +-- Location: FF_X43_Y19_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(51)); + +-- Location: MLABCELL_X37_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~2_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~3_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\); + +-- Location: MLABCELL_X37_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13368\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011101000101111001101010111000000111111011111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\); + +-- Location: MLABCELL_X37_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_OTERM2567\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011110111001111111100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(51), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_OTERM2567\); + +-- Location: FF_X37_Y24_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_OTERM2567\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51)); + +-- Location: FF_X40_Y17_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(51)); + +-- Location: FF_X40_Y17_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(51)); + +-- Location: FF_X40_Y17_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(51)); + +-- Location: LABCELL_X41_Y18_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[51]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[51]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[51]~feeder_combout\); + +-- Location: FF_X41_Y18_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[51]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(51)); + +-- Location: LABCELL_X40_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(51) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(51)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(51)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(51) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(51) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(51))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(51) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(51) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(51) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(51))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(51)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(51) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(51) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(51)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(51))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101001100010011110111000001110011011111000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(51), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(51), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(51), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(51), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~0_combout\); + +-- Location: FF_X42_Y19_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(51)); + +-- Location: FF_X42_Y19_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(51)); + +-- Location: FF_X37_Y23_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(51)); + +-- Location: FF_X42_Y19_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(51)); + +-- Location: MLABCELL_X42_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(51) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(51)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(51) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(51) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(51) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(51)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(51))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(51) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(51)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(51))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(51), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(51), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(51), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(51), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~1_combout\); + +-- Location: LABCELL_X43_Y19_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux170~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux170~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~2_combout\); + +-- Location: FF_X43_Y19_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(51)); + +-- Location: LABCELL_X43_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(51) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(51) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(51) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(51) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(51), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(51), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(51), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(51), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~0_combout\); + +-- Location: LABCELL_X32_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(19)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(19))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(19)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(19) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(19)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000100010001000100001100001111111101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(19), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(19), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~1_combout\); + +-- Location: LABCELL_X36_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(43))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(19)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(43))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(19)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000001100000011111101011111010111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[47]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(43), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(19), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~2_combout\); + +-- Location: LABCELL_X36_Y12_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[51]_NEW1802\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[51]_OTERM1803\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(51))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(50))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(51))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(50)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(50), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(51), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[51]_OTERM1803\); + +-- Location: FF_X36_Y12_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[51]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[51]_OTERM1803\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(51)); + +-- Location: LABCELL_X31_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[20]_NEW1992\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[20]_OTERM1993\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[20]_OTERM1993\); + +-- Location: FF_X31_Y19_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[20]_OTERM1993\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20)); + +-- Location: FF_X34_Y16_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(20)); + +-- Location: FF_X36_Y17_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(20)); + +-- Location: FF_X36_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(20)); + +-- Location: FF_X36_Y17_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(20)); + +-- Location: LABCELL_X36_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(20)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(20))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(20))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~0_combout\); + +-- Location: MLABCELL_X34_Y15_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[20]~feeder_combout\); + +-- Location: FF_X34_Y15_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(20)); + +-- Location: FF_X31_Y15_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(20)); + +-- Location: LABCELL_X29_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[20]~feeder_combout\); + +-- Location: FF_X29_Y15_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(20)); + +-- Location: FF_X31_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(20)); + +-- Location: LABCELL_X31_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(20) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(20)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(20)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~1_combout\); + +-- Location: LABCELL_X32_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010110101010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux303~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux303~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~2_combout\); + +-- Location: FF_X32_Y15_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(20)); + +-- Location: LABCELL_X21_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[20]_NEW2112\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[20]_OTERM2113\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(20))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(20))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[20]_OTERM2113\); + +-- Location: FF_X21_Y17_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[20]_OTERM2113\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20)); + +-- Location: LABCELL_X26_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[20]~feeder_combout\); + +-- Location: FF_X26_Y15_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(20)); + +-- Location: FF_X25_Y16_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(20)); + +-- Location: FF_X24_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(20)); + +-- Location: FF_X24_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(20)); + +-- Location: LABCELL_X24_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(20) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(20))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(20))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(20))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010100010000001111010011101010010111100100101011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~1_combout\); + +-- Location: FF_X26_Y16_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(20)); + +-- Location: FF_X26_Y16_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(20)); + +-- Location: FF_X25_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(20)); + +-- Location: FF_X25_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(20)); + +-- Location: LABCELL_X25_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(20)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(20)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(20) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~0_combout\); + +-- Location: LABCELL_X31_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux357~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux357~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~2_combout\); + +-- Location: FF_X31_Y15_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(20)); + +-- Location: LABCELL_X29_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114_RESYN12850\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20) +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000011000000010000001111101111110011111110111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[20]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\); + +-- Location: LABCELL_X29_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_OTERM2115\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ +-- & (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001000110011111111011100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_OTERM2115\); + +-- Location: FF_X29_Y20_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_OTERM2115\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20)); + +-- Location: FF_X34_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(20)); + +-- Location: FF_X34_Y15_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(20)); + +-- Location: FF_X34_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(20)); + +-- Location: LABCELL_X32_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[20]~feeder_combout\); + +-- Location: FF_X32_Y15_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(20)); + +-- Location: MLABCELL_X34_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(20) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(20))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(20)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(20))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(20))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(20)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(20) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(20))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011100000100110001111111010000110111001101001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~1_combout\); + +-- Location: FF_X29_Y14_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(20)); + +-- Location: FF_X29_Y18_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(20)); + +-- Location: LABCELL_X31_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[20]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[20]~feeder_combout\); + +-- Location: FF_X31_Y16_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(20)); + +-- Location: FF_X31_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(20)); + +-- Location: LABCELL_X31_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(20) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(20)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(20)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~0_combout\); + +-- Location: LABCELL_X32_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux327~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux327~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~2_combout\); + +-- Location: FF_X32_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(20)); + +-- Location: FF_X19_Y17_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[20]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[20]~DUPLICATE_q\); + +-- Location: LABCELL_X21_Y17_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[20]_NEW2116\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[20]_OTERM2117\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[20]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[20]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[20]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[20]_OTERM2117\); + +-- Location: FF_X21_Y17_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[20]_OTERM2117\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20)); + +-- Location: FF_X26_Y16_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(20)); + +-- Location: FF_X26_Y16_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(20)); + +-- Location: FF_X29_Y16_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(20)); + +-- Location: FF_X26_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(20)); + +-- Location: LABCELL_X26_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(20)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(20)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(20) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(20), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~0_combout\); + +-- Location: LABCELL_X26_Y15_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[20]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[20]~feeder_combout\); + +-- Location: FF_X26_Y15_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[20]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(20)); + +-- Location: FF_X25_Y15_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(20)); + +-- Location: FF_X26_Y15_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(20)); + +-- Location: FF_X26_Y15_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(20)); + +-- Location: LABCELL_X26_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(20) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(20) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(20))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(20))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(20) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(20))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010000100111001101101000110110011100101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(20), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(20), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~1_combout\); + +-- Location: LABCELL_X32_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux389~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux389~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~2_combout\); + +-- Location: FF_X32_Y15_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(20)); + +-- Location: MLABCELL_X23_Y36_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~0_combout\); + +-- Location: MLABCELL_X23_Y36_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101101010101111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~1_combout\); + +-- Location: LABCELL_X35_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13218\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13218_BDD13219\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~1_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001111100110001000111001100110100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1458~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1458~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13218_BDD13219\); + +-- Location: LABCELL_X35_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13220\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13218_BDD13219\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13218_BDD13219\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[52]_NEW2466_RESYN13218_BDD13219\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(52), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\); + +-- Location: LABCELL_X35_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_OTERM2467\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110010000000000000110111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_OTERM2467\); + +-- Location: FF_X35_Y26_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_OTERM2467\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52)); + +-- Location: LABCELL_X36_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[52]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[52]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(52), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[52]~feeder_combout\); + +-- Location: FF_X36_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[52]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(52)); + +-- Location: LABCELL_X36_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[52]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[52]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(52), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[52]~feeder_combout\); + +-- Location: FF_X36_Y15_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[52]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(52)); + +-- Location: FF_X36_Y15_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(52)); + +-- Location: LABCELL_X39_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[52]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[52]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(52), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[52]~feeder_combout\); + +-- Location: FF_X39_Y15_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[52]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(52)); + +-- Location: LABCELL_X36_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(52) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(52) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(52) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(52) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(52)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(52) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(52))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(52) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(52) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(52))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101011111000000110101000011110011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(52), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(52), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(52), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~0_combout\); + +-- Location: FF_X40_Y15_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(52)); + +-- Location: LABCELL_X40_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[52]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[52]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(52), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[52]~feeder_combout\); + +-- Location: FF_X40_Y15_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[52]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(52)); + +-- Location: FF_X40_Y15_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(52)); + +-- Location: FF_X37_Y15_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(52)); + +-- Location: LABCELL_X40_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(52) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(52))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(52)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(52) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(52))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(52) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(52) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(52) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(52))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(52)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(52) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(52))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(52) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011010000101010001111110110000101110101011010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(52), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(52), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(52), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~1_combout\); + +-- Location: LABCELL_X39_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux105~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux105~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~2_combout\); + +-- Location: FF_X39_Y15_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(52)); + +-- Location: FF_X28_Y29_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG618\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM619\); + +-- Location: FF_X35_Y25_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG626\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM627\); + +-- Location: LABCELL_X32_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617~feeder_combout\); + +-- Location: FF_X32_Y21_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG616\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617\); + +-- Location: FF_X23_Y13_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(20)); + +-- Location: MLABCELL_X23_Y36_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001000100010001001110111011101110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1_combout\); + +-- Location: MLABCELL_X23_Y36_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0_combout\); + +-- Location: MLABCELL_X23_Y36_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\); + +-- Location: MLABCELL_X23_Y36_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][4]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3_combout\); + +-- Location: MLABCELL_X23_Y36_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010100010010100101111001000000111101001110101011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~1_combout\); + +-- Location: LABCELL_X35_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100110011001100110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~2_combout\); + +-- Location: LABCELL_X32_Y21_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~2_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000011110011111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~3_combout\); + +-- Location: FF_X32_Y21_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG628\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM629\); + +-- Location: FF_X32_Y21_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG624\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM625\); + +-- Location: FF_X28_Y29_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG620\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM621\); + +-- Location: LABCELL_X32_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM627\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM621\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM625\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM619\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM629\) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM627\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM629\)) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001000111111111000000111111111100010011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM619\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM627\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM617\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM629\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM623\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM625\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM621\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\); + +-- Location: LABCELL_X36_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[52]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[52]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[52]~feeder_combout\); + +-- Location: FF_X36_Y21_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[52]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(52)); + +-- Location: FF_X41_Y19_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(52)); + +-- Location: FF_X41_Y19_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(52)); + +-- Location: FF_X41_Y19_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(52)); + +-- Location: LABCELL_X41_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(52)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(52) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(52) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(52))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(52))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(52), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(52), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(52), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~1_combout\); + +-- Location: LABCELL_X39_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[52]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[52]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[52]~feeder_combout\); + +-- Location: FF_X39_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[52]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(52)); + +-- Location: FF_X39_Y16_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(52)); + +-- Location: LABCELL_X40_Y16_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[52]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[52]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[52]~feeder_combout\); + +-- Location: FF_X40_Y16_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[52]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(52)); + +-- Location: FF_X39_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(52)); + +-- Location: LABCELL_X39_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(52)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(52) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(52)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(52))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(52))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(52), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(52), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(52), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~0_combout\); + +-- Location: LABCELL_X39_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux41~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux41~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~2_combout\); + +-- Location: FF_X39_Y15_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(52)); + +-- Location: MLABCELL_X23_Y36_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][4]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~1_combout\); + +-- Location: MLABCELL_X23_Y36_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][4]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][4]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~0_combout\); + +-- Location: MLABCELL_X23_Y36_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13222\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13222_BDD13223\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux174~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000000000111111110011111100111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1574~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1574~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13222_BDD13223\); + +-- Location: MLABCELL_X34_Y34_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13224\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13222_BDD13223\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13222_BDD13223\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011011101000000001101110100100010111111110010001011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[52]_NEW2468_RESYN13222_BDD13223\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(52), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\); + +-- Location: MLABCELL_X34_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_OTERM2469\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_OTERM2469\); + +-- Location: FF_X34_Y34_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_OTERM2469\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52)); + +-- Location: FF_X42_Y24_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(52)); + +-- Location: FF_X37_Y29_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(52)); + +-- Location: FF_X42_Y24_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(52)); + +-- Location: MLABCELL_X42_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[52]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[52]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(52), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[52]~feeder_combout\); + +-- Location: FF_X42_Y24_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[52]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(52)); + +-- Location: MLABCELL_X42_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(52) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(52) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(52) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(52))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(52) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(52) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(52) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(52)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(52) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(52))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100000000000111010011001100011101110011000001110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(52), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(52), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(52), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~1_combout\); + +-- Location: FF_X42_Y26_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(52)); + +-- Location: FF_X43_Y25_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(52)); + +-- Location: FF_X42_Y26_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(52)); + +-- Location: FF_X43_Y25_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(52)); + +-- Location: LABCELL_X43_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(52))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(52))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(52)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(52) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(52) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(52), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(52), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(52), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~0_combout\); + +-- Location: LABCELL_X43_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000000000000000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux233~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux233~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~2_combout\); + +-- Location: FF_X43_Y25_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(52)); + +-- Location: MLABCELL_X23_Y36_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13398\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\); + +-- Location: LABCELL_X40_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13400\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52) & ( +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001100000000001000111010111101110011010100000111001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(52), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\); + +-- Location: LABCELL_X40_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_OTERM2589\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_OTERM2589\); + +-- Location: FF_X40_Y26_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_OTERM2589\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52)); + +-- Location: FF_X42_Y19_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(52)); + +-- Location: FF_X42_Y19_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(52)); + +-- Location: FF_X40_Y19_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(52)); + +-- Location: FF_X42_Y19_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(52)); + +-- Location: MLABCELL_X42_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(52)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(52) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(52)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(52))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(52))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(52), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(52), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(52), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~1_combout\); + +-- Location: FF_X41_Y17_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(52)); + +-- Location: FF_X43_Y17_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(52)); + +-- Location: FF_X43_Y19_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(52)); + +-- Location: FF_X43_Y19_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(52)); + +-- Location: LABCELL_X43_Y19_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(52) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(52)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(52)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(52) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(52) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(52))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(52) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(52) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(52))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(52)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(52) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(52))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101001100010011110111000001110011011111000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(52), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(52), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(52), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~0_combout\); + +-- Location: LABCELL_X43_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux169~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux169~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~2_combout\); + +-- Location: FF_X43_Y19_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(52)); + +-- Location: LABCELL_X39_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(52) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(52)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(52) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(52)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(52))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(52) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(52)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(52))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(52), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(52), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(52), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~0_combout\); + +-- Location: LABCELL_X32_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(20)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(20)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(20)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(20)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010010111110101111100100010011101110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(20), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~1_combout\); + +-- Location: LABCELL_X35_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(48)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(20)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(48)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(20) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(48))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(20)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(48))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(20) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110100001010100011111000100001011101010110101101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(20), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(48), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[44]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~2_combout\); + +-- Location: LABCELL_X36_Y12_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[52]_NEW1812\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[52]_OTERM1813\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(52))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(51))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(52))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(51)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(51), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(52), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[52]_OTERM1813\); + +-- Location: FF_X36_Y12_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[52]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[52]_OTERM1813\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(52)); + +-- Location: LABCELL_X29_Y19_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[21]_NEW1988\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[21]_OTERM1989\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(21))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[21]_OTERM1989\); + +-- Location: FF_X29_Y19_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[21]_OTERM1989\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(21)); + +-- Location: FF_X26_Y13_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(21)); + +-- Location: FF_X25_Y13_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(21)); + +-- Location: FF_X25_Y13_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(21)); + +-- Location: FF_X25_Y13_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(21)); + +-- Location: LABCELL_X25_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(21) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(21))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(21))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(21)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(21))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(21)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(21))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(21)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010001000100101111101110111000010100111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~1_combout\); + +-- Location: FF_X26_Y13_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(21)); + +-- Location: LABCELL_X39_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(21) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[21]~feeder_combout\); + +-- Location: FF_X39_Y13_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(21)); + +-- Location: MLABCELL_X37_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(21) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[21]~feeder_combout\); + +-- Location: FF_X37_Y13_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(21)); + +-- Location: FF_X37_Y13_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(21)); + +-- Location: MLABCELL_X37_Y13_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(21)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(21)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(21))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(21))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~0_combout\); + +-- Location: LABCELL_X36_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux302~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux302~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~2_combout\); + +-- Location: FF_X36_Y13_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(21)); + +-- Location: LABCELL_X24_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[21]_NEW2132\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[21]_OTERM2133\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[21]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[21]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[21]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[21]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101010000010111110101000001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[21]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[21]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[21]_OTERM2133\); + +-- Location: FF_X24_Y15_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[21]_OTERM2133\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21)); + +-- Location: LABCELL_X26_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[21]~feeder_combout\); + +-- Location: FF_X26_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(21)); + +-- Location: LABCELL_X25_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[21]~feeder_combout\); + +-- Location: FF_X25_Y15_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(21)); + +-- Location: LABCELL_X26_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[21]~feeder_combout\); + +-- Location: FF_X26_Y15_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(21)); + +-- Location: FF_X26_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(21)); + +-- Location: LABCELL_X26_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(21)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(21) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(21))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(21))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~1_combout\); + +-- Location: FF_X31_Y16_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(21)); + +-- Location: FF_X36_Y16_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(21)); + +-- Location: FF_X36_Y16_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(21)); + +-- Location: LABCELL_X26_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[21]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[21]~feeder_combout\); + +-- Location: FF_X26_Y16_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(21)); + +-- Location: LABCELL_X36_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(21) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(21))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(21))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(21))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(21)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(21))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(21)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(21))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(21)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010011000111000001111111010000110100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~0_combout\); + +-- Location: LABCELL_X36_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux356~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux356~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~2_combout\); + +-- Location: FF_X36_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(21)); + +-- Location: FF_X23_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_OTERM2135\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134_RESYN12854\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\)) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000011000000010000001111101111110011111110111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[21]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\); + +-- Location: MLABCELL_X23_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_OTERM2135\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010001000000010010111011111110111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_OTERM2135\); + +-- Location: FF_X23_Y20_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_OTERM2135\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21)); + +-- Location: LABCELL_X29_Y15_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[21]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[21]~feeder_combout\); + +-- Location: FF_X29_Y15_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(21)); + +-- Location: FF_X32_Y16_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(21)); + +-- Location: FF_X29_Y15_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(21)); + +-- Location: FF_X29_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(21)); + +-- Location: LABCELL_X29_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(21)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(21))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(21))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~1_combout\); + +-- Location: FF_X36_Y16_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(21)); + +-- Location: FF_X31_Y16_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(21)); + +-- Location: LABCELL_X29_Y14_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[21]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[21]~feeder_combout\); + +-- Location: FF_X29_Y14_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(21)); + +-- Location: FF_X36_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(21)); + +-- Location: LABCELL_X36_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(21))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(21))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(21)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~0_combout\); + +-- Location: LABCELL_X36_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux326~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux326~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~2_combout\); + +-- Location: FF_X36_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(21)); + +-- Location: LABCELL_X24_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[21]_NEW2136\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[21]_OTERM2137\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(21))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(21)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(21) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[21]_OTERM2137\); + +-- Location: FF_X24_Y17_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[21]_OTERM2137\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(21)); + +-- Location: LABCELL_X26_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[21]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(21) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[21]~feeder_combout\); + +-- Location: FF_X26_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(21)); + +-- Location: LABCELL_X26_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[21]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(21) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[21]~feeder_combout\); + +-- Location: FF_X26_Y15_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(21)); + +-- Location: FF_X26_Y15_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(21)); + +-- Location: FF_X39_Y18_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(21)); + +-- Location: LABCELL_X26_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(21) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(21))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(21))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(21)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(21))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(21) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(21))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(21)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000100110000101010011011110001100101011101001110110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~1_combout\); + +-- Location: LABCELL_X29_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[21]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(21) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[21]~feeder_combout\); + +-- Location: FF_X29_Y16_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(21)); + +-- Location: FF_X36_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(21)); + +-- Location: FF_X36_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(21)); + +-- Location: FF_X26_Y16_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(21), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(21)); + +-- Location: LABCELL_X36_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(21) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(21)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(21))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(21))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(21) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(21))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(21) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(21))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001000011010011000100111101110000011100110111110001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(21), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~0_combout\); + +-- Location: LABCELL_X36_Y16_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux388~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux388~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~2_combout\); + +-- Location: FF_X36_Y16_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(21)); + +-- Location: MLABCELL_X28_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[21]~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[21]~feeder_combout\); + +-- Location: FF_X28_Y17_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[21]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(21)); + +-- Location: MLABCELL_X34_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~1_RTM0258\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~1_RTM0258_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(21) & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(21) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(21) & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(21) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000111111111101010111010101110101011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(21), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~1_RTM0258_combout\); + +-- Location: FF_X34_Y25_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_NEW_REG256\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~1_RTM0258_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM257\); + +-- Location: MLABCELL_X34_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111111111111000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~3_combout\); + +-- Location: MLABCELL_X34_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~0_combout\); + +-- Location: MLABCELL_X34_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1_combout\); + +-- Location: MLABCELL_X34_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2_combout\); + +-- Location: MLABCELL_X37_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111000001010000010100110000001111111111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~0_combout\); + +-- Location: FF_X32_Y25_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_NEW_REG254\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM255\); + +-- Location: LABCELL_X32_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227~feeder_combout\); + +-- Location: FF_X32_Y25_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG226\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\); + +-- Location: FF_X31_Y25_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_NEW_REG252\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM253\); + +-- Location: MLABCELL_X34_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM253\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM255\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM257\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM253\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM257\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM253\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM255\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM257\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM253\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM257\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001111110011111100110011111111110011111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM257\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM255\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM227\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM225\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM253\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\); + +-- Location: LABCELL_X40_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[53]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[53]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1393~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[53]~feeder_combout\); + +-- Location: FF_X40_Y16_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[53]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(53)); + +-- Location: LABCELL_X41_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[53]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[53]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1393~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[53]~feeder_combout\); + +-- Location: FF_X41_Y16_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[53]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(53)); + +-- Location: LABCELL_X41_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[53]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[53]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1393~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[53]~feeder_combout\); + +-- Location: FF_X41_Y16_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[53]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(53)); + +-- Location: FF_X41_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(53)); + +-- Location: LABCELL_X41_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(53)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(53) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(53) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(53) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(53)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(53))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(53) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(53)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(53))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(53), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(53), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(53), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~0_combout\); + +-- Location: FF_X36_Y21_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(53)); + +-- Location: FF_X36_Y21_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(53)); + +-- Location: FF_X37_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(53)); + +-- Location: FF_X36_Y21_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(53)); + +-- Location: LABCELL_X36_Y21_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(53)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(53) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(53) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(53) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(53)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(53))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(53) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(53)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(53))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(53), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(53), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(53), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~1_combout\); + +-- Location: LABCELL_X36_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux40~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux40~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~2_combout\); + +-- Location: FF_X36_Y16_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(53)); + +-- Location: FF_X35_Y26_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_OTERM2481\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(53)); + +-- Location: MLABCELL_X34_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100111111000001010011000011110101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][5]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~1_combout\); + +-- Location: MLABCELL_X34_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000010101010000111100110011111111110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~0_combout\); + +-- Location: LABCELL_X35_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13246\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13246_BDD13247\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\)))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011111101011111001100000101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1457~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1457~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13246_BDD13247\); + +-- Location: LABCELL_X35_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13248\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(53) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13246_BDD13247\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(53) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13246_BDD13247\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]_NEW2480_RESYN13246_BDD13247\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(53), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\); + +-- Location: LABCELL_X35_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_OTERM2481\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(53) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111110010000000000000110111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_OTERM2481\); + +-- Location: FF_X35_Y26_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_OTERM2481\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE_q\); + +-- Location: MLABCELL_X37_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[53]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[53]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[53]~feeder_combout\); + +-- Location: FF_X37_Y19_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[53]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(53)); + +-- Location: LABCELL_X40_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[53]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[53]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[53]~feeder_combout\); + +-- Location: FF_X40_Y17_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[53]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(53)); + +-- Location: FF_X41_Y18_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(53)); + +-- Location: LABCELL_X41_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[53]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[53]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[53]~feeder_combout\); + +-- Location: FF_X41_Y18_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[53]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(53)); + +-- Location: LABCELL_X41_Y18_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(53) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(53))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(53))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(53) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(53) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(53))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(53)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(53) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(53) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(53))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(53)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(53) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(53) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(53))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(53)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000011000100011100111111011101000000111101110111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(53), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(53), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(53), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~0_combout\); + +-- Location: MLABCELL_X37_Y20_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[53]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[53]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[53]~feeder_combout\); + +-- Location: FF_X37_Y20_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[53]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(53)); + +-- Location: FF_X36_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(53)); + +-- Location: FF_X36_Y20_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(53)); + +-- Location: FF_X36_Y20_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(53)); + +-- Location: LABCELL_X36_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(53) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(53))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(53))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(53) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(53) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(53))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(53))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(53) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(53) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(53)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(53))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(53) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(53) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(53))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(53)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100000110010101110100101010011011100011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(53), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(53), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(53), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~1_combout\); + +-- Location: LABCELL_X36_Y16_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux104~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux104~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~2_combout\); + +-- Location: FF_X36_Y16_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(53)); + +-- Location: FF_X35_Y26_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_OTERM2483\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(53)); + +-- Location: MLABCELL_X34_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111000000000011001101010101000011111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~0_combout\); + +-- Location: MLABCELL_X34_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011010101010000111111111111001100110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][5]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][5]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][5]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][5]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~1_combout\); + +-- Location: MLABCELL_X34_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13250\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13250_BDD13251\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux173~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000101010001000000010101000110101011111110111010101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1573~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1573~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13250_BDD13251\); + +-- Location: LABCELL_X35_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13252\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(53) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13250_BDD13251\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(53) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13250_BDD13251\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010111011000000001011101101000100111111110100010011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]_NEW2482_RESYN13250_BDD13251\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(53), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\); + +-- Location: LABCELL_X35_Y26_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_OTERM2483\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(53) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100101111000000001101000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_OTERM2483\); + +-- Location: FF_X35_Y26_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_OTERM2483\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE_q\); + +-- Location: FF_X43_Y17_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(53)); + +-- Location: FF_X42_Y17_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(53)); + +-- Location: FF_X43_Y17_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(53)); + +-- Location: FF_X43_Y17_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(53)); + +-- Location: LABCELL_X43_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(53))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(53)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(53))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(53)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(53) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(53)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(53) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(53)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111101000100011101110100010001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(53), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(53), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(53), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~0_combout\); + +-- Location: LABCELL_X36_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[53]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[53]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[53]~feeder_combout\); + +-- Location: FF_X36_Y20_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[53]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(53)); + +-- Location: FF_X37_Y18_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(53)); + +-- Location: LABCELL_X36_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[53]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[53]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[53]~feeder_combout\); + +-- Location: FF_X36_Y20_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[53]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(53)); + +-- Location: FF_X36_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(53)); + +-- Location: LABCELL_X36_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(53)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(53) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(53)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(53) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(53)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(53))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(53) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(53)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(53))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(53), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(53), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(53), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~1_combout\); + +-- Location: LABCELL_X36_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux232~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux232~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~2_combout\); + +-- Location: FF_X36_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(53)); + +-- Location: MLABCELL_X37_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101001000100111011110101111101011110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\); + +-- Location: FF_X36_Y23_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_OTERM2576\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(53)); + +-- Location: LABCELL_X36_Y23_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13380\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(53) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(53) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(53) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(53) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000001110011110100010100000011101010111100111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(53), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\); + +-- Location: LABCELL_X36_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_OTERM2576\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(53) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(53) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000101111111110111010100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_OTERM2576\); + +-- Location: FF_X36_Y23_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_OTERM2576\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE_q\); + +-- Location: FF_X37_Y15_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(53)); + +-- Location: FF_X40_Y15_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(53)); + +-- Location: FF_X40_Y15_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(53)); + +-- Location: FF_X40_Y15_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(53)); + +-- Location: LABCELL_X40_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(53)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(53) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(53)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(53) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(53))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(53)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(53) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(53))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(53)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(53), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(53), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(53), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~1_combout\); + +-- Location: FF_X44_Y15_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(53)); + +-- Location: MLABCELL_X49_Y15_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[53]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[53]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[53]~feeder_combout\); + +-- Location: FF_X49_Y15_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[53]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(53)); + +-- Location: FF_X49_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(53)); + +-- Location: MLABCELL_X49_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[53]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[53]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[53]~feeder_combout\); + +-- Location: FF_X49_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[53]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(53)); + +-- Location: MLABCELL_X49_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(53) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(53)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(53)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(53) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(53) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(53)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(53) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(53) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(53) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(53))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(53)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(53) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(53) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(53))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(53) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111000001001100011111000100001101110011010011110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(53), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(53), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(53), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~0_combout\); + +-- Location: LABCELL_X50_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux168~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux168~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~2_combout\); + +-- Location: FF_X50_Y15_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(53)); + +-- Location: LABCELL_X36_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(53) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(53) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(53) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(53) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(53), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(53), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(53), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(53), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~0_combout\); + +-- Location: LABCELL_X36_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(21) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(21) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(21) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(21)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(21)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(21))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100000000000111010011001100011101110011000001110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(21), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(21), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(21), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~1_combout\); + +-- Location: LABCELL_X36_Y12_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(49))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(21))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(49)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(21))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(49))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(21))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(49)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(21))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000011001001010100011101101001100010111010110111001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(49), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(45), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~2_combout\); + +-- Location: LABCELL_X36_Y12_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[53]_NEW1810\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[53]_OTERM1811\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(53))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(52))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(53))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(52)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(52), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(53), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[53]_OTERM1811\); + +-- Location: FF_X36_Y12_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[53]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[53]_OTERM1811\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(53)); + +-- Location: LABCELL_X29_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[22]_NEW1990\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[22]_OTERM1991\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(22))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(22) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(22))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[22]_OTERM1991\); + +-- Location: FF_X29_Y19_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[22]_OTERM1991\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(22)); + +-- Location: FF_X24_Y11_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(22)); + +-- Location: FF_X32_Y11_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(22)); + +-- Location: FF_X29_Y11_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(22)); + +-- Location: FF_X29_Y11_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(22)); + +-- Location: LABCELL_X29_Y11_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(22))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(22))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~1_combout\); + +-- Location: MLABCELL_X34_Y13_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[22]~feeder_combout\); + +-- Location: FF_X34_Y13_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(22)); + +-- Location: FF_X32_Y11_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(22)); + +-- Location: FF_X28_Y13_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(22)); + +-- Location: MLABCELL_X28_Y13_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[22]~feeder_combout\); + +-- Location: FF_X28_Y13_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(22)); + +-- Location: MLABCELL_X28_Y13_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(22) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(22))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(22))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(22))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001111110101000000110000010111110011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~0_combout\); + +-- Location: MLABCELL_X28_Y13_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux301~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux301~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~2_combout\); + +-- Location: FF_X28_Y13_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(22)); + +-- Location: MLABCELL_X23_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144_RESYN12856\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22) & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000111000000000000011111111111100011111111111110001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\); + +-- Location: MLABCELL_X23_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_OTERM2145\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010001000000010010111011111110111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_OTERM2145\); + +-- Location: FF_X23_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_OTERM2145\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22)); + +-- Location: FF_X35_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(22)); + +-- Location: FF_X35_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(22)); + +-- Location: MLABCELL_X34_Y18_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[22]~feeder_combout\); + +-- Location: FF_X34_Y18_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(22)); + +-- Location: FF_X35_Y18_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(22)); + +-- Location: LABCELL_X35_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(22) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(22) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(22) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(22) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~1_combout\); + +-- Location: MLABCELL_X34_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[22]~feeder_combout\); + +-- Location: FF_X34_Y17_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(22)); + +-- Location: LABCELL_X29_Y17_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[22]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[22]~feeder_combout\); + +-- Location: FF_X29_Y17_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(22)); + +-- Location: FF_X29_Y17_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(22)); + +-- Location: FF_X29_Y17_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(22)); + +-- Location: LABCELL_X29_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(22)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(22)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~0_combout\); + +-- Location: LABCELL_X35_Y16_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux325~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux325~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~2_combout\); + +-- Location: FF_X35_Y16_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(22)); + +-- Location: MLABCELL_X23_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[22]_NEW2142\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[22]_OTERM2143\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(22)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(22)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[22]_OTERM2143\); + +-- Location: FF_X23_Y15_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[22]_OTERM2143\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22)); + +-- Location: LABCELL_X26_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[22]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[22]~feeder_combout\); + +-- Location: FF_X26_Y15_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(22)); + +-- Location: LABCELL_X25_Y15_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[22]~feeder_combout\); + +-- Location: FF_X25_Y15_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(22)); + +-- Location: FF_X26_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(22)); + +-- Location: FF_X26_Y15_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(22)); + +-- Location: LABCELL_X26_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(22) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(22))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(22) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(22) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(22)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(22))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101010000111100110101111100000011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~1_combout\); + +-- Location: FF_X29_Y16_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(22)); + +-- Location: LABCELL_X26_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[22]~feeder_combout\); + +-- Location: FF_X26_Y16_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(22)); + +-- Location: LABCELL_X26_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[22]~feeder_combout\); + +-- Location: FF_X26_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(22)); + +-- Location: FF_X26_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(22)); + +-- Location: LABCELL_X26_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(22))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(22))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100111111111100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~0_combout\); + +-- Location: LABCELL_X35_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux355~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux355~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~2_combout\); + +-- Location: FF_X35_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(22)); + +-- Location: LABCELL_X19_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[22]_NEW2146\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[22]_OTERM2147\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(22))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(22)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(22) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[22]_OTERM2147\); + +-- Location: FF_X19_Y17_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[22]_OTERM2147\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(22)); + +-- Location: MLABCELL_X34_Y18_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[22]~feeder_combout\); + +-- Location: FF_X34_Y18_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(22)); + +-- Location: MLABCELL_X34_Y18_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[22]~feeder_combout\); + +-- Location: FF_X34_Y18_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(22)); + +-- Location: FF_X35_Y18_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(22)); + +-- Location: FF_X35_Y18_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(22)); + +-- Location: LABCELL_X35_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(22) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(22))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(22) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(22)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(22)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(22))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(22) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(22)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000110110001101110101010111111110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(22), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~1_combout\); + +-- Location: LABCELL_X29_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[22]~feeder_combout\); + +-- Location: FF_X29_Y17_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(22)); + +-- Location: LABCELL_X29_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[22]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(22) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(22), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[22]~feeder_combout\); + +-- Location: FF_X29_Y17_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[22]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(22)); + +-- Location: FF_X34_Y17_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(22)); + +-- Location: FF_X29_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(22), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(22)); + +-- Location: LABCELL_X29_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(22))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(22))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~0_combout\); + +-- Location: LABCELL_X35_Y16_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux387~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux387~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~2_combout\); + +-- Location: FF_X35_Y16_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(22)); + +-- Location: FF_X32_Y29_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~371_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE_q\); + +-- Location: MLABCELL_X37_Y28_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010110101010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\); + +-- Location: LABCELL_X36_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\); + +-- Location: LABCELL_X36_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\); + +-- Location: LABCELL_X36_Y28_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\); + +-- Location: MLABCELL_X37_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13390\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011101010100001101101010101000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\); + +-- Location: LABCELL_X40_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13392\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010001101000101111001100001100010111011010111011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(54), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\); + +-- Location: LABCELL_X40_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_OTERM2584\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_OTERM2584\); + +-- Location: FF_X40_Y26_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_OTERM2584\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54)); + +-- Location: LABCELL_X43_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[54]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[54]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(54), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[54]~feeder_combout\); + +-- Location: FF_X43_Y15_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[54]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(54)); + +-- Location: LABCELL_X41_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[54]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[54]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(54), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[54]~feeder_combout\); + +-- Location: FF_X41_Y17_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[54]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(54)); + +-- Location: FF_X41_Y17_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(54)); + +-- Location: FF_X41_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(54)); + +-- Location: LABCELL_X41_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(54) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(54))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(54))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(54) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(54) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(54)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(54))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(54) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(54) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(54))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(54) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(54))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(54)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000111001101000011011111000100110001111111010011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(54), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(54), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(54), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~0_combout\); + +-- Location: LABCELL_X40_Y15_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[54]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[54]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(54), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[54]~feeder_combout\); + +-- Location: FF_X40_Y15_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[54]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(54)); + +-- Location: FF_X35_Y14_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(54)); + +-- Location: LABCELL_X43_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[54]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[54]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(54), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[54]~feeder_combout\); + +-- Location: FF_X43_Y15_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[54]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(54)); + +-- Location: FF_X35_Y14_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(54)); + +-- Location: LABCELL_X35_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(54)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(54) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(54) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(54)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(54))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(54)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(54))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(54), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(54), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(54), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~1_combout\); + +-- Location: LABCELL_X35_Y16_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux167~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux167~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~2_combout\); + +-- Location: FF_X35_Y16_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(54)); + +-- Location: LABCELL_X36_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011010101010000000000001111001100110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~1_combout\); + +-- Location: LABCELL_X36_Y28_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~0_combout\); + +-- Location: LABCELL_X36_Y27_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13386\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13386_BDD13387\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010010101011111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1456~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1456~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13386_BDD13387\); + +-- Location: FF_X37_Y23_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_OTERM2582\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]~DUPLICATE_q\); + +-- Location: MLABCELL_X37_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13388\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13386_BDD13387\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13386_BDD13387\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100101111001011110010111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]_NEW2581_RESYN13386_BDD13387\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\); + +-- Location: MLABCELL_X37_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_OTERM2582\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_OTERM2582\); + +-- Location: FF_X37_Y23_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_OTERM2582\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54)); + +-- Location: FF_X42_Y19_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(54)); + +-- Location: FF_X37_Y23_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(54)); + +-- Location: FF_X42_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(54)); + +-- Location: FF_X42_Y19_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(54)); + +-- Location: MLABCELL_X42_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(54) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(54)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(54)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(54) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(54) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(54))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(54) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(54) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(54) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(54)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(54) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(54)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(54))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101010000111100110101111100000011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(54), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(54), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(54), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~1_combout\); + +-- Location: FF_X44_Y15_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(54)); + +-- Location: FF_X44_Y15_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(54)); + +-- Location: LABCELL_X43_Y15_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[54]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[54]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(54), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[54]~feeder_combout\); + +-- Location: FF_X43_Y15_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[54]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(54)); + +-- Location: FF_X44_Y15_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(54)); + +-- Location: LABCELL_X44_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(54)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(54) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(54) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(54))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(54)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(54))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(54)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(54), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(54), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(54), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~0_combout\); + +-- Location: LABCELL_X36_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux103~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux103~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~2_combout\); + +-- Location: FF_X36_Y16_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(54)); + +-- Location: FF_X19_Y13_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(22)); + +-- Location: MLABCELL_X34_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(22) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(22) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(22) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010111100100011000000000000000010101111001000111010111100100011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~1_combout\); + +-- Location: FF_X34_Y25_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_NEW_REG272\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM273\); + +-- Location: LABCELL_X32_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269~feeder_combout\); + +-- Location: FF_X32_Y25_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_NEW_REG268\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269\); + +-- Location: MLABCELL_X37_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000010001010111110001000100001010101110110101111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~0_combout\); + +-- Location: FF_X37_Y25_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_NEW_REG270\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM271\); + +-- Location: LABCELL_X36_Y21_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM271\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM273\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM271\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM273\) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM271\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM273\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM271\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM273\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000001000000010100000101000001100000011000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM225\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM227\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM273\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM269\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM271\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\); + +-- Location: FF_X36_Y21_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(54)); + +-- Location: FF_X36_Y21_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(54)); + +-- Location: MLABCELL_X34_Y21_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[54]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[54]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1392~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[54]~feeder_combout\); + +-- Location: FF_X34_Y21_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[54]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(54)); + +-- Location: FF_X36_Y21_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(54)); + +-- Location: LABCELL_X36_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(54)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(54) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(54) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(54)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(54))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(54)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(54))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(54), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(54), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(54), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~1_combout\); + +-- Location: FF_X41_Y16_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(54)); + +-- Location: LABCELL_X41_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[54]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[54]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1392~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[54]~feeder_combout\); + +-- Location: FF_X41_Y16_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[54]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(54)); + +-- Location: FF_X41_Y16_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(54)); + +-- Location: LABCELL_X40_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[54]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[54]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1392~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[54]~feeder_combout\); + +-- Location: FF_X40_Y16_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[54]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(54)); + +-- Location: LABCELL_X41_Y16_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(54) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(54))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(54))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(54) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(54) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(54) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(54))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(54) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(54)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(54) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(54) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(54))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(54)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100111111000001010011000011110101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(54), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(54), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(54), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~0_combout\); + +-- Location: LABCELL_X35_Y16_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux39~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux39~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~2_combout\); + +-- Location: FF_X35_Y16_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(54)); + +-- Location: FF_X37_Y26_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_OTERM2587\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(54)); + +-- Location: LABCELL_X36_Y28_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100000000111111110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][6]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~1_combout\); + +-- Location: LABCELL_X36_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101000000000000111100110011010101011111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][6]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~0_combout\); + +-- Location: LABCELL_X36_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13394\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux172~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000011000001010000001111110101111100111111010111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1572~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1572~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\); + +-- Location: MLABCELL_X37_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13396\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(54) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(54) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(54) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011111100111100110000001100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(54), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\); + +-- Location: MLABCELL_X37_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_OTERM2587\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(54) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_OTERM2587\); + +-- Location: FF_X37_Y26_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_OTERM2587\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE_q\); + +-- Location: FF_X45_Y31_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(54)); + +-- Location: FF_X45_Y31_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(54)); + +-- Location: FF_X44_Y31_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(54)); + +-- Location: FF_X45_Y31_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(54)); + +-- Location: MLABCELL_X45_Y31_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(54)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(54))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(54)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(54))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(54)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(54) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(54)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101101010101111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(54), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(54), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(54), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~1_combout\); + +-- Location: FF_X47_Y30_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(54)); + +-- Location: FF_X47_Y29_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(54)); + +-- Location: FF_X47_Y30_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(54)); + +-- Location: FF_X47_Y30_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(54)); + +-- Location: LABCELL_X47_Y30_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(54) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(54)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(54) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(54)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(54)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(54))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(54) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(54)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(54))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(54), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(54), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(54), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~0_combout\); + +-- Location: LABCELL_X47_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux231~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux231~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~2_combout\); + +-- Location: FF_X47_Y24_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(54)); + +-- Location: LABCELL_X35_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(54) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(54) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(54) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(54) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(54), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(54), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(54), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(54), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~0_combout\); + +-- Location: LABCELL_X35_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(22))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(22) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(22)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(22)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(22) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(22)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011111101011111001100000101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(22), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(22), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(22), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~1_combout\); + +-- Location: LABCELL_X36_Y12_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(50)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(22))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(50) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(22))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(50)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(22) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(50) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101001000101010111101110111000001010111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(50), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(22), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(46), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~2_combout\); + +-- Location: LABCELL_X36_Y12_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]_NEW1816\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]_OTERM1817\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(54))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(53))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(54))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(53)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(53), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(54), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]_OTERM1817\); + +-- Location: FF_X36_Y12_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]_OTERM1817\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(54)); + +-- Location: LABCELL_X36_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111001111110011111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_SP~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\); + +-- Location: LABCELL_X31_Y25_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9283\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9283_BDD9284\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9283_BDD9284\); + +-- Location: LABCELL_X31_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9285\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9285_BDD9286\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111001111111111111100111111111111110011111100001111001111110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9285_BDD9286\); + +-- Location: LABCELL_X31_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9285_BDD9286\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9283_BDD9284\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9285_BDD9286\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9283_BDD9284\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9285_BDD9286\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9283_BDD9284\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9285_BDD9286\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9283_BDD9284\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000011110000111100000000000001010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_RESYN9283_BDD9284\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_RESYN9285_BDD9286\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\); + +-- Location: LABCELL_X31_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[6]_NEW2258\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[6]_OTERM2259\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[6]_OTERM2259\); + +-- Location: FF_X31_Y29_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[6]_OTERM2259\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(6)); + +-- Location: LABCELL_X36_Y9_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(0) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ & \myVirtualToplevel|RESET_n~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001000000000000000000000000000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0_combout\); + +-- Location: FF_X34_Y9_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(6)); + +-- Location: LABCELL_X36_Y9_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ & \myVirtualToplevel|RESET_n~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000001000000000000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0_combout\); + +-- Location: FF_X34_Y9_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(6)); + +-- Location: LABCELL_X36_Y9_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000001000000000000000000000000000000010000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0_combout\); + +-- Location: FF_X36_Y9_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(6)); + +-- Location: LABCELL_X36_Y9_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|RESET_n~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(0))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000010000000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0_combout\); + +-- Location: FF_X34_Y9_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(6)); + +-- Location: MLABCELL_X34_Y9_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(6)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(6)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(6)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(6)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~1_combout\); + +-- Location: MLABCELL_X37_Y9_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[6]~feeder_combout\); + +-- Location: LABCELL_X36_Y9_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|RESET_n~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000100000000000000000000000000000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0_combout\); + +-- Location: FF_X37_Y9_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(6)); + +-- Location: MLABCELL_X37_Y9_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[6]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(6) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[6]~feeder_combout\); + +-- Location: LABCELL_X40_Y14_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0_combout\ & +-- \myVirtualToplevel|RESET_n~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Decoder0~0_combout\, + datac => \myVirtualToplevel|ALT_INV_RESET_n~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0_combout\); + +-- Location: FF_X37_Y9_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[6]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(6)); + +-- Location: LABCELL_X36_Y9_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ & (\myVirtualToplevel|RESET_n~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000001000000000000000100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0_combout\); + +-- Location: FF_X37_Y9_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(6)); + +-- Location: LABCELL_X36_Y9_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|RESET_n~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000100000000000000000000000000000001000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0_combout\); + +-- Location: FF_X36_Y9_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(6), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(6)); + +-- Location: MLABCELL_X37_Y9_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(6)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(6)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(6) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(6) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(6) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(6))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(6)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(6) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(6)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(6))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001011010100010101101110100001101010111111000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(6), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(6), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(6), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~0_combout\); + +-- Location: LABCELL_X39_Y10_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux287~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux287~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~2_combout\); + +-- Location: FF_X39_Y10_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(6)); + +-- Location: MLABCELL_X23_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[30]_NEW2158\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[30]_OTERM2159\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(30))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(30)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(30) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(30), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(30), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[30]_OTERM2159\); + +-- Location: FF_X23_Y18_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[30]_OTERM2159\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(30)); + +-- Location: LABCELL_X24_Y11_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[30]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(30) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[30]~feeder_combout\); + +-- Location: FF_X24_Y11_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(30)); + +-- Location: MLABCELL_X28_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[30]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(30) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[30]~feeder_combout\); + +-- Location: FF_X28_Y11_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(30)); + +-- Location: FF_X28_Y11_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(30)); + +-- Location: FF_X24_Y11_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(30)); + +-- Location: MLABCELL_X28_Y11_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(30) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(30) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(30) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(30)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(30) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(30) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(30))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(30)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(30) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(30))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000010110000000101011011010100011010101110100001111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(30), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(30), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~1_combout\); + +-- Location: MLABCELL_X28_Y12_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[30]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(30) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[30]~feeder_combout\); + +-- Location: FF_X28_Y12_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(30)); + +-- Location: FF_X26_Y11_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(30)); + +-- Location: FF_X26_Y12_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(30), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(30)); + +-- Location: MLABCELL_X28_Y12_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[30]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(30) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[30]~feeder_combout\); + +-- Location: FF_X28_Y12_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[30]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(30)); + +-- Location: LABCELL_X26_Y12_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(30) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(30) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(30) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(30) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(30))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(30))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(30) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(30))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(30)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(30) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(30) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(30)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(30))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100001001101010111000010101100111010011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(30), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(30), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(30), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(30), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~0_combout\); + +-- Location: LABCELL_X26_Y12_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100010001000100010001110111011101110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux379~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux379~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~2_combout\); + +-- Location: FF_X26_Y12_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(30)); + +-- Location: LABCELL_X32_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000000000000010000000000001001100000000000100110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~2_combout\); + +-- Location: LABCELL_X32_Y23_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~2_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010001010101000001000101010101000100010101010100010001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1384~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~3_combout\); + +-- Location: FF_X32_Y23_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_NEW_REG288\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM289\); + +-- Location: FF_X32_Y27_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_NEW_REG282\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM283\); + +-- Location: LABCELL_X32_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~1_combout\); + +-- Location: FF_X32_Y23_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_NEW_REG286\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM287\); + +-- Location: FF_X21_Y14_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[30]~47_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(30)); + +-- Location: LABCELL_X32_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(30) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(30), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~0_combout\); + +-- Location: FF_X32_Y23_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_NEW_REG284\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM285\); + +-- Location: LABCELL_X32_Y23_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM285\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM285\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM283\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM287\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM289\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010111110101010101011111010111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM289\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM283\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM287\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM285\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\); + +-- Location: FF_X35_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(62)); + +-- Location: FF_X35_Y18_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(62)); + +-- Location: FF_X35_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(62)); + +-- Location: LABCELL_X36_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[62]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[62]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1384~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[62]~feeder_combout\); + +-- Location: FF_X36_Y18_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[62]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(62)); + +-- Location: LABCELL_X35_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(62) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(62) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(62))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(62))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(62) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(62) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(62)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(62))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(62) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(62) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(62) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(62)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(62) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(62) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(62))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(62)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001001010111010100101010011110100010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(62), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(62), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(62), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(62), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~1_combout\); + +-- Location: LABCELL_X41_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1384~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~feeder_combout\); + +-- Location: FF_X41_Y16_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(62)); + +-- Location: LABCELL_X41_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[62]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[62]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1384~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[62]~feeder_combout\); + +-- Location: FF_X41_Y16_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[62]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(62)); + +-- Location: FF_X37_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(62)); + +-- Location: FF_X37_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(62)); + +-- Location: MLABCELL_X37_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(62) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(62) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(62)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(62)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(62) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(62) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(62)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(62))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(62) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(62) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(62)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(62))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(62) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(62) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(62)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(62))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010001010010001101100111000010011100110110101011111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(62), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(62), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(62), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(62), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~0_combout\); + +-- Location: MLABCELL_X37_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux31~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux31~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~2_combout\); + +-- Location: FF_X37_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(62)); + +-- Location: LABCELL_X35_Y23_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]_NEW2623\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]_OTERM2624\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001010001100110000101000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[22]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(62), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[62]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]_OTERM2624\); + +-- Location: FF_X35_Y23_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]_OTERM2624\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62)); + +-- Location: LABCELL_X41_Y19_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[62]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[62]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(62), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[62]~feeder_combout\); + +-- Location: FF_X41_Y19_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[62]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(62)); + +-- Location: LABCELL_X41_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[62]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[62]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(62), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[62]~feeder_combout\); + +-- Location: FF_X41_Y19_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[62]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(62)); + +-- Location: FF_X41_Y19_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(62)); + +-- Location: FF_X40_Y15_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(62)); + +-- Location: LABCELL_X41_Y19_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(62) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(62) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(62)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(62)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(62) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(62) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(62)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(62) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(62) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(62) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(62))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(62)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(62) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(62) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(62)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(62))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100111101001100011100110111000001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(62), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(62), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(62), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(62), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~1_combout\); + +-- Location: LABCELL_X44_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[62]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[62]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(62), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[62]~feeder_combout\); + +-- Location: FF_X44_Y15_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[62]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(62)); + +-- Location: FF_X43_Y15_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(62)); + +-- Location: FF_X44_Y15_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(62)); + +-- Location: LABCELL_X44_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[62]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[62]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(62), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[62]~feeder_combout\); + +-- Location: FF_X44_Y15_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[62]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(62)); + +-- Location: LABCELL_X44_Y15_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(62) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(62) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(62))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(62))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(62) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(62) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(62))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(62)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(62) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(62) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(62))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(62)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(62) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(62) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(62))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(62)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010111110011000001010000001111110101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(62), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(62), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(62), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(62), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~0_combout\); + +-- Location: MLABCELL_X37_Y16_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux95~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux95~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~2_combout\); + +-- Location: FF_X37_Y16_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(62)); + +-- Location: MLABCELL_X37_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector46~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector46~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(62) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(62) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000000000000000001111000011110000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(62), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(62), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector46~0_combout\); + +-- Location: LABCELL_X39_Y10_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~116\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~116_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector46~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(6))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\ & ( +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(30)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000010100000101000011110000111111110101001101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(6), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(30), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DECODED_OPCODE~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector46~0_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~116_combout\); + +-- Location: LABCELL_X39_Y10_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~112\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~112_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~116_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(54))))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(30) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(54))))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000001000010011000000100001001100000000000100010000000000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(30), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(54), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~116_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~112_combout\); + +-- Location: MLABCELL_X42_Y11_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~2_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\); + +-- Location: FF_X40_Y10_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~16_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(61)); + +-- Location: LABCELL_X39_Y10_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000011110000111100000000000000000000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\); + +-- Location: LABCELL_X39_Y10_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001100000011000011110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\); + +-- Location: FF_X36_Y12_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]_OTERM1807\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]~DUPLICATE_q\); + +-- Location: FF_X19_Y14_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~105_sumout\, + asdata => \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\, + sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(25)); + +-- Location: LABCELL_X24_Y15_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[25]_NEW2128\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[25]_OTERM2129\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(25))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(25))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(25), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[25]_OTERM2129\); + +-- Location: FF_X24_Y15_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[25]_OTERM2129\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25)); + +-- Location: FF_X24_Y12_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(25)); + +-- Location: LABCELL_X25_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[25]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[25]~feeder_combout\); + +-- Location: FF_X25_Y12_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(25)); + +-- Location: FF_X28_Y10_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(25)); + +-- Location: LABCELL_X24_Y12_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[25]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[25]~feeder_combout\); + +-- Location: FF_X24_Y12_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(25)); + +-- Location: MLABCELL_X28_Y10_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(25) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(25) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(25))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(25) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(25) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(25) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(25)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(25))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101010000111100110101111100000011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(25), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~1_combout\); + +-- Location: LABCELL_X26_Y10_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[25]~feeder_combout\); + +-- Location: FF_X26_Y10_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(25)); + +-- Location: FF_X25_Y12_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(25)); + +-- Location: FF_X28_Y10_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(25)); + +-- Location: FF_X28_Y10_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(25)); + +-- Location: MLABCELL_X28_Y10_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(25) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(25)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(25))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(25) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(25))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(25) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(25) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(25) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(25) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(25) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101001000101010111101110111000001010111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~0_combout\); + +-- Location: LABCELL_X29_Y10_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux352~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux352~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~2_combout\); + +-- Location: FF_X29_Y10_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(25)); + +-- Location: LABCELL_X36_Y10_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(25) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(25) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100000001000000010000010101000101010001010100010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[49]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~37_combout\); + +-- Location: LABCELL_X39_Y10_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000100000001000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9_combout\); + +-- Location: MLABCELL_X23_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[24]_NEW2148\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[24]_OTERM2149\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(24)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(24)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[24]_OTERM2149\); + +-- Location: FF_X23_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[24]_OTERM2149\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24)); + +-- Location: FF_X26_Y10_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(24)); + +-- Location: FF_X25_Y12_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(24)); + +-- Location: FF_X26_Y12_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(24)); + +-- Location: LABCELL_X26_Y10_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[24]~feeder_combout\); + +-- Location: FF_X26_Y10_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(24)); + +-- Location: LABCELL_X26_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(24) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(24)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(24))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(24) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(24))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(24) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(24) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(24) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(24) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(24) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000000011010100001111001101011111000000110101111111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(24), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~0_combout\); + +-- Location: FF_X25_Y12_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(24)); + +-- Location: LABCELL_X24_Y12_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[24]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[24]~feeder_combout\); + +-- Location: FF_X24_Y12_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(24)); + +-- Location: FF_X26_Y12_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(24)); + +-- Location: LABCELL_X24_Y12_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[24]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[24]~feeder_combout\); + +-- Location: FF_X24_Y12_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(24)); + +-- Location: LABCELL_X26_Y12_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(24) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(24))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(24) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(24) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(24) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(24) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(24))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(24)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001100000000010100110000111101010011111100000101001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(24), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~1_combout\); + +-- Location: LABCELL_X26_Y12_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux353~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux353~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~2_combout\); + +-- Location: FF_X26_Y12_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(24)); + +-- Location: LABCELL_X36_Y12_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(48)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(24))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(48), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~23_combout\); + +-- Location: LABCELL_X29_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]_NEW1994\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]_OTERM1995\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(23))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001011001110000000101100111000010011110111110001001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]_OTERM1995\); + +-- Location: FF_X29_Y19_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]_OTERM1995\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(23)); + +-- Location: FF_X26_Y13_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(23)); + +-- Location: LABCELL_X25_Y13_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(23) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[23]~feeder_combout\); + +-- Location: FF_X25_Y13_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(23)); + +-- Location: FF_X24_Y13_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(23)); + +-- Location: FF_X25_Y13_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(23)); + +-- Location: LABCELL_X25_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(23)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(23)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~1_combout\); + +-- Location: FF_X28_Y13_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(23)); + +-- Location: FF_X26_Y13_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(23)); + +-- Location: FF_X28_Y13_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(23)); + +-- Location: LABCELL_X29_Y13_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(23) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[23]~feeder_combout\); + +-- Location: FF_X29_Y13_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(23)); + +-- Location: MLABCELL_X28_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(23)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(23) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(23)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(23))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(23) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110100001010100011111000100001011101010110101101111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~0_combout\); + +-- Location: MLABCELL_X28_Y13_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux300~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux300~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~2_combout\); + +-- Location: FF_X28_Y13_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(23)); + +-- Location: MLABCELL_X23_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[23]_NEW2126\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[23]_OTERM2127\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(23))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(23))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(23)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[23]_OTERM2127\); + +-- Location: FF_X23_Y17_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[23]_OTERM2127\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(23)); + +-- Location: FF_X32_Y14_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(23)); + +-- Location: FF_X32_Y15_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(23)); + +-- Location: FF_X32_Y16_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(23)); + +-- Location: FF_X32_Y16_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(23)); + +-- Location: LABCELL_X32_Y16_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(23)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(23))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(23))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100100010001000100111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~1_combout\); + +-- Location: LABCELL_X31_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[23]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(23) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[23]~feeder_combout\); + +-- Location: FF_X31_Y17_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(23)); + +-- Location: MLABCELL_X28_Y14_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[23]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(23) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[23]~feeder_combout\); + +-- Location: FF_X28_Y14_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(23)); + +-- Location: MLABCELL_X28_Y14_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(23) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[23]~feeder_combout\); + +-- Location: FF_X28_Y14_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(23)); + +-- Location: FF_X28_Y14_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(23)); + +-- Location: MLABCELL_X28_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(23)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(23)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(23)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010011010100110101001100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~0_combout\); + +-- Location: LABCELL_X36_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux386~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux386~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~2_combout\); + +-- Location: FF_X36_Y14_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(23)); + +-- Location: FF_X23_Y20_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_OTERM2125\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(23)); + +-- Location: MLABCELL_X23_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124_RESYN12852\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(23) & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000011000000010000001111101111110011111110111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\); + +-- Location: MLABCELL_X23_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_OTERM2125\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010000000100010010111111101110111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_OTERM2125\); + +-- Location: FF_X23_Y20_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_OTERM2125\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y14_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[23]~feeder_combout\); + +-- Location: FF_X31_Y14_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(23)); + +-- Location: LABCELL_X35_Y17_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[23]~feeder_combout\); + +-- Location: FF_X35_Y17_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(23)); + +-- Location: FF_X36_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(23)); + +-- Location: LABCELL_X35_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[23]~feeder_combout\); + +-- Location: FF_X35_Y17_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(23)); + +-- Location: LABCELL_X36_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(23) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(23)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(23)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(23)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(23))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(23)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(23))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(23))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100110001000011010011110111000001111100011100110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~0_combout\); + +-- Location: FF_X31_Y15_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(23)); + +-- Location: LABCELL_X36_Y14_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[23]~feeder_combout\); + +-- Location: FF_X36_Y14_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(23)); + +-- Location: FF_X35_Y14_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(23)); + +-- Location: LABCELL_X35_Y14_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[23]~feeder_combout\); + +-- Location: FF_X35_Y14_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(23)); + +-- Location: LABCELL_X35_Y14_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(23) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(23)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(23)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(23)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011111101011111001100000101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~1_combout\); + +-- Location: LABCELL_X36_Y14_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux324~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux324~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~2_combout\); + +-- Location: FF_X36_Y14_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(23)); + +-- Location: LABCELL_X24_Y15_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[23]_NEW2122\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[23]_OTERM2123\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[23]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[23]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100100111001001110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[23]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[23]_OTERM2123\); + +-- Location: FF_X24_Y15_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[23]_OTERM2123\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23)); + +-- Location: FF_X31_Y13_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(23)); + +-- Location: LABCELL_X29_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[23]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[23]~feeder_combout\); + +-- Location: FF_X29_Y14_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(23)); + +-- Location: FF_X31_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(23)); + +-- Location: FF_X31_Y13_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(23)); + +-- Location: LABCELL_X31_Y13_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(23) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(23)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(23))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(23))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~1_combout\); + +-- Location: MLABCELL_X28_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[23]~feeder_combout\); + +-- Location: FF_X28_Y14_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(23)); + +-- Location: MLABCELL_X28_Y14_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[23]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(23), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[23]~feeder_combout\); + +-- Location: FF_X28_Y14_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(23)); + +-- Location: FF_X29_Y14_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(23)); + +-- Location: FF_X29_Y14_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(23)); + +-- Location: LABCELL_X29_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(23))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(23)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(23))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(23)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(23), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~0_combout\); + +-- Location: LABCELL_X36_Y14_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux354~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux354~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~2_combout\); + +-- Location: FF_X36_Y14_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(23)); + +-- Location: FF_X34_Y35_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_OTERM2475\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(55)); + +-- Location: LABCELL_X36_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101101011111010111100010001101110110001000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~1_combout\); + +-- Location: LABCELL_X36_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\ & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~0_combout\); + +-- Location: LABCELL_X36_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13234\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13234_BDD13235\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~1_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010111110101111100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1455~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1455~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13234_BDD13235\); + +-- Location: MLABCELL_X34_Y35_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13236\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(55) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13234_BDD13235\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(55) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13234_BDD13235\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100001011000010110000101101001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]_NEW2474_RESYN13234_BDD13235\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(55), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\); + +-- Location: MLABCELL_X34_Y35_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_OTERM2475\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(55) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101110101001010101000101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_OTERM2475\); + +-- Location: FF_X34_Y35_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_OTERM2475\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE_q\); + +-- Location: FF_X39_Y18_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(55)); + +-- Location: FF_X39_Y18_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(55)); + +-- Location: MLABCELL_X37_Y11_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[55]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[55]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[55]~feeder_combout\); + +-- Location: FF_X37_Y11_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[55]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(55)); + +-- Location: FF_X39_Y18_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(55)); + +-- Location: LABCELL_X39_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(55)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(55) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(55)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(55) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(55)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(55))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(55) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(55)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(55))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(55), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(55), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(55), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~1_combout\); + +-- Location: LABCELL_X48_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[55]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[55]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[55]~feeder_combout\); + +-- Location: FF_X48_Y14_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[55]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(55)); + +-- Location: LABCELL_X48_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[55]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[55]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[55]~feeder_combout\); + +-- Location: FF_X48_Y14_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[55]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(55)); + +-- Location: FF_X48_Y14_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(55)); + +-- Location: MLABCELL_X37_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[55]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[55]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[55]~feeder_combout\); + +-- Location: FF_X37_Y11_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[55]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(55)); + +-- Location: LABCELL_X48_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(55) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(55)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(55))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(55) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(55))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(55) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(55)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(55) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(55) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(55) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(55) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(55) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010000000011010001001100111101110111000000110111011111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(55), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(55), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(55), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~0_combout\); + +-- Location: LABCELL_X36_Y14_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux102~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux102~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~2_combout\); + +-- Location: FF_X36_Y14_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(55)); + +-- Location: FF_X40_Y26_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_OTERM2595\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(55)); + +-- Location: LABCELL_X36_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~1_combout\); + +-- Location: LABCELL_X36_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~2_combout\); + +-- Location: LABCELL_X36_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~3_combout\); + +-- Location: LABCELL_X36_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~0_combout\); + +-- Location: MLABCELL_X37_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux327~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000100101001010100010111101110000011101010111101001111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\); + +-- Location: LABCELL_X40_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13408\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(55) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(55) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(55) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001011101110110000101101000100010011111111111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(55), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\); + +-- Location: LABCELL_X40_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_OTERM2595\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(55) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_OTERM2595\); + +-- Location: FF_X40_Y26_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_OTERM2595\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE_q\); + +-- Location: FF_X42_Y16_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(55)); + +-- Location: LABCELL_X43_Y16_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[55]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[55]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[55]~feeder_combout\); + +-- Location: FF_X43_Y16_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[55]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(55)); + +-- Location: FF_X42_Y16_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(55)); + +-- Location: FF_X42_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(55)); + +-- Location: MLABCELL_X42_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(55)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(55))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(55)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(55))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(55) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(55)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(55) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(55) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(55), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(55), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(55), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~0_combout\); + +-- Location: FF_X35_Y15_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(55)); + +-- Location: MLABCELL_X45_Y17_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[55]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[55]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[55]~feeder_combout\); + +-- Location: FF_X45_Y17_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[55]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(55)); + +-- Location: MLABCELL_X37_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[55]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[55]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[55]~feeder_combout\); + +-- Location: FF_X37_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[55]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(55)); + +-- Location: FF_X37_Y15_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(55)); + +-- Location: MLABCELL_X37_Y15_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(55)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(55) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(55) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(55) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(55)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(55))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(55) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(55)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(55))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(55), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(55), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(55), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~1_combout\); + +-- Location: LABCELL_X36_Y14_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux166~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux166~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~2_combout\); + +-- Location: FF_X36_Y14_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(55)); + +-- Location: LABCELL_X36_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100111111111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~1_combout\); + +-- Location: LABCELL_X36_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\ +-- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~0_combout\); + +-- Location: LABCELL_X36_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13410\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13410_BDD13411\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010101000100000001010110111010101111111011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1571~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1571~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux179~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13410_BDD13411\); + +-- Location: LABCELL_X36_Y23_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13412\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13410_BDD13411\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13410_BDD13411\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000100110001001100010011000100111011001110110011101100111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[55]_NEW2597_RESYN13410_BDD13411\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(55), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\); + +-- Location: LABCELL_X36_Y23_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_OTERM2598\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000101101111111010111100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_OTERM2598\); + +-- Location: FF_X36_Y23_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_OTERM2598\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55)); + +-- Location: MLABCELL_X45_Y15_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[55]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[55]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(55), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[55]~feeder_combout\); + +-- Location: FF_X45_Y15_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[55]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(55)); + +-- Location: FF_X34_Y17_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(55)); + +-- Location: FF_X39_Y17_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(55)); + +-- Location: FF_X34_Y17_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(55)); + +-- Location: LABCELL_X39_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(55) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(55))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(55))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(55) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(55))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(55)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(55) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(55))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(55)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(55) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(55))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(55)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001001100010000110100111101110000011111000111001101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(55), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(55), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(55), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~1_combout\); + +-- Location: FF_X43_Y16_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(55)); + +-- Location: FF_X34_Y17_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(55)); + +-- Location: FF_X39_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(55)); + +-- Location: MLABCELL_X45_Y19_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[55]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[55]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(55), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[55]~feeder_combout\); + +-- Location: FF_X45_Y19_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[55]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(55)); + +-- Location: LABCELL_X39_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(55) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(55)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(55))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(55)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(55) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(55) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(55) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(55))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(55) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(55) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(55) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(55) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101011101110000010100100010101011110111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(55), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(55), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(55), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~0_combout\); + +-- Location: LABCELL_X39_Y17_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux230~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux230~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~2_combout\); + +-- Location: FF_X39_Y17_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(55)); + +-- Location: LABCELL_X36_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~3_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~1_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~2_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~0_combout\); + +-- Location: FF_X36_Y25_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_NEW_REG246\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM247\); + +-- Location: FF_X31_Y25_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_NEW_REG244\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM245\); + +-- Location: LABCELL_X17_Y15_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[23]~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[23]~feeder_combout\); + +-- Location: FF_X17_Y15_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[23]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(23)); + +-- Location: MLABCELL_X34_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~1_RTM0250\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~1_RTM0250_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(23))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(23))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(23)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100011111111100011111000111110001111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(23), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~1_RTM0250_combout\); + +-- Location: FF_X34_Y25_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_NEW_REG248\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~1_RTM0250_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM249\); + +-- Location: MLABCELL_X37_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM245\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM249\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM245\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM249\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM245\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM249\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ +-- & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM247\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM245\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM249\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM247\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000011110011111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM225\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM227\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM247\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM245\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM249\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\); + +-- Location: FF_X37_Y21_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(55)); + +-- Location: FF_X37_Y21_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(55)); + +-- Location: FF_X37_Y21_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(55)); + +-- Location: FF_X37_Y19_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(55)); + +-- Location: MLABCELL_X37_Y21_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(55) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(55))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(55))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(55))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(55))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(55) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(55)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(55))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(55) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(55) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(55)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(55))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001000110000100110101011110001010110011101001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(55), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(55), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(55), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~1_combout\); + +-- Location: LABCELL_X41_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[55]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[55]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1391~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[55]~feeder_combout\); + +-- Location: FF_X41_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[55]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(55)); + +-- Location: LABCELL_X41_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[55]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[55]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1391~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[55]~feeder_combout\); + +-- Location: FF_X41_Y16_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[55]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(55)); + +-- Location: FF_X41_Y16_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(55)); + +-- Location: LABCELL_X47_Y19_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[55]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[55]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1391~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[55]~feeder_combout\); + +-- Location: FF_X47_Y19_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[55]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(55)); + +-- Location: LABCELL_X41_Y16_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(55) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(55) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(55))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(55))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(55) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(55)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(55))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(55) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(55) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(55))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(55))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(55) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(55))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(55)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100001001100001010100110111000011001010111010011101101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(55), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(55), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(55), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~0_combout\); + +-- Location: LABCELL_X36_Y14_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux38~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux38~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~2_combout\); + +-- Location: FF_X36_Y14_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(55)); + +-- Location: LABCELL_X36_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(55) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(55))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(55)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(55) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(55)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(55) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(55))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(55)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(55) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(55)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111010100110101001111110000111111110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(55), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(55), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(55), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(55), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~0_combout\); + +-- Location: LABCELL_X36_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(23)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(23) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(23) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(23)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(23))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(23) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111000001001100011111000100001101110011010011110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(23), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(23), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~1_combout\); + +-- Location: LABCELL_X36_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(51))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(23)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(51))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111000000000011001101000111010001111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(51), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[47]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(23), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~2_combout\); + +-- Location: LABCELL_X36_Y12_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[55]_NEW1814\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[55]_OTERM1815\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(55))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(54))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(55))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(54)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(54), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[55]_OTERM1815\); + +-- Location: FF_X36_Y12_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[55]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[55]_OTERM1815\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(55)); + +-- Location: LABCELL_X36_Y10_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(55) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(52) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(55) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000001111111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(52), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(55), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~24_combout\); + +-- Location: LABCELL_X20_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000010110000000110101011101000010101101101010001111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_combout\); + +-- Location: LABCELL_X31_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[0]_NEW2246\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[0]_OTERM2247\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(0) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100010001000100010001000100010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[0]_OTERM2247\); + +-- Location: FF_X31_Y29_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[0]_OTERM2247\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(0)); + +-- Location: MLABCELL_X37_Y9_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[0]~feeder_combout\); + +-- Location: FF_X37_Y9_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(0)); + +-- Location: LABCELL_X36_Y9_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[0]~feeder_combout\); + +-- Location: FF_X36_Y9_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(0)); + +-- Location: FF_X37_Y9_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(0)); + +-- Location: FF_X37_Y9_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(0)); + +-- Location: MLABCELL_X37_Y9_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(0) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100001101001111010000000111110001110011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~0_combout\); + +-- Location: FF_X35_Y9_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(0)); + +-- Location: FF_X34_Y9_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(0)); + +-- Location: MLABCELL_X34_Y9_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[0]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[0]~feeder_combout\); + +-- Location: FF_X34_Y9_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(0)); + +-- Location: FF_X35_Y9_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(0)); + +-- Location: LABCELL_X35_Y9_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(0))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(0))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~1_combout\); + +-- Location: MLABCELL_X37_Y10_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux293~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux293~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~2_combout\); + +-- Location: FF_X37_Y10_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(0)); + +-- Location: LABCELL_X39_Y10_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111100000000111111110000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\); + +-- Location: LABCELL_X39_Y10_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111111111111000011111111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DECODED_OPCODE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\); + +-- Location: LABCELL_X24_Y17_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[24]_NEW2150\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[24]_OTERM2151\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(24)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(24))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(24) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[24]_OTERM2151\); + +-- Location: FF_X24_Y17_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[24]_OTERM2151\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(24)); + +-- Location: FF_X26_Y10_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(24)); + +-- Location: FF_X26_Y10_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(24)); + +-- Location: FF_X25_Y12_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(24)); + +-- Location: FF_X26_Y12_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(24)); + +-- Location: LABCELL_X26_Y12_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(24)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(24) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(24)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(24)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(24)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(24), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~0_combout\); + +-- Location: LABCELL_X29_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(24) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(24), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[24]~feeder_combout\); + +-- Location: FF_X29_Y11_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[24]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(24)); + +-- Location: FF_X25_Y12_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(24)); + +-- Location: FF_X25_Y10_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(24)); + +-- Location: FF_X26_Y12_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(24), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(24)); + +-- Location: LABCELL_X26_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(24)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(24) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(24) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(24)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(24)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(24), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(24), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(24), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(24), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~1_combout\); + +-- Location: LABCELL_X26_Y12_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux385~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux385~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~2_combout\); + +-- Location: FF_X26_Y12_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(24)); + +-- Location: LABCELL_X31_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[0]_NEW2249\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[0]_OTERM2250\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000001110000010000000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[0]_OTERM2250\); + +-- Location: FF_X31_Y29_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[0]_OTERM2250\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0)); + +-- Location: FF_X49_Y17_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(0)); + +-- Location: FF_X49_Y17_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(0)); + +-- Location: FF_X49_Y17_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(0)); + +-- Location: LABCELL_X50_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[0]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[0]~feeder_combout\); + +-- Location: FF_X50_Y19_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(0)); + +-- Location: MLABCELL_X49_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(0)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110100000001110011011111000100111101001100011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~1_combout\); + +-- Location: MLABCELL_X49_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[0]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[0]~feeder_combout\); + +-- Location: FF_X49_Y14_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(0)); + +-- Location: LABCELL_X48_Y14_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[0]~feeder_combout\); + +-- Location: FF_X48_Y14_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(0)); + +-- Location: FF_X48_Y14_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(0)); + +-- Location: LABCELL_X48_Y14_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[0]~feeder_combout\); + +-- Location: FF_X48_Y14_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(0)); + +-- Location: LABCELL_X48_Y14_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(0)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(0)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(0)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010011000111000001111111010000110100111101110011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~0_combout\); + +-- Location: LABCELL_X47_Y12_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux299~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux299~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~2_combout\); + +-- Location: FF_X47_Y12_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(0)); + +-- Location: LABCELL_X44_Y31_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111001100110100011111001100010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~6_combout\); + +-- Location: LABCELL_X36_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000100010001000100001010010111111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~5_combout\); + +-- Location: MLABCELL_X45_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~1_combout\); + +-- Location: MLABCELL_X45_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111111110101010100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~15_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~3_combout\); + +-- Location: MLABCELL_X45_Y32_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~10_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~2_combout\); + +-- Location: MLABCELL_X45_Y32_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~0_combout\); + +-- Location: MLABCELL_X45_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~3_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~3_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~3_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~3_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000010101001001100011011110001100100111011010111010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~4_combout\); + +-- Location: LABCELL_X44_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13422\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~6_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~6_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~6_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000100000101010001010110101110101011101011111110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\); + +-- Location: LABCELL_X44_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13424\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000000011001100000000111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(56), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\); + +-- Location: LABCELL_X44_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_OTERM2606\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000000101111101111111010100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(56), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_OTERM2606\); + +-- Location: FF_X44_Y29_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_OTERM2606\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56)); + +-- Location: LABCELL_X47_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[56]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(56), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[56]~feeder_combout\); + +-- Location: FF_X47_Y26_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(56)); + +-- Location: FF_X44_Y26_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(56)); + +-- Location: LABCELL_X47_Y26_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[56]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(56), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[56]~feeder_combout\); + +-- Location: FF_X47_Y26_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(56)); + +-- Location: FF_X47_Y26_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(56)); + +-- Location: LABCELL_X47_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(56))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(56)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(56))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(56)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(56)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(56) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(56)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010010111110101111100100010011101110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(56), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(56), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(56), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(56), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~0_combout\); + +-- Location: MLABCELL_X42_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[56]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(56), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[56]~feeder_combout\); + +-- Location: FF_X42_Y24_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(56)); + +-- Location: LABCELL_X43_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[56]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(56), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[56]~feeder_combout\); + +-- Location: FF_X43_Y24_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(56)); + +-- Location: MLABCELL_X42_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[56]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(56), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[56]~feeder_combout\); + +-- Location: FF_X42_Y24_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(56)); + +-- Location: FF_X42_Y24_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(56)); + +-- Location: MLABCELL_X42_Y24_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(56)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(56) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(56)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(56)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(56))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(56)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(56))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(56), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(56), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(56), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(56), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~1_combout\); + +-- Location: LABCELL_X44_Y24_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux229~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux229~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~2_combout\); + +-- Location: FF_X44_Y24_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(56)); + +-- Location: LABCELL_X36_Y32_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\); + +-- Location: LABCELL_X36_Y32_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\); + +-- Location: LABCELL_X44_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][8]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\); + +-- Location: LABCELL_X36_Y32_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\); + +-- Location: LABCELL_X36_Y32_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13418\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001010100111101000100101011101010010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\); + +-- Location: FF_X37_Y35_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_OTERM2603\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(56)); + +-- Location: MLABCELL_X37_Y35_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13420\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(56) & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(56) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(56) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(56) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100000000000011011101110100101111001000100010111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(56), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\); + +-- Location: MLABCELL_X37_Y35_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_OTERM2603\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(56) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001101111111011101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(56), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_OTERM2603\); + +-- Location: FF_X37_Y35_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_OTERM2603\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE_q\); + +-- Location: LABCELL_X47_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[56]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[56]~feeder_combout\); + +-- Location: FF_X47_Y24_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(56)); + +-- Location: FF_X48_Y24_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(56)); + +-- Location: LABCELL_X48_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[56]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[56]~feeder_combout\); + +-- Location: FF_X48_Y24_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(56)); + +-- Location: FF_X47_Y24_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(56)); + +-- Location: LABCELL_X47_Y24_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(56)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(56) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(56)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(56))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(56)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(56))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(56)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(56), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(56), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(56), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(56), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~1_combout\); + +-- Location: LABCELL_X43_Y25_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[56]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[56]~feeder_combout\); + +-- Location: FF_X43_Y25_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(56)); + +-- Location: LABCELL_X50_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[56]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[56]~feeder_combout\); + +-- Location: FF_X50_Y23_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(56)); + +-- Location: FF_X43_Y25_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(56)); + +-- Location: LABCELL_X44_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[56]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[56]~feeder_combout\); + +-- Location: FF_X44_Y26_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(56)); + +-- Location: LABCELL_X43_Y25_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(56) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(56)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(56)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(56) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(56) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(56))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(56) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(56) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(56) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(56)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(56) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(56)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(56))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011011010101010001101110101010000110111111111100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(56), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(56), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(56), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(56), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~0_combout\); + +-- Location: LABCELL_X44_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux165~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux165~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~2_combout\); + +-- Location: FF_X44_Y23_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(56)); + +-- Location: LABCELL_X39_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~38_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~0_combout\); + +-- Location: FF_X39_Y25_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_NEW_REG742\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM743\); + +-- Location: FF_X32_Y25_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_NEW_REG740\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM741\); + +-- Location: FF_X21_Y14_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(24)); + +-- Location: LABCELL_X36_Y32_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000111101000101010011101010010010101111111001011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~1_combout\); + +-- Location: LABCELL_X35_Y28_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100000000001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~2_combout\); + +-- Location: LABCELL_X36_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~3_RTM0747\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~3_RTM0747_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(24))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(24)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011111111111111111100000011111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(24), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~3_RTM0747_combout\); + +-- Location: FF_X36_Y24_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_NEW_REG745\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~3_RTM0747_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM746\); + +-- Location: LABCELL_X39_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM746\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM746\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM746\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\ +-- & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM743\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM741\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101011110011111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM743\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM741\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM711~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM623\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM715\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM746\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\); + +-- Location: LABCELL_X39_Y16_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[56]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[56]~feeder_combout\); + +-- Location: FF_X39_Y16_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(56)); + +-- Location: FF_X39_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(56)); + +-- Location: FF_X39_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(56)); + +-- Location: FF_X34_Y17_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(56)); + +-- Location: LABCELL_X39_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(56) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(56)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(56)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(56) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(56) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(56) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(56)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(56) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(56))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(56) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(56) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(56)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(56))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110111010101000011011010101010001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(56), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(56), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(56), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(56), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~0_combout\); + +-- Location: LABCELL_X39_Y18_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[56]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[56]~feeder_combout\); + +-- Location: FF_X39_Y18_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(56)); + +-- Location: FF_X39_Y19_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(56)); + +-- Location: FF_X39_Y25_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(56)); + +-- Location: FF_X39_Y19_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(56)); + +-- Location: LABCELL_X39_Y19_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(56)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(56) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(56)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(56))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(56)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(56))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(56)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(56), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(56), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(56), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(56), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~1_combout\); + +-- Location: LABCELL_X39_Y19_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux37~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux37~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~2_combout\); + +-- Location: FF_X39_Y19_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(56)); + +-- Location: LABCELL_X44_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~0_combout\); + +-- Location: LABCELL_X36_Y32_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~1_combout\); + +-- Location: MLABCELL_X37_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13414\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13414_BDD13415\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~1_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001111110101000000110000010111110011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1454~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1454~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13414_BDD13415\); + +-- Location: FF_X37_Y26_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_OTERM2601\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(56)); + +-- Location: MLABCELL_X37_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13416\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(56) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13414_BDD13415\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(56) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13414_BDD13415\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100101111001011110010111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]_NEW2600_RESYN13414_BDD13415\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(56), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\); + +-- Location: MLABCELL_X37_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_OTERM2601\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(56) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010001101011101111111100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(56), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_OTERM2601\); + +-- Location: FF_X37_Y26_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_OTERM2601\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y22_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[56]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[56]~feeder_combout\); + +-- Location: FF_X42_Y22_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(56)); + +-- Location: MLABCELL_X42_Y22_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[56]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[56]~feeder_combout\); + +-- Location: FF_X42_Y22_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(56)); + +-- Location: FF_X40_Y24_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(56)); + +-- Location: FF_X44_Y22_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(56)); + +-- Location: LABCELL_X44_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(56)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(56) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(56) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(56)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(56))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(56)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(56))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(56), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(56), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(56), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(56), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~1_combout\); + +-- Location: MLABCELL_X37_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[56]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[56]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[56]~feeder_combout\); + +-- Location: FF_X37_Y22_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[56]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(56)); + +-- Location: FF_X41_Y22_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(56)); + +-- Location: FF_X41_Y22_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(56)); + +-- Location: FF_X41_Y22_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(56)); + +-- Location: LABCELL_X41_Y22_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(56)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(56))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(56) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(56)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(56))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(56) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(56)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(56) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(56)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010010101011111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(56), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(56), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(56), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(56), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~0_combout\); + +-- Location: LABCELL_X44_Y22_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux101~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux101~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~2_combout\); + +-- Location: FF_X44_Y22_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(56)); + +-- Location: LABCELL_X44_Y23_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(56) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(56) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(56) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(56) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(56), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(56), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(56), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(56), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~0_combout\); + +-- Location: MLABCELL_X37_Y10_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(0) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(0) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(0))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100000001111100011100110100111101000011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(24), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector52~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~1_combout\); + +-- Location: LABCELL_X36_Y10_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~23_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~24_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~23_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~24_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~23_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~24_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector52~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~25_combout\); + +-- Location: LABCELL_X36_Y10_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~25_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(56) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~25_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(56)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000011111111001100001111111100000000110011110000000011001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(56), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~25_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~26_combout\); + +-- Location: FF_X36_Y10_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~26_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(56)); + +-- Location: LABCELL_X36_Y10_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(56) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(53) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(56) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111100110011001100110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(53), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(56), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~38_combout\); + +-- Location: LABCELL_X26_Y32_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~19_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~14_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~9_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~4_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000011110000111100110011001100110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~19_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_combout\); + +-- Location: LABCELL_X31_Y29_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[1]_NEW2228\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[1]_OTERM2229\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[1]_OTERM2229\); + +-- Location: FF_X31_Y29_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[1]_OTERM2229\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(1)); + +-- Location: MLABCELL_X34_Y9_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[1]~feeder_combout\); + +-- Location: FF_X34_Y9_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(1)); + +-- Location: MLABCELL_X34_Y9_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[1]~feeder_combout\); + +-- Location: FF_X34_Y9_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(1)); + +-- Location: FF_X34_Y9_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(1)); + +-- Location: FF_X35_Y9_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(1)); + +-- Location: MLABCELL_X34_Y9_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(1) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(1)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110110101010100011011101010100001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~1_combout\); + +-- Location: FF_X37_Y9_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(1)); + +-- Location: FF_X36_Y9_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(1)); + +-- Location: MLABCELL_X37_Y9_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[1]~feeder_combout\); + +-- Location: FF_X37_Y9_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(1)); + +-- Location: FF_X36_Y9_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(1)); + +-- Location: LABCELL_X36_Y9_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(1))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(1))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~0_combout\); + +-- Location: LABCELL_X35_Y9_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux292~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux292~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~2_combout\); + +-- Location: FF_X35_Y9_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(1)); + +-- Location: MLABCELL_X23_Y17_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[25]_NEW2130\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[25]_OTERM2131\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(25))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(25) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(25))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(25)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010101110000001001010111000010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[25]_OTERM2131\); + +-- Location: FF_X23_Y17_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[25]_OTERM2131\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(25)); + +-- Location: LABCELL_X24_Y11_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[25]~feeder_combout\); + +-- Location: FF_X24_Y11_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(25)); + +-- Location: LABCELL_X24_Y11_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[25]~feeder_combout\); + +-- Location: FF_X24_Y11_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(25)); + +-- Location: LABCELL_X25_Y11_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[25]~feeder_combout\); + +-- Location: FF_X25_Y11_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(25)); + +-- Location: FF_X24_Y11_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(25)); + +-- Location: LABCELL_X24_Y11_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(25)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(25) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(25) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(25))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(25)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(25))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(25), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(25), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~1_combout\); + +-- Location: MLABCELL_X28_Y12_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[25]~feeder_combout\); + +-- Location: FF_X28_Y12_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(25)); + +-- Location: LABCELL_X26_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[25]~feeder_combout\); + +-- Location: FF_X26_Y13_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(25)); + +-- Location: FF_X28_Y13_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(25), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(25)); + +-- Location: LABCELL_X25_Y11_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[25]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(25) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[25]~feeder_combout\); + +-- Location: FF_X25_Y11_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[25]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(25)); + +-- Location: MLABCELL_X28_Y13_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(25) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(25))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(25)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(25) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(25))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(25) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(25) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(25) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(25) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(25)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(25) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(25) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(25) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(25) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000010001010111110001000100001010101110110101111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(25), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(25), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(25), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~0_combout\); + +-- Location: MLABCELL_X28_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux384~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux384~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~2_combout\); + +-- Location: FF_X28_Y13_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(25)); + +-- Location: MLABCELL_X45_Y31_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000000011110101010100110011111111110000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~6_combout\); + +-- Location: MLABCELL_X45_Y31_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010001000100111011101011111010111110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~5_combout\); + +-- Location: LABCELL_X44_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101101011111010111100100010011101110010001001110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~13_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~15_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~12_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~3_combout\); + +-- Location: LABCELL_X44_Y30_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~3_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101000000001111111100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~0_combout\); + +-- Location: LABCELL_X44_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111101010000010100000101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~7_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~1_combout\); + +-- Location: LABCELL_X44_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~9_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux266~9_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~10_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~2_combout\); + +-- Location: LABCELL_X44_Y30_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011010101010000111111111111001100110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~4_combout\); + +-- Location: MLABCELL_X45_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13242\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~4_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~5_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010000000100110001001111011100110111001101111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\); + +-- Location: FF_X45_Y27_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_OTERM2479\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(57)); + +-- Location: MLABCELL_X45_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13244\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(57) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(57) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(57) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001111111100110011000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\); + +-- Location: MLABCELL_X45_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_OTERM2479\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(57) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011110111001111111100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_OTERM2479\); + +-- Location: FF_X45_Y27_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_OTERM2479\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE_q\); + +-- Location: LABCELL_X50_Y24_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[57]~feeder_combout\); + +-- Location: FF_X50_Y24_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(57)); + +-- Location: LABCELL_X48_Y20_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[57]~feeder_combout\); + +-- Location: FF_X48_Y20_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(57)); + +-- Location: LABCELL_X48_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[57]~feeder_combout\); + +-- Location: FF_X48_Y20_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(57)); + +-- Location: FF_X48_Y20_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(57)); + +-- Location: LABCELL_X48_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(57)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(57) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(57) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(57)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(57))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(57)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(57))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(57), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(57), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(57), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~0_combout\); + +-- Location: LABCELL_X50_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[57]~feeder_combout\); + +-- Location: FF_X50_Y24_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(57)); + +-- Location: LABCELL_X48_Y24_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[57]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[57]~feeder_combout\); + +-- Location: FF_X48_Y24_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(57)); + +-- Location: FF_X48_Y24_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(57)); + +-- Location: LABCELL_X43_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[57]~feeder_combout\); + +-- Location: FF_X43_Y24_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(57)); + +-- Location: LABCELL_X48_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(57) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(57))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(57)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(57))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(57) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(57) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(57))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(57)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(57) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(57))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(57) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011100000100110001111111010000110111001101001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(57), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(57), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~1_combout\); + +-- Location: LABCELL_X47_Y18_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux228~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux228~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~2_combout\); + +-- Location: FF_X47_Y18_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(57)); + +-- Location: FF_X32_Y25_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_NEW_REG630\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM631\); + +-- Location: FF_X18_Y14_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(25)); + +-- Location: MLABCELL_X45_Y31_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\); + +-- Location: MLABCELL_X45_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\); + +-- Location: MLABCELL_X45_Y31_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\); + +-- Location: MLABCELL_X45_Y31_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\); + +-- Location: MLABCELL_X45_Y31_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000111010100100101011110100010101001111111001011110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~0_combout\); + +-- Location: LABCELL_X36_Y31_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001101010101011101110101010101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~1_combout\); + +-- Location: LABCELL_X35_Y25_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~1_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(25)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011010101110101011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(25), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~2_combout\); + +-- Location: FF_X35_Y25_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_NEW_REG634\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM635\); + +-- Location: FF_X32_Y21_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_NEW_REG632\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM633\); + +-- Location: LABCELL_X32_Y21_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM627\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM621\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM633\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM619\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM635\) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM627\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM631\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM635\)) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0001000111111111000000111111111100010011111111110000001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM619\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM627\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM631\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM635\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM623\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM633\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM621\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\); + +-- Location: LABCELL_X36_Y15_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[57]~feeder_combout\); + +-- Location: FF_X36_Y15_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(57)); + +-- Location: LABCELL_X36_Y15_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[57]~feeder_combout\); + +-- Location: FF_X36_Y15_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(57)); + +-- Location: FF_X36_Y15_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(57)); + +-- Location: LABCELL_X39_Y15_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[57]~feeder_combout\); + +-- Location: FF_X39_Y15_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(57)); + +-- Location: LABCELL_X36_Y15_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(57) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(57))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(57))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(57) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(57))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(57)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(57) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(57))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(57)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(57) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(57))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(57)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000101010011100000111101000100101001011110111010101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(57), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(57), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~0_combout\); + +-- Location: LABCELL_X26_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[57]~feeder_combout\); + +-- Location: FF_X26_Y14_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(57)); + +-- Location: LABCELL_X35_Y18_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[57]~feeder_combout\); + +-- Location: FF_X35_Y18_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(57)); + +-- Location: FF_X35_Y14_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(57)); + +-- Location: FF_X35_Y14_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(57)); + +-- Location: LABCELL_X35_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(57)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(57) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(57) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(57))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(57)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(57))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(57)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(57), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(57), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(57), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~1_combout\); + +-- Location: LABCELL_X36_Y14_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010111110101111101011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux36~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux36~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~2_combout\); + +-- Location: FF_X36_Y14_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(57)); + +-- Location: MLABCELL_X45_Y31_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13374\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010100010000001111010011101010010111100100101011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\); + +-- Location: FF_X41_Y26_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_OTERM2573\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(57)); + +-- Location: LABCELL_X41_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13376\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(57) & ( +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(57) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(57) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010100000000010001011100111101110101001100000111010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\); + +-- Location: LABCELL_X41_Y26_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_OTERM2573\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(57) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000101111111110111010100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_OTERM2573\); + +-- Location: FF_X41_Y26_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_OTERM2573\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE_q\); + +-- Location: FF_X44_Y25_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(57)); + +-- Location: MLABCELL_X45_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[57]~feeder_combout\); + +-- Location: FF_X45_Y23_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(57)); + +-- Location: FF_X42_Y23_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(57)); + +-- Location: MLABCELL_X42_Y24_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[57]~feeder_combout\); + +-- Location: FF_X42_Y24_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(57)); + +-- Location: MLABCELL_X42_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(57) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(57))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(57))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(57) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(57))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(57)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(57) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(57))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(57)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(57) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(57))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(57)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000101010001001010010111101110000011110100111010101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(57), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(57), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~1_combout\); + +-- Location: FF_X48_Y18_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(57)); + +-- Location: MLABCELL_X45_Y20_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[57]~feeder_combout\); + +-- Location: FF_X45_Y20_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(57)); + +-- Location: FF_X48_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(57)); + +-- Location: FF_X48_Y18_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(57)); + +-- Location: LABCELL_X48_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(57) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(57)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(57)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(57) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(57))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(57) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(57) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(57) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(57)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(57) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(57)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(57))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011101001100110001110111001100000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(57), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(57), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~0_combout\); + +-- Location: LABCELL_X47_Y18_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux164~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux164~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~2_combout\); + +-- Location: FF_X47_Y18_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(57)); + +-- Location: MLABCELL_X45_Y31_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101111101011111010100000011111100110000001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~0_combout\); + +-- Location: MLABCELL_X45_Y31_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000111111001100000011111100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~1_combout\); + +-- Location: LABCELL_X40_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13238\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13238_BDD13239\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~1_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111010001000100010000001100001111110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1453~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1453~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13238_BDD13239\); + +-- Location: FF_X40_Y27_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_OTERM2477\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]~DUPLICATE_q\); + +-- Location: LABCELL_X40_Y27_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13240\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13238_BDD13239\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13238_BDD13239\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100101111001011110010111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]_NEW2476_RESYN13238_BDD13239\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\); + +-- Location: LABCELL_X40_Y27_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_OTERM2477\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001110111111101110100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_OTERM2477\); + +-- Location: FF_X40_Y27_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_OTERM2477\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57)); + +-- Location: LABCELL_X50_Y20_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[57]~feeder_combout\); + +-- Location: FF_X50_Y20_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(57)); + +-- Location: LABCELL_X50_Y18_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[57]~feeder_combout\); + +-- Location: FF_X50_Y18_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(57)); + +-- Location: LABCELL_X50_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[57]~feeder_combout\); + +-- Location: FF_X50_Y20_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(57)); + +-- Location: FF_X50_Y20_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(57)); + +-- Location: LABCELL_X50_Y20_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(57)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(57) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(57)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(57))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(57)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(57))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(57)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(57), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(57), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(57), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~0_combout\); + +-- Location: LABCELL_X50_Y16_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[57]~feeder_combout\); + +-- Location: FF_X50_Y16_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(57)); + +-- Location: LABCELL_X50_Y16_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[57]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[57]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[57]~feeder_combout\); + +-- Location: FF_X50_Y16_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[57]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(57)); + +-- Location: FF_X47_Y18_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(57)); + +-- Location: FF_X47_Y18_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(57)); + +-- Location: LABCELL_X47_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(57) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(57)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(57)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(57)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(57))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(57) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(57) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(57)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(57) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(57) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(57))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110100000001110011011111000100111101001100011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(57), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(57), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~1_combout\); + +-- Location: LABCELL_X47_Y18_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101111101011111010100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux100~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux100~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~2_combout\); + +-- Location: FF_X47_Y18_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(57)); + +-- Location: LABCELL_X47_Y18_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(57) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(57) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(57)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(57)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(57) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(57)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(57) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(57) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(57))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(57)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(57) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(57) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(57)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(57))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000011010000000100111101001100011100110111000001111111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(57), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(57), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(57), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~0_combout\); + +-- Location: LABCELL_X20_Y32_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[1]_NEW2231\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[1]_OTERM2232\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\))))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100010001000000110001000100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[1]_OTERM2232\); + +-- Location: FF_X20_Y32_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[1]_OTERM2232\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1)); + +-- Location: FF_X49_Y14_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(1)); + +-- Location: FF_X49_Y14_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(1)); + +-- Location: LABCELL_X50_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[1]~feeder_combout\); + +-- Location: FF_X50_Y20_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(1)); + +-- Location: FF_X49_Y14_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(1)); + +-- Location: MLABCELL_X49_Y14_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(1))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(1))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~0_combout\); + +-- Location: LABCELL_X50_Y19_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[1]~feeder_combout\); + +-- Location: FF_X50_Y19_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(1)); + +-- Location: LABCELL_X50_Y19_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[1]~feeder_combout\); + +-- Location: FF_X50_Y19_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(1)); + +-- Location: FF_X49_Y19_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(1)); + +-- Location: FF_X50_Y19_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(1)); + +-- Location: LABCELL_X50_Y19_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(1) & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(1))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(1)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(1))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000110110001101100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~1_combout\); + +-- Location: MLABCELL_X49_Y14_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux298~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux298~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~2_combout\); + +-- Location: FF_X37_Y10_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(1)); + +-- Location: MLABCELL_X37_Y10_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(1) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(25))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(25), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector51~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~10_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~1_combout\); + +-- Location: LABCELL_X36_Y10_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~37_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~38_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~37_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~38_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000000000101010100000000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~37_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~38_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector51~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~39_combout\); + +-- Location: LABCELL_X36_Y10_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~39_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(57) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~39_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(57)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110011111111000011001111111100000000111100110000000011110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(57), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~39_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~40_combout\); + +-- Location: FF_X36_Y10_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~40_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(57)); + +-- Location: LABCELL_X31_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[2]_NEW2237\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[2]_OTERM2238\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000000111010000000000011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[2]_OTERM2238\); + +-- Location: FF_X31_Y29_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[2]_OTERM2238\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2)); + +-- Location: LABCELL_X50_Y14_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[2]~feeder_combout\); + +-- Location: FF_X50_Y14_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(2)); + +-- Location: MLABCELL_X49_Y14_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[2]~feeder_combout\); + +-- Location: FF_X49_Y14_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(2)); + +-- Location: FF_X49_Y14_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(2)); + +-- Location: MLABCELL_X49_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[2]~feeder_combout\); + +-- Location: FF_X49_Y14_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(2)); + +-- Location: MLABCELL_X49_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(2) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(2)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(2))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(2) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(2))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(2) +-- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000000101011101110000010100100010101011110111011110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~0_combout\); + +-- Location: FF_X49_Y17_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(2)); + +-- Location: FF_X48_Y17_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(2)); + +-- Location: FF_X49_Y17_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(2)); + +-- Location: FF_X49_Y17_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(2)); + +-- Location: MLABCELL_X49_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(2) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(2))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(2)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(2) & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(2))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(2))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100000101011001110100100110101011100011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~1_combout\); + +-- Location: LABCELL_X39_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux297~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux297~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~2_combout\); + +-- Location: FF_X39_Y14_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(2)); + +-- Location: LABCELL_X17_Y32_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~19_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_combout\); + +-- Location: LABCELL_X31_Y29_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[2]_NEW2234\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[2]_OTERM2235\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(2)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000000001111000000000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[2]_OTERM2235\); + +-- Location: FF_X31_Y29_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[2]_OTERM2235\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(2)); + +-- Location: FF_X36_Y9_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(2)); + +-- Location: MLABCELL_X37_Y9_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[2]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(2) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[2]~feeder_combout\); + +-- Location: FF_X37_Y9_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(2)); + +-- Location: MLABCELL_X37_Y9_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[2]~feeder_combout\); + +-- Location: FF_X37_Y9_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(2)); + +-- Location: FF_X36_Y9_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(2)); + +-- Location: LABCELL_X36_Y9_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(2)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~0_combout\); + +-- Location: MLABCELL_X34_Y9_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[2]~feeder_combout\); + +-- Location: FF_X34_Y9_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(2)); + +-- Location: MLABCELL_X34_Y9_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(2) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[2]~feeder_combout\); + +-- Location: FF_X34_Y9_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[2]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(2)); + +-- Location: FF_X35_Y9_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(2)); + +-- Location: FF_X35_Y9_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(2), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(2)); + +-- Location: LABCELL_X35_Y9_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(2)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(2)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(2)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~1_combout\); + +-- Location: LABCELL_X35_Y9_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux291~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux291~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~2_combout\); + +-- Location: FF_X35_Y9_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(2)); + +-- Location: LABCELL_X24_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[26]_NEW2140\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[26]_OTERM2141\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(26)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(26)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[26]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(26), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[26]_OTERM2141\); + +-- Location: FF_X24_Y17_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[26]_OTERM2141\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26)); + +-- Location: LABCELL_X25_Y11_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[26]~feeder_combout\); + +-- Location: FF_X25_Y11_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(26)); + +-- Location: LABCELL_X26_Y11_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[26]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[26]~feeder_combout\); + +-- Location: FF_X26_Y11_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(26)); + +-- Location: MLABCELL_X28_Y10_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[26]~feeder_combout\); + +-- Location: FF_X28_Y10_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(26)); + +-- Location: FF_X28_Y11_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(26)); + +-- Location: MLABCELL_X28_Y11_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(26))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(26))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(26)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(26) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(26)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010010111110101111100010001101110110001000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(26), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(26), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~0_combout\); + +-- Location: FF_X29_Y11_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(26)); + +-- Location: MLABCELL_X28_Y11_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[26]~feeder_combout\); + +-- Location: FF_X28_Y11_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(26)); + +-- Location: LABCELL_X24_Y11_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[26]~feeder_combout\); + +-- Location: FF_X24_Y11_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(26)); + +-- Location: FF_X28_Y11_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(26)); + +-- Location: MLABCELL_X28_Y11_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(26)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(26) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(26))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(26))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(26), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(26), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~1_combout\); + +-- Location: LABCELL_X29_Y11_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux383~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux383~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~2_combout\); + +-- Location: FF_X29_Y11_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(26)); + +-- Location: MLABCELL_X37_Y28_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~6_combout\); + +-- Location: LABCELL_X39_Y34_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111100001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~5_combout\); + +-- Location: LABCELL_X40_Y34_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~3_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~0_combout\ +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~2_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000011110000111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~0_combout\); + +-- Location: LABCELL_X40_Y34_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100110011010101010011001100001111000000000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~11_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~2_combout\); + +-- Location: LABCELL_X40_Y34_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~5_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~1_combout\); + +-- Location: LABCELL_X40_Y34_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111110011001100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~13_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~3_combout\); + +-- Location: LABCELL_X40_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~2_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~2_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011100000000010001111100110001000111001100110100011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~4_combout\); + +-- Location: LABCELL_X39_Y34_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13258\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000000000101010110101111101011111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~5_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\); + +-- Location: FF_X45_Y27_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_OTERM2487\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(58)); + +-- Location: MLABCELL_X45_Y27_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13260\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(58) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(58) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(58) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100111111001100001100000011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(58), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\); + +-- Location: MLABCELL_X45_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_OTERM2487\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(58) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000011110111111100111100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_OTERM2487\); + +-- Location: FF_X45_Y27_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_OTERM2487\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE_q\); + +-- Location: MLABCELL_X45_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[58]~feeder_combout\); + +-- Location: FF_X45_Y24_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(58)); + +-- Location: MLABCELL_X45_Y23_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[58]~feeder_combout\); + +-- Location: FF_X45_Y23_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(58)); + +-- Location: MLABCELL_X42_Y26_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[58]~feeder_combout\); + +-- Location: FF_X42_Y26_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(58)); + +-- Location: FF_X45_Y24_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(58)); + +-- Location: MLABCELL_X45_Y24_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(58)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(58) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(58) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(58))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(58))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(58), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(58), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(58), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~0_combout\); + +-- Location: LABCELL_X50_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[58]~feeder_combout\); + +-- Location: FF_X50_Y24_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(58)); + +-- Location: MLABCELL_X45_Y27_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[58]~feeder_combout\); + +-- Location: FF_X45_Y27_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(58)); + +-- Location: FF_X47_Y24_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(58)); + +-- Location: LABCELL_X47_Y24_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[58]~feeder_combout\); + +-- Location: FF_X47_Y24_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(58)); + +-- Location: LABCELL_X47_Y24_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(58) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(58)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(58)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(58) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(58))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(58) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(58) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(58) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(58)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(58) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(58) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(58))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000110100000001110011011111000100111101001100011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(58), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(58), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(58), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~1_combout\); + +-- Location: LABCELL_X47_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111111111001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux227~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux227~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~2_combout\); + +-- Location: FF_X47_Y24_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(58)); + +-- Location: MLABCELL_X37_Y28_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0_combout\); + +-- Location: MLABCELL_X37_Y28_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101001011111000010100101111100001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1_combout\); + +-- Location: MLABCELL_X37_Y28_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3_combout\); + +-- Location: MLABCELL_X37_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111010101010101010100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\); + +-- Location: MLABCELL_X37_Y28_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100001101001111010000000111110001110011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\); + +-- Location: FF_X41_Y26_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_OTERM2579\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(58)); + +-- Location: LABCELL_X41_Y26_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13384\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(58) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(58) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(58) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(58) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000101110011110100010100110000011101011111111101110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(58), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\); + +-- Location: LABCELL_X41_Y26_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_OTERM2579\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(58) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000101101110101111111100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_OTERM2579\); + +-- Location: FF_X41_Y26_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_OTERM2579\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE_q\); + +-- Location: FF_X44_Y24_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(58)); + +-- Location: LABCELL_X43_Y23_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[58]~feeder_combout\); + +-- Location: FF_X43_Y23_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(58)); + +-- Location: MLABCELL_X45_Y24_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[58]~feeder_combout\); + +-- Location: FF_X45_Y24_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(58)); + +-- Location: FF_X44_Y24_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(58)); + +-- Location: LABCELL_X44_Y24_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(58)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(58) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(58)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(58))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(58))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(58), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(58), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(58), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~1_combout\); + +-- Location: MLABCELL_X45_Y23_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[58]~feeder_combout\); + +-- Location: FF_X45_Y23_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(58)); + +-- Location: FF_X41_Y24_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(58)); + +-- Location: MLABCELL_X45_Y24_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[58]~feeder_combout\); + +-- Location: FF_X45_Y24_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(58)); + +-- Location: FF_X45_Y24_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(58)); + +-- Location: MLABCELL_X45_Y24_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(58)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(58) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(58)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(58))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(58))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(58), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(58), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(58), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~0_combout\); + +-- Location: LABCELL_X44_Y24_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux163~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux163~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~2_combout\); + +-- Location: FF_X44_Y24_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(58)); + +-- Location: LABCELL_X32_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101000000000000111100110101001101011111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~0_combout\); + +-- Location: FF_X32_Y25_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_NEW_REG262\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM263\); + +-- Location: FF_X26_Y17_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(26)); + +-- Location: MLABCELL_X34_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~1_RTM0266\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~1_RTM0266_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(26))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(26))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(26))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(26)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111001100110011111101010101010111110111011101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(26), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~1_RTM0266_combout\); + +-- Location: FF_X34_Y25_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_NEW_REG264\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~1_RTM0266_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM265\); + +-- Location: FF_X31_Y25_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_NEW_REG260\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM261\); + +-- Location: LABCELL_X32_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM261\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM261\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM263\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM265\) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM261\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM263\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM265\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM261\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM263\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM265\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011011100110111001101110011011100110111001101111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM263\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM265\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM225\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM261\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM227\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\); + +-- Location: MLABCELL_X42_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1388~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[58]~feeder_combout\); + +-- Location: FF_X42_Y17_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(58)); + +-- Location: FF_X42_Y14_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(58)); + +-- Location: FF_X42_Y14_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(58)); + +-- Location: FF_X42_Y14_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(58)); + +-- Location: MLABCELL_X42_Y14_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(58))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(58))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(58)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(58) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(58) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(58), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(58), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(58), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~0_combout\); + +-- Location: LABCELL_X39_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1388~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[58]~feeder_combout\); + +-- Location: FF_X39_Y20_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(58)); + +-- Location: LABCELL_X40_Y18_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1388~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[58]~feeder_combout\); + +-- Location: FF_X40_Y18_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(58)); + +-- Location: MLABCELL_X42_Y17_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1388~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[58]~feeder_combout\); + +-- Location: FF_X42_Y17_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(58)); + +-- Location: FF_X39_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(58)); + +-- Location: LABCELL_X39_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(58)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(58) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(58) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(58))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(58))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(58), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(58), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(58), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~1_combout\); + +-- Location: LABCELL_X39_Y17_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010110101010101010101111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux35~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux35~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~2_combout\); + +-- Location: FF_X39_Y17_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(58)); + +-- Location: MLABCELL_X37_Y30_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111100001111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~1_combout\); + +-- Location: MLABCELL_X37_Y28_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000000110000001111110011111100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][10]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~0_combout\); + +-- Location: LABCELL_X39_Y27_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13254\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13254_BDD13255\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~0_combout\ +-- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000001100000011111101011111010111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1452~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1452~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13254_BDD13255\); + +-- Location: LABCELL_X39_Y27_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13256\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13254_BDD13255\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13254_BDD13255\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100101111001011110010111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[58]_NEW2484_RESYN13254_BDD13255\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(58), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\); + +-- Location: LABCELL_X39_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_OTERM2485\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_OTERM2485\); + +-- Location: FF_X39_Y27_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_OTERM2485\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58)); + +-- Location: FF_X40_Y20_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(58)); + +-- Location: FF_X43_Y20_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(58)); + +-- Location: LABCELL_X43_Y21_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[58]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(58), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[58]~feeder_combout\); + +-- Location: FF_X43_Y21_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(58)); + +-- Location: FF_X43_Y20_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(58)); + +-- Location: LABCELL_X43_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(58))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(58))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(58)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(58) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(58) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100000000001100111111111100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(58), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(58), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(58), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~0_combout\); + +-- Location: MLABCELL_X42_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[58]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[58]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(58), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[58]~feeder_combout\); + +-- Location: FF_X42_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[58]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(58)); + +-- Location: FF_X41_Y20_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(58)); + +-- Location: FF_X42_Y20_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(58)); + +-- Location: FF_X39_Y20_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(58)); + +-- Location: MLABCELL_X42_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(58) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(58) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(58) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(58))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(58) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(58) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(58))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(58) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(58) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(58)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(58))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011000001010000001100000101111100111111010100000011111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(58), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(58), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(58), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~1_combout\); + +-- Location: LABCELL_X43_Y20_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux99~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux99~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~2_combout\); + +-- Location: FF_X43_Y20_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(58)); + +-- Location: LABCELL_X43_Y20_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(58))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(58)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(58) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(58))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(58)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(58) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(58)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(58) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(58)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111101010011010100110101001101010011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(58), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(58), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(58), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~0_combout\); + +-- Location: MLABCELL_X37_Y10_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(2))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(2))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011000000111111001100000101000001011111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(26), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector50~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~1_combout\); + +-- Location: LABCELL_X36_Y10_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(54)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(57))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(57) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(57), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(54), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~34_combout\); + +-- Location: MLABCELL_X23_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[26]_NEW2138\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[26]_OTERM2139\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(26))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(26))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(26), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[26]_OTERM2139\); + +-- Location: FF_X23_Y17_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[26]_OTERM2139\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26)); + +-- Location: FF_X26_Y10_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(26)); + +-- Location: LABCELL_X26_Y10_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[26]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[26]~feeder_combout\); + +-- Location: FF_X26_Y10_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(26)); + +-- Location: FF_X26_Y12_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(26)); + +-- Location: LABCELL_X25_Y12_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[26]~feeder_combout\); + +-- Location: FF_X25_Y12_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(26)); + +-- Location: LABCELL_X26_Y12_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(26) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(26) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(26)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(26) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(26))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(26) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(26))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100000000001101011111000000110101000011110011010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(26), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~0_combout\); + +-- Location: FF_X24_Y12_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(26)); + +-- Location: LABCELL_X25_Y12_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[26]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[26]~feeder_combout\); + +-- Location: FF_X25_Y12_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[26]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(26)); + +-- Location: FF_X26_Y12_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(26)); + +-- Location: FF_X24_Y12_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(26)); + +-- Location: LABCELL_X26_Y12_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(26) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(26) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(26) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(26))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(26) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(26) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(26) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(26)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(26) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(26) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(26)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(26))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100000000000110110101010100011011101010100001101111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(26), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(26), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(26), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~1_combout\); + +-- Location: LABCELL_X26_Y12_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux351~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux351~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~2_combout\); + +-- Location: FF_X26_Y12_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(26)); + +-- Location: LABCELL_X36_Y12_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(50))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(26)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110000001111110011000000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(50), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~6_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(26), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~12_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~33_combout\); + +-- Location: LABCELL_X36_Y10_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~35_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~33_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~34_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101000000000111110100000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector50~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~34_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~33_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~35_combout\); + +-- Location: LABCELL_X36_Y10_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(58) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(58)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~35_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110011111100000011001111110000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~35_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(58), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~36_combout\); + +-- Location: FF_X36_Y10_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~36_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(58)); + +-- Location: LABCELL_X36_Y10_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(55)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(58))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(58)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(58), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(55), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~42_combout\); + +-- Location: MLABCELL_X23_Y15_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[27]_NEW2118\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[27]_OTERM2119\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(27))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(27))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100001111010101010000111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[27]_OTERM2119\); + +-- Location: FF_X23_Y15_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[27]_OTERM2119\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27)); + +-- Location: LABCELL_X25_Y12_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[27]~feeder_combout\); + +-- Location: FF_X25_Y12_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(27)); + +-- Location: LABCELL_X26_Y10_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[27]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[27]~feeder_combout\); + +-- Location: FF_X26_Y10_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(27)); + +-- Location: MLABCELL_X28_Y10_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[27]~feeder_combout\); + +-- Location: FF_X28_Y10_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(27)); + +-- Location: FF_X28_Y10_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(27)); + +-- Location: MLABCELL_X28_Y10_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(27))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(27))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(27)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(27) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(27)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100001111110011111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(27), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(27), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~0_combout\); + +-- Location: LABCELL_X25_Y12_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[27]~feeder_combout\); + +-- Location: FF_X25_Y12_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(27)); + +-- Location: FF_X29_Y11_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(27)); + +-- Location: FF_X32_Y10_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(27)); + +-- Location: FF_X32_Y10_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(27)); + +-- Location: LABCELL_X32_Y10_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(27)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(27) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(27) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(27)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(27)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(27), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~1_combout\); + +-- Location: LABCELL_X31_Y10_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux350~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux350~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~2_combout\); + +-- Location: FF_X31_Y10_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(27)); + +-- Location: LABCELL_X36_Y10_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(27)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(51) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(51), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~41_combout\); + +-- Location: LABCELL_X17_Y32_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000000011111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~9_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~19_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~14_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_combout\); + +-- Location: LABCELL_X31_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[3]_NEW2240\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[3]_OTERM2241\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[3]_OTERM2241\); + +-- Location: FF_X31_Y29_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[3]_OTERM2241\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(3)); + +-- Location: FF_X34_Y9_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(3)); + +-- Location: FF_X34_Y9_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(3)); + +-- Location: FF_X35_Y9_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(3)); + +-- Location: LABCELL_X35_Y9_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[3]~feeder_combout\); + +-- Location: FF_X35_Y9_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(3)); + +-- Location: LABCELL_X35_Y9_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(3) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(3) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(3)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(3))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100000000000111010011001100011101110011000001110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~1_combout\); + +-- Location: FF_X37_Y9_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(3)); + +-- Location: FF_X37_Y9_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(3)); + +-- Location: FF_X36_Y9_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(3)); + +-- Location: FF_X36_Y9_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(3)); + +-- Location: LABCELL_X36_Y9_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(3))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(3))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~0_combout\); + +-- Location: LABCELL_X35_Y9_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011001100110000110011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux290~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux290~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~2_combout\); + +-- Location: FF_X35_Y9_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(3)); + +-- Location: MLABCELL_X23_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[27]_NEW2120\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[27]_OTERM2121\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(27))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(27))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(27))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(27)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110101011000000011010101101000101111011110100010111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[27]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[27]_OTERM2121\); + +-- Location: FF_X23_Y17_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[27]_OTERM2121\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(27)); + +-- Location: LABCELL_X29_Y11_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[27]~feeder_combout\); + +-- Location: FF_X29_Y11_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(27)); + +-- Location: LABCELL_X25_Y10_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[27]~feeder_combout\); + +-- Location: FF_X25_Y10_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(27)); + +-- Location: FF_X28_Y10_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(27)); + +-- Location: MLABCELL_X28_Y11_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[27]~feeder_combout\); + +-- Location: FF_X28_Y11_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(27)); + +-- Location: MLABCELL_X28_Y10_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(27) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(27)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(27))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(27) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(27) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(27) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(27) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(27))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(27) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(27) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(27) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100100010000001010111011110101111001000101010111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~1_combout\); + +-- Location: LABCELL_X26_Y10_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[27]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(27) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[27]~feeder_combout\); + +-- Location: FF_X26_Y10_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(27)); + +-- Location: LABCELL_X25_Y10_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[27]~feeder_combout\); + +-- Location: FF_X25_Y10_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(27)); + +-- Location: MLABCELL_X28_Y10_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(27) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(27), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[27]~feeder_combout\); + +-- Location: FF_X28_Y10_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[27]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(27)); + +-- Location: FF_X28_Y10_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(27), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(27)); + +-- Location: MLABCELL_X28_Y10_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(27))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(27) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(27))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(27) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(27)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(27) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(27) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001000100011101110111011100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(27), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(27), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(27), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(27), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~0_combout\); + +-- Location: LABCELL_X29_Y10_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~1_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000010100000101000001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux382~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux382~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~2_combout\); + +-- Location: FF_X29_Y10_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(27)); + +-- Location: LABCELL_X36_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001101110111011101100010001000100011011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2_combout\); + +-- Location: LABCELL_X36_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0_combout\); + +-- Location: LABCELL_X36_Y29_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000010101010101010111111111111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3_combout\); + +-- Location: LABCELL_X36_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111110000111100001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\); + +-- Location: MLABCELL_X37_Y29_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13402\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011010001010110011110001001101010111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\); + +-- Location: FF_X35_Y34_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_OTERM2592\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(59)); + +-- Location: LABCELL_X35_Y34_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13404\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(59) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(59) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(59) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(59) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000000010000101100010001101110111111000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(59), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\); + +-- Location: LABCELL_X35_Y34_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_OTERM2592\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(59) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010001111111110101110100000000010101011111111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_OTERM2592\); + +-- Location: FF_X35_Y34_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_OTERM2592\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE_q\); + +-- Location: FF_X45_Y23_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(59)); + +-- Location: LABCELL_X43_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[59]~feeder_combout\); + +-- Location: FF_X43_Y22_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[59]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(59)); + +-- Location: LABCELL_X43_Y22_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[59]~feeder_combout\); + +-- Location: FF_X43_Y22_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[59]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(59)); + +-- Location: FF_X43_Y22_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(59)); + +-- Location: LABCELL_X43_Y22_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(59)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(59) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(59)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(59))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(59))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(59), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(59), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(59), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~1_combout\); + +-- Location: FF_X45_Y22_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(59)); + +-- Location: LABCELL_X52_Y20_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[59]~feeder_combout\); + +-- Location: FF_X52_Y20_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[59]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(59)); + +-- Location: LABCELL_X52_Y20_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[59]~feeder_combout\); + +-- Location: FF_X52_Y20_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[59]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(59)); + +-- Location: FF_X52_Y20_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(59)); + +-- Location: LABCELL_X52_Y20_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(59))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(59))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(59)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(59) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(59)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100001100111111111100011101000111010001110100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(59), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(59), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(59), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~0_combout\); + +-- Location: LABCELL_X53_Y14_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux162~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux162~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~2_combout\); + +-- Location: FF_X53_Y14_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(59)); + +-- Location: LABCELL_X36_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101101011111010111100010001101110110001000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~1_combout\); + +-- Location: LABCELL_X36_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111110011010100000101000000000011111100110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][11]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~0_combout\); + +-- Location: LABCELL_X36_Y26_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13226\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13226_BDD13227\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\))) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~1_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~1_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011100010101001101101000110010101111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1451~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1451~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13226_BDD13227\); + +-- Location: FF_X37_Y26_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_OTERM2471\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]~DUPLICATE_q\); + +-- Location: MLABCELL_X37_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13228\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13226_BDD13227\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13226_BDD13227\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011011101000000001101110100100010111111110010001011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]_NEW2470_RESYN13226_BDD13227\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\); + +-- Location: MLABCELL_X37_Y26_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_OTERM2471\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_OTERM2471\); + +-- Location: FF_X37_Y26_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_OTERM2471\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59)); + +-- Location: FF_X49_Y20_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(59)); + +-- Location: LABCELL_X43_Y21_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(59), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[59]~feeder_combout\); + +-- Location: FF_X43_Y21_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[59]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(59)); + +-- Location: LABCELL_X43_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(59), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[59]~feeder_combout\); + +-- Location: FF_X43_Y21_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[59]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(59)); + +-- Location: FF_X43_Y21_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(59)); + +-- Location: LABCELL_X43_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(59)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(59) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(59) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(59))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(59))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111001111000000111100111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(59), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(59), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(59), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~0_combout\); + +-- Location: LABCELL_X41_Y21_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(59), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[59]~feeder_combout\); + +-- Location: FF_X41_Y21_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[59]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(59)); + +-- Location: FF_X47_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(59)); + +-- Location: FF_X47_Y16_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(59)); + +-- Location: FF_X47_Y16_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(59)); + +-- Location: LABCELL_X47_Y16_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(59) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(59) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(59) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(59))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(59) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(59) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(59))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(59) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(59) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(59))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010100010000001111010011101010010111100100101011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(59), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(59), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(59), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~1_combout\); + +-- Location: LABCELL_X53_Y14_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~1_combout\ ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111111111111111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux98~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux98~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~2_combout\); + +-- Location: FF_X53_Y14_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(59)); + +-- Location: LABCELL_X36_Y29_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111001101010011010111110000111111110011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~5_combout\); + +-- Location: LABCELL_X36_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001010100010010100101111001000000111101001110101011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][11]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~6_combout\); + +-- Location: LABCELL_X44_Y33_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100000011000000111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~8_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~11_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~2_combout\); + +-- Location: LABCELL_X44_Y33_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3_combout\) ) ) ) # +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~0_combout\); + +-- Location: LABCELL_X44_Y33_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~5_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~5_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~4_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101111111110101010100001111001100110000111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~4_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~7_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~1_combout\); + +-- Location: LABCELL_X44_Y33_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~15_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~15_combout\) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~14_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~14_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux264~12_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~12_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~14_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~3_combout\); + +-- Location: LABCELL_X44_Y33_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~2_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~2_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001101100011011000000001010101000011011000110110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~4_combout\); + +-- Location: LABCELL_X40_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13230\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13230_BDD13231\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~6_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000100010001000110101010111111111011101110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~6_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13230_BDD13231\); + +-- Location: FF_X40_Y29_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_OTERM2473\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(59)); + +-- Location: LABCELL_X40_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13232\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(59) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13230_BDD13231\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(59) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13230_BDD13231\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101111000000001010111101010000111111110101000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]_NEW2472_RESYN13230_BDD13231\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(59), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\); + +-- Location: LABCELL_X40_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_OTERM2473\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(59) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001110111111101110100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_OTERM2473\); + +-- Location: FF_X40_Y29_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_OTERM2473\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE_q\); + +-- Location: FF_X44_Y26_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(59)); + +-- Location: FF_X44_Y26_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(59)); + +-- Location: MLABCELL_X45_Y26_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[59]~feeder_combout\); + +-- Location: FF_X45_Y26_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[59]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(59)); + +-- Location: FF_X44_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(59)); + +-- Location: LABCELL_X44_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(59)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(59) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(59)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(59))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(59))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100011101000111010001110100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(59), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(59), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(59), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~0_combout\); + +-- Location: FF_X52_Y27_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(59)); + +-- Location: FF_X52_Y27_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(59)); + +-- Location: LABCELL_X53_Y27_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[59]~feeder_combout\); + +-- Location: FF_X53_Y27_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[59]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(59)); + +-- Location: FF_X52_Y27_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(59)); + +-- Location: LABCELL_X52_Y27_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(59)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(59) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(59) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(59))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(59))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111110101000001011111010100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(59), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(59), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(59), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~1_combout\); + +-- Location: LABCELL_X53_Y26_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111001111110011111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux226~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux226~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~2_combout\); + +-- Location: FF_X53_Y26_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(59)); + +-- Location: FF_X32_Y25_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_NEW_REG731\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM732\); + +-- Location: LABCELL_X39_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000010100000101000001010000010100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~38_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~0_combout\); + +-- Location: FF_X39_Y25_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_NEW_REG733\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM734\); + +-- Location: FF_X21_Y14_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(27)); + +-- Location: MLABCELL_X37_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000100011011101101011111010111110001000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~1_combout\); + +-- Location: LABCELL_X36_Y27_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000011110000111101010101010101010101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~2_combout\); + +-- Location: LABCELL_X36_Y27_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~3_RTM0738\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~3_RTM0738_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~1_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~2_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(27))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~2_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(27)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011010101010111011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(27), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~3_RTM0738_combout\); + +-- Location: FF_X36_Y27_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_NEW_REG736\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~3_RTM0738_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM737\); + +-- Location: LABCELL_X39_Y25_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM734\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM737\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM734\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM737\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM734\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM737\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM732\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711~DUPLICATE_q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM734\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM737\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM732\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011011111000000000101011111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM711~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM623\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM732\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM715\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM734\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM737\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\); + +-- Location: MLABCELL_X42_Y22_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[59]~feeder_combout\); + +-- Location: FF_X42_Y22_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[59]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(59)); + +-- Location: FF_X44_Y19_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(59)); + +-- Location: FF_X41_Y19_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(59)); + +-- Location: FF_X41_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(59)); + +-- Location: LABCELL_X41_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(59)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(59) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(59) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(59))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(59)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(59))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(59)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111101000100010001000111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(59), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(59), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(59), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~1_combout\); + +-- Location: LABCELL_X43_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[59]~feeder_combout\); + +-- Location: FF_X43_Y17_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[59]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(59)); + +-- Location: LABCELL_X44_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[59]~feeder_combout\); + +-- Location: FF_X44_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[59]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(59)); + +-- Location: FF_X44_Y17_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(59)); + +-- Location: LABCELL_X44_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[59]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[59]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[59]~feeder_combout\); + +-- Location: FF_X44_Y17_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[59]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(59)); + +-- Location: LABCELL_X44_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(59) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(59))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(59))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(59) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(59) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(59) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(59) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(59) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(59))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(59) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(59) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(59))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(59)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100111010101010010011110101010001001111111111100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(59), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(59), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(59), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~0_combout\); + +-- Location: LABCELL_X44_Y19_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux34~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux34~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~2_combout\); + +-- Location: FF_X44_Y19_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(59)); + +-- Location: LABCELL_X53_Y14_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(59) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(59) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(59)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(59)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(59) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(59) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(59)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(59))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(59) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(59) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(59)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(59))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(59) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(59) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(59)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(59))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100010001000000111101110111001111000100011100111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(59), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(59), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(59), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~0_combout\); + +-- Location: LABCELL_X31_Y29_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[3]_NEW2243\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[3]_OTERM2244\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\))))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000100000101010000010000010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[3]_OTERM2244\); + +-- Location: FF_X31_Y29_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[3]_OTERM2244\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3)); + +-- Location: FF_X48_Y24_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(3)); + +-- Location: FF_X48_Y24_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(3)); + +-- Location: FF_X48_Y24_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(3)); + +-- Location: FF_X37_Y24_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(3)); + +-- Location: LABCELL_X48_Y24_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(3) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(3))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(3)))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(3) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(3) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(3)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(3) & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110000000001010011111111110101001100001111010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~1_combout\); + +-- Location: LABCELL_X43_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[3]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[3]~feeder_combout\); + +-- Location: FF_X43_Y25_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(3)); + +-- Location: MLABCELL_X42_Y26_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[3]~feeder_combout\); + +-- Location: FF_X42_Y26_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(3)); + +-- Location: LABCELL_X44_Y27_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[3]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(3), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[3]~feeder_combout\); + +-- Location: FF_X44_Y27_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[3]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(3)); + +-- Location: FF_X43_Y25_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(3)); + +-- Location: LABCELL_X43_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(3))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(3))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(3) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(3)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010010111110101111100010001101110110001000110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(3), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(3), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(3), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~0_combout\); + +-- Location: LABCELL_X43_Y25_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux296~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux296~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~2_combout\); + +-- Location: FF_X43_Y25_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(3)); + +-- Location: MLABCELL_X37_Y10_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(3) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(3))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(27)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(3))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(3), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(27), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector49~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~11_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~1_combout\); + +-- Location: LABCELL_X36_Y10_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~42_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~41_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~1_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~42_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~41_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000101000001010000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~42_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~41_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector49~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~9_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~43_combout\); + +-- Location: LABCELL_X36_Y10_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(59) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(59)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~43_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101011111010000010101111101000000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~43_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(59), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~44_combout\); + +-- Location: FF_X36_Y10_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~44_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(59)); + +-- Location: LABCELL_X36_Y10_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(56))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(59)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(59) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(56), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(59), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~20_combout\); + +-- Location: FF_X18_Y17_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[28]~41_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(28)); + +-- Location: LABCELL_X19_Y17_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[28]_NEW2162\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[28]_OTERM2163\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(28))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(28)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(28) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[28]_OTERM2163\); + +-- Location: FF_X19_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[28]_OTERM2163\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(28)); + +-- Location: LABCELL_X25_Y12_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[28]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(28) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[28]~feeder_combout\); + +-- Location: FF_X25_Y12_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(28)); + +-- Location: LABCELL_X24_Y12_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[28]~feeder_combout\); + +-- Location: FF_X24_Y12_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(28)); + +-- Location: FF_X25_Y12_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(28)); + +-- Location: FF_X24_Y12_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(28)); + +-- Location: LABCELL_X25_Y12_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(28) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(28))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(28) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(28)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(28)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(28)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011111101011111001100000101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(28), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~1_combout\); + +-- Location: LABCELL_X26_Y10_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[28]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(28) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[28]~feeder_combout\); + +-- Location: FF_X26_Y10_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(28)); + +-- Location: FF_X26_Y10_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(28)); + +-- Location: LABCELL_X25_Y12_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[28]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(28) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[28]~feeder_combout\); + +-- Location: FF_X25_Y12_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(28)); + +-- Location: FF_X26_Y10_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(28)); + +-- Location: LABCELL_X26_Y10_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(28)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(28) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(28) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(28))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(28))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101010101001100110101010100000000000011111111111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(28), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~0_combout\); + +-- Location: LABCELL_X31_Y10_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~1_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~1_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000000000000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux381~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux381~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~2_combout\); + +-- Location: FF_X31_Y10_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(28)); + +-- Location: LABCELL_X21_Y32_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~19_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~14_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~9_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~4_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000000001111111100001111000011110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~19_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_combout\); + +-- Location: LABCELL_X31_Y29_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[4]_NEW2261\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[4]_OTERM2262\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(4) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[4]_OTERM2262\); + +-- Location: FF_X31_Y29_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[4]_OTERM2262\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(4)); + +-- Location: MLABCELL_X37_Y9_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[4]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(4) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[4]~feeder_combout\); + +-- Location: FF_X37_Y9_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(4)); + +-- Location: FF_X37_Y9_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(4)); + +-- Location: FF_X37_Y9_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(4)); + +-- Location: FF_X36_Y9_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(4)); + +-- Location: MLABCELL_X37_Y9_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(4)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(4)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(4))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(4)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(4))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(4) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(4))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000101000000111111010111110011000001011111001111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~0_combout\); + +-- Location: MLABCELL_X34_Y9_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[4]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(4) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[4]~feeder_combout\); + +-- Location: FF_X34_Y9_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(4)); + +-- Location: LABCELL_X35_Y9_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[4]~feeder_combout\); + +-- Location: FF_X35_Y9_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(4)); + +-- Location: FF_X34_Y9_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(4)); + +-- Location: FF_X34_Y9_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(4)); + +-- Location: MLABCELL_X34_Y9_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(4)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(4))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(4))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~1_combout\); + +-- Location: MLABCELL_X37_Y10_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux289~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux289~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~2_combout\); + +-- Location: FF_X37_Y10_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(4)); + +-- Location: LABCELL_X40_Y25_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\); + +-- Location: LABCELL_X40_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\); + +-- Location: LABCELL_X40_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\); + +-- Location: LABCELL_X40_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000110011111111110011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\); + +-- Location: LABCELL_X40_Y25_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13442\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13442_BDD13443\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100000000001001111010101000100111010101010010011111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13442_BDD13443\); + +-- Location: FF_X41_Y26_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_OTERM2617\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(60)); + +-- Location: LABCELL_X41_Y26_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13444\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(60) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13442_BDD13443\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(60) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(60) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13442_BDD13443\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(60) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000000001101110100101111001011110010001011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]_NEW2616_RESYN13442_BDD13443\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\); + +-- Location: LABCELL_X41_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_OTERM2617\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(60) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(60) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000101101110101111111100000000010101011010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_OTERM2617\); + +-- Location: FF_X41_Y26_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_OTERM2617\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y24_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[60]~feeder_combout\); + +-- Location: FF_X43_Y24_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(60)); + +-- Location: FF_X48_Y24_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(60)); + +-- Location: FF_X45_Y24_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(60)); + +-- Location: FF_X43_Y24_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(60)); + +-- Location: LABCELL_X43_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(60)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(60) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(60) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(60) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(60))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(60)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(60) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(60))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(60)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100001111010101010000111100110011000000000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(60), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(60), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(60), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~1_combout\); + +-- Location: MLABCELL_X42_Y26_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[60]~feeder_combout\); + +-- Location: FF_X42_Y26_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(60)); + +-- Location: MLABCELL_X42_Y26_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[60]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[60]~feeder_combout\); + +-- Location: FF_X42_Y26_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(60)); + +-- Location: FF_X42_Y26_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(60)); + +-- Location: FF_X45_Y26_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(60)); + +-- Location: MLABCELL_X42_Y26_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(60) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(60))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(60))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(60) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(60))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(60)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(60) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(60))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(60)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(60) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(60))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(60)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000001010011101110000101000100010010111110111011101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(60), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(60), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~0_combout\); + +-- Location: MLABCELL_X42_Y22_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux161~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux161~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~2_combout\); + +-- Location: FF_X42_Y22_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(60)); + +-- Location: FF_X21_Y14_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|MEM_DATA_READ[28]~41_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(28)); + +-- Location: MLABCELL_X34_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~1_RTM0232\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~1_RTM0232_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(28)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(28)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(28)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110111000001010011011100000101001101111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~1_RTM0232_combout\); + +-- Location: FF_X34_Y25_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG230\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~1_RTM0232_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM231\); + +-- Location: LABCELL_X40_Y25_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011100000100110001111111010000110111001101001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~2_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~0_combout\); + +-- Location: FF_X34_Y25_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG228\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM229\); + +-- Location: LABCELL_X32_Y25_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223~feeder_combout\); + +-- Location: FF_X32_Y25_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG222\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223\); + +-- Location: LABCELL_X36_Y21_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM229\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM231\) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM229\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\)) +-- # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM231\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM229\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM231\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100111111001100110011111100110011001111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM231\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM229\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM225\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM227\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM223\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\); + +-- Location: LABCELL_X36_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1386~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[60]~feeder_combout\); + +-- Location: FF_X36_Y20_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(60)); + +-- Location: FF_X37_Y20_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(60)); + +-- Location: FF_X37_Y20_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(60)); + +-- Location: FF_X36_Y21_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(60)); + +-- Location: MLABCELL_X37_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(60) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(60) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(60))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(60) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(60))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(60) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(60))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(60), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(60), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~1_combout\); + +-- Location: MLABCELL_X42_Y16_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1386~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[60]~feeder_combout\); + +-- Location: FF_X42_Y16_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(60)); + +-- Location: FF_X39_Y16_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(60)); + +-- Location: FF_X42_Y16_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(60)); + +-- Location: MLABCELL_X42_Y16_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1386~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[60]~feeder_combout\); + +-- Location: FF_X42_Y16_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(60)); + +-- Location: MLABCELL_X42_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(60) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(60))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(60)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(60))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(60) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(60) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(60) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(60)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(60) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(60) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(60) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(60) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000010001001111110001000100001100110111010011111111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(60), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(60), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~0_combout\); + +-- Location: MLABCELL_X37_Y20_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux33~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux33~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~2_combout\); + +-- Location: FF_X37_Y20_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(60)); + +-- Location: LABCELL_X40_Y25_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~5_combout\); + +-- Location: LABCELL_X40_Y25_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~6_combout\); + +-- Location: LABCELL_X43_Y29_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~13_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~15_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~12_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~14_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100001111000011110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~15_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~3_combout\); + +-- Location: LABCELL_X43_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001001110111001000100111011100000101000001011010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~2_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~0_combout\); + +-- Location: LABCELL_X43_Y29_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100110011000011110011001101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~11_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~8_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~9_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~2_combout\); + +-- Location: LABCELL_X43_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~5_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~7_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~4_combout\ +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~6_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101001100110011001100000000111111110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~4_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~7_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~1_combout\); + +-- Location: LABCELL_X43_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000110001001010001011100110100100011101010110110011111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~4_combout\); + +-- Location: MLABCELL_X45_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13446\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13446_BDD13447\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~5_combout\))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~6_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~5_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001011000000010000101111110001111110111111000111111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~5_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~6_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13446_BDD13447\); + +-- Location: FF_X42_Y27_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_OTERM2620\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y27_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13448\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13446_BDD13447\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13446_BDD13447\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000011000011110000001100001111110011110000111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]_NEW2619_RESYN13446_BDD13447\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\); + +-- Location: MLABCELL_X42_Y27_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_OTERM2620\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110111001100110000100011001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_OTERM2620\); + +-- Location: FF_X42_Y27_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_OTERM2620\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60)); + +-- Location: FF_X48_Y29_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(60)); + +-- Location: MLABCELL_X49_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[60]~feeder_combout\); + +-- Location: FF_X49_Y29_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(60)); + +-- Location: FF_X48_Y29_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(60)); + +-- Location: FF_X48_Y29_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(60)); + +-- Location: LABCELL_X48_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(60))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(60))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(60) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(60)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(60) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(60)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010011101110111011100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(60), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(60), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(60), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~0_combout\); + +-- Location: LABCELL_X52_Y30_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[60]~feeder_combout\); + +-- Location: FF_X52_Y30_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(60)); + +-- Location: LABCELL_X52_Y30_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[60]~feeder_combout\); + +-- Location: FF_X52_Y30_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(60)); + +-- Location: FF_X52_Y30_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(60)); + +-- Location: LABCELL_X50_Y30_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[60]~feeder_combout\); + +-- Location: FF_X50_Y30_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(60)); + +-- Location: LABCELL_X52_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(60) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(60) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(60))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(60) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(60))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(60) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(60))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100000011000111011100111111010001000011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(60), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(60), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~1_combout\); + +-- Location: LABCELL_X50_Y28_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux225~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux225~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~2_combout\); + +-- Location: FF_X50_Y28_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(60)); + +-- Location: LABCELL_X40_Y25_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010010001100001001101010111000010101100111010011011110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~1_combout\); + +-- Location: LABCELL_X40_Y25_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~0_combout\); + +-- Location: LABCELL_X40_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13438\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13438_BDD13439\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~1_combout\)) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~1_combout\)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010010101011111111100011011000110110001101100011011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1450~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1450~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13438_BDD13439\); + +-- Location: FF_X40_Y27_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_OTERM2615\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~DUPLICATE_q\); + +-- Location: LABCELL_X40_Y27_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13440\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13438_BDD13439\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13438_BDD13439\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110100001101000011010000110100101111001011110010111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]_NEW2614_RESYN13438_BDD13439\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\); + +-- Location: LABCELL_X40_Y27_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_OTERM2615\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000100011110111001111111100000000001100111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_OTERM2615\); + +-- Location: FF_X40_Y27_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_OTERM2615\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60)); + +-- Location: MLABCELL_X49_Y20_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[60]~feeder_combout\); + +-- Location: FF_X49_Y20_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(60)); + +-- Location: LABCELL_X52_Y20_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[60]~feeder_combout\); + +-- Location: FF_X52_Y20_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(60)); + +-- Location: LABCELL_X52_Y20_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[60]~feeder_combout\); + +-- Location: FF_X52_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(60)); + +-- Location: FF_X52_Y20_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(60)); + +-- Location: LABCELL_X52_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(60))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(60)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(60))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(60) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(60)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(60) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(60)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110000000011111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(60), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(60), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(60), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~0_combout\); + +-- Location: LABCELL_X48_Y21_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[60]~feeder_combout\); + +-- Location: FF_X48_Y21_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(60)); + +-- Location: LABCELL_X47_Y23_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[60]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[60]~feeder_combout\); + +-- Location: FF_X47_Y23_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(60)); + +-- Location: FF_X47_Y23_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(60)); + +-- Location: LABCELL_X43_Y24_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[60]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[60]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[60]~feeder_combout\); + +-- Location: FF_X43_Y24_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[60]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(60)); + +-- Location: LABCELL_X47_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(60) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(60))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(60)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(60) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(60))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(60) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(60) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(60) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(60) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(60)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(60) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(60) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(60) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(60) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100110000000001010011111111110101001100001111010100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(60), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(60), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(60), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~1_combout\); + +-- Location: MLABCELL_X42_Y22_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux97~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux97~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~2_combout\); + +-- Location: FF_X42_Y22_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(60)); + +-- Location: MLABCELL_X42_Y22_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(60) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(60) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(60) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(60) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(60), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(60), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(60), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(60), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~0_combout\); + +-- Location: LABCELL_X20_Y32_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[4]_NEW2264\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[4]_OTERM2265\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\))))) ) ) +-- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001001110000000000100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~9_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[4]_OTERM2265\); + +-- Location: FF_X20_Y32_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[4]_OTERM2265\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4)); + +-- Location: LABCELL_X47_Y13_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[4]~feeder_combout\); + +-- Location: FF_X47_Y13_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(4)); + +-- Location: FF_X48_Y15_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(4)); + +-- Location: FF_X47_Y15_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(4)); + +-- Location: FF_X48_Y15_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(4)); + +-- Location: LABCELL_X48_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(4)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(4)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(4)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100011101000111010001110100011100000000110011000011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(4), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~1_combout\); + +-- Location: LABCELL_X52_Y16_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[4]~feeder_combout\); + +-- Location: FF_X52_Y16_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(4)); + +-- Location: LABCELL_X40_Y14_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[4]~feeder_combout\); + +-- Location: FF_X40_Y14_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(4)); + +-- Location: FF_X52_Y16_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(4)); + +-- Location: LABCELL_X40_Y14_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[4]~feeder_combout\); + +-- Location: FF_X40_Y14_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[4]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(4)); + +-- Location: LABCELL_X52_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(4)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(4) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(4) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(4) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(4))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(4)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(4) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(4))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100001101001100010011110111000001110011011111000111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(4), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~0_combout\); + +-- Location: MLABCELL_X49_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux295~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux295~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~2_combout\); + +-- Location: FF_X49_Y13_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(4)); + +-- Location: MLABCELL_X37_Y10_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(4) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(4)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(4)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(4)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100000001001100011100000111110001000011010011110111001101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(4), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector48~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(4), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~1_combout\); + +-- Location: LABCELL_X21_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[28]_NEW2160\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[28]_OTERM2161\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(28)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(28)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111101000111010001110100011101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(28), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[28]_OTERM2161\); + +-- Location: FF_X21_Y17_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[28]_OTERM2161\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28)); + +-- Location: LABCELL_X25_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[28]~feeder_combout\); + +-- Location: FF_X25_Y12_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(28)); + +-- Location: FF_X26_Y10_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(28)); + +-- Location: FF_X26_Y10_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(28)); + +-- Location: FF_X26_Y10_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(28)); + +-- Location: LABCELL_X26_Y10_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(28)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(28) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(28) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(28)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(28) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(28))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(28)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(28), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(28), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~0_combout\); + +-- Location: LABCELL_X24_Y12_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[28]~feeder_combout\); + +-- Location: FF_X24_Y12_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(28)); + +-- Location: LABCELL_X25_Y12_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[28]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[28]~feeder_combout\); + +-- Location: FF_X25_Y12_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[28]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(28)); + +-- Location: FF_X24_Y12_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(28)); + +-- Location: FF_X24_Y12_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(28)); + +-- Location: LABCELL_X24_Y12_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(28) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(28) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(28) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(28))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(28))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(28) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(28) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(28)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(28))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100000001111100011100110100111101000011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(28), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(28), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(28), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~1_combout\); + +-- Location: LABCELL_X29_Y10_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~1_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000001100110011001111001100110011001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux349~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux349~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~2_combout\); + +-- Location: FF_X29_Y10_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(28)); + +-- Location: LABCELL_X36_Y10_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(28)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(52) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(52), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~12_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(28), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~6_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~19_combout\); + +-- Location: LABCELL_X36_Y10_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~21_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~20_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~1_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011000000110011001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~20_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector48~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~19_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~21_combout\); + +-- Location: LABCELL_X40_Y10_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~21_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(60))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(60) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010111110000010101011111000001010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(60), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~21_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~22_combout\); + +-- Location: FF_X40_Y10_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~22_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(60)); + +-- Location: LABCELL_X40_Y10_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(60) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(57)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(57), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~14_combout\); + +-- Location: MLABCELL_X23_Y16_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[29]_NEW2152\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[29]_OTERM2153\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(29))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(29))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(29), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(29), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[29]_OTERM2153\); + +-- Location: FF_X23_Y16_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[29]_OTERM2153\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29)); + +-- Location: LABCELL_X24_Y12_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[29]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[29]~feeder_combout\); + +-- Location: FF_X24_Y12_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(29)); + +-- Location: FF_X25_Y12_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(29)); + +-- Location: LABCELL_X24_Y12_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[29]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[29]~feeder_combout\); + +-- Location: FF_X24_Y12_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(29)); + +-- Location: FF_X24_Y12_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(29)); + +-- Location: LABCELL_X24_Y12_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(29)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(29) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(29)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(29))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(29))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011010100110101001101010011010100000000111100000000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(29), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~1_combout\); + +-- Location: LABCELL_X26_Y10_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[29]~feeder_combout\); + +-- Location: FF_X26_Y10_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(29)); + +-- Location: FF_X25_Y12_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(29)); + +-- Location: FF_X26_Y10_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(29)); + +-- Location: LABCELL_X26_Y10_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[29]~feeder_combout\); + +-- Location: FF_X26_Y10_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(29)); + +-- Location: LABCELL_X26_Y10_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(29) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(29))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(29))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(29) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(29) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(29))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(29))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(29) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(29)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(29))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(29) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(29)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000010011010001100101011110001010100110111100111011011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(29), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~0_combout\); + +-- Location: LABCELL_X29_Y10_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux348~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux348~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~2_combout\); + +-- Location: FF_X29_Y10_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(29)); + +-- Location: LABCELL_X36_Y10_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(53) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(29)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(53) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(29))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001000000010000000101000101010001010100010101000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(53), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~13_combout\); + +-- Location: LABCELL_X31_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[5]_NEW2252\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[5]_OTERM2253\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(5) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[5]_OTERM2253\); + +-- Location: FF_X31_Y29_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[5]_OTERM2253\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(5)); + +-- Location: FF_X34_Y9_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(5)); + +-- Location: FF_X35_Y9_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(5)); + +-- Location: FF_X34_Y9_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(5)); + +-- Location: FF_X34_Y9_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(5)); + +-- Location: MLABCELL_X34_Y9_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(5)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(5) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(5)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(5)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001011111010100000101111100110000001100000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(5), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~1_combout\); + +-- Location: FF_X37_Y9_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(5)); + +-- Location: FF_X37_Y9_N47 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(5)); + +-- Location: FF_X37_Y9_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(5)); + +-- Location: FF_X36_Y9_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(5)); + +-- Location: MLABCELL_X37_Y9_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(5) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(5)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(5)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(5)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(5))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(5)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(5))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(5) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(5))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000101000000111111010111110011000001011111001111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~0_combout\); + +-- Location: MLABCELL_X37_Y10_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux288~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux288~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~2_combout\); + +-- Location: FF_X37_Y10_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(5)); + +-- Location: LABCELL_X21_Y17_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[29]_NEW2154\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[29]_OTERM2155\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(29))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(29))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(29), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[29]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[29]_OTERM2155\); + +-- Location: FF_X21_Y17_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[29]_OTERM2155\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29)); + +-- Location: LABCELL_X25_Y11_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[29]~feeder_combout\); + +-- Location: FF_X25_Y11_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(29)); + +-- Location: LABCELL_X25_Y11_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[29]~feeder_combout\); + +-- Location: FF_X25_Y11_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(29)); + +-- Location: LABCELL_X26_Y11_N21 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[29]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[29]~feeder_combout\); + +-- Location: FF_X26_Y11_N23 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(29)); + +-- Location: FF_X26_Y11_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(29)); + +-- Location: LABCELL_X26_Y11_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(29)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(29)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(29)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(29) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(29) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(29), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(29), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~0_combout\); + +-- Location: LABCELL_X25_Y11_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[29]~feeder_combout\); + +-- Location: FF_X25_Y11_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(29)); + +-- Location: LABCELL_X24_Y11_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[29]~feeder_combout\); + +-- Location: FF_X24_Y11_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(29)); + +-- Location: LABCELL_X24_Y11_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[29]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(29), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[29]~feeder_combout\); + +-- Location: FF_X24_Y11_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(29)); + +-- Location: FF_X24_Y11_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(29)); + +-- Location: LABCELL_X24_Y11_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(29) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(29)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(29) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(29)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(29)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(29) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(29)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010011100100111001001110010011100000000101010100101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(29), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(29), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(29), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~1_combout\); + +-- Location: LABCELL_X29_Y10_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001111110011111100111111001111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux380~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux380~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~2_combout\); + +-- Location: FF_X29_Y10_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(29)); + +-- Location: LABCELL_X31_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[5]_NEW2255\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[5]_OTERM2256\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\)))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000001010001010000000101000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~4_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[5]_OTERM2256\); + +-- Location: FF_X31_Y29_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[5]_OTERM2256\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5)); + +-- Location: LABCELL_X50_Y24_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[5]~feeder_combout\); + +-- Location: FF_X50_Y24_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(5)); + +-- Location: FF_X49_Y24_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(5)); + +-- Location: LABCELL_X50_Y24_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[5]~feeder_combout\); + +-- Location: FF_X50_Y24_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(5)); + +-- Location: FF_X49_Y24_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(5)); + +-- Location: MLABCELL_X49_Y24_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(5)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(5) & +-- ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(5) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) ) +-- # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(5)))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(5)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100001111001100110000111101010101000000000101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~1_combout\); + +-- Location: MLABCELL_X49_Y26_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[5]~feeder_combout\); + +-- Location: FF_X49_Y26_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(5)); + +-- Location: FF_X43_Y29_N31 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(5)); + +-- Location: LABCELL_X53_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(5), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[5]~feeder_combout\); + +-- Location: FF_X53_Y25_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[5]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(5)); + +-- Location: FF_X49_Y26_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(5)); + +-- Location: MLABCELL_X49_Y26_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(5))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(5))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(5)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(5) +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(5) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100000000000011111111111100110011010101010011001101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(5), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(5), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~0_combout\); + +-- Location: LABCELL_X47_Y24_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux294~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux294~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~2_combout\); + +-- Location: FF_X47_Y24_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(5)); + +-- Location: FF_X37_Y23_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_OTERM2608\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(61)); + +-- Location: MLABCELL_X37_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111001100110011001101010101010101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~1_combout\); + +-- Location: MLABCELL_X37_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001100110011001101010101010101010000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~0_combout\); + +-- Location: LABCELL_X35_Y22_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13426\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13426_BDD13427\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\)))) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000000110000010100000011111101011111001100000101111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1449~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1449~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13426_BDD13427\); + +-- Location: MLABCELL_X37_Y23_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13428\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(61) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13426_BDD13427\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(61) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13426_BDD13427\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011011101000000001101110100100010111111110010001011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]_NEW2607_RESYN13426_BDD13427\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\); + +-- Location: MLABCELL_X37_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_OTERM2608\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(61) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101110101010101001000101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_OTERM2608\); + +-- Location: FF_X37_Y23_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_OTERM2608\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE_q\); + +-- Location: LABCELL_X43_Y17_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[61]~feeder_combout\); + +-- Location: FF_X43_Y17_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(61)); + +-- Location: FF_X41_Y17_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(61)); + +-- Location: FF_X41_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(61)); + +-- Location: LABCELL_X41_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[61]~feeder_combout\); + +-- Location: FF_X41_Y17_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(61)); + +-- Location: LABCELL_X41_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(61) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(61))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(61))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(61) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(61))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(61)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(61) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(61))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(61)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(61) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(61) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(61))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(61)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010101000110100001111110110000101101011011101010111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(61), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(61), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~0_combout\); + +-- Location: FF_X41_Y20_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(61)); + +-- Location: LABCELL_X39_Y20_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[61]~feeder_combout\); + +-- Location: FF_X39_Y20_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(61)); + +-- Location: LABCELL_X40_Y23_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[61]~feeder_combout\); + +-- Location: FF_X40_Y23_N28 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(61)); + +-- Location: FF_X41_Y20_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(61)); + +-- Location: LABCELL_X41_Y20_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(61)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(61) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(61)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(61) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(61))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(61)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(61) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(61))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(61)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(61), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(61), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(61), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~1_combout\); + +-- Location: MLABCELL_X37_Y17_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux96~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux96~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~2_combout\); + +-- Location: FF_X37_Y17_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(61)); + +-- Location: MLABCELL_X37_Y29_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010000000001010101001010101111111110101010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3_combout\); + +-- Location: MLABCELL_X37_Y29_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2_combout\); + +-- Location: MLABCELL_X37_Y29_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1_combout\); + +-- Location: MLABCELL_X37_Y29_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001000100010001001110111011101110111011101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\); + +-- Location: MLABCELL_X37_Y29_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13430\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000010101010001001110010011101010101111111110010011100100111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\); + +-- Location: FF_X31_Y34_N41 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_OTERM2610\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]~DUPLICATE_q\); + +-- Location: LABCELL_X31_Y34_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13432\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000000011100110110101111101011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\); + +-- Location: LABCELL_X31_Y34_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_OTERM2610\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000110011101100110000110001001100111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_OTERM2610\); + +-- Location: FF_X31_Y34_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_OTERM2610\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61)); + +-- Location: LABCELL_X40_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[61]~feeder_combout\); + +-- Location: FF_X40_Y17_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(61)); + +-- Location: LABCELL_X41_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[61]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[61]~feeder_combout\); + +-- Location: FF_X41_Y17_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(61)); + +-- Location: FF_X41_Y17_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(61)); + +-- Location: LABCELL_X41_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[61]~feeder_combout\); + +-- Location: FF_X41_Y17_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(61)); + +-- Location: LABCELL_X41_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(61) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(61))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(61))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(61) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(61) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(61) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(61) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(61) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(61))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(61) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(61) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(61))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(61)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001000111001100110100011111001100010001111111111101000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(61), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(61), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~0_combout\); + +-- Location: LABCELL_X40_Y15_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[61]~feeder_combout\); + +-- Location: FF_X40_Y15_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(61)); + +-- Location: FF_X37_Y17_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(61)); + +-- Location: FF_X37_Y17_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(61)); + +-- Location: MLABCELL_X45_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[61]~feeder_combout\); + +-- Location: FF_X45_Y15_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(61)); + +-- Location: MLABCELL_X37_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(61) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(61) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(61))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(61) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(61) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(61) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(61) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(61)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(61) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(61))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001110100000000000111010011001100011101110011000001110111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(61), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(61), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~1_combout\); + +-- Location: MLABCELL_X37_Y17_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010110101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux160~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux160~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~2_combout\); + +-- Location: FF_X37_Y17_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(61)); + +-- Location: LABCELL_X41_Y30_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011000011110000111100000000111111110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~5_combout\); + +-- Location: MLABCELL_X37_Y29_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101001100110000000000001111010101010011001111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~6_combout\); + +-- Location: MLABCELL_X45_Y30_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111111111110000111101010101001100110101010100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~6_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~7_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~5_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~4_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~1_combout\); + +-- Location: MLABCELL_X45_Y30_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~12_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~14_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~13_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~15_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~3_combout\); + +-- Location: MLABCELL_X45_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~11_combout\ ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~10_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~9_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~8_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000000001111111101010101010101010011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~10_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~8_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~9_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~2_combout\); + +-- Location: MLABCELL_X45_Y30_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111101010101000011110101010100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~3_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~0_combout\); + +-- Location: LABCELL_X44_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~3_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~1_combout\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000011101110011000001110100110011000111011111111100011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~1_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~2_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~4_combout\); + +-- Location: LABCELL_X40_Y29_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13434\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13434_BDD13435\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~4_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~4_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000001010000010111110011111100111111010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~5_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~6_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~4_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13434_BDD13435\); + +-- Location: FF_X40_Y29_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_OTERM2613\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(61)); + +-- Location: LABCELL_X40_Y29_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13436\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(61) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13434_BDD13435\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(61) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13434_BDD13435\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011110101000000001111010100001010111111110000101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]_NEW2612_RESYN13434_BDD13435\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\); + +-- Location: LABCELL_X40_Y29_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_OTERM2613\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(61) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(61) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000010001110111111101110100010001000100011101110111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_OTERM2613\); + +-- Location: FF_X40_Y29_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_OTERM2613\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE_q\); + +-- Location: FF_X43_Y20_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(61)); + +-- Location: FF_X45_Y20_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(61)); + +-- Location: FF_X43_Y20_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(61)); + +-- Location: MLABCELL_X45_Y19_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[61]~feeder_combout\); + +-- Location: FF_X45_Y19_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(61)); + +-- Location: LABCELL_X43_Y20_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(61) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(61))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(61))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(61) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(61) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(61)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(61) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(61) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(61)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(61))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(61) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(61))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(61)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000001110000001010100111101000100101011101010010111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(61), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(61), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~0_combout\); + +-- Location: LABCELL_X48_Y15_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[61]~feeder_combout\); + +-- Location: FF_X48_Y15_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(61)); + +-- Location: LABCELL_X41_Y25_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[61]~feeder_combout\); + +-- Location: FF_X41_Y25_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(61)); + +-- Location: FF_X48_Y15_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE_q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(61)); + +-- Location: LABCELL_X44_Y13_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[61]~feeder_combout\); + +-- Location: FF_X44_Y13_N46 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(61)); + +-- Location: LABCELL_X48_Y15_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(61) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(61) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(61))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(61) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(61))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(61) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(61))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100000011000111011100111111010001000011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(61), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(61), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~1_combout\); + +-- Location: MLABCELL_X37_Y17_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~1_combout\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010110101111000001011010111100000101101011110000010110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux224~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux224~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~2_combout\); + +-- Location: FF_X37_Y17_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(61)); + +-- Location: LABCELL_X26_Y17_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[29]~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~44_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[29]~feeder_combout\); + +-- Location: FF_X26_Y17_N13 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[29]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(29)); + +-- Location: MLABCELL_X34_Y25_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~1_RTM0280\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~1_RTM0280_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & ( +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(29))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(29))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(29)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111010101010101111100110011001111110111011101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~1_RTM0280_combout\); + +-- Location: FF_X34_Y25_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_NEW_REG278\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~1_RTM0280_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM279\); + +-- Location: MLABCELL_X37_Y29_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001000110000100110101011110001010110011101001101111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~0_combout\); + +-- Location: FF_X34_Y25_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_NEW_REG276\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM277\); + +-- Location: LABCELL_X32_Y25_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275~feeder_combout\); + +-- Location: FF_X32_Y25_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_NEW_REG274\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275\); + +-- Location: MLABCELL_X34_Y25_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM277\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM279\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM279\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM277\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM279\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM279\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010111110101111101110111011101110111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM279\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM227\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM277\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM225\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM275\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\); + +-- Location: LABCELL_X36_Y19_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1385~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[61]~feeder_combout\); + +-- Location: FF_X36_Y19_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(61)); + +-- Location: LABCELL_X36_Y19_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1385~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[61]~feeder_combout\); + +-- Location: FF_X36_Y19_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(61)); + +-- Location: FF_X36_Y19_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(61)); + +-- Location: LABCELL_X36_Y15_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[61]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[61]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1385~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[61]~feeder_combout\); + +-- Location: FF_X36_Y15_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[61]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(61)); + +-- Location: LABCELL_X36_Y19_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(61) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(61)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(61)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(61) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(61))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(61)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(61) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(61) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(61))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(61))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(61) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(61) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(61))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011010001010110011110001001101010111100110111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(61), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(61), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~0_combout\); + +-- Location: FF_X36_Y21_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(61)); + +-- Location: FF_X37_Y17_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(61)); + +-- Location: FF_X37_Y17_N20 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(61)); + +-- Location: FF_X36_Y21_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(61)); + +-- Location: MLABCELL_X37_Y17_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(61) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(61) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(61))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(61) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(61))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(61) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(61) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(61)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(61))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110001000100000011000111011100111111010001000011111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(61), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(61), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(61), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~1_combout\); + +-- Location: MLABCELL_X37_Y17_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000001010101000000000101010110101010111111111010101011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux32~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux32~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~2_combout\); + +-- Location: FF_X37_Y17_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[61]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(61)); + +-- Location: MLABCELL_X37_Y17_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(61) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(61) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(61) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(61) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111010101010101010100001111000011110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(61), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(61), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(61), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(61), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~0_combout\); + +-- Location: MLABCELL_X37_Y10_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(5)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(5) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(5))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(5))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(5) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(29)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(5))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010011000100000001111100011100110100111101000011011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(5), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~11_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~10_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(29), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector47~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~1_combout\); + +-- Location: LABCELL_X39_Y10_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~14_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~13_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~14_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~13_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101000000000101010100000000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~14_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~9_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~13_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector47~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~15_combout\); + +-- Location: LABCELL_X40_Y10_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(61) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~15_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(61) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~15_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(61) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~15_combout\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101000001010000111111111111111100000000000000001010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~3_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~15_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~16_combout\); + +-- Location: FF_X40_Y10_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~16_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE_q\); + +-- Location: FF_X36_Y10_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~36_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~DUPLICATE_q\); + +-- Location: LABCELL_X40_Y10_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE_q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000001010000010100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~7_combout\); + +-- Location: LABCELL_X40_Y10_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~7_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~7_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~112_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101001101010101010100110101010101011111010101010101111101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(62), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~112_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~3_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~7_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~8_combout\); + +-- Location: FF_X40_Y10_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~8_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62)); + +-- Location: LABCELL_X24_Y15_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[31]_NEW2164\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[31]_OTERM2165\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(31))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(31))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(31), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(31), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[31]_OTERM2165\); + +-- Location: FF_X24_Y15_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[31]_OTERM2165\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31)); + +-- Location: FF_X24_Y12_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(31)); + +-- Location: FF_X25_Y12_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(31)); + +-- Location: FF_X26_Y12_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(31)); + +-- Location: LABCELL_X24_Y12_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[31]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[31]~feeder_combout\); + +-- Location: FF_X24_Y12_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(31)); + +-- Location: LABCELL_X26_Y12_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(31) & ( +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(31) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(31))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(31) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(31))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(31) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(31))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000100010000010100111011101011111001000100101111101110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(31), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~1_combout\); + +-- Location: FF_X25_Y12_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(31)); + +-- Location: FF_X26_Y10_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(31)); + +-- Location: FF_X26_Y10_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(31)); + +-- Location: FF_X26_Y10_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(31)); + +-- Location: LABCELL_X26_Y10_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(31) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(31))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(31)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(31))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(31) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(31) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(31) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(31)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(31) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(31) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(31) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000010001010111110001000100001010101110110101111110111011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(31), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~0_combout\); + +-- Location: LABCELL_X29_Y10_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111100001111000000001111000011111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux346~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux346~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~2_combout\); + +-- Location: FF_X29_Y10_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(31)); + +-- Location: LABCELL_X25_Y30_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~22_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~20_combout\))))) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~27_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\ +-- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~21_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0100011001000110010001100101011101010111010101110100011001010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~23_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~27_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~21_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~20_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~22_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_combout\); + +-- Location: LABCELL_X31_Y29_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]_NEW2267\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]_OTERM2268\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]_OTERM2268\); + +-- Location: FF_X31_Y29_N10 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]_OTERM2268\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7)); + +-- Location: LABCELL_X35_Y9_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~feeder_combout\); + +-- Location: FF_X35_Y9_N29 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(7)); + +-- Location: MLABCELL_X34_Y9_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~feeder_combout\); + +-- Location: FF_X34_Y9_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(7)); + +-- Location: FF_X34_Y9_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(7)); + +-- Location: FF_X34_Y9_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(7)); + +-- Location: MLABCELL_X34_Y9_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(7)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(7))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(7) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(7)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(7) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(7))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001001010010000001110101011110100010111100101010011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(7), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~1_combout\); + +-- Location: FF_X37_Y9_N55 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(7)); + +-- Location: FF_X37_Y9_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(7)); + +-- Location: FF_X37_Y9_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(7)); + +-- Location: LABCELL_X36_Y9_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~feeder_combout\); + +-- Location: FF_X36_Y9_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(7)); + +-- Location: MLABCELL_X37_Y9_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(7) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(7))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(7))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(7) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(7))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(7)))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(7))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(7)))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(7) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(7)))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100000101000100011010111110111011000001011011101110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(7), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(7), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(7), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~0_combout\); + +-- Location: LABCELL_X39_Y10_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux286~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux286~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~2_combout\); + +-- Location: FF_X39_Y10_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(7)); + +-- Location: LABCELL_X24_Y17_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[31]_NEW2166\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[31]_OTERM2167\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(31) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(31))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(31) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(31))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111001101000000011100110100100011111011110010001111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[31]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[31]_OTERM2167\); + +-- Location: FF_X24_Y17_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[31]_OTERM2167\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(31)); + +-- Location: FF_X35_Y13_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(31)); + +-- Location: FF_X36_Y13_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(31)); + +-- Location: MLABCELL_X37_Y13_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[31]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(31) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[31]~feeder_combout\); + +-- Location: FF_X37_Y13_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(31)); + +-- Location: FF_X36_Y13_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(31)); + +-- Location: LABCELL_X36_Y13_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(31)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(31) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(31)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(31))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(31))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000110111011000100011011101100001010000010100101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(31), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(31), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~1_combout\); + +-- Location: LABCELL_X40_Y13_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[31]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(31) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[31]~feeder_combout\); + +-- Location: FF_X40_Y13_N49 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(31)); + +-- Location: FF_X42_Y13_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(31)); + +-- Location: MLABCELL_X37_Y13_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[31]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(31) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(31), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[31]~feeder_combout\); + +-- Location: FF_X37_Y13_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(31)); + +-- Location: FF_X37_Y13_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(31), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(31)); + +-- Location: MLABCELL_X37_Y13_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(31) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(31)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(31) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(31)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(31))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(31) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(31)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(31))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111011101000100011101110100000011000000111100111111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(31), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(31), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(31), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~0_combout\); + +-- Location: LABCELL_X36_Y13_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux378~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux378~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~2_combout\); + +-- Location: FF_X36_Y13_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(31)); + +-- Location: FF_X32_Y25_N1 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_NEW_REG368\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM369\); + +-- Location: LABCELL_X32_Y23_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ +-- & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000000000000010000000000001001100000000000100110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~0_combout\); + +-- Location: LABCELL_X32_Y23_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000001111000001000000111100001100000011110000110000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1383~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~1_combout\); + +-- Location: FF_X32_Y23_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_NEW_REG372\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM373\); + +-- Location: FF_X32_Y23_N26 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_NEW_REG366\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM367\); + +-- Location: MLABCELL_X28_Y17_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~50_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~feeder_combout\); + +-- Location: FF_X28_Y17_N43 +\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(31)); + +-- Location: FF_X32_Y23_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_NEW_REG370\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(31), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM371\); + +-- Location: LABCELL_X32_Y23_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM367\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM371\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM373\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM369\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM347\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM367\ & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM371\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM373\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM347\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM367\ +-- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM371\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM347\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM369\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM373\) +-- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM367\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM371\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM373\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111001011110010111101011111010111110111111101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM347\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM369\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM373\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM367\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM371\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\); + +-- Location: FF_X36_Y12_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(63)); + +-- Location: FF_X39_Y12_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(63)); + +-- Location: FF_X36_Y12_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(63)); + +-- Location: FF_X39_Y12_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(63)); + +-- Location: LABCELL_X39_Y12_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(63) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(63)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(63) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(63)) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(63) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(63))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(63)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(63) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(63))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(63)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100010001110111010001000111011100001100000011000011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(63), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(63), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(63), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(63), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~1_combout\); + +-- Location: LABCELL_X41_Y14_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[63]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[63]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1383~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[63]~feeder_combout\); + +-- Location: FF_X41_Y14_N58 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[63]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(63)); + +-- Location: LABCELL_X40_Y14_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[63]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[63]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1383~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[63]~feeder_combout\); + +-- Location: FF_X40_Y14_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[63]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(63)); + +-- Location: FF_X41_Y14_N14 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\, + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(63)); + +-- Location: LABCELL_X40_Y14_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[63]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[63]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(63) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(63) & ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(63) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111111111100000000001100111111111100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1383~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Decoder0~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(63), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[63]~1_combout\); + +-- Location: FF_X40_Y14_N19 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[63]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(63)); + +-- Location: LABCELL_X41_Y14_N12 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(63) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(63) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(63)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(63)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(63) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(63) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(63))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(63)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(63) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(63) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(63)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(63) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(63) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(63) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(63))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(63) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111000001000011011100110100110001111100010011110111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(63), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(63), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(63), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(63), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~0_combout\); + +-- Location: MLABCELL_X45_Y14_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~1_combout\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101000001010000010100000101001011111010111110101111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux30~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux30~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~2_combout\); + +-- Location: FF_X45_Y14_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(63)); + +-- Location: LABCELL_X35_Y23_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[63]_NEW2621\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[63]_OTERM2622\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\) # +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)))) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63) & +-- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\)) ) ) ) +-- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & (\myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100000001111100011111000100001101000000011111110111110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[62]~1_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(63), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[63]_OTERM2622\); + +-- Location: FF_X35_Y23_N52 +\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[63]_OTERM2622\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63)); + +-- Location: LABCELL_X47_Y16_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[63]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[63]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(63), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[63]~feeder_combout\); + +-- Location: FF_X47_Y16_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[63]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(63)); + +-- Location: LABCELL_X44_Y13_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[63]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[63]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(63), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[63]~feeder_combout\); + +-- Location: FF_X44_Y13_N34 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[63]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(63)); + +-- Location: FF_X47_Y16_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(63)); + +-- Location: LABCELL_X47_Y16_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[63]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[63]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(63), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[63]~feeder_combout\); + +-- Location: FF_X47_Y16_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[63]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(63)); + +-- Location: LABCELL_X47_Y16_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(63) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(63) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(63))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(63)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(63) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(63) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(63))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(63) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(63) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(63) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(63) & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(63)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(63) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(63) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(63) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(63) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1))))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010000100010101111110111011000010101011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(63), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(63), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(63), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(63), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~1_combout\); + +-- Location: LABCELL_X40_Y14_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[63]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[63]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(63), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[63]~feeder_combout\); + +-- Location: FF_X40_Y14_N4 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[63]~feeder_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(63)); + +-- Location: LABCELL_X40_Y14_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[63]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[63]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(63)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(63) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Decoder0~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(63), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(63), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[63]~0_combout\); + +-- Location: FF_X40_Y14_N59 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[63]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(63)); + +-- Location: FF_X45_Y14_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(63)); + +-- Location: FF_X45_Y14_N50 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63), + sload => VCC, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(63)); + +-- Location: MLABCELL_X45_Y14_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(63) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(63))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(63)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(63) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(63))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(63)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(63) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(63)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(63) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(63) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010100000000010101011111111100110011000011110011001100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(63), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(63), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(63), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(63), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~0_combout\); + +-- Location: MLABCELL_X45_Y14_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~0_combout\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010101001010101010101011111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux94~1_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux94~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~2_combout\); + +-- Location: FF_X45_Y14_N11 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(63)); + +-- Location: MLABCELL_X45_Y14_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector45~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector45~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(63) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(63)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(63) & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(63))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011000000000000001100000000001100110011000000110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(63), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(63), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector45~0_combout\); + +-- Location: LABCELL_X39_Y10_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~108\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~108_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector45~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\)))))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(7))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\ & ( +-- (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(31)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000010100000101000011110000111111110101001101010000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(7), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DECODED_OPCODE~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector45~0_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~108_combout\); + +-- Location: LABCELL_X39_Y10_N48 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~104\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~104_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~108_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\)))) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(55))))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~q\ & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(31) & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(55))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000000011011000000000001101100000000000100010000000000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(55), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(31), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~4_combout\, + datag => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~108_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~104_combout\); + +-- Location: LABCELL_X40_Y10_N24 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(59) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(59) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011110011110000001111001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(62), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(59), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~17_combout\); + +-- Location: LABCELL_X40_Y10_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~17_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~17_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~104_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ & +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000010111111000100001011111101010000111111110101000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~104_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~3_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(63), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~17_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~18_combout\); + +-- Location: FF_X40_Y10_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~18_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63)); + +-- Location: LABCELL_X40_Y10_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan3~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(62), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(63), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan3~0_combout\); + +-- Location: FF_X36_Y10_N37 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~26_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~DUPLICATE_q\); + +-- Location: LABCELL_X40_Y10_N27 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~0_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~DUPLICATE_q\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010111000000110101011100000011010101110000001101010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(63), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~0_combout\); + +-- Location: LABCELL_X40_Y10_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan3~0_combout\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(60))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000011111001011110001111100101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan3~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector121~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~1_combout\); + +-- Location: LABCELL_X41_Y10_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~1_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~1_combout\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111110111111001111111011111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector114~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTCRLF~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_PRECR~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(0), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector121~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~2_combout\); + +-- Location: FF_X41_Y10_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(0)); + +-- Location: FF_X43_Y9_N16 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~29_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(6)); + +-- Location: LABCELL_X40_Y10_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(60)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62) & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63) & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(60))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000000011110000111111111111000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(62), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(63), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~0_combout\); + +-- Location: LABCELL_X40_Y10_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(57)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000010101010000111101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector120~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(57), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~1_combout\); + +-- Location: LABCELL_X41_Y10_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\ & ( +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~58_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~1_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111110111111001111111011111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector114~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector120~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~58_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(1), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SEPERATOR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~2_combout\); + +-- Location: FF_X41_Y10_N53 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(1)); + +-- Location: M10K_X38_Y8_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + logical_ram_name => "zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|zpu_uart_debug:\DEBUG:DEBUGUART|altsyncram:TX_FIFO_rtl_0|altsyncram_o6q1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 12, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 2, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 4095, + port_a_logical_ram_depth => 4096, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 12, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 2, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 4095, + port_b_logical_ram_depth => 4096, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO~21_combout\, + portbre => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA[0]~0_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X41_Y8_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~feeder_combout\); + +-- Location: LABCELL_X41_Y8_N39 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[1]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a1\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[1]~feeder_combout\); + +-- Location: LABCELL_X40_Y10_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(60))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001010001010101010101000101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(63), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(60), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(62), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~0_combout\); + +-- Location: LABCELL_X40_Y10_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001111110011001100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector119~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~1_combout\); + +-- Location: LABCELL_X41_Y10_N42 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\ ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(2) & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111111111111101111111111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector114~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector119~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_PRECR~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTCRLF~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(2), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SEPERATOR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~2_combout\); + +-- Location: FF_X41_Y10_N44 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~2_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(2)); + +-- Location: LABCELL_X41_Y10_N57 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~58_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SEPERATOR~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTCRLF~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_PRECR~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~58_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~2_combout\); + +-- Location: LABCELL_X40_Y10_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE_q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000110000000000000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(62), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(63), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~0_combout\); + +-- Location: LABCELL_X40_Y10_N9 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(59))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(59), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~1_combout\); + +-- Location: LABCELL_X41_Y10_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~1_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(3))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011111010111100001111101011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector114~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~2_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(3), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~1_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~3_combout\); + +-- Location: FF_X41_Y10_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~3_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(3)); + +-- Location: M10K_X38_Y9_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + logical_ram_name => "zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|zpu_uart_debug:\DEBUG:DEBUGUART|altsyncram:TX_FIFO_rtl_0|altsyncram_o6q1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 12, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 2, + port_a_first_address => 0, + port_a_first_bit_number => 2, + port_a_last_address => 4095, + port_a_logical_ram_depth => 4096, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 12, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 2, + port_b_first_address => 0, + port_b_first_bit_number => 2, + port_b_last_address => 4095, + port_b_logical_ram_depth => 4096, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO~21_combout\, + portbre => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA[0]~0_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X41_Y8_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[2]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2~portbdataout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[2]~feeder_combout\); + +-- Location: LABCELL_X41_Y8_N3 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[3]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a3\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[3]~feeder_combout\); + +-- Location: LABCELL_X40_Y10_N18 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(60) & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan3~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(60) & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan3~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100100011111010110010001111101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(60), + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan3~0_combout\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~0_combout\); + +-- Location: MLABCELL_X42_Y10_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18~combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18~combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000111111111010101011110000111100001111101111111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_WideOr18~combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector117~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(4), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~1_combout\); + +-- Location: FF_X42_Y10_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~1_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(4)); + +-- Location: FF_X41_Y10_N7 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~55_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~DUPLICATE_q\); + +-- Location: MLABCELL_X42_Y10_N45 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SPACE~q\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~57_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~DUPLICATE_q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000000000110000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SPACE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~57_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_SPLITSPACE~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SEPERATOR~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~1_combout\); + +-- Location: MLABCELL_X42_Y10_N36 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ & +-- ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(61)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011000000111100001100000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(61), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~0_combout\); + +-- Location: MLABCELL_X42_Y10_N51 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18~combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18~combout\ & +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000000000000010000000000000001100000000000000110000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_WideOr18~combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~2_combout\); + +-- Location: MLABCELL_X42_Y10_N6 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~1_combout\) # +-- ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~2_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~1_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~0_combout\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(5))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110011111111110111001111111111011100110111001101110011011100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~1_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(5), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~2_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~3_combout\); + +-- Location: FF_X42_Y10_N8 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~3_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(5)); + +-- Location: M10K_X46_Y8_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + logical_ram_name => "zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|zpu_uart_debug:\DEBUG:DEBUGUART|altsyncram:TX_FIFO_rtl_0|altsyncram_o6q1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 12, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 2, + port_a_first_address => 0, + port_a_first_bit_number => 4, + port_a_last_address => 4095, + port_a_logical_ram_depth => 4096, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 12, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 2, + port_b_first_address => 0, + port_b_first_bit_number => 4, + port_b_last_address => 4095, + port_b_logical_ram_depth => 4096, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO~21_combout\, + portbre => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA[0]~0_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X41_Y8_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[4]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4~portbdataout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[4]~feeder_combout\); + +-- Location: LABCELL_X41_Y8_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[5]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a5\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[5]~feeder_combout\); + +-- Location: LABCELL_X40_Y10_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan3~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62) & ( +-- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan3~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000100011111000111110001111100011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan3~0_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(62), + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~0_combout\); + +-- Location: MLABCELL_X42_Y10_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(6))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(6)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110001010101110111010101010111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector114~0_combout\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(6), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector115~0_combout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~1_combout\); + +-- Location: FF_X42_Y10_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~1_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(6)); + +-- Location: FF_X43_Y9_N22 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~21_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(8)); + +-- Location: FF_X43_Y9_N25 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~37_sumout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(9)); + +-- Location: MLABCELL_X42_Y10_N33 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ & +-- (((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63)))) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(7)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011001100000000001100110000000101110011010000010111001101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector114~0_combout\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(63), + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(7), + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~1_combout\); + +-- Location: FF_X42_Y10_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~1_combout\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(7)); + +-- Location: M10K_X46_Y9_N0 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + logical_ram_name => "zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|zpu_uart_debug:\DEBUG:DEBUGUART|altsyncram:TX_FIFO_rtl_0|altsyncram_o6q1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 12, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 2, + port_a_first_address => 0, + port_a_first_bit_number => 6, + port_a_last_address => 4095, + port_a_logical_ram_depth => 4096, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 12, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 2, + port_b_first_address => 0, + port_b_first_bit_number => 6, + port_b_last_address => 4095, + port_b_logical_ram_depth => 4096, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO~21_combout\, + portbre => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA[0]~0_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X41_Y8_N30 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[6]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6~portbdataout\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[6]~feeder_combout\); + +-- Location: LABCELL_X41_Y8_N15 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[7]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a7\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[7]~feeder_combout\); + +-- Location: FF_X41_Y8_N17 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[7]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(8), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(7)); + +-- Location: FF_X41_Y8_N32 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[6]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(7), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(6)); + +-- Location: FF_X41_Y8_N35 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[5]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(6), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(5)); + +-- Location: FF_X41_Y8_N2 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[4]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(5), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(4)); + +-- Location: FF_X41_Y8_N5 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[3]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(4), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(3)); + +-- Location: FF_X41_Y8_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[2]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(3), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(2)); + +-- Location: FF_X41_Y8_N40 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[1]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(2), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(1)); + +-- Location: FF_X41_Y8_N38 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~feeder_combout\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(1), + sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\, + ena => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(0)); + +-- Location: LABCELL_X40_Y8_N54 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(0)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~q\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(0) +-- & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\ & ( +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(0)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~q\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~q\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001100111111111111110011110000111111001111111111111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(0), + datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_CLOCK~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TXD~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_DATA_LOADED~q\, + combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~0_combout\); + +-- Location: FF_X40_Y8_N56 +\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~q\); + +-- Location: LABCELL_X5_Y8_N12 +\myVirtualToplevel|UART0|TX_BUFFER[7]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER[7]~feeder_combout\ = \myVirtualToplevel|UART0|TX_BUFFER\(8) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(8), + combout => \myVirtualToplevel|UART0|TX_BUFFER[7]~feeder_combout\); + +-- Location: MLABCELL_X9_Y8_N36 +\myVirtualToplevel|UART0|TX_DATA[0]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA[0]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( \myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ((!\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ & +-- (!\myVirtualToplevel|UART0|Equal5~3_combout\)) # (\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ & ((\myVirtualToplevel|UART1|Equal7~0_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( \myVirtualToplevel|UART0_CS~combout\ & ( +-- (!\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & (!\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ & !\myVirtualToplevel|UART0|Equal5~3_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( !\myVirtualToplevel|UART0_CS~combout\ & ( +-- (!\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & (!\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ & !\myVirtualToplevel|UART0|Equal5~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( !\myVirtualToplevel|UART0_CS~combout\ & ( +-- (!\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & (!\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ & !\myVirtualToplevel|UART0|Equal5~3_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000010000000100000001000000010000000100000001000000010100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_Equal5~3_combout\, + datad => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\, + combout => \myVirtualToplevel|UART0|TX_DATA[0]~4_combout\); + +-- Location: LABCELL_X10_Y8_N27 +\myVirtualToplevel|UART0|TX_FIFO~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO~33_combout\ = ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & +-- !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(3), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(4), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\, + combout => \myVirtualToplevel|UART0|TX_FIFO~33_combout\); + +-- Location: LABCELL_X12_Y9_N42 +\myVirtualToplevel|UART0|TX_FIFO~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO~31_combout\ = ( !\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ & ( \myVirtualToplevel|UART0|TX_RESET~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_RESET~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\, + combout => \myVirtualToplevel|UART0|TX_FIFO~31_combout\); + +-- Location: LABCELL_X12_Y8_N18 +\myVirtualToplevel|UART0|Equal6~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal6~4_combout\ = ( \myVirtualToplevel|UART0|Add6~5_sumout\ & ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7) ) ) # ( !\myVirtualToplevel|UART0|Add6~5_sumout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001111001100110011001100110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(7), + dataf => \myVirtualToplevel|UART0|ALT_INV_Add6~5_sumout\, + combout => \myVirtualToplevel|UART0|Equal6~4_combout\); + +-- Location: LABCELL_X12_Y8_N21 +\myVirtualToplevel|UART0|Equal6~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|Equal6~3_combout\ = ( \myVirtualToplevel|UART0|Add6~1_sumout\ & ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) ) ) # ( !\myVirtualToplevel|UART0|Add6~1_sumout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111111110000111100001111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(6), + dataf => \myVirtualToplevel|UART0|ALT_INV_Add6~1_sumout\, + combout => \myVirtualToplevel|UART0|Equal6~3_combout\); + +-- Location: LABCELL_X12_Y8_N6 +\myVirtualToplevel|UART0|TX_FIFO~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO~32_combout\ = ( \myVirtualToplevel|UART0|Equal6~3_combout\ & ( \myVirtualToplevel|UART0|Equal6~0_combout\ & ( (\myVirtualToplevel|UART0|TX_FIFO~31_combout\ & \myVirtualToplevel|UART0|TX_OVERRUN~1_combout\) ) ) ) # ( +-- !\myVirtualToplevel|UART0|Equal6~3_combout\ & ( \myVirtualToplevel|UART0|Equal6~0_combout\ & ( (\myVirtualToplevel|UART0|TX_FIFO~31_combout\ & (\myVirtualToplevel|UART0|TX_OVERRUN~1_combout\ & ((!\myVirtualToplevel|UART0|Equal6~1_combout\) # +-- (\myVirtualToplevel|UART0|Equal6~4_combout\)))) ) ) ) # ( \myVirtualToplevel|UART0|Equal6~3_combout\ & ( !\myVirtualToplevel|UART0|Equal6~0_combout\ & ( (\myVirtualToplevel|UART0|TX_FIFO~31_combout\ & \myVirtualToplevel|UART0|TX_OVERRUN~1_combout\) ) ) ) +-- # ( !\myVirtualToplevel|UART0|Equal6~3_combout\ & ( !\myVirtualToplevel|UART0|Equal6~0_combout\ & ( (\myVirtualToplevel|UART0|TX_FIFO~31_combout\ & \myVirtualToplevel|UART0|TX_OVERRUN~1_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001100000000001000110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Equal6~1_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~31_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_Equal6~4_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~1_combout\, + datae => \myVirtualToplevel|UART0|ALT_INV_Equal6~3_combout\, + dataf => \myVirtualToplevel|UART0|ALT_INV_Equal6~0_combout\, + combout => \myVirtualToplevel|UART0|TX_FIFO~32_combout\); + +-- Location: LABCELL_X12_Y8_N12 +\myVirtualToplevel|UART0|TX_FIFO~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO~34_combout\ = ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & ( \myVirtualToplevel|UART0|TX_FIFO~32_combout\ & ( (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) & +-- (\myVirtualToplevel|UART0|TX_FIFO~33_combout\ & !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(0), + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(6), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~33_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(7), + datae => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(1), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~32_combout\, + combout => \myVirtualToplevel|UART0|TX_FIFO~34_combout\); + +-- Location: FF_X6_Y8_N31 +\myVirtualToplevel|UART0|TX_FIFO~25\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO~25_q\); + +-- Location: FF_X6_Y8_N14 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(24)); + +-- Location: MLABCELL_X9_Y8_N6 +\myVirtualToplevel|UART0|TX_FIFO~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO~35_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\ ) # ( !\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\ & ( \myVirtualToplevel|UART0|TX_FIFO~17_q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~17_q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR[0]~0_combout\, + combout => \myVirtualToplevel|UART0|TX_FIFO~35_combout\); + +-- Location: FF_X9_Y8_N7 +\myVirtualToplevel|UART0|TX_FIFO~17\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_FIFO~35_combout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO~17_q\); + +-- Location: FF_X9_Y8_N16 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(15)); + +-- Location: FF_X9_Y8_N41 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(11)); + +-- Location: FF_X9_Y8_N50 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(13)); + +-- Location: FF_X9_Y8_N32 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add8~1_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(14)); + +-- Location: FF_X10_Y8_N55 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add8~29_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(12)); + +-- Location: MLABCELL_X9_Y8_N30 +\myVirtualToplevel|UART0|TX_FIFO~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO~26_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(12) & ( (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(11) & (!\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(13) $ +-- (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(14)))) ) ) # ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(12) & ( (!\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(11) & (!\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(13) $ +-- (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(14)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000000001100110000000000110000110000000000110011000000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(11), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(13), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(14), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(12), + combout => \myVirtualToplevel|UART0|TX_FIFO~26_combout\); + +-- Location: FF_X10_Y8_N8 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add8~5_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(16)); + +-- Location: FF_X10_Y8_N13 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(5)); + +-- Location: FF_X10_Y8_N5 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add8~17_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(6)); + +-- Location: FF_X10_Y8_N20 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add8~21_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(8)); + +-- Location: FF_X12_Y8_N59 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(7)); + +-- Location: LABCELL_X10_Y8_N18 +\myVirtualToplevel|UART0|TX_FIFO~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO~28_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(8) & ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(7) & ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(5) $ +-- (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(6)) ) ) ) # ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(8) & ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(7) & ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(5) $ +-- (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(6)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100001111000011000000000000000000000000000000001100001111000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(5), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(6), + datae => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(8), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(7), + combout => \myVirtualToplevel|UART0|TX_FIFO~28_combout\); + +-- Location: FF_X12_Y8_N28 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(3)); + +-- Location: FF_X10_Y8_N59 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add8~9_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(2)); + +-- Location: FF_X10_Y8_N23 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add8~13_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(4)); + +-- Location: FF_X10_Y8_N17 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(1)); + +-- Location: FF_X12_Y8_N4 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|TX_FIFO~32_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(0)); + +-- Location: LABCELL_X10_Y8_N12 +\myVirtualToplevel|UART0|TX_FIFO~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO~27_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(0) & ( (!\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(3) & (!\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(4) & +-- (!\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(2) $ (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(1))))) # (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(3) & (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(4) & +-- (!\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(2) $ (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(1))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000100001000011000010000100001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(3), + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(2), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(4), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(1), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(0), + combout => \myVirtualToplevel|UART0|TX_FIFO~27_combout\); + +-- Location: FF_X10_Y8_N11 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|Add8~25_sumout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(10)); + +-- Location: FF_X12_Y8_N10 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(9)); + +-- Location: LABCELL_X10_Y8_N9 +\myVirtualToplevel|UART0|TX_FIFO~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO~29_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(9) & ( (\myVirtualToplevel|UART0|TX_FIFO~28_combout\ & (\myVirtualToplevel|UART0|TX_FIFO~27_combout\ & \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(10))) ) ) +-- # ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(9) & ( (\myVirtualToplevel|UART0|TX_FIFO~28_combout\ & (\myVirtualToplevel|UART0|TX_FIFO~27_combout\ & !\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(10))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000000000000000000001010000000000000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~28_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~27_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(10), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(9), + combout => \myVirtualToplevel|UART0|TX_FIFO~29_combout\); + +-- Location: LABCELL_X10_Y8_N6 +\myVirtualToplevel|UART0|TX_FIFO~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO~30_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO~29_combout\ & ( (\myVirtualToplevel|UART0|TX_FIFO~26_combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(15) $ (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(16)))) +-- ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001100000000110000110000000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(15), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~26_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(16), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~29_combout\, + combout => \myVirtualToplevel|UART0|TX_FIFO~30_combout\); + +-- Location: LABCELL_X6_Y8_N24 +\myVirtualToplevel|UART0|TX_DATA[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO~30_combout\ & ( (!\myVirtualToplevel|UART0|Equal5~3_combout\ & (!\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ & !\myVirtualToplevel|UART0|TX_DATA_LOADED~q\)) ) ) # ( +-- !\myVirtualToplevel|UART0|TX_FIFO~30_combout\ & ( (!\myVirtualToplevel|UART0|Equal5~3_combout\ & (\myVirtualToplevel|UART0|TX_FIFO~17_q\ & (!\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ & !\myVirtualToplevel|UART0|TX_DATA_LOADED~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000001000000000000010100000000000001010000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Equal5~3_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~17_q\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~30_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA[0]~1_combout\); + +-- Location: LABCELL_X6_Y8_N9 +\myVirtualToplevel|UART0|TX_DATA[0]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ = ( !\myVirtualToplevel|UART0|TX_FIFO~30_combout\ & ( (!\myVirtualToplevel|UART0|Equal5~3_combout\ & (!\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & !\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_Equal5~3_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~30_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA[0]~2_combout\); + +-- Location: M10K_X11_Y8_N0 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block +-- pragma translate_off +GENERIC MAP ( + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + logical_ram_name => "zpu_soc:myVirtualToplevel|uart:UART0|altsyncram:TX_FIFO_rtl_0|altsyncram_1jo1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 8, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 40, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 255, + port_a_logical_ram_depth => 256, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_no_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 8, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 40, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 255, + port_b_logical_ram_depth => 256, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_no_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M20K") +-- pragma translate_on +PORT MAP ( + portawe => \myVirtualToplevel|UART0|TX_FIFO~32_combout\, + portbre => VCC, + portbaddrstall => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR[0]~0_combout\, + clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + portadatain => \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: LABCELL_X6_Y8_N30 +\myVirtualToplevel|UART0|TX_DATA~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) & ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & +-- (((!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)) # (\myVirtualToplevel|UART0|TX_FIFO~25_q\))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\) # +-- (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(24))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) & ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & +-- (\myVirtualToplevel|UART0|TX_FIFO~25_q\ & ((\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\) # (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(24))))) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) & ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)) # +-- (\myVirtualToplevel|UART0|TX_FIFO~25_q\))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(24) & !\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) & ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (\myVirtualToplevel|UART0|TX_FIFO~25_q\ & +-- ((\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(24) & !\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001101010000111100110101000000000011010111111111001101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~25_q\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(24), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~1_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7), + dataf => \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\, + combout => \myVirtualToplevel|UART0|TX_DATA~18_combout\); + +-- Location: LABCELL_X5_Y8_N0 +\myVirtualToplevel|UART0|TX_DATA[7]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA[7]~19_combout\ = ( \myVirtualToplevel|UART0|TX_DATA~18_combout\ & ( ((\myVirtualToplevel|UART0|TX_DATA[0]~4_combout\ & \myVirtualToplevel|UART0|TX_DATA[0]~0_combout\)) # (\myVirtualToplevel|UART0|TX_DATA\(7)) ) ) # ( +-- !\myVirtualToplevel|UART0|TX_DATA~18_combout\ & ( (\myVirtualToplevel|UART0|TX_DATA\(7) & ((!\myVirtualToplevel|UART0|TX_DATA[0]~4_combout\) # (!\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~4_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~0_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA\(7), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA~18_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA[7]~19_combout\); + +-- Location: FF_X5_Y8_N2 +\myVirtualToplevel|UART0|TX_DATA[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_DATA[7]~19_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_DATA\(7)); + +-- Location: FF_X5_Y8_N14 +\myVirtualToplevel|UART0|TX_BUFFER[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER[7]~feeder_combout\, + asdata => \myVirtualToplevel|UART0|TX_DATA\(7), + sload => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(7)); + +-- Location: LABCELL_X5_Y8_N15 +\myVirtualToplevel|UART0|TX_BUFFER[6]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER[6]~feeder_combout\ = \myVirtualToplevel|UART0|TX_BUFFER\(7) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(7), + combout => \myVirtualToplevel|UART0|TX_BUFFER[6]~feeder_combout\); + +-- Location: FF_X6_Y8_N25 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(23)); + +-- Location: FF_X6_Y8_N56 +\myVirtualToplevel|UART0|TX_FIFO~24\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO~24_q\); + +-- Location: LABCELL_X6_Y8_N54 +\myVirtualToplevel|UART0|TX_DATA~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) & ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & +-- (((!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\) # (\myVirtualToplevel|UART0|TX_FIFO~24_q\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)) # +-- (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(23)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) & ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & +-- (((\myVirtualToplevel|UART0|TX_FIFO~24_q\ & \myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)) # (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(23)))) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) & ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\) # +-- (\myVirtualToplevel|UART0|TX_FIFO~24_q\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(23) & ((!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) & ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|TX_FIFO~24_q\ & +-- \myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(23) & ((!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010101110110000101000010001010111111011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~1_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(23), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~24_q\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6), + dataf => \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\, + combout => \myVirtualToplevel|UART0|TX_DATA~16_combout\); + +-- Location: LABCELL_X5_Y8_N3 +\myVirtualToplevel|UART0|TX_DATA[6]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA[6]~17_combout\ = ( \myVirtualToplevel|UART0|TX_DATA~16_combout\ & ( ((\myVirtualToplevel|UART0|TX_DATA[0]~4_combout\ & \myVirtualToplevel|UART0|TX_DATA[0]~0_combout\)) # (\myVirtualToplevel|UART0|TX_DATA\(6)) ) ) # ( +-- !\myVirtualToplevel|UART0|TX_DATA~16_combout\ & ( (\myVirtualToplevel|UART0|TX_DATA\(6) & ((!\myVirtualToplevel|UART0|TX_DATA[0]~4_combout\) # (!\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~4_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~0_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA\(6), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA~16_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA[6]~17_combout\); + +-- Location: FF_X5_Y8_N5 +\myVirtualToplevel|UART0|TX_DATA[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_DATA[6]~17_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_DATA\(6)); + +-- Location: FF_X5_Y8_N16 +\myVirtualToplevel|UART0|TX_BUFFER[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER[6]~feeder_combout\, + asdata => \myVirtualToplevel|UART0|TX_DATA\(6), + sload => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(6)); + +-- Location: LABCELL_X7_Y8_N27 +\myVirtualToplevel|UART0|TX_BUFFER[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER[5]~feeder_combout\ = \myVirtualToplevel|UART0|TX_BUFFER\(6) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(6), + combout => \myVirtualToplevel|UART0|TX_BUFFER[5]~feeder_combout\); + +-- Location: LABCELL_X6_Y8_N6 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[22]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + combout => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[22]~feeder_combout\); + +-- Location: FF_X6_Y8_N8 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[22]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(22)); + +-- Location: FF_X6_Y8_N2 +\myVirtualToplevel|UART0|TX_FIFO~23\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5), + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO~23_q\); + +-- Location: LABCELL_X6_Y8_N0 +\myVirtualToplevel|UART0|TX_DATA~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) & ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & +-- (((!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\) # (\myVirtualToplevel|UART0|TX_FIFO~23_q\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)) # +-- (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(22)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) & ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & +-- (((\myVirtualToplevel|UART0|TX_FIFO~23_q\ & \myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)) # (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(22)))) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) & ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\) # +-- (\myVirtualToplevel|UART0|TX_FIFO~23_q\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(22) & ((!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) & ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a5\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|TX_FIFO~23_q\ & +-- \myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(22) & ((!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100001010101110110000101000010001010111111011101101011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~1_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(22), + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~23_q\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5), + dataf => \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\, + combout => \myVirtualToplevel|UART0|TX_DATA~14_combout\); + +-- Location: LABCELL_X7_Y8_N45 +\myVirtualToplevel|UART0|TX_DATA[5]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA[5]~15_combout\ = ( \myVirtualToplevel|UART0|TX_DATA~14_combout\ & ( ((\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\ & \myVirtualToplevel|UART0|TX_DATA[0]~4_combout\)) # (\myVirtualToplevel|UART0|TX_DATA\(5)) ) ) # ( +-- !\myVirtualToplevel|UART0|TX_DATA~14_combout\ & ( (\myVirtualToplevel|UART0|TX_DATA\(5) & ((!\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\) # (!\myVirtualToplevel|UART0|TX_DATA[0]~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~0_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~4_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA\(5), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA~14_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA[5]~15_combout\); + +-- Location: FF_X7_Y8_N47 +\myVirtualToplevel|UART0|TX_DATA[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_DATA[5]~15_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_DATA\(5)); + +-- Location: FF_X7_Y8_N29 +\myVirtualToplevel|UART0|TX_BUFFER[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER[5]~feeder_combout\, + asdata => \myVirtualToplevel|UART0|TX_DATA\(5), + sload => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(5)); + +-- Location: LABCELL_X7_Y8_N24 +\myVirtualToplevel|UART0|TX_BUFFER[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER[4]~feeder_combout\ = \myVirtualToplevel|UART0|TX_BUFFER\(5) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(5), + combout => \myVirtualToplevel|UART0|TX_BUFFER[4]~feeder_combout\); + +-- Location: FF_X6_Y8_N20 +\myVirtualToplevel|UART0|TX_FIFO~22\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4), + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO~22_q\); + +-- Location: FF_X6_Y8_N28 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(21)); + +-- Location: LABCELL_X6_Y8_N18 +\myVirtualToplevel|UART0|TX_DATA~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( \myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & +-- ((\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(21)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a4\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( +-- \myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & ((\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(21)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & +-- (\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a4\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( !\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\) # +-- (\myVirtualToplevel|UART0|TX_FIFO~22_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( !\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & ( (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & \myVirtualToplevel|UART0|TX_FIFO~22_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011110011111100111100010001110111010001000111011101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~2_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~22_q\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(21), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~1_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA~12_combout\); + +-- Location: LABCELL_X7_Y8_N42 +\myVirtualToplevel|UART0|TX_DATA[4]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA[4]~13_combout\ = ( \myVirtualToplevel|UART0|TX_DATA~12_combout\ & ( ((\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\ & \myVirtualToplevel|UART0|TX_DATA[0]~4_combout\)) # (\myVirtualToplevel|UART0|TX_DATA\(4)) ) ) # ( +-- !\myVirtualToplevel|UART0|TX_DATA~12_combout\ & ( (\myVirtualToplevel|UART0|TX_DATA\(4) & ((!\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\) # (!\myVirtualToplevel|UART0|TX_DATA[0]~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~0_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~4_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA\(4), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA~12_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA[4]~13_combout\); + +-- Location: FF_X7_Y8_N44 +\myVirtualToplevel|UART0|TX_DATA[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_DATA[4]~13_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_DATA\(4)); + +-- Location: FF_X7_Y8_N26 +\myVirtualToplevel|UART0|TX_BUFFER[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER[4]~feeder_combout\, + asdata => \myVirtualToplevel|UART0|TX_DATA\(4), + sload => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(4)); + +-- Location: LABCELL_X7_Y8_N33 +\myVirtualToplevel|UART0|TX_BUFFER[3]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER[3]~feeder_combout\ = \myVirtualToplevel|UART0|TX_BUFFER\(4) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(4), + combout => \myVirtualToplevel|UART0|TX_BUFFER[3]~feeder_combout\); + +-- Location: FF_X6_Y8_N38 +\myVirtualToplevel|UART0|TX_FIFO~21\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3), + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO~21_q\); + +-- Location: FF_X6_Y8_N7 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(20)); + +-- Location: LABCELL_X6_Y8_N36 +\myVirtualToplevel|UART0|TX_DATA~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & +-- (((!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\) # (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(20))))) # (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & (((\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\)) # +-- (\myVirtualToplevel|UART0|TX_FIFO~21_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & +-- (((\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(20))))) # (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & (((\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\)) # (\myVirtualToplevel|UART0|TX_FIFO~21_q\))) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & (((!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\) # +-- (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(20))))) # (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART0|TX_FIFO~21_q\ & (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a3\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & (((\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & +-- \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(20))))) # (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART0|TX_FIFO~21_q\ & (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000011100110100001101110000010011000111111101001111011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~21_q\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~2_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~1_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(20), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3), + dataf => \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\, + combout => \myVirtualToplevel|UART0|TX_DATA~10_combout\); + +-- Location: LABCELL_X7_Y8_N51 +\myVirtualToplevel|UART0|TX_DATA[3]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA[3]~11_combout\ = ( \myVirtualToplevel|UART0|TX_DATA~10_combout\ & ( ((\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\ & \myVirtualToplevel|UART0|TX_DATA[0]~4_combout\)) # (\myVirtualToplevel|UART0|TX_DATA\(3)) ) ) # ( +-- !\myVirtualToplevel|UART0|TX_DATA~10_combout\ & ( (\myVirtualToplevel|UART0|TX_DATA\(3) & ((!\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\) # (!\myVirtualToplevel|UART0|TX_DATA[0]~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~0_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~4_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA\(3), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA~10_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA[3]~11_combout\); + +-- Location: FF_X7_Y8_N53 +\myVirtualToplevel|UART0|TX_DATA[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_DATA[3]~11_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_DATA\(3)); + +-- Location: FF_X7_Y8_N35 +\myVirtualToplevel|UART0|TX_BUFFER[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER[3]~feeder_combout\, + asdata => \myVirtualToplevel|UART0|TX_DATA\(3), + sload => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(3)); + +-- Location: LABCELL_X7_Y8_N30 +\myVirtualToplevel|UART0|TX_BUFFER[2]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER[2]~feeder_combout\ = \myVirtualToplevel|UART0|TX_BUFFER\(3) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(3), + combout => \myVirtualToplevel|UART0|TX_BUFFER[2]~feeder_combout\); + +-- Location: LABCELL_X6_Y8_N27 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[19]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + combout => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[19]~feeder_combout\); + +-- Location: FF_X6_Y8_N29 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[19]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(19)); + +-- Location: FF_X6_Y8_N44 +\myVirtualToplevel|UART0|TX_FIFO~20\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO~20_q\); + +-- Location: LABCELL_X6_Y8_N42 +\myVirtualToplevel|UART0|TX_DATA~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( \myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(19))) +-- # (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & ((\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a2\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( \myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & ( +-- (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(19))) # (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & ((\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a2\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( !\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\) # (\myVirtualToplevel|UART0|TX_FIFO~20_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) +-- & ( !\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & ( (\myVirtualToplevel|UART0|TX_FIFO~20_q\ & \myVirtualToplevel|UART0|TX_DATA[0]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011111111110011001101010101000011110101010100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(19), + datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~20_q\, + datac => \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~2_combout\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~1_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA~8_combout\); + +-- Location: LABCELL_X7_Y8_N48 +\myVirtualToplevel|UART0|TX_DATA[2]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA[2]~9_combout\ = ( \myVirtualToplevel|UART0|TX_DATA~8_combout\ & ( ((\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\ & \myVirtualToplevel|UART0|TX_DATA[0]~4_combout\)) # (\myVirtualToplevel|UART0|TX_DATA\(2)) ) ) # ( +-- !\myVirtualToplevel|UART0|TX_DATA~8_combout\ & ( (\myVirtualToplevel|UART0|TX_DATA\(2) & ((!\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\) # (!\myVirtualToplevel|UART0|TX_DATA[0]~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~0_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~4_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA\(2), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA~8_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA[2]~9_combout\); + +-- Location: FF_X7_Y8_N49 +\myVirtualToplevel|UART0|TX_DATA[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_DATA[2]~9_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_DATA\(2)); + +-- Location: FF_X7_Y8_N32 +\myVirtualToplevel|UART0|TX_BUFFER[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER[2]~feeder_combout\, + asdata => \myVirtualToplevel|UART0|TX_DATA\(2), + sload => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(2)); + +-- Location: LABCELL_X7_Y8_N39 +\myVirtualToplevel|UART0|TX_BUFFER[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER[1]~feeder_combout\ = \myVirtualToplevel|UART0|TX_BUFFER\(2) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(2), + combout => \myVirtualToplevel|UART0|TX_BUFFER[1]~feeder_combout\); + +-- Location: FF_X6_Y8_N50 +\myVirtualToplevel|UART0|TX_FIFO~19\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO~19_q\); + +-- Location: FF_X12_Y8_N16 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(18)); + +-- Location: LABCELL_X6_Y8_N48 +\myVirtualToplevel|UART0|TX_DATA~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) & ( \myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(18))) +-- # (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & ((\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a1\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) & ( \myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & ( +-- (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(18))) # (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & ((\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a1\))) ) ) ) # ( +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) & ( !\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\) # (\myVirtualToplevel|UART0|TX_FIFO~19_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) +-- & ( !\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & ( (\myVirtualToplevel|UART0|TX_FIFO~19_q\ & \myVirtualToplevel|UART0|TX_DATA[0]~2_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001110111011101110100001100001111110000110000111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~19_q\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~2_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(18), + datad => \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~1_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA~6_combout\); + +-- Location: LABCELL_X7_Y8_N57 +\myVirtualToplevel|UART0|TX_DATA[1]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA[1]~7_combout\ = ( \myVirtualToplevel|UART0|TX_DATA~6_combout\ & ( ((\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\ & \myVirtualToplevel|UART0|TX_DATA[0]~4_combout\)) # (\myVirtualToplevel|UART0|TX_DATA\(1)) ) ) # ( +-- !\myVirtualToplevel|UART0|TX_DATA~6_combout\ & ( (\myVirtualToplevel|UART0|TX_DATA\(1) & ((!\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\) # (!\myVirtualToplevel|UART0|TX_DATA[0]~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~0_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~4_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA\(1), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA~6_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA[1]~7_combout\); + +-- Location: FF_X7_Y8_N59 +\myVirtualToplevel|UART0|TX_DATA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_DATA[1]~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_DATA\(1)); + +-- Location: FF_X7_Y8_N41 +\myVirtualToplevel|UART0|TX_BUFFER[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER[1]~feeder_combout\, + asdata => \myVirtualToplevel|UART0|TX_DATA\(1), + sload => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(1)); + +-- Location: LABCELL_X7_Y8_N36 +\myVirtualToplevel|UART0|TX_BUFFER[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_BUFFER[0]~feeder_combout\ = \myVirtualToplevel|UART0|TX_BUFFER\(1) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(1), + combout => \myVirtualToplevel|UART0|TX_BUFFER[0]~feeder_combout\); + +-- Location: FF_X6_Y8_N17 +\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(17)); + +-- Location: FF_X6_Y8_N35 +\myVirtualToplevel|UART0|TX_FIFO~18\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + sload => VCC, + ena => \myVirtualToplevel|UART0|TX_FIFO~34_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_FIFO~18_q\); + +-- Location: LABCELL_X6_Y8_N15 +\myVirtualToplevel|UART0|TX_DATA~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & +-- ((!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\) # ((\myVirtualToplevel|UART0|TX_FIFO~18_q\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(17))) # +-- (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & +-- (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & ((\myVirtualToplevel|UART0|TX_FIFO~18_q\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(17))) # (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\))) +-- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & ((!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\) # +-- ((\myVirtualToplevel|UART0|TX_FIFO~18_q\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(17)))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( !\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (!\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & +-- ((\myVirtualToplevel|UART0|TX_FIFO~18_q\)))) # (\myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ & (!\myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(17)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010000100110100011001010111000010101001101111001110110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~1_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~2_combout\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(17), + datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~18_q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0), + dataf => \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\, + combout => \myVirtualToplevel|UART0|TX_DATA~3_combout\); + +-- Location: LABCELL_X7_Y8_N54 +\myVirtualToplevel|UART0|TX_DATA[0]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TX_DATA[0]~5_combout\ = ( \myVirtualToplevel|UART0|TX_DATA~3_combout\ & ( ((\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\ & \myVirtualToplevel|UART0|TX_DATA[0]~4_combout\)) # (\myVirtualToplevel|UART0|TX_DATA\(0)) ) ) # ( +-- !\myVirtualToplevel|UART0|TX_DATA~3_combout\ & ( (\myVirtualToplevel|UART0|TX_DATA\(0) & ((!\myVirtualToplevel|UART0|TX_DATA[0]~0_combout\) # (!\myVirtualToplevel|UART0|TX_DATA[0]~4_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011101110000000001110111000010001111111110001000111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~0_combout\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~4_combout\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_DATA\(0), + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA~3_combout\, + combout => \myVirtualToplevel|UART0|TX_DATA[0]~5_combout\); + +-- Location: FF_X7_Y8_N56 +\myVirtualToplevel|UART0|TX_DATA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_DATA[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_DATA\(0)); + +-- Location: FF_X7_Y8_N37 +\myVirtualToplevel|UART0|TX_BUFFER[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TX_BUFFER[0]~feeder_combout\, + asdata => \myVirtualToplevel|UART0|TX_DATA\(0), + sload => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + ena => \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TX_BUFFER\(0)); + +-- Location: MLABCELL_X9_Y8_N0 +\myVirtualToplevel|UART0|TXD~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|UART0|TXD~0_combout\ = ( \myVirtualToplevel|UART0|TXD~q\ & ( \myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ( ((!\myVirtualToplevel|UART0|TX_CLOCK~q\) # ((!\myVirtualToplevel|UART0|TX_STATE~q\) # +-- (!\myVirtualToplevel|UART0|TX_BUFFER\(0)))) # (\myVirtualToplevel|UART0|TX_ENABLE~q\) ) ) ) # ( !\myVirtualToplevel|UART0|TXD~q\ & ( \myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ( (!\myVirtualToplevel|UART0|TX_ENABLE~q\ & +-- ((!\myVirtualToplevel|UART0|TX_STATE~q\) # ((\myVirtualToplevel|UART0|TX_CLOCK~q\ & !\myVirtualToplevel|UART0|TX_BUFFER\(0))))) ) ) ) # ( \myVirtualToplevel|UART0|TXD~q\ & ( !\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ( +-- ((!\myVirtualToplevel|UART0|TX_CLOCK~q\) # ((!\myVirtualToplevel|UART0|TX_STATE~q\) # (!\myVirtualToplevel|UART0|TX_BUFFER\(0)))) # (\myVirtualToplevel|UART0|TX_ENABLE~q\) ) ) ) # ( !\myVirtualToplevel|UART0|TXD~q\ & ( +-- !\myVirtualToplevel|UART0|TX_DATA_LOADED~q\ & ( (!\myVirtualToplevel|UART0|TX_ENABLE~q\ & (\myVirtualToplevel|UART0|TX_CLOCK~q\ & (\myVirtualToplevel|UART0|TX_STATE~q\ & !\myVirtualToplevel|UART0|TX_BUFFER\(0)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000000111111111111110110100010101000001111111111111101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\, + datab => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK~q\, + datac => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\, + datad => \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(0), + datae => \myVirtualToplevel|UART0|ALT_INV_TXD~q\, + dataf => \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\, + combout => \myVirtualToplevel|UART0|TXD~0_combout\); + +-- Location: FF_X9_Y8_N1 +\myVirtualToplevel|UART0|TXD\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|UART0|TXD~0_combout\, + clrn => \myVirtualToplevel|UART0|TX_RESET~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|UART0|TXD~q\); + +-- Location: LABCELL_X24_Y7_N39 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(2)) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(2)))))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100100011001100010010001100110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(2), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(9), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~1_combout\); + +-- Location: LABCELL_X25_Y7_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~48\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~48_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & +-- ((((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & ((((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\))))) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "1111011100000000111100000000000011110111111111111111000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~0_combout\, + datag => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~48_combout\); + +-- Location: LABCELL_X24_Y7_N33 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~48_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~1_combout\ & !\myVirtualToplevel|SD_HNDSHK_IN\(0))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\ & +-- ((\myVirtualToplevel|SD_HNDSHK_IN\(0)))))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~48_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & +-- \myVirtualToplevel|SD_HNDSHK_IN\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000010001000000000001000100100000000100010010000000010001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~1_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~48_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\); + +-- Location: LABCELL_X24_Y7_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # (\myVirtualToplevel|SD_HNDSHK_IN\(0))))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001000100010001000100010000000100010001000000010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\, + datac => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\); + +-- Location: MLABCELL_X23_Y7_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & \myVirtualToplevel|SD_HNDSHK_IN\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000001100110000000000110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datad => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\); + +-- Location: MLABCELL_X23_Y7_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~8_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000000000000111100000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~8_combout\); + +-- Location: LABCELL_X19_Y9_N54 +\myVirtualToplevel|SD_DATA_WRITE[7]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SD_DATA_WRITE[7]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|SD_CS~combout\ & ( (\myVirtualToplevel|RESET_n~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000001000000010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2), + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3), + dataf => \myVirtualToplevel|ALT_INV_SD_CS~combout\, + combout => \myVirtualToplevel|SD_DATA_WRITE[7]~0_combout\); + +-- Location: FF_X23_Y7_N20 +\myVirtualToplevel|SD_DATA_WRITE[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4), + sload => VCC, + ena => \myVirtualToplevel|SD_DATA_WRITE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_DATA_WRITE\(4)); + +-- Location: FF_X23_Y7_N1 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[43]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v~12_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(43)); + +-- Location: MLABCELL_X23_Y7_N33 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100110011001100110011001100110000001100110011000000110011001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_process_0~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\); + +-- Location: MLABCELL_X23_Y7_N21 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~14\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~14_combout\ = (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010101010101000001010101010100000101010101010000010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~5_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~14_combout\); + +-- Location: LABCELL_X20_Y7_N3 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][31]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][31]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~feeder_combout\); + +-- Location: LABCELL_X21_Y7_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\)) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010001000100010001000100010001011100010111000101110001011100010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\); + +-- Location: LABCELL_X21_Y7_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~23_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\); + +-- Location: LABCELL_X21_Y9_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~2_combout\ = ( \myVirtualToplevel|SD_ADDR[0][30]~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) ) ) ) # ( !\myVirtualToplevel|SD_ADDR[0][30]~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) ) ) ) # ( \myVirtualToplevel|SD_ADDR[0][30]~q\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\) ) ) ) # ( +-- !\myVirtualToplevel|SD_ADDR[0][30]~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001111110011111100110000001100000011000000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datae => \myVirtualToplevel|ALT_INV_SD_ADDR[0][30]~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~2_combout\); + +-- Location: LABCELL_X21_Y7_N3 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~0_combout\); + +-- Location: LABCELL_X20_Y7_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[37]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[37]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][29]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][29]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[37]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N39 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[36]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[36]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][28]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_ADDR[0][28]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[36]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[35]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[35]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][27]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][27]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[35]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N21 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[34]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[34]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][26]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_ADDR[0][26]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[34]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[33]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[33]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][25]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][25]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[33]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N15 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[32]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[32]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][24]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_ADDR[0][24]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[32]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[31]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[31]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][23]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][23]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[31]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N33 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[30]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[30]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][22]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][22]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[30]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[29]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[29]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][21]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][21]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[29]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N3 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[28]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[28]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][20]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][20]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[28]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[27]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[27]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][19]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_ADDR[0][19]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[27]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N9 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[26]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[26]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][18]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][18]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[26]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[25]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[25]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][17]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_ADDR[0][17]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[25]~feeder_combout\); + +-- Location: FF_X18_Y9_N28 +\myVirtualToplevel|SD_ADDR[0][16]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][16]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][16]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y9_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~feeder_combout\ = ( \myVirtualToplevel|SD_ADDR[0][16]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_SD_ADDR[0][16]~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[23]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[23]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][15]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][15]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[23]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N27 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[22]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[22]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][14]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_ADDR[0][14]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[22]~feeder_combout\); + +-- Location: FF_X18_Y9_N19 +\myVirtualToplevel|SD_ADDR[0][13]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][13]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][13]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y9_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[21]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[21]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][13]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][13]~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[21]~feeder_combout\); + +-- Location: FF_X13_Y10_N31 +\myVirtualToplevel|SD_ADDR[0][12]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][12]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][12]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y9_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[20]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[20]~feeder_combout\ = ( \myVirtualToplevel|SD_ADDR[0][12]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_SD_ADDR[0][12]~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[20]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[19]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[19]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][11]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_ADDR[0][11]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[19]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[18]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[18]~feeder_combout\ = ( \myVirtualToplevel|SD_ADDR[0][10]~q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ALT_INV_SD_ADDR[0][10]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[18]~feeder_combout\); + +-- Location: LABCELL_X20_Y9_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[17]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[17]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][9]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][9]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[17]~feeder_combout\); + +-- Location: LABCELL_X20_Y7_N9 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[14]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[14]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][6]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][6]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[14]~feeder_combout\); + +-- Location: FF_X18_Y9_N22 +\myVirtualToplevel|SD_ADDR[0][4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SD_ADDR[0][4]~feeder_combout\, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][4]~q\); + +-- Location: LABCELL_X20_Y7_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[12]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[12]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][4]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][4]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[12]~feeder_combout\); + +-- Location: FF_X18_Y9_N43 +\myVirtualToplevel|SD_ADDR[0][2]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + sload => VCC, + ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_ADDR[0][2]~DUPLICATE_q\); + +-- Location: LABCELL_X20_Y7_N15 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[10]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[10]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][2]~DUPLICATE_q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][2]~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[10]~feeder_combout\); + +-- Location: LABCELL_X20_Y7_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[8]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[8]~feeder_combout\ = \myVirtualToplevel|SD_ADDR[0][0]~q\ + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_ADDR[0][0]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[8]~feeder_combout\); + +-- Location: LABCELL_X20_Y7_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000010100000101000001010000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19_combout\); + +-- Location: LABCELL_X21_Y7_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010000000000000101000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~0_combout\); + +-- Location: LABCELL_X21_Y7_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(1) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~0_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~0_combout\)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(1) & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~0_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~0_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000101100000000000010110000000000001010000000000000101000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector157~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(1), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~1_combout\); + +-- Location: LABCELL_X21_Y7_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~1_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(1) & +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\))) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~1_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111100000000001011110000000000101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(1), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector157~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~2_combout\); + +-- Location: FF_X21_Y7_N58 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~2_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(1)); + +-- Location: LABCELL_X21_Y7_N21 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[2]~43\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[2]~43_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(2) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(1) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(2) & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(1) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(2) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(1) & ( +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(2) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(1) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000111111111101110100100000001000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~23_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(2), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(1), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[2]~43_combout\); + +-- Location: FF_X21_Y7_N22 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[2]~43_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(2)); + +-- Location: LABCELL_X21_Y7_N9 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~41\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~41_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(2)) # +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011001111111111111100111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(2), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[6]~19_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~41_combout\); + +-- Location: LABCELL_X21_Y7_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~42\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~42_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~41_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(3) & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~41_combout\ & ( +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(3)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111111111000001011111111100000000111110100000000011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(3), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[3]~41_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~42_combout\); + +-- Location: FF_X21_Y7_N8 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~42_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(3)); + +-- Location: LABCELL_X21_Y7_N27 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(3) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(4)) +-- # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(4)) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(3) +-- & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(4)) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111101011001000111100001100000011111010110010001111000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(4), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(3), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~23_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~0_combout\); + +-- Location: LABCELL_X21_Y7_N39 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\) # +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(4))))) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~0_combout\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111111111111111111111110100111101011111010011110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr40~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(4), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector154~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~1_combout\); + +-- Location: FF_X21_Y7_N41 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~1_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(4)); + +-- Location: LABCELL_X21_Y7_N33 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~39\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~39_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19_combout\ & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(4)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110111111101111111011111110111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(4), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[6]~19_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~39_combout\); + +-- Location: LABCELL_X21_Y7_N15 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~40\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~40_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~39_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(5) & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~39_combout\ & ( +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(5)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111111111000100011111111100000000111011100000000011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(5), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[5]~39_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~40_combout\); + +-- Location: FF_X21_Y7_N17 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~40_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(5)); + +-- Location: LABCELL_X21_Y7_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~37\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~37_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(5) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19_combout\ & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(5) & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000111000001110000011100000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[6]~19_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(5), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~37_combout\); + +-- Location: LABCELL_X21_Y7_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~38\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~38_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~37_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(6) & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~37_combout\ & ( +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(6)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000111111111000100011111111100000000111011100000000011101110", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(6), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[6]~37_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~38_combout\); + +-- Location: FF_X21_Y7_N13 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~38_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(6)); + +-- Location: LABCELL_X21_Y7_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[7]~36\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[7]~36_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(7) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(6) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(7) & ( +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(6) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(7) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(6) & ( +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(7) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(6) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0010000000000000111111011111110100100010000000001111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~23_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(7), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(6), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[7]~36_combout\); + +-- Location: FF_X21_Y7_N19 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[7]~36_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(7)); + +-- Location: LABCELL_X20_Y7_N33 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000011110000111100001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\); + +-- Location: FF_X20_Y7_N8 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[8]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(7), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(8)); + +-- Location: LABCELL_X20_Y7_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~34\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~34_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(8) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) # (\myVirtualToplevel|SD_ADDR[0][1]~q\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(8) & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\ & \myVirtualToplevel|SD_ADDR[0][1]~q\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000101000000000000010100001010000011110000101000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr40~0_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_ADDR[0][1]~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(8), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~34_combout\); + +-- Location: LABCELL_X20_Y7_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~35\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~35_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~34_combout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(9)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~34_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(9))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(9)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111011000000011111101100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(9), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[9]~34_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~35_combout\); + +-- Location: FF_X20_Y7_N47 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~35_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(9)); + +-- Location: FF_X20_Y7_N17 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[10]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(9), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(10)); + +-- Location: LABCELL_X20_Y7_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~32\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~32_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\ & \myVirtualToplevel|SD_ADDR[0][3]~q\) ) ) # +-- ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(10) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(10), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr40~0_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_ADDR[0][3]~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~32_combout\); + +-- Location: LABCELL_X20_Y7_N21 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~33\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~33_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~32_combout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(11)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~32_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(11))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(11)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111011000000011111101100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(11), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[11]~32_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~33_combout\); + +-- Location: FF_X20_Y7_N23 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~33_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(11)); + +-- Location: FF_X20_Y7_N14 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[12]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(11), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(12)); + +-- Location: LABCELL_X20_Y7_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~30\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~30_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(12))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ((\myVirtualToplevel|SD_ADDR[0][5]~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(12), + datad => \myVirtualToplevel|ALT_INV_SD_ADDR[0][5]~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr40~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~30_combout\); + +-- Location: LABCELL_X20_Y7_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~31\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~31_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~30_combout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(13)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~30_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(13))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(13)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111011000000011111101100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(13), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[13]~30_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~31_combout\); + +-- Location: FF_X20_Y7_N20 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~31_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(13)); + +-- Location: FF_X20_Y7_N11 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[14]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(13), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(14)); + +-- Location: LABCELL_X20_Y7_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~28\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~28_combout\ = (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(14))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ((\myVirtualToplevel|SD_ADDR[0][7]~q\))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001000000111000000100000011100000010000001110000001000000111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(14), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr40~0_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_ADDR[0][7]~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~28_combout\); + +-- Location: LABCELL_X20_Y7_N39 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~29\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~29_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~28_combout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(15)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~28_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(15))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(15)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111011000000011111101100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(15), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[15]~28_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~29_combout\); + +-- Location: FF_X20_Y7_N41 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~29_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(15)); + +-- Location: LABCELL_X20_Y7_N27 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~26\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~26_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(15))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ((\myVirtualToplevel|SD_ADDR[0][8]~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001010010111110000101001011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(15), + datad => \myVirtualToplevel|ALT_INV_SD_ADDR[0][8]~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr40~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~26_combout\); + +-- Location: LABCELL_X20_Y7_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~27\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~27_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~26_combout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(16)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~26_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(16))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(16)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111011000000011111101100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(16), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[16]~26_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~27_combout\); + +-- Location: FF_X20_Y7_N37 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~27_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(16)); + +-- Location: FF_X20_Y9_N8 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[17]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(16), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(17)); + +-- Location: FF_X20_Y9_N47 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[18]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(17), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(18)); + +-- Location: FF_X20_Y9_N44 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[19]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(18), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(19)); + +-- Location: FF_X20_Y9_N52 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[20]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(19), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(20)); + +-- Location: FF_X20_Y9_N56 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[21]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(20), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(21)); + +-- Location: FF_X20_Y9_N29 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[22]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(21), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(22)); + +-- Location: FF_X20_Y9_N26 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[23]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(22), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(23)); + +-- Location: FF_X20_Y9_N59 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(23), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(24)); + +-- Location: FF_X20_Y9_N50 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[25]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[25]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(24), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(25)); + +-- Location: FF_X20_Y9_N11 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[26]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[26]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(25), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(26)); + +-- Location: FF_X20_Y9_N1 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[27]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[27]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(26), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(27)); + +-- Location: FF_X20_Y9_N5 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[28]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[28]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(27), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(28)); + +-- Location: FF_X20_Y9_N32 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[29]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[29]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(28), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(29)); + +-- Location: FF_X20_Y9_N35 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[30]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[30]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(29), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(30)); + +-- Location: FF_X20_Y9_N14 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[31]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[31]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(30), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(31)); + +-- Location: FF_X20_Y9_N17 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[32]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[32]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(31), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(32)); + +-- Location: FF_X20_Y9_N20 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[33]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[33]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(32), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(33)); + +-- Location: FF_X20_Y9_N23 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[34]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[34]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(33), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(34)); + +-- Location: FF_X20_Y9_N38 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[35]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[35]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(34), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(35)); + +-- Location: FF_X20_Y9_N40 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[36]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[36]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(35), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(36)); + +-- Location: FF_X20_Y7_N1 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[37]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[37]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(36), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(37)); + +-- Location: LABCELL_X21_Y7_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(37) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~0_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111111111110000111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(37), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~1_combout\); + +-- Location: LABCELL_X21_Y7_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~3_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~1_combout\ ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~1_combout\ & ( +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(38)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\)))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~2_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100111111001111010011111100111111111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~2_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(38), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~3_combout\); + +-- Location: FF_X21_Y7_N47 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[38]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~3_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(38)); + +-- Location: FF_X20_Y7_N4 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~feeder_combout\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(38), + sclr => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(39)); + +-- Location: FF_X23_Y7_N26 +\myVirtualToplevel|SD_DATA_WRITE[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0), + sload => VCC, + ena => \myVirtualToplevel|SD_DATA_WRITE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_DATA_WRITE\(0)); + +-- Location: LABCELL_X26_Y7_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal8~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal8~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000001000000000000000100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[9]~DUPLICATE_q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal8~0_combout\); + +-- Location: LABCELL_X25_Y7_N51 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~20\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~20_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal8~0_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) # ((\myVirtualToplevel|SD_RD\(0))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal8~0_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1011101111110000101110111111000000000000111100000000000011110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datab => \myVirtualToplevel|ALT_INV_SD_RD\(0), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal8~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[6]~19_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~20_combout\); + +-- Location: MLABCELL_X23_Y7_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~21\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~21_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~20_combout\ & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(39))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & ((\myVirtualToplevel|SD_DATA_WRITE\(0))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~20_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(39))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & ((\myVirtualToplevel|SD_DATA_WRITE\(0)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010000010000010101001011101011111110101110101111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~5_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_process_0~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(39), + datad => \myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[40]~20_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~21_combout\); + +-- Location: MLABCELL_X23_Y7_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~16_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\) # +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\)) # (\myVirtualToplevel|SD_HNDSHK_IN\(0)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111100111111111111110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~16_combout\); + +-- Location: MLABCELL_X23_Y7_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~22\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~22_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~16_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(40)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~21_combout\)) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~16_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(40) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100000101111101010000010111110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[40]~21_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~2_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(40), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[41]~16_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~22_combout\); + +-- Location: FF_X23_Y7_N56 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~22_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(40)); + +-- Location: FF_X23_Y7_N32 +\myVirtualToplevel|SD_DATA_WRITE[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1), + sload => VCC, + ena => \myVirtualToplevel|SD_DATA_WRITE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_DATA_WRITE\(1)); + +-- Location: MLABCELL_X23_Y7_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~17_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(40))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & ((\myVirtualToplevel|SD_DATA_WRITE\(1)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000111111000011000011111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_process_0~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(40), + datad => \myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(1), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~5_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~17_combout\); + +-- Location: MLABCELL_X23_Y7_N45 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~18_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~16_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ & +-- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(41))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~17_combout\)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~14_combout\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~16_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(41) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111111000000001111111100010101101111110001010110111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~2_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~14_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[41]~17_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(41), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[41]~16_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~18_combout\); + +-- Location: FF_X23_Y7_N47 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~18_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(41)); + +-- Location: FF_X23_Y7_N29 +\myVirtualToplevel|SD_DATA_WRITE[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2), + sload => VCC, + ena => \myVirtualToplevel|SD_DATA_WRITE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_DATA_WRITE\(2)); + +-- Location: MLABCELL_X23_Y7_N27 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~13_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(41))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & ((\myVirtualToplevel|SD_DATA_WRITE\(2)))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000100000101010000010000010101000001000001010100000100000101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~5_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_process_0~1_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(41), + datad => \myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(2), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~13_combout\); + +-- Location: MLABCELL_X23_Y7_N42 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~15_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~13_combout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(42)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~13_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(42))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(42)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\ & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~14_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000111111011000000011111101100000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~2_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~14_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(42), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~13_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~15_combout\); + +-- Location: FF_X23_Y7_N43 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~15_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(42)); + +-- Location: LABCELL_X25_Y7_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000001001000000000000100100000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(9), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~1_combout\); + +-- Location: MLABCELL_X23_Y7_N18 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(42)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111110000000000111111000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(42), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~0_combout\); + +-- Location: LABCELL_X25_Y7_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~1_combout\ & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) # ((!\myVirtualToplevel|SD_WR\(0)) # (\myVirtualToplevel|SD_RD\(0))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110000101100001111000010110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datab => \myVirtualToplevel|ALT_INV_SD_RD\(0), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~1_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_WR\(0), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~0_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~2_combout\); + +-- Location: LABCELL_X25_Y7_N30 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~3_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & ( \myVirtualToplevel|SD_RD\(0) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & ( \myVirtualToplevel|SD_RD\(0) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\) # +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\)))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & ( !\myVirtualToplevel|SD_RD\(0) & +-- ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & ( !\myVirtualToplevel|SD_RD\(0) & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1000000010100000101000001010000010001010101010101010101010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + dataf => \myVirtualToplevel|ALT_INV_SD_RD\(0), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~3_combout\); + +-- Location: LABCELL_X24_Y7_N57 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~2_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~3_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(43))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(42))))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~2_combout\ & ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~3_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(43) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) # +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(42)) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000101010101010100000000000000000001110111011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(43), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(42), + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~0_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~2_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~3_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4_combout\); + +-- Location: FF_X24_Y7_N56 +\myVirtualToplevel|SD_DATA_WRITE[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3), + sload => VCC, + ena => \myVirtualToplevel|SD_DATA_WRITE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_DATA_WRITE\(3)); + +-- Location: MLABCELL_X23_Y7_N0 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v~12_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(43) & ( \myVirtualToplevel|SD_DATA_WRITE\(3) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4_combout\) # +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\) # (\myVirtualToplevel|SD_HNDSHK_IN\(0))))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(43) & ( +-- \myVirtualToplevel|SD_DATA_WRITE\(3) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4_combout\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ +-- & ((!\myVirtualToplevel|SD_HNDSHK_IN\(0) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4_combout\)) # (\myVirtualToplevel|SD_HNDSHK_IN\(0) & +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\)))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(43) & ( !\myVirtualToplevel|SD_DATA_WRITE\(3) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4_combout\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & ((!\myVirtualToplevel|SD_HNDSHK_IN\(0) & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\))) # (\myVirtualToplevel|SD_HNDSHK_IN\(0) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\)))) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(43) & ( !\myVirtualToplevel|SD_DATA_WRITE\(3) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # +-- ((!\myVirtualToplevel|SD_HNDSHK_IN\(0) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\)))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110101000000000111111100001010011101011000000011111111100010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\, + datab => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~4_combout\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(43), + dataf => \myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(3), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v~12_combout\); + +-- Location: FF_X23_Y7_N2 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[43]~DUPLICATE\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v~12_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[43]~DUPLICATE_q\); + +-- Location: MLABCELL_X23_Y7_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~44\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~44_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & +-- ((((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\)))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & (\myVirtualToplevel|SD_DATA_WRITE\(4))) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & +-- ((((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[43]~DUPLICATE_q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\)))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & (\myVirtualToplevel|SD_DATA_WRITE\(4))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0011111111111111001111111111111101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(4), + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[43]~DUPLICATE_q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_process_0~1_combout\, + datag => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~44_combout\); + +-- Location: MLABCELL_X23_Y7_N9 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~11_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~44_combout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ & +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(44)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~44_combout\ & ( +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(44) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111010000000001111101000000101111111110000010111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(44), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[44]~44_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~11_combout\); + +-- Location: FF_X23_Y7_N11 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~11_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(44)); + +-- Location: FF_X23_Y7_N50 +\myVirtualToplevel|SD_DATA_WRITE[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5), + sload => VCC, + ena => \myVirtualToplevel|SD_DATA_WRITE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_DATA_WRITE\(5)); + +-- Location: MLABCELL_X23_Y7_N48 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~9_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\ & ((\myVirtualToplevel|SD_DATA_WRITE\(5)))) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~8_combout\)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & ( +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(44)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~8_combout\)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011101000111010001110100011101000001010111110100000101011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[45]~8_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(44), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~5_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(5), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_process_0~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~9_combout\); + +-- Location: MLABCELL_X23_Y7_N39 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~10_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\ & +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(45)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~9_combout\)) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(45) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110101001101010011010100110101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[45]~9_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(45), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~0_combout\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~2_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~10_combout\); + +-- Location: FF_X23_Y7_N14 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~10_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(45)); + +-- Location: FF_X23_Y7_N38 +\myVirtualToplevel|SD_DATA_WRITE[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6), + sload => VCC, + ena => \myVirtualToplevel|SD_DATA_WRITE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_DATA_WRITE\(6)); + +-- Location: MLABCELL_X23_Y7_N36 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~6_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\ & !\myVirtualToplevel|SD_DATA_WRITE\(6)) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(45) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000110000001100000011110000000000001111000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(45), + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~5_combout\, + datad => \myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(6), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_process_0~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~6_combout\); + +-- Location: LABCELL_X24_Y7_N24 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~7_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~6_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(46) & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~6_combout\ & ( +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(46)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001111111111000000111111111100000000111111000000000011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~0_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~2_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(46), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[46]~6_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~7_combout\); + +-- Location: FF_X24_Y7_N26 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~7_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(46)); + +-- Location: FF_X24_Y7_N14 +\myVirtualToplevel|SD_DATA_WRITE[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7), + sload => VCC, + ena => \myVirtualToplevel|SD_DATA_WRITE[7]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SD_DATA_WRITE\(7)); + +-- Location: LABCELL_X24_Y7_N12 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~3_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(46)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & (((!\myVirtualToplevel|SD_DATA_WRITE\(7))))) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ & ((!\myVirtualToplevel|SD_DATA_WRITE\(7)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1101110110001000110111011000100011010101100000001101010110000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_process_0~1_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(46), + datad => \myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(7), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~3_combout\); + +-- Location: LABCELL_X24_Y7_N27 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~4_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~3_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(47) & +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~3_combout\ & ( +-- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(47)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010111111111000001011111111100000000111110100000000011111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~2_combout\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~0_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(47), + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~3_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~4_combout\); + +-- Location: FF_X24_Y7_N29 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(47)); + +-- Location: LABCELL_X25_Y7_N6 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector172~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector172~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(47) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & +-- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(47) & ( +-- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\) ) ) ) # ( +-- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(47) & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\)) # +-- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001101110111111100111111111100000000000000001100000010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~0_combout\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\, + datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(47), + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector172~0_combout\); + +-- Location: FF_X25_Y7_N7 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector172~0_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~q\); + +-- Location: MLABCELL_X23_Y5_N54 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~2_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & +-- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|cs_bo~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010001010101010101000101010101000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\, + datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\, + datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\, + datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_cs_bo~q\, + dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\, + combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~2_combout\); + +-- Location: FF_X23_Y5_N55 +\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|cs_bo\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~2_combout\, + ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|cs_bo~q\); + +-- Location: LABCELL_X17_Y4_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~0_combout\ = (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)))) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(0))))) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000100100011000000010010001100000001001000110000000100100011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(0), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~0_combout\); + +-- Location: LABCELL_X20_Y6_N6 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(1) & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(0) +-- & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(2))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000010000000100000001000000010000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(1), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(0), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(2), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(3), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0_combout\); + +-- Location: LABCELL_X20_Y6_N3 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~0_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(6) & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(7)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000100010001000100010001000100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(6), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(7), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(5), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~0_combout\); + +-- Location: LABCELL_X17_Y4_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1_combout\ = (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011110000110000001111000011000000111100001100000011110000110000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1_combout\); + +-- Location: MLABCELL_X18_Y4_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( (\myVirtualToplevel|RESET_n~q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000001000000000000000100000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3_combout\); + +-- Location: LABCELL_X17_Y4_N3 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~2_combout\ = (\myVirtualToplevel|RESET_n~q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000000000001010000000000000101000000000000010100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ALT_INV_RESET_n~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(4), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~2_combout\); + +-- Location: LABCELL_X17_Y4_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\); + +-- Location: LABCELL_X17_Y4_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~2_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0_combout\ & (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3_combout\)))) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0_combout\ & (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3_combout\)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~2_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\ & ( +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~2_combout\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~2_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1_combout\ & +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000011110001000100011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~0_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~1_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~3_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~2_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~1_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\); + +-- Location: FF_X17_Y4_N50 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~0_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(0)); + +-- Location: FF_X19_Y4_N10 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(1)); + +-- Location: MLABCELL_X18_Y4_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~5_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(1) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(1)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(1)) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(1) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(1) & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(1)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000110000001100000011000000110000111111001111110011111100111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(1), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(1), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~5_combout\); + +-- Location: FF_X18_Y4_N14 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~5_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(1)); + +-- Location: FF_X17_Y6_N49 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(2)); + +-- Location: LABCELL_X19_Y4_N15 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~6_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(2) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(2) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(2), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(2), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~6_combout\); + +-- Location: FF_X19_Y4_N17 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~6_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(2)); + +-- Location: FF_X19_Y4_N37 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(3)); + +-- Location: LABCELL_X19_Y4_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~7_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(3) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(3) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(3), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(3), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~7_combout\); + +-- Location: FF_X19_Y4_N13 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~7_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(3)); + +-- Location: LABCELL_X17_Y6_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[4]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[4]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[4]~feeder_combout\); + +-- Location: FF_X17_Y6_N35 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[4]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(4)); + +-- Location: LABCELL_X17_Y6_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~8_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(4) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(4)) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(4) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(4)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000110011000000000011001111001100111111111100110011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(4), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(4), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~8_combout\); + +-- Location: FF_X17_Y6_N13 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~8_combout\, + asdata => VCC, + sload => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(4)); + +-- Location: LABCELL_X17_Y6_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[5]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[5]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[5]~feeder_combout\); + +-- Location: FF_X17_Y6_N37 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[5]~feeder_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(5)); + +-- Location: LABCELL_X17_Y6_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~9_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(5) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(5) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(5), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(5), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~9_combout\); + +-- Location: FF_X17_Y6_N43 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~9_combout\, + asdata => VCC, + sload => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(5)); + +-- Location: FF_X19_Y4_N34 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7), + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(6)); + +-- Location: MLABCELL_X18_Y4_N15 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~10_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(6) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(6) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000000111111110000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(6), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(6), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~10_combout\); + +-- Location: FF_X18_Y4_N17 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~10_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(6)); + +-- Location: FF_X18_Y7_N34 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(7)); + +-- Location: MLABCELL_X18_Y7_N51 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~11_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(7) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(7) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011010101010101010100110011001100110101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(7), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(7), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~11_combout\); + +-- Location: FF_X18_Y7_N52 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~11_combout\, + sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(7)); + +-- Location: LABCELL_X17_Y4_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~12_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(8)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000101000001010000010100000101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(8), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~12_combout\); + +-- Location: FF_X17_Y4_N31 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~12_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(8)); + +-- Location: LABCELL_X17_Y4_N33 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~13\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~13_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(9)) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1010101010101010101010101010101010101111101011111010111110101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(9), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~13_combout\); + +-- Location: FF_X17_Y4_N35 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~13_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(9)); + +-- Location: LABCELL_X17_Y5_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~15\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~15_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0_combout\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~0_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000000000000010000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~0_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~0_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(4), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~15_combout\); + +-- Location: LABCELL_X17_Y5_N45 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100001100000011000000110000001100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1_combout\); + +-- Location: LABCELL_X20_Y4_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~16\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~16_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ +-- & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~0_combout\)))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\)))) ) +-- ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\) ) +-- ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\) +-- ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000001100000011000000110000001100000011010100110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~0_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~7_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~0_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(4), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~1_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~16_combout\); + +-- Location: LABCELL_X17_Y5_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux28~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux28~0_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(10) +-- & (((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~5_combout\)))) ) ) # ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(10))) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(10)))))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(10)))))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "on", + lut_mask => "0000000011000100000011000011111100000000110011000000000011111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~5_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(10), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR\(10), + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datag => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~2_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux28~0_combout\); + +-- Location: LABCELL_X17_Y5_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~17\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~17_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(10) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux28~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~15_combout\) # +-- (((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~14_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~16_combout\)) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(10) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux28~0_combout\ & ( ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~14_combout\)) +-- # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~16_combout\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(10) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux28~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~15_combout\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~14_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1_combout\)))) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~16_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(10) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux28~0_combout\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~16_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111101011110010111100001111110011111010111111101111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~15_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~1_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~16_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~14_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR\(10), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux28~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~17_combout\); + +-- Location: FF_X17_Y5_N55 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~17_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(10)); + +-- Location: LABCELL_X17_Y4_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~18\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~18_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(11) & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000011000000110000001100000011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(11), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~18_combout\); + +-- Location: FF_X17_Y4_N26 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~18_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(11)); + +-- Location: FF_X17_Y9_N5 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(2)); + +-- Location: LABCELL_X17_Y9_N0 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ & +-- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\) # +-- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000011111100110011001111110000000000111111001100110011111100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~1_combout\); + +-- Location: FF_X17_Y9_N1 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~1_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(0)); + +-- Location: LABCELL_X17_Y9_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux92~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux92~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(0) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\) # ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(2) & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0))) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(0) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\) # ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(2)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1110111011111111111011101111111111101110101010101110111010101010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuIsWriting~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\(2), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux92~0_combout\); + +-- Location: MLABCELL_X18_Y6_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[0]~0_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(4) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(3) & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0001000000000000000000000000000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(3), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(4), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[0]~0_combout\); + +-- Location: FF_X17_Y9_N13 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux92~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM\(0)); + +-- Location: LABCELL_X17_Y9_N45 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\) # +-- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0100110001001100010011000100110001001111010011110100111101001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\, + datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\, + dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~3_combout\); + +-- Location: FF_X17_Y9_N47 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~3_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(1)); + +-- Location: FF_X17_Y9_N43 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\, + asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + sload => VCC, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(3)); + +-- Location: LABCELL_X17_Y9_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux91~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux91~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(3) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(1))) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(3) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\) # ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)) # +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(1))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111011111110111111101111111010111010101110101011101010111010", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuIsWriting~q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\(1), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\(3), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux91~0_combout\); + +-- Location: FF_X17_Y9_N55 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux91~0_combout\, + clrn => \myVirtualToplevel|RESET_n~q\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM\(1)); + +-- Location: MLABCELL_X18_Y5_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~feeder_combout\ = \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010101010101010101010101010101010101010101010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(0), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~feeder_combout\); + +-- Location: LABCELL_X19_Y4_N57 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\) # +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011110101111100011111010111110001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~5_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~3_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~4_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~1_combout\); + +-- Location: LABCELL_X17_Y5_N6 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~1_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000000000000101010101010111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~19_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~1_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~1_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~0_combout\); + +-- Location: FF_X18_Y5_N55 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~feeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA\(0)); + +-- Location: MLABCELL_X18_Y5_N57 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[1]~feeder\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[1]~feeder_combout\ = \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011001100110011001100110011001100110011001100110011001100110011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[1]~feeder_combout\); + +-- Location: FF_X18_Y5_N59 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[1]~feeder_combout\, + ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA\(1)); + +-- Location: MLABCELL_X18_Y4_N24 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ +-- & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\)) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1100000011000000110000001100000000000000110000000000000011000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuIsWriting~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~0_combout\); + +-- Location: MLABCELL_X18_Y4_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~1\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~0_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~2_combout\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\) # +-- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\)))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000000101010110000000010101011", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~2_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~1_combout\); + +-- Location: LABCELL_X19_Y6_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~9_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(1) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011110000111100001111000000000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(1), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter[2]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~9_combout\); + +-- Location: LABCELL_X19_Y6_N57 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~8_combout\ = (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(7) & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(6)) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000001111000000000000111100000000000011110000000000001111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(7), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(6), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~8_combout\); + +-- Location: LABCELL_X19_Y6_N30 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~2\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~2_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5) & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~8_combout\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~9_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5) & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~9_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~8_combout\)) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000011000000000000000000000000000000000000000011000100", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(0), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(5), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~9_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~8_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(4), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(3), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~2_combout\); + +-- Location: LABCELL_X17_Y4_N12 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~3\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~3_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ & ( ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~0_combout\) # +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0_combout\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111111111111000000000000000011111111111111010000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~2_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~0_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~0_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~3_combout\); + +-- Location: LABCELL_X17_Y4_N42 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~4\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~4_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~1_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~3_combout\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~1_combout\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~3_combout\ ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~1_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~3_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ & +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0))))) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~1_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~3_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0101010101010101010001000000010011111111111111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~0_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~19_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~1_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~3_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~4_combout\); + +-- Location: FF_X17_Y4_N43 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_WE_n\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~4_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_WE_n~q\); + +-- Location: LABCELL_X19_Y4_N48 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~5\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~5_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4_combout\ & +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4_combout\ ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000111100001111000011110000111100000101000000010000010100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~5_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~3_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~4_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~4_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~5_combout\); + +-- Location: LABCELL_X19_Y4_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~6\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~6_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & ( (((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\)) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000011111111011111111111111111111111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~6_combout\); + +-- Location: LABCELL_X19_Y6_N54 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~7\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~7_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE_q\ & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(1) & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(0))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000000001000000010000000100000001", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter[2]~DUPLICATE_q\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(1), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(0), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(3), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~7_combout\); + +-- Location: LABCELL_X19_Y6_N39 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~8\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~8_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3) +-- & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~8_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~9_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~8_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~7_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~8_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000010100000101000011110000111100000000000011000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~7_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(3), + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~8_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~9_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(4), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(5), + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~8_combout\); + +-- Location: LABCELL_X17_Y4_N27 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal2~0\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal2~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~0_combout\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4)) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000000000001111000000000000111100000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~0_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(4), + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal2~0_combout\); + +-- Location: LABCELL_X17_Y4_N6 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~9\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~9_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal2~0_combout\ & ( ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\ & +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal2~0_combout\ & ( +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal2~0_combout\ & ( +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~8_combout\)))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~6_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal2~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\) # +-- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~8_combout\))) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111000011000000111101011101010111000000110000001101010111010101", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~6_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~1_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~8_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~0_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal2~0_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~9_combout\); + +-- Location: LABCELL_X17_Y4_N36 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~10\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~10_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~5_combout\ +-- & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1_combout\)))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~9_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~5_combout\ & +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1_combout\)))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~9_combout\) ) ) ) # ( +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~5_combout\ & +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1_combout\)))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~9_combout\) ) ) ) # ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~9_combout\) # +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~5_combout\) ) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0011111100111111001111110001111100111111000111110011111100011111", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~1_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~5_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~9_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~1_combout\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~19_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~10_combout\); + +-- Location: FF_X17_Y4_N37 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_RAS_n\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~10_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_RAS_n~q\); + +-- Location: MLABCELL_X18_Y4_N18 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~11\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~11_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~2_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) & +-- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~2_combout\ & ( +-- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\)) ) ) +-- ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "0000000000000000000000000000110000000000000000000000001000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0), + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\, + datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~2_combout\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~11_combout\); + +-- Location: LABCELL_X17_Y4_N57 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~12\ : cyclonev_lcell_comb +-- Equation(s): +-- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~12_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~11_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\) # ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\) # +-- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~8_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\))) ) ) + +-- pragma translate_off +GENERIC MAP ( + extended_lut => "off", + lut_mask => "1111111011111111111111101111111100000000000000000000000000000000", + shared_arith => "off") +-- pragma translate_on +PORT MAP ( + dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~0_combout\, + datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\, + datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~8_combout\, + datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\, + dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~11_combout\, + combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~12_combout\); + +-- Location: FF_X17_Y4_N59 +\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_CAS_n\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\, + d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~12_combout\, + ena => \myVirtualToplevel|RESET_n~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_CAS_n~q\); + + +pll_reconfig_inst_tasks : altera_pll_reconfig_tasks +-- pragma translate_off +GENERIC MAP ( + number_of_fplls => 1); +-- pragma translate_on +END structure; + + diff --git a/zpu/build/simulation/modelsim/QMV_zpu_modelsim.xrf b/zpu/build/simulation/modelsim/QMV_zpu_modelsim.xrf new file mode 100644 index 0000000..aa3e69f --- /dev/null +++ b/zpu/build/simulation/modelsim/QMV_zpu_modelsim.xrf @@ -0,0 +1,22081 @@ +vendor_name = ModelSim +source_file = 1, QMV.cdf +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/QMV_zpu_Toplevel.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/Clock_50to100.qip +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/Clock_50to100.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/QMV_zpu_constraints.sdc +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/cpu/zpu_core_flex.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/cpu/zpu_pkg.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/cpu/zpu_core_small.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/cpu/zpu_core_medium.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/cpu/zpu_core_evo.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/cpu/zpu_core_evo_L2.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/cpu/zpu_uart_debug.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/zpu_soc_pkg.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/zpu_soc.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/RAM/dpram.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/uart/uart.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/intr/interrupt_controller.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/spi/spi.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/SDMMC/SDCard.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/ps2/io_ps2_com.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/timer/timer_controller.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/BRAM/BootROM.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/BRAM/DualPortBootBRAM.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/BRAM/SinglePortBootBRAM.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/BRAM/SinglePortBRAM.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/ioctl/ioctl.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/SDRAM/48LC16M16.qip +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/SDRAM/sdram.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/sysbus/SDRAM/48LC16M16.sdc +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/WishBone/I2C/i2c_master_top.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/WishBone/I2C/i2c_master_byte_ctrl.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/WishBone/I2C/i2c_master_bit_ctrl.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/WishBone/SDRAM/48LC16M16.qip +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/WishBone/SDRAM/wbsdram.vhd +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/devices/WishBone/SRAM/sram.vhd +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/vhdl/ieee/timing_b.vhd +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/vhdl/ieee/timing_p.vhd +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/altpll.tdf +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/aglobal171.inc +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/stratix_pll.inc +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/stratixii_pll.inc +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/cycloneii_pll.inc +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/cbx.lst +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/Clock_50to100_altpll.v +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/altsyncram.tdf +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/stratix_ram_block.inc +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/lpm_mux.inc +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/lpm_decode.inc +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/a_rdenreg.inc +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/altrom.inc +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/altram.inc +source_file = 1, /CAD/QuartusII/17.1/quartus/libraries/megafunctions/altdpram.inc +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/altsyncram_1jo1.tdf +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/altsyncram_d902.tdf +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/decode_5la.tdf +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/mux_lfb.tdf +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/altsyncram_e902.tdf +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/QMV_zpu.ram1_SinglePortBootBRAM_affed8c6.hdl.mif +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/altsyncram_f902.tdf +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/altsyncram_g902.tdf +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/altsyncram_o6q1.tdf +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/altsyncram_bnn1.tdf +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/QMV_zpu.ram0_evo_L2cache_a612c956.hdl.mif +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/altsyncram_cnn1.tdf +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/QMV_zpu.ram1_evo_L2cache_a612c956.hdl.mif +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/altsyncram_dnn1.tdf +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/QMV_zpu.ram2_evo_L2cache_a612c956.hdl.mif +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/altsyncram_enn1.tdf +source_file = 1, /srv/dvlp/Projects/dev/github/zpu/build/db/QMV_zpu.ram3_evo_L2cache_a612c956.hdl.mif +design_name = QMV_zpu +instance = comp, \UART_TX_1~output\, UART_TX_1~output, QMV_zpu, 1 +instance = comp, \SDRAM_CLK~output\, SDRAM_CLK~output, QMV_zpu, 1 +instance = comp, \UART_TX_0~output\, UART_TX_0~output, QMV_zpu, 1 +instance = comp, \SDCARD_MOSI[0]~output\, SDCARD_MOSI[0]~output, QMV_zpu, 1 +instance = comp, \SDCARD_CLK[0]~output\, SDCARD_CLK[0]~output, QMV_zpu, 1 +instance = comp, \SDCARD_CS[0]~output\, SDCARD_CS[0]~output, QMV_zpu, 1 +instance = comp, \SDRAM_ADDR[0]~output\, SDRAM_ADDR[0]~output, QMV_zpu, 1 +instance = comp, \SDRAM_ADDR[1]~output\, SDRAM_ADDR[1]~output, QMV_zpu, 1 +instance = comp, \SDRAM_ADDR[2]~output\, SDRAM_ADDR[2]~output, QMV_zpu, 1 +instance = comp, \SDRAM_ADDR[3]~output\, SDRAM_ADDR[3]~output, QMV_zpu, 1 +instance = comp, \SDRAM_ADDR[4]~output\, SDRAM_ADDR[4]~output, QMV_zpu, 1 +instance = comp, \SDRAM_ADDR[5]~output\, SDRAM_ADDR[5]~output, QMV_zpu, 1 +instance = comp, \SDRAM_ADDR[6]~output\, SDRAM_ADDR[6]~output, QMV_zpu, 1 +instance = comp, \SDRAM_ADDR[7]~output\, SDRAM_ADDR[7]~output, QMV_zpu, 1 +instance = comp, \SDRAM_ADDR[8]~output\, SDRAM_ADDR[8]~output, QMV_zpu, 1 +instance = comp, \SDRAM_ADDR[9]~output\, SDRAM_ADDR[9]~output, QMV_zpu, 1 +instance = comp, \SDRAM_ADDR[10]~output\, SDRAM_ADDR[10]~output, QMV_zpu, 1 +instance = comp, \SDRAM_ADDR[11]~output\, SDRAM_ADDR[11]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQM[0]~output\, SDRAM_DQM[0]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQM[1]~output\, SDRAM_DQM[1]~output, QMV_zpu, 1 +instance = comp, \SDRAM_BA[0]~output\, SDRAM_BA[0]~output, QMV_zpu, 1 +instance = comp, \SDRAM_BA[1]~output\, SDRAM_BA[1]~output, QMV_zpu, 1 +instance = comp, \SDRAM_WE~output\, SDRAM_WE~output, QMV_zpu, 1 +instance = comp, \SDRAM_RAS~output\, SDRAM_RAS~output, QMV_zpu, 1 +instance = comp, \SDRAM_CAS~output\, SDRAM_CAS~output, QMV_zpu, 1 +instance = comp, \LEDR~output\, LEDR~output, QMV_zpu, 1 +instance = comp, \SDRAM_CKE~output\, SDRAM_CKE~output, QMV_zpu, 1 +instance = comp, \SDRAM_CS~output\, SDRAM_CS~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[12]~output\, SDRAM_DQ[12]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[13]~output\, SDRAM_DQ[13]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[14]~output\, SDRAM_DQ[14]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[15]~output\, SDRAM_DQ[15]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[0]~output\, SDRAM_DQ[0]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[1]~output\, SDRAM_DQ[1]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[2]~output\, SDRAM_DQ[2]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[3]~output\, SDRAM_DQ[3]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[4]~output\, SDRAM_DQ[4]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[5]~output\, SDRAM_DQ[5]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[6]~output\, SDRAM_DQ[6]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[7]~output\, SDRAM_DQ[7]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[8]~output\, SDRAM_DQ[8]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[9]~output\, SDRAM_DQ[9]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[10]~output\, SDRAM_DQ[10]~output, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[11]~output\, SDRAM_DQ[11]~output, QMV_zpu, 1 +instance = comp, \CLOCK_50~input\, CLOCK_50~input, QMV_zpu, 1 +instance = comp, \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT\, mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT, QMV_zpu, 1 +instance = comp, \KEY~input\, KEY~input, QMV_zpu, 1 +instance = comp, \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL\, mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL, QMV_zpu, 1 +instance = comp, \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG\, mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG, QMV_zpu, 1 +instance = comp, \mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER\, mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER, QMV_zpu, 1 +instance = comp, \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0\, mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0, QMV_zpu, 1 +instance = comp, \mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER\, mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER, QMV_zpu, 1 +instance = comp, \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0\, mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0, QMV_zpu, 1 +instance = comp, \UART_RX_1~input\, UART_RX_1~input, QMV_zpu, 1 +instance = comp, \UART_RX_0~input\, UART_RX_0~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX~3\, myVirtualToplevel|RESET_COUNTER_RX~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[0]\, myVirtualToplevel|RESET_COUNTER_RX[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~13\, myVirtualToplevel|Add1~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~29\, myVirtualToplevel|Add1~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~33\, myVirtualToplevel|Add1~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~1\, myVirtualToplevel|Add1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX~0\, myVirtualToplevel|RESET_COUNTER_RX~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[9]\, myVirtualToplevel|RESET_COUNTER_RX[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~21\, myVirtualToplevel|Add1~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX~5\, myVirtualToplevel|RESET_COUNTER_RX~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[10]\, myVirtualToplevel|RESET_COUNTER_RX[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~37\, myVirtualToplevel|Add1~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[11]\, myVirtualToplevel|RESET_COUNTER_RX[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~17\, myVirtualToplevel|Add1~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX~4\, myVirtualToplevel|RESET_COUNTER_RX~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[12]\, myVirtualToplevel|RESET_COUNTER_RX[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~41\, myVirtualToplevel|Add1~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[13]\, myVirtualToplevel|RESET_COUNTER_RX[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~45\, myVirtualToplevel|Add1~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[14]\, myVirtualToplevel|RESET_COUNTER_RX[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~25\, myVirtualToplevel|Add1~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[15]\, myVirtualToplevel|RESET_COUNTER_RX[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal11~1\, myVirtualToplevel|Equal11~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal11~3\, myVirtualToplevel|Equal11~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal11~0\, myVirtualToplevel|Equal11~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[0]~6\, myVirtualToplevel|RESET_COUNTER_RX[0]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[1]\, myVirtualToplevel|RESET_COUNTER_RX[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~9\, myVirtualToplevel|Add1~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX~2\, myVirtualToplevel|RESET_COUNTER_RX~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[2]\, myVirtualToplevel|RESET_COUNTER_RX[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~49\, myVirtualToplevel|Add1~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[3]\, myVirtualToplevel|RESET_COUNTER_RX[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~5\, myVirtualToplevel|Add1~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX~1\, myVirtualToplevel|RESET_COUNTER_RX~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[4]\, myVirtualToplevel|RESET_COUNTER_RX[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~53\, myVirtualToplevel|Add1~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[5]\, myVirtualToplevel|RESET_COUNTER_RX[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~57\, myVirtualToplevel|Add1~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[6]\, myVirtualToplevel|RESET_COUNTER_RX[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add1~61\, myVirtualToplevel|Add1~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[7]\, myVirtualToplevel|RESET_COUNTER_RX[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER_RX[8]\, myVirtualToplevel|RESET_COUNTER_RX[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal11~2\, myVirtualToplevel|Equal11~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal11~4\, myVirtualToplevel|Equal11~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[0]~7\, myVirtualToplevel|RESET_COUNTER[0]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[0]\, myVirtualToplevel|RESET_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~62\, myVirtualToplevel|Add2~62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~25\, myVirtualToplevel|Add2~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[1]~6\, myVirtualToplevel|RESET_COUNTER[1]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[1]\, myVirtualToplevel|RESET_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~21\, myVirtualToplevel|Add2~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[2]~5\, myVirtualToplevel|RESET_COUNTER[2]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[2]\, myVirtualToplevel|RESET_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~17\, myVirtualToplevel|Add2~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[3]~4\, myVirtualToplevel|RESET_COUNTER[3]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[3]\, myVirtualToplevel|RESET_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~13\, myVirtualToplevel|Add2~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[4]~3\, myVirtualToplevel|RESET_COUNTER[4]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[4]\, myVirtualToplevel|RESET_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~9\, myVirtualToplevel|Add2~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[5]~2\, myVirtualToplevel|RESET_COUNTER[5]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[5]\, myVirtualToplevel|RESET_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~5\, myVirtualToplevel|Add2~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[6]~1\, myVirtualToplevel|RESET_COUNTER[6]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[6]\, myVirtualToplevel|RESET_COUNTER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal12~0\, myVirtualToplevel|Equal12~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~1\, myVirtualToplevel|Add2~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[7]~0\, myVirtualToplevel|RESET_COUNTER[7]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[7]\, myVirtualToplevel|RESET_COUNTER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal12~1\, myVirtualToplevel|Equal12~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~57\, myVirtualToplevel|Add2~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[8]~15\, myVirtualToplevel|RESET_COUNTER[8]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[8]\, myVirtualToplevel|RESET_COUNTER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~53\, myVirtualToplevel|Add2~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[9]~14\, myVirtualToplevel|RESET_COUNTER[9]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[9]\, myVirtualToplevel|RESET_COUNTER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~41\, myVirtualToplevel|Add2~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[10]~11\, myVirtualToplevel|RESET_COUNTER[10]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[10]\, myVirtualToplevel|RESET_COUNTER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~37\, myVirtualToplevel|Add2~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[11]~10\, myVirtualToplevel|RESET_COUNTER[11]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[11]\, myVirtualToplevel|RESET_COUNTER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~49\, myVirtualToplevel|Add2~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[12]~13\, myVirtualToplevel|RESET_COUNTER[12]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[12]\, myVirtualToplevel|RESET_COUNTER[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~45\, myVirtualToplevel|Add2~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[13]~12\, myVirtualToplevel|RESET_COUNTER[13]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[13]\, myVirtualToplevel|RESET_COUNTER[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal12~3\, myVirtualToplevel|Equal12~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~33\, myVirtualToplevel|Add2~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[14]~9\, myVirtualToplevel|RESET_COUNTER[14]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[14]\, myVirtualToplevel|RESET_COUNTER[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add2~29\, myVirtualToplevel|Add2~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[15]~8\, myVirtualToplevel|RESET_COUNTER[15]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_COUNTER[15]\, myVirtualToplevel|RESET_COUNTER[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal12~2\, myVirtualToplevel|Equal12~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_n~0\, myVirtualToplevel|RESET_n~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_n~feeder\, myVirtualToplevel|RESET_n~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RESET_n\, myVirtualToplevel|RESET_n, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~54\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpL2_0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~9\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add0~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~5\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add0~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~21\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add0~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[2]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[3]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~13\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add0~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[4]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~25\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add0~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[5]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~29\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add0~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[6]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~17\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add0~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[7]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~5\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add1~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~13\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add1~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]~4\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~21\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add1~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~17\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add1~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]~6\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~25\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add1~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]~8\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~9\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add1~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]~3\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~5\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add1~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal3~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdIsReady, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~45\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add2~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdBusy~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdBusy, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|process_0~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|process_0~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|process_0~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_NEW_REG989\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Write_NEW_REG989, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoReadIdx[0]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State~20\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle\, myVirtualToplevel|\ZPUEVO:ZPU0|state.State_Idle, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init\, myVirtualToplevel|\ZPUEVO:ZPU0|state.State_Init, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state~25\, myVirtualToplevel|\ZPUEVO:ZPU0|state~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|state.State_Init~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state~31\, myVirtualToplevel|\ZPUEVO:ZPU0|state~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|state.State_Idle~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1682~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[21]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1685~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1685~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1684~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1684~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1683~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1683~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1682~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC_StartAddr[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC_EndAddr[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC_EndAddr[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC_EndAddr[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC_EndAddr[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal137~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC_StartAddr[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1682~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1682~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[17]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1681~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1681~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1680~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1680~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1679~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1679~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~57\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]_NEW3310\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[23]_NEW3310, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~104\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~104, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~105\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~105, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.valid, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~4\, myVirtualToplevel|MEM_DATA_READ[2]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~19\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5]~165, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2\, myVirtualToplevel|\ZPUEVO:ZPU0|MEMXACT~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2IncAddr~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~1\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2IncAddr~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2IncAddr, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]_NEW3259\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[2]_NEW3259, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]_NEW3262\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[3]_NEW3262, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]_NEW3286\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[4]_NEW3286, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]_NEW3283\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[5]_NEW3283, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]_NEW3271\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[6]_NEW3271, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]_NEW3268\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[7]_NEW3268, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]_NEW3265\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[8]_NEW3265, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~89\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~93\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[23]~24_RESYN8923, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0\, myVirtualToplevel|\ZPUEVO:ZPU0|tInsnExec~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[23]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~100\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~100, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~99\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~99, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~1\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteHword~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1152\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1152, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|multResult[31]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector420~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0\, myVirtualToplevel|\ZPUEVO:ZPU0|divQuotientFractional~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|divQuotientFractional[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|divQuotientFractional[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0\, myVirtualToplevel|\ZPUEVO:ZPU0|divStart~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divStart~1\, myVirtualToplevel|\ZPUEVO:ZPU0|divStart~1, QMV_zpu, 1 +instance = comp, \~GND\, ~GND, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divStart\, myVirtualToplevel|\ZPUEVO:ZPU0|divStart, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0\, myVirtualToplevel|\ZPUEVO:ZPU0|process_0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|divQuotientFractional[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divComplete\, myVirtualToplevel|\ZPUEVO:ZPU0|divComplete, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[4]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|divQuotientFractional[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[0]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[1]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal157~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[2]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add59~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Add59~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[3]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal157~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[4]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add61~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Add61~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[5]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|bitCnt[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal157~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~1\, myVirtualToplevel|\ZPUEVO:ZPU0|divComplete~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|divComplete~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state~26\, myVirtualToplevel|\ZPUEVO:ZPU0|state~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state~27\, myVirtualToplevel|\ZPUEVO:ZPU0|state~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2\, myVirtualToplevel|\ZPUEVO:ZPU0|state.State_Div2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[15]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]_NEW3298\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[12]_NEW3298, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]_NEW3295\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[13]_NEW3295, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]_NEW3289\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[15]_NEW3289, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]_NEW3322\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[16]_NEW3322, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]_NEW3307\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[17]_NEW3307, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]_NEW3304\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[18]_NEW3304, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]_NEW1902\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[3]_NEW1902, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]_NEW1900\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[4]_NEW1900, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]_NEW1898\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[5]_NEW1898, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]_NEW1896\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[6]_NEW1896, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]_NEW1894\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[7]_NEW1894, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]_NEW1892\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[8]_NEW1892, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]_NEW1890\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[9]_NEW1890, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]_NEW1888\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[10]_NEW1888, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]_NEW1886\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[11]_NEW1886, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]_NEW1884\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[12]_NEW1884, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]_NEW1882\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[13]_NEW1882, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]_NEW1880\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[14]_NEW1880, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]_NEW1878\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[15]_NEW1878, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]_NEW1876\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[16]_NEW1876, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~93\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~89\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[17]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan25~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]_NEW1870\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[19]_NEW1870, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]_NEW1866\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[21]_NEW1866, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]_NEW1864\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[22]_NEW1864, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]_NEW1862\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[23]_NEW1862, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add17~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add17~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan13~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan25~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan13~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan13~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan13~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]_NEW1946\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[3]_NEW1946, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]_NEW1944\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[4]_NEW1944, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]_NEW1942\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[5]_NEW1942, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]_NEW1938\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[7]_NEW1938, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]_NEW1936\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[8]_NEW1936, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]_NEW1934\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[9]_NEW1934, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]_NEW1932\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[10]_NEW1932, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]_NEW1930\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[11]_NEW1930, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]_NEW1928\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[12]_NEW1928, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]_NEW1926\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[13]_NEW1926, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]_NEW1924\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[14]_NEW1924, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]_NEW1922\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[15]_NEW1922, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]_NEW1920\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[16]_NEW1920, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]_NEW1918\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[17]_NEW1918, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]_NEW1916\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[18]_NEW1916, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]_NEW1914\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[19]_NEW1914, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]_NEW1912\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[20]_NEW1912, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]_NEW1910\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[21]_NEW1910, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]_NEW1908\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[22]_NEW1908, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[2]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add18~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add18~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal136~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal136~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal136~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal136~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[11]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add16~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add16~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]_NEW1906\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[23]_NEW1906, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]_NEW2625\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[4]_NEW2625, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]_NEW2628\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[5]_NEW2628, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]_NEW2631\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[6]_NEW2631, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]_NEW2634\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[7]_NEW2634, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]_NEW2637\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[8]_NEW2637, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]_NEW2640\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[9]_NEW2640, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]_NEW2643\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[10]_NEW2643, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]_NEW2646\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[11]_NEW2646, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]_NEW2649\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[12]_NEW2649, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]_NEW2652\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[13]_NEW2652, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]_NEW2655\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[14]_NEW2655, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]_NEW2658\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[15]_NEW2658, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]_NEW2661\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[16]_NEW2661, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]_NEW2667\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[18]_NEW2667, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]_NEW2670\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[19]_NEW2670, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]_NEW2673\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[20]_NEW2673, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]_NEW2676\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[21]_NEW2676, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~94\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~94, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~90\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~90, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]_NEW2679\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[22]_NEW2679, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add8~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add8~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~10\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~18\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan7~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~4\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~10\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan6~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add0~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_RESYN12370\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal1~0_RESYN12370, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal1~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal1~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add9~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add9~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]_NEW2682\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[23]_NEW2682, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_RESYN12470\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~19_RESYN12470, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHE_LEVEL1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~16_RESYN12688, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~5\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~6\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHE_LEVEL1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add15~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add15~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]_NEW1874\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[17]_NEW1874, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]_NEW1872\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[18]_NEW1872, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add11~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~22_RESYN12704, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_RESYN12706\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~23_RESYN12706, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder4~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal136~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal136~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~5\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHE_LEVEL1~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal136~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal136~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~11_RESYN8423, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHE_LEVEL1~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHE_LEVEL1~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1352~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state~30\, myVirtualToplevel|\ZPUEVO:ZPU0|state~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2\, myVirtualToplevel|\ZPUEVO:ZPU0|state.State_Mult2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1352~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1243~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder4~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[2]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_NEW_REG755\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[1]_NEW_REG755, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoReadIdx[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_NEW_REG1486\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_NEW_REG1486, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1243~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1243~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~2_RESYN12622, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~263\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][3]~263, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal1~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[11]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG686\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG686, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1430\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1430, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder4~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[23]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector765~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag\, myVirtualToplevel|\ZPUEVO:ZPU0|idimFlag, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector505~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[18]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder8~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[23]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector973~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1346~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~6_RESYN8775, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~6_RESYN8777, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~4\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~16_RESYN9145, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~16_RESYN9147, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~1\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1Invalid~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~2\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1Invalid~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~15\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1Invalid~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1Invalid~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan14~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1Invalid~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~5\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Invalid~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Invalid~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Invalid~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~16_RESYN8771, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~16_RESYN8773, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~12\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~6_RESYN8767, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~6_RESYN8769, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan15~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~8_RESYN12618, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~4\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan0~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Invalid~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~0_RESYN8959, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[23]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG939\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG939, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1001\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1001, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder8~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder10~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr165\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr165, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector508~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector508~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector386~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1006~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector508~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector508~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector706~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder10~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector706~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~19\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector508~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector508~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~20\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[18]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~22\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1005\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1005, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1007\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1007, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG999\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG999, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector574~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder9~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder8~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector574~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector574~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~16\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_NEW_REG1023\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_NEW_REG1023, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_NEW_REG1025\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_NEW_REG1025, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_NEW_REG1021\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_NEW_REG1021, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector505~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector640~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[22]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector640~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1128\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1128, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1126\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1126, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1122\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1122, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1124\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1124, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG959\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG959, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~8\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG963\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG963, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder8~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector508~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[23]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector508~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~7\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG961\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG961, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG955\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG955, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG957\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG957, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~3_RTM0967\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~3_RTM0967, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG965\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG965, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux10~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder8~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~7\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1045\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1045, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1041\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1041, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder8~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector904~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder9~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[26]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector904~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~6\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1043\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1043, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~1_RTM01049\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~1_RTM01049, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1047\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1047, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder8~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder8~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_NEW_REG1150\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_NEW_REG1150, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector772~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[18]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector772~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~6\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_NEW_REG1148\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_NEW_REG1148, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1003\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1003, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_NEW_REG1146\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_NEW_REG1146, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector838~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector838~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[26]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1166\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1166, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1162\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1162, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1164\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1164, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1160\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1160, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1031\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1031, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~1_RTM01039\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~1_RTM01039, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1037\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1037, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1027\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1027, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[28]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector970~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector970~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1033\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1033, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~6\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1035\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1035, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1029\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1029, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux10~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux10~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG941\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG941, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG943\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG943, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1095\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1095, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1093\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1093, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder9~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector769~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector765~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector505~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector769~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector505~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector769~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector769~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector765~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector973~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector505~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1097\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1097, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector967~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector967~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector967~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector967~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder9~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector963~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG951\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG951, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG953\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG953, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG949\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG949, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1057\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1057, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector901~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector901~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector897~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector901~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector901~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1061\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1061, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1059\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1059, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1017\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1017, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector835~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector835~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder9~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector831~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector835~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector835~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector835~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1019\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1019, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1015\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1015, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux7~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG973\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG973, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG971\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG971, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector703~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector703~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector703~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector703~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder9~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector699~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG975\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG975, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1011\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1011, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1009\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1009, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder9~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector501~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector505~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector505~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector505~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector505~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1013\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1013, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector637~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector637~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder9~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector633~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector637~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector637~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector637~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1067\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1067, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1063\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1063, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_WRITE[7]~1\, myVirtualToplevel|SD_DATA_WRITE[7]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoReadIdx[2]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[18]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[16]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[23]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[18]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[0]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan25~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan16~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan16~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder4~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~297\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][1]~297, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2, QMV_zpu, 1 +instance = comp, \SDCARD_MISO[0]~input\, SDCARD_MISO[0]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|hndShk_r, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[0]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector21~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~6\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~13\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add0~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~25\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add0~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v~9\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[1]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add0~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector20~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector20~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[2]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]~7\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector19~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector19~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[3]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]~3\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add0~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector18~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector18~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[4]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]~8\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]~6\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[1]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]~5\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[2]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[3]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]~7\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[4]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]~3\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[5]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]~4\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[6]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]~8\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[7]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal6~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal6~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add3~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE\, myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector14~0\, myVirtualToplevel|Selector14~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector15~8\, myVirtualToplevel|Selector15~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2\, myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector14~1\, myVirtualToplevel|Selector14~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector14~2\, myVirtualToplevel|Selector14~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1\, myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_STATE.SD_STATE_READ_2\, myVirtualToplevel|SD_STATE.SD_STATE_READ_2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE\, myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector15~0\, myVirtualToplevel|Selector15~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector15~6\, myVirtualToplevel|Selector15~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector11~2\, myVirtualToplevel|Selector11~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_STATE.SD_STATE_RESET\, myVirtualToplevel|SD_STATE.SD_STATE_RESET, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector12~1\, myVirtualToplevel|Selector12~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1\, myVirtualToplevel|SD_STATE.SD_STATE_RESET_1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER~5\, myVirtualToplevel|SD_RESET_TIMER~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE\, myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector3~0\, myVirtualToplevel|Selector3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER[0]\, myVirtualToplevel|SD_RESET_TIMER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add0~25\, myVirtualToplevel|Add0~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add0~17\, myVirtualToplevel|Add0~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector8~0\, myVirtualToplevel|Selector8~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER[3]~3\, myVirtualToplevel|SD_RESET_TIMER[3]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER[1]\, myVirtualToplevel|SD_RESET_TIMER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add0~9\, myVirtualToplevel|Add0~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER~2\, myVirtualToplevel|SD_RESET_TIMER~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER[2]\, myVirtualToplevel|SD_RESET_TIMER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE\, myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add0~13\, myVirtualToplevel|Add0~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector6~0\, myVirtualToplevel|Selector6~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE\, myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add0~5\, myVirtualToplevel|Add0~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER~1\, myVirtualToplevel|SD_RESET_TIMER~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER[4]\, myVirtualToplevel|SD_RESET_TIMER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add0~21\, myVirtualToplevel|Add0~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER~4\, myVirtualToplevel|SD_RESET_TIMER~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER[5]\, myVirtualToplevel|SD_RESET_TIMER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add0~1\, myVirtualToplevel|Add0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER~0\, myVirtualToplevel|SD_RESET_TIMER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER[6]\, myVirtualToplevel|SD_RESET_TIMER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET_TIMER[3]\, myVirtualToplevel|SD_RESET_TIMER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal8~0\, myVirtualToplevel|Equal8~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal8~1\, myVirtualToplevel|Equal8~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector15~7\, myVirtualToplevel|Selector15~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector18~0\, myVirtualToplevel|Selector18~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE\, myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector15~3\, myVirtualToplevel|Selector15~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector15~4\, myVirtualToplevel|Selector15~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector15~5\, myVirtualToplevel|Selector15~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector10~0\, myVirtualToplevel|Selector10~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_STATE.SD_STATE_IDLE\, myVirtualToplevel|SD_STATE.SD_STATE_IDLE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector2~0\, myVirtualToplevel|Selector2~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RD[0]\, myVirtualToplevel|SD_RD[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RD[0]~_wirecell\, myVirtualToplevel|SD_RD[0]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~5\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add3~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~13\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add3~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~17\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add3~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[3]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~21\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add3~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~25\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add3~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[5]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~29\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add3~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[6]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~33\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add3~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[7]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~37\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add3~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[8]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~9\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add3~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[1]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal4~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~62\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~64, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal2~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|mosi_o~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~57\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~76, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~78, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~75, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~79\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~79, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~60\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~87\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~87, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~80, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~82\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~82, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~55\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~56\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~74\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~74, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|WideOr40~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector160~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector160~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|doDeselect_v, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~66, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~72, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~73\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector110~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector67~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector68~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~40\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~89\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector70~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector68~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|WideOr13~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|mosi_o~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclk_r, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector64~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector66~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add4~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add4~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector68~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector66~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[5]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add4~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector65~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector65~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[6]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector71~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector71~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector110~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector71~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]~8\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add4~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector64~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector64~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[7]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector70~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector87~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector70~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector70~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~17\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add4~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add4~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector70~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~5\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector70~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[1]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal12~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add4~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector69~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~6\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add4~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector68~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~3\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector68~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[3]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector67~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[4]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal12~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal12~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~63, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~65\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rx_v[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~70, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|WideOr34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~54\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~71\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~71, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|busy_o~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|busy_o, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector1~0\, myVirtualToplevel|Selector1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_WR[0]\, myVirtualToplevel|SD_WR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~61\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~88\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~88, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~84, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~86\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~86, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~52\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~69\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector159~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector159~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add0~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector17~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector17~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[5]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]~4\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Add0~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector16~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector16~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[6]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]~5\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal0~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~46\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~60\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector29~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector29~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~3\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector29~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~50\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~67, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~68\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~68, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~49\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~57\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~44\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~61\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector29~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~46\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~54\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~55\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector15~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector15~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[0]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[16]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_NEW_REG785\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[16]_NEW_REG785, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG504\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG504, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_NEW_REG781\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[16]_NEW_REG781, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector18~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector18~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1434\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1434, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~54\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1211~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector634~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_RESYN12644\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector766~5_RESYN12644, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector766~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector766~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector386~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector634~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector634~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector363~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1006~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr171~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1006~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1006~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid_NEW3341\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.valid_NEW3341, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.valid~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[1]~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector502~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector700~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector700~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector571~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector568~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux4~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector766~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector765~5_RESYN12640, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector765~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector898~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector898~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector898~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector964~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector964~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector964~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux4~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux4~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~53\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~55\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[7]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux74~0\, myVirtualToplevel|Mux74~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_NEW_REG1404\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_NEW_REG1404, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_NEW_REG1402\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_NEW_REG1402, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector768~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector768~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector768~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector636~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector636~2_RESYN12428, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector636~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_NEW_REG1406\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_NEW_REG1406, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector570~2_RESYN12434, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector570~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector567~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector570~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_NEW_REG1360\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_NEW_REG1360, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_NEW_REG1362\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_NEW_REG1362, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_NEW_REG1358\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_NEW_REG1358, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector504~2_RESYN12432, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector504~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector504~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_NEW_REG1366\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_NEW_REG1366, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_NEW_REG1292\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_NEW_REG1292, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_NEW_REG1364\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_NEW_REG1364, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_NEW_REG1368\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_NEW_REG1368, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_NEW_REG1284\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_NEW_REG1284, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_NEW_REG1286\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_NEW_REG1286, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector702~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector702~2_RESYN12430, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector702~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector702~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_NEW_REG1288\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_NEW_REG1288, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux6~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1055\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1055, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_NEW_REG1370\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_NEW_REG1370, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector900~2_RESYN12424, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector900~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector900~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_NEW_REG1372\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_NEW_REG1372, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_NEW_REG1620\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_NEW_REG1620, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_NEW_REG1622\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_NEW_REG1622, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector768~5_RESYN12420, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector768~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector768~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_NEW_REG1624\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_NEW_REG1624, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG985\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG985, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector966~2_RESYN12426, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector966~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector966~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector966~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_NEW_REG1294\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_NEW_REG1294, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_NEW_REG1290\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_NEW_REG1290, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector834~2_RESYN12422, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector834~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector834~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_NEW_REG1450\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_NEW_REG1450, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_NEW_REG1452\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_NEW_REG1452, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_NEW_REG1448\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_NEW_REG1448, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux6~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux6~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~60\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~59\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~61\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector6~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector6~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[9]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[25]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1243~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~3\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_NEW_REG8\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_NEW_REG8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux110~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux110~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[0]~input\, SDRAM_DQ[0]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_NEW_REG10\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_NEW_REG10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[10]~2\, myVirtualToplevel|MEM_DATA_READ[10]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[0]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]_NEW3177\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[10]_NEW3177, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[26]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[26]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[0]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]_NEW3049\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[10]_NEW3049, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[28]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[28]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]_NEW2985\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[10]_NEW2985, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[0]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]_NEW3113\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[10]_NEW3113, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux95~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]_NEW2793\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[10]_NEW2793, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]_NEW2857\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[10]_NEW2857, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[22]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[22]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]_NEW2729\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[10]_NEW2729, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[23]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[23]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]_NEW2921\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[10]_NEW2921, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux95~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux95~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal7~0\, myVirtualToplevel|UART1|Equal7~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]_NEW2925\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[15]_NEW2925, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]_NEW2733\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[15]_NEW2733, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]_NEW2861\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[15]_NEW2861, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]_NEW2797\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[15]_NEW2797, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux90~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]_NEW3117\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[15]_NEW3117, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]_NEW3181\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[15]_NEW3181, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]_NEW2989\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[15]_NEW2989, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]_NEW3053\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[15]_NEW3053, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux90~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux90~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][15]~feeder\, myVirtualToplevel|SD_ADDR[0][15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][15]\, myVirtualToplevel|SD_ADDR[0][15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux68~0\, myVirtualToplevel|Mux68~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_READ_ENABLE~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_READ_ENABLE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_READ_ENABLE~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~1\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_READ_ENABLE~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_READ_ENABLE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[31]~0\, myVirtualToplevel|IO_DATA_READ_SD[31]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[15]\, myVirtualToplevel|IO_DATA_READ_SD[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_NEW_REG1408\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[8]_NEW_REG1408, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[7]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[7]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector351~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_NEW_REG40\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_NEW_REG40, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[7]~input\, SDRAM_DQ[7]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_NEW_REG42\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_NEW_REG42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector215~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector215~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~42\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[23]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[23]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[23]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~43\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[4]~44\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[4]~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~45\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux94~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux94~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_NEW_REG12\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_NEW_REG12, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[13]~input\, SDRAM_DQ[13]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_NEW_REG88\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_NEW_REG88, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_NEW_REG86\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_NEW_REG86, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[2]~input\, SDRAM_DQ[2]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_NEW_REG32\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_NEW_REG32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_NEW_REG64\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_NEW_REG64, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector13~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector13~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[18]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_NEW_REG921\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[18]_NEW_REG921, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[10]~input\, SDRAM_DQ[10]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_NEW_REG24\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_NEW_REG24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_NEW_REG22\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_NEW_REG22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1678~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1678~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1677~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1677~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[22]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1676~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1676~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_NEW_REG893\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[23]_NEW_REG893, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_NEW_REG891\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[23]_NEW_REG891, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_NEW_REG1176\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[22]_NEW_REG1176, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[25]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~29\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[7]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_NEW_REG552\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[7]_NEW_REG552, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~28\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[7]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_NEW_REG550\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[7]_NEW_REG550, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_NEW_REG548\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[7]_NEW_REG548, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG508\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG508, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux75~0\, myVirtualToplevel|Mux75~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1324~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1324~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1331~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1Invalid~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_RESYN12624\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~1_RESYN12624, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~5\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_RESYN12628\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~7_RESYN12628, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|multResult[31]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG4\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG4, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[1]~input\, SDRAM_DQ[1]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG6\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_ENABLE_FIFO~0\, myVirtualToplevel|UART0|RX_ENABLE_FIFO~0, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[5]~input\, SDRAM_DQ[5]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_NEW_REG56\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_NEW_REG56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_NEW_REG74\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_NEW_REG74, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state~22\, myVirtualToplevel|\ZPUEVO:ZPU0|state~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector499~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1072~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~48\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~49\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~50\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[9]~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_NEW_REG1330\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[8]_NEW_REG1330, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[29]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_NEW_REG751\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[24]_NEW_REG751, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_NEW_REG1332\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[8]_NEW_REG1332, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_NEW_REG1328\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[8]_NEW_REG1328, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[8]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[0]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[0]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~33\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[9]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_NEW_REG540\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[9]_NEW_REG540, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_NEW_REG536\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[9]_NEW_REG536, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1526\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1526, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~41\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[9]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1532\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1532, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1528\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1528, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1074~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1074~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1530\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1530, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[9]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[23]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[23]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~37\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[9]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1542\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1542, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1536\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1536, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[23]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1540\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1540, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[23]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1350~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[23]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[23]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[23]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1538\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1538, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[9]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1378\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1378, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1382\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1382, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~42\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[9]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1384\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1384, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1380\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1380, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[9]~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1560\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1560, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~40\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[9]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1566\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1566, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1564\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1564, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1562\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1562, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[9]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux40~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1256\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1256, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~41\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[9]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1258\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1258, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1250\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1250, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1252\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1252, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1254\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1254, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[9]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~40\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[9]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1426\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1426, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1420\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1420, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1422\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1422, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1424\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1424, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[9]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1276\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1276, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~44\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[9]~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1282\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1282, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1278\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1278, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1280\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1280, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[9]~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~38\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[9]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1476\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1476, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1470\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1470, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1474\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1474, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1472\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1472, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[9]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux40~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux40~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~32\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[9]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_NEW_REG538\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[9]_NEW_REG538, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~35\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[10]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_NEW_REG534\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[10]_NEW_REG534, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_NEW_REG530\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[10]_NEW_REG530, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1073~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[10]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~43\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[10]~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[10]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~41\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[10]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[10]~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~47\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[10]~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[10]~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~44\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[10]~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux39~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[10]~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~44\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[10]~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[10]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~40\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[10]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[10]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~43\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[10]~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[10]~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~45\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[10]~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux39~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux39~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~34\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[10]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_NEW_REG532\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[10]_NEW_REG532, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]_NEW3047\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[11]_NEW3047, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]_NEW3175\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[11]_NEW3175, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]_NEW3111\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[11]_NEW3111, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]_NEW2983\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[11]_NEW2983, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux94~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]_NEW2919\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[11]_NEW2919, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]_NEW2791\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[11]_NEW2791, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]_NEW2727\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[11]_NEW2727, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]_NEW2855\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[11]_NEW2855, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux94~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux94~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][11]~feeder\, myVirtualToplevel|SD_ADDR[0][11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][11]\, myVirtualToplevel|SD_ADDR[0][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux72~0\, myVirtualToplevel|Mux72~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[11]\, myVirtualToplevel|IO_DATA_READ_SD[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteByte~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~0\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_WRITE_BYTE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_WRITE_BYTE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~0\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_WRITE_HWORD~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_WRITE_HWORD, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG2, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[3]~input\, SDRAM_DQ[3]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_NEW_REG36\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_NEW_REG36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_NEW_REG34\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_NEW_REG34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1079~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[4]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~34\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[4]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[4]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~37\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[4]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[4]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~38\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[4]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[4]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~39\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[4]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux45~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[4]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~41\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[4]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[4]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~38\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[4]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[4]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~37\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[4]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[4]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~35\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[4]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux45~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux45~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector212~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector212~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1078~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[5]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~36\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[5]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[5]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~39\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[5]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[5]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~40\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[5]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[5]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~41\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[5]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux44~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[5]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~39\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[5]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[5]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~43\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[5]~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[5]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~37\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[5]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[5]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~40\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[5]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux44~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux44~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector211~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector211~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1071~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[12]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~29\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[12]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[12]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~31\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[12]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[12]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[12]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[12]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~30\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[12]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux37~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[12]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~33\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[12]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[12]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~29\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[12]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[12]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~30\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[12]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[12]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~27\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[12]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux37~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux37~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector204~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector204~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]_NEW3328\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[12]_NEW3328, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1069~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~33\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[14]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~35\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[14]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[14]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~34\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[14]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[14]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~30\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[14]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux35~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[14]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~31\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[14]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[14]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~33\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[14]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[14]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~37\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[14]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[14]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~34\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[14]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux35~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux35~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1070~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]_NEW2979\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[13]_NEW2979, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]_NEW3171\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[13]_NEW3171, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]_NEW3043\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[13]_NEW3043, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]_NEW3107\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[13]_NEW3107, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux92~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]_NEW2851\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[13]_NEW2851, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]_NEW2723\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[13]_NEW2723, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]_NEW2915\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[13]_NEW2915, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]_NEW2787\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[13]_NEW2787, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux92~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux92~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][13]~feeder\, myVirtualToplevel|SD_ADDR[0][13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][13]\, myVirtualToplevel|SD_ADDR[0][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux70~0\, myVirtualToplevel|Mux70~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[13]\, myVirtualToplevel|IO_DATA_READ_SD[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_NEW_REG54\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_NEW_REG54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[16]~0\, myVirtualToplevel|INT_ENABLE[16]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[5]\, myVirtualToplevel|INT_ENABLE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0\, myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[5]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add4~33\, myVirtualToplevel|Add4~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add3~17\, myVirtualToplevel|Add3~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1\, myVirtualToplevel|MICROSEC_DOWN_COUNTER~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Mux0~0\, myVirtualToplevel|UART1|Mux0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_TICK_HALT~0\, myVirtualToplevel|RTC_TICK_HALT~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_TICK_HALT\, myVirtualToplevel|RTC_TICK_HALT, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0\, myVirtualToplevel|RTC_MICROSEC_TICK[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1\, myVirtualToplevel|RTC_MICROSEC_TICK[1]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_TICK[0]\, myVirtualToplevel|RTC_MICROSEC_TICK[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add3~1\, myVirtualToplevel|Add3~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_TICK[1]\, myVirtualToplevel|RTC_MICROSEC_TICK[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add3~21\, myVirtualToplevel|Add3~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_TICK[2]\, myVirtualToplevel|RTC_MICROSEC_TICK[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add3~5\, myVirtualToplevel|Add3~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_TICK[3]\, myVirtualToplevel|RTC_MICROSEC_TICK[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add3~9\, myVirtualToplevel|Add3~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_TICK[4]\, myVirtualToplevel|RTC_MICROSEC_TICK[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add3~25\, myVirtualToplevel|Add3~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_TICK[5]\, myVirtualToplevel|RTC_MICROSEC_TICK[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add3~29\, myVirtualToplevel|Add3~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_TICK[6]\, myVirtualToplevel|RTC_MICROSEC_TICK[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add3~13\, myVirtualToplevel|Add3~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_TICK[7]\, myVirtualToplevel|RTC_MICROSEC_TICK[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal13~0\, myVirtualToplevel|Equal13~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal13~1\, myVirtualToplevel|Equal13~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER~0\, myVirtualToplevel|RTC_MILLISEC_COUNTER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3\, myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[2]~DUPLICATE\, myVirtualToplevel|RTC_MICROSEC_COUNTER[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~1\, myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add4~5\, myVirtualToplevel|Add4~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add4~13\, myVirtualToplevel|Add4~13, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[6]~input\, SDRAM_DQ[6]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_NEW_REG46\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_NEW_REG46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_NEW_REG44\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_NEW_REG44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[6]\, myVirtualToplevel|INT_ENABLE[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[6]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal4~0_RESYN12606\, myVirtualToplevel|Equal4~0_RESYN12606, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal4~0\, myVirtualToplevel|Equal4~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1_CS\, myVirtualToplevel|UART1_CS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_ENABLE~0\, myVirtualToplevel|UART1|RX_ENABLE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_ENABLE~0\, myVirtualToplevel|UART1|TX_ENABLE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_ENABLE\, myVirtualToplevel|UART1|RX_ENABLE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_RESET~0\, myVirtualToplevel|UART1|RX_RESET~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_RESET\, myVirtualToplevel|UART1|RX_RESET, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[0]~1\, myVirtualToplevel|UART1|RX_DATA[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RXD_SYNC2\, myVirtualToplevel|UART1|RXD_SYNC2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RXD_SYNC\, myVirtualToplevel|UART1|RXD_SYNC, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Selector4~0\, myVirtualToplevel|UART1|Selector4~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_STATE.start~DUPLICATE\, myVirtualToplevel|UART1|RX_STATE.start~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_BUFFER[1]~0\, myVirtualToplevel|UART1|RX_BUFFER[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_BUFFER[8]\, myVirtualToplevel|UART1|RX_BUFFER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Selector5~0\, myVirtualToplevel|UART1|Selector5~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE\, myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Selector6~0\, myVirtualToplevel|UART1|Selector6~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_BUFFER[6]\, myVirtualToplevel|UART1|RX_BUFFER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Selector7~0\, myVirtualToplevel|UART1|Selector7~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_BUFFER[5]\, myVirtualToplevel|UART1|RX_BUFFER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Selector8~0\, myVirtualToplevel|UART1|Selector8~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_BUFFER[4]\, myVirtualToplevel|UART1|RX_BUFFER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Selector9~0\, myVirtualToplevel|UART1|Selector9~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_BUFFER[3]\, myVirtualToplevel|UART1|RX_BUFFER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Selector10~0\, myVirtualToplevel|UART1|Selector10~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_BUFFER[2]\, myVirtualToplevel|UART1|RX_BUFFER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Selector11~0\, myVirtualToplevel|UART1|Selector11~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_BUFFER[1]\, myVirtualToplevel|UART1|RX_BUFFER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Selector12~0\, myVirtualToplevel|UART1|Selector12~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_BUFFER[0]\, myVirtualToplevel|UART1|RX_BUFFER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_STATE.bits~0\, myVirtualToplevel|UART1|RX_STATE.bits~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_STATE.bits\, myVirtualToplevel|UART1|RX_STATE.bits, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_STATE.stop~2\, myVirtualToplevel|UART1|RX_STATE.stop~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_STATE.start~0\, myVirtualToplevel|UART1|RX_STATE.start~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_STATE.start\, myVirtualToplevel|UART1|RX_STATE.start, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_STATE.idle~0\, myVirtualToplevel|UART1|RX_STATE.idle~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_STATE.idle\, myVirtualToplevel|UART1|RX_STATE.idle, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]_NEW2721\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[14]_NEW2721, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]_NEW2849\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[14]_NEW2849, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]_NEW2785\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[14]_NEW2785, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]_NEW2913\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[14]_NEW2913, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux91~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]_NEW2977\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[14]_NEW2977, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]_NEW3041\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[14]_NEW3041, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]_NEW3105\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[14]_NEW3105, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]_NEW3169\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[14]_NEW3169, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux91~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux91~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[14]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[0]~1\, myVirtualToplevel|UART1|RX_COUNTER[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[13]\, myVirtualToplevel|UART1|RX_COUNTER[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]_NEW3173\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[12]_NEW3173, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]_NEW3109\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[12]_NEW3109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]_NEW2981\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[12]_NEW2981, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]_NEW3045\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[12]_NEW3045, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux93~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]_NEW2725\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[12]_NEW2725, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]_NEW2789\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[12]_NEW2789, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]_NEW2917\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[12]_NEW2917, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]_NEW2853\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[12]_NEW2853, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux93~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux93~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[12]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[11]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~0\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~4\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~1\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[1]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]~5\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~15\, myVirtualToplevel|UART1|RX_COUNTER~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[0]\, myVirtualToplevel|UART1|RX_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~53\, myVirtualToplevel|UART1|Add1~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~17\, myVirtualToplevel|UART1|Add1~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~6\, myVirtualToplevel|UART1|RX_COUNTER~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~_wirecell\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[1]\, myVirtualToplevel|UART1|RX_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~21\, myVirtualToplevel|UART1|Add1~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~7\, myVirtualToplevel|UART1|RX_COUNTER~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~2\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~_wirecell\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[2]\, myVirtualToplevel|UART1|RX_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~25\, myVirtualToplevel|UART1|Add1~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~8\, myVirtualToplevel|UART1|RX_COUNTER~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~3\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~_wirecell\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[3]\, myVirtualToplevel|UART1|RX_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~29\, myVirtualToplevel|UART1|Add1~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~9\, myVirtualToplevel|UART1|RX_COUNTER~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~_wirecell\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[4]\, myVirtualToplevel|UART1|RX_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~33\, myVirtualToplevel|UART1|Add1~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~10\, myVirtualToplevel|UART1|RX_COUNTER~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[6]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[5]\, myVirtualToplevel|UART1|RX_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~37\, myVirtualToplevel|UART1|Add1~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~11\, myVirtualToplevel|UART1|RX_COUNTER~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[7]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[6]\, myVirtualToplevel|UART1|RX_COUNTER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~1\, myVirtualToplevel|UART1|Add1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~2\, myVirtualToplevel|UART1|RX_COUNTER~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]~feeder\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE\, myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~5\, myVirtualToplevel|UART1|Add1~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~3\, myVirtualToplevel|UART1|RX_COUNTER~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[9]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[8]\, myVirtualToplevel|UART1|RX_COUNTER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~9\, myVirtualToplevel|UART1|Add1~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~4\, myVirtualToplevel|UART1|RX_COUNTER~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~_wirecell\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[9]\, myVirtualToplevel|UART1|RX_COUNTER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~13\, myVirtualToplevel|UART1|Add1~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~5\, myVirtualToplevel|UART1|RX_COUNTER~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE\, myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~41\, myVirtualToplevel|UART1|Add1~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~12\, myVirtualToplevel|UART1|RX_COUNTER~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[11]\, myVirtualToplevel|UART1|RX_COUNTER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~45\, myVirtualToplevel|UART1|Add1~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~13\, myVirtualToplevel|UART1|RX_COUNTER~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[13]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[12]\, myVirtualToplevel|UART1|RX_COUNTER[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~57\, myVirtualToplevel|UART1|Add1~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~16\, myVirtualToplevel|UART1|RX_COUNTER~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[13]~DUPLICATE\, myVirtualToplevel|UART1|RX_COUNTER[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[15]\, myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE\, myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~61\, myVirtualToplevel|UART1|Add1~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~17\, myVirtualToplevel|UART1|RX_COUNTER~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[14]\, myVirtualToplevel|UART1|RX_COUNTER[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[0]~DUPLICATE\, myVirtualToplevel|UART1|RX_COUNTER[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add1~49\, myVirtualToplevel|UART1|Add1~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER~14\, myVirtualToplevel|UART1|RX_COUNTER~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[15]\, myVirtualToplevel|UART1|RX_COUNTER[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal1~3\, myVirtualToplevel|UART1|Equal1~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal1~1\, myVirtualToplevel|UART1|Equal1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal1~2\, myVirtualToplevel|UART1|Equal1~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[7]\, myVirtualToplevel|UART1|RX_COUNTER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_COUNTER[10]\, myVirtualToplevel|UART1|RX_COUNTER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal1~0\, myVirtualToplevel|UART1|Equal1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal1~4\, myVirtualToplevel|UART1|Equal1~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK~0\, myVirtualToplevel|UART1|RX_CLOCK~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_CLOCK\, myVirtualToplevel|UART1|RX_CLOCK, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_STATE.stop~0\, myVirtualToplevel|UART1|RX_STATE.stop~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_STATE.stop~1\, myVirtualToplevel|UART1|RX_STATE.stop~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_STATE.stop\, myVirtualToplevel|UART1|RX_STATE.stop, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_INTR~0\, myVirtualToplevel|UART1|RX_INTR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_ENABLE_FIFO~0\, myVirtualToplevel|UART1|RX_ENABLE_FIFO~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_ENABLE_FIFO\, myVirtualToplevel|UART1|RX_ENABLE_FIFO, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~1\, myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add3~5\, myVirtualToplevel|UART1|Add3~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA_READY~0\, myVirtualToplevel|UART1|RX_DATA_READY~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA_READY~1\, myVirtualToplevel|UART1|RX_DATA_READY~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA_READY\, myVirtualToplevel|UART1|RX_DATA_READY, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|process_3~0\, myVirtualToplevel|UART1|process_3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add4~9\, myVirtualToplevel|UART1|Add4~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add4~1\, myVirtualToplevel|UART1|Add4~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]\, myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add4~21\, myVirtualToplevel|UART1|Add4~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]\, myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add4~17\, myVirtualToplevel|UART1|Add4~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[6]\, myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add3~25\, myVirtualToplevel|UART1|Add3~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add3~21\, myVirtualToplevel|UART1|Add3~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[6]\, myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal2~2\, myVirtualToplevel|UART1|Equal2~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add4~5\, myVirtualToplevel|UART1|Add4~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[1]\, myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE\, myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal2~0\, myVirtualToplevel|UART1|Equal2~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add3~29\, myVirtualToplevel|UART1|Add3~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[7]\, myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add4~25\, myVirtualToplevel|UART1|Add4~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[7]\, myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal2~3\, myVirtualToplevel|UART1|Equal2~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0\, myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]\, myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add3~9\, myVirtualToplevel|UART1|Add3~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[1]\, myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add3~17\, myVirtualToplevel|UART1|Add3~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[2]\, myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add3~13\, myVirtualToplevel|UART1|Add3~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[3]\, myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add3~1\, myVirtualToplevel|UART1|Add3~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[4]\, myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[5]\, myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add2~21\, myVirtualToplevel|UART1|Add2~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add2~25\, myVirtualToplevel|UART1|Add2~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add2~29\, myVirtualToplevel|UART1|Add2~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add2~9\, myVirtualToplevel|UART1|Add2~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add2~13\, myVirtualToplevel|UART1|Add2~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add2~17\, myVirtualToplevel|UART1|Add2~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE\, myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal3~0\, myVirtualToplevel|UART1|Equal3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add2~1\, myVirtualToplevel|UART1|Add2~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add2~5\, myVirtualToplevel|UART1|Add2~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal3~1\, myVirtualToplevel|UART1|Equal3~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal3~2\, myVirtualToplevel|UART1|Equal3~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0\, myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]\, myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add4~13\, myVirtualToplevel|UART1|Add4~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[2]\, myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[3]\, myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE\, myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal2~1\, myVirtualToplevel|UART1|Equal2~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal2~4\, myVirtualToplevel|UART1|Equal2~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[0]~0\, myVirtualToplevel|UART1|RX_DATA[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~31\, myVirtualToplevel|UART1|RX_FIFO~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal3~3\, myVirtualToplevel|UART1|Equal3~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~32\, myVirtualToplevel|UART1|RX_FIFO~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE\, myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_BUFFER[5]~DUPLICATE\, myVirtualToplevel|UART1|RX_BUFFER[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_BUFFER[7]\, myVirtualToplevel|UART1|RX_BUFFER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0\, myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]~feeder\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[15]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[13]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[11]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[14]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[12]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~26\, myVirtualToplevel|UART1|RX_FIFO~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[16]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[9]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[0]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[2]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[4]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[3]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[1]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~27\, myVirtualToplevel|UART1|RX_FIFO~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[10]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[7]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[6]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[8]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[5]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~28\, myVirtualToplevel|UART1|RX_FIFO~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~29\, myVirtualToplevel|UART1|RX_FIFO~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~30\, myVirtualToplevel|UART1|RX_FIFO~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE\, myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[0]~3\, myVirtualToplevel|UART1|RX_DATA[0]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~33\, myVirtualToplevel|UART1|RX_FIFO~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~34\, myVirtualToplevel|UART1|RX_FIFO~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~24\, myVirtualToplevel|UART1|RX_FIFO~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~35\, myVirtualToplevel|UART1|RX_FIFO~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~17\, myVirtualToplevel|UART1|RX_FIFO~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[0]~2\, myVirtualToplevel|UART1|RX_DATA[0]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA~8\, myVirtualToplevel|UART1|RX_DATA~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[6]~9\, myVirtualToplevel|UART1|RX_DATA[6]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[6]\, myVirtualToplevel|UART1|RX_DATA[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~47\, myVirtualToplevel|IO_DATA_READ~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_ENABLE~0\, myVirtualToplevel|UART0|RX_ENABLE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_ENABLE\, myVirtualToplevel|UART0|RX_ENABLE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_RESET~0\, myVirtualToplevel|UART0|RX_RESET~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_RESET\, myVirtualToplevel|UART0|RX_RESET, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[0]~1\, myVirtualToplevel|UART0|RX_DATA[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RXD_SYNC2\, myVirtualToplevel|UART0|RXD_SYNC2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RXD_SYNC\, myVirtualToplevel|UART0|RXD_SYNC, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Selector6~0\, myVirtualToplevel|UART0|Selector6~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]~5\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~15\, myVirtualToplevel|UART0|RX_COUNTER~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[1]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[0]~1\, myVirtualToplevel|UART0|RX_COUNTER[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[0]\, myVirtualToplevel|UART0|RX_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~53\, myVirtualToplevel|UART0|Add1~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~17\, myVirtualToplevel|UART0|Add1~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~6\, myVirtualToplevel|UART0|RX_COUNTER~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~1\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~_wirecell\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[1]\, myVirtualToplevel|UART0|RX_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~21\, myVirtualToplevel|UART0|Add1~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~7\, myVirtualToplevel|UART0|RX_COUNTER~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~2\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~_wirecell\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[2]\, myVirtualToplevel|UART0|RX_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~25\, myVirtualToplevel|UART0|Add1~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~8\, myVirtualToplevel|UART0|RX_COUNTER~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~3\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~_wirecell\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[3]\, myVirtualToplevel|UART0|RX_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~29\, myVirtualToplevel|UART0|Add1~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~9\, myVirtualToplevel|UART0|RX_COUNTER~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~4\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~_wirecell\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[4]\, myVirtualToplevel|UART0|RX_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal1~1\, myVirtualToplevel|UART0|Equal1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[9]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[7]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~33\, myVirtualToplevel|UART0|Add1~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~10\, myVirtualToplevel|UART0|RX_COUNTER~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[6]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[5]\, myVirtualToplevel|UART0|RX_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~37\, myVirtualToplevel|UART0|Add1~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~11\, myVirtualToplevel|UART0|RX_COUNTER~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[6]\, myVirtualToplevel|UART0|RX_COUNTER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~1\, myVirtualToplevel|UART0|Add1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~2\, myVirtualToplevel|UART0|RX_COUNTER~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[8]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE\, myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~5\, myVirtualToplevel|UART0|Add1~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~3\, myVirtualToplevel|UART0|RX_COUNTER~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[8]\, myVirtualToplevel|UART0|RX_COUNTER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~9\, myVirtualToplevel|UART0|Add1~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~4\, myVirtualToplevel|UART0|RX_COUNTER~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~0\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~_wirecell\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[9]\, myVirtualToplevel|UART0|RX_COUNTER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~13\, myVirtualToplevel|UART0|Add1~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~5\, myVirtualToplevel|UART0|RX_COUNTER~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]~feeder\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE\, myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~41\, myVirtualToplevel|UART0|Add1~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~12\, myVirtualToplevel|UART0|RX_COUNTER~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~DUPLICATE\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[11]\, myVirtualToplevel|UART0|RX_COUNTER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~45\, myVirtualToplevel|UART0|Add1~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~13\, myVirtualToplevel|UART0|RX_COUNTER~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13]~DUPLICATE\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[12]\, myVirtualToplevel|UART0|RX_COUNTER[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~57\, myVirtualToplevel|UART0|Add1~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~16\, myVirtualToplevel|UART0|RX_COUNTER~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]~feeder\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[13]\, myVirtualToplevel|UART0|RX_COUNTER[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~61\, myVirtualToplevel|UART0|Add1~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~17\, myVirtualToplevel|UART0|RX_COUNTER~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[15]\, myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[14]\, myVirtualToplevel|UART0|RX_COUNTER[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add1~49\, myVirtualToplevel|UART0|Add1~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER~14\, myVirtualToplevel|UART0|RX_COUNTER~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[15]\, myVirtualToplevel|UART0|RX_COUNTER[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal1~3\, myVirtualToplevel|UART0|Equal1~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal1~2\, myVirtualToplevel|UART0|Equal1~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[7]\, myVirtualToplevel|UART0|RX_COUNTER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_COUNTER[10]\, myVirtualToplevel|UART0|RX_COUNTER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal1~0\, myVirtualToplevel|UART0|Equal1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal1~4\, myVirtualToplevel|UART0|Equal1~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK~0\, myVirtualToplevel|UART0|RX_CLOCK~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK\, myVirtualToplevel|UART0|RX_CLOCK, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[1]~0\, myVirtualToplevel|UART0|RX_BUFFER[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[6]\, myVirtualToplevel|UART0|RX_BUFFER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Selector7~0\, myVirtualToplevel|UART0|Selector7~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[5]\, myVirtualToplevel|UART0|RX_BUFFER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Selector8~0\, myVirtualToplevel|UART0|Selector8~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[4]\, myVirtualToplevel|UART0|RX_BUFFER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Selector9~0\, myVirtualToplevel|UART0|Selector9~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[3]\, myVirtualToplevel|UART0|RX_BUFFER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Selector10~0\, myVirtualToplevel|UART0|Selector10~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[2]\, myVirtualToplevel|UART0|RX_BUFFER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Selector11~0\, myVirtualToplevel|UART0|Selector11~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[1]\, myVirtualToplevel|UART0|RX_BUFFER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Selector12~0\, myVirtualToplevel|UART0|Selector12~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[0]\, myVirtualToplevel|UART0|RX_BUFFER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE\, myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_STATE.stop~0\, myVirtualToplevel|UART0|RX_STATE.stop~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_STATE.stop~1\, myVirtualToplevel|UART0|RX_STATE.stop~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_STATE.stop\, myVirtualToplevel|UART0|RX_STATE.stop, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_STATE.stop~2\, myVirtualToplevel|UART0|RX_STATE.stop~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_STATE.idle~0\, myVirtualToplevel|UART0|RX_STATE.idle~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_STATE.idle\, myVirtualToplevel|UART0|RX_STATE.idle, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_STATE.start~0\, myVirtualToplevel|UART0|RX_STATE.start~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_STATE.start\, myVirtualToplevel|UART0|RX_STATE.start, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_STATE.bits~0\, myVirtualToplevel|UART0|RX_STATE.bits~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_STATE.bits\, myVirtualToplevel|UART0|RX_STATE.bits, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Selector4~0\, myVirtualToplevel|UART0|Selector4~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[8]\, myVirtualToplevel|UART0|RX_BUFFER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Selector5~0\, myVirtualToplevel|UART0|Selector5~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[7]\, myVirtualToplevel|UART0|RX_BUFFER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[23]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1\, myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_INTR~0\, myVirtualToplevel|UART0|RX_INTR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add3~5\, myVirtualToplevel|UART0|Add3~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add4~5\, myVirtualToplevel|UART0|Add4~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[1]\, myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add4~21\, myVirtualToplevel|UART0|Add4~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[2]\, myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add4~9\, myVirtualToplevel|UART0|Add4~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3]\, myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add4~1\, myVirtualToplevel|UART0|Add4~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[4]\, myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add4~25\, myVirtualToplevel|UART0|Add4~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[5]\, myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add4~13\, myVirtualToplevel|UART0|Add4~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[6]\, myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add4~17\, myVirtualToplevel|UART0|Add4~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[7]\, myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add3~9\, myVirtualToplevel|UART0|Add3~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add3~25\, myVirtualToplevel|UART0|Add3~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[2]\, myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add3~13\, myVirtualToplevel|UART0|Add3~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[3]\, myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add3~1\, myVirtualToplevel|UART0|Add3~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[4]\, myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add3~29\, myVirtualToplevel|UART0|Add3~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[5]\, myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add3~17\, myVirtualToplevel|UART0|Add3~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[6]\, myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add3~21\, myVirtualToplevel|UART0|Add3~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[7]\, myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal2~2\, myVirtualToplevel|UART0|Equal2~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal2~1\, myVirtualToplevel|UART0|Equal2~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]\, myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE\, myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal2~0\, myVirtualToplevel|UART0|Equal2~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal2~3\, myVirtualToplevel|UART0|Equal2~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal2~4\, myVirtualToplevel|UART0|Equal2~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA_READY~0\, myVirtualToplevel|UART0|RX_DATA_READY~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA_READY~1\, myVirtualToplevel|UART0|RX_DATA_READY~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA_READY\, myVirtualToplevel|UART0|RX_DATA_READY, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|process_3~0\, myVirtualToplevel|UART0|process_3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0\, myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE\, myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[1]\, myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add2~21\, myVirtualToplevel|UART0|Add2~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add2~25\, myVirtualToplevel|UART0|Add2~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add2~29\, myVirtualToplevel|UART0|Add2~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal3~1\, myVirtualToplevel|UART0|Equal3~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add2~9\, myVirtualToplevel|UART0|Add2~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add2~13\, myVirtualToplevel|UART0|Add2~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add2~17\, myVirtualToplevel|UART0|Add2~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add2~1\, myVirtualToplevel|UART0|Add2~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add2~5\, myVirtualToplevel|UART0|Add2~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal3~0\, myVirtualToplevel|UART0|Equal3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal3~2\, myVirtualToplevel|UART0|Equal3~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0\, myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]\, myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~33\, myVirtualToplevel|UART0|RX_FIFO~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~31\, myVirtualToplevel|UART0|RX_FIFO~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal3~3\, myVirtualToplevel|UART0|Equal3~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~32\, myVirtualToplevel|UART0|RX_FIFO~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~34\, myVirtualToplevel|UART0|RX_FIFO~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~24\, myVirtualToplevel|UART0|RX_FIFO~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~35\, myVirtualToplevel|UART0|RX_FIFO~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~17\, myVirtualToplevel|UART0|RX_FIFO~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[15]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[13]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[11]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[14]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[12]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~26\, myVirtualToplevel|UART0|RX_FIFO~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[16]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[4]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[2]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[1]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[3]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[0]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~27\, myVirtualToplevel|UART0|RX_FIFO~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[9]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[10]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[8]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[6]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[5]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[7]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~28\, myVirtualToplevel|UART0|RX_FIFO~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~29\, myVirtualToplevel|UART0|RX_FIFO~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~30\, myVirtualToplevel|UART0|RX_FIFO~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[7]~2\, myVirtualToplevel|UART0|RX_DATA[7]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3]~DUPLICATE\, myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE\, myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE\, myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE\, myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE\, myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0\, myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[7]~3\, myVirtualToplevel|UART0|RX_DATA[7]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA~8\, myVirtualToplevel|UART0|RX_DATA~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[6]~9\, myVirtualToplevel|UART0|RX_DATA[6]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[6]\, myVirtualToplevel|UART0|RX_DATA[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~48\, myVirtualToplevel|IO_DATA_READ~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[0]~46\, myVirtualToplevel|IO_DATA_READ[0]~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~50\, myVirtualToplevel|IO_DATA_READ~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add19~41\, myVirtualToplevel|Add19~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal36~1\, myVirtualToplevel|Equal36~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add19~21\, myVirtualToplevel|Add19~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add19~25\, myVirtualToplevel|Add19~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTR0_CS~0\, myVirtualToplevel|INTR0_CS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1\, myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[7]\, myVirtualToplevel|SECOND_DOWN_COUNTER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add19~29\, myVirtualToplevel|Add19~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[8]\, myVirtualToplevel|SECOND_DOWN_COUNTER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add19~9\, myVirtualToplevel|Add19~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[9]\, myVirtualToplevel|SECOND_DOWN_COUNTER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add19~13\, myVirtualToplevel|Add19~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE\, myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add19~17\, myVirtualToplevel|Add19~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE\, myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal36~0\, myVirtualToplevel|Equal36~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~93\, myVirtualToplevel|Add18~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[0]\, myVirtualToplevel|SECOND_DOWN_TICK[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~89\, myVirtualToplevel|Add18~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[1]\, myVirtualToplevel|SECOND_DOWN_TICK[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~85\, myVirtualToplevel|Add18~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[2]\, myVirtualToplevel|SECOND_DOWN_TICK[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~81\, myVirtualToplevel|Add18~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[3]\, myVirtualToplevel|SECOND_DOWN_TICK[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~77\, myVirtualToplevel|Add18~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[4]\, myVirtualToplevel|SECOND_DOWN_TICK[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~73\, myVirtualToplevel|Add18~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[5]\, myVirtualToplevel|SECOND_DOWN_TICK[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~109\, myVirtualToplevel|Add18~109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[6]\, myVirtualToplevel|SECOND_DOWN_TICK[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~105\, myVirtualToplevel|Add18~105, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[7]\, myVirtualToplevel|SECOND_DOWN_TICK[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~69\, myVirtualToplevel|Add18~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[8]\, myVirtualToplevel|SECOND_DOWN_TICK[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~65\, myVirtualToplevel|Add18~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[9]\, myVirtualToplevel|SECOND_DOWN_TICK[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~13\, myVirtualToplevel|Add18~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[10]\, myVirtualToplevel|SECOND_DOWN_TICK[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~9\, myVirtualToplevel|Add18~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[11]\, myVirtualToplevel|SECOND_DOWN_TICK[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~45\, myVirtualToplevel|Add18~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE\, myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~41\, myVirtualToplevel|Add18~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[13]\, myVirtualToplevel|SECOND_DOWN_TICK[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~37\, myVirtualToplevel|Add18~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[14]\, myVirtualToplevel|SECOND_DOWN_TICK[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~33\, myVirtualToplevel|Add18~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE\, myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~29\, myVirtualToplevel|Add18~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE\, myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~5\, myVirtualToplevel|Add18~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[17]\, myVirtualToplevel|SECOND_DOWN_TICK[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~25\, myVirtualToplevel|Add18~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[18]\, myVirtualToplevel|SECOND_DOWN_TICK[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~1\, myVirtualToplevel|Add18~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[19]\, myVirtualToplevel|SECOND_DOWN_TICK[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~21\, myVirtualToplevel|Add18~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[20]\, myVirtualToplevel|SECOND_DOWN_TICK[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~17\, myVirtualToplevel|Add18~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[21]\, myVirtualToplevel|SECOND_DOWN_TICK[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~61\, myVirtualToplevel|Add18~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[22]\, myVirtualToplevel|SECOND_DOWN_TICK[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~57\, myVirtualToplevel|Add18~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[23]\, myVirtualToplevel|SECOND_DOWN_TICK[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~53\, myVirtualToplevel|Add18~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[24]\, myVirtualToplevel|SECOND_DOWN_TICK[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~101\, myVirtualToplevel|Add18~101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[25]\, myVirtualToplevel|SECOND_DOWN_TICK[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~49\, myVirtualToplevel|Add18~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[26]\, myVirtualToplevel|SECOND_DOWN_TICK[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add18~97\, myVirtualToplevel|Add18~97, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[27]\, myVirtualToplevel|SECOND_DOWN_TICK[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal35~6\, myVirtualToplevel|Equal35~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[12]\, myVirtualToplevel|SECOND_DOWN_TICK[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[15]\, myVirtualToplevel|SECOND_DOWN_TICK[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal35~1\, myVirtualToplevel|Equal35~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[16]\, myVirtualToplevel|SECOND_DOWN_TICK[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal35~0\, myVirtualToplevel|Equal35~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal35~2\, myVirtualToplevel|Equal35~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal35~4\, myVirtualToplevel|Equal35~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal35~5\, myVirtualToplevel|Equal35~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_TICK[23]~DUPLICATE\, myVirtualToplevel|SECOND_DOWN_TICK[23]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal35~3\, myVirtualToplevel|Equal35~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal35~7\, myVirtualToplevel|Equal35~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER~0\, myVirtualToplevel|SECOND_DOWN_COUNTER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[0]\, myVirtualToplevel|SECOND_DOWN_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add19~45\, myVirtualToplevel|Add19~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE\, myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add19~37\, myVirtualToplevel|Add19~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[2]\, myVirtualToplevel|SECOND_DOWN_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add19~33\, myVirtualToplevel|Add19~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE\, myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add19~1\, myVirtualToplevel|Add19~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[4]\, myVirtualToplevel|SECOND_DOWN_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add19~5\, myVirtualToplevel|Add19~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[5]\, myVirtualToplevel|SECOND_DOWN_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[6]\, myVirtualToplevel|SECOND_DOWN_COUNTER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~69\, myVirtualToplevel|Add16~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[0]\, myVirtualToplevel|MILLISEC_UP_TICK[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~65\, myVirtualToplevel|Add16~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~61\, myVirtualToplevel|Add16~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[2]\, myVirtualToplevel|MILLISEC_UP_TICK[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~57\, myVirtualToplevel|Add16~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[3]\, myVirtualToplevel|MILLISEC_UP_TICK[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[1]\, myVirtualToplevel|MILLISEC_UP_TICK[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal34~3\, myVirtualToplevel|Equal34~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~5\, myVirtualToplevel|Add16~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[4]\, myVirtualToplevel|MILLISEC_UP_TICK[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~1\, myVirtualToplevel|Add16~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~21\, myVirtualToplevel|Add16~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[6]\, myVirtualToplevel|MILLISEC_UP_TICK[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~53\, myVirtualToplevel|Add16~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[7]\, myVirtualToplevel|MILLISEC_UP_TICK[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~17\, myVirtualToplevel|Add16~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[8]\, myVirtualToplevel|MILLISEC_UP_TICK[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~49\, myVirtualToplevel|Add16~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[9]\, myVirtualToplevel|MILLISEC_UP_TICK[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~45\, myVirtualToplevel|Add16~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[10]\, myVirtualToplevel|MILLISEC_UP_TICK[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~41\, myVirtualToplevel|Add16~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[11]\, myVirtualToplevel|MILLISEC_UP_TICK[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~37\, myVirtualToplevel|Add16~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[12]\, myVirtualToplevel|MILLISEC_UP_TICK[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~33\, myVirtualToplevel|Add16~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[13]\, myVirtualToplevel|MILLISEC_UP_TICK[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~29\, myVirtualToplevel|Add16~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[14]\, myVirtualToplevel|MILLISEC_UP_TICK[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~13\, myVirtualToplevel|Add16~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[15]\, myVirtualToplevel|MILLISEC_UP_TICK[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~9\, myVirtualToplevel|Add16~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[16]\, myVirtualToplevel|MILLISEC_UP_TICK[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add16~25\, myVirtualToplevel|Add16~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[17]\, myVirtualToplevel|MILLISEC_UP_TICK[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal34~0\, myVirtualToplevel|Equal34~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal34~1\, myVirtualToplevel|Equal34~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal34~2\, myVirtualToplevel|Equal34~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_TICK[5]\, myVirtualToplevel|MILLISEC_UP_TICK[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal34~4\, myVirtualToplevel|Equal34~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal3~0\, myVirtualToplevel|Equal3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0\, myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~125\, myVirtualToplevel|Add17~125, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[0]\, myVirtualToplevel|MILLISEC_UP_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~89\, myVirtualToplevel|Add17~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[1]\, myVirtualToplevel|MILLISEC_UP_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~85\, myVirtualToplevel|Add17~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[2]\, myVirtualToplevel|MILLISEC_UP_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~81\, myVirtualToplevel|Add17~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[3]\, myVirtualToplevel|MILLISEC_UP_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~49\, myVirtualToplevel|Add17~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~53\, myVirtualToplevel|Add17~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[5]\, myVirtualToplevel|MILLISEC_UP_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~69\, myVirtualToplevel|Add17~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[6]\, myVirtualToplevel|MILLISEC_UP_COUNTER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~89\, myVirtualToplevel|Add13~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~93\, myVirtualToplevel|Add13~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[1]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~85\, myVirtualToplevel|Add13~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~81\, myVirtualToplevel|Add13~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[3]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~49\, myVirtualToplevel|Add13~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[4]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~53\, myVirtualToplevel|Add13~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~69\, myVirtualToplevel|Add13~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~73\, myVirtualToplevel|Add13~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[7]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~77\, myVirtualToplevel|Add13~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[8]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~57\, myVirtualToplevel|Add13~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[9]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~61\, myVirtualToplevel|Add13~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~65\, myVirtualToplevel|Add13~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[11]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~33\, myVirtualToplevel|Add13~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~37\, myVirtualToplevel|Add13~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~41\, myVirtualToplevel|Add13~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~45\, myVirtualToplevel|Add13~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[15]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~1\, myVirtualToplevel|Add13~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[16]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~21\, myVirtualToplevel|Add13~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_NEW_REG1614\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[17]_NEW_REG1614, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|LessThan0~1\, myVirtualToplevel|LessThan0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector216~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector216~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node[0]\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[1]~64\, myVirtualToplevel|MEM_DATA_READ[1]~64, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate\, myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|data_o[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector63~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector63~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnData_v, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|data_o[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][2]\, myVirtualToplevel|SD_ADDR[0][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux81~0\, myVirtualToplevel|Mux81~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[2]\, myVirtualToplevel|IO_DATA_READ_SD[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127\, myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125\, myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~34\, myVirtualToplevel|MEM_DATA_READ[2]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[0]~70\, myVirtualToplevel|IO_DATA_READ[0]~70, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[19]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~20\, myVirtualToplevel|UART0|RX_FIFO~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA~14\, myVirtualToplevel|UART0|RX_DATA~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[2]~15\, myVirtualToplevel|UART0|RX_DATA[2]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[2]\, myVirtualToplevel|UART0|RX_DATA[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4\, myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[9]\, myVirtualToplevel|RTC_MILLISEC_COUNTER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add5~33\, myVirtualToplevel|Add5~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[0]\, myVirtualToplevel|RTC_MILLISEC_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add5~37\, myVirtualToplevel|Add5~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[1]\, myVirtualToplevel|RTC_MILLISEC_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add5~29\, myVirtualToplevel|Add5~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[2]\, myVirtualToplevel|RTC_MILLISEC_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add5~25\, myVirtualToplevel|Add5~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]\, myVirtualToplevel|RTC_MILLISEC_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add5~1\, myVirtualToplevel|Add5~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[4]\, myVirtualToplevel|RTC_MILLISEC_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add5~5\, myVirtualToplevel|Add5~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add5~13\, myVirtualToplevel|Add5~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[6]\, myVirtualToplevel|RTC_MILLISEC_COUNTER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add5~17\, myVirtualToplevel|Add5~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[7]\, myVirtualToplevel|RTC_MILLISEC_COUNTER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add5~21\, myVirtualToplevel|Add5~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[8]\, myVirtualToplevel|RTC_MILLISEC_COUNTER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add5~9\, myVirtualToplevel|Add5~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE\, myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[1]~DUPLICATE\, myVirtualToplevel|RTC_MILLISEC_COUNTER[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2\, myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3\, myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[5]\, myVirtualToplevel|RTC_MILLISEC_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[5]~DUPLICATE\, myVirtualToplevel|RTC_MILLISEC_COUNTER[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[6]~DUPLICATE\, myVirtualToplevel|RTC_MILLISEC_COUNTER[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1\, myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER~5\, myVirtualToplevel|RTC_SECOND_COUNTER~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1\, myVirtualToplevel|RTC_SECOND_COUNTER[3]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER[0]\, myVirtualToplevel|RTC_SECOND_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE\, myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER~6\, myVirtualToplevel|RTC_SECOND_COUNTER~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER[1]\, myVirtualToplevel|RTC_SECOND_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add6~0\, myVirtualToplevel|Add6~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER~4\, myVirtualToplevel|RTC_SECOND_COUNTER~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE\, myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER[2]\, myVirtualToplevel|RTC_SECOND_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER~3\, myVirtualToplevel|RTC_SECOND_COUNTER~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER[3]\, myVirtualToplevel|RTC_SECOND_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add6~1\, myVirtualToplevel|Add6~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER[4]\, myVirtualToplevel|RTC_SECOND_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER~0\, myVirtualToplevel|RTC_SECOND_COUNTER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE\, myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER~2\, myVirtualToplevel|RTC_SECOND_COUNTER~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER[5]\, myVirtualToplevel|RTC_SECOND_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER~0\, myVirtualToplevel|RTC_MINUTE_COUNTER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER~1\, myVirtualToplevel|RTC_MINUTE_COUNTER~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER~8\, myVirtualToplevel|RTC_MINUTE_COUNTER~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4\, myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER[0]\, myVirtualToplevel|RTC_MINUTE_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE\, myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER~9\, myVirtualToplevel|RTC_MINUTE_COUNTER~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER[1]\, myVirtualToplevel|RTC_MINUTE_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add7~0\, myVirtualToplevel|Add7~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER[2]\, myVirtualToplevel|RTC_MINUTE_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER~6\, myVirtualToplevel|RTC_MINUTE_COUNTER~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER[3]\, myVirtualToplevel|RTC_MINUTE_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add7~1\, myVirtualToplevel|Add7~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER~3\, myVirtualToplevel|RTC_MINUTE_COUNTER~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE\, myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER[4]\, myVirtualToplevel|RTC_MINUTE_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER[5]\, myVirtualToplevel|RTC_MINUTE_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER~10\, myVirtualToplevel|RTC_MINUTE_COUNTER~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE\, myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2\, myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER~7\, myVirtualToplevel|RTC_MINUTE_COUNTER~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE\, myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~74\, myVirtualToplevel|IO_DATA_READ~74, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~65\, myVirtualToplevel|Add15~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[0]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~69\, myVirtualToplevel|Add15~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[1]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~61\, myVirtualToplevel|Add15~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~57\, myVirtualToplevel|Add15~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[3]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~25\, myVirtualToplevel|Add15~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[4]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal33~3\, myVirtualToplevel|Equal33~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~29\, myVirtualToplevel|Add15~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[5]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~45\, myVirtualToplevel|Add15~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[6]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~49\, myVirtualToplevel|Add15~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~53\, myVirtualToplevel|Add15~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~33\, myVirtualToplevel|Add15~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~37\, myVirtualToplevel|Add15~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[10]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~41\, myVirtualToplevel|Add15~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~9\, myVirtualToplevel|Add15~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[12]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~13\, myVirtualToplevel|Add15~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~17\, myVirtualToplevel|Add15~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~21\, myVirtualToplevel|Add15~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~1\, myVirtualToplevel|Add15~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal33~0\, myVirtualToplevel|Equal33~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add15~5\, myVirtualToplevel|Add15~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[17]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal33~1\, myVirtualToplevel|Equal33~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal33~2\, myVirtualToplevel|Equal33~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~69\, myVirtualToplevel|Add14~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[0]\, myVirtualToplevel|MILLISEC_DOWN_TICK[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~65\, myVirtualToplevel|Add14~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[1]\, myVirtualToplevel|MILLISEC_DOWN_TICK[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~61\, myVirtualToplevel|Add14~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[2]\, myVirtualToplevel|MILLISEC_DOWN_TICK[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~5\, myVirtualToplevel|Add14~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[3]\, myVirtualToplevel|MILLISEC_DOWN_TICK[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~57\, myVirtualToplevel|Add14~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[4]\, myVirtualToplevel|MILLISEC_DOWN_TICK[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal32~3\, myVirtualToplevel|Equal32~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~1\, myVirtualToplevel|Add14~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[5]\, myVirtualToplevel|MILLISEC_DOWN_TICK[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~21\, myVirtualToplevel|Add14~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[6]\, myVirtualToplevel|MILLISEC_DOWN_TICK[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~53\, myVirtualToplevel|Add14~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[7]\, myVirtualToplevel|MILLISEC_DOWN_TICK[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~17\, myVirtualToplevel|Add14~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[8]\, myVirtualToplevel|MILLISEC_DOWN_TICK[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~49\, myVirtualToplevel|Add14~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[9]\, myVirtualToplevel|MILLISEC_DOWN_TICK[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~45\, myVirtualToplevel|Add14~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[10]\, myVirtualToplevel|MILLISEC_DOWN_TICK[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~41\, myVirtualToplevel|Add14~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[11]\, myVirtualToplevel|MILLISEC_DOWN_TICK[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~37\, myVirtualToplevel|Add14~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~33\, myVirtualToplevel|Add14~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~29\, myVirtualToplevel|Add14~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~13\, myVirtualToplevel|Add14~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[15]\, myVirtualToplevel|MILLISEC_DOWN_TICK[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~9\, myVirtualToplevel|Add14~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[16]\, myVirtualToplevel|MILLISEC_DOWN_TICK[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[13]\, myVirtualToplevel|MILLISEC_DOWN_TICK[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[12]\, myVirtualToplevel|MILLISEC_DOWN_TICK[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[14]\, myVirtualToplevel|MILLISEC_DOWN_TICK[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[17]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_TICK[17]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add14~25\, myVirtualToplevel|Add14~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_TICK[17]\, myVirtualToplevel|MILLISEC_DOWN_TICK[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal32~0\, myVirtualToplevel|Equal32~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal32~1\, myVirtualToplevel|Equal32~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal32~2\, myVirtualToplevel|Equal32~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal32~4\, myVirtualToplevel|Equal32~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0\, myVirtualToplevel|MILLISEC_DOWN_COUNTER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~73\, myVirtualToplevel|IO_DATA_READ~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_HOUR_COUNTER~1\, myVirtualToplevel|RTC_HOUR_COUNTER~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER~5\, myVirtualToplevel|RTC_MONTH_COUNTER~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6\, myVirtualToplevel|RTC_MONTH_COUNTER[3]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE\, myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER~7\, myVirtualToplevel|RTC_MONTH_COUNTER~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER[2]\, myVirtualToplevel|RTC_MONTH_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER~4\, myVirtualToplevel|RTC_MONTH_COUNTER~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER[3]\, myVirtualToplevel|RTC_MONTH_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5\, myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_HOUR_COUNTER~5\, myVirtualToplevel|RTC_HOUR_COUNTER~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2\, myVirtualToplevel|RTC_HOUR_COUNTER[2]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_HOUR_COUNTER[0]\, myVirtualToplevel|RTC_HOUR_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_HOUR_COUNTER~6\, myVirtualToplevel|RTC_HOUR_COUNTER~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_HOUR_COUNTER[1]\, myVirtualToplevel|RTC_HOUR_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_HOUR_COUNTER~4\, myVirtualToplevel|RTC_HOUR_COUNTER~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_HOUR_COUNTER[2]\, myVirtualToplevel|RTC_HOUR_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER~0\, myVirtualToplevel|RTC_MONTH_COUNTER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_HOUR_COUNTER~3\, myVirtualToplevel|RTC_HOUR_COUNTER~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_HOUR_COUNTER[3]\, myVirtualToplevel|RTC_HOUR_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_HOUR_COUNTER~0\, myVirtualToplevel|RTC_HOUR_COUNTER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_HOUR_COUNTER[4]\, myVirtualToplevel|RTC_HOUR_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER~1\, myVirtualToplevel|RTC_MONTH_COUNTER~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER~3\, myVirtualToplevel|RTC_MONTH_COUNTER~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER[0]\, myVirtualToplevel|RTC_DAY_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER~2\, myVirtualToplevel|RTC_DAY_COUNTER~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER~6\, myVirtualToplevel|RTC_DAY_COUNTER~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE\, myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[5]~49\, myVirtualToplevel|IO_DATA_READ[5]~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[6]~1\, myVirtualToplevel|RTC_YEAR_COUNTER[6]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[0]_NEW1628\, myVirtualToplevel|RTC_YEAR_COUNTER[0]_NEW1628, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[0]\, myVirtualToplevel|RTC_YEAR_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add11~41\, myVirtualToplevel|Add11~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add11~45\, myVirtualToplevel|Add11~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[1]_NEW1626\, myVirtualToplevel|RTC_YEAR_COUNTER[1]_NEW1626, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[1]\, myVirtualToplevel|RTC_YEAR_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER~8\, myVirtualToplevel|RTC_DAY_COUNTER~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER[4]~3\, myVirtualToplevel|RTC_DAY_COUNTER[4]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER[1]\, myVirtualToplevel|RTC_DAY_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|process_1~2\, myVirtualToplevel|process_1~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add9~0\, myVirtualToplevel|Add9~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE\, myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|process_1~3\, myVirtualToplevel|process_1~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER[4]\, myVirtualToplevel|RTC_DAY_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER[2]\, myVirtualToplevel|RTC_DAY_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER~5\, myVirtualToplevel|RTC_DAY_COUNTER~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE\, myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER~4\, myVirtualToplevel|RTC_DAY_COUNTER~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER[3]\, myVirtualToplevel|RTC_DAY_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add9~1\, myVirtualToplevel|Add9~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER~7\, myVirtualToplevel|RTC_DAY_COUNTER~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER[5]\, myVirtualToplevel|RTC_DAY_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|process_1~4\, myVirtualToplevel|process_1~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|process_1~5\, myVirtualToplevel|process_1~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER~0\, myVirtualToplevel|RTC_DAY_COUNTER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER~1\, myVirtualToplevel|RTC_DAY_COUNTER~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER[4]~DUPLICATE\, myVirtualToplevel|RTC_DAY_COUNTER[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE\, myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|process_1~0\, myVirtualToplevel|process_1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|process_1~1\, myVirtualToplevel|process_1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER~2\, myVirtualToplevel|RTC_MONTH_COUNTER~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER~8\, myVirtualToplevel|RTC_MONTH_COUNTER~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER~9\, myVirtualToplevel|RTC_MONTH_COUNTER~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER[0]\, myVirtualToplevel|RTC_MONTH_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER~10\, myVirtualToplevel|RTC_MONTH_COUNTER~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MONTH_COUNTER[1]\, myVirtualToplevel|RTC_MONTH_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER~0\, myVirtualToplevel|RTC_YEAR_COUNTER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add11~37\, myVirtualToplevel|Add11~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[2]_NEW1754\, myVirtualToplevel|RTC_YEAR_COUNTER[2]_NEW1754, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[2]\, myVirtualToplevel|RTC_YEAR_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~72\, myVirtualToplevel|IO_DATA_READ~72, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~75\, myVirtualToplevel|IO_DATA_READ~75, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~29\, myVirtualToplevel|UART1|Add9~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~34\, myVirtualToplevel|UART1|Add9~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~39\, myVirtualToplevel|UART1|Add9~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~42\, myVirtualToplevel|UART1|Add9~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~36\, myVirtualToplevel|UART1|Add9~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~31\, myVirtualToplevel|UART1|Add9~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~21\, myVirtualToplevel|UART1|Add9~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~20\, myVirtualToplevel|UART1|RX_FIFO~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]~feeder\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA~14\, myVirtualToplevel|UART1|RX_DATA~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[2]~15\, myVirtualToplevel|UART1|RX_DATA[2]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[2]\, myVirtualToplevel|UART1|RX_DATA[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~76\, myVirtualToplevel|IO_DATA_READ~76, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~77\, myVirtualToplevel|IO_DATA_READ~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[0]~5\, myVirtualToplevel|IO_DATA_READ[0]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[2]\, myVirtualToplevel|IO_DATA_READ[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[2]\, myVirtualToplevel|INT_ENABLE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[2]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616\, myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~22\, myVirtualToplevel|MEM_DATA_READ[2]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~35\, myVirtualToplevel|MEM_DATA_READ[2]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~36\, myVirtualToplevel|MEM_DATA_READ[2]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_NEW_REG30\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_NEW_REG30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806\, myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate\, myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[4]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]_NEW3210\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[3]_NEW3210, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]_NEW3222\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[4]_NEW3222, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]_NEW3207\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[5]_NEW3207, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]_NEW3204\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[6]_NEW3204, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]_NEW3201\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[7]_NEW3201, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~374\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][6]~374, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1308\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1308, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1312\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1312, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1314\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1314, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1310\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1310, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[9]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[1]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[1]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_NEW_REG1316\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[10]_NEW_REG1316, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_NEW_REG1318\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[10]_NEW_REG1318, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_NEW_REG1320\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[10]_NEW_REG1320, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[10]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[2]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[2]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_NEW_REG1322\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[11]_NEW_REG1322, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_NEW_REG1324\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[11]_NEW_REG1324, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_NEW_REG1326\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[11]_NEW_REG1326, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[11]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[3]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[3]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_NEW_REG1352\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[12]_NEW_REG1352, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_NEW_REG1354\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[12]_NEW_REG1354, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_NEW_REG1356\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[12]_NEW_REG1356, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[12]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[4]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[4]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_NEW_REG1342\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[13]_NEW_REG1342, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_NEW_REG1340\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[13]_NEW_REG1340, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_NEW_REG1344\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[13]_NEW_REG1344, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[13]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[5]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[5]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_NEW_REG1346\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[14]_NEW_REG1346, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_NEW_REG1348\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[14]_NEW_REG1348, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_NEW_REG1350\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[14]_NEW_REG1350, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[14]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[6]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[6]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_NEW_REG1334\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[15]_NEW_REG1334, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_NEW_REG1336\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[15]_NEW_REG1336, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_NEW_REG1338\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[15]_NEW_REG1338, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[15]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[7]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[7]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~375\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][6]~375, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder4~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~373\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][6]~373, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~372\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][6]~372, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder4~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~377\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][6]~377, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~376\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][6]~376, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder4~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~379\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][6]~379, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~378\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][6]~378, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~389\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][6]~389, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~388\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][6]~388, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder4~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~393\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][6]~393, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~392\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][6]~392, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~391\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][6]~391, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~390\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][6]~390, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~394\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][6]~394, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~395\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][6]~395, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node[1]\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node[0]\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b[0]\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[17]~66\, myVirtualToplevel|MEM_DATA_READ[17]~66, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG602\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG602, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG598\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG598, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG594\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG594, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG596\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG596, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[30]~20\, myVirtualToplevel|MEM_DATA_READ[30]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[27]~21\, myVirtualToplevel|MEM_DATA_READ[27]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[17]~23\, myVirtualToplevel|MEM_DATA_READ[17]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1073\, myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1073, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[17]~2\, myVirtualToplevel|IO_DATA_READ[17]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1079\, myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1079, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[17]~1\, myVirtualToplevel|IO_DATA_READ[17]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[17]~0\, myVirtualToplevel|IO_DATA_READ[17]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~1\, myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_RESET~0\, myVirtualToplevel|UART1|TX_RESET~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_RESET\, myVirtualToplevel|UART1|TX_RESET, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_ENABLE~1\, myVirtualToplevel|UART1|TX_ENABLE~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_ENABLE\, myVirtualToplevel|UART1|TX_ENABLE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_OVERRUN~0\, myVirtualToplevel|UART1|TX_OVERRUN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_ENABLE_FIFO~0\, myVirtualToplevel|UART1|TX_ENABLE_FIFO~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_ENABLE_FIFO\, myVirtualToplevel|UART1|TX_ENABLE_FIFO, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0\, myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]\, myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add7~1\, myVirtualToplevel|UART1|Add7~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[1]\, myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add7~21\, myVirtualToplevel|UART1|Add7~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[2]\, myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add7~13\, myVirtualToplevel|UART1|Add7~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[3]\, myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add7~25\, myVirtualToplevel|UART1|Add7~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[4]\, myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add7~17\, myVirtualToplevel|UART1|Add7~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[5]\, myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add7~5\, myVirtualToplevel|UART1|Add7~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[6]\, myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add8~1\, myVirtualToplevel|UART1|Add8~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1]\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal5~0\, myVirtualToplevel|UART1|Equal5~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add8~21\, myVirtualToplevel|UART1|Add8~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2]\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add8~13\, myVirtualToplevel|UART1|Add8~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3]\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add8~25\, myVirtualToplevel|UART1|Add8~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[4]\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal5~3\, myVirtualToplevel|UART1|Equal5~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add7~9\, myVirtualToplevel|UART1|Add7~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[7]\, myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add8~17\, myVirtualToplevel|UART1|Add8~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5]\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add8~5\, myVirtualToplevel|UART1|Add8~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add8~9\, myVirtualToplevel|UART1|Add8~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[7]\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal5~1\, myVirtualToplevel|UART1|Equal5~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal5~2\, myVirtualToplevel|UART1|Equal5~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal5~4\, myVirtualToplevel|UART1|Equal5~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER[16]~9\, myVirtualToplevel|UART1|TX_BUFFER[16]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~61\, myVirtualToplevel|UART1|Add0~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~6\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~_wirecell\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER~0\, myVirtualToplevel|UART1|TX_COUNTER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[0]\, myVirtualToplevel|UART1|TX_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~49\, myVirtualToplevel|UART1|Add0~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[1]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[1]\, myVirtualToplevel|UART1|TX_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~53\, myVirtualToplevel|UART1|Add0~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~5\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~_wirecell\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[2]\, myVirtualToplevel|UART1|TX_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~37\, myVirtualToplevel|UART1|Add0~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_NEW_REG905\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[19]_NEW_REG905, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]_NEW2773\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[19]_NEW2773, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]_NEW2901\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[19]_NEW2901, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]_NEW2837\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[19]_NEW2837, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]_NEW2709\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[19]_NEW2709, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux23~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]_NEW3157\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[19]_NEW3157, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]_NEW3029\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[19]_NEW3029, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]_NEW2965\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[19]_NEW2965, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]_NEW3093\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[19]_NEW3093, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux23~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux23~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector15~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector273~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector273~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_NEW_REG907\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[19]_NEW_REG907, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~4\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~_wirecell\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[3]\, myVirtualToplevel|UART1|TX_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~33\, myVirtualToplevel|UART1|Add0~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_NEW_REG909\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[20]_NEW_REG909, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]_NEW3027\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[20]_NEW3027, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]_NEW2963\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[20]_NEW2963, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]_NEW3155\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[20]_NEW3155, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]_NEW3091\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[20]_NEW3091, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux22~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]_NEW2835\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[20]_NEW2835, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]_NEW2707\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[20]_NEW2707, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]_NEW2771\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[20]_NEW2771, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]_NEW2899\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[20]_NEW2899, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux22~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux22~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector14~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector272~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector272~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_NEW_REG911\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[20]_NEW_REG911, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~3\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~_wirecell\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[4]\, myVirtualToplevel|UART1|TX_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~29\, myVirtualToplevel|UART1|Add0~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_NEW_REG917\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[21]_NEW_REG917, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux92~0\, myVirtualToplevel|Mux92~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[4]~feeder\, myVirtualToplevel|IO_DATA_READ_SOCCFG[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[4]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[4]\, myVirtualToplevel|MILLISEC_UP_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux268~0\, myVirtualToplevel|Mux268~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux268~1\, myVirtualToplevel|Mux268~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[3]\, myVirtualToplevel|RTC_YEAR_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add11~33\, myVirtualToplevel|Add11~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[3]_NEW1756\, myVirtualToplevel|RTC_YEAR_COUNTER[3]_NEW1756, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE\, myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add11~1\, myVirtualToplevel|Add11~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[4]_NEW1772\, myVirtualToplevel|RTC_YEAR_COUNTER[4]_NEW1772, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[4]\, myVirtualToplevel|RTC_YEAR_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[4]~34\, myVirtualToplevel|IO_DATA_READ[4]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[4]~35\, myVirtualToplevel|IO_DATA_READ[4]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[21]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~22\, myVirtualToplevel|UART1|RX_FIFO~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA~4\, myVirtualToplevel|UART1|RX_DATA~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[4]~5\, myVirtualToplevel|UART1|RX_DATA[4]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[4]\, myVirtualToplevel|UART1|RX_DATA[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add5~26\, myVirtualToplevel|UART1|Add5~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add5~17\, myVirtualToplevel|UART1|Add5~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add5~21\, myVirtualToplevel|UART1|Add5~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add5~9\, myVirtualToplevel|UART1|Add5~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add5~13\, myVirtualToplevel|UART1|Add5~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add5~1\, myVirtualToplevel|UART1|Add5~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add5~5\, myVirtualToplevel|UART1|Add5~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_INTR~2\, myVirtualToplevel|UART1|RX_INTR~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_INTR~3\, myVirtualToplevel|UART1|RX_INTR~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_INTR~1\, myVirtualToplevel|UART1|RX_INTR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_INTR~4\, myVirtualToplevel|UART1|RX_INTR~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_INTR~5\, myVirtualToplevel|UART1|RX_INTR~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_INTR\, myVirtualToplevel|UART1|RX_INTR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_INTR~2\, myVirtualToplevel|UART0|RX_INTR~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add5~26\, myVirtualToplevel|UART0|Add5~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add5~17\, myVirtualToplevel|UART0|Add5~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add5~21\, myVirtualToplevel|UART0|Add5~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_INTR~3\, myVirtualToplevel|UART0|RX_INTR~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add5~9\, myVirtualToplevel|UART0|Add5~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add5~13\, myVirtualToplevel|UART0|Add5~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add5~1\, myVirtualToplevel|UART0|Add5~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_INTR~1\, myVirtualToplevel|UART0|RX_INTR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add5~5\, myVirtualToplevel|UART0|Add5~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_INTR~4\, myVirtualToplevel|UART0|RX_INTR~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_INTR~5\, myVirtualToplevel|UART0|RX_INTR~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_INTR\, myVirtualToplevel|UART0|RX_INTR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[21]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~22\, myVirtualToplevel|UART0|RX_FIFO~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA~4\, myVirtualToplevel|UART0|RX_DATA~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[4]~5\, myVirtualToplevel|UART0|RX_DATA[4]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[4]\, myVirtualToplevel|UART0|RX_DATA[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~33\, myVirtualToplevel|IO_DATA_READ~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~24\, myVirtualToplevel|UART1|Add9~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~28\, myVirtualToplevel|UART1|Add9~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~17\, myVirtualToplevel|UART1|Add9~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~1\, myVirtualToplevel|UART1|Add9~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[4]~36\, myVirtualToplevel|IO_DATA_READ[4]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[4]\, myVirtualToplevel|IO_DATA_READ[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739\, myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~57\, myVirtualToplevel|\TIMER:TIMER1|Add0~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[0]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~45\, myVirtualToplevel|\TIMER:TIMER1|Add0~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[1]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~41\, myVirtualToplevel|\TIMER:TIMER1|Add0~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[2]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~29\, myVirtualToplevel|\TIMER:TIMER1|Add0~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~25\, myVirtualToplevel|\TIMER:TIMER1|Add0~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[4]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~37\, myVirtualToplevel|\TIMER:TIMER1|Add0~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[5]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~21\, myVirtualToplevel|\TIMER:TIMER1|Add0~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[6]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~61\, myVirtualToplevel|\TIMER:TIMER1|Add0~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[7]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~17\, myVirtualToplevel|\TIMER:TIMER1|Add0~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[8]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~33\, myVirtualToplevel|\TIMER:TIMER1|Add0~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[9]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~13\, myVirtualToplevel|\TIMER:TIMER1|Add0~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~9\, myVirtualToplevel|\TIMER:TIMER1|Add0~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~5\, myVirtualToplevel|\TIMER:TIMER1|Add0~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[12]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~1\, myVirtualToplevel|\TIMER:TIMER1|Add0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~53\, myVirtualToplevel|\TIMER:TIMER1|Add0~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[14]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add0~49\, myVirtualToplevel|\TIMER:TIMER1|Add0~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[15]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal0~3\, myVirtualToplevel|\TIMER:TIMER1|Equal0~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal0~1\, myVirtualToplevel|\TIMER:TIMER1|Equal0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal0~2\, myVirtualToplevel|\TIMER:TIMER1|Equal0~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|prescale_counter[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal0~0\, myVirtualToplevel|\TIMER:TIMER1|Equal0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal0~4\, myVirtualToplevel|\TIMER:TIMER1|Equal0~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|prescaled_tick\, myVirtualToplevel|\TIMER:TIMER1|prescaled_tick, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER_REG_REQ~feeder\, myVirtualToplevel|TIMER_REG_REQ~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|process_0~0\, myVirtualToplevel|process_0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER_REG_REQ\, myVirtualToplevel|TIMER_REG_REQ, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Mux2~1\, myVirtualToplevel|\TIMER:TIMER1|Mux2~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~1\, myVirtualToplevel|\TIMER:TIMER1|timer_enabled[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]\, myVirtualToplevel|\TIMER:TIMER1|timer_enabled[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][31]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~85\, myVirtualToplevel|\TIMER:TIMER1|Add1~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_index[0]~0\, myVirtualToplevel|\TIMER:TIMER1|timer_index[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_index[0]\, myVirtualToplevel|\TIMER:TIMER1|timer_index[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Mux2~0\, myVirtualToplevel|\TIMER:TIMER1|Mux2~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Mux2~2\, myVirtualToplevel|\TIMER:TIMER1|Mux2~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~22\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][0]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~97\, myVirtualToplevel|\TIMER:TIMER1|Add1~97, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~25\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][1]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~101\, myVirtualToplevel|\TIMER:TIMER1|Add1~101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~26\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][2]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~69\, myVirtualToplevel|\TIMER:TIMER1|Add1~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~18\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][3]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~73\, myVirtualToplevel|\TIMER:TIMER1|Add1~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~19\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][4]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~77\, myVirtualToplevel|\TIMER:TIMER1|Add1~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~20\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][5]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~89\, myVirtualToplevel|\TIMER:TIMER1|Add1~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~23\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][6]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~93\, myVirtualToplevel|\TIMER:TIMER1|Add1~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~24\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][7]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~113\, myVirtualToplevel|\TIMER:TIMER1|Add1~113, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~29\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][8]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~9\, myVirtualToplevel|\TIMER:TIMER1|Add1~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~3\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][9]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~13\, myVirtualToplevel|\TIMER:TIMER1|Add1~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~4\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][10]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~33\, myVirtualToplevel|\TIMER:TIMER1|Add1~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~9\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][11]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~81\, myVirtualToplevel|\TIMER:TIMER1|Add1~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~21\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][12]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~105\, myVirtualToplevel|\TIMER:TIMER1|Add1~105, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~27\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][13]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~109\, myVirtualToplevel|\TIMER:TIMER1|Add1~109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~28\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][14]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~41\, myVirtualToplevel|\TIMER:TIMER1|Add1~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~11\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][15]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][15]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~45\, myVirtualToplevel|\TIMER:TIMER1|Add1~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~12\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][16]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~65\, myVirtualToplevel|\TIMER:TIMER1|Add1~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~17\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][17]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~117\, myVirtualToplevel|\TIMER:TIMER1|Add1~117, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~30\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][18]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~121\, myVirtualToplevel|\TIMER:TIMER1|Add1~121, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~31\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][19]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~125\, myVirtualToplevel|\TIMER:TIMER1|Add1~125, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~32\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][20]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~25\, myVirtualToplevel|\TIMER:TIMER1|Add1~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~7\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][21]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~61\, myVirtualToplevel|\TIMER:TIMER1|Add1~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_NEW_REG913\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[22]_NEW_REG913, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_NEW_REG72\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_NEW_REG72, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[22]~12\, myVirtualToplevel|MEM_DATA_READ[22]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_ENABLE_FIFO~0\, myVirtualToplevel|UART0|TX_ENABLE_FIFO~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_ENABLE_FIFO\, myVirtualToplevel|UART0|TX_ENABLE_FIFO, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add8~9\, myVirtualToplevel|UART0|Add8~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_RESET~0\, myVirtualToplevel|UART0|TX_RESET~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_RESET\, myVirtualToplevel|UART0|TX_RESET, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~1\, myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal3~1\, myVirtualToplevel|Equal3~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_ENABLE~1\, myVirtualToplevel|UART0|TX_ENABLE~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_ENABLE\, myVirtualToplevel|UART0|TX_ENABLE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_OVERRUN~0\, myVirtualToplevel|UART0|TX_OVERRUN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_OVERRUN~1\, myVirtualToplevel|UART0|TX_OVERRUN~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add6~21\, myVirtualToplevel|UART0|Add6~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add6~25\, myVirtualToplevel|UART0|Add6~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add6~29\, myVirtualToplevel|UART0|Add6~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add6~9\, myVirtualToplevel|UART0|Add6~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add6~13\, myVirtualToplevel|UART0|Add6~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add6~17\, myVirtualToplevel|UART0|Add6~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add6~1\, myVirtualToplevel|UART0|Add6~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add8~1\, myVirtualToplevel|UART0|Add8~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add8~5\, myVirtualToplevel|UART0|Add8~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[7]\, myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add6~5\, myVirtualToplevel|UART0|Add6~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE\, myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add7~9\, myVirtualToplevel|UART0|Add7~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[1]\, myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal6~1\, myVirtualToplevel|UART0|Equal6~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE\, myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal6~0\, myVirtualToplevel|UART0|Equal6~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal6~2\, myVirtualToplevel|UART0|Equal6~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0\, myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]\, myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add7~13\, myVirtualToplevel|UART0|Add7~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]\, myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add7~17\, myVirtualToplevel|UART0|Add7~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[3]\, myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add7~21\, myVirtualToplevel|UART0|Add7~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[4]\, myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add7~25\, myVirtualToplevel|UART0|Add7~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]\, myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add7~1\, myVirtualToplevel|UART0|Add7~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[6]\, myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add7~5\, myVirtualToplevel|UART0|Add7~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[7]\, myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal5~0\, myVirtualToplevel|UART0|Equal5~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal5~1\, myVirtualToplevel|UART0|Equal5~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal5~2\, myVirtualToplevel|UART0|Equal5~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~37\, myVirtualToplevel|UART0|Add0~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~4\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~_wirecell\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER~0\, myVirtualToplevel|UART0|TX_COUNTER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[0]\, myVirtualToplevel|UART0|TX_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~21\, myVirtualToplevel|UART0|Add0~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[1]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[1]\, myVirtualToplevel|UART0|TX_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~25\, myVirtualToplevel|UART0|Add0~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~2\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~_wirecell\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[2]\, myVirtualToplevel|UART0|TX_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~29\, myVirtualToplevel|UART0|Add0~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~3\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~_wirecell\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE\, myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~49\, myVirtualToplevel|UART0|Add0~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~5\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~_wirecell\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[4]\, myVirtualToplevel|UART0|TX_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~53\, myVirtualToplevel|UART0|Add0~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~6\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~_wirecell\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[5]\, myVirtualToplevel|UART0|TX_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~1\, myVirtualToplevel|UART0|Add0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[6]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[6]\, myVirtualToplevel|UART0|TX_COUNTER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~33\, myVirtualToplevel|UART0|Add0~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr168~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~4_RESYN12768, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector982~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector982~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector982~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal141~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector982~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector983~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][0]~feeder\, myVirtualToplevel|SD_ADDR[0][0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][0]\, myVirtualToplevel|SD_ADDR[0][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[0]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|data_o[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux83~0\, myVirtualToplevel|Mux83~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[0]\, myVirtualToplevel|IO_DATA_READ_SD[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[0]\, myVirtualToplevel|INT_ENABLE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux86~0\, myVirtualToplevel|Mux86~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[0]~feeder\, myVirtualToplevel|IO_DATA_READ_SOCCFG[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[0]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]~feeder\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~18\, myVirtualToplevel|UART0|RX_FIFO~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA~16\, myVirtualToplevel|UART0|RX_DATA~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[0]~17\, myVirtualToplevel|UART0|RX_DATA[0]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[0]\, myVirtualToplevel|UART0|RX_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_EMPTY_V\, myVirtualToplevel|UART0|RX_EMPTY_V, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_EMPTY_V\, myVirtualToplevel|UART1|RX_EMPTY_V, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[17]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~18\, myVirtualToplevel|UART1|RX_FIFO~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA~16\, myVirtualToplevel|UART1|RX_DATA~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[0]~17\, myVirtualToplevel|UART1|RX_DATA[0]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[0]\, myVirtualToplevel|UART1|RX_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~92\, myVirtualToplevel|IO_DATA_READ~92, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~88\, myVirtualToplevel|IO_DATA_READ~88, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[0]~DUPLICATE\, myVirtualToplevel|SECOND_DOWN_COUNTER[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~89\, myVirtualToplevel|IO_DATA_READ~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~90\, myVirtualToplevel|IO_DATA_READ~90, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~91\, myVirtualToplevel|IO_DATA_READ~91, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~93\, myVirtualToplevel|IO_DATA_READ~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[0]\, myVirtualToplevel|IO_DATA_READ[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743\, myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[0]~94\, myVirtualToplevel|MEM_DATA_READ[0]~94, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate\, myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector358~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[26]~78\, myVirtualToplevel|IO_DATA_READ[26]~78, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[24]~86\, myVirtualToplevel|IO_DATA_READ[24]~86, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~73\, myVirtualToplevel|Add17~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[7]\, myVirtualToplevel|MILLISEC_UP_COUNTER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~77\, myVirtualToplevel|Add17~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~57\, myVirtualToplevel|Add17~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[9]\, myVirtualToplevel|MILLISEC_UP_COUNTER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~61\, myVirtualToplevel|Add17~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[10]\, myVirtualToplevel|MILLISEC_UP_COUNTER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~65\, myVirtualToplevel|Add17~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[11]\, myVirtualToplevel|MILLISEC_UP_COUNTER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~33\, myVirtualToplevel|Add17~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~37\, myVirtualToplevel|Add17~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[13]\, myVirtualToplevel|MILLISEC_UP_COUNTER[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~41\, myVirtualToplevel|Add17~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[14]\, myVirtualToplevel|MILLISEC_UP_COUNTER[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~45\, myVirtualToplevel|Add17~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~1\, myVirtualToplevel|Add17~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[16]\, myVirtualToplevel|MILLISEC_UP_COUNTER[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~21\, myVirtualToplevel|Add17~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[17]\, myVirtualToplevel|MILLISEC_UP_COUNTER[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~25\, myVirtualToplevel|Add17~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~29\, myVirtualToplevel|Add17~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~13\, myVirtualToplevel|Add17~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~5\, myVirtualToplevel|Add17~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~9\, myVirtualToplevel|Add17~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[22]\, myVirtualToplevel|MILLISEC_UP_COUNTER[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~17\, myVirtualToplevel|Add17~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[23]\, myVirtualToplevel|MILLISEC_UP_COUNTER[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~121\, myVirtualToplevel|Add17~121, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]_NEW3035\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[24]_NEW3035, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]_NEW3163\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[24]_NEW3163, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]_NEW2971\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[24]_NEW2971, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]_NEW3099\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[24]_NEW3099, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux18~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]_NEW2715\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[24]_NEW2715, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]_NEW2843\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[24]_NEW2843, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]_NEW2907\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[24]_NEW2907, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]_NEW2779\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[24]_NEW2779, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux18~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux18~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[24]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[24]\, myVirtualToplevel|MILLISEC_UP_COUNTER[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[24]~87\, myVirtualToplevel|IO_DATA_READ[24]~87, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[24]\, myVirtualToplevel|IO_DATA_READ[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux87~0\, myVirtualToplevel|Mux87~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[24]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector7~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector7~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[8]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[24]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][24]~feeder\, myVirtualToplevel|SD_ADDR[0][24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][24]\, myVirtualToplevel|SD_ADDR[0][24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[24]\, myVirtualToplevel|IO_DATA_READ_SD[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[18]~6\, myVirtualToplevel|MEM_DATA_READ[18]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[24]~60\, myVirtualToplevel|MEM_DATA_READ[24]~60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_NEW_REG14\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_NEW_REG14, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[8]~input\, SDRAM_DQ[8]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_NEW_REG16\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_NEW_REG16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node[1]\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node[0]\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[24]~61\, myVirtualToplevel|MEM_DATA_READ[24]~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[24]~62\, myVirtualToplevel|MEM_DATA_READ[24]~62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector358~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~89\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~98\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~98, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~103\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~103, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~94\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~94, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~89\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~52\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~75\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~75, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~80\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~80, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~66\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~66, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~71\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~71, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~35\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~39\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~43\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~47\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~22\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~26\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~30\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector983~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[20]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~21\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~22\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[17]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[17]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[1]~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector983~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector983~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector983~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector983~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1\, myVirtualToplevel|\ZPUEVO:ZPU0|RESULT~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector983~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector983~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector300~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[25]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[1]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[1]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~109\, myVirtualToplevel|Add17~109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[25]\, myVirtualToplevel|MILLISEC_UP_COUNTER[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~113\, myVirtualToplevel|Add17~113, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[26]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~117\, myVirtualToplevel|Add17~117, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_RESYN8993\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~9_RESYN8993, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector974~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~256\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][3]~256, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~257\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][3]~257, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~249\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][3]~249, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~248\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][3]~248, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux154~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~268\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][3]~268, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~261\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][3]~261, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~269\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][3]~269, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~260\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][3]~260, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux154~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][13]~438, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][13]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][13]~437, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][13]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]_NEW1840\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][3]_NEW1840, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]_NEW1838\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][3]_NEW1838, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~253\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][3]~253, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~252\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][3]~252, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux154~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~265\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][3]~265, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~264\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][3]~264, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~273\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][3]~273, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~272\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][3]~272, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux154~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux154~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~259\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][3]~259, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~275\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][3]~275, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~271\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][3]~271, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~255\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][3]~255, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux154~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~254\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][3]~254, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~270\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][3]~270, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~274\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][3]~274, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~258\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][3]~258, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux154~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~266\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][3]~266, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~250\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][3]~250, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~246\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][3]~246, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux154~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~247\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][3]~247, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~251\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][3]~251, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~267\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][3]~267, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux154~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux154~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux154~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan17~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan17~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan17~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux161~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux161~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux161~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux161~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux161~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux168~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux168~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux168~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux168~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux168~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux168~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux168~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux168~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux168~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux168~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux168~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~346\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][7]~346, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~350\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][7]~350, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~355\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][7]~355, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~354\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][7]~354, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~344\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][7]~344, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~348\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][7]~348, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~360\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][7]~360, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~361\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][7]~361, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux184~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~349\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][7]~349, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~345\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][7]~345, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~18\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~365\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][7]~365, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~364\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][7]~364, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~16\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~359\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][7]~359, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~358\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][7]~358, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~347\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][7]~347, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~19\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux184~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]_NEW3159\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[18]_NEW3159, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]_NEW3095\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[18]_NEW3095, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]_NEW2967\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[18]_NEW2967, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]_NEW3031\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[18]_NEW3031, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux24~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]_NEW2711\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[18]_NEW2711, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]_NEW2839\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[18]_NEW2839, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]_NEW2903\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[18]_NEW2903, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]_NEW2775\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[18]_NEW2775, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux24~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux24~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[18]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[2]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[2]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[19]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[3]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[3]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[20]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[4]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[4]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]~27\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[21]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[5]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[5]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]_NEW2703\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[22]_NEW2703, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]_NEW2895\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[22]_NEW2895, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]_NEW2831\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[22]_NEW2831, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]_NEW2767\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[22]_NEW2767, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux20~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]_NEW3087\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[22]_NEW3087, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]_NEW3023\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[22]_NEW3023, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]_NEW3151\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[22]_NEW3151, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]_NEW2959\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[22]_NEW2959, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux20~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux20~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[22]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[6]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[6]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux88~0\, myVirtualToplevel|Mux88~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[23]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector8~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector8~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[7]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[23]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][23]\, myVirtualToplevel|SD_ADDR[0][23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[23]\, myVirtualToplevel|IO_DATA_READ_SD[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1262\, myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1262, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~40\, myVirtualToplevel|UART1|Add10~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~38\, myVirtualToplevel|UART1|Add10~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~37\, myVirtualToplevel|UART1|Add10~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~39\, myVirtualToplevel|UART1|Add10~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~43\, myVirtualToplevel|UART1|Add10~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~42\, myVirtualToplevel|UART1|Add10~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~41\, myVirtualToplevel|UART1|Add10~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~32\, myVirtualToplevel|UART1|Add10~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~35\, myVirtualToplevel|UART1|Add10~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~1\, myVirtualToplevel|UART1|Add10~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~21\, myVirtualToplevel|UART1|Add10~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~25\, myVirtualToplevel|UART1|Add10~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~29\, myVirtualToplevel|UART1|Add10~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~13\, myVirtualToplevel|UART1|Add10~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~5\, myVirtualToplevel|UART1|Add10~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~9\, myVirtualToplevel|UART1|Add10~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add10~17\, myVirtualToplevel|UART1|Add10~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~15\, myVirtualToplevel|IO_DATA_READ~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[23]_NEW_REG1304\, myVirtualToplevel|IO_DATA_READ[23]_NEW_REG1304, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1260\, myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1260, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~25\, myVirtualToplevel|Add13~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~29\, myVirtualToplevel|Add13~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[19]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~13\, myVirtualToplevel|Add13~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~5\, myVirtualToplevel|Add13~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~9\, myVirtualToplevel|Add13~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add13~17\, myVirtualToplevel|Add13~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~16\, myVirtualToplevel|IO_DATA_READ~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[23]_NEW_REG1306\, myVirtualToplevel|IO_DATA_READ[23]_NEW_REG1306, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~17\, myVirtualToplevel|IO_DATA_READ~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[23]~17\, myVirtualToplevel|MEM_DATA_READ[23]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_NEW_REG68\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_NEW_REG68, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[23]~18\, myVirtualToplevel|MEM_DATA_READ[23]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[23]~19\, myVirtualToplevel|MEM_DATA_READ[23]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]~25\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[23]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[7]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[7]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~340\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][7]~340, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~336\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][7]~336, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]_NEW1828\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][7]_NEW1828, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]_NEW1826\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][7]_NEW1826, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~342\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][7]~342, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~338\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][7]~338, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~353\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][7]~353, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~352\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][7]~352, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux184~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~339\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][7]~339, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~343\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][7]~343, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~341\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][7]~341, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~356\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][7]~356, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~357\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][7]~357, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~363\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][7]~363, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~362\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][7]~362, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux184~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux184~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux183~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux183~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux183~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux183~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux183~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux183~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux183~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux183~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux183~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux183~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux183~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_RESYN12678\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan25~4_RESYN12678, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan25~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_RESYN12670\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan25~1_RESYN12670, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan25~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan19~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector386~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux181~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux181~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux181~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux181~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux181~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux181~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux181~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux181~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux181~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux181~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector386~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~37\, myVirtualToplevel|MEM_DATA_READ[2]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~38\, myVirtualToplevel|MEM_DATA_READ[2]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_RESYN12778\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~90_RESYN12778, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~90, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~119_RESYN8671, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~119, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~120\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~120, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8669\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~116_RESYN8669, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~109\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~105\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~105, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~101\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~97\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~97, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~113\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~113, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~117\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~117, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~160\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~160, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~155\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~155, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~156\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~156, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~127_RESYN8675, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~127_RESYN8673, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~127, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~128\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~128, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~129\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~129, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8677\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~134_RESYN8677, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~93\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~89\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~93\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~109\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~105\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~105, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~101\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~97\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~97, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~113\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~113, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~117\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~117, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~121\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~121, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~121\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~121, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~148_RESYN9275, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~137\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~137, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~18\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~120\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~120, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~116\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~116, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~112\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~112, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~108\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~108, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~124\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~124, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~128\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~128, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~132\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~132, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~144\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~144, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~142\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~142, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~44\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9025\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~146_RESYN9025, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9027\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~146_RESYN9027, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9029\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~146_RESYN9029, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~146, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8685\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~141_RESYN8685, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8683\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~141_RESYN8683, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~141, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[31]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[19]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[19]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]_NEW1708\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[0]_NEW1708, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~89\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~93\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]_NEW1710\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[1]_NEW1710, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[2]_NEW1712\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[2]_NEW1712, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[3]_NEW1714\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[3]_NEW1714, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[4]_NEW1716\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[4]_NEW1716, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[5]_NEW1718\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[5]_NEW1718, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]_NEW1720\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[6]_NEW1720, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]_NEW1722\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[7]_NEW1722, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[8]_NEW1724\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[8]_NEW1724, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]_NEW1726\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[9]_NEW1726, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[10]_NEW1728\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[10]_NEW1728, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[11]_NEW1730\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[11]_NEW1730, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[12]_NEW1736\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[12]_NEW1736, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[13]_NEW1630\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[13]_NEW1630, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[14]_NEW1732\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[14]_NEW1732, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[15]_NEW1734\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[15]_NEW1734, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]_NEW1752\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[16]_NEW1752, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[17]_NEW1742\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[17]_NEW1742, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]_NEW1740\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[18]_NEW1740, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[19]_NEW1738\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[19]_NEW1738, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[20]_NEW1746\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[20]_NEW1746, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]_NEW1750\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[21]_NEW1750, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[22]_NEW1748\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[22]_NEW1748, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[23]_NEW1744\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[23]_NEW1744, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~125\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~125, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[24]_NEW1692\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[24]_NEW1692, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~121\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~121, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[25]_NEW1694\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[25]_NEW1694, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~109\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[26]_NEW1696\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[26]_NEW1696, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~117\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~117, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[27]_NEW1698\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[27]_NEW1698, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~113\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~113, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[28]_NEW1700\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[28]_NEW1700, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~101\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[29]_NEW1702\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[29]_NEW1702, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~105\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~105, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]_NEW1704\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[30]_NEW1704, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_NEW_REG795\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[30]_NEW_REG795, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_NEW_REG793\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[30]_NEW_REG793, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_NEW_REG791\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[30]_NEW_REG791, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_NEW_REG787\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[30]_NEW_REG787, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_NEW_REG789\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[30]_NEW_REG789, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~30\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~373, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~358\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~358, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~362\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~362, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~350\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~350, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~342\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~342, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~346\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~346, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~354\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~354, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~719\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~719, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~715\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~715, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~711\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~711, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~707\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~707, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~723\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~723, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~727\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~727, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~731\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~731, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~147\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~147, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9277\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~148_RESYN9277, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~148, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[12]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[28]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][28]\, myVirtualToplevel|SD_ADDR[0][28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[28]\, myVirtualToplevel|IO_DATA_READ_SD[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[28]~40\, myVirtualToplevel|MEM_DATA_READ[28]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[4]~0\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[4]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_NEW_REG90\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_NEW_REG90, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[12]~input\, SDRAM_DQ[12]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_NEW_REG92\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_NEW_REG92, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~79\, myVirtualToplevel|IO_DATA_READ~79, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[28]\, myVirtualToplevel|IO_DATA_READ[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[28]~39\, myVirtualToplevel|MEM_DATA_READ[28]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[28]~41\, myVirtualToplevel|MEM_DATA_READ[28]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector985~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~366\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][6]~366, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector298~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector298~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[27]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[27]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[3]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[3]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]_NEW2949\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[28]_NEW2949, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[28]_NEW3077\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[28]_NEW3077, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[28]_NEW3013\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[28]_NEW3013, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[28]_NEW3141\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[28]_NEW3141, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux14~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[28]_NEW2885\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[28]_NEW2885, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[28]_NEW2693\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[28]_NEW2693, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[28]_NEW2821\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[28]_NEW2821, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[28]_NEW2757\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[28]_NEW2757, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux14~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux14~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector297~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector297~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[28]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[28]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[4]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[4]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_NEW_REG767\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[29]_NEW_REG767, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[29]_NEW3139\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[29]_NEW3139, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[29]_NEW2947\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[29]_NEW2947, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[29]_NEW3011\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[29]_NEW3011, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[29]_NEW3075\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[29]_NEW3075, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux13~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[29]_NEW2819\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[29]_NEW2819, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[29]_NEW2691\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[29]_NEW2691, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[29]_NEW2755\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[29]_NEW2755, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[29]_NEW2883\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[29]_NEW2883, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux13~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux13~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector296~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector296~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_NEW_REG769\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[29]_NEW_REG769, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[29]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[5]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[5]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[30]_NEW3073\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[30]_NEW3073, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[30]_NEW3137\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[30]_NEW3137, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[30]_NEW2945\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[30]_NEW2945, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[30]_NEW3009\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[30]_NEW3009, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux12~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[30]_NEW2817\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[30]_NEW2817, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[30]_NEW2753\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[30]_NEW2753, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[30]_NEW2881\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[30]_NEW2881, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[30]_NEW2689\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[30]_NEW2689, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux12~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux12~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector295~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector295~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[30]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[30]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[6]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[6]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[31]_NEW3085\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[31]_NEW3085, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[31]_NEW3149\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[31]_NEW3149, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[31]_NEW3021\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[31]_NEW3021, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[31]_NEW2957\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[31]_NEW2957, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux11~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[31]_NEW2701\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[31]_NEW2701, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[31]_NEW2765\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[31]_NEW2765, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[31]_NEW2829\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[31]_NEW2829, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[31]_NEW2893\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[31]_NEW2893, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux11~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux11~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector294~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector294~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_NEW_REG765\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[31]_NEW_REG765, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_NEW_REG763\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[31]_NEW_REG763, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[31]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[7]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[7]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~367\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][6]~367, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~371\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][6]~371, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~370\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][6]~370, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux158~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~369\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][6]~369, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~368\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][6]~368, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]_NEW1822\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][6]_NEW1822, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]_NEW1824\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][6]_NEW1824, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux158~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~387\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][6]~387, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~386\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][6]~386, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux158~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~384\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][6]~384, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~385\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][6]~385, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~380\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][6]~380, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~381\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][6]~381, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux158~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux158~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_RESYN8957\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector386~8_RESYN8957, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector386~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8749\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~5_RESYN8749, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1326~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_NEW_REG799\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[28]_NEW_REG799, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[20]_NEW_REG1212\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[20]_NEW_REG1212, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~3\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8745\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~5_RESYN8745, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN9337\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN9337, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12594\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12594, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector985~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector985~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12592\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12592, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9335\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9335, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~14\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~14\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~21\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~23\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~15\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~16\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_RESYN13470\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_RESYN13470, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~3_RESYN8963, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~3_RESYN8965, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux151~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux151~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux151~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux151~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux151~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux151~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux151~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux151~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~383\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][6]~383, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux151~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux151~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux151~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector985~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8967\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~3_RESYN8967, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1327~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~6\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~242\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][2]~242, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~243\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][2]~243, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~235\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][2]~235, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~234\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][2]~234, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux155~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~239\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][2]~239, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~230\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][2]~230, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~231\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][2]~231, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~238\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][2]~238, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux155~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]_NEW1842\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][2]_NEW1842, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]_NEW1844\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][2]_NEW1844, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~223\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][2]~223, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~222\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][2]~222, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux155~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~218\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][2]~218, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~219\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][2]~219, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~227\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][2]~227, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux155~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux155~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~244\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][2]~244, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~228\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][2]~228, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~224\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][2]~224, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~240\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][2]~240, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux155~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~237\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][2]~237, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~233\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][2]~233, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~221\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][2]~221, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~217\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][2]~217, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux155~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~241\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][2]~241, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~225\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][2]~225, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~245\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][2]~245, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~229\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][2]~229, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux155~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~232\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][2]~232, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~220\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][2]~220, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~236\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][2]~236, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~216\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][2]~216, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux155~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux155~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux155~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~0\, myVirtualToplevel|\ZPUEVO:ZPU0|RESULT~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux162~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux162~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux162~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux162~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux162~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~4\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~4\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~5\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~89\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~93\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector989~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[16]_NEW_REG1238\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[16]_NEW_REG1238, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~0\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1331~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1331~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1331~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1331~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[15]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector990~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~287\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][1]~287, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~278\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][1]~278, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~279\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][1]~279, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~286\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][1]~286, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux156~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~291\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][1]~291, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~298\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][1]~298, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~299\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][1]~299, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~290\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][1]~290, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux156~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]_NEW1848\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][1]_NEW1848, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~283\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][1]~283, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]_NEW1846\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][1]_NEW1846, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~282\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][1]~282, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux156~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~295\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][1]~295, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~303\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][1]~303, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~294\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][1]~294, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~302\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][1]~302, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux156~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux156~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~280\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][1]~280, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~276\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][1]~276, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~292\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][1]~292, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux156~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~281\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][1]~281, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~293\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][1]~293, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux156~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~289\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][1]~289, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~305\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][1]~305, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~301\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][1]~301, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~285\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][1]~285, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux156~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~300\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][1]~300, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~304\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][1]~304, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~288\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][1]~288, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~284\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][1]~284, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux156~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux156~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux156~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector990~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_NEW_REG1182\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[15]_NEW_REG1182, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_NEW_REG1180\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[15]_NEW_REG1180, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_NEW_REG1184\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[15]_NEW_REG1184, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~11\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1332~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1332~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1332~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~5\, myVirtualToplevel|\ZPUEVO:ZPU0|RESULT~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector990~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1332~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux163~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux163~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux163~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux163~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux163~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector990~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector990~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~50\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~40\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector990~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector990~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector990~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~37\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~39\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~32\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~19\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~37\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~38\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector990~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1332~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1332~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[14]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~10\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1333~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1333~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1333~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~319\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][0]~319, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~311\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][0]~311, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~327\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][0]~327, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~335\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][0]~335, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux157~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~310\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][0]~310, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~326\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][0]~326, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~318\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][0]~318, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan11~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~435\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][0]~435, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~436\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][0]~436, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~334\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][0]~334, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux157~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~323\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][0]~323, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~331\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][0]~331, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~315\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][0]~315, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~307\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][0]~307, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux157~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~322\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][0]~322, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~314\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][0]~314, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~330\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][0]~330, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~306\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][0]~306, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux157~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux157~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~316\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][0]~316, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~312\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][0]~312, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~313\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][0]~313, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~317\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][0]~317, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux157~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~320\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][0]~320, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~325\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][0]~325, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~321\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][0]~321, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux157~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~308\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][0]~308, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]_NEW1832\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][0]_NEW1832, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]_NEW1830\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][0]_NEW1830, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux157~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~329\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][0]~329, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~332\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][0]~332, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~333\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][0]~333, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~328\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][0]~328, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux157~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux157~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux157~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux164~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux164~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux164~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux164~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux164~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8709\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~15_RESYN8709, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~26\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8705\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~15_RESYN8705, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~30\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_RESYN9111\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~15_RESYN8707_RESYN9111, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~15_RESYN8707, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8711\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~15_RESYN8711, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector991~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1333~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8979\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1334~3_RESYN8979, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9345\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9345, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9349\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9349, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9347\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9347, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1334~3_RESYN8983, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_RESYN9251\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1334~4_RESYN9251, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector992~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector992~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~35\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector992~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~24\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~36\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector992~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector992~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux165~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux165~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux165~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux165~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux165~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux165~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux165~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux165~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux165~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux165~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux165~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector992~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_NEW_REG1186\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[13]_NEW_REG1186, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_NEW_REG1188\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[13]_NEW_REG1188, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~9\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1334~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1334~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1334~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector992~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1334~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[12]_NEW_REG1240\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[12]_NEW_REG1240, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[0]_OTERM1209~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~8\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1335~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1335~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1335~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8977\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1335~3_RESYN8977, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8975\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1335~3_RESYN8975, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1335~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~418\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][5]~418, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~411\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][5]~411, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~419\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][5]~419, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~410\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][5]~410, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux166~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~396\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][5]~396, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~405\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][5]~405, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~397\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][5]~397, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~404\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][5]~404, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux166~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~413\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][5]~413, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~421\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][5]~421, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~412\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][5]~412, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~420\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][5]~420, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux166~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~402\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][5]~402, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~403\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][5]~403, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]_NEW1820\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][5]_NEW1820, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]_NEW1818\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][5]_NEW1818, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux166~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux166~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~406\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][5]~406, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~408\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][5]~408, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~424\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][5]~424, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~422\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][5]~422, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux166~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~399\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][5]~399, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~415\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][5]~415, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~417\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][5]~417, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~401\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][5]~401, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux166~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~423\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][5]~423, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~407\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][5]~407, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~409\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][5]~409, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~425\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][5]~425, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux166~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~398\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][5]~398, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~414\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][5]~414, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~416\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][5]~416, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~400\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][5]~400, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux166~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux166~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux166~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~34\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~31\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~22\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~33\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~34\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~19\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux159~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux152~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux152~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux152~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux152~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux152~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux152~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux152~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux152~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux152~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux152~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux152~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux180~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux180~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux180~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux180~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux180~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_RESYN12770\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~5_RESYN12770, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1335~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector995~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~62\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector995~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector995~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector995~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector995~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector995~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector995~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector995~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector995~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector995~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector995~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~34\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~56\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~11\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~10\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~57\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~39\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~59\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~60\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~13\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~47\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~58\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~61\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector995~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_NEW_REG901\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[25]_NEW_REG901, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_NEW_REG1230\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[10]_NEW_REG1230, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_NEW_REG1228\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[10]_NEW_REG1228, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~15\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1337~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1337~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1337~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1337~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[9]_NEW_REG1248\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[9]_NEW_REG1248, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~14\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1338~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1338~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector996~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector996~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector996~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~55\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~64\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~64, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector996~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector996~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector996~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector996~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector996~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1338~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector996~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector996~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector996~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux169~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux169~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux169~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux169~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux169~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux169~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux169~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux169~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux169~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux169~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux169~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~53\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~54\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~7\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~50\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~49\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~9\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~51\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~52\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector996~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1338~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector996~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1338~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector998~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector998~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[26]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~70\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~70, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~71\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~71, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~6\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~39\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~165\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~165, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector998~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1340~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector998~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector998~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector998~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~83\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~83, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~72\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~72, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector998~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector998~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector998~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector998~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector998~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[7]_NEW_REG1246\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[7]_NEW_REG1246, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_NEW_REG1206\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[0]_NEW_REG1206, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~18\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1340~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1340~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1340~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector998~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1340~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux172~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux172~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux172~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux172~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux172~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~69\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~78\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~78, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[6]_NEW_REG1242\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[6]_NEW_REG1242, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~17\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1341~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1341~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1341~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~68\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~68, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~37\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~13\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~4\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~19\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector999~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1341~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux173~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux173~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux173~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux173~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux173~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~2\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~9\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~33\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~46\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~48\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1000~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[5]_NEW_REG1244\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[5]_NEW_REG1244, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~13\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1342~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1342~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1342~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1342~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector354~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector354~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector354~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector354~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~82\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~82, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~21\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1345~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1345~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1345~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux176~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux176~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux176~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux176~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux176~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~23\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~81\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~44\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~45\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~80\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~80, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~78\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~78, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~79\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~79, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1003~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1345~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector350~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector350~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector347~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector347~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~109\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~105\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~105, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~101\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~97\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~97, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~113\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~113, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~117\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~117, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~121\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~121, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[30]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[30]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~75\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~75, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~130\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~130, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8679\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~134_RESYN8679, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8681\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~134_RESYN8681, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~134, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_NEW_REG899\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[25]_NEW_REG899, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[29]_NEW_REG969\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[29]_NEW_REG969, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~29\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~135\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~135, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~157\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~157, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~136\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~136, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8667\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~116_RESYN8667, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~112\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~112, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~113\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~113, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~116, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~121\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~121, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9263\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~123_RESYN9263, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9267\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~123_RESYN9267, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_NEW_REG797\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[28]_NEW_REG797, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~28\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~122\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~122, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9269\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~123_RESYN9269, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~123, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[28]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[28]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[28]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy~0\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97\, myVirtualToplevel|\ZPUEVO:ZPU0|Add60~97, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[58]_NEW1684\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[58]_NEW1684, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[57]_NEW1682\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[57]_NEW1682, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[59]_NEW1686\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[59]_NEW1686, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[60]_NEW1688\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[60]_NEW1688, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[61]_NEW1690\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[61]_NEW1690, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~20\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1344~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1344~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~77\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~92\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~92, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1344~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux175~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux175~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux175~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux175~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux175~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6\, myVirtualToplevel|\ZPUEVO:ZPU0|RESULT~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~76\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~76, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~42\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~43\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~20\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~15\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1002~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1344~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal145~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~16\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~43\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder11~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~24\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1320~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1320~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1320~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8649\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~13_RESYN8649, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8651\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~13_RESYN8651, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8647\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~13_RESYN8647, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector978~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1320~3_RESYN8995, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8997\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1320~3_RESYN8997, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8999\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1320~3_RESYN8999, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1320~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[27]_NEW2951\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[27]_NEW2951, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[27]_NEW3015\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[27]_NEW3015, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[27]_NEW3143\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[27]_NEW3143, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[27]_NEW3079\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[27]_NEW3079, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux15~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[27]_NEW2887\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[27]_NEW2887, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[27]_NEW2823\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[27]_NEW2823, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[27]_NEW2695\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[27]_NEW2695, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[27]_NEW2759\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[27]_NEW2759, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux15~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux15~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[27]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[27]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[27]\, myVirtualToplevel|MILLISEC_UP_COUNTER[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~93\, myVirtualToplevel|Add17~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[28]\, myVirtualToplevel|MILLISEC_UP_COUNTER[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~97\, myVirtualToplevel|Add17~97, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[29]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[29]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[29]\, myVirtualToplevel|MILLISEC_UP_COUNTER[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~101\, myVirtualToplevel|Add17~101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[30]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[30]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[30]\, myVirtualToplevel|MILLISEC_UP_COUNTER[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add17~105\, myVirtualToplevel|Add17~105, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[31]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[31]\, myVirtualToplevel|MILLISEC_UP_COUNTER[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~82\, myVirtualToplevel|IO_DATA_READ~82, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[31]\, myVirtualToplevel|IO_DATA_READ[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector0~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[15]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[31]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][31]\, myVirtualToplevel|SD_ADDR[0][31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[31]\, myVirtualToplevel|IO_DATA_READ_SD[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[31]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[31]~48\, myVirtualToplevel|MEM_DATA_READ[31]~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_NEW_REG78\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_NEW_REG78, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[15]~input\, SDRAM_DQ[15]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_NEW_REG80\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_NEW_REG80, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~29\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[7]~3\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[7]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[31]~49\, myVirtualToplevel|MEM_DATA_READ[31]~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[31]~50\, myVirtualToplevel|MEM_DATA_READ[31]~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector974~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector974~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector974~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector974~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector974~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~136\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~136, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector974~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector974~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~125\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~125, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~48\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~49\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector974~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector974~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7\, myVirtualToplevel|\ZPUEVO:ZPU0|RESULT~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add33~125\, myVirtualToplevel|\ZPUEVO:ZPU0|Add33~125, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector974~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector974~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector974~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~735\, myVirtualToplevel|\ZPUEVO:ZPU0|Mult0~735, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9033\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1316~2_RESYN9033, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]_NEW1706\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[31]_NEW1706, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~31\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_NEW_REG522\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[31]_NEW_REG522, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_67\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_67, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_NEW_REG516\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[31]_NEW_REG516, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[31]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_63\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_63, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_NEW_REG514\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[31]_NEW_REG514, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_NEW_REG520\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[31]_NEW_REG520, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_NEW_REG518\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[31]_NEW_REG518, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~32\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9031\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1316~2_RESYN9031, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1316~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1316~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add7~125\, myVirtualToplevel|\ZPUEVO:ZPU0|Add7~125, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[31]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_RESYN12772\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~10_RESYN12772, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_RESYN12802\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~23_RESYN12802, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_RESYN9011\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[26]~14_RESYN9011, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[26]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~93\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux150~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux150~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux150~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux150~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux150~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux150~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux150~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux150~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~16\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux150~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_RESYN12546\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[26]~15_RESYN12546, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux181~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[26]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~88\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~88, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~95\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~95, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~149\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~149, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_RESYN8655\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~94_RESYN8655, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~94, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[26]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~92\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~92, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~150\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~150, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~96\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~96, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~91\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~91, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~97\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~97, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12774\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12774, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN9003\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~11_RESYN9003, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12776\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12776, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[26]_NEW_REG903\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[26]_NEW_REG903, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~25\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~98\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~98, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~99\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~99, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~100\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~100, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[26]_NEW2953\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[26]_NEW2953, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[26]_NEW3145\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[26]_NEW3145, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]_NEW3017\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[26]_NEW3017, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]_NEW3081\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[26]_NEW3081, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux16~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[26]_NEW2697\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[26]_NEW2697, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[26]_NEW2761\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[26]_NEW2761, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[26]_NEW2889\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[26]_NEW2889, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[26]_NEW2825\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[26]_NEW2825, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux16~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux16~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector299~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector299~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_NEW_REG761\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[26]_NEW_REG761, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_NEW_REG759\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[26]_NEW_REG759, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[26]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[2]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[2]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~337\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][7]~337, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~20\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~27\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~28\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~31\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~30\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux179~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~22\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux179~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_RESYN12674\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~5_RESYN12674, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8633\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector983~3_RESYN8633, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~10\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~12\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~17\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~13\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~11\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector983~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8631\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector983~3_RESYN8631, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector983~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[22]_NEW_REG1174\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[22]_NEW_REG1174, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~2\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1325~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1325~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1325~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1325~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector982~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~18\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~19\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_NEW_REG895\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[23]_NEW_REG895, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_NEW_REG889\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[23]_NEW_REG889, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[23]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add35~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add35~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector982~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector982~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector982~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~2\, myVirtualToplevel|\ZPUEVO:ZPU0|RESULT~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9109\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_RESYN8969\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector982~3_RESYN8969, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector982~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~17\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~28\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~18\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector982~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector982~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9107\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9107, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1324~4_RESYN8635, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8973\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1324~4_RESYN8973, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_NEW_REG1170\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[23]_NEW_REG1170, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_NEW_REG1168\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[23]_NEW_REG1168, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_NEW_REG1172\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[23]_NEW_REG1172, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~4\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1324~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1324~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8971\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1324~4_RESYN8971, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1324~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[23]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[23]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[23]_NEW2973\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[23]_NEW2973, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[23]_NEW3165\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[23]_NEW3165, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[23]_NEW3101\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[23]_NEW3101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[23]_NEW3037\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[23]_NEW3037, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux19~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[23]_NEW2781\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[23]_NEW2781, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]_NEW2909\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[23]_NEW2909, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[23]_NEW2845\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[23]_NEW2845, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[23]_NEW2717\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[23]_NEW2717, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux19~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux19~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector11~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector11~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector269~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector269~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_NEW_REG935\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[23]_NEW_REG935, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_NEW_REG933\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[23]_NEW_REG933, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~feeder\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[7]\, myVirtualToplevel|UART0|TX_COUNTER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~17\, myVirtualToplevel|UART0|Add0~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[8]~feeder\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[8]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[8]\, myVirtualToplevel|UART0|TX_COUNTER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~9\, myVirtualToplevel|UART0|Add0~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[9]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[9]\, myVirtualToplevel|UART0|TX_COUNTER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~13\, myVirtualToplevel|UART0|Add0~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~1\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~_wirecell\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[10]\, myVirtualToplevel|UART0|TX_COUNTER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~41\, myVirtualToplevel|UART0|Add0~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[11]~feeder\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[11]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[11]\, myVirtualToplevel|UART0|TX_COUNTER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~45\, myVirtualToplevel|UART0|Add0~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[12]~feeder\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[12]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[12]\, myVirtualToplevel|UART0|TX_COUNTER[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal0~2\, myVirtualToplevel|UART0|Equal0~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~57\, myVirtualToplevel|UART0|Add0~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[13]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[13]\, myVirtualToplevel|UART0|TX_COUNTER[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~61\, myVirtualToplevel|UART0|Add0~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[14]~feeder\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[14]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[14]~DUPLICATE\, myVirtualToplevel|UART0|TX_COUNTER[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add0~5\, myVirtualToplevel|UART0|Add0~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[15]\, myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[15]\, myVirtualToplevel|UART0|TX_COUNTER[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal0~0\, myVirtualToplevel|UART0|Equal0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[14]\, myVirtualToplevel|UART0|TX_COUNTER[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal0~3\, myVirtualToplevel|UART0|Equal0~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_COUNTER[3]\, myVirtualToplevel|UART0|TX_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal0~1\, myVirtualToplevel|UART0|Equal0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal0~4\, myVirtualToplevel|UART0|Equal0~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK~0\, myVirtualToplevel|UART0|TX_CLOCK~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_CLOCK\, myVirtualToplevel|UART0|TX_CLOCK, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[16]~9\, myVirtualToplevel|UART0|TX_BUFFER[16]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[0]~0\, myVirtualToplevel|UART0|TX_DATA[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[0]~0\, myVirtualToplevel|UART0|TX_BUFFER[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[16]\, myVirtualToplevel|UART0|TX_BUFFER[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER~8\, myVirtualToplevel|UART0|TX_BUFFER~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[15]\, myVirtualToplevel|UART0|TX_BUFFER[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER~7\, myVirtualToplevel|UART0|TX_BUFFER~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[14]\, myVirtualToplevel|UART0|TX_BUFFER[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER~6\, myVirtualToplevel|UART0|TX_BUFFER~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[13]\, myVirtualToplevel|UART0|TX_BUFFER[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER~5\, myVirtualToplevel|UART0|TX_BUFFER~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[12]\, myVirtualToplevel|UART0|TX_BUFFER[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER~4\, myVirtualToplevel|UART0|TX_BUFFER~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[11]\, myVirtualToplevel|UART0|TX_BUFFER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER~3\, myVirtualToplevel|UART0|TX_BUFFER~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[10]\, myVirtualToplevel|UART0|TX_BUFFER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER~2\, myVirtualToplevel|UART0|TX_BUFFER~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[9]\, myVirtualToplevel|UART0|TX_BUFFER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER~1\, myVirtualToplevel|UART0|TX_BUFFER~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[8]\, myVirtualToplevel|UART0|TX_BUFFER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_STATE~0\, myVirtualToplevel|UART0|TX_STATE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_STATE\, myVirtualToplevel|UART0|TX_STATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal5~3\, myVirtualToplevel|UART0|Equal5~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA_LOADED~0\, myVirtualToplevel|UART0|TX_DATA_LOADED~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA_LOADED\, myVirtualToplevel|UART0|TX_DATA_LOADED, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0\, myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]\, myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add8~13\, myVirtualToplevel|UART0|Add8~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[1]\, myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add8~17\, myVirtualToplevel|UART0|Add8~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[2]\, myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add8~21\, myVirtualToplevel|UART0|Add8~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[3]\, myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add8~25\, myVirtualToplevel|UART0|Add8~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[4]\, myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Add8~29\, myVirtualToplevel|UART0|Add8~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[5]\, myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[6]\, myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~9\, myVirtualToplevel|IO_DATA_READ~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1266\, myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1266, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~10\, myVirtualToplevel|IO_DATA_READ~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1268\, myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1268, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~11\, myVirtualToplevel|IO_DATA_READ~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector9~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector9~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[6]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[22]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][22]~feeder\, myVirtualToplevel|SD_ADDR[0][22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][22]\, myVirtualToplevel|SD_ADDR[0][22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[22]\, myVirtualToplevel|IO_DATA_READ_SD[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[22]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[22]~11\, myVirtualToplevel|MEM_DATA_READ[22]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[22]~13\, myVirtualToplevel|MEM_DATA_READ[22]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector12~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector12~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector270~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector270~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_NEW_REG915\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[22]_NEW_REG915, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~16\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][22]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][22]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~29\, myVirtualToplevel|\TIMER:TIMER1|Add1~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~8\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][23]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][23]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~57\, myVirtualToplevel|\TIMER:TIMER1|Add1~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~15\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][24]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][24]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~53\, myVirtualToplevel|\TIMER:TIMER1|Add1~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~14\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][25]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][25]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~49\, myVirtualToplevel|\TIMER:TIMER1|Add1~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~13\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][26]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][26]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~37\, myVirtualToplevel|\TIMER:TIMER1|Add1~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~10\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][27]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][27]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~17\, myVirtualToplevel|\TIMER:TIMER1|Add1~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~5\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][28]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][28]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~21\, myVirtualToplevel|\TIMER:TIMER1|Add1~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~6\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][29]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][29]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~1\, myVirtualToplevel|\TIMER:TIMER1|Add1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~1\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][30]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][30]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Add1~5\, myVirtualToplevel|\TIMER:TIMER1|Add1~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~2\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][31]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]\, myVirtualToplevel|\TIMER:TIMER1|timer_limit[0][31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal1~0\, myVirtualToplevel|\TIMER:TIMER1|Equal1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal1~1\, myVirtualToplevel|\TIMER:TIMER1|Equal1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal1~2\, myVirtualToplevel|\TIMER:TIMER1|Equal1~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal1~3\, myVirtualToplevel|\TIMER:TIMER1|Equal1~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal1~4\, myVirtualToplevel|\TIMER:TIMER1|Equal1~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal1~5\, myVirtualToplevel|\TIMER:TIMER1|Equal1~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~DUPLICATE\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][19]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal1~6\, myVirtualToplevel|\TIMER:TIMER1|Equal1~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]\, myVirtualToplevel|\TIMER:TIMER1|timer_counter[0][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal1~7\, myVirtualToplevel|\TIMER:TIMER1|Equal1~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|Equal1~8\, myVirtualToplevel|\TIMER:TIMER1|Equal1~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|ticks~0\, myVirtualToplevel|\TIMER:TIMER1|ticks~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|ticks[0]\, myVirtualToplevel|\TIMER:TIMER1|ticks[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[4]\, myVirtualToplevel|INT_ENABLE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal138~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal138~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal138~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal138~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal138~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal138~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal138~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal138~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal138~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal138~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|interruptSuspendedAddr[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal138~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal138~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal138~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~0\, myVirtualToplevel|\ZPUEVO:ZPU0|inInterrupt~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt\, myVirtualToplevel|\ZPUEVO:ZPU0|inInterrupt, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~24\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|INT_DONE\, myVirtualToplevel|\ZPUEVO:ZPU0|INT_DONE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[11]\, myVirtualToplevel|INT_ENABLE[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[8]\, myVirtualToplevel|INT_ENABLE[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_INTR~0\, myVirtualToplevel|UART1|TX_INTR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_INTR\, myVirtualToplevel|UART1|TX_INTR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_INTR~0\, myVirtualToplevel|UART0|TX_INTR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_INTR\, myVirtualToplevel|UART0|TX_INTR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[9]\, myVirtualToplevel|INT_ENABLE[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[10]\, myVirtualToplevel|INT_ENABLE[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~6\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[4]~DUPLICATE\, myVirtualToplevel|INT_ENABLE[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~5\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~7\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending[17]\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~0\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|int~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|int\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|int, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~0\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending[4]\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[4]\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|status[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL~1\, myVirtualToplevel|IO_DATA_READ_INTRCTL~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[4]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[4]~90\, myVirtualToplevel|MEM_DATA_READ[4]~90, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[4]~input\, SDRAM_DQ[4]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_NEW_REG60\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_NEW_REG60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_NEW_REG58\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_NEW_REG58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[4]~131\, myVirtualToplevel|MEM_DATA_READ[4]~131, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add34~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add34~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[21]_NEW_REG1214\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[21]_NEW_REG1214, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~1\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1326~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1326~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1326~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_RESYN8961\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector984~4_RESYN8961, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector984~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector984~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector984~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_RESYN8629\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector984~8_RESYN8629, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector984~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1326~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector984~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector984~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector984~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~7\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~9\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~8\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~9\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector984~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1326~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1326~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[21]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[21]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[21]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[21]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[21]_NEW3153\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[21]_NEW3153, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[21]_NEW3089\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[21]_NEW3089, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[21]_NEW3025\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[21]_NEW3025, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[21]_NEW2961\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[21]_NEW2961, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux21~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[21]_NEW2705\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[21]_NEW2705, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[21]_NEW2897\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[21]_NEW2897, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[21]_NEW2833\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[21]_NEW2833, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[21]_NEW2769\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[21]_NEW2769, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux21~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux21~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector13~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector13~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector271~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector271~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_NEW_REG919\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[21]_NEW_REG919, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~2\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~_wirecell\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[5]\, myVirtualToplevel|UART1|TX_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~17\, myVirtualToplevel|UART1|Add0~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[6]\, myVirtualToplevel|UART1|TX_COUNTER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~21\, myVirtualToplevel|UART1|Add0~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[7]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[7]\, myVirtualToplevel|UART1|TX_COUNTER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~57\, myVirtualToplevel|UART1|Add0~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[8]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[8]\, myVirtualToplevel|UART1|TX_COUNTER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~25\, myVirtualToplevel|UART1|Add0~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[9]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[9]\, myVirtualToplevel|UART1|TX_COUNTER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal0~1\, myVirtualToplevel|UART1|Equal0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~13\, myVirtualToplevel|UART1|Add0~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~1\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~_wirecell\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~_wirecell, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[10]\, myVirtualToplevel|UART1|TX_COUNTER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~9\, myVirtualToplevel|UART1|Add0~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[11]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[11]\, myVirtualToplevel|UART1|TX_COUNTER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~5\, myVirtualToplevel|UART1|Add0~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[12]~feeder\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[12]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[12]\, myVirtualToplevel|UART1|TX_COUNTER[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~1\, myVirtualToplevel|UART1|Add0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[13]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[13]\, myVirtualToplevel|UART1|TX_COUNTER[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~41\, myVirtualToplevel|UART1|Add0~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[14]~feeder\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[14]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[14]\, myVirtualToplevel|UART1|TX_COUNTER[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add0~45\, myVirtualToplevel|UART1|Add0~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[15]~feeder\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[15]\, myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_COUNTER[15]\, myVirtualToplevel|UART1|TX_COUNTER[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal0~2\, myVirtualToplevel|UART1|Equal0~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal0~0\, myVirtualToplevel|UART1|Equal0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal0~3\, myVirtualToplevel|UART1|Equal0~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal0~4\, myVirtualToplevel|UART1|Equal0~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK~0\, myVirtualToplevel|UART1|TX_CLOCK~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_CLOCK\, myVirtualToplevel|UART1|TX_CLOCK, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER[8]~1\, myVirtualToplevel|UART1|TX_BUFFER[8]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER[16]\, myVirtualToplevel|UART1|TX_BUFFER[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER~8\, myVirtualToplevel|UART1|TX_BUFFER~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER[15]\, myVirtualToplevel|UART1|TX_BUFFER[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER~7\, myVirtualToplevel|UART1|TX_BUFFER~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER[14]\, myVirtualToplevel|UART1|TX_BUFFER[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER~6\, myVirtualToplevel|UART1|TX_BUFFER~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER[13]\, myVirtualToplevel|UART1|TX_BUFFER[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER~5\, myVirtualToplevel|UART1|TX_BUFFER~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER[12]\, myVirtualToplevel|UART1|TX_BUFFER[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER~4\, myVirtualToplevel|UART1|TX_BUFFER~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER[11]\, myVirtualToplevel|UART1|TX_BUFFER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER~3\, myVirtualToplevel|UART1|TX_BUFFER~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER[10]\, myVirtualToplevel|UART1|TX_BUFFER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER~2\, myVirtualToplevel|UART1|TX_BUFFER~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER[9]\, myVirtualToplevel|UART1|TX_BUFFER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER~0\, myVirtualToplevel|UART1|TX_BUFFER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUFFER[8]\, myVirtualToplevel|UART1|TX_BUFFER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_STATE~0\, myVirtualToplevel|UART1|TX_STATE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_STATE\, myVirtualToplevel|UART1|TX_STATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_DATA_LOADED~0\, myVirtualToplevel|UART1|TX_DATA_LOADED~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_DATA_LOADED\, myVirtualToplevel|UART1|TX_DATA_LOADED, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[6]\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[6]~DUPLICATE\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5]~DUPLICATE\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3]~DUPLICATE\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2]~DUPLICATE\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1]~DUPLICATE\, myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add6~9\, myVirtualToplevel|UART1|Add6~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add6~13\, myVirtualToplevel|UART1|Add6~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add6~5\, myVirtualToplevel|UART1|Add6~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add6~17\, myVirtualToplevel|UART1|Add6~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add6~21\, myVirtualToplevel|UART1|Add6~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add6~25\, myVirtualToplevel|UART1|Add6~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add6~29\, myVirtualToplevel|UART1|Add6~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal6~3\, myVirtualToplevel|UART1|Equal6~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add6~1\, myVirtualToplevel|UART1|Add6~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal6~0\, myVirtualToplevel|UART1|Equal6~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal6~1\, myVirtualToplevel|UART1|Equal6~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal6~2\, myVirtualToplevel|UART1|Equal6~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Equal6~4\, myVirtualToplevel|UART1|Equal6~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~18\, myVirtualToplevel|IO_DATA_READ~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1083\, myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1083, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[17]~3\, myVirtualToplevel|IO_DATA_READ[17]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1081\, myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1081, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1077\, myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1077, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1075\, myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1075, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~19\, myVirtualToplevel|IO_DATA_READ~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]_NEW_REG66\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]_NEW_REG66, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[17]~24\, myVirtualToplevel|MEM_DATA_READ[17]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG592\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG592, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG600\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG600, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[17]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[1]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[1]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~382\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][6]~382, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux149~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector988~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector988~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector988~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector988~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector988~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector988~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector988~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~3\, myVirtualToplevel|\ZPUEVO:ZPU0|RESULT~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector988~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector988~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~31\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~22\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector988~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~20\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~8\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight0~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~21\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector988~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector988~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[17]_NEW_REG1236\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[17]_NEW_REG1236, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~5\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1330~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1330~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1330~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1330~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[17]_NEW3161\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[17]_NEW3161, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[17]_NEW3097\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[17]_NEW3097, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[17]_NEW3033\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[17]_NEW3033, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[17]_NEW2969\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[17]_NEW2969, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux25~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[17]_NEW2713\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[17]_NEW2713, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[17]_NEW2777\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[17]_NEW2777, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[17]_NEW2905\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[17]_NEW2905, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[17]_NEW2841\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[17]_NEW2841, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux25~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux25~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector17~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector17~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector275~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector275~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_NEW_REG1616\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[17]_NEW_REG1616, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal31~3\, myVirtualToplevel|Equal31~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal31~4\, myVirtualToplevel|Equal31~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal31~0\, myVirtualToplevel|Equal31~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal31~1\, myVirtualToplevel|Equal31~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal31~2\, myVirtualToplevel|Equal31~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal31~5\, myVirtualToplevel|Equal31~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add12~13\, myVirtualToplevel|Add12~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_TICK[0]\, myVirtualToplevel|MICROSEC_DOWN_TICK[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add12~9\, myVirtualToplevel|Add12~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_TICK[1]\, myVirtualToplevel|MICROSEC_DOWN_TICK[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add12~29\, myVirtualToplevel|Add12~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_TICK[2]\, myVirtualToplevel|MICROSEC_DOWN_TICK[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add12~25\, myVirtualToplevel|Add12~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_TICK[3]\, myVirtualToplevel|MICROSEC_DOWN_TICK[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add12~21\, myVirtualToplevel|Add12~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_TICK[4]\, myVirtualToplevel|MICROSEC_DOWN_TICK[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add12~5\, myVirtualToplevel|Add12~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_TICK[5]\, myVirtualToplevel|MICROSEC_DOWN_TICK[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add12~1\, myVirtualToplevel|Add12~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_TICK[6]\, myVirtualToplevel|MICROSEC_DOWN_TICK[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add12~17\, myVirtualToplevel|Add12~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_TICK[7]\, myVirtualToplevel|MICROSEC_DOWN_TICK[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal30~0\, myVirtualToplevel|Equal30~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Equal30~1\, myVirtualToplevel|Equal30~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0\, myVirtualToplevel|MICROSEC_DOWN_COUNTER~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~51\, myVirtualToplevel|IO_DATA_READ~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~52\, myVirtualToplevel|IO_DATA_READ~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[5]\, myVirtualToplevel|RTC_YEAR_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add11~5\, myVirtualToplevel|Add11~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[5]_NEW1770\, myVirtualToplevel|RTC_YEAR_COUNTER[5]_NEW1770, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[5]~DUPLICATE\, myVirtualToplevel|RTC_YEAR_COUNTER[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add11~21\, myVirtualToplevel|Add11~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[6]_NEW1762\, myVirtualToplevel|RTC_YEAR_COUNTER[6]_NEW1762, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[6]\, myVirtualToplevel|RTC_YEAR_COUNTER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~53\, myVirtualToplevel|IO_DATA_READ~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~54\, myVirtualToplevel|IO_DATA_READ~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~26\, myVirtualToplevel|UART1|Add9~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~25\, myVirtualToplevel|UART1|Add9~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~5\, myVirtualToplevel|UART1|Add9~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~9\, myVirtualToplevel|UART1|Add9~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~55\, myVirtualToplevel|IO_DATA_READ~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[6]\, myVirtualToplevel|IO_DATA_READ[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[6]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[6]~86_RESYN8735\, myVirtualToplevel|MEM_DATA_READ[6]~86_RESYN8735, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[6]~86\, myVirtualToplevel|MEM_DATA_READ[6]~86, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[6]~111\, myVirtualToplevel|MEM_DATA_READ[6]~111, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[6]_NEW2991\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[6]_NEW2991, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[6]_NEW3055\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[6]_NEW3055, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[6]_NEW3183\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[6]_NEW3183, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[6]_NEW3119\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[6]_NEW3119, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux81~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[6]_NEW2927\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[6]_NEW2927, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[6]_NEW2863\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[6]_NEW2863, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[6]_NEW2735\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[6]_NEW2735, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[6]_NEW2799\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[6]_NEW2799, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux81~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux81~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]\, myVirtualToplevel|RTC_MICROSEC_COUNTER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add4~17\, myVirtualToplevel|Add4~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[7]\, myVirtualToplevel|RTC_MICROSEC_COUNTER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add4~21\, myVirtualToplevel|Add4~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[8]\, myVirtualToplevel|RTC_MICROSEC_COUNTER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[5]~DUPLICATE\, myVirtualToplevel|RTC_MICROSEC_COUNTER[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~0\, myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add4~9\, myVirtualToplevel|Add4~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[9]\, myVirtualToplevel|RTC_MICROSEC_COUNTER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[0]~DUPLICATE\, myVirtualToplevel|RTC_MICROSEC_COUNTER[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2\, myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[0]\, myVirtualToplevel|RTC_MICROSEC_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add4~37\, myVirtualToplevel|Add4~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[1]\, myVirtualToplevel|RTC_MICROSEC_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add4~29\, myVirtualToplevel|Add4~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[2]\, myVirtualToplevel|RTC_MICROSEC_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add4~25\, myVirtualToplevel|Add4~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[3]\, myVirtualToplevel|RTC_MICROSEC_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add4~1\, myVirtualToplevel|Add4~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[4]\, myVirtualToplevel|RTC_MICROSEC_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_MICROSEC_COUNTER[5]\, myVirtualToplevel|RTC_MICROSEC_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_SECOND_COUNTER[5]~DUPLICATE\, myVirtualToplevel|RTC_SECOND_COUNTER[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux267~1\, myVirtualToplevel|Mux267~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux267~0\, myVirtualToplevel|Mux267~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[5]~38\, myVirtualToplevel|IO_DATA_READ[5]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~23\, myVirtualToplevel|UART1|RX_FIFO~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[22]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA~6\, myVirtualToplevel|UART1|RX_DATA~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[5]~7\, myVirtualToplevel|UART1|RX_DATA[5]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[5]\, myVirtualToplevel|UART1|RX_DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[22]~feeder\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[22]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~23\, myVirtualToplevel|UART0|RX_FIFO~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA~6\, myVirtualToplevel|UART0|RX_DATA~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[5]~7\, myVirtualToplevel|UART0|RX_DATA[5]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[5]\, myVirtualToplevel|UART0|RX_DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_ENABLE_FIFO\, myVirtualToplevel|UART0|RX_ENABLE_FIFO, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~37\, myVirtualToplevel|IO_DATA_READ~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[5]~39\, myVirtualToplevel|IO_DATA_READ[5]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[5]\, myVirtualToplevel|IO_DATA_READ[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[5]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[5]~88_RESYN8737\, myVirtualToplevel|MEM_DATA_READ[5]~88_RESYN8737, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[5]~88\, myVirtualToplevel|MEM_DATA_READ[5]~88, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[5]~127\, myVirtualToplevel|MEM_DATA_READ[5]~127, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[5]_NEW2929\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[5]_NEW2929, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[5]_NEW2865\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[5]_NEW2865, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[5]_NEW2737\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[5]_NEW2737, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[5]_NEW2801\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[5]_NEW2801, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux82~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[5]_NEW2993\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[5]_NEW2993, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[5]_NEW3185\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[5]_NEW3185, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[5]_NEW3057\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[5]_NEW3057, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[5]_NEW3121\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[5]_NEW3121, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux82~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux82~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[5]~1\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[5]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[13]\, myVirtualToplevel|INT_ENABLE[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[13]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~28\, myVirtualToplevel|IO_DATA_READ~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~29\, myVirtualToplevel|IO_DATA_READ~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~30\, myVirtualToplevel|IO_DATA_READ~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[13]\, myVirtualToplevel|IO_DATA_READ[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux90~0\, myVirtualToplevel|Mux90~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[13]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[13]~72_RESYN8721\, myVirtualToplevel|MEM_DATA_READ[13]~72_RESYN8721, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[13]~72\, myVirtualToplevel|MEM_DATA_READ[13]~72, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]_NEW_REG98\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]_NEW_REG98, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]~13\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~0\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node[0]\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[13]~143\, myVirtualToplevel|MEM_DATA_READ[13]~143, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector345~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector345~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~27\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[13]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~28\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[13]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~32\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[13]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~33\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[13]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~30\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[13]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~31\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[13]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~31\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[13]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~32\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[13]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux36~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~28\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[13]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~29\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[13]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~30\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[13]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~31\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[13]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~31\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[13]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~32\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[13]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~34\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[13]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~35\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[13]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux36~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux36~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector202~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector202~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[3]\, myVirtualToplevel|INT_ENABLE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[3]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux91~0\, myVirtualToplevel|Mux91~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[3]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~65\, myVirtualToplevel|IO_DATA_READ~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[3]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_COUNTER[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[3]\, myVirtualToplevel|SECOND_DOWN_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~66\, myVirtualToplevel|IO_DATA_READ~66, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~67\, myVirtualToplevel|IO_DATA_READ~67, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~68\, myVirtualToplevel|IO_DATA_READ~68, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[20]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~21\, myVirtualToplevel|UART1|RX_FIFO~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA~12\, myVirtualToplevel|UART1|RX_DATA~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[3]~13\, myVirtualToplevel|UART1|RX_DATA[3]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[3]\, myVirtualToplevel|UART1|RX_DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_OVERRUN~0\, myVirtualToplevel|UART1|RX_OVERRUN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_OVERRUN\, myVirtualToplevel|UART1|RX_OVERRUN, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_OVERRUN~0\, myVirtualToplevel|UART0|RX_OVERRUN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_OVERRUN\, myVirtualToplevel|UART0|RX_OVERRUN, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~69\, myVirtualToplevel|IO_DATA_READ~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[20]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~21\, myVirtualToplevel|UART0|RX_FIFO~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA~12\, myVirtualToplevel|UART0|RX_DATA~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[3]~13\, myVirtualToplevel|UART0|RX_DATA[3]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[3]\, myVirtualToplevel|UART0|RX_DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~71\, myVirtualToplevel|IO_DATA_READ~71, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[3]\, myVirtualToplevel|IO_DATA_READ[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[3]~92_RESYN8741\, myVirtualToplevel|MEM_DATA_READ[3]~92_RESYN8741, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[3]~92\, myVirtualToplevel|MEM_DATA_READ[3]~92, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[3]~99\, myVirtualToplevel|MEM_DATA_READ[3]~99, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[3]_NEW3189\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[3]_NEW3189, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[3]_NEW3061\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[3]_NEW3061, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[3]_NEW3125\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[3]_NEW3125, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[3]_NEW2997\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[3]_NEW2997, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux84~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[3]_NEW2741\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[3]_NEW2741, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[3]_NEW2933\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[3]_NEW2933, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[3]_NEW2805\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[3]_NEW2805, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[3]_NEW2869\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[3]_NEW2869, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux84~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux84~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[3]~6\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[3]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[11]~DUPLICATE\, myVirtualToplevel|INT_ENABLE[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~3\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending[11]\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[11]\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|status[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL~4\, myVirtualToplevel|IO_DATA_READ_INTRCTL~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[11]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[11]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~43\, myVirtualToplevel|IO_DATA_READ~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[11]~42\, myVirtualToplevel|IO_DATA_READ[11]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[11]\, myVirtualToplevel|RTC_YEAR_COUNTER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[8]\, myVirtualToplevel|RTC_YEAR_COUNTER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add11~25\, myVirtualToplevel|Add11~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[7]_NEW1760\, myVirtualToplevel|RTC_YEAR_COUNTER[7]_NEW1760, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[7]\, myVirtualToplevel|RTC_YEAR_COUNTER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add11~29\, myVirtualToplevel|Add11~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[8]_NEW1758\, myVirtualToplevel|RTC_YEAR_COUNTER[8]_NEW1758, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[8]~DUPLICATE\, myVirtualToplevel|RTC_YEAR_COUNTER[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add11~9\, myVirtualToplevel|Add11~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[9]_NEW1768\, myVirtualToplevel|RTC_YEAR_COUNTER[9]_NEW1768, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[9]\, myVirtualToplevel|RTC_YEAR_COUNTER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add11~13\, myVirtualToplevel|Add11~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[10]\, myVirtualToplevel|RTC_YEAR_COUNTER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[10]_NEW1766\, myVirtualToplevel|RTC_YEAR_COUNTER[10]_NEW1766, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[10]~DUPLICATE\, myVirtualToplevel|RTC_YEAR_COUNTER[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Add11~17\, myVirtualToplevel|Add11~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[11]_NEW1764\, myVirtualToplevel|RTC_YEAR_COUNTER[11]_NEW1764, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|RTC_YEAR_COUNTER[11]~DUPLICATE\, myVirtualToplevel|RTC_YEAR_COUNTER[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[11]\, myVirtualToplevel|SECOND_DOWN_COUNTER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~104\, myVirtualToplevel|IO_DATA_READ~104, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~45\, myVirtualToplevel|IO_DATA_READ~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[11]\, myVirtualToplevel|IO_DATA_READ[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[11]~76_RESYN8725\, myVirtualToplevel|MEM_DATA_READ[11]~76_RESYN8725, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[11]~76\, myVirtualToplevel|MEM_DATA_READ[11]~76, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[11]~input\, SDRAM_DQ[11]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_NEW_REG20\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_NEW_REG20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]_NEW_REG48\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]_NEW_REG48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]~20\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[11]~115\, myVirtualToplevel|MEM_DATA_READ[11]~115, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~37\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[11]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_NEW_REG528\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[11]_NEW_REG528, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_NEW_REG524\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[11]_NEW_REG524, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~36\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[11]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_NEW_REG526\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[11]_NEW_REG526, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~309\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][0]~309, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~20_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~42\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[11]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~43\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[11]~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~44\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~45\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11]~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~45\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[11]~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~46\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[11]~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~48\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[11]~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~49\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[11]~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux38~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~45\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[11]~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~46\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[11]~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~41\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[11]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~42\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[11]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~44\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[11]~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~45\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[11]~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~46\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[11]~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~47\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[11]~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux38~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux38~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector205~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector205~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SOCCFG_CS_RESYN8753\, myVirtualToplevel|SOCCFG_CS_RESYN8753, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SOCCFG_CS\, myVirtualToplevel|SOCCFG_CS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[18]~7\, myVirtualToplevel|MEM_DATA_READ[18]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[21]\, myVirtualToplevel|MILLISEC_UP_COUNTER[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~7\, myVirtualToplevel|IO_DATA_READ~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~6\, myVirtualToplevel|IO_DATA_READ~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~8\, myVirtualToplevel|IO_DATA_READ~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[21]\, myVirtualToplevel|IO_DATA_READ[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[21]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector10~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector10~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[5]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[21]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][21]~feeder\, myVirtualToplevel|SD_ADDR[0][21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][21]\, myVirtualToplevel|SD_ADDR[0][21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[21]\, myVirtualToplevel|IO_DATA_READ_SD[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[21]~8\, myVirtualToplevel|MEM_DATA_READ[21]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[5]~1\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[5]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[21]~9\, myVirtualToplevel|MEM_DATA_READ[21]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[21]~10\, myVirtualToplevel|MEM_DATA_READ[21]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1062~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[21]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[21]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[21]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[21]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[21]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[21]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[21]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[21]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux28~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[21]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[21]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[21]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[21]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[21]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[21]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[21]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[21]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux28~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux28~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1063~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[20]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[20]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[20]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[20]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[20]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[20]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[20]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[20]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux29~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[20]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[20]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[20]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[20]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[20]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[20]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[20]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[20]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux29~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux29~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1064~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~27\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[19]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~28\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[19]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[19]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~24\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[19]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[19]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~27\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[19]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~28\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[19]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~29\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[19]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux30~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~24\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[19]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~25\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[19]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~30\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[19]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~31\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[19]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[19]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~27\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[19]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~27\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[19]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~28\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[19]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux30~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux30~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector195~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector195~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[21]_NEW3346\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[21]_NEW3346, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector196~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector196~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[20]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[20]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_SELECT~0\, myVirtualToplevel|IO_SELECT~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0_CS\, myVirtualToplevel|UART0_CS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_ENABLE~0\, myVirtualToplevel|UART0|TX_ENABLE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE\, myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[7]~0\, myVirtualToplevel|UART0|RX_DATA[7]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~19\, myVirtualToplevel|UART0|RX_FIFO~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[18]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA~18\, myVirtualToplevel|UART0|RX_DATA~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[1]~19\, myVirtualToplevel|UART0|RX_DATA[1]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[1]\, myVirtualToplevel|UART0|RX_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FULL_V~0\, myVirtualToplevel|UART0|RX_FULL_V~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FULL_V\, myVirtualToplevel|UART0|RX_FULL_V, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FULL_V~0\, myVirtualToplevel|UART1|RX_FULL_V~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FULL_V\, myVirtualToplevel|UART1|RX_FULL_V, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~19\, myVirtualToplevel|UART1|RX_FIFO~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[18]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA~18\, myVirtualToplevel|UART1|RX_DATA~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[1]~19\, myVirtualToplevel|UART1|RX_DATA[1]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[1]\, myVirtualToplevel|UART1|RX_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~98\, myVirtualToplevel|IO_DATA_READ~98, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[1]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_COUNTER[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[1]\, myVirtualToplevel|SECOND_DOWN_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~95\, myVirtualToplevel|IO_DATA_READ~95, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~94\, myVirtualToplevel|IO_DATA_READ~94, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~96\, myVirtualToplevel|IO_DATA_READ~96, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~97\, myVirtualToplevel|IO_DATA_READ~97, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~99\, myVirtualToplevel|IO_DATA_READ~99, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[1]\, myVirtualToplevel|IO_DATA_READ[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[1]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|data_o[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[1]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|data_o[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][1]\, myVirtualToplevel|SD_ADDR[0][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux82~0\, myVirtualToplevel|Mux82~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[1]\, myVirtualToplevel|IO_DATA_READ_SD[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[1]\, myVirtualToplevel|INT_ENABLE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[1]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[1]~63\, myVirtualToplevel|MEM_DATA_READ[1]~63, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[1]~65\, myVirtualToplevel|MEM_DATA_READ[1]~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_NEW_REG1208\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[0]_NEW_REG1208, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[8]_NEW_REG1220\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[8]_NEW_REG1220, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~19\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1339~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1339~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1339~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~41\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~73\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~41\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~74\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~74, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux170~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux170~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux170~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux170~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux170~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux170~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux170~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux170~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux170~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux170~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux170~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector997~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1339~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[8]_NEW3003\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[8]_NEW3003, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[8]_NEW3131\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[8]_NEW3131, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[8]_NEW3195\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[8]_NEW3195, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[8]_NEW3067\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[8]_NEW3067, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux97~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[8]_NEW2939\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[8]_NEW2939, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[8]_NEW2811\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[8]_NEW2811, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[8]_NEW2747\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[8]_NEW2747, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[8]_NEW2875\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[8]_NEW2875, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux97~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux97~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][8]\, myVirtualToplevel|SD_ADDR[0][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux75~1\, myVirtualToplevel|Mux75~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[8]\, myVirtualToplevel|IO_DATA_READ_SD[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[0]~7\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[0]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~4\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending[8]\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[8]\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|status[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL~5\, myVirtualToplevel|IO_DATA_READ_INTRCTL~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[8]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[8]~64\, myVirtualToplevel|IO_DATA_READ[8]~64, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[8]\, myVirtualToplevel|MILLISEC_UP_COUNTER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux264~0\, myVirtualToplevel|Mux264~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[8]~100\, myVirtualToplevel|IO_DATA_READ[8]~100, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[8]\, myVirtualToplevel|IO_DATA_READ[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux94~0\, myVirtualToplevel|Mux94~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[8]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[8]~82_RESYN8731\, myVirtualToplevel|MEM_DATA_READ[8]~82_RESYN8731, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[8]~82\, myVirtualToplevel|MEM_DATA_READ[8]~82, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]_NEW_REG38\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]_NEW_REG38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]~23\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[8]~103\, myVirtualToplevel|MEM_DATA_READ[8]~103, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~31\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[8]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_NEW_REG546\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[8]_NEW_REG546, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~30\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[8]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_NEW_REG544\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[8]_NEW_REG544, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_NEW_REG542\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[8]_NEW_REG542, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~186\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][4]~186, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~190\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][4]~190, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~206\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][4]~206, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~202\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][4]~202, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux153~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~207\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][4]~207, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~203\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][4]~203, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~191\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][4]~191, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~187\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][4]~187, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux153~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~195\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][4]~195, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~199\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][4]~199, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~211\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][4]~211, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~215\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][4]~215, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux153~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~214\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][4]~214, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~210\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][4]~210, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~198\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][4]~198, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~194\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][4]~194, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux153~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux153~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]_NEW1834\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][4]_NEW1834, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]_NEW1836\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][4]_NEW1836, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~193\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][4]~193, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~192\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][4]~192, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux153~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~213\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][4]~213, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~205\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][4]~205, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~204\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][4]~204, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~212\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][4]~212, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux153~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~201\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][4]~201, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~200\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][4]~200, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~209\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][4]~209, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux153~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~188\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][4]~188, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~189\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][4]~189, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~197\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][4]~197, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~196\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][4]~196, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux153~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux153~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux153~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux160~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux160~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux160~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux160~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux160~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8703\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~11_RESYN8703, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~32\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8699\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~11_RESYN8699, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8701\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~11_RESYN8701, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4\, myVirtualToplevel|\ZPUEVO:ZPU0|RESULT~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector987~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[18]_NEW_REG1234\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[18]_NEW_REG1234, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~6\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1329~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1329~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1329~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1329~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN9301\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1328~4_RESYN9301, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~33\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~27\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~26\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~28\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12798\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1328~4_RESYN12798, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12800\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1328~4_RESYN12800, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1328~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_RESYN9249\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector986~1_RESYN9249, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector986~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector986~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~29\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector986~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector986~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector986~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1328~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[19]_NEW_REG1232\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[19]_NEW_REG1232, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~7\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1328~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1328~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1328~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1328~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~27\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~28\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[19]~29\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[19]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~15\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~16\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[20]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~9\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~10\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_NEW_REG1400\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[21]_NEW_REG1400, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_NEW_REG1398\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[21]_NEW_REG1398, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[21]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~12\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~13\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_NEW_REG1178\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[22]_NEW_REG1178, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[22]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1061~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[22]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[22]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[22]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[22]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux27~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[22]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[22]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[22]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[22]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[22]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[22]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[22]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[22]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux27~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux27~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector194~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector194~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|BRAM_WREN~1\, myVirtualToplevel|BRAM_WREN~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[6]~2\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[6]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][14]\, myVirtualToplevel|SD_ADDR[0][14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux69~0\, myVirtualToplevel|Mux69~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[14]\, myVirtualToplevel|IO_DATA_READ_SD[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[14]\, myVirtualToplevel|INT_ENABLE[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[14]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~112\, myVirtualToplevel|IO_DATA_READ~112, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[14]\, myVirtualToplevel|IO_DATA_READ[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[14]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[14]~70_RESYN8719\, myVirtualToplevel|MEM_DATA_READ[14]~70_RESYN8719, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[14]~70\, myVirtualToplevel|MEM_DATA_READ[14]~70, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[14]~input\, SDRAM_DQ[14]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_NEW_REG84\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_NEW_REG84, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]_NEW_REG96\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]_NEW_REG96, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]~14\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[14]~139\, myVirtualToplevel|MEM_DATA_READ[14]~139, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector352~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector352~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~50\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[6]~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add19~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add19~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1077~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~51\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[6]~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~44\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[6]~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~45\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[6]~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~46\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[6]~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~47\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[6]~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~47\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[6]~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~48\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[6]~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux43~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~47\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[6]~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~48\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[6]~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~48\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[6]~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~49\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[6]~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~43\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[6]~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~44\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[6]~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~46\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[6]~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~47\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[6]~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux43~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux43~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector210~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector210~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER0_CS~0\, myVirtualToplevel|TIMER0_CS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER0_CS~1\, myVirtualToplevel|TIMER0_CS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[26]\, myVirtualToplevel|MILLISEC_UP_COUNTER[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[26]~84\, myVirtualToplevel|IO_DATA_READ[26]~84, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[26]\, myVirtualToplevel|IO_DATA_READ[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector5~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector5~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[10]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[26]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][26]~feeder\, myVirtualToplevel|SD_ADDR[0][26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][26]\, myVirtualToplevel|SD_ADDR[0][26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[26]\, myVirtualToplevel|IO_DATA_READ_SD[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[26]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[26]~54\, myVirtualToplevel|MEM_DATA_READ[26]~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[2]~5\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[2]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[26]~55\, myVirtualToplevel|MEM_DATA_READ[26]~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[26]~56\, myVirtualToplevel|MEM_DATA_READ[26]~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector356~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector356~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[2]_NEW2871\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[2]_NEW2871, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[2]_NEW2935\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[2]_NEW2935, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[2]_NEW2743\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[2]_NEW2743, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[2]_NEW2807\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[2]_NEW2807, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux85~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[2]_NEW3127\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[2]_NEW3127, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[2]_NEW3191\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[2]_NEW3191, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[2]_NEW2999\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[2]_NEW2999, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[2]_NEW3063\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[2]_NEW3063, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux85~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux85~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector16~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector16~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector274~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector274~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_NEW_REG923\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[18]_NEW_REG923, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][18]\, myVirtualToplevel|SD_ADDR[0][18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[18]\, myVirtualToplevel|IO_DATA_READ_SD[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[18]\, myVirtualToplevel|MILLISEC_UP_COUNTER[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~21\, myVirtualToplevel|IO_DATA_READ~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUSY~0\, myVirtualToplevel|UART1|TX_BUSY~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_BUSY\, myVirtualToplevel|UART1|TX_BUSY, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUSY~0\, myVirtualToplevel|UART0|TX_BUSY~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUSY\, myVirtualToplevel|UART0|TX_BUSY, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~20\, myVirtualToplevel|IO_DATA_READ~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~22\, myVirtualToplevel|IO_DATA_READ~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[18]\, myVirtualToplevel|IO_DATA_READ[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[18]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[18]~28\, myVirtualToplevel|MEM_DATA_READ[18]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[2]~6\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[2]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[18]~29\, myVirtualToplevel|MEM_DATA_READ[18]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[18]~30\, myVirtualToplevel|MEM_DATA_READ[18]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector198~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector198~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[18]_NEW3339\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[18]_NEW3339, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_SELECT~1\, myVirtualToplevel|IO_SELECT~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTR0_CS_RESYN8755\, myVirtualToplevel|INTR0_CS_RESYN8755, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTR0_CS\, myVirtualToplevel|INTR0_CS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[19]\, myVirtualToplevel|MILLISEC_UP_COUNTER[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~24\, myVirtualToplevel|IO_DATA_READ~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~23\, myVirtualToplevel|IO_DATA_READ~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~25\, myVirtualToplevel|IO_DATA_READ~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[19]\, myVirtualToplevel|IO_DATA_READ[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[19]~feeder\, myVirtualToplevel|IO_DATA_READ_SOCCFG[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[19]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector12~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector12~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[3]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[19]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][19]~feeder\, myVirtualToplevel|SD_ADDR[0][19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][19]\, myVirtualToplevel|SD_ADDR[0][19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[19]\, myVirtualToplevel|IO_DATA_READ_SD[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[19]~31\, myVirtualToplevel|MEM_DATA_READ[19]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[3]~7\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[3]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[19]~32\, myVirtualToplevel|MEM_DATA_READ[19]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]_NEW_REG62\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]_NEW_REG62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[19]~33\, myVirtualToplevel|MEM_DATA_READ[19]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[19]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[19]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|BRAM_WREN~0\, myVirtualToplevel|BRAM_WREN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~5\, myVirtualToplevel|MEM_DATA_READ[2]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector2~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector2~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[29]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][29]\, myVirtualToplevel|SD_ADDR[0][29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[29]\, myVirtualToplevel|IO_DATA_READ_SD[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~80\, myVirtualToplevel|IO_DATA_READ~80, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[29]\, myVirtualToplevel|IO_DATA_READ[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[29]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[29]~42\, myVirtualToplevel|MEM_DATA_READ[29]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[5]~1\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[5]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[29]~43\, myVirtualToplevel|MEM_DATA_READ[29]~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[29]~44\, myVirtualToplevel|MEM_DATA_READ[29]~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector353~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector353~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~46\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~47\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[5]~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~57\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~58\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~59\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[6]~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1076~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~49\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[7]~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~50\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[7]~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~48\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[7]~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~49\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[7]~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~45\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[7]~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~46\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[7]~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~50\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[7]~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~51\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[7]~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux42~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~48\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[7]~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~49\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[7]~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~46\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[7]~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~47\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[7]~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~49\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[7]~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~50\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[7]~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~52\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[7]~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~53\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[7]~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux42~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux42~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector209~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector209~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0\, myVirtualToplevel|\TIMER:TIMER1|timer_enabled[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[7]\, myVirtualToplevel|INT_ENABLE[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[7]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO~25\, myVirtualToplevel|UART0|RX_FIFO~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[24]\, myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA~10\, myVirtualToplevel|UART0|RX_DATA~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[7]~11\, myVirtualToplevel|UART0|RX_DATA[7]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|RX_DATA[7]\, myVirtualToplevel|UART0|RX_DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~57\, myVirtualToplevel|IO_DATA_READ~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[24]\, myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_FIFO~25\, myVirtualToplevel|UART1|RX_FIFO~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA~10\, myVirtualToplevel|UART1|RX_DATA~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[7]~11\, myVirtualToplevel|UART1|RX_DATA[7]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|RX_DATA[7]\, myVirtualToplevel|UART1|RX_DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~56\, myVirtualToplevel|IO_DATA_READ~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~58\, myVirtualToplevel|IO_DATA_READ~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[7]~DUPLICATE\, myVirtualToplevel|MILLISEC_UP_COUNTER[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~59\, myVirtualToplevel|IO_DATA_READ~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~60\, myVirtualToplevel|IO_DATA_READ~60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~61\, myVirtualToplevel|IO_DATA_READ~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~62\, myVirtualToplevel|IO_DATA_READ~62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~27\, myVirtualToplevel|UART1|Add9~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|Add9~13\, myVirtualToplevel|UART1|Add9~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~63\, myVirtualToplevel|IO_DATA_READ~63, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[7]\, myVirtualToplevel|IO_DATA_READ[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[7]~feeder\, myVirtualToplevel|IO_DATA_READ_SOCCFG[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[7]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[7]~84_RESYN8733\, myVirtualToplevel|MEM_DATA_READ[7]~84_RESYN8733, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[7]~84\, myVirtualToplevel|MEM_DATA_READ[7]~84, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[7]~107\, myVirtualToplevel|MEM_DATA_READ[7]~107, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[7]_NEW3197\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[7]_NEW3197, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[7]_NEW3133\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[7]_NEW3133, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[7]_NEW3005\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[7]_NEW3005, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[7]_NEW3069\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[7]_NEW3069, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux80~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[7]_NEW2877\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[7]_NEW2877, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[7]_NEW2941\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[7]_NEW2941, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[7]_NEW2749\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[7]_NEW2749, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[7]_NEW2813\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[7]_NEW2813, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux80~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux80~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][7]\, myVirtualToplevel|SD_ADDR[0][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[7]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|data_o[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux76~0\, myVirtualToplevel|Mux76~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[7]\, myVirtualToplevel|IO_DATA_READ_SD[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate\, myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector351~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector351~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~60\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~61\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[7]~62\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[7]~62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~63\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~63, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~64\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~64, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[8]~65\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[8]~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1075~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1075~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~52\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[8]~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_NEW_REG1410\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[8]_NEW_REG1410, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[8]~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_NEW_REG1580\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[8]_NEW_REG1580, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~51\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[8]~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_NEW_REG1582\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[8]_NEW_REG1582, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~52\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[8]~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~47\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[8]~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_NEW_REG1572\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[8]_NEW_REG1572, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_NEW_REG1570\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[8]_NEW_REG1570, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~48\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[8]~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~50\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[8]~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_NEW_REG1598\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[8]_NEW_REG1598, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_NEW_REG1596\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[8]_NEW_REG1596, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~51\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[8]~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux41~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_NEW_REG1270\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[8]_NEW_REG1270, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_NEW_REG1272\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[8]_NEW_REG1272, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~51\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[8]~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_NEW_REG1274\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[8]_NEW_REG1274, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~52\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[8]~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~48\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[8]~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_NEW_REG1496\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[8]_NEW_REG1496, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_NEW_REG1494\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[8]_NEW_REG1494, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~49\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[8]~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_NEW_REG1374\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[8]_NEW_REG1374, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~54\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[8]~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_NEW_REG1376\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[8]_NEW_REG1376, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~55\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[8]~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~50\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[8]~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_NEW_REG1446\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[8]_NEW_REG1446, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_NEW_REG1444\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[8]_NEW_REG1444, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~51\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[8]~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux41~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux41~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector208~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector208~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|LessThan3~0\, myVirtualToplevel|LessThan3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node[1]\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[7]~3\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[7]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[15]\, myVirtualToplevel|INT_ENABLE[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[15]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[15]\, myVirtualToplevel|MILLISEC_UP_COUNTER[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[15]~DUPLICATE\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[15]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~31\, myVirtualToplevel|IO_DATA_READ~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~32\, myVirtualToplevel|IO_DATA_READ~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[15]\, myVirtualToplevel|IO_DATA_READ[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[15]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[15]~68_RESYN8717\, myVirtualToplevel|MEM_DATA_READ[15]~68_RESYN8717, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[15]~68\, myVirtualToplevel|MEM_DATA_READ[15]~68, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]_NEW_REG94\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]_NEW_REG94, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]~15\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[15]~135\, myVirtualToplevel|MEM_DATA_READ[15]~135, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_SELECT~2\, myVirtualToplevel|IO_SELECT~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SOCCFG_CS~0\, myVirtualToplevel|SOCCFG_CS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][0]~0\, myVirtualToplevel|SD_ADDR[0][0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][10]\, myVirtualToplevel|SD_ADDR[0][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux73~0\, myVirtualToplevel|Mux73~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux73~1\, myVirtualToplevel|Mux73~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[10]\, myVirtualToplevel|IO_DATA_READ_SD[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[2]~5\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[2]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~2\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending[10]\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[10]~feeder\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|status[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[10]\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|status[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL~3\, myVirtualToplevel|IO_DATA_READ_INTRCTL~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[10]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux93~0\, myVirtualToplevel|Mux93~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[10]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SECOND_DOWN_COUNTER[10]\, myVirtualToplevel|SECOND_DOWN_COUNTER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~108\, myVirtualToplevel|IO_DATA_READ~108, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~44\, myVirtualToplevel|IO_DATA_READ~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[10]\, myVirtualToplevel|IO_DATA_READ[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[10]~78_RESYN8727\, myVirtualToplevel|MEM_DATA_READ[10]~78_RESYN8727, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[10]~78\, myVirtualToplevel|MEM_DATA_READ[10]~78, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]_NEW_REG50\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]_NEW_REG50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]~19\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[10]~119\, myVirtualToplevel|MEM_DATA_READ[10]~119, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector348~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector348~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~51\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~52\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~53\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[10]~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~54\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~55\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[11]~56\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[11]~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add21~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add21~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~30\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~31\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~32\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[12]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~33\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~34\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~35\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[13]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add20~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~4\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~7\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[16]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1067~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[16]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[16]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[16]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[16]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[16]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[16]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[16]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[16]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux33~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[16]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[16]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[16]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[16]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[16]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[16]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux33~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux33~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12612\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector200~0_RESYN12612, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12614\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector200~0_RESYN12614, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector200~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]_NEW3335\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[16]_NEW3335, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node[1]\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[0]~95\, myVirtualToplevel|MEM_DATA_READ[0]~95, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[32]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[34]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[34]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[35]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[36]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[38]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[38]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[43]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[43]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[45]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[45]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[46]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[46]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[47]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[47]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[50]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[50]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[51]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[51]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[52]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[52]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[53]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[53]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[54]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[54]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[55]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[55]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]_NEW3330\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[42]_NEW3330, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[39]_NEW3325\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[39]_NEW3325, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~54\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~55\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~56\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[31]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~20\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[32]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[33]_NEW1634\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[33]_NEW1634, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[35]_NEW1638\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[35]_NEW1638, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[34]_NEW1636\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[34]_NEW1636, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~16\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[32]_NEW1632\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[32]_NEW1632, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~19\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~21\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~61\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~59\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~58\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~60\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~62\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[56]_NEW1680\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[56]_NEW1680, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[55]_NEW1678\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[55]_NEW1678, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[54]_NEW1676\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[54]_NEW1676, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[53]_NEW1674\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[53]_NEW1674, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~5\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]_NEW1672\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[52]_NEW1672, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[51]_NEW1670\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[51]_NEW1670, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[50]_NEW1668\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[50]_NEW1668, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~6\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~4\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[36]_NEW1640\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[36]_NEW1640, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]_NEW1642\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[37]_NEW1642, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[37]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~12\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[40]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[39]_NEW1646\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[39]_NEW1646, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[38]_NEW1644\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[38]_NEW1644, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~10\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[40]_NEW1648\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[40]_NEW1648, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[42]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[42]_NEW1652\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[42]_NEW1652, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[41]_NEW1650\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[41]_NEW1650, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~11\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~17\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~18\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[46]_NEW1660\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[46]_NEW1660, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[43]_NEW1654\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[43]_NEW1654, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[45]_NEW1658\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[45]_NEW1658, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[44]_NEW1656\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[44]_NEW1656, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~14\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[48]_NEW1664\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[48]_NEW1664, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[49]_NEW1666\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[49]_NEW1666, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[47]_NEW1662\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[47]_NEW1662, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~13\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~15\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~22\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~26\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~23\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~24\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~25\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~27\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~28\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~29\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~30\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~57\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~45\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~46\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~47\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~48\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~52\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~49\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~50\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~51\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~37\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~38\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~39\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~34\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~31\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|dividendCopy[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~32\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~33\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~35\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~43\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~40\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~41\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~42\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~44\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~53\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan28~63, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~27\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9017\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1323~2_RESYN9017, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9019\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1323~2_RESYN9019, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1323~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8665\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector981~6_RESYN8665, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8663\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector981~6_RESYN8663, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector981~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector981~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8659\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector981~2_RESYN8659, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~47\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftLeft0~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8657\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector981~2_RESYN8657, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8661\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector981~2_RESYN8661, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector981~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9021\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1323~3_RESYN9021, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~5_RESYN8715\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1323~5_RESYN8715, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9023\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1323~3_RESYN9023, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1323~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~161\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~161, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12554\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~151_RESYN12554, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9077_RESYN9359\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~151_RESYN9077_RESYN9359, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_RESYN12602\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_RESYN12602, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9357\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9357, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~151_RESYN9075, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12556\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~151_RESYN12556, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~151, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~101_RESYN9015, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~152\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~152, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12542\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12542, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_RESYN13472\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_RESYN13472, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_NEW_REG897\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[25]_NEW_REG897, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~26\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12780\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~108_RESYN12780, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12782\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~108_RESYN12782, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~108, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~109\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[25]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[25]_NEW2763\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[25]_NEW2763, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[25]_NEW2699\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[25]_NEW2699, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[25]_NEW2891\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[25]_NEW2891, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]_NEW2827\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[25]_NEW2827, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux17~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[25]_NEW3147\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[25]_NEW3147, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[25]_NEW3019\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[25]_NEW3019, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[25]_NEW3083\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[25]_NEW3083, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[25]_NEW2955\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[25]_NEW2955, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux17~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux17~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[25]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[25]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][25]~feeder\, myVirtualToplevel|SD_ADDR[0][25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][25]\, myVirtualToplevel|SD_ADDR[0][25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[25]\, myVirtualToplevel|IO_DATA_READ_SD[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[25]~52\, myVirtualToplevel|MEM_DATA_READ[25]~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[1]~4\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[1]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~83\, myVirtualToplevel|IO_DATA_READ~83, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[25]\, myVirtualToplevel|IO_DATA_READ[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_NEW_REG26\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_NEW_REG26, QMV_zpu, 1 +instance = comp, \SDRAM_DQ[9]~input\, SDRAM_DQ[9]~input, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_NEW_REG28\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_NEW_REG28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[25]~51\, myVirtualToplevel|MEM_DATA_READ[25]~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[25]~53\, myVirtualToplevel|MEM_DATA_READ[25]~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector349~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector349~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[9]_NEW3051\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[9]_NEW3051, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[9]_NEW3179\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[9]_NEW3179, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[9]_NEW3115\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[9]_NEW3115, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[9]_NEW2987\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[9]_NEW2987, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux96~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[9]_NEW2731\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[9]_NEW2731, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[9]_NEW2859\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[9]_NEW2859, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[9]_NEW2795\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[9]_NEW2795, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[9]_NEW2923\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[9]_NEW2923, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux96~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux96~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][9]\, myVirtualToplevel|SD_ADDR[0][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux74~1\, myVirtualToplevel|Mux74~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[9]\, myVirtualToplevel|IO_DATA_READ_SD[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[1]~4\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[1]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~1\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending[9]\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|pending[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[9]~feeder\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|status[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[9]\, myVirtualToplevel|\INTRCTL:INTCONTROLLER|status[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL~2\, myVirtualToplevel|IO_DATA_READ_INTRCTL~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[9]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[9]~40\, myVirtualToplevel|IO_DATA_READ[9]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux263~0\, myVirtualToplevel|Mux263~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[9]~41\, myVirtualToplevel|IO_DATA_READ[9]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[9]\, myVirtualToplevel|IO_DATA_READ[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[9]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[9]~80_RESYN8729\, myVirtualToplevel|MEM_DATA_READ[9]~80_RESYN8729, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[9]~80\, myVirtualToplevel|MEM_DATA_READ[9]~80, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]_NEW_REG52\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]_NEW_REG52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]~18\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[9]~123\, myVirtualToplevel|MEM_DATA_READ[9]~123, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector357~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector357~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_35\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_NEW_REG1484\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[1]_NEW_REG1484, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]_NEW_REG1584\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[1]_NEW_REG1584, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[0]~62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[0]~60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[0]~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~52\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[1]~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_NEW_REG1552\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[0]_NEW_REG1552, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~53\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[1]~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]_NEW_REG1586\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[1]_NEW_REG1586, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~54\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[1]~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_NEW_REG1556\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[0]_NEW_REG1556, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~55\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[1]~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_NEW_REG1482\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[1]_NEW_REG1482, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~56\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[1]~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1436\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1436, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~57\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[1]~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]_NEW_REG1534\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[1]_NEW_REG1534, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~63\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[0]~63, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_NEW_REG1480\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[0]_NEW_REG1480, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]~64\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[1]~64, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux88~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~51\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[1]~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~52\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[1]~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~54\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[0]~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[1]~55\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[1]~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~57\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[1]~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_NEW_REG1546\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[0]_NEW_REG1546, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~55\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[1]~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_NEW_REG1606\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[1]_NEW_REG1606, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_NEW_REG1604\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[1]_NEW_REG1604, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~58\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[1]~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~56\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[0]~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_NEW_REG1548\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[0]_NEW_REG1548, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]_NEW_REG1558\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[1]_NEW_REG1558, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]~57\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[1]~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux88~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux88~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector276~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector276~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_NEW_REG783\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[16]_NEW_REG783, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][16]~feeder\, myVirtualToplevel|SD_ADDR[0][16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][16]\, myVirtualToplevel|SD_ADDR[0][16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[16]\, myVirtualToplevel|IO_DATA_READ_SD[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[0]~0\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|l1_w0_n0_mux_dataout~0\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|l1_w0_n0_mux_dataout~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[16]\, myVirtualToplevel|INT_ENABLE[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[16]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]\, myVirtualToplevel|MILLISEC_DOWN_COUNTER[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~116\, myVirtualToplevel|IO_DATA_READ~116, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~4\, myVirtualToplevel|IO_DATA_READ~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[16]\, myVirtualToplevel|IO_DATA_READ[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux89~0\, myVirtualToplevel|Mux89~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[16]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[16]~0\, myVirtualToplevel|MEM_DATA_READ[16]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]_NEW_REG76\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]_NEW_REG76, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[16]~3\, myVirtualToplevel|MEM_DATA_READ[16]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[16]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[16]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]_NEW2911\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[16]_NEW2911, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[16]_NEW2719\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[16]_NEW2719, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[16]_NEW2847\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[16]_NEW2847, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[16]_NEW2783\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[16]_NEW2783, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux26~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[16]_NEW3103\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[16]_NEW3103, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[16]_NEW2975\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[16]_NEW2975, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[16]_NEW3167\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[16]_NEW3167, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[16]_NEW3039\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[16]_NEW3039, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux26~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux26~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[16]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[16]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[0]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~296\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][1]~296, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux177~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux177~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux177~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux177~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux177~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1004~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1004~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1004~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~87\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~87, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~106\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~106, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1004~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1004~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[1]_NEW_REG1222\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[1]_NEW_REG1222, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~23\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1346~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1346~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1004~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1004~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1346~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1004~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1004~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1004~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1004~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~83\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~83, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~84\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~84, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~86\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~86, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~48\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~49\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~85\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1004~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1004~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1346~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[1]_NEW2809\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[1]_NEW2809, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[1]_NEW2937\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[1]_NEW2937, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[1]_NEW2745\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[1]_NEW2745, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[1]_NEW2873\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[1]_NEW2873, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux86~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[1]_NEW3129\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[1]_NEW3129, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[1]_NEW3065\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[1]_NEW3065, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[1]_NEW3001\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[1]_NEW3001, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[1]_NEW3193\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[1]_NEW3193, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux86~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux86~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector15~1\, myVirtualToplevel|Selector15~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector15~2\, myVirtualToplevel|Selector15~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector13~0\, myVirtualToplevel|Selector13~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_STATE.SD_STATE_WRITE\, myVirtualToplevel|SD_STATE.SD_STATE_WRITE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector19~0\, myVirtualToplevel|Selector19~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_REQ\, myVirtualToplevel|SD_DATA_REQ, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector12~0\, myVirtualToplevel|Selector12~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector11~0\, myVirtualToplevel|Selector11~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector11~1\, myVirtualToplevel|Selector11~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector16~0\, myVirtualToplevel|Selector16~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_STATE.SD_STATE_READ\, myVirtualToplevel|SD_STATE.SD_STATE_READ, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_VALID~0\, myVirtualToplevel|SD_DATA_VALID~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_VALID\, myVirtualToplevel|SD_DATA_VALID, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector21~0\, myVirtualToplevel|Selector21~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_VALID~DUPLICATE\, myVirtualToplevel|SD_DATA_VALID~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector17~0\, myVirtualToplevel|Selector17~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector17~1\, myVirtualToplevel|Selector17~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_STATE.SD_STATE_READ_1\, myVirtualToplevel|SD_STATE.SD_STATE_READ_1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector20~0\, myVirtualToplevel|Selector20~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector20~1\, myVirtualToplevel|Selector20~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_HNDSHK_IN[0]\, myVirtualToplevel|SD_HNDSHK_IN[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|hndShk_r~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|hndShk_r~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|hndShk_r~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_OVERRUN~0\, myVirtualToplevel|SD_OVERRUN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_OVERRUN~1\, myVirtualToplevel|SD_OVERRUN~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_OVERRUN\, myVirtualToplevel|SD_OVERRUN, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][6]\, myVirtualToplevel|SD_ADDR[0][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[6]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|data_o[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux77~0\, myVirtualToplevel|Mux77~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[6]\, myVirtualToplevel|IO_DATA_READ_SD[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate\, myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~27\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[6]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_NEW_REG558\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[6]_NEW_REG558, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_NEW_REG554\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[6]_NEW_REG554, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[6]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_NEW_REG556\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[6]_NEW_REG556, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~226\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][2]~226, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~20_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector571~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector571~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector571~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector571~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector571~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG947\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG947, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG937\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG937, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG945\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG945, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux7~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux7~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~0\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_WRITE_ENABLE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~1\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_WRITE_ENABLE~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_WRITE_ENABLE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_CHANNEL~0\, myVirtualToplevel|SD_CHANNEL~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_CHANNEL\, myVirtualToplevel|SD_CHANNEL, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Selector0~0\, myVirtualToplevel|Selector0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_RESET[0]\, myVirtualToplevel|SD_RESET[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~58\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~59\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~83\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v~83, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector3~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector1~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[14]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[30]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][30]\, myVirtualToplevel|SD_ADDR[0][30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[30]\, myVirtualToplevel|IO_DATA_READ_SD[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[30]~46\, myVirtualToplevel|MEM_DATA_READ[30]~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[6]~2\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[6]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_NEW_REG82\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_NEW_REG82, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~81\, myVirtualToplevel|IO_DATA_READ~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[30]\, myVirtualToplevel|IO_DATA_READ[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[30]~45\, myVirtualToplevel|MEM_DATA_READ[30]~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[30]~47\, myVirtualToplevel|MEM_DATA_READ[30]~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector344~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector344~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~36\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~37\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~38\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[14]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~39\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~40\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[15]~41\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[15]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1068~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~32\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~33\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~38\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[15]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~39\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[15]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~35\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[15]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~36\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[15]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~34\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[15]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~35\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[15]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux34~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~35\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[15]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~36\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[15]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~36\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[15]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~37\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[15]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~31\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[15]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~32\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[15]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~34\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[15]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~35\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[15]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux34~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux34~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector201~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector201~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b[0]\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[3]~6\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[3]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector4~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector4~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[11]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[27]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][27]~feeder\, myVirtualToplevel|SD_ADDR[0][27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][27]\, myVirtualToplevel|SD_ADDR[0][27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[27]\, myVirtualToplevel|IO_DATA_READ_SD[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[27]~58\, myVirtualToplevel|MEM_DATA_READ[27]~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~85\, myVirtualToplevel|IO_DATA_READ~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[27]\, myVirtualToplevel|IO_DATA_READ[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_NEW_REG18\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_NEW_REG18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[27]~57\, myVirtualToplevel|MEM_DATA_READ[27]~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[27]~59\, myVirtualToplevel|MEM_DATA_READ[27]~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector355~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector355~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~72\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~72, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[3]~66\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[3]~66, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1080~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~50\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[3]~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~51\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[3]~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~56\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[3]~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~57\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[3]~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~52\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[3]~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~53\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[3]~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~53\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[3]~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~54\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[3]~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux46~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~53\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[3]~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~54\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[3]~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~52\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[3]~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~53\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[3]~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~49\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[3]~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~50\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[3]~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~54\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~55\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3]~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux46~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux46~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector213~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector213~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][5]\, myVirtualToplevel|SD_ADDR[0][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[5]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|data_o[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux78~0\, myVirtualToplevel|Mux78~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[5]\, myVirtualToplevel|IO_DATA_READ_SD[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate\, myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~25\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[5]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_NEW_REG564\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[5]_NEW_REG564, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_NEW_REG560\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[5]_NEW_REG560, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~24\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[5]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_NEW_REG562\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[5]_NEW_REG562, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~351\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][7]~351, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~0_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector993~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1001~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1001~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~55\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~45\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1001~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1001~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1001~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1001~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[4]_NEW_REG1224\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[4]_NEW_REG1224, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~12\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1343~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1343~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1343~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux174~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux174~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux174~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux174~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux174~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1001~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1001~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1001~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~42\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~30\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~41\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~43\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~44\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1001~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1001~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux167~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux167~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux167~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux167~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux167~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux167~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux167~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux167~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux167~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux167~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux167~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1001~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1343~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[4]_NEW3059\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[4]_NEW3059, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[4]_NEW3123\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[4]_NEW3123, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[4]_NEW2995\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[4]_NEW2995, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[4]_NEW3187\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[4]_NEW3187, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux83~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[4]_NEW2931\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[4]_NEW2931, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[4]_NEW2739\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[4]_NEW2739, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[4]_NEW2803\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[4]_NEW2803, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[4]_NEW2867\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[4]_NEW2867, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux83~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux83~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][4]~feeder\, myVirtualToplevel|SD_ADDR[0][4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][4]~DUPLICATE\, myVirtualToplevel|SD_ADDR[0][4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[4]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|data_o[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux79~0\, myVirtualToplevel|Mux79~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[4]\, myVirtualToplevel|IO_DATA_READ_SD[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate\, myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[4]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_NEW_REG570\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[4]_NEW_REG570, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_NEW_REG566\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[4]_NEW_REG566, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[4]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_NEW_REG568\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[4]_NEW_REG568, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~208\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][4]~208, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~19\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~20_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal139~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[25]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8491\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8491, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[0]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]_NEW2879\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[0]_NEW2879, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].data[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[0]_NEW2751\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[0]_NEW2751, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].data[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]_NEW2815\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[0]_NEW2815, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].data[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[0]_NEW2943\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[0]_NEW2943, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].data[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux87~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]_NEW3199\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[0]_NEW3199, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].data[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]_NEW3071\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[0]_NEW3071, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].data[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]_NEW3135\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[0]_NEW3135, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].data[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[0]_NEW3007\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[0]_NEW3007, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].data[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux87~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux87~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[0]_NEW3219\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[0]_NEW3219, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~324\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][0]~324, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux171~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux171~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux171~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux171~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux171~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux171~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux171~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux171~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux171~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux171~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux171~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~24\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~10\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~12\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~13\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~5\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~11\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal142~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~4\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~14\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal142~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~15\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~16\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~17\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~18\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~19\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~20\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~21\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~22\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal142~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal142~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~16\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~23\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~25\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan23~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~46\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~47\, myVirtualToplevel|\ZPUEVO:ZPU0|ShiftRight1~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~41\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~40\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~39\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~10\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~11\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~12\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~6\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~17\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~4\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~13\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~14\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~15\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~5\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~18\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan24~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal142~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal142~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal142~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~22\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux178~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux178~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux178~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux178~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux178~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~16\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~22\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8985\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1347~3_RESYN8985, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add36~101\, myVirtualToplevel|\ZPUEVO:ZPU0|Add36~101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~20\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~18\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8987\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1347~3_RESYN8987, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1347~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1005~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_NEW_REG1210\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[0]_NEW_REG1210, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_NEW_REG1204\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[0]_NEW_REG1204, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~22\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1347~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1347~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1347~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1347~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_39\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1432\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1432, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_NEW_REG1600\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[0]_NEW_REG1600, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_NEW_REG1602\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[0]_NEW_REG1602, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]~53\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[0]~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~56\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[0]~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]_NEW_REG1618\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[0]_NEW_REG1618, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]~59\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[0]~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_NEW_REG1544\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[0]_NEW_REG1544, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~58\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[0]~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux89~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1428\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1428, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]~58\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[0]~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_NEW_REG1554\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[0]_NEW_REG1554, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]~56\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[0]~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_NEW_REG1478\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[0]_NEW_REG1478, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~65\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[0]~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_NEW_REG1550\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[0]_NEW_REG1550, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]~54\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[0]~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux89~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux89~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[0]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[0]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG690\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG690, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG688\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG688, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG684\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG684, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_WREN~0\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM2_WREN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~262\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][3]~262, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~20_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector574~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1350~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[2]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[2]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[2]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[2]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[2]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[2]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]_NEW2687\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[2]_NEW2687, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Decoder8~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1115~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1115~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1115~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_NEW_REG1488\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_NEW_REG1488, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector764~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector566~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector566~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_NEW_REG1492\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_NEW_REG1492, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector764~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector566~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector566~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector566~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_NEW_REG1490\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_NEW_REG1490, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_NEW_REG1498\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_NEW_REG1498, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector500~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector500~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector500~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_NEW_REG1500\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_NEW_REG1500, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector500~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_NEW_REG1504\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_NEW_REG1504, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1083~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1083~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1083~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_NEW_REG1502\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_NEW_REG1502, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1147~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1147~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1147~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_NEW_REG1416\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_NEW_REG1416, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector632~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_NEW_REG1418\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_NEW_REG1418, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector632~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector632~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector632~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_NEW_REG1414\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_NEW_REG1414, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_NEW_REG1412\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_NEW_REG1412, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector698~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_NEW_REG1394\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_NEW_REG1394, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1179~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1179~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1179~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_NEW_REG1396\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_NEW_REG1396, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector698~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector698~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector698~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_NEW_REG1392\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_NEW_REG1392, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_NEW_REG1390\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_NEW_REG1390, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux2~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector764~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8495\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector764~3_RESYN8495, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8497\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector764~3_RESYN8497, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector764~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1211~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1211~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1211~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1275~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1275~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1275~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_NEW_REG1512\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_NEW_REG1512, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector896~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_NEW_REG1510\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_NEW_REG1510, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector896~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector896~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector896~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_NEW_REG1508\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_NEW_REG1508, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_NEW_REG1506\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_NEW_REG1506, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector962~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector962~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector962~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_NEW_REG1456\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_NEW_REG1456, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector962~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_NEW_REG1458\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_NEW_REG1458, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1307~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1307~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1307~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_NEW_REG1460\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_NEW_REG1460, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_NEW_REG1454\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_NEW_REG1454, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector830~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_NEW_REG1594\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_NEW_REG1594, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1243~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1243~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1243~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_NEW_REG1590\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_NEW_REG1590, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector830~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector830~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector830~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_NEW_REG1592\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_NEW_REG1592, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_NEW_REG1588\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_NEW_REG1588, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux2~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux2~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_NEW_REG1296\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_NEW_REG1296, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_NEW_REG1300\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_NEW_REG1300, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector631~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector631~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12404\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector631~4_RESYN12404, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[22]~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12402\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector631~4_RESYN12402, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector631~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_NEW_REG1302\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_NEW_REG1302, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_NEW_REG1464\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_NEW_REG1464, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_NEW_REG1466\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_NEW_REG1466, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_NEW_REG1462\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_NEW_REG1462, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12408\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector697~2_RESYN12408, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12406\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector697~2_RESYN12406, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector697~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector697~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN12632\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~13_RESYN12632, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_NEW_REG1468\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_NEW_REG1468, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_NEW_REG1514\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_NEW_REG1514, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_NEW_REG1516\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_NEW_REG1516, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector499~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector499~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12412\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector499~4_RESYN12412, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12410\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector499~4_RESYN12410, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector499~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_NEW_REG1518\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_NEW_REG1518, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_NEW_REG1576\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_NEW_REG1576, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_NEW_REG1574\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_NEW_REG1574, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector565~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector565~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_NEW_REG1578\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_NEW_REG1578, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_NEW_REG1298\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_NEW_REG1298, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_RESYN8493\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector829~4_RESYN8493, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector829~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector829~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector829~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector829~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12396\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector763~4_RESYN12396, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12394\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector763~4_RESYN12394, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector763~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector763~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector763~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_NEW_REG1612\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_NEW_REG1612, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_NEW_REG1608\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_NEW_REG1608, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_NEW_REG1610\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_NEW_REG1610, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_NEW_REG1440\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_NEW_REG1440, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_NEW_REG1438\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_NEW_REG1438, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector895~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector895~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector895~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector895~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector895~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_NEW_REG1442\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_NEW_REG1442, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12398\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector961~4_RESYN12398, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12400\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector961~4_RESYN12400, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector961~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector961~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector961~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_NEW_REG1524\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_NEW_REG1524, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_NEW_REG1520\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_NEW_REG1520, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_NEW_REG1522\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_NEW_REG1522, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux1~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_RESYN8587\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector507~1_RESYN8587, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector507~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_RESYN8589\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector573~1_RESYN8589, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector573~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_RESYN8583\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector639~1_RESYN8583, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector639~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux9~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_RESYN8571\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector771~2_RESYN8571, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector771~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux9~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux9~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector567~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector765~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_RESYN12642\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector765~8_RESYN12642, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector765~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector699~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector633~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector633~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux3~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector963~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector831~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector897~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector897~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector765~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux3~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoReadIdx[2]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector215~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector215~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[29]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG682\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG682, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~40\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[1]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~38\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[1]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~39\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[1]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[1]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_NEW_REG757\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[1]_NEW_REG757, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_WREN~0\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM0_WREN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~78, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal131~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal131~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~76, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr153~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_RESYN12504\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr149~1_RESYN12504, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr149~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~92\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~92, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr152~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~80\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~80, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr153~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr153~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr153~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr152~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr153~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~49\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][9]~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~47\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][9]~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~48\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][9]~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~50\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][9]~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux147~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_RESYN12726\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr134~0_RESYN12726, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr134~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~82\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~82, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_RESYN12698\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~55_RESYN12698, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~51\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr132~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr132~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_RESYN12728\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~0_RESYN12728, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_RESYN12732\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~2_RESYN12732, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_RESYN12484\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~5_RESYN12484, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_RESYN12734\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~4_RESYN12734, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal12~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal12~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr132~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_RESYN12730\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~1_RESYN12730, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~5\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~17\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~11\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~12\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~6\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~14\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][11]~426, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~35\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][9]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][11]~427, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~36\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][9]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][11]~428, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~37\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][9]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][11]~429, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~38\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][9]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux147~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12500\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr141~6_RESYN12500, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12502\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr141~6_RESYN12502, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr141~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal67~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal67~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr141~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_RESYN12742\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr141~1_RESYN12742, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr141~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_RESYN12738\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr140~0_RESYN12738, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr140~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_RESYN12740\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr141~0_RESYN12740, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr141~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_RESYN12496\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~90_RESYN12496, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~90, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr138~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr141~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~46\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][9]~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~45\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][9]~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~43\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][9]~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~44\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][9]~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux147~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_RESYN12490\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~87_RESYN12490, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~87, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_RESYN12492\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr147~3_RESYN12492, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr147~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~83\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~83, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~64, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~67, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr147~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr145~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr147~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_RESYN12486\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr143~1_RESYN12486, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr143~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_RESYN12488\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr147~0_RESYN12488, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr147~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_RESYN12736\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr146~0_RESYN12736, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr146~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr146~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr147~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~40\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][9]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~41\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][9]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~42\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][9]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~39\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][9]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux147~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux147~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_RESYN12712\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr149~0_RESYN12712, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr149~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr151~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr151~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_RESYN12714\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr150~0_RESYN12714, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr150~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr151~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_RESYN12716\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr154~0_RESYN12716, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr154~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr152~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr154~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr150~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux133~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux133~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux135~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux135~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~79\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~79, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr154~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr154~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][8]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][8]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][8]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][8]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux148~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~66\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~66, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr145~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_RESYN8929\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~63_RESYN8929, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~63, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~68\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~68, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr148~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr148~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~59\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr144~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~14\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr145~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr148~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal99~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr148~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux121~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux121~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux123~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr148~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][8]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][8]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][8]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][8]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux148~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_RESYN12708\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr138~0_RESYN12708, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr138~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_RESYN8935\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr142~0_RESYN8935, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr142~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr139~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr142~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_RESYN12564\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr142~6_RESYN12564, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr142~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_RESYN12710\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr138~1_RESYN12710, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr138~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr142~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr142, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][8]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][8]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][8]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][8]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux148~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_RESYN8605\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr132~2_RESYN8605, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_RESYN12696\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr136~0_RESYN12696, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_RESYN12694\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr131~1_RESYN12694, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr131~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr136~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr136~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_RESYN12700\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr136~2_RESYN12700, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr136~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_RESYN12804\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr136~5_RESYN12804, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr136~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_RESYN12702\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr136~3_RESYN12702, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr136~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr136~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][8]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][8]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][8]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][8]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux148~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux148~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector442~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector442~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector442~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector442~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~67\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~67, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr162~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr162~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[23]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~68\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~68, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~0\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1209~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1209~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1209~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1209~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_RESYN9089\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector728~6_RESYN8447_RESYN9089, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector728~6_RESYN8447, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~1\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8449\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector728~6_RESYN8449, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector728~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector728~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9165\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector728~8_RESYN9165, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9167\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector728~8_RESYN9167, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector728~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8825\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1209~3_RESYN8825, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector728~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1209~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector508~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8823\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1209~3_RESYN8823, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector728~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8827\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1209~3_RESYN8827, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1209~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1209~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1273~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1273~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~3\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1273~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1273~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~4\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~6_RESYN8457\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~6_RESYN8457, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8833\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~10_RESYN8833, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12388\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1273~0_RESYN12388, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_RESYN12558\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~11_RESYN12558, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8461\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~8_RESYN8461, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_RESYN9091\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~8_RESYN8459_RESYN9091, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~8_RESYN8459, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8831\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~10_RESYN8831, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12386\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1273~0_RESYN12386, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector860~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1273~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1273~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_RESYN8829\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1241~4_RESYN8829, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1241~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~2\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1241~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector794~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~46\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8453\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1241~3_RESYN8453, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector794~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector794~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector794~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1241~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector794~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector794~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector794~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8455\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1241~3_RESYN8455, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1241~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1241~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1241~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1241~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1241~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1305~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1305~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~5\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1305~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1305~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector926~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector926~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8841\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1305~1_RESYN8841, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector926~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~6\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector926~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector926~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8843\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1305~1_RESYN8843, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8463\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector926~5_RESYN8463, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~49\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8465\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector926~5_RESYN8465, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_RESYN8837\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector926~3_RESYN8837, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector926~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector926~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1305~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1305~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux47~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1113~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~10\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1113~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1113~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1113~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector530~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8861\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1113~0_RESYN8861, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector530~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~11\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8473\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector530~8_RESYN8473, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8475\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector530~8_RESYN8475, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector530~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector530~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector530~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8859\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1113~0_RESYN8859, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_RESYN12634\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector530~6_RESYN12634, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector530~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector530~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1113~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1113~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1113~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~7\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12588\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12588, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12590\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12590, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~11_RESYN8851, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8853\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~11_RESYN8853, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8469\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~10_RESYN8469, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~9\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_RESYN9093\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~10_RESYN8467_RESYN9093, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~10_RESYN8467, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9179\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1081~5_RESYN9179, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~8\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1081~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1081~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1081~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1081~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9173\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1081~5_RESYN9173, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9177\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1081~5_RESYN9177, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9169\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~7_RESYN9169, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9171\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~7_RESYN9171, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9175\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1081~5_RESYN9175, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_RESYN9323\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~8_RESYN8845_RESYN9323, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~8_RESYN8845, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_RESYN9325\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~8_RESYN8847_RESYN9325, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~8_RESYN8847, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8849\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~8_RESYN8849, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector464~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1081~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1177~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1177~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~12\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1177~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1177~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector662~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector662~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8867\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1177~4_RESYN8867, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector662~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~53\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~13\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector662~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8869\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1177~4_RESYN8869, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector662~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector662~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12638\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector662~5_RESYN12638, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12636\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector662~5_RESYN12636, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector662~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1177~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1177~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1177~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1145~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector596~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8873\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1145~0_RESYN8873, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8875\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1145~0_RESYN8875, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|addr~14\, myVirtualToplevel|\ZPUEVO:ZPU0|addr~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector596~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector596~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~55\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector596~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_RESYN8479\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector596~4_RESYN8479, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector596~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector596~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector596~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector596~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector596~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8877\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1145~0_RESYN8877, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1145~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1145~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1145~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1145~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1145~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux47~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux47~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector214~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector214~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][3]\, myVirtualToplevel|SD_ADDR[0][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|data_o[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux80~0\, myVirtualToplevel|Mux80~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[3]\, myVirtualToplevel|IO_DATA_READ_SD[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate\, myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[3]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_NEW_REG576\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[3]_NEW_REG576, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[3]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_NEW_REG574\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[3]_NEW_REG574, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_NEW_REG572\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[3]_NEW_REG572, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~277\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][1]~277, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~19\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~20_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tIdx~0\, myVirtualToplevel|\ZPUEVO:ZPU0|tIdx~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector973~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector973~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8427\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector973~5_RESYN8427, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8425\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector973~5_RESYN8425, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector973~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1352~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1352~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[1]_NEW2685\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[1]_NEW2685, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoWriteIdx[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal4~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~5\, myVirtualToplevel|\ZPUEVO:ZPU0|MEMXACT~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~4\, myVirtualToplevel|\ZPUEVO:ZPU0|MEMXACT~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1\, myVirtualToplevel|\ZPUEVO:ZPU0|MEMXACT~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG502\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG502, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG512\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG512, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG510\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG510, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG506\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG506, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_RESYN12692\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr131~0_RESYN12692, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr131~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_RESYN12754\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr131~4_RESYN12754, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr131~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_RESYN12746\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr131~3_RESYN12746, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr131~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_RESYN12756\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr131~5_RESYN12756, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr131~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr131~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~158\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][13]~158, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~159\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][13]~159, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~156\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][13]~156, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~157\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][13]~157, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux143~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr143~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr143~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr143~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~6\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr143~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr143~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr143~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~162\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][13]~162, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~161\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][13]~161, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~163\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][13]~163, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~160\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][13]~160, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux143~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12764\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr137~6_RESYN12764, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~71, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12510\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr137~2_RESYN12510, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12766\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr137~6_RESYN12766, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12762\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr137~6_RESYN12762, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr137~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~166\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][13]~166, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~164\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][13]~164, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~167\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][13]~167, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~165\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][13]~165, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux143~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~6\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr149~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr149~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr149~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr149~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr149~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~171\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][13]~171, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~168\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][13]~168, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~169\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][13]~169, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~170\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][13]~170, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux143~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux143~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_RESYN9207\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~24_RESYN9207, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state~28\, myVirtualToplevel|\ZPUEVO:ZPU0|state~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state~29\, myVirtualToplevel|\ZPUEVO:ZPU0|state~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2\, myVirtualToplevel|\ZPUEVO:ZPU0|state.State_Mod2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[29]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1331~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state~23\, myVirtualToplevel|\ZPUEVO:ZPU0|state~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state~24\, myVirtualToplevel|\ZPUEVO:ZPU0|state~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute\, myVirtualToplevel|\ZPUEVO:ZPU0|state.State_Execute, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1363~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1348~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1065\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1065, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector506~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector638~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector506~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector506~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector638~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector638~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector638~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1154\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1154, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG977\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG977, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector572~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector572~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector572~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector572~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG979\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG979, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1107\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1107, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector506~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector506~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector506~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector506~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1109\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1156\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1156, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector704~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector704~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector704~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1158\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1158, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux8~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector968~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector968~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector968~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector968~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG983\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG983, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG981\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG981, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1051\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1051, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector902~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector902~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector902~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1053\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1053, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector770~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector770~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector770~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector770~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1218\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1218, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1216\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1216, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector836~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector836~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector836~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1202\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1202, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1200\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1200, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux8~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux8~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteHword~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~2\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteHword~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteHword, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector301~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector301~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_NEW_REG753\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[24]_NEW_REG753, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_NEW_REG749\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[24]_NEW_REG749, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[24]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[0]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[0]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~48\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr134~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_RESYN12520\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr134~1_RESYN12520, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr134~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr131~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~50\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr134~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr134~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr152~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~7\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr152~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr152~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr152~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr152~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~113\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][10]~113, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr146~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_RESYN12522\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr146~3_RESYN12522, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr146~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr146~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr146~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~112\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][10]~112, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12750\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr137~2_RESYN12750, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr137~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_RESYN12512\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr140~1_RESYN12512, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr140~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_RESYN12514\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr140~2_RESYN12514, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr140~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr140~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal46~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal46~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~102\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~102, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~7\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr140~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr140~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12526\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr140~4_RESYN12526, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12524\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr140~4_RESYN12524, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr140~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~6\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr140~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux146~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~434\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][8]~434, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9247\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~27_RESYN9247, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9245\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~27_RESYN9245, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan12~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][8]~95, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~122\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][10]~122, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~125\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][10]~125, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~124\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][10]~124, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~123\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][10]~123, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux146~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~117\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][10]~117, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~114\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][10]~114, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~115\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][10]~115, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~116\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][10]~116, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux146~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~118\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][10]~118, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~121\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][10]~121, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~120\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][10]~120, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~119\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][10]~119, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux146~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux146~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr160~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr160~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8639\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8639, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8641\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8641, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[21]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult[11]_NEW_REG1226\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult[11]_NEW_REG1226, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divResult~16\, myVirtualToplevel|\ZPUEVO:ZPU0|divResult~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1336~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1336~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1336~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~67\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~67, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~63\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~63, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~65\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~64\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~64, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~66\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~66, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector994~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1336~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.word[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~23\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~93\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~89\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~101\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~98\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~98, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~102\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~102, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]_NEW3274\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[11]_NEW3274, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_RESYN12626\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~3_RESYN12626, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_RESYN8921\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~22_RESYN8921, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~166\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5]~166, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9237\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5]~82_RESYN9237, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~78\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5]~78, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_RESYN8603\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5]~81_RESYN8603, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5]~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9239\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5]~82_RESYN9239, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9235\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5]~82_RESYN9235, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~77\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal143~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal143~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal143~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal143~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal143~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~9\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~14\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9213\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~17_RESYN9213, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~8\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~13\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[29]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[26]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~10\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~11\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~12\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9215\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~17_RESYN9215, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal143~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_RESYN12460\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal143~1_RESYN12460, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal143~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_RESYN9217\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~14_RESYN9217, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_RESYN9307\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5]~164_RESYN9307, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5]~164, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5]~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5]~82, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_RESYN12684\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[7]~43_RESYN12684, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[7]~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9221\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[8]~33_RESYN9221, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9223\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[8]~33_RESYN9223, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[8]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[9]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_RESYN8599\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[7]~48_RESYN8599, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[7]~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~45\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[7]~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~44\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~49\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[7]~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~50\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[7]~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_RESYN12682\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[8]~35_RESYN12682, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[8]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~37\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[8]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_RESYN8597\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[8]~40_RESYN8597, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[8]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~36\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~41\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[8]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~42\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[8]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_RESYN12680\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[9]~25_RESYN12680, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[9]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~28\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[9]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_RESYN8595\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[9]~31_RESYN8595, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[9]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~27\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~32\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[9]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~34\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[9]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]_NEW3280\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[9]_NEW3280, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector207~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector207~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|TIMER0_CS~2\, myVirtualToplevel|TIMER0_CS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1264\, myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1264, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_OVERRUN~1\, myVirtualToplevel|UART1|TX_OVERRUN~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART1|TX_OVERRUN\, myVirtualToplevel|UART1|TX_OVERRUN, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_OVERRUN~2\, myVirtualToplevel|UART0|TX_OVERRUN~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_OVERRUN\, myVirtualToplevel|UART0|TX_OVERRUN, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~12\, myVirtualToplevel|IO_DATA_READ~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[20]_NEW_REG1386\, myVirtualToplevel|IO_DATA_READ[20]_NEW_REG1386, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[20]\, myVirtualToplevel|MILLISEC_UP_COUNTER[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~13\, myVirtualToplevel|IO_DATA_READ~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[20]_NEW_REG1388\, myVirtualToplevel|IO_DATA_READ[20]_NEW_REG1388, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ~14\, myVirtualToplevel|IO_DATA_READ~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector11~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector11~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[4]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[20]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][20]\, myVirtualToplevel|SD_ADDR[0][20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[20]\, myVirtualToplevel|IO_DATA_READ_SD[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[20]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[20]~14\, myVirtualToplevel|MEM_DATA_READ[20]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]_NEW_REG70\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]_NEW_REG70, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]~7\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[4]~3\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[4]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[20]~15\, myVirtualToplevel|MEM_DATA_READ[20]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[20]~16\, myVirtualToplevel|MEM_DATA_READ[20]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[20]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[20]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~106\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~106, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~89\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~93\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~89\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~103\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~103, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~107\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~107, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[20]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[21]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add1~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add1~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1\, myVirtualToplevel|\ZPUEVO:ZPU0|tInsnExec~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector767~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_RESYN12652\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector767~5_RESYN12652, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector767~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector899~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector899~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector767~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux5~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector503~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector503~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector701~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector701~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector635~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector635~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12452\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector569~2_RESYN12452, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12454\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector569~2_RESYN12454, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector569~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux5~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux5~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~56\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~58\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[15]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector343~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector343~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~116\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~116, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~114\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~114, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~115\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~115, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~113\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~113, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~117\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~117, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~145\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~145, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~144\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~144, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~143\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~143, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~146\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~146, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~147\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~147, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~139\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~139, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~140\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~140, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~141\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~141, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~138\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~138, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~142\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~142, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~135\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~135, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~134\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~134, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~136\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~136, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~133\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~133, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~137\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~137, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[19]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]_NEW3301\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[19]_NEW3301, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector197~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector197~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[22]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[22]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|LessThan0~0_RESYN12604\, myVirtualToplevel|LessThan0~0_RESYN12604, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|LessThan0~0\, myVirtualToplevel|LessThan0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[10]~1\, myVirtualToplevel|MEM_DATA_READ[10]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[4]~0\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[4]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][12]~feeder\, myVirtualToplevel|SD_ADDR[0][12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][12]\, myVirtualToplevel|SD_ADDR[0][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|Mux71~0\, myVirtualToplevel|Mux71~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[12]\, myVirtualToplevel|IO_DATA_READ_SD[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|INT_ENABLE[12]\, myVirtualToplevel|INT_ENABLE[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_INTRCTL[12]\, myVirtualToplevel|IO_DATA_READ_INTRCTL[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]\, myVirtualToplevel|MICROSEC_DOWN_COUNTER[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MILLISEC_UP_COUNTER[12]\, myVirtualToplevel|MILLISEC_UP_COUNTER[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[12]~26\, myVirtualToplevel|IO_DATA_READ[12]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[12]~27\, myVirtualToplevel|IO_DATA_READ[12]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ[12]\, myVirtualToplevel|IO_DATA_READ[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SOCCFG[12]\, myVirtualToplevel|IO_DATA_READ_SOCCFG[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[12]~74_RESYN8723\, myVirtualToplevel|MEM_DATA_READ[12]~74_RESYN8723, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[12]~74\, myVirtualToplevel|MEM_DATA_READ[12]~74, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]_NEW_REG100\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]_NEW_REG100, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]~12\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4\, myVirtualToplevel|\ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[12]~147\, myVirtualToplevel|MEM_DATA_READ[12]~147, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector346~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector346~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~96\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~96, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~95\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~95, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~94\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~94, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~93\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~97\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~97, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~90\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~90, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~89\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~91\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~91, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~88\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~88, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~92\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~92, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~120\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~120, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~119\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~119, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~121\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~121, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~118\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~118, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~122\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~122, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]_NEW3292\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[14]_NEW3292, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9151\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9151, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9149\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9149, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1Invalid~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8953\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[23]~3_RESYN8953, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8955\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[23]~3_RESYN8955, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[23]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~24\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp~25\, myVirtualToplevel|\ZPUEVO:ZPU0|sp~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[18]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[18]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|sp[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|sp[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1065~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~25\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[18]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[18]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[18]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[18]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~28\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[18]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~29\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[18]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~24\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[18]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~25\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[18]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux31~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~24\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[18]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~25\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[18]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[18]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~27\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[18]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~25\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[18]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[18]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[18]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[18]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux31~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux31~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~4\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~5\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1060~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add27~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[23]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[23]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~24\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[23]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~25\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[23]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[23]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[23]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[23]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[23]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[23]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[23]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[23]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[23]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[23]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[23]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[23]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[23]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux0~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_RESYN12534\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~13_RESYN12534, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8621\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8621, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8623\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8623, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~10\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~11\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12532\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~6_RESYN12532, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12530\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~6_RESYN12530, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan2~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~1\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteByte~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~2\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteByte~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteByte, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_WREN~0\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHEL2|RAM3_WREN~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr134~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~98\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][10]~98, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~97\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][10]~97, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~99\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][10]~99, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~96\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][10]~96, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux146~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~101\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][10]~101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~103\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][10]~103, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~102\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][10]~102, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~100\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][10]~100, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux146~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~104\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][10]~104, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~107\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][10]~107, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~105\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][10]~105, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~106\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][10]~106, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux146~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~110\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][10]~110, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~109\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][10]~109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~108\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][10]~108, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~111\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][10]~111, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux146~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux146~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~31\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~33\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~32\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~34\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan26~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan26~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~35\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~36\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~51\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpMem_0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~46\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~47\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_NEW_REG296\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_NEW_REG296, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_NEW_REG300\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_NEW_REG300, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~53\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~49\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_2\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpL1_2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~39\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1190\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1190, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1192\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1192, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_NEW_REG298\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_NEW_REG298, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1194\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1194, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1196\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1196, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1198\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_Start_NEW_REG1198, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_End, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugAllInfo~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo\, myVirtualToplevel|\ZPUEVO:ZPU0|debugAllInfo, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~55\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_End~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~37\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_Idle, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0\, myVirtualToplevel|\ZPUEVO:ZPU0|inBreak~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_RESYN8615\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr132~8_RESYN8615, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr132~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr132~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr132~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~129\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][12]~129, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~127\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][12]~127, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~128\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][12]~128, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~126\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][12]~126, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux144~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~85\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr144~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr144~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr144~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr144~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr145~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~10\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr145~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr144~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~132\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][12]~132, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~133\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][12]~133, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~131\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][12]~131, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~130\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][12]~130, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux144~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_RESYN8617\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr138~6_RESYN8617, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr138~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr138~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~136\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][12]~136, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~137\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][12]~137, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~135\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][12]~135, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~134\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][12]~134, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux144~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr150~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr150~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_RESYN12752\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr150~2_RESYN12752, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr150~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr150~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~141\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][12]~141, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~138\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][12]~138, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~140\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][12]~140, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~139\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][12]~139, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux144~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux144~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_RESYN12676\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~21_RESYN12676, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~131\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~131, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~130\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~130, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~129\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~129, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~128\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~128, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~132\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~132, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add3~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add3~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]_NEW3319\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[21]_NEW3319, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]_NEW3316\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[22]_NEW3316, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal6~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal6~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal6~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan9~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[0]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~62\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add10~45\, myVirtualToplevel|\ZPUEVO:ZPU0|Add10~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pause[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|pause[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal6~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal6~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State~24\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State~16\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddrPause\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State.State_LatchAddrPause, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State~23\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State~25\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State~17\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_PreSetAddr\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State.State_PreSetAddr, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State~21\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State~22\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State~15\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State.State_LatchAddr, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State~18\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State~19\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State~14\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode\, myVirtualToplevel|\ZPUEVO:ZPU0|l1State.State_Decode, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][8]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][8]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_RESYN8613\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr139~2_RESYN8613, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr139~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_RESYN12748\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr139~3_RESYN12748, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr139~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr139~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~75\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][11]~75, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~73\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][11]~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~76\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][11]~76, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~74\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][11]~74, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux145~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~1\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr133~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr132~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~94\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~94, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr133~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr133~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~66\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][11]~66, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~67\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][11]~67, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~65\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][11]~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~68\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][11]~68, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux145~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr145~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_RESYN12508\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr145~4_RESYN12508, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr145~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr145~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~72\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][11]~72, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~71\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][11]~71, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~69\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][11]~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~70\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][11]~70, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux145~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_RESYN12516\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr151~4_RESYN12516, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr151~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_RESYN12518\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr151~5_RESYN12518, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr151~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr151~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~78\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][11]~78, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~77\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][11]~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~79\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][11]~79, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~80\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][11]~80, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux145~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux145~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux145~10_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr159\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr159, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~53\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[6]~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9225\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[6]~61_RESYN9225, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9229\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[6]~61_RESYN9229, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9233\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[6]~61_RESYN9233, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~55\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[6]~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_RESYN12686\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[6]~60_RESYN12686, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[6]~60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_RESYN8601\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[6]~58_RESYN8601, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[6]~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~54\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9231\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[6]~61_RESYN9231, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[6]~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]_NEW1940\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[6]_NEW1940, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal135~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal135~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal135~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal135~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal135~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal135~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal135~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal135~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal135~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal135~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal135~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2\, myVirtualToplevel|\ZPUEVO:ZPU0|CACHE_LEVEL1~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]_NEW1868\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[20]_NEW1868, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1FetchIdx[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal136~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][11]~431, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~92\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][11]~92, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~94\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][11]~94, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~93\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][11]~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~91\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][11]~91, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux145~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][11]~433, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~83\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][11]~83, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~85\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][11]~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~86\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][11]~86, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~84\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][11]~84, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux145~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr133~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~82\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][11]~82, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860_RESYN12810\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860_RESYN12810, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][11]~432, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~81\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][11]~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux145~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~90\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][11]~90, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~89\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][11]~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][11]~430, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~88\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][11]~88, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~87\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][11]~87, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux145~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux145~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~69\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~70\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~70, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~68\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~68, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~67\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~67, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~71\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~71, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~61\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][9]~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~64\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][9]~64, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~62\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][9]~62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~63\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][9]~63, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux147~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~53\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][9]~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~56\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][9]~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~55\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][9]~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~54\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][9]~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux147~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~7\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr141~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_RESYN12744\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~7_RESYN12744, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr135~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~51\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][9]~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~52\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][9]~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux147~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~57\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][9]~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~58\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][9]~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~59\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][9]~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~60\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][9]~60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux147~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux147~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux147~10_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][8]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~24\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][8]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][8]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~25\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][8]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux148~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~31\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][8]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~33\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][8]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~34\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][8]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~32\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][8]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux148~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~30\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][8]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~27\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][8]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~29\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][8]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~28\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][8]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux148~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][8]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136_RESYN12724\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr136_RESYN12724, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr136, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]_NEW1850\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][8]_NEW1850, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][8]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux148~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux148~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux148~10_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~74\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~74, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~75\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~75, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~73\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~72\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~72, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~76\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~76, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux146~10_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~124\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~124, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~125\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~125, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~126\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~126, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~123\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~123, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~127\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~127, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[22]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~7\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~5\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add22~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add22~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add25~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add25~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add24~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add24~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add23~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add23~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~3\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add32~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add32~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~11\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~12\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[23]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Invalid~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Invalid~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~42\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~41\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~43\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_TOSNOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr116~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[14]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[14]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[16]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1675~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1675~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[23]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[23]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add6~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add6~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector193~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector193~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]_NEW3344\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[23]_NEW3344, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|process_1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuLastEN\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuLastEN, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|process_1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_NOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~48\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~47\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~49\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_NOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~50\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~51\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[31]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.valid, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector420~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1349~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector420~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector420~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1349~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.valid, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS.valid, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~154\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~154, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|TOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|TOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~156\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~156, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~157\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~157, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12462\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~7_RESYN12462, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12464\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~7_RESYN12464, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector387~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector387~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector387~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~155\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~155, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_RESYN13460\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~158_RESYN8941_RESYN13460, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~158_RESYN8941, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~158\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~158, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~159\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~159, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add37~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~64\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~64, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~65\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~63\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~63, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~62\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~66\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~66, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~172\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][13]~172, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]_NEW1854\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][13]_NEW1854, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_RESYN12528\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr137~3_RESYN12528, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr137~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~88\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~88, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~4\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr137~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_RESYN12758\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~104_RESYN12758, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104\, myVirtualToplevel|\ZPUEVO:ZPU0|tDecodedOpcode~104, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~5_RESYN12760\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr137~5_RESYN12760, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852_RESYN12808\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852_RESYN12808, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~173\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][13]~173, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux143~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~178\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][13]~178, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~181\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][13]~181, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~179\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][13]~179, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~180\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][13]~180, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux143~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~185\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][13]~185, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~183\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][13]~183, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~182\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][13]~182, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~184\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][13]~184, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux143~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~174\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][13]~174, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~177\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][13]~177, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~175\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][13]~175, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~176\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][13]~176, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux143~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux143~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux143~10_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector363~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~0\, myVirtualToplevel|\ZPUEVO:ZPU0|idimFlag~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~1\, myVirtualToplevel|\ZPUEVO:ZPU0|idimFlag~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|idimFlag~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~0\, myVirtualToplevel|\ZPUEVO:ZPU0|intTriggered~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered\, myVirtualToplevel|\ZPUEVO:ZPU0|intTriggered, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1\, myVirtualToplevel|\ZPUEVO:ZPU0|inBreak~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~2\, myVirtualToplevel|\ZPUEVO:ZPU0|inBreak~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|inBreak\, myVirtualToplevel|\ZPUEVO:ZPU0|inBreak, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12718\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~153_RESYN12718, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~152\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~152, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~149\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~149, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector386~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector386~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12722\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~153_RESYN12722, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12720\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~153_RESYN12720, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_RESYN13458\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~151_RESYN8937_RESYN13458, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~151_RESYN8937, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8939\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~151_RESYN8939, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~151\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~151, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~153\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~153, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~153\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][12]~153, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~152\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][12]~152, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~154\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][12]~154, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~155\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][12]~155, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux144~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~144\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][12]~144, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~147\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][12]~147, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~146\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][12]~146, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~145\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][12]~145, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux144~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~148\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][12]~148, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~151\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][12]~151, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~150\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][12]~150, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~149\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][12]~149, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux144~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~143\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][12]~143, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]_NEW1856\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][12]_NEW1856, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]_NEW1858\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][12]_NEW1858, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~142\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][12]~142, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux144~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux144~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux144~10_Duplicate, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[12]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~85\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~84\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~84, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~86\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~86, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~83\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~83, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~87\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~87, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]_NEW3277\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[10]_NEW3277, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector206~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector206~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_CS~0\, myVirtualToplevel|SD_CS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_CS_RESYN9119\, myVirtualToplevel|SD_CS_RESYN9119, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_CS_RESYN9121\, myVirtualToplevel|SD_CS_RESYN9121, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_CS\, myVirtualToplevel|SD_CS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[17]~25\, myVirtualToplevel|MEM_DATA_READ[17]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector14~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector14~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[1]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|error_o[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[17]~feeder\, myVirtualToplevel|IO_DATA_READ_SD[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][17]\, myVirtualToplevel|SD_ADDR[0][17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_DATA_READ_SD[17]\, myVirtualToplevel|IO_DATA_READ_SD[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[17]~26\, myVirtualToplevel|MEM_DATA_READ[17]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[17]~27\, myVirtualToplevel|MEM_DATA_READ[17]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector199~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector199~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[17]_NEW3333\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[17]_NEW3333, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_SELECT_RESYN9117\, myVirtualToplevel|IO_SELECT_RESYN9117, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_SELECT_RESYN9115\, myVirtualToplevel|IO_SELECT_RESYN9115, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|IO_SELECT\, myVirtualToplevel|IO_SELECT, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_BUSY~1_RESYN12610\, myVirtualToplevel|MEM_BUSY~1_RESYN12610, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_READ_ENABLE_LAST\, myVirtualToplevel|MEM_READ_ENABLE_LAST, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_BUSY~1_RESYN12608\, myVirtualToplevel|MEM_BUSY~1_RESYN12608, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_BUSY~1\, myVirtualToplevel|MEM_BUSY~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoReadIdx[2]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoReadIdx[2]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoReadIdx[2]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoReadIdx[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add5~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Add5~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoReadIdx[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add5~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add5~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1066~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[17]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~24\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[17]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[6].addr[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[17]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[17]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[5].addr[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~24\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[17]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~25\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[17]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[7].addr[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[17]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[17]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[4].addr[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux32~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[17]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~27\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[17]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[0].addr[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[17]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~24\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[17]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[1].addr[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[17]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[17]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[3].addr[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[17]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[17]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxFifo[2].addr[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux32~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux32~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan3~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan3~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~11\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~9\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~10\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan3~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~12\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan3~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~7\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~8\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12582\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12582, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12586\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12586, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12584\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12584, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~10\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan3~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan3~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan3~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan3~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8625\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8625, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2MxAddrInCache~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2WriteData[29]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_NEW_REG993\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Write_NEW_REG993, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~1\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Write~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_NEW_REG997\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Write_NEW_REG997, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr128~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr128~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Write~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_NEW_REG995\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Write_NEW_REG995, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_NEW_REG987\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Write_NEW_REG987, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_NEW_REG991\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Write_NEW_REG991, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Write~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]_NEW3313\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[20]_NEW3313, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~3\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2FetchIdx[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~18\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~10\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Invalid~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~16\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_RESYN12620\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~13_RESYN12620, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~14\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~15\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~10\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~11\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~6\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~9\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~9\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Invalid~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~3\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Invalid~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Invalid~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3\, myVirtualToplevel|\ZPUEVO:ZPU0|MEMXACT~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]_NEW2664\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17]_NEW2664, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal0~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal0~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal0~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal0~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal0~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal0~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal0~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal0~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal0~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal0~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal0~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~38\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~39\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~40\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector203~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector203~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]_NEW3337\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[13]_NEW3337, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[4]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[5]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal5~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuBank[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][5]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][5]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][5]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][5]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux13~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux13~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[3]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][3]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][3]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][3]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][3]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux15~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux15~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][4]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][4]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][4]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux14~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux14~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal6~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[9]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][9]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][9]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][9]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][9]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux9~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux9~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[10]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][10]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][10]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux8~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux8~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~4\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal6~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[6]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[6]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][6]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][6]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][6]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux12~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux12~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[7]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][7]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][7]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][7]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux11~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux11~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~3\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal6~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux18~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux18~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux17~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux17~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[2]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[2]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][2]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][2]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][2]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux16~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux16~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal6~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[11]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[11]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[8]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuRow[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux7~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux7~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][8]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][8]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][8]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux10~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux10~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal6~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~5\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal6~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[0]~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[0]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|process_0~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~17\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~14\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~15\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~9\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~10\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~11\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add3~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~13\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal5~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~4\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~6\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~7\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~8\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|process_0~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~41\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add2~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~17\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add2~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[2]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~13\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add2~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3]~DUPLICATE\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~9\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add2~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[4]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~5\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add2~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[5]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add2~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[6]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~25\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add2~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[7]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~21\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add2~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[8]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~29\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add2~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[9]~DUPLICATE\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~37\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add2~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[10]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[9]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~33\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Add2~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[11]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|process_0~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux93~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux93~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdDone~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdDone~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdDone~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~3\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdDone~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdDone, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDoneLast\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDoneLast, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|process_1~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~5\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~6\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~44\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_TOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~45\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~46\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_TOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid\, myVirtualToplevel|\ZPUEVO:ZPU0|muxTOS.valid, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~110\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~110, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~109\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~111\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~111, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~108\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~108, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~112\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~112, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|pc[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~17\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9139\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~20_RESYN9139, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9141\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~20_RESYN9141, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9143\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~20_RESYN9143, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan1~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL2Invalid~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~63\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~63, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~62\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~64\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~64, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector218~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector218~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.valid, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[3]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~85\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[3]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1694~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1694~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~49\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~53\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~69\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1692~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1692~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~73\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1691~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1691~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~77\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1690~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1690~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add44~57\, myVirtualToplevel|\ZPUEVO:ZPU0|Add44~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1689~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1689~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~61\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1688~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1688~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add56~65\, myVirtualToplevel|\ZPUEVO:ZPU0|Add56~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1686~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1686~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal148~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal148~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal149~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal149~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal149~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal153~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal153~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~45\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpL2_1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~50\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_2\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpL2_2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~41\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~42\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpMem, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpL1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~38\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpL1~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[12]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1687~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1687~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal149~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal149~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~43\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpL1_1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1693~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1693~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal154~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal154~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~44\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpMem_1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1_RTM0883\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpMem_1_RTM0883, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_NEW_REG881\, myVirtualToplevel|\ZPUEVO:ZPU0|debugLoad_NEW_REG881, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugOutputOnce~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugOutputOnce~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce\, myVirtualToplevel|\ZPUEVO:ZPU0|debugOutputOnce, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugLoad~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~160\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~160, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~161\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~161, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42\, myVirtualToplevel|\ZPUEVO:ZPU0|RotateRight0~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector362~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector362~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan26~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux255~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux254~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux254~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux255~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux255~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan25~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12538\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan25~5_RESYN12538, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12536\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan25~5_RESYN12536, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan25~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22\, myVirtualToplevel|\ZPUEVO:ZPU0|PROCESSOR~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DATA~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugLoad_OTERM878~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_NEW_REG877\, myVirtualToplevel|\ZPUEVO:ZPU0|debugLoad_NEW_REG877, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugLoad_OTERM876~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_NEW_REG875\, myVirtualToplevel|\ZPUEVO:ZPU0|debugLoad_NEW_REG875, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr179~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr177~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugLoad_OTERM880~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_NEW_REG879\, myVirtualToplevel|\ZPUEVO:ZPU0|debugLoad_NEW_REG879, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1659~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1659~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal11~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~21\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[2]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~25\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~13\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~29\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~49\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~9\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~5\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~53\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~17\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~5\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~57\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~61\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal10~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~33\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~37\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~41\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~45\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add12~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_COUNTER[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal10~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal10~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal10~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal10~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_CLOCK~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_CLOCK, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[16]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[16]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_CLOCK~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_DATA_LOADED, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~8\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~7\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~6\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~5\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_STATE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_STATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_DATA_LOADED~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_DATA_LOADED~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add15~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add16~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal11~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~33\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add16~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~21\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add16~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~37\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add16~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~41\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add16~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal11~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal11~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~25\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add16~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal11~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|process_2~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[0]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~5\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add16~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~9\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add16~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~13\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add16~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~17\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add16~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~29\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add16~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~29\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add13~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~33\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add13~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~21\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add13~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~25\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add13~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~37\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add13~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~41\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add13~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~13\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add13~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~17\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add13~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal12~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~45\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add13~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~5\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal12~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~5\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add13~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~9\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add13~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add13~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal12~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal12~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1356~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan25~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~162\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~162, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS_NEW2180\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS_NEW2180, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_TOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_TOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Decoder0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_TOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_TOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_TOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_TOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_TOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_TOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux28~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_TOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_TOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux28~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_PC~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1379~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_PC~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal148~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal148~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal148~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Equal148~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1701~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1701~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC_WidthCounter[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1700~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1700~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC_WidthCounter[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1358~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1699~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1699~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC_WidthCounter[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugPC_WidthCounter[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1379~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1379~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC_NEW2182\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_PC_NEW2182, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_PC, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_PC\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_PC, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_PC\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_PC, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_PC\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_PC, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_PC\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_PC, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_PC\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_PC, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux26~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux26~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~14\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.WRITE_PC, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP_NEW2184\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_SP_NEW2184, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_SP, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_SP\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_SP, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_SP\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_SP, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_SP\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_SP, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux27~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux27~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~13\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.WRITE_SP, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~15\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~16\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[39]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS_NEW2178\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS_NEW2178, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_NOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_NOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_NOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_NOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_NOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_NOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_NOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_NOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux29~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux29~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~17\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_ADD_SEPERATOR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1377~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1377~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE_NEW2188\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_OPCODE_NEW2188, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux24~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux24~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~11\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_ADD_SPACE~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~46\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add14~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~42\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add14~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~38\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add14~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~34\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add14~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~30\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add14~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~26\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add14~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~22\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add14~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~18\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add14~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add14~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add14~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~9\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add14~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_ADD_SEPERATOR~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_ADD_SPACE~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_ADD_SPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_SPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.FMT_PRE_SPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222_RESYN12864\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222_RESYN12864, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.FMT_PRE_CR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_PRE_CR\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].FMT_PRE_CR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_PRE_CR\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].FMT_PRE_CR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_PRE_CR\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].FMT_PRE_CR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux4~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux4~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_ADD_SEPERATOR~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_ADD_SEPERATOR~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_ADD_SEPERATOR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~32\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector42~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector44~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector44~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE_NEW2186\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE_NEW2186, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DECODED_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DECODED_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DECODED_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DECODED_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux25~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DECODED_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DECODED_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux25~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~12\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[21]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[57]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DATA~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3_NEW2218\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DATA3_NEW2218, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DATA3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux22~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux22~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DATA, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174_RESYN12858\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174_RESYN12858, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux20~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux20~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG348\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG348, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG238\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG238, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_RTM0364\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr179~0_RTM0364, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[0]_NEW_REG362\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[0]_NEW_REG362, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1354~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~9\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~8\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~10\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1356~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[1]_NEW2226\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[1]_NEW2226, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~5\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~6\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~7\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal2~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~21\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.WRITE_DATA, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2_NEW2220\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DATA2_NEW2220, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DATA2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux21~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux21~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~22\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.WRITE_DATA2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~19\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.WRITE_DATA3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4_NEW2216\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DATA4_NEW2216, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.WRITE_DATA4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux23~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux23~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~20\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.WRITE_DATA4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[3]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_DATA_PRTMODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].FMT_DATA_PRTMODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_DATA_PRTMODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].FMT_DATA_PRTMODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_DATA_PRTMODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].FMT_DATA_PRTMODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux1~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~41\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~42\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_WRITE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_SPLIT_DATA~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_SPLIT_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector112~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector112~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[63]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BITCNT[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BITCNT[0]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BITCNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[1]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BITCNT[1]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BITCNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[2]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BITCNT[2]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BITCNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BITCNT[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_NIBBLECNT~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_NIBBLECNT~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_NIBBLECNT, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[21]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[3]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[30]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[2]_NEW2190\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[2]_NEW2190, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux11~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux11~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux11~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add4~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[2]_NEW2196\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[2]_NEW2196, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux14~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux14~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux14~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[2]_NEW2198\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[2]_NEW2198, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux17~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux17~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux17~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux8~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux8~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux8~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add4~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector13~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector44~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_LOAD~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector44~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector44~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~5\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector44~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[0]_NEW2210\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[0]_NEW2210, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux13~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux13~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux13~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG604\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG604, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1363~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG614\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG614, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG606\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG606, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG610\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG610, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG608\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG608, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr172, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG612\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_NEW_REG612, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1363~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux10~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux10~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux10~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~5\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~7\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[0]_NEW2212\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[0]_NEW2212, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux16~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux16~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux16~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[0]_NEW2214\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[0]_NEW2214, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux19~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux19~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux19~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~6\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~8\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~6\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector44~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~17\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~13\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[1]_NEW2200\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[1]_NEW2200, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux12~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux12~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux12~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[1]_NEW2208\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[1]_NEW2208, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux18~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux18~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux18~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux9~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux9~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux9~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[1]_NEW2206\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[1]_NEW2206, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux15~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux15~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux15~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add4~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add4~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector43~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector43~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~9\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector42~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector42~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~5\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector41~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector41~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~125\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~125, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~113\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~113, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~109\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~109, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~105\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~105, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~101\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~6\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|LessThan2~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~121\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~121, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~117\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~117, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~73\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~69\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~57\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~53\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~65\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[15]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[15]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~61\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[16]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~97\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~97, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~93\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~89\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~85\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~81\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~77\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~49\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~45\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~33\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~29\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~41\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~37\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|LessThan2~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[26]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[26]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~25\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~21\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|LessThan2~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[25]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[25]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|LessThan2~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|LessThan2~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|LessThan2~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~5\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|LessThan2~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|LessThan2~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_WORDCNT[2]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_WORDCNT[2]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_WORDCNT[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector111~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_WORDCNT[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_SPLIT_DATA~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_SPLIT_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector113~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector113~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_WORDCNT[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector111~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~44\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~45\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~55\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~34\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~35\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~36\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[63]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector13~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add8~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector13~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_BYTECNT[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|LessThan2~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~30\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~38\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~39\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~29\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_PRECR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~53\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_PRECR~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~60\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~61\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_ADD_SPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~59\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~51\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~52\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_START, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|WideOr18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_LOAD~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_LOAD, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal12~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal12~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[0]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~5\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add15~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~9\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add15~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~13\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add15~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~17\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add15~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~29\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add15~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~33\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add15~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~21\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add15~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~37\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add15~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~41\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add15~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~25\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add15~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~13\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Add14~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_FULL~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_NEW_REG1142\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_END_NEW_REG1142, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG775\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG775, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE_NEW2170\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE_NEW2170, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_SPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_SPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_SPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_SPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_SPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_SPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_SPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_SPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux3~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_SPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_SPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~24\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_NEW_REG871\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_NEW_REG871, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~56\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG779\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG779, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG771\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG771, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_NEW_REG873\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_NEW_REG873, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_NEW_REG869\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_NEW_REG869, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~57\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1358~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1358~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1358~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1358~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF_NEW2172\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF_NEW2172, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_CRLF\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_CRLF, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux5~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_CRLF\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_CRLF, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux5~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~23\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~54\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG773\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG773, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG777\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_NEW_REG777, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~58\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~48\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~49\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_NEW_REG1144\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_END_NEW_REG1144, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~47\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_IDLE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|process_0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|process_0~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal1~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0\, myVirtualToplevel|\ZPUEVO:ZPU0|divComplete~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|READY~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState~40\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpL2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr195~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0\, myVirtualToplevel|\ZPUEVO:ZPU0|MEMXACT~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~52\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~37\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState~65\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_Idle~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle\, myVirtualToplevel|\ZPUEVO:ZPU0|mxState.MemXact_Idle, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0\, myVirtualToplevel|\ZPUEVO:ZPU0|WideOr123~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector241~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector245~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector245~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~8\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add2~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Add2~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add2~41\, myVirtualToplevel|\ZPUEVO:ZPU0|Add2~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~11\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector244~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector244~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add2~37\, myVirtualToplevel|\ZPUEVO:ZPU0|Add2~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~10\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector243~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector243~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add2~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Add2~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~1\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector242~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector242~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add2~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add2~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector241~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector241~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add2~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Add2~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~3\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector240~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector240~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add2~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Add2~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~4\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector239~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector239~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add2~33\, myVirtualToplevel|\ZPUEVO:ZPU0|Add2~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~9\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector238~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector238~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add2~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Add2~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~2\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector237~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector237~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add2~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Add2~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~6\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector236~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector236~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add2~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Add2~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~5\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector235~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector235~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxHoldCycles[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~0\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan4~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~1\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan4~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan4~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_ADDR[23]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[28]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|MEM_DATA_OUT[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[28]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[12]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[12]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux175~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux175~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~20\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal5~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~14\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~enfeeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~enfeeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[13]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[13]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~5\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[29]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux176~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux176~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[14]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[14]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~6\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[30]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux177~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux177~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~enfeeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~enfeeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[15]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[15]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~7\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[31]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux179~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux179~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~enfeeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~enfeeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[16]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[16]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux162~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux162~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~enfeeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~enfeeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[17]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[17]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[1]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux164~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux164~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[18]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[18]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[2]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[2]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux165~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux165~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~enfeeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~enfeeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[3]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[3]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[19]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[19]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux166~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux166~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~enfeeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~enfeeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[4]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[4]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux167~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux167~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~enfeeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~enfeeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[5]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[5]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux168~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux168~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~enfeeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~enfeeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[6]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[6]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[22]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[22]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux169~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux169~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~enfeeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~enfeeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[7]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[7]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[23]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[23]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux170~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux170~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~enfeeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~enfeeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~9\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[24]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux171~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux171~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~enfeeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~enfeeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[9]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[9]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~10\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[25]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux172~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux172~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~enfeeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~enfeeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~11\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[26]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[10]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[10]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux173~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux173~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[11]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[11]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~12\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[27]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux174~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux174~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~reg0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~reg0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~enfeeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~enfeeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~en\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~en, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~6\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal12~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~7\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Equal12~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO~21\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA[0]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_DATA[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector114~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[23]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[30]_NEW2156\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[30]_NEW2156, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux347~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux347~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux347~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[63]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[39]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[54]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[39]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN8819\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~13_RESYN8819, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_RESYN12786\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~163_RESYN12786, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|pc~163\, myVirtualToplevel|\ZPUEVO:ZPU0|pc~163, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[10]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_RESYN9163\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~12_RESYN9163, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12\, myVirtualToplevel|\ZPUEVO:ZPU0|LessThan10~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[10]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[10]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[10]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Add48~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1536~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1536~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13338\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13338, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13340\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13340, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux189~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux189~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux189~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1414~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1414~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1414~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1414~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG354\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG354, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG352\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG352, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG224\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG224, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG346\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG346, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_162\, myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_162, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[31]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG350\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[32]_NEW_REG350, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1414~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux61~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux61~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux61~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG318\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG318, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add45~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_NEW_REG448\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[5]_NEW_REG448, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1478~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_NEW_REG464\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[32]_NEW_REG464, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Add45~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux404~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux404~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_NEW_REG462\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[32]_NEW_REG462, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1478~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_NEW_REG466\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[32]_NEW_REG466, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1478~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[32]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[32]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[32]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[32]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux125~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[32]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[32]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[32]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[32]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[32]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[32]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux125~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux125~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Add52~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[42]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[42]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[42]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[42]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1592~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[42]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1592~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1592~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1592~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1592~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1592~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1592~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1592~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1592~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13090\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13090, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13092\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13092, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux253~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[32]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[32]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux253~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux253~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector76~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector76~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[0]_NEW2012\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[0]_NEW2012, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux409~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux409~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux409~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[0]_NEW2014\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[0]_NEW2014, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux377~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux377~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux377~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~46\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[32]~46, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~47\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[32]~47, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~50\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[8]~50, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_NEW_REG803\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[11]_NEW_REG803, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_NEW_REG865\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[31]_NEW_REG865, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_NEW_REG1099\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[27]_NEW_REG1099, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_NEW_REG801\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[11]_NEW_REG801, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_NEW_REG1103\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[26]_NEW_REG1103, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_NEW_REG861\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[22]_NEW_REG861, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_NEW_REG857\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[21]_NEW_REG857, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_NEW_REG841\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[17]_NEW_REG841, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_NEW_REG849\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[16]_NEW_REG849, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_NEW_REG805\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[11]_NEW_REG805, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_NEW_REG813\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[10]_NEW_REG813, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_NEW_REG809\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[9]_NEW_REG809, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_NEW_REG817\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[8]_NEW_REG817, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1564~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1564~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13274\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13274, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13276\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13276, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux221~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux221~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux221~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[12]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[12]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[12]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1620~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1620~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1620~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[12]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1620~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1620~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add40~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Add40~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[12]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1620~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1620~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1620~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1620~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12878\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12878, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12880\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12880, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux285~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux285~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux285~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1508~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG316\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG316, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG322\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG322, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux432~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux432~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux432~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux432~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux432~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG324\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG324, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1508~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux157~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux157~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux157~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN~100\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN~100, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG438\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG438, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_NEW_REG580\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[1]_NEW_REG580, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_NEW_REG586\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[0]_NEW_REG586, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG332\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG332, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_NEW_REG588\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[0]_NEW_REG588, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1446~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1446~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1446~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_NEW_REG590\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[0]_NEW_REG590, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1446~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux93~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux93~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux93~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[0]~89\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[0]~89, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[42]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector362~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[42]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[29]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_RESYN9299\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[10]~20_RESYN9299, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[10]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9047\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1438~2_RESYN9047, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9045\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1438~2_RESYN9045, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9049\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1438~2_RESYN9049, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1438~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[8]_NEW3235\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[8]_NEW3235, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux85~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux85~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux85~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[10]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[10]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1556~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[10]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1556~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[10]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1556~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1556~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1556~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1556~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1556~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1556~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1556~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1556~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12938\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12938, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12940\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12940, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux213~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux213~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux213~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1612~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1612~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1612~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1612~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1612~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1612~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1612~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1612~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1612~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12942\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12942, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12944\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12944, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux277~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux277~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux277~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1500~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1500~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12934\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12934, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12936\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12936, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux149~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux149~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux149~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector100~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[6]~78, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1618~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1618~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1618~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1618~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1618~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1618~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1618~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1618~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1618~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12874\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12874, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12876\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12876, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux283~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux283~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux283~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec\, myVirtualToplevel|\ZPUEVO:ZPU0|\PROCESSOR:tInsnExec, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector362~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~2\, myVirtualToplevel|\ZPUEVO:ZPU0|tInsnExec~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[62]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG308\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG308, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG302\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG302, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1506~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG306\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG306, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1506~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG310\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG310, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1_RTM0314\, myVirtualToplevel|\ZPUEVO:ZPU0|debugState.Debug_DumpL1_1_RTM0314, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG312\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG312, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG304\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[2]_NEW_REG304, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1506~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux155~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux155~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux155~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1430~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[27]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG376\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG376, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG374\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG374, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1444~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG378\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG378, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1444~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1444~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG382\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG382, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1444~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG380\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[2]_NEW_REG380, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1444~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux91~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux91~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux91~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1562~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1562~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13266\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13266, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13268\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13268, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux219~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux219~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux219~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~91\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[2]~91, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1445~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1445~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1445~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_NEW_REG584\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[1]_NEW_REG584, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_NEW_REG578\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[1]_NEW_REG578, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_NEW_REG582\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[1]_NEW_REG582, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1445~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux92~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux92~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux92~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1507~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[34]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1507~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1507~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[1]_NEW2276\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[1]_NEW2276, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux156~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux156~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux156~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1563~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1563~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13262\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13262, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13264\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13264, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux220~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux220~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux220~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~94\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[1]~94, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1619~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1619~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1619~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1619~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1619~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1619~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1619~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1619~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1619~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12870\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12870, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12872\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12872, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux284~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux284~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux284~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[1]~90, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~95\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[1]~95, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~96\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[1]~96, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~92\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[2]~92, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~93\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[2]~93, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1617~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1617~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1617~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1617~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1617~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1617~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1617~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1617~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1617~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12866\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12866, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12868\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12868, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux282~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux282~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux282~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9067\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1443~2_RESYN9067, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9069\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1443~2_RESYN9069, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9071\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1443~2_RESYN9071, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1443~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[3]_NEW3225\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[3]_NEW3225, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux90~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux90~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux90~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1561~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1561~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13270\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13270, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13272\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13272, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux218~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux218~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux218~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1505~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1505~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1505~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[3]_NEW2272\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[3]_NEW2272, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux154~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux154~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux154~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~97\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[3]~97, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~98\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[3]~98, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~99\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[3]~99, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1616~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1616~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1616~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1616~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1616~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1616~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1616~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1616~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1616~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12882\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12882, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12884\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12884, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux281~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux281~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux281~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1560~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1560~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13286\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13286, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13288\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13288, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux217~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux217~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux217~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1442~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_NEW_REG386\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[4]_NEW_REG386, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1442~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1442~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_NEW_REG388\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[4]_NEW_REG388, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1442~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_NEW_REG384\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[4]_NEW_REG384, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1442~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux89~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux89~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux89~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1504~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux428~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux428~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1504~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1504~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG446\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG446, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG436\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG436, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG442\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG442, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG434\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG434, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\PROCESSOR:tInsnExec~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG444\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG444, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1504~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux153~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux153~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux153~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector104~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector104~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~87\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[4]~87, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~88\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[4]~88, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1503~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_NEW_REG454\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[5]_NEW_REG454, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux427~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux427~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_NEW_REG450\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[5]_NEW_REG450, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1503~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_NEW_REG452\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[5]_NEW_REG452, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1503~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux152~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux152~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux152~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1615~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1615~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1615~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1615~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12902\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12902, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1615~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1615~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1615~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1615~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1615~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12904\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12904, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux280~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux280~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux280~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1559~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1559~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13278\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13278, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13280\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13280, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux216~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux216~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux216~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9057\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1441~2_RESYN9057, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9055\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1441~2_RESYN9055, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9059\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1441~2_RESYN9059, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1441~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[5]_NEW3231\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[5]_NEW3231, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux88~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux88~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux88~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector103~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector103~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~82\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[5]~82, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~83\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[5]~83, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1614~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1614~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1614~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1614~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12918\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12918, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1614~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1614~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1614~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1614~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1614~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12920\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12920, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux279~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux279~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux279~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1502~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_NEW_REG478\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[6]_NEW_REG478, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux426~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux426~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_NEW_REG476\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[6]_NEW_REG476, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1502~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_NEW_REG480\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[6]_NEW_REG480, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1502~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux151~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux151~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux151~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1440~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1440~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_NEW_REG400\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[6]_NEW_REG400, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1440~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_NEW_REG396\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[6]_NEW_REG396, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1440~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_NEW_REG398\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[6]_NEW_REG398, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1440~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux87~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux87~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux87~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1558~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1558~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13282\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13282, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13284\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13284, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux215~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux215~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux215~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector102~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector102~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~79\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[6]~79, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~80\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[6]~80, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1613~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1613~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1613~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1613~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1613~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1613~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1613~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1613~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1613~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12886\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12886, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12888\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12888, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux278~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux278~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux278~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG440\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[4]_NEW_REG440, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux425~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux425~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1501~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1501~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_NEW_REG927\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[7]_NEW_REG927, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_NEW_REG925\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[7]_NEW_REG925, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1501~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux150~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux150~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux150~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1557~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1557~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13290\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13290, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13292\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13292, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux214~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux214~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux214~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9061\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1439~2_RESYN9061, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9063\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1439~2_RESYN9063, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9065\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1439~2_RESYN9065, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1439~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[7]_NEW3227\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[7]_NEW3227, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux86~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux86~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux86~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector101~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector101~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~85\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[7]~85, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~86\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[7]~86, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector100~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_NEW_REG819\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[8]_NEW_REG819, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[8]~76, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1437~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_NEW_REG392\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[9]_NEW_REG392, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1437~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1437~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_NEW_REG394\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[9]_NEW_REG394, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1437~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_NEW_REG390\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[9]_NEW_REG390, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1437~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux84~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux84~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux84~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1499~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1499~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12906\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12906, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12908\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12908, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux148~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux148~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux148~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1555~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1555~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1555~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1555~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1555~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1555~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1555~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1555~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1555~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1555~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12910\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12910, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12912\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12912, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux212~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux212~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux212~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1611~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1611~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1611~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1611~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1611~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1611~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1611~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1611~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1611~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12914\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12914, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12916\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12916, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux276~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux276~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux276~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector99~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector99~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_NEW_REG811\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[9]_NEW_REG811, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[9]~81, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1554~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1554~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1554~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1554~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1554~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1554~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1554~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1554~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1554~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1554~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12926\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12926, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12928\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12928, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux211~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux211~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux211~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1498~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1498~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12922\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12922, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12924\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12924, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux147~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux147~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux147~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9051\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1436~2_RESYN9051, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1436~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9053\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1436~2_RESYN9053, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1436~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]_NEW3233\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[10]_NEW3233, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux83~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux83~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux83~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1610~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1610~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1610~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1610~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12930\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12930, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1610~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1610~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1610~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1610~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1610~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12932\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12932, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux275~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux275~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux275~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector98~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector98~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_NEW_REG815\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[10]_NEW_REG815, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[10]~77, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1497~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1497~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12890\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12890, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12892\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12892, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux146~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux146~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux146~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1553~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1553~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1553~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1553~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1553~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1553~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1553~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1553~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1553~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1553~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12894\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12894, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12896\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12896, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux210~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux210~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux210~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[10]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9297\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9297, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9295\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9295, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[10]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux82~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux82~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux82~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1609~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1609~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1609~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1609~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12898\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12898, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1609~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1609~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1609~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1609~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1609~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12900\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12900, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux274~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux274~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux274~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector97~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector97~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_NEW_REG807\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[11]_NEW_REG807, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[11]~84, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[15]_NEW_REG1568\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[15]_NEW_REG1568, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux142~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux142~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux142~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG326\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG326, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG330\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG330, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1431~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1431~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG336\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG336, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG334\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG334, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG328\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[15]_NEW_REG328, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1431~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux78~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux78~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux78~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector93~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_NEW_REG829\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[14]_NEW_REG829, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_NEW_REG342\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[14]_NEW_REG342, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_NEW_REG338\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[14]_NEW_REG338, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1432~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_NEW_REG344\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[14]_NEW_REG344, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_NEW_REG340\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[14]_NEW_REG340, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1432~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux79~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux79~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux79~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector94~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_NEW_REG825\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[13]_NEW_REG825, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1607~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1607~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1607~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1607~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1607~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1607~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1607~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1607~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1607~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12974\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12974, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12976\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12976, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux272~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux272~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux272~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9035\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1433~2_RESYN9035, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9037\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1433~2_RESYN9037, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9039\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1433~2_RESYN9039, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1433~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[13]_NEW3241\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[13]_NEW3241, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux80~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux80~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux80~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1495~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1495~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12966\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12966, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12968\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12968, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux144~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux144~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux144~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1551~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1551~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1551~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1551~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1551~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1551~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1551~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1551~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1551~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1551~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12970\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12970, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12972\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12972, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux208~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux208~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux208~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector95~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_NEW_REG821\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[12]_NEW_REG821, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1496~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1496~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12946\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12946, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12948\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12948, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux145~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux145~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux145~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1552~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1552~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1552~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1552~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1552~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1552~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1552~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1552~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1552~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1552~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12950\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12950, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12952\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12952, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux209~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux209~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux209~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1608~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1608~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1608~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1608~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12954\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12954, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1608~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1608~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1608~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1608~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1608~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12956\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12956, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux273~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux273~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux273~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1434~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9041\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1434~2_RESYN9041, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9043\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1434~2_RESYN9043, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1434~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[12]_NEW3237\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[12]_NEW3237, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux81~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux81~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux81~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector96~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector96~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_NEW_REG823\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[12]_NEW_REG823, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[12]~75, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector95~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_NEW_REG827\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[13]_NEW_REG827, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[13]~72, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector94~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_NEW_REG831\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[14]_NEW_REG831, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[14]~70, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector93~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_NEW_REG835\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[15]_NEW_REG835, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_NEW_REG833\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[15]_NEW_REG833, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[15]~74, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux418~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux418~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1494~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_NEW_REG931\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[16]_NEW_REG931, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_NEW_REG929\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[16]_NEW_REG929, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1494~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux141~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux141~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux141~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_NEW_REG636\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[16]_NEW_REG636, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1430~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1430~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1430~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_NEW_REG638\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[16]_NEW_REG638, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux362~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux362~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_NEW_REG642\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[16]_NEW_REG642, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux362~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux362~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_NEW_REG640\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[16]_NEW_REG640, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1430~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux77~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux77~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux77~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1550~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1550~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13306\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13306, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13308\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13308, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux205~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux205~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux205~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1606~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1606~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Add39~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1606~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Add39~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1606~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1606~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Add39~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1606~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1606~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12988\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12988, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12990\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12990, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux269~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux269~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux269~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector92~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector92~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_NEW_REG851\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[16]_NEW_REG851, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[16]~68, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1605~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1605~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1605~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1605~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1605~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1605~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1605~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1605~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1605~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12978\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12978, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12980\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12980, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux268~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux268~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux268~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux417~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux417~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_NEW_REG887\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[17]_NEW_REG887, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_NEW_REG885\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[17]_NEW_REG885, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1493~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux140~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux140~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux140~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1549~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1549~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1549~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1549~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13294\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13294, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13296\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13296, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux204~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux204~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux204~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1429~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1429~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_NEW_REG692\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[17]_NEW_REG692, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux361~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux361~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_NEW_REG694\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[17]_NEW_REG694, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux361~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux361~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_NEW_REG696\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[17]_NEW_REG696, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1429~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux76~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux76~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux76~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector91~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector91~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_NEW_REG843\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[17]_NEW_REG843, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[17]~71, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_NEW_REG853\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[20]_NEW_REG853, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_NEW_REG837\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[19]_NEW_REG837, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_NEW_REG845\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[18]_NEW_REG845, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1548~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1548~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13298\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13298, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13300\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13300, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux203~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux203~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux203~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12790\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12790, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[23]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1428~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1428~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1428~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12792\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12792, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12796\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12796, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[23]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1428~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[23]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[18]_NEW3243\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[18]_NEW3243, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux75~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux75~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux75~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1604~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1604~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1604~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1604~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1604~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1604~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1604~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12984\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12984, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12986\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12986, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux267~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux267~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux267~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1492~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1492~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1492~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332_RESYN12982\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332_RESYN12982, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux139~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux139~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux139~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector90~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector90~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_NEW_REG847\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[18]_NEW_REG847, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[18]~69, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1547~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1547~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1547~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1427~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1427~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[19]_NEW3239\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[19]_NEW3239, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux74~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux74~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux74~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1603~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1603~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1603~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1603~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1603~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1603~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1603~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1603~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1603~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12962\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12962, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12964\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12964, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux266~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux266~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux266~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1547~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13302\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13302, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13304\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13304, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux202~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux202~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux202~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1491~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1491~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12958\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12958, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12960\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12960, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux138~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux138~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux138~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector89~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector89~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_NEW_REG839\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[19]_NEW_REG839, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[19]~73, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1602~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1602~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1602~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1602~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1602~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1602~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1602~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12994\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12994, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12996\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12996, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux265~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux265~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux265~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1490~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1490~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1490~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338_RESYN12992\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338_RESYN12992, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux137~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux137~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux137~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1546~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1546~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13318\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13318, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13320\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13320, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux201~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux201~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux201~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG660\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG660, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1419~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1426~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG662\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG662, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1426~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1426~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1426~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG656\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG656, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG654\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG654, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG658\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[20]_NEW_REG658, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1426~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux73~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux73~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux73~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector88~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector88~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_NEW_REG855\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[20]_NEW_REG855, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[20]~67, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1545~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1545~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[22][5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1545~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1545~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13312\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13312, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux200~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux200~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux200~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1601~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1601~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1601~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1601~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1489~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1489~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13010\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13010, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13012\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13012, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux136~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux136~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux136~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1425~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1425~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[21]_NEW3247\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[21]_NEW3247, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux72~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux72~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux72~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1601~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1601~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1601~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1601~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1601~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13014\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13014, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13016\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13016, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux264~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux264~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux264~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector87~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector87~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_NEW_REG859\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[21]_NEW_REG859, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[21]~64, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1488~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1488~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1488~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360_RESYN13026\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360_RESYN13026, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux135~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux135~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux135~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1600~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1600~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1600~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1600~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1600~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1600~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1600~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13028\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13028, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13030\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13030, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux263~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux263~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux263~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1544~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1544~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13314\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13314, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13316\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13316, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux199~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux199~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux199~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1424~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1424~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1424~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1424~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[22]_NEW3251\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[22]_NEW3251, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux71~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux71~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux71~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector86~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector86~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_NEW_REG863\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[22]_NEW_REG863, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[22]~62, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1420~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1420~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1420~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_NEW_REG704\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[26]_NEW_REG704, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_NEW_REG700\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[27]_NEW_REG700, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1420~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_NEW_REG706\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[26]_NEW_REG706, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1420~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux67~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux67~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux67~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1484~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1484~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1484~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364_RESYN13032\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364_RESYN13032, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux131~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux131~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux131~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1596~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1596~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1596~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1596~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux265~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1596~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1596~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1596~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13038\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13038, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13040\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13040, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux259~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux259~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux259~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1540~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1540~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1540~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1540~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1540~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1540~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1540~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13034\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13034, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13036\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13036, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux195~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux195~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux195~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector82~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1541~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1541~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1541~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1541~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1541~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1541~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1541~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1541~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux266~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1541~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12572\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12572, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12574\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12574, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux196~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux196~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux196~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1421~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1421~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[25]_NEW3249\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[25]_NEW3249, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux68~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux68~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux68~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1597~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1597~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1597~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1597~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1597~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1597~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1597~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1597~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1597~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13022\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13022, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13024\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13024, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux260~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux260~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux260~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1485~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1485~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13018\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13018, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[25]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13020\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13020, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux132~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux132~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux132~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector83~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_NEW_REG1130\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[24]_NEW_REG1130, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1598~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1598~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1598~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1598~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1598~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux267~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1598~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1598~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13048\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13048, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[24]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13050\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13050, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux261~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux261~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux261~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8695\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1422~4_RESYN8695, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8693\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1422~4_RESYN8693, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8697\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1422~4_RESYN8697, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1422~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[24]_NEW3253\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[24]_NEW3253, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux69~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux69~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux69~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1542~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1542~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1542~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1542~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1542~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1542~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1542~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13044\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13044, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13046\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13046, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux197~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux197~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux197~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1486~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1486~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1486~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[24]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370_RESYN13042\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370_RESYN13042, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux133~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux133~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux133~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector84~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_NEW_REG1134\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[23]_NEW_REG1134, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux523~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux523~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux523~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux523~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1487~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1487~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN12998\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN12998, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN13000\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN13000, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux134~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux134~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux134~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux299~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux299~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux299~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux299~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~17\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux299~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux299~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~25\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux299~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux299~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~16\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux299~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_NEW_REG406\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[23]_NEW_REG406, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux523~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_NEW_REG404\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[23]_NEW_REG404, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_NEW_REG402\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[23]_NEW_REG402, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG320\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[0]_NEW_REG320, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1599~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux262~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux262~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux262~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1543~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1543~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1543~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1543~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13322\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13322, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13324\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13324, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux198~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux198~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux198~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1423~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1423~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1423~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]_NEW3245\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[23]_NEW3245, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux70~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux70~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux70~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector85~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector85~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_NEW_REG1136\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[23]_NEW_REG1136, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[23]~66, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector84~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_NEW_REG1132\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[24]_NEW_REG1132, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[24]~60, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector83~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_NEW_REG1140\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[25]_NEW_REG1140, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_NEW_REG1138\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[25]_NEW_REG1138, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[25]~63, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector82~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_NEW_REG1105\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[26]_NEW_REG1105, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[26]~61, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1595~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1595~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1595~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1595~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1595~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1595~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1595~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1595~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux264~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1595~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13006\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13006, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13008\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13008, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux258~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux258~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux258~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1539~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1539~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1539~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1539~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1539~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1539~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1539~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1539~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1539~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12568\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12568, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12570\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12570, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux194~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux194~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux194~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1483~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1483~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13002\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13002, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[27]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13004\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13004, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux130~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux130~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux130~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1419~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_NEW_REG702\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[27]_NEW_REG702, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1419~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1419~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1419~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_NEW_REG698\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[27]_NEW_REG698, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1419~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux66~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux66~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux66~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector81~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector81~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_NEW_REG1101\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[27]_NEW_REG1101, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[27]~65, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_NEW_REG472\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[30]_NEW_REG472, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1416~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_NEW_REG474\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[30]_NEW_REG474, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_NEW_REG468\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[30]_NEW_REG468, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~3\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_NEW_REG470\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[30]_NEW_REG470, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1416~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux63~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux63~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux63~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[30]_NEW2396\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[30]_NEW2396, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux127~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux127~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux127~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector78~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_NEW_REG1089\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[29]_NEW_REG1089, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1482~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1482~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1482~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376_RESYN13052\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376_RESYN13052, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux129~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux129~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux129~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1594~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1594~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1594~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1594~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux263~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1594~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1594~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1594~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13058\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13058, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13060\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13060, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux257~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux257~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux257~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8689\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1418~4_RESYN8689, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8687\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1418~4_RESYN8687, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8691\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1418~4_RESYN8691, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1418~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[28]_NEW3255\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[28]_NEW3255, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux65~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux65~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux65~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1538~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1538~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1538~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1538~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1538~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1538~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1538~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13054\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13054, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13056\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13056, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux193~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux193~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux193~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector80~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector80~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_NEW_REG1087\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[28]_NEW_REG1087, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_NEW_REG1085\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[28]_NEW_REG1085, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[28]~59, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1593~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1593~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1593~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1593~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1593~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1593~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~10\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1593~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1593~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~11\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux262~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1593~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13074\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13074, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13076\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13076, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux256~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux256~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux256~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1481~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1481~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13070\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13070, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13072\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13072, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux128~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux128~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux128~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1537~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1537~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1537~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1417~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1417~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]_NEW3257\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[29]_NEW3257, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux64~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux64~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux64~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1537~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1537~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1537~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1537~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1537~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1537~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12576\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12576, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12578\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12578, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux192~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux192~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux192~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector79~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector79~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_NEW_REG1091\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[29]_NEW_REG1091, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[29]~57, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector78~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_NEW_REG1071\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[30]_NEW_REG1071, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_NEW_REG1069\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[30]_NEW_REG1069, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[30]~51, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[31]_NEW2382\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[31]_NEW2382, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux126~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux126~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux126~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1415~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_NEW_REG668\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[31]_NEW_REG668, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_NEW_REG666\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[31]_NEW_REG666, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_NEW_REG664\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[31]_NEW_REG664, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1415~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux62~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux62~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux62~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector77~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector77~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_NEW_REG867\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[31]_NEW_REG867, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[31]~58, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[23]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[23]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[0]_NEW1954\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[0]_NEW1954, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux323~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux323~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux323~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~45\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[32]~45, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~48\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[32]~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~49\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[32]~49, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[1]_NEW1948\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[1]_NEW1948, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux322~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux322~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux322~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~54\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[33]~54, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~55\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[33]~55, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[1]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[1]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[1]_NEW2002\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[1]_NEW2002, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux408~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux408~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux408~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[1]_NEW2004\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[1]_NEW2004, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux376~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux376~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux376~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1477~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_NEW_REG460\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[33]_NEW_REG460, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux403~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux403~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_NEW_REG456\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[33]_NEW_REG456, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1477~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_NEW_REG458\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[33]_NEW_REG458, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1477~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux124~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux124~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux124~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_153\, myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_153, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1413~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1413~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1413~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1413~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]_NEW2168\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[33]_NEW2168, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux60~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux60~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux60~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1591~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1591~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1591~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1591~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13078\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13078, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1591~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1591~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1591~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1591~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1591~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13080\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13080, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux252~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux252~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux252~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1535~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1535~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13326\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13326, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13328\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13328, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux188~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[33]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux188~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux188~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector75~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector75~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~52\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[33]~52, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~53\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[33]~53, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~56\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[33]~56, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[39]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[2]_NEW1950\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[2]_NEW1950, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux321~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux321~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux321~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008_RESYN12816\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008_RESYN12816, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux345~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux345~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux345~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[2]_NEW2006\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[2]_NEW2006, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux375~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux375~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux375~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[2]_NEW2010\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[2]_NEW2010, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux407~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux407~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux407~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[39]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1590~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1590~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1590~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1590~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13086\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13086, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1590~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1590~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1590~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1590~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1590~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13088\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13088, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux251~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux251~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux251~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_RTM0716\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[57]~0_RTM0716, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[59]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG714\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG714, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_NEW_REG1113\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[34]_NEW_REG1113, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1412~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1412~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_156\, myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_156, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1412~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~4_RTM01120\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1412~4_RTM01120, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_NEW_REG1118\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[34]_NEW_REG1118, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_NEW_REG1111\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[34]_NEW_REG1111, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG484\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG484, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1412~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_NEW_REG1115\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[34]_NEW_REG1115, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1412~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[34]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[34]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[34]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[34]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux59~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux59~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux59~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1476~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1476~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13082\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13082, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13084\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13084, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[34]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[34]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[34]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[34]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[34]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[34]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux123~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[34]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[34]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[34]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[34]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux123~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux123~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1534~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1534~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13330\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13330, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[34]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13332\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13332, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[34]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[34]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux187~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[34]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[34]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[34]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[34]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[34]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[34]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux187~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux187~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[34]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector74~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector74~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector74~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]_NEW1776\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[34]_NEW1776, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[34]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[3]_NEW2000\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[3]_NEW2000, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux406~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux406~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux406~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[3]_NEW1996\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[3]_NEW1996, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux374~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux374~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux374~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998_RESYN12814\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998_RESYN12814, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux344~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux344~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux344~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1533~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1533~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13334\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13334, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13336\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13336, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[35]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[35]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux186~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[35]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[35]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[35]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[35]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux186~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux186~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[45]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG102\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG102, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1411~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1411~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1411~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[42]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1411~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG110\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG110, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_159\, myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_159, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG108\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG108, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG106\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG106, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1411~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux58~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[35]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[35]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[35]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[35]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux58~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux58~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1589~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1589~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1589~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1589~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1589~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1589~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1589~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1589~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1589~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13066\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13066, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13068\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13068, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[35]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[35]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[35]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[35]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[35]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[35]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux250~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[35]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[35]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux250~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux250~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1475~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1475~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13062\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13062, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13064\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13064, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[35]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[35]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[35]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[35]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux122~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux122~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux122~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector73~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector73~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[3]_NEW1952\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[3]_NEW1952, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux320~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux320~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux320~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector73~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[35]_NEW1774\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[35]_NEW1774, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[35]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[4]_NEW1964\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[4]_NEW1964, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux319~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux319~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux319~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[4]_NEW2020\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[4]_NEW2020, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux405~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux405~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux405~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018_RESYN12818\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018_RESYN12818, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux343~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux343~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux343~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[4]_NEW2016\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[4]_NEW2016, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux373~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux373~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux373~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1474~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1474~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13094\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13094, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13096\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13096, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux121~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[36]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux121~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux121~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1410~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1410~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1410~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1410~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_NEW_REG116\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[36]_NEW_REG116, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_174\, myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_174, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_NEW_REG114\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[36]_NEW_REG114, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_NEW_REG112\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[36]_NEW_REG112, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1410~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[36]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux57~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[36]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[36]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux57~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux57~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1588~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1588~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1588~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1588~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13098\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13098, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1588~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1588~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1588~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1588~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1588~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13100\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13100, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[36]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[36]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux249~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[36]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux249~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux249~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1532~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1532~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13350\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13350, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[36]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13352\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13352, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[36]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[36]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[36]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux185~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[36]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[36]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux185~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux185~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector72~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector72~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector72~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[36]_NEW1782\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[36]_NEW1782, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[36]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[5]_NEW1956\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[5]_NEW1956, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux318~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux318~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux318~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[5]_NEW2038\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[5]_NEW2038, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux404~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux404~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux404~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[5]_NEW2034\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[5]_NEW2034, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux372~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux372~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux372~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036_RESYN12824\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036_RESYN12824, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux342~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux342~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux342~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1531~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1531~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13342\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13342, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13344\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13344, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux184~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux184~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux184~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1473~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1473~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13118\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13118, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[37]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13120\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13120, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux120~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux120~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux120~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1587~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1587~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1587~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1587~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13122\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13122, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1587~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1587~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1587~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1587~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1587~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13124\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13124, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux248~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux248~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux248~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1409~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1409~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1409~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1409~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_NEW_REG128\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[37]_NEW_REG128, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_168\, myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_168, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_NEW_REG126\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[37]_NEW_REG126, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_NEW_REG124\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[37]_NEW_REG124, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1409~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux56~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[37]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux56~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux56~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector71~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector71~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector71~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[37]_NEW1778\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[37]_NEW1778, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[37]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[6]_NEW1960\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[6]_NEW1960, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux317~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux317~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux317~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048_RESYN12828\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048_RESYN12828, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux341~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux341~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux341~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[6]_NEW2050\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[6]_NEW2050, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux403~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux403~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux403~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[6]_NEW2046\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[6]_NEW2046, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux371~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux371~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux371~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1530~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1530~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13346\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13346, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13348\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13348, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[38]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[38]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[38]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[38]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[38]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[38]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux183~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[38]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[38]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[38]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[38]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[38]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[38]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux183~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux183~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[42]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG142\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG142, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[42]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG140\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG140, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_171\, myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_171, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1408~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1408~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1408~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1408~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~2_RTM0146\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1408~2_RTM0146, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG144\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG144, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG138\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG138, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG136\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[38]_NEW_REG136, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1408~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[38]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[38]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux55~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[38]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[38]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux55~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux55~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1586~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1586~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1586~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1586~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13142\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13142, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1586~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1586~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1586~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1586~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1586~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13144\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13144, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[38]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[38]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux247~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[38]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[38]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux247~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux247~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1472~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1472~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13138\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13138, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13140\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13140, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[38]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[38]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[38]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[38]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux119~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux119~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux119~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[38]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector70~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector70~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector70~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]_NEW1780\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[38]_NEW1780, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[7]_NEW1966\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[7]_NEW1966, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux316~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux316~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux316~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[7]_NEW2026\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[7]_NEW2026, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux402~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux402~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux402~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024_RESYN12820\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024_RESYN12820, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux340~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux340~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux340~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[7]_NEW2022\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[7]_NEW2022, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux370~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux370~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux370~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1529~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1529~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13354\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13354, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13356\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13356, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux182~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux182~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux182~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1471~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1471~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13102\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13102, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13104\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13104, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux118~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux118~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux118~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux509~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux509~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux509~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux509~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux509~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_NEW_REG360\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[39]_NEW_REG360, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_NEW_REG356\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[39]_NEW_REG356, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_NEW_REG358\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[39]_NEW_REG358, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1585~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux246~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux246~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux246~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_165\, myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_165, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_NEW_REG120\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[39]_NEW_REG120, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1407~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1407~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1407~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1407~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_NEW_REG122\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[39]_NEW_REG122, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG104\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[35]_NEW_REG104, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_NEW_REG118\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[39]_NEW_REG118, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1407~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux54~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[39]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux54~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux54~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector69~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector69~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector69~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]_NEW1784\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[39]_NEW1784, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[8]_NEW1970\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[8]_NEW1970, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux315~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux315~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux315~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[8]_NEW2062\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[8]_NEW2062, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux401~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux401~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux401~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060_RESYN12832\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060_RESYN12832, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux339~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux339~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux339~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[8]_NEW2058\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[8]_NEW2058, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[8]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux369~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux369~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux369~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_NEW_REG494\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[40]_NEW_REG494, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[34]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG486\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG486, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1394~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1406~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_NEW_REG496\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[40]_NEW_REG496, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1406~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1406~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1406~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~4_RTM0500\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1406~4_RTM0500, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_NEW_REG498\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[40]_NEW_REG498, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1406~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux53~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux53~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux53~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1584~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1584~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1584~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1584~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13166\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13166, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1584~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1584~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1584~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1584~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1584~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13168\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13168, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux245~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux245~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux245~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1470~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1470~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13158\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13158, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[40]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13160\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13160, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux117~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux117~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux117~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[42]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[42]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1528~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1528~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[42]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1528~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[42]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1528~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1528~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1528~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1528~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1528~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1528~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1528~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13162\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13162, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13164\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13164, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux181~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[40]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[40]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux181~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux181~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector68~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector68~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector68~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[40]_NEW1792\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[40]_NEW1792, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[40]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[9]_NEW1958\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[9]_NEW1958, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux314~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux314~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux314~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042_RESYN12826\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042_RESYN12826, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux338~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux338~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux338~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[9]_NEW2040\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[9]_NEW2040, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux368~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux368~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux368~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[9]_NEW2044\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[9]_NEW2044, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux400~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux400~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux400~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_NEW_REG130\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[41]_NEW_REG130, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1405~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1405~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1405~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1405~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_NEW_REG134\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[41]_NEW_REG134, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[9]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[9]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_NEW_REG132\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[41]_NEW_REG132, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1405~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux52~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux52~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux52~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1583~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1583~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1583~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1583~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13134\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13134, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1583~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1583~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1583~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1583~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1583~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13136\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13136, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux244~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux244~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux244~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1469~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1469~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13126\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13126, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13128\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13128, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux116~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux116~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux116~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1527~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1527~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1527~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1527~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1527~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1527~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1527~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1527~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1527~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1527~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13130\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13130, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13132\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13132, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux180~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[41]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[41]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux180~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux180~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector67~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector67~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector67~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[41]_NEW1790\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[41]_NEW1790, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[41]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[10]_NEW1962\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[10]_NEW1962, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux313~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux313~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux313~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054_RESYN12830\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054_RESYN12830, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux337~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux337~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux337~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[10]_NEW2056\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[10]_NEW2056, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux399~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux399~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux399~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[10]_NEW2052\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[10]_NEW2052, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[10]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux367~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux367~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux367~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1582~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1582~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1582~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1582~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13154\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13154, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1582~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1582~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1582~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1582~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1582~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13156\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13156, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux243~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux243~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux243~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1526~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1526~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1526~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1526~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1526~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1526~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1526~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1526~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1526~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1526~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13150\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13150, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13152\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13152, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux179~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux179~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux179~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1468~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1468~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13146\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13146, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13148\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13148, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux115~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux115~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux115~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[10]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1404~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1404~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1404~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1404~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~2_RTM0152\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1404~2_RTM0152, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_NEW_REG150\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[42]_NEW_REG150, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_NEW_REG148\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[42]_NEW_REG148, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1404~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[42]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[42]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux51~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux51~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux51~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector66~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector66~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector66~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[42]_NEW1788\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[42]_NEW1788, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[42]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[11]_NEW1968\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[11]_NEW1968, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux312~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux312~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux312~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[11]_NEW2028\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[11]_NEW2028, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux366~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux366~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux366~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[11]_NEW2032\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[11]_NEW2032, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux398~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux398~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux398~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030_RESYN12822\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030_RESYN12822, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux336~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[11]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[11]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux336~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux336~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1525~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1525~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1525~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1525~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1525~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1525~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1525~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1525~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1525~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1525~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13110\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13110, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13112\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13112, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[43]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[43]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[43]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[43]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux178~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[43]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[43]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[43]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[43]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux178~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux178~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1581~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1581~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1581~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1581~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1581~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1581~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1581~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1581~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1581~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13114\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13114, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13116\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13116, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux242~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[43]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[43]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux242~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux242~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1403~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG488\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG488, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG482\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG482, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1403~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1403~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[11]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1403~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~4_RTM0492\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1403~4_RTM0492, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG490\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[43]_NEW_REG490, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1403~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux50~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[43]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[43]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[43]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[43]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux50~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux50~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1467~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1467~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13106\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13106, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13108\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13108, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[43]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[43]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux114~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux114~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux114~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector65~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector65~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector65~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[43]_NEW1786\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[43]_NEW1786, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[43]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[12]_NEW1980\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[12]_NEW1980, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux311~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux311~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux311~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[12]_NEW2068\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[12]_NEW2068, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux397~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux397~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux397~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]_NEW2064\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[12]_NEW2064, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux365~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux365~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux365~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066_RESYN12834\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066_RESYN12834, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux335~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[12]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux335~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux335~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1466~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1466~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13170\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13170, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13172\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13172, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux113~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux113~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux113~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1580~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1580~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1580~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1580~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1580~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1580~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1580~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1580~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1580~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13178\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13178, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13180\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13180, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux241~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux241~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux241~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_NEW_REG154\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[44]_NEW_REG154, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[12]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_NEW_REG156\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[44]_NEW_REG156, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1402~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1402~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1402~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1402~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_NEW_REG158\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[44]_NEW_REG158, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1402~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux49~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux49~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux49~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1524~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1524~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1524~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1524~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1524~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1524~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1524~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1524~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1524~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1524~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13174\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13174, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13176\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13176, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux177~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[44]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[44]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux177~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux177~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[44]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector64~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector64~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector64~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]_NEW1798\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[44]_NEW1798, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[13]_NEW1972\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[13]_NEW1972, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux310~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux310~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux310~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[13]_NEW2082\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[13]_NEW2082, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux364~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux364~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux364~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084_RESYN12840\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084_RESYN12840, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux334~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux334~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux334~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[13]_NEW2086\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[13]_NEW2086, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux396~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[13]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[13]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux396~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux396~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1465~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1465~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13190\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13190, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13192\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13192, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[45]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[45]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux112~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[45]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[45]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[45]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[45]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[45]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[45]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux112~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux112~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1523~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1523~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1523~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1523~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1523~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1523~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1523~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1523~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1523~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1523~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13194\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13194, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[45]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13196\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13196, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux176~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[45]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[45]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux176~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux176~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~8\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1579~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~7\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1579~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1579~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1579~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~9\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1579~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1579~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1579~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1579~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1579~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13198\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13198, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13200\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13200, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[45]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[45]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[45]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[45]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[45]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[45]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux240~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux240~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux240~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1401~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1401~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1401~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1401~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_NEW_REG164\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[45]_NEW_REG164, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[13]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_NEW_REG162\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[45]_NEW_REG162, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_NEW_REG160\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[45]_NEW_REG160, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1401~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[45]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[45]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[45]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[45]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux48~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[45]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[45]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux48~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux48~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector63~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector63~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector63~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[45]_NEW1794\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[45]_NEW1794, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[45]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[14]_NEW1976\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[14]_NEW1976, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux309~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux309~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux309~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[14]_NEW2094\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[14]_NEW2094, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux363~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux363~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux363~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[14]_NEW2098\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[14]_NEW2098, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux395~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux395~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux395~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096_RESYN12844\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096_RESYN12844, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux333~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux333~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux333~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_NEW_REG680\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[46]_NEW_REG680, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_NEW_REG678\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[46]_NEW_REG678, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_NEW_REG676\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[46]_NEW_REG676, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1464~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[46]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[46]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[46]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[46]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux111~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[46]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[46]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux111~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux111~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[14]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[14]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG240\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG240, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[47]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG242\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG242, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG236\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG236, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG234\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[46]_NEW_REG234, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1400~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[46]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[46]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux47~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[46]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[46]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[46]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[46]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux47~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux47~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector62~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector62~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector62~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[46]_NEW1796\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[46]_NEW1796, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[46]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[15]_NEW2070\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[15]_NEW2070, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux362~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux362~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux362~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072_RESYN12836\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072_RESYN12836, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux332~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux332~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux332~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[15]_NEW2074\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[15]_NEW2074, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux394~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux394~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux394~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_NEW_REG670\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[47]_NEW_REG670, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_NEW_REG672\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[47]_NEW_REG672, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_NEW_REG674\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[47]_NEW_REG674, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1463~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[47]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[47]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[47]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[47]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux110~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[47]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[47]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[47]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[47]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux110~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux110~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_NEW_REG294\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[47]_NEW_REG294, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_NEW_REG292\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[47]_NEW_REG292, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_NEW_REG290\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[47]_NEW_REG290, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1399~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[47]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[47]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux46~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[47]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[47]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[47]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[47]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[47]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[47]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux46~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux46~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector61~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector61~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[15]_NEW1982\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[15]_NEW1982, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux308~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[15]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[15]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux308~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux308~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[15]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector61~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]_NEW1800\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[47]_NEW1800, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[16]_NEW1986\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[16]_NEW1986, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux307~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux307~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux307~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108_RESYN12848\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108_RESYN12848, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux331~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux331~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux331~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[16]_NEW2110\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[16]_NEW2110, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux393~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux393~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux393~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[16]_NEW2106\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[16]_NEW2106, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux361~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[16]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[16]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux361~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux361~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1398~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_NEW_REG648\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[48]_NEW_REG648, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1398~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_NEW_REG644\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[48]_NEW_REG644, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG408\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG408, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_NEW_REG646\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[48]_NEW_REG646, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux334~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux334~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux334~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux334~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux334~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[16]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1398~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~2_RTM0652\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1398~2_RTM0652, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_NEW_REG650\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[48]_NEW_REG650, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1398~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux45~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux45~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux45~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13370\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13370, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13372\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13372, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux173~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux173~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux173~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux390~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux390~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_NEW_REG428\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[48]_NEW_REG428, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_NEW_REG420\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[49]_NEW_REG420, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1462~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_NEW_REG432\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[48]_NEW_REG432, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1462~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_NEW_REG430\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[48]_NEW_REG430, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1462~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux109~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux109~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux109~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1578~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1578~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13214\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13214, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13216\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13216, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux237~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[48]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[48]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux237~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux237~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector60~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector60~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector60~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[48]_NEW1808\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[48]_NEW1808, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[48]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[48], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[17]_NEW1974\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[17]_NEW1974, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux306~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux306~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux306~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[17]_NEW2088\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[17]_NEW2088, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux360~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux360~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux360~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[17]_NEW2092\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[17]_NEW2092, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux392~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux392~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux392~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux333~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux333~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux333~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux333~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13358\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13358, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13360\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13360, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux172~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux172~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux172~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1461~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_NEW_REG426\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[49]_NEW_REG426, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1461~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_NEW_REG424\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[49]_NEW_REG424, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux389~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux389~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_NEW_REG422\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[49]_NEW_REG422, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1461~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux108~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux108~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux108~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1577~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1577~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13202\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13202, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13204\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13204, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux236~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux236~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux236~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux333~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1397~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~3_RTM0418\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1397~3_RTM0418, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG416\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG416, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1397~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1397~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG414\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG414, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG412\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG412, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG410\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[49]_NEW_REG410, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1397~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux44~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[49]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[49]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux44~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux44~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector59~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090_RESYN12842\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090_RESYN12842, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux330~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[17]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux330~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux330~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[17]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector59~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector59~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]_NEW1806\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[49]_NEW1806, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[49], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[18]_NEW1978\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[18]_NEW1978, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux305~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux305~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux305~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|NOS.word[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[18]_NEW2104\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[18]_NEW2104, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux391~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux391~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux391~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102_RESYN12846\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102_RESYN12846, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux329~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux329~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux329~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[18]_NEW2100\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[18]_NEW2100, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux359~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[18]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux359~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux359~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_NEW_REG722\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[50]_NEW_REG722, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1396~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_NEW_REG724\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[50]_NEW_REG724, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[18]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux332~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux332~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux332~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux332~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1396~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1396~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~3_RTM0729\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1396~3_RTM0729, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_NEW_REG727\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[50]_NEW_REG727, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG622\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG622, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1396~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[50]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[50]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[50]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[50]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux43~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[50]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[50]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux43~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux43~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1576~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1576~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13210\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13210, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13212\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13212, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[50]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[50]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[50]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[50]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux235~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[50]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[50]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[50]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[50]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux235~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux235~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13362\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13362, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13364\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13364, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux171~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[50]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[50]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[50]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[50]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux171~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux171~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1460~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[60]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1460~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13206\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13206, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13208\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13208, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux107~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux107~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux107~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector58~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector58~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector58~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[50]_NEW1804\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[50]_NEW1804, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[50]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[50], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[47]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[19]_NEW1984\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[19]_NEW1984, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux304~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux304~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux304~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[19]_NEW2080\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[19]_NEW2080, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux390~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux390~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux390~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078_RESYN12838\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078_RESYN12838, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux328~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux328~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux328~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[19]_NEW2076\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[19]_NEW2076, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux358~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux358~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux358~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1459~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1459~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13182\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13182, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13184\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13184, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux106~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[51]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[51]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux106~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux106~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1575~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1575~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13186\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13186, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13188\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13188, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux234~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[51]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[51]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[51]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[51]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux234~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux234~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1395~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG712\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG712, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG710\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG710, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG708\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG708, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[19]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[19]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux331~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux331~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux331~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux331~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1395~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1395~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~3_RTM0720\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1395~3_RTM0720, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG718\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[51]_NEW_REG718, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1395~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux42~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[51]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[51]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[51]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[51]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux42~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux42~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13368\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13368, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[51]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[51]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux170~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux170~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux170~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector57~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector57~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector57~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[51]_NEW1802\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[51]_NEW1802, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[51]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[51], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[20]_NEW1992\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[20]_NEW1992, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux303~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux303~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux303~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[20]_NEW2112\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[20]_NEW2112, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux357~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux357~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux357~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114_RESYN12850\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114_RESYN12850, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux327~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux327~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux327~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[20]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[20]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[20]_NEW2116\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[20]_NEW2116, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux389~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[20]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux389~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux389~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1458~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1458~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13218\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13218, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13220\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13220, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[52]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[52]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[52]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[52]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[52]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[52]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux105~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[52]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[52]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux105~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux105~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG618\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG618, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG626\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG626, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG616\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG616, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[20]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux330~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux330~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux330~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux330~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1394~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1394~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1394~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG628\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG628, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG624\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG624, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG620\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[52]_NEW_REG620, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1394~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[52]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[52]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux41~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[52]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[52]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[52]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[52]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux41~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux41~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1574~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1574~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13222\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13222, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13224\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13224, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[52]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[52]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux233~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux233~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux233~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13398\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13398, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13400\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13400, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux169~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux169~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux169~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector56~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector56~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector56~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[52]_NEW1812\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[52]_NEW1812, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[52]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[52], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[21]_NEW1988\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[21]_NEW1988, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux302~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux302~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux302~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[21]_NEW2132\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[21]_NEW2132, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux356~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux356~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux356~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[21]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134_RESYN12854\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134_RESYN12854, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux326~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux326~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux326~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[21]_NEW2136\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[21]_NEW2136, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux388~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux388~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux388~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[21]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[21]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~1_RTM0258\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1393~1_RTM0258, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_NEW_REG256\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[53]_NEW_REG256, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux329~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux329~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux329~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux329~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1393~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_NEW_REG254\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[53]_NEW_REG254, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG226\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG226, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_NEW_REG252\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[53]_NEW_REG252, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1393~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[53]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[53]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[53]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[53]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[53]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[53]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux40~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux40~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux40~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1457~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1457~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13246\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13246, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13248\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13248, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[53]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[53]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[53]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[53]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[53]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[53]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux104~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[53]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[53]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux104~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux104~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1573~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1573~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13250\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13250, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13252\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13252, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux232~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[53]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[53]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[53]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[53]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux232~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux232~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13380\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13380, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux168~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[53]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[53]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[53]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[53]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux168~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux168~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector55~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector55~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector55~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[53]_NEW1810\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[53]_NEW1810, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[53]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[53], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[22]_NEW1990\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[22]_NEW1990, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux301~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux301~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux301~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144_RESYN12856\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144_RESYN12856, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux325~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux325~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux325~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[22]_NEW2142\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[22]_NEW2142, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux355~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux355~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux355~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[22]_NEW2146\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[22]_NEW2146, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux387~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[22]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux387~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux387~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux328~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux328~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux328~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux328~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13390\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13390, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13392\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13392, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[54]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[54]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[54]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[54]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux167~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[54]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[54]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[54]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[54]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux167~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux167~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1456~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1456~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13386\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13386, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[54]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13388\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13388, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux103~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[54]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[54]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux103~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux103~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[22]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1392~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_NEW_REG272\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[54]_NEW_REG272, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_NEW_REG268\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[54]_NEW_REG268, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1392~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_NEW_REG270\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[54]_NEW_REG270, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1392~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[54]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[54]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux39~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[54]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[54]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[54]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[54]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux39~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux39~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1572~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1572~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13394\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13394, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13396\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13396, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux231~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux231~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux231~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector54~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector54~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector54~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]_NEW1816\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[54]_NEW1816, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[54], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[63]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9283\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9283, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9285\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9285, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[7]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[6]_NEW2258\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[6]_NEW2258, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux287~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux287~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux287~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.OPCODE[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[30]_NEW2158\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[30]_NEW2158, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux379~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[30]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux379~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux379~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1384~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1384~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_NEW_REG288\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[62]_NEW_REG288, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_NEW_REG282\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[62]_NEW_REG282, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1384~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_NEW_REG286\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[62]_NEW_REG286, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[30]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1384~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_NEW_REG284\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[62]_NEW_REG284, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1384~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[62]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[62]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux31~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[62]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[62]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux31~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux31~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]_NEW2623\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[62]_NEW2623, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[62]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[62]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[62]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[62]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux95~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[62]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[62]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[62]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[62]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux95~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux95~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector46~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector46~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~116\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[62]~116, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~112\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[62]~112, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[63]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[60]~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[59]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[49]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxTOS.word[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[25]_NEW2128\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[25]_NEW2128, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux352~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux352~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux352~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~37\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[57]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[60]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[24]_NEW2148\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[24]_NEW2148, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux353~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux353~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux353~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~23\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[56]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]_NEW1994\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[23]_NEW1994, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.PC[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].PC[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].PC[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].PC[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].PC[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux300~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].PC[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].PC[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].PC[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].PC[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux300~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux300~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.PC[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[23]_NEW2126\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[23]_NEW2126, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux386~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux386~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux386~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124_RESYN12852\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124_RESYN12852, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].SP[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].SP[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].SP[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].SP[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux324~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].SP[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].SP[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].SP[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].SP[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux324~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux324~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.SP[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[23]_NEW2122\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[23]_NEW2122, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux354~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux354~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux354~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1455~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1455~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13234\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13234, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13236\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13236, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[55]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[55]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux102~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[55]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[55]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[55]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[55]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[55]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[55]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux102~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux102~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux327~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux327~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux327~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux327~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13408\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13408, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[55]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[55]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux166~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[55]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[55]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[55]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[55]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux166~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux166~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1571~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1571~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13410\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13410, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13412\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13412, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[55]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[55]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux230~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[55]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[55]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux230~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux230~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1391~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_NEW_REG246\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[55]_NEW_REG246, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_NEW_REG244\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[55]_NEW_REG244, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[23]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[23]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~1_RTM0250\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1391~1_RTM0250, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_NEW_REG248\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[55]_NEW_REG248, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1391~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux38~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[55]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[55]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[55]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[55]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[55]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[55]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux38~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux38~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector53~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector53~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector53~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[55]_NEW1814\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[55]_NEW1814, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[55]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[55], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~24\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[56]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux253~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[0]_NEW2246\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[0]_NEW2246, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux293~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux293~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux293~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[63]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[59]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[24]_NEW2150\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[24]_NEW2150, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux385~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[24]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux385~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux385~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[0]_NEW2249\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[0]_NEW2249, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux299~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux299~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux299~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1570~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1570~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1570~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1570~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1570~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1570~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1570~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13422\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13422, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13424\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13424, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux229~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux229~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux229~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux326~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux326~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux326~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux326~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13418\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13418, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13420\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13420, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux165~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux165~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux165~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1390~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_NEW_REG742\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[56]_NEW_REG742, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_NEW_REG740\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[56]_NEW_REG740, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[24]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1390~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1390~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~3_RTM0747\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1390~3_RTM0747, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_NEW_REG745\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[56]_NEW_REG745, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1390~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux37~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux37~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux37~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1454~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1454~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13414\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13414, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13416\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13416, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux101~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[56]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[56]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux101~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux101~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector52~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector52~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~25\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[56]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~26\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[56]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[56], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~38\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[57]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux252~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[1]_NEW2228\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[1]_NEW2228, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux292~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux292~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux292~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[25]_NEW2130\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[25]_NEW2130, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux384~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[25]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux384~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux384~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1569~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1569~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1569~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1569~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1569~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1569~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1569~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13242\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13242, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13244\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13244, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux228~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux228~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux228~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_NEW_REG630\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[57]_NEW_REG630, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[25]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux325~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux325~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux325~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux325~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1389~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1389~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1389~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_NEW_REG634\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[57]_NEW_REG634, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_NEW_REG632\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[57]_NEW_REG632, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1389~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux36~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux36~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux36~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13374\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13374, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13376\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13376, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux164~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux164~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux164~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1453~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1453~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13238\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13238, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[57]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13240\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13240, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux100~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[57]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[57]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux100~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux100~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector51~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[1]_NEW2231\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[1]_NEW2231, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux298~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux298~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux298~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector51~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~39\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[57]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~40\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[57]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[57], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[2]_NEW2237\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[2]_NEW2237, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux297~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux297~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux297~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux251~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[2]_NEW2234\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[2]_NEW2234, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux291~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux291~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux291~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.OPCODE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[26]_NEW2140\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[26]_NEW2140, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux383~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux383~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux383~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1568~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1568~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1568~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1568~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1568~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1568~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1568~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13258\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13258, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13260\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13260, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux227~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux227~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux227~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux324~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux324~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux324~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux324~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13384\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13384, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux163~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux163~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux163~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1388~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_NEW_REG262\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[58]_NEW_REG262, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~1_RTM0266\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1388~1_RTM0266, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_NEW_REG264\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[58]_NEW_REG264, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_NEW_REG260\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[58]_NEW_REG260, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1388~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux35~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux35~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux35~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1452~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1452~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13254\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13254, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13256\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13256, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux99~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[58]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[58]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux99~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux99~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector50~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector50~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~34\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[58]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[26]_NEW2138\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[26]_NEW2138, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux351~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[26]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux351~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux351~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[26]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~33\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[58]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~35\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[58]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~36\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[58]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[58], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~42\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[59]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[27]_NEW2118\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[27]_NEW2118, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux350~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux350~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux350~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~41\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[59]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux250~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[3]_NEW2240\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[3]_NEW2240, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux290~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux290~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux290~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[27]_NEW2120\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[27]_NEW2120, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux382~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[27]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux382~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux382~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux323~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux323~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux323~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux323~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13402\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13402, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13404\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13404, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux162~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux162~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux162~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1451~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1451~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13226\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13226, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[59]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13228\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13228, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux98~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux98~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux98~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1567~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1567~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1567~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1567~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1567~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1567~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1567~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13230\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13230, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13232\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13232, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux226~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux226~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux226~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_NEW_REG731\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[59]_NEW_REG731, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1387~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_NEW_REG733\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[59]_NEW_REG733, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[27]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1387~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1387~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~3_RTM0738\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1387~3_RTM0738, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_NEW_REG736\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[59]_NEW_REG736, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1387~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux34~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[59]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[59]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux34~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux34~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector49~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[3]_NEW2243\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[3]_NEW2243, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux296~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux296~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux296~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector49~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~43\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[59]~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~44\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[59]~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[59], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~20\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[60]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxNOS.word[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[28]_NEW2162\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[28]_NEW2162, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux381~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux381~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux381~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux249~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[4]_NEW2261\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[4]_NEW2261, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux289~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux289~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux289~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux322~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux322~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux322~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux322~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13442\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13442, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13444\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13444, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux161~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux161~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux161~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~1_RTM0232\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1386~1_RTM0232, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG230\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG230, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1386~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG228\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG228, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG222\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[60]_NEW_REG222, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1386~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux33~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux33~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux33~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1566~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1566~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1566~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1566~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1566~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1566~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1566~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13446\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13446, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[60]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13448\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13448, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux225~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux225~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux225~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1450~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1450~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13438\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13438, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[60]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13440\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13440, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux97~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[60]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[60]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux97~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux97~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector48~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[4]_NEW2264\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[4]_NEW2264, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux295~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux295~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux295~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector48~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[28]_NEW2160\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[28]_NEW2160, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux349~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[28]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux349~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux349~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[28]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~19\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[60]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~21\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[60]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~22\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[60]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[60], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~14\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[61]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[29]_NEW2152\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[29]_NEW2152, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux348~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux348~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux348~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~13\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[61]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[5]_NEW2252\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[5]_NEW2252, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux288~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux288~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux288~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[29]_NEW2154\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[29]_NEW2154, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux380~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux380~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux380~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[5]_NEW2255\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[5]_NEW2255, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux294~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux294~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux294~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1449~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1449~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13426\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13426, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13428\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13428, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux96~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux96~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux96~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux321~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux321~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux321~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux321~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13430\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13430, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[61]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13432\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13432, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA3[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux160~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA3[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux160~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux160~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA3[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~5\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1565~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~6\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1565~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1565~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~3\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1565~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1565~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1565~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~4\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1565~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13434\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13434, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13436\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13436, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA4[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux224~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA4[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux224~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux224~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA4[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[29]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[29]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~1_RTM0280\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1385~1_RTM0280, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_NEW_REG278\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[61]_NEW_REG278, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1385~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_NEW_REG276\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[61]_NEW_REG276, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_NEW_REG274\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[61]_NEW_REG274, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1385~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[61]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[61]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux32~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux32~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux32~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[61]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[61], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector47~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector47~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~15\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[61]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~16\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[61]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[58]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~7\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[62]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~8\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[62]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[62], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[31]_NEW2164\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[31]_NEW2164, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_TOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux346~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux346~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux346~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_TOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Mux182~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]_NEW2267\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[7]_NEW2267, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.OPCODE[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux286~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux286~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux286~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.OPCODE[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[31]_NEW2166\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[31]_NEW2166, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.STACK_NOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux378~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux378~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux378~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.STACK_NOS[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_NEW_REG368\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[63]_NEW_REG368, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~0\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1383~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~1\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1383~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_NEW_REG372\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[63]_NEW_REG372, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_NEW_REG366\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[63]_NEW_REG366, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]\, myVirtualToplevel|\ZPUEVO:ZPU0|mxMemVal.word[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_NEW_REG370\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA[63]_NEW_REG370, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2\, myVirtualToplevel|\ZPUEVO:ZPU0|Selector1383~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux30~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[63]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[63]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[63]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[63]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[63]~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[63]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux30~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux30~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[63]_NEW2621\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[63]_NEW2621, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|debugRec.DATA2[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[63]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[63]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[63]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[63]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[3].DATA2[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[63]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[63]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux94~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[63]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[63]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[63]~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[63]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBG_FIFO[5].DATA2[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux94~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Mux94~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|DBGREC.DATA2[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector45~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector45~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~108\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[63]~108, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~104\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[63]~104, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~17\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[63]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~18\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[63]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[63], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan3~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|LessThan3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_DATA_IN[56]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector121~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector121~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector121~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_WRITE_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector120~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector120~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector120~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_WRITE_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[1]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector119~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector119~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector119~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_WRITE_DATA[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector118~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector118~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector118~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector118~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_WRITE_DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[2]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[3]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector117~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector117~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_WRITE_DATA[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~DUPLICATE\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector116~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector116~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~2\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector116~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~3\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector116~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_WRITE_DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[4]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[5]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector115~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector115~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_WRITE_DATA[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~1\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|Selector114~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_WRITE_DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[6]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[7]~feeder\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[7]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[6]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[5]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[4]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[3]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[2]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[1]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TX_BUFFER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~0\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TXD~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD\, myVirtualToplevel|\ZPUEVO:ZPU0|\DEBUG:DEBUGUART|TXD, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[7]~feeder\, myVirtualToplevel|UART0|TX_BUFFER[7]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[0]~4\, myVirtualToplevel|UART0|TX_DATA[0]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~33\, myVirtualToplevel|UART0|TX_FIFO~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~31\, myVirtualToplevel|UART0|TX_FIFO~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal6~4\, myVirtualToplevel|UART0|Equal6~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|Equal6~3\, myVirtualToplevel|UART0|Equal6~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~32\, myVirtualToplevel|UART0|TX_FIFO~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~34\, myVirtualToplevel|UART0|TX_FIFO~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~25\, myVirtualToplevel|UART0|TX_FIFO~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[24]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~35\, myVirtualToplevel|UART0|TX_FIFO~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~17\, myVirtualToplevel|UART0|TX_FIFO~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[15]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[11]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[13]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[14]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[12]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~26\, myVirtualToplevel|UART0|TX_FIFO~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[16]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[5]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[6]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[8]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[7]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~28\, myVirtualToplevel|UART0|TX_FIFO~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[3]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[2]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[4]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[1]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[0]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~27\, myVirtualToplevel|UART0|TX_FIFO~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[10]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[9]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~29\, myVirtualToplevel|UART0|TX_FIFO~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~30\, myVirtualToplevel|UART0|TX_FIFO~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[0]~1\, myVirtualToplevel|UART0|TX_DATA[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[0]~2\, myVirtualToplevel|UART0|TX_DATA[0]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0\, myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA~18\, myVirtualToplevel|UART0|TX_DATA~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[7]~19\, myVirtualToplevel|UART0|TX_DATA[7]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[7]\, myVirtualToplevel|UART0|TX_DATA[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[7]\, myVirtualToplevel|UART0|TX_BUFFER[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[6]~feeder\, myVirtualToplevel|UART0|TX_BUFFER[6]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[23]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~24\, myVirtualToplevel|UART0|TX_FIFO~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA~16\, myVirtualToplevel|UART0|TX_DATA~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[6]~17\, myVirtualToplevel|UART0|TX_DATA[6]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[6]\, myVirtualToplevel|UART0|TX_DATA[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[6]\, myVirtualToplevel|UART0|TX_BUFFER[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[5]~feeder\, myVirtualToplevel|UART0|TX_BUFFER[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[22]~feeder\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[22]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~23\, myVirtualToplevel|UART0|TX_FIFO~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA~14\, myVirtualToplevel|UART0|TX_DATA~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[5]~15\, myVirtualToplevel|UART0|TX_DATA[5]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[5]\, myVirtualToplevel|UART0|TX_DATA[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[5]\, myVirtualToplevel|UART0|TX_BUFFER[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[4]~feeder\, myVirtualToplevel|UART0|TX_BUFFER[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~22\, myVirtualToplevel|UART0|TX_FIFO~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[21]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA~12\, myVirtualToplevel|UART0|TX_DATA~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[4]~13\, myVirtualToplevel|UART0|TX_DATA[4]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[4]\, myVirtualToplevel|UART0|TX_DATA[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[4]\, myVirtualToplevel|UART0|TX_BUFFER[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[3]~feeder\, myVirtualToplevel|UART0|TX_BUFFER[3]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~21\, myVirtualToplevel|UART0|TX_FIFO~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[20]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA~10\, myVirtualToplevel|UART0|TX_DATA~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[3]~11\, myVirtualToplevel|UART0|TX_DATA[3]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[3]\, myVirtualToplevel|UART0|TX_DATA[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[3]\, myVirtualToplevel|UART0|TX_BUFFER[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[2]~feeder\, myVirtualToplevel|UART0|TX_BUFFER[2]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[19]~feeder\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[19]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~20\, myVirtualToplevel|UART0|TX_FIFO~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA~8\, myVirtualToplevel|UART0|TX_DATA~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[2]~9\, myVirtualToplevel|UART0|TX_DATA[2]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[2]\, myVirtualToplevel|UART0|TX_DATA[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[2]\, myVirtualToplevel|UART0|TX_BUFFER[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[1]~feeder\, myVirtualToplevel|UART0|TX_BUFFER[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~19\, myVirtualToplevel|UART0|TX_FIFO~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[18]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA~6\, myVirtualToplevel|UART0|TX_DATA~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[1]~7\, myVirtualToplevel|UART0|TX_DATA[1]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[1]\, myVirtualToplevel|UART0|TX_DATA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[1]\, myVirtualToplevel|UART0|TX_BUFFER[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[0]~feeder\, myVirtualToplevel|UART0|TX_BUFFER[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[17]\, myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_FIFO~18\, myVirtualToplevel|UART0|TX_FIFO~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA~3\, myVirtualToplevel|UART0|TX_DATA~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[0]~5\, myVirtualToplevel|UART0|TX_DATA[0]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_DATA[0]\, myVirtualToplevel|UART0|TX_DATA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TX_BUFFER[0]\, myVirtualToplevel|UART0|TX_BUFFER[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TXD~0\, myVirtualToplevel|UART0|TXD~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|UART0|TXD\, myVirtualToplevel|UART0|TXD, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~48\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~48, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|process_0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~8\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_WRITE[7]~0\, myVirtualToplevel|SD_DATA_WRITE[7]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_WRITE[4]\, myVirtualToplevel|SD_DATA_WRITE[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[43]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[43], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~14\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~14, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector120~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector120~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[37]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[37]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[36]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[36]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[35]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[35]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[34]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[34]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[33]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[33]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[32]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[32]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[31]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[31]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[30]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[30]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[29]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[29]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[28]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[28]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[27]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[27]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[26]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[26]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[25]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[25]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][16]~DUPLICATE\, myVirtualToplevel|SD_ADDR[0][16]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[23]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[23]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[22]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[22]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][13]~DUPLICATE\, myVirtualToplevel|SD_ADDR[0][13]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[21]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[21]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][12]~DUPLICATE\, myVirtualToplevel|SD_ADDR[0][12]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[20]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[20]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[19]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[19]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[18]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[18]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[17]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[17]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[14]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[14]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][4]\, myVirtualToplevel|SD_ADDR[0][4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[12]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[12]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_ADDR[0][2]~DUPLICATE\, myVirtualToplevel|SD_ADDR[0][2]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[10]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[10]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[8]~feeder\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[8]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector157~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector157~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector157~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[1]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[2]~43\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[2]~43, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[2]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~41\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~41, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~42\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~42, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector154~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector154~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[4]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~39\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~39, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~40\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~40, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~37\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~37, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~38\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~38, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[7]~36\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[7]~36, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[7]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[8]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~34\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~34, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~35\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~35, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[10]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~32\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~32, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~33\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~33, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[12]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[12], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~30\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~30, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~31\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~31, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[13], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[14]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[14], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~28\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~28, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~29\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~29, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[15], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~26\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~26, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~27\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~27, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[16], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[17]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[17], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[18]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[18], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[19]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[19], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[20]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[20], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[21]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[21], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[22]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[22], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[23]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[23], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[24], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[25]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[25], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[26]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[26], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[27]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[27], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[28]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[28], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[29]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[29], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[30]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[30], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[31]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[31], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[32]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[32], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[33]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[33], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[34]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[34], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[35]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[35], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[36]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[36], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[37]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[37], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector120~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~3\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector120~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[38]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[38], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[39], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_WRITE[0]\, myVirtualToplevel|SD_DATA_WRITE[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal8~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Equal8~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~20\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~20, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~21\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~21, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~16\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~22\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~22, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[40], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_WRITE[1]\, myVirtualToplevel|SD_DATA_WRITE[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~17\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~18\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[41], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_WRITE[2]\, myVirtualToplevel|SD_DATA_WRITE[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~13\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~15\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[42], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~1\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector115~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector115~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector115~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~3\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector115~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector115~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_WRITE[3]\, myVirtualToplevel|SD_DATA_WRITE[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v~12\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[43]~DUPLICATE\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[43]~DUPLICATE, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~44\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~44, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~11\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[44], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_WRITE[5]\, myVirtualToplevel|SD_DATA_WRITE[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~9\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~10\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[45], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_WRITE[6]\, myVirtualToplevel|SD_DATA_WRITE[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~6\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~7\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[46], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SD_DATA_WRITE[7]\, myVirtualToplevel|SD_DATA_WRITE[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~3\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~4\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|tx_v[47], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector172~0\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector172~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|mosi_o, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~2\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|Selector110~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|cs_bo\, myVirtualToplevel|\SDCARD0:SDCARDS:0:SDCARD|cs_bo, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal3~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|process_0~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal1~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuCol[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~5\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[2]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuCol[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~6\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[2]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[3]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuCol[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~7\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[3]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[4]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuCol[4]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[4]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuCol[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~8\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[4]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[4], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[5]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuCol[5]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[5]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuCol[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~9\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[5]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[5], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[6]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuCol[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~10\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[6]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[6], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[7]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuCol[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~11\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[7]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[7], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~12\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[8]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[8], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~13\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~13, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[9]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[9], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~15\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~15, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|process_0~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~16\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~16, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux28~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux28~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~17\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~17, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[10]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[10], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~18\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~18, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[11]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[11], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[2]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[2], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux92~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux92~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[0]~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~3\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux91~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Mux91~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[1]~feeder\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[1]~feeder, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[1]\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[1], QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCmd~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~1\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCmd~1, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~9\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|process_0~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~8\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|process_0~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~2\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCmd~2, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~3\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCmd~3, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~4\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCmd~4, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_WE_n\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_WE_n, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~5\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCmd~5, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~6\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCmd~6, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~7\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCmd~7, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~8\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCmd~8, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal2~0\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|Equal2~0, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~9\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCmd~9, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~10\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCmd~10, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_RAS_n\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_RAS_n, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~11\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCmd~11, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~12\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|sdCmd~12, QMV_zpu, 1 +instance = comp, \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_CAS_n\, myVirtualToplevel|\ZPUSDRAMEVO:ZPUSDRAM|SDRAM_CAS_n, QMV_zpu, 1 diff --git a/zpu/cpu/zpu_core_evo.vhd b/zpu/cpu/zpu_core_evo.vhd new file mode 100755 index 0000000..d65473b --- /dev/null +++ b/zpu/cpu/zpu_core_evo.vhd @@ -0,0 +1,3567 @@ +-- ZPU Evolution +-- +-- Copyright 2004-2008 (ZPU Design, Small, Medium) oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- Copyright 2008 (zpuino) alvieboy - Álvaro Lopes - alvieboy@alvie.com +-- Copyright 2013 (zpuflex) Alastair M. Robinson +-- Copyright 2018-2019 (ZPU Evo) Philip Smart +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. +-- +-- Evo History: +-- 181230 v0.1 Initial version created by merging items of the Small, Medium and Flex versions. +-- 190328 v0.5 Working with Instruction, Emulation or No Cache with or without seperate instruction +-- bus. Runs numerous tests and output same as the Medium CPU. One small issue is running +-- without an instruction bus and instruction/emulation cache enabled, the DMIPS value is lower +-- than just with instruction bus or emulation bus, seems some clash which reuults in waits states +-- slowing the CPU down. +-- 191021 v1.0 First release. All variations tested but more work needed on the SDRAM controller to +-- make use of burst mode in order to populate the L2 cache in fewer cycles. +-- Additional instructions need to be added back in after test and verification, albeit some +-- which are specific to the Sharp Emulator should be skipped. +-- Additional effort needs spending on the Wishbone Error signal to retry the bus transaction, +-- currently it just aborts it which is not ideal. +-- 191126 v1.1 Bug fixes. When switching off WishBone the CPU wouldnt run. +-- 191215 v1.2 Bug fixes. Removed L2 Cache megacore and replaced with inferred equivalent, fixed hardware +-- byte/h-word write which was always defaulting to read-update-write, fixed L2 timing with +-- external SDRAM, minor tweaks and currently looking at better constraints. +-- 191220 v1.21 Changes to Mult, shifting it from a combination assignment to a clocked assignment to improve +-- slack. Small changes made for slack in setup and hold. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_pkg.all; + +-------------------------------------------------------------------------------------------------------------------------------------------- +-- ZPU Evo Signal Description. +-------------------------------------------------------------------------------------------------------------------------------------------- +-- +-- Main Memory/IO Bus. +-- ------------------- +-- This bus is used to access all external memory and IO, it can also, via configuration, be used to read instructions from attached memory. +-- +-- MEM_WRITE_ENABLE - set to '1' for a single cycle to send off a write request. +-- MEM_DATA_OUT is valid only while MEM_WRITE_ENABLE='1'. +-- MEM_WRITE_BYTE - set to '1' when performing a byte write with data in bits 7-0 of MEM_DATA_OUT +-- MEM_WRITE_HWORD - set to '1' when performing a half word write with data in bits 15-0 of MEM_DATA_OUT +-- MEM_READ_ENABLE - set to '1' for a single cycle to send off a read request. Data is expected on MEM_DATA_IN on next clock rising edge +-- unless MEM_BUSY is asserted in which case the data is read on the next clock rising edge after MEM_BUSY is +-- de-asserted. +-- +-- MEM_BUSY - This signal is used to prolong a read or write cycle, whilst asserted, any read or write cycle is paused as is the +-- CPU with signals remaining in same state just prior to MEM_BUSY assetion. +-- Set to '0' when MEM_READ is valid after a read request. +-- If set to '1'(busy), the current cycle is held until released. For MEM_READ_ENABLE = '1' this means data will be +-- latched on clock rising edge following deassertion of MEM_BUSY. For MEM_WRITE_ENABLE, the write transaction is held +-- with MEM_WRITE_ENABLE asserted until the cycle following the deassertion of MEM_BUSY. +-- MEM_ADDR - address for read/write request +-- MEM_DATA_IN - read data. Valid only on the cycle after mem_busy='0' after +-- MEM_READ_ENABLE='1' for a single cycle. +-- MEM_DATA_OUT - data to write +-- +-- Wishbone Bus B4 Specification +-- ----------------------------- +-- This bus is the industry standard for FPGA IP designs and the one primarily used in OpenCores. In this implementation it is +-- 32bit wide using a Master/Multi-Slave configuration with the ZPU acting as Master. It is a compile time configurable extension as +-- some uses of the ZPU Evo wont need it and thus saves fabric area. The description below is taken from the OpenCores Wishbone B4 +-- specification. +-- +-- WB_CLK_I - The clock input [WB_CLK_I] coordinates all activities for the internal logic within the WISHBONE interconnect. +-- - All WISHBONE output signals are registered at the rising edge of [WB_CLK_I]. All WISHBONE input signals are +-- - stable before the rising edge of [WB_CLK_I]. +-- WB_RST_I - The reset input [WB_RST_I] forces the WISHBONE interface to restart. In this design, this signal is tied to the +-- - ZPU reset via an OR mechanism, forcing the ZPU to reset if activated. +-- WB_ACK_I - The acknowledge input [WB_ACK_I], when asserted, indicates the normal termination of a bus cycle. +-- WB_DAT_I - The data input array [WB_DAT_I] is used to pass binary data. The array boundaries are determined by the port size, +-- - with a port size of 32-bits in this design. +-- WB_DAT_O - The data output array [DAT_O()] is used to pass binary data. The array boundaries are determined by the port size, +-- - with a port size of 32-bits in this design. +-- WB_ADR_O - The address output array [WB_ADR_O] is used to pass a binary address. The higher array boundary is specific to the +-- - address width of the core, and the lower array boundary is determined by the data port size and granularity. +-- - This design is 32bit so WB_ADR[1:0] specify the byte level granularity. +-- WB_CYC_O - The cycle output [WB_CYC_O], when asserted, indicates that a valid bus cycle is in progress. The signal is asserted +-- - for the duration of all bus cycles. +-- WB_STB_O - The strobe output [WB_STB_O] indicates a valid data transfer cycle. It is used to qualify various other signals on +-- - the interface such as [WB_SEL_O]. The SLAVE asserts either the [WB_ACK_I], [WB_ERR_I] or [WB_RTY_I] signals in +-- - response to every assertion of the [WB_STB_O] signal. +-- WB_CTI_O - The Cycle Type Idenfier [WB_CTI_O] Address Tag provides additional information about the current cycle. The MASTER +-- - sends this information to the SLAVE. The SLAVE can use this information to prepare the response for the next cycle. +-- WB_WE_O - The write enable output [WB_WE_O] indicates whether the current local bus cycle is a READ or WRITE cycle. The +-- - signal is negated during READ cycles, and is asserted during WRITE cycles. +-- WB_SEL_O - The select output array [WB_SEL_O] indicates where valid data is expected on the [WB_DAT_I] signal array during +-- - READ cycles, and where it is placed on the [WB_DAT_O] signal array during WRITE cycles. The array boundaries are +-- - determined by the granularity of a port which is 32bit in this design leading to a WB_SEL_O width of 4 bits, 1 +-- - bit to represent each byte. ie. WB_SEL_O[3] = MSB, WB_SEL_O[0] = LSB. +-- WB_HALT_I - +-- WB_ERR_I - The error input [WB_ERR_I] indicates an abnormal cycle termination. The source of the error, and the response +-- - generated by the MASTER is defined by the IP core supplier, in this case the intention (NYI) is to retry +-- - the transaction. +-- WB_INTA_I - A non standard signal to allow a wishbone device to interrupt the ZPU when set to logic '1'. The interrupt is +-- - registered on the next rising edge. +-- +-- +-- Instruction Memory Bus +-- ---------------------- +-- This bus is used for dedicated faster response read only memory containing the code to be run. Using this bus results in faster +-- CPU performance. If this bus is not used/disabled, all instructions will be fetched via the main bus (System or Wishbone bus). +-- +-- MEM_BUSY_INSN - Memory is busy ('1') so data invalid. +-- MEM_DATA_IN_INSN - Instruction data in. +-- MEM_ADDR_INSN - Instruction address bus. +-- MEM_READ_ENABLE_INSN - Instruction read enable signal (active high). +-- +-- INT_REQ - Set to '1' by external logic until interrupts are acknowledged by CPU. +-- INT_ACK - Set to '1' for 1 clock cycle when the interrupt is acknowledged and processing commences. +-- INT_DONE - Set to '1' for 1 clock cycle when the interrupt processing is complete +-- BREAK - Set to '1' when CPU hits a BREAK instruction +-- CONTINUE - When the CPU is halted due to a BREAK instruction, this signal, when asserted ('1') forces the CPU to commence +-- processing of the instruction following the BREAK instruction. +-- DEBUG_TXD - Serial output of runtime debug data if enabled. + +entity zpu_core_evo is + generic ( + -- Optional hardware features to be implemented. + IMPL_HW_BYTE_WRITE : boolean := false; -- Enable use of hardware direct byte write rather than read 32bits-modify 8 bits-write 32bits. + IMPL_HW_WORD_WRITE : boolean := false; -- Enable use of hardware direct byte write rather than read 32bits-modify 16 bits-write 32bits. + IMPL_OPTIMIZE_IM : boolean := true; -- Optimise Im instructions to gain speed. + IMPL_USE_INSN_BUS : boolean := true; -- Use a seperate bus to read instruction memory, normally implemented in BRAM. + IMPL_USE_WB_BUS : boolean := true; -- Use the wishbone interface in addition to direct access bus. + -- Optional instructions to be implemented in hardware: + IMPL_ASHIFTLEFT : boolean := true; -- Arithmetic Shift Left (uses same logic so normally combined with ASHIFTRIGHT and LSHIFTRIGHT). + IMPL_ASHIFTRIGHT : boolean := true; -- Arithmetic Shift Right. + IMPL_CALL : boolean := true; -- Call to direct address. + IMPL_CALLPCREL : boolean := true; -- Call to indirect address (add offset to program counter). + IMPL_DIV : boolean := true; -- 32bit signed division. + IMPL_EQ : boolean := true; -- Equality test. + IMPL_EXTENDED_INSN : boolean := true; -- Extended multibyte instruction set. + IMPL_FIADD32 : boolean := true; -- Fixed point Q17.15 addition. + IMPL_FIDIV32 : boolean := true; -- Fixed point Q17.15 division. + IMPL_FIMULT32 : boolean := true; -- Fixed point Q17.15 multiplication. + IMPL_LOADB : boolean := true; -- Load single byte from memory. + IMPL_LOADH : boolean := true; -- Load half word (16bit) from memory. + IMPL_LSHIFTRIGHT : boolean := true; -- Logical shift right. + IMPL_MOD : boolean := true; -- 32bit modulo (remainder after division). + IMPL_MULT : boolean := true; -- 32bit signed multiplication. + IMPL_NEG : boolean := true; -- Negate value in TOS. + IMPL_NEQ : boolean := true; -- Not equal test. + IMPL_POPPCREL : boolean := true; -- Pop a value into the Program Counter from a location relative to the Stack Pointer. + IMPL_PUSHSPADD : boolean := true; -- Add a value to the Stack pointer and push it onto the stack. + IMPL_STOREB : boolean := true; -- Store/Write a single byte to memory/IO. + IMPL_STOREH : boolean := true; -- Store/Write a half word (16bit) to memory/IO. + IMPL_SUB : boolean := true; -- 32bit signed subtract. + IMPL_XOR : boolean := true; -- Exclusive or of value in TOS. + -- Size/Control parameters for the optional hardware. + MAX_INSNRAM_SIZE : integer := 16384; -- Maximum size of the optional Instruction BRAM on the INSN Bus. + MAX_L1CACHE_BITS : integer := 4; -- Maximum size in instructionsG of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache. + MAX_L2CACHE_BITS : integer := 12; -- Maximum size in bytes of the Level 1 instruction cache governed by the number of bits, ie. 8 = 256 byte cache. + MAX_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits. + RESET_ADDR_CPU : integer := 0; -- Initial start address of the CPU. + START_ADDR_MEM : integer := 0; -- Start address of program memory. + STACK_ADDR : integer := 0; -- Initial stack address on CPU start. + CLK_FREQ : integer := 100000000 -- Frequency of the input clock. + ); + port ( + CLK : in std_logic; -- Main clock. + RESET : in std_logic; -- Reset the CPU (high). + ENABLE : in std_logic; -- Enable the CPU (high), setting low will halt the CPU until signal is returned high. + -- Main Memory/IO bus. + MEM_BUSY : in std_logic; + MEM_DATA_IN : in std_logic_vector(WORD_32BIT_RANGE); + MEM_DATA_OUT : out std_logic_vector(WORD_32BIT_RANGE); + MEM_ADDR : out std_logic_vector(ADDR_BIT_RANGE); + MEM_WRITE_ENABLE : out std_logic; + MEM_READ_ENABLE : out std_logic; + MEM_WRITE_BYTE : out std_logic; + MEM_WRITE_HWORD : out std_logic; + -- Instruction memory bus (if implemented). + MEM_BUSY_INSN : in std_logic; + MEM_DATA_IN_INSN : in std_logic_vector(WORD_32BIT_RANGE); + MEM_ADDR_INSN : out std_logic_vector(ADDR_BIT_RANGE); + MEM_READ_ENABLE_INSN : out std_logic; + -- Master Wishbone Memory/IO bus interface. + WB_CLK_I : in std_logic; + WB_RST_I : in std_logic; + WB_ACK_I : in std_logic; + WB_DAT_I : in std_logic_vector(WORD_32BIT_RANGE); + WB_DAT_O : out std_logic_vector(WORD_32BIT_RANGE); + WB_ADR_O : out std_logic_vector(ADDR_BIT_RANGE); + WB_CYC_O : out std_logic; + WB_STB_O : out std_logic; + WB_CTI_O : out std_logic_vector(2 downto 0); + WB_WE_O : out std_logic; + WB_SEL_O : out std_logic_vector(WORD_4BYTE_RANGE); + WB_HALT_I : in std_logic; + WB_ERR_I : in std_logic; + WB_INTA_I : in std_logic; + + -- Set to one to jump to interrupt vector + -- The ZPU will communicate with the hardware that caused the + -- interrupt via memory mapped IO or the interrupt flag can + -- be cleared automatically + INT_REQ : in std_logic; + INT_ACK : out std_logic; -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + INT_DONE : out std_logic; -- Interrupt service routine completed/done. + -- Break and debug signals. + BREAK : out std_logic; -- A break instruction encountered. + CONTINUE : in std_logic; -- When break activated, processing stops. Setting CONTINUE to logic 1 resumes processing with next instruction. + DEBUG_TXD : out std_logic -- Debug serial output. + ); +end zpu_core_evo; + +architecture behave of zpu_core_evo is + + -- Constants. + constant MAX_L1CACHE_SIZE : integer := (2**(MAX_L1CACHE_BITS)); + constant MAX_L2CACHE_SIZE : integer := (2**MAX_L2CACHE_BITS); + subtype L1CACHE_BIT_RANGE is natural range MAX_L1CACHE_BITS-1 downto 0; + subtype L2CACHE_BIT_RANGE is natural range MAX_L2CACHE_BITS-1 downto 0; + subtype L2CACHE_32BIT_RANGE is natural range MAX_L2CACHE_BITS-1 downto 2; + + -- Instruction offset in the instruction vector. + subtype INSN_RANGE is natural range 13 downto 0; + subtype OPCODE_RANGE is natural range 7 downto 0; + subtype DECODED_RANGE is natural range 13 downto 8; + subtype OPCODE_IM_RANGE is natural range 6 downto 0; + subtype IM_DATA_RANGE is natural range 6 downto 0; + subtype OPCODE_PARAM_RANGE is natural range 1 downto 0; + subtype OPCODE_INSN_RANGE is natural range 7 downto 2; + + -- Decoded instruction states. Used in the execution unit state machine according to instruction being processed. + type InsnType is + ( + Insn_Add, -- 00 + Insn_AddSP, -- 01 + Insn_AddTop, -- 02 + Insn_Alshift, -- 03 + Insn_And, -- 04 + Insn_Break, -- 05 + Insn_Call, -- 06 + Insn_Callpcrel, -- 07 + Insn_Div, -- 08 + Insn_Emulate, -- 09 + Insn_Eq, -- 0a + Insn_Eqbranch, -- 0b + Insn_Extend, -- 0c + Insn_FiAdd32, -- 0d + Insn_FiDiv32, -- 0e + Insn_FiMult32, -- 0f + Insn_Flip, -- 10 + Insn_Im, -- 11 + Insn_Lessthan, -- 12 + Insn_Lessthanorequal, -- 13 + Insn_Load, -- 14 + Insn_Loadb, -- 15 + Insn_Loadh, -- 16 + Insn_LoadSP, -- 17 + Insn_Mod, -- 18 + Insn_Mult, -- 19 + Insn_Neg, -- 1a + Insn_Neq, -- 1b + Insn_Neqbranch, -- 1c + Insn_Nop, -- 1d + Insn_Not, -- 1e + Insn_Or, -- 1f + Insn_PopPC, -- 20 + Insn_PopPCRel, -- 21 + Insn_PopSP, -- 22 + Insn_PushPC, -- 23 + Insn_PushSP, -- 24 + Insn_Pushspadd, -- 25 + Insn_Shift, -- 26 + Insn_Store, -- 27 + Insn_Storeb, -- 28 + Insn_Storeh, -- 29 + Insn_StoreSP, -- 2a + Insn_Sub, -- 2b + Insn_Ulessthan, -- 2c + Insn_Ulessthanorequal, -- 2d + Insn_Xor -- 2e + ); + + -- State machine states. Some states are extension of instruction execution whilst others maintain the ZPU runtime operations and state. + -- + type StateType is + ( + State_Div2, + State_Mult2, + State_Execute, + State_FiAdd2, + State_FiDiv2, + State_FiMult2, + State_Idle, + State_Init, + State_Mod2 + ); + + -- Decoder state machine states. Unit which fetches, decodes and stores the decoded instructions and the required states needed to do this. + -- + type DecoderStateType is + ( + Decode_Idle, + Decode_Fetch, + Decode_Word, + Decode_WriteCache + ); + + type Level1CacheStateType is + ( + State_PreSetAddr, + State_LatchAddr, + State_Decode, + State_Store + ); + + -- Memory transaction processing unit. All CPU memory accesses (except Instruction Fetch) go through this unit. These states define + -- those required to implement the unit. + -- + type MemXactStateType is + ( + MemXact_Idle, + MemXact_MemoryFetch, + MemXact_OpcodeFetch, + MemXact_TOS, + MemXact_NOS, + MemXact_TOSNOS, + MemXact_TOSNOS_2, + MemXact_TOSNOS_3, + MemXact_ReadByteToTOS, + MemXact_ReadWordToTOS, + MemXact_ReadAddToTOS, + MemXact_WriteToAddr, + MemXact_WriteByteToAddr, + MemXact_WriteByteToAddr2, + MemXact_WriteHWordToAddr, + MemXact_WriteHWordToAddr2 + ); + + -- Memory transaction processing commands. These states (commands) are the actions which the MTP can process. + -- + type MemXactCmdType is + ( + MX_CMD_READTOS, + MX_CMD_READNOS, + MX_CMD_READTOSNOS, + MX_CMD_READBYTETOTOS, + MX_CMD_READWORDTOTOS, + MX_CMD_READADDTOTOS, + MX_CMD_WRITEBYTETOADDR, + MX_CMD_WRITEHWORDTOADDR, + MX_CMD_WRITETOINDADDR, + MX_CMD_WRITE + ); + + -- Debug states. These states are those required to output debug data via the debug serialisation unit. + -- + type DebugType is + ( + Debug_Idle, + Debug_Start, + Debug_DumpL1, + Debug_DumpL1_1, + Debug_DumpL1_2, + Debug_DumpL2, + Debug_DumpL2_0, + Debug_DumpL2_1, + Debug_DumpL2_2, + Debug_DumpMem, + Debug_DumpMem_0, + Debug_DumpMem_1, + Debug_DumpMem_2, + Debug_End + ); + + -- Record to store a memory word and its validity, typically used for stack caching. + -- + type WordRecord is record + word : unsigned(WORD_32BIT_RANGE); + valid : std_logic; + end record; + + -- Record to contain an opcode and its decoded form. + -- + type InsnRecord is record + decodedOpcode : InsnType; + opcode : std_logic_vector(7 downto 0); + end record; + + -- Memory transaction records. Memory reads and writes are pushed into a queue and executed sequentially. + -- + type MemXactRecord is record + addr : std_logic_vector(ADDR_BIT_RANGE); + data : std_logic_vector(WORD_32BIT_RANGE); + cmd : MemXactCmdType; + end record; + -- + -- Array definitions. + type InsnWord is array(natural range 0 to wordBytes-1) of InsnRecord; + type InsnQueue is array(natural range 0 to 2*wordBytes-1) of InsnRecord; + type InsnL1Array is array(natural range 0 to ((2**(MAX_L1CACHE_BITS))-1)) of std_logic_vector(INSN_RANGE); + type MemXactArray is array(natural range 0 to ((2**MAX_MXCACHE_BITS)-1)) of MemXactRecord; + + signal pc : unsigned(ADDR_BIT_RANGE); -- Current program location being executed. + signal pcLast : unsigned(ADDR_BIT_RANGE); -- Last program location executed. + signal incPC : unsigned(ADDR_BIT_RANGE); -- Next program location to be executed. + signal incIncPC : unsigned(ADDR_BIT_RANGE); -- Next +2 program location to be executed. + signal inc3PC : unsigned(ADDR_BIT_RANGE); -- Next +3 program location to be executed. + signal inc4PC : unsigned(ADDR_BIT_RANGE); -- Next +4 program location to be executed. + signal inc5PC : unsigned(ADDR_BIT_RANGE); -- Next +5 program location to be executed. + signal sp : unsigned(ADDR_32BIT_RANGE); -- Current stack pointer. + signal incSp : unsigned(ADDR_32BIT_RANGE); -- Stack pointer when 1 value is popped. + signal incIncSp : unsigned(ADDR_32BIT_RANGE); -- Stack pointer when 2 values are popped. + signal decSp : unsigned(ADDR_32BIT_RANGE); -- Stack pointer after a value is pushed. + signal TOS : WordRecord; -- Top Of Stack value. + signal NOS : WordRecord; -- Next Of Stack value (ie. value after TOS). + signal mxTOS : WordRecord; -- Top Of Stack retrieved by the Memory Transaction Processor. + signal mxNOS : WordRecord; -- Next Of Stack retrieved by the MXP. + signal muxTOS : WordRecord; -- Multiplexed (to get most recent) TOS, either from MXP or current value. + signal muxNOS : WordRecord; -- Multiplexed (to get most recent) NOS, either from MXP or current value. + signal divResult : unsigned(WORD_32BIT_RANGE); + signal divRemainder : unsigned(WORD_32BIT_RANGE); + signal divStart : std_logic; + signal divComplete : std_logic; + signal quotientFractional : integer range 0 to 15; -- Fractional component size of a fixed point value. + signal divQuotientFractional : integer range 0 to 15; -- Fractional component size for the divider as it can be changed dynamically for integer division. + signal multResult : unsigned(wordSize*2-1 downto 0); -- Result after internal multiplication. + signal state : StateType; + signal fpAddResult : std_logic_vector(WORD_32BIT_RANGE); + signal fpMultResult : std_logic_vector(WORD_32BIT_RANGE); + signal bitCnt : unsigned(5 downto 0); + signal dividendCopy : std_logic_vector(61 downto 0); + signal divisorCopy : std_logic_vector(61 downto 0); + + -- Wishbone processing. + -- + signal ZPURESET : std_logic; + signal wbXactActive : std_logic; -- Wishbone interface is active. + + -- Break processing. + -- + signal inBreak : std_logic; -- Flag to indicate when the CPU is halted (1) due to a BREAK instruction or illegal instruction. + + -- Interrupt procesing. + -- + signal intTriggered : std_logic; -- Flag to indicate an interrupt has been requested, reset when interrupt processing starts. + signal inInterrupt : std_logic; -- Flag to indicate that the CPU is currently inside an interrupt processing block. + signal interruptSuspendedAddr : unsigned(ADDR_BIT_RANGE); -- Address that was interrupted by the interrupt, used to return processing when interrupt complete. + + -- Instruction storage, decoding and processing. + -- + signal insnExParameter : unsigned(WORD_32BIT_RANGE); -- Parameter storage for the extended instruction. + signal idimFlag : std_logic; -- Flag to indicate concurrent Im instructions which are building a larger word in TOS. + signal l1State : Level1CacheStateType; -- Current state of the L1 Cache decode and populate machine. + + -- Cache L1 specific signals. + -- + signal cacheL1 : InsnL1Array; -- Level 1 cache, implemented as registers to gain random access for instruction lookahead optimisation and instruction set extension. + signal cacheL1StartAddr : unsigned(ADDR_BIT_RANGE); -- Absolute address of first instruction in cache. + signal cacheL1FetchIdx : unsigned(ADDR_BIT_RANGE); -- Index into L1 cache decoded instructions will be placed. + signal cacheL1Invalid : std_logic; -- A flag to indicate when the L1 cache is in invalid. + signal cacheL1Empty : std_logic; -- A flag to indicate when the L1 cache is empty. + signal cacheL1Full : std_logic; -- A flag to indicate when the L1 cache is full. + signal cacheL1InsnAfterPC : unsigned(ADDR_BIT_RANGE); -- Count of how many instructions are in the cache after the current program counter. + attribute ramstyle : string; + attribute ramstyle of cacheL1 : signal is "logic"; + + -- Cache L2 (primary) specific signals. + -- + signal cacheL2FetchIdx : unsigned(ADDR_BIT_RANGE); -- Location in memory being read by the decoder for storage into cache. + signal cacheL2StartAddr : unsigned(ADDR_BIT_RANGE); -- The actual program address stored in the first cache location. + signal cacheL2Active : std_logic; -- A flag to indicate when the L2 cache is in use. + signal cacheL2Invalid : std_logic; -- A flag to indicate when the L2 cache is in invalid. + signal cacheL2Empty : std_logic; -- A flag to indicate the instruction cache is empty. + signal cacheL2Mux2Addr : unsigned(L2CACHE_32BIT_RANGE); -- Multiplexed address into L2 cache between the L1 fetch and debug fetch. + signal cacheL2Word : std_logic_vector(WORD_32BIT_RANGE); + signal cacheL2Write : std_logic; + signal cacheL2WriteByte : std_logic; -- Update a single byte in the L2 cache. + signal cacheL2WriteHword : std_logic; -- Update a 16bit half-word in the L2 cache. + signal cacheL2WriteAddr : unsigned(L2CACHE_BIT_RANGE); + signal cacheL2WriteData : std_logic_vector(WORD_32BIT_RANGE); + signal cacheL2IncAddr : std_logic; -- A flag to indicate when the L2 cache write address should be incremented, generally after a write pulse. + signal cacheL2MxAddrInCache : std_logic; -- A flag to indicate when an MXP address exists in the L2 cache. + signal cacheL2Full : std_logic; -- A flag to indicate when the L2 cache is full. + + -- Memory transaction processor. + -- + signal mxFifo : MemXactArray; + signal mxState : MemXactStateType; + signal mxFifoWriteIdx : unsigned(MAX_MXCACHE_BITS-1 downto 0); + signal mxFifoReadIdx : unsigned(MAX_MXCACHE_BITS-1 downto 0); + signal mxInsnData : std_logic_vector(WORD_32BIT_RANGE); + signal mxMemVal : WordRecord; -- Direct memory read result. + signal mxHoldCycles : integer range 0 to 3; -- Cycles to hold and extend memory transactions. + + -- Hardware Debugging. + -- + signal debugPC : unsigned(ADDR_BIT_RANGE); -- Debug PC for reading L1, L2 and memory for debugger output. + signal debugPC_StartAddr : unsigned(ADDR_BIT_RANGE); -- Start address for dump of memory contents. + signal debugPC_EndAddr : unsigned(ADDR_BIT_RANGE); -- End address for dump of memory contents. + signal debugPC_Width : integer range 4 to 32; -- Width of output in bytes. + signal debugPC_WidthCounter : integer range 0 to 31; -- Counter to match variable width. + signal debugState : DebugType; + signal debugOutputOnce : std_logic; -- Signal to prevent continuous output of debug messages when in a wait. + signal debugAllInfo : std_logic; -- Output all information from start point of entry to debug FSM if set. + signal debugRec : zpu_dbg_t; + signal debugLoad : std_logic; -- Load a debug record into the debug serialiser fsm, 1 = load, 0 = inactive. + signal debugReady : std_logic; -- Flag to indicate serializer fsm is busy (0) or available (1). + + --------------------------------------------- + -- Functions specific to the CPU core. + --------------------------------------------- + +begin + -- If the wishbone interface is enabled, assign permanent connections. + WB_INIT: if IMPL_USE_WB_BUS = true generate + ZPURESET <= RESET or WB_RST_I; + else generate + ZPURESET <= RESET; + end generate; + + --------------------------------------------- + -- Cache storage. + --------------------------------------------- + + -- Level 2 cache inferred with byte level write. + -- + CACHEL2 : work.evo_L2cache + generic map ( + addrbits => MAX_L2CACHE_BITS + ) + port map ( + clk => CLK, + memAAddr => std_logic_vector(cacheL2WriteAddr), + memAWriteEnable => cacheL2Write, + memAWriteByte => cacheL2WriteByte, + memAWriteHalfWord => cacheL2WriteHword, + memAWrite => cacheL2WriteData, + memARead => open, + + memBAddr => std_logic_vector(cacheL2Mux2Addr), + memBWrite => (others => '0'), + memBWriteEnable => '0', + memBRead => cacheL2Word + ); + + -- Instruction cache memory. cache instructions from the resync program counter forwards, when we get to a relative or direct + -- jump, if the destination is in cache, read from cache else resync. This speeds up operations where a resync (ie. branch, call etc) would + -- occur, saving cycles. It more especially speeds up the process if using one main bus and the external memory speed is slower than bram. + -- + -- Description of signals: + -- cacheL2StartAddr Absolute Start Address of word in first cache location. + -- cacheL2Active 1 when L2 cache is active, 0 when using dedicated instruction BRAM. + -- cacheL2Empty 1 when cache is empty, 0 when valid data present. + -- cacheL2Invalid 1 when the contents of L2Cache are no longer valid (due to next insn being out of cache scope). + -- cacheL2Mux2Addr Address multiplexer into cache. Address is set to the DebugPC address when the Debug state machine is not idle, all other times it is set to the Next cache fetch address. + -- cacheL2MxAddrInCache When a queued MX Processor address is in the L2 cache, set to 1 else set to 0. Used to determine if a memory write should be written into cache (write thru). + -- cacheL2Full 1 when cache is full, 0 otherwise. + -- + cacheL2Active <= '1' when IMPL_USE_INSN_BUS = false or (IMPL_USE_INSN_BUS = true and pc >= to_unsigned(MAX_INSNRAM_SIZE, pc'length)) + else '0'; + cacheL2Empty <= '1' when cacheL2FetchIdx(ADDR_32BIT_RANGE) = cacheL2StartAddr(ADDR_32BIT_RANGE) + else '0'; + cacheL2Invalid <= '1' when pc(ADDR_32BIT_RANGE) < cacheL2StartAddr(ADDR_32BIT_RANGE) or (pc(ADDR_32BIT_RANGE) > cacheL2FetchIdx(ADDR_32BIT_RANGE)) + else '0'; + cacheL2Mux2Addr <= cacheL1FetchIdx(L2CACHE_32BIT_RANGE) when DEBUG_CPU = false or (DEBUG_CPU = true and debugState = Debug_Idle) + else + debugPC(L2CACHE_32BIT_RANGE) when DEBUG_CPU = true + else + (others => 'X'); + cacheL2MxAddrInCache <= '1' when (to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)), cacheL2StartAddr'length) >= cacheL2StartAddr and to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)), cacheL2FetchIdx'length) < cacheL2FetchIdx) and (IMPL_USE_INSN_BUS = false or (IMPL_USE_INSN_BUS = true and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= MAX_INSNRAM_SIZE)) + else '0'; + cacheL2Full <= '1' when cacheL2FetchIdx(ADDR_32BIT_RANGE) - cacheL2StartAddr(ADDR_32BIT_RANGE) = MAX_L2CACHE_SIZE / 4 + else '0'; + --------------------------------------------- + -- End of Cache storage. + --------------------------------------------- + + ------------------------------------ + -- Memory transaction processor MXP. + ------------------------------------ + -- The mxp localises all memory/io operations into a single process. This aids in adaptation to differing bus topolgies as only this process + -- needs updating (the local INSN bus uses a direct BRAM/ROM connection and bypasses the MXP). This logic processes a queue of transactions in fifo + -- order and fetches instructions as required.. The processor unit commits requests to the queue and this logic fulfills them. If the CPU is only + -- using one bus for all memory and IO operations then memory transactions in the queue are completed before instruction fetches. If the instruction + -- queue is empty then the processor will stall until instructions are fetched. + -- + MEMXACT: process(CLK, ZPURESET, TOS, NOS, debugState) + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if ZPURESET = '1' then + MEM_WRITE_BYTE <= '0'; + MEM_WRITE_HWORD <= '0'; + MEM_READ_ENABLE <= '0'; + MEM_WRITE_ENABLE <= '0'; + WB_ADR_O(ADDR_32BIT_RANGE) <= (others => '0'); + WB_DAT_O <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '0'; + WB_STB_O <= '0'; + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + wbXactActive <= '0'; + cacheL2Write <= '0'; + cacheL2IncAddr <= '0'; + cacheL2FetchIdx <= (others => '0'); + cacheL2StartAddr <= (others => '0'); + mxFifoReadIdx <= (others => '0'); + mxState <= MemXact_Idle; + mxTOS <= ((others => '0'), '0'); + mxNOS <= ((others => '0'), '0'); + mxHoldCycles <= 0; + if DEBUG_CPU = true then + mxMemVal.valid <= '0'; + end if; + + ------------------------ + -- FALLING CLOCK EDGE -- + ------------------------ + elsif falling_edge(CLK) then + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(CLK) then + -- TOS/NOS values read in by the MXP are only valid for 1 cycle, so reset the valid flag. + mxTOS.valid <= '0'; + mxNOS.valid <= '0'; + + -- Memory signals are one clock width wide, reset them to inactive on each clock to ensure this.^^ + MEM_READ_ENABLE <= '0'; + MEM_WRITE_ENABLE <= '0'; + + -- Width signals are one clock width wide unless extended by busy signal. + if MEM_BUSY = '0' then + MEM_WRITE_BYTE <= '0'; + MEM_WRITE_HWORD <= '0'; + end if; + + -- Complete any active cache memory writes. + if cacheL2Write = '1' and mxHoldCycles = 0 then + cacheL2Write <= '0'; + cacheL2WriteByte <= '0'; + cacheL2WriteHword <= '0'; + + -- Once the cache write is complete, we update the address if needed, which will be setup in time for the next word to be read in from external memory. + if cacheL2IncAddr = '1' then + cacheL2IncAddr <= '0'; + + -- Update the address from where we fetch the next instruction, 32bit aligned 4 bytes. + cacheL2FetchIdx <= cacheL2FetchIdx + wordBytes; + end if; + end if; + + -- If wishbone interface is active and an ACK is received, deassert the signals. + if IMPL_USE_WB_BUS = true and wbXactActive = '1' and WB_ACK_I = '1' and WB_HALT_I = '0' and mxHoldCycles = 0 then + wbXactActive <= '0'; + WB_WE_O <= '0'; + WB_CYC_O <= '0'; + WB_STB_O <= '0'; + end if; + + -- TODO: WB_ERR_I needs better handling, should retry at least once and then issue a BREAK. + if IMPL_USE_WB_BUS = true and WB_ERR_I = '1' then + wbXactActive <= '0'; + WB_WE_O <= '0'; + WB_CYC_O <= '0'; + WB_STB_O <= '0'; + end if; + + -- If the hold cycle counter is not 0, then we are holding on the current transaction until it reaches zero, so decrement + -- ready to test next cycle. This mechanism is to prolong a memory cycle as without it, address setup and hold is 1 cycle and + -- valid data is expected at the end of the cycle. ie. the address and control signals are set on the current rising edge and become + -- active and on the next rising edge the data is expected to be valid, few components (ie. register ram) can meet this timing requirement. + if mxHoldCycles > 0 then + mxHoldCycles <= mxHoldCycles - 1; + end if; + + -- If the external memory is busy (1) or the wishbone interface is active and no ACK received then we have to back off and wait till next clock cycle and check again. + if MEM_BUSY = '0' and ((IMPL_USE_WB_BUS = true and ((wbXactActive = '1' and WB_ACK_I = '1') or wbXactActive = '0')) or IMPL_USE_WB_BUS = false) and mxHoldCycles = 0 then + + -- Memory transaction processor state machine. Idle is the control state and depending upon entries in the queue, debug or L2 usage, it + -- directs the FSM states accordingly. + case mxState is + when MemXact_Idle => + -- If there are no memory transactions to complete, debugging is enabled and the debug outputter is active, read the memory location + -- according to the given index. + if DEBUG_CPU = true and (mxFifoWriteIdx - mxFifoReadIdx) = 0 and (debugState /= Debug_Idle and debugState /= Debug_DumpL1 and debugState /= Debug_DumpL2 and debugState /= Debug_DumpMem) then + if IMPL_USE_WB_BUS = true and debugPC(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(debugPC(ADDR_32BIT_RANGE)); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxHoldCycles <= 1; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(debugPC(ADDR_32BIT_RANGE)); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE <= '1'; + end if; + mxMemVal.valid <= '0'; + mxState <= MemXact_MemoryFetch; + + -- If instruction queue is empty or there are no memory transactions to process and the instruction queue isnt full, + -- read the next instruction and fill the instruction queue. + elsif cacheL2Active = '1' and (mxFifoWriteIdx - mxFifoReadIdx) = 0 and cacheL2Invalid = '0' and cacheL2Full = '0' and cacheL2IncAddr = '0' then + if IMPL_USE_WB_BUS = true and cacheL2FetchIdx(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL2FetchIdx(ADDR_32BIT_RANGE)); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxHoldCycles <= 1; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL2FetchIdx(ADDR_32BIT_RANGE)); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE <= '1'; + mxHoldCycles <= 1; + end if; + cacheL2WriteAddr <= cacheL2FetchIdx(L2CACHE_BIT_RANGE); + mxState <= MemXact_OpcodeFetch; + + -- If there is an item on the queue and the memory system isnt busy from a previous operation, process + -- the queue item. + -- + elsif (mxFifoWriteIdx - mxFifoReadIdx) > 0 then + + -- Setup the address from the queue element and process the command. + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + end if; + mxHoldCycles <= 1; + + case mxFifo(to_integer(mxFifoReadIdx)).cmd is + -- Read to TOS + when MX_CMD_READTOS => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_TOS; + + -- Read to NOS + when MX_CMD_READNOS => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_NOS; + + -- Read both TOS and NOS (save cycles). + when MX_CMD_READTOSNOS => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_TOSNOS; + + -- Read Byte to TOS + when MX_CMD_READBYTETOTOS => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_ReadByteToTOS; + + -- Read Word to TOS + when MX_CMD_READWORDTOTOS => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_ReadWordToTOS; + + -- Read word and add to TOS + when MX_CMD_READADDTOTOS => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_ReadAddToTOS; + + -- Write value to address + when MX_CMD_WRITE => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_DAT_O <= mxFifo(to_integer(mxFifoReadIdx)).data; + WB_WE_O <= '1'; + wbXactActive <= '1'; + else + MEM_DATA_OUT <= mxFifo(to_integer(mxFifoReadIdx)).data; + MEM_WRITE_ENABLE <= '1'; + end if; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_BIT_RANGE)); + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + mxState <= MemXact_Idle; + mxHoldCycles <= 0; + + -- Read value at address, then write data to the value's address. + when MX_CMD_WRITETOINDADDR => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_WE_O <= '0'; + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_WriteToAddr; + + -- To write a byte, if hardware supports it, write out to the byte aligned address with data in bits 7-0 otherwise + -- we first read the 32bit word, update it and write it back. + when MX_CMD_WRITEBYTETOADDR => + -- If Hardware byte write not implemented or it is a write to the Startup ROM we have to resort + -- to a read-modify-write operation. + if IMPL_HW_BYTE_WRITE = false + then + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_32BIT_RANGE)) & "00"; + mxState <= MemXact_WriteByteToAddr; + else + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_DAT_O <= (others => 'X'); + case mxFifo(to_integer(mxFifoReadIdx)).addr(1 downto 0) is + when "00" => + WB_SEL_O <= "1000"; + WB_DAT_O(31 downto 24) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + when "01" => + WB_SEL_O <= "0100"; + WB_DAT_O(23 downto 16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + when "10" => + WB_SEL_O <= "0010"; + WB_DAT_O(15 downto 8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + when "11" => + WB_SEL_O <= "0001"; + WB_DAT_O(7 downto 0) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + end case; + + WB_ADR_O(ADDR_32BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0)<= (others => '0'); + WB_WE_O <= '1'; + wbXactActive <= '1'; + else + MEM_ADDR(ADDR_BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_BIT_RANGE); + MEM_WRITE_ENABLE <= '1'; + MEM_DATA_OUT <= X"000000" & mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0); + MEM_WRITE_BYTE <= '1'; + end if; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + mxHoldCycles <= 0; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_BIT_RANGE)); + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2WriteByte <= '1'; + cacheL2Write <= '1'; + end if; + end if; + + -- To write a word, if hardware supports it, write out to the word aligned address with data in bits 15-0 otherwise + -- we first read the 32bit word, update it and write it back. + when MX_CMD_WRITEHWORDTOADDR => + -- If Hardware half-word write not implemented or it is a write to the Startup ROM we have to resort + -- to a read-modify-write operation. + if IMPL_HW_WORD_WRITE = false + then + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_32BIT_RANGE)) & "00"; + mxState <= MemXact_WriteHWordToAddr; + else + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_DAT_O <= (others => 'X'); + case mxFifo(to_integer(mxFifoReadIdx)).addr(1) is + when '0' => + WB_SEL_O <= "1100"; + WB_DAT_O(31 downto 16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + when '1' => + WB_SEL_O <= "0011"; + WB_DAT_O(15 downto 0) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + end case; + WB_ADR_O(ADDR_32BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0)<= (others => '0'); + WB_WE_O <= '1'; + wbXactActive <= '1'; + else + MEM_ADDR(ADDR_BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_16BIT_RANGE) & "0"; + MEM_WRITE_ENABLE <= '1'; + MEM_DATA_OUT <= X"0000" & mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0); + MEM_WRITE_HWORD <= '1'; + end if; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_BIT_RANGE)); + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2WriteHword <= '1'; + cacheL2Write <= '1'; + end if; + mxHoldCycles <= 0; + end if; + + when others => + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end case; + end if; + + when MemXact_MemoryFetch => + if DEBUG_CPU = true then + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxMemVal.word <= unsigned(WB_DAT_I); + else + mxMemVal.word <= unsigned(MEM_DATA_IN); + end if; + mxMemVal.valid <= '1'; + end if; + mxState <= MemXact_Idle; + + when MemXact_OpcodeFetch => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + cacheL2WriteData <= WB_DAT_I; + else + cacheL2WriteData <= MEM_DATA_IN; + end if; + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + cacheL2IncAddr <= '1'; + mxState <= MemXact_Idle; + + when MemXact_TOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word <= unsigned(WB_DAT_I); + else + mxTOS.word <= unsigned(MEM_DATA_IN); + end if; + mxTOS.valid <= '1'; + if cacheL2Active = '1' then + mxHoldCycles <= 1; + end if; + mxState <= MemXact_Idle; + + when MemXact_NOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxNOS.word <= unsigned(WB_DAT_I); + else + mxNOS.word <= unsigned(MEM_DATA_IN); + end if; + mxNOS.valid <= '1'; + if cacheL2Active = '1' then + mxHoldCycles <= 1; + end if; + mxState <= MemXact_Idle; + + when MemXact_TOSNOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word <= unsigned(WB_DAT_I); + else + mxTOS.word <= unsigned(MEM_DATA_IN); + MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE))) + 1, ADDR_32BIT_SIZE)); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE <= '1'; + mxHoldCycles <= 1; + end if; + mxTOS.valid <= '1'; + mxState <= MemXact_TOSNOS_2; + + when MemXact_TOSNOS_2 => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE))) + 1, ADDR_32BIT_SIZE)); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxState <= MemXact_TOSNOS_3; + else + mxNOS.word <= unsigned(MEM_DATA_IN); + mxNOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + if cacheL2Active = '1' then + mxHoldCycles <= 1; + end if; + + when MemXact_TOSNOS_3 => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxNOS.word <= unsigned(WB_DAT_I); + mxNOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + + when MemXact_ReadByteToTOS => + mxTOS.word <= (others => '0'); + if wbXactActive = '1' then + mxTOS.word(7 downto 0) <= unsigned(WB_DAT_I(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8)); + else + mxTOS.word(7 downto 0) <= unsigned(MEM_DATA_IN(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8)); + end if; + mxTOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_ReadWordToTOS => + mxTOS.word <= (others => '0'); + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word(15 downto 0) <= unsigned(WB_DAT_I(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16)); + else + mxTOS.word(15 downto 0) <= unsigned(MEM_DATA_IN(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16)); + end if; + mxTOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_ReadAddToTOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word <= muxTOS.word + unsigned(WB_DAT_I); + else + mxTOS.word <= muxTOS.word + unsigned(MEM_DATA_IN); + end if; + mxTOS.valid <= '1'; + mxState <= MemXact_Idle; + + when MemXact_WriteToAddr => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= WB_DAT_I(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_DAT_O <= mxFifo(to_integer(mxFifoReadIdx)).data; + WB_WE_O <= '1'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + cacheL2WriteAddr <= unsigned(WB_DAT_I(L2CACHE_BIT_RANGE)); + else + MEM_ADDR(ADDR_32BIT_RANGE) <= MEM_DATA_IN(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_DATA_OUT <= mxFifo(to_integer(mxFifoReadIdx)).data; + MEM_WRITE_ENABLE <= '1'; + cacheL2WriteAddr <= unsigned(MEM_DATA_IN(L2CACHE_BIT_RANGE)); + end if; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_WriteByteToAddr => + -- For wishbone, we need to store the data and terminate the current cycle before we can commence a write cycle. + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + WB_DAT_O <= WB_DAT_I; + WB_DAT_O(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + cacheL2WriteData <= WB_DAT_I; + mxState <= MemXact_WriteByteToAddr2; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_DATA_OUT <= MEM_DATA_IN; + MEM_DATA_OUT(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + MEM_WRITE_ENABLE <= '1'; + cacheL2WriteData <= MEM_DATA_IN; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + -- If the data write is to a cached location, we have read the original value, so update cache with modified version. + if cacheL2MxAddrInCache = '1' then + -- Update the data to write with the actual changed byte, + cacheL2WriteData(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + + when MemXact_WriteByteToAddr2 => + if IMPL_USE_WB_BUS = true then + WB_ADR_O(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '1'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + + when MemXact_WriteHWordToAddr => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + WB_DAT_O <= WB_DAT_I; + WB_DAT_O(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + cacheL2WriteData <= WB_DAT_I; + mxState <= MemXact_WriteHWordToAddr2; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_DATA_OUT <= MEM_DATA_IN; + MEM_DATA_OUT(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + cacheL2WriteData <= MEM_DATA_IN; + MEM_WRITE_ENABLE <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + -- If the data write is to a cached location, we have read the original value, so update cache with modified version. + if cacheL2MxAddrInCache = '1' then + -- Update the data to write with the actual changed byte, + cacheL2WriteData(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + + when MemXact_WriteHWordToAddr2 => + if IMPL_USE_WB_BUS = true then + WB_ADR_O(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '1'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + + when others => + end case; + end if; + + -- Instruction Level 2 cache, we read upto the limit then back off until the gap between executed and read instructions + -- gets to a watermark and then re-enable reading. This allows the cache to maintain a set of past and future instructions so that when a + -- branch or call occurs, there is a chance we already have the needed instructions in cache. + -- + if cacheL2Active = '1' then + + -- If L2 fetching has been halted and the PC approaches the threshold (detault 3/4) then advance the Start Address of L2 data and re-enable L2 filling. + if cacheL2FetchIdx(ADDR_32BIT_RANGE) > pc(ADDR_32BIT_RANGE) and pc(ADDR_32BIT_RANGE) > cacheL2StartAddr(ADDR_32BIT_RANGE) and (pc - cacheL2StartAddr) > ((MAX_L2CACHE_SIZE/4)*3) and cacheL2Full = '1' then + cacheL2StartAddr <= cacheL2StartAddr + 16; + end if; + + -- If the PC goes out of scope of L2 data, reset and start fetching a fresh from the current PC address. + if cacheL2Invalid = '1' then + cacheL2FetchIdx <= pc(ADDR_32BIT_RANGE) & "00"; + cacheL2StartAddr <= pc(ADDR_32BIT_RANGE) & "00"; + cacheL2Write <= '0'; + cacheL2IncAddr <= '0'; + if (mxFifoWriteIdx - mxFifoReadIdx) = 0 and (mxState = MemXact_Idle or mxState = MemXact_OpcodeFetch) then + mxState <= MemXact_Idle; + end if; + end if; + end if; + end if; + end process; + + -- Use a mux to get the latest TOS/NOS values. This saves 1 clock cycle between data being retrieved and processed. + muxTOS.valid <= mxTOS.valid or TOS.valid; + muxTOS.word <= mxTOS.word when mxTOS.valid = '1' else TOS.word; + muxNOS.valid <= mxNOS.valid or NOS.valid; + muxNOS.word <= mxNOS.word when mxNOS.valid = '1' else NOS.word; + ----------------------------------------------------------------------------------------------------------------------------------------------------------------- + + ------------------------------------------------------------------------------ + -- L1 Cache + -- + -- L1 cache is a very small closely coupled cache which holds a decoded + -- shadow copy of the L2 cache or the BRAM at the point of execution and a few + -- instructions ahead. It is implemented in logic cells to allow instant + -- random access. This is required to perform instruction optimisation such as + -- multiple IM's and also to allow extended 2+ byte instructions which have + -- almost zero penalty over 1 byte instructions. + ------------------------------------------------------------------------------ + CACHE_LEVEL1: process(CLK, ZPURESET, pc) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable tDecodedOpcode : InsnType; + variable tInsnOffset : unsigned(4 downto 0); + begin + + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if ZPURESET = '1' then + cacheL1StartAddr <= (others => '0'); + cacheL1FetchIdx <= (others => '0'); + l1State <= State_PreSetAddr; + MEM_READ_ENABLE_INSN <= '0'; + MEM_ADDR_INSN <= (others => DontCareValue); + + ------------------------ + -- FALLING CLOCK EDGE -- + ------------------------ + elsif falling_edge(CLK) then + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(CLK) then + + -- If the cache becomes invalid due to a change in the PC or no cached data available then resync. + if (cacheL1Invalid = '1' and cacheL1Empty = '0') then -- or (cacheL2Active = '1' and cacheL2Invalid = '1') then + + -- RESYNC L1 Cache with BRAM/L2 Cache starting at current PC value.. + cacheL1FetchIdx <= pc(ADDR_32BIT_RANGE) & "00"; + cacheL1StartAddr <= pc(ADDR_32BIT_RANGE) & "00"; + + -- For BRAM preset the next address. + if cacheL2Active = '0' then + MEM_ADDR_INSN(ADDR_32BIT_RANGE) <= std_logic_vector(pc(ADDR_32BIT_RANGE)); + MEM_ADDR_INSN(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE_INSN <= '1'; + --else for L2 the address is automatically set in cacheL1FetchIdx + end if; + + -- State machine goes directly to the latch address phase. + l1State <= State_LatchAddr; + + -- If there is space in the L1 cache and data is available in the L2 cache/BRAM and we are not outputting debug information, fetch the next word, decode and place in L1. + elsif cacheL1Full = '0' + and + -- If BRAM ensure the memory is ready, for L2 no need to wait as the pointers control the reading of L2 data. + ((cacheL2Active = '0' and MEM_BUSY_INSN = '0') or (cacheL2Active = '1')) + and + -- If using L2 cache then only process when cached data is available in L2. + (cacheL2Active = '0' or (cacheL2Active = '1' and cacheL2Empty = '0' and cacheL2FetchIdx(ADDR_32BIT_RANGE) > cacheL1FetchIdx(ADDR_32BIT_RANGE)+1 )) + and + -- If debugging, only process if the debug FSM is idle as the L2 address is muxed with the debug address. + ((DEBUG_CPU = false or (DEBUG_CPU = true and debugState = Debug_Idle))) then + + case l1State is + when State_PreSetAddr => + -- For BRAM, set the address to read, external memory via L2 cache is set by the cacheL1FetchIdx signal. + if cacheL2Active = '0' then + MEM_ADDR_INSN(ADDR_32BIT_RANGE) <= std_logic_vector(pc(ADDR_32BIT_RANGE)); + MEM_ADDR_INSN(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE_INSN <= '1'; + --else for L2 the address is automatically set in cacheL1FetchIdx + end if; + l1State <= State_LatchAddr; + + -- This state gives time for the BRAM/L2 to latch the address ready for decode. + when State_LatchAddr => + l1State <= State_Decode; + + when State_Decode => + -- Read cycle for BRAM is at least one clock, so on next cycle clear the BRAM read signal. + if cacheL2Active = '0' then + MEM_READ_ENABLE_INSN <= '0'; + -- else for L2 there is no distinct signal, always outputs data for given input address. + end if; + + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + if cacheL2Active = '0' then + tOpcode := MEM_DATA_IN_INSN((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + else + tOpcode := cacheL2Word((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + end if; + + tInsnOffset(4) := not tOpcode(4); + tInsnOffset(3 downto 0) := unsigned(tOpcode(3 downto 0)); + + if (tOpcode(7 downto 7) = OpCode_Im) then tDecodedOpcode := Insn_Im; + + elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then tDecodedOpcode := Insn_StoreSP; + + elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then tDecodedOpcode := Insn_LoadSP; + + -- Emulated instructions, if there is no defined state to handle the instruction in hardware then it automatically runs the instruction + -- microcode from the vector 0x0+xxxxx*32. + elsif (tOpcode(7 downto 5) = OpCode_Emulate) then tDecodedOpcode := Insn_Emulate; + + if tOpcode(5 downto 0) = OpCode_Neqbranch then tDecodedOpcode := Insn_Neqbranch; + elsif tOpcode(5 downto 0) = OpCode_Eqbranch then tDecodedOpcode := Insn_Eqbranch; + elsif IMPL_EQ = true and tOpcode(5 downto 0) = OpCode_Eq then tDecodedOpcode := Insn_Eq; + elsif tOpcode(5 downto 0) = OpCode_Lessthan then tDecodedOpcode := Insn_Lessthan; + elsif tOpcode(5 downto 0) = OpCode_Lessthanorequal then tDecodedOpcode := Insn_Lessthanorequal; + elsif tOpcode(5 downto 0) = OpCode_Ulessthan then tDecodedOpcode := Insn_Ulessthan; + elsif tOpcode(5 downto 0) = OpCode_Ulessthanorequal then tDecodedOpcode := Insn_Ulessthanorequal; + elsif IMPL_LOADB = true and tOpcode(5 downto 0) = OpCode_Loadb then tDecodedOpcode := Insn_Loadb; + elsif IMPL_LOADH = true and tOpcode(5 downto 0) = OpCode_Loadh then tDecodedOpcode := Insn_Loadh; + elsif IMPL_MULT = true and tOpcode(5 downto 0) = OpCode_Mult then tDecodedOpcode := Insn_Mult; + elsif IMPL_STOREB = true and tOpcode(5 downto 0) = OpCode_Storeb then tDecodedOpcode := Insn_Storeb; + elsif IMPL_STOREH = true and tOpcode(5 downto 0) = OpCode_Storeh then tDecodedOpcode := Insn_Storeh; + elsif IMPL_PUSHSPADD = true and tOpcode(5 downto 0) = OpCode_Pushspadd then tDecodedOpcode := Insn_Pushspadd; + elsif IMPL_CALLPCREL = true and tOpcode(5 downto 0) = OpCode_Callpcrel then tDecodedOpcode := Insn_Callpcrel; + elsif IMPL_CALL = true and tOpcode(5 downto 0) = OpCode_Call then tDecodedOpcode := Insn_Call; + elsif IMPL_SUB = true and tOpcode(5 downto 0) = OpCode_Sub then tDecodedOpcode := Insn_Sub; + elsif IMPL_POPPCREL = true and tOpcode(5 downto 0) = OpCode_PopPCRel then tDecodedOpcode := Insn_PopPCRel; + elsif IMPL_LSHIFTRIGHT = true and tOpcode(5 downto 0) = OpCode_Lshiftright then tDecodedOpcode := Insn_Alshift; + elsif IMPL_ASHIFTLEFT = true and tOpcode(5 downto 0) = OpCode_Ashiftleft then tDecodedOpcode := Insn_Alshift; + elsif IMPL_ASHIFTRIGHT = true and tOpcode(5 downto 0) = OpCode_Ashiftright then tDecodedOpcode := Insn_Alshift; + elsif IMPL_XOR = true and tOpcode(5 downto 0) = OpCode_Xor then tDecodedOpcode := Insn_Xor; + elsif IMPL_DIV = true and tOpcode(5 downto 0) = OpCode_Div then tDecodedOpcode := Insn_Div; + elsif IMPL_MOD = true and tOpcode(5 downto 0) = OpCode_Mod then tDecodedOpcode := Insn_Mod; + elsif IMPL_NEG = true and tOpcode(5 downto 0) = OpCode_Neg then tDecodedOpcode := Insn_Neg; + elsif IMPL_NEQ = true and tOpcode(5 downto 0) = OpCode_Neq then tDecodedOpcode := Insn_Neq; + elsif IMPL_FIADD32 = true and tOpcode(5 downto 0) = OpCode_FiAdd32 then tDecodedOpcode := Insn_FiAdd32; + elsif IMPL_FIDIV32 = true and tOpcode(5 downto 0) = OpCode_FiDiv32 then tDecodedOpcode := Insn_FiDiv32; + elsif IMPL_FIMULT32 = true and tOpcode(5 downto 0) = OpCode_FiMult32 then tDecodedOpcode := Insn_FiMult32; + + end if; + + elsif (tOpcode(7 downto 4) = OpCode_AddSP) then + if tInsnOffset = 0 then tDecodedOpcode := Insn_Shift; + elsif tInsnOffset = 1 then tDecodedOpcode := Insn_AddTop; + else tDecodedOpcode := Insn_AddSP; + end if; + + -- Extended multibyte instruction set. If the extend instruction is encountered then during the execution phase the lookahead mechanism is used to determine + -- the extended instruction and execute accordingly. + elsif IMPL_EXTENDED_INSN = true and tOpcode(3 downto 0) = Opcode_Extend then tDecodedOpcode := Insn_Extend; + + else + case tOpcode(3 downto 0) is + when OpCode_Nop => tDecodedOpcode := Insn_Nop; + when OpCode_PushSP => tDecodedOpcode := Insn_PushSP; + when OpCode_PopPC => tDecodedOpcode := Insn_PopPC; + when OpCode_Add => tDecodedOpcode := Insn_Add; + when OpCode_Or => tDecodedOpcode := Insn_Or; + when OpCode_And => tDecodedOpcode := Insn_And; + when OpCode_Load => tDecodedOpcode := Insn_Load; + when OpCode_Not => tDecodedOpcode := Insn_Not; + when OpCode_Flip => tDecodedOpcode := Insn_Flip; + when OpCode_Store => tDecodedOpcode := Insn_Store; + when OpCode_PopSP => tDecodedOpcode := Insn_PopSP; + when others => tDecodedOpcode := Insn_Break; + end case; + end if; + + -- Store the decoded op directly into L1 cache. + cacheL1(to_integer(cacheL1FetchIdx+i))(DECODED_RANGE) <= std_logic_vector(to_unsigned(InsnType'POS(tDecodedOpcode), 6)); + cacheL1(to_integer(cacheL1FetchIdx+i))(OPCODE_RANGE) <= tOpcode; + end loop; + + -- Set address for next read, via cacheL1FetchIdx for L2 and external signals for BRAM. NB cacheL1FetchIdx always points to the next + -- available slot except during this state of the decoder. + cacheL1FetchIdx <= cacheL1FetchIdx + wordBytes; + + -- If we are not using L2 cache then take instructions direct from instruction BRAM. If a seperate + -- Instruction BRAM is not implemented, this will be ignored as L2 is our only source. + -- + if cacheL2Active = '0' then + MEM_ADDR_INSN(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL1FetchIdx(ADDR_32BIT_RANGE)+1); + MEM_ADDR_INSN(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE_INSN <= '1'; + --else for L2 the address is automatically set in cacheL1FetchIdx + end if; + + -- Repeat the fetch and decode until the L1 cache is full then disable fetching until a space becomes available. + -- We halt just before the full mark because it takes one cycle to halt. + l1State <= State_LatchAddr; + + when others => + l1State <= State_PreSetAddr; + end case; + + -- If there is only a set number of instructions remaining in the cache then we need to creep the start address forward so that + -- more instructions are fetched and decoded. We do this to ensure as many past instructions are available for backward jumps which + -- are most common in C. Adjust the threshold if forward jumps are more common. + elsif cacheL1InsnAfterPC < 8 and cacheL1Full = '1' then + cacheL1StartAddr <= cacheL1StartAddr + 8; + end if; + end if; + end process; + + -- Description of signals: + -- cacheL1StartAddr Absolute Start Address of word in first cache location. + -- cacheL1FetchIdx Next location a decoded instruction set (4 instructions) will be written into. + -- cacheL1InsnAfterPC Number of instructions stored in cache forward of current PC. + -- cacheL1Empty 1 when cache is empty, 0 when valid data present. + -- cacheL1Invalid 1 when cache doesnt have any valid instructions stored. + -- cacheL1Full 1 when cache is full, 0 otherwise. + -- + cacheL1InsnAfterPC <= cacheL1FetchIdx - pc when cacheL1Invalid = '0' + else to_unsigned(0, cacheL1InsnAfterPC'length); + cacheL1Empty <= '1' when cacheL1FetchIdx(ADDR_32BIT_RANGE) = cacheL1StartAddr(ADDR_32BIT_RANGE) + else '0'; + cacheL1Invalid <= '0' when (cacheL2Active = '0' or (cacheL2Active = '1' and cacheL2Invalid = '0')) and pc(ADDR_32BIT_RANGE) >= cacheL1StartAddr(ADDR_32BIT_RANGE) and pc(ADDR_32BIT_RANGE) < cacheL1FetchIdx(ADDR_32BIT_RANGE) + else '1'; + cacheL1Full <= '1' when cacheL1FetchIdx(ADDR_32BIT_RANGE) - cacheL1StartAddr(ADDR_32BIT_RANGE) = MAX_L1CACHE_SIZE / 4 + else '0'; + ------------------------------------------------------------------------------ + -- End of L1 Cache + ------------------------------------------------------------------------------ + + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Processor - Execution unit. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + PROCESSOR: process(CLK, ZPURESET, TOS, NOS, cacheL1, pc, sp, mxTOS, mxNOS, cacheL1FetchIdx, cacheL1StartAddr, cacheL2Active, cacheL2Empty, inBreak) + variable tSpOffset : unsigned(4 downto 0); + variable tIdx : integer range 0 to 3; + variable tInsnExec : std_logic; + variable tShiftCnt : integer range 0 to 31; + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + -- Prepare general stack possibility addresses, ie. Popped, 2xPopped or Pushed. + -- + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + incPC <= pc + 1; + incIncPC <= pc + 2; + inc3PC <= pc + 3; + inc4PC <= pc + 4; + inc5PC <= pc + 5; + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if ZPURESET = '1' then + inBreak <= '0'; + INT_ACK <= '0'; + INT_DONE <= '0'; + tIdx := 0; + tSpOffset := (others => '0'); + state <= State_Init; + sp <= to_unsigned(STACK_ADDR, maxAddrBit)(ADDR_32BIT_RANGE); + pc <= to_unsigned(RESET_ADDR_CPU, pc'LENGTH); + pcLast <= to_unsigned(RESET_ADDR_CPU, pc'LENGTH); + idimFlag <= '0'; + inInterrupt <= '0'; + mxFifoWriteIdx <= (others => '0'); + interruptSuspendedAddr <= (others => '0'); + TOS <= ((others => '0'), '0'); + NOS <= ((others => '0'), '0'); + -- + if IMPL_DIV = true or IMPL_FIDIV32 = true or IMPL_MOD = true then + divStart <= '0'; + divQuotientFractional <= 0; + end if; + if IMPL_FIADD32 = true or IMPL_FIMULT32 = true then + quotientFractional <= 15; + end if; + if DEBUG_CPU = true then + debugRec <= ZPU_DBG_T_INIT; + debugLoad <= '0'; + debugState <= Debug_Idle; + debugAllInfo <= '0'; + debugPC_StartAddr <= (others => '0'); + debugPC_EndAddr <= (others => '0'); + debugPC_Width <= 32; + debugPC_WidthCounter <= 0; + debugOutputOnce <= '0'; + else + debugPC_StartAddr <= (others => DontCareValue); + debugPC_EndAddr <= (others => DontCareValue); + debugPC_Width <= 32; + debugPC_WidthCounter <= 0; + debugRec <= ZPU_DBG_T_DONTCARE; + debugLoad <= DontCareValue; + debugReady <= DontCareValue; + debugOutputOnce <= DontCareValue; + end if; + + ------------------------ + -- FALLING CLOCK EDGE -- + ------------------------ + elsif falling_edge(CLK) then + + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(CLK) then + + --if DEBUG_CPU = true and debugState = Debug_Idle and pc = X"058be" then + -- debugPC_StartAddr <= X"01fc00"; --to_unsigned(131072-(512*3), debugPC_StartAddr'LENGTH); + -- debugPC_EndAddr <= X"01ff00"; --to_unsigned(131072, debugPC_EndAddr'LENGTH); + -- debugPC_Width <= 4; + -- debugState <= Debug_DumpMem; + --end if; + + if DEBUG_CPU = true and debugState = Debug_Idle and pc = X"1002b67" then --cacheL1FetchIdx < cacheL1FetchIdx_last then + debugState <= Debug_Start; + end if; + + -- In debug mode, the memory dump start and stop address are controlled by 2 vectors, preload them with defaults if uninitialised. + if DEBUG_CPU = true and debugPC_EndAddr = 0 then + debugPC_StartAddr <= to_unsigned(16#1000000#, debugPC_StartAddr'LENGTH); + debugPC_EndAddr <= to_unsigned(16#1001000#, debugPC_EndAddr'LENGTH); + end if; + + -- If the Memory Transaction processor has updated the stack parameters, update our working copy. + -- + if mxTOS.valid = '1' then + TOS.valid <= '1'; + TOS.word <= mxTOS.word; + end if; + if mxNOS.valid = '1' then + NOS.valid <= '1'; + NOS.word <= mxNOS.word; + end if; + + -- If debugging enabled, loading of debug information into the debug serialiser is only 1 clock width wide, reset on each clock tick. + -- + if DEBUG_CPU = true then + debugLoad <= '0'; + end if; + + -- Division start is only 1 clock width wide. + if IMPL_DIV = true or IMPL_FIDIV32 = true or IMPL_MOD = true then + divStart <= '0'; + divQuotientFractional <= 15; -- Always reset the quotient, integer division sets to 0 as no fractional component. + end if; + + -- If interrupt is active, we only clear the interrupt state once the PC is reset to the address which was suspended after the + -- interrupt, this prevents recursive interrupt triggers, desirable in cetain circumstances but not for this current design. + -- + if (INT_REQ = '1' or (IMPL_USE_WB_BUS = true and WB_INTA_I = '1')) and intTriggered = '0' then + intTriggered <= '1'; + end if; + INT_ACK <= '0'; -- Reset interrupt acknowledge if set, width is 1 clock only. + INT_DONE <= '0'; -- Reset interrupt done if set, width is 1 clock only. + if inInterrupt = '1' and pc(ADDR_BIT_RANGE) = interruptSuspendedAddr(ADDR_BIT_RANGE) then + inInterrupt <= '0'; -- no longer in an interrupt + INT_DONE <= '1'; -- Interrupt service routine complete. + end if; + + -- BREAK signal follows internal signal on clock edge. + BREAK <= inBreak; + + ------------------------------------- + -- Execution Processor. + ------------------------------------- + if (DEBUG_CPU = false or (DEBUG_CPU = true and debugReady = '1')) then + + case state is + -- If the emulation cache is implemented, initialise it else startup the CPU. + when State_Init => + state <= State_Idle; + + -- Idle the CPU if ENABLE signal is low. + -- + when State_Idle => + if ENABLE = '1' then + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + + if DEBUG_CPU = true and DEBUG_LEVEL >= 4 and debugState = Debug_Idle then + debugPC_StartAddr <= to_unsigned(0, debugPC_StartAddr'LENGTH); + debugPC_EndAddr <= to_unsigned(65536, debugPC_EndAddr'LENGTH); + debugState <= Debug_DumpMem; + end if; + end if; + + -- Each instruction must: + -- + -- 1. set idimFlag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + when State_Execute => + + -- If the debug state machine is outputting data, hold off from further actions. + if DEBUG_CPU = true and debugState /= Debug_Idle then + + -- When a break is active, all processing is suspended. + elsif inBreak = '1' then + + -- If continue flag set, resume with next instruction. + if CONTINUE = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + inBreak <= '0'; + end if; + + -- Act immediately if an interrupt has occurred. Do not recurse into ISR while interrupt line is active + elsif intTriggered = '1' and inInterrupt = '0' and idimFlag = '0' then + + -- We have to wait for TOS and NOS to become valid so they can be saved, so loop until they are valid. + if muxTOS.valid = '1' and muxNOS.valid = '1' then + -- We got an interrupt, execute interrupt instead of next instruction + intTriggered <= '0'; + inInterrupt <= '1'; + INT_ACK <= '1'; -- Acknowledge interrupt. + interruptSuspendedAddr <= pc(ADDR_BIT_RANGE); -- Save address which got interrupted. + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= pc; + NOS.word <= muxTOS.word; + pc <= to_unsigned(32+START_ADDR_MEM, maxAddrBit); -- Load Vector 0x20 (from memory start) as next address to execute from. + sp <= decSp; + + -- Setup a memory transaction to save NOS back to RAM, TOS in effect already popped. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- If debug enabled, write out state during fetch. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(6, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"494D544552505400"; + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end if; + + -- If the CPU is externally disabled during processing, go to the Idle state and wait until it is re-enabled. + -- + elsif ENABLE = '0' then + state <= State_Idle; + + -- Execution depends on the L1 having decoded instructions stored at the current PC. + -- As a minimum the cache must be valid and that there is at least 1 instruction in the cache. + elsif cacheL1Invalid = '0' and cacheL1InsnAfterPC > 4 then -- and (cacheL2Active = '0' or (cacheL2Active = '1' and cacheL2Full = '1')) then + + -- Remember the last PC location executed, used for jump detection. + pcLast <= pc; + + -- Set the stack offset for current instruction from its opcode. + tSpOffset(4) := not cacheL1(to_integer(pc))(4); + tSpOffset(3 downto 0) := unsigned(cacheL1(to_integer(pc)))(3 downto 0); + tInsnExec := '0'; + if DEBUG_CPU = true then + debugOutputOnce <= '0'; + end if; + + -------------------------------------------------------------------------------------------------------------- + -- Start of Instruction Execution Case block - process the current instruction held in L1 Cache. + -------------------------------------------------------------------------------------------------------------- + case InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE)))) is + + -- Immediate, store 7bit signed extended value into TOS. If this is the first Im then we set IDIM, if this is a subsequent Im following + -- on from other Im's without gap, then we shift TOS 7 bits to left and add in the new value. NB. First Im, bit 6 of bits 6-0 is used to set + -- all bits 31 downto 6 with the same value. + -- An optimisation has been added where by if more than 1 Im are sequential and in the L1 cache, then the result is calculated in 1 cycle. If due + -- to not enough cache data a > 1 Im is partially processed, ie. 3 Im out of 5, then the 3 are processed in 1 cycle and the remaining two in seperate + -- cycles. + when Insn_Im => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '1'; + pc <= incPC; + + -- If this is the first Im (single or non-cached) or this is a multi Im instruction, save current TOS and build new TOS from Im. + -- + if idimFlag = '0' then + -- As we are pushing a value, current TOS becomes NOS and we write back old NOS to memory. + NOS.word <= muxTOS.word; + sp <= decSp; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- All Im combinations sign extend the 7th bit of the first Im instruction then just overwrite the bits available. + --if cacheL1(to_integer(pc))(6) = '1' then + -- TOS.word <= "11111111111111111111111110000000"; + --else + -- TOS.word <= (others => '0'); + --end if; + for i in wordSize-1 downto 7 loop + TOS.word(i) <= cacheL1(to_integer(pc))(6); + end loop; + + -- For non-optimised hardware or optimised but we only have 1 Im, used the original logic. + if IMPL_OPTIMIZE_IM = false then + TOS.word(IM_DATA_RANGE) <= unsigned(cacheL1(to_integer(pc))(IM_DATA_RANGE)); + + -- If Im optimisation is enabled, work out if we have sufficient instructions and then determine how many Ims are grouped together, otherwise default to just 1 Im per time processing. + elsif IMPL_OPTIMIZE_IM = true then + + -- Debug code, if enabled, writes out the data relevant to the Im instruction being optimised. + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 and cacheL1FetchIdx(L1CACHE_BIT_RANGE) - pc(L1CACHE_BIT_RANGE) > 2 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA2(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.DATA3(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)); + debugRec.DATA4(63 downto 0) <= "0000000000000000" & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 16)) & std_logic_vector(cacheL2FetchIdx(15 downto 0)) & "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & "0000" & idimFlag & tInsnExec & cacheL2Full & cacheL2Write; + debugRec.OPCODE <= (others => DontCareValue); + debugRec.DECODED_OPCODE <= (others => DontCareValue); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + + -- TODO: + -- Perhaps use cacheL1InsnAfterPC in this loop to preserve logic. + -- Same for extended instructions. + -- + -- 5 Consecutive IM's + --if cacheL1FetchIdx - pc > 5 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '1' and cacheL1(to_integer(inc4PC))(7) = '1' and cacheL1(to_integer(inc5PC))(7) = '0' then + if cacheL1InsnAfterPC > 5 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '1' and cacheL1(to_integer(inc4PC))(7) = '1' and cacheL1(to_integer(inc5PC))(7) = '0' then + TOS.word(31 downto 0) <= unsigned(cacheL1(to_integer(pc))(3 downto 0)) & unsigned(cacheL1(to_integer(incPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incIncPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(inc3PC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(inc4PC))(OPCODE_IM_RANGE)); + pc <= inc5PC; + -- 4 Consecutive IM's + --elsif cacheL1FetchIdx - pc > 4 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '1' and cacheL1(to_integer(inc4PC))(7) = '0' then + elsif cacheL1InsnAfterPC > 4 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '1' and cacheL1(to_integer(inc4PC))(7) = '0' then + TOS.word(27 downto 0) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incIncPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(inc3PC))(OPCODE_IM_RANGE)); + pc <= inc4PC; + -- 3 Consecutive IM's + elsif cacheL1InsnAfterPC > 3 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '0' then + TOS.word(20 downto 0) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incIncPC))(OPCODE_IM_RANGE)); + pc <= inc3PC; + -- 2 Consecutive IM's + elsif cacheL1InsnAfterPC > 2 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '0' then + TOS.word(13 downto 0) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incPC))(OPCODE_IM_RANGE)); + pc <= incIncPC; + -- 1 IM + else + TOS.word(IM_DATA_RANGE) <= unsigned(cacheL1(to_integer(pc))(OPCODE_RANGE)(IM_DATA_RANGE)); + end if; + end if; + else + -- Further single Im instructions shift left by 7 bits then add it the value from the current opcode. + TOS.word(wordSize-1 downto 7) <= muxTOS.word(wordSize-8 downto 0); + TOS.word(IM_DATA_RANGE) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)); + end if; + end if; + + -- Store into Stack pointer + offset, write out the value in TOS to the location pointed by Stack pointer plus any offset given in the opcode. + when Insn_StoreSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + tIdx := 0; + idimFlag <= '0'; + sp <= incSp; + pc <= incPC; + + -- Always need to read the new NOS location into NOS unless the offset is 2 when the location will be + -- overwritten with TOS, so just use TOS. + if tSpOffset /= 2 then + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + tIdx := tIdx + 1; + end if; + + -- Write value of TOS to the memory location sp + offset stored in opcode if offset not 0 or 1. + -- + if tSpOffset >= 2 then + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).addr(ADDR_32BIT_RANGE)<= std_logic_vector(sp+tSpOffset); + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).data<= std_logic_vector(muxTOS.word); + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).cmd <= MX_CMD_WRITE; + tIdx := tIdx + 1; + end if; + + case tSpOffset is + -- If the offset is 0, we are writing into unused stack (as the stack pointer is incremented), so just assign + -- NOS to TOS and read the new NOS. + when "00000" => + TOS.word <= muxNOS.word; + + -- If the offset is 1 then we do nothing as a write of TOS to SP+1 is the location of the new TOS, so TOS doesnt change. + -- We read NOS though from the new location. + when "00001" => + + -- When offset is 2, TOS is written to the new NOS position in memory, so no point to reread, we just reuse TOS. + -- + when "00010" => + NOS.word <= muxTOS.word; + TOS.word <= muxNOS.word; + + -- All other cases TOS becomes NOS and we read the new NOS . + -- + when others => + TOS.word <= muxNOS.word; + end case; + + mxFifoWriteIdx <= mxFifoWriteIdx + tIdx; + end if; + + -- Load from Stack pointer + offset: save NOS onto stack (TOS is popped and no longer needed so we are not concerned), read into TOS + -- the value pointed to by the SP + Offset. NOS becomes the old TOS as we virtually pushed the read value onto the stack. + when Insn_LoadSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + sp <= decSp; + pc <= incPC; + + -- Commit NOS to memory as we will refresh NOS from TOS. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- If the offset is 0 then we are duplicating TOS into NOS. + if tSpOffset = 0 then + NOS.word <= muxTOS.word; + + -- If the offset is 1 then we are duplicating NOS into TOS. + elsif tSpOffset = 1 then + TOS.word <= muxNOS.word; + NOS.word <= muxTOS.word; + + -- Else we read the value at Sp + Offset into TOS. + else + -- Read TOS from the location pointed to by SP + Offset. + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_32BIT_RANGE) <= std_logic_vector(sp+tSpOffset); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_READTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + + -- NOS becomes TOS as we are pushing a new value onto the stack. + NOS.word <= muxTOS.word; + end if; + end if; + + -- Emulate. This is a dummy placeholder for instructions which have not been implemented in hardware. If an Opcode cannot be translated to + -- a state machine state, it falls through to here, the NOS is saved back onto the stack, TOS is set to NOS and TOS takes on + -- the next program counter value (ie. next instruction after the one which is not implemented). The Program counter is then set + -- to the vector containing the microcode to implement the instruction and a jump is made to that location. When the microcode is complete it + -- should set the Program counter to the value stored in TOS. + when Insn_Emulate => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + sp <= decSp; + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= incPC; + NOS.word <= muxTOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- The emulate address is calculated by the opcode value left shifted 5 places. If the BRAM start address is not zero then this is added to ensure the + -- emulation microcode is read form the BRAM: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= to_unsigned(to_integer(unsigned(cacheL1(to_integer(pc))(OPCODE_RANGE)(4 downto 0)) & "00000"), pc'LENGTH) + START_ADDR_MEM; + end if; + + -- Call function relative to current PC value. The Program counter for the next instruction after this (ie. call return address) is stored in TOS + -- and the Program counter is set to the value currently in TOS+PC (remember that assignments only occur at end of the cycle, so writing to TOS wont + -- actually happen until the moment we leave this cycle) and we start processing from the new Program counter location, or the called location. + when Insn_Callpcrel => + if IMPL_CALLPCREL = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= incPC; + pc <= pc + muxTOS.word(ADDR_BIT_RANGE); + end if; + end if; + + -- Call function. Same as above except the PC is set to the value stored in TOS, not TOS+PC. + when Insn_Call => + if IMPL_CALL = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= incPC; + pc <= muxTOS.word(ADDR_BIT_RANGE); + end if; + end if; + + -- Add value from location pointed to bye Stack Pointer. Setup to read the value stored at Stack pointer location + offset contained + -- in the OpCode. We then forward to the next state which adds the value read to the value stored in TOS. + when Insn_AddSP => + -- if TOS.valid = '1' and NOS.valid = '1' then + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(sp+tSpOffset); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READADDTOTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Push stack pointer. TOS is set to stack pointer value and old TOS value assigned to NOS. The current NOS value is written out + -- onto the stack. In effect TOS = sp, NOS = TOS and NOS stored to NOS-1, we accomplish a push stack pointer onto the stack. + when Insn_PushSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= decSp; + TOS.word <= (others => '0'); + TOS.word(ADDR_32BIT_RANGE) <= sp; + NOS.word <= muxTOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Pop the value on the stack into the Program counter. This is accomplished by setting the PC to the TOS value, then writing out the + -- NOS value (because NOS and TOS are not normally stored, they are held in register) and performing a resync. + when Insn_PopPC => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= muxTOS.word(ADDR_BIT_RANGE); + sp <= incSp; + TOS.word <= muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Same as above except the program counter is added to the value in TOS before being assigned to the next program counter value. + when Insn_PopPCRel => + if IMPL_POPPCREL = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= pc + muxTOS.word(ADDR_BIT_RANGE); + sp <= incSp; + TOS.word <= muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Add NOS to TOS and store into TOS. NOS is then read from the stack. + when Insn_Add => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxTOS.word + muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Subtract NOS from TOS and store into TOS. NOS is then read from the stack. + when Insn_Sub => + if IMPL_SUB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxNOS.word - muxTOS.word; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform a logical OR between TOS and NOS and store the result in TOS. We then retrieve the next stack value into NOS. + when Insn_Or => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxTOS.word or muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a logical AND between TOS and NOS and store the result in TOS. We then retrieve the next stack value into NOS. + when Insn_And => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxTOS.word and muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a Equal comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next stack value into NOS. + when Insn_Eq => + if IMPL_EQ = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (muxTOS.word = muxNOS.word) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform an unsigned less than comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next stack value into NOS. + when Insn_Ulessthan => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (muxTOS.word < muxNOS.word) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform an unsigned less than or equal comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next + -- stack value into NOS. + when Insn_Ulessthanorequal => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (muxTOS.word <= muxNOS.word) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a signed less than comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next stack value into NOS. + when Insn_Lessthan => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (signed(muxTOS.word) < signed(muxNOS.word)) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a signed less than or equal comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next + -- stack value into NOS. + when Insn_Lessthanorequal => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (signed(muxTOS.word) <= signed(muxNOS.word)) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Load TOS (next cycle) with the value pointed to by TOS. + when Insn_Load => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Write the NOS value to the memory location pointed by TOS. + when Insn_Store => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incIncSp; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE)<= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + + -- Write the NOS value into memory location pointed to by the current Stack Pointer - 1 (ie. next of stack), + -- then set the Stack Pointer to the current TOS value. + when Insn_PopSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= muxTOS.word(ADDR_32BIT_RANGE); + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + + -- No operation, just waste time. + when Insn_Nop => + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + -- Negate the TOS value. + when Insn_Not => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word <= not muxTOS.word; + end if; + + -- Reverse all the bits in the TOS. + when Insn_Flip => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + for i in 0 to wordSize-1 loop + TOS.word(i) <= muxTOS.word(wordSize-1-i); + end loop; + end if; + + -- Add the TOS and NOS together, store in the TOS. + when Insn_AddTop => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word <= muxTOS.word + muxNOS.word; + end if; + + -- Shift the TOS right 1 bit. + when Insn_Shift => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word(wordSize-1 downto 1) <= muxTOS.word(wordSize-2 downto 0); + TOS.word(0) <= '0'; + end if; + + -- Add the TOS to the Stack Pointer and store in TOS. This is word aligned so bits 0 & 1 are zero. + when Insn_Pushspadd => + if IMPL_PUSHSPADD = true then + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word <= (others => '0'); + TOS.word(ADDR_32BIT_RANGE) <= muxTOS.word((maxAddrBit-1)-minAddrBit downto 0)+sp; + end if; + end if; + + -- If the NOS is not 0 (or 0 for Eq) then add the TOS to the Program Counter. As the address is not guaranteed to be sequential, resync to + -- retrieve the new TOS / NOS (because they are both now invalid) and the new program instruction. If the NOS is 0 then just + -- retrieve the new TOS / NOS. + when Insn_Neqbranch | Insn_Eqbranch => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + -- branches are almost always taken as they form loops + idimFlag <= '0'; + sp <= incIncSp; + + if (InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE)))) = Insn_Neqbranch and muxNOS.word /= 0) or (InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE)))) = Insn_Eqbranch and NOS.word = 0) then + pc <= pc + muxTOS.word(ADDR_BIT_RANGE); + else + pc <= incPC; + end if; + + -- need to fetch stack again. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Set in motion a signed multiplication of the TOS * NOS. + when Insn_Mult => + if IMPL_MULT = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_Mult2; + multResult <= muxTOS.word * muxNOS.word; + end if; + end if; + + -- Set in motion a signed division of the TOS / NOS. + when Insn_Div => + if IMPL_DIV = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + divStart <= '1'; + divQuotientFractional <= 0; + state <= State_Div2; + end if; + end if; + + -- Set in motion a fixed point addition of the TOS / NOS. + when Insn_FiAdd32 => + if IMPL_FIADD32 = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_FiAdd2; + end if; + end if; + + -- Set in motion a fixed point division of the TOS / NOS. + when Insn_FiDiv32 => + if IMPL_FIDIV32 = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_FiDiv2; + end if; + end if; + + -- Set in motion a fixed point multiplication of the TOS / NOS. + when Insn_FiMult32 => + if IMPL_FIMULT32 = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_FiMult2; + end if; + end if; + + -- Read the aligned word pointed to by the TOS and then process in the next state to extract just the required byte. + when Insn_Loadb => + if IMPL_LOADB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READBYTETOTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Read the aligned dword pointed to by the TOS and update just the one required byte, + -- The loadb and storeb can be sped up by implementing hardware byte read/write. + when Insn_Storeb => + if IMPL_STOREB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incIncSp; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)+1).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_WRITEBYTETOADDR; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + end if; + + -- Read the aligned dword pointed to by the TOS and then process in the next state to extract just the required word. + when Insn_Loadh => + if IMPL_LOADH = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READWORDTOTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Read the aligned dword pointed to by the TOS and update just the one required word, + -- The loadb and storeb can be sped up by implementing hardware byte read/write. + when Insn_Storeh => + if IMPL_STOREB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incIncSp; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)+1).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_WRITEHWORDTOADDR; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + end if; + + -- Perform an exclusive or of the TOS and NOS which is stored in TOS in the next state. NOS is read from the + -- new location. + when Insn_Xor => + if IMPL_XOR = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxNOS.word xor muxTOS.word; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform a negation or inverse of the TOS. + when Insn_Neg => + if IMPL_NEG = true then + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + TOS.word <= (not muxTOS.word) + 1; + end if; + end if; + + -- Perform a signed comparison of TOS v NOS, if they are not equal, set the result to 1 which is stored in TOS in the next state. NOS + -- is read from the new memory location. + when Insn_Neq => + if IMPL_NEQ = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (signed(muxTOS.word) /= signed(muxNOS.word)) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform a modulo of TOS v NOS and push to stack. TOS is set to the result and NOS is read from the new stack location. + when Insn_Mod => + if IMPL_MOD = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + divStart <= '1'; + divQuotientFractional <= 0; + state <= State_Mod2; + end if; + end if; + + -- Shift NOS left or right TOS times according to the instruction. The shifting is done by VHDL operators paying attention to + -- shift left arithmetic where the sla operator doesnt give the normal results. + when Insn_Alshift => + if IMPL_ASHIFTLEFT = true or IMPL_ASHIFTRIGHT = true or IMPL_LSHIFTRIGHT = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + + -- Positions to shift stored in TOS. + tShiftCnt := to_integer(unsigned(std_logic_vector(muxTOS.word(4 downto 0)))); + + -- Logical Shift Right + if (muxNOS.word(31) and cacheL1(to_integer(pc))(OPCODE_RANGE)(2)) = '0' and cacheL1(to_integer(pc))(OPCODE_RANGE)(0) = '0' then + if (tShiftCnt = 0) then + TOS.word <= (others => '0'); + else + TOS.word <= unsigned(to_stdlogicvector(to_bitvector(std_logic_vector(muxNOS.word)) srl tShiftCnt)); + end if; + end if; + + -- Arithmetic Shift Right + if (muxNOS.word(31) and cacheL1(to_integer(pc))(OPCODE_RANGE)(2)) = '1' and cacheL1(to_integer(pc))(OPCODE_RANGE)(0) = '0' then + if (tShiftCnt = 0) then -- ASR #32 + TOS.word <= (others => std_logic(muxNOS.word(31))); + else + TOS.word <= unsigned(to_stdlogicvector(to_bitvector(std_logic_vector(muxNOS.word)) sra tShiftCnt)); + end if; + end if; + + -- Arithmetic Shift Left (NB. VHDL sla behaves in a non-standard way, it mirrors sra hence use of sll). + if (muxNOS.word(31) and cacheL1(to_integer(pc))(OPCODE_RANGE)(2)) = '0' and cacheL1(to_integer(pc))(OPCODE_RANGE)(0) = '1' then + if (tShiftCnt = 0) then + TOS.word <= muxNOS.word; + else + TOS.word <= unsigned(to_stdlogicvector(to_bitvector(std_logic_vector(muxNOS.word)) sll tShiftCnt)); + end if; + end if; + + -- Fetch new NOS value. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + -- The ZPU has an 8 bit instruction set which has few spare slots. This intruction allows extended multibyte additions to be coded and processed. + -- The instructions are coded as: Extend,,[,,,] + -- Where ParamSize = 00 - No parameter bytes + -- 01 - 8 bit parameter + -- 10 - 16 bit parameter + -- 11 - 32 bit parameter + -- Thus without any additional data fetches, new instructions have access to 3 parameters, TOS, NOS and the InsnParameter. + -- ie. To create an LDIR, Source=TOS, Dest=NOS and InsnParameter=Count + when Insn_Extend => + -- Ensure L1 cache has sufficient data to process this instruction, otherwise wait until it does before decoding and executing. + if cacheL1FetchIdx - pc > to_integer(unsigned(cacheL1(to_integer(pc)+1)(OPCODE_RANGE)(OPCODE_PARAM_RANGE)))+1 then + tInsnExec := '1'; + + -- For instructions which use a parameter, build the value ready for use. + -- TODO: This should be variables to meet the 1 cycle requirement or set during decode. + case cacheL1(to_integer(pc)+1)(OPCODE_PARAM_RANGE) is + when "00" => insnExParameter <= X"00000000"; + when "01" => insnExParameter <= X"000000" & unsigned(cacheL1(to_integer(pc)+2)(OPCODE_RANGE)); + when "10" => insnExParameter <= X"0000" & unsigned(cacheL1(to_integer(pc)+2)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+3)(OPCODE_RANGE)); + when "11" => insnExParameter <= unsigned(cacheL1(to_integer(pc)+2)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+3)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+4)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+5)(OPCODE_RANGE)); + end case; + + -- Decode the extended instruction at this point as we have access to 8 future instructions or bytes so can work out what is required and execute. + -- 1:0 = 00 means an instruction which operates with a default, byte, half-word or word parameter. ie. Extend,,[,,,] + + -- Memory fill instruction. Fill memory starting at address in NOS with zero, 8 bit, 16 or 32 bit repeating value for TOS bytes. + --if cacheL1(to_integer(pc)+1)(OPCODE_INSN_RANGE) = Opcode_Ex_Fill then + --end if; + + -- Debug code, if enabled, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(5, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"455854454E440000"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end if; + + -- Breakpoint, this is not a nornal instruction and used by debuggers to suspend a program exection. At the moment + -- this instuction sets the BREAK flag and just continues. + when Insn_Break => + tInsnExec := '1'; + report "Break instruction encountered" severity failure; + inBreak <= '1'; + + -- Debug code, if ENABLEd, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"425245414B504E54"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + + -- Dump out the L1, L2 and Memory for debugging. + debugState <= Debug_Start; + end if; + + -- Should never get here, so if debugging enabled, report. + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + inBreak <= '1'; + + -- Debug code, if ENABLEd, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(6, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"494C4C4547414C00"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end case; + + -- During waits, if debug enabled, output state and dump the L1 cache. + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 and (pc = X"1f00010") then + if debugState = Debug_Idle then + debugState <= Debug_DumpL2; + end if; + end if; + + -- Debug code, if enabled, writes out the current instruction. + --if ((DEBUG_CPU = true and DEBUG_LEVEL >= 1) or (DEBUG_CPU = true and pc >= X"000009b8" and pc < X"00000d3e")) and tInsnExec = '1' then + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 and tInsnExec = '1' then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1InsnAfterPC), 16)); + debugRec.DATA2(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 24)) & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 24)) & "10000000" & '0' & cacheL2IncAddr & idimFlag & tInsnExec & cacheL2Full & cacheL2Active & cacheL2Empty & cacheL2Write; + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + else + if DEBUG_CPU = true and debugOutputOnce = '0' then + -- During waits, if debug enabled, output state and dump the L1 cache. + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 and (pc = X"1002b67") then + if debugState = Debug_Idle then + debugState <= Debug_DumpL2; + end if; + end if; + --if (DEBUG_CPU = true and DEBUG_LEVEL >= 1) or (DEBUG_CPU = true and pc >= X"000009b8" and pc < X"00000d3e") then + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1InsnAfterPC), 16)); + debugRec.DATA2(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 24)) & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 24)) & "00000000" & '0' & cacheL2IncAddr & idimFlag & tInsnExec & cacheL2Full & cacheL2Active & cacheL2Empty & cacheL2Write; + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + debugOutputOnce <= '1'; + end if; + end if; + + -------------------------------------------------------------------------------------------------------------- + -- End of Instruction Execution Case block. + -------------------------------------------------------------------------------------------------------------- + + when State_Mult2 => + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(multResult); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= std_logic_vector(to_unsigned(InsnType'POS(InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE))))) , 6)); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + + TOS.word <= multResult(wordSize-1 downto 0); + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + + when State_Div2 => + if IMPL_DIV = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + + if divStart = '0' and divComplete = '1' then + TOS.word <= unsigned(divResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_Mod2 => + if IMPL_MOD = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divRemainder); + debugLoad <= '1'; + end if; + + if divStart = '0' and divComplete = '1' then + TOS.word <= unsigned(divRemainder(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_FiAdd2 => + if IMPL_FIADD32 = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + if divComplete = '1' and muxTOS.valid = '1' and muxNOS.valid = '1' then + TOS.word <= unsigned(fpAddResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_FiDiv2 => + if IMPL_FIDIV32 = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + if divComplete = '1' and muxTOS.valid = '1' and muxNOS.valid = '1' then + TOS.word <= unsigned(divResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_FiMult2 => + if IMPL_FIMULT32 = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + if divComplete = '1' and muxTOS.valid = '1' and muxNOS.valid = '1' then + TOS.word <= unsigned(fpMultResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + -- Should never reach this state, if debug enabled, output details. + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + inBreak <= '1'; + + -- Debug code, if ENABLEd, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"494C4C4547414C53"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end case; + -------------------------------------------------------------------------------------------------------------- + -- End of Instruction State Case block. + -------------------------------------------------------------------------------------------------------------- + + -- In debug mode, output the current data and the decoded instruction queue. + if DEBUG_CPU = true then + case debugState is + when Debug_Idle => + + when Debug_Start => + + -- Write out the primary data. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)); + debugRec.DATA2(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 16)) & std_logic_vector(cacheL2FetchIdx(15 downto 0)) & "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & "0000" & idimFlag & tInsnExec & cacheL2Full & cacheL2Write; + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + debugAllInfo <= '1'; + + debugState <= Debug_DumpL1; + + when Debug_DumpL1 => + debugPC <= (others => '0'); + debugState <= Debug_DumpL1_1; + + when Debug_DumpL1_1 => + -- Write out the opcode. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_SPLIT_DATA <= "01"; + if debugPC = MAX_L1CACHE_SIZE-(wordBytes*4) then + debugRec.FMT_POST_CRLF <= '1'; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '0'; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.DATA(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+ 0)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 1)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 2)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 3)(INSN_RANGE); + debugRec.DATA2(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+ 4)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 5)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 6)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 7)(INSN_RANGE); + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+ 8)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 9)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+10)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+11)(INSN_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+12)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+13)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+14)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+15)(INSN_RANGE); + if debugPC = 0 then + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(to_unsigned(to_integer(pc), debugRec.PC'LENGTH)); + debugRec.WRITE_PC <= '1'; + else + debugRec.WRITE_PC <= '0'; + end if; + debugLoad <= '1'; + debugState <= Debug_DumpL1_2; + debugPC <= debugPC + (wordBytes * 4); -- 16 instructions are output per loop. + + when Debug_DumpL1_2 => + -- Move onto next opcode in Fifo. + if debugPC = MAX_L1CACHE_SIZE then + if debugAllInfo = '1' then + -- if IMPL_USE_INSN_BUS = true then + -- debugState <= Debug_End; + -- else + debugState <= Debug_DumpL2; + -- end if; + else + debugState <= Debug_End; + end if; + else + debugState <= Debug_DumpL1_1; + end if; + + when Debug_DumpL2 => + debugPC <= (others => '0'); + debugState <= Debug_DumpL2_0; + + -- Wait state at start of dump so initial address gets registered in cache memory and data output. + when Debug_DumpL2_0 => + debugState <= Debug_DumpL2_1; + + -- Output the contents of L2 in the format + when Debug_DumpL2_1 => + -- Write out the opcode. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_SPLIT_DATA <= "01"; + if debugPC = MAX_L2CACHE_SIZE-1 or debugPC(4 downto 2) = "111" then + debugRec.FMT_POST_CRLF <= '1'; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(3, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + if debugPC(4 downto 2) = "000" then + debugRec.WRITE_PC <= '1'; + else + debugRec.WRITE_PC <= '0'; + end if; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(debugPC); + debugRec.DATA(63 downto 32) <= cacheL2Word(31 downto 24) & cacheL2Word(23 downto 16) & cacheL2Word(15 downto 8) & cacheL2Word(7 downto 0); + debugLoad <= '1'; + debugState <= Debug_DumpL2_2; + debugPC <= debugPC + wordBytes; -- 4 instructions are output per loop (limited by memory read into cacheL2Word). + + when Debug_DumpL2_2 => + -- Move onto next opcode in Fifo. + if debugPC = MAX_L2CACHE_SIZE then + if debugAllInfo = '1' then + debugState <= Debug_DumpMem; + else + debugState <= Debug_End; + end if; + else + debugState <= Debug_DumpL2_1; + end if; + + when Debug_DumpMem => + debugPC <= debugPC_StartAddr; + debugPC_WidthCounter <= 0; + debugState <= Debug_DumpMem_0; + + when Debug_DumpMem_0 => + if mxMemVal.valid = '0' then + debugState <= Debug_DumpMem_1; + end if; + + -- Output the contents of memory in the format + when Debug_DumpMem_1 => + if mxMemVal.valid = '1' then + debugPC_WidthCounter <= debugPC_WidthCounter+4; + + -- Write out the memory location. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_SPLIT_DATA <= "01"; + if debugPC = debugPC_EndAddr or debugPC_WidthCounter = debugPC_Width-4 then + debugRec.FMT_POST_CRLF <= '1'; + debugPC_WidthCounter <= 0; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(3, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + if debugPC_WidthCounter = 0 then + debugRec.WRITE_PC <= '1'; + else + debugRec.WRITE_PC <= '0'; + end if; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(debugPC); + debugRec.DATA(63 downto 32) <= std_logic_vector(mxMemVal.word(31 downto 24)) & std_logic_vector(mxMemVal.word(23 downto 16)) & std_logic_vector(mxMemVal.word(15 downto 8)) & std_logic_vector(mxMemVal.word(7 downto 0)); + debugLoad <= '1'; + debugState <= Debug_DumpMem_2; + debugPC <= debugPC + wordBytes; + end if; + + when Debug_DumpMem_2 => + -- Move onto next opcode in Fifo. + if debugPC = debugPC_EndAddr then + debugState <= Debug_End; + else + debugState <= Debug_DumpMem_1; + end if; + + when Debug_End => + debugAllInfo <= '0'; + debugState <= Debug_Idle; + end case; + end if; + end if; + --------------------------------------------------------------------------------------------------------------------------------------------------- + end if; + end process; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Hardware divider - Fixed Point. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + DIVIDER : if IMPL_DIV = true or IMPL_FIDIV32 = true or IMPL_MOD = true generate + process(CLK, ZPURESET, divStart, dividendCopy) + begin + divRemainder <= unsigned(dividendCopy(31 downto 0)); + + if ZPURESET = '1' then + divComplete <= '1'; + divResult <= (others => '0'); + + elsif rising_edge(CLK) then + + if divComplete = '1' and divStart = '1' then + divComplete <= '0'; + bitCnt <= to_unsigned((32+divQuotientFractional)-2, bitCnt'LENGTH); + divResult <= (others => '0'); + + dividendCopy(30 downto 0) <= std_logic_vector(muxTOS.word(30 downto 0)); + dividendCopy(61 downto 31) <= (others => '0'); + + divisorCopy(61) <= '0'; + divisorCopy(60 downto 30) <= std_logic_vector(muxNOS.word(30 downto 0)); + divisorCopy(29 downto 0) <= (others => '0'); + + -- set sign bit + if((muxTOS.word(31) = '1' and muxNOS.word(31) = '0') or (muxTOS.word(31) = '0' and muxNOS.word(31) = '1')) then + divResult(31) <= '1'; + else + divResult(31) <= '0'; + end if; + + elsif divComplete = '0' and (DEBUG_CPU = false or (DEBUG_CPU = true and debugReady = '1')) then + -- 64bit compare of divisor/dividend. + if((unsigned(dividendCopy)) >= unsigned(divisorCopy)) then + --subtract, should only occur when the dividend is greater than the divisor. + dividendCopy <= std_logic_vector(to_unsigned(to_integer(unsigned(dividendCopy)) - to_integer(unsigned(divisorCopy)), dividendCopy'LENGTH)); + --set quotient + divResult(to_integer(bitCnt)) <= '1'; + end if; + + --reduce divisor + divisorCopy <= to_stdlogicvector(to_bitvector(divisorCopy) srl 1); + + --stop condition + if bitCnt = 0 then + divComplete <= '1'; + else + --reduce bit counter + bitCnt <= bitCnt - 1; + end if; + end if; + end if; + end process; + else generate + dividendCopy <= (others => DontCareValue); + end generate; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Hardware adder - Fixed Point. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + FIADD32: if IMPL_FIADD32 = true generate + process(muxTOS.word, muxNOS.word, ZPURESET) + begin + if ZPURESET = '1' then + fpAddResult <= (others => '0'); + else + -- both negative + if muxTOS.word(31) = '1' and muxNOS.word(31) = '1' then + -- sign + fpAddResult(31) <= '1'; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxTOS.word(30 downto 0)) + to_integer(muxNOS.word(30 downto 0)), 31)); + + --both positive + elsif muxTOS.word(31) = '0' and muxNOS.word(31) = '0' then + -- sign + fpAddResult(31) <= '0'; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxTOS.word(30 downto 0)) + to_integer(muxNOS.word(30 downto 0)), 31)); + + -- subtract TOS - NOS + elsif muxTOS.word(31) = '0' and muxNOS.word(31) = '1' then + -- sign + if muxTOS.word(30 downto 0) > muxNOS.word(30 downto 0) then + fpAddResult(31) <= '1'; + else + fpAddResult(31) <= '0'; + end if; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxTOS.word(30 downto 0)) - to_integer(muxNOS.word(30 downto 0)), 31)); + + -- subtract NOS - TOS + else + -- sign + if muxTOS.word(30 downto 0) < muxNOS.word(30 downto 0) then + fpAddResult(31) <= '1'; + else + fpAddResult(31) <= '0'; + end if; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxNOS.word(30 downto 0)) - to_integer(muxTOS.word(30 downto 0)), 31)); + end if; + end if; + end process; + else generate + fpAddResult <= (others => DontCareValue); + end generate; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Hardware multiplier - Fixed Point. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + FIMULT32: if IMPL_FIMULT32 = true generate + signal TOSflip : std_logic_vector(31 downto 0); + signal NOSflip : std_logic_vector(31 downto 0); + signal TOSmult : std_logic_vector(31 downto 0); + signal NOSmult : std_logic_vector(31 downto 0); + signal resultFlip : std_logic_vector(63 downto 0); + signal result : std_logic_vector(63 downto 0); + begin + process(muxTOS.word, TOSflip) + begin + for i in 0 to wordSize-1 loop + TOSflip(i) <= muxTOS.word(wordSize-1-i); + end loop; + TOSflip <= std_logic_vector(signed(TOSflip) + 1); + end process; + + process(muxNOS.word, NOSflip) + begin + for i in 0 to wordSize-1 loop + NOSflip(i) <= muxNOS.word(wordSize-1-i); + end loop; + NOSflip <= std_logic_vector(signed(NOSflip) + 1); + end process; + + process(result, quotientFractional, resultFlip) + begin + for i in quotientFractional to 30+quotientFractional loop + resultFlip(i) <= result(30+quotientFractional-i); + end loop; + resultFlip <= std_logic_vector(signed(resultFlip) + 1); + end process; + + process(muxTOS.word, muxNOS.word, TOSflip, NOSflip) + begin + if muxTOS.word(31) = '1' then + TOSmult <= TOSflip; + else + TOSmult <= std_logic_vector(muxTOS.word); + end if; + + if muxNOS.word(31) = '1' then + NOSmult <= NOSflip; + else + NOSmult <= std_logic_vector(muxNOS.word); + end if; + end process; + + process(TOSmult, NOSmult) + begin + result <= std_logic_vector(signed(TOSmult) * signed(NOSmult)); + end process; + + process(result, resultFlip, muxTOS.word, muxNOS.word, quotientFractional) + begin + -- sign + if (muxTOS.word(31) = '1' and muxNOS.word(31) = '0') or (muxTOS.word(31) = '0' and muxNOS.word(31) = '1') then + fpMultResult(31) <= '1'; + fpMultResult(30 downto 0) <= resultFlip(30 downto 0); + else + fpMultResult(31) <= '0'; + fpMultResult(30 downto 0) <= result(30+quotientFractional downto quotientFractional); + end if; + end process; + else generate + fpMultResult <= (others => DontCareValue); + quotientFractional <= 0; + end generate; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Debugger output processor. + -- This logic takes a debug record and expands it to human readable form then dispatches it to the debug serial port. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Add debug uart if required. Increasing the TX and DBG Fifo depth can help short term (ie. initial start of the CPU) + -- but once full, the debug run will eventually operate at the slowest denominator, ie. the TX speed and how quick it can + -- shift 10 bits. + DEBUG : if DEBUG_CPU = true generate + DEBUGUART: entity work.zpu_uart_debug + generic map ( + CLK_FREQ => CLK_FREQ -- Frequency of master clock. + ) + port map ( + -- CPU Interface + CLK => CLK, -- Master clock + RESET => ZPURESET, -- high active sync reset + DEBUG_DATA => debugRec, -- write data + CS => debugLoad, -- Chip Select. + READY => debugReady, -- Debug processor ready for next command. + + -- Serial data + TXD => DEBUG_TXD + ); + end generate; + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- End of debugger output processor. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + +end behave; diff --git a/zpu/cpu/zpu_core_evo.vhd..2 b/zpu/cpu/zpu_core_evo.vhd..2 new file mode 100755 index 0000000..98525d3 --- /dev/null +++ b/zpu/cpu/zpu_core_evo.vhd..2 @@ -0,0 +1,3598 @@ +-- ZPU Evolution +-- +-- Copyright 2004-2008 (ZPU Design, Small, Medium) oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- Copyright 2008 (zpuino) alvieboy - Álvaro Lopes - alvieboy@alvie.com +-- Copyright 2013 (zpuflex) Alastair M. Robinson +-- Copyright 2018-2019 (ZPU Evo) Philip Smart +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. +-- +-- Evo History: +-- 181230 v0.1 Initial version created by merging items of the Small, Medium and Flex versions. +-- 190328 v0.5 Working with Instruction, Emulation or No Cache with or without seperate instruction +-- bus. Runs numerous tests and output same as the Medium CPU. One small issue is running +-- without an instruction bus and instruction/emulation cache enabled, the DMIPS value is lower +-- than just with instruction bus or emulation bus, seems some clash which reuults in waits states +-- slowing the CPU down. +-- 191021 v1.0 First release. All variations tested but more work needed on the SDRAM controller to +-- make use of burst mode in order to populate the L2 cache in fewer cycles. +-- Additional instructions need to be added back in after test and verification, albeit some +-- which are specific to the Sharp Emulator should be skipped. +-- Additional effort needs spending on the Wishbone Error signal to retry the bus transaction, +-- currently it just aborts it which is not ideal. +-- 191126 v1.1 Bug fixes. When switching off WishBone the CPU wouldnt run. +-- 191215 v1.2 Bug fixes. Removed L2 Cache megacore and replaced with inferred equivalent, fixed hardware +-- byte/h-word write which was always defaulting to read-update-write, fixed L2 timing with +-- external SDRAM, minor tweaks and currently looking at better constraints. +-- 191220 v1.21 Changes to Mult, shifting it from a combination assignment to a clocked assignment to improve +-- slack. Small changes made for slack in setup and hold. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_pkg.all; + +-------------------------------------------------------------------------------------------------------------------------------------------- +-- ZPU Evo Signal Description. +-------------------------------------------------------------------------------------------------------------------------------------------- +-- +-- Main Memory/IO Bus. +-- ------------------- +-- This bus is used to access all external memory and IO, it can also, via configuration, be used to read instructions from attached memory. +-- +-- MEM_WRITE_ENABLE - set to '1' for a single cycle to send off a write request. +-- MEM_DATA_OUT is valid only while MEM_WRITE_ENABLE='1'. +-- MEM_WRITE_BYTE - set to '1' when performing a byte write with data in bits 7-0 of MEM_DATA_OUT +-- MEM_WRITE_HWORD - set to '1' when performing a half word write with data in bits 15-0 of MEM_DATA_OUT +-- MEM_READ_ENABLE - set to '1' for a single cycle to send off a read request. Data is expected on MEM_DATA_IN on next clock rising edge +-- unless MEM_BUSY is asserted in which case the data is read on the next clock rising edge after MEM_BUSY is +-- de-asserted. +-- +-- MEM_BUSY - This signal is used to prolong a read or write cycle, whilst asserted, any read or write cycle is paused as is the +-- CPU with signals remaining in same state just prior to MEM_BUSY assetion. +-- Set to '0' when MEM_READ is valid after a read request. +-- If set to '1'(busy), the current cycle is held until released. For MEM_READ_ENABLE = '1' this means data will be +-- latched on clock rising edge following deassertion of MEM_BUSY. For MEM_WRITE_ENABLE, the write transaction is held +-- with MEM_WRITE_ENABLE asserted until the cycle following the deassertion of MEM_BUSY. +-- MEM_ADDR - address for read/write request +-- MEM_DATA_IN - read data. Valid only on the cycle after mem_busy='0' after +-- MEM_READ_ENABLE='1' for a single cycle. +-- MEM_DATA_OUT - data to write +-- +-- Wishbone Bus B4 Specification +-- ----------------------------- +-- This bus is the industry standard for FPGA IP designs and the one primarily used in OpenCores. In this implementation it is +-- 32bit wide using a Master/Multi-Slave configuration with the ZPU acting as Master. It is a compile time configurable extension as +-- some uses of the ZPU Evo wont need it and thus saves fabric area. The description below is taken from the OpenCores Wishbone B4 +-- specification. +-- +-- WB_CLK_I - The clock input [WB_CLK_I] coordinates all activities for the internal logic within the WISHBONE interconnect. +-- - All WISHBONE output signals are registered at the rising edge of [WB_CLK_I]. All WISHBONE input signals are +-- - stable before the rising edge of [WB_CLK_I]. +-- WB_RST_I - The reset input [WB_RST_I] forces the WISHBONE interface to restart. In this design, this signal is tied to the +-- - ZPU reset via an OR mechanism, forcing the ZPU to reset if activated. +-- WB_ACK_I - The acknowledge input [WB_ACK_I], when asserted, indicates the normal termination of a bus cycle. +-- WB_DAT_I - The data input array [WB_DAT_I] is used to pass binary data. The array boundaries are determined by the port size, +-- - with a port size of 32-bits in this design. +-- WB_DAT_O - The data output array [DAT_O()] is used to pass binary data. The array boundaries are determined by the port size, +-- - with a port size of 32-bits in this design. +-- WB_ADR_O - The address output array [WB_ADR_O] is used to pass a binary address. The higher array boundary is specific to the +-- - address width of the core, and the lower array boundary is determined by the data port size and granularity. +-- - This design is 32bit so WB_ADR[1:0] specify the byte level granularity. +-- WB_CYC_O - The cycle output [WB_CYC_O], when asserted, indicates that a valid bus cycle is in progress. The signal is asserted +-- - for the duration of all bus cycles. +-- WB_STB_O - The strobe output [WB_STB_O] indicates a valid data transfer cycle. It is used to qualify various other signals on +-- - the interface such as [WB_SEL_O]. The SLAVE asserts either the [WB_ACK_I], [WB_ERR_I] or [WB_RTY_I] signals in +-- - response to every assertion of the [WB_STB_O] signal. +-- WB_CTI_O - The Cycle Type Idenfier [WB_CTI_O] Address Tag provides additional information about the current cycle. The MASTER +-- - sends this information to the SLAVE. The SLAVE can use this information to prepare the response for the next cycle. +-- WB_WE_O - The write enable output [WB_WE_O] indicates whether the current local bus cycle is a READ or WRITE cycle. The +-- - signal is negated during READ cycles, and is asserted during WRITE cycles. +-- WB_SEL_O - The select output array [WB_SEL_O] indicates where valid data is expected on the [WB_DAT_I] signal array during +-- - READ cycles, and where it is placed on the [WB_DAT_O] signal array during WRITE cycles. The array boundaries are +-- - determined by the granularity of a port which is 32bit in this design leading to a WB_SEL_O width of 4 bits, 1 +-- - bit to represent each byte. ie. WB_SEL_O[3] = MSB, WB_SEL_O[0] = LSB. +-- WB_HALT_I - +-- WB_ERR_I - The error input [WB_ERR_I] indicates an abnormal cycle termination. The source of the error, and the response +-- - generated by the MASTER is defined by the IP core supplier, in this case the intention (NYI) is to retry +-- - the transaction. +-- WB_INTA_I - A non standard signal to allow a wishbone device to interrupt the ZPU when set to logic '1'. The interrupt is +-- - registered on the next rising edge. +-- +-- +-- Instruction Memory Bus +-- ---------------------- +-- This bus is used for dedicated faster response read only memory containing the code to be run. Using this bus results in faster +-- CPU performance. If this bus is not used/disabled, all instructions will be fetched via the main bus (System or Wishbone bus). +-- +-- MEM_BUSY_INSN - Memory is busy ('1') so data invalid. +-- MEM_DATA_IN_INSN - Instruction data in. +-- MEM_ADDR_INSN - Instruction address bus. +-- MEM_READ_ENABLE_INSN - Instruction read enable signal (active high). +-- +-- INT_REQ - Set to '1' by external logic until interrupts are acknowledged by CPU. +-- INT_ACK - Set to '1' for 1 clock cycle when the interrupt is acknowledged and processing commences. +-- INT_DONE - Set to '1' for 1 clock cycle when the interrupt processing is complete +-- BREAK - Set to '1' when CPU hits a BREAK instruction +-- CONTINUE - When the CPU is halted due to a BREAK instruction, this signal, when asserted ('1') forces the CPU to commence +-- processing of the instruction following the BREAK instruction. +-- DEBUG_TXD - Serial output of runtime debug data if enabled. + +entity zpu_core_evo is + generic ( + -- Optional hardware features to be implemented. + IMPL_HW_BYTE_WRITE : boolean := false; -- Enable use of hardware direct byte write rather than read 32bits-modify 8 bits-write 32bits. + IMPL_HW_WORD_WRITE : boolean := false; -- Enable use of hardware direct byte write rather than read 32bits-modify 16 bits-write 32bits. + IMPL_OPTIMIZE_IM : boolean := true; -- Optimise Im instructions to gain speed. + IMPL_USE_INSN_BUS : boolean := true; -- Use a seperate bus to read instruction memory, normally implemented in BRAM. + IMPL_USE_WB_BUS : boolean := true; -- Use the wishbone interface in addition to direct access bus. + -- Optional instructions to be implemented in hardware: + IMPL_ASHIFTLEFT : boolean := true; -- Arithmetic Shift Left (uses same logic so normally combined with ASHIFTRIGHT and LSHIFTRIGHT). + IMPL_ASHIFTRIGHT : boolean := true; -- Arithmetic Shift Right. + IMPL_CALL : boolean := true; -- Call to direct address. + IMPL_CALLPCREL : boolean := true; -- Call to indirect address (add offset to program counter). + IMPL_DIV : boolean := true; -- 32bit signed division. + IMPL_EQ : boolean := true; -- Equality test. + IMPL_EXTENDED_INSN : boolean := true; -- Extended multibyte instruction set. + IMPL_FIADD32 : boolean := true; -- Fixed point Q17.15 addition. + IMPL_FIDIV32 : boolean := true; -- Fixed point Q17.15 division. + IMPL_FIMULT32 : boolean := true; -- Fixed point Q17.15 multiplication. + IMPL_LOADB : boolean := true; -- Load single byte from memory. + IMPL_LOADH : boolean := true; -- Load half word (16bit) from memory. + IMPL_LSHIFTRIGHT : boolean := true; -- Logical shift right. + IMPL_MOD : boolean := true; -- 32bit modulo (remainder after division). + IMPL_MULT : boolean := true; -- 32bit signed multiplication. + IMPL_NEG : boolean := true; -- Negate value in TOS. + IMPL_NEQ : boolean := true; -- Not equal test. + IMPL_POPPCREL : boolean := true; -- Pop a value into the Program Counter from a location relative to the Stack Pointer. + IMPL_PUSHSPADD : boolean := true; -- Add a value to the Stack pointer and push it onto the stack. + IMPL_STOREB : boolean := true; -- Store/Write a single byte to memory/IO. + IMPL_STOREH : boolean := true; -- Store/Write a half word (16bit) to memory/IO. + IMPL_SUB : boolean := true; -- 32bit signed subtract. + IMPL_XOR : boolean := true; -- Exclusive or of value in TOS. + -- Size/Control parameters for the optional hardware. + MAX_INSNRAM_SIZE : integer := 16384; -- Maximum size of the optional Instruction BRAM on the INSN Bus. + MAX_L1CACHE_BITS : integer := 4; -- Maximum size in instructionsG of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache. + MAX_L2CACHE_BITS : integer := 12; -- Maximum size in bytes of the Level 1 instruction cache governed by the number of bits, ie. 8 = 256 byte cache. + MAX_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits. + RESET_ADDR_CPU : integer := 0; -- Initial start address of the CPU. + START_ADDR_MEM : integer := 0; -- Start address of program memory. + STACK_ADDR : integer := 0; -- Initial stack address on CPU start. + CLK_FREQ : integer := 100000000 -- Frequency of the input clock. + ); + port ( + CLK : in std_logic; -- Main clock. + RESET : in std_logic; -- Reset the CPU (high). + ENABLE : in std_logic; -- Enable the CPU (high), setting low will halt the CPU until signal is returned high. + -- Main Memory/IO bus. + MEM_BUSY : in std_logic; + MEM_DATA_IN : in std_logic_vector(WORD_32BIT_RANGE); + MEM_DATA_OUT : out std_logic_vector(WORD_32BIT_RANGE); + MEM_ADDR : out std_logic_vector(ADDR_BIT_RANGE); + MEM_WRITE_ENABLE : out std_logic; + MEM_READ_ENABLE : out std_logic; + MEM_WRITE_BYTE : out std_logic; + MEM_WRITE_HWORD : out std_logic; + -- Instruction memory bus (if implemented). + MEM_BUSY_INSN : in std_logic; + MEM_DATA_IN_INSN : in std_logic_vector(WORD_32BIT_RANGE); + MEM_ADDR_INSN : out std_logic_vector(ADDR_BIT_RANGE); + MEM_READ_ENABLE_INSN : out std_logic; + -- Master Wishbone Memory/IO bus interface. + WB_CLK_I : in std_logic; + WB_RST_I : in std_logic; + WB_ACK_I : in std_logic; + WB_DAT_I : in std_logic_vector(WORD_32BIT_RANGE); + WB_DAT_O : out std_logic_vector(WORD_32BIT_RANGE); + WB_ADR_O : out std_logic_vector(ADDR_BIT_RANGE); + WB_CYC_O : out std_logic; + WB_STB_O : out std_logic; + WB_CTI_O : out std_logic_vector(2 downto 0); + WB_WE_O : out std_logic; + WB_SEL_O : out std_logic_vector(WORD_4BYTE_RANGE); + WB_HALT_I : in std_logic; + WB_ERR_I : in std_logic; + WB_INTA_I : in std_logic; + + -- Set to one to jump to interrupt vector + -- The ZPU will communicate with the hardware that caused the + -- interrupt via memory mapped IO or the interrupt flag can + -- be cleared automatically + INT_REQ : in std_logic; + INT_ACK : out std_logic; -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + INT_DONE : out std_logic; -- Interrupt service routine completed/done. + -- Break and debug signals. + BREAK : out std_logic; -- A break instruction encountered. + CONTINUE : in std_logic; -- When break activated, processing stops. Setting CONTINUE to logic 1 resumes processing with next instruction. + DEBUG_TXD : out std_logic -- Debug serial output. + ); +end zpu_core_evo; + +architecture behave of zpu_core_evo is + + -- Constants. + constant MAX_L1CACHE_SIZE : integer := (2**(MAX_L1CACHE_BITS)); + constant MAX_L2CACHE_SIZE : integer := (2**MAX_L2CACHE_BITS); + subtype L1CACHE_BIT_RANGE is natural range MAX_L1CACHE_BITS-1 downto 0; + subtype L2CACHE_BIT_RANGE is natural range MAX_L2CACHE_BITS-1 downto 0; + subtype L2CACHE_32BIT_RANGE is natural range MAX_L2CACHE_BITS-1 downto 2; + + -- Instruction offset in the instruction vector. + subtype INSN_RANGE is natural range 13 downto 0; + subtype OPCODE_RANGE is natural range 7 downto 0; + subtype DECODED_RANGE is natural range 13 downto 8; + subtype OPCODE_IM_RANGE is natural range 6 downto 0; + subtype IM_DATA_RANGE is natural range 6 downto 0; + subtype OPCODE_PARAM_RANGE is natural range 1 downto 0; + subtype OPCODE_INSN_RANGE is natural range 7 downto 2; + + -- Decoded instruction states. Used in the execution unit state machine according to instruction being processed. + type InsnType is + ( + Insn_Add, -- 00 + Insn_AddSP, -- 01 + Insn_AddTop, -- 02 + Insn_Alshift, -- 03 + Insn_And, -- 04 + Insn_Break, -- 05 + Insn_Call, -- 06 + Insn_Callpcrel, -- 07 + Insn_Div, -- 08 + Insn_Emulate, -- 09 + Insn_Eq, -- 0a + Insn_Eqbranch, -- 0b + Insn_Extend, -- 0c + Insn_FiAdd32, -- 0d + Insn_FiDiv32, -- 0e + Insn_FiMult32, -- 0f + Insn_Flip, -- 10 + Insn_Im, -- 11 + Insn_Lessthan, -- 12 + Insn_Lessthanorequal, -- 13 + Insn_Load, -- 14 + Insn_Loadb, -- 15 + Insn_Loadh, -- 16 + Insn_LoadSP, -- 17 + Insn_Mod, -- 18 + Insn_Mult, -- 19 + Insn_Neg, -- 1a + Insn_Neq, -- 1b + Insn_Neqbranch, -- 1c + Insn_Nop, -- 1d + Insn_Not, -- 1e + Insn_Or, -- 1f + Insn_PopPC, -- 20 + Insn_PopPCRel, -- 21 + Insn_PopSP, -- 22 + Insn_PushPC, -- 23 + Insn_PushSP, -- 24 + Insn_Pushspadd, -- 25 + Insn_Shift, -- 26 + Insn_Store, -- 27 + Insn_Storeb, -- 28 + Insn_Storeh, -- 29 + Insn_StoreSP, -- 2a + Insn_Sub, -- 2b + Insn_Ulessthan, -- 2c + Insn_Ulessthanorequal, -- 2d + Insn_Xor -- 2e + ); + + -- State machine states. Some states are extension of instruction execution whilst others maintain the ZPU runtime operations and state. + -- + type StateType is + ( + State_Div2, + State_Mult2, + State_Execute, + State_FiAdd2, + State_FiDiv2, + State_FiMult2, + State_Idle, + State_Init, + State_Mod2 + ); + + -- Decoder state machine states. Unit which fetches, decodes and stores the decoded instructions and the required states needed to do this. + -- + type DecoderStateType is + ( + Decode_Idle, + Decode_Fetch, + Decode_Word, + Decode_WriteCache + ); + + type Level1CacheStateType is + ( + State_PreSetAddr, + State_LatchAddr, + State_LatchAddrPause, + State_Decode, + State_Store + ); + + -- Memory transaction processing unit. All CPU memory accesses (except Instruction Fetch) go through this unit. These states define + -- those required to implement the unit. + -- + type MemXactStateType is + ( + MemXact_Idle, + MemXact_MemoryFetch, + MemXact_OpcodeFetch, + MemXact_TOS, + MemXact_NOS, + MemXact_TOSNOS, + MemXact_TOSNOS_2, + MemXact_TOSNOS_3, + MemXact_ReadByteToTOS, + MemXact_ReadWordToTOS, + MemXact_ReadAddToTOS, + MemXact_WriteToAddr, + MemXact_WriteByteToAddr, + MemXact_WriteByteToAddr2, + MemXact_WriteHWordToAddr, + MemXact_WriteHWordToAddr2 + ); + + -- Memory transaction processing commands. These states (commands) are the actions which the MTP can process. + -- + type MemXactCmdType is + ( + MX_CMD_READTOS, + MX_CMD_READNOS, + MX_CMD_READTOSNOS, + MX_CMD_READBYTETOTOS, + MX_CMD_READWORDTOTOS, + MX_CMD_READADDTOTOS, + MX_CMD_WRITEBYTETOADDR, + MX_CMD_WRITEHWORDTOADDR, + MX_CMD_WRITETOINDADDR, + MX_CMD_WRITE + ); + + -- Debug states. These states are those required to output debug data via the debug serialisation unit. + -- + type DebugType is + ( + Debug_Idle, + Debug_Start, + Debug_DumpL1, + Debug_DumpL1_1, + Debug_DumpL1_2, + Debug_DumpL2, + Debug_DumpL2_0, + Debug_DumpL2_1, + Debug_DumpL2_2, + Debug_DumpMem, + Debug_DumpMem_0, + Debug_DumpMem_1, + Debug_DumpMem_2, + Debug_End + ); + + -- Record to store a memory word and its validity, typically used for stack caching. + -- + type WordRecord is record + word : unsigned(WORD_32BIT_RANGE); + valid : std_logic; + end record; + + -- Record to contain an opcode and its decoded form. + -- + type InsnRecord is record + decodedOpcode : InsnType; + opcode : std_logic_vector(7 downto 0); + end record; + + -- Memory transaction records. Memory reads and writes are pushed into a queue and executed sequentially. + -- + type MemXactRecord is record + addr : std_logic_vector(ADDR_BIT_RANGE); + data : std_logic_vector(WORD_32BIT_RANGE); + cmd : MemXactCmdType; + end record; + -- + -- Array definitions. + type InsnWord is array(natural range 0 to wordBytes-1) of InsnRecord; + type InsnQueue is array(natural range 0 to 2*wordBytes-1) of InsnRecord; + type InsnL1Array is array(natural range 0 to ((2**(MAX_L1CACHE_BITS))-1)) of std_logic_vector(INSN_RANGE); + type MemXactArray is array(natural range 0 to ((2**MAX_MXCACHE_BITS)-1)) of MemXactRecord; + + signal pc : unsigned(ADDR_BIT_RANGE); -- Current program location being executed. + signal pcLast : unsigned(ADDR_BIT_RANGE); -- Last program location executed. + signal incPC : unsigned(ADDR_BIT_RANGE); -- Next program location to be executed. + signal incIncPC : unsigned(ADDR_BIT_RANGE); -- Next +2 program location to be executed. + signal inc3PC : unsigned(ADDR_BIT_RANGE); -- Next +3 program location to be executed. + signal inc4PC : unsigned(ADDR_BIT_RANGE); -- Next +4 program location to be executed. + signal inc5PC : unsigned(ADDR_BIT_RANGE); -- Next +5 program location to be executed. + signal sp : unsigned(ADDR_32BIT_RANGE); -- Current stack pointer. + signal incSp : unsigned(ADDR_32BIT_RANGE); -- Stack pointer when 1 value is popped. + signal incIncSp : unsigned(ADDR_32BIT_RANGE); -- Stack pointer when 2 values are popped. + signal decSp : unsigned(ADDR_32BIT_RANGE); -- Stack pointer after a value is pushed. + signal TOS : WordRecord; -- Top Of Stack value. + signal NOS : WordRecord; -- Next Of Stack value (ie. value after TOS). + signal mxTOS : WordRecord; -- Top Of Stack retrieved by the Memory Transaction Processor. + signal mxNOS : WordRecord; -- Next Of Stack retrieved by the MXP. + signal muxTOS : WordRecord; -- Multiplexed (to get most recent) TOS, either from MXP or current value. + signal muxNOS : WordRecord; -- Multiplexed (to get most recent) NOS, either from MXP or current value. + signal divResult : unsigned(WORD_32BIT_RANGE); + signal divRemainder : unsigned(WORD_32BIT_RANGE); + signal divStart : std_logic; + signal divComplete : std_logic; + signal quotientFractional : integer range 0 to 15; -- Fractional component size of a fixed point value. + signal divQuotientFractional : integer range 0 to 15; -- Fractional component size for the divider as it can be changed dynamically for integer division. + signal multResult : unsigned(wordSize*2-1 downto 0); -- Result after internal multiplication. + signal state : StateType; + signal fpAddResult : std_logic_vector(WORD_32BIT_RANGE); + signal fpMultResult : std_logic_vector(WORD_32BIT_RANGE); + signal bitCnt : unsigned(5 downto 0); + signal dividendCopy : std_logic_vector(61 downto 0); + signal divisorCopy : std_logic_vector(61 downto 0); + + -- Wishbone processing. + -- + signal ZPURESET : std_logic; + signal wbXactActive : std_logic; -- Wishbone interface is active. + + -- Break processing. + -- + signal inBreak : std_logic; -- Flag to indicate when the CPU is halted (1) due to a BREAK instruction or illegal instruction. + + -- Interrupt procesing. + -- + signal intTriggered : std_logic; -- Flag to indicate an interrupt has been requested, reset when interrupt processing starts. + signal inInterrupt : std_logic; -- Flag to indicate that the CPU is currently inside an interrupt processing block. + signal interruptSuspendedAddr : unsigned(ADDR_BIT_RANGE); -- Address that was interrupted by the interrupt, used to return processing when interrupt complete. + + -- Instruction storage, decoding and processing. + -- + signal insnExParameter : unsigned(WORD_32BIT_RANGE); -- Parameter storage for the extended instruction. + signal idimFlag : std_logic; -- Flag to indicate concurrent Im instructions which are building a larger word in TOS. + signal l1State : Level1CacheStateType; -- Current state of the L1 Cache decode and populate machine. + + -- Cache L1 specific signals. + -- + signal cacheL1 : InsnL1Array; -- Level 1 cache, implemented as registers to gain random access for instruction lookahead optimisation and instruction set extension. + signal cacheL1StartAddr : unsigned(ADDR_BIT_RANGE); -- Absolute address of first instruction in cache. + signal cacheL1FetchIdx : unsigned(ADDR_BIT_RANGE); -- Index into L1 cache decoded instructions will be placed. + signal cacheL1Invalid : std_logic; -- A flag to indicate when the L1 cache is in invalid. + signal cacheL1Empty : std_logic; -- A flag to indicate when the L1 cache is empty. + signal cacheL1Full : std_logic; -- A flag to indicate when the L1 cache is full. + signal cacheL1InsnAfterPC : unsigned(ADDR_BIT_RANGE); -- Count of how many instructions are in the cache after the current program counter. + attribute ramstyle : string; + attribute ramstyle of cacheL1 : signal is "logic"; + + -- Cache L2 (primary) specific signals. + -- + signal cacheL2FetchIdx : unsigned(ADDR_BIT_RANGE); -- Location in memory being read by the decoder for storage into cache. + signal cacheL2StartAddr : unsigned(ADDR_BIT_RANGE); -- The actual program address stored in the first cache location. + signal cacheL2Active : std_logic; -- A flag to indicate when the L2 cache is in use. + signal cacheL2Invalid : std_logic; -- A flag to indicate when the L2 cache is in invalid. + signal cacheL2Empty : std_logic; -- A flag to indicate the instruction cache is empty. + signal cacheL2Mux2Addr : unsigned(L2CACHE_32BIT_RANGE); -- Multiplexed address into L2 cache between the L1 fetch and debug fetch. + signal cacheL2Word : std_logic_vector(WORD_32BIT_RANGE); + signal cacheL2Write : std_logic; + signal cacheL2WriteByte : std_logic; -- Update a single byte in the L2 cache. + signal cacheL2WriteHword : std_logic; -- Update a 16bit half-word in the L2 cache. + signal cacheL2WriteAddr : unsigned(L2CACHE_BIT_RANGE); + signal cacheL2WriteData : std_logic_vector(WORD_32BIT_RANGE); + signal cacheL2IncAddr : std_logic; -- A flag to indicate when the L2 cache write address should be incremented, generally after a write pulse. + signal cacheL2MxAddrInCache : std_logic; -- A flag to indicate when an MXP address exists in the L2 cache. + signal cacheL2Full : std_logic; -- A flag to indicate when the L2 cache is full. +signal cacheL2InsnAfterPC : unsigned(ADDR_BIT_RANGE); -- Count of how many instructions are in the cache after the current program counter. + + -- Memory transaction processor. + -- + signal mxFifo : MemXactArray; + signal mxState : MemXactStateType; + signal mxFifoWriteIdx : unsigned(MAX_MXCACHE_BITS-1 downto 0); + signal mxFifoReadIdx : unsigned(MAX_MXCACHE_BITS-1 downto 0); + signal mxInsnData : std_logic_vector(WORD_32BIT_RANGE); + signal mxMemVal : WordRecord; -- Direct memory read result. + signal mxHoldCycles : integer range 0 to 2047; -- Cycles to hold and extend memory transactions. + + -- Hardware Debugging. + -- + signal debugPC : unsigned(ADDR_BIT_RANGE); -- Debug PC for reading L1, L2 and memory for debugger output. + signal debugPC_StartAddr : unsigned(ADDR_BIT_RANGE); -- Start address for dump of memory contents. + signal debugPC_EndAddr : unsigned(ADDR_BIT_RANGE); -- End address for dump of memory contents. + signal debugPC_Width : integer range 4 to 32; -- Width of output in bytes. + signal debugPC_WidthCounter : integer range 0 to 31; -- Counter to match variable width. + signal debugState : DebugType; + signal debugOutputOnce : std_logic; -- Signal to prevent continuous output of debug messages when in a wait. + signal debugAllInfo : std_logic; -- Output all information from start point of entry to debug FSM if set. + signal debugRec : zpu_dbg_t; + signal debugLoad : std_logic; -- Load a debug record into the debug serialiser fsm, 1 = load, 0 = inactive. + signal debugReady : std_logic; -- Flag to indicate serializer fsm is busy (0) or available (1). +signal pause : integer range 0 to 65535; + --------------------------------------------- + -- Functions specific to the CPU core. + --------------------------------------------- + +begin + -- If the wishbone interface is enabled, assign permanent connections. + WB_INIT: if IMPL_USE_WB_BUS = true generate + ZPURESET <= RESET or WB_RST_I; + else generate + ZPURESET <= RESET; + end generate; + + --------------------------------------------- + -- Cache storage. + --------------------------------------------- + + -- Level 2 cache inferred with byte level write. + -- + CACHEL2 : work.evo_L2cache + generic map ( + addrbits => MAX_L2CACHE_BITS + ) + port map ( + clk => CLK, + memAAddr => std_logic_vector(cacheL2WriteAddr), + memAWriteEnable => cacheL2Write, + memAWriteByte => cacheL2WriteByte, + memAWriteHalfWord => cacheL2WriteHword, + memAWrite => cacheL2WriteData, + memARead => open, + + memBAddr => std_logic_vector(cacheL2Mux2Addr), + memBWrite => (others => '0'), + memBWriteEnable => '0', + memBRead => cacheL2Word + ); + + -- Instruction cache memory. cache instructions from the resync program counter forwards, when we get to a relative or direct + -- jump, if the destination is in cache, read from cache else resync. This speeds up operations where a resync (ie. branch, call etc) would + -- occur, saving cycles. It more especially speeds up the process if using one main bus and the external memory speed is slower than bram. + -- + -- Description of signals: + -- cacheL2StartAddr Absolute Start Address of word in first cache location. + -- cacheL2Active 1 when L2 cache is active, 0 when using dedicated instruction BRAM. + -- cacheL2Empty 1 when cache is empty, 0 when valid data present. + -- cacheL2Invalid 1 when the contents of L2Cache are no longer valid (due to next insn being out of cache scope). + -- cacheL2Mux2Addr Address multiplexer into cache. Address is set to the DebugPC address when the Debug state machine is not idle, all other times it is set to the Next cache fetch address. + -- cacheL2MxAddrInCache When a queued MX Processor address is in the L2 cache, set to 1 else set to 0. Used to determine if a memory write should be written into cache (write thru). + -- cacheL2Full 1 when cache is full, 0 otherwise. + -- + cacheL2Active <= '1' when IMPL_USE_INSN_BUS = false or (IMPL_USE_INSN_BUS = true and pc >= to_unsigned(MAX_INSNRAM_SIZE, pc'length)) + else '0'; + cacheL2Empty <= '1' when cacheL2FetchIdx(ADDR_32BIT_RANGE) = cacheL2StartAddr(ADDR_32BIT_RANGE) + else '0'; +-- cacheL2Invalid <= '1' when pc(ADDR_32BIT_RANGE) < cacheL2StartAddr(ADDR_32BIT_RANGE) or (pc(ADDR_32BIT_RANGE) > cacheL2FetchIdx(ADDR_32BIT_RANGE)) + cacheL2Invalid <= '0' when pc(ADDR_32BIT_RANGE) >= cacheL2StartAddr(ADDR_32BIT_RANGE) and pc(ADDR_32BIT_RANGE) < cacheL2FetchIdx(ADDR_32BIT_RANGE) + else '1'; + cacheL2Mux2Addr <= cacheL1FetchIdx(L2CACHE_32BIT_RANGE) when DEBUG_CPU = false or (DEBUG_CPU = true and debugState = Debug_Idle) + else + debugPC(L2CACHE_32BIT_RANGE) when DEBUG_CPU = true + else + (others => 'X'); + cacheL2MxAddrInCache <= '1' when (to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)), cacheL2StartAddr'length) >= cacheL2StartAddr and to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)), cacheL2FetchIdx'length) < cacheL2FetchIdx) and (IMPL_USE_INSN_BUS = false or (IMPL_USE_INSN_BUS = true and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= MAX_INSNRAM_SIZE)) + else '0'; + cacheL2Full <= '1' when cacheL2FetchIdx(ADDR_32BIT_RANGE) - cacheL2StartAddr(ADDR_32BIT_RANGE) = MAX_L2CACHE_SIZE / 4 + else '0'; + + cacheL2InsnAfterPC <= cacheL2FetchIdx - pc when cacheL2Invalid = '0' + else to_unsigned(0, cacheL2InsnAfterPC'length); + --------------------------------------------- + -- End of Cache storage. + --------------------------------------------- + + ------------------------------------ + -- Memory transaction processor MXP. + ------------------------------------ + -- The mxp localises all memory/io operations into a single process. This aids in adaptation to differing bus topolgies as only this process + -- needs updating (the local INSN bus uses a direct BRAM/ROM connection and bypasses the MXP). This logic processes a queue of transactions in fifo + -- order and fetches instructions as required.. The processor unit commits requests to the queue and this logic fulfills them. If the CPU is only + -- using one bus for all memory and IO operations then memory transactions in the queue are completed before instruction fetches. If the instruction + -- queue is empty then the processor will stall until instructions are fetched. + -- + MEMXACT: process(CLK, ZPURESET, TOS, NOS, debugState) + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if ZPURESET = '1' then + MEM_WRITE_BYTE <= '0'; + MEM_WRITE_HWORD <= '0'; + MEM_READ_ENABLE <= '0'; + MEM_WRITE_ENABLE <= '0'; + WB_ADR_O(ADDR_32BIT_RANGE) <= (others => '0'); + WB_DAT_O <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '0'; + WB_STB_O <= '0'; + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + wbXactActive <= '0'; + cacheL2Write <= '0'; + cacheL2IncAddr <= '0'; + cacheL2FetchIdx <= (others => '0'); + cacheL2StartAddr <= (others => '0'); + mxFifoReadIdx <= (others => '0'); + mxState <= MemXact_Idle; + mxTOS <= ((others => '0'), '0'); + mxNOS <= ((others => '0'), '0'); + mxHoldCycles <= 0; + if DEBUG_CPU = true then + mxMemVal.valid <= '0'; + end if; + + ------------------------ + -- FALLING CLOCK EDGE -- + ------------------------ + elsif falling_edge(CLK) then + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(CLK) then + + -- If the hold cycle counter is not 0, then we are holding on the current transaction until it reaches zero, so decrement + -- ready to test next cycle. This mechanism is to prolong a memory cycle as without it, address setup and hold is 1 cycle and + -- valid data is expected at the end of the cycle. ie. the address and control signals are set on the current rising edge and become + -- active shortly thereafter and on the next rising edge the data is expected to be valid, few components (ie. register ram) can meet + -- this timing requirement. + if mxHoldCycles > 0 then + mxHoldCycles <= mxHoldCycles - 1; + end if; + + -- TOS/NOS values read in by the MXP are only valid for 1 cycle, so reset the valid flag. + mxTOS.valid <= '0'; + mxNOS.valid <= '0'; + + -- Memory signals are one clock width wide unless extended by a wait, if no wait, reset them to inactive to ensure this. + if MEM_BUSY = '0' then + MEM_READ_ENABLE <= '0'; + MEM_WRITE_ENABLE <= '0'; + + -- Width signals are one clock width wide unless extended by a wait signal. + MEM_WRITE_BYTE <= '0'; + MEM_WRITE_HWORD <= '0'; + end if; + + -- Complete any active cache memory writes. + if cacheL2Write = '1' and mxHoldCycles = 0 then + cacheL2Write <= '0'; + cacheL2WriteByte <= '0'; + cacheL2WriteHword <= '0'; + + -- Once the cache write is complete, we update the address if needed, which will be setup in time for the next word to be read in from external memory. + if cacheL2IncAddr = '1' then + cacheL2IncAddr <= '0'; + + -- Update the address from where we fetch the next instruction, 32bit aligned 4 bytes. + cacheL2FetchIdx <= cacheL2FetchIdx + wordBytes; + end if; + end if; + + -- If wishbone interface is active and an ACK is received, deassert the signals. + if IMPL_USE_WB_BUS = true and wbXactActive = '1' and WB_ACK_I = '1' and WB_HALT_I = '0' and mxHoldCycles = 0 then + wbXactActive <= '0'; + WB_WE_O <= '0'; + WB_CYC_O <= '0'; + WB_STB_O <= '0'; + end if; + + -- TODO: WB_ERR_I needs better handling, should retry at least once and then issue a BREAK. + if IMPL_USE_WB_BUS = true and WB_ERR_I = '1' then + wbXactActive <= '0'; + WB_WE_O <= '0'; + WB_CYC_O <= '0'; + WB_STB_O <= '0'; + end if; + + -- If the external memory is busy (1) or the wishbone interface is active and no ACK received then we have to back off and wait till next clock cycle and check again. + if mxHoldCycles = 0 and MEM_BUSY = '0' and ((IMPL_USE_WB_BUS = true and ((wbXactActive = '1' and WB_ACK_I = '1') or wbXactActive = '0')) or IMPL_USE_WB_BUS = false) then + + -- Memory transaction processor state machine. Idle is the control state and depending upon entries in the queue, debug or L2 usage, it + -- directs the FSM states accordingly. + case mxState is + when MemXact_Idle => + -- If there are no memory transactions to complete, debugging is enabled and the debug outputter is active, read the memory location + -- according to the given index. + if DEBUG_CPU = true and (mxFifoWriteIdx - mxFifoReadIdx) = 0 and (debugState /= Debug_Idle and debugState /= Debug_DumpL1 and debugState /= Debug_DumpL2 and debugState /= Debug_DumpMem) then + if IMPL_USE_WB_BUS = true and debugPC(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(debugPC(ADDR_32BIT_RANGE)); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxHoldCycles <= 1; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(debugPC(ADDR_32BIT_RANGE)); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE <= '1'; + end if; + mxMemVal.valid <= '0'; + mxState <= MemXact_MemoryFetch; + + -- If instruction queue is empty or there are no memory transactions to process and the instruction queue isnt full, + -- read the next instruction and fill the instruction queue. + --elsif cacheL2Active = '1' and (mxFifoWriteIdx - mxFifoReadIdx) = 0 and cacheL2Invalid = '0' and cacheL2Full = '0' and cacheL2IncAddr = '0' then + --elsif cacheL2Active = '1' and (mxFifoWriteIdx - mxFifoReadIdx) = 0 and cacheL2Invalid = '0' and cacheL2Full = '0' and cacheL2IncAddr = '0' then + elsif cacheL2Active = '1' and (mxFifoWriteIdx - mxFifoReadIdx) = 0 and cacheL2Full = '0' and cacheL2IncAddr = '0' then + if IMPL_USE_WB_BUS = true and cacheL2FetchIdx(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL2FetchIdx(ADDR_32BIT_RANGE)); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxHoldCycles <= 1; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL2FetchIdx(ADDR_32BIT_RANGE)); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE <= '1'; + mxHoldCycles <= 1; + end if; + cacheL2WriteAddr <= cacheL2FetchIdx(L2CACHE_BIT_RANGE); + mxState <= MemXact_OpcodeFetch; + + -- If there is an item on the queue and the memory system isnt busy from a previous operation, process + -- the queue item. + -- + elsif (mxFifoWriteIdx - mxFifoReadIdx) > 0 then + + -- Setup the address from the queue element and process the command. + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + end if; + mxHoldCycles <= 1; + + case mxFifo(to_integer(mxFifoReadIdx)).cmd is + -- Read to TOS + when MX_CMD_READTOS => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_TOS; + + -- Read to NOS + when MX_CMD_READNOS => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_NOS; + + -- Read both TOS and NOS (save cycles). + when MX_CMD_READTOSNOS => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_TOSNOS; + + -- Read Byte to TOS + when MX_CMD_READBYTETOTOS => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_ReadByteToTOS; + + -- Read Word to TOS + when MX_CMD_READWORDTOTOS => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_ReadWordToTOS; + + -- Read word and add to TOS + when MX_CMD_READADDTOTOS => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_ReadAddToTOS; + + -- Write value to address + when MX_CMD_WRITE => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_DAT_O <= mxFifo(to_integer(mxFifoReadIdx)).data; + WB_WE_O <= '1'; + wbXactActive <= '1'; + else + MEM_DATA_OUT <= mxFifo(to_integer(mxFifoReadIdx)).data; + MEM_WRITE_ENABLE <= '1'; + end if; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_BIT_RANGE)); + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + mxState <= MemXact_Idle; + mxHoldCycles <= 0; + + -- Read value at address, then write data to the value's address. + when MX_CMD_WRITETOINDADDR => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_WE_O <= '0'; + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_WriteToAddr; + + -- To write a byte, if hardware supports it, write out to the byte aligned address with data in bits 7-0 otherwise + -- we first read the 32bit word, update it and write it back. + when MX_CMD_WRITEBYTETOADDR => + -- If Hardware byte write not implemented or it is a write to the Startup ROM we have to resort + -- to a read-modify-write operation. + if IMPL_HW_BYTE_WRITE = false + then + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_32BIT_RANGE)) & "00"; + mxState <= MemXact_WriteByteToAddr; + else + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_DAT_O <= (others => 'X'); + case mxFifo(to_integer(mxFifoReadIdx)).addr(1 downto 0) is + when "00" => + WB_SEL_O <= "1000"; + WB_DAT_O(31 downto 24) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + when "01" => + WB_SEL_O <= "0100"; + WB_DAT_O(23 downto 16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + when "10" => + WB_SEL_O <= "0010"; + WB_DAT_O(15 downto 8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + when "11" => + WB_SEL_O <= "0001"; + WB_DAT_O(7 downto 0) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + end case; + + WB_ADR_O(ADDR_32BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0)<= (others => '0'); + WB_WE_O <= '1'; + wbXactActive <= '1'; + else + MEM_ADDR(ADDR_BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_BIT_RANGE); + MEM_WRITE_ENABLE <= '1'; + MEM_DATA_OUT <= X"000000" & mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0); + MEM_WRITE_BYTE <= '1'; + end if; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + mxHoldCycles <= 0; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_BIT_RANGE)); + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2WriteByte <= '1'; + cacheL2Write <= '1'; + end if; + end if; + + -- To write a word, if hardware supports it, write out to the word aligned address with data in bits 15-0 otherwise + -- we first read the 32bit word, update it and write it back. + when MX_CMD_WRITEHWORDTOADDR => + -- If Hardware half-word write not implemented or it is a write to the Startup ROM we have to resort + -- to a read-modify-write operation. + if IMPL_HW_WORD_WRITE = false + then + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_32BIT_RANGE)) & "00"; + mxState <= MemXact_WriteHWordToAddr; + else + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_DAT_O <= (others => 'X'); + case mxFifo(to_integer(mxFifoReadIdx)).addr(1) is + when '0' => + WB_SEL_O <= "1100"; + WB_DAT_O(31 downto 16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + when '1' => + WB_SEL_O <= "0011"; + WB_DAT_O(15 downto 0) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + end case; + WB_ADR_O(ADDR_32BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0)<= (others => '0'); + WB_WE_O <= '1'; + wbXactActive <= '1'; + else + MEM_ADDR(ADDR_BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_16BIT_RANGE) & "0"; + MEM_WRITE_ENABLE <= '1'; + MEM_DATA_OUT <= X"0000" & mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0); + MEM_WRITE_HWORD <= '1'; + end if; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_BIT_RANGE)); + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2WriteHword <= '1'; + cacheL2Write <= '1'; + end if; + mxHoldCycles <= 0; + end if; + + when others => + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end case; + end if; + + when MemXact_MemoryFetch => + if DEBUG_CPU = true then + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxMemVal.word <= unsigned(WB_DAT_I); + else + mxMemVal.word <= unsigned(MEM_DATA_IN); + end if; + mxMemVal.valid <= '1'; + end if; + mxState <= MemXact_Idle; + + when MemXact_OpcodeFetch => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + cacheL2WriteData <= WB_DAT_I; + else + cacheL2WriteData <= MEM_DATA_IN; + end if; + +--mxHoldCycles <= 1; + -- Initiate a cache memory write. + cacheL2Write <= '1'; + cacheL2IncAddr <= '1'; + mxState <= MemXact_Idle; + + when MemXact_TOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word <= unsigned(WB_DAT_I); + else + mxTOS.word <= unsigned(MEM_DATA_IN); + end if; + mxTOS.valid <= '1'; + if cacheL2Active = '1' then + mxHoldCycles <= 1; + end if; + mxState <= MemXact_Idle; + + when MemXact_NOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxNOS.word <= unsigned(WB_DAT_I); + else + mxNOS.word <= unsigned(MEM_DATA_IN); + end if; + mxNOS.valid <= '1'; + if cacheL2Active = '1' then + mxHoldCycles <= 1; + end if; + mxState <= MemXact_Idle; + + when MemXact_TOSNOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word <= unsigned(WB_DAT_I); + else + mxTOS.word <= unsigned(MEM_DATA_IN); + MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE))) + 1, ADDR_32BIT_SIZE)); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE <= '1'; + mxHoldCycles <= 1; + end if; + mxTOS.valid <= '1'; + mxState <= MemXact_TOSNOS_2; + + when MemXact_TOSNOS_2 => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE))) + 1, ADDR_32BIT_SIZE)); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxState <= MemXact_TOSNOS_3; + else + mxNOS.word <= unsigned(MEM_DATA_IN); + mxNOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + if cacheL2Active = '1' then + mxHoldCycles <= 1; + end if; + + when MemXact_TOSNOS_3 => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxNOS.word <= unsigned(WB_DAT_I); + mxNOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + + when MemXact_ReadByteToTOS => + mxTOS.word <= (others => '0'); + if wbXactActive = '1' then + mxTOS.word(7 downto 0) <= unsigned(WB_DAT_I(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8)); + else + mxTOS.word(7 downto 0) <= unsigned(MEM_DATA_IN(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8)); + end if; + mxTOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_ReadWordToTOS => + mxTOS.word <= (others => '0'); + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word(15 downto 0) <= unsigned(WB_DAT_I(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16)); + else + mxTOS.word(15 downto 0) <= unsigned(MEM_DATA_IN(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16)); + end if; + mxTOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_ReadAddToTOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word <= muxTOS.word + unsigned(WB_DAT_I); + else + mxTOS.word <= muxTOS.word + unsigned(MEM_DATA_IN); + end if; + mxTOS.valid <= '1'; + mxState <= MemXact_Idle; + + when MemXact_WriteToAddr => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= WB_DAT_I(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_DAT_O <= mxFifo(to_integer(mxFifoReadIdx)).data; + WB_WE_O <= '1'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + cacheL2WriteAddr <= unsigned(WB_DAT_I(L2CACHE_BIT_RANGE)); + else + MEM_ADDR(ADDR_32BIT_RANGE) <= MEM_DATA_IN(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_DATA_OUT <= mxFifo(to_integer(mxFifoReadIdx)).data; + MEM_WRITE_ENABLE <= '1'; + cacheL2WriteAddr <= unsigned(MEM_DATA_IN(L2CACHE_BIT_RANGE)); + end if; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_WriteByteToAddr => + -- For wishbone, we need to store the data and terminate the current cycle before we can commence a write cycle. + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + WB_DAT_O <= WB_DAT_I; + WB_DAT_O(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + cacheL2WriteData <= WB_DAT_I; + mxState <= MemXact_WriteByteToAddr2; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_DATA_OUT <= MEM_DATA_IN; + MEM_DATA_OUT(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + MEM_WRITE_ENABLE <= '1'; + cacheL2WriteData <= MEM_DATA_IN; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + -- If the data write is to a cached location, we have read the original value, so update cache with modified version. + if cacheL2MxAddrInCache = '1' then + -- Update the data to write with the actual changed byte, + cacheL2WriteData(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + + when MemXact_WriteByteToAddr2 => + if IMPL_USE_WB_BUS = true then + WB_ADR_O(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '1'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + + when MemXact_WriteHWordToAddr => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + WB_DAT_O <= WB_DAT_I; + WB_DAT_O(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + cacheL2WriteData <= WB_DAT_I; + mxState <= MemXact_WriteHWordToAddr2; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_DATA_OUT <= MEM_DATA_IN; + MEM_DATA_OUT(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + cacheL2WriteData <= MEM_DATA_IN; + MEM_WRITE_ENABLE <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + -- If the data write is to a cached location, we have read the original value, so update cache with modified version. + if cacheL2MxAddrInCache = '1' then + -- Update the data to write with the actual changed byte, + cacheL2WriteData(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + + when MemXact_WriteHWordToAddr2 => + if IMPL_USE_WB_BUS = true then + WB_ADR_O(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '1'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + + when others => + end case; + end if; + + -- Instruction Level 2 cache, we read upto the limit then back off until the gap between executed and read instructions + -- gets to a watermark and then re-enable reading. This allows the cache to maintain a set of past and future instructions so that when a + -- branch or call occurs, there is a chance we already have the needed instructions in cache. + -- + if cacheL2Active = '1' then + + -- If L2 fetching has been halted and the PC approaches the threshold (detault 3/4) then advance the Start Address of L2 data and re-enable L2 filling. + if cacheL2FetchIdx(ADDR_32BIT_RANGE) > pc(ADDR_32BIT_RANGE) and pc(ADDR_32BIT_RANGE) > cacheL2StartAddr(ADDR_32BIT_RANGE) and (pc - cacheL2StartAddr) > ((MAX_L2CACHE_SIZE/4)*3) and cacheL2Full = '1' then + cacheL2StartAddr <= cacheL2StartAddr + 16; + end if; + + -- If the PC goes out of scope of L2 data, reset and start fetching a fresh from the current PC address. + if cacheL2Invalid = '1' and cacheL2Empty = '0' then + cacheL2FetchIdx <= pc(ADDR_32BIT_RANGE) & "00"; + cacheL2StartAddr <= pc(ADDR_32BIT_RANGE) & "00"; + cacheL2Write <= '0'; + cacheL2IncAddr <= '0'; + if (mxFifoWriteIdx - mxFifoReadIdx) = 0 and (mxState = MemXact_Idle or mxState = MemXact_OpcodeFetch) then + mxState <= MemXact_Idle; + end if; + end if; + end if; + end if; + end process; + + -- Use a mux to get the latest TOS/NOS values. This saves 1 clock cycle between data being retrieved and processed. + muxTOS.valid <= mxTOS.valid or TOS.valid; + muxTOS.word <= mxTOS.word when mxTOS.valid = '1' else TOS.word; + muxNOS.valid <= mxNOS.valid or NOS.valid; + muxNOS.word <= mxNOS.word when mxNOS.valid = '1' else NOS.word; + ----------------------------------------------------------------------------------------------------------------------------------------------------------------- + + ------------------------------------------------------------------------------ + -- L1 Cache + -- + -- L1 cache is a very small closely coupled cache which holds a decoded + -- shadow copy of the L2 cache or the BRAM at the point of execution and a few + -- instructions ahead. It is implemented in logic cells to allow instant + -- random access. This is required to perform instruction optimisation such as + -- multiple IM's and also to allow extended 2+ byte instructions which have + -- almost zero penalty over 1 byte instructions. + ------------------------------------------------------------------------------ + CACHE_LEVEL1: process(CLK, ZPURESET, pc) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable tDecodedOpcode : InsnType; + variable tInsnOffset : unsigned(4 downto 0); + begin + + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if ZPURESET = '1' then + cacheL1StartAddr <= (others => '0'); + cacheL1FetchIdx <= (others => '0'); + l1State <= State_PreSetAddr; + MEM_READ_ENABLE_INSN <= '0'; + MEM_ADDR_INSN <= (others => DontCareValue); + pause <= 0; + + ------------------------ + -- FALLING CLOCK EDGE -- + ------------------------ + elsif falling_edge(CLK) then + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(CLK) then + + if pause > 0 then + pause <= pause - 1; + end if; + + -- If the cache becomes invalid due to a change in the PC or no cached data available then resync. + if (cacheL1Invalid = '1' and cacheL1Empty = '0') then + + +-- elsif pc(ADDR_32BIT_RANGE) >= cacheL1StartAddr(ADDR_32BIT_RANGE) and pc(ADDR_32BIT_RANGE) < cacheL1FetchIdx(ADDR_32BIT_RANGE) + + -- RESYNC L1 Cache with BRAM/L2 Cache starting at current PC value.. + cacheL1FetchIdx <= pc(ADDR_32BIT_RANGE) & "00"; + cacheL1StartAddr <= pc(ADDR_32BIT_RANGE) & "00"; + + -- For BRAM preset the next address. + if cacheL2Active = '0' then + MEM_ADDR_INSN(ADDR_32BIT_RANGE) <= std_logic_vector(pc(ADDR_32BIT_RANGE)); + MEM_ADDR_INSN(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE_INSN <= '1'; + --else for L2 the address is automatically set in cacheL1FetchIdx + end if; + + -- State machine goes directly to the latch address phase. + l1State <= State_LatchAddrPause; + + -- WHat the issue will be is the L2 cache is being filled correctly from the SDRAM but it is taking too long for the L1 which is expecting the data + -- thus need to see what signal it has to wait for and add in. +-- if pc >= X"00010000" then +-- pause <= 2047; +-- end if; + + -- If there is space in the L1 cache and data is available in the L2 cache/BRAM and we are not outputting debug information, fetch the next word, decode and place in L1. + elsif cacheL1Full = '0' + and + -- If BRAM ensure the memory is ready, for L2 no need to wait as the pointers control the reading of L2 data. + ((cacheL2Active = '0' and MEM_BUSY_INSN = '0') or (cacheL2Active = '1')) + and + -- If using L2 cache then only process when cached data is available in L2. + -- (cacheL2Active = '0' or (cacheL2Active = '1' and cacheL2Empty = '0' and MEM_BUSY = '0' and cacheL1StartAddr(ADDR_32BIT_RANGE) >= cacheL2StartAddr(ADDR_32BIT_RANGE) and cacheL2FetchIdx(ADDR_32BIT_RANGE) > cacheL1FetchIdx(ADDR_32BIT_RANGE)+1 )) -- and cacheL2Full = '1' )) --cacheL2FetchIdx(ADDR_32BIT_RANGE) > cacheL2StartAddr(ADDR_32BIT_RANGE)+16 )) + (cacheL2Active = '0' or (cacheL2Active = '1' and cacheL2InsnAfterPC > 8 and MEM_BUSY = '0' and cacheL1StartAddr(ADDR_32BIT_RANGE) >= cacheL2StartAddr(ADDR_32BIT_RANGE) and cacheL2FetchIdx(ADDR_32BIT_RANGE) > cacheL1FetchIdx(ADDR_32BIT_RANGE)+1 )) + + and + -- If debugging, only process if the debug FSM is idle as the L2 address is muxed with the debug address. + ((DEBUG_CPU = false or (DEBUG_CPU = true and debugState = Debug_Idle))) then + + + case l1State is + when State_PreSetAddr => + -- For BRAM, set the address to read, external memory via L2 cache is set by the cacheL1FetchIdx signal. + if cacheL2Active = '0' then + MEM_ADDR_INSN(ADDR_32BIT_RANGE) <= std_logic_vector(pc(ADDR_32BIT_RANGE)); + MEM_ADDR_INSN(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE_INSN <= '1'; + --else for L2 the address is automatically set in cacheL1FetchIdx + end if; + l1State <= State_LatchAddr; + + when State_LatchAddrPause => + if pause = 0 then + l1State <= State_Decode; + end if; + + -- This state gives time for the BRAM/L2 to latch the address ready for decode. + when State_LatchAddr => + l1State <= State_Decode; + + when State_Decode => + -- Read cycle for BRAM is at least one clock, so on next cycle clear the BRAM read signal. + if cacheL2Active = '0' then + MEM_READ_ENABLE_INSN <= '0'; + -- else for L2 there is no distinct signal, always outputs data for given input address. + end if; + + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + if cacheL2Active = '0' then + tOpcode := MEM_DATA_IN_INSN((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + else + tOpcode := cacheL2Word((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + end if; + + tInsnOffset(4) := not tOpcode(4); + tInsnOffset(3 downto 0) := unsigned(tOpcode(3 downto 0)); + + if (tOpcode(7 downto 7) = OpCode_Im) then tDecodedOpcode := Insn_Im; + + elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then tDecodedOpcode := Insn_StoreSP; + + elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then tDecodedOpcode := Insn_LoadSP; + + -- Emulated instructions, if there is no defined state to handle the instruction in hardware then it automatically runs the instruction + -- microcode from the vector 0x0+xxxxx*32. + elsif (tOpcode(7 downto 5) = OpCode_Emulate) then tDecodedOpcode := Insn_Emulate; + + if tOpcode(5 downto 0) = OpCode_Neqbranch then tDecodedOpcode := Insn_Neqbranch; + elsif tOpcode(5 downto 0) = OpCode_Eqbranch then tDecodedOpcode := Insn_Eqbranch; + elsif IMPL_EQ = true and tOpcode(5 downto 0) = OpCode_Eq then tDecodedOpcode := Insn_Eq; + elsif tOpcode(5 downto 0) = OpCode_Lessthan then tDecodedOpcode := Insn_Lessthan; + elsif tOpcode(5 downto 0) = OpCode_Lessthanorequal then tDecodedOpcode := Insn_Lessthanorequal; + elsif tOpcode(5 downto 0) = OpCode_Ulessthan then tDecodedOpcode := Insn_Ulessthan; + elsif tOpcode(5 downto 0) = OpCode_Ulessthanorequal then tDecodedOpcode := Insn_Ulessthanorequal; + elsif IMPL_LOADB = true and tOpcode(5 downto 0) = OpCode_Loadb then tDecodedOpcode := Insn_Loadb; + elsif IMPL_LOADH = true and tOpcode(5 downto 0) = OpCode_Loadh then tDecodedOpcode := Insn_Loadh; + elsif IMPL_MULT = true and tOpcode(5 downto 0) = OpCode_Mult then tDecodedOpcode := Insn_Mult; + elsif IMPL_STOREB = true and tOpcode(5 downto 0) = OpCode_Storeb then tDecodedOpcode := Insn_Storeb; + elsif IMPL_STOREH = true and tOpcode(5 downto 0) = OpCode_Storeh then tDecodedOpcode := Insn_Storeh; + elsif IMPL_PUSHSPADD = true and tOpcode(5 downto 0) = OpCode_Pushspadd then tDecodedOpcode := Insn_Pushspadd; + elsif IMPL_CALLPCREL = true and tOpcode(5 downto 0) = OpCode_Callpcrel then tDecodedOpcode := Insn_Callpcrel; + elsif IMPL_CALL = true and tOpcode(5 downto 0) = OpCode_Call then tDecodedOpcode := Insn_Call; + elsif IMPL_SUB = true and tOpcode(5 downto 0) = OpCode_Sub then tDecodedOpcode := Insn_Sub; + elsif IMPL_POPPCREL = true and tOpcode(5 downto 0) = OpCode_PopPCRel then tDecodedOpcode := Insn_PopPCRel; + elsif IMPL_LSHIFTRIGHT = true and tOpcode(5 downto 0) = OpCode_Lshiftright then tDecodedOpcode := Insn_Alshift; + elsif IMPL_ASHIFTLEFT = true and tOpcode(5 downto 0) = OpCode_Ashiftleft then tDecodedOpcode := Insn_Alshift; + elsif IMPL_ASHIFTRIGHT = true and tOpcode(5 downto 0) = OpCode_Ashiftright then tDecodedOpcode := Insn_Alshift; + elsif IMPL_XOR = true and tOpcode(5 downto 0) = OpCode_Xor then tDecodedOpcode := Insn_Xor; + elsif IMPL_DIV = true and tOpcode(5 downto 0) = OpCode_Div then tDecodedOpcode := Insn_Div; + elsif IMPL_MOD = true and tOpcode(5 downto 0) = OpCode_Mod then tDecodedOpcode := Insn_Mod; + elsif IMPL_NEG = true and tOpcode(5 downto 0) = OpCode_Neg then tDecodedOpcode := Insn_Neg; + elsif IMPL_NEQ = true and tOpcode(5 downto 0) = OpCode_Neq then tDecodedOpcode := Insn_Neq; + elsif IMPL_FIADD32 = true and tOpcode(5 downto 0) = OpCode_FiAdd32 then tDecodedOpcode := Insn_FiAdd32; + elsif IMPL_FIDIV32 = true and tOpcode(5 downto 0) = OpCode_FiDiv32 then tDecodedOpcode := Insn_FiDiv32; + elsif IMPL_FIMULT32 = true and tOpcode(5 downto 0) = OpCode_FiMult32 then tDecodedOpcode := Insn_FiMult32; + + end if; + + elsif (tOpcode(7 downto 4) = OpCode_AddSP) then + if tInsnOffset = 0 then tDecodedOpcode := Insn_Shift; + elsif tInsnOffset = 1 then tDecodedOpcode := Insn_AddTop; + else tDecodedOpcode := Insn_AddSP; + end if; + + -- Extended multibyte instruction set. If the extend instruction is encountered then during the execution phase the lookahead mechanism is used to determine + -- the extended instruction and execute accordingly. + elsif IMPL_EXTENDED_INSN = true and tOpcode(3 downto 0) = Opcode_Extend then tDecodedOpcode := Insn_Extend; + + else + case tOpcode(3 downto 0) is + when OpCode_Nop => tDecodedOpcode := Insn_Nop; + when OpCode_PushSP => tDecodedOpcode := Insn_PushSP; + when OpCode_PopPC => tDecodedOpcode := Insn_PopPC; + when OpCode_Add => tDecodedOpcode := Insn_Add; + when OpCode_Or => tDecodedOpcode := Insn_Or; + when OpCode_And => tDecodedOpcode := Insn_And; + when OpCode_Load => tDecodedOpcode := Insn_Load; + when OpCode_Not => tDecodedOpcode := Insn_Not; + when OpCode_Flip => tDecodedOpcode := Insn_Flip; + when OpCode_Store => tDecodedOpcode := Insn_Store; + when OpCode_PopSP => tDecodedOpcode := Insn_PopSP; + when others => tDecodedOpcode := Insn_Break; + end case; + end if; + + -- Store the decoded op directly into L1 cache. + cacheL1(to_integer(cacheL1FetchIdx+i))(DECODED_RANGE) <= std_logic_vector(to_unsigned(InsnType'POS(tDecodedOpcode), 6)); + cacheL1(to_integer(cacheL1FetchIdx+i))(OPCODE_RANGE) <= tOpcode; + end loop; + + -- Set address for next read, via cacheL1FetchIdx for L2 and external signals for BRAM. NB cacheL1FetchIdx always points to the next + -- available slot except during this state of the decoder. + cacheL1FetchIdx <= cacheL1FetchIdx + wordBytes; + + -- If we are not using L2 cache then take instructions direct from instruction BRAM. If a seperate + -- Instruction BRAM is not implemented, this will be ignored as L2 is our only source. + -- + if cacheL2Active = '0' then + MEM_ADDR_INSN(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL1FetchIdx(ADDR_32BIT_RANGE)+1); + MEM_ADDR_INSN(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE_INSN <= '1'; + --else for L2 the address is automatically set in cacheL1FetchIdx + end if; + + -- Repeat the fetch and decode until the L1 cache is full then disable fetching until a space becomes available. + -- We halt just before the full mark because it takes one cycle to halt. + l1State <= State_LatchAddr; + + when others => + l1State <= State_PreSetAddr; + end case; + + -- If there is only a set number of instructions remaining in the cache then we need to creep the start address forward so that + -- more instructions are fetched and decoded. We do this to ensure as many past instructions are available for backward jumps which + -- are most common in C. Adjust the threshold if forward jumps are more common. + elsif cacheL1InsnAfterPC < 8 and cacheL1Full = '1' then + cacheL1StartAddr <= cacheL1StartAddr + 8; + end if; + end if; + end process; + + -- Description of signals: + -- cacheL1StartAddr Absolute Start Address of word in first cache location. + -- cacheL1FetchIdx Next location a decoded instruction set (4 instructions) will be written into. + -- cacheL1InsnAfterPC Number of instructions stored in cache forward of current PC. + -- cacheL1Empty 1 when cache is empty, 0 when valid data present. + -- cacheL1Invalid 1 when cache doesnt have any valid instructions stored. + -- cacheL1Full 1 when cache is full, 0 otherwise. + -- + cacheL1InsnAfterPC <= cacheL1FetchIdx - pc when cacheL1Invalid = '0' + else to_unsigned(0, cacheL1InsnAfterPC'length); + cacheL1Empty <= '1' when cacheL1FetchIdx(ADDR_32BIT_RANGE) = cacheL1StartAddr(ADDR_32BIT_RANGE) + else '0'; + --cacheL1Invalid <= '0' when (cacheL2Active = '0' or (cacheL2Active = '1' and cacheL2Invalid = '0')) and pc(ADDR_32BIT_RANGE) >= cacheL1StartAddr(ADDR_32BIT_RANGE) and pc(ADDR_32BIT_RANGE) < cacheL1FetchIdx(ADDR_32BIT_RANGE) + cacheL1Invalid <= '0' when (cacheL2Active = '0' or (cacheL2Active = '1' and cacheL2InsnAfterPC > 8)) and pc(ADDR_32BIT_RANGE) >= cacheL1StartAddr(ADDR_32BIT_RANGE) and pc(ADDR_32BIT_RANGE) < cacheL1FetchIdx(ADDR_32BIT_RANGE) + else '1'; + cacheL1Full <= '1' when cacheL1FetchIdx(ADDR_32BIT_RANGE) - cacheL1StartAddr(ADDR_32BIT_RANGE) = MAX_L1CACHE_SIZE / 4 + else '0'; + ------------------------------------------------------------------------------ + -- End of L1 Cache + ------------------------------------------------------------------------------ + + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Processor - Execution unit. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + PROCESSOR: process(CLK, ZPURESET, TOS, NOS, cacheL1, pc, sp, mxTOS, mxNOS, cacheL1FetchIdx, cacheL1StartAddr, cacheL2Active, cacheL2Empty, inBreak) + variable tSpOffset : unsigned(4 downto 0); + variable tIdx : integer range 0 to 3; + variable tInsnExec : std_logic; + variable tShiftCnt : integer range 0 to 31; + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + -- Prepare general stack possibility addresses, ie. Popped, 2xPopped or Pushed. + -- + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + incPC <= pc + 1; + incIncPC <= pc + 2; + inc3PC <= pc + 3; + inc4PC <= pc + 4; + inc5PC <= pc + 5; + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if ZPURESET = '1' then + inBreak <= '0'; + INT_ACK <= '0'; + INT_DONE <= '0'; + tIdx := 0; + tSpOffset := (others => '0'); + state <= State_Init; + sp <= to_unsigned(STACK_ADDR, maxAddrBit)(ADDR_32BIT_RANGE); + pc <= to_unsigned(RESET_ADDR_CPU, pc'LENGTH); + pcLast <= to_unsigned(RESET_ADDR_CPU, pc'LENGTH); + idimFlag <= '0'; + inInterrupt <= '0'; + mxFifoWriteIdx <= (others => '0'); + interruptSuspendedAddr <= (others => '0'); + TOS <= ((others => '0'), '0'); + NOS <= ((others => '0'), '0'); + -- + if IMPL_DIV = true or IMPL_FIDIV32 = true or IMPL_MOD = true then + divStart <= '0'; + divQuotientFractional <= 0; + end if; + if IMPL_FIADD32 = true or IMPL_FIMULT32 = true then + quotientFractional <= 15; + end if; + if DEBUG_CPU = true then + debugRec <= ZPU_DBG_T_INIT; + debugLoad <= '0'; + debugState <= Debug_Idle; + debugAllInfo <= '0'; + debugPC_StartAddr <= (others => '0'); + debugPC_EndAddr <= (others => '0'); + debugPC_Width <= 32; + debugPC_WidthCounter <= 0; + debugOutputOnce <= '0'; + else + debugPC_StartAddr <= (others => DontCareValue); + debugPC_EndAddr <= (others => DontCareValue); + debugPC_Width <= 32; + debugPC_WidthCounter <= 0; + debugRec <= ZPU_DBG_T_DONTCARE; + debugLoad <= DontCareValue; + debugReady <= DontCareValue; + debugOutputOnce <= DontCareValue; + end if; + + ------------------------ + -- FALLING CLOCK EDGE -- + ------------------------ + elsif falling_edge(CLK) then + + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(CLK) then + + --if DEBUG_CPU = true and debugState = Debug_Idle and pc = X"058be" then + -- debugPC_StartAddr <= X"01fc00"; --to_unsigned(131072-(512*3), debugPC_StartAddr'LENGTH); + -- debugPC_EndAddr <= X"01ff00"; --to_unsigned(131072, debugPC_EndAddr'LENGTH); + -- debugPC_Width <= 4; + -- debugState <= Debug_DumpMem; + --end if; + + if DEBUG_CPU = true and debugState = Debug_Idle and pc = X"1002b67" then --cacheL1FetchIdx < cacheL1FetchIdx_last then + debugState <= Debug_Start; + end if; + + -- In debug mode, the memory dump start and stop address are controlled by 2 vectors, preload them with defaults if uninitialised. + if DEBUG_CPU = true and debugPC_EndAddr = 0 then + debugPC_StartAddr <= to_unsigned(16#0010000#, debugPC_StartAddr'LENGTH); + debugPC_EndAddr <= to_unsigned(16#0010800#, debugPC_EndAddr'LENGTH); + end if; + + -- If the Memory Transaction processor has updated the stack parameters, update our working copy. + -- + if mxTOS.valid = '1' then + TOS.valid <= '1'; + TOS.word <= mxTOS.word; + end if; + if mxNOS.valid = '1' then + NOS.valid <= '1'; + NOS.word <= mxNOS.word; + end if; + + -- If debugging enabled, loading of debug information into the debug serialiser is only 1 clock width wide, reset on each clock tick. + -- + if DEBUG_CPU = true then + debugLoad <= '0'; + end if; + + -- Division start is only 1 clock width wide. + if IMPL_DIV = true or IMPL_FIDIV32 = true or IMPL_MOD = true then + divStart <= '0'; + divQuotientFractional <= 15; -- Always reset the quotient, integer division sets to 0 as no fractional component. + end if; + + -- If interrupt is active, we only clear the interrupt state once the PC is reset to the address which was suspended after the + -- interrupt, this prevents recursive interrupt triggers, desirable in cetain circumstances but not for this current design. + -- + if (INT_REQ = '1' or (IMPL_USE_WB_BUS = true and WB_INTA_I = '1')) and intTriggered = '0' then + intTriggered <= '1'; + end if; + INT_ACK <= '0'; -- Reset interrupt acknowledge if set, width is 1 clock only. + INT_DONE <= '0'; -- Reset interrupt done if set, width is 1 clock only. + if inInterrupt = '1' and pc(ADDR_BIT_RANGE) = interruptSuspendedAddr(ADDR_BIT_RANGE) then + inInterrupt <= '0'; -- no longer in an interrupt + INT_DONE <= '1'; -- Interrupt service routine complete. + end if; + + -- BREAK signal follows internal signal on clock edge. + BREAK <= inBreak; + + ------------------------------------- + -- Execution Processor. + ------------------------------------- + if (DEBUG_CPU = false or (DEBUG_CPU = true and debugReady = '1')) then + + case state is + -- If the emulation cache is implemented, initialise it else startup the CPU. + when State_Init => + state <= State_Idle; + + -- Idle the CPU if ENABLE signal is low. + -- + when State_Idle => + if ENABLE = '1' then + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + + if DEBUG_CPU = true and DEBUG_LEVEL >= 4 and debugState = Debug_Idle then + debugPC_StartAddr <= to_unsigned(0, debugPC_StartAddr'LENGTH); + debugPC_EndAddr <= to_unsigned(65536, debugPC_EndAddr'LENGTH); + debugState <= Debug_DumpMem; + end if; + end if; + + -- Each instruction must: + -- + -- 1. set idimFlag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + when State_Execute => + + -- If the debug state machine is outputting data, hold off from further actions. + if DEBUG_CPU = true and debugState /= Debug_Idle then + + -- When a break is active, all processing is suspended. + elsif inBreak = '1' then + + -- If continue flag set, resume with next instruction. + if CONTINUE = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + inBreak <= '0'; + end if; + + -- Act immediately if an interrupt has occurred. Do not recurse into ISR while interrupt line is active + elsif intTriggered = '1' and inInterrupt = '0' and idimFlag = '0' then + + -- We have to wait for TOS and NOS to become valid so they can be saved, so loop until they are valid. + if muxTOS.valid = '1' and muxNOS.valid = '1' then + -- We got an interrupt, execute interrupt instead of next instruction + intTriggered <= '0'; + inInterrupt <= '1'; + INT_ACK <= '1'; -- Acknowledge interrupt. + interruptSuspendedAddr <= pc(ADDR_BIT_RANGE); -- Save address which got interrupted. + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= pc; + NOS.word <= muxTOS.word; + pc <= to_unsigned(32+START_ADDR_MEM, maxAddrBit); -- Load Vector 0x20 (from memory start) as next address to execute from. + sp <= decSp; + + -- Setup a memory transaction to save NOS back to RAM, TOS in effect already popped. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- If debug enabled, write out state during fetch. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(6, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"494D544552505400"; + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end if; + + -- If the CPU is externally disabled during processing, go to the Idle state and wait until it is re-enabled. + -- + elsif ENABLE = '0' then + state <= State_Idle; + + -- Execution depends on the L1 having decoded instructions stored at the current PC. + -- As a minimum the cache must be valid and that there is at least 1 instruction in the cache. + elsif cacheL1Invalid = '0' then --and cacheL1InsnAfterPC > 4 then + + -- Remember the last PC location executed, used for jump detection. + pcLast <= pc; + + -- Set the stack offset for current instruction from its opcode. + tSpOffset(4) := not cacheL1(to_integer(pc))(4); + tSpOffset(3 downto 0) := unsigned(cacheL1(to_integer(pc)))(3 downto 0); + tInsnExec := '0'; + if DEBUG_CPU = true then + debugOutputOnce <= '0'; + end if; + + -------------------------------------------------------------------------------------------------------------- + -- Start of Instruction Execution Case block - process the current instruction held in L1 Cache. + -------------------------------------------------------------------------------------------------------------- + case InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE)))) is + + -- Immediate, store 7bit signed extended value into TOS. If this is the first Im then we set IDIM, if this is a subsequent Im following + -- on from other Im's without gap, then we shift TOS 7 bits to left and add in the new value. NB. First Im, bit 6 of bits 6-0 is used to set + -- all bits 31 downto 6 with the same value. + -- An optimisation has been added where by if more than 1 Im are sequential and in the L1 cache, then the result is calculated in 1 cycle. If due + -- to not enough cache data a > 1 Im is partially processed, ie. 3 Im out of 5, then the 3 are processed in 1 cycle and the remaining two in seperate + -- cycles. + when Insn_Im => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '1'; + pc <= incPC; + + -- If this is the first Im (single or non-cached) or this is a multi Im instruction, save current TOS and build new TOS from Im. + -- + if idimFlag = '0' then + -- As we are pushing a value, current TOS becomes NOS and we write back old NOS to memory. + NOS.word <= muxTOS.word; + sp <= decSp; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- All Im combinations sign extend the 7th bit of the first Im instruction then just overwrite the bits available. + --if cacheL1(to_integer(pc))(6) = '1' then + -- TOS.word <= "11111111111111111111111110000000"; + --else + -- TOS.word <= (others => '0'); + --end if; + for i in wordSize-1 downto 7 loop + TOS.word(i) <= cacheL1(to_integer(pc))(6); + end loop; + + -- For non-optimised hardware or optimised but we only have 1 Im, use the original logic. + if IMPL_OPTIMIZE_IM = false then + TOS.word(IM_DATA_RANGE) <= unsigned(cacheL1(to_integer(pc))(IM_DATA_RANGE)); + + -- If Im optimisation is enabled, work out if we have sufficient instructions and then determine how many Ims are grouped together, otherwise default to just 1 Im per time processing. + elsif IMPL_OPTIMIZE_IM = true then + + -- Debug code, if enabled, writes out the data relevant to the Im instruction being optimised. + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 and cacheL1FetchIdx(L1CACHE_BIT_RANGE) - pc(L1CACHE_BIT_RANGE) > 2 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA2(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.DATA3(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)); + debugRec.DATA4(63 downto 0) <= "0000000000000000" & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 16)) & std_logic_vector(cacheL2FetchIdx(15 downto 0)) & "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & "0000" & idimFlag & tInsnExec & cacheL2Full & cacheL2Write; + debugRec.OPCODE <= (others => DontCareValue); + debugRec.DECODED_OPCODE <= (others => DontCareValue); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + + -- 5 Consecutive IM's + --if cacheL1FetchIdx - pc > 5 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '1' and cacheL1(to_integer(inc4PC))(7) = '1' and cacheL1(to_integer(inc5PC))(7) = '0' then + if cacheL1InsnAfterPC > 5 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '1' and cacheL1(to_integer(inc4PC))(7) = '1' and cacheL1(to_integer(inc5PC))(7) = '0' then + TOS.word(31 downto 0) <= unsigned(cacheL1(to_integer(pc))(3 downto 0)) & unsigned(cacheL1(to_integer(incPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incIncPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(inc3PC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(inc4PC))(OPCODE_IM_RANGE)); + pc <= inc5PC; + -- 4 Consecutive IM's + --elsif cacheL1FetchIdx - pc > 4 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '1' and cacheL1(to_integer(inc4PC))(7) = '0' then + elsif cacheL1InsnAfterPC > 4 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '1' and cacheL1(to_integer(inc4PC))(7) = '0' then + TOS.word(27 downto 0) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incIncPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(inc3PC))(OPCODE_IM_RANGE)); + pc <= inc4PC; + -- 3 Consecutive IM's + elsif cacheL1InsnAfterPC > 3 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '0' then + TOS.word(20 downto 0) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incIncPC))(OPCODE_IM_RANGE)); + pc <= inc3PC; + -- 2 Consecutive IM's + elsif cacheL1InsnAfterPC > 2 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '0' then + TOS.word(13 downto 0) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incPC))(OPCODE_IM_RANGE)); + pc <= incIncPC; + -- 1 IM + else + TOS.word(IM_DATA_RANGE) <= unsigned(cacheL1(to_integer(pc))(OPCODE_RANGE)(IM_DATA_RANGE)); + end if; + end if; + else + -- Further single Im instructions shift left by 7 bits then add it the value from the current opcode. + TOS.word(wordSize-1 downto 7) <= muxTOS.word(wordSize-8 downto 0); + TOS.word(IM_DATA_RANGE) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)); + end if; + end if; + + -- Store into Stack pointer + offset, write out the value in TOS to the location pointed by Stack pointer plus any offset given in the opcode. + when Insn_StoreSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + tIdx := 0; + idimFlag <= '0'; + sp <= incSp; + pc <= incPC; + + -- Always need to read the new NOS location into NOS unless the offset is 2 when the location will be + -- overwritten with TOS, so just use TOS. + if tSpOffset /= 2 then + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + tIdx := tIdx + 1; + end if; + + -- Write value of TOS to the memory location sp + offset stored in opcode if offset not 0 or 1. + -- + if tSpOffset >= 2 then + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).addr(ADDR_32BIT_RANGE)<= std_logic_vector(sp+tSpOffset); + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).data<= std_logic_vector(muxTOS.word); + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).cmd <= MX_CMD_WRITE; + tIdx := tIdx + 1; + end if; + + case tSpOffset is + -- If the offset is 0, we are writing into unused stack (as the stack pointer is incremented), so just assign + -- NOS to TOS and read the new NOS. + when "00000" => + TOS.word <= muxNOS.word; + + -- If the offset is 1 then we do nothing as a write of TOS to SP+1 is the location of the new TOS, so TOS doesnt change. + -- We read NOS though from the new location. + when "00001" => + + -- When offset is 2, TOS is written to the new NOS position in memory, so no point to reread, we just reuse TOS. + -- + when "00010" => + NOS.word <= muxTOS.word; + TOS.word <= muxNOS.word; + + -- All other cases TOS becomes NOS and we read the new NOS . + -- + when others => + TOS.word <= muxNOS.word; + end case; + + mxFifoWriteIdx <= mxFifoWriteIdx + tIdx; + end if; + + -- Load from Stack pointer + offset: save NOS onto stack (TOS is popped and no longer needed so we are not concerned), read into TOS + -- the value pointed to by the SP + Offset. NOS becomes the old TOS as we virtually pushed the read value onto the stack. + when Insn_LoadSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + sp <= decSp; + pc <= incPC; + + -- Commit NOS to memory as we will refresh NOS from TOS. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- If the offset is 0 then we are duplicating TOS into NOS. + if tSpOffset = 0 then + NOS.word <= muxTOS.word; + + -- If the offset is 1 then we are duplicating NOS into TOS. + elsif tSpOffset = 1 then + TOS.word <= muxNOS.word; + NOS.word <= muxTOS.word; + + -- Else we read the value at Sp + Offset into TOS. + else + -- Read TOS from the location pointed to by SP + Offset. + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_32BIT_RANGE) <= std_logic_vector(sp+tSpOffset); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_READTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + + -- NOS becomes TOS as we are pushing a new value onto the stack. + NOS.word <= muxTOS.word; + end if; + end if; + + -- Emulate. This is a dummy placeholder for instructions which have not been implemented in hardware. If an Opcode cannot be translated to + -- a state machine state, it falls through to here, the NOS is saved back onto the stack, TOS is set to NOS and TOS takes on + -- the next program counter value (ie. next instruction after the one which is not implemented). The Program counter is then set + -- to the vector containing the microcode to implement the instruction and a jump is made to that location. When the microcode is complete it + -- should set the Program counter to the value stored in TOS. + when Insn_Emulate => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + sp <= decSp; + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= incPC; + NOS.word <= muxTOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- The emulate address is calculated by the opcode value left shifted 5 places. If the BRAM start address is not zero then this is added to ensure the + -- emulation microcode is read form the BRAM: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= to_unsigned(to_integer(unsigned(cacheL1(to_integer(pc))(OPCODE_RANGE)(4 downto 0)) & "00000"), pc'LENGTH) + START_ADDR_MEM; + end if; + + -- Call function relative to current PC value. The Program counter for the next instruction after this (ie. call return address) is stored in TOS + -- and the Program counter is set to the value currently in TOS+PC (remember that assignments only occur at end of the cycle, so writing to TOS wont + -- actually happen until the moment we leave this cycle) and we start processing from the new Program counter location, or the called location. + when Insn_Callpcrel => + if IMPL_CALLPCREL = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= incPC; + pc <= pc + muxTOS.word(ADDR_BIT_RANGE); + end if; + end if; + + -- Call function. Same as above except the PC is set to the value stored in TOS, not TOS+PC. + when Insn_Call => + if IMPL_CALL = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= incPC; + pc <= muxTOS.word(ADDR_BIT_RANGE); + end if; + end if; + + -- Add value from location pointed to bye Stack Pointer. Setup to read the value stored at Stack pointer location + offset contained + -- in the OpCode. We then forward to the next state which adds the value read to the value stored in TOS. + when Insn_AddSP => + -- if TOS.valid = '1' and NOS.valid = '1' then + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(sp+tSpOffset); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READADDTOTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Push stack pointer. TOS is set to stack pointer value and old TOS value assigned to NOS. The current NOS value is written out + -- onto the stack. In effect TOS = sp, NOS = TOS and NOS stored to NOS-1, we accomplish a push stack pointer onto the stack. + when Insn_PushSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= decSp; + TOS.word <= (others => '0'); + TOS.word(ADDR_32BIT_RANGE) <= sp; + NOS.word <= muxTOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Pop the value on the stack into the Program counter. This is accomplished by setting the PC to the TOS value, then writing out the + -- NOS value (because NOS and TOS are not normally stored, they are held in register) and performing a resync. + when Insn_PopPC => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= muxTOS.word(ADDR_BIT_RANGE); + sp <= incSp; + TOS.word <= muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Same as above except the program counter is added to the value in TOS before being assigned to the next program counter value. + when Insn_PopPCRel => + if IMPL_POPPCREL = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= pc + muxTOS.word(ADDR_BIT_RANGE); + sp <= incSp; + TOS.word <= muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Add NOS to TOS and store into TOS. NOS is then read from the stack. + when Insn_Add => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxTOS.word + muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Subtract NOS from TOS and store into TOS. NOS is then read from the stack. + when Insn_Sub => + if IMPL_SUB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxNOS.word - muxTOS.word; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform a logical OR between TOS and NOS and store the result in TOS. We then retrieve the next stack value into NOS. + when Insn_Or => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxTOS.word or muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a logical AND between TOS and NOS and store the result in TOS. We then retrieve the next stack value into NOS. + when Insn_And => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxTOS.word and muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a Equal comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next stack value into NOS. + when Insn_Eq => + if IMPL_EQ = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (muxTOS.word = muxNOS.word) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform an unsigned less than comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next stack value into NOS. + when Insn_Ulessthan => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (muxTOS.word < muxNOS.word) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform an unsigned less than or equal comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next + -- stack value into NOS. + when Insn_Ulessthanorequal => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (muxTOS.word <= muxNOS.word) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a signed less than comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next stack value into NOS. + when Insn_Lessthan => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (signed(muxTOS.word) < signed(muxNOS.word)) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a signed less than or equal comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next + -- stack value into NOS. + when Insn_Lessthanorequal => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (signed(muxTOS.word) <= signed(muxNOS.word)) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Load TOS (next cycle) with the value pointed to by TOS. + when Insn_Load => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Write the NOS value to the memory location pointed by TOS. + when Insn_Store => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incIncSp; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE)<= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + + -- Write the NOS value into memory location pointed to by the current Stack Pointer - 1 (ie. next of stack), + -- then set the Stack Pointer to the current TOS value. + when Insn_PopSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= muxTOS.word(ADDR_32BIT_RANGE); + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + + -- No operation, just waste time. + when Insn_Nop => + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + -- Negate the TOS value. + when Insn_Not => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word <= not muxTOS.word; + end if; + + -- Reverse all the bits in the TOS. + when Insn_Flip => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + for i in 0 to wordSize-1 loop + TOS.word(i) <= muxTOS.word(wordSize-1-i); + end loop; + end if; + + -- Add the TOS and NOS together, store in the TOS. + when Insn_AddTop => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word <= muxTOS.word + muxNOS.word; + end if; + + -- Shift the TOS right 1 bit. + when Insn_Shift => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word(wordSize-1 downto 1) <= muxTOS.word(wordSize-2 downto 0); + TOS.word(0) <= '0'; + end if; + + -- Add the TOS to the Stack Pointer and store in TOS. This is word aligned so bits 0 & 1 are zero. + when Insn_Pushspadd => + if IMPL_PUSHSPADD = true then + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word <= (others => '0'); + TOS.word(ADDR_32BIT_RANGE) <= muxTOS.word((maxAddrBit-1)-minAddrBit downto 0)+sp; + end if; + end if; + + -- If the NOS is not 0 (or 0 for Eq) then add the TOS to the Program Counter. As the address is not guaranteed to be sequential, resync to + -- retrieve the new TOS / NOS (because they are both now invalid) and the new program instruction. If the NOS is 0 then just + -- retrieve the new TOS / NOS. + when Insn_Neqbranch | Insn_Eqbranch => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + -- branches are almost always taken as they form loops + idimFlag <= '0'; + sp <= incIncSp; + + if (InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE)))) = Insn_Neqbranch and muxNOS.word /= 0) or (InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE)))) = Insn_Eqbranch and NOS.word = 0) then + pc <= pc + muxTOS.word(ADDR_BIT_RANGE); + else + pc <= incPC; + end if; + + -- need to fetch stack again. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Set in motion a signed multiplication of the TOS * NOS. + when Insn_Mult => + if IMPL_MULT = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_Mult2; + multResult <= muxTOS.word * muxNOS.word; + end if; + end if; + + -- Set in motion a signed division of the TOS / NOS. + when Insn_Div => + if IMPL_DIV = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + divStart <= '1'; + divQuotientFractional <= 0; + state <= State_Div2; + end if; + end if; + + -- Set in motion a fixed point addition of the TOS / NOS. + when Insn_FiAdd32 => + if IMPL_FIADD32 = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_FiAdd2; + end if; + end if; + + -- Set in motion a fixed point division of the TOS / NOS. + when Insn_FiDiv32 => + if IMPL_FIDIV32 = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_FiDiv2; + end if; + end if; + + -- Set in motion a fixed point multiplication of the TOS / NOS. + when Insn_FiMult32 => + if IMPL_FIMULT32 = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_FiMult2; + end if; + end if; + + -- Read the aligned word pointed to by the TOS and then process in the next state to extract just the required byte. + when Insn_Loadb => + if IMPL_LOADB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READBYTETOTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Read the aligned dword pointed to by the TOS and update just the one required byte, + -- The loadb and storeb can be sped up by implementing hardware byte read/write. + when Insn_Storeb => + if IMPL_STOREB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incIncSp; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)+1).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_WRITEBYTETOADDR; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + end if; + + -- Read the aligned dword pointed to by the TOS and then process in the next state to extract just the required word. + when Insn_Loadh => + if IMPL_LOADH = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READWORDTOTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Read the aligned dword pointed to by the TOS and update just the one required word, + -- The loadb and storeb can be sped up by implementing hardware byte read/write. + when Insn_Storeh => + if IMPL_STOREH = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incIncSp; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)+1).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_WRITEHWORDTOADDR; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + end if; + + -- Perform an exclusive or of the TOS and NOS which is stored in TOS in the next state. NOS is read from the + -- new location. + when Insn_Xor => + if IMPL_XOR = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxNOS.word xor muxTOS.word; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform a negation or inverse of the TOS. + when Insn_Neg => + if IMPL_NEG = true then + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + TOS.word <= (not muxTOS.word) + 1; + end if; + end if; + + -- Perform a signed comparison of TOS v NOS, if they are not equal, set the result to 1 which is stored in TOS in the next state. NOS + -- is read from the new memory location. + when Insn_Neq => + if IMPL_NEQ = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (signed(muxTOS.word) /= signed(muxNOS.word)) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform a modulo of TOS v NOS and push to stack. TOS is set to the result and NOS is read from the new stack location. + when Insn_Mod => + if IMPL_MOD = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + divStart <= '1'; + divQuotientFractional <= 0; + state <= State_Mod2; + end if; + end if; + + -- Shift NOS left or right TOS times according to the instruction. The shifting is done by VHDL operators paying attention to + -- shift left arithmetic where the sla operator doesnt give the normal results. + when Insn_Alshift => + if IMPL_ASHIFTLEFT = true or IMPL_ASHIFTRIGHT = true or IMPL_LSHIFTRIGHT = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + + -- Positions to shift stored in TOS. + tShiftCnt := to_integer(unsigned(std_logic_vector(muxTOS.word(4 downto 0)))); + + -- Logical Shift Right + if (muxNOS.word(31) and cacheL1(to_integer(pc))(OPCODE_RANGE)(2)) = '0' and cacheL1(to_integer(pc))(OPCODE_RANGE)(0) = '0' then + if (tShiftCnt = 0) then + TOS.word <= (others => '0'); + else + TOS.word <= unsigned(to_stdlogicvector(to_bitvector(std_logic_vector(muxNOS.word)) srl tShiftCnt)); + end if; + end if; + + -- Arithmetic Shift Right + if (muxNOS.word(31) and cacheL1(to_integer(pc))(OPCODE_RANGE)(2)) = '1' and cacheL1(to_integer(pc))(OPCODE_RANGE)(0) = '0' then + if (tShiftCnt = 0) then -- ASR #32 + TOS.word <= (others => std_logic(muxNOS.word(31))); + else + TOS.word <= unsigned(to_stdlogicvector(to_bitvector(std_logic_vector(muxNOS.word)) sra tShiftCnt)); + end if; + end if; + + -- Arithmetic Shift Left (NB. VHDL sla behaves in a non-standard way, it mirrors sra hence use of sll). + if (muxNOS.word(31) and cacheL1(to_integer(pc))(OPCODE_RANGE)(2)) = '0' and cacheL1(to_integer(pc))(OPCODE_RANGE)(0) = '1' then + if (tShiftCnt = 0) then + TOS.word <= muxNOS.word; + else + TOS.word <= unsigned(to_stdlogicvector(to_bitvector(std_logic_vector(muxNOS.word)) sll tShiftCnt)); + end if; + end if; + + -- Fetch new NOS value. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + -- The ZPU has an 8 bit instruction set which has few spare slots. This intruction allows extended multibyte additions to be coded and processed. + -- The instructions are coded as: Extend,,[,,,] + -- Where ParamSize = 00 - No parameter bytes + -- 01 - 8 bit parameter + -- 10 - 16 bit parameter + -- 11 - 32 bit parameter + -- Thus without any additional data fetches, new instructions have access to 3 parameters, TOS, NOS and the InsnParameter. + -- ie. To create an LDIR, Source=TOS, Dest=NOS and InsnParameter=Count + when Insn_Extend => + -- Ensure L1 cache has sufficient data to process this instruction, otherwise wait until it does before decoding and executing. + if cacheL1FetchIdx - pc > to_integer(unsigned(cacheL1(to_integer(pc)+1)(OPCODE_RANGE)(OPCODE_PARAM_RANGE)))+1 then + tInsnExec := '1'; + + -- For instructions which use a parameter, build the value ready for use. + -- TODO: This should be variables to meet the 1 cycle requirement or set during decode. + case cacheL1(to_integer(pc)+1)(OPCODE_PARAM_RANGE) is + when "00" => insnExParameter <= X"00000000"; + when "01" => insnExParameter <= X"000000" & unsigned(cacheL1(to_integer(pc)+2)(OPCODE_RANGE)); + when "10" => insnExParameter <= X"0000" & unsigned(cacheL1(to_integer(pc)+2)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+3)(OPCODE_RANGE)); + when "11" => insnExParameter <= unsigned(cacheL1(to_integer(pc)+2)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+3)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+4)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+5)(OPCODE_RANGE)); + end case; + + -- Decode the extended instruction at this point as we have access to 8 future instructions or bytes so can work out what is required and execute. + -- 1:0 = 00 means an instruction which operates with a default, byte, half-word or word parameter. ie. Extend,,[,,,] + + -- Memory fill instruction. Fill memory starting at address in NOS with zero, 8 bit, 16 or 32 bit repeating value for TOS bytes. + --if cacheL1(to_integer(pc)+1)(OPCODE_INSN_RANGE) = Opcode_Ex_Fill then + --end if; + + -- Debug code, if enabled, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(5, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"455854454E440000"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end if; + + -- Breakpoint, this is not a nornal instruction and used by debuggers to suspend a program exection. At the moment + -- this instuction sets the BREAK flag and just continues. + when Insn_Break => + tInsnExec := '1'; + report "Break instruction encountered" severity failure; + inBreak <= '1'; + + -- Debug code, if ENABLEd, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"425245414B504E54"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + + -- Dump out the L1, L2 and Memory for debugging. + debugState <= Debug_Start; + end if; + + -- Should never get here, so if debugging enabled, report. + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + inBreak <= '1'; + + -- Debug code, if ENABLEd, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(6, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"494C4C4547414C00"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end case; + + -- During waits, if debug enabled, output state and dump the L1 cache. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 and (pc = X"00010008") then + if debugState = Debug_Idle then + --debugState <= Debug_DumpL2; + debugState <= Debug_Start; + end if; + end if; + + -- Debug code, if enabled, writes out the current instruction. + if ((DEBUG_CPU = true and DEBUG_LEVEL >= 1) or (DEBUG_CPU = true and pc >= X"0000a000")) and tInsnExec = '1' then + --if ((DEBUG_CPU = true and DEBUG_LEVEL >= 1)) and tInsnExec = '1' then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1InsnAfterPC), 16)); + debugRec.DATA2(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 24)) & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 24)) & "10000000" & '0' & cacheL2IncAddr & idimFlag & tInsnExec & cacheL2Full & cacheL2Active & cacheL2Empty & cacheL2Write; + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + else + if DEBUG_CPU = true and debugOutputOnce = '0' then + -- During waits, if debug enabled, output state and dump the L1 cache. + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 and (pc = X"1002b67") then + if debugState = Debug_Idle then + debugState <= Debug_DumpL2; + end if; + end if; + --if (DEBUG_CPU = true and DEBUG_LEVEL >= 1) then + if (DEBUG_CPU = true and DEBUG_LEVEL >= 1) or (DEBUG_CPU = true and pc >= X"0000a000") then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1InsnAfterPC), 16)); + debugRec.DATA2(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 24)) & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 24)) & "00000000" & '0' & cacheL2IncAddr & idimFlag & tInsnExec & cacheL2Full & cacheL2Active & cacheL2Empty & cacheL2Write; + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + debugOutputOnce <= '1'; + end if; + end if; + + -------------------------------------------------------------------------------------------------------------- + -- End of Instruction Execution Case block. + -------------------------------------------------------------------------------------------------------------- + + when State_Mult2 => + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(multResult); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= std_logic_vector(to_unsigned(InsnType'POS(InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE))))) , 6)); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + + TOS.word <= multResult(wordSize-1 downto 0); + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + + when State_Div2 => + if IMPL_DIV = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + + if divStart = '0' and divComplete = '1' then + TOS.word <= unsigned(divResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_Mod2 => + if IMPL_MOD = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divRemainder); + debugLoad <= '1'; + end if; + + if divStart = '0' and divComplete = '1' then + TOS.word <= unsigned(divRemainder(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_FiAdd2 => + if IMPL_FIADD32 = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + if divComplete = '1' and muxTOS.valid = '1' and muxNOS.valid = '1' then + TOS.word <= unsigned(fpAddResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_FiDiv2 => + if IMPL_FIDIV32 = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + if divComplete = '1' and muxTOS.valid = '1' and muxNOS.valid = '1' then + TOS.word <= unsigned(divResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_FiMult2 => + if IMPL_FIMULT32 = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + if divComplete = '1' and muxTOS.valid = '1' and muxNOS.valid = '1' then + TOS.word <= unsigned(fpMultResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + -- Should never reach this state, if debug enabled, output details. + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + inBreak <= '1'; + + -- Debug code, if ENABLEd, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"494C4C4547414C53"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end case; + -------------------------------------------------------------------------------------------------------------- + -- End of Instruction State Case block. + -------------------------------------------------------------------------------------------------------------- + + -- In debug mode, output the current data and the decoded instruction queue. + if DEBUG_CPU = true then + case debugState is + when Debug_Idle => + + when Debug_Start => + + -- Write out the primary data. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)); + debugRec.DATA2(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 16)) & std_logic_vector(cacheL2FetchIdx(15 downto 0)) & "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & "0000" & idimFlag & tInsnExec & cacheL2Full & cacheL2Write; + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + debugAllInfo <= '1'; + + debugState <= Debug_DumpL1; + + when Debug_DumpL1 => + debugPC <= (others => '0'); + debugState <= Debug_DumpL1_1; + + when Debug_DumpL1_1 => + -- Write out the opcode. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_SPLIT_DATA <= "01"; + if debugPC = MAX_L1CACHE_SIZE-(wordBytes*4) then + debugRec.FMT_POST_CRLF <= '1'; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '0'; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.DATA(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+ 0)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 1)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 2)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 3)(INSN_RANGE); + debugRec.DATA2(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+ 4)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 5)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 6)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 7)(INSN_RANGE); + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+ 8)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 9)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+10)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+11)(INSN_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+12)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+13)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+14)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+15)(INSN_RANGE); + if debugPC = 0 then + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(to_unsigned(to_integer(pc), debugRec.PC'LENGTH)); + debugRec.WRITE_PC <= '1'; + else + debugRec.WRITE_PC <= '0'; + end if; + debugLoad <= '1'; + debugState <= Debug_DumpL1_2; + debugPC <= debugPC + (wordBytes * 4); -- 16 instructions are output per loop. + + when Debug_DumpL1_2 => + -- Move onto next opcode in Fifo. + if debugPC = MAX_L1CACHE_SIZE then + if debugAllInfo = '1' then + -- if IMPL_USE_INSN_BUS = true then + -- debugState <= Debug_End; + -- else + debugState <= Debug_DumpL2; + -- end if; + else + debugState <= Debug_End; + end if; + else + debugState <= Debug_DumpL1_1; + end if; + + when Debug_DumpL2 => + debugPC <= (others => '0'); + debugState <= Debug_DumpL2_0; + + -- Wait state at start of dump so initial address gets registered in cache memory and data output. + when Debug_DumpL2_0 => + debugState <= Debug_DumpL2_1; + + -- Output the contents of L2 in the format + when Debug_DumpL2_1 => + -- Write out the opcode. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_SPLIT_DATA <= "01"; + if debugPC = MAX_L2CACHE_SIZE-1 or debugPC(4 downto 2) = "111" then + debugRec.FMT_POST_CRLF <= '1'; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(3, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + if debugPC(4 downto 2) = "000" then + debugRec.WRITE_PC <= '1'; + else + debugRec.WRITE_PC <= '0'; + end if; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(debugPC); + debugRec.DATA(63 downto 32) <= cacheL2Word(31 downto 24) & cacheL2Word(23 downto 16) & cacheL2Word(15 downto 8) & cacheL2Word(7 downto 0); + debugLoad <= '1'; + debugState <= Debug_DumpL2_2; + debugPC <= debugPC + wordBytes; -- 4 instructions are output per loop (limited by memory read into cacheL2Word). + + when Debug_DumpL2_2 => + -- Move onto next opcode in Fifo. + if debugPC = MAX_L2CACHE_SIZE then + if debugAllInfo = '1' then + debugState <= Debug_DumpMem; + else + debugState <= Debug_End; + end if; + else + debugState <= Debug_DumpL2_1; + end if; + + when Debug_DumpMem => + debugPC <= debugPC_StartAddr; + debugPC_WidthCounter <= 0; + debugState <= Debug_DumpMem_0; + + when Debug_DumpMem_0 => + if mxMemVal.valid = '0' then + debugState <= Debug_DumpMem_1; + end if; + + -- Output the contents of memory in the format + when Debug_DumpMem_1 => + if mxMemVal.valid = '1' then + debugPC_WidthCounter <= debugPC_WidthCounter+4; + + -- Write out the memory location. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_SPLIT_DATA <= "01"; + if debugPC = debugPC_EndAddr or debugPC_WidthCounter = debugPC_Width-4 then + debugRec.FMT_POST_CRLF <= '1'; + debugPC_WidthCounter <= 0; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(3, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + if debugPC_WidthCounter = 0 then + debugRec.WRITE_PC <= '1'; + else + debugRec.WRITE_PC <= '0'; + end if; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(debugPC); + debugRec.DATA(63 downto 32) <= std_logic_vector(mxMemVal.word(31 downto 24)) & std_logic_vector(mxMemVal.word(23 downto 16)) & std_logic_vector(mxMemVal.word(15 downto 8)) & std_logic_vector(mxMemVal.word(7 downto 0)); + debugLoad <= '1'; + debugState <= Debug_DumpMem_2; + debugPC <= debugPC + wordBytes; + end if; + + when Debug_DumpMem_2 => + -- Move onto next opcode in Fifo. + if debugPC = debugPC_EndAddr then + debugState <= Debug_End; + else + debugState <= Debug_DumpMem_1; + end if; + + when Debug_End => + debugAllInfo <= '0'; + debugState <= Debug_Idle; + end case; + end if; + end if; + --------------------------------------------------------------------------------------------------------------------------------------------------- + end if; + end process; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Hardware divider - Fixed Point. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + DIVIDER : if IMPL_DIV = true or IMPL_FIDIV32 = true or IMPL_MOD = true generate + process(CLK, ZPURESET, divStart, dividendCopy) + begin + divRemainder <= unsigned(dividendCopy(31 downto 0)); + + if ZPURESET = '1' then + divComplete <= '1'; + divResult <= (others => '0'); + + elsif rising_edge(CLK) then + + if divComplete = '1' and divStart = '1' then + divComplete <= '0'; + bitCnt <= to_unsigned((32+divQuotientFractional)-2, bitCnt'LENGTH); + divResult <= (others => '0'); + + dividendCopy(30 downto 0) <= std_logic_vector(muxTOS.word(30 downto 0)); + dividendCopy(61 downto 31) <= (others => '0'); + + divisorCopy(61) <= '0'; + divisorCopy(60 downto 30) <= std_logic_vector(muxNOS.word(30 downto 0)); + divisorCopy(29 downto 0) <= (others => '0'); + + -- set sign bit + if((muxTOS.word(31) = '1' and muxNOS.word(31) = '0') or (muxTOS.word(31) = '0' and muxNOS.word(31) = '1')) then + divResult(31) <= '1'; + else + divResult(31) <= '0'; + end if; + + elsif divComplete = '0' and (DEBUG_CPU = false or (DEBUG_CPU = true and debugReady = '1')) then + -- 64bit compare of divisor/dividend. + if((unsigned(dividendCopy)) >= unsigned(divisorCopy)) then + --subtract, should only occur when the dividend is greater than the divisor. + dividendCopy <= std_logic_vector(to_unsigned(to_integer(unsigned(dividendCopy)) - to_integer(unsigned(divisorCopy)), dividendCopy'LENGTH)); + --set quotient + divResult(to_integer(bitCnt)) <= '1'; + end if; + + --reduce divisor + divisorCopy <= to_stdlogicvector(to_bitvector(divisorCopy) srl 1); + + --stop condition + if bitCnt = 0 then + divComplete <= '1'; + else + --reduce bit counter + bitCnt <= bitCnt - 1; + end if; + end if; + end if; + end process; + else generate + dividendCopy <= (others => DontCareValue); + end generate; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Hardware adder - Fixed Point. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + FIADD32: if IMPL_FIADD32 = true generate + process(muxTOS.word, muxNOS.word, ZPURESET) + begin + if ZPURESET = '1' then + fpAddResult <= (others => '0'); + else + -- both negative + if muxTOS.word(31) = '1' and muxNOS.word(31) = '1' then + -- sign + fpAddResult(31) <= '1'; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxTOS.word(30 downto 0)) + to_integer(muxNOS.word(30 downto 0)), 31)); + + --both positive + elsif muxTOS.word(31) = '0' and muxNOS.word(31) = '0' then + -- sign + fpAddResult(31) <= '0'; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxTOS.word(30 downto 0)) + to_integer(muxNOS.word(30 downto 0)), 31)); + + -- subtract TOS - NOS + elsif muxTOS.word(31) = '0' and muxNOS.word(31) = '1' then + -- sign + if muxTOS.word(30 downto 0) > muxNOS.word(30 downto 0) then + fpAddResult(31) <= '1'; + else + fpAddResult(31) <= '0'; + end if; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxTOS.word(30 downto 0)) - to_integer(muxNOS.word(30 downto 0)), 31)); + + -- subtract NOS - TOS + else + -- sign + if muxTOS.word(30 downto 0) < muxNOS.word(30 downto 0) then + fpAddResult(31) <= '1'; + else + fpAddResult(31) <= '0'; + end if; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxNOS.word(30 downto 0)) - to_integer(muxTOS.word(30 downto 0)), 31)); + end if; + end if; + end process; + else generate + fpAddResult <= (others => DontCareValue); + end generate; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Hardware multiplier - Fixed Point. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + FIMULT32: if IMPL_FIMULT32 = true generate + signal TOSflip : std_logic_vector(31 downto 0); + signal NOSflip : std_logic_vector(31 downto 0); + signal TOSmult : std_logic_vector(31 downto 0); + signal NOSmult : std_logic_vector(31 downto 0); + signal resultFlip : std_logic_vector(63 downto 0); + signal result : std_logic_vector(63 downto 0); + begin + process(muxTOS.word, TOSflip) + begin + for i in 0 to wordSize-1 loop + TOSflip(i) <= muxTOS.word(wordSize-1-i); + end loop; + TOSflip <= std_logic_vector(signed(TOSflip) + 1); + end process; + + process(muxNOS.word, NOSflip) + begin + for i in 0 to wordSize-1 loop + NOSflip(i) <= muxNOS.word(wordSize-1-i); + end loop; + NOSflip <= std_logic_vector(signed(NOSflip) + 1); + end process; + + process(result, quotientFractional, resultFlip) + begin + for i in quotientFractional to 30+quotientFractional loop + resultFlip(i) <= result(30+quotientFractional-i); + end loop; + resultFlip <= std_logic_vector(signed(resultFlip) + 1); + end process; + + process(muxTOS.word, muxNOS.word, TOSflip, NOSflip) + begin + if muxTOS.word(31) = '1' then + TOSmult <= TOSflip; + else + TOSmult <= std_logic_vector(muxTOS.word); + end if; + + if muxNOS.word(31) = '1' then + NOSmult <= NOSflip; + else + NOSmult <= std_logic_vector(muxNOS.word); + end if; + end process; + + process(TOSmult, NOSmult) + begin + result <= std_logic_vector(signed(TOSmult) * signed(NOSmult)); + end process; + + process(result, resultFlip, muxTOS.word, muxNOS.word, quotientFractional) + begin + -- sign + if (muxTOS.word(31) = '1' and muxNOS.word(31) = '0') or (muxTOS.word(31) = '0' and muxNOS.word(31) = '1') then + fpMultResult(31) <= '1'; + fpMultResult(30 downto 0) <= resultFlip(30 downto 0); + else + fpMultResult(31) <= '0'; + fpMultResult(30 downto 0) <= result(30+quotientFractional downto quotientFractional); + end if; + end process; + else generate + fpMultResult <= (others => DontCareValue); + quotientFractional <= 0; + end generate; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Debugger output processor. + -- This logic takes a debug record and expands it to human readable form then dispatches it to the debug serial port. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Add debug uart if required. Increasing the TX and DBG Fifo depth can help short term (ie. initial start of the CPU) + -- but once full, the debug run will eventually operate at the slowest denominator, ie. the TX speed and how quick it can + -- shift 10 bits. + DEBUG : if DEBUG_CPU = true generate + DEBUGUART: entity work.zpu_uart_debug + generic map ( + CLK_FREQ => CLK_FREQ -- Frequency of master clock. + ) + port map ( + -- CPU Interface + CLK => CLK, -- Master clock + RESET => ZPURESET, -- high active sync reset + DEBUG_DATA => debugRec, -- write data + CS => debugLoad, -- Chip Select. + READY => debugReady, -- Debug processor ready for next command. + + -- Serial data + TXD => DEBUG_TXD + ); + end generate; + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- End of debugger output processor. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + +end behave; diff --git a/zpu/cpu/zpu_core_evo.vhd.1 b/zpu/cpu/zpu_core_evo.vhd.1 new file mode 100755 index 0000000..4e3bcdf --- /dev/null +++ b/zpu/cpu/zpu_core_evo.vhd.1 @@ -0,0 +1,3565 @@ +-- ZPU Evolution +-- +-- Copyright 2004-2008 (ZPU Design, Small, Medium) oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- Copyright 2008 (zpuino) alvieboy - Álvaro Lopes - alvieboy@alvie.com +-- Copyright 2013 (zpuflex) Alastair M. Robinson +-- Copyright 2018-2019 (ZPU Evo) Philip Smart +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. +-- +-- Evo History: +-- 181230 v0.1 Initial version created by merging items of the Small, Medium and Flex versions. +-- 190328 v0.5 Working with Instruction, Emulation or No Cache with or without seperate instruction +-- bus. Runs numerous tests and output same as the Medium CPU. One small issue is running +-- without an instruction bus and instruction/emulation cache enabled, the DMIPS value is lower +-- than just with instruction bus or emulation bus, seems some clash which reuults in waits states +-- slowing the CPU down. +-- 191021 v1.0 First release. All variations tested but more work needed on the SDRAM controller to +-- make use of burst mode in order to populate the L2 cache in fewer cycles. +-- Additional instructions need to be added back in after test and verification, albeit some +-- which are specific to the Sharp Emulator should be skipped. +-- Additional effort needs spending on the Wishbone Error signal to retry the bus transaction, +-- currently it just aborts it which is not ideal. +-- 191126 v1.1 Bug fixes. When switching off WishBone the CPU wouldnt run. +-- 191215 v1.2 Bug fixes. Removed L2 Cache megacore and replaced with inferred equivalent, fixed hardware +-- byte/h-word write which was always defaulting to read-update-write, fixed L2 timing with +-- external SDRAM, minor tweaks and currently looking at better constraints. +-- 191220 v1.21 Changes to Mult, shifting it from a combination assignment to a clocked assignment to improve +-- slack. Small changes made for slack in setup and hold. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_pkg.all; + +-------------------------------------------------------------------------------------------------------------------------------------------- +-- ZPU Evo Signal Description. +-------------------------------------------------------------------------------------------------------------------------------------------- +-- +-- Main Memory/IO Bus. +-- ------------------- +-- This bus is used to access all external memory and IO, it can also, via configuration, be used to read instructions from attached memory. +-- +-- MEM_WRITE_ENABLE - set to '1' for a single cycle to send off a write request. +-- MEM_DATA_OUT is valid only while MEM_WRITE_ENABLE='1'. +-- MEM_WRITE_BYTE - set to '1' when performing a byte write with data in bits 7-0 of MEM_DATA_OUT +-- MEM_WRITE_HWORD - set to '1' when performing a half word write with data in bits 15-0 of MEM_DATA_OUT +-- MEM_READ_ENABLE - set to '1' for a single cycle to send off a read request. Data is expected on MEM_DATA_IN on next clock rising edge +-- unless MEM_BUSY is asserted in which case the data is read on the next clock rising edge after MEM_BUSY is +-- de-asserted. +-- +-- MEM_BUSY - This signal is used to prolong a read or write cycle, whilst asserted, any read or write cycle is paused as is the +-- CPU with signals remaining in same state just prior to MEM_BUSY assetion. +-- Set to '0' when MEM_READ is valid after a read request. +-- If set to '1'(busy), the current cycle is held until released. For MEM_READ_ENABLE = '1' this means data will be +-- latched on clock rising edge following deassertion of MEM_BUSY. For MEM_WRITE_ENABLE, the write transaction is held +-- with MEM_WRITE_ENABLE asserted until the cycle following the deassertion of MEM_BUSY. +-- MEM_ADDR - address for read/write request +-- MEM_DATA_IN - read data. Valid only on the cycle after mem_busy='0' after +-- MEM_READ_ENABLE='1' for a single cycle. +-- MEM_DATA_OUT - data to write +-- +-- Wishbone Bus B4 Specification +-- ----------------------------- +-- This bus is the industry standard for FPGA IP designs and the one primarily used in OpenCores. In this implementation it is +-- 32bit wide using a Master/Multi-Slave configuration with the ZPU acting as Master. It is a compile time configurable extension as +-- some uses of the ZPU Evo wont need it and thus saves fabric area. The description below is taken from the OpenCores Wishbone B4 +-- specification. +-- +-- WB_CLK_I - The clock input [WB_CLK_I] coordinates all activities for the internal logic within the WISHBONE interconnect. +-- - All WISHBONE output signals are registered at the rising edge of [WB_CLK_I]. All WISHBONE input signals are +-- - stable before the rising edge of [WB_CLK_I]. +-- WB_RST_I - The reset input [WB_RST_I] forces the WISHBONE interface to restart. In this design, this signal is tied to the +-- - ZPU reset via an OR mechanism, forcing the ZPU to reset if activated. +-- WB_ACK_I - The acknowledge input [WB_ACK_I], when asserted, indicates the normal termination of a bus cycle. +-- WB_DAT_I - The data input array [WB_DAT_I] is used to pass binary data. The array boundaries are determined by the port size, +-- - with a port size of 32-bits in this design. +-- WB_DAT_O - The data output array [DAT_O()] is used to pass binary data. The array boundaries are determined by the port size, +-- - with a port size of 32-bits in this design. +-- WB_ADR_O - The address output array [WB_ADR_O] is used to pass a binary address. The higher array boundary is specific to the +-- - address width of the core, and the lower array boundary is determined by the data port size and granularity. +-- - This design is 32bit so WB_ADR[1:0] specify the byte level granularity. +-- WB_CYC_O - The cycle output [WB_CYC_O], when asserted, indicates that a valid bus cycle is in progress. The signal is asserted +-- - for the duration of all bus cycles. +-- WB_STB_O - The strobe output [WB_STB_O] indicates a valid data transfer cycle. It is used to qualify various other signals on +-- - the interface such as [WB_SEL_O]. The SLAVE asserts either the [WB_ACK_I], [WB_ERR_I] or [WB_RTY_I] signals in +-- - response to every assertion of the [WB_STB_O] signal. +-- WB_CTI_O - The Cycle Type Idenfier [WB_CTI_O] Address Tag provides additional information about the current cycle. The MASTER +-- - sends this information to the SLAVE. The SLAVE can use this information to prepare the response for the next cycle. +-- WB_WE_O - The write enable output [WB_WE_O] indicates whether the current local bus cycle is a READ or WRITE cycle. The +-- - signal is negated during READ cycles, and is asserted during WRITE cycles. +-- WB_SEL_O - The select output array [WB_SEL_O] indicates where valid data is expected on the [WB_DAT_I] signal array during +-- - READ cycles, and where it is placed on the [WB_DAT_O] signal array during WRITE cycles. The array boundaries are +-- - determined by the granularity of a port which is 32bit in this design leading to a WB_SEL_O width of 4 bits, 1 +-- - bit to represent each byte. ie. WB_SEL_O[3] = MSB, WB_SEL_O[0] = LSB. +-- WB_HALT_I - +-- WB_ERR_I - The error input [WB_ERR_I] indicates an abnormal cycle termination. The source of the error, and the response +-- - generated by the MASTER is defined by the IP core supplier, in this case the intention (NYI) is to retry +-- - the transaction. +-- WB_INTA_I - A non standard signal to allow a wishbone device to interrupt the ZPU when set to logic '1'. The interrupt is +-- - registered on the next rising edge. +-- +-- +-- Instruction Memory Bus +-- ---------------------- +-- This bus is used for dedicated faster response read only memory containing the code to be run. Using this bus results in faster +-- CPU performance. If this bus is not used/disabled, all instructions will be fetched via the main bus (System or Wishbone bus). +-- +-- MEM_BUSY_INSN - Memory is busy ('1') so data invalid. +-- MEM_DATA_IN_INSN - Instruction data in. +-- MEM_ADDR_INSN - Instruction address bus. +-- MEM_READ_ENABLE_INSN - Instruction read enable signal (active high). +-- +-- INT_REQ - Set to '1' by external logic until interrupts are acknowledged by CPU. +-- INT_ACK - Set to '1' for 1 clock cycle when the interrupt is acknowledged and processing commences. +-- INT_DONE - Set to '1' for 1 clock cycle when the interrupt processing is complete +-- BREAK - Set to '1' when CPU hits a BREAK instruction +-- CONTINUE - When the CPU is halted due to a BREAK instruction, this signal, when asserted ('1') forces the CPU to commence +-- processing of the instruction following the BREAK instruction. +-- DEBUG_TXD - Serial output of runtime debug data if enabled. + +entity zpu_core_evo is + generic ( + -- Optional hardware features to be implemented. + IMPL_HW_BYTE_WRITE : boolean := false; -- Enable use of hardware direct byte write rather than read 32bits-modify 8 bits-write 32bits. + IMPL_HW_WORD_WRITE : boolean := false; -- Enable use of hardware direct byte write rather than read 32bits-modify 16 bits-write 32bits. + IMPL_OPTIMIZE_IM : boolean := true; -- Optimise Im instructions to gain speed. + IMPL_USE_INSN_BUS : boolean := true; -- Use a seperate bus to read instruction memory, normally implemented in BRAM. + IMPL_USE_WB_BUS : boolean := true; -- Use the wishbone interface in addition to direct access bus. + -- Optional instructions to be implemented in hardware: + IMPL_ASHIFTLEFT : boolean := true; -- Arithmetic Shift Left (uses same logic so normally combined with ASHIFTRIGHT and LSHIFTRIGHT). + IMPL_ASHIFTRIGHT : boolean := true; -- Arithmetic Shift Right. + IMPL_CALL : boolean := true; -- Call to direct address. + IMPL_CALLPCREL : boolean := true; -- Call to indirect address (add offset to program counter). + IMPL_DIV : boolean := true; -- 32bit signed division. + IMPL_EQ : boolean := true; -- Equality test. + IMPL_EXTENDED_INSN : boolean := true; -- Extended multibyte instruction set. + IMPL_FIADD32 : boolean := true; -- Fixed point Q17.15 addition. + IMPL_FIDIV32 : boolean := true; -- Fixed point Q17.15 division. + IMPL_FIMULT32 : boolean := true; -- Fixed point Q17.15 multiplication. + IMPL_LOADB : boolean := true; -- Load single byte from memory. + IMPL_LOADH : boolean := true; -- Load half word (16bit) from memory. + IMPL_LSHIFTRIGHT : boolean := true; -- Logical shift right. + IMPL_MOD : boolean := true; -- 32bit modulo (remainder after division). + IMPL_MULT : boolean := true; -- 32bit signed multiplication. + IMPL_NEG : boolean := true; -- Negate value in TOS. + IMPL_NEQ : boolean := true; -- Not equal test. + IMPL_POPPCREL : boolean := true; -- Pop a value into the Program Counter from a location relative to the Stack Pointer. + IMPL_PUSHSPADD : boolean := true; -- Add a value to the Stack pointer and push it onto the stack. + IMPL_STOREB : boolean := true; -- Store/Write a single byte to memory/IO. + IMPL_STOREH : boolean := true; -- Store/Write a half word (16bit) to memory/IO. + IMPL_SUB : boolean := true; -- 32bit signed subtract. + IMPL_XOR : boolean := true; -- Exclusive or of value in TOS. + -- Size/Control parameters for the optional hardware. + MAX_INSNRAM_SIZE : integer := 16384; -- Maximum size of the optional Instruction BRAM on the INSN Bus. + MAX_L1CACHE_BITS : integer := 4; -- Maximum size in instructionsG of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache. + MAX_L2CACHE_BITS : integer := 12; -- Maximum size in bytes of the Level 1 instruction cache governed by the number of bits, ie. 8 = 256 byte cache. + MAX_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits. + RESET_ADDR_CPU : integer := 0; -- Initial start address of the CPU. + START_ADDR_MEM : integer := 0; -- Start address of program memory. + STACK_ADDR : integer := 0; -- Initial stack address on CPU start. + CLK_FREQ : integer := 100000000 -- Frequency of the input clock. + ); + port ( + CLK : in std_logic; -- Main clock. + RESET : in std_logic; -- Reset the CPU (high). + ENABLE : in std_logic; -- Enable the CPU (high), setting low will halt the CPU until signal is returned high. + -- Main Memory/IO bus. + MEM_BUSY : in std_logic; + MEM_DATA_IN : in std_logic_vector(WORD_32BIT_RANGE); + MEM_DATA_OUT : out std_logic_vector(WORD_32BIT_RANGE); + MEM_ADDR : out std_logic_vector(ADDR_BIT_RANGE); + MEM_WRITE_ENABLE : out std_logic; + MEM_READ_ENABLE : out std_logic; + MEM_WRITE_BYTE : out std_logic; + MEM_WRITE_HWORD : out std_logic; + -- Instruction memory bus (if implemented). + MEM_BUSY_INSN : in std_logic; + MEM_DATA_IN_INSN : in std_logic_vector(WORD_32BIT_RANGE); + MEM_ADDR_INSN : out std_logic_vector(ADDR_BIT_RANGE); + MEM_READ_ENABLE_INSN : out std_logic; + -- Master Wishbone Memory/IO bus interface. + WB_CLK_I : in std_logic; + WB_RST_I : in std_logic; + WB_ACK_I : in std_logic; + WB_DAT_I : in std_logic_vector(WORD_32BIT_RANGE); + WB_DAT_O : out std_logic_vector(WORD_32BIT_RANGE); + WB_ADR_O : out std_logic_vector(ADDR_BIT_RANGE); + WB_CYC_O : out std_logic; + WB_STB_O : out std_logic; + WB_CTI_O : out std_logic_vector(2 downto 0); + WB_WE_O : out std_logic; + WB_SEL_O : out std_logic_vector(WORD_4BYTE_RANGE); + WB_HALT_I : in std_logic; + WB_ERR_I : in std_logic; + WB_INTA_I : in std_logic; + + -- Set to one to jump to interrupt vector + -- The ZPU will communicate with the hardware that caused the + -- interrupt via memory mapped IO or the interrupt flag can + -- be cleared automatically + INT_REQ : in std_logic; + INT_ACK : out std_logic; -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + INT_DONE : out std_logic; -- Interrupt service routine completed/done. + -- Break and debug signals. + BREAK : out std_logic; -- A break instruction encountered. + CONTINUE : in std_logic; -- When break activated, processing stops. Setting CONTINUE to logic 1 resumes processing with next instruction. + DEBUG_TXD : out std_logic -- Debug serial output. + ); +end zpu_core_evo; + +architecture behave of zpu_core_evo is + + -- Constants. + constant MAX_L1CACHE_SIZE : integer := (2**(MAX_L1CACHE_BITS)); + constant MAX_L2CACHE_SIZE : integer := (2**MAX_L2CACHE_BITS); + subtype L1CACHE_BIT_RANGE is natural range MAX_L1CACHE_BITS-1 downto 0; + subtype L2CACHE_BIT_RANGE is natural range MAX_L2CACHE_BITS-1 downto 0; + subtype L2CACHE_32BIT_RANGE is natural range MAX_L2CACHE_BITS-1 downto 2; + + -- Instruction offset in the instruction vector. + subtype INSN_RANGE is natural range 13 downto 0; + subtype OPCODE_RANGE is natural range 7 downto 0; + subtype DECODED_RANGE is natural range 13 downto 8; + subtype OPCODE_IM_RANGE is natural range 6 downto 0; + subtype IM_DATA_RANGE is natural range 6 downto 0; + subtype OPCODE_PARAM_RANGE is natural range 1 downto 0; + subtype OPCODE_INSN_RANGE is natural range 7 downto 2; + + -- Decoded instruction states. Used in the execution unit state machine according to instruction being processed. + type InsnType is + ( + Insn_Add, -- 00 + Insn_AddSP, -- 01 + Insn_AddTop, -- 02 + Insn_Alshift, -- 03 + Insn_And, -- 04 + Insn_Break, -- 05 + Insn_Call, -- 06 + Insn_Callpcrel, -- 07 + Insn_Div, -- 08 + Insn_Emulate, -- 09 + Insn_Eq, -- 0a + Insn_Eqbranch, -- 0b + Insn_Extend, -- 0c + Insn_FiAdd32, -- 0d + Insn_FiDiv32, -- 0e + Insn_FiMult32, -- 0f + Insn_Flip, -- 10 + Insn_Im, -- 11 + Insn_Lessthan, -- 12 + Insn_Lessthanorequal, -- 13 + Insn_Load, -- 14 + Insn_Loadb, -- 15 + Insn_Loadh, -- 16 + Insn_LoadSP, -- 17 + Insn_Mod, -- 18 + Insn_Mult, -- 19 + Insn_Neg, -- 1a + Insn_Neq, -- 1b + Insn_Neqbranch, -- 1c + Insn_Nop, -- 1d + Insn_Not, -- 1e + Insn_Or, -- 1f + Insn_PopPC, -- 20 + Insn_PopPCRel, -- 21 + Insn_PopSP, -- 22 + Insn_PushPC, -- 23 + Insn_PushSP, -- 24 + Insn_Pushspadd, -- 25 + Insn_Shift, -- 26 + Insn_Store, -- 27 + Insn_Storeb, -- 28 + Insn_Storeh, -- 29 + Insn_StoreSP, -- 2a + Insn_Sub, -- 2b + Insn_Ulessthan, -- 2c + Insn_Ulessthanorequal, -- 2d + Insn_Xor -- 2e + ); + + -- State machine states. Some states are extension of instruction execution whilst others maintain the ZPU runtime operations and state. + -- + type StateType is + ( + State_Div2, + State_Mult2, + State_Execute, + State_FiAdd2, + State_FiDiv2, + State_FiMult2, + State_Idle, + State_Init, + State_Mod2 + ); + + -- Decoder state machine states. Unit which fetches, decodes and stores the decoded instructions and the required states needed to do this. + -- + type DecoderStateType is + ( + Decode_Idle, + Decode_Fetch, + Decode_Word, + Decode_WriteCache + ); + + type Level1CacheStateType is + ( + State_PreSetAddr, + State_LatchAddr, + State_Decode, + State_Store + ); + + -- Memory transaction processing unit. All CPU memory accesses (except Instruction Fetch) go through this unit. These states define + -- those required to implement the unit. + -- + type MemXactStateType is + ( + MemXact_Idle, + MemXact_MemoryFetch, + MemXact_OpcodeFetch, + MemXact_TOS, + MemXact_NOS, + MemXact_TOSNOS, + MemXact_TOSNOS_2, + MemXact_TOSNOS_3, + MemXact_ReadByteToTOS, + MemXact_ReadWordToTOS, + MemXact_ReadAddToTOS, + MemXact_WriteToAddr, + MemXact_WriteByteToAddr, + MemXact_WriteByteToAddr2, + MemXact_WriteHWordToAddr, + MemXact_WriteHWordToAddr2 + ); + + -- Memory transaction processing commands. These states (commands) are the actions which the MTP can process. + -- + type MemXactCmdType is + ( + MX_CMD_READTOS, + MX_CMD_READNOS, + MX_CMD_READTOSNOS, + MX_CMD_READBYTETOTOS, + MX_CMD_READWORDTOTOS, + MX_CMD_READADDTOTOS, + MX_CMD_WRITEBYTETOADDR, + MX_CMD_WRITEHWORDTOADDR, + MX_CMD_WRITETOINDADDR, + MX_CMD_WRITE + ); + + -- Debug states. These states are those required to output debug data via the debug serialisation unit. + -- + type DebugType is + ( + Debug_Idle, + Debug_Start, + Debug_DumpL1, + Debug_DumpL1_1, + Debug_DumpL1_2, + Debug_DumpL2, + Debug_DumpL2_0, + Debug_DumpL2_1, + Debug_DumpL2_2, + Debug_DumpMem, + Debug_DumpMem_0, + Debug_DumpMem_1, + Debug_DumpMem_2, + Debug_End + ); + + -- Record to store a memory word and its validity, typically used for stack caching. + -- + type WordRecord is record + word : unsigned(WORD_32BIT_RANGE); + valid : std_logic; + end record; + + -- Record to contain an opcode and its decoded form. + -- + type InsnRecord is record + decodedOpcode : InsnType; + opcode : std_logic_vector(7 downto 0); + end record; + + -- Memory transaction records. Memory reads and writes are pushed into a queue and executed sequentially. + -- + type MemXactRecord is record + addr : std_logic_vector(ADDR_BIT_RANGE); + data : std_logic_vector(WORD_32BIT_RANGE); + cmd : MemXactCmdType; + end record; + -- + -- Array definitions. + type InsnWord is array(natural range 0 to wordBytes-1) of InsnRecord; + type InsnQueue is array(natural range 0 to 2*wordBytes-1) of InsnRecord; + type InsnL1Array is array(natural range 0 to ((2**(MAX_L1CACHE_BITS))-1)) of std_logic_vector(INSN_RANGE); + type MemXactArray is array(natural range 0 to ((2**MAX_MXCACHE_BITS)-1)) of MemXactRecord; + + signal pc : unsigned(ADDR_BIT_RANGE); -- Current program location being executed. + signal pcLast : unsigned(ADDR_BIT_RANGE); -- Last program location executed. + signal incPC : unsigned(ADDR_BIT_RANGE); -- Next program location to be executed. + signal incIncPC : unsigned(ADDR_BIT_RANGE); -- Next +2 program location to be executed. + signal inc3PC : unsigned(ADDR_BIT_RANGE); -- Next +3 program location to be executed. + signal inc4PC : unsigned(ADDR_BIT_RANGE); -- Next +4 program location to be executed. + signal inc5PC : unsigned(ADDR_BIT_RANGE); -- Next +5 program location to be executed. + signal sp : unsigned(ADDR_32BIT_RANGE); -- Current stack pointer. + signal incSp : unsigned(ADDR_32BIT_RANGE); -- Stack pointer when 1 value is popped. + signal incIncSp : unsigned(ADDR_32BIT_RANGE); -- Stack pointer when 2 values are popped. + signal decSp : unsigned(ADDR_32BIT_RANGE); -- Stack pointer after a value is pushed. + signal TOS : WordRecord; -- Top Of Stack value. + signal NOS : WordRecord; -- Next Of Stack value (ie. value after TOS). + signal mxTOS : WordRecord; -- Top Of Stack retrieved by the Memory Transaction Processor. + signal mxNOS : WordRecord; -- Next Of Stack retrieved by the MXP. + signal muxTOS : WordRecord; -- Multiplexed (to get most recent) TOS, either from MXP or current value. + signal muxNOS : WordRecord; -- Multiplexed (to get most recent) NOS, either from MXP or current value. + signal divResult : unsigned(WORD_32BIT_RANGE); + signal divRemainder : unsigned(WORD_32BIT_RANGE); + signal divStart : std_logic; + signal divComplete : std_logic; + signal quotientFractional : integer range 0 to 15; -- Fractional component size of a fixed point value. + signal divQuotientFractional : integer range 0 to 15; -- Fractional component size for the divider as it can be changed dynamically for integer division. + signal multResult : unsigned(wordSize*2-1 downto 0); -- Result after internal multiplication. + signal state : StateType; + signal fpAddResult : std_logic_vector(WORD_32BIT_RANGE); + signal fpMultResult : std_logic_vector(WORD_32BIT_RANGE); + signal bitCnt : unsigned(5 downto 0); + signal dividendCopy : std_logic_vector(61 downto 0); + signal divisorCopy : std_logic_vector(61 downto 0); + + -- Wishbone processing. + -- + signal ZPURESET : std_logic; + signal wbXactActive : std_logic; -- Wishbone interface is active. + + -- Break processing. + -- + signal inBreak : std_logic; -- Flag to indicate when the CPU is halted (1) due to a BREAK instruction or illegal instruction. + + -- Interrupt procesing. + -- + signal intTriggered : std_logic; -- Flag to indicate an interrupt has been requested, reset when interrupt processing starts. + signal inInterrupt : std_logic; -- Flag to indicate that the CPU is currently inside an interrupt processing block. + signal interruptSuspendedAddr : unsigned(ADDR_BIT_RANGE); -- Address that was interrupted by the interrupt, used to return processing when interrupt complete. + + -- Instruction storage, decoding and processing. + -- + signal insnExParameter : unsigned(WORD_32BIT_RANGE); -- Parameter storage for the extended instruction. + signal idimFlag : std_logic; -- Flag to indicate concurrent Im instructions which are building a larger word in TOS. + signal l1State : Level1CacheStateType; -- Current state of the L1 Cache decode and populate machine. + + -- Cache L1 specific signals. + -- + signal cacheL1 : InsnL1Array; -- Level 1 cache, implemented as registers to gain random access for instruction lookahead optimisation and instruction set extension. + signal cacheL1StartAddr : unsigned(ADDR_BIT_RANGE); -- Absolute address of first instruction in cache. + signal cacheL1FetchIdx : unsigned(ADDR_BIT_RANGE); -- Index into L1 cache decoded instructions will be placed. + signal cacheL1Invalid : std_logic; -- A flag to indicate when the L1 cache is in invalid. + signal cacheL1Empty : std_logic; -- A flag to indicate when the L1 cache is empty. + signal cacheL1Full : std_logic; -- A flag to indicate when the L1 cache is full. + signal cacheL1InsnAfterPC : unsigned(ADDR_BIT_RANGE); -- Count of how many instructions are in the cache after the current program counter. + attribute ramstyle : string; + attribute ramstyle of cacheL1 : signal is "logic"; + + -- Cache L2 (primary) specific signals. + -- + signal cacheL2FetchIdx : unsigned(ADDR_BIT_RANGE); -- Location in memory being read by the decoder for storage into cache. + signal cacheL2StartAddr : unsigned(ADDR_BIT_RANGE); -- The actual program address stored in the first cache location. + signal cacheL2Active : std_logic; -- A flag to indicate when the L2 cache is in use. + signal cacheL2Invalid : std_logic; -- A flag to indicate when the L2 cache is in invalid. + signal cacheL2Empty : std_logic; -- A flag to indicate the instruction cache is empty. + signal cacheL2Mux2Addr : unsigned(L2CACHE_32BIT_RANGE); -- Multiplexed address into L2 cache between the L1 fetch and debug fetch. + signal cacheL2Word : std_logic_vector(WORD_32BIT_RANGE); + signal cacheL2Write : std_logic; + signal cacheL2WriteByte : std_logic; -- Update a single byte in the L2 cache. + signal cacheL2WriteHword : std_logic; -- Update a 16bit half-word in the L2 cache. + signal cacheL2WriteAddr : unsigned(L2CACHE_BIT_RANGE); + signal cacheL2WriteData : std_logic_vector(WORD_32BIT_RANGE); + signal cacheL2IncAddr : std_logic; -- A flag to indicate when the L2 cache write address should be incremented, generally after a write pulse. + signal cacheL2MxAddrInCache : std_logic; -- A flag to indicate when an MXP address exists in the L2 cache. + signal cacheL2Full : std_logic; -- A flag to indicate when the L2 cache is full. + + -- Memory transaction processor. + -- + signal mxFifo : MemXactArray; + signal mxState : MemXactStateType; + signal mxFifoWriteIdx : unsigned(MAX_MXCACHE_BITS-1 downto 0); + signal mxFifoReadIdx : unsigned(MAX_MXCACHE_BITS-1 downto 0); + signal mxInsnData : std_logic_vector(WORD_32BIT_RANGE); + signal mxMemVal : WordRecord; -- Direct memory read result. + signal mxHoldCycles : integer range 0 to 3; -- Cycles to hold and extend memory transactions. + + -- Hardware Debugging. + -- + signal debugPC : unsigned(ADDR_BIT_RANGE); -- Debug PC for reading L1, L2 and memory for debugger output. + signal debugPC_StartAddr : unsigned(ADDR_BIT_RANGE); -- Start address for dump of memory contents. + signal debugPC_EndAddr : unsigned(ADDR_BIT_RANGE); -- End address for dump of memory contents. + signal debugPC_Width : integer range 4 to 32; -- Width of output in bytes. + signal debugPC_WidthCounter : integer range 0 to 31; -- Counter to match variable width. + signal debugState : DebugType; + signal debugOutputOnce : std_logic; -- Signal to prevent continuous output of debug messages when in a wait. + signal debugAllInfo : std_logic; -- Output all information from start point of entry to debug FSM if set. + signal debugRec : zpu_dbg_t; + signal debugLoad : std_logic; -- Load a debug record into the debug serialiser fsm, 1 = load, 0 = inactive. + signal debugReady : std_logic; -- Flag to indicate serializer fsm is busy (0) or available (1). + + --------------------------------------------- + -- Functions specific to the CPU core. + --------------------------------------------- + +begin + -- If the wishbone interface is enabled, assign permanent connections. + WB_INIT: if IMPL_USE_WB_BUS = true generate + ZPURESET <= RESET or WB_RST_I; + else generate + ZPURESET <= RESET; + end generate; + + --------------------------------------------- + -- Cache storage. + --------------------------------------------- + + -- Level 2 cache inferred with byte level write. + -- + CACHEL2 : work.evo_L2cache + generic map ( + addrbits => MAX_L2CACHE_BITS + ) + port map ( + clk => CLK, + memAAddr => std_logic_vector(cacheL2WriteAddr), + memAWriteEnable => cacheL2Write, + memAWriteByte => cacheL2WriteByte, + memAWriteHalfWord => cacheL2WriteHword, + memAWrite => cacheL2WriteData, + memARead => open, + + memBAddr => std_logic_vector(cacheL2Mux2Addr), + memBWrite => (others => '0'), + memBWriteEnable => '0', + memBRead => cacheL2Word + ); + + -- Instruction cache memory. cache instructions from the resync program counter forwards, when we get to a relative or direct + -- jump, if the destination is in cache, read from cache else resync. This speeds up operations where a resync (ie. branch, call etc) would + -- occur, saving cycles. It more especially speeds up the process if using one main bus and the external memory speed is slower than bram. + -- + -- Description of signals: + -- cacheL2StartAddr Absolute Start Address of word in first cache location. + -- cacheL2Active 1 when L2 cache is active, 0 when using dedicated instruction BRAM. + -- cacheL2Empty 1 when cache is empty, 0 when valid data present. + -- cacheL2Invalid 1 when the contents of L2Cache are no longer valid (due to next insn being out of cache scope). + -- cacheL2Mux2Addr Address multiplexer into cache. Address is set to the DebugPC address when the Debug state machine is not idle, all other times it is set to the Next cache fetch address. + -- cacheL2MxAddrInCache When a queued MX Processor address is in the L2 cache, set to 1 else set to 0. Used to determine if a memory write should be written into cache (write thru). + -- cacheL2Full 1 when cache is full, 0 otherwise. + -- + cacheL2Active <= '1' when IMPL_USE_INSN_BUS = false or (IMPL_USE_INSN_BUS = true and pc >= to_unsigned(MAX_INSNRAM_SIZE, pc'length)) + else '0'; + cacheL2Empty <= '1' when cacheL2FetchIdx(ADDR_32BIT_RANGE) = cacheL2StartAddr(ADDR_32BIT_RANGE) + else '0'; + cacheL2Invalid <= '1' when pc(ADDR_32BIT_RANGE) < cacheL2StartAddr(ADDR_32BIT_RANGE) or (pc(ADDR_32BIT_RANGE) > cacheL2FetchIdx(ADDR_32BIT_RANGE)) + else '0'; + cacheL2Mux2Addr <= cacheL1FetchIdx(L2CACHE_32BIT_RANGE) when DEBUG_CPU = false or (DEBUG_CPU = true and debugState = Debug_Idle) + else + debugPC(L2CACHE_32BIT_RANGE) when DEBUG_CPU = true + else + (others => 'X'); + cacheL2MxAddrInCache <= '1' when (to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)), cacheL2StartAddr'length) >= cacheL2StartAddr and to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)), cacheL2FetchIdx'length) < cacheL2FetchIdx) and (IMPL_USE_INSN_BUS = false or (IMPL_USE_INSN_BUS = true and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= MAX_INSNRAM_SIZE)) + else '0'; + cacheL2Full <= '1' when cacheL2FetchIdx(ADDR_32BIT_RANGE) - cacheL2StartAddr(ADDR_32BIT_RANGE) = MAX_L2CACHE_SIZE / 4 + else '0'; + --------------------------------------------- + -- End of Cache storage. + --------------------------------------------- + + ------------------------------------ + -- Memory transaction processor MXP. + ------------------------------------ + -- The mxp localises all memory/io operations into a single process. This aids in adaptation to differing bus topolgies as only this process + -- needs updating (the local INSN bus uses a direct BRAM/ROM connection and bypasses the MXP). This logic processes a queue of transactions in fifo + -- order and fetches instructions as required.. The processor unit commits requests to the queue and this logic fulfills them. If the CPU is only + -- using one bus for all memory and IO operations then memory transactions in the queue are completed before instruction fetches. If the instruction + -- queue is empty then the processor will stall until instructions are fetched. + -- + MEMXACT: process(CLK, ZPURESET, TOS, NOS, debugState) + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if ZPURESET = '1' then + MEM_WRITE_BYTE <= '0'; + MEM_WRITE_HWORD <= '0'; + MEM_READ_ENABLE <= '0'; + MEM_WRITE_ENABLE <= '0'; + WB_ADR_O(ADDR_32BIT_RANGE) <= (others => '0'); + WB_DAT_O <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '0'; + WB_STB_O <= '0'; + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + wbXactActive <= '0'; + cacheL2Write <= '0'; + cacheL2IncAddr <= '0'; + cacheL2FetchIdx <= (others => '0'); + cacheL2StartAddr <= (others => '0'); + mxFifoReadIdx <= (others => '0'); + mxState <= MemXact_Idle; + mxTOS <= ((others => '0'), '0'); + mxNOS <= ((others => '0'), '0'); + mxHoldCycles <= 0; + if DEBUG_CPU = true then + mxMemVal.valid <= '0'; + end if; + + ------------------------ + -- FALLING CLOCK EDGE -- + ------------------------ + elsif falling_edge(CLK) then + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(CLK) then + -- TOS/NOS values read in by the MXP are only valid for 1 cycle, so reset the valid flag. + mxTOS.valid <= '0'; + mxNOS.valid <= '0'; + + -- Memory signals are one clock width wide, reset them to inactive on each clock to ensure this.^^ + MEM_READ_ENABLE <= '0'; + MEM_WRITE_ENABLE <= '0'; + + -- Width signals are one clock width wide unless extended by busy signal. + if MEM_BUSY = '0' then + MEM_WRITE_BYTE <= '0'; + MEM_WRITE_HWORD <= '0'; + end if; + + -- Complete any active cache memory writes. + if cacheL2Write = '1' and mxHoldCycles = 0 then + cacheL2Write <= '0'; + cacheL2WriteByte <= '0'; + cacheL2WriteHword <= '0'; + + -- Once the cache write is complete, we update the address if needed, which will be setup in time for the next word to be read in from external memory. + if cacheL2IncAddr = '1' then + cacheL2IncAddr <= '0'; + + -- Update the address from where we fetch the next instruction, 32bit aligned 4 bytes. + cacheL2FetchIdx <= cacheL2FetchIdx + wordBytes; + end if; + end if; + + -- If wishbone interface is active and an ACK is received, deassert the signals. + if IMPL_USE_WB_BUS = true and wbXactActive = '1' and WB_ACK_I = '1' and WB_HALT_I = '0' and mxHoldCycles = 0 then + wbXactActive <= '0'; + WB_WE_O <= '0'; + WB_CYC_O <= '0'; + WB_STB_O <= '0'; + end if; + + -- TODO: WB_ERR_I needs better handling, should retry at least once and then issue a BREAK. + if IMPL_USE_WB_BUS = true and WB_ERR_I = '1' then + wbXactActive <= '0'; + WB_WE_O <= '0'; + WB_CYC_O <= '0'; + WB_STB_O <= '0'; + end if; + + -- If the hold cycle counter is not 0, then we are holding on the current transaction until it reaches zero, so decrement + -- ready to test next cycle. This mechanism is to prolong a memory cycle as without it, address setup and hold is 1 cycle and + -- valid data is expected at the end of the cycle. ie. the address and control signals are set on the current rising edge and become + -- active and on the next rising edge the data is expected to be valid, few components (ie. register ram) can meet this timing requirement. + if mxHoldCycles > 0 then + mxHoldCycles <= mxHoldCycles - 1; + end if; + + -- If the external memory is busy (1) or the wishbone interface is active and no ACK received then we have to back off and wait till next clock cycle and check again. + if MEM_BUSY = '0' and ((IMPL_USE_WB_BUS = true and ((wbXactActive = '1' and WB_ACK_I = '1') or wbXactActive = '0')) or IMPL_USE_WB_BUS = false) and mxHoldCycles = 0 then + + -- Memory transaction processor state machine. Idle is the control state and depending upon entries in the queue, debug or L2 usage, it + -- directs the FSM states accordingly. + case mxState is + when MemXact_Idle => + -- If there are no memory transactions to complete, debugging is enabled and the debug outputter is active, read the memory location + -- according to the given index. + if DEBUG_CPU = true and (mxFifoWriteIdx - mxFifoReadIdx) = 0 and (debugState /= Debug_Idle and debugState /= Debug_DumpL1 and debugState /= Debug_DumpL2 and debugState /= Debug_DumpMem) then + if IMPL_USE_WB_BUS = true and debugPC(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(debugPC(ADDR_32BIT_RANGE)); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxHoldCycles <= 1; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(debugPC(ADDR_32BIT_RANGE)); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE <= '1'; + end if; + mxMemVal.valid <= '0'; + mxState <= MemXact_MemoryFetch; + + -- If instruction queue is empty or there are no memory transactions to process and the instruction queue isnt full, + -- read the next instruction and fill the instruction queue. + elsif cacheL2Active = '1' and (mxFifoWriteIdx - mxFifoReadIdx) = 0 and cacheL2Invalid = '0' and cacheL2Full = '0' and cacheL2IncAddr = '0' then + if IMPL_USE_WB_BUS = true and cacheL2FetchIdx(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL2FetchIdx(ADDR_32BIT_RANGE)); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxHoldCycles <= 1; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL2FetchIdx(ADDR_32BIT_RANGE)); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE <= '1'; + mxHoldCycles <= 1; + end if; + cacheL2WriteAddr <= cacheL2FetchIdx(L2CACHE_BIT_RANGE); + mxState <= MemXact_OpcodeFetch; + + -- If there is an item on the queue and the memory system isnt busy from a previous operation, process + -- the queue item. + -- + elsif (mxFifoWriteIdx - mxFifoReadIdx) > 0 then + + -- Setup the address from the queue element and process the command. + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + end if; + mxHoldCycles <= 1; + + case mxFifo(to_integer(mxFifoReadIdx)).cmd is + -- Read to TOS + when MX_CMD_READTOS => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_TOS; + + -- Read to NOS + when MX_CMD_READNOS => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_NOS; + + -- Read both TOS and NOS (save cycles). + when MX_CMD_READTOSNOS => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_TOSNOS; + + -- Read Byte to TOS + when MX_CMD_READBYTETOTOS => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_ReadByteToTOS; + + -- Read Word to TOS + when MX_CMD_READWORDTOTOS => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_ReadWordToTOS; + + -- Read word and add to TOS + when MX_CMD_READADDTOTOS => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_ReadAddToTOS; + + -- Write value to address + when MX_CMD_WRITE => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_DAT_O <= mxFifo(to_integer(mxFifoReadIdx)).data; + WB_WE_O <= '1'; + wbXactActive <= '1'; + else + MEM_DATA_OUT <= mxFifo(to_integer(mxFifoReadIdx)).data; + MEM_WRITE_ENABLE <= '1'; + end if; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_BIT_RANGE)); + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + mxState <= MemXact_Idle; + mxHoldCycles <= 0; + + -- Read value at address, then write data to the value's address. + when MX_CMD_WRITETOINDADDR => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_WE_O <= '0'; + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_WriteToAddr; + + -- To write a byte, if hardware supports it, write out to the byte aligned address with data in bits 7-0 otherwise + -- we first read the 32bit word, update it and write it back. + when MX_CMD_WRITEBYTETOADDR => + -- If Hardware byte write not implemented or it is a write to the Startup ROM we have to resort + -- to a read-modify-write operation. + if IMPL_HW_BYTE_WRITE = false + then + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_32BIT_RANGE)) & "00"; + mxState <= MemXact_WriteByteToAddr; + else + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_DAT_O <= (others => 'X'); + case mxFifo(to_integer(mxFifoReadIdx)).addr(1 downto 0) is + when "00" => + WB_SEL_O <= "1000"; + WB_DAT_O(31 downto 24) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + when "01" => + WB_SEL_O <= "0100"; + WB_DAT_O(23 downto 16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + when "10" => + WB_SEL_O <= "0010"; + WB_DAT_O(15 downto 8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + when "11" => + WB_SEL_O <= "0001"; + WB_DAT_O(7 downto 0) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + end case; + + WB_ADR_O(ADDR_32BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0)<= (others => '0'); + WB_WE_O <= '1'; + wbXactActive <= '1'; + else + MEM_ADDR(ADDR_BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_BIT_RANGE); + MEM_WRITE_ENABLE <= '1'; + MEM_DATA_OUT <= X"000000" & mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0); + MEM_WRITE_BYTE <= '1'; + end if; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + mxHoldCycles <= 0; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_BIT_RANGE)); + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2WriteByte <= '1'; + cacheL2Write <= '1'; + end if; + end if; + + -- To write a word, if hardware supports it, write out to the word aligned address with data in bits 15-0 otherwise + -- we first read the 32bit word, update it and write it back. + when MX_CMD_WRITEHWORDTOADDR => + -- If Hardware half-word write not implemented or it is a write to the Startup ROM we have to resort + -- to a read-modify-write operation. + if IMPL_HW_WORD_WRITE = false + then + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_32BIT_RANGE)) & "00"; + mxState <= MemXact_WriteHWordToAddr; + else + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_DAT_O <= (others => 'X'); + case mxFifo(to_integer(mxFifoReadIdx)).addr(1) is + when '0' => + WB_SEL_O <= "1100"; + WB_DAT_O(31 downto 16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + when '1' => + WB_SEL_O <= "0011"; + WB_DAT_O(15 downto 0) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + end case; + WB_ADR_O(ADDR_32BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0)<= (others => '0'); + WB_WE_O <= '1'; + wbXactActive <= '1'; + else + MEM_ADDR(ADDR_BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_16BIT_RANGE) & "0"; + MEM_WRITE_ENABLE <= '1'; + MEM_DATA_OUT <= X"0000" & mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0); + MEM_WRITE_HWORD <= '1'; + end if; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_BIT_RANGE)); + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2WriteHword <= '1'; + cacheL2Write <= '1'; + end if; + mxHoldCycles <= 0; + end if; + + when others => + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end case; + end if; + + when MemXact_MemoryFetch => + if DEBUG_CPU = true then + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxMemVal.word <= unsigned(WB_DAT_I); + else + mxMemVal.word <= unsigned(MEM_DATA_IN); + end if; + mxMemVal.valid <= '1'; + end if; + mxState <= MemXact_Idle; + + when MemXact_OpcodeFetch => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + cacheL2WriteData <= WB_DAT_I; + else + cacheL2WriteData <= MEM_DATA_IN; + end if; + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + cacheL2IncAddr <= '1'; + mxState <= MemXact_Idle; + + when MemXact_TOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word <= unsigned(WB_DAT_I); + else + mxTOS.word <= unsigned(MEM_DATA_IN); + end if; + mxTOS.valid <= '1'; + if cacheL2Active = '1' then + mxHoldCycles <= 1; + end if; + mxState <= MemXact_Idle; + + when MemXact_NOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxNOS.word <= unsigned(WB_DAT_I); + else + mxNOS.word <= unsigned(MEM_DATA_IN); + end if; + mxNOS.valid <= '1'; + if cacheL2Active = '1' then + mxHoldCycles <= 1; + end if; + mxState <= MemXact_Idle; + + when MemXact_TOSNOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word <= unsigned(WB_DAT_I); + else + mxTOS.word <= unsigned(MEM_DATA_IN); + MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE))) + 1, ADDR_32BIT_SIZE)); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE <= '1'; + mxHoldCycles <= 1; + end if; + mxTOS.valid <= '1'; + mxState <= MemXact_TOSNOS_2; + + when MemXact_TOSNOS_2 => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE))) + 1, ADDR_32BIT_SIZE)); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxState <= MemXact_TOSNOS_3; + else + mxNOS.word <= unsigned(MEM_DATA_IN); + mxNOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + if cacheL2Active = '1' then + mxHoldCycles <= 1; + end if; + + when MemXact_TOSNOS_3 => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxNOS.word <= unsigned(WB_DAT_I); + mxNOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + + when MemXact_ReadByteToTOS => + mxTOS.word <= (others => '0'); + if wbXactActive = '1' then + mxTOS.word(7 downto 0) <= unsigned(WB_DAT_I(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8)); + else + mxTOS.word(7 downto 0) <= unsigned(MEM_DATA_IN(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8)); + end if; + mxTOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_ReadWordToTOS => + mxTOS.word <= (others => '0'); + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word(15 downto 0) <= unsigned(WB_DAT_I(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16)); + else + mxTOS.word(15 downto 0) <= unsigned(MEM_DATA_IN(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16)); + end if; + mxTOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_ReadAddToTOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word <= muxTOS.word + unsigned(WB_DAT_I); + else + mxTOS.word <= muxTOS.word + unsigned(MEM_DATA_IN); + end if; + mxTOS.valid <= '1'; + mxState <= MemXact_Idle; + + when MemXact_WriteToAddr => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= WB_DAT_I(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_DAT_O <= mxFifo(to_integer(mxFifoReadIdx)).data; + WB_WE_O <= '1'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + cacheL2WriteAddr <= unsigned(WB_DAT_I(L2CACHE_BIT_RANGE)); + else + MEM_ADDR(ADDR_32BIT_RANGE) <= MEM_DATA_IN(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_DATA_OUT <= mxFifo(to_integer(mxFifoReadIdx)).data; + MEM_WRITE_ENABLE <= '1'; + cacheL2WriteAddr <= unsigned(MEM_DATA_IN(L2CACHE_BIT_RANGE)); + end if; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_WriteByteToAddr => + -- For wishbone, we need to store the data and terminate the current cycle before we can commence a write cycle. + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + WB_DAT_O <= WB_DAT_I; + WB_DAT_O(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + cacheL2WriteData <= WB_DAT_I; + mxState <= MemXact_WriteByteToAddr2; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_DATA_OUT <= MEM_DATA_IN; + MEM_DATA_OUT(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + MEM_WRITE_ENABLE <= '1'; + cacheL2WriteData <= MEM_DATA_IN; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + -- If the data write is to a cached location, we have read the original value, so update cache with modified version. + if cacheL2MxAddrInCache = '1' then + -- Update the data to write with the actual changed byte, + cacheL2WriteData(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + + when MemXact_WriteByteToAddr2 => + if IMPL_USE_WB_BUS = true then + WB_ADR_O(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '1'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + + when MemXact_WriteHWordToAddr => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + WB_DAT_O <= WB_DAT_I; + WB_DAT_O(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + cacheL2WriteData <= WB_DAT_I; + mxState <= MemXact_WriteHWordToAddr2; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_DATA_OUT <= MEM_DATA_IN; + MEM_DATA_OUT(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + cacheL2WriteData <= MEM_DATA_IN; + MEM_WRITE_ENABLE <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + -- If the data write is to a cached location, we have read the original value, so update cache with modified version. + if cacheL2MxAddrInCache = '1' then + -- Update the data to write with the actual changed byte, + cacheL2WriteData(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + + when MemXact_WriteHWordToAddr2 => + if IMPL_USE_WB_BUS = true then + WB_ADR_O(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '1'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + + when others => + end case; + end if; + + -- Instruction Level 2 cache, we read upto the limit then back off until the gap between executed and read instructions + -- gets to a watermark and then re-enable reading. This allows the cache to maintain a set of past and future instructions so that when a + -- branch or call occurs, there is a chance we already have the needed instructions in cache. + -- + if cacheL2Active = '1' then + + -- If L2 fetching has been halted and the PC approaches the threshold (detault 3/4) then advance the Start Address of L2 data and re-enable L2 filling. + if cacheL2FetchIdx(ADDR_32BIT_RANGE) > pc(ADDR_32BIT_RANGE) and pc(ADDR_32BIT_RANGE) > cacheL2StartAddr(ADDR_32BIT_RANGE) and (pc - cacheL2StartAddr) > ((MAX_L2CACHE_SIZE/4)*3) and cacheL2Full = '1' then + cacheL2StartAddr <= cacheL2StartAddr + 16; + end if; + + -- If the PC goes out of scope of L2 data, reset and start fetching a fresh from the current PC address. + if cacheL2Invalid = '1' then + cacheL2FetchIdx <= pc(ADDR_32BIT_RANGE) & "00"; + cacheL2StartAddr <= pc(ADDR_32BIT_RANGE) & "00"; + cacheL2Write <= '0'; + cacheL2IncAddr <= '0'; + if (mxFifoWriteIdx - mxFifoReadIdx) = 0 and (mxState = MemXact_Idle or mxState = MemXact_OpcodeFetch) then + mxState <= MemXact_Idle; + end if; + end if; + end if; + end if; + end process; + + -- Use a mux to get the latest TOS/NOS values. This saves 1 clock cycle between data being retrieved and processed. + muxTOS.valid <= mxTOS.valid or TOS.valid; + muxTOS.word <= mxTOS.word when mxTOS.valid = '1' else TOS.word; + muxNOS.valid <= mxNOS.valid or NOS.valid; + muxNOS.word <= mxNOS.word when mxNOS.valid = '1' else NOS.word; + ----------------------------------------------------------------------------------------------------------------------------------------------------------------- + + ------------------------------------------------------------------------------ + -- L1 Cache + -- + -- L1 cache is a very small closely coupled cache which holds a decoded + -- shadow copy of the L2 cache or the BRAM at the point of execution and a few + -- instructions ahead. It is implemented in logic cells to allow instant + -- random access. This is required to perform instruction optimisation such as + -- multiple IM's and also to allow extended 2+ byte instructions which have + -- almost zero penalty over 1 byte instructions. + ------------------------------------------------------------------------------ + CACHE_LEVEL1: process(CLK, ZPURESET, pc) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable tDecodedOpcode : InsnType; + variable tInsnOffset : unsigned(4 downto 0); + begin + + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if ZPURESET = '1' then + cacheL1StartAddr <= (others => '0'); + cacheL1FetchIdx <= (others => '0'); + l1State <= State_PreSetAddr; + MEM_READ_ENABLE_INSN <= '0'; + MEM_ADDR_INSN <= (others => DontCareValue); + + ------------------------ + -- FALLING CLOCK EDGE -- + ------------------------ + elsif falling_edge(CLK) then + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(CLK) then + + -- If the cache becomes invalid due to a change in the PC or no cached data available then resync. + if (cacheL1Invalid = '1' and cacheL1Empty = '0') then -- or (cacheL2Active = '1' and cacheL2Invalid = '1') then + + -- RESYNC L1 Cache with BRAM/L2 Cache starting at current PC value.. + cacheL1FetchIdx <= pc(ADDR_32BIT_RANGE) & "00"; + cacheL1StartAddr <= pc(ADDR_32BIT_RANGE) & "00"; + + -- For BRAM preset the next address. + if cacheL2Active = '0' then + MEM_ADDR_INSN(ADDR_32BIT_RANGE) <= std_logic_vector(pc(ADDR_32BIT_RANGE)); + MEM_ADDR_INSN(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE_INSN <= '1'; + --else for L2 the address is automatically set in cacheL1FetchIdx + end if; + + -- State machine goes directly to the latch address phase. + l1State <= State_LatchAddr; + + -- If there is space in the L1 cache and data is available in the L2 cache/BRAM and we are not outputting debug information, fetch the next word, decode and place in L1. + elsif cacheL1Full = '0' + and + -- If BRAM ensure the memory is ready, for L2 no need to wait as the pointers control the reading of L2 data. + ((cacheL2Active = '0' and MEM_BUSY_INSN = '0') or (cacheL2Active = '1')) + and + -- If using L2 cache then only process when cached data is available in L2. + (cacheL2Active = '0' or (cacheL2Active = '1' and cacheL2Empty = '0' and cacheL2FetchIdx(ADDR_32BIT_RANGE) > cacheL1FetchIdx(ADDR_32BIT_RANGE)+1 )) + and + -- If debugging, only process if the debug FSM is idle as the L2 address is muxed with the debug address. + ((DEBUG_CPU = false or (DEBUG_CPU = true and debugState = Debug_Idle))) then + + case l1State is + when State_PreSetAddr => + -- For BRAM, set the address to read, external memory via L2 cache is set by the cacheL1FetchIdx signal. + if cacheL2Active = '0' then + MEM_ADDR_INSN(ADDR_32BIT_RANGE) <= std_logic_vector(pc(ADDR_32BIT_RANGE)); + MEM_ADDR_INSN(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE_INSN <= '1'; + --else for L2 the address is automatically set in cacheL1FetchIdx + end if; + l1State <= State_LatchAddr; + + -- This state gives time for the BRAM/L2 to latch the address ready for decode. + when State_LatchAddr => + l1State <= State_Decode; + + when State_Decode => + -- Read cycle for BRAM is at least one clock, so on next cycle clear the BRAM read signal. + if cacheL2Active = '0' then + MEM_READ_ENABLE_INSN <= '0'; + -- else for L2 there is no distinct signal, always outputs data for given input address. + end if; + + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + if cacheL2Active = '0' then + tOpcode := MEM_DATA_IN_INSN((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + else + tOpcode := cacheL2Word((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + end if; + + tInsnOffset(4) := not tOpcode(4); + tInsnOffset(3 downto 0) := unsigned(tOpcode(3 downto 0)); + + if (tOpcode(7 downto 7) = OpCode_Im) then tDecodedOpcode := Insn_Im; + + elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then tDecodedOpcode := Insn_StoreSP; + + elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then tDecodedOpcode := Insn_LoadSP; + + -- Emulated instructions, if there is no defined state to handle the instruction in hardware then it automatically runs the instruction + -- microcode from the vector 0x0+xxxxx*32. + elsif (tOpcode(7 downto 5) = OpCode_Emulate) then tDecodedOpcode := Insn_Emulate; + + if tOpcode(5 downto 0) = OpCode_Neqbranch then tDecodedOpcode := Insn_Neqbranch; + elsif tOpcode(5 downto 0) = OpCode_Eqbranch then tDecodedOpcode := Insn_Eqbranch; + elsif IMPL_EQ = true and tOpcode(5 downto 0) = OpCode_Eq then tDecodedOpcode := Insn_Eq; + elsif tOpcode(5 downto 0) = OpCode_Lessthan then tDecodedOpcode := Insn_Lessthan; + elsif tOpcode(5 downto 0) = OpCode_Lessthanorequal then tDecodedOpcode := Insn_Lessthanorequal; + elsif tOpcode(5 downto 0) = OpCode_Ulessthan then tDecodedOpcode := Insn_Ulessthan; + elsif tOpcode(5 downto 0) = OpCode_Ulessthanorequal then tDecodedOpcode := Insn_Ulessthanorequal; + elsif IMPL_LOADB = true and tOpcode(5 downto 0) = OpCode_Loadb then tDecodedOpcode := Insn_Loadb; + elsif IMPL_LOADH = true and tOpcode(5 downto 0) = OpCode_Loadh then tDecodedOpcode := Insn_Loadh; + elsif IMPL_MULT = true and tOpcode(5 downto 0) = OpCode_Mult then tDecodedOpcode := Insn_Mult; + elsif IMPL_STOREB = true and tOpcode(5 downto 0) = OpCode_Storeb then tDecodedOpcode := Insn_Storeb; + elsif IMPL_STOREH = true and tOpcode(5 downto 0) = OpCode_Storeh then tDecodedOpcode := Insn_Storeh; + elsif IMPL_PUSHSPADD = true and tOpcode(5 downto 0) = OpCode_Pushspadd then tDecodedOpcode := Insn_Pushspadd; + elsif IMPL_CALLPCREL = true and tOpcode(5 downto 0) = OpCode_Callpcrel then tDecodedOpcode := Insn_Callpcrel; + elsif IMPL_CALL = true and tOpcode(5 downto 0) = OpCode_Call then tDecodedOpcode := Insn_Call; + elsif IMPL_SUB = true and tOpcode(5 downto 0) = OpCode_Sub then tDecodedOpcode := Insn_Sub; + elsif IMPL_POPPCREL = true and tOpcode(5 downto 0) = OpCode_PopPCRel then tDecodedOpcode := Insn_PopPCRel; + elsif IMPL_LSHIFTRIGHT = true and tOpcode(5 downto 0) = OpCode_Lshiftright then tDecodedOpcode := Insn_Alshift; + elsif IMPL_ASHIFTLEFT = true and tOpcode(5 downto 0) = OpCode_Ashiftleft then tDecodedOpcode := Insn_Alshift; + elsif IMPL_ASHIFTRIGHT = true and tOpcode(5 downto 0) = OpCode_Ashiftright then tDecodedOpcode := Insn_Alshift; + elsif IMPL_XOR = true and tOpcode(5 downto 0) = OpCode_Xor then tDecodedOpcode := Insn_Xor; + elsif IMPL_DIV = true and tOpcode(5 downto 0) = OpCode_Div then tDecodedOpcode := Insn_Div; + elsif IMPL_MOD = true and tOpcode(5 downto 0) = OpCode_Mod then tDecodedOpcode := Insn_Mod; + elsif IMPL_NEG = true and tOpcode(5 downto 0) = OpCode_Neg then tDecodedOpcode := Insn_Neg; + elsif IMPL_NEQ = true and tOpcode(5 downto 0) = OpCode_Neq then tDecodedOpcode := Insn_Neq; + elsif IMPL_FIADD32 = true and tOpcode(5 downto 0) = OpCode_FiAdd32 then tDecodedOpcode := Insn_FiAdd32; + elsif IMPL_FIDIV32 = true and tOpcode(5 downto 0) = OpCode_FiDiv32 then tDecodedOpcode := Insn_FiDiv32; + elsif IMPL_FIMULT32 = true and tOpcode(5 downto 0) = OpCode_FiMult32 then tDecodedOpcode := Insn_FiMult32; + + end if; + + elsif (tOpcode(7 downto 4) = OpCode_AddSP) then + if tInsnOffset = 0 then tDecodedOpcode := Insn_Shift; + elsif tInsnOffset = 1 then tDecodedOpcode := Insn_AddTop; + else tDecodedOpcode := Insn_AddSP; + end if; + + -- Extended multibyte instruction set. If the extend instruction is encountered then during the execution phase the lookahead mechanism is used to determine + -- the extended instruction and execute accordingly. + elsif IMPL_EXTENDED_INSN = true and tOpcode(3 downto 0) = Opcode_Extend then tDecodedOpcode := Insn_Extend; + + else + case tOpcode(3 downto 0) is + when OpCode_Nop => tDecodedOpcode := Insn_Nop; + when OpCode_PushSP => tDecodedOpcode := Insn_PushSP; + when OpCode_PopPC => tDecodedOpcode := Insn_PopPC; + when OpCode_Add => tDecodedOpcode := Insn_Add; + when OpCode_Or => tDecodedOpcode := Insn_Or; + when OpCode_And => tDecodedOpcode := Insn_And; + when OpCode_Load => tDecodedOpcode := Insn_Load; + when OpCode_Not => tDecodedOpcode := Insn_Not; + when OpCode_Flip => tDecodedOpcode := Insn_Flip; + when OpCode_Store => tDecodedOpcode := Insn_Store; + when OpCode_PopSP => tDecodedOpcode := Insn_PopSP; + when others => tDecodedOpcode := Insn_Break; + end case; + end if; + + -- Store the decoded op directly into L1 cache. + cacheL1(to_integer(cacheL1FetchIdx+i))(DECODED_RANGE) <= std_logic_vector(to_unsigned(InsnType'POS(tDecodedOpcode), 6)); + cacheL1(to_integer(cacheL1FetchIdx+i))(OPCODE_RANGE) <= tOpcode; + end loop; + + -- Set address for next read, via cacheL1FetchIdx for L2 and external signals for BRAM. NB cacheL1FetchIdx always points to the next + -- available slot except during this state of the decoder. + cacheL1FetchIdx <= cacheL1FetchIdx + wordBytes; + + -- If we are not using L2 cache then take instructions direct from instruction BRAM. If a seperate + -- Instruction BRAM is not implemented, this will be ignored as L2 is our only source. + -- + if cacheL2Active = '0' then + MEM_ADDR_INSN(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL1FetchIdx(ADDR_32BIT_RANGE)+1); + MEM_ADDR_INSN(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE_INSN <= '1'; + --else for L2 the address is automatically set in cacheL1FetchIdx + end if; + + -- Repeat the fetch and decode until the L1 cache is full then disable fetching until a space becomes available. + -- We halt just before the full mark because it takes one cycle to halt. + l1State <= State_LatchAddr; + + when others => + l1State <= State_PreSetAddr; + end case; + + -- If there is only a set number of instructions remaining in the cache then we need to creep the start address forward so that + -- more instructions are fetched and decoded. We do this to ensure as many past instructions are available for backward jumps which + -- are most common in C. Adjust the threshold if forward jumps are more common. + elsif cacheL1InsnAfterPC < 8 and cacheL1Full = '1' then + cacheL1StartAddr <= cacheL1StartAddr + 8; + end if; + end if; + end process; + + -- Description of signals: + -- cacheL1StartAddr Absolute Start Address of word in first cache location. + -- cacheL1FetchIdx Next location a decoded instruction set (4 instructions) will be written into. + -- cacheL1InsnAfterPC Number of instructions stored in cache forward of current PC. + -- cacheL1Empty 1 when cache is empty, 0 when valid data present. + -- cacheL1Invalid 1 when cache doesnt have any valid instructions stored. + -- cacheL1Full 1 when cache is full, 0 otherwise. + -- + cacheL1InsnAfterPC <= cacheL1FetchIdx - pc when cacheL1Invalid = '0' + else to_unsigned(0, cacheL1InsnAfterPC'length); + cacheL1Empty <= '1' when cacheL1FetchIdx(ADDR_32BIT_RANGE) = cacheL1StartAddr(ADDR_32BIT_RANGE) + else '0'; + cacheL1Invalid <= '0' when (cacheL2Active = '0' or (cacheL2Active = '1' and cacheL2Invalid = '0')) and pc(ADDR_32BIT_RANGE) >= cacheL1StartAddr(ADDR_32BIT_RANGE) and pc(ADDR_32BIT_RANGE) < cacheL1FetchIdx(ADDR_32BIT_RANGE) + else '1'; + cacheL1Full <= '1' when cacheL1FetchIdx(ADDR_32BIT_RANGE) - cacheL1StartAddr(ADDR_32BIT_RANGE) = MAX_L1CACHE_SIZE / 4 + else '0'; + ------------------------------------------------------------------------------ + -- End of L1 Cache + ------------------------------------------------------------------------------ + + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Processor - Execution unit. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + PROCESSOR: process(CLK, ZPURESET, TOS, NOS, cacheL1, pc, sp, mxTOS, mxNOS, cacheL1FetchIdx, cacheL1StartAddr, cacheL2Active, cacheL2Empty, inBreak) + variable tSpOffset : unsigned(4 downto 0); + variable tIdx : integer range 0 to 3; + variable tInsnExec : std_logic; + variable tShiftCnt : integer range 0 to 31; + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + -- Prepare general stack possibility addresses, ie. Popped, 2xPopped or Pushed. + -- + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + incPC <= pc + 1; + incIncPC <= pc + 2; + inc3PC <= pc + 3; + inc4PC <= pc + 4; + inc5PC <= pc + 5; + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if ZPURESET = '1' then + inBreak <= '0'; + INT_ACK <= '0'; + INT_DONE <= '0'; + tIdx := 0; + tSpOffset := (others => '0'); + state <= State_Init; + sp <= to_unsigned(STACK_ADDR, maxAddrBit)(ADDR_32BIT_RANGE); + pc <= to_unsigned(RESET_ADDR_CPU, pc'LENGTH); + pcLast <= to_unsigned(RESET_ADDR_CPU, pc'LENGTH); + idimFlag <= '0'; + inInterrupt <= '0'; + mxFifoWriteIdx <= (others => '0'); + interruptSuspendedAddr <= (others => '0'); + TOS <= ((others => '0'), '0'); + NOS <= ((others => '0'), '0'); + -- + if IMPL_DIV = true or IMPL_FIDIV32 = true or IMPL_MOD = true then + divStart <= '0'; + divQuotientFractional <= 0; + end if; + if IMPL_FIADD32 = true or IMPL_FIMULT32 = true then + quotientFractional <= 15; + end if; + if DEBUG_CPU = true then + debugRec <= ZPU_DBG_T_INIT; + debugLoad <= '0'; + debugState <= Debug_Idle; + debugAllInfo <= '0'; + debugPC_StartAddr <= (others => '0'); + debugPC_EndAddr <= (others => '0'); + debugPC_Width <= 32; + debugPC_WidthCounter <= 0; + debugOutputOnce <= '0'; + else + debugPC_StartAddr <= (others => DontCareValue); + debugPC_EndAddr <= (others => DontCareValue); + debugPC_Width <= 32; + debugPC_WidthCounter <= 0; + debugRec <= ZPU_DBG_T_DONTCARE; + debugLoad <= DontCareValue; + debugReady <= DontCareValue; + debugOutputOnce <= DontCareValue; + end if; + + ------------------------ + -- FALLING CLOCK EDGE -- + ------------------------ + elsif falling_edge(CLK) then + + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(CLK) then + + --if DEBUG_CPU = true and debugState = Debug_Idle and pc = X"058be" then + -- debugPC_StartAddr <= X"01fc00"; --to_unsigned(131072-(512*3), debugPC_StartAddr'LENGTH); + -- debugPC_EndAddr <= X"01ff00"; --to_unsigned(131072, debugPC_EndAddr'LENGTH); + -- debugPC_Width <= 4; + -- debugState <= Debug_DumpMem; + --end if; + + if DEBUG_CPU = true and debugState = Debug_Idle and pc = X"1002b67" then --cacheL1FetchIdx < cacheL1FetchIdx_last then + debugState <= Debug_Start; + end if; + + -- In debug mode, the memory dump start and stop address are controlled by 2 vectors, preload them with defaults if uninitialised. + if DEBUG_CPU = true and debugPC_EndAddr = 0 then + debugPC_StartAddr <= to_unsigned(16#1000000#, debugPC_StartAddr'LENGTH); + debugPC_EndAddr <= to_unsigned(16#1001000#, debugPC_EndAddr'LENGTH); + end if; + + -- If the Memory Transaction processor has updated the stack parameters, update our working copy. + -- + if mxTOS.valid = '1' then + TOS.valid <= '1'; + TOS.word <= mxTOS.word; + end if; + if mxNOS.valid = '1' then + NOS.valid <= '1'; + NOS.word <= mxNOS.word; + end if; + + -- If debugging enabled, loading of debug information into the debug serialiser is only 1 clock width wide, reset on each clock tick. + -- + if DEBUG_CPU = true then + debugLoad <= '0'; + end if; + + -- Division start is only 1 clock width wide. + if IMPL_DIV = true or IMPL_FIDIV32 = true or IMPL_MOD = true then + divStart <= '0'; + divQuotientFractional <= 15; -- Always reset the quotient, integer division sets to 0 as no fractional component. + end if; + + -- If interrupt is active, we only clear the interrupt state once the PC is reset to the address which was suspended after the + -- interrupt, this prevents recursive interrupt triggers, desirable in cetain circumstances but not for this current design. + -- + if (INT_REQ = '1' or (IMPL_USE_WB_BUS = true and WB_INTA_I = '1')) and intTriggered = '0' then + intTriggered <= '1'; + end if; + INT_ACK <= '0'; -- Reset interrupt acknowledge if set, width is 1 clock only. + INT_DONE <= '0'; -- Reset interrupt done if set, width is 1 clock only. + if inInterrupt = '1' and pc(ADDR_BIT_RANGE) = interruptSuspendedAddr(ADDR_BIT_RANGE) then + inInterrupt <= '0'; -- no longer in an interrupt + INT_DONE <= '1'; -- Interrupt service routine complete. + end if; + + -- BREAK signal follows internal signal on clock edge. + BREAK <= inBreak; + + ------------------------------------- + -- Execution Processor. + ------------------------------------- + if (DEBUG_CPU = false or (DEBUG_CPU = true and debugReady = '1')) then + + case state is + -- If the emulation cache is implemented, initialise it else startup the CPU. + when State_Init => + state <= State_Idle; + + -- Idle the CPU if ENABLE signal is low. + -- + when State_Idle => + if ENABLE = '1' then + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + + if DEBUG_CPU = true and DEBUG_LEVEL >= 4 and debugState = Debug_Idle then + debugPC_StartAddr <= to_unsigned(0, debugPC_StartAddr'LENGTH); + debugPC_EndAddr <= to_unsigned(65536, debugPC_EndAddr'LENGTH); + debugState <= Debug_DumpMem; + end if; + end if; + + -- Each instruction must: + -- + -- 1. set idimFlag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + when State_Execute => + + -- If the debug state machine is outputting data, hold off from further actions. + if DEBUG_CPU = true and debugState /= Debug_Idle then + + -- When a break is active, all processing is suspended. + elsif inBreak = '1' then + + -- If continue flag set, resume with next instruction. + if CONTINUE = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + inBreak <= '0'; + end if; + + -- Act immediately if an interrupt has occurred. Do not recurse into ISR while interrupt line is active + elsif intTriggered = '1' and inInterrupt = '0' and idimFlag = '0' then + + -- We have to wait for TOS and NOS to become valid so they can be saved, so loop until they are valid. + if muxTOS.valid = '1' and muxNOS.valid = '1' then + -- We got an interrupt, execute interrupt instead of next instruction + intTriggered <= '0'; + inInterrupt <= '1'; + INT_ACK <= '1'; -- Acknowledge interrupt. + interruptSuspendedAddr <= pc(ADDR_BIT_RANGE); -- Save address which got interrupted. + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= pc; + NOS.word <= muxTOS.word; + pc <= to_unsigned(32+START_ADDR_MEM, maxAddrBit); -- Load Vector 0x20 (from memory start) as next address to execute from. + sp <= decSp; + + -- Setup a memory transaction to save NOS back to RAM, TOS in effect already popped. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- If debug enabled, write out state during fetch. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(6, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"494D544552505400"; + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end if; + + -- If the CPU is externally disabled during processing, go to the Idle state and wait until it is re-enabled. + -- + elsif ENABLE = '0' then + state <= State_Idle; + + -- Execution depends on the L1 having decoded instructions stored at the current PC. + -- As a minimum the cache must be valid and that there is at least 1 instruction in the cache. + elsif cacheL1Invalid = '0' and cacheL1InsnAfterPC > 4 then -- and (cacheL2Active = '0' or (cacheL2Active = '1' and cacheL2Full = '1')) then + + -- Remember the last PC location executed, used for jump detection. + pcLast <= pc; + + -- Set the stack offset for current instruction from its opcode. + tSpOffset(4) := not cacheL1(to_integer(pc))(4); + tSpOffset(3 downto 0) := unsigned(cacheL1(to_integer(pc)))(3 downto 0); + tInsnExec := '0'; + if DEBUG_CPU = true then + debugOutputOnce <= '0'; + end if; + + -------------------------------------------------------------------------------------------------------------- + -- Start of Instruction Execution Case block - process the current instruction held in L1 Cache. + -------------------------------------------------------------------------------------------------------------- + case InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE)))) is + + -- Immediate, store 7bit signed extended value into TOS. If this is the first Im then we set IDIM, if this is a subsequent Im following + -- on from other Im's without gap, then we shift TOS 7 bits to left and add in the new value. NB. First Im, bit 6 of bits 6-0 is used to set + -- all bits 31 downto 6 with the same value. + -- An optimisation has been added where by if more than 1 Im are sequential and in the L1 cache, then the result is calculated in 1 cycle. If due + -- to not enough cache data a > 1 Im is partially processed, ie. 3 Im out of 5, then the 3 are processed in 1 cycle and the remaining two in seperate + -- cycles. + when Insn_Im => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '1'; + pc <= incPC; + + -- If this is the first Im (single or non-cached) or this is a multi Im instruction, save current TOS and build new TOS from Im. + -- + if idimFlag = '0' then + -- As we are pushing a value, current TOS becomes NOS and we write back old NOS to memory. + NOS.word <= muxTOS.word; + sp <= decSp; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- All Im combinations sign extend the 7th bit of the first Im instruction then just overwrite the bits available. + --if cacheL1(to_integer(pc))(6) = '1' then + -- TOS.word <= "11111111111111111111111110000000"; + --else + -- TOS.word <= (others => '0'); + --end if; + for i in wordSize-1 downto 7 loop + TOS.word(i) <= cacheL1(to_integer(pc))(6); + end loop; + + -- For non-optimised hardware or optimised but we only have 1 Im, used the original logic. + if IMPL_OPTIMIZE_IM = false then + TOS.word(IM_DATA_RANGE) <= unsigned(cacheL1(to_integer(pc))(IM_DATA_RANGE)); + + -- If Im optimisation is enabled, work out if we have sufficient instructions and then determine how many Ims are grouped together, otherwise default to just 1 Im per time processing. + elsif IMPL_OPTIMIZE_IM = true then + + -- Debug code, if enabled, writes out the data relevant to the Im instruction being optimised. + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 and cacheL1FetchIdx(L1CACHE_BIT_RANGE) - pc(L1CACHE_BIT_RANGE) > 2 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA2(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.DATA3(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)); + debugRec.DATA4(63 downto 0) <= "0000000000000000" & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 16)) & std_logic_vector(cacheL2FetchIdx(15 downto 0)) & "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & "0000" & idimFlag & tInsnExec & cacheL2Full & cacheL2Write; + debugRec.OPCODE <= (others => DontCareValue); + debugRec.DECODED_OPCODE <= (others => DontCareValue); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + + -- TODO: + -- Perhaps use cacheL1InsnAfterPC in this loop to preserve logic. + -- Same for extended instructions. + -- + -- 5 Consecutive IM's + --if cacheL1FetchIdx - pc > 5 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '1' and cacheL1(to_integer(inc4PC))(7) = '1' and cacheL1(to_integer(inc5PC))(7) = '0' then + if cacheL1InsnAfterPC > 5 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '1' and cacheL1(to_integer(inc4PC))(7) = '1' and cacheL1(to_integer(inc5PC))(7) = '0' then + TOS.word(31 downto 0) <= unsigned(cacheL1(to_integer(pc))(3 downto 0)) & unsigned(cacheL1(to_integer(incPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incIncPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(inc3PC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(inc4PC))(OPCODE_IM_RANGE)); + pc <= inc5PC; + -- 4 Consecutive IM's + --elsif cacheL1FetchIdx - pc > 4 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '1' and cacheL1(to_integer(inc4PC))(7) = '0' then + elsif cacheL1InsnAfterPC > 4 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '1' and cacheL1(to_integer(inc4PC))(7) = '0' then + TOS.word(27 downto 0) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incIncPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(inc3PC))(OPCODE_IM_RANGE)); + pc <= inc4PC; + -- 3 Consecutive IM's + elsif cacheL1InsnAfterPC > 3 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '1' and cacheL1(to_integer(inc3PC))(7) = '0' then + TOS.word(20 downto 0) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incPC))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incIncPC))(OPCODE_IM_RANGE)); + pc <= inc3PC; + -- 2 Consecutive IM's + elsif cacheL1InsnAfterPC > 2 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(incPC))(7) = '1' and cacheL1(to_integer(incIncPC))(7) = '0' then + TOS.word(13 downto 0) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(incPC))(OPCODE_IM_RANGE)); + pc <= incIncPC; + -- 1 IM + else + TOS.word(IM_DATA_RANGE) <= unsigned(cacheL1(to_integer(pc))(OPCODE_RANGE)(IM_DATA_RANGE)); + end if; + end if; + else + -- Further single Im instructions shift left by 7 bits then add it the value from the current opcode. + TOS.word(wordSize-1 downto 7) <= muxTOS.word(wordSize-8 downto 0); + TOS.word(IM_DATA_RANGE) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)); + end if; + end if; + + -- Store into Stack pointer + offset, write out the value in TOS to the location pointed by Stack pointer plus any offset given in the opcode. + when Insn_StoreSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + tIdx := 0; + idimFlag <= '0'; + sp <= incSp; + pc <= incPC; + + -- Always need to read the new NOS location into NOS unless the offset is 2 when the location will be + -- overwritten with TOS, so just use TOS. + if tSpOffset /= 2 then + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + tIdx := tIdx + 1; + end if; + + -- Write value of TOS to the memory location sp + offset stored in opcode if offset not 0 or 1. + -- + if tSpOffset >= 2 then + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).addr(ADDR_32BIT_RANGE)<= std_logic_vector(sp+tSpOffset); + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).data<= std_logic_vector(muxTOS.word); + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).cmd <= MX_CMD_WRITE; + tIdx := tIdx + 1; + end if; + + case tSpOffset is + -- If the offset is 0, we are writing into unused stack (as the stack pointer is incremented), so just assign + -- NOS to TOS and read the new NOS. + when "00000" => + TOS.word <= muxNOS.word; + + -- If the offset is 1 then we do nothing as a write of TOS to SP+1 is the location of the new TOS, so TOS doesnt change. + -- We read NOS though from the new location. + when "00001" => + + -- When offset is 2, TOS is written to the new NOS position in memory, so no point to reread, we just reuse TOS. + -- + when "00010" => + NOS.word <= muxTOS.word; + TOS.word <= muxNOS.word; + + -- All other cases TOS becomes NOS and we read the new NOS . + -- + when others => + TOS.word <= muxNOS.word; + end case; + + mxFifoWriteIdx <= mxFifoWriteIdx + tIdx; + end if; + + -- Load from Stack pointer + offset: save NOS onto stack (TOS is popped and no longer needed so we are not concerned), read into TOS + -- the value pointed to by the SP + Offset. NOS becomes the old TOS as we virtually pushed the read value onto the stack. + when Insn_LoadSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + sp <= decSp; + pc <= incPC; + + -- Commit NOS to memory as we will refresh NOS from TOS. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- If the offset is 0 then we are duplicating TOS into NOS. + if tSpOffset = 0 then + NOS.word <= muxTOS.word; + + -- If the offset is 1 then we are duplicating NOS into TOS. + elsif tSpOffset = 1 then + TOS.word <= muxNOS.word; + NOS.word <= muxTOS.word; + + -- Else we read the value at Sp + Offset into TOS. + else + -- Read TOS from the location pointed to by SP + Offset. + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_32BIT_RANGE) <= std_logic_vector(sp+tSpOffset); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_READTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + + -- NOS becomes TOS as we are pushing a new value onto the stack. + NOS.word <= muxTOS.word; + end if; + end if; + + -- Emulate. This is a dummy placeholder for instructions which have not been implemented in hardware. If an Opcode cannot be translated to + -- a state machine state, it falls through to here, the NOS is saved back onto the stack, TOS is set to NOS and TOS takes on + -- the next program counter value (ie. next instruction after the one which is not implemented). The Program counter is then set + -- to the vector containing the microcode to implement the instruction and a jump is made to that location. When the microcode is complete it + -- should set the Program counter to the value stored in TOS. + when Insn_Emulate => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + sp <= decSp; + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= incPC; + NOS.word <= muxTOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- The emulate address is calculated by the opcode value left shifted 5 places. If the BRAM start address is not zero then this is added to ensure the + -- emulation microcode is read form the BRAM: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= to_unsigned(to_integer(unsigned(cacheL1(to_integer(pc))(OPCODE_RANGE)(4 downto 0)) & "00000"), pc'LENGTH) + START_ADDR_MEM; + end if; + + -- Call function relative to current PC value. The Program counter for the next instruction after this (ie. call return address) is stored in TOS + -- and the Program counter is set to the value currently in TOS+PC (remember that assignments only occur at end of the cycle, so writing to TOS wont + -- actually happen until the moment we leave this cycle) and we start processing from the new Program counter location, or the called location. + when Insn_Callpcrel => + if IMPL_CALLPCREL = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= incPC; + pc <= pc + muxTOS.word(ADDR_BIT_RANGE); + end if; + end if; + + -- Call function. Same as above except the PC is set to the value stored in TOS, not TOS+PC. + when Insn_Call => + if IMPL_CALL = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= incPC; + pc <= muxTOS.word(ADDR_BIT_RANGE); + end if; + end if; + + -- Add value from location pointed to bye Stack Pointer. Setup to read the value stored at Stack pointer location + offset contained + -- in the OpCode. We then forward to the next state which adds the value read to the value stored in TOS. + when Insn_AddSP => + -- if TOS.valid = '1' and NOS.valid = '1' then + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(sp+tSpOffset); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READADDTOTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Push stack pointer. TOS is set to stack pointer value and old TOS value assigned to NOS. The current NOS value is written out + -- onto the stack. In effect TOS = sp, NOS = TOS and NOS stored to NOS-1, we accomplish a push stack pointer onto the stack. + when Insn_PushSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= decSp; + TOS.word <= (others => '0'); + TOS.word(ADDR_32BIT_RANGE) <= sp; + NOS.word <= muxTOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Pop the value on the stack into the Program counter. This is accomplished by setting the PC to the TOS value, then writing out the + -- NOS value (because NOS and TOS are not normally stored, they are held in register) and performing a resync. + when Insn_PopPC => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= muxTOS.word(ADDR_BIT_RANGE); + sp <= incSp; + TOS.word <= muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Same as above except the program counter is added to the value in TOS before being assigned to the next program counter value. + when Insn_PopPCRel => + if IMPL_POPPCREL = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= pc + muxTOS.word(ADDR_BIT_RANGE); + sp <= incSp; + TOS.word <= muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Add NOS to TOS and store into TOS. NOS is then read from the stack. + when Insn_Add => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxTOS.word + muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Subtract NOS from TOS and store into TOS. NOS is then read from the stack. + when Insn_Sub => + if IMPL_SUB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxNOS.word - muxTOS.word; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform a logical OR between TOS and NOS and store the result in TOS. We then retrieve the next stack value into NOS. + when Insn_Or => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxTOS.word or muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a logical AND between TOS and NOS and store the result in TOS. We then retrieve the next stack value into NOS. + when Insn_And => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxTOS.word and muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a Equal comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next stack value into NOS. + when Insn_Eq => + if IMPL_EQ = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (muxTOS.word = muxNOS.word) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform an unsigned less than comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next stack value into NOS. + when Insn_Ulessthan => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (muxTOS.word < muxNOS.word) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform an unsigned less than or equal comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next + -- stack value into NOS. + when Insn_Ulessthanorequal => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (muxTOS.word <= muxNOS.word) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a signed less than comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next stack value into NOS. + when Insn_Lessthan => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (signed(muxTOS.word) < signed(muxNOS.word)) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a signed less than or equal comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next + -- stack value into NOS. + when Insn_Lessthanorequal => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (signed(muxTOS.word) <= signed(muxNOS.word)) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Load TOS (next cycle) with the value pointed to by TOS. + when Insn_Load => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Write the NOS value to the memory location pointed by TOS. + when Insn_Store => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incIncSp; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE)<= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + + -- Write the NOS value into memory location pointed to by the current Stack Pointer - 1 (ie. next of stack), + -- then set the Stack Pointer to the current TOS value. + when Insn_PopSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= muxTOS.word(ADDR_32BIT_RANGE); + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + + -- No operation, just waste time. + when Insn_Nop => + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + -- Negate the TOS value. + when Insn_Not => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word <= not muxTOS.word; + end if; + + -- Reverse all the bits in the TOS. + when Insn_Flip => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + for i in 0 to wordSize-1 loop + TOS.word(i) <= muxTOS.word(wordSize-1-i); + end loop; + end if; + + -- Add the TOS and NOS together, store in the TOS. + when Insn_AddTop => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word <= muxTOS.word + muxNOS.word; + end if; + + -- Shift the TOS right 1 bit. + when Insn_Shift => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word(wordSize-1 downto 1) <= muxTOS.word(wordSize-2 downto 0); + TOS.word(0) <= '0'; + end if; + + -- Add the TOS to the Stack Pointer and store in TOS. This is word aligned so bits 0 & 1 are zero. + when Insn_Pushspadd => + if IMPL_PUSHSPADD = true then + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word <= (others => '0'); + TOS.word(ADDR_32BIT_RANGE) <= muxTOS.word((maxAddrBit-1)-minAddrBit downto 0)+sp; + end if; + end if; + + -- If the NOS is not 0 (or 0 for Eq) then add the TOS to the Program Counter. As the address is not guaranteed to be sequential, resync to + -- retrieve the new TOS / NOS (because they are both now invalid) and the new program instruction. If the NOS is 0 then just + -- retrieve the new TOS / NOS. + when Insn_Neqbranch | Insn_Eqbranch => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + -- branches are almost always taken as they form loops + idimFlag <= '0'; + sp <= incIncSp; + + if (InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE)))) = Insn_Neqbranch and muxNOS.word /= 0) or (InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE)))) = Insn_Eqbranch and NOS.word = 0) then + pc <= pc + muxTOS.word(ADDR_BIT_RANGE); + else + pc <= incPC; + end if; + + -- need to fetch stack again. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Set in motion a signed multiplication of the TOS * NOS. + when Insn_Mult => + if IMPL_MULT = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_Mult2; + multResult <= muxTOS.word * muxNOS.word; + end if; + end if; + + -- Set in motion a signed division of the TOS / NOS. + when Insn_Div => + if IMPL_DIV = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + divStart <= '1'; + divQuotientFractional <= 0; + state <= State_Div2; + end if; + end if; + + -- Set in motion a fixed point addition of the TOS / NOS. + when Insn_FiAdd32 => + if IMPL_FIADD32 = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_FiAdd2; + end if; + end if; + + -- Set in motion a fixed point division of the TOS / NOS. + when Insn_FiDiv32 => + if IMPL_FIDIV32 = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_FiDiv2; + end if; + end if; + + -- Set in motion a fixed point multiplication of the TOS / NOS. + when Insn_FiMult32 => + if IMPL_FIMULT32 = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_FiMult2; + end if; + end if; + + -- Read the aligned word pointed to by the TOS and then process in the next state to extract just the required byte. + when Insn_Loadb => + if IMPL_LOADB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READBYTETOTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Read the aligned dword pointed to by the TOS and update just the one required byte, + -- The loadb and storeb can be sped up by implementing hardware byte read/write. + when Insn_Storeb => + if IMPL_STOREB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incIncSp; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)+1).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_WRITEBYTETOADDR; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + end if; + + -- Read the aligned dword pointed to by the TOS and then process in the next state to extract just the required word. + when Insn_Loadh => + if IMPL_LOADH = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READWORDTOTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Read the aligned dword pointed to by the TOS and update just the one required word, + -- The loadb and storeb can be sped up by implementing hardware byte read/write. + when Insn_Storeh => + if IMPL_STOREB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incIncSp; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)+1).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_WRITEHWORDTOADDR; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + end if; + + -- Perform an exclusive or of the TOS and NOS which is stored in TOS in the next state. NOS is read from the + -- new location. + when Insn_Xor => + if IMPL_XOR = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxNOS.word xor muxTOS.word; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform a negation or inverse of the TOS. + when Insn_Neg => + if IMPL_NEG = true then + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + TOS.word <= (not muxTOS.word) + 1; + end if; + end if; + + -- Perform a signed comparison of TOS v NOS, if they are not equal, set the result to 1 which is stored in TOS in the next state. NOS + -- is read from the new memory location. + when Insn_Neq => + if IMPL_NEQ = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (signed(muxTOS.word) /= signed(muxNOS.word)) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform a modulo of TOS v NOS and push to stack. TOS is set to the result and NOS is read from the new stack location. + when Insn_Mod => + if IMPL_MOD = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + divStart <= '1'; + divQuotientFractional <= 0; + state <= State_Mod2; + end if; + end if; + + -- Shift NOS left or right TOS times according to the instruction. The shifting is done by VHDL operators paying attention to + -- shift left arithmetic where the sla operator doesnt give the normal results. + when Insn_Alshift => + if IMPL_ASHIFTLEFT = true or IMPL_ASHIFTRIGHT = true or IMPL_LSHIFTRIGHT = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + + -- Positions to shift stored in TOS. + tShiftCnt := to_integer(unsigned(std_logic_vector(muxTOS.word(4 downto 0)))); + + -- Logical Shift Right + if (muxNOS.word(31) and cacheL1(to_integer(pc))(OPCODE_RANGE)(2)) = '0' and cacheL1(to_integer(pc))(OPCODE_RANGE)(0) = '0' then + if (tShiftCnt = 0) then + TOS.word <= (others => '0'); + else + TOS.word <= unsigned(to_stdlogicvector(to_bitvector(std_logic_vector(muxNOS.word)) srl tShiftCnt)); + end if; + end if; + + -- Arithmetic Shift Right + if (muxNOS.word(31) and cacheL1(to_integer(pc))(OPCODE_RANGE)(2)) = '1' and cacheL1(to_integer(pc))(OPCODE_RANGE)(0) = '0' then + if (tShiftCnt = 0) then -- ASR #32 + TOS.word <= (others => std_logic(muxNOS.word(31))); + else + TOS.word <= unsigned(to_stdlogicvector(to_bitvector(std_logic_vector(muxNOS.word)) sra tShiftCnt)); + end if; + end if; + + -- Arithmetic Shift Left (NB. VHDL sla behaves in a non-standard way, it mirrors sra hence use of sll). + if (muxNOS.word(31) and cacheL1(to_integer(pc))(OPCODE_RANGE)(2)) = '0' and cacheL1(to_integer(pc))(OPCODE_RANGE)(0) = '1' then + if (tShiftCnt = 0) then + TOS.word <= muxNOS.word; + else + TOS.word <= unsigned(to_stdlogicvector(to_bitvector(std_logic_vector(muxNOS.word)) sll tShiftCnt)); + end if; + end if; + + -- Fetch new NOS value. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + -- The ZPU has an 8 bit instruction set which has few spare slots. This intruction allows extended multibyte additions to be coded and processed. + -- The instructions are coded as: Extend,,[,,,] + -- Where ParamSize = 00 - No parameter bytes + -- 01 - 8 bit parameter + -- 10 - 16 bit parameter + -- 11 - 32 bit parameter + -- Thus without any additional data fetches, new instructions have access to 3 parameters, TOS, NOS and the InsnParameter. + -- ie. To create an LDIR, Source=TOS, Dest=NOS and InsnParameter=Count + when Insn_Extend => + -- Ensure L1 cache has sufficient data to process this instruction, otherwise wait until it does before decoding and executing. + if cacheL1FetchIdx - pc > to_integer(unsigned(cacheL1(to_integer(pc)+1)(OPCODE_RANGE)(OPCODE_PARAM_RANGE)))+1 then + tInsnExec := '1'; + + -- For instructions which use a parameter, build the value ready for use. + -- TODO: This should be variables to meet the 1 cycle requirement or set during decode. + case cacheL1(to_integer(pc)+1)(OPCODE_PARAM_RANGE) is + when "00" => insnExParameter <= X"00000000"; + when "01" => insnExParameter <= X"000000" & unsigned(cacheL1(to_integer(pc)+2)(OPCODE_RANGE)); + when "10" => insnExParameter <= X"0000" & unsigned(cacheL1(to_integer(pc)+2)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+3)(OPCODE_RANGE)); + when "11" => insnExParameter <= unsigned(cacheL1(to_integer(pc)+2)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+3)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+4)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+5)(OPCODE_RANGE)); + end case; + + -- Decode the extended instruction at this point as we have access to 8 future instructions or bytes so can work out what is required and execute. + -- 1:0 = 00 means an instruction which operates with a default, byte, half-word or word parameter. ie. Extend,,[,,,] + + -- Memory fill instruction. Fill memory starting at address in NOS with zero, 8 bit, 16 or 32 bit repeating value for TOS bytes. + --if cacheL1(to_integer(pc)+1)(OPCODE_INSN_RANGE) = Opcode_Ex_Fill then + --end if; + + -- Debug code, if enabled, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(5, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"455854454E440000"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end if; + + -- Breakpoint, this is not a nornal instruction and used by debuggers to suspend a program exection. At the moment + -- this instuction sets the BREAK flag and just continues. + when Insn_Break => + tInsnExec := '1'; + report "Break instruction encountered" severity failure; + inBreak <= '1'; + + -- Debug code, if ENABLEd, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"425245414B504E54"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + + -- Dump out the L1, L2 and Memory for debugging. + debugState <= Debug_Start; + end if; + + -- Should never get here, so if debugging enabled, report. + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + inBreak <= '1'; + + -- Debug code, if ENABLEd, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(6, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"494C4C4547414C00"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end case; + + -- During waits, if debug enabled, output state and dump the L1 cache. + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 and (pc = X"1f00010") then + if debugState = Debug_Idle then + debugState <= Debug_DumpL2; + end if; + end if; + + -- Debug code, if enabled, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 and tInsnExec = '1' then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1InsnAfterPC), 16)); + debugRec.DATA2(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 24)) & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 24)) & "10000000" & '0' & cacheL2IncAddr & idimFlag & tInsnExec & cacheL2Full & cacheL2Active & cacheL2Empty & cacheL2Write; + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + else + if DEBUG_CPU = true and debugOutputOnce = '0' then + -- During waits, if debug enabled, output state and dump the L1 cache. + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 and (pc = X"1002b67") then + if debugState = Debug_Idle then + debugState <= Debug_DumpL2; + end if; + end if; + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1InsnAfterPC), 16)); + debugRec.DATA2(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 24)) & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 24)) & "00000000" & '0' & cacheL2IncAddr & idimFlag & tInsnExec & cacheL2Full & cacheL2Active & cacheL2Empty & cacheL2Write; + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + debugOutputOnce <= '1'; + end if; + end if; + + -------------------------------------------------------------------------------------------------------------- + -- End of Instruction Execution Case block. + -------------------------------------------------------------------------------------------------------------- + + when State_Mult2 => + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(multResult); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= std_logic_vector(to_unsigned(InsnType'POS(InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE))))) , 6)); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + + TOS.word <= multResult(wordSize-1 downto 0); + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + + when State_Div2 => + if IMPL_DIV = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + + if divStart = '0' and divComplete = '1' then + TOS.word <= unsigned(divResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_Mod2 => + if IMPL_MOD = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divRemainder); + debugLoad <= '1'; + end if; + + if divStart = '0' and divComplete = '1' then + TOS.word <= unsigned(divRemainder(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_FiAdd2 => + if IMPL_FIADD32 = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + if divComplete = '1' and muxTOS.valid = '1' and muxNOS.valid = '1' then + TOS.word <= unsigned(fpAddResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_FiDiv2 => + if IMPL_FIDIV32 = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + if divComplete = '1' and muxTOS.valid = '1' and muxNOS.valid = '1' then + TOS.word <= unsigned(divResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_FiMult2 => + if IMPL_FIMULT32 = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + if divComplete = '1' and muxTOS.valid = '1' and muxNOS.valid = '1' then + TOS.word <= unsigned(fpMultResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + -- Should never reach this state, if debug enabled, output details. + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + inBreak <= '1'; + + -- Debug code, if ENABLEd, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"494C4C4547414C53"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end case; + -------------------------------------------------------------------------------------------------------------- + -- End of Instruction State Case block. + -------------------------------------------------------------------------------------------------------------- + + -- In debug mode, output the current data and the decoded instruction queue. + if DEBUG_CPU = true then + case debugState is + when Debug_Idle => + + when Debug_Start => + + -- Write out the primary data. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)); + debugRec.DATA2(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 16)) & std_logic_vector(cacheL2FetchIdx(15 downto 0)) & "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & "0000" & idimFlag & tInsnExec & cacheL2Full & cacheL2Write; + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + debugAllInfo <= '1'; + + debugState <= Debug_DumpL1; + + when Debug_DumpL1 => + debugPC <= (others => '0'); + debugState <= Debug_DumpL1_1; + + when Debug_DumpL1_1 => + -- Write out the opcode. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_SPLIT_DATA <= "01"; + if debugPC = MAX_L1CACHE_SIZE-(wordBytes*4) then + debugRec.FMT_POST_CRLF <= '1'; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '0'; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.DATA(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+ 0)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 1)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 2)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 3)(INSN_RANGE); + debugRec.DATA2(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+ 4)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 5)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 6)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 7)(INSN_RANGE); + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+ 8)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 9)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+10)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+11)(INSN_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+12)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+13)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+14)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+15)(INSN_RANGE); + if debugPC = 0 then + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(to_unsigned(to_integer(pc), debugRec.PC'LENGTH)); + debugRec.WRITE_PC <= '1'; + else + debugRec.WRITE_PC <= '0'; + end if; + debugLoad <= '1'; + debugState <= Debug_DumpL1_2; + debugPC <= debugPC + (wordBytes * 4); -- 16 instructions are output per loop. + + when Debug_DumpL1_2 => + -- Move onto next opcode in Fifo. + if debugPC = MAX_L1CACHE_SIZE then + if debugAllInfo = '1' then + -- if IMPL_USE_INSN_BUS = true then + -- debugState <= Debug_End; + -- else + debugState <= Debug_DumpL2; + -- end if; + else + debugState <= Debug_End; + end if; + else + debugState <= Debug_DumpL1_1; + end if; + + when Debug_DumpL2 => + debugPC <= (others => '0'); + debugState <= Debug_DumpL2_0; + + -- Wait state at start of dump so initial address gets registered in cache memory and data output. + when Debug_DumpL2_0 => + debugState <= Debug_DumpL2_1; + + -- Output the contents of L2 in the format + when Debug_DumpL2_1 => + -- Write out the opcode. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_SPLIT_DATA <= "01"; + if debugPC = MAX_L2CACHE_SIZE-1 or debugPC(4 downto 2) = "111" then + debugRec.FMT_POST_CRLF <= '1'; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(3, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + if debugPC(4 downto 2) = "000" then + debugRec.WRITE_PC <= '1'; + else + debugRec.WRITE_PC <= '0'; + end if; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(debugPC); + debugRec.DATA(63 downto 32) <= cacheL2Word(31 downto 24) & cacheL2Word(23 downto 16) & cacheL2Word(15 downto 8) & cacheL2Word(7 downto 0); + debugLoad <= '1'; + debugState <= Debug_DumpL2_2; + debugPC <= debugPC + wordBytes; -- 4 instructions are output per loop (limited by memory read into cacheL2Word). + + when Debug_DumpL2_2 => + -- Move onto next opcode in Fifo. + if debugPC = MAX_L2CACHE_SIZE then + if debugAllInfo = '1' then + debugState <= Debug_DumpMem; + else + debugState <= Debug_End; + end if; + else + debugState <= Debug_DumpL2_1; + end if; + + when Debug_DumpMem => + debugPC <= debugPC_StartAddr; + debugPC_WidthCounter <= 0; + debugState <= Debug_DumpMem_0; + + when Debug_DumpMem_0 => + if mxMemVal.valid = '0' then + debugState <= Debug_DumpMem_1; + end if; + + -- Output the contents of memory in the format + when Debug_DumpMem_1 => + if mxMemVal.valid = '1' then + debugPC_WidthCounter <= debugPC_WidthCounter+4; + + -- Write out the memory location. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_SPLIT_DATA <= "01"; + if debugPC = debugPC_EndAddr or debugPC_WidthCounter = debugPC_Width-4 then + debugRec.FMT_POST_CRLF <= '1'; + debugPC_WidthCounter <= 0; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(3, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + if debugPC_WidthCounter = 0 then + debugRec.WRITE_PC <= '1'; + else + debugRec.WRITE_PC <= '0'; + end if; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(debugPC); + debugRec.DATA(63 downto 32) <= std_logic_vector(mxMemVal.word(31 downto 24)) & std_logic_vector(mxMemVal.word(23 downto 16)) & std_logic_vector(mxMemVal.word(15 downto 8)) & std_logic_vector(mxMemVal.word(7 downto 0)); + debugLoad <= '1'; + debugState <= Debug_DumpMem_2; + debugPC <= debugPC + wordBytes; + end if; + + when Debug_DumpMem_2 => + -- Move onto next opcode in Fifo. + if debugPC = debugPC_EndAddr then + debugState <= Debug_End; + else + debugState <= Debug_DumpMem_1; + end if; + + when Debug_End => + debugAllInfo <= '0'; + debugState <= Debug_Idle; + end case; + end if; + end if; + --------------------------------------------------------------------------------------------------------------------------------------------------- + end if; + end process; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Hardware divider - Fixed Point. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + DIVIDER : if IMPL_DIV = true or IMPL_FIDIV32 = true or IMPL_MOD = true generate + process(CLK, ZPURESET, divStart, dividendCopy) + begin + divRemainder <= unsigned(dividendCopy(31 downto 0)); + + if ZPURESET = '1' then + divComplete <= '1'; + divResult <= (others => '0'); + + elsif rising_edge(CLK) then + + if divComplete = '1' and divStart = '1' then + divComplete <= '0'; + bitCnt <= to_unsigned((32+divQuotientFractional)-2, bitCnt'LENGTH); + divResult <= (others => '0'); + + dividendCopy(30 downto 0) <= std_logic_vector(muxTOS.word(30 downto 0)); + dividendCopy(61 downto 31) <= (others => '0'); + + divisorCopy(61) <= '0'; + divisorCopy(60 downto 30) <= std_logic_vector(muxNOS.word(30 downto 0)); + divisorCopy(29 downto 0) <= (others => '0'); + + -- set sign bit + if((muxTOS.word(31) = '1' and muxNOS.word(31) = '0') or (muxTOS.word(31) = '0' and muxNOS.word(31) = '1')) then + divResult(31) <= '1'; + else + divResult(31) <= '0'; + end if; + + elsif divComplete = '0' and (DEBUG_CPU = false or (DEBUG_CPU = true and debugReady = '1')) then + -- 64bit compare of divisor/dividend. + if((unsigned(dividendCopy)) >= unsigned(divisorCopy)) then + --subtract, should only occur when the dividend is greater than the divisor. + dividendCopy <= std_logic_vector(to_unsigned(to_integer(unsigned(dividendCopy)) - to_integer(unsigned(divisorCopy)), dividendCopy'LENGTH)); + --set quotient + divResult(to_integer(bitCnt)) <= '1'; + end if; + + --reduce divisor + divisorCopy <= to_stdlogicvector(to_bitvector(divisorCopy) srl 1); + + --stop condition + if bitCnt = 0 then + divComplete <= '1'; + else + --reduce bit counter + bitCnt <= bitCnt - 1; + end if; + end if; + end if; + end process; + else generate + dividendCopy <= (others => DontCareValue); + end generate; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Hardware adder - Fixed Point. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + FIADD32: if IMPL_FIADD32 = true generate + process(muxTOS.word, muxNOS.word, ZPURESET) + begin + if ZPURESET = '1' then + fpAddResult <= (others => '0'); + else + -- both negative + if muxTOS.word(31) = '1' and muxNOS.word(31) = '1' then + -- sign + fpAddResult(31) <= '1'; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxTOS.word(30 downto 0)) + to_integer(muxNOS.word(30 downto 0)), 31)); + + --both positive + elsif muxTOS.word(31) = '0' and muxNOS.word(31) = '0' then + -- sign + fpAddResult(31) <= '0'; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxTOS.word(30 downto 0)) + to_integer(muxNOS.word(30 downto 0)), 31)); + + -- subtract TOS - NOS + elsif muxTOS.word(31) = '0' and muxNOS.word(31) = '1' then + -- sign + if muxTOS.word(30 downto 0) > muxNOS.word(30 downto 0) then + fpAddResult(31) <= '1'; + else + fpAddResult(31) <= '0'; + end if; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxTOS.word(30 downto 0)) - to_integer(muxNOS.word(30 downto 0)), 31)); + + -- subtract NOS - TOS + else + -- sign + if muxTOS.word(30 downto 0) < muxNOS.word(30 downto 0) then + fpAddResult(31) <= '1'; + else + fpAddResult(31) <= '0'; + end if; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxNOS.word(30 downto 0)) - to_integer(muxTOS.word(30 downto 0)), 31)); + end if; + end if; + end process; + else generate + fpAddResult <= (others => DontCareValue); + end generate; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Hardware multiplier - Fixed Point. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + FIMULT32: if IMPL_FIMULT32 = true generate + signal TOSflip : std_logic_vector(31 downto 0); + signal NOSflip : std_logic_vector(31 downto 0); + signal TOSmult : std_logic_vector(31 downto 0); + signal NOSmult : std_logic_vector(31 downto 0); + signal resultFlip : std_logic_vector(63 downto 0); + signal result : std_logic_vector(63 downto 0); + begin + process(muxTOS.word, TOSflip) + begin + for i in 0 to wordSize-1 loop + TOSflip(i) <= muxTOS.word(wordSize-1-i); + end loop; + TOSflip <= std_logic_vector(signed(TOSflip) + 1); + end process; + + process(muxNOS.word, NOSflip) + begin + for i in 0 to wordSize-1 loop + NOSflip(i) <= muxNOS.word(wordSize-1-i); + end loop; + NOSflip <= std_logic_vector(signed(NOSflip) + 1); + end process; + + process(result, quotientFractional, resultFlip) + begin + for i in quotientFractional to 30+quotientFractional loop + resultFlip(i) <= result(30+quotientFractional-i); + end loop; + resultFlip <= std_logic_vector(signed(resultFlip) + 1); + end process; + + process(muxTOS.word, muxNOS.word, TOSflip, NOSflip) + begin + if muxTOS.word(31) = '1' then + TOSmult <= TOSflip; + else + TOSmult <= std_logic_vector(muxTOS.word); + end if; + + if muxNOS.word(31) = '1' then + NOSmult <= NOSflip; + else + NOSmult <= std_logic_vector(muxNOS.word); + end if; + end process; + + process(TOSmult, NOSmult) + begin + result <= std_logic_vector(signed(TOSmult) * signed(NOSmult)); + end process; + + process(result, resultFlip, muxTOS.word, muxNOS.word, quotientFractional) + begin + -- sign + if (muxTOS.word(31) = '1' and muxNOS.word(31) = '0') or (muxTOS.word(31) = '0' and muxNOS.word(31) = '1') then + fpMultResult(31) <= '1'; + fpMultResult(30 downto 0) <= resultFlip(30 downto 0); + else + fpMultResult(31) <= '0'; + fpMultResult(30 downto 0) <= result(30+quotientFractional downto quotientFractional); + end if; + end process; + else generate + fpMultResult <= (others => DontCareValue); + quotientFractional <= 0; + end generate; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Debugger output processor. + -- This logic takes a debug record and expands it to human readable form then dispatches it to the debug serial port. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Add debug uart if required. Increasing the TX and DBG Fifo depth can help short term (ie. initial start of the CPU) + -- but once full, the debug run will eventually operate at the slowest denominator, ie. the TX speed and how quick it can + -- shift 10 bits. + DEBUG : if DEBUG_CPU = true generate + DEBUGUART: entity work.zpu_uart_debug + generic map ( + CLK_FREQ => CLK_FREQ -- Frequency of master clock. + ) + port map ( + -- CPU Interface + CLK => CLK, -- Master clock + RESET => ZPURESET, -- high active sync reset + DEBUG_DATA => debugRec, -- write data + CS => debugLoad, -- Chip Select. + READY => debugReady, -- Debug processor ready for next command. + + -- Serial data + TXD => DEBUG_TXD + ); + end generate; + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- End of debugger output processor. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + +end behave; diff --git a/zpu/cpu/zpu_core_evo.vhd.bakPreMultChange b/zpu/cpu/zpu_core_evo.vhd.bakPreMultChange new file mode 100755 index 0000000..24e9b46 --- /dev/null +++ b/zpu/cpu/zpu_core_evo.vhd.bakPreMultChange @@ -0,0 +1,3539 @@ +-- ZPU Evolution +-- +-- Copyright 2004-2008 (ZPU Design, Small, Medium) oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- Copyright 2008 (zpuino) alvieboy - Álvaro Lopes - alvieboy@alvie.com +-- Copyright 2013 (zpuflex) Alastair M. Robinson +-- Copyright 2018-2019 (ZPU Evo) Philip Smart +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. +-- +-- Evo History: +-- 181230 v0.1 Initial version created by merging items of the Small, Medium and Flex versions. +-- 190328 v0.5 Working with Instruction, Emulation or No Cache with or without seperate instruction +-- bus. Runs numerous tests and output same as the Medium CPU. One small issue is running +-- without an instruction bus and instruction/emulation cache enabled, the DMIPS value is lower +-- that just with instruction bus or emulation bus, seems some clash which reuults in waits states +-- slowing the CPU down. +-- 191021 v1.0 First release. All variations tested but more work needed on the SDRAM controller to +-- make use of burst mode in order to populate the L2 cache in fewer cycles. +-- Additional instructions need to be added back in after test and verification, albeit some +-- which are sepcific to the Sharp Emulator should be skipped. +-- Additional effort needs spending on the Wishbone Error signal to retry the bus transaction, +-- currently it just aborts it which is not ideal. +-- 191126 v1.1 Bug fixes. When switching off WishBone the CPU wouldnt run. +-- 191215 v1.2 Bug fixes. Removed L2 Cache megacore and replaced with inferred equivalent, fixed hardware +-- byte/h-word write which was always defaulting to read-update-write, fixed L2 timing with +-- external SDRAM, minor tweaks and currently looking at better constraints. +-- 191220 v1.21 Changes to Mult, shifting it from a combination assignment to a clocked assignment to improve +-- slack. Small changes made for slack in setup and hold. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_pkg.all; + +-------------------------------------------------------------------------------------------------------------------------------------------- +-- ZPU Evo Signal Description. +-------------------------------------------------------------------------------------------------------------------------------------------- +-- +-- Main Memory/IO Bus. +-- ------------------- +-- This bus is used to access all external memory and IO, it can also, via configuration, be used to read instructions from attahed memory. +-- +-- MEM_WRITE_ENABLE - set to '1' for a single cycle to send off a write request. +-- MEM_WRITE is valid only while MEM_WRITE_ENABLE='1'. +-- MEM_WRITE_BYTE - set to '1' when performing a byte write with data in bits 7-0 of MEM_DATA_OUT +-- MEM_WRITE_HWORD - set to '1' when performing a half word write with data in bits 15-0 of MEM_DATA_OUT +-- MEM_READ_ENABLE - set to '1' for a single cycle to send off a read request. +-- +-- MEM_BUSY - It is illegal to send off a read/write request when mem_busy='1'. +-- Set to '0' when MEM_READ is valid after a read request. +-- If it goes to '1'(busy), it is on the cycle after MEM_READ/writeEnable +-- is '1'. +-- MEM_ADDR - address for read/write request +-- MEM_DATA_IN - read data. Valid only on the cycle after mem_busy='0' after +-- MEM_READ_ENABLE='1' for a single cycle. +-- MEM_DATA_OUT - data to write +-- +-- Wishbone Bus B4 Specification +-- ----------------------------- +-- This bus is the industry standard for FPGA IP designs and the one primarily used in OpenCores. In this implementation it is +-- 32bit wide using a Master/Multi-Slave configuration with the ZPU acting as Master. It is a compile time configurable extension as +-- some uses of the ZPU Evo wont need it and thus saves fabric area. The description below is taken from the OpenCores Wishbone B4 +-- specification. +-- +-- WB_CLK_I - The clock input [WB_CLK_I] coordinates all activities for the internal logic within the WISHBONE interconnect. +-- - All WISHBONE output signals are registered at the rising edge of [WB_CLK_I]. All WISHBONE input signals are +-- - stable before the rising edge of [WB_CLK_I]. +-- WB_RST_I - The reset input [WB_RST_I] forces the WISHBONE interface to restart. In this design, this signal is tied to the +-- - ZPU reset via an OR mechanism, forcing the ZPU to reset if activated. +-- WB_ACK_I - The acknowledge input [WB_ACK_I], when asserted, indicates the normal termination of a bus cycle. +-- WB_DAT_I - The data input array [WB_DAT_I] is used to pass binary data. The array boundaries are determined by the port size, +-- - with a port size of 32-bits in this design. +-- WB_DAT_O - The data output array [DAT_O()] is used to pass binary data. The array boundaries are determined by the port size, +-- - with a port size of 32-bits in this design. +-- WB_ADR_O - The address output array [WB_ADR_O] is used to pass a binary address. The higher array boundary is specific to the +-- - address width of the core, and the lower array boundary is determined by the data port size and granularity. +-- - This design is 32bit so WB_ADR[1:0] specify the byte level granularity. +-- WB_CYC_O - The cycle output [WB_CYC_O], when asserted, indicates that a valid bus cycle is in progress. The signal is asserted +-- - for the duration of all bus cycles. +-- WB_STB_O - The strobe output [WB_STB_O] indicates a valid data transfer cycle. It is used to qualify various other signals on +-- - the interface such as [WB_SEL_O]. The SLAVE asserts either the [WB_ACK_I], [WB_ERR_I] or [WB_RTY_I] signals in +-- - response to every assertion of the [WB_STB_O] signal. +-- WB_CTI_O - The Cycle Type Idenfier [WB_CTI_O] Address Tag provides additional information about the current cycle. The MASTER +-- - sends this information to the SLAVE. The SLAVE can use this information to prepare the response for the next cycle. +-- WB_WE_O - The write enable output [WB_WE_O] indicates whether the current local bus cycle is a READ or WRITE cycle. The +-- - signal is negated during READ cycles, and is asserted during WRITE cycles. +-- WB_SEL_O - The select output array [WB_SEL_O] indicates where valid data is expected on the [WB_DAT_I] signal array during +-- - READ cycles, and where it is placed on the [WB_DAT_O] signal array during WRITE cycles. The array boundaries are +-- - determined by the granularity of a port which is 32bit in this design leading to a WB_SEL_O width of 4 bits, 1 +-- - bit to represent each byte. ie. WB_SEL_O[3] = MSB, WB_SEL_O[0] = LSB. +-- WB_HALT_I - +-- WB_ERR_I - The error input [WB_ERR_I] indicates an abnormal cycle termination. The source of the error, and the response +-- - generated by the MASTER is defined by the IP core supplier, in this case the intention (NYI) is to retry +-- - the transaction. +-- WB_INTA_I - A non standard signal to allow a wishbone device to interrupt the ZPU when set to logic '1'. The interrupt is +-- - registered on the next rising edge. +-- +-- +-- Instruction Memory Bus +-- ---------------------- +-- This bus is used for dedicated faster response read only memory containing the code to be run. Using this bus results in faster +-- CPU performance. If this bus is not used/disabled, all instructions will be fetched via the main bus. +-- +-- MEM_BUSY_INSN - Memory is busy ('1') so data invalid. +-- MEM_DATA_IN_INSN - Instruction data in. +-- MEM_ADDR_INSN - Instruction address bus. +-- MEM_READ_ENABLE_INSN - Instruction read enable signal (active high). +-- +-- INT_REQ - set to '1' by external logic until interrupts are acknowledged by CPU. +-- INT_ACK - set to '1' for 1 clock cycle when the interrupt is acknowledged and processing commences. +-- INT_DONE - set to '1' for 1 clock cycle when the interrupt processing is complete +-- BREAK - set to '1' when CPU hits BREAK instruction +-- DEBUG_TXD - Serial output of runtime debug data if enabled. + +entity zpu_core_evo is + generic ( + -- Optional hardware features to be implemented. + IMPL_HW_BYTE_WRITE : boolean := false; -- Enable use of hardware direct byte write rather than read 32bits-modify 8 bits-write 32bits. + IMPL_HW_WORD_WRITE : boolean := false; -- Enable use of hardware direct byte write rather than read 32bits-modify 16 bits-write 32bits. + IMPL_OPTIMIZE_IM : boolean := true; -- Optimise Im instructions to gain speed. + IMPL_USE_INSN_BUS : boolean := true; -- Use a seperate bus to read instruction memory, normally implemented in BRAM. + IMPL_USE_WB_BUS : boolean := true; -- Use the wishbone interface in addition to direct access bus. + -- Optional instructions to be implemented in hardware: + IMPL_ASHIFTLEFT : boolean := true; -- Arithmetic Shift Left (uses same logic so normally combined with ASHIFTRIGHT and LSHIFTRIGHT). + IMPL_ASHIFTRIGHT : boolean := true; -- Arithmetic Shift Right. + IMPL_CALL : boolean := true; -- Call to direct address. + IMPL_CALLPCREL : boolean := true; -- Call to indirect address (add offset to program counter). + IMPL_DIV : boolean := true; -- 32bit signed division. + IMPL_EQ : boolean := true; -- Equality test. + IMPL_EXTENDED_INSN : boolean := true; -- Extended multibyte instruction set. + IMPL_FIADD32 : boolean := true; -- Fixed point Q17.15 addition. + IMPL_FIDIV32 : boolean := true; -- Fixed point Q17.15 division. + IMPL_FIMULT32 : boolean := true; -- Fixed point Q17.15 multiplication. + IMPL_LOADB : boolean := true; -- Load single byte from memory. + IMPL_LOADH : boolean := true; -- Load half word (16bit) from memory. + IMPL_LSHIFTRIGHT : boolean := true; -- Logical shift right. + IMPL_MOD : boolean := true; -- 32bit modulo (remainder after division). + IMPL_MULT : boolean := true; -- 32bit signed multiplication. + IMPL_NEG : boolean := true; -- Negate value in TOS. + IMPL_NEQ : boolean := true; -- Not equal test. + IMPL_POPPCREL : boolean := true; -- Pop a value into the Program Counter from a location relative to the Stack Pointer. + IMPL_PUSHSPADD : boolean := true; -- Add a value to the Stack pointer and push it onto the stack. + IMPL_STOREB : boolean := true; -- Store/Write a single byte to memory/IO. + IMPL_STOREH : boolean := true; -- Store/Write a half word (16bit) to memory/IO. + IMPL_SUB : boolean := true; -- 32bit signed subtract. + IMPL_XOR : boolean := true; -- Exclusive or of value in TOS. + -- Size/Control parameters for the optional hardware. + MAX_INSNRAM_SIZE : integer := 16384; -- Maximum size of the optional Instruction BRAM on the INSN Bus. + MAX_L1CACHE_BITS : integer := 4; -- Maximum size in instructionsG of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache. + MAX_L2CACHE_BITS : integer := 12; -- Maximum size in bytes of the Level 1 instruction cache governed by the number of bits, ie. 8 = 256 byte cache. + MAX_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits. + RESET_ADDR_CPU : integer := 0; -- Initial start address of the CPU. + START_ADDR_MEM : integer := 0; -- Start address of program memory. + STACK_ADDR : integer := 0; -- Initial stack address on CPU start. + CLK_FREQ : integer := 100000000 -- Frequency of the input clock. + ); + port ( + CLK : in std_logic; -- Main clock. + RESET : in std_logic; -- Reset the CPU (high). + ENABLE : in std_logic; -- Enable the CPU (high), setting low will halt the CPU until signal is returned high. + -- Main Memory/IO bus. + MEM_BUSY : in std_logic; + MEM_DATA_IN : in std_logic_vector(WORD_32BIT_RANGE); + MEM_DATA_OUT : out std_logic_vector(WORD_32BIT_RANGE); + MEM_ADDR : out std_logic_vector(ADDR_BIT_RANGE); + MEM_WRITE_ENABLE : out std_logic; + MEM_READ_ENABLE : out std_logic; + MEM_WRITE_BYTE : out std_logic; + MEM_WRITE_HWORD : out std_logic; + -- Instruction memory bus (if implemented). + MEM_BUSY_INSN : in std_logic; + MEM_DATA_IN_INSN : in std_logic_vector(WORD_32BIT_RANGE); + MEM_ADDR_INSN : out std_logic_vector(ADDR_BIT_RANGE); + MEM_READ_ENABLE_INSN : out std_logic; + -- Master Wishbone Memory/IO bus interface. + WB_CLK_I : in std_logic; + WB_RST_I : in std_logic; + WB_ACK_I : in std_logic; + WB_DAT_I : in std_logic_vector(WORD_32BIT_RANGE); + WB_DAT_O : out std_logic_vector(WORD_32BIT_RANGE); + WB_ADR_O : out std_logic_vector(ADDR_BIT_RANGE); + WB_CYC_O : out std_logic; + WB_STB_O : out std_logic; + WB_CTI_O : out std_logic_vector(2 downto 0); + WB_WE_O : out std_logic; + WB_SEL_O : out std_logic_vector(WORD_4BYTE_RANGE); + WB_HALT_I : in std_logic; + WB_ERR_I : in std_logic; + WB_INTA_I : in std_logic; + + -- Set to one to jump to interrupt vector + -- The ZPU will communicate with the hardware that caused the + -- interrupt via memory mapped IO or the interrupt flag can + -- be cleared automatically + INT_REQ : in std_logic; + INT_ACK : out std_logic; -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + INT_DONE : out std_logic; -- Interrupt service routine completed/done. + -- Break and debug signals. + BREAK : out std_logic; -- A break instruction encountered. + CONTINUE : in std_logic; -- When break activated, processing stops. Setting CONTINUE to logic 1 resumes processing with next instruction. + DEBUG_TXD : out std_logic -- Debug serial output. + ); +end zpu_core_evo; + +architecture behave of zpu_core_evo is + + -- Constants. + constant MAX_L1CACHE_SIZE : integer := (2**(MAX_L1CACHE_BITS)); + constant MAX_L2CACHE_SIZE : integer := (2**MAX_L2CACHE_BITS); + subtype L1CACHE_BIT_RANGE is natural range MAX_L1CACHE_BITS-1 downto 0; + subtype L2CACHE_BIT_RANGE is natural range MAX_L2CACHE_BITS-1 downto 0; + subtype L2CACHE_32BIT_RANGE is natural range MAX_L2CACHE_BITS-1 downto 2; + + -- Instruction offset in the instruction vector. + subtype INSN_RANGE is natural range 13 downto 0; + subtype OPCODE_RANGE is natural range 7 downto 0; + subtype DECODED_RANGE is natural range 13 downto 8; + subtype OPCODE_IM_RANGE is natural range 6 downto 0; + subtype IM_DATA_RANGE is natural range 6 downto 0; + subtype OPCODE_PARAM_RANGE is natural range 1 downto 0; + subtype OPCODE_INSN_RANGE is natural range 7 downto 2; + + -- Decoded instruction states. Used in the execution unit state machine according to instruction being processed. + type InsnType is + ( + Insn_Add, -- 00 + Insn_AddSP, -- 01 + Insn_AddTop, -- 02 + Insn_Alshift, -- 03 + Insn_And, -- 04 + Insn_Break, -- 05 + Insn_Call, -- 06 + Insn_Callpcrel, -- 07 + Insn_Div, -- 08 + Insn_Emulate, -- 09 + Insn_Eq, -- 0a + Insn_Eqbranch, -- 0b + Insn_Extend, -- 0c + Insn_FiAdd32, -- 0d + Insn_FiDiv32, -- 0e + Insn_FiMult32, -- 0f + Insn_Flip, -- 10 + Insn_Im, -- 11 + Insn_Lessthan, -- 12 + Insn_Lessthanorequal, -- 13 + Insn_Load, -- 14 + Insn_Loadb, -- 15 + Insn_Loadh, -- 16 + Insn_LoadSP, -- 17 + Insn_Mod, -- 18 + Insn_Mult, -- 19 + Insn_Neg, -- 1a + Insn_Neq, -- 1b + Insn_Neqbranch, -- 1c + Insn_Nop, -- 1d + Insn_Not, -- 1e + Insn_Or, -- 1f + Insn_PopPC, -- 20 + Insn_PopPCRel, -- 21 + Insn_PopSP, -- 22 + Insn_PushPC, -- 23 + Insn_PushSP, -- 24 + Insn_Pushspadd, -- 25 + Insn_Shift, -- 26 + Insn_Store, -- 27 + Insn_Storeb, -- 28 + Insn_Storeh, -- 29 + Insn_StoreSP, -- 2a + Insn_Sub, -- 2b + Insn_Ulessthan, -- 2c + Insn_Ulessthanorequal, -- 2d + Insn_Xor -- 2e + ); + + -- State machine states. Some states are extension of instruction execution whilst others maintain the ZPU runtime operations and state. + -- + type StateType is + ( + State_Div2, + State_Mult2, + State_Execute, + State_FiAdd2, + State_FiDiv2, + State_FiMult2, + State_Idle, + State_Init, + State_Mod2 + ); + + -- Decoder state machine states. Unit which fetches, decodes and stores the decoded instructions and the required states needed to do this. + -- + type DecoderStateType is + ( + Decode_Idle, + Decode_Fetch, + Decode_Word, + Decode_WriteCache + ); + + type Level1CacheStateType is + ( + State_PreSetAddr, + State_LatchAddr, + State_Decode, + State_Store + ); + + -- Memory transaction processing unit. All CPU memory accesses (except Instruction Fetch) go through this unit. These states define + -- those required to implement the unit. + -- + type MemXactStateType is + ( + MemXact_Idle, + MemXact_MemoryFetch, + MemXact_OpcodeFetch, + MemXact_TOS, + MemXact_NOS, + MemXact_TOSNOS, + MemXact_TOSNOS_2, + MemXact_TOSNOS_3, + MemXact_ReadByteToTOS, + MemXact_ReadWordToTOS, + MemXact_ReadAddToTOS, + MemXact_WriteToAddr, + MemXact_WriteByteToAddr, + MemXact_WriteByteToAddr2, + MemXact_WriteHWordToAddr, + MemXact_WriteHWordToAddr2, + MemXact_Write + ); + + -- Memory transaction processing commands. These states (commands) are the actions which the MTP can process. + -- + type MemXactCmdType is + ( + MX_CMD_READTOS, + MX_CMD_READNOS, + MX_CMD_READTOSNOS, + MX_CMD_READBYTETOTOS, + MX_CMD_READWORDTOTOS, + MX_CMD_READADDTOTOS, + MX_CMD_WRITEBYTETOADDR, + MX_CMD_WRITEHWORDTOADDR, + MX_CMD_WRITETOINDADDR, + MX_CMD_WRITE + ); + + -- Debug states. These states are those required to output debug data via the debug serialisation unit. + -- + type DebugType is + ( + Debug_Idle, + Debug_Start, + Debug_DumpL1, + Debug_DumpL1_1, + Debug_DumpL1_2, + Debug_DumpL2, + Debug_DumpL2_1, + Debug_DumpL2_2, + Debug_DumpMem, + Debug_DumpMem_0, + Debug_DumpMem_1, + Debug_DumpMem_2, + Debug_End + ); + + -- Record to store a memory word and its validity, typically used for stack caching. + -- + type WordRecord is record + word : unsigned(WORD_32BIT_RANGE); + valid : std_logic; + end record; + + -- Record to contain an opcode and its decoded form. + -- + type InsnRecord is record + decodedOpcode : InsnType; + opcode : std_logic_vector(7 downto 0); + end record; + + -- Memory transaction records. Memory reads and writes are pushed into a queue and executed sequentially. + -- + type MemXactRecord is record + addr : std_logic_vector(ADDR_BIT_RANGE); + data : std_logic_vector(WORD_32BIT_RANGE); + cmd : MemXactCmdType; + end record; + -- + -- Array definitions. + type InsnWord is array(natural range 0 to wordBytes-1) of InsnRecord; + type InsnQueue is array(natural range 0 to 2*wordBytes-1) of InsnRecord; + type InsnL1Array is array(natural range 0 to ((2**(MAX_L1CACHE_BITS))-1)) of std_logic_vector(INSN_RANGE); + type MemXactArray is array(natural range 0 to ((2**MAX_MXCACHE_BITS)-1)) of MemXactRecord; + + signal pc : unsigned(ADDR_BIT_RANGE); -- Current program location being executed. + signal pcLast : unsigned(ADDR_BIT_RANGE); -- Last program location executed. + signal incPC : unsigned(ADDR_BIT_RANGE); -- Next program location to be executed. + + signal sp : unsigned(ADDR_32BIT_RANGE); -- Current stack pointer. + signal incSp : unsigned(ADDR_32BIT_RANGE); -- Stack pointer when 1 value is popped. + signal incIncSp : unsigned(ADDR_32BIT_RANGE); -- Stack pointer when 2 values are popped. + signal decSp : unsigned(ADDR_32BIT_RANGE); -- Stack pointer after a value is pushed. + signal TOS : WordRecord; -- Top Of Stack value. + signal NOS : WordRecord; -- Next Of Stack value (ie. value after TOS). + signal mxTOS : WordRecord; -- Top Of Stack retrieved by the Memory Transaction Processor. + signal mxNOS : WordRecord; -- Next Of Stack retrieved by the MXP. + signal muxTOS : WordRecord; -- Multiplexed (to get most recent) TOS, either from MXP or current value. + signal muxNOS : WordRecord; -- Multiplexed (to get most recent) NOS, either from MXP or current value. + signal divResult : unsigned(WORD_32BIT_RANGE); + signal divRemainder : unsigned(WORD_32BIT_RANGE); + signal divStart : std_logic; + signal divComplete : std_logic; + signal quotientFractional : integer range 0 to 15 := 15; -- Fractional component size of a fixed point value. + signal divQuotientFractional : integer range 0 to 15 := 15; -- Fractional component size for the divider as it can be changed dynamically for integer division. + signal state : StateType; + signal fpAddResult : std_logic_vector(WORD_32BIT_RANGE); + signal fpMultResult : std_logic_vector(WORD_32BIT_RANGE); + signal bitCnt : unsigned(5 downto 0); + signal dividendCopy : std_logic_vector(61 downto 0); + signal divisorCopy : std_logic_vector(61 downto 0); + + -- Wishbone processing. + -- + signal ZPURESET : std_logic; + signal wbXactActive : std_logic; -- Wishbone interface is active. + + -- Break processing. + -- + signal inBreak : std_logic; -- Flag to indicate when the CPU is halted (1) due to a BREAK instruction or illegal instruction. + + -- Interrupt procesing. + -- + signal inInterrupt : std_logic; + signal interruptSuspendedAddr : unsigned(ADDR_BIT_RANGE); + + -- Instruction storage, decoding and processing. + -- + signal insnExParameter : unsigned(WORD_32BIT_RANGE); -- Parameter storage for the extended instruction. + signal idimFlag : std_logic; -- Flag to indicate concurrent Im instructions which are building a larger word in TOS. + signal l1State : Level1CacheStateType; -- Current state of the L1 Cache decode and populate machine. + + -- Cache L1 specific signals. + signal cacheL1 : InsnL1Array; -- Level 1 cache, implemented as registers to gain random access for instruction lookahead optimisation and instruction set extension. + signal cacheL1StartAddr : unsigned(ADDR_BIT_RANGE); -- Absolute address of first instruction in cache. + signal cacheL1FetchIdx : unsigned(ADDR_BIT_RANGE); -- Index into L1 cache decoded instructions will be placed. + signal cacheL1Invalid : std_logic; -- A flag to indicate when the L1 cache is in invalid. + signal cacheL1Empty : std_logic; -- A flag to indicate when the L1 cache is empty. + signal cacheL1Full : std_logic; -- A flag to indicate when the L1 cache is full. + signal cacheL1InsnAfterPC : unsigned(ADDR_BIT_RANGE); -- Count of how many instructions are in the cache after the current program counter. + attribute ramstyle : string; + attribute ramstyle of cacheL1 : signal is "logic"; + + -- Cache L2 (primary) specific signals. + signal cacheL2FetchIdx : unsigned(ADDR_BIT_RANGE); -- Location in memory being read by the decoder for storage into cache. + signal cacheL2StartAddr : unsigned(ADDR_BIT_RANGE); -- The actual program address stored in the first cache location. + signal cacheL2Active : std_logic; -- A flag to indicate when the L2 cache is in use. + signal cacheL2Invalid : std_logic; -- A flag to indicate when the L2 cache is in invalid. + signal cacheL2Empty : std_logic; -- A flag to indicate the instruction cache is empty. + signal cacheL2Mux2Addr : unsigned(L2CACHE_32BIT_RANGE); -- Multiplexed address into L2 cache between the L1 fetch and debug fetch. + signal cacheL2Word : std_logic_vector(WORD_32BIT_RANGE); + signal cacheL2Write : std_logic; + signal cacheL2WriteByte : std_logic; -- Update a single byte in the L2 cache. + signal cacheL2WriteHword : std_logic; -- Update a 16bit half-word in the L2 cache. + signal cacheL2WriteAddr : unsigned(L2CACHE_BIT_RANGE); + signal cacheL2WriteData : std_logic_vector(WORD_32BIT_RANGE); + signal cacheL2IncAddr : std_logic; -- A flag to indicate when the L2 cache write address should be incremented, generally after a write pulse. + signal cacheL2MxAddrInCache : std_logic; -- A flag to indicate when an MXP address exists in the L2 cache. + signal cacheL2Full : std_logic; -- A flag to indicate when the L2 cache is full. + + -- Memory transaction processor. + -- + signal mxFifo : MemXactArray; + signal mxState : MemXactStateType; + signal mxFifoWriteIdx : unsigned(MAX_MXCACHE_BITS-1 downto 0); + signal mxFifoReadIdx : unsigned(MAX_MXCACHE_BITS-1 downto 0); + signal mxInsnData : std_logic_vector(WORD_32BIT_RANGE); + signal mxMemVal : WordRecord; -- Direct memory read result. + signal mxHoldCycles : integer range 0 to 3; -- Cycles to hold and extend memory transactions. + + -- Hardware Debugging. + -- + signal debugPC : unsigned(ADDR_BIT_RANGE); -- Debug PC for reading L1, L2 and memory for debugger output. + signal debugPC_StartAddr : unsigned(ADDR_BIT_RANGE); -- Start address for dump of memory contents. + signal debugPC_EndAddr : unsigned(ADDR_BIT_RANGE); -- End address for dump of memory contents. + signal debugPC_Width : integer range 4 to 32; -- Width of output in bytes. + signal debugPC_WidthCounter : integer range 0 to 31; -- Counter to match variable width. + signal debugState : DebugType; + signal debugOutputOnce : std_logic; -- Signal to prevent continuous output of debug messages when in a wait. + signal debugAllInfo : std_logic; -- Output all information from start point of entry to debug FSM if set. + signal debugRec : zpu_dbg_t; + signal debugLoad : std_logic; -- Load a debug record into the debug serialiser fsm, 1 = load, 0 = inactive. + signal debugReady : std_logic; -- Flag to indicate serializer fsm is busy (0) or available (1). + + --------------------------------------------- + -- Functions + --------------------------------------------- + +begin + -- If the wishbone interface is enabled, assign permanent connections. + WB_INIT: if IMPL_USE_WB_BUS = true generate + --WB_CLK_I <= open; + ZPURESET <= RESET or WB_RST_I; + else generate + ZPURESET <= RESET; + end generate; + + --------------------------------------------- + -- Cache storage. + --------------------------------------------- + + -- Level 2 cache inferred with byte level write. + -- + CACHEL2 : work.evo_L2cache + generic map ( + addrbits => MAX_L2CACHE_BITS + ) + port map ( + clk => CLK, + memAAddr => std_logic_vector(cacheL2WriteAddr), + memAWriteEnable => cacheL2Write, + memAWriteByte => cacheL2WriteByte, + memAWriteHalfWord => cacheL2WriteHword, + memAWrite => cacheL2WriteData, + memARead => open, + + memBAddr => std_logic_vector(cacheL2Mux2Addr), + memBWrite => (others => '0'), + memBWriteEnable => '0', + memBRead => cacheL2Word + ); + + -- Instruction cache memory. cache instructions from the resync program counter forwards, when we get to a relative or direct + -- jump, if the destination is in cache, read from cache else resync. This speeds up operations where a resync (ie. branch, call etc) would + -- occur, saving cycles. It more especially speeds up the process if using one main bus and the external memory speed is slower than bram. + -- + -- Description of signals: + -- cacheL2StartAddr Absolute Start Address of word in first cache location. + -- cacheL2Active 1 when L2 cache is active, 0 when using dedicated instruction BRAM. + -- cacheL2Empty 1 when cache is empty, 0 when valid data present. + -- cacheL2Invalid 1 when the contents of L2Cache are no longer valid (due to next insn being out of cache scope). + -- cacheL2Mux2Addr Address multiplexer into cache. Address is set to the DebugPC address when the Debug state machine is not idle, all other times it is set to the Next cache fetch address. + -- cacheL2MxAddrInCache When a queued MX Processor address is in the L2 cache, set to 1 else set to 0. Used to determine if a memory write should be written into cache (write thru). + -- cacheL2Full 1 when cache is full, 0 otherwise. + -- + cacheL2Active <= '1' when IMPL_USE_INSN_BUS = false or (IMPL_USE_INSN_BUS = true and pc >= to_unsigned(MAX_INSNRAM_SIZE, pc'length)) + else '0'; + cacheL2Empty <= '1' when cacheL2FetchIdx(ADDR_32BIT_RANGE) = cacheL2StartAddr(ADDR_32BIT_RANGE) + else '0'; + cacheL2Invalid <= '1' when pc(ADDR_32BIT_RANGE) < cacheL2StartAddr(ADDR_32BIT_RANGE) or (pc(ADDR_32BIT_RANGE) > cacheL2FetchIdx(ADDR_32BIT_RANGE)) + else '0'; + cacheL2Mux2Addr <= cacheL1FetchIdx(L2CACHE_32BIT_RANGE) when DEBUG_CPU = false or (DEBUG_CPU = true and debugState = Debug_Idle) + else + debugPC(L2CACHE_32BIT_RANGE) when DEBUG_CPU = true + else + (others => 'X'); + cacheL2MxAddrInCache <= '1' when (to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)), cacheL2StartAddr'length) >= cacheL2StartAddr and to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)), cacheL2FetchIdx'length) < cacheL2FetchIdx) and (IMPL_USE_INSN_BUS = false or (IMPL_USE_INSN_BUS = true and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= MAX_INSNRAM_SIZE)) + else '0'; + cacheL2Full <= '1' when cacheL2FetchIdx(ADDR_32BIT_RANGE) - cacheL2StartAddr(ADDR_32BIT_RANGE) = MAX_L2CACHE_SIZE / 4 + else '0'; + --------------------------------------------- + -- End of Cache storage. + --------------------------------------------- + + ------------------------------------ + -- Memory transaction processor MXP. + ------------------------------------ + -- The mxp localises all memory/io operations into a single process. This aids in adaptation to differing bus topolgies as only this process + -- needs updating (the local INSN bus uses a direct BRAM/ROM connection and bypasses the MXP). This logic processes a queue of transactions in fifo + -- order and fetches instructions as required.. The processor unit commits requests to the queue and this logic fulfills them. If the CPU is only + -- using one bus for all memory and IO operations then memory transactions in the queue are completed before instruction fetches. If the instruction + -- queue is empty then the processor will stall until instructions are fetched. + -- + MEMXACT: process(CLK, ZPURESET, TOS, NOS, debugState) + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if ZPURESET = '1' then + MEM_WRITE_BYTE <= '0'; + MEM_WRITE_HWORD <= '0'; + MEM_READ_ENABLE <= '0'; + MEM_WRITE_ENABLE <= '0'; + WB_ADR_O(ADDR_32BIT_RANGE) <= (others => '0'); + WB_DAT_O <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '0'; + WB_STB_O <= '0'; + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + wbXactActive <= '0'; + cacheL2Write <= '0'; + cacheL2IncAddr <= '0'; + cacheL2FetchIdx <= (others => '0'); + cacheL2StartAddr <= (others => '0'); + mxFifoReadIdx <= (others => '0'); + mxState <= MemXact_Idle; + mxTOS <= ((others => '0'), '0'); + mxNOS <= ((others => '0'), '0'); + mxHoldCycles <= 0; + if DEBUG_CPU = true then + mxMemVal.valid <= '0'; + end if; + + ------------------------ + -- FALLING CLOCK EDGE -- + ------------------------ + elsif falling_edge(CLK) then + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(CLK) then + -- TOS/NOS values read in by the MXP are only valid for 1 cycle, so reset the valid flag. + mxTOS.valid <= '0'; + mxNOS.valid <= '0'; + + -- Memory signals are one clock width wide, reset them to inactive on each clock to ensure this.^^ + MEM_READ_ENABLE <= '0'; + MEM_WRITE_ENABLE <= '0'; + + -- Width signals are one clock width wide unless extended by busy signal. + if MEM_BUSY = '0' then + MEM_WRITE_BYTE <= '0'; + MEM_WRITE_HWORD <= '0'; + end if; + + -- Complete any active cache memory writes. + if cacheL2Write = '1' and mxHoldCycles = 0 then + cacheL2Write <= '0'; + cacheL2WriteByte <= '0'; + cacheL2WriteHword <= '0'; + + -- Once the cache write is complete, we update the address if needed, which will be setup in time for the next word to be read in from external memory. + if cacheL2IncAddr = '1' then + cacheL2IncAddr <= '0'; + + -- Update the address from where we fetch the next instruction, 32bit aligned 4 bytes. + cacheL2FetchIdx <= cacheL2FetchIdx + wordBytes; + end if; + end if; + + -- If wishbone interface is active and an ACK is received, deassert the signals. + if IMPL_USE_WB_BUS = true and wbXactActive = '1' and WB_ACK_I = '1' and WB_HALT_I = '0' and mxHoldCycles = 0 then + wbXactActive <= '0'; + WB_WE_O <= '0'; + WB_CYC_O <= '0'; + WB_STB_O <= '0'; + end if; + + -- TODO: WB_ERR_I needs better handling, should retry at least once and then issue a BREAK. + if IMPL_USE_WB_BUS = true and WB_ERR_I = '1' then + wbXactActive <= '0'; + WB_WE_O <= '0'; + WB_CYC_O <= '0'; + WB_STB_O <= '0'; + end if; + + -- If the hold cycle counter is not 0, then we are holding on the current transaction until it reaches zero, so decrement + -- ready to test next cycle. This mechanism is to prolong a memory cycle as without it, address setup and hold is 1 cycle and + -- valid data is expected at the end of the cycle. ie. the address and control signals are set on the current rising edge and become + -- active and on the next rising edge the data is expected to be valid, few components (ie. register ram) can meet this timing requirement. + if mxHoldCycles > 0 then + mxHoldCycles <= mxHoldCycles - 1; + end if; + + -- If the external memory is busy (1) or the wishbone interface is active and no ACK received then we have to back off and wait till next clock cycle and check again. + if MEM_BUSY = '0' and ((IMPL_USE_WB_BUS = true and ((wbXactActive = '1' and WB_ACK_I = '1') or wbXactActive = '0')) or IMPL_USE_WB_BUS = false) and mxHoldCycles = 0 then + + -- Memory transaction processor state machine. Idle is the control state and depending upon entries in the queue, debug or L2 usage, it + -- directs the FSM states accordingly. + case mxState is + when MemXact_Idle => + -- If there are no memory transactions to complete, debugging is enabled and the debug outputter is active, read the memory location + -- according to the given index. + if DEBUG_CPU = true and (mxFifoWriteIdx - mxFifoReadIdx) = 0 and (debugState /= Debug_Idle and debugState /= Debug_DumpL1 and debugState /= Debug_DumpL2 and debugState /= Debug_DumpMem) then + if IMPL_USE_WB_BUS = true and debugPC(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(debugPC(ADDR_32BIT_RANGE)); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxHoldCycles <= 1; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(debugPC(ADDR_32BIT_RANGE)); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE <= '1'; + end if; + mxMemVal.valid <= '0'; + mxState <= MemXact_MemoryFetch; + + -- If instruction queue is empty or there are no memory transactions to process and the instruction queue isnt full, + -- read the next instruction and fill the instruction queue. + elsif cacheL2Active = '1' and (mxFifoWriteIdx - mxFifoReadIdx) = 0 and cacheL2Invalid = '0' and cacheL2Full = '0' and cacheL2IncAddr = '0' then + if IMPL_USE_WB_BUS = true and cacheL2FetchIdx(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL2FetchIdx(ADDR_32BIT_RANGE)); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxHoldCycles <= 1; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL2FetchIdx(ADDR_32BIT_RANGE)); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE <= '1'; + end if; + cacheL2WriteAddr <= cacheL2FetchIdx(L2CACHE_BIT_RANGE); + mxHoldCycles <= 1; + mxState <= MemXact_OpcodeFetch; + + -- If there is an item on the queue and the memory system isnt busy from a previous operation, process + -- the queue item. + -- + elsif (mxFifoWriteIdx - mxFifoReadIdx) > 0 then + + -- Setup the address from the queue element and process the command. + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_CTI_O <= "000"; + WB_SEL_O <= "1111"; + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + end if; + mxHoldCycles <= 1; + + case mxFifo(to_integer(mxFifoReadIdx)).cmd is + -- Read to TOS + when MX_CMD_READTOS => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_TOS; + + -- Read to NOS + when MX_CMD_READNOS => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_NOS; + + -- Read both TOS and NOS (save cycles). + when MX_CMD_READTOSNOS => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_TOSNOS; + + -- Read Byte to TOS + when MX_CMD_READBYTETOTOS => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_ReadByteToTOS; + + -- Read Word to TOS + when MX_CMD_READWORDTOTOS => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_ReadWordToTOS; + + -- Read word and add to TOS + when MX_CMD_READADDTOTOS => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_ReadAddToTOS; + + -- Write value to address + when MX_CMD_WRITE => + mxFifoReadIdx <= mxFifoReadIdx + 1; + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_DAT_O <= mxFifo(to_integer(mxFifoReadIdx)).data; + WB_WE_O <= '1'; + wbXactActive <= '1'; + else + MEM_DATA_OUT <= mxFifo(to_integer(mxFifoReadIdx)).data; + MEM_WRITE_ENABLE <= '1'; + end if; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_BIT_RANGE)); + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + mxState <= MemXact_Idle; + mxHoldCycles <= 0; + + -- Read value at address, then write data to the value's address. + when MX_CMD_WRITETOINDADDR => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_WE_O <= '0'; + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + mxState <= MemXact_WriteToAddr; + + -- To write a byte, if hardware supports it, write out to the byte aligned address with data in bits 7-0 otherwise + -- we first read the 32bit word, update it and write it back. + when MX_CMD_WRITEBYTETOADDR => + -- If Hardware byte write not implemented or it is a write to the Startup ROM we have to resort + -- to a read-modify-write operation. + if IMPL_HW_BYTE_WRITE = false + then + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_32BIT_RANGE)) & "00"; + mxState <= MemXact_WriteByteToAddr; + else + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_DAT_O <= (others => 'X'); + case mxFifo(to_integer(mxFifoReadIdx)).addr(1 downto 0) is + when "00" => + WB_SEL_O <= "1000"; + WB_DAT_O(31 downto 24) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + when "01" => + WB_SEL_O <= "0100"; + WB_DAT_O(23 downto 16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + when "10" => + WB_SEL_O <= "0010"; + WB_DAT_O(15 downto 8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + when "11" => + WB_SEL_O <= "0001"; + WB_DAT_O(7 downto 0) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + end case; + + WB_ADR_O(ADDR_32BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0)<= (others => '0'); + WB_WE_O <= '1'; + wbXactActive <= '1'; + else + MEM_ADDR(ADDR_BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_BIT_RANGE); + MEM_WRITE_ENABLE <= '1'; + MEM_DATA_OUT <= X"000000" & mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0); + MEM_WRITE_BYTE <= '1'; + end if; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + mxHoldCycles <= 0; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_BIT_RANGE)); + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2WriteByte <= '1'; + cacheL2Write <= '1'; + end if; + end if; + + -- To write a word, if hardware supports it, write out to the word aligned address with data in bits 15-0 otherwise + -- we first read the 32bit word, update it and write it back. + when MX_CMD_WRITEHWORDTOADDR => + -- If Hardware half-word write not implemented or it is a write to the Startup ROM we have to resort + -- to a read-modify-write operation. + if IMPL_HW_WORD_WRITE = false + then + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + wbXactActive <= '1'; + else + MEM_READ_ENABLE <= '1'; + end if; + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_32BIT_RANGE)) & "00"; + mxState <= MemXact_WriteHWordToAddr; + else + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_DAT_O <= (others => 'X'); + case mxFifo(to_integer(mxFifoReadIdx)).addr(1) is + when '0' => + WB_SEL_O <= "1100"; + WB_DAT_O(31 downto 16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + when '1' => + WB_SEL_O <= "0011"; + WB_DAT_O(15 downto 0) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + end case; + WB_ADR_O(ADDR_32BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0)<= (others => '0'); + WB_WE_O <= '1'; + wbXactActive <= '1'; + else + MEM_ADDR(ADDR_BIT_RANGE)<= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_16BIT_RANGE) & "0"; + MEM_WRITE_ENABLE <= '1'; + MEM_DATA_OUT <= X"0000" & mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0); + MEM_WRITE_HWORD <= '1'; + end if; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteAddr <= unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(L2CACHE_BIT_RANGE)); + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2WriteHword <= '1'; + cacheL2Write <= '1'; + end if; + mxHoldCycles <= 0; + end if; + + when others => + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end case; + end if; + + when MemXact_MemoryFetch => + if DEBUG_CPU = true then + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxMemVal.word <= unsigned(WB_DAT_I); + else + mxMemVal.word <= unsigned(MEM_DATA_IN); + end if; + mxMemVal.valid <= '1'; + end if; + mxState <= MemXact_Idle; + + when MemXact_OpcodeFetch => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + cacheL2WriteData <= WB_DAT_I; + else + cacheL2WriteData <= MEM_DATA_IN; + end if; + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + cacheL2IncAddr <= '1'; + mxState <= MemXact_Idle; + + when MemXact_TOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word <= unsigned(WB_DAT_I); + else + mxTOS.word <= unsigned(MEM_DATA_IN); + end if; + mxTOS.valid <= '1'; + if cacheL2Active = '1' then + mxHoldCycles <= 1; + end if; + mxState <= MemXact_Idle; + + when MemXact_NOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxNOS.word <= unsigned(WB_DAT_I); + else + mxNOS.word <= unsigned(MEM_DATA_IN); + end if; + mxNOS.valid <= '1'; + if cacheL2Active = '1' then + mxHoldCycles <= 1; + end if; + mxState <= MemXact_Idle; + + when MemXact_TOSNOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word <= unsigned(WB_DAT_I); + else + mxTOS.word <= unsigned(MEM_DATA_IN); + MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE))) + 1, ADDR_32BIT_SIZE)); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE <= '1'; + mxHoldCycles <= 1; + end if; + mxTOS.valid <= '1'; + mxState <= MemXact_TOSNOS_2; + + when MemXact_TOSNOS_2 => + if IMPL_USE_WB_BUS = true and mxFifo(to_integer(mxFifoReadIdx)).addr(WB_SELECT_BIT) = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(to_unsigned(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE))) + 1, ADDR_32BIT_SIZE)); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '0'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxState <= MemXact_TOSNOS_3; + else + mxNOS.word <= unsigned(MEM_DATA_IN); + mxNOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + if cacheL2Active = '1' then + mxHoldCycles <= 1; + end if; + + when MemXact_TOSNOS_3 => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxNOS.word <= unsigned(WB_DAT_I); + mxNOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + + when MemXact_ReadByteToTOS => + mxTOS.word <= (others => '0'); + if wbXactActive = '1' then + mxTOS.word(7 downto 0) <= unsigned(WB_DAT_I(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8)); + else + mxTOS.word(7 downto 0) <= unsigned(MEM_DATA_IN(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8)); + end if; + mxTOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_ReadWordToTOS => + mxTOS.word <= (others => '0'); + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word(15 downto 0) <= unsigned(WB_DAT_I(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16)); + else + mxTOS.word(15 downto 0) <= unsigned(MEM_DATA_IN(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16)); + end if; + mxTOS.valid <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_ReadAddToTOS => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + mxTOS.word <= muxTOS.word + unsigned(WB_DAT_I); + else + mxTOS.word <= muxTOS.word + unsigned(MEM_DATA_IN); + end if; + mxTOS.valid <= '1'; + mxState <= MemXact_Idle; + + when MemXact_WriteToAddr => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + WB_ADR_O(ADDR_32BIT_RANGE) <= WB_DAT_I(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_DAT_O <= mxFifo(to_integer(mxFifoReadIdx)).data; + WB_WE_O <= '1'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + cacheL2WriteAddr <= unsigned(WB_DAT_I(L2CACHE_BIT_RANGE)); + else + MEM_ADDR(ADDR_32BIT_RANGE) <= MEM_DATA_IN(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_DATA_OUT <= mxFifo(to_integer(mxFifoReadIdx)).data; + MEM_WRITE_ENABLE <= '1'; + cacheL2WriteAddr <= unsigned(MEM_DATA_IN(L2CACHE_BIT_RANGE)); + end if; + + -- If the data write is to a cached location, update cache at same time. + if cacheL2MxAddrInCache = '1' then + cacheL2WriteData <= mxFifo(to_integer(mxFifoReadIdx)).data; + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_WriteByteToAddr => + -- For wishbone, we need to store the data and terminate the current cycle before we can commence a write cycle. + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + WB_DAT_O <= WB_DAT_I; + WB_DAT_O(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + cacheL2WriteData <= WB_DAT_I; + mxState <= MemXact_WriteByteToAddr2; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_DATA_OUT <= MEM_DATA_IN; + MEM_DATA_OUT(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + MEM_WRITE_ENABLE <= '1'; + cacheL2WriteData <= MEM_DATA_IN; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + -- If the data write is to a cached location, we have read the original value, so update cache with modified version. + if cacheL2MxAddrInCache = '1' then + -- Update the data to write with the actual changed byte, + cacheL2WriteData(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 0))))*8) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(7 downto 0)); + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + + when MemXact_WriteByteToAddr2 => + WB_ADR_O(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '1'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_WriteHWordToAddr => + if IMPL_USE_WB_BUS = true and wbXactActive = '1' then + WB_DAT_O <= WB_DAT_I; + WB_DAT_O(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + cacheL2WriteData <= WB_DAT_I; + mxState <= MemXact_WriteHWordToAddr2; + else + MEM_ADDR(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0'); + MEM_DATA_OUT <= MEM_DATA_IN; + MEM_DATA_OUT(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + cacheL2WriteData <= MEM_DATA_IN; + MEM_WRITE_ENABLE <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + end if; + -- If the data write is to a cached location, we have read the original value, so update cache with modified version. + if cacheL2MxAddrInCache = '1' then + -- Update the data to write with the actual changed byte, + cacheL2WriteData(((wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr(byteBits-1 downto 1))))*16) <= std_logic_vector(mxFifo(to_integer(mxFifoReadIdx)).data(15 downto 0)); + + -- Initiate a cache memory write. + cacheL2Write <= '1'; + end if; + + when MemXact_WriteHWordToAddr2 => + WB_ADR_O(ADDR_32BIT_RANGE) <= mxFifo(to_integer(mxFifoReadIdx)).addr(ADDR_32BIT_RANGE); + WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0'); + WB_WE_O <= '1'; + WB_CYC_O <= '1'; + WB_STB_O <= '1'; + WB_SEL_O <= "1111"; + wbXactActive <= '1'; + mxFifoReadIdx <= mxFifoReadIdx + 1; + mxState <= MemXact_Idle; + + when MemXact_Write => + mxState <= MemXact_Idle; + + when others => + end case; + end if; + + -- Instruction Level 2 cache, we read upto the limit then back off until the gap between executed and read instructions + -- gets to a watermark and then re-enable reading. This allows the cache to maintain a set of past and future instructions so that when a + -- branch or call occurs, there is a chance we already have the needed instructions in cache. + -- + if cacheL2Active = '1' then + + -- If L2 fetching has been halted and the PC approaches the threshold (detault 3/4) then advance the Start Address of L2 data and re-enable L2 filling. + if cacheL2FetchIdx(ADDR_32BIT_RANGE) > pc(ADDR_32BIT_RANGE) and pc(ADDR_32BIT_RANGE) > cacheL2StartAddr(ADDR_32BIT_RANGE) and (pc - cacheL2StartAddr) > ((MAX_L2CACHE_SIZE/4)*3) and cacheL2Full = '1' then + cacheL2StartAddr <= cacheL2StartAddr + 16; + end if; + + -- If the PC goes out of scope of L2 data, reset and start fetching a fresh from the current PC address. + if cacheL2Invalid = '1' then + cacheL2FetchIdx <= pc(ADDR_32BIT_RANGE) & "00"; + cacheL2StartAddr <= pc(ADDR_32BIT_RANGE) & "00"; + cacheL2Write <= '0'; + cacheL2IncAddr <= '0'; + if (mxFifoWriteIdx - mxFifoReadIdx) = 0 and (mxState = MemXact_Idle or mxState = MemXact_OpcodeFetch) then + mxState <= MemXact_Idle; + end if; + end if; + end if; + end if; + end process; + + -- Use a mux to get the latest TOS/NOS values. This saves 1 clock cycle between data being retrieved and processed. + muxTOS.valid <= mxTOS.valid or TOS.valid; + muxTOS.word <= mxTOS.word when mxTOS.valid = '1' else TOS.word; + muxNOS.valid <= mxNOS.valid or NOS.valid; + muxNOS.word <= mxNOS.word when mxNOS.valid = '1' else NOS.word; + ----------------------------------------------------------------------------------------------------------------------------------------------------------------- + + ------------------------------------------------------------------------------ + -- L1 Cache + -- + -- L1 cache is a very small closely coupled cache which holds a decoded + -- shadow copy of the L2 cache or the BRAM at the point of execution and a few + -- instructions ahead. It is implemented in logic cells to allow instant + -- random access. This is required to perform instruction optimisation such as + -- multiple IM's and also to allow extended 2+ byte instructions which have + -- almost zero penalty over 1 byte instructions. + ------------------------------------------------------------------------------ + CACHE_LEVEL1: process(CLK, ZPURESET, pc) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable tDecodedOpcode : InsnType; + variable tInsnOffset : unsigned(4 downto 0); + begin + + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if ZPURESET = '1' then + cacheL1StartAddr <= (others => '0'); + cacheL1FetchIdx <= (others => '0'); + l1State <= State_PreSetAddr; + MEM_READ_ENABLE_INSN <= '0'; + MEM_ADDR_INSN <= (others => DontCareValue); + + ------------------------ + -- FALLING CLOCK EDGE -- + ------------------------ + elsif falling_edge(CLK) then + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(CLK) then + + -- If the cache becomes invalid due to a change in the PC or no cached data available then resync. + if (cacheL1Invalid = '1' and cacheL1Empty = '0') then -- or (cacheL2Active = '1' and cacheL2Invalid = '1') then + + -- RESYNC L1 Cache with BRAM/L2 Cache starting at current PC value.. + cacheL1FetchIdx <= pc(ADDR_32BIT_RANGE) & "00"; + cacheL1StartAddr <= pc(ADDR_32BIT_RANGE) & "00"; + + -- For BRAM preset the next address. + if cacheL2Active = '0' then + MEM_ADDR_INSN(ADDR_32BIT_RANGE) <= std_logic_vector(pc(ADDR_32BIT_RANGE)); + MEM_ADDR_INSN(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE_INSN <= '1'; + --else for L2 the address is automatically set in cacheL1FetchIdx + end if; + + -- State machine goes directly to the latch address phase. + l1State <= State_LatchAddr; + + -- If there is space in the L1 cache and data is available in the L2 cache/BRAM and we are not outputting debug information, fetch the next word, decode and place in L1. + elsif cacheL1Full = '0' + and + -- If BRAM ensure the memory is ready, for L2 no need to wait as the pointers control the reading of L2 data. + ((cacheL2Active = '0' and MEM_BUSY_INSN = '0') or (cacheL2Active = '1')) + and + -- If using L2 cache then only process when cached data is available in L2. + (cacheL2Active = '0' or (cacheL2Active = '1' and cacheL2Empty = '0' and cacheL2FetchIdx(ADDR_32BIT_RANGE) > cacheL1FetchIdx(ADDR_32BIT_RANGE)+1 )) + and + -- If debugging, only process if the debug FSM is idle as the L2 address is muxed with the debug address. + ((DEBUG_CPU = false or (DEBUG_CPU = true and debugState = Debug_Idle))) then + + case l1State is + when State_PreSetAddr => + -- For BRAM, set the address to read, external memory via L2 cache is set by the cacheL1FetchIdx signal. + if cacheL2Active = '0' then + MEM_ADDR_INSN(ADDR_32BIT_RANGE) <= std_logic_vector(pc(ADDR_32BIT_RANGE)); + MEM_ADDR_INSN(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE_INSN <= '1'; + --else for L2 the address is automatically set in cacheL1FetchIdx + end if; + l1State <= State_LatchAddr; + + -- This state gives time for the BRAM/L2 to latch the address ready for decode. + when State_LatchAddr => + l1State <= State_Decode; + + when State_Decode => + -- Read cycle for BRAM is at least one clock, so on next cycle clear the BRAM read signal. + if cacheL2Active = '0' then + MEM_READ_ENABLE_INSN <= '0'; + -- else for L2 there is no distinct signal, always outputs data for given input address. + end if; + + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + if cacheL2Active = '0' then + tOpcode := MEM_DATA_IN_INSN((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + else + tOpcode := cacheL2Word((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + end if; + + tInsnOffset(4) := not tOpcode(4); + tInsnOffset(3 downto 0) := unsigned(tOpcode(3 downto 0)); + + if (tOpcode(7 downto 7) = OpCode_Im) then tDecodedOpcode := Insn_Im; + + elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then tDecodedOpcode := Insn_StoreSP; + + elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then tDecodedOpcode := Insn_LoadSP; + + -- Emulated instructions, if there is no defined state to handle the instruction in hardware then it automatically runs the instruction + -- microcode from the vector 0x0+xxxxx*32. + elsif (tOpcode(7 downto 5) = OpCode_Emulate) then tDecodedOpcode := Insn_Emulate; + + if tOpcode(5 downto 0) = OpCode_Neqbranch then tDecodedOpcode := Insn_Neqbranch; + elsif tOpcode(5 downto 0) = OpCode_Eqbranch then tDecodedOpcode := Insn_Eqbranch; + elsif IMPL_EQ = true and tOpcode(5 downto 0) = OpCode_Eq then tDecodedOpcode := Insn_Eq; + elsif tOpcode(5 downto 0) = OpCode_Lessthan then tDecodedOpcode := Insn_Lessthan; + elsif tOpcode(5 downto 0) = OpCode_Lessthanorequal then tDecodedOpcode := Insn_Lessthanorequal; + elsif tOpcode(5 downto 0) = OpCode_Ulessthan then tDecodedOpcode := Insn_Ulessthan; + elsif tOpcode(5 downto 0) = OpCode_Ulessthanorequal then tDecodedOpcode := Insn_Ulessthanorequal; + elsif IMPL_LOADB = true and tOpcode(5 downto 0) = OpCode_Loadb then tDecodedOpcode := Insn_Loadb; + elsif IMPL_LOADH = true and tOpcode(5 downto 0) = OpCode_Loadh then tDecodedOpcode := Insn_Loadh; + elsif IMPL_MULT = true and tOpcode(5 downto 0) = OpCode_Mult then tDecodedOpcode := Insn_Mult; + elsif IMPL_STOREB = true and tOpcode(5 downto 0) = OpCode_Storeb then tDecodedOpcode := Insn_Storeb; + elsif IMPL_STOREH = true and tOpcode(5 downto 0) = OpCode_Storeh then tDecodedOpcode := Insn_Storeh; + elsif IMPL_PUSHSPADD = true and tOpcode(5 downto 0) = OpCode_Pushspadd then tDecodedOpcode := Insn_Pushspadd; + elsif IMPL_CALLPCREL = true and tOpcode(5 downto 0) = OpCode_Callpcrel then tDecodedOpcode := Insn_Callpcrel; + elsif IMPL_CALL = true and tOpcode(5 downto 0) = OpCode_Call then tDecodedOpcode := Insn_Call; + elsif IMPL_SUB = true and tOpcode(5 downto 0) = OpCode_Sub then tDecodedOpcode := Insn_Sub; + elsif IMPL_POPPCREL = true and tOpcode(5 downto 0) = OpCode_PopPCRel then tDecodedOpcode := Insn_PopPCRel; + elsif IMPL_LSHIFTRIGHT = true and tOpcode(5 downto 0) = OpCode_Lshiftright then tDecodedOpcode := Insn_Alshift; + elsif IMPL_ASHIFTLEFT = true and tOpcode(5 downto 0) = OpCode_Ashiftleft then tDecodedOpcode := Insn_Alshift; + elsif IMPL_ASHIFTRIGHT = true and tOpcode(5 downto 0) = OpCode_Ashiftright then tDecodedOpcode := Insn_Alshift; + elsif IMPL_XOR = true and tOpcode(5 downto 0) = OpCode_Xor then tDecodedOpcode := Insn_Xor; + elsif IMPL_DIV = true and tOpcode(5 downto 0) = OpCode_Div then tDecodedOpcode := Insn_Div; + elsif IMPL_MOD = true and tOpcode(5 downto 0) = OpCode_Mod then tDecodedOpcode := Insn_Mod; + elsif IMPL_NEG = true and tOpcode(5 downto 0) = OpCode_Neg then tDecodedOpcode := Insn_Neg; + elsif IMPL_NEQ = true and tOpcode(5 downto 0) = OpCode_Neq then tDecodedOpcode := Insn_Neq; + elsif IMPL_FIADD32 = true and tOpcode(5 downto 0) = OpCode_FiAdd32 then tDecodedOpcode := Insn_FiAdd32; + elsif IMPL_FIDIV32 = true and tOpcode(5 downto 0) = OpCode_FiDiv32 then tDecodedOpcode := Insn_FiDiv32; + elsif IMPL_FIMULT32 = true and tOpcode(5 downto 0) = OpCode_FiMult32 then tDecodedOpcode := Insn_FiMult32; + + end if; + + elsif (tOpcode(7 downto 4) = OpCode_AddSP) then + if tInsnOffset = 0 then tDecodedOpcode := Insn_Shift; + elsif tInsnOffset = 1 then tDecodedOpcode := Insn_AddTop; + else tDecodedOpcode := Insn_AddSP; + end if; + + -- Extended multibyte instruction set. If the extend instruction is encountered then during the execution phase the lookahead mechanism is used to determine + -- the extended instruction and execute accordingly. + elsif IMPL_EXTENDED_INSN = true and tOpcode(3 downto 0) = Opcode_Extend then tDecodedOpcode := Insn_Extend; + + else + case tOpcode(3 downto 0) is + when OpCode_Nop => tDecodedOpcode := Insn_Nop; + when OpCode_PushSP => tDecodedOpcode := Insn_PushSP; + when OpCode_PopPC => tDecodedOpcode := Insn_PopPC; + when OpCode_Add => tDecodedOpcode := Insn_Add; + when OpCode_Or => tDecodedOpcode := Insn_Or; + when OpCode_And => tDecodedOpcode := Insn_And; + when OpCode_Load => tDecodedOpcode := Insn_Load; + when OpCode_Not => tDecodedOpcode := Insn_Not; + when OpCode_Flip => tDecodedOpcode := Insn_Flip; + when OpCode_Store => tDecodedOpcode := Insn_Store; + when OpCode_PopSP => tDecodedOpcode := Insn_PopSP; + when others => tDecodedOpcode := Insn_Break; + end case; + end if; + + -- Store the decoded op directly into L1 cache. + cacheL1(to_integer(cacheL1FetchIdx+i))(DECODED_RANGE) <= std_logic_vector(to_unsigned(InsnType'POS(tDecodedOpcode), 6)); + cacheL1(to_integer(cacheL1FetchIdx+i))(OPCODE_RANGE) <= tOpcode; + end loop; + + -- Set address for next read, via cacheL1FetchIdx for L2 and external signals for BRAM. NB cacheL1FetchIdx always points to the next + -- available slot except during this state of the decoder. + cacheL1FetchIdx <= cacheL1FetchIdx + wordBytes; + + -- If we are not using L2 cache then take instructions direct from instruction BRAM. If a seperate + -- Instruction BRAM is not implemented, this will be ignored as L2 is our only source. + -- + if cacheL2Active = '0' then + MEM_ADDR_INSN(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL1FetchIdx(ADDR_32BIT_RANGE)+1); + MEM_ADDR_INSN(minAddrBit-1 downto 0) <= (others => '0'); + MEM_READ_ENABLE_INSN <= '1'; + --else for L2 the address is automatically set in cacheL1FetchIdx + end if; + + -- Repeat the fetch and decode until the L1 cache is full then disable fetching until a space becomes available. + -- We halt just before the full mark because it takes one cycle to halt. + l1State <= State_LatchAddr; + + when others => + l1State <= State_PreSetAddr; + end case; + + -- If there is only a set number of instructions remaining in the cache then we need to creep the start address forward so that + -- more instructions are fetched and decoded. We do this to ensure as many past instructions are available for backward jumps which + -- are most common in C. Adjust the threshold if forward jumps are more common. + elsif cacheL1InsnAfterPC < 8 and cacheL1Full = '1' then + cacheL1StartAddr <= cacheL1StartAddr + 8; + end if; + end if; + end process; + + -- Description of signals: + -- cacheL1StartAddr Absolute Start Address of word in first cache location. + -- cacheL1FetchIdx Next location a decoded instruction set (4 instructions) will be written into. + -- cacheL1InsnAfterPC Number of instructions stored in cache forward of current PC. + -- cacheL1Empty 1 when cache is empty, 0 when valid data present. + -- cacheL1Invalid 1 when cache doesnt have any valid instructions stored. + -- cacheL1Full 1 when cache is full, 0 otherwise. + -- + cacheL1InsnAfterPC <= cacheL1FetchIdx - pc when cacheL1Invalid = '0' + else to_unsigned(0, cacheL1InsnAfterPC'length); + cacheL1Empty <= '1' when cacheL1FetchIdx(ADDR_32BIT_RANGE) = cacheL1StartAddr(ADDR_32BIT_RANGE) + else '0'; + cacheL1Invalid <= '0' when (cacheL2Active = '0' or (cacheL2Active = '1' and cacheL2Invalid = '0')) and pc(ADDR_32BIT_RANGE) >= cacheL1StartAddr(ADDR_32BIT_RANGE) and pc(ADDR_32BIT_RANGE) < cacheL1FetchIdx(ADDR_32BIT_RANGE) + else '1'; + cacheL1Full <= '1' when cacheL1FetchIdx(ADDR_32BIT_RANGE) - cacheL1StartAddr(ADDR_32BIT_RANGE) = MAX_L1CACHE_SIZE / 4 + else '0'; + ------------------------------------------------------------------------------ + -- End of L1 Cache + ------------------------------------------------------------------------------ + + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Processor - Execution unit. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + PROCESSOR: process(CLK, ZPURESET, TOS, NOS, cacheL1, pc, sp, mxTOS, mxNOS, cacheL1FetchIdx, cacheL1StartAddr, cacheL2Active, cacheL2Empty, inBreak) + variable tSpOffset : unsigned(4 downto 0); + variable tIdx : integer range 0 to 3; + variable tInsnExec : std_logic; + variable tMultResult : unsigned(wordSize*2-1 downto 0); + variable tShiftCnt : integer range 0 to 31; + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + -- Prepare general stack possibility addresses, ie. Popped, 2xPopped or Pushed. + -- + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + incPC <= pc + 1; + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if ZPURESET = '1' then + inBreak <= '0'; + INT_ACK <= '0'; + INT_DONE <= '0'; + tIdx := 0; + tSpOffset := (others => '0'); + state <= State_Init; + sp <= to_unsigned(STACK_ADDR, maxAddrBit)(ADDR_32BIT_RANGE); + pc <= to_unsigned(RESET_ADDR_CPU, pc'LENGTH); + pcLast <= to_unsigned(RESET_ADDR_CPU, pc'LENGTH); + idimFlag <= '0'; + inInterrupt <= '0'; + mxFifoWriteIdx <= (others => '0'); + interruptSuspendedAddr <= (others => '0'); + TOS <= ((others => '0'), '0'); + NOS <= ((others => '0'), '0'); + -- + if IMPL_MULT = true then + tMultResult := (others => DontCareValue); + end if; + if IMPL_DIV = true or IMPL_FIDIV32 = true or IMPL_MOD = true then + divStart <= '0'; + divQuotientFractional <= 0; + end if; + if IMPL_FIADD32 = true or IMPL_FIMULT32 = true then + quotientFractional <= 15; + end if; + if DEBUG_CPU = true then + debugRec <= ZPU_DBG_T_INIT; + debugLoad <= '0'; + debugState <= Debug_Idle; + debugAllInfo <= '0'; + debugPC_StartAddr <= (others => '0'); + debugPC_EndAddr <= (others => '0'); + debugPC_Width <= 32; + debugPC_WidthCounter <= 0; + debugOutputOnce <= '0'; + else + debugPC_StartAddr <= (others => DontCareValue); + debugPC_EndAddr <= (others => DontCareValue); + debugPC_Width <= 32; + debugPC_WidthCounter <= 0; + debugRec <= ZPU_DBG_T_DONTCARE; + debugLoad <= DontCareValue; + debugReady <= DontCareValue; + debugOutputOnce <= DontCareValue; + end if; + + ------------------------ + -- FALLING CLOCK EDGE -- + ------------------------ + elsif falling_edge(CLK) then + + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(CLK) then + + --if DEBUG_CPU = true and debugState = Debug_Idle and pc = X"058be" then + -- debugPC_StartAddr <= X"01fc00"; --to_unsigned(131072-(512*3), debugPC_StartAddr'LENGTH); + -- debugPC_EndAddr <= X"01ff00"; --to_unsigned(131072, debugPC_EndAddr'LENGTH); + -- debugPC_Width <= 4; + -- debugState <= Debug_DumpMem; + --end if; + + if DEBUG_CPU = true and debugState = Debug_Idle and pc = X"1002b67" then --cacheL1FetchIdx < cacheL1FetchIdx_last then + debugState <= Debug_Start; + end if; + + -- In debug mode, the memory dump start and stop address are controlled by 2 vectors, preload them with defaults if uninitialised. + if DEBUG_CPU = true and debugPC_EndAddr = 0 then + debugPC_StartAddr <= to_unsigned(16#1000000#, debugPC_StartAddr'LENGTH); + debugPC_EndAddr <= to_unsigned(16#1001000#, debugPC_EndAddr'LENGTH); + end if; + + -- If the Memory Transaction processor has updated the stack parameters, update our working copy. + -- + if mxTOS.valid = '1' then + TOS.valid <= '1'; + TOS.word <= mxTOS.word; + end if; + if mxNOS.valid = '1' then + NOS.valid <= '1'; + NOS.word <= mxNOS.word; + end if; + + -- If debugging enabled, loading of debug information into the debug serialiser is only 1 clock width wide, reset on each clock tick. + -- + if DEBUG_CPU = true then + debugLoad <= '0'; + end if; + + -- Multiply unconditionally the TOS and NOS to save time obtaining result. + if IMPL_MULT = true then + tMultResult := muxTOS.word * muxNOS.word; + end if; + + -- Division start is only 1 clock width wide. + if IMPL_DIV = true or IMPL_FIDIV32 = true or IMPL_MOD = true then + divStart <= '0'; + divQuotientFractional <= 15; -- Always reset the quotient, integer division sets to 0 as no fractional component. + end if; + + -- If interrupt is active, we only clear the interrupt state once the PC is reset to the address which was suspended after the + -- interrupt, this prevents recursive interrupt triggers, desirable in cetain circumstances but not for this current design. + -- + INT_ACK <= '0'; -- Reset interrupt acknowledge if set, width is 1 clock only. + INT_DONE <= '0'; -- Reset interrupt done if set, width is 1 clock only. + if inInterrupt = '1' and pc(ADDR_BIT_RANGE) = interruptSuspendedAddr(ADDR_BIT_RANGE) then + inInterrupt <= '0'; -- no longer in an interrupt + INT_DONE <= '1'; -- Interrupt service routine complete. + end if; + + -- BREAK signal follows internal signal on clock edge. + BREAK <= inBreak; + + ------------------------------------- + -- Execution Processor. + ------------------------------------- + if (DEBUG_CPU = false or (DEBUG_CPU = true and debugReady = '1')) then + + case state is + -- If the emulation cache is implemented, initialise it else startup the CPU. + when State_Init => + state <= State_Idle; + + -- Idle the CPU if ENABLE signal is low. + -- + when State_Idle => + if ENABLE = '1' then + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + + if DEBUG_CPU = true and DEBUG_LEVEL >= 4 and debugState = Debug_Idle then + debugPC_StartAddr <= to_unsigned(0, debugPC_StartAddr'LENGTH); + debugPC_EndAddr <= to_unsigned(65536, debugPC_EndAddr'LENGTH); + debugState <= Debug_DumpMem; + end if; + end if; + + -- Each instruction must: + -- + -- 1. set idimFlag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + when State_Execute => + + -- If the debug state machine is outputting data, hold off from further actions. + if DEBUG_CPU = true and debugState /= Debug_Idle then + + -- When a break is active, all processing is suspended. + elsif inBreak = '1' then + + -- If continue flag set, resume with next instruction. + if CONTINUE = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + inBreak <= '0'; + end if; + + -- Act immediately if an interrupt has occurred. Do not recurse into ISR while interrupt line is active + elsif (INT_REQ = '1' or (IMPL_USE_WB_BUS = true and WB_INTA_I = '1')) and inInterrupt = '0' and idimFlag = '0' then + + -- We have to wait for TOS and NOS to become valid so they can be saved, so loop until they are valid. + if muxTOS.valid = '1' and muxNOS.valid = '1' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + INT_ACK <= '1'; -- Acknowledge interrupt. + interruptSuspendedAddr <= pc(ADDR_BIT_RANGE); -- Save address which got interrupted. + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= pc; + NOS.word <= muxTOS.word; + pc <= to_unsigned(32+START_ADDR_MEM, maxAddrBit); -- Load Vector 0x20 (from memory start) as next address to execute from. + sp <= decSp; + + -- Setup a memory transaction to save NOS back to RAM, TOS in effect already popped. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- If debug enabled, write out state during fetch. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(6, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"494D544552505400"; + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end if; + + -- If the CPU is externally disabled during processing, go to the Idle state and wait until it is re-enabled. + -- + elsif ENABLE = '0' then + state <= State_Idle; + + -- Execution depends on the L1 having decoded instructions stored at the current PC. + -- As a minimum the cache must be valid and that there is at least 1 instruction in the cache. + elsif cacheL1Invalid = '0' and cacheL1InsnAfterPC > 4 then -- and (cacheL2Active = '0' or (cacheL2Active = '1' and cacheL2Full = '1')) then + + -- Remember the last PC location executed, used for jump detection. + pcLast <= pc; + + -- Set the stack offset for current instruction from its opcode. + tSpOffset(4) := not cacheL1(to_integer(pc))(4); + tSpOffset(3 downto 0) := unsigned(cacheL1(to_integer(pc)))(3 downto 0); + tInsnExec := '0'; + if DEBUG_CPU = true then + debugOutputOnce <= '0'; + end if; + + -------------------------------------------------------------------------------------------------------------- + -- Start of Instruction Execution Case block - process the current instruction held in L1 Cache. + -------------------------------------------------------------------------------------------------------------- + case InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE)))) is + + -- Immediate, store 7bit signed extended value into TOS. If this is the first Im then we set IDIM, if this is a subsequent Im following + -- on from other Im's without gap, then we shift TOS 7 bits to left and add in the new value. NB. First Im, bit 6 of bits 6-0 is used to set + -- all bits 31 downto 6 with the same value. + -- An optimisation has been added where by if more than 1 Im are sequential and in the L1 cache, then the result is calculated in 1 cycle. If due + -- to not enough cache data a > 1 Im is partially processed, ie. 3 Im out of 5, then the 3 are processed in 1 cycle and the remaining two in seperate + -- cycles. + when Insn_Im => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '1'; + pc <= incPC; + + -- If this is the first Im (single or non-cached) or this is a multi Im instruction, save current TOS and build new TOS from Im. + -- + if idimFlag = '0' then + -- As we are pushing a value, current TOS becomes NOS and we write back old NOS to memory. + NOS.word <= muxTOS.word; + sp <= decSp; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- All Im combinations sign extend the 7th bit of the first Im instruction then just overwrite the bits available. + for i in wordSize-1 downto 7 loop + TOS.word(i) <= cacheL1(to_integer(pc))(6); + end loop; + + -- For non-optimised hardware or optimised but we only have 1 Im, used the original logic. + if IMPL_OPTIMIZE_IM = false then + TOS.word(IM_DATA_RANGE) <= unsigned(cacheL1(to_integer(pc))(IM_DATA_RANGE)); + + -- If Im optimisation is enabled, work out if we have sufficient instructions and then determine how many Ims are grouped together, otherwise default to just 1 Im per time processing. + elsif IMPL_OPTIMIZE_IM = true then + + -- Debug code, if enabled, writes out the data relevant to the Im instruction being optimised. + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 and cacheL1FetchIdx(L1CACHE_BIT_RANGE) - pc(L1CACHE_BIT_RANGE) > 2 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA2(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.DATA3(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)); + debugRec.DATA4(63 downto 0) <= "0000000000000000" & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 16)) & std_logic_vector(cacheL2FetchIdx(15 downto 0)) & "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & "0000" & idimFlag & tInsnExec & cacheL2Full & cacheL2Write; + debugRec.OPCODE <= (others => DontCareValue); + debugRec.DECODED_OPCODE <= (others => DontCareValue); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + + -- TODO: + -- Perhaps use cacheL1InsnAfterPC in this loop to preserve logic. + -- Same for extended instructions. + -- + -- 5 Consecutive IM's + if cacheL1FetchIdx - pc > 5 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(pc)+1)(7) = '1' and cacheL1(to_integer(pc)+2)(7) = '1' and cacheL1(to_integer(pc)+3)(7) = '1' and cacheL1(to_integer(pc)+4)(7) = '1' and cacheL1(to_integer(pc)+5)(7) = '0' then + TOS.word(31 downto 0) <= unsigned(cacheL1(to_integer(pc))(3 downto 0)) & unsigned(cacheL1(to_integer(pc)+1)(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(pc)+2)(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(pc)+3)(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(pc)+4)(OPCODE_IM_RANGE)); + pc <= pc + 5; + -- 4 Consecutive IM's + elsif cacheL1FetchIdx - pc > 4 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(pc)+1)(7) = '1' and cacheL1(to_integer(pc)+2)(7) = '1' and cacheL1(to_integer(pc)+3)(7) = '1' and cacheL1(to_integer(pc)+4)(7) = '0' then + TOS.word(27 downto 0) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(pc)+1)(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(pc)+2)(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(pc)+3)(OPCODE_IM_RANGE)); + pc <= pc + 4; + -- 3 Consecutive IM's + elsif cacheL1FetchIdx - pc > 3 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(pc)+1)(7) = '1' and cacheL1(to_integer(pc)+2)(7) = '1' and cacheL1(to_integer(pc)+3)(7) = '0' then + TOS.word(20 downto 0) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(pc)+1)(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(pc)+2)(OPCODE_IM_RANGE)); + pc <= pc + 3; + -- 2 Consecutive IM's + elsif cacheL1FetchIdx - pc > 2 and cacheL1(to_integer(pc))(7) = '1' and cacheL1(to_integer(pc)+1)(7) = '1' and cacheL1(to_integer(pc)+2)(7) = '0' then + TOS.word(13 downto 0) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)) & unsigned(cacheL1(to_integer(pc)+1)(OPCODE_IM_RANGE)); + pc <= pc + 2; + -- 1 IM + else + TOS.word(IM_DATA_RANGE) <= unsigned(cacheL1(to_integer(pc))(OPCODE_RANGE)(IM_DATA_RANGE)); + end if; + end if; + else + -- Further single Im instructions shift left by 7 bits then add it the value from the current opcode. + TOS.word(wordSize-1 downto 7) <= muxTOS.word(wordSize-8 downto 0); + TOS.word(IM_DATA_RANGE) <= unsigned(cacheL1(to_integer(pc))(OPCODE_IM_RANGE)); + end if; + end if; + + -- Store into Stack pointer + offset, write out the value in TOS to the location pointed by Stack pointer plus any offset given in the opcode. + when Insn_StoreSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + tIdx := 0; + idimFlag <= '0'; + sp <= incSp; + pc <= incPC; + + -- Always need to read the new NOS location into NOS unless the offset is 2 when the location will be + -- overwritten with TOS, so just use TOS. + if tSpOffset /= 2 then + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + tIdx := tIdx + 1; + end if; + + -- Write value of TOS to the memory location sp + offset stored in opcode if offset not 0 or 1. + -- + if tSpOffset >= 2 then + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).addr(ADDR_32BIT_RANGE)<= std_logic_vector(sp+tSpOffset); + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).data<= std_logic_vector(muxTOS.word); + mxFifo(to_integer(mxFifoWriteIdx)+tIdx).cmd <= MX_CMD_WRITE; + tIdx := tIdx + 1; + end if; + + case tSpOffset is + -- If the offset is 0, we are writing into unused stack (as the stack pointer is incremented), so just assign + -- NOS to TOS and read the new NOS. + when "00000" => + TOS.word <= muxNOS.word; + + -- If the offset is 1 then we do nothing as a write of TOS to SP+1 is the location of the new TOS, so TOS doesnt change. + -- We read NOS though from the new location. + when "00001" => + + -- When offset is 2, TOS is written to the new NOS position in memory, so no point to reread, we just reuse TOS. + -- + when "00010" => + NOS.word <= muxTOS.word; + TOS.word <= muxNOS.word; + + -- All other cases TOS becomes NOS and we read the new NOS . + -- + when others => + TOS.word <= muxNOS.word; + end case; + + mxFifoWriteIdx <= mxFifoWriteIdx + tIdx; + end if; + + -- Load from Stack pointer + offset: save NOS onto stack (TOS is popped and no longer needed so we are not concerned), read into TOS + -- the value pointed to by the SP + Offset. NOS becomes the old TOS as we virtually pushed the read value onto the stack. + when Insn_LoadSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + sp <= decSp; + pc <= incPC; + + -- Commit NOS to memory as we will refresh NOS from TOS. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- If the offset is 0 then we are duplicating TOS into NOS. + if tSpOffset = 0 then + NOS.word <= muxTOS.word; + + -- If the offset is 1 then we are duplicating NOS into TOS. + elsif tSpOffset = 1 then + TOS.word <= muxNOS.word; + NOS.word <= muxTOS.word; + + -- Else we read the value at Sp + Offset into TOS. + else + -- Read TOS from the location pointed to by SP + Offset. + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_32BIT_RANGE) <= std_logic_vector(sp+tSpOffset); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_READTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + + -- NOS becomes TOS as we are pushing a new value onto the stack. + NOS.word <= muxTOS.word; + end if; + end if; + + -- Emulate. This is a dummy placeholder for instructions which have not been implemented in hardware. If an Opcode cannot be translated to + -- a state machine state, it falls through to here, the NOS is saved back onto the stack, TOS is set to NOS and TOS takes on + -- the next program counter value (ie. next instruction after the one which is not implemented). The Program counter is then set + -- to the vector containing the microcode to implement the instruction and a jump is made to that location. When the microcode is complete it + -- should set the Program counter to the value stored in TOS. + when Insn_Emulate => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + sp <= decSp; + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= incPC; + NOS.word <= muxTOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + + -- The emulate address is calculated by the opcode value left shifted 5 places. If the BRAM start address is not zero then this is added to ensure the + -- emulation microcode is read form the BRAM: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= to_unsigned(to_integer(unsigned(cacheL1(to_integer(pc))(OPCODE_RANGE)(4 downto 0)) & "00000"), pc'LENGTH) + START_ADDR_MEM; + end if; + + -- Call function relative to current PC value. The Program counter for the next instruction after this (ie. call return address) is stored in TOS + -- and the Program counter is set to the value currently in TOS+PC (remember that assignments only occur at end of the cycle, so writing to TOS wont + -- actually happen until the moment we leave this cycle) and we start processing from the new Program counter location, or the called location. + when Insn_Callpcrel => + if IMPL_CALLPCREL = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= incPC; + pc <= pc + muxTOS.word(ADDR_BIT_RANGE); + end if; + end if; + + -- Call function. Same as above except the PC is set to the value stored in TOS, not TOS+PC. + when Insn_Call => + if IMPL_CALL = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + -- TOS.word <= (others => DontCareValue); + TOS.word(ADDR_BIT_RANGE) <= incPC; + pc <= muxTOS.word(ADDR_BIT_RANGE); + end if; + end if; + + -- Add value from location pointed to bye Stack Pointer. Setup to read the value stored at Stack pointer location + offset contained + -- in the OpCode. We then forward to the next state which adds the value read to the value stored in TOS. + when Insn_AddSP => + -- if TOS.valid = '1' and NOS.valid = '1' then + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(sp+tSpOffset); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READADDTOTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Push stack pointer. TOS is set to stack pointer value and old TOS value assigned to NOS. The current NOS value is written out + -- onto the stack. In effect TOS = sp, NOS = TOS and NOS stored to NOS-1, we accomplish a push stack pointer onto the stack. + when Insn_PushSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= decSp; + TOS.word <= (others => '0'); + TOS.word(ADDR_32BIT_RANGE) <= sp; + NOS.word <= muxTOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Pop the value on the stack into the Program counter. This is accomplished by setting the PC to the TOS value, then writing out the + -- NOS value (because NOS and TOS are not normally stored, they are held in register) and performing a resync. + when Insn_PopPC => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= muxTOS.word(ADDR_BIT_RANGE); + sp <= incSp; + TOS.word <= muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Same as above except the program counter is added to the value in TOS before being assigned to the next program counter value. + when Insn_PopPCRel => + if IMPL_POPPCREL = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= pc + muxTOS.word(ADDR_BIT_RANGE); + sp <= incSp; + TOS.word <= muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Add NOS to TOS and store into TOS. NOS is then read from the stack. + when Insn_Add => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxTOS.word + muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Subtract NOS from TOS and store into TOS. NOS is then read from the stack. + when Insn_Sub => + if IMPL_SUB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxNOS.word - muxTOS.word; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform a logical OR between TOS and NOS and store the result in TOS. We then retrieve the next stack value into NOS. + when Insn_Or => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxTOS.word or muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a logical AND between TOS and NOS and store the result in TOS. We then retrieve the next stack value into NOS. + when Insn_And => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxTOS.word and muxNOS.word; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a Equal comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next stack value into NOS. + when Insn_Eq => + if IMPL_EQ = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (muxTOS.word = muxNOS.word) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform an unsigned less than comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next stack value into NOS. + when Insn_Ulessthan => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (muxTOS.word < muxNOS.word) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform an unsigned less than or equal comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next + -- stack value into NOS. + when Insn_Ulessthanorequal => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (muxTOS.word <= muxNOS.word) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a signed less than comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next stack value into NOS. + when Insn_Lessthan => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (signed(muxTOS.word) < signed(muxNOS.word)) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Perform a signed less than or equal comparison between TOS and NOS and store 1 in TOS if equal otherwise 0. We then retrieve the next + -- stack value into NOS. + when Insn_Lessthanorequal => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (signed(muxTOS.word) <= signed(muxNOS.word)) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Load TOS (next cycle) with the value pointed to by TOS. + when Insn_Load => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Write the NOS value to the memory location pointed by TOS. + when Insn_Store => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incIncSp; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE)<= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + + -- Write the NOS value into memory location pointed to by the current Stack Pointer - 1 (ie. next of stack), + -- then set the Stack Pointer to the current TOS value. + when Insn_PopSP => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= muxTOS.word(ADDR_32BIT_RANGE); + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_WRITE; + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + + -- No operation, just waste time. + when Insn_Nop => + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + -- Negate the TOS value. + when Insn_Not => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word <= not muxTOS.word; + end if; + + -- Reverse all the bits in the TOS. + when Insn_Flip => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + for i in 0 to wordSize-1 loop + TOS.word(i) <= muxTOS.word(wordSize-1-i); + end loop; + end if; + + -- Add the TOS and NOS together, store in the TOS. + when Insn_AddTop => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word <= muxTOS.word + muxNOS.word; + end if; + + -- Shift the TOS right 1 bit. + when Insn_Shift => + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word(wordSize-1 downto 1) <= muxTOS.word(wordSize-2 downto 0); + TOS.word(0) <= '0'; + end if; + + -- Add the TOS to the Stack Pointer and store in TOS. This is word aligned so bits 0 & 1 are zero. + when Insn_Pushspadd => + if IMPL_PUSHSPADD = true then + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + + TOS.word <= (others => '0'); + TOS.word(ADDR_32BIT_RANGE) <= muxTOS.word((maxAddrBit-1)-minAddrBit downto 0)+sp; + end if; + end if; + + -- If the NOS is not 0 (or 0 for Eq) then add the TOS to the Program Counter. As the address is not guaranteed to be sequential, resync to + -- retrieve the new TOS / NOS (because they are both now invalid) and the new program instruction. If the NOS is 0 then just + -- retrieve the new TOS / NOS. + when Insn_Neqbranch | Insn_Eqbranch => + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + -- branches are almost always taken as they form loops + idimFlag <= '0'; + sp <= incIncSp; + + if (InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE)))) = Insn_Neqbranch and muxNOS.word /= 0) or (InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE)))) = Insn_Eqbranch and NOS.word = 0) then + pc <= pc + muxTOS.word(ADDR_BIT_RANGE); + else + pc <= incPC; + end if; + + -- need to fetch stack again. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + + -- Set in motion a signed multiplication of the TOS * NOS. + when Insn_Mult => + if IMPL_MULT = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(tMultResult); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= std_logic_vector(to_unsigned(InsnType'POS(InsnType'VAL(to_integer(unsigned(cacheL1(to_integer(pc))(DECODED_RANGE))))) , 6)); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= tMultResult(wordSize-1 downto 0); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + --state <= State_Execute; + end if; + end if; + + -- Set in motion a signed division of the TOS / NOS. + when Insn_Div => + if IMPL_DIV = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + divStart <= '1'; + divQuotientFractional <= 0; + state <= State_Div2; + end if; + end if; + + -- Set in motion a fixed point addition of the TOS / NOS. + when Insn_FiAdd32 => + if IMPL_FIADD32 = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_FiAdd2; + end if; + end if; + + -- Set in motion a fixed point division of the TOS / NOS. + when Insn_FiDiv32 => + if IMPL_FIDIV32 = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_FiDiv2; + end if; + end if; + + -- Set in motion a fixed point multiplication of the TOS / NOS. + when Insn_FiMult32 => + if IMPL_FIMULT32 = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + state <= State_FiMult2; + end if; + end if; + + -- Read the aligned word pointed to by the TOS and then process in the next state to extract just the required byte. + when Insn_Loadb => + if IMPL_LOADB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READBYTETOTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Read the aligned dword pointed to by the TOS and update just the one required byte, + -- The loadb and storeb can be sped up by implementing hardware byte read/write. + when Insn_Storeb => + if IMPL_STOREB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incIncSp; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)+1).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_WRITEBYTETOADDR; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + end if; + + -- Read the aligned dword pointed to by the TOS and then process in the next state to extract just the required word. + when Insn_Loadh => + if IMPL_LOADH = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READWORDTOTOS; + TOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Read the aligned dword pointed to by the TOS and update just the one required word, + -- The loadb and storeb can be sped up by implementing hardware byte read/write. + when Insn_Storeh => + if IMPL_STOREB = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incIncSp; + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READTOSNOS; + TOS.valid <= '0'; + NOS.valid <= '0'; + + mxFifo(to_integer(mxFifoWriteIdx)+1).addr(ADDR_BIT_RANGE) <= std_logic_vector(muxTOS.word(ADDR_BIT_RANGE)); + mxFifo(to_integer(mxFifoWriteIdx)+1).data <= std_logic_vector(muxNOS.word); + mxFifo(to_integer(mxFifoWriteIdx)+1).cmd <= MX_CMD_WRITEHWORDTOADDR; + mxFifoWriteIdx <= mxFifoWriteIdx + 2; + end if; + end if; + + -- Perform an exclusive or of the TOS and NOS which is stored in TOS in the next state. NOS is read from the + -- new location. + when Insn_Xor => + if IMPL_XOR = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= muxNOS.word xor muxTOS.word; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform a negation or inverse of the TOS. + when Insn_Neg => + if IMPL_NEG = true then + if muxTOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + TOS.word <= (not muxTOS.word) + 1; + end if; + end if; + + -- Perform a signed comparison of TOS v NOS, if they are not equal, set the result to 1 which is stored in TOS in the next state. NOS + -- is read from the new memory location. + when Insn_Neq => + if IMPL_NEQ = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + TOS.word <= (others => '0'); + if (signed(muxTOS.word) /= signed(muxNOS.word)) then + TOS.word(0) <= '1'; + end if; + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE)<= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + end if; + end if; + + -- Perform a modulo of TOS v NOS and push to stack. TOS is set to the result and NOS is read from the new stack location. + when Insn_Mod => + if IMPL_MOD = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + divStart <= '1'; + divQuotientFractional <= 0; + state <= State_Mod2; + end if; + end if; + + -- Shift NOS left or right TOS times according to the instruction. The shifting is done by VHDL operators paying attention to + -- shift left arithmetic where the sla operator doesnt give the normal results. + when Insn_Alshift => + if IMPL_ASHIFTLEFT = true or IMPL_ASHIFTRIGHT = true or IMPL_LSHIFTRIGHT = true then + if muxTOS.valid = '1' and muxNOS.valid = '1' then + tInsnExec := '1'; + idimFlag <= '0'; + pc <= incPC; + sp <= incSp; + + -- Positions to shift stored in TOS. + tShiftCnt := to_integer(unsigned(std_logic_vector(muxTOS.word(4 downto 0)))); + + -- Logical Shift Right + if (muxNOS.word(31) and cacheL1(to_integer(pc))(OPCODE_RANGE)(2)) = '0' and cacheL1(to_integer(pc))(OPCODE_RANGE)(0) = '0' then + if (tShiftCnt = 0) then + TOS.word <= (others => '0'); + else + TOS.word <= unsigned(to_stdlogicvector(to_bitvector(std_logic_vector(muxNOS.word)) srl tShiftCnt)); + end if; + end if; + + -- Arithmetic Shift Right + if (muxNOS.word(31) and cacheL1(to_integer(pc))(OPCODE_RANGE)(2)) = '1' and cacheL1(to_integer(pc))(OPCODE_RANGE)(0) = '0' then + if (tShiftCnt = 0) then -- ASR #32 + TOS.word <= (others => std_logic(muxNOS.word(31))); + else + TOS.word <= unsigned(to_stdlogicvector(to_bitvector(std_logic_vector(muxNOS.word)) sra tShiftCnt)); + end if; + end if; + + -- Arithmetic Shift Left (NB. VHDL sla behaves in a non-standard way, it mirrors sra hence use of sll). + if (muxNOS.word(31) and cacheL1(to_integer(pc))(OPCODE_RANGE)(2)) = '0' and cacheL1(to_integer(pc))(OPCODE_RANGE)(0) = '1' then + if (tShiftCnt = 0) then + TOS.word <= muxNOS.word; + else + TOS.word <= unsigned(to_stdlogicvector(to_bitvector(std_logic_vector(muxNOS.word)) sll tShiftCnt)); + end if; + end if; + + -- Fetch new NOS value. + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incIncSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + -- The ZPU has an 8 bit instruction set which has few spare slots. This intruction allows extended multibyte additions to be coded and processed. + -- The instructions are coded as: Extend,,[,,,] + -- Where ParamSize = 00 - No parameter bytes + -- 01 - 8 bit parameter + -- 10 - 16 bit parameter + -- 11 - 32 bit parameter + -- Thus without any additional data fetches, new instructions have access to 3 parameters, TOS, NOS and the InsnParameter. + -- ie. To create an LDIR, Source=TOS, Dest=NOS and InsnParameter=Count + when Insn_Extend => + -- Ensure L1 cache has sufficient data to process this instruction, otherwise wait until it does before decoding and executing. + if cacheL1FetchIdx - pc > to_integer(unsigned(cacheL1(to_integer(pc)+1)(OPCODE_RANGE)(OPCODE_PARAM_RANGE)))+1 then + tInsnExec := '1'; + + -- For instructions which use a parameter, build the value ready for use. + -- TODO: This should be variables to meet the 1 cycle requirement or set during decode. + case cacheL1(to_integer(pc)+1)(OPCODE_PARAM_RANGE) is + when "00" => insnExParameter <= X"00000000"; + when "01" => insnExParameter <= X"000000" & unsigned(cacheL1(to_integer(pc)+2)(OPCODE_RANGE)); + when "10" => insnExParameter <= X"0000" & unsigned(cacheL1(to_integer(pc)+2)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+3)(OPCODE_RANGE)); + when "11" => insnExParameter <= unsigned(cacheL1(to_integer(pc)+2)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+3)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+4)(OPCODE_RANGE)) & unsigned(cacheL1(to_integer(pc)+5)(OPCODE_RANGE)); + end case; + + -- Decode the extended instruction at this point as we have access to 8 future instructions or bytes so can work out what is required and execute. + -- 1:0 = 00 means an instruction which operates with a default, byte, half-word or word parameter. ie. Extend,,[,,,] + + -- Memory fill instruction. Fill memory starting at address in NOS with zero, 8 bit, 16 or 32 bit repeating value for TOS bytes. + --if cacheL1(to_integer(pc)+1)(OPCODE_INSN_RANGE) = Opcode_Ex_Fill then + --end if; + + -- Debug code, if enabled, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(5, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"455854454E440000"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end if; + + -- Breakpoint, this is not a nornal instruction and used by debuggers to suspend a program exection. At the moment + -- this instuction sets the BREAK flag and just continues. + when Insn_Break => + tInsnExec := '1'; + report "Break instruction encountered" severity failure; + inBreak <= '1'; + + -- Debug code, if ENABLEd, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"425245414B504E54"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + + -- Dump out the L1, L2 and Memory for debugging. + debugState <= Debug_Start; + end if; + + -- Should never get here, so if debugging enabled, report. + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + inBreak <= '1'; + + -- Debug code, if ENABLEd, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(6, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"494C4C4547414C00"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end case; + + -- During waits, if debug enabled, output state and dump the L1 cache. + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 and (pc = X"1f00010") then + if debugState = Debug_Idle then + debugState <= Debug_DumpL2; + end if; + end if; + + -- Debug code, if enabled, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 and tInsnExec = '1' then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1InsnAfterPC), 16)); + debugRec.DATA2(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 24)) & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 24)) & "10000000" & '0' & cacheL2IncAddr & idimFlag & tInsnExec & cacheL2Full & cacheL2Active & cacheL2Empty & cacheL2Write; + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + else + if DEBUG_CPU = true and debugOutputOnce = '0' then + -- During waits, if debug enabled, output state and dump the L1 cache. + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 and (pc = X"1002b67") then + if debugState = Debug_Idle then + debugState <= Debug_DumpL2; + end if; + end if; + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1InsnAfterPC), 16)); + debugRec.DATA2(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 24)) & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 24)) & "00000000" & '0' & cacheL2IncAddr & idimFlag & tInsnExec & cacheL2Full & cacheL2Active & cacheL2Empty & cacheL2Write; + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + debugOutputOnce <= '1'; + end if; + end if; + + -------------------------------------------------------------------------------------------------------------- + -- End of Instruction Execution Case block. + -------------------------------------------------------------------------------------------------------------- + + when State_Div2 => + if IMPL_DIV = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + + if divStart = '0' and divComplete = '1' then + TOS.word <= unsigned(divResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_Mod2 => + if IMPL_MOD = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divRemainder); + debugLoad <= '1'; + end if; + + if divStart = '0' and divComplete = '1' then + TOS.word <= unsigned(divRemainder(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_FiAdd2 => + if IMPL_FIADD32 = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + if divComplete = '1' and muxTOS.valid = '1' and muxNOS.valid = '1' then + TOS.word <= unsigned(fpAddResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_FiDiv2 => + if IMPL_FIDIV32 = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + if divComplete = '1' and muxTOS.valid = '1' and muxNOS.valid = '1' then + TOS.word <= unsigned(divResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + when State_FiMult2 => + if IMPL_FIMULT32 = true then + if DEBUG_CPU = true and DEBUG_LEVEL >= 5 then + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= "00" & std_logic_vector(divisorCopy(61 downto 0)); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= dividendCopy(31 downto 0); + debugRec.STACK_NOS <= std_logic_vector(divResult); + debugLoad <= '1'; + end if; + if divComplete = '1' and muxTOS.valid = '1' and muxNOS.valid = '1' then + TOS.word <= unsigned(fpMultResult(31 downto 0)); + + mxFifo(to_integer(mxFifoWriteIdx)).addr(ADDR_32BIT_RANGE) <= std_logic_vector(incSp); + mxFifo(to_integer(mxFifoWriteIdx)).cmd <= MX_CMD_READNOS; + NOS.valid <= '0'; + mxFifoWriteIdx <= mxFifoWriteIdx + 1; + state <= State_Execute; + end if; + end if; + + -- Should never reach this state, if debug enabled, output details. + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + inBreak <= '1'; + + -- Debug code, if ENABLEd, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 0 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA <= X"494C4C4547414C53"; + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + end if; + end case; + -------------------------------------------------------------------------------------------------------------- + -- End of Instruction State Case block. + -------------------------------------------------------------------------------------------------------------- + + -- In debug mode, output the current data and the decoded instruction queue. + if DEBUG_CPU = true then + case debugState is + when Debug_Idle => + + when Debug_Start => + + -- Write out the primary data. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "11"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(pc), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL1StartAddr), 16)); + debugRec.DATA2(63 downto 0) <= std_logic_vector(to_unsigned(to_integer(cacheL2FetchIdx), 16)) & std_logic_vector(to_unsigned(to_integer(cacheL2StartAddr), 16)) & std_logic_vector(cacheL2FetchIdx(15 downto 0)) & "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & "0000" & idimFlag & tInsnExec & cacheL2Full & cacheL2Write; + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(pc))(DECODED_RANGE) & cacheL1(to_integer(pc))(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+1)(DECODED_RANGE) & cacheL1(to_integer(pc)+1)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+2)(DECODED_RANGE) & cacheL1(to_integer(pc)+2)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+3)(DECODED_RANGE) & cacheL1(to_integer(pc)+3)(OPCODE_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(pc)+4)(DECODED_RANGE) & cacheL1(to_integer(pc)+4)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+5)(DECODED_RANGE) & cacheL1(to_integer(pc)+5)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+6)(DECODED_RANGE) & cacheL1(to_integer(pc)+6)(OPCODE_RANGE) & "00" & cacheL1(to_integer(pc)+7)(DECODED_RANGE) & cacheL1(to_integer(pc)+7)(OPCODE_RANGE); + debugRec.OPCODE <= cacheL1(to_integer(pc))(OPCODE_RANGE); + debugRec.DECODED_OPCODE <= cacheL1(to_integer(pc))(DECODED_RANGE); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(muxTOS.word); + debugRec.STACK_NOS <= std_logic_vector(muxNOS.word); + debugLoad <= '1'; + debugAllInfo <= '1'; + + debugState <= Debug_DumpL1; + + when Debug_DumpL1 => + debugPC <= (others => '0'); + debugState <= Debug_DumpL1_1; + + when Debug_DumpL1_1 => + -- Write out the opcode. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_SPLIT_DATA <= "01"; + if debugPC = MAX_L1CACHE_SIZE-(wordBytes*4) then + debugRec.FMT_POST_CRLF <= '1'; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(7, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '1'; + debugRec.WRITE_DATA3 <= '1'; + debugRec.WRITE_DATA4 <= '1'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '0'; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.DATA(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+ 0)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 1)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 2)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 3)(INSN_RANGE); + debugRec.DATA2(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+ 4)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 5)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 6)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 7)(INSN_RANGE); + debugRec.DATA3(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+ 8)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+ 9)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+10)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+11)(INSN_RANGE); + debugRec.DATA4(63 downto 0) <= "00" & cacheL1(to_integer(debugPC)+12)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+13)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+14)(INSN_RANGE) & "00" & cacheL1(to_integer(debugPC)+15)(INSN_RANGE); + if debugPC = 0 then + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(to_unsigned(to_integer(pc), debugRec.PC'LENGTH)); + debugRec.WRITE_PC <= '1'; + else + debugRec.WRITE_PC <= '0'; + end if; + debugLoad <= '1'; + debugState <= Debug_DumpL1_2; + debugPC <= debugPC + (wordBytes * 4); -- 16 instructions are output per loop. + + when Debug_DumpL1_2 => + -- Move onto next opcode in Fifo. + if debugPC = MAX_L1CACHE_SIZE then + if debugAllInfo = '1' then + -- if IMPL_USE_INSN_BUS = true then + -- debugState <= Debug_End; + -- else + debugState <= Debug_DumpL2; + -- end if; + else + debugState <= Debug_End; + end if; + else + debugState <= Debug_DumpL1_1; + end if; + + when Debug_DumpL2 => + debugPC <= (others => '0'); + debugState <= Debug_DumpL2_1; + + -- Output the contents of L2 in the format + when Debug_DumpL2_1 => + -- Write out the opcode. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_SPLIT_DATA <= "01"; + if debugPC = MAX_L2CACHE_SIZE-1 or debugPC(4 downto 2) = "111" then + debugRec.FMT_POST_CRLF <= '1'; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(3, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + if debugPC(4 downto 2) = "000" then + debugRec.WRITE_PC <= '1'; + else + debugRec.WRITE_PC <= '0'; + end if; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(debugPC); + debugRec.DATA(63 downto 32) <= cacheL2Word(31 downto 24) & cacheL2Word(23 downto 16) & cacheL2Word(15 downto 8) & cacheL2Word(7 downto 0); + debugLoad <= '1'; + debugState <= Debug_DumpL2_2; + debugPC <= debugPC + wordBytes; -- 4 instructions are output per loop (limited by memory read into cacheL2Word). + + when Debug_DumpL2_2 => + -- Move onto next opcode in Fifo. + if debugPC = MAX_L2CACHE_SIZE then + if debugAllInfo = '1' then + debugState <= Debug_DumpMem; + else + debugState <= Debug_End; + end if; + else + debugState <= Debug_DumpL2_1; + end if; + + when Debug_DumpMem => + debugPC <= debugPC_StartAddr; + debugPC_WidthCounter <= 0; + debugState <= Debug_DumpMem_0; + + when Debug_DumpMem_0 => + if mxMemVal.valid = '0' then + debugState <= Debug_DumpMem_1; + end if; + + -- Output the contents of memory in the format + when Debug_DumpMem_1 => + if mxMemVal.valid = '1' then + debugPC_WidthCounter <= debugPC_WidthCounter+4; + + -- Write out the memory location. + debugRec.FMT_DATA_PRTMODE <= "01"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_SPLIT_DATA <= "01"; + if debugPC = debugPC_EndAddr or debugPC_WidthCounter = debugPC_Width-4 then + debugRec.FMT_POST_CRLF <= '1'; + debugPC_WidthCounter <= 0; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(3, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + if debugPC_WidthCounter = 0 then + debugRec.WRITE_PC <= '1'; + else + debugRec.WRITE_PC <= '0'; + end if; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(debugPC); + debugRec.DATA(63 downto 32) <= std_logic_vector(mxMemVal.word(31 downto 24)) & std_logic_vector(mxMemVal.word(23 downto 16)) & std_logic_vector(mxMemVal.word(15 downto 8)) & std_logic_vector(mxMemVal.word(7 downto 0)); + debugLoad <= '1'; + debugState <= Debug_DumpMem_2; + debugPC <= debugPC + wordBytes; + end if; + + when Debug_DumpMem_2 => + -- Move onto next opcode in Fifo. + if debugPC = debugPC_EndAddr then + debugState <= Debug_End; + else + debugState <= Debug_DumpMem_1; + end if; + + when Debug_End => + debugAllInfo <= '0'; + debugState <= Debug_Idle; + end case; + end if; + end if; + --------------------------------------------------------------------------------------------------------------------------------------------------- + end if; + end process; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Hardware divider - Fixed Point. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + DIVIDER : if IMPL_DIV = true or IMPL_FIDIV32 = true or IMPL_MOD = true generate + process(CLK, ZPURESET, divStart, dividendCopy) + begin + divRemainder <= unsigned(dividendCopy(31 downto 0)); + + if ZPURESET = '1' then + divComplete <= '1'; + divResult <= (others => '0'); + + elsif rising_edge(CLK) then + + if divComplete = '1' and divStart = '1' then + divComplete <= '0'; + bitCnt <= to_unsigned((32+divQuotientFractional)-2, bitCnt'LENGTH); + divResult <= (others => '0'); + + dividendCopy(30 downto 0) <= std_logic_vector(muxTOS.word(30 downto 0)); + dividendCopy(61 downto 31) <= (others => '0'); + + divisorCopy(61) <= '0'; + divisorCopy(60 downto 30) <= std_logic_vector(muxNOS.word(30 downto 0)); + divisorCopy(29 downto 0) <= (others => '0'); + + -- set sign bit + if((muxTOS.word(31) = '1' and muxNOS.word(31) = '0') or (muxTOS.word(31) = '0' and muxNOS.word(31) = '1')) then + divResult(31) <= '1'; + else + divResult(31) <= '0'; + end if; + + elsif divComplete = '0' and (DEBUG_CPU = false or (DEBUG_CPU = true and debugReady = '1')) then + -- 64bit compare of divisor/dividend. + if((unsigned(dividendCopy)) >= unsigned(divisorCopy)) then + --subtract, should only occur when the dividend is greater than the divisor. + dividendCopy <= std_logic_vector(to_unsigned(to_integer(unsigned(dividendCopy)) - to_integer(unsigned(divisorCopy)), dividendCopy'LENGTH)); + --set quotient + divResult(to_integer(bitCnt)) <= '1'; + end if; + + --reduce divisor + divisorCopy <= to_stdlogicvector(to_bitvector(divisorCopy) srl 1); + + --stop condition + if bitCnt = 0 then + divComplete <= '1'; + else + --reduce bit counter + bitCnt <= bitCnt - 1; + end if; + end if; + end if; + end process; + else generate + dividendCopy <= (others => DontCareValue); + end generate; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Hardware adder - Fixed Point. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + FIADD32: if IMPL_FIADD32 = true generate + process(muxTOS.word, muxNOS.word, ZPURESET) + begin + if ZPURESET = '1' then + fpAddResult <= (others => '0'); + else + -- both negative + if muxTOS.word(31) = '1' and muxNOS.word(31) = '1' then + -- sign + fpAddResult(31) <= '1'; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxTOS.word(30 downto 0)) + to_integer(muxNOS.word(30 downto 0)), 31)); + + --both positive + elsif muxTOS.word(31) = '0' and muxNOS.word(31) = '0' then + -- sign + fpAddResult(31) <= '0'; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxTOS.word(30 downto 0)) + to_integer(muxNOS.word(30 downto 0)), 31)); + + -- subtract TOS - NOS + elsif muxTOS.word(31) = '0' and muxNOS.word(31) = '1' then + -- sign + if muxTOS.word(30 downto 0) > muxNOS.word(30 downto 0) then + fpAddResult(31) <= '1'; + else + fpAddResult(31) <= '0'; + end if; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxTOS.word(30 downto 0)) - to_integer(muxNOS.word(30 downto 0)), 31)); + + -- subtract NOS - TOS + else + -- sign + if muxTOS.word(30 downto 0) < muxNOS.word(30 downto 0) then + fpAddResult(31) <= '1'; + else + fpAddResult(31) <= '0'; + end if; + -- whole + fpAddResult(30 downto 0) <= std_logic_vector(to_unsigned(to_integer(muxNOS.word(30 downto 0)) - to_integer(muxTOS.word(30 downto 0)), 31)); + end if; + end if; + end process; + else generate + fpAddResult <= (others => DontCareValue); + end generate; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Hardware multiplier - Fixed Point. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + FIMULT32: if IMPL_FIMULT32 = true generate + signal TOSflip : std_logic_vector(31 downto 0); + signal NOSflip : std_logic_vector(31 downto 0); + signal TOSmult : std_logic_vector(31 downto 0); + signal NOSmult : std_logic_vector(31 downto 0); + signal resultFlip : std_logic_vector(63 downto 0); + signal result : std_logic_vector(63 downto 0); + begin + process(muxTOS.word, TOSflip) + begin + for i in 0 to wordSize-1 loop + TOSflip(i) <= muxTOS.word(wordSize-1-i); + end loop; + TOSflip <= std_logic_vector(signed(TOSflip) + 1); + end process; + + process(muxNOS.word, NOSflip) + begin + for i in 0 to wordSize-1 loop + NOSflip(i) <= muxNOS.word(wordSize-1-i); + end loop; + NOSflip <= std_logic_vector(signed(NOSflip) + 1); + end process; + + process(result, quotientFractional, resultFlip) + begin + for i in quotientFractional to 30+quotientFractional loop + resultFlip(i) <= result(30+quotientFractional-i); + end loop; + resultFlip <= std_logic_vector(signed(resultFlip) + 1); + end process; + + process(muxTOS.word, muxNOS.word, TOSflip, NOSflip) + begin + if muxTOS.word(31) = '1' then + TOSmult <= TOSflip; + else + TOSmult <= std_logic_vector(muxTOS.word); + end if; + + if muxNOS.word(31) = '1' then + NOSmult <= NOSflip; + else + NOSmult <= std_logic_vector(muxNOS.word); + end if; + end process; + + process(TOSmult, NOSmult) + begin + result <= std_logic_vector(signed(TOSmult) * signed(NOSmult)); + end process; + + process(result, resultFlip, muxTOS.word, muxNOS.word, quotientFractional) + begin + -- sign + if (muxTOS.word(31) = '1' and muxNOS.word(31) = '0') or (muxTOS.word(31) = '0' and muxNOS.word(31) = '1') then + fpMultResult(31) <= '1'; + fpMultResult(30 downto 0) <= resultFlip(30 downto 0); + else + fpMultResult(31) <= '0'; + fpMultResult(30 downto 0) <= result(30+quotientFractional downto quotientFractional); + end if; + end process; + else generate + fpMultResult <= (others => DontCareValue); + quotientFractional <= 0; + end generate; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Debugger output processor. + -- This logic takes a debug record and expands it to human readable form then dispatches it to the debug serial port. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Add debug uart if required. Increasing the TX and DBG Fifo depth can help short term (ie. initial start of the CPU) + -- but once full, the debug run will eventually operate at the slowest denominator, ie. the TX speed and how quick it can + -- shift 10 bits. + DEBUG : if DEBUG_CPU = true generate + DEBUGUART: entity work.zpu_uart_debug + generic map ( + CLK_FREQ => CLK_FREQ -- Frequency of master clock. + ) + port map ( + -- CPU Interface + CLK => CLK, -- Master clock + RESET => ZPURESET, -- high active sync reset + DEBUG_DATA => debugRec, -- write data + CS => debugLoad, -- Chip Select. + READY => debugReady, -- Debug processor ready for next command. + + -- Serial data + TXD => DEBUG_TXD + ); + end generate; + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- End of debugger output processor. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + +end behave; diff --git a/zpu/cpu/zpu_core_evo_L2.vhd b/zpu/cpu/zpu_core_evo_L2.vhd new file mode 100644 index 0000000..1617797 --- /dev/null +++ b/zpu/cpu/zpu_core_evo_L2.vhd @@ -0,0 +1,226 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity evo_L2cache is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + + memBAddr : in std_logic_vector(addrbits-1 downto 2); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBRead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end evo_L2cache; + +architecture arch of evo_L2cache is + + -- Declare 4 byte wide arrays for byte level addressing. + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + -- Correctly assigning the Little Endian value to the correct array, byte writes the data is in '7 downto 0', h-word writes + -- the data is in '15 downto 0'. + -- + RAM0_DATA <= memAWrite(7 downto 0); + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 0 - Port B - bits 7 downto 0 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM0(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(7 downto 0); + memBRead(7 downto 0) <= memBWrite(7 downto 0); + else + memBRead(7 downto 0) <= RAM0(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 1 - Port B - bits 15 downto 8 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM1(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(15 downto 8); + memBRead(15 downto 8) <= memBWrite(15 downto 8); + else + memBRead(15 downto 8) <= RAM1(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 2 - Port B - bits 23 downto 16 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM2(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(23 downto 16); + memBRead(23 downto 16) <= memBWrite(23 downto 16); + else + memBRead(23 downto 16) <= RAM2(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 3 - Port B - bits 31 downto 24 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM3(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(31 downto 24); + memBRead(31 downto 24) <= memBWrite(31 downto 24); + else + memBRead(31 downto 24) <= RAM3(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + +end arch; diff --git a/zpu/cpu/zpu_core_flex.vhd b/zpu/cpu/zpu_core_flex.vhd new file mode 100644 index 0000000..cb810d0 --- /dev/null +++ b/zpu/cpu/zpu_core_flex.vhd @@ -0,0 +1,1184 @@ +-- ZPU (flex variant) +-- +-- Copyright 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com +-- +-- Changes by Alastair M. Robinson, 2013 +-- to allow the core to run from external RAM, and to balance performance and area. +-- The goal is to make the ZPU a useful support CPU for such tasks as loading +-- ROMs from SD Card, while keeping the area under 1,000 logic cells. +-- To this end, there are a number of generics which can be used to adjust the +-- speed / area balance. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + + +-- WARNING - the stack bit has changed from bit 26 to bit 30. +-- RTL code which relies upon this will need updating. +-- Provided the linkscripts and CPU are kept in sync, +-- this change should be essentially invisible to the user. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_pkg.all; + +entity zpu_core_flex is + generic ( + IMPL_MULTIPLY : boolean; -- Self explanatory + IMPL_COMPARISON_SUB : boolean; -- Include sub and (U)lessthan(orequal) + IMPL_EQBRANCH : boolean; -- Include eqbranch and neqbranch + IMPL_STOREBH : boolean; -- Include halfword and byte writes + IMPL_LOADBH : boolean; -- Include halfword and byte reads + IMPL_CALL : boolean; -- Include call + IMPL_SHIFT : boolean; -- Include lshiftright, ashiftright and ashiftleft + IMPL_XOR : boolean; -- include xor instruction + -- REMAP_STACK : boolean; -- Map the stack / Boot ROM to an address specific by "stackbit" - default 0x40000000 + CACHE : boolean; -- Cache - only 32-bits but reduces re-fetching and speeds up consecutive IMs in particular. +-- stackbit : integer -- Specify base address of stack - defaults to 0x40000000 + CLK_FREQ : integer := 100000000; -- Frequency of the input clock. + STACK_ADDR : integer := 0 -- Initial stack address on CPU start. + ); + port ( + clk : in std_logic; + -- asynchronous reset signal + reset : in std_logic; + -- this particular implementation of the ZPU does not + -- have a clocked enable signal + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(WORD_32BIT_RANGE); + mem_write : out std_logic_vector(WORD_32BIT_RANGE); + out_mem_addr : out std_logic_vector(ADDR_BIT_RANGE); + out_mem_writeEnable : out std_logic; + out_mem_bEnable : out std_logic; -- Enable byte write + out_mem_hEnable : out std_logic; -- Enable halfword write + out_mem_readEnable : out std_logic; + -- Set to one to jump to interrupt vector + -- The ZPU will communicate with the hardware that caused the + -- interrupt via memory mapped IO or the interrupt flag can + -- be cleared automatically + interrupt_request : in std_logic; + interrupt_ack : out std_logic; -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + interrupt_done : out std_logic; -- Interrupt service routine completed/done. + -- Signal that the break instruction is executed, normally only used + -- in simulation to stop simulation + break : out std_logic; + debug_txd : out std_logic; -- Debug serial output. + -- + MEM_A_WRITE_ENABLE : out std_logic; + MEM_A_ADDR : out std_logic_vector(ADDR_32BIT_RANGE); + MEM_A_WRITE : out std_logic_vector(WORD_32BIT_RANGE); + MEM_B_WRITE_ENABLE : out std_logic; + MEM_B_ADDR : out std_logic_vector(ADDR_32BIT_RANGE); + MEM_B_WRITE : out std_logic_vector(WORD_32BIT_RANGE); + MEM_A_READ : in std_logic_vector(WORD_32BIT_RANGE); + MEM_B_READ : in std_logic_vector(WORD_32BIT_RANGE) + ); + end zpu_core_flex; + + architecture behave of zpu_core_flex is + + -- state machine. + type State_Type is ( + State_Fetch, + State_WriteIODone, + State_Execute, + State_StoreToStack, + State_Add, + State_Or, + State_And, + State_Xor, + State_Store, + State_ReadIO, + State_ReadIOBH, + State_WriteIO, + State_WriteIOBH, + State_Load, + State_FetchNext, + State_AddSP, + State_AddSP2, + State_ReadIODone, + State_StoreAndDecode, + State_Decode, + State_Resync, + State_Interrupt, + State_Mult, + State_Comparison, + State_EqNeq, + State_Sub, + State_IncSP, + State_Shift, + State_Debug + ); + + type DecodedOpcodeType is ( + Decoded_Nop, + Decoded_Im, + Decoded_ImShift, + Decoded_LoadSP, + Decoded_StoreSP , + Decoded_AddSP, + Decoded_Emulate, + Decoded_Break, + Decoded_PushSP, + Decoded_PopPC, + Decoded_Add, + Decoded_Or, + Decoded_And, + Decoded_Load, + Decoded_LoadBH, + Decoded_Not, + Decoded_Xor, + Decoded_Flip, + Decoded_Store, + Decoded_StoreBH, + Decoded_PopSP, + Decoded_Interrupt, + Decoded_Mult, + Decoded_Sub, + Decoded_Comparison, + Decoded_EqNeq, + Decoded_EqBranch, + Decoded_Call, + Decoded_Shift + ); + + -- + type DebugType is + ( + Debug_Start, + Debug_DumpFifo, + Debug_DumpFifo_1, + Debug_End + ); + + -- start byte address of stack. + -- point to top of RAM - 2*words + --constant spStart : unsigned(spStart(ADDR_32BIT_RANGE)); + --std_logic_vector(ADDR_BIT_RANGE) := std_logic_vector(to_unsigned((2**(maxAddrBitBRAM+1))-8, maxAddrBit)); + + signal memAWriteEnable : std_logic; + signal memAAddr : unsigned(ADDR_32BIT_RANGE); + signal memAWrite : unsigned(WORD_32BIT_RANGE); + signal memARead : unsigned(WORD_32BIT_RANGE); + signal memBWriteEnable : std_logic; + signal memBAddr : unsigned(ADDR_32BIT_RANGE); + signal memBWrite : unsigned(WORD_32BIT_RANGE); + signal memBRead : unsigned(WORD_32BIT_RANGE); + + signal pc : unsigned(ADDR_BIT_RANGE); -- Synthesis tools should reduce this automatically + signal sp : unsigned(ADDR_32BIT_RANGE); + signal interrupt_suspended_addr : unsigned(ADDR_BIT_RANGE); -- Save address which got interrupted. + + + -- this signal is set upon executing an IM instruction + -- the subsequence IM instruction will then behave differently. + -- all other instructions will clear the idim_flag. + -- this yields highly compact immediate instructions. + signal idim_flag : std_logic; + -- + signal busy : std_logic; + -- + signal begin_inst : std_logic; + signal fetchneeded : std_logic; + + signal trace_opcode : std_logic_vector(7 downto 0); + signal trace_pc : std_logic_vector(ADDR_BIT_RANGE); + signal trace_sp : std_logic_vector(ADDR_32BIT_RANGE); + signal trace_topOfStack : std_logic_vector(WORD_32BIT_RANGE); + signal trace_topOfStackB : std_logic_vector(WORD_32BIT_RANGE); + signal debugState : DebugType; + signal debugCnt : integer; + signal debugRec : zpu_dbg_t; + signal debugLoad : std_logic; + signal debugReady : std_logic; + + signal programword : std_logic_vector(WORD_32BIT_RANGE); + signal cachedprogramword : std_logic_vector(WORD_32BIT_RANGE); + signal inrom : std_logic; + signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); + signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + signal opcode_saved : std_logic_vector(OpCode_Size-1 downto 0); + -- + signal decodedOpcode : DecodedOpcodeType; + signal sampledDecodedOpcode : DecodedOpcodeType; + + signal state : State_Type; + -- + subtype index is std_logic_vector(2 downto 0); + -- + signal tOpcode_sel : index; + -- + signal inInterrupt : std_logic; + + signal comparison_sub_result : unsigned(wordSize downto 0); -- Extra bit needed for signed comparisons + signal comparison_sign_mod : std_logic; + signal comparison_eq : std_logic; + + signal eqbranch_zero : std_logic; + + signal shift_done : std_logic; + signal shift_sign : std_logic; + signal shift_count : unsigned(5 downto 0); + signal shift_reg : unsigned(31 downto 0); + signal shift_direction : std_logic; + + signal add_low : unsigned(17 downto 0); + + begin + + -- Wire up the BRAM (RAM/ROM) + MEM_A_ADDR <= std_logic_vector(memAAddr(ADDR_32BIT_RANGE)); + MEM_A_WRITE <= std_logic_vector(memAWrite); + MEM_B_ADDR <= std_logic_vector(memBAddr(ADDR_32BIT_RANGE)); + MEM_B_WRITE <= std_logic_vector(memBWrite); + memARead <= unsigned(MEM_A_READ); + memBRead <= unsigned(MEM_B_READ); + MEM_A_WRITE_ENABLE <= memAWriteEnable; + MEM_B_WRITE_ENABLE <= memBWriteEnable; + + tOpcode_sel(2) <= '1' when CACHE=true and fetchneeded='0' else '0'; + tOpcode_sel(1 downto 0) <= std_logic_vector(pc(minAddrBit-1 downto 0)); + + programword <= MEM_B_READ; + inrom <='1'; + + -- move out calculation of the opcode to a separate process + -- to make things a bit easier to read + decodeControl : process(programword, cachedprogramword, comparison_sub_result, pc, tOpcode_sel) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + + -- simplify opcode selection a bit so it passes more synthesizers + case (tOpcode_sel) is + when "000" => tOpcode := std_logic_vector(programword(31 downto 24)); + + when "001" => tOpcode := std_logic_vector(programword(23 downto 16)); + + when "010" => tOpcode := std_logic_vector(programword(15 downto 8)); + + when "011" => tOpcode := std_logic_vector(programword(7 downto 0)); + + when "100" => tOpcode := std_logic_vector(cachedprogramword(31 downto 24)); + + when "101" => tOpcode := std_logic_vector(cachedprogramword(23 downto 16)); + + when "110" => tOpcode := std_logic_vector(cachedprogramword(15 downto 8)); + + when "111" => tOpcode := std_logic_vector(cachedprogramword(7 downto 0)); + + when others => tOpcode := std_logic_vector(programword(7 downto 0)); + end case; + + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7) = OpCode_Im) then + sampledDecodedOpcode <= Decoded_Im; + elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then + sampledDecodedOpcode <= Decoded_StoreSP; + elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then + sampledDecodedOpcode <= Decoded_LoadSP; + elsif (tOpcode(7 downto 5) = OpCode_Emulate) then + sampledDecodedOpcode <= Decoded_Emulate; + if IMPL_CALL=true and tOpcode(5 downto 0) = OpCode_Call then + sampledDecodedOpcode <= Decoded_Call; + end if; + if IMPL_MULTIPLY=true and tOpcode(5 downto 0) = OpCode_Mult then + sampledDecodedOpcode <= Decoded_Mult; + end if; + if IMPL_XOR=true and tOpcode(5 downto 0) = OpCode_Xor then + sampledDecodedOpcode <= Decoded_Xor; + end if; + if IMPL_COMPARISON_SUB=true then + if tOpcode(5 downto 0) = OpCode_Eq or tOpcode(5 downto 0) = OpCode_Neq then + sampledDecodedOpcode <= Decoded_EqNeq; + elsif tOpcode(5 downto 0)= OpCode_Sub then + sampledDecodedOpcode <= Decoded_Sub; + elsif tOpcode(5 downto 0)= OpCode_Lessthanorequal or tOpcode(5 downto 0)= OpCode_Lessthan + or tOpcode(5 downto 0) = OpCode_Ulessthanorequal or tOpcode(5 downto 0)= OpCode_Ulessthan then + sampledDecodedOpcode <= Decoded_Comparison; + end if; + end if; + if IMPL_EQBRANCH=true then + if tOpcode(5 downto 0) = OpCode_EqBranch or tOpcode(5 downto 0)= OpCode_NeqBranch then + sampledDecodedOpcode <= Decoded_EqBranch; + end if; + end if; + if IMPL_STOREBH=true then + if tOpcode(5 downto 0) = OpCode_StoreB or tOpcode(5 downto 0) = OpCode_StoreH then + sampledDecodedOpcode <= Decoded_StoreBH; + end if; + end if; + -- LOADB and LOADH don't do any bitshifting based on address- it's the supporting + -- SOC's responsibility to make sure the result is in the low order bits. + if IMPL_LOADBH=true then + if tOpcode(5 downto 0) = OpCode_LoadB or tOpcode(5 downto 0) = OpCode_LoadH then + -- if tOpcode(5 downto 0) = OpCode_LoadH then -- Disable LoadB for now, since it doesn't yet work. + sampledDecodedOpcode <= Decoded_LoadBH; + end if; + end if; + if IMPL_SHIFT=true then + if tOpcode(5 downto 0) = OpCode_Lshiftright or tOpcode(5 downto 0) = OpCode_Ashiftright or tOpcode(5 downto 0) = OpCode_Ashiftleft then + sampledDecodedOpcode <= Decoded_Shift; + end if; + end if; + elsif (tOpcode(7 downto 4) = OpCode_AddSP) then + sampledDecodedOpcode <= Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode <= Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode <= Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode <= Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode <= Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode <= Decoded_Or; + when OpCode_And => + sampledDecodedOpcode <= Decoded_And; + when OpCode_Load => + sampledDecodedOpcode <= Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode <= Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode <= Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode <= Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode <= Decoded_PopSP; + when others => + sampledDecodedOpcode <= Decoded_Nop; + end case; -- tOpcode(3 downto 0) + end if; -- tOpcode + end process; + + + opcodeControl: process(clk, reset, comparison_sub_result, shift_count, memBRead) + variable spOffset : unsigned(4 downto 0); + variable tMultResult : unsigned(wordSize*2-1 downto 0); + begin + + if IMPL_COMPARISON_SUB=true and comparison_sub_result='0'&X"00000000" then + comparison_eq <= '1'; + else + comparison_eq <= '0'; + end if; + + if IMPL_SHIFT=true and shift_count="000000" then + shift_done <= '1'; + else + shift_done <= '0'; + end if; + + -- Needs to happen outside the clock edge + eqbranch_zero<='0'; + if IMPL_EQBRANCH=true and memBRead=X"00000000" then + eqbranch_zero <= '1'; + end if; + + if reset = '1' then + state <= State_Resync; + break <= '0'; + sp <= to_unsigned(STACK_ADDR, maxAddrBit)(ADDR_32BIT_RANGE); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + out_mem_bEnable <= '0'; + out_mem_hEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + inInterrupt <= '0'; + fetchneeded <= '1'; + interrupt_ack <= '0'; + interrupt_done <= '0'; + if DEBUG_CPU = true then + debugRec <= ZPU_DBG_T_INIT; + debugCnt <= 0; + debugLoad <= '0'; + end if; + + elsif (clk'event and clk = '1') then + + if DEBUG_CPU = true then + debugLoad <= '0'; + end if; + + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + + -- If the cpu can run, continue with next state. + -- + if DEBUG_CPU = false or (DEBUG_CPU = true and debugReady = '1') then + + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); + --out_mem_addr <= (others => DontCareValue); + --mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + + -- We want memAAddr to remain stable since the length of the fetch depends on external RAM. + --memAAddr <= (others => DontCareValue); + --memBAddr(ADDR_32BIT_RANGE) <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + --out_mem_bEnable <= '0'; + --out_mem_hEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + --out_mem_addr <= std_logic_vector(memARead(ADDR_BIT_RANGE)); + --mem_write <= std_logic_vector(memBRead); + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + + -- If interrupt is active, we only clear the interrupt state once the PC is reset to the address which was suspended after the + -- interrupt, this prevents recursive interrupt triggers, desirable in cetain circumstances but not for this current design. + -- + interrupt_ack <= '0'; -- Reset interrupt acknowledge if set, width is 1 clock only. + interrupt_done <= '0'; -- Reset interrupt done if set, width is 1 clock only. + if inInterrupt = '1' and pc(ADDR_BIT_RANGE) = interrupt_suspended_addr(ADDR_BIT_RANGE) then + inInterrupt <= '0'; -- no longer in an interrupt + interrupt_done <= '1'; -- Interrupt service routine complete. + end if; + + -- Handle shift instructions + IF IMPL_SHIFT=true then + if shift_done='0' then + if shift_direction='1' then + shift_reg <= shift_reg(30 downto 0)&"0"; -- Shift left + else + shift_reg <= shift_sign&shift_reg(31 downto 1); -- Shift right + end if; + shift_count <= shift_count-1; + end if; + end if; + + -- Pipelining of addition + add_low <= ("00"&memARead(15 downto 0)) + ("00"&memBRead(15 downto 0)); + + if IMPL_MULTIPLY=true then + tMultResult := memARead * memBRead; + end if; + + if IMPL_COMPARISON_SUB=true then + comparison_sub_result <= unsigned('0'&memBRead)-unsigned('0'&memARead); + comparison_sign_mod <= memARead(wordSize-1) xor memBRead(wordSize-1); + end if; + + case state is + + when State_Execute => + opcode_saved <= opcode; + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + fetchneeded <= '1'; + state <= State_Fetch; + if CACHE = true or inrom = '0' then + if pc(1 downto 0) /= "11" then -- We fetch four bytes at a time. + fetchneeded <= '0'; + state <= State_Decode; + end if; + end if; + + -- during the next cycle we'll be reading the next opcode + spOffset(4) := not opcode(4); + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + + -- Debug code, if enabled, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '0'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= (others => '0'); + debugRec.DATA2(63 downto 0) <= (others => '0'); + debugRec.DATA3(63 downto 0) <= (others => '0'); + debugRec.DATA4(63 downto 0) <= (others => '0'); + debugRec.OPCODE <= opcode; + debugRec.DECODED_OPCODE <= std_logic_vector(to_unsigned(DecodedOpcodeType'POS(decodedOpcode), 6)); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(memARead); + debugRec.STACK_NOS <= std_logic_vector(memBRead); + debugLoad <= '1'; + end if; + + idim_flag <= '0'; + + case decodedOpcode is + + when Decoded_Interrupt => + interrupt_ack <= '1'; -- Acknowledge interrupt. + interrupt_suspended_addr <= pc(ADDR_BIT_RANGE); -- Save address which got interrupted. + sp <= sp - 1; + memAAddr <= sp - 1; + memAWriteEnable <= '1'; + memAWrite <= (others => DontCareValue); + memAWrite(ADDR_BIT_RANGE) <= pc; + + pc <= (others => '0'); + pc(5 downto 0) <= to_unsigned(32, 6); -- interrupt address + fetchneeded <= '1'; -- Need to set this any time PC changes. + state <= State_Fetch; + report "ZPU jumped to interrupt!" severity note; + + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag = '0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + memBAddr <= sp; + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + memBAddr <= sp+1; + end if; -- idim_flag + + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + state <= State_Fetch; + + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(ADDR_BIT_RANGE) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(4 downto 0)); + fetchneeded <= '1'; -- Need to set this any time pc changes. + state <= State_Fetch; + + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + state <= State_Fetch; + + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memBAddr <= sp; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(ADDR_32BIT_RANGE) <= sp; + + when Decoded_PopPC => + pc <= memARead(ADDR_BIT_RANGE); + fetchneeded <= '1'; -- Need to set this any time PC changes. + sp <= sp + 1; + memAAddr <= sp+1; + memBAddr <= sp+2; + state <= State_Fetch; + + when Decoded_EqBranch => + if IMPL_EQBRANCH=true then + sp <= sp + 1; + if (eqbranch_zero xor opcode(0))='0' then -- eqbranch is 55, neqbranch is 56 + pc <= pc + memARead(ADDR_BIT_RANGE); + fetchneeded <= '1'; -- Need to set this any time PC changes. + end if; + state <= State_IncSP; + end if; + + when Decoded_Comparison => + if IMPL_COMPARISON_SUB=true then + sp <= sp + 1; + state <= State_Comparison; + end if; + + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + + when Decoded_Sub => + if IMPL_COMPARISON_SUB=true then + sp <= sp + 1; + state <= State_Sub; + end if; + + when Decoded_Or => + memAAddr <= sp+1; + memBAddr <= sp+2; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + sp <= sp + 1; + + when Decoded_And => + memAAddr <= sp+1; + memBAddr <= sp+2; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + sp <= sp + 1; + + when Decoded_Xor => + memAAddr <= sp+1; + memBAddr <= sp+2; + memAWriteEnable <= '1'; + memAWrite <= memARead xor memBRead; + sp <= sp + 1; + + when Decoded_Mult => + sp <= sp + 1; + state <= State_Mult; + + when Decoded_Load => + if (memARead(ioBit) = '1') then + out_mem_addr(1 downto 0) <= "00"; + out_mem_addr(ADDR_32BIT_RANGE) <= std_logic_vector(memARead(ADDR_32BIT_RANGE)); + -- FIXME trigger some kind of alignment exception if memARead(1 downto 0) are not zero + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(ADDR_32BIT_RANGE); + state <= State_Fetch; + end if; + + when Decoded_LoadBH => + out_mem_addr(ADDR_BIT_RANGE) <= std_logic_vector(memARead(ADDR_BIT_RANGE)); + out_mem_bEnable <= opcode(0); -- Loadb is opcode 51, %00110011 + out_mem_hEnable <= not opcode(0); -- Loadh is opcode 34, %00100010 + out_mem_readEnable <= '1'; + state <= State_ReadIOBH; + + when Decoded_EqNeq => + sp <= sp + 1; + state <= State_EqNeq; + + when Decoded_Not => + memAAddr <= sp; + memBAddr <= sp+1; + memAWriteEnable <= '1'; + memAWrite <= not memARead; + + when Decoded_Flip => + memAAddr <= sp; + memBAddr <= sp+1; + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + + when Decoded_Store => + memBAddr(ADDR_32BIT_RANGE) <= sp + 1; + sp <= sp + 1; + + if (memARead(ioBit) = '0') then + state <= State_Store; + else + state <= State_WriteIO; + end if; + + when Decoded_StoreBH => + memBAddr(ADDR_32BIT_RANGE) <= sp + 1; + sp <= sp + 1; + state <= State_WriteIOBH; + + when Decoded_PopSP => + sp <= memARead(ADDR_32BIT_RANGE); + state <= State_Resync; + + when Decoded_Call => + if IMPL_CALL=true then + pc <= memARead(ADDR_BIT_RANGE); -- Set PC to value on top of stack + fetchneeded <= '1'; -- Need to set this any time PC changes. + + memAWriteEnable <= '1'; + memAAddr <= sp; -- Replace stack top with PC+1 + memAWrite <= (others => DontCareValue); + memAWrite(ADDR_BIT_RANGE) <= pc + 1; + state <= State_Fetch; + end if; + + when Decoded_Shift => + IF IMPL_SHIFT=true then + sp <= sp + 1; + shift_count <= unsigned(memARead(5 downto 0)); -- 6 bit distance + shift_reg <= memBRead; -- 32-bit value + shift_direction <= opcode(0); -- 1 for left, (Opcode 43 for Ashiftleft) + shift_sign <= memBRead(31) and opcode(2); -- 1 for arithmetic, (opcode 44 for Ashiftright, 42 for lshiftright) + state <= State_Shift; + end if; + + when Decoded_Nop => + memAAddr <= sp; + state <= State_Fetch; + + when others => + null; + + end case; -- decodedOpcode + + -- From this point on opcode is not guaranteed to be valid if using BlockRAM. + + when State_ReadIO => + memAAddr <= sp; + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= unsigned(mem_read); + end if; + if CACHE=false then + fetchneeded <= '1'; -- Need to set this any time out_mem_addr changes. + end if; + + when State_ReadIOBH => + if IMPL_LOADBH=true then + out_mem_bEnable <= opcode_saved(0); -- Loadb is opcode 51, %00110011 + out_mem_hEnable <= not opcode_saved(0); -- Loadh is copde 34, %00100010 + if in_mem_busy = '0' then + memAAddr <= sp; + -- memAWrite(31 downto 16)<=(others =>'0'); + memAWrite(31 downto 8) <= (others =>'0'); + -- if opcode_saved(0)='1' then -- byte read; upper 24 bits should be zeroed + -- if memARead(0)='1' then -- odd address + -- memAWrite(7 downto 0) <= unsigned(mem_read(7 downto 0)); + -- else + -- memAWrite(7 downto 0) <= unsigned(mem_read(15 downto 8)); + -- end if; + -- else -- short read; upper word should be zeroed. + if opcode_saved(0)='0' then -- only write the top 8 bits for halfword reads + memAWrite(15 downto 8) <= unsigned(mem_read(15 downto 8)); + end if; + memAWrite(7 downto 0) <= unsigned(mem_read(7 downto 0)); + -- end if; + state <= State_Fetch; + memAWriteEnable <= '1'; + out_mem_bEnable <= '0'; + out_mem_hEnable <= '0'; + end if; + if CACHE=false then + fetchneeded <= '1'; -- Need to set this any time out_mem_addr changes. + end if; + end if; + + when State_WriteIO => + -- mem_writeMask <= (others => '1'); + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr(1 downto 0) <= "00"; + out_mem_addr(ADDR_BIT_RANGE) <= std_logic_vector(memARead(ADDR_BIT_RANGE)); + -- FIXME - trigger and alignment exception if memARead(1 downto 0) are not zero. + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + if CACHE=false then + fetchneeded <= '1'; -- Need to set this any time out_mem_addr changes. + end if; + -- (actually, only necessary for writes if mem_read doesn't hold its contents) + + when State_WriteIOBH => + if IMPL_STOREBH=true then + -- mem_writeMask <= (others => '1'); + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_bEnable <= not opcode_saved(0); -- storeb is opcode 52 + out_mem_hEnable <= opcode_saved(0); -- storeh is opcode 35 + out_mem_addr <= std_logic_vector(memARead(ADDR_BIT_RANGE)); + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + if CACHE=false then + fetchneeded <= '1'; -- Need to set this any time out_mem_addr changes. + end if; + -- (actually, only necessary for writes if mem_read doesn't hold its contents) + end if; + + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + out_mem_bEnable <= '0'; + out_mem_hEnable <= '0'; + end if; + + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(ADDR_32BIT_RANGE); + state <= State_FetchNext; + + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + if in_mem_busy='0' or fetchneeded='0' or inrom='1' then + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + + -- If debug enabled, write out state during fetch. + if DEBUG_CPU = true and DEBUG_LEVEL >= 2 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(4, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= X"4645544348000000"; + debugRec.DATA2(63 downto 0) <= (others => '0'); + debugRec.DATA3(63 downto 0) <= (others => '0'); + debugRec.DATA4(63 downto 0) <= (others => '0'); + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(memARead); + debugRec.STACK_NOS <= std_logic_vector(memBRead); + debugLoad <= '1'; + end if; + end if; + + when State_StoreAndDecode => + if interrupt_request = '1' and inInterrupt = '0' and idim_flag = '0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + decodedOpcode <= Decoded_Interrupt; + end if; + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + + when State_Decode => + if interrupt_request = '1' and inInterrupt = '0' and idim_flag = '0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + decodedOpcode <= Decoded_Interrupt; + end if; + -- during the State_Execute cycle we'll be fetching SP+1 (AMR - already done at FetchNext, yes?) + memAAddr <= sp; + memBAddr <= sp + 1; + if fetchneeded='1' then + cachedprogramword <= programword; + fetchneeded <= '0'; + end if; + state <= State_Execute; + + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr(ADDR_32BIT_RANGE) <= memARead(ADDR_32BIT_RANGE); + memAWrite <= memBRead; + state <= State_Resync; + + when State_AddSP => + state <= State_AddSP2; + + when State_AddSP2 => + state <= State_Add; + + when State_Add => + memAAddr <= sp; + memBAddr <= sp+1; + memAWriteEnable <= '1'; + memAWrite(31 downto 16) <= memARead(31 downto 16)+memBRead(31 downto 16)+add_low(17 downto 16); + memAWrite(15 downto 0) <= add_low(15 downto 0); + state<=State_Decode; + if fetchneeded = '1' then + state <= State_Fetch; + end if; + + when State_Sub => + memAAddr <= sp; + memBAddr <= sp+1; + memAWriteEnable <= '1'; + memAWrite <= comparison_sub_result(wordSize-1 downto 0); + state <= State_Decode; + if fetchneeded = '1' then + state <= State_Fetch; + end if; + + when State_Mult => + memAAddr <= sp; + memBAddr <= sp+1; + memAWriteEnable <= '1'; + memAWrite <= tMultResult(wordSize-1 downto 0); + state <= State_Decode; + if fetchneeded = '1' then + state <= State_Fetch; + end if; + + when State_IncSP => + sp <= sp+1; + state <= State_Resync; + + when State_Resync => + memAAddr <= sp; + memBAddr <= sp+1; + state <= State_Decode; + if fetchneeded = '1' then + state <= State_Fetch; + end if; + + when State_EqNeq => + memAAddr <= sp; + memBAddr <= sp+1; + memAWriteEnable <= '1'; + memAWrite <= (others =>'0'); + memAWrite(0) <= comparison_eq xor opcode_saved(4); -- eq is 46, neq is 48. + state <= State_Decode; + if fetchneeded = '1' then + state <= State_Fetch; + end if; + + when State_Comparison => + memAAddr <= sp; + memBAddr <= sp+1; + memAWriteEnable <= '1'; + memAWrite <= (others => '0'); + -- ulessthan: opcode 38, ulessthanorequal, 39 + if opcode_saved(1) = '1' then + memAWrite(0) <= not (comparison_sub_result(wordSize) or (not opcode_saved(0) and comparison_eq)); + else -- Signed comparison, lt: 36, ult: 37 + memAWrite(0) <= not ((comparison_sub_result(wordSize) xor comparison_sign_mod) or (not opcode_saved(0) and comparison_eq)); + end if; + state <= State_Decode; + if fetchneeded = '1' then + state <= State_Fetch; + end if; + + when State_Shift => + if shift_done='1' then + memAAddr <= sp; + memBAddr <= sp+1; + memAWriteEnable <= '1'; + memAWrite <= shift_reg; + state <= State_Decode; + if fetchneeded = '1' then + state <= State_Fetch; + end if; + end if; + + when State_Debug => + case debugState is + when Debug_Start => + + -- Write out the primary data. + if DEBUG_CPU = true then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '0'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '0'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= (others => '0'); + debugRec.DATA2(63 downto 0) <= (others => '0'); + debugRec.DATA3(63 downto 0) <= (others => '0'); + debugRec.DATA4(63 downto 0) <= (others => '0'); + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(memARead); + debugRec.STACK_NOS <= std_logic_vector(memBRead); + debugLoad <= '1'; + debugCnt <= 0; + debugState <= Debug_DumpFifo; + end if; + + when Debug_DumpFifo => + -- Write out the opcode. + if DEBUG_CPU = true then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '0'; + if debugCnt = 3 then + debugRec.FMT_POST_CRLF <= '1'; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '0'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '0'; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.DATA(63 downto 0) <= (others => '0'); + debugRec.DATA2(63 downto 0) <= (others => '0'); + debugRec.DATA3(63 downto 0) <= (others => '0'); + debugRec.DATA4(63 downto 0) <= (others => '0'); + debugRec.OPCODE <= opcode; + debugRec.DECODED_OPCODE <= std_logic_vector(to_unsigned(DecodedOpcodeType'POS(decodedOpcode), 6)); + debugRec.PC(ADDR_BIT_RANGE) <= (others => '0'); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= (others => '0'); + debugRec.STACK_NOS <= (others => '0'); + debugLoad <= '1'; + debugCnt <= 0; + debugState <= Debug_DumpFifo_1; + end if; + + when Debug_DumpFifo_1 => + -- Move onto next opcode in Fifo. + debugCnt <= debugCnt + 1; + if debugCnt = 3 then + debugState <= Debug_End; + else + debugState <= Debug_DumpFifo; + end if; + + when Debug_End => + state <= State_Execute; + end case; + + when others => + null; + + end case; -- state + end if; -- Debug + end if; -- reset, enable + end process; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Debugger output processor. + -- This logic takes a debug record and expands it to human readable form then dispatches it to the debug serial port. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Add debug uart if required. Increasing the TX and DBG Fifo depth can help short term (ie. initial start of the CPU) + -- but once full, the debug run will eventually operate at the slowest denominator, ie. the TX speed and how quick it can + -- shift 10 bits. + DEBUG : if DEBUG_CPU = true generate + DEBUGUART: entity work.zpu_uart_debug + generic map ( + CLK_FREQ => CLK_FREQ -- Frequency of master clock. + ) + port map ( + -- CPU Interface + CLK => clk, -- master clock + RESET => reset, -- high active sync reset + DEBUG_DATA => debugRec, -- write data + CS => debugLoad, -- Chip Select. + READY => debugReady, -- Debug processor ready for next command. + + -- Serial data + TXD => debug_txd + ); + end generate; + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- End of debugger output processor. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + +end behave; diff --git a/zpu/cpu/zpu_core_medium.vhd b/zpu/cpu/zpu_core_medium.vhd new file mode 100644 index 0000000..a581828 --- /dev/null +++ b/zpu/cpu/zpu_core_medium.vhd @@ -0,0 +1,1252 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_pkg.all; + + +-- mem_writeEnable - set to '1' for a single cycle to send off a write request. +-- mem_write is valid only while mem_writeEnable='1'. +-- mem_readEnable - set to '1' for a single cycle to send off a read request. +-- +-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. +-- Set to '0' when mem_read is valid after a read request. +-- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable +-- is '1'. +-- mem_addr - address for read/write request +-- mem_read - read data. Valid only on the cycle after mem_busy='0' after +-- mem_readEnable='1' for a single cycle. +-- mem_write - data to write +-- mem_writeMask - set to '1' for those bits that are to be written to memory upon +-- write request +-- break - set to '1' when CPU hits break instruction +-- interrupt - set to '1' until interrupts are cleared by CPU. + +entity zpu_core_medium is + generic ( + CLK_FREQ : integer := 100000000; -- Frequency of the input clock. + STACK_ADDR : integer := 0 -- Initial stack address on CPU start. + ); + port ( + clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(WORD_32BIT_RANGE); + mem_write : out std_logic_vector(WORD_32BIT_RANGE); + out_mem_addr : out std_logic_vector(ADDR_BIT_RANGE); + out_mem_writeEnable : out std_logic; + out_mem_bEnable : out std_logic; -- Enable byte write + out_mem_hEnable : out std_logic; -- Enable halfword write + out_mem_readEnable : out std_logic; + mem_writeMask : out std_logic_vector(WORD_4BYTE_RANGE); + -- Set to one to jump to interrupt vector + -- The ZPU will communicate with the hardware that caused the + -- interrupt via memory mapped IO or the interrupt flag can + -- be cleared automatically + interrupt_request : in std_logic; + interrupt_ack : out std_logic; -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + interrupt_done : out std_logic; -- Interrupt service routine completed/done. + break : out std_logic; + debug_txd : out std_logic -- Debug serial output. + ); +end zpu_core_medium; + +architecture behave of zpu_core_medium is + + type InsnType is + ( + State_Add, -- 00 + State_AddSP, -- 01 + State_AddTop, -- 02 + State_Alshift, -- 03 + State_And, -- 04 + State_Break, -- 05 + State_Call, -- 06 + State_Callpcrel, -- 07 +-- State_Div, + State_Dup, -- 08 + State_DupStackB, -- 09 + State_Emulate, -- 0a + State_Eq, -- 0b + State_Flip, -- 0c + State_Im, -- 0d + State_Lessthan, -- 0e + State_Lessthanorequal, -- 0f + State_Load, -- 10 + State_Loadb, -- 11 + State_Loadh, -- 12 + State_LoadSP, -- 13 +-- State_Mod, + State_Mult, -- 14 + State_Neq, -- 15 + State_Neqbranch, -- 16 + State_Nop, -- 17 + State_Not, -- 18 + State_Or, -- 19 + State_Pop, -- 1a + State_PopDown, -- 1b + State_PopPC, -- 1c + State_PopPCRel, -- 1d + State_PopSP, -- 1e +-- State_PushPC, + State_PushSP, -- 1f + State_Pushspadd, -- 20 + State_Shift, -- 21 + State_Store, -- 22 + State_Storeb, -- 23 + State_Storeh, -- 24 + State_StoreSP, -- 25 + State_Sub, -- 26 + State_Ulessthan, -- 27 + State_Ulessthanorequal, -- 28 + State_Xor, -- 29 + State_InsnFetch + ); + + type StateType is + ( + State_Load2, + State_Popped, + State_LoadSP2, + State_LoadSP3, + State_AddSP2, + State_Fetch, + State_Execute, + State_Decode, + State_Decode2, + State_Resync, + + State_StoreSP2, + State_Resync2, + State_Resync3, + State_Loadb2, + State_Storeb2, + State_Mult2, + State_Mult3, + State_Mult5, + State_Mult4, + State_BinaryOpResult2, + State_BinaryOpResult, + State_Idle, + State_Interrupt, + State_Debug + ); + -- + type DebugType is + ( + Debug_Start, + Debug_DumpFifo, + Debug_DumpFifo_1, + Debug_End + ); + + signal pc : unsigned(ADDR_BIT_RANGE); + signal sp : unsigned(ADDR_32BIT_RANGE); + signal interrupt_suspended_addr : unsigned(ADDR_BIT_RANGE); + signal incSp : unsigned(ADDR_32BIT_RANGE); + signal incIncSp : unsigned(ADDR_32BIT_RANGE); + signal decSp : unsigned(ADDR_32BIT_RANGE); + signal stackA : unsigned(WORD_32BIT_RANGE); + signal binaryOpResult : unsigned(WORD_32BIT_RANGE); + signal binaryOpResult2 : unsigned(WORD_32BIT_RANGE); + signal multResult2 : unsigned(WORD_32BIT_RANGE); + signal multResult3 : unsigned(WORD_32BIT_RANGE); + signal multResult : unsigned(WORD_32BIT_RANGE); + signal multA : unsigned(WORD_32BIT_RANGE); + signal multB : unsigned(WORD_32BIT_RANGE); + signal stackB : unsigned(WORD_32BIT_RANGE); + signal idim_flag : std_logic; + signal busy : std_logic; + signal mem_writeEnable : std_logic; + signal mem_readEnable : std_logic; + signal mem_addr : std_logic_vector(ADDR_32BIT_RANGE); + signal mem_delayAddr : std_logic_vector(ADDR_32BIT_RANGE); + signal mem_delayReadEnable : std_logic; + + signal inInterrupt : std_logic; + + signal decodeWord : std_logic_vector(WORD_32BIT_RANGE); + + + signal state : StateType; + signal debugState : DebugType; + signal debugCnt : integer; + signal debugRec : zpu_dbg_t; + signal debugLoad : std_logic; + signal debugReady : std_logic; + signal insn : InsnType; + type InsnArray is array(0 to wordBytes-1) of InsnType; + signal decodedOpcode : InsnArray; + + type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + + signal opcode : OpcodeArray; + + signal begin_inst : std_logic; + signal trace_opcode : std_logic_vector(7 downto 0); + signal trace_pc : std_logic_vector(ADDR_BIT_RANGE); + signal trace_sp : std_logic_vector(ADDR_32BIT_RANGE); + signal trace_topOfStack : std_logic_vector(WORD_32BIT_RANGE); + signal trace_topOfStackB : std_logic_vector(WORD_32BIT_RANGE); + + signal clkDivider : std_logic; + +begin + + +-- traceFileGenerate: +-- if Generate_Trace generate +-- trace_file: trace port map ( +-- clk => clk, +-- begin_inst => begin_inst, +-- pc => trace_pc, +-- opcode => trace_opcode, +-- sp => trace_sp, +-- memA => trace_topOfStack, +-- memB => trace_topOfStackB, +-- busy => busy, +-- intsp => (others => 'U') +-- ); +-- end generate; + + -- Not yet implemented. + out_mem_bEnable <= '0'; -- Enable byte write + out_mem_hEnable <= '0'; -- Enable halfword write + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_writeEnable <= mem_writeEnable; + out_mem_readEnable <= mem_readEnable; + out_mem_addr(ADDR_32BIT_RANGE) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + multiPipe: process(clk, areset) + variable tMultResult : unsigned(wordSize*2-1 downto 0); + begin + if areset = '1' then + tMultResult := (others => '0'); + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + end if; + end process; + + + opcodeControl: process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : unsigned(4 downto 0); + variable tSpOffset : unsigned(4 downto 0); + variable nextPC : unsigned(ADDR_BIT_RANGE); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tCPURun : std_logic; + -- variable tMultResult : unsigned(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + tCPURun := '1'; + sp <= to_unsigned(STACK_ADDR, maxAddrBit)(ADDR_32BIT_RANGE); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + inInterrupt <= '0'; + mem_writeEnable <= '0'; + mem_readEnable <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + interrupt_ack <= '0'; + interrupt_done <= '0'; + clkDivider <= '0'; + if DEBUG_CPU = true then + debugRec <= ZPU_DBG_T_INIT; + debugCnt <= 0; + debugLoad <= '0'; + end if; + + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + -- tMultResult := multA * multB; + -- multResult3 <= multResult2; + -- multResult2 <= multResult; + -- multResult <= tMultResult(wordSize-1 downto 0); + + binaryOpResult2 <= binaryOpResult; -- pipeline a bit. + + multA <= (others => DontCareValue); + multB <= (others => DontCareValue); + + -- mem_addr <= (others => DontCareValue); + mem_readEnable <='0'; + mem_writeEnable <='0'; + -- mem_write <= (others => DontCareValue); + + if DEBUG_CPU = true then + debugLoad <= '0'; + end if; + + if (mem_writeEnable = '1') and (mem_readEnable = '1') then + report "read/write collision" severity failure; + end if; + + + -- At the moment, the main state machine wont run at full (100MHz) speed, only 1/2 speed, hence the divider. + -- Once the delay causing it to fail is removed, freq reduced or re-engineered, remove this divider. + clkDivider <= '1'; + if clkDivider = '1' then + clkDivider <= '0'; + if DEBUG_CPU = false or (DEBUG_CPU = true and debugReady = '1') then + tCPURun := '1'; + end if; + else + tCPURun := '0'; + end if; + + spOffset(4) := not opcode(to_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0) := unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0)); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0))); + trace_pc <= std_logic_vector(pc); + trace_sp <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(stackA); + trace_topOfStackB <= std_logic_vector(stackB); + begin_inst <= '0'; + + -- If interrupt is active, we only clear the interrupt state once the PC is reset to the address which was suspended after the + -- interrupt, this prevents recursive interrupt triggers, desirable in cetain circumstances but not for this current design. + -- + interrupt_ack <= '0'; -- Reset interrupt acknowledge if set, width is 1 clock only. + interrupt_done <= '0'; -- Reset interrupt done if set, width is 1 clock only. + if inInterrupt = '1' and pc(ADDR_BIT_RANGE) = interrupt_suspended_addr(ADDR_BIT_RANGE) then + inInterrupt <= '0'; -- no longer in an interrupt + interrupt_done <= '1'; -- Interrupt service routine complete. + end if; + + -- If the cpu can run, continue with next state. + -- + if tCPURun = '1' then + case state is + when State_Idle => + if enable = '1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(sp); + mem_readEnable <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if in_mem_busy = '0' then + stackA <= unsigned(mem_read); + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Resync3; + + -- If debug enabled, write out state during resync. + --if DEBUG_CPU = true then + -- debugRec.FMT_DATA_PRTMODE <= "00"; + -- debugRec.FMT_PRE_SPACE <= '0'; + -- debugRec.FMT_POST_SPACE <= '0'; + -- debugRec.FMT_PRE_CR <= '1'; + -- debugRec.FMT_POST_CRLF <= '1'; + -- debugRec.FMT_SPLIT_DATA <= "00"; + -- debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(5, 3)); + -- debugRec.WRITE_DATA <= '1'; + -- debugRec.WRITE_OPCODE <= '0'; + -- debugRec.WRITE_DECODED_OPCODE <= '0'; + -- debugRec.WRITE_PC <= '1'; + -- debugRec.WRITE_SP <= '1'; + -- debugRec.WRITE_STACK_TOS <= '1'; + -- debugRec.WRITE_STACK_NOS <= '1'; + -- debugRec.DATA <= X"524553594E430000"; + -- debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + -- debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + -- debugRec.STACK_TOS <= std_logic_vector(stackA); + -- debugRec.STACK_NOS <= std_logic_vector(stackB); + -- debugLoad <= '1'; + --end if; + end if; + when State_Resync3 => + if in_mem_busy = '0' then + stackB <= unsigned(mem_read); + mem_addr <= std_logic_vector(pc(ADDR_32BIT_RANGE)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if in_mem_busy = '0' then + decodeWord <= mem_read; + state <= State_Decode2; + -- Do not recurse into ISR while interrupt line is active + if interrupt_request = '1' and inInterrupt = '0' and idim_flag = '0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + interrupt_ack <= '1'; -- Acknowledge interrupt. + interrupt_suspended_addr <= pc(ADDR_BIT_RANGE); -- Save address which got interrupted. + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(ADDR_BIT_RANGE) <= pc; + stackB <= stackA; + pc <= to_unsigned(32, maxAddrBit); + state <= State_Interrupt; + end if; + end if; + when State_Interrupt => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(pc(ADDR_32BIT_RANGE)); + mem_readEnable <= '1'; + state <= State_Decode; + report "ZPU jumped to interrupt!" severity note; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4) := not tOpcode(4); + tSpOffset(3 downto 0) :=unsigned(tOpcode(3 downto 0)); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7) = OpCode_Im) then + tNextState := State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset = 1 then + tNextState := State_PopDown; + else + tNextState := State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState := State_Dup; + elsif tSpOffset = 1 then + tNextState := State_DupStackB; + else + tNextState := State_LoadSP; + end if; + elsif (tOpcode(7 downto 5) = OpCode_Emulate) then + tNextState := State_Emulate; + if tOpcode(5 downto 0) = OpCode_Neqbranch then + tNextState := State_Neqbranch; + elsif tOpcode(5 downto 0) = OpCode_Eq then + tNextState := State_Eq; + elsif tOpcode(5 downto 0) = OpCode_Lessthan then + tNextState := State_Lessthan; + elsif tOpcode(5 downto 0) = OpCode_Lessthanorequal then + tNextState := State_Lessthanorequal; -- + elsif tOpcode(5 downto 0) = OpCode_Ulessthan then + tNextState := State_Ulessthan; + elsif tOpcode(5 downto 0) = OpCode_Ulessthanorequal then + tNextState := State_Ulessthanorequal; -- + elsif tOpcode(5 downto 0) = OpCode_Loadb then + tNextState := State_Loadb; + elsif tOpcode(5 downto 0) = OpCode_Loadh then + -- Emulated + elsif tOpcode(5 downto 0) = OpCode_Mult then + tNextState := State_Mult; + elsif tOpcode(5 downto 0) = OpCode_Storeb then + tNextState := State_Storeb; + elsif tOpcode(5 downto 0) = OpCode_Storeh then + -- Emulated + elsif tOpcode(5 downto 0) = OpCode_Pushspadd then + tNextState := State_Pushspadd; + elsif tOpcode(5 downto 0) = OpCode_Callpcrel then + tNextState := State_Callpcrel; + elsif tOpcode(5 downto 0) = OpCode_Call then + tNextState := State_Call; -- + elsif tOpcode(5 downto 0) = OpCode_Sub then + tNextState := State_Sub; + elsif tOpcode(5 downto 0) = OpCode_PopPCRel then + tNextState := State_PopPCRel; -- + elsif tOpcode(5 downto 0) = OpCode_Lshiftright then + -- Emulated + elsif tOpcode(5 downto 0) = OpCode_Ashiftleft then + -- Emulated + elsif tOpcode(5 downto 0) = OpCode_Ashiftright then + -- Emulated + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState := State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => tNextState := State_Nop; + when OpCode_PushSP => tNextState := State_PushSP; + when OpCode_PopPC => tNextState := State_PopPC; + when OpCode_Add => tNextState := State_Add; + when OpCode_Or => tNextState := State_Or; + when OpCode_And => tNextState := State_And; + when OpCode_Load => tNextState := State_Load; + when OpCode_Not => tNextState := State_Not; + when OpCode_Flip => tNextState := State_Flip; + when OpCode_Store => tNextState := State_Store; + when OpCode_PopSP => tNextState := State_PopSP; + when others => tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + --state <= State_Execute; + if DEBUG_CPU = true then + state <= State_Execute; + debugState <= Debug_Start; + else + state <= State_Execute; + end if; + + when State_Debug => + case debugState is + when Debug_Start => + + -- Write out the primary data. + if DEBUG_CPU = true then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '0'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '0'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= (others => '0'); + debugRec.DATA2(63 downto 0) <= (others => '0'); + debugRec.DATA3(63 downto 0) <= (others => '0'); + debugRec.DATA4(63 downto 0) <= (others => '0'); + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(stackA); + debugRec.STACK_NOS <= std_logic_vector(stackB); + debugLoad <= '1'; + debugCnt <= 0; + debugState <= Debug_DumpFifo; + end if; + + when Debug_DumpFifo => + -- Write out the opcode. + if DEBUG_CPU = true then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '0'; + if debugCnt = 3 then + debugRec.FMT_POST_CRLF <= '1'; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '0'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '0'; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.DATA(63 downto 0) <= (others => '0'); + debugRec.DATA2(63 downto 0) <= (others => '0'); + debugRec.DATA3(63 downto 0) <= (others => '0'); + debugRec.DATA4(63 downto 0) <= (others => '0'); + debugRec.OPCODE <= opcode(debugCnt); + debugRec.DECODED_OPCODE <= std_logic_vector(to_unsigned(InsnType'POS(tDecodedOpcode(debugCnt)), 6)); + debugRec.PC(ADDR_BIT_RANGE) <= (others => '0'); + debugRec.SP(ADDR_32BIT_RANGE) <= (others => '0'); + debugRec.STACK_TOS <= (others => '0'); + debugRec.STACK_NOS <= (others => '0'); + debugLoad <= '1'; + debugCnt <= 0; + debugState <= Debug_DumpFifo_1; + end if; + + when Debug_DumpFifo_1 => + -- Move onto next opcode in Fifo. + debugCnt <= debugCnt + 1; + if debugCnt = 3 then + debugState <= Debug_End; + else + debugState <= Debug_DumpFifo; + end if; + + when Debug_End => + state <= State_Execute; + end case; + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + + -- Debug code, if enabled, writes out the current instruction. + if DEBUG_CPU = true and insn /= State_InsnFetch and pc >= X"9000" then + + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '0'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= (others => '0'); + debugRec.DATA2(63 downto 0) <= (others => '0'); + debugRec.DATA3(63 downto 0) <= (others => '0'); + debugRec.DATA4(63 downto 0) <= (others => '0'); + debugRec.OPCODE <= opcode(to_integer(pc(byteBits-1 downto 0))); + debugRec.DECODED_OPCODE <= std_logic_vector(to_unsigned(InsnType'POS(insn), 6)); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(stackA); + debugRec.STACK_NOS <= std_logic_vector(stackB); + debugLoad <= '1'; + end if; + + insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag = '1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + else + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + end if; + end if; + when State_StoreSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + mem_write <= std_logic_vector(stackA); + stackA <= stackB; + sp <= incSp; + end if; + + when State_LoadSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + when State_Emulate => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(ADDR_BIT_RANGE) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0)); + state <= State_Fetch; + end if; + when State_Callpcrel => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(ADDR_BIT_RANGE) <= pc + 1; + + pc <= pc + stackA(ADDR_BIT_RANGE); + state <= State_Fetch; + end if; + when State_Call => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(ADDR_BIT_RANGE) <= pc + 1; + pc <= stackA(ADDR_BIT_RANGE); + state <= State_Fetch; + end if; + when State_AddSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + end if; + when State_PushSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(ADDR_32BIT_RANGE) <= sp; + stackB <= stackA; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + when State_PopPC => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(ADDR_BIT_RANGE); + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + when State_PopPCRel => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(ADDR_BIT_RANGE) + pc; + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + when State_Add => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_Sub => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + end if; + when State_Pop => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + end if; + when State_PopDown => + if in_mem_busy = '0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + state <= State_Popped; + end if; + when State_Or => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_And => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_Eq => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA = stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Ulessthan => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Lessthan => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Load => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= std_logic_vector(stackA(ADDR_32BIT_RANGE)); + mem_readEnable <= '1'; + end if; + + when State_Dup => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + when State_DupStackB => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + when State_Store => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= std_logic_vector(stackA(ADDR_32BIT_RANGE)); + mem_write <= std_logic_vector(stackB); + mem_writeEnable <= '1'; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_PopSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + sp <= stackA(ADDR_32BIT_RANGE); + state <= State_Resync; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(ADDR_32BIT_RANGE) <= stackA((maxAddrBit-1)-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(ADDR_BIT_RANGE) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when State_Loadb => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= std_logic_vector(stackA(ADDR_32BIT_RANGE)); + mem_readEnable <= '1'; + end if; + when State_Storeb => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= std_logic_vector(stackA(ADDR_32BIT_RANGE)); + mem_readEnable <= '1'; + end if; + + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if in_mem_busy = '0' then + state <= State_LoadSP3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset+1); + end if; + when State_LoadSP3 => + if in_mem_busy = '0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= unsigned(mem_read); + end if; + when State_AddSP2 => + if in_mem_busy = '0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + unsigned(mem_read); + end if; + when State_Load2 => + if in_mem_busy = '0' then + stackA <= unsigned(mem_read); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if in_mem_busy = '0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8)); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(stackA(ADDR_32BIT_RANGE)); + mem_write <= mem_read; + mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0)); + mem_writeEnable <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(pc(ADDR_32BIT_RANGE)); + mem_readEnable <= '1'; + state <= State_Decode; + + -- If debug enabled, write out state during fetch. + if DEBUG_CPU = true and pc >= X"9000" then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(4, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= X"4645544348000000"; + debugRec.DATA2(63 downto 0) <= (others => '0'); + debugRec.DATA3(63 downto 0) <= (others => '0'); + debugRec.DATA4(63 downto 0) <= (others => '0'); + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(stackA); + debugRec.STACK_NOS <= std_logic_vector(stackB); + debugLoad <= '1'; + end if; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + if in_mem_busy = '0' then + stackA <= multResult3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + state <= State_BinaryOpResult2; + when State_BinaryOpResult2 => + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + stackA <= binaryOpResult2; + state <= State_Popped; + when State_Popped => + if in_mem_busy = '0' then + pc <= pc + 1; + stackB <= unsigned(mem_read); + state <= State_Execute; + end if; + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end if; + end process; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Debugger output processor. + -- This logic takes a debug record and expands it to human readable form then dispatches it to the debug serial port. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Add debug uart if required. Increasing the TX and DBG Fifo depth can help short term (ie. initial start of the CPU) + -- but once full, the debug run will eventually operate at the slowest denominator, ie. the TX speed and how quick it can + -- shift 10 bits. + DEBUG : if DEBUG_CPU = true generate + DEBUGUART: entity work.zpu_uart_debug + generic map ( + CLK_FREQ => CLK_FREQ -- Frequency of master clock. + ) + port map ( + -- CPU Interface + CLK => clk, -- master clock + RESET => areset, -- high active sync reset + DEBUG_DATA => debugRec, -- write data + CS => debugLoad, -- Chip Select. + READY => debugReady, -- Debug processor ready for next command. + + -- Serial data + TXD => debug_txd + ); + end generate; + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- End of debugger output processor. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + +end behave; diff --git a/zpu/cpu/zpu_core_small.vhd b/zpu/cpu/zpu_core_small.vhd new file mode 100644 index 0000000..2262d7d --- /dev/null +++ b/zpu/cpu/zpu_core_small.vhd @@ -0,0 +1,771 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.zpu_pkg.all; + +entity zpu_core_small is + generic ( + CLK_FREQ : integer := 100000000; -- Frequency of the input clock. + STACK_ADDR : integer := 0 -- Initial stack address on CPU start. + ); + port ( + clk : in std_logic; + -- asynchronous reset signal + areset : in std_logic; + -- this particular implementation of the ZPU does not + -- have a clocked enable signal + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(WORD_32BIT_RANGE); + mem_write : out std_logic_vector(WORD_32BIT_RANGE); + out_mem_addr : out std_logic_vector(ADDR_BIT_RANGE); + out_mem_writeEnable : out std_logic; + out_mem_bEnable : out std_logic; -- Enable byte write + out_mem_hEnable : out std_logic; -- Enable halfword write + out_mem_readEnable : out std_logic; + -- this implementation of the ZPU *always* reads and writes entire + -- 32 bit words, so mem_writeMask is tied to (others => '1'). + mem_writeMask : out std_logic_vector(WORD_4BYTE_RANGE); + -- Set to one to jump to interrupt vector + -- The ZPU will communicate with the hardware that caused the + -- interrupt via memory mapped IO or the interrupt flag can + -- be cleared automatically + interrupt_request : in std_logic; + interrupt_ack : out std_logic; -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + interrupt_done : out std_logic; -- Interrupt service routine completed/done. + -- Signal that the break instruction is executed, normally only used + -- in simulation to stop simulation + break : out std_logic; + debug_txd : out std_logic; -- Debug serial output. + -- + MEM_A_WRITE_ENABLE : out std_logic; + MEM_A_ADDR : out std_logic_vector(ADDR_32BIT_RANGE); + MEM_A_WRITE : out std_logic_vector(WORD_32BIT_RANGE); + MEM_B_WRITE_ENABLE : out std_logic; + MEM_B_ADDR : out std_logic_vector(ADDR_32BIT_RANGE); + MEM_B_WRITE : out std_logic_vector(WORD_32BIT_RANGE); + MEM_A_READ : in std_logic_vector(WORD_32BIT_RANGE); + MEM_B_READ : in std_logic_vector(WORD_32BIT_RANGE) + ); +end zpu_core_small; + +architecture behave of zpu_core_small is + + -- state machine. + type State_Type is + ( + State_Fetch, + State_WriteIODone, + State_Execute, + State_StoreToStack, + State_Add, + State_Or, + State_And, + State_Store, + State_ReadIO, + State_WriteIO, + State_Load, + State_FetchNext, + State_AddSP, + State_ReadIODone, + State_Decode, + State_Resync, + State_Interrupt, + State_Debug + ); + + type DecodedOpcodeType is + ( + Decoded_Nop, + Decoded_Im, + Decoded_ImShift, + Decoded_LoadSP, + Decoded_StoreSP , + Decoded_AddSP, + Decoded_Emulate, + Decoded_Break, + Decoded_PushSP, + Decoded_PopPC, + Decoded_Add, + Decoded_Or, + Decoded_And, + Decoded_Load, + Decoded_Not, + Decoded_Flip, + Decoded_Store, + Decoded_PopSP, + Decoded_Interrupt + ); + + -- + type DebugType is + ( + Debug_Start, + Debug_DumpFifo, + Debug_DumpFifo_1, + Debug_End + ); + + signal readIO : std_logic; + + signal memAWriteEnable : std_logic; + signal memAAddr : unsigned(ADDR_32BIT_RANGE); + signal memAWrite : unsigned(WORD_32BIT_RANGE); + signal memARead : unsigned(WORD_32BIT_RANGE); + signal memBWriteEnable : std_logic; + signal memBAddr : unsigned(ADDR_32BIT_RANGE); + signal memBWrite : unsigned(WORD_32BIT_RANGE); + signal memBRead : unsigned(WORD_32BIT_RANGE); + + signal pc : unsigned(ADDR_BIT_RANGE); + signal sp : unsigned(ADDR_32BIT_RANGE); + signal interrupt_suspended_addr : unsigned(ADDR_BIT_RANGE); + + -- this signal is set upon executing an IM instruction + -- the subsequence IM instruction will then behave differently. + -- all other instructions will clear the idim_flag. + -- this yields highly compact immediate instructions. + signal idim_flag : std_logic; + + signal busy : std_logic; + + signal begin_inst : std_logic; + + signal trace_opcode : std_logic_vector(7 downto 0); + signal trace_pc : std_logic_vector(ADDR_BIT_RANGE); + signal trace_sp : std_logic_vector(ADDR_32BIT_RANGE); + signal trace_topOfStack : std_logic_vector(WORD_32BIT_RANGE); + signal trace_topOfStackB : std_logic_vector(WORD_32BIT_RANGE); + signal debugState : DebugType; + signal debugCnt : integer; + signal debugRec : zpu_dbg_t; + signal debugLoad : std_logic; + signal debugReady : std_logic; + + signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); + signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + + signal decodedOpcode : DecodedOpcodeType; + signal sampledDecodedOpcode : DecodedOpcodeType; + + signal state : State_Type; + + subtype index is integer range 0 to 3; + + signal tOpcode_sel : index; + + signal inInterrupt : std_logic; + +begin + + -- generate a trace file. + -- + -- This is only used in simulation to see what instructions are + -- executed. + -- + -- a quick & dirty regression test is then to commit trace files + -- to CVS and compare the latest trace file against the last known + -- good trace file +-- traceFileGenerate: +-- if Generate_Trace generate +-- trace_file: trace port map ( +-- clk => clk, +-- begin_inst => begin_inst, +-- pc => trace_pc, +-- opcode => trace_opcode, +-- sp => trace_sp, +-- memA => trace_topOfStack, +-- memB => trace_topOfStackB, +-- busy => busy, +-- intsp => (others => 'U') +-- ); +-- end generate; + + + -- Not yet implemented. + out_mem_bEnable <= '0'; -- Enable byte write + out_mem_hEnable <= '0'; -- Enable halfword write + + -- Wire up the RAM/ROM + MEM_A_ADDR <= std_logic_vector(memAAddr(ADDR_32BIT_RANGE)); + MEM_A_WRITE <= std_logic_vector(memAWrite); + MEM_B_ADDR <= std_logic_vector(memBAddr(ADDR_32BIT_RANGE)); + MEM_B_WRITE <= std_logic_vector(memBWrite); + memARead <= unsigned(MEM_A_READ); + memBRead <= unsigned(MEM_B_READ); + MEM_A_WRITE_ENABLE <= memAWriteEnable; + MEM_B_WRITE_ENABLE <= memBWriteEnable; + + -- mem_writeMask is not used in this design, tie it to 1 + mem_writeMask <= (others => '1'); + + tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + + -- move out calculation of the opcode to a seperate process + -- to make things a bit easier to read + decodeControl: process(memBRead, pc,tOpcode_sel) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + + -- simplify opcode selection a bit so it passes more synthesizers + case (tOpcode_sel) is + + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); + end case; + + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7) = OpCode_Im) then + sampledDecodedOpcode <= Decoded_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + sampledDecodedOpcode <= Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + sampledDecodedOpcode <= Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + sampledDecodedOpcode <= Decoded_Emulate; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + sampledDecodedOpcode <= Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode <= Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode <= Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode <= Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode <= Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode <= Decoded_Or; + when OpCode_And => + sampledDecodedOpcode <= Decoded_And; + when OpCode_Load => + sampledDecodedOpcode <= Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode <= Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode <= Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode <= Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode <= Decoded_PopSP; + when others => + sampledDecodedOpcode <= Decoded_Nop; + end case; + end if; + end process; + + + opcodeControl: + process(clk, areset) + variable spOffset : unsigned(4 downto 0); + begin + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= to_unsigned(STACK_ADDR, maxAddrBit)(ADDR_32BIT_RANGE); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + inInterrupt <= '0'; + interrupt_ack <= '0'; + interrupt_done <= '0'; + if DEBUG_CPU = true then + debugRec <= ZPU_DBG_T_INIT; + debugCnt <= 0; + debugLoad <= '0'; + end if; + + elsif (clk'event and clk = '1') then + + if DEBUG_CPU = true then + debugLoad <= '0'; + end if; + + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + + -- If the cpu can run, continue with next state. + -- + if DEBUG_CPU = false or (DEBUG_CPU = true and debugReady = '1') then + + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); + -- out_mem_addr <= (others => DontCareValue); + -- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= std_logic_vector(memARead(ADDR_BIT_RANGE)); + mem_write <= std_logic_vector(memBRead); + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + + -- If interrupt is active, we only clear the interrupt state once the PC is reset to the address which was suspended after the + -- interrupt, this prevents recursive interrupt triggers, desirable in cetain circumstances but not for this current design. + -- + interrupt_ack <= '0'; -- Reset interrupt acknowledge if set, width is 1 clock only. + interrupt_done <= '0'; -- Reset interrupt done if set, width is 1 clock only. + if inInterrupt = '1' and pc(ADDR_BIT_RANGE) = interrupt_suspended_addr(ADDR_BIT_RANGE) then + inInterrupt <= '0'; -- no longer in an interrupt + interrupt_done <= '1'; -- Interrupt service routine complete. + end if; + + case state is + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + --begin_inst <= '1'; + --trace_pc <= (others => '0'); + --trace_pc(ADDR_BIT_RANGE) <= std_logic_vector(pc); + --trace_opcode <= opcode; + --trace_sp <= (others => '0'); + --trace_sp(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + --trace_topOfStack <= std_logic_vector(memARead); + --trace_topOfStackB <= std_logic_vector(memBRead); + + -- during the next cycle we'll be reading the next opcode + spOffset(4) :=not opcode(4); + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + -- Debug code, if enabled, writes out the current instruction. + if DEBUG_CPU = true and DEBUG_LEVEL >= 1 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '0'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= (others => '0'); + debugRec.DATA2(63 downto 0) <= (others => '0'); + debugRec.DATA3(63 downto 0) <= (others => '0'); + debugRec.DATA4(63 downto 0) <= (others => '0'); + debugRec.OPCODE <= opcode; + debugRec.DECODED_OPCODE <= std_logic_vector(to_unsigned(DecodedOpcodeType'POS(decodedOpcode), 6)); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(memARead); + debugRec.STACK_NOS <= std_logic_vector(memBRead); + debugLoad <= '1'; + end if; + + idim_flag <= '0'; + case decodedOpcode is + when Decoded_Interrupt => + interrupt_ack <= '1'; -- Acknowledge interrupt. + interrupt_suspended_addr <= pc(ADDR_BIT_RANGE); -- Save address which got interrupted. + sp <= sp - 1; + memAAddr <= sp - 1; + memAWriteEnable <= '1'; + memAWrite <= (others => DontCareValue); + memAWrite(ADDR_BIT_RANGE) <= pc; + pc <= to_unsigned(32, maxAddrBit); -- interrupt address + report "ZPU jumped to interrupt!" severity note; + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag='0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + end if; + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(ADDR_BIT_RANGE) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(4 downto 0)); + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(ADDR_32BIT_RANGE) <= sp; + when Decoded_PopPC => + pc <= memARead(ADDR_BIT_RANGE); + sp <= sp + 1; + state <= State_Resync; + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + when Decoded_And => + sp <= sp + 1; + state <= State_And; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= std_logic_vector(memARead(ADDR_BIT_RANGE)); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(ADDR_32BIT_RANGE); + end if; + when Decoded_Not => + memAAddr <= sp(ADDR_32BIT_RANGE); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + when Decoded_Flip => + memAAddr <= sp(ADDR_32BIT_RANGE); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit)='1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + when Decoded_PopSP => + sp <= memARead(ADDR_32BIT_RANGE); + state <= State_Resync; + when Decoded_Nop => + memAAddr <= sp; + when others => + null; + end case; + when State_ReadIO => + memAAddr <= sp; + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= unsigned(mem_read); + end if; + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= std_logic_vector(memARead(ADDR_BIT_RANGE)); + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(ADDR_32BIT_RANGE); + state <= State_FetchNext; + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + + -- If debug enabled, write out state during fetch. + if DEBUG_CPU = true and DEBUG_LEVEL >= 2 then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '1'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(4, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '1'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= X"4645544348000000"; + debugRec.DATA2(63 downto 0) <= (others => '0'); + debugRec.DATA3(63 downto 0) <= (others => '0'); + debugRec.DATA4(63 downto 0) <= (others => '0'); + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(memARead); + debugRec.STACK_NOS <= std_logic_vector(memBRead); + debugLoad <= '1'; + end if; + when State_Decode => + if interrupt_request='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + decodedOpcode <= Decoded_Interrupt; + end if; + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(ADDR_32BIT_RANGE); + memAWrite <= memBRead; + state <= State_Resync; + when State_AddSP => + state <= State_Add; + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + when State_Debug => + case debugState is + when Debug_Start => + + -- Write out the primary data. + if DEBUG_CPU = true then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '0'; + debugRec.FMT_PRE_CR <= '1'; + debugRec.FMT_POST_CRLF <= '0'; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '0'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '0'; + debugRec.WRITE_DECODED_OPCODE <= '0'; + debugRec.WRITE_PC <= '1'; + debugRec.WRITE_SP <= '1'; + debugRec.WRITE_STACK_TOS <= '1'; + debugRec.WRITE_STACK_NOS <= '1'; + debugRec.DATA(63 downto 0) <= (others => '0'); + debugRec.DATA2(63 downto 0) <= (others => '0'); + debugRec.DATA3(63 downto 0) <= (others => '0'); + debugRec.DATA4(63 downto 0) <= (others => '0'); + debugRec.OPCODE <= (others => '0'); + debugRec.DECODED_OPCODE <= (others => '0'); + debugRec.PC(ADDR_BIT_RANGE) <= std_logic_vector(pc); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= std_logic_vector(memARead); + debugRec.STACK_NOS <= std_logic_vector(memBRead); + debugLoad <= '1'; + debugCnt <= 0; + debugState <= Debug_DumpFifo; + end if; + + when Debug_DumpFifo => + -- Write out the opcode. + if DEBUG_CPU = true then + debugRec.FMT_DATA_PRTMODE <= "00"; + debugRec.FMT_PRE_SPACE <= '0'; + debugRec.FMT_POST_SPACE <= '1'; + debugRec.FMT_PRE_CR <= '0'; + if debugCnt = 3 then + debugRec.FMT_POST_CRLF <= '1'; + else + debugRec.FMT_POST_CRLF <= '0'; + end if; + debugRec.FMT_SPLIT_DATA <= "00"; + debugRec.DATA_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA2_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA3_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.DATA4_BYTECNT <= std_logic_vector(to_unsigned(0, 3)); + debugRec.WRITE_DATA <= '0'; + debugRec.WRITE_DATA2 <= '0'; + debugRec.WRITE_DATA3 <= '0'; + debugRec.WRITE_DATA4 <= '0'; + debugRec.WRITE_OPCODE <= '1'; + debugRec.WRITE_DECODED_OPCODE <= '1'; + debugRec.WRITE_PC <= '0'; + debugRec.WRITE_SP <= '0'; + debugRec.WRITE_STACK_TOS <= '0'; + debugRec.WRITE_STACK_NOS <= '0'; + debugRec.DATA(63 downto 0) <= (others => '0'); + debugRec.DATA2(63 downto 0) <= (others => '0'); + debugRec.DATA3(63 downto 0) <= (others => '0'); + debugRec.DATA4(63 downto 0) <= (others => '0'); + debugRec.OPCODE <= opcode; + debugRec.DECODED_OPCODE <= std_logic_vector(to_unsigned(DecodedOpcodeType'POS(decodedOpcode), 6)); + debugRec.PC(ADDR_BIT_RANGE) <= (others => '0'); + debugRec.SP(ADDR_32BIT_RANGE) <= std_logic_vector(sp); + debugRec.STACK_TOS <= (others => '0'); + debugRec.STACK_NOS <= (others => '0'); + debugLoad <= '1'; + debugCnt <= 0; + debugState <= Debug_DumpFifo_1; + end if; + + when Debug_DumpFifo_1 => + -- Move onto next opcode in Fifo. + debugCnt <= debugCnt + 1; + if debugCnt = 3 then + debugState <= Debug_End; + else + debugState <= Debug_DumpFifo; + end if; + + when Debug_End => + state <= State_Execute; + end case; + when others => + null; + end case; + end if; + end if; + end process; + + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Debugger output processor. + -- This logic takes a debug record and expands it to human readable form then dispatches it to the debug serial port. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- Add debug uart if required. Increasing the TX and DBG Fifo depth can help short term (ie. initial start of the CPU) + -- but once full, the debug run will eventually operate at the slowest denominator, ie. the TX speed and how quick it can + -- shift 10 bits. + DEBUG : if DEBUG_CPU = true generate + DEBUGUART: entity work.zpu_uart_debug + generic map ( + CLK_FREQ => CLK_FREQ -- Frequency of master clock. + ) + port map ( + -- CPU Interface + CLK => clk, -- master clock + RESET => areset, -- high active sync reset + DEBUG_DATA => debugRec, -- write data + CS => debugLoad, -- Chip Select. + READY => debugReady, -- Debug processor ready for next command. + + -- Serial data + TXD => debug_txd + ); + end generate; + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + -- End of debugger output processor. + ----------------------------------------------------------------------------------------------------------------------------------------------------------- + +end behave; diff --git a/zpu/cpu/zpu_pkg.vhd b/zpu/cpu/zpu_pkg.vhd new file mode 100644 index 0000000..cc420d2 --- /dev/null +++ b/zpu/cpu/zpu_pkg.vhd @@ -0,0 +1,473 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com +-- Copyright 2018-2019 psmart - Philip Smart +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package zpu_pkg is + + -- Necessary functions for type conversion. + -- + function bool_to_integer(level : boolean) return integer; + + -- Evo specific options. + -- + constant EVO_USE_INSN_BUS : boolean := false; -- Use a seperate instruction bus to connect to the BRAM memory. All other operations go over the normal bus. + constant EVO_USE_HW_BYTE_WRITE : boolean := true; -- Implement hardware writing of bytes, reads are always 32bit and aligned. + constant EVO_USE_HW_WORD_WRITE : boolean := true; -- Implement hardware writing of 16bit words, reads are always 32bit and aligned. + constant EVO_USE_WB_BUS : boolean := false; -- Implement the wishbone interface in addition to the standard direct interface. NB: Change WB_ACTIVE to 1 above if enabling. + + -- Debug options. + -- + constant DEBUG_CPU : boolean := false; -- Enable CPU debugging output. + constant DEBUG_LEVEL : integer := 0; -- Level of debugging output. 0 = Basic, such as Breakpoint, 1 =+ Executing Instructions, 2 =+ L1 Cache contents, 3 =+ L2 Cache contents, 4 =+ Memory contents, 5=+ 4Everything else. + constant DEBUG_MAX_TX_FIFO_BITS : integer := 12; -- Size of UART TX Fifo for debug output. + constant DEBUG_MAX_FIFO_BITS : integer := 3; -- Size of debug output data records fifo. + constant DEBUG_TX_BAUD_RATE : integer := 115200; --230400; -- Baud rate for the debug transmitter. + + -- Constants common to all ZPU models source code. + constant Generate_Trace : boolean := false; -- generate trace output or not. + constant wordPower : integer := 5; -- The number of bits in a word, defined as 2^wordPower). + constant DontCareValue : std_logic := 'X'; -- during simulation, set this to '0' to get matching trace.txt + constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes + constant wordSize : integer := 2**wordPower; + constant wordBytes : integer := wordSize/8; + constant minAddrBit : integer := byteBits; + constant WB_ACTIVE : integer := bool_to_integer(EVO_USE_WB_BUS); -- Set to 1 if the wishbone interface is active to divide the address space in two, lower = direct access, upper = wishbone. + constant maxAddrBit : integer := 24 + WB_ACTIVE; -- Maximum address limit in bits. + constant maxAddrSize : integer := (2**maxAddrBit); -- Maximum address space size in bytes. + constant maxIOBit : integer := maxAddrBit - WB_ACTIVE - 4; -- Upper bit (to define range) of IO space in top section of address space. + constant ioBit : integer := maxAddrBit - 1; -- Non-EVO: MSB is used to differentiate IO and memory. + + constant ADDR_32BIT_SIZE : integer := maxAddrBit - minAddrBit; -- Bits in the address bus relevant for 32bit access. + constant WB_SELECT_BIT : integer := maxAddrBit - 1; -- Bit which divides the wishbone interface from normal memory space. + + -- Ranges used throughout the SOC/ZPU source. + subtype ADDR_BIT_RANGE is natural range maxAddrBit-1 downto 0; -- Full address range - 1 byte aligned + subtype ADDR_16BIT_RANGE is natural range maxAddrBit-1 downto 1; -- Full address range - 2 bytes (16bit) aligned + subtype ADDR_32BIT_RANGE is natural range maxAddrBit-1 downto minAddrBit; -- Full address range - 4 bytes (32bit) aligned + subtype ADDR_64BIT_RANGE is natural range maxAddrBit-1 downto minAddrBit+1; -- Full address range - 8 bytes (64bit) aligned + subtype ADDR_IOBIT_RANGE is natural range ioBit downto minAddrBit; -- Non-EVO: IO range. + subtype WORD_32BIT_RANGE is natural range wordSize-1 downto 0; -- Number of bits in a word (normally 32 for this CPU). + subtype WORD_16BIT_RANGE is natural range (wordSize/2)-1 downto 0; -- Number of bits in a half-word (normally 16 for this CPU). + subtype WORD_UPPER_16BIT_RANGE is natural range (wordSize/2)-1 downto wordSize/4; -- Number of bits in a half-word (normally 16 for this CPU). + subtype WORD_LOWER_16BIT_RANGE is natural range (wordSize/4)-1 downto 0; -- Number of bits in a half-word (normally 16 for this CPU). + subtype WORD_8BIT_RANGE is natural range (wordSize/4)-1 downto 0; -- Number of bits in a byte (normally 8 for this CPU). + subtype WORD_4BYTE_RANGE is natural range wordBytes-1 downto 0; -- Bits needed to represent wordSize in bytes (normally 4 for 32bits). + subtype BYTE_RANGE is natural range 7 downto 0; -- Number of bits in a byte. + + ------------------------------------------------------------ + -- components + ------------------------------------------------------------ + component zpu_core_flex is + generic ( + IMPL_MULTIPLY : boolean := true; -- Self explanatory + IMPL_COMPARISON_SUB : boolean := true; -- Include sub and (U)lessthan(orequal) + IMPL_EQBRANCH : boolean := true; -- Include eqbranch and neqbranch + IMPL_STOREBH : boolean := false; -- Include halfword and byte writes + IMPL_LOADBH : boolean := false; -- Include halfword and byte reads + IMPL_CALL : boolean := true; -- Include call + IMPL_SHIFT : boolean := true; -- Include lshiftright, ashiftright and ashiftleft + IMPL_XOR : boolean := true; -- include xor instruction + CACHE : boolean := true; + CLK_FREQ : integer := 100000000; -- Frequency of the input clock. + STACK_ADDR : integer := 0 -- Initial stack address on CPU start. + ); + port ( + clk : in std_logic; + reset : in std_logic; + enable : in std_logic := '1'; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(WORD_32BIT_RANGE); + mem_write : out std_logic_vector(WORD_32BIT_RANGE); + out_mem_addr : out std_logic_vector(ADDR_BIT_RANGE); + out_mem_writeEnable : out std_logic; + out_mem_bEnable : out std_logic; + out_mem_hEnable : out std_logic; + out_mem_readEnable : out std_logic; + --mem_writeMask + interrupt_request : in std_logic; + interrupt_ack : out std_logic; -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + interrupt_done : out std_logic; -- Interrupt service routine completed/done. + break : out std_logic; + debug_txd : out std_logic; -- Debug serial output. + -- + MEM_A_WRITE_ENABLE : out std_logic; + MEM_A_ADDR : out std_logic_vector(ADDR_32BIT_RANGE); + MEM_A_WRITE : out std_logic_vector(WORD_32BIT_RANGE); + MEM_B_WRITE_ENABLE : out std_logic; + MEM_B_ADDR : out std_logic_vector(ADDR_32BIT_RANGE); + MEM_B_WRITE : out std_logic_vector(WORD_32BIT_RANGE); + MEM_A_READ : in std_logic_vector(WORD_32BIT_RANGE); + MEM_B_READ : in std_logic_vector(WORD_32BIT_RANGE) + ); + end component zpu_core_flex; + + component zpu_core_small is + generic ( + CLK_FREQ : integer := 100000000; -- Frequency of the input clock. + STACK_ADDR : integer := 0 -- Initial stack address on CPU start. + ); + port ( + clk : in std_logic; + -- asynchronous reset signal + areset : in std_logic; + -- this particular implementation of the ZPU does not + -- have a clocked enable signal + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(WORD_32BIT_RANGE); + mem_write : out std_logic_vector(WORD_32BIT_RANGE); + out_mem_addr : out std_logic_vector(ADDR_BIT_RANGE); + out_mem_writeEnable : out std_logic; + out_mem_bEnable : out std_logic; + out_mem_hEnable : out std_logic; + out_mem_readEnable : out std_logic; + -- this implementation of the ZPU *always* reads and writes entire + -- 32 bit words, so mem_writeMask is tied to (others => '1'). + mem_writeMask : out std_logic_vector(wordBytes-1 downto 0); + -- Set to one to jump to interrupt vector + -- The ZPU will communicate with the hardware that caused the + -- interrupt via memory mapped IO or the interrupt flag can + -- be cleared automatically + interrupt_request : in std_logic; + interrupt_ack : out std_logic; -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + interrupt_done : out std_logic; -- Interrupt service routine completed/done. : out std_logic_vector(wordBytes-1 downto 0); + -- Signal that the break instruction is executed, normally only used + -- in simulation to stop simulation + break : out std_logic; + debug_txd : out std_logic; -- Debug serial output. + -- + MEM_A_WRITE_ENABLE : out std_logic; + MEM_A_ADDR : out std_logic_vector(ADDR_32BIT_RANGE); + MEM_A_WRITE : out std_logic_vector(WORD_32BIT_RANGE); + MEM_B_WRITE_ENABLE : out std_logic; + MEM_B_ADDR : out std_logic_vector(ADDR_32BIT_RANGE); + MEM_B_WRITE : out std_logic_vector(WORD_32BIT_RANGE); + MEM_A_READ : in std_logic_vector(WORD_32BIT_RANGE); + MEM_B_READ : in std_logic_vector(WORD_32BIT_RANGE) + ); + end component zpu_core_small; + + component zpu_core_medium is + generic ( + CLK_FREQ : integer := 100000000; -- Frequency of the input clock. + STACK_ADDR : integer := 0 -- Initial stack address on CPU start. + ); + port ( + clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(WORD_32BIT_RANGE); + mem_write : out std_logic_vector(WORD_32BIT_RANGE); + out_mem_addr : out std_logic_vector(ADDR_BIT_RANGE); + out_mem_writeEnable : out std_logic; + out_mem_bEnable : out std_logic; + out_mem_hEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask : out std_logic_vector(WORD_4BYTE_RANGE); + interrupt_request : in std_logic; + interrupt_ack : out std_logic; -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + interrupt_done : out std_logic; -- Interrupt service routine completed/done. : out std_logic_vector(wordBytes-1 downto 0); + break : out std_logic; + debug_txd : out std_logic -- Debug serial output. + ); + end component zpu_core_medium; + + component zpu_core_evo is + generic ( + -- Optional hardware features to be implemented. + IMPL_HW_BYTE_WRITE : boolean := false; -- Enable use of hardware direct byte write rather than read 32bits-modify 8 bits-write 32bits. + IMPL_HW_WORD_WRITE : boolean := false; -- Enable use of hardware direct byte write rather than read 32bits-modify 16 bits-write 32bits. + IMPL_OPTIMIZE_IM : boolean := true; -- If the instruction cache is enabled, optimise Im instructions to gain speed. + IMPL_USE_INSN_BUS : boolean := true; -- Use a seperate bus to read instruction memory, normally implemented in BRAM. + IMPL_USE_WB_BUS : boolean := true; -- Use the wishbone interface in addition to direct access bus. + -- Optional instructions to be implemented in hardware: + IMPL_ASHIFTLEFT : boolean := true; -- Arithmetic Shift Left (uses same logic so normally combined with ASHIFTRIGHT and LSHIFTRIGHT). + IMPL_ASHIFTRIGHT : boolean := true; -- Arithmetic Shift Right. + IMPL_CALL : boolean := true; -- Call to direct address. + IMPL_CALLPCREL : boolean := true; -- Call to indirect address (add offset to program counter). + IMPL_DIV : boolean := true; -- 32bit signed division. + IMPL_EQ : boolean := true; -- Equality test. + IMPL_EXTENDED_INSN : boolean := true; -- Extended multibyte instruction set. + IMPL_FIADD32 : boolean := true; -- Fixed point Q17.15 addition. + IMPL_FIDIV32 : boolean := true; -- Fixed point Q17.15 division. + IMPL_FIMULT32 : boolean := true; -- Fixed point Q17.15 multiplication. + IMPL_LOADB : boolean := true; -- Load single byte from memory. + IMPL_LOADH : boolean := true; -- Load half word (16bit) from memory. + IMPL_LSHIFTRIGHT : boolean := true; -- Logical shift right. + IMPL_MOD : boolean := true; -- 32bit modulo (remainder after division). + IMPL_MULT : boolean := true; -- 32bit signed multiplication. + IMPL_NEG : boolean := true; -- Negate value in TOS. + IMPL_NEQ : boolean := true; -- Not equal test. + IMPL_POPPCREL : boolean := true; -- Pop a value into the Program Counter from a location relative to the Stack Pointer. + IMPL_PUSHSPADD : boolean := true; -- Add a value to the Stack pointer and push it onto the stack. + IMPL_STOREB : boolean := true; -- Store/Write a single byte to memory/IO. + IMPL_STOREH : boolean := true; -- Store/Write a half word (16bit) to memory/IO. + IMPL_SUB : boolean := true; -- 32bit signed subtract. + IMPL_XOR : boolean := true; -- Exclusive or of value in TOS. + -- Size/Control parameters for the optional hardware. + MAX_INSNRAM_SIZE : integer := 32768; -- Maximum size of the optional Instruction BRAM on the INSN Bus. + MAX_L1CACHE_BITS : integer := 4; -- Maximum size in bytes of the Level 1 instruction cache governed by the number of bits, ie. 8 = 256 byte cache. + MAX_L2CACHE_BITS : integer := 12; -- Maximum size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache. + MAX_MXCACHE_BITS : integer := 4; -- Maximum size of the memory transaction cache governed by the number of bits. + RESET_ADDR_CPU : integer := 0; -- Initial start address of the CPU. + START_ADDR_MEM : integer := 0; -- Start address of program memory. + STACK_ADDR : integer := 0; -- Initial stack address on CPU start. + CLK_FREQ : integer := 100000000 -- Frequency of the input clock. + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + ENABLE : in std_logic; + -- + MEM_BUSY : in std_logic; + MEM_DATA_IN : in std_logic_vector(WORD_32BIT_RANGE); + MEM_DATA_OUT : out std_logic_vector(WORD_32BIT_RANGE); + MEM_ADDR : out std_logic_vector(ADDR_BIT_RANGE); + MEM_WRITE_ENABLE : out std_logic; + MEM_READ_ENABLE : out std_logic; + MEM_WRITE_BYTE : out std_logic; + MEM_WRITE_HWORD : out std_logic; + -- Instruction memory path + MEM_BUSY_INSN : in std_logic; + MEM_DATA_IN_INSN : in std_logic_vector(WORD_32BIT_RANGE); + MEM_ADDR_INSN : out std_logic_vector(ADDR_BIT_RANGE); + MEM_READ_ENABLE_INSN : out std_logic; + -- Master Wishbone Memory/IO bus interface. + WB_CLK_I : in std_logic; + WB_RST_I : in std_logic; + WB_ACK_I : in std_logic; + WB_DAT_I : in std_logic_vector(WORD_32BIT_RANGE); + WB_DAT_O : out std_logic_vector(WORD_32BIT_RANGE); + WB_ADR_O : out std_logic_vector(ADDR_BIT_RANGE); + WB_CYC_O : out std_logic; + WB_STB_O : out std_logic; + WB_CTI_O : out std_logic_vector(2 downto 0); + WB_WE_O : out std_logic; + WB_SEL_O : out std_logic_vector(WORD_4BYTE_RANGE); + WB_HALT_I : in std_logic; + WB_ERR_I : in std_logic; + WB_INTA_I : in std_logic; + + -- Set to one to jump to interrupt vector + -- The ZPU will communicate with the hardware that caused the + -- interrupt via memory mapped IO or the interrupt flag can + -- be cleared automatically + INT_REQ : in std_logic; + INT_ACK : out std_logic; -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + INT_DONE : out std_logic; -- Interrupt service routine completed/done. + -- Break and debug signals. + BREAK : out std_logic; -- A break instruction encountered. + CONTINUE : in std_logic; -- When break activated, processing stops. Setting CONTINUE to logic 1 resumes processing with next instruction. + DEBUG_TXD : out std_logic -- Debug serial output. + ); + end component zpu_core_evo; + + component dpram + generic ( + init_file : string; + widthad_a : natural; + width_a : natural; + widthad_b : natural; + width_b : natural; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + port ( + clock_a : in std_logic := '1'; + clocken_a : in std_logic := '1'; + address_a : in std_logic_vector (widthad_a-1 downto 0); + data_a : in std_logic_vector (width_a-1 downto 0); + wren_a : in std_logic := '0'; + q_a : out std_logic_vector (width_a-1 downto 0); + + clock_b : in std_logic; + clocken_b : in std_logic := '1'; + address_b : in std_logic_vector (widthad_b-1 downto 0); + data_b : in std_logic_vector (width_b-1 downto 0); + wren_b : in std_logic := '0'; + q_b : out std_logic_vector (width_b-1 downto 0) + ); + end component; + + ------------------------------------------------------------ + -- constants + ------------------------------------------------------------ + + -- opcode decode constants + constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; + constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; + constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; + constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; + constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; + constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; + -- + constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; + constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001"; + constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; + constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011"; + -- + constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; + constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; + constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; + constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; + -- + constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; + constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; + constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; + constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; + -- + constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; + constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; + constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_Extend : std_logic_vector(3 downto 0) := "1111"; + -- + constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6)); + constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6)); + -- + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6)); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6)); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6)); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6)); + -- + constant OpCode_NA5 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6)); + constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6)); + -- + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6)); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6)); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6)); + constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6)); + -- + constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6)); + constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6)); + -- + constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6)); + constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6)); + constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6)); + -- + constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6)); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6)); + -- + constant OpCode_Div : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(53, 6)); + constant OpCode_Mod : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(54, 6)); + -- + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6)); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6)); + constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6)); + -- + constant OpCode_FiAdd32 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(58, 6)); + constant OpCode_FiDiv32 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(59, 6)); + constant OpCode_FiMult32 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(60, 6)); + -- + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6)); + constant OpCode_NA6 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6)); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6)); + -- + -- Extension instructions. + constant Opcode_Ex_ESR : std_logic_vector(7 downto 0) := "00000000"; + constant Opcode_Ex_LDIR : std_logic_vector(7 downto 3) := "00001"; + constant Opcode_Ex_Fill : std_logic_vector(7 downto 3) := "00010"; + -- + constant OpCode_Size : integer := 8; + -- + + ------------------------------------------------------------ + -- records + ------------------------------------------------------------ + + -- Debug structure, currently only for the trace module + type zpu_dbgo_t is record + b_inst : std_logic; + opcode : unsigned(OpCode_Size-1 downto 0); + pc : unsigned(31 downto 0); + sp : unsigned(31 downto 0); + stk_a : unsigned(31 downto 0); + stk_b : unsigned(31 downto 0); + end record; + + type zpu_dbg_t is record + FMT_DATA_PRTMODE : std_logic_vector(1 downto 0); + FMT_PRE_SPACE : std_logic; + FMT_POST_SPACE : std_logic; + FMT_PRE_CR : std_logic; + FMT_POST_CRLF : std_logic; + FMT_SPLIT_DATA : std_logic_vector(1 downto 0); + DATA_BYTECNT : std_logic_vector(2 downto 0); + DATA2_BYTECNT : std_logic_vector(2 downto 0); + DATA3_BYTECNT : std_logic_vector(2 downto 0); + DATA4_BYTECNT : std_logic_vector(2 downto 0); + WRITE_DATA : std_logic; + WRITE_DATA2 : std_logic; + WRITE_DATA3 : std_logic; + WRITE_DATA4 : std_logic; + WRITE_OPCODE : std_logic; + WRITE_DECODED_OPCODE : std_logic; + WRITE_PC : std_logic; + WRITE_SP : std_logic; + WRITE_STACK_TOS : std_logic; + WRITE_STACK_NOS : std_logic; + DATA : std_logic_vector(63 downto 0); + DATA2 : std_logic_vector(63 downto 0); + DATA3 : std_logic_vector(63 downto 0); + DATA4 : std_logic_vector(63 downto 0); + OPCODE : std_logic_vector(OpCode_Size-1 downto 0); + DECODED_OPCODE : std_logic_vector(5 downto 0); + PC : std_logic_vector(ADDR_BIT_RANGE); + SP : std_logic_vector(ADDR_32BIT_RANGE); + STACK_TOS : std_logic_vector(WORD_32BIT_RANGE); + STACK_NOS : std_logic_vector(WORD_32BIT_RANGE); + end record; + + constant ZPU_DBG_T_INIT : zpu_dbg_t := ("00", '0', '0', '0', '0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0')); + constant ZPU_DBG_T_DONTCARE : zpu_dbg_t := ((others => DontCareValue), DontCareValue, DontCareValue, DontCareValue, DontCareValue, (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), DontCareValue, DontCareValue, DontCareValue, DontCareValue, DontCareValue, DontCareValue, DontCareValue, DontCareValue, DontCareValue, DontCareValue, (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue), (others => DontCareValue)); +end zpu_pkg; + +package body zpu_pkg is + + -- Helper to convert Boolean to integer. + -- + function bool_to_integer(level : boolean) return integer is + begin + if level then + return(1); + else + return(0); + end if; + end function; + +end package body zpu_pkg; diff --git a/zpu/cpu/zpu_uart_debug.vhd b/zpu/cpu/zpu_uart_debug.vhd new file mode 100644 index 0000000..9fcd4df --- /dev/null +++ b/zpu/cpu/zpu_uart_debug.vhd @@ -0,0 +1,516 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: zpu_uart_debug.vhd +-- Created: January 2019 +-- Author(s): Philip Smart +-- Description: An extension of the simplistic UART Tx, still fixed at 8N1 with configurable baud rate +-- but adding a debug serialisaztion FSM for output of ZPU runtime data. +-- Credits: Originally using the simplistic UART as a guide, which was written by the following +-- authors:- +-- Philippe Carton, philippe.carton2 libertysurf.fr +-- Juan Pablo Daniel Borgna, jpdborgna gmail.com +-- Salvador E. Tropea, salvador inti.gob.ar +-- Copyright: (c) 2019 Philip Smart +-- +-- History: January 2019 - Initial module written using the simplistic UART as a guide but +-- adding cache and debug serialisation FSM. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; + +-- Based on the simplistic UART, handles 8N1 RS232 Rx/Tx with independent programmable baud rate and selectable FIFO buffers. +entity zpu_uart_debug is + generic ( + TX_FIFO_BIT_DEPTH : integer := DEBUG_MAX_TX_FIFO_BITS; + DBG_FIFO_BIT_DEPTH : integer := DEBUG_MAX_FIFO_BITS; + CLK_FREQ : integer := 100000000; + TX_BAUD_RATE : integer := DEBUG_TX_BAUD_RATE -- Default baud rate + ); + port ( + -- CPU Interface + CLK : in std_logic; -- memory master clock + RESET : in std_logic; -- high active sync reset + DEBUG_DATA : zpu_dbg_t; + CS : in std_logic; -- Chip Select. + READY : out std_logic; -- Debug processor ready to process new command. + + -- Serial data + TXD : out std_logic + ); +end zpu_uart_debug; + +architecture rtl of zpu_uart_debug is + + type DebugStates is + ( + ST_IDLE, + ST_START, + ST_ADD_SEPERATOR, + ST_ADD_SPACE, + ST_PRECR, + ST_WRITE, + ST_WRITEHEX, + ST_WRITEBIN, + ST_SPLITSPACE, + ST_POSTSPACE, + ST_POSTCRLF, + ST_POSTLF, + ST_END + ); + + signal SM_STATE : DebugStates; + signal SM_BITCNT : integer range 0 to 7; + signal SM_BYTECNT : integer; + signal SM_WORDCNT : integer range 0 to 4; + signal SM_NIBBLECNT : std_logic; + signal SM_ADD_SEPERATOR : std_logic; + signal SM_ADD_SPACE : std_logic; + signal SM_SPLIT_DATA : std_logic_vector(1 downto 0); + + type TXSTATES is (idle, bits); + signal TX_STATE : TXSTATES := idle; + signal TX_BUFFER : std_logic_vector(17 downto 0); -- Transmit serialisation buffer. + signal TX_DATA : std_logic_vector(7 downto 0); -- Transmit holding register. + signal TX_DATA_LOADED : std_logic; -- Data loaded into transmit buffer. + signal TX_COUNTER : unsigned(15 downto 0); -- TX Clock generator counter. + signal TX_CLOCK : std_logic; -- TX Clock. + signal TX_LOAD : std_logic; -- Load byte into TX fifo. + signal TX_FIFO_FULL : std_logic; -- TX Fifo is full = 1. + signal TX_WRITE_DATA : std_logic_vector(7 downto 0); -- write data + signal SM_DATA_IN : std_logic_vector(63 downto 0); -- Buffered input data. + signal DBGREC : zpu_dbg_t; + + type ZPU_DBG_MEM_T is array (natural range 0 to ((2**DBG_FIFO_BIT_DEPTH)-1)) of zpu_dbg_t; + attribute ramstyle : string; + signal DBG_FIFO : ZPU_DBG_MEM_T; + attribute ramstyle of DBG_FIFO: signal is "M9K"; + signal DBG_FIFO_WR_ADDR : unsigned(DBG_FIFO_BIT_DEPTH-1 downto 0); + signal DBG_FIFO_RD_ADDR : unsigned(DBG_FIFO_BIT_DEPTH-1 downto 0); + + -- FIFO buffers. + --type TX_MEM_T is array (natural range 0 to ((2**TX_FIFO_BIT_DEPTH)-1)) of std_logic_vector(7 downto 0); + type TX_MEM_T is array (natural range 0 to ((2**TX_FIFO_BIT_DEPTH)-1)) of std_logic_vector(7 downto 0); + signal TX_FIFO : TX_MEM_T; + -- TX Fifo address pointers. + --signal TX_FIFO_WR_ADDR : unsigned(TX_FIFO_BIT_DEPTH-1 downto 0); + --signal TX_FIFO_RD_ADDR : unsigned(TX_FIFO_BIT_DEPTH-1 downto 0); + signal TX_FIFO_WR_ADDR : unsigned(TX_FIFO_BIT_DEPTH-1 downto 0); + signal TX_FIFO_RD_ADDR : unsigned(TX_FIFO_BIT_DEPTH-1 downto 0); + +begin + -- Debug processor. External input provides a 32bit input which is translated to [1-4]x8bit characters + -- or [1-4]byte Hex roeds and sent to the debug uart transmitter. + -- + process(CLK, RESET, DBG_FIFO_RD_ADDR, DBG_FIFO_WR_ADDR) + variable DBG_FULL_V : std_logic; + variable DBG_EMPTY_V : std_logic; + begin + if DBG_FIFO_RD_ADDR = DBG_FIFO_WR_ADDR then + DBG_EMPTY_V := '1'; + else + DBG_EMPTY_V := '0'; + end if; + + if DBG_FIFO_WR_ADDR = DBG_FIFO_RD_ADDR-1 then + DBG_FULL_V := '1'; + else + DBG_FULL_V := '0'; + end if; + + -- If we are to fill the last fifo slot, set ready to false so that no more writes occur (if cpu checking). + -- + if (DBG_FIFO_WR_ADDR - DBG_FIFO_RD_ADDR) > ((2**DBG_FIFO_BIT_DEPTH)-2) then + READY <= '0'; + elsif (DBG_FIFO_WR_ADDR - DBG_FIFO_RD_ADDR) < ((2**DBG_FIFO_BIT_DEPTH)-2) then + READY <= '1'; + else + READY <= '0'; + end if; + + if RESET='1' then + TX_LOAD <= '0'; + SM_STATE <= ST_IDLE; + SM_BYTECNT <= 0; + SM_WORDCNT <= 0; + SM_NIBBLECNT <= '1'; + SM_ADD_SPACE <= '0'; + SM_ADD_SEPERATOR <= '0'; + DBG_FIFO_WR_ADDR <= (others => '0'); + DBG_FIFO_RD_ADDR <= (others => '0'); + READY <= '1'; + + elsif rising_edge(CLK) then + + -- If cpu is writing a record to be processed, store in fifo if not full, otherwise wait. + -- + if CS = '1' then + -- Store data in FIFO if not full. + -- + if DBG_FULL_V = '0' then + DBG_FIFO(to_integer(DBG_FIFO_WR_ADDR)) <= DEBUG_DATA; + DBG_FIFO_WR_ADDR <= DBG_FIFO_WR_ADDR + 1; + end if; + end if; + + -- When idle, if we have a record in the fifo, extract top record and process. + -- + if SM_STATE = ST_IDLE and DBG_EMPTY_V = '0' then + DBGREC <= DBG_FIFO(to_integer(DBG_FIFO_RD_ADDR)); + DBG_FIFO_RD_ADDR <= DBG_FIFO_RD_ADDR + 1; + SM_STATE <= ST_START; + SM_SPLIT_DATA <= "00"; + end if; + + -- Only add characters if the TX Fifo has space, otherwise suspend. + -- + TX_LOAD <= '0'; + if TX_FIFO_FULL = '0' then + case SM_STATE is + when ST_IDLE => + + when ST_START => + if SM_ADD_SEPERATOR = '1' then + SM_STATE <= ST_ADD_SEPERATOR; + SM_ADD_SEPERATOR <= '0'; + elsif SM_ADD_SPACE = '1' then + SM_STATE <= ST_ADD_SPACE; + SM_ADD_SPACE <= '0'; + elsif DBGREC.FMT_PRE_SPACE = '1' then + SM_STATE <= ST_ADD_SPACE; + DBGREC.FMT_PRE_SPACE <= '0'; + elsif DBGREC.FMT_PRE_CR = '1' then + SM_STATE <= ST_PRECR; + DBGREC.FMT_PRE_CR <= '0'; + elsif DBGREC.WRITE_PC = '1' then + DBGREC.WRITE_PC <= '0'; + SM_BYTECNT <= 4; + SM_DATA_IN(63 downto 32) <= std_logic_vector(to_unsigned(to_integer(unsigned(DBGREC.PC)), 32)); + SM_ADD_SPACE <= '1'; + SM_STATE <= ST_WRITEHEX; + elsif DBGREC.WRITE_SP = '1' then + DBGREC.WRITE_SP <= '0'; + SM_BYTECNT <= 4; + SM_DATA_IN(63 downto 32) <= std_logic_vector(to_unsigned(to_integer(unsigned(DBGREC.SP)), 30)) & "00"; + SM_ADD_SPACE <= '1'; + SM_STATE <= ST_WRITEHEX; + elsif DBGREC.WRITE_STACK_TOS = '1' then + DBGREC.WRITE_STACK_TOS <= '0'; + SM_BYTECNT <= 4; + SM_DATA_IN(63 downto 32) <= DBGREC.STACK_TOS; + SM_ADD_SPACE <= '1'; + SM_STATE <= ST_WRITEHEX; + elsif DBGREC.WRITE_STACK_NOS = '1' then + DBGREC.WRITE_STACK_NOS <= '0'; + SM_BYTECNT <= 4; + SM_DATA_IN(63 downto 32) <= DBGREC.STACK_NOS; + SM_ADD_SPACE <= '1'; + SM_STATE <= ST_WRITEHEX; + elsif DBGREC.WRITE_OPCODE = '1' then + DBGREC.WRITE_OPCODE <= '0'; + SM_BYTECNT <= 1; + SM_DATA_IN(63 downto 56) <= DBGREC.OPCODE; + SM_ADD_SEPERATOR <= '1'; + SM_STATE <= ST_WRITEHEX; + elsif DBGREC.WRITE_DECODED_OPCODE = '1' then + DBGREC.WRITE_DECODED_OPCODE <= '0'; + SM_BYTECNT <= 1; + SM_DATA_IN(63 downto 56) <= "00" & DBGREC.DECODED_OPCODE; + SM_ADD_SPACE <= '1'; + SM_STATE <= ST_WRITEHEX; + elsif DBGREC.FMT_SPLIT_DATA /= "00" then + SM_SPLIT_DATA <= DBGREC.FMT_SPLIT_DATA; + DBGREC.FMT_SPLIT_DATA <= "00"; + elsif DBGREC.WRITE_DATA = '1' then + DBGREC.WRITE_DATA <= '0'; + SM_BITCNT <= 7; + SM_BYTECNT <= to_integer(unsigned(DBGREC.DATA_BYTECNT)) + 1; + SM_WORDCNT <= 0; + SM_DATA_IN <= DBGREC.DATA; + if DBGREC.FMT_DATA_PRTMODE = "10" then + SM_STATE <= ST_WRITEBIN; + elsif DBGREC.FMT_DATA_PRTMODE = "01" then + SM_STATE <= ST_WRITEHEX; + else + SM_STATE <= ST_WRITE; + end if; + elsif DBGREC.WRITE_DATA2 = '1' then + DBGREC.WRITE_DATA2 <= '0'; + SM_BYTECNT <= to_integer(unsigned(DBGREC.DATA2_BYTECNT)) + 1; + SM_BITCNT <= 7; + SM_WORDCNT <= 0; + SM_DATA_IN <= DBGREC.DATA2; + if DBGREC.FMT_DATA_PRTMODE = "10" then + SM_STATE <= ST_WRITEBIN; + elsif DBGREC.FMT_DATA_PRTMODE = "01" then + SM_STATE <= ST_WRITEHEX; + else + SM_STATE <= ST_WRITE; + end if; + elsif DBGREC.WRITE_DATA3 = '1' then + DBGREC.WRITE_DATA3 <= '0'; + SM_BYTECNT <= to_integer(unsigned(DBGREC.DATA3_BYTECNT)) + 1; + SM_BITCNT <= 7; + SM_WORDCNT <= 0; + SM_DATA_IN <= DBGREC.DATA3; + if DBGREC.FMT_DATA_PRTMODE = "10" then + SM_STATE <= ST_WRITEBIN; + elsif DBGREC.FMT_DATA_PRTMODE = "01" then + SM_STATE <= ST_WRITEHEX; + else + SM_STATE <= ST_WRITE; + end if; + elsif DBGREC.WRITE_DATA4 = '1' then + DBGREC.WRITE_DATA4 <= '0'; + SM_BYTECNT <= to_integer(unsigned(DBGREC.DATA4_BYTECNT)) + 1; + SM_BITCNT <= 7; + SM_WORDCNT <= 0; + SM_DATA_IN <= DBGREC.DATA4; + if DBGREC.FMT_DATA_PRTMODE = "10" then + SM_STATE <= ST_WRITEBIN; + elsif DBGREC.FMT_DATA_PRTMODE = "01" then + SM_STATE <= ST_WRITEHEX; + else + SM_STATE <= ST_WRITE; + end if; + else + SM_STATE <= ST_END; + end if; + + when ST_ADD_SPACE => + TX_WRITE_DATA(7 downto 0) <= X"20"; + TX_LOAD <= '1'; + SM_STATE <= ST_START; + + when ST_ADD_SEPERATOR => + TX_WRITE_DATA(7 downto 0) <= X"2E"; + TX_LOAD <= '1'; + SM_STATE <= ST_START; + + when ST_PRECR => + TX_WRITE_DATA(7 downto 0) <= X"0D"; + TX_LOAD <= '1'; + SM_STATE <= ST_START; + + when ST_WRITE => + if SM_BYTECNT > 0 then + TX_WRITE_DATA(7 downto 0) <= SM_DATA_IN(63 downto 56); + TX_LOAD <= '1'; + SM_DATA_IN(63 downto 8) <= SM_DATA_IN(55 downto 0); + SM_BYTECNT <= SM_BYTECNT - 1; + else + SM_STATE <= ST_START; + end if; + + when ST_WRITEHEX => + if SM_BYTECNT > 0 then + if unsigned(SM_DATA_IN(63 downto 60)) < 10 then + TX_WRITE_DATA(7 downto 0) <= std_logic_vector(unsigned(SM_DATA_IN(63 downto 60)) + X"30"); + else + TX_WRITE_DATA(7 downto 0) <= std_logic_vector(unsigned(SM_DATA_IN(63 downto 60)) + X"57"); + end if; + TX_LOAD <= '1'; + SM_DATA_IN(63 downto 4) <= SM_DATA_IN(59 downto 0); + if SM_NIBBLECNT = '0' then + SM_BYTECNT <= SM_BYTECNT - 1; + if SM_SPLIT_DATA = "01" and SM_WORDCNT = 0 then + SM_STATE <= ST_SPLITSPACE; + SM_WORDCNT <= 0; + elsif SM_SPLIT_DATA = "10" and SM_WORDCNT = 1 then + SM_STATE <= ST_SPLITSPACE; + SM_WORDCNT <= 0; + elsif SM_SPLIT_DATA = "11" and SM_WORDCNT > 2 then + SM_STATE <= ST_SPLITSPACE; + SM_WORDCNT <= 0; + else + SM_WORDCNT <= SM_WORDCNT + 1; + end if; + end if; + SM_NIBBLECNT <= not SM_NIBBLECNT; + else + SM_STATE <= ST_START; + end if; + + when ST_WRITEBIN => + if SM_BYTECNT > 0 then + if SM_DATA_IN(63) = '1' then + TX_WRITE_DATA(7 downto 0) <= X"31"; + else + TX_WRITE_DATA(7 downto 0) <= X"30"; + end if; + TX_LOAD <= '1'; + SM_DATA_IN(63 downto 1) <= SM_DATA_IN(62 downto 0); + if SM_BITCNT > 0 then + SM_BITCNT <= SM_BITCNT-1; + else + SM_BITCNT <= 7; + SM_BYTECNT <= SM_BYTECNT - 1; + end if; + else + SM_STATE <= ST_START; + end if; + + when ST_SPLITSPACE => + TX_WRITE_DATA(7 downto 0) <= X"20"; + TX_LOAD <= '1'; + SM_STATE <= ST_WRITEHEX; + + when ST_POSTSPACE => + TX_WRITE_DATA(7 downto 0) <= X"20"; + TX_LOAD <= '1'; + SM_STATE <= ST_END; + + when ST_POSTCRLF => + TX_WRITE_DATA(7 downto 0) <= X"0D"; + TX_LOAD <= '1'; + SM_STATE <= ST_POSTLF; + + when ST_POSTLF => + TX_WRITE_DATA(7 downto 0) <= X"0A"; + TX_LOAD <= '1'; + SM_STATE <= ST_END; + + when ST_END => + if DBGREC.FMT_POST_SPACE = '1' then + SM_STATE <= ST_POSTSPACE; + DBGREC.FMT_POST_SPACE <= '0'; + elsif DBGREC.FMT_POST_CRLF = '1' then + SM_STATE <= ST_POSTCRLF; + DBGREC.FMT_POST_CRLF <= '0'; + else + SM_STATE <= ST_IDLE; + end if; + end case; + end if; + end if; + end process; + + -- Tx Clock generation + -- Very simple - the counter is reset when either it reaches zero or + -- the Tx is idle, and counts down once per system clock tick. + process(CLK, RESET) + begin + if RESET='1' then + TX_CLOCK <= '0'; + TX_COUNTER <= to_unsigned(CLK_FREQ/TX_BAUD_RATE, TX_COUNTER'length); + elsif rising_edge(CLK) then + TX_CLOCK <= '0'; + + if TX_STATE = idle then + TX_COUNTER <= to_unsigned(CLK_FREQ/TX_BAUD_RATE, TX_COUNTER'length); + else + TX_COUNTER <= TX_COUNTER-1; + if TX_COUNTER = 0 then + TX_CLOCK <= '1'; + TX_COUNTER <= to_unsigned(CLK_FREQ/TX_BAUD_RATE, TX_COUNTER'length); + end if; + end if; + end if; + end process; + + + -- Data Tx + -- Similarly to the Rx routine, we use a shift register larger than the word, + -- which also includes a marker bit. This time the marker bit is a zero, and when + -- the zero reaches bit 8, we know we've transmitted the entire word plus one stop bit. + process(clk,RESET,TX_STATE,TX_FIFO_RD_ADDR,TX_FIFO_WR_ADDR) + variable TX_FULL_V : std_logic; + variable TX_EMPTY_V : std_logic; + variable DATA_HEX_LSB : std_logic_vector(7 downto 0); + variable DATA_HEX_MSB : std_logic_vector(7 downto 0); + begin + if TX_FIFO_RD_ADDR=TX_FIFO_WR_ADDR then + TX_EMPTY_V := '1'; + else + TX_EMPTY_V := '0'; + end if; + + if TX_FIFO_WR_ADDR = TX_FIFO_RD_ADDR-1 then + TX_FULL_V := '1'; + else + TX_FULL_V := '0'; + end if; + + -- Full is set when we are almost full or an unspecified state and reset when the data in the buffer is 256 bytes less than + -- maximum. + if (TX_FIFO_WR_ADDR - TX_FIFO_RD_ADDR) > ((2**TX_FIFO_BIT_DEPTH)-16) then + TX_FIFO_FULL <= '1'; + elsif (TX_FIFO_WR_ADDR - TX_FIFO_RD_ADDR) < ((2**TX_FIFO_BIT_DEPTH)-256) then + TX_FIFO_FULL <= '0'; + else + TX_FIFO_FULL <= '1'; + end if; + + if RESET='1' then + TX_STATE <= idle; + TX_DATA_LOADED <= '0'; + TXD <= '1'; + TX_FIFO_FULL <= '0'; + TX_FIFO_WR_ADDR <= (others => '0'); + TX_FIFO_RD_ADDR <= (others => '0'); + + elsif rising_edge(clk) then + + -- If CPU writes data, load into FIFO. + -- + if TX_LOAD = '1' then + + -- Store data in FIFO if not full. + -- + if TX_FULL_V = '0' then + TX_FIFO(to_integer(TX_FIFO_WR_ADDR)) <= TX_WRITE_DATA(7 downto 0); + TX_FIFO_WR_ADDR <= TX_FIFO_WR_ADDR + 1; + end if; + end if; + + -- If FIFO enabled, pop the next byte into the TX holding register. + if TX_DATA_LOADED = '0' and TX_EMPTY_V = '0' then + TX_DATA <= TX_FIFO(to_integer(TX_FIFO_RD_ADDR)); + TX_FIFO_RD_ADDR <= TX_FIFO_RD_ADDR + 1; + TX_DATA_LOADED <= '1'; + end if; + + -- TX state machine, serialise the TX buffer. + case TX_STATE is + when idle => + -- If data loaded into the TX holding register and we are at idle (ie last byte transmitted), + -- load into the transmit buffer and commence transmission. + -- + if TX_DATA_LOADED = '1' then + TX_BUFFER <= "0111111111" & TX_DATA; -- marker bit + data + TX_STATE <= bits; + TXD <= '0'; -- Start bit + TX_DATA_LOADED <= '0'; + end if; + when bits => + if TX_CLOCK='1' then + TXD <= TX_BUFFER(0); + TX_BUFFER <= '0' & TX_BUFFER(17 downto 1); + + if TX_BUFFER(8) = '0' then -- Marker bit has reached bit 8 + TX_STATE <= idle; + end if; + end if; + when others => + TX_STATE <= idle; + end case; + end if; + end process; +end architecture; diff --git a/zpu/devices/WishBone/I2C/i2c_master_bit_ctrl.vhd b/zpu/devices/WishBone/I2C/i2c_master_bit_ctrl.vhd new file mode 100644 index 0000000..a095fde --- /dev/null +++ b/zpu/devices/WishBone/I2C/i2c_master_bit_ctrl.vhd @@ -0,0 +1,576 @@ +--------------------------------------------------------------------- +---- ---- +---- WISHBONE revB2 I2C Master Core; bit-controller ---- +---- ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2000 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- CVS Log +-- +-- $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $ +-- +-- $Date: 2009-02-04 20:17:34 $ +-- $Revision: 1.17 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- Revision 1.16 2009/01/20 20:40:36 rherveille +-- Fixed type iscl_oen instead of scl_oen +-- +-- Revision 1.15 2009/01/20 10:34:51 rherveille +-- Added SCL clock synchronization logic +-- Fixed slave_wait signal generation +-- +-- Revision 1.14 2006/10/11 12:10:13 rherveille +-- Added missing semicolons ';' on endif +-- +-- Revision 1.13 2006/10/06 10:48:24 rherveille +-- fixed short scl high pulse after clock stretch +-- +-- Revision 1.12 2004/05/07 11:53:31 rherveille +-- Fixed previous fix :) Made a variable vs signal mistake. +-- +-- Revision 1.11 2004/05/07 11:04:00 rherveille +-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. +-- +-- Revision 1.10 2004/02/27 07:49:43 rherveille +-- Fixed a bug in the arbitration-lost signal generation. VHDL version only. +-- +-- Revision 1.9 2003/08/12 14:48:37 rherveille +-- Forgot an 'end if' :-/ +-- +-- Revision 1.8 2003/08/09 07:01:13 rherveille +-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +-- Fixed a potential bug in the byte controller's host-acknowledge generation. +-- +-- Revision 1.7 2003/02/05 00:06:02 rherveille +-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. +-- +-- Revision 1.6 2003/02/01 02:03:06 rherveille +-- Fixed a few 'arbitration lost' bugs. VHDL version only. +-- +-- Revision 1.5 2002/12/26 16:05:47 rherveille +-- Core is now a Multimaster I2C controller. +-- +-- Revision 1.4 2002/11/30 22:24:37 rherveille +-- Cleaned up code +-- +-- Revision 1.3 2002/10/30 18:09:53 rherveille +-- Fixed some reported minor start/stop generation timing issuess. +-- +-- Revision 1.2 2002/06/15 07:37:04 rherveille +-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. +-- +-- Revision 1.1 2001/11/05 12:02:33 rherveille +-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. +-- Code updated, is now up-to-date to doc. rev.0.4. +-- Added headers. +-- + + +-- +------------------------------------- +-- Bit controller section +------------------------------------ +-- +-- Translate simple commands into SCL/SDA transitions +-- Each command has 5 states, A/B/C/D/idle +-- +-- start: SCL ~~~~~~~~~~~~~~\____ +-- SDA XX/~~~~~~~\______ +-- x | A | B | C | D | i +-- +-- repstart SCL ______/~~~~~~~\___ +-- SDA __/~~~~~~~\______ +-- x | A | B | C | D | i +-- +-- stop SCL _______/~~~~~~~~~~~ +-- SDA ==\___________/~~~~~ +-- x | A | B | C | D | i +-- +--- write SCL ______/~~~~~~~\____ +-- SDA XXX===============XX +-- x | A | B | C | D | i +-- +--- read SCL ______/~~~~~~~\____ +-- SDA XXXXXXX=XXXXXXXXXXX +-- x | A | B | C | D | i +-- + +-- Timing: Normal mode Fast mode +----------------------------------------------------------------- +-- Fscl 100KHz 400KHz +-- Th_scl 4.0us 0.6us High period of SCL +-- Tl_scl 4.7us 1.3us Low period of SCL +-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition +-- Tsu:sto 4.0us 0.6us setup time for a stop conditon +-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2c_master_bit_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; + nReset : in std_logic; + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- clock prescale value + + cmd : in std_logic_vector(3 downto 0); + cmd_ack : out std_logic; -- command completed + busy : out std_logic; -- i2c bus busy + al : out std_logic; -- arbitration lost + + din : in std_logic; + dout : out std_logic; + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); +end entity i2c_master_bit_ctrl; + +architecture structural of i2c_master_bit_ctrl is + constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; + constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; + constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; + constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; + constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; + + type states is (idle, start_a, start_b, start_c, start_d, start_e, + stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); + signal c_state : states; + + signal iscl_oen, isda_oen : std_logic; -- internal I2C lines + signal sda_chk : std_logic; -- check SDA status (multi-master arbitration) + signal dscl_oen : std_logic; -- delayed scl_oen signals + signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs + signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA + signal clk_en : std_logic; -- statemachine clock enable + signal scl_sync, slave_wait : std_logic; -- clock generation signals + signal ial : std_logic; -- internal arbitration lost signal + signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis) + +begin + -- whenever the slave is not ready it can delay the cycle by pulling SCL low + -- delay scl_oen + process (clk, nReset) + begin + if (nReset = '0') then + dscl_oen <= '0'; + elsif (clk'event and clk = '1') then + dscl_oen <= iscl_oen; + end if; + end process; + + -- slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low + -- slave_wait remains asserted until the slave releases SCL + process (clk, nReset) + begin + if (nReset = '0') then + slave_wait <= '0'; + elsif (clk'event and clk = '1') then + slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL); + end if; + end process; + + -- master drives SCL high, but another master pulls it low + -- master start counting down its low cycle now (clock synchronization) + scl_sync <= dSCL and not sSCL and iscl_oen; + + -- generate clk enable signal + gen_clken: process(clk, nReset) + begin + if (nReset = '0') then + cnt <= (others => '0'); + clk_en <= '1'; + elsif (clk'event and clk = '1') then + if ((rst = '1') or (cnt = 0) or (ena = '0') or (scl_sync = '1')) then + cnt <= clk_cnt; + clk_en <= '1'; + elsif (slave_wait = '1') then + cnt <= cnt; + clk_en <= '0'; + else + cnt <= cnt -1; + clk_en <= '0'; + end if; + end if; + end process gen_clken; + + + -- generate bus status controller + bus_status_ctrl: block + signal cSCL, cSDA : std_logic_vector( 1 downto 0); -- capture SDA and SCL + signal fSCL, fSDA : std_logic_vector( 2 downto 0); -- filter inputs for SCL and SDA + signal filter_cnt : unsigned(13 downto 0); -- clock divider for filter + signal sta_condition : std_logic; -- start detected + signal sto_condition : std_logic; -- stop detected + signal cmd_stop : std_logic; -- STOP command + signal ibusy : std_logic; -- internal busy signal + begin + -- capture SCL and SDA + capture_scl_sda: process(clk, nReset) + begin + if (nReset = '0') then + cSCL <= "00"; + cSDA <= "00"; + elsif (clk'event and clk = '1') then + if (rst = '1') then + cSCL <= "00"; + cSDA <= "00"; + else + cSCL <= (cSCL(0) & scl_i); + cSDA <= (cSDA(0) & sda_i); + end if; + end if; + end process capture_scl_sda; + + -- filter SCL and SDA; (attempt to) remove glitches + filter_divider: process(clk, nReset) + begin + if (nReset = '0') then + filter_cnt <= (others => '0'); + elsif (clk'event and clk = '1') then + if ( (rst = '1') or (ena = '0') ) then + filter_cnt <= (others => '0'); + elsif (filter_cnt = 0) then + filter_cnt <= clk_cnt(15 downto 2); + else + filter_cnt <= filter_cnt -1; + end if; + end if; + end process filter_divider; + + filter_scl_sda: process(clk, nReset) + begin + if (nReset = '0') then + fSCL <= (others => '1'); + fSDA <= (others => '1'); + elsif (clk'event and clk = '1') then + if (rst = '1') then + fSCL <= (others => '1'); + fSDA <= (others => '1'); + elsif (filter_cnt = 0) then + fSCL <= (fSCL(1 downto 0) & cSCL(1)); + fSDA <= (fSDA(1 downto 0) & cSDA(1)); + end if; + end if; + end process filter_scl_sda; + + -- generate filtered SCL and SDA signals + scl_sda: process(clk, nReset) + begin + if (nReset = '0') then + sSCL <= '1'; + sSDA <= '1'; + + dSCL <= '1'; + dSDA <= '1'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + sSCL <= '1'; + sSDA <= '1'; + + dSCL <= '1'; + dSDA <= '1'; + else + sSCL <= (fSCL(2) and fSCL(1)) or + (fSCL(2) and fSCL(0)) or + (fSCL(1) and fSCL(0)); + sSDA <= (fSDA(2) and fSDA(1)) or + (fSDA(2) and fSDA(0)) or + (fSDA(1) and fSDA(0)); + + dSCL <= sSCL; + dSDA <= sSDA; + end if; + end if; + end process scl_sda; + + + -- detect start condition => detect falling edge on SDA while SCL is high + -- detect stop condition => detect rising edge on SDA while SCL is high + detect_sta_sto: process(clk, nReset) + begin + if (nReset = '0') then + sta_condition <= '0'; + sto_condition <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + sta_condition <= '0'; + sto_condition <= '0'; + else + sta_condition <= (not sSDA and dSDA) and sSCL; + sto_condition <= (sSDA and not dSDA) and sSCL; + end if; + end if; + end process detect_sta_sto; + + + -- generate i2c-bus busy signal + gen_busy: process(clk, nReset) + begin + if (nReset = '0') then + ibusy <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + ibusy <= '0'; + else + ibusy <= (sta_condition or ibusy) and not sto_condition; + end if; + end if; + end process gen_busy; + busy <= ibusy; + + + -- generate arbitration lost signal + -- aribitration lost when: + -- 1) master drives SDA high, but the i2c bus is low + -- 2) stop detected while not requested (detect during 'idle' state) + gen_al: process(clk, nReset) + begin + if (nReset = '0') then + cmd_stop <= '0'; + ial <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + cmd_stop <= '0'; + ial <= '0'; + else + if (clk_en = '1') then + if (cmd = I2C_CMD_STOP) then + cmd_stop <= '1'; + else + cmd_stop <= '0'; + end if; + end if; + + if (c_state = idle) then + ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop); + else + ial <= (sda_chk and not sSDA and isda_oen); + end if; + end if; + end if; + end process gen_al; + al <= ial; + + + -- generate dout signal, store dout on rising edge of SCL + gen_dout: process(clk, nReset) + begin + if (nReset = '0') then + dout <= '0'; + elsif (clk'event and clk = '1') then + if (sSCL = '1' and dSCL = '0') then + dout <= sSDA; + end if; + end if; + end process gen_dout; + end block bus_status_ctrl; + + + -- generate statemachine + nxt_state_decoder : process (clk, nReset) + begin + if (nReset = '0') then + c_state <= idle; + cmd_ack <= '0'; + iscl_oen <= '1'; + isda_oen <= '1'; + sda_chk <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1' or ial = '1') then + c_state <= idle; + cmd_ack <= '0'; + iscl_oen <= '1'; + isda_oen <= '1'; + sda_chk <= '0'; + else + cmd_ack <= '0'; -- default no acknowledge + + if (clk_en = '1') then + case (c_state) is + -- idle + when idle => + case cmd is + when I2C_CMD_START => c_state <= start_a; + when I2C_CMD_STOP => c_state <= stop_a; + when I2C_CMD_WRITE => c_state <= wr_a; + when I2C_CMD_READ => c_state <= rd_a; + when others => c_state <= idle; -- NOP command + end case; + + iscl_oen <= iscl_oen; -- keep SCL in same state + isda_oen <= isda_oen; -- keep SDA in same state + sda_chk <= '0'; -- don't check SDA + + -- start + when start_a => + c_state <= start_b; + iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start) + isda_oen <= '1'; -- set SDA high + sda_chk <= '0'; -- don't check SDA + + when start_b => + c_state <= start_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= '1'; -- keep SDA high + sda_chk <= '0'; -- don't check SDA + + when start_c => + c_state <= start_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '0'; -- set SDA low + sda_chk <= '0'; -- don't check SDA + + when start_d => + c_state <= start_e; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + when start_e => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '0'; -- set SCL low + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + -- stop + when stop_a => + c_state <= stop_b; + iscl_oen <= '0'; -- keep SCL low + isda_oen <= '0'; -- set SDA low + sda_chk <= '0'; -- don't check SDA + + when stop_b => + c_state <= stop_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + when stop_c => + c_state <= stop_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + when stop_d => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '1'; -- set SDA high + sda_chk <= '0'; -- don't check SDA + + -- read + when rd_a => + c_state <= rd_b; + iscl_oen <= '0'; -- keep SCL low + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + when rd_b => + c_state <= rd_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + when rd_c => + c_state <= rd_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + when rd_d => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '0'; -- set SCL low + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + -- write + when wr_a => + c_state <= wr_b; + iscl_oen <= '0'; -- keep SCL low + isda_oen <= din; -- set SDA + sda_chk <= '0'; -- don't check SDA (SCL low) + + when wr_b => + c_state <= wr_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= din; -- keep SDA + sda_chk <= '0'; -- don't check SDA yet + -- Allow some more time for SDA and SCL to settle + + when wr_c => + c_state <= wr_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= din; -- keep SDA + sda_chk <= '1'; -- check SDA + + when wr_d => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '0'; -- set SCL low + isda_oen <= din; -- keep SDA + sda_chk <= '0'; -- don't check SDA (SCL low) + + when others => + + end case; + end if; + end if; + end if; + end process nxt_state_decoder; + + + -- assign outputs + scl_o <= '0'; + scl_oen <= iscl_oen; + sda_o <= '0'; + sda_oen <= isda_oen; +end architecture structural; + diff --git a/zpu/devices/WishBone/I2C/i2c_master_byte_ctrl.vhd b/zpu/devices/WishBone/I2C/i2c_master_byte_ctrl.vhd new file mode 100644 index 0000000..2be7d0c --- /dev/null +++ b/zpu/devices/WishBone/I2C/i2c_master_byte_ctrl.vhd @@ -0,0 +1,367 @@ +--------------------------------------------------------------------- +---- ---- +---- WISHBONE revB2 compl. I2C Master Core; byte-controller ---- +---- ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2000 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- CVS Log +-- +-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004-02-18 11:41:48 rherveille Exp $ +-- +-- $Date: 2004-02-18 11:41:48 $ +-- $Revision: 1.5 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- Revision 1.4 2003/08/09 07:01:13 rherveille +-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +-- Fixed a potential bug in the byte controller's host-acknowledge generation. +-- +-- Revision 1.3 2002/12/26 16:05:47 rherveille +-- Core is now a Multimaster I2C controller. +-- +-- Revision 1.2 2002/11/30 22:24:37 rherveille +-- Cleaned up code +-- +-- Revision 1.1 2001/11/05 12:02:33 rherveille +-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. +-- Code updated, is now up-to-date to doc. rev.0.4. +-- Added headers. +-- + + + + +-- +------------------------------------------ +-- Byte controller section +------------------------------------------ +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2c_master_byte_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) + nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- 4x SCL + + -- input signals + start, + stop, + read, + write, + ack_in : std_logic; + din : in std_logic_vector(7 downto 0); + + -- output signals + cmd_ack : out std_logic; -- command done + ack_out : out std_logic; + i2c_busy : out std_logic; -- arbitration lost + i2c_al : out std_logic; -- i2c bus busy + dout : out std_logic_vector(7 downto 0); + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); +end entity i2c_master_byte_ctrl; + +architecture structural of i2c_master_byte_ctrl is + component i2c_master_bit_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; + nReset : in std_logic; + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- clock prescale value + + cmd : in std_logic_vector(3 downto 0); + cmd_ack : out std_logic; -- command done + busy : out std_logic; -- i2c bus busy + al : out std_logic; -- arbitration lost + + din : in std_logic; + dout : out std_logic; + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); + end component i2c_master_bit_ctrl; + + -- commands for bit_controller block + constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; + constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; + constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; + constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; + constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; + + -- signals for bit_controller + signal core_cmd : std_logic_vector(3 downto 0); + signal core_ack, core_txd, core_rxd : std_logic; + signal al : std_logic; + + -- signals for shift register + signal sr : std_logic_vector(7 downto 0); -- 8bit shift register + signal shift, ld : std_logic; + + -- signals for state machine + signal go, host_ack : std_logic; + signal dcnt : unsigned(2 downto 0); -- data counter + signal cnt_done : std_logic; + +begin + -- hookup bit_controller + bit_ctrl: i2c_master_bit_ctrl port map( + clk => clk, + rst => rst, + nReset => nReset, + ena => ena, + clk_cnt => clk_cnt, + cmd => core_cmd, + cmd_ack => core_ack, + busy => i2c_busy, + al => al, + din => core_txd, + dout => core_rxd, + scl_i => scl_i, + scl_o => scl_o, + scl_oen => scl_oen, + sda_i => sda_i, + sda_o => sda_o, + sda_oen => sda_oen + ); + i2c_al <= al; + + -- generate host-command-acknowledge + cmd_ack <= host_ack; + + -- generate go-signal + go <= (read or write or stop) and not host_ack; + + -- assign Dout output to shift-register + dout <= sr; + + -- generate shift register + shift_register: process(clk, nReset) + begin + if (nReset = '0') then + sr <= (others => '0'); + elsif (clk'event and clk = '1') then + if (rst = '1') then + sr <= (others => '0'); + elsif (ld = '1') then + sr <= din; + elsif (shift = '1') then + sr <= (sr(6 downto 0) & core_rxd); + end if; + end if; + end process shift_register; + + -- generate data-counter + data_cnt: process(clk, nReset) + begin + if (nReset = '0') then + dcnt <= (others => '0'); + elsif (clk'event and clk = '1') then + if (rst = '1') then + dcnt <= (others => '0'); + elsif (ld = '1') then + dcnt <= (others => '1'); -- load counter with 7 + elsif (shift = '1') then + dcnt <= dcnt -1; + end if; + end if; + end process data_cnt; + + cnt_done <= '1' when (dcnt = 0) else '0'; + + -- + -- state machine + -- + statemachine : block + type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); + signal c_state : states; + begin + -- + -- command interpreter, translate complex commands into simpler I2C commands + -- + nxt_state_decoder: process(clk, nReset) + begin + if (nReset = '0') then + core_cmd <= I2C_CMD_NOP; + core_txd <= '0'; + shift <= '0'; + ld <= '0'; + host_ack <= '0'; + c_state <= st_idle; + ack_out <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1' or al = '1') then + core_cmd <= I2C_CMD_NOP; + core_txd <= '0'; + shift <= '0'; + ld <= '0'; + host_ack <= '0'; + c_state <= st_idle; + ack_out <= '0'; + else + -- initialy reset all signal + core_txd <= sr(7); + shift <= '0'; + ld <= '0'; + host_ack <= '0'; + + case c_state is + when st_idle => + if (go = '1') then + if (start = '1') then + c_state <= st_start; + core_cmd <= I2C_CMD_START; + elsif (read = '1') then + c_state <= st_read; + core_cmd <= I2C_CMD_READ; + elsif (write = '1') then + c_state <= st_write; + core_cmd <= I2C_CMD_WRITE; + else -- stop + c_state <= st_stop; + core_cmd <= I2C_CMD_STOP; + end if; + + ld <= '1'; + end if; + + when st_start => + if (core_ack = '1') then + if (read = '1') then + c_state <= st_read; + core_cmd <= I2C_CMD_READ; + else + c_state <= st_write; + core_cmd <= I2C_CMD_WRITE; + end if; + + ld <= '1'; + end if; + + when st_write => + if (core_ack = '1') then + if (cnt_done = '1') then + c_state <= st_ack; + core_cmd <= I2C_CMD_READ; + else + c_state <= st_write; -- stay in same state + core_cmd <= I2C_CMD_WRITE; -- write next bit + shift <= '1'; + end if; + end if; + + when st_read => + if (core_ack = '1') then + if (cnt_done = '1') then + c_state <= st_ack; + core_cmd <= I2C_CMD_WRITE; + else + c_state <= st_read; -- stay in same state + core_cmd <= I2C_CMD_READ; -- read next bit + end if; + + shift <= '1'; + core_txd <= ack_in; + end if; + + when st_ack => + if (core_ack = '1') then + -- check for stop; Should a STOP command be generated ? + if (stop = '1') then + c_state <= st_stop; + core_cmd <= I2C_CMD_STOP; + else + c_state <= st_idle; + core_cmd <= I2C_CMD_NOP; + + -- generate command acknowledge signal + host_ack <= '1'; + end if; + + -- assign ack_out output to core_rxd (contains last received bit) + ack_out <= core_rxd; + + core_txd <= '1'; + else + core_txd <= ack_in; + end if; + + when st_stop => + if (core_ack = '1') then + c_state <= st_idle; + core_cmd <= I2C_CMD_NOP; + + -- generate command acknowledge signal + host_ack <= '1'; + end if; + + when others => -- illegal states + c_state <= st_idle; + core_cmd <= I2C_CMD_NOP; + report ("Byte controller entered illegal state."); + + end case; + + end if; + end if; + end process nxt_state_decoder; + + end block statemachine; + +end architecture structural; + diff --git a/zpu/devices/WishBone/I2C/i2c_master_top.vhd b/zpu/devices/WishBone/I2C/i2c_master_top.vhd new file mode 100644 index 0000000..99e6ee7 --- /dev/null +++ b/zpu/devices/WishBone/I2C/i2c_master_top.vhd @@ -0,0 +1,362 @@ +--------------------------------------------------------------------- +---- ---- +---- WISHBONE revB2 compl. I2C Master Core; top level ---- +---- ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2000 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- CVS Log +-- +-- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $ +-- +-- $Date: 2009-01-20 10:38:45 $ +-- $Revision: 1.8 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- Revision 1.7 2004/03/14 10:17:03 rherveille +-- Fixed simulation issue when writing to CR register +-- +-- Revision 1.6 2003/08/09 07:01:13 rherveille +-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +-- Fixed a potential bug in the byte controller's host-acknowledge generation. +-- +-- Revision 1.5 2003/02/01 02:03:06 rherveille +-- Fixed a few 'arbitration lost' bugs. VHDL version only. +-- +-- Revision 1.4 2002/12/26 16:05:47 rherveille +-- Core is now a Multimaster I2C controller. +-- +-- Revision 1.3 2002/11/30 22:24:37 rherveille +-- Cleaned up code +-- +-- Revision 1.2 2001/11/10 10:52:44 rherveille +-- Changed PRER reset value from 0x0000 to 0xffff, conform specs. +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2c_master_top is + generic( + ARST_LVL : std_logic := '0' -- asynchronous reset level + ); + port ( + -- wishbone signals + wb_clk_i : in std_logic; -- master clock input + wb_rst_i : in std_logic := '0'; -- synchronous active high reset + arst_i : in std_logic := not ARST_LVL; -- asynchronous reset + wb_adr_i : in std_logic_vector(2 downto 0); -- lower address bits + wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input + wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output + wb_we_i : in std_logic; -- Write enable input + wb_stb_i : in std_logic; -- Strobe signals / core select signal + wb_cyc_i : in std_logic; -- Valid bus cycle input + wb_ack_o : out std_logic; -- Bus cycle acknowledge output + wb_inta_o : out std_logic; -- interrupt request output signal + + -- i2c lines + scl_pad_i : in std_logic; -- i2c clock line input + scl_pad_o : out std_logic; -- i2c clock line output + scl_padoen_o : out std_logic; -- i2c clock line output enable, active low + sda_pad_i : in std_logic; -- i2c data line input + sda_pad_o : out std_logic; -- i2c data line output + sda_padoen_o : out std_logic -- i2c data line output enable, active low + ); +end entity i2c_master_top; + +architecture structural of i2c_master_top is + component i2c_master_byte_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) + nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- 4x SCL + + -- input signals + start, + stop, + read, + write, + ack_in : std_logic; + din : in std_logic_vector(7 downto 0); + + -- output signals + cmd_ack : out std_logic; + ack_out : out std_logic; + i2c_busy : out std_logic; + i2c_al : out std_logic; + dout : out std_logic_vector(7 downto 0); + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); + end component i2c_master_byte_ctrl; + + -- registers + signal prer : unsigned(15 downto 0); -- clock prescale register + signal ctr : std_logic_vector(7 downto 0); -- control register + signal txr : std_logic_vector(7 downto 0); -- transmit register + signal rxr : std_logic_vector(7 downto 0); -- receive register + signal cr : std_logic_vector(7 downto 0); -- command register + signal sr : std_logic_vector(7 downto 0); -- status register + + -- internal reset signal + signal rst_i : std_logic; + + -- wishbone write access + signal wb_wacc : std_logic; + + -- internal acknowledge signal + signal iack_o : std_logic; + + -- done signal: command completed, clear command register + signal done : std_logic; + + -- command register signals + signal sta, sto, rd, wr, ack, iack : std_logic; + + signal core_en : std_logic; -- core enable signal + signal ien : std_logic; -- interrupt enable signal + + -- status register signals + signal irxack, rxack : std_logic; -- received aknowledge from slave + signal tip : std_logic; -- transfer in progress + signal irq_flag : std_logic; -- interrupt pending flag + signal i2c_busy : std_logic; -- i2c bus busy (start signal detected) + signal i2c_al, al : std_logic; -- arbitration lost + +begin + -- generate internal reset signal + rst_i <= arst_i xor ARST_LVL; + + -- generate acknowledge output signal + gen_ack_o : process(wb_clk_i) + begin + if (wb_clk_i'event and wb_clk_i = '1') then + iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored + end if; + end process gen_ack_o; + wb_ack_o <= iack_o; + + -- generate wishbone write access signal + wb_wacc <= wb_we_i and wb_cyc_i and wb_stb_i;-- and iack_o; + + -- assign wb_dat_o + assign_dato : process(wb_clk_i) + begin + if (wb_clk_i'event and wb_clk_i = '1') then + if (wb_we_i = '0') and (wb_cyc_i = '1') and (wb_stb_i = '1') then + case wb_adr_i is + when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0)); + when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8)); + when "010" => wb_dat_o <= ctr; + when "011" => wb_dat_o <= rxr; -- write is transmit register TxR + when "100" => wb_dat_o <= sr; -- write is command register CR + + -- Debugging registers: + -- These registers are not documented. + -- Functionality could change in future releases + when "101" => wb_dat_o <= txr; + when "110" => wb_dat_o <= cr; + when "111" => wb_dat_o <= (others => '0'); + when others => wb_dat_o <= (others => '0'); + end case; + else + wb_dat_o <= (others => '0'); + end if; + end if; + end process assign_dato; + + + -- generate registers (CR, SR see below) + gen_regs: process(rst_i, wb_clk_i) + begin + if (rst_i = '0') then + prer <= (others => '1'); + ctr <= (others => '0'); + txr <= (others => '0'); + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + prer <= (others => '1'); + ctr <= (others => '0'); + txr <= (others => '0'); + elsif (wb_wacc = '1') then + case wb_adr_i is + when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i); + when "001" => prer(15 downto 8) <= unsigned(wb_dat_i); + when "010" => ctr <= wb_dat_i; + when "011" => txr <= wb_dat_i; + when "100" => null; --write to CR, avoid executing the others clause + + -- illegal cases, for simulation only + when others => + report ("Illegal write address, setting all registers to unknown."); + prer <= (others => 'X'); + ctr <= (others => 'X'); + txr <= (others => 'X'); + end case; + end if; + end if; + end process gen_regs; + + + -- generate command register + gen_cr: process(rst_i, wb_clk_i) + begin + if (rst_i = '0') then + cr <= (others => '0'); + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + cr <= (others => '0'); + elsif (wb_wacc = '1') then + if ( (core_en = '1') and (wb_adr_i = "100") ) then + -- only take new commands when i2c core enabled + -- pending commands are finished + cr <= wb_dat_i; + end if; + else + if (done = '1' or i2c_al = '1') then + cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost + end if; + + cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0' + cr(0) <= '0'; -- clear IRQ_ACK bit + end if; + end if; + end process gen_cr; + + -- decode command register + sta <= cr(7); + sto <= cr(6); + rd <= cr(5); + wr <= cr(4); + ack <= cr(3); + iack <= cr(0); + + -- decode control register + core_en <= ctr(7); + ien <= ctr(6); + + -- hookup byte controller block + byte_ctrl: i2c_master_byte_ctrl + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + nReset => rst_i, + ena => core_en, + clk_cnt => prer, + start => sta, + stop => sto, + read => rd, + write => wr, + ack_in => ack, + i2c_busy => i2c_busy, + i2c_al => i2c_al, + din => txr, + cmd_ack => done, + ack_out => irxack, + dout => rxr, + scl_i => scl_pad_i, + scl_o => scl_pad_o, + scl_oen => scl_padoen_o, + sda_i => sda_pad_i, + sda_o => sda_pad_o, + sda_oen => sda_padoen_o + ); + + + -- status register block + interrupt request signal + st_irq_block : block + begin + -- generate status register bits + gen_sr_bits: process (wb_clk_i, rst_i) + begin + if (rst_i = '0') then + al <= '0'; + rxack <= '0'; + tip <= '0'; + irq_flag <= '0'; + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + al <= '0'; + rxack <= '0'; + tip <= '0'; + irq_flag <= '0'; + else + al <= i2c_al or (al and not sta); + rxack <= irxack; + tip <= (rd or wr); + + -- interrupt request flag is always generated + irq_flag <= (done or i2c_al or irq_flag) and not iack; + end if; + end if; + end process gen_sr_bits; + + -- generate interrupt request signals + gen_irq: process (wb_clk_i, rst_i) + begin + if (rst_i = '0') then + wb_inta_o <= '0'; + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + wb_inta_o <= '0'; + else + -- interrupt signal is only generated when IEN (interrupt enable bit) is set + wb_inta_o <= irq_flag and ien; + end if; + end if; + end process gen_irq; + + -- assign status register bits + sr(7) <= rxack; + sr(6) <= i2c_busy; + sr(5) <= al; + sr(4 downto 2) <= (others => '0'); -- reserved + sr(1) <= tip; + sr(0) <= irq_flag; + end block; + +end architecture structural; diff --git a/zpu/devices/WishBone/I2C/readme b/zpu/devices/WishBone/I2C/readme new file mode 100644 index 0000000..0d049f7 --- /dev/null +++ b/zpu/devices/WishBone/I2C/readme @@ -0,0 +1,25 @@ + + +-- This code is provided for free and may be used and -- +-- distributed without restriction provided that the -- +-- copyright statement is not removed from the file and -- +-- that any derivative work contains the original -- +-- copyright notice and the associated disclaimer. -- + +-- Comments and suggestions are always welcome -- + +The i2c_master core consists of three files: + +- i2c_master_top -- top level +- i2c_master_byte_ctrl -- byte controller +- i2c_master_bit_ctrl -- bit controller + +VHDL needs to be compiled in order. The files are listed +above in descending order. + +I2C.VHD and tst_ds1621.vhd are not supported anymore. +They remain mostly for historical purposes, altough they +might prove usefull. + +Richard Herveille +rherveille@opencores.org diff --git a/zpu/devices/WishBone/SDRAM.old/sdram.qip b/zpu/devices/WishBone/SDRAM.old/sdram.qip new file mode 100644 index 0000000..a0e34f0 --- /dev/null +++ b/zpu/devices/WishBone/SDRAM.old/sdram.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sdram.vhd ] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sdram.sdc ] diff --git a/zpu/devices/WishBone/SDRAM.old/sdram.sdc b/zpu/devices/WishBone/SDRAM.old/sdram.sdc new file mode 100644 index 0000000..73d4248 --- /dev/null +++ b/zpu/devices/WishBone/SDRAM.old/sdram.sdc @@ -0,0 +1,19 @@ +derive_pll_clocks + +#create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_generated_clock -source [get_pins -compatibility_mode {*mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] \ + -name SDRAM_CLK [get_ports {SDRAM_CLK}] + +derive_clock_uncertainty + +# Set acceptable delays for SDRAM chip (See correspondent chip datasheet) +set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]] +set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]] + +# -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] +set_multicycle_path -from [get_clocks {SDRAM_CLK}] \ + -to [get_clocks {*mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] \ + -setup 2 + +set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}] +set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}] diff --git a/zpu/devices/WishBone/SDRAM.old/sdram.vhd b/zpu/devices/WishBone/SDRAM.old/sdram.vhd new file mode 100644 index 0000000..e140e14 --- /dev/null +++ b/zpu/devices/WishBone/SDRAM.old/sdram.vhd @@ -0,0 +1,494 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: sdram.vhd +-- Created: September 2019 +-- Original Author: Stephen J. Leary 2013-2014 +-- VHDL Author: Philip Smart +-- Description: Original module written by Stephen J. Leary 2013-2014 in Verilog for use with the +-- MT48LC16M16 chip. +-- It has been translated into VHDL and undergoing extensive modifications to work +-- with the ZPU EVO processor, specifically burst tuning to enhance L2 Cache Fill +-- performance. +-- Credits: +-- Copyright: Copyright (c) 2013-2014, Stephen J. Leary, All rights reserved. +-- VHDL translation and enhancements (c) 2019 Philip Smart +-- +-- History: September 2019 - Initial module based on translaction of Stephen J. Leary's Verilog +-- source code. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_soc_pkg.all; +use work.zpu_pkg.all; + +entity SDRAM is + generic ( + MAX_DATACACHE_BITS : integer := 4 -- Maximum size in addr bits of 32bit datacache for burst transactions. + ); + port ( + -- SDRAM Interface + SD_CLK : in std_logic; -- sdram is accessed at 100MHz + SD_RST : in std_logic; -- reset the sdram controller. + SD_CKE : out std_logic; -- clock enable. + SD_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus + SD_ADDR : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus + SD_DQM : out std_logic_vector(1 downto 0); -- two byte masks + SD_BA : out std_logic_vector(1 downto 0); -- two banks + SD_CS_n : out std_logic; -- a single chip select + SD_WE_n : out std_logic; -- write enable + SD_RAS_n : out std_logic; -- row address select + SD_CAS_n : out std_logic; -- columns address select + SD_READY : out std_logic; -- sd ready. + + -- WishBone interface. + WB_CLK : in std_logic; -- Master clock at which the Wishbone interface operates. + WB_DAT_I : in std_logic_vector(WORD_32BIT_RANGE); -- Data input from Master + WB_DAT_O : out std_logic_vector(WORD_32BIT_RANGE); -- Data output to Master + WB_ACK_O : out std_logic; + WB_ADR_I : in std_logic_vector(23 downto 0); -- lower 2 bits are ignored. + WB_SEL_I : in std_logic_vector(3 downto 0); + WB_CTI_I : in std_logic_vector(2 downto 0); -- 000 Classic cycle, 001 Constant address burst cycle, 010 Incrementing burst cycle, 111 End-of-Burst + + WB_STB_I : in std_logic; + WB_CYC_I : in std_logic; -- cpu/chipset requests cycle + WB_WE_I : in std_logic -- cpu/chipset requests write + ); +end SDRAM; + +architecture Structure of SDRAM is + + -- Constants for register access. + -- + constant RASCAS_DELAY : integer := 3; -- tRCD=20ns -> 2 cycles@100MHz + constant RFC_DELAY : integer := 70; -- tRFC=66ns time in nS for a autorefresh to complete. + constant RAM_CLK : integer := 100000000; + + -- Command table from the Micron datasheet. + -- Name (Function) CS# RAS# CAS# WE# DQM ADDR DQ + -- COMMAND INHIBIT (NOP) H X X X X X X + -- NO OPERATION (NOP) L H H H X X X + -- ACTIVE (select bank and activate row) L L H H X Bank/row X + -- READ (select bank and column, and start READ burst) L H L H L/H Bank/col X + -- WRITE (select bank and column, and start WRITE burst) L H L L L/H Bank/col Valid + -- BURST TERMINATE L H H L X X Active + -- PRECHARGE (Deactivate row in bank or banks) L L H L X Code X + -- AUTO REFRESH or SELF REFRESH (enter self refresh mode) L L L H X X X + -- LOAD MODE REGISTER L L L L X Op-code X + -- Write enable/output enable X X X X L X Active + -- Write inhibit/output High-Z X X X X H X High-Z + constant CMD_INHIBIT : std_logic_vector(3 downto 0) := "1111"; + constant CMD_NOP : std_logic_vector(3 downto 0) := "0111"; + constant CMD_ACTIVE : std_logic_vector(3 downto 0) := "0011"; + constant CMD_READ : std_logic_vector(3 downto 0) := "0101"; + constant CMD_WRITE : std_logic_vector(3 downto 0) := "0100"; + constant CMD_BURST_TERMINATE : std_logic_vector(3 downto 0) := "0110"; + constant CMD_PRECHARGE : std_logic_vector(3 downto 0) := "0010"; + constant CMD_AUTO_REFRESH : std_logic_vector(3 downto 0) := "0001"; + constant CMD_LOAD_MODE : std_logic_vector(3 downto 0) := "0000"; + + -- Load Mode Register setting. + -- 12:10 = Reserved : + -- 9 = Write Burst Mode : 0 = Programmed Burst Length, 1 = Single Location Access + -- 8:7 = Operating Mode : 00 = Standard Operation, all other values reserved. + -- 6:4 = CAS Latency : 010 = 2, 011 = 3, all other values reserved. + -- 3 = Burst Type : 0 = Sequential, 1 = Interleaved. + -- 2:0 = Burst Length : When 000 = 1, 001 = 2, 010 = 4, 011 = 8, all others reserved except 111 when BT = 0 sets full page access. + -- | A12-A10 | A9  A8-A7 | A6 A5 A4 | A3  A2 A1 A0 | + -- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len| + constant WRITE_BURST_MODE : std_logic := '1'; + constant OP_MODE : std_logic_vector(1 downto 0) := "00"; + constant CAS_LATENCY : std_logic_vector(2 downto 0) := "011"; + constant BURST_TYPE : std_logic := '0'; + constant BURST_LENGTH : std_logic_vector(2 downto 0) := "000"; + constant MODE : std_logic_vector(12 downto 0) := "000" & WRITE_BURST_MODE & OP_MODE & CAS_LATENCY & BURST_TYPE & BURST_LENGTH; + + -- FSM Cycle States. + constant CYCLE_PRECHARGE : integer := 0; -- 0 + constant CYCLE_RAS_START : integer := 3; -- 3 + constant CYCLE_RAS_NEXT : integer := CYCLE_RAS_START + 1; -- 4 + constant CYCLE_CAS0 : integer := CYCLE_RAS_START + RASCAS_DELAY; -- 3 + RASCAS_DELAY + constant CYCLE_CAS1 : integer := CYCLE_CAS0 + 1; -- 4 + RASCAS_DELAY + constant CYCLE_CAS2 : integer := CYCLE_CAS1 + 1; -- 5 + RASCAS_DELAY + constant CYCLE_CAS3 : integer := CYCLE_CAS2 + 1; -- 6 + RASCAS_DELAY + constant CYCLE_READ0 : integer := CYCLE_CAS0 + to_integer(unsigned(CAS_LATENCY)) + 1; -- 3 + RASCAS_DELAY + CAS_LATENCY + constant CYCLE_READ1 : integer := CYCLE_READ0 + 1; -- 4 + RASCAS_DELAY + CAS_LATENCY + constant CYCLE_READ2 : integer := CYCLE_READ1 + 1; -- 5 + RASCAS_DELAY + CAS_LATENCY + constant CYCLE_READ3 : integer := CYCLE_READ2 + 1; -- 6 + RASCAS_DELAY + CAS_LATENCY + constant CYCLE_END : integer := CYCLE_READ3 + 1; -- 9 + RASCAS_DELAY + CAS_LATENCY + constant CYCLE_RFSH_START : integer := CYCLE_RAS_START; -- 3 + constant CYCLE_RFSH_END : integer := CYCLE_RFSH_START + ((RFC_DELAY/RAM_CLK) * 10000000) + 1; -- 3 + RFC_DELAY in clock ticks. + + -- Period in clock cycles between SDRAM refresh cycles. + constant REFRESH_PERIOD : integer := (RAM_CLK / (64 * 8192)) - CYCLE_END; + + type BankArray is array(natural range 0 to 3) of std_logic_vector(12 downto 0); + + -- Cache for holding burst reads to allow for differing speeds of WishBone Master. + type DataCacheArray is array(natural range 0 to ((2**(MAX_DATACACHE_BITS))-1)) of std_logic_vector(WORD_32BIT_RANGE); + signal readCache : DataCacheArray; + attribute ramstyle : string; + attribute ramstyle of readCache : signal is "logic"; + signal cacheReadAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0); + signal cacheWriteAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0); + + signal sd_dat : std_logic_vector(31 downto 0); + signal sd_dat_nxt : std_logic_vector(31 downto 0); + signal sd_stb : std_logic; + signal sd_we : std_logic; + signal sd_cyc : std_logic; + signal sd_burst : std_logic; + signal sd_cycle : integer range 0 to 31; + signal sd_done : std_logic; + signal sd_cmd : std_logic_vector(3 downto 0); + signal sd_refresh : unsigned(3 downto 0); + signal sd_auto_refresh : std_logic; + signal sd_req : std_logic_vector(2 downto 0); + + signal sd_in_rst : unsigned(7 downto 0); + signal sd_rst_timer : unsigned(6 downto 0); + signal sd_active_row : BankArray; + signal sd_active_bank : std_logic_vector(1 downto 0); + signal sd_bank : natural range 0 to 3; + signal sd_row : std_logic_vector(12 downto 0); + signal sd_reading : std_logic; + signal sd_writing : std_logic; + signal sd_rdy : std_logic; + signal sd_mxadr : std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus + signal sd_dout : std_logic_vector(15 downto 0); + signal sd_din : std_logic_vector(15 downto 0); + signal sd_done_last : std_logic; + + signal burst_mode : std_logic; + signal can_burst : std_logic; + + signal wb_ack : std_logic; + signal wb_burst : std_logic; + +begin + + -- Tri-state control of the SDRAM data bus. + process(sd_writing, SD_DQ, sd_dout) + begin + if (sd_writing = '0') then + SD_DQ <= (others => 'Z'); + sd_din <= SD_DQ; + else + SD_DQ <= sd_dout; + sd_din <= SD_DQ; + end if; + end process; + + -- Main FSM for SDRAM control and refresh. + process(SD_CLK, SD_RST) + begin + if (SD_RST = '1') then + sd_rst_timer <= (others => '0'); -- 0 upto 127 + sd_in_rst <= (others => '1'); -- 255 downto 0 + sd_mxadr <= (others => '0'); + sd_auto_refresh <= '0'; + sd_active_bank <= (others => '0'); + sd_refresh <= (others => '0'); + sd_active_row <= ((others => '0'), (others => '0'), (others => '0'), (others => '0')); + sd_rdy <= '0'; + sd_cmd <= CMD_AUTO_REFRESH; + sd_stb <= '0'; + sd_cyc <= '0'; + sd_burst <= '0'; + sd_we <= '0'; + sd_cycle <= 0; + sd_done <= '0'; + cacheWriteAddr <= (others => '0'); + + elsif rising_edge(SD_CLK) then + + -- If no specific command given the default is NOP. + sd_cmd <= CMD_NOP; + + -- Initialisation on power up or reset. The SDRAM must be given at least 100uS to initialise and a fixed setup pattern applied. + if (sd_rdy = '0') then + sd_rst_timer <= sd_rst_timer + 1; + + -- 1uS timer. + if (sd_rst_timer = RAM_CLK/1000000) then + sd_rst_timer <= (others => '0'); + sd_in_rst <= sd_in_rst - 1; + end if; + + -- Every 1uS check for the next init action. + if (sd_rst_timer = 0) then + + -- 100uS wait, no action as the SDRAM starts up. + -- ie. 255 downto 155 + + -- Precharge all banks + if(sd_in_rst = 155) then + sd_cmd <= CMD_PRECHARGE; + sd_mxadr(10) <= '1'; + end if; + + -- Load the Mode register with our parameters. + if(sd_in_rst = 148 or sd_in_rst = 147) then + sd_cmd <= CMD_LOAD_MODE; + sd_mxadr <= MODE; + end if; + + -- 2 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after + -- the other. + if(sd_in_rst = 145 or sd_in_rst = 140) then + sd_cmd <= CMD_AUTO_REFRESH; + end if; + + -- SDRAM ready. + if(sd_in_rst = 135) then + sd_rdy <= '1'; + end if; + end if; + else + + -- bring the wishbone bus signal into the ram clock domain. + sd_we <= WB_WE_I; + if (sd_req = "111") then + sd_stb <= WB_STB_I; + sd_cyc <= WB_CYC_I; + end if; + + sd_refresh <= sd_refresh + 1; + + -- Auto refresh. On timeout it kicks in so that 8192 auto refreshes are + -- issued in a 64ms period. Other bus operations are stalled during this period. + if ((sd_refresh > REFRESH_PERIOD) and (sd_cycle = 0)) then + sd_auto_refresh <= '1'; + sd_refresh <= (others => '0'); + sd_cmd <= CMD_PRECHARGE; + sd_mxadr(10) <= '1'; + sd_active_bank <= (others => '0'); + + -- In auto refresh period. + elsif (sd_auto_refresh = '1') then + + -- while the cycle is active count. + sd_cycle <= sd_cycle + 1; + case (sd_cycle) is + when CYCLE_RFSH_START => + sd_cmd <= CMD_AUTO_REFRESH; + + when CYCLE_RFSH_END => + -- reset the count. + sd_auto_refresh <= '0'; + sd_cycle <= 0; + + when others => + end case; + + elsif (sd_cyc = '1' or (sd_cycle /= 0) or (sd_cycle = 0 and sd_req = "111")) then + + -- while the cycle is active count. + sd_cycle <= sd_cycle + 1; + case (sd_cycle) is + + when CYCLE_PRECHARGE => + -- If the bank is not open then no need to precharge, move onto RAS. + if (sd_active_bank(sd_bank) = '0') then + sd_cycle <= CYCLE_RAS_START; +--The active row isnt being reset + -- If the requested row is already active, go to CAS for immediate access to this row. + elsif (sd_active_row(sd_bank) = sd_row) then + sd_cycle <= CYCLE_CAS0; -- - 1; -- FIXME: Why doesn't work without -1? + + -- Otherwise we close out the open bank by issuing a PRECHARGE. + else + sd_cmd <= CMD_PRECHARGE; + sd_mxadr(10) <= '0'; + SD_BA <= std_logic_vector(to_unsigned(sd_bank, SD_BA'length)); + sd_active_bank(sd_bank) <= '0'; -- Store flag to indicate which bank is being made active. + end if; + + -- Open the requested row. + when CYCLE_RAS_START => + sd_cmd <= CMD_ACTIVE; + --sd_mxadr <= '0' & sd_row; -- 0 & Addr[20:9] presented to SDRAM as row address. + sd_mxadr <= sd_row; -- Addr[21:9] presented to SDRAM as row address. + SD_BA <= std_logic_vector(to_unsigned(sd_bank, SD_BA'length)); -- Addr[23:22] + sd_active_row(sd_bank) <= sd_row; -- Store number of row being made active + sd_active_bank(sd_bank) <= '1'; -- Store flag to indicate which bank is being made active. + + when CYCLE_RAS_NEXT => + sd_mxadr(12 downto 11) <= "11"; -- Set DQ to tri--state. + + -- this is the first CAS cycle + when CYCLE_CAS0 => + -- Process on a 32bit boundary, as this is a 16bit chip we need 2 accesses for a 32bit alignment. + --sd_mxadr <= "0000" & WB_ADR_I(23) & WB_ADR_I(8 downto 2) & '0'; -- CAS address = Addr[23,8:2] accessing first 16bit location within the 32bit external alignment with no auto precharge + sd_mxadr <= "0000" & WB_ADR_I(8 downto 1) & '0'; -- CAS address = Addr[23,8:2] accessing first 16bit location within the 32bit external alignment with no auto precharge + SD_BA <= std_logic_vector(to_unsigned(sd_bank, SD_BA'length)); -- Ensure bank is the correct one opened. + + if (sd_reading = '1') then + sd_cmd <= CMD_READ; + elsif (sd_writing = '1') then + sd_cmd <= CMD_WRITE; + sd_mxadr(12 downto 11)<= not WB_SEL_I(1 downto 0); -- For writing, set DQM to the negated WB_SEL values, indicating which bytes to process. + sd_dout <= wb_dat_i(15 downto 0); -- Assign corresponding data to the SDRAM databus. + end if; + + when CYCLE_CAS1 => + --sd_mxadr <= "0000" & WB_ADR_I(23) & WB_ADR_I(8 downto 2) & '1'; -- As per CAS0 except we now access second 16bit location within the 32bit external alignment. + sd_mxadr <= "0000" & WB_ADR_I(8 downto 1) & '1'; -- As per CAS0 except we now access second 16bit location within the 32bit external alignment. + if (sd_reading = '1') then + sd_cmd <= CMD_READ; + if (burst_mode = '1' and can_burst = '1') then + sd_burst <= '1'; + end if; + elsif (sd_writing = '1') then + sd_cmd <= CMD_WRITE; + sd_mxadr(12 downto 11)<= not WB_SEL_I(3 downto 2); + sd_done <= not sd_done; + sd_dout <= wb_dat_i(31 downto 16); + -- sd_cycle <= CYCLE_END; + end if; + + + -- CAS2/3 ... are to handle burst transfers according to programmed Mode register word. + when CYCLE_CAS2 => + if (sd_burst = '1') then + --sd_mxadr <= "0000" & WB_ADR_I(23) & WB_ADR_I(8 downto 3) & "10"; -- no auto precharge + sd_mxadr <= "0000" & WB_ADR_I(8 downto 2) & "10"; -- no auto precharge + if (sd_reading = '1') then + sd_cmd <= CMD_READ; + end if; + end if; + + when CYCLE_CAS3 => + if (sd_burst = '1') then + --sd_mxadr <= "0000" & WB_ADR_I(23) & WB_ADR_I(8 downto 3) & "11"; -- no auto precharge + sd_mxadr <= "0000" & WB_ADR_I(8 downto 2) & "11"; -- no auto precharge + if (sd_reading = '1') then + sd_cmd <= CMD_READ; + end if; + end if; + + -- Data is available CAS Latency clocks after the read request, so these read operations operate in parallel to the CAS + -- cycles requesting the data. ie. CL=2 then CYCLE_READ0 will be processed same time as CYCLE_CAS2. + when CYCLE_READ0 => + if (sd_reading = '1') then + sd_dat(15 downto 0) <= sd_din; + else + if (sd_writing = '1') then + sd_cycle <= CYCLE_END; + end if; + end if; + + when CYCLE_READ1 => + if (sd_reading = '1') then + sd_dat(31 downto 16) <= sd_din; + sd_done <= not sd_done; + end if; + + when CYCLE_READ2 => + if (sd_reading = '1') then + sd_dat_nxt(15 downto 0)<= sd_din; + end if; + + when CYCLE_READ3 => + if (sd_reading = '1') then + sd_dat_nxt(31 downto 16)<= sd_din; + end if; + + when CYCLE_END => + sd_burst <= '0'; + sd_cyc <= '0'; + sd_stb <= '0'; + + when others => + end case; + else + sd_cycle <= 0; + sd_burst <= '0'; + end if; + end if; + end if; + end process; + + -- WishBone interface for sending received data and setting up the correct ACK signal for any read/write activity. + process(SD_RST, WB_CLK, sd_rdy) + begin + if (SD_RST = '1') then + sd_done_last <= '0'; + wb_ack <= '0'; + wb_burst <= '0'; + + -- If the SDRAM isnt ready, we can only wait. + elsif sd_rdy = '0' then + + elsif rising_edge(WB_CLK) then + + -- Note SDRAM activity via a previous/last signal. + sd_done_last <= sd_done; + + -- If there has been a change in the SDRAM activity and it hasnt been acknowleged, send the ACK else cancel any previous ACK. + if (sd_done xor sd_done_last) = '1' and wb_ack = '0' then + wb_ack <= '1'; + else + wb_ack <= '0'; + end if; + + -- If we are in an active Cycle and the Strobe is activated, assign any read data to the WB bus. + if (WB_STB_I = '1' and WB_CYC_I = '1') then + + -- If there has been a change in the SDRAM activity and it hasnt been acknowledged, send the current data held to the WB Bus. + if ((sd_done xor sd_done_last) = '1' and wb_ack = '0') then + wb_dat_o <= sd_dat; + wb_burst <= burst_mode; + end if; + + -- If there has been an acknowledge due to sending of the first data word and we are in burst mode, then send the 2nd read value + -- whilst maintaining the ack. + if (wb_ack = '1' and wb_burst = '1') then + wb_ack <= '1'; + wb_burst <= '0'; + wb_dat_o <= sd_dat_nxt; + end if; + else + wb_burst <= '0'; + end if; + end if; + end process; + + sd_req <= WB_STB_I & WB_CYC_I & not wb_ack; + sd_bank <= to_integer(unsigned(WB_ADR_I(23 downto 22))); + sd_row <= WB_ADR_I(21 downto 9); + + burst_mode <= '1' when WB_CTI_I = "010" else '0'; + can_burst <= '1' when WB_ADR_I(2) = '0' else '0'; + sd_reading <= '1' when sd_stb = '1' and sd_cyc = '1' and sd_we = '0' else '0'; + sd_writing <= '1' when sd_stb = '1' and sd_cyc = '1' and sd_we = '1' else '0'; + + -- drive control signals according to current command + SD_CS_n <= sd_cmd(3); + SD_RAS_n <= sd_cmd(2); + SD_CAS_n <= sd_cmd(1); + SD_WE_n <= sd_cmd(0); + SD_CKE <= '1'; + SD_DQM <= sd_mxadr(12 downto 11); + SD_ADDR <= sd_mxadr; + + WB_ACK_O <= wb_ack; + SD_READY <= sd_rdy; + +end Structure; diff --git a/zpu/devices/WishBone/SDRAM/48LC16M16.qip b/zpu/devices/WishBone/SDRAM/48LC16M16.qip new file mode 100644 index 0000000..c21ead0 --- /dev/null +++ b/zpu/devices/WishBone/SDRAM/48LC16M16.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) wbsdram.vhd ] +#set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) 48LC16M16.sdc ] diff --git a/zpu/devices/WishBone/SDRAM/48LC16M16.sdc b/zpu/devices/WishBone/SDRAM/48LC16M16.sdc new file mode 100644 index 0000000..9d3d13c --- /dev/null +++ b/zpu/devices/WishBone/SDRAM/48LC16M16.sdc @@ -0,0 +1,90 @@ +# ------------------------------------------------------------------------------ +# Constraints definition original author: +# 8/19/2014 D. W. Hawkings (dwh@ovro.caltech.edu) +# Adapted and enhanced for the Micron 48LC16M16 SDRAM by Philip Smart Dec 2019. +# ------------------------------------------------------------------------------ +derive_pll_clocks + +# ----------------------------------------------------------------- +# SDRAM Clock +# Set these variables to the system and memory clock PLL paths for +# your board. +# ----------------------------------------------------------------- +set sysclk_pll "mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk" +set memclk_pll "mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk" +create_generated_clock -name SDRAM_CLK -source $memclk_pll [get_ports {SDRAM_CLK}] +derive_clock_uncertainty + +# ----------------------------------------------------------------- +# SDRAM Constraints +# ----------------------------------------------------------------- +# +# SDRAM timing parameters +# +# Generally, the command/address/data all have the same setup/hold +# time. +# +# SDRAM clock can lead System clock by min: +# tlead = tcoutmin(FPGA) – th(SDRAM) +# +# SDRAM clock can lag System clock by min: +# tlag = toh(SDRAM) – th(FPGA) +# +# tSU = Data Setup time (ie. tDS, tAS) on falling edge. +# tH = Hold time (ie. tDH, tAH) for SDRAM. +# tCOUT (min) = Data out hold time (ie. tOH) +# tCOUT (max) = Access time for CL in use (ie. tAC3). +# +set sdram_tsu 1.5 +set sdram_th 0.8 +set sdram_tco_min 3.0 +set sdram_tco_max 5.4 + +# FPGA timing constraints +set sdram_input_delay_min $sdram_tco_min +set sdram_input_delay_max $sdram_tco_max +set sdram_output_delay_min -$sdram_th +set sdram_output_delay_max $sdram_tsu + +# PLL to FPGA output (clear the unconstrained path warning) +#set_min_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 1 +#set_max_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 6 + +# FPGA Outputs +set sdram_outputs [get_ports { + SDRAM_CKE + SDRAM_CS + SDRAM_RAS + SDRAM_CAS + SDRAM_WE + SDRAM_DQM[*] + SDRAM_BA[*] + SDRAM_ADDR[*] + SDRAM_DQ[*] +}] +set_output_delay -clock SDRAM_CLK -min $sdram_output_delay_min $sdram_outputs +set_output_delay -clock SDRAM_CLK -max $sdram_output_delay_max $sdram_outputs + +# FPGA Inputs +set sdram_inputs [get_ports { + SDRAM_DQ[*] +}] +set_input_delay -clock SDRAM_CLK -min $sdram_input_delay_min $sdram_inputs +set_input_delay -clock SDRAM_CLK -max $sdram_input_delay_max $sdram_inputs + +# ----------------------------------------------------------------- +# SDRAM-to-FPGA multi-cycle constraint +# ----------------------------------------------------------------- + +# The PLL is configured so that SDRAM clock leads the system +# clock by ~90-degrees (0.25 period or 2.5ns for 100MHz clock). +# This will need changing for different clocks, in the PLL +# RTL file and the SoC contraints file. + +# The following multi-cycle constraint declares to TimeQuest that +# the path between the SDRAM_CLK and the System Clock can be an +# extra clock period to the read path to ensure that the latch +# clock that occurs 1.25 periods after the launch clock is used in +# the timing analysis. +# +set_multicycle_path -setup -end -from SDRAM_CLK -to $sysclk_pll 2 diff --git a/zpu/devices/WishBone/SDRAM/48LC16M16_cached.qip b/zpu/devices/WishBone/SDRAM/48LC16M16_cached.qip new file mode 100644 index 0000000..98c0011 --- /dev/null +++ b/zpu/devices/WishBone/SDRAM/48LC16M16_cached.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) wbsdram_cached.vhd ] +#set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) 48LC16M16.sdc ] diff --git a/zpu/devices/WishBone/SDRAM/W9864G6.qip b/zpu/devices/WishBone/SDRAM/W9864G6.qip new file mode 100644 index 0000000..9c49ebe --- /dev/null +++ b/zpu/devices/WishBone/SDRAM/W9864G6.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) wbsdram.vhd ] +#set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) W9864G6.sdc ] diff --git a/zpu/devices/WishBone/SDRAM/W9864G6.sdc b/zpu/devices/WishBone/SDRAM/W9864G6.sdc new file mode 100644 index 0000000..5e0b98a --- /dev/null +++ b/zpu/devices/WishBone/SDRAM/W9864G6.sdc @@ -0,0 +1,90 @@ +# ------------------------------------------------------------------------------ +# Constraints definition original author: +# 8/19/2014 D. W. Hawkings (dwh@ovro.caltech.edu) +# Adapted and enhanced for the Winbond W9864G6 SDRAM by Philip Smart Dec 2019. +# ------------------------------------------------------------------------------ +derive_pll_clocks + +# ----------------------------------------------------------------- +# SDRAM Clock +# Set these variables to the system and memory clock PLL paths for +# your board. +# ----------------------------------------------------------------- +set sysclk_pll "mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk" +set memclk_pll "mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk" +create_generated_clock -name SDRAM_CLK -source $memclk_pll [get_ports {SDRAM_CLK}] +derive_clock_uncertainty + +# ----------------------------------------------------------------- +# SDRAM Constraints +# ----------------------------------------------------------------- +# +# SDRAM timing parameters +# +# Generally, the command/address/data all have the same setup/hold +# time. +# +# SDRAM clock can lead System clock by min: +# tlead = tcoutmin(FPGA) – th(SDRAM) +# +# SDRAM clock can lag System clock by min: +# tlag = toh(SDRAM) – th(FPGA) +# +# tSU = Data Setup time (ie. tDS, tAS) on falling edge. +# tH = Hold time (ie. tDH, tAH) for SDRAM. +# tCOUT (min) = Data out hold time (ie. tOH) +# tCOUT (max) = Access time for CL in use (ie. tAC3). +# +set sdram_tsu 1.5 +set sdram_th 0.8 +set sdram_tco_min 3.0 +set sdram_tco_max 5.0 + +# FPGA timing constraints +set sdram_input_delay_min $sdram_tco_min +set sdram_input_delay_max $sdram_tco_max +set sdram_output_delay_min -$sdram_th +set sdram_output_delay_max $sdram_tsu + +# PLL to FPGA output (clear the unconstrained path warning) +#set_min_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 1 +#set_max_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 6 + +# FPGA Outputs +set sdram_outputs [get_ports { + SDRAM_CKE + SDRAM_CS + SDRAM_RAS + SDRAM_CAS + SDRAM_WE + SDRAM_DQM[*] + SDRAM_BA[*] + SDRAM_ADDR[*] + SDRAM_DQ[*] +}] +set_output_delay -clock SDRAM_CLK -min $sdram_output_delay_min $sdram_outputs +set_output_delay -clock SDRAM_CLK -max $sdram_output_delay_max $sdram_outputs + +# FPGA Inputs +set sdram_inputs [get_ports { + SDRAM_DQ[*] +}] +set_input_delay -clock SDRAM_CLK -min $sdram_input_delay_min $sdram_inputs +set_input_delay -clock SDRAM_CLK -max $sdram_input_delay_max $sdram_inputs + +# ----------------------------------------------------------------- +# SDRAM-to-FPGA multi-cycle constraint +# ----------------------------------------------------------------- + +# The PLL is configured so that SDRAM clock leads the system +# clock by ~90-degrees (0.25 period or 2.5ns for 100MHz clock). +# This will need changing for different clocks, in the PLL +# RTL file and the SoC contraints file. + +# The following multi-cycle constraint declares to TimeQuest that +# the path between the SDRAM_CLK and the System Clock can be an +# extra clock period to the read path to ensure that the latch +# clock that occurs 1.25 periods after the launch clock is used in +# the timing analysis. +# +set_multicycle_path -setup -end -from SDRAM_CLK -to $sysclk_pll 2 diff --git a/zpu/devices/WishBone/SDRAM/W9864G6_cached.qip b/zpu/devices/WishBone/SDRAM/W9864G6_cached.qip new file mode 100644 index 0000000..61c54c5 --- /dev/null +++ b/zpu/devices/WishBone/SDRAM/W9864G6_cached.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) wbsdram_cached.vhd ] +#set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) W9864G6.sdc ] diff --git a/zpu/devices/WishBone/SDRAM/wbsdram.vhd b/zpu/devices/WishBone/SDRAM/wbsdram.vhd new file mode 100644 index 0000000..b51169e --- /dev/null +++ b/zpu/devices/WishBone/SDRAM/wbsdram.vhd @@ -0,0 +1,504 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: wbsdram.vhd +-- Created: September 2019 +-- Author: Philip Smart +-- Description: A configurable cached sdram controller for use with the ZPU EVO Processor and SoC. +-- The module is instantiated with the parameters to describe the underlying SDRAM chip +-- and in theory should work with most 16/32 bit SDRAM chips if they adhere to the SDRAM +-- standard. +-- Credits: Stephen J. Leary 2013-2014 - Basic sdram cycle structure of this module was based on +-- the verilog MT48LC16M16 chip controller written by Stephen. +-- Copyright: (c) 2019-2020 Philip Smart +-- +-- History: September 2019 - Initial module translation to VHDL based on Stephen J. Leary's Verilog +-- source code. +-- November 2019 - Adapted for the system bus for use when no Wishbone interface is +-- instantiated in the ZPU Evo. +-- December 2019 - Extensive changes, metability stability, autorefresh to ACTIVE timing +-- and parameterisation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_soc_pkg.all; +use work.zpu_pkg.all; + +entity WBSDRAM is + generic ( + MAX_DATACACHE_BITS : integer := 4; -- Maximum size in addr bits of 32bit datacache for burst transactions. + SDRAM_ROWS : integer := 4096; -- Number of Rows in the SDRAM. + SDRAM_COLUMNS : integer := 256; -- Number of Columns in an SDRAM page (ie. 1 row). + SDRAM_BANKS : integer := 4; -- Number of banks in the SDRAM. + SDRAM_DATAWIDTH : integer := 16; -- Data width of SDRAM chip (16, 32). + SDRAM_CLK_FREQ : integer := 100000000; -- Frequency of the SDRAM clock in Hertz. + SDRAM_tRCD : integer := 20; -- tRCD - RAS to CAS minimum period (in ns). + SDRAM_tRP : integer := 20; -- tRP - Precharge delay, min time for a precharge command to complete (in ns). + SDRAM_tRFC : integer := 70; -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns + SDRAM_tREF : integer := 64 -- tREF - period of time a complete refresh of all rows is made within (in ms). + ); + port ( + -- SDRAM Interface + SDRAM_CLK : in std_logic; -- SDRAM is accessed at given clock, frequency specified in RAM_CLK. + SDRAM_RST : in std_logic; -- Reset the sdram controller. + SDRAM_CKE : out std_logic; -- Clock enable. + SDRAM_DQ : inout std_logic_vector(SDRAM_DATAWIDTH-1 downto 0); -- Bidirectional data bus + SDRAM_ADDR : out std_logic_vector(log2ceil(SDRAM_ROWS) - 1 downto 0); -- Multiplexed address bus + SDRAM_DQM : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of byte masks dependent on number of banks. + SDRAM_BA : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of banks in SDRAM + SDRAM_CS_n : out std_logic; -- Single chip select + SDRAM_WE_n : out std_logic; -- Write enable + SDRAM_RAS_n : out std_logic; -- Row address select + SDRAM_CAS_n : out std_logic; -- Columns address select + SDRAM_READY : out std_logic; -- SD ready. + + -- WishBone interface. + WB_CLK : in std_logic; -- Master clock at which the Wishbone interface operates. + WB_RST_I : in std_logic; -- high active sync reset + WB_DATA_I : in std_logic_vector(WORD_32BIT_RANGE); -- Data input from Master + WB_DATA_O : out std_logic_vector(WORD_32BIT_RANGE); -- Data output to Master + WB_ACK_O : out std_logic; + WB_ADR_I : in std_logic_vector(log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS) downto 0); + WB_SEL_I : in std_logic_vector(3 downto 0); + WB_CTI_I : in std_logic_vector(2 downto 0); -- 000 Classic cycle, 001 Constant address burst cycle, 010 Incrementing burst cycle, 111 End-of-Burst + WB_STB_I : in std_logic; + WB_CYC_I : in std_logic; -- cpu/chipset requests cycle + WB_WE_I : in std_logic; -- cpu/chipset requests write + WB_TGC_I : in std_logic_vector(06 downto 0); -- cycle tag + WB_HALT_O : out std_logic; -- throttle master + WB_ERR_O : out std_logic -- abnormal cycle termination + ); +end WBSDRAM; + +architecture Structure of WBSDRAM is + + -- Constants to define the structure of the SDRAM in bits for provisioning of signals. + constant SDRAM_ROW_BITS : integer := log2ceil(SDRAM_ROWS); + constant SDRAM_COLUMN_BITS : integer := log2ceil(SDRAM_COLUMNS); + constant SDRAM_ARRAY_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS); + constant SDRAM_BANK_BITS : integer := log2ceil(SDRAM_BANKS); + constant SDRAM_ADDR_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS * (SDRAM_DATAWIDTH/8)); + + -- Command table for a standard SDRAM. + -- + -- Name (Function) CKE CS# RAS# CAS# WE# DQM ADDR DQ + -- COMMAND INHIBIT (NOP) H H X X X X X X + -- NO OPERATION (NOP) H L H H H X X X + -- ACTIVE (select bank and activate row) H L L H H X Bank/row X + -- READ (select bank and column, and start READ burst) H L H L H L/H Bank/col X + -- WRITE (select bank and column, and start WRITE burst) H L H L L L/H Bank/col Valid + -- BURST TERMINATE H L H H L X X Active + -- PRECHARGE (Deactivate row in bank or banks) H L L H L X Code X + -- AUTO REFRESH or SELF REFRESH (enter self refresh mode) H L L L H X X X + -- LOAD MODE REGISTER H L L L L X Op-code X + -- Write enable/output enable H X X X X L X Active + -- Write inhibit/output High-Z H X X X X H X High-Z + -- Self Refresh Entry L L L L H X X X + -- Self Refresh Exit (Device is idle) H H X X X X X X + -- Self Refresh Exit (Device is in Self Refresh state) H L H H X X X X + -- Clock suspend mode Entry L X X X X X X X + -- Clock suspend mode Exit H X X X X X X X + -- Power down mode Entry (Device is idle) L H X X X X X X + -- Power down mode Entry (Device is Active) L L H H X X X X + -- Power down mode Exit (Any state) H H X X X X X X + -- Power down mode Exit (Device is powered down) H L H H X X X X + + constant CMD_INHIBIT : std_logic_vector(4 downto 0) := "11111"; + constant CMD_NOP : std_logic_vector(4 downto 0) := "10111"; + constant CMD_ACTIVE : std_logic_vector(4 downto 0) := "10011"; + constant CMD_READ : std_logic_vector(4 downto 0) := "10101"; + constant CMD_WRITE : std_logic_vector(4 downto 0) := "10100"; + constant CMD_BURST_TERMINATE : std_logic_vector(4 downto 0) := "10110"; + constant CMD_PRECHARGE : std_logic_vector(4 downto 0) := "10010"; + constant CMD_AUTO_REFRESH : std_logic_vector(4 downto 0) := "10001"; + constant CMD_LOAD_MODE : std_logic_vector(4 downto 0) := "10000"; + constant CMD_SELF_REFRESH_START : std_logic_vector(4 downto 0) := "00001"; + constant CMD_SELF_REFRESH_END : std_logic_vector(4 downto 0) := "10110"; + constant CMD_CLOCK_SUSPEND : std_logic_vector(4 downto 0) := "00000"; + constant CMD_CLOCK_RESTORE : std_logic_vector(4 downto 0) := "10000"; + constant CMD_POWER_DOWN : std_logic_vector(4 downto 0) := "01000"; + constant CMD_POWER_RESTORE : std_logic_vector(4 downto 0) := "01100"; + + -- Load Mode Register setting for a standard SDRAM. + -- + -- xx:10 = Reserved : + -- 9 = Write Burst Mode : 0 = Programmed Burst Length, 1 = Single Location Access + -- 8:7 = Operating Mode : 00 = Standard Operation, all other values reserved. + -- 6:4 = CAS Latency : 010 = 2, 011 = 3, all other values reserved. + -- 3 = Burst Type : 0 = Sequential, 1 = Interleaved. + -- 2:0 = Burst Length : When 000 = 1, 001 = 2, 010 = 4, 011 = 8, all others reserved except 111 when BT = 0 sets full page access. + -- | A12-A10 | A9  A8-A7 | A6 A5 A4 | A3  A2 A1 A0 | + -- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len| + constant WRITE_BURST_MODE : std_logic := '1'; + constant OP_MODE : std_logic_vector(1 downto 0) := "00"; + constant CAS_LATENCY : std_logic_vector(2 downto 0) := "011"; + constant BURST_TYPE : std_logic := '0'; + constant BURST_LENGTH : std_logic_vector(2 downto 0) := "000"; + constant MODE : std_logic_vector(SDRAM_ROW_BITS-1 downto 0) := std_logic_vector(to_unsigned(to_integer(unsigned("00" & WRITE_BURST_MODE & OP_MODE & CAS_LATENCY & BURST_TYPE & BURST_LENGTH)), SDRAM_ROW_BITS)); + + -- FSM Cycle States governed in units of time, the state changes location according to the configurable parameters to ensure correct actuation at the correct time. + -- + constant CYCLE_PRECHARGE : integer := 0; -- ~0 + constant CYCLE_RAS_START : integer := clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ); -- ~3 + constant CYCLE_CAS_START : integer := CYCLE_RAS_START + clockTicks(SDRAM_tRCD, SDRAM_CLK_FREQ); -- ~3 + tRCD + constant CYCLE_CAS_END : integer := CYCLE_CAS_START + 1; -- ~4 + tRCD + constant CYCLE_READ_START : integer := CYCLE_CAS_START + to_integer(unsigned(CAS_LATENCY)) + 1; -- ~3 + tRCD + CAS_LATENCY + constant CYCLE_READ_END : integer := CYCLE_READ_START + 1; -- ~4 + tRCD + CAS_LATENCY + constant CYCLE_END : integer := CYCLE_READ_END + 1; -- ~9 + tRCD + CAS_LATENCY + constant CYCLE_RFSH_START : integer := clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ); -- ~tRP + constant CYCLE_RFSH_END : integer := CYCLE_RFSH_START + clockTicks(SDRAM_tRFC, SDRAM_CLK_FREQ) + clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ) + 1; -- ~tRP (start) + tRFC (min autorefresh time) + tRP (end) in clock ticks. + + -- Period in clock cycles between SDRAM refresh cycles. This equates to tREF / SDRAM_ROWS to evenly divide the time, then subtract the length of the refresh period as this is + -- the time it takes when a refresh starts until completion. + constant REFRESH_PERIOD : integer := (((SDRAM_tREF * SDRAM_CLK_FREQ ) / SDRAM_ROWS) - (SDRAM_tRFC * 1000)) / 1000; + + -- Array of row addresses, one per bank, to indicate the row in use per bank. + type BankArray is array(natural range 0 to SDRAM_BANKS-1) of std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + + -- SDRAM domain signals. + signal sdBusy : std_logic; + signal sdCycle : integer range 0 to 31; + signal sdDataOut : std_logic_vector(WORD_32BIT_RANGE); + signal sdDone : std_logic; + shared variable sdCmd : std_logic_vector(4 downto 0); + signal sdRefreshCount : unsigned(11 downto 0); + signal sdAutoRefresh : std_logic; + signal sdResetTimer : unsigned(WORD_8BIT_RANGE); + signal sdInResetCounter : unsigned(WORD_8BIT_RANGE); + signal sdIsReady : std_logic; + signal sdActiveRow : BankArray; + signal sdActiveBank : std_logic_vector(1 downto 0); + + -- CPU domain signals. + signal cpuBusy : std_logic; + signal cpuDQM : std_logic_vector(3 downto 0); + signal cpuDoneLast : std_logic; + signal cpuBank : natural range 0 to SDRAM_BANKS-1; + signal cpuRow : std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + signal cpuCol : std_logic_vector(SDRAM_COLUMN_BITS-1 downto 0); + signal cpuDataIn : std_logic_vector(WORD_32BIT_RANGE); + signal cpuIsWriting : std_logic; + signal cpuDoneAck : std_logic; + signal wbACK : std_logic; + +begin + + -- Main FSM for SDRAM control and refresh. + process(ALL) + begin + + if (SDRAM_RST = '1') then + sdResetTimer <= (others => '0'); -- 0 upto 255 + sdInResetCounter <= (others => '1'); -- 255 downto 0 + sdAutoRefresh <= '0'; + sdRefreshCount <= (others => '0'); + sdActiveBank <= (others => '0'); + sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0')); + sdIsReady <= '0'; + sdCmd := CMD_AUTO_REFRESH; + SDRAM_DQM <= (others => '1'); + sdCycle <= 0; + sdDone <= '0'; + + elsif rising_edge(SDRAM_CLK) then + + -- Tri-state control of the SDRAM databus, when reading, the output drivers are disabled. + if (cpuIsWriting = '0') then + SDRAM_DQ <= (others => 'Z'); + end if; + + -- If no specific command given the default is NOP. + sdCmd := CMD_NOP; + + -- Initialisation on power up or reset. The SDRAM must be given at least 200uS to initialise and a fixed setup pattern applied. + if (sdIsReady = '0') then + sdResetTimer <= sdResetTimer + 1; + + -- 1uS timer. + if (sdResetTimer = SDRAM_CLK_FREQ/1000000) then + sdResetTimer <= (others => '0'); + sdInResetCounter <= sdInResetCounter - 1; + end if; + + -- Every 1uS check for the next init action. + if (sdResetTimer = 0) then + + -- 200uS wait, no action as the SDRAM starts up. + -- ie. 255 downto 55 + + -- Precharge all banks + if(sdInResetCounter = 55) then + sdCmd := CMD_PRECHARGE; + SDRAM_ADDR(10) <= '1'; + end if; + + -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after + -- the other. + if(sdInResetCounter >= 40 and sdInResetCounter <= 48) then + sdCmd := CMD_AUTO_REFRESH; + end if; + + -- Load the Mode register with our parameters. + if(sdInResetCounter = 39) then + sdCmd := CMD_LOAD_MODE; + SDRAM_ADDR <= MODE; + end if; + + -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after + -- the other. + if(sdInResetCounter >= 30 and sdInResetCounter <= 38) then + sdCmd := CMD_AUTO_REFRESH; + end if; + + -- SDRAM ready. + if(sdInResetCounter = 20) then + sdIsReady <= '1'; + end if; + end if; + + else + + -- Counter to time periods between autorefresh. + sdRefreshCount <= sdRefreshCount + 1; + + -- This mechanism is used to reduce the possibility of metastability issues due to differing clocks. + -- We only act after both Busy signals are high, thus one SDRAM clock after cpuBusy goes high. + sdBusy <= cpuBusy; + + -- If the SDRAM has completed its transaction and the CPU has acknowledged it, remove the signals. + if (sdDone = '1' and cpuDoneAck = '1') then + sdDone <= '0'; + end if; + + -- Auto refresh. On timeout it kicks in so that ROWS auto refreshes are + -- issued in a tRFC period. Other bus operations are stalled during this period. + if (sdRefreshCount > REFRESH_PERIOD and sdCycle = 0) then + sdAutoRefresh <= '1'; + sdRefreshCount <= (others => '0'); + sdCmd := CMD_PRECHARGE; + SDRAM_ADDR(10) <= '1'; + sdActiveBank <= (others => '0'); + sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0')); + + -- In auto refresh period. + elsif (sdAutoRefresh = '1') then + + -- while the cycle is active count. + sdCycle <= sdCycle + 1; + case (sdCycle) is + when CYCLE_RFSH_START => + sdCmd := CMD_AUTO_REFRESH; + + when CYCLE_RFSH_END => + -- reset the count. + sdAutoRefresh <= '0'; + sdCycle <= 0; + + when others => + end case; + + elsif (((cpuBusy = '1' and sdBusy = '1') and sdCycle = 0) or sdCycle /= 0) then + + -- while the cycle is active count. + sdCycle <= sdCycle + 1; + case (sdCycle) is + + when CYCLE_PRECHARGE => + -- If the bank is not open then no need to precharge, move onto RAS. + if (sdActiveBank(cpuBank) = '0') then + sdCycle <= CYCLE_RAS_START; + + -- If the requested row is already active, go to CAS for immediate access to this row. + elsif (sdActiveRow(cpuBank) = cpuRow) then + sdCycle <= CYCLE_CAS_START; + + -- Otherwise we close out the open bank by issuing a PRECHARGE. + else + sdCmd := CMD_PRECHARGE; + SDRAM_ADDR(10) <= '0'; + SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); + sdActiveBank(cpuBank) <= '0'; -- Store flag to indicate which bank is being made active. + end if; + + -- Open the requested row. + when CYCLE_RAS_START => + sdCmd := CMD_ACTIVE; + SDRAM_ADDR <= cpuRow; -- Addr presented to SDRAM as row address. + SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Addr presented to SDRAM as bank select. + sdActiveRow(cpuBank) <= cpuRow; -- Store number of row being made active + sdActiveBank(cpuBank) <= '1'; -- Store flag to indicate which bank is being made active. + + -- CAS start, for 32 bit chips, only 1 CAS cycle is needed, for 16bit chips we need 2 to read/write 2x16bit words. + when CYCLE_CAS_START => + + -- If writing, setup for a write with preset mask. + if (cpuIsWriting = '1') then + + if SDRAM_DATAWIDTH = 32 then + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 2) & '0' & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing 32bit data with no auto precharge + SDRAM_DQ <= cpuDataIn; -- Assign corresponding data to the SDRAM databus. + SDRAM_DQM <= not cpuDQM(3 downto 0); + sdCycle <= CYCLE_END; + + elsif SDRAM_DATAWIDTH = 16 then + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge + SDRAM_DQ <= cpuDataIn((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH); -- Assign corresponding data to the SDRAM databus. + SDRAM_DQM <= not cpuDQM(3 downto 2); + else + report "SDRAM datawidth parameter invalid, should be 16 or 32!" severity error; + end if; + sdCmd := CMD_WRITE; + + else + -- Setup for a read. + sdCmd := CMD_READ; + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge + SDRAM_DQM <= "00"; -- For reads dont mask the data output. + end if; + + when CYCLE_CAS_END => + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '1')), SDRAM_ROW_BITS)); -- CAS address = Next address accessing second 16bit location within the 32bit external alignment with no auto precharge + + -- When writing, setup for a write with preset mask with the correct word. + if (cpuIsWriting = '1') then + SDRAM_DQM <= not cpuDQM(1 downto 0); + SDRAM_DQ <= cpuDataIn(SDRAM_DATAWIDTH-1 downto 0); + sdDone <= '1'; + sdCycle <= CYCLE_END; + sdCmd := CMD_WRITE; + else + -- Setup for a read, change to write if flag set. + sdCmd := CMD_READ; + SDRAM_DQM <= "00"; -- For reads dont mask the data output. + end if; + + -- Data is available CAS Latency clocks after the read request. For 32bit chips, only 1 cycle is needed, for 16bit we need 2 read cycles of + -- 16 bits each. + when CYCLE_READ_START => + + if SDRAM_DATAWIDTH = 32 then + sdDataOut <= SDRAM_DQ; + sdCycle <= CYCLE_END; + + elsif SDRAM_DATAWIDTH = 16 then + sdDataOut((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH) <= SDRAM_DQ; + else + report "SDRAM datawidth parameter invalid, should be 16 or 32!" severity error; + end if; + + -- Second and final read cycle for 16bit SDRAM chips to create a 32bit word. + when CYCLE_READ_END => + sdDataOut(SDRAM_DATAWIDTH-1 downto 0) <= SDRAM_DQ; + + when CYCLE_END => + sdDone <= '1'; + sdCycle <= 0; + + -- Other states are wait states, waiting for the correct time slot for SDRAM access. + when others => + end case; + else + sdCycle <= 0; + end if; + end if; + + -- drive control signals according to current command + SDRAM_CKE <= sdCmd(4); + SDRAM_CS_n <= sdCmd(3); + SDRAM_RAS_n <= sdCmd(2); + SDRAM_CAS_n <= sdCmd(1); + SDRAM_WE_n <= sdCmd(0); + end if; + + end process; + + + -- CPU/WishBone side logic. When the CPU initiates a transaction, capture the signals and the captured values are used within the SDRAM domain. This is to prevent + -- any changes CPU side or differing signal lengths due to CPU architecture or clock being propogated into the SDRAM domain. The CPU only needs to know + -- when the transation is complete and data read. + -- + process(ALL) + begin + if (WB_RST_I = '1') then + cpuDoneLast <= '0'; + cpuBusy <= '0'; + cpuBank <= 0; + cpuRow <= (others => '0'); + cpuCol <= (others => '0'); + cpuDQM <= (others => '1'); + cpuDoneAck <= '0'; + cpuIsWriting <= '0'; + wbACK <= '0'; + + -- Wait for the SDRAM to become ready by holding the CPU in a wait state. + elsif sdIsReady = '0' then + cpuBusy <= '1'; + + elsif rising_edge(WB_CLK) then + + -- Detect a Wishbone cycle and commence an SDRAM access. + if (WB_STB_I = '1' and WB_CYC_I = '1' and cpuBusy = '0') then + cpuBusy <= '1'; + cpuBank <= to_integer(unsigned(WB_ADR_I(SDRAM_ADDR_BITS-1 downto SDRAM_ARRAY_BITS+1))); + cpuRow <= std_logic_vector(to_unsigned(to_integer(unsigned(WB_ADR_I(SDRAM_ARRAY_BITS downto SDRAM_COLUMN_BITS+1))), SDRAM_ROW_BITS)); + cpuCol <= WB_ADR_I(SDRAM_COLUMN_BITS downto 2) & '0'; + cpuDQM <= WB_SEL_I; + cpuDataIn <= WB_DATA_I; + end if; + + if (WB_STB_I = '1' and WB_CYC_I = '1' and cpuBusy = '1') then + cpuIsWriting <= WB_WE_I; + end if; + + -- Note SDRAM activity via a previous/last signal. + cpuDoneLast <= sdDone; + + -- If there has been a change in the SDRAM activity and it hasnt been acknowleged, send the ACK and use the cycle to latch the retrieved data. + if (cpuDoneLast = '0' and sdDone = '1') then + cpuDoneAck <= '1'; + WB_DATA_O <= sdDataOut; + end if; + + -- If we are at the end of an active Cycle and the acknowledge to the sdram fsm has been sent, clear all signals and assert the Wishbone Ack to + -- complete. + if (cpuDoneLast = '1' and sdDone = '0' and cpuDoneAck = '1' and wbACK = '0') then + cpuBusy <= '0'; + cpuDoneAck <= '0'; + cpuIsWriting <= '0'; + wbACK <= '1'; + else + wbACK <= '0'; + end if; + + end if; + end process; + + -- System bus control signals. + SDRAM_READY <= sdIsReady; + + -- Wishbone bus control signals. + WB_ACK_O <= wbACK; + + --- Throttle not needed. + WB_HALT_O <= '0'; + + --- Error not yet implemented. + WB_ERR_O <= '0'; + +end Structure; diff --git a/zpu/devices/WishBone/SDRAM/wbsdram_cached.vhd b/zpu/devices/WishBone/SDRAM/wbsdram_cached.vhd new file mode 100644 index 0000000..2e9939f --- /dev/null +++ b/zpu/devices/WishBone/SDRAM/wbsdram_cached.vhd @@ -0,0 +1,712 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: wbsdram_cached.vhd +-- Created: September 2019 +-- Author: Philip Smart +-- Description: A configurable cached sdram controller for use with the ZPU EVO Processor and SoC. +-- The module is instantiated with the parameters to describe the underlying SDRAM chip +-- and in theory should work with most 16/32 bit SDRAM chips if they adhere to the SDRAM +-- standard. +-- Credits: Stephen J. Leary 2013-2014 - Basic sdram cycle structure of this module was based on +-- the verilog MT48LC16M16 chip controller written by Stephen. +-- Copyright: (c) 2019-2020 Philip Smart +-- +-- History: September 2019 - Initial module translation to VHDL based on Stephen J. Leary's Verilog +-- source code. +-- November 2019 - Adapted for the system bus for use when no Wishbone interface is +-- instantiated in the ZPU Evo. +-- December 2019 - Extensive changes, metability stability, autorefresh to ACTIVE timing +-- and parameterisation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_soc_pkg.all; +use work.zpu_pkg.all; + +entity WBSDRAM is + generic ( + MAX_DATACACHE_BITS : integer := 4; -- Maximum size in addr bits of 32bit datacache for burst transactions. + SDRAM_ROWS : integer := 4096; -- Number of Rows in the SDRAM. + SDRAM_COLUMNS : integer := 256; -- Number of Columns in an SDRAM page (ie. 1 row). + SDRAM_BANKS : integer := 4; -- Number of banks in the SDRAM. + SDRAM_DATAWIDTH : integer := 16; -- Data width of SDRAM chip (16, 32). + SDRAM_CLK_FREQ : integer := 100000000; -- Frequency of the SDRAM clock in Hertz. + SDRAM_tRCD : integer := 20; -- tRCD - RAS to CAS minimum period (in ns). + SDRAM_tRP : integer := 20; -- tRP - Precharge delay, min time for a precharge command to complete (in ns). + SDRAM_tRFC : integer := 70; -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns + SDRAM_tREF : integer := 64 -- tREF - period of time a complete refresh of all rows is made within (in ms). + ); + port ( + -- SDRAM Interface + SDRAM_CLK : in std_logic; -- SDRAM is accessed at given clock, frequency specified in RAM_CLK. + SDRAM_RST : in std_logic; -- Reset the sdram controller. + SDRAM_CKE : out std_logic; -- Clock enable. + SDRAM_DQ : inout std_logic_vector(SDRAM_DATAWIDTH-1 downto 0); -- Bidirectional data bus + SDRAM_ADDR : out std_logic_vector(log2ceil(SDRAM_ROWS) - 1 downto 0); -- Multiplexed address bus + SDRAM_DQM : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of byte masks dependent on number of banks. + SDRAM_BA : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of banks in SDRAM + SDRAM_CS_n : out std_logic; -- Single chip select + SDRAM_WE_n : out std_logic; -- Write enable + SDRAM_RAS_n : out std_logic; -- Row address select + SDRAM_CAS_n : out std_logic; -- Columns address select + SDRAM_READY : out std_logic; -- SD ready. + + -- WishBone interface. + WB_CLK : in std_logic; -- Master clock at which the Wishbone interface operates. + WB_RST_I : in std_logic; -- high active sync reset + WB_DATA_I : in std_logic_vector(WORD_32BIT_RANGE); -- Data input from Master + WB_DATA_O : out std_logic_vector(WORD_32BIT_RANGE); -- Data output to Master + WB_ACK_O : out std_logic; + WB_ADR_I : in std_logic_vector(log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS) downto 0); + WB_SEL_I : in std_logic_vector(3 downto 0); + WB_CTI_I : in std_logic_vector(2 downto 0); -- 000 Classic cycle, 001 Constant address burst cycle, 010 Incrementing burst cycle, 111 End-of-Burst + WB_STB_I : in std_logic; + WB_CYC_I : in std_logic; -- cpu/chipset requests cycle + WB_WE_I : in std_logic; -- cpu/chipset requests write + WB_TGC_I : in std_logic_vector(06 downto 0); -- cycle tag + WB_HALT_O : out std_logic; -- throttle master + WB_ERR_O : out std_logic -- abnormal cycle termination + ); +end WBSDRAM; + +architecture Structure of WBSDRAM is + + -- Constants to define the structure of the SDRAM in bits for provisioning of signals. + constant SDRAM_ROW_BITS : integer := log2ceil(SDRAM_ROWS); + constant SDRAM_COLUMN_BITS : integer := log2ceil(SDRAM_COLUMNS); + constant SDRAM_ARRAY_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS); + constant SDRAM_BANK_BITS : integer := log2ceil(SDRAM_BANKS); + constant SDRAM_ADDR_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS * (SDRAM_DATAWIDTH/8)); + + -- Command table for a standard SDRAM. + -- + -- Name (Function) CKE CS# RAS# CAS# WE# DQM ADDR DQ + -- COMMAND INHIBIT (NOP) H H X X X X X X + -- NO OPERATION (NOP) H L H H H X X X + -- ACTIVE (select bank and activate row) H L L H H X Bank/row X + -- READ (select bank and column, and start READ burst) H L H L H L/H Bank/col X + -- WRITE (select bank and column, and start WRITE burst) H L H L L L/H Bank/col Valid + -- BURST TERMINATE H L H H L X X Active + -- PRECHARGE (Deactivate row in bank or banks) H L L H L X Code X + -- AUTO REFRESH or SELF REFRESH (enter self refresh mode) H L L L H X X X + -- LOAD MODE REGISTER H L L L L X Op-code X + -- Write enable/output enable H X X X X L X Active + -- Write inhibit/output High-Z H X X X X H X High-Z + -- Self Refresh Entry L L L L H X X X + -- Self Refresh Exit (Device is idle) H H X X X X X X + -- Self Refresh Exit (Device is in Self Refresh state) H L H H X X X X + -- Clock suspend mode Entry L X X X X X X X + -- Clock suspend mode Exit H X X X X X X X + -- Power down mode Entry (Device is idle) L H X X X X X X + -- Power down mode Entry (Device is Active) L L H H X X X X + -- Power down mode Exit (Any state) H H X X X X X X + -- Power down mode Exit (Device is powered down) H L H H X X X X + + constant CMD_INHIBIT : std_logic_vector(4 downto 0) := "11111"; + constant CMD_NOP : std_logic_vector(4 downto 0) := "10111"; + constant CMD_ACTIVE : std_logic_vector(4 downto 0) := "10011"; + constant CMD_READ : std_logic_vector(4 downto 0) := "10101"; + constant CMD_WRITE : std_logic_vector(4 downto 0) := "10100"; + constant CMD_BURST_TERMINATE : std_logic_vector(4 downto 0) := "10110"; + constant CMD_PRECHARGE : std_logic_vector(4 downto 0) := "10010"; + constant CMD_AUTO_REFRESH : std_logic_vector(4 downto 0) := "10001"; + constant CMD_LOAD_MODE : std_logic_vector(4 downto 0) := "10000"; + constant CMD_SELF_REFRESH_START : std_logic_vector(4 downto 0) := "00001"; + constant CMD_SELF_REFRESH_END : std_logic_vector(4 downto 0) := "10110"; + constant CMD_CLOCK_SUSPEND : std_logic_vector(4 downto 0) := "00000"; + constant CMD_CLOCK_RESTORE : std_logic_vector(4 downto 0) := "10000"; + constant CMD_POWER_DOWN : std_logic_vector(4 downto 0) := "01000"; + constant CMD_POWER_RESTORE : std_logic_vector(4 downto 0) := "01100"; + + -- Load Mode Register setting for a standard SDRAM. + -- + -- xx:10 = Reserved : + -- 9 = Write Burst Mode : 0 = Programmed Burst Length, 1 = Single Location Access + -- 8:7 = Operating Mode : 00 = Standard Operation, all other values reserved. + -- 6:4 = CAS Latency : 010 = 2, 011 = 3, all other values reserved. + -- 3 = Burst Type : 0 = Sequential, 1 = Interleaved. + -- 2:0 = Burst Length : When 000 = 1, 001 = 2, 010 = 4, 011 = 8, all others reserved except 111 when BT = 0 sets full page access. + -- | A12-A10 | A9  A8-A7 | A6 A5 A4 | A3  A2 A1 A0 | + -- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len| + constant WRITE_BURST_MODE : std_logic := '1'; + constant OP_MODE : std_logic_vector(1 downto 0) := "00"; + constant CAS_LATENCY : std_logic_vector(2 downto 0) := "011"; + constant BURST_TYPE : std_logic := '0'; + constant BURST_LENGTH : std_logic_vector(2 downto 0) := "111"; + constant MODE : std_logic_vector(SDRAM_ROW_BITS-1 downto 0) := std_logic_vector(to_unsigned(to_integer(unsigned("00" & WRITE_BURST_MODE & OP_MODE & CAS_LATENCY & BURST_TYPE & BURST_LENGTH)), SDRAM_ROW_BITS)); + + -- FSM Cycle States governed in units of time, the state changes location according to the configurable parameters to ensure correct actuation at the correct time. + -- + constant CYCLE_PRECHARGE : integer := 0; -- ~0 + constant CYCLE_RAS_START : integer := clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ); -- ~3 + constant CYCLE_CAS_START : integer := CYCLE_RAS_START + clockTicks(SDRAM_tRCD, SDRAM_CLK_FREQ); -- ~3 + tRCD + constant CYCLE_WRITE_END : integer := CYCLE_CAS_START + 1; -- ~4 + tRCD + constant CYCLE_READ_START : integer := CYCLE_CAS_START + to_integer(unsigned(CAS_LATENCY)) + 1; -- ~3 + tRCD + CAS_LATENCY + constant CYCLE_READ_END : integer := CYCLE_READ_START + 1; -- ~4 + tRCD + CAS_LATENCY + constant CYCLE_END : integer := CYCLE_READ_END + 1; -- ~9 + tRCD + CAS_LATENCY + constant CYCLE_RFSH_START : integer := clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ); -- ~tRP + constant CYCLE_RFSH_END : integer := CYCLE_RFSH_START + clockTicks(SDRAM_tRFC, SDRAM_CLK_FREQ) + clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ) + 1; -- ~tRP (start) + tRFC (min autorefresh time) + tRP (end) in clock ticks. + + -- Period in clock cycles between SDRAM refresh cycles. This equates to tREF / SDRAM_ROWS to evenly divide the time, then subtract the length of the refresh period as this is + -- the time it takes when a refresh starts until completion. + constant REFRESH_PERIOD : integer := (((SDRAM_tREF * SDRAM_CLK_FREQ ) / SDRAM_ROWS) - (SDRAM_tRFC * 1000)) / 1000; + + -- Array of row addresses, one per bank, to indicate the row in use per bank. + type BankArray is array(natural range 0 to SDRAM_BANKS-1) of std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + type BankCacheArray is array(natural range 0 to SDRAM_BANKS-1) of std_logic_vector(((SDRAM_ROW_BITS-1)+SDRAM_BANK_BITS) downto 0); + + -- SDRAM domain signals. + signal sdBusy : std_logic; + signal sdCycle : integer range 0 to 31; + signal sdDone : std_logic; + shared variable sdCmd : std_logic_vector(4 downto 0); + signal sdRefreshCount : unsigned(11 downto 0); + signal sdAutoRefresh : std_logic; + signal sdResetTimer : unsigned(WORD_8BIT_RANGE); + signal sdInResetCounter : unsigned(WORD_8BIT_RANGE); + signal sdIsReady : std_logic; + signal sdActiveRow : BankArray; + signal sdActiveBank : std_logic_vector(1 downto 0); + signal sdWriteColumnAddr : unsigned(SDRAM_COLUMN_BITS-1 downto 0); -- Address at byte level as bit 0 is used as part of the fifo write enable. + signal sdWriteCnt : integer range 0 to SDRAM_COLUMNS-1; + + -- CPU domain signals. + signal cpuBusy : std_logic; + signal cpuDQM : std_logic_vector(3 downto 0); + signal cpuBank : natural range 0 to SDRAM_BANKS-1; + signal cpuRow : std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + signal cpuCol : std_logic_vector(SDRAM_COLUMN_BITS-1 downto 0); + signal cpuDataOut : std_logic_vector(WORD_32BIT_RANGE); + signal cpuDataIn : std_logic_vector(WORD_32BIT_RANGE); + signal cpuDoneLast : std_logic; + signal cpuIsWriting : std_logic; + signal cpuLastEN : std_logic; + signal cpuCachedBank : std_logic_vector(SDRAM_BANK_BITS-1 downto 0); + signal cpuCachedRow : BankCacheArray; + signal wbACK : std_logic; + + -- Infer a BRAM array for 4 banks of 16bit words. 32bit is created by 2 arrays. + type ramArray is array(natural range 0 to ((SDRAM_COLUMNS/2)*4)-1) of std_logic_vector(WORD_8BIT_RANGE); + + -- Declare the BRAM arrays for 32bit as a set of 4 x 8bit banks. + shared variable fifoCache_3 : ramArray := + ( + others => X"00" + ); + shared variable fifoCache_2 : ramArray := + ( + others => X"00" + ); + shared variable fifoCache_1 : ramArray := + ( + others => X"00" + ); + shared variable fifoCache_0 : ramArray := + ( + others => X"00" + ); + + -- Fifo control signals. + signal fifoDataOutHi : std_logic_vector(WORD_16BIT_RANGE); + signal fifoDataOutLo : std_logic_vector(WORD_16BIT_RANGE); + signal fifoDataInHi : std_logic_vector(WORD_16BIT_RANGE); + signal fifoDataInLo : std_logic_vector(WORD_16BIT_RANGE); + signal fifoSdWREN_1 : std_logic; + signal fifoSdWREN_0 : std_logic; + signal fifoCPUWREN_3 : std_logic; + signal fifoCPUWREN_2 : std_logic; + signal fifoCPUWREN_1 : std_logic; + signal fifoCPUWREN_0 : std_logic; +begin + + -- Main FSM for SDRAM control and refresh. + process(ALL) + begin + + if (SDRAM_RST = '1') then + sdResetTimer <= (others => '0'); -- 0 upto 127 + sdInResetCounter <= (others => '1'); -- 255 downto 0 + sdAutoRefresh <= '0'; + sdRefreshCount <= (others => '0'); + sdActiveBank <= (others => '0'); + sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0')); + sdIsReady <= '0'; + sdCmd := CMD_AUTO_REFRESH; + SDRAM_DQM <= (others => '1'); + sdCycle <= 0; + sdDone <= '0'; + fifoSdWREN_0 <= '0'; + fifoSdWREN_1 <= '0'; + sdWriteColumnAddr <= (others => '0'); + + elsif rising_edge(SDRAM_CLK) then + + -- Write Enables are only 1 clock wide, clear on each cycle. + fifoSdWREN_1 <= '0'; + fifoSdWREN_0 <= '0'; + + -- Tri-state control, set the SDRAM databus to tri-state if we are not in write mode. + if (cpuIsWriting = '0') then + SDRAM_DQ <= (others => 'Z'); + end if; + + -- If no specific command given the default is NOP. + sdCmd := CMD_NOP; + + -- Initialisation on power up or reset. The SDRAM must be given at least 200uS to initialise and a fixed setup pattern applied. + if (sdIsReady = '0') then + sdResetTimer <= sdResetTimer + 1; + + -- 1uS timer. + if (sdResetTimer = SDRAM_CLK_FREQ/1000000) then + sdResetTimer <= (others => '0'); + sdInResetCounter <= sdInResetCounter - 1; + end if; + + -- Every 1uS check for the next init action. + if (sdResetTimer = 0) then + + -- 200uS wait, no action as the SDRAM starts up. + -- ie. 255 downto 55 + + -- Precharge all banks + if(sdInResetCounter = 55) then + sdCmd := CMD_PRECHARGE; + SDRAM_ADDR(10) <= '1'; + end if; + + -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after + -- the other. + if(sdInResetCounter >= 40 and sdInResetCounter <= 48) then + sdCmd := CMD_AUTO_REFRESH; + end if; + + -- Load the Mode register with our parameters. + if(sdInResetCounter = 39) then + sdCmd := CMD_LOAD_MODE; + SDRAM_ADDR <= MODE; + end if; + + -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after + -- the other. + if(sdInResetCounter >= 30 and sdInResetCounter <= 38) then + sdCmd := CMD_AUTO_REFRESH; + end if; + + -- SDRAM ready. + if(sdInResetCounter = 20) then + sdIsReady <= '1'; + end if; + end if; + + else + + -- Counter to time periods between autorefresh. + sdRefreshCount <= sdRefreshCount + 1; + + -- This mechanism is used to reduce the possibility of metastability issues due to differing clocks. + -- We only act after both Busy signals are high, thus one SDRAM clock after cpuBusy goes high. + sdBusy <= cpuBusy; + + -- Auto refresh. On timeout it kicks in so that ROWS auto refreshes are + -- issued in a tRFC period. Other bus operations are stalled during this period. + if (sdRefreshCount > REFRESH_PERIOD and sdCycle = 0) then + sdAutoRefresh <= '1'; + sdRefreshCount <= (others => '0'); + sdCmd := CMD_PRECHARGE; + SDRAM_ADDR(10) <= '1'; + sdActiveBank <= (others => '0'); + sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0')); + + -- In auto refresh period. + elsif (sdAutoRefresh = '1') then + + -- while the cycle is active count. + sdCycle <= sdCycle + 1; + case (sdCycle) is + when CYCLE_RFSH_START => + sdCmd := CMD_AUTO_REFRESH; + + when CYCLE_RFSH_END => + -- reset the count. + sdAutoRefresh <= '0'; + sdCycle <= 0; + + when others => + end case; + + elsif ((cpuBusy = '1' and sdCycle = 0) or sdCycle /= 0) then -- or (sdCycle = 0 and CS = '1')) then + + -- while the cycle is active count. + sdCycle <= sdCycle + 1; + case (sdCycle) is + + when CYCLE_PRECHARGE => + -- If the bank is not open then no need to precharge, move onto RAS. + if (sdActiveBank(cpuBank) = '0') then + sdCycle <= CYCLE_RAS_START; + + -- If the requested row is already active, go to CAS for immediate access to this row. + elsif (sdActiveRow(cpuBank) = cpuRow) then + sdCycle <= CYCLE_CAS_START; + + -- Otherwise we close out the open bank by issuing a PRECHARGE. + else + sdCmd := CMD_PRECHARGE; + SDRAM_ADDR(10) <= '0'; + SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); + sdActiveBank(cpuBank) <= '0'; -- Store flag to indicate which bank is being made active. + end if; + + -- Open the requested row. + when CYCLE_RAS_START => + sdCmd := CMD_ACTIVE; + SDRAM_ADDR <= cpuRow; -- Addr presented to SDRAM as row address. + SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Addr presented to SDRAM as bank select. + sdActiveRow(cpuBank) <= cpuRow; -- Store number of row being made active + sdActiveBank(cpuBank) <= '1'; -- Store flag to indicate which bank is being made active. + + -- CAS start, for 32 bit chips, only 1 CAS cycle is needed, for 16bit chips we need 2 to read/write 2x16bit words. + when CYCLE_CAS_START => + -- If writing, setup for a write with preset mask. + if (cpuIsWriting = '1') then + sdCmd := CMD_WRITE; + if SDRAM_DATAWIDTH = 32 then + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 2) & '0' & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing 32bit data with no auto precharge + SDRAM_DQ <= cpuDataIn; -- Assign corresponding data to the SDRAM databus. + SDRAM_DQM <= not cpuDQM(3 downto 0); + sdDone <= '1'; + sdCycle <= CYCLE_END; + + -- A fake statement used to convince Quartus Prime to infer block ram for the fifo and not use registers. + fifoDataInHi <= fifoDataOutHi; + fifoDataInLo <= fifoDataOutLo; + + elsif SDRAM_DATAWIDTH = 16 then + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge + SDRAM_DQ <= cpuDataIn((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH); -- Assign corresponding data to the SDRAM databus. + SDRAM_DQM <= not cpuDQM(3 downto 2); + + -- A fake statement used to convince Quartus Prime to infer block ram for the fifo and not use registers. + fifoDataInHi <= fifoDataOutHi; + else + report "SDRAM datawidth parameter invalid, should be 16 or 32!" severity error; + end if; + + else + -- Setup for a read. + sdCmd := CMD_READ; + SDRAM_ADDR <= (others => '0'); + SDRAM_DQM <= "00"; -- For reads dont mask the data output. + sdWriteCnt <= SDRAM_COLUMNS-1; + sdWriteColumnAddr <= (others => '1'); + end if; + + -- For writes, this state writes out the second word of a 32bit word if we have a 16bit wide SDRAM chip. + -- + when CYCLE_WRITE_END => + -- When writing, setup for a write with preset mask with the correct word. + if (cpuIsWriting = '1') then + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '1')), SDRAM_ROW_BITS)); -- CAS address = Next address accessing second 16bit location within the 32bit external alignment with no auto precharge + sdCmd := CMD_WRITE; + SDRAM_DQM <= not cpuDQM(1 downto 0); + SDRAM_DQ <= cpuDataIn(SDRAM_DATAWIDTH-1 downto 0); + sdDone <= '1'; + sdCycle <= CYCLE_END; + + -- A fake statement used to convince Quartus Prime to infer block ram for the fifo and not use registers. + fifoDataInLo <= fifoDataOutLo; + end if; + + -- Data is available after CAS Latency (2 or 3) clocks after the read request. + -- The data is read as a full page burst, 1 clock per word. + when CYCLE_READ_START => + + if SDRAM_DATAWIDTH = 32 then + fifoSdWREN_1 <= '1'; + fifoSdWREN_0 <= '1'; + sdWriteCnt <= sdWriteCnt - 2; + sdWriteColumnAddr <= sdWriteColumnAddr + 2; + fifoDataInHi <= SDRAM_DQ(WORD_UPPER_16BIT_RANGE); + fifoDataInLo <= SDRAM_DQ(WORD_LOWER_16BIT_RANGE); + + if sdWriteCnt > 1 then + sdCycle <= CYCLE_READ_START; + end if; + + elsif SDRAM_DATAWIDTH = 16 then + if fifoSdWREN_1 = '0' then + fifoSdWREN_1 <= '1'; + fifoDataInHi <= SDRAM_DQ; + else + fifoSdWREN_0 <= '1'; + fifoDataInLo <= SDRAM_DQ; + end if; + sdWriteCnt <= sdWriteCnt - 1; + sdWriteColumnAddr <= sdWriteColumnAddr + 1; + + if sdWriteCnt > 0 then + sdCycle <= CYCLE_READ_START; + end if; + + else + report "SDRAM datawidth parameter invalid, should be 16 or 32!" severity error; + end if; + + when CYCLE_READ_END => + sdDone <= '1'; + + when CYCLE_END => + sdCycle <= 0; + sdDone <= '0'; + + -- Other states are wait states, waiting for the correct time slot for SDRAM access. + when others => + end case; + else + sdCycle <= 0; + end if; + end if; + + -- drive control signals according to current command + SDRAM_CKE <= sdCmd(4); + SDRAM_CS_n <= sdCmd(3); + SDRAM_RAS_n <= sdCmd(2); + SDRAM_CAS_n <= sdCmd(1); + SDRAM_WE_n <= sdCmd(0); + end if; + end process; + + + -- CPU/BUS side logic. When the CPU initiates a transaction, capture the signals and the captured values are used within the SDRAM domain. This is to prevent + -- any changes CPU side or differing signal lengths due to CPU architecture or clock being propogated into the SDRAM domain. The CPU only needs to know + -- when the transation is complete and data read. + -- + process(ALL) + variable bank : std_logic_vector(1 downto 0); + variable row : std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + variable writeThru : std_logic; + begin + + -- Setup the bank and row as variables to make code reading easier. + bank := WB_ADR_I(SDRAM_ADDR_BITS-1) & WB_ADR_I((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) downto (SDRAM_COLUMN_BITS+1)); + row := WB_ADR_I(SDRAM_ADDR_BITS-2 downto (SDRAM_COLUMN_BITS+SDRAM_BANK_BITS)); + + -- For write operations, if the cached page row for the current bank is the same as the row given by the cpu then we write to both the SDRAM and to the cache. + if cpuCachedBank(to_integer(unsigned(bank))) = '1' and cpuCachedRow(to_integer(unsigned(bank))) = WB_ADR_I(SDRAM_ADDR_BITS-1) & WB_ADR_I((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) downto (SDRAM_COLUMN_BITS+1)) & row then + writeThru := '1'; + else + writeThru := '0'; + end if; + + -- Setup signals to initial state, critical they start at the right values. + if (WB_RST_I = '1') then + cpuDoneLast <= '0'; + cpuBusy <= '0'; + cpuBank <= 0; + cpuRow <= (others => '0'); + cpuCol <= (others => '0'); + cpuDQM <= (others => '1'); + cpuLastEN <= '0'; + cpuCachedBank <= (others => '0'); + cpuCachedRow <= ( others => (others => '0') ); + cpuIsWriting <= '0'; + fifoCPUWREN_3 <= '0'; + fifoCPUWREN_2 <= '0'; + fifoCPUWREN_1 <= '0'; + fifoCPUWREN_0 <= '0'; + wbACK <= '0'; + + -- Wait for the SDRAM to become ready by holding the CPU in a wait state. + elsif sdIsReady = '0' then + cpuBusy <= '1'; + + elsif rising_edge(WB_CLK) then + + -- CPU Cache writes are only 1 cycle wide, so clear any asserted write. + fifoCPUWREN_3 <= '0'; + fifoCPUWREN_2 <= '0'; + fifoCPUWREN_1 <= '0'; + fifoCPUWREN_0 <= '0'; + + if wbACK = '1' then + wbACK <= '0'; + end if; + + -- Detect a Wishbone cycle and commence an SDRAM access. + if (WB_STB_I = '1' and WB_CYC_I = '1' and cpuBusy = '0' and wbACK = '0') then + + -- Organisation of the memory is as follows: + -- + -- Bank: [(SDRAM_ADDR_BITS-1) .. (SDRAM_ADDR_BITS-1)] & [((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) .. (SDRAM_COLUMN_BITS+1)] + -- Row: [(SDRAM_ADDR_BITS-2) .. (SDRAM_COLUMN_BITS+SDRAM_BANK_BITS)] + -- Column: [(SDRAM_COLUMN_BITS downto 2)] + -- The bank is split so that the Bank MSB splits the SDRAM in 2, upper and lower segment, this is because Stack normally resides in the top upper + -- segment and code in the bottom lower segment. The remaining bank bits are split at the page level such that 2 or more pages residing in different + -- banks are contiguous, hoping to gain a little performance benefit through having a wider spread for code caching and stack caching and write thru. + -- + cpuBank <= to_integer(unsigned(bank)); + cpuRow <= row; + cpuCol <= WB_ADR_I(SDRAM_COLUMN_BITS downto 2) & '0'; + cpuDQM <= WB_SEL_I; + cpuDataIn <= WB_DATA_I; + + -- For write operations, we write direct to memory. If the data is in cache then a write-thru is performed to preserve the cached bank. + if WB_WE_I = '1' then + + -- If we are writing to a cached page, update the changed bytes in cache. + if writeThru = '1' then + if WB_SEL_I(0) then + fifoCPUWREN_0 <= '1'; + end if; + if WB_SEL_I(1) then + fifoCPUWREN_1 <= '1'; + end if; + if WB_SEL_I(2) then + fifoCPUWREN_2 <= '1'; + end if; + if WB_SEL_I(3) then + fifoCPUWREN_3 <= '1'; + end if; + end if; + + -- Set the flags, cpuBusy indicates to the SDRAM FSM to perform an operation. + cpuIsWriting <= WB_WE_I; + cpuBusy <= '1'; + + -- For reads, if the row is cached then we just fall through to perform a read operation from cache otherwise the + -- SDRAM needs to be instructed to read a page into cache before reading. + -- + elsif cpuCachedBank(to_integer(unsigned(bank))) = '0' or cpuCachedRow(to_integer(unsigned(bank))) /= WB_ADR_I(SDRAM_ADDR_BITS-1) & WB_ADR_I((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) downto (SDRAM_COLUMN_BITS+1)) & row then + + cpuCachedBank(to_integer(unsigned(bank))) <= '1'; + cpuCachedRow (to_integer(unsigned(bank))) <= WB_ADR_I(SDRAM_ADDR_BITS-1) & WB_ADR_I((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) downto (SDRAM_COLUMN_BITS+1)) & row; + + -- Set the flags, cpuBusy indicates to the SDRAM FSM to perform an operation. + cpuBusy <= '1'; + + else + wbACK <= '1'; + end if; + end if; + + -- Note SDRAM activity via a previous/last signal. + cpuDoneLast <= sdDone; + + -- A change in the Done signal then we end the SDRAM request and release the CPU. + if cpuDoneLast = '1' and sdDone = '0' then + cpuBusy <= '0'; + cpuIsWriting <= '0'; + wbACK <= '1'; + end if; + end if; + end process; + + -- System bus control signals. + SDRAM_READY <= sdIsReady; + + -- Wishbone bus control signals. + WB_ACK_O <= wbACK; + + --- Throttle not needed. + WB_HALT_O <= '0'; + + --- Error not yet implemented. + WB_ERR_O <= '0'; + + ------------------------------------------------------------------------------------------------------------------------- + -- Inferred Dual Port RAM. + -- + -- The dual port ram is used to buffer a full page within the SDRAM, one buffer for each bank. The addressing is such + -- that half of the banks appear in the lower segment of the address space and half in the top segment, the MSB of the + -- SDRAM address is used for the split. This is to cater for stack where typically, on the ZPU, the stack would reside + -- in the very top of memory working down and the applications would reside at the bottom of the memory working up. + -- + ------------------------------------------------------------------------------------------------------------------------- + + -- SDRAM Side of dual port RAM. + -- For Read: fifoDataOutHi <= fifoCache_3(sdWriteColumnAddr) + -- fifoDataOutLo <= fifoCache_0(sdWriteColumnAddr) + -- For Write: fifoCache_3 _1 <= fifoDataIn when sdWriteColumnAddr(0) = '0' + -- fifoCache_2 _0 <= fifoDataIn when sdWriteColumnAddr(0) = '1' + -- fifoSdWREN must be asserted ('1') for write operations. + process(ALL) + variable cacheAddr : unsigned(SDRAM_COLUMN_BITS-2+SDRAM_BANK_BITS downto 0); + begin + -- Setup the address based on the index (sdWriteColumnAddr) and the bank (cpuBank) as the cache is linear for 4 banks. + -- + cacheAddr := to_unsigned(cpuBank, SDRAM_BANK_BITS) & sdWriteColumnAddr(SDRAM_COLUMN_BITS-1 downto 1); + + if rising_edge(SDRAM_CLK) then + if fifoSdWREN_1 = '1' then + fifoCache_3(to_integer(cacheAddr)) := fifoDataInHi(WORD_UPPER_16BIT_RANGE); + fifoCache_2(to_integer(cacheAddr)) := fifoDataInHi(WORD_LOWER_16BIT_RANGE); + else + fifoDataOutHi(WORD_UPPER_16BIT_RANGE) <= fifoCache_3(to_integer(cacheAddr)); + fifoDataOutHi(WORD_LOWER_16BIT_RANGE) <= fifoCache_2(to_integer(cacheAddr)); + end if; + + if fifoSdWREN_0 = '1' then + fifoCache_1(to_integer(cacheAddr)) := fifoDataInLo(WORD_UPPER_16BIT_RANGE); + fifoCache_0(to_integer(cacheAddr)) := fifoDataInLo(WORD_LOWER_16BIT_RANGE); + else + fifoDataOutLo(WORD_UPPER_16BIT_RANGE) <= fifoCache_1(to_integer(cacheAddr)); + fifoDataOutLo(WORD_LOWER_16BIT_RANGE) <= fifoCache_0(to_integer(cacheAddr)); + end if; + end if; + end process; + + -- CPU Side of dual port RAM, byte addressable. + -- For Read: DATA_OUT <= fifoCache(bank + ADDR(COLUMN_BITS .. 2)) + -- For Write: fifoCache(0..3) <= cpuDataIn + process(ALL) + variable cacheAddr : unsigned(SDRAM_COLUMN_BITS-2+SDRAM_BANK_BITS downto 0); + begin + -- Setup the address based on the column address bits, 32 bit aligned and the bank (cpuBank) as the cache is linear for 4 banks. + -- + cacheAddr := to_unsigned(cpuBank, SDRAM_BANK_BITS) & unsigned(WB_ADR_I(SDRAM_COLUMN_BITS downto 2)); + + if rising_edge(WB_CLK) then + if fifoCPUWREN_3 = '1' then + fifoCache_3(to_integer(cacheAddr)) := cpuDataIn(31 downto 24); + else + WB_DATA_O((SDRAM_DATAWIDTH*2)-1 downto ((SDRAM_DATAWIDTH*2)-(SDRAM_DATAWIDTH/2)))<= fifoCache_3(to_integer(unsigned(cacheAddr))); + end if; + + if fifoCPUWREN_2 = '1' then + fifoCache_2(to_integer(cacheAddr)) := cpuDataIn(23 downto 16); + else + WB_DATA_O(((SDRAM_DATAWIDTH*2)-(SDRAM_DATAWIDTH/2))-1 downto SDRAM_DATAWIDTH) <= fifoCache_2(to_integer(unsigned(cacheAddr))); + end if; + + if fifoCPUWREN_1 = '1' then + fifoCache_1(to_integer(cacheAddr)) := cpuDataIn(15 downto 8); + else + WB_DATA_O(SDRAM_DATAWIDTH-1 downto SDRAM_DATAWIDTH/2) <= fifoCache_1(to_integer(unsigned(cacheAddr))); + end if; + + if fifoCPUWREN_0 = '1' then + fifoCache_0(to_integer(cacheAddr)) := cpuDataIn(7 downto 0); + else + WB_DATA_O((SDRAM_DATAWIDTH/2)-1 downto 0) <= fifoCache_0(to_integer(unsigned(cacheAddr))); + end if; + end if; + end process; +end Structure; diff --git a/zpu/devices/WishBone/SRAM/sram.vhd b/zpu/devices/WishBone/SRAM/sram.vhd new file mode 100644 index 0000000..752c2b7 --- /dev/null +++ b/zpu/devices/WishBone/SRAM/sram.vhd @@ -0,0 +1,159 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: sram.vhd +-- Created: September 2019 +-- Author(s): Philip Smart +-- Description: WishBone encapsulation of BRAM memory. +-- +-- Credits: +-- Copyright: (c) 2019 Philip Smart +-- +-- History: September 2019 - Initial creation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_soc_pkg.all; +use work.zpu_pkg.all; + +entity SRAM is + generic ( + addrbits : integer := 16 -- Size, in bits (representing bytes), of total memory to allocate. + ); + port ( + -- Wishbone Bus -- + WB_CLK_I : in std_logic; -- WishBone master clock + WB_RST_I : in std_logic; -- high active sync reset + WB_CYC_I : in std_logic; + WB_TGC_I : in std_logic_vector(06 downto 0); -- cycle tag + WB_ADR_I : in std_logic_vector(addrbits-1 downto 0); -- adr in + WB_DATA_I : in std_logic_vector(31 downto 0); -- write data + WB_DATA_O : out std_logic_vector(31 downto 0); -- read data + WB_SEL_I : in std_logic_vector(03 downto 0); -- data quantity + WB_WE_I : in std_logic; -- write enable + WB_STB_I : in std_logic; -- valid cycle + WB_ACK_O : out std_logic; -- acknowledge + WB_CTI_I : in std_logic_vector(2 downto 0); -- 000 Classic cycle, 001 Constant address burst cycle, 010 Incrementing burst cycle, 111 End-of-Burst + WB_HALT_O : out std_logic; -- throttle master + WB_ERR_O : out std_logic -- abnormal cycle termination + ); +end SRAM; + +architecture Behavioral of SRAM is + + --- Muxed ACK signal. + signal WB_ACK_O_INT : std_logic; + + -- Define memory as an array of 4x8bit blocks to allow for individual byte write/read. + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + others => x"AA" + ); + shared variable RAM1 : ramArray := + ( + others => x"55" + ); + shared variable RAM2 : ramArray := + ( + others => x"AA" + ); + shared variable RAM3 : ramArray := + ( + others => x"55" + ); + +begin + + -- RAM Byte 0 - bits 7 to 0 + process(WB_CLK_I) + begin + if rising_edge(WB_CLK_I) then + if WB_WE_I = '1' and WB_STB_I = '1' and WB_SEL_I(0) = '1' then + RAM0(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2)))) := WB_DATA_I(7 downto 0); + else + WB_DATA_O(7 downto 0) <= RAM0(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - bits 15 to 8 + process(WB_CLK_I) + begin + if rising_edge(WB_CLK_I) then + if WB_WE_I = '1' and WB_STB_I = '1' and WB_SEL_I(1) = '1' then + RAM1(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2)))) := WB_DATA_I(15 downto 8); + else + WB_DATA_O(15 downto 8) <= RAM1(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - bits 23 to 16 + process(WB_CLK_I) + begin + if rising_edge(WB_CLK_I) then + if WB_WE_I = '1' and WB_STB_I = '1' and WB_SEL_I(2) = '1' then + RAM2(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2)))) := WB_DATA_I(23 downto 16); + else + WB_DATA_O(23 downto 16) <= RAM2(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - bits 31 to 24 + process(WB_CLK_I) + begin + if rising_edge(WB_CLK_I) then + if WB_WE_I = '1' and WB_STB_I = '1' and WB_SEL_I(3) = '1' then + RAM3(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2)))) := WB_DATA_I(31 downto 24); + else + WB_DATA_O(31 downto 24) <= RAM3(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- WishBone control. + WISHBONECTL: process(WB_CLK_I) + begin + if rising_edge(WB_CLK_I) then + + --- ACK Control + if (WB_RST_I = '1') then + WB_ACK_O_INT <= '0'; + elsif (WB_CTI_I = "000") or (WB_CTI_I = "111") then + WB_ACK_O_INT <= WB_STB_I and (not WB_ACK_O_INT); + else + WB_ACK_O_INT <= WB_STB_I; + end if; + + end if; + end process; + + --- ACK Signal + WB_ACK_O <= WB_ACK_O_INT; + + --- Throttle + WB_HALT_O <= '0'; + + --- Error + WB_ERR_O <= '0'; + +end Behavioral; diff --git a/zpu/devices/sysbus/BRAM/BootROM.vhd b/zpu/devices/sysbus/BRAM/BootROM.vhd new file mode 120000 index 0000000..dd63ee0 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/BootROM.vhd @@ -0,0 +1 @@ +zOS_BootROM.vhd \ No newline at end of file diff --git a/zpu/devices/sysbus/BRAM/DualPortBootBRAM.vhd b/zpu/devices/sysbus/BRAM/DualPortBootBRAM.vhd new file mode 120000 index 0000000..7ea7ad2 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/DualPortBootBRAM.vhd @@ -0,0 +1 @@ +zOS_DualPortBootBRAM.vhd \ No newline at end of file diff --git a/zpu/devices/sysbus/BRAM/IOCP_BootROM.vhd b/zpu/devices/sysbus/BRAM/IOCP_BootROM.vhd new file mode 100644 index 0000000..f495024 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/IOCP_BootROM.vhd @@ -0,0 +1,1121 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com +-- Modified by Philip Smart 02/2019 for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity BootROM is +port ( + clk : in std_logic; + areset : in std_logic := '0'; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + memBRead : out std_logic_vector(WORD_32BIT_RANGE) +); +end BootROM; + +architecture arch of BootROM is + +type ram_type is array(natural range 0 to (2**(SOC_MAX_ADDR_BRAM_BIT-2))-1) of std_logic_vector(WORD_32BIT_RANGE); + +shared variable ram : ram_type := +( + 0 => x"0b0b0b88", + 1 => x"e0040000", + 2 => x"00000000", + 3 => x"00000000", + 4 => x"00000000", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"88088c08", + 9 => x"90080b0b", + 10 => x"0b888008", + 11 => x"2d900c8c", + 12 => x"0c880c04", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a50400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"09810572", + 51 => x"0a100a72", + 52 => x"0a100a31", + 53 => x"050a8106", + 54 => x"51515351", + 55 => x"04000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b88", + 73 => x"c4040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b88a7", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"04067383", + 106 => x"06098105", + 107 => x"8205832b", + 108 => x"0b2b0772", + 109 => x"fc060c51", + 110 => x"51040000", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b0b9f", + 162 => x"d0738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"88ac0400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"88088c08", + 169 => x"90087575", + 170 => x"0b0b0b89", + 171 => x"cf2d5050", + 172 => x"88085690", + 173 => x"0c8c0c88", + 174 => x"0c510400", + 175 => x"00000000", + 176 => x"88088c08", + 177 => x"90087575", + 178 => x"0b0b0b8b", + 179 => x"812d5050", + 180 => x"88085690", + 181 => x"0c8c0c88", + 182 => x"0c510400", + 183 => x"00000000", + 184 => x"72097081", + 185 => x"0509060a", + 186 => x"8106ff05", + 187 => x"70547106", + 188 => x"73097274", + 189 => x"05ff0506", + 190 => x"07515151", + 191 => x"04000000", + 192 => x"72097081", + 193 => x"0509060a", + 194 => x"098106ff", + 195 => x"05705471", + 196 => x"06730972", + 197 => x"7405ff05", + 198 => x"06075151", + 199 => x"51040000", + 200 => x"05ff0504", + 201 => x"00000000", + 202 => x"00000000", + 203 => x"00000000", + 204 => x"00000000", + 205 => x"00000000", + 206 => x"00000000", + 207 => x"00000000", + 208 => x"04000000", + 209 => x"00000000", + 210 => x"00000000", + 211 => x"00000000", + 212 => x"00000000", + 213 => x"00000000", + 214 => x"00000000", + 215 => x"00000000", + 216 => x"71810552", + 217 => x"04000000", + 218 => x"00000000", + 219 => x"00000000", + 220 => x"00000000", + 221 => x"00000000", + 222 => x"00000000", + 223 => x"00000000", + 224 => x"04000000", + 225 => x"00000000", + 226 => x"00000000", + 227 => x"00000000", + 228 => x"00000000", + 229 => x"00000000", + 230 => x"00000000", + 231 => x"00000000", + 232 => x"02840572", + 233 => x"10100552", + 234 => x"04000000", + 235 => x"00000000", + 236 => x"00000000", + 237 => x"00000000", + 238 => x"00000000", + 239 => x"00000000", + 240 => x"00000000", + 241 => x"00000000", + 242 => x"00000000", + 243 => x"00000000", + 244 => x"00000000", + 245 => x"00000000", + 246 => x"00000000", + 247 => x"00000000", + 248 => x"717105ff", + 249 => x"05715351", + 250 => x"020d0400", + 251 => x"00000000", + 252 => x"00000000", + 253 => x"00000000", + 254 => x"00000000", + 255 => x"00000000", + 256 => x"00000404", + 257 => x"04000000", + 258 => x"10101010", + 259 => x"10101010", + 260 => x"10101010", + 261 => x"10101010", + 262 => x"10101010", + 263 => x"10101010", + 264 => x"10101010", + 265 => x"10101053", + 266 => x"51040000", + 267 => x"7381ff06", + 268 => x"73830609", + 269 => x"81058305", + 270 => x"1010102b", + 271 => x"0772fc06", + 272 => x"0c515104", + 273 => x"72728072", + 274 => x"8106ff05", + 275 => x"09720605", + 276 => x"71105272", + 277 => x"0a100a53", + 278 => x"72ed3851", + 279 => x"51535104", + 280 => x"9ff470a0", + 281 => x"a4278e38", + 282 => x"80717084", + 283 => x"05530c0b", + 284 => x"0b0b88e2", + 285 => x"0488fe51", + 286 => x"9e9d0400", + 287 => x"80040088", + 288 => x"fe040000", + 289 => x"00940802", + 290 => x"940cfd3d", + 291 => x"0d805394", + 292 => x"088c0508", + 293 => x"52940888", + 294 => x"05085182", + 295 => x"de3f8808", + 296 => x"70880c54", + 297 => x"853d0d94", + 298 => x"0c049408", + 299 => x"02940cfd", + 300 => x"3d0d8153", + 301 => x"94088c05", + 302 => x"08529408", + 303 => x"88050851", + 304 => x"82b93f88", + 305 => x"0870880c", + 306 => x"54853d0d", + 307 => x"940c0494", + 308 => x"0802940c", + 309 => x"f93d0d80", + 310 => x"0b9408fc", + 311 => x"050c9408", + 312 => x"88050880", + 313 => x"25ab3894", + 314 => x"08880508", + 315 => x"30940888", + 316 => x"050c800b", + 317 => x"9408f405", + 318 => x"0c9408fc", + 319 => x"05088838", + 320 => x"810b9408", + 321 => x"f4050c94", + 322 => x"08f40508", + 323 => x"9408fc05", + 324 => x"0c94088c", + 325 => x"05088025", + 326 => x"ab389408", + 327 => x"8c050830", + 328 => x"94088c05", + 329 => x"0c800b94", + 330 => x"08f0050c", + 331 => x"9408fc05", + 332 => x"08883881", + 333 => x"0b9408f0", + 334 => x"050c9408", + 335 => x"f0050894", + 336 => x"08fc050c", + 337 => x"80539408", + 338 => x"8c050852", + 339 => x"94088805", + 340 => x"085181a7", + 341 => x"3f880870", + 342 => x"9408f805", + 343 => x"0c549408", + 344 => x"fc050880", + 345 => x"2e8c3894", + 346 => x"08f80508", + 347 => x"309408f8", + 348 => x"050c9408", + 349 => x"f8050870", + 350 => x"880c5489", + 351 => x"3d0d940c", + 352 => x"04940802", + 353 => x"940cfb3d", + 354 => x"0d800b94", + 355 => x"08fc050c", + 356 => x"94088805", + 357 => x"08802593", + 358 => x"38940888", + 359 => x"05083094", + 360 => x"0888050c", + 361 => x"810b9408", + 362 => x"fc050c94", + 363 => x"088c0508", + 364 => x"80258c38", + 365 => x"94088c05", + 366 => x"08309408", + 367 => x"8c050c81", + 368 => x"5394088c", + 369 => x"05085294", + 370 => x"08880508", + 371 => x"51ad3f88", + 372 => x"08709408", + 373 => x"f8050c54", + 374 => x"9408fc05", + 375 => x"08802e8c", + 376 => x"389408f8", + 377 => x"05083094", + 378 => x"08f8050c", + 379 => x"9408f805", + 380 => x"0870880c", + 381 => x"54873d0d", + 382 => x"940c0494", + 383 => x"0802940c", + 384 => x"fd3d0d81", + 385 => x"0b9408fc", + 386 => x"050c800b", + 387 => x"9408f805", + 388 => x"0c94088c", + 389 => x"05089408", + 390 => x"88050827", + 391 => x"ac389408", + 392 => x"fc050880", + 393 => x"2ea33880", + 394 => x"0b94088c", + 395 => x"05082499", + 396 => x"3894088c", + 397 => x"05081094", + 398 => x"088c050c", + 399 => x"9408fc05", + 400 => x"08109408", + 401 => x"fc050cc9", + 402 => x"399408fc", + 403 => x"0508802e", + 404 => x"80c93894", + 405 => x"088c0508", + 406 => x"94088805", + 407 => x"0826a138", + 408 => x"94088805", + 409 => x"0894088c", + 410 => x"05083194", + 411 => x"0888050c", + 412 => x"9408f805", + 413 => x"089408fc", + 414 => x"05080794", + 415 => x"08f8050c", + 416 => x"9408fc05", + 417 => x"08812a94", + 418 => x"08fc050c", + 419 => x"94088c05", + 420 => x"08812a94", + 421 => x"088c050c", + 422 => x"ffaf3994", + 423 => x"08900508", + 424 => x"802e8f38", + 425 => x"94088805", + 426 => x"08709408", + 427 => x"f4050c51", + 428 => x"8d399408", + 429 => x"f8050870", + 430 => x"9408f405", + 431 => x"0c519408", + 432 => x"f4050888", + 433 => x"0c853d0d", + 434 => x"940c04ff", + 435 => x"3d0d8188", + 436 => x"0b87c092", + 437 => x"8c0c810b", + 438 => x"87c0928c", + 439 => x"0c850b87", + 440 => x"c0988c0c", + 441 => x"87c0928c", + 442 => x"08708206", + 443 => x"51517080", + 444 => x"2e8a3887", + 445 => x"c0988c08", + 446 => x"5170e938", + 447 => x"87c0928c", + 448 => x"08fc8080", + 449 => x"06527193", + 450 => x"3887c098", + 451 => x"8c085170", + 452 => x"802e8838", + 453 => x"710b0b0b", + 454 => x"9ff0340b", + 455 => x"0b0b9ff0", + 456 => x"33880c83", + 457 => x"3d0d04fa", + 458 => x"3d0d787b", + 459 => x"7d565856", + 460 => x"800b0b0b", + 461 => x"0b9ff033", + 462 => x"81065255", + 463 => x"82527075", + 464 => x"2e098106", + 465 => x"819e3885", + 466 => x"0b87c098", + 467 => x"8c0c7987", + 468 => x"c092800c", + 469 => x"840b87c0", + 470 => x"928c0c87", + 471 => x"c0928c08", + 472 => x"70852a70", + 473 => x"81065152", + 474 => x"5370802e", + 475 => x"a73887c0", + 476 => x"92840870", + 477 => x"81ff0676", + 478 => x"79275253", + 479 => x"5173802e", + 480 => x"90387080", + 481 => x"2e8b3871", + 482 => x"76708105", + 483 => x"5834ff14", + 484 => x"54811555", + 485 => x"72a20651", + 486 => x"70802e8b", + 487 => x"3887c098", + 488 => x"8c085170", + 489 => x"ffb53887", + 490 => x"c0988c08", + 491 => x"51709538", + 492 => x"810b87c0", + 493 => x"928c0c87", + 494 => x"c0928c08", + 495 => x"70820651", + 496 => x"5170f438", + 497 => x"8073fc80", + 498 => x"80065252", + 499 => x"70722e09", + 500 => x"81068f38", + 501 => x"87c0988c", + 502 => x"08517072", + 503 => x"2e098106", + 504 => x"83388152", + 505 => x"71880c88", + 506 => x"3d0d04fe", + 507 => x"3d0d7481", + 508 => x"11337133", + 509 => x"71882b07", + 510 => x"880c5351", + 511 => x"843d0d04", + 512 => x"fd3d0d75", + 513 => x"83113382", + 514 => x"12337190", + 515 => x"2b71882b", + 516 => x"07811433", + 517 => x"70720788", + 518 => x"2b753371", + 519 => x"07880c52", + 520 => x"53545654", + 521 => x"52853d0d", + 522 => x"04f93d0d", + 523 => x"790b0b0b", + 524 => x"9ff40857", + 525 => x"57817727", + 526 => x"80ed3876", + 527 => x"88170827", + 528 => x"80e53875", + 529 => x"33557482", + 530 => x"2e893874", + 531 => x"832eae38", + 532 => x"80d53974", + 533 => x"54761083", + 534 => x"fe065376", + 535 => x"882a8c17", + 536 => x"08055288", + 537 => x"3d705255", + 538 => x"fdbd3f88", + 539 => x"08b93874", + 540 => x"51fef83f", + 541 => x"880883ff", + 542 => x"ff0655ad", + 543 => x"39845476", + 544 => x"822b83fc", + 545 => x"06537687", + 546 => x"2a8c1708", + 547 => x"0552883d", + 548 => x"705255fd", + 549 => x"923f8808", + 550 => x"8e387451", + 551 => x"fee23f88", + 552 => x"08f00a06", + 553 => x"55833981", + 554 => x"5574880c", + 555 => x"893d0d04", + 556 => x"fb3d0d0b", + 557 => x"0b0b9ff4", + 558 => x"08fe1988", + 559 => x"1208fe05", + 560 => x"55565480", + 561 => x"56747327", + 562 => x"8d388214", + 563 => x"33757129", + 564 => x"94160805", + 565 => x"57537588", + 566 => x"0c873d0d", + 567 => x"04fd3d0d", + 568 => x"7554800b", + 569 => x"0b0b0b9f", + 570 => x"f4087033", + 571 => x"51535371", + 572 => x"832e0981", + 573 => x"068c3894", + 574 => x"1451fdef", + 575 => x"3f880890", + 576 => x"2b539a14", + 577 => x"51fde43f", + 578 => x"880883ff", + 579 => x"ff067307", + 580 => x"880c853d", + 581 => x"0d04fc3d", + 582 => x"0d760b0b", + 583 => x"0b9ff408", + 584 => x"55558075", + 585 => x"23881508", + 586 => x"5372812e", + 587 => x"88388814", + 588 => x"08732685", + 589 => x"388152b0", + 590 => x"39729038", + 591 => x"73335271", + 592 => x"832e0981", + 593 => x"06853890", + 594 => x"14085372", + 595 => x"8c160c72", + 596 => x"802e8b38", + 597 => x"7251fed8", + 598 => x"3f880852", + 599 => x"85399014", + 600 => x"08527190", + 601 => x"160c8052", + 602 => x"71880c86", + 603 => x"3d0d04fa", + 604 => x"3d0d780b", + 605 => x"0b0b9ff4", + 606 => x"08712281", + 607 => x"057083ff", + 608 => x"ff065754", + 609 => x"57557380", + 610 => x"2e883890", + 611 => x"15085372", + 612 => x"86388352", + 613 => x"80dc3973", + 614 => x"8f065271", + 615 => x"80cf3881", + 616 => x"1390160c", + 617 => x"8c150853", + 618 => x"728f3883", + 619 => x"0b841722", + 620 => x"57527376", + 621 => x"27bc38b5", + 622 => x"39821633", + 623 => x"ff057484", + 624 => x"2a065271", + 625 => x"a8387251", + 626 => x"fcdf3f81", + 627 => x"52718808", + 628 => x"27a03883", + 629 => x"52880888", + 630 => x"17082796", + 631 => x"3888088c", + 632 => x"160c8808", + 633 => x"51fdc93f", + 634 => x"88089016", + 635 => x"0c737523", + 636 => x"80527188", + 637 => x"0c883d0d", + 638 => x"04f23d0d", + 639 => x"60626458", + 640 => x"5e5c7533", + 641 => x"5574a02e", + 642 => x"09810688", + 643 => x"38811670", + 644 => x"4456ef39", + 645 => x"62703356", + 646 => x"5674af2e", + 647 => x"09810684", + 648 => x"38811643", + 649 => x"800b881d", + 650 => x"0c627033", + 651 => x"5155749f", + 652 => x"268f387b", + 653 => x"51fddf3f", + 654 => x"88085680", + 655 => x"7d3482d3", + 656 => x"39933d84", + 657 => x"1d087058", + 658 => x"5a5f8a55", + 659 => x"a0767081", + 660 => x"055834ff", + 661 => x"155574ff", + 662 => x"2e098106", + 663 => x"ef388070", + 664 => x"595b887f", + 665 => x"085f5a7a", + 666 => x"811c7081", + 667 => x"ff066013", + 668 => x"703370af", + 669 => x"327030a0", + 670 => x"73277180", + 671 => x"25075151", + 672 => x"525b535d", + 673 => x"57557480", + 674 => x"c73876ae", + 675 => x"2e098106", + 676 => x"83388155", + 677 => x"777a2775", + 678 => x"07557480", + 679 => x"2e9f3879", + 680 => x"88327030", + 681 => x"78ae3270", + 682 => x"30707307", + 683 => x"9f2a5351", + 684 => x"57515675", + 685 => x"9b388858", + 686 => x"8b5affab", + 687 => x"39778119", + 688 => x"7081ff06", + 689 => x"721c535a", + 690 => x"57557675", + 691 => x"34ff9839", + 692 => x"7a1e7f0c", + 693 => x"805576a0", + 694 => x"26833881", + 695 => x"55748b1a", + 696 => x"347b51fc", + 697 => x"b13f8808", + 698 => x"80ef38a0", + 699 => x"547b2270", + 700 => x"852b83e0", + 701 => x"06545590", + 702 => x"1c08527c", + 703 => x"51f8a83f", + 704 => x"88085788", + 705 => x"0880fb38", + 706 => x"7c335574", + 707 => x"802e80ee", + 708 => x"388b1d33", + 709 => x"70832a70", + 710 => x"81065156", + 711 => x"5674b238", + 712 => x"8b7d841e", + 713 => x"08880859", + 714 => x"5b5b58ff", + 715 => x"185877ff", + 716 => x"2e9a3879", + 717 => x"7081055b", + 718 => x"33797081", + 719 => x"055b3371", + 720 => x"71315256", + 721 => x"5675802e", + 722 => x"e2388639", + 723 => x"75802e92", + 724 => x"387b51fc", + 725 => x"9a3fff8e", + 726 => x"39880856", + 727 => x"8808b438", + 728 => x"83397656", + 729 => x"841c088b", + 730 => x"11335155", + 731 => x"74a5388b", + 732 => x"1d337084", + 733 => x"2a708106", + 734 => x"51565674", + 735 => x"89388356", + 736 => x"92398156", + 737 => x"8e397c51", + 738 => x"fad33f88", + 739 => x"08881d0c", + 740 => x"fdaf3975", + 741 => x"880c903d", + 742 => x"0d04f93d", + 743 => x"0d797b59", + 744 => x"57825483", + 745 => x"fe537752", + 746 => x"7651f6fb", + 747 => x"3f835688", + 748 => x"0880e738", + 749 => x"7651f8b3", + 750 => x"3f880883", + 751 => x"ffff0655", + 752 => x"82567482", + 753 => x"d4d52e09", + 754 => x"810680ce", + 755 => x"387554b6", + 756 => x"53775276", + 757 => x"51f6d03f", + 758 => x"88085688", + 759 => x"08943876", + 760 => x"51f8883f", + 761 => x"880883ff", + 762 => x"ff065574", + 763 => x"8182c62e", + 764 => x"a9388254", + 765 => x"80d25377", + 766 => x"527651f6", + 767 => x"aa3f8808", + 768 => x"56880894", + 769 => x"387651f7", + 770 => x"e23f8808", + 771 => x"83ffff06", + 772 => x"55748182", + 773 => x"c62e8338", + 774 => x"81567588", + 775 => x"0c893d0d", + 776 => x"04ed3d0d", + 777 => x"6559800b", + 778 => x"0b0b0b9f", + 779 => x"f40cf59b", + 780 => x"3f880881", + 781 => x"06558256", + 782 => x"7482f238", + 783 => x"7475538d", + 784 => x"3d705357", + 785 => x"5afed33f", + 786 => x"880881ff", + 787 => x"06577681", + 788 => x"2e098106", + 789 => x"b3389054", + 790 => x"83be5374", + 791 => x"527551f5", + 792 => x"c63f8808", + 793 => x"ab388d3d", + 794 => x"33557480", + 795 => x"2eac3895", + 796 => x"3de40551", + 797 => x"f78a3f88", + 798 => x"08880853", + 799 => x"76525afe", + 800 => x"993f8808", + 801 => x"81ff0657", + 802 => x"76832e09", + 803 => x"81068638", + 804 => x"81568299", + 805 => x"3976802e", + 806 => x"86388656", + 807 => x"828f39a4", + 808 => x"548d5379", + 809 => x"527551f4", + 810 => x"fe3f8156", + 811 => x"880881fd", + 812 => x"38953de5", + 813 => x"0551f6b3", + 814 => x"3f880883", + 815 => x"ffff0658", + 816 => x"778c3895", + 817 => x"3df30551", + 818 => x"f6b63f88", + 819 => x"085802af", + 820 => x"05337871", + 821 => x"29028805", + 822 => x"ad057054", + 823 => x"52595bf6", + 824 => x"8a3f8808", + 825 => x"83ffff06", + 826 => x"7a058c1a", + 827 => x"0c8c3d33", + 828 => x"821a3495", + 829 => x"3de00551", + 830 => x"f5f13f88", + 831 => x"08841a23", + 832 => x"953de205", + 833 => x"51f5e43f", + 834 => x"880883ff", + 835 => x"ff065675", + 836 => x"8c38953d", + 837 => x"ef0551f5", + 838 => x"e73f8808", + 839 => x"567a51f5", + 840 => x"ca3f8808", + 841 => x"83ffff06", + 842 => x"76713179", + 843 => x"31841b22", + 844 => x"70842a82", + 845 => x"1d335672", + 846 => x"71315559", + 847 => x"5c5155ee", + 848 => x"c43f8808", + 849 => x"82057088", + 850 => x"1b0c8808", + 851 => x"e08a0556", + 852 => x"567483df", + 853 => x"fe268338", + 854 => x"825783ff", + 855 => x"f6762785", + 856 => x"38835789", + 857 => x"39865676", + 858 => x"802e80c1", + 859 => x"38767934", + 860 => x"76832e09", + 861 => x"81069038", + 862 => x"953dfb05", + 863 => x"51f5813f", + 864 => x"8808901a", + 865 => x"0c88398c", + 866 => x"19081890", + 867 => x"1a0c7983", + 868 => x"ffff068c", + 869 => x"1a081971", + 870 => x"842a0594", + 871 => x"1b0c5580", + 872 => x"0b811a34", + 873 => x"780b0b0b", + 874 => x"9ff40c80", + 875 => x"5675880c", + 876 => x"953d0d04", + 877 => x"ea3d0d0b", + 878 => x"0b0b9ff4", + 879 => x"08558554", + 880 => x"74802e80", + 881 => x"df38800b", + 882 => x"81163498", + 883 => x"3de01145", + 884 => x"6954893d", + 885 => x"705457ec", + 886 => x"0551f89d", + 887 => x"3f880854", + 888 => x"880880c0", + 889 => x"38883d33", + 890 => x"5473802e", + 891 => x"933802a7", + 892 => x"05337084", + 893 => x"2a708106", + 894 => x"51555773", + 895 => x"802e8538", + 896 => x"8354a139", + 897 => x"7551f5d5", + 898 => x"3f8808a0", + 899 => x"160c983d", + 900 => x"dc0551f3", + 901 => x"eb3f8808", + 902 => x"9c160c73", + 903 => x"98160c81", + 904 => x"0b811634", + 905 => x"73880c98", + 906 => x"3d0d04f6", + 907 => x"3d0d7d7f", + 908 => x"7e0b0b0b", + 909 => x"9ff40859", + 910 => x"5b5c5880", + 911 => x"7b0c8557", + 912 => x"75802e81", + 913 => x"d1388116", + 914 => x"33810655", + 915 => x"84577480", + 916 => x"2e81c338", + 917 => x"91397481", + 918 => x"17348639", + 919 => x"800b8117", + 920 => x"34815781", + 921 => x"b1399c16", + 922 => x"08981708", + 923 => x"31557478", + 924 => x"27833874", + 925 => x"5877802e", + 926 => x"819a3898", + 927 => x"16087083", + 928 => x"ff065657", + 929 => x"7480c738", + 930 => x"821633ff", + 931 => x"0577892a", + 932 => x"067081ff", + 933 => x"065b5579", + 934 => x"9e387687", + 935 => x"38a01608", + 936 => x"558b39a4", + 937 => x"160851f3", + 938 => x"803f8808", + 939 => x"55817527", + 940 => x"ffaa3874", + 941 => x"a4170ca4", + 942 => x"160851f3", + 943 => x"f33f8808", + 944 => x"55880880", + 945 => x"2eff8f38", + 946 => x"88081aa8", + 947 => x"170c9816", + 948 => x"0883ff06", + 949 => x"84807131", + 950 => x"51557775", + 951 => x"27833877", + 952 => x"55745498", + 953 => x"160883ff", + 954 => x"0653a816", + 955 => x"08527851", + 956 => x"f0b53f88", + 957 => x"08fee538", + 958 => x"98160815", + 959 => x"98170c77", + 960 => x"75317b08", + 961 => x"167c0c58", + 962 => x"78802efe", + 963 => x"e8387419", + 964 => x"59fee239", + 965 => x"80577688", + 966 => x"0c8c3d0d", + 967 => x"04fb3d0d", + 968 => x"87c0948c", + 969 => x"08548784", + 970 => x"80527351", + 971 => x"ead73f88", + 972 => x"08902b87", + 973 => x"c0948c08", + 974 => x"56548784", + 975 => x"80527451", + 976 => x"eac33f73", + 977 => x"88080787", + 978 => x"c0948c0c", + 979 => x"87c0949c", + 980 => x"08548784", + 981 => x"80527351", + 982 => x"eaab3f88", + 983 => x"08902b87", + 984 => x"c0949c08", + 985 => x"56548784", + 986 => x"80527451", + 987 => x"ea973f73", + 988 => x"88080787", + 989 => x"c0949c0c", + 990 => x"8c80830b", + 991 => x"87c09484", + 992 => x"0c8c8083", + 993 => x"0b87c094", + 994 => x"940c9ff8", + 995 => x"51f9923f", + 996 => x"8808b838", + 997 => x"9fe051fc", + 998 => x"9b3f8808", + 999 => x"ae38a080", + 1000 => x"0b880887", + 1001 => x"c098880c", + 1002 => x"55873dfc", + 1003 => x"05538480", + 1004 => x"527451fc", + 1005 => x"f63f8808", + 1006 => x"8d387554", + 1007 => x"73802e86", + 1008 => x"38731555", + 1009 => x"e439a080", + 1010 => x"54730480", + 1011 => x"54fb3900", + 1012 => x"00ffffff", + 1013 => x"ff00ffff", + 1014 => x"ffff00ff", + 1015 => x"ffffff00", + 1016 => x"424f4f54", + 1017 => x"54494e59", + 1018 => x"2e524f4d", + 1019 => x"00000000", + 1020 => x"01000000", + others => x"00000000" + ); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + + +end arch; + diff --git a/zpu/devices/sysbus/BRAM/IOCP_DualPortBootBRAM.vhd b/zpu/devices/sysbus/BRAM/IOCP_DualPortBootBRAM.vhd new file mode 100644 index 0000000..7b78f48 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/IOCP_DualPortBootBRAM.vhd @@ -0,0 +1,4306 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity DualPortBootBRAM is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + + memBAddr : in std_logic_vector(addrbits-1 downto 2); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBRead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end DualPortBootBRAM; + +architecture arch of DualPortBootBRAM is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + 0 => x"88", + 1 => x"00", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"0b", + 10 => x"08", + 11 => x"8c", + 12 => x"04", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"08", + 17 => x"09", + 18 => x"05", + 19 => x"83", + 20 => x"52", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"08", + 25 => x"73", + 26 => x"81", + 27 => x"83", + 28 => x"06", + 29 => x"ff", + 30 => x"0b", + 31 => x"00", + 32 => x"05", + 33 => x"73", + 34 => x"06", + 35 => x"06", + 36 => x"06", + 37 => x"00", + 38 => x"00", + 39 => x"00", + 40 => x"73", + 41 => x"53", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"09", + 49 => x"06", + 50 => x"72", + 51 => x"72", + 52 => x"31", + 53 => x"06", + 54 => x"51", + 55 => x"00", + 56 => x"73", + 57 => x"53", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"88", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"2b", + 81 => x"04", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"06", + 89 => x"0b", + 90 => x"a7", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"ff", + 97 => x"2a", + 98 => x"0a", + 99 => x"05", + 100 => x"51", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"51", + 105 => x"83", + 106 => x"05", + 107 => x"2b", + 108 => x"72", + 109 => x"51", + 110 => x"00", + 111 => x"00", + 112 => x"05", + 113 => x"70", + 114 => x"06", + 115 => x"53", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"05", + 121 => x"70", + 122 => x"06", + 123 => x"06", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"05", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"81", + 137 => x"51", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"06", + 145 => x"06", + 146 => x"04", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"08", + 153 => x"09", + 154 => x"05", + 155 => x"2a", + 156 => x"52", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"08", + 161 => x"9f", + 162 => x"06", + 163 => x"08", + 164 => x"0b", + 165 => x"00", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"75", + 170 => x"89", + 171 => x"50", + 172 => x"90", + 173 => x"88", + 174 => x"00", + 175 => x"00", + 176 => x"08", + 177 => x"75", + 178 => x"8b", + 179 => x"50", + 180 => x"90", + 181 => x"88", + 182 => x"00", + 183 => x"00", + 184 => x"81", + 185 => x"0a", + 186 => x"05", + 187 => x"06", + 188 => x"74", + 189 => x"06", + 190 => x"51", + 191 => x"00", + 192 => x"81", + 193 => x"0a", + 194 => x"ff", + 195 => x"71", + 196 => x"72", + 197 => x"05", + 198 => x"51", + 199 => x"00", + 200 => x"04", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"52", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"72", + 233 => x"52", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"ff", + 249 => x"51", + 250 => x"00", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"04", + 257 => x"00", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"53", + 266 => x"00", + 267 => x"06", + 268 => x"09", + 269 => x"05", + 270 => x"2b", + 271 => x"06", + 272 => x"04", + 273 => x"72", + 274 => x"05", + 275 => x"05", + 276 => x"72", + 277 => x"53", + 278 => x"51", + 279 => x"04", + 280 => x"a0", + 281 => x"38", + 282 => x"84", + 283 => x"0b", + 284 => x"e2", + 285 => x"51", + 286 => x"00", + 287 => x"88", + 288 => x"00", + 289 => x"02", + 290 => x"3d", + 291 => x"94", + 292 => x"08", + 293 => x"88", + 294 => x"82", + 295 => x"08", + 296 => x"54", + 297 => x"94", + 298 => x"08", + 299 => x"fd", + 300 => x"53", + 301 => x"05", + 302 => x"08", + 303 => x"51", + 304 => x"88", + 305 => x"0c", + 306 => x"0d", + 307 => x"94", + 308 => x"0c", + 309 => x"80", + 310 => x"fc", + 311 => x"08", + 312 => x"80", + 313 => x"94", + 314 => x"08", + 315 => x"88", + 316 => x"0b", + 317 => x"05", + 318 => x"fc", + 319 => x"38", + 320 => x"08", + 321 => x"94", + 322 => x"08", + 323 => x"05", + 324 => x"8c", + 325 => x"25", + 326 => x"08", + 327 => x"30", + 328 => x"05", + 329 => x"94", + 330 => x"0c", + 331 => x"05", + 332 => x"81", + 333 => x"f0", + 334 => x"08", + 335 => x"94", + 336 => x"0c", + 337 => x"08", + 338 => x"52", + 339 => x"05", + 340 => x"a7", + 341 => x"70", + 342 => x"05", + 343 => x"08", + 344 => x"80", + 345 => x"94", + 346 => x"08", + 347 => x"f8", + 348 => x"08", + 349 => x"70", + 350 => x"89", + 351 => x"0c", + 352 => x"02", + 353 => x"3d", + 354 => x"94", + 355 => x"0c", + 356 => x"05", + 357 => x"93", + 358 => x"88", + 359 => x"94", + 360 => x"0c", + 361 => x"08", + 362 => x"94", + 363 => x"08", + 364 => x"38", + 365 => x"05", + 366 => x"08", + 367 => x"81", + 368 => x"8c", + 369 => x"94", + 370 => x"08", + 371 => x"88", + 372 => x"08", + 373 => x"54", + 374 => x"05", + 375 => x"8c", + 376 => x"f8", + 377 => x"94", + 378 => x"0c", + 379 => x"05", + 380 => x"0c", + 381 => x"0d", + 382 => x"94", + 383 => x"0c", + 384 => x"81", + 385 => x"fc", + 386 => x"0b", + 387 => x"05", + 388 => x"8c", + 389 => x"08", + 390 => x"27", + 391 => x"08", + 392 => x"80", + 393 => x"80", + 394 => x"8c", + 395 => x"99", + 396 => x"8c", + 397 => x"94", + 398 => x"0c", + 399 => x"05", + 400 => x"08", + 401 => x"c9", + 402 => x"fc", + 403 => x"2e", + 404 => x"94", + 405 => x"08", + 406 => x"05", + 407 => x"38", + 408 => x"05", + 409 => x"8c", + 410 => x"94", + 411 => x"0c", + 412 => x"05", + 413 => x"fc", + 414 => x"94", + 415 => x"0c", + 416 => x"05", + 417 => x"94", + 418 => x"0c", + 419 => x"05", + 420 => x"94", + 421 => x"0c", + 422 => x"94", + 423 => x"08", + 424 => x"38", + 425 => x"05", + 426 => x"08", + 427 => x"51", + 428 => x"08", + 429 => x"70", + 430 => x"05", + 431 => x"08", + 432 => x"88", + 433 => x"0d", + 434 => x"ff", + 435 => x"88", + 436 => x"92", + 437 => x"0b", + 438 => x"8c", + 439 => x"87", + 440 => x"0c", + 441 => x"8c", + 442 => x"06", + 443 => x"80", + 444 => x"87", + 445 => x"08", + 446 => x"38", + 447 => x"8c", + 448 => x"80", + 449 => x"93", + 450 => x"98", + 451 => x"70", + 452 => x"38", + 453 => x"0b", + 454 => x"0b", + 455 => x"f0", + 456 => x"83", + 457 => x"fa", + 458 => x"7b", + 459 => x"56", + 460 => x"0b", + 461 => x"33", + 462 => x"55", + 463 => x"75", + 464 => x"06", + 465 => x"85", + 466 => x"98", + 467 => x"87", + 468 => x"0c", + 469 => x"c0", + 470 => x"87", + 471 => x"08", + 472 => x"70", + 473 => x"52", + 474 => x"2e", + 475 => x"c0", + 476 => x"70", + 477 => x"76", + 478 => x"53", + 479 => x"2e", + 480 => x"80", + 481 => x"71", + 482 => x"05", + 483 => x"14", + 484 => x"55", + 485 => x"51", + 486 => x"8b", + 487 => x"98", + 488 => x"70", + 489 => x"87", + 490 => x"08", + 491 => x"38", + 492 => x"c0", + 493 => x"87", + 494 => x"08", + 495 => x"51", + 496 => x"38", + 497 => x"80", + 498 => x"52", + 499 => x"09", + 500 => x"38", + 501 => x"8c", + 502 => x"72", + 503 => x"06", + 504 => x"52", + 505 => x"88", + 506 => x"fe", + 507 => x"81", + 508 => x"33", + 509 => x"07", + 510 => x"51", + 511 => x"04", + 512 => x"75", + 513 => x"82", + 514 => x"90", + 515 => x"2b", + 516 => x"33", + 517 => x"88", + 518 => x"71", + 519 => x"52", + 520 => x"54", + 521 => x"0d", + 522 => x"0d", + 523 => x"0b", + 524 => x"57", + 525 => x"27", + 526 => x"76", + 527 => x"27", + 528 => x"75", + 529 => x"82", + 530 => x"74", + 531 => x"38", + 532 => x"74", + 533 => x"83", + 534 => x"76", + 535 => x"17", + 536 => x"88", + 537 => x"55", + 538 => x"88", + 539 => x"74", + 540 => x"3f", + 541 => x"ff", + 542 => x"ad", + 543 => x"76", + 544 => x"fc", + 545 => x"87", + 546 => x"08", + 547 => x"3d", + 548 => x"fd", + 549 => x"08", + 550 => x"51", + 551 => x"88", + 552 => x"06", + 553 => x"81", + 554 => x"0c", + 555 => x"04", + 556 => x"0b", + 557 => x"f4", + 558 => x"88", + 559 => x"05", + 560 => x"80", + 561 => x"27", + 562 => x"14", + 563 => x"29", + 564 => x"05", + 565 => x"88", + 566 => x"0d", + 567 => x"0d", + 568 => x"0b", + 569 => x"9f", + 570 => x"33", + 571 => x"71", + 572 => x"81", + 573 => x"94", + 574 => x"ef", + 575 => x"90", + 576 => x"14", + 577 => x"3f", + 578 => x"ff", + 579 => x"07", + 580 => x"3d", + 581 => x"3d", + 582 => x"0b", + 583 => x"08", + 584 => x"75", + 585 => x"08", + 586 => x"2e", + 587 => x"14", + 588 => x"85", + 589 => x"b0", + 590 => x"38", + 591 => x"71", + 592 => x"81", + 593 => x"90", + 594 => x"72", + 595 => x"72", + 596 => x"38", + 597 => x"d8", + 598 => x"52", + 599 => x"14", + 600 => x"90", + 601 => x"52", + 602 => x"86", + 603 => x"fa", + 604 => x"0b", + 605 => x"f4", + 606 => x"81", + 607 => x"ff", + 608 => x"54", + 609 => x"80", + 610 => x"90", + 611 => x"72", + 612 => x"52", + 613 => x"73", + 614 => x"71", + 615 => x"81", + 616 => x"0c", + 617 => x"53", + 618 => x"83", + 619 => x"22", + 620 => x"76", + 621 => x"b5", + 622 => x"33", + 623 => x"84", + 624 => x"71", + 625 => x"51", + 626 => x"81", + 627 => x"08", + 628 => x"83", + 629 => x"88", + 630 => x"96", + 631 => x"8c", + 632 => x"08", + 633 => x"3f", + 634 => x"16", + 635 => x"23", + 636 => x"88", + 637 => x"0d", + 638 => x"0d", + 639 => x"58", + 640 => x"33", + 641 => x"2e", + 642 => x"88", + 643 => x"70", + 644 => x"39", + 645 => x"56", + 646 => x"2e", + 647 => x"84", + 648 => x"43", + 649 => x"1d", + 650 => x"33", + 651 => x"9f", + 652 => x"7b", + 653 => x"3f", + 654 => x"80", + 655 => x"d3", + 656 => x"84", + 657 => x"58", + 658 => x"55", + 659 => x"81", + 660 => x"ff", + 661 => x"ff", + 662 => x"06", + 663 => x"70", + 664 => x"7f", + 665 => x"7a", + 666 => x"81", + 667 => x"13", + 668 => x"af", + 669 => x"a0", + 670 => x"80", + 671 => x"51", + 672 => x"5d", + 673 => x"80", + 674 => x"ae", + 675 => x"06", + 676 => x"55", + 677 => x"75", + 678 => x"80", + 679 => x"79", + 680 => x"30", + 681 => x"70", + 682 => x"07", + 683 => x"51", + 684 => x"75", + 685 => x"58", + 686 => x"ab", + 687 => x"19", + 688 => x"06", + 689 => x"5a", + 690 => x"75", + 691 => x"39", + 692 => x"0c", + 693 => x"a0", + 694 => x"81", + 695 => x"1a", + 696 => x"fc", + 697 => x"08", + 698 => x"a0", + 699 => x"70", + 700 => x"e0", + 701 => x"90", + 702 => x"7c", + 703 => x"3f", + 704 => x"88", + 705 => x"38", + 706 => x"74", + 707 => x"ee", + 708 => x"33", + 709 => x"70", + 710 => x"56", + 711 => x"38", + 712 => x"1e", + 713 => x"59", + 714 => x"ff", + 715 => x"ff", + 716 => x"79", + 717 => x"5b", + 718 => x"81", + 719 => x"71", + 720 => x"56", + 721 => x"2e", + 722 => x"39", + 723 => x"92", + 724 => x"fc", + 725 => x"8e", + 726 => x"56", + 727 => x"38", + 728 => x"56", + 729 => x"8b", + 730 => x"55", + 731 => x"8b", + 732 => x"84", + 733 => x"06", + 734 => x"74", + 735 => x"56", + 736 => x"56", + 737 => x"51", + 738 => x"88", + 739 => x"0c", + 740 => x"75", + 741 => x"3d", + 742 => x"3d", + 743 => x"59", + 744 => x"83", + 745 => x"52", + 746 => x"fb", + 747 => x"88", + 748 => x"38", + 749 => x"b3", + 750 => x"83", + 751 => x"55", + 752 => x"82", + 753 => x"09", + 754 => x"ce", + 755 => x"b6", + 756 => x"76", + 757 => x"3f", + 758 => x"88", + 759 => x"76", + 760 => x"3f", + 761 => x"ff", + 762 => x"74", + 763 => x"2e", + 764 => x"54", + 765 => x"77", + 766 => x"f6", + 767 => x"08", + 768 => x"94", + 769 => x"f7", + 770 => x"08", + 771 => x"06", + 772 => x"82", + 773 => x"38", + 774 => x"88", + 775 => x"0d", + 776 => x"0d", + 777 => x"0b", + 778 => x"9f", + 779 => x"9b", + 780 => x"81", + 781 => x"56", + 782 => x"38", + 783 => x"8d", + 784 => x"57", + 785 => x"3f", + 786 => x"ff", + 787 => x"81", + 788 => x"06", + 789 => x"54", + 790 => x"74", + 791 => x"f5", + 792 => x"08", + 793 => x"3d", + 794 => x"80", + 795 => x"95", + 796 => x"51", + 797 => x"88", + 798 => x"53", + 799 => x"fe", + 800 => x"08", + 801 => x"57", + 802 => x"09", + 803 => x"38", + 804 => x"99", + 805 => x"2e", + 806 => x"56", + 807 => x"a4", + 808 => x"79", + 809 => x"f4", + 810 => x"56", + 811 => x"fd", + 812 => x"e5", + 813 => x"b3", + 814 => x"83", + 815 => x"58", + 816 => x"95", + 817 => x"51", + 818 => x"88", + 819 => x"af", + 820 => x"71", + 821 => x"05", + 822 => x"54", + 823 => x"f6", + 824 => x"08", + 825 => x"06", + 826 => x"1a", + 827 => x"33", + 828 => x"95", + 829 => x"51", + 830 => x"88", + 831 => x"23", + 832 => x"05", + 833 => x"3f", + 834 => x"ff", + 835 => x"75", + 836 => x"3d", + 837 => x"f5", + 838 => x"08", + 839 => x"f5", + 840 => x"08", + 841 => x"06", + 842 => x"79", + 843 => x"22", + 844 => x"82", + 845 => x"72", + 846 => x"59", + 847 => x"ee", + 848 => x"08", + 849 => x"88", + 850 => x"08", + 851 => x"56", + 852 => x"df", + 853 => x"38", + 854 => x"ff", + 855 => x"85", + 856 => x"89", + 857 => x"76", + 858 => x"c1", + 859 => x"34", + 860 => x"09", + 861 => x"38", + 862 => x"05", + 863 => x"3f", + 864 => x"1a", + 865 => x"8c", + 866 => x"90", + 867 => x"83", + 868 => x"8c", + 869 => x"71", + 870 => x"94", + 871 => x"80", + 872 => x"34", + 873 => x"0b", + 874 => x"80", + 875 => x"0c", + 876 => x"04", + 877 => x"0b", + 878 => x"f4", + 879 => x"54", + 880 => x"80", + 881 => x"0b", + 882 => x"98", + 883 => x"45", + 884 => x"3d", + 885 => x"ec", + 886 => x"9d", + 887 => x"54", + 888 => x"c0", + 889 => x"33", + 890 => x"2e", + 891 => x"a7", + 892 => x"84", + 893 => x"06", + 894 => x"73", + 895 => x"38", + 896 => x"39", + 897 => x"d5", + 898 => x"a0", + 899 => x"3d", + 900 => x"f3", + 901 => x"08", + 902 => x"73", + 903 => x"81", + 904 => x"34", + 905 => x"98", + 906 => x"f6", + 907 => x"7f", + 908 => x"0b", + 909 => x"59", + 910 => x"80", + 911 => x"57", + 912 => x"81", + 913 => x"16", + 914 => x"55", + 915 => x"80", + 916 => x"38", + 917 => x"81", + 918 => x"39", + 919 => x"17", + 920 => x"81", + 921 => x"16", + 922 => x"08", + 923 => x"78", + 924 => x"74", + 925 => x"2e", + 926 => x"98", + 927 => x"83", + 928 => x"57", + 929 => x"38", + 930 => x"ff", + 931 => x"2a", + 932 => x"ff", + 933 => x"79", + 934 => x"87", + 935 => x"08", + 936 => x"a4", + 937 => x"f3", + 938 => x"08", + 939 => x"27", + 940 => x"74", + 941 => x"a4", + 942 => x"f3", + 943 => x"08", + 944 => x"80", + 945 => x"38", + 946 => x"a8", + 947 => x"16", + 948 => x"06", + 949 => x"31", + 950 => x"75", + 951 => x"77", + 952 => x"98", + 953 => x"ff", + 954 => x"16", + 955 => x"51", + 956 => x"88", + 957 => x"38", + 958 => x"15", + 959 => x"77", + 960 => x"08", + 961 => x"58", + 962 => x"fe", + 963 => x"19", + 964 => x"39", + 965 => x"88", + 966 => x"0d", + 967 => x"0d", + 968 => x"8c", + 969 => x"84", + 970 => x"51", + 971 => x"88", + 972 => x"87", + 973 => x"08", + 974 => x"84", + 975 => x"51", + 976 => x"73", + 977 => x"87", + 978 => x"0c", + 979 => x"9c", + 980 => x"84", + 981 => x"51", + 982 => x"88", + 983 => x"87", + 984 => x"08", + 985 => x"84", + 986 => x"51", + 987 => x"73", + 988 => x"87", + 989 => x"0c", + 990 => x"0b", + 991 => x"84", + 992 => x"83", + 993 => x"94", + 994 => x"f8", + 995 => x"3f", + 996 => x"38", + 997 => x"fc", + 998 => x"08", + 999 => x"80", + 1000 => x"87", + 1001 => x"0c", + 1002 => x"fc", + 1003 => x"80", + 1004 => x"fc", + 1005 => x"08", + 1006 => x"54", + 1007 => x"86", + 1008 => x"55", + 1009 => x"80", + 1010 => x"80", + 1011 => x"00", + 1012 => x"ff", + 1013 => x"ff", + 1014 => x"ff", + 1015 => x"00", + 1016 => x"54", + 1017 => x"59", + 1018 => x"4d", + 1019 => x"00", + 1020 => x"00", + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + 0 => x"0b", + 1 => x"00", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"8c", + 9 => x"0b", + 10 => x"80", + 11 => x"0c", + 12 => x"0c", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"06", + 17 => x"06", + 18 => x"82", + 19 => x"2a", + 20 => x"06", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"06", + 25 => x"ff", + 26 => x"09", + 27 => x"05", + 28 => x"09", + 29 => x"ff", + 30 => x"0b", + 31 => x"04", + 32 => x"81", + 33 => x"73", + 34 => x"09", + 35 => x"73", + 36 => x"81", + 37 => x"04", + 38 => x"00", + 39 => x"00", + 40 => x"24", + 41 => x"07", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"81", + 50 => x"05", + 51 => x"0a", + 52 => x"0a", + 53 => x"81", + 54 => x"53", + 55 => x"00", + 56 => x"26", + 57 => x"07", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"51", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"9f", + 89 => x"05", + 90 => x"88", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"2a", + 97 => x"06", + 98 => x"09", + 99 => x"ff", + 100 => x"53", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"53", + 105 => x"73", + 106 => x"81", + 107 => x"83", + 108 => x"07", + 109 => x"0c", + 110 => x"00", + 111 => x"00", + 112 => x"81", + 113 => x"09", + 114 => x"09", + 115 => x"06", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"81", + 121 => x"09", + 122 => x"09", + 123 => x"81", + 124 => x"04", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"81", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"09", + 137 => x"53", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"09", + 146 => x"51", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"06", + 153 => x"06", + 154 => x"83", + 155 => x"10", + 156 => x"06", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"06", + 161 => x"0b", + 162 => x"83", + 163 => x"05", + 164 => x"0b", + 165 => x"04", + 166 => x"00", + 167 => x"00", + 168 => x"8c", + 169 => x"75", + 170 => x"0b", + 171 => x"50", + 172 => x"56", + 173 => x"0c", + 174 => x"04", + 175 => x"00", + 176 => x"8c", + 177 => x"75", + 178 => x"0b", + 179 => x"50", + 180 => x"56", + 181 => x"0c", + 182 => x"04", + 183 => x"00", + 184 => x"70", + 185 => x"06", + 186 => x"ff", + 187 => x"71", + 188 => x"72", + 189 => x"05", + 190 => x"51", + 191 => x"00", + 192 => x"70", + 193 => x"06", + 194 => x"06", + 195 => x"54", + 196 => x"09", + 197 => x"ff", + 198 => x"51", + 199 => x"00", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"05", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"05", + 233 => x"05", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"05", + 249 => x"53", + 250 => x"04", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"04", + 257 => x"00", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"10", + 266 => x"00", + 267 => x"ff", + 268 => x"06", + 269 => x"83", + 270 => x"10", + 271 => x"fc", + 272 => x"51", + 273 => x"80", + 274 => x"ff", + 275 => x"06", + 276 => x"52", + 277 => x"0a", + 278 => x"38", + 279 => x"51", + 280 => x"70", + 281 => x"8e", + 282 => x"70", + 283 => x"0c", + 284 => x"88", + 285 => x"fe", + 286 => x"04", + 287 => x"00", + 288 => x"00", + 289 => x"08", + 290 => x"fd", + 291 => x"53", + 292 => x"05", + 293 => x"08", + 294 => x"51", + 295 => x"88", + 296 => x"0c", + 297 => x"0d", + 298 => x"94", + 299 => x"0c", + 300 => x"81", + 301 => x"8c", + 302 => x"94", + 303 => x"08", + 304 => x"3f", + 305 => x"88", + 306 => x"3d", + 307 => x"04", + 308 => x"94", + 309 => x"0d", + 310 => x"08", + 311 => x"94", + 312 => x"08", + 313 => x"38", + 314 => x"05", + 315 => x"08", + 316 => x"80", + 317 => x"f4", + 318 => x"08", + 319 => x"88", + 320 => x"94", + 321 => x"0c", + 322 => x"05", + 323 => x"fc", + 324 => x"08", + 325 => x"80", + 326 => x"94", + 327 => x"08", + 328 => x"8c", + 329 => x"0b", + 330 => x"05", + 331 => x"fc", + 332 => x"38", + 333 => x"08", + 334 => x"94", + 335 => x"08", + 336 => x"05", + 337 => x"94", + 338 => x"08", + 339 => x"88", + 340 => x"81", + 341 => x"08", + 342 => x"f8", + 343 => x"94", + 344 => x"08", + 345 => x"38", + 346 => x"05", + 347 => x"08", + 348 => x"94", + 349 => x"08", + 350 => x"54", + 351 => x"94", + 352 => x"08", + 353 => x"fb", + 354 => x"0b", + 355 => x"05", + 356 => x"88", + 357 => x"25", + 358 => x"08", + 359 => x"30", + 360 => x"05", + 361 => x"94", + 362 => x"0c", + 363 => x"05", + 364 => x"8c", + 365 => x"8c", + 366 => x"94", + 367 => x"0c", + 368 => x"08", + 369 => x"52", + 370 => x"05", + 371 => x"3f", + 372 => x"94", + 373 => x"0c", + 374 => x"fc", + 375 => x"2e", + 376 => x"08", + 377 => x"30", + 378 => x"05", + 379 => x"f8", + 380 => x"88", + 381 => x"3d", + 382 => x"04", + 383 => x"94", + 384 => x"0d", + 385 => x"08", + 386 => x"80", + 387 => x"f8", + 388 => x"08", + 389 => x"94", + 390 => x"08", + 391 => x"94", + 392 => x"08", + 393 => x"38", + 394 => x"08", + 395 => x"24", + 396 => x"08", + 397 => x"10", + 398 => x"05", + 399 => x"fc", + 400 => x"94", + 401 => x"0c", + 402 => x"08", + 403 => x"80", + 404 => x"38", + 405 => x"05", + 406 => x"88", + 407 => x"a1", + 408 => x"88", + 409 => x"08", + 410 => x"31", + 411 => x"05", + 412 => x"f8", + 413 => x"08", + 414 => x"07", + 415 => x"05", + 416 => x"fc", + 417 => x"2a", + 418 => x"05", + 419 => x"8c", + 420 => x"2a", + 421 => x"05", + 422 => x"39", + 423 => x"05", + 424 => x"8f", + 425 => x"88", + 426 => x"94", + 427 => x"0c", + 428 => x"94", + 429 => x"08", + 430 => x"f4", + 431 => x"94", + 432 => x"08", + 433 => x"3d", + 434 => x"04", + 435 => x"81", + 436 => x"c0", + 437 => x"81", + 438 => x"92", + 439 => x"0b", + 440 => x"8c", + 441 => x"92", + 442 => x"82", + 443 => x"70", + 444 => x"38", + 445 => x"8c", + 446 => x"e9", + 447 => x"92", + 448 => x"80", + 449 => x"71", + 450 => x"c0", + 451 => x"51", + 452 => x"88", + 453 => x"0b", + 454 => x"34", + 455 => x"9f", + 456 => x"0c", + 457 => x"04", + 458 => x"78", + 459 => x"58", + 460 => x"0b", + 461 => x"f0", + 462 => x"52", + 463 => x"70", + 464 => x"81", + 465 => x"38", + 466 => x"c0", + 467 => x"79", + 468 => x"80", + 469 => x"87", + 470 => x"0c", + 471 => x"8c", + 472 => x"2a", + 473 => x"51", + 474 => x"80", + 475 => x"87", + 476 => x"08", + 477 => x"06", + 478 => x"52", + 479 => x"80", + 480 => x"70", + 481 => x"38", + 482 => x"81", + 483 => x"ff", + 484 => x"15", + 485 => x"06", + 486 => x"2e", + 487 => x"c0", + 488 => x"51", + 489 => x"38", + 490 => x"8c", + 491 => x"95", + 492 => x"87", + 493 => x"0c", + 494 => x"8c", + 495 => x"06", + 496 => x"f4", + 497 => x"fc", + 498 => x"52", + 499 => x"2e", + 500 => x"8f", + 501 => x"98", + 502 => x"70", + 503 => x"81", + 504 => x"81", + 505 => x"0c", + 506 => x"04", + 507 => x"74", + 508 => x"71", + 509 => x"2b", + 510 => x"53", + 511 => x"0d", + 512 => x"0d", + 513 => x"33", + 514 => x"71", + 515 => x"88", + 516 => x"14", + 517 => x"07", + 518 => x"33", + 519 => x"0c", + 520 => x"56", + 521 => x"3d", + 522 => x"3d", + 523 => x"0b", + 524 => x"08", + 525 => x"77", + 526 => x"38", + 527 => x"08", + 528 => x"38", + 529 => x"74", + 530 => x"38", + 531 => x"ae", + 532 => x"39", + 533 => x"10", + 534 => x"53", + 535 => x"8c", + 536 => x"52", + 537 => x"52", + 538 => x"3f", + 539 => x"38", + 540 => x"f8", + 541 => x"83", + 542 => x"55", + 543 => x"54", + 544 => x"83", + 545 => x"76", + 546 => x"17", + 547 => x"88", + 548 => x"55", + 549 => x"88", + 550 => x"74", + 551 => x"3f", + 552 => x"0a", + 553 => x"39", + 554 => x"88", + 555 => x"0d", + 556 => x"0d", + 557 => x"9f", + 558 => x"19", + 559 => x"fe", + 560 => x"54", + 561 => x"73", + 562 => x"82", + 563 => x"71", + 564 => x"08", + 565 => x"75", + 566 => x"3d", + 567 => x"3d", + 568 => x"80", + 569 => x"0b", + 570 => x"70", + 571 => x"53", + 572 => x"09", + 573 => x"38", + 574 => x"fd", + 575 => x"08", + 576 => x"9a", + 577 => x"e4", + 578 => x"83", + 579 => x"73", + 580 => x"85", + 581 => x"fc", + 582 => x"0b", + 583 => x"f4", + 584 => x"80", + 585 => x"15", + 586 => x"81", + 587 => x"88", + 588 => x"26", + 589 => x"52", + 590 => x"90", + 591 => x"52", + 592 => x"09", + 593 => x"38", + 594 => x"53", + 595 => x"0c", + 596 => x"8b", + 597 => x"fe", + 598 => x"08", + 599 => x"90", + 600 => x"71", + 601 => x"80", + 602 => x"0c", + 603 => x"04", + 604 => x"78", + 605 => x"9f", + 606 => x"22", + 607 => x"83", + 608 => x"57", + 609 => x"73", + 610 => x"38", + 611 => x"53", + 612 => x"83", + 613 => x"39", + 614 => x"52", + 615 => x"38", + 616 => x"16", + 617 => x"08", + 618 => x"38", + 619 => x"17", + 620 => x"73", + 621 => x"38", + 622 => x"16", + 623 => x"74", + 624 => x"52", + 625 => x"72", + 626 => x"3f", + 627 => x"88", + 628 => x"38", + 629 => x"08", + 630 => x"27", + 631 => x"08", + 632 => x"88", + 633 => x"c9", + 634 => x"90", + 635 => x"75", + 636 => x"71", + 637 => x"3d", + 638 => x"3d", + 639 => x"64", + 640 => x"75", + 641 => x"a0", + 642 => x"06", + 643 => x"16", + 644 => x"ef", + 645 => x"33", + 646 => x"af", + 647 => x"06", + 648 => x"16", + 649 => x"88", + 650 => x"70", + 651 => x"74", + 652 => x"38", + 653 => x"df", + 654 => x"56", + 655 => x"82", + 656 => x"3d", + 657 => x"70", + 658 => x"8a", + 659 => x"70", + 660 => x"34", + 661 => x"74", + 662 => x"81", + 663 => x"80", + 664 => x"88", + 665 => x"5a", + 666 => x"70", + 667 => x"60", + 668 => x"70", + 669 => x"30", + 670 => x"71", + 671 => x"51", + 672 => x"53", + 673 => x"74", + 674 => x"76", + 675 => x"81", + 676 => x"81", + 677 => x"27", + 678 => x"74", + 679 => x"38", + 680 => x"70", + 681 => x"32", + 682 => x"73", + 683 => x"53", + 684 => x"56", + 685 => x"88", + 686 => x"ff", + 687 => x"81", + 688 => x"ff", + 689 => x"53", + 690 => x"76", + 691 => x"98", + 692 => x"7f", + 693 => x"76", + 694 => x"38", + 695 => x"8b", + 696 => x"51", + 697 => x"88", + 698 => x"38", + 699 => x"22", + 700 => x"83", + 701 => x"55", + 702 => x"52", + 703 => x"a8", + 704 => x"57", + 705 => x"fb", + 706 => x"55", + 707 => x"80", + 708 => x"1d", + 709 => x"2a", + 710 => x"51", + 711 => x"b2", + 712 => x"84", + 713 => x"08", + 714 => x"58", + 715 => x"77", + 716 => x"38", + 717 => x"05", + 718 => x"70", + 719 => x"33", + 720 => x"52", + 721 => x"80", + 722 => x"86", + 723 => x"2e", + 724 => x"51", + 725 => x"ff", + 726 => x"08", + 727 => x"b4", + 728 => x"76", + 729 => x"08", + 730 => x"51", + 731 => x"38", + 732 => x"70", + 733 => x"81", + 734 => x"56", + 735 => x"83", + 736 => x"81", + 737 => x"7c", + 738 => x"3f", + 739 => x"1d", + 740 => x"39", + 741 => x"90", + 742 => x"f9", + 743 => x"7b", + 744 => x"54", + 745 => x"77", + 746 => x"f6", + 747 => x"56", + 748 => x"e7", + 749 => x"f8", + 750 => x"08", + 751 => x"06", + 752 => x"74", + 753 => x"2e", + 754 => x"80", + 755 => x"54", + 756 => x"52", + 757 => x"d0", + 758 => x"56", + 759 => x"38", + 760 => x"88", + 761 => x"83", + 762 => x"55", + 763 => x"c6", + 764 => x"82", + 765 => x"53", + 766 => x"51", + 767 => x"88", + 768 => x"08", + 769 => x"51", + 770 => x"88", + 771 => x"ff", + 772 => x"81", + 773 => x"83", + 774 => x"75", + 775 => x"3d", + 776 => x"3d", + 777 => x"80", + 778 => x"0b", + 779 => x"f5", + 780 => x"08", + 781 => x"82", + 782 => x"f2", + 783 => x"53", + 784 => x"53", + 785 => x"d3", + 786 => x"81", + 787 => x"76", + 788 => x"81", + 789 => x"90", + 790 => x"53", + 791 => x"51", + 792 => x"88", + 793 => x"8d", + 794 => x"74", + 795 => x"38", + 796 => x"05", + 797 => x"3f", + 798 => x"08", + 799 => x"5a", + 800 => x"88", + 801 => x"06", + 802 => x"2e", + 803 => x"86", + 804 => x"82", + 805 => x"80", + 806 => x"86", + 807 => x"39", + 808 => x"53", + 809 => x"51", + 810 => x"81", + 811 => x"81", + 812 => x"3d", + 813 => x"f6", + 814 => x"08", + 815 => x"06", + 816 => x"38", + 817 => x"05", + 818 => x"3f", + 819 => x"02", + 820 => x"78", + 821 => x"88", + 822 => x"70", + 823 => x"5b", + 824 => x"88", + 825 => x"ff", + 826 => x"8c", + 827 => x"3d", + 828 => x"34", + 829 => x"05", + 830 => x"3f", + 831 => x"1a", + 832 => x"e2", + 833 => x"e4", + 834 => x"83", + 835 => x"56", + 836 => x"95", + 837 => x"51", + 838 => x"88", + 839 => x"51", + 840 => x"88", + 841 => x"ff", + 842 => x"31", + 843 => x"1b", + 844 => x"2a", + 845 => x"56", + 846 => x"55", + 847 => x"55", + 848 => x"88", + 849 => x"70", + 850 => x"88", + 851 => x"05", + 852 => x"83", + 853 => x"83", + 854 => x"83", + 855 => x"27", + 856 => x"57", + 857 => x"56", + 858 => x"80", + 859 => x"79", + 860 => x"2e", + 861 => x"90", + 862 => x"fb", + 863 => x"81", + 864 => x"90", + 865 => x"39", + 866 => x"18", + 867 => x"79", + 868 => x"06", + 869 => x"19", + 870 => x"05", + 871 => x"55", + 872 => x"1a", + 873 => x"0b", + 874 => x"0c", + 875 => x"88", + 876 => x"0d", + 877 => x"0d", + 878 => x"9f", + 879 => x"85", + 880 => x"2e", + 881 => x"80", + 882 => x"34", + 883 => x"11", + 884 => x"89", + 885 => x"57", + 886 => x"f8", + 887 => x"08", + 888 => x"80", + 889 => x"3d", + 890 => x"80", + 891 => x"02", + 892 => x"70", + 893 => x"81", + 894 => x"57", + 895 => x"85", + 896 => x"a1", + 897 => x"f5", + 898 => x"08", + 899 => x"98", + 900 => x"51", + 901 => x"88", + 902 => x"0c", + 903 => x"0c", + 904 => x"16", + 905 => x"0c", + 906 => x"04", + 907 => x"7d", + 908 => x"0b", + 909 => x"08", + 910 => x"58", + 911 => x"85", + 912 => x"2e", + 913 => x"81", + 914 => x"06", + 915 => x"74", + 916 => x"c3", + 917 => x"74", + 918 => x"86", + 919 => x"81", + 920 => x"57", + 921 => x"9c", + 922 => x"17", + 923 => x"74", + 924 => x"38", + 925 => x"80", + 926 => x"38", + 927 => x"70", + 928 => x"56", + 929 => x"c7", + 930 => x"33", + 931 => x"89", + 932 => x"81", + 933 => x"55", + 934 => x"76", + 935 => x"16", + 936 => x"39", + 937 => x"51", + 938 => x"88", + 939 => x"75", + 940 => x"38", + 941 => x"0c", + 942 => x"51", + 943 => x"88", + 944 => x"08", + 945 => x"8f", + 946 => x"1a", + 947 => x"98", + 948 => x"ff", + 949 => x"71", + 950 => x"77", + 951 => x"38", + 952 => x"54", + 953 => x"83", + 954 => x"a8", + 955 => x"78", + 956 => x"3f", + 957 => x"e5", + 958 => x"08", + 959 => x"0c", + 960 => x"7b", + 961 => x"0c", + 962 => x"2e", + 963 => x"74", + 964 => x"e2", + 965 => x"76", + 966 => x"3d", + 967 => x"3d", + 968 => x"94", + 969 => x"87", + 970 => x"73", + 971 => x"3f", + 972 => x"2b", + 973 => x"8c", + 974 => x"87", + 975 => x"74", + 976 => x"3f", + 977 => x"07", + 978 => x"8c", + 979 => x"94", + 980 => x"87", + 981 => x"73", + 982 => x"3f", + 983 => x"2b", + 984 => x"9c", + 985 => x"87", + 986 => x"74", + 987 => x"3f", + 988 => x"07", + 989 => x"9c", + 990 => x"83", + 991 => x"94", + 992 => x"80", + 993 => x"c0", + 994 => x"9f", + 995 => x"92", + 996 => x"b8", + 997 => x"51", + 998 => x"88", + 999 => x"a0", + 1000 => x"08", + 1001 => x"88", + 1002 => x"3d", + 1003 => x"84", + 1004 => x"51", + 1005 => x"88", + 1006 => x"75", + 1007 => x"2e", + 1008 => x"15", + 1009 => x"a0", + 1010 => x"04", + 1011 => x"39", + 1012 => x"ff", + 1013 => x"ff", + 1014 => x"00", + 1015 => x"ff", + 1016 => x"4f", + 1017 => x"4e", + 1018 => x"4f", + 1019 => x"00", + 1020 => x"00", + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + 0 => x"0b", + 1 => x"04", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"08", + 10 => x"88", + 11 => x"90", + 12 => x"88", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"fd", + 17 => x"83", + 18 => x"05", + 19 => x"2b", + 20 => x"ff", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"fd", + 25 => x"ff", + 26 => x"06", + 27 => x"82", + 28 => x"2b", + 29 => x"83", + 30 => x"0b", + 31 => x"a5", + 32 => x"09", + 33 => x"05", + 34 => x"06", + 35 => x"09", + 36 => x"0a", + 37 => x"51", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"2e", + 42 => x"04", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"73", + 49 => x"06", + 50 => x"81", + 51 => x"10", + 52 => x"10", + 53 => x"0a", + 54 => x"51", + 55 => x"00", + 56 => x"72", + 57 => x"2e", + 58 => x"04", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"04", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"0a", + 81 => x"53", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"81", + 90 => x"0b", + 91 => x"04", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"9f", + 98 => x"74", + 99 => x"06", + 100 => x"07", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"06", + 106 => x"09", + 107 => x"05", + 108 => x"2b", + 109 => x"06", + 110 => x"04", + 111 => x"00", + 112 => x"09", + 113 => x"05", + 114 => x"05", + 115 => x"81", + 116 => x"04", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"09", + 121 => x"05", + 122 => x"05", + 123 => x"09", + 124 => x"51", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"09", + 129 => x"04", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"09", + 145 => x"73", + 146 => x"53", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"fc", + 153 => x"83", + 154 => x"05", + 155 => x"10", + 156 => x"ff", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"fc", + 161 => x"0b", + 162 => x"73", + 163 => x"10", + 164 => x"0b", + 165 => x"ac", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"08", + 170 => x"0b", + 171 => x"2d", + 172 => x"08", + 173 => x"8c", + 174 => x"51", + 175 => x"00", + 176 => x"08", + 177 => x"08", + 178 => x"0b", + 179 => x"2d", + 180 => x"08", + 181 => x"8c", + 182 => x"51", + 183 => x"00", + 184 => x"09", + 185 => x"09", + 186 => x"06", + 187 => x"54", + 188 => x"09", + 189 => x"ff", + 190 => x"51", + 191 => x"00", + 192 => x"09", + 193 => x"09", + 194 => x"81", + 195 => x"70", + 196 => x"73", + 197 => x"05", + 198 => x"07", + 199 => x"04", + 200 => x"ff", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"81", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"84", + 233 => x"10", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"71", + 250 => x"0d", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"00", + 257 => x"00", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"10", + 266 => x"04", + 267 => x"81", + 268 => x"83", + 269 => x"05", + 270 => x"10", + 271 => x"72", + 272 => x"51", + 273 => x"72", + 274 => x"06", + 275 => x"72", + 276 => x"10", + 277 => x"10", + 278 => x"ed", + 279 => x"53", + 280 => x"f4", + 281 => x"27", + 282 => x"71", + 283 => x"53", + 284 => x"0b", + 285 => x"88", + 286 => x"9d", + 287 => x"04", + 288 => x"04", + 289 => x"94", + 290 => x"0c", + 291 => x"80", + 292 => x"8c", + 293 => x"94", + 294 => x"08", + 295 => x"3f", + 296 => x"88", + 297 => x"3d", + 298 => x"04", + 299 => x"94", + 300 => x"0d", + 301 => x"08", + 302 => x"52", + 303 => x"05", + 304 => x"b9", + 305 => x"70", + 306 => x"85", + 307 => x"0c", + 308 => x"02", + 309 => x"3d", + 310 => x"94", + 311 => x"0c", + 312 => x"05", + 313 => x"ab", + 314 => x"88", + 315 => x"94", + 316 => x"0c", + 317 => x"08", + 318 => x"94", + 319 => x"08", + 320 => x"0b", + 321 => x"05", + 322 => x"f4", + 323 => x"08", + 324 => x"94", + 325 => x"08", + 326 => x"38", + 327 => x"05", + 328 => x"08", + 329 => x"80", + 330 => x"f0", + 331 => x"08", + 332 => x"88", + 333 => x"94", + 334 => x"0c", + 335 => x"05", + 336 => x"fc", + 337 => x"53", + 338 => x"05", + 339 => x"08", + 340 => x"51", + 341 => x"88", + 342 => x"08", + 343 => x"54", + 344 => x"05", + 345 => x"8c", + 346 => x"f8", + 347 => x"94", + 348 => x"0c", + 349 => x"05", + 350 => x"0c", + 351 => x"0d", + 352 => x"94", + 353 => x"0c", + 354 => x"80", + 355 => x"fc", + 356 => x"08", + 357 => x"80", + 358 => x"94", + 359 => x"08", + 360 => x"88", + 361 => x"0b", + 362 => x"05", + 363 => x"8c", + 364 => x"25", + 365 => x"08", + 366 => x"30", + 367 => x"05", + 368 => x"94", + 369 => x"08", + 370 => x"88", + 371 => x"ad", + 372 => x"70", + 373 => x"05", + 374 => x"08", + 375 => x"80", + 376 => x"94", + 377 => x"08", + 378 => x"f8", + 379 => x"08", + 380 => x"70", + 381 => x"87", + 382 => x"0c", + 383 => x"02", + 384 => x"3d", + 385 => x"94", + 386 => x"0c", + 387 => x"08", + 388 => x"94", + 389 => x"08", + 390 => x"05", + 391 => x"38", + 392 => x"05", + 393 => x"a3", + 394 => x"94", + 395 => x"08", + 396 => x"94", + 397 => x"08", + 398 => x"8c", + 399 => x"08", + 400 => x"10", + 401 => x"05", + 402 => x"94", + 403 => x"08", + 404 => x"c9", + 405 => x"8c", + 406 => x"08", + 407 => x"26", + 408 => x"08", + 409 => x"94", + 410 => x"08", + 411 => x"88", + 412 => x"08", + 413 => x"94", + 414 => x"08", + 415 => x"f8", + 416 => x"08", + 417 => x"81", + 418 => x"fc", + 419 => x"08", + 420 => x"81", + 421 => x"8c", + 422 => x"af", + 423 => x"90", + 424 => x"2e", + 425 => x"08", + 426 => x"70", + 427 => x"05", + 428 => x"39", + 429 => x"05", + 430 => x"08", + 431 => x"51", + 432 => x"05", + 433 => x"85", + 434 => x"0c", + 435 => x"0d", + 436 => x"87", + 437 => x"0c", + 438 => x"c0", + 439 => x"85", + 440 => x"98", + 441 => x"c0", + 442 => x"70", + 443 => x"51", + 444 => x"8a", + 445 => x"98", + 446 => x"70", + 447 => x"c0", + 448 => x"fc", + 449 => x"52", + 450 => x"87", + 451 => x"08", + 452 => x"2e", + 453 => x"0b", + 454 => x"f0", + 455 => x"0b", + 456 => x"88", + 457 => x"0d", + 458 => x"0d", + 459 => x"56", + 460 => x"0b", + 461 => x"9f", + 462 => x"06", + 463 => x"52", + 464 => x"09", + 465 => x"9e", + 466 => x"87", + 467 => x"0c", + 468 => x"92", + 469 => x"0b", + 470 => x"8c", + 471 => x"92", + 472 => x"85", + 473 => x"06", + 474 => x"70", + 475 => x"38", + 476 => x"84", + 477 => x"ff", + 478 => x"27", + 479 => x"73", + 480 => x"38", + 481 => x"8b", + 482 => x"70", + 483 => x"34", + 484 => x"81", + 485 => x"a2", + 486 => x"80", + 487 => x"87", + 488 => x"08", + 489 => x"b5", + 490 => x"98", + 491 => x"70", + 492 => x"0b", + 493 => x"8c", + 494 => x"92", + 495 => x"82", + 496 => x"70", + 497 => x"73", + 498 => x"06", + 499 => x"72", + 500 => x"06", + 501 => x"c0", + 502 => x"51", + 503 => x"09", + 504 => x"38", + 505 => x"88", + 506 => x"0d", + 507 => x"0d", + 508 => x"33", + 509 => x"88", + 510 => x"0c", + 511 => x"3d", + 512 => x"3d", + 513 => x"11", + 514 => x"33", + 515 => x"71", + 516 => x"81", + 517 => x"72", + 518 => x"75", + 519 => x"88", + 520 => x"54", + 521 => x"85", + 522 => x"f9", + 523 => x"0b", + 524 => x"f4", + 525 => x"81", + 526 => x"ed", + 527 => x"17", + 528 => x"e5", + 529 => x"55", + 530 => x"89", + 531 => x"2e", + 532 => x"d5", + 533 => x"76", + 534 => x"06", + 535 => x"2a", + 536 => x"05", + 537 => x"70", + 538 => x"bd", + 539 => x"b9", + 540 => x"fe", + 541 => x"08", + 542 => x"06", + 543 => x"84", + 544 => x"2b", + 545 => x"53", + 546 => x"8c", + 547 => x"52", + 548 => x"52", + 549 => x"3f", + 550 => x"38", + 551 => x"e2", + 552 => x"f0", + 553 => x"83", + 554 => x"74", + 555 => x"3d", + 556 => x"3d", + 557 => x"0b", + 558 => x"fe", + 559 => x"08", + 560 => x"56", + 561 => x"74", + 562 => x"38", + 563 => x"75", + 564 => x"16", + 565 => x"53", + 566 => x"87", + 567 => x"fd", + 568 => x"54", + 569 => x"0b", + 570 => x"08", + 571 => x"53", + 572 => x"2e", + 573 => x"8c", + 574 => x"51", + 575 => x"88", + 576 => x"53", + 577 => x"fd", + 578 => x"08", + 579 => x"06", + 580 => x"0c", + 581 => x"04", + 582 => x"76", + 583 => x"9f", + 584 => x"55", + 585 => x"88", + 586 => x"72", + 587 => x"38", + 588 => x"73", + 589 => x"81", + 590 => x"72", + 591 => x"33", + 592 => x"2e", + 593 => x"85", + 594 => x"08", + 595 => x"16", + 596 => x"2e", + 597 => x"51", + 598 => x"88", + 599 => x"39", + 600 => x"52", + 601 => x"0c", + 602 => x"88", + 603 => x"0d", + 604 => x"0d", + 605 => x"0b", + 606 => x"71", + 607 => x"70", + 608 => x"06", + 609 => x"55", + 610 => x"88", + 611 => x"08", + 612 => x"38", + 613 => x"dc", + 614 => x"06", + 615 => x"cf", + 616 => x"90", + 617 => x"15", + 618 => x"8f", + 619 => x"84", + 620 => x"52", + 621 => x"bc", + 622 => x"82", + 623 => x"05", + 624 => x"06", + 625 => x"38", + 626 => x"df", + 627 => x"71", + 628 => x"a0", + 629 => x"88", + 630 => x"08", + 631 => x"88", + 632 => x"0c", + 633 => x"fd", + 634 => x"08", + 635 => x"73", + 636 => x"52", + 637 => x"88", + 638 => x"f2", + 639 => x"62", + 640 => x"5c", + 641 => x"74", + 642 => x"81", + 643 => x"81", + 644 => x"56", + 645 => x"70", + 646 => x"74", + 647 => x"81", + 648 => x"81", + 649 => x"0b", + 650 => x"62", + 651 => x"55", + 652 => x"8f", + 653 => x"fd", + 654 => x"08", + 655 => x"34", + 656 => x"93", + 657 => x"08", + 658 => x"5f", + 659 => x"76", + 660 => x"58", + 661 => x"55", + 662 => x"09", + 663 => x"38", + 664 => x"5b", + 665 => x"5f", + 666 => x"1c", + 667 => x"06", + 668 => x"33", + 669 => x"70", + 670 => x"27", + 671 => x"07", + 672 => x"5b", + 673 => x"55", + 674 => x"38", + 675 => x"09", + 676 => x"38", + 677 => x"7a", + 678 => x"55", + 679 => x"9f", + 680 => x"32", + 681 => x"ae", + 682 => x"70", + 683 => x"2a", + 684 => x"51", + 685 => x"38", + 686 => x"5a", + 687 => x"77", + 688 => x"81", + 689 => x"1c", + 690 => x"55", + 691 => x"ff", + 692 => x"1e", + 693 => x"55", + 694 => x"83", + 695 => x"74", + 696 => x"7b", + 697 => x"3f", + 698 => x"ef", + 699 => x"7b", + 700 => x"2b", + 701 => x"54", + 702 => x"08", + 703 => x"f8", + 704 => x"08", + 705 => x"80", + 706 => x"33", + 707 => x"2e", + 708 => x"8b", + 709 => x"83", + 710 => x"06", + 711 => x"74", + 712 => x"7d", + 713 => x"88", + 714 => x"5b", + 715 => x"58", + 716 => x"9a", + 717 => x"81", + 718 => x"79", + 719 => x"5b", + 720 => x"31", + 721 => x"75", + 722 => x"38", + 723 => x"80", + 724 => x"7b", + 725 => x"3f", + 726 => x"88", + 727 => x"08", + 728 => x"39", + 729 => x"1c", + 730 => x"33", + 731 => x"a5", + 732 => x"33", + 733 => x"70", + 734 => x"56", + 735 => x"38", + 736 => x"39", + 737 => x"39", + 738 => x"d3", + 739 => x"88", + 740 => x"af", + 741 => x"0c", + 742 => x"04", + 743 => x"79", + 744 => x"82", + 745 => x"53", + 746 => x"51", + 747 => x"83", + 748 => x"80", + 749 => x"51", + 750 => x"88", + 751 => x"ff", + 752 => x"56", + 753 => x"d5", + 754 => x"06", + 755 => x"75", + 756 => x"77", + 757 => x"f6", + 758 => x"08", + 759 => x"94", + 760 => x"f8", + 761 => x"08", + 762 => x"06", + 763 => x"82", + 764 => x"38", + 765 => x"d2", + 766 => x"76", + 767 => x"3f", + 768 => x"88", + 769 => x"76", + 770 => x"3f", + 771 => x"ff", + 772 => x"74", + 773 => x"2e", + 774 => x"56", + 775 => x"89", + 776 => x"ed", + 777 => x"59", + 778 => x"0b", + 779 => x"0c", + 780 => x"88", + 781 => x"55", + 782 => x"82", + 783 => x"75", + 784 => x"70", + 785 => x"fe", + 786 => x"08", + 787 => x"57", + 788 => x"09", + 789 => x"38", + 790 => x"be", + 791 => x"75", + 792 => x"3f", + 793 => x"38", + 794 => x"55", + 795 => x"ac", + 796 => x"e4", + 797 => x"8a", + 798 => x"88", + 799 => x"52", + 800 => x"3f", + 801 => x"ff", + 802 => x"83", + 803 => x"06", + 804 => x"56", + 805 => x"76", + 806 => x"38", + 807 => x"8f", + 808 => x"8d", + 809 => x"75", + 810 => x"3f", + 811 => x"08", + 812 => x"95", + 813 => x"51", + 814 => x"88", + 815 => x"ff", + 816 => x"8c", + 817 => x"f3", + 818 => x"b6", + 819 => x"58", + 820 => x"33", + 821 => x"02", + 822 => x"05", + 823 => x"59", + 824 => x"3f", + 825 => x"ff", + 826 => x"05", + 827 => x"8c", + 828 => x"1a", + 829 => x"e0", + 830 => x"f1", + 831 => x"84", + 832 => x"3d", + 833 => x"f5", + 834 => x"08", + 835 => x"06", + 836 => x"38", + 837 => x"05", + 838 => x"3f", + 839 => x"7a", + 840 => x"3f", + 841 => x"ff", + 842 => x"71", + 843 => x"84", + 844 => x"84", + 845 => x"33", + 846 => x"31", + 847 => x"51", + 848 => x"3f", + 849 => x"05", + 850 => x"0c", + 851 => x"8a", + 852 => x"74", + 853 => x"26", + 854 => x"57", + 855 => x"76", + 856 => x"83", + 857 => x"86", + 858 => x"2e", + 859 => x"76", + 860 => x"83", + 861 => x"06", + 862 => x"3d", + 863 => x"f5", + 864 => x"08", + 865 => x"88", + 866 => x"08", + 867 => x"0c", + 868 => x"ff", + 869 => x"08", + 870 => x"2a", + 871 => x"0c", + 872 => x"81", + 873 => x"0b", + 874 => x"f4", + 875 => x"75", + 876 => x"3d", + 877 => x"3d", + 878 => x"0b", + 879 => x"55", + 880 => x"80", + 881 => x"38", + 882 => x"16", + 883 => x"e0", + 884 => x"54", + 885 => x"54", + 886 => x"51", + 887 => x"88", + 888 => x"08", + 889 => x"88", + 890 => x"73", + 891 => x"38", + 892 => x"33", + 893 => x"70", + 894 => x"55", + 895 => x"2e", + 896 => x"54", + 897 => x"51", + 898 => x"88", + 899 => x"0c", + 900 => x"05", + 901 => x"3f", + 902 => x"16", + 903 => x"16", + 904 => x"81", + 905 => x"88", + 906 => x"0d", + 907 => x"0d", + 908 => x"0b", + 909 => x"f4", + 910 => x"5c", + 911 => x"0c", + 912 => x"80", + 913 => x"38", + 914 => x"81", + 915 => x"57", + 916 => x"81", + 917 => x"39", + 918 => x"34", + 919 => x"0b", + 920 => x"81", + 921 => x"39", + 922 => x"98", + 923 => x"55", + 924 => x"83", + 925 => x"77", + 926 => x"9a", + 927 => x"08", + 928 => x"06", + 929 => x"80", + 930 => x"16", + 931 => x"77", + 932 => x"70", + 933 => x"5b", + 934 => x"38", + 935 => x"a0", + 936 => x"8b", + 937 => x"08", + 938 => x"3f", + 939 => x"81", + 940 => x"aa", + 941 => x"17", + 942 => x"08", + 943 => x"3f", + 944 => x"88", + 945 => x"ff", + 946 => x"08", + 947 => x"0c", + 948 => x"83", + 949 => x"80", + 950 => x"55", + 951 => x"83", + 952 => x"74", + 953 => x"08", + 954 => x"53", + 955 => x"52", + 956 => x"b5", + 957 => x"fe", + 958 => x"16", + 959 => x"17", + 960 => x"31", + 961 => x"7c", + 962 => x"80", + 963 => x"38", + 964 => x"fe", + 965 => x"57", + 966 => x"8c", + 967 => x"fb", + 968 => x"c0", + 969 => x"54", + 970 => x"52", + 971 => x"d7", + 972 => x"90", + 973 => x"94", + 974 => x"54", + 975 => x"52", + 976 => x"c3", + 977 => x"08", + 978 => x"94", + 979 => x"c0", + 980 => x"54", + 981 => x"52", + 982 => x"ab", + 983 => x"90", + 984 => x"94", + 985 => x"54", + 986 => x"52", + 987 => x"97", + 988 => x"08", + 989 => x"94", + 990 => x"80", + 991 => x"c0", + 992 => x"8c", + 993 => x"87", + 994 => x"0c", + 995 => x"f9", + 996 => x"08", + 997 => x"e0", + 998 => x"3f", + 999 => x"38", + 1000 => x"88", + 1001 => x"98", + 1002 => x"87", + 1003 => x"53", + 1004 => x"74", + 1005 => x"3f", + 1006 => x"38", + 1007 => x"80", + 1008 => x"73", + 1009 => x"39", + 1010 => x"73", + 1011 => x"fb", + 1012 => x"ff", + 1013 => x"00", + 1014 => x"ff", + 1015 => x"ff", + 1016 => x"4f", + 1017 => x"49", + 1018 => x"52", + 1019 => x"00", + 1020 => x"00", + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + 0 => x"0b", + 1 => x"e0", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"88", + 9 => x"90", + 10 => x"0b", + 11 => x"2d", + 12 => x"0c", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"71", + 17 => x"72", + 18 => x"81", + 19 => x"83", + 20 => x"ff", + 21 => x"04", + 22 => x"00", + 23 => x"00", + 24 => x"71", + 25 => x"83", + 26 => x"83", + 27 => x"05", + 28 => x"2b", + 29 => x"73", + 30 => x"0b", + 31 => x"83", + 32 => x"72", + 33 => x"72", + 34 => x"09", + 35 => x"73", + 36 => x"07", + 37 => x"53", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"73", + 42 => x"51", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"71", + 50 => x"09", + 51 => x"0a", + 52 => x"0a", + 53 => x"05", + 54 => x"51", + 55 => x"04", + 56 => x"72", + 57 => x"73", + 58 => x"51", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"c4", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"0a", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"09", + 90 => x"0b", + 91 => x"05", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"73", + 98 => x"09", + 99 => x"81", + 100 => x"06", + 101 => x"04", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"04", + 106 => x"06", + 107 => x"82", + 108 => x"0b", + 109 => x"fc", + 110 => x"51", + 111 => x"00", + 112 => x"72", + 113 => x"72", + 114 => x"81", + 115 => x"0a", + 116 => x"51", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"72", + 121 => x"72", + 122 => x"81", + 123 => x"0a", + 124 => x"53", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"71", + 129 => x"52", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"04", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"73", + 146 => x"07", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"71", + 153 => x"72", + 154 => x"81", + 155 => x"10", + 156 => x"81", + 157 => x"04", + 158 => x"00", + 159 => x"00", + 160 => x"71", + 161 => x"0b", + 162 => x"d0", + 163 => x"10", + 164 => x"06", + 165 => x"88", + 166 => x"00", + 167 => x"00", + 168 => x"88", + 169 => x"90", + 170 => x"0b", + 171 => x"cf", + 172 => x"88", + 173 => x"0c", + 174 => x"0c", + 175 => x"00", + 176 => x"88", + 177 => x"90", + 178 => x"0b", + 179 => x"81", + 180 => x"88", + 181 => x"0c", + 182 => x"0c", + 183 => x"00", + 184 => x"72", + 185 => x"05", + 186 => x"81", + 187 => x"70", + 188 => x"73", + 189 => x"05", + 190 => x"07", + 191 => x"04", + 192 => x"72", + 193 => x"05", + 194 => x"09", + 195 => x"05", + 196 => x"06", + 197 => x"74", + 198 => x"06", + 199 => x"51", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"04", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"71", + 217 => x"04", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"04", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"02", + 233 => x"10", + 234 => x"04", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"05", + 250 => x"02", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"00", + 257 => x"04", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"10", + 266 => x"51", + 267 => x"73", + 268 => x"73", + 269 => x"81", + 270 => x"10", + 271 => x"07", + 272 => x"0c", + 273 => x"72", + 274 => x"81", + 275 => x"09", + 276 => x"71", + 277 => x"0a", + 278 => x"72", + 279 => x"51", + 280 => x"9f", + 281 => x"a4", + 282 => x"80", + 283 => x"05", + 284 => x"0b", + 285 => x"04", + 286 => x"9e", + 287 => x"80", + 288 => x"fe", + 289 => x"00", + 290 => x"94", + 291 => x"0d", + 292 => x"08", + 293 => x"52", + 294 => x"05", + 295 => x"de", + 296 => x"70", + 297 => x"85", + 298 => x"0c", + 299 => x"02", + 300 => x"3d", + 301 => x"94", + 302 => x"08", + 303 => x"88", + 304 => x"82", + 305 => x"08", + 306 => x"54", + 307 => x"94", + 308 => x"08", + 309 => x"f9", + 310 => x"0b", + 311 => x"05", + 312 => x"88", + 313 => x"25", + 314 => x"08", + 315 => x"30", + 316 => x"05", + 317 => x"94", + 318 => x"0c", + 319 => x"05", + 320 => x"81", + 321 => x"f4", + 322 => x"08", + 323 => x"94", + 324 => x"0c", + 325 => x"05", + 326 => x"ab", + 327 => x"8c", + 328 => x"94", + 329 => x"0c", + 330 => x"08", + 331 => x"94", + 332 => x"08", + 333 => x"0b", + 334 => x"05", + 335 => x"f0", + 336 => x"08", + 337 => x"80", + 338 => x"8c", + 339 => x"94", + 340 => x"08", + 341 => x"3f", + 342 => x"94", + 343 => x"0c", + 344 => x"fc", + 345 => x"2e", + 346 => x"08", + 347 => x"30", + 348 => x"05", + 349 => x"f8", + 350 => x"88", + 351 => x"3d", + 352 => x"04", + 353 => x"94", + 354 => x"0d", + 355 => x"08", + 356 => x"94", + 357 => x"08", + 358 => x"38", + 359 => x"05", + 360 => x"08", + 361 => x"81", + 362 => x"fc", + 363 => x"08", + 364 => x"80", + 365 => x"94", + 366 => x"08", + 367 => x"8c", + 368 => x"53", + 369 => x"05", + 370 => x"08", + 371 => x"51", + 372 => x"08", + 373 => x"f8", + 374 => x"94", + 375 => x"08", + 376 => x"38", + 377 => x"05", + 378 => x"08", + 379 => x"94", + 380 => x"08", + 381 => x"54", + 382 => x"94", + 383 => x"08", + 384 => x"fd", + 385 => x"0b", + 386 => x"05", + 387 => x"94", + 388 => x"0c", + 389 => x"05", + 390 => x"88", + 391 => x"ac", + 392 => x"fc", + 393 => x"2e", + 394 => x"0b", + 395 => x"05", + 396 => x"38", + 397 => x"05", + 398 => x"08", + 399 => x"94", + 400 => x"08", + 401 => x"fc", + 402 => x"39", + 403 => x"05", + 404 => x"80", + 405 => x"08", + 406 => x"94", + 407 => x"08", + 408 => x"94", + 409 => x"08", + 410 => x"05", + 411 => x"08", + 412 => x"94", + 413 => x"08", + 414 => x"05", + 415 => x"08", + 416 => x"94", + 417 => x"08", + 418 => x"08", + 419 => x"94", + 420 => x"08", + 421 => x"08", + 422 => x"ff", + 423 => x"08", + 424 => x"80", + 425 => x"94", + 426 => x"08", + 427 => x"f4", + 428 => x"8d", + 429 => x"f8", + 430 => x"94", + 431 => x"0c", + 432 => x"f4", + 433 => x"0c", + 434 => x"94", + 435 => x"3d", + 436 => x"0b", + 437 => x"8c", + 438 => x"87", + 439 => x"0c", + 440 => x"c0", + 441 => x"87", + 442 => x"08", + 443 => x"51", + 444 => x"2e", + 445 => x"c0", + 446 => x"51", + 447 => x"87", + 448 => x"08", + 449 => x"06", + 450 => x"38", + 451 => x"8c", + 452 => x"80", + 453 => x"71", + 454 => x"9f", + 455 => x"0b", + 456 => x"33", + 457 => x"3d", + 458 => x"3d", + 459 => x"7d", + 460 => x"80", + 461 => x"0b", + 462 => x"81", + 463 => x"82", + 464 => x"2e", + 465 => x"81", + 466 => x"0b", + 467 => x"8c", + 468 => x"c0", + 469 => x"84", + 470 => x"92", + 471 => x"c0", + 472 => x"70", + 473 => x"81", + 474 => x"53", + 475 => x"a7", + 476 => x"92", + 477 => x"81", + 478 => x"79", + 479 => x"51", + 480 => x"90", + 481 => x"2e", + 482 => x"76", + 483 => x"58", + 484 => x"54", + 485 => x"72", + 486 => x"70", + 487 => x"38", + 488 => x"8c", + 489 => x"ff", + 490 => x"c0", + 491 => x"51", + 492 => x"81", + 493 => x"92", + 494 => x"c0", + 495 => x"70", + 496 => x"51", + 497 => x"80", + 498 => x"80", + 499 => x"70", + 500 => x"81", + 501 => x"87", + 502 => x"08", + 503 => x"2e", + 504 => x"83", + 505 => x"71", + 506 => x"3d", + 507 => x"3d", + 508 => x"11", + 509 => x"71", + 510 => x"88", + 511 => x"84", + 512 => x"fd", + 513 => x"83", + 514 => x"12", + 515 => x"2b", + 516 => x"07", + 517 => x"70", + 518 => x"2b", + 519 => x"07", + 520 => x"53", + 521 => x"52", + 522 => x"04", + 523 => x"79", + 524 => x"9f", + 525 => x"57", + 526 => x"80", + 527 => x"88", + 528 => x"80", + 529 => x"33", + 530 => x"2e", + 531 => x"83", + 532 => x"80", + 533 => x"54", + 534 => x"fe", + 535 => x"88", + 536 => x"08", + 537 => x"3d", + 538 => x"fd", + 539 => x"08", + 540 => x"51", + 541 => x"88", + 542 => x"ff", + 543 => x"39", + 544 => x"82", + 545 => x"06", + 546 => x"2a", + 547 => x"05", + 548 => x"70", + 549 => x"92", + 550 => x"8e", + 551 => x"fe", + 552 => x"08", + 553 => x"55", + 554 => x"55", + 555 => x"89", + 556 => x"fb", + 557 => x"0b", + 558 => x"08", + 559 => x"12", + 560 => x"55", + 561 => x"56", + 562 => x"8d", + 563 => x"33", + 564 => x"94", + 565 => x"57", + 566 => x"0c", + 567 => x"04", + 568 => x"75", + 569 => x"0b", + 570 => x"f4", + 571 => x"51", + 572 => x"83", + 573 => x"06", + 574 => x"14", + 575 => x"3f", + 576 => x"2b", + 577 => x"51", + 578 => x"88", + 579 => x"ff", + 580 => x"88", + 581 => x"0d", + 582 => x"0d", + 583 => x"0b", + 584 => x"55", + 585 => x"23", + 586 => x"53", + 587 => x"88", + 588 => x"08", + 589 => x"38", + 590 => x"39", + 591 => x"73", + 592 => x"83", + 593 => x"06", + 594 => x"14", + 595 => x"8c", + 596 => x"80", + 597 => x"72", + 598 => x"3f", + 599 => x"85", + 600 => x"08", + 601 => x"16", + 602 => x"71", + 603 => x"3d", + 604 => x"3d", + 605 => x"0b", + 606 => x"08", + 607 => x"05", + 608 => x"ff", + 609 => x"57", + 610 => x"2e", + 611 => x"15", + 612 => x"86", + 613 => x"80", + 614 => x"8f", + 615 => x"80", + 616 => x"13", + 617 => x"8c", + 618 => x"72", + 619 => x"0b", + 620 => x"57", + 621 => x"27", + 622 => x"39", + 623 => x"ff", + 624 => x"2a", + 625 => x"a8", + 626 => x"fc", + 627 => x"52", + 628 => x"27", + 629 => x"52", + 630 => x"17", + 631 => x"38", + 632 => x"16", + 633 => x"51", + 634 => x"88", + 635 => x"0c", + 636 => x"80", + 637 => x"0c", + 638 => x"04", + 639 => x"60", + 640 => x"5e", + 641 => x"55", + 642 => x"09", + 643 => x"38", + 644 => x"44", + 645 => x"62", + 646 => x"56", + 647 => x"09", + 648 => x"38", + 649 => x"80", + 650 => x"0c", + 651 => x"51", + 652 => x"26", + 653 => x"51", + 654 => x"88", + 655 => x"7d", + 656 => x"39", + 657 => x"1d", + 658 => x"5a", + 659 => x"a0", + 660 => x"05", + 661 => x"15", + 662 => x"2e", + 663 => x"ef", + 664 => x"59", + 665 => x"08", + 666 => x"81", + 667 => x"ff", + 668 => x"70", + 669 => x"32", + 670 => x"73", + 671 => x"25", + 672 => x"52", + 673 => x"57", + 674 => x"c7", + 675 => x"2e", + 676 => x"83", + 677 => x"77", + 678 => x"07", + 679 => x"2e", + 680 => x"88", + 681 => x"78", + 682 => x"30", + 683 => x"9f", + 684 => x"57", + 685 => x"9b", + 686 => x"8b", + 687 => x"39", + 688 => x"70", + 689 => x"72", + 690 => x"57", + 691 => x"34", + 692 => x"7a", + 693 => x"80", + 694 => x"26", + 695 => x"55", + 696 => x"34", + 697 => x"b1", + 698 => x"80", + 699 => x"54", + 700 => x"85", + 701 => x"06", + 702 => x"1c", + 703 => x"51", + 704 => x"88", + 705 => x"08", + 706 => x"7c", + 707 => x"80", + 708 => x"38", + 709 => x"70", + 710 => x"81", + 711 => x"56", + 712 => x"8b", + 713 => x"08", + 714 => x"5b", + 715 => x"18", + 716 => x"2e", + 717 => x"70", + 718 => x"33", + 719 => x"05", + 720 => x"71", + 721 => x"56", + 722 => x"e2", + 723 => x"75", + 724 => x"38", + 725 => x"9a", + 726 => x"39", + 727 => x"88", + 728 => x"83", + 729 => x"84", + 730 => x"11", + 731 => x"74", + 732 => x"1d", + 733 => x"2a", + 734 => x"51", + 735 => x"89", + 736 => x"92", + 737 => x"8e", + 738 => x"fa", + 739 => x"08", + 740 => x"fd", + 741 => x"88", + 742 => x"0d", + 743 => x"0d", + 744 => x"57", + 745 => x"fe", + 746 => x"76", + 747 => x"3f", + 748 => x"08", + 749 => x"76", + 750 => x"3f", + 751 => x"ff", + 752 => x"82", + 753 => x"d4", + 754 => x"81", + 755 => x"38", + 756 => x"53", + 757 => x"51", + 758 => x"88", + 759 => x"08", + 760 => x"51", + 761 => x"88", + 762 => x"ff", + 763 => x"81", + 764 => x"a9", + 765 => x"80", + 766 => x"52", + 767 => x"aa", + 768 => x"56", + 769 => x"38", + 770 => x"e2", + 771 => x"83", + 772 => x"55", + 773 => x"c6", + 774 => x"81", + 775 => x"0c", + 776 => x"04", + 777 => x"65", + 778 => x"0b", + 779 => x"f4", + 780 => x"3f", + 781 => x"06", + 782 => x"74", + 783 => x"74", + 784 => x"3d", + 785 => x"5a", + 786 => x"88", + 787 => x"06", + 788 => x"2e", + 789 => x"b3", + 790 => x"83", + 791 => x"52", + 792 => x"c6", + 793 => x"ab", + 794 => x"33", + 795 => x"2e", + 796 => x"3d", + 797 => x"f7", + 798 => x"08", + 799 => x"76", + 800 => x"99", + 801 => x"81", + 802 => x"76", + 803 => x"81", + 804 => x"81", + 805 => x"39", + 806 => x"86", + 807 => x"82", + 808 => x"54", + 809 => x"52", + 810 => x"fe", + 811 => x"88", + 812 => x"38", + 813 => x"05", + 814 => x"3f", + 815 => x"ff", + 816 => x"77", + 817 => x"3d", + 818 => x"f6", + 819 => x"08", + 820 => x"05", + 821 => x"29", + 822 => x"ad", + 823 => x"52", + 824 => x"8a", + 825 => x"83", + 826 => x"7a", + 827 => x"0c", + 828 => x"82", + 829 => x"3d", + 830 => x"f5", + 831 => x"08", + 832 => x"95", + 833 => x"51", + 834 => x"88", + 835 => x"ff", + 836 => x"8c", + 837 => x"ef", + 838 => x"e7", + 839 => x"56", + 840 => x"ca", + 841 => x"83", + 842 => x"76", + 843 => x"31", + 844 => x"70", + 845 => x"1d", + 846 => x"71", + 847 => x"5c", + 848 => x"c4", + 849 => x"82", + 850 => x"1b", + 851 => x"e0", + 852 => x"56", + 853 => x"fe", + 854 => x"82", + 855 => x"f6", + 856 => x"38", + 857 => x"39", + 858 => x"80", + 859 => x"38", + 860 => x"76", + 861 => x"81", + 862 => x"95", + 863 => x"51", + 864 => x"88", + 865 => x"0c", + 866 => x"19", + 867 => x"1a", + 868 => x"ff", + 869 => x"1a", + 870 => x"84", + 871 => x"1b", + 872 => x"0b", + 873 => x"78", + 874 => x"9f", + 875 => x"56", + 876 => x"95", + 877 => x"ea", + 878 => x"0b", + 879 => x"08", + 880 => x"74", + 881 => x"df", + 882 => x"81", + 883 => x"3d", + 884 => x"69", + 885 => x"70", + 886 => x"05", + 887 => x"3f", + 888 => x"88", + 889 => x"38", + 890 => x"54", + 891 => x"93", + 892 => x"05", + 893 => x"2a", + 894 => x"51", + 895 => x"80", + 896 => x"83", + 897 => x"75", + 898 => x"3f", + 899 => x"16", + 900 => x"dc", + 901 => x"eb", + 902 => x"9c", + 903 => x"98", + 904 => x"0b", + 905 => x"73", + 906 => x"3d", + 907 => x"3d", + 908 => x"7e", + 909 => x"9f", + 910 => x"5b", + 911 => x"7b", + 912 => x"75", + 913 => x"d1", + 914 => x"33", + 915 => x"84", + 916 => x"2e", + 917 => x"91", + 918 => x"17", + 919 => x"80", + 920 => x"34", + 921 => x"b1", + 922 => x"08", + 923 => x"31", + 924 => x"27", + 925 => x"58", + 926 => x"81", + 927 => x"16", + 928 => x"ff", + 929 => x"74", + 930 => x"82", + 931 => x"05", + 932 => x"06", + 933 => x"06", + 934 => x"9e", + 935 => x"38", + 936 => x"55", + 937 => x"16", + 938 => x"80", + 939 => x"55", + 940 => x"ff", + 941 => x"a4", + 942 => x"16", + 943 => x"f3", + 944 => x"55", + 945 => x"2e", + 946 => x"88", + 947 => x"17", + 948 => x"08", + 949 => x"84", + 950 => x"51", + 951 => x"27", + 952 => x"55", + 953 => x"16", + 954 => x"06", + 955 => x"08", + 956 => x"f0", + 957 => x"08", + 958 => x"98", + 959 => x"98", + 960 => x"75", + 961 => x"16", + 962 => x"78", + 963 => x"e8", + 964 => x"59", + 965 => x"80", + 966 => x"0c", + 967 => x"04", + 968 => x"87", + 969 => x"08", + 970 => x"80", + 971 => x"ea", + 972 => x"08", + 973 => x"c0", + 974 => x"56", + 975 => x"80", + 976 => x"ea", + 977 => x"88", + 978 => x"c0", + 979 => x"87", + 980 => x"08", + 981 => x"80", + 982 => x"ea", + 983 => x"08", + 984 => x"c0", + 985 => x"56", + 986 => x"80", + 987 => x"ea", + 988 => x"88", + 989 => x"c0", + 990 => x"8c", + 991 => x"87", + 992 => x"0c", + 993 => x"0b", + 994 => x"94", + 995 => x"51", + 996 => x"88", + 997 => x"9f", + 998 => x"9b", + 999 => x"ae", + 1000 => x"0b", + 1001 => x"c0", + 1002 => x"55", + 1003 => x"05", + 1004 => x"52", + 1005 => x"f6", + 1006 => x"8d", + 1007 => x"73", + 1008 => x"38", + 1009 => x"e4", + 1010 => x"54", + 1011 => x"54", + 1012 => x"00", + 1013 => x"ff", + 1014 => x"ff", + 1015 => x"ff", + 1016 => x"42", + 1017 => x"54", + 1018 => x"2e", + 1019 => x"00", + 1020 => x"01", + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 0 - Port B - bits 7 downto 0 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM0(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(7 downto 0); + memBRead(7 downto 0) <= memBWrite(7 downto 0); + else + memBRead(7 downto 0) <= RAM0(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 1 - Port B - bits 15 downto 8 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM1(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(15 downto 8); + memBRead(15 downto 8) <= memBWrite(15 downto 8); + else + memBRead(15 downto 8) <= RAM1(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 2 - Port B - bits 23 downto 16 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM2(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(23 downto 16); + memBRead(23 downto 16) <= memBWrite(23 downto 16); + else + memBRead(23 downto 16) <= RAM2(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 3 - Port B - bits 31 downto 24 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM3(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(31 downto 24); + memBRead(31 downto 24) <= memBWrite(31 downto 24); + else + memBRead(31 downto 24) <= RAM3(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + +end arch; diff --git a/zpu/devices/sysbus/BRAM/IOCP_SinglePortBRAM.vhd b/zpu/devices/sysbus/BRAM/IOCP_SinglePortBRAM.vhd new file mode 100644 index 0000000..805a2c0 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/IOCP_SinglePortBRAM.vhd @@ -0,0 +1,164 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity SinglePortBRAM is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end SinglePortBRAM; + +architecture arch of SinglePortBRAM is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; +end arch; diff --git a/zpu/devices/sysbus/BRAM/IOCP_SinglePortBootBRAM.vhd b/zpu/devices/sysbus/BRAM/IOCP_SinglePortBootBRAM.vhd new file mode 100644 index 0000000..fdc6c22 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/IOCP_SinglePortBootBRAM.vhd @@ -0,0 +1,4248 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity SinglePortBootBRAM is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end SinglePortBootBRAM; + +architecture arch of SinglePortBootBRAM is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + 0 => x"88", + 1 => x"00", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"0b", + 10 => x"08", + 11 => x"8c", + 12 => x"04", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"08", + 17 => x"09", + 18 => x"05", + 19 => x"83", + 20 => x"52", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"08", + 25 => x"73", + 26 => x"81", + 27 => x"83", + 28 => x"06", + 29 => x"ff", + 30 => x"0b", + 31 => x"00", + 32 => x"05", + 33 => x"73", + 34 => x"06", + 35 => x"06", + 36 => x"06", + 37 => x"00", + 38 => x"00", + 39 => x"00", + 40 => x"73", + 41 => x"53", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"09", + 49 => x"06", + 50 => x"72", + 51 => x"72", + 52 => x"31", + 53 => x"06", + 54 => x"51", + 55 => x"00", + 56 => x"73", + 57 => x"53", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"88", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"2b", + 81 => x"04", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"06", + 89 => x"0b", + 90 => x"a7", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"ff", + 97 => x"2a", + 98 => x"0a", + 99 => x"05", + 100 => x"51", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"51", + 105 => x"83", + 106 => x"05", + 107 => x"2b", + 108 => x"72", + 109 => x"51", + 110 => x"00", + 111 => x"00", + 112 => x"05", + 113 => x"70", + 114 => x"06", + 115 => x"53", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"05", + 121 => x"70", + 122 => x"06", + 123 => x"06", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"05", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"81", + 137 => x"51", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"06", + 145 => x"06", + 146 => x"04", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"08", + 153 => x"09", + 154 => x"05", + 155 => x"2a", + 156 => x"52", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"08", + 161 => x"9f", + 162 => x"06", + 163 => x"08", + 164 => x"0b", + 165 => x"00", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"75", + 170 => x"89", + 171 => x"50", + 172 => x"90", + 173 => x"88", + 174 => x"00", + 175 => x"00", + 176 => x"08", + 177 => x"75", + 178 => x"8b", + 179 => x"50", + 180 => x"90", + 181 => x"88", + 182 => x"00", + 183 => x"00", + 184 => x"81", + 185 => x"0a", + 186 => x"05", + 187 => x"06", + 188 => x"74", + 189 => x"06", + 190 => x"51", + 191 => x"00", + 192 => x"81", + 193 => x"0a", + 194 => x"ff", + 195 => x"71", + 196 => x"72", + 197 => x"05", + 198 => x"51", + 199 => x"00", + 200 => x"04", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"52", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"72", + 233 => x"52", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"ff", + 249 => x"51", + 250 => x"00", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"04", + 257 => x"00", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"53", + 266 => x"00", + 267 => x"06", + 268 => x"09", + 269 => x"05", + 270 => x"2b", + 271 => x"06", + 272 => x"04", + 273 => x"72", + 274 => x"05", + 275 => x"05", + 276 => x"72", + 277 => x"53", + 278 => x"51", + 279 => x"04", + 280 => x"a0", + 281 => x"38", + 282 => x"84", + 283 => x"0b", + 284 => x"e2", + 285 => x"51", + 286 => x"00", + 287 => x"88", + 288 => x"00", + 289 => x"02", + 290 => x"3d", + 291 => x"94", + 292 => x"08", + 293 => x"88", + 294 => x"82", + 295 => x"08", + 296 => x"54", + 297 => x"94", + 298 => x"08", + 299 => x"fd", + 300 => x"53", + 301 => x"05", + 302 => x"08", + 303 => x"51", + 304 => x"88", + 305 => x"0c", + 306 => x"0d", + 307 => x"94", + 308 => x"0c", + 309 => x"80", + 310 => x"fc", + 311 => x"08", + 312 => x"80", + 313 => x"94", + 314 => x"08", + 315 => x"88", + 316 => x"0b", + 317 => x"05", + 318 => x"fc", + 319 => x"38", + 320 => x"08", + 321 => x"94", + 322 => x"08", + 323 => x"05", + 324 => x"8c", + 325 => x"25", + 326 => x"08", + 327 => x"30", + 328 => x"05", + 329 => x"94", + 330 => x"0c", + 331 => x"05", + 332 => x"81", + 333 => x"f0", + 334 => x"08", + 335 => x"94", + 336 => x"0c", + 337 => x"08", + 338 => x"52", + 339 => x"05", + 340 => x"a7", + 341 => x"70", + 342 => x"05", + 343 => x"08", + 344 => x"80", + 345 => x"94", + 346 => x"08", + 347 => x"f8", + 348 => x"08", + 349 => x"70", + 350 => x"89", + 351 => x"0c", + 352 => x"02", + 353 => x"3d", + 354 => x"94", + 355 => x"0c", + 356 => x"05", + 357 => x"93", + 358 => x"88", + 359 => x"94", + 360 => x"0c", + 361 => x"08", + 362 => x"94", + 363 => x"08", + 364 => x"38", + 365 => x"05", + 366 => x"08", + 367 => x"81", + 368 => x"8c", + 369 => x"94", + 370 => x"08", + 371 => x"88", + 372 => x"08", + 373 => x"54", + 374 => x"05", + 375 => x"8c", + 376 => x"f8", + 377 => x"94", + 378 => x"0c", + 379 => x"05", + 380 => x"0c", + 381 => x"0d", + 382 => x"94", + 383 => x"0c", + 384 => x"81", + 385 => x"fc", + 386 => x"0b", + 387 => x"05", + 388 => x"8c", + 389 => x"08", + 390 => x"27", + 391 => x"08", + 392 => x"80", + 393 => x"80", + 394 => x"8c", + 395 => x"99", + 396 => x"8c", + 397 => x"94", + 398 => x"0c", + 399 => x"05", + 400 => x"08", + 401 => x"c9", + 402 => x"fc", + 403 => x"2e", + 404 => x"94", + 405 => x"08", + 406 => x"05", + 407 => x"38", + 408 => x"05", + 409 => x"8c", + 410 => x"94", + 411 => x"0c", + 412 => x"05", + 413 => x"fc", + 414 => x"94", + 415 => x"0c", + 416 => x"05", + 417 => x"94", + 418 => x"0c", + 419 => x"05", + 420 => x"94", + 421 => x"0c", + 422 => x"94", + 423 => x"08", + 424 => x"38", + 425 => x"05", + 426 => x"08", + 427 => x"51", + 428 => x"08", + 429 => x"70", + 430 => x"05", + 431 => x"08", + 432 => x"88", + 433 => x"0d", + 434 => x"ff", + 435 => x"88", + 436 => x"92", + 437 => x"0b", + 438 => x"8c", + 439 => x"87", + 440 => x"0c", + 441 => x"8c", + 442 => x"06", + 443 => x"80", + 444 => x"87", + 445 => x"08", + 446 => x"38", + 447 => x"8c", + 448 => x"80", + 449 => x"93", + 450 => x"98", + 451 => x"70", + 452 => x"38", + 453 => x"0b", + 454 => x"0b", + 455 => x"f0", + 456 => x"83", + 457 => x"fa", + 458 => x"7b", + 459 => x"56", + 460 => x"0b", + 461 => x"33", + 462 => x"55", + 463 => x"75", + 464 => x"06", + 465 => x"85", + 466 => x"98", + 467 => x"87", + 468 => x"0c", + 469 => x"c0", + 470 => x"87", + 471 => x"08", + 472 => x"70", + 473 => x"52", + 474 => x"2e", + 475 => x"c0", + 476 => x"70", + 477 => x"76", + 478 => x"53", + 479 => x"2e", + 480 => x"80", + 481 => x"71", + 482 => x"05", + 483 => x"14", + 484 => x"55", + 485 => x"51", + 486 => x"8b", + 487 => x"98", + 488 => x"70", + 489 => x"87", + 490 => x"08", + 491 => x"38", + 492 => x"c0", + 493 => x"87", + 494 => x"08", + 495 => x"51", + 496 => x"38", + 497 => x"80", + 498 => x"52", + 499 => x"09", + 500 => x"38", + 501 => x"8c", + 502 => x"72", + 503 => x"06", + 504 => x"52", + 505 => x"88", + 506 => x"fe", + 507 => x"81", + 508 => x"33", + 509 => x"07", + 510 => x"51", + 511 => x"04", + 512 => x"75", + 513 => x"82", + 514 => x"90", + 515 => x"2b", + 516 => x"33", + 517 => x"88", + 518 => x"71", + 519 => x"52", + 520 => x"54", + 521 => x"0d", + 522 => x"0d", + 523 => x"0b", + 524 => x"57", + 525 => x"27", + 526 => x"76", + 527 => x"27", + 528 => x"75", + 529 => x"82", + 530 => x"74", + 531 => x"38", + 532 => x"74", + 533 => x"83", + 534 => x"76", + 535 => x"17", + 536 => x"88", + 537 => x"55", + 538 => x"88", + 539 => x"74", + 540 => x"3f", + 541 => x"ff", + 542 => x"ad", + 543 => x"76", + 544 => x"fc", + 545 => x"87", + 546 => x"08", + 547 => x"3d", + 548 => x"fd", + 549 => x"08", + 550 => x"51", + 551 => x"88", + 552 => x"06", + 553 => x"81", + 554 => x"0c", + 555 => x"04", + 556 => x"0b", + 557 => x"f4", + 558 => x"88", + 559 => x"05", + 560 => x"80", + 561 => x"27", + 562 => x"14", + 563 => x"29", + 564 => x"05", + 565 => x"88", + 566 => x"0d", + 567 => x"0d", + 568 => x"0b", + 569 => x"9f", + 570 => x"33", + 571 => x"71", + 572 => x"81", + 573 => x"94", + 574 => x"ef", + 575 => x"90", + 576 => x"14", + 577 => x"3f", + 578 => x"ff", + 579 => x"07", + 580 => x"3d", + 581 => x"3d", + 582 => x"0b", + 583 => x"08", + 584 => x"75", + 585 => x"08", + 586 => x"2e", + 587 => x"14", + 588 => x"85", + 589 => x"b0", + 590 => x"38", + 591 => x"71", + 592 => x"81", + 593 => x"90", + 594 => x"72", + 595 => x"72", + 596 => x"38", + 597 => x"d8", + 598 => x"52", + 599 => x"14", + 600 => x"90", + 601 => x"52", + 602 => x"86", + 603 => x"fa", + 604 => x"0b", + 605 => x"f4", + 606 => x"81", + 607 => x"ff", + 608 => x"54", + 609 => x"80", + 610 => x"90", + 611 => x"72", + 612 => x"52", + 613 => x"73", + 614 => x"71", + 615 => x"81", + 616 => x"0c", + 617 => x"53", + 618 => x"83", + 619 => x"22", + 620 => x"76", + 621 => x"b5", + 622 => x"33", + 623 => x"84", + 624 => x"71", + 625 => x"51", + 626 => x"81", + 627 => x"08", + 628 => x"83", + 629 => x"88", + 630 => x"96", + 631 => x"8c", + 632 => x"08", + 633 => x"3f", + 634 => x"16", + 635 => x"23", + 636 => x"88", + 637 => x"0d", + 638 => x"0d", + 639 => x"58", + 640 => x"33", + 641 => x"2e", + 642 => x"88", + 643 => x"70", + 644 => x"39", + 645 => x"56", + 646 => x"2e", + 647 => x"84", + 648 => x"43", + 649 => x"1d", + 650 => x"33", + 651 => x"9f", + 652 => x"7b", + 653 => x"3f", + 654 => x"80", + 655 => x"d3", + 656 => x"84", + 657 => x"58", + 658 => x"55", + 659 => x"81", + 660 => x"ff", + 661 => x"ff", + 662 => x"06", + 663 => x"70", + 664 => x"7f", + 665 => x"7a", + 666 => x"81", + 667 => x"13", + 668 => x"af", + 669 => x"a0", + 670 => x"80", + 671 => x"51", + 672 => x"5d", + 673 => x"80", + 674 => x"ae", + 675 => x"06", + 676 => x"55", + 677 => x"75", + 678 => x"80", + 679 => x"79", + 680 => x"30", + 681 => x"70", + 682 => x"07", + 683 => x"51", + 684 => x"75", + 685 => x"58", + 686 => x"ab", + 687 => x"19", + 688 => x"06", + 689 => x"5a", + 690 => x"75", + 691 => x"39", + 692 => x"0c", + 693 => x"a0", + 694 => x"81", + 695 => x"1a", + 696 => x"fc", + 697 => x"08", + 698 => x"a0", + 699 => x"70", + 700 => x"e0", + 701 => x"90", + 702 => x"7c", + 703 => x"3f", + 704 => x"88", + 705 => x"38", + 706 => x"74", + 707 => x"ee", + 708 => x"33", + 709 => x"70", + 710 => x"56", + 711 => x"38", + 712 => x"1e", + 713 => x"59", + 714 => x"ff", + 715 => x"ff", + 716 => x"79", + 717 => x"5b", + 718 => x"81", + 719 => x"71", + 720 => x"56", + 721 => x"2e", + 722 => x"39", + 723 => x"92", + 724 => x"fc", + 725 => x"8e", + 726 => x"56", + 727 => x"38", + 728 => x"56", + 729 => x"8b", + 730 => x"55", + 731 => x"8b", + 732 => x"84", + 733 => x"06", + 734 => x"74", + 735 => x"56", + 736 => x"56", + 737 => x"51", + 738 => x"88", + 739 => x"0c", + 740 => x"75", + 741 => x"3d", + 742 => x"3d", + 743 => x"59", + 744 => x"83", + 745 => x"52", + 746 => x"fb", + 747 => x"88", + 748 => x"38", + 749 => x"b3", + 750 => x"83", + 751 => x"55", + 752 => x"82", + 753 => x"09", + 754 => x"ce", + 755 => x"b6", + 756 => x"76", + 757 => x"3f", + 758 => x"88", + 759 => x"76", + 760 => x"3f", + 761 => x"ff", + 762 => x"74", + 763 => x"2e", + 764 => x"54", + 765 => x"77", + 766 => x"f6", + 767 => x"08", + 768 => x"94", + 769 => x"f7", + 770 => x"08", + 771 => x"06", + 772 => x"82", + 773 => x"38", + 774 => x"88", + 775 => x"0d", + 776 => x"0d", + 777 => x"0b", + 778 => x"9f", + 779 => x"9b", + 780 => x"81", + 781 => x"56", + 782 => x"38", + 783 => x"8d", + 784 => x"57", + 785 => x"3f", + 786 => x"ff", + 787 => x"81", + 788 => x"06", + 789 => x"54", + 790 => x"74", + 791 => x"f5", + 792 => x"08", + 793 => x"3d", + 794 => x"80", + 795 => x"95", + 796 => x"51", + 797 => x"88", + 798 => x"53", + 799 => x"fe", + 800 => x"08", + 801 => x"57", + 802 => x"09", + 803 => x"38", + 804 => x"99", + 805 => x"2e", + 806 => x"56", + 807 => x"a4", + 808 => x"79", + 809 => x"f4", + 810 => x"56", + 811 => x"fd", + 812 => x"e5", + 813 => x"b3", + 814 => x"83", + 815 => x"58", + 816 => x"95", + 817 => x"51", + 818 => x"88", + 819 => x"af", + 820 => x"71", + 821 => x"05", + 822 => x"54", + 823 => x"f6", + 824 => x"08", + 825 => x"06", + 826 => x"1a", + 827 => x"33", + 828 => x"95", + 829 => x"51", + 830 => x"88", + 831 => x"23", + 832 => x"05", + 833 => x"3f", + 834 => x"ff", + 835 => x"75", + 836 => x"3d", + 837 => x"f5", + 838 => x"08", + 839 => x"f5", + 840 => x"08", + 841 => x"06", + 842 => x"79", + 843 => x"22", + 844 => x"82", + 845 => x"72", + 846 => x"59", + 847 => x"ee", + 848 => x"08", + 849 => x"88", + 850 => x"08", + 851 => x"56", + 852 => x"df", + 853 => x"38", + 854 => x"ff", + 855 => x"85", + 856 => x"89", + 857 => x"76", + 858 => x"c1", + 859 => x"34", + 860 => x"09", + 861 => x"38", + 862 => x"05", + 863 => x"3f", + 864 => x"1a", + 865 => x"8c", + 866 => x"90", + 867 => x"83", + 868 => x"8c", + 869 => x"71", + 870 => x"94", + 871 => x"80", + 872 => x"34", + 873 => x"0b", + 874 => x"80", + 875 => x"0c", + 876 => x"04", + 877 => x"0b", + 878 => x"f4", + 879 => x"54", + 880 => x"80", + 881 => x"0b", + 882 => x"98", + 883 => x"45", + 884 => x"3d", + 885 => x"ec", + 886 => x"9d", + 887 => x"54", + 888 => x"c0", + 889 => x"33", + 890 => x"2e", + 891 => x"a7", + 892 => x"84", + 893 => x"06", + 894 => x"73", + 895 => x"38", + 896 => x"39", + 897 => x"d5", + 898 => x"a0", + 899 => x"3d", + 900 => x"f3", + 901 => x"08", + 902 => x"73", + 903 => x"81", + 904 => x"34", + 905 => x"98", + 906 => x"f6", + 907 => x"7f", + 908 => x"0b", + 909 => x"59", + 910 => x"80", + 911 => x"57", + 912 => x"81", + 913 => x"16", + 914 => x"55", + 915 => x"80", + 916 => x"38", + 917 => x"81", + 918 => x"39", + 919 => x"17", + 920 => x"81", + 921 => x"16", + 922 => x"08", + 923 => x"78", + 924 => x"74", + 925 => x"2e", + 926 => x"98", + 927 => x"83", + 928 => x"57", + 929 => x"38", + 930 => x"ff", + 931 => x"2a", + 932 => x"ff", + 933 => x"79", + 934 => x"87", + 935 => x"08", + 936 => x"a4", + 937 => x"f3", + 938 => x"08", + 939 => x"27", + 940 => x"74", + 941 => x"a4", + 942 => x"f3", + 943 => x"08", + 944 => x"80", + 945 => x"38", + 946 => x"a8", + 947 => x"16", + 948 => x"06", + 949 => x"31", + 950 => x"75", + 951 => x"77", + 952 => x"98", + 953 => x"ff", + 954 => x"16", + 955 => x"51", + 956 => x"88", + 957 => x"38", + 958 => x"15", + 959 => x"77", + 960 => x"08", + 961 => x"58", + 962 => x"fe", + 963 => x"19", + 964 => x"39", + 965 => x"88", + 966 => x"0d", + 967 => x"0d", + 968 => x"8c", + 969 => x"84", + 970 => x"51", + 971 => x"88", + 972 => x"87", + 973 => x"08", + 974 => x"84", + 975 => x"51", + 976 => x"73", + 977 => x"87", + 978 => x"0c", + 979 => x"9c", + 980 => x"84", + 981 => x"51", + 982 => x"88", + 983 => x"87", + 984 => x"08", + 985 => x"84", + 986 => x"51", + 987 => x"73", + 988 => x"87", + 989 => x"0c", + 990 => x"0b", + 991 => x"84", + 992 => x"83", + 993 => x"94", + 994 => x"f8", + 995 => x"3f", + 996 => x"38", + 997 => x"fc", + 998 => x"08", + 999 => x"80", + 1000 => x"87", + 1001 => x"0c", + 1002 => x"fc", + 1003 => x"80", + 1004 => x"fc", + 1005 => x"08", + 1006 => x"54", + 1007 => x"86", + 1008 => x"55", + 1009 => x"80", + 1010 => x"80", + 1011 => x"00", + 1012 => x"ff", + 1013 => x"ff", + 1014 => x"ff", + 1015 => x"00", + 1016 => x"54", + 1017 => x"59", + 1018 => x"4d", + 1019 => x"00", + 1020 => x"00", + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + 0 => x"0b", + 1 => x"00", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"8c", + 9 => x"0b", + 10 => x"80", + 11 => x"0c", + 12 => x"0c", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"06", + 17 => x"06", + 18 => x"82", + 19 => x"2a", + 20 => x"06", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"06", + 25 => x"ff", + 26 => x"09", + 27 => x"05", + 28 => x"09", + 29 => x"ff", + 30 => x"0b", + 31 => x"04", + 32 => x"81", + 33 => x"73", + 34 => x"09", + 35 => x"73", + 36 => x"81", + 37 => x"04", + 38 => x"00", + 39 => x"00", + 40 => x"24", + 41 => x"07", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"81", + 50 => x"05", + 51 => x"0a", + 52 => x"0a", + 53 => x"81", + 54 => x"53", + 55 => x"00", + 56 => x"26", + 57 => x"07", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"51", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"9f", + 89 => x"05", + 90 => x"88", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"2a", + 97 => x"06", + 98 => x"09", + 99 => x"ff", + 100 => x"53", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"53", + 105 => x"73", + 106 => x"81", + 107 => x"83", + 108 => x"07", + 109 => x"0c", + 110 => x"00", + 111 => x"00", + 112 => x"81", + 113 => x"09", + 114 => x"09", + 115 => x"06", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"81", + 121 => x"09", + 122 => x"09", + 123 => x"81", + 124 => x"04", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"81", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"09", + 137 => x"53", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"09", + 146 => x"51", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"06", + 153 => x"06", + 154 => x"83", + 155 => x"10", + 156 => x"06", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"06", + 161 => x"0b", + 162 => x"83", + 163 => x"05", + 164 => x"0b", + 165 => x"04", + 166 => x"00", + 167 => x"00", + 168 => x"8c", + 169 => x"75", + 170 => x"0b", + 171 => x"50", + 172 => x"56", + 173 => x"0c", + 174 => x"04", + 175 => x"00", + 176 => x"8c", + 177 => x"75", + 178 => x"0b", + 179 => x"50", + 180 => x"56", + 181 => x"0c", + 182 => x"04", + 183 => x"00", + 184 => x"70", + 185 => x"06", + 186 => x"ff", + 187 => x"71", + 188 => x"72", + 189 => x"05", + 190 => x"51", + 191 => x"00", + 192 => x"70", + 193 => x"06", + 194 => x"06", + 195 => x"54", + 196 => x"09", + 197 => x"ff", + 198 => x"51", + 199 => x"00", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"05", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"05", + 233 => x"05", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"05", + 249 => x"53", + 250 => x"04", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"04", + 257 => x"00", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"10", + 266 => x"00", + 267 => x"ff", + 268 => x"06", + 269 => x"83", + 270 => x"10", + 271 => x"fc", + 272 => x"51", + 273 => x"80", + 274 => x"ff", + 275 => x"06", + 276 => x"52", + 277 => x"0a", + 278 => x"38", + 279 => x"51", + 280 => x"70", + 281 => x"8e", + 282 => x"70", + 283 => x"0c", + 284 => x"88", + 285 => x"fe", + 286 => x"04", + 287 => x"00", + 288 => x"00", + 289 => x"08", + 290 => x"fd", + 291 => x"53", + 292 => x"05", + 293 => x"08", + 294 => x"51", + 295 => x"88", + 296 => x"0c", + 297 => x"0d", + 298 => x"94", + 299 => x"0c", + 300 => x"81", + 301 => x"8c", + 302 => x"94", + 303 => x"08", + 304 => x"3f", + 305 => x"88", + 306 => x"3d", + 307 => x"04", + 308 => x"94", + 309 => x"0d", + 310 => x"08", + 311 => x"94", + 312 => x"08", + 313 => x"38", + 314 => x"05", + 315 => x"08", + 316 => x"80", + 317 => x"f4", + 318 => x"08", + 319 => x"88", + 320 => x"94", + 321 => x"0c", + 322 => x"05", + 323 => x"fc", + 324 => x"08", + 325 => x"80", + 326 => x"94", + 327 => x"08", + 328 => x"8c", + 329 => x"0b", + 330 => x"05", + 331 => x"fc", + 332 => x"38", + 333 => x"08", + 334 => x"94", + 335 => x"08", + 336 => x"05", + 337 => x"94", + 338 => x"08", + 339 => x"88", + 340 => x"81", + 341 => x"08", + 342 => x"f8", + 343 => x"94", + 344 => x"08", + 345 => x"38", + 346 => x"05", + 347 => x"08", + 348 => x"94", + 349 => x"08", + 350 => x"54", + 351 => x"94", + 352 => x"08", + 353 => x"fb", + 354 => x"0b", + 355 => x"05", + 356 => x"88", + 357 => x"25", + 358 => x"08", + 359 => x"30", + 360 => x"05", + 361 => x"94", + 362 => x"0c", + 363 => x"05", + 364 => x"8c", + 365 => x"8c", + 366 => x"94", + 367 => x"0c", + 368 => x"08", + 369 => x"52", + 370 => x"05", + 371 => x"3f", + 372 => x"94", + 373 => x"0c", + 374 => x"fc", + 375 => x"2e", + 376 => x"08", + 377 => x"30", + 378 => x"05", + 379 => x"f8", + 380 => x"88", + 381 => x"3d", + 382 => x"04", + 383 => x"94", + 384 => x"0d", + 385 => x"08", + 386 => x"80", + 387 => x"f8", + 388 => x"08", + 389 => x"94", + 390 => x"08", + 391 => x"94", + 392 => x"08", + 393 => x"38", + 394 => x"08", + 395 => x"24", + 396 => x"08", + 397 => x"10", + 398 => x"05", + 399 => x"fc", + 400 => x"94", + 401 => x"0c", + 402 => x"08", + 403 => x"80", + 404 => x"38", + 405 => x"05", + 406 => x"88", + 407 => x"a1", + 408 => x"88", + 409 => x"08", + 410 => x"31", + 411 => x"05", + 412 => x"f8", + 413 => x"08", + 414 => x"07", + 415 => x"05", + 416 => x"fc", + 417 => x"2a", + 418 => x"05", + 419 => x"8c", + 420 => x"2a", + 421 => x"05", + 422 => x"39", + 423 => x"05", + 424 => x"8f", + 425 => x"88", + 426 => x"94", + 427 => x"0c", + 428 => x"94", + 429 => x"08", + 430 => x"f4", + 431 => x"94", + 432 => x"08", + 433 => x"3d", + 434 => x"04", + 435 => x"81", + 436 => x"c0", + 437 => x"81", + 438 => x"92", + 439 => x"0b", + 440 => x"8c", + 441 => x"92", + 442 => x"82", + 443 => x"70", + 444 => x"38", + 445 => x"8c", + 446 => x"e9", + 447 => x"92", + 448 => x"80", + 449 => x"71", + 450 => x"c0", + 451 => x"51", + 452 => x"88", + 453 => x"0b", + 454 => x"34", + 455 => x"9f", + 456 => x"0c", + 457 => x"04", + 458 => x"78", + 459 => x"58", + 460 => x"0b", + 461 => x"f0", + 462 => x"52", + 463 => x"70", + 464 => x"81", + 465 => x"38", + 466 => x"c0", + 467 => x"79", + 468 => x"80", + 469 => x"87", + 470 => x"0c", + 471 => x"8c", + 472 => x"2a", + 473 => x"51", + 474 => x"80", + 475 => x"87", + 476 => x"08", + 477 => x"06", + 478 => x"52", + 479 => x"80", + 480 => x"70", + 481 => x"38", + 482 => x"81", + 483 => x"ff", + 484 => x"15", + 485 => x"06", + 486 => x"2e", + 487 => x"c0", + 488 => x"51", + 489 => x"38", + 490 => x"8c", + 491 => x"95", + 492 => x"87", + 493 => x"0c", + 494 => x"8c", + 495 => x"06", + 496 => x"f4", + 497 => x"fc", + 498 => x"52", + 499 => x"2e", + 500 => x"8f", + 501 => x"98", + 502 => x"70", + 503 => x"81", + 504 => x"81", + 505 => x"0c", + 506 => x"04", + 507 => x"74", + 508 => x"71", + 509 => x"2b", + 510 => x"53", + 511 => x"0d", + 512 => x"0d", + 513 => x"33", + 514 => x"71", + 515 => x"88", + 516 => x"14", + 517 => x"07", + 518 => x"33", + 519 => x"0c", + 520 => x"56", + 521 => x"3d", + 522 => x"3d", + 523 => x"0b", + 524 => x"08", + 525 => x"77", + 526 => x"38", + 527 => x"08", + 528 => x"38", + 529 => x"74", + 530 => x"38", + 531 => x"ae", + 532 => x"39", + 533 => x"10", + 534 => x"53", + 535 => x"8c", + 536 => x"52", + 537 => x"52", + 538 => x"3f", + 539 => x"38", + 540 => x"f8", + 541 => x"83", + 542 => x"55", + 543 => x"54", + 544 => x"83", + 545 => x"76", + 546 => x"17", + 547 => x"88", + 548 => x"55", + 549 => x"88", + 550 => x"74", + 551 => x"3f", + 552 => x"0a", + 553 => x"39", + 554 => x"88", + 555 => x"0d", + 556 => x"0d", + 557 => x"9f", + 558 => x"19", + 559 => x"fe", + 560 => x"54", + 561 => x"73", + 562 => x"82", + 563 => x"71", + 564 => x"08", + 565 => x"75", + 566 => x"3d", + 567 => x"3d", + 568 => x"80", + 569 => x"0b", + 570 => x"70", + 571 => x"53", + 572 => x"09", + 573 => x"38", + 574 => x"fd", + 575 => x"08", + 576 => x"9a", + 577 => x"e4", + 578 => x"83", + 579 => x"73", + 580 => x"85", + 581 => x"fc", + 582 => x"0b", + 583 => x"f4", + 584 => x"80", + 585 => x"15", + 586 => x"81", + 587 => x"88", + 588 => x"26", + 589 => x"52", + 590 => x"90", + 591 => x"52", + 592 => x"09", + 593 => x"38", + 594 => x"53", + 595 => x"0c", + 596 => x"8b", + 597 => x"fe", + 598 => x"08", + 599 => x"90", + 600 => x"71", + 601 => x"80", + 602 => x"0c", + 603 => x"04", + 604 => x"78", + 605 => x"9f", + 606 => x"22", + 607 => x"83", + 608 => x"57", + 609 => x"73", + 610 => x"38", + 611 => x"53", + 612 => x"83", + 613 => x"39", + 614 => x"52", + 615 => x"38", + 616 => x"16", + 617 => x"08", + 618 => x"38", + 619 => x"17", + 620 => x"73", + 621 => x"38", + 622 => x"16", + 623 => x"74", + 624 => x"52", + 625 => x"72", + 626 => x"3f", + 627 => x"88", + 628 => x"38", + 629 => x"08", + 630 => x"27", + 631 => x"08", + 632 => x"88", + 633 => x"c9", + 634 => x"90", + 635 => x"75", + 636 => x"71", + 637 => x"3d", + 638 => x"3d", + 639 => x"64", + 640 => x"75", + 641 => x"a0", + 642 => x"06", + 643 => x"16", + 644 => x"ef", + 645 => x"33", + 646 => x"af", + 647 => x"06", + 648 => x"16", + 649 => x"88", + 650 => x"70", + 651 => x"74", + 652 => x"38", + 653 => x"df", + 654 => x"56", + 655 => x"82", + 656 => x"3d", + 657 => x"70", + 658 => x"8a", + 659 => x"70", + 660 => x"34", + 661 => x"74", + 662 => x"81", + 663 => x"80", + 664 => x"88", + 665 => x"5a", + 666 => x"70", + 667 => x"60", + 668 => x"70", + 669 => x"30", + 670 => x"71", + 671 => x"51", + 672 => x"53", + 673 => x"74", + 674 => x"76", + 675 => x"81", + 676 => x"81", + 677 => x"27", + 678 => x"74", + 679 => x"38", + 680 => x"70", + 681 => x"32", + 682 => x"73", + 683 => x"53", + 684 => x"56", + 685 => x"88", + 686 => x"ff", + 687 => x"81", + 688 => x"ff", + 689 => x"53", + 690 => x"76", + 691 => x"98", + 692 => x"7f", + 693 => x"76", + 694 => x"38", + 695 => x"8b", + 696 => x"51", + 697 => x"88", + 698 => x"38", + 699 => x"22", + 700 => x"83", + 701 => x"55", + 702 => x"52", + 703 => x"a8", + 704 => x"57", + 705 => x"fb", + 706 => x"55", + 707 => x"80", + 708 => x"1d", + 709 => x"2a", + 710 => x"51", + 711 => x"b2", + 712 => x"84", + 713 => x"08", + 714 => x"58", + 715 => x"77", + 716 => x"38", + 717 => x"05", + 718 => x"70", + 719 => x"33", + 720 => x"52", + 721 => x"80", + 722 => x"86", + 723 => x"2e", + 724 => x"51", + 725 => x"ff", + 726 => x"08", + 727 => x"b4", + 728 => x"76", + 729 => x"08", + 730 => x"51", + 731 => x"38", + 732 => x"70", + 733 => x"81", + 734 => x"56", + 735 => x"83", + 736 => x"81", + 737 => x"7c", + 738 => x"3f", + 739 => x"1d", + 740 => x"39", + 741 => x"90", + 742 => x"f9", + 743 => x"7b", + 744 => x"54", + 745 => x"77", + 746 => x"f6", + 747 => x"56", + 748 => x"e7", + 749 => x"f8", + 750 => x"08", + 751 => x"06", + 752 => x"74", + 753 => x"2e", + 754 => x"80", + 755 => x"54", + 756 => x"52", + 757 => x"d0", + 758 => x"56", + 759 => x"38", + 760 => x"88", + 761 => x"83", + 762 => x"55", + 763 => x"c6", + 764 => x"82", + 765 => x"53", + 766 => x"51", + 767 => x"88", + 768 => x"08", + 769 => x"51", + 770 => x"88", + 771 => x"ff", + 772 => x"81", + 773 => x"83", + 774 => x"75", + 775 => x"3d", + 776 => x"3d", + 777 => x"80", + 778 => x"0b", + 779 => x"f5", + 780 => x"08", + 781 => x"82", + 782 => x"f2", + 783 => x"53", + 784 => x"53", + 785 => x"d3", + 786 => x"81", + 787 => x"76", + 788 => x"81", + 789 => x"90", + 790 => x"53", + 791 => x"51", + 792 => x"88", + 793 => x"8d", + 794 => x"74", + 795 => x"38", + 796 => x"05", + 797 => x"3f", + 798 => x"08", + 799 => x"5a", + 800 => x"88", + 801 => x"06", + 802 => x"2e", + 803 => x"86", + 804 => x"82", + 805 => x"80", + 806 => x"86", + 807 => x"39", + 808 => x"53", + 809 => x"51", + 810 => x"81", + 811 => x"81", + 812 => x"3d", + 813 => x"f6", + 814 => x"08", + 815 => x"06", + 816 => x"38", + 817 => x"05", + 818 => x"3f", + 819 => x"02", + 820 => x"78", + 821 => x"88", + 822 => x"70", + 823 => x"5b", + 824 => x"88", + 825 => x"ff", + 826 => x"8c", + 827 => x"3d", + 828 => x"34", + 829 => x"05", + 830 => x"3f", + 831 => x"1a", + 832 => x"e2", + 833 => x"e4", + 834 => x"83", + 835 => x"56", + 836 => x"95", + 837 => x"51", + 838 => x"88", + 839 => x"51", + 840 => x"88", + 841 => x"ff", + 842 => x"31", + 843 => x"1b", + 844 => x"2a", + 845 => x"56", + 846 => x"55", + 847 => x"55", + 848 => x"88", + 849 => x"70", + 850 => x"88", + 851 => x"05", + 852 => x"83", + 853 => x"83", + 854 => x"83", + 855 => x"27", + 856 => x"57", + 857 => x"56", + 858 => x"80", + 859 => x"79", + 860 => x"2e", + 861 => x"90", + 862 => x"fb", + 863 => x"81", + 864 => x"90", + 865 => x"39", + 866 => x"18", + 867 => x"79", + 868 => x"06", + 869 => x"19", + 870 => x"05", + 871 => x"55", + 872 => x"1a", + 873 => x"0b", + 874 => x"0c", + 875 => x"88", + 876 => x"0d", + 877 => x"0d", + 878 => x"9f", + 879 => x"85", + 880 => x"2e", + 881 => x"80", + 882 => x"34", + 883 => x"11", + 884 => x"89", + 885 => x"57", + 886 => x"f8", + 887 => x"08", + 888 => x"80", + 889 => x"3d", + 890 => x"80", + 891 => x"02", + 892 => x"70", + 893 => x"81", + 894 => x"57", + 895 => x"85", + 896 => x"a1", + 897 => x"f5", + 898 => x"08", + 899 => x"98", + 900 => x"51", + 901 => x"88", + 902 => x"0c", + 903 => x"0c", + 904 => x"16", + 905 => x"0c", + 906 => x"04", + 907 => x"7d", + 908 => x"0b", + 909 => x"08", + 910 => x"58", + 911 => x"85", + 912 => x"2e", + 913 => x"81", + 914 => x"06", + 915 => x"74", + 916 => x"c3", + 917 => x"74", + 918 => x"86", + 919 => x"81", + 920 => x"57", + 921 => x"9c", + 922 => x"17", + 923 => x"74", + 924 => x"38", + 925 => x"80", + 926 => x"38", + 927 => x"70", + 928 => x"56", + 929 => x"c7", + 930 => x"33", + 931 => x"89", + 932 => x"81", + 933 => x"55", + 934 => x"76", + 935 => x"16", + 936 => x"39", + 937 => x"51", + 938 => x"88", + 939 => x"75", + 940 => x"38", + 941 => x"0c", + 942 => x"51", + 943 => x"88", + 944 => x"08", + 945 => x"8f", + 946 => x"1a", + 947 => x"98", + 948 => x"ff", + 949 => x"71", + 950 => x"77", + 951 => x"38", + 952 => x"54", + 953 => x"83", + 954 => x"a8", + 955 => x"78", + 956 => x"3f", + 957 => x"e5", + 958 => x"08", + 959 => x"0c", + 960 => x"7b", + 961 => x"0c", + 962 => x"2e", + 963 => x"74", + 964 => x"e2", + 965 => x"76", + 966 => x"3d", + 967 => x"3d", + 968 => x"94", + 969 => x"87", + 970 => x"73", + 971 => x"3f", + 972 => x"2b", + 973 => x"8c", + 974 => x"87", + 975 => x"74", + 976 => x"3f", + 977 => x"07", + 978 => x"8c", + 979 => x"94", + 980 => x"87", + 981 => x"73", + 982 => x"3f", + 983 => x"2b", + 984 => x"9c", + 985 => x"87", + 986 => x"74", + 987 => x"3f", + 988 => x"07", + 989 => x"9c", + 990 => x"83", + 991 => x"94", + 992 => x"80", + 993 => x"c0", + 994 => x"9f", + 995 => x"92", + 996 => x"b8", + 997 => x"51", + 998 => x"88", + 999 => x"a0", + 1000 => x"08", + 1001 => x"88", + 1002 => x"3d", + 1003 => x"84", + 1004 => x"51", + 1005 => x"88", + 1006 => x"75", + 1007 => x"2e", + 1008 => x"15", + 1009 => x"a0", + 1010 => x"04", + 1011 => x"39", + 1012 => x"ff", + 1013 => x"ff", + 1014 => x"00", + 1015 => x"ff", + 1016 => x"4f", + 1017 => x"4e", + 1018 => x"4f", + 1019 => x"00", + 1020 => x"00", + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + 0 => x"0b", + 1 => x"04", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"08", + 10 => x"88", + 11 => x"90", + 12 => x"88", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"fd", + 17 => x"83", + 18 => x"05", + 19 => x"2b", + 20 => x"ff", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"fd", + 25 => x"ff", + 26 => x"06", + 27 => x"82", + 28 => x"2b", + 29 => x"83", + 30 => x"0b", + 31 => x"a5", + 32 => x"09", + 33 => x"05", + 34 => x"06", + 35 => x"09", + 36 => x"0a", + 37 => x"51", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"2e", + 42 => x"04", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"73", + 49 => x"06", + 50 => x"81", + 51 => x"10", + 52 => x"10", + 53 => x"0a", + 54 => x"51", + 55 => x"00", + 56 => x"72", + 57 => x"2e", + 58 => x"04", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"04", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"0a", + 81 => x"53", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"81", + 90 => x"0b", + 91 => x"04", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"9f", + 98 => x"74", + 99 => x"06", + 100 => x"07", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"06", + 106 => x"09", + 107 => x"05", + 108 => x"2b", + 109 => x"06", + 110 => x"04", + 111 => x"00", + 112 => x"09", + 113 => x"05", + 114 => x"05", + 115 => x"81", + 116 => x"04", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"09", + 121 => x"05", + 122 => x"05", + 123 => x"09", + 124 => x"51", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"09", + 129 => x"04", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"09", + 145 => x"73", + 146 => x"53", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"fc", + 153 => x"83", + 154 => x"05", + 155 => x"10", + 156 => x"ff", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"fc", + 161 => x"0b", + 162 => x"73", + 163 => x"10", + 164 => x"0b", + 165 => x"ac", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"08", + 170 => x"0b", + 171 => x"2d", + 172 => x"08", + 173 => x"8c", + 174 => x"51", + 175 => x"00", + 176 => x"08", + 177 => x"08", + 178 => x"0b", + 179 => x"2d", + 180 => x"08", + 181 => x"8c", + 182 => x"51", + 183 => x"00", + 184 => x"09", + 185 => x"09", + 186 => x"06", + 187 => x"54", + 188 => x"09", + 189 => x"ff", + 190 => x"51", + 191 => x"00", + 192 => x"09", + 193 => x"09", + 194 => x"81", + 195 => x"70", + 196 => x"73", + 197 => x"05", + 198 => x"07", + 199 => x"04", + 200 => x"ff", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"81", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"84", + 233 => x"10", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"71", + 250 => x"0d", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"00", + 257 => x"00", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"10", + 266 => x"04", + 267 => x"81", + 268 => x"83", + 269 => x"05", + 270 => x"10", + 271 => x"72", + 272 => x"51", + 273 => x"72", + 274 => x"06", + 275 => x"72", + 276 => x"10", + 277 => x"10", + 278 => x"ed", + 279 => x"53", + 280 => x"f4", + 281 => x"27", + 282 => x"71", + 283 => x"53", + 284 => x"0b", + 285 => x"88", + 286 => x"9d", + 287 => x"04", + 288 => x"04", + 289 => x"94", + 290 => x"0c", + 291 => x"80", + 292 => x"8c", + 293 => x"94", + 294 => x"08", + 295 => x"3f", + 296 => x"88", + 297 => x"3d", + 298 => x"04", + 299 => x"94", + 300 => x"0d", + 301 => x"08", + 302 => x"52", + 303 => x"05", + 304 => x"b9", + 305 => x"70", + 306 => x"85", + 307 => x"0c", + 308 => x"02", + 309 => x"3d", + 310 => x"94", + 311 => x"0c", + 312 => x"05", + 313 => x"ab", + 314 => x"88", + 315 => x"94", + 316 => x"0c", + 317 => x"08", + 318 => x"94", + 319 => x"08", + 320 => x"0b", + 321 => x"05", + 322 => x"f4", + 323 => x"08", + 324 => x"94", + 325 => x"08", + 326 => x"38", + 327 => x"05", + 328 => x"08", + 329 => x"80", + 330 => x"f0", + 331 => x"08", + 332 => x"88", + 333 => x"94", + 334 => x"0c", + 335 => x"05", + 336 => x"fc", + 337 => x"53", + 338 => x"05", + 339 => x"08", + 340 => x"51", + 341 => x"88", + 342 => x"08", + 343 => x"54", + 344 => x"05", + 345 => x"8c", + 346 => x"f8", + 347 => x"94", + 348 => x"0c", + 349 => x"05", + 350 => x"0c", + 351 => x"0d", + 352 => x"94", + 353 => x"0c", + 354 => x"80", + 355 => x"fc", + 356 => x"08", + 357 => x"80", + 358 => x"94", + 359 => x"08", + 360 => x"88", + 361 => x"0b", + 362 => x"05", + 363 => x"8c", + 364 => x"25", + 365 => x"08", + 366 => x"30", + 367 => x"05", + 368 => x"94", + 369 => x"08", + 370 => x"88", + 371 => x"ad", + 372 => x"70", + 373 => x"05", + 374 => x"08", + 375 => x"80", + 376 => x"94", + 377 => x"08", + 378 => x"f8", + 379 => x"08", + 380 => x"70", + 381 => x"87", + 382 => x"0c", + 383 => x"02", + 384 => x"3d", + 385 => x"94", + 386 => x"0c", + 387 => x"08", + 388 => x"94", + 389 => x"08", + 390 => x"05", + 391 => x"38", + 392 => x"05", + 393 => x"a3", + 394 => x"94", + 395 => x"08", + 396 => x"94", + 397 => x"08", + 398 => x"8c", + 399 => x"08", + 400 => x"10", + 401 => x"05", + 402 => x"94", + 403 => x"08", + 404 => x"c9", + 405 => x"8c", + 406 => x"08", + 407 => x"26", + 408 => x"08", + 409 => x"94", + 410 => x"08", + 411 => x"88", + 412 => x"08", + 413 => x"94", + 414 => x"08", + 415 => x"f8", + 416 => x"08", + 417 => x"81", + 418 => x"fc", + 419 => x"08", + 420 => x"81", + 421 => x"8c", + 422 => x"af", + 423 => x"90", + 424 => x"2e", + 425 => x"08", + 426 => x"70", + 427 => x"05", + 428 => x"39", + 429 => x"05", + 430 => x"08", + 431 => x"51", + 432 => x"05", + 433 => x"85", + 434 => x"0c", + 435 => x"0d", + 436 => x"87", + 437 => x"0c", + 438 => x"c0", + 439 => x"85", + 440 => x"98", + 441 => x"c0", + 442 => x"70", + 443 => x"51", + 444 => x"8a", + 445 => x"98", + 446 => x"70", + 447 => x"c0", + 448 => x"fc", + 449 => x"52", + 450 => x"87", + 451 => x"08", + 452 => x"2e", + 453 => x"0b", + 454 => x"f0", + 455 => x"0b", + 456 => x"88", + 457 => x"0d", + 458 => x"0d", + 459 => x"56", + 460 => x"0b", + 461 => x"9f", + 462 => x"06", + 463 => x"52", + 464 => x"09", + 465 => x"9e", + 466 => x"87", + 467 => x"0c", + 468 => x"92", + 469 => x"0b", + 470 => x"8c", + 471 => x"92", + 472 => x"85", + 473 => x"06", + 474 => x"70", + 475 => x"38", + 476 => x"84", + 477 => x"ff", + 478 => x"27", + 479 => x"73", + 480 => x"38", + 481 => x"8b", + 482 => x"70", + 483 => x"34", + 484 => x"81", + 485 => x"a2", + 486 => x"80", + 487 => x"87", + 488 => x"08", + 489 => x"b5", + 490 => x"98", + 491 => x"70", + 492 => x"0b", + 493 => x"8c", + 494 => x"92", + 495 => x"82", + 496 => x"70", + 497 => x"73", + 498 => x"06", + 499 => x"72", + 500 => x"06", + 501 => x"c0", + 502 => x"51", + 503 => x"09", + 504 => x"38", + 505 => x"88", + 506 => x"0d", + 507 => x"0d", + 508 => x"33", + 509 => x"88", + 510 => x"0c", + 511 => x"3d", + 512 => x"3d", + 513 => x"11", + 514 => x"33", + 515 => x"71", + 516 => x"81", + 517 => x"72", + 518 => x"75", + 519 => x"88", + 520 => x"54", + 521 => x"85", + 522 => x"f9", + 523 => x"0b", + 524 => x"f4", + 525 => x"81", + 526 => x"ed", + 527 => x"17", + 528 => x"e5", + 529 => x"55", + 530 => x"89", + 531 => x"2e", + 532 => x"d5", + 533 => x"76", + 534 => x"06", + 535 => x"2a", + 536 => x"05", + 537 => x"70", + 538 => x"bd", + 539 => x"b9", + 540 => x"fe", + 541 => x"08", + 542 => x"06", + 543 => x"84", + 544 => x"2b", + 545 => x"53", + 546 => x"8c", + 547 => x"52", + 548 => x"52", + 549 => x"3f", + 550 => x"38", + 551 => x"e2", + 552 => x"f0", + 553 => x"83", + 554 => x"74", + 555 => x"3d", + 556 => x"3d", + 557 => x"0b", + 558 => x"fe", + 559 => x"08", + 560 => x"56", + 561 => x"74", + 562 => x"38", + 563 => x"75", + 564 => x"16", + 565 => x"53", + 566 => x"87", + 567 => x"fd", + 568 => x"54", + 569 => x"0b", + 570 => x"08", + 571 => x"53", + 572 => x"2e", + 573 => x"8c", + 574 => x"51", + 575 => x"88", + 576 => x"53", + 577 => x"fd", + 578 => x"08", + 579 => x"06", + 580 => x"0c", + 581 => x"04", + 582 => x"76", + 583 => x"9f", + 584 => x"55", + 585 => x"88", + 586 => x"72", + 587 => x"38", + 588 => x"73", + 589 => x"81", + 590 => x"72", + 591 => x"33", + 592 => x"2e", + 593 => x"85", + 594 => x"08", + 595 => x"16", + 596 => x"2e", + 597 => x"51", + 598 => x"88", + 599 => x"39", + 600 => x"52", + 601 => x"0c", + 602 => x"88", + 603 => x"0d", + 604 => x"0d", + 605 => x"0b", + 606 => x"71", + 607 => x"70", + 608 => x"06", + 609 => x"55", + 610 => x"88", + 611 => x"08", + 612 => x"38", + 613 => x"dc", + 614 => x"06", + 615 => x"cf", + 616 => x"90", + 617 => x"15", + 618 => x"8f", + 619 => x"84", + 620 => x"52", + 621 => x"bc", + 622 => x"82", + 623 => x"05", + 624 => x"06", + 625 => x"38", + 626 => x"df", + 627 => x"71", + 628 => x"a0", + 629 => x"88", + 630 => x"08", + 631 => x"88", + 632 => x"0c", + 633 => x"fd", + 634 => x"08", + 635 => x"73", + 636 => x"52", + 637 => x"88", + 638 => x"f2", + 639 => x"62", + 640 => x"5c", + 641 => x"74", + 642 => x"81", + 643 => x"81", + 644 => x"56", + 645 => x"70", + 646 => x"74", + 647 => x"81", + 648 => x"81", + 649 => x"0b", + 650 => x"62", + 651 => x"55", + 652 => x"8f", + 653 => x"fd", + 654 => x"08", + 655 => x"34", + 656 => x"93", + 657 => x"08", + 658 => x"5f", + 659 => x"76", + 660 => x"58", + 661 => x"55", + 662 => x"09", + 663 => x"38", + 664 => x"5b", + 665 => x"5f", + 666 => x"1c", + 667 => x"06", + 668 => x"33", + 669 => x"70", + 670 => x"27", + 671 => x"07", + 672 => x"5b", + 673 => x"55", + 674 => x"38", + 675 => x"09", + 676 => x"38", + 677 => x"7a", + 678 => x"55", + 679 => x"9f", + 680 => x"32", + 681 => x"ae", + 682 => x"70", + 683 => x"2a", + 684 => x"51", + 685 => x"38", + 686 => x"5a", + 687 => x"77", + 688 => x"81", + 689 => x"1c", + 690 => x"55", + 691 => x"ff", + 692 => x"1e", + 693 => x"55", + 694 => x"83", + 695 => x"74", + 696 => x"7b", + 697 => x"3f", + 698 => x"ef", + 699 => x"7b", + 700 => x"2b", + 701 => x"54", + 702 => x"08", + 703 => x"f8", + 704 => x"08", + 705 => x"80", + 706 => x"33", + 707 => x"2e", + 708 => x"8b", + 709 => x"83", + 710 => x"06", + 711 => x"74", + 712 => x"7d", + 713 => x"88", + 714 => x"5b", + 715 => x"58", + 716 => x"9a", + 717 => x"81", + 718 => x"79", + 719 => x"5b", + 720 => x"31", + 721 => x"75", + 722 => x"38", + 723 => x"80", + 724 => x"7b", + 725 => x"3f", + 726 => x"88", + 727 => x"08", + 728 => x"39", + 729 => x"1c", + 730 => x"33", + 731 => x"a5", + 732 => x"33", + 733 => x"70", + 734 => x"56", + 735 => x"38", + 736 => x"39", + 737 => x"39", + 738 => x"d3", + 739 => x"88", + 740 => x"af", + 741 => x"0c", + 742 => x"04", + 743 => x"79", + 744 => x"82", + 745 => x"53", + 746 => x"51", + 747 => x"83", + 748 => x"80", + 749 => x"51", + 750 => x"88", + 751 => x"ff", + 752 => x"56", + 753 => x"d5", + 754 => x"06", + 755 => x"75", + 756 => x"77", + 757 => x"f6", + 758 => x"08", + 759 => x"94", + 760 => x"f8", + 761 => x"08", + 762 => x"06", + 763 => x"82", + 764 => x"38", + 765 => x"d2", + 766 => x"76", + 767 => x"3f", + 768 => x"88", + 769 => x"76", + 770 => x"3f", + 771 => x"ff", + 772 => x"74", + 773 => x"2e", + 774 => x"56", + 775 => x"89", + 776 => x"ed", + 777 => x"59", + 778 => x"0b", + 779 => x"0c", + 780 => x"88", + 781 => x"55", + 782 => x"82", + 783 => x"75", + 784 => x"70", + 785 => x"fe", + 786 => x"08", + 787 => x"57", + 788 => x"09", + 789 => x"38", + 790 => x"be", + 791 => x"75", + 792 => x"3f", + 793 => x"38", + 794 => x"55", + 795 => x"ac", + 796 => x"e4", + 797 => x"8a", + 798 => x"88", + 799 => x"52", + 800 => x"3f", + 801 => x"ff", + 802 => x"83", + 803 => x"06", + 804 => x"56", + 805 => x"76", + 806 => x"38", + 807 => x"8f", + 808 => x"8d", + 809 => x"75", + 810 => x"3f", + 811 => x"08", + 812 => x"95", + 813 => x"51", + 814 => x"88", + 815 => x"ff", + 816 => x"8c", + 817 => x"f3", + 818 => x"b6", + 819 => x"58", + 820 => x"33", + 821 => x"02", + 822 => x"05", + 823 => x"59", + 824 => x"3f", + 825 => x"ff", + 826 => x"05", + 827 => x"8c", + 828 => x"1a", + 829 => x"e0", + 830 => x"f1", + 831 => x"84", + 832 => x"3d", + 833 => x"f5", + 834 => x"08", + 835 => x"06", + 836 => x"38", + 837 => x"05", + 838 => x"3f", + 839 => x"7a", + 840 => x"3f", + 841 => x"ff", + 842 => x"71", + 843 => x"84", + 844 => x"84", + 845 => x"33", + 846 => x"31", + 847 => x"51", + 848 => x"3f", + 849 => x"05", + 850 => x"0c", + 851 => x"8a", + 852 => x"74", + 853 => x"26", + 854 => x"57", + 855 => x"76", + 856 => x"83", + 857 => x"86", + 858 => x"2e", + 859 => x"76", + 860 => x"83", + 861 => x"06", + 862 => x"3d", + 863 => x"f5", + 864 => x"08", + 865 => x"88", + 866 => x"08", + 867 => x"0c", + 868 => x"ff", + 869 => x"08", + 870 => x"2a", + 871 => x"0c", + 872 => x"81", + 873 => x"0b", + 874 => x"f4", + 875 => x"75", + 876 => x"3d", + 877 => x"3d", + 878 => x"0b", + 879 => x"55", + 880 => x"80", + 881 => x"38", + 882 => x"16", + 883 => x"e0", + 884 => x"54", + 885 => x"54", + 886 => x"51", + 887 => x"88", + 888 => x"08", + 889 => x"88", + 890 => x"73", + 891 => x"38", + 892 => x"33", + 893 => x"70", + 894 => x"55", + 895 => x"2e", + 896 => x"54", + 897 => x"51", + 898 => x"88", + 899 => x"0c", + 900 => x"05", + 901 => x"3f", + 902 => x"16", + 903 => x"16", + 904 => x"81", + 905 => x"88", + 906 => x"0d", + 907 => x"0d", + 908 => x"0b", + 909 => x"f4", + 910 => x"5c", + 911 => x"0c", + 912 => x"80", + 913 => x"38", + 914 => x"81", + 915 => x"57", + 916 => x"81", + 917 => x"39", + 918 => x"34", + 919 => x"0b", + 920 => x"81", + 921 => x"39", + 922 => x"98", + 923 => x"55", + 924 => x"83", + 925 => x"77", + 926 => x"9a", + 927 => x"08", + 928 => x"06", + 929 => x"80", + 930 => x"16", + 931 => x"77", + 932 => x"70", + 933 => x"5b", + 934 => x"38", + 935 => x"a0", + 936 => x"8b", + 937 => x"08", + 938 => x"3f", + 939 => x"81", + 940 => x"aa", + 941 => x"17", + 942 => x"08", + 943 => x"3f", + 944 => x"88", + 945 => x"ff", + 946 => x"08", + 947 => x"0c", + 948 => x"83", + 949 => x"80", + 950 => x"55", + 951 => x"83", + 952 => x"74", + 953 => x"08", + 954 => x"53", + 955 => x"52", + 956 => x"b5", + 957 => x"fe", + 958 => x"16", + 959 => x"17", + 960 => x"31", + 961 => x"7c", + 962 => x"80", + 963 => x"38", + 964 => x"fe", + 965 => x"57", + 966 => x"8c", + 967 => x"fb", + 968 => x"c0", + 969 => x"54", + 970 => x"52", + 971 => x"d7", + 972 => x"90", + 973 => x"94", + 974 => x"54", + 975 => x"52", + 976 => x"c3", + 977 => x"08", + 978 => x"94", + 979 => x"c0", + 980 => x"54", + 981 => x"52", + 982 => x"ab", + 983 => x"90", + 984 => x"94", + 985 => x"54", + 986 => x"52", + 987 => x"97", + 988 => x"08", + 989 => x"94", + 990 => x"80", + 991 => x"c0", + 992 => x"8c", + 993 => x"87", + 994 => x"0c", + 995 => x"f9", + 996 => x"08", + 997 => x"e0", + 998 => x"3f", + 999 => x"38", + 1000 => x"88", + 1001 => x"98", + 1002 => x"87", + 1003 => x"53", + 1004 => x"74", + 1005 => x"3f", + 1006 => x"38", + 1007 => x"80", + 1008 => x"73", + 1009 => x"39", + 1010 => x"73", + 1011 => x"fb", + 1012 => x"ff", + 1013 => x"00", + 1014 => x"ff", + 1015 => x"ff", + 1016 => x"4f", + 1017 => x"49", + 1018 => x"52", + 1019 => x"00", + 1020 => x"00", + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + 0 => x"0b", + 1 => x"e0", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"88", + 9 => x"90", + 10 => x"0b", + 11 => x"2d", + 12 => x"0c", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"71", + 17 => x"72", + 18 => x"81", + 19 => x"83", + 20 => x"ff", + 21 => x"04", + 22 => x"00", + 23 => x"00", + 24 => x"71", + 25 => x"83", + 26 => x"83", + 27 => x"05", + 28 => x"2b", + 29 => x"73", + 30 => x"0b", + 31 => x"83", + 32 => x"72", + 33 => x"72", + 34 => x"09", + 35 => x"73", + 36 => x"07", + 37 => x"53", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"73", + 42 => x"51", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"71", + 50 => x"09", + 51 => x"0a", + 52 => x"0a", + 53 => x"05", + 54 => x"51", + 55 => x"04", + 56 => x"72", + 57 => x"73", + 58 => x"51", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"c4", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"0a", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"09", + 90 => x"0b", + 91 => x"05", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"73", + 98 => x"09", + 99 => x"81", + 100 => x"06", + 101 => x"04", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"04", + 106 => x"06", + 107 => x"82", + 108 => x"0b", + 109 => x"fc", + 110 => x"51", + 111 => x"00", + 112 => x"72", + 113 => x"72", + 114 => x"81", + 115 => x"0a", + 116 => x"51", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"72", + 121 => x"72", + 122 => x"81", + 123 => x"0a", + 124 => x"53", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"71", + 129 => x"52", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"04", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"73", + 146 => x"07", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"71", + 153 => x"72", + 154 => x"81", + 155 => x"10", + 156 => x"81", + 157 => x"04", + 158 => x"00", + 159 => x"00", + 160 => x"71", + 161 => x"0b", + 162 => x"d0", + 163 => x"10", + 164 => x"06", + 165 => x"88", + 166 => x"00", + 167 => x"00", + 168 => x"88", + 169 => x"90", + 170 => x"0b", + 171 => x"cf", + 172 => x"88", + 173 => x"0c", + 174 => x"0c", + 175 => x"00", + 176 => x"88", + 177 => x"90", + 178 => x"0b", + 179 => x"81", + 180 => x"88", + 181 => x"0c", + 182 => x"0c", + 183 => x"00", + 184 => x"72", + 185 => x"05", + 186 => x"81", + 187 => x"70", + 188 => x"73", + 189 => x"05", + 190 => x"07", + 191 => x"04", + 192 => x"72", + 193 => x"05", + 194 => x"09", + 195 => x"05", + 196 => x"06", + 197 => x"74", + 198 => x"06", + 199 => x"51", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"04", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"71", + 217 => x"04", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"04", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"02", + 233 => x"10", + 234 => x"04", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"05", + 250 => x"02", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"00", + 257 => x"04", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"10", + 266 => x"51", + 267 => x"73", + 268 => x"73", + 269 => x"81", + 270 => x"10", + 271 => x"07", + 272 => x"0c", + 273 => x"72", + 274 => x"81", + 275 => x"09", + 276 => x"71", + 277 => x"0a", + 278 => x"72", + 279 => x"51", + 280 => x"9f", + 281 => x"a4", + 282 => x"80", + 283 => x"05", + 284 => x"0b", + 285 => x"04", + 286 => x"9e", + 287 => x"80", + 288 => x"fe", + 289 => x"00", + 290 => x"94", + 291 => x"0d", + 292 => x"08", + 293 => x"52", + 294 => x"05", + 295 => x"de", + 296 => x"70", + 297 => x"85", + 298 => x"0c", + 299 => x"02", + 300 => x"3d", + 301 => x"94", + 302 => x"08", + 303 => x"88", + 304 => x"82", + 305 => x"08", + 306 => x"54", + 307 => x"94", + 308 => x"08", + 309 => x"f9", + 310 => x"0b", + 311 => x"05", + 312 => x"88", + 313 => x"25", + 314 => x"08", + 315 => x"30", + 316 => x"05", + 317 => x"94", + 318 => x"0c", + 319 => x"05", + 320 => x"81", + 321 => x"f4", + 322 => x"08", + 323 => x"94", + 324 => x"0c", + 325 => x"05", + 326 => x"ab", + 327 => x"8c", + 328 => x"94", + 329 => x"0c", + 330 => x"08", + 331 => x"94", + 332 => x"08", + 333 => x"0b", + 334 => x"05", + 335 => x"f0", + 336 => x"08", + 337 => x"80", + 338 => x"8c", + 339 => x"94", + 340 => x"08", + 341 => x"3f", + 342 => x"94", + 343 => x"0c", + 344 => x"fc", + 345 => x"2e", + 346 => x"08", + 347 => x"30", + 348 => x"05", + 349 => x"f8", + 350 => x"88", + 351 => x"3d", + 352 => x"04", + 353 => x"94", + 354 => x"0d", + 355 => x"08", + 356 => x"94", + 357 => x"08", + 358 => x"38", + 359 => x"05", + 360 => x"08", + 361 => x"81", + 362 => x"fc", + 363 => x"08", + 364 => x"80", + 365 => x"94", + 366 => x"08", + 367 => x"8c", + 368 => x"53", + 369 => x"05", + 370 => x"08", + 371 => x"51", + 372 => x"08", + 373 => x"f8", + 374 => x"94", + 375 => x"08", + 376 => x"38", + 377 => x"05", + 378 => x"08", + 379 => x"94", + 380 => x"08", + 381 => x"54", + 382 => x"94", + 383 => x"08", + 384 => x"fd", + 385 => x"0b", + 386 => x"05", + 387 => x"94", + 388 => x"0c", + 389 => x"05", + 390 => x"88", + 391 => x"ac", + 392 => x"fc", + 393 => x"2e", + 394 => x"0b", + 395 => x"05", + 396 => x"38", + 397 => x"05", + 398 => x"08", + 399 => x"94", + 400 => x"08", + 401 => x"fc", + 402 => x"39", + 403 => x"05", + 404 => x"80", + 405 => x"08", + 406 => x"94", + 407 => x"08", + 408 => x"94", + 409 => x"08", + 410 => x"05", + 411 => x"08", + 412 => x"94", + 413 => x"08", + 414 => x"05", + 415 => x"08", + 416 => x"94", + 417 => x"08", + 418 => x"08", + 419 => x"94", + 420 => x"08", + 421 => x"08", + 422 => x"ff", + 423 => x"08", + 424 => x"80", + 425 => x"94", + 426 => x"08", + 427 => x"f4", + 428 => x"8d", + 429 => x"f8", + 430 => x"94", + 431 => x"0c", + 432 => x"f4", + 433 => x"0c", + 434 => x"94", + 435 => x"3d", + 436 => x"0b", + 437 => x"8c", + 438 => x"87", + 439 => x"0c", + 440 => x"c0", + 441 => x"87", + 442 => x"08", + 443 => x"51", + 444 => x"2e", + 445 => x"c0", + 446 => x"51", + 447 => x"87", + 448 => x"08", + 449 => x"06", + 450 => x"38", + 451 => x"8c", + 452 => x"80", + 453 => x"71", + 454 => x"9f", + 455 => x"0b", + 456 => x"33", + 457 => x"3d", + 458 => x"3d", + 459 => x"7d", + 460 => x"80", + 461 => x"0b", + 462 => x"81", + 463 => x"82", + 464 => x"2e", + 465 => x"81", + 466 => x"0b", + 467 => x"8c", + 468 => x"c0", + 469 => x"84", + 470 => x"92", + 471 => x"c0", + 472 => x"70", + 473 => x"81", + 474 => x"53", + 475 => x"a7", + 476 => x"92", + 477 => x"81", + 478 => x"79", + 479 => x"51", + 480 => x"90", + 481 => x"2e", + 482 => x"76", + 483 => x"58", + 484 => x"54", + 485 => x"72", + 486 => x"70", + 487 => x"38", + 488 => x"8c", + 489 => x"ff", + 490 => x"c0", + 491 => x"51", + 492 => x"81", + 493 => x"92", + 494 => x"c0", + 495 => x"70", + 496 => x"51", + 497 => x"80", + 498 => x"80", + 499 => x"70", + 500 => x"81", + 501 => x"87", + 502 => x"08", + 503 => x"2e", + 504 => x"83", + 505 => x"71", + 506 => x"3d", + 507 => x"3d", + 508 => x"11", + 509 => x"71", + 510 => x"88", + 511 => x"84", + 512 => x"fd", + 513 => x"83", + 514 => x"12", + 515 => x"2b", + 516 => x"07", + 517 => x"70", + 518 => x"2b", + 519 => x"07", + 520 => x"53", + 521 => x"52", + 522 => x"04", + 523 => x"79", + 524 => x"9f", + 525 => x"57", + 526 => x"80", + 527 => x"88", + 528 => x"80", + 529 => x"33", + 530 => x"2e", + 531 => x"83", + 532 => x"80", + 533 => x"54", + 534 => x"fe", + 535 => x"88", + 536 => x"08", + 537 => x"3d", + 538 => x"fd", + 539 => x"08", + 540 => x"51", + 541 => x"88", + 542 => x"ff", + 543 => x"39", + 544 => x"82", + 545 => x"06", + 546 => x"2a", + 547 => x"05", + 548 => x"70", + 549 => x"92", + 550 => x"8e", + 551 => x"fe", + 552 => x"08", + 553 => x"55", + 554 => x"55", + 555 => x"89", + 556 => x"fb", + 557 => x"0b", + 558 => x"08", + 559 => x"12", + 560 => x"55", + 561 => x"56", + 562 => x"8d", + 563 => x"33", + 564 => x"94", + 565 => x"57", + 566 => x"0c", + 567 => x"04", + 568 => x"75", + 569 => x"0b", + 570 => x"f4", + 571 => x"51", + 572 => x"83", + 573 => x"06", + 574 => x"14", + 575 => x"3f", + 576 => x"2b", + 577 => x"51", + 578 => x"88", + 579 => x"ff", + 580 => x"88", + 581 => x"0d", + 582 => x"0d", + 583 => x"0b", + 584 => x"55", + 585 => x"23", + 586 => x"53", + 587 => x"88", + 588 => x"08", + 589 => x"38", + 590 => x"39", + 591 => x"73", + 592 => x"83", + 593 => x"06", + 594 => x"14", + 595 => x"8c", + 596 => x"80", + 597 => x"72", + 598 => x"3f", + 599 => x"85", + 600 => x"08", + 601 => x"16", + 602 => x"71", + 603 => x"3d", + 604 => x"3d", + 605 => x"0b", + 606 => x"08", + 607 => x"05", + 608 => x"ff", + 609 => x"57", + 610 => x"2e", + 611 => x"15", + 612 => x"86", + 613 => x"80", + 614 => x"8f", + 615 => x"80", + 616 => x"13", + 617 => x"8c", + 618 => x"72", + 619 => x"0b", + 620 => x"57", + 621 => x"27", + 622 => x"39", + 623 => x"ff", + 624 => x"2a", + 625 => x"a8", + 626 => x"fc", + 627 => x"52", + 628 => x"27", + 629 => x"52", + 630 => x"17", + 631 => x"38", + 632 => x"16", + 633 => x"51", + 634 => x"88", + 635 => x"0c", + 636 => x"80", + 637 => x"0c", + 638 => x"04", + 639 => x"60", + 640 => x"5e", + 641 => x"55", + 642 => x"09", + 643 => x"38", + 644 => x"44", + 645 => x"62", + 646 => x"56", + 647 => x"09", + 648 => x"38", + 649 => x"80", + 650 => x"0c", + 651 => x"51", + 652 => x"26", + 653 => x"51", + 654 => x"88", + 655 => x"7d", + 656 => x"39", + 657 => x"1d", + 658 => x"5a", + 659 => x"a0", + 660 => x"05", + 661 => x"15", + 662 => x"2e", + 663 => x"ef", + 664 => x"59", + 665 => x"08", + 666 => x"81", + 667 => x"ff", + 668 => x"70", + 669 => x"32", + 670 => x"73", + 671 => x"25", + 672 => x"52", + 673 => x"57", + 674 => x"c7", + 675 => x"2e", + 676 => x"83", + 677 => x"77", + 678 => x"07", + 679 => x"2e", + 680 => x"88", + 681 => x"78", + 682 => x"30", + 683 => x"9f", + 684 => x"57", + 685 => x"9b", + 686 => x"8b", + 687 => x"39", + 688 => x"70", + 689 => x"72", + 690 => x"57", + 691 => x"34", + 692 => x"7a", + 693 => x"80", + 694 => x"26", + 695 => x"55", + 696 => x"34", + 697 => x"b1", + 698 => x"80", + 699 => x"54", + 700 => x"85", + 701 => x"06", + 702 => x"1c", + 703 => x"51", + 704 => x"88", + 705 => x"08", + 706 => x"7c", + 707 => x"80", + 708 => x"38", + 709 => x"70", + 710 => x"81", + 711 => x"56", + 712 => x"8b", + 713 => x"08", + 714 => x"5b", + 715 => x"18", + 716 => x"2e", + 717 => x"70", + 718 => x"33", + 719 => x"05", + 720 => x"71", + 721 => x"56", + 722 => x"e2", + 723 => x"75", + 724 => x"38", + 725 => x"9a", + 726 => x"39", + 727 => x"88", + 728 => x"83", + 729 => x"84", + 730 => x"11", + 731 => x"74", + 732 => x"1d", + 733 => x"2a", + 734 => x"51", + 735 => x"89", + 736 => x"92", + 737 => x"8e", + 738 => x"fa", + 739 => x"08", + 740 => x"fd", + 741 => x"88", + 742 => x"0d", + 743 => x"0d", + 744 => x"57", + 745 => x"fe", + 746 => x"76", + 747 => x"3f", + 748 => x"08", + 749 => x"76", + 750 => x"3f", + 751 => x"ff", + 752 => x"82", + 753 => x"d4", + 754 => x"81", + 755 => x"38", + 756 => x"53", + 757 => x"51", + 758 => x"88", + 759 => x"08", + 760 => x"51", + 761 => x"88", + 762 => x"ff", + 763 => x"81", + 764 => x"a9", + 765 => x"80", + 766 => x"52", + 767 => x"aa", + 768 => x"56", + 769 => x"38", + 770 => x"e2", + 771 => x"83", + 772 => x"55", + 773 => x"c6", + 774 => x"81", + 775 => x"0c", + 776 => x"04", + 777 => x"65", + 778 => x"0b", + 779 => x"f4", + 780 => x"3f", + 781 => x"06", + 782 => x"74", + 783 => x"74", + 784 => x"3d", + 785 => x"5a", + 786 => x"88", + 787 => x"06", + 788 => x"2e", + 789 => x"b3", + 790 => x"83", + 791 => x"52", + 792 => x"c6", + 793 => x"ab", + 794 => x"33", + 795 => x"2e", + 796 => x"3d", + 797 => x"f7", + 798 => x"08", + 799 => x"76", + 800 => x"99", + 801 => x"81", + 802 => x"76", + 803 => x"81", + 804 => x"81", + 805 => x"39", + 806 => x"86", + 807 => x"82", + 808 => x"54", + 809 => x"52", + 810 => x"fe", + 811 => x"88", + 812 => x"38", + 813 => x"05", + 814 => x"3f", + 815 => x"ff", + 816 => x"77", + 817 => x"3d", + 818 => x"f6", + 819 => x"08", + 820 => x"05", + 821 => x"29", + 822 => x"ad", + 823 => x"52", + 824 => x"8a", + 825 => x"83", + 826 => x"7a", + 827 => x"0c", + 828 => x"82", + 829 => x"3d", + 830 => x"f5", + 831 => x"08", + 832 => x"95", + 833 => x"51", + 834 => x"88", + 835 => x"ff", + 836 => x"8c", + 837 => x"ef", + 838 => x"e7", + 839 => x"56", + 840 => x"ca", + 841 => x"83", + 842 => x"76", + 843 => x"31", + 844 => x"70", + 845 => x"1d", + 846 => x"71", + 847 => x"5c", + 848 => x"c4", + 849 => x"82", + 850 => x"1b", + 851 => x"e0", + 852 => x"56", + 853 => x"fe", + 854 => x"82", + 855 => x"f6", + 856 => x"38", + 857 => x"39", + 858 => x"80", + 859 => x"38", + 860 => x"76", + 861 => x"81", + 862 => x"95", + 863 => x"51", + 864 => x"88", + 865 => x"0c", + 866 => x"19", + 867 => x"1a", + 868 => x"ff", + 869 => x"1a", + 870 => x"84", + 871 => x"1b", + 872 => x"0b", + 873 => x"78", + 874 => x"9f", + 875 => x"56", + 876 => x"95", + 877 => x"ea", + 878 => x"0b", + 879 => x"08", + 880 => x"74", + 881 => x"df", + 882 => x"81", + 883 => x"3d", + 884 => x"69", + 885 => x"70", + 886 => x"05", + 887 => x"3f", + 888 => x"88", + 889 => x"38", + 890 => x"54", + 891 => x"93", + 892 => x"05", + 893 => x"2a", + 894 => x"51", + 895 => x"80", + 896 => x"83", + 897 => x"75", + 898 => x"3f", + 899 => x"16", + 900 => x"dc", + 901 => x"eb", + 902 => x"9c", + 903 => x"98", + 904 => x"0b", + 905 => x"73", + 906 => x"3d", + 907 => x"3d", + 908 => x"7e", + 909 => x"9f", + 910 => x"5b", + 911 => x"7b", + 912 => x"75", + 913 => x"d1", + 914 => x"33", + 915 => x"84", + 916 => x"2e", + 917 => x"91", + 918 => x"17", + 919 => x"80", + 920 => x"34", + 921 => x"b1", + 922 => x"08", + 923 => x"31", + 924 => x"27", + 925 => x"58", + 926 => x"81", + 927 => x"16", + 928 => x"ff", + 929 => x"74", + 930 => x"82", + 931 => x"05", + 932 => x"06", + 933 => x"06", + 934 => x"9e", + 935 => x"38", + 936 => x"55", + 937 => x"16", + 938 => x"80", + 939 => x"55", + 940 => x"ff", + 941 => x"a4", + 942 => x"16", + 943 => x"f3", + 944 => x"55", + 945 => x"2e", + 946 => x"88", + 947 => x"17", + 948 => x"08", + 949 => x"84", + 950 => x"51", + 951 => x"27", + 952 => x"55", + 953 => x"16", + 954 => x"06", + 955 => x"08", + 956 => x"f0", + 957 => x"08", + 958 => x"98", + 959 => x"98", + 960 => x"75", + 961 => x"16", + 962 => x"78", + 963 => x"e8", + 964 => x"59", + 965 => x"80", + 966 => x"0c", + 967 => x"04", + 968 => x"87", + 969 => x"08", + 970 => x"80", + 971 => x"ea", + 972 => x"08", + 973 => x"c0", + 974 => x"56", + 975 => x"80", + 976 => x"ea", + 977 => x"88", + 978 => x"c0", + 979 => x"87", + 980 => x"08", + 981 => x"80", + 982 => x"ea", + 983 => x"08", + 984 => x"c0", + 985 => x"56", + 986 => x"80", + 987 => x"ea", + 988 => x"88", + 989 => x"c0", + 990 => x"8c", + 991 => x"87", + 992 => x"0c", + 993 => x"0b", + 994 => x"94", + 995 => x"51", + 996 => x"88", + 997 => x"9f", + 998 => x"9b", + 999 => x"ae", + 1000 => x"0b", + 1001 => x"c0", + 1002 => x"55", + 1003 => x"05", + 1004 => x"52", + 1005 => x"f6", + 1006 => x"8d", + 1007 => x"73", + 1008 => x"38", + 1009 => x"e4", + 1010 => x"54", + 1011 => x"54", + 1012 => x"00", + 1013 => x"ff", + 1014 => x"ff", + 1015 => x"ff", + 1016 => x"42", + 1017 => x"54", + 1018 => x"2e", + 1019 => x"00", + 1020 => x"01", + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; +end arch; diff --git a/zpu/devices/sysbus/BRAM/IOCP_ZPUTA_BootROM.vhd b/zpu/devices/sysbus/BRAM/IOCP_ZPUTA_BootROM.vhd new file mode 100644 index 0000000..712ed90 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/IOCP_ZPUTA_BootROM.vhd @@ -0,0 +1,8240 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com +-- Modified by Philip Smart 02/2019 for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity BootROM is +port ( + clk : in std_logic; + areset : in std_logic := '0'; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + memBRead : out std_logic_vector(WORD_32BIT_RANGE) +); +end BootROM; + +architecture arch of BootROM is + +type ram_type is array(natural range 0 to (2**(SOC_MAX_ADDR_BRAM_BIT-2))-1) of std_logic_vector(WORD_32BIT_RANGE); + +shared variable ram : ram_type := +( + 0 => x"0b0b0b88", + 1 => x"e9040000", + 2 => x"00000000", + 3 => x"00000000", + 4 => x"00000000", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"88088c08", + 9 => x"90080b0b", + 10 => x"0b888008", + 11 => x"2d900c8c", + 12 => x"0c880c04", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a50400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"09810572", + 51 => x"0a100a72", + 52 => x"0a100a31", + 53 => x"050a8106", + 54 => x"51515351", + 55 => x"04000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b88", + 73 => x"c4040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b88a7", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"04067383", + 106 => x"06098105", + 107 => x"8205832b", + 108 => x"0b2b0772", + 109 => x"fc060c51", + 110 => x"51040000", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b0b9f", + 162 => x"cc738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"88ac0400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"88088c08", + 169 => x"90087575", + 170 => x"0b0b0b89", + 171 => x"cb2d5050", + 172 => x"88085690", + 173 => x"0c8c0c88", + 174 => x"0c510400", + 175 => x"00000000", + 176 => x"88088c08", + 177 => x"90087575", + 178 => x"0b0b0b8a", + 179 => x"fd2d5050", + 180 => x"88085690", + 181 => x"0c8c0c88", + 182 => x"0c510400", + 183 => x"00000000", + 184 => x"72097081", + 185 => x"0509060a", + 186 => x"8106ff05", + 187 => x"70547106", + 188 => x"73097274", + 189 => x"05ff0506", + 190 => x"07515151", + 191 => x"04000000", + 192 => x"72097081", + 193 => x"0509060a", + 194 => x"098106ff", + 195 => x"05705471", + 196 => x"06730972", + 197 => x"7405ff05", + 198 => x"06075151", + 199 => x"51040000", + 200 => x"05ff0504", + 201 => x"00000000", + 202 => x"00000000", + 203 => x"00000000", + 204 => x"00000000", + 205 => x"00000000", + 206 => x"00000000", + 207 => x"00000000", + 208 => x"04000000", + 209 => x"00000000", + 210 => x"00000000", + 211 => x"00000000", + 212 => x"00000000", + 213 => x"00000000", + 214 => x"00000000", + 215 => x"00000000", + 216 => x"71810552", + 217 => x"04000000", + 218 => x"00000000", + 219 => x"00000000", + 220 => x"00000000", + 221 => x"00000000", + 222 => x"00000000", + 223 => x"00000000", + 224 => x"04000000", + 225 => x"00000000", + 226 => x"00000000", + 227 => x"00000000", + 228 => x"00000000", + 229 => x"00000000", + 230 => x"00000000", + 231 => x"00000000", + 232 => x"02840572", + 233 => x"10100552", + 234 => x"04000000", + 235 => x"00000000", + 236 => x"00000000", + 237 => x"00000000", + 238 => x"00000000", + 239 => x"00000000", + 240 => x"00000000", + 241 => x"00000000", + 242 => x"00000000", + 243 => x"00000000", + 244 => x"00000000", + 245 => x"00000000", + 246 => x"00000000", + 247 => x"00000000", + 248 => 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x"7c0d0a00", + 8836 => x"72656164", + 8837 => x"00000000", + 8838 => x"5a505554", + 8839 => x"41000000", + 8840 => x"0a2a2a20", + 8841 => x"25732028", + 8842 => x"00000000", + 8843 => x"32392f31", + 8844 => x"322f3230", + 8845 => x"31390000", + 8846 => x"76312e34", + 8847 => x"00000000", + 8848 => x"205a5055", + 8849 => x"2c207265", + 8850 => x"76202530", + 8851 => x"32782920", + 8852 => x"25732025", + 8853 => x"73202a2a", + 8854 => x"0a0a0000", + 8855 => x"5a505554", + 8856 => x"4120496e", + 8857 => x"74657272", + 8858 => x"75707420", + 8859 => x"48616e64", + 8860 => x"6c65720a", + 8861 => x"00000000", + 8862 => x"54696d65", + 8863 => x"7220696e", + 8864 => x"74657272", + 8865 => x"7570740a", + 8866 => x"00000000", + 8867 => x"50533220", + 8868 => x"696e7465", + 8869 => x"72727570", + 8870 => x"740a0000", + 8871 => x"494f4354", + 8872 => x"4c205244", + 8873 => x"20696e74", + 8874 => x"65727275", + 8875 => x"70740a00", + 8876 => x"494f4354", + 8877 => x"4c205752", + 8878 => x"20696e74", + 8879 => x"65727275", + 8880 => x"70740a00", + 8881 => x"55415254", + 8882 => x"30205258", + 8883 => x"20696e74", + 8884 => x"65727275", + 8885 => x"70740a00", + 8886 => x"55415254", + 8887 => x"30205458", + 8888 => x"20696e74", + 8889 => x"65727275", + 8890 => x"70740a00", + 8891 => x"55415254", + 8892 => x"31205258", + 8893 => x"20696e74", + 8894 => x"65727275", + 8895 => x"70740a00", + 8896 => x"55415254", + 8897 => x"31205458", + 8898 => x"20696e74", + 8899 => x"65727275", + 8900 => x"70740a00", + 8901 => x"53657474", + 8902 => x"696e6720", + 8903 => x"75702074", + 8904 => x"696d6572", + 8905 => x"2e2e2e0a", + 8906 => x"00000000", + 8907 => x"456e6162", + 8908 => x"6c696e67", + 8909 => x"2074696d", + 8910 => x"65722e2e", + 8911 => x"2e0a0000", + 8912 => x"6175746f", + 8913 => x"65786563", + 8914 => x"2e626174", + 8915 => x"00000000", + 8916 => x"303a0000", + 8917 => x"4661696c", + 8918 => x"65642074", + 8919 => x"6f20696e", + 8920 => x"69746961", + 8921 => x"6c697365", + 8922 => x"20736420", + 8923 => x"63617264", + 8924 => x"20302c20", + 8925 => x"706c6561", + 8926 => x"73652069", + 8927 => x"6e697420", + 8928 => x"6d616e75", + 8929 => x"616c6c79", + 8930 => x"2e0a0000", + 8931 => x"2a200000", + 8932 => x"42616420", + 8933 => x"6469736b", + 8934 => x"20696421", + 8935 => x"0a000000", + 8936 => x"496e6974", + 8937 => x"69616c69", + 8938 => x"7365642e", + 8939 => x"0a000000", + 8940 => x"4661696c", + 8941 => x"65642074", + 8942 => x"6f20696e", + 8943 => x"69746961", + 8944 => x"6c697365", + 8945 => x"2e0a0000", + 8946 => x"72633d25", + 8947 => x"640a0000", + 8948 => x"25753a00", + 8949 => x"436c6561", + 8950 => x"72696e67", + 8951 => x"2e2e2e2e", + 8952 => x"00000000", + 8953 => x"44756d70", + 8954 => x"204d656d", + 8955 => x"6f72790a", + 8956 => x"00000000", + 8957 => x"0a436f6d", + 8958 => x"706c6574", + 8959 => x"652e0a00", + 8960 => x"25303858", + 8961 => x"20253032", + 8962 => x"582d0000", + 8963 => x"3f3f3f0a", + 8964 => x"00000000", + 8965 => x"25303858", + 8966 => x"20253034", + 8967 => x"582d0000", + 8968 => x"25303858", + 8969 => x"20253038", + 8970 => x"582d0000", + 8971 => x"53656172", + 8972 => x"6368696e", + 8973 => x"672e2e0a", + 8974 => x"00000000", + 8975 => x"2530386c", + 8976 => x"782d3e25", + 8977 => x"30386c78", + 8978 => x"0a000000", + 8979 => x"44697361", + 8980 => x"626c696e", + 8981 => x"6720696e", + 8982 => x"74657272", + 8983 => x"75707473", + 8984 => x"0a000000", + 8985 => x"456e6162", + 8986 => x"6c696e67", + 8987 => x"20696e74", + 8988 => x"65727275", + 8989 => x"7074730a", + 8990 => x"00000000", + 8991 => x"44697361", + 8992 => x"626c6564", + 8993 => x"20756172", + 8994 => x"74206669", + 8995 => x"666f0a00", + 8996 => x"456e6162", + 8997 => x"6c696e67", + 8998 => x"20756172", + 8999 => x"74206669", + 9000 => x"666f0a00", + 9001 => x"45786563", + 9002 => x"7574696e", + 9003 => x"6720636f", + 9004 => x"64652040", + 9005 => x"20253038", + 9006 => x"78202e2e", + 9007 => x"2e0a0000", + 9008 => x"43616c6c", + 9009 => x"696e6720", + 9010 => x"636f6465", + 9011 => x"20402025", + 9012 => x"30387820", + 9013 => x"2e2e2e0a", + 9014 => x"00000000", + 9015 => x"43616c6c", + 9016 => x"20726574", + 9017 => x"75726e65", + 9018 => x"6420636f", + 9019 => x"64652028", + 9020 => x"2564292e", + 9021 => x"0a000000", + 9022 => x"52657374", + 9023 => x"61727469", + 9024 => x"6e672061", + 9025 => x"70706c69", + 9026 => x"63617469", + 9027 => x"6f6e2e2e", + 9028 => x"2e0a0000", + 9029 => x"436f6c64", + 9030 => x"20726562", + 9031 => x"6f6f7469", + 9032 => x"6e672e2e", + 9033 => x"2e0a0000", + 9034 => x"5a505500", + 9035 => x"62696e00", + 9036 => x"25643a5c", + 9037 => x"25735c25", + 9038 => x"732e2573", + 9039 => x"00000000", + 9040 => x"25643a5c", + 9041 => x"25735c25", + 9042 => x"73000000", + 9043 => x"25643a5c", + 9044 => x"25730000", + 9045 => x"42616420", + 9046 => x"636f6d6d", + 9047 => x"616e642e", + 9048 => x"0a000000", + 9049 => x"52756e6e", + 9050 => x"696e672e", + 9051 => x"2e2e0a00", + 9052 => x"456e6162", + 9053 => x"6c696e67", + 9054 => x"20696e74", + 9055 => x"65727275", + 9056 => x"7074732e", + 9057 => x"2e2e0a00", + 9058 => x"00000000", + 9059 => x"00000000", + 9060 => x"00007fff", + 9061 => x"00000000", + 9062 => x"00007fff", + 9063 => x"00010000", + 9064 => x"00007fff", + 9065 => x"00010000", + 9066 => x"00810000", + 9067 => x"01000000", + 9068 => x"017fffff", + 9069 => x"00000000", + 9070 => x"00000000", + 9071 => x"00007800", + 9072 => x"00000000", + 9073 => x"05f5e100", + 9074 => x"05f5e100", + 9075 => x"05f5e100", + 9076 => x"00000000", + 9077 => x"01010101", + 9078 => x"01010101", + 9079 => x"01011001", + 9080 => x"01000000", + 9081 => x"00000000", + 9082 => x"01000000", + 9083 => x"00000000", + 9084 => x"00006768", + 9085 => x"01020100", + 9086 => x"00000000", + 9087 => x"00000000", + 9088 => x"00006770", + 9089 => x"01040100", + 9090 => x"00000000", + 9091 => x"00000000", + 9092 => x"00006778", + 9093 => x"01140300", + 9094 => x"00000000", + 9095 => x"00000000", + 9096 => x"00006780", + 9097 => x"012b0300", + 9098 => x"00000000", + 9099 => x"00000000", + 9100 => x"00006788", + 9101 => x"01300300", + 9102 => x"00000000", + 9103 => x"00000000", + 9104 => x"00006790", + 9105 => x"013c0400", + 9106 => x"00000000", + 9107 => x"00000000", + 9108 => x"00006798", + 9109 => x"01400400", + 9110 => x"00000000", + 9111 => x"00000000", + 9112 => x"000067a0", + 9113 => x"01450400", + 9114 => x"00000000", + 9115 => x"00000000", + 9116 => x"000067a8", + 9117 => x"01410400", + 9118 => x"00000000", + 9119 => x"00000000", + 9120 => x"000067ac", + 9121 => x"01420400", + 9122 => x"00000000", + 9123 => x"00000000", + 9124 => x"000067b0", + 9125 => x"01430400", + 9126 => x"00000000", + 9127 => x"00000000", + 9128 => x"000067b4", + 9129 => x"01500500", + 9130 => x"00000000", + 9131 => x"00000000", + 9132 => x"000067b8", + 9133 => x"01510500", + 9134 => x"00000000", + 9135 => x"00000000", + 9136 => x"000067bc", + 9137 => x"01540500", + 9138 => x"00000000", + 9139 => x"00000000", + 9140 => x"000067c0", + 9141 => x"01550500", + 9142 => x"00000000", + 9143 => x"00000000", + 9144 => x"000067c4", + 9145 => x"01790700", + 9146 => x"00000000", + 9147 => x"00000000", + 9148 => x"000067cc", + 9149 => x"01780700", + 9150 => x"00000000", + 9151 => x"00000000", + 9152 => x"000067d0", + 9153 => x"01820800", + 9154 => x"00000000", + 9155 => x"00000000", + 9156 => x"000067d8", + 9157 => x"01830800", + 9158 => x"00000000", + 9159 => x"00000000", + 9160 => x"000067e0", + 9161 => x"01850800", + 9162 => x"00000000", + 9163 => x"00000000", + 9164 => x"000067e8", + 9165 => x"01870800", + 9166 => x"00000000", + 9167 => x"00000000", + others => x"00000000" + ); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + + +end arch; + diff --git a/zpu/devices/sysbus/BRAM/IOCP_ZPUTA_DualPortBootBRAM.vhd b/zpu/devices/sysbus/BRAM/IOCP_ZPUTA_DualPortBootBRAM.vhd new file mode 100644 index 0000000..af4a608 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/IOCP_ZPUTA_DualPortBootBRAM.vhd @@ -0,0 +1,31314 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use pkgs.config_pkg.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity DualPortBootBRAM is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + + memBAddr : in std_logic_vector(addrbits-1 downto 2); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBRead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end DualPortBootBRAM; + +architecture arch of DualPortBootBRAM is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + 0 => x"88", + 1 => x"00", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"0b", + 10 => x"08", + 11 => x"8c", + 12 => x"04", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"08", + 17 => x"09", + 18 => x"05", + 19 => x"83", + 20 => x"52", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"08", + 25 => x"73", + 26 => x"81", + 27 => x"83", + 28 => x"06", + 29 => x"ff", + 30 => x"0b", + 31 => x"00", + 32 => x"05", + 33 => x"73", + 34 => x"06", + 35 => x"06", + 36 => x"06", + 37 => x"00", + 38 => x"00", + 39 => x"00", + 40 => x"73", + 41 => x"53", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"09", + 49 => x"06", + 50 => x"72", + 51 => x"72", + 52 => x"31", + 53 => x"06", + 54 => x"51", + 55 => x"00", + 56 => x"73", + 57 => x"53", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"88", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"2b", + 81 => x"04", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"06", + 89 => x"0b", + 90 => x"a7", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"ff", + 97 => x"2a", + 98 => x"0a", + 99 => x"05", + 100 => x"51", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"51", + 105 => x"83", + 106 => x"05", + 107 => x"2b", + 108 => x"72", + 109 => x"51", + 110 => x"00", + 111 => x"00", + 112 => x"05", + 113 => x"70", + 114 => x"06", + 115 => x"53", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"05", + 121 => x"70", + 122 => x"06", + 123 => x"06", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"05", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"81", + 137 => x"51", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"06", + 145 => x"06", + 146 => x"04", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"08", + 153 => x"09", + 154 => x"05", + 155 => x"2a", + 156 => x"52", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"08", + 161 => x"9f", + 162 => x"06", + 163 => x"08", + 164 => x"0b", + 165 => x"00", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"75", + 170 => x"89", + 171 => x"50", + 172 => x"90", + 173 => x"88", + 174 => x"00", + 175 => x"00", + 176 => x"08", + 177 => x"75", + 178 => x"8a", + 179 => x"50", + 180 => x"90", + 181 => x"88", + 182 => x"00", + 183 => x"00", + 184 => x"81", + 185 => x"0a", + 186 => x"05", + 187 => x"06", + 188 => x"74", + 189 => x"06", + 190 => x"51", + 191 => x"00", + 192 => x"81", + 193 => x"0a", + 194 => x"ff", + 195 => x"71", + 196 => x"72", + 197 => x"05", + 198 => x"51", + 199 => x"00", + 200 => x"04", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"52", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"72", + 233 => x"52", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"ff", + 249 => x"51", + 250 => x"00", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"04", + 257 => x"00", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"53", + 266 => x"00", + 267 => x"06", + 268 => x"09", + 269 => x"05", + 270 => x"2b", + 271 => x"06", + 272 => x"04", + 273 => x"72", + 274 => x"05", + 275 => x"05", + 276 => x"72", + 277 => x"53", + 278 => x"51", + 279 => x"04", + 280 => x"88", + 281 => x"00", + 282 => x"70", + 283 => x"8b", + 284 => x"70", + 285 => x"0c", + 286 => x"88", + 287 => x"99", + 288 => x"02", + 289 => x"3d", + 290 => x"94", + 291 => x"08", + 292 => x"88", + 293 => x"82", + 294 => x"08", + 295 => x"54", + 296 => x"94", + 297 => x"08", + 298 => x"fd", + 299 => x"53", + 300 => x"05", + 301 => x"08", + 302 => x"51", + 303 => x"88", + 304 => x"0c", + 305 => x"0d", + 306 => x"94", + 307 => x"0c", + 308 => x"80", + 309 => x"fc", + 310 => x"08", + 311 => x"80", + 312 => x"94", + 313 => x"08", + 314 => x"88", + 315 => x"0b", + 316 => x"05", + 317 => x"fc", + 318 => x"38", + 319 => x"08", + 320 => x"94", + 321 => x"08", + 322 => x"05", + 323 => x"8c", + 324 => x"25", + 325 => x"08", + 326 => x"30", + 327 => x"05", + 328 => x"94", + 329 => x"0c", + 330 => x"05", + 331 => x"81", + 332 => x"f0", + 333 => x"08", + 334 => x"94", + 335 => x"0c", + 336 => x"08", + 337 => x"52", + 338 => x"05", + 339 => x"a7", + 340 => x"70", + 341 => x"05", + 342 => x"08", + 343 => x"80", + 344 => x"94", + 345 => x"08", + 346 => x"f8", + 347 => x"08", + 348 => x"70", + 349 => x"89", + 350 => x"0c", + 351 => x"02", + 352 => x"3d", + 353 => x"94", + 354 => x"0c", + 355 => x"05", + 356 => x"93", + 357 => x"88", + 358 => x"94", + 359 => x"0c", + 360 => x"08", + 361 => x"94", + 362 => x"08", + 363 => x"38", + 364 => x"05", + 365 => x"08", + 366 => x"81", + 367 => x"8c", + 368 => x"94", + 369 => x"08", + 370 => x"88", + 371 => x"08", + 372 => x"54", + 373 => x"05", + 374 => x"8c", + 375 => x"f8", + 376 => x"94", + 377 => x"0c", + 378 => x"05", + 379 => x"0c", + 380 => x"0d", + 381 => x"94", + 382 => x"0c", + 383 => x"81", + 384 => x"fc", + 385 => x"0b", + 386 => x"05", + 387 => x"8c", + 388 => x"08", + 389 => x"27", + 390 => x"08", + 391 => x"80", + 392 => x"80", + 393 => x"8c", + 394 => x"99", + 395 => x"8c", + 396 => x"94", + 397 => x"0c", + 398 => x"05", + 399 => x"08", + 400 => x"c9", + 401 => x"fc", + 402 => x"2e", + 403 => x"94", + 404 => x"08", + 405 => x"05", + 406 => x"38", + 407 => x"05", + 408 => x"8c", + 409 => x"94", + 410 => x"0c", + 411 => x"05", + 412 => x"fc", + 413 => x"94", + 414 => x"0c", + 415 => x"05", + 416 => x"94", + 417 => x"0c", + 418 => x"05", + 419 => x"94", + 420 => x"0c", + 421 => x"94", + 422 => x"08", + 423 => x"38", + 424 => x"05", + 425 => x"08", + 426 => x"51", + 427 => x"08", + 428 => x"70", + 429 => x"05", + 430 => x"08", + 431 => x"88", + 432 => x"0d", + 433 => x"ff", + 434 => x"88", + 435 => x"92", + 436 => x"0b", + 437 => x"8c", + 438 => x"87", + 439 => x"0c", + 440 => x"8c", + 441 => x"06", + 442 => x"80", + 443 => x"87", + 444 => x"08", + 445 => x"38", + 446 => x"8c", + 447 => x"80", + 448 => x"93", + 449 => x"98", + 450 => x"70", + 451 => x"38", + 452 => x"0b", + 453 => x"0b", + 454 => x"a8", + 455 => x"83", + 456 => x"fa", + 457 => x"7b", + 458 => x"56", + 459 => x"0b", + 460 => x"33", + 461 => x"55", + 462 => x"75", + 463 => x"06", + 464 => x"85", + 465 => x"98", + 466 => x"87", + 467 => x"0c", + 468 => x"c0", + 469 => x"87", + 470 => x"08", + 471 => x"70", + 472 => x"52", + 473 => x"2e", + 474 => x"c0", + 475 => x"70", + 476 => x"76", + 477 => x"53", + 478 => x"2e", + 479 => x"80", + 480 => x"71", + 481 => x"05", + 482 => x"14", + 483 => x"55", + 484 => x"51", + 485 => x"8b", + 486 => x"98", + 487 => x"70", + 488 => x"87", + 489 => x"08", + 490 => x"38", + 491 => x"c0", + 492 => x"87", + 493 => x"08", + 494 => x"51", + 495 => x"38", + 496 => x"80", + 497 => x"52", + 498 => x"09", + 499 => x"38", + 500 => x"8c", + 501 => x"72", + 502 => x"06", + 503 => x"52", + 504 => x"88", + 505 => x"fe", + 506 => x"81", + 507 => x"33", + 508 => x"07", + 509 => x"51", + 510 => x"04", + 511 => x"75", + 512 => x"82", + 513 => x"90", + 514 => x"2b", + 515 => x"33", + 516 => x"88", + 517 => x"71", + 518 => x"52", + 519 => x"54", + 520 => x"0d", + 521 => x"0d", + 522 => x"0b", + 523 => x"57", + 524 => x"27", + 525 => x"76", + 526 => x"27", + 527 => x"75", + 528 => x"82", + 529 => x"74", + 530 => x"38", + 531 => x"74", + 532 => x"83", + 533 => x"76", + 534 => x"17", + 535 => x"88", + 536 => x"55", + 537 => x"88", + 538 => x"74", + 539 => x"3f", + 540 => x"ff", + 541 => x"ad", + 542 => x"76", + 543 => x"fc", + 544 => x"87", + 545 => x"08", + 546 => x"3d", + 547 => x"fd", + 548 => x"08", + 549 => x"51", + 550 => x"88", + 551 => x"06", + 552 => x"81", + 553 => x"0c", + 554 => x"04", + 555 => x"0b", + 556 => x"ac", + 557 => x"88", + 558 => x"05", + 559 => x"80", + 560 => x"27", + 561 => x"14", + 562 => x"29", + 563 => x"05", + 564 => x"88", + 565 => x"0d", + 566 => x"0d", + 567 => x"0b", + 568 => x"9f", + 569 => x"33", + 570 => x"71", + 571 => x"81", + 572 => x"94", + 573 => x"ef", + 574 => x"90", + 575 => x"14", + 576 => x"3f", + 577 => x"ff", + 578 => x"07", + 579 => x"3d", + 580 => x"3d", + 581 => x"0b", + 582 => x"08", + 583 => x"75", + 584 => x"08", + 585 => x"2e", + 586 => x"14", + 587 => x"85", + 588 => x"b0", + 589 => x"38", + 590 => x"71", + 591 => x"81", + 592 => x"90", + 593 => x"72", + 594 => x"72", + 595 => x"38", + 596 => x"d8", + 597 => x"52", + 598 => x"14", + 599 => x"90", + 600 => x"52", + 601 => x"86", + 602 => x"fa", + 603 => x"0b", + 604 => x"ac", + 605 => x"81", + 606 => x"ff", + 607 => x"54", + 608 => x"80", + 609 => x"90", + 610 => x"72", + 611 => x"52", + 612 => x"73", + 613 => x"71", + 614 => x"81", + 615 => x"0c", + 616 => x"53", + 617 => x"83", + 618 => x"22", + 619 => x"76", + 620 => x"b5", + 621 => x"33", + 622 => x"84", + 623 => x"71", + 624 => x"51", + 625 => x"81", + 626 => x"08", + 627 => x"83", + 628 => x"88", + 629 => x"96", + 630 => x"8c", + 631 => x"08", + 632 => x"3f", + 633 => x"16", + 634 => x"23", + 635 => x"88", + 636 => x"0d", + 637 => x"0d", + 638 => x"58", + 639 => x"33", + 640 => x"2e", + 641 => x"88", + 642 => x"70", + 643 => x"39", + 644 => x"56", + 645 => x"2e", + 646 => x"84", + 647 => x"43", + 648 => x"1d", + 649 => x"33", + 650 => x"9f", + 651 => x"7b", + 652 => x"3f", + 653 => x"80", + 654 => x"d3", + 655 => x"84", + 656 => x"58", + 657 => x"55", + 658 => x"81", + 659 => x"ff", + 660 => x"ff", + 661 => x"06", + 662 => x"70", + 663 => x"7f", + 664 => x"7a", + 665 => x"81", + 666 => x"13", + 667 => x"af", + 668 => x"a0", + 669 => x"80", + 670 => x"51", + 671 => x"5d", + 672 => x"80", + 673 => x"ae", + 674 => x"06", + 675 => x"55", + 676 => x"75", + 677 => x"80", + 678 => x"79", + 679 => x"30", + 680 => x"70", + 681 => x"07", + 682 => x"51", + 683 => x"75", + 684 => x"58", + 685 => x"ab", + 686 => x"19", + 687 => x"06", + 688 => x"5a", + 689 => x"75", + 690 => x"39", + 691 => x"0c", + 692 => x"a0", + 693 => x"81", + 694 => x"1a", + 695 => x"fc", + 696 => x"08", + 697 => x"a0", + 698 => x"70", + 699 => x"e0", + 700 => x"90", + 701 => x"7c", + 702 => x"3f", + 703 => x"88", + 704 => x"38", + 705 => x"74", + 706 => x"ee", + 707 => x"33", + 708 => x"70", + 709 => x"56", + 710 => x"38", + 711 => x"1e", + 712 => x"59", + 713 => x"ff", + 714 => x"ff", + 715 => x"79", + 716 => x"5b", + 717 => x"81", + 718 => x"71", + 719 => x"56", + 720 => x"2e", + 721 => x"39", + 722 => x"92", + 723 => x"fc", + 724 => x"8e", + 725 => x"56", + 726 => x"38", + 727 => x"56", + 728 => x"8b", + 729 => x"55", + 730 => x"8b", + 731 => x"84", + 732 => x"06", + 733 => x"74", + 734 => x"56", + 735 => x"56", + 736 => x"51", + 737 => x"88", + 738 => x"0c", + 739 => x"75", + 740 => x"3d", + 741 => x"3d", + 742 => x"59", + 743 => x"83", + 744 => x"52", + 745 => x"fb", + 746 => x"88", + 747 => x"38", + 748 => x"b3", + 749 => x"83", + 750 => x"55", + 751 => x"82", + 752 => x"09", + 753 => x"ce", + 754 => x"b6", + 755 => x"76", + 756 => x"3f", + 757 => x"88", + 758 => x"76", + 759 => x"3f", + 760 => x"ff", + 761 => x"74", + 762 => x"2e", + 763 => x"54", + 764 => x"77", + 765 => x"f6", + 766 => x"08", + 767 => x"94", + 768 => x"f7", + 769 => x"08", + 770 => x"06", + 771 => x"82", + 772 => x"38", + 773 => x"88", + 774 => x"0d", + 775 => x"0d", + 776 => x"0b", + 777 => x"9f", + 778 => x"9b", + 779 => x"81", + 780 => x"56", + 781 => x"38", + 782 => x"8d", + 783 => x"57", + 784 => x"3f", + 785 => x"ff", + 786 => x"81", + 787 => x"06", + 788 => x"54", + 789 => x"74", + 790 => x"f5", + 791 => x"08", + 792 => x"3d", + 793 => x"80", + 794 => x"95", + 795 => x"51", + 796 => x"88", + 797 => x"53", + 798 => x"fe", + 799 => x"08", + 800 => x"57", + 801 => x"09", + 802 => x"38", + 803 => x"99", + 804 => x"2e", + 805 => x"56", + 806 => x"a4", + 807 => x"79", + 808 => x"f4", + 809 => x"56", + 810 => x"fd", + 811 => x"e5", + 812 => x"b3", + 813 => x"83", + 814 => x"58", + 815 => x"95", + 816 => x"51", + 817 => x"88", + 818 => x"af", + 819 => x"71", + 820 => x"05", + 821 => x"54", + 822 => x"f6", + 823 => x"08", + 824 => x"06", + 825 => x"1a", + 826 => x"33", + 827 => x"95", + 828 => x"51", + 829 => x"88", + 830 => x"23", + 831 => x"05", + 832 => x"3f", + 833 => x"ff", + 834 => x"75", + 835 => x"3d", + 836 => x"f5", + 837 => x"08", + 838 => x"f5", + 839 => x"08", + 840 => x"06", + 841 => x"79", + 842 => x"22", + 843 => x"82", + 844 => x"72", + 845 => x"59", + 846 => x"ee", + 847 => x"08", + 848 => x"88", + 849 => x"08", + 850 => x"56", + 851 => x"df", + 852 => x"38", + 853 => x"ff", + 854 => x"85", + 855 => x"89", + 856 => x"76", + 857 => x"c1", + 858 => x"34", + 859 => x"09", + 860 => x"38", + 861 => x"05", + 862 => x"3f", + 863 => x"1a", + 864 => x"8c", + 865 => x"90", + 866 => x"83", + 867 => x"8c", + 868 => x"71", + 869 => x"94", + 870 => x"80", + 871 => x"34", + 872 => x"0b", + 873 => x"80", + 874 => x"0c", + 875 => x"04", + 876 => x"0b", + 877 => x"ac", + 878 => x"54", + 879 => x"80", + 880 => x"0b", + 881 => x"98", + 882 => x"45", + 883 => x"3d", + 884 => x"ec", + 885 => x"9d", + 886 => x"54", + 887 => x"c0", + 888 => x"33", + 889 => x"2e", + 890 => x"a7", + 891 => x"84", + 892 => x"06", + 893 => x"73", + 894 => x"38", + 895 => x"39", + 896 => x"d5", + 897 => x"a0", + 898 => x"3d", + 899 => x"f3", + 900 => x"08", + 901 => x"73", + 902 => x"81", + 903 => x"34", + 904 => x"98", + 905 => x"f6", + 906 => x"7f", + 907 => x"0b", + 908 => x"59", + 909 => x"80", + 910 => x"57", + 911 => x"81", + 912 => x"16", + 913 => x"55", + 914 => x"80", + 915 => x"38", + 916 => x"81", + 917 => x"39", + 918 => x"17", + 919 => x"81", + 920 => x"16", + 921 => x"08", + 922 => x"78", + 923 => x"74", + 924 => x"2e", + 925 => x"98", + 926 => x"83", + 927 => x"57", + 928 => x"38", + 929 => x"ff", + 930 => x"2a", + 931 => x"ff", + 932 => x"79", + 933 => x"87", + 934 => x"08", + 935 => x"a4", + 936 => x"f3", + 937 => x"08", + 938 => x"27", + 939 => x"74", + 940 => x"a4", + 941 => x"f3", + 942 => x"08", + 943 => x"80", + 944 => x"38", + 945 => x"a8", + 946 => x"16", + 947 => x"06", + 948 => x"31", + 949 => x"75", + 950 => x"77", + 951 => x"98", + 952 => x"ff", + 953 => x"16", + 954 => x"51", + 955 => x"88", + 956 => x"38", + 957 => x"15", + 958 => x"77", + 959 => x"08", + 960 => x"58", + 961 => x"fe", + 962 => x"19", + 963 => x"39", + 964 => x"88", + 965 => x"0d", + 966 => x"0d", + 967 => x"e4", + 968 => x"94", + 969 => x"90", + 970 => x"87", + 971 => x"0c", + 972 => x"0b", + 973 => x"84", + 974 => x"83", + 975 => x"94", + 976 => x"b0", + 977 => x"3f", + 978 => x"38", + 979 => x"fc", + 980 => x"08", + 981 => x"80", + 982 => x"87", + 983 => x"0c", + 984 => x"fc", + 985 => x"80", + 986 => x"fd", + 987 => x"08", + 988 => x"54", + 989 => x"86", + 990 => x"55", + 991 => x"80", + 992 => x"80", + 993 => x"00", + 994 => x"ff", + 995 => x"ff", + 996 => x"ff", + 997 => x"00", + 998 => x"54", + 999 => x"59", + 1000 => x"4d", + 1001 => x"00", + 1002 => x"00", + 2048 => x"c4", + 2049 => x"0b", + 2050 => x"04", + 2051 => x"ff", + 2052 => x"ff", + 2053 => x"ff", + 2054 => x"ff", + 2055 => x"ff", + 2056 => x"c4", + 2057 => x"0b", + 2058 => x"04", + 2059 => x"c4", + 2060 => x"0b", + 2061 => x"04", + 2062 => x"c4", + 2063 => x"0b", + 2064 => x"04", + 2065 => x"c4", + 2066 => x"0b", + 2067 => x"04", + 2068 => x"c4", + 2069 => x"0b", + 2070 => x"04", + 2071 => x"c5", + 2072 => x"0b", + 2073 => x"04", + 2074 => x"c5", + 2075 => x"0b", + 2076 => x"04", + 2077 => x"c5", + 2078 => x"0b", + 2079 => x"04", + 2080 => x"c5", + 2081 => x"0b", + 2082 => x"04", + 2083 => x"c6", + 2084 => x"0b", + 2085 => x"04", + 2086 => x"c6", + 2087 => x"0b", + 2088 => x"04", + 2089 => x"c6", + 2090 => x"0b", + 2091 => x"04", + 2092 => x"c6", + 2093 => x"0b", + 2094 => x"04", + 2095 => x"c7", + 2096 => x"0b", + 2097 => x"04", + 2098 => x"c7", + 2099 => x"0b", + 2100 => x"04", + 2101 => x"c7", + 2102 => x"0b", + 2103 => x"04", + 2104 => x"c7", + 2105 => x"0b", + 2106 => x"04", + 2107 => x"c8", + 2108 => x"0b", + 2109 => x"04", + 2110 => x"c8", + 2111 => x"0b", + 2112 => x"04", + 2113 => x"c8", + 2114 => x"0b", + 2115 => x"04", + 2116 => x"c8", + 2117 => x"0b", + 2118 => x"04", + 2119 => x"c9", + 2120 => x"0b", + 2121 => x"04", + 2122 => x"c9", + 2123 => x"0b", + 2124 => x"04", + 2125 => x"c9", + 2126 => x"0b", + 2127 => x"04", + 2128 => x"c9", + 2129 => x"0b", + 2130 => x"04", + 2131 => x"00", + 2132 => x"00", + 2133 => x"00", + 2134 => x"00", + 2135 => x"00", + 2136 => x"00", + 2137 => x"00", + 2138 => x"00", + 2139 => x"00", + 2140 => x"00", + 2141 => x"00", + 2142 => x"00", + 2143 => x"00", + 2144 => x"00", + 2145 => x"00", + 2146 => x"00", + 2147 => x"00", + 2148 => x"00", + 2149 => x"00", + 2150 => x"00", + 2151 => x"00", + 2152 => x"00", + 2153 => x"00", + 2154 => x"00", + 2155 => x"00", + 2156 => x"00", + 2157 => x"00", + 2158 => x"00", + 2159 => x"00", + 2160 => x"00", + 2161 => x"00", + 2162 => x"00", + 2163 => x"00", + 2164 => x"00", + 2165 => x"00", + 2166 => x"00", + 2167 => x"00", + 2168 => x"00", + 2169 => x"00", + 2170 => x"00", + 2171 => x"00", + 2172 => x"00", + 2173 => x"00", + 2174 => x"00", + 2175 => x"00", + 2176 => x"80", + 2177 => x"d4", + 2178 => x"80", + 2179 => x"d4", + 2180 => x"90", + 2181 => x"d4", + 2182 => x"c0", + 2183 => x"d4", + 2184 => x"90", + 2185 => x"d4", + 2186 => x"85", + 2187 => x"d4", + 2188 => x"90", + 2189 => x"d4", + 2190 => x"a3", + 2191 => x"d4", + 2192 => x"90", + 2193 => x"d4", + 2194 => x"f7", + 2195 => x"d4", + 2196 => x"90", + 2197 => x"d4", + 2198 => x"8b", + 2199 => x"d4", + 2200 => x"90", + 2201 => x"d4", + 2202 => x"c4", + 2203 => x"d4", + 2204 => x"90", + 2205 => x"d4", + 2206 => x"a8", + 2207 => x"d4", + 2208 => x"90", + 2209 => x"d4", + 2210 => x"be", + 2211 => x"d4", + 2212 => x"90", + 2213 => x"d4", + 2214 => x"9d", + 2215 => x"d4", + 2216 => x"90", + 2217 => x"d4", + 2218 => x"b3", + 2219 => x"d4", + 2220 => x"90", + 2221 => x"d4", + 2222 => x"d7", + 2223 => x"d4", + 2224 => x"90", + 2225 => x"d4", + 2226 => x"80", + 2227 => x"d4", + 2228 => x"90", + 2229 => x"d4", + 2230 => x"ce", + 2231 => x"d4", + 2232 => x"90", + 2233 => x"d4", + 2234 => x"d8", + 2235 => x"d4", + 2236 => x"90", + 2237 => x"d4", + 2238 => x"90", + 2239 => x"d4", + 2240 => x"90", + 2241 => x"d4", + 2242 => x"ea", + 2243 => x"d4", + 2244 => x"90", + 2245 => x"d4", + 2246 => x"f2", + 2247 => x"d4", + 2248 => x"90", + 2249 => x"d4", + 2250 => x"e9", + 2251 => x"d4", + 2252 => x"90", + 2253 => x"d4", + 2254 => x"f8", + 2255 => x"d4", + 2256 => x"90", + 2257 => x"d4", + 2258 => x"df", + 2259 => x"d4", + 2260 => x"90", + 2261 => x"d4", + 2262 => x"92", + 2263 => x"d4", + 2264 => x"90", + 2265 => x"d4", + 2266 => x"86", + 2267 => x"d4", + 2268 => x"90", + 2269 => x"d4", + 2270 => x"9a", + 2271 => x"d4", + 2272 => x"90", + 2273 => x"d4", + 2274 => x"bd", + 2275 => x"d4", + 2276 => x"90", + 2277 => x"d4", + 2278 => x"e1", + 2279 => x"d4", + 2280 => x"90", + 2281 => x"d4", + 2282 => x"8a", + 2283 => x"d4", + 2284 => x"90", + 2285 => x"d4", + 2286 => x"9a", + 2287 => x"d4", + 2288 => x"90", + 2289 => x"d4", + 2290 => x"92", + 2291 => x"d4", + 2292 => x"90", + 2293 => x"d4", + 2294 => x"f3", + 2295 => x"d4", + 2296 => x"90", + 2297 => x"d4", + 2298 => x"80", + 2299 => x"d4", + 2300 => x"90", + 2301 => x"d4", + 2302 => x"f7", + 2303 => x"d4", + 2304 => x"90", + 2305 => x"d4", + 2306 => x"fd", + 2307 => x"d4", + 2308 => x"90", + 2309 => x"d4", + 2310 => x"c9", + 2311 => x"d4", + 2312 => x"90", + 2313 => x"d4", + 2314 => x"a2", + 2315 => x"d4", + 2316 => x"90", + 2317 => x"d4", + 2318 => x"cc", + 2319 => x"d4", + 2320 => x"90", + 2321 => x"d4", + 2322 => x"da", + 2323 => x"d4", + 2324 => x"90", + 2325 => x"d4", + 2326 => x"f6", + 2327 => x"d4", + 2328 => x"90", + 2329 => x"d4", + 2330 => x"81", + 2331 => x"d4", + 2332 => x"90", + 2333 => x"d4", + 2334 => x"ee", + 2335 => x"d4", + 2336 => x"90", + 2337 => x"d4", + 2338 => x"83", + 2339 => x"d4", + 2340 => x"90", + 2341 => x"d4", + 2342 => x"df", + 2343 => x"d4", + 2344 => x"90", + 2345 => x"d4", + 2346 => x"fe", + 2347 => x"d4", + 2348 => x"90", + 2349 => x"d4", + 2350 => x"d7", + 2351 => x"d4", + 2352 => x"90", + 2353 => x"d4", + 2354 => x"b1", + 2355 => x"d4", + 2356 => x"90", + 2357 => x"d4", + 2358 => x"81", + 2359 => x"d4", + 2360 => x"90", + 2361 => x"d4", + 2362 => x"e6", + 2363 => x"d4", + 2364 => x"90", + 2365 => x"d4", + 2366 => x"f3", + 2367 => x"d4", + 2368 => x"90", + 2369 => x"d4", + 2370 => x"dd", + 2371 => x"d4", + 2372 => x"90", + 2373 => x"c8", + 2374 => x"cc", + 2375 => x"80", + 2376 => x"05", + 2377 => x"0b", + 2378 => x"04", + 2379 => x"51", + 2380 => x"04", + 2381 => x"93", + 2382 => x"82", + 2383 => x"fd", + 2384 => x"53", + 2385 => x"08", + 2386 => x"52", + 2387 => x"08", + 2388 => x"51", + 2389 => x"82", + 2390 => x"70", + 2391 => x"0c", + 2392 => x"0d", + 2393 => x"0c", + 2394 => x"d4", + 2395 => x"93", + 2396 => x"3d", + 2397 => x"82", + 2398 => x"8c", + 2399 => x"82", + 2400 => x"88", + 2401 => x"93", + 2402 => x"c8", + 2403 => x"93", + 2404 => x"85", + 2405 => x"93", + 2406 => x"82", + 2407 => x"02", + 2408 => x"0c", + 2409 => x"81", + 2410 => x"d4", + 2411 => x"0c", + 2412 => x"93", + 2413 => x"05", + 2414 => x"d4", + 2415 => x"08", + 2416 => x"08", + 2417 => x"27", + 2418 => x"93", + 2419 => x"05", + 2420 => x"ae", + 2421 => x"82", + 2422 => x"8c", + 2423 => x"a2", + 2424 => x"d4", + 2425 => x"08", + 2426 => x"d4", + 2427 => x"0c", + 2428 => x"08", + 2429 => x"10", + 2430 => x"08", + 2431 => x"ff", + 2432 => x"93", + 2433 => x"05", + 2434 => x"80", + 2435 => x"93", + 2436 => x"05", + 2437 => x"d4", + 2438 => x"08", + 2439 => x"82", + 2440 => x"88", + 2441 => x"93", + 2442 => x"05", + 2443 => x"93", + 2444 => x"05", + 2445 => x"d4", + 2446 => x"08", + 2447 => x"08", + 2448 => x"07", + 2449 => x"08", + 2450 => x"82", + 2451 => x"fc", + 2452 => x"2a", + 2453 => x"08", + 2454 => x"82", + 2455 => x"8c", + 2456 => x"2a", + 2457 => x"08", + 2458 => x"ff", + 2459 => x"93", + 2460 => x"05", + 2461 => x"93", + 2462 => x"d4", + 2463 => x"08", + 2464 => x"d4", + 2465 => x"0c", + 2466 => x"82", + 2467 => x"f8", + 2468 => x"82", + 2469 => x"f4", + 2470 => x"82", + 2471 => x"f4", + 2472 => x"93", + 2473 => x"3d", + 2474 => x"d4", + 2475 => x"3d", + 2476 => x"71", + 2477 => x"9f", + 2478 => x"55", + 2479 => x"72", + 2480 => x"74", + 2481 => x"70", + 2482 => x"38", + 2483 => x"71", + 2484 => x"38", + 2485 => x"81", + 2486 => x"ff", + 2487 => x"ff", + 2488 => x"06", + 2489 => x"82", + 2490 => x"86", + 2491 => x"74", + 2492 => x"75", + 2493 => x"90", + 2494 => x"54", + 2495 => x"27", + 2496 => x"71", + 2497 => x"53", + 2498 => x"70", + 2499 => x"0c", + 2500 => x"84", + 2501 => x"72", + 2502 => x"05", + 2503 => x"12", + 2504 => x"26", + 2505 => x"72", + 2506 => x"72", + 2507 => x"05", + 2508 => x"12", + 2509 => x"26", + 2510 => x"53", + 2511 => x"fb", + 2512 => x"79", + 2513 => x"83", + 2514 => x"52", + 2515 => x"71", + 2516 => x"54", + 2517 => x"73", + 2518 => x"c6", + 2519 => x"54", + 2520 => x"70", + 2521 => x"52", + 2522 => x"2e", + 2523 => x"33", + 2524 => x"2e", + 2525 => x"95", + 2526 => x"81", + 2527 => x"70", + 2528 => x"54", + 2529 => x"70", + 2530 => x"33", + 2531 => x"ff", + 2532 => x"ff", + 2533 => x"31", + 2534 => x"0c", + 2535 => x"3d", + 2536 => x"09", + 2537 => x"fd", + 2538 => x"70", + 2539 => x"81", + 2540 => x"51", + 2541 => x"38", + 2542 => x"16", + 2543 => x"56", + 2544 => x"08", + 2545 => x"73", + 2546 => x"ff", + 2547 => x"0b", + 2548 => x"0c", + 2549 => x"04", + 2550 => x"80", + 2551 => x"71", + 2552 => x"87", + 2553 => x"93", + 2554 => x"ff", + 2555 => x"81", + 2556 => x"83", + 2557 => x"38", + 2558 => x"c8", + 2559 => x"0d", + 2560 => x"0d", + 2561 => x"70", + 2562 => x"73", + 2563 => x"cd", + 2564 => x"51", + 2565 => x"09", + 2566 => x"38", + 2567 => x"33", + 2568 => x"a0", + 2569 => x"73", + 2570 => x"81", + 2571 => x"72", + 2572 => x"70", + 2573 => x"38", + 2574 => x"30", + 2575 => x"74", + 2576 => x"70", + 2577 => x"33", + 2578 => x"2e", + 2579 => x"88", + 2580 => x"70", + 2581 => x"34", + 2582 => x"73", + 2583 => x"93", + 2584 => x"3d", + 2585 => x"3d", + 2586 => x"72", + 2587 => x"91", + 2588 => x"fc", + 2589 => x"51", + 2590 => x"82", + 2591 => x"85", + 2592 => x"83", + 2593 => x"72", + 2594 => x"0c", + 2595 => x"04", + 2596 => x"7d", + 2597 => x"ff", + 2598 => x"81", + 2599 => x"26", + 2600 => x"83", + 2601 => x"05", + 2602 => x"79", + 2603 => x"b1", + 2604 => x"33", + 2605 => x"79", + 2606 => x"a5", + 2607 => x"33", + 2608 => x"79", + 2609 => x"99", + 2610 => x"33", + 2611 => x"79", + 2612 => x"8d", + 2613 => x"22", + 2614 => x"79", + 2615 => x"81", + 2616 => x"1c", + 2617 => x"5b", + 2618 => x"26", + 2619 => x"8a", + 2620 => x"88", + 2621 => x"86", + 2622 => x"85", + 2623 => x"84", + 2624 => x"83", + 2625 => x"82", + 2626 => x"7b", + 2627 => x"f6", + 2628 => x"89", + 2629 => x"98", + 2630 => x"7b", + 2631 => x"87", + 2632 => x"0c", + 2633 => x"87", + 2634 => x"0c", + 2635 => x"87", + 2636 => x"0c", + 2637 => x"87", + 2638 => x"0c", + 2639 => x"87", + 2640 => x"0c", + 2641 => x"87", + 2642 => x"0c", + 2643 => x"87", + 2644 => x"0c", + 2645 => x"87", + 2646 => x"0c", + 2647 => x"80", + 2648 => x"93", + 2649 => x"3d", + 2650 => x"3d", + 2651 => x"87", + 2652 => x"5c", + 2653 => x"87", + 2654 => x"08", + 2655 => x"23", + 2656 => x"b8", + 2657 => x"82", + 2658 => x"c0", + 2659 => x"5b", + 2660 => x"34", + 2661 => x"b0", + 2662 => x"84", + 2663 => x"c0", + 2664 => x"5b", + 2665 => x"34", + 2666 => x"a8", + 2667 => x"86", + 2668 => x"c0", + 2669 => x"5b", + 2670 => x"23", + 2671 => x"a0", + 2672 => x"8a", + 2673 => x"7c", + 2674 => x"22", + 2675 => x"22", + 2676 => x"33", + 2677 => x"33", + 2678 => x"33", + 2679 => x"33", + 2680 => x"33", + 2681 => x"52", + 2682 => x"51", + 2683 => x"8d", + 2684 => x"80", + 2685 => x"8b", + 2686 => x"30", + 2687 => x"51", + 2688 => x"0b", + 2689 => x"c0", + 2690 => x"0d", + 2691 => x"0d", + 2692 => x"82", + 2693 => x"54", + 2694 => x"94", + 2695 => x"80", + 2696 => x"87", + 2697 => x"51", + 2698 => x"96", + 2699 => x"06", + 2700 => x"70", + 2701 => x"38", + 2702 => x"70", + 2703 => x"51", + 2704 => x"71", + 2705 => x"32", + 2706 => x"51", + 2707 => x"2e", + 2708 => x"93", + 2709 => x"06", + 2710 => x"ff", + 2711 => x"0b", + 2712 => x"33", + 2713 => x"94", + 2714 => x"80", + 2715 => x"87", + 2716 => x"52", + 2717 => x"73", + 2718 => x"0c", + 2719 => x"04", + 2720 => x"02", + 2721 => x"0b", + 2722 => x"c0", + 2723 => x"87", + 2724 => x"51", + 2725 => x"86", + 2726 => x"94", + 2727 => x"08", + 2728 => x"70", + 2729 => x"52", + 2730 => x"2e", + 2731 => x"91", + 2732 => x"06", + 2733 => x"d7", + 2734 => x"2a", + 2735 => x"81", + 2736 => x"70", + 2737 => x"38", + 2738 => x"70", + 2739 => x"51", + 2740 => x"38", + 2741 => x"8b", + 2742 => x"87", + 2743 => x"52", + 2744 => x"86", + 2745 => x"94", + 2746 => x"72", + 2747 => x"0d", + 2748 => x"0d", + 2749 => x"74", + 2750 => x"70", + 2751 => x"f7", + 2752 => x"81", + 2753 => x"0b", + 2754 => x"c0", + 2755 => x"87", + 2756 => x"51", + 2757 => x"86", + 2758 => x"94", + 2759 => x"08", + 2760 => x"70", + 2761 => x"52", + 2762 => x"2e", + 2763 => x"91", + 2764 => x"06", + 2765 => x"d7", + 2766 => x"2a", + 2767 => x"81", + 2768 => x"70", + 2769 => x"38", + 2770 => x"70", + 2771 => x"51", + 2772 => x"38", + 2773 => x"8b", + 2774 => x"87", + 2775 => x"52", + 2776 => x"86", + 2777 => x"94", + 2778 => x"72", + 2779 => x"74", + 2780 => x"70", + 2781 => x"75", + 2782 => x"0c", + 2783 => x"04", + 2784 => x"0b", + 2785 => x"c0", + 2786 => x"c0", + 2787 => x"71", + 2788 => x"38", + 2789 => x"94", + 2790 => x"70", + 2791 => x"81", + 2792 => x"51", + 2793 => x"e2", + 2794 => x"82", + 2795 => x"51", + 2796 => x"80", + 2797 => x"2e", + 2798 => x"c0", + 2799 => x"71", + 2800 => x"ff", + 2801 => x"c8", + 2802 => x"3d", + 2803 => x"3d", + 2804 => x"82", + 2805 => x"51", + 2806 => x"84", + 2807 => x"2e", + 2808 => x"c0", + 2809 => x"71", + 2810 => x"2a", + 2811 => x"51", + 2812 => x"52", + 2813 => x"a2", + 2814 => x"82", + 2815 => x"51", + 2816 => x"80", + 2817 => x"2e", + 2818 => x"c0", + 2819 => x"71", + 2820 => x"2b", + 2821 => x"51", + 2822 => x"82", + 2823 => x"83", + 2824 => x"fd", + 2825 => x"c0", + 2826 => x"08", + 2827 => x"8a", + 2828 => x"53", + 2829 => x"83", + 2830 => x"8b", + 2831 => x"c0", + 2832 => x"71", + 2833 => x"87", + 2834 => x"08", + 2835 => x"88", + 2836 => x"9e", + 2837 => x"0c", + 2838 => x"87", + 2839 => x"08", + 2840 => x"90", + 2841 => x"9e", + 2842 => x"0c", + 2843 => x"87", + 2844 => x"08", + 2845 => x"98", + 2846 => x"9e", + 2847 => x"0c", + 2848 => x"87", + 2849 => x"08", + 2850 => x"a0", + 2851 => x"9e", + 2852 => x"0c", + 2853 => x"52", + 2854 => x"13", + 2855 => x"87", + 2856 => x"08", + 2857 => x"81", + 2858 => x"34", + 2859 => x"80", + 2860 => x"9e", + 2861 => x"a0", + 2862 => x"52", + 2863 => x"2e", + 2864 => x"53", + 2865 => x"80", + 2866 => x"9e", + 2867 => x"81", + 2868 => x"51", + 2869 => x"80", + 2870 => x"81", + 2871 => x"8b", + 2872 => x"0b", + 2873 => x"88", + 2874 => x"c0", + 2875 => x"52", + 2876 => x"2e", + 2877 => x"52", + 2878 => x"f3", + 2879 => x"87", + 2880 => x"08", + 2881 => x"06", + 2882 => x"70", + 2883 => x"38", + 2884 => x"82", + 2885 => x"80", + 2886 => x"9e", + 2887 => x"88", + 2888 => x"52", + 2889 => x"2e", + 2890 => x"52", + 2891 => x"f5", + 2892 => x"87", + 2893 => x"08", + 2894 => x"06", + 2895 => x"70", + 2896 => x"38", + 2897 => x"82", + 2898 => x"80", + 2899 => x"9e", + 2900 => x"82", + 2901 => x"52", + 2902 => x"2e", + 2903 => x"52", + 2904 => x"f7", + 2905 => x"87", + 2906 => x"08", + 2907 => x"06", + 2908 => x"70", + 2909 => x"38", + 2910 => x"82", + 2911 => x"82", + 2912 => x"87", + 2913 => x"70", + 2914 => x"e0", + 2915 => x"2c", + 2916 => x"53", + 2917 => x"81", + 2918 => x"71", + 2919 => x"08", + 2920 => x"51", + 2921 => x"80", + 2922 => x"81", + 2923 => x"34", + 2924 => x"c0", + 2925 => x"70", + 2926 => x"52", + 2927 => x"2e", + 2928 => x"52", + 2929 => x"fb", + 2930 => x"9e", + 2931 => x"87", + 2932 => x"70", + 2933 => x"34", + 2934 => x"04", + 2935 => x"81", + 2936 => x"84", + 2937 => x"8b", + 2938 => x"73", + 2939 => x"38", + 2940 => x"51", + 2941 => x"81", + 2942 => x"84", + 2943 => x"8b", + 2944 => x"55", + 2945 => x"2e", + 2946 => x"15", + 2947 => x"8b", + 2948 => x"81", + 2949 => x"8a", + 2950 => x"8b", + 2951 => x"55", + 2952 => x"2e", + 2953 => x"15", + 2954 => x"15", + 2955 => x"f7", + 2956 => x"e9", + 2957 => x"f3", + 2958 => x"55", + 2959 => x"81", + 2960 => x"73", + 2961 => x"38", + 2962 => x"70", + 2963 => x"11", + 2964 => x"81", + 2965 => x"89", + 2966 => x"8b", + 2967 => x"73", + 2968 => x"38", + 2969 => x"51", + 2970 => x"82", + 2971 => x"54", + 2972 => x"88", + 2973 => x"fc", + 2974 => x"3f", + 2975 => x"33", + 2976 => x"2e", + 2977 => x"f8", + 2978 => x"97", + 2979 => x"f8", + 2980 => x"55", + 2981 => x"8c", + 2982 => x"33", + 2983 => x"94", + 2984 => x"3f", + 2985 => x"33", + 2986 => x"2e", + 2987 => x"f8", + 2988 => x"ef", + 2989 => x"fb", + 2990 => x"55", + 2991 => x"8c", + 2992 => x"33", + 2993 => x"d0", + 2994 => x"3f", + 2995 => x"51", + 2996 => x"82", + 2997 => x"70", + 2998 => x"52", + 2999 => x"f8", + 3000 => x"55", + 3001 => x"73", + 3002 => x"f9", + 3003 => x"ad", + 3004 => x"08", + 3005 => x"c8", + 3006 => x"3f", + 3007 => x"52", + 3008 => x"51", + 3009 => x"90", + 3010 => x"81", + 3011 => x"88", + 3012 => x"3d", + 3013 => x"3d", + 3014 => x"05", + 3015 => x"85", + 3016 => x"71", + 3017 => x"0b", + 3018 => x"05", + 3019 => x"04", + 3020 => x"51", + 3021 => x"ac", + 3022 => x"c8", + 3023 => x"3f", + 3024 => x"fa", + 3025 => x"a9", + 3026 => x"81", + 3027 => x"f7", + 3028 => x"39", + 3029 => x"51", + 3030 => x"88", + 3031 => x"e4", + 3032 => x"3f", + 3033 => x"04", + 3034 => x"0c", + 3035 => x"87", + 3036 => x"0c", + 3037 => x"0d", + 3038 => x"84", + 3039 => x"52", + 3040 => x"70", + 3041 => x"82", + 3042 => x"72", + 3043 => x"0d", + 3044 => x"0d", + 3045 => x"84", + 3046 => x"8c", + 3047 => x"80", + 3048 => x"09", + 3049 => x"80", + 3050 => x"82", + 3051 => x"73", + 3052 => x"3d", + 3053 => x"8c", + 3054 => x"c0", + 3055 => x"04", + 3056 => x"02", + 3057 => x"53", + 3058 => x"09", + 3059 => x"38", + 3060 => x"3f", + 3061 => x"08", + 3062 => x"38", + 3063 => x"08", + 3064 => x"34", + 3065 => x"08", + 3066 => x"93", + 3067 => x"39", + 3068 => x"08", + 3069 => x"38", + 3070 => x"93", + 3071 => x"71", + 3072 => x"0d", + 3073 => x"0d", + 3074 => x"33", + 3075 => x"08", + 3076 => x"d8", + 3077 => x"ff", + 3078 => x"82", + 3079 => x"84", + 3080 => x"fe", + 3081 => x"70", + 3082 => x"71", + 3083 => x"38", + 3084 => x"05", + 3085 => x"ff", + 3086 => x"33", + 3087 => x"38", + 3088 => x"04", + 3089 => x"76", + 3090 => x"08", + 3091 => x"d8", + 3092 => x"54", + 3093 => x"80", + 3094 => x"72", + 3095 => x"54", + 3096 => x"dc", + 3097 => x"52", + 3098 => x"73", + 3099 => x"0c", + 3100 => x"04", + 3101 => x"66", + 3102 => x"78", + 3103 => x"5a", + 3104 => x"80", + 3105 => x"38", + 3106 => x"88", + 3107 => x"fe", + 3108 => x"39", + 3109 => x"70", + 3110 => x"33", + 3111 => x"75", + 3112 => x"81", + 3113 => x"81", + 3114 => x"05", + 3115 => x"5d", + 3116 => x"ad", + 3117 => x"06", + 3118 => x"79", + 3119 => x"5b", + 3120 => x"75", + 3121 => x"81", + 3122 => x"7b", + 3123 => x"08", + 3124 => x"05", + 3125 => x"5c", + 3126 => x"39", + 3127 => x"72", + 3128 => x"38", + 3129 => x"16", + 3130 => x"70", + 3131 => x"33", + 3132 => x"57", + 3133 => x"27", + 3134 => x"80", + 3135 => x"30", + 3136 => x"80", + 3137 => x"cc", + 3138 => x"70", + 3139 => x"25", + 3140 => x"59", + 3141 => x"54", + 3142 => x"8c", + 3143 => x"07", + 3144 => x"05", + 3145 => x"5d", + 3146 => x"83", + 3147 => x"55", + 3148 => x"27", + 3149 => x"16", + 3150 => x"06", + 3151 => x"be", + 3152 => x"96", + 3153 => x"38", + 3154 => x"81", + 3155 => x"53", + 3156 => x"7b", + 3157 => x"08", + 3158 => x"80", + 3159 => x"54", + 3160 => x"8d", + 3161 => x"70", + 3162 => x"51", + 3163 => x"f5", + 3164 => x"2a", + 3165 => x"51", + 3166 => x"38", + 3167 => x"55", + 3168 => x"27", + 3169 => x"81", + 3170 => x"56", + 3171 => x"b0", + 3172 => x"38", + 3173 => x"55", + 3174 => x"26", + 3175 => x"51", + 3176 => x"73", + 3177 => x"53", + 3178 => x"fd", + 3179 => x"51", + 3180 => x"73", + 3181 => x"53", + 3182 => x"f2", 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x"e0", + 3242 => x"73", + 3243 => x"58", + 3244 => x"06", + 3245 => x"55", + 3246 => x"a0", + 3247 => x"2a", + 3248 => x"51", + 3249 => x"38", + 3250 => x"55", + 3251 => x"27", + 3252 => x"81", + 3253 => x"56", + 3254 => x"e4", + 3255 => x"38", + 3256 => x"55", + 3257 => x"26", + 3258 => x"18", + 3259 => x"05", + 3260 => x"53", + 3261 => x"c8", + 3262 => x"38", + 3263 => x"55", + 3264 => x"27", + 3265 => x"a0", + 3266 => x"3f", + 3267 => x"55", + 3268 => x"26", + 3269 => x"e3", + 3270 => x"0d", + 3271 => x"0d", + 3272 => x"70", + 3273 => x"08", + 3274 => x"51", + 3275 => x"85", + 3276 => x"fe", + 3277 => x"82", + 3278 => x"85", + 3279 => x"52", + 3280 => x"b0", + 3281 => x"e0", + 3282 => x"73", + 3283 => x"82", + 3284 => x"84", + 3285 => x"fd", + 3286 => x"93", + 3287 => x"82", + 3288 => x"87", + 3289 => x"53", + 3290 => x"fa", + 3291 => x"82", + 3292 => x"85", + 3293 => x"fa", + 3294 => x"7a", + 3295 => x"53", + 3296 => x"08", + 3297 => x"fa", + 3298 => x"73", + 3299 => x"39", + 3300 => x"93", + 3301 => x"71", + 3302 => x"c8", + 3303 => x"06", + 3304 => x"2e", + 3305 => x"8d", + 3306 => x"38", + 3307 => x"70", + 3308 => x"70", + 3309 => x"2a", + 3310 => x"06", + 3311 => x"53", + 3312 => x"8e", + 3313 => x"74", + 3314 => x"52", + 3315 => x"3f", + 3316 => x"74", + 3317 => x"38", + 3318 => x"74", + 3319 => x"b2", + 3320 => x"52", + 3321 => x"81", + 3322 => x"ff", + 3323 => x"f7", + 3324 => x"9e", + 3325 => x"52", + 3326 => x"8a", + 3327 => x"3f", + 3328 => x"82", + 3329 => x"88", + 3330 => x"fe", + 3331 => x"93", + 3332 => x"82", + 3333 => x"77", + 3334 => x"53", + 3335 => x"72", + 3336 => x"0c", + 3337 => x"04", + 3338 => x"7a", + 3339 => x"80", + 3340 => x"75", + 3341 => x"56", + 3342 => x"a0", + 3343 => x"06", + 3344 => x"08", + 3345 => x"0c", + 3346 => x"33", + 3347 => x"a0", + 3348 => x"73", + 3349 => x"81", + 3350 => x"81", + 3351 => x"76", + 3352 => x"70", + 3353 => x"58", + 3354 => x"09", + 3355 => x"d3", + 3356 => x"81", + 3357 => x"74", + 3358 => x"55", + 3359 => x"e2", + 3360 => x"73", + 3361 => x"09", + 3362 => x"38", + 3363 => x"14", + 3364 => x"08", + 3365 => x"54", + 3366 => x"39", + 3367 => x"81", + 3368 => x"75", + 3369 => x"56", + 3370 => x"39", + 3371 => x"74", + 3372 => x"38", + 3373 => x"80", + 3374 => x"89", + 3375 => x"38", + 3376 => x"d0", + 3377 => x"56", + 3378 => x"80", + 3379 => x"39", + 3380 => x"e1", + 3381 => x"80", + 3382 => x"57", + 3383 => x"74", + 3384 => x"38", + 3385 => x"27", + 3386 => x"14", + 3387 => x"06", + 3388 => x"14", + 3389 => x"06", + 3390 => x"74", + 3391 => x"f9", + 3392 => x"ff", + 3393 => x"89", + 3394 => x"38", + 3395 => x"c5", + 3396 => x"29", + 3397 => x"81", + 3398 => x"75", + 3399 => x"56", + 3400 => x"a0", + 3401 => x"38", + 3402 => x"84", + 3403 => x"56", + 3404 => x"81", + 3405 => x"93", + 3406 => x"3d", + 3407 => x"3d", + 3408 => x"5a", + 3409 => x"7a", + 3410 => x"70", + 3411 => x"58", + 3412 => x"09", + 3413 => x"38", + 3414 => x"05", + 3415 => x"08", + 3416 => x"53", + 3417 => x"f0", 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x"04", + 3477 => x"02", + 3478 => x"51", + 3479 => x"72", + 3480 => x"82", + 3481 => x"33", + 3482 => x"93", + 3483 => x"3d", + 3484 => x"3d", + 3485 => x"05", + 3486 => x"05", + 3487 => x"55", + 3488 => x"72", + 3489 => x"ed", + 3490 => x"29", + 3491 => x"8c", + 3492 => x"52", + 3493 => x"84", + 3494 => x"52", + 3495 => x"72", + 3496 => x"c0", + 3497 => x"51", + 3498 => x"85", + 3499 => x"98", + 3500 => x"52", + 3501 => x"8c", + 3502 => x"70", + 3503 => x"51", + 3504 => x"87", + 3505 => x"51", + 3506 => x"72", + 3507 => x"c0", + 3508 => x"70", + 3509 => x"80", + 3510 => x"71", + 3511 => x"c0", + 3512 => x"51", + 3513 => x"87", + 3514 => x"8c", + 3515 => x"82", + 3516 => x"33", + 3517 => x"93", + 3518 => x"3d", + 3519 => x"3d", + 3520 => x"65", + 3521 => x"80", + 3522 => x"56", + 3523 => x"83", + 3524 => x"fe", + 3525 => x"93", + 3526 => x"06", + 3527 => x"71", + 3528 => x"80", + 3529 => x"87", + 3530 => x"73", + 3531 => x"c0", + 3532 => x"87", + 3533 => x"12", + 3534 => x"57", + 3535 => x"76", + 3536 => x"92", + 3537 => x"71", + 3538 => x"75", + 3539 => x"70", + 3540 => x"81", + 3541 => x"54", + 3542 => x"8e", + 3543 => x"52", + 3544 => x"81", + 3545 => x"81", + 3546 => x"a2", + 3547 => x"80", + 3548 => x"75", + 3549 => x"d5", + 3550 => x"52", + 3551 => x"87", + 3552 => x"80", + 3553 => x"81", + 3554 => x"c0", + 3555 => x"53", + 3556 => x"82", + 3557 => x"71", + 3558 => x"1b", + 3559 => x"84", + 3560 => x"1e", + 3561 => x"06", + 3562 => x"7a", + 3563 => x"38", + 3564 => x"80", + 3565 => x"87", + 3566 => x"26", + 3567 => x"73", + 3568 => x"06", + 3569 => x"2e", + 3570 => x"52", + 3571 => x"82", + 3572 => x"90", + 3573 => x"f3", + 3574 => x"62", + 3575 => x"05", + 3576 => x"56", + 3577 => x"83", + 3578 => x"fc", + 3579 => x"93", + 3580 => x"06", + 3581 => x"71", + 3582 => x"80", + 3583 => x"98", + 3584 => x"2b", + 3585 => x"8c", + 3586 => x"92", + 3587 => x"41", + 3588 => x"56", + 3589 => x"87", + 3590 => x"19", + 3591 => x"52", + 3592 => x"80", + 3593 => x"70", + 3594 => x"81", + 3595 => x"54", + 3596 => x"8c", + 3597 => x"81", + 3598 => x"78", + 3599 => x"53", + 3600 => x"70", + 3601 => x"52", + 3602 => x"87", + 3603 => x"52", + 3604 => x"75", + 3605 => x"80", + 3606 => x"72", + 3607 => x"99", + 3608 => x"0c", + 3609 => x"8c", + 3610 => x"08", + 3611 => x"51", + 3612 => x"38", + 3613 => x"8d", + 3614 => x"70", + 3615 => x"84", + 3616 => x"5d", + 3617 => x"2e", + 3618 => x"fc", + 3619 => x"52", + 3620 => x"7d", + 3621 => x"fc", + 3622 => x"80", + 3623 => x"71", + 3624 => x"38", + 3625 => x"54", + 3626 => x"c8", + 3627 => x"0d", + 3628 => x"0d", + 3629 => x"05", + 3630 => x"02", + 3631 => x"05", + 3632 => x"55", + 3633 => x"8c", + 3634 => x"c8", + 3635 => x"52", + 3636 => x"bc", + 3637 => x"72", + 3638 => x"38", + 3639 => x"88", + 3640 => x"2e", + 3641 => x"39", + 3642 => x"9a", + 3643 => x"74", + 3644 => x"c0", + 3645 => x"70", + 3646 => x"94", + 3647 => x"0a", + 3648 => x"54", + 3649 => x"80", + 3650 => x"54", + 3651 => x"54", + 3652 => x"c8", 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x"16", + 3712 => x"52", + 3713 => x"86", + 3714 => x"2e", + 3715 => x"82", + 3716 => x"86", + 3717 => x"fe", + 3718 => x"76", + 3719 => x"54", + 3720 => x"2e", + 3721 => x"73", + 3722 => x"81", + 3723 => x"52", + 3724 => x"2e", + 3725 => x"73", + 3726 => x"06", + 3727 => x"33", + 3728 => x"0c", + 3729 => x"04", + 3730 => x"93", + 3731 => x"80", + 3732 => x"c8", + 3733 => x"3d", + 3734 => x"80", + 3735 => x"33", + 3736 => x"78", + 3737 => x"38", + 3738 => x"16", + 3739 => x"16", + 3740 => x"17", + 3741 => x"fa", + 3742 => x"93", + 3743 => x"2e", + 3744 => x"b8", + 3745 => x"c8", + 3746 => x"34", + 3747 => x"a4", + 3748 => x"55", + 3749 => x"08", + 3750 => x"82", + 3751 => x"74", + 3752 => x"81", + 3753 => x"81", + 3754 => x"08", + 3755 => x"05", + 3756 => x"81", + 3757 => x"fa", + 3758 => x"39", + 3759 => x"82", + 3760 => x"89", + 3761 => x"fa", + 3762 => x"7a", + 3763 => x"56", + 3764 => x"75", + 3765 => x"76", + 3766 => x"3f", + 3767 => x"08", + 3768 => x"c8", + 3769 => x"81", + 3770 => x"b4", + 3771 => x"17", + 3772 => x"8a", + 3773 => x"c8", + 3774 => x"85", + 3775 => x"81", + 3776 => x"18", + 3777 => x"93", + 3778 => x"3d", + 3779 => x"3d", + 3780 => x"52", + 3781 => x"3f", + 3782 => x"08", + 3783 => x"c8", + 3784 => x"38", + 3785 => x"74", + 3786 => x"81", + 3787 => x"38", + 3788 => x"59", + 3789 => x"09", + 3790 => x"e3", + 3791 => x"53", + 3792 => x"08", + 3793 => x"70", + 3794 => x"80", + 3795 => x"d5", + 3796 => x"17", + 3797 => x"3f", + 3798 => x"a4", + 3799 => x"51", + 3800 => x"86", + 3801 => x"f2", + 3802 => x"17", + 3803 => x"3f", + 3804 => x"52", + 3805 => x"51", + 3806 => x"8c", + 3807 => x"84", + 3808 => x"fb", + 3809 => x"17", + 3810 => x"70", + 3811 => x"79", + 3812 => x"52", + 3813 => x"51", + 3814 => x"77", + 3815 => x"80", + 3816 => x"81", + 3817 => x"fa", + 3818 => x"93", + 3819 => x"2e", + 3820 => x"58", + 3821 => x"c8", + 3822 => x"0d", + 3823 => x"0d", + 3824 => x"98", + 3825 => x"05", + 3826 => x"80", + 3827 => x"27", + 3828 => x"14", + 3829 => x"29", + 3830 => x"05", + 3831 => x"82", + 3832 => x"87", + 3833 => x"f9", + 3834 => x"7a", + 3835 => x"54", + 3836 => x"27", + 3837 => x"14", + 3838 => x"86", + 3839 => x"81", + 3840 => x"74", + 3841 => x"72", + 3842 => x"f5", + 3843 => x"24", + 3844 => x"81", + 3845 => x"81", + 3846 => x"83", + 3847 => x"38", + 3848 => x"74", + 3849 => x"70", + 3850 => x"16", + 3851 => x"74", + 3852 => x"93", + 3853 => x"c8", + 3854 => x"38", + 3855 => x"06", + 3856 => x"33", + 3857 => x"89", + 3858 => x"08", + 3859 => x"54", + 3860 => x"fc", + 3861 => x"93", + 3862 => x"fe", + 3863 => x"ff", + 3864 => x"11", + 3865 => x"2b", + 3866 => x"81", + 3867 => x"2a", + 3868 => x"51", + 3869 => x"e2", + 3870 => x"ff", + 3871 => x"da", + 3872 => x"2a", + 3873 => x"05", + 3874 => x"fc", + 3875 => x"93", + 3876 => x"c6", + 3877 => x"83", + 3878 => x"05", + 3879 => x"f8", + 3880 => x"93", + 3881 => x"ff", + 3882 => x"ae", + 3883 => x"2a", + 3884 => x"05", + 3885 => x"fc", + 3886 => x"93", + 3887 => x"38", + 3888 => x"83", + 3889 => x"05", + 3890 => x"f8", + 3891 => x"93", + 3892 => x"0a", + 3893 => x"39", + 3894 => x"82", + 3895 => x"89", + 3896 => x"f7", + 3897 => x"7d", + 3898 => x"55", + 3899 => x"74", + 3900 => x"38", + 3901 => x"08", + 3902 => x"38", + 3903 => x"72", + 3904 => x"a8", + 3905 => x"24", + 3906 => x"81", + 3907 => x"82", + 3908 => x"83", + 3909 => x"38", + 3910 => x"73", + 3911 => x"70", + 3912 => x"17", + 3913 => x"75", + 3914 => x"9b", + 3915 => x"c8", + 3916 => x"93", + 3917 => x"ea", + 3918 => x"ff", + 3919 => x"11", + 3920 => x"81", + 3921 => x"51", + 3922 => x"72", + 3923 => x"38", + 3924 => x"9f", + 3925 => x"33", + 3926 => x"07", + 3927 => x"78", + 3928 => x"83", + 3929 => x"89", + 3930 => x"08", + 3931 => x"51", + 3932 => x"82", + 3933 => x"57", + 3934 => x"08", + 3935 => x"78", + 3936 => x"15", + 3937 => x"81", + 3938 => x"2a", + 3939 => x"58", + 3940 => x"75", + 3941 => x"33", + 3942 => x"76", + 3943 => x"07", + 3944 => x"34", + 3945 => x"16", + 3946 => x"39", + 3947 => x"a4", + 3948 => x"52", + 3949 => x"8f", + 3950 => x"c8", + 3951 => x"93", + 3952 => x"de", + 3953 => x"ff", + 3954 => x"73", + 3955 => x"06", + 3956 => x"05", + 3957 => x"3f", + 3958 => x"16", + 3959 => x"39", + 3960 => x"a4", + 3961 => x"52", + 3962 => x"db", + 3963 => x"c8", + 3964 => x"93", + 3965 => x"38", + 3966 => x"06", + 3967 => x"83", + 3968 => x"11", + 3969 => x"54", + 3970 => x"f6", + 3971 => x"93", + 3972 => x"0a", + 3973 => x"52", + 3974 => x"dd", + 3975 => x"83", + 3976 => x"82", + 3977 => x"8b", + 3978 => x"f9", + 3979 => x"7b", + 3980 => x"58", + 3981 => x"81", + 3982 => x"38", + 3983 => x"74", + 3984 => x"82", + 3985 => x"39", + 3986 => x"aa", + 3987 => x"75", + 3988 => x"fd", + 3989 => x"93", + 3990 => x"82", + 3991 => x"80", + 3992 => x"39", + 3993 => x"ed", + 3994 => x"80", + 3995 => x"93", + 3996 => x"80", + 3997 => x"52", + 3998 => x"eb", + 3999 => x"c8", + 4000 => x"93", + 4001 => x"2e", + 4002 => x"82", + 4003 => x"81", + 4004 => x"82", + 4005 => x"ff", + 4006 => x"80", + 4007 => x"74", + 4008 => x"3f", + 4009 => x"08", + 4010 => x"15", + 4011 => x"54", + 4012 => x"74", + 4013 => x"90", + 4014 => x"05", + 4015 => x"84", + 4016 => x"07", + 4017 => x"16", + 4018 => x"98", + 4019 => x"26", + 4020 => x"80", + 4021 => x"93", + 4022 => x"3d", + 4023 => x"3d", + 4024 => x"71", + 4025 => x"5c", + 4026 => x"8c", + 4027 => x"77", + 4028 => x"38", + 4029 => x"78", + 4030 => x"81", + 4031 => x"7a", + 4032 => x"f9", + 4033 => x"55", + 4034 => x"c8", + 4035 => x"e9", + 4036 => x"c8", + 4037 => x"93", + 4038 => x"2e", + 4039 => x"82", + 4040 => x"55", + 4041 => x"82", + 4042 => x"26", + 4043 => x"7a", + 4044 => x"90", + 4045 => x"2e", + 4046 => x"80", + 4047 => x"2e", + 4048 => x"80", + 4049 => x"1b", + 4050 => x"08", + 4051 => x"38", + 4052 => x"52", + 4053 => x"8f", + 4054 => x"c8", + 4055 => x"5a", + 4056 => x"08", + 4057 => x"81", + 4058 => x"82", + 4059 => x"5a", + 4060 => x"70", + 4061 => x"07", + 4062 => x"7d", + 4063 => x"51", + 4064 => x"73", + 4065 => x"75", + 4066 => x"38", + 4067 => x"56", + 4068 => x"8a", + 4069 => x"1a", + 4070 => x"38", + 4071 => x"57", + 4072 => x"38", + 4073 => x"17", + 4074 => x"08", + 4075 => x"38", + 4076 => x"78", + 4077 => x"38", + 4078 => x"51", + 4079 => x"82", + 4080 => x"56", + 4081 => x"08", + 4082 => x"38", + 4083 => x"93", + 4084 => x"2e", + 4085 => x"86", + 4086 => x"c8", + 4087 => x"ff", + 4088 => x"70", + 4089 => x"25", + 4090 => x"51", + 4091 => x"73", + 4092 => x"76", + 4093 => x"81", + 4094 => x"38", + 4095 => x"f9", + 4096 => x"76", + 4097 => x"f9", + 4098 => x"93", + 4099 => x"93", + 4100 => x"70", + 4101 => x"08", + 4102 => x"7d", + 4103 => x"07", + 4104 => x"06", + 4105 => x"56", + 4106 => x"2e", + 4107 => x"53", + 4108 => x"51", + 4109 => x"82", + 4110 => x"56", + 4111 => x"76", + 4112 => x"98", + 4113 => x"05", + 4114 => x"08", + 4115 => x"38", + 4116 => x"ff", + 4117 => x"0c", + 4118 => x"81", + 4119 => x"84", + 4120 => x"39", + 4121 => x"81", + 4122 => x"89", + 4123 => x"89", + 4124 => x"85", + 4125 => x"76", + 4126 => x"93", + 4127 => x"3d", + 4128 => x"3d", + 4129 => x"52", + 4130 => x"3f", + 4131 => x"93", + 4132 => x"db", + 4133 => x"76", + 4134 => x"3f", + 4135 => x"08", + 4136 => x"08", + 4137 => x"5a", + 4138 => x"80", + 4139 => x"70", + 4140 => x"98", + 4141 => x"81", + 4142 => x"84", + 4143 => x"56", + 4144 => x"55", + 4145 => x"97", + 4146 => x"75", + 4147 => x"52", + 4148 => x"51", + 4149 => x"82", + 4150 => x"80", + 4151 => x"80", + 4152 => x"22", + 4153 => x"76", + 4154 => x"81", + 4155 => x"74", + 4156 => x"0c", + 4157 => x"04", + 4158 => x"7a", + 4159 => x"58", + 4160 => x"f0", + 4161 => x"8a", + 4162 => x"06", + 4163 => x"2e", + 4164 => x"58", + 4165 => x"74", + 4166 => x"88", + 4167 => x"73", + 4168 => x"33", + 4169 => x"27", + 4170 => x"16", + 4171 => x"9b", + 4172 => x"2a", + 4173 => x"88", + 4174 => x"58", + 4175 => x"81", + 4176 => x"16", + 4177 => x"0c", + 4178 => x"8a", + 4179 => x"89", + 4180 => x"72", + 4181 => x"38", + 4182 => x"51", + 4183 => x"82", + 4184 => x"54", + 4185 => x"08", + 4186 => x"38", + 4187 => x"93", + 4188 => x"8b", + 4189 => x"08", + 4190 => x"08", + 4191 => x"82", + 4192 => x"39", + 4193 => x"55", + 4194 => x"cc", + 4195 => x"75", + 4196 => x"3f", + 4197 => x"08", + 4198 => x"73", + 4199 => x"82", + 4200 => x"08", + 4201 => x"38", + 4202 => x"58", + 4203 => x"89", + 4204 => x"08", + 4205 => x"0c", + 4206 => x"06", + 4207 => x"9c", + 4208 => x"58", + 4209 => x"c8", + 4210 => x"0d", + 4211 => x"0d", + 4212 => x"08", + 4213 => x"a0", + 4214 => x"59", + 4215 => x"0a", + 4216 => x"38", + 4217 => x"16", + 4218 => x"98", + 4219 => x"2e", + 4220 => x"75", + 4221 => x"54", + 4222 => x"38", + 4223 => x"81", + 4224 => x"0c", + 4225 => x"98", + 4226 => x"2a", + 4227 => x"59", + 4228 => x"26", + 4229 => x"73", + 4230 => x"84", + 4231 => x"39", + 4232 => x"ff", + 4233 => x"2a", + 4234 => x"72", + 4235 => x"94", + 4236 => x"74", + 4237 => x"3f", + 4238 => x"08", + 4239 => x"81", + 4240 => x"c8", + 4241 => x"84", + 4242 => x"82", + 4243 => x"ff", + 4244 => x"38", + 4245 => x"82", + 4246 => x"26", + 4247 => x"77", + 4248 => x"98", + 4249 => x"53", + 4250 => x"94", + 4251 => x"74", + 4252 => x"3f", + 4253 => x"08", + 4254 => x"82", + 4255 => x"80", + 4256 => x"38", + 4257 => x"93", + 4258 => x"2e", + 4259 => x"53", + 4260 => x"08", + 4261 => x"38", + 4262 => x"08", + 4263 => x"fb", + 4264 => x"53", + 4265 => x"08", + 4266 => x"94", + 4267 => x"52", + 4268 => x"89", + 4269 => x"c8", + 4270 => x"0c", + 4271 => x"0c", + 4272 => x"06", + 4273 => x"9c", + 4274 => x"53", + 4275 => x"c8", + 4276 => x"0d", + 4277 => x"0d", + 4278 => x"08", + 4279 => x"80", + 4280 => x"fc", + 4281 => x"93", + 4282 => x"82", + 4283 => x"80", + 4284 => x"93", + 4285 => x"98", + 4286 => x"77", + 4287 => x"3f", + 4288 => x"08", + 4289 => x"c8", + 4290 => x"38", + 4291 => x"08", + 4292 => x"70", + 4293 => x"55", + 4294 => x"2e", + 4295 => x"83", + 4296 => x"72", + 4297 => x"25", + 4298 => x"53", + 4299 => x"8b", + 4300 => x"57", + 4301 => x"9a", + 4302 => x"80", + 4303 => x"75", + 4304 => x"3f", + 4305 => x"08", + 4306 => x"c8", + 4307 => x"ff", + 4308 => x"84", + 4309 => x"06", + 4310 => x"54", + 4311 => x"c8", + 4312 => x"0d", + 4313 => x"0d", + 4314 => x"52", + 4315 => x"3f", + 4316 => x"08", + 4317 => x"06", + 4318 => x"51", + 4319 => x"83", + 4320 => x"06", + 4321 => x"14", + 4322 => x"3f", + 4323 => x"08", + 4324 => x"07", + 4325 => x"93", + 4326 => x"3d", + 4327 => x"3d", + 4328 => x"70", + 4329 => x"06", + 4330 => x"53", + 4331 => x"ab", + 4332 => x"33", + 4333 => x"83", + 4334 => x"06", + 4335 => x"90", + 4336 => x"15", + 4337 => x"3f", + 4338 => x"04", + 4339 => x"7b", + 4340 => x"84", + 4341 => x"58", + 4342 => x"80", + 4343 => x"38", + 4344 => x"52", + 4345 => x"df", + 4346 => x"c8", + 4347 => x"93", + 4348 => x"f1", + 4349 => x"08", + 4350 => x"53", + 4351 => x"84", + 4352 => x"39", + 4353 => x"8b", + 4354 => x"bf", + 4355 => x"ff", + 4356 => x"51", + 4357 => x"17", + 4358 => x"e5", + 4359 => x"76", + 4360 => x"30", + 4361 => x"9f", + 4362 => x"55", + 4363 => x"80", + 4364 => x"76", + 4365 => x"38", + 4366 => x"06", + 4367 => x"88", + 4368 => x"06", + 4369 => x"54", + 4370 => x"99", + 4371 => x"75", + 4372 => x"3f", + 4373 => x"08", + 4374 => x"c8", + 4375 => x"98", + 4376 => x"fc", + 4377 => x"2e", + 4378 => x"0b", + 4379 => x"77", + 4380 => x"0c", + 4381 => x"04", + 4382 => x"7a", + 4383 => x"56", + 4384 => x"51", + 4385 => x"82", + 4386 => x"54", + 4387 => x"08", + 4388 => x"86", + 4389 => x"80", + 4390 => x"16", + 4391 => x"51", + 4392 => x"82", + 4393 => x"57", + 4394 => x"08", + 4395 => x"9c", + 4396 => x"33", + 4397 => x"80", + 4398 => x"9c", + 4399 => x"11", + 4400 => x"55", + 4401 => x"17", + 4402 => x"33", + 4403 => x"70", + 4404 => x"55", + 4405 => x"38", + 4406 => x"16", + 4407 => x"ea", + 4408 => x"93", + 4409 => x"2e", + 4410 => x"52", + 4411 => x"dd", + 4412 => x"c8", + 4413 => x"93", + 4414 => x"2e", + 4415 => x"76", + 4416 => x"93", + 4417 => x"3d", + 4418 => x"3d", + 4419 => x"08", + 4420 => x"52", + 4421 => x"bd", + 4422 => x"c8", + 4423 => x"93", + 4424 => x"38", + 4425 => x"52", + 4426 => x"9b", + 4427 => x"c8", + 4428 => x"93", + 4429 => x"38", + 4430 => x"93", + 4431 => x"9c", + 4432 => x"e9", + 4433 => x"53", + 4434 => x"9c", + 4435 => x"e8", + 4436 => x"0b", + 4437 => x"74", + 4438 => x"0c", + 4439 => x"04", + 4440 => x"76", + 4441 => x"12", + 4442 => x"53", + 4443 => x"d7", + 4444 => x"c8", + 4445 => x"93", + 4446 => x"38", + 4447 => x"53", + 4448 => x"81", + 4449 => x"34", + 4450 => x"c8", + 4451 => x"0d", + 4452 => x"0d", + 4453 => x"57", + 4454 => x"17", + 4455 => x"08", + 4456 => x"89", + 4457 => x"55", + 4458 => x"08", + 4459 => x"81", + 4460 => x"52", + 4461 => x"ad", + 4462 => x"2e", + 4463 => x"84", + 4464 => x"53", + 4465 => x"09", + 4466 => x"38", + 4467 => x"05", + 4468 => x"81", + 4469 => x"15", + 4470 => x"88", + 4471 => x"81", + 4472 => x"15", + 4473 => x"27", + 4474 => x"15", + 4475 => x"80", + 4476 => x"34", + 4477 => x"52", + 4478 => x"88", + 4479 => x"17", + 4480 => x"51", + 4481 => x"82", + 4482 => x"76", + 4483 => x"08", + 4484 => x"e6", + 4485 => x"93", + 4486 => x"17", + 4487 => x"08", + 4488 => x"e5", + 4489 => x"93", + 4490 => x"17", + 4491 => x"0d", + 4492 => x"0d", + 4493 => x"7f", + 4494 => x"5a", + 4495 => x"a0", + 4496 => x"e7", + 4497 => x"70", + 4498 => x"79", + 4499 => x"73", + 4500 => x"81", + 4501 => x"38", + 4502 => x"33", + 4503 => x"ae", + 4504 => x"70", + 4505 => x"82", + 4506 => x"51", + 4507 => x"54", + 4508 => x"7a", + 4509 => x"74", + 4510 => x"58", + 4511 => x"af", + 4512 => x"77", + 4513 => x"70", + 4514 => x"06", + 4515 => x"51", + 4516 => x"74", + 4517 => x"38", + 4518 => x"a0", + 4519 => x"38", + 4520 => x"0c", + 4521 => x"76", + 4522 => x"a0", + 4523 => x"1c", + 4524 => x"82", + 4525 => x"17", + 4526 => x"19", + 4527 => x"a0", + 4528 => x"8c", + 4529 => x"32", + 4530 => x"80", + 4531 => x"30", + 4532 => x"71", + 4533 => x"53", + 4534 => x"55", + 4535 => x"b5", + 4536 => x"81", + 4537 => x"77", + 4538 => x"51", + 4539 => x"af", + 4540 => x"06", + 4541 => x"5a", + 4542 => x"70", + 4543 => x"55", + 4544 => x"2e", + 4545 => x"83", + 4546 => x"79", + 4547 => x"73", + 4548 => x"bc", + 4549 => x"32", + 4550 => x"80", + 4551 => x"27", + 4552 => x"54", + 4553 => x"a2", + 4554 => x"32", + 4555 => x"ae", + 4556 => x"72", + 4557 => x"9f", + 4558 => x"51", + 4559 => x"74", + 4560 => x"88", + 4561 => x"fe", + 4562 => x"98", + 4563 => x"80", + 4564 => x"75", + 4565 => x"81", + 4566 => x"33", + 4567 => x"51", + 4568 => x"82", + 4569 => x"80", + 4570 => x"78", + 4571 => x"81", + 4572 => x"59", + 4573 => x"d7", + 4574 => x"c8", + 4575 => x"89", + 4576 => x"54", + 4577 => x"86", + 4578 => x"80", + 4579 => x"18", + 4580 => x"34", + 4581 => x"11", + 4582 => x"74", + 4583 => x"58", + 4584 => x"75", + 4585 => x"f0", + 4586 => x"3f", + 4587 => x"08", + 4588 => x"ff", + 4589 => x"73", + 4590 => x"38", + 4591 => x"81", + 4592 => x"54", + 4593 => x"75", + 4594 => x"18", + 4595 => x"39", + 4596 => x"0c", + 4597 => x"80", + 4598 => x"7a", + 4599 => x"81", + 4600 => x"81", + 4601 => x"85", + 4602 => x"54", + 4603 => x"8d", + 4604 => x"86", + 4605 => x"86", + 4606 => x"80", + 4607 => x"1c", + 4608 => x"73", + 4609 => x"0c", + 4610 => x"04", + 4611 => x"78", + 4612 => x"56", + 4613 => x"33", + 4614 => x"72", + 4615 => x"38", + 4616 => x"7a", + 4617 => x"54", + 4618 => x"dc", + 4619 => x"81", + 4620 => x"06", + 4621 => x"2e", + 4622 => x"17", + 4623 => x"0c", + 4624 => x"1a", + 4625 => x"70", + 4626 => x"55", + 4627 => x"09", + 4628 => x"38", + 4629 => x"7a", + 4630 => x"54", + 4631 => x"dc", + 4632 => x"06", + 4633 => x"54", + 4634 => x"53", + 4635 => x"80", + 4636 => x"0c", + 4637 => x"51", + 4638 => x"26", + 4639 => x"80", + 4640 => x"34", + 4641 => x"51", + 4642 => x"82", + 4643 => x"55", + 4644 => x"85", + 4645 => x"39", + 4646 => x"05", + 4647 => x"fb", + 4648 => x"93", + 4649 => x"82", + 4650 => x"81", + 4651 => x"51", + 4652 => x"82", + 4653 => x"ab", + 4654 => x"55", + 4655 => x"08", + 4656 => x"c2", + 4657 => x"c8", + 4658 => x"09", + 4659 => x"ec", + 4660 => x"2a", + 4661 => x"51", + 4662 => x"2e", + 4663 => x"82", + 4664 => x"06", + 4665 => x"80", + 4666 => x"38", + 4667 => x"ab", + 4668 => x"55", + 4669 => x"73", + 4670 => x"81", + 4671 => x"72", + 4672 => x"55", + 4673 => x"82", + 4674 => x"06", + 4675 => x"ac", + 4676 => x"33", + 4677 => x"70", + 4678 => x"54", + 4679 => x"2e", + 4680 => x"90", + 4681 => x"ff", + 4682 => x"05", + 4683 => x"f4", + 4684 => x"93", + 4685 => x"17", + 4686 => x"39", + 4687 => x"c8", + 4688 => x"0d", + 4689 => x"0d", + 4690 => x"79", + 4691 => x"54", + 4692 => x"74", + 4693 => x"d0", + 4694 => x"81", + 4695 => x"70", + 4696 => x"30", + 4697 => x"71", + 4698 => x"51", + 4699 => x"70", + 4700 => x"ba", + 4701 => x"06", + 4702 => x"74", + 4703 => x"52", + 4704 => x"26", + 4705 => x"15", + 4706 => x"06", + 4707 => x"59", + 4708 => x"2e", + 4709 => x"80", + 4710 => x"e8", + 4711 => x"10", + 4712 => x"08", + 4713 => x"57", + 4714 => x"81", + 4715 => x"75", + 4716 => x"57", + 4717 => x"12", + 4718 => x"70", + 4719 => x"38", + 4720 => x"81", + 4721 => x"51", + 4722 => x"51", + 4723 => x"89", + 4724 => x"70", + 4725 => x"54", + 4726 => x"74", + 4727 => x"30", + 4728 => x"80", + 4729 => x"2a", + 4730 => x"53", + 4731 => x"b9", + 4732 => x"75", + 4733 => x"30", + 4734 => x"9f", + 4735 => x"2a", + 4736 => x"53", + 4737 => x"2e", + 4738 => x"18", + 4739 => x"25", + 4740 => x"8b", + 4741 => x"24", + 4742 => x"77", + 4743 => x"79", + 4744 => x"82", + 4745 => x"51", + 4746 => x"c8", + 4747 => x"0d", + 4748 => x"0d", + 4749 => x"0b", + 4750 => x"ff", + 4751 => x"0c", + 4752 => x"51", + 4753 => x"84", + 4754 => x"c8", + 4755 => x"38", + 4756 => x"51", + 4757 => x"82", + 4758 => x"83", + 4759 => x"54", + 4760 => x"82", + 4761 => x"09", + 4762 => x"e7", + 4763 => x"b4", + 4764 => x"55", + 4765 => x"2e", + 4766 => x"83", + 4767 => x"73", + 4768 => x"70", + 4769 => x"25", + 4770 => x"51", + 4771 => x"38", + 4772 => x"54", + 4773 => x"2e", + 4774 => x"b5", + 4775 => x"81", + 4776 => x"80", + 4777 => x"de", + 4778 => x"93", + 4779 => x"82", + 4780 => x"80", + 4781 => x"85", + 4782 => x"84", + 4783 => x"16", + 4784 => x"3f", + 4785 => x"08", + 4786 => x"c8", + 4787 => x"83", + 4788 => x"74", + 4789 => x"0c", + 4790 => x"04", + 4791 => x"60", + 4792 => x"80", + 4793 => x"58", + 4794 => x"0c", + 4795 => x"d5", + 4796 => x"c8", + 4797 => x"56", + 4798 => x"93", + 4799 => x"87", + 4800 => x"93", + 4801 => x"10", + 4802 => x"05", + 4803 => x"53", + 4804 => x"80", + 4805 => x"38", + 4806 => x"76", + 4807 => x"75", + 4808 => x"72", + 4809 => x"38", + 4810 => x"51", + 4811 => x"82", + 4812 => x"81", + 4813 => x"81", + 4814 => x"72", + 4815 => x"80", + 4816 => x"73", + 4817 => x"81", + 4818 => x"8a", + 4819 => x"cf", + 4820 => x"86", + 4821 => x"75", + 4822 => x"16", + 4823 => x"81", + 4824 => x"d6", + 4825 => x"93", + 4826 => x"ff", + 4827 => x"06", + 4828 => x"56", + 4829 => x"38", + 4830 => x"8f", + 4831 => x"2a", + 4832 => x"51", + 4833 => x"72", + 4834 => x"80", + 4835 => x"52", + 4836 => x"3f", + 4837 => x"08", + 4838 => x"57", + 4839 => x"09", + 4840 => x"e4", + 4841 => x"73", + 4842 => x"90", + 4843 => x"10", + 4844 => x"83", + 4845 => x"55", + 4846 => x"57", + 4847 => x"8d", + 4848 => x"16", + 4849 => x"3f", + 4850 => x"08", + 4851 => x"0c", + 4852 => x"83", + 4853 => x"38", + 4854 => x"3d", + 4855 => x"05", + 4856 => x"5b", + 4857 => x"79", + 4858 => x"38", + 4859 => x"51", + 4860 => x"82", + 4861 => x"81", + 4862 => x"81", + 4863 => x"38", + 4864 => x"83", + 4865 => x"38", + 4866 => x"84", + 4867 => x"38", + 4868 => x"81", + 4869 => x"38", + 4870 => x"d9", + 4871 => x"93", + 4872 => x"ff", + 4873 => x"8d", + 4874 => x"80", + 4875 => x"06", + 4876 => x"80", + 4877 => x"d9", + 4878 => x"93", + 4879 => x"ff", + 4880 => x"73", + 4881 => x"d8", + 4882 => x"e6", + 4883 => x"c8", + 4884 => x"9c", + 4885 => x"c4", + 4886 => x"16", + 4887 => x"15", + 4888 => x"53", + 4889 => x"81", + 4890 => x"38", + 4891 => x"74", + 4892 => x"c1", + 4893 => x"55", + 4894 => x"16", + 4895 => x"ff", + 4896 => x"72", + 4897 => x"38", + 4898 => x"06", + 4899 => x"2e", + 4900 => x"56", + 4901 => x"80", + 4902 => x"d8", + 4903 => x"93", + 4904 => x"16", + 4905 => x"c8", + 4906 => x"ff", + 4907 => x"53", + 4908 => x"83", + 4909 => x"c7", + 4910 => x"dd", + 4911 => x"c8", + 4912 => x"ff", + 4913 => x"8d", + 4914 => x"15", + 4915 => x"3f", + 4916 => x"08", + 4917 => x"15", + 4918 => x"3f", + 4919 => x"08", + 4920 => x"06", + 4921 => x"78", + 4922 => x"b3", + 4923 => x"22", + 4924 => x"84", + 4925 => x"56", + 4926 => x"73", + 4927 => x"38", + 4928 => x"52", + 4929 => x"51", + 4930 => x"3f", + 4931 => x"08", + 4932 => x"82", + 4933 => x"80", + 4934 => x"38", + 4935 => x"93", + 4936 => x"ff", + 4937 => x"26", + 4938 => x"57", + 4939 => x"f5", + 4940 => x"82", + 4941 => x"f5", + 4942 => x"81", + 4943 => x"76", + 4944 => x"db", + 4945 => x"98", + 4946 => x"a0", + 4947 => x"19", + 4948 => x"77", + 4949 => x"0c", + 4950 => x"09", + 4951 => x"38", + 4952 => x"51", + 4953 => x"82", + 4954 => x"83", + 4955 => x"53", + 4956 => x"82", + 4957 => x"15", + 4958 => x"56", + 4959 => x"38", + 4960 => x"51", + 4961 => x"82", + 4962 => x"a8", + 4963 => x"15", + 4964 => x"53", + 4965 => x"15", + 4966 => x"56", + 4967 => x"81", + 4968 => x"15", + 4969 => x"16", + 4970 => x"2e", + 4971 => x"88", + 4972 => x"08", + 4973 => x"39", + 4974 => x"10", + 4975 => x"05", + 4976 => x"98", + 4977 => x"06", + 4978 => x"83", + 4979 => x"2a", + 4980 => x"72", + 4981 => x"26", + 4982 => x"ff", + 4983 => x"0c", + 4984 => x"16", + 4985 => x"0b", + 4986 => x"76", + 4987 => x"81", + 4988 => x"38", + 4989 => x"51", + 4990 => x"82", + 4991 => x"83", + 4992 => x"53", + 4993 => x"09", + 4994 => x"f9", + 4995 => x"52", + 4996 => x"b3", + 4997 => x"c8", + 4998 => x"38", + 4999 => x"08", + 5000 => x"84", + 5001 => x"d5", + 5002 => x"93", + 5003 => x"ff", + 5004 => x"72", + 5005 => x"2e", + 5006 => x"80", + 5007 => x"15", + 5008 => x"3f", + 5009 => x"08", + 5010 => x"a4", + 5011 => x"81", + 5012 => x"84", + 5013 => x"d5", + 5014 => x"93", + 5015 => x"8a", + 5016 => x"2e", + 5017 => x"9d", + 5018 => x"15", + 5019 => x"3f", + 5020 => x"08", + 5021 => x"84", + 5022 => x"d5", + 5023 => x"93", + 5024 => x"16", + 5025 => x"34", + 5026 => x"22", + 5027 => x"72", + 5028 => x"23", + 5029 => x"23", + 5030 => x"16", + 5031 => x"75", + 5032 => x"0c", + 5033 => x"04", + 5034 => x"77", + 5035 => x"73", + 5036 => x"38", + 5037 => x"2e", + 5038 => x"08", + 5039 => x"53", + 5040 => x"a4", + 5041 => x"22", + 5042 => x"57", + 5043 => x"2e", + 5044 => x"94", + 5045 => x"33", + 5046 => x"3f", + 5047 => x"08", + 5048 => x"71", + 5049 => x"55", + 5050 => x"73", + 5051 => x"06", + 5052 => x"08", + 5053 => x"71", + 5054 => x"82", + 5055 => x"87", + 5056 => x"fa", + 5057 => x"ab", + 5058 => x"58", + 5059 => x"05", + 5060 => x"b1", + 5061 => x"c8", + 5062 => x"54", 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x"39", + 5122 => x"70", + 5123 => x"55", + 5124 => x"83", + 5125 => x"75", + 5126 => x"76", + 5127 => x"81", + 5128 => x"74", + 5129 => x"a7", + 5130 => x"7a", + 5131 => x"3f", + 5132 => x"08", + 5133 => x"b2", + 5134 => x"8e", + 5135 => x"b9", + 5136 => x"a0", + 5137 => x"34", + 5138 => x"52", + 5139 => x"ce", + 5140 => x"62", + 5141 => x"d2", + 5142 => x"55", + 5143 => x"16", + 5144 => x"2e", + 5145 => x"7a", + 5146 => x"77", + 5147 => x"99", + 5148 => x"53", + 5149 => x"b3", + 5150 => x"c8", + 5151 => x"93", + 5152 => x"e6", + 5153 => x"7a", + 5154 => x"3f", + 5155 => x"08", + 5156 => x"8c", + 5157 => x"56", + 5158 => x"82", + 5159 => x"b2", + 5160 => x"84", + 5161 => x"06", + 5162 => x"74", + 5163 => x"38", + 5164 => x"39", + 5165 => x"70", + 5166 => x"55", + 5167 => x"8f", + 5168 => x"05", + 5169 => x"55", + 5170 => x"83", + 5171 => x"75", + 5172 => x"76", + 5173 => x"81", + 5174 => x"74", + 5175 => x"38", + 5176 => x"07", + 5177 => x"11", + 5178 => x"0c", + 5179 => x"0c", + 5180 => x"f6", + 5181 => x"74", + 5182 => x"3f", + 5183 => x"08", + 5184 => x"62", + 5185 => x"d0", + 5186 => x"93", + 5187 => x"19", + 5188 => x"0c", + 5189 => x"84", + 5190 => x"90", + 5191 => x"91", + 5192 => x"9c", + 5193 => x"94", + 5194 => x"80", + 5195 => x"a8", + 5196 => x"98", + 5197 => x"2a", + 5198 => x"51", + 5199 => x"2e", + 5200 => x"8c", + 5201 => x"2e", + 5202 => x"8c", + 5203 => x"19", + 5204 => x"11", + 5205 => x"2b", + 5206 => x"8c", + 5207 => x"5a", + 5208 => x"a5", + 5209 => x"77", + 5210 => x"3f", + 5211 => x"08", + 5212 => x"c8", + 5213 => x"83", + 5214 => x"76", + 5215 => x"81", + 5216 => x"81", + 5217 => x"31", + 5218 => x"70", + 5219 => x"25", + 5220 => x"26", + 5221 => x"55", + 5222 => x"76", + 5223 => x"75", + 5224 => x"78", + 5225 => x"55", + 5226 => x"b9", + 5227 => x"7a", + 5228 => x"3f", + 5229 => x"08", + 5230 => x"56", + 5231 => x"89", + 5232 => x"c8", + 5233 => x"9c", + 5234 => x"81", + 5235 => x"a8", + 5236 => x"81", + 5237 => x"55", + 5238 => x"82", + 5239 => x"80", + 5240 => x"81", + 5241 => x"2e", + 5242 => x"78", + 5243 => x"74", + 5244 => x"0c", + 5245 => x"04", + 5246 => x"7f", + 5247 => x"5f", + 5248 => x"80", + 5249 => x"3d", + 5250 => x"76", + 5251 => x"3f", + 5252 => x"08", + 5253 => x"c8", + 5254 => x"91", + 5255 => x"74", + 5256 => x"38", + 5257 => x"ae", + 5258 => x"33", + 5259 => x"87", + 5260 => x"2e", + 5261 => x"bd", + 5262 => x"91", + 5263 => x"56", + 5264 => x"81", + 5265 => x"34", + 5266 => x"8a", + 5267 => x"91", + 5268 => x"56", + 5269 => x"81", + 5270 => x"34", + 5271 => x"f6", + 5272 => x"91", + 5273 => x"56", + 5274 => x"81", + 5275 => x"34", + 5276 => x"e2", + 5277 => x"08", + 5278 => x"31", + 5279 => x"27", + 5280 => x"59", + 5281 => x"82", + 5282 => x"17", + 5283 => x"ff", + 5284 => x"74", + 5285 => x"7d", + 5286 => x"ff", + 5287 => x"2a", + 5288 => x"7a", + 5289 => x"87", + 5290 => x"08", + 5291 => x"98", + 5292 => x"76", + 5293 => x"3f", + 5294 => x"08", + 5295 => x"27", + 5296 => x"74", + 5297 => x"fb", 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x"06", + 5357 => x"52", + 5358 => x"ec", + 5359 => x"31", + 5360 => x"7e", + 5361 => x"94", + 5362 => x"94", + 5363 => x"59", + 5364 => x"38", + 5365 => x"82", + 5366 => x"8f", + 5367 => x"f3", + 5368 => x"62", + 5369 => x"5f", + 5370 => x"7d", + 5371 => x"fc", + 5372 => x"51", + 5373 => x"82", + 5374 => x"55", + 5375 => x"08", + 5376 => x"17", + 5377 => x"80", + 5378 => x"74", + 5379 => x"39", + 5380 => x"70", + 5381 => x"81", + 5382 => x"56", + 5383 => x"80", + 5384 => x"38", + 5385 => x"0b", + 5386 => x"82", + 5387 => x"39", + 5388 => x"18", + 5389 => x"83", + 5390 => x"0b", + 5391 => x"81", + 5392 => x"39", + 5393 => x"18", + 5394 => x"83", + 5395 => x"0b", + 5396 => x"81", + 5397 => x"39", + 5398 => x"18", + 5399 => x"83", + 5400 => x"17", + 5401 => x"74", + 5402 => x"27", + 5403 => x"17", + 5404 => x"78", + 5405 => x"8c", + 5406 => x"08", + 5407 => x"06", + 5408 => x"82", + 5409 => x"8a", + 5410 => x"05", + 5411 => x"06", + 5412 => x"80", + 5413 => x"96", + 5414 => x"08", + 5415 => x"38", + 5416 => x"51", + 5417 => x"82", + 5418 => x"55", + 5419 => x"17", + 5420 => x"51", + 5421 => x"82", + 5422 => x"55", + 5423 => x"82", + 5424 => x"81", + 5425 => x"38", + 5426 => x"fe", + 5427 => x"98", + 5428 => x"17", + 5429 => x"74", + 5430 => x"90", + 5431 => x"98", + 5432 => x"74", + 5433 => x"38", + 5434 => x"17", + 5435 => x"17", + 5436 => x"11", + 5437 => x"c5", + 5438 => x"93", + 5439 => x"ba", + 5440 => x"33", + 5441 => x"55", + 5442 => x"34", + 5443 => x"52", + 5444 => x"a9", + 5445 => x"c8", + 5446 => x"fe", + 5447 => x"93", + 5448 => x"79", + 5449 => x"58", + 5450 => x"80", + 5451 => x"1b", + 5452 => x"22", + 5453 => x"74", + 5454 => x"38", + 5455 => x"5a", + 5456 => x"53", + 5457 => x"81", + 5458 => x"55", + 5459 => x"82", + 5460 => x"fd", + 5461 => x"17", + 5462 => x"55", + 5463 => x"9b", + 5464 => x"53", + 5465 => x"29", + 5466 => x"17", + 5467 => x"3f", + 5468 => x"80", + 5469 => x"74", + 5470 => x"79", + 5471 => x"80", + 5472 => x"17", + 5473 => x"a1", + 5474 => x"08", + 5475 => x"27", + 5476 => x"54", + 5477 => x"17", + 5478 => x"11", + 5479 => x"c2", + 5480 => x"93", + 5481 => x"b0", + 5482 => x"18", + 5483 => x"08", + 5484 => x"84", + 5485 => x"57", + 5486 => x"27", + 5487 => x"56", + 5488 => x"52", + 5489 => x"83", + 5490 => x"a8", + 5491 => x"d8", + 5492 => x"33", + 5493 => x"55", + 5494 => x"34", + 5495 => x"7d", + 5496 => x"0c", + 5497 => x"19", + 5498 => x"94", + 5499 => x"1a", + 5500 => x"5d", + 5501 => x"27", + 5502 => x"55", + 5503 => x"0c", + 5504 => x"38", + 5505 => x"80", + 5506 => x"74", + 5507 => x"80", + 5508 => x"93", + 5509 => x"3d", + 5510 => x"3d", + 5511 => x"3d", + 5512 => x"70", + 5513 => x"80", + 5514 => x"c8", + 5515 => x"93", + 5516 => x"aa", + 5517 => x"33", + 5518 => x"70", + 5519 => x"56", + 5520 => x"2e", + 5521 => x"75", + 5522 => x"74", + 5523 => x"38", + 5524 => x"18", + 5525 => x"18", + 5526 => x"11", + 5527 => x"c2", + 5528 => x"55", + 5529 => x"08", + 5530 => x"90", + 5531 => x"ff", + 5532 => x"90", + 5533 => x"18", + 5534 => x"51", + 5535 => x"82", + 5536 => x"57", + 5537 => x"08", + 5538 => x"a4", + 5539 => x"11", + 5540 => x"56", + 5541 => x"17", + 5542 => x"08", + 5543 => x"77", + 5544 => x"fa", + 5545 => x"08", + 5546 => x"51", + 5547 => x"82", + 5548 => x"52", + 5549 => x"c5", + 5550 => x"52", + 5551 => x"c5", + 5552 => x"55", + 5553 => x"16", + 5554 => x"c8", + 5555 => x"93", + 5556 => x"19", + 5557 => x"06", + 5558 => x"90", + 5559 => x"55", + 5560 => x"c8", + 5561 => x"0d", + 5562 => x"0d", + 5563 => x"54", + 5564 => x"82", + 5565 => x"53", + 5566 => x"08", + 5567 => x"3d", + 5568 => x"73", + 5569 => x"3f", + 5570 => x"08", + 5571 => x"c8", + 5572 => x"82", + 5573 => x"74", + 5574 => x"93", + 5575 => x"3d", + 5576 => x"3d", + 5577 => x"51", + 5578 => x"8b", + 5579 => x"82", + 5580 => x"24", + 5581 => x"93", + 5582 => x"93", + 5583 => x"53", + 5584 => x"c8", + 5585 => x"0d", + 5586 => x"0d", + 5587 => x"3d", + 5588 => x"94", + 5589 => x"84", + 5590 => x"c8", + 5591 => x"93", + 5592 => x"df", + 5593 => x"63", + 5594 => x"d4", + 5595 => x"9c", + 5596 => x"c8", + 5597 => x"93", + 5598 => x"38", + 5599 => x"05", + 5600 => x"2b", + 5601 => x"80", + 5602 => x"76", + 5603 => x"0c", + 5604 => x"02", + 5605 => x"70", + 5606 => x"81", + 5607 => x"56", + 5608 => x"93", + 5609 => x"53", + 5610 => x"d7", + 5611 => x"93", + 5612 => x"15", + 5613 => x"85", + 5614 => x"2e", + 5615 => x"83", + 5616 => x"74", + 5617 => x"0c", + 5618 => x"04", + 5619 => x"a3", + 5620 => x"3d", + 5621 => x"80", + 5622 => x"53", + 5623 => x"b8", + 5624 => x"3d", + 5625 => x"3f", + 5626 => x"08", + 5627 => x"c8", + 5628 => x"38", + 5629 => x"7f", + 5630 => x"4a", + 5631 => x"59", + 5632 => x"81", + 5633 => x"3d", + 5634 => x"40", + 5635 => x"52", + 5636 => x"e4", + 5637 => x"c8", + 5638 => x"93", + 5639 => x"de", + 5640 => x"7e", + 5641 => x"3f", + 5642 => x"08", + 5643 => x"c8", + 5644 => x"38", + 5645 => x"51", + 5646 => x"82", + 5647 => x"48", + 5648 => x"51", + 5649 => x"82", + 5650 => x"57", + 5651 => x"08", + 5652 => x"7c", + 5653 => x"73", + 5654 => x"3f", + 5655 => x"08", + 5656 => x"c8", + 5657 => x"6c", + 5658 => x"d5", + 5659 => x"93", + 5660 => x"2e", + 5661 => x"52", + 5662 => x"d1", + 5663 => x"c8", + 5664 => x"93", + 5665 => x"2e", + 5666 => x"84", + 5667 => x"06", + 5668 => x"57", + 5669 => x"38", + 5670 => x"bc", + 5671 => x"05", + 5672 => x"3f", + 5673 => x"70", + 5674 => x"11", + 5675 => x"57", + 5676 => x"80", + 5677 => x"81", + 5678 => x"81", + 5679 => x"55", + 5680 => x"38", + 5681 => x"78", + 5682 => x"38", + 5683 => x"39", + 5684 => x"99", + 5685 => x"ff", + 5686 => x"08", + 5687 => x"70", + 5688 => x"56", + 5689 => x"33", + 5690 => x"eb", + 5691 => x"a3", + 5692 => x"55", + 5693 => x"34", + 5694 => x"fe", + 5695 => x"81", + 5696 => x"7c", + 5697 => x"06", + 5698 => x"19", + 5699 => x"11", + 5700 => x"74", + 5701 => x"82", + 5702 => x"70", + 5703 => x"fb", + 5704 => x"08", + 5705 => x"52", + 5706 => x"58", + 5707 => x"8d", + 5708 => x"70", + 5709 => x"51", + 5710 => x"f5", + 5711 => x"54", + 5712 => x"a5", + 5713 => x"77", + 5714 => x"38", + 5715 => x"73", + 5716 => x"81", + 5717 => x"81", + 5718 => x"78", + 5719 => x"ba", + 5720 => x"05", + 5721 => x"18", + 5722 => x"38", + 5723 => x"96", + 5724 => x"08", + 5725 => x"5a", + 5726 => x"7a", + 5727 => x"5c", + 5728 => x"26", + 5729 => x"7a", + 5730 => x"93", + 5731 => x"3d", + 5732 => x"3d", + 5733 => x"90", + 5734 => x"54", + 5735 => x"57", + 5736 => x"82", + 5737 => x"5a", + 5738 => x"08", + 5739 => x"17", + 5740 => x"80", + 5741 => x"79", + 5742 => x"39", + 5743 => x"78", + 5744 => x"90", + 5745 => x"81", + 5746 => x"06", + 5747 => x"74", + 5748 => x"17", + 5749 => x"17", + 5750 => x"70", + 5751 => x"5b", + 5752 => x"82", + 5753 => x"8a", + 5754 => x"89", + 5755 => x"55", + 5756 => x"b6", + 5757 => x"ff", + 5758 => x"96", + 5759 => x"93", + 5760 => x"17", + 5761 => x"53", + 5762 => x"96", + 5763 => x"93", + 5764 => x"26", + 5765 => x"30", + 5766 => x"18", + 5767 => x"18", + 5768 => x"18", + 5769 => x"80", + 5770 => x"17", + 5771 => x"be", + 5772 => x"76", + 5773 => x"3f", + 5774 => x"08", + 5775 => x"c8", + 5776 => x"09", + 5777 => x"38", + 5778 => x"18", + 5779 => x"82", + 5780 => x"93", + 5781 => x"2e", + 5782 => x"8b", + 5783 => x"91", + 5784 => x"55", + 5785 => x"82", + 5786 => x"88", + 5787 => x"98", + 5788 => x"80", + 5789 => x"38", + 5790 => x"80", + 5791 => x"79", + 5792 => x"08", + 5793 => x"0c", + 5794 => x"70", + 5795 => x"81", + 5796 => x"5d", + 5797 => x"2e", + 5798 => x"52", + 5799 => x"be", + 5800 => x"c8", + 5801 => x"93", + 5802 => x"38", + 5803 => x"08", + 5804 => x"75", + 5805 => x"c2", + 5806 => x"93", + 5807 => x"75", + 5808 => x"e1", + 5809 => x"27", + 5810 => x"55", + 5811 => x"76", + 5812 => x"82", + 5813 => x"34", + 5814 => x"d8", + 5815 => x"18", + 5816 => x"26", + 5817 => x"94", + 5818 => x"94", + 5819 => x"83", + 5820 => x"74", + 5821 => x"38", + 5822 => x"51", + 5823 => x"82", + 5824 => x"8b", + 5825 => x"91", + 5826 => x"55", + 5827 => x"77", + 5828 => x"93", + 5829 => x"5b", + 5830 => x"94", + 5831 => x"92", + 5832 => x"08", + 5833 => x"90", + 5834 => x"c0", + 5835 => x"90", + 5836 => x"17", + 5837 => x"06", + 5838 => x"2e", + 5839 => x"9c", + 5840 => x"2e", + 5841 => x"90", + 5842 => x"98", + 5843 => x"74", + 5844 => x"38", + 5845 => x"17", + 5846 => x"17", + 5847 => x"11", + 5848 => x"ff", + 5849 => x"82", + 5850 => x"80", + 5851 => x"81", + 5852 => x"34", + 5853 => x"39", + 5854 => x"80", + 5855 => x"74", + 5856 => x"81", + 5857 => x"a8", + 5858 => x"81", + 5859 => x"55", + 5860 => x"3f", + 5861 => x"08", + 5862 => x"38", + 5863 => x"18", + 5864 => x"90", + 5865 => x"91", + 5866 => x"55", + 5867 => x"9c", + 5868 => x"55", + 5869 => x"c8", + 5870 => x"0d", + 5871 => x"0d", + 5872 => x"54", + 5873 => x"81", + 5874 => x"53", + 5875 => x"05", + 5876 => x"84", + 5877 => x"84", + 5878 => x"c8", + 5879 => x"93", + 5880 => x"ef", + 5881 => x"0c", + 5882 => x"51", + 5883 => x"82", + 5884 => x"55", + 5885 => x"08", + 5886 => x"ab", + 5887 => x"98", + 5888 => x"80", + 5889 => x"38", + 5890 => x"70", + 5891 => x"81", + 5892 => x"57", + 5893 => x"93", + 5894 => x"08", + 5895 => x"ce", + 5896 => x"93", + 5897 => x"17", + 5898 => x"85", + 5899 => x"38", + 5900 => x"14", + 5901 => x"23", + 5902 => x"51", + 5903 => x"82", + 5904 => x"55", + 5905 => x"09", + 5906 => x"38", + 5907 => x"80", + 5908 => x"80", + 5909 => x"54", + 5910 => x"c8", + 5911 => x"0d", + 5912 => x"0d", + 5913 => x"fc", + 5914 => x"52", + 5915 => x"3f", + 5916 => x"08", + 5917 => x"c8", + 5918 => x"82", + 5919 => x"74", + 5920 => x"93", + 5921 => x"3d", + 5922 => x"3d", + 5923 => x"89", + 5924 => x"54", + 5925 => x"54", + 5926 => x"82", + 5927 => x"53", + 5928 => x"08", + 5929 => x"74", + 5930 => x"93", + 5931 => x"73", + 5932 => x"3f", + 5933 => x"08", + 5934 => x"80", + 5935 => x"ce", + 5936 => x"93", + 5937 => x"82", + 5938 => x"84", + 5939 => x"06", + 5940 => x"53", + 5941 => x"74", + 5942 => x"d1", + 5943 => x"52", + 5944 => x"e9", + 5945 => x"c8", + 5946 => x"93", + 5947 => x"2e", + 5948 => x"83", + 5949 => x"72", + 5950 => x"0c", + 5951 => x"04", + 5952 => x"64", + 5953 => x"88", + 5954 => x"95", + 5955 => x"db", + 5956 => x"93", + 5957 => x"82", + 5958 => x"b5", + 5959 => x"73", + 5960 => x"3f", + 5961 => x"08", + 5962 => x"c8", + 5963 => x"02", + 5964 => x"33", + 5965 => x"55", + 5966 => x"25", + 5967 => x"55", + 5968 => x"80", + 5969 => x"75", + 5970 => x"d4", + 5971 => x"c1", + 5972 => x"93", + 5973 => x"3d", + 5974 => x"3d", + 5975 => x"55", + 5976 => x"90", + 5977 => x"52", + 5978 => x"da", + 5979 => x"93", + 5980 => x"82", + 5981 => x"82", + 5982 => x"74", + 5983 => x"98", + 5984 => x"05", + 5985 => x"15", + 5986 => x"93", + 5987 => x"08", + 5988 => x"e9", + 5989 => x"81", + 5990 => x"59", + 5991 => x"80", + 5992 => x"56", + 5993 => x"81", + 5994 => x"06", + 5995 => x"82", + 5996 => x"75", + 5997 => x"f0", + 5998 => x"bc", + 5999 => x"93", + 6000 => x"2e", + 6001 => x"93", + 6002 => x"2e", + 6003 => x"93", + 6004 => x"70", + 6005 => x"08", + 6006 => x"78", + 6007 => x"7d", + 6008 => x"54", + 6009 => x"76", + 6010 => x"80", + 6011 => x"98", + 6012 => x"12", + 6013 => x"54", + 6014 => x"98", + 6015 => x"81", + 6016 => x"58", + 6017 => x"3f", + 6018 => x"08", + 6019 => x"c8", + 6020 => x"38", + 6021 => x"51", + 6022 => x"2e", + 6023 => x"a0", + 6024 => x"b4", + 6025 => x"b5", + 6026 => x"93", + 6027 => x"ff", + 6028 => x"30", + 6029 => x"19", + 6030 => x"59", + 6031 => x"39", + 6032 => x"05", + 6033 => x"ea", + 6034 => x"c8", + 6035 => x"06", + 6036 => x"80", + 6037 => x"18", + 6038 => x"54", + 6039 => x"06", + 6040 => x"55", + 6041 => x"38", + 6042 => x"7a", + 6043 => x"0c", + 6044 => x"11", + 6045 => x"55", + 6046 => x"16", + 6047 => x"93", + 6048 => x"3d", + 6049 => x"3d", + 6050 => x"3d", + 6051 => x"70", + 6052 => x"94", + 6053 => x"c8", + 6054 => x"93", + 6055 => x"38", + 6056 => x"57", + 6057 => x"86", + 6058 => x"81", + 6059 => x"18", + 6060 => x"2a", + 6061 => x"51", + 6062 => x"56", + 6063 => x"81", + 6064 => x"18", + 6065 => x"08", + 6066 => x"38", + 6067 => x"9a", + 6068 => x"88", + 6069 => x"77", + 6070 => x"cf", + 6071 => x"c8", + 6072 => x"0b", + 6073 => x"80", + 6074 => x"18", + 6075 => x"51", + 6076 => x"3f", + 6077 => x"08", + 6078 => x"08", + 6079 => x"30", + 6080 => x"80", + 6081 => x"58", + 6082 => x"c8", + 6083 => x"09", + 6084 => x"38", + 6085 => x"9b", + 6086 => x"75", + 6087 => x"27", + 6088 => x"18", + 6089 => x"52", + 6090 => x"bd", + 6091 => x"93", + 6092 => x"94", + 6093 => x"19", + 6094 => x"33", + 6095 => x"55", + 6096 => x"34", + 6097 => x"74", + 6098 => x"74", + 6099 => x"38", + 6100 => x"18", + 6101 => x"18", + 6102 => x"11", + 6103 => x"ff", + 6104 => x"82", + 6105 => x"80", + 6106 => x"81", + 6107 => x"90", + 6108 => x"ff", + 6109 => x"90", + 6110 => x"80", + 6111 => x"76", + 6112 => x"76", + 6113 => x"76", + 6114 => x"93", + 6115 => x"3d", + 6116 => x"3d", + 6117 => x"8c", + 6118 => x"d5", + 6119 => x"9f", + 6120 => x"05", + 6121 => x"51", + 6122 => x"82", + 6123 => x"56", + 6124 => x"08", + 6125 => x"81", + 6126 => x"ff", + 6127 => x"77", + 6128 => x"9f", + 6129 => x"51", + 6130 => x"82", + 6131 => x"81", + 6132 => x"56", + 6133 => x"3f", + 6134 => x"38", + 6135 => x"05", + 6136 => x"2a", + 6137 => x"51", + 6138 => x"80", + 6139 => x"86", + 6140 => x"95", + 6141 => x"98", + 6142 => x"f5", + 6143 => x"f7", + 6144 => x"98", + 6145 => x"73", + 6146 => x"38", + 6147 => x"39", + 6148 => x"05", + 6149 => x"54", + 6150 => x"83", + 6151 => x"75", + 6152 => x"6a", + 6153 => x"c6", + 6154 => x"93", + 6155 => x"84", + 6156 => x"05", + 6157 => x"2a", + 6158 => x"51", + 6159 => x"73", + 6160 => x"e5", + 6161 => x"9c", + 6162 => x"a5", + 6163 => x"55", + 6164 => x"08", + 6165 => x"d1", + 6166 => x"a0", + 6167 => x"91", + 6168 => x"76", + 6169 => x"a4", + 6170 => x"85", + 6171 => x"89", + 6172 => x"54", + 6173 => x"82", + 6174 => x"56", + 6175 => x"08", + 6176 => x"82", + 6177 => x"52", + 6178 => x"c0", + 6179 => x"c8", + 6180 => x"93", + 6181 => x"38", + 6182 => x"84", + 6183 => x"70", + 6184 => x"2c", + 6185 => x"56", + 6186 => x"dd", + 6187 => x"a8", + 6188 => x"bd", + 6189 => x"d4", + 6190 => x"a4", + 6191 => x"c8", + 6192 => x"c8", + 6193 => x"82", + 6194 => x"07", + 6195 => x"30", + 6196 => x"9f", + 6197 => x"52", + 6198 => x"56", + 6199 => x"9b", + 6200 => x"ac", + 6201 => x"89", + 6202 => x"76", + 6203 => x"d4", + 6204 => x"ba", + 6205 => x"93", + 6206 => x"75", + 6207 => x"51", + 6208 => x"3f", + 6209 => x"08", + 6210 => x"b0", + 6211 => x"e1", + 6212 => x"93", + 6213 => x"3d", + 6214 => x"3d", + 6215 => x"98", + 6216 => x"52", + 6217 => x"d3", + 6218 => x"93", + 6219 => x"82", + 6220 => x"82", + 6221 => x"5d", + 6222 => x"3d", + 6223 => x"cd", + 6224 => x"93", + 6225 => x"82", + 6226 => x"83", + 6227 => x"74", + 6228 => x"81", + 6229 => x"38", + 6230 => x"05", + 6231 => x"2a", + 6232 => x"51", + 6233 => x"80", + 6234 => x"86", + 6235 => x"2e", + 6236 => x"81", + 6237 => x"59", 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x"c4", + 6297 => x"b7", + 6298 => x"82", + 6299 => x"98", + 6300 => x"db", + 6301 => x"3d", + 6302 => x"cd", + 6303 => x"53", + 6304 => x"84", + 6305 => x"3d", + 6306 => x"3f", + 6307 => x"08", + 6308 => x"c8", + 6309 => x"38", + 6310 => x"3d", + 6311 => x"3d", + 6312 => x"ca", + 6313 => x"93", + 6314 => x"82", + 6315 => x"82", + 6316 => x"81", + 6317 => x"81", + 6318 => x"73", + 6319 => x"38", + 6320 => x"82", + 6321 => x"53", + 6322 => x"52", + 6323 => x"88", + 6324 => x"ad", + 6325 => x"53", + 6326 => x"05", + 6327 => x"70", + 6328 => x"ad", + 6329 => x"3d", + 6330 => x"51", + 6331 => x"82", + 6332 => x"55", + 6333 => x"08", + 6334 => x"6e", + 6335 => x"06", + 6336 => x"55", + 6337 => x"08", + 6338 => x"88", + 6339 => x"2e", + 6340 => x"81", + 6341 => x"3d", + 6342 => x"51", + 6343 => x"82", + 6344 => x"55", + 6345 => x"08", + 6346 => x"67", + 6347 => x"a7", + 6348 => x"05", + 6349 => x"51", + 6350 => x"3f", + 6351 => x"33", + 6352 => x"8b", + 6353 => x"84", + 6354 => x"06", + 6355 => x"73", + 6356 => x"a0", + 6357 => x"8b", + 6358 => x"54", + 6359 => x"15", + 6360 => x"33", + 6361 => x"70", + 6362 => x"55", + 6363 => x"2e", + 6364 => x"6d", + 6365 => x"d5", + 6366 => x"77", + 6367 => x"e5", + 6368 => x"c8", + 6369 => x"51", + 6370 => x"3f", + 6371 => x"93", + 6372 => x"2e", + 6373 => x"93", + 6374 => x"77", + 6375 => x"a7", + 6376 => x"c8", + 6377 => x"19", + 6378 => x"93", + 6379 => x"38", + 6380 => x"54", + 6381 => x"09", + 6382 => x"38", + 6383 => x"52", + 6384 => x"bf", + 6385 => x"54", + 6386 => x"15", + 6387 => x"38", + 6388 => x"05", + 6389 => x"3f", + 6390 => x"08", + 6391 => x"c8", + 6392 => x"77", + 6393 => x"a6", + 6394 => x"c8", + 6395 => x"82", + 6396 => x"a7", + 6397 => x"ed", + 6398 => x"80", + 6399 => x"02", + 6400 => x"df", + 6401 => x"57", + 6402 => x"3d", + 6403 => x"96", + 6404 => x"c8", + 6405 => x"c8", + 6406 => x"93", + 6407 => x"d4", + 6408 => x"65", + 6409 => x"d4", + 6410 => x"e0", + 6411 => x"c8", + 6412 => x"93", + 6413 => x"38", + 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x"c9", + 6532 => x"93", + 6533 => x"82", + 6534 => x"83", + 6535 => x"53", + 6536 => x"3d", + 6537 => x"51", + 6538 => x"3f", + 6539 => x"71", + 6540 => x"55", + 6541 => x"27", + 6542 => x"74", + 6543 => x"05", + 6544 => x"ff", + 6545 => x"ff", + 6546 => x"82", + 6547 => x"80", + 6548 => x"6a", + 6549 => x"53", + 6550 => x"a7", + 6551 => x"93", + 6552 => x"2e", + 6553 => x"88", + 6554 => x"6b", + 6555 => x"56", + 6556 => x"56", + 6557 => x"54", + 6558 => x"8a", + 6559 => x"70", + 6560 => x"06", + 6561 => x"ff", + 6562 => x"38", + 6563 => x"16", + 6564 => x"80", + 6565 => x"75", + 6566 => x"f8", + 6567 => x"f7", + 6568 => x"c8", + 6569 => x"81", + 6570 => x"88", + 6571 => x"26", + 6572 => x"39", + 6573 => x"86", + 6574 => x"82", + 6575 => x"ff", + 6576 => x"38", + 6577 => x"05", + 6578 => x"76", + 6579 => x"55", + 6580 => x"81", + 6581 => x"3d", + 6582 => x"bc", + 6583 => x"74", + 6584 => x"6b", + 6585 => x"56", + 6586 => x"26", + 6587 => x"89", + 6588 => x"86", + 6589 => x"e5", + 6590 => x"38", + 6591 => x"a8", + 6592 => x"05", + 6593 => x"70", + 6594 => x"56", + 6595 => x"2e", + 6596 => x"94", + 6597 => x"57", + 6598 => x"8c", + 6599 => x"70", + 6600 => x"73", + 6601 => x"38", + 6602 => x"41", + 6603 => x"3d", + 6604 => x"ff", + 6605 => x"82", + 6606 => x"54", + 6607 => x"08", + 6608 => x"81", + 6609 => x"ff", + 6610 => x"82", + 6611 => x"54", + 6612 => x"08", + 6613 => x"80", + 6614 => x"8b", + 6615 => x"ff", + 6616 => x"65", + 6617 => x"c0", + 6618 => x"65", + 6619 => x"34", + 6620 => x"0b", + 6621 => x"77", + 6622 => x"92", + 6623 => x"c8", + 6624 => x"df", + 6625 => x"c8", + 6626 => x"09", + 6627 => x"d3", + 6628 => x"76", + 6629 => x"cb", + 6630 => x"9a", + 6631 => x"51", + 6632 => x"3f", + 6633 => x"08", + 6634 => x"c8", + 6635 => x"a0", + 6636 => x"c8", + 6637 => x"51", + 6638 => x"3f", + 6639 => x"0b", + 6640 => x"8b", + 6641 => x"ff", + 6642 => x"65", + 6643 => x"d8", + 6644 => x"81", + 6645 => x"34", + 6646 => x"a6", + 6647 => x"93", + 6648 => x"73", + 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x"82", + 7237 => x"ff", + 7238 => x"87", + 7239 => x"fe", + 7240 => x"81", + 7241 => x"81", + 7242 => x"02", + 7243 => x"e3", + 7244 => x"73", + 7245 => x"07", + 7246 => x"ff", + 7247 => x"54", + 7248 => x"57", + 7249 => x"75", + 7250 => x"81", + 7251 => x"81", + 7252 => x"d8", + 7253 => x"bc", + 7254 => x"93", + 7255 => x"82", + 7256 => x"bb", + 7257 => x"c8", + 7258 => x"98", + 7259 => x"93", + 7260 => x"81", + 7261 => x"d4", + 7262 => x"84", + 7263 => x"52", + 7264 => x"51", + 7265 => x"82", + 7266 => x"58", + 7267 => x"08", + 7268 => x"80", + 7269 => x"7a", + 7270 => x"58", + 7271 => x"81", + 7272 => x"d8", + 7273 => x"c1", + 7274 => x"70", + 7275 => x"25", + 7276 => x"9f", + 7277 => x"51", + 7278 => x"74", + 7279 => x"38", + 7280 => x"53", + 7281 => x"88", + 7282 => x"51", + 7283 => x"77", + 7284 => x"93", + 7285 => x"96", + 7286 => x"f8", + 7287 => x"b7", + 7288 => x"ff", + 7289 => x"80", + 7290 => x"7a", + 7291 => x"3f", + 7292 => x"08", + 7293 => x"80", + 7294 => x"76", + 7295 => x"38", + 7296 => x"55", + 7297 => x"93", + 7298 => x"52", + 7299 => x"2d", + 7300 => x"08", + 7301 => x"75", + 7302 => x"93", + 7303 => x"3d", + 7304 => x"3d", + 7305 => x"05", + 7306 => x"ec", + 7307 => x"f4", + 7308 => x"81", + 7309 => x"8b", + 7310 => x"52", + 7311 => x"d6", + 7312 => x"80", + 7313 => x"8c", + 7314 => x"33", + 7315 => x"94", + 7316 => x"c9", + 7317 => x"2e", + 7318 => x"f6", + 7319 => x"3d", + 7320 => x"3d", + 7321 => x"96", + 7322 => x"fe", + 7323 => x"81", + 7324 => x"ff", + 7325 => x"b0", + 7326 => x"f5", + 7327 => x"fe", + 7328 => x"72", + 7329 => x"81", + 7330 => x"71", + 7331 => x"38", + 7332 => x"ee", + 7333 => x"86", + 7334 => x"f0", + 7335 => x"51", + 7336 => x"3f", + 7337 => x"70", + 7338 => x"52", + 7339 => x"95", + 7340 => x"fe", + 7341 => x"82", + 7342 => x"fe", + 7343 => x"80", + 7344 => x"af", + 7345 => x"2a", + 7346 => x"51", + 7347 => x"2e", + 7348 => x"51", + 7349 => x"3f", + 7350 => x"51", + 7351 => x"3f", + 7352 => x"ee", + 7353 => x"84", + 7354 => x"06", + 7355 => x"80", + 7356 => x"81", + 7357 => x"fb", + 7358 => x"84", + 7359 => x"f1", + 7360 => x"fe", + 7361 => x"72", + 7362 => x"81", + 7363 => x"71", + 7364 => x"38", + 7365 => x"ed", + 7366 => x"87", + 7367 => x"ef", + 7368 => x"51", + 7369 => x"3f", + 7370 => x"70", + 7371 => x"52", + 7372 => x"95", + 7373 => x"fe", + 7374 => x"82", + 7375 => x"fe", + 7376 => x"80", + 7377 => x"ab", + 7378 => x"2a", + 7379 => x"51", + 7380 => x"2e", + 7381 => x"51", + 7382 => x"3f", + 7383 => x"51", + 7384 => x"3f", + 7385 => x"ed", + 7386 => x"88", + 7387 => x"06", + 7388 => x"80", + 7389 => x"81", + 7390 => x"f7", + 7391 => x"d4", + 7392 => x"ed", + 7393 => x"fe", + 7394 => x"fe", + 7395 => x"84", + 7396 => x"fa", + 7397 => x"70", + 7398 => x"56", + 7399 => x"2e", + 7400 => x"8e", + 7401 => x"0c", + 7402 => x"53", + 7403 => x"81", + 7404 => x"75", + 7405 => x"72", + 7406 => x"38", + 7407 => x"30", + 7408 => x"75", + 7409 => x"72", + 7410 => x"33", + 7411 => x"2e", + 7412 => x"88", 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x"fe", + 7472 => x"fe", + 7473 => x"82", + 7474 => x"8c", + 7475 => x"d4", + 7476 => x"c9", + 7477 => x"39", + 7478 => x"f0", + 7479 => x"f8", + 7480 => x"fe", + 7481 => x"93", + 7482 => x"2e", + 7483 => x"60", + 7484 => x"80", + 7485 => x"05", + 7486 => x"80", + 7487 => x"51", + 7488 => x"3f", + 7489 => x"08", + 7490 => x"59", + 7491 => x"82", + 7492 => x"fe", + 7493 => x"81", + 7494 => x"39", + 7495 => x"51", + 7496 => x"3f", + 7497 => x"b4", + 7498 => x"11", + 7499 => x"05", + 7500 => x"f4", + 7501 => x"c8", + 7502 => x"fe", + 7503 => x"53", + 7504 => x"80", + 7505 => x"51", + 7506 => x"3f", + 7507 => x"08", + 7508 => x"8c", + 7509 => x"c5", + 7510 => x"39", + 7511 => x"f4", + 7512 => x"f8", + 7513 => x"fd", + 7514 => x"93", + 7515 => x"2e", + 7516 => x"89", + 7517 => x"38", + 7518 => x"f0", + 7519 => x"f8", + 7520 => x"fd", + 7521 => x"93", + 7522 => x"38", + 7523 => x"08", + 7524 => x"82", + 7525 => x"96", + 7526 => x"59", + 7527 => x"3f", + 7528 => x"33", + 7529 => x"60", + 7530 => x"82", + 7531 => x"51", + 7532 => x"3f", + 7533 => x"08", + 7534 => x"38", + 7535 => x"08", + 7536 => x"3f", + 7537 => x"82", + 7538 => x"fe", + 7539 => x"81", + 7540 => x"39", + 7541 => x"f8", + 7542 => x"e4", + 7543 => x"93", + 7544 => x"3d", + 7545 => x"52", + 7546 => x"fa", + 7547 => x"82", + 7548 => x"52", + 7549 => x"a7", + 7550 => x"c8", + 7551 => x"fc", + 7552 => x"93", + 7553 => x"f3", + 7554 => x"e5", + 7555 => x"fe", + 7556 => x"fe", + 7557 => x"82", + 7558 => x"b5", + 7559 => x"05", + 7560 => x"e4", + 7561 => x"93", + 7562 => x"3d", + 7563 => x"52", + 7564 => x"b2", + 7565 => x"c8", + 7566 => x"fe", + 7567 => x"59", + 7568 => x"3f", + 7569 => x"58", + 7570 => x"57", + 7571 => x"55", + 7572 => x"08", + 7573 => x"54", + 7574 => x"52", + 7575 => x"fb", + 7576 => x"c8", + 7577 => x"fc", + 7578 => x"93", + 7579 => x"f2", + 7580 => x"fd", + 7581 => x"98", + 7582 => x"a7", + 7583 => x"fe", + 7584 => x"fb", + 7585 => x"89", + 7586 => x"f3", + 7587 => x"51", + 7588 => x"3f", + 7589 => x"84", + 7590 => x"87", + 7591 => x"0c", + 7592 => x"0b", + 7593 => x"94", + 7594 => x"c8", + 7595 => x"f3", + 7596 => x"39", + 7597 => x"51", + 7598 => x"3f", + 7599 => x"0b", + 7600 => x"84", + 7601 => x"83", + 7602 => x"94", + 7603 => x"a1", + 7604 => x"fe", + 7605 => x"fe", + 7606 => x"fe", + 7607 => x"82", + 7608 => x"80", + 7609 => x"38", + 7610 => x"89", + 7611 => x"f8", + 7612 => x"59", + 7613 => x"3d", + 7614 => x"53", + 7615 => x"51", + 7616 => x"3f", + 7617 => x"08", + 7618 => x"e5", + 7619 => x"82", + 7620 => x"fe", + 7621 => x"60", + 7622 => x"82", + 7623 => x"5e", + 7624 => x"08", + 7625 => x"c9", + 7626 => x"c8", + 7627 => x"8a", + 7628 => x"f7", + 7629 => x"b9", + 7630 => x"c4", + 7631 => x"e3", + 7632 => x"bc", + 7633 => x"39", + 7634 => x"51", + 7635 => x"3f", + 7636 => x"a0", + 7637 => x"84", + 7638 => x"39", + 7639 => x"51", + 7640 => x"2e", + 7641 => x"7c", + 7642 => x"78", + 7643 => x"cb", + 7644 => x"fe", + 7645 => x"fe", + 7646 => x"82", + 7647 => x"82", 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x"df", + 7707 => x"df", + 7708 => x"df", + 7709 => x"df", + 7710 => x"df", + 7711 => x"df", + 7712 => x"df", + 7713 => x"df", + 7714 => x"df", + 7715 => x"df", + 7716 => x"d3", + 7717 => x"df", + 7718 => x"df", + 7719 => x"df", + 7720 => x"53", + 7721 => x"df", + 7722 => x"d7", + 7723 => x"df", + 7724 => x"df", + 7725 => x"db", + 7726 => x"bf", + 7727 => x"f3", + 7728 => x"fe", + 7729 => x"09", + 7730 => x"14", + 7731 => x"1f", + 7732 => x"2a", + 7733 => x"35", + 7734 => x"40", + 7735 => x"4b", + 7736 => x"56", + 7737 => x"61", + 7738 => x"6c", + 7739 => x"77", + 7740 => x"82", + 7741 => x"8d", + 7742 => x"97", + 7743 => x"a1", + 7744 => x"ab", + 7745 => x"b5", + 7746 => x"71", + 7747 => x"5c", + 7748 => x"b9", + 7749 => x"5c", + 7750 => x"27", + 7751 => x"5c", + 7752 => x"5c", + 7753 => x"5c", + 7754 => x"5c", + 7755 => x"5c", + 7756 => x"5c", + 7757 => x"5c", + 7758 => x"5c", + 7759 => x"5c", + 7760 => x"5c", + 7761 => x"5c", + 7762 => x"5c", + 7763 => x"5c", + 7764 => x"5c", + 7765 => x"5c", + 7766 => x"5c", + 7767 => x"5c", + 7768 => x"5c", + 7769 => x"5c", + 7770 => x"5c", + 7771 => x"5c", + 7772 => x"5c", + 7773 => x"5c", + 7774 => x"5c", + 7775 => x"5c", + 7776 => x"5c", + 7777 => x"5c", + 7778 => x"5c", + 7779 => x"5c", + 7780 => x"5c", + 7781 => x"5c", + 7782 => x"5c", + 7783 => x"5c", + 7784 => x"5c", + 7785 => x"5c", + 7786 => x"5c", + 7787 => x"5c", + 7788 => x"5c", + 7789 => x"d4", + 7790 => x"5c", + 7791 => x"5c", + 7792 => x"5c", + 7793 => x"5c", + 7794 => x"0d", + 7795 => x"5c", + 7796 => x"5c", + 7797 => x"5c", + 7798 => x"5c", + 7799 => x"5c", + 7800 => x"5c", + 7801 => x"5c", + 7802 => x"5c", + 7803 => x"5c", + 7804 => x"5c", + 7805 => x"5c", + 7806 => x"5c", + 7807 => x"5c", + 7808 => x"5c", + 7809 => x"5c", + 7810 => x"5c", + 7811 => x"5c", + 7812 => x"5c", + 7813 => x"5c", + 7814 => x"5c", + 7815 => x"5c", + 7816 => x"5c", + 7817 => x"5c", + 7818 => x"5c", + 7819 => x"5c", + 7820 => x"5c", + 7821 => x"5c", + 7822 => x"5c", + 7823 => x"5c", + 7824 => x"5c", + 7825 => x"5c", + 7826 => x"75", + 7827 => x"86", + 7828 => x"5c", + 7829 => x"5c", + 7830 => x"97", + 7831 => x"b4", + 7832 => x"5c", + 7833 => x"5c", + 7834 => x"5c", + 7835 => x"5c", + 7836 => x"5c", + 7837 => x"5c", + 7838 => x"5c", + 7839 => x"5c", + 7840 => x"5c", + 7841 => x"5c", + 7842 => x"5c", + 7843 => x"5c", + 7844 => x"5c", + 7845 => x"5c", + 7846 => x"5c", + 7847 => x"5c", + 7848 => x"5c", + 7849 => x"5c", + 7850 => x"5c", + 7851 => x"5c", + 7852 => x"5c", + 7853 => x"5c", + 7854 => x"5c", + 7855 => x"5c", + 7856 => x"5c", + 7857 => x"5c", + 7858 => x"5c", + 7859 => x"5c", + 7860 => x"5c", + 7861 => x"5c", + 7862 => x"5c", + 7863 => x"5c", + 7864 => x"5c", + 7865 => x"5c", + 7866 => x"d1", + 7867 => x"f6", + 7868 => x"5c", + 7869 => x"5c", + 7870 => x"5c", + 7871 => x"5c", + 7872 => x"5c", + 7873 => x"5c", + 7874 => x"5c", + 7875 => x"5c", + 7876 => x"39", + 7877 => x"48", + 7878 => x"5c", + 7879 => x"55", + 7880 => x"5c", + 7881 => x"71", + 7882 => x"25", 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x"20", + 7942 => x"43", + 7943 => x"20", + 7944 => x"76", + 7945 => x"73", + 7946 => x"32", + 7947 => x"0a", + 7948 => x"00", + 7949 => x"20", + 7950 => x"45", + 7951 => x"50", + 7952 => x"4f", + 7953 => x"4f", + 7954 => x"52", + 7955 => x"00", + 7956 => x"20", + 7957 => x"45", + 7958 => x"28", + 7959 => x"65", + 7960 => x"25", + 7961 => x"29", + 7962 => x"00", + 7963 => x"72", + 7964 => x"65", + 7965 => x"00", + 7966 => x"20", + 7967 => x"20", + 7968 => x"65", + 7969 => x"65", + 7970 => x"72", + 7971 => x"64", + 7972 => x"73", + 7973 => x"25", + 7974 => x"0a", + 7975 => x"00", + 7976 => x"20", + 7977 => x"20", + 7978 => x"6f", + 7979 => x"53", + 7980 => x"74", + 7981 => x"64", + 7982 => x"73", + 7983 => x"25", + 7984 => x"0a", + 7985 => x"00", + 7986 => x"20", + 7987 => x"63", + 7988 => x"74", + 7989 => x"20", + 7990 => x"72", + 7991 => x"20", + 7992 => x"20", + 7993 => x"25", + 7994 => x"0a", + 7995 => x"00", + 7996 => x"20", + 7997 => x"20", + 7998 => x"20", + 7999 => x"20", + 8000 => x"20", + 8001 => x"20", + 8002 => x"20", + 8003 => x"25", + 8004 => x"0a", + 8005 => x"00", + 8006 => x"20", + 8007 => x"74", + 8008 => x"43", + 8009 => x"6b", + 8010 => x"65", + 8011 => x"20", + 8012 => x"20", + 8013 => x"25", + 8014 => x"0a", + 8015 => x"00", + 8016 => x"6c", + 8017 => x"00", + 8018 => x"69", + 8019 => x"00", + 8020 => x"78", + 8021 => x"00", + 8022 => x"00", + 8023 => x"6d", + 8024 => x"00", + 8025 => x"6e", + 8026 => x"00", + 8027 => x"00", + 8028 => x"2c", + 8029 => x"3d", + 8030 => x"5d", + 8031 => x"00", + 8032 => x"00", + 8033 => x"33", + 8034 => x"00", + 8035 => x"00", + 8036 => x"00", + 8037 => x"00", + 8038 => x"00", + 8039 => x"00", + 8040 => x"00", + 8041 => x"00", + 8042 => x"00", + 8043 => x"00", + 8044 => x"00", + 8045 => x"4d", + 8046 => x"53", + 8047 => x"00", + 8048 => x"4e", + 8049 => x"20", + 8050 => x"46", + 8051 => x"32", + 8052 => x"00", + 8053 => x"4e", + 8054 => x"20", + 8055 => x"46", + 8056 => x"20", + 8057 => x"00", + 8058 => x"6c", + 8059 => x"00", + 8060 => x"00", + 8061 => x"00", + 8062 => x"41", + 8063 => x"80", + 8064 => x"49", + 8065 => x"8f", + 8066 => x"4f", + 8067 => x"55", + 8068 => x"9b", + 8069 => x"9f", + 8070 => x"55", + 8071 => x"a7", + 8072 => x"ab", + 8073 => x"af", + 8074 => x"b3", + 8075 => x"b7", + 8076 => x"bb", + 8077 => x"bf", + 8078 => x"c3", + 8079 => x"c7", + 8080 => x"cb", + 8081 => x"cf", + 8082 => x"d3", + 8083 => x"d7", + 8084 => x"db", + 8085 => x"df", + 8086 => x"e3", + 8087 => x"e7", + 8088 => x"eb", + 8089 => x"ef", + 8090 => x"f3", + 8091 => x"f7", + 8092 => x"fb", + 8093 => x"ff", + 8094 => x"3b", + 8095 => x"2f", + 8096 => x"3a", + 8097 => x"7c", + 8098 => x"00", + 8099 => x"04", + 8100 => x"40", + 8101 => x"00", + 8102 => x"00", + 8103 => x"02", + 8104 => x"08", + 8105 => x"20", + 8106 => x"00", + 8107 => x"31", + 8108 => x"00", + 8109 => x"31", + 8110 => x"00", + 8111 => x"41", + 8112 => x"00", + 8113 => x"4b", + 8114 => x"20", + 8115 => x"54", + 8116 => x"53", + 8117 => x"00", + 8118 => x"4b", + 8119 => x"46", + 8120 => x"20", + 8121 => x"54", + 8122 => x"53", + 8123 => x"00", + 8124 => x"45", + 8125 => x"54", + 8126 => x"43", + 8127 => x"52", + 8128 => x"00", + 8129 => x"4f", + 8130 => x"00", + 8131 => x"44", + 8132 => x"45", + 8133 => x"00", + 8134 => x"54", + 8135 => x"00", + 8136 => x"43", + 8137 => x"4f", + 8138 => x"00", + 8139 => x"43", + 8140 => x"4d", + 8141 => x"44", + 8142 => x"00", + 8143 => x"6d", + 8144 => x"00", + 8145 => x"69", + 8146 => x"00", + 8147 => x"61", + 8148 => x"00", + 8149 => x"63", + 8150 => x"00", + 8151 => x"6d", + 8152 => x"00", + 8153 => x"69", + 8154 => x"00", + 8155 => x"61", + 8156 => x"00", + 8157 => x"69", + 8158 => x"00", + 8159 => x"6c", + 8160 => x"00", + 8161 => x"6e", + 8162 => x"00", + 8163 => x"69", + 8164 => x"00", + 8165 => x"65", + 8166 => x"00", + 8167 => x"6f", + 8168 => x"00", + 8169 => x"65", + 8170 => x"00", + 8171 => x"61", + 8172 => x"00", + 8173 => x"73", + 8174 => x"74", + 8175 => x"00", + 8176 => x"69", + 8177 => x"00", + 8178 => x"75", + 8179 => x"00", + 8180 => x"6c", + 8181 => x"00", + 8182 => x"74", + 8183 => x"00", + 8184 => x"6d", + 8185 => x"00", + 8186 => x"6e", + 8187 => x"00", + 8188 => x"6c", + 8189 => x"00", + 8190 => x"64", + 8191 => x"00", + 8192 => x"61", + 8193 => x"00", + 8194 => x"72", + 8195 => x"00", + 8196 => x"74", + 8197 => x"00", + 8198 => x"00", + 8199 => x"6e", + 8200 => x"00", + 8201 => x"72", + 8202 => x"00", + 8203 => x"61", + 8204 => x"00", + 8205 => x"65", + 8206 => x"00", + 8207 => x"76", + 8208 => x"00", + 8209 => x"6d", + 8210 => x"00", + 8211 => x"00", + 8212 => x"69", + 8213 => x"00", + 8214 => x"6f", + 8215 => x"72", + 8216 => x"00", + 8217 => x"62", + 8218 => x"00", + 8219 => x"66", + 8220 => x"00", + 8221 => x"72", + 8222 => x"00", + 8223 => x"6d", + 8224 => x"00", + 8225 => x"00", + 8226 => x"00", + 8227 => x"00", + 8228 => x"00", + 8229 => x"00", + 8230 => x"00", + 8231 => x"00", + 8232 => x"00", + 8233 => x"00", + 8234 => x"79", + 8235 => x"00", + 8236 => x"65", + 8237 => x"6b", + 8238 => x"00", + 8239 => x"6c", + 8240 => x"00", + 8241 => x"00", + 8242 => x"74", + 8243 => x"00", + 8244 => x"65", + 8245 => x"00", + 8246 => x"70", + 8247 => x"00", + 8248 => x"6f", + 8249 => x"00", + 8250 => x"65", + 8251 => x"00", + 8252 => x"74", + 8253 => x"00", + 8254 => x"6b", + 8255 => x"72", + 8256 => x"00", + 8257 => x"65", + 8258 => x"6c", + 8259 => x"72", + 8260 => x"0a", + 8261 => x"00", + 8262 => x"6b", + 8263 => x"74", + 8264 => x"61", + 8265 => x"0a", + 8266 => x"00", + 8267 => x"66", + 8268 => x"20", + 8269 => x"6e", + 8270 => x"00", + 8271 => x"70", + 8272 => x"20", + 8273 => x"6e", + 8274 => x"00", + 8275 => x"61", + 8276 => x"20", + 8277 => x"65", + 8278 => x"65", + 8279 => x"00", + 8280 => x"65", + 8281 => x"64", + 8282 => x"65", + 8283 => x"00", + 8284 => x"65", + 8285 => x"72", + 8286 => x"79", + 8287 => x"69", + 8288 => x"2e", + 8289 => x"00", + 8290 => x"65", + 8291 => x"6e", + 8292 => x"20", + 8293 => x"61", + 8294 => x"2e", + 8295 => x"00", + 8296 => x"69", + 8297 => x"72", + 8298 => x"20", + 8299 => x"74", + 8300 => x"65", + 8301 => x"00", + 8302 => x"76", + 8303 => x"75", + 8304 => x"72", + 8305 => x"20", + 8306 => x"61", + 8307 => x"2e", + 8308 => x"00", + 8309 => x"6b", + 8310 => x"74", + 8311 => x"61", + 8312 => x"64", + 8313 => x"00", + 8314 => x"63", + 8315 => x"61", + 8316 => x"6c", + 8317 => x"69", + 8318 => x"79", + 8319 => x"6d", + 8320 => x"75", + 8321 => x"6f", + 8322 => x"69", + 8323 => x"0a", + 8324 => x"00", + 8325 => x"6d", + 8326 => x"61", + 8327 => x"74", + 8328 => x"0a", + 8329 => x"00", + 8330 => x"65", + 8331 => x"2c", + 8332 => x"65", + 8333 => x"69", + 8334 => x"63", + 8335 => x"65", + 8336 => x"64", + 8337 => x"00", + 8338 => x"65", + 8339 => x"20", + 8340 => x"6b", + 8341 => x"0a", + 8342 => x"00", + 8343 => x"75", + 8344 => x"63", + 8345 => x"74", + 8346 => x"6d", + 8347 => x"2e", + 8348 => x"00", + 8349 => x"20", + 8350 => x"79", + 8351 => x"65", + 8352 => x"69", + 8353 => x"2e", + 8354 => x"00", + 8355 => x"61", + 8356 => x"65", + 8357 => x"69", + 8358 => x"72", + 8359 => x"74", + 8360 => x"00", + 8361 => x"63", + 8362 => x"2e", + 8363 => x"00", + 8364 => x"6e", + 8365 => x"20", + 8366 => x"6f", + 8367 => x"00", + 8368 => x"75", + 8369 => x"74", + 8370 => x"25", + 8371 => x"74", + 8372 => x"75", + 8373 => x"74", + 8374 => x"73", + 8375 => x"0a", + 8376 => x"00", + 8377 => x"64", + 8378 => x"00", + 8379 => x"54", + 8380 => x"00", + 8381 => x"20", + 8382 => x"28", + 8383 => x"00", + 8384 => x"30", + 8385 => x"30", + 8386 => x"00", + 8387 => x"33", + 8388 => x"00", + 8389 => x"55", + 8390 => x"65", + 8391 => x"30", + 8392 => x"20", + 8393 => x"25", + 8394 => x"2a", + 8395 => x"00", + 8396 => x"54", + 8397 => x"6e", + 8398 => x"72", + 8399 => x"20", + 8400 => x"64", + 8401 => x"0a", + 8402 => x"00", + 8403 => x"65", + 8404 => x"6e", + 8405 => x"72", + 8406 => x"0a", + 8407 => x"00", + 8408 => x"20", + 8409 => x"65", + 8410 => x"70", + 8411 => x"00", + 8412 => x"54", + 8413 => x"44", + 8414 => x"74", + 8415 => x"75", + 8416 => x"00", + 8417 => x"54", + 8418 => x"52", + 8419 => x"74", + 8420 => x"75", + 8421 => x"00", + 8422 => x"54", + 8423 => x"58", + 8424 => x"74", + 8425 => x"75", + 8426 => x"00", + 8427 => x"54", + 8428 => x"58", + 8429 => x"74", + 8430 => x"75", + 8431 => x"00", + 8432 => x"54", + 8433 => x"58", + 8434 => x"74", + 8435 => x"75", + 8436 => x"00", + 8437 => x"54", + 8438 => x"58", + 8439 => x"74", + 8440 => x"75", + 8441 => x"00", + 8442 => x"74", + 8443 => x"20", + 8444 => x"74", + 8445 => x"72", + 8446 => x"0a", + 8447 => x"00", + 8448 => x"62", + 8449 => x"67", + 8450 => x"6d", + 8451 => x"2e", + 8452 => x"00", + 8453 => x"00", + 8454 => x"6c", + 8455 => x"74", + 8456 => x"6e", + 8457 => x"61", + 8458 => x"65", + 8459 => x"20", + 8460 => x"64", + 8461 => x"20", + 8462 => x"61", + 8463 => x"69", + 8464 => x"20", + 8465 => x"75", + 8466 => x"79", + 8467 => x"00", + 8468 => x"00", + 8469 => x"20", + 8470 => x"6b", + 8471 => x"21", + 8472 => x"00", + 8473 => x"74", + 8474 => x"69", + 8475 => x"2e", + 8476 => x"00", + 8477 => x"6c", + 8478 => x"74", + 8479 => x"6e", + 8480 => x"61", + 8481 => x"65", + 8482 => x"00", + 8483 => x"25", + 8484 => x"00", + 8485 => x"00", + 8486 => x"61", + 8487 => x"6e", + 8488 => x"6e", + 8489 => x"72", + 8490 => x"73", + 8491 => x"00", + 8492 => x"62", + 8493 => x"67", + 8494 => x"74", + 8495 => x"75", + 8496 => x"0a", + 8497 => x"00", + 8498 => x"61", + 8499 => x"64", + 8500 => x"72", + 8501 => x"69", + 8502 => x"00", + 8503 => x"62", + 8504 => x"67", + 8505 => x"72", + 8506 => x"69", + 8507 => x"00", + 8508 => x"63", + 8509 => x"6e", + 8510 => x"6f", + 8511 => x"40", + 8512 => x"38", + 8513 => x"2e", + 8514 => x"00", + 8515 => x"6c", + 8516 => x"20", + 8517 => x"65", + 8518 => x"25", + 8519 => x"20", + 8520 => x"0a", + 8521 => x"00", + 8522 => x"6c", + 8523 => x"74", + 8524 => x"65", + 8525 => x"6f", + 8526 => x"28", + 8527 => x"2e", + 8528 => x"00", + 8529 => x"74", + 8530 => x"69", + 8531 => x"61", + 8532 => x"69", + 8533 => x"69", + 8534 => x"2e", + 8535 => x"00", + 8536 => x"64", + 8537 => x"62", + 8538 => x"69", + 8539 => x"2e", + 8540 => x"00", + 8541 => x"00", + 8542 => x"00", + 8543 => x"5c", + 8544 => x"25", + 8545 => x"73", + 8546 => x"00", + 8547 => x"20", + 8548 => x"6d", + 8549 => x"2e", + 8550 => x"00", + 8551 => x"6e", + 8552 => x"2e", + 8553 => x"00", + 8554 => x"62", + 8555 => x"67", + 8556 => x"74", + 8557 => x"75", + 8558 => x"2e", + 8559 => x"00", + 8560 => x"00", + 8561 => x"00", + 8562 => x"ff", + 8563 => x"00", + 8564 => x"ff", + 8565 => x"00", + 8566 => x"ff", + 8567 => x"00", + 8568 => x"00", + 8569 => x"00", + 8570 => x"00", + 8571 => x"00", + 8572 => x"01", + 8573 => x"01", + 8574 => x"01", + 8575 => x"00", + 8576 => x"00", + 8577 => x"00", + 8578 => x"3c", + 8579 => x"00", + 8580 => x"00", + 8581 => x"00", + 8582 => x"44", + 8583 => x"00", + 8584 => x"00", + 8585 => x"00", + 8586 => x"4c", + 8587 => x"00", + 8588 => x"00", + 8589 => x"00", + 8590 => x"54", + 8591 => x"00", + 8592 => x"00", + 8593 => x"00", + 8594 => x"5c", + 8595 => x"00", + 8596 => x"00", + 8597 => x"00", + 8598 => x"64", + 8599 => x"00", + 8600 => x"00", + 8601 => x"00", + 8602 => x"6c", + 8603 => x"00", + 8604 => x"00", + 8605 => x"00", + 8606 => x"74", + 8607 => x"00", + 8608 => x"00", + 8609 => x"00", + 8610 => x"7c", + 8611 => x"00", + 8612 => x"00", + 8613 => x"00", + 8614 => x"84", + 8615 => x"00", + 8616 => x"00", + 8617 => x"00", + 8618 => x"8c", + 8619 => x"00", + 8620 => x"00", + 8621 => x"00", + 8622 => x"94", + 8623 => x"00", + 8624 => x"00", + 8625 => x"00", + 8626 => x"9c", + 8627 => x"00", + 8628 => x"00", + 8629 => x"00", + 8630 => x"a4", + 8631 => x"00", + 8632 => x"00", + 8633 => x"00", + 8634 => x"ac", + 8635 => x"00", + 8636 => x"00", + 8637 => x"00", + 8638 => x"b4", + 8639 => x"00", + 8640 => x"00", + 8641 => x"00", + 8642 => x"c0", + 8643 => x"00", + 8644 => x"00", + 8645 => x"00", + 8646 => x"c8", + 8647 => x"00", + 8648 => x"00", + 8649 => x"00", + 8650 => x"d0", + 8651 => x"00", + 8652 => x"00", + 8653 => x"00", + 8654 => x"d8", + 8655 => x"00", + 8656 => x"00", + 8657 => x"00", + 8658 => x"e0", + 8659 => x"00", + 8660 => x"00", + 8661 => x"00", + 8662 => x"e8", + 8663 => x"00", + 8664 => x"00", + 8665 => x"00", + 8666 => x"f0", + 8667 => x"00", + 8668 => x"00", + 8669 => x"00", + 8670 => x"f8", + 8671 => x"00", + 8672 => x"00", + 8673 => x"00", + 8674 => x"00", + 8675 => x"00", + 8676 => x"00", + 8677 => x"00", + 8678 => x"08", + 8679 => x"00", + 8680 => x"00", + 8681 => x"00", + 8682 => x"10", + 8683 => x"00", + 8684 => x"00", + 8685 => x"00", + 8686 => x"18", + 8687 => x"00", + 8688 => x"00", + 8689 => x"00", + 8690 => x"1c", + 8691 => x"00", + 8692 => x"00", + 8693 => x"00", + 8694 => x"24", + 8695 => x"00", + 8696 => x"00", + 8697 => x"00", + 8698 => x"2c", + 8699 => x"00", + 8700 => x"00", + 8701 => x"00", + 8702 => x"34", + 8703 => x"00", + 8704 => x"00", + 8705 => x"00", + 8706 => x"3c", + 8707 => x"00", + 8708 => x"00", + 8709 => x"00", + 8710 => x"44", + 8711 => x"00", + 8712 => x"00", + 8713 => x"00", + 8714 => x"4c", + 8715 => x"00", + 8716 => x"00", + 8717 => x"00", + 8718 => x"50", + 8719 => x"00", + 8720 => x"00", + 8721 => x"00", + 8722 => x"58", + 8723 => x"00", + 8724 => x"00", + 8725 => x"00", + 8726 => x"64", + 8727 => x"00", + 8728 => x"00", + 8729 => x"00", + 8730 => x"6c", + 8731 => x"00", + 8732 => x"00", + 8733 => x"00", + 8734 => x"74", + 8735 => x"00", + 8736 => x"00", + 8737 => x"00", + 8738 => x"7c", + 8739 => x"00", + 8740 => x"00", + 8741 => x"00", + 8742 => x"84", + 8743 => x"00", + 8744 => x"00", + 8745 => x"00", + 8746 => x"88", + 8747 => x"00", + 8748 => x"00", + 8749 => x"00", + 8750 => x"8c", + 8751 => x"00", + 8752 => x"00", + 8753 => x"00", + 8754 => x"90", + 8755 => x"00", + 8756 => x"00", + 8757 => x"00", + 8758 => x"94", + 8759 => x"00", + 8760 => x"00", + 8761 => x"00", + 8762 => x"98", + 8763 => x"00", + 8764 => x"00", + 8765 => x"00", + 8766 => x"9c", + 8767 => x"00", + 8768 => x"00", + 8769 => x"00", + 8770 => x"a0", + 8771 => x"00", + 8772 => x"00", + 8773 => x"00", + 8774 => x"a4", + 8775 => x"00", + 8776 => x"00", + 8777 => x"00", + 8778 => x"a8", + 8779 => x"00", + 8780 => x"00", + 8781 => x"00", + 8782 => x"b0", + 8783 => x"00", + 8784 => x"00", + 8785 => x"00", + 8786 => x"bc", + 8787 => x"00", + 8788 => x"00", + 8789 => x"00", + 8790 => x"c4", + 8791 => x"00", + 8792 => x"00", + 8793 => x"00", + 8794 => x"c8", + 8795 => x"00", + 8796 => x"00", + 8797 => x"00", + 8798 => x"d0", + 8799 => x"00", + 8800 => x"00", + 8801 => x"00", + 8802 => x"d8", + 8803 => x"00", + 8804 => x"00", + 8805 => x"00", + 8806 => x"e0", + 8807 => x"00", + 8808 => x"00", + 8809 => x"00", + 8810 => x"e8", + 8811 => x"00", + 8812 => x"00", + 8813 => x"00", + 8814 => x"f0", + 8815 => x"00", + 8816 => x"00", + 8817 => x"00", + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + 0 => x"0b", + 1 => x"00", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"8c", + 9 => x"0b", + 10 => x"80", + 11 => x"0c", + 12 => x"0c", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"06", + 17 => x"06", + 18 => x"82", + 19 => x"2a", + 20 => x"06", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"06", + 25 => x"ff", + 26 => x"09", + 27 => x"05", + 28 => x"09", + 29 => x"ff", + 30 => x"0b", + 31 => x"04", + 32 => x"81", + 33 => x"73", + 34 => x"09", + 35 => x"73", + 36 => x"81", + 37 => x"04", + 38 => x"00", + 39 => x"00", + 40 => x"24", + 41 => x"07", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"81", + 50 => x"05", + 51 => x"0a", + 52 => x"0a", + 53 => x"81", + 54 => x"53", + 55 => x"00", + 56 => x"26", + 57 => x"07", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"51", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"9f", + 89 => x"05", + 90 => x"88", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"2a", + 97 => x"06", + 98 => x"09", + 99 => x"ff", + 100 => x"53", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"53", + 105 => x"73", + 106 => x"81", + 107 => x"83", + 108 => x"07", + 109 => x"0c", + 110 => x"00", + 111 => x"00", + 112 => x"81", + 113 => x"09", + 114 => x"09", + 115 => x"06", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"81", + 121 => x"09", + 122 => x"09", + 123 => x"81", + 124 => x"04", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"81", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"09", + 137 => x"53", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"09", + 146 => x"51", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"06", + 153 => x"06", + 154 => x"83", + 155 => x"10", + 156 => x"06", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"06", + 161 => x"0b", + 162 => x"83", + 163 => x"05", + 164 => x"0b", + 165 => x"04", + 166 => x"00", + 167 => x"00", + 168 => x"8c", + 169 => x"75", + 170 => x"0b", + 171 => x"50", + 172 => x"56", + 173 => x"0c", + 174 => x"04", + 175 => x"00", + 176 => x"8c", + 177 => x"75", + 178 => x"0b", + 179 => x"50", + 180 => x"56", + 181 => x"0c", + 182 => x"04", + 183 => x"00", + 184 => x"70", + 185 => x"06", + 186 => x"ff", + 187 => x"71", + 188 => x"72", + 189 => x"05", + 190 => x"51", + 191 => x"00", + 192 => x"70", + 193 => x"06", + 194 => x"06", + 195 => x"54", + 196 => x"09", + 197 => x"ff", + 198 => x"51", + 199 => x"00", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"05", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"05", + 233 => x"05", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"05", + 249 => x"53", + 250 => x"04", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"04", + 257 => x"00", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"10", + 266 => x"00", + 267 => x"ff", + 268 => x"06", + 269 => x"83", + 270 => x"10", + 271 => x"fc", + 272 => x"51", + 273 => x"80", + 274 => x"ff", + 275 => x"06", + 276 => x"52", + 277 => x"0a", + 278 => x"38", + 279 => x"51", + 280 => x"00", + 281 => x"00", + 282 => x"ac", + 283 => x"27", + 284 => x"71", + 285 => x"53", + 286 => x"04", + 287 => x"9e", + 288 => x"08", + 289 => x"fd", + 290 => x"53", + 291 => x"05", + 292 => x"08", + 293 => x"51", + 294 => x"88", + 295 => x"0c", + 296 => x"0d", + 297 => x"94", + 298 => x"0c", + 299 => x"81", + 300 => x"8c", + 301 => x"94", + 302 => x"08", + 303 => x"3f", + 304 => x"88", + 305 => x"3d", + 306 => x"04", + 307 => x"94", + 308 => x"0d", + 309 => x"08", + 310 => x"94", + 311 => x"08", + 312 => x"38", + 313 => x"05", + 314 => x"08", + 315 => x"80", + 316 => x"f4", + 317 => x"08", + 318 => x"88", + 319 => x"94", + 320 => x"0c", + 321 => x"05", + 322 => x"fc", + 323 => x"08", + 324 => x"80", + 325 => x"94", + 326 => x"08", + 327 => x"8c", + 328 => x"0b", + 329 => x"05", + 330 => x"fc", + 331 => x"38", + 332 => x"08", + 333 => x"94", + 334 => x"08", + 335 => x"05", + 336 => x"94", + 337 => x"08", + 338 => x"88", + 339 => x"81", + 340 => x"08", + 341 => x"f8", + 342 => x"94", + 343 => x"08", + 344 => x"38", + 345 => x"05", + 346 => x"08", + 347 => x"94", + 348 => x"08", + 349 => x"54", + 350 => x"94", + 351 => x"08", + 352 => x"fb", + 353 => x"0b", + 354 => x"05", + 355 => x"88", + 356 => x"25", + 357 => x"08", + 358 => x"30", + 359 => x"05", + 360 => x"94", + 361 => x"0c", + 362 => x"05", + 363 => x"8c", + 364 => x"8c", + 365 => x"94", + 366 => x"0c", + 367 => x"08", + 368 => x"52", + 369 => x"05", + 370 => x"3f", + 371 => x"94", + 372 => x"0c", + 373 => x"fc", + 374 => x"2e", + 375 => x"08", + 376 => x"30", + 377 => x"05", + 378 => x"f8", + 379 => x"88", + 380 => x"3d", + 381 => x"04", + 382 => x"94", + 383 => x"0d", + 384 => x"08", + 385 => x"80", + 386 => x"f8", + 387 => x"08", + 388 => x"94", + 389 => x"08", + 390 => x"94", + 391 => x"08", + 392 => x"38", + 393 => x"08", + 394 => x"24", + 395 => x"08", + 396 => x"10", + 397 => x"05", + 398 => x"fc", + 399 => x"94", + 400 => x"0c", + 401 => x"08", + 402 => x"80", + 403 => x"38", + 404 => x"05", + 405 => x"88", + 406 => x"a1", + 407 => x"88", + 408 => x"08", + 409 => x"31", + 410 => x"05", + 411 => x"f8", + 412 => x"08", + 413 => x"07", + 414 => x"05", + 415 => x"fc", + 416 => x"2a", + 417 => x"05", + 418 => x"8c", + 419 => x"2a", + 420 => x"05", + 421 => x"39", + 422 => x"05", + 423 => x"8f", + 424 => x"88", + 425 => x"94", + 426 => x"0c", + 427 => x"94", + 428 => x"08", + 429 => x"f4", + 430 => x"94", + 431 => x"08", + 432 => x"3d", + 433 => x"04", + 434 => x"81", + 435 => x"c0", + 436 => x"81", + 437 => x"92", + 438 => x"0b", + 439 => x"8c", + 440 => x"92", + 441 => x"82", + 442 => x"70", + 443 => x"38", + 444 => x"8c", + 445 => x"e9", + 446 => x"92", + 447 => x"80", + 448 => x"71", + 449 => x"c0", + 450 => x"51", + 451 => x"88", + 452 => x"0b", + 453 => x"34", + 454 => x"9f", + 455 => x"0c", + 456 => x"04", + 457 => x"78", + 458 => x"58", + 459 => x"0b", + 460 => x"a8", + 461 => x"52", + 462 => x"70", + 463 => x"81", + 464 => x"38", + 465 => x"c0", + 466 => x"79", + 467 => x"80", + 468 => x"87", + 469 => x"0c", + 470 => x"8c", + 471 => x"2a", + 472 => x"51", + 473 => x"80", + 474 => x"87", + 475 => x"08", + 476 => x"06", + 477 => x"52", + 478 => x"80", + 479 => x"70", + 480 => x"38", + 481 => x"81", + 482 => x"ff", + 483 => x"15", + 484 => x"06", + 485 => x"2e", + 486 => x"c0", + 487 => x"51", + 488 => x"38", + 489 => x"8c", + 490 => x"95", + 491 => x"87", + 492 => x"0c", + 493 => x"8c", + 494 => x"06", + 495 => x"f4", + 496 => x"fc", + 497 => x"52", + 498 => x"2e", + 499 => x"8f", + 500 => x"98", + 501 => x"70", + 502 => x"81", + 503 => x"81", + 504 => x"0c", + 505 => x"04", + 506 => x"74", + 507 => x"71", + 508 => x"2b", + 509 => x"53", + 510 => x"0d", + 511 => x"0d", + 512 => x"33", + 513 => x"71", + 514 => x"88", + 515 => x"14", + 516 => x"07", + 517 => x"33", + 518 => x"0c", + 519 => x"56", + 520 => x"3d", + 521 => x"3d", + 522 => x"0b", + 523 => x"08", + 524 => x"77", + 525 => x"38", + 526 => x"08", + 527 => x"38", + 528 => x"74", + 529 => x"38", + 530 => x"ae", + 531 => x"39", + 532 => x"10", + 533 => x"53", + 534 => x"8c", + 535 => x"52", + 536 => x"52", + 537 => x"3f", + 538 => x"38", + 539 => x"f8", + 540 => x"83", + 541 => x"55", + 542 => x"54", + 543 => x"83", + 544 => x"76", + 545 => x"17", + 546 => x"88", + 547 => x"55", + 548 => x"88", + 549 => x"74", + 550 => x"3f", + 551 => x"0a", + 552 => x"39", + 553 => x"88", + 554 => x"0d", + 555 => x"0d", + 556 => x"9f", + 557 => x"19", + 558 => x"fe", + 559 => x"54", + 560 => x"73", + 561 => x"82", + 562 => x"71", + 563 => x"08", + 564 => x"75", + 565 => x"3d", + 566 => x"3d", + 567 => x"80", + 568 => x"0b", + 569 => x"70", + 570 => x"53", + 571 => x"09", + 572 => x"38", + 573 => x"fd", + 574 => x"08", + 575 => x"9a", + 576 => x"e4", + 577 => x"83", + 578 => x"73", + 579 => x"85", + 580 => x"fc", + 581 => x"0b", + 582 => x"ac", + 583 => x"80", + 584 => x"15", + 585 => x"81", + 586 => x"88", + 587 => x"26", + 588 => x"52", + 589 => x"90", + 590 => x"52", + 591 => x"09", + 592 => x"38", + 593 => x"53", + 594 => x"0c", + 595 => x"8b", + 596 => x"fe", + 597 => x"08", + 598 => x"90", + 599 => x"71", + 600 => x"80", + 601 => x"0c", + 602 => x"04", + 603 => x"78", + 604 => x"9f", + 605 => x"22", + 606 => x"83", + 607 => x"57", + 608 => x"73", + 609 => x"38", + 610 => x"53", + 611 => x"83", + 612 => x"39", + 613 => x"52", + 614 => x"38", + 615 => x"16", + 616 => x"08", + 617 => x"38", + 618 => x"17", + 619 => x"73", + 620 => x"38", + 621 => x"16", + 622 => x"74", + 623 => x"52", + 624 => x"72", + 625 => x"3f", + 626 => x"88", + 627 => x"38", + 628 => x"08", + 629 => x"27", + 630 => x"08", + 631 => x"88", + 632 => x"c9", + 633 => x"90", + 634 => x"75", + 635 => x"71", + 636 => x"3d", + 637 => x"3d", + 638 => x"64", + 639 => x"75", + 640 => x"a0", + 641 => x"06", + 642 => x"16", + 643 => x"ef", + 644 => x"33", + 645 => x"af", + 646 => x"06", + 647 => x"16", + 648 => x"88", + 649 => x"70", + 650 => x"74", + 651 => x"38", + 652 => x"df", + 653 => x"56", + 654 => x"82", + 655 => x"3d", + 656 => x"70", + 657 => x"8a", + 658 => x"70", + 659 => x"34", + 660 => x"74", + 661 => x"81", + 662 => x"80", + 663 => x"88", + 664 => x"5a", + 665 => x"70", + 666 => x"60", + 667 => x"70", + 668 => x"30", + 669 => x"71", + 670 => x"51", + 671 => x"53", + 672 => x"74", + 673 => x"76", + 674 => x"81", + 675 => x"81", + 676 => x"27", + 677 => x"74", + 678 => x"38", + 679 => x"70", + 680 => x"32", + 681 => x"73", + 682 => x"53", + 683 => x"56", + 684 => x"88", + 685 => x"ff", + 686 => x"81", + 687 => x"ff", + 688 => x"53", + 689 => x"76", + 690 => x"98", + 691 => x"7f", + 692 => x"76", + 693 => x"38", + 694 => x"8b", + 695 => x"51", + 696 => x"88", + 697 => x"38", + 698 => x"22", + 699 => x"83", + 700 => x"55", + 701 => x"52", + 702 => x"a8", + 703 => x"57", + 704 => x"fb", + 705 => x"55", + 706 => x"80", + 707 => x"1d", + 708 => x"2a", + 709 => x"51", + 710 => x"b2", + 711 => x"84", + 712 => x"08", + 713 => x"58", + 714 => x"77", + 715 => x"38", + 716 => x"05", + 717 => x"70", + 718 => x"33", + 719 => x"52", + 720 => x"80", + 721 => x"86", + 722 => x"2e", + 723 => x"51", + 724 => x"ff", + 725 => x"08", + 726 => x"b4", + 727 => x"76", + 728 => x"08", + 729 => x"51", + 730 => x"38", + 731 => x"70", + 732 => x"81", + 733 => x"56", + 734 => x"83", + 735 => x"81", + 736 => x"7c", + 737 => x"3f", + 738 => x"1d", + 739 => x"39", + 740 => x"90", + 741 => x"f9", + 742 => x"7b", + 743 => x"54", + 744 => x"77", + 745 => x"f6", + 746 => x"56", + 747 => x"e7", + 748 => x"f8", + 749 => x"08", + 750 => x"06", + 751 => x"74", + 752 => x"2e", + 753 => x"80", + 754 => x"54", + 755 => x"52", + 756 => x"d0", + 757 => x"56", + 758 => x"38", + 759 => x"88", + 760 => x"83", + 761 => x"55", + 762 => x"c6", + 763 => x"82", + 764 => x"53", + 765 => x"51", + 766 => x"88", + 767 => x"08", + 768 => x"51", + 769 => x"88", + 770 => x"ff", + 771 => x"81", + 772 => x"83", + 773 => x"75", + 774 => x"3d", + 775 => x"3d", + 776 => x"80", + 777 => x"0b", + 778 => x"f5", + 779 => x"08", + 780 => x"82", + 781 => x"f2", + 782 => x"53", + 783 => x"53", + 784 => x"d3", + 785 => x"81", + 786 => x"76", + 787 => x"81", + 788 => x"90", + 789 => x"53", + 790 => x"51", + 791 => x"88", + 792 => x"8d", + 793 => x"74", + 794 => x"38", + 795 => x"05", + 796 => x"3f", + 797 => x"08", + 798 => x"5a", + 799 => x"88", + 800 => x"06", + 801 => x"2e", + 802 => x"86", + 803 => x"82", + 804 => x"80", + 805 => x"86", + 806 => x"39", + 807 => x"53", + 808 => x"51", + 809 => x"81", + 810 => x"81", + 811 => x"3d", + 812 => x"f6", + 813 => x"08", + 814 => x"06", + 815 => x"38", + 816 => x"05", + 817 => x"3f", + 818 => x"02", + 819 => x"78", + 820 => x"88", + 821 => x"70", + 822 => x"5b", + 823 => x"88", + 824 => x"ff", + 825 => x"8c", + 826 => x"3d", + 827 => x"34", + 828 => x"05", + 829 => x"3f", + 830 => x"1a", + 831 => x"e2", + 832 => x"e4", + 833 => x"83", + 834 => x"56", + 835 => x"95", + 836 => x"51", + 837 => x"88", + 838 => x"51", + 839 => x"88", + 840 => x"ff", + 841 => x"31", + 842 => x"1b", + 843 => x"2a", + 844 => x"56", + 845 => x"55", + 846 => x"55", + 847 => x"88", + 848 => x"70", + 849 => x"88", + 850 => x"05", + 851 => x"83", + 852 => x"83", + 853 => x"83", + 854 => x"27", + 855 => x"57", + 856 => x"56", + 857 => x"80", + 858 => x"79", + 859 => x"2e", + 860 => x"90", + 861 => x"fb", + 862 => x"81", + 863 => x"90", + 864 => x"39", + 865 => x"18", + 866 => x"79", + 867 => x"06", + 868 => x"19", + 869 => x"05", + 870 => x"55", + 871 => x"1a", + 872 => x"0b", + 873 => x"0c", + 874 => x"88", + 875 => x"0d", + 876 => x"0d", + 877 => x"9f", + 878 => x"85", + 879 => x"2e", + 880 => x"80", + 881 => x"34", + 882 => x"11", + 883 => x"89", + 884 => x"57", + 885 => x"f8", + 886 => x"08", + 887 => x"80", + 888 => x"3d", + 889 => x"80", + 890 => x"02", + 891 => x"70", + 892 => x"81", + 893 => x"57", + 894 => x"85", + 895 => x"a1", + 896 => x"f5", + 897 => x"08", + 898 => x"98", + 899 => x"51", + 900 => x"88", + 901 => x"0c", + 902 => x"0c", + 903 => x"16", + 904 => x"0c", + 905 => x"04", + 906 => x"7d", + 907 => x"0b", + 908 => x"08", + 909 => x"58", + 910 => x"85", + 911 => x"2e", + 912 => x"81", + 913 => x"06", + 914 => x"74", + 915 => x"c3", + 916 => x"74", + 917 => x"86", + 918 => x"81", + 919 => x"57", + 920 => x"9c", + 921 => x"17", + 922 => x"74", + 923 => x"38", + 924 => x"80", + 925 => x"38", + 926 => x"70", + 927 => x"56", + 928 => x"c7", + 929 => x"33", + 930 => x"89", + 931 => x"81", + 932 => x"55", + 933 => x"76", + 934 => x"16", + 935 => x"39", + 936 => x"51", + 937 => x"88", + 938 => x"75", + 939 => x"38", + 940 => x"0c", + 941 => x"51", + 942 => x"88", + 943 => x"08", + 944 => x"8f", + 945 => x"1a", + 946 => x"98", + 947 => x"ff", + 948 => x"71", + 949 => x"77", + 950 => x"38", + 951 => x"54", + 952 => x"83", + 953 => x"a8", + 954 => x"78", + 955 => x"3f", + 956 => x"e5", + 957 => x"08", + 958 => x"0c", + 959 => x"7b", + 960 => x"0c", + 961 => x"2e", + 962 => x"74", + 963 => x"e2", + 964 => x"76", + 965 => x"3d", + 966 => x"3d", + 967 => x"86", + 968 => x"c0", + 969 => x"9b", + 970 => x"0b", + 971 => x"9c", + 972 => x"83", + 973 => x"94", + 974 => x"80", + 975 => x"c0", + 976 => x"9f", + 977 => x"d6", + 978 => x"b8", + 979 => x"51", + 980 => x"88", + 981 => x"a0", + 982 => x"08", + 983 => x"88", + 984 => x"3d", + 985 => x"84", + 986 => x"51", + 987 => x"88", + 988 => x"75", + 989 => x"2e", + 990 => x"15", + 991 => x"a0", + 992 => x"04", + 993 => x"39", + 994 => x"ff", + 995 => x"ff", + 996 => x"00", + 997 => x"ff", + 998 => x"4f", + 999 => x"4e", + 1000 => x"4f", + 1001 => x"00", + 1002 => x"00", + 2048 => x"80", + 2049 => x"0b", + 2050 => x"95", + 2051 => x"ff", + 2052 => x"ff", + 2053 => x"ff", + 2054 => x"ff", + 2055 => x"ff", + 2056 => x"80", + 2057 => x"0b", + 2058 => x"85", + 2059 => x"80", + 2060 => x"0b", + 2061 => x"a5", + 2062 => x"80", + 2063 => x"0b", + 2064 => x"c5", + 2065 => x"80", + 2066 => x"0b", + 2067 => x"e5", + 2068 => x"80", + 2069 => x"0b", + 2070 => x"85", + 2071 => x"80", + 2072 => x"0b", + 2073 => x"a5", + 2074 => x"80", + 2075 => x"0b", + 2076 => x"c5", + 2077 => x"80", + 2078 => x"0b", + 2079 => x"e5", + 2080 => x"80", + 2081 => x"0b", + 2082 => x"85", + 2083 => x"80", + 2084 => x"0b", + 2085 => x"a5", + 2086 => x"80", + 2087 => x"0b", + 2088 => x"c5", + 2089 => x"80", + 2090 => x"0b", + 2091 => x"e5", + 2092 => x"80", + 2093 => x"0b", + 2094 => x"85", + 2095 => x"80", + 2096 => x"0b", + 2097 => x"a5", + 2098 => x"80", + 2099 => x"0b", + 2100 => x"c5", + 2101 => x"80", + 2102 => x"0b", + 2103 => x"e5", + 2104 => x"80", + 2105 => x"0b", + 2106 => x"85", + 2107 => x"80", + 2108 => x"0b", + 2109 => x"a5", + 2110 => x"80", + 2111 => x"0b", + 2112 => x"c5", + 2113 => x"80", + 2114 => x"0b", + 2115 => x"e5", + 2116 => x"80", + 2117 => x"0b", + 2118 => x"85", + 2119 => x"80", + 2120 => x"0b", + 2121 => x"a5", + 2122 => x"80", + 2123 => x"0b", + 2124 => x"c5", + 2125 => x"80", + 2126 => x"0b", + 2127 => x"e5", + 2128 => x"80", + 2129 => x"0b", + 2130 => x"85", + 2131 => x"00", + 2132 => x"00", + 2133 => x"00", + 2134 => x"00", + 2135 => x"00", + 2136 => x"00", + 2137 => x"00", + 2138 => x"00", + 2139 => x"00", + 2140 => x"00", + 2141 => x"00", + 2142 => x"00", + 2143 => x"00", + 2144 => x"00", + 2145 => x"00", + 2146 => x"00", + 2147 => x"00", + 2148 => x"00", + 2149 => x"00", + 2150 => x"00", + 2151 => x"00", + 2152 => x"00", + 2153 => x"00", + 2154 => x"00", + 2155 => x"00", + 2156 => x"00", + 2157 => x"00", + 2158 => x"00", + 2159 => x"00", + 2160 => x"00", + 2161 => x"00", + 2162 => x"00", + 2163 => x"00", + 2164 => x"00", + 2165 => x"00", + 2166 => x"00", + 2167 => x"00", + 2168 => x"00", + 2169 => x"00", + 2170 => x"00", + 2171 => x"00", + 2172 => x"00", + 2173 => x"00", + 2174 => x"00", + 2175 => x"00", + 2176 => x"c4", + 2177 => x"93", + 2178 => x"d5", + 2179 => x"93", + 2180 => x"80", + 2181 => x"93", + 2182 => x"df", + 2183 => x"93", + 2184 => x"80", + 2185 => x"93", + 2186 => x"e0", + 2187 => x"93", + 2188 => x"80", + 2189 => x"93", + 2190 => x"e0", + 2191 => x"93", + 2192 => x"80", + 2193 => x"93", + 2194 => x"e6", + 2195 => x"93", + 2196 => x"80", + 2197 => x"93", + 2198 => x"e8", + 2199 => x"93", + 2200 => x"80", + 2201 => x"93", + 2202 => x"e0", + 2203 => x"93", + 2204 => x"80", + 2205 => x"93", + 2206 => x"e8", + 2207 => x"93", + 2208 => x"80", + 2209 => x"93", + 2210 => x"ea", + 2211 => x"93", + 2212 => x"80", + 2213 => x"93", + 2214 => x"e6", + 2215 => x"93", + 2216 => x"80", + 2217 => x"93", + 2218 => x"e6", + 2219 => x"93", + 2220 => x"80", + 2221 => x"93", + 2222 => x"e6", + 2223 => x"93", + 2224 => x"80", + 2225 => x"93", + 2226 => x"d7", + 2227 => x"93", + 2228 => x"80", + 2229 => x"93", + 2230 => x"d7", + 2231 => x"93", + 2232 => x"80", + 2233 => x"93", + 2234 => x"cf", + 2235 => x"93", + 2236 => x"80", + 2237 => x"93", + 2238 => x"d1", + 2239 => x"93", + 2240 => x"80", + 2241 => x"93", + 2242 => x"d2", + 2243 => x"93", + 2244 => x"80", + 2245 => x"93", + 2246 => x"9e", + 2247 => x"93", + 2248 => x"80", + 2249 => x"93", + 2250 => x"ad", + 2251 => x"93", + 2252 => x"80", + 2253 => x"93", + 2254 => x"a3", + 2255 => x"93", + 2256 => x"80", + 2257 => x"93", + 2258 => x"a7", + 2259 => x"93", + 2260 => x"80", + 2261 => x"93", + 2262 => x"b3", + 2263 => x"93", + 2264 => x"80", + 2265 => x"93", + 2266 => x"bd", + 2267 => x"93", + 2268 => x"80", + 2269 => x"93", + 2270 => x"ac", + 2271 => x"93", + 2272 => x"80", + 2273 => x"93", + 2274 => x"b7", + 2275 => x"93", + 2276 => x"80", + 2277 => x"93", + 2278 => x"b8", + 2279 => x"93", + 2280 => x"80", + 2281 => x"93", + 2282 => x"b9", + 2283 => x"93", + 2284 => x"80", + 2285 => x"93", + 2286 => x"c2", + 2287 => x"93", + 2288 => x"80", + 2289 => x"93", + 2290 => x"bf", + 2291 => x"93", + 2292 => x"80", + 2293 => x"93", + 2294 => x"c4", + 2295 => x"93", + 2296 => x"80", + 2297 => x"93", + 2298 => x"ba", + 2299 => x"93", + 2300 => x"80", + 2301 => x"93", + 2302 => x"c7", + 2303 => x"93", + 2304 => x"80", + 2305 => x"93", + 2306 => x"c8", + 2307 => x"93", + 2308 => x"80", + 2309 => x"93", + 2310 => x"ae", + 2311 => x"93", + 2312 => x"80", + 2313 => x"93", + 2314 => x"ae", + 2315 => x"93", + 2316 => x"80", + 2317 => x"93", + 2318 => x"af", + 2319 => x"93", + 2320 => x"80", + 2321 => x"93", + 2322 => x"ba", + 2323 => x"93", + 2324 => x"80", + 2325 => x"93", + 2326 => x"c9", + 2327 => x"93", + 2328 => x"80", + 2329 => x"93", + 2330 => x"cc", + 2331 => x"93", + 2332 => x"80", + 2333 => x"93", + 2334 => x"cf", + 2335 => x"93", + 2336 => x"80", + 2337 => x"93", + 2338 => x"9e", + 2339 => x"93", + 2340 => x"80", + 2341 => x"93", + 2342 => x"d2", + 2343 => x"93", + 2344 => x"80", + 2345 => x"93", + 2346 => x"ed", + 2347 => x"93", + 2348 => x"80", + 2349 => x"93", + 2350 => x"ef", + 2351 => x"93", + 2352 => x"80", + 2353 => x"93", + 2354 => x"f1", + 2355 => x"93", + 2356 => x"80", + 2357 => x"93", + 2358 => x"d0", + 2359 => x"93", + 2360 => x"80", + 2361 => x"93", + 2362 => x"d0", + 2363 => x"93", + 2364 => x"80", + 2365 => x"93", + 2366 => x"d3", + 2367 => x"93", + 2368 => x"80", + 2369 => x"93", + 2370 => x"df", + 2371 => x"93", + 2372 => x"80", + 2373 => x"93", + 2374 => x"b6", + 2375 => x"38", + 2376 => x"84", + 2377 => x"0b", + 2378 => x"98", + 2379 => x"80", + 2380 => x"da", + 2381 => x"82", + 2382 => x"02", + 2383 => x"0c", + 2384 => x"80", + 2385 => x"d4", + 2386 => x"08", + 2387 => x"d4", + 2388 => x"08", + 2389 => x"3f", + 2390 => x"08", + 2391 => x"c8", + 2392 => x"3d", + 2393 => x"d4", + 2394 => x"93", + 2395 => x"82", + 2396 => x"fd", + 2397 => x"53", + 2398 => x"08", + 2399 => x"52", + 2400 => x"08", + 2401 => x"51", + 2402 => x"93", + 2403 => x"82", + 2404 => x"54", + 2405 => x"82", + 2406 => x"04", + 2407 => x"08", + 2408 => x"d4", + 2409 => x"0d", + 2410 => x"93", + 2411 => x"05", + 2412 => x"82", + 2413 => x"f8", + 2414 => x"93", + 2415 => x"05", + 2416 => x"d4", + 2417 => x"08", + 2418 => x"82", + 2419 => x"fc", + 2420 => x"2e", + 2421 => x"0b", + 2422 => x"08", + 2423 => x"24", + 2424 => x"93", + 2425 => x"05", + 2426 => x"93", + 2427 => x"05", + 2428 => x"d4", + 2429 => x"08", + 2430 => x"d4", + 2431 => x"0c", + 2432 => x"82", + 2433 => x"fc", + 2434 => x"2e", + 2435 => x"82", + 2436 => x"8c", + 2437 => x"93", + 2438 => x"05", + 2439 => x"38", + 2440 => x"08", + 2441 => x"82", + 2442 => x"8c", + 2443 => x"82", + 2444 => x"88", + 2445 => x"93", + 2446 => x"05", + 2447 => x"d4", + 2448 => x"08", + 2449 => x"d4", + 2450 => x"0c", + 2451 => x"08", + 2452 => x"81", + 2453 => x"d4", + 2454 => x"0c", + 2455 => x"08", + 2456 => x"81", + 2457 => x"d4", + 2458 => x"0c", + 2459 => x"82", + 2460 => x"90", + 2461 => x"2e", + 2462 => x"93", + 2463 => x"05", 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x"80", + 2523 => x"72", + 2524 => x"75", + 2525 => x"06", + 2526 => x"12", + 2527 => x"33", + 2528 => x"06", + 2529 => x"52", + 2530 => x"72", + 2531 => x"81", + 2532 => x"81", + 2533 => x"71", + 2534 => x"c8", + 2535 => x"87", + 2536 => x"71", + 2537 => x"fb", + 2538 => x"06", + 2539 => x"82", + 2540 => x"51", + 2541 => x"97", + 2542 => x"84", + 2543 => x"54", + 2544 => x"75", + 2545 => x"38", + 2546 => x"52", + 2547 => x"80", + 2548 => x"c8", + 2549 => x"0d", + 2550 => x"0d", + 2551 => x"52", + 2552 => x"52", + 2553 => x"82", + 2554 => x"81", + 2555 => x"07", + 2556 => x"52", + 2557 => x"e8", + 2558 => x"93", + 2559 => x"3d", + 2560 => x"3d", + 2561 => x"08", + 2562 => x"55", + 2563 => x"80", + 2564 => x"33", + 2565 => x"2e", + 2566 => x"8c", + 2567 => x"70", + 2568 => x"70", + 2569 => x"38", + 2570 => x"39", + 2571 => x"80", + 2572 => x"53", + 2573 => x"83", + 2574 => x"70", + 2575 => x"2a", + 2576 => x"51", + 2577 => x"71", + 2578 => x"a0", + 2579 => x"06", + 2580 => x"72", + 2581 => x"54", + 2582 => x"0c", + 2583 => x"82", + 2584 => x"86", + 2585 => x"fc", + 2586 => x"53", + 2587 => x"2e", + 2588 => x"3d", + 2589 => x"72", + 2590 => x"3f", + 2591 => x"08", + 2592 => x"53", + 2593 => x"53", + 2594 => x"c8", + 2595 => x"0d", + 2596 => x"0d", + 2597 => x"33", + 2598 => x"5c", + 2599 => x"8b", + 2600 => x"38", + 2601 => x"ff", + 2602 => x"5b", + 2603 => x"81", + 2604 => x"1c", + 2605 => x"5b", + 2606 => x"81", + 2607 => x"1c", + 2608 => x"5b", + 2609 => x"81", + 2610 => x"1c", + 2611 => x"5b", + 2612 => x"81", + 2613 => x"1c", + 2614 => x"5b", + 2615 => x"26", + 2616 => x"8a", + 2617 => x"87", + 2618 => x"e7", + 2619 => x"38", + 2620 => x"59", + 2621 => x"58", + 2622 => x"57", + 2623 => x"56", + 2624 => x"55", + 2625 => x"54", + 2626 => x"53", + 2627 => x"81", + 2628 => x"94", + 2629 => x"c0", + 2630 => x"81", + 2631 => x"22", + 2632 => x"bc", + 2633 => x"33", + 2634 => x"b8", + 2635 => x"33", + 2636 => x"b4", + 2637 => x"33", + 2638 => x"b0", + 2639 => x"33", + 2640 => x"ac", + 2641 => x"33", + 2642 => x"a8", + 2643 => x"22", + 2644 => x"a4", + 2645 => x"22", + 2646 => x"a0", + 2647 => x"0c", + 2648 => x"82", + 2649 => x"8d", + 2650 => x"f5", + 2651 => x"5a", + 2652 => x"9c", + 2653 => x"0c", + 2654 => x"bc", + 2655 => x"7a", + 2656 => x"98", + 2657 => x"7a", + 2658 => x"87", + 2659 => x"08", + 2660 => x"1b", + 2661 => x"98", + 2662 => x"7a", + 2663 => x"87", + 2664 => x"08", + 2665 => x"1b", + 2666 => x"98", + 2667 => x"7a", + 2668 => x"87", + 2669 => x"08", + 2670 => x"1b", + 2671 => x"98", + 2672 => x"7a", + 2673 => x"80", + 2674 => x"1a", + 2675 => x"1a", + 2676 => x"1a", + 2677 => x"1a", + 2678 => x"1a", + 2679 => x"1a", + 2680 => x"1a", + 2681 => x"22", + 2682 => x"a8", + 2683 => x"3f", + 2684 => x"04", + 2685 => x"02", + 2686 => x"70", + 2687 => x"2a", + 2688 => x"70", + 2689 => x"8b", + 2690 => x"3d", + 2691 => x"3d", + 2692 => x"0b", + 2693 => x"33", + 2694 => x"c0", + 2695 => x"72", + 2696 => x"38", + 2697 => x"94", + 2698 => x"70", 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x"2e", + 2758 => x"c0", + 2759 => x"70", + 2760 => x"2a", + 2761 => x"51", + 2762 => x"80", + 2763 => x"71", + 2764 => x"81", + 2765 => x"70", + 2766 => x"96", + 2767 => x"70", + 2768 => x"51", + 2769 => x"8d", + 2770 => x"2a", + 2771 => x"51", + 2772 => x"bc", + 2773 => x"82", + 2774 => x"51", + 2775 => x"80", + 2776 => x"2e", + 2777 => x"c0", + 2778 => x"74", + 2779 => x"16", + 2780 => x"56", + 2781 => x"38", + 2782 => x"c8", + 2783 => x"0d", + 2784 => x"0d", + 2785 => x"8b", + 2786 => x"87", + 2787 => x"51", + 2788 => x"86", + 2789 => x"94", + 2790 => x"08", + 2791 => x"70", + 2792 => x"51", + 2793 => x"2e", + 2794 => x"0b", + 2795 => x"33", + 2796 => x"94", + 2797 => x"80", + 2798 => x"87", + 2799 => x"52", + 2800 => x"81", + 2801 => x"93", + 2802 => x"83", + 2803 => x"ff", + 2804 => x"0b", + 2805 => x"33", + 2806 => x"94", + 2807 => x"80", + 2808 => x"87", + 2809 => x"52", + 2810 => x"82", + 2811 => x"06", + 2812 => x"ff", + 2813 => x"2e", + 2814 => x"0b", + 2815 => x"33", + 2816 => x"94", + 2817 => x"80", + 2818 => x"87", + 2819 => x"52", + 2820 => x"98", + 2821 => x"2c", + 2822 => x"71", + 2823 => x"0c", + 2824 => x"04", + 2825 => x"87", + 2826 => x"70", + 2827 => x"2a", + 2828 => x"52", + 2829 => x"2e", + 2830 => x"82", + 2831 => x"87", + 2832 => x"08", + 2833 => x"11", + 2834 => x"a0", + 2835 => x"52", + 2836 => x"c0", + 2837 => x"71", + 2838 => x"11", + 2839 => x"90", + 2840 => x"52", + 2841 => x"c0", + 2842 => x"71", + 2843 => x"11", + 2844 => x"98", + 2845 => x"52", + 2846 => x"c0", + 2847 => x"71", + 2848 => x"11", + 2849 => x"a8", + 2850 => x"52", + 2851 => x"c0", + 2852 => x"71", + 2853 => x"08", + 2854 => x"a4", + 2855 => x"12", + 2856 => x"84", + 2857 => x"51", + 2858 => x"13", + 2859 => x"52", + 2860 => x"c0", + 2861 => x"70", + 2862 => x"51", + 2863 => x"80", + 2864 => x"81", + 2865 => x"34", + 2866 => x"c0", + 2867 => x"70", + 2868 => x"06", + 2869 => x"70", + 2870 => x"38", + 2871 => x"82", + 2872 => x"80", + 2873 => x"9e", + 2874 => x"80", + 2875 => x"51", + 2876 => x"80", + 2877 => x"81", + 2878 => x"8b", + 2879 => x"0b", + 2880 => x"88", + 2881 => x"80", + 2882 => x"52", + 2883 => x"83", + 2884 => x"71", + 2885 => x"34", + 2886 => x"c0", + 2887 => x"70", + 2888 => x"51", + 2889 => x"80", + 2890 => x"81", + 2891 => x"8b", + 2892 => x"0b", + 2893 => x"88", + 2894 => x"80", + 2895 => x"52", + 2896 => x"83", + 2897 => x"71", + 2898 => x"34", + 2899 => x"c0", + 2900 => x"70", + 2901 => x"51", + 2902 => x"80", + 2903 => x"81", + 2904 => x"8b", + 2905 => x"0b", + 2906 => x"88", + 2907 => x"80", + 2908 => x"52", + 2909 => x"83", + 2910 => x"71", + 2911 => x"34", + 2912 => x"52", + 2913 => x"88", + 2914 => x"80", + 2915 => x"86", + 2916 => x"52", + 2917 => x"70", + 2918 => x"34", + 2919 => x"73", + 2920 => x"06", + 2921 => x"70", + 2922 => x"38", + 2923 => x"74", + 2924 => x"87", + 2925 => x"08", + 2926 => x"51", + 2927 => x"80", + 2928 => x"81", + 2929 => x"8b", + 2930 => x"c0", + 2931 => x"70", + 2932 => x"51", + 2933 => x"fc", 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x"15", + 2993 => x"f8", + 2994 => x"d2", + 2995 => x"ec", + 2996 => x"3f", + 2997 => x"70", + 2998 => x"05", + 2999 => x"81", + 3000 => x"55", + 3001 => x"3f", + 3002 => x"81", + 3003 => x"88", + 3004 => x"15", + 3005 => x"f9", + 3006 => x"a2", + 3007 => x"22", + 3008 => x"f0", + 3009 => x"3f", + 3010 => x"52", + 3011 => x"51", + 3012 => x"86", + 3013 => x"ff", + 3014 => x"8e", + 3015 => x"71", + 3016 => x"38", + 3017 => x"0b", + 3018 => x"c4", + 3019 => x"08", + 3020 => x"c0", + 3021 => x"3f", + 3022 => x"fa", + 3023 => x"b2", + 3024 => x"81", + 3025 => x"f7", + 3026 => x"39", + 3027 => x"51", + 3028 => x"91", + 3029 => x"dc", + 3030 => x"3f", + 3031 => x"fa", + 3032 => x"8e", + 3033 => x"0d", + 3034 => x"80", + 3035 => x"0b", + 3036 => x"84", + 3037 => x"3d", + 3038 => x"96", + 3039 => x"52", + 3040 => x"0c", + 3041 => x"70", + 3042 => x"0c", + 3043 => x"3d", + 3044 => x"3d", + 3045 => x"96", + 3046 => x"82", + 3047 => x"52", + 3048 => x"73", + 3049 => x"8c", + 3050 => x"70", + 3051 => x"0c", + 3052 => x"83", + 3053 => x"82", + 3054 => x"87", + 3055 => x"0c", + 3056 => x"0d", + 3057 => x"33", + 3058 => x"2e", + 3059 => x"85", + 3060 => x"ed", + 3061 => x"e0", + 3062 => x"95", + 3063 => x"e0", + 3064 => x"72", + 3065 => x"e0", + 3066 => x"82", + 3067 => x"92", + 3068 => x"d8", + 3069 => x"8a", + 3070 => x"82", + 3071 => x"52", + 3072 => x"3d", + 3073 => x"3d", + 3074 => x"05", + 3075 => x"d8", + 3076 => x"93", + 3077 => x"51", + 3078 => x"72", + 3079 => x"0c", + 3080 => x"04", + 3081 => x"74", + 3082 => x"53", + 3083 => x"91", + 3084 => x"81", + 3085 => x"51", + 3086 => x"72", + 3087 => x"f1", + 3088 => x"0d", + 3089 => x"0d", + 3090 => x"d8", + 3091 => x"93", + 3092 => x"33", + 3093 => x"71", + 3094 => x"38", + 3095 => x"05", + 3096 => x"fe", + 3097 => x"33", + 3098 => x"38", + 3099 => x"d8", + 3100 => x"0d", + 3101 => x"0d", + 3102 => x"59", + 3103 => x"05", + 3104 => x"75", + 3105 => x"92", + 3106 => x"2e", + 3107 => x"51", + 3108 => x"e8", + 3109 => x"7a", + 3110 => x"5c", + 3111 => x"5a", + 3112 => x"09", + 3113 => x"38", + 3114 => x"81", + 3115 => x"57", + 3116 => x"75", + 3117 => x"81", + 3118 => x"82", + 3119 => x"05", + 3120 => x"5d", + 3121 => x"09", + 3122 => x"38", + 3123 => x"71", + 3124 => x"81", + 3125 => x"59", + 3126 => x"9f", + 3127 => x"53", + 3128 => x"97", + 3129 => x"29", + 3130 => x"79", + 3131 => x"5b", + 3132 => x"55", + 3133 => x"73", + 3134 => x"75", + 3135 => x"70", + 3136 => x"07", + 3137 => x"80", + 3138 => x"30", + 3139 => x"80", + 3140 => x"53", + 3141 => x"54", + 3142 => x"2e", + 3143 => x"84", + 3144 => x"81", + 3145 => x"57", + 3146 => x"2e", + 3147 => x"75", + 3148 => x"76", + 3149 => x"e0", + 3150 => x"ff", + 3151 => x"ff", + 3152 => x"72", + 3153 => x"98", + 3154 => x"10", + 3155 => x"05", + 3156 => x"04", + 3157 => x"71", + 3158 => x"53", + 3159 => x"54", + 3160 => x"2e", + 3161 => x"14", + 3162 => x"33", + 3163 => x"72", + 3164 => x"81", + 3165 => x"06", + 3166 => x"a3", + 3167 => x"15", + 3168 => x"7a", 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x"81", + 3228 => x"53", + 3229 => x"05", + 3230 => x"16", + 3231 => x"74", + 3232 => x"77", + 3233 => x"07", + 3234 => x"9f", + 3235 => x"51", + 3236 => x"72", + 3237 => x"7c", + 3238 => x"81", + 3239 => x"72", + 3240 => x"38", + 3241 => x"05", + 3242 => x"ad", + 3243 => x"18", + 3244 => x"81", + 3245 => x"b0", + 3246 => x"38", + 3247 => x"81", + 3248 => x"06", + 3249 => x"a3", + 3250 => x"15", + 3251 => x"7a", + 3252 => x"7c", + 3253 => x"06", + 3254 => x"f9", + 3255 => x"8b", + 3256 => x"15", + 3257 => x"73", + 3258 => x"ff", + 3259 => x"e0", + 3260 => x"33", + 3261 => x"f9", + 3262 => x"ef", + 3263 => x"15", + 3264 => x"7a", + 3265 => x"38", + 3266 => x"b5", + 3267 => x"15", + 3268 => x"73", + 3269 => x"fa", + 3270 => x"3d", + 3271 => x"3d", + 3272 => x"70", + 3273 => x"52", + 3274 => x"73", + 3275 => x"3f", + 3276 => x"04", + 3277 => x"74", + 3278 => x"0c", + 3279 => x"05", + 3280 => x"fa", + 3281 => x"93", + 3282 => x"80", + 3283 => x"0b", + 3284 => x"0c", + 3285 => x"04", + 3286 => x"82", + 3287 => x"76", + 3288 => x"0c", + 3289 => x"05", + 3290 => x"53", + 3291 => x"72", + 3292 => x"0c", + 3293 => x"04", + 3294 => x"78", + 3295 => x"80", + 3296 => x"dc", + 3297 => x"80", + 3298 => x"39", + 3299 => x"f3", + 3300 => x"82", + 3301 => x"52", + 3302 => x"93", + 3303 => x"ff", + 3304 => x"80", + 3305 => x"73", + 3306 => x"ca", + 3307 => x"32", + 3308 => x"30", + 3309 => x"9f", + 3310 => x"25", + 3311 => x"51", + 3312 => x"2e", + 3313 => x"15", + 3314 => x"06", + 3315 => x"f1", + 3316 => x"9f", + 3317 => x"bb", + 3318 => x"52", + 3319 => x"ff", + 3320 => x"15", + 3321 => x"34", + 3322 => x"81", + 3323 => x"55", + 3324 => x"ff", + 3325 => x"17", + 3326 => x"34", + 3327 => x"c1", + 3328 => x"72", + 3329 => x"0c", + 3330 => x"04", + 3331 => x"82", + 3332 => x"75", + 3333 => x"0c", + 3334 => x"52", + 3335 => x"3f", + 3336 => x"dc", + 3337 => x"0d", + 3338 => x"0d", + 3339 => x"55", + 3340 => x"0c", + 3341 => x"33", + 3342 => x"73", + 3343 => x"81", + 3344 => x"74", + 3345 => x"75", + 3346 => x"70", + 3347 => x"73", + 3348 => x"38", + 3349 => x"09", + 3350 => x"38", + 3351 => x"11", + 3352 => x"08", + 3353 => x"54", + 3354 => x"2e", + 3355 => x"80", + 3356 => x"08", + 3357 => x"0c", + 3358 => x"33", + 3359 => x"80", + 3360 => x"38", + 3361 => x"2e", + 3362 => x"a1", + 3363 => x"81", + 3364 => x"75", + 3365 => x"56", + 3366 => x"c1", + 3367 => x"08", + 3368 => x"0c", + 3369 => x"33", + 3370 => x"b1", + 3371 => x"a0", + 3372 => x"82", + 3373 => x"53", + 3374 => x"57", + 3375 => x"9d", + 3376 => x"39", + 3377 => x"80", + 3378 => x"26", + 3379 => x"8b", + 3380 => x"80", + 3381 => x"56", + 3382 => x"8a", + 3383 => x"a0", + 3384 => x"c5", + 3385 => x"74", + 3386 => x"e0", + 3387 => x"ff", + 3388 => x"d0", + 3389 => x"ff", + 3390 => x"90", + 3391 => x"38", + 3392 => x"81", + 3393 => x"53", + 3394 => x"c5", + 3395 => x"27", + 3396 => x"76", + 3397 => x"08", + 3398 => x"0c", + 3399 => x"33", + 3400 => x"73", + 3401 => x"bd", + 3402 => x"2e", + 3403 => x"30", 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x"06", + 3463 => x"74", + 3464 => x"73", + 3465 => x"38", + 3466 => x"14", + 3467 => x"05", + 3468 => x"08", + 3469 => x"54", + 3470 => x"26", + 3471 => x"77", + 3472 => x"38", + 3473 => x"75", + 3474 => x"56", + 3475 => x"c8", + 3476 => x"0d", + 3477 => x"0d", + 3478 => x"33", + 3479 => x"70", + 3480 => x"38", + 3481 => x"11", + 3482 => x"82", + 3483 => x"83", + 3484 => x"fd", + 3485 => x"97", + 3486 => x"84", + 3487 => x"33", + 3488 => x"51", + 3489 => x"80", + 3490 => x"90", + 3491 => x"92", + 3492 => x"88", + 3493 => x"2e", + 3494 => x"88", + 3495 => x"0c", + 3496 => x"87", + 3497 => x"05", + 3498 => x"0c", + 3499 => x"c0", + 3500 => x"70", + 3501 => x"98", + 3502 => x"08", + 3503 => x"51", + 3504 => x"2e", + 3505 => x"08", + 3506 => x"38", + 3507 => x"87", + 3508 => x"05", + 3509 => x"80", + 3510 => x"51", + 3511 => x"87", + 3512 => x"08", + 3513 => x"2e", + 3514 => x"82", + 3515 => x"34", + 3516 => x"13", + 3517 => x"82", + 3518 => x"85", + 3519 => x"f2", + 3520 => x"63", + 3521 => x"05", + 3522 => x"33", + 3523 => x"58", + 3524 => x"5b", + 3525 => x"82", + 3526 => x"81", + 3527 => x"52", + 3528 => x"38", + 3529 => x"5d", + 3530 => x"8c", + 3531 => x"87", + 3532 => x"11", + 3533 => x"84", + 3534 => x"5c", + 3535 => x"85", + 3536 => x"c0", + 3537 => x"7c", + 3538 => x"84", + 3539 => x"08", + 3540 => x"70", + 3541 => x"53", + 3542 => x"2e", + 3543 => x"08", + 3544 => x"70", + 3545 => x"34", + 3546 => x"73", + 3547 => x"71", + 3548 => x"38", + 3549 => x"71", + 3550 => x"08", + 3551 => x"2e", + 3552 => x"84", + 3553 => x"38", + 3554 => x"87", + 3555 => x"1e", + 3556 => x"70", + 3557 => x"52", + 3558 => x"ff", + 3559 => x"39", + 3560 => x"81", + 3561 => x"ff", + 3562 => x"5c", + 3563 => x"90", + 3564 => x"80", + 3565 => x"71", + 3566 => x"7d", + 3567 => x"38", + 3568 => x"80", + 3569 => x"80", + 3570 => x"81", + 3571 => x"73", + 3572 => x"0c", + 3573 => x"04", + 3574 => x"60", + 3575 => x"8c", + 3576 => x"33", + 3577 => x"57", + 3578 => x"5a", + 3579 => x"82", + 3580 => x"81", + 3581 => x"52", + 3582 => x"38", + 3583 => x"c0", + 3584 => x"84", + 3585 => x"92", + 3586 => x"c0", + 3587 => x"72", + 3588 => x"5a", + 3589 => x"0c", + 3590 => x"80", + 3591 => x"0c", + 3592 => x"0c", + 3593 => x"08", + 3594 => x"70", + 3595 => x"53", + 3596 => x"2e", + 3597 => x"70", + 3598 => x"33", + 3599 => x"13", + 3600 => x"2a", + 3601 => x"51", + 3602 => x"2e", + 3603 => x"08", + 3604 => x"38", + 3605 => x"71", + 3606 => x"38", + 3607 => x"2e", + 3608 => x"75", + 3609 => x"92", + 3610 => x"72", + 3611 => x"06", + 3612 => x"f7", + 3613 => x"5a", + 3614 => x"1c", + 3615 => x"06", + 3616 => x"5d", + 3617 => x"80", + 3618 => x"73", + 3619 => x"06", + 3620 => x"38", + 3621 => x"fe", + 3622 => x"fc", + 3623 => x"52", + 3624 => x"83", + 3625 => x"71", + 3626 => x"93", + 3627 => x"3d", + 3628 => x"3d", + 3629 => x"84", + 3630 => x"33", + 3631 => x"b3", + 3632 => x"54", + 3633 => x"fb", + 3634 => x"93", + 3635 => x"06", + 3636 => x"71", + 3637 => x"54", + 3638 => x"a2", + 3639 => x"24", + 3640 => x"80", + 3641 => x"a7", + 3642 => x"2e", + 3643 => x"39", + 3644 => x"87", + 3645 => x"05", + 3646 => x"52", + 3647 => x"80", + 3648 => x"80", + 3649 => x"81", + 3650 => x"80", + 3651 => x"84", + 3652 => x"93", + 3653 => x"3d", + 3654 => x"3d", + 3655 => x"33", + 3656 => x"70", + 3657 => x"07", + 3658 => x"0c", + 3659 => x"83", + 3660 => x"fd", + 3661 => x"83", + 3662 => x"12", + 3663 => x"2b", + 3664 => x"07", + 3665 => x"71", + 3666 => x"71", + 3667 => x"82", + 3668 => x"51", + 3669 => x"52", + 3670 => x"04", + 3671 => x"73", + 3672 => x"92", + 3673 => x"52", + 3674 => x"81", + 3675 => x"70", + 3676 => x"70", + 3677 => x"3d", + 3678 => x"3d", + 3679 => x"52", + 3680 => x"70", + 3681 => x"34", + 3682 => x"51", + 3683 => x"81", + 3684 => x"70", + 3685 => x"70", + 3686 => x"05", + 3687 => x"88", + 3688 => x"72", + 3689 => x"0d", + 3690 => x"0d", + 3691 => x"54", + 3692 => x"80", + 3693 => x"71", + 3694 => x"53", + 3695 => x"81", + 3696 => x"ff", + 3697 => x"ef", + 3698 => x"0d", + 3699 => x"0d", + 3700 => x"54", + 3701 => x"72", + 3702 => x"54", + 3703 => x"51", + 3704 => x"84", + 3705 => x"fc", + 3706 => x"77", + 3707 => x"53", + 3708 => x"05", + 3709 => x"70", + 3710 => x"33", + 3711 => x"ff", + 3712 => x"52", + 3713 => x"2e", + 3714 => x"80", + 3715 => x"71", + 3716 => x"0c", + 3717 => x"04", + 3718 => x"74", + 3719 => x"53", + 3720 => x"80", + 3721 => x"70", + 3722 => x"38", + 3723 => x"33", + 3724 => x"80", + 3725 => x"70", + 3726 => x"81", + 3727 => x"71", + 3728 => x"c8", + 3729 => x"0d", + 3730 => x"82", + 3731 => x"04", + 3732 => x"93", + 3733 => x"f9", + 3734 => x"56", + 3735 => x"17", + 3736 => x"74", + 3737 => x"d7", + 3738 => x"b0", + 3739 => x"b4", + 3740 => x"81", + 3741 => x"57", + 3742 => x"82", + 3743 => x"78", + 3744 => x"06", + 3745 => x"93", + 3746 => x"17", + 3747 => x"08", + 3748 => x"31", + 3749 => x"17", + 3750 => x"38", + 3751 => x"55", + 3752 => x"09", + 3753 => x"38", + 3754 => x"16", + 3755 => x"08", + 3756 => x"52", + 3757 => x"51", + 3758 => x"83", + 3759 => x"77", + 3760 => x"0c", + 3761 => x"04", + 3762 => x"78", + 3763 => x"80", + 3764 => x"08", + 3765 => x"38", + 3766 => x"fb", + 3767 => x"c8", + 3768 => x"93", + 3769 => x"38", + 3770 => x"53", + 3771 => x"81", + 3772 => x"f8", + 3773 => x"93", + 3774 => x"2e", + 3775 => x"55", + 3776 => x"b0", + 3777 => x"82", + 3778 => x"88", + 3779 => x"f8", + 3780 => x"70", + 3781 => x"bf", + 3782 => x"c8", + 3783 => x"93", + 3784 => x"91", + 3785 => x"55", + 3786 => x"09", + 3787 => x"f0", + 3788 => x"33", + 3789 => x"2e", + 3790 => x"80", + 3791 => x"80", + 3792 => x"c8", + 3793 => x"17", + 3794 => x"fd", + 3795 => x"d4", + 3796 => x"b2", + 3797 => x"84", + 3798 => x"85", + 3799 => x"75", + 3800 => x"3f", + 3801 => x"e4", + 3802 => x"98", + 3803 => x"8a", + 3804 => x"08", + 3805 => x"17", + 3806 => x"3f", + 3807 => x"52", + 3808 => x"51", + 3809 => x"a0", + 3810 => x"05", + 3811 => x"0c", + 3812 => x"75", + 3813 => x"33", + 3814 => x"3f", + 3815 => x"34", + 3816 => x"52", + 3817 => x"51", + 3818 => x"82", + 3819 => x"80", + 3820 => x"81", + 3821 => x"93", + 3822 => x"3d", + 3823 => x"3d", + 3824 => x"1a", + 3825 => x"fe", + 3826 => x"54", + 3827 => x"73", + 3828 => x"8a", + 3829 => x"76", + 3830 => x"08", + 3831 => x"75", + 3832 => x"0c", + 3833 => x"04", + 3834 => x"7a", + 3835 => x"56", + 3836 => x"75", + 3837 => x"98", + 3838 => x"26", + 3839 => x"56", + 3840 => x"ff", + 3841 => x"56", + 3842 => x"80", + 3843 => x"82", + 3844 => x"72", + 3845 => x"38", + 3846 => x"72", + 3847 => x"8e", + 3848 => x"39", + 3849 => x"15", + 3850 => x"a4", + 3851 => x"53", + 3852 => x"fd", + 3853 => x"93", + 3854 => x"9f", + 3855 => x"ff", + 3856 => x"11", + 3857 => x"70", + 3858 => x"18", + 3859 => x"76", + 3860 => x"53", + 3861 => x"82", + 3862 => x"80", + 3863 => x"83", + 3864 => x"b4", + 3865 => x"88", + 3866 => x"77", + 3867 => x"84", + 3868 => x"5a", + 3869 => x"80", + 3870 => x"9f", + 3871 => x"80", + 3872 => x"88", + 3873 => x"08", + 3874 => x"51", + 3875 => x"82", + 3876 => x"80", + 3877 => x"15", + 3878 => x"74", + 3879 => x"51", + 3880 => x"82", + 3881 => x"83", + 3882 => x"56", + 3883 => x"87", + 3884 => x"08", + 3885 => x"51", + 3886 => x"82", + 3887 => x"9b", + 3888 => x"2b", + 3889 => x"74", + 3890 => x"51", + 3891 => x"82", + 3892 => x"f0", + 3893 => x"83", + 3894 => x"75", + 3895 => x"0c", + 3896 => x"04", + 3897 => x"7b", + 3898 => x"55", + 3899 => x"81", + 3900 => x"af", + 3901 => x"16", + 3902 => x"a7", + 3903 => x"53", + 3904 => x"81", + 3905 => x"77", + 3906 => x"72", + 3907 => x"38", + 3908 => x"72", + 3909 => x"c9", + 3910 => x"39", + 3911 => x"14", + 3912 => x"a4", + 3913 => x"53", + 3914 => x"fb", + 3915 => x"93", + 3916 => x"82", + 3917 => x"81", + 3918 => x"83", + 3919 => x"b4", + 3920 => x"76", + 3921 => x"5b", + 3922 => x"57", + 3923 => x"8f", + 3924 => x"2b", + 3925 => x"78", + 3926 => x"71", + 3927 => x"76", + 3928 => x"0b", + 3929 => x"78", + 3930 => x"16", + 3931 => x"74", + 3932 => x"3f", + 3933 => x"08", + 3934 => x"c8", + 3935 => x"38", + 3936 => x"06", + 3937 => x"75", + 3938 => x"84", + 3939 => x"51", + 3940 => x"38", + 3941 => x"78", + 3942 => x"06", + 3943 => x"06", + 3944 => x"78", + 3945 => x"83", + 3946 => x"f7", + 3947 => x"2a", + 3948 => x"05", + 3949 => x"fa", + 3950 => x"93", + 3951 => x"82", + 3952 => x"80", + 3953 => x"83", + 3954 => x"52", + 3955 => x"ff", + 3956 => x"b4", + 3957 => x"84", + 3958 => x"83", + 3959 => x"c3", + 3960 => x"2a", + 3961 => x"05", + 3962 => x"f9", + 3963 => x"93", + 3964 => x"82", + 3965 => x"ab", + 3966 => x"0a", + 3967 => x"2b", + 3968 => x"76", + 3969 => x"70", + 3970 => x"56", + 3971 => x"82", + 3972 => x"8f", + 3973 => x"07", + 3974 => x"f6", + 3975 => x"0b", + 3976 => x"76", + 3977 => x"0c", + 3978 => x"04", + 3979 => x"79", + 3980 => x"08", + 3981 => x"57", + 3982 => x"88", + 3983 => x"08", + 3984 => x"38", + 3985 => x"8e", + 3986 => x"2e", + 3987 => x"53", + 3988 => x"51", + 3989 => x"82", + 3990 => x"56", + 3991 => x"08", + 3992 => x"93", + 3993 => x"80", + 3994 => x"56", + 3995 => x"82", + 3996 => x"56", + 3997 => x"73", + 3998 => x"fa", + 3999 => x"93", + 4000 => x"82", + 4001 => x"80", + 4002 => x"38", + 4003 => x"08", + 4004 => x"38", + 4005 => x"08", + 4006 => x"38", + 4007 => x"52", + 4008 => x"c0", + 4009 => x"c8", + 4010 => x"98", + 4011 => x"05", + 4012 => x"08", + 4013 => x"38", + 4014 => x"81", + 4015 => x"0c", + 4016 => x"81", + 4017 => x"84", + 4018 => x"54", + 4019 => x"76", + 4020 => x"38", + 4021 => x"82", + 4022 => x"89", + 4023 => x"f5", + 4024 => x"7f", + 4025 => x"5c", + 4026 => x"38", + 4027 => x"58", + 4028 => x"88", + 4029 => x"08", + 4030 => x"38", + 4031 => x"39", + 4032 => x"51", + 4033 => x"81", + 4034 => x"93", + 4035 => x"82", + 4036 => x"93", + 4037 => x"82", + 4038 => x"ff", + 4039 => x"38", + 4040 => x"08", + 4041 => x"08", + 4042 => x"08", + 4043 => x"38", + 4044 => x"55", + 4045 => x"75", + 4046 => x"38", + 4047 => x"7b", + 4048 => x"06", + 4049 => x"81", + 4050 => x"19", + 4051 => x"83", + 4052 => x"76", + 4053 => x"f9", + 4054 => x"93", + 4055 => x"80", + 4056 => x"c8", + 4057 => x"09", + 4058 => x"38", + 4059 => x"08", + 4060 => x"32", + 4061 => x"72", + 4062 => x"70", + 4063 => x"53", + 4064 => x"54", + 4065 => x"38", + 4066 => x"95", + 4067 => x"08", + 4068 => x"27", + 4069 => x"98", + 4070 => x"83", + 4071 => x"80", + 4072 => x"de", + 4073 => x"81", + 4074 => x"19", + 4075 => x"89", + 4076 => x"76", + 4077 => x"b6", + 4078 => x"7b", + 4079 => x"3f", + 4080 => x"08", + 4081 => x"c8", + 4082 => x"b6", + 4083 => x"82", + 4084 => x"81", + 4085 => x"06", + 4086 => x"93", + 4087 => x"75", + 4088 => x"30", + 4089 => x"80", + 4090 => x"07", + 4091 => x"54", + 4092 => x"38", + 4093 => x"09", + 4094 => x"ab", + 4095 => x"80", + 4096 => x"53", + 4097 => x"51", + 4098 => x"82", + 4099 => x"82", + 4100 => x"30", + 4101 => x"c8", + 4102 => x"25", + 4103 => x"7f", + 4104 => x"72", + 4105 => x"51", + 4106 => x"80", + 4107 => x"76", + 4108 => x"78", + 4109 => x"3f", + 4110 => x"08", + 4111 => x"38", + 4112 => x"0c", + 4113 => x"fe", + 4114 => x"19", + 4115 => x"89", + 4116 => x"08", + 4117 => x"1a", + 4118 => x"33", + 4119 => x"73", + 4120 => x"94", + 4121 => x"75", + 4122 => x"38", + 4123 => x"55", + 4124 => x"55", + 4125 => x"57", + 4126 => x"82", + 4127 => x"8d", + 4128 => x"f7", + 4129 => x"70", + 4130 => x"cb", + 4131 => x"82", + 4132 => x"80", + 4133 => x"52", + 4134 => x"a2", + 4135 => x"c8", + 4136 => x"c8", + 4137 => x"0c", + 4138 => x"53", + 4139 => x"17", + 4140 => x"f2", + 4141 => x"59", + 4142 => x"56", + 4143 => x"16", + 4144 => x"22", + 4145 => x"27", + 4146 => x"54", + 4147 => x"78", + 4148 => x"33", + 4149 => x"3f", + 4150 => x"08", + 4151 => x"38", + 4152 => x"18", + 4153 => x"74", + 4154 => x"38", + 4155 => x"55", + 4156 => x"c8", + 4157 => x"0d", + 4158 => x"0d", + 4159 => x"08", + 4160 => x"74", + 4161 => x"26", + 4162 => x"9f", + 4163 => x"80", + 4164 => x"82", + 4165 => x"39", + 4166 => x"0c", + 4167 => x"54", + 4168 => x"75", + 4169 => x"73", + 4170 => x"a8", + 4171 => x"73", + 4172 => x"85", + 4173 => x"0b", + 4174 => x"5a", + 4175 => x"27", + 4176 => x"a8", + 4177 => x"18", + 4178 => x"39", + 4179 => x"70", + 4180 => x"58", + 4181 => x"b6", + 4182 => x"76", + 4183 => x"3f", + 4184 => x"08", + 4185 => x"c8", + 4186 => x"bf", + 4187 => x"82", + 4188 => x"27", + 4189 => x"16", + 4190 => x"c8", + 4191 => x"38", + 4192 => x"c1", + 4193 => x"31", + 4194 => x"27", + 4195 => x"52", + 4196 => x"aa", + 4197 => x"c8", + 4198 => x"0c", + 4199 => x"0c", + 4200 => x"17", + 4201 => x"9d", + 4202 => x"81", + 4203 => x"74", + 4204 => x"18", + 4205 => x"18", + 4206 => x"ff", + 4207 => x"05", + 4208 => x"80", + 4209 => x"93", + 4210 => x"3d", + 4211 => x"3d", + 4212 => x"71", + 4213 => x"08", + 4214 => x"59", + 4215 => x"80", + 4216 => x"86", + 4217 => x"98", + 4218 => x"53", + 4219 => x"80", + 4220 => x"38", + 4221 => x"06", + 4222 => x"c1", + 4223 => x"08", + 4224 => x"16", + 4225 => x"08", + 4226 => x"85", + 4227 => x"22", + 4228 => x"73", + 4229 => x"38", + 4230 => x"0c", + 4231 => x"ad", + 4232 => x"22", + 4233 => x"89", + 4234 => x"53", + 4235 => x"38", + 4236 => x"52", + 4237 => x"b0", + 4238 => x"c8", + 4239 => x"53", + 4240 => x"93", + 4241 => x"81", + 4242 => x"53", + 4243 => x"08", + 4244 => x"f9", + 4245 => x"08", + 4246 => x"08", + 4247 => x"38", + 4248 => x"77", + 4249 => x"84", + 4250 => x"39", + 4251 => x"52", + 4252 => x"eb", + 4253 => x"c8", + 4254 => x"53", + 4255 => x"08", + 4256 => x"c9", + 4257 => x"82", + 4258 => x"81", + 4259 => x"81", + 4260 => x"c8", + 4261 => x"b5", + 4262 => x"c8", + 4263 => x"51", + 4264 => x"81", + 4265 => x"c8", + 4266 => x"73", + 4267 => x"73", + 4268 => x"f2", + 4269 => x"93", + 4270 => x"16", + 4271 => x"16", + 4272 => x"ff", + 4273 => x"05", + 4274 => x"80", + 4275 => x"93", + 4276 => x"3d", + 4277 => x"3d", + 4278 => x"71", + 4279 => x"56", + 4280 => x"51", + 4281 => x"82", + 4282 => x"54", + 4283 => x"08", + 4284 => x"82", + 4285 => x"57", + 4286 => x"52", + 4287 => x"c8", + 4288 => x"c8", + 4289 => x"93", + 4290 => x"c7", + 4291 => x"c8", + 4292 => x"08", + 4293 => x"54", + 4294 => x"e5", + 4295 => x"06", + 4296 => x"55", + 4297 => x"80", + 4298 => x"51", + 4299 => x"2e", + 4300 => x"17", + 4301 => x"2e", + 4302 => x"39", + 4303 => x"52", + 4304 => x"8a", + 4305 => x"c8", + 4306 => x"93", + 4307 => x"2e", + 4308 => x"73", + 4309 => x"81", + 4310 => x"87", + 4311 => x"93", + 4312 => x"3d", + 4313 => x"3d", + 4314 => x"11", + 4315 => x"aa", + 4316 => x"c8", + 4317 => x"ff", + 4318 => x"33", + 4319 => x"71", + 4320 => x"81", + 4321 => x"94", + 4322 => x"8e", + 4323 => x"c8", + 4324 => x"73", + 4325 => x"82", + 4326 => x"85", + 4327 => x"fc", + 4328 => x"79", + 4329 => x"ff", + 4330 => x"12", + 4331 => x"eb", + 4332 => x"70", + 4333 => x"72", + 4334 => x"81", + 4335 => x"73", + 4336 => x"94", + 4337 => x"94", + 4338 => x"0d", + 4339 => x"0d", + 4340 => x"56", + 4341 => x"5a", + 4342 => x"08", + 4343 => x"86", + 4344 => x"08", + 4345 => x"ed", + 4346 => x"93", + 4347 => x"82", + 4348 => x"80", + 4349 => x"16", + 4350 => x"56", + 4351 => x"38", + 4352 => x"e2", + 4353 => x"08", + 4354 => x"70", + 4355 => x"81", + 4356 => x"51", + 4357 => x"86", + 4358 => x"81", + 4359 => x"30", + 4360 => x"70", + 4361 => x"06", + 4362 => x"51", + 4363 => x"73", + 4364 => x"38", + 4365 => x"96", + 4366 => x"df", + 4367 => x"72", + 4368 => x"81", + 4369 => x"81", + 4370 => x"2e", + 4371 => x"52", + 4372 => x"fa", + 4373 => x"c8", + 4374 => x"93", + 4375 => x"38", + 4376 => x"fe", + 4377 => x"80", + 4378 => x"80", + 4379 => x"0c", + 4380 => x"c8", + 4381 => x"0d", + 4382 => x"0d", + 4383 => x"59", + 4384 => x"75", + 4385 => x"3f", + 4386 => x"08", + 4387 => x"c8", + 4388 => x"38", + 4389 => x"57", + 4390 => x"98", + 4391 => x"77", + 4392 => x"3f", + 4393 => x"08", + 4394 => x"c8", + 4395 => x"38", + 4396 => x"70", + 4397 => x"73", + 4398 => x"38", + 4399 => x"8b", + 4400 => x"06", + 4401 => x"86", + 4402 => x"15", + 4403 => x"2a", + 4404 => x"51", + 4405 => x"93", + 4406 => x"a0", + 4407 => x"51", + 4408 => x"82", + 4409 => x"80", + 4410 => x"80", + 4411 => x"f9", + 4412 => x"93", + 4413 => x"82", + 4414 => x"80", + 4415 => x"38", + 4416 => x"82", + 4417 => x"8a", + 4418 => x"fb", + 4419 => x"70", + 4420 => x"81", + 4421 => x"fb", + 4422 => x"93", + 4423 => x"82", + 4424 => x"b4", + 4425 => x"08", + 4426 => x"eb", + 4427 => x"93", + 4428 => x"82", + 4429 => x"a0", + 4430 => x"82", + 4431 => x"52", + 4432 => x"51", + 4433 => x"8b", + 4434 => x"52", + 4435 => x"51", + 4436 => x"81", + 4437 => x"34", + 4438 => x"c8", + 4439 => x"0d", + 4440 => x"0d", + 4441 => x"98", + 4442 => x"70", + 4443 => x"ea", + 4444 => x"93", + 4445 => x"82", + 4446 => x"8d", + 4447 => x"08", + 4448 => x"34", + 4449 => x"16", + 4450 => x"93", + 4451 => x"3d", + 4452 => x"3d", + 4453 => x"57", + 4454 => x"89", + 4455 => x"17", + 4456 => x"81", + 4457 => x"70", + 4458 => x"17", + 4459 => x"33", + 4460 => x"54", + 4461 => x"2e", + 4462 => x"85", + 4463 => x"06", + 4464 => x"e5", + 4465 => x"2e", + 4466 => x"8e", + 4467 => x"88", + 4468 => x"0b", + 4469 => x"81", + 4470 => x"15", + 4471 => x"72", + 4472 => x"81", + 4473 => x"74", + 4474 => x"75", + 4475 => x"52", + 4476 => x"13", + 4477 => x"08", + 4478 => x"33", + 4479 => x"9c", + 4480 => x"05", + 4481 => x"3f", + 4482 => x"08", + 4483 => x"17", + 4484 => x"51", + 4485 => x"82", + 4486 => x"86", + 4487 => x"17", + 4488 => x"51", + 4489 => x"82", + 4490 => x"84", + 4491 => x"3d", + 4492 => x"3d", + 4493 => x"08", + 4494 => x"5d", + 4495 => x"53", + 4496 => x"51", + 4497 => x"80", + 4498 => x"88", + 4499 => x"5a", + 4500 => x"09", + 4501 => x"df", + 4502 => x"70", + 4503 => x"71", + 4504 => x"30", + 4505 => x"73", + 4506 => x"51", + 4507 => x"57", + 4508 => x"38", + 4509 => x"75", + 4510 => x"18", + 4511 => x"75", + 4512 => x"30", + 4513 => x"32", + 4514 => x"73", + 4515 => x"53", + 4516 => x"55", + 4517 => x"89", + 4518 => x"75", + 4519 => x"e4", + 4520 => x"7c", + 4521 => x"a0", + 4522 => x"38", + 4523 => x"8b", + 4524 => x"54", + 4525 => x"78", + 4526 => x"81", + 4527 => x"54", + 4528 => x"82", + 4529 => x"af", + 4530 => x"77", + 4531 => x"70", + 4532 => x"25", + 4533 => x"07", + 4534 => x"51", + 4535 => x"2e", + 4536 => x"39", + 4537 => x"80", + 4538 => x"33", + 4539 => x"73", + 4540 => x"81", + 4541 => x"81", + 4542 => x"1a", + 4543 => x"55", + 4544 => x"dc", + 4545 => x"06", + 4546 => x"55", + 4547 => x"54", + 4548 => x"81", + 4549 => x"ae", + 4550 => x"70", + 4551 => x"7d", + 4552 => x"51", + 4553 => x"2e", + 4554 => x"8b", + 4555 => x"77", + 4556 => x"30", + 4557 => x"71", + 4558 => x"53", + 4559 => x"55", + 4560 => x"38", + 4561 => x"5a", + 4562 => x"75", + 4563 => x"73", + 4564 => x"38", + 4565 => x"06", + 4566 => x"11", + 4567 => x"75", + 4568 => x"3f", + 4569 => x"08", + 4570 => x"38", + 4571 => x"33", + 4572 => x"54", + 4573 => x"e5", + 4574 => x"93", + 4575 => x"2e", + 4576 => x"1a", + 4577 => x"26", + 4578 => x"54", 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x"33", + 4638 => x"9f", + 4639 => x"ff", + 4640 => x"17", + 4641 => x"75", + 4642 => x"3f", + 4643 => x"08", + 4644 => x"39", + 4645 => x"a5", + 4646 => x"84", + 4647 => x"51", + 4648 => x"82", + 4649 => x"55", + 4650 => x"08", + 4651 => x"75", + 4652 => x"3f", + 4653 => x"08", + 4654 => x"55", + 4655 => x"c8", + 4656 => x"80", + 4657 => x"93", + 4658 => x"2e", + 4659 => x"80", + 4660 => x"85", + 4661 => x"06", + 4662 => x"80", + 4663 => x"73", + 4664 => x"81", + 4665 => x"72", + 4666 => x"ad", + 4667 => x"0b", + 4668 => x"80", + 4669 => x"39", + 4670 => x"70", + 4671 => x"53", + 4672 => x"85", + 4673 => x"73", + 4674 => x"81", + 4675 => x"72", + 4676 => x"16", + 4677 => x"2a", + 4678 => x"51", + 4679 => x"80", + 4680 => x"38", + 4681 => x"83", + 4682 => x"b4", + 4683 => x"51", + 4684 => x"82", + 4685 => x"88", + 4686 => x"dd", + 4687 => x"93", + 4688 => x"3d", + 4689 => x"3d", + 4690 => x"ff", + 4691 => x"72", + 4692 => x"5a", + 4693 => x"81", + 4694 => x"70", + 4695 => x"33", + 4696 => x"70", + 4697 => x"26", + 4698 => x"06", + 4699 => x"53", + 4700 => x"72", + 4701 => x"81", + 4702 => x"38", + 4703 => x"11", + 4704 => x"89", + 4705 => x"82", + 4706 => x"ff", + 4707 => x"51", + 4708 => x"77", + 4709 => x"38", + 4710 => x"fb", + 4711 => x"77", + 4712 => x"70", + 4713 => x"57", + 4714 => x"70", + 4715 => x"33", + 4716 => x"05", + 4717 => x"9f", + 4718 => x"54", + 4719 => x"89", + 4720 => x"70", + 4721 => x"55", + 4722 => x"13", + 4723 => x"26", + 4724 => x"13", + 4725 => x"06", + 4726 => x"30", + 4727 => x"70", + 4728 => x"07", + 4729 => x"9f", + 4730 => x"55", + 4731 => x"ff", + 4732 => x"30", + 4733 => x"70", + 4734 => x"07", + 4735 => x"9f", + 4736 => x"55", + 4737 => x"80", + 4738 => x"81", + 4739 => x"78", + 4740 => x"38", + 4741 => x"83", + 4742 => x"77", + 4743 => x"5a", + 4744 => x"39", + 4745 => x"33", + 4746 => x"93", + 4747 => x"3d", + 4748 => x"3d", + 4749 => x"80", + 4750 => x"34", + 4751 => x"17", + 4752 => x"75", + 4753 => x"3f", + 4754 => x"93", + 4755 => x"84", + 4756 => x"16", + 4757 => x"3f", + 4758 => x"08", + 4759 => x"06", + 4760 => x"73", + 4761 => x"2e", + 4762 => x"80", + 4763 => x"0b", + 4764 => x"55", + 4765 => x"e9", + 4766 => x"06", + 4767 => x"55", + 4768 => x"32", + 4769 => x"80", + 4770 => x"51", + 4771 => x"8e", + 4772 => x"33", + 4773 => x"e8", + 4774 => x"06", + 4775 => x"53", + 4776 => x"52", + 4777 => x"51", + 4778 => x"82", + 4779 => x"55", + 4780 => x"08", + 4781 => x"38", + 4782 => x"fb", + 4783 => x"86", + 4784 => x"a3", + 4785 => x"c8", + 4786 => x"93", + 4787 => x"2e", + 4788 => x"55", + 4789 => x"c8", + 4790 => x"0d", + 4791 => x"0d", + 4792 => x"05", + 4793 => x"33", + 4794 => x"74", + 4795 => x"fc", + 4796 => x"93", + 4797 => x"8b", + 4798 => x"82", + 4799 => x"24", + 4800 => x"82", + 4801 => x"10", + 4802 => x"e4", + 4803 => x"56", + 4804 => x"74", + 4805 => x"88", + 4806 => x"0c", + 4807 => x"06", + 4808 => x"57", + 4809 => x"af", + 4810 => x"33", + 4811 => x"3f", + 4812 => x"08", + 4813 => x"70", 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x"83", + 4873 => x"53", + 4874 => x"84", + 4875 => x"81", + 4876 => x"38", + 4877 => x"51", + 4878 => x"82", + 4879 => x"83", + 4880 => x"54", + 4881 => x"80", + 4882 => x"d9", + 4883 => x"93", + 4884 => x"73", + 4885 => x"80", + 4886 => x"82", + 4887 => x"c4", + 4888 => x"05", + 4889 => x"72", + 4890 => x"b4", + 4891 => x"33", + 4892 => x"80", + 4893 => x"52", + 4894 => x"8a", + 4895 => x"83", + 4896 => x"53", + 4897 => x"8b", + 4898 => x"73", + 4899 => x"80", + 4900 => x"8d", + 4901 => x"39", + 4902 => x"51", + 4903 => x"82", + 4904 => x"88", + 4905 => x"93", + 4906 => x"ff", + 4907 => x"06", + 4908 => x"72", + 4909 => x"80", + 4910 => x"d8", + 4911 => x"93", + 4912 => x"ff", + 4913 => x"72", + 4914 => x"d4", + 4915 => x"e3", + 4916 => x"c8", + 4917 => x"c2", + 4918 => x"be", + 4919 => x"c8", + 4920 => x"ff", + 4921 => x"56", + 4922 => x"83", + 4923 => x"15", + 4924 => x"71", + 4925 => x"59", + 4926 => x"77", + 4927 => x"a0", + 4928 => x"22", + 4929 => x"31", + 4930 => x"ab", + 4931 => x"c8", + 4932 => x"56", + 4933 => x"08", + 4934 => x"84", + 4935 => x"82", + 4936 => x"80", + 4937 => x"f5", + 4938 => x"83", + 4939 => x"ff", + 4940 => x"38", + 4941 => x"9f", + 4942 => x"38", + 4943 => x"56", + 4944 => x"82", + 4945 => x"13", + 4946 => x"79", + 4947 => x"79", + 4948 => x"0c", + 4949 => x"16", + 4950 => x"2e", + 4951 => x"b7", + 4952 => x"15", + 4953 => x"3f", + 4954 => x"08", + 4955 => x"06", + 4956 => x"72", + 4957 => x"88", + 4958 => x"8d", + 4959 => x"a0", + 4960 => x"15", + 4961 => x"3f", + 4962 => x"08", + 4963 => x"98", + 4964 => x"2b", + 4965 => x"88", + 4966 => x"8d", + 4967 => x"2e", + 4968 => x"a4", + 4969 => x"a8", + 4970 => x"82", + 4971 => x"06", + 4972 => x"15", + 4973 => x"94", + 4974 => x"08", + 4975 => x"08", + 4976 => x"2a", + 4977 => x"81", + 4978 => x"53", + 4979 => x"89", + 4980 => x"56", + 4981 => x"08", + 4982 => x"38", + 4983 => x"16", + 4984 => x"8c", + 4985 => x"80", + 4986 => x"34", + 4987 => x"09", + 4988 => x"92", + 4989 => x"15", + 4990 => x"3f", + 4991 => x"08", + 4992 => x"06", + 4993 => x"2e", + 4994 => x"80", + 4995 => x"1a", + 4996 => x"d9", + 4997 => x"93", + 4998 => x"ea", + 4999 => x"c8", + 5000 => x"34", + 5001 => x"51", + 5002 => x"82", + 5003 => x"83", + 5004 => x"53", + 5005 => x"d5", + 5006 => x"06", + 5007 => x"b4", + 5008 => x"ef", + 5009 => x"c8", + 5010 => x"85", + 5011 => x"09", + 5012 => x"38", + 5013 => x"51", + 5014 => x"82", + 5015 => x"86", + 5016 => x"f2", + 5017 => x"06", + 5018 => x"9c", + 5019 => x"c3", + 5020 => x"c8", + 5021 => x"0c", + 5022 => x"51", + 5023 => x"82", + 5024 => x"8c", + 5025 => x"75", + 5026 => x"f4", + 5027 => x"53", + 5028 => x"f4", + 5029 => x"16", + 5030 => x"94", + 5031 => x"56", + 5032 => x"c8", + 5033 => x"0d", + 5034 => x"0d", + 5035 => x"55", + 5036 => x"b5", + 5037 => x"80", + 5038 => x"73", + 5039 => x"53", + 5040 => x"2e", + 5041 => x"14", + 5042 => x"22", + 5043 => x"76", + 5044 => x"06", + 5045 => x"13", + 5046 => x"f9", + 5047 => x"c8", + 5048 => x"52", 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x"76", + 5108 => x"74", + 5109 => x"c3", + 5110 => x"2e", + 5111 => x"84", + 5112 => x"06", + 5113 => x"3d", + 5114 => x"ea", + 5115 => x"93", + 5116 => x"76", + 5117 => x"a0", + 5118 => x"05", + 5119 => x"55", + 5120 => x"85", + 5121 => x"90", + 5122 => x"2a", + 5123 => x"51", + 5124 => x"2e", + 5125 => x"56", + 5126 => x"38", + 5127 => x"70", + 5128 => x"55", + 5129 => x"81", + 5130 => x"52", + 5131 => x"b6", + 5132 => x"c8", + 5133 => x"88", + 5134 => x"62", + 5135 => x"d2", + 5136 => x"55", + 5137 => x"16", + 5138 => x"62", + 5139 => x"e6", + 5140 => x"52", + 5141 => x"51", + 5142 => x"7a", + 5143 => x"83", + 5144 => x"80", + 5145 => x"38", + 5146 => x"08", + 5147 => x"54", + 5148 => x"05", + 5149 => x"db", + 5150 => x"93", + 5151 => x"82", + 5152 => x"82", + 5153 => x"52", + 5154 => x"bc", + 5155 => x"c8", + 5156 => x"1b", + 5157 => x"56", + 5158 => x"75", + 5159 => x"02", + 5160 => x"70", + 5161 => x"81", + 5162 => x"59", + 5163 => x"85", + 5164 => x"9c", + 5165 => x"2a", + 5166 => x"51", + 5167 => x"2e", + 5168 => x"b2", + 5169 => x"06", + 5170 => x"2e", + 5171 => x"56", + 5172 => x"38", + 5173 => x"70", + 5174 => x"55", + 5175 => x"86", + 5176 => x"c0", + 5177 => x"b0", + 5178 => x"1a", + 5179 => x"1a", + 5180 => x"81", + 5181 => x"52", + 5182 => x"ea", + 5183 => x"c8", + 5184 => x"0c", + 5185 => x"51", + 5186 => x"82", + 5187 => x"8c", + 5188 => x"78", + 5189 => x"22", + 5190 => x"76", + 5191 => x"75", + 5192 => x"75", + 5193 => x"75", + 5194 => x"84", + 5195 => x"52", + 5196 => x"d1", + 5197 => x"85", + 5198 => x"06", + 5199 => x"80", + 5200 => x"38", + 5201 => x"80", + 5202 => x"38", + 5203 => x"94", + 5204 => x"8a", + 5205 => x"89", + 5206 => x"08", + 5207 => x"5d", + 5208 => x"55", + 5209 => x"52", + 5210 => x"fc", + 5211 => x"c8", + 5212 => x"93", + 5213 => x"26", + 5214 => x"56", + 5215 => x"09", + 5216 => x"38", + 5217 => x"7a", + 5218 => x"30", + 5219 => x"80", + 5220 => x"7d", + 5221 => x"51", + 5222 => x"38", + 5223 => x"0c", + 5224 => x"38", + 5225 => x"06", + 5226 => x"2e", + 5227 => x"52", + 5228 => x"8a", + 5229 => x"c8", + 5230 => x"82", + 5231 => x"78", + 5232 => x"93", + 5233 => x"70", + 5234 => x"55", + 5235 => x"53", + 5236 => x"7a", + 5237 => x"52", + 5238 => x"3f", + 5239 => x"08", + 5240 => x"38", + 5241 => x"80", + 5242 => x"80", + 5243 => x"55", + 5244 => x"c8", + 5245 => x"0d", + 5246 => x"0d", + 5247 => x"63", + 5248 => x"57", + 5249 => x"8f", + 5250 => x"52", + 5251 => x"99", + 5252 => x"c8", + 5253 => x"93", + 5254 => x"38", + 5255 => x"55", + 5256 => x"86", + 5257 => x"83", + 5258 => x"17", + 5259 => x"55", + 5260 => x"80", + 5261 => x"38", + 5262 => x"0b", + 5263 => x"82", + 5264 => x"39", + 5265 => x"18", + 5266 => x"83", + 5267 => x"0b", + 5268 => x"82", + 5269 => x"39", + 5270 => x"18", + 5271 => x"82", + 5272 => x"0b", + 5273 => x"81", + 5274 => x"39", + 5275 => x"18", + 5276 => x"82", + 5277 => x"17", + 5278 => x"08", + 5279 => x"79", + 5280 => x"74", + 5281 => x"2e", + 5282 => x"94", + 5283 => x"83", + 5284 => x"56", + 5285 => x"38", + 5286 => x"22", + 5287 => x"89", + 5288 => x"55", + 5289 => x"75", + 5290 => x"17", + 5291 => x"39", + 5292 => x"52", + 5293 => x"b0", + 5294 => x"c8", + 5295 => x"75", + 5296 => x"38", + 5297 => x"fe", + 5298 => x"98", + 5299 => x"17", + 5300 => x"51", + 5301 => x"82", + 5302 => x"80", + 5303 => x"38", + 5304 => x"08", + 5305 => x"2a", + 5306 => x"80", + 5307 => x"38", + 5308 => x"8a", + 5309 => x"56", + 5310 => x"27", + 5311 => x"7b", + 5312 => x"54", + 5313 => x"52", + 5314 => x"33", + 5315 => x"ef", + 5316 => x"c8", + 5317 => x"38", + 5318 => x"70", + 5319 => x"56", + 5320 => x"9b", + 5321 => x"08", + 5322 => x"74", + 5323 => x"38", + 5324 => x"a8", + 5325 => x"84", + 5326 => x"51", + 5327 => x"79", + 5328 => x"80", + 5329 => x"17", + 5330 => x"80", + 5331 => x"17", + 5332 => x"2b", + 5333 => x"80", + 5334 => x"81", + 5335 => x"08", + 5336 => x"52", + 5337 => x"33", + 5338 => x"ec", + 5339 => x"c8", + 5340 => x"38", + 5341 => x"80", + 5342 => x"74", + 5343 => x"81", + 5344 => x"a8", + 5345 => x"81", + 5346 => x"55", + 5347 => x"82", + 5348 => x"fd", + 5349 => x"9c", + 5350 => x"17", + 5351 => x"06", + 5352 => x"31", + 5353 => x"76", + 5354 => x"78", + 5355 => x"94", + 5356 => x"ff", + 5357 => x"05", + 5358 => x"cb", + 5359 => x"76", + 5360 => x"17", + 5361 => x"1d", + 5362 => x"18", + 5363 => x"5d", + 5364 => x"b7", + 5365 => x"75", + 5366 => x"0c", + 5367 => x"04", + 5368 => x"7f", + 5369 => x"5f", + 5370 => x"80", + 5371 => x"3d", + 5372 => x"76", + 5373 => x"3f", + 5374 => x"08", + 5375 => x"c8", + 5376 => x"91", + 5377 => x"74", + 5378 => x"38", + 5379 => x"82", + 5380 => x"33", + 5381 => x"70", + 5382 => x"56", + 5383 => x"74", + 5384 => x"ee", + 5385 => x"82", + 5386 => x"34", + 5387 => x"e2", + 5388 => x"91", + 5389 => x"56", + 5390 => x"81", + 5391 => x"34", + 5392 => x"ce", + 5393 => x"91", + 5394 => x"56", + 5395 => x"81", + 5396 => x"34", + 5397 => x"ba", + 5398 => x"91", + 5399 => x"56", + 5400 => x"94", + 5401 => x"55", + 5402 => x"08", + 5403 => x"94", + 5404 => x"59", + 5405 => x"83", + 5406 => x"17", + 5407 => x"ff", + 5408 => x"74", + 5409 => x"7d", + 5410 => x"ff", + 5411 => x"2a", + 5412 => x"7a", + 5413 => x"75", + 5414 => x"17", + 5415 => x"a3", + 5416 => x"76", + 5417 => x"3f", + 5418 => x"08", + 5419 => x"98", + 5420 => x"76", + 5421 => x"3f", + 5422 => x"08", + 5423 => x"2e", + 5424 => x"74", + 5425 => x"df", + 5426 => x"2e", + 5427 => x"74", + 5428 => x"88", + 5429 => x"38", + 5430 => x"0c", + 5431 => x"70", + 5432 => x"58", + 5433 => x"a5", + 5434 => x"9c", + 5435 => x"a8", + 5436 => x"81", + 5437 => x"55", + 5438 => x"82", + 5439 => x"fe", + 5440 => x"17", + 5441 => x"06", + 5442 => x"18", + 5443 => x"08", + 5444 => x"cd", + 5445 => x"93", + 5446 => x"2e", + 5447 => x"82", + 5448 => x"1b", + 5449 => x"5b", + 5450 => x"2e", + 5451 => x"79", + 5452 => x"11", + 5453 => x"56", + 5454 => x"85", + 5455 => x"31", + 5456 => x"77", + 5457 => x"7d", + 5458 => x"52", + 5459 => x"3f", + 5460 => x"08", + 5461 => x"9c", + 5462 => x"31", + 5463 => x"27", + 5464 => x"80", + 5465 => x"80", + 5466 => x"a8", + 5467 => x"b9", + 5468 => x"33", + 5469 => x"55", + 5470 => x"34", + 5471 => x"56", + 5472 => x"9c", + 5473 => x"2e", + 5474 => x"17", + 5475 => x"08", + 5476 => x"81", + 5477 => x"a8", + 5478 => x"81", + 5479 => x"55", + 5480 => x"82", + 5481 => x"fd", + 5482 => x"9c", + 5483 => x"17", + 5484 => x"06", + 5485 => x"31", + 5486 => x"76", + 5487 => x"78", + 5488 => x"7b", + 5489 => x"08", + 5490 => x"17", + 5491 => x"c7", + 5492 => x"17", + 5493 => x"07", + 5494 => x"18", + 5495 => x"31", + 5496 => x"7e", + 5497 => x"94", + 5498 => x"70", + 5499 => x"8c", + 5500 => x"58", + 5501 => x"76", + 5502 => x"75", + 5503 => x"18", + 5504 => x"f6", + 5505 => x"33", + 5506 => x"55", + 5507 => x"34", + 5508 => x"82", + 5509 => x"8f", + 5510 => x"f7", + 5511 => x"8c", + 5512 => x"53", + 5513 => x"f1", + 5514 => x"93", + 5515 => x"82", + 5516 => x"81", + 5517 => x"18", + 5518 => x"2a", + 5519 => x"51", + 5520 => x"80", + 5521 => x"38", + 5522 => x"55", + 5523 => x"a7", + 5524 => x"9c", + 5525 => x"a8", + 5526 => x"81", + 5527 => x"55", + 5528 => x"81", + 5529 => x"c8", + 5530 => x"38", + 5531 => x"80", + 5532 => x"74", + 5533 => x"a0", + 5534 => x"79", + 5535 => x"3f", + 5536 => x"08", + 5537 => x"c8", + 5538 => x"38", + 5539 => x"8b", + 5540 => x"07", + 5541 => x"8b", + 5542 => x"18", + 5543 => x"52", + 5544 => x"d9", + 5545 => x"18", + 5546 => x"16", + 5547 => x"3f", + 5548 => x"0a", + 5549 => x"51", + 5550 => x"76", + 5551 => x"51", + 5552 => x"79", + 5553 => x"83", + 5554 => x"51", + 5555 => x"82", + 5556 => x"90", + 5557 => x"bf", + 5558 => x"74", + 5559 => x"76", + 5560 => x"93", + 5561 => x"3d", + 5562 => x"3d", + 5563 => x"52", + 5564 => x"3f", + 5565 => x"08", + 5566 => x"c8", + 5567 => x"86", + 5568 => x"52", + 5569 => x"a1", + 5570 => x"c8", + 5571 => x"93", + 5572 => x"38", + 5573 => x"08", + 5574 => x"82", + 5575 => x"86", + 5576 => x"fe", + 5577 => x"3d", + 5578 => x"3f", + 5579 => x"0b", + 5580 => x"08", + 5581 => x"82", + 5582 => x"82", + 5583 => x"80", + 5584 => x"93", + 5585 => x"3d", + 5586 => x"3d", + 5587 => x"93", + 5588 => x"52", + 5589 => x"e7", + 5590 => x"93", + 5591 => x"82", + 5592 => x"80", + 5593 => x"58", + 5594 => x"3d", + 5595 => x"e1", + 5596 => x"93", + 5597 => x"82", + 5598 => x"be", + 5599 => x"c7", + 5600 => x"98", + 5601 => x"73", + 5602 => x"38", + 5603 => x"12", + 5604 => x"39", + 5605 => x"33", + 5606 => x"70", + 5607 => x"55", + 5608 => x"2e", + 5609 => x"7f", + 5610 => x"54", + 5611 => x"82", + 5612 => x"94", + 5613 => x"39", + 5614 => x"84", + 5615 => x"06", + 5616 => x"55", + 5617 => x"c8", + 5618 => x"0d", + 5619 => x"0d", + 5620 => x"a3", + 5621 => x"5c", + 5622 => x"80", + 5623 => x"ff", + 5624 => x"a2", + 5625 => x"f5", + 5626 => x"c8", + 5627 => x"93", + 5628 => x"93", + 5629 => x"7b", + 5630 => x"08", + 5631 => x"56", + 5632 => x"2e", + 5633 => x"96", + 5634 => x"3d", + 5635 => x"a0", + 5636 => x"d1", + 5637 => x"93", + 5638 => x"82", + 5639 => x"81", + 5640 => x"52", + 5641 => x"a0", + 5642 => x"c8", + 5643 => x"93", + 5644 => x"cb", + 5645 => x"7e", + 5646 => x"3f", + 5647 => x"08", + 5648 => x"7a", + 5649 => x"3f", + 5650 => x"08", + 5651 => x"c8", + 5652 => x"38", + 5653 => x"52", + 5654 => x"f1", + 5655 => x"c8", + 5656 => x"93", + 5657 => x"38", + 5658 => x"51", + 5659 => x"82", + 5660 => x"75", + 5661 => x"76", + 5662 => x"d2", + 5663 => x"93", + 5664 => x"82", + 5665 => x"80", + 5666 => x"76", + 5667 => x"81", + 5668 => x"82", + 5669 => x"ef", + 5670 => x"ff", + 5671 => x"d4", + 5672 => x"ee", + 5673 => x"3d", + 5674 => x"81", + 5675 => x"52", + 5676 => x"73", + 5677 => x"38", + 5678 => x"16", + 5679 => x"51", + 5680 => x"f4", + 5681 => x"54", + 5682 => x"85", + 5683 => x"af", + 5684 => x"2e", + 5685 => x"58", + 5686 => x"3d", + 5687 => x"18", + 5688 => x"58", + 5689 => x"14", + 5690 => x"75", + 5691 => x"19", + 5692 => x"11", + 5693 => x"74", + 5694 => x"74", + 5695 => x"76", + 5696 => x"78", + 5697 => x"81", + 5698 => x"ff", + 5699 => x"08", + 5700 => x"af", + 5701 => x"70", + 5702 => x"33", + 5703 => x"81", + 5704 => x"70", + 5705 => x"52", + 5706 => x"57", + 5707 => x"2e", + 5708 => x"16", + 5709 => x"33", + 5710 => x"73", + 5711 => x"16", + 5712 => x"26", + 5713 => x"58", + 5714 => x"94", + 5715 => x"54", + 5716 => x"70", + 5717 => x"34", + 5718 => x"75", + 5719 => x"38", + 5720 => x"81", + 5721 => x"81", + 5722 => x"83", + 5723 => x"76", + 5724 => x"3d", + 5725 => x"1a", + 5726 => x"33", + 5727 => x"05", + 5728 => x"79", + 5729 => x"80", + 5730 => x"82", + 5731 => x"a1", + 5732 => x"f4", + 5733 => x"60", + 5734 => x"05", + 5735 => x"59", + 5736 => x"3f", + 5737 => x"08", + 5738 => x"c8", + 5739 => x"91", + 5740 => x"79", + 5741 => x"38", + 5742 => x"f9", + 5743 => x"08", + 5744 => x"38", + 5745 => x"70", + 5746 => x"81", + 5747 => x"56", + 5748 => x"8c", + 5749 => x"94", + 5750 => x"80", + 5751 => x"0c", + 5752 => x"2e", + 5753 => x"7c", + 5754 => x"70", + 5755 => x"51", + 5756 => x"2e", + 5757 => x"52", + 5758 => x"ff", + 5759 => x"82", + 5760 => x"ff", + 5761 => x"70", + 5762 => x"ff", + 5763 => x"82", + 5764 => x"75", + 5765 => x"78", + 5766 => x"94", + 5767 => x"94", + 5768 => x"98", + 5769 => x"58", + 5770 => x"88", + 5771 => x"75", + 5772 => x"52", + 5773 => x"a7", + 5774 => x"c8", + 5775 => x"93", + 5776 => x"2e", + 5777 => x"8b", + 5778 => x"91", + 5779 => x"55", + 5780 => x"82", + 5781 => x"ff", + 5782 => x"06", + 5783 => x"0b", + 5784 => x"81", + 5785 => x"39", + 5786 => x"08", + 5787 => x"75", + 5788 => x"75", + 5789 => x"a1", + 5790 => x"27", + 5791 => x"77", + 5792 => x"18", + 5793 => x"19", + 5794 => x"33", + 5795 => x"70", + 5796 => x"57", + 5797 => x"80", + 5798 => x"75", + 5799 => x"c8", + 5800 => x"93", + 5801 => x"82", + 5802 => x"94", + 5803 => x"c8", + 5804 => x"39", + 5805 => x"51", + 5806 => x"82", + 5807 => x"56", + 5808 => x"81", + 5809 => x"76", + 5810 => x"7c", + 5811 => x"08", + 5812 => x"38", + 5813 => x"18", + 5814 => x"81", + 5815 => x"98", + 5816 => x"79", + 5817 => x"38", + 5818 => x"18", + 5819 => x"77", + 5820 => x"55", + 5821 => x"a1", + 5822 => x"7c", + 5823 => x"3f", + 5824 => x"08", + 5825 => x"0b", + 5826 => x"82", + 5827 => x"39", + 5828 => x"82", + 5829 => x"05", + 5830 => x"08", + 5831 => x"27", + 5832 => x"17", + 5833 => x"0c", + 5834 => x"80", + 5835 => x"74", + 5836 => x"94", + 5837 => x"ff", + 5838 => x"80", + 5839 => x"38", + 5840 => x"7b", + 5841 => x"38", + 5842 => x"70", + 5843 => x"5c", + 5844 => x"b0", + 5845 => x"9c", + 5846 => x"a8", + 5847 => x"81", + 5848 => x"55", + 5849 => x"3f", + 5850 => x"08", + 5851 => x"38", + 5852 => x"18", + 5853 => x"bd", + 5854 => x"33", + 5855 => x"55", + 5856 => x"34", + 5857 => x"53", + 5858 => x"7c", + 5859 => x"52", + 5860 => x"eb", + 5861 => x"c8", + 5862 => x"93", + 5863 => x"91", + 5864 => x"55", + 5865 => x"0b", + 5866 => x"81", + 5867 => x"7a", + 5868 => x"79", + 5869 => x"93", + 5870 => x"3d", + 5871 => x"3d", + 5872 => x"89", + 5873 => x"2e", + 5874 => x"80", + 5875 => x"fc", + 5876 => x"3d", + 5877 => x"de", + 5878 => x"93", + 5879 => x"82", + 5880 => x"80", + 5881 => x"76", + 5882 => x"75", + 5883 => x"3f", + 5884 => x"08", + 5885 => x"c8", + 5886 => x"38", + 5887 => x"70", + 5888 => x"57", + 5889 => x"a6", + 5890 => x"33", + 5891 => x"70", + 5892 => x"55", + 5893 => x"2e", + 5894 => x"16", + 5895 => x"51", + 5896 => x"82", + 5897 => x"88", + 5898 => x"39", + 5899 => x"95", + 5900 => x"86", + 5901 => x"17", + 5902 => x"75", + 5903 => x"3f", + 5904 => x"08", + 5905 => x"2e", + 5906 => x"83", + 5907 => x"74", + 5908 => x"38", + 5909 => x"74", + 5910 => x"93", + 5911 => x"3d", + 5912 => x"3d", + 5913 => x"3d", + 5914 => x"70", + 5915 => x"b9", + 5916 => x"c8", + 5917 => x"93", + 5918 => x"38", + 5919 => x"08", + 5920 => x"82", + 5921 => x"86", + 5922 => x"fb", + 5923 => x"79", + 5924 => x"05", + 5925 => x"56", + 5926 => x"3f", + 5927 => x"08", + 5928 => x"c8", + 5929 => x"38", + 5930 => x"82", + 5931 => x"52", + 5932 => x"c5", + 5933 => x"c8", + 5934 => x"39", + 5935 => x"51", + 5936 => x"82", + 5937 => x"53", + 5938 => x"08", + 5939 => x"81", + 5940 => x"80", + 5941 => x"38", + 5942 => x"51", + 5943 => x"72", + 5944 => x"c9", + 5945 => x"93", + 5946 => x"82", + 5947 => x"84", + 5948 => x"06", + 5949 => x"53", + 5950 => x"c8", + 5951 => x"0d", + 5952 => x"0d", + 5953 => x"53", + 5954 => x"53", + 5955 => x"54", + 5956 => x"82", + 5957 => x"55", + 5958 => x"08", + 5959 => x"52", + 5960 => x"e9", + 5961 => x"c8", + 5962 => x"93", + 5963 => x"38", + 5964 => x"05", + 5965 => x"2b", + 5966 => x"80", + 5967 => x"86", + 5968 => x"75", + 5969 => x"38", + 5970 => x"3d", + 5971 => x"d0", + 5972 => x"82", + 5973 => x"93", + 5974 => x"f2", + 5975 => x"63", + 5976 => x"53", + 5977 => x"05", + 5978 => x"51", + 5979 => x"82", + 5980 => x"59", + 5981 => x"08", + 5982 => x"7a", + 5983 => x"08", + 5984 => x"fe", + 5985 => x"90", + 5986 => x"26", + 5987 => x"15", + 5988 => x"81", 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x"82", + 6048 => x"90", + 6049 => x"f8", + 6050 => x"8b", + 6051 => x"53", + 6052 => x"e0", + 6053 => x"93", + 6054 => x"82", + 6055 => x"8a", + 6056 => x"33", + 6057 => x"2e", + 6058 => x"56", + 6059 => x"90", + 6060 => x"81", + 6061 => x"06", + 6062 => x"87", + 6063 => x"2e", + 6064 => x"94", + 6065 => x"19", + 6066 => x"bc", + 6067 => x"08", + 6068 => x"53", + 6069 => x"52", + 6070 => x"be", + 6071 => x"93", + 6072 => x"80", + 6073 => x"0c", + 6074 => x"98", + 6075 => x"77", + 6076 => x"f4", + 6077 => x"c8", + 6078 => x"c8", + 6079 => x"70", + 6080 => x"07", + 6081 => x"57", + 6082 => x"93", + 6083 => x"2e", + 6084 => x"83", + 6085 => x"76", + 6086 => x"55", + 6087 => x"08", + 6088 => x"98", + 6089 => x"75", + 6090 => x"ff", + 6091 => x"82", + 6092 => x"57", + 6093 => x"8c", + 6094 => x"18", + 6095 => x"07", + 6096 => x"19", + 6097 => x"38", + 6098 => x"55", + 6099 => x"ab", + 6100 => x"9c", + 6101 => x"a8", + 6102 => x"81", + 6103 => x"55", + 6104 => x"3f", + 6105 => x"08", + 6106 => x"38", + 6107 => x"39", + 6108 => x"80", + 6109 => x"74", + 6110 => x"76", + 6111 => x"38", + 6112 => x"34", + 6113 => x"39", + 6114 => x"82", + 6115 => x"8a", + 6116 => x"e3", + 6117 => x"fb", + 6118 => x"96", + 6119 => x"53", + 6120 => x"a4", + 6121 => x"3d", + 6122 => x"3f", + 6123 => x"08", + 6124 => x"c8", + 6125 => x"38", + 6126 => x"51", + 6127 => x"3f", + 6128 => x"52", + 6129 => x"05", + 6130 => x"3f", + 6131 => x"08", + 6132 => x"52", + 6133 => x"9a", + 6134 => x"ae", + 6135 => x"f7", + 6136 => x"85", + 6137 => x"06", + 6138 => x"73", + 6139 => x"38", + 6140 => x"82", + 6141 => x"fb", + 6142 => x"95", + 6143 => x"80", + 6144 => x"70", + 6145 => x"55", + 6146 => x"85", + 6147 => x"90", + 6148 => x"d2", + 6149 => x"06", + 6150 => x"2e", + 6151 => x"56", + 6152 => x"38", + 6153 => x"51", + 6154 => x"82", + 6155 => x"02", + 6156 => x"d2", + 6157 => x"84", + 6158 => x"06", + 6159 => x"57", + 6160 => x"80", + 6161 => x"fb", + 6162 => x"95", + 6163 => x"78", + 6164 => x"14", + 6165 => x"80", + 6166 => x"fb", + 6167 => x"95", + 6168 => x"59", + 6169 => x"fb", + 6170 => x"95", + 6171 => x"52", + 6172 => x"52", + 6173 => x"3f", + 6174 => x"08", + 6175 => x"c8", + 6176 => x"38", + 6177 => x"08", + 6178 => x"c6", + 6179 => x"93", + 6180 => x"82", + 6181 => x"83", + 6182 => x"75", + 6183 => x"30", + 6184 => x"9f", + 6185 => x"58", + 6186 => x"80", + 6187 => x"fb", + 6188 => x"94", + 6189 => x"3d", + 6190 => x"c9", + 6191 => x"93", + 6192 => x"93", + 6193 => x"70", + 6194 => x"08", + 6195 => x"79", + 6196 => x"07", + 6197 => x"06", + 6198 => x"56", + 6199 => x"2e", + 6200 => x"fb", + 6201 => x"94", + 6202 => x"53", + 6203 => x"3d", + 6204 => x"ff", + 6205 => x"82", + 6206 => x"56", + 6207 => x"77", + 6208 => x"8b", + 6209 => x"c8", + 6210 => x"fb", + 6211 => x"93", + 6212 => x"82", + 6213 => x"9f", + 6214 => x"ea", + 6215 => x"53", + 6216 => x"05", + 6217 => x"51", + 6218 => x"82", + 6219 => x"55", + 6220 => x"08", + 6221 => x"77", + 6222 => x"98", + 6223 => x"51", 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x"93", + 6283 => x"38", + 6284 => x"96", + 6285 => x"ae", + 6286 => x"53", + 6287 => x"51", + 6288 => x"63", + 6289 => x"8b", + 6290 => x"54", + 6291 => x"15", + 6292 => x"ff", + 6293 => x"82", + 6294 => x"55", + 6295 => x"53", + 6296 => x"3d", + 6297 => x"ff", + 6298 => x"74", + 6299 => x"0c", + 6300 => x"04", + 6301 => x"a8", + 6302 => x"51", + 6303 => x"82", + 6304 => x"ff", + 6305 => x"a8", + 6306 => x"d1", + 6307 => x"c8", + 6308 => x"93", + 6309 => x"d7", + 6310 => x"a8", + 6311 => x"a7", + 6312 => x"51", + 6313 => x"82", + 6314 => x"55", + 6315 => x"08", + 6316 => x"02", + 6317 => x"33", + 6318 => x"54", + 6319 => x"83", + 6320 => x"74", + 6321 => x"a0", + 6322 => x"08", + 6323 => x"ff", + 6324 => x"ff", + 6325 => x"ac", + 6326 => x"d4", + 6327 => x"3d", + 6328 => x"ff", + 6329 => x"a9", + 6330 => x"73", + 6331 => x"3f", + 6332 => x"08", + 6333 => x"c8", + 6334 => x"62", + 6335 => x"81", + 6336 => x"84", + 6337 => x"3d", + 6338 => x"38", + 6339 => x"84", + 6340 => x"06", + 6341 => x"a7", + 6342 => x"05", + 6343 => x"3f", + 6344 => x"08", + 6345 => x"c8", + 6346 => x"38", + 6347 => x"53", + 6348 => x"95", + 6349 => x"16", + 6350 => x"ed", + 6351 => x"05", + 6352 => x"34", + 6353 => x"70", + 6354 => x"81", + 6355 => x"57", + 6356 => x"76", + 6357 => x"73", + 6358 => x"77", + 6359 => x"83", + 6360 => x"16", + 6361 => x"2a", + 6362 => x"51", + 6363 => x"80", + 6364 => x"38", + 6365 => x"80", + 6366 => x"52", + 6367 => x"bf", + 6368 => x"93", + 6369 => x"77", + 6370 => x"b2", + 6371 => x"82", + 6372 => x"80", + 6373 => x"82", + 6374 => x"52", + 6375 => x"ae", + 6376 => x"93", + 6377 => x"d4", + 6378 => x"82", + 6379 => x"bf", + 6380 => x"33", + 6381 => x"2e", + 6382 => x"92", + 6383 => x"75", + 6384 => x"ff", + 6385 => x"77", + 6386 => x"83", + 6387 => x"9f", + 6388 => x"d4", + 6389 => x"89", + 6390 => x"c8", + 6391 => x"93", + 6392 => x"38", + 6393 => x"ae", + 6394 => x"93", + 6395 => x"74", + 6396 => x"0c", + 6397 => x"04", + 6398 => x"02", + 6399 => x"33", + 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x"54", + 6518 => x"73", + 6519 => x"38", + 6520 => x"73", + 6521 => x"38", + 6522 => x"18", + 6523 => x"ff", + 6524 => x"82", + 6525 => x"7b", + 6526 => x"93", + 6527 => x"3d", + 6528 => x"3d", + 6529 => x"9a", + 6530 => x"05", + 6531 => x"51", + 6532 => x"82", + 6533 => x"55", + 6534 => x"08", + 6535 => x"8b", + 6536 => x"9a", + 6537 => x"05", + 6538 => x"a1", + 6539 => x"70", + 6540 => x"57", + 6541 => x"74", + 6542 => x"38", + 6543 => x"81", + 6544 => x"81", + 6545 => x"56", + 6546 => x"3f", + 6547 => x"08", + 6548 => x"38", + 6549 => x"70", + 6550 => x"ff", + 6551 => x"82", + 6552 => x"80", + 6553 => x"75", + 6554 => x"07", + 6555 => x"4c", + 6556 => x"80", + 6557 => x"16", + 6558 => x"26", + 6559 => x"16", + 6560 => x"ff", + 6561 => x"80", + 6562 => x"87", + 6563 => x"f8", + 6564 => x"75", + 6565 => x"38", + 6566 => x"fc", + 6567 => x"a6", + 6568 => x"93", + 6569 => x"38", + 6570 => x"27", + 6571 => x"89", + 6572 => x"8b", + 6573 => x"27", + 6574 => x"55", + 6575 => x"81", + 6576 => x"93", + 6577 => x"77", + 6578 => x"05", + 6579 => x"55", + 6580 => x"34", + 6581 => x"9a", + 6582 => x"ff", + 6583 => x"75", + 6584 => x"17", + 6585 => x"56", + 6586 => x"9f", + 6587 => x"38", + 6588 => x"54", + 6589 => x"81", + 6590 => x"ea", + 6591 => x"2e", + 6592 => x"9f", + 6593 => x"12", + 6594 => x"52", + 6595 => x"a0", + 6596 => x"06", + 6597 => x"17", + 6598 => x"2e", + 6599 => x"15", + 6600 => x"54", + 6601 => x"ee", + 6602 => x"80", + 6603 => x"8f", + 6604 => x"55", + 6605 => x"3f", + 6606 => x"08", + 6607 => x"c8", + 6608 => x"38", + 6609 => x"51", + 6610 => x"3f", + 6611 => x"08", + 6612 => x"c8", + 6613 => x"76", + 6614 => x"38", + 6615 => x"3d", + 6616 => x"52", + 6617 => x"a4", + 6618 => x"39", + 6619 => x"74", + 6620 => x"81", + 6621 => x"34", + 6622 => x"a7", + 6623 => x"93", + 6624 => x"80", + 6625 => x"93", + 6626 => x"2e", + 6627 => x"80", + 6628 => x"54", + 6629 => x"80", + 6630 => x"52", + 6631 => x"05", + 6632 => x"b2", + 6633 => x"c8", + 6634 => x"93", + 6635 => x"38", + 6636 => x"93", + 6637 => x"65", + 6638 => x"91", + 6639 => x"88", + 6640 => x"34", + 6641 => x"3d", + 6642 => x"52", + 6643 => x"a3", + 6644 => x"54", + 6645 => x"15", + 6646 => x"ff", + 6647 => x"82", + 6648 => x"54", + 6649 => x"82", + 6650 => x"9a", + 6651 => x"f1", + 6652 => x"63", + 6653 => x"80", + 6654 => x"94", + 6655 => x"55", + 6656 => x"5c", + 6657 => x"3f", + 6658 => x"08", + 6659 => x"c8", + 6660 => x"91", + 6661 => x"76", + 6662 => x"38", + 6663 => x"b7", + 6664 => x"2e", + 6665 => x"18", + 6666 => x"90", + 6667 => x"81", + 6668 => x"06", + 6669 => x"73", + 6670 => x"54", + 6671 => x"82", + 6672 => x"39", + 6673 => x"84", + 6674 => x"11", + 6675 => x"2b", + 6676 => x"54", + 6677 => x"fe", + 6678 => x"ff", + 6679 => x"70", + 6680 => x"07", + 6681 => x"93", + 6682 => x"62", + 6683 => x"5d", + 6684 => x"55", + 6685 => x"79", + 6686 => x"98", + 6687 => x"26", + 6688 => x"59", + 6689 => x"5d", + 6690 => x"52", + 6691 => x"a6", + 6692 => x"93", + 6693 => x"16", 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x"d1", + 6753 => x"c8", + 6754 => x"82", + 6755 => x"55", + 6756 => x"2e", + 6757 => x"08", + 6758 => x"34", + 6759 => x"06", + 6760 => x"79", + 6761 => x"cb", + 6762 => x"c8", + 6763 => x"06", + 6764 => x"56", + 6765 => x"74", + 6766 => x"75", + 6767 => x"81", + 6768 => x"8a", + 6769 => x"8d", + 6770 => x"fc", + 6771 => x"52", + 6772 => x"9d", + 6773 => x"93", + 6774 => x"38", + 6775 => x"93", + 6776 => x"80", + 6777 => x"38", + 6778 => x"67", + 6779 => x"80", + 6780 => x"81", + 6781 => x"5e", + 6782 => x"86", + 6783 => x"26", + 6784 => x"81", + 6785 => x"8b", + 6786 => x"78", + 6787 => x"80", + 6788 => x"93", + 6789 => x"39", + 6790 => x"51", + 6791 => x"3f", + 6792 => x"08", + 6793 => x"6e", + 6794 => x"fe", + 6795 => x"82", + 6796 => x"7e", + 6797 => x"08", + 6798 => x"70", + 6799 => x"25", + 6800 => x"08", + 6801 => x"93", + 6802 => x"80", + 6803 => x"52", + 6804 => x"46", + 6805 => x"75", + 6806 => x"98", + 6807 => x"53", + 6808 => x"51", + 6809 => x"3f", + 6810 => x"93", + 6811 => x"e5", + 6812 => x"2a", + 6813 => x"51", + 6814 => x"74", + 6815 => x"81", + 6816 => x"bf", + 6817 => x"63", + 6818 => x"c9", + 6819 => x"31", + 6820 => x"80", + 6821 => x"8a", + 6822 => x"57", + 6823 => x"26", + 6824 => x"7c", + 6825 => x"81", + 6826 => x"74", + 6827 => x"38", + 6828 => x"55", + 6829 => x"88", + 6830 => x"06", + 6831 => x"38", + 6832 => x"39", + 6833 => x"55", + 6834 => x"42", + 6835 => x"8a", + 6836 => x"59", + 6837 => x"09", + 6838 => x"f1", + 6839 => x"38", + 6840 => x"78", + 6841 => x"0b", + 6842 => x"70", + 6843 => x"58", + 6844 => x"80", + 6845 => x"74", + 6846 => x"38", + 6847 => x"10", + 6848 => x"70", + 6849 => x"5a", + 6850 => x"2e", + 6851 => x"75", + 6852 => x"78", + 6853 => x"fe", + 6854 => x"82", + 6855 => x"82", + 6856 => x"10", + 6857 => x"54", + 6858 => x"56", + 6859 => x"3f", + 6860 => x"08", + 6861 => x"80", + 6862 => x"8a", + 6863 => x"fd", + 6864 => x"75", + 6865 => x"38", + 6866 => x"89", + 6867 => x"38", + 6868 => x"78", + 6869 => x"0b", + 6870 => x"70", + 6871 => x"58", + 6872 => x"80", + 6873 => x"74", + 6874 => x"38", + 6875 => x"10", + 6876 => x"70", + 6877 => x"5a", + 6878 => x"2e", + 6879 => x"75", + 6880 => x"78", + 6881 => x"fe", + 6882 => x"82", + 6883 => x"10", + 6884 => x"82", + 6885 => x"9f", + 6886 => x"38", + 6887 => x"93", + 6888 => x"29", + 6889 => x"2a", + 6890 => x"58", + 6891 => x"76", + 6892 => x"51", + 6893 => x"3f", + 6894 => x"08", + 6895 => x"53", + 6896 => x"80", + 6897 => x"ef", + 6898 => x"c8", + 6899 => x"ff", + 6900 => x"1b", + 6901 => x"05", + 6902 => x"05", + 6903 => x"72", + 6904 => x"52", + 6905 => x"40", + 6906 => x"09", + 6907 => x"38", + 6908 => x"18", + 6909 => x"39", + 6910 => x"78", + 6911 => x"70", + 6912 => x"55", + 6913 => x"87", + 6914 => x"7b", + 6915 => x"79", + 6916 => x"31", + 6917 => x"f2", + 6918 => x"93", + 6919 => x"61", + 6920 => x"81", + 6921 => x"82", + 6922 => x"83", + 6923 => x"91", + 6924 => x"38", + 6925 => x"58", + 6926 => x"38", + 6927 => x"95", + 6928 => x"2e", + 6929 => x"80", + 6930 => x"ff", + 6931 => x"b4", + 6932 => x"38", + 6933 => x"74", + 6934 => x"86", + 6935 => x"fc", + 6936 => x"81", + 6937 => x"55", + 6938 => x"86", + 6939 => x"fc", + 6940 => x"8b", + 6941 => x"58", + 6942 => x"27", + 6943 => x"8e", + 6944 => x"39", + 6945 => x"26", + 6946 => x"8b", + 6947 => x"58", + 6948 => x"27", + 6949 => x"8e", + 6950 => x"39", + 6951 => x"81", + 6952 => x"06", + 6953 => x"55", + 6954 => x"26", + 6955 => x"8e", + 6956 => x"a1", + 6957 => x"80", + 6958 => x"ff", + 6959 => x"8b", + 6960 => x"b4", + 6961 => x"ff", + 6962 => x"7d", + 6963 => x"51", + 6964 => x"3f", + 6965 => x"05", + 6966 => x"ff", + 6967 => x"8e", + 6968 => x"98", + 6969 => x"7f", + 6970 => x"61", + 6971 => x"30", + 6972 => x"84", + 6973 => x"51", + 6974 => x"51", + 6975 => x"3f", + 6976 => x"ff", + 6977 => x"02", + 6978 => x"22", + 6979 => x"51", + 6980 => x"3f", + 6981 => x"52", + 6982 => x"ff", + 6983 => x"f8", + 6984 => x"34", + 6985 => x"1f", + 6986 => x"b0", + 6987 => x"52", + 6988 => x"ff", + 6989 => x"63", + 6990 => x"51", + 6991 => x"3f", + 6992 => x"09", + 6993 => x"cf", + 6994 => x"b2", + 6995 => x"c3", + 6996 => x"98", + 6997 => x"52", + 6998 => x"ff", + 6999 => x"82", + 7000 => x"51", + 7001 => x"3f", + 7002 => x"1f", + 7003 => x"ec", + 7004 => x"b2", + 7005 => x"97", + 7006 => x"80", + 7007 => x"05", + 7008 => x"80", + 7009 => x"93", + 7010 => x"c0", + 7011 => x"1f", + 7012 => x"95", + 7013 => x"82", + 7014 => x"52", + 7015 => x"ff", + 7016 => x"7b", + 7017 => x"06", + 7018 => x"51", + 7019 => x"3f", + 7020 => x"a4", + 7021 => x"7f", + 7022 => x"93", + 7023 => x"d4", + 7024 => x"51", + 7025 => x"3f", + 7026 => x"52", + 7027 => x"51", + 7028 => x"3f", + 7029 => x"53", + 7030 => x"51", + 7031 => x"3f", + 7032 => x"93", + 7033 => x"ed", + 7034 => x"2e", + 7035 => x"80", + 7036 => x"54", + 7037 => x"53", + 7038 => x"51", + 7039 => x"3f", + 7040 => x"52", + 7041 => x"97", + 7042 => x"8b", + 7043 => x"52", + 7044 => x"96", + 7045 => x"8a", + 7046 => x"52", + 7047 => x"51", + 7048 => x"3f", + 7049 => x"83", + 7050 => x"ff", + 7051 => x"82", + 7052 => x"1f", + 7053 => x"c2", + 7054 => x"d5", + 7055 => x"1f", + 7056 => x"98", + 7057 => x"63", + 7058 => x"7e", + 7059 => x"ff", + 7060 => x"81", + 7061 => x"05", + 7062 => x"79", + 7063 => x"f8", + 7064 => x"80", + 7065 => x"ff", + 7066 => x"7f", + 7067 => x"61", + 7068 => x"81", + 7069 => x"f8", + 7070 => x"ff", + 7071 => x"ff", + 7072 => x"51", + 7073 => x"3f", + 7074 => x"88", + 7075 => x"95", + 7076 => x"39", + 7077 => x"f8", + 7078 => x"2e", + 7079 => x"55", + 7080 => x"51", + 7081 => x"3f", + 7082 => x"57", + 7083 => x"83", + 7084 => x"76", + 7085 => x"7e", + 7086 => x"ff", + 7087 => x"82", + 7088 => x"82", + 7089 => x"53", + 7090 => x"51", + 7091 => x"3f", + 7092 => x"78", + 7093 => x"74", + 7094 => x"1b", + 7095 => x"2e", + 7096 => x"78", + 7097 => x"2e", + 7098 => x"55", + 7099 => x"61", + 7100 => x"74", + 7101 => x"75", + 7102 => x"79", + 7103 => x"d8", + 7104 => x"c8", + 7105 => x"38", + 7106 => x"78", + 7107 => x"74", + 7108 => x"57", + 7109 => x"93", + 7110 => x"65", + 7111 => x"26", + 7112 => x"57", + 7113 => x"83", + 7114 => x"7c", + 7115 => x"06", + 7116 => x"ff", + 7117 => x"77", + 7118 => x"ff", + 7119 => x"82", + 7120 => x"83", + 7121 => x"ff", + 7122 => x"83", + 7123 => x"77", + 7124 => x"0b", + 7125 => x"81", + 7126 => x"34", + 7127 => x"34", + 7128 => x"34", + 7129 => x"57", + 7130 => x"52", + 7131 => x"eb", + 7132 => x"0b", + 7133 => x"82", + 7134 => x"82", + 7135 => x"55", + 7136 => x"34", + 7137 => x"08", + 7138 => x"63", + 7139 => x"1f", + 7140 => x"e6", + 7141 => x"83", + 7142 => x"ff", + 7143 => x"81", + 7144 => x"7e", + 7145 => x"ff", + 7146 => x"81", + 7147 => x"c8", + 7148 => x"80", + 7149 => x"79", + 7150 => x"f6", + 7151 => x"82", + 7152 => x"91", + 7153 => x"8e", + 7154 => x"81", + 7155 => x"81", + 7156 => x"80", + 7157 => x"93", + 7158 => x"3d", + 7159 => x"3d", + 7160 => x"71", + 7161 => x"e2", + 7162 => x"10", + 7163 => x"05", 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x"56", + 7223 => x"e7", + 7224 => x"74", + 7225 => x"e8", + 7226 => x"e8", + 7227 => x"93", + 7228 => x"9a", + 7229 => x"52", + 7230 => x"e8", + 7231 => x"93", + 7232 => x"75", + 7233 => x"af", + 7234 => x"c8", + 7235 => x"54", + 7236 => x"52", + 7237 => x"51", + 7238 => x"3f", + 7239 => x"04", + 7240 => x"0d", + 7241 => x"08", + 7242 => x"08", + 7243 => x"84", + 7244 => x"71", + 7245 => x"75", + 7246 => x"87", + 7247 => x"07", + 7248 => x"5c", + 7249 => x"55", + 7250 => x"38", + 7251 => x"52", + 7252 => x"fb", + 7253 => x"ff", + 7254 => x"82", + 7255 => x"58", + 7256 => x"08", + 7257 => x"93", + 7258 => x"c0", + 7259 => x"82", + 7260 => x"59", + 7261 => x"fb", + 7262 => x"55", + 7263 => x"76", + 7264 => x"15", + 7265 => x"3f", + 7266 => x"08", + 7267 => x"c8", + 7268 => x"7a", + 7269 => x"38", + 7270 => x"18", + 7271 => x"39", + 7272 => x"fb", + 7273 => x"ca", + 7274 => x"30", + 7275 => x"80", + 7276 => x"70", + 7277 => x"06", + 7278 => x"56", + 7279 => x"90", + 7280 => x"e4", + 7281 => x"98", + 7282 => x"78", + 7283 => x"3f", + 7284 => x"82", + 7285 => x"81", + 7286 => x"04", + 7287 => x"02", + 7288 => x"57", + 7289 => x"59", + 7290 => x"52", + 7291 => x"b0", + 7292 => x"c8", + 7293 => x"76", + 7294 => x"38", + 7295 => x"98", + 7296 => x"61", + 7297 => x"82", + 7298 => x"7f", + 7299 => x"75", + 7300 => x"c8", + 7301 => x"39", + 7302 => x"82", + 7303 => x"8a", + 7304 => x"fb", + 7305 => x"9f", + 7306 => x"85", + 7307 => x"85", + 7308 => x"ff", + 7309 => x"82", + 7310 => x"22", + 7311 => x"f9", + 7312 => x"86", + 7313 => x"86", + 7314 => x"15", + 7315 => x"86", + 7316 => x"81", + 7317 => x"80", + 7318 => x"fe", + 7319 => x"87", + 7320 => x"fe", + 7321 => x"c0", + 7322 => x"53", + 7323 => x"3f", + 7324 => x"ee", + 7325 => x"86", + 7326 => x"f0", + 7327 => x"51", + 7328 => x"3f", + 7329 => x"70", + 7330 => x"52", + 7331 => x"95", + 7332 => x"fe", + 7333 => x"82", + 7334 => x"fe", + 7335 => x"80", + 7336 => x"d0", + 7337 => x"2a", + 7338 => x"51", + 7339 => x"2e", + 7340 => x"51", + 7341 => x"3f", + 7342 => x"51", + 7343 => x"3f", + 7344 => x"ee", + 7345 => x"83", + 7346 => x"06", + 7347 => x"80", + 7348 => x"81", + 7349 => x"9c", + 7350 => x"f0", + 7351 => x"92", + 7352 => x"fe", + 7353 => x"72", + 7354 => x"81", + 7355 => x"71", + 7356 => x"38", + 7357 => x"ed", + 7358 => x"87", + 7359 => x"ef", + 7360 => x"51", + 7361 => x"3f", + 7362 => x"70", + 7363 => x"52", + 7364 => x"95", + 7365 => x"fe", + 7366 => x"82", + 7367 => x"fe", + 7368 => x"80", + 7369 => x"cc", + 7370 => x"2a", + 7371 => x"51", + 7372 => x"2e", + 7373 => x"51", + 7374 => x"3f", + 7375 => x"51", + 7376 => x"3f", + 7377 => x"ed", + 7378 => x"87", + 7379 => x"06", + 7380 => x"80", + 7381 => x"81", + 7382 => x"98", + 7383 => x"c0", + 7384 => x"8e", + 7385 => x"fe", + 7386 => x"72", + 7387 => x"81", + 7388 => x"71", + 7389 => x"38", + 7390 => x"ec", + 7391 => x"87", + 7392 => x"ee", + 7393 => x"51", + 7394 => x"3f", + 7395 => x"3f", + 7396 => x"04", + 7397 => x"78", + 7398 => x"55", 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x"51", + 7458 => x"3f", + 7459 => x"51", + 7460 => x"3f", + 7461 => x"f8", + 7462 => x"f8", + 7463 => x"c8", + 7464 => x"70", + 7465 => x"59", + 7466 => x"26", + 7467 => x"78", + 7468 => x"f2", + 7469 => x"78", + 7470 => x"3d", + 7471 => x"53", + 7472 => x"51", + 7473 => x"3f", + 7474 => x"08", + 7475 => x"88", + 7476 => x"fc", + 7477 => x"9a", + 7478 => x"fe", + 7479 => x"fe", + 7480 => x"fe", + 7481 => x"82", + 7482 => x"80", + 7483 => x"81", + 7484 => x"38", + 7485 => x"bf", + 7486 => x"02", + 7487 => x"33", + 7488 => x"ef", + 7489 => x"c8", + 7490 => x"06", + 7491 => x"38", + 7492 => x"51", + 7493 => x"3f", + 7494 => x"d6", + 7495 => x"f4", + 7496 => x"80", + 7497 => x"39", + 7498 => x"f4", + 7499 => x"f8", + 7500 => x"fd", + 7501 => x"93", + 7502 => x"2e", + 7503 => x"80", + 7504 => x"02", + 7505 => x"33", + 7506 => x"e6", + 7507 => x"c8", + 7508 => x"89", + 7509 => x"fb", + 7510 => x"96", + 7511 => x"fe", + 7512 => x"fe", + 7513 => x"fe", + 7514 => x"82", + 7515 => x"80", + 7516 => x"60", + 7517 => x"fa", + 7518 => x"fe", + 7519 => x"fe", + 7520 => x"fe", + 7521 => x"82", + 7522 => x"86", + 7523 => x"c8", + 7524 => x"53", + 7525 => x"52", + 7526 => x"52", + 7527 => x"94", + 7528 => x"05", + 7529 => x"52", + 7530 => x"29", + 7531 => x"05", + 7532 => x"d0", + 7533 => x"c8", + 7534 => x"8c", + 7535 => x"c8", + 7536 => x"9a", + 7537 => x"39", + 7538 => x"51", + 7539 => x"3f", + 7540 => x"9e", + 7541 => x"fe", + 7542 => x"fe", + 7543 => x"82", + 7544 => x"b5", + 7545 => x"05", + 7546 => x"e4", + 7547 => x"53", + 7548 => x"08", + 7549 => x"f6", + 7550 => x"93", + 7551 => x"2e", + 7552 => x"82", + 7553 => x"51", + 7554 => x"fc", + 7555 => x"3d", + 7556 => x"51", + 7557 => x"3f", + 7558 => x"08", + 7559 => x"f8", + 7560 => x"fe", + 7561 => x"82", + 7562 => x"b5", + 7563 => x"05", + 7564 => x"e4", + 7565 => x"93", + 7566 => x"3d", + 7567 => x"52", + 7568 => x"a3", + 7569 => x"c4", + 7570 => x"fc", + 7571 => x"80", + 7572 => x"c8", + 7573 => x"06", + 7574 => x"79", + 7575 => x"f6", + 7576 => x"93", + 7577 => x"2e", + 7578 => x"82", + 7579 => x"51", + 7580 => x"fb", + 7581 => x"89", + 7582 => x"f3", + 7583 => x"51", + 7584 => x"3f", + 7585 => x"82", + 7586 => x"fe", + 7587 => x"a2", + 7588 => x"e2", + 7589 => x"39", + 7590 => x"0b", + 7591 => x"84", + 7592 => x"81", + 7593 => x"94", + 7594 => x"89", + 7595 => x"f2", + 7596 => x"be", + 7597 => x"dc", + 7598 => x"e8", + 7599 => x"83", + 7600 => x"94", + 7601 => x"80", + 7602 => x"c0", + 7603 => x"fb", + 7604 => x"3d", + 7605 => x"53", + 7606 => x"51", + 7607 => x"3f", + 7608 => x"08", + 7609 => x"8a", + 7610 => x"82", + 7611 => x"fe", + 7612 => x"60", + 7613 => x"b4", + 7614 => x"11", + 7615 => x"05", + 7616 => x"a5", + 7617 => x"c8", + 7618 => x"fa", + 7619 => x"52", + 7620 => x"51", + 7621 => x"3f", + 7622 => x"2d", + 7623 => x"08", + 7624 => x"c8", + 7625 => x"fa", + 7626 => x"93", + 7627 => x"82", + 7628 => x"fe", + 7629 => x"fa", + 7630 => x"8a", + 7631 => x"f1", + 7632 => x"d1", + 7633 => x"aa", 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x"e4", + 7693 => x"ee", + 7694 => x"51", + 7695 => x"f7", + 7696 => x"04", + 7697 => x"2f", + 7698 => x"2f", + 7699 => x"2f", + 7700 => x"2f", + 7701 => x"2f", + 7702 => x"2f", + 7703 => x"31", + 7704 => x"31", + 7705 => x"31", + 7706 => x"31", + 7707 => x"31", + 7708 => x"31", + 7709 => x"31", + 7710 => x"31", + 7711 => x"31", + 7712 => x"31", + 7713 => x"31", + 7714 => x"31", + 7715 => x"31", + 7716 => x"31", + 7717 => x"31", + 7718 => x"31", + 7719 => x"31", + 7720 => x"31", + 7721 => x"31", + 7722 => x"31", + 7723 => x"31", + 7724 => x"31", + 7725 => x"31", + 7726 => x"70", + 7727 => x"6f", + 7728 => x"6f", + 7729 => x"70", + 7730 => x"70", + 7731 => x"70", + 7732 => x"70", + 7733 => x"70", + 7734 => x"70", + 7735 => x"70", + 7736 => x"70", + 7737 => x"70", + 7738 => x"70", + 7739 => x"70", + 7740 => x"70", + 7741 => x"70", + 7742 => x"70", + 7743 => x"70", + 7744 => x"70", + 7745 => x"70", + 7746 => x"74", + 7747 => x"77", + 7748 => x"74", + 7749 => x"77", + 7750 => x"75", + 7751 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=> x"69", + 8457 => x"69", + 8458 => x"73", + 8459 => x"64", + 8460 => x"72", + 8461 => x"2c", + 8462 => x"65", + 8463 => x"20", + 8464 => x"74", + 8465 => x"6e", + 8466 => x"6c", + 8467 => x"00", + 8468 => x"00", + 8469 => x"64", + 8470 => x"73", + 8471 => x"64", + 8472 => x"00", + 8473 => x"69", + 8474 => x"6c", + 8475 => x"64", + 8476 => x"00", + 8477 => x"69", + 8478 => x"20", + 8479 => x"69", + 8480 => x"69", + 8481 => x"73", + 8482 => x"00", + 8483 => x"3d", + 8484 => x"00", + 8485 => x"3a", + 8486 => x"73", + 8487 => x"69", + 8488 => x"69", + 8489 => x"72", + 8490 => x"74", + 8491 => x"00", + 8492 => x"61", + 8493 => x"6e", + 8494 => x"6e", + 8495 => x"72", + 8496 => x"73", + 8497 => x"00", + 8498 => x"73", + 8499 => x"65", + 8500 => x"61", + 8501 => x"66", + 8502 => x"0a", + 8503 => x"61", + 8504 => x"6e", + 8505 => x"61", + 8506 => x"66", + 8507 => x"0a", + 8508 => x"65", + 8509 => x"69", + 8510 => x"63", + 8511 => x"20", + 8512 => x"30", + 8513 => x"2e", + 8514 => x"00", + 8515 => x"6c", + 8516 => x"67", + 8517 => x"64", + 8518 => x"20", + 8519 => x"78", + 8520 => x"2e", + 8521 => x"00", + 8522 => x"6c", + 8523 => x"65", + 8524 => x"6e", + 8525 => x"63", + 8526 => x"20", + 8527 => x"29", + 8528 => x"00", + 8529 => x"73", + 8530 => x"74", + 8531 => x"20", + 8532 => x"6c", + 8533 => x"74", + 8534 => x"2e", + 8535 => x"00", + 8536 => x"6c", + 8537 => x"65", + 8538 => x"74", + 8539 => x"2e", + 8540 => x"00", + 8541 => x"55", + 8542 => x"6e", + 8543 => x"3a", + 8544 => x"5c", + 8545 => x"25", + 8546 => x"00", + 8547 => x"64", + 8548 => x"6d", + 8549 => x"64", + 8550 => x"00", + 8551 => x"6e", + 8552 => x"67", + 8553 => x"0a", + 8554 => x"61", + 8555 => x"6e", + 8556 => x"6e", + 8557 => x"72", + 8558 => x"73", + 8559 => x"0a", + 8560 => x"00", + 8561 => x"00", + 8562 => x"7f", + 8563 => x"00", + 8564 => x"7f", + 8565 => x"00", + 8566 => x"7f", + 8567 => x"00", + 8568 => x"00", + 8569 => x"78", + 8570 => x"00", + 8571 => x"e1", + 8572 => x"01", + 8573 => x"01", + 8574 => x"01", + 8575 => x"00", + 8576 => x"00", + 8577 => x"00", + 8578 => x"7f", + 8579 => x"01", + 8580 => x"00", + 8581 => x"00", + 8582 => x"7f", + 8583 => x"01", + 8584 => x"00", + 8585 => x"00", + 8586 => x"7f", + 8587 => x"01", + 8588 => x"00", + 8589 => x"00", + 8590 => x"7f", + 8591 => x"01", + 8592 => x"00", + 8593 => x"00", + 8594 => x"7f", + 8595 => x"02", + 8596 => x"00", + 8597 => x"00", + 8598 => x"7f", + 8599 => x"02", + 8600 => x"00", + 8601 => x"00", + 8602 => x"7f", + 8603 => x"02", + 8604 => x"00", + 8605 => x"00", + 8606 => x"7f", + 8607 => x"02", + 8608 => x"00", + 8609 => x"00", + 8610 => x"7f", + 8611 => x"02", + 8612 => x"00", + 8613 => x"00", + 8614 => x"7f", + 8615 => x"02", + 8616 => x"00", + 8617 => x"00", + 8618 => x"7f", + 8619 => x"03", + 8620 => x"00", + 8621 => x"00", + 8622 => x"7f", + 8623 => x"03", + 8624 => x"00", + 8625 => x"00", + 8626 => x"7f", + 8627 => x"03", + 8628 => x"00", + 8629 => x"00", + 8630 => x"7f", + 8631 => x"03", + 8632 => x"00", + 8633 => x"00", + 8634 => x"7f", + 8635 => x"03", + 8636 => x"00", + 8637 => x"00", + 8638 => x"7f", + 8639 => x"03", + 8640 => x"00", + 8641 => x"00", + 8642 => x"7f", + 8643 => x"03", + 8644 => x"00", + 8645 => x"00", + 8646 => x"7f", + 8647 => x"03", + 8648 => x"00", + 8649 => x"00", + 8650 => x"7f", + 8651 => x"03", + 8652 => x"00", + 8653 => x"00", + 8654 => x"7f", + 8655 => x"03", + 8656 => x"00", + 8657 => x"00", + 8658 => x"7f", + 8659 => x"03", + 8660 => x"00", + 8661 => x"00", + 8662 => x"7f", + 8663 => x"03", + 8664 => x"00", + 8665 => x"00", + 8666 => x"7f", + 8667 => x"03", + 8668 => x"00", + 8669 => x"00", + 8670 => x"7f", + 8671 => x"03", + 8672 => x"00", + 8673 => x"00", + 8674 => x"80", + 8675 => x"03", + 8676 => x"00", + 8677 => x"00", + 8678 => x"80", + 8679 => x"03", + 8680 => x"00", + 8681 => x"00", + 8682 => x"80", + 8683 => x"03", + 8684 => x"00", + 8685 => x"00", + 8686 => x"80", + 8687 => x"03", + 8688 => x"00", + 8689 => x"00", + 8690 => x"80", + 8691 => x"03", + 8692 => x"00", + 8693 => x"00", + 8694 => x"80", + 8695 => x"03", + 8696 => x"00", + 8697 => x"00", + 8698 => x"80", + 8699 => x"03", + 8700 => x"00", + 8701 => x"00", + 8702 => x"80", + 8703 => x"03", + 8704 => x"00", + 8705 => x"00", + 8706 => x"80", + 8707 => x"03", + 8708 => x"00", + 8709 => x"00", + 8710 => x"80", + 8711 => x"03", + 8712 => x"00", + 8713 => x"00", + 8714 => x"80", + 8715 => x"03", + 8716 => x"00", + 8717 => x"00", + 8718 => x"80", + 8719 => x"03", + 8720 => x"00", + 8721 => x"00", + 8722 => x"80", + 8723 => x"03", + 8724 => x"00", + 8725 => x"00", + 8726 => x"80", + 8727 => x"03", + 8728 => x"00", + 8729 => x"00", + 8730 => x"80", + 8731 => x"03", + 8732 => x"00", + 8733 => x"00", + 8734 => x"80", + 8735 => x"04", + 8736 => x"00", + 8737 => x"00", + 8738 => x"80", + 8739 => x"04", + 8740 => x"00", + 8741 => x"00", + 8742 => x"80", + 8743 => x"04", + 8744 => x"00", + 8745 => x"00", + 8746 => x"80", + 8747 => x"04", + 8748 => x"00", + 8749 => x"00", + 8750 => x"80", + 8751 => x"04", + 8752 => x"00", + 8753 => x"00", + 8754 => x"80", + 8755 => x"05", + 8756 => x"00", + 8757 => x"00", + 8758 => x"80", + 8759 => x"05", + 8760 => x"00", + 8761 => x"00", + 8762 => x"80", + 8763 => x"05", + 8764 => x"00", + 8765 => x"00", + 8766 => x"80", + 8767 => x"05", + 8768 => x"00", + 8769 => x"00", + 8770 => x"80", + 8771 => x"05", + 8772 => x"00", + 8773 => x"00", + 8774 => x"80", + 8775 => x"05", + 8776 => x"00", + 8777 => x"00", + 8778 => x"80", + 8779 => x"06", + 8780 => x"00", + 8781 => x"00", + 8782 => x"80", + 8783 => x"06", + 8784 => x"00", + 8785 => x"00", + 8786 => x"80", + 8787 => x"07", + 8788 => x"00", + 8789 => x"00", + 8790 => x"80", + 8791 => x"07", + 8792 => x"00", + 8793 => x"00", + 8794 => x"80", + 8795 => x"08", + 8796 => x"00", + 8797 => x"00", + 8798 => x"80", + 8799 => x"08", + 8800 => x"00", + 8801 => x"00", + 8802 => x"80", + 8803 => x"08", + 8804 => x"00", + 8805 => x"00", + 8806 => x"80", + 8807 => x"08", + 8808 => x"00", + 8809 => x"00", + 8810 => x"80", + 8811 => x"08", + 8812 => x"00", + 8813 => x"00", + 8814 => x"80", + 8815 => x"08", + 8816 => x"00", + 8817 => x"00", + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + 0 => x"0b", + 1 => x"04", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"08", + 10 => x"88", + 11 => x"90", + 12 => x"88", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"fd", + 17 => x"83", + 18 => x"05", + 19 => x"2b", + 20 => x"ff", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"fd", + 25 => x"ff", + 26 => x"06", + 27 => x"82", + 28 => x"2b", + 29 => x"83", + 30 => x"0b", + 31 => x"a5", + 32 => x"09", + 33 => x"05", + 34 => x"06", + 35 => x"09", + 36 => x"0a", + 37 => x"51", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"2e", + 42 => x"04", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"73", + 49 => x"06", + 50 => x"81", + 51 => x"10", + 52 => x"10", + 53 => x"0a", + 54 => x"51", + 55 => x"00", + 56 => x"72", + 57 => x"2e", + 58 => x"04", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"04", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"0a", + 81 => x"53", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"81", + 90 => x"0b", + 91 => x"04", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"9f", + 98 => x"74", + 99 => x"06", + 100 => x"07", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"06", + 106 => x"09", + 107 => x"05", + 108 => x"2b", + 109 => x"06", + 110 => x"04", + 111 => x"00", + 112 => x"09", + 113 => x"05", + 114 => x"05", + 115 => x"81", + 116 => x"04", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"09", + 121 => x"05", + 122 => x"05", + 123 => x"09", + 124 => x"51", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"09", + 129 => x"04", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"09", + 145 => x"73", + 146 => x"53", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"fc", + 153 => x"83", + 154 => x"05", + 155 => x"10", + 156 => x"ff", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"fc", + 161 => x"0b", + 162 => x"73", + 163 => x"10", + 164 => x"0b", + 165 => x"ac", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"08", + 170 => x"0b", + 171 => x"2d", + 172 => x"08", + 173 => x"8c", + 174 => x"51", + 175 => x"00", + 176 => x"08", + 177 => x"08", + 178 => x"0b", + 179 => x"2d", + 180 => x"08", + 181 => x"8c", + 182 => x"51", + 183 => x"00", + 184 => x"09", + 185 => x"09", + 186 => x"06", + 187 => x"54", + 188 => x"09", + 189 => x"ff", + 190 => x"51", + 191 => x"00", + 192 => x"09", + 193 => x"09", + 194 => x"81", + 195 => x"70", + 196 => x"73", + 197 => x"05", + 198 => x"07", + 199 => x"04", + 200 => x"ff", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"81", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"84", + 233 => x"10", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"71", + 250 => x"0d", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"00", + 257 => x"00", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"10", + 266 => x"04", + 267 => x"81", + 268 => x"83", + 269 => x"05", + 270 => x"10", + 271 => x"72", + 272 => x"51", + 273 => x"72", + 274 => x"06", + 275 => x"72", + 276 => x"10", + 277 => x"10", + 278 => x"ed", + 279 => x"53", + 280 => x"04", + 281 => x"04", + 282 => x"9f", + 283 => x"dc", + 284 => x"80", + 285 => x"05", + 286 => x"eb", + 287 => x"51", + 288 => x"94", + 289 => x"0c", + 290 => x"80", + 291 => x"8c", + 292 => x"94", + 293 => x"08", + 294 => x"3f", + 295 => x"88", + 296 => x"3d", + 297 => x"04", + 298 => x"94", + 299 => x"0d", + 300 => x"08", + 301 => x"52", + 302 => x"05", + 303 => x"b9", + 304 => x"70", + 305 => x"85", + 306 => x"0c", + 307 => x"02", + 308 => x"3d", + 309 => x"94", + 310 => x"0c", + 311 => x"05", + 312 => x"ab", + 313 => x"88", + 314 => x"94", + 315 => x"0c", + 316 => x"08", + 317 => x"94", + 318 => x"08", + 319 => x"0b", + 320 => x"05", + 321 => x"f4", + 322 => x"08", + 323 => x"94", + 324 => x"08", + 325 => x"38", + 326 => x"05", + 327 => x"08", + 328 => x"80", + 329 => x"f0", + 330 => x"08", + 331 => x"88", + 332 => x"94", + 333 => x"0c", + 334 => x"05", + 335 => x"fc", + 336 => x"53", + 337 => x"05", + 338 => x"08", + 339 => x"51", + 340 => x"88", + 341 => x"08", + 342 => x"54", + 343 => x"05", + 344 => x"8c", + 345 => x"f8", + 346 => x"94", + 347 => x"0c", + 348 => x"05", + 349 => x"0c", + 350 => x"0d", + 351 => x"94", + 352 => x"0c", + 353 => x"80", + 354 => x"fc", + 355 => x"08", + 356 => x"80", + 357 => x"94", + 358 => x"08", + 359 => x"88", + 360 => x"0b", + 361 => x"05", + 362 => x"8c", + 363 => x"25", + 364 => x"08", + 365 => x"30", + 366 => x"05", + 367 => x"94", + 368 => x"08", + 369 => x"88", + 370 => x"ad", + 371 => x"70", + 372 => x"05", + 373 => x"08", + 374 => x"80", + 375 => x"94", + 376 => x"08", + 377 => x"f8", + 378 => x"08", + 379 => x"70", + 380 => x"87", + 381 => x"0c", + 382 => x"02", + 383 => x"3d", + 384 => x"94", + 385 => x"0c", + 386 => x"08", + 387 => x"94", + 388 => x"08", + 389 => x"05", + 390 => x"38", + 391 => x"05", + 392 => x"a3", + 393 => x"94", + 394 => x"08", + 395 => x"94", + 396 => x"08", + 397 => x"8c", + 398 => x"08", + 399 => x"10", + 400 => x"05", + 401 => x"94", + 402 => x"08", + 403 => x"c9", + 404 => x"8c", + 405 => x"08", + 406 => x"26", + 407 => x"08", + 408 => x"94", + 409 => x"08", + 410 => x"88", + 411 => x"08", + 412 => x"94", + 413 => x"08", + 414 => x"f8", + 415 => x"08", + 416 => x"81", + 417 => x"fc", + 418 => x"08", + 419 => x"81", + 420 => x"8c", + 421 => x"af", + 422 => x"90", + 423 => x"2e", + 424 => x"08", + 425 => x"70", + 426 => x"05", + 427 => x"39", + 428 => x"05", + 429 => x"08", + 430 => x"51", + 431 => x"05", + 432 => x"85", + 433 => x"0c", + 434 => x"0d", + 435 => x"87", + 436 => x"0c", + 437 => x"c0", + 438 => x"85", + 439 => x"98", + 440 => x"c0", + 441 => x"70", + 442 => x"51", + 443 => x"8a", + 444 => x"98", + 445 => x"70", + 446 => x"c0", + 447 => x"fc", + 448 => x"52", + 449 => x"87", + 450 => x"08", + 451 => x"2e", + 452 => x"0b", + 453 => x"a8", + 454 => x"0b", + 455 => x"88", + 456 => x"0d", + 457 => x"0d", + 458 => x"56", + 459 => x"0b", + 460 => x"9f", + 461 => x"06", + 462 => x"52", + 463 => x"09", + 464 => x"9e", + 465 => x"87", + 466 => x"0c", + 467 => x"92", + 468 => x"0b", + 469 => x"8c", + 470 => x"92", + 471 => x"85", + 472 => x"06", + 473 => x"70", + 474 => x"38", + 475 => x"84", + 476 => x"ff", + 477 => x"27", + 478 => x"73", + 479 => x"38", + 480 => x"8b", + 481 => x"70", + 482 => x"34", + 483 => x"81", + 484 => x"a2", + 485 => x"80", + 486 => x"87", + 487 => x"08", + 488 => x"b5", + 489 => x"98", + 490 => x"70", + 491 => x"0b", + 492 => x"8c", + 493 => x"92", + 494 => x"82", + 495 => x"70", + 496 => x"73", + 497 => x"06", + 498 => x"72", + 499 => x"06", + 500 => x"c0", + 501 => x"51", + 502 => x"09", + 503 => x"38", + 504 => x"88", + 505 => x"0d", + 506 => x"0d", + 507 => x"33", + 508 => x"88", + 509 => x"0c", + 510 => x"3d", + 511 => x"3d", + 512 => x"11", + 513 => x"33", + 514 => x"71", + 515 => x"81", + 516 => x"72", + 517 => x"75", + 518 => x"88", + 519 => x"54", + 520 => x"85", + 521 => x"f9", + 522 => x"0b", + 523 => x"ac", + 524 => x"81", + 525 => x"ed", + 526 => x"17", + 527 => x"e5", + 528 => x"55", + 529 => x"89", + 530 => x"2e", + 531 => x"d5", + 532 => x"76", + 533 => x"06", + 534 => x"2a", + 535 => x"05", + 536 => x"70", + 537 => x"bd", + 538 => x"b9", + 539 => x"fe", + 540 => x"08", + 541 => x"06", + 542 => x"84", + 543 => x"2b", + 544 => x"53", + 545 => x"8c", + 546 => x"52", + 547 => x"52", + 548 => x"3f", + 549 => x"38", + 550 => x"e2", + 551 => x"f0", + 552 => x"83", + 553 => x"74", + 554 => x"3d", + 555 => x"3d", + 556 => x"0b", + 557 => x"fe", + 558 => x"08", + 559 => x"56", + 560 => x"74", + 561 => x"38", + 562 => x"75", + 563 => x"16", + 564 => x"53", + 565 => x"87", + 566 => x"fd", + 567 => x"54", + 568 => x"0b", + 569 => x"08", + 570 => x"53", + 571 => x"2e", + 572 => x"8c", + 573 => x"51", + 574 => x"88", + 575 => x"53", + 576 => x"fd", + 577 => x"08", + 578 => x"06", + 579 => x"0c", + 580 => x"04", + 581 => x"76", + 582 => x"9f", + 583 => x"55", + 584 => x"88", + 585 => x"72", + 586 => x"38", + 587 => x"73", + 588 => x"81", + 589 => x"72", + 590 => x"33", + 591 => x"2e", + 592 => x"85", + 593 => x"08", + 594 => x"16", + 595 => x"2e", + 596 => x"51", + 597 => x"88", + 598 => x"39", + 599 => x"52", + 600 => x"0c", + 601 => x"88", + 602 => x"0d", + 603 => x"0d", + 604 => x"0b", + 605 => x"71", + 606 => x"70", + 607 => x"06", + 608 => x"55", + 609 => x"88", + 610 => x"08", + 611 => x"38", + 612 => x"dc", + 613 => x"06", + 614 => x"cf", + 615 => x"90", + 616 => x"15", + 617 => x"8f", + 618 => x"84", + 619 => x"52", + 620 => x"bc", + 621 => x"82", + 622 => x"05", + 623 => x"06", + 624 => x"38", + 625 => x"df", + 626 => x"71", + 627 => x"a0", + 628 => x"88", + 629 => x"08", + 630 => x"88", + 631 => x"0c", + 632 => x"fd", + 633 => x"08", + 634 => x"73", + 635 => x"52", + 636 => x"88", + 637 => x"f2", + 638 => x"62", + 639 => x"5c", + 640 => x"74", + 641 => x"81", + 642 => x"81", + 643 => x"56", + 644 => x"70", + 645 => x"74", + 646 => x"81", + 647 => x"81", + 648 => x"0b", + 649 => x"62", + 650 => x"55", + 651 => x"8f", + 652 => x"fd", + 653 => x"08", + 654 => x"34", + 655 => x"93", + 656 => x"08", + 657 => x"5f", + 658 => x"76", + 659 => x"58", + 660 => x"55", + 661 => x"09", + 662 => x"38", + 663 => x"5b", + 664 => x"5f", + 665 => x"1c", + 666 => x"06", + 667 => x"33", + 668 => x"70", + 669 => x"27", + 670 => x"07", + 671 => x"5b", + 672 => x"55", + 673 => x"38", + 674 => x"09", + 675 => x"38", + 676 => x"7a", + 677 => x"55", + 678 => x"9f", + 679 => x"32", + 680 => x"ae", + 681 => x"70", + 682 => x"2a", + 683 => x"51", + 684 => x"38", + 685 => x"5a", + 686 => x"77", + 687 => x"81", + 688 => x"1c", + 689 => x"55", + 690 => x"ff", + 691 => x"1e", + 692 => x"55", + 693 => x"83", + 694 => x"74", + 695 => x"7b", + 696 => x"3f", + 697 => x"ef", + 698 => x"7b", + 699 => x"2b", + 700 => x"54", + 701 => x"08", + 702 => x"f8", + 703 => x"08", + 704 => x"80", + 705 => x"33", + 706 => x"2e", + 707 => x"8b", + 708 => x"83", + 709 => x"06", + 710 => x"74", + 711 => x"7d", + 712 => x"88", + 713 => x"5b", + 714 => x"58", + 715 => x"9a", + 716 => x"81", + 717 => x"79", + 718 => x"5b", + 719 => x"31", + 720 => x"75", + 721 => x"38", + 722 => x"80", + 723 => x"7b", + 724 => x"3f", + 725 => x"88", + 726 => x"08", + 727 => x"39", + 728 => x"1c", + 729 => x"33", + 730 => x"a5", + 731 => x"33", + 732 => x"70", + 733 => x"56", + 734 => x"38", + 735 => x"39", + 736 => x"39", + 737 => x"d3", + 738 => x"88", + 739 => x"af", + 740 => x"0c", + 741 => x"04", + 742 => x"79", + 743 => x"82", + 744 => x"53", + 745 => x"51", + 746 => x"83", + 747 => x"80", + 748 => x"51", + 749 => x"88", + 750 => x"ff", + 751 => x"56", + 752 => x"d5", + 753 => x"06", + 754 => x"75", + 755 => x"77", + 756 => x"f6", + 757 => x"08", + 758 => x"94", + 759 => x"f8", + 760 => x"08", + 761 => x"06", + 762 => x"82", + 763 => x"38", + 764 => x"d2", + 765 => x"76", + 766 => x"3f", + 767 => x"88", + 768 => x"76", + 769 => x"3f", + 770 => x"ff", + 771 => x"74", + 772 => x"2e", + 773 => x"56", + 774 => x"89", + 775 => x"ed", + 776 => x"59", + 777 => x"0b", + 778 => x"0c", + 779 => x"88", + 780 => x"55", + 781 => x"82", + 782 => x"75", + 783 => x"70", + 784 => x"fe", + 785 => x"08", + 786 => x"57", + 787 => x"09", + 788 => x"38", + 789 => x"be", + 790 => x"75", + 791 => x"3f", + 792 => x"38", + 793 => x"55", + 794 => x"ac", + 795 => x"e4", + 796 => x"8a", + 797 => x"88", + 798 => x"52", + 799 => x"3f", + 800 => x"ff", + 801 => x"83", + 802 => x"06", + 803 => x"56", + 804 => x"76", + 805 => x"38", + 806 => x"8f", + 807 => x"8d", + 808 => x"75", + 809 => x"3f", + 810 => x"08", + 811 => x"95", + 812 => x"51", + 813 => x"88", + 814 => x"ff", + 815 => x"8c", + 816 => x"f3", + 817 => x"b6", + 818 => x"58", + 819 => x"33", + 820 => x"02", + 821 => x"05", + 822 => x"59", + 823 => x"3f", + 824 => x"ff", + 825 => x"05", + 826 => x"8c", + 827 => x"1a", + 828 => x"e0", + 829 => x"f1", + 830 => x"84", + 831 => x"3d", + 832 => x"f5", + 833 => x"08", + 834 => x"06", + 835 => x"38", + 836 => x"05", + 837 => x"3f", + 838 => x"7a", + 839 => x"3f", + 840 => x"ff", + 841 => x"71", + 842 => x"84", + 843 => x"84", + 844 => x"33", + 845 => x"31", + 846 => x"51", + 847 => x"3f", + 848 => x"05", + 849 => x"0c", + 850 => x"8a", + 851 => x"74", + 852 => x"26", + 853 => x"57", + 854 => x"76", + 855 => x"83", + 856 => x"86", + 857 => x"2e", + 858 => x"76", + 859 => x"83", + 860 => x"06", + 861 => x"3d", + 862 => x"f5", + 863 => x"08", + 864 => x"88", + 865 => x"08", + 866 => x"0c", + 867 => x"ff", + 868 => x"08", + 869 => x"2a", + 870 => x"0c", + 871 => x"81", + 872 => x"0b", + 873 => x"ac", + 874 => x"75", + 875 => x"3d", + 876 => x"3d", + 877 => x"0b", + 878 => x"55", + 879 => x"80", + 880 => x"38", + 881 => x"16", + 882 => x"e0", + 883 => x"54", + 884 => x"54", + 885 => x"51", + 886 => x"88", + 887 => x"08", + 888 => x"88", + 889 => x"73", + 890 => x"38", + 891 => x"33", + 892 => x"70", + 893 => x"55", + 894 => x"2e", + 895 => x"54", + 896 => x"51", + 897 => x"88", + 898 => x"0c", + 899 => x"05", + 900 => x"3f", + 901 => x"16", + 902 => x"16", + 903 => x"81", + 904 => x"88", + 905 => x"0d", + 906 => x"0d", + 907 => x"0b", + 908 => x"ac", + 909 => x"5c", + 910 => x"0c", + 911 => x"80", + 912 => x"38", + 913 => x"81", + 914 => x"57", + 915 => x"81", + 916 => x"39", + 917 => x"34", + 918 => x"0b", + 919 => x"81", + 920 => x"39", + 921 => x"98", + 922 => x"55", + 923 => x"83", + 924 => x"77", + 925 => x"9a", + 926 => x"08", + 927 => x"06", + 928 => x"80", + 929 => x"16", + 930 => x"77", + 931 => x"70", + 932 => x"5b", + 933 => x"38", + 934 => x"a0", + 935 => x"8b", + 936 => x"08", + 937 => x"3f", + 938 => x"81", + 939 => x"aa", + 940 => x"17", + 941 => x"08", + 942 => x"3f", + 943 => x"88", + 944 => x"ff", + 945 => x"08", + 946 => x"0c", + 947 => x"83", + 948 => x"80", + 949 => x"55", + 950 => x"83", + 951 => x"74", + 952 => x"08", + 953 => x"53", + 954 => x"52", + 955 => x"b5", + 956 => x"fe", + 957 => x"16", + 958 => x"17", + 959 => x"31", + 960 => x"7c", + 961 => x"80", + 962 => x"38", + 963 => x"fe", + 964 => x"57", + 965 => x"8c", + 966 => x"fb", + 967 => x"90", + 968 => x"87", + 969 => x"0c", + 970 => x"e4", + 971 => x"94", + 972 => x"80", + 973 => x"c0", + 974 => x"8c", + 975 => x"87", + 976 => x"0c", + 977 => x"f9", + 978 => x"08", + 979 => x"98", + 980 => x"3f", + 981 => x"38", + 982 => x"88", + 983 => x"98", + 984 => x"87", + 985 => x"53", + 986 => x"74", + 987 => x"3f", + 988 => x"38", + 989 => x"80", + 990 => x"73", + 991 => x"39", + 992 => x"73", + 993 => x"fb", + 994 => x"ff", + 995 => x"00", + 996 => x"ff", + 997 => x"ff", + 998 => x"4f", + 999 => x"49", + 1000 => x"52", + 1001 => x"00", + 1002 => x"00", + 2048 => x"0b", + 2049 => x"0b", + 2050 => x"ca", + 2051 => x"ff", + 2052 => x"ff", + 2053 => x"ff", + 2054 => x"ff", + 2055 => x"ff", + 2056 => x"0b", + 2057 => x"04", + 2058 => x"c4", + 2059 => x"0b", + 2060 => x"04", + 2061 => x"c4", + 2062 => x"0b", + 2063 => x"04", + 2064 => x"c4", + 2065 => x"0b", + 2066 => x"04", + 2067 => x"c4", + 2068 => x"0b", + 2069 => x"04", + 2070 => x"c5", + 2071 => x"0b", + 2072 => x"04", + 2073 => x"c5", + 2074 => x"0b", + 2075 => x"04", + 2076 => x"c5", + 2077 => x"0b", + 2078 => x"04", + 2079 => x"c5", + 2080 => x"0b", + 2081 => x"04", + 2082 => x"c6", + 2083 => x"0b", + 2084 => x"04", + 2085 => x"c6", + 2086 => x"0b", + 2087 => x"04", + 2088 => x"c6", + 2089 => x"0b", + 2090 => x"04", + 2091 => x"c6", + 2092 => x"0b", + 2093 => x"04", + 2094 => x"c7", + 2095 => x"0b", + 2096 => x"04", + 2097 => x"c7", + 2098 => x"0b", + 2099 => x"04", + 2100 => x"c7", + 2101 => x"0b", + 2102 => x"04", + 2103 => x"c7", + 2104 => x"0b", + 2105 => x"04", + 2106 => x"c8", + 2107 => x"0b", + 2108 => x"04", + 2109 => x"c8", + 2110 => x"0b", + 2111 => x"04", + 2112 => x"c8", + 2113 => x"0b", + 2114 => x"04", + 2115 => x"c8", + 2116 => x"0b", + 2117 => x"04", + 2118 => x"c9", + 2119 => x"0b", + 2120 => x"04", + 2121 => x"c9", + 2122 => x"0b", + 2123 => x"04", + 2124 => x"c9", + 2125 => x"0b", + 2126 => x"04", + 2127 => x"c9", + 2128 => x"0b", + 2129 => x"04", + 2130 => x"ca", + 2131 => x"00", + 2132 => x"00", + 2133 => x"00", + 2134 => x"00", + 2135 => x"00", + 2136 => x"00", + 2137 => x"00", + 2138 => x"00", + 2139 => x"00", + 2140 => x"00", + 2141 => x"00", + 2142 => x"00", + 2143 => x"00", + 2144 => x"00", + 2145 => x"00", + 2146 => x"00", + 2147 => x"00", + 2148 => x"00", + 2149 => x"00", + 2150 => x"00", + 2151 => x"00", + 2152 => x"00", + 2153 => x"00", + 2154 => x"00", + 2155 => x"00", + 2156 => x"00", + 2157 => x"00", + 2158 => x"00", + 2159 => x"00", + 2160 => x"00", + 2161 => x"00", + 2162 => x"00", + 2163 => x"00", + 2164 => x"00", + 2165 => x"00", + 2166 => x"00", + 2167 => x"00", + 2168 => x"00", + 2169 => x"00", + 2170 => x"00", + 2171 => x"00", + 2172 => x"00", + 2173 => x"00", + 2174 => x"00", + 2175 => x"00", + 2176 => x"80", + 2177 => x"82", + 2178 => x"80", + 2179 => x"82", + 2180 => x"83", + 2181 => x"82", + 2182 => x"80", + 2183 => x"82", + 2184 => x"83", + 2185 => x"82", + 2186 => x"80", + 2187 => x"82", + 2188 => x"83", + 2189 => x"82", + 2190 => x"80", + 2191 => x"82", + 2192 => x"83", + 2193 => x"82", + 2194 => x"80", + 2195 => x"82", + 2196 => x"83", + 2197 => x"82", + 2198 => x"80", + 2199 => x"82", + 2200 => x"83", + 2201 => x"82", + 2202 => x"80", + 2203 => x"82", + 2204 => x"83", + 2205 => x"82", + 2206 => x"80", + 2207 => x"82", + 2208 => x"83", + 2209 => x"82", + 2210 => x"80", + 2211 => x"82", + 2212 => x"83", + 2213 => x"82", + 2214 => x"80", + 2215 => x"82", + 2216 => x"83", + 2217 => x"82", + 2218 => x"80", + 2219 => x"82", + 2220 => x"83", + 2221 => x"82", + 2222 => x"80", + 2223 => x"82", + 2224 => x"83", + 2225 => x"82", + 2226 => x"80", + 2227 => x"82", + 2228 => x"83", + 2229 => x"82", + 2230 => x"80", + 2231 => x"82", + 2232 => x"83", + 2233 => x"82", + 2234 => x"80", + 2235 => x"82", + 2236 => x"83", + 2237 => x"82", + 2238 => x"80", + 2239 => x"82", + 2240 => x"83", + 2241 => x"82", + 2242 => x"80", + 2243 => x"82", + 2244 => x"83", + 2245 => x"82", + 2246 => x"81", + 2247 => x"82", + 2248 => x"83", + 2249 => x"82", + 2250 => x"81", + 2251 => x"82", + 2252 => x"83", + 2253 => x"82", + 2254 => x"81", + 2255 => x"82", + 2256 => x"83", + 2257 => x"82", + 2258 => x"81", + 2259 => x"82", + 2260 => x"83", + 2261 => x"82", + 2262 => x"81", + 2263 => x"82", + 2264 => x"83", + 2265 => x"82", + 2266 => x"81", + 2267 => x"82", + 2268 => x"83", + 2269 => x"82", + 2270 => x"81", + 2271 => x"82", + 2272 => x"83", + 2273 => x"82", + 2274 => x"81", + 2275 => x"82", + 2276 => x"83", + 2277 => x"82", + 2278 => x"81", + 2279 => x"82", + 2280 => x"83", + 2281 => x"82", + 2282 => x"81", + 2283 => x"82", + 2284 => x"83", + 2285 => x"82", + 2286 => x"81", + 2287 => x"82", + 2288 => x"83", + 2289 => x"82", + 2290 => x"81", + 2291 => x"82", + 2292 => x"83", + 2293 => x"82", + 2294 => x"81", + 2295 => x"82", + 2296 => x"83", + 2297 => x"82", + 2298 => x"81", + 2299 => x"82", + 2300 => x"83", + 2301 => x"82", + 2302 => x"81", + 2303 => x"82", + 2304 => x"83", + 2305 => x"82", + 2306 => x"81", + 2307 => x"82", + 2308 => x"83", + 2309 => x"82", + 2310 => x"81", + 2311 => x"82", + 2312 => x"83", + 2313 => x"82", + 2314 => x"81", + 2315 => x"82", + 2316 => x"83", + 2317 => x"82", + 2318 => x"81", + 2319 => x"82", + 2320 => x"83", + 2321 => x"82", + 2322 => x"81", + 2323 => x"82", + 2324 => x"83", + 2325 => x"82", + 2326 => x"81", + 2327 => x"82", + 2328 => x"83", + 2329 => x"82", + 2330 => x"81", + 2331 => x"82", + 2332 => x"83", + 2333 => x"82", + 2334 => x"81", + 2335 => x"82", + 2336 => x"83", + 2337 => x"82", + 2338 => x"81", + 2339 => x"82", + 2340 => x"83", + 2341 => x"82", + 2342 => x"81", + 2343 => x"82", + 2344 => x"83", + 2345 => x"82", + 2346 => x"80", + 2347 => x"82", + 2348 => x"83", + 2349 => x"82", + 2350 => x"80", + 2351 => x"82", + 2352 => x"83", + 2353 => x"82", + 2354 => x"80", + 2355 => x"82", + 2356 => x"83", + 2357 => x"82", + 2358 => x"80", + 2359 => x"82", + 2360 => x"83", + 2361 => x"82", + 2362 => x"80", + 2363 => x"82", + 2364 => x"83", + 2365 => x"82", + 2366 => x"80", + 2367 => x"82", + 2368 => x"83", + 2369 => x"82", + 2370 => x"81", + 2371 => x"82", + 2372 => x"83", + 2373 => x"82", + 2374 => x"82", + 2375 => x"8e", + 2376 => x"70", + 2377 => x"0c", + 2378 => x"ca", + 2379 => x"c4", + 2380 => x"ef", + 2381 => x"04", + 2382 => x"08", + 2383 => x"d4", + 2384 => x"0d", + 2385 => x"93", + 2386 => x"05", + 2387 => x"93", + 2388 => x"05", + 2389 => x"c5", + 2390 => x"c8", + 2391 => x"93", + 2392 => x"85", + 2393 => x"93", + 2394 => x"82", + 2395 => x"02", + 2396 => x"0c", + 2397 => x"81", + 2398 => x"d4", + 2399 => x"08", + 2400 => x"d4", + 2401 => x"08", + 2402 => x"82", + 2403 => x"70", + 2404 => x"0c", + 2405 => x"0d", + 2406 => x"0c", + 2407 => x"d4", + 2408 => x"93", + 2409 => x"3d", + 2410 => x"82", + 2411 => x"fc", + 2412 => x"0b", + 2413 => x"08", + 2414 => x"82", + 2415 => x"8c", + 2416 => x"93", + 2417 => x"05", + 2418 => x"38", + 2419 => x"08", + 2420 => x"80", + 2421 => x"80", + 2422 => x"d4", + 2423 => x"08", + 2424 => x"82", + 2425 => x"8c", + 2426 => x"82", + 2427 => x"8c", + 2428 => x"93", + 2429 => x"05", + 2430 => x"93", + 2431 => x"05", + 2432 => x"39", + 2433 => x"08", + 2434 => x"80", + 2435 => x"38", + 2436 => x"08", + 2437 => x"82", + 2438 => x"88", + 2439 => x"ad", + 2440 => x"d4", + 2441 => x"08", + 2442 => x"08", + 2443 => x"31", + 2444 => x"08", + 2445 => x"82", + 2446 => x"f8", + 2447 => x"93", + 2448 => x"05", + 2449 => x"93", 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x"0c", + 2509 => x"71", + 2510 => x"38", + 2511 => x"8e", + 2512 => x"0d", + 2513 => x"72", + 2514 => x"53", + 2515 => x"93", + 2516 => x"73", + 2517 => x"54", + 2518 => x"2e", + 2519 => x"73", + 2520 => x"71", + 2521 => x"ff", + 2522 => x"70", + 2523 => x"38", + 2524 => x"70", + 2525 => x"81", + 2526 => x"81", + 2527 => x"71", + 2528 => x"ff", + 2529 => x"54", + 2530 => x"38", + 2531 => x"73", + 2532 => x"75", + 2533 => x"71", + 2534 => x"93", + 2535 => x"52", + 2536 => x"04", + 2537 => x"f7", + 2538 => x"14", + 2539 => x"84", + 2540 => x"06", + 2541 => x"70", + 2542 => x"14", + 2543 => x"08", + 2544 => x"71", + 2545 => x"dc", + 2546 => x"54", + 2547 => x"39", + 2548 => x"93", + 2549 => x"3d", + 2550 => x"3d", + 2551 => x"54", + 2552 => x"2b", + 2553 => x"3f", + 2554 => x"08", + 2555 => x"72", + 2556 => x"54", + 2557 => x"25", + 2558 => x"82", + 2559 => x"84", + 2560 => x"fc", + 2561 => x"70", + 2562 => x"55", + 2563 => x"2e", + 2564 => x"73", + 2565 => x"a0", + 2566 => x"06", + 2567 => x"14", + 2568 => x"54", + 2569 => x"f6", + 2570 => x"84", + 2571 => x"52", + 2572 => x"52", + 2573 => x"2e", + 2574 => x"53", + 2575 => x"9f", + 2576 => x"51", + 2577 => x"38", + 2578 => x"70", + 2579 => x"81", + 2580 => x"80", + 2581 => x"05", + 2582 => x"75", + 2583 => x"70", + 2584 => x"0c", + 2585 => x"04", + 2586 => x"76", + 2587 => x"80", + 2588 => x"86", + 2589 => x"52", + 2590 => x"c4", + 2591 => x"c8", + 2592 => x"80", + 2593 => x"74", + 2594 => x"93", + 2595 => x"3d", + 2596 => x"3d", + 2597 => x"11", + 2598 => x"5b", + 2599 => x"79", + 2600 => x"bf", + 2601 => x"33", + 2602 => x"82", + 2603 => x"26", + 2604 => x"84", + 2605 => x"83", + 2606 => x"26", + 2607 => x"85", + 2608 => x"84", + 2609 => x"26", + 2610 => x"86", + 2611 => x"85", + 2612 => x"26", + 2613 => x"88", + 2614 => x"86", + 2615 => x"e7", + 2616 => x"38", + 2617 => x"5a", + 2618 => x"87", + 2619 => x"f3", + 2620 => x"22", + 2621 => x"22", + 2622 => x"33", + 2623 => x"33", + 2624 => x"33", + 2625 => x"33", + 2626 => x"33", + 2627 => x"52", + 2628 => x"51", + 2629 => x"87", + 2630 => x"5b", + 2631 => x"7b", + 2632 => x"98", + 2633 => x"1c", + 2634 => x"98", + 2635 => x"1c", + 2636 => x"98", + 2637 => x"1c", + 2638 => x"98", + 2639 => x"1c", + 2640 => x"98", + 2641 => x"1c", + 2642 => x"98", + 2643 => x"1c", + 2644 => x"98", + 2645 => x"1c", + 2646 => x"98", + 2647 => x"7b", + 2648 => x"7a", + 2649 => x"0c", + 2650 => x"04", + 2651 => x"7d", + 2652 => x"98", + 2653 => x"7c", + 2654 => x"98", + 2655 => x"7a", + 2656 => x"c0", + 2657 => x"5b", + 2658 => x"34", + 2659 => x"b4", + 2660 => x"83", + 2661 => x"c0", + 2662 => x"5b", + 2663 => x"34", + 2664 => x"ac", + 2665 => x"85", + 2666 => x"c0", + 2667 => x"5b", + 2668 => x"34", + 2669 => x"a4", + 2670 => x"88", + 2671 => x"c0", + 2672 => x"5b", + 2673 => x"23", + 2674 => x"8a", + 2675 => x"88", + 2676 => x"86", + 2677 => x"85", + 2678 => x"84", + 2679 => x"83", + 2680 => x"82", + 2681 => x"79", + 2682 => x"f6", + 2683 => x"af", + 2684 => x"0d", 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x"94", + 2744 => x"80", + 2745 => x"87", + 2746 => x"52", + 2747 => x"85", + 2748 => x"fb", + 2749 => x"54", + 2750 => x"52", + 2751 => x"2e", + 2752 => x"73", + 2753 => x"55", + 2754 => x"82", + 2755 => x"54", + 2756 => x"94", + 2757 => x"80", + 2758 => x"87", + 2759 => x"51", + 2760 => x"96", + 2761 => x"06", + 2762 => x"70", + 2763 => x"38", + 2764 => x"70", + 2765 => x"51", + 2766 => x"71", + 2767 => x"32", + 2768 => x"51", + 2769 => x"2e", + 2770 => x"93", + 2771 => x"06", + 2772 => x"ff", + 2773 => x"0b", + 2774 => x"33", + 2775 => x"94", + 2776 => x"80", + 2777 => x"87", + 2778 => x"52", + 2779 => x"81", + 2780 => x"52", + 2781 => x"8b", + 2782 => x"93", + 2783 => x"3d", + 2784 => x"3d", + 2785 => x"82", + 2786 => x"52", + 2787 => x"84", + 2788 => x"2e", + 2789 => x"c0", + 2790 => x"70", + 2791 => x"2a", + 2792 => x"51", + 2793 => x"80", + 2794 => x"0b", + 2795 => x"c0", + 2796 => x"c0", + 2797 => x"70", + 2798 => x"38", + 2799 => x"90", + 2800 => x"70", + 2801 => x"82", + 2802 => x"51", + 2803 => x"04", + 2804 => x"0b", + 2805 => x"c0", + 2806 => x"c0", + 2807 => x"70", + 2808 => x"38", + 2809 => x"94", + 2810 => x"70", + 2811 => x"81", + 2812 => x"51", + 2813 => x"80", + 2814 => x"0b", + 2815 => x"c0", + 2816 => x"c0", + 2817 => x"70", + 2818 => x"38", + 2819 => x"90", + 2820 => x"70", + 2821 => x"98", + 2822 => x"51", + 2823 => x"c8", + 2824 => x"0d", + 2825 => x"0d", + 2826 => x"80", + 2827 => x"9c", + 2828 => x"51", + 2829 => x"80", + 2830 => x"38", + 2831 => x"0b", + 2832 => x"9c", + 2833 => x"84", + 2834 => x"9e", + 2835 => x"0c", + 2836 => x"87", + 2837 => x"08", + 2838 => x"8c", + 2839 => x"9e", + 2840 => x"0c", + 2841 => x"87", + 2842 => x"08", + 2843 => x"94", + 2844 => x"9e", + 2845 => x"0c", + 2846 => x"87", + 2847 => x"08", + 2848 => x"9c", + 2849 => x"9e", + 2850 => x"0c", + 2851 => x"87", + 2852 => x"08", + 2853 => x"73", + 2854 => x"70", + 2855 => x"a8", + 2856 => x"9e", + 2857 => x"0c", + 2858 => x"ac", + 2859 => x"12", + 2860 => x"87", + 2861 => x"08", + 2862 => x"06", + 2863 => x"70", + 2864 => x"38", + 2865 => x"72", + 2866 => x"87", + 2867 => x"08", + 2868 => x"80", + 2869 => x"52", + 2870 => x"83", + 2871 => x"71", + 2872 => x"34", + 2873 => x"c0", + 2874 => x"70", + 2875 => x"06", + 2876 => x"70", + 2877 => x"38", + 2878 => x"82", + 2879 => x"80", + 2880 => x"9e", + 2881 => x"90", + 2882 => x"52", + 2883 => x"2e", + 2884 => x"52", + 2885 => x"f4", + 2886 => x"87", + 2887 => x"08", + 2888 => x"06", + 2889 => x"70", + 2890 => x"38", + 2891 => x"82", + 2892 => x"80", + 2893 => x"9e", + 2894 => x"84", + 2895 => x"52", + 2896 => x"2e", + 2897 => x"52", + 2898 => x"f6", + 2899 => x"87", + 2900 => x"08", + 2901 => x"06", + 2902 => x"70", + 2903 => x"38", + 2904 => x"82", + 2905 => x"80", + 2906 => x"9e", + 2907 => x"81", + 2908 => x"52", + 2909 => x"2e", + 2910 => x"52", + 2911 => x"f8", + 2912 => x"f9", + 2913 => x"9e", + 2914 => x"70", + 2915 => x"70", + 2916 => x"51", + 2917 => x"72", + 2918 => x"54", + 2919 => x"80", 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x"51", + 2979 => x"82", + 2980 => x"33", + 2981 => x"80", + 2982 => x"81", + 2983 => x"81", + 2984 => x"88", + 2985 => x"8b", + 2986 => x"73", + 2987 => x"38", + 2988 => x"51", + 2989 => x"82", + 2990 => x"33", + 2991 => x"80", + 2992 => x"81", + 2993 => x"81", + 2994 => x"88", + 2995 => x"f8", + 2996 => x"d1", + 2997 => x"dc", + 2998 => x"84", + 2999 => x"54", + 3000 => x"53", + 3001 => x"b7", + 3002 => x"52", + 3003 => x"51", + 3004 => x"88", + 3005 => x"81", + 3006 => x"88", + 3007 => x"15", + 3008 => x"f9", + 3009 => x"97", + 3010 => x"08", + 3011 => x"98", + 3012 => x"3f", + 3013 => x"04", + 3014 => x"02", + 3015 => x"52", + 3016 => x"bb", + 3017 => x"10", + 3018 => x"f0", + 3019 => x"71", + 3020 => x"fa", + 3021 => x"bb", + 3022 => x"81", + 3023 => x"f7", + 3024 => x"39", + 3025 => x"51", + 3026 => x"9a", + 3027 => x"d8", + 3028 => x"3f", + 3029 => x"fa", + 3030 => x"97", + 3031 => x"81", + 3032 => x"f7", + 3033 => x"3d", + 3034 => x"88", + 3035 => x"80", + 3036 => x"96", + 3037 => x"ff", + 3038 => x"c0", + 3039 => x"08", + 3040 => x"72", + 3041 => x"07", + 3042 => x"80", + 3043 => x"83", + 3044 => x"ff", + 3045 => x"c0", + 3046 => x"08", + 3047 => x"0c", + 3048 => x"0c", + 3049 => x"82", + 3050 => x"06", + 3051 => x"80", + 3052 => x"51", + 3053 => x"04", + 3054 => x"08", + 3055 => x"84", + 3056 => x"3d", + 3057 => x"05", + 3058 => x"8a", + 3059 => x"06", + 3060 => x"51", + 3061 => x"93", + 3062 => x"2e", + 3063 => x"93", + 3064 => x"72", + 3065 => x"93", + 3066 => x"05", + 3067 => x"0c", + 3068 => x"93", + 3069 => x"2e", + 3070 => x"51", + 3071 => x"08", + 3072 => x"84", + 3073 => x"fe", + 3074 => x"97", + 3075 => x"93", + 3076 => x"82", + 3077 => x"54", + 3078 => x"3f", + 3079 => x"d8", + 3080 => x"0d", + 3081 => x"0d", + 3082 => x"53", + 3083 => x"2e", + 3084 => x"70", + 3085 => x"33", + 3086 => x"3f", + 3087 => x"71", + 3088 => x"3d", + 3089 => x"3d", + 3090 => x"93", + 3091 => x"82", + 3092 => x"71", + 3093 => x"53", + 3094 => x"91", + 3095 => x"81", + 3096 => x"51", + 3097 => x"72", + 3098 => x"f1", + 3099 => x"93", + 3100 => x"3d", + 3101 => x"3d", + 3102 => x"5d", + 3103 => x"81", + 3104 => x"56", + 3105 => x"85", + 3106 => x"a5", + 3107 => x"75", + 3108 => x"3f", + 3109 => x"70", + 3110 => x"05", + 3111 => x"5e", + 3112 => x"2e", + 3113 => x"8c", + 3114 => x"70", + 3115 => x"33", + 3116 => x"39", + 3117 => x"09", + 3118 => x"38", + 3119 => x"81", + 3120 => x"57", + 3121 => x"2e", + 3122 => x"92", + 3123 => x"1d", + 3124 => x"70", + 3125 => x"33", + 3126 => x"53", + 3127 => x"16", + 3128 => x"26", + 3129 => x"8a", + 3130 => x"05", + 3131 => x"05", + 3132 => x"11", + 3133 => x"89", + 3134 => x"38", + 3135 => x"32", + 3136 => x"72", + 3137 => x"78", + 3138 => x"70", + 3139 => x"07", + 3140 => x"07", + 3141 => x"52", + 3142 => x"80", + 3143 => x"7c", + 3144 => x"70", + 3145 => x"33", + 3146 => x"80", + 3147 => x"38", + 3148 => x"e0", + 3149 => x"38", + 3150 => x"81", + 3151 => x"53", + 3152 => x"53", + 3153 => x"81", + 3154 => x"10", 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x"90", + 3214 => x"80", + 3215 => x"76", + 3216 => x"3f", + 3217 => x"08", + 3218 => x"7b", + 3219 => x"55", + 3220 => x"82", + 3221 => x"57", + 3222 => x"99", + 3223 => x"16", + 3224 => x"06", + 3225 => x"75", + 3226 => x"89", + 3227 => x"70", + 3228 => x"56", + 3229 => x"78", + 3230 => x"b0", + 3231 => x"72", + 3232 => x"18", + 3233 => x"79", + 3234 => x"70", + 3235 => x"06", + 3236 => x"58", + 3237 => x"38", + 3238 => x"70", + 3239 => x"53", + 3240 => x"8e", + 3241 => x"78", + 3242 => x"53", + 3243 => x"81", + 3244 => x"7d", + 3245 => x"54", + 3246 => x"83", + 3247 => x"7c", + 3248 => x"81", + 3249 => x"72", + 3250 => x"81", + 3251 => x"72", + 3252 => x"38", + 3253 => x"81", + 3254 => x"51", + 3255 => x"75", + 3256 => x"81", + 3257 => x"79", + 3258 => x"38", + 3259 => x"3d", + 3260 => x"70", + 3261 => x"58", + 3262 => x"77", + 3263 => x"81", + 3264 => x"72", + 3265 => x"f5", + 3266 => x"f9", + 3267 => x"81", + 3268 => x"79", + 3269 => x"38", + 3270 => x"96", + 3271 => x"fd", + 3272 => x"3d", + 3273 => x"05", + 3274 => x"52", + 3275 => x"c6", + 3276 => x"0d", + 3277 => x"0d", + 3278 => x"e0", + 3279 => x"88", + 3280 => x"51", + 3281 => x"82", + 3282 => x"53", + 3283 => x"80", + 3284 => x"e0", + 3285 => x"0d", + 3286 => x"0d", + 3287 => x"08", + 3288 => x"d8", + 3289 => x"88", + 3290 => x"52", + 3291 => x"3f", + 3292 => x"d8", + 3293 => x"0d", + 3294 => x"0d", + 3295 => x"57", + 3296 => x"93", + 3297 => x"2e", + 3298 => x"86", + 3299 => x"80", + 3300 => x"55", + 3301 => x"08", + 3302 => x"82", + 3303 => x"81", + 3304 => x"73", + 3305 => x"38", + 3306 => x"80", + 3307 => x"88", + 3308 => x"76", + 3309 => x"07", + 3310 => x"80", + 3311 => x"54", + 3312 => x"80", + 3313 => x"ff", + 3314 => x"ff", + 3315 => x"f7", + 3316 => x"39", + 3317 => x"ff", + 3318 => x"16", + 3319 => x"25", + 3320 => x"76", + 3321 => x"72", + 3322 => x"74", + 3323 => x"52", + 3324 => x"3f", + 3325 => x"74", + 3326 => x"72", + 3327 => x"f7", + 3328 => x"53", + 3329 => x"c8", + 3330 => x"0d", + 3331 => x"0d", + 3332 => x"08", + 3333 => x"dc", + 3334 => x"76", + 3335 => x"d9", + 3336 => x"93", + 3337 => x"3d", + 3338 => x"3d", + 3339 => x"5a", + 3340 => x"7a", + 3341 => x"70", + 3342 => x"58", + 3343 => x"09", + 3344 => x"38", + 3345 => x"05", + 3346 => x"08", + 3347 => x"53", + 3348 => x"f0", + 3349 => x"2e", + 3350 => x"8e", + 3351 => x"08", + 3352 => x"75", + 3353 => x"56", + 3354 => x"b0", + 3355 => x"06", + 3356 => x"74", + 3357 => x"75", + 3358 => x"70", + 3359 => x"73", + 3360 => x"9a", + 3361 => x"f8", + 3362 => x"06", + 3363 => x"0b", + 3364 => x"0c", + 3365 => x"33", + 3366 => x"80", + 3367 => x"75", + 3368 => x"76", + 3369 => x"70", + 3370 => x"57", + 3371 => x"56", + 3372 => x"81", + 3373 => x"14", + 3374 => x"88", + 3375 => x"27", + 3376 => x"f3", + 3377 => x"53", + 3378 => x"89", + 3379 => x"38", + 3380 => x"56", + 3381 => x"80", + 3382 => x"39", + 3383 => x"56", + 3384 => x"80", + 3385 => x"e0", + 3386 => x"38", + 3387 => x"81", + 3388 => x"53", + 3389 => x"81", + 3390 => x"53", + 3391 => x"8e", + 3392 => x"70", + 3393 => x"55", + 3394 => x"27", + 3395 => x"77", + 3396 => x"76", + 3397 => x"75", + 3398 => x"76", + 3399 => x"70", + 3400 => x"56", + 3401 => x"ff", + 3402 => x"80", + 3403 => x"75", + 3404 => x"79", + 3405 => x"75", + 3406 => x"0c", + 3407 => x"04", + 3408 => x"7a", + 3409 => x"80", + 3410 => x"75", + 3411 => x"56", + 3412 => x"a0", + 3413 => x"06", + 3414 => x"08", + 3415 => x"0c", + 3416 => x"33", + 3417 => x"a0", + 3418 => x"73", + 3419 => x"81", + 3420 => x"81", + 3421 => x"76", + 3422 => x"70", + 3423 => x"58", + 3424 => x"09", + 3425 => x"d3", + 3426 => x"81", + 3427 => x"74", + 3428 => x"55", + 3429 => x"e2", + 3430 => x"73", + 3431 => x"09", + 3432 => x"38", + 3433 => x"14", + 3434 => x"08", + 3435 => x"54", + 3436 => x"39", + 3437 => x"81", + 3438 => x"75", + 3439 => x"56", + 3440 => x"39", + 3441 => x"74", + 3442 => x"38", + 3443 => x"80", + 3444 => x"89", + 3445 => x"38", + 3446 => x"d0", + 3447 => x"56", + 3448 => x"80", + 3449 => x"39", + 3450 => x"e1", + 3451 => x"80", + 3452 => x"57", + 3453 => x"74", + 3454 => x"38", + 3455 => x"27", + 3456 => x"14", + 3457 => x"06", + 3458 => x"14", + 3459 => x"06", + 3460 => x"74", + 3461 => x"f9", + 3462 => x"ff", + 3463 => x"89", + 3464 => x"38", + 3465 => x"c5", + 3466 => x"29", + 3467 => x"81", + 3468 => x"75", + 3469 => x"56", + 3470 => x"a0", + 3471 => x"38", + 3472 => x"84", + 3473 => x"56", + 3474 => x"81", + 3475 => x"93", + 3476 => x"3d", + 3477 => x"3d", + 3478 => x"05", + 3479 => x"52", + 3480 => x"87", + 3481 => x"84", + 3482 => x"71", + 3483 => x"0c", + 3484 => x"04", + 3485 => x"02", + 3486 => x"02", + 3487 => x"05", + 3488 => x"83", + 3489 => x"26", + 3490 => x"72", + 3491 => x"c0", + 3492 => x"51", + 3493 => x"80", + 3494 => x"81", + 3495 => x"71", + 3496 => x"29", + 3497 => x"8c", + 3498 => x"71", + 3499 => x"87", + 3500 => x"0c", + 3501 => x"c0", + 3502 => x"71", + 3503 => x"06", + 3504 => x"80", + 3505 => x"73", + 3506 => x"ef", + 3507 => x"29", + 3508 => x"8c", + 3509 => x"fc", + 3510 => x"53", + 3511 => x"38", + 3512 => x"8c", + 3513 => x"80", + 3514 => x"71", + 3515 => x"14", + 3516 => x"84", + 3517 => x"70", + 3518 => x"0c", + 3519 => x"04", + 3520 => x"61", + 3521 => x"8c", + 3522 => x"05", + 3523 => x"5d", + 3524 => x"52", + 3525 => x"3f", + 3526 => x"08", + 3527 => x"55", + 3528 => x"ac", + 3529 => x"58", + 3530 => x"98", + 3531 => x"2b", + 3532 => x"8c", + 3533 => x"92", + 3534 => x"42", + 3535 => x"56", + 3536 => x"87", + 3537 => x"1a", + 3538 => x"52", + 3539 => x"74", + 3540 => x"2a", + 3541 => x"51", + 3542 => x"80", + 3543 => x"78", + 3544 => x"78", + 3545 => x"5a", + 3546 => x"57", + 3547 => x"52", + 3548 => x"87", + 3549 => x"52", + 3550 => x"75", + 3551 => x"80", + 3552 => x"76", + 3553 => x"99", + 3554 => x"0c", + 3555 => x"8c", + 3556 => x"08", + 3557 => x"51", + 3558 => x"38", + 3559 => x"8d", + 3560 => x"1c", + 3561 => x"81", + 3562 => x"53", + 3563 => x"2e", + 3564 => x"fc", + 3565 => x"52", + 3566 => x"7e", + 3567 => x"80", + 3568 => x"80", + 3569 => x"71", + 3570 => x"38", + 3571 => x"54", + 3572 => x"c8", + 3573 => x"0d", + 3574 => x"0d", + 3575 => x"02", + 3576 => x"05", + 3577 => x"5c", + 3578 => x"52", + 3579 => x"3f", + 3580 => x"08", + 3581 => x"55", + 3582 => x"ae", + 3583 => x"87", + 3584 => x"73", + 3585 => x"c0", + 3586 => x"87", + 3587 => x"12", + 3588 => x"57", + 3589 => x"76", + 3590 => x"92", + 3591 => x"71", + 3592 => x"75", + 3593 => x"74", + 3594 => x"2a", + 3595 => x"51", + 3596 => x"80", + 3597 => x"76", + 3598 => x"58", + 3599 => x"81", + 3600 => x"81", + 3601 => x"06", + 3602 => x"80", + 3603 => x"75", + 3604 => x"d3", + 3605 => x"52", + 3606 => x"87", + 3607 => x"80", + 3608 => x"81", + 3609 => x"c0", + 3610 => x"53", + 3611 => x"82", + 3612 => x"71", + 3613 => x"1a", + 3614 => x"81", + 3615 => x"ff", + 3616 => x"1d", + 3617 => x"79", + 3618 => x"38", + 3619 => x"80", + 3620 => x"87", + 3621 => x"26", + 3622 => x"73", + 3623 => x"06", + 3624 => x"2e", + 3625 => x"52", + 3626 => x"82", + 3627 => x"8f", + 3628 => x"f7", + 3629 => x"02", + 3630 => x"05", + 3631 => x"05", + 3632 => x"71", + 3633 => x"56", + 3634 => x"82", + 3635 => x"81", + 3636 => x"54", + 3637 => x"81", + 3638 => x"2e", + 3639 => x"74", + 3640 => x"72", + 3641 => x"38", + 3642 => x"83", + 3643 => x"a0", + 3644 => x"29", + 3645 => x"8c", + 3646 => x"51", + 3647 => x"88", + 3648 => x"0c", + 3649 => x"39", + 3650 => x"0c", + 3651 => x"39", + 3652 => x"82", + 3653 => x"8b", + 3654 => x"ff", + 3655 => x"70", + 3656 => x"33", + 3657 => x"72", + 3658 => x"c8", + 3659 => x"52", + 3660 => x"04", + 3661 => x"75", + 3662 => x"82", + 3663 => x"90", + 3664 => x"2b", + 3665 => x"33", + 3666 => x"33", + 3667 => x"07", + 3668 => x"0c", + 3669 => x"54", + 3670 => x"0d", + 3671 => x"0d", + 3672 => x"05", + 3673 => x"52", + 3674 => x"70", + 3675 => x"34", + 3676 => x"51", + 3677 => x"83", + 3678 => x"ff", + 3679 => x"75", + 3680 => x"72", + 3681 => x"54", + 3682 => x"2a", + 3683 => x"70", + 3684 => x"34", + 3685 => x"51", + 3686 => x"81", + 3687 => x"70", + 3688 => x"70", + 3689 => x"3d", + 3690 => x"3d", + 3691 => x"77", + 3692 => x"70", + 3693 => x"38", + 3694 => x"05", + 3695 => x"70", + 3696 => x"34", + 3697 => x"70", + 3698 => x"3d", + 3699 => x"3d", + 3700 => x"76", + 3701 => x"72", + 3702 => x"05", + 3703 => x"11", + 3704 => x"38", + 3705 => x"04", + 3706 => x"78", + 3707 => x"56", + 3708 => x"81", + 3709 => x"74", + 3710 => x"56", + 3711 => x"31", + 3712 => x"52", + 3713 => x"80", + 3714 => x"71", + 3715 => x"38", + 3716 => x"c8", + 3717 => x"0d", + 3718 => x"0d", + 3719 => x"33", + 3720 => x"70", + 3721 => x"38", + 3722 => x"94", + 3723 => x"70", + 3724 => x"70", + 3725 => x"38", + 3726 => x"09", + 3727 => x"38", + 3728 => x"93", + 3729 => x"3d", + 3730 => x"0b", + 3731 => x"0c", + 3732 => x"82", + 3733 => x"04", + 3734 => x"79", + 3735 => x"83", + 3736 => x"58", + 3737 => x"80", + 3738 => x"54", + 3739 => x"53", + 3740 => x"53", + 3741 => x"52", + 3742 => x"3f", + 3743 => x"08", + 3744 => x"81", + 3745 => x"82", + 3746 => x"83", + 3747 => x"16", + 3748 => x"08", + 3749 => x"9c", + 3750 => x"a4", + 3751 => x"33", + 3752 => x"2e", + 3753 => x"98", + 3754 => x"b0", + 3755 => x"17", + 3756 => x"76", + 3757 => x"33", + 3758 => x"3f", + 3759 => x"58", + 3760 => x"c8", + 3761 => x"0d", + 3762 => x"0d", + 3763 => x"57", + 3764 => x"17", + 3765 => x"af", + 3766 => x"fe", + 3767 => x"93", + 3768 => x"82", + 3769 => x"9f", + 3770 => x"74", + 3771 => x"52", + 3772 => x"51", + 3773 => x"82", + 3774 => x"80", + 3775 => x"ff", + 3776 => x"74", + 3777 => x"75", + 3778 => x"0c", + 3779 => x"04", + 3780 => x"7a", + 3781 => x"fe", + 3782 => x"93", + 3783 => x"82", + 3784 => x"81", + 3785 => x"33", + 3786 => x"2e", + 3787 => x"80", + 3788 => x"17", + 3789 => x"81", + 3790 => x"06", + 3791 => x"84", + 3792 => x"93", + 3793 => x"b4", + 3794 => x"56", + 3795 => x"82", + 3796 => x"84", + 3797 => x"fc", + 3798 => x"8b", + 3799 => x"52", + 3800 => x"97", + 3801 => x"85", + 3802 => x"84", + 3803 => x"fc", + 3804 => x"17", + 3805 => x"9c", + 3806 => x"ff", + 3807 => x"08", + 3808 => x"17", + 3809 => x"3f", + 3810 => x"81", + 3811 => x"19", + 3812 => x"53", + 3813 => x"17", + 3814 => x"bd", + 3815 => x"18", + 3816 => x"80", + 3817 => x"33", + 3818 => x"3f", + 3819 => x"08", + 3820 => x"38", + 3821 => x"82", + 3822 => x"8a", + 3823 => x"fb", + 3824 => x"fe", + 3825 => x"08", + 3826 => x"56", + 3827 => x"74", + 3828 => x"38", + 3829 => x"70", + 3830 => x"16", + 3831 => x"53", + 3832 => x"c8", + 3833 => x"0d", + 3834 => x"0d", + 3835 => x"08", + 3836 => x"81", + 3837 => x"38", + 3838 => x"75", + 3839 => x"81", + 3840 => x"39", + 3841 => x"54", + 3842 => x"2e", + 3843 => x"72", + 3844 => x"38", + 3845 => x"8d", + 3846 => x"39", + 3847 => x"81", + 3848 => x"b6", + 3849 => x"2a", + 3850 => x"2a", + 3851 => x"05", + 3852 => x"57", + 3853 => x"82", + 3854 => x"81", + 3855 => x"83", + 3856 => x"b4", + 3857 => x"19", + 3858 => x"a4", + 3859 => x"55", + 3860 => x"59", + 3861 => x"3f", + 3862 => x"08", + 3863 => x"76", + 3864 => x"14", + 3865 => x"70", + 3866 => x"07", + 3867 => x"71", + 3868 => x"52", + 3869 => x"72", + 3870 => x"77", + 3871 => x"56", + 3872 => x"74", + 3873 => x"15", + 3874 => x"73", + 3875 => x"3f", + 3876 => x"08", + 3877 => x"74", + 3878 => x"06", + 3879 => x"05", + 3880 => x"3f", + 3881 => x"08", + 3882 => x"06", + 3883 => x"74", + 3884 => x"15", + 3885 => x"73", + 3886 => x"3f", + 3887 => x"08", + 3888 => x"82", + 3889 => x"06", + 3890 => x"05", + 3891 => x"3f", + 3892 => x"08", + 3893 => x"56", + 3894 => x"56", + 3895 => x"c8", + 3896 => x"0d", + 3897 => x"0d", + 3898 => x"58", + 3899 => x"57", + 3900 => x"82", + 3901 => x"98", + 3902 => x"82", + 3903 => x"33", + 3904 => x"2e", + 3905 => x"72", + 3906 => x"38", + 3907 => x"8d", + 3908 => x"39", + 3909 => x"81", + 3910 => x"88", + 3911 => x"2a", + 3912 => x"2a", + 3913 => x"05", + 3914 => x"59", + 3915 => x"82", + 3916 => x"57", + 3917 => x"08", + 3918 => x"78", + 3919 => x"15", + 3920 => x"1b", + 3921 => x"56", + 3922 => x"75", + 3923 => x"2e", + 3924 => x"84", + 3925 => x"06", + 3926 => x"06", + 3927 => x"53", + 3928 => x"81", + 3929 => x"34", + 3930 => x"a4", + 3931 => x"52", + 3932 => x"d5", + 3933 => x"c8", + 3934 => x"93", + 3935 => x"a4", + 3936 => x"ff", + 3937 => x"11", + 3938 => x"78", + 3939 => x"55", + 3940 => x"8f", + 3941 => x"2a", + 3942 => x"8f", + 3943 => x"f0", + 3944 => x"73", + 3945 => x"0b", + 3946 => x"80", + 3947 => x"88", + 3948 => x"08", + 3949 => x"51", + 3950 => x"82", + 3951 => x"57", + 3952 => x"08", + 3953 => x"75", + 3954 => x"06", + 3955 => x"83", + 3956 => x"05", + 3957 => x"f7", + 3958 => x"0b", + 3959 => x"80", + 3960 => x"87", + 3961 => x"08", + 3962 => x"51", + 3963 => x"82", + 3964 => x"57", + 3965 => x"08", + 3966 => x"f0", + 3967 => x"82", + 3968 => x"06", + 3969 => x"05", + 3970 => x"54", + 3971 => x"3f", + 3972 => x"08", + 3973 => x"76", + 3974 => x"51", + 3975 => x"81", + 3976 => x"34", + 3977 => x"c8", + 3978 => x"0d", + 3979 => x"0d", + 3980 => x"72", + 3981 => x"55", + 3982 => x"27", + 3983 => x"15", + 3984 => x"86", + 3985 => x"81", + 3986 => x"80", + 3987 => x"ff", + 3988 => x"74", + 3989 => x"3f", + 3990 => x"08", + 3991 => x"c8", + 3992 => x"38", + 3993 => x"56", + 3994 => x"81", + 3995 => x"39", + 3996 => x"08", + 3997 => x"39", + 3998 => x"51", + 3999 => x"82", + 4000 => x"56", + 4001 => x"08", + 4002 => x"c9", + 4003 => x"c8", + 4004 => x"d2", + 4005 => x"c8", + 4006 => x"cf", + 4007 => x"73", + 4008 => x"fc", + 4009 => x"93", + 4010 => x"38", + 4011 => x"fe", + 4012 => x"15", + 4013 => x"93", + 4014 => x"08", + 4015 => x"16", + 4016 => x"33", + 4017 => x"73", + 4018 => x"75", + 4019 => x"08", + 4020 => x"a4", + 4021 => x"75", + 4022 => x"0c", + 4023 => x"04", + 4024 => x"7d", + 4025 => x"5b", + 4026 => x"95", + 4027 => x"08", + 4028 => x"2e", + 4029 => x"19", + 4030 => x"b7", + 4031 => x"b3", + 4032 => x"7b", + 4033 => x"3f", + 4034 => x"82", + 4035 => x"27", + 4036 => x"82", + 4037 => x"55", + 4038 => x"08", + 4039 => x"db", + 4040 => x"c8", + 4041 => x"19", + 4042 => x"c8", + 4043 => x"cb", + 4044 => x"80", + 4045 => x"08", + 4046 => x"bf", + 4047 => x"77", + 4048 => x"81", + 4049 => x"38", + 4050 => x"98", + 4051 => x"26", + 4052 => x"57", + 4053 => x"51", + 4054 => x"82", + 4055 => x"56", + 4056 => x"93", + 4057 => x"2e", + 4058 => x"86", + 4059 => x"c8", + 4060 => x"ff", + 4061 => x"70", + 4062 => x"25", + 4063 => x"79", + 4064 => x"56", + 4065 => x"f3", + 4066 => x"2e", + 4067 => x"19", + 4068 => x"76", + 4069 => x"75", + 4070 => x"27", + 4071 => x"58", + 4072 => x"80", + 4073 => x"57", + 4074 => x"98", + 4075 => x"26", + 4076 => x"57", + 4077 => x"81", + 4078 => x"52", + 4079 => x"a9", + 4080 => x"c8", + 4081 => x"93", + 4082 => x"2e", + 4083 => x"5a", + 4084 => x"08", + 4085 => x"81", + 4086 => x"82", + 4087 => x"5a", + 4088 => x"70", + 4089 => x"07", + 4090 => x"7d", + 4091 => x"56", + 4092 => x"ff", + 4093 => x"2e", + 4094 => x"ff", + 4095 => x"55", + 4096 => x"ff", + 4097 => x"78", + 4098 => x"3f", + 4099 => x"08", + 4100 => x"08", + 4101 => x"93", + 4102 => x"80", + 4103 => x"70", + 4104 => x"2a", + 4105 => x"57", + 4106 => x"74", + 4107 => x"38", + 4108 => x"52", + 4109 => x"ad", + 4110 => x"c8", + 4111 => x"a6", + 4112 => x"1a", + 4113 => x"08", + 4114 => x"90", + 4115 => x"26", + 4116 => x"19", + 4117 => x"90", + 4118 => x"19", + 4119 => x"54", + 4120 => x"34", + 4121 => x"57", + 4122 => x"8d", + 4123 => x"80", + 4124 => x"75", + 4125 => x"81", + 4126 => x"74", + 4127 => x"0c", + 4128 => x"04", + 4129 => x"7b", + 4130 => x"f3", + 4131 => x"55", + 4132 => x"08", + 4133 => x"7c", + 4134 => x"f6", + 4135 => x"93", + 4136 => x"93", + 4137 => x"19", + 4138 => x"80", + 4139 => x"b4", + 4140 => x"55", + 4141 => x"74", + 4142 => x"80", + 4143 => x"77", + 4144 => x"17", + 4145 => x"75", + 4146 => x"77", + 4147 => x"53", + 4148 => x"17", + 4149 => x"81", + 4150 => x"c8", + 4151 => x"df", + 4152 => x"8a", + 4153 => x"58", + 4154 => x"83", + 4155 => x"77", + 4156 => x"93", + 4157 => x"3d", + 4158 => x"3d", + 4159 => x"71", + 4160 => x"57", + 4161 => x"0a", + 4162 => x"74", + 4163 => x"72", + 4164 => x"38", + 4165 => x"ae", + 4166 => x"18", + 4167 => x"08", + 4168 => x"38", + 4169 => x"82", + 4170 => x"38", + 4171 => x"54", + 4172 => x"74", + 4173 => x"82", + 4174 => x"22", + 4175 => x"79", + 4176 => x"38", + 4177 => x"98", + 4178 => x"d1", + 4179 => x"22", + 4180 => x"54", + 4181 => x"26", + 4182 => x"52", + 4183 => x"89", + 4184 => x"c8", + 4185 => x"93", + 4186 => x"2e", + 4187 => x"0b", + 4188 => x"08", + 4189 => x"98", + 4190 => x"93", + 4191 => x"86", + 4192 => x"80", + 4193 => x"73", + 4194 => x"73", + 4195 => x"73", + 4196 => x"f4", + 4197 => x"93", + 4198 => x"18", + 4199 => x"18", + 4200 => x"98", + 4201 => x"2e", + 4202 => x"39", + 4203 => x"39", + 4204 => x"98", + 4205 => x"98", + 4206 => x"83", + 4207 => x"b4", + 4208 => x"0c", + 4209 => x"82", + 4210 => x"8a", + 4211 => x"f9", + 4212 => x"7b", + 4213 => x"13", + 4214 => x"59", + 4215 => x"f0", + 4216 => x"27", + 4217 => x"0b", + 4218 => x"84", + 4219 => x"08", + 4220 => x"da", + 4221 => x"ff", + 4222 => x"81", + 4223 => x"15", + 4224 => x"98", + 4225 => x"15", + 4226 => x"75", + 4227 => x"18", + 4228 => x"77", + 4229 => x"a6", + 4230 => x"16", + 4231 => x"81", + 4232 => x"17", + 4233 => x"77", + 4234 => x"51", + 4235 => x"8e", + 4236 => x"08", + 4237 => x"f3", + 4238 => x"93", + 4239 => x"82", + 4240 => x"82", + 4241 => x"27", + 4242 => x"81", + 4243 => x"c8", + 4244 => x"80", + 4245 => x"17", + 4246 => x"c8", + 4247 => x"cc", + 4248 => x"38", + 4249 => x"0c", + 4250 => x"e2", + 4251 => x"08", + 4252 => x"f8", + 4253 => x"93", + 4254 => x"87", + 4255 => x"c8", + 4256 => x"80", + 4257 => x"53", + 4258 => x"08", + 4259 => x"38", + 4260 => x"93", + 4261 => x"2e", + 4262 => x"93", + 4263 => x"76", + 4264 => x"3f", + 4265 => x"93", + 4266 => x"38", + 4267 => x"0c", + 4268 => x"51", + 4269 => x"82", + 4270 => x"98", + 4271 => x"90", + 4272 => x"83", + 4273 => x"b4", + 4274 => x"0c", + 4275 => x"82", + 4276 => x"89", + 4277 => x"f8", + 4278 => x"7c", + 4279 => x"5a", + 4280 => x"75", + 4281 => x"3f", + 4282 => x"08", + 4283 => x"c8", + 4284 => x"38", + 4285 => x"08", + 4286 => x"08", + 4287 => x"ef", + 4288 => x"93", + 4289 => x"82", + 4290 => x"80", + 4291 => x"93", + 4292 => x"17", + 4293 => x"51", + 4294 => x"81", + 4295 => x"81", + 4296 => x"81", + 4297 => x"70", + 4298 => x"07", + 4299 => x"80", + 4300 => x"81", + 4301 => x"79", + 4302 => x"83", + 4303 => x"81", + 4304 => x"fd", + 4305 => x"93", + 4306 => x"82", + 4307 => x"80", + 4308 => x"38", + 4309 => x"09", + 4310 => x"38", + 4311 => x"82", + 4312 => x"8a", + 4313 => x"fd", + 4314 => x"9a", + 4315 => x"eb", + 4316 => x"93", + 4317 => x"ff", + 4318 => x"70", + 4319 => x"53", + 4320 => x"09", + 4321 => x"38", + 4322 => x"eb", + 4323 => x"93", + 4324 => x"2b", + 4325 => x"72", + 4326 => x"0c", + 4327 => x"04", + 4328 => x"77", + 4329 => x"ff", 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x"ef", + 4389 => x"84", + 4390 => x"39", + 4391 => x"52", + 4392 => x"a5", + 4393 => x"c8", + 4394 => x"93", + 4395 => x"d1", + 4396 => x"08", + 4397 => x"54", + 4398 => x"db", + 4399 => x"08", + 4400 => x"bf", + 4401 => x"73", + 4402 => x"8b", + 4403 => x"83", + 4404 => x"06", + 4405 => x"73", + 4406 => x"53", + 4407 => x"74", + 4408 => x"3f", + 4409 => x"08", + 4410 => x"38", + 4411 => x"51", + 4412 => x"82", + 4413 => x"57", + 4414 => x"08", + 4415 => x"9c", + 4416 => x"73", + 4417 => x"0c", + 4418 => x"04", + 4419 => x"77", + 4420 => x"54", + 4421 => x"51", + 4422 => x"82", + 4423 => x"55", + 4424 => x"08", + 4425 => x"14", + 4426 => x"51", + 4427 => x"82", + 4428 => x"55", + 4429 => x"08", + 4430 => x"53", + 4431 => x"08", + 4432 => x"08", + 4433 => x"3f", + 4434 => x"14", + 4435 => x"08", + 4436 => x"3f", + 4437 => x"17", + 4438 => x"93", + 4439 => x"3d", + 4440 => x"3d", + 4441 => x"08", + 4442 => x"54", + 4443 => x"53", + 4444 => x"82", + 4445 => x"54", + 4446 => x"08", + 4447 => x"13", + 4448 => x"73", + 4449 => x"83", + 4450 => x"82", + 4451 => x"86", + 4452 => x"fa", + 4453 => x"7a", + 4454 => x"0b", + 4455 => x"98", + 4456 => x"2e", + 4457 => x"80", + 4458 => x"9c", + 4459 => x"70", + 4460 => x"56", + 4461 => x"a0", + 4462 => x"72", + 4463 => x"81", + 4464 => x"81", + 4465 => x"89", + 4466 => x"06", + 4467 => x"15", + 4468 => x"ae", + 4469 => x"34", + 4470 => x"75", + 4471 => x"52", + 4472 => x"34", + 4473 => x"8a", + 4474 => x"38", + 4475 => x"05", + 4476 => x"81", + 4477 => x"17", + 4478 => x"12", + 4479 => x"34", + 4480 => x"9c", + 4481 => x"ac", + 4482 => x"c8", + 4483 => x"9c", + 4484 => x"05", + 4485 => x"3f", + 4486 => x"08", + 4487 => x"9c", + 4488 => x"05", + 4489 => x"3f", + 4490 => x"08", + 4491 => x"88", + 4492 => x"f5", + 4493 => x"70", + 4494 => x"05", + 4495 => x"8b", + 4496 => x"7a", + 4497 => x"3f", + 4498 => x"58", + 4499 => x"55", + 4500 => x"2e", + 4501 => x"80", + 4502 => x"17", + 4503 => x"19", + 4504 => x"70", + 4505 => x"2a", + 4506 => x"07", + 4507 => x"59", + 4508 => x"8c", + 4509 => x"54", + 4510 => x"81", + 4511 => x"39", + 4512 => x"70", + 4513 => x"dc", + 4514 => x"70", + 4515 => x"2a", + 4516 => x"51", + 4517 => x"2e", + 4518 => x"54", + 4519 => x"82", + 4520 => x"19", + 4521 => x"54", + 4522 => x"83", + 4523 => x"73", + 4524 => x"80", + 4525 => x"39", + 4526 => x"33", + 4527 => x"57", + 4528 => x"27", + 4529 => x"75", + 4530 => x"30", + 4531 => x"32", + 4532 => x"80", + 4533 => x"25", + 4534 => x"56", + 4535 => x"80", + 4536 => x"84", + 4537 => x"57", + 4538 => x"70", + 4539 => x"5a", + 4540 => x"09", + 4541 => x"38", + 4542 => x"77", + 4543 => x"51", + 4544 => x"80", + 4545 => x"81", + 4546 => x"81", + 4547 => x"07", + 4548 => x"38", + 4549 => x"75", + 4550 => x"30", + 4551 => x"7a", + 4552 => x"51", + 4553 => x"80", + 4554 => x"79", + 4555 => x"30", + 4556 => x"70", + 4557 => x"25", + 4558 => x"07", + 4559 => x"51", + 4560 => x"b1", + 4561 => x"8b", + 4562 => x"39", + 4563 => x"54", + 4564 => x"8c", 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x"88", + 4624 => x"39", + 4625 => x"80", + 4626 => x"51", + 4627 => x"af", + 4628 => x"06", + 4629 => x"55", + 4630 => x"33", + 4631 => x"72", + 4632 => x"09", + 4633 => x"38", + 4634 => x"74", + 4635 => x"d4", + 4636 => x"88", + 4637 => x"70", + 4638 => x"72", + 4639 => x"38", + 4640 => x"ab", + 4641 => x"52", + 4642 => x"ee", + 4643 => x"c8", + 4644 => x"aa", + 4645 => x"81", + 4646 => x"3d", + 4647 => x"75", + 4648 => x"3f", + 4649 => x"08", + 4650 => x"c8", + 4651 => x"38", + 4652 => x"c6", + 4653 => x"c8", + 4654 => x"33", + 4655 => x"93", + 4656 => x"2e", + 4657 => x"82", + 4658 => x"84", + 4659 => x"06", + 4660 => x"73", + 4661 => x"81", + 4662 => x"72", + 4663 => x"38", + 4664 => x"70", + 4665 => x"53", + 4666 => x"ff", + 4667 => x"80", + 4668 => x"34", + 4669 => x"c6", + 4670 => x"2a", + 4671 => x"51", + 4672 => x"38", + 4673 => x"39", + 4674 => x"70", + 4675 => x"53", + 4676 => x"86", + 4677 => x"84", + 4678 => x"06", + 4679 => x"72", + 4680 => x"f1", + 4681 => x"08", + 4682 => x"17", + 4683 => x"76", + 4684 => x"3f", + 4685 => x"08", + 4686 => x"fe", + 4687 => x"82", + 4688 => x"88", + 4689 => x"f6", + 4690 => x"59", + 4691 => x"70", + 4692 => x"56", + 4693 => x"2e", + 4694 => x"76", + 4695 => x"58", + 4696 => x"32", + 4697 => x"a0", + 4698 => x"2a", + 4699 => x"52", + 4700 => x"38", + 4701 => x"09", + 4702 => x"a9", + 4703 => x"d0", + 4704 => x"70", + 4705 => x"38", + 4706 => x"81", + 4707 => x"11", + 4708 => x"70", + 4709 => x"ff", + 4710 => x"81", + 4711 => x"58", + 4712 => x"1b", + 4713 => x"08", + 4714 => x"75", + 4715 => x"57", + 4716 => x"81", + 4717 => x"ff", + 4718 => x"54", + 4719 => x"26", + 4720 => x"14", + 4721 => x"06", + 4722 => x"9f", + 4723 => x"99", + 4724 => x"e0", + 4725 => x"ff", + 4726 => x"73", + 4727 => x"32", + 4728 => x"72", + 4729 => x"73", + 4730 => x"53", + 4731 => x"70", + 4732 => x"73", + 4733 => x"32", + 4734 => x"72", + 4735 => x"73", + 4736 => x"53", + 4737 => x"70", + 4738 => x"38", + 4739 => x"83", + 4740 => x"8c", + 4741 => x"77", + 4742 => x"38", + 4743 => x"0c", + 4744 => x"86", + 4745 => x"f8", + 4746 => x"82", + 4747 => x"8c", + 4748 => x"fb", + 4749 => x"56", + 4750 => x"17", + 4751 => x"b0", + 4752 => x"52", + 4753 => x"81", + 4754 => x"82", + 4755 => x"81", + 4756 => x"b2", + 4757 => x"c3", + 4758 => x"c8", + 4759 => x"ff", + 4760 => x"55", + 4761 => x"d5", + 4762 => x"06", + 4763 => x"80", + 4764 => x"33", + 4765 => x"81", + 4766 => x"81", + 4767 => x"81", + 4768 => x"eb", + 4769 => x"70", + 4770 => x"07", + 4771 => x"73", + 4772 => x"16", + 4773 => x"81", + 4774 => x"81", + 4775 => x"83", + 4776 => x"80", + 4777 => x"16", + 4778 => x"3f", + 4779 => x"08", + 4780 => x"c8", + 4781 => x"9d", + 4782 => x"81", + 4783 => x"81", + 4784 => x"de", + 4785 => x"93", + 4786 => x"82", + 4787 => x"80", + 4788 => x"82", + 4789 => x"93", + 4790 => x"3d", + 4791 => x"3d", + 4792 => x"84", + 4793 => x"05", + 4794 => x"80", + 4795 => x"51", + 4796 => x"82", + 4797 => x"58", + 4798 => x"0b", + 4799 => x"08", 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x"2e", + 4859 => x"52", + 4860 => x"bf", + 4861 => x"c8", + 4862 => x"06", + 4863 => x"27", + 4864 => x"14", + 4865 => x"27", + 4866 => x"56", + 4867 => x"85", + 4868 => x"56", + 4869 => x"85", + 4870 => x"15", + 4871 => x"3f", + 4872 => x"08", + 4873 => x"06", + 4874 => x"72", + 4875 => x"09", + 4876 => x"ed", + 4877 => x"15", + 4878 => x"3f", + 4879 => x"08", + 4880 => x"06", + 4881 => x"38", + 4882 => x"51", + 4883 => x"82", + 4884 => x"54", + 4885 => x"0c", + 4886 => x"33", + 4887 => x"80", + 4888 => x"ff", + 4889 => x"56", + 4890 => x"84", + 4891 => x"15", + 4892 => x"29", + 4893 => x"33", + 4894 => x"72", + 4895 => x"72", + 4896 => x"06", + 4897 => x"2e", + 4898 => x"13", + 4899 => x"72", + 4900 => x"38", + 4901 => x"89", + 4902 => x"15", + 4903 => x"3f", + 4904 => x"08", + 4905 => x"82", + 4906 => x"83", + 4907 => x"8f", + 4908 => x"56", + 4909 => x"38", + 4910 => x"51", + 4911 => x"82", + 4912 => x"83", + 4913 => x"53", + 4914 => x"80", + 4915 => x"d8", + 4916 => x"93", + 4917 => x"80", + 4918 => x"d8", + 4919 => x"93", + 4920 => x"ff", + 4921 => x"8d", + 4922 => x"2e", + 4923 => x"88", + 4924 => x"1a", + 4925 => x"05", + 4926 => x"56", + 4927 => x"83", + 4928 => x"15", + 4929 => x"78", + 4930 => x"b0", + 4931 => x"93", + 4932 => x"8d", + 4933 => x"c8", + 4934 => x"83", + 4935 => x"57", + 4936 => x"08", + 4937 => x"ff", + 4938 => x"38", + 4939 => x"83", + 4940 => x"83", + 4941 => x"72", + 4942 => x"83", + 4943 => x"8d", + 4944 => x"2e", + 4945 => x"82", + 4946 => x"0c", + 4947 => x"0c", + 4948 => x"16", + 4949 => x"ac", + 4950 => x"83", + 4951 => x"06", + 4952 => x"de", + 4953 => x"b3", + 4954 => x"c8", + 4955 => x"ff", + 4956 => x"56", + 4957 => x"38", + 4958 => x"53", + 4959 => x"82", + 4960 => x"e0", + 4961 => x"ac", + 4962 => x"c8", + 4963 => x"0c", + 4964 => x"82", + 4965 => x"39", + 4966 => x"53", + 4967 => x"80", + 4968 => x"38", + 4969 => x"14", + 4970 => x"76", + 4971 => x"81", + 4972 => x"98", + 4973 => x"53", + 4974 => x"15", + 4975 => x"16", + 4976 => x"81", + 4977 => x"08", + 4978 => x"51", + 4979 => x"13", + 4980 => x"8d", + 4981 => x"16", + 4982 => x"c5", + 4983 => x"90", + 4984 => x"0b", + 4985 => x"ff", + 4986 => x"16", + 4987 => x"2e", + 4988 => x"81", + 4989 => x"e4", + 4990 => x"9f", + 4991 => x"c8", + 4992 => x"ff", + 4993 => x"81", + 4994 => x"06", + 4995 => x"81", + 4996 => x"51", + 4997 => x"82", + 4998 => x"80", + 4999 => x"93", + 5000 => x"16", + 5001 => x"15", + 5002 => x"3f", + 5003 => x"08", + 5004 => x"06", + 5005 => x"d4", + 5006 => x"81", + 5007 => x"38", + 5008 => x"d5", + 5009 => x"93", + 5010 => x"8b", + 5011 => x"2e", + 5012 => x"b3", + 5013 => x"15", + 5014 => x"3f", + 5015 => x"08", + 5016 => x"e4", + 5017 => x"81", + 5018 => x"84", + 5019 => x"d5", + 5020 => x"93", + 5021 => x"16", + 5022 => x"15", + 5023 => x"3f", + 5024 => x"08", + 5025 => x"76", + 5026 => x"93", + 5027 => x"05", + 5028 => x"93", + 5029 => x"86", + 5030 => x"0b", + 5031 => x"80", + 5032 => x"93", + 5033 => x"3d", + 5034 => x"3d", + 5035 => x"89", + 5036 => x"2e", + 5037 => x"08", + 5038 => x"38", + 5039 => x"33", + 5040 => x"80", + 5041 => x"84", + 5042 => x"14", + 5043 => x"71", + 5044 => x"81", + 5045 => x"81", + 5046 => x"ce", + 5047 => x"93", + 5048 => x"06", + 5049 => x"38", + 5050 => x"53", + 5051 => x"09", + 5052 => x"38", + 5053 => x"78", + 5054 => x"52", + 5055 => x"c8", + 5056 => x"0d", + 5057 => x"0d", + 5058 => x"33", + 5059 => x"3d", + 5060 => x"56", + 5061 => x"82", + 5062 => x"55", + 5063 => x"0b", + 5064 => x"08", + 5065 => x"38", + 5066 => x"08", + 5067 => x"93", + 5068 => x"08", + 5069 => x"80", + 5070 => x"80", + 5071 => x"80", + 5072 => x"78", + 5073 => x"34", + 5074 => x"82", + 5075 => x"79", + 5076 => x"75", + 5077 => x"2e", + 5078 => x"53", + 5079 => x"53", + 5080 => x"f6", + 5081 => x"93", + 5082 => x"73", + 5083 => x"0c", + 5084 => x"04", + 5085 => x"67", + 5086 => x"80", + 5087 => x"58", + 5088 => x"77", + 5089 => x"e9", + 5090 => x"06", + 5091 => x"3d", + 5092 => x"99", + 5093 => x"52", + 5094 => x"3f", + 5095 => x"08", + 5096 => x"c8", + 5097 => x"38", + 5098 => x"52", + 5099 => x"05", + 5100 => x"3f", + 5101 => x"08", + 5102 => x"c8", + 5103 => x"02", + 5104 => x"33", + 5105 => x"56", + 5106 => x"25", + 5107 => x"56", + 5108 => x"55", + 5109 => x"81", + 5110 => x"80", + 5111 => x"75", + 5112 => x"81", + 5113 => x"97", + 5114 => x"51", + 5115 => x"82", + 5116 => x"56", + 5117 => x"57", + 5118 => x"b2", + 5119 => x"06", + 5120 => x"2e", + 5121 => x"56", + 5122 => x"82", + 5123 => x"06", + 5124 => x"80", + 5125 => x"88", + 5126 => x"d0", + 5127 => x"2a", + 5128 => x"51", + 5129 => x"2e", + 5130 => x"62", + 5131 => x"e6", + 5132 => x"93", + 5133 => x"82", + 5134 => x"52", + 5135 => x"51", + 5136 => x"62", + 5137 => x"8b", + 5138 => x"53", + 5139 => x"51", + 5140 => x"75", + 5141 => x"05", + 5142 => x"3f", + 5143 => x"0b", + 5144 => x"78", + 5145 => x"e9", + 5146 => x"11", + 5147 => x"7a", + 5148 => x"d4", + 5149 => x"55", + 5150 => x"82", + 5151 => x"56", + 5152 => x"08", + 5153 => x"74", + 5154 => x"d4", + 5155 => x"93", + 5156 => x"ff", + 5157 => x"0c", + 5158 => x"39", + 5159 => x"38", + 5160 => x"33", + 5161 => x"70", + 5162 => x"56", + 5163 => x"2e", + 5164 => x"56", + 5165 => x"81", + 5166 => x"06", + 5167 => x"80", + 5168 => x"02", + 5169 => x"81", + 5170 => x"80", + 5171 => x"87", + 5172 => x"98", + 5173 => x"2a", + 5174 => x"51", + 5175 => x"2e", + 5176 => x"80", + 5177 => x"7a", + 5178 => x"a0", + 5179 => x"a4", + 5180 => x"75", + 5181 => x"62", + 5182 => x"e4", + 5183 => x"93", + 5184 => x"19", + 5185 => x"05", + 5186 => x"3f", + 5187 => x"08", + 5188 => x"74", + 5189 => x"15", + 5190 => x"23", + 5191 => x"34", + 5192 => x"34", + 5193 => x"0c", + 5194 => x"0c", + 5195 => x"75", + 5196 => x"51", + 5197 => x"76", + 5198 => x"81", + 5199 => x"74", + 5200 => x"a3", + 5201 => x"08", + 5202 => x"9b", + 5203 => x"08", + 5204 => x"7a", + 5205 => x"70", + 5206 => x"1b", + 5207 => x"08", + 5208 => x"51", + 5209 => x"76", + 5210 => x"d4", + 5211 => x"93", + 5212 => x"82", + 5213 => x"81", + 5214 => x"82", + 5215 => x"2e", + 5216 => x"83", + 5217 => x"78", + 5218 => x"75", + 5219 => x"07", + 5220 => x"7b", + 5221 => x"51", + 5222 => x"cb", + 5223 => x"19", + 5224 => x"c8", + 5225 => x"ff", + 5226 => x"80", + 5227 => x"76", + 5228 => x"d4", + 5229 => x"93", + 5230 => x"38", + 5231 => x"39", + 5232 => x"82", + 5233 => x"05", + 5234 => x"0c", + 5235 => x"74", + 5236 => x"52", + 5237 => x"33", + 5238 => x"a4", + 5239 => x"c8", + 5240 => x"83", + 5241 => x"75", + 5242 => x"38", + 5243 => x"75", + 5244 => x"93", + 5245 => x"3d", + 5246 => x"3d", + 5247 => x"64", + 5248 => x"5a", + 5249 => x"0c", + 5250 => x"05", + 5251 => x"f9", + 5252 => x"93", + 5253 => x"82", + 5254 => x"8a", + 5255 => x"33", + 5256 => x"2e", + 5257 => x"56", + 5258 => x"90", + 5259 => x"06", + 5260 => x"74", + 5261 => x"a0", + 5262 => x"82", + 5263 => x"34", + 5264 => x"94", + 5265 => x"91", + 5266 => x"56", + 5267 => x"82", + 5268 => x"34", + 5269 => x"80", + 5270 => x"91", + 5271 => x"56", + 5272 => x"81", + 5273 => x"34", + 5274 => x"ec", + 5275 => x"91", + 5276 => x"56", + 5277 => x"8c", + 5278 => x"18", + 5279 => x"74", + 5280 => x"38", + 5281 => x"80", + 5282 => x"38", + 5283 => x"70", + 5284 => x"56", + 5285 => x"83", + 5286 => x"11", + 5287 => x"77", + 5288 => x"5c", + 5289 => x"38", + 5290 => x"88", + 5291 => x"8f", + 5292 => x"08", + 5293 => x"d2", + 5294 => x"93", + 5295 => x"81", + 5296 => x"f7", + 5297 => x"2e", + 5298 => x"74", + 5299 => x"98", + 5300 => x"7d", + 5301 => x"3f", + 5302 => x"08", + 5303 => x"ef", + 5304 => x"c8", + 5305 => x"89", + 5306 => x"79", + 5307 => x"d7", + 5308 => x"7e", + 5309 => x"51", + 5310 => x"76", + 5311 => x"74", + 5312 => x"79", + 5313 => x"7b", + 5314 => x"11", + 5315 => x"c7", + 5316 => x"93", + 5317 => x"c1", + 5318 => x"33", + 5319 => x"56", + 5320 => x"25", + 5321 => x"17", + 5322 => x"55", + 5323 => x"90", + 5324 => x"53", + 5325 => x"74", + 5326 => x"1c", + 5327 => x"3f", + 5328 => x"56", + 5329 => x"9c", + 5330 => x"2e", + 5331 => x"90", + 5332 => x"98", + 5333 => x"74", + 5334 => x"38", + 5335 => x"17", + 5336 => x"17", + 5337 => x"11", + 5338 => x"c8", + 5339 => x"93", + 5340 => x"ef", + 5341 => x"33", + 5342 => x"55", + 5343 => x"34", + 5344 => x"53", + 5345 => x"7d", + 5346 => x"52", + 5347 => x"3f", + 5348 => x"08", + 5349 => x"77", + 5350 => x"94", + 5351 => x"ff", + 5352 => x"71", + 5353 => x"78", + 5354 => x"38", + 5355 => x"53", + 5356 => x"83", + 5357 => x"a8", + 5358 => x"51", + 5359 => x"78", + 5360 => x"08", + 5361 => x"76", + 5362 => x"08", + 5363 => x"0c", + 5364 => x"fd", + 5365 => x"56", + 5366 => x"c8", + 5367 => x"0d", + 5368 => x"0d", + 5369 => x"63", + 5370 => x"57", + 5371 => x"8f", + 5372 => x"52", + 5373 => x"b2", + 5374 => x"c8", + 5375 => x"93", + 5376 => x"38", + 5377 => x"55", + 5378 => x"86", + 5379 => x"84", + 5380 => x"17", + 5381 => x"2a", + 5382 => x"51", + 5383 => x"56", + 5384 => x"83", + 5385 => x"39", + 5386 => x"18", + 5387 => x"83", + 5388 => x"0b", + 5389 => x"81", + 5390 => x"39", + 5391 => x"18", + 5392 => x"83", + 5393 => x"0b", + 5394 => x"82", + 5395 => x"39", + 5396 => x"18", + 5397 => x"83", + 5398 => x"0b", + 5399 => x"81", + 5400 => x"39", + 5401 => x"19", + 5402 => x"18", + 5403 => x"38", + 5404 => x"09", + 5405 => x"2e", + 5406 => x"94", + 5407 => x"83", + 5408 => x"56", + 5409 => x"38", + 5410 => x"22", + 5411 => x"89", + 5412 => x"55", + 5413 => x"38", + 5414 => x"88", + 5415 => x"74", + 5416 => x"52", + 5417 => x"b8", + 5418 => x"c8", + 5419 => x"39", + 5420 => x"52", + 5421 => x"a8", + 5422 => x"c8", + 5423 => x"80", + 5424 => x"38", + 5425 => x"fe", + 5426 => x"ff", + 5427 => x"38", + 5428 => x"0c", + 5429 => x"85", + 5430 => x"18", + 5431 => x"33", + 5432 => x"56", + 5433 => x"25", + 5434 => x"54", + 5435 => x"53", + 5436 => x"7d", + 5437 => x"52", + 5438 => x"3f", + 5439 => x"08", + 5440 => x"90", + 5441 => x"ff", + 5442 => x"90", + 5443 => x"17", + 5444 => x"51", + 5445 => x"82", + 5446 => x"80", + 5447 => x"38", + 5448 => x"08", + 5449 => x"2a", + 5450 => x"80", + 5451 => x"38", + 5452 => x"8a", + 5453 => x"56", + 5454 => x"27", + 5455 => x"7b", + 5456 => x"54", + 5457 => x"52", + 5458 => x"33", + 5459 => x"89", + 5460 => x"c8", + 5461 => x"38", + 5462 => x"78", + 5463 => x"7a", + 5464 => x"84", + 5465 => x"84", + 5466 => x"52", + 5467 => x"c8", + 5468 => x"17", + 5469 => x"06", + 5470 => x"18", + 5471 => x"2b", + 5472 => x"39", + 5473 => x"78", + 5474 => x"94", + 5475 => x"18", + 5476 => x"38", + 5477 => x"53", + 5478 => x"7d", + 5479 => x"52", + 5480 => x"3f", + 5481 => x"08", + 5482 => x"77", + 5483 => x"94", + 5484 => x"ff", + 5485 => x"71", + 5486 => x"78", + 5487 => x"38", + 5488 => x"53", + 5489 => x"17", + 5490 => x"06", + 5491 => x"51", + 5492 => x"90", + 5493 => x"80", + 5494 => x"90", + 5495 => x"76", + 5496 => x"17", + 5497 => x"1d", + 5498 => x"18", + 5499 => x"0c", + 5500 => x"58", + 5501 => x"74", + 5502 => x"38", + 5503 => x"8c", + 5504 => x"fc", + 5505 => x"17", + 5506 => x"07", + 5507 => x"18", + 5508 => x"75", + 5509 => x"0c", + 5510 => x"04", + 5511 => x"7b", + 5512 => x"05", + 5513 => x"58", + 5514 => x"82", + 5515 => x"57", + 5516 => x"08", + 5517 => x"90", + 5518 => x"86", + 5519 => x"06", + 5520 => x"74", + 5521 => x"98", + 5522 => x"2b", + 5523 => x"25", + 5524 => x"54", + 5525 => x"53", + 5526 => x"79", + 5527 => x"52", + 5528 => x"3f", + 5529 => x"93", + 5530 => x"f6", + 5531 => x"33", + 5532 => x"55", + 5533 => x"34", + 5534 => x"52", + 5535 => x"c9", + 5536 => x"c8", + 5537 => x"93", + 5538 => x"d4", + 5539 => x"08", + 5540 => x"a0", + 5541 => x"74", + 5542 => x"88", + 5543 => x"75", + 5544 => x"51", + 5545 => x"8c", + 5546 => x"9c", + 5547 => x"cb", + 5548 => x"b2", + 5549 => x"16", + 5550 => x"3f", + 5551 => x"16", + 5552 => x"3f", + 5553 => x"0b", + 5554 => x"79", + 5555 => x"3f", + 5556 => x"08", + 5557 => x"81", + 5558 => x"57", + 5559 => x"34", + 5560 => x"82", + 5561 => x"8b", + 5562 => x"fc", + 5563 => x"70", + 5564 => x"a8", + 5565 => x"c8", + 5566 => x"93", + 5567 => x"38", + 5568 => x"05", + 5569 => x"ef", + 5570 => x"93", + 5571 => x"82", + 5572 => x"87", + 5573 => x"c8", + 5574 => x"72", + 5575 => x"0c", + 5576 => x"04", + 5577 => x"85", + 5578 => x"9b", + 5579 => x"80", + 5580 => x"c8", + 5581 => x"38", + 5582 => x"08", + 5583 => x"34", + 5584 => x"82", + 5585 => x"84", + 5586 => x"ef", + 5587 => x"53", + 5588 => x"05", + 5589 => x"51", + 5590 => x"82", + 5591 => x"55", + 5592 => x"08", + 5593 => x"76", + 5594 => x"93", + 5595 => x"51", + 5596 => x"82", + 5597 => x"55", + 5598 => x"08", + 5599 => x"80", + 5600 => x"70", + 5601 => x"56", + 5602 => x"89", + 5603 => x"94", + 5604 => x"a7", + 5605 => x"05", + 5606 => x"2a", + 5607 => x"51", + 5608 => x"80", + 5609 => x"76", + 5610 => x"52", + 5611 => x"3f", + 5612 => x"08", + 5613 => x"83", + 5614 => x"74", + 5615 => x"81", + 5616 => x"85", + 5617 => x"93", + 5618 => x"3d", + 5619 => x"3d", + 5620 => x"08", + 5621 => x"5b", + 5622 => x"34", + 5623 => x"3d", + 5624 => x"52", + 5625 => x"e5", + 5626 => x"93", + 5627 => x"82", + 5628 => x"83", + 5629 => x"46", + 5630 => x"11", + 5631 => x"68", + 5632 => x"80", + 5633 => x"38", + 5634 => x"94", + 5635 => x"5b", + 5636 => x"51", + 5637 => x"82", + 5638 => x"57", + 5639 => x"08", + 5640 => x"6b", + 5641 => x"c5", + 5642 => x"93", + 5643 => x"82", + 5644 => x"81", + 5645 => x"52", + 5646 => x"ab", + 5647 => x"c8", + 5648 => x"52", + 5649 => x"b2", + 5650 => x"c8", + 5651 => x"93", + 5652 => x"ac", + 5653 => x"80", + 5654 => x"d6", + 5655 => x"93", + 5656 => x"82", + 5657 => x"a4", + 5658 => x"7e", + 5659 => x"3f", + 5660 => x"08", + 5661 => x"38", + 5662 => x"51", + 5663 => x"82", + 5664 => x"57", + 5665 => x"08", + 5666 => x"38", + 5667 => x"09", + 5668 => x"38", + 5669 => x"81", + 5670 => x"3d", + 5671 => x"53", + 5672 => x"d9", + 5673 => x"93", + 5674 => x"12", + 5675 => x"51", + 5676 => x"56", + 5677 => x"8e", + 5678 => x"70", + 5679 => x"33", + 5680 => x"73", + 5681 => x"16", + 5682 => x"27", + 5683 => x"57", + 5684 => x"80", + 5685 => x"7d", + 5686 => x"a3", + 5687 => x"ff", + 5688 => x"57", + 5689 => x"81", + 5690 => x"34", + 5691 => x"ff", + 5692 => x"08", + 5693 => x"af", + 5694 => x"55", + 5695 => x"38", + 5696 => x"38", + 5697 => x"09", + 5698 => x"38", + 5699 => x"3d", + 5700 => x"59", + 5701 => x"80", + 5702 => x"f8", + 5703 => x"10", + 5704 => x"05", + 5705 => x"33", + 5706 => x"57", + 5707 => x"78", + 5708 => x"81", + 5709 => x"70", + 5710 => x"56", + 5711 => x"82", + 5712 => x"79", + 5713 => x"80", + 5714 => x"27", + 5715 => x"15", + 5716 => x"7a", + 5717 => x"5c", + 5718 => x"58", + 5719 => x"ee", + 5720 => x"70", + 5721 => x"34", + 5722 => x"77", + 5723 => x"57", + 5724 => x"a2", + 5725 => x"81", + 5726 => x"73", + 5727 => x"81", + 5728 => x"7b", + 5729 => x"38", + 5730 => x"76", + 5731 => x"0c", + 5732 => x"04", + 5733 => x"7e", + 5734 => x"fc", + 5735 => x"53", + 5736 => x"86", + 5737 => x"c8", + 5738 => x"93", + 5739 => x"38", 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x"38", + 5799 => x"51", + 5800 => x"82", + 5801 => x"56", + 5802 => x"08", + 5803 => x"93", + 5804 => x"b5", + 5805 => x"76", + 5806 => x"3f", + 5807 => x"08", + 5808 => x"2e", + 5809 => x"81", + 5810 => x"38", + 5811 => x"15", + 5812 => x"8b", + 5813 => x"91", + 5814 => x"55", + 5815 => x"75", + 5816 => x"77", + 5817 => x"98", + 5818 => x"08", + 5819 => x"0c", + 5820 => x"06", + 5821 => x"2e", + 5822 => x"52", + 5823 => x"bf", + 5824 => x"c8", + 5825 => x"82", + 5826 => x"34", + 5827 => x"a6", + 5828 => x"2a", + 5829 => x"08", + 5830 => x"17", + 5831 => x"08", + 5832 => x"94", + 5833 => x"18", + 5834 => x"33", + 5835 => x"55", + 5836 => x"34", + 5837 => x"83", + 5838 => x"74", + 5839 => x"f4", + 5840 => x"08", + 5841 => x"ec", + 5842 => x"33", + 5843 => x"56", + 5844 => x"25", + 5845 => x"54", + 5846 => x"53", + 5847 => x"7c", + 5848 => x"52", + 5849 => x"f1", + 5850 => x"c8", + 5851 => x"8a", + 5852 => x"91", + 5853 => x"55", + 5854 => x"17", + 5855 => x"06", + 5856 => x"18", + 5857 => x"7a", + 5858 => x"52", + 5859 => x"33", + 5860 => x"b6", + 5861 => x"93", + 5862 => x"2e", + 5863 => x"0b", + 5864 => x"81", + 5865 => x"81", + 5866 => x"34", + 5867 => x"39", + 5868 => x"0c", + 5869 => x"82", + 5870 => x"8e", + 5871 => x"f9", + 5872 => x"56", + 5873 => x"80", + 5874 => x"38", + 5875 => x"3d", + 5876 => x"8a", + 5877 => x"51", + 5878 => x"82", + 5879 => x"55", + 5880 => x"08", + 5881 => x"77", + 5882 => x"52", + 5883 => x"9e", + 5884 => x"c8", + 5885 => x"93", + 5886 => x"ca", + 5887 => x"33", + 5888 => x"55", + 5889 => x"24", + 5890 => x"16", + 5891 => x"2a", + 5892 => x"51", + 5893 => x"80", + 5894 => x"9c", + 5895 => x"77", + 5896 => x"3f", + 5897 => x"08", + 5898 => x"83", + 5899 => x"74", + 5900 => x"54", + 5901 => x"84", + 5902 => x"52", + 5903 => x"ba", + 5904 => x"c8", + 5905 => x"84", + 5906 => x"06", + 5907 => x"55", + 5908 => x"84", + 5909 => x"0c", + 5910 => x"82", + 5911 => x"89", + 5912 => x"fc", + 5913 => x"87", + 5914 => x"53", + 5915 => x"e4", + 5916 => x"93", + 5917 => x"82", + 5918 => x"87", + 5919 => x"c8", + 5920 => x"72", + 5921 => x"0c", + 5922 => x"04", + 5923 => x"77", + 5924 => x"fc", + 5925 => x"53", + 5926 => x"8e", + 5927 => x"c8", + 5928 => x"93", + 5929 => x"d1", + 5930 => x"38", + 5931 => x"08", + 5932 => x"c8", + 5933 => x"93", + 5934 => x"bd", + 5935 => x"73", + 5936 => x"3f", + 5937 => x"08", + 5938 => x"c8", + 5939 => x"09", + 5940 => x"38", + 5941 => x"a1", + 5942 => x"73", + 5943 => x"3f", + 5944 => x"51", + 5945 => x"82", + 5946 => x"53", + 5947 => x"08", + 5948 => x"81", + 5949 => x"80", + 5950 => x"93", + 5951 => x"3d", + 5952 => x"3d", + 5953 => x"80", + 5954 => x"70", + 5955 => x"52", + 5956 => x"3f", + 5957 => x"08", + 5958 => x"c8", + 5959 => x"63", + 5960 => x"d5", + 5961 => x"93", + 5962 => x"82", + 5963 => x"a3", + 5964 => x"c7", + 5965 => x"98", + 5966 => x"73", + 5967 => x"38", + 5968 => x"39", + 5969 => x"8b", + 5970 => x"93", + 5971 => x"51", + 5972 => x"74", + 5973 => x"0c", + 5974 => x"04", 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x"ff", + 6034 => x"82", + 6035 => x"f0", + 6036 => x"30", + 6037 => x"19", + 6038 => x"59", + 6039 => x"83", + 6040 => x"17", + 6041 => x"ff", + 6042 => x"7a", + 6043 => x"90", + 6044 => x"7a", + 6045 => x"81", + 6046 => x"73", + 6047 => x"78", + 6048 => x"0c", + 6049 => x"04", + 6050 => x"7a", + 6051 => x"05", + 6052 => x"58", + 6053 => x"82", + 6054 => x"57", + 6055 => x"08", + 6056 => x"18", + 6057 => x"80", + 6058 => x"76", + 6059 => x"39", + 6060 => x"70", + 6061 => x"81", + 6062 => x"56", + 6063 => x"80", + 6064 => x"38", + 6065 => x"8c", + 6066 => x"81", + 6067 => x"18", + 6068 => x"80", + 6069 => x"08", + 6070 => x"ff", + 6071 => x"82", + 6072 => x"57", + 6073 => x"19", + 6074 => x"39", + 6075 => x"52", + 6076 => x"b9", + 6077 => x"93", + 6078 => x"93", + 6079 => x"32", + 6080 => x"72", + 6081 => x"52", + 6082 => x"82", + 6083 => x"81", + 6084 => x"06", + 6085 => x"57", + 6086 => x"78", + 6087 => x"16", + 6088 => x"38", + 6089 => x"53", + 6090 => x"51", + 6091 => x"3f", + 6092 => x"08", + 6093 => x"08", + 6094 => x"90", + 6095 => x"c0", + 6096 => x"90", + 6097 => x"b9", + 6098 => x"2b", + 6099 => x"25", + 6100 => x"54", + 6101 => x"53", + 6102 => x"78", + 6103 => x"52", + 6104 => x"f5", + 6105 => x"c8", + 6106 => x"85", + 6107 => x"8c", + 6108 => x"33", + 6109 => x"55", + 6110 => x"34", + 6111 => x"89", + 6112 => x"19", + 6113 => x"83", + 6114 => x"75", + 6115 => x"0c", + 6116 => x"04", + 6117 => x"81", + 6118 => x"ff", + 6119 => x"82", + 6120 => x"ff", + 6121 => x"a0", + 6122 => x"b2", + 6123 => x"c8", + 6124 => x"93", + 6125 => x"d3", + 6126 => x"90", + 6127 => x"b3", + 6128 => x"6f", + 6129 => x"d4", + 6130 => x"c2", + 6131 => x"c8", + 6132 => x"94", + 6133 => x"96", + 6134 => x"82", + 6135 => x"80", + 6136 => x"70", + 6137 => x"81", + 6138 => x"55", + 6139 => x"83", + 6140 => x"75", + 6141 => x"81", + 6142 => x"ff", + 6143 => x"02", + 6144 => x"33", + 6145 => x"55", + 6146 => x"25", + 6147 => x"56", + 6148 => x"80", + 6149 => x"81", + 6150 => x"80", + 6151 => x"87", + 6152 => x"e7", + 6153 => x"77", + 6154 => x"3f", + 6155 => x"08", + 6156 => x"80", + 6157 => x"70", + 6158 => x"81", + 6159 => x"56", + 6160 => x"2e", + 6161 => x"81", + 6162 => x"ff", + 6163 => x"87", + 6164 => x"94", + 6165 => x"2e", + 6166 => x"81", + 6167 => x"ff", + 6168 => x"77", + 6169 => x"81", + 6170 => x"ff", + 6171 => x"80", + 6172 => x"70", + 6173 => x"82", + 6174 => x"c8", + 6175 => x"93", + 6176 => x"87", + 6177 => x"c8", + 6178 => x"51", + 6179 => x"82", + 6180 => x"56", + 6181 => x"08", + 6182 => x"56", + 6183 => x"70", + 6184 => x"07", + 6185 => x"06", + 6186 => x"75", + 6187 => x"81", + 6188 => x"ff", + 6189 => x"9f", + 6190 => x"51", + 6191 => x"82", + 6192 => x"82", + 6193 => x"30", + 6194 => x"c8", + 6195 => x"25", + 6196 => x"7b", + 6197 => x"72", + 6198 => x"51", + 6199 => x"80", + 6200 => x"81", + 6201 => x"ff", + 6202 => x"80", + 6203 => x"9f", + 6204 => x"51", + 6205 => x"3f", + 6206 => x"08", + 6207 => x"38", + 6208 => x"b4", + 6209 => x"93", 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x"51", + 6269 => x"a0", + 6270 => x"52", + 6271 => x"51", + 6272 => x"3f", + 6273 => x"0b", + 6274 => x"34", + 6275 => x"d4", + 6276 => x"51", + 6277 => x"77", + 6278 => x"83", + 6279 => x"3d", + 6280 => x"c5", + 6281 => x"93", + 6282 => x"82", + 6283 => x"af", + 6284 => x"63", + 6285 => x"ff", + 6286 => x"75", + 6287 => x"77", + 6288 => x"3f", + 6289 => x"0b", + 6290 => x"77", + 6291 => x"83", + 6292 => x"51", + 6293 => x"3f", + 6294 => x"08", + 6295 => x"80", + 6296 => x"98", + 6297 => x"51", + 6298 => x"3f", + 6299 => x"c8", + 6300 => x"0d", + 6301 => x"0d", + 6302 => x"05", + 6303 => x"3f", + 6304 => x"3d", + 6305 => x"52", + 6306 => x"d0", + 6307 => x"93", + 6308 => x"82", + 6309 => x"82", + 6310 => x"4c", + 6311 => x"52", + 6312 => x"05", + 6313 => x"3f", + 6314 => x"08", + 6315 => x"c8", + 6316 => x"38", + 6317 => x"05", + 6318 => x"06", + 6319 => x"2e", + 6320 => x"55", + 6321 => x"38", + 6322 => x"3d", + 6323 => x"3d", + 6324 => x"51", + 6325 => x"3f", + 6326 => x"3d", + 6327 => x"91", + 6328 => x"54", + 6329 => x"3f", + 6330 => x"52", + 6331 => x"9e", + 6332 => x"c8", + 6333 => x"93", + 6334 => x"38", + 6335 => x"09", + 6336 => x"38", + 6337 => x"a1", + 6338 => x"83", + 6339 => x"74", + 6340 => x"81", + 6341 => x"38", + 6342 => x"a8", + 6343 => x"ec", + 6344 => x"c8", + 6345 => x"93", + 6346 => x"c4", + 6347 => x"93", + 6348 => x"ff", + 6349 => x"8d", + 6350 => x"ac", + 6351 => x"ab", + 6352 => x"17", + 6353 => x"33", + 6354 => x"70", + 6355 => x"55", + 6356 => x"38", + 6357 => x"54", + 6358 => x"34", + 6359 => x"0b", + 6360 => x"8b", + 6361 => x"84", + 6362 => x"06", + 6363 => x"73", + 6364 => x"db", + 6365 => x"2e", + 6366 => x"75", + 6367 => x"ff", + 6368 => x"82", + 6369 => x"52", + 6370 => x"b0", + 6371 => x"55", + 6372 => x"08", + 6373 => x"38", + 6374 => x"08", + 6375 => x"ff", + 6376 => x"82", + 6377 => x"80", + 6378 => x"55", + 6379 => x"08", + 6380 => x"16", + 6381 => x"ae", + 6382 => x"06", + 6383 => x"53", + 6384 => x"51", + 6385 => x"3f", + 6386 => x"0b", + 6387 => x"74", + 6388 => x"3d", + 6389 => x"c3", + 6390 => x"93", + 6391 => x"82", + 6392 => x"8c", + 6393 => x"ff", + 6394 => x"82", + 6395 => x"55", + 6396 => x"c8", + 6397 => x"0d", + 6398 => x"0d", + 6399 => x"05", + 6400 => x"05", + 6401 => x"33", + 6402 => x"53", + 6403 => x"05", + 6404 => x"51", + 6405 => x"82", + 6406 => x"55", + 6407 => x"08", + 6408 => x"78", + 6409 => x"95", + 6410 => x"51", + 6411 => x"82", + 6412 => x"55", + 6413 => x"08", + 6414 => x"80", + 6415 => x"81", + 6416 => x"73", + 6417 => x"38", + 6418 => x"aa", + 6419 => x"06", + 6420 => x"8b", + 6421 => x"06", + 6422 => x"07", + 6423 => x"56", + 6424 => x"34", + 6425 => x"0b", + 6426 => x"78", + 6427 => x"a0", + 6428 => x"c8", + 6429 => x"82", + 6430 => x"95", + 6431 => x"ee", + 6432 => x"56", + 6433 => x"3d", + 6434 => x"95", + 6435 => x"ce", + 6436 => x"c8", + 6437 => x"93", + 6438 => x"d3", + 6439 => x"64", + 6440 => x"d4", + 6441 => x"e6", + 6442 => x"c8", + 6443 => x"93", + 6444 => x"38", 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x"86", + 6504 => x"34", + 6505 => x"30", + 6506 => x"80", + 6507 => x"70", + 6508 => x"2a", + 6509 => x"56", + 6510 => x"80", + 6511 => x"7b", + 6512 => x"53", + 6513 => x"81", + 6514 => x"c8", + 6515 => x"93", + 6516 => x"38", + 6517 => x"51", + 6518 => x"58", + 6519 => x"8b", + 6520 => x"58", + 6521 => x"83", + 6522 => x"7b", + 6523 => x"51", + 6524 => x"3f", + 6525 => x"08", + 6526 => x"82", + 6527 => x"98", + 6528 => x"e8", + 6529 => x"53", + 6530 => x"b8", + 6531 => x"3d", + 6532 => x"3f", + 6533 => x"08", + 6534 => x"c8", + 6535 => x"38", + 6536 => x"52", + 6537 => x"bc", + 6538 => x"a7", + 6539 => x"6b", + 6540 => x"52", + 6541 => x"9f", + 6542 => x"b5", + 6543 => x"6b", + 6544 => x"70", + 6545 => x"52", + 6546 => x"fe", + 6547 => x"c8", + 6548 => x"a2", + 6549 => x"33", + 6550 => x"54", + 6551 => x"3f", + 6552 => x"08", + 6553 => x"38", + 6554 => x"74", + 6555 => x"05", + 6556 => x"39", + 6557 => x"9f", + 6558 => x"99", + 6559 => x"e0", + 6560 => x"ff", + 6561 => x"54", + 6562 => x"27", + 6563 => x"fa", + 6564 => x"56", + 6565 => x"a3", + 6566 => x"81", + 6567 => x"ff", + 6568 => x"82", + 6569 => x"93", + 6570 => x"76", + 6571 => x"76", + 6572 => x"38", + 6573 => x"77", + 6574 => x"86", + 6575 => x"39", + 6576 => x"27", + 6577 => x"3d", + 6578 => x"bc", + 6579 => x"2a", + 6580 => x"75", + 6581 => x"57", + 6582 => x"05", + 6583 => x"54", + 6584 => x"81", + 6585 => x"33", + 6586 => x"73", + 6587 => x"cd", + 6588 => x"33", + 6589 => x"73", + 6590 => x"81", + 6591 => x"80", + 6592 => x"02", + 6593 => x"78", + 6594 => x"51", + 6595 => x"73", + 6596 => x"81", + 6597 => x"ff", + 6598 => x"80", + 6599 => x"76", + 6600 => x"51", + 6601 => x"2e", + 6602 => x"5f", + 6603 => x"52", + 6604 => x"52", + 6605 => x"c2", + 6606 => x"c8", + 6607 => x"93", + 6608 => x"a1", + 6609 => x"74", + 6610 => x"82", + 6611 => x"c8", + 6612 => x"93", + 6613 => x"38", + 6614 => x"91", + 6615 => x"9a", + 6616 => x"05", + 6617 => x"ff", + 6618 => x"86", + 6619 => x"e5", + 6620 => x"54", + 6621 => x"15", + 6622 => x"ff", + 6623 => x"82", + 6624 => x"54", + 6625 => x"82", + 6626 => x"84", + 6627 => x"06", + 6628 => x"80", + 6629 => x"2e", + 6630 => x"81", + 6631 => x"d4", + 6632 => x"b6", + 6633 => x"93", + 6634 => x"82", + 6635 => x"b5", + 6636 => x"82", + 6637 => x"52", + 6638 => x"a4", + 6639 => x"54", + 6640 => x"15", + 6641 => x"9a", + 6642 => x"05", + 6643 => x"ff", + 6644 => x"77", + 6645 => x"83", + 6646 => x"51", + 6647 => x"3f", + 6648 => x"08", + 6649 => x"74", + 6650 => x"0c", + 6651 => x"04", + 6652 => x"61", + 6653 => x"05", + 6654 => x"33", + 6655 => x"05", + 6656 => x"5e", + 6657 => x"a2", + 6658 => x"c8", + 6659 => x"93", + 6660 => x"38", + 6661 => x"57", + 6662 => x"86", + 6663 => x"82", + 6664 => x"80", + 6665 => x"8c", + 6666 => x"38", + 6667 => x"70", + 6668 => x"81", + 6669 => x"55", + 6670 => x"87", + 6671 => x"39", + 6672 => x"89", + 6673 => x"81", + 6674 => x"8a", + 6675 => x"89", + 6676 => x"7d", + 6677 => x"54", + 6678 => x"3f", + 6679 => x"06", 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x"84", + 6739 => x"07", + 6740 => x"84", + 6741 => x"54", + 6742 => x"c8", + 6743 => x"0d", + 6744 => x"0d", + 6745 => x"05", + 6746 => x"33", + 6747 => x"5e", + 6748 => x"d3", + 6749 => x"c8", + 6750 => x"57", + 6751 => x"93", + 6752 => x"8c", + 6753 => x"93", + 6754 => x"10", + 6755 => x"05", + 6756 => x"80", + 6757 => x"74", + 6758 => x"75", + 6759 => x"ff", + 6760 => x"52", + 6761 => x"99", + 6762 => x"93", + 6763 => x"ff", + 6764 => x"06", + 6765 => x"57", + 6766 => x"38", + 6767 => x"70", + 6768 => x"55", + 6769 => x"8c", + 6770 => x"3d", + 6771 => x"83", + 6772 => x"ff", + 6773 => x"82", + 6774 => x"98", + 6775 => x"2e", + 6776 => x"82", + 6777 => x"8c", + 6778 => x"05", + 6779 => x"74", + 6780 => x"38", + 6781 => x"80", + 6782 => x"2e", + 6783 => x"78", + 6784 => x"77", + 6785 => x"26", + 6786 => x"18", + 6787 => x"74", + 6788 => x"38", + 6789 => x"be", + 6790 => x"77", + 6791 => x"98", + 6792 => x"c8", + 6793 => x"54", + 6794 => x"58", + 6795 => x"3f", + 6796 => x"08", + 6797 => x"c8", + 6798 => x"30", + 6799 => x"80", + 6800 => x"c8", + 6801 => x"82", + 6802 => x"07", + 6803 => x"07", + 6804 => x"58", + 6805 => x"57", + 6806 => x"38", + 6807 => x"05", + 6808 => x"79", + 6809 => x"cb", + 6810 => x"82", + 6811 => x"8a", + 6812 => x"83", + 6813 => x"06", + 6814 => x"44", + 6815 => x"09", + 6816 => x"38", + 6817 => x"57", + 6818 => x"8a", + 6819 => x"64", + 6820 => x"57", + 6821 => x"27", + 6822 => x"93", + 6823 => x"80", + 6824 => x"38", + 6825 => x"70", + 6826 => x"55", + 6827 => x"95", + 6828 => x"06", + 6829 => x"2e", + 6830 => x"81", + 6831 => x"85", + 6832 => x"8f", + 6833 => x"06", + 6834 => x"82", + 6835 => x"2e", + 6836 => x"77", + 6837 => x"2e", + 6838 => x"80", + 6839 => x"b4", + 6840 => x"2a", + 6841 => x"81", + 6842 => x"9c", + 6843 => x"52", + 6844 => x"74", + 6845 => x"38", + 6846 => x"98", + 6847 => x"79", + 6848 => x"18", + 6849 => x"57", + 6850 => x"80", + 6851 => x"76", + 6852 => x"38", + 6853 => x"51", + 6854 => x"3f", + 6855 => x"08", + 6856 => x"08", + 6857 => x"7f", + 6858 => x"52", + 6859 => x"88", + 6860 => x"c8", + 6861 => x"5b", + 6862 => x"80", + 6863 => x"43", + 6864 => x"0a", + 6865 => x"8b", + 6866 => x"89", + 6867 => x"b4", + 6868 => x"2a", + 6869 => x"81", + 6870 => x"8c", + 6871 => x"52", + 6872 => x"74", + 6873 => x"38", + 6874 => x"98", + 6875 => x"79", + 6876 => x"18", + 6877 => x"57", + 6878 => x"80", + 6879 => x"76", + 6880 => x"38", + 6881 => x"51", + 6882 => x"3f", + 6883 => x"08", + 6884 => x"57", + 6885 => x"08", + 6886 => x"92", + 6887 => x"82", + 6888 => x"83", + 6889 => x"72", + 6890 => x"51", + 6891 => x"52", + 6892 => x"05", + 6893 => x"80", + 6894 => x"c8", + 6895 => x"7e", + 6896 => x"80", + 6897 => x"f2", + 6898 => x"93", + 6899 => x"ff", + 6900 => x"63", + 6901 => x"64", + 6902 => x"ff", + 6903 => x"70", + 6904 => x"31", + 6905 => x"57", + 6906 => x"2e", + 6907 => x"89", + 6908 => x"60", + 6909 => x"84", + 6910 => x"5c", + 6911 => x"16", + 6912 => x"51", + 6913 => x"26", + 6914 => x"65", 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x"54", + 6974 => x"1f", + 6975 => x"dd", + 6976 => x"ff", + 6977 => x"38", + 6978 => x"05", + 6979 => x"1f", + 6980 => x"c9", + 6981 => x"65", + 6982 => x"51", + 6983 => x"3f", + 6984 => x"05", + 6985 => x"98", + 6986 => x"98", + 6987 => x"ff", + 6988 => x"51", + 6989 => x"3f", + 6990 => x"1f", + 6991 => x"bb", + 6992 => x"2e", + 6993 => x"80", + 6994 => x"88", + 6995 => x"80", + 6996 => x"ff", + 6997 => x"7b", + 6998 => x"51", + 6999 => x"3f", + 7000 => x"1f", + 7001 => x"93", + 7002 => x"b0", + 7003 => x"97", + 7004 => x"52", + 7005 => x"ff", + 7006 => x"ff", + 7007 => x"c0", + 7008 => x"7f", + 7009 => x"34", + 7010 => x"fb", + 7011 => x"c7", + 7012 => x"98", + 7013 => x"39", + 7014 => x"0a", + 7015 => x"51", + 7016 => x"3f", + 7017 => x"ff", + 7018 => x"1f", + 7019 => x"ad", + 7020 => x"7f", + 7021 => x"a9", + 7022 => x"34", + 7023 => x"fb", + 7024 => x"1f", + 7025 => x"e2", + 7026 => x"d5", + 7027 => x"1f", + 7028 => x"89", + 7029 => x"63", + 7030 => x"79", + 7031 => x"f9", + 7032 => x"82", + 7033 => x"83", + 7034 => x"83", + 7035 => x"06", + 7036 => x"81", + 7037 => x"05", + 7038 => x"79", + 7039 => x"d9", + 7040 => x"80", + 7041 => x"ff", + 7042 => x"84", + 7043 => x"d2", + 7044 => x"ff", + 7045 => x"86", + 7046 => x"f2", + 7047 => x"1f", + 7048 => x"d7", + 7049 => x"52", + 7050 => x"51", + 7051 => x"3f", + 7052 => x"ec", + 7053 => x"96", + 7054 => x"d4", + 7055 => x"fe", + 7056 => x"96", + 7057 => x"54", + 7058 => x"53", + 7059 => x"51", + 7060 => x"3f", + 7061 => x"81", + 7062 => x"52", + 7063 => x"92", + 7064 => x"53", + 7065 => x"51", + 7066 => x"3f", + 7067 => x"5b", + 7068 => x"09", + 7069 => x"38", + 7070 => x"51", + 7071 => x"3f", + 7072 => x"1f", + 7073 => x"f3", + 7074 => x"52", + 7075 => x"ff", + 7076 => x"95", + 7077 => x"ff", + 7078 => x"81", + 7079 => x"f8", + 7080 => x"7e", + 7081 => x"d3", + 7082 => x"60", + 7083 => x"26", + 7084 => x"57", + 7085 => x"53", + 7086 => x"51", + 7087 => x"3f", + 7088 => x"08", + 7089 => x"7d", + 7090 => x"7e", + 7091 => x"fe", + 7092 => x"75", + 7093 => x"56", + 7094 => x"81", + 7095 => x"80", + 7096 => x"38", + 7097 => x"83", + 7098 => x"62", + 7099 => x"74", + 7100 => x"38", + 7101 => x"54", + 7102 => x"52", + 7103 => x"91", + 7104 => x"93", + 7105 => x"c8", + 7106 => x"75", + 7107 => x"56", + 7108 => x"8c", + 7109 => x"2e", + 7110 => x"57", + 7111 => x"ff", + 7112 => x"84", + 7113 => x"2e", + 7114 => x"57", + 7115 => x"81", + 7116 => x"80", + 7117 => x"53", + 7118 => x"51", + 7119 => x"3f", + 7120 => x"52", + 7121 => x"51", + 7122 => x"3f", + 7123 => x"56", + 7124 => x"81", + 7125 => x"34", + 7126 => x"17", + 7127 => x"17", + 7128 => x"17", + 7129 => x"05", + 7130 => x"c1", + 7131 => x"fe", + 7132 => x"fe", + 7133 => x"34", + 7134 => x"08", + 7135 => x"07", + 7136 => x"17", + 7137 => x"c8", + 7138 => x"34", + 7139 => x"c6", + 7140 => x"93", + 7141 => x"52", + 7142 => x"51", + 7143 => x"3f", + 7144 => x"53", + 7145 => x"51", + 7146 => x"3f", + 7147 => x"93", + 7148 => x"38", + 7149 => x"52", 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x"82", + 7209 => x"fe", + 7210 => x"a7", + 7211 => x"f4", + 7212 => x"f1", + 7213 => x"82", + 7214 => x"fe", + 7215 => x"93", + 7216 => x"a4", + 7217 => x"dd", + 7218 => x"82", + 7219 => x"fe", + 7220 => x"83", + 7221 => x"fb", + 7222 => x"79", + 7223 => x"87", + 7224 => x"38", + 7225 => x"87", + 7226 => x"fe", + 7227 => x"82", + 7228 => x"55", + 7229 => x"e8", + 7230 => x"fe", + 7231 => x"82", + 7232 => x"52", + 7233 => x"e8", + 7234 => x"93", + 7235 => x"74", + 7236 => x"75", + 7237 => x"c0", + 7238 => x"83", + 7239 => x"0d", + 7240 => x"3d", + 7241 => x"3d", + 7242 => x"3d", + 7243 => x"05", + 7244 => x"33", + 7245 => x"70", + 7246 => x"25", + 7247 => x"27", + 7248 => x"5a", + 7249 => x"93", + 7250 => x"87", + 7251 => x"77", + 7252 => x"3d", + 7253 => x"51", + 7254 => x"3f", + 7255 => x"08", + 7256 => x"c8", + 7257 => x"82", + 7258 => x"87", + 7259 => x"0c", + 7260 => x"08", + 7261 => x"3d", + 7262 => x"55", + 7263 => x"53", + 7264 => x"d8", + 7265 => x"f2", + 7266 => x"c8", + 7267 => x"93", + 7268 => x"38", + 7269 => x"89", + 7270 => x"7b", + 7271 => x"d5", + 7272 => x"3d", + 7273 => x"51", + 7274 => x"77", + 7275 => x"07", + 7276 => x"30", + 7277 => x"72", + 7278 => x"51", + 7279 => x"2e", + 7280 => x"85", + 7281 => x"c0", + 7282 => x"52", + 7283 => x"87", + 7284 => x"74", + 7285 => x"0c", + 7286 => x"0d", + 7287 => x"0d", + 7288 => x"33", + 7289 => x"57", + 7290 => x"7b", + 7291 => x"fe", + 7292 => x"93", + 7293 => x"38", + 7294 => x"88", + 7295 => x"2e", + 7296 => x"39", + 7297 => x"54", + 7298 => x"53", + 7299 => x"51", + 7300 => x"93", + 7301 => x"83", + 7302 => x"78", + 7303 => x"0c", + 7304 => x"04", + 7305 => x"02", + 7306 => x"82", + 7307 => x"82", + 7308 => x"56", + 7309 => x"3f", + 7310 => x"70", + 7311 => x"fe", + 7312 => x"82", + 7313 => x"82", + 7314 => x"81", + 7315 => x"82", + 7316 => x"ff", + 7317 => x"75", + 7318 => x"38", + 7319 => x"3f", + 7320 => x"04", + 7321 => x"87", + 7322 => x"08", + 7323 => x"ff", + 7324 => x"fe", + 7325 => x"82", + 7326 => x"fe", + 7327 => x"80", + 7328 => x"f1", + 7329 => x"2a", + 7330 => x"51", + 7331 => x"2e", + 7332 => x"51", + 7333 => x"3f", + 7334 => x"51", + 7335 => x"3f", + 7336 => x"ee", + 7337 => x"82", + 7338 => x"06", + 7339 => x"80", + 7340 => x"81", + 7341 => x"bd", + 7342 => x"e0", + 7343 => x"b3", + 7344 => x"fe", + 7345 => x"72", + 7346 => x"81", + 7347 => x"71", + 7348 => x"38", + 7349 => x"ee", + 7350 => x"86", + 7351 => x"f0", + 7352 => x"51", + 7353 => x"3f", + 7354 => x"70", + 7355 => x"52", + 7356 => x"95", + 7357 => x"fe", + 7358 => x"82", + 7359 => x"fe", + 7360 => x"80", + 7361 => x"ed", + 7362 => x"2a", + 7363 => x"51", + 7364 => x"2e", + 7365 => x"51", + 7366 => x"3f", + 7367 => x"51", + 7368 => x"3f", + 7369 => x"ed", + 7370 => x"86", + 7371 => x"06", + 7372 => x"80", + 7373 => x"81", + 7374 => x"b9", + 7375 => x"ac", + 7376 => x"af", + 7377 => x"fe", + 7378 => x"72", + 7379 => x"81", + 7380 => x"71", + 7381 => x"38", + 7382 => x"ed", + 7383 => x"87", + 7384 => x"ef", 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x"7b", + 7444 => x"ea", + 7445 => x"ff", + 7446 => x"82", + 7447 => x"5a", + 7448 => x"8b", + 7449 => x"98", + 7450 => x"b3", + 7451 => x"81", + 7452 => x"82", + 7453 => x"fe", + 7454 => x"96", + 7455 => x"59", + 7456 => x"54", + 7457 => x"78", + 7458 => x"a4", + 7459 => x"61", + 7460 => x"e5", + 7461 => x"fe", + 7462 => x"fd", + 7463 => x"93", + 7464 => x"2b", + 7465 => x"51", + 7466 => x"87", + 7467 => x"38", + 7468 => x"81", + 7469 => x"59", + 7470 => x"b4", + 7471 => x"11", + 7472 => x"05", + 7473 => x"e2", + 7474 => x"c8", + 7475 => x"82", + 7476 => x"fe", + 7477 => x"ff", + 7478 => x"3d", + 7479 => x"53", + 7480 => x"51", + 7481 => x"3f", + 7482 => x"08", + 7483 => x"38", + 7484 => x"83", + 7485 => x"02", + 7486 => x"52", + 7487 => x"05", + 7488 => x"82", + 7489 => x"93", + 7490 => x"ff", + 7491 => x"8e", + 7492 => x"e4", + 7493 => x"8d", + 7494 => x"fe", + 7495 => x"88", + 7496 => x"f6", + 7497 => x"cb", + 7498 => x"fe", + 7499 => x"fe", + 7500 => x"fe", + 7501 => x"82", + 7502 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=> x"73", + 8208 => x"00", + 8209 => x"64", + 8210 => x"00", + 8211 => x"63", + 8212 => x"64", + 8213 => x"65", + 8214 => x"73", + 8215 => x"64", + 8216 => x"00", + 8217 => x"6c", + 8218 => x"6c", + 8219 => x"6d", + 8220 => x"00", + 8221 => x"63", + 8222 => x"00", + 8223 => x"64", + 8224 => x"00", + 8225 => x"65", + 8226 => x"65", + 8227 => x"65", + 8228 => x"69", + 8229 => x"69", + 8230 => x"72", + 8231 => x"74", + 8232 => x"66", + 8233 => x"66", + 8234 => x"68", + 8235 => x"00", + 8236 => x"6f", + 8237 => x"61", + 8238 => x"00", + 8239 => x"61", + 8240 => x"00", + 8241 => x"6d", + 8242 => x"65", + 8243 => x"72", + 8244 => x"65", + 8245 => x"00", + 8246 => x"65", + 8247 => x"00", + 8248 => x"6e", + 8249 => x"00", + 8250 => x"69", + 8251 => x"00", + 8252 => x"65", + 8253 => x"00", + 8254 => x"69", + 8255 => x"45", + 8256 => x"72", + 8257 => x"6e", + 8258 => x"6e", + 8259 => x"65", + 8260 => x"72", + 8261 => x"00", + 8262 => x"69", + 8263 => x"6e", + 8264 => x"72", + 8265 => x"79", + 8266 => x"00", + 8267 => x"6f", + 8268 => x"6c", + 8269 => x"6f", + 8270 => x"2e", + 8271 => x"6f", + 8272 => x"74", + 8273 => x"6f", + 8274 => x"2e", + 8275 => x"6e", + 8276 => x"69", + 8277 => x"69", + 8278 => x"61", + 8279 => x"0a", + 8280 => x"63", + 8281 => x"73", + 8282 => x"6e", + 8283 => x"2e", + 8284 => x"69", + 8285 => x"61", + 8286 => x"61", + 8287 => x"65", + 8288 => x"74", + 8289 => x"00", + 8290 => x"69", + 8291 => x"68", + 8292 => x"6c", + 8293 => x"6e", + 8294 => x"69", + 8295 => x"00", + 8296 => x"44", + 8297 => x"20", + 8298 => x"74", + 8299 => x"72", + 8300 => x"63", + 8301 => x"2e", + 8302 => x"72", + 8303 => x"20", + 8304 => x"62", + 8305 => x"69", + 8306 => x"6e", + 8307 => x"69", + 8308 => x"00", + 8309 => x"69", + 8310 => x"6e", + 8311 => x"65", + 8312 => x"6c", + 8313 => x"0a", + 8314 => x"6f", + 8315 => x"6d", + 8316 => x"69", + 8317 => x"20", + 8318 => x"65", + 8319 => x"74", + 8320 => x"66", + 8321 => x"64", + 8322 => x"20", + 8323 => x"6b", + 8324 => x"00", + 8325 => x"6f", + 8326 => x"74", + 8327 => x"6f", + 8328 => x"64", + 8329 => x"00", + 8330 => x"69", + 8331 => x"75", + 8332 => x"6f", + 8333 => x"61", + 8334 => x"6e", + 8335 => x"6e", + 8336 => x"6c", + 8337 => x"0a", + 8338 => x"69", + 8339 => x"69", + 8340 => x"6f", + 8341 => x"64", + 8342 => x"00", + 8343 => x"6e", + 8344 => x"66", + 8345 => x"65", + 8346 => x"6d", + 8347 => x"72", + 8348 => x"00", + 8349 => x"6f", + 8350 => x"61", + 8351 => x"6f", + 8352 => x"20", + 8353 => x"65", + 8354 => x"00", + 8355 => x"61", + 8356 => x"65", + 8357 => x"73", + 8358 => x"63", + 8359 => x"65", + 8360 => x"0a", + 8361 => x"75", + 8362 => x"73", + 8363 => x"00", + 8364 => x"6e", + 8365 => x"77", + 8366 => x"72", + 8367 => x"2e", + 8368 => x"25", + 8369 => x"62", + 8370 => x"73", + 8371 => x"20", + 8372 => x"25", + 8373 => x"62", + 8374 => x"73", + 8375 => x"63", + 8376 => x"00", + 8377 => x"65", + 8378 => x"00", + 8379 => x"50", + 8380 => x"00", + 8381 => x"2a", + 8382 => x"73", + 8383 => x"00", + 8384 => x"38", + 8385 => x"2f", + 8386 => x"39", + 8387 => x"31", + 8388 => x"00", + 8389 => x"5a", + 8390 => x"20", + 8391 => x"20", + 8392 => x"78", + 8393 => x"73", + 8394 => x"20", + 8395 => x"0a", + 8396 => x"50", + 8397 => x"20", + 8398 => x"65", + 8399 => x"70", + 8400 => x"61", + 8401 => x"65", + 8402 => x"00", + 8403 => x"69", + 8404 => x"20", + 8405 => x"65", + 8406 => x"70", + 8407 => x"00", + 8408 => x"53", + 8409 => x"6e", + 8410 => x"72", + 8411 => x"0a", + 8412 => x"4f", + 8413 => x"20", + 8414 => x"69", + 8415 => x"72", + 8416 => x"74", + 8417 => x"4f", + 8418 => x"20", + 8419 => x"69", + 8420 => x"72", + 8421 => x"74", + 8422 => x"41", + 8423 => x"20", + 8424 => x"69", + 8425 => x"72", + 8426 => x"74", + 8427 => x"41", + 8428 => x"20", + 8429 => x"69", + 8430 => x"72", + 8431 => x"74", + 8432 => x"41", + 8433 => x"20", + 8434 => x"69", + 8435 => x"72", + 8436 => x"74", + 8437 => x"41", + 8438 => x"20", + 8439 => x"69", + 8440 => x"72", + 8441 => x"74", + 8442 => x"65", + 8443 => x"6e", + 8444 => x"70", + 8445 => x"6d", + 8446 => x"2e", + 8447 => x"00", + 8448 => x"6e", + 8449 => x"69", + 8450 => x"74", + 8451 => x"72", + 8452 => x"0a", + 8453 => x"3a", + 8454 => x"61", + 8455 => x"64", + 8456 => x"20", + 8457 => x"74", + 8458 => x"69", + 8459 => x"73", + 8460 => x"61", + 8461 => x"30", + 8462 => x"6c", + 8463 => x"65", + 8464 => x"69", + 8465 => x"61", + 8466 => x"6c", + 8467 => x"0a", + 8468 => x"20", + 8469 => x"61", + 8470 => x"69", + 8471 => x"69", + 8472 => x"00", + 8473 => x"6e", + 8474 => x"61", + 8475 => x"65", + 8476 => x"00", + 8477 => x"61", + 8478 => x"64", + 8479 => x"20", + 8480 => x"74", + 8481 => x"69", + 8482 => x"0a", + 8483 => x"63", + 8484 => x"0a", + 8485 => x"75", + 8486 => x"69", + 8487 => x"6c", + 8488 => x"20", + 8489 => x"65", + 8490 => x"70", + 8491 => x"00", + 8492 => x"6e", + 8493 => x"69", + 8494 => x"69", + 8495 => x"72", + 8496 => x"74", + 8497 => x"00", + 8498 => x"69", + 8499 => x"6c", + 8500 => x"75", + 8501 => x"20", + 8502 => x"6f", + 8503 => x"6e", + 8504 => x"69", + 8505 => x"75", + 8506 => x"20", + 8507 => x"6f", + 8508 => x"78", + 8509 => x"74", + 8510 => x"20", + 8511 => x"65", + 8512 => x"25", + 8513 => x"20", + 8514 => x"0a", + 8515 => x"61", + 8516 => x"6e", + 8517 => x"6f", + 8518 => x"40", + 8519 => x"38", + 8520 => x"2e", + 8521 => x"00", + 8522 => x"61", + 8523 => x"72", + 8524 => x"72", + 8525 => x"20", + 8526 => x"65", + 8527 => x"64", + 8528 => x"00", + 8529 => x"65", + 8530 => x"72", + 8531 => x"67", + 8532 => x"70", + 8533 => x"61", + 8534 => x"6e", + 8535 => x"0a", + 8536 => x"6f", + 8537 => x"72", + 8538 => x"6f", + 8539 => x"67", + 8540 => x"0a", + 8541 => x"50", + 8542 => x"69", + 8543 => x"64", + 8544 => x"73", + 8545 => x"2e", + 8546 => x"00", + 8547 => x"61", + 8548 => x"6f", + 8549 => x"6e", + 8550 => x"00", + 8551 => x"75", + 8552 => x"6e", + 8553 => x"2e", + 8554 => x"6e", + 8555 => x"69", + 8556 => x"69", + 8557 => x"72", + 8558 => x"74", + 8559 => x"2e", + 8560 => x"00", + 8561 => x"00", + 8562 => x"00", + 8563 => x"00", + 8564 => x"00", + 8565 => x"01", + 8566 => x"00", + 8567 => x"00", + 8568 => x"00", + 8569 => x"00", + 8570 => x"00", + 8571 => x"f5", + 8572 => x"01", + 8573 => x"01", + 8574 => x"01", + 8575 => x"00", + 8576 => x"00", + 8577 => x"00", + 8578 => x"00", + 8579 => x"01", + 8580 => x"00", + 8581 => x"00", + 8582 => x"00", + 8583 => x"02", + 8584 => x"00", + 8585 => x"00", + 8586 => x"00", + 8587 => x"03", + 8588 => x"00", + 8589 => x"00", + 8590 => x"00", + 8591 => x"04", + 8592 => x"00", + 8593 => x"00", + 8594 => x"00", + 8595 => x"0a", + 8596 => x"00", + 8597 => x"00", + 8598 => x"00", + 8599 => x"0b", + 8600 => x"00", + 8601 => x"00", + 8602 => x"00", + 8603 => x"0c", + 8604 => x"00", + 8605 => x"00", + 8606 => x"00", + 8607 => x"0d", + 8608 => x"00", + 8609 => x"00", + 8610 => x"00", + 8611 => x"0e", + 8612 => x"00", + 8613 => x"00", + 8614 => x"00", + 8615 => x"0f", + 8616 => x"00", + 8617 => x"00", + 8618 => x"00", + 8619 => x"14", + 8620 => x"00", + 8621 => x"00", + 8622 => x"00", + 8623 => x"17", + 8624 => x"00", + 8625 => x"00", + 8626 => x"00", + 8627 => x"18", + 8628 => x"00", + 8629 => x"00", + 8630 => x"00", + 8631 => x"19", + 8632 => x"00", + 8633 => x"00", + 8634 => x"00", + 8635 => x"1a", + 8636 => x"00", + 8637 => x"00", + 8638 => x"00", + 8639 => x"1c", + 8640 => x"00", + 8641 => x"00", + 8642 => x"00", + 8643 => x"1d", + 8644 => x"00", + 8645 => x"00", + 8646 => x"00", + 8647 => x"1e", + 8648 => x"00", + 8649 => x"00", + 8650 => x"00", + 8651 => x"22", + 8652 => x"00", + 8653 => x"00", + 8654 => x"00", + 8655 => x"23", + 8656 => x"00", + 8657 => x"00", + 8658 => x"00", + 8659 => x"24", + 8660 => x"00", + 8661 => x"00", + 8662 => x"00", + 8663 => x"1f", + 8664 => x"00", + 8665 => x"00", + 8666 => x"00", + 8667 => x"20", + 8668 => x"00", + 8669 => x"00", + 8670 => x"00", + 8671 => x"21", + 8672 => x"00", + 8673 => x"00", + 8674 => x"00", + 8675 => x"15", + 8676 => x"00", + 8677 => x"00", + 8678 => x"00", + 8679 => x"16", + 8680 => x"00", + 8681 => x"00", + 8682 => x"00", + 8683 => x"1b", + 8684 => x"00", + 8685 => x"00", + 8686 => x"00", + 8687 => x"25", + 8688 => x"00", + 8689 => x"00", + 8690 => x"00", + 8691 => x"2d", + 8692 => x"00", + 8693 => x"00", + 8694 => x"00", + 8695 => x"2e", + 8696 => x"00", + 8697 => x"00", + 8698 => x"00", + 8699 => x"2b", + 8700 => x"00", + 8701 => x"00", + 8702 => x"00", + 8703 => x"30", + 8704 => x"00", + 8705 => x"00", + 8706 => x"00", + 8707 => x"2f", + 8708 => x"00", + 8709 => x"00", + 8710 => x"00", + 8711 => x"2c", + 8712 => x"00", + 8713 => x"00", + 8714 => x"00", + 8715 => x"26", + 8716 => x"00", + 8717 => x"00", + 8718 => x"00", + 8719 => x"27", + 8720 => x"00", + 8721 => x"00", + 8722 => x"00", + 8723 => x"28", + 8724 => x"00", + 8725 => x"00", + 8726 => x"00", + 8727 => x"29", + 8728 => x"00", + 8729 => x"00", + 8730 => x"00", + 8731 => x"2a", + 8732 => x"00", + 8733 => x"00", + 8734 => x"00", + 8735 => x"3c", + 8736 => x"00", + 8737 => x"00", + 8738 => x"00", + 8739 => x"3d", + 8740 => x"00", + 8741 => x"00", + 8742 => x"00", + 8743 => x"3e", + 8744 => x"00", + 8745 => x"00", + 8746 => x"00", + 8747 => x"3f", + 8748 => x"00", + 8749 => x"00", + 8750 => x"00", + 8751 => x"40", + 8752 => x"00", + 8753 => x"00", + 8754 => x"00", + 8755 => x"50", + 8756 => x"00", + 8757 => x"00", + 8758 => x"00", + 8759 => x"51", + 8760 => x"00", + 8761 => x"00", + 8762 => x"00", + 8763 => x"52", + 8764 => x"00", + 8765 => x"00", + 8766 => x"00", + 8767 => x"53", + 8768 => x"00", + 8769 => x"00", + 8770 => x"00", + 8771 => x"54", + 8772 => x"00", + 8773 => x"00", + 8774 => x"00", + 8775 => x"55", + 8776 => x"00", + 8777 => x"00", + 8778 => x"00", + 8779 => x"64", + 8780 => x"00", + 8781 => x"00", + 8782 => x"00", + 8783 => x"65", + 8784 => x"00", + 8785 => x"00", + 8786 => x"00", + 8787 => x"79", + 8788 => x"00", + 8789 => x"00", + 8790 => x"00", + 8791 => x"78", + 8792 => x"00", + 8793 => x"00", + 8794 => x"00", + 8795 => x"82", + 8796 => x"00", + 8797 => x"00", + 8798 => x"00", + 8799 => x"83", + 8800 => x"00", + 8801 => x"00", + 8802 => x"00", + 8803 => x"84", + 8804 => x"00", + 8805 => x"00", + 8806 => x"00", + 8807 => x"85", + 8808 => x"00", + 8809 => x"00", + 8810 => x"00", + 8811 => x"86", + 8812 => x"00", + 8813 => x"00", + 8814 => x"00", + 8815 => x"87", + 8816 => x"00", + 8817 => x"00", + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + 0 => x"0b", + 1 => x"e9", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"88", + 9 => x"90", + 10 => x"0b", + 11 => x"2d", + 12 => x"0c", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"71", + 17 => x"72", + 18 => x"81", + 19 => x"83", + 20 => x"ff", + 21 => x"04", + 22 => x"00", + 23 => x"00", + 24 => x"71", + 25 => x"83", + 26 => x"83", + 27 => x"05", + 28 => x"2b", + 29 => x"73", + 30 => x"0b", + 31 => x"83", + 32 => x"72", + 33 => x"72", + 34 => x"09", + 35 => x"73", + 36 => x"07", + 37 => x"53", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"73", + 42 => x"51", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"71", + 50 => x"09", + 51 => x"0a", + 52 => x"0a", + 53 => x"05", + 54 => x"51", + 55 => x"04", + 56 => x"72", + 57 => x"73", + 58 => x"51", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"c4", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"0a", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"09", + 90 => x"0b", + 91 => x"05", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"73", + 98 => x"09", + 99 => x"81", + 100 => x"06", + 101 => x"04", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"04", + 106 => x"06", + 107 => x"82", + 108 => x"0b", + 109 => x"fc", + 110 => x"51", + 111 => x"00", + 112 => x"72", + 113 => x"72", + 114 => x"81", + 115 => x"0a", + 116 => x"51", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"72", + 121 => x"72", + 122 => x"81", + 123 => x"0a", + 124 => x"53", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"71", + 129 => x"52", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"04", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"73", + 146 => x"07", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"71", + 153 => x"72", + 154 => x"81", + 155 => x"10", + 156 => x"81", + 157 => x"04", + 158 => x"00", + 159 => x"00", + 160 => x"71", + 161 => x"0b", + 162 => x"88", + 163 => x"10", + 164 => x"06", + 165 => x"88", + 166 => x"00", + 167 => x"00", + 168 => x"88", + 169 => x"90", + 170 => x"0b", + 171 => x"cb", + 172 => x"88", + 173 => x"0c", + 174 => x"0c", + 175 => x"00", + 176 => x"88", + 177 => x"90", + 178 => x"0b", + 179 => x"fd", + 180 => x"88", + 181 => x"0c", + 182 => x"0c", + 183 => x"00", + 184 => x"72", + 185 => x"05", + 186 => x"81", + 187 => x"70", + 188 => x"73", + 189 => x"05", + 190 => x"07", + 191 => x"04", + 192 => x"72", + 193 => x"05", + 194 => x"09", + 195 => x"05", + 196 => x"06", + 197 => x"74", + 198 => x"06", + 199 => x"51", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"04", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"71", + 217 => x"04", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"04", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"02", + 233 => x"10", + 234 => x"04", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"05", + 250 => x"02", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"00", + 257 => x"04", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"10", + 266 => x"51", + 267 => x"73", + 268 => x"73", + 269 => x"81", + 270 => x"10", + 271 => x"07", + 272 => x"0c", + 273 => x"72", + 274 => x"81", + 275 => x"09", + 276 => x"71", + 277 => x"0a", + 278 => x"72", + 279 => x"51", + 280 => x"80", + 281 => x"e2", + 282 => x"00", + 283 => x"9f", + 284 => x"38", + 285 => x"84", + 286 => x"88", + 287 => x"e2", + 288 => x"04", + 289 => x"94", + 290 => x"0d", + 291 => x"08", + 292 => x"52", + 293 => x"05", + 294 => x"de", + 295 => x"70", + 296 => x"85", + 297 => x"0c", + 298 => x"02", + 299 => x"3d", + 300 => x"94", + 301 => x"08", + 302 => x"88", + 303 => x"82", + 304 => x"08", + 305 => x"54", + 306 => x"94", + 307 => x"08", + 308 => x"f9", + 309 => x"0b", + 310 => x"05", + 311 => x"88", + 312 => x"25", + 313 => x"08", + 314 => x"30", + 315 => x"05", + 316 => x"94", + 317 => x"0c", + 318 => x"05", + 319 => x"81", + 320 => x"f4", + 321 => x"08", + 322 => x"94", + 323 => x"0c", + 324 => x"05", + 325 => x"ab", + 326 => x"8c", + 327 => x"94", + 328 => x"0c", + 329 => x"08", + 330 => x"94", + 331 => x"08", + 332 => x"0b", + 333 => x"05", + 334 => x"f0", + 335 => x"08", + 336 => x"80", + 337 => x"8c", + 338 => x"94", + 339 => x"08", + 340 => x"3f", + 341 => x"94", + 342 => x"0c", + 343 => x"fc", + 344 => x"2e", + 345 => x"08", + 346 => x"30", + 347 => x"05", + 348 => x"f8", + 349 => x"88", + 350 => x"3d", + 351 => x"04", + 352 => x"94", + 353 => x"0d", + 354 => x"08", + 355 => x"94", + 356 => x"08", + 357 => x"38", + 358 => x"05", + 359 => x"08", + 360 => x"81", + 361 => x"fc", + 362 => x"08", + 363 => x"80", + 364 => x"94", + 365 => x"08", + 366 => x"8c", + 367 => x"53", + 368 => x"05", + 369 => x"08", + 370 => x"51", + 371 => x"08", + 372 => x"f8", + 373 => x"94", + 374 => x"08", + 375 => x"38", + 376 => x"05", + 377 => x"08", + 378 => x"94", + 379 => x"08", + 380 => x"54", + 381 => x"94", + 382 => x"08", + 383 => x"fd", + 384 => x"0b", + 385 => x"05", + 386 => x"94", + 387 => x"0c", + 388 => x"05", + 389 => x"88", + 390 => x"ac", + 391 => x"fc", + 392 => x"2e", + 393 => x"0b", + 394 => x"05", + 395 => x"38", + 396 => x"05", + 397 => x"08", + 398 => x"94", + 399 => x"08", + 400 => x"fc", + 401 => x"39", + 402 => x"05", + 403 => x"80", + 404 => x"08", + 405 => x"94", + 406 => x"08", + 407 => x"94", + 408 => x"08", + 409 => x"05", + 410 => x"08", + 411 => x"94", + 412 => x"08", + 413 => x"05", + 414 => x"08", + 415 => x"94", + 416 => x"08", + 417 => x"08", + 418 => x"94", + 419 => x"08", + 420 => x"08", + 421 => x"ff", + 422 => x"08", + 423 => x"80", + 424 => x"94", + 425 => x"08", + 426 => x"f4", + 427 => x"8d", + 428 => x"f8", + 429 => x"94", + 430 => x"0c", + 431 => x"f4", + 432 => x"0c", + 433 => x"94", + 434 => x"3d", + 435 => x"0b", + 436 => x"8c", + 437 => x"87", + 438 => x"0c", + 439 => x"c0", + 440 => x"87", + 441 => x"08", + 442 => x"51", + 443 => x"2e", + 444 => x"c0", + 445 => x"51", + 446 => x"87", + 447 => x"08", + 448 => x"06", + 449 => x"38", + 450 => x"8c", + 451 => x"80", + 452 => x"71", + 453 => x"9f", + 454 => x"0b", + 455 => x"33", + 456 => x"3d", + 457 => x"3d", + 458 => x"7d", + 459 => x"80", + 460 => x"0b", + 461 => x"81", + 462 => x"82", + 463 => x"2e", + 464 => x"81", + 465 => x"0b", + 466 => x"8c", + 467 => x"c0", + 468 => x"84", + 469 => x"92", + 470 => x"c0", + 471 => x"70", + 472 => x"81", + 473 => x"53", + 474 => x"a7", + 475 => x"92", + 476 => x"81", + 477 => x"79", + 478 => x"51", + 479 => x"90", + 480 => x"2e", + 481 => x"76", + 482 => x"58", + 483 => x"54", + 484 => x"72", + 485 => x"70", + 486 => x"38", + 487 => x"8c", + 488 => x"ff", + 489 => x"c0", + 490 => x"51", + 491 => x"81", + 492 => x"92", + 493 => x"c0", + 494 => x"70", + 495 => x"51", + 496 => x"80", + 497 => x"80", + 498 => x"70", + 499 => x"81", + 500 => x"87", + 501 => x"08", + 502 => x"2e", + 503 => x"83", + 504 => x"71", + 505 => x"3d", + 506 => x"3d", + 507 => x"11", + 508 => x"71", + 509 => x"88", + 510 => x"84", + 511 => x"fd", + 512 => x"83", + 513 => x"12", + 514 => x"2b", + 515 => x"07", + 516 => x"70", + 517 => x"2b", + 518 => x"07", + 519 => x"53", + 520 => x"52", + 521 => x"04", + 522 => x"79", + 523 => x"9f", + 524 => x"57", + 525 => x"80", + 526 => x"88", + 527 => x"80", + 528 => x"33", + 529 => x"2e", + 530 => x"83", + 531 => x"80", + 532 => x"54", + 533 => x"fe", + 534 => x"88", + 535 => x"08", + 536 => x"3d", + 537 => x"fd", + 538 => x"08", + 539 => x"51", + 540 => x"88", + 541 => x"ff", + 542 => x"39", + 543 => x"82", + 544 => x"06", + 545 => x"2a", + 546 => x"05", + 547 => x"70", + 548 => x"92", + 549 => x"8e", + 550 => x"fe", + 551 => x"08", + 552 => x"55", + 553 => x"55", + 554 => x"89", + 555 => x"fb", + 556 => x"0b", + 557 => x"08", + 558 => x"12", + 559 => x"55", + 560 => x"56", + 561 => x"8d", + 562 => x"33", + 563 => x"94", + 564 => x"57", + 565 => x"0c", + 566 => x"04", + 567 => x"75", + 568 => x"0b", + 569 => x"ac", + 570 => x"51", + 571 => x"83", + 572 => x"06", + 573 => x"14", + 574 => x"3f", + 575 => x"2b", + 576 => x"51", + 577 => x"88", + 578 => x"ff", + 579 => x"88", + 580 => x"0d", + 581 => x"0d", + 582 => x"0b", + 583 => x"55", + 584 => x"23", + 585 => x"53", + 586 => x"88", + 587 => x"08", + 588 => x"38", + 589 => x"39", + 590 => x"73", + 591 => x"83", + 592 => x"06", + 593 => x"14", + 594 => x"8c", + 595 => x"80", + 596 => x"72", + 597 => x"3f", + 598 => x"85", + 599 => x"08", + 600 => x"16", + 601 => x"71", + 602 => x"3d", + 603 => x"3d", + 604 => x"0b", + 605 => x"08", + 606 => x"05", + 607 => x"ff", + 608 => x"57", + 609 => x"2e", + 610 => x"15", + 611 => x"86", + 612 => x"80", + 613 => x"8f", + 614 => x"80", + 615 => x"13", + 616 => x"8c", + 617 => x"72", + 618 => x"0b", + 619 => x"57", + 620 => x"27", + 621 => x"39", + 622 => x"ff", + 623 => x"2a", + 624 => x"a8", + 625 => x"fc", + 626 => x"52", + 627 => x"27", + 628 => x"52", + 629 => x"17", + 630 => x"38", + 631 => x"16", + 632 => x"51", + 633 => x"88", + 634 => x"0c", + 635 => x"80", + 636 => x"0c", + 637 => x"04", + 638 => x"60", + 639 => x"5e", + 640 => x"55", + 641 => x"09", + 642 => x"38", + 643 => x"44", + 644 => x"62", + 645 => x"56", + 646 => x"09", + 647 => x"38", + 648 => x"80", + 649 => x"0c", + 650 => x"51", + 651 => x"26", + 652 => x"51", + 653 => x"88", + 654 => x"7d", + 655 => x"39", + 656 => x"1d", + 657 => x"5a", + 658 => x"a0", + 659 => x"05", + 660 => x"15", + 661 => x"2e", + 662 => x"ef", + 663 => x"59", + 664 => x"08", + 665 => x"81", + 666 => x"ff", + 667 => x"70", + 668 => x"32", + 669 => x"73", + 670 => x"25", + 671 => x"52", + 672 => x"57", + 673 => x"c7", + 674 => x"2e", + 675 => x"83", + 676 => x"77", + 677 => x"07", + 678 => x"2e", + 679 => x"88", + 680 => x"78", + 681 => x"30", + 682 => x"9f", + 683 => x"57", + 684 => x"9b", + 685 => x"8b", + 686 => x"39", + 687 => x"70", + 688 => x"72", + 689 => x"57", + 690 => x"34", + 691 => x"7a", + 692 => x"80", + 693 => x"26", + 694 => x"55", + 695 => x"34", + 696 => x"b1", + 697 => x"80", + 698 => x"54", + 699 => x"85", + 700 => x"06", + 701 => x"1c", + 702 => x"51", + 703 => x"88", + 704 => x"08", + 705 => x"7c", + 706 => x"80", + 707 => x"38", + 708 => x"70", + 709 => x"81", + 710 => x"56", + 711 => x"8b", + 712 => x"08", + 713 => x"5b", + 714 => x"18", + 715 => x"2e", + 716 => x"70", + 717 => x"33", + 718 => x"05", + 719 => x"71", + 720 => x"56", + 721 => x"e2", + 722 => x"75", + 723 => x"38", + 724 => x"9a", + 725 => x"39", + 726 => x"88", + 727 => x"83", + 728 => x"84", + 729 => x"11", + 730 => x"74", + 731 => x"1d", + 732 => x"2a", + 733 => x"51", + 734 => x"89", + 735 => x"92", + 736 => x"8e", + 737 => x"fa", + 738 => x"08", + 739 => x"fd", + 740 => x"88", + 741 => x"0d", + 742 => x"0d", + 743 => x"57", + 744 => x"fe", + 745 => x"76", + 746 => x"3f", + 747 => x"08", + 748 => x"76", + 749 => x"3f", + 750 => x"ff", + 751 => x"82", + 752 => x"d4", + 753 => x"81", + 754 => x"38", + 755 => x"53", + 756 => x"51", + 757 => x"88", + 758 => x"08", + 759 => x"51", + 760 => x"88", + 761 => x"ff", + 762 => x"81", + 763 => x"a9", + 764 => x"80", + 765 => x"52", + 766 => x"aa", + 767 => x"56", + 768 => x"38", + 769 => x"e2", + 770 => x"83", + 771 => x"55", + 772 => x"c6", + 773 => x"81", + 774 => x"0c", + 775 => x"04", + 776 => x"65", + 777 => x"0b", + 778 => x"ac", + 779 => x"3f", + 780 => x"06", + 781 => x"74", + 782 => x"74", + 783 => x"3d", + 784 => x"5a", + 785 => x"88", + 786 => x"06", + 787 => x"2e", + 788 => x"b3", + 789 => x"83", + 790 => x"52", + 791 => x"c6", + 792 => x"ab", + 793 => x"33", + 794 => x"2e", + 795 => x"3d", + 796 => x"f7", + 797 => x"08", + 798 => x"76", + 799 => x"99", + 800 => x"81", + 801 => x"76", + 802 => x"81", + 803 => x"81", + 804 => x"39", + 805 => x"86", + 806 => x"82", + 807 => x"54", + 808 => x"52", + 809 => x"fe", + 810 => x"88", + 811 => x"38", + 812 => x"05", + 813 => x"3f", + 814 => x"ff", + 815 => x"77", + 816 => x"3d", + 817 => x"f6", + 818 => x"08", + 819 => x"05", + 820 => x"29", + 821 => x"ad", + 822 => x"52", + 823 => x"8a", + 824 => x"83", + 825 => x"7a", + 826 => x"0c", + 827 => x"82", + 828 => x"3d", + 829 => x"f5", + 830 => x"08", + 831 => x"95", + 832 => x"51", + 833 => x"88", + 834 => x"ff", + 835 => x"8c", + 836 => x"ef", + 837 => x"e7", + 838 => x"56", + 839 => x"ca", + 840 => x"83", + 841 => x"76", + 842 => x"31", + 843 => x"70", + 844 => x"1d", + 845 => x"71", + 846 => x"5c", + 847 => x"c4", + 848 => x"82", + 849 => x"1b", + 850 => x"e0", + 851 => x"56", + 852 => x"fe", + 853 => x"82", + 854 => x"f6", + 855 => x"38", + 856 => x"39", + 857 => x"80", + 858 => x"38", + 859 => x"76", + 860 => x"81", + 861 => x"95", + 862 => x"51", + 863 => x"88", + 864 => x"0c", + 865 => x"19", + 866 => x"1a", + 867 => x"ff", + 868 => x"1a", + 869 => x"84", + 870 => x"1b", + 871 => x"0b", + 872 => x"78", + 873 => x"9f", + 874 => x"56", + 875 => x"95", + 876 => x"ea", + 877 => x"0b", + 878 => x"08", + 879 => x"74", + 880 => x"df", + 881 => x"81", + 882 => x"3d", + 883 => x"69", + 884 => x"70", + 885 => x"05", + 886 => x"3f", + 887 => x"88", + 888 => x"38", + 889 => x"54", + 890 => x"93", + 891 => x"05", + 892 => x"2a", + 893 => x"51", + 894 => x"80", + 895 => x"83", + 896 => x"75", + 897 => x"3f", + 898 => x"16", + 899 => x"dc", + 900 => x"eb", + 901 => x"9c", + 902 => x"98", + 903 => x"0b", + 904 => x"73", + 905 => x"3d", + 906 => x"3d", + 907 => x"7e", + 908 => x"9f", + 909 => x"5b", + 910 => x"7b", + 911 => x"75", + 912 => x"d1", + 913 => x"33", + 914 => x"84", + 915 => x"2e", + 916 => x"91", + 917 => x"17", + 918 => x"80", + 919 => x"34", + 920 => x"b1", + 921 => x"08", + 922 => x"31", + 923 => x"27", + 924 => x"58", + 925 => x"81", + 926 => x"16", + 927 => x"ff", + 928 => x"74", + 929 => x"82", + 930 => x"05", + 931 => x"06", + 932 => x"06", + 933 => x"9e", + 934 => x"38", + 935 => x"55", + 936 => x"16", + 937 => x"80", + 938 => x"55", + 939 => x"ff", + 940 => x"a4", + 941 => x"16", + 942 => x"f3", + 943 => x"55", + 944 => x"2e", + 945 => x"88", + 946 => x"17", + 947 => x"08", + 948 => x"84", + 949 => x"51", + 950 => x"27", + 951 => x"55", + 952 => x"16", + 953 => x"06", + 954 => x"08", + 955 => x"f0", + 956 => x"08", + 957 => x"98", + 958 => x"98", + 959 => x"75", + 960 => x"16", + 961 => x"78", + 962 => x"e8", + 963 => x"59", + 964 => x"80", + 965 => x"0c", + 966 => x"04", + 967 => x"9b", + 968 => x"0b", + 969 => x"8c", + 970 => x"86", + 971 => x"c0", + 972 => x"8c", + 973 => x"87", + 974 => x"0c", + 975 => x"0b", + 976 => x"94", + 977 => x"51", + 978 => x"88", + 979 => x"9f", + 980 => x"df", + 981 => x"ae", + 982 => x"0b", + 983 => x"c0", + 984 => x"55", + 985 => x"05", + 986 => x"52", + 987 => x"ba", + 988 => x"8d", + 989 => x"73", + 990 => x"38", + 991 => x"e4", + 992 => x"54", + 993 => x"54", + 994 => x"00", + 995 => x"ff", + 996 => x"ff", + 997 => x"ff", + 998 => x"42", + 999 => x"54", + 1000 => x"2e", + 1001 => x"00", + 1002 => x"01", + 2048 => x"0b", + 2049 => x"80", + 2050 => x"80", + 2051 => x"ff", + 2052 => x"ff", + 2053 => x"ff", + 2054 => x"ff", + 2055 => x"ff", + 2056 => x"0b", + 2057 => x"80", + 2058 => x"80", + 2059 => x"0b", + 2060 => x"95", + 2061 => x"80", + 2062 => x"0b", + 2063 => x"b5", + 2064 => x"80", + 2065 => x"0b", + 2066 => x"d5", + 2067 => x"80", + 2068 => x"0b", + 2069 => x"f5", + 2070 => x"80", + 2071 => x"0b", + 2072 => x"95", + 2073 => x"80", + 2074 => x"0b", + 2075 => x"b5", + 2076 => x"80", + 2077 => x"0b", + 2078 => x"d5", + 2079 => x"80", + 2080 => x"0b", + 2081 => x"f5", + 2082 => x"80", + 2083 => x"0b", + 2084 => x"95", + 2085 => x"80", + 2086 => x"0b", + 2087 => x"b5", + 2088 => x"80", + 2089 => x"0b", + 2090 => x"d5", + 2091 => x"80", + 2092 => x"0b", + 2093 => x"f5", + 2094 => x"80", + 2095 => x"0b", + 2096 => x"95", + 2097 => x"80", + 2098 => x"0b", + 2099 => x"b5", + 2100 => x"80", + 2101 => x"0b", + 2102 => x"d5", + 2103 => x"80", + 2104 => x"0b", + 2105 => x"f5", + 2106 => x"80", + 2107 => x"0b", + 2108 => x"95", + 2109 => x"80", + 2110 => x"0b", + 2111 => x"b5", + 2112 => x"80", + 2113 => x"0b", + 2114 => x"d5", + 2115 => x"80", + 2116 => x"0b", + 2117 => x"f5", + 2118 => x"80", + 2119 => x"0b", + 2120 => x"95", + 2121 => x"80", + 2122 => x"0b", + 2123 => x"b5", + 2124 => x"80", + 2125 => x"0b", + 2126 => x"d5", + 2127 => x"80", + 2128 => x"0b", + 2129 => x"f5", + 2130 => x"80", + 2131 => x"00", + 2132 => x"00", + 2133 => x"00", + 2134 => x"00", + 2135 => x"00", + 2136 => x"00", + 2137 => x"00", + 2138 => x"00", + 2139 => x"00", + 2140 => x"00", + 2141 => x"00", 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x"08", + 2201 => x"04", + 2202 => x"0c", + 2203 => x"2d", + 2204 => x"08", + 2205 => x"04", + 2206 => x"0c", + 2207 => x"2d", + 2208 => x"08", + 2209 => x"04", + 2210 => x"0c", + 2211 => x"2d", + 2212 => x"08", + 2213 => x"04", + 2214 => x"0c", + 2215 => x"2d", + 2216 => x"08", + 2217 => x"04", + 2218 => x"0c", + 2219 => x"2d", + 2220 => x"08", + 2221 => x"04", + 2222 => x"0c", + 2223 => x"2d", + 2224 => x"08", + 2225 => x"04", + 2226 => x"0c", + 2227 => x"2d", + 2228 => x"08", + 2229 => x"04", + 2230 => x"0c", + 2231 => x"2d", + 2232 => x"08", + 2233 => x"04", + 2234 => x"0c", + 2235 => x"2d", + 2236 => x"08", + 2237 => x"04", + 2238 => x"0c", + 2239 => x"2d", + 2240 => x"08", + 2241 => x"04", + 2242 => x"0c", + 2243 => x"2d", + 2244 => x"08", + 2245 => x"04", + 2246 => x"0c", + 2247 => x"2d", + 2248 => x"08", + 2249 => x"04", + 2250 => x"0c", + 2251 => x"2d", + 2252 => x"08", + 2253 => x"04", + 2254 => x"0c", + 2255 => x"2d", + 2256 => x"08", + 2257 => x"04", + 2258 => x"0c", + 2259 => x"2d", + 2260 => x"08", + 2261 => x"04", + 2262 => x"0c", + 2263 => x"2d", + 2264 => x"08", + 2265 => x"04", + 2266 => x"0c", + 2267 => x"2d", + 2268 => x"08", + 2269 => x"04", + 2270 => x"0c", + 2271 => x"2d", + 2272 => x"08", + 2273 => x"04", + 2274 => x"0c", + 2275 => x"2d", + 2276 => x"08", + 2277 => x"04", + 2278 => x"0c", + 2279 => x"2d", + 2280 => x"08", + 2281 => x"04", + 2282 => x"0c", + 2283 => x"2d", + 2284 => x"08", + 2285 => x"04", + 2286 => x"0c", + 2287 => x"2d", + 2288 => x"08", + 2289 => x"04", + 2290 => x"0c", + 2291 => x"2d", + 2292 => x"08", + 2293 => x"04", + 2294 => x"0c", + 2295 => x"2d", + 2296 => x"08", + 2297 => x"04", + 2298 => x"0c", + 2299 => x"2d", + 2300 => x"08", + 2301 => x"04", + 2302 => x"0c", + 2303 => x"2d", + 2304 => x"08", + 2305 => x"04", + 2306 => x"0c", + 2307 => x"2d", + 2308 => x"08", + 2309 => x"04", + 2310 => x"0c", + 2311 => x"2d", + 2312 => x"08", + 2313 => x"04", + 2314 => x"0c", + 2315 => x"2d", + 2316 => x"08", + 2317 => x"04", + 2318 => x"0c", + 2319 => x"2d", + 2320 => x"08", + 2321 => x"04", + 2322 => x"0c", + 2323 => x"2d", + 2324 => x"08", + 2325 => x"04", + 2326 => x"0c", + 2327 => x"2d", + 2328 => x"08", + 2329 => x"04", + 2330 => x"0c", + 2331 => x"2d", + 2332 => x"08", + 2333 => x"04", + 2334 => x"0c", + 2335 => x"2d", + 2336 => x"08", + 2337 => x"04", + 2338 => x"0c", + 2339 => x"2d", + 2340 => x"08", + 2341 => x"04", + 2342 => x"0c", + 2343 => x"2d", + 2344 => x"08", + 2345 => x"04", + 2346 => x"0c", + 2347 => x"2d", + 2348 => x"08", + 2349 => x"04", + 2350 => x"0c", + 2351 => x"2d", + 2352 => x"08", + 2353 => x"04", + 2354 => x"0c", + 2355 => x"2d", + 2356 => x"08", + 2357 => x"04", + 2358 => x"0c", + 2359 => x"2d", + 2360 => x"08", + 2361 => x"04", + 2362 => x"0c", + 2363 => x"2d", + 2364 => x"08", + 2365 => x"04", + 2366 => x"0c", + 2367 => x"2d", + 2368 => x"08", + 2369 => x"04", + 2370 => x"0c", + 2371 => x"2d", + 2372 => x"08", + 2373 => x"04", + 2374 => x"70", + 2375 => x"27", + 2376 => x"71", + 2377 => x"53", + 2378 => x"80", + 2379 => x"80", + 2380 => x"81", + 2381 => x"3c", + 2382 => x"d4", + 2383 => x"93", + 2384 => x"3d", + 2385 => x"82", + 2386 => x"8c", + 2387 => x"82", + 2388 => x"88", + 2389 => x"80", + 2390 => x"93", + 2391 => x"82", + 2392 => x"54", + 2393 => x"82", + 2394 => x"04", + 2395 => x"08", + 2396 => x"d4", + 2397 => x"0d", + 2398 => x"93", + 2399 => x"05", + 2400 => x"93", + 2401 => x"05", + 2402 => x"3f", + 2403 => x"08", + 2404 => x"c8", + 2405 => x"3d", + 2406 => x"d4", + 2407 => x"93", + 2408 => x"82", + 2409 => x"fd", + 2410 => x"0b", + 2411 => x"08", + 2412 => x"80", + 2413 => x"d4", + 2414 => x"0c", + 2415 => x"08", + 2416 => x"82", + 2417 => x"88", + 2418 => x"b9", + 2419 => x"d4", + 2420 => x"08", + 2421 => x"38", + 2422 => x"93", + 2423 => x"05", + 2424 => x"38", + 2425 => x"08", + 2426 => x"10", + 2427 => x"08", + 2428 => x"82", + 2429 => x"fc", + 2430 => x"82", + 2431 => x"fc", + 2432 => x"b8", + 2433 => x"d4", + 2434 => x"08", + 2435 => x"e1", + 2436 => x"d4", + 2437 => x"08", + 2438 => x"08", + 2439 => x"26", + 2440 => x"93", + 2441 => x"05", + 2442 => x"d4", + 2443 => x"08", + 2444 => x"d4", + 2445 => x"0c", + 2446 => x"08", + 2447 => x"82", + 2448 => x"fc", + 2449 => x"82", + 2450 => x"f8", + 2451 => x"93", + 2452 => x"05", + 2453 => x"82", + 2454 => x"fc", + 2455 => x"93", + 2456 => x"05", + 2457 => x"82", + 2458 => x"8c", + 2459 => x"95", + 2460 => x"d4", + 2461 => x"08", + 2462 => x"38", + 2463 => x"08", + 2464 => x"70", + 2465 => x"08", + 2466 => x"51", + 2467 => x"93", + 2468 => x"05", + 2469 => x"93", + 2470 => x"05", + 2471 => x"93", + 2472 => x"05", + 2473 => x"c8", + 2474 => x"0d", + 2475 => x"0c", + 2476 => x"0d", + 2477 => x"02", + 2478 => x"05", + 2479 => x"53", + 2480 => x"27", + 2481 => x"83", + 2482 => x"80", + 2483 => x"ff", + 2484 => x"ff", + 2485 => x"73", + 2486 => x"05", + 2487 => x"12", + 2488 => x"2e", + 2489 => x"ef", + 2490 => x"93", + 2491 => x"3d", + 2492 => x"74", + 2493 => x"07", + 2494 => x"2b", + 2495 => x"51", + 2496 => x"a5", + 2497 => x"70", + 2498 => x"0c", + 2499 => x"84", + 2500 => x"72", + 2501 => x"05", + 2502 => x"71", + 2503 => x"53", + 2504 => x"52", + 2505 => x"dd", + 2506 => x"27", + 2507 => x"71", + 2508 => x"53", + 2509 => x"52", + 2510 => x"f2", + 2511 => x"ff", + 2512 => x"3d", + 2513 => x"70", + 2514 => x"06", + 2515 => x"70", + 2516 => x"73", + 2517 => x"56", + 2518 => x"08", + 2519 => x"38", + 2520 => x"52", + 2521 => x"81", + 2522 => x"54", + 2523 => x"9d", + 2524 => x"55", + 2525 => x"09", + 2526 => x"38", + 2527 => x"14", + 2528 => x"81", + 2529 => x"56", + 2530 => x"e5", + 2531 => x"55", + 2532 => x"06", + 2533 => x"06", + 2534 => x"82", + 2535 => x"52", + 2536 => x"0d", + 2537 => x"70", + 2538 => x"ff", + 2539 => x"f8", + 2540 => x"80", + 2541 => x"51", + 2542 => x"84", + 2543 => x"71", + 2544 => x"54", + 2545 => x"2e", + 2546 => x"75", + 2547 => x"94", + 2548 => x"82", + 2549 => x"87", + 2550 => x"fe", + 2551 => x"70", + 2552 => x"88", + 2553 => x"9b", + 2554 => x"c8", + 2555 => x"06", + 2556 => x"14", + 2557 => x"73", + 2558 => x"71", + 2559 => x"0c", + 2560 => x"04", + 2561 => x"76", + 2562 => x"53", + 2563 => x"80", + 2564 => x"38", + 2565 => x"70", + 2566 => x"81", + 2567 => x"81", + 2568 => x"52", + 2569 => x"2e", + 2570 => x"52", + 2571 => x"12", + 2572 => x"33", + 2573 => x"a0", + 2574 => x"81", + 2575 => x"70", + 2576 => x"06", + 2577 => x"e6", + 2578 => x"51", + 2579 => x"09", + 2580 => x"38", + 2581 => x"81", + 2582 => x"71", + 2583 => x"51", + 2584 => x"c8", + 2585 => x"0d", + 2586 => x"0d", + 2587 => x"08", + 2588 => x"38", + 2589 => x"05", + 2590 => x"99", + 2591 => x"93", + 2592 => x"38", + 2593 => x"39", + 2594 => x"82", + 2595 => x"86", + 2596 => x"f5", + 2597 => x"82", + 2598 => x"05", + 2599 => x"5b", + 2600 => x"81", + 2601 => x"1c", + 2602 => x"5a", + 2603 => x"9e", + 2604 => x"38", + 2605 => x"5a", + 2606 => x"97", + 2607 => x"38", + 2608 => x"5a", + 2609 => x"bb", + 2610 => x"38", + 2611 => x"5a", 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x"7a", + 2671 => x"87", + 2672 => x"08", + 2673 => x"1b", + 2674 => x"0c", + 2675 => x"59", + 2676 => x"58", + 2677 => x"57", + 2678 => x"56", + 2679 => x"55", + 2680 => x"54", + 2681 => x"53", + 2682 => x"81", + 2683 => x"92", + 2684 => x"3d", + 2685 => x"3d", + 2686 => x"05", + 2687 => x"70", + 2688 => x"51", + 2689 => x"0b", + 2690 => x"34", + 2691 => x"04", + 2692 => x"75", + 2693 => x"8b", + 2694 => x"54", + 2695 => x"84", + 2696 => x"2e", + 2697 => x"c0", + 2698 => x"70", + 2699 => x"2a", + 2700 => x"51", + 2701 => x"80", + 2702 => x"71", + 2703 => x"81", + 2704 => x"70", + 2705 => x"96", + 2706 => x"70", + 2707 => x"51", + 2708 => x"8d", + 2709 => x"2a", + 2710 => x"51", + 2711 => x"bc", + 2712 => x"82", + 2713 => x"51", + 2714 => x"80", + 2715 => x"2e", + 2716 => x"c0", + 2717 => x"73", + 2718 => x"82", + 2719 => x"85", + 2720 => x"fd", + 2721 => x"97", + 2722 => x"0b", + 2723 => x"33", + 2724 => x"c0", + 2725 => x"72", + 2726 => x"38", + 2727 => x"94", + 2728 => x"70", + 2729 => x"81", + 2730 => x"52", + 2731 => x"8c", + 2732 => x"2a", + 2733 => x"51", + 2734 => x"38", + 2735 => x"81", + 2736 => x"06", + 2737 => x"80", + 2738 => x"71", + 2739 => x"81", + 2740 => x"70", + 2741 => x"0b", + 2742 => x"c0", + 2743 => x"c0", + 2744 => x"70", + 2745 => x"38", + 2746 => x"90", + 2747 => x"0c", + 2748 => x"04", + 2749 => x"77", + 2750 => x"33", + 2751 => x"76", + 2752 => x"38", + 2753 => x"05", + 2754 => x"0b", + 2755 => x"33", + 2756 => x"c0", + 2757 => x"72", + 2758 => x"38", + 2759 => x"94", + 2760 => x"70", + 2761 => x"81", + 2762 => x"52", + 2763 => x"8c", + 2764 => x"2a", + 2765 => x"51", + 2766 => x"38", + 2767 => x"81", + 2768 => x"06", + 2769 => x"80", + 2770 => x"71", + 2771 => x"81", + 2772 => x"70", + 2773 => x"0b", + 2774 => x"c0", + 2775 => x"c0", + 2776 => x"70", + 2777 => x"38", + 2778 => x"90", + 2779 => x"0c", + 2780 => x"33", + 2781 => x"ff", + 2782 => x"82", + 2783 => x"87", + 2784 => x"ff", + 2785 => x"0b", + 2786 => x"33", + 2787 => x"94", + 2788 => x"80", + 2789 => x"87", + 2790 => x"51", + 2791 => x"82", + 2792 => x"06", + 2793 => x"70", + 2794 => x"38", + 2795 => x"8b", + 2796 => x"87", + 2797 => x"52", + 2798 => x"86", + 2799 => x"94", + 2800 => x"08", + 2801 => x"06", + 2802 => x"0c", + 2803 => x"0d", + 2804 => x"0d", + 2805 => x"8b", + 2806 => x"87", + 2807 => x"52", + 2808 => x"86", + 2809 => x"94", + 2810 => x"08", + 2811 => x"70", + 2812 => x"51", + 2813 => x"70", + 2814 => x"38", + 2815 => x"8b", + 2816 => x"87", + 2817 => x"52", + 2818 => x"86", + 2819 => x"94", + 2820 => x"08", + 2821 => x"70", + 2822 => x"53", + 2823 => x"93", + 2824 => x"3d", + 2825 => x"3d", + 2826 => x"9e", + 2827 => x"70", + 2828 => x"06", + 2829 => x"70", + 2830 => x"9f", + 2831 => x"c4", + 2832 => x"9e", + 2833 => x"0c", + 2834 => x"c0", + 2835 => x"71", + 2836 => x"11", + 2837 => x"8c", + 2838 => x"52", + 2839 => x"c0", + 2840 => x"71", + 2841 => x"11", + 2842 => x"94", + 2843 => x"52", + 2844 => x"c0", + 2845 => x"71", + 2846 => x"11", + 2847 => x"a4", + 2848 => x"52", + 2849 => x"c0", + 2850 => x"71", + 2851 => x"11", + 2852 => x"ac", + 2853 => x"52", + 2854 => x"52", + 2855 => x"23", + 2856 => x"c0", + 2857 => x"71", + 2858 => x"0b", + 2859 => x"ad", + 2860 => x"0b", + 2861 => x"88", + 2862 => x"80", + 2863 => x"53", + 2864 => x"83", + 2865 => x"72", + 2866 => x"0b", + 2867 => x"88", + 2868 => x"80", + 2869 => x"52", + 2870 => x"2e", + 2871 => x"52", + 2872 => x"f2", + 2873 => x"87", + 2874 => x"08", + 2875 => x"80", + 2876 => x"52", + 2877 => x"83", + 2878 => x"71", + 2879 => x"34", + 2880 => x"c0", + 2881 => x"70", + 2882 => x"51", + 2883 => x"80", + 2884 => x"81", + 2885 => x"8b", + 2886 => x"0b", + 2887 => x"88", + 2888 => x"80", + 2889 => x"52", + 2890 => x"83", + 2891 => x"71", + 2892 => x"34", + 2893 => x"c0", + 2894 => x"70", + 2895 => x"51", + 2896 => x"80", + 2897 => x"81", + 2898 => x"8b", + 2899 => x"0b", + 2900 => x"88", + 2901 => x"80", + 2902 => x"52", + 2903 => x"83", + 2904 => x"71", + 2905 => x"34", + 2906 => x"c0", + 2907 => x"70", + 2908 => x"51", + 2909 => x"80", + 2910 => x"81", + 2911 => x"8b", + 2912 => x"8b", + 2913 => x"c0", + 2914 => x"08", + 2915 => x"06", + 2916 => x"51", + 2917 => x"70", + 2918 => x"05", + 2919 => x"54", + 2920 => x"70", + 2921 => x"52", + 2922 => x"2e", + 2923 => x"52", + 2924 => x"80", + 2925 => x"9e", + 2926 => x"88", + 2927 => x"52", + 2928 => x"83", + 2929 => x"71", + 2930 => x"34", + 2931 => x"88", + 2932 => x"06", + 2933 => x"82", + 2934 => x"85", + 2935 => x"fc", + 2936 => x"f6", + 2937 => x"be", + 2938 => x"f0", + 2939 => x"80", + 2940 => x"81", + 2941 => x"84", + 2942 => x"f6", + 2943 => x"a6", + 2944 => x"f1", + 2945 => x"55", + 2946 => x"91", + 2947 => x"08", + 2948 => x"c4", + 2949 => x"f7", + 2950 => x"84", + 2951 => x"f2", + 2952 => x"55", + 2953 => x"90", + 2954 => x"08", + 2955 => x"08", + 2956 => x"a8", + 2957 => x"3f", + 2958 => x"70", + 2959 => x"73", + 2960 => x"15", + 2961 => x"80", + 2962 => x"82", + 2963 => x"08", + 2964 => x"08", + 2965 => x"f7", + 2966 => x"c4", + 2967 => x"f5", + 2968 => x"80", + 2969 => x"81", + 2970 => x"83", + 2971 => x"8b", + 2972 => x"73", + 2973 => x"38", + 2974 => x"51", + 2975 => x"82", + 2976 => x"54", + 2977 => x"88", + 2978 => x"88", + 2979 => x"3f", + 2980 => x"70", + 2981 => x"73", + 2982 => x"38", + 2983 => x"52", + 2984 => x"51", + 2985 => x"82", + 2986 => x"54", + 2987 => x"88", + 2988 => x"b4", + 2989 => x"3f", + 2990 => x"70", + 2991 => x"73", + 2992 => x"38", + 2993 => x"52", + 2994 => x"51", + 2995 => x"81", + 2996 => x"82", + 2997 => x"8b", + 2998 => x"70", + 2999 => x"08", + 3000 => x"f8", + 3001 => x"88", + 3002 => x"08", + 3003 => x"a0", + 3004 => x"3f", + 3005 => x"52", + 3006 => x"51", + 3007 => x"8c", + 3008 => x"81", + 3009 => x"88", + 3010 => x"15", + 3011 => x"fa", + 3012 => x"8c", + 3013 => x"0d", + 3014 => x"0d", + 3015 => x"33", + 3016 => x"26", + 3017 => x"10", + 3018 => x"81", + 3019 => x"52", + 3020 => x"81", + 3021 => x"f7", + 3022 => x"39", + 3023 => x"51", + 3024 => x"a3", + 3025 => x"d0", + 3026 => x"3f", + 3027 => x"fa", + 3028 => x"a0", + 3029 => x"81", + 3030 => x"f7", + 3031 => x"39", + 3032 => x"51", + 3033 => x"83", + 3034 => x"71", + 3035 => x"04", + 3036 => x"c0", + 3037 => x"04", + 3038 => x"87", + 3039 => x"70", + 3040 => x"80", + 3041 => x"74", + 3042 => x"8c", + 3043 => x"0c", + 3044 => x"04", + 3045 => x"87", + 3046 => x"70", + 3047 => x"80", + 3048 => x"72", + 3049 => x"70", + 3050 => x"08", + 3051 => x"8c", + 3052 => x"0c", + 3053 => x"0d", + 3054 => x"80", + 3055 => x"96", + 3056 => x"fe", + 3057 => x"93", + 3058 => x"72", + 3059 => x"81", + 3060 => x"8d", + 3061 => x"82", + 3062 => x"80", + 3063 => x"82", + 3064 => x"52", + 3065 => x"82", + 3066 => x"81", + 3067 => x"e0", + 3068 => x"82", + 3069 => x"80", + 3070 => x"72", + 3071 => x"d8", + 3072 => x"2d", + 3073 => x"04", + 3074 => x"02", + 3075 => x"82", + 3076 => x"76", + 3077 => x"0c", + 3078 => x"a7", + 3079 => x"93", + 3080 => x"3d", + 3081 => x"3d", + 3082 => x"33", + 3083 => x"80", + 3084 => x"72", + 3085 => x"54", + 3086 => x"87", + 3087 => x"52", + 3088 => x"84", + 3089 => x"fd", + 3090 => x"82", + 3091 => x"77", + 3092 => x"0c", + 3093 => x"55", + 3094 => x"2e", + 3095 => x"70", + 3096 => x"33", + 3097 => x"3f", + 3098 => x"71", + 3099 => x"82", + 3100 => x"85", + 3101 => x"ec", + 3102 => x"68", + 3103 => x"70", + 3104 => x"33", + 3105 => x"2e", + 3106 => x"75", + 3107 => x"38", + 3108 => x"af", + 3109 => x"80", + 3110 => x"81", + 3111 => x"58", + 3112 => x"b0", + 3113 => x"06", + 3114 => x"79", + 3115 => x"5b", + 3116 => x"92", + 3117 => x"2e", + 3118 => x"8a", + 3119 => x"70", + 3120 => x"33", + 3121 => x"aa", + 3122 => x"06", + 3123 => x"84", + 3124 => x"7b", + 3125 => x"5d", + 3126 => x"5d", + 3127 => x"d0", + 3128 => x"89", + 3129 => x"79", + 3130 => x"d0", + 3131 => x"81", + 3132 => x"d0", + 3133 => x"5a", + 3134 => x"eb", + 3135 => x"ec", + 3136 => x"70", + 3137 => x"25", + 3138 => x"32", + 3139 => x"72", + 3140 => x"73", + 3141 => x"52", + 3142 => x"73", + 3143 => x"38", + 3144 => x"79", + 3145 => x"5b", + 3146 => x"75", + 3147 => x"ec", + 3148 => x"80", + 3149 => x"89", + 3150 => x"70", + 3151 => x"56", + 3152 => x"15", + 3153 => x"26", + 3154 => x"72", + 3155 => x"f0", + 3156 => x"72", + 3157 => x"84", + 3158 => x"57", + 3159 => x"75", + 3160 => x"72", + 3161 => x"38", + 3162 => x"16", + 3163 => x"54", + 3164 => x"38", + 3165 => x"70", + 3166 => x"53", + 3167 => x"73", + 3168 => x"53", + 3169 => x"99", + 3170 => x"2a", + 3171 => x"a0", + 3172 => x"3f", + 3173 => x"73", + 3174 => x"53", + 3175 => x"ef", + 3176 => x"fd", + 3177 => x"81", + 3178 => x"72", + 3179 => x"ce", + 3180 => x"fc", + 3181 => x"81", + 3182 => x"79", + 3183 => x"38", + 3184 => x"7b", + 3185 => x"12", + 3186 => x"53", + 3187 => x"fd", + 3188 => x"5b", + 3189 => x"5b", + 3190 => x"5b", + 3191 => x"5b", + 3192 => x"51", + 3193 => x"fd", + 3194 => x"82", + 3195 => x"06", + 3196 => x"80", + 3197 => x"7b", + 3198 => x"08", + 3199 => x"9c", + 3200 => x"c4", + 3201 => x"06", + 3202 => x"84", + 3203 => x"59", + 3204 => x"39", + 3205 => x"71", + 3206 => x"53", + 3207 => x"32", + 3208 => x"72", + 3209 => x"70", + 3210 => x"06", + 3211 => x"53", + 3212 => x"88", + 3213 => x"7d", + 3214 => x"57", + 3215 => x"52", + 3216 => x"a8", + 3217 => x"c8", + 3218 => x"06", + 3219 => x"52", + 3220 => x"3f", + 3221 => x"08", + 3222 => x"27", + 3223 => x"a7", + 3224 => x"ff", + 3225 => x"54", + 3226 => x"2e", + 3227 => x"14", + 3228 => x"06", + 3229 => x"3d", + 3230 => x"05", + 3231 => x"54", + 3232 => x"81", + 3233 => x"70", + 3234 => x"2a", + 3235 => x"27", + 3236 => x"54", + 3237 => x"a6", + 3238 => x"2a", + 3239 => x"51", + 3240 => x"2e", + 3241 => x"3d", + 3242 => x"05", + 3243 => x"34", + 3244 => x"77", + 3245 => x"54", + 3246 => x"72", + 3247 => x"55", + 3248 => x"70", + 3249 => x"53", + 3250 => x"73", + 3251 => x"53", + 3252 => x"99", + 3253 => x"2a", + 3254 => x"74", + 3255 => x"3f", + 3256 => x"73", + 3257 => x"53", + 3258 => x"ef", + 3259 => x"97", + 3260 => x"11", + 3261 => x"54", + 3262 => x"3f", + 3263 => x"73", + 3264 => x"53", + 3265 => x"fa", + 3266 => x"51", + 3267 => x"73", + 3268 => x"53", + 3269 => x"f2", + 3270 => x"39", + 3271 => x"04", + 3272 => x"86", + 3273 => x"84", + 3274 => x"55", + 3275 => x"fa", + 3276 => x"3d", + 3277 => x"3d", + 3278 => x"93", + 3279 => x"3d", + 3280 => x"75", + 3281 => x"3f", + 3282 => x"08", + 3283 => x"34", + 3284 => x"93", + 3285 => x"3d", + 3286 => x"3d", + 3287 => x"d8", + 3288 => x"93", + 3289 => x"3d", + 3290 => x"77", + 3291 => x"87", + 3292 => x"93", + 3293 => x"3d", + 3294 => x"3d", + 3295 => x"57", + 3296 => x"82", + 3297 => x"73", + 3298 => x"38", + 3299 => x"53", + 3300 => x"80", + 3301 => x"dc", + 3302 => x"2d", + 3303 => x"08", + 3304 => x"54", + 3305 => x"e6", + 3306 => x"2e", + 3307 => x"73", + 3308 => x"30", + 3309 => x"78", + 3310 => x"72", + 3311 => x"52", + 3312 => x"72", + 3313 => x"38", + 3314 => x"81", + 3315 => x"55", + 3316 => x"c1", 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x"73", + 3376 => x"80", + 3377 => x"14", + 3378 => x"72", + 3379 => x"e8", + 3380 => x"80", + 3381 => x"39", + 3382 => x"dc", + 3383 => x"80", + 3384 => x"27", + 3385 => x"80", + 3386 => x"89", + 3387 => x"70", + 3388 => x"55", + 3389 => x"70", + 3390 => x"55", + 3391 => x"27", + 3392 => x"14", + 3393 => x"06", + 3394 => x"74", + 3395 => x"73", + 3396 => x"38", + 3397 => x"14", + 3398 => x"05", + 3399 => x"08", + 3400 => x"54", + 3401 => x"26", + 3402 => x"77", + 3403 => x"38", + 3404 => x"75", + 3405 => x"56", + 3406 => x"c8", + 3407 => x"0d", + 3408 => x"0d", + 3409 => x"55", + 3410 => x"0c", + 3411 => x"33", + 3412 => x"73", + 3413 => x"81", + 3414 => x"74", + 3415 => x"75", + 3416 => x"70", + 3417 => x"73", + 3418 => x"38", + 3419 => x"09", + 3420 => x"38", + 3421 => x"11", + 3422 => x"08", + 3423 => x"54", + 3424 => x"2e", + 3425 => x"80", + 3426 => x"08", + 3427 => x"0c", + 3428 => x"33", + 3429 => x"80", + 3430 => x"38", + 3431 => x"2e", + 3432 => x"a1", + 3433 => x"81", + 3434 => x"75", + 3435 => x"56", + 3436 => x"c1", + 3437 => x"08", + 3438 => x"0c", + 3439 => x"33", + 3440 => x"b1", + 3441 => x"a0", + 3442 => x"82", + 3443 => x"53", + 3444 => x"57", + 3445 => x"9d", + 3446 => x"39", + 3447 => x"80", + 3448 => x"26", + 3449 => x"8b", + 3450 => x"80", + 3451 => x"56", + 3452 => x"8a", + 3453 => x"a0", + 3454 => x"c5", + 3455 => x"74", + 3456 => x"e0", + 3457 => x"ff", + 3458 => x"d0", + 3459 => x"ff", + 3460 => x"90", + 3461 => x"38", + 3462 => x"81", + 3463 => x"53", + 3464 => x"c5", + 3465 => x"27", + 3466 => x"76", + 3467 => x"08", + 3468 => x"0c", + 3469 => x"33", + 3470 => x"73", + 3471 => x"bd", + 3472 => x"2e", + 3473 => x"30", + 3474 => x"0c", + 3475 => x"82", + 3476 => x"8a", + 3477 => x"ff", + 3478 => x"8f", + 3479 => x"81", + 3480 => x"26", + 3481 => x"8c", + 3482 => x"52", + 3483 => x"c8", + 3484 => x"0d", + 3485 => x"0d", + 3486 => x"33", + 3487 => x"9b", + 3488 => x"53", + 3489 => x"81", + 3490 => x"38", + 3491 => x"87", + 3492 => x"05", + 3493 => x"73", + 3494 => x"38", + 3495 => x"71", + 3496 => x"90", + 3497 => x"92", + 3498 => x"81", + 3499 => x"0b", + 3500 => x"8c", + 3501 => x"87", + 3502 => x"54", + 3503 => x"82", + 3504 => x"70", + 3505 => x"38", + 3506 => x"70", + 3507 => x"90", + 3508 => x"92", + 3509 => x"08", + 3510 => x"06", + 3511 => x"92", + 3512 => x"98", + 3513 => x"70", + 3514 => x"38", + 3515 => x"84", + 3516 => x"8c", + 3517 => x"51", + 3518 => x"c8", + 3519 => x"0d", + 3520 => x"0d", + 3521 => x"02", + 3522 => x"c3", + 3523 => x"41", + 3524 => x"73", + 3525 => x"bf", + 3526 => x"c8", + 3527 => x"7b", + 3528 => x"81", + 3529 => x"70", + 3530 => x"c0", + 3531 => x"84", + 3532 => x"92", + 3533 => x"c0", + 3534 => x"72", + 3535 => x"5b", + 3536 => x"0c", + 3537 => x"80", + 3538 => x"0c", + 3539 => x"0c", + 3540 => x"85", + 3541 => x"06", + 3542 => x"71", + 3543 => x"38", + 3544 => x"71", + 3545 => x"05", + 3546 => x"17", + 3547 => x"06", + 3548 => x"2e", + 3549 => x"08", + 3550 => x"38", + 3551 => x"71", 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x"1d", + 3611 => x"70", + 3612 => x"52", + 3613 => x"ff", + 3614 => x"39", + 3615 => x"81", + 3616 => x"80", + 3617 => x"52", + 3618 => x"90", + 3619 => x"80", + 3620 => x"71", + 3621 => x"7c", + 3622 => x"38", + 3623 => x"80", + 3624 => x"80", + 3625 => x"81", + 3626 => x"73", + 3627 => x"0c", + 3628 => x"04", + 3629 => x"7d", + 3630 => x"af", + 3631 => x"88", + 3632 => x"33", + 3633 => x"56", + 3634 => x"3f", + 3635 => x"08", + 3636 => x"83", + 3637 => x"38", + 3638 => x"74", + 3639 => x"72", + 3640 => x"38", + 3641 => x"8a", + 3642 => x"72", + 3643 => x"38", + 3644 => x"90", + 3645 => x"92", + 3646 => x"08", + 3647 => x"39", + 3648 => x"76", + 3649 => x"8b", + 3650 => x"76", + 3651 => x"83", + 3652 => x"73", + 3653 => x"0c", + 3654 => x"04", + 3655 => x"73", + 3656 => x"12", + 3657 => x"2b", + 3658 => x"93", + 3659 => x"52", + 3660 => x"0d", + 3661 => x"0d", + 3662 => x"33", + 3663 => x"71", + 3664 => x"88", + 3665 => x"14", + 3666 => x"74", + 3667 => x"2b", + 3668 => x"c8", + 3669 => x"56", + 3670 => x"3d", + 3671 => x"3d", + 3672 => x"84", + 3673 => x"22", + 3674 => x"72", + 3675 => x"54", + 3676 => x"2a", + 3677 => x"34", + 3678 => x"04", + 3679 => x"73", + 3680 => x"70", + 3681 => x"05", + 3682 => x"88", + 3683 => x"72", + 3684 => x"54", + 3685 => x"2a", + 3686 => x"70", + 3687 => x"34", + 3688 => x"51", + 3689 => x"83", + 3690 => x"fe", + 3691 => x"75", + 3692 => x"51", + 3693 => x"93", + 3694 => x"81", + 3695 => x"73", + 3696 => x"55", + 3697 => x"51", + 3698 => x"84", + 3699 => x"fe", + 3700 => x"77", + 3701 => x"53", + 3702 => x"81", + 3703 => x"ff", + 3704 => x"f4", + 3705 => x"0d", + 3706 => x"0d", + 3707 => x"56", + 3708 => x"70", + 3709 => x"33", + 3710 => x"05", + 3711 => x"71", + 3712 => x"56", + 3713 => x"72", + 3714 => x"38", + 3715 => x"e2", + 3716 => x"93", + 3717 => x"3d", + 3718 => x"3d", + 3719 => x"71", + 3720 => x"52", + 3721 => x"99", + 3722 => x"2e", + 3723 => x"12", + 3724 => x"52", + 3725 => x"89", + 3726 => x"2e", + 3727 => x"ee", + 3728 => x"82", + 3729 => x"84", + 3730 => x"80", + 3731 => x"c8", + 3732 => x"0b", + 3733 => x"0c", + 3734 => x"0d", + 3735 => x"0b", + 3736 => x"56", + 3737 => x"2e", + 3738 => x"81", + 3739 => x"08", + 3740 => x"70", + 3741 => x"33", + 3742 => x"de", + 3743 => x"c8", + 3744 => x"09", + 3745 => x"38", + 3746 => x"08", + 3747 => x"b0", + 3748 => x"17", + 3749 => x"74", + 3750 => x"27", + 3751 => x"16", + 3752 => x"82", + 3753 => x"06", + 3754 => x"54", + 3755 => x"9c", + 3756 => x"53", + 3757 => x"16", + 3758 => x"9e", + 3759 => x"81", + 3760 => x"93", + 3761 => x"3d", + 3762 => x"3d", + 3763 => x"56", + 3764 => x"b0", + 3765 => x"2e", + 3766 => x"51", + 3767 => x"82", + 3768 => x"56", + 3769 => x"08", + 3770 => x"54", + 3771 => x"17", + 3772 => x"33", + 3773 => x"3f", + 3774 => x"08", + 3775 => x"38", + 3776 => x"56", + 3777 => x"0c", + 3778 => x"c8", + 3779 => x"0d", + 3780 => x"0d", + 3781 => x"57", + 3782 => x"82", + 3783 => x"58", + 3784 => x"08", + 3785 => x"76", + 3786 => x"83", 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x"2e", + 3846 => x"bf", + 3847 => x"2e", + 3848 => x"81", + 3849 => x"81", + 3850 => x"89", + 3851 => x"08", + 3852 => x"52", + 3853 => x"3f", + 3854 => x"08", + 3855 => x"76", + 3856 => x"14", + 3857 => x"81", + 3858 => x"2a", + 3859 => x"05", + 3860 => x"59", + 3861 => x"f2", + 3862 => x"c8", + 3863 => x"38", + 3864 => x"06", + 3865 => x"33", + 3866 => x"7a", + 3867 => x"06", + 3868 => x"5a", + 3869 => x"53", + 3870 => x"38", + 3871 => x"06", + 3872 => x"39", + 3873 => x"a4", + 3874 => x"52", + 3875 => x"ba", + 3876 => x"c8", + 3877 => x"38", + 3878 => x"ff", + 3879 => x"b4", + 3880 => x"f8", + 3881 => x"c8", + 3882 => x"ff", + 3883 => x"39", + 3884 => x"a4", + 3885 => x"52", + 3886 => x"8e", + 3887 => x"c8", + 3888 => x"74", + 3889 => x"fc", + 3890 => x"b4", + 3891 => x"e5", + 3892 => x"c8", + 3893 => x"06", + 3894 => x"81", + 3895 => x"93", + 3896 => x"3d", + 3897 => x"3d", + 3898 => x"7f", + 3899 => x"82", + 3900 => x"27", + 3901 => x"73", + 3902 => x"27", + 3903 => x"74", + 3904 => x"77", + 3905 => x"38", + 3906 => x"89", + 3907 => x"2e", + 3908 => x"91", + 3909 => x"2e", + 3910 => x"82", + 3911 => x"81", + 3912 => x"89", + 3913 => x"08", + 3914 => x"52", + 3915 => x"3f", + 3916 => x"08", + 3917 => x"c8", + 3918 => x"38", + 3919 => x"06", + 3920 => x"81", + 3921 => x"06", + 3922 => x"58", + 3923 => x"80", + 3924 => x"75", + 3925 => x"f0", + 3926 => x"8f", + 3927 => x"58", + 3928 => x"34", + 3929 => x"16", + 3930 => x"2a", + 3931 => x"05", + 3932 => x"fa", + 3933 => x"93", + 3934 => x"82", + 3935 => x"81", + 3936 => x"83", + 3937 => x"b4", + 3938 => x"06", + 3939 => x"57", + 3940 => x"72", + 3941 => x"88", + 3942 => x"57", + 3943 => x"81", + 3944 => x"54", + 3945 => x"81", + 3946 => x"34", + 3947 => x"73", + 3948 => x"16", + 3949 => x"74", + 3950 => x"3f", + 3951 => x"08", + 3952 => x"c8", + 3953 => x"38", + 3954 => x"ff", + 3955 => x"14", + 3956 => x"75", + 3957 => x"51", + 3958 => x"81", + 3959 => x"34", + 3960 => x"73", + 3961 => x"16", + 3962 => x"74", + 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4668 => x"17", + 4669 => x"80", + 4670 => x"82", + 4671 => x"06", + 4672 => x"bb", + 4673 => x"b7", + 4674 => x"2a", + 4675 => x"51", + 4676 => x"38", + 4677 => x"70", + 4678 => x"81", + 4679 => x"54", + 4680 => x"fe", + 4681 => x"16", + 4682 => x"06", + 4683 => x"52", + 4684 => x"b4", + 4685 => x"c8", + 4686 => x"0c", + 4687 => x"74", + 4688 => x"0c", + 4689 => x"04", + 4690 => x"7c", + 4691 => x"08", + 4692 => x"59", + 4693 => x"80", + 4694 => x"38", + 4695 => x"05", + 4696 => x"ba", + 4697 => x"72", + 4698 => x"9f", + 4699 => x"51", + 4700 => x"e8", + 4701 => x"2e", + 4702 => x"81", + 4703 => x"33", + 4704 => x"52", + 4705 => x"92", + 4706 => x"72", + 4707 => x"d0", + 4708 => x"51", + 4709 => x"80", + 4710 => x"0b", + 4711 => x"5c", + 4712 => x"10", + 4713 => x"7a", + 4714 => x"51", + 4715 => x"05", + 4716 => x"70", + 4717 => x"33", + 4718 => x"53", + 4719 => x"99", + 4720 => x"e0", + 4721 => x"ff", + 4722 => x"ff", + 4723 => x"70", + 4724 => x"38", + 4725 => x"81", + 4726 => x"51", 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x"82", + 4786 => x"55", + 4787 => x"08", + 4788 => x"38", + 4789 => x"82", + 4790 => x"87", + 4791 => x"f3", + 4792 => x"02", + 4793 => x"c7", + 4794 => x"54", + 4795 => x"7f", + 4796 => x"3f", + 4797 => x"08", + 4798 => x"80", + 4799 => x"c8", + 4800 => x"9e", + 4801 => x"c8", + 4802 => x"82", + 4803 => x"70", + 4804 => x"8c", + 4805 => x"2e", + 4806 => x"74", + 4807 => x"81", + 4808 => x"33", + 4809 => x"80", + 4810 => x"81", + 4811 => x"d6", + 4812 => x"93", + 4813 => x"ff", + 4814 => x"06", + 4815 => x"99", + 4816 => x"2e", + 4817 => x"82", + 4818 => x"06", + 4819 => x"56", + 4820 => x"38", + 4821 => x"ca", + 4822 => x"34", + 4823 => x"34", + 4824 => x"15", + 4825 => x"8d", + 4826 => x"c8", + 4827 => x"06", + 4828 => x"54", + 4829 => x"72", + 4830 => x"76", + 4831 => x"38", + 4832 => x"70", + 4833 => x"53", + 4834 => x"86", + 4835 => x"70", + 4836 => x"5a", + 4837 => x"82", + 4838 => x"81", + 4839 => x"76", + 4840 => x"81", + 4841 => x"38", + 4842 => x"90", + 4843 => x"3d", + 4844 => x"05", + 4845 => x"f6", + 4846 => x"59", + 4847 => x"72", + 4848 => x"38", + 4849 => x"51", + 4850 => x"82", + 4851 => x"57", + 4852 => x"81", + 4853 => x"74", + 4854 => x"80", + 4855 => x"74", + 4856 => x"f0", + 4857 => x"53", + 4858 => x"80", + 4859 => x"79", + 4860 => x"fc", + 4861 => x"93", + 4862 => x"ff", + 4863 => x"77", + 4864 => x"81", + 4865 => x"74", + 4866 => x"81", + 4867 => x"2e", + 4868 => x"8d", + 4869 => x"26", + 4870 => x"bf", + 4871 => x"fc", + 4872 => x"c8", + 4873 => x"ff", + 4874 => x"56", + 4875 => x"2e", + 4876 => x"84", + 4877 => x"ca", + 4878 => x"e0", + 4879 => x"c8", + 4880 => x"ff", + 4881 => x"8d", + 4882 => x"15", + 4883 => x"3f", + 4884 => x"08", + 4885 => x"16", + 4886 => x"15", + 4887 => x"34", + 4888 => x"33", + 4889 => x"8d", + 4890 => x"26", + 4891 => x"82", + 4892 => x"71", + 4893 => x"17", + 4894 => x"53", + 4895 => x"23", + 4896 => x"ff", + 4897 => x"80", + 4898 => x"ff", + 4899 => x"53", + 4900 => x"86", + 4901 => x"84", + 4902 => x"c5", + 4903 => x"fc", + 4904 => x"c8", + 4905 => x"23", + 4906 => x"08", + 4907 => x"06", + 4908 => x"8d", + 4909 => x"ea", + 4910 => x"15", + 4911 => x"3f", + 4912 => x"08", + 4913 => x"06", + 4914 => x"38", + 4915 => x"51", + 4916 => x"82", + 4917 => x"53", + 4918 => x"51", + 4919 => x"82", + 4920 => x"83", + 4921 => x"59", + 4922 => x"80", + 4923 => x"38", + 4924 => x"74", + 4925 => x"2a", + 4926 => x"8d", + 4927 => x"26", + 4928 => x"8a", + 4929 => x"72", + 4930 => x"ff", + 4931 => x"82", + 4932 => x"53", + 4933 => x"93", + 4934 => x"2e", + 4935 => x"80", + 4936 => x"c8", + 4937 => x"ff", + 4938 => x"83", + 4939 => x"72", + 4940 => x"26", + 4941 => x"57", + 4942 => x"26", + 4943 => x"57", + 4944 => x"80", + 4945 => x"38", + 4946 => x"16", + 4947 => x"16", + 4948 => x"a4", + 4949 => x"1a", + 4950 => x"76", + 4951 => x"81", + 4952 => x"80", + 4953 => x"d7", + 4954 => x"93", + 4955 => x"ff", + 4956 => x"8d", + 4957 => x"aa", + 4958 => x"22", + 4959 => x"72", + 4960 => x"80", + 4961 => x"d7", + 4962 => x"93", + 4963 => x"16", + 4964 => x"08", + 4965 => x"b6", + 4966 => x"22", + 4967 => x"72", + 4968 => x"fe", + 4969 => x"08", + 4970 => x"0c", + 4971 => x"09", + 4972 => x"38", + 4973 => x"10", + 4974 => x"98", + 4975 => x"98", + 4976 => x"70", + 4977 => x"17", + 4978 => x"05", + 4979 => x"ff", + 4980 => x"53", + 4981 => x"9c", + 4982 => x"81", + 4983 => x"0b", + 4984 => x"ff", + 4985 => x"0c", + 4986 => x"84", + 4987 => x"83", + 4988 => x"06", + 4989 => x"80", + 4990 => x"d6", + 4991 => x"93", + 4992 => x"ff", + 4993 => x"72", + 4994 => x"81", + 4995 => x"38", + 4996 => x"74", + 4997 => x"3f", + 4998 => x"08", + 4999 => x"82", + 5000 => x"84", + 5001 => x"b2", + 5002 => x"f0", + 5003 => x"c8", + 5004 => x"ff", + 5005 => x"82", + 5006 => x"09", + 5007 => x"c8", + 5008 => x"51", + 5009 => x"82", + 5010 => x"84", + 5011 => x"d2", + 5012 => x"06", + 5013 => x"98", + 5014 => x"d9", + 5015 => x"c8", + 5016 => x"85", + 5017 => x"09", + 5018 => x"38", + 5019 => x"51", + 5020 => x"82", + 5021 => x"90", + 5022 => x"a0", + 5023 => x"b5", + 5024 => x"c8", + 5025 => x"0c", + 5026 => x"82", + 5027 => x"81", + 5028 => x"82", + 5029 => x"72", + 5030 => x"80", + 5031 => x"0c", + 5032 => x"82", + 5033 => x"8f", + 5034 => x"fb", + 5035 => x"54", + 5036 => x"80", + 5037 => x"73", + 5038 => x"af", + 5039 => x"70", + 5040 => x"71", + 5041 => x"38", + 5042 => x"86", + 5043 => x"52", + 5044 => x"09", + 5045 => x"38", + 5046 => x"51", + 5047 => x"82", + 5048 => x"81", + 5049 => x"83", + 5050 => x"80", + 5051 => x"2e", + 5052 => x"84", + 5053 => x"53", + 5054 => x"0c", + 5055 => x"93", + 5056 => x"3d", + 5057 => x"3d", + 5058 => x"05", + 5059 => x"89", + 5060 => x"52", + 5061 => x"3f", + 5062 => x"08", + 5063 => x"80", + 5064 => x"c8", + 5065 => x"c4", + 5066 => x"c8", + 5067 => x"82", + 5068 => x"70", + 5069 => x"73", + 5070 => x"38", + 5071 => x"78", + 5072 => x"38", + 5073 => x"74", + 5074 => x"10", + 5075 => x"05", + 5076 => x"54", + 5077 => x"80", + 5078 => x"80", + 5079 => x"70", + 5080 => x"51", + 5081 => x"82", + 5082 => x"54", + 5083 => x"c8", + 5084 => x"0d", + 5085 => x"0d", + 5086 => x"05", + 5087 => x"33", + 5088 => x"55", + 5089 => x"84", + 5090 => x"bf", + 5091 => x"98", + 5092 => x"53", + 5093 => x"05", + 5094 => x"c3", + 5095 => x"c8", + 5096 => x"93", + 5097 => x"c5", + 5098 => x"68", + 5099 => x"d4", + 5100 => x"db", + 5101 => x"c8", + 5102 => x"93", + 5103 => x"38", + 5104 => x"05", + 5105 => x"2b", + 5106 => x"80", + 5107 => x"86", + 5108 => x"06", + 5109 => x"2e", + 5110 => x"75", + 5111 => x"38", + 5112 => x"09", + 5113 => x"38", + 5114 => x"05", + 5115 => x"3f", + 5116 => x"08", + 5117 => x"07", + 5118 => x"02", + 5119 => x"91", + 5120 => x"80", + 5121 => x"87", + 5122 => x"76", + 5123 => x"81", + 5124 => x"74", + 5125 => x"38", + 5126 => x"83", + 5127 => x"83", + 5128 => x"06", + 5129 => x"80", + 5130 => x"38", + 5131 => x"51", + 5132 => x"82", + 5133 => x"59", + 5134 => x"0a", + 5135 => x"05", + 5136 => x"3f", + 5137 => x"0b", + 5138 => x"75", + 5139 => x"7a", + 5140 => x"3f", + 5141 => x"9c", + 5142 => x"a0", + 5143 => x"81", + 5144 => x"34", + 5145 => x"80", + 5146 => x"b0", + 5147 => x"55", + 5148 => x"3d", + 5149 => x"51", + 5150 => x"3f", + 5151 => x"08", + 5152 => x"c8", + 5153 => x"38", + 5154 => x"51", + 5155 => x"82", + 5156 => x"7b", + 5157 => x"12", + 5158 => x"b6", + 5159 => x"cd", + 5160 => x"05", + 5161 => x"2a", + 5162 => x"51", + 5163 => x"80", + 5164 => x"84", + 5165 => x"76", + 5166 => x"81", + 5167 => x"74", + 5168 => x"38", + 5169 => x"33", + 5170 => x"74", + 5171 => x"38", + 5172 => x"82", + 5173 => x"83", + 5174 => x"06", + 5175 => x"80", + 5176 => x"76", + 5177 => x"57", + 5178 => x"08", + 5179 => x"63", + 5180 => x"55", + 5181 => x"38", + 5182 => x"51", + 5183 => x"82", + 5184 => x"88", + 5185 => x"9c", + 5186 => x"a9", + 5187 => x"c8", + 5188 => x"0c", + 5189 => x"86", + 5190 => x"19", + 5191 => x"19", + 5192 => x"19", + 5193 => x"19", + 5194 => x"19", + 5195 => x"53", + 5196 => x"18", + 5197 => x"3f", + 5198 => x"70", + 5199 => x"55", + 5200 => x"81", + 5201 => x"18", + 5202 => x"81", + 5203 => x"18", + 5204 => x"0c", + 5205 => x"22", + 5206 => x"88", + 5207 => x"1c", + 5208 => x"5c", + 5209 => x"39", + 5210 => x"51", + 5211 => x"82", + 5212 => x"57", + 5213 => x"08", + 5214 => x"38", + 5215 => x"ff", + 5216 => x"06", + 5217 => x"56", + 5218 => x"59", + 5219 => x"77", + 5220 => x"70", + 5221 => x"06", + 5222 => x"74", + 5223 => x"98", + 5224 => x"80", + 5225 => x"83", + 5226 => x"74", + 5227 => x"38", + 5228 => x"51", + 5229 => x"82", + 5230 => x"85", + 5231 => x"a8", + 5232 => x"2a", + 5233 => x"08", + 5234 => x"1a", + 5235 => x"54", + 5236 => x"18", + 5237 => x"11", + 5238 => x"ca", + 5239 => x"93", + 5240 => x"2e", + 5241 => x"56", + 5242 => x"84", + 5243 => x"0c", + 5244 => x"82", + 5245 => x"97", + 5246 => x"f3", + 5247 => x"62", + 5248 => x"5f", + 5249 => x"7d", + 5250 => x"fc", + 5251 => x"51", + 5252 => x"82", + 5253 => x"55", + 5254 => x"08", + 5255 => x"17", + 5256 => x"80", + 5257 => x"74", + 5258 => x"39", + 5259 => x"81", + 5260 => x"56", + 5261 => x"83", + 5262 => x"39", + 5263 => x"18", + 5264 => x"83", + 5265 => x"0b", + 5266 => x"81", + 5267 => x"39", + 5268 => x"18", + 5269 => x"83", + 5270 => x"0b", + 5271 => x"81", + 5272 => x"39", + 5273 => x"18", + 5274 => x"82", + 5275 => x"0b", + 5276 => x"81", + 5277 => x"39", + 5278 => x"94", + 5279 => x"55", + 5280 => x"83", + 5281 => x"78", + 5282 => x"cb", + 5283 => x"08", + 5284 => x"06", + 5285 => x"82", + 5286 => x"8a", + 5287 => x"05", + 5288 => x"06", + 5289 => x"a8", + 5290 => x"38", + 5291 => x"55", + 5292 => x"17", + 5293 => x"51", + 5294 => x"82", + 5295 => x"55", + 5296 => x"fe", + 5297 => x"ff", + 5298 => x"38", + 5299 => x"0c", + 5300 => x"52", + 5301 => x"e8", + 5302 => x"c8", + 5303 => x"fe", + 5304 => x"93", + 5305 => x"79", + 5306 => x"58", + 5307 => x"80", + 5308 => x"1b", + 5309 => x"22", + 5310 => x"74", + 5311 => x"38", + 5312 => x"5a", + 5313 => x"53", + 5314 => x"81", + 5315 => x"55", + 5316 => x"82", + 5317 => x"fe", + 5318 => x"17", + 5319 => x"2b", + 5320 => x"80", + 5321 => x"9c", + 5322 => x"31", + 5323 => x"27", + 5324 => x"80", + 5325 => x"52", + 5326 => x"29", + 5327 => x"eb", + 5328 => x"2b", + 5329 => x"39", + 5330 => x"78", + 5331 => x"38", + 5332 => x"70", + 5333 => x"56", + 5334 => x"a5", + 5335 => x"9c", + 5336 => x"a8", + 5337 => x"81", + 5338 => x"55", + 5339 => x"82", + 5340 => x"fd", + 5341 => x"17", + 5342 => x"06", + 5343 => x"18", + 5344 => x"77", + 5345 => x"52", + 5346 => x"33", + 5347 => x"f1", + 5348 => x"c8", + 5349 => x"38", + 5350 => x"0c", + 5351 => x"83", + 5352 => x"80", + 5353 => x"55", + 5354 => x"83", + 5355 => x"75", + 5356 => x"08", + 5357 => x"17", + 5358 => x"7b", + 5359 => x"3f", + 5360 => x"7d", + 5361 => x"0c", + 5362 => x"19", + 5363 => x"1a", + 5364 => x"78", + 5365 => x"80", + 5366 => x"93", + 5367 => x"3d", + 5368 => x"3d", + 5369 => x"64", + 5370 => x"5a", + 5371 => x"0c", + 5372 => x"05", + 5373 => x"f5", + 5374 => x"93", + 5375 => x"82", + 5376 => x"8a", + 5377 => x"33", + 5378 => x"2e", + 5379 => x"56", + 5380 => x"90", + 5381 => x"81", + 5382 => x"06", + 5383 => x"87", + 5384 => x"2e", + 5385 => x"bd", + 5386 => x"91", + 5387 => x"56", + 5388 => x"81", + 5389 => x"34", + 5390 => x"d8", + 5391 => x"91", + 5392 => x"56", + 5393 => x"82", + 5394 => x"34", + 5395 => x"c4", + 5396 => x"91", + 5397 => x"56", + 5398 => x"81", + 5399 => x"34", + 5400 => x"b0", + 5401 => x"08", + 5402 => x"94", + 5403 => x"86", + 5404 => x"08", + 5405 => x"80", + 5406 => x"38", + 5407 => x"70", + 5408 => x"56", + 5409 => x"a8", + 5410 => x"11", + 5411 => x"77", + 5412 => x"5c", + 5413 => x"c6", + 5414 => x"38", + 5415 => x"55", + 5416 => x"7a", + 5417 => x"d4", + 5418 => x"93", + 5419 => x"8f", + 5420 => x"08", + 5421 => x"d4", + 5422 => x"93", + 5423 => x"74", + 5424 => x"c3", + 5425 => x"2e", + 5426 => x"74", + 5427 => x"e3", + 5428 => x"18", + 5429 => x"08", + 5430 => x"88", + 5431 => x"17", + 5432 => x"2b", + 5433 => x"80", + 5434 => x"81", + 5435 => x"08", + 5436 => x"52", + 5437 => x"33", + 5438 => x"de", + 5439 => x"c8", + 5440 => x"38", + 5441 => x"80", + 5442 => x"74", + 5443 => x"98", + 5444 => x"7d", + 5445 => x"3f", + 5446 => x"08", + 5447 => x"a7", + 5448 => x"c8", + 5449 => x"89", + 5450 => x"79", + 5451 => x"d5", + 5452 => x"7e", + 5453 => x"51", + 5454 => x"76", + 5455 => x"74", + 5456 => x"79", + 5457 => x"7b", + 5458 => x"11", + 5459 => x"c5", + 5460 => x"93", + 5461 => x"f9", + 5462 => x"08", + 5463 => x"74", + 5464 => x"38", + 5465 => x"74", + 5466 => x"1c", + 5467 => x"51", + 5468 => x"90", + 5469 => x"ff", + 5470 => x"90", + 5471 => x"89", + 5472 => x"db", + 5473 => x"08", + 5474 => x"38", + 5475 => x"8c", + 5476 => x"98", + 5477 => x"77", + 5478 => x"52", + 5479 => x"33", + 5480 => x"dd", + 5481 => x"c8", + 5482 => x"38", + 5483 => x"0c", + 5484 => x"83", + 5485 => x"80", + 5486 => x"55", + 5487 => x"83", + 5488 => x"75", + 5489 => x"94", + 5490 => x"ff", + 5491 => x"05", + 5492 => x"3f", + 5493 => x"ff", + 5494 => x"74", + 5495 => x"78", + 5496 => x"08", + 5497 => x"76", + 5498 => x"08", + 5499 => x"1b", + 5500 => x"08", + 5501 => x"59", + 5502 => x"83", + 5503 => x"74", + 5504 => x"78", + 5505 => x"90", + 5506 => x"c0", + 5507 => x"90", + 5508 => x"56", + 5509 => x"c8", + 5510 => x"0d", + 5511 => x"0d", + 5512 => x"fc", + 5513 => x"52", + 5514 => x"3f", + 5515 => x"08", + 5516 => x"c8", + 5517 => x"38", + 5518 => x"70", + 5519 => x"81", + 5520 => x"56", + 5521 => x"81", + 5522 => x"98", + 5523 => x"80", + 5524 => x"81", + 5525 => x"08", + 5526 => x"52", + 5527 => x"33", + 5528 => x"f6", + 5529 => x"82", + 5530 => x"80", + 5531 => x"18", + 5532 => x"06", + 5533 => x"19", + 5534 => x"08", + 5535 => x"c8", + 5536 => x"93", + 5537 => x"82", + 5538 => x"80", + 5539 => x"18", + 5540 => x"33", + 5541 => x"56", + 5542 => x"34", + 5543 => x"53", + 5544 => x"08", + 5545 => x"3f", + 5546 => x"52", + 5547 => x"c5", + 5548 => x"88", + 5549 => x"96", + 5550 => x"c0", + 5551 => x"92", + 5552 => x"9a", + 5553 => x"81", + 5554 => x"34", + 5555 => x"c1", + 5556 => x"c8", + 5557 => x"33", + 5558 => x"56", + 5559 => x"19", + 5560 => x"74", + 5561 => x"0c", + 5562 => x"04", + 5563 => x"76", + 5564 => x"fe", + 5565 => x"93", + 5566 => x"82", + 5567 => x"9c", + 5568 => x"fc", + 5569 => x"51", + 5570 => x"82", + 5571 => x"53", + 5572 => x"08", + 5573 => x"93", + 5574 => x"0c", + 5575 => x"c8", + 5576 => x"0d", + 5577 => x"0d", + 5578 => x"e4", + 5579 => x"53", + 5580 => x"93", + 5581 => x"8b", + 5582 => x"c8", + 5583 => x"f8", + 5584 => x"72", + 5585 => x"0c", + 5586 => x"04", + 5587 => x"80", + 5588 => x"d0", + 5589 => x"3d", + 5590 => x"3f", + 5591 => x"08", + 5592 => x"c8", + 5593 => x"38", + 5594 => x"52", + 5595 => x"05", + 5596 => x"3f", + 5597 => x"08", + 5598 => x"c8", + 5599 => x"02", + 5600 => x"33", + 5601 => x"55", + 5602 => x"25", + 5603 => x"7a", + 5604 => x"54", + 5605 => x"a2", + 5606 => x"84", + 5607 => x"06", + 5608 => x"73", + 5609 => x"38", + 5610 => x"70", + 5611 => x"b8", + 5612 => x"c8", + 5613 => x"0c", + 5614 => x"55", + 5615 => x"09", + 5616 => x"38", + 5617 => x"82", + 5618 => x"93", + 5619 => x"e1", + 5620 => x"3d", + 5621 => x"08", + 5622 => x"7a", + 5623 => x"a1", + 5624 => x"05", + 5625 => x"51", + 5626 => x"82", + 5627 => x"57", + 5628 => x"08", + 5629 => x"7e", + 5630 => x"94", + 5631 => x"55", + 5632 => x"74", + 5633 => x"f9", + 5634 => x"70", + 5635 => x"5e", + 5636 => x"7a", + 5637 => x"3f", + 5638 => x"08", + 5639 => x"c8", + 5640 => x"38", + 5641 => x"51", + 5642 => x"82", + 5643 => x"57", + 5644 => x"08", + 5645 => x"6c", + 5646 => x"d6", + 5647 => x"93", + 5648 => x"76", + 5649 => x"d1", + 5650 => x"93", + 5651 => x"82", + 5652 => x"81", + 5653 => x"54", + 5654 => x"51", + 5655 => x"82", + 5656 => x"57", + 5657 => x"08", + 5658 => x"52", + 5659 => x"f8", + 5660 => x"c8", + 5661 => x"95", + 5662 => x"73", + 5663 => x"3f", + 5664 => x"08", + 5665 => x"c8", + 5666 => x"cc", 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x"19", + 5726 => x"54", + 5727 => x"70", + 5728 => x"34", + 5729 => x"ec", + 5730 => x"34", + 5731 => x"c8", + 5732 => x"0d", + 5733 => x"0d", + 5734 => x"3d", + 5735 => x"71", + 5736 => x"ea", + 5737 => x"93", + 5738 => x"82", + 5739 => x"8a", + 5740 => x"33", + 5741 => x"2e", + 5742 => x"55", + 5743 => x"8c", + 5744 => x"27", + 5745 => x"17", + 5746 => x"2a", + 5747 => x"51", + 5748 => x"85", + 5749 => x"08", + 5750 => x"08", + 5751 => x"94", + 5752 => x"77", + 5753 => x"b3", + 5754 => x"11", + 5755 => x"2b", + 5756 => x"75", + 5757 => x"38", + 5758 => x"18", + 5759 => x"b9", + 5760 => x"c8", + 5761 => x"7a", + 5762 => x"57", + 5763 => x"a9", + 5764 => x"c8", + 5765 => x"95", + 5766 => x"76", + 5767 => x"0c", + 5768 => x"08", + 5769 => x"08", + 5770 => x"c9", + 5771 => x"08", + 5772 => x"38", + 5773 => x"51", + 5774 => x"82", + 5775 => x"56", + 5776 => x"08", + 5777 => x"81", + 5778 => x"82", + 5779 => x"34", + 5780 => x"e3", + 5781 => x"c8", + 5782 => x"09", + 5783 => x"38", + 5784 => x"18", + 5785 => x"82", + 5786 => x"93", + 5787 => x"18", + 5788 => x"18", + 5789 => x"2e", + 5790 => x"78", + 5791 => x"ea", + 5792 => x"31", + 5793 => x"1a", + 5794 => x"90", + 5795 => x"81", + 5796 => x"06", + 5797 => x"58", + 5798 => x"9a", + 5799 => x"76", + 5800 => x"3f", + 5801 => x"08", + 5802 => x"c8", + 5803 => x"82", + 5804 => x"58", + 5805 => x"52", + 5806 => x"ae", + 5807 => x"c8", + 5808 => x"ff", + 5809 => x"38", + 5810 => x"8a", + 5811 => x"98", + 5812 => x"26", + 5813 => x"0b", + 5814 => x"82", + 5815 => x"39", + 5816 => x"0c", + 5817 => x"ff", + 5818 => x"17", + 5819 => x"18", + 5820 => x"ff", + 5821 => x"80", + 5822 => x"75", + 5823 => x"c1", + 5824 => x"93", + 5825 => x"38", + 5826 => x"18", + 5827 => x"81", + 5828 => x"89", + 5829 => x"c8", + 5830 => x"8c", + 5831 => x"18", + 5832 => x"38", + 5833 => x"8c", + 5834 => x"17", + 5835 => x"07", + 5836 => x"18", + 5837 => x"08", + 5838 => x"55", + 5839 => x"80", + 5840 => x"17", + 5841 => x"80", + 5842 => x"17", + 5843 => x"2b", + 5844 => x"80", + 5845 => x"81", + 5846 => x"08", + 5847 => x"52", + 5848 => x"33", + 5849 => x"b8", + 5850 => x"93", + 5851 => x"2e", + 5852 => x"0b", + 5853 => x"81", + 5854 => x"90", + 5855 => x"ff", + 5856 => x"90", + 5857 => x"54", + 5858 => x"17", + 5859 => x"11", + 5860 => x"ff", + 5861 => x"82", + 5862 => x"80", + 5863 => x"81", + 5864 => x"34", + 5865 => x"39", + 5866 => x"18", + 5867 => x"87", + 5868 => x"18", + 5869 => x"74", + 5870 => x"0c", + 5871 => x"04", + 5872 => x"79", + 5873 => x"75", + 5874 => x"8f", + 5875 => x"89", + 5876 => x"52", + 5877 => x"05", + 5878 => x"3f", + 5879 => x"08", + 5880 => x"c8", + 5881 => x"38", + 5882 => x"7a", + 5883 => x"d8", + 5884 => x"93", + 5885 => x"82", + 5886 => x"80", + 5887 => x"16", + 5888 => x"2b", + 5889 => x"74", + 5890 => x"86", + 5891 => x"84", + 5892 => x"06", + 5893 => x"73", + 5894 => x"38", + 5895 => x"52", + 5896 => x"c4", + 5897 => x"c8", + 5898 => x"0c", + 5899 => x"55", + 5900 => x"77", + 5901 => x"22", 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x"51", + 5961 => x"82", + 5962 => x"55", + 5963 => x"08", + 5964 => x"80", + 5965 => x"70", + 5966 => x"57", + 5967 => x"85", + 5968 => x"90", + 5969 => x"2e", + 5970 => x"52", + 5971 => x"05", + 5972 => x"3f", + 5973 => x"c8", + 5974 => x"0d", + 5975 => x"0d", + 5976 => x"5a", + 5977 => x"3d", + 5978 => x"91", + 5979 => x"ef", + 5980 => x"c8", + 5981 => x"93", + 5982 => x"84", + 5983 => x"0c", + 5984 => x"11", + 5985 => x"55", + 5986 => x"08", + 5987 => x"38", + 5988 => x"7a", + 5989 => x"39", + 5990 => x"cf", + 5991 => x"81", + 5992 => x"7b", + 5993 => x"56", + 5994 => x"2e", + 5995 => x"80", + 5996 => x"75", + 5997 => x"52", + 5998 => x"05", + 5999 => x"aa", + 6000 => x"c8", + 6001 => x"d0", + 6002 => x"c8", + 6003 => x"cd", + 6004 => x"c8", + 6005 => x"82", + 6006 => x"07", + 6007 => x"05", + 6008 => x"53", + 6009 => x"98", + 6010 => x"26", + 6011 => x"fb", + 6012 => x"11", + 6013 => x"08", + 6014 => x"80", + 6015 => x"38", + 6016 => x"18", + 6017 => x"ff", + 6018 => x"82", + 6019 => x"59", + 6020 => x"08", + 6021 => x"7a", + 6022 => x"54", + 6023 => x"09", + 6024 => x"38", + 6025 => x"05", + 6026 => x"f0", + 6027 => x"c8", + 6028 => x"ff", + 6029 => x"70", + 6030 => x"82", + 6031 => x"51", + 6032 => x"7a", + 6033 => x"51", + 6034 => x"3f", + 6035 => x"08", + 6036 => x"70", + 6037 => x"25", + 6038 => x"58", + 6039 => x"74", + 6040 => x"ff", + 6041 => x"75", + 6042 => x"76", + 6043 => x"77", + 6044 => x"54", + 6045 => x"33", + 6046 => x"55", + 6047 => x"34", + 6048 => x"c8", + 6049 => x"0d", + 6050 => x"0d", + 6051 => x"fc", + 6052 => x"52", + 6053 => x"3f", + 6054 => x"08", + 6055 => x"c8", + 6056 => x"91", + 6057 => x"76", + 6058 => x"38", + 6059 => x"dc", + 6060 => x"33", + 6061 => x"70", + 6062 => x"56", + 6063 => x"74", + 6064 => x"c8", + 6065 => x"08", + 6066 => x"27", + 6067 => x"94", + 6068 => x"38", + 6069 => x"18", + 6070 => x"51", + 6071 => x"3f", + 6072 => x"08", + 6073 => x"88", + 6074 => x"ca", + 6075 => x"08", + 6076 => x"ff", + 6077 => x"82", + 6078 => x"82", + 6079 => x"ff", + 6080 => x"70", + 6081 => x"25", + 6082 => x"56", + 6083 => x"08", + 6084 => x"81", + 6085 => x"82", + 6086 => x"38", + 6087 => x"98", + 6088 => x"92", + 6089 => x"08", + 6090 => x"77", + 6091 => x"fe", + 6092 => x"c8", + 6093 => x"18", + 6094 => x"0c", + 6095 => x"80", + 6096 => x"74", + 6097 => x"76", + 6098 => x"98", + 6099 => x"80", + 6100 => x"81", + 6101 => x"08", + 6102 => x"52", + 6103 => x"33", + 6104 => x"b0", + 6105 => x"93", + 6106 => x"2e", + 6107 => x"57", + 6108 => x"18", + 6109 => x"06", + 6110 => x"19", + 6111 => x"2e", + 6112 => x"91", + 6113 => x"56", + 6114 => x"56", + 6115 => x"c8", + 6116 => x"0d", + 6117 => x"0d", + 6118 => x"51", + 6119 => x"3f", + 6120 => x"3d", + 6121 => x"52", + 6122 => x"d6", + 6123 => x"93", + 6124 => x"82", + 6125 => x"82", + 6126 => x"fb", + 6127 => x"96", + 6128 => x"44", + 6129 => x"3d", + 6130 => x"d0", + 6131 => x"93", + 6132 => x"fb", + 6133 => x"ff", + 6134 => x"75", + 6135 => x"02", + 6136 => x"33", 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x"80", + 6196 => x"70", + 6197 => x"2a", + 6198 => x"57", + 6199 => x"74", + 6200 => x"38", + 6201 => x"51", + 6202 => x"3f", + 6203 => x"52", + 6204 => x"05", + 6205 => x"b6", + 6206 => x"c8", + 6207 => x"8c", + 6208 => x"ff", + 6209 => x"82", + 6210 => x"56", + 6211 => x"51", + 6212 => x"3f", + 6213 => x"c8", + 6214 => x"0d", + 6215 => x"0d", + 6216 => x"3d", + 6217 => x"99", + 6218 => x"b3", + 6219 => x"c8", + 6220 => x"93", + 6221 => x"b5", + 6222 => x"68", + 6223 => x"d4", + 6224 => x"cb", + 6225 => x"c8", + 6226 => x"93", + 6227 => x"38", + 6228 => x"84", + 6229 => x"06", + 6230 => x"02", + 6231 => x"33", + 6232 => x"70", + 6233 => x"55", + 6234 => x"2e", + 6235 => x"55", + 6236 => x"09", + 6237 => x"f5", + 6238 => x"80", + 6239 => x"c4", + 6240 => x"ba", + 6241 => x"93", + 6242 => x"80", + 6243 => x"c8", + 6244 => x"09", + 6245 => x"38", + 6246 => x"81", + 6247 => x"06", + 6248 => x"55", + 6249 => x"09", + 6250 => x"38", + 6251 => x"88", + 6252 => x"74", + 6253 => x"75", + 6254 => x"ff", + 6255 => x"82", + 6256 => x"55", + 6257 => x"08", + 6258 => x"8b", + 6259 => x"b4", + 6260 => x"af", + 6261 => x"54", + 6262 => x"15", + 6263 => x"90", + 6264 => x"34", + 6265 => x"ca", + 6266 => x"af", + 6267 => x"53", + 6268 => x"77", + 6269 => x"3f", + 6270 => x"18", + 6271 => x"18", + 6272 => x"a7", + 6273 => x"ae", + 6274 => x"15", + 6275 => x"80", + 6276 => x"77", + 6277 => x"3f", + 6278 => x"0b", + 6279 => x"98", + 6280 => x"51", + 6281 => x"82", + 6282 => x"55", + 6283 => x"08", + 6284 => x"52", + 6285 => x"51", + 6286 => x"3f", + 6287 => x"52", + 6288 => x"dd", + 6289 => x"90", + 6290 => x"34", + 6291 => x"0b", + 6292 => x"77", + 6293 => x"b9", + 6294 => x"c8", + 6295 => x"39", + 6296 => x"52", + 6297 => x"05", + 6298 => x"c2", + 6299 => x"93", + 6300 => x"3d", + 6301 => x"3d", + 6302 => x"84", + 6303 => x"c8", + 6304 => x"a7", + 6305 => x"05", + 6306 => x"51", + 6307 => x"82", + 6308 => x"55", + 6309 => x"08", + 6310 => x"77", + 6311 => x"08", + 6312 => x"d4", + 6313 => x"e7", + 6314 => x"c8", + 6315 => x"93", + 6316 => x"bd", + 6317 => x"97", + 6318 => x"a0", + 6319 => x"80", + 6320 => x"86", + 6321 => x"a9", + 6322 => x"a3", + 6323 => x"a7", + 6324 => x"05", + 6325 => x"d3", + 6326 => x"a7", + 6327 => x"52", + 6328 => x"52", + 6329 => x"c3", + 6330 => x"08", + 6331 => x"ca", + 6332 => x"93", + 6333 => x"82", + 6334 => x"94", + 6335 => x"2e", + 6336 => x"8a", + 6337 => x"64", + 6338 => x"2e", + 6339 => x"55", + 6340 => x"09", + 6341 => x"b8", + 6342 => x"ff", + 6343 => x"c3", + 6344 => x"93", + 6345 => x"82", + 6346 => x"81", + 6347 => x"56", + 6348 => x"3d", + 6349 => x"52", + 6350 => x"ff", + 6351 => x"02", + 6352 => x"8b", + 6353 => x"16", + 6354 => x"2a", + 6355 => x"51", + 6356 => x"89", + 6357 => x"07", + 6358 => x"17", + 6359 => x"81", + 6360 => x"34", + 6361 => x"70", + 6362 => x"81", + 6363 => x"57", + 6364 => x"80", + 6365 => x"63", + 6366 => x"38", + 6367 => x"51", + 6368 => x"3f", + 6369 => x"08", + 6370 => x"ff", + 6371 => x"82", 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x"0c", + 6431 => x"04", + 6432 => x"65", + 6433 => x"94", + 6434 => x"52", + 6435 => x"cc", + 6436 => x"93", + 6437 => x"82", + 6438 => x"80", + 6439 => x"59", + 6440 => x"3d", + 6441 => x"c6", + 6442 => x"93", + 6443 => x"82", + 6444 => x"bc", + 6445 => x"cb", + 6446 => x"a0", + 6447 => x"80", + 6448 => x"86", + 6449 => x"38", + 6450 => x"84", + 6451 => x"90", + 6452 => x"54", + 6453 => x"96", + 6454 => x"a9", + 6455 => x"54", + 6456 => x"15", + 6457 => x"ff", + 6458 => x"82", + 6459 => x"55", + 6460 => x"c8", + 6461 => x"0d", + 6462 => x"0d", + 6463 => x"59", + 6464 => x"3d", + 6465 => x"99", + 6466 => x"d3", + 6467 => x"c8", + 6468 => x"c8", + 6469 => x"82", + 6470 => x"07", + 6471 => x"30", + 6472 => x"9f", + 6473 => x"52", + 6474 => x"56", + 6475 => x"80", + 6476 => x"5d", + 6477 => x"52", + 6478 => x"52", + 6479 => x"bb", + 6480 => x"c8", + 6481 => x"93", + 6482 => x"ce", + 6483 => x"73", + 6484 => x"fb", + 6485 => x"c8", + 6486 => x"93", + 6487 => x"38", + 6488 => x"08", + 6489 => x"08", + 6490 => x"58", + 6491 => x"18", + 6492 => x"58", + 6493 => x"74", + 6494 => x"58", + 6495 => x"ec", + 6496 => x"54", + 6497 => x"77", + 6498 => x"38", + 6499 => x"11", + 6500 => x"55", + 6501 => x"2e", + 6502 => x"84", + 6503 => x"06", + 6504 => x"79", + 6505 => x"75", + 6506 => x"07", + 6507 => x"30", + 6508 => x"9f", + 6509 => x"52", + 6510 => x"74", + 6511 => x"38", + 6512 => x"08", + 6513 => x"aa", + 6514 => x"93", + 6515 => x"82", + 6516 => x"a7", + 6517 => x"33", + 6518 => x"c3", + 6519 => x"2e", + 6520 => x"e4", + 6521 => x"2e", + 6522 => x"58", + 6523 => x"05", + 6524 => x"c1", + 6525 => x"c8", + 6526 => x"75", + 6527 => x"0c", + 6528 => x"04", + 6529 => x"82", + 6530 => x"ff", + 6531 => x"9b", + 6532 => x"cb", + 6533 => x"c8", + 6534 => x"93", + 6535 => x"c8", + 6536 => x"a0", + 6537 => x"ff", + 6538 => x"ff", + 6539 => x"80", + 6540 => x"33", + 6541 => x"57", + 6542 => x"81", + 6543 => x"33", + 6544 => x"4c", + 6545 => x"06", + 6546 => x"a7", + 6547 => x"93", + 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x"38", + 6666 => x"90", + 6667 => x"33", + 6668 => x"70", + 6669 => x"55", + 6670 => x"38", + 6671 => x"99", + 6672 => x"81", + 6673 => x"57", + 6674 => x"7f", + 6675 => x"70", + 6676 => x"55", + 6677 => x"51", + 6678 => x"dd", + 6679 => x"7b", + 6680 => x"70", + 6681 => x"2a", + 6682 => x"08", + 6683 => x"11", + 6684 => x"40", + 6685 => x"5f", + 6686 => x"88", + 6687 => x"08", + 6688 => x"38", + 6689 => x"79", + 6690 => x"5a", + 6691 => x"51", + 6692 => x"3f", + 6693 => x"08", + 6694 => x"56", + 6695 => x"14", + 6696 => x"83", + 6697 => x"75", + 6698 => x"95", + 6699 => x"2e", + 6700 => x"75", + 6701 => x"1a", + 6702 => x"2e", + 6703 => x"39", + 6704 => x"5a", + 6705 => x"09", + 6706 => x"38", + 6707 => x"81", + 6708 => x"80", + 6709 => x"7c", + 6710 => x"7d", + 6711 => x"38", + 6712 => x"75", + 6713 => x"81", + 6714 => x"ff", + 6715 => x"74", + 6716 => x"ff", + 6717 => x"82", + 6718 => x"57", + 6719 => x"08", + 6720 => x"81", + 6721 => x"58", + 6722 => x"d4", + 6723 => x"ff", + 6724 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7958 => x"52", + 7959 => x"54", + 7960 => x"72", + 7961 => x"30", + 7962 => x"2e", + 7963 => x"41", + 7964 => x"65", + 7965 => x"73", + 7966 => x"20", + 7967 => x"43", + 7968 => x"52", + 7969 => x"74", + 7970 => x"63", + 7971 => x"20", + 7972 => x"72", + 7973 => x"20", + 7974 => x"30", + 7975 => x"00", + 7976 => x"20", + 7977 => x"43", + 7978 => x"4d", + 7979 => x"72", + 7980 => x"74", + 7981 => x"20", + 7982 => x"72", + 7983 => x"20", + 7984 => x"30", + 7985 => x"00", + 7986 => x"20", + 7987 => x"53", + 7988 => x"6b", + 7989 => x"61", + 7990 => x"41", + 7991 => x"65", + 7992 => x"20", + 7993 => x"20", + 7994 => x"30", + 7995 => x"00", + 7996 => x"20", + 7997 => x"5a", + 7998 => x"49", + 7999 => x"20", + 8000 => x"20", + 8001 => x"20", + 8002 => x"20", + 8003 => x"20", + 8004 => x"30", + 8005 => x"00", + 8006 => x"20", + 8007 => x"53", + 8008 => x"65", + 8009 => x"6c", + 8010 => x"20", + 8011 => x"71", + 8012 => x"20", + 8013 => x"20", + 8014 => x"30", + 8015 => x"00", + 8016 => x"53", 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x"b4", + 8076 => x"b8", + 8077 => x"bc", + 8078 => x"c0", + 8079 => x"c4", + 8080 => x"c8", + 8081 => x"cc", + 8082 => x"d0", + 8083 => x"d4", + 8084 => x"d8", + 8085 => x"dc", + 8086 => x"e0", + 8087 => x"e4", + 8088 => x"e8", + 8089 => x"ec", + 8090 => x"f0", + 8091 => x"f4", + 8092 => x"f8", + 8093 => x"fc", + 8094 => x"2b", + 8095 => x"3d", + 8096 => x"5c", + 8097 => x"3c", + 8098 => x"7f", + 8099 => x"00", + 8100 => x"00", + 8101 => x"01", + 8102 => x"00", + 8103 => x"00", + 8104 => x"00", + 8105 => x"00", + 8106 => x"00", + 8107 => x"46", + 8108 => x"32", + 8109 => x"46", + 8110 => x"36", + 8111 => x"65", + 8112 => x"54", + 8113 => x"44", + 8114 => x"20", + 8115 => x"43", + 8116 => x"52", + 8117 => x"00", + 8118 => x"44", + 8119 => x"20", + 8120 => x"46", + 8121 => x"43", + 8122 => x"52", + 8123 => x"00", + 8124 => x"46", + 8125 => x"53", + 8126 => x"45", + 8127 => x"4f", + 8128 => x"4f", + 8129 => x"4d", + 8130 => x"52", + 8131 => x"48", + 8132 => x"57", + 8133 => x"00", + 8134 => x"54", + 8135 => x"49", + 8136 => x"45", + 8137 => x"55", + 8138 => x"4e", + 8139 => x"4d", + 8140 => x"20", + 8141 => x"4d", + 8142 => x"53", + 8143 => x"64", + 8144 => x"70", + 8145 => x"64", + 8146 => x"74", + 8147 => x"64", + 8148 => x"74", + 8149 => x"64", + 8150 => x"74", + 8151 => x"62", + 8152 => x"70", + 8153 => x"62", + 8154 => x"74", + 8155 => x"62", + 8156 => x"64", + 8157 => x"62", + 8158 => x"74", + 8159 => x"62", + 8160 => x"6c", + 8161 => x"62", + 8162 => x"00", + 8163 => x"66", + 8164 => x"74", + 8165 => x"66", + 8166 => x"6e", + 8167 => x"66", + 8168 => x"73", + 8169 => x"66", + 8170 => x"6b", + 8171 => x"66", + 8172 => x"64", + 8173 => x"66", + 8174 => x"70", + 8175 => x"00", + 8176 => x"66", + 8177 => x"74", + 8178 => x"66", + 8179 => x"6e", + 8180 => x"66", + 8181 => x"6f", + 8182 => x"66", + 8183 => x"72", + 8184 => x"66", + 8185 => x"65", + 8186 => x"66", + 8187 => x"61", + 8188 => x"66", + 8189 => x"00", + 8190 => x"66", + 8191 => x"69", + 8192 => x"66", + 8193 => x"74", + 8194 => x"66", + 8195 => x"00", + 8196 => x"66", + 8197 => x"00", + 8198 => x"66", + 8199 => x"66", + 8200 => x"63", + 8201 => x"66", + 8202 => x"61", + 8203 => x"66", + 8204 => x"64", + 8205 => x"66", + 8206 => x"63", + 8207 => x"66", + 8208 => x"65", + 8209 => x"66", + 8210 => x"70", + 8211 => x"66", + 8212 => x"66", + 8213 => x"76", + 8214 => x"66", + 8215 => x"77", + 8216 => x"00", + 8217 => x"66", + 8218 => x"65", + 8219 => x"66", + 8220 => x"73", + 8221 => x"6d", + 8222 => x"00", + 8223 => x"6d", + 8224 => x"70", + 8225 => x"6d", + 8226 => x"6d", + 8227 => x"6d", + 8228 => x"68", + 8229 => x"68", + 8230 => x"68", + 8231 => x"68", + 8232 => x"68", + 8233 => x"68", + 8234 => x"64", + 8235 => x"00", + 8236 => x"63", + 8237 => x"6d", + 8238 => x"00", + 8239 => x"63", + 8240 => x"00", + 8241 => x"6a", + 8242 => x"72", + 8243 => x"61", + 8244 => x"72", + 8245 => x"74", + 8246 => x"68", + 8247 => x"00", + 8248 => x"69", + 8249 => x"00", + 8250 => x"74", + 8251 => x"00", + 8252 => x"74", + 8253 => x"00", + 8254 => x"44", + 8255 => x"20", + 8256 => x"6f", + 8257 => x"49", + 8258 => x"72", + 8259 => x"20", + 8260 => x"6f", + 8261 => x"00", + 8262 => x"44", + 8263 => x"20", + 8264 => x"20", + 8265 => x"64", + 8266 => x"00", + 8267 => x"4e", + 8268 => x"69", + 8269 => x"66", + 8270 => x"64", + 8271 => x"4e", + 8272 => x"61", + 8273 => x"66", + 8274 => x"64", + 8275 => x"49", + 8276 => x"6c", + 8277 => x"66", + 8278 => x"6e", + 8279 => x"2e", + 8280 => x"41", + 8281 => x"73", + 8282 => x"65", + 8283 => x"64", + 8284 => x"46", + 8285 => x"20", + 8286 => x"65", + 8287 => x"20", + 8288 => x"73", + 8289 => x"0a", + 8290 => x"46", + 8291 => x"20", + 8292 => x"64", + 8293 => x"69", + 8294 => x"6c", + 8295 => x"0a", + 8296 => x"53", + 8297 => x"73", + 8298 => x"69", + 8299 => x"70", + 8300 => x"65", + 8301 => x"64", + 8302 => x"44", + 8303 => x"65", + 8304 => x"6d", + 8305 => x"20", + 8306 => x"69", + 8307 => x"6c", + 8308 => x"0a", + 8309 => x"44", + 8310 => x"20", + 8311 => x"20", + 8312 => x"62", + 8313 => x"2e", + 8314 => x"4e", + 8315 => x"6f", + 8316 => x"74", + 8317 => x"65", + 8318 => x"6c", + 8319 => x"73", + 8320 => x"20", + 8321 => x"6e", + 8322 => x"6e", + 8323 => x"73", + 8324 => x"00", + 8325 => x"46", + 8326 => x"61", + 8327 => x"62", + 8328 => x"65", + 8329 => x"00", + 8330 => x"54", + 8331 => x"6f", + 8332 => x"20", + 8333 => x"72", + 8334 => x"6f", + 8335 => x"61", + 8336 => x"6c", + 8337 => x"2e", + 8338 => x"46", + 8339 => x"20", + 8340 => x"6c", + 8341 => x"65", + 8342 => x"00", + 8343 => x"49", + 8344 => x"66", + 8345 => x"69", + 8346 => x"20", + 8347 => x"6f", + 8348 => x"0a", + 8349 => x"54", + 8350 => x"6d", + 8351 => x"20", + 8352 => x"6e", + 8353 => x"6c", + 8354 => x"0a", + 8355 => x"50", + 8356 => x"6d", + 8357 => x"72", + 8358 => x"6e", + 8359 => x"72", + 8360 => x"2e", + 8361 => x"53", + 8362 => x"65", + 8363 => x"0a", + 8364 => x"55", + 8365 => x"6f", + 8366 => x"65", + 8367 => x"72", + 8368 => x"0a", + 8369 => x"20", + 8370 => x"65", + 8371 => x"73", + 8372 => x"20", + 8373 => x"20", + 8374 => x"65", + 8375 => x"65", + 8376 => x"00", + 8377 => x"72", + 8378 => x"00", + 8379 => x"5a", + 8380 => x"41", + 8381 => x"0a", + 8382 => x"25", + 8383 => x"00", + 8384 => x"31", + 8385 => x"37", + 8386 => x"31", + 8387 => x"76", + 8388 => x"00", + 8389 => x"20", + 8390 => x"2c", + 8391 => x"76", + 8392 => x"32", + 8393 => x"25", + 8394 => x"73", + 8395 => x"0a", + 8396 => x"5a", + 8397 => x"41", + 8398 => x"74", + 8399 => x"75", + 8400 => x"48", + 8401 => x"6c", + 8402 => x"00", + 8403 => x"54", + 8404 => x"72", + 8405 => x"74", + 8406 => x"75", + 8407 => x"00", + 8408 => x"50", + 8409 => x"69", + 8410 => x"72", + 8411 => x"74", + 8412 => x"49", + 8413 => x"4c", + 8414 => x"20", + 8415 => x"65", + 8416 => x"70", + 8417 => x"49", + 8418 => x"4c", + 8419 => x"20", + 8420 => x"65", + 8421 => x"70", + 8422 => x"55", + 8423 => x"30", + 8424 => x"20", + 8425 => x"65", + 8426 => x"70", + 8427 => x"55", + 8428 => x"30", + 8429 => x"20", + 8430 => x"65", + 8431 => x"70", + 8432 => x"55", + 8433 => x"31", + 8434 => x"20", + 8435 => x"65", + 8436 => x"70", + 8437 => x"55", + 8438 => x"31", + 8439 => x"20", + 8440 => x"65", + 8441 => x"70", + 8442 => x"53", + 8443 => x"69", + 8444 => x"75", + 8445 => x"69", + 8446 => x"2e", + 8447 => x"00", + 8448 => x"45", + 8449 => x"6c", + 8450 => x"20", + 8451 => x"65", + 8452 => x"2e", + 8453 => x"30", + 8454 => x"46", + 8455 => x"65", + 8456 => x"6f", + 8457 => x"69", + 8458 => x"6c", + 8459 => x"20", + 8460 => x"63", + 8461 => x"20", + 8462 => x"70", + 8463 => x"73", + 8464 => x"6e", + 8465 => x"6d", + 8466 => x"61", + 8467 => x"2e", + 8468 => x"2a", + 8469 => x"42", + 8470 => x"64", + 8471 => x"20", + 8472 => x"0a", + 8473 => x"49", + 8474 => x"69", + 8475 => x"73", + 8476 => x"0a", + 8477 => x"46", + 8478 => x"65", + 8479 => x"6f", + 8480 => x"69", + 8481 => x"6c", + 8482 => x"2e", + 8483 => x"72", + 8484 => x"64", + 8485 => x"25", + 8486 => x"44", + 8487 => x"62", + 8488 => x"67", + 8489 => x"74", + 8490 => x"75", + 8491 => x"0a", + 8492 => x"45", + 8493 => x"6c", + 8494 => x"20", + 8495 => x"65", + 8496 => x"70", + 8497 => x"00", + 8498 => x"44", + 8499 => x"62", + 8500 => x"20", + 8501 => x"74", + 8502 => x"66", + 8503 => x"45", + 8504 => x"6c", + 8505 => x"20", + 8506 => x"74", + 8507 => x"66", + 8508 => x"45", + 8509 => x"75", + 8510 => x"67", + 8511 => x"64", + 8512 => x"20", + 8513 => x"78", + 8514 => x"2e", + 8515 => x"43", + 8516 => x"69", + 8517 => x"63", + 8518 => x"20", + 8519 => x"30", + 8520 => x"2e", + 8521 => x"00", + 8522 => x"43", + 8523 => x"20", + 8524 => x"75", + 8525 => x"64", + 8526 => x"64", + 8527 => x"25", + 8528 => x"0a", + 8529 => x"52", + 8530 => x"61", + 8531 => x"6e", + 8532 => x"70", + 8533 => x"63", + 8534 => x"6f", + 8535 => x"2e", + 8536 => x"43", + 8537 => x"20", + 8538 => x"6f", + 8539 => x"6e", + 8540 => x"2e", + 8541 => x"5a", + 8542 => x"62", + 8543 => x"25", + 8544 => x"25", + 8545 => x"73", + 8546 => x"00", + 8547 => x"42", + 8548 => x"63", + 8549 => x"61", + 8550 => x"0a", + 8551 => x"52", + 8552 => x"69", + 8553 => x"2e", + 8554 => x"45", + 8555 => x"6c", + 8556 => x"20", + 8557 => x"65", + 8558 => x"70", + 8559 => x"2e", + 8560 => x"00", + 8561 => x"00", + 8562 => x"00", + 8563 => x"00", + 8564 => x"00", + 8565 => x"00", + 8566 => x"00", + 8567 => x"00", + 8568 => x"00", + 8569 => x"00", + 8570 => x"00", + 8571 => x"05", + 8572 => x"00", + 8573 => x"01", + 8574 => x"80", + 8575 => x"01", + 8576 => x"00", + 8577 => x"01", + 8578 => x"00", + 8579 => x"00", + 8580 => x"00", + 8581 => x"00", + 8582 => x"00", + 8583 => x"01", + 8584 => x"00", + 8585 => x"00", + 8586 => x"00", + 8587 => x"00", + 8588 => x"00", + 8589 => x"00", + 8590 => x"00", + 8591 => x"01", + 8592 => x"00", + 8593 => x"00", + 8594 => x"00", + 8595 => x"00", + 8596 => x"00", + 8597 => x"00", + 8598 => x"00", + 8599 => x"00", + 8600 => x"00", + 8601 => x"00", + 8602 => x"00", + 8603 => x"00", + 8604 => x"00", + 8605 => x"00", + 8606 => x"00", + 8607 => x"00", + 8608 => x"00", + 8609 => x"00", + 8610 => x"00", + 8611 => x"00", + 8612 => x"00", + 8613 => x"00", + 8614 => x"00", + 8615 => x"00", + 8616 => x"00", + 8617 => x"00", + 8618 => x"00", + 8619 => x"01", + 8620 => x"00", + 8621 => x"00", + 8622 => x"00", + 8623 => x"00", + 8624 => x"00", + 8625 => x"00", + 8626 => x"00", + 8627 => x"00", + 8628 => x"00", + 8629 => x"00", + 8630 => x"00", + 8631 => x"00", + 8632 => x"00", + 8633 => x"00", + 8634 => x"00", + 8635 => x"00", + 8636 => x"00", + 8637 => x"00", + 8638 => x"00", + 8639 => x"00", + 8640 => x"00", + 8641 => x"00", + 8642 => x"00", + 8643 => x"00", + 8644 => x"00", + 8645 => x"00", + 8646 => x"00", + 8647 => x"00", + 8648 => x"00", + 8649 => x"00", + 8650 => x"00", + 8651 => x"00", + 8652 => x"00", + 8653 => x"00", + 8654 => x"00", + 8655 => x"00", + 8656 => x"00", + 8657 => x"00", + 8658 => x"00", + 8659 => x"00", + 8660 => x"00", + 8661 => x"00", + 8662 => x"00", + 8663 => x"00", + 8664 => x"00", + 8665 => x"00", + 8666 => x"00", + 8667 => x"00", + 8668 => x"00", + 8669 => x"00", + 8670 => x"00", + 8671 => x"00", + 8672 => x"00", + 8673 => x"00", + 8674 => x"00", + 8675 => x"00", + 8676 => x"00", + 8677 => x"00", + 8678 => x"00", + 8679 => x"00", + 8680 => x"00", + 8681 => x"00", + 8682 => x"00", + 8683 => x"00", + 8684 => x"00", + 8685 => x"00", + 8686 => x"00", + 8687 => x"00", + 8688 => x"00", + 8689 => x"00", + 8690 => x"00", + 8691 => x"00", + 8692 => x"00", + 8693 => x"00", + 8694 => x"00", + 8695 => x"00", + 8696 => x"00", + 8697 => x"00", + 8698 => x"00", + 8699 => x"01", + 8700 => x"00", + 8701 => x"00", + 8702 => x"00", + 8703 => x"01", + 8704 => x"00", + 8705 => x"00", + 8706 => x"00", + 8707 => x"00", + 8708 => x"00", + 8709 => x"00", + 8710 => x"00", + 8711 => x"00", + 8712 => x"00", + 8713 => x"00", + 8714 => x"00", + 8715 => x"00", + 8716 => x"00", + 8717 => x"00", + 8718 => x"00", + 8719 => x"00", + 8720 => x"00", + 8721 => x"00", + 8722 => x"00", + 8723 => x"00", + 8724 => x"00", + 8725 => x"00", + 8726 => x"00", + 8727 => x"00", + 8728 => x"00", + 8729 => x"00", + 8730 => x"00", + 8731 => x"00", + 8732 => x"00", + 8733 => x"00", + 8734 => x"00", + 8735 => x"00", + 8736 => x"00", + 8737 => x"00", + 8738 => x"00", + 8739 => x"00", + 8740 => x"00", + 8741 => x"00", + 8742 => x"00", + 8743 => x"00", + 8744 => x"00", + 8745 => x"00", + 8746 => x"00", + 8747 => x"00", + 8748 => x"00", + 8749 => x"00", + 8750 => x"00", + 8751 => x"00", + 8752 => x"00", + 8753 => x"00", + 8754 => x"00", + 8755 => x"01", + 8756 => x"00", + 8757 => x"00", + 8758 => x"00", + 8759 => x"01", + 8760 => x"00", + 8761 => x"00", + 8762 => x"00", + 8763 => x"00", + 8764 => x"00", + 8765 => x"00", + 8766 => x"00", + 8767 => x"00", + 8768 => x"00", + 8769 => x"00", + 8770 => x"00", + 8771 => x"01", + 8772 => x"00", + 8773 => x"00", + 8774 => x"00", + 8775 => x"01", + 8776 => x"00", + 8777 => x"00", + 8778 => x"00", + 8779 => x"00", + 8780 => x"00", + 8781 => x"00", + 8782 => x"00", + 8783 => x"00", + 8784 => x"00", + 8785 => x"00", + 8786 => x"00", + 8787 => x"01", + 8788 => x"00", + 8789 => x"00", + 8790 => x"00", + 8791 => x"01", + 8792 => x"00", + 8793 => x"00", + 8794 => x"00", + 8795 => x"01", + 8796 => x"00", + 8797 => x"00", + 8798 => x"00", + 8799 => x"01", + 8800 => x"00", + 8801 => x"00", + 8802 => x"00", + 8803 => x"00", + 8804 => x"00", + 8805 => x"00", + 8806 => x"00", + 8807 => x"01", + 8808 => x"00", + 8809 => x"00", + 8810 => x"00", + 8811 => x"00", + 8812 => x"00", + 8813 => x"00", + 8814 => x"00", + 8815 => x"01", + 8816 => x"00", + 8817 => x"00", + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 0 - Port B - bits 7 downto 0 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM0(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(7 downto 0); + memBRead(7 downto 0) <= memBWrite(7 downto 0); + else + memBRead(7 downto 0) <= RAM0(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 1 - Port B - bits 15 downto 8 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM1(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(15 downto 8); + memBRead(15 downto 8) <= memBWrite(15 downto 8); + else + memBRead(15 downto 8) <= RAM1(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 2 - Port B - bits 23 downto 16 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM2(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(23 downto 16); + memBRead(23 downto 16) <= memBWrite(23 downto 16); + else + memBRead(23 downto 16) <= RAM2(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 3 - Port B - bits 31 downto 24 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM3(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(31 downto 24); + memBRead(31 downto 24) <= memBWrite(31 downto 24); + else + memBRead(31 downto 24) <= RAM3(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + +end arch; diff --git a/zpu/devices/sysbus/BRAM/IOCP_ZPUTA_SinglePortBRAM.vhd b/zpu/devices/sysbus/BRAM/IOCP_ZPUTA_SinglePortBRAM.vhd new file mode 100644 index 0000000..0fb02ea --- /dev/null +++ b/zpu/devices/sysbus/BRAM/IOCP_ZPUTA_SinglePortBRAM.vhd @@ -0,0 +1,26027 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity SinglePortBRAM is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end SinglePortBRAM; + +architecture arch of SinglePortBRAM is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + 0 => x"84", + 1 => x"0b", + 2 => x"04", + 3 => x"ff", + 4 => x"ff", + 5 => x"ff", + 6 => x"ff", + 7 => x"ff", + 8 => x"84", + 9 => x"0b", + 10 => x"04", + 11 => x"84", + 12 => x"0b", + 13 => x"04", + 14 => x"84", + 15 => x"0b", + 16 => x"04", + 17 => x"84", + 18 => x"0b", + 19 => x"04", + 20 => x"84", + 21 => x"0b", + 22 => x"04", + 23 => x"85", + 24 => x"0b", + 25 => x"04", + 26 => x"85", + 27 => x"0b", + 28 => x"04", + 29 => x"85", + 30 => x"0b", + 31 => x"04", + 32 => x"86", + 33 => x"0b", + 34 => x"04", + 35 => x"86", + 36 => x"0b", + 37 => x"04", + 38 => x"86", + 39 => x"0b", + 40 => x"04", + 41 => x"86", + 42 => x"0b", + 43 => x"04", + 44 => x"87", + 45 => x"0b", + 46 => x"04", + 47 => x"87", + 48 => x"0b", + 49 => x"04", + 50 => x"87", + 51 => x"0b", + 52 => x"04", + 53 => x"87", + 54 => x"0b", + 55 => x"04", + 56 => x"88", + 57 => x"0b", + 58 => x"04", + 59 => x"88", + 60 => x"0b", + 61 => x"04", + 62 => x"88", + 63 => x"0b", + 64 => x"04", + 65 => x"88", + 66 => x"0b", + 67 => x"04", + 68 => x"89", + 69 => x"0b", + 70 => x"04", + 71 => x"89", + 72 => x"0b", + 73 => x"04", + 74 => x"89", + 75 => x"0b", + 76 => x"04", + 77 => x"8a", + 78 => x"0b", + 79 => x"04", + 80 => x"8a", + 81 => x"0b", + 82 => x"04", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"00", + 89 => x"00", + 90 => x"00", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"00", + 97 => x"00", + 98 => x"00", + 99 => x"00", + 100 => x"00", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"00", + 105 => x"00", + 106 => x"00", + 107 => x"00", + 108 => x"00", + 109 => x"00", + 110 => x"00", + 111 => x"00", + 112 => x"00", + 113 => x"00", + 114 => x"00", + 115 => x"00", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"00", + 121 => x"00", + 122 => x"00", + 123 => x"00", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"80", + 129 => x"94", + 130 => x"8f", + 131 => x"94", + 132 => x"80", + 133 => x"ca", + 134 => x"9f", + 135 => x"ca", + 136 => x"c0", + 137 => x"91", + 138 => x"90", + 139 => x"91", + 140 => x"88", + 141 => x"04", + 142 => x"0c", + 143 => x"2d", + 144 => x"08", + 145 => x"90", + 146 => x"94", + 147 => x"da", + 148 => x"94", + 149 => x"80", + 150 => x"ca", + 151 => x"a7", + 152 => x"ca", + 153 => x"c0", + 154 => x"91", + 155 => x"90", + 156 => x"91", + 157 => x"88", + 158 => x"04", + 159 => x"0c", + 160 => x"2d", + 161 => x"08", + 162 => x"90", + 163 => x"94", + 164 => x"e7", + 165 => x"94", + 166 => x"80", + 167 => x"ca", + 168 => x"a6", + 169 => x"ca", + 170 => x"c0", + 171 => x"91", + 172 => x"90", + 173 => x"91", + 174 => x"88", + 175 => x"04", + 176 => x"0c", + 177 => x"2d", + 178 => x"08", + 179 => x"90", + 180 => x"94", + 181 => x"9c", + 182 => x"94", + 183 => x"80", + 184 => x"ca", + 185 => x"97", + 186 => x"ca", + 187 => x"c0", + 188 => x"91", + 189 => x"90", + 190 => x"91", + 191 => x"88", + 192 => x"04", + 193 => x"0c", + 194 => x"2d", + 195 => x"08", + 196 => x"90", + 197 => x"94", + 198 => x"f1", + 199 => x"94", + 200 => x"80", + 201 => x"ca", + 202 => x"dc", + 203 => x"ca", + 204 => x"c0", + 205 => x"91", + 206 => x"90", + 207 => x"91", + 208 => x"88", + 209 => x"04", + 210 => x"0c", + 211 => x"2d", + 212 => x"08", + 213 => x"90", + 214 => x"94", + 215 => x"fe", + 216 => x"94", + 217 => x"80", + 218 => x"ca", + 219 => x"ee", + 220 => x"ca", + 221 => x"c0", + 222 => x"91", + 223 => x"90", + 224 => x"91", + 225 => x"88", + 226 => x"04", + 227 => x"0c", + 228 => x"2d", + 229 => x"08", + 230 => x"90", + 231 => x"94", + 232 => x"bb", + 233 => x"94", + 234 => x"80", + 235 => x"ca", + 236 => x"f2", + 237 => x"ca", + 238 => x"c0", + 239 => x"91", + 240 => x"90", + 241 => x"91", + 242 => x"88", + 243 => x"04", + 244 => x"0c", + 245 => x"2d", + 246 => x"08", + 247 => x"90", + 248 => x"94", + 249 => x"c9", + 250 => x"94", + 251 => x"80", + 252 => x"ca", + 253 => x"fd", + 254 => x"ca", + 255 => x"c0", + 256 => x"91", + 257 => x"90", + 258 => x"91", + 259 => x"88", + 260 => x"04", + 261 => x"0c", + 262 => x"2d", + 263 => x"08", + 264 => x"90", + 265 => x"94", + 266 => x"b8", + 267 => x"94", + 268 => x"80", + 269 => x"ca", + 270 => x"e9", + 271 => x"ca", + 272 => x"c0", + 273 => x"91", + 274 => x"90", + 275 => x"91", + 276 => x"88", + 277 => x"04", + 278 => x"0c", + 279 => x"2d", + 280 => x"08", + 281 => x"90", + 282 => x"94", + 283 => x"d4", + 284 => x"94", + 285 => x"80", + 286 => x"ca", + 287 => x"82", + 288 => x"ca", + 289 => x"c0", + 290 => x"91", + 291 => x"91", + 292 => x"91", + 293 => x"88", + 294 => x"04", + 295 => x"0c", + 296 => x"2d", + 297 => x"08", + 298 => x"90", + 299 => x"94", + 300 => x"bb", + 301 => x"94", + 302 => x"80", + 303 => x"ca", + 304 => x"8a", + 305 => x"ca", + 306 => x"c0", + 307 => x"91", + 308 => x"90", + 309 => x"91", + 310 => x"88", + 311 => x"04", + 312 => x"0c", + 313 => x"2d", + 314 => x"08", + 315 => x"90", + 316 => x"94", + 317 => x"c4", + 318 => x"94", + 319 => x"80", + 320 => x"ca", + 321 => x"90", + 322 => x"ca", + 323 => x"c0", + 324 => x"91", + 325 => x"90", + 326 => x"91", + 327 => x"88", + 328 => x"04", + 329 => x"0c", + 330 => x"2d", + 331 => x"08", + 332 => x"90", + 333 => x"94", + 334 => x"82", + 335 => x"94", + 336 => x"80", + 337 => x"ca", + 338 => x"e1", + 339 => x"38", + 340 => x"84", + 341 => x"0b", + 342 => x"c9", + 343 => x"80", + 344 => x"c5", + 345 => x"91", + 346 => x"02", + 347 => x"0c", + 348 => x"80", + 349 => x"94", + 350 => x"08", + 351 => x"94", + 352 => x"08", + 353 => x"3f", + 354 => x"08", + 355 => x"88", + 356 => x"3d", + 357 => x"94", + 358 => x"ca", + 359 => x"91", + 360 => x"fd", + 361 => x"53", + 362 => x"08", + 363 => x"52", + 364 => x"08", + 365 => x"51", + 366 => x"ca", + 367 => x"91", + 368 => x"54", + 369 => x"91", + 370 => x"04", + 371 => x"08", + 372 => x"94", + 373 => x"0d", + 374 => x"ca", + 375 => x"05", + 376 => x"91", + 377 => x"f8", + 378 => x"ca", + 379 => x"05", + 380 => x"94", + 381 => x"08", + 382 => x"91", + 383 => x"fc", + 384 => x"2e", + 385 => x"0b", + 386 => x"08", + 387 => x"24", + 388 => x"ca", + 389 => x"05", + 390 => x"ca", + 391 => x"05", + 392 => x"94", + 393 => x"08", + 394 => x"94", + 395 => x"0c", + 396 => x"91", + 397 => x"fc", + 398 => x"2e", + 399 => x"91", + 400 => x"8c", + 401 => x"ca", + 402 => x"05", + 403 => x"38", + 404 => x"08", + 405 => x"91", + 406 => x"8c", + 407 => x"91", + 408 => x"88", + 409 => x"ca", + 410 => x"05", + 411 => x"94", + 412 => x"08", + 413 => x"94", + 414 => x"0c", + 415 => x"08", + 416 => x"81", + 417 => x"94", + 418 => x"0c", + 419 => x"08", + 420 => x"81", + 421 => x"94", + 422 => x"0c", + 423 => x"91", + 424 => x"90", + 425 => x"2e", + 426 => x"ca", + 427 => x"05", + 428 => x"ca", + 429 => x"05", + 430 => x"39", + 431 => x"08", + 432 => x"70", + 433 => x"08", + 434 => x"51", + 435 => x"08", + 436 => x"91", + 437 => x"85", + 438 => x"ca", + 439 => x"fc", + 440 => x"79", + 441 => x"05", + 442 => x"57", + 443 => x"83", + 444 => x"38", + 445 => x"51", + 446 => x"a4", + 447 => x"52", + 448 => x"93", + 449 => x"70", + 450 => x"34", + 451 => x"71", + 452 => x"81", + 453 => x"74", + 454 => x"0c", + 455 => x"04", + 456 => x"2b", + 457 => x"71", + 458 => x"51", + 459 => x"72", + 460 => x"72", + 461 => x"05", + 462 => x"71", + 463 => x"53", + 464 => x"70", + 465 => x"0c", + 466 => x"84", + 467 => x"f0", + 468 => x"8f", + 469 => x"83", + 470 => x"38", + 471 => x"84", + 472 => x"fc", + 473 => x"83", + 474 => x"70", + 475 => x"39", + 476 => x"77", + 477 => x"07", + 478 => x"54", + 479 => x"38", + 480 => x"08", + 481 => x"71", + 482 => x"80", + 483 => x"75", + 484 => x"33", + 485 => x"06", + 486 => x"80", + 487 => x"72", + 488 => x"75", + 489 => x"06", + 490 => x"12", + 491 => x"33", + 492 => x"06", + 493 => x"52", + 494 => x"72", + 495 => x"81", + 496 => x"81", + 497 => x"71", + 498 => x"88", + 499 => x"87", + 500 => x"71", + 501 => x"fb", + 502 => x"06", + 503 => x"82", + 504 => x"51", + 505 => x"97", + 506 => x"84", + 507 => x"54", + 508 => x"75", + 509 => x"38", + 510 => x"52", + 511 => x"80", + 512 => x"88", + 513 => x"0d", + 514 => x"0d", + 515 => x"53", + 516 => x"52", + 517 => x"91", + 518 => x"81", + 519 => x"07", + 520 => x"52", + 521 => x"e8", + 522 => x"ca", + 523 => x"3d", + 524 => x"3d", + 525 => x"08", + 526 => x"56", + 527 => x"80", + 528 => x"33", + 529 => x"2e", + 530 => x"86", + 531 => x"52", + 532 => x"53", + 533 => x"13", + 534 => x"33", + 535 => x"06", + 536 => x"70", + 537 => x"38", + 538 => x"80", + 539 => x"74", + 540 => x"81", + 541 => x"70", + 542 => x"81", + 543 => x"80", + 544 => x"05", + 545 => x"76", + 546 => x"70", + 547 => x"0c", + 548 => x"04", + 549 => x"76", + 550 => x"80", + 551 => x"86", + 552 => x"52", + 553 => x"bf", + 554 => x"88", + 555 => x"80", + 556 => x"74", + 557 => x"ca", + 558 => x"3d", + 559 => x"3d", + 560 => x"11", + 561 => x"52", + 562 => x"70", + 563 => x"98", + 564 => x"33", + 565 => x"82", + 566 => x"26", + 567 => x"84", + 568 => x"83", + 569 => x"26", + 570 => x"85", + 571 => x"84", + 572 => x"26", + 573 => x"86", + 574 => x"85", + 575 => x"26", + 576 => x"88", + 577 => x"86", + 578 => x"e7", + 579 => x"38", + 580 => x"54", + 581 => x"87", + 582 => x"cc", + 583 => x"87", + 584 => x"0c", + 585 => x"c0", + 586 => x"82", + 587 => x"c0", + 588 => x"83", + 589 => x"c0", + 590 => x"84", + 591 => x"c0", + 592 => x"85", + 593 => x"c0", + 594 => x"86", + 595 => x"c0", + 596 => x"74", + 597 => x"a4", + 598 => x"c0", + 599 => x"80", + 600 => x"98", + 601 => x"52", + 602 => x"88", + 603 => x"0d", + 604 => x"0d", + 605 => x"c0", + 606 => x"81", + 607 => x"c0", + 608 => x"5e", + 609 => x"87", + 610 => x"08", + 611 => x"1c", + 612 => x"98", + 613 => x"79", + 614 => x"87", + 615 => x"08", + 616 => x"1c", + 617 => x"98", + 618 => x"79", + 619 => x"87", + 620 => x"08", + 621 => x"1c", + 622 => x"98", + 623 => x"7b", + 624 => x"87", + 625 => x"08", + 626 => x"1c", + 627 => x"0c", + 628 => x"ff", + 629 => x"83", + 630 => x"58", + 631 => x"57", + 632 => x"56", + 633 => x"55", + 634 => x"54", + 635 => x"53", + 636 => x"ff", + 637 => x"b3", + 638 => x"84", + 639 => x"0d", + 640 => x"0d", + 641 => x"33", + 642 => x"9f", + 643 => x"52", + 644 => x"91", + 645 => x"83", + 646 => x"fb", + 647 => x"0b", + 648 => x"e0", + 649 => x"ff", + 650 => x"56", + 651 => x"84", + 652 => x"2e", + 653 => x"c0", + 654 => x"70", + 655 => x"2a", + 656 => x"53", + 657 => x"80", + 658 => x"71", + 659 => x"81", + 660 => x"70", + 661 => x"81", + 662 => x"06", + 663 => x"80", + 664 => x"71", + 665 => x"81", + 666 => x"70", + 667 => x"73", + 668 => x"51", + 669 => x"80", + 670 => x"2e", + 671 => x"c0", + 672 => x"75", + 673 => x"91", + 674 => x"87", + 675 => x"fb", + 676 => x"9f", + 677 => x"0b", + 678 => x"33", + 679 => x"06", + 680 => x"87", + 681 => x"51", + 682 => x"86", + 683 => x"94", + 684 => x"08", + 685 => x"70", + 686 => x"54", + 687 => x"2e", + 688 => x"91", + 689 => x"06", + 690 => x"d7", + 691 => x"32", + 692 => x"51", + 693 => x"2e", + 694 => x"93", + 695 => x"06", + 696 => x"ff", + 697 => x"81", + 698 => x"87", + 699 => x"52", + 700 => x"86", + 701 => x"94", + 702 => x"72", + 703 => x"0d", + 704 => x"0d", + 705 => x"74", + 706 => x"ff", + 707 => x"57", + 708 => x"80", + 709 => x"81", + 710 => x"15", + 711 => x"c6", + 712 => x"81", + 713 => x"57", + 714 => x"c0", + 715 => x"75", + 716 => x"38", + 717 => x"94", + 718 => x"70", + 719 => x"81", + 720 => x"52", + 721 => x"8c", + 722 => x"2a", + 723 => x"51", + 724 => x"38", + 725 => x"70", + 726 => x"51", + 727 => x"8d", + 728 => x"2a", + 729 => x"51", + 730 => x"be", + 731 => x"ff", + 732 => x"c0", + 733 => x"70", + 734 => x"38", + 735 => x"90", + 736 => x"0c", + 737 => x"33", + 738 => x"06", + 739 => x"70", + 740 => x"76", + 741 => x"0c", + 742 => x"04", + 743 => x"0b", + 744 => x"e0", + 745 => x"ff", + 746 => x"87", + 747 => x"51", + 748 => x"86", + 749 => x"94", + 750 => x"08", + 751 => x"70", + 752 => x"51", + 753 => x"2e", + 754 => x"81", + 755 => x"87", + 756 => x"52", + 757 => x"86", + 758 => x"94", + 759 => x"08", + 760 => x"06", + 761 => x"0c", + 762 => x"0d", + 763 => x"0d", + 764 => x"c6", + 765 => x"81", + 766 => x"53", + 767 => x"84", + 768 => x"2e", + 769 => x"c0", + 770 => x"71", + 771 => x"2a", + 772 => x"51", + 773 => x"52", + 774 => x"a0", + 775 => x"ff", + 776 => x"c0", + 777 => x"70", + 778 => x"38", + 779 => x"90", + 780 => x"70", + 781 => x"98", + 782 => x"51", + 783 => x"88", + 784 => x"0d", + 785 => x"0d", + 786 => x"80", + 787 => x"2a", + 788 => x"51", + 789 => x"83", + 790 => x"c0", + 791 => x"91", + 792 => x"87", + 793 => x"08", + 794 => x"0c", + 795 => x"8c", + 796 => x"ec", + 797 => x"9e", + 798 => x"c6", + 799 => x"c0", + 800 => x"91", + 801 => x"87", + 802 => x"08", + 803 => x"0c", + 804 => x"a4", + 805 => x"fc", + 806 => x"9e", + 807 => x"c7", + 808 => x"c0", + 809 => x"91", + 810 => x"87", + 811 => x"08", + 812 => x"c7", + 813 => x"c0", + 814 => x"91", + 815 => x"81", + 816 => x"90", + 817 => x"87", + 818 => x"08", + 819 => x"06", + 820 => x"70", + 821 => x"38", + 822 => x"91", + 823 => x"80", + 824 => x"9e", + 825 => x"81", + 826 => x"51", + 827 => x"80", + 828 => x"81", + 829 => x"c7", + 830 => x"0b", + 831 => x"88", + 832 => x"c0", + 833 => x"52", + 834 => x"2e", + 835 => x"52", + 836 => x"93", + 837 => x"87", + 838 => x"08", + 839 => x"06", + 840 => x"70", + 841 => x"38", + 842 => x"91", + 843 => x"80", + 844 => x"9e", + 845 => x"88", + 846 => x"52", + 847 => x"2e", + 848 => x"52", + 849 => x"95", + 850 => x"87", + 851 => x"08", + 852 => x"06", + 853 => x"70", + 854 => x"38", + 855 => x"91", + 856 => x"80", + 857 => x"9e", + 858 => x"82", + 859 => x"52", + 860 => x"2e", + 861 => x"52", + 862 => x"97", + 863 => x"87", + 864 => x"08", + 865 => x"06", + 866 => x"70", + 867 => x"38", + 868 => x"91", + 869 => x"87", + 870 => x"08", + 871 => x"06", + 872 => x"51", + 873 => x"91", + 874 => x"80", + 875 => x"9e", + 876 => x"90", + 877 => x"52", + 878 => x"83", + 879 => x"71", + 880 => x"34", + 881 => x"c0", + 882 => x"70", + 883 => x"52", + 884 => x"2e", + 885 => x"52", + 886 => x"9b", + 887 => x"9e", + 888 => x"87", + 889 => x"70", + 890 => x"34", + 891 => x"04", + 892 => x"91", + 893 => x"84", + 894 => x"c7", + 895 => x"73", + 896 => x"38", + 897 => x"51", + 898 => x"91", + 899 => x"84", + 900 => x"c7", + 901 => x"73", + 902 => x"38", + 903 => x"08", + 904 => x"e4", + 905 => x"b4", + 906 => x"d4", + 907 => x"92", + 908 => x"80", + 909 => x"91", + 910 => x"53", + 911 => x"08", + 912 => x"ec", + 913 => x"3f", + 914 => x"33", + 915 => x"38", + 916 => x"33", + 917 => x"2e", + 918 => x"c6", + 919 => x"91", + 920 => x"52", + 921 => x"51", + 922 => x"91", + 923 => x"54", + 924 => x"88", + 925 => x"b4", + 926 => x"3f", + 927 => x"33", + 928 => x"2e", + 929 => x"b5", + 930 => x"90", + 931 => x"97", + 932 => x"80", + 933 => x"91", + 934 => x"82", + 935 => x"c7", + 936 => x"73", + 937 => x"38", + 938 => x"33", + 939 => x"d8", + 940 => x"3f", + 941 => x"33", + 942 => x"2e", + 943 => x"b5", + 944 => x"d8", + 945 => x"9b", + 946 => x"80", + 947 => x"91", + 948 => x"52", + 949 => x"51", + 950 => x"91", + 951 => x"82", + 952 => x"c6", + 953 => x"91", + 954 => x"88", + 955 => x"c7", + 956 => x"91", + 957 => x"88", + 958 => x"c7", + 959 => x"91", + 960 => x"87", + 961 => x"c7", + 962 => x"91", + 963 => x"87", + 964 => x"c7", + 965 => x"91", + 966 => x"87", + 967 => x"3d", + 968 => x"3d", + 969 => x"05", + 970 => x"52", + 971 => x"ac", + 972 => x"29", + 973 => x"b3", + 974 => x"71", + 975 => x"b8", + 976 => x"39", + 977 => x"51", + 978 => x"b8", + 979 => x"39", + 980 => x"51", + 981 => x"b8", + 982 => x"39", + 983 => x"51", + 984 => x"84", + 985 => x"71", + 986 => x"04", + 987 => x"c0", + 988 => x"04", + 989 => x"87", + 990 => x"70", + 991 => x"80", + 992 => x"74", + 993 => x"c7", + 994 => x"0c", + 995 => x"04", + 996 => x"87", + 997 => x"70", + 998 => x"a0", + 999 => x"72", + 1000 => x"70", + 1001 => x"08", + 1002 => x"c7", + 1003 => x"0c", + 1004 => x"0d", + 1005 => x"a0", + 1006 => x"96", + 1007 => x"fe", + 1008 => x"93", + 1009 => x"72", + 1010 => x"81", + 1011 => x"8d", + 1012 => x"91", + 1013 => x"52", + 1014 => x"90", + 1015 => x"34", + 1016 => x"08", + 1017 => x"ca", + 1018 => x"39", + 1019 => x"08", + 1020 => x"2e", + 1021 => x"51", + 1022 => x"3d", + 1023 => x"3d", + 1024 => x"05", + 1025 => x"98", + 1026 => x"ca", + 1027 => x"51", + 1028 => x"72", + 1029 => x"0c", + 1030 => x"04", + 1031 => x"75", + 1032 => x"70", + 1033 => x"53", + 1034 => x"2e", + 1035 => x"81", + 1036 => x"81", + 1037 => x"87", + 1038 => x"85", + 1039 => x"fc", + 1040 => x"91", + 1041 => x"78", + 1042 => x"0c", + 1043 => x"33", + 1044 => x"06", + 1045 => x"80", + 1046 => x"72", + 1047 => x"51", + 1048 => x"fe", + 1049 => x"39", + 1050 => x"98", + 1051 => x"0d", + 1052 => x"0d", + 1053 => x"59", + 1054 => x"05", + 1055 => x"75", + 1056 => x"f8", + 1057 => x"2e", + 1058 => x"82", + 1059 => x"70", + 1060 => x"05", + 1061 => x"5b", + 1062 => x"2e", + 1063 => x"85", + 1064 => x"8b", + 1065 => x"2e", + 1066 => x"8a", + 1067 => x"78", + 1068 => x"5a", + 1069 => x"aa", + 1070 => x"06", + 1071 => x"84", + 1072 => x"7b", + 1073 => x"5d", + 1074 => x"59", + 1075 => x"d0", + 1076 => x"89", + 1077 => x"7a", + 1078 => x"10", + 1079 => x"d0", + 1080 => x"81", + 1081 => x"57", + 1082 => x"75", + 1083 => x"70", + 1084 => x"07", + 1085 => x"80", + 1086 => x"30", + 1087 => x"80", + 1088 => x"53", + 1089 => x"55", + 1090 => x"2e", + 1091 => x"84", + 1092 => x"81", + 1093 => x"57", + 1094 => x"2e", + 1095 => x"75", + 1096 => x"76", + 1097 => x"e0", + 1098 => x"ff", + 1099 => x"73", + 1100 => x"81", + 1101 => x"80", + 1102 => x"38", + 1103 => x"2e", + 1104 => x"73", + 1105 => x"8b", + 1106 => x"c2", + 1107 => x"38", + 1108 => x"73", + 1109 => x"81", + 1110 => x"8f", + 1111 => x"d5", + 1112 => x"38", + 1113 => x"24", + 1114 => x"80", + 1115 => x"38", + 1116 => x"73", + 1117 => x"80", + 1118 => x"ef", + 1119 => x"19", + 1120 => x"59", + 1121 => x"33", + 1122 => x"75", + 1123 => x"81", + 1124 => x"70", + 1125 => x"55", + 1126 => x"79", + 1127 => x"90", + 1128 => x"16", + 1129 => x"7b", + 1130 => x"a0", + 1131 => x"3f", + 1132 => x"53", + 1133 => x"e9", + 1134 => x"fc", + 1135 => x"81", + 1136 => x"72", + 1137 => x"b0", + 1138 => x"fb", + 1139 => x"39", + 1140 => x"83", + 1141 => x"59", + 1142 => x"82", + 1143 => x"88", + 1144 => x"8a", + 1145 => x"90", + 1146 => x"75", + 1147 => x"3f", + 1148 => x"79", + 1149 => x"81", + 1150 => x"72", + 1151 => x"38", + 1152 => x"59", + 1153 => x"84", + 1154 => x"58", + 1155 => x"80", + 1156 => x"30", + 1157 => x"80", + 1158 => x"55", + 1159 => x"25", + 1160 => x"80", + 1161 => x"74", + 1162 => x"07", + 1163 => x"0b", + 1164 => x"57", + 1165 => x"51", + 1166 => x"91", + 1167 => x"81", + 1168 => x"53", + 1169 => x"e6", + 1170 => x"ca", + 1171 => x"89", + 1172 => x"38", + 1173 => x"75", + 1174 => x"84", + 1175 => x"53", + 1176 => x"06", + 1177 => x"53", + 1178 => x"81", + 1179 => x"81", + 1180 => x"70", + 1181 => x"2a", + 1182 => x"76", + 1183 => x"38", + 1184 => x"38", + 1185 => x"70", + 1186 => x"53", + 1187 => x"8e", + 1188 => x"77", + 1189 => x"53", + 1190 => x"81", + 1191 => x"7a", + 1192 => x"55", + 1193 => x"83", + 1194 => x"79", + 1195 => x"81", + 1196 => x"72", + 1197 => x"17", + 1198 => x"27", + 1199 => x"51", + 1200 => x"75", + 1201 => x"72", + 1202 => x"81", + 1203 => x"7a", + 1204 => x"38", + 1205 => x"05", + 1206 => x"ff", + 1207 => x"70", + 1208 => x"57", + 1209 => x"76", + 1210 => x"81", + 1211 => x"72", + 1212 => x"84", + 1213 => x"f9", + 1214 => x"39", + 1215 => x"04", + 1216 => x"86", + 1217 => x"84", + 1218 => x"55", + 1219 => x"fa", + 1220 => x"3d", + 1221 => x"3d", + 1222 => x"ca", + 1223 => x"3d", + 1224 => x"75", + 1225 => x"3f", + 1226 => x"08", + 1227 => x"34", + 1228 => x"ca", + 1229 => x"3d", + 1230 => x"3d", + 1231 => x"98", + 1232 => x"ca", + 1233 => x"3d", + 1234 => x"77", + 1235 => x"a1", + 1236 => x"ca", + 1237 => x"3d", + 1238 => x"3d", + 1239 => x"91", + 1240 => x"70", + 1241 => x"55", + 1242 => x"80", + 1243 => x"38", + 1244 => x"08", + 1245 => x"91", + 1246 => x"81", + 1247 => x"72", + 1248 => x"cb", + 1249 => x"2e", + 1250 => x"88", + 1251 => x"70", + 1252 => x"51", + 1253 => x"2e", + 1254 => x"80", + 1255 => x"ff", + 1256 => x"39", + 1257 => x"c8", + 1258 => x"52", + 1259 => x"c0", + 1260 => x"52", + 1261 => x"81", + 1262 => x"51", + 1263 => x"ff", + 1264 => x"15", + 1265 => x"34", + 1266 => x"f3", + 1267 => x"72", + 1268 => x"0c", + 1269 => x"04", + 1270 => x"91", + 1271 => x"75", + 1272 => x"0c", + 1273 => x"52", + 1274 => x"3f", + 1275 => x"9c", + 1276 => x"0d", + 1277 => x"0d", + 1278 => x"56", + 1279 => x"0c", + 1280 => x"70", + 1281 => x"73", + 1282 => x"81", + 1283 => x"81", + 1284 => x"ed", + 1285 => x"2e", + 1286 => x"8e", + 1287 => x"08", + 1288 => x"76", + 1289 => x"56", + 1290 => x"b0", + 1291 => x"06", + 1292 => x"75", + 1293 => x"76", + 1294 => x"70", + 1295 => x"73", + 1296 => x"8b", + 1297 => x"73", + 1298 => x"85", + 1299 => x"82", + 1300 => x"76", + 1301 => x"70", + 1302 => x"ac", + 1303 => x"a0", + 1304 => x"fa", + 1305 => x"53", + 1306 => x"57", + 1307 => x"98", + 1308 => x"39", + 1309 => x"80", + 1310 => x"26", + 1311 => x"86", + 1312 => x"80", + 1313 => x"57", + 1314 => x"74", + 1315 => x"38", + 1316 => x"27", + 1317 => x"14", + 1318 => x"06", + 1319 => x"14", + 1320 => x"06", + 1321 => x"74", + 1322 => x"f9", + 1323 => x"ff", + 1324 => x"89", + 1325 => x"38", + 1326 => x"c5", + 1327 => x"29", + 1328 => x"81", + 1329 => x"76", + 1330 => x"56", + 1331 => x"ba", + 1332 => x"2e", + 1333 => x"30", + 1334 => x"0c", + 1335 => x"91", + 1336 => x"8a", + 1337 => x"f8", + 1338 => x"7c", + 1339 => x"70", + 1340 => x"75", + 1341 => x"55", + 1342 => x"2e", + 1343 => x"87", + 1344 => x"76", + 1345 => x"73", + 1346 => x"81", + 1347 => x"81", + 1348 => x"77", + 1349 => x"70", + 1350 => x"58", + 1351 => x"09", + 1352 => x"c2", + 1353 => x"81", + 1354 => x"75", + 1355 => x"55", + 1356 => x"e2", + 1357 => x"90", + 1358 => x"f8", + 1359 => x"8f", + 1360 => x"81", + 1361 => x"75", + 1362 => x"55", + 1363 => x"81", + 1364 => x"27", + 1365 => x"d0", + 1366 => x"55", + 1367 => x"73", + 1368 => x"80", + 1369 => x"14", + 1370 => x"72", + 1371 => x"e0", + 1372 => x"80", + 1373 => x"39", + 1374 => x"55", + 1375 => x"80", + 1376 => x"e0", + 1377 => x"38", + 1378 => x"81", + 1379 => x"53", + 1380 => x"81", + 1381 => x"53", + 1382 => x"8e", + 1383 => x"70", + 1384 => x"55", + 1385 => x"27", + 1386 => x"77", + 1387 => x"74", + 1388 => x"76", + 1389 => x"77", + 1390 => x"70", + 1391 => x"55", + 1392 => x"77", + 1393 => x"38", + 1394 => x"74", + 1395 => x"55", + 1396 => x"88", + 1397 => x"0d", + 1398 => x"0d", + 1399 => x"33", + 1400 => x"70", + 1401 => x"38", + 1402 => x"11", + 1403 => x"91", + 1404 => x"83", + 1405 => x"fc", + 1406 => x"9b", + 1407 => x"84", + 1408 => x"33", + 1409 => x"51", + 1410 => x"80", + 1411 => x"84", + 1412 => x"92", + 1413 => x"51", + 1414 => x"80", + 1415 => x"81", + 1416 => x"72", + 1417 => x"92", + 1418 => x"81", + 1419 => x"0b", + 1420 => x"8c", + 1421 => x"71", + 1422 => x"06", + 1423 => x"80", + 1424 => x"87", + 1425 => x"08", + 1426 => x"38", + 1427 => x"80", + 1428 => x"71", + 1429 => x"c0", + 1430 => x"51", + 1431 => x"87", + 1432 => x"c7", + 1433 => x"91", + 1434 => x"33", + 1435 => x"ca", + 1436 => x"3d", + 1437 => x"3d", + 1438 => x"64", + 1439 => x"bf", + 1440 => x"40", + 1441 => x"74", + 1442 => x"cd", + 1443 => x"88", + 1444 => x"7a", + 1445 => x"81", + 1446 => x"72", + 1447 => x"87", + 1448 => x"11", + 1449 => x"8c", + 1450 => x"92", + 1451 => x"5a", + 1452 => x"58", + 1453 => x"c0", + 1454 => x"76", + 1455 => x"76", + 1456 => x"70", + 1457 => x"81", + 1458 => x"54", + 1459 => x"8e", + 1460 => x"52", + 1461 => x"81", + 1462 => x"81", + 1463 => x"74", + 1464 => x"53", + 1465 => x"83", + 1466 => x"78", + 1467 => x"8f", + 1468 => x"2e", + 1469 => x"c0", + 1470 => x"52", + 1471 => x"87", + 1472 => x"08", + 1473 => x"2e", + 1474 => x"84", + 1475 => x"38", + 1476 => x"87", + 1477 => x"15", + 1478 => x"70", + 1479 => x"52", + 1480 => x"ff", + 1481 => x"39", + 1482 => x"81", + 1483 => x"ff", + 1484 => x"57", + 1485 => x"90", + 1486 => x"80", + 1487 => x"71", + 1488 => x"78", + 1489 => x"38", + 1490 => x"80", + 1491 => x"80", + 1492 => x"81", + 1493 => x"72", + 1494 => x"0c", + 1495 => x"04", + 1496 => x"60", + 1497 => x"8c", + 1498 => x"33", + 1499 => x"5b", + 1500 => x"74", + 1501 => x"e1", + 1502 => x"88", + 1503 => x"79", + 1504 => x"78", + 1505 => x"06", + 1506 => x"77", + 1507 => x"87", + 1508 => x"11", + 1509 => x"8c", + 1510 => x"92", + 1511 => x"59", + 1512 => x"85", + 1513 => x"98", + 1514 => x"7d", + 1515 => x"0c", + 1516 => x"08", + 1517 => x"70", + 1518 => x"53", + 1519 => x"2e", + 1520 => x"70", + 1521 => x"33", + 1522 => x"18", + 1523 => x"2a", + 1524 => x"51", + 1525 => x"2e", + 1526 => x"c0", + 1527 => x"52", + 1528 => x"87", + 1529 => x"08", + 1530 => x"2e", + 1531 => x"84", + 1532 => x"38", + 1533 => x"87", + 1534 => x"15", + 1535 => x"70", + 1536 => x"52", + 1537 => x"ff", + 1538 => x"39", + 1539 => x"81", + 1540 => x"80", + 1541 => x"52", + 1542 => x"90", + 1543 => x"80", + 1544 => x"71", + 1545 => x"7a", + 1546 => x"38", + 1547 => x"80", + 1548 => x"80", + 1549 => x"81", + 1550 => x"72", + 1551 => x"0c", + 1552 => x"04", + 1553 => x"7e", + 1554 => x"b3", + 1555 => x"88", + 1556 => x"33", + 1557 => x"56", + 1558 => x"3f", + 1559 => x"08", + 1560 => x"83", + 1561 => x"fe", + 1562 => x"87", + 1563 => x"0c", + 1564 => x"76", + 1565 => x"38", + 1566 => x"93", + 1567 => x"2b", + 1568 => x"8c", + 1569 => x"71", + 1570 => x"38", + 1571 => x"71", + 1572 => x"c6", + 1573 => x"39", + 1574 => x"81", + 1575 => x"06", + 1576 => x"71", + 1577 => x"38", + 1578 => x"8c", + 1579 => x"e8", + 1580 => x"98", + 1581 => x"71", + 1582 => x"73", + 1583 => x"92", + 1584 => x"72", + 1585 => x"06", + 1586 => x"f7", + 1587 => x"80", + 1588 => x"88", + 1589 => x"0c", + 1590 => x"80", + 1591 => x"56", + 1592 => x"56", + 1593 => x"91", + 1594 => x"8c", + 1595 => x"fe", + 1596 => x"81", + 1597 => x"33", + 1598 => x"07", + 1599 => x"0c", + 1600 => x"3d", + 1601 => x"3d", + 1602 => x"11", + 1603 => x"33", + 1604 => x"71", + 1605 => x"81", + 1606 => x"72", + 1607 => x"75", + 1608 => x"91", + 1609 => x"52", + 1610 => x"54", + 1611 => x"0d", + 1612 => x"0d", + 1613 => x"05", + 1614 => x"52", + 1615 => x"70", + 1616 => x"34", + 1617 => x"51", + 1618 => x"83", + 1619 => x"ff", + 1620 => x"75", + 1621 => x"72", + 1622 => x"54", + 1623 => x"2a", + 1624 => x"70", + 1625 => x"34", + 1626 => x"51", + 1627 => x"81", + 1628 => x"70", + 1629 => x"70", + 1630 => x"3d", + 1631 => x"3d", + 1632 => x"77", + 1633 => x"70", + 1634 => x"38", + 1635 => x"05", + 1636 => x"70", + 1637 => x"34", + 1638 => x"eb", + 1639 => x"0d", + 1640 => x"0d", + 1641 => x"54", + 1642 => x"72", + 1643 => x"54", + 1644 => x"51", + 1645 => x"84", + 1646 => x"fc", + 1647 => x"77", + 1648 => x"53", + 1649 => x"05", + 1650 => x"70", + 1651 => x"33", + 1652 => x"ff", + 1653 => x"52", + 1654 => x"2e", + 1655 => x"80", + 1656 => x"71", + 1657 => x"0c", + 1658 => x"04", + 1659 => x"74", + 1660 => x"89", + 1661 => x"2e", + 1662 => x"11", + 1663 => x"52", + 1664 => x"70", + 1665 => x"88", + 1666 => x"0d", + 1667 => x"91", + 1668 => x"04", + 1669 => x"ca", + 1670 => x"f7", + 1671 => x"56", + 1672 => x"17", + 1673 => x"74", + 1674 => x"d6", + 1675 => x"b0", + 1676 => x"b4", + 1677 => x"81", + 1678 => x"59", + 1679 => x"91", + 1680 => x"7a", + 1681 => x"06", + 1682 => x"ca", + 1683 => x"17", + 1684 => x"08", + 1685 => x"08", + 1686 => x"08", + 1687 => x"74", + 1688 => x"38", + 1689 => x"55", + 1690 => x"09", + 1691 => x"38", + 1692 => x"18", + 1693 => x"81", + 1694 => x"f9", + 1695 => x"39", + 1696 => x"91", + 1697 => x"8b", + 1698 => x"fa", + 1699 => x"7a", + 1700 => x"57", + 1701 => x"08", + 1702 => x"75", + 1703 => x"3f", + 1704 => x"08", + 1705 => x"88", + 1706 => x"81", + 1707 => x"b4", + 1708 => x"16", + 1709 => x"be", + 1710 => x"88", + 1711 => x"85", + 1712 => x"81", + 1713 => x"17", + 1714 => x"ca", + 1715 => x"3d", + 1716 => x"3d", + 1717 => x"52", + 1718 => x"3f", + 1719 => x"08", + 1720 => x"88", + 1721 => x"38", + 1722 => x"74", + 1723 => x"81", + 1724 => x"38", + 1725 => x"59", + 1726 => x"09", + 1727 => x"e3", + 1728 => x"53", + 1729 => x"08", + 1730 => x"70", + 1731 => x"91", + 1732 => x"d5", + 1733 => x"17", + 1734 => x"3f", + 1735 => x"a4", + 1736 => x"51", + 1737 => x"86", + 1738 => x"f2", + 1739 => x"17", + 1740 => x"3f", + 1741 => x"52", + 1742 => x"51", + 1743 => x"8c", + 1744 => x"84", + 1745 => x"fc", + 1746 => x"17", + 1747 => x"70", + 1748 => x"79", + 1749 => x"52", + 1750 => x"51", + 1751 => x"77", + 1752 => x"80", + 1753 => x"81", + 1754 => x"f9", + 1755 => x"ca", + 1756 => x"2e", + 1757 => x"58", + 1758 => x"88", + 1759 => x"0d", + 1760 => x"0d", + 1761 => x"98", + 1762 => x"05", + 1763 => x"80", + 1764 => x"27", + 1765 => x"14", + 1766 => x"29", + 1767 => x"05", + 1768 => x"91", + 1769 => x"87", + 1770 => x"f9", + 1771 => x"7a", + 1772 => x"54", + 1773 => x"27", + 1774 => x"76", + 1775 => x"27", + 1776 => x"ff", + 1777 => x"58", + 1778 => x"80", + 1779 => x"82", + 1780 => x"72", + 1781 => x"38", + 1782 => x"72", + 1783 => x"8e", + 1784 => x"39", + 1785 => x"17", + 1786 => x"a4", + 1787 => x"53", + 1788 => x"fd", + 1789 => x"ca", + 1790 => x"9f", + 1791 => x"ff", + 1792 => x"11", + 1793 => x"70", + 1794 => x"18", + 1795 => x"76", + 1796 => x"53", + 1797 => x"91", + 1798 => x"80", + 1799 => x"83", + 1800 => x"b4", + 1801 => x"88", + 1802 => x"79", + 1803 => x"84", + 1804 => x"58", + 1805 => x"80", + 1806 => x"9f", + 1807 => x"80", + 1808 => x"88", + 1809 => x"08", + 1810 => x"51", + 1811 => x"91", + 1812 => x"80", + 1813 => x"10", + 1814 => x"74", + 1815 => x"51", + 1816 => x"91", + 1817 => x"83", + 1818 => x"58", + 1819 => x"87", + 1820 => x"08", + 1821 => x"51", + 1822 => x"91", + 1823 => x"9b", + 1824 => x"2b", + 1825 => x"74", + 1826 => x"51", + 1827 => x"91", + 1828 => x"f0", + 1829 => x"83", + 1830 => x"77", + 1831 => x"0c", + 1832 => x"04", + 1833 => x"7a", + 1834 => x"58", + 1835 => x"81", + 1836 => x"9e", + 1837 => x"17", + 1838 => x"96", + 1839 => x"53", + 1840 => x"81", + 1841 => x"79", + 1842 => x"72", + 1843 => x"38", + 1844 => x"72", + 1845 => x"b8", + 1846 => x"39", + 1847 => x"17", + 1848 => x"a4", + 1849 => x"53", + 1850 => x"fb", + 1851 => x"ca", + 1852 => x"91", + 1853 => x"81", + 1854 => x"83", + 1855 => x"b4", + 1856 => x"78", + 1857 => x"56", + 1858 => x"76", + 1859 => x"38", + 1860 => x"9f", + 1861 => x"33", + 1862 => x"07", + 1863 => x"74", + 1864 => x"83", + 1865 => x"89", + 1866 => x"08", + 1867 => x"51", + 1868 => x"91", + 1869 => x"59", + 1870 => x"08", + 1871 => x"74", + 1872 => x"16", + 1873 => x"84", + 1874 => x"76", + 1875 => x"88", + 1876 => x"81", + 1877 => x"8f", + 1878 => x"53", + 1879 => x"80", + 1880 => x"88", + 1881 => x"08", + 1882 => x"51", + 1883 => x"91", + 1884 => x"59", + 1885 => x"08", + 1886 => x"77", + 1887 => x"06", + 1888 => x"83", + 1889 => x"05", + 1890 => x"f7", + 1891 => x"39", + 1892 => x"a4", + 1893 => x"52", + 1894 => x"ef", + 1895 => x"88", + 1896 => x"ca", + 1897 => x"38", + 1898 => x"06", + 1899 => x"83", + 1900 => x"18", + 1901 => x"54", + 1902 => x"f6", + 1903 => x"ca", + 1904 => x"0a", + 1905 => x"52", + 1906 => x"83", + 1907 => x"83", + 1908 => x"91", + 1909 => x"8a", + 1910 => x"f8", + 1911 => x"7c", + 1912 => x"59", + 1913 => x"81", + 1914 => x"38", + 1915 => x"08", + 1916 => x"73", + 1917 => x"38", + 1918 => x"52", + 1919 => x"a4", + 1920 => x"88", + 1921 => x"ca", + 1922 => x"f2", + 1923 => x"82", + 1924 => x"39", + 1925 => x"e6", + 1926 => x"88", + 1927 => x"de", + 1928 => x"78", + 1929 => x"3f", + 1930 => x"08", + 1931 => x"88", + 1932 => x"80", + 1933 => x"ca", + 1934 => x"2e", + 1935 => x"ca", + 1936 => x"2e", + 1937 => x"53", + 1938 => x"51", + 1939 => x"91", + 1940 => x"c5", + 1941 => x"08", + 1942 => x"18", + 1943 => x"57", + 1944 => x"90", + 1945 => x"90", + 1946 => x"16", + 1947 => x"54", + 1948 => x"34", + 1949 => x"78", + 1950 => x"38", + 1951 => x"91", + 1952 => x"8a", + 1953 => x"f6", + 1954 => x"7e", + 1955 => x"5b", + 1956 => x"38", + 1957 => x"58", + 1958 => x"88", + 1959 => x"08", + 1960 => x"38", + 1961 => x"39", + 1962 => x"51", + 1963 => x"81", + 1964 => x"ca", + 1965 => x"82", + 1966 => x"ca", + 1967 => x"91", + 1968 => x"ff", + 1969 => x"38", + 1970 => x"91", + 1971 => x"26", + 1972 => x"79", + 1973 => x"08", + 1974 => x"73", + 1975 => x"b9", + 1976 => x"2e", + 1977 => x"80", + 1978 => x"1a", + 1979 => x"08", + 1980 => x"38", + 1981 => x"52", + 1982 => x"af", + 1983 => x"91", + 1984 => x"81", + 1985 => x"06", + 1986 => x"ca", + 1987 => x"91", + 1988 => x"09", + 1989 => x"72", + 1990 => x"70", + 1991 => x"ca", + 1992 => x"51", + 1993 => x"73", + 1994 => x"91", + 1995 => x"80", + 1996 => x"8c", + 1997 => x"81", + 1998 => x"38", + 1999 => x"08", + 2000 => x"73", + 2001 => x"75", + 2002 => x"77", + 2003 => x"56", + 2004 => x"76", + 2005 => x"82", + 2006 => x"26", + 2007 => x"75", + 2008 => x"f8", + 2009 => x"ca", + 2010 => x"2e", + 2011 => x"59", + 2012 => x"08", + 2013 => x"81", + 2014 => x"91", + 2015 => x"59", + 2016 => x"08", + 2017 => x"70", + 2018 => x"25", + 2019 => x"51", + 2020 => x"73", + 2021 => x"75", + 2022 => x"81", + 2023 => x"38", + 2024 => x"f5", + 2025 => x"75", + 2026 => x"f9", + 2027 => x"ca", + 2028 => x"ca", + 2029 => x"70", + 2030 => x"08", + 2031 => x"51", + 2032 => x"80", + 2033 => x"73", + 2034 => x"38", + 2035 => x"52", + 2036 => x"d0", + 2037 => x"88", + 2038 => x"a5", + 2039 => x"18", + 2040 => x"08", + 2041 => x"18", + 2042 => x"74", + 2043 => x"38", + 2044 => x"18", + 2045 => x"33", + 2046 => x"73", + 2047 => x"97", + 2048 => x"74", + 2049 => x"38", + 2050 => x"55", + 2051 => x"ca", + 2052 => x"85", + 2053 => x"75", + 2054 => x"ca", + 2055 => x"3d", + 2056 => x"3d", + 2057 => x"52", + 2058 => x"3f", + 2059 => x"08", + 2060 => x"91", + 2061 => x"80", + 2062 => x"52", + 2063 => x"c1", + 2064 => x"88", + 2065 => x"88", + 2066 => x"0c", + 2067 => x"53", + 2068 => x"15", + 2069 => x"f2", + 2070 => x"56", + 2071 => x"16", + 2072 => x"22", + 2073 => x"27", + 2074 => x"54", + 2075 => x"76", + 2076 => x"33", + 2077 => x"3f", + 2078 => x"08", + 2079 => x"38", + 2080 => x"76", + 2081 => x"70", + 2082 => x"9f", + 2083 => x"56", + 2084 => x"ca", + 2085 => x"3d", + 2086 => x"3d", + 2087 => x"71", + 2088 => x"57", + 2089 => x"0a", + 2090 => x"38", + 2091 => x"53", + 2092 => x"38", + 2093 => x"0c", + 2094 => x"54", + 2095 => x"75", + 2096 => x"73", + 2097 => x"a8", + 2098 => x"73", + 2099 => x"85", + 2100 => x"0b", + 2101 => x"5a", + 2102 => x"27", + 2103 => x"a8", + 2104 => x"18", + 2105 => x"39", + 2106 => x"70", + 2107 => x"58", + 2108 => x"b2", + 2109 => x"76", + 2110 => x"3f", + 2111 => x"08", + 2112 => x"88", + 2113 => x"bd", + 2114 => x"91", + 2115 => x"27", + 2116 => x"16", + 2117 => x"88", + 2118 => x"38", + 2119 => x"39", + 2120 => x"55", + 2121 => x"52", + 2122 => x"d5", + 2123 => x"88", + 2124 => x"0c", + 2125 => x"0c", + 2126 => x"53", + 2127 => x"80", + 2128 => x"85", + 2129 => x"94", + 2130 => x"2a", + 2131 => x"0c", + 2132 => x"06", + 2133 => x"9c", + 2134 => x"58", + 2135 => x"88", + 2136 => x"0d", + 2137 => x"0d", + 2138 => x"90", + 2139 => x"05", + 2140 => x"f0", + 2141 => x"27", + 2142 => x"0b", + 2143 => x"98", + 2144 => x"84", + 2145 => x"2e", + 2146 => x"76", + 2147 => x"58", + 2148 => x"38", + 2149 => x"15", + 2150 => x"08", + 2151 => x"38", + 2152 => x"88", + 2153 => x"53", + 2154 => x"81", + 2155 => x"c0", + 2156 => x"22", + 2157 => x"89", + 2158 => x"72", + 2159 => x"74", + 2160 => x"f3", + 2161 => x"ca", + 2162 => x"82", + 2163 => x"91", + 2164 => x"27", + 2165 => x"81", + 2166 => x"88", + 2167 => x"80", + 2168 => x"16", + 2169 => x"88", + 2170 => x"ca", + 2171 => x"38", + 2172 => x"0c", + 2173 => x"dd", + 2174 => x"08", + 2175 => x"f9", + 2176 => x"ca", + 2177 => x"87", + 2178 => x"88", + 2179 => x"80", + 2180 => x"55", + 2181 => x"08", + 2182 => x"38", + 2183 => x"ca", + 2184 => x"2e", + 2185 => x"ca", + 2186 => x"75", + 2187 => x"3f", + 2188 => x"08", + 2189 => x"94", + 2190 => x"52", + 2191 => x"c1", + 2192 => x"88", + 2193 => x"0c", + 2194 => x"0c", + 2195 => x"05", + 2196 => x"80", + 2197 => x"ca", + 2198 => x"3d", + 2199 => x"3d", + 2200 => x"71", + 2201 => x"57", + 2202 => x"51", + 2203 => x"91", + 2204 => x"54", + 2205 => x"08", + 2206 => x"91", + 2207 => x"56", + 2208 => x"52", + 2209 => x"83", + 2210 => x"88", + 2211 => x"ca", + 2212 => x"d2", + 2213 => x"88", + 2214 => x"08", + 2215 => x"54", + 2216 => x"e5", + 2217 => x"06", + 2218 => x"58", + 2219 => x"08", + 2220 => x"38", + 2221 => x"75", + 2222 => x"80", + 2223 => x"81", + 2224 => x"7a", + 2225 => x"06", + 2226 => x"39", + 2227 => x"08", + 2228 => x"76", + 2229 => x"3f", + 2230 => x"08", + 2231 => x"88", + 2232 => x"ff", + 2233 => x"84", + 2234 => x"06", + 2235 => x"54", + 2236 => x"88", + 2237 => x"0d", + 2238 => x"0d", + 2239 => x"52", + 2240 => x"3f", + 2241 => x"08", + 2242 => x"06", + 2243 => x"51", + 2244 => x"83", + 2245 => x"06", + 2246 => x"14", + 2247 => x"3f", + 2248 => x"08", + 2249 => x"07", + 2250 => x"ca", + 2251 => x"3d", + 2252 => x"3d", + 2253 => x"70", + 2254 => x"06", + 2255 => x"53", + 2256 => x"ed", + 2257 => x"33", + 2258 => x"83", + 2259 => x"06", + 2260 => x"90", + 2261 => x"15", + 2262 => x"3f", + 2263 => x"04", + 2264 => x"7b", + 2265 => x"84", + 2266 => x"58", + 2267 => x"80", + 2268 => x"38", + 2269 => x"52", + 2270 => x"8f", + 2271 => x"88", + 2272 => x"ca", + 2273 => x"f5", + 2274 => x"08", + 2275 => x"53", + 2276 => x"84", + 2277 => x"39", + 2278 => x"70", + 2279 => x"81", + 2280 => x"51", + 2281 => x"16", + 2282 => x"88", + 2283 => x"81", + 2284 => x"38", + 2285 => x"ae", + 2286 => x"81", + 2287 => x"54", + 2288 => x"2e", + 2289 => x"8f", + 2290 => x"91", + 2291 => x"76", + 2292 => x"54", + 2293 => x"09", + 2294 => x"38", + 2295 => x"7a", + 2296 => x"80", + 2297 => x"fa", + 2298 => x"ca", + 2299 => x"91", + 2300 => x"89", + 2301 => x"08", + 2302 => x"86", + 2303 => x"98", + 2304 => x"91", + 2305 => x"8b", + 2306 => x"fb", + 2307 => x"70", + 2308 => x"81", + 2309 => x"fc", + 2310 => x"ca", + 2311 => x"91", + 2312 => x"b4", + 2313 => x"08", + 2314 => x"ec", + 2315 => x"ca", + 2316 => x"91", + 2317 => x"a0", + 2318 => x"91", + 2319 => x"52", + 2320 => x"51", + 2321 => x"8b", + 2322 => x"52", + 2323 => x"51", + 2324 => x"81", + 2325 => x"34", + 2326 => x"88", + 2327 => x"0d", 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x"15", + 2387 => x"70", + 2388 => x"56", + 2389 => x"09", + 2390 => x"38", + 2391 => x"80", + 2392 => x"30", + 2393 => x"78", + 2394 => x"54", + 2395 => x"73", + 2396 => x"60", + 2397 => x"54", + 2398 => x"96", + 2399 => x"0b", + 2400 => x"80", + 2401 => x"f6", + 2402 => x"ca", + 2403 => x"85", + 2404 => x"3d", + 2405 => x"5c", + 2406 => x"53", + 2407 => x"51", + 2408 => x"80", + 2409 => x"88", + 2410 => x"5c", + 2411 => x"09", + 2412 => x"d4", + 2413 => x"70", + 2414 => x"71", + 2415 => x"30", + 2416 => x"73", + 2417 => x"51", + 2418 => x"57", + 2419 => x"38", + 2420 => x"75", + 2421 => x"17", + 2422 => x"75", + 2423 => x"30", + 2424 => x"51", + 2425 => x"80", + 2426 => x"38", + 2427 => x"87", + 2428 => x"26", + 2429 => x"77", + 2430 => x"a4", + 2431 => x"27", + 2432 => x"a0", + 2433 => x"39", + 2434 => x"33", + 2435 => x"57", + 2436 => x"27", + 2437 => x"75", + 2438 => x"30", + 2439 => x"32", + 2440 => x"80", + 2441 => x"25", + 2442 => x"56", + 2443 => x"80", + 2444 => x"84", + 2445 => x"58", + 2446 => x"70", + 2447 => x"55", + 2448 => x"09", + 2449 => x"38", + 2450 => x"80", + 2451 => x"30", + 2452 => x"77", + 2453 => x"54", + 2454 => x"81", + 2455 => x"ae", + 2456 => x"06", + 2457 => x"54", + 2458 => x"74", + 2459 => x"80", + 2460 => x"7b", + 2461 => x"30", + 2462 => x"70", + 2463 => x"25", + 2464 => x"07", + 2465 => x"51", + 2466 => x"a7", + 2467 => x"8b", + 2468 => x"39", + 2469 => x"54", + 2470 => x"8c", + 2471 => x"ff", + 2472 => x"94", + 2473 => x"54", + 2474 => x"e1", + 2475 => x"88", + 2476 => x"b2", + 2477 => x"70", + 2478 => x"71", + 2479 => x"54", + 2480 => x"91", + 2481 => x"80", + 2482 => x"38", + 2483 => x"76", + 2484 => x"df", + 2485 => x"54", + 2486 => x"81", + 2487 => x"55", + 2488 => x"34", + 2489 => x"52", + 2490 => x"51", + 2491 => x"91", + 2492 => x"bf", + 2493 => x"16", + 2494 => x"26", + 2495 => x"16", + 2496 => x"06", + 2497 => x"17", + 2498 => x"34", + 2499 => x"fd", + 2500 => x"19", + 2501 => x"80", + 2502 => x"79", + 2503 => x"81", + 2504 => x"81", + 2505 => x"85", + 2506 => x"54", + 2507 => x"8f", + 2508 => x"86", + 2509 => x"39", + 2510 => x"f3", + 2511 => x"73", + 2512 => x"80", + 2513 => x"52", + 2514 => x"ce", + 2515 => x"88", + 2516 => x"ca", + 2517 => x"d7", + 2518 => x"08", + 2519 => x"e6", + 2520 => x"ca", + 2521 => x"91", + 2522 => x"80", + 2523 => x"1b", + 2524 => x"55", + 2525 => x"2e", + 2526 => x"8b", + 2527 => x"06", + 2528 => x"1c", + 2529 => x"33", + 2530 => x"70", + 2531 => x"55", + 2532 => x"38", + 2533 => x"52", + 2534 => x"9f", + 2535 => x"88", + 2536 => x"8b", + 2537 => x"7a", + 2538 => x"3f", + 2539 => x"75", + 2540 => x"57", + 2541 => x"2e", + 2542 => x"84", + 2543 => x"06", + 2544 => x"75", + 2545 => x"81", + 2546 => x"2a", + 2547 => x"73", + 2548 => x"38", + 2549 => x"54", + 2550 => x"fb", + 2551 => x"80", + 2552 => x"34", + 2553 => x"c1", + 2554 => x"06", + 2555 => x"38", + 2556 => x"39", + 2557 => x"70", + 2558 => x"54", + 2559 => x"86", + 2560 => x"84", + 2561 => x"06", + 2562 => x"73", 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x"38", + 2622 => x"83", + 2623 => x"74", + 2624 => x"59", + 2625 => x"39", + 2626 => x"33", + 2627 => x"ca", + 2628 => x"3d", + 2629 => x"3d", + 2630 => x"80", + 2631 => x"34", + 2632 => x"17", + 2633 => x"75", + 2634 => x"3f", + 2635 => x"ca", + 2636 => x"80", + 2637 => x"16", + 2638 => x"3f", + 2639 => x"08", + 2640 => x"06", + 2641 => x"73", + 2642 => x"2e", + 2643 => x"80", + 2644 => x"0b", + 2645 => x"56", + 2646 => x"e9", + 2647 => x"06", + 2648 => x"57", + 2649 => x"32", + 2650 => x"80", + 2651 => x"51", + 2652 => x"8a", + 2653 => x"e8", + 2654 => x"06", + 2655 => x"53", + 2656 => x"52", + 2657 => x"51", + 2658 => x"91", + 2659 => x"55", + 2660 => x"08", + 2661 => x"38", + 2662 => x"b8", + 2663 => x"86", + 2664 => x"97", + 2665 => x"88", + 2666 => x"ca", + 2667 => x"2e", + 2668 => x"55", + 2669 => x"88", + 2670 => x"0d", + 2671 => x"0d", + 2672 => x"05", + 2673 => x"33", + 2674 => x"75", + 2675 => x"fc", + 2676 => x"ca", + 2677 => x"8b", + 2678 => x"91", + 2679 => x"24", + 2680 => x"91", + 2681 => x"84", + 2682 => x"a4", + 2683 => x"55", + 2684 => x"73", + 2685 => x"e6", + 2686 => x"0c", + 2687 => x"06", + 2688 => x"57", + 2689 => x"ae", + 2690 => x"33", + 2691 => x"3f", + 2692 => x"08", + 2693 => x"70", + 2694 => x"55", + 2695 => x"76", + 2696 => x"b8", + 2697 => x"2a", + 2698 => x"51", + 2699 => x"72", + 2700 => x"86", + 2701 => x"74", + 2702 => x"15", + 2703 => x"81", + 2704 => x"d7", + 2705 => x"ca", + 2706 => x"ff", + 2707 => x"06", + 2708 => x"56", + 2709 => x"38", + 2710 => x"8f", + 2711 => x"2a", + 2712 => x"51", + 2713 => x"72", + 2714 => x"80", + 2715 => x"52", + 2716 => x"3f", + 2717 => x"08", + 2718 => x"57", + 2719 => x"09", + 2720 => x"e2", + 2721 => x"74", + 2722 => x"56", + 2723 => x"33", + 2724 => x"72", + 2725 => x"38", + 2726 => x"51", + 2727 => x"91", + 2728 => x"57", + 2729 => x"84", + 2730 => x"ff", + 2731 => x"56", + 2732 => x"25", + 2733 => x"0b", + 2734 => x"56", + 2735 => x"05", + 2736 => x"83", + 2737 => x"2e", + 2738 => x"52", + 2739 => x"c6", + 2740 => x"88", + 2741 => x"06", + 2742 => x"27", + 2743 => x"16", + 2744 => x"27", + 2745 => x"56", + 2746 => x"84", + 2747 => x"56", + 2748 => x"84", + 2749 => x"14", + 2750 => x"3f", + 2751 => x"08", + 2752 => x"06", + 2753 => x"80", + 2754 => x"06", + 2755 => x"80", + 2756 => x"db", + 2757 => x"ca", + 2758 => x"ff", + 2759 => x"77", + 2760 => x"d8", + 2761 => x"de", + 2762 => x"88", + 2763 => x"9c", + 2764 => x"c4", + 2765 => x"15", + 2766 => x"14", + 2767 => x"70", + 2768 => x"51", + 2769 => x"56", + 2770 => x"84", + 2771 => x"81", + 2772 => x"71", + 2773 => x"16", + 2774 => x"53", + 2775 => x"23", + 2776 => x"8b", + 2777 => x"73", + 2778 => x"80", + 2779 => x"8d", + 2780 => x"39", + 2781 => x"51", + 2782 => x"91", + 2783 => x"53", + 2784 => x"08", + 2785 => x"72", + 2786 => x"8d", + 2787 => x"ce", + 2788 => x"14", + 2789 => x"3f", + 2790 => x"08", + 2791 => x"06", + 2792 => x"38", + 2793 => x"51", + 2794 => x"91", + 2795 => x"55", + 2796 => x"51", + 2797 => x"91", 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x"0c", + 2857 => x"84", + 2858 => x"83", + 2859 => x"06", + 2860 => x"80", + 2861 => x"d8", + 2862 => x"ca", + 2863 => x"ff", + 2864 => x"72", + 2865 => x"81", + 2866 => x"38", + 2867 => x"73", + 2868 => x"3f", + 2869 => x"08", + 2870 => x"91", + 2871 => x"84", + 2872 => x"b2", + 2873 => x"87", + 2874 => x"88", + 2875 => x"ff", + 2876 => x"82", + 2877 => x"09", + 2878 => x"c8", + 2879 => x"51", + 2880 => x"91", + 2881 => x"84", + 2882 => x"d2", + 2883 => x"06", + 2884 => x"98", + 2885 => x"ee", + 2886 => x"88", + 2887 => x"85", + 2888 => x"09", + 2889 => x"38", + 2890 => x"51", + 2891 => x"91", + 2892 => x"90", + 2893 => x"a0", + 2894 => x"ca", + 2895 => x"88", + 2896 => x"0c", + 2897 => x"91", + 2898 => x"81", + 2899 => x"91", + 2900 => x"72", + 2901 => x"80", + 2902 => x"0c", + 2903 => x"91", + 2904 => x"90", + 2905 => x"fb", + 2906 => x"54", + 2907 => x"80", + 2908 => x"73", + 2909 => x"80", + 2910 => x"72", + 2911 => x"80", + 2912 => x"86", + 2913 => x"15", + 2914 => x"71", + 2915 => x"81", + 2916 => x"81", + 2917 => x"d0", + 2918 => x"ca", + 2919 => x"06", + 2920 => x"38", + 2921 => x"54", + 2922 => x"80", + 2923 => x"71", + 2924 => x"91", + 2925 => x"87", + 2926 => x"fa", + 2927 => x"ab", + 2928 => x"58", + 2929 => x"05", + 2930 => x"e6", + 2931 => x"80", + 2932 => x"88", + 2933 => x"38", + 2934 => x"08", + 2935 => x"ca", + 2936 => x"08", + 2937 => x"80", + 2938 => x"80", + 2939 => x"54", + 2940 => x"84", + 2941 => x"34", + 2942 => x"75", + 2943 => x"2e", + 2944 => x"53", + 2945 => x"53", + 2946 => x"f7", + 2947 => x"ca", + 2948 => x"73", + 2949 => x"0c", + 2950 => x"04", + 2951 => x"67", + 2952 => x"80", + 2953 => x"59", + 2954 => x"78", + 2955 => x"c8", + 2956 => x"06", + 2957 => x"3d", + 2958 => x"99", + 2959 => x"52", + 2960 => x"3f", + 2961 => x"08", + 2962 => x"88", + 2963 => x"38", + 2964 => x"52", + 2965 => x"52", + 2966 => x"3f", + 2967 => x"08", + 2968 => x"88", + 2969 => x"02", + 2970 => x"33", + 2971 => x"55", + 2972 => x"25", + 2973 => x"55", + 2974 => x"54", + 2975 => x"81", + 2976 => x"80", + 2977 => x"74", + 2978 => x"81", + 2979 => x"75", + 2980 => x"3f", + 2981 => x"08", + 2982 => x"02", + 2983 => x"91", + 2984 => x"81", + 2985 => x"82", + 2986 => x"06", + 2987 => x"80", + 2988 => x"88", + 2989 => x"39", + 2990 => x"58", + 2991 => x"38", + 2992 => x"70", + 2993 => x"54", + 2994 => x"81", + 2995 => x"52", + 2996 => x"a5", + 2997 => x"88", + 2998 => x"88", + 2999 => x"62", + 3000 => x"d4", + 3001 => x"54", + 3002 => x"15", + 3003 => x"62", + 3004 => x"e8", + 3005 => x"52", + 3006 => x"51", + 3007 => x"7a", + 3008 => x"83", + 3009 => x"80", + 3010 => x"38", + 3011 => x"08", + 3012 => x"53", + 3013 => x"3d", + 3014 => x"dd", + 3015 => x"ca", + 3016 => x"91", + 3017 => x"82", + 3018 => x"39", + 3019 => x"38", + 3020 => x"33", + 3021 => x"70", + 3022 => x"55", + 3023 => x"2e", + 3024 => x"55", + 3025 => x"77", + 3026 => x"81", + 3027 => x"73", + 3028 => x"38", + 3029 => x"54", + 3030 => x"a0", + 3031 => x"82", + 3032 => x"52", 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x"54", + 3092 => x"a2", + 3093 => x"7a", + 3094 => x"3f", + 3095 => x"08", + 3096 => x"55", + 3097 => x"89", + 3098 => x"88", + 3099 => x"1a", + 3100 => x"80", + 3101 => x"54", + 3102 => x"88", + 3103 => x"0d", + 3104 => x"0d", + 3105 => x"64", + 3106 => x"59", + 3107 => x"90", + 3108 => x"52", + 3109 => x"cf", + 3110 => x"88", + 3111 => x"ca", + 3112 => x"38", + 3113 => x"55", + 3114 => x"86", + 3115 => x"82", + 3116 => x"19", + 3117 => x"55", + 3118 => x"80", + 3119 => x"38", + 3120 => x"0b", + 3121 => x"82", + 3122 => x"39", + 3123 => x"1a", + 3124 => x"82", + 3125 => x"19", + 3126 => x"08", + 3127 => x"7c", + 3128 => x"74", + 3129 => x"2e", + 3130 => x"94", + 3131 => x"83", + 3132 => x"56", + 3133 => x"38", + 3134 => x"22", + 3135 => x"89", + 3136 => x"55", + 3137 => x"75", + 3138 => x"19", + 3139 => x"39", + 3140 => x"52", + 3141 => x"93", + 3142 => x"88", + 3143 => x"75", + 3144 => x"38", + 3145 => x"ff", + 3146 => x"98", + 3147 => x"19", + 3148 => x"51", + 3149 => x"91", + 3150 => x"80", + 3151 => x"38", + 3152 => x"08", + 3153 => x"2a", + 3154 => x"80", + 3155 => x"38", + 3156 => x"8a", + 3157 => x"5c", + 3158 => x"27", + 3159 => x"7a", + 3160 => x"54", + 3161 => x"52", + 3162 => x"51", + 3163 => x"91", + 3164 => x"fe", + 3165 => x"83", + 3166 => x"56", + 3167 => x"9f", + 3168 => x"08", + 3169 => x"74", + 3170 => x"38", + 3171 => x"b4", + 3172 => x"16", + 3173 => x"89", + 3174 => x"51", + 3175 => x"77", + 3176 => x"b9", + 3177 => x"1a", + 3178 => x"08", + 3179 => x"84", + 3180 => x"57", + 3181 => x"27", + 3182 => x"56", + 3183 => x"52", + 3184 => x"c7", + 3185 => x"88", + 3186 => x"38", + 3187 => x"19", + 3188 => x"06", + 3189 => x"52", + 3190 => x"a2", + 3191 => x"31", + 3192 => x"7f", + 3193 => x"94", + 3194 => x"94", + 3195 => x"5c", + 3196 => x"80", + 3197 => x"ca", + 3198 => x"3d", + 3199 => x"3d", + 3200 => x"65", + 3201 => x"5d", + 3202 => x"0c", + 3203 => x"05", + 3204 => x"f6", + 3205 => x"ca", + 3206 => x"91", + 3207 => x"8a", + 3208 => x"33", + 3209 => x"2e", + 3210 => x"56", + 3211 => x"90", + 3212 => x"81", + 3213 => x"06", + 3214 => x"87", + 3215 => x"2e", + 3216 => x"95", + 3217 => x"91", + 3218 => x"56", + 3219 => x"81", + 3220 => x"34", + 3221 => x"8e", + 3222 => x"08", + 3223 => x"56", + 3224 => x"84", + 3225 => x"5c", + 3226 => x"82", + 3227 => x"18", + 3228 => x"ff", + 3229 => x"74", + 3230 => x"7e", + 3231 => x"ff", + 3232 => x"2a", + 3233 => x"7a", + 3234 => x"8c", + 3235 => x"08", + 3236 => x"38", + 3237 => x"39", + 3238 => x"52", + 3239 => x"e7", + 3240 => x"88", + 3241 => x"ca", + 3242 => x"2e", + 3243 => x"74", + 3244 => x"91", + 3245 => x"2e", + 3246 => x"74", + 3247 => x"88", + 3248 => x"38", + 3249 => x"0c", + 3250 => x"15", + 3251 => x"08", + 3252 => x"06", + 3253 => x"51", + 3254 => x"91", + 3255 => x"fe", + 3256 => x"18", + 3257 => x"51", + 3258 => x"91", + 3259 => x"80", + 3260 => x"38", + 3261 => x"08", + 3262 => x"2a", + 3263 => x"80", + 3264 => x"38", + 3265 => x"8a", + 3266 => x"5b", + 3267 => x"27", + 3268 => x"7b", + 3269 => x"54", + 3270 => x"52", + 3271 => x"51", + 3272 => x"91", + 3273 => x"fe", + 3274 => x"b0", + 3275 => x"31", + 3276 => x"79", + 3277 => x"84", + 3278 => x"16", + 3279 => x"89", + 3280 => x"52", + 3281 => x"cc", + 3282 => x"55", + 3283 => x"16", + 3284 => x"2b", + 3285 => x"39", + 3286 => x"94", + 3287 => x"93", + 3288 => x"cd", + 3289 => x"ca", + 3290 => x"e3", + 3291 => x"b0", + 3292 => x"76", + 3293 => x"94", + 3294 => x"ff", + 3295 => x"71", + 3296 => x"7b", + 3297 => x"38", + 3298 => x"18", + 3299 => x"51", + 3300 => x"91", + 3301 => x"fd", + 3302 => x"53", + 3303 => x"18", + 3304 => x"06", + 3305 => x"51", + 3306 => x"7e", + 3307 => x"83", + 3308 => x"76", + 3309 => x"17", + 3310 => x"1e", + 3311 => x"18", + 3312 => x"0c", + 3313 => x"58", + 3314 => x"74", + 3315 => x"38", + 3316 => x"8c", + 3317 => x"90", + 3318 => x"33", + 3319 => x"55", + 3320 => x"34", + 3321 => x"91", + 3322 => x"90", + 3323 => x"f8", + 3324 => x"8b", + 3325 => x"53", + 3326 => x"f2", + 3327 => x"ca", + 3328 => x"91", + 3329 => x"80", + 3330 => x"16", + 3331 => x"2a", + 3332 => x"51", + 3333 => x"80", + 3334 => x"38", + 3335 => x"52", + 3336 => x"e7", + 3337 => x"88", + 3338 => x"ca", + 3339 => x"d4", + 3340 => x"08", + 3341 => x"a0", + 3342 => x"73", + 3343 => x"88", + 3344 => x"74", + 3345 => x"51", + 3346 => x"8c", + 3347 => x"9c", + 3348 => x"fb", + 3349 => x"b2", + 3350 => x"15", + 3351 => x"3f", + 3352 => x"15", + 3353 => x"3f", + 3354 => x"0b", + 3355 => x"78", + 3356 => x"3f", + 3357 => x"08", + 3358 => x"81", + 3359 => x"57", + 3360 => x"34", + 3361 => x"88", + 3362 => x"0d", + 3363 => x"0d", + 3364 => x"54", + 3365 => x"91", + 3366 => x"53", + 3367 => x"08", + 3368 => x"3d", + 3369 => x"73", + 3370 => x"3f", + 3371 => x"08", + 3372 => x"88", + 3373 => x"91", + 3374 => x"74", + 3375 => x"ca", + 3376 => x"3d", + 3377 => x"3d", + 3378 => x"51", + 3379 => x"8b", + 3380 => x"91", + 3381 => x"24", + 3382 => x"ca", + 3383 => x"ca", + 3384 => x"52", + 3385 => x"88", + 3386 => x"0d", + 3387 => x"0d", + 3388 => x"3d", + 3389 => x"94", + 3390 => x"c1", + 3391 => x"88", + 3392 => x"ca", + 3393 => x"e0", + 3394 => x"63", + 3395 => x"d4", + 3396 => x"8d", + 3397 => x"88", + 3398 => x"ca", + 3399 => x"38", + 3400 => x"05", + 3401 => x"2b", + 3402 => x"80", + 3403 => x"76", + 3404 => x"0c", + 3405 => x"02", + 3406 => x"70", + 3407 => x"81", + 3408 => x"56", + 3409 => x"9e", + 3410 => x"53", + 3411 => x"db", + 3412 => x"ca", + 3413 => x"15", + 3414 => x"91", + 3415 => x"84", + 3416 => x"06", + 3417 => x"55", + 3418 => x"88", + 3419 => x"0d", + 3420 => x"0d", + 3421 => x"5b", + 3422 => x"80", + 3423 => x"ff", + 3424 => x"9f", + 3425 => x"b5", + 3426 => x"88", + 3427 => x"ca", + 3428 => x"fc", + 3429 => x"7a", + 3430 => x"08", + 3431 => x"64", + 3432 => x"2e", + 3433 => x"a0", + 3434 => x"70", + 3435 => x"ea", + 3436 => x"88", + 3437 => x"ca", + 3438 => x"d4", + 3439 => x"7b", + 3440 => x"3f", + 3441 => x"08", + 3442 => x"88", + 3443 => x"38", + 3444 => x"51", + 3445 => x"91", + 3446 => x"45", + 3447 => x"51", + 3448 => x"91", + 3449 => x"57", + 3450 => x"08", + 3451 => x"80", + 3452 => x"da", + 3453 => x"ca", + 3454 => x"91", + 3455 => x"a4", + 3456 => x"7b", + 3457 => x"3f", + 3458 => x"88", + 3459 => x"38", + 3460 => x"51", + 3461 => x"91", + 3462 => x"57", + 3463 => x"08", + 3464 => x"38", + 3465 => x"09", + 3466 => x"38", + 3467 => x"e0", + 3468 => x"dc", + 3469 => x"ff", + 3470 => x"74", + 3471 => x"3f", + 3472 => x"78", + 3473 => x"33", + 3474 => x"56", + 3475 => x"91", + 3476 => x"05", + 3477 => x"81", + 3478 => x"56", + 3479 => x"f5", + 3480 => x"54", + 3481 => x"81", + 3482 => x"80", + 3483 => x"78", + 3484 => x"55", + 3485 => x"11", + 3486 => x"18", + 3487 => x"58", + 3488 => x"34", + 3489 => x"ff", + 3490 => x"55", + 3491 => x"34", + 3492 => x"77", + 3493 => x"81", + 3494 => x"ff", + 3495 => x"55", + 3496 => x"34", + 3497 => x"ca", + 3498 => x"84", + 3499 => x"84", + 3500 => x"70", + 3501 => x"56", + 3502 => x"76", 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x"98", + 3562 => x"58", + 3563 => x"39", + 3564 => x"54", + 3565 => x"73", + 3566 => x"cd", + 3567 => x"ca", + 3568 => x"91", + 3569 => x"81", + 3570 => x"38", + 3571 => x"08", + 3572 => x"9b", + 3573 => x"88", + 3574 => x"0c", + 3575 => x"0c", + 3576 => x"81", + 3577 => x"76", + 3578 => x"38", + 3579 => x"94", + 3580 => x"94", + 3581 => x"16", + 3582 => x"2a", + 3583 => x"51", + 3584 => x"72", + 3585 => x"38", + 3586 => x"51", + 3587 => x"91", + 3588 => x"54", + 3589 => x"08", + 3590 => x"ca", + 3591 => x"a7", + 3592 => x"74", + 3593 => x"3f", + 3594 => x"08", + 3595 => x"2e", + 3596 => x"74", + 3597 => x"79", + 3598 => x"14", + 3599 => x"38", + 3600 => x"0c", + 3601 => x"94", + 3602 => x"94", + 3603 => x"83", + 3604 => x"72", + 3605 => x"38", + 3606 => x"51", + 3607 => x"91", + 3608 => x"94", + 3609 => x"91", + 3610 => x"53", + 3611 => x"81", + 3612 => x"34", + 3613 => x"39", + 3614 => x"91", + 3615 => x"05", + 3616 => x"08", + 3617 => x"08", + 3618 => x"38", + 3619 => x"0c", + 3620 => x"80", + 3621 => x"72", + 3622 => x"73", + 3623 => x"53", + 3624 => x"8c", + 3625 => x"16", + 3626 => x"38", + 3627 => x"0c", + 3628 => x"91", + 3629 => x"8b", + 3630 => x"f9", + 3631 => x"56", + 3632 => x"80", + 3633 => x"38", + 3634 => x"3d", + 3635 => x"8a", + 3636 => x"51", + 3637 => x"91", + 3638 => x"55", + 3639 => x"08", + 3640 => x"77", + 3641 => x"52", + 3642 => x"b5", + 3643 => x"88", + 3644 => x"ca", + 3645 => x"c3", + 3646 => x"33", + 3647 => x"55", + 3648 => x"24", + 3649 => x"16", + 3650 => x"2a", + 3651 => x"51", + 3652 => x"80", + 3653 => x"9c", + 3654 => x"77", + 3655 => x"3f", + 3656 => x"08", + 3657 => x"77", + 3658 => x"22", + 3659 => x"74", + 3660 => x"ce", + 3661 => x"ca", + 3662 => x"74", + 3663 => x"81", + 3664 => x"85", + 3665 => x"74", + 3666 => x"38", + 3667 => x"74", + 3668 => x"ca", + 3669 => x"3d", + 3670 => x"3d", + 3671 => x"3d", + 3672 => x"70", + 3673 => x"ff", + 3674 => x"88", + 3675 => x"91", + 3676 => x"73", + 3677 => x"0d", + 3678 => x"0d", + 3679 => x"3d", + 3680 => x"71", + 3681 => x"e7", + 3682 => x"ca", + 3683 => x"91", + 3684 => x"80", + 3685 => x"93", + 3686 => x"88", + 3687 => x"51", + 3688 => x"91", + 3689 => x"53", + 3690 => x"91", + 3691 => x"52", + 3692 => x"ac", + 3693 => x"88", + 3694 => x"ca", + 3695 => x"2e", + 3696 => x"85", + 3697 => x"87", + 3698 => x"88", + 3699 => x"74", + 3700 => x"d5", + 3701 => x"52", + 3702 => x"89", + 3703 => x"88", + 3704 => x"70", + 3705 => x"07", + 3706 => x"91", + 3707 => x"06", + 3708 => x"54", + 3709 => x"88", + 3710 => x"0d", + 3711 => x"0d", + 3712 => x"53", + 3713 => x"53", + 3714 => x"56", + 3715 => x"91", + 3716 => x"55", + 3717 => x"08", + 3718 => x"52", + 3719 => x"81", + 3720 => x"88", + 3721 => x"ca", + 3722 => x"38", + 3723 => x"05", + 3724 => x"2b", + 3725 => x"80", + 3726 => x"86", + 3727 => x"76", + 3728 => x"38", + 3729 => x"51", + 3730 => x"74", + 3731 => x"0c", + 3732 => x"04", + 3733 => x"63", + 3734 => x"80", + 3735 => x"ec", + 3736 => x"3d", + 3737 => x"3f", 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x"51", + 3797 => x"ff", + 3798 => x"56", + 3799 => x"38", + 3800 => x"7c", + 3801 => x"0c", + 3802 => x"81", + 3803 => x"74", + 3804 => x"7a", + 3805 => x"0c", + 3806 => x"04", + 3807 => x"79", + 3808 => x"05", + 3809 => x"57", + 3810 => x"91", + 3811 => x"56", + 3812 => x"08", + 3813 => x"91", + 3814 => x"75", + 3815 => x"90", + 3816 => x"81", + 3817 => x"06", + 3818 => x"87", + 3819 => x"2e", + 3820 => x"94", + 3821 => x"73", + 3822 => x"27", + 3823 => x"73", + 3824 => x"ca", + 3825 => x"88", + 3826 => x"76", + 3827 => x"3f", + 3828 => x"08", + 3829 => x"0c", + 3830 => x"39", + 3831 => x"52", + 3832 => x"bf", + 3833 => x"ca", + 3834 => x"2e", + 3835 => x"83", + 3836 => x"91", + 3837 => x"81", + 3838 => x"06", + 3839 => x"56", + 3840 => x"a0", + 3841 => x"91", + 3842 => x"98", + 3843 => x"94", + 3844 => x"08", + 3845 => x"88", + 3846 => x"51", + 3847 => x"91", + 3848 => x"56", + 3849 => x"8c", + 3850 => x"17", + 3851 => x"07", + 3852 => x"18", + 3853 => x"2e", + 3854 => x"91", + 3855 => x"55", + 3856 => x"88", + 3857 => x"0d", + 3858 => x"0d", + 3859 => x"3d", + 3860 => x"52", + 3861 => x"da", + 3862 => x"ca", + 3863 => x"91", + 3864 => x"81", + 3865 => x"45", + 3866 => x"52", + 3867 => x"52", + 3868 => x"3f", + 3869 => x"08", + 3870 => x"88", + 3871 => x"38", + 3872 => x"05", + 3873 => x"2a", + 3874 => x"51", + 3875 => x"55", + 3876 => x"38", + 3877 => x"54", + 3878 => x"81", + 3879 => x"80", + 3880 => x"70", + 3881 => x"54", + 3882 => x"81", + 3883 => x"52", + 3884 => x"c5", + 3885 => x"88", + 3886 => x"2a", + 3887 => x"51", + 3888 => x"80", + 3889 => x"38", + 3890 => x"ca", + 3891 => x"15", + 3892 => x"86", + 3893 => x"91", + 3894 => x"5c", + 3895 => x"3d", + 3896 => x"c7", + 3897 => x"ca", + 3898 => x"91", + 3899 => x"80", + 3900 => x"ca", + 3901 => x"73", + 3902 => x"3f", + 3903 => x"08", + 3904 => x"88", + 3905 => x"87", + 3906 => x"39", + 3907 => x"08", + 3908 => x"38", + 3909 => x"08", + 3910 => x"77", + 3911 => x"3f", + 3912 => x"08", + 3913 => x"08", + 3914 => x"ca", + 3915 => x"80", + 3916 => x"55", + 3917 => x"94", + 3918 => x"2e", + 3919 => x"53", + 3920 => x"51", + 3921 => x"91", + 3922 => x"55", + 3923 => x"78", + 3924 => x"fe", + 3925 => x"88", + 3926 => x"91", + 3927 => x"a0", + 3928 => x"e9", + 3929 => x"53", + 3930 => x"05", + 3931 => x"51", + 3932 => x"91", + 3933 => x"54", + 3934 => x"08", + 3935 => x"78", + 3936 => x"8e", + 3937 => x"58", + 3938 => x"91", + 3939 => x"54", + 3940 => x"08", + 3941 => x"54", + 3942 => x"91", + 3943 => x"84", + 3944 => x"06", + 3945 => x"02", + 3946 => x"33", + 3947 => x"81", + 3948 => x"86", + 3949 => x"f6", + 3950 => x"74", + 3951 => x"70", + 3952 => x"c3", + 3953 => x"88", + 3954 => x"56", + 3955 => x"08", + 3956 => x"54", + 3957 => x"08", + 3958 => x"81", + 3959 => x"82", + 3960 => x"88", + 3961 => x"09", + 3962 => x"38", + 3963 => x"b4", + 3964 => x"b0", + 3965 => x"88", + 3966 => x"51", + 3967 => x"91", + 3968 => x"54", + 3969 => x"08", + 3970 => x"8b", + 3971 => x"b4", + 3972 => x"b7", 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x"86", + 4032 => x"aa", + 4033 => x"a4", + 4034 => x"a8", + 4035 => x"05", + 4036 => x"ea", + 4037 => x"77", + 4038 => x"70", + 4039 => x"b4", + 4040 => x"3d", + 4041 => x"51", + 4042 => x"91", + 4043 => x"55", + 4044 => x"08", + 4045 => x"6f", + 4046 => x"06", + 4047 => x"a2", + 4048 => x"92", + 4049 => x"81", + 4050 => x"ca", + 4051 => x"2e", + 4052 => x"81", + 4053 => x"51", + 4054 => x"91", + 4055 => x"55", + 4056 => x"08", + 4057 => x"68", + 4058 => x"a8", + 4059 => x"05", + 4060 => x"51", + 4061 => x"3f", + 4062 => x"33", + 4063 => x"8b", + 4064 => x"84", + 4065 => x"06", + 4066 => x"73", + 4067 => x"a0", + 4068 => x"8b", + 4069 => x"54", + 4070 => x"15", + 4071 => x"33", + 4072 => x"70", + 4073 => x"55", + 4074 => x"2e", + 4075 => x"6e", + 4076 => x"df", + 4077 => x"78", + 4078 => x"3f", + 4079 => x"08", + 4080 => x"ff", + 4081 => x"82", + 4082 => x"88", + 4083 => x"80", + 4084 => x"ca", + 4085 => x"78", + 4086 => x"af", + 4087 => x"88", + 4088 => x"d4", + 4089 => x"55", + 4090 => x"08", + 4091 => x"81", + 4092 => x"73", + 4093 => x"81", + 4094 => x"63", + 4095 => x"76", + 4096 => x"3f", + 4097 => x"0b", + 4098 => x"87", + 4099 => x"88", + 4100 => x"77", + 4101 => x"3f", + 4102 => x"08", + 4103 => x"88", + 4104 => x"78", + 4105 => x"aa", + 4106 => x"88", + 4107 => x"91", + 4108 => x"a8", + 4109 => x"ed", + 4110 => x"80", + 4111 => x"02", + 4112 => x"df", + 4113 => x"57", + 4114 => x"3d", + 4115 => x"96", + 4116 => x"e9", + 4117 => x"88", + 4118 => x"ca", + 4119 => x"cf", + 4120 => x"65", + 4121 => x"d4", + 4122 => x"b5", + 4123 => x"88", + 4124 => x"ca", + 4125 => x"38", + 4126 => x"05", + 4127 => x"06", + 4128 => x"73", + 4129 => x"a7", + 4130 => x"09", + 4131 => x"71", + 4132 => x"06", + 4133 => x"55", + 4134 => x"15", + 4135 => x"81", + 4136 => x"34", + 4137 => x"b4", + 4138 => x"ca", + 4139 => x"74", + 4140 => x"0c", + 4141 => x"04", + 4142 => x"64", + 4143 => x"93", + 4144 => x"52", + 4145 => x"d1", + 4146 => x"ca", + 4147 => x"91", + 4148 => x"80", + 4149 => x"58", + 4150 => x"3d", + 4151 => x"c8", + 4152 => x"ca", + 4153 => x"91", + 4154 => x"b4", + 4155 => x"c7", + 4156 => x"a0", + 4157 => x"55", + 4158 => x"84", + 4159 => x"17", + 4160 => x"2b", + 4161 => x"96", + 4162 => x"b0", + 4163 => x"54", + 4164 => x"15", + 4165 => x"ff", + 4166 => x"91", + 4167 => x"55", + 4168 => x"88", + 4169 => x"0d", + 4170 => x"0d", + 4171 => x"5a", + 4172 => x"3d", + 4173 => x"99", + 4174 => x"81", + 4175 => x"88", + 4176 => x"88", + 4177 => x"91", + 4178 => x"07", + 4179 => x"55", + 4180 => x"2e", + 4181 => x"81", + 4182 => x"55", + 4183 => x"2e", + 4184 => x"7b", + 4185 => x"80", + 4186 => x"70", + 4187 => x"be", + 4188 => x"ca", + 4189 => x"91", + 4190 => x"80", + 4191 => x"52", + 4192 => x"dc", + 4193 => x"88", + 4194 => x"ca", + 4195 => x"38", + 4196 => x"08", + 4197 => x"08", + 4198 => x"56", + 4199 => x"19", + 4200 => x"59", + 4201 => x"74", + 4202 => x"56", + 4203 => x"ec", + 4204 => x"75", + 4205 => x"74", + 4206 => x"2e", + 4207 => x"16", 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x"39", + 4267 => x"08", + 4268 => x"15", + 4269 => x"ff", + 4270 => x"73", + 4271 => x"38", + 4272 => x"83", + 4273 => x"56", + 4274 => x"75", + 4275 => x"91", + 4276 => x"33", + 4277 => x"2e", + 4278 => x"52", + 4279 => x"51", + 4280 => x"3f", + 4281 => x"08", + 4282 => x"ff", + 4283 => x"38", + 4284 => x"88", + 4285 => x"8a", + 4286 => x"38", + 4287 => x"ec", + 4288 => x"75", + 4289 => x"74", + 4290 => x"73", + 4291 => x"05", + 4292 => x"17", + 4293 => x"70", + 4294 => x"34", + 4295 => x"70", + 4296 => x"ff", + 4297 => x"55", + 4298 => x"26", + 4299 => x"8b", + 4300 => x"86", + 4301 => x"e5", + 4302 => x"38", + 4303 => x"99", + 4304 => x"05", + 4305 => x"70", + 4306 => x"73", + 4307 => x"81", + 4308 => x"ff", + 4309 => x"ed", + 4310 => x"80", + 4311 => x"91", + 4312 => x"55", + 4313 => x"3f", + 4314 => x"08", + 4315 => x"88", + 4316 => x"38", + 4317 => x"51", + 4318 => x"3f", + 4319 => x"08", + 4320 => x"88", + 4321 => x"76", + 4322 => x"67", + 4323 => x"34", + 4324 => x"91", + 4325 => x"84", + 4326 => x"06", + 4327 => x"80", + 4328 => x"2e", + 4329 => x"81", + 4330 => x"ff", + 4331 => x"91", + 4332 => x"54", + 4333 => x"08", + 4334 => x"53", + 4335 => x"08", + 4336 => x"ff", + 4337 => x"67", + 4338 => x"8b", + 4339 => x"53", + 4340 => x"51", + 4341 => x"3f", + 4342 => x"0b", + 4343 => x"79", + 4344 => x"ee", + 4345 => x"88", + 4346 => x"55", + 4347 => x"88", + 4348 => x"0d", + 4349 => x"0d", + 4350 => x"88", + 4351 => x"05", + 4352 => x"fc", + 4353 => x"54", + 4354 => x"d2", + 4355 => x"ca", + 4356 => x"91", + 4357 => x"82", + 4358 => x"1a", + 4359 => x"82", + 4360 => x"80", + 4361 => x"8c", + 4362 => x"78", + 4363 => x"1a", + 4364 => x"2a", + 4365 => x"51", + 4366 => x"90", + 4367 => x"82", + 4368 => x"58", + 4369 => x"81", + 4370 => x"39", + 4371 => x"22", + 4372 => x"70", + 4373 => x"56", + 4374 => x"82", + 4375 => x"14", + 4376 => x"30", + 4377 => x"9f", + 4378 => x"88", + 4379 => x"19", + 4380 => x"5a", + 4381 => x"81", + 4382 => x"38", + 4383 => x"77", + 4384 => x"82", + 4385 => x"56", + 4386 => x"74", + 4387 => x"ff", + 4388 => x"81", + 4389 => x"55", + 4390 => x"75", + 4391 => x"82", + 4392 => x"88", + 4393 => x"ff", + 4394 => x"ca", + 4395 => x"2e", + 4396 => x"91", + 4397 => x"8e", + 4398 => x"56", + 4399 => x"09", + 4400 => x"38", + 4401 => x"59", + 4402 => x"77", + 4403 => x"06", + 4404 => x"87", + 4405 => x"39", + 4406 => x"ba", + 4407 => x"55", + 4408 => x"2e", + 4409 => x"15", + 4410 => x"2e", + 4411 => x"83", + 4412 => x"75", + 4413 => x"7e", + 4414 => x"a8", + 4415 => x"88", + 4416 => x"ca", + 4417 => x"ce", + 4418 => x"16", + 4419 => x"56", + 4420 => x"38", + 4421 => x"19", + 4422 => x"8c", + 4423 => x"7d", + 4424 => x"38", + 4425 => x"0c", + 4426 => x"0c", + 4427 => x"80", + 4428 => x"73", + 4429 => x"98", + 4430 => x"05", + 4431 => x"57", + 4432 => x"26", + 4433 => x"7b", + 4434 => x"0c", + 4435 => x"81", + 4436 => x"84", + 4437 => x"54", + 4438 => x"88", + 4439 => x"0d", + 4440 => x"0d", + 4441 => x"88", + 4442 => x"05", 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x"08", + 4502 => x"74", + 4503 => x"41", + 4504 => x"56", + 4505 => x"8a", + 4506 => x"61", + 4507 => x"55", + 4508 => x"27", + 4509 => x"93", + 4510 => x"80", + 4511 => x"38", + 4512 => x"70", + 4513 => x"43", + 4514 => x"95", + 4515 => x"06", + 4516 => x"2e", + 4517 => x"77", + 4518 => x"74", + 4519 => x"83", + 4520 => x"06", + 4521 => x"82", + 4522 => x"2e", + 4523 => x"78", + 4524 => x"2e", + 4525 => x"80", + 4526 => x"ae", + 4527 => x"2a", + 4528 => x"91", + 4529 => x"56", + 4530 => x"2e", + 4531 => x"77", + 4532 => x"91", + 4533 => x"79", + 4534 => x"70", + 4535 => x"5a", + 4536 => x"86", + 4537 => x"27", + 4538 => x"52", + 4539 => x"fc", + 4540 => x"ca", + 4541 => x"29", + 4542 => x"70", + 4543 => x"55", + 4544 => x"0b", + 4545 => x"08", + 4546 => x"05", + 4547 => x"ff", + 4548 => x"27", + 4549 => x"88", + 4550 => x"ae", + 4551 => x"2a", + 4552 => x"91", + 4553 => x"56", + 4554 => x"2e", + 4555 => x"77", + 4556 => x"91", + 4557 => x"79", + 4558 => x"70", + 4559 => x"5a", + 4560 => x"86", + 4561 => x"27", + 4562 => x"52", + 4563 => x"fc", + 4564 => x"ca", + 4565 => x"84", + 4566 => x"ca", + 4567 => x"f5", + 4568 => x"81", + 4569 => x"88", + 4570 => x"ca", + 4571 => x"71", + 4572 => x"83", + 4573 => x"5e", + 4574 => x"89", + 4575 => x"5c", + 4576 => x"1c", + 4577 => x"05", + 4578 => x"ff", + 4579 => x"70", + 4580 => x"31", + 4581 => x"57", + 4582 => x"83", + 4583 => x"06", + 4584 => x"1c", + 4585 => x"5c", + 4586 => x"1d", + 4587 => x"29", + 4588 => x"31", + 4589 => x"55", + 4590 => x"87", + 4591 => x"7c", + 4592 => x"7a", + 4593 => x"31", + 4594 => x"fb", + 4595 => x"ca", + 4596 => x"7d", + 4597 => x"81", + 4598 => x"91", + 4599 => x"83", + 4600 => x"80", + 4601 => x"87", + 4602 => x"81", + 4603 => x"fd", + 4604 => x"f8", + 4605 => x"2e", + 4606 => x"80", + 4607 => x"ff", + 4608 => x"ca", + 4609 => x"a0", + 4610 => x"38", + 4611 => x"74", + 4612 => x"86", + 4613 => x"fd", + 4614 => x"81", + 4615 => x"80", + 4616 => x"83", + 4617 => x"39", + 4618 => x"08", + 4619 => x"92", + 4620 => x"b8", + 4621 => x"59", + 4622 => x"27", + 4623 => x"86", + 4624 => x"55", + 4625 => x"09", + 4626 => x"38", + 4627 => x"f5", + 4628 => x"38", + 4629 => x"55", + 4630 => x"86", + 4631 => x"80", + 4632 => x"7a", + 4633 => x"b9", + 4634 => x"91", + 4635 => x"7a", + 4636 => x"8a", + 4637 => x"52", + 4638 => x"ff", + 4639 => x"79", + 4640 => x"7b", + 4641 => x"06", + 4642 => x"51", + 4643 => x"3f", + 4644 => x"1c", + 4645 => x"32", + 4646 => x"96", + 4647 => x"06", + 4648 => x"91", + 4649 => x"a1", + 4650 => x"55", + 4651 => x"ff", + 4652 => x"74", + 4653 => x"06", + 4654 => x"51", + 4655 => x"3f", + 4656 => x"52", + 4657 => x"ff", + 4658 => x"f8", + 4659 => x"34", + 4660 => x"1b", + 4661 => x"d9", + 4662 => x"52", + 4663 => x"ff", + 4664 => x"60", + 4665 => x"51", + 4666 => x"3f", + 4667 => x"09", + 4668 => x"cb", + 4669 => x"b2", + 4670 => x"c3", + 4671 => x"a0", + 4672 => x"52", + 4673 => x"ff", + 4674 => x"82", + 4675 => x"51", + 4676 => x"3f", + 4677 => x"1b", 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x"7e", + 4737 => x"d8", + 4738 => x"80", + 4739 => x"ff", + 4740 => x"7f", + 4741 => x"7d", + 4742 => x"81", + 4743 => x"f8", + 4744 => x"ff", + 4745 => x"ff", + 4746 => x"51", + 4747 => x"3f", + 4748 => x"88", + 4749 => x"39", + 4750 => x"f8", + 4751 => x"2e", + 4752 => x"55", + 4753 => x"51", + 4754 => x"3f", + 4755 => x"57", + 4756 => x"83", + 4757 => x"76", + 4758 => x"7a", + 4759 => x"ff", + 4760 => x"91", + 4761 => x"82", + 4762 => x"80", + 4763 => x"88", + 4764 => x"51", + 4765 => x"3f", + 4766 => x"78", + 4767 => x"74", + 4768 => x"18", + 4769 => x"2e", + 4770 => x"79", + 4771 => x"2e", + 4772 => x"55", + 4773 => x"62", + 4774 => x"74", + 4775 => x"75", + 4776 => x"7e", + 4777 => x"b8", + 4778 => x"88", + 4779 => x"38", + 4780 => x"78", + 4781 => x"74", + 4782 => x"56", + 4783 => x"93", + 4784 => x"66", + 4785 => x"26", + 4786 => x"56", + 4787 => x"83", + 4788 => x"64", + 4789 => x"77", + 4790 => x"84", + 4791 => x"52", + 4792 => x"9d", + 4793 => x"d4", + 4794 => x"51", + 4795 => x"3f", + 4796 => x"55", + 4797 => x"81", + 4798 => x"34", + 4799 => x"16", + 4800 => x"16", + 4801 => x"16", + 4802 => x"05", + 4803 => x"c1", + 4804 => x"fe", + 4805 => x"fe", + 4806 => x"34", + 4807 => x"08", + 4808 => x"07", + 4809 => x"16", + 4810 => x"88", + 4811 => x"34", + 4812 => x"c6", + 4813 => x"9c", + 4814 => x"52", + 4815 => x"51", + 4816 => x"3f", + 4817 => x"53", + 4818 => x"51", + 4819 => x"3f", + 4820 => x"ca", + 4821 => x"38", + 4822 => x"52", + 4823 => x"99", + 4824 => x"56", + 4825 => x"08", + 4826 => x"39", + 4827 => x"39", + 4828 => x"39", + 4829 => x"08", + 4830 => x"ca", + 4831 => x"3d", + 4832 => x"3d", + 4833 => x"71", + 4834 => x"8e", + 4835 => x"29", + 4836 => x"05", + 4837 => x"04", + 4838 => x"51", + 4839 => x"91", + 4840 => x"80", + 4841 => x"bb", + 4842 => x"f2", + 4843 => x"8c", + 4844 => x"39", + 4845 => x"51", + 4846 => x"91", + 4847 => x"80", + 4848 => x"bc", + 4849 => x"d6", + 4850 => x"d0", + 4851 => x"39", + 4852 => x"51", + 4853 => x"91", + 4854 => x"80", + 4855 => x"bd", + 4856 => x"39", + 4857 => x"51", + 4858 => x"bd", + 4859 => x"39", + 4860 => x"51", + 4861 => x"be", + 4862 => x"39", + 4863 => x"51", + 4864 => x"be", + 4865 => x"39", + 4866 => x"51", + 4867 => x"be", + 4868 => x"39", + 4869 => x"51", + 4870 => x"bf", + 4871 => x"87", + 4872 => x"3d", + 4873 => x"3d", + 4874 => x"56", + 4875 => x"e7", + 4876 => x"74", + 4877 => x"e8", + 4878 => x"39", + 4879 => x"74", + 4880 => x"a3", + 4881 => x"88", + 4882 => x"51", + 4883 => x"3f", + 4884 => x"08", + 4885 => x"75", + 4886 => x"a0", + 4887 => x"a0", + 4888 => x"0d", + 4889 => x"0d", + 4890 => x"02", + 4891 => x"c7", + 4892 => x"73", + 4893 => x"5d", + 4894 => x"5c", + 4895 => x"91", + 4896 => x"ff", + 4897 => x"91", + 4898 => x"ff", + 4899 => x"80", + 4900 => x"27", + 4901 => x"79", + 4902 => x"38", + 4903 => x"a7", + 4904 => x"39", + 4905 => x"72", + 4906 => x"38", + 4907 => x"91", + 4908 => x"ff", + 4909 => x"89", + 4910 => x"dc", + 4911 => x"dc", + 4912 => x"55", + 4913 => x"74", + 4914 => x"78", + 4915 => x"72", + 4916 => x"bf", + 4917 => x"8c", + 4918 => x"39", + 4919 => x"51", + 4920 => x"3f", + 4921 => x"a1", + 4922 => x"53", + 4923 => x"8e", + 4924 => x"52", + 4925 => x"51", + 4926 => x"3f", + 4927 => x"bf", + 4928 => x"86", + 4929 => x"15", + 4930 => x"fe", + 4931 => x"ff", + 4932 => x"bf", + 4933 => x"86", + 4934 => x"55", + 4935 => x"aa", + 4936 => x"70", + 4937 => x"26", + 4938 => x"9f", + 4939 => x"38", + 4940 => x"8b", + 4941 => x"fe", + 4942 => x"73", + 4943 => x"a0", + 4944 => x"d7", + 4945 => x"55", + 4946 => x"bf", + 4947 => x"85", + 4948 => x"16", + 4949 => x"56", + 4950 => x"3f", + 4951 => x"08", + 4952 => x"98", + 4953 => x"74", + 4954 => x"81", + 4955 => x"fe", + 4956 => x"91", + 4957 => x"98", + 4958 => x"2c", + 4959 => x"70", + 4960 => x"07", + 4961 => x"56", + 4962 => x"74", + 4963 => x"38", + 4964 => x"74", + 4965 => x"81", + 4966 => x"80", + 4967 => x"7a", + 4968 => x"76", + 4969 => x"38", + 4970 => x"91", + 4971 => x"8d", + 4972 => x"ec", + 4973 => x"02", + 4974 => x"e3", + 4975 => x"72", + 4976 => x"07", + 4977 => x"87", + 4978 => x"07", + 4979 => x"5a", + 4980 => x"57", + 4981 => x"38", + 4982 => x"52", + 4983 => x"52", + 4984 => x"3f", + 4985 => x"08", + 4986 => x"88", + 4987 => x"91", + 4988 => x"87", + 4989 => x"0c", + 4990 => x"08", + 4991 => x"d4", + 4992 => x"80", + 4993 => x"76", + 4994 => x"3f", + 4995 => x"08", + 4996 => x"88", + 4997 => x"7a", + 4998 => x"2e", + 4999 => x"19", + 5000 => x"59", + 5001 => x"3d", + 5002 => x"cc", + 5003 => x"30", + 5004 => x"80", + 5005 => x"79", + 5006 => x"38", + 5007 => x"90", + 5008 => x"f8", + 5009 => x"98", + 5010 => x"78", + 5011 => x"3f", + 5012 => x"91", + 5013 => x"96", + 5014 => x"f9", + 5015 => x"02", + 5016 => x"05", + 5017 => x"ff", + 5018 => x"7a", + 5019 => x"fe", + 5020 => x"ca", + 5021 => x"38", + 5022 => x"88", + 5023 => x"2e", + 5024 => x"39", + 5025 => x"54", + 5026 => x"53", + 5027 => x"51", + 5028 => x"ca", + 5029 => x"83", + 5030 => x"76", + 5031 => x"0c", + 5032 => x"04", + 5033 => x"02", + 5034 => x"91", + 5035 => x"91", + 5036 => x"55", + 5037 => x"3f", + 5038 => x"22", + 5039 => x"e2", + 5040 => x"94", + 5041 => x"a0", + 5042 => x"89", + 5043 => x"c0", + 5044 => x"88", + 5045 => x"80", + 5046 => x"fe", + 5047 => x"86", + 5048 => x"fe", + 5049 => x"c0", + 5050 => x"53", + 5051 => x"3f", + 5052 => x"f6", + 5053 => x"c0", + 5054 => x"f8", + 5055 => x"51", + 5056 => x"3f", + 5057 => x"70", + 5058 => x"52", + 5059 => x"95", + 5060 => x"fe", + 5061 => x"91", + 5062 => x"fe", + 5063 => x"80", + 5064 => x"dd", + 5065 => x"2a", + 5066 => x"51", + 5067 => x"2e", + 5068 => x"51", + 5069 => x"3f", + 5070 => x"51", + 5071 => x"3f", + 5072 => x"f5", + 5073 => x"83", + 5074 => x"06", + 5075 => x"80", + 5076 => x"81", + 5077 => x"a9", + 5078 => x"84", + 5079 => x"a1", + 5080 => x"fe", + 5081 => x"72", + 5082 => x"81", + 5083 => x"71", + 5084 => x"38", + 5085 => x"f5", + 5086 => x"c1", + 5087 => x"f7", + 5088 => x"51", + 5089 => x"3f", + 5090 => x"70", + 5091 => x"52", + 5092 => x"95", + 5093 => x"fe", + 5094 => x"91", + 5095 => x"fe", + 5096 => x"80", + 5097 => x"d9", + 5098 => x"2a", + 5099 => x"51", + 5100 => x"2e", + 5101 => x"51", + 5102 => x"3f", + 5103 => x"51", + 5104 => x"3f", + 5105 => x"f4", + 5106 => x"87", + 5107 => x"06", + 5108 => x"80", + 5109 => x"81", + 5110 => x"a5", + 5111 => x"d4", + 5112 => x"9d", + 5113 => x"fe", + 5114 => x"72", + 5115 => x"81", + 5116 => x"71", + 5117 => x"38", + 5118 => x"f4", + 5119 => x"c1", + 5120 => x"f5", + 5121 => x"51", + 5122 => x"3f", + 5123 => x"3f", + 5124 => x"04", + 5125 => x"78", + 5126 => x"55", + 5127 => x"80", + 5128 => x"38", + 5129 => x"77", + 5130 => x"33", + 5131 => x"39", + 5132 => x"80", + 5133 => x"81", + 5134 => x"57", + 5135 => x"2e", + 5136 => x"53", + 5137 => x"84", + 5138 => x"38", + 5139 => x"06", + 5140 => x"2e", + 5141 => x"88", + 5142 => x"70", + 5143 => x"34", + 5144 => x"90", + 5145 => x"a8", + 5146 => x"53", + 5147 => x"55", + 5148 => x"3f", + 5149 => x"08", + 5150 => x"15", + 5151 => x"81", + 5152 => x"38", + 5153 => x"81", + 5154 => x"53", + 5155 => x"d2", + 5156 => x"72", + 5157 => x"0c", + 5158 => x"04", + 5159 => x"80", + 5160 => x"e1", + 5161 => x"5c", + 5162 => x"51", + 5163 => x"3f", + 5164 => x"08", + 5165 => x"59", + 5166 => x"09", + 5167 => x"38", + 5168 => x"52", + 5169 => x"52", + 5170 => x"ca", + 5171 => x"78", + 5172 => x"b8", + 5173 => x"e3", + 5174 => x"88", + 5175 => x"88", + 5176 => x"ac", + 5177 => x"39", + 5178 => x"5c", + 5179 => x"51", + 5180 => x"3f", + 5181 => x"46", + 5182 => x"53", + 5183 => x"51", + 5184 => x"3f", + 5185 => x"64", + 5186 => x"ce", + 5187 => x"fe", + 5188 => x"fd", + 5189 => x"ca", + 5190 => x"2b", + 5191 => x"51", + 5192 => x"c2", + 5193 => x"38", + 5194 => x"24", + 5195 => x"78", + 5196 => x"ef", + 5197 => x"24", + 5198 => x"84", + 5199 => x"38", + 5200 => x"90", + 5201 => x"2e", + 5202 => x"78", + 5203 => x"a9", + 5204 => x"39", + 5205 => x"82", + 5206 => x"ab", + 5207 => x"38", + 5208 => x"78", + 5209 => x"f2", + 5210 => x"24", + 5211 => x"bc", + 5212 => x"38", + 5213 => x"84", + 5214 => x"c8", + 5215 => x"c0", + 5216 => x"38", + 5217 => x"2e", + 5218 => x"8e", + 5219 => x"80", + 5220 => x"a5", + 5221 => x"f8", + 5222 => x"78", + 5223 => x"8c", + 5224 => x"80", + 5225 => x"38", + 5226 => x"2e", + 5227 => x"78", + 5228 => x"8c", + 5229 => x"8c", + 5230 => x"d4", + 5231 => x"38", + 5232 => x"2e", + 5233 => x"8d", + 5234 => x"81", + 5235 => x"e0", + 5236 => x"83", + 5237 => x"78", + 5238 => x"8d", + 5239 => x"81", + 5240 => x"bd", + 5241 => x"39", + 5242 => x"2e", + 5243 => x"78", + 5244 => x"fd", + 5245 => x"cc", + 5246 => x"fe", + 5247 => x"fe", + 5248 => x"ff", + 5249 => x"91", + 5250 => x"88", + 5251 => x"e8", + 5252 => x"39", + 5253 => x"f0", + 5254 => x"f8", + 5255 => x"83", + 5256 => x"ca", + 5257 => x"2e", + 5258 => x"63", + 5259 => x"80", + 5260 => x"cb", + 5261 => x"02", + 5262 => x"33", + 5263 => x"b7", + 5264 => x"88", + 5265 => x"06", + 5266 => x"38", + 5267 => x"51", + 5268 => x"3f", + 5269 => x"94", + 5270 => x"88", + 5271 => x"39", + 5272 => x"f4", + 5273 => x"f8", + 5274 => x"83", + 5275 => x"ca", + 5276 => x"2e", + 5277 => x"80", + 5278 => x"02", + 5279 => x"33", + 5280 => x"c0", + 5281 => x"88", + 5282 => x"c3", + 5283 => x"8a", + 5284 => x"fe", + 5285 => x"fe", + 5286 => x"ff", + 5287 => x"91", + 5288 => x"80", + 5289 => x"63", + 5290 => x"c0", + 5291 => x"fe", + 5292 => x"fe", + 5293 => x"ff", + 5294 => x"91", + 5295 => x"86", + 5296 => x"88", + 5297 => x"53", + 5298 => x"52", + 5299 => x"80", + 5300 => x"80", + 5301 => x"53", + 5302 => x"84", + 5303 => x"cb", + 5304 => x"ff", + 5305 => x"91", + 5306 => x"81", + 5307 => x"c2", + 5308 => x"fa", + 5309 => x"5c", + 5310 => x"b7", + 5311 => x"05", + 5312 => x"ae", + 5313 => x"88", + 5314 => x"fe", + 5315 => x"5b", + 5316 => x"3f", + 5317 => x"ca", + 5318 => x"7a", + 5319 => x"3f", + 5320 => x"b7", + 5321 => x"05", + 5322 => x"86", + 5323 => x"88", + 5324 => x"fe", + 5325 => x"5b", + 5326 => x"3f", + 5327 => x"08", + 5328 => x"f8", + 5329 => x"fe", + 5330 => x"91", + 5331 => x"b8", + 5332 => x"05", + 5333 => x"ea", + 5334 => x"c6", + 5335 => x"ca", + 5336 => x"56", + 5337 => x"ca", + 5338 => x"ff", + 5339 => x"53", + 5340 => x"51", + 5341 => x"91", + 5342 => x"80", + 5343 => x"38", + 5344 => x"08", + 5345 => x"3f", + 5346 => x"b7", + 5347 => x"11", + 5348 => x"05", + 5349 => x"dd", + 5350 => x"88", + 5351 => x"fa", + 5352 => x"3d", + 5353 => x"53", + 5354 => x"51", + 5355 => x"3f", + 5356 => x"08", + 5357 => x"b4", + 5358 => x"fe", + 5359 => x"fe", + 5360 => x"ff", + 5361 => x"91", + 5362 => x"86", + 5363 => x"88", + 5364 => x"c3", + 5365 => x"f8", + 5366 => x"63", + 5367 => x"7b", + 5368 => x"38", + 5369 => x"7a", + 5370 => x"5c", + 5371 => x"26", + 5372 => x"e1", + 5373 => x"fe", + 5374 => x"fe", + 5375 => x"fe", + 5376 => x"91", + 5377 => x"80", + 5378 => x"38", + 5379 => x"f0", + 5380 => x"f8", + 5381 => x"ff", + 5382 => x"ca", + 5383 => x"2e", + 5384 => x"b7", + 5385 => x"11", + 5386 => x"05", + 5387 => x"c5", + 5388 => x"88", + 5389 => x"f9", + 5390 => x"c3", + 5391 => x"f7", + 5392 => x"5a", + 5393 => x"81", + 5394 => x"59", + 5395 => x"05", + 5396 => x"34", + 5397 => x"42", + 5398 => x"3d", + 5399 => x"53", + 5400 => x"51", + 5401 => x"3f", + 5402 => x"08", + 5403 => x"fc", + 5404 => x"fe", + 5405 => x"fe", + 5406 => x"fe", + 5407 => x"91", + 5408 => x"80", + 5409 => x"38", + 5410 => x"ec", + 5411 => x"f8", + 5412 => x"fe", + 5413 => x"ca", + 5414 => x"2e", + 5415 => x"91", + 5416 => x"fe", + 5417 => x"63", + 5418 => x"27", + 5419 => x"70", + 5420 => x"41", + 5421 => x"7f", + 5422 => x"78", + 5423 => x"79", + 5424 => x"52", + 5425 => x"51", + 5426 => x"3f", + 5427 => x"81", + 5428 => x"d5", + 5429 => x"f4", + 5430 => x"39", + 5431 => x"f4", + 5432 => x"f8", + 5433 => x"fe", + 5434 => x"ca", + 5435 => x"c4", + 5436 => x"91", + 5437 => x"80", + 5438 => x"91", + 5439 => x"44", + 5440 => x"c7", + 5441 => x"78", + 5442 => x"38", + 5443 => x"08", + 5444 => x"91", + 5445 => x"59", + 5446 => x"91", + 5447 => x"59", + 5448 => x"88", + 5449 => x"f4", + 5450 => x"39", + 5451 => x"08", + 5452 => x"44", + 5453 => x"f0", + 5454 => x"f8", + 5455 => x"fd", + 5456 => x"ca", + 5457 => x"c3", + 5458 => x"91", + 5459 => x"80", + 5460 => x"91", + 5461 => x"43", + 5462 => x"c7", + 5463 => x"78", + 5464 => x"38", + 5465 => x"08", + 5466 => x"91", + 5467 => x"59", + 5468 => x"91", + 5469 => x"59", + 5470 => x"88", + 5471 => x"f8", + 5472 => x"39", + 5473 => x"08", + 5474 => x"b7", + 5475 => x"11", + 5476 => x"05", + 5477 => x"dd", + 5478 => x"88", + 5479 => x"9b", + 5480 => x"5b", + 5481 => x"2e", + 5482 => x"59", + 5483 => x"8d", + 5484 => x"2e", + 5485 => x"a0", + 5486 => x"88", + 5487 => x"f0", + 5488 => x"d8", + 5489 => x"63", + 5490 => x"62", + 5491 => x"ed", + 5492 => x"c4", + 5493 => x"bd", + 5494 => x"fe", + 5495 => x"fe", + 5496 => x"fe", + 5497 => x"91", + 5498 => x"80", + 5499 => x"38", + 5500 => x"f0", + 5501 => x"f8", + 5502 => x"fb", + 5503 => x"ca", + 5504 => x"2e", + 5505 => x"59", + 5506 => x"05", + 5507 => x"63", + 5508 => x"b7", + 5509 => x"11", + 5510 => x"05", + 5511 => x"d5", + 5512 => x"88", + 5513 => x"f5", + 5514 => x"70", + 5515 => x"91", + 5516 => x"fe", + 5517 => x"80", + 5518 => x"51", + 5519 => x"3f", + 5520 => x"33", + 5521 => x"2e", + 5522 => x"9f", + 5523 => x"38", + 5524 => x"f0", + 5525 => x"f8", + 5526 => x"fb", + 5527 => x"ca", + 5528 => x"2e", + 5529 => x"59", + 5530 => x"05", + 5531 => x"63", + 5532 => x"ff", + 5533 => x"c4", + 5534 => x"f3", + 5535 => x"aa", + 5536 => x"fe", + 5537 => x"fe", + 5538 => x"fe", + 5539 => x"91", + 5540 => x"80", + 5541 => x"38", + 5542 => x"e4", + 5543 => x"f8", + 5544 => x"fc", + 5545 => x"ca", + 5546 => x"2e", + 5547 => x"59", + 5548 => x"22", + 5549 => x"05", + 5550 => x"41", + 5551 => x"e4", + 5552 => x"f8", + 5553 => x"fc", + 5554 => x"ca", + 5555 => x"38", + 5556 => x"60", + 5557 => x"52", + 5558 => x"51", + 5559 => x"3f", + 5560 => x"79", + 5561 => x"f2", + 5562 => x"79", + 5563 => x"ae", + 5564 => x"38", + 5565 => x"87", + 5566 => x"05", + 5567 => x"b7", + 5568 => x"11", + 5569 => x"05", + 5570 => x"db", + 5571 => x"88", + 5572 => x"92", + 5573 => x"02", + 5574 => x"79", + 5575 => x"5b", + 5576 => x"ff", + 5577 => x"c4", + 5578 => x"f1", + 5579 => x"a3", + 5580 => x"fe", + 5581 => x"fe", + 5582 => x"fe", + 5583 => x"91", + 5584 => x"80", + 5585 => x"38", + 5586 => x"e4", + 5587 => x"f8", + 5588 => x"fb", + 5589 => x"ca", + 5590 => x"2e", + 5591 => x"60", + 5592 => x"60", + 5593 => x"b7", + 5594 => x"11", + 5595 => x"05", + 5596 => x"f3", + 5597 => x"88", + 5598 => x"f2", + 5599 => x"70", + 5600 => x"91", + 5601 => x"fe", + 5602 => x"80", + 5603 => x"51", + 5604 => x"3f", + 5605 => x"33", + 5606 => x"2e", + 5607 => x"9f", + 5608 => x"38", + 5609 => x"e4", + 5610 => x"f8", + 5611 => x"fa", + 5612 => x"ca", + 5613 => x"2e", + 5614 => x"53", + 5615 => x"c4", + 5616 => x"f6", + 5617 => x"60", + 5618 => x"60", + 5619 => x"ff", + 5620 => x"c4", + 5621 => x"f0", + 5622 => x"a2", + 5623 => x"b8", + 5624 => x"b8", + 5625 => x"fe", + 5626 => x"f1", + 5627 => x"c4", + 5628 => x"f0", + 5629 => x"51", + 5630 => x"3f", + 5631 => x"84", + 5632 => x"87", + 5633 => x"0c", + 5634 => x"0b", + 5635 => x"94", + 5636 => x"e8", + 5637 => x"84", + 5638 => x"39", + 5639 => x"51", + 5640 => x"3f", + 5641 => x"0b", + 5642 => x"84", + 5643 => x"83", + 5644 => x"94", + 5645 => x"b4", + 5646 => x"fe", + 5647 => x"fe", + 5648 => x"fe", + 5649 => x"91", + 5650 => x"80", + 5651 => x"38", + 5652 => x"c5", + 5653 => x"f5", + 5654 => x"59", + 5655 => x"3d", + 5656 => x"53", + 5657 => x"51", + 5658 => x"3f", + 5659 => x"08", + 5660 => x"f8", + 5661 => x"91", + 5662 => x"fe", + 5663 => x"63", + 5664 => x"91", + 5665 => x"5e", + 5666 => x"08", + 5667 => x"dc", + 5668 => x"88", + 5669 => x"c5", + 5670 => x"f4", + 5671 => x"cc", + 5672 => x"e4", + 5673 => x"f4", + 5674 => x"d4", + 5675 => x"39", + 5676 => x"51", + 5677 => x"3f", + 5678 => x"a0", + 5679 => x"b0", + 5680 => x"39", + 5681 => x"51", + 5682 => x"2e", + 5683 => x"7b", + 5684 => x"d2", + 5685 => x"2e", + 5686 => x"b7", + 5687 => x"05", + 5688 => x"ce", + 5689 => x"94", + 5690 => x"88", + 5691 => x"c6", + 5692 => x"53", + 5693 => x"52", + 5694 => x"52", + 5695 => x"96", + 5696 => x"e4", + 5697 => x"bc", + 5698 => x"64", + 5699 => x"81", + 5700 => x"54", + 5701 => x"53", + 5702 => x"52", + 5703 => x"bb", + 5704 => x"88", + 5705 => x"81", + 5706 => x"32", + 5707 => x"8a", + 5708 => x"2e", + 5709 => x"ef", + 5710 => x"c6", + 5711 => x"f3", + 5712 => x"a8", + 5713 => x"0d", + 5714 => x"ca", + 5715 => x"94", + 5716 => x"ca", + 5717 => x"97", + 5718 => x"ca", + 5719 => x"e5", + 5720 => x"ec", + 5721 => x"c6", + 5722 => x"e3", + 5723 => x"c6", + 5724 => x"ed", + 5725 => x"9d", + 5726 => x"eb", + 5727 => x"51", + 5728 => x"ee", + 5729 => x"04", + 5730 => x"3e", + 5731 => x"44", + 5732 => x"4a", + 5733 => x"50", + 5734 => x"56", + 5735 => x"14", + 5736 => x"98", + 5737 => x"9f", + 5738 => x"a6", + 5739 => x"ad", + 5740 => x"b4", + 5741 => x"bb", + 5742 => x"c2", + 5743 => x"c9", + 5744 => x"d0", + 5745 => x"d7", + 5746 => x"de", + 5747 => x"e4", + 5748 => x"ea", + 5749 => x"f0", + 5750 => x"f6", + 5751 => x"fc", + 5752 => x"02", + 5753 => x"08", + 5754 => x"0e", + 5755 => x"25", + 5756 => x"64", + 5757 => x"3a", + 5758 => x"25", + 5759 => x"64", + 5760 => x"00", + 5761 => x"20", + 5762 => x"66", + 5763 => x"72", + 5764 => x"6f", + 5765 => x"00", + 5766 => x"72", + 5767 => x"53", + 5768 => x"63", + 5769 => x"69", + 5770 => x"00", + 5771 => x"65", + 5772 => x"65", + 5773 => x"6d", + 5774 => x"6d", + 5775 => x"65", + 5776 => x"00", + 5777 => x"20", + 5778 => x"4e", + 5779 => x"41", + 5780 => x"53", + 5781 => x"74", + 5782 => x"38", + 5783 => x"53", + 5784 => x"3d", + 5785 => x"58", + 5786 => x"00", + 5787 => x"20", + 5788 => x"4d", + 5789 => x"74", + 5790 => x"3d", + 5791 => x"58", + 5792 => x"69", + 5793 => x"25", + 5794 => x"29", + 5795 => x"00", + 5796 => x"20", + 5797 => x"20", + 5798 => x"61", + 5799 => x"25", + 5800 => x"2c", + 5801 => x"7a", + 5802 => x"30", + 5803 => x"2e", + 5804 => x"00", + 5805 => x"20", + 5806 => x"54", + 5807 => x"00", + 5808 => x"20", + 5809 => x"0a", + 5810 => x"00", + 5811 => x"20", + 5812 => x"0a", + 5813 => x"00", + 5814 => x"20", + 5815 => x"43", + 5816 => x"20", + 5817 => x"76", + 5818 => x"73", + 5819 => x"32", + 5820 => x"0a", + 5821 => x"00", + 5822 => x"20", + 5823 => x"45", + 5824 => x"50", + 5825 => x"4f", + 5826 => x"4f", + 5827 => x"52", + 5828 => x"00", + 5829 => x"20", + 5830 => x"45", + 5831 => x"28", + 5832 => x"65", + 5833 => x"25", + 5834 => x"29", + 5835 => x"00", + 5836 => x"72", + 5837 => x"65", + 5838 => x"00", + 5839 => x"20", + 5840 => x"20", + 5841 => x"65", + 5842 => x"65", + 5843 => x"72", + 5844 => x"64", + 5845 => x"73", + 5846 => x"25", + 5847 => x"0a", + 5848 => x"00", + 5849 => x"20", + 5850 => x"20", + 5851 => x"6f", + 5852 => x"53", + 5853 => x"74", + 5854 => x"64", + 5855 => x"73", + 5856 => x"25", + 5857 => x"0a", + 5858 => x"00", + 5859 => x"20", + 5860 => x"63", + 5861 => x"74", + 5862 => x"20", + 5863 => x"72", + 5864 => x"20", + 5865 => x"20", + 5866 => x"25", + 5867 => x"0a", + 5868 => x"00", + 5869 => x"20", + 5870 => x"20", + 5871 => x"20", + 5872 => x"20", + 5873 => x"20", + 5874 => x"20", + 5875 => x"20", + 5876 => x"25", + 5877 => x"0a", + 5878 => x"00", + 5879 => x"20", + 5880 => x"74", + 5881 => x"43", + 5882 => x"6b", + 5883 => x"65", + 5884 => x"20", + 5885 => x"20", + 5886 => x"25", + 5887 => x"0a", + 5888 => x"00", + 5889 => x"6c", + 5890 => x"00", + 5891 => x"69", + 5892 => x"00", + 5893 => x"78", + 5894 => x"00", + 5895 => x"00", + 5896 => x"6d", + 5897 => x"00", + 5898 => x"6e", + 5899 => x"00", + 5900 => x"00", + 5901 => x"2c", + 5902 => x"3d", + 5903 => x"5d", + 5904 => x"00", + 5905 => x"00", + 5906 => x"33", + 5907 => x"00", + 5908 => x"4d", + 5909 => x"53", + 5910 => x"00", + 5911 => x"4e", + 5912 => x"20", + 5913 => x"46", + 5914 => x"32", + 5915 => x"00", + 5916 => x"4e", + 5917 => x"20", + 5918 => x"46", + 5919 => x"20", + 5920 => x"00", + 5921 => x"30", + 5922 => x"00", + 5923 => x"00", + 5924 => x"00", + 5925 => x"41", + 5926 => x"80", + 5927 => x"49", + 5928 => x"8f", + 5929 => x"4f", + 5930 => x"55", + 5931 => x"9b", + 5932 => x"9f", + 5933 => x"55", + 5934 => x"a7", + 5935 => x"ab", + 5936 => x"af", + 5937 => x"b3", + 5938 => x"b7", + 5939 => x"bb", + 5940 => x"bf", + 5941 => x"c3", + 5942 => x"c7", + 5943 => x"cb", + 5944 => x"cf", + 5945 => x"d3", + 5946 => x"d7", + 5947 => x"db", + 5948 => x"df", + 5949 => x"e3", + 5950 => x"e7", + 5951 => x"eb", + 5952 => x"ef", + 5953 => x"f3", + 5954 => x"f7", + 5955 => x"fb", + 5956 => x"ff", + 5957 => x"3b", + 5958 => x"2f", + 5959 => x"3a", + 5960 => x"7c", + 5961 => x"00", + 5962 => x"04", + 5963 => x"40", + 5964 => x"00", + 5965 => x"00", + 5966 => x"02", + 5967 => x"08", + 5968 => x"20", + 5969 => x"00", + 5970 => x"69", + 5971 => x"00", + 5972 => x"63", + 5973 => x"00", + 5974 => x"69", + 5975 => x"00", + 5976 => x"61", + 5977 => x"00", + 5978 => x"65", + 5979 => x"00", + 5980 => x"65", + 5981 => x"00", + 5982 => x"70", + 5983 => x"00", + 5984 => x"66", + 5985 => x"00", + 5986 => x"6d", + 5987 => x"00", + 5988 => x"00", + 5989 => x"00", + 5990 => x"00", + 5991 => x"00", + 5992 => x"00", + 5993 => x"00", + 5994 => x"00", + 5995 => x"6c", + 5996 => x"00", + 5997 => x"00", + 5998 => x"74", + 5999 => x"00", + 6000 => x"65", + 6001 => x"00", + 6002 => x"6f", + 6003 => x"00", + 6004 => x"74", + 6005 => x"00", + 6006 => x"6b", + 6007 => x"72", + 6008 => x"00", + 6009 => x"65", + 6010 => x"6c", + 6011 => x"72", + 6012 => x"0a", + 6013 => x"00", + 6014 => x"6b", + 6015 => x"74", + 6016 => x"61", + 6017 => x"0a", + 6018 => x"00", + 6019 => x"66", + 6020 => x"20", + 6021 => x"6e", + 6022 => x"00", + 6023 => x"70", + 6024 => x"20", + 6025 => x"6e", + 6026 => x"00", + 6027 => x"61", + 6028 => x"20", + 6029 => x"65", + 6030 => x"65", + 6031 => x"00", + 6032 => x"65", + 6033 => x"64", + 6034 => x"65", + 6035 => x"00", + 6036 => x"65", + 6037 => x"72", + 6038 => x"79", + 6039 => x"69", + 6040 => x"2e", + 6041 => x"00", + 6042 => x"65", + 6043 => x"6e", + 6044 => x"20", + 6045 => x"61", + 6046 => x"2e", + 6047 => x"00", + 6048 => x"69", + 6049 => x"72", + 6050 => x"20", + 6051 => x"74", + 6052 => x"65", + 6053 => x"00", + 6054 => x"76", + 6055 => x"75", + 6056 => x"72", + 6057 => x"20", + 6058 => x"61", + 6059 => x"2e", + 6060 => x"00", + 6061 => x"6b", + 6062 => x"74", + 6063 => x"61", + 6064 => x"64", + 6065 => x"00", + 6066 => x"63", + 6067 => x"61", + 6068 => x"6c", + 6069 => x"69", + 6070 => x"79", + 6071 => x"6d", + 6072 => x"75", + 6073 => x"6f", + 6074 => x"69", + 6075 => x"0a", + 6076 => x"00", + 6077 => x"6d", + 6078 => x"61", + 6079 => x"74", + 6080 => x"0a", + 6081 => x"00", + 6082 => x"65", + 6083 => x"2c", + 6084 => x"65", + 6085 => x"69", + 6086 => x"63", + 6087 => x"65", + 6088 => x"64", + 6089 => x"00", + 6090 => x"65", + 6091 => x"20", + 6092 => x"6b", + 6093 => x"0a", + 6094 => x"00", + 6095 => x"75", + 6096 => x"63", + 6097 => x"74", + 6098 => x"6d", + 6099 => x"2e", + 6100 => x"00", + 6101 => x"20", + 6102 => x"79", + 6103 => x"65", + 6104 => x"69", + 6105 => x"2e", + 6106 => x"00", + 6107 => x"61", + 6108 => x"65", + 6109 => x"69", + 6110 => x"72", + 6111 => x"74", + 6112 => x"00", + 6113 => x"63", + 6114 => x"2e", + 6115 => x"00", + 6116 => x"6e", + 6117 => x"20", + 6118 => x"6f", + 6119 => x"00", + 6120 => x"75", + 6121 => x"74", + 6122 => x"25", + 6123 => x"74", + 6124 => x"75", + 6125 => x"74", + 6126 => x"73", + 6127 => x"0a", + 6128 => x"00", + 6129 => x"58", + 6130 => x"00", + 6131 => x"00", + 6132 => x"58", + 6133 => x"00", + 6134 => x"20", + 6135 => x"20", + 6136 => x"00", + 6137 => x"58", + 6138 => x"00", + 6139 => x"00", + 6140 => x"00", + 6141 => x"00", + 6142 => x"64", + 6143 => x"00", + 6144 => x"54", + 6145 => x"00", + 6146 => x"20", + 6147 => x"28", + 6148 => x"00", + 6149 => x"30", + 6150 => x"30", + 6151 => x"00", + 6152 => x"33", + 6153 => x"00", + 6154 => x"55", + 6155 => x"65", + 6156 => x"30", + 6157 => x"20", + 6158 => x"25", + 6159 => x"2a", + 6160 => x"00", + 6161 => x"54", + 6162 => x"6e", + 6163 => x"72", + 6164 => x"20", + 6165 => x"64", + 6166 => x"0a", + 6167 => x"00", + 6168 => x"65", + 6169 => x"6e", + 6170 => x"72", + 6171 => x"0a", + 6172 => x"00", + 6173 => x"20", + 6174 => x"65", + 6175 => x"70", + 6176 => x"00", + 6177 => x"54", + 6178 => x"44", + 6179 => x"74", + 6180 => x"75", + 6181 => x"00", + 6182 => x"54", + 6183 => x"52", + 6184 => x"74", + 6185 => x"75", + 6186 => x"00", + 6187 => x"54", + 6188 => x"58", + 6189 => x"74", + 6190 => x"75", + 6191 => x"00", + 6192 => x"54", + 6193 => x"58", + 6194 => x"74", + 6195 => x"75", + 6196 => x"00", + 6197 => x"54", + 6198 => x"58", + 6199 => x"74", + 6200 => x"75", + 6201 => x"00", + 6202 => x"54", + 6203 => x"58", + 6204 => x"74", + 6205 => x"75", + 6206 => x"00", + 6207 => x"74", + 6208 => x"20", + 6209 => x"74", + 6210 => x"72", + 6211 => x"0a", + 6212 => x"00", + 6213 => x"62", + 6214 => x"67", + 6215 => x"6d", + 6216 => x"2e", + 6217 => x"00", + 6218 => x"00", + 6219 => x"6c", + 6220 => x"74", + 6221 => x"6e", + 6222 => x"61", + 6223 => x"65", + 6224 => x"20", + 6225 => x"64", + 6226 => x"20", + 6227 => x"61", + 6228 => x"69", + 6229 => x"20", + 6230 => x"75", + 6231 => x"79", + 6232 => x"00", + 6233 => x"00", + 6234 => x"20", + 6235 => x"6b", + 6236 => x"21", + 6237 => x"00", + 6238 => x"74", + 6239 => x"69", + 6240 => x"2e", + 6241 => x"00", + 6242 => x"6c", + 6243 => x"74", + 6244 => x"6e", + 6245 => x"61", + 6246 => x"65", + 6247 => x"00", + 6248 => x"25", + 6249 => x"00", + 6250 => x"00", + 6251 => x"61", + 6252 => x"67", + 6253 => x"00", + 6254 => x"79", + 6255 => x"2e", + 6256 => x"00", + 6257 => x"70", + 6258 => x"6e", + 6259 => x"2e", + 6260 => x"00", + 6261 => x"6c", + 6262 => x"30", + 6263 => x"2d", + 6264 => x"38", + 6265 => x"25", + 6266 => x"29", + 6267 => x"00", + 6268 => x"70", + 6269 => x"6d", + 6270 => x"0a", + 6271 => x"00", + 6272 => x"6d", + 6273 => x"74", + 6274 => x"00", + 6275 => x"58", + 6276 => x"32", + 6277 => x"00", + 6278 => x"0a", + 6279 => x"00", + 6280 => x"58", + 6281 => x"34", + 6282 => x"00", + 6283 => x"58", + 6284 => x"38", + 6285 => x"00", + 6286 => x"61", + 6287 => x"6e", + 6288 => x"6e", + 6289 => x"72", + 6290 => x"73", + 6291 => x"00", + 6292 => x"62", + 6293 => x"67", + 6294 => x"74", + 6295 => x"75", + 6296 => x"0a", + 6297 => x"00", + 6298 => x"61", + 6299 => x"64", + 6300 => x"72", + 6301 => x"69", + 6302 => x"00", + 6303 => x"62", + 6304 => x"67", + 6305 => x"72", + 6306 => x"69", + 6307 => x"00", + 6308 => x"63", + 6309 => x"6e", + 6310 => x"6f", + 6311 => x"40", + 6312 => x"38", + 6313 => x"2e", + 6314 => x"00", + 6315 => x"6c", + 6316 => x"20", + 6317 => x"65", + 6318 => x"25", + 6319 => x"20", + 6320 => x"0a", + 6321 => x"00", + 6322 => x"6c", + 6323 => x"74", + 6324 => x"65", + 6325 => x"6f", + 6326 => x"28", + 6327 => x"2e", + 6328 => x"00", + 6329 => x"74", + 6330 => x"69", + 6331 => x"61", + 6332 => x"69", + 6333 => x"69", + 6334 => x"2e", + 6335 => x"00", + 6336 => x"64", + 6337 => x"62", + 6338 => x"69", + 6339 => x"2e", + 6340 => x"00", + 6341 => x"00", + 6342 => x"00", + 6343 => x"5c", + 6344 => x"25", + 6345 => x"73", + 6346 => x"00", + 6347 => x"20", + 6348 => x"6d", + 6349 => x"2e", + 6350 => x"00", + 6351 => x"6e", + 6352 => x"2e", + 6353 => x"00", + 6354 => x"62", + 6355 => x"67", + 6356 => x"74", + 6357 => x"75", + 6358 => x"2e", + 6359 => x"00", + 6360 => x"00", + 6361 => x"00", + 6362 => x"ff", + 6363 => x"00", + 6364 => x"ff", + 6365 => x"00", + 6366 => x"ff", + 6367 => x"00", + 6368 => x"00", + 6369 => x"00", + 6370 => x"00", + 6371 => x"00", + 6372 => x"01", + 6373 => x"01", + 6374 => x"01", + 6375 => x"00", + 6376 => x"00", + 6377 => x"00", + 6378 => x"48", + 6379 => x"00", + 6380 => x"00", + 6381 => x"00", + 6382 => x"50", + 6383 => x"00", + 6384 => x"00", + 6385 => x"00", + 6386 => x"58", + 6387 => x"00", + 6388 => x"00", + 6389 => x"00", + 6390 => x"60", + 6391 => x"00", + 6392 => x"00", + 6393 => x"00", + 6394 => x"68", + 6395 => x"00", + 6396 => x"00", + 6397 => x"00", + 6398 => x"70", + 6399 => x"00", + 6400 => x"00", + 6401 => x"00", + 6402 => x"78", + 6403 => x"00", + 6404 => x"00", + 6405 => x"00", + 6406 => x"80", + 6407 => x"00", + 6408 => x"00", + 6409 => x"00", + 6410 => x"88", + 6411 => x"00", + 6412 => x"00", + 6413 => x"00", + 6414 => x"90", + 6415 => x"00", + 6416 => x"00", + 6417 => x"00", + 6418 => x"94", + 6419 => x"00", + 6420 => x"00", + 6421 => x"00", + 6422 => x"98", + 6423 => x"00", + 6424 => x"00", + 6425 => x"00", + 6426 => x"9c", + 6427 => x"00", + 6428 => x"00", + 6429 => x"00", + 6430 => x"a0", + 6431 => x"00", + 6432 => x"00", + 6433 => x"00", + 6434 => x"a4", + 6435 => x"00", + 6436 => x"00", + 6437 => x"00", + 6438 => x"a8", + 6439 => x"00", + 6440 => x"00", + 6441 => x"00", + 6442 => x"ac", + 6443 => x"00", + 6444 => x"00", + 6445 => x"00", + 6446 => x"b4", + 6447 => x"00", + 6448 => x"00", + 6449 => x"00", + 6450 => x"b8", + 6451 => x"00", + 6452 => x"00", + 6453 => x"00", + 6454 => x"c0", + 6455 => x"00", + 6456 => x"00", + 6457 => x"00", + 6458 => x"c8", + 6459 => x"00", + 6460 => x"00", + 6461 => x"00", + 6462 => x"d0", + 6463 => x"00", + 6464 => x"00", + 6465 => x"00", + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + 0 => x"90", + 1 => x"0b", + 2 => x"c6", + 3 => x"ff", + 4 => x"ff", + 5 => x"ff", + 6 => x"ff", + 7 => x"ff", + 8 => x"90", + 9 => x"0b", + 10 => x"85", + 11 => x"90", + 12 => x"0b", + 13 => x"a7", + 14 => x"90", + 15 => x"0b", + 16 => x"c9", + 17 => x"90", + 18 => x"0b", + 19 => x"eb", + 20 => x"90", + 21 => x"0b", + 22 => x"8d", + 23 => x"90", + 24 => x"0b", + 25 => x"af", + 26 => x"90", + 27 => x"0b", + 28 => x"d1", + 29 => x"90", + 30 => x"0b", + 31 => x"f3", + 32 => x"90", + 33 => x"0b", + 34 => x"95", + 35 => x"90", + 36 => x"0b", + 37 => x"b7", + 38 => x"90", + 39 => x"0b", + 40 => x"d9", + 41 => x"90", + 42 => x"0b", + 43 => x"fb", + 44 => x"90", + 45 => x"0b", + 46 => x"9d", + 47 => x"90", + 48 => x"0b", + 49 => x"bf", + 50 => x"90", + 51 => x"0b", + 52 => x"e1", + 53 => x"90", + 54 => x"0b", + 55 => x"83", + 56 => x"90", + 57 => x"0b", + 58 => x"a5", + 59 => x"90", + 60 => x"0b", + 61 => x"c7", + 62 => x"90", + 63 => x"0b", + 64 => x"e9", + 65 => x"90", + 66 => x"0b", + 67 => x"8b", + 68 => x"90", + 69 => x"0b", + 70 => x"ad", + 71 => x"90", + 72 => x"0b", + 73 => x"cf", + 74 => x"90", + 75 => x"0b", + 76 => x"f1", + 77 => x"90", + 78 => x"0b", + 79 => x"93", + 80 => x"90", + 81 => x"0b", + 82 => x"b5", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"00", + 89 => x"00", + 90 => x"00", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"00", + 97 => x"00", + 98 => x"00", + 99 => x"00", + 100 => x"00", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"00", + 105 => x"00", + 106 => x"00", + 107 => x"00", + 108 => x"00", + 109 => x"00", + 110 => x"00", + 111 => x"00", + 112 => x"00", + 113 => x"00", + 114 => x"00", + 115 => x"00", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"00", + 121 => x"00", + 122 => x"00", + 123 => x"00", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"84", + 129 => x"ca", + 130 => x"95", + 131 => x"ca", + 132 => x"c0", + 133 => x"91", + 134 => x"90", + 135 => x"91", + 136 => x"88", + 137 => x"04", + 138 => x"0c", + 139 => x"2d", + 140 => x"08", + 141 => x"90", + 142 => x"94", + 143 => x"9c", + 144 => x"94", + 145 => x"80", + 146 => x"ca", + 147 => x"a6", + 148 => x"ca", + 149 => x"c0", + 150 => x"91", + 151 => x"90", + 152 => x"91", + 153 => x"88", + 154 => x"04", + 155 => x"0c", + 156 => x"2d", + 157 => x"08", + 158 => x"90", + 159 => x"94", + 160 => x"f5", + 161 => x"94", + 162 => x"80", + 163 => x"ca", + 164 => x"a9", + 165 => x"ca", + 166 => x"c0", + 167 => x"91", + 168 => x"90", + 169 => x"91", + 170 => x"88", + 171 => x"04", + 172 => x"0c", + 173 => x"2d", + 174 => x"08", + 175 => x"90", + 176 => x"94", + 177 => x"ba", + 178 => x"94", + 179 => x"80", + 180 => x"ca", + 181 => x"97", + 182 => x"ca", + 183 => x"c0", + 184 => x"91", + 185 => x"90", + 186 => x"91", + 187 => x"88", + 188 => x"04", + 189 => x"0c", + 190 => x"2d", + 191 => x"08", + 192 => x"90", + 193 => x"94", + 194 => x"be", + 195 => x"94", + 196 => x"80", + 197 => x"ca", + 198 => x"92", + 199 => x"ca", + 200 => x"c0", + 201 => x"91", + 202 => x"90", + 203 => x"91", + 204 => x"88", + 205 => x"04", + 206 => x"0c", + 207 => x"2d", + 208 => x"08", + 209 => x"90", + 210 => x"94", + 211 => x"81", + 212 => x"94", + 213 => x"80", + 214 => x"ca", + 215 => x"e3", + 216 => x"ca", + 217 => x"c0", + 218 => x"91", + 219 => x"90", + 220 => x"91", + 221 => x"88", + 222 => x"04", + 223 => x"0c", + 224 => x"2d", + 225 => x"08", + 226 => x"90", + 227 => x"94", + 228 => x"ef", + 229 => x"94", + 230 => x"80", + 231 => x"ca", + 232 => x"f1", + 233 => x"ca", + 234 => x"c0", + 235 => x"91", + 236 => x"90", + 237 => x"91", + 238 => x"88", + 239 => x"04", + 240 => x"0c", + 241 => x"2d", + 242 => x"08", + 243 => x"90", + 244 => x"94", + 245 => x"e3", + 246 => x"94", + 247 => x"80", + 248 => x"ca", + 249 => x"f8", + 250 => x"ca", + 251 => x"c0", + 252 => x"91", + 253 => x"90", + 254 => x"91", + 255 => x"88", + 256 => x"04", + 257 => x"0c", + 258 => x"2d", + 259 => x"08", + 260 => x"90", + 261 => x"94", + 262 => x"b7", + 263 => x"94", + 264 => x"80", + 265 => x"ca", + 266 => x"81", + 267 => x"ca", + 268 => x"c0", + 269 => x"91", + 270 => x"90", + 271 => x"91", + 272 => x"88", + 273 => x"04", + 274 => x"0c", + 275 => x"2d", + 276 => x"08", + 277 => x"90", + 278 => x"94", + 279 => x"f1", + 280 => x"94", + 281 => x"80", + 282 => x"ca", + 283 => x"f4", + 284 => x"ca", + 285 => x"c0", + 286 => x"91", + 287 => x"91", + 288 => x"91", + 289 => x"88", + 290 => x"04", + 291 => x"0c", + 292 => x"2d", + 293 => x"08", + 294 => x"90", + 295 => x"94", + 296 => x"f5", + 297 => x"94", + 298 => x"80", + 299 => x"ca", + 300 => x"db", + 301 => x"ca", + 302 => x"c0", + 303 => x"91", + 304 => x"91", + 305 => x"91", + 306 => x"88", + 307 => x"04", + 308 => x"0c", + 309 => x"2d", + 310 => x"08", + 311 => x"90", + 312 => x"94", + 313 => x"e0", + 314 => x"94", + 315 => x"80", + 316 => x"ca", + 317 => x"b0", + 318 => x"ca", + 319 => x"c0", + 320 => x"91", + 321 => x"90", + 322 => x"91", + 323 => x"88", + 324 => x"04", + 325 => x"0c", + 326 => x"2d", + 327 => x"08", + 328 => x"90", + 329 => x"94", + 330 => x"81", + 331 => x"94", + 332 => x"80", + 333 => x"ca", + 334 => x"97", + 335 => x"ca", + 336 => x"c0", + 337 => x"91", + 338 => x"91", + 339 => x"8e", + 340 => x"70", + 341 => x"0c", + 342 => x"8a", + 343 => x"84", + 344 => x"b2", + 345 => x"04", + 346 => x"08", + 347 => x"94", + 348 => x"0d", + 349 => x"ca", + 350 => x"05", + 351 => x"ca", + 352 => x"05", + 353 => x"c5", + 354 => x"88", + 355 => x"ca", + 356 => x"85", + 357 => x"ca", + 358 => x"91", + 359 => x"02", + 360 => x"0c", + 361 => x"81", + 362 => x"94", + 363 => x"08", + 364 => x"94", + 365 => x"08", + 366 => x"91", + 367 => x"70", + 368 => x"0c", + 369 => x"0d", + 370 => x"0c", + 371 => x"94", + 372 => x"ca", + 373 => x"3d", + 374 => x"91", + 375 => x"fc", + 376 => x"0b", + 377 => x"08", + 378 => x"91", + 379 => x"8c", + 380 => x"ca", + 381 => x"05", + 382 => x"38", + 383 => x"08", + 384 => x"80", + 385 => x"80", + 386 => x"94", + 387 => x"08", + 388 => x"91", + 389 => x"8c", + 390 => x"91", + 391 => x"8c", + 392 => x"ca", + 393 => x"05", + 394 => x"ca", + 395 => x"05", + 396 => x"39", + 397 => x"08", + 398 => x"80", + 399 => x"38", + 400 => x"08", + 401 => x"91", + 402 => x"88", + 403 => x"ad", + 404 => x"94", + 405 => x"08", + 406 => x"08", + 407 => x"31", + 408 => x"08", + 409 => x"91", + 410 => x"f8", + 411 => x"ca", + 412 => x"05", + 413 => x"ca", + 414 => x"05", + 415 => x"94", + 416 => x"08", + 417 => x"ca", + 418 => x"05", + 419 => x"94", + 420 => x"08", + 421 => x"ca", + 422 => x"05", + 423 => x"39", + 424 => x"08", + 425 => x"80", + 426 => x"91", + 427 => x"88", + 428 => x"91", + 429 => x"f4", + 430 => x"91", + 431 => x"94", + 432 => x"08", + 433 => x"94", + 434 => x"0c", + 435 => x"94", + 436 => x"08", + 437 => x"0c", + 438 => x"91", + 439 => x"04", + 440 => x"76", + 441 => x"8c", + 442 => x"33", + 443 => x"55", + 444 => x"8a", + 445 => x"06", + 446 => x"2e", + 447 => x"12", + 448 => x"2e", + 449 => x"73", + 450 => x"55", + 451 => x"52", + 452 => x"09", + 453 => x"38", + 454 => x"88", + 455 => x"0d", + 456 => x"88", + 457 => x"70", + 458 => x"07", + 459 => x"8f", + 460 => x"38", + 461 => x"84", + 462 => x"72", + 463 => x"05", + 464 => x"71", + 465 => x"53", + 466 => x"70", + 467 => x"0c", + 468 => x"71", + 469 => x"38", + 470 => x"90", + 471 => x"70", + 472 => x"0c", + 473 => x"71", + 474 => x"38", + 475 => x"8e", + 476 => x"0d", + 477 => x"72", + 478 => x"53", + 479 => x"93", + 480 => x"73", + 481 => x"54", + 482 => x"2e", + 483 => x"73", + 484 => x"71", + 485 => x"ff", + 486 => x"70", + 487 => x"38", + 488 => x"70", + 489 => x"81", + 490 => x"81", + 491 => x"71", + 492 => x"ff", + 493 => x"54", + 494 => x"38", + 495 => x"73", + 496 => x"75", + 497 => x"71", + 498 => x"ca", + 499 => x"52", + 500 => x"04", + 501 => x"f7", + 502 => x"14", + 503 => x"84", + 504 => x"06", + 505 => x"70", + 506 => x"14", + 507 => x"08", + 508 => x"71", + 509 => x"dc", + 510 => x"54", + 511 => x"39", + 512 => x"ca", + 513 => x"3d", + 514 => x"3d", + 515 => x"83", + 516 => x"2b", + 517 => x"3f", + 518 => x"08", + 519 => x"72", + 520 => x"54", + 521 => x"25", + 522 => x"91", + 523 => x"84", + 524 => x"fb", + 525 => x"70", + 526 => x"53", + 527 => x"2e", + 528 => x"71", + 529 => x"a0", + 530 => x"06", + 531 => x"12", + 532 => x"71", + 533 => x"81", + 534 => x"73", + 535 => x"ff", + 536 => x"55", + 537 => x"83", + 538 => x"70", + 539 => x"38", + 540 => x"73", + 541 => x"51", + 542 => x"09", + 543 => x"38", + 544 => x"81", + 545 => x"72", + 546 => x"51", + 547 => x"88", + 548 => x"0d", + 549 => x"0d", + 550 => x"08", + 551 => x"38", + 552 => x"05", + 553 => x"98", + 554 => x"ca", + 555 => x"38", + 556 => x"39", + 557 => x"91", + 558 => x"86", + 559 => x"fc", + 560 => x"82", + 561 => x"05", + 562 => x"52", + 563 => x"81", + 564 => x"13", + 565 => x"51", + 566 => x"9e", + 567 => x"38", + 568 => x"51", + 569 => x"97", + 570 => x"38", + 571 => x"51", + 572 => x"bb", + 573 => x"38", + 574 => x"51", + 575 => x"bb", + 576 => x"38", + 577 => x"55", + 578 => x"87", + 579 => x"d9", + 580 => x"22", + 581 => x"73", + 582 => x"80", + 583 => x"0b", + 584 => x"9c", + 585 => x"87", + 586 => x"0c", + 587 => x"87", + 588 => x"0c", + 589 => x"87", + 590 => x"0c", + 591 => x"87", + 592 => x"0c", + 593 => x"87", + 594 => x"0c", + 595 => x"87", + 596 => x"0c", + 597 => x"98", + 598 => x"87", + 599 => x"0c", + 600 => x"c0", + 601 => x"80", + 602 => x"ca", + 603 => x"3d", + 604 => x"3d", + 605 => x"87", + 606 => x"5d", + 607 => x"87", + 608 => x"08", + 609 => x"23", + 610 => x"b8", + 611 => x"82", + 612 => x"c0", + 613 => x"5a", + 614 => x"34", + 615 => x"b0", + 616 => x"84", + 617 => x"c0", + 618 => x"5a", + 619 => x"34", + 620 => x"a8", + 621 => x"86", + 622 => x"c0", + 623 => x"5c", + 624 => x"23", + 625 => x"a0", + 626 => x"8a", + 627 => x"7d", + 628 => x"ff", + 629 => x"7b", + 630 => x"06", + 631 => x"33", + 632 => x"33", + 633 => x"33", + 634 => x"33", + 635 => x"33", + 636 => x"ff", + 637 => x"91", + 638 => x"92", + 639 => x"3d", + 640 => x"3d", + 641 => x"05", + 642 => x"70", + 643 => x"52", + 644 => x"0b", + 645 => x"34", + 646 => x"04", + 647 => x"77", + 648 => x"c6", + 649 => x"81", + 650 => x"55", + 651 => x"94", + 652 => x"80", + 653 => x"87", + 654 => x"51", + 655 => x"96", + 656 => x"06", + 657 => x"70", + 658 => x"38", + 659 => x"70", + 660 => x"51", + 661 => x"72", + 662 => x"81", + 663 => x"70", + 664 => x"38", + 665 => x"70", + 666 => x"51", + 667 => x"38", + 668 => x"06", + 669 => x"94", + 670 => x"80", + 671 => x"87", + 672 => x"52", + 673 => x"75", + 674 => x"0c", + 675 => x"04", + 676 => x"02", + 677 => x"0b", + 678 => x"e0", + 679 => x"ff", + 680 => x"56", + 681 => x"84", + 682 => x"2e", + 683 => x"c0", + 684 => x"70", + 685 => x"2a", + 686 => x"53", + 687 => x"80", + 688 => x"71", + 689 => x"81", + 690 => x"70", + 691 => x"81", + 692 => x"06", + 693 => x"80", + 694 => x"71", + 695 => x"81", + 696 => x"70", + 697 => x"73", + 698 => x"51", + 699 => x"80", + 700 => x"2e", + 701 => x"c0", + 702 => x"75", + 703 => x"3d", + 704 => x"3d", + 705 => x"80", + 706 => x"81", + 707 => x"53", + 708 => x"2e", + 709 => x"71", + 710 => x"81", + 711 => x"91", + 712 => x"70", + 713 => x"59", + 714 => x"87", + 715 => x"51", + 716 => x"86", + 717 => x"94", + 718 => x"08", + 719 => x"70", + 720 => x"54", + 721 => x"2e", + 722 => x"91", + 723 => x"06", + 724 => x"d7", + 725 => x"32", + 726 => x"51", + 727 => x"2e", + 728 => x"93", + 729 => x"06", + 730 => x"ff", + 731 => x"81", + 732 => x"87", + 733 => x"52", + 734 => x"86", + 735 => x"94", + 736 => x"72", + 737 => x"74", + 738 => x"ff", + 739 => x"57", + 740 => x"38", + 741 => x"88", + 742 => x"0d", + 743 => x"0d", + 744 => x"c6", + 745 => x"81", + 746 => x"52", + 747 => x"84", + 748 => x"2e", + 749 => x"c0", + 750 => x"70", + 751 => x"2a", + 752 => x"51", + 753 => x"80", + 754 => x"71", + 755 => x"51", + 756 => x"80", + 757 => x"2e", + 758 => x"c0", + 759 => x"71", + 760 => x"ff", + 761 => x"88", + 762 => x"3d", + 763 => x"3d", + 764 => x"91", + 765 => x"70", + 766 => x"52", + 767 => x"94", + 768 => x"80", + 769 => x"87", + 770 => x"52", + 771 => x"82", + 772 => x"06", + 773 => x"ff", + 774 => x"2e", + 775 => x"81", + 776 => x"87", + 777 => x"52", + 778 => x"86", + 779 => x"94", + 780 => x"08", + 781 => x"70", + 782 => x"53", + 783 => x"ca", + 784 => x"3d", + 785 => x"3d", + 786 => x"9e", + 787 => x"9c", + 788 => x"51", + 789 => x"2e", + 790 => x"87", + 791 => x"08", + 792 => x"0c", + 793 => x"a0", + 794 => x"e8", + 795 => x"9e", + 796 => x"c6", + 797 => x"c0", + 798 => x"91", + 799 => x"87", + 800 => x"08", + 801 => x"0c", + 802 => x"98", + 803 => x"f8", + 804 => x"9e", + 805 => x"c6", + 806 => x"c0", + 807 => x"91", + 808 => x"87", + 809 => x"08", + 810 => x"0c", + 811 => x"80", + 812 => x"91", + 813 => x"87", + 814 => x"08", + 815 => x"0c", + 816 => x"c7", + 817 => x"0b", + 818 => x"88", + 819 => x"80", + 820 => x"52", + 821 => x"83", + 822 => x"71", + 823 => x"34", + 824 => x"c0", + 825 => x"70", + 826 => x"06", + 827 => x"70", + 828 => x"38", + 829 => x"91", + 830 => x"80", + 831 => x"9e", + 832 => x"80", + 833 => x"51", + 834 => x"80", + 835 => x"81", + 836 => x"c7", + 837 => x"0b", + 838 => x"88", + 839 => x"80", + 840 => x"52", + 841 => x"83", + 842 => x"71", + 843 => x"34", + 844 => x"c0", + 845 => x"70", + 846 => x"51", + 847 => x"80", + 848 => x"81", + 849 => x"c7", + 850 => x"0b", + 851 => x"88", + 852 => x"80", + 853 => x"52", + 854 => x"83", + 855 => x"71", + 856 => x"34", + 857 => x"c0", + 858 => x"70", + 859 => x"51", + 860 => x"80", + 861 => x"81", + 862 => x"c7", + 863 => x"0b", + 864 => x"88", + 865 => x"80", + 866 => x"52", + 867 => x"83", + 868 => x"71", + 869 => x"34", + 870 => x"88", + 871 => x"e0", + 872 => x"2c", + 873 => x"70", + 874 => x"34", + 875 => x"c0", + 876 => x"70", + 877 => x"52", + 878 => x"2e", + 879 => x"52", + 880 => x"9a", + 881 => x"87", + 882 => x"08", + 883 => x"51", + 884 => x"80", + 885 => x"81", + 886 => x"c7", + 887 => x"c0", + 888 => x"70", + 889 => x"51", + 890 => x"9c", + 891 => x"0d", + 892 => x"0d", + 893 => x"51", + 894 => x"91", + 895 => x"54", + 896 => x"88", + 897 => x"98", + 898 => x"3f", + 899 => x"51", + 900 => x"91", + 901 => x"54", + 902 => x"92", + 903 => x"e8", + 904 => x"c6", + 905 => x"91", + 906 => x"89", + 907 => x"c7", + 908 => x"73", + 909 => x"38", + 910 => x"08", + 911 => x"ec", + 912 => x"b4", + 913 => x"b9", + 914 => x"93", + 915 => x"8b", + 916 => x"94", + 917 => x"80", + 918 => x"91", + 919 => x"53", + 920 => x"08", + 921 => x"90", + 922 => x"3f", + 923 => x"33", + 924 => x"2e", + 925 => x"b5", + 926 => x"a1", + 927 => x"96", + 928 => x"80", + 929 => x"91", + 930 => x"83", + 931 => x"c7", + 932 => x"73", + 933 => x"38", + 934 => x"51", + 935 => x"91", + 936 => x"54", + 937 => x"8d", + 938 => x"99", + 939 => x"b5", + 940 => x"cd", + 941 => x"9a", + 942 => x"80", + 943 => x"91", + 944 => x"82", + 945 => x"c7", + 946 => x"73", + 947 => x"38", + 948 => x"33", + 949 => x"94", + 950 => x"3f", + 951 => x"51", + 952 => x"91", + 953 => x"52", + 954 => x"51", + 955 => x"91", + 956 => x"52", + 957 => x"51", + 958 => x"91", + 959 => x"52", + 960 => x"51", + 961 => x"91", + 962 => x"52", + 963 => x"51", + 964 => x"91", + 965 => x"52", + 966 => x"51", + 967 => x"85", + 968 => x"fe", + 969 => x"92", + 970 => x"05", + 971 => x"26", + 972 => x"84", + 973 => x"91", + 974 => x"52", + 975 => x"91", + 976 => x"9d", + 977 => x"8c", + 978 => x"91", + 979 => x"91", + 980 => x"9c", + 981 => x"91", + 982 => x"85", + 983 => x"a8", + 984 => x"3f", + 985 => x"04", + 986 => x"0c", + 987 => x"87", + 988 => x"0c", + 989 => x"0d", + 990 => x"84", + 991 => x"52", + 992 => x"70", + 993 => x"91", + 994 => x"72", + 995 => x"0d", + 996 => x"0d", + 997 => x"84", + 998 => x"c7", + 999 => x"80", + 1000 => x"09", + 1001 => x"a0", + 1002 => x"91", + 1003 => x"73", + 1004 => x"3d", + 1005 => x"c7", + 1006 => x"c0", + 1007 => x"04", + 1008 => x"02", + 1009 => x"53", + 1010 => x"09", + 1011 => x"38", + 1012 => x"3f", + 1013 => x"08", + 1014 => x"2e", + 1015 => x"72", + 1016 => x"a0", + 1017 => x"91", + 1018 => x"8f", + 1019 => x"98", + 1020 => x"80", + 1021 => x"72", + 1022 => x"84", + 1023 => x"fe", + 1024 => x"97", + 1025 => x"ca", + 1026 => x"91", + 1027 => x"54", + 1028 => x"3f", + 1029 => x"98", + 1030 => x"0d", + 1031 => x"0d", + 1032 => x"33", + 1033 => x"06", + 1034 => x"80", + 1035 => x"72", + 1036 => x"51", + 1037 => x"ff", + 1038 => x"39", + 1039 => x"04", + 1040 => x"77", + 1041 => x"08", + 1042 => x"98", + 1043 => x"73", + 1044 => x"ff", + 1045 => x"71", + 1046 => x"38", + 1047 => x"06", + 1048 => x"54", + 1049 => x"e7", + 1050 => x"ca", + 1051 => x"3d", + 1052 => x"3d", + 1053 => x"59", + 1054 => x"81", + 1055 => x"56", + 1056 => x"84", + 1057 => x"a5", + 1058 => x"06", + 1059 => x"80", + 1060 => x"81", + 1061 => x"58", + 1062 => x"b0", + 1063 => x"06", + 1064 => x"5a", + 1065 => x"ad", + 1066 => x"06", + 1067 => x"5a", + 1068 => x"05", + 1069 => x"75", + 1070 => x"81", + 1071 => x"77", + 1072 => x"08", + 1073 => x"05", + 1074 => x"5d", + 1075 => x"39", + 1076 => x"72", + 1077 => x"38", + 1078 => x"7b", + 1079 => x"05", + 1080 => x"70", + 1081 => x"33", + 1082 => x"39", + 1083 => x"32", + 1084 => x"72", + 1085 => x"78", + 1086 => x"70", + 1087 => x"07", + 1088 => x"07", + 1089 => x"51", + 1090 => x"80", + 1091 => x"79", + 1092 => x"70", + 1093 => x"33", + 1094 => x"80", + 1095 => x"38", + 1096 => x"e0", + 1097 => x"38", + 1098 => x"81", + 1099 => x"53", + 1100 => x"2e", + 1101 => x"73", + 1102 => x"a2", + 1103 => x"c3", + 1104 => x"38", + 1105 => x"24", + 1106 => x"80", + 1107 => x"8c", + 1108 => x"39", + 1109 => x"2e", + 1110 => x"81", + 1111 => x"80", + 1112 => x"80", + 1113 => x"d5", + 1114 => x"73", + 1115 => x"8e", + 1116 => x"39", + 1117 => x"2e", + 1118 => x"80", + 1119 => x"84", + 1120 => x"56", + 1121 => x"74", + 1122 => x"72", + 1123 => x"38", + 1124 => x"15", + 1125 => x"54", + 1126 => x"38", + 1127 => x"56", + 1128 => x"81", + 1129 => x"72", + 1130 => x"38", + 1131 => x"90", + 1132 => x"06", + 1133 => x"2e", + 1134 => x"51", + 1135 => x"74", + 1136 => x"53", + 1137 => x"fd", + 1138 => x"51", + 1139 => x"ef", + 1140 => x"19", + 1141 => x"53", + 1142 => x"39", + 1143 => x"39", + 1144 => x"39", + 1145 => x"39", + 1146 => x"39", + 1147 => x"d0", + 1148 => x"39", + 1149 => x"70", + 1150 => x"53", + 1151 => x"88", + 1152 => x"19", + 1153 => x"39", + 1154 => x"54", + 1155 => x"74", + 1156 => x"70", + 1157 => x"07", + 1158 => x"55", + 1159 => x"80", + 1160 => x"72", + 1161 => x"38", + 1162 => x"90", + 1163 => x"80", + 1164 => x"5e", + 1165 => x"74", + 1166 => x"3f", + 1167 => x"08", + 1168 => x"7c", + 1169 => x"54", + 1170 => x"91", + 1171 => x"55", + 1172 => x"92", + 1173 => x"53", + 1174 => x"2e", + 1175 => x"14", + 1176 => x"ff", + 1177 => x"14", + 1178 => x"70", + 1179 => x"34", + 1180 => x"30", + 1181 => x"9f", + 1182 => x"57", + 1183 => x"85", + 1184 => x"b1", + 1185 => x"2a", + 1186 => x"51", + 1187 => x"2e", + 1188 => x"3d", + 1189 => x"05", + 1190 => x"34", + 1191 => x"76", + 1192 => x"54", + 1193 => x"72", + 1194 => x"54", + 1195 => x"70", + 1196 => x"56", + 1197 => x"81", + 1198 => x"7b", + 1199 => x"73", + 1200 => x"3f", + 1201 => x"53", + 1202 => x"74", + 1203 => x"53", + 1204 => x"eb", + 1205 => x"77", + 1206 => x"53", + 1207 => x"14", + 1208 => x"54", + 1209 => x"3f", + 1210 => x"74", + 1211 => x"53", + 1212 => x"fb", + 1213 => x"51", + 1214 => x"ef", + 1215 => x"0d", + 1216 => x"0d", + 1217 => x"70", + 1218 => x"08", + 1219 => x"51", + 1220 => x"85", + 1221 => x"fe", + 1222 => x"91", + 1223 => x"85", + 1224 => x"52", + 1225 => x"ca", + 1226 => x"a0", + 1227 => x"73", + 1228 => x"91", + 1229 => x"84", + 1230 => x"fd", + 1231 => x"ca", + 1232 => x"91", + 1233 => x"87", + 1234 => x"53", + 1235 => x"fa", + 1236 => x"91", + 1237 => x"85", + 1238 => x"fb", + 1239 => x"79", + 1240 => x"08", + 1241 => x"57", + 1242 => x"71", + 1243 => x"e0", + 1244 => x"9c", + 1245 => x"2d", + 1246 => x"08", + 1247 => x"53", + 1248 => x"80", + 1249 => x"8d", + 1250 => x"72", + 1251 => x"30", + 1252 => x"51", + 1253 => x"80", + 1254 => x"71", + 1255 => x"38", + 1256 => x"97", + 1257 => x"25", + 1258 => x"16", + 1259 => x"25", + 1260 => x"14", + 1261 => x"34", + 1262 => x"72", + 1263 => x"3f", + 1264 => x"73", + 1265 => x"72", + 1266 => x"f7", + 1267 => x"53", + 1268 => x"88", + 1269 => x"0d", + 1270 => x"0d", + 1271 => x"08", + 1272 => x"9c", + 1273 => x"76", + 1274 => x"ef", + 1275 => x"ca", + 1276 => x"3d", + 1277 => x"3d", + 1278 => x"5a", + 1279 => x"7a", + 1280 => x"08", + 1281 => x"53", + 1282 => x"09", + 1283 => x"38", + 1284 => x"0c", + 1285 => x"ad", + 1286 => x"06", + 1287 => x"76", + 1288 => x"0c", + 1289 => x"33", + 1290 => x"73", + 1291 => x"81", + 1292 => x"38", + 1293 => x"05", + 1294 => x"08", + 1295 => x"53", + 1296 => x"2e", + 1297 => x"57", + 1298 => x"2e", + 1299 => x"39", + 1300 => x"13", + 1301 => x"08", + 1302 => x"53", + 1303 => x"55", + 1304 => x"80", + 1305 => x"14", + 1306 => x"88", + 1307 => x"27", + 1308 => x"eb", + 1309 => x"53", + 1310 => x"89", + 1311 => x"38", + 1312 => x"55", + 1313 => x"8a", + 1314 => x"a0", + 1315 => x"c2", + 1316 => x"74", + 1317 => x"e0", + 1318 => x"ff", + 1319 => x"d0", + 1320 => x"ff", + 1321 => x"90", + 1322 => x"38", + 1323 => x"81", + 1324 => x"53", + 1325 => x"ca", + 1326 => x"27", + 1327 => x"77", + 1328 => x"08", + 1329 => x"0c", + 1330 => x"33", + 1331 => x"ff", + 1332 => x"80", + 1333 => x"74", + 1334 => x"79", + 1335 => x"74", + 1336 => x"0c", + 1337 => x"04", + 1338 => x"7a", + 1339 => x"80", + 1340 => x"58", + 1341 => x"33", + 1342 => x"a0", + 1343 => x"06", + 1344 => x"13", + 1345 => x"39", + 1346 => x"09", + 1347 => x"38", + 1348 => x"11", + 1349 => x"08", + 1350 => x"54", + 1351 => x"2e", + 1352 => x"80", + 1353 => x"08", + 1354 => x"0c", + 1355 => x"33", + 1356 => x"80", + 1357 => x"38", + 1358 => x"80", + 1359 => x"38", + 1360 => x"57", + 1361 => x"0c", + 1362 => x"33", + 1363 => x"39", + 1364 => x"74", + 1365 => x"38", + 1366 => x"80", + 1367 => x"89", + 1368 => x"38", + 1369 => x"d0", + 1370 => x"55", + 1371 => x"80", + 1372 => x"39", + 1373 => x"d9", + 1374 => x"80", + 1375 => x"27", + 1376 => x"80", + 1377 => x"89", + 1378 => x"70", + 1379 => x"55", + 1380 => x"70", + 1381 => x"55", + 1382 => x"27", + 1383 => x"14", + 1384 => x"06", + 1385 => x"74", + 1386 => x"73", + 1387 => x"38", + 1388 => x"14", + 1389 => x"05", + 1390 => x"08", + 1391 => x"54", + 1392 => x"39", + 1393 => x"84", + 1394 => x"55", + 1395 => x"81", + 1396 => x"ca", + 1397 => x"3d", + 1398 => x"3d", + 1399 => x"05", + 1400 => x"52", + 1401 => x"87", + 1402 => x"a4", + 1403 => x"71", + 1404 => x"0c", + 1405 => x"04", + 1406 => x"02", + 1407 => x"02", + 1408 => x"05", + 1409 => x"83", + 1410 => x"26", + 1411 => x"72", + 1412 => x"c0", + 1413 => x"53", + 1414 => x"74", + 1415 => x"38", + 1416 => x"73", + 1417 => x"c0", + 1418 => x"51", + 1419 => x"85", + 1420 => x"98", + 1421 => x"52", + 1422 => x"82", + 1423 => x"70", + 1424 => x"38", + 1425 => x"8c", + 1426 => x"ec", + 1427 => x"fc", + 1428 => x"52", + 1429 => x"87", + 1430 => x"08", + 1431 => x"2e", + 1432 => x"91", + 1433 => x"34", + 1434 => x"13", + 1435 => x"91", + 1436 => x"86", + 1437 => x"f3", + 1438 => x"62", + 1439 => x"05", + 1440 => x"57", + 1441 => x"83", + 1442 => x"fe", + 1443 => x"ca", + 1444 => x"06", + 1445 => x"71", + 1446 => x"71", + 1447 => x"2b", + 1448 => x"80", + 1449 => x"92", + 1450 => x"c0", + 1451 => x"41", + 1452 => x"5a", + 1453 => x"87", + 1454 => x"0c", + 1455 => x"84", + 1456 => x"08", + 1457 => x"70", + 1458 => x"53", + 1459 => x"2e", + 1460 => x"08", + 1461 => x"70", + 1462 => x"34", + 1463 => x"80", + 1464 => x"53", + 1465 => x"2e", + 1466 => x"53", + 1467 => x"26", + 1468 => x"80", + 1469 => x"87", + 1470 => x"08", + 1471 => x"38", + 1472 => x"8c", + 1473 => x"80", + 1474 => x"78", + 1475 => x"99", + 1476 => x"0c", + 1477 => x"8c", + 1478 => x"08", + 1479 => x"51", + 1480 => x"38", + 1481 => x"8d", + 1482 => x"17", + 1483 => x"81", + 1484 => x"53", + 1485 => x"2e", + 1486 => x"fc", + 1487 => x"52", + 1488 => x"7d", + 1489 => x"ed", + 1490 => x"80", + 1491 => x"71", + 1492 => x"38", + 1493 => x"53", + 1494 => x"88", + 1495 => x"0d", + 1496 => x"0d", + 1497 => x"02", + 1498 => x"05", + 1499 => x"58", + 1500 => x"80", + 1501 => x"fc", + 1502 => x"ca", + 1503 => x"06", + 1504 => x"71", + 1505 => x"81", + 1506 => x"38", + 1507 => x"2b", + 1508 => x"80", + 1509 => x"92", + 1510 => x"c0", + 1511 => x"40", + 1512 => x"5a", + 1513 => x"c0", + 1514 => x"76", + 1515 => x"76", + 1516 => x"75", + 1517 => x"2a", + 1518 => x"51", + 1519 => x"80", + 1520 => x"7a", + 1521 => x"5c", + 1522 => x"81", + 1523 => x"81", + 1524 => x"06", + 1525 => x"80", + 1526 => x"87", + 1527 => x"08", + 1528 => x"38", + 1529 => x"8c", + 1530 => x"80", + 1531 => x"77", + 1532 => x"99", + 1533 => x"0c", + 1534 => x"8c", + 1535 => x"08", + 1536 => x"51", + 1537 => x"38", + 1538 => x"8d", + 1539 => x"70", + 1540 => x"84", + 1541 => x"5b", + 1542 => x"2e", + 1543 => x"fc", + 1544 => x"52", + 1545 => x"7d", + 1546 => x"f8", + 1547 => x"80", + 1548 => x"71", + 1549 => x"38", + 1550 => x"53", + 1551 => x"88", + 1552 => x"0d", + 1553 => x"0d", + 1554 => x"05", + 1555 => x"02", + 1556 => x"05", + 1557 => x"54", + 1558 => x"fe", + 1559 => x"88", + 1560 => x"53", + 1561 => x"80", + 1562 => x"0b", + 1563 => x"8c", + 1564 => x"71", + 1565 => x"dc", + 1566 => x"24", + 1567 => x"84", + 1568 => x"92", + 1569 => x"54", + 1570 => x"8d", + 1571 => x"39", + 1572 => x"80", + 1573 => x"cb", + 1574 => x"70", + 1575 => x"81", + 1576 => x"52", + 1577 => x"8a", + 1578 => x"98", + 1579 => x"71", + 1580 => x"c0", + 1581 => x"52", + 1582 => x"81", + 1583 => x"c0", + 1584 => x"53", + 1585 => x"82", + 1586 => x"71", + 1587 => x"39", + 1588 => x"39", + 1589 => x"77", + 1590 => x"81", + 1591 => x"72", + 1592 => x"84", + 1593 => x"73", + 1594 => x"0c", + 1595 => x"04", + 1596 => x"74", + 1597 => x"71", + 1598 => x"2b", + 1599 => x"88", + 1600 => x"84", + 1601 => x"fd", + 1602 => x"83", + 1603 => x"12", + 1604 => x"2b", + 1605 => x"07", + 1606 => x"70", + 1607 => x"2b", + 1608 => x"07", + 1609 => x"0c", + 1610 => x"56", + 1611 => x"3d", + 1612 => x"3d", + 1613 => x"84", + 1614 => x"22", + 1615 => x"72", + 1616 => x"54", + 1617 => x"2a", + 1618 => x"34", + 1619 => x"04", + 1620 => x"73", + 1621 => x"70", + 1622 => x"05", + 1623 => x"88", + 1624 => x"72", + 1625 => x"54", + 1626 => x"2a", + 1627 => x"70", + 1628 => x"34", + 1629 => x"51", + 1630 => x"83", + 1631 => x"fe", + 1632 => x"75", + 1633 => x"51", + 1634 => x"92", + 1635 => x"81", + 1636 => x"73", + 1637 => x"55", + 1638 => x"51", + 1639 => x"3d", + 1640 => x"3d", + 1641 => x"76", + 1642 => x"72", + 1643 => x"05", + 1644 => x"11", + 1645 => x"38", + 1646 => x"04", + 1647 => x"78", + 1648 => x"56", + 1649 => x"81", + 1650 => x"74", + 1651 => x"56", + 1652 => x"31", + 1653 => x"52", + 1654 => x"80", + 1655 => x"71", + 1656 => x"38", + 1657 => x"88", + 1658 => x"0d", + 1659 => x"0d", + 1660 => x"51", + 1661 => x"73", + 1662 => x"81", + 1663 => x"33", + 1664 => x"38", + 1665 => x"ca", + 1666 => x"3d", + 1667 => x"0b", + 1668 => x"0c", + 1669 => x"91", + 1670 => x"04", + 1671 => x"7b", + 1672 => x"83", + 1673 => x"5a", + 1674 => x"80", + 1675 => x"54", + 1676 => x"53", + 1677 => x"53", + 1678 => x"52", + 1679 => x"3f", + 1680 => x"08", + 1681 => x"81", + 1682 => x"91", + 1683 => x"83", + 1684 => x"16", + 1685 => x"18", + 1686 => x"18", + 1687 => x"58", + 1688 => x"9f", + 1689 => x"33", + 1690 => x"2e", + 1691 => x"93", + 1692 => x"76", + 1693 => x"52", + 1694 => x"51", + 1695 => x"83", + 1696 => x"79", + 1697 => x"0c", + 1698 => x"04", + 1699 => x"78", + 1700 => x"80", + 1701 => x"17", + 1702 => x"38", + 1703 => x"fc", + 1704 => x"88", + 1705 => x"ca", + 1706 => x"38", + 1707 => x"53", + 1708 => x"81", + 1709 => x"f7", + 1710 => x"ca", + 1711 => x"2e", + 1712 => x"55", + 1713 => x"b0", + 1714 => x"91", + 1715 => x"88", + 1716 => x"f8", + 1717 => x"70", + 1718 => x"c0", + 1719 => x"88", + 1720 => x"ca", + 1721 => x"91", + 1722 => x"55", + 1723 => x"09", + 1724 => x"f0", + 1725 => x"33", + 1726 => x"2e", + 1727 => x"80", + 1728 => x"80", + 1729 => x"88", + 1730 => x"17", + 1731 => x"fd", + 1732 => x"d4", + 1733 => x"b2", + 1734 => x"96", + 1735 => x"85", + 1736 => x"75", + 1737 => x"3f", + 1738 => x"e4", + 1739 => x"98", + 1740 => x"9c", + 1741 => x"08", + 1742 => x"17", + 1743 => x"3f", + 1744 => x"52", + 1745 => x"51", + 1746 => x"a0", + 1747 => x"05", + 1748 => x"0c", + 1749 => x"75", + 1750 => x"33", + 1751 => x"3f", + 1752 => x"34", + 1753 => x"52", + 1754 => x"51", + 1755 => x"91", + 1756 => x"80", + 1757 => x"81", + 1758 => x"ca", + 1759 => x"3d", + 1760 => x"3d", + 1761 => x"1a", + 1762 => x"fe", + 1763 => x"54", + 1764 => x"73", + 1765 => x"8a", + 1766 => x"71", + 1767 => x"08", + 1768 => x"75", + 1769 => x"0c", + 1770 => x"04", + 1771 => x"7a", + 1772 => x"56", + 1773 => x"77", + 1774 => x"38", + 1775 => x"08", + 1776 => x"38", + 1777 => x"54", + 1778 => x"2e", + 1779 => x"72", + 1780 => x"38", + 1781 => x"8d", + 1782 => x"39", + 1783 => x"81", + 1784 => x"b6", + 1785 => x"2a", + 1786 => x"2a", + 1787 => x"05", + 1788 => x"55", + 1789 => x"91", + 1790 => x"81", + 1791 => x"83", + 1792 => x"b4", + 1793 => x"17", + 1794 => x"a4", + 1795 => x"55", + 1796 => x"57", + 1797 => x"3f", + 1798 => x"08", + 1799 => x"74", + 1800 => x"14", + 1801 => x"70", + 1802 => x"07", + 1803 => x"71", + 1804 => x"52", + 1805 => x"72", + 1806 => x"75", + 1807 => x"58", + 1808 => x"76", + 1809 => x"15", + 1810 => x"73", + 1811 => x"3f", + 1812 => x"08", + 1813 => x"76", + 1814 => x"06", + 1815 => x"05", + 1816 => x"3f", + 1817 => x"08", + 1818 => x"06", + 1819 => x"76", + 1820 => x"15", + 1821 => x"73", + 1822 => x"3f", + 1823 => x"08", + 1824 => x"82", + 1825 => x"06", + 1826 => x"05", + 1827 => x"3f", + 1828 => x"08", + 1829 => x"58", + 1830 => x"58", + 1831 => x"88", + 1832 => x"0d", + 1833 => x"0d", + 1834 => x"5a", + 1835 => x"59", + 1836 => x"82", + 1837 => x"98", + 1838 => x"82", + 1839 => x"33", + 1840 => x"2e", + 1841 => x"72", + 1842 => x"38", + 1843 => x"8d", + 1844 => x"39", + 1845 => x"81", + 1846 => x"f7", + 1847 => x"2a", + 1848 => x"2a", + 1849 => x"05", + 1850 => x"55", + 1851 => x"91", + 1852 => x"59", + 1853 => x"08", + 1854 => x"74", + 1855 => x"16", + 1856 => x"16", + 1857 => x"59", + 1858 => x"53", + 1859 => x"8f", + 1860 => x"2b", + 1861 => x"74", + 1862 => x"71", + 1863 => x"72", + 1864 => x"0b", + 1865 => x"74", + 1866 => x"17", + 1867 => x"75", + 1868 => x"3f", + 1869 => x"08", + 1870 => x"88", + 1871 => x"38", + 1872 => x"06", + 1873 => x"78", + 1874 => x"54", + 1875 => x"77", + 1876 => x"33", + 1877 => x"71", + 1878 => x"51", + 1879 => x"34", + 1880 => x"76", + 1881 => x"17", + 1882 => x"75", + 1883 => x"3f", + 1884 => x"08", + 1885 => x"88", + 1886 => x"38", + 1887 => x"ff", + 1888 => x"10", + 1889 => x"76", + 1890 => x"51", + 1891 => x"be", + 1892 => x"2a", + 1893 => x"05", + 1894 => x"f9", + 1895 => x"ca", + 1896 => x"91", + 1897 => x"ab", + 1898 => x"0a", + 1899 => x"2b", + 1900 => x"70", + 1901 => x"70", + 1902 => x"54", + 1903 => x"91", + 1904 => x"8f", + 1905 => x"07", + 1906 => x"f7", + 1907 => x"0b", + 1908 => x"78", + 1909 => x"0c", + 1910 => x"04", + 1911 => x"7a", + 1912 => x"08", + 1913 => x"59", + 1914 => x"a4", + 1915 => x"17", + 1916 => x"38", + 1917 => x"aa", + 1918 => x"73", + 1919 => x"fd", + 1920 => x"ca", + 1921 => x"91", + 1922 => x"80", + 1923 => x"39", + 1924 => x"eb", + 1925 => x"80", + 1926 => x"ca", + 1927 => x"80", + 1928 => x"52", + 1929 => x"84", + 1930 => x"88", + 1931 => x"ca", + 1932 => x"2e", + 1933 => x"91", + 1934 => x"81", + 1935 => x"91", + 1936 => x"ff", + 1937 => x"80", + 1938 => x"75", + 1939 => x"3f", + 1940 => x"08", + 1941 => x"16", + 1942 => x"90", + 1943 => x"55", + 1944 => x"27", + 1945 => x"15", + 1946 => x"84", + 1947 => x"07", + 1948 => x"17", + 1949 => x"76", + 1950 => x"a6", + 1951 => x"73", + 1952 => x"0c", + 1953 => x"04", + 1954 => x"7c", + 1955 => x"59", + 1956 => x"95", + 1957 => x"08", + 1958 => x"2e", + 1959 => x"17", + 1960 => x"b2", + 1961 => x"ae", + 1962 => x"7a", + 1963 => x"3f", + 1964 => x"91", + 1965 => x"27", + 1966 => x"91", + 1967 => x"55", + 1968 => x"08", + 1969 => x"d2", + 1970 => x"08", + 1971 => x"08", + 1972 => x"38", + 1973 => x"17", + 1974 => x"54", + 1975 => x"82", + 1976 => x"7a", + 1977 => x"06", + 1978 => x"81", + 1979 => x"17", + 1980 => x"83", + 1981 => x"75", + 1982 => x"f9", + 1983 => x"59", + 1984 => x"08", + 1985 => x"81", + 1986 => x"91", + 1987 => x"59", + 1988 => x"08", + 1989 => x"70", + 1990 => x"25", + 1991 => x"91", + 1992 => x"54", + 1993 => x"55", + 1994 => x"38", + 1995 => x"08", + 1996 => x"38", + 1997 => x"54", + 1998 => x"90", + 1999 => x"18", + 2000 => x"38", + 2001 => x"39", + 2002 => x"38", + 2003 => x"16", + 2004 => x"08", + 2005 => x"38", + 2006 => x"78", + 2007 => x"38", + 2008 => x"51", + 2009 => x"91", + 2010 => x"80", + 2011 => x"80", + 2012 => x"88", + 2013 => x"09", + 2014 => x"38", + 2015 => x"08", + 2016 => x"88", + 2017 => x"30", + 2018 => x"80", + 2019 => x"07", + 2020 => x"55", + 2021 => x"38", + 2022 => x"09", + 2023 => x"ae", + 2024 => x"80", + 2025 => x"53", + 2026 => x"51", + 2027 => x"91", + 2028 => x"91", + 2029 => x"30", + 2030 => x"88", + 2031 => x"25", + 2032 => x"79", + 2033 => x"38", + 2034 => x"8f", + 2035 => x"79", + 2036 => x"f9", + 2037 => x"ca", + 2038 => x"74", + 2039 => x"8c", + 2040 => x"17", + 2041 => x"90", + 2042 => x"54", + 2043 => x"86", + 2044 => x"90", + 2045 => x"17", + 2046 => x"54", + 2047 => x"34", + 2048 => x"56", + 2049 => x"90", + 2050 => x"80", + 2051 => x"91", + 2052 => x"55", + 2053 => x"56", + 2054 => x"91", + 2055 => x"8c", + 2056 => x"f8", + 2057 => x"70", + 2058 => x"f0", + 2059 => x"88", + 2060 => x"56", + 2061 => x"08", + 2062 => x"7b", + 2063 => x"f6", + 2064 => x"ca", + 2065 => x"ca", + 2066 => x"17", + 2067 => x"80", + 2068 => x"b4", + 2069 => x"57", + 2070 => x"77", + 2071 => x"81", + 2072 => x"15", + 2073 => x"78", + 2074 => x"81", + 2075 => x"53", + 2076 => x"15", + 2077 => x"e9", + 2078 => x"88", + 2079 => x"df", + 2080 => x"22", + 2081 => x"30", + 2082 => x"70", + 2083 => x"51", + 2084 => x"91", + 2085 => x"8a", + 2086 => x"f8", + 2087 => x"7c", + 2088 => x"56", + 2089 => x"80", + 2090 => x"f1", + 2091 => x"06", + 2092 => x"e9", + 2093 => x"18", + 2094 => x"08", + 2095 => x"38", + 2096 => x"82", + 2097 => x"38", + 2098 => x"54", + 2099 => x"74", + 2100 => x"82", + 2101 => x"22", + 2102 => x"79", + 2103 => x"38", + 2104 => x"98", + 2105 => x"cd", + 2106 => x"22", + 2107 => x"54", + 2108 => x"26", + 2109 => x"52", + 2110 => x"b0", + 2111 => x"88", + 2112 => x"ca", + 2113 => x"2e", + 2114 => x"0b", + 2115 => x"08", + 2116 => x"98", + 2117 => x"ca", + 2118 => x"85", + 2119 => x"bd", + 2120 => x"31", + 2121 => x"73", + 2122 => x"f4", + 2123 => x"ca", + 2124 => x"18", + 2125 => x"18", + 2126 => x"08", + 2127 => x"72", + 2128 => x"38", + 2129 => x"58", + 2130 => x"89", + 2131 => x"18", + 2132 => x"ff", + 2133 => x"05", + 2134 => x"80", + 2135 => x"ca", + 2136 => x"3d", + 2137 => x"3d", + 2138 => x"08", + 2139 => x"a0", + 2140 => x"54", + 2141 => x"77", + 2142 => x"80", + 2143 => x"0c", + 2144 => x"53", + 2145 => x"80", + 2146 => x"38", + 2147 => x"06", + 2148 => x"b5", + 2149 => x"98", + 2150 => x"14", + 2151 => x"92", + 2152 => x"2a", + 2153 => x"56", + 2154 => x"26", + 2155 => x"80", + 2156 => x"16", + 2157 => x"77", + 2158 => x"53", + 2159 => x"38", + 2160 => x"51", + 2161 => x"91", + 2162 => x"53", + 2163 => x"0b", + 2164 => x"08", + 2165 => x"38", + 2166 => x"ca", + 2167 => x"2e", + 2168 => x"98", + 2169 => x"ca", + 2170 => x"80", + 2171 => x"8a", + 2172 => x"15", + 2173 => x"80", + 2174 => x"14", + 2175 => x"51", + 2176 => x"91", + 2177 => x"53", + 2178 => x"ca", + 2179 => x"2e", + 2180 => x"82", + 2181 => x"88", + 2182 => x"ba", + 2183 => x"91", + 2184 => x"ff", + 2185 => x"91", + 2186 => x"52", + 2187 => x"f3", + 2188 => x"88", + 2189 => x"72", + 2190 => x"72", + 2191 => x"f2", + 2192 => x"ca", + 2193 => x"15", + 2194 => x"15", + 2195 => x"b4", + 2196 => x"0c", + 2197 => x"91", + 2198 => x"8a", + 2199 => x"f7", + 2200 => x"7d", + 2201 => x"5b", + 2202 => x"76", + 2203 => x"3f", + 2204 => x"08", + 2205 => x"88", + 2206 => x"38", + 2207 => x"08", + 2208 => x"08", + 2209 => x"f0", + 2210 => x"ca", + 2211 => x"91", + 2212 => x"80", + 2213 => x"ca", + 2214 => x"18", + 2215 => x"51", + 2216 => x"81", + 2217 => x"81", + 2218 => x"81", + 2219 => x"88", + 2220 => x"83", + 2221 => x"77", + 2222 => x"72", + 2223 => x"38", + 2224 => x"75", + 2225 => x"81", + 2226 => x"a5", + 2227 => x"88", + 2228 => x"52", + 2229 => x"8e", + 2230 => x"88", + 2231 => x"ca", + 2232 => x"2e", + 2233 => x"73", + 2234 => x"81", + 2235 => x"87", + 2236 => x"ca", + 2237 => x"3d", + 2238 => x"3d", + 2239 => x"11", + 2240 => x"ec", + 2241 => x"88", + 2242 => x"ff", + 2243 => x"33", + 2244 => x"71", + 2245 => x"81", + 2246 => x"94", + 2247 => x"d0", + 2248 => x"88", + 2249 => x"73", + 2250 => x"91", + 2251 => x"85", + 2252 => x"fc", + 2253 => x"79", + 2254 => x"ff", + 2255 => x"12", + 2256 => x"eb", + 2257 => x"70", + 2258 => x"72", + 2259 => x"81", + 2260 => x"73", + 2261 => x"94", + 2262 => x"d6", + 2263 => x"0d", + 2264 => x"0d", + 2265 => x"55", + 2266 => x"5a", + 2267 => x"08", + 2268 => x"8a", + 2269 => x"08", + 2270 => x"ee", + 2271 => x"ca", + 2272 => x"91", + 2273 => x"80", + 2274 => x"15", + 2275 => x"55", + 2276 => x"38", + 2277 => x"e6", + 2278 => x"33", + 2279 => x"70", + 2280 => x"58", + 2281 => x"86", + 2282 => x"ca", + 2283 => x"73", + 2284 => x"83", + 2285 => x"73", + 2286 => x"38", + 2287 => x"06", + 2288 => x"80", + 2289 => x"75", + 2290 => x"38", + 2291 => x"08", + 2292 => x"54", + 2293 => x"2e", + 2294 => x"83", + 2295 => x"73", + 2296 => x"38", + 2297 => x"51", + 2298 => x"91", + 2299 => x"58", + 2300 => x"08", + 2301 => x"15", + 2302 => x"38", + 2303 => x"0b", + 2304 => x"77", + 2305 => x"0c", + 2306 => x"04", + 2307 => x"77", + 2308 => x"54", + 2309 => x"51", + 2310 => x"91", + 2311 => x"55", + 2312 => x"08", + 2313 => x"14", + 2314 => x"51", + 2315 => x"91", + 2316 => x"55", + 2317 => x"08", + 2318 => x"53", + 2319 => x"08", + 2320 => x"08", + 2321 => x"3f", + 2322 => x"14", + 2323 => x"08", + 2324 => x"3f", + 2325 => x"17", + 2326 => x"ca", + 2327 => x"3d", + 2328 => x"3d", + 2329 => x"08", + 2330 => x"54", + 2331 => x"53", + 2332 => x"91", + 2333 => x"8d", + 2334 => x"08", + 2335 => x"34", + 2336 => x"15", + 2337 => x"0d", + 2338 => x"0d", + 2339 => x"57", + 2340 => x"17", + 2341 => x"08", + 2342 => x"82", + 2343 => x"89", + 2344 => x"55", + 2345 => x"14", + 2346 => x"16", + 2347 => x"71", + 2348 => x"38", + 2349 => x"09", + 2350 => x"38", + 2351 => x"73", + 2352 => x"81", + 2353 => x"ae", + 2354 => x"05", + 2355 => x"15", + 2356 => x"70", + 2357 => x"34", + 2358 => x"8a", + 2359 => x"38", + 2360 => x"05", + 2361 => x"81", + 2362 => x"17", + 2363 => x"12", + 2364 => x"34", + 2365 => x"9c", + 2366 => x"e8", + 2367 => x"ca", + 2368 => x"0c", + 2369 => x"e7", + 2370 => x"ca", + 2371 => x"17", + 2372 => x"51", + 2373 => x"91", + 2374 => x"84", + 2375 => x"3d", + 2376 => x"3d", + 2377 => x"08", + 2378 => x"61", + 2379 => x"55", + 2380 => x"2e", + 2381 => x"55", + 2382 => x"2e", + 2383 => x"80", + 2384 => x"94", + 2385 => x"1c", + 2386 => x"81", + 2387 => x"61", + 2388 => x"56", + 2389 => x"2e", + 2390 => x"83", + 2391 => x"73", + 2392 => x"70", + 2393 => x"25", + 2394 => x"51", + 2395 => x"38", + 2396 => x"0c", + 2397 => x"51", + 2398 => x"26", + 2399 => x"80", + 2400 => x"34", + 2401 => x"51", + 2402 => x"91", + 2403 => x"55", + 2404 => x"91", + 2405 => x"1d", + 2406 => x"8b", + 2407 => x"79", + 2408 => x"3f", + 2409 => x"57", + 2410 => x"55", + 2411 => x"2e", + 2412 => x"80", + 2413 => x"18", + 2414 => x"1a", + 2415 => x"70", + 2416 => x"2a", + 2417 => x"07", + 2418 => x"5a", + 2419 => x"8c", + 2420 => x"54", + 2421 => x"81", + 2422 => x"39", + 2423 => x"70", + 2424 => x"2a", + 2425 => x"75", + 2426 => x"8c", + 2427 => x"2e", + 2428 => x"a0", + 2429 => x"38", + 2430 => x"0c", + 2431 => x"76", + 2432 => x"38", + 2433 => x"b8", + 2434 => x"70", + 2435 => x"5a", + 2436 => x"76", + 2437 => x"38", + 2438 => x"70", + 2439 => x"dc", + 2440 => x"72", + 2441 => x"80", + 2442 => x"51", + 2443 => x"73", + 2444 => x"38", + 2445 => x"18", + 2446 => x"1a", + 2447 => x"55", + 2448 => x"2e", + 2449 => x"83", + 2450 => x"73", + 2451 => x"70", + 2452 => x"25", + 2453 => x"51", + 2454 => x"38", + 2455 => x"75", + 2456 => x"81", + 2457 => x"81", + 2458 => x"27", + 2459 => x"73", + 2460 => x"38", + 2461 => x"70", + 2462 => x"32", + 2463 => x"80", + 2464 => x"2a", + 2465 => x"56", + 2466 => x"81", + 2467 => x"57", + 2468 => x"f5", + 2469 => x"2b", + 2470 => x"25", + 2471 => x"80", + 2472 => x"b9", + 2473 => x"57", + 2474 => x"e6", + 2475 => x"ca", + 2476 => x"2e", + 2477 => x"18", + 2478 => x"1a", + 2479 => x"56", + 2480 => x"3f", + 2481 => x"08", + 2482 => x"e8", + 2483 => x"54", + 2484 => x"80", + 2485 => x"17", + 2486 => x"34", + 2487 => x"11", + 2488 => x"74", + 2489 => x"75", + 2490 => x"b4", + 2491 => x"3f", + 2492 => x"08", + 2493 => x"9f", + 2494 => x"99", + 2495 => x"e0", + 2496 => x"ff", + 2497 => x"79", + 2498 => x"74", + 2499 => x"57", + 2500 => x"77", + 2501 => x"76", + 2502 => x"38", + 2503 => x"73", + 2504 => x"09", + 2505 => x"38", + 2506 => x"84", + 2507 => x"27", + 2508 => x"39", + 2509 => x"f2", + 2510 => x"80", + 2511 => x"54", + 2512 => x"34", + 2513 => x"58", + 2514 => x"f2", + 2515 => x"ca", + 2516 => x"91", + 2517 => x"80", + 2518 => x"1b", + 2519 => x"51", + 2520 => x"91", + 2521 => x"56", + 2522 => x"08", + 2523 => x"9c", + 2524 => x"33", + 2525 => x"80", + 2526 => x"38", + 2527 => x"bf", + 2528 => x"86", + 2529 => x"15", + 2530 => x"2a", + 2531 => x"51", + 2532 => x"92", + 2533 => x"79", + 2534 => x"e4", + 2535 => x"ca", + 2536 => x"2e", + 2537 => x"52", + 2538 => x"ba", + 2539 => x"39", + 2540 => x"33", + 2541 => x"80", + 2542 => x"74", + 2543 => x"81", + 2544 => x"38", + 2545 => x"70", + 2546 => x"82", + 2547 => x"54", + 2548 => x"96", + 2549 => x"06", + 2550 => x"2e", + 2551 => x"ff", + 2552 => x"1c", + 2553 => x"80", + 2554 => x"81", + 2555 => x"ba", + 2556 => x"b6", + 2557 => x"2a", + 2558 => x"51", + 2559 => x"38", + 2560 => x"70", + 2561 => x"81", + 2562 => x"55", + 2563 => x"e1", + 2564 => x"08", + 2565 => x"1d", + 2566 => x"7c", + 2567 => x"3f", + 2568 => x"08", + 2569 => x"fa", + 2570 => x"91", + 2571 => x"8f", + 2572 => x"f6", + 2573 => x"5b", + 2574 => x"70", + 2575 => x"59", + 2576 => x"73", + 2577 => x"c6", + 2578 => x"81", + 2579 => x"70", + 2580 => x"52", + 2581 => x"8d", + 2582 => x"38", + 2583 => x"09", + 2584 => x"a5", + 2585 => x"d0", + 2586 => x"ff", + 2587 => x"53", + 2588 => x"91", + 2589 => x"73", + 2590 => x"d0", + 2591 => x"71", + 2592 => x"f7", + 2593 => x"91", + 2594 => x"55", + 2595 => x"55", + 2596 => x"81", + 2597 => x"74", + 2598 => x"56", + 2599 => x"12", + 2600 => x"70", + 2601 => x"38", + 2602 => x"81", + 2603 => x"51", + 2604 => x"51", + 2605 => x"89", + 2606 => x"70", + 2607 => x"53", + 2608 => x"70", + 2609 => x"51", + 2610 => x"09", + 2611 => x"38", + 2612 => x"38", + 2613 => x"77", + 2614 => x"70", + 2615 => x"2a", + 2616 => x"07", + 2617 => x"51", + 2618 => x"8f", + 2619 => x"84", + 2620 => x"83", + 2621 => x"94", + 2622 => x"74", + 2623 => x"38", + 2624 => x"0c", + 2625 => x"86", + 2626 => x"b8", + 2627 => x"91", + 2628 => x"8c", + 2629 => x"fa", + 2630 => x"56", + 2631 => x"17", + 2632 => x"b0", + 2633 => x"52", + 2634 => x"e0", + 2635 => x"91", + 2636 => x"81", + 2637 => x"b2", + 2638 => x"b4", + 2639 => x"88", + 2640 => x"ff", + 2641 => x"55", + 2642 => x"d5", + 2643 => x"06", + 2644 => x"80", + 2645 => x"33", + 2646 => x"81", + 2647 => x"81", + 2648 => x"81", + 2649 => x"eb", + 2650 => x"70", + 2651 => x"07", + 2652 => x"73", + 2653 => x"81", + 2654 => x"81", + 2655 => x"83", + 2656 => x"c4", + 2657 => x"16", + 2658 => x"3f", + 2659 => x"08", + 2660 => x"88", + 2661 => x"9d", + 2662 => x"91", + 2663 => x"81", + 2664 => x"e0", + 2665 => x"ca", + 2666 => x"91", + 2667 => x"80", + 2668 => x"82", + 2669 => x"ca", + 2670 => x"3d", + 2671 => x"3d", + 2672 => x"84", + 2673 => x"05", + 2674 => x"80", + 2675 => x"51", + 2676 => x"91", + 2677 => x"58", + 2678 => x"0b", + 2679 => x"08", + 2680 => x"38", + 2681 => x"08", + 2682 => x"ca", + 2683 => x"08", + 2684 => x"56", + 2685 => x"86", + 2686 => x"75", + 2687 => x"fe", + 2688 => x"54", + 2689 => x"2e", + 2690 => x"14", + 2691 => x"ca", + 2692 => x"88", + 2693 => x"06", + 2694 => x"54", + 2695 => x"38", + 2696 => x"86", + 2697 => x"82", + 2698 => x"06", + 2699 => x"56", + 2700 => x"38", + 2701 => x"80", + 2702 => x"81", + 2703 => x"52", + 2704 => x"51", + 2705 => x"91", + 2706 => x"81", + 2707 => x"81", + 2708 => x"83", + 2709 => x"87", + 2710 => x"2e", + 2711 => x"82", + 2712 => x"06", + 2713 => x"56", + 2714 => x"38", + 2715 => x"74", + 2716 => x"a3", + 2717 => x"88", + 2718 => x"06", + 2719 => x"2e", + 2720 => x"80", + 2721 => x"3d", + 2722 => x"83", + 2723 => x"15", + 2724 => x"53", + 2725 => x"8d", + 2726 => x"15", + 2727 => x"3f", + 2728 => x"08", + 2729 => x"70", + 2730 => x"0c", + 2731 => x"16", + 2732 => x"80", + 2733 => x"80", + 2734 => x"54", + 2735 => x"84", + 2736 => x"5b", + 2737 => x"80", + 2738 => x"7a", + 2739 => x"fc", + 2740 => x"ca", + 2741 => x"ff", + 2742 => x"77", + 2743 => x"81", + 2744 => x"76", + 2745 => x"81", + 2746 => x"2e", + 2747 => x"8d", + 2748 => x"26", + 2749 => x"bf", + 2750 => x"f4", + 2751 => x"88", + 2752 => x"ff", + 2753 => x"84", + 2754 => x"81", + 2755 => x"38", + 2756 => x"51", + 2757 => x"91", + 2758 => x"83", + 2759 => x"58", + 2760 => x"80", + 2761 => x"db", + 2762 => x"ca", + 2763 => x"77", + 2764 => x"80", + 2765 => x"82", + 2766 => x"c4", + 2767 => x"11", + 2768 => x"06", + 2769 => x"8d", + 2770 => x"26", + 2771 => x"74", + 2772 => x"78", + 2773 => x"c1", + 2774 => x"59", + 2775 => x"15", + 2776 => x"2e", + 2777 => x"13", + 2778 => x"72", + 2779 => x"38", + 2780 => x"eb", + 2781 => x"14", + 2782 => x"3f", + 2783 => x"08", + 2784 => x"88", + 2785 => x"23", + 2786 => x"57", + 2787 => x"83", + 2788 => x"c7", + 2789 => x"d8", + 2790 => x"88", + 2791 => x"ff", + 2792 => x"8d", + 2793 => x"14", + 2794 => x"3f", + 2795 => x"08", + 2796 => x"14", + 2797 => x"3f", + 2798 => x"08", + 2799 => x"06", + 2800 => x"72", + 2801 => x"97", + 2802 => x"22", + 2803 => x"84", + 2804 => x"5a", + 2805 => x"83", + 2806 => x"14", + 2807 => x"79", + 2808 => x"b3", + 2809 => x"ca", + 2810 => x"91", + 2811 => x"80", + 2812 => x"38", + 2813 => x"08", + 2814 => x"ff", + 2815 => x"38", + 2816 => x"83", + 2817 => x"83", + 2818 => x"74", + 2819 => x"85", + 2820 => x"89", + 2821 => x"76", + 2822 => x"c3", + 2823 => x"70", + 2824 => x"7b", + 2825 => x"73", + 2826 => x"17", + 2827 => x"ac", + 2828 => x"55", + 2829 => x"09", + 2830 => x"38", + 2831 => x"51", + 2832 => x"91", + 2833 => x"83", + 2834 => x"53", + 2835 => x"82", + 2836 => x"82", + 2837 => x"e0", + 2838 => x"ab", + 2839 => x"88", + 2840 => x"0c", + 2841 => x"53", + 2842 => x"56", + 2843 => x"81", + 2844 => x"13", + 2845 => x"74", + 2846 => x"82", + 2847 => x"74", + 2848 => x"81", + 2849 => x"06", + 2850 => x"83", + 2851 => x"2a", + 2852 => x"72", + 2853 => x"26", + 2854 => x"ff", + 2855 => x"0c", + 2856 => x"15", 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x"09", + 2916 => x"38", + 2917 => x"51", + 2918 => x"91", + 2919 => x"81", + 2920 => x"88", + 2921 => x"08", + 2922 => x"39", + 2923 => x"73", + 2924 => x"74", + 2925 => x"0c", + 2926 => x"04", + 2927 => x"02", + 2928 => x"7a", + 2929 => x"fc", + 2930 => x"f4", + 2931 => x"54", + 2932 => x"ca", + 2933 => x"bc", + 2934 => x"88", + 2935 => x"91", + 2936 => x"70", + 2937 => x"73", + 2938 => x"38", + 2939 => x"78", + 2940 => x"2e", + 2941 => x"74", + 2942 => x"0c", + 2943 => x"80", + 2944 => x"80", + 2945 => x"70", + 2946 => x"51", + 2947 => x"91", + 2948 => x"54", + 2949 => x"88", + 2950 => x"0d", + 2951 => x"0d", + 2952 => x"05", + 2953 => x"33", + 2954 => x"54", + 2955 => x"84", + 2956 => x"bf", + 2957 => x"98", + 2958 => x"53", + 2959 => x"05", + 2960 => x"fa", + 2961 => x"88", + 2962 => x"ca", + 2963 => x"a4", + 2964 => x"68", + 2965 => x"70", + 2966 => x"c6", + 2967 => x"88", + 2968 => x"ca", + 2969 => x"38", + 2970 => x"05", + 2971 => x"2b", + 2972 => x"80", + 2973 => x"86", + 2974 => x"06", + 2975 => x"2e", + 2976 => x"74", + 2977 => x"38", + 2978 => x"09", + 2979 => x"38", + 2980 => x"f8", + 2981 => x"88", + 2982 => x"39", + 2983 => x"33", + 2984 => x"73", + 2985 => x"77", + 2986 => x"81", + 2987 => x"73", + 2988 => x"38", + 2989 => x"bc", + 2990 => x"07", + 2991 => x"b4", + 2992 => x"2a", + 2993 => x"51", + 2994 => x"2e", + 2995 => x"62", + 2996 => x"e8", + 2997 => x"ca", + 2998 => x"82", + 2999 => x"52", + 3000 => x"51", + 3001 => x"62", + 3002 => x"8b", + 3003 => x"53", + 3004 => x"51", + 3005 => x"80", + 3006 => x"05", + 3007 => x"3f", + 3008 => x"0b", + 3009 => x"75", + 3010 => x"f1", + 3011 => x"11", + 3012 => x"80", + 3013 => x"97", + 3014 => x"51", + 3015 => x"91", + 3016 => x"55", + 3017 => x"08", + 3018 => x"b7", + 3019 => x"c4", + 3020 => x"05", + 3021 => x"2a", + 3022 => x"51", + 3023 => x"80", + 3024 => x"84", + 3025 => x"39", + 3026 => x"70", + 3027 => x"54", + 3028 => x"a9", + 3029 => x"06", + 3030 => x"2e", + 3031 => x"55", + 3032 => x"73", + 3033 => x"d6", + 3034 => x"ca", + 3035 => x"ff", + 3036 => x"0c", + 3037 => x"ca", + 3038 => x"f8", + 3039 => x"2a", + 3040 => x"51", + 3041 => x"2e", + 3042 => x"80", + 3043 => x"7a", + 3044 => x"a0", + 3045 => x"a4", + 3046 => x"53", + 3047 => x"e6", + 3048 => x"ca", + 3049 => x"ca", + 3050 => x"1b", + 3051 => x"05", + 3052 => x"d3", + 3053 => x"88", + 3054 => x"88", + 3055 => x"0c", + 3056 => x"56", + 3057 => x"84", + 3058 => x"90", + 3059 => x"0b", + 3060 => x"80", + 3061 => x"0c", + 3062 => x"1a", + 3063 => x"2a", + 3064 => x"51", + 3065 => x"2e", + 3066 => x"91", + 3067 => x"80", + 3068 => x"38", + 3069 => x"08", + 3070 => x"8a", + 3071 => x"89", + 3072 => x"59", + 3073 => x"76", + 3074 => x"d7", + 3075 => x"ca", + 3076 => x"91", + 3077 => x"81", + 3078 => x"82", + 3079 => x"88", + 3080 => x"09", + 3081 => x"38", + 3082 => x"78", + 3083 => x"30", + 3084 => x"80", + 3085 => x"77", + 3086 => x"38", + 3087 => x"06", + 3088 => x"c3", + 3089 => x"1a", + 3090 => x"38", + 3091 => x"06", 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x"08", + 3151 => x"83", + 3152 => x"88", + 3153 => x"89", + 3154 => x"77", + 3155 => x"d6", + 3156 => x"7f", + 3157 => x"58", + 3158 => x"75", + 3159 => x"75", + 3160 => x"77", + 3161 => x"7c", + 3162 => x"33", + 3163 => x"3f", + 3164 => x"08", + 3165 => x"7e", + 3166 => x"56", + 3167 => x"2e", + 3168 => x"16", + 3169 => x"55", + 3170 => x"94", + 3171 => x"53", + 3172 => x"b0", + 3173 => x"31", + 3174 => x"05", + 3175 => x"3f", + 3176 => x"56", + 3177 => x"9c", + 3178 => x"19", + 3179 => x"06", + 3180 => x"31", + 3181 => x"76", + 3182 => x"7b", + 3183 => x"08", + 3184 => x"d1", + 3185 => x"ca", + 3186 => x"81", + 3187 => x"94", + 3188 => x"ff", + 3189 => x"05", + 3190 => x"cf", + 3191 => x"76", + 3192 => x"17", + 3193 => x"1e", + 3194 => x"18", + 3195 => x"5e", + 3196 => x"39", + 3197 => x"91", + 3198 => x"90", + 3199 => x"f2", + 3200 => x"63", + 3201 => x"40", + 3202 => x"7e", + 3203 => x"fc", + 3204 => x"51", + 3205 => x"91", + 3206 => x"55", + 3207 => x"08", + 3208 => x"18", + 3209 => x"80", + 3210 => x"74", + 3211 => x"39", + 3212 => x"70", + 3213 => x"81", + 3214 => x"56", + 3215 => x"80", + 3216 => x"38", + 3217 => x"0b", + 3218 => x"82", + 3219 => x"39", + 3220 => x"19", + 3221 => x"83", + 3222 => x"18", + 3223 => x"56", + 3224 => x"27", + 3225 => x"09", + 3226 => x"2e", + 3227 => x"94", + 3228 => x"83", + 3229 => x"56", + 3230 => x"38", + 3231 => x"22", + 3232 => x"89", + 3233 => x"55", + 3234 => x"75", + 3235 => x"18", + 3236 => x"9c", + 3237 => x"85", + 3238 => x"08", + 3239 => x"d7", + 3240 => x"ca", + 3241 => x"91", + 3242 => x"80", + 3243 => x"38", + 3244 => x"ff", + 3245 => x"ff", + 3246 => x"38", + 3247 => x"0c", + 3248 => x"85", + 3249 => x"19", + 3250 => x"b0", + 3251 => x"19", + 3252 => x"81", + 3253 => x"74", + 3254 => x"3f", + 3255 => x"08", + 3256 => x"98", + 3257 => x"7e", + 3258 => x"3f", + 3259 => x"08", + 3260 => x"d2", + 3261 => x"88", + 3262 => x"89", + 3263 => x"78", + 3264 => x"d5", + 3265 => x"7f", + 3266 => x"58", + 3267 => x"75", + 3268 => x"75", + 3269 => x"78", + 3270 => x"7c", + 3271 => x"33", + 3272 => x"3f", + 3273 => x"08", + 3274 => x"7e", + 3275 => x"78", + 3276 => x"74", + 3277 => x"38", + 3278 => x"b0", + 3279 => x"31", + 3280 => x"05", + 3281 => x"51", + 3282 => x"7e", + 3283 => x"83", + 3284 => x"89", + 3285 => x"db", + 3286 => x"08", + 3287 => x"26", + 3288 => x"51", + 3289 => x"91", + 3290 => x"fd", + 3291 => x"77", + 3292 => x"55", + 3293 => x"0c", + 3294 => x"83", + 3295 => x"80", + 3296 => x"55", + 3297 => x"83", + 3298 => x"9c", + 3299 => x"7e", + 3300 => x"3f", + 3301 => x"08", + 3302 => x"75", + 3303 => x"94", + 3304 => x"ff", + 3305 => x"05", + 3306 => x"3f", + 3307 => x"0b", + 3308 => x"7b", + 3309 => x"08", + 3310 => x"76", + 3311 => x"08", + 3312 => x"1c", + 3313 => x"08", + 3314 => x"5c", + 3315 => x"83", + 3316 => x"74", + 3317 => x"fd", + 3318 => x"18", + 3319 => x"07", + 3320 => x"19", + 3321 => x"75", + 3322 => x"0c", + 3323 => x"04", + 3324 => x"7a", + 3325 => x"05", + 3326 => x"56", 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x"ca", + 3386 => x"3d", + 3387 => x"3d", + 3388 => x"93", + 3389 => x"52", + 3390 => x"e9", + 3391 => x"ca", + 3392 => x"91", + 3393 => x"80", + 3394 => x"58", + 3395 => x"3d", + 3396 => x"e0", + 3397 => x"ca", + 3398 => x"91", + 3399 => x"bc", + 3400 => x"c7", + 3401 => x"98", + 3402 => x"73", + 3403 => x"38", + 3404 => x"12", + 3405 => x"39", + 3406 => x"33", + 3407 => x"70", + 3408 => x"55", + 3409 => x"2e", + 3410 => x"7f", + 3411 => x"54", + 3412 => x"91", + 3413 => x"94", + 3414 => x"39", + 3415 => x"08", + 3416 => x"81", + 3417 => x"85", + 3418 => x"ca", + 3419 => x"3d", + 3420 => x"3d", + 3421 => x"5b", + 3422 => x"34", + 3423 => x"3d", + 3424 => x"52", + 3425 => x"e8", + 3426 => x"ca", + 3427 => x"91", + 3428 => x"82", + 3429 => x"43", + 3430 => x"11", + 3431 => x"58", + 3432 => x"80", + 3433 => x"38", + 3434 => x"3d", + 3435 => x"d5", + 3436 => x"ca", + 3437 => x"91", + 3438 => x"82", + 3439 => x"52", + 3440 => x"c8", + 3441 => x"88", + 3442 => x"ca", + 3443 => x"c1", + 3444 => x"7b", + 3445 => x"3f", + 3446 => x"08", + 3447 => x"74", + 3448 => x"3f", + 3449 => x"08", + 3450 => x"88", + 3451 => x"38", + 3452 => x"51", + 3453 => x"91", + 3454 => x"57", + 3455 => x"08", + 3456 => x"52", + 3457 => x"f2", + 3458 => x"ca", + 3459 => x"a6", + 3460 => x"74", + 3461 => x"3f", + 3462 => x"08", + 3463 => x"88", + 3464 => x"cc", + 3465 => x"2e", + 3466 => x"86", + 3467 => x"81", + 3468 => x"81", + 3469 => x"3d", + 3470 => x"52", + 3471 => x"c9", + 3472 => x"3d", + 3473 => x"11", + 3474 => x"5a", + 3475 => x"2e", + 3476 => x"b9", + 3477 => x"16", + 3478 => x"33", + 3479 => x"73", + 3480 => x"16", + 3481 => x"26", + 3482 => x"75", + 3483 => x"38", + 3484 => x"05", + 3485 => x"6f", + 3486 => x"ff", + 3487 => x"55", + 3488 => x"74", + 3489 => x"38", + 3490 => x"11", + 3491 => x"74", + 3492 => x"39", + 3493 => x"09", + 3494 => x"38", + 3495 => x"11", + 3496 => x"74", + 3497 => x"91", + 3498 => x"70", + 3499 => x"b9", + 3500 => x"08", + 3501 => x"5c", + 3502 => x"73", + 3503 => x"38", + 3504 => x"1a", + 3505 => x"55", + 3506 => x"38", + 3507 => x"73", + 3508 => x"38", + 3509 => x"76", + 3510 => x"74", + 3511 => x"33", + 3512 => x"05", + 3513 => x"15", + 3514 => x"ba", + 3515 => x"05", + 3516 => x"ff", + 3517 => x"06", + 3518 => x"57", + 3519 => x"18", + 3520 => x"54", + 3521 => x"70", + 3522 => x"34", + 3523 => x"ee", + 3524 => x"34", + 3525 => x"88", + 3526 => x"0d", + 3527 => x"0d", + 3528 => x"3d", + 3529 => x"71", + 3530 => x"ec", + 3531 => x"ca", + 3532 => x"91", + 3533 => x"82", + 3534 => x"15", + 3535 => x"82", + 3536 => x"15", + 3537 => x"76", + 3538 => x"90", + 3539 => x"81", + 3540 => x"06", + 3541 => x"72", + 3542 => x"56", + 3543 => x"54", + 3544 => x"17", + 3545 => x"78", + 3546 => x"38", + 3547 => x"22", + 3548 => x"59", + 3549 => x"78", + 3550 => x"76", + 3551 => x"51", + 3552 => x"3f", + 3553 => x"08", + 3554 => x"54", + 3555 => x"53", + 3556 => x"3f", + 3557 => x"08", + 3558 => x"38", + 3559 => x"75", + 3560 => x"18", + 3561 => x"31", + 3562 => x"57", + 3563 => x"b1", + 3564 => x"08", + 3565 => x"38", + 3566 => x"51", + 3567 => x"91", + 3568 => x"54", + 3569 => x"08", + 3570 => x"9a", + 3571 => x"88", + 3572 => x"81", + 3573 => x"ca", + 3574 => x"16", + 3575 => x"16", + 3576 => x"2e", + 3577 => x"76", + 3578 => x"dc", + 3579 => x"31", + 3580 => x"18", + 3581 => x"90", + 3582 => x"81", + 3583 => x"06", + 3584 => x"56", + 3585 => x"9a", + 3586 => x"74", + 3587 => x"3f", + 3588 => x"08", + 3589 => x"88", + 3590 => x"91", + 3591 => x"56", + 3592 => x"52", + 3593 => x"84", + 3594 => x"88", + 3595 => x"ff", + 3596 => x"81", + 3597 => x"38", + 3598 => x"98", + 3599 => x"a6", + 3600 => x"16", + 3601 => x"39", + 3602 => x"16", + 3603 => x"75", + 3604 => x"53", + 3605 => x"aa", + 3606 => x"79", + 3607 => x"3f", + 3608 => x"08", + 3609 => x"0b", + 3610 => x"82", + 3611 => x"39", + 3612 => x"16", + 3613 => x"bb", + 3614 => x"2a", + 3615 => x"08", + 3616 => x"15", + 3617 => x"15", + 3618 => x"90", + 3619 => x"16", + 3620 => x"33", + 3621 => x"53", + 3622 => x"34", + 3623 => x"06", + 3624 => x"2e", + 3625 => x"9c", + 3626 => x"85", + 3627 => x"16", + 3628 => x"72", + 3629 => x"0c", + 3630 => x"04", + 3631 => x"79", + 3632 => x"75", + 3633 => x"8a", + 3634 => x"89", + 3635 => x"52", + 3636 => x"05", + 3637 => x"3f", + 3638 => x"08", + 3639 => x"88", + 3640 => x"38", + 3641 => x"7a", + 3642 => x"d8", + 3643 => x"ca", + 3644 => x"91", + 3645 => x"80", + 3646 => x"16", + 3647 => x"2b", + 3648 => x"74", + 3649 => x"86", + 3650 => x"84", + 3651 => x"06", + 3652 => x"73", + 3653 => x"38", + 3654 => x"52", + 3655 => x"da", + 3656 => x"88", + 3657 => x"0c", + 3658 => x"14", + 3659 => x"23", + 3660 => x"51", + 3661 => x"91", + 3662 => x"55", + 3663 => x"09", + 3664 => x"38", + 3665 => x"39", + 3666 => x"84", + 3667 => x"0c", + 3668 => x"91", + 3669 => x"89", + 3670 => x"fc", + 3671 => x"87", + 3672 => x"53", + 3673 => x"e7", + 3674 => x"ca", + 3675 => x"38", + 3676 => x"08", + 3677 => x"3d", + 3678 => x"3d", + 3679 => x"89", + 3680 => x"54", + 3681 => x"54", + 3682 => x"91", + 3683 => x"53", + 3684 => x"08", + 3685 => x"74", + 3686 => x"ca", + 3687 => x"73", + 3688 => x"3f", + 3689 => x"08", + 3690 => x"39", + 3691 => x"08", + 3692 => x"d3", + 3693 => x"ca", + 3694 => x"91", + 3695 => x"84", + 3696 => x"06", + 3697 => x"53", + 3698 => x"ca", + 3699 => x"38", + 3700 => x"51", + 3701 => x"72", + 3702 => x"cf", + 3703 => x"ca", + 3704 => x"32", + 3705 => x"72", + 3706 => x"70", + 3707 => x"08", + 3708 => x"54", + 3709 => x"ca", + 3710 => x"3d", + 3711 => x"3d", + 3712 => x"80", + 3713 => x"70", + 3714 => x"52", + 3715 => x"3f", + 3716 => x"08", + 3717 => x"88", + 3718 => x"64", + 3719 => x"d6", + 3720 => x"ca", + 3721 => x"91", + 3722 => x"a0", + 3723 => x"cb", + 3724 => x"98", + 3725 => x"73", + 3726 => x"38", + 3727 => x"39", + 3728 => x"88", + 3729 => x"75", + 3730 => x"3f", + 3731 => x"88", + 3732 => x"0d", + 3733 => x"0d", + 3734 => x"5c", + 3735 => x"3d", + 3736 => x"93", + 3737 => x"d6", + 3738 => x"88", + 3739 => x"ca", + 3740 => x"80", + 3741 => x"0c", + 3742 => x"11", + 3743 => x"90", + 3744 => x"56", + 3745 => x"74", + 3746 => x"75", + 3747 => x"e4", + 3748 => x"81", + 3749 => x"5b", + 3750 => x"91", + 3751 => x"75", + 3752 => x"73", + 3753 => x"81", + 3754 => x"82", + 3755 => x"76", + 3756 => x"f0", + 3757 => x"f4", + 3758 => x"88", + 3759 => x"d1", + 3760 => x"88", + 3761 => x"ce", + 3762 => x"88", + 3763 => x"91", + 3764 => x"07", + 3765 => x"05", + 3766 => x"53", + 3767 => x"98", + 3768 => x"26", + 3769 => x"f9", + 3770 => x"08", + 3771 => x"08", + 3772 => x"98", + 3773 => x"81", + 3774 => x"58", + 3775 => x"3f", + 3776 => x"08", + 3777 => x"88", + 3778 => x"38", + 3779 => x"77", + 3780 => x"5d", + 3781 => x"74", + 3782 => x"81", + 3783 => x"b4", + 3784 => x"bb", + 3785 => x"ca", + 3786 => x"ff", + 3787 => x"30", + 3788 => x"1b", + 3789 => x"5b", + 3790 => x"39", + 3791 => x"ff", + 3792 => x"91", + 3793 => x"f0", + 3794 => x"30", + 3795 => x"1b", + 3796 => x"5b", + 3797 => x"83", + 3798 => x"58", + 3799 => x"92", + 3800 => x"0c", + 3801 => x"12", + 3802 => x"33", + 3803 => x"54", + 3804 => x"34", + 3805 => x"88", + 3806 => x"0d", + 3807 => x"0d", + 3808 => x"fc", + 3809 => x"52", + 3810 => x"3f", + 3811 => x"08", + 3812 => x"88", + 3813 => x"38", + 3814 => x"56", + 3815 => x"38", + 3816 => x"70", + 3817 => x"81", + 3818 => x"55", + 3819 => x"80", + 3820 => x"38", + 3821 => x"54", + 3822 => x"08", + 3823 => x"38", + 3824 => x"91", + 3825 => x"53", + 3826 => x"52", + 3827 => x"8c", + 3828 => x"88", + 3829 => x"19", + 3830 => x"c9", + 3831 => x"08", + 3832 => x"ff", + 3833 => x"91", + 3834 => x"ff", + 3835 => x"06", + 3836 => x"56", + 3837 => x"08", + 3838 => x"81", + 3839 => x"82", + 3840 => x"75", + 3841 => x"54", + 3842 => x"08", + 3843 => x"27", + 3844 => x"17", + 3845 => x"ca", + 3846 => x"76", + 3847 => x"3f", + 3848 => x"08", + 3849 => x"08", + 3850 => x"90", + 3851 => x"c0", + 3852 => x"90", + 3853 => x"80", + 3854 => x"75", + 3855 => x"75", + 3856 => x"ca", + 3857 => x"3d", + 3858 => x"3d", + 3859 => x"a0", + 3860 => x"05", + 3861 => x"51", + 3862 => x"91", + 3863 => x"55", + 3864 => x"08", + 3865 => x"78", + 3866 => x"08", + 3867 => x"70", + 3868 => x"ae", + 3869 => x"88", + 3870 => x"ca", + 3871 => x"db", + 3872 => x"fb", + 3873 => x"85", + 3874 => x"06", + 3875 => x"86", + 3876 => x"c7", + 3877 => x"2b", + 3878 => x"24", + 3879 => x"02", + 3880 => x"33", + 3881 => x"58", + 3882 => x"76", + 3883 => x"6b", + 3884 => x"cc", + 3885 => x"ca", + 3886 => x"84", + 3887 => x"06", + 3888 => x"73", + 3889 => x"d4", + 3890 => x"91", + 3891 => x"94", + 3892 => x"81", + 3893 => x"5a", + 3894 => x"08", + 3895 => x"8a", + 3896 => x"54", + 3897 => x"91", + 3898 => x"55", + 3899 => x"08", + 3900 => x"91", + 3901 => x"52", + 3902 => x"e5", + 3903 => x"88", + 3904 => x"ca", + 3905 => x"38", + 3906 => x"cf", + 3907 => x"88", + 3908 => x"88", + 3909 => x"88", + 3910 => x"38", + 3911 => x"c2", + 3912 => x"88", + 3913 => x"88", + 3914 => x"91", + 3915 => x"07", + 3916 => x"55", + 3917 => x"2e", + 3918 => x"80", + 3919 => x"80", + 3920 => x"77", + 3921 => x"3f", + 3922 => x"08", + 3923 => x"38", + 3924 => x"ba", + 3925 => x"ca", + 3926 => x"74", + 3927 => x"0c", + 3928 => x"04", + 3929 => x"82", + 3930 => x"c0", + 3931 => x"3d", + 3932 => x"3f", + 3933 => x"08", + 3934 => x"88", + 3935 => x"38", + 3936 => x"52", + 3937 => x"52", + 3938 => x"3f", + 3939 => x"08", + 3940 => x"88", + 3941 => x"88", + 3942 => x"39", + 3943 => x"08", + 3944 => x"81", + 3945 => x"38", + 3946 => x"05", + 3947 => x"2a", + 3948 => x"55", + 3949 => x"81", + 3950 => x"5a", + 3951 => x"3d", + 3952 => x"c1", + 3953 => x"ca", + 3954 => x"55", + 3955 => x"88", + 3956 => x"87", + 3957 => x"88", + 3958 => x"09", + 3959 => x"38", + 3960 => x"ca", + 3961 => x"2e", + 3962 => x"86", + 3963 => x"81", + 3964 => x"81", + 3965 => x"ca", + 3966 => x"78", + 3967 => x"3f", + 3968 => x"08", + 3969 => x"88", + 3970 => x"38", + 3971 => x"52", + 3972 => x"ff", + 3973 => x"78", + 3974 => x"b4", + 3975 => x"54", + 3976 => x"15", + 3977 => x"b2", + 3978 => x"ca", + 3979 => x"b6", + 3980 => x"53", + 3981 => x"53", + 3982 => x"3f", + 3983 => x"b4", + 3984 => x"d4", + 3985 => x"b6", + 3986 => x"54", + 3987 => x"d5", + 3988 => x"53", + 3989 => x"11", + 3990 => x"d7", + 3991 => x"81", + 3992 => x"34", + 3993 => x"a4", + 3994 => x"88", + 3995 => x"ca", + 3996 => x"38", + 3997 => x"0a", + 3998 => x"05", + 3999 => x"d0", + 4000 => x"64", + 4001 => x"c9", + 4002 => x"54", + 4003 => x"15", + 4004 => x"81", + 4005 => x"34", + 4006 => x"b8", + 4007 => x"ca", + 4008 => x"8b", + 4009 => x"75", + 4010 => x"ff", + 4011 => x"73", + 4012 => x"0c", + 4013 => x"04", + 4014 => x"a9", + 4015 => x"51", + 4016 => x"82", + 4017 => x"ff", + 4018 => x"a9", + 4019 => x"ee", + 4020 => x"88", + 4021 => x"ca", + 4022 => x"d3", + 4023 => x"a9", + 4024 => x"9d", + 4025 => x"58", + 4026 => x"91", + 4027 => x"55", + 4028 => x"08", + 4029 => x"02", + 4030 => x"33", + 4031 => x"54", + 4032 => x"82", + 4033 => x"53", + 4034 => x"52", + 4035 => x"88", + 4036 => x"b4", + 4037 => x"53", + 4038 => x"3d", + 4039 => x"ff", + 4040 => x"aa", + 4041 => x"73", + 4042 => x"3f", + 4043 => x"08", + 4044 => x"88", + 4045 => x"63", + 4046 => x"81", + 4047 => x"65", + 4048 => x"2e", + 4049 => x"55", + 4050 => x"91", + 4051 => x"84", + 4052 => x"06", + 4053 => x"73", + 4054 => x"3f", + 4055 => x"08", + 4056 => x"88", + 4057 => x"38", + 4058 => x"53", + 4059 => x"95", + 4060 => x"16", + 4061 => x"87", + 4062 => x"05", + 4063 => x"34", + 4064 => x"70", + 4065 => x"81", + 4066 => x"55", + 4067 => x"74", + 4068 => x"73", + 4069 => x"78", + 4070 => x"83", + 4071 => x"16", + 4072 => x"2a", + 4073 => x"51", + 4074 => x"80", + 4075 => x"38", + 4076 => x"80", + 4077 => x"52", + 4078 => x"be", + 4079 => x"88", + 4080 => x"51", + 4081 => x"3f", + 4082 => x"ca", + 4083 => x"2e", + 4084 => x"91", + 4085 => x"52", + 4086 => x"b5", + 4087 => x"ca", + 4088 => x"80", + 4089 => x"58", + 4090 => x"88", + 4091 => x"38", + 4092 => x"54", + 4093 => x"09", + 4094 => x"38", + 4095 => x"52", + 4096 => x"af", + 4097 => x"81", + 4098 => x"34", + 4099 => x"ca", + 4100 => x"38", + 4101 => x"ca", + 4102 => x"88", + 4103 => x"ca", + 4104 => x"38", + 4105 => x"b5", + 4106 => x"ca", + 4107 => x"74", + 4108 => x"0c", + 4109 => x"04", + 4110 => x"02", + 4111 => x"33", + 4112 => x"80", + 4113 => x"57", + 4114 => x"95", + 4115 => x"52", + 4116 => x"d2", + 4117 => x"ca", + 4118 => x"91", + 4119 => x"80", + 4120 => x"5a", + 4121 => x"3d", + 4122 => x"c9", + 4123 => x"ca", + 4124 => x"91", + 4125 => x"b8", + 4126 => x"cf", + 4127 => x"a0", + 4128 => x"55", + 4129 => x"75", + 4130 => x"71", + 4131 => x"33", + 4132 => x"74", + 4133 => x"57", + 4134 => x"8b", + 4135 => x"54", + 4136 => x"15", + 4137 => x"ff", + 4138 => x"91", + 4139 => x"55", + 4140 => x"88", + 4141 => x"0d", + 4142 => x"0d", + 4143 => x"53", + 4144 => x"05", + 4145 => x"51", + 4146 => x"91", + 4147 => x"55", + 4148 => x"08", + 4149 => x"76", + 4150 => x"93", + 4151 => x"51", + 4152 => x"91", + 4153 => x"55", + 4154 => x"08", + 4155 => x"80", + 4156 => x"81", + 4157 => x"86", + 4158 => x"38", + 4159 => x"86", + 4160 => x"90", + 4161 => x"54", + 4162 => x"ff", + 4163 => x"76", + 4164 => x"83", + 4165 => x"51", + 4166 => x"3f", + 4167 => x"08", + 4168 => x"ca", + 4169 => x"3d", + 4170 => x"3d", + 4171 => x"5c", + 4172 => x"98", + 4173 => x"52", + 4174 => x"d1", + 4175 => x"ca", + 4176 => x"ca", + 4177 => x"70", + 4178 => x"08", + 4179 => x"51", + 4180 => x"80", + 4181 => x"38", + 4182 => x"06", + 4183 => x"80", + 4184 => x"38", + 4185 => x"5f", + 4186 => x"3d", + 4187 => x"ff", + 4188 => x"91", + 4189 => x"57", + 4190 => x"08", + 4191 => x"74", + 4192 => x"c3", + 4193 => x"ca", + 4194 => x"91", + 4195 => x"bf", + 4196 => x"88", + 4197 => x"88", + 4198 => x"59", + 4199 => x"81", + 4200 => x"56", + 4201 => x"33", + 4202 => x"16", + 4203 => x"27", + 4204 => x"56", + 4205 => x"80", + 4206 => x"80", + 4207 => x"ff", + 4208 => x"70", + 4209 => x"56", + 4210 => x"e8", + 4211 => x"76", + 4212 => x"81", + 4213 => x"80", + 4214 => x"57", + 4215 => x"78", + 4216 => x"51", + 4217 => x"2e", + 4218 => x"73", + 4219 => x"38", + 4220 => x"08", + 4221 => x"b1", + 4222 => x"ca", + 4223 => x"91", + 4224 => x"a7", + 4225 => x"33", + 4226 => x"c3", + 4227 => x"2e", + 4228 => x"e4", + 4229 => x"2e", + 4230 => x"56", + 4231 => x"05", + 4232 => x"e3", + 4233 => x"88", + 4234 => x"76", + 4235 => x"0c", + 4236 => x"04", + 4237 => x"82", + 4238 => x"ff", + 4239 => x"9d", + 4240 => x"fa", + 4241 => x"88", + 4242 => x"88", + 4243 => x"91", + 4244 => x"83", + 4245 => x"53", + 4246 => x"3d", + 4247 => x"ff", + 4248 => x"73", + 4249 => x"70", + 4250 => x"52", + 4251 => x"9f", + 4252 => x"bc", + 4253 => x"74", + 4254 => x"6d", + 4255 => x"70", + 4256 => x"af", + 4257 => x"ca", + 4258 => x"2e", + 4259 => x"70", + 4260 => x"57", + 4261 => x"fd", + 4262 => x"88", + 4263 => x"8d", + 4264 => x"2b", + 4265 => x"81", + 4266 => x"86", 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x"08", + 4326 => x"81", + 4327 => x"38", + 4328 => x"74", + 4329 => x"38", + 4330 => x"51", + 4331 => x"3f", + 4332 => x"08", + 4333 => x"88", + 4334 => x"a0", + 4335 => x"88", + 4336 => x"51", + 4337 => x"3f", + 4338 => x"0b", + 4339 => x"8b", + 4340 => x"67", + 4341 => x"a7", + 4342 => x"81", + 4343 => x"34", + 4344 => x"ad", + 4345 => x"ca", + 4346 => x"73", + 4347 => x"ca", + 4348 => x"3d", + 4349 => x"3d", + 4350 => x"02", + 4351 => x"cb", + 4352 => x"3d", + 4353 => x"72", + 4354 => x"5a", + 4355 => x"91", + 4356 => x"58", + 4357 => x"08", + 4358 => x"91", + 4359 => x"77", + 4360 => x"7c", + 4361 => x"38", + 4362 => x"59", + 4363 => x"90", + 4364 => x"81", + 4365 => x"06", + 4366 => x"73", + 4367 => x"54", + 4368 => x"82", + 4369 => x"39", + 4370 => x"8b", + 4371 => x"11", + 4372 => x"2b", + 4373 => x"54", + 4374 => x"ff", + 4375 => x"ff", + 4376 => x"70", + 4377 => x"07", + 4378 => x"ca", + 4379 => x"8c", + 4380 => x"40", + 4381 => x"55", + 4382 => x"88", + 4383 => x"08", + 4384 => x"38", + 4385 => x"77", + 4386 => x"56", + 4387 => x"51", + 4388 => x"3f", + 4389 => x"55", + 4390 => x"08", + 4391 => x"38", + 4392 => x"ca", + 4393 => x"2e", + 4394 => x"91", + 4395 => x"ff", + 4396 => x"38", + 4397 => x"08", + 4398 => x"16", + 4399 => x"2e", + 4400 => x"87", + 4401 => x"74", + 4402 => x"74", + 4403 => x"81", + 4404 => x"38", + 4405 => x"ff", + 4406 => x"2e", + 4407 => x"7b", + 4408 => x"80", + 4409 => x"81", + 4410 => x"81", + 4411 => x"06", + 4412 => x"56", + 4413 => x"52", + 4414 => x"af", + 4415 => x"ca", + 4416 => x"91", + 4417 => x"80", + 4418 => x"81", + 4419 => x"56", + 4420 => x"d3", + 4421 => x"ff", + 4422 => x"7c", + 4423 => x"55", + 4424 => x"b3", + 4425 => x"1b", + 4426 => x"1b", + 4427 => x"33", + 4428 => x"54", + 4429 => x"34", + 4430 => x"fe", + 4431 => x"08", + 4432 => x"74", + 4433 => x"75", + 4434 => x"16", + 4435 => x"33", + 4436 => x"73", + 4437 => x"77", + 4438 => x"ca", + 4439 => x"3d", + 4440 => x"3d", + 4441 => x"02", + 4442 => x"eb", + 4443 => x"3d", + 4444 => x"59", + 4445 => x"8b", + 4446 => x"91", + 4447 => x"24", + 4448 => x"91", + 4449 => x"84", + 4450 => x"a4", + 4451 => x"51", + 4452 => x"2e", + 4453 => x"75", + 4454 => x"88", + 4455 => x"06", + 4456 => x"7e", + 4457 => x"d0", + 4458 => x"88", + 4459 => x"06", + 4460 => x"56", + 4461 => x"74", + 4462 => x"76", + 4463 => x"81", + 4464 => x"8a", + 4465 => x"b2", + 4466 => x"fc", + 4467 => x"52", + 4468 => x"a4", + 4469 => x"ca", + 4470 => x"38", + 4471 => x"80", + 4472 => x"74", + 4473 => x"26", + 4474 => x"15", + 4475 => x"74", + 4476 => x"38", + 4477 => x"80", + 4478 => x"84", + 4479 => x"92", + 4480 => x"80", + 4481 => x"38", + 4482 => x"06", + 4483 => x"2e", + 4484 => x"56", + 4485 => x"78", + 4486 => x"89", + 4487 => x"2b", + 4488 => x"43", + 4489 => x"38", + 4490 => x"30", + 4491 => x"77", + 4492 => x"91", + 4493 => x"c2", + 4494 => x"f8", + 4495 => x"52", + 4496 => x"a4", + 4497 => x"56", + 4498 => x"08", + 4499 => x"77", + 4500 => x"77", + 4501 => x"88", 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x"2e", + 4561 => x"75", + 4562 => x"79", + 4563 => x"fe", + 4564 => x"91", + 4565 => x"10", + 4566 => x"91", + 4567 => x"9f", + 4568 => x"38", + 4569 => x"ca", + 4570 => x"91", + 4571 => x"05", + 4572 => x"2a", + 4573 => x"56", + 4574 => x"17", + 4575 => x"81", + 4576 => x"60", + 4577 => x"65", + 4578 => x"12", + 4579 => x"30", + 4580 => x"74", + 4581 => x"59", + 4582 => x"7d", + 4583 => x"81", + 4584 => x"76", + 4585 => x"41", + 4586 => x"76", + 4587 => x"90", + 4588 => x"62", + 4589 => x"51", + 4590 => x"26", + 4591 => x"75", + 4592 => x"31", + 4593 => x"65", + 4594 => x"fe", + 4595 => x"91", + 4596 => x"58", + 4597 => x"09", + 4598 => x"38", + 4599 => x"08", + 4600 => x"26", + 4601 => x"78", + 4602 => x"79", + 4603 => x"78", + 4604 => x"86", + 4605 => x"82", + 4606 => x"06", + 4607 => x"83", + 4608 => x"91", + 4609 => x"27", + 4610 => x"8f", + 4611 => x"55", + 4612 => x"26", + 4613 => x"59", + 4614 => x"62", + 4615 => x"74", + 4616 => x"38", + 4617 => x"88", + 4618 => x"88", + 4619 => x"26", + 4620 => x"86", + 4621 => x"1a", + 4622 => x"79", + 4623 => x"38", + 4624 => x"80", + 4625 => x"2e", + 4626 => x"83", + 4627 => x"9f", + 4628 => x"8b", + 4629 => x"06", + 4630 => x"74", + 4631 => x"84", + 4632 => x"52", + 4633 => x"a2", + 4634 => x"53", + 4635 => x"52", + 4636 => x"a2", + 4637 => x"80", + 4638 => x"51", + 4639 => x"3f", + 4640 => x"34", + 4641 => x"ff", + 4642 => x"1b", + 4643 => x"a2", + 4644 => x"90", + 4645 => x"83", + 4646 => x"70", + 4647 => x"80", + 4648 => x"55", + 4649 => x"ff", + 4650 => x"66", + 4651 => x"ff", + 4652 => x"38", + 4653 => x"ff", + 4654 => x"1b", + 4655 => x"f2", + 4656 => x"74", + 4657 => x"51", + 4658 => x"3f", + 4659 => x"1c", + 4660 => x"98", + 4661 => x"a0", + 4662 => x"ff", + 4663 => x"51", + 4664 => x"3f", + 4665 => x"1b", + 4666 => x"e4", + 4667 => x"2e", + 4668 => x"80", + 4669 => x"88", + 4670 => x"80", + 4671 => x"ff", + 4672 => x"7c", + 4673 => x"51", + 4674 => x"3f", + 4675 => x"1b", + 4676 => x"bc", + 4677 => x"b0", + 4678 => x"a0", + 4679 => x"52", + 4680 => x"ff", + 4681 => x"ff", + 4682 => x"c0", + 4683 => x"0b", + 4684 => x"34", + 4685 => x"b8", + 4686 => x"c7", + 4687 => x"39", + 4688 => x"0a", + 4689 => x"51", + 4690 => x"3f", + 4691 => x"ff", + 4692 => x"1b", + 4693 => x"da", + 4694 => x"0b", + 4695 => x"a9", + 4696 => x"34", + 4697 => x"b8", + 4698 => x"1b", + 4699 => x"8f", + 4700 => x"d5", + 4701 => x"1b", + 4702 => x"ff", + 4703 => x"81", + 4704 => x"7a", + 4705 => x"ff", + 4706 => x"81", + 4707 => x"88", + 4708 => x"38", + 4709 => x"09", + 4710 => x"ee", + 4711 => x"60", + 4712 => x"7a", + 4713 => x"ff", + 4714 => x"84", + 4715 => x"52", + 4716 => x"9f", + 4717 => x"8b", + 4718 => x"52", + 4719 => x"9f", + 4720 => x"8a", + 4721 => x"52", + 4722 => x"51", + 4723 => x"3f", + 4724 => x"83", + 4725 => x"ff", + 4726 => x"82", + 4727 => x"1b", + 4728 => x"ec", + 4729 => x"d5", + 4730 => x"ff", + 4731 => x"75", + 4732 => x"05", + 4733 => x"7e", + 4734 => x"e5", + 4735 => x"60", + 4736 => x"52", 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x"c2", + 4796 => x"1b", + 4797 => x"34", + 4798 => x"16", + 4799 => x"82", + 4800 => x"83", + 4801 => x"84", + 4802 => x"67", + 4803 => x"fd", + 4804 => x"51", + 4805 => x"3f", + 4806 => x"16", + 4807 => x"88", + 4808 => x"bf", + 4809 => x"86", + 4810 => x"ca", + 4811 => x"16", + 4812 => x"83", + 4813 => x"ff", + 4814 => x"66", + 4815 => x"1b", + 4816 => x"8c", + 4817 => x"77", + 4818 => x"7e", + 4819 => x"91", + 4820 => x"91", + 4821 => x"a2", + 4822 => x"80", + 4823 => x"ff", + 4824 => x"81", + 4825 => x"88", + 4826 => x"89", + 4827 => x"8a", + 4828 => x"86", + 4829 => x"88", + 4830 => x"91", + 4831 => x"99", + 4832 => x"ff", + 4833 => x"52", + 4834 => x"81", + 4835 => x"84", + 4836 => x"9c", + 4837 => x"08", + 4838 => x"d8", + 4839 => x"39", + 4840 => x"51", + 4841 => x"91", + 4842 => x"80", + 4843 => x"bc", + 4844 => x"eb", + 4845 => x"9c", + 4846 => x"39", + 4847 => x"51", + 4848 => x"91", + 4849 => x"80", + 4850 => x"bc", + 4851 => x"cf", + 4852 => x"e8", + 4853 => x"39", + 4854 => x"51", + 4855 => x"91", + 4856 => x"bb", + 4857 => x"b4", + 4858 => x"91", + 4859 => x"af", + 4860 => x"f4", + 4861 => x"91", + 4862 => x"a3", + 4863 => x"a8", + 4864 => x"91", + 4865 => x"97", + 4866 => x"d4", + 4867 => x"91", + 4868 => x"8b", + 4869 => x"84", + 4870 => x"91", + 4871 => x"ff", + 4872 => x"83", + 4873 => x"fb", + 4874 => x"79", + 4875 => x"87", + 4876 => x"38", + 4877 => x"87", + 4878 => x"91", + 4879 => x"52", + 4880 => x"f2", + 4881 => x"ca", + 4882 => x"75", + 4883 => x"98", + 4884 => x"88", + 4885 => x"53", + 4886 => x"bf", + 4887 => x"8d", + 4888 => x"3d", + 4889 => x"3d", + 4890 => x"61", + 4891 => x"80", + 4892 => x"73", + 4893 => x"5f", + 4894 => x"5c", + 4895 => x"52", + 4896 => x"51", + 4897 => x"3f", + 4898 => x"51", + 4899 => x"3f", + 4900 => x"77", + 4901 => x"38", + 4902 => x"89", + 4903 => x"2e", + 4904 => x"c6", + 4905 => x"53", + 4906 => x"8e", + 4907 => x"52", + 4908 => x"51", + 4909 => x"3f", + 4910 => x"bf", + 4911 => x"86", + 4912 => x"15", + 4913 => x"39", + 4914 => x"72", + 4915 => x"38", + 4916 => x"91", + 4917 => x"ff", + 4918 => x"89", + 4919 => x"d8", + 4920 => x"b9", + 4921 => x"55", + 4922 => x"16", + 4923 => x"27", + 4924 => x"33", + 4925 => x"e4", + 4926 => x"85", + 4927 => x"91", + 4928 => x"ff", + 4929 => x"81", + 4930 => x"51", + 4931 => x"3f", + 4932 => x"91", + 4933 => x"ff", + 4934 => x"80", + 4935 => x"27", + 4936 => x"16", + 4937 => x"72", + 4938 => x"53", + 4939 => x"90", + 4940 => x"2e", + 4941 => x"80", + 4942 => x"38", + 4943 => x"39", + 4944 => x"f9", + 4945 => x"15", + 4946 => x"91", + 4947 => x"ff", + 4948 => x"76", + 4949 => x"5a", + 4950 => x"92", + 4951 => x"88", + 4952 => x"70", + 4953 => x"55", + 4954 => x"09", + 4955 => x"38", + 4956 => x"3f", + 4957 => x"08", + 4958 => x"98", + 4959 => x"32", + 4960 => x"72", + 4961 => x"51", + 4962 => x"55", + 4963 => x"8c", + 4964 => x"38", + 4965 => x"09", + 4966 => x"38", + 4967 => x"39", + 4968 => x"72", + 4969 => x"d6", + 4970 => x"72", + 4971 => x"0c", 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x"04", + 5031 => x"88", + 5032 => x"0d", + 5033 => x"0d", + 5034 => x"33", + 5035 => x"53", + 5036 => x"52", + 5037 => x"c9", + 5038 => x"88", + 5039 => x"80", + 5040 => x"c0", + 5041 => x"c0", + 5042 => x"c7", + 5043 => x"91", + 5044 => x"ff", + 5045 => x"74", + 5046 => x"38", + 5047 => x"3f", + 5048 => x"04", + 5049 => x"87", + 5050 => x"08", + 5051 => x"fd", + 5052 => x"fe", + 5053 => x"91", + 5054 => x"fe", + 5055 => x"80", + 5056 => x"fe", + 5057 => x"2a", + 5058 => x"51", + 5059 => x"2e", + 5060 => x"51", + 5061 => x"3f", + 5062 => x"51", + 5063 => x"3f", + 5064 => x"f5", + 5065 => x"82", + 5066 => x"06", + 5067 => x"80", + 5068 => x"81", + 5069 => x"ca", + 5070 => x"f4", + 5071 => x"c2", + 5072 => x"fe", + 5073 => x"72", + 5074 => x"81", + 5075 => x"71", + 5076 => x"38", + 5077 => x"f5", + 5078 => x"c1", + 5079 => x"f7", + 5080 => x"51", + 5081 => x"3f", + 5082 => x"70", + 5083 => x"52", + 5084 => x"95", + 5085 => x"fe", + 5086 => x"91", + 5087 => x"fe", + 5088 => x"80", + 5089 => x"fa", + 5090 => x"2a", + 5091 => x"51", + 5092 => x"2e", + 5093 => x"51", + 5094 => x"3f", + 5095 => x"51", + 5096 => x"3f", + 5097 => x"f4", + 5098 => x"86", + 5099 => x"06", + 5100 => x"80", + 5101 => x"81", + 5102 => x"c6", + 5103 => x"c0", + 5104 => x"be", + 5105 => x"fe", + 5106 => x"72", + 5107 => x"81", + 5108 => x"71", + 5109 => x"38", + 5110 => x"f4", + 5111 => x"c1", + 5112 => x"f6", + 5113 => x"51", + 5114 => x"3f", + 5115 => x"70", + 5116 => x"52", + 5117 => x"95", + 5118 => x"fe", + 5119 => x"91", + 5120 => x"fe", + 5121 => x"80", + 5122 => x"f6", + 5123 => x"a6", + 5124 => x"0d", + 5125 => x"0d", + 5126 => x"70", + 5127 => x"73", + 5128 => x"f0", + 5129 => x"73", + 5130 => x"15", + 5131 => x"e4", + 5132 => x"54", + 5133 => x"70", + 5134 => x"57", + 5135 => x"a0", + 5136 => x"81", + 5137 => x"2e", + 5138 => x"e5", + 5139 => x"ff", + 5140 => x"a0", + 5141 => x"06", + 5142 => x"74", + 5143 => x"56", + 5144 => x"75", + 5145 => x"c7", + 5146 => x"08", + 5147 => x"52", + 5148 => x"fd", + 5149 => x"88", + 5150 => x"84", + 5151 => x"72", + 5152 => x"a3", + 5153 => x"70", + 5154 => x"57", + 5155 => x"27", + 5156 => x"53", + 5157 => x"88", + 5158 => x"0d", + 5159 => x"0d", + 5160 => x"91", + 5161 => x"5e", + 5162 => x"7b", + 5163 => x"c8", + 5164 => x"88", + 5165 => x"06", + 5166 => x"2e", + 5167 => x"a2", + 5168 => x"a8", + 5169 => x"70", + 5170 => x"84", + 5171 => x"53", + 5172 => x"cb", + 5173 => x"b9", + 5174 => x"ca", + 5175 => x"2e", + 5176 => x"c2", + 5177 => x"d7", + 5178 => x"5e", + 5179 => x"e4", + 5180 => x"a9", + 5181 => x"70", + 5182 => x"f8", + 5183 => x"79", + 5184 => x"dc", + 5185 => x"52", + 5186 => x"84", + 5187 => x"3d", + 5188 => x"51", + 5189 => x"91", + 5190 => x"90", + 5191 => x"2c", + 5192 => x"80", + 5193 => x"da", + 5194 => x"c2", + 5195 => x"38", + 5196 => x"83", + 5197 => x"b0", + 5198 => x"78", + 5199 => x"a1", + 5200 => x"24", + 5201 => x"80", + 5202 => x"38", + 5203 => x"81", + 5204 => x"f1", + 5205 => x"2e", + 5206 => x"78", + 5207 => x"9c", + 5208 => x"39", + 5209 => x"85", + 5210 => x"bf", + 5211 => x"78", + 5212 => x"98", + 5213 => x"2e", + 5214 => x"8e", + 5215 => x"80", + 5216 => x"d9", + 5217 => x"c1", + 5218 => x"38", + 5219 => x"78", + 5220 => x"8d", + 5221 => x"80", + 5222 => x"38", + 5223 => x"2e", + 5224 => x"78", + 5225 => x"92", + 5226 => x"c3", + 5227 => x"38", + 5228 => x"2e", + 5229 => x"8e", + 5230 => x"80", + 5231 => x"c0", + 5232 => x"d5", + 5233 => x"38", + 5234 => x"78", + 5235 => x"8d", + 5236 => x"81", + 5237 => x"38", + 5238 => x"2e", + 5239 => x"78", + 5240 => x"8d", + 5241 => x"dd", + 5242 => x"85", + 5243 => x"38", + 5244 => x"2e", + 5245 => x"8d", + 5246 => x"3d", + 5247 => x"53", + 5248 => x"51", + 5249 => x"3f", + 5250 => x"08", + 5251 => x"c2", + 5252 => x"ab", + 5253 => x"fe", + 5254 => x"fe", + 5255 => x"ff", + 5256 => x"91", + 5257 => x"80", + 5258 => x"81", + 5259 => x"38", + 5260 => x"80", + 5261 => x"52", + 5262 => x"05", + 5263 => x"87", + 5264 => x"ca", + 5265 => x"ff", + 5266 => x"8e", + 5267 => x"f8", + 5268 => x"c9", + 5269 => x"fd", + 5270 => x"c3", + 5271 => x"b6", + 5272 => x"fe", + 5273 => x"fe", + 5274 => x"ff", + 5275 => x"91", + 5276 => x"80", + 5277 => x"38", + 5278 => x"52", + 5279 => x"05", + 5280 => x"8b", + 5281 => x"ca", + 5282 => x"91", + 5283 => x"8c", + 5284 => x"3d", + 5285 => x"53", + 5286 => x"51", + 5287 => x"3f", + 5288 => x"08", + 5289 => x"38", + 5290 => x"fc", + 5291 => x"3d", + 5292 => x"53", + 5293 => x"51", + 5294 => x"3f", + 5295 => x"08", + 5296 => x"ca", + 5297 => x"63", + 5298 => x"a8", + 5299 => x"ff", + 5300 => x"02", + 5301 => x"33", + 5302 => x"63", + 5303 => x"91", + 5304 => x"51", + 5305 => x"3f", + 5306 => x"08", + 5307 => x"91", + 5308 => x"fe", + 5309 => x"81", + 5310 => x"39", + 5311 => x"f8", + 5312 => x"ea", + 5313 => x"ca", + 5314 => x"3d", + 5315 => x"52", + 5316 => x"81", + 5317 => x"91", + 5318 => x"52", + 5319 => x"94", + 5320 => x"39", + 5321 => x"f8", + 5322 => x"ea", + 5323 => x"ca", + 5324 => x"3d", + 5325 => x"52", + 5326 => x"d9", + 5327 => x"88", + 5328 => x"fe", + 5329 => x"5a", + 5330 => x"3f", + 5331 => x"08", + 5332 => x"f8", + 5333 => x"fe", + 5334 => x"91", + 5335 => x"91", + 5336 => x"80", + 5337 => x"91", + 5338 => x"81", + 5339 => x"78", + 5340 => x"7a", + 5341 => x"3f", + 5342 => x"08", + 5343 => x"ed", + 5344 => x"88", + 5345 => x"fb", + 5346 => x"39", + 5347 => x"f4", + 5348 => x"f8", + 5349 => x"80", + 5350 => x"ca", + 5351 => x"2e", + 5352 => x"b7", + 5353 => x"11", + 5354 => x"05", + 5355 => x"c6", + 5356 => x"88", + 5357 => x"fa", + 5358 => x"3d", + 5359 => x"53", + 5360 => x"51", + 5361 => x"3f", + 5362 => x"08", + 5363 => x"ca", + 5364 => x"91", + 5365 => x"fe", + 5366 => x"63", + 5367 => x"79", + 5368 => x"f2", + 5369 => x"78", + 5370 => x"05", + 5371 => x"7a", + 5372 => x"81", + 5373 => x"3d", + 5374 => x"53", + 5375 => x"51", + 5376 => x"3f", + 5377 => x"08", + 5378 => x"e1", + 5379 => x"fe", + 5380 => x"fe", + 5381 => x"fe", + 5382 => x"91", + 5383 => x"80", + 5384 => x"38", + 5385 => x"ec", + 5386 => x"f8", + 5387 => x"ff", + 5388 => x"ca", + 5389 => x"2e", + 5390 => x"91", + 5391 => x"fe", + 5392 => x"63", + 5393 => x"27", + 5394 => x"61", + 5395 => x"81", + 5396 => x"79", + 5397 => x"05", + 5398 => x"b7", + 5399 => x"11", + 5400 => x"05", + 5401 => x"8e", + 5402 => x"88", + 5403 => x"f8", + 5404 => x"3d", + 5405 => x"53", + 5406 => x"51", + 5407 => x"3f", + 5408 => x"08", + 5409 => x"e5", + 5410 => x"fe", + 5411 => x"fe", + 5412 => x"fe", + 5413 => x"91", + 5414 => x"80", + 5415 => x"38", + 5416 => x"51", + 5417 => x"3f", + 5418 => x"63", + 5419 => x"61", + 5420 => x"33", + 5421 => x"78", + 5422 => x"38", + 5423 => x"54", + 5424 => x"79", + 5425 => x"d4", + 5426 => x"b5", + 5427 => x"62", + 5428 => x"5a", + 5429 => x"c2", + 5430 => x"ba", + 5431 => x"fe", + 5432 => x"fe", + 5433 => x"fe", + 5434 => x"91", + 5435 => x"80", + 5436 => x"c7", + 5437 => x"78", + 5438 => x"38", + 5439 => x"08", + 5440 => x"91", + 5441 => x"59", + 5442 => x"88", + 5443 => x"ec", + 5444 => x"39", + 5445 => x"33", + 5446 => x"38", + 5447 => x"33", + 5448 => x"2e", + 5449 => x"c6", + 5450 => x"89", + 5451 => x"84", + 5452 => x"05", + 5453 => x"fe", + 5454 => x"fe", + 5455 => x"fe", + 5456 => x"91", + 5457 => x"80", + 5458 => x"c7", + 5459 => x"78", + 5460 => x"38", + 5461 => x"08", + 5462 => x"91", + 5463 => x"59", + 5464 => x"88", + 5465 => x"f0", + 5466 => x"39", + 5467 => x"33", + 5468 => x"38", + 5469 => x"33", + 5470 => x"2e", + 5471 => x"c6", + 5472 => x"88", + 5473 => x"84", + 5474 => x"43", + 5475 => x"ec", + 5476 => x"f8", + 5477 => x"fc", + 5478 => x"ca", + 5479 => x"2e", + 5480 => x"62", + 5481 => x"88", + 5482 => x"81", + 5483 => x"2e", + 5484 => x"80", + 5485 => x"79", + 5486 => x"38", + 5487 => x"c3", + 5488 => x"f4", + 5489 => x"55", + 5490 => x"53", + 5491 => x"51", + 5492 => x"91", + 5493 => x"84", + 5494 => x"3d", + 5495 => x"53", + 5496 => x"51", + 5497 => x"3f", + 5498 => x"08", + 5499 => x"fd", + 5500 => x"fe", + 5501 => x"fe", + 5502 => x"fe", + 5503 => x"91", + 5504 => x"80", + 5505 => x"63", + 5506 => x"cb", + 5507 => x"34", + 5508 => x"44", + 5509 => x"f0", + 5510 => x"f8", + 5511 => x"fb", + 5512 => x"ca", + 5513 => x"38", + 5514 => x"63", + 5515 => x"52", + 5516 => x"51", + 5517 => x"3f", + 5518 => x"79", + 5519 => x"9b", + 5520 => x"79", + 5521 => x"ae", + 5522 => x"38", + 5523 => x"a0", + 5524 => x"fe", + 5525 => x"fe", + 5526 => x"fe", + 5527 => x"91", + 5528 => x"80", + 5529 => x"63", + 5530 => x"cb", + 5531 => x"34", + 5532 => x"44", + 5533 => x"91", + 5534 => x"fe", + 5535 => x"ff", + 5536 => x"3d", + 5537 => x"53", + 5538 => x"51", + 5539 => x"3f", + 5540 => x"08", + 5541 => x"d5", + 5542 => x"fe", + 5543 => x"fe", + 5544 => x"fe", + 5545 => x"91", + 5546 => x"80", + 5547 => x"60", + 5548 => x"05", + 5549 => x"82", + 5550 => x"78", + 5551 => x"fe", + 5552 => x"fe", + 5553 => x"fe", + 5554 => x"91", + 5555 => x"df", + 5556 => x"39", + 5557 => x"54", + 5558 => x"a0", + 5559 => x"a1", + 5560 => x"52", + 5561 => x"f8", + 5562 => x"45", + 5563 => x"78", + 5564 => x"f9", + 5565 => x"26", + 5566 => x"84", + 5567 => x"39", + 5568 => x"e4", + 5569 => x"f8", + 5570 => x"fb", + 5571 => x"ca", + 5572 => x"2e", + 5573 => x"59", + 5574 => x"22", + 5575 => x"05", + 5576 => x"41", + 5577 => x"91", + 5578 => x"fe", + 5579 => x"ff", + 5580 => x"3d", + 5581 => x"53", + 5582 => x"51", + 5583 => x"3f", + 5584 => x"08", + 5585 => x"a5", + 5586 => x"fe", + 5587 => x"fe", + 5588 => x"fe", + 5589 => x"91", + 5590 => x"80", + 5591 => x"60", + 5592 => x"59", + 5593 => x"41", + 5594 => x"e4", + 5595 => x"f8", + 5596 => x"fa", + 5597 => x"ca", + 5598 => x"38", + 5599 => x"60", + 5600 => x"52", + 5601 => x"51", + 5602 => x"3f", + 5603 => x"79", + 5604 => x"c7", + 5605 => x"79", + 5606 => x"ae", + 5607 => x"38", + 5608 => x"a8", + 5609 => x"fe", + 5610 => x"fe", + 5611 => x"fe", + 5612 => x"91", + 5613 => x"80", + 5614 => x"7f", + 5615 => x"91", + 5616 => x"fe", + 5617 => x"60", + 5618 => x"59", + 5619 => x"41", + 5620 => x"91", + 5621 => x"fe", + 5622 => x"ff", + 5623 => x"c4", + 5624 => x"f0", + 5625 => x"51", + 5626 => x"3f", + 5627 => x"91", + 5628 => x"fe", + 5629 => x"a2", + 5630 => x"f9", + 5631 => x"39", + 5632 => x"0b", + 5633 => x"84", + 5634 => x"81", + 5635 => x"94", + 5636 => x"c4", + 5637 => x"f0", + 5638 => x"d1", + 5639 => x"fc", + 5640 => x"f9", + 5641 => x"83", + 5642 => x"94", + 5643 => x"80", + 5644 => x"c0", + 5645 => x"f1", + 5646 => x"3d", + 5647 => x"53", + 5648 => x"51", + 5649 => x"3f", + 5650 => x"08", + 5651 => x"9d", + 5652 => x"91", + 5653 => x"fe", + 5654 => x"63", + 5655 => x"b7", + 5656 => x"11", + 5657 => x"05", + 5658 => x"8a", + 5659 => x"88", + 5660 => x"f0", + 5661 => x"52", + 5662 => x"51", + 5663 => x"3f", + 5664 => x"2d", + 5665 => x"08", + 5666 => x"88", + 5667 => x"f0", + 5668 => x"ca", + 5669 => x"91", + 5670 => x"fe", + 5671 => x"f0", + 5672 => x"c5", + 5673 => x"ee", + 5674 => x"ce", + 5675 => x"bd", + 5676 => x"80", + 5677 => x"e5", + 5678 => x"ff", + 5679 => x"ea", + 5680 => x"a9", + 5681 => x"33", + 5682 => x"80", + 5683 => x"38", + 5684 => x"80", + 5685 => x"80", + 5686 => x"38", + 5687 => x"f8", + 5688 => x"de", + 5689 => x"c6", + 5690 => x"ca", + 5691 => x"91", + 5692 => x"80", + 5693 => x"9c", + 5694 => x"70", + 5695 => x"f4", + 5696 => x"c6", + 5697 => x"ca", + 5698 => x"56", + 5699 => x"46", + 5700 => x"80", + 5701 => x"0a", + 5702 => x"0a", + 5703 => x"ea", + 5704 => x"ca", + 5705 => x"7c", + 5706 => x"81", + 5707 => x"78", + 5708 => x"ff", + 5709 => x"06", + 5710 => x"91", + 5711 => x"fe", + 5712 => x"ef", + 5713 => x"3d", + 5714 => x"91", + 5715 => x"90", + 5716 => x"91", + 5717 => x"90", + 5718 => x"91", + 5719 => x"fe", + 5720 => x"fe", + 5721 => x"91", + 5722 => x"fe", + 5723 => x"91", + 5724 => x"fe", + 5725 => x"91", + 5726 => x"fe", + 5727 => x"81", + 5728 => x"3f", + 5729 => x"80", + 5730 => x"0f", + 5731 => x"0f", + 5732 => x"0f", + 5733 => x"0f", + 5734 => x"0f", + 5735 => x"4c", + 5736 => x"4b", + 5737 => x"4b", + 5738 => x"4b", + 5739 => x"4b", + 5740 => x"4b", + 5741 => x"4b", + 5742 => x"4b", + 5743 => x"4b", + 5744 => x"4b", + 5745 => x"4b", + 5746 => x"4b", + 5747 => x"4b", + 5748 => x"4b", + 5749 => x"4b", + 5750 => x"4b", + 5751 => x"4b", + 5752 => x"4c", + 5753 => x"4c", + 5754 => x"4c", + 5755 => x"2f", + 5756 => x"25", + 5757 => x"64", + 5758 => x"3a", + 5759 => x"25", + 5760 => x"0a", + 5761 => x"43", + 5762 => x"6e", + 5763 => x"75", + 5764 => x"69", + 5765 => x"00", + 5766 => x"66", + 5767 => x"20", + 5768 => x"20", + 5769 => x"66", + 5770 => x"00", + 5771 => x"44", + 5772 => x"63", + 5773 => x"69", + 5774 => x"65", + 5775 => x"74", + 5776 => x"0a", + 5777 => x"20", + 5778 => x"53", + 5779 => x"52", + 5780 => x"28", + 5781 => x"72", + 5782 => x"30", + 5783 => x"20", + 5784 => x"65", + 5785 => x"38", + 5786 => x"0a", + 5787 => x"20", + 5788 => x"41", + 5789 => x"53", + 5790 => x"74", + 5791 => x"38", + 5792 => x"53", + 5793 => x"3d", + 5794 => x"58", + 5795 => x"00", + 5796 => x"20", + 5797 => x"4d", + 5798 => x"74", + 5799 => x"3d", + 5800 => x"58", + 5801 => x"69", + 5802 => x"25", + 5803 => x"29", + 5804 => x"00", + 5805 => x"20", + 5806 => x"43", + 5807 => x"00", + 5808 => x"20", + 5809 => x"32", + 5810 => x"00", + 5811 => x"20", + 5812 => x"49", + 5813 => x"00", + 5814 => x"20", + 5815 => x"20", + 5816 => x"64", + 5817 => x"65", + 5818 => x"65", + 5819 => x"30", + 5820 => x"2e", + 5821 => x"00", + 5822 => x"20", + 5823 => x"54", + 5824 => x"55", + 5825 => x"43", + 5826 => x"52", + 5827 => x"45", + 5828 => x"00", + 5829 => x"20", + 5830 => x"4d", + 5831 => x"20", + 5832 => x"6d", + 5833 => x"3d", + 5834 => x"58", + 5835 => x"00", + 5836 => x"64", + 5837 => x"73", + 5838 => x"0a", + 5839 => x"20", + 5840 => x"55", + 5841 => x"73", + 5842 => x"56", + 5843 => x"6f", + 5844 => x"64", + 5845 => x"73", + 5846 => x"20", + 5847 => x"58", + 5848 => x"00", + 5849 => x"20", + 5850 => x"55", + 5851 => x"6d", + 5852 => x"20", + 5853 => x"72", + 5854 => x"64", + 5855 => x"73", + 5856 => x"20", + 5857 => x"58", + 5858 => x"00", + 5859 => x"20", + 5860 => x"61", + 5861 => x"53", + 5862 => x"74", + 5863 => x"64", + 5864 => x"73", + 5865 => x"20", + 5866 => x"20", + 5867 => x"58", + 5868 => x"00", + 5869 => x"20", + 5870 => x"55", + 5871 => x"20", + 5872 => x"20", + 5873 => x"20", + 5874 => x"20", + 5875 => x"20", + 5876 => x"20", + 5877 => x"58", + 5878 => x"00", + 5879 => x"20", + 5880 => x"73", + 5881 => x"20", + 5882 => x"63", + 5883 => x"72", + 5884 => x"20", + 5885 => x"20", + 5886 => x"20", + 5887 => x"58", + 5888 => x"00", + 5889 => x"61", + 5890 => x"00", + 5891 => x"64", + 5892 => x"00", + 5893 => x"65", + 5894 => x"00", + 5895 => x"4f", + 5896 => x"4f", + 5897 => x"00", + 5898 => x"6b", + 5899 => x"6e", + 5900 => x"00", + 5901 => x"2b", + 5902 => x"3c", + 5903 => x"5b", + 5904 => x"00", + 5905 => x"54", + 5906 => x"54", + 5907 => x"00", + 5908 => x"90", + 5909 => x"4f", + 5910 => x"30", + 5911 => x"20", + 5912 => x"45", + 5913 => x"20", + 5914 => x"33", + 5915 => x"20", + 5916 => x"20", + 5917 => x"45", + 5918 => x"20", + 5919 => x"20", + 5920 => x"20", + 5921 => x"5c", + 5922 => x"00", + 5923 => x"00", + 5924 => x"00", + 5925 => x"45", + 5926 => x"8f", + 5927 => x"45", + 5928 => x"8e", + 5929 => x"92", + 5930 => x"55", + 5931 => x"9a", + 5932 => x"9e", + 5933 => x"4f", + 5934 => x"a6", + 5935 => x"aa", + 5936 => x"ae", + 5937 => x"b2", + 5938 => x"b6", + 5939 => x"ba", + 5940 => x"be", + 5941 => x"c2", + 5942 => x"c6", + 5943 => x"ca", + 5944 => x"ce", + 5945 => x"d2", + 5946 => x"d6", + 5947 => x"da", + 5948 => x"de", + 5949 => x"e2", + 5950 => x"e6", + 5951 => x"ea", + 5952 => x"ee", + 5953 => x"f2", + 5954 => x"f6", + 5955 => x"fa", + 5956 => x"fe", + 5957 => x"2c", + 5958 => x"5d", + 5959 => x"2a", + 5960 => x"3f", + 5961 => x"00", + 5962 => x"00", + 5963 => x"00", + 5964 => x"02", + 5965 => x"00", + 5966 => x"00", + 5967 => x"00", + 5968 => x"00", + 5969 => x"00", + 5970 => x"6e", + 5971 => x"00", + 5972 => x"6f", + 5973 => x"00", + 5974 => x"6e", + 5975 => x"00", + 5976 => x"6f", + 5977 => x"00", + 5978 => x"78", + 5979 => x"00", + 5980 => x"6c", + 5981 => x"00", + 5982 => x"6f", + 5983 => x"00", + 5984 => x"69", + 5985 => x"00", + 5986 => x"75", + 5987 => x"00", + 5988 => x"62", + 5989 => x"68", + 5990 => x"77", + 5991 => x"64", + 5992 => x"65", + 5993 => x"64", + 5994 => x"65", + 5995 => x"6c", + 5996 => x"00", + 5997 => x"70", + 5998 => x"73", + 5999 => x"74", + 6000 => x"73", + 6001 => x"00", + 6002 => x"66", + 6003 => x"00", + 6004 => x"73", + 6005 => x"00", + 6006 => x"73", + 6007 => x"72", + 6008 => x"0a", + 6009 => x"74", + 6010 => x"61", + 6011 => x"72", + 6012 => x"2e", + 6013 => x"00", + 6014 => x"73", + 6015 => x"6f", + 6016 => x"65", + 6017 => x"2e", + 6018 => x"00", + 6019 => x"20", + 6020 => x"65", + 6021 => x"75", + 6022 => x"0a", + 6023 => x"20", + 6024 => x"68", + 6025 => x"75", + 6026 => x"0a", + 6027 => x"76", + 6028 => x"64", + 6029 => x"6c", + 6030 => x"6d", + 6031 => x"00", + 6032 => x"63", + 6033 => x"20", + 6034 => x"69", + 6035 => x"0a", + 6036 => x"6c", + 6037 => x"6c", + 6038 => x"64", + 6039 => x"78", + 6040 => x"73", + 6041 => x"00", + 6042 => x"6c", + 6043 => x"61", + 6044 => x"65", + 6045 => x"76", + 6046 => x"64", + 6047 => x"00", + 6048 => x"20", + 6049 => x"77", + 6050 => x"65", + 6051 => x"6f", + 6052 => x"74", + 6053 => x"0a", + 6054 => x"69", + 6055 => x"6e", + 6056 => x"65", + 6057 => x"73", + 6058 => x"76", + 6059 => x"64", + 6060 => x"00", + 6061 => x"73", + 6062 => x"6f", + 6063 => x"6e", + 6064 => x"65", + 6065 => x"00", + 6066 => x"20", + 6067 => x"70", + 6068 => x"62", + 6069 => x"66", + 6070 => x"73", + 6071 => x"65", + 6072 => x"6f", + 6073 => x"20", + 6074 => x"64", + 6075 => x"2e", + 6076 => x"00", + 6077 => x"72", + 6078 => x"20", + 6079 => x"72", + 6080 => x"2e", + 6081 => x"00", + 6082 => x"6d", + 6083 => x"74", + 6084 => x"70", + 6085 => x"74", + 6086 => x"20", + 6087 => x"63", + 6088 => x"65", + 6089 => x"00", + 6090 => x"6c", + 6091 => x"73", + 6092 => x"63", + 6093 => x"2e", + 6094 => x"00", + 6095 => x"73", + 6096 => x"69", + 6097 => x"6e", + 6098 => x"65", + 6099 => x"79", + 6100 => x"00", + 6101 => x"6f", + 6102 => x"6e", + 6103 => x"70", + 6104 => x"66", + 6105 => x"73", + 6106 => x"00", + 6107 => x"72", + 6108 => x"74", + 6109 => x"20", + 6110 => x"6f", + 6111 => x"63", + 6112 => x"00", + 6113 => x"63", + 6114 => x"73", + 6115 => x"00", + 6116 => x"6b", + 6117 => x"6e", + 6118 => x"72", + 6119 => x"0a", + 6120 => x"6c", + 6121 => x"79", + 6122 => x"20", + 6123 => x"61", + 6124 => x"6c", + 6125 => x"79", + 6126 => x"2f", + 6127 => x"2e", + 6128 => x"00", + 6129 => x"38", + 6130 => x"00", + 6131 => x"20", + 6132 => x"34", + 6133 => x"00", + 6134 => x"20", + 6135 => x"20", + 6136 => x"00", + 6137 => x"32", + 6138 => x"00", + 6139 => x"00", + 6140 => x"00", + 6141 => x"0a", + 6142 => x"61", + 6143 => x"00", + 6144 => x"55", + 6145 => x"00", + 6146 => x"2a", + 6147 => x"20", + 6148 => x"00", + 6149 => x"2f", + 6150 => x"32", + 6151 => x"00", + 6152 => x"2e", + 6153 => x"00", + 6154 => x"50", + 6155 => x"72", + 6156 => x"25", + 6157 => x"29", + 6158 => x"20", + 6159 => x"2a", + 6160 => x"00", + 6161 => x"55", + 6162 => x"49", + 6163 => x"72", + 6164 => x"74", + 6165 => x"6e", + 6166 => x"72", + 6167 => x"00", + 6168 => x"6d", + 6169 => x"69", + 6170 => x"72", + 6171 => x"74", + 6172 => x"00", + 6173 => x"32", + 6174 => x"74", + 6175 => x"75", + 6176 => x"00", + 6177 => x"43", + 6178 => x"52", + 6179 => x"6e", + 6180 => x"72", + 6181 => x"0a", + 6182 => x"43", + 6183 => x"57", + 6184 => x"6e", + 6185 => x"72", + 6186 => x"0a", + 6187 => x"52", + 6188 => x"52", + 6189 => x"6e", + 6190 => x"72", + 6191 => x"0a", + 6192 => x"52", + 6193 => x"54", + 6194 => x"6e", + 6195 => x"72", + 6196 => x"0a", + 6197 => x"52", + 6198 => x"52", + 6199 => x"6e", + 6200 => x"72", + 6201 => x"0a", + 6202 => x"52", + 6203 => x"54", + 6204 => x"6e", + 6205 => x"72", + 6206 => x"0a", + 6207 => x"74", + 6208 => x"67", + 6209 => x"20", + 6210 => x"65", + 6211 => x"2e", + 6212 => x"00", + 6213 => x"61", + 6214 => x"6e", + 6215 => x"69", + 6216 => x"2e", + 6217 => x"00", + 6218 => x"00", + 6219 => x"69", + 6220 => x"20", + 6221 => x"69", + 6222 => x"69", + 6223 => x"73", + 6224 => x"64", + 6225 => x"72", + 6226 => x"2c", + 6227 => x"65", + 6228 => x"20", + 6229 => x"74", + 6230 => x"6e", + 6231 => x"6c", + 6232 => x"00", + 6233 => x"00", + 6234 => x"64", + 6235 => x"73", + 6236 => x"64", + 6237 => x"00", + 6238 => x"69", + 6239 => x"6c", + 6240 => x"64", + 6241 => x"00", + 6242 => x"69", + 6243 => x"20", + 6244 => x"69", + 6245 => x"69", + 6246 => x"73", + 6247 => x"00", + 6248 => x"3d", + 6249 => x"00", + 6250 => x"3a", + 6251 => x"65", + 6252 => x"6e", + 6253 => x"2e", + 6254 => x"70", + 6255 => x"67", + 6256 => x"00", + 6257 => x"6d", + 6258 => x"69", + 6259 => x"2e", + 6260 => x"00", + 6261 => x"38", + 6262 => x"25", + 6263 => x"29", + 6264 => x"30", + 6265 => x"28", + 6266 => x"78", + 6267 => x"00", + 6268 => x"6d", + 6269 => x"65", + 6270 => x"79", + 6271 => x"00", + 6272 => x"6f", + 6273 => x"65", + 6274 => x"0a", + 6275 => x"38", + 6276 => x"30", + 6277 => x"00", + 6278 => x"3f", + 6279 => x"00", + 6280 => x"38", + 6281 => x"30", + 6282 => x"00", + 6283 => x"38", + 6284 => x"30", + 6285 => x"00", + 6286 => x"73", + 6287 => x"69", + 6288 => x"69", + 6289 => x"72", + 6290 => x"74", + 6291 => x"00", + 6292 => x"61", + 6293 => x"6e", + 6294 => x"6e", + 6295 => x"72", + 6296 => x"73", + 6297 => x"00", + 6298 => x"73", + 6299 => x"65", + 6300 => x"61", + 6301 => x"66", + 6302 => x"0a", + 6303 => x"61", + 6304 => x"6e", + 6305 => x"61", + 6306 => x"66", + 6307 => x"0a", + 6308 => x"65", + 6309 => x"69", + 6310 => x"63", + 6311 => x"20", + 6312 => x"30", + 6313 => x"2e", + 6314 => x"00", + 6315 => x"6c", + 6316 => x"67", + 6317 => x"64", + 6318 => x"20", + 6319 => x"78", + 6320 => x"2e", + 6321 => x"00", + 6322 => x"6c", + 6323 => x"65", + 6324 => x"6e", + 6325 => x"63", + 6326 => x"20", + 6327 => x"29", + 6328 => x"00", + 6329 => x"73", + 6330 => x"74", + 6331 => x"20", + 6332 => x"6c", + 6333 => x"74", + 6334 => x"2e", + 6335 => x"00", + 6336 => x"6c", + 6337 => x"65", + 6338 => x"74", + 6339 => x"2e", + 6340 => x"00", + 6341 => x"55", + 6342 => x"6e", + 6343 => x"3a", + 6344 => x"5c", + 6345 => x"25", + 6346 => x"00", + 6347 => x"64", + 6348 => x"6d", + 6349 => x"64", + 6350 => x"00", + 6351 => x"6e", + 6352 => x"67", + 6353 => x"0a", + 6354 => x"61", + 6355 => x"6e", + 6356 => x"6e", + 6357 => x"72", + 6358 => x"73", + 6359 => x"0a", + 6360 => x"00", + 6361 => x"00", + 6362 => x"7f", + 6363 => x"00", + 6364 => x"7f", + 6365 => x"00", + 6366 => x"7f", + 6367 => x"00", + 6368 => x"00", + 6369 => x"78", + 6370 => x"00", + 6371 => x"e1", + 6372 => x"01", + 6373 => x"01", + 6374 => x"01", + 6375 => x"00", + 6376 => x"00", + 6377 => x"00", + 6378 => x"5d", + 6379 => x"01", + 6380 => x"00", + 6381 => x"00", + 6382 => x"5d", + 6383 => x"01", + 6384 => x"00", + 6385 => x"00", + 6386 => x"5d", + 6387 => x"03", + 6388 => x"00", + 6389 => x"00", + 6390 => x"5d", + 6391 => x"03", + 6392 => x"00", + 6393 => x"00", + 6394 => x"5d", + 6395 => x"03", + 6396 => x"00", + 6397 => x"00", + 6398 => x"5d", + 6399 => x"04", + 6400 => x"00", + 6401 => x"00", + 6402 => x"5d", + 6403 => x"04", + 6404 => x"00", + 6405 => x"00", + 6406 => x"5d", + 6407 => x"04", + 6408 => x"00", + 6409 => x"00", + 6410 => x"5d", + 6411 => x"04", + 6412 => x"00", + 6413 => x"00", + 6414 => x"5d", + 6415 => x"04", + 6416 => x"00", + 6417 => x"00", + 6418 => x"5d", + 6419 => x"04", + 6420 => x"00", + 6421 => x"00", + 6422 => x"5d", + 6423 => x"04", + 6424 => x"00", + 6425 => x"00", + 6426 => x"5d", + 6427 => x"05", + 6428 => x"00", + 6429 => x"00", + 6430 => x"5d", + 6431 => x"05", + 6432 => x"00", + 6433 => x"00", + 6434 => x"5d", + 6435 => x"05", + 6436 => x"00", + 6437 => x"00", + 6438 => x"5d", + 6439 => x"05", + 6440 => x"00", + 6441 => x"00", + 6442 => x"5d", + 6443 => x"07", + 6444 => x"00", + 6445 => x"00", + 6446 => x"5d", + 6447 => x"07", + 6448 => x"00", + 6449 => x"00", + 6450 => x"5d", + 6451 => x"08", + 6452 => x"00", + 6453 => x"00", + 6454 => x"5d", + 6455 => x"08", + 6456 => x"00", + 6457 => x"00", + 6458 => x"5d", + 6459 => x"08", + 6460 => x"00", + 6461 => x"00", + 6462 => x"5d", + 6463 => x"08", + 6464 => x"00", + 6465 => x"00", + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + 0 => x"0b", + 1 => x"0b", + 2 => x"8a", + 3 => x"ff", + 4 => x"ff", + 5 => x"ff", + 6 => x"ff", + 7 => x"ff", + 8 => x"0b", + 9 => x"04", + 10 => x"84", + 11 => x"0b", + 12 => x"04", + 13 => x"84", + 14 => x"0b", + 15 => x"04", + 16 => x"84", + 17 => x"0b", + 18 => x"04", + 19 => x"84", + 20 => x"0b", + 21 => x"04", + 22 => x"85", + 23 => x"0b", + 24 => x"04", + 25 => x"85", + 26 => x"0b", + 27 => x"04", + 28 => x"85", + 29 => x"0b", + 30 => x"04", + 31 => x"85", + 32 => x"0b", + 33 => x"04", + 34 => x"86", + 35 => x"0b", + 36 => x"04", + 37 => x"86", + 38 => x"0b", + 39 => x"04", + 40 => x"86", + 41 => x"0b", + 42 => x"04", + 43 => x"86", + 44 => x"0b", + 45 => x"04", + 46 => x"87", + 47 => x"0b", + 48 => x"04", + 49 => x"87", + 50 => x"0b", + 51 => x"04", + 52 => x"87", + 53 => x"0b", + 54 => x"04", + 55 => x"88", + 56 => x"0b", + 57 => x"04", + 58 => x"88", + 59 => x"0b", + 60 => x"04", + 61 => x"88", + 62 => x"0b", + 63 => x"04", + 64 => x"88", + 65 => x"0b", + 66 => x"04", + 67 => x"89", + 68 => x"0b", + 69 => x"04", + 70 => x"89", + 71 => x"0b", + 72 => x"04", + 73 => x"89", + 74 => x"0b", + 75 => x"04", + 76 => x"89", + 77 => x"0b", + 78 => x"04", + 79 => x"8a", + 80 => x"0b", + 81 => x"04", + 82 => x"8a", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"00", + 89 => x"00", + 90 => x"00", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"00", + 97 => x"00", + 98 => x"00", + 99 => x"00", + 100 => x"00", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"00", + 105 => x"00", + 106 => x"00", + 107 => x"00", + 108 => x"00", + 109 => x"00", + 110 => x"00", + 111 => x"00", + 112 => x"00", + 113 => x"00", + 114 => x"00", + 115 => x"00", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"00", + 121 => x"00", + 122 => x"00", + 123 => x"00", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"90", + 129 => x"91", + 130 => x"90", + 131 => x"91", + 132 => x"88", + 133 => x"04", + 134 => x"0c", + 135 => x"2d", + 136 => x"08", + 137 => x"90", + 138 => x"94", + 139 => x"fe", + 140 => x"94", + 141 => x"80", + 142 => x"ca", + 143 => x"a0", + 144 => x"ca", + 145 => x"c0", + 146 => x"91", + 147 => x"90", + 148 => x"91", + 149 => x"88", + 150 => x"04", + 151 => x"0c", + 152 => x"2d", + 153 => x"08", + 154 => x"90", + 155 => x"94", + 156 => x"bf", + 157 => x"94", + 158 => x"80", + 159 => x"ca", + 160 => x"a7", + 161 => x"ca", + 162 => x"c0", + 163 => x"91", + 164 => x"90", + 165 => x"91", + 166 => x"88", + 167 => x"04", + 168 => x"0c", + 169 => x"2d", + 170 => x"08", + 171 => x"90", + 172 => x"94", + 173 => x"96", + 174 => x"94", + 175 => x"80", + 176 => x"ca", + 177 => x"a6", + 178 => x"ca", + 179 => x"c0", + 180 => x"91", + 181 => x"90", + 182 => x"91", + 183 => x"88", + 184 => x"04", + 185 => x"0c", + 186 => x"2d", + 187 => x"08", + 188 => x"90", + 189 => x"94", + 190 => x"89", + 191 => x"94", + 192 => x"80", + 193 => x"ca", + 194 => x"91", + 195 => x"ca", + 196 => x"c0", + 197 => x"91", + 198 => x"90", + 199 => x"91", + 200 => x"88", + 201 => x"04", + 202 => x"0c", + 203 => x"2d", + 204 => x"08", + 205 => x"90", + 206 => x"94", + 207 => x"8d", + 208 => x"94", + 209 => x"80", + 210 => x"ca", + 211 => x"e1", + 212 => x"ca", + 213 => x"c0", + 214 => x"91", + 215 => x"90", + 216 => x"91", + 217 => x"88", + 218 => x"04", + 219 => x"0c", + 220 => x"2d", + 221 => x"08", + 222 => x"90", + 223 => x"94", + 224 => x"fc", + 225 => x"94", + 226 => x"80", + 227 => x"ca", + 228 => x"e7", + 229 => x"ca", + 230 => x"c0", + 231 => x"91", + 232 => x"90", + 233 => x"91", + 234 => x"88", + 235 => x"04", + 236 => x"0c", + 237 => x"2d", + 238 => x"08", + 239 => x"90", + 240 => x"94", + 241 => x"f9", + 242 => x"94", + 243 => x"80", + 244 => x"ca", + 245 => x"fa", + 246 => x"ca", + 247 => x"c0", + 248 => x"91", + 249 => x"90", + 250 => x"91", + 251 => x"88", + 252 => x"04", + 253 => x"0c", + 254 => x"2d", + 255 => x"08", + 256 => x"90", + 257 => x"94", + 258 => x"fd", + 259 => x"94", + 260 => x"80", + 261 => x"ca", + 262 => x"80", + 263 => x"ca", + 264 => x"c0", + 265 => x"91", + 266 => x"91", + 267 => x"91", + 268 => x"88", + 269 => x"04", + 270 => x"0c", + 271 => x"2d", + 272 => x"08", + 273 => x"90", + 274 => x"94", + 275 => x"c6", + 276 => x"94", + 277 => x"80", + 278 => x"ca", + 279 => x"ea", + 280 => x"ca", + 281 => x"c0", + 282 => x"91", + 283 => x"90", + 284 => x"91", + 285 => x"88", + 286 => x"04", + 287 => x"0c", + 288 => x"2d", + 289 => x"08", + 290 => x"90", + 291 => x"94", + 292 => x"b3", + 293 => x"94", + 294 => x"80", + 295 => x"ca", + 296 => x"87", + 297 => x"ca", + 298 => x"c0", + 299 => x"91", + 300 => x"90", + 301 => x"91", + 302 => x"88", + 303 => x"04", + 304 => x"0c", + 305 => x"2d", + 306 => x"08", + 307 => x"90", + 308 => x"94", + 309 => x"f6", + 310 => x"94", + 311 => x"80", + 312 => x"ca", + 313 => x"ae", + 314 => x"ca", + 315 => x"c0", + 316 => x"91", + 317 => x"90", + 318 => x"91", + 319 => x"88", + 320 => x"04", + 321 => x"0c", + 322 => x"2d", + 323 => x"08", + 324 => x"90", + 325 => x"94", + 326 => x"94", + 327 => x"94", + 328 => x"80", + 329 => x"ca", + 330 => x"94", + 331 => x"ca", + 332 => x"c0", + 333 => x"91", + 334 => x"91", + 335 => x"91", + 336 => x"88", + 337 => x"04", + 338 => x"70", + 339 => x"27", + 340 => x"71", + 341 => x"53", + 342 => x"90", + 343 => x"90", + 344 => x"91", + 345 => x"3c", + 346 => x"94", + 347 => x"ca", + 348 => x"3d", + 349 => x"91", + 350 => x"8c", + 351 => x"91", + 352 => x"88", + 353 => x"80", + 354 => x"ca", + 355 => x"91", + 356 => x"54", + 357 => x"91", + 358 => x"04", + 359 => x"08", + 360 => x"94", + 361 => x"0d", + 362 => x"ca", + 363 => x"05", + 364 => x"ca", + 365 => x"05", + 366 => x"3f", + 367 => x"08", + 368 => x"88", + 369 => x"3d", + 370 => x"94", + 371 => x"ca", + 372 => x"91", + 373 => x"fd", + 374 => x"0b", + 375 => x"08", + 376 => x"80", + 377 => x"94", + 378 => x"0c", + 379 => x"08", + 380 => x"91", + 381 => x"88", + 382 => x"b9", + 383 => x"94", + 384 => x"08", + 385 => x"38", + 386 => x"ca", + 387 => x"05", + 388 => x"38", + 389 => x"08", + 390 => x"10", + 391 => x"08", + 392 => x"91", + 393 => x"fc", + 394 => x"91", + 395 => x"fc", + 396 => x"b8", + 397 => x"94", + 398 => x"08", + 399 => x"e1", + 400 => x"94", + 401 => x"08", + 402 => x"08", + 403 => x"26", + 404 => x"ca", + 405 => x"05", + 406 => x"94", + 407 => x"08", + 408 => x"94", + 409 => x"0c", + 410 => x"08", + 411 => x"91", + 412 => x"fc", + 413 => x"91", + 414 => x"f8", + 415 => x"ca", + 416 => x"05", + 417 => x"91", + 418 => x"fc", + 419 => x"ca", + 420 => x"05", + 421 => x"91", + 422 => x"8c", + 423 => x"95", + 424 => x"94", + 425 => x"08", + 426 => x"38", + 427 => x"08", + 428 => x"70", + 429 => x"08", + 430 => x"51", + 431 => x"ca", + 432 => x"05", + 433 => x"ca", + 434 => x"05", + 435 => x"ca", + 436 => x"05", + 437 => x"88", + 438 => x"0d", + 439 => x"0c", + 440 => x"0d", + 441 => x"02", + 442 => x"05", + 443 => x"53", + 444 => x"27", + 445 => x"83", + 446 => x"80", + 447 => x"ff", + 448 => x"ff", + 449 => x"73", + 450 => x"05", + 451 => x"12", + 452 => x"2e", + 453 => x"ef", + 454 => x"ca", + 455 => x"3d", + 456 => x"74", + 457 => x"07", + 458 => x"2b", + 459 => x"51", + 460 => x"a5", + 461 => x"70", + 462 => x"0c", + 463 => x"84", + 464 => x"72", + 465 => x"05", + 466 => x"71", + 467 => x"53", + 468 => x"52", + 469 => x"dd", + 470 => x"27", + 471 => x"71", + 472 => x"53", + 473 => x"52", + 474 => x"f2", + 475 => x"ff", + 476 => x"3d", + 477 => x"70", + 478 => x"06", + 479 => x"70", + 480 => x"73", + 481 => x"56", + 482 => x"08", + 483 => x"38", + 484 => x"52", + 485 => x"81", + 486 => x"54", + 487 => x"9d", + 488 => x"55", + 489 => x"09", + 490 => x"38", + 491 => x"14", + 492 => x"81", + 493 => x"56", + 494 => x"e5", + 495 => x"55", + 496 => x"06", + 497 => x"06", + 498 => x"91", + 499 => x"52", + 500 => x"0d", + 501 => x"70", + 502 => x"ff", + 503 => x"f8", + 504 => x"80", + 505 => x"51", + 506 => x"84", + 507 => x"71", + 508 => x"54", + 509 => x"2e", + 510 => x"75", + 511 => x"94", + 512 => x"91", + 513 => x"87", + 514 => x"fe", + 515 => x"52", + 516 => x"88", + 517 => x"86", + 518 => x"88", + 519 => x"06", + 520 => x"14", + 521 => x"80", + 522 => x"71", + 523 => x"0c", + 524 => x"04", + 525 => x"77", + 526 => x"53", + 527 => x"80", + 528 => x"38", + 529 => x"70", + 530 => x"81", + 531 => x"81", + 532 => x"39", + 533 => x"39", + 534 => x"80", + 535 => x"81", + 536 => x"55", + 537 => x"2e", + 538 => x"55", + 539 => x"84", + 540 => x"38", + 541 => x"06", + 542 => x"2e", + 543 => x"88", + 544 => x"70", + 545 => x"34", + 546 => x"71", + 547 => x"ca", + 548 => x"3d", + 549 => x"3d", + 550 => x"72", + 551 => x"91", + 552 => x"fc", + 553 => x"51", + 554 => x"91", + 555 => x"85", + 556 => x"83", + 557 => x"72", + 558 => x"0c", + 559 => x"04", + 560 => x"76", + 561 => x"ff", + 562 => x"81", + 563 => x"26", + 564 => x"83", + 565 => x"05", + 566 => x"70", + 567 => x"8a", + 568 => x"33", + 569 => x"70", + 570 => x"fe", + 571 => x"33", + 572 => x"70", + 573 => x"f2", + 574 => x"33", + 575 => x"70", + 576 => x"e6", + 577 => x"22", + 578 => x"74", + 579 => x"80", + 580 => x"13", + 581 => x"52", + 582 => x"26", + 583 => x"81", + 584 => x"98", + 585 => x"22", + 586 => x"bc", + 587 => x"33", + 588 => x"b8", + 589 => x"33", + 590 => x"b4", + 591 => x"33", + 592 => x"b0", + 593 => x"33", + 594 => x"ac", + 595 => x"33", + 596 => x"a8", + 597 => x"c0", + 598 => x"73", + 599 => x"a0", + 600 => x"87", + 601 => x"0c", + 602 => x"91", + 603 => x"86", + 604 => x"f3", + 605 => x"5b", + 606 => x"9c", + 607 => x"0c", + 608 => x"bc", + 609 => x"7b", + 610 => x"98", + 611 => x"79", + 612 => x"87", + 613 => x"08", + 614 => x"1c", + 615 => x"98", + 616 => x"79", + 617 => x"87", + 618 => x"08", + 619 => x"1c", + 620 => x"98", + 621 => x"79", + 622 => x"87", + 623 => x"08", + 624 => x"1c", + 625 => x"98", + 626 => x"79", + 627 => x"80", + 628 => x"83", + 629 => x"59", + 630 => x"ff", + 631 => x"1b", + 632 => x"1b", + 633 => x"1b", + 634 => x"1b", + 635 => x"1b", + 636 => x"83", + 637 => x"52", + 638 => x"51", + 639 => x"8f", + 640 => x"ff", + 641 => x"8f", + 642 => x"30", + 643 => x"51", + 644 => x"0b", + 645 => x"e0", + 646 => x"0d", + 647 => x"0d", + 648 => x"91", + 649 => x"70", + 650 => x"57", + 651 => x"c0", + 652 => x"74", + 653 => x"38", + 654 => x"94", + 655 => x"70", + 656 => x"81", + 657 => x"52", + 658 => x"8c", + 659 => x"2a", + 660 => x"51", + 661 => x"38", + 662 => x"70", + 663 => x"51", + 664 => x"8d", + 665 => x"2a", + 666 => x"51", + 667 => x"be", + 668 => x"ff", + 669 => x"c0", + 670 => x"70", + 671 => x"38", + 672 => x"90", + 673 => x"0c", + 674 => x"88", + 675 => x"0d", + 676 => x"0d", + 677 => x"33", + 678 => x"c6", + 679 => x"81", + 680 => x"55", + 681 => x"94", + 682 => x"80", + 683 => x"87", + 684 => x"51", + 685 => x"96", + 686 => x"06", + 687 => x"70", + 688 => x"38", + 689 => x"70", + 690 => x"51", + 691 => x"72", + 692 => x"81", + 693 => x"70", + 694 => x"38", + 695 => x"70", + 696 => x"51", + 697 => x"38", + 698 => x"06", + 699 => x"94", + 700 => x"80", + 701 => x"87", + 702 => x"52", + 703 => x"87", + 704 => x"f9", + 705 => x"54", + 706 => x"70", + 707 => x"53", + 708 => x"77", + 709 => x"38", + 710 => x"06", + 711 => x"0b", + 712 => x"33", + 713 => x"06", + 714 => x"58", + 715 => x"84", + 716 => x"2e", + 717 => x"c0", + 718 => x"70", + 719 => x"2a", + 720 => x"53", + 721 => x"80", + 722 => x"71", + 723 => x"81", + 724 => x"70", + 725 => x"81", + 726 => x"06", + 727 => x"80", + 728 => x"71", + 729 => x"81", + 730 => x"70", + 731 => x"74", + 732 => x"51", + 733 => x"80", + 734 => x"2e", + 735 => x"c0", + 736 => x"77", + 737 => x"17", + 738 => x"81", + 739 => x"53", + 740 => x"84", + 741 => x"ca", + 742 => x"3d", + 743 => x"3d", + 744 => x"91", + 745 => x"70", + 746 => x"54", + 747 => x"94", + 748 => x"80", + 749 => x"87", + 750 => x"51", + 751 => x"82", + 752 => x"06", + 753 => x"70", + 754 => x"38", + 755 => x"06", + 756 => x"94", + 757 => x"80", + 758 => x"87", + 759 => x"52", + 760 => x"81", + 761 => x"ca", + 762 => x"84", + 763 => x"fe", + 764 => x"0b", + 765 => x"33", + 766 => x"06", + 767 => x"c0", + 768 => x"70", + 769 => x"38", + 770 => x"94", + 771 => x"70", + 772 => x"81", + 773 => x"51", + 774 => x"80", + 775 => x"72", + 776 => x"51", + 777 => x"80", + 778 => x"2e", + 779 => x"c0", + 780 => x"71", + 781 => x"2b", + 782 => x"51", + 783 => x"91", + 784 => x"84", + 785 => x"ff", + 786 => x"c0", + 787 => x"70", + 788 => x"06", + 789 => x"80", + 790 => x"38", + 791 => x"9c", + 792 => x"e4", + 793 => x"9e", + 794 => x"c6", + 795 => x"c0", + 796 => x"91", + 797 => x"87", + 798 => x"08", + 799 => x"0c", + 800 => x"94", + 801 => x"f4", + 802 => x"9e", + 803 => x"c6", + 804 => x"c0", + 805 => x"91", + 806 => x"87", + 807 => x"08", + 808 => x"0c", + 809 => x"ac", + 810 => x"84", + 811 => x"9e", + 812 => x"70", + 813 => x"23", + 814 => x"84", + 815 => x"8c", + 816 => x"91", + 817 => x"80", + 818 => x"9e", + 819 => x"a0", + 820 => x"52", + 821 => x"2e", + 822 => x"52", + 823 => x"91", + 824 => x"87", + 825 => x"08", + 826 => x"80", + 827 => x"52", + 828 => x"83", + 829 => x"71", + 830 => x"34", + 831 => x"c0", + 832 => x"70", + 833 => x"06", + 834 => x"70", + 835 => x"38", + 836 => x"91", + 837 => x"80", + 838 => x"9e", + 839 => x"90", + 840 => x"52", + 841 => x"2e", + 842 => x"52", + 843 => x"94", + 844 => x"87", + 845 => x"08", + 846 => x"06", + 847 => x"70", + 848 => x"38", + 849 => x"91", + 850 => x"80", + 851 => x"9e", + 852 => x"84", + 853 => x"52", + 854 => x"2e", + 855 => x"52", + 856 => x"96", + 857 => x"87", + 858 => x"08", + 859 => x"06", + 860 => x"70", + 861 => x"38", + 862 => x"91", + 863 => x"80", + 864 => x"9e", + 865 => x"81", + 866 => x"52", + 867 => x"2e", + 868 => x"52", + 869 => x"98", + 870 => x"9e", + 871 => x"80", + 872 => x"86", + 873 => x"51", + 874 => x"99", + 875 => x"87", + 876 => x"08", + 877 => x"51", + 878 => x"80", + 879 => x"81", + 880 => x"c7", + 881 => x"0b", + 882 => x"88", + 883 => x"06", + 884 => x"70", + 885 => x"38", + 886 => x"91", + 887 => x"87", + 888 => x"08", + 889 => x"51", + 890 => x"c7", + 891 => x"3d", + 892 => x"3d", + 893 => x"84", + 894 => x"3f", + 895 => x"33", + 896 => x"2e", + 897 => x"b4", + 898 => x"92", + 899 => x"ac", + 900 => x"3f", + 901 => x"33", + 902 => x"2e", + 903 => x"c6", + 904 => x"91", + 905 => x"52", + 906 => x"51", + 907 => x"91", + 908 => x"54", + 909 => x"92", + 910 => x"f0", + 911 => x"c6", + 912 => x"91", + 913 => x"89", + 914 => x"c7", + 915 => x"73", + 916 => x"c7", + 917 => x"73", + 918 => x"38", + 919 => x"08", + 920 => x"f4", + 921 => x"b5", + 922 => x"96", + 923 => x"95", + 924 => x"80", + 925 => x"91", + 926 => x"83", + 927 => x"c7", + 928 => x"73", + 929 => x"38", + 930 => x"51", + 931 => x"91", + 932 => x"54", + 933 => x"88", + 934 => x"cc", + 935 => x"3f", + 936 => x"33", + 937 => x"2e", + 938 => x"c7", + 939 => x"91", + 940 => x"88", + 941 => x"c7", + 942 => x"73", + 943 => x"38", + 944 => x"51", + 945 => x"91", + 946 => x"54", + 947 => x"8d", + 948 => x"9c", + 949 => x"b6", + 950 => x"a6", + 951 => x"b0", + 952 => x"3f", + 953 => x"08", + 954 => x"bc", + 955 => x"3f", + 956 => x"08", + 957 => x"e4", + 958 => x"3f", + 959 => x"08", + 960 => x"8c", + 961 => x"3f", + 962 => x"22", + 963 => x"b4", + 964 => x"3f", + 965 => x"08", + 966 => x"dc", + 967 => x"3f", + 968 => x"04", + 969 => x"02", + 970 => x"ff", + 971 => x"84", + 972 => x"71", + 973 => x"0b", + 974 => x"05", + 975 => x"04", + 976 => x"51", + 977 => x"b8", + 978 => x"39", + 979 => x"51", + 980 => x"b8", + 981 => x"39", + 982 => x"51", + 983 => x"b8", + 984 => x"9f", + 985 => x"0d", + 986 => x"80", + 987 => x"0b", + 988 => x"84", + 989 => x"3d", + 990 => x"96", + 991 => x"52", + 992 => x"0c", + 993 => x"70", + 994 => x"0c", + 995 => x"3d", + 996 => x"3d", + 997 => x"96", + 998 => x"91", + 999 => x"52", + 1000 => x"73", + 1001 => x"c7", + 1002 => x"70", + 1003 => x"0c", + 1004 => x"83", + 1005 => x"91", + 1006 => x"87", + 1007 => x"0c", + 1008 => x"0d", + 1009 => x"33", + 1010 => x"2e", + 1011 => x"85", + 1012 => x"ed", + 1013 => x"a0", + 1014 => x"80", + 1015 => x"72", + 1016 => x"ca", + 1017 => x"05", + 1018 => x"0c", + 1019 => x"ca", + 1020 => x"71", + 1021 => x"38", + 1022 => x"2d", + 1023 => x"04", + 1024 => x"02", + 1025 => x"91", + 1026 => x"76", + 1027 => x"0c", + 1028 => x"ad", + 1029 => x"ca", + 1030 => x"3d", + 1031 => x"3d", + 1032 => x"73", + 1033 => x"ff", + 1034 => x"71", + 1035 => x"38", + 1036 => x"06", + 1037 => x"54", + 1038 => x"e7", + 1039 => x"0d", + 1040 => x"0d", + 1041 => x"98", + 1042 => x"ca", + 1043 => x"54", + 1044 => x"81", + 1045 => x"53", + 1046 => x"8e", + 1047 => x"ff", + 1048 => x"14", + 1049 => x"3f", + 1050 => x"91", + 1051 => x"86", + 1052 => x"ec", + 1053 => x"68", + 1054 => x"70", + 1055 => x"33", + 1056 => x"2e", + 1057 => x"75", + 1058 => x"81", + 1059 => x"38", + 1060 => x"70", + 1061 => x"33", + 1062 => x"75", + 1063 => x"81", + 1064 => x"81", + 1065 => x"75", + 1066 => x"81", + 1067 => x"82", + 1068 => x"81", + 1069 => x"56", + 1070 => x"09", + 1071 => x"38", + 1072 => x"71", + 1073 => x"81", + 1074 => x"59", + 1075 => x"9d", + 1076 => x"53", + 1077 => x"95", + 1078 => x"29", + 1079 => x"76", + 1080 => x"79", + 1081 => x"5b", + 1082 => x"e5", + 1083 => x"ec", + 1084 => x"70", + 1085 => x"25", + 1086 => x"32", + 1087 => x"72", + 1088 => x"73", + 1089 => x"58", + 1090 => x"73", + 1091 => x"38", + 1092 => x"79", + 1093 => x"5b", + 1094 => x"75", + 1095 => x"de", + 1096 => x"80", + 1097 => x"89", + 1098 => x"70", + 1099 => x"55", + 1100 => x"cf", + 1101 => x"38", + 1102 => x"24", + 1103 => x"80", + 1104 => x"8e", + 1105 => x"c3", + 1106 => x"73", + 1107 => x"81", + 1108 => x"99", + 1109 => x"c4", + 1110 => x"38", + 1111 => x"73", + 1112 => x"81", + 1113 => x"80", + 1114 => x"38", + 1115 => x"2e", + 1116 => x"f9", + 1117 => x"d8", + 1118 => x"38", + 1119 => x"77", + 1120 => x"08", + 1121 => x"80", + 1122 => x"55", + 1123 => x"8d", + 1124 => x"70", + 1125 => x"51", + 1126 => x"f5", + 1127 => x"2a", + 1128 => x"74", + 1129 => x"53", + 1130 => x"8f", + 1131 => x"fc", + 1132 => x"81", + 1133 => x"80", + 1134 => x"73", + 1135 => x"3f", + 1136 => x"56", + 1137 => x"27", + 1138 => x"a0", + 1139 => x"3f", + 1140 => x"84", + 1141 => x"33", + 1142 => x"93", + 1143 => x"95", + 1144 => x"91", + 1145 => x"8d", + 1146 => x"89", + 1147 => x"fb", + 1148 => x"86", + 1149 => x"2a", + 1150 => x"51", + 1151 => x"2e", + 1152 => x"84", + 1153 => x"86", + 1154 => x"78", + 1155 => x"08", + 1156 => x"32", + 1157 => x"72", + 1158 => x"51", + 1159 => x"74", + 1160 => x"38", + 1161 => x"88", + 1162 => x"7a", + 1163 => x"55", + 1164 => x"3d", + 1165 => x"52", + 1166 => x"e0", + 1167 => x"88", + 1168 => x"06", + 1169 => x"52", + 1170 => x"3f", + 1171 => x"08", + 1172 => x"27", + 1173 => x"14", + 1174 => x"f8", + 1175 => x"87", + 1176 => x"81", + 1177 => x"b0", + 1178 => x"7d", + 1179 => x"5f", + 1180 => x"75", + 1181 => x"07", + 1182 => x"54", + 1183 => x"26", + 1184 => x"ff", + 1185 => x"84", + 1186 => x"06", + 1187 => x"80", + 1188 => x"96", + 1189 => x"e0", + 1190 => x"73", + 1191 => x"57", + 1192 => x"06", + 1193 => x"54", + 1194 => x"a0", + 1195 => x"2a", + 1196 => x"54", + 1197 => x"38", + 1198 => x"76", + 1199 => x"38", + 1200 => x"fd", + 1201 => x"06", + 1202 => x"38", + 1203 => x"56", + 1204 => x"26", + 1205 => x"3d", + 1206 => x"05", + 1207 => x"ff", + 1208 => x"53", + 1209 => x"d9", + 1210 => x"38", + 1211 => x"56", + 1212 => x"27", + 1213 => x"a0", + 1214 => x"3f", + 1215 => x"3d", + 1216 => x"3d", + 1217 => x"70", + 1218 => x"52", + 1219 => x"73", + 1220 => x"3f", + 1221 => x"04", + 1222 => x"74", + 1223 => x"0c", + 1224 => x"05", + 1225 => x"fa", + 1226 => x"ca", + 1227 => x"80", + 1228 => x"0b", + 1229 => x"0c", + 1230 => x"04", + 1231 => x"91", + 1232 => x"76", + 1233 => x"0c", + 1234 => x"05", + 1235 => x"53", + 1236 => x"72", + 1237 => x"0c", + 1238 => x"04", + 1239 => x"77", + 1240 => x"9c", + 1241 => x"54", + 1242 => x"54", + 1243 => x"80", + 1244 => x"ca", + 1245 => x"71", + 1246 => x"88", + 1247 => x"06", + 1248 => x"2e", + 1249 => x"72", + 1250 => x"38", + 1251 => x"70", + 1252 => x"25", + 1253 => x"73", + 1254 => x"38", + 1255 => x"86", + 1256 => x"54", + 1257 => x"73", + 1258 => x"ff", + 1259 => x"72", + 1260 => x"74", + 1261 => x"72", + 1262 => x"54", + 1263 => x"81", + 1264 => x"39", + 1265 => x"80", + 1266 => x"51", + 1267 => x"81", + 1268 => x"ca", + 1269 => x"3d", + 1270 => x"3d", + 1271 => x"9c", + 1272 => x"ca", + 1273 => x"53", + 1274 => x"fe", + 1275 => x"91", + 1276 => x"84", + 1277 => x"f8", + 1278 => x"7c", + 1279 => x"70", + 1280 => x"75", + 1281 => x"55", + 1282 => x"2e", + 1283 => x"87", + 1284 => x"76", + 1285 => x"73", + 1286 => x"81", + 1287 => x"81", + 1288 => x"77", + 1289 => x"70", + 1290 => x"58", + 1291 => x"09", + 1292 => x"c2", + 1293 => x"81", + 1294 => x"75", + 1295 => x"55", + 1296 => x"e2", + 1297 => x"90", + 1298 => x"f8", + 1299 => x"8f", + 1300 => x"81", + 1301 => x"75", + 1302 => x"55", + 1303 => x"81", + 1304 => x"27", + 1305 => x"d0", + 1306 => x"55", + 1307 => x"73", + 1308 => x"80", + 1309 => x"14", + 1310 => x"72", + 1311 => x"e0", + 1312 => x"80", + 1313 => x"39", + 1314 => x"55", + 1315 => x"80", + 1316 => x"e0", + 1317 => x"38", + 1318 => x"81", + 1319 => x"53", + 1320 => x"81", + 1321 => x"53", + 1322 => x"8e", + 1323 => x"70", + 1324 => x"55", + 1325 => x"27", + 1326 => x"77", + 1327 => x"74", + 1328 => x"76", + 1329 => x"77", + 1330 => x"70", + 1331 => x"55", + 1332 => x"77", + 1333 => x"38", + 1334 => x"74", + 1335 => x"55", + 1336 => x"88", + 1337 => x"0d", + 1338 => x"0d", + 1339 => x"56", + 1340 => x"0c", + 1341 => x"70", + 1342 => x"73", + 1343 => x"81", + 1344 => x"81", + 1345 => x"ed", + 1346 => x"2e", + 1347 => x"8e", + 1348 => x"08", + 1349 => x"76", + 1350 => x"56", + 1351 => x"b0", + 1352 => x"06", + 1353 => x"75", + 1354 => x"76", + 1355 => x"70", + 1356 => x"73", + 1357 => x"8b", + 1358 => x"73", + 1359 => x"85", + 1360 => x"82", + 1361 => x"76", + 1362 => x"70", + 1363 => x"ac", + 1364 => x"a0", + 1365 => x"fa", + 1366 => x"53", + 1367 => x"57", + 1368 => x"98", + 1369 => x"39", + 1370 => x"80", + 1371 => x"26", + 1372 => x"86", + 1373 => x"80", + 1374 => x"57", + 1375 => x"74", + 1376 => x"38", + 1377 => x"27", + 1378 => x"14", + 1379 => x"06", + 1380 => x"14", + 1381 => x"06", + 1382 => x"74", + 1383 => x"f9", + 1384 => x"ff", + 1385 => x"89", + 1386 => x"38", + 1387 => x"c5", + 1388 => x"29", + 1389 => x"81", + 1390 => x"76", + 1391 => x"56", + 1392 => x"ba", + 1393 => x"2e", + 1394 => x"30", + 1395 => x"0c", + 1396 => x"91", + 1397 => x"8a", + 1398 => x"ff", + 1399 => x"8f", + 1400 => x"81", + 1401 => x"26", + 1402 => x"c7", + 1403 => x"52", + 1404 => x"88", + 1405 => x"0d", + 1406 => x"0d", + 1407 => x"33", + 1408 => x"9f", + 1409 => x"53", + 1410 => x"81", + 1411 => x"38", + 1412 => x"87", + 1413 => x"11", + 1414 => x"54", + 1415 => x"84", + 1416 => x"54", + 1417 => x"87", + 1418 => x"11", + 1419 => x"0c", + 1420 => x"c0", + 1421 => x"70", + 1422 => x"70", + 1423 => x"51", + 1424 => x"8a", + 1425 => x"98", + 1426 => x"70", + 1427 => x"08", + 1428 => x"06", + 1429 => x"38", + 1430 => x"8c", + 1431 => x"80", + 1432 => x"71", + 1433 => x"14", + 1434 => x"a4", + 1435 => x"70", + 1436 => x"0c", + 1437 => x"04", + 1438 => x"60", + 1439 => x"8c", + 1440 => x"33", + 1441 => x"5b", + 1442 => x"5a", + 1443 => x"91", + 1444 => x"81", + 1445 => x"52", + 1446 => x"38", + 1447 => x"84", + 1448 => x"92", + 1449 => x"c0", + 1450 => x"87", + 1451 => x"13", + 1452 => x"57", + 1453 => x"0b", + 1454 => x"8c", + 1455 => x"0c", + 1456 => x"75", + 1457 => x"2a", + 1458 => x"51", + 1459 => x"80", + 1460 => x"7b", + 1461 => x"7b", + 1462 => x"5d", + 1463 => x"59", + 1464 => x"06", + 1465 => x"73", + 1466 => x"81", + 1467 => x"ff", + 1468 => x"72", + 1469 => x"38", + 1470 => x"8c", + 1471 => x"c3", + 1472 => x"98", + 1473 => x"71", + 1474 => x"38", + 1475 => x"2e", + 1476 => x"76", + 1477 => x"92", + 1478 => x"72", + 1479 => x"06", + 1480 => x"f7", + 1481 => x"5a", + 1482 => x"80", + 1483 => x"70", + 1484 => x"5a", + 1485 => x"80", + 1486 => x"73", + 1487 => x"06", + 1488 => x"38", + 1489 => x"fe", + 1490 => x"fc", + 1491 => x"52", + 1492 => x"83", + 1493 => x"71", + 1494 => x"ca", + 1495 => x"3d", + 1496 => x"3d", + 1497 => x"64", + 1498 => x"bf", + 1499 => x"40", + 1500 => x"59", + 1501 => x"58", + 1502 => x"91", + 1503 => x"81", + 1504 => x"52", + 1505 => x"09", + 1506 => x"b1", + 1507 => x"84", + 1508 => x"92", + 1509 => x"c0", + 1510 => x"87", + 1511 => x"13", + 1512 => x"56", + 1513 => x"87", + 1514 => x"0c", + 1515 => x"82", + 1516 => x"58", + 1517 => x"84", + 1518 => x"06", + 1519 => x"71", + 1520 => x"38", + 1521 => x"05", + 1522 => x"0c", + 1523 => x"73", + 1524 => x"81", + 1525 => x"71", + 1526 => x"38", + 1527 => x"8c", + 1528 => x"d0", + 1529 => x"98", + 1530 => x"71", + 1531 => x"38", + 1532 => x"2e", + 1533 => x"76", + 1534 => x"92", + 1535 => x"72", + 1536 => x"06", + 1537 => x"f7", + 1538 => x"59", + 1539 => x"1a", + 1540 => x"06", + 1541 => x"59", + 1542 => x"80", + 1543 => x"73", + 1544 => x"06", + 1545 => x"38", + 1546 => x"fe", + 1547 => x"fc", + 1548 => x"52", + 1549 => x"83", + 1550 => x"71", + 1551 => x"ca", + 1552 => x"3d", + 1553 => x"3d", + 1554 => x"84", + 1555 => x"33", + 1556 => x"b7", + 1557 => x"54", + 1558 => x"fa", + 1559 => x"ca", + 1560 => x"06", + 1561 => x"72", + 1562 => x"85", + 1563 => x"98", + 1564 => x"56", + 1565 => x"80", + 1566 => x"76", + 1567 => x"74", + 1568 => x"c0", + 1569 => x"54", + 1570 => x"2e", + 1571 => x"d4", + 1572 => x"2e", + 1573 => x"80", + 1574 => x"08", + 1575 => x"70", + 1576 => x"51", + 1577 => x"2e", + 1578 => x"c0", + 1579 => x"52", + 1580 => x"87", + 1581 => x"08", + 1582 => x"38", + 1583 => x"87", + 1584 => x"14", + 1585 => x"70", + 1586 => x"52", + 1587 => x"96", + 1588 => x"92", + 1589 => x"0a", + 1590 => x"39", + 1591 => x"0c", + 1592 => x"39", + 1593 => x"54", + 1594 => x"88", + 1595 => x"0d", + 1596 => x"0d", + 1597 => x"33", + 1598 => x"88", + 1599 => x"ca", + 1600 => x"51", + 1601 => x"04", + 1602 => x"75", + 1603 => x"82", + 1604 => x"90", + 1605 => x"2b", + 1606 => x"33", + 1607 => x"88", + 1608 => x"71", + 1609 => x"88", + 1610 => x"54", + 1611 => x"85", + 1612 => x"ff", + 1613 => x"02", + 1614 => x"05", + 1615 => x"70", + 1616 => x"05", + 1617 => x"88", + 1618 => x"72", + 1619 => x"0d", + 1620 => x"0d", + 1621 => x"52", + 1622 => x"81", + 1623 => x"70", + 1624 => x"70", + 1625 => x"05", + 1626 => x"88", + 1627 => x"72", + 1628 => x"54", + 1629 => x"2a", + 1630 => x"34", + 1631 => x"04", + 1632 => x"76", + 1633 => x"54", + 1634 => x"2e", + 1635 => x"70", + 1636 => x"33", + 1637 => x"05", + 1638 => x"11", + 1639 => x"84", + 1640 => x"fe", + 1641 => x"77", + 1642 => x"53", + 1643 => x"81", + 1644 => x"ff", + 1645 => x"f4", + 1646 => x"0d", + 1647 => x"0d", + 1648 => x"56", + 1649 => x"70", + 1650 => x"33", + 1651 => x"05", + 1652 => x"71", + 1653 => x"56", + 1654 => x"72", + 1655 => x"38", + 1656 => x"e2", + 1657 => x"ca", + 1658 => x"3d", + 1659 => x"3d", + 1660 => x"54", + 1661 => x"71", + 1662 => x"38", + 1663 => x"70", + 1664 => x"f3", + 1665 => x"91", + 1666 => x"84", + 1667 => x"80", + 1668 => x"88", + 1669 => x"0b", + 1670 => x"0c", + 1671 => x"0d", + 1672 => x"0b", + 1673 => x"56", + 1674 => x"2e", + 1675 => x"81", + 1676 => x"08", + 1677 => x"70", + 1678 => x"33", + 1679 => x"a2", + 1680 => x"88", + 1681 => x"09", + 1682 => x"38", + 1683 => x"08", + 1684 => x"b0", + 1685 => x"a4", + 1686 => x"9c", + 1687 => x"56", + 1688 => x"27", + 1689 => x"16", + 1690 => x"82", + 1691 => x"06", + 1692 => x"54", + 1693 => x"78", + 1694 => x"33", + 1695 => x"3f", + 1696 => x"5a", + 1697 => x"88", + 1698 => x"0d", + 1699 => x"0d", + 1700 => x"56", + 1701 => x"b0", + 1702 => x"af", + 1703 => x"fe", + 1704 => x"ca", + 1705 => x"91", + 1706 => x"9f", + 1707 => x"74", + 1708 => x"52", + 1709 => x"51", + 1710 => x"91", + 1711 => x"80", + 1712 => x"ff", + 1713 => x"74", + 1714 => x"76", + 1715 => x"0c", + 1716 => x"04", + 1717 => x"7a", + 1718 => x"fe", + 1719 => x"ca", + 1720 => x"91", + 1721 => x"81", + 1722 => x"33", + 1723 => x"2e", + 1724 => x"80", + 1725 => x"17", + 1726 => x"81", + 1727 => x"06", + 1728 => x"84", + 1729 => x"ca", + 1730 => x"b4", + 1731 => x"56", + 1732 => x"82", + 1733 => x"84", + 1734 => x"fc", + 1735 => x"8b", + 1736 => x"52", + 1737 => x"a9", + 1738 => x"85", + 1739 => x"84", + 1740 => x"fc", + 1741 => x"17", + 1742 => x"9c", + 1743 => x"91", + 1744 => x"08", + 1745 => x"17", + 1746 => x"3f", + 1747 => x"81", + 1748 => x"19", + 1749 => x"53", + 1750 => x"17", + 1751 => x"82", + 1752 => x"18", + 1753 => x"80", + 1754 => x"33", + 1755 => x"3f", + 1756 => x"08", + 1757 => x"38", + 1758 => x"91", + 1759 => x"8a", + 1760 => x"fb", + 1761 => x"fe", + 1762 => x"08", + 1763 => x"56", + 1764 => x"74", + 1765 => x"38", + 1766 => x"75", + 1767 => x"16", + 1768 => x"53", + 1769 => x"88", + 1770 => x"0d", + 1771 => x"0d", + 1772 => x"08", + 1773 => x"81", + 1774 => x"df", + 1775 => x"15", + 1776 => x"d7", + 1777 => x"33", + 1778 => x"82", + 1779 => x"38", + 1780 => x"89", + 1781 => x"2e", + 1782 => x"bf", + 1783 => x"2e", + 1784 => x"81", + 1785 => x"81", + 1786 => x"89", + 1787 => x"08", + 1788 => x"52", + 1789 => x"3f", + 1790 => x"08", + 1791 => x"74", + 1792 => x"14", + 1793 => x"81", + 1794 => x"2a", + 1795 => x"05", + 1796 => x"57", + 1797 => x"f5", + 1798 => x"88", + 1799 => x"38", + 1800 => x"06", + 1801 => x"33", + 1802 => x"78", + 1803 => x"06", + 1804 => x"5c", + 1805 => x"53", + 1806 => x"38", + 1807 => x"06", + 1808 => x"39", + 1809 => x"a4", + 1810 => x"52", + 1811 => x"bd", + 1812 => x"88", + 1813 => x"38", + 1814 => x"fe", + 1815 => x"b4", + 1816 => x"8d", + 1817 => x"88", + 1818 => x"ff", + 1819 => x"39", + 1820 => x"a4", + 1821 => x"52", + 1822 => x"91", + 1823 => x"88", + 1824 => x"76", + 1825 => x"fc", + 1826 => x"b4", + 1827 => x"f8", + 1828 => x"88", + 1829 => x"06", + 1830 => x"81", + 1831 => x"ca", + 1832 => x"3d", + 1833 => x"3d", + 1834 => x"7e", + 1835 => x"82", + 1836 => x"27", + 1837 => x"76", + 1838 => x"27", + 1839 => x"75", + 1840 => x"79", + 1841 => x"38", + 1842 => x"89", + 1843 => x"2e", + 1844 => x"80", + 1845 => x"2e", + 1846 => x"81", + 1847 => x"81", + 1848 => x"89", + 1849 => x"08", + 1850 => x"52", + 1851 => x"3f", + 1852 => x"08", + 1853 => x"88", + 1854 => x"38", + 1855 => x"06", + 1856 => x"81", + 1857 => x"06", + 1858 => x"77", + 1859 => x"2e", + 1860 => x"84", + 1861 => x"06", + 1862 => x"06", + 1863 => x"53", + 1864 => x"81", + 1865 => x"34", + 1866 => x"a4", + 1867 => x"52", + 1868 => x"d9", + 1869 => x"88", + 1870 => x"ca", + 1871 => x"94", + 1872 => x"ff", + 1873 => x"05", + 1874 => x"54", + 1875 => x"38", + 1876 => x"74", + 1877 => x"06", + 1878 => x"07", + 1879 => x"74", + 1880 => x"39", + 1881 => x"a4", + 1882 => x"52", + 1883 => x"9d", + 1884 => x"88", + 1885 => x"ca", + 1886 => x"d8", + 1887 => x"ff", + 1888 => x"76", + 1889 => x"06", + 1890 => x"05", + 1891 => x"3f", + 1892 => x"87", + 1893 => x"08", + 1894 => x"51", + 1895 => x"91", + 1896 => x"59", + 1897 => x"08", + 1898 => x"f0", + 1899 => x"82", + 1900 => x"06", + 1901 => x"05", + 1902 => x"54", + 1903 => x"3f", + 1904 => x"08", + 1905 => x"74", + 1906 => x"51", + 1907 => x"81", + 1908 => x"34", + 1909 => x"88", + 1910 => x"0d", + 1911 => x"0d", + 1912 => x"72", + 1913 => x"56", + 1914 => x"27", + 1915 => x"98", + 1916 => x"9d", + 1917 => x"2e", + 1918 => x"53", + 1919 => x"51", + 1920 => x"91", + 1921 => x"54", + 1922 => x"08", + 1923 => x"93", + 1924 => x"80", + 1925 => x"54", + 1926 => x"91", + 1927 => x"54", + 1928 => x"74", + 1929 => x"fb", + 1930 => x"ca", + 1931 => x"91", + 1932 => x"80", + 1933 => x"38", + 1934 => x"08", + 1935 => x"38", + 1936 => x"08", + 1937 => x"38", + 1938 => x"52", + 1939 => x"d6", + 1940 => x"88", + 1941 => x"98", + 1942 => x"11", + 1943 => x"57", + 1944 => x"74", + 1945 => x"81", + 1946 => x"0c", + 1947 => x"81", + 1948 => x"84", + 1949 => x"55", + 1950 => x"ff", + 1951 => x"54", + 1952 => x"88", + 1953 => x"0d", + 1954 => x"0d", + 1955 => x"08", + 1956 => x"79", + 1957 => x"17", + 1958 => x"80", + 1959 => x"98", + 1960 => x"26", + 1961 => x"58", + 1962 => x"52", + 1963 => x"fd", + 1964 => x"74", + 1965 => x"08", + 1966 => x"38", + 1967 => x"08", + 1968 => x"88", + 1969 => x"82", + 1970 => x"17", + 1971 => x"88", + 1972 => x"c7", + 1973 => x"90", + 1974 => x"56", + 1975 => x"2e", + 1976 => x"77", + 1977 => x"81", + 1978 => x"38", + 1979 => x"98", + 1980 => x"26", + 1981 => x"56", + 1982 => x"51", + 1983 => x"80", + 1984 => x"88", + 1985 => x"09", + 1986 => x"38", + 1987 => x"08", + 1988 => x"88", + 1989 => x"30", + 1990 => x"80", + 1991 => x"07", + 1992 => x"08", + 1993 => x"55", + 1994 => x"ef", + 1995 => x"88", + 1996 => x"95", + 1997 => x"08", + 1998 => x"27", + 1999 => x"98", + 2000 => x"89", + 2001 => x"85", + 2002 => x"db", + 2003 => x"81", + 2004 => x"17", + 2005 => x"89", + 2006 => x"75", + 2007 => x"ac", + 2008 => x"7a", + 2009 => x"3f", + 2010 => x"08", + 2011 => x"38", + 2012 => x"ca", + 2013 => x"2e", + 2014 => x"86", + 2015 => x"88", + 2016 => x"ca", + 2017 => x"70", + 2018 => x"07", + 2019 => x"7c", + 2020 => x"55", + 2021 => x"f8", + 2022 => x"2e", + 2023 => x"ff", + 2024 => x"55", + 2025 => x"ff", + 2026 => x"76", + 2027 => x"3f", + 2028 => x"08", + 2029 => x"08", + 2030 => x"ca", + 2031 => x"80", + 2032 => x"55", + 2033 => x"94", + 2034 => x"2e", + 2035 => x"53", + 2036 => x"51", + 2037 => x"91", + 2038 => x"55", + 2039 => x"75", + 2040 => x"98", + 2041 => x"05", + 2042 => x"56", + 2043 => x"26", + 2044 => x"15", + 2045 => x"84", + 2046 => x"07", + 2047 => x"18", + 2048 => x"ff", + 2049 => x"2e", + 2050 => x"39", + 2051 => x"39", + 2052 => x"08", + 2053 => x"81", + 2054 => x"74", + 2055 => x"0c", + 2056 => x"04", + 2057 => x"7a", + 2058 => x"f3", + 2059 => x"ca", + 2060 => x"81", + 2061 => x"88", + 2062 => x"38", + 2063 => x"51", + 2064 => x"91", + 2065 => x"91", + 2066 => x"b0", + 2067 => x"84", + 2068 => x"52", + 2069 => x"52", + 2070 => x"3f", + 2071 => x"39", + 2072 => x"8a", + 2073 => x"75", + 2074 => x"38", + 2075 => x"19", + 2076 => x"81", + 2077 => x"ed", + 2078 => x"ca", + 2079 => x"2e", + 2080 => x"15", + 2081 => x"70", + 2082 => x"07", + 2083 => x"53", + 2084 => x"75", + 2085 => x"0c", + 2086 => x"04", + 2087 => x"7a", + 2088 => x"58", + 2089 => x"f0", + 2090 => x"80", + 2091 => x"9f", + 2092 => x"80", + 2093 => x"90", + 2094 => x"17", + 2095 => x"aa", + 2096 => x"53", + 2097 => x"88", + 2098 => x"08", + 2099 => x"38", + 2100 => x"53", + 2101 => x"17", + 2102 => x"72", + 2103 => x"fe", + 2104 => x"08", + 2105 => x"80", + 2106 => x"16", + 2107 => x"2b", + 2108 => x"75", + 2109 => x"73", + 2110 => x"f5", + 2111 => x"ca", + 2112 => x"91", + 2113 => x"ff", + 2114 => x"81", + 2115 => x"88", + 2116 => x"38", + 2117 => x"91", + 2118 => x"26", + 2119 => x"58", + 2120 => x"73", + 2121 => x"39", + 2122 => x"51", + 2123 => x"91", + 2124 => x"98", + 2125 => x"94", + 2126 => x"17", + 2127 => x"58", + 2128 => x"9a", + 2129 => x"81", + 2130 => x"74", + 2131 => x"98", + 2132 => x"83", + 2133 => x"b4", + 2134 => x"0c", + 2135 => x"91", + 2136 => x"8a", + 2137 => x"f8", + 2138 => x"70", + 2139 => x"08", + 2140 => x"57", + 2141 => x"0a", + 2142 => x"38", + 2143 => x"15", + 2144 => x"08", + 2145 => x"72", + 2146 => x"cb", + 2147 => x"ff", + 2148 => x"81", + 2149 => x"13", + 2150 => x"94", + 2151 => x"74", + 2152 => x"85", + 2153 => x"22", + 2154 => x"73", + 2155 => x"38", + 2156 => x"8a", + 2157 => x"05", + 2158 => x"06", + 2159 => x"8a", + 2160 => x"73", + 2161 => x"3f", + 2162 => x"08", + 2163 => x"81", + 2164 => x"88", + 2165 => x"ff", + 2166 => x"91", + 2167 => x"ff", + 2168 => x"38", + 2169 => x"91", + 2170 => x"26", + 2171 => x"7b", + 2172 => x"98", + 2173 => x"55", + 2174 => x"94", + 2175 => x"73", + 2176 => x"3f", + 2177 => x"08", + 2178 => x"91", + 2179 => x"80", + 2180 => x"38", + 2181 => x"ca", + 2182 => x"2e", + 2183 => x"55", + 2184 => x"08", + 2185 => x"38", + 2186 => x"08", + 2187 => x"fb", + 2188 => x"ca", + 2189 => x"38", + 2190 => x"0c", + 2191 => x"51", + 2192 => x"91", + 2193 => x"98", + 2194 => x"90", + 2195 => x"16", + 2196 => x"15", + 2197 => x"74", + 2198 => x"0c", + 2199 => x"04", + 2200 => x"7b", + 2201 => x"5b", + 2202 => x"52", + 2203 => x"ac", + 2204 => x"88", + 2205 => x"ca", + 2206 => x"ec", + 2207 => x"88", + 2208 => x"17", + 2209 => x"51", + 2210 => x"91", + 2211 => x"54", + 2212 => x"08", + 2213 => x"91", + 2214 => x"9c", + 2215 => x"33", + 2216 => x"72", + 2217 => x"09", + 2218 => x"38", + 2219 => x"ca", + 2220 => x"72", + 2221 => x"55", + 2222 => x"53", + 2223 => x"8e", + 2224 => x"56", + 2225 => x"09", + 2226 => x"38", + 2227 => x"ca", + 2228 => x"81", + 2229 => x"fd", + 2230 => x"ca", + 2231 => x"91", + 2232 => x"80", + 2233 => x"38", + 2234 => x"09", + 2235 => x"38", + 2236 => x"91", + 2237 => x"8b", + 2238 => x"fd", + 2239 => x"9a", + 2240 => x"eb", + 2241 => x"ca", + 2242 => x"ff", + 2243 => x"70", + 2244 => x"53", + 2245 => x"09", + 2246 => x"38", + 2247 => x"eb", + 2248 => x"ca", + 2249 => x"2b", + 2250 => x"72", + 2251 => x"0c", + 2252 => x"04", + 2253 => x"77", + 2254 => x"ff", + 2255 => x"9a", + 2256 => x"55", + 2257 => x"76", + 2258 => x"53", + 2259 => x"09", + 2260 => x"38", + 2261 => x"52", + 2262 => x"eb", + 2263 => x"3d", + 2264 => x"3d", + 2265 => x"5b", + 2266 => x"08", + 2267 => x"15", + 2268 => x"81", + 2269 => x"15", + 2270 => x"51", + 2271 => x"91", + 2272 => x"58", + 2273 => x"08", + 2274 => x"9c", + 2275 => x"33", + 2276 => x"86", + 2277 => x"80", + 2278 => x"13", + 2279 => x"06", + 2280 => x"06", + 2281 => x"72", + 2282 => x"91", + 2283 => x"53", + 2284 => x"2e", + 2285 => x"53", + 2286 => x"a9", + 2287 => x"74", + 2288 => x"72", + 2289 => x"38", + 2290 => x"99", + 2291 => x"88", + 2292 => x"06", + 2293 => x"88", + 2294 => x"06", + 2295 => x"54", + 2296 => x"a0", + 2297 => x"74", + 2298 => x"3f", + 2299 => x"08", + 2300 => x"88", + 2301 => x"98", + 2302 => x"fa", + 2303 => x"80", + 2304 => x"0c", + 2305 => x"88", + 2306 => x"0d", + 2307 => x"0d", + 2308 => x"57", + 2309 => x"73", + 2310 => x"3f", + 2311 => x"08", + 2312 => x"88", + 2313 => x"98", + 2314 => x"75", + 2315 => x"3f", + 2316 => x"08", + 2317 => x"88", + 2318 => x"a0", + 2319 => x"88", + 2320 => x"14", + 2321 => x"db", + 2322 => x"a0", + 2323 => x"14", + 2324 => x"ac", + 2325 => x"83", + 2326 => x"91", + 2327 => x"87", + 2328 => x"fd", + 2329 => x"70", + 2330 => x"08", + 2331 => x"55", + 2332 => x"3f", + 2333 => x"08", + 2334 => x"13", + 2335 => x"73", + 2336 => x"83", + 2337 => x"3d", + 2338 => x"3d", + 2339 => x"57", + 2340 => x"89", + 2341 => x"17", + 2342 => x"81", + 2343 => x"70", + 2344 => x"55", + 2345 => x"08", + 2346 => x"81", + 2347 => x"52", + 2348 => x"a8", + 2349 => x"2e", + 2350 => x"84", + 2351 => x"52", + 2352 => x"09", + 2353 => x"38", + 2354 => x"81", + 2355 => x"81", + 2356 => x"73", + 2357 => x"55", + 2358 => x"55", + 2359 => x"c5", + 2360 => x"88", + 2361 => x"0b", + 2362 => x"9c", + 2363 => x"8b", + 2364 => x"17", + 2365 => x"08", + 2366 => x"52", + 2367 => x"91", + 2368 => x"76", + 2369 => x"51", + 2370 => x"91", + 2371 => x"86", + 2372 => x"12", + 2373 => x"3f", + 2374 => x"08", + 2375 => x"88", + 2376 => x"f3", + 2377 => x"70", + 2378 => x"80", + 2379 => x"51", + 2380 => x"af", + 2381 => x"81", + 2382 => x"dc", + 2383 => x"74", + 2384 => x"38", + 2385 => x"88", + 2386 => x"39", + 2387 => x"80", + 2388 => x"56", + 2389 => x"af", + 2390 => x"06", + 2391 => x"56", + 2392 => x"32", + 2393 => x"80", + 2394 => x"51", + 2395 => x"dc", + 2396 => x"1c", + 2397 => x"33", + 2398 => x"9f", + 2399 => x"ff", + 2400 => x"1c", + 2401 => x"7a", + 2402 => x"3f", + 2403 => x"08", + 2404 => x"39", + 2405 => x"a0", + 2406 => x"5e", + 2407 => x"52", + 2408 => x"ff", + 2409 => x"59", + 2410 => x"33", + 2411 => x"ae", + 2412 => x"06", + 2413 => x"78", + 2414 => x"81", + 2415 => x"32", + 2416 => x"9f", + 2417 => x"26", + 2418 => x"53", + 2419 => x"73", + 2420 => x"17", + 2421 => x"34", + 2422 => x"db", + 2423 => x"32", + 2424 => x"9f", + 2425 => x"54", + 2426 => x"2e", + 2427 => x"80", + 2428 => x"75", + 2429 => x"bd", + 2430 => x"7e", + 2431 => x"a0", + 2432 => x"bd", + 2433 => x"82", + 2434 => x"18", + 2435 => x"1a", + 2436 => x"a0", + 2437 => x"fc", + 2438 => x"32", + 2439 => x"80", + 2440 => x"30", + 2441 => x"71", + 2442 => x"51", + 2443 => x"55", + 2444 => x"ac", + 2445 => x"81", + 2446 => x"78", + 2447 => x"51", + 2448 => x"af", + 2449 => x"06", + 2450 => x"55", + 2451 => x"32", + 2452 => x"80", + 2453 => x"51", + 2454 => x"db", + 2455 => x"39", + 2456 => x"09", + 2457 => x"38", + 2458 => x"7c", + 2459 => x"54", + 2460 => x"a2", + 2461 => x"32", + 2462 => x"ae", + 2463 => x"72", + 2464 => x"9f", + 2465 => x"51", + 2466 => x"74", + 2467 => x"88", + 2468 => x"fe", + 2469 => x"98", + 2470 => x"80", + 2471 => x"75", + 2472 => x"91", + 2473 => x"33", + 2474 => x"51", + 2475 => x"91", + 2476 => x"80", + 2477 => x"78", + 2478 => x"81", + 2479 => x"5a", + 2480 => x"d2", + 2481 => x"88", + 2482 => x"80", + 2483 => x"1c", + 2484 => x"27", + 2485 => x"79", + 2486 => x"74", + 2487 => x"7a", + 2488 => x"74", + 2489 => x"39", + 2490 => x"b8", + 2491 => x"fe", + 2492 => x"88", + 2493 => x"ff", + 2494 => x"73", + 2495 => x"38", + 2496 => x"81", + 2497 => x"54", + 2498 => x"75", + 2499 => x"17", + 2500 => x"39", + 2501 => x"0c", + 2502 => x"99", + 2503 => x"54", + 2504 => x"2e", + 2505 => x"84", + 2506 => x"34", + 2507 => x"76", + 2508 => x"8b", + 2509 => x"81", + 2510 => x"56", + 2511 => x"80", + 2512 => x"1b", + 2513 => x"08", + 2514 => x"51", + 2515 => x"91", + 2516 => x"56", + 2517 => x"08", + 2518 => x"98", + 2519 => x"76", + 2520 => x"3f", + 2521 => x"08", + 2522 => x"88", + 2523 => x"38", + 2524 => x"70", + 2525 => x"73", + 2526 => x"be", + 2527 => x"33", + 2528 => x"73", + 2529 => x"8b", + 2530 => x"83", + 2531 => x"06", + 2532 => x"73", + 2533 => x"53", + 2534 => x"51", + 2535 => x"91", + 2536 => x"80", + 2537 => x"75", + 2538 => x"f3", + 2539 => x"9f", + 2540 => x"1c", + 2541 => x"74", + 2542 => x"38", + 2543 => x"09", + 2544 => x"e7", + 2545 => x"2a", + 2546 => x"77", + 2547 => x"51", + 2548 => x"2e", + 2549 => x"81", + 2550 => x"80", + 2551 => x"38", + 2552 => x"ab", + 2553 => x"55", + 2554 => x"75", + 2555 => x"73", + 2556 => x"55", + 2557 => x"82", + 2558 => x"06", + 2559 => x"ab", + 2560 => x"33", + 2561 => x"70", + 2562 => x"55", + 2563 => x"2e", + 2564 => x"1b", + 2565 => x"06", + 2566 => x"52", + 2567 => x"db", + 2568 => x"88", + 2569 => x"0c", + 2570 => x"74", + 2571 => x"0c", + 2572 => x"04", + 2573 => x"7c", + 2574 => x"08", + 2575 => x"55", + 2576 => x"59", + 2577 => x"81", + 2578 => x"70", + 2579 => x"33", + 2580 => x"52", + 2581 => x"2e", + 2582 => x"ee", + 2583 => x"2e", + 2584 => x"81", + 2585 => x"33", + 2586 => x"81", + 2587 => x"52", + 2588 => x"26", + 2589 => x"14", + 2590 => x"06", + 2591 => x"52", + 2592 => x"80", + 2593 => x"0b", + 2594 => x"59", + 2595 => x"7a", + 2596 => x"70", + 2597 => x"33", + 2598 => x"05", + 2599 => x"9f", + 2600 => x"53", + 2601 => x"89", + 2602 => x"70", + 2603 => x"54", + 2604 => x"12", + 2605 => x"26", + 2606 => x"12", + 2607 => x"06", + 2608 => x"30", + 2609 => x"51", + 2610 => x"2e", + 2611 => x"85", + 2612 => x"be", + 2613 => x"74", + 2614 => x"30", + 2615 => x"9f", + 2616 => x"2a", + 2617 => x"54", + 2618 => x"2e", + 2619 => x"15", + 2620 => x"55", + 2621 => x"ff", + 2622 => x"39", + 2623 => x"86", + 2624 => x"7c", + 2625 => x"51", + 2626 => x"ca", + 2627 => x"70", + 2628 => x"0c", + 2629 => x"04", + 2630 => x"78", + 2631 => x"83", + 2632 => x"0b", + 2633 => x"79", + 2634 => x"e2", + 2635 => x"55", + 2636 => x"08", + 2637 => x"84", + 2638 => x"df", + 2639 => x"ca", + 2640 => x"ff", + 2641 => x"83", + 2642 => x"d4", + 2643 => x"81", + 2644 => x"38", + 2645 => x"17", + 2646 => x"74", + 2647 => x"09", + 2648 => x"38", + 2649 => x"81", + 2650 => x"30", + 2651 => x"79", + 2652 => x"54", + 2653 => x"74", + 2654 => x"09", + 2655 => x"38", + 2656 => x"b8", + 2657 => x"ea", + 2658 => x"b1", + 2659 => x"88", + 2660 => x"ca", + 2661 => x"2e", + 2662 => x"53", + 2663 => x"52", + 2664 => x"51", + 2665 => x"91", + 2666 => x"55", + 2667 => x"08", + 2668 => x"38", + 2669 => x"91", + 2670 => x"88", + 2671 => x"f2", + 2672 => x"02", + 2673 => x"cb", + 2674 => x"55", + 2675 => x"60", + 2676 => x"3f", + 2677 => x"08", + 2678 => x"80", + 2679 => x"88", + 2680 => x"fc", + 2681 => x"88", + 2682 => x"91", + 2683 => x"70", + 2684 => x"8c", + 2685 => x"2e", + 2686 => x"73", + 2687 => x"81", + 2688 => x"33", + 2689 => x"80", + 2690 => x"81", + 2691 => x"d7", + 2692 => x"ca", + 2693 => x"ff", + 2694 => x"06", + 2695 => x"98", + 2696 => x"2e", + 2697 => x"74", + 2698 => x"81", + 2699 => x"8a", + 2700 => x"ac", + 2701 => x"39", + 2702 => x"77", + 2703 => x"81", + 2704 => x"33", + 2705 => x"3f", + 2706 => x"08", + 2707 => x"70", + 2708 => x"55", + 2709 => x"86", + 2710 => x"80", + 2711 => x"74", + 2712 => x"81", + 2713 => x"8a", + 2714 => x"f4", + 2715 => x"53", + 2716 => x"fd", + 2717 => x"ca", + 2718 => x"ff", + 2719 => x"82", + 2720 => x"06", + 2721 => x"8c", + 2722 => x"58", + 2723 => x"f6", + 2724 => x"58", + 2725 => x"2e", + 2726 => x"fa", + 2727 => x"e8", + 2728 => x"88", + 2729 => x"78", + 2730 => x"5a", + 2731 => x"90", + 2732 => x"75", + 2733 => x"38", + 2734 => x"3d", + 2735 => x"70", + 2736 => x"08", + 2737 => x"7a", + 2738 => x"38", + 2739 => x"51", + 2740 => x"91", + 2741 => x"81", + 2742 => x"81", + 2743 => x"38", + 2744 => x"83", + 2745 => x"38", + 2746 => x"84", + 2747 => x"38", + 2748 => x"81", + 2749 => x"38", + 2750 => x"db", + 2751 => x"ca", + 2752 => x"ff", + 2753 => x"72", + 2754 => x"09", + 2755 => x"d0", + 2756 => x"14", + 2757 => x"3f", + 2758 => x"08", + 2759 => x"06", + 2760 => x"38", + 2761 => x"51", + 2762 => x"91", + 2763 => x"58", + 2764 => x"0c", + 2765 => x"33", + 2766 => x"80", + 2767 => x"ff", + 2768 => x"ff", + 2769 => x"55", + 2770 => x"81", + 2771 => x"38", + 2772 => x"06", + 2773 => x"80", + 2774 => x"52", + 2775 => x"8a", + 2776 => x"80", + 2777 => x"ff", + 2778 => x"53", + 2779 => x"86", + 2780 => x"83", + 2781 => x"c5", + 2782 => x"f5", + 2783 => x"88", + 2784 => x"ca", + 2785 => x"15", + 2786 => x"06", + 2787 => x"76", + 2788 => x"80", + 2789 => x"da", + 2790 => x"ca", + 2791 => x"ff", + 2792 => x"74", + 2793 => x"d4", + 2794 => x"dc", + 2795 => x"88", + 2796 => x"c2", + 2797 => x"b9", + 2798 => x"88", + 2799 => x"ff", + 2800 => x"56", + 2801 => x"83", + 2802 => x"14", + 2803 => x"71", + 2804 => x"5a", + 2805 => x"26", + 2806 => x"8a", + 2807 => x"74", + 2808 => x"ff", + 2809 => x"91", + 2810 => x"55", + 2811 => x"08", + 2812 => x"ec", + 2813 => x"88", + 2814 => x"ff", + 2815 => x"83", + 2816 => x"74", + 2817 => x"26", + 2818 => x"57", + 2819 => x"26", + 2820 => x"57", + 2821 => x"56", + 2822 => x"82", + 2823 => x"15", + 2824 => x"0c", + 2825 => x"0c", + 2826 => x"a4", + 2827 => x"1d", + 2828 => x"54", + 2829 => x"2e", + 2830 => x"af", + 2831 => x"14", + 2832 => x"3f", + 2833 => x"08", + 2834 => x"06", + 2835 => x"72", + 2836 => x"79", + 2837 => x"80", + 2838 => x"d9", + 2839 => x"ca", + 2840 => x"15", + 2841 => x"2b", + 2842 => x"8d", + 2843 => x"2e", + 2844 => x"77", + 2845 => x"0c", + 2846 => x"76", + 2847 => x"38", + 2848 => x"70", + 2849 => x"81", + 2850 => x"53", + 2851 => x"89", + 2852 => x"56", + 2853 => x"08", + 2854 => x"38", + 2855 => x"15", + 2856 => x"8c", + 2857 => x"80", + 2858 => x"34", + 2859 => x"09", + 2860 => x"92", + 2861 => x"14", + 2862 => x"3f", + 2863 => x"08", + 2864 => x"06", + 2865 => x"2e", + 2866 => x"80", + 2867 => x"1b", + 2868 => x"db", + 2869 => x"ca", + 2870 => x"ea", + 2871 => x"88", + 2872 => x"34", + 2873 => x"51", + 2874 => x"91", + 2875 => x"83", + 2876 => x"53", + 2877 => x"d5", + 2878 => x"06", + 2879 => x"b4", + 2880 => x"84", + 2881 => x"88", + 2882 => x"85", + 2883 => x"09", + 2884 => x"38", + 2885 => x"51", + 2886 => x"91", + 2887 => x"86", + 2888 => x"f2", + 2889 => x"06", + 2890 => x"9c", + 2891 => x"d8", + 2892 => x"88", + 2893 => x"0c", + 2894 => x"51", + 2895 => x"91", + 2896 => x"8c", + 2897 => x"74", + 2898 => x"b4", + 2899 => x"53", + 2900 => x"b4", + 2901 => x"15", + 2902 => x"94", + 2903 => x"56", + 2904 => x"88", + 2905 => x"0d", + 2906 => x"0d", + 2907 => x"55", + 2908 => x"b9", + 2909 => x"53", + 2910 => x"b1", + 2911 => x"52", + 2912 => x"a9", + 2913 => x"22", + 2914 => x"57", + 2915 => x"2e", + 2916 => x"99", + 2917 => x"33", + 2918 => x"3f", + 2919 => x"08", + 2920 => x"71", + 2921 => x"74", + 2922 => x"83", + 2923 => x"78", + 2924 => x"52", + 2925 => x"88", + 2926 => x"0d", + 2927 => x"0d", + 2928 => x"33", + 2929 => x"3d", + 2930 => x"56", + 2931 => x"8b", + 2932 => x"91", + 2933 => x"24", + 2934 => x"ca", + 2935 => x"29", + 2936 => x"05", + 2937 => x"55", + 2938 => x"84", + 2939 => x"34", + 2940 => x"80", + 2941 => x"80", + 2942 => x"75", + 2943 => x"75", + 2944 => x"38", + 2945 => x"3d", + 2946 => x"05", + 2947 => x"3f", + 2948 => x"08", + 2949 => x"ca", + 2950 => x"3d", + 2951 => x"3d", + 2952 => x"84", + 2953 => x"05", + 2954 => x"89", + 2955 => x"2e", + 2956 => x"77", + 2957 => x"54", + 2958 => x"05", + 2959 => x"84", + 2960 => x"f6", + 2961 => x"ca", + 2962 => x"91", + 2963 => x"84", + 2964 => x"5c", + 2965 => x"3d", + 2966 => x"ed", + 2967 => x"ca", + 2968 => x"91", + 2969 => x"92", + 2970 => x"d7", + 2971 => x"98", + 2972 => x"73", + 2973 => x"38", + 2974 => x"9c", + 2975 => x"80", + 2976 => x"38", + 2977 => x"95", + 2978 => x"2e", + 2979 => x"aa", + 2980 => x"ea", + 2981 => x"ca", + 2982 => x"9e", + 2983 => x"05", + 2984 => x"54", + 2985 => x"38", + 2986 => x"70", + 2987 => x"54", + 2988 => x"8e", + 2989 => x"83", + 2990 => x"88", + 2991 => x"83", + 2992 => x"83", + 2993 => x"06", + 2994 => x"80", + 2995 => x"38", + 2996 => x"51", + 2997 => x"91", + 2998 => x"56", + 2999 => x"0a", + 3000 => x"05", + 3001 => x"3f", + 3002 => x"0b", + 3003 => x"80", + 3004 => x"7a", + 3005 => x"3f", + 3006 => x"9c", + 3007 => x"d1", + 3008 => x"81", + 3009 => x"34", + 3010 => x"80", + 3011 => x"b0", + 3012 => x"54", + 3013 => x"52", + 3014 => x"05", + 3015 => x"3f", + 3016 => x"08", + 3017 => x"88", + 3018 => x"38", + 3019 => x"82", + 3020 => x"b2", + 3021 => x"84", + 3022 => x"06", + 3023 => x"73", + 3024 => x"38", + 3025 => x"ad", + 3026 => x"2a", + 3027 => x"51", + 3028 => x"2e", + 3029 => x"81", + 3030 => x"80", + 3031 => x"87", + 3032 => x"39", + 3033 => x"51", + 3034 => x"91", + 3035 => x"7b", + 3036 => x"12", + 3037 => x"91", + 3038 => x"81", + 3039 => x"83", + 3040 => x"06", + 3041 => x"80", + 3042 => x"77", + 3043 => x"58", + 3044 => x"08", + 3045 => x"63", + 3046 => x"63", + 3047 => x"57", + 3048 => x"91", + 3049 => x"91", + 3050 => x"88", + 3051 => x"9c", + 3052 => x"d2", + 3053 => x"ca", + 3054 => x"ca", + 3055 => x"1b", + 3056 => x"0c", + 3057 => x"22", + 3058 => x"77", + 3059 => x"80", + 3060 => x"34", + 3061 => x"1a", + 3062 => x"94", + 3063 => x"85", + 3064 => x"06", + 3065 => x"80", + 3066 => x"38", + 3067 => x"08", + 3068 => x"84", + 3069 => x"88", + 3070 => x"0c", + 3071 => x"70", + 3072 => x"52", + 3073 => x"39", + 3074 => x"51", + 3075 => x"91", + 3076 => x"57", + 3077 => x"08", + 3078 => x"38", + 3079 => x"ca", + 3080 => x"2e", + 3081 => x"83", + 3082 => x"75", + 3083 => x"74", + 3084 => x"07", + 3085 => x"54", + 3086 => x"8a", + 3087 => x"75", + 3088 => x"73", + 3089 => x"98", + 3090 => x"a9", + 3091 => x"ff", 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x"88", + 3151 => x"ff", + 3152 => x"ca", + 3153 => x"7c", + 3154 => x"57", + 3155 => x"80", + 3156 => x"1a", + 3157 => x"22", + 3158 => x"75", + 3159 => x"38", + 3160 => x"58", + 3161 => x"53", + 3162 => x"1b", + 3163 => x"88", + 3164 => x"88", + 3165 => x"38", + 3166 => x"33", + 3167 => x"80", + 3168 => x"b0", + 3169 => x"31", + 3170 => x"27", + 3171 => x"80", + 3172 => x"52", + 3173 => x"77", + 3174 => x"7d", + 3175 => x"e0", + 3176 => x"2b", + 3177 => x"76", + 3178 => x"94", + 3179 => x"ff", + 3180 => x"71", + 3181 => x"7b", + 3182 => x"38", + 3183 => x"19", + 3184 => x"51", + 3185 => x"91", + 3186 => x"fe", + 3187 => x"53", + 3188 => x"83", + 3189 => x"b4", + 3190 => x"51", + 3191 => x"7b", + 3192 => x"08", + 3193 => x"76", + 3194 => x"08", + 3195 => x"0c", + 3196 => x"f3", + 3197 => x"75", + 3198 => x"0c", + 3199 => x"04", + 3200 => x"60", + 3201 => x"40", + 3202 => x"80", + 3203 => x"3d", + 3204 => x"77", + 3205 => x"3f", + 3206 => x"08", + 3207 => x"88", + 3208 => x"91", + 3209 => x"74", + 3210 => x"38", + 3211 => x"b8", + 3212 => x"33", + 3213 => x"70", + 3214 => x"56", + 3215 => x"74", + 3216 => x"a4", + 3217 => x"82", + 3218 => x"34", + 3219 => x"98", + 3220 => x"91", + 3221 => x"56", + 3222 => x"94", + 3223 => x"11", + 3224 => x"76", + 3225 => x"75", + 3226 => x"80", + 3227 => x"38", + 3228 => x"70", + 3229 => x"56", + 3230 => x"fd", + 3231 => x"11", + 3232 => x"77", + 3233 => x"5c", + 3234 => x"38", + 3235 => x"88", + 3236 => x"74", + 3237 => x"52", + 3238 => x"18", + 3239 => x"51", + 3240 => x"91", + 3241 => x"55", + 3242 => x"08", + 3243 => x"ab", + 3244 => x"2e", + 3245 => x"74", + 3246 => x"95", + 3247 => x"19", + 3248 => x"08", + 3249 => x"88", + 3250 => x"55", + 3251 => x"9c", + 3252 => x"09", + 3253 => x"38", + 3254 => x"c1", + 3255 => x"88", + 3256 => x"38", + 3257 => x"52", + 3258 => x"97", + 3259 => x"88", + 3260 => x"fe", + 3261 => x"ca", + 3262 => x"7c", + 3263 => x"57", + 3264 => x"80", + 3265 => x"1b", + 3266 => x"22", + 3267 => x"75", + 3268 => x"38", + 3269 => x"59", + 3270 => x"53", + 3271 => x"1a", + 3272 => x"be", + 3273 => x"88", + 3274 => x"38", + 3275 => x"08", + 3276 => x"56", + 3277 => x"9b", + 3278 => x"53", + 3279 => x"77", + 3280 => x"7d", + 3281 => x"16", + 3282 => x"3f", + 3283 => x"0b", + 3284 => x"78", + 3285 => x"80", + 3286 => x"18", + 3287 => x"08", + 3288 => x"7e", + 3289 => x"3f", + 3290 => x"08", + 3291 => x"7e", + 3292 => x"0c", + 3293 => x"19", + 3294 => x"08", + 3295 => x"84", + 3296 => x"57", + 3297 => x"27", + 3298 => x"56", + 3299 => x"52", + 3300 => x"f9", + 3301 => x"88", + 3302 => x"38", + 3303 => x"52", + 3304 => x"83", + 3305 => x"b4", + 3306 => x"d4", + 3307 => x"81", + 3308 => x"34", + 3309 => x"7e", + 3310 => x"0c", + 3311 => x"1a", + 3312 => x"94", + 3313 => x"1b", + 3314 => x"5e", + 3315 => x"27", + 3316 => x"55", + 3317 => x"0c", + 3318 => x"90", + 3319 => x"c0", + 3320 => x"90", + 3321 => x"56", + 3322 => x"88", + 3323 => x"0d", + 3324 => x"0d", + 3325 => x"fc", + 3326 => x"52", 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x"91", + 3386 => x"83", + 3387 => x"ef", + 3388 => x"53", + 3389 => x"05", + 3390 => x"51", + 3391 => x"91", + 3392 => x"55", + 3393 => x"08", + 3394 => x"76", + 3395 => x"93", + 3396 => x"51", + 3397 => x"91", + 3398 => x"55", + 3399 => x"08", + 3400 => x"80", + 3401 => x"70", + 3402 => x"56", + 3403 => x"89", + 3404 => x"94", + 3405 => x"b2", + 3406 => x"05", + 3407 => x"2a", + 3408 => x"51", + 3409 => x"80", + 3410 => x"76", + 3411 => x"52", + 3412 => x"3f", + 3413 => x"08", + 3414 => x"8e", + 3415 => x"88", + 3416 => x"09", + 3417 => x"38", + 3418 => x"91", + 3419 => x"93", + 3420 => x"e4", + 3421 => x"6f", + 3422 => x"7a", + 3423 => x"9e", + 3424 => x"05", + 3425 => x"51", + 3426 => x"91", + 3427 => x"57", + 3428 => x"08", + 3429 => x"7b", + 3430 => x"94", + 3431 => x"55", + 3432 => x"73", + 3433 => x"ed", + 3434 => x"93", + 3435 => x"55", + 3436 => x"91", + 3437 => x"57", + 3438 => x"08", + 3439 => x"68", + 3440 => x"c9", + 3441 => x"ca", + 3442 => x"91", + 3443 => x"82", + 3444 => x"52", + 3445 => x"a3", + 3446 => x"88", + 3447 => x"52", + 3448 => x"b8", + 3449 => x"88", + 3450 => x"ca", + 3451 => x"a2", + 3452 => x"74", + 3453 => x"3f", + 3454 => x"08", + 3455 => x"88", + 3456 => x"69", + 3457 => x"d9", + 3458 => x"91", + 3459 => x"2e", + 3460 => x"52", + 3461 => x"cf", + 3462 => x"88", + 3463 => x"ca", + 3464 => x"2e", + 3465 => x"84", + 3466 => x"06", + 3467 => x"57", + 3468 => x"76", + 3469 => x"9e", + 3470 => x"05", + 3471 => x"dc", + 3472 => x"90", + 3473 => x"81", + 3474 => x"56", + 3475 => x"80", + 3476 => x"02", + 3477 => x"81", + 3478 => x"70", + 3479 => x"56", + 3480 => x"81", + 3481 => x"78", + 3482 => x"38", + 3483 => x"99", + 3484 => x"81", + 3485 => x"18", + 3486 => x"18", + 3487 => x"58", + 3488 => x"33", + 3489 => x"ee", + 3490 => x"6f", + 3491 => x"af", + 3492 => x"8d", + 3493 => x"2e", + 3494 => x"8a", + 3495 => x"6f", + 3496 => x"af", + 3497 => x"0b", + 3498 => x"33", + 3499 => x"91", + 3500 => x"70", + 3501 => x"52", + 3502 => x"56", + 3503 => x"8d", + 3504 => x"70", + 3505 => x"51", + 3506 => x"f5", + 3507 => x"54", + 3508 => x"a7", + 3509 => x"74", + 3510 => x"38", + 3511 => x"73", + 3512 => x"81", + 3513 => x"81", + 3514 => x"39", + 3515 => x"81", + 3516 => x"74", + 3517 => x"81", + 3518 => x"91", + 3519 => x"6e", + 3520 => x"59", + 3521 => x"7a", + 3522 => x"5c", + 3523 => x"26", + 3524 => x"7a", + 3525 => x"ca", + 3526 => x"3d", + 3527 => x"3d", + 3528 => x"8d", + 3529 => x"54", + 3530 => x"55", + 3531 => x"91", + 3532 => x"53", + 3533 => x"08", + 3534 => x"91", + 3535 => x"72", + 3536 => x"8c", + 3537 => x"73", + 3538 => x"38", + 3539 => x"70", + 3540 => x"81", + 3541 => x"57", + 3542 => x"73", + 3543 => x"08", + 3544 => x"94", + 3545 => x"75", + 3546 => x"97", + 3547 => x"11", + 3548 => x"2b", + 3549 => x"73", + 3550 => x"38", + 3551 => x"16", + 3552 => x"e5", + 3553 => x"88", + 3554 => x"78", + 3555 => x"55", + 3556 => x"d5", + 3557 => x"88", + 3558 => x"96", + 3559 => x"70", + 3560 => x"94", + 3561 => x"71", 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x"15", + 3621 => x"07", + 3622 => x"16", + 3623 => x"ff", + 3624 => x"80", + 3625 => x"77", + 3626 => x"2e", + 3627 => x"9c", + 3628 => x"53", + 3629 => x"88", + 3630 => x"0d", + 3631 => x"0d", + 3632 => x"54", + 3633 => x"81", + 3634 => x"53", + 3635 => x"05", + 3636 => x"84", + 3637 => x"e7", + 3638 => x"88", + 3639 => x"ca", + 3640 => x"ea", + 3641 => x"0c", + 3642 => x"51", + 3643 => x"91", + 3644 => x"55", + 3645 => x"08", + 3646 => x"ab", + 3647 => x"98", + 3648 => x"80", + 3649 => x"38", + 3650 => x"70", + 3651 => x"81", + 3652 => x"57", + 3653 => x"ad", + 3654 => x"08", + 3655 => x"d3", + 3656 => x"ca", + 3657 => x"17", + 3658 => x"86", + 3659 => x"17", + 3660 => x"75", + 3661 => x"3f", + 3662 => x"08", + 3663 => x"2e", + 3664 => x"85", + 3665 => x"86", + 3666 => x"2e", + 3667 => x"76", + 3668 => x"73", + 3669 => x"0c", + 3670 => x"04", + 3671 => x"76", + 3672 => x"05", + 3673 => x"53", + 3674 => x"91", + 3675 => x"87", + 3676 => x"88", + 3677 => x"86", + 3678 => x"fb", + 3679 => x"79", + 3680 => x"05", + 3681 => x"56", + 3682 => x"3f", + 3683 => x"08", + 3684 => x"88", + 3685 => x"38", + 3686 => x"91", + 3687 => x"52", + 3688 => x"f8", + 3689 => x"88", + 3690 => x"ca", + 3691 => x"88", + 3692 => x"51", + 3693 => x"91", + 3694 => x"53", + 3695 => x"08", + 3696 => x"81", + 3697 => x"80", + 3698 => x"91", + 3699 => x"a6", + 3700 => x"73", + 3701 => x"3f", + 3702 => x"51", + 3703 => x"91", + 3704 => x"84", + 3705 => x"70", + 3706 => x"2c", + 3707 => x"88", + 3708 => x"51", + 3709 => x"91", + 3710 => x"87", + 3711 => x"ee", + 3712 => x"57", + 3713 => x"3d", + 3714 => x"3d", + 3715 => x"af", + 3716 => x"88", + 3717 => x"ca", + 3718 => x"38", + 3719 => x"51", + 3720 => x"91", + 3721 => x"55", + 3722 => x"08", + 3723 => x"80", + 3724 => x"70", + 3725 => x"58", + 3726 => x"85", + 3727 => x"8d", + 3728 => x"2e", + 3729 => x"52", + 3730 => x"be", + 3731 => x"ca", + 3732 => x"3d", + 3733 => x"3d", + 3734 => x"55", + 3735 => x"92", + 3736 => x"52", + 3737 => x"de", + 3738 => x"ca", + 3739 => x"91", + 3740 => x"82", + 3741 => x"74", + 3742 => x"98", + 3743 => x"11", + 3744 => x"59", + 3745 => x"75", + 3746 => x"38", + 3747 => x"81", + 3748 => x"5b", + 3749 => x"82", + 3750 => x"39", + 3751 => x"08", + 3752 => x"59", + 3753 => x"09", + 3754 => x"38", + 3755 => x"57", + 3756 => x"3d", + 3757 => x"c1", + 3758 => x"ca", + 3759 => x"2e", + 3760 => x"ca", + 3761 => x"2e", + 3762 => x"ca", + 3763 => x"70", + 3764 => x"08", + 3765 => x"7a", + 3766 => x"7f", + 3767 => x"54", + 3768 => x"77", + 3769 => x"80", + 3770 => x"15", + 3771 => x"88", + 3772 => x"75", + 3773 => x"52", + 3774 => x"52", + 3775 => x"8d", + 3776 => x"88", + 3777 => x"ca", + 3778 => x"d6", + 3779 => x"33", + 3780 => x"1a", + 3781 => x"54", + 3782 => x"09", + 3783 => x"38", + 3784 => x"ff", + 3785 => x"91", + 3786 => x"83", + 3787 => x"70", + 3788 => x"25", + 3789 => x"59", + 3790 => x"9b", + 3791 => x"51", + 3792 => x"3f", + 3793 => x"08", + 3794 => x"70", + 3795 => x"25", + 3796 => x"59", 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x"34", + 3856 => x"91", + 3857 => x"89", + 3858 => x"e2", + 3859 => x"53", + 3860 => x"a4", + 3861 => x"3d", + 3862 => x"3f", + 3863 => x"08", + 3864 => x"88", + 3865 => x"38", + 3866 => x"3d", + 3867 => x"3d", + 3868 => x"d1", + 3869 => x"ca", + 3870 => x"91", + 3871 => x"81", + 3872 => x"80", + 3873 => x"70", + 3874 => x"81", + 3875 => x"56", + 3876 => x"81", + 3877 => x"98", + 3878 => x"74", + 3879 => x"38", + 3880 => x"05", + 3881 => x"06", + 3882 => x"55", + 3883 => x"38", + 3884 => x"51", + 3885 => x"91", + 3886 => x"74", + 3887 => x"81", + 3888 => x"56", + 3889 => x"80", + 3890 => x"54", + 3891 => x"08", + 3892 => x"2e", + 3893 => x"73", + 3894 => x"88", + 3895 => x"52", + 3896 => x"52", + 3897 => x"3f", + 3898 => x"08", + 3899 => x"88", + 3900 => x"38", + 3901 => x"08", + 3902 => x"cc", + 3903 => x"ca", + 3904 => x"91", + 3905 => x"86", + 3906 => x"80", + 3907 => x"ca", + 3908 => x"2e", + 3909 => x"ca", + 3910 => x"c0", + 3911 => x"ce", + 3912 => x"ca", + 3913 => x"ca", + 3914 => x"70", + 3915 => x"08", + 3916 => x"51", + 3917 => x"80", + 3918 => x"73", + 3919 => x"38", + 3920 => x"52", + 3921 => x"95", + 3922 => x"88", + 3923 => x"8c", + 3924 => x"ff", + 3925 => x"91", + 3926 => x"55", + 3927 => x"88", + 3928 => x"0d", + 3929 => x"0d", + 3930 => x"3d", + 3931 => x"9a", + 3932 => x"cb", + 3933 => x"88", + 3934 => x"ca", + 3935 => x"b0", + 3936 => x"69", + 3937 => x"70", + 3938 => x"97", + 3939 => x"88", + 3940 => x"ca", + 3941 => x"38", + 3942 => x"94", + 3943 => x"88", + 3944 => x"09", + 3945 => x"88", + 3946 => x"df", + 3947 => x"85", + 3948 => x"51", + 3949 => x"74", + 3950 => x"78", + 3951 => x"8a", + 3952 => x"57", + 3953 => x"91", + 3954 => x"75", + 3955 => x"ca", + 3956 => x"38", + 3957 => x"ca", + 3958 => x"2e", + 3959 => x"83", + 3960 => x"91", + 3961 => x"ff", + 3962 => x"06", + 3963 => x"54", + 3964 => x"73", + 3965 => x"91", + 3966 => x"52", + 3967 => x"a4", + 3968 => x"88", + 3969 => x"ca", + 3970 => x"9a", + 3971 => x"a0", + 3972 => x"51", + 3973 => x"3f", + 3974 => x"0b", + 3975 => x"78", + 3976 => x"bf", + 3977 => x"88", + 3978 => x"80", + 3979 => x"ff", + 3980 => x"75", + 3981 => x"11", + 3982 => x"f8", + 3983 => x"78", + 3984 => x"80", + 3985 => x"ff", + 3986 => x"78", + 3987 => x"80", + 3988 => x"7f", + 3989 => x"d4", + 3990 => x"c9", + 3991 => x"54", + 3992 => x"15", + 3993 => x"cb", + 3994 => x"ca", + 3995 => x"91", + 3996 => x"b2", + 3997 => x"b2", + 3998 => x"96", + 3999 => x"b5", + 4000 => x"53", + 4001 => x"51", + 4002 => x"64", + 4003 => x"8b", + 4004 => x"54", + 4005 => x"15", + 4006 => x"ff", + 4007 => x"91", + 4008 => x"54", + 4009 => x"53", + 4010 => x"51", + 4011 => x"3f", + 4012 => x"88", + 4013 => x"0d", + 4014 => x"0d", + 4015 => x"05", + 4016 => x"3f", + 4017 => x"3d", + 4018 => x"52", + 4019 => x"d5", + 4020 => x"ca", + 4021 => x"91", + 4022 => x"82", + 4023 => x"4d", + 4024 => x"52", + 4025 => x"52", + 4026 => x"3f", + 4027 => x"08", + 4028 => x"88", + 4029 => x"38", + 4030 => x"05", + 4031 => x"06", + 4032 => x"73", + 4033 => x"a0", + 4034 => x"08", + 4035 => x"ff", + 4036 => x"ff", + 4037 => x"ac", + 4038 => x"92", + 4039 => x"54", + 4040 => x"3f", + 4041 => x"52", + 4042 => x"f7", + 4043 => x"88", + 4044 => x"ca", + 4045 => x"38", + 4046 => x"09", + 4047 => x"38", + 4048 => x"08", + 4049 => x"88", + 4050 => x"39", + 4051 => x"08", + 4052 => x"81", + 4053 => x"38", + 4054 => x"b1", + 4055 => x"88", + 4056 => x"ca", + 4057 => x"c8", + 4058 => x"93", + 4059 => x"ff", + 4060 => x"8d", + 4061 => x"b4", + 4062 => x"af", + 4063 => x"17", + 4064 => x"33", + 4065 => x"70", + 4066 => x"55", + 4067 => x"38", + 4068 => x"54", + 4069 => x"34", + 4070 => x"0b", + 4071 => x"8b", + 4072 => x"84", + 4073 => x"06", + 4074 => x"73", + 4075 => x"e5", + 4076 => x"2e", + 4077 => x"75", + 4078 => x"c6", + 4079 => x"ca", + 4080 => x"78", + 4081 => x"bb", + 4082 => x"91", + 4083 => x"80", + 4084 => x"38", + 4085 => x"08", + 4086 => x"ff", + 4087 => x"91", + 4088 => x"79", + 4089 => x"58", + 4090 => x"ca", + 4091 => x"c0", + 4092 => x"33", + 4093 => x"2e", + 4094 => x"99", + 4095 => x"75", + 4096 => x"c6", + 4097 => x"54", + 4098 => x"15", + 4099 => x"91", + 4100 => x"9c", + 4101 => x"c8", + 4102 => x"ca", + 4103 => x"91", + 4104 => x"8c", + 4105 => x"ff", + 4106 => x"91", + 4107 => x"55", + 4108 => x"88", + 4109 => x"0d", + 4110 => x"0d", + 4111 => x"05", + 4112 => x"05", + 4113 => x"33", + 4114 => x"53", + 4115 => x"05", + 4116 => x"51", + 4117 => x"91", + 4118 => x"55", + 4119 => x"08", + 4120 => x"78", + 4121 => x"95", + 4122 => x"51", + 4123 => x"91", + 4124 => x"55", + 4125 => x"08", + 4126 => x"80", + 4127 => x"81", + 4128 => x"86", + 4129 => x"38", + 4130 => x"61", + 4131 => x"12", + 4132 => x"7a", + 4133 => x"51", + 4134 => x"74", + 4135 => x"78", + 4136 => x"83", + 4137 => x"51", + 4138 => x"3f", + 4139 => x"08", + 4140 => x"ca", + 4141 => x"3d", + 4142 => x"3d", + 4143 => x"82", + 4144 => x"d0", + 4145 => x"3d", + 4146 => x"3f", + 4147 => x"08", + 4148 => x"88", + 4149 => x"38", + 4150 => x"52", + 4151 => x"05", + 4152 => x"3f", + 4153 => x"08", + 4154 => x"88", + 4155 => x"02", + 4156 => x"33", + 4157 => x"54", + 4158 => x"a6", + 4159 => x"22", + 4160 => x"71", + 4161 => x"53", + 4162 => x"51", + 4163 => x"3f", + 4164 => x"0b", + 4165 => x"76", + 4166 => x"b8", + 4167 => x"88", + 4168 => x"91", + 4169 => x"93", + 4170 => x"ea", + 4171 => x"6b", + 4172 => x"53", + 4173 => x"05", + 4174 => x"51", + 4175 => x"91", + 4176 => x"91", + 4177 => x"30", + 4178 => x"88", + 4179 => x"25", + 4180 => x"79", + 4181 => x"85", + 4182 => x"75", + 4183 => x"73", + 4184 => x"f9", + 4185 => x"80", + 4186 => x"8d", + 4187 => x"54", + 4188 => x"3f", + 4189 => x"08", + 4190 => x"88", + 4191 => x"38", + 4192 => x"51", + 4193 => x"91", + 4194 => x"57", + 4195 => x"08", + 4196 => x"ca", + 4197 => x"ca", + 4198 => x"5b", + 4199 => x"18", + 4200 => x"18", + 4201 => x"74", + 4202 => x"81", + 4203 => x"78", + 4204 => x"8b", + 4205 => x"54", + 4206 => x"75", + 4207 => x"38", + 4208 => x"1b", + 4209 => x"55", + 4210 => x"2e", + 4211 => x"39", + 4212 => x"09", + 4213 => x"38", + 4214 => x"80", + 4215 => x"70", + 4216 => x"25", + 4217 => x"80", + 4218 => x"38", + 4219 => x"bc", + 4220 => x"11", + 4221 => x"ff", + 4222 => x"91", + 4223 => x"57", + 4224 => x"08", + 4225 => x"70", + 4226 => x"80", + 4227 => x"83", + 4228 => x"80", + 4229 => x"84", + 4230 => x"a7", + 4231 => x"b4", + 4232 => x"ad", + 4233 => x"ca", + 4234 => x"0c", + 4235 => x"88", + 4236 => x"0d", + 4237 => x"0d", + 4238 => x"3d", + 4239 => x"52", + 4240 => x"ce", + 4241 => x"ca", + 4242 => x"ca", + 4243 => x"54", + 4244 => x"08", + 4245 => x"8b", + 4246 => x"8b", + 4247 => x"59", + 4248 => x"3f", + 4249 => x"33", + 4250 => x"06", + 4251 => x"57", + 4252 => x"81", + 4253 => x"58", + 4254 => x"06", + 4255 => x"4e", + 4256 => x"ff", + 4257 => x"91", + 4258 => x"80", + 4259 => x"6c", + 4260 => x"53", + 4261 => x"ae", + 4262 => x"ca", + 4263 => x"2e", + 4264 => x"88", + 4265 => x"6d", + 4266 => x"55", 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x"88", + 4326 => x"09", + 4327 => x"cc", + 4328 => x"76", + 4329 => x"c4", + 4330 => x"74", + 4331 => x"b0", + 4332 => x"88", + 4333 => x"ca", + 4334 => x"38", + 4335 => x"ca", + 4336 => x"67", + 4337 => x"db", + 4338 => x"88", + 4339 => x"34", + 4340 => x"52", + 4341 => x"ab", + 4342 => x"54", + 4343 => x"15", + 4344 => x"ff", + 4345 => x"91", + 4346 => x"54", + 4347 => x"91", + 4348 => x"9c", + 4349 => x"f2", + 4350 => x"62", + 4351 => x"80", + 4352 => x"93", + 4353 => x"55", + 4354 => x"5e", + 4355 => x"3f", + 4356 => x"08", + 4357 => x"88", + 4358 => x"38", + 4359 => x"58", + 4360 => x"38", + 4361 => x"97", + 4362 => x"08", + 4363 => x"38", + 4364 => x"70", + 4365 => x"81", + 4366 => x"55", + 4367 => x"87", + 4368 => x"39", + 4369 => x"90", + 4370 => x"82", + 4371 => x"8a", + 4372 => x"89", + 4373 => x"7f", + 4374 => x"56", + 4375 => x"3f", + 4376 => x"06", + 4377 => x"72", + 4378 => x"91", + 4379 => x"05", + 4380 => x"7c", + 4381 => x"55", + 4382 => x"27", + 4383 => x"16", + 4384 => x"83", + 4385 => x"76", + 4386 => x"80", + 4387 => x"79", + 4388 => x"99", + 4389 => x"7f", + 4390 => x"14", + 4391 => x"83", + 4392 => x"91", + 4393 => x"81", + 4394 => x"38", + 4395 => x"08", + 4396 => x"95", + 4397 => x"88", + 4398 => x"81", + 4399 => x"7b", + 4400 => x"06", + 4401 => x"39", + 4402 => x"56", + 4403 => x"09", + 4404 => x"b9", + 4405 => x"80", + 4406 => x"80", + 4407 => x"78", + 4408 => x"7a", + 4409 => x"38", + 4410 => x"73", + 4411 => x"81", + 4412 => x"ff", + 4413 => x"74", + 4414 => x"ff", + 4415 => x"91", + 4416 => x"58", + 4417 => x"08", + 4418 => x"74", + 4419 => x"16", + 4420 => x"73", + 4421 => x"39", + 4422 => x"7e", + 4423 => x"0c", + 4424 => x"2e", + 4425 => x"88", + 4426 => x"8c", + 4427 => x"1a", + 4428 => x"07", + 4429 => x"1b", + 4430 => x"08", + 4431 => x"16", + 4432 => x"75", + 4433 => x"38", + 4434 => x"90", + 4435 => x"15", + 4436 => x"54", + 4437 => x"34", + 4438 => x"91", + 4439 => x"90", + 4440 => x"e9", + 4441 => x"6d", + 4442 => x"80", + 4443 => x"9d", + 4444 => x"5c", + 4445 => x"3f", + 4446 => x"0b", + 4447 => x"08", + 4448 => x"38", + 4449 => x"08", + 4450 => x"ca", + 4451 => x"08", + 4452 => x"80", + 4453 => x"80", + 4454 => x"ca", + 4455 => x"ff", + 4456 => x"52", + 4457 => x"a0", + 4458 => x"ca", + 4459 => x"ff", + 4460 => x"06", + 4461 => x"56", + 4462 => x"38", + 4463 => x"70", + 4464 => x"55", + 4465 => x"8b", + 4466 => x"3d", + 4467 => x"83", + 4468 => x"ff", + 4469 => x"91", + 4470 => x"99", + 4471 => x"74", + 4472 => x"38", + 4473 => x"80", + 4474 => x"ff", + 4475 => x"55", + 4476 => x"83", + 4477 => x"78", + 4478 => x"38", + 4479 => x"26", + 4480 => x"81", + 4481 => x"8b", + 4482 => x"79", + 4483 => x"80", + 4484 => x"93", + 4485 => x"39", + 4486 => x"6e", + 4487 => x"89", + 4488 => x"48", + 4489 => x"83", + 4490 => x"61", + 4491 => x"25", + 4492 => x"55", + 4493 => x"8a", + 4494 => x"3d", + 4495 => x"81", + 4496 => x"ff", + 4497 => x"81", + 4498 => x"88", + 4499 => x"38", + 4500 => x"70", + 4501 => x"ca", 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x"80", + 4561 => x"76", + 4562 => x"38", + 4563 => x"51", + 4564 => x"3f", + 4565 => x"08", + 4566 => x"57", + 4567 => x"08", + 4568 => x"96", + 4569 => x"91", + 4570 => x"10", + 4571 => x"08", + 4572 => x"72", + 4573 => x"59", + 4574 => x"ff", + 4575 => x"5d", + 4576 => x"44", + 4577 => x"11", + 4578 => x"70", + 4579 => x"71", + 4580 => x"06", + 4581 => x"52", + 4582 => x"40", + 4583 => x"09", + 4584 => x"38", + 4585 => x"18", + 4586 => x"39", + 4587 => x"79", + 4588 => x"70", + 4589 => x"58", + 4590 => x"76", + 4591 => x"38", + 4592 => x"7d", + 4593 => x"70", + 4594 => x"55", + 4595 => x"3f", + 4596 => x"08", + 4597 => x"2e", + 4598 => x"9b", + 4599 => x"88", + 4600 => x"f5", + 4601 => x"38", + 4602 => x"38", + 4603 => x"59", + 4604 => x"38", + 4605 => x"7d", + 4606 => x"81", + 4607 => x"38", + 4608 => x"0b", + 4609 => x"08", + 4610 => x"78", + 4611 => x"1a", + 4612 => x"c0", + 4613 => x"74", + 4614 => x"39", + 4615 => x"55", + 4616 => x"8f", + 4617 => x"fd", + 4618 => x"ca", + 4619 => x"f5", + 4620 => x"78", + 4621 => x"79", + 4622 => x"80", + 4623 => x"f1", + 4624 => x"39", + 4625 => x"81", + 4626 => x"06", + 4627 => x"55", + 4628 => x"27", + 4629 => x"81", + 4630 => x"56", + 4631 => x"38", + 4632 => x"80", + 4633 => x"ff", + 4634 => x"8b", + 4635 => x"d0", + 4636 => x"ff", + 4637 => x"84", + 4638 => x"1b", + 4639 => x"b3", + 4640 => x"1c", + 4641 => x"ff", + 4642 => x"8e", + 4643 => x"a1", + 4644 => x"0b", + 4645 => x"7d", + 4646 => x"30", + 4647 => x"84", + 4648 => x"51", + 4649 => x"51", + 4650 => x"3f", + 4651 => x"83", + 4652 => x"90", + 4653 => x"ff", + 4654 => x"93", + 4655 => x"a0", + 4656 => x"39", + 4657 => x"1b", + 4658 => x"85", + 4659 => x"95", + 4660 => x"52", + 4661 => x"ff", + 4662 => x"81", + 4663 => x"1b", + 4664 => x"cf", + 4665 => x"9c", + 4666 => x"a0", + 4667 => x"83", + 4668 => x"06", + 4669 => x"82", + 4670 => x"52", + 4671 => x"51", + 4672 => x"3f", + 4673 => x"1b", + 4674 => x"c5", + 4675 => x"ac", + 4676 => x"a0", + 4677 => x"52", + 4678 => x"ff", + 4679 => x"86", + 4680 => x"51", + 4681 => x"3f", + 4682 => x"80", + 4683 => x"a9", + 4684 => x"1c", + 4685 => x"91", + 4686 => x"80", + 4687 => x"ae", + 4688 => x"b2", + 4689 => x"1b", + 4690 => x"85", + 4691 => x"ff", + 4692 => x"96", + 4693 => x"9f", + 4694 => x"80", + 4695 => x"34", + 4696 => x"1c", + 4697 => x"91", + 4698 => x"ab", + 4699 => x"a0", + 4700 => x"d4", + 4701 => x"fe", + 4702 => x"59", + 4703 => x"3f", + 4704 => x"53", + 4705 => x"51", + 4706 => x"3f", + 4707 => x"ca", + 4708 => x"e7", + 4709 => x"2e", + 4710 => x"80", + 4711 => x"54", + 4712 => x"53", + 4713 => x"51", + 4714 => x"3f", + 4715 => x"80", + 4716 => x"ff", + 4717 => x"84", + 4718 => x"d2", + 4719 => x"ff", + 4720 => x"86", + 4721 => x"f2", + 4722 => x"1b", + 4723 => x"81", + 4724 => x"52", + 4725 => x"51", + 4726 => x"3f", + 4727 => x"ec", + 4728 => x"9e", + 4729 => x"d4", + 4730 => x"51", + 4731 => x"3f", + 4732 => x"87", + 4733 => x"52", + 4734 => x"9a", + 4735 => x"54", + 4736 => x"7a", + 4737 => x"ff", + 4738 => x"65", + 4739 => x"7a", + 4740 => x"8f", + 4741 => x"80", + 4742 => x"2e", + 4743 => x"9a", + 4744 => x"7a", + 4745 => x"a9", + 4746 => x"84", + 4747 => x"9e", + 4748 => x"0a", + 4749 => x"51", + 4750 => x"ff", + 4751 => x"7d", + 4752 => x"38", + 4753 => x"52", + 4754 => x"9e", + 4755 => x"55", + 4756 => x"62", + 4757 => x"74", + 4758 => x"75", + 4759 => x"7e", + 4760 => x"fe", + 4761 => x"88", + 4762 => x"38", + 4763 => x"91", + 4764 => x"52", + 4765 => x"9e", + 4766 => x"16", + 4767 => x"56", + 4768 => x"38", + 4769 => x"77", + 4770 => x"8d", + 4771 => x"7d", + 4772 => x"38", + 4773 => x"57", + 4774 => x"83", + 4775 => x"76", + 4776 => x"7a", + 4777 => x"ff", + 4778 => x"91", + 4779 => x"81", + 4780 => x"16", + 4781 => x"56", + 4782 => x"38", + 4783 => x"83", + 4784 => x"86", + 4785 => x"ff", + 4786 => x"38", + 4787 => x"82", + 4788 => x"81", + 4789 => x"06", + 4790 => x"fe", + 4791 => x"53", + 4792 => x"51", + 4793 => x"3f", + 4794 => x"52", + 4795 => x"9c", + 4796 => x"be", + 4797 => x"75", + 4798 => x"81", + 4799 => x"0b", + 4800 => x"77", + 4801 => x"75", + 4802 => x"60", + 4803 => x"80", + 4804 => x"75", + 4805 => x"d1", + 4806 => x"85", + 4807 => x"ca", + 4808 => x"2a", + 4809 => x"75", + 4810 => x"91", + 4811 => x"87", + 4812 => x"52", + 4813 => x"51", + 4814 => x"3f", + 4815 => x"ca", + 4816 => x"9c", + 4817 => x"54", + 4818 => x"52", + 4819 => x"98", + 4820 => x"56", + 4821 => x"08", + 4822 => x"53", + 4823 => x"51", + 4824 => x"3f", + 4825 => x"ca", + 4826 => x"38", + 4827 => x"56", + 4828 => x"56", + 4829 => x"ca", + 4830 => x"75", + 4831 => x"0c", + 4832 => x"04", + 4833 => x"73", + 4834 => x"26", + 4835 => x"71", + 4836 => x"b3", + 4837 => x"71", + 4838 => x"bb", + 4839 => x"80", + 4840 => x"e4", + 4841 => x"39", + 4842 => x"51", + 4843 => x"91", + 4844 => x"80", + 4845 => x"bc", + 4846 => x"e4", + 4847 => x"ac", + 4848 => x"39", + 4849 => x"51", + 4850 => x"91", + 4851 => x"80", + 4852 => x"bc", + 4853 => x"c8", + 4854 => x"80", + 4855 => x"39", + 4856 => x"51", + 4857 => x"bd", + 4858 => x"39", + 4859 => x"51", + 4860 => x"bd", + 4861 => x"39", + 4862 => x"51", + 4863 => x"be", + 4864 => x"39", + 4865 => x"51", + 4866 => x"be", + 4867 => x"39", + 4868 => x"51", + 4869 => x"bf", + 4870 => x"39", + 4871 => x"51", + 4872 => x"3f", + 4873 => x"04", + 4874 => x"77", + 4875 => x"74", + 4876 => x"8a", + 4877 => x"75", + 4878 => x"51", + 4879 => x"e8", + 4880 => x"fe", + 4881 => x"91", + 4882 => x"52", + 4883 => x"f2", + 4884 => x"ca", + 4885 => x"79", + 4886 => x"91", + 4887 => x"ff", + 4888 => x"87", + 4889 => x"f5", + 4890 => x"7f", + 4891 => x"05", + 4892 => x"33", + 4893 => x"66", + 4894 => x"5a", + 4895 => x"78", + 4896 => x"c4", + 4897 => x"fa", + 4898 => x"cc", + 4899 => x"8e", + 4900 => x"74", + 4901 => x"fc", + 4902 => x"2e", + 4903 => x"a0", + 4904 => x"80", + 4905 => x"16", + 4906 => x"27", + 4907 => x"22", + 4908 => x"d0", + 4909 => x"ca", + 4910 => x"91", + 4911 => x"ff", + 4912 => x"82", + 4913 => x"c3", + 4914 => x"53", + 4915 => x"8e", + 4916 => x"52", + 4917 => x"51", + 4918 => x"3f", + 4919 => x"bf", + 4920 => x"86", + 4921 => x"15", + 4922 => x"74", + 4923 => x"78", + 4924 => x"72", + 4925 => x"bf", + 4926 => x"8c", + 4927 => x"39", + 4928 => x"51", + 4929 => x"3f", + 4930 => x"a0", + 4931 => x"8d", + 4932 => x"39", + 4933 => x"51", + 4934 => x"3f", + 4935 => x"77", + 4936 => x"74", + 4937 => x"79", + 4938 => x"55", + 4939 => x"27", + 4940 => x"80", + 4941 => x"73", + 4942 => x"85", + 4943 => x"83", + 4944 => x"fe", + 4945 => x"81", + 4946 => x"39", + 4947 => x"51", + 4948 => x"3f", + 4949 => x"1a", + 4950 => x"fd", + 4951 => x"ca", + 4952 => x"2b", + 4953 => x"51", + 4954 => x"2e", + 4955 => x"a5", + 4956 => x"fb", + 4957 => x"88", + 4958 => x"70", + 4959 => x"a0", + 4960 => x"70", + 4961 => x"2a", + 4962 => x"51", + 4963 => x"2e", + 4964 => x"dd", + 4965 => x"2e", + 4966 => x"85", + 4967 => x"8c", + 4968 => x"53", + 4969 => x"fd", + 4970 => x"53", + 4971 => x"88", + 4972 => x"0d", + 4973 => x"0d", + 4974 => x"05", + 4975 => x"33", + 4976 => x"70", + 4977 => x"25", + 4978 => x"74", + 4979 => x"51", + 4980 => x"56", + 4981 => x"80", + 4982 => x"53", + 4983 => x"3d", + 4984 => x"c0", + 4985 => x"ca", + 4986 => x"91", + 4987 => x"b8", + 4988 => x"88", + 4989 => x"98", + 4990 => x"ca", + 4991 => x"96", + 4992 => x"54", + 4993 => x"77", + 4994 => x"c4", + 4995 => x"ca", + 4996 => x"91", + 4997 => x"90", + 4998 => x"74", + 4999 => x"38", + 5000 => x"19", + 5001 => x"39", + 5002 => x"05", + 5003 => x"3f", + 5004 => x"77", + 5005 => x"51", + 5006 => x"2e", + 5007 => x"80", + 5008 => x"91", + 5009 => x"87", + 5010 => x"08", + 5011 => x"fb", + 5012 => x"57", + 5013 => x"88", + 5014 => x"0d", + 5015 => x"0d", + 5016 => x"05", + 5017 => x"57", + 5018 => x"80", + 5019 => x"79", + 5020 => x"3f", + 5021 => x"08", + 5022 => x"80", + 5023 => x"75", + 5024 => x"38", + 5025 => x"55", + 5026 => x"ca", + 5027 => x"52", + 5028 => x"2d", + 5029 => x"08", + 5030 => x"77", + 5031 => x"ca", + 5032 => x"3d", + 5033 => x"3d", + 5034 => x"05", + 5035 => x"80", + 5036 => x"88", + 5037 => x"88", + 5038 => x"c7", + 5039 => x"ff", + 5040 => x"91", + 5041 => x"91", + 5042 => x"91", + 5043 => x"52", + 5044 => x"51", + 5045 => x"3f", + 5046 => x"85", + 5047 => x"92", + 5048 => x"0d", + 5049 => x"0d", + 5050 => x"80", + 5051 => x"80", + 5052 => x"51", + 5053 => x"3f", + 5054 => x"51", + 5055 => x"3f", + 5056 => x"f5", + 5057 => x"81", + 5058 => x"06", + 5059 => x"80", + 5060 => x"81", + 5061 => x"eb", + 5062 => x"e0", + 5063 => x"e3", + 5064 => x"fe", + 5065 => x"72", + 5066 => x"81", + 5067 => x"71", + 5068 => x"38", + 5069 => x"f5", + 5070 => x"c0", + 5071 => x"f7", + 5072 => x"51", + 5073 => x"3f", + 5074 => x"70", + 5075 => x"52", + 5076 => x"95", + 5077 => x"fe", + 5078 => x"91", + 5079 => x"fe", + 5080 => x"80", + 5081 => x"9b", + 5082 => x"2a", + 5083 => x"51", + 5084 => x"2e", + 5085 => x"51", + 5086 => x"3f", + 5087 => x"51", + 5088 => x"3f", + 5089 => x"f4", + 5090 => x"85", + 5091 => x"06", + 5092 => x"80", + 5093 => x"81", + 5094 => x"e7", + 5095 => x"ac", + 5096 => x"df", + 5097 => x"fe", + 5098 => x"72", + 5099 => x"81", + 5100 => x"71", + 5101 => x"38", + 5102 => x"f4", + 5103 => x"c1", + 5104 => x"f6", + 5105 => x"51", + 5106 => x"3f", + 5107 => x"70", + 5108 => x"52", + 5109 => x"95", + 5110 => x"fe", + 5111 => x"91", + 5112 => x"fe", + 5113 => x"80", + 5114 => x"97", + 5115 => x"2a", + 5116 => x"51", + 5117 => x"2e", + 5118 => x"51", + 5119 => x"3f", + 5120 => x"51", + 5121 => x"3f", + 5122 => x"f3", + 5123 => x"ff", + 5124 => x"3d", + 5125 => x"3d", + 5126 => x"08", + 5127 => x"57", + 5128 => x"80", + 5129 => x"39", + 5130 => x"85", + 5131 => x"80", + 5132 => x"14", + 5133 => x"33", + 5134 => x"06", + 5135 => x"74", + 5136 => x"38", + 5137 => x"80", + 5138 => x"72", + 5139 => x"81", + 5140 => x"72", + 5141 => x"81", + 5142 => x"80", + 5143 => x"05", + 5144 => x"56", + 5145 => x"91", + 5146 => x"77", + 5147 => x"08", + 5148 => x"ed", + 5149 => x"ca", + 5150 => x"38", + 5151 => x"53", + 5152 => x"ff", + 5153 => x"16", + 5154 => x"06", + 5155 => x"76", + 5156 => x"ff", + 5157 => x"ca", + 5158 => x"3d", + 5159 => x"3d", + 5160 => x"71", + 5161 => x"0c", + 5162 => x"52", + 5163 => x"8a", + 5164 => x"ca", + 5165 => x"ff", + 5166 => x"7c", + 5167 => x"06", + 5168 => x"c2", + 5169 => x"3d", + 5170 => x"ff", + 5171 => x"7b", + 5172 => x"91", + 5173 => x"ff", + 5174 => x"91", + 5175 => x"7c", + 5176 => x"91", + 5177 => x"90", + 5178 => x"70", + 5179 => x"c2", + 5180 => x"fe", + 5181 => x"3d", + 5182 => x"80", + 5183 => x"52", + 5184 => x"eb", + 5185 => x"f8", + 5186 => x"ff", + 5187 => x"b7", + 5188 => x"05", + 5189 => x"3f", + 5190 => x"08", + 5191 => x"90", + 5192 => x"78", + 5193 => x"8a", + 5194 => x"80", + 5195 => x"e0", + 5196 => x"2e", + 5197 => x"78", + 5198 => x"38", + 5199 => x"82", + 5200 => x"84", + 5201 => x"78", + 5202 => x"a2", + 5203 => x"2e", + 5204 => x"8e", + 5205 => x"94", + 5206 => x"38", + 5207 => x"83", + 5208 => x"e2", + 5209 => x"2e", + 5210 => x"78", + 5211 => x"38", + 5212 => x"84", + 5213 => x"bd", + 5214 => x"38", + 5215 => x"78", + 5216 => x"86", + 5217 => x"80", + 5218 => x"cf", + 5219 => x"39", + 5220 => x"2e", + 5221 => x"78", + 5222 => x"b0", + 5223 => x"d1", + 5224 => x"38", + 5225 => x"24", + 5226 => x"80", + 5227 => x"83", + 5228 => x"d0", + 5229 => x"38", + 5230 => x"78", + 5231 => x"8c", + 5232 => x"80", + 5233 => x"d6", + 5234 => x"39", + 5235 => x"2e", + 5236 => x"78", + 5237 => x"92", + 5238 => x"f9", + 5239 => x"38", + 5240 => x"2e", + 5241 => x"8d", + 5242 => x"81", + 5243 => x"cf", + 5244 => x"87", + 5245 => x"38", + 5246 => x"b7", + 5247 => x"11", + 5248 => x"05", + 5249 => x"ef", + 5250 => x"88", + 5251 => x"91", + 5252 => x"8e", + 5253 => x"3d", + 5254 => x"53", + 5255 => x"51", + 5256 => x"3f", + 5257 => x"08", + 5258 => x"38", + 5259 => x"83", + 5260 => x"02", + 5261 => x"33", + 5262 => x"cf", + 5263 => x"ff", + 5264 => x"91", + 5265 => x"81", + 5266 => x"78", + 5267 => x"c2", + 5268 => x"fb", + 5269 => x"5d", + 5270 => x"91", + 5271 => x"8b", + 5272 => x"3d", + 5273 => x"53", + 5274 => x"51", + 5275 => x"3f", + 5276 => x"08", + 5277 => x"f6", + 5278 => x"80", + 5279 => x"cf", + 5280 => x"ff", + 5281 => x"91", + 5282 => x"52", + 5283 => x"51", + 5284 => x"b7", + 5285 => x"11", + 5286 => x"05", + 5287 => x"d7", + 5288 => x"88", + 5289 => x"87", + 5290 => x"26", + 5291 => x"b7", + 5292 => x"11", + 5293 => x"05", + 5294 => x"bb", + 5295 => x"88", + 5296 => x"91", + 5297 => x"43", + 5298 => x"c3", + 5299 => x"51", + 5300 => x"3f", + 5301 => x"05", + 5302 => x"52", + 5303 => x"29", + 5304 => x"05", + 5305 => x"d5", + 5306 => x"88", + 5307 => x"38", + 5308 => x"51", + 5309 => x"3f", + 5310 => x"f2", + 5311 => x"fe", + 5312 => x"fe", + 5313 => x"91", + 5314 => x"b8", + 5315 => x"05", + 5316 => x"eb", + 5317 => x"53", + 5318 => x"08", + 5319 => x"f5", + 5320 => x"d5", + 5321 => x"fe", + 5322 => x"fe", + 5323 => x"91", + 5324 => x"b8", + 5325 => x"05", + 5326 => x"ea", + 5327 => x"ca", + 5328 => x"3d", + 5329 => x"52", + 5330 => x"ca", + 5331 => x"88", + 5332 => x"fe", + 5333 => x"59", + 5334 => x"3f", + 5335 => x"58", + 5336 => x"57", + 5337 => x"55", + 5338 => x"08", + 5339 => x"54", + 5340 => x"52", + 5341 => x"e5", + 5342 => x"88", + 5343 => x"fa", + 5344 => x"ca", + 5345 => x"ef", + 5346 => x"e2", + 5347 => x"fe", + 5348 => x"fe", + 5349 => x"ff", + 5350 => x"91", + 5351 => x"80", + 5352 => x"38", + 5353 => x"f0", + 5354 => x"f8", + 5355 => x"80", + 5356 => x"ca", + 5357 => x"2e", + 5358 => x"b7", + 5359 => x"11", + 5360 => x"05", + 5361 => x"af", + 5362 => x"88", + 5363 => x"91", + 5364 => x"42", + 5365 => x"51", + 5366 => x"3f", + 5367 => x"5a", + 5368 => x"81", + 5369 => x"59", + 5370 => x"84", + 5371 => x"7a", + 5372 => x"38", + 5373 => x"b7", + 5374 => x"11", + 5375 => x"05", + 5376 => x"f3", + 5377 => x"88", + 5378 => x"f9", + 5379 => x"3d", + 5380 => x"53", + 5381 => x"51", + 5382 => x"3f", + 5383 => x"08", + 5384 => x"ca", + 5385 => x"fe", + 5386 => x"fe", + 5387 => x"fe", + 5388 => x"91", + 5389 => x"80", + 5390 => x"38", + 5391 => x"51", + 5392 => x"3f", + 5393 => x"63", + 5394 => x"38", + 5395 => x"70", + 5396 => x"33", + 5397 => x"81", + 5398 => x"39", + 5399 => x"f4", + 5400 => x"f8", + 5401 => x"ff", + 5402 => x"ca", + 5403 => x"2e", + 5404 => x"b7", + 5405 => x"11", + 5406 => x"05", + 5407 => x"f7", + 5408 => x"88", + 5409 => x"f8", + 5410 => x"3d", + 5411 => x"53", + 5412 => x"51", + 5413 => x"3f", + 5414 => x"08", + 5415 => x"ce", + 5416 => x"c4", + 5417 => x"f6", + 5418 => x"79", + 5419 => x"38", + 5420 => x"7b", + 5421 => x"5b", + 5422 => x"92", + 5423 => x"7a", + 5424 => x"53", + 5425 => x"c3", + 5426 => x"fc", + 5427 => x"1a", + 5428 => x"43", + 5429 => x"91", + 5430 => x"86", + 5431 => x"3d", + 5432 => x"53", + 5433 => x"51", + 5434 => x"3f", + 5435 => x"08", + 5436 => x"91", + 5437 => x"59", + 5438 => x"88", + 5439 => x"e4", + 5440 => x"39", + 5441 => x"33", + 5442 => x"2e", + 5443 => x"c6", + 5444 => x"a2", + 5445 => x"93", + 5446 => x"8b", + 5447 => x"94", + 5448 => x"80", + 5449 => x"91", + 5450 => x"44", + 5451 => x"c7", + 5452 => x"80", + 5453 => x"3d", + 5454 => x"53", + 5455 => x"51", + 5456 => x"3f", + 5457 => x"08", + 5458 => x"91", + 5459 => x"59", + 5460 => x"88", + 5461 => x"e8", + 5462 => x"39", + 5463 => x"33", + 5464 => x"2e", + 5465 => x"c6", + 5466 => x"a1", + 5467 => x"93", + 5468 => x"8b", + 5469 => x"94", + 5470 => x"80", + 5471 => x"91", + 5472 => x"43", + 5473 => x"c7", + 5474 => x"05", + 5475 => x"fe", + 5476 => x"fe", + 5477 => x"fe", + 5478 => x"91", + 5479 => x"80", + 5480 => x"80", + 5481 => x"79", + 5482 => x"38", + 5483 => x"90", + 5484 => x"78", + 5485 => x"38", + 5486 => x"83", + 5487 => x"91", + 5488 => x"fe", + 5489 => x"a0", + 5490 => x"61", + 5491 => x"63", + 5492 => x"3f", + 5493 => x"51", + 5494 => x"b7", + 5495 => x"11", + 5496 => x"05", + 5497 => x"8f", + 5498 => x"88", + 5499 => x"f5", + 5500 => x"3d", + 5501 => x"53", + 5502 => x"51", + 5503 => x"3f", + 5504 => x"08", + 5505 => x"38", + 5506 => x"80", + 5507 => x"79", + 5508 => x"05", + 5509 => x"fe", + 5510 => x"fe", + 5511 => x"fe", + 5512 => x"91", + 5513 => x"e0", + 5514 => x"39", + 5515 => x"54", + 5516 => x"8c", + 5517 => x"ca", + 5518 => x"52", + 5519 => x"fa", + 5520 => x"45", + 5521 => x"78", + 5522 => x"a2", + 5523 => x"27", + 5524 => x"3d", + 5525 => x"53", + 5526 => x"51", + 5527 => x"3f", + 5528 => x"08", + 5529 => x"38", + 5530 => x"80", + 5531 => x"79", + 5532 => x"05", + 5533 => x"39", + 5534 => x"51", + 5535 => x"3f", + 5536 => x"b7", + 5537 => x"11", + 5538 => x"05", + 5539 => x"d9", + 5540 => x"88", + 5541 => x"f4", + 5542 => x"3d", + 5543 => x"53", + 5544 => x"51", + 5545 => x"3f", + 5546 => x"08", + 5547 => x"38", + 5548 => x"be", + 5549 => x"70", + 5550 => x"23", + 5551 => x"3d", + 5552 => x"53", + 5553 => x"51", + 5554 => x"3f", + 5555 => x"08", + 5556 => x"9a", + 5557 => x"22", + 5558 => x"c4", + 5559 => x"f8", + 5560 => x"f8", + 5561 => x"fe", + 5562 => x"79", + 5563 => x"59", + 5564 => x"f3", + 5565 => x"9f", + 5566 => x"60", + 5567 => x"d5", + 5568 => x"fe", + 5569 => x"fe", + 5570 => x"fe", + 5571 => x"91", + 5572 => x"80", + 5573 => x"60", + 5574 => x"05", + 5575 => x"82", + 5576 => x"78", + 5577 => x"39", + 5578 => x"51", + 5579 => x"3f", + 5580 => x"b7", + 5581 => x"11", + 5582 => x"05", + 5583 => x"a9", + 5584 => x"88", + 5585 => x"f3", + 5586 => x"3d", + 5587 => x"53", + 5588 => x"51", + 5589 => x"3f", + 5590 => x"08", + 5591 => x"38", + 5592 => x"0c", + 5593 => x"05", + 5594 => x"fe", + 5595 => x"fe", + 5596 => x"fe", + 5597 => x"91", + 5598 => x"e4", + 5599 => x"39", + 5600 => x"54", + 5601 => x"ac", + 5602 => x"f6", + 5603 => x"52", + 5604 => x"f7", + 5605 => x"45", + 5606 => x"78", + 5607 => x"ce", + 5608 => x"27", + 5609 => x"3d", + 5610 => x"53", + 5611 => x"51", + 5612 => x"3f", + 5613 => x"08", + 5614 => x"38", + 5615 => x"52", + 5616 => x"51", + 5617 => x"3f", + 5618 => x"0c", + 5619 => x"05", + 5620 => x"39", + 5621 => x"51", + 5622 => x"3f", + 5623 => x"91", + 5624 => x"fe", + 5625 => x"82", + 5626 => x"a6", + 5627 => x"39", + 5628 => x"51", + 5629 => x"3f", + 5630 => x"ee", + 5631 => x"ee", + 5632 => x"81", + 5633 => x"94", + 5634 => x"80", + 5635 => x"c0", + 5636 => x"91", + 5637 => x"fe", + 5638 => x"f1", + 5639 => x"c4", + 5640 => x"ef", + 5641 => x"80", + 5642 => x"c0", + 5643 => x"8c", + 5644 => x"87", + 5645 => x"0c", + 5646 => x"b7", + 5647 => x"11", + 5648 => x"05", + 5649 => x"af", + 5650 => x"88", + 5651 => x"f1", + 5652 => x"52", + 5653 => x"51", + 5654 => x"3f", + 5655 => x"04", + 5656 => x"f4", + 5657 => x"f8", + 5658 => x"f7", + 5659 => x"ca", + 5660 => x"2e", + 5661 => x"63", + 5662 => x"ac", + 5663 => x"82", + 5664 => x"78", + 5665 => x"88", + 5666 => x"ca", + 5667 => x"2e", + 5668 => x"91", + 5669 => x"52", + 5670 => x"51", + 5671 => x"3f", + 5672 => x"91", + 5673 => x"fe", + 5674 => x"fe", + 5675 => x"f0", + 5676 => x"c6", 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x"04", + 5736 => x"04", + 5737 => x"04", + 5738 => x"04", + 5739 => x"04", + 5740 => x"04", + 5741 => x"04", + 5742 => x"04", + 5743 => x"04", + 5744 => x"04", + 5745 => x"04", + 5746 => x"04", + 5747 => x"04", + 5748 => x"04", + 5749 => x"04", + 5750 => x"04", + 5751 => x"04", + 5752 => x"04", + 5753 => x"04", + 5754 => x"04", + 5755 => x"64", + 5756 => x"2f", + 5757 => x"25", + 5758 => x"64", + 5759 => x"2e", + 5760 => x"64", + 5761 => x"6f", + 5762 => x"6f", + 5763 => x"67", + 5764 => x"74", + 5765 => x"00", + 5766 => x"28", + 5767 => x"6d", + 5768 => x"43", + 5769 => x"6e", + 5770 => x"29", + 5771 => x"0a", + 5772 => x"69", + 5773 => x"20", + 5774 => x"6c", + 5775 => x"6e", + 5776 => x"3a", + 5777 => x"20", + 5778 => x"4e", + 5779 => x"42", + 5780 => x"20", + 5781 => x"61", + 5782 => x"25", + 5783 => x"2c", + 5784 => x"7a", + 5785 => x"30", + 5786 => x"2e", + 5787 => x"20", + 5788 => x"52", + 5789 => x"28", + 5790 => x"72", + 5791 => x"30", + 5792 => x"20", + 5793 => x"65", + 5794 => x"38", + 5795 => x"0a", + 5796 => x"20", + 5797 => x"41", + 5798 => x"53", + 5799 => x"74", + 5800 => x"38", + 5801 => x"53", + 5802 => x"3d", + 5803 => x"58", + 5804 => x"00", + 5805 => x"20", + 5806 => x"4f", + 5807 => x"0a", + 5808 => x"20", + 5809 => x"53", + 5810 => x"00", + 5811 => x"20", + 5812 => x"50", + 5813 => x"00", + 5814 => x"20", + 5815 => x"44", + 5816 => x"72", + 5817 => x"44", + 5818 => x"63", + 5819 => x"25", + 5820 => x"29", + 5821 => x"00", + 5822 => x"20", + 5823 => x"4e", + 5824 => x"52", + 5825 => x"20", + 5826 => x"54", + 5827 => x"4c", + 5828 => x"00", + 5829 => x"20", + 5830 => x"49", + 5831 => x"31", + 5832 => x"69", + 5833 => x"73", + 5834 => x"31", + 5835 => x"0a", + 5836 => x"64", + 5837 => x"73", + 5838 => x"3a", + 5839 => x"20", + 5840 => x"50", + 5841 => x"65", + 5842 => x"20", + 5843 => x"74", + 5844 => x"41", + 5845 => x"65", + 5846 => x"3d", + 5847 => x"38", + 5848 => x"00", + 5849 => x"20", + 5850 => x"50", + 5851 => x"65", + 5852 => x"79", + 5853 => x"61", + 5854 => x"41", + 5855 => x"65", + 5856 => x"3d", + 5857 => x"38", + 5858 => x"00", + 5859 => x"20", + 5860 => x"74", + 5861 => x"20", + 5862 => x"72", + 5863 => x"64", + 5864 => x"73", + 5865 => x"20", + 5866 => x"3d", + 5867 => x"38", + 5868 => x"00", + 5869 => x"20", + 5870 => x"50", + 5871 => x"64", + 5872 => x"20", + 5873 => x"20", + 5874 => x"20", + 5875 => x"20", + 5876 => x"3d", + 5877 => x"38", + 5878 => x"00", + 5879 => x"20", + 5880 => x"79", + 5881 => x"6d", + 5882 => x"6f", + 5883 => x"46", + 5884 => x"20", + 5885 => x"20", + 5886 => x"3d", + 5887 => x"38", + 5888 => x"00", + 5889 => x"6d", + 5890 => x"00", + 5891 => x"65", + 5892 => x"6d", + 5893 => x"6c", + 5894 => x"00", + 5895 => x"56", + 5896 => x"56", + 5897 => x"6e", + 5898 => x"6e", + 5899 => x"77", + 5900 => x"44", + 5901 => x"2a", + 5902 => x"3b", + 5903 => x"3f", + 5904 => x"7f", + 5905 => x"41", + 5906 => x"41", + 5907 => x"00", + 5908 => x"fe", + 5909 => x"44", + 5910 => x"2e", + 5911 => x"4f", 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x"69", + 5971 => x"00", + 5972 => x"69", + 5973 => x"6c", + 5974 => x"69", + 5975 => x"00", + 5976 => x"6c", + 5977 => x"00", + 5978 => x"65", + 5979 => x"00", + 5980 => x"63", + 5981 => x"72", + 5982 => x"63", + 5983 => x"00", + 5984 => x"64", + 5985 => x"00", + 5986 => x"64", + 5987 => x"00", + 5988 => x"65", + 5989 => x"65", + 5990 => x"65", + 5991 => x"69", + 5992 => x"69", + 5993 => x"66", + 5994 => x"66", + 5995 => x"61", + 5996 => x"00", + 5997 => x"6d", + 5998 => x"65", + 5999 => x"72", + 6000 => x"65", + 6001 => x"00", + 6002 => x"6e", + 6003 => x"00", + 6004 => x"65", + 6005 => x"00", + 6006 => x"69", + 6007 => x"45", + 6008 => x"72", + 6009 => x"6e", + 6010 => x"6e", + 6011 => x"65", + 6012 => x"72", + 6013 => x"00", + 6014 => x"69", + 6015 => x"6e", + 6016 => x"72", + 6017 => x"79", + 6018 => x"00", + 6019 => x"6f", + 6020 => x"6c", + 6021 => x"6f", + 6022 => x"2e", + 6023 => x"6f", + 6024 => x"74", + 6025 => x"6f", + 6026 => x"2e", + 6027 => x"6e", + 6028 => x"69", + 6029 => x"69", + 6030 => x"61", + 6031 => x"0a", + 6032 => x"63", + 6033 => x"73", + 6034 => x"6e", + 6035 => x"2e", + 6036 => x"69", + 6037 => x"61", + 6038 => x"61", + 6039 => x"65", + 6040 => x"74", + 6041 => x"00", + 6042 => x"69", + 6043 => x"68", + 6044 => x"6c", + 6045 => x"6e", + 6046 => x"69", + 6047 => x"00", + 6048 => x"44", + 6049 => x"20", + 6050 => x"74", + 6051 => x"72", + 6052 => x"63", + 6053 => x"2e", + 6054 => x"72", + 6055 => x"20", + 6056 => x"62", + 6057 => x"69", + 6058 => x"6e", + 6059 => x"69", + 6060 => x"00", + 6061 => x"69", + 6062 => x"6e", + 6063 => x"65", + 6064 => x"6c", + 6065 => x"0a", + 6066 => x"6f", + 6067 => x"6d", + 6068 => x"69", + 6069 => x"20", + 6070 => x"65", + 6071 => x"74", + 6072 => x"66", + 6073 => x"64", + 6074 => x"20", + 6075 => x"6b", + 6076 => x"00", + 6077 => x"6f", + 6078 => x"74", + 6079 => x"6f", + 6080 => x"64", + 6081 => x"00", + 6082 => x"69", + 6083 => x"75", + 6084 => x"6f", + 6085 => x"61", + 6086 => x"6e", + 6087 => x"6e", + 6088 => x"6c", + 6089 => x"0a", + 6090 => x"69", + 6091 => x"69", + 6092 => x"6f", + 6093 => x"64", + 6094 => x"00", + 6095 => x"6e", + 6096 => x"66", + 6097 => x"65", + 6098 => x"6d", + 6099 => x"72", + 6100 => x"00", + 6101 => x"6f", + 6102 => x"61", + 6103 => x"6f", + 6104 => x"20", + 6105 => x"65", + 6106 => x"00", + 6107 => x"61", + 6108 => x"65", + 6109 => x"73", + 6110 => x"63", + 6111 => x"65", + 6112 => x"0a", + 6113 => x"75", + 6114 => x"73", + 6115 => x"00", + 6116 => x"6e", + 6117 => x"77", + 6118 => x"72", + 6119 => x"2e", + 6120 => x"25", + 6121 => x"62", + 6122 => x"73", + 6123 => x"20", + 6124 => x"25", + 6125 => x"62", + 6126 => x"73", + 6127 => x"63", + 6128 => x"00", + 6129 => x"30", + 6130 => x"00", + 6131 => x"20", + 6132 => x"30", + 6133 => x"00", + 6134 => x"20", + 6135 => x"20", + 6136 => x"00", + 6137 => x"30", + 6138 => x"00", + 6139 => x"20", + 6140 => x"7c", + 6141 => x"0d", + 6142 => x"65", + 6143 => x"00", + 6144 => x"50", + 6145 => x"00", + 6146 => x"2a", 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x"72", + 6206 => x"74", + 6207 => x"65", + 6208 => x"6e", + 6209 => x"70", + 6210 => x"6d", + 6211 => x"2e", + 6212 => x"00", + 6213 => x"6e", + 6214 => x"69", + 6215 => x"74", + 6216 => x"72", + 6217 => x"0a", + 6218 => x"3a", + 6219 => x"61", + 6220 => x"64", + 6221 => x"20", + 6222 => x"74", + 6223 => x"69", + 6224 => x"73", + 6225 => x"61", + 6226 => x"30", + 6227 => x"6c", + 6228 => x"65", + 6229 => x"69", + 6230 => x"61", + 6231 => x"6c", + 6232 => x"0a", + 6233 => x"20", + 6234 => x"61", + 6235 => x"69", + 6236 => x"69", + 6237 => x"00", + 6238 => x"6e", + 6239 => x"61", + 6240 => x"65", + 6241 => x"00", + 6242 => x"61", + 6243 => x"64", + 6244 => x"20", + 6245 => x"74", + 6246 => x"69", + 6247 => x"0a", + 6248 => x"63", + 6249 => x"0a", + 6250 => x"75", + 6251 => x"6c", + 6252 => x"69", + 6253 => x"2e", + 6254 => x"6f", + 6255 => x"6e", + 6256 => x"2e", + 6257 => x"6f", + 6258 => x"72", + 6259 => x"2e", + 6260 => x"00", + 6261 => x"30", + 6262 => x"28", + 6263 => x"78", + 6264 => x"25", + 6265 => x"78", + 6266 => x"38", + 6267 => x"00", + 6268 => x"75", + 6269 => x"4d", + 6270 => x"72", + 6271 => x"00", + 6272 => x"43", + 6273 => x"6c", + 6274 => x"2e", + 6275 => x"30", + 6276 => x"25", + 6277 => x"2d", + 6278 => x"3f", + 6279 => x"00", + 6280 => x"30", + 6281 => x"25", + 6282 => x"2d", + 6283 => x"30", + 6284 => x"25", + 6285 => x"2d", + 6286 => x"69", + 6287 => x"6c", + 6288 => x"20", + 6289 => x"65", + 6290 => x"70", + 6291 => x"00", + 6292 => x"6e", + 6293 => x"69", + 6294 => x"69", + 6295 => x"72", + 6296 => x"74", + 6297 => x"00", + 6298 => x"69", + 6299 => x"6c", + 6300 => x"75", + 6301 => x"20", + 6302 => x"6f", + 6303 => x"6e", + 6304 => x"69", + 6305 => x"75", + 6306 => x"20", + 6307 => x"6f", + 6308 => x"78", + 6309 => x"74", + 6310 => x"20", + 6311 => x"65", + 6312 => x"25", + 6313 => x"20", + 6314 => x"0a", + 6315 => x"61", + 6316 => x"6e", + 6317 => x"6f", + 6318 => x"40", + 6319 => x"38", + 6320 => x"2e", + 6321 => x"00", + 6322 => x"61", + 6323 => x"72", + 6324 => x"72", + 6325 => x"20", + 6326 => x"65", + 6327 => x"64", + 6328 => x"00", + 6329 => x"65", + 6330 => x"72", + 6331 => x"67", + 6332 => x"70", + 6333 => x"61", + 6334 => x"6e", + 6335 => x"0a", + 6336 => x"6f", + 6337 => x"72", + 6338 => x"6f", + 6339 => x"67", + 6340 => x"0a", + 6341 => x"50", + 6342 => x"69", + 6343 => x"64", + 6344 => x"73", + 6345 => x"2e", + 6346 => x"00", + 6347 => x"61", + 6348 => x"6f", + 6349 => x"6e", + 6350 => x"00", + 6351 => x"75", + 6352 => x"6e", + 6353 => x"2e", + 6354 => x"6e", + 6355 => x"69", + 6356 => x"69", + 6357 => x"72", + 6358 => x"74", + 6359 => x"2e", + 6360 => x"00", + 6361 => x"00", + 6362 => x"00", + 6363 => x"00", + 6364 => x"00", + 6365 => x"01", + 6366 => x"00", + 6367 => x"00", + 6368 => x"00", + 6369 => x"00", + 6370 => x"00", + 6371 => x"f5", + 6372 => x"01", + 6373 => x"01", + 6374 => x"01", + 6375 => x"00", + 6376 => x"00", + 6377 => x"00", + 6378 => x"04", + 6379 => x"02", + 6380 => x"00", + 6381 => x"00", + 6382 => x"04", + 6383 => x"04", + 6384 => x"00", + 6385 => x"00", + 6386 => x"04", + 6387 => x"14", + 6388 => x"00", + 6389 => x"00", + 6390 => x"04", + 6391 => x"2b", + 6392 => x"00", + 6393 => x"00", + 6394 => x"04", + 6395 => x"30", + 6396 => x"00", + 6397 => x"00", + 6398 => x"04", + 6399 => x"3c", + 6400 => x"00", + 6401 => x"00", + 6402 => x"04", + 6403 => x"3d", + 6404 => x"00", + 6405 => x"00", + 6406 => x"04", + 6407 => x"3f", + 6408 => x"00", + 6409 => x"00", + 6410 => x"04", + 6411 => x"40", + 6412 => x"00", + 6413 => x"00", + 6414 => x"04", + 6415 => x"41", + 6416 => x"00", + 6417 => x"00", + 6418 => x"04", + 6419 => x"42", + 6420 => x"00", + 6421 => x"00", + 6422 => x"04", + 6423 => x"43", + 6424 => x"00", + 6425 => x"00", + 6426 => x"04", + 6427 => x"50", + 6428 => x"00", + 6429 => x"00", + 6430 => x"04", + 6431 => x"51", + 6432 => x"00", + 6433 => x"00", + 6434 => x"04", + 6435 => x"54", + 6436 => x"00", + 6437 => x"00", + 6438 => x"04", + 6439 => x"55", + 6440 => x"00", + 6441 => x"00", + 6442 => x"04", + 6443 => x"79", + 6444 => x"00", + 6445 => x"00", + 6446 => x"04", + 6447 => x"78", + 6448 => x"00", + 6449 => x"00", + 6450 => x"04", + 6451 => x"82", + 6452 => x"00", + 6453 => x"00", + 6454 => x"04", + 6455 => x"83", + 6456 => x"00", + 6457 => x"00", + 6458 => x"04", + 6459 => x"85", + 6460 => x"00", + 6461 => x"00", + 6462 => x"04", + 6463 => x"87", + 6464 => x"00", + 6465 => x"00", + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + 0 => x"0b", + 1 => x"80", + 2 => x"90", + 3 => x"ff", + 4 => x"ff", + 5 => x"ff", + 6 => x"ff", + 7 => x"ff", + 8 => x"0b", + 9 => x"80", + 10 => x"90", + 11 => x"0b", + 12 => x"96", + 13 => x"90", + 14 => x"0b", + 15 => x"b8", + 16 => x"90", + 17 => x"0b", + 18 => x"da", + 19 => x"90", + 20 => x"0b", + 21 => x"fc", + 22 => x"90", + 23 => x"0b", + 24 => x"9e", + 25 => x"90", + 26 => x"0b", + 27 => x"c0", + 28 => x"90", + 29 => x"0b", + 30 => x"e2", + 31 => x"90", + 32 => x"0b", + 33 => x"84", + 34 => x"90", + 35 => x"0b", + 36 => x"a6", + 37 => x"90", + 38 => x"0b", + 39 => x"c8", + 40 => x"90", + 41 => x"0b", + 42 => x"ea", + 43 => x"90", + 44 => x"0b", + 45 => x"8c", + 46 => x"90", + 47 => x"0b", + 48 => x"ae", + 49 => x"90", + 50 => x"0b", + 51 => x"d0", + 52 => x"90", + 53 => x"0b", + 54 => x"f2", + 55 => x"90", + 56 => x"0b", + 57 => x"94", + 58 => x"90", + 59 => x"0b", + 60 => x"b6", + 61 => x"90", + 62 => x"0b", + 63 => x"d8", + 64 => x"90", + 65 => x"0b", + 66 => x"fa", + 67 => x"90", + 68 => x"0b", + 69 => x"9c", + 70 => x"90", + 71 => x"0b", + 72 => x"be", + 73 => x"90", + 74 => x"0b", + 75 => x"e0", + 76 => x"90", + 77 => x"0b", + 78 => x"82", + 79 => x"90", + 80 => x"0b", + 81 => x"a4", + 82 => x"90", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"00", + 89 => x"00", + 90 => x"00", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"00", + 97 => x"00", + 98 => x"00", + 99 => x"00", + 100 => x"00", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"00", + 105 => x"00", + 106 => x"00", + 107 => x"00", + 108 => x"00", + 109 => x"00", + 110 => x"00", + 111 => x"00", + 112 => x"00", + 113 => x"00", + 114 => x"00", + 115 => x"00", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"00", + 121 => x"00", + 122 => x"00", + 123 => x"00", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"00", + 129 => x"04", + 130 => x"0c", + 131 => x"2d", + 132 => x"08", + 133 => x"90", + 134 => x"94", + 135 => x"bf", + 136 => x"94", + 137 => x"80", + 138 => x"ca", + 139 => x"9f", + 140 => x"ca", + 141 => x"c0", + 142 => x"91", + 143 => x"90", + 144 => x"91", + 145 => x"88", + 146 => x"04", + 147 => x"0c", + 148 => x"2d", + 149 => x"08", + 150 => x"90", + 151 => x"94", + 152 => x"d8", + 153 => x"94", + 154 => x"80", + 155 => x"ca", + 156 => x"a0", + 157 => x"ca", + 158 => x"c0", + 159 => x"91", + 160 => x"90", + 161 => x"91", + 162 => x"88", + 163 => x"04", + 164 => x"0c", + 165 => x"2d", + 166 => x"08", + 167 => x"90", + 168 => x"94", + 169 => x"80", + 170 => x"94", + 171 => x"80", + 172 => x"ca", + 173 => x"a6", + 174 => x"ca", + 175 => x"c0", + 176 => x"91", + 177 => x"90", + 178 => x"91", + 179 => x"88", + 180 => x"04", + 181 => x"0c", + 182 => x"2d", + 183 => x"08", + 184 => x"90", + 185 => x"94", + 186 => x"ed", + 187 => x"94", + 188 => x"80", + 189 => x"ca", + 190 => x"90", + 191 => x"ca", + 192 => x"c0", + 193 => x"91", + 194 => x"90", + 195 => x"91", + 196 => x"88", + 197 => x"04", + 198 => x"0c", + 199 => x"2d", + 200 => x"08", + 201 => x"90", + 202 => x"94", + 203 => x"9c", + 204 => x"94", + 205 => x"80", + 206 => x"ca", + 207 => x"e9", + 208 => x"ca", + 209 => x"c0", + 210 => x"91", + 211 => x"90", + 212 => x"91", + 213 => x"88", + 214 => x"04", + 215 => x"0c", + 216 => x"2d", + 217 => x"08", + 218 => x"90", + 219 => x"94", + 220 => x"9c", + 221 => x"94", + 222 => x"80", + 223 => x"ca", + 224 => x"f6", + 225 => x"ca", + 226 => x"c0", + 227 => x"91", + 228 => x"90", + 229 => x"91", + 230 => x"88", + 231 => x"04", + 232 => x"0c", + 233 => x"2d", + 234 => x"08", + 235 => x"90", + 236 => x"94", + 237 => x"da", + 238 => x"94", + 239 => x"80", + 240 => x"ca", + 241 => x"f2", + 242 => x"ca", + 243 => x"c0", + 244 => x"91", + 245 => x"90", + 246 => x"91", + 247 => x"88", + 248 => x"04", + 249 => x"0c", + 250 => x"2d", + 251 => x"08", + 252 => x"90", + 253 => x"94", + 254 => x"b7", + 255 => x"94", + 256 => x"80", + 257 => x"ca", + 258 => x"f3", + 259 => x"ca", + 260 => x"c0", + 261 => x"91", + 262 => x"91", + 263 => x"91", + 264 => x"88", + 265 => x"04", + 266 => x"0c", + 267 => x"2d", + 268 => x"08", + 269 => x"90", + 270 => x"94", + 271 => x"ed", + 272 => x"94", + 273 => x"80", + 274 => x"ca", + 275 => x"e9", + 276 => x"ca", + 277 => x"c0", + 278 => x"91", + 279 => x"90", + 280 => x"91", + 281 => x"88", + 282 => x"04", + 283 => x"0c", + 284 => x"2d", + 285 => x"08", + 286 => x"90", + 287 => x"94", + 288 => x"a9", + 289 => x"94", + 290 => x"80", + 291 => x"ca", + 292 => x"84", + 293 => x"ca", + 294 => x"c0", + 295 => x"91", + 296 => x"91", + 297 => x"91", + 298 => x"88", + 299 => x"04", + 300 => x"0c", + 301 => x"2d", + 302 => x"08", + 303 => x"90", + 304 => x"94", + 305 => x"e1", + 306 => x"94", + 307 => x"80", + 308 => x"ca", + 309 => x"ac", + 310 => x"ca", + 311 => x"c0", + 312 => x"91", + 313 => x"90", + 314 => x"91", + 315 => x"88", + 316 => x"04", + 317 => x"0c", + 318 => x"2d", + 319 => x"08", + 320 => x"90", + 321 => x"94", + 322 => x"b2", + 323 => x"94", + 324 => x"80", + 325 => x"ca", + 326 => x"91", + 327 => x"ca", + 328 => x"c0", + 329 => x"91", + 330 => x"90", + 331 => x"91", + 332 => x"88", + 333 => x"04", + 334 => x"0c", + 335 => x"2d", + 336 => x"08", + 337 => x"90", + 338 => x"88", + 339 => x"8c", + 340 => x"80", + 341 => x"05", + 342 => x"0b", + 343 => x"04", + 344 => x"51", + 345 => x"04", + 346 => x"ca", + 347 => x"91", + 348 => x"fd", + 349 => x"53", + 350 => x"08", + 351 => x"52", + 352 => x"08", + 353 => x"51", + 354 => x"91", + 355 => x"70", + 356 => x"0c", + 357 => x"0d", + 358 => x"0c", + 359 => x"94", + 360 => x"ca", + 361 => x"3d", + 362 => x"91", + 363 => x"8c", + 364 => x"91", + 365 => x"88", + 366 => x"93", + 367 => x"88", + 368 => x"ca", + 369 => x"85", + 370 => x"ca", + 371 => x"91", + 372 => x"02", + 373 => x"0c", + 374 => x"81", + 375 => x"94", + 376 => x"0c", + 377 => x"ca", + 378 => x"05", + 379 => x"94", + 380 => x"08", + 381 => x"08", + 382 => x"27", + 383 => x"ca", + 384 => x"05", + 385 => x"ae", + 386 => x"91", + 387 => x"8c", + 388 => x"a2", + 389 => x"94", + 390 => x"08", + 391 => x"94", + 392 => x"0c", + 393 => x"08", + 394 => x"10", + 395 => x"08", + 396 => x"ff", + 397 => x"ca", + 398 => x"05", + 399 => x"80", + 400 => x"ca", + 401 => x"05", + 402 => x"94", + 403 => x"08", + 404 => x"91", + 405 => x"88", + 406 => x"ca", + 407 => x"05", + 408 => x"ca", + 409 => x"05", + 410 => x"94", + 411 => x"08", + 412 => x"08", + 413 => x"07", + 414 => x"08", + 415 => x"91", + 416 => x"fc", + 417 => x"2a", + 418 => x"08", + 419 => x"91", + 420 => x"8c", + 421 => x"2a", + 422 => x"08", + 423 => x"ff", + 424 => x"ca", + 425 => x"05", + 426 => x"93", + 427 => x"94", + 428 => x"08", + 429 => x"94", + 430 => x"0c", + 431 => x"91", + 432 => x"f8", + 433 => x"91", + 434 => x"f4", + 435 => x"91", + 436 => x"f4", + 437 => x"ca", + 438 => x"3d", + 439 => x"94", + 440 => x"3d", + 441 => x"71", + 442 => x"9f", + 443 => x"55", + 444 => x"72", + 445 => x"74", + 446 => x"70", + 447 => x"38", + 448 => x"71", + 449 => x"38", + 450 => x"81", + 451 => x"ff", + 452 => x"ff", + 453 => x"06", + 454 => x"91", + 455 => x"86", + 456 => x"74", + 457 => x"75", + 458 => x"90", + 459 => x"54", + 460 => x"27", + 461 => x"71", + 462 => x"53", + 463 => x"70", + 464 => x"0c", + 465 => x"84", + 466 => x"72", + 467 => x"05", + 468 => x"12", + 469 => x"26", + 470 => x"72", + 471 => x"72", + 472 => x"05", + 473 => x"12", + 474 => x"26", + 475 => x"53", + 476 => x"fb", + 477 => x"79", + 478 => x"83", + 479 => x"52", + 480 => x"71", + 481 => x"54", + 482 => x"73", + 483 => x"c6", + 484 => x"54", + 485 => x"70", + 486 => x"52", + 487 => x"2e", + 488 => x"33", + 489 => x"2e", + 490 => x"95", + 491 => x"81", + 492 => x"70", + 493 => x"54", + 494 => x"70", + 495 => x"33", + 496 => x"ff", + 497 => x"ff", + 498 => x"31", + 499 => x"0c", + 500 => x"3d", + 501 => x"09", + 502 => x"fd", + 503 => x"70", + 504 => x"81", + 505 => x"51", + 506 => x"38", + 507 => x"16", + 508 => x"56", + 509 => x"08", + 510 => x"73", + 511 => x"ff", + 512 => x"0b", + 513 => x"0c", + 514 => x"04", + 515 => x"80", + 516 => x"71", + 517 => x"87", + 518 => x"ca", + 519 => x"ff", + 520 => x"ff", + 521 => x"72", + 522 => x"38", + 523 => x"88", + 524 => x"0d", + 525 => x"0d", + 526 => x"70", + 527 => x"71", + 528 => x"ca", + 529 => x"51", + 530 => x"09", + 531 => x"38", + 532 => x"f1", + 533 => x"84", + 534 => x"53", + 535 => x"70", + 536 => x"53", + 537 => x"a0", + 538 => x"81", + 539 => x"2e", + 540 => x"e5", + 541 => x"ff", + 542 => x"a0", + 543 => x"06", + 544 => x"73", + 545 => x"55", + 546 => x"0c", + 547 => x"91", + 548 => x"87", + 549 => x"fc", + 550 => x"53", + 551 => x"2e", + 552 => x"3d", + 553 => x"72", + 554 => x"3f", + 555 => x"08", + 556 => x"53", + 557 => x"53", + 558 => x"88", + 559 => x"0d", + 560 => x"0d", + 561 => x"33", + 562 => x"53", + 563 => x"8b", + 564 => x"38", + 565 => x"ff", + 566 => x"52", + 567 => x"81", + 568 => x"13", + 569 => x"52", + 570 => x"80", + 571 => x"13", + 572 => x"52", + 573 => x"80", + 574 => x"13", + 575 => x"52", + 576 => x"80", + 577 => x"13", + 578 => x"52", + 579 => x"26", + 580 => x"8a", + 581 => x"87", + 582 => x"e7", + 583 => x"38", + 584 => x"c0", + 585 => x"72", + 586 => x"98", + 587 => x"13", + 588 => x"98", + 589 => x"13", + 590 => x"98", + 591 => x"13", + 592 => x"98", + 593 => x"13", + 594 => x"98", + 595 => x"13", + 596 => x"98", + 597 => x"87", + 598 => x"0c", + 599 => x"98", + 600 => x"0b", + 601 => x"9c", + 602 => x"71", + 603 => x"0c", + 604 => x"04", + 605 => x"7f", + 606 => x"98", + 607 => x"7d", + 608 => x"98", + 609 => x"7d", + 610 => x"c0", + 611 => x"5a", + 612 => x"34", + 613 => x"b4", + 614 => x"83", + 615 => x"c0", + 616 => x"5a", + 617 => x"34", + 618 => x"ac", + 619 => x"85", + 620 => x"c0", + 621 => x"5a", + 622 => x"34", + 623 => x"a4", + 624 => x"88", + 625 => x"c0", + 626 => x"5a", + 627 => x"23", + 628 => x"79", + 629 => x"06", + 630 => x"ff", + 631 => x"86", + 632 => x"85", + 633 => x"84", + 634 => x"83", + 635 => x"82", + 636 => x"7d", + 637 => x"06", + 638 => x"ec", + 639 => x"3f", + 640 => x"04", + 641 => x"02", + 642 => x"70", + 643 => x"2a", + 644 => x"70", + 645 => x"c6", + 646 => x"3d", + 647 => x"3d", + 648 => x"0b", + 649 => x"33", + 650 => x"06", + 651 => x"87", + 652 => x"51", + 653 => x"86", + 654 => x"94", + 655 => x"08", + 656 => x"70", + 657 => x"54", + 658 => x"2e", + 659 => x"91", + 660 => x"06", + 661 => x"d7", + 662 => x"32", + 663 => x"51", + 664 => x"2e", + 665 => x"93", + 666 => x"06", + 667 => x"ff", + 668 => x"81", + 669 => x"87", + 670 => x"52", + 671 => x"86", + 672 => x"94", + 673 => x"72", + 674 => x"ca", + 675 => x"3d", + 676 => x"3d", + 677 => x"05", + 678 => x"91", + 679 => x"70", + 680 => x"57", + 681 => x"c0", + 682 => x"74", + 683 => x"38", + 684 => x"94", + 685 => x"70", + 686 => x"81", + 687 => x"52", + 688 => x"8c", + 689 => x"2a", + 690 => x"51", + 691 => x"38", + 692 => x"70", + 693 => x"51", + 694 => x"8d", + 695 => x"2a", + 696 => x"51", + 697 => x"be", + 698 => x"ff", + 699 => x"c0", + 700 => x"70", + 701 => x"38", + 702 => x"90", + 703 => x"0c", + 704 => x"04", + 705 => x"79", + 706 => x"33", + 707 => x"06", + 708 => x"70", + 709 => x"fe", + 710 => x"ff", + 711 => x"0b", + 712 => x"e0", + 713 => x"ff", + 714 => x"55", + 715 => x"94", + 716 => x"80", + 717 => x"87", + 718 => x"51", + 719 => x"96", + 720 => x"06", + 721 => x"70", + 722 => x"38", + 723 => x"70", + 724 => x"51", + 725 => x"72", + 726 => x"81", + 727 => x"70", + 728 => x"38", + 729 => x"70", + 730 => x"51", + 731 => x"38", + 732 => x"06", + 733 => x"94", + 734 => x"80", + 735 => x"87", + 736 => x"52", + 737 => x"81", + 738 => x"70", + 739 => x"53", + 740 => x"ff", + 741 => x"91", + 742 => x"89", + 743 => x"fe", + 744 => x"0b", + 745 => x"33", + 746 => x"06", + 747 => x"c0", + 748 => x"72", + 749 => x"38", + 750 => x"94", + 751 => x"70", + 752 => x"81", + 753 => x"51", + 754 => x"e2", + 755 => x"ff", + 756 => x"c0", + 757 => x"70", + 758 => x"38", + 759 => x"90", + 760 => x"70", + 761 => x"91", + 762 => x"51", + 763 => x"04", + 764 => x"0b", + 765 => x"e0", + 766 => x"ff", + 767 => x"87", + 768 => x"52", + 769 => x"86", + 770 => x"94", + 771 => x"08", + 772 => x"70", + 773 => x"51", + 774 => x"70", + 775 => x"38", + 776 => x"06", + 777 => x"94", + 778 => x"80", + 779 => x"87", + 780 => x"52", + 781 => x"98", + 782 => x"2c", + 783 => x"71", + 784 => x"0c", + 785 => x"04", + 786 => x"87", + 787 => x"08", + 788 => x"8a", + 789 => x"70", + 790 => x"93", + 791 => x"9e", + 792 => x"c6", + 793 => x"c0", + 794 => x"91", + 795 => x"87", + 796 => x"08", + 797 => x"0c", + 798 => x"90", + 799 => x"f0", + 800 => x"9e", + 801 => x"c6", + 802 => x"c0", + 803 => x"91", + 804 => x"87", + 805 => x"08", + 806 => x"0c", + 807 => x"a8", + 808 => x"80", + 809 => x"9e", + 810 => x"c7", + 811 => x"c0", + 812 => x"51", + 813 => x"88", + 814 => x"9e", + 815 => x"c7", + 816 => x"0b", + 817 => x"34", + 818 => x"c0", + 819 => x"70", + 820 => x"51", + 821 => x"80", + 822 => x"81", + 823 => x"c7", + 824 => x"0b", + 825 => x"88", + 826 => x"80", + 827 => x"52", + 828 => x"2e", + 829 => x"52", + 830 => x"92", + 831 => x"87", + 832 => x"08", + 833 => x"80", + 834 => x"52", + 835 => x"83", + 836 => x"71", + 837 => x"34", + 838 => x"c0", + 839 => x"70", + 840 => x"51", + 841 => x"80", + 842 => x"81", + 843 => x"c7", + 844 => x"0b", + 845 => x"88", + 846 => x"80", + 847 => x"52", + 848 => x"83", + 849 => x"71", + 850 => x"34", + 851 => x"c0", + 852 => x"70", + 853 => x"51", + 854 => x"80", + 855 => x"81", + 856 => x"c7", + 857 => x"0b", + 858 => x"88", + 859 => x"80", + 860 => x"52", + 861 => x"83", + 862 => x"71", + 863 => x"34", + 864 => x"c0", + 865 => x"70", + 866 => x"51", + 867 => x"80", + 868 => x"81", + 869 => x"c7", + 870 => x"c0", + 871 => x"70", + 872 => x"70", + 873 => x"51", + 874 => x"c7", + 875 => x"0b", + 876 => x"88", + 877 => x"06", + 878 => x"70", + 879 => x"38", + 880 => x"91", + 881 => x"80", + 882 => x"9e", + 883 => x"88", + 884 => x"52", + 885 => x"83", + 886 => x"71", + 887 => x"34", + 888 => x"88", + 889 => x"06", + 890 => x"91", + 891 => x"83", + 892 => x"fd", + 893 => x"b4", + 894 => x"a3", + 895 => x"90", + 896 => x"80", + 897 => x"91", + 898 => x"84", + 899 => x"b4", + 900 => x"8b", + 901 => x"91", + 902 => x"80", + 903 => x"91", + 904 => x"53", + 905 => x"08", + 906 => x"c4", + 907 => x"3f", + 908 => x"33", + 909 => x"2e", + 910 => x"c6", + 911 => x"91", + 912 => x"52", + 913 => x"51", + 914 => x"91", + 915 => x"54", + 916 => x"91", + 917 => x"54", + 918 => x"92", + 919 => x"f8", + 920 => x"c6", + 921 => x"91", + 922 => x"89", + 923 => x"c7", + 924 => x"73", + 925 => x"38", + 926 => x"51", + 927 => x"91", + 928 => x"54", + 929 => x"88", + 930 => x"c0", + 931 => x"3f", + 932 => x"33", + 933 => x"2e", + 934 => x"b5", + 935 => x"ff", + 936 => x"98", + 937 => x"80", + 938 => x"91", + 939 => x"52", + 940 => x"51", + 941 => x"91", + 942 => x"54", + 943 => x"88", + 944 => x"f8", + 945 => x"3f", + 946 => x"33", + 947 => x"2e", + 948 => x"c7", + 949 => x"91", + 950 => x"88", + 951 => x"b6", + 952 => x"bb", + 953 => x"fc", + 954 => x"b6", + 955 => x"93", + 956 => x"80", + 957 => x"b6", + 958 => x"87", + 959 => x"84", + 960 => x"b7", + 961 => x"fb", + 962 => x"88", + 963 => x"b7", + 964 => x"ef", + 965 => x"8c", + 966 => x"b7", + 967 => x"e3", + 968 => x"0d", + 969 => x"0d", + 970 => x"33", + 971 => x"71", + 972 => x"38", + 973 => x"0b", + 974 => x"88", + 975 => x"08", + 976 => x"84", + 977 => x"91", + 978 => x"97", + 979 => x"94", + 980 => x"91", + 981 => x"8b", + 982 => x"a0", + 983 => x"91", + 984 => x"f7", + 985 => x"3d", + 986 => x"88", + 987 => x"80", + 988 => x"96", + 989 => x"ff", + 990 => x"c0", + 991 => x"08", + 992 => x"72", + 993 => x"07", + 994 => x"a0", + 995 => x"83", + 996 => x"ff", + 997 => x"c0", + 998 => x"08", + 999 => x"0c", + 1000 => x"0c", + 1001 => x"91", + 1002 => x"06", + 1003 => x"a0", + 1004 => x"51", + 1005 => x"04", + 1006 => x"08", + 1007 => x"84", + 1008 => x"3d", + 1009 => x"05", + 1010 => x"8a", + 1011 => x"06", + 1012 => x"51", + 1013 => x"ca", + 1014 => x"71", + 1015 => x"38", + 1016 => x"91", + 1017 => x"81", + 1018 => x"a0", + 1019 => x"91", + 1020 => x"52", + 1021 => x"85", + 1022 => x"71", + 1023 => x"0d", + 1024 => x"0d", + 1025 => x"33", + 1026 => x"08", + 1027 => x"98", + 1028 => x"ff", + 1029 => x"91", + 1030 => x"84", + 1031 => x"fd", + 1032 => x"54", + 1033 => x"81", + 1034 => x"53", + 1035 => x"8e", + 1036 => x"ff", + 1037 => x"14", + 1038 => x"3f", + 1039 => x"3d", + 1040 => x"3d", + 1041 => x"ca", + 1042 => x"91", + 1043 => x"56", + 1044 => x"70", + 1045 => x"53", + 1046 => x"2e", + 1047 => x"81", + 1048 => x"81", + 1049 => x"da", + 1050 => x"74", + 1051 => x"0c", + 1052 => x"04", + 1053 => x"66", + 1054 => x"78", + 1055 => x"5a", + 1056 => x"80", + 1057 => x"38", + 1058 => x"09", + 1059 => x"de", + 1060 => x"7a", + 1061 => x"5c", + 1062 => x"5b", + 1063 => x"09", + 1064 => x"38", + 1065 => x"39", + 1066 => x"09", + 1067 => x"38", + 1068 => x"70", + 1069 => x"33", + 1070 => x"2e", + 1071 => x"92", + 1072 => x"19", + 1073 => x"70", + 1074 => x"33", + 1075 => x"53", + 1076 => x"16", + 1077 => x"26", + 1078 => x"88", + 1079 => x"05", + 1080 => x"05", + 1081 => x"05", + 1082 => x"5b", + 1083 => x"80", + 1084 => x"30", + 1085 => x"80", + 1086 => x"cc", + 1087 => x"70", + 1088 => x"25", + 1089 => x"54", + 1090 => x"53", + 1091 => x"8c", + 1092 => x"07", + 1093 => x"05", + 1094 => x"5a", + 1095 => x"83", + 1096 => x"54", + 1097 => x"27", + 1098 => x"16", + 1099 => x"06", + 1100 => x"80", + 1101 => x"aa", + 1102 => x"cf", + 1103 => x"73", + 1104 => x"81", + 1105 => x"80", + 1106 => x"38", + 1107 => x"2e", + 1108 => x"81", + 1109 => x"80", + 1110 => x"8a", + 1111 => x"39", + 1112 => x"2e", + 1113 => x"73", + 1114 => x"8a", + 1115 => x"d3", + 1116 => x"80", + 1117 => x"80", + 1118 => x"ee", + 1119 => x"39", + 1120 => x"71", + 1121 => x"53", + 1122 => x"54", + 1123 => x"2e", + 1124 => x"15", + 1125 => x"33", + 1126 => x"72", + 1127 => x"81", + 1128 => x"39", + 1129 => x"56", + 1130 => x"27", + 1131 => x"51", + 1132 => x"75", + 1133 => x"72", + 1134 => x"38", + 1135 => x"df", + 1136 => x"16", + 1137 => x"7b", + 1138 => x"38", + 1139 => x"f2", + 1140 => x"77", + 1141 => x"12", + 1142 => x"53", + 1143 => x"5c", + 1144 => x"5c", + 1145 => x"5c", + 1146 => x"5c", + 1147 => x"51", + 1148 => x"fd", + 1149 => x"82", + 1150 => x"06", + 1151 => x"80", + 1152 => x"77", + 1153 => x"53", + 1154 => x"18", + 1155 => x"72", + 1156 => x"c4", + 1157 => x"70", + 1158 => x"25", + 1159 => x"55", + 1160 => x"8d", + 1161 => x"2e", + 1162 => x"30", + 1163 => x"5b", + 1164 => x"8f", + 1165 => x"7b", + 1166 => x"e6", + 1167 => x"ca", + 1168 => x"ff", + 1169 => x"75", + 1170 => x"9e", + 1171 => x"88", + 1172 => x"74", + 1173 => x"a7", + 1174 => x"80", + 1175 => x"38", + 1176 => x"72", + 1177 => x"54", + 1178 => x"72", + 1179 => x"05", + 1180 => x"17", + 1181 => x"77", + 1182 => x"51", + 1183 => x"9f", + 1184 => x"72", + 1185 => x"79", + 1186 => x"81", + 1187 => x"72", + 1188 => x"38", + 1189 => x"05", + 1190 => x"ad", + 1191 => x"17", + 1192 => x"81", + 1193 => x"b0", + 1194 => x"38", + 1195 => x"81", + 1196 => x"06", + 1197 => x"9f", + 1198 => x"55", + 1199 => x"97", + 1200 => x"f9", + 1201 => x"81", + 1202 => x"8b", + 1203 => x"16", + 1204 => x"73", + 1205 => x"96", + 1206 => x"e0", + 1207 => x"17", + 1208 => x"33", + 1209 => x"f9", + 1210 => x"f2", + 1211 => x"16", + 1212 => x"7b", + 1213 => x"38", + 1214 => x"c6", + 1215 => x"96", + 1216 => x"fd", + 1217 => x"3d", + 1218 => x"05", + 1219 => x"52", + 1220 => x"e0", + 1221 => x"0d", + 1222 => x"0d", + 1223 => x"a0", + 1224 => x"88", + 1225 => x"51", + 1226 => x"91", + 1227 => x"53", + 1228 => x"80", + 1229 => x"a0", + 1230 => x"0d", + 1231 => x"0d", + 1232 => x"08", + 1233 => x"98", + 1234 => x"88", + 1235 => x"52", + 1236 => x"3f", + 1237 => x"98", + 1238 => x"0d", + 1239 => x"0d", + 1240 => x"ca", + 1241 => x"56", + 1242 => x"80", + 1243 => x"2e", + 1244 => x"91", + 1245 => x"52", + 1246 => x"ca", + 1247 => x"ff", + 1248 => x"80", + 1249 => x"38", + 1250 => x"b9", + 1251 => x"32", + 1252 => x"80", + 1253 => x"52", + 1254 => x"8b", + 1255 => x"2e", + 1256 => x"14", + 1257 => x"9f", + 1258 => x"38", + 1259 => x"73", + 1260 => x"38", + 1261 => x"72", + 1262 => x"14", + 1263 => x"f8", + 1264 => x"af", + 1265 => x"52", + 1266 => x"8a", + 1267 => x"3f", + 1268 => x"91", + 1269 => x"87", + 1270 => x"fe", + 1271 => x"ca", + 1272 => x"91", + 1273 => x"77", + 1274 => x"53", + 1275 => x"72", + 1276 => x"0c", + 1277 => x"04", + 1278 => x"7a", + 1279 => x"80", + 1280 => x"58", + 1281 => x"33", + 1282 => x"a0", + 1283 => x"06", + 1284 => x"13", + 1285 => x"39", + 1286 => x"09", + 1287 => x"38", + 1288 => x"11", + 1289 => x"08", + 1290 => x"54", + 1291 => x"2e", + 1292 => x"80", + 1293 => x"08", + 1294 => x"0c", + 1295 => x"33", + 1296 => x"80", + 1297 => x"38", + 1298 => x"80", + 1299 => x"38", + 1300 => x"57", + 1301 => x"0c", + 1302 => x"33", + 1303 => x"39", + 1304 => x"74", + 1305 => x"38", + 1306 => x"80", + 1307 => x"89", + 1308 => x"38", + 1309 => x"d0", + 1310 => x"55", + 1311 => x"80", + 1312 => x"39", + 1313 => x"d9", + 1314 => x"80", + 1315 => x"27", + 1316 => x"80", + 1317 => x"89", + 1318 => x"70", + 1319 => x"55", + 1320 => x"70", + 1321 => x"55", + 1322 => x"27", + 1323 => x"14", + 1324 => x"06", + 1325 => x"74", + 1326 => x"73", + 1327 => x"38", + 1328 => x"14", + 1329 => x"05", + 1330 => x"08", + 1331 => x"54", + 1332 => x"39", + 1333 => x"84", + 1334 => x"55", + 1335 => x"81", + 1336 => x"ca", + 1337 => x"3d", + 1338 => x"3d", + 1339 => x"5a", + 1340 => x"7a", + 1341 => x"08", + 1342 => x"53", + 1343 => x"09", + 1344 => x"38", + 1345 => x"0c", + 1346 => x"ad", + 1347 => x"06", + 1348 => x"76", + 1349 => x"0c", + 1350 => x"33", + 1351 => x"73", + 1352 => x"81", + 1353 => x"38", + 1354 => x"05", + 1355 => x"08", + 1356 => x"53", + 1357 => x"2e", + 1358 => x"57", + 1359 => x"2e", + 1360 => x"39", + 1361 => x"13", + 1362 => x"08", + 1363 => x"53", + 1364 => x"55", + 1365 => x"80", + 1366 => x"14", + 1367 => x"88", + 1368 => x"27", + 1369 => x"eb", + 1370 => x"53", + 1371 => x"89", + 1372 => x"38", + 1373 => x"55", + 1374 => x"8a", + 1375 => x"a0", + 1376 => x"c2", + 1377 => x"74", + 1378 => x"e0", + 1379 => x"ff", + 1380 => x"d0", + 1381 => x"ff", + 1382 => x"90", + 1383 => x"38", + 1384 => x"81", + 1385 => x"53", + 1386 => x"ca", + 1387 => x"27", + 1388 => x"77", + 1389 => x"08", + 1390 => x"0c", + 1391 => x"33", + 1392 => x"ff", + 1393 => x"80", + 1394 => x"74", + 1395 => x"79", + 1396 => x"74", + 1397 => x"0c", + 1398 => x"04", + 1399 => x"02", + 1400 => x"51", + 1401 => x"72", + 1402 => x"91", + 1403 => x"33", + 1404 => x"ca", + 1405 => x"3d", + 1406 => x"3d", + 1407 => x"05", + 1408 => x"05", + 1409 => x"56", + 1410 => x"72", + 1411 => x"e0", + 1412 => x"2b", + 1413 => x"8c", + 1414 => x"88", + 1415 => x"2e", + 1416 => x"88", + 1417 => x"0c", + 1418 => x"8c", + 1419 => x"71", + 1420 => x"87", + 1421 => x"0c", + 1422 => x"08", + 1423 => x"51", + 1424 => x"2e", + 1425 => x"c0", + 1426 => x"51", + 1427 => x"71", + 1428 => x"80", + 1429 => x"92", + 1430 => x"98", + 1431 => x"70", + 1432 => x"38", + 1433 => x"a4", + 1434 => x"c7", + 1435 => x"51", + 1436 => x"88", + 1437 => x"0d", + 1438 => x"0d", + 1439 => x"02", + 1440 => x"05", + 1441 => x"58", + 1442 => x"52", + 1443 => x"3f", + 1444 => x"08", + 1445 => x"54", + 1446 => x"be", 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x"2e", + 1506 => x"81", + 1507 => x"74", + 1508 => x"c0", + 1509 => x"87", + 1510 => x"12", + 1511 => x"84", + 1512 => x"5f", + 1513 => x"0b", + 1514 => x"8c", + 1515 => x"0c", + 1516 => x"80", + 1517 => x"70", + 1518 => x"81", + 1519 => x"54", + 1520 => x"8c", + 1521 => x"81", + 1522 => x"7c", + 1523 => x"58", + 1524 => x"70", + 1525 => x"52", + 1526 => x"8a", + 1527 => x"98", + 1528 => x"71", + 1529 => x"c0", + 1530 => x"52", + 1531 => x"87", + 1532 => x"80", + 1533 => x"81", + 1534 => x"c0", + 1535 => x"53", + 1536 => x"82", + 1537 => x"71", + 1538 => x"19", + 1539 => x"81", + 1540 => x"ff", + 1541 => x"19", + 1542 => x"78", + 1543 => x"38", + 1544 => x"80", + 1545 => x"87", + 1546 => x"26", + 1547 => x"73", + 1548 => x"06", + 1549 => x"2e", + 1550 => x"52", + 1551 => x"91", + 1552 => x"8f", + 1553 => x"f6", + 1554 => x"02", + 1555 => x"05", + 1556 => x"05", + 1557 => x"71", + 1558 => x"57", + 1559 => x"91", + 1560 => x"81", + 1561 => x"54", + 1562 => x"38", + 1563 => x"c0", + 1564 => x"81", + 1565 => x"2e", + 1566 => x"71", + 1567 => x"38", + 1568 => x"87", + 1569 => x"11", + 1570 => x"80", + 1571 => x"80", + 1572 => x"83", + 1573 => x"38", + 1574 => x"72", + 1575 => x"2a", + 1576 => x"51", + 1577 => x"80", + 1578 => x"87", + 1579 => x"08", + 1580 => x"38", + 1581 => x"8c", + 1582 => x"96", + 1583 => x"0c", + 1584 => x"8c", + 1585 => x"08", + 1586 => x"51", + 1587 => x"38", + 1588 => x"56", + 1589 => x"80", + 1590 => x"85", + 1591 => x"77", + 1592 => x"83", + 1593 => x"75", + 1594 => x"ca", + 1595 => x"3d", + 1596 => x"3d", + 1597 => x"11", + 1598 => x"71", + 1599 => x"91", + 1600 => x"53", + 1601 => x"0d", + 1602 => x"0d", + 1603 => x"33", + 1604 => x"71", + 1605 => x"88", + 1606 => x"14", + 1607 => x"07", + 1608 => x"33", + 1609 => x"ca", + 1610 => x"53", + 1611 => x"52", + 1612 => x"04", + 1613 => x"73", + 1614 => x"92", + 1615 => x"52", + 1616 => x"81", + 1617 => x"70", + 1618 => x"70", + 1619 => x"3d", + 1620 => x"3d", + 1621 => x"52", + 1622 => x"70", + 1623 => x"34", + 1624 => x"51", + 1625 => x"81", + 1626 => x"70", + 1627 => x"70", + 1628 => x"05", + 1629 => x"88", + 1630 => x"72", + 1631 => x"0d", + 1632 => x"0d", + 1633 => x"54", + 1634 => x"80", + 1635 => x"71", + 1636 => x"53", + 1637 => x"81", + 1638 => x"ff", + 1639 => x"39", + 1640 => x"04", + 1641 => x"75", + 1642 => x"52", + 1643 => x"70", + 1644 => x"34", + 1645 => x"70", + 1646 => x"3d", + 1647 => x"3d", + 1648 => x"79", + 1649 => x"74", + 1650 => x"56", + 1651 => x"81", + 1652 => x"71", + 1653 => x"16", + 1654 => x"52", + 1655 => x"86", + 1656 => x"2e", + 1657 => x"91", + 1658 => x"86", + 1659 => x"fe", + 1660 => x"76", + 1661 => x"39", + 1662 => x"8a", + 1663 => x"51", + 1664 => x"71", + 1665 => x"33", + 1666 => x"0c", + 1667 => x"04", + 1668 => x"ca", + 1669 => x"80", + 1670 => x"88", + 1671 => x"3d", + 1672 => x"80", + 1673 => x"33", + 1674 => x"7a", + 1675 => x"38", + 1676 => x"16", + 1677 => x"16", + 1678 => x"17", + 1679 => x"fa", + 1680 => x"ca", + 1681 => x"2e", + 1682 => x"b7", + 1683 => x"88", + 1684 => x"34", + 1685 => x"70", + 1686 => x"31", + 1687 => x"59", + 1688 => x"77", + 1689 => x"82", + 1690 => x"74", + 1691 => x"81", + 1692 => x"81", + 1693 => x"53", + 1694 => x"16", + 1695 => x"e3", + 1696 => x"81", + 1697 => x"ca", + 1698 => x"3d", + 1699 => x"3d", + 1700 => x"56", + 1701 => x"74", + 1702 => x"2e", + 1703 => x"51", + 1704 => x"91", + 1705 => x"57", + 1706 => x"08", + 1707 => x"54", + 1708 => x"16", + 1709 => x"33", + 1710 => x"3f", + 1711 => x"08", + 1712 => x"38", + 1713 => x"57", + 1714 => x"0c", + 1715 => x"88", + 1716 => x"0d", + 1717 => x"0d", + 1718 => x"57", + 1719 => x"91", + 1720 => x"58", + 1721 => x"08", + 1722 => x"76", + 1723 => x"83", + 1724 => x"06", + 1725 => x"84", + 1726 => x"78", + 1727 => x"81", + 1728 => x"38", + 1729 => x"91", + 1730 => x"52", + 1731 => x"52", + 1732 => x"3f", + 1733 => x"52", + 1734 => x"51", + 1735 => x"84", + 1736 => x"d2", + 1737 => x"fc", + 1738 => x"8a", + 1739 => x"52", + 1740 => x"51", + 1741 => x"90", + 1742 => x"84", + 1743 => x"fc", + 1744 => x"17", + 1745 => x"a0", + 1746 => x"86", + 1747 => x"08", + 1748 => x"b0", + 1749 => x"55", + 1750 => x"81", + 1751 => x"f8", + 1752 => x"84", + 1753 => x"53", + 1754 => x"17", + 1755 => x"d7", + 1756 => x"88", + 1757 => x"83", + 1758 => x"77", + 1759 => x"0c", + 1760 => x"04", + 1761 => x"77", + 1762 => x"12", + 1763 => x"55", + 1764 => x"56", + 1765 => x"8d", + 1766 => x"22", + 1767 => x"ac", + 1768 => x"57", + 1769 => x"ca", + 1770 => x"3d", + 1771 => x"3d", + 1772 => x"70", + 1773 => x"57", + 1774 => x"81", + 1775 => x"98", + 1776 => x"81", + 1777 => x"74", + 1778 => x"72", + 1779 => x"f5", + 1780 => x"24", + 1781 => x"81", + 1782 => x"81", + 1783 => x"83", + 1784 => x"38", + 1785 => x"76", + 1786 => x"70", + 1787 => x"16", + 1788 => x"74", + 1789 => x"96", + 1790 => x"88", + 1791 => x"38", + 1792 => x"06", + 1793 => x"33", + 1794 => x"89", + 1795 => x"08", + 1796 => x"54", + 1797 => x"fc", + 1798 => x"ca", + 1799 => x"fe", + 1800 => x"ff", + 1801 => x"11", + 1802 => x"2b", + 1803 => x"81", + 1804 => x"2a", + 1805 => x"51", + 1806 => x"e2", + 1807 => x"ff", + 1808 => x"da", + 1809 => x"2a", + 1810 => x"05", + 1811 => x"fc", + 1812 => x"ca", + 1813 => x"c6", + 1814 => x"83", + 1815 => x"05", + 1816 => x"f9", + 1817 => x"ca", + 1818 => x"ff", + 1819 => x"ae", + 1820 => x"2a", + 1821 => x"05", + 1822 => x"fc", + 1823 => x"ca", + 1824 => x"38", + 1825 => x"83", + 1826 => x"05", + 1827 => x"f8", + 1828 => x"ca", + 1829 => x"0a", + 1830 => x"39", + 1831 => x"91", + 1832 => x"89", + 1833 => x"f8", + 1834 => x"7c", + 1835 => x"56", + 1836 => x"77", + 1837 => x"38", + 1838 => x"08", + 1839 => x"38", + 1840 => x"72", + 1841 => x"9d", + 1842 => x"24", + 1843 => x"81", + 1844 => x"82", + 1845 => x"83", + 1846 => x"38", + 1847 => x"76", + 1848 => x"70", + 1849 => x"18", + 1850 => x"76", + 1851 => x"9e", + 1852 => x"88", + 1853 => x"ca", + 1854 => x"d9", + 1855 => x"ff", + 1856 => x"05", + 1857 => x"81", + 1858 => x"54", + 1859 => x"80", + 1860 => x"77", + 1861 => x"f0", + 1862 => x"8f", + 1863 => x"51", + 1864 => x"34", + 1865 => x"17", + 1866 => x"2a", + 1867 => x"05", + 1868 => x"fa", + 1869 => x"ca", + 1870 => x"91", + 1871 => x"81", + 1872 => x"83", + 1873 => x"b4", + 1874 => x"2a", + 1875 => x"8f", + 1876 => x"2a", + 1877 => x"f0", + 1878 => x"06", + 1879 => x"72", + 1880 => x"ec", + 1881 => x"2a", + 1882 => x"05", + 1883 => x"fa", + 1884 => x"ca", + 1885 => x"91", + 1886 => x"80", + 1887 => x"83", + 1888 => x"52", + 1889 => x"fe", + 1890 => x"b4", + 1891 => x"a4", + 1892 => x"76", + 1893 => x"17", + 1894 => x"75", + 1895 => x"3f", + 1896 => x"08", + 1897 => x"88", + 1898 => x"77", + 1899 => x"77", + 1900 => x"fc", + 1901 => x"b4", + 1902 => x"51", + 1903 => x"c9", + 1904 => x"88", + 1905 => x"06", + 1906 => x"72", + 1907 => x"3f", + 1908 => x"17", + 1909 => x"ca", + 1910 => x"3d", + 1911 => x"3d", + 1912 => x"7e", + 1913 => x"56", + 1914 => x"75", + 1915 => x"74", + 1916 => x"27", + 1917 => x"80", + 1918 => x"ff", + 1919 => x"75", + 1920 => x"3f", + 1921 => x"08", + 1922 => x"88", + 1923 => x"38", + 1924 => x"54", + 1925 => x"81", + 1926 => x"39", + 1927 => x"08", + 1928 => x"39", + 1929 => x"51", + 1930 => x"91", + 1931 => x"58", + 1932 => x"08", + 1933 => x"c7", + 1934 => x"88", + 1935 => x"d2", + 1936 => x"88", + 1937 => x"cf", + 1938 => x"74", + 1939 => x"fc", + 1940 => x"ca", + 1941 => x"38", + 1942 => x"fe", + 1943 => x"08", + 1944 => x"74", + 1945 => x"38", + 1946 => x"17", + 1947 => x"33", + 1948 => x"73", + 1949 => x"77", + 1950 => x"26", + 1951 => x"80", + 1952 => x"ca", + 1953 => x"3d", + 1954 => x"3d", + 1955 => x"71", + 1956 => x"5b", + 1957 => x"8c", + 1958 => x"77", + 1959 => x"38", + 1960 => x"78", + 1961 => x"81", + 1962 => x"79", + 1963 => x"f9", + 1964 => x"55", + 1965 => x"88", + 1966 => x"e0", + 1967 => x"88", + 1968 => x"ca", + 1969 => x"2e", + 1970 => x"98", + 1971 => x"ca", + 1972 => x"82", + 1973 => x"58", + 1974 => x"70", + 1975 => x"80", + 1976 => x"38", + 1977 => x"09", + 1978 => x"e2", + 1979 => x"56", + 1980 => x"76", + 1981 => x"82", + 1982 => x"7a", + 1983 => x"3f", + 1984 => x"ca", + 1985 => x"2e", + 1986 => x"86", + 1987 => x"88", + 1988 => x"ca", + 1989 => x"70", + 1990 => x"07", + 1991 => x"7c", + 1992 => x"88", + 1993 => x"51", + 1994 => x"81", + 1995 => x"ca", + 1996 => x"2e", + 1997 => x"17", + 1998 => x"74", + 1999 => x"73", + 2000 => x"27", + 2001 => x"58", + 2002 => x"80", + 2003 => x"56", + 2004 => x"98", + 2005 => x"26", + 2006 => x"56", + 2007 => x"81", + 2008 => x"52", + 2009 => x"c6", + 2010 => x"88", + 2011 => x"b8", + 2012 => x"91", + 2013 => x"81", + 2014 => x"06", + 2015 => x"ca", + 2016 => x"91", + 2017 => x"09", + 2018 => x"72", + 2019 => x"70", + 2020 => x"51", + 2021 => x"80", + 2022 => x"78", + 2023 => x"06", + 2024 => x"73", + 2025 => x"39", + 2026 => x"52", + 2027 => x"f7", + 2028 => x"88", + 2029 => x"88", + 2030 => x"91", + 2031 => x"07", + 2032 => x"55", + 2033 => x"2e", + 2034 => x"80", + 2035 => x"75", + 2036 => x"76", + 2037 => x"3f", + 2038 => x"08", + 2039 => x"38", + 2040 => x"0c", + 2041 => x"fe", + 2042 => x"08", + 2043 => x"74", + 2044 => x"ff", + 2045 => x"0c", + 2046 => x"81", + 2047 => x"84", + 2048 => x"39", + 2049 => x"81", + 2050 => x"8c", + 2051 => x"8c", + 2052 => x"88", + 2053 => x"39", + 2054 => x"55", + 2055 => x"88", + 2056 => x"0d", + 2057 => x"0d", + 2058 => x"55", + 2059 => x"91", + 2060 => x"58", + 2061 => x"ca", + 2062 => x"d8", + 2063 => x"74", + 2064 => x"3f", + 2065 => x"08", + 2066 => x"08", + 2067 => x"59", + 2068 => x"77", + 2069 => x"70", + 2070 => x"c8", + 2071 => x"84", + 2072 => x"56", + 2073 => x"58", + 2074 => x"97", + 2075 => x"75", + 2076 => x"52", + 2077 => x"51", + 2078 => x"91", + 2079 => x"80", + 2080 => x"8a", + 2081 => x"32", + 2082 => x"72", + 2083 => x"2a", + 2084 => x"56", + 2085 => x"88", + 2086 => x"0d", + 2087 => x"0d", + 2088 => x"08", + 2089 => x"74", + 2090 => x"26", + 2091 => x"74", + 2092 => x"72", + 2093 => x"74", + 2094 => x"88", + 2095 => x"73", + 2096 => x"33", + 2097 => x"27", + 2098 => x"16", + 2099 => x"9b", + 2100 => x"2a", + 2101 => x"88", + 2102 => x"58", + 2103 => x"80", + 2104 => x"16", + 2105 => x"0c", + 2106 => x"8a", + 2107 => x"89", + 2108 => x"72", + 2109 => x"38", + 2110 => x"51", + 2111 => x"91", + 2112 => x"54", + 2113 => x"08", + 2114 => x"38", + 2115 => x"ca", + 2116 => x"8b", + 2117 => x"08", + 2118 => x"08", + 2119 => x"82", + 2120 => x"74", + 2121 => x"cb", + 2122 => x"75", + 2123 => x"3f", + 2124 => x"08", + 2125 => x"73", + 2126 => x"98", + 2127 => x"82", + 2128 => x"2e", + 2129 => x"39", + 2130 => x"39", + 2131 => x"13", + 2132 => x"74", + 2133 => x"16", + 2134 => x"18", + 2135 => x"77", + 2136 => x"0c", + 2137 => x"04", + 2138 => x"7a", + 2139 => x"12", + 2140 => x"59", + 2141 => x"80", + 2142 => x"86", + 2143 => x"98", + 2144 => x"14", + 2145 => x"55", + 2146 => x"81", + 2147 => x"83", + 2148 => x"77", + 2149 => x"81", + 2150 => x"0c", + 2151 => x"55", + 2152 => x"76", + 2153 => x"17", + 2154 => x"74", + 2155 => x"9b", + 2156 => x"39", + 2157 => x"ff", + 2158 => x"2a", + 2159 => x"81", + 2160 => x"52", + 2161 => x"e6", + 2162 => x"88", + 2163 => x"55", + 2164 => x"ca", + 2165 => x"80", + 2166 => x"55", + 2167 => x"08", + 2168 => x"f4", + 2169 => x"08", + 2170 => x"08", + 2171 => x"38", + 2172 => x"77", + 2173 => x"84", + 2174 => x"39", + 2175 => x"52", + 2176 => x"86", + 2177 => x"88", + 2178 => x"55", + 2179 => x"08", + 2180 => x"c4", + 2181 => x"91", + 2182 => x"81", + 2183 => x"81", + 2184 => x"88", + 2185 => x"b0", + 2186 => x"88", + 2187 => x"51", + 2188 => x"91", + 2189 => x"a0", + 2190 => x"15", + 2191 => x"75", + 2192 => x"3f", + 2193 => x"08", + 2194 => x"76", + 2195 => x"77", + 2196 => x"9c", + 2197 => x"55", + 2198 => x"88", + 2199 => x"0d", + 2200 => x"0d", + 2201 => x"08", + 2202 => x"80", + 2203 => x"fc", + 2204 => x"ca", + 2205 => x"91", + 2206 => x"80", + 2207 => x"ca", + 2208 => x"98", + 2209 => x"78", + 2210 => x"3f", + 2211 => x"08", + 2212 => x"88", + 2213 => x"38", + 2214 => x"08", + 2215 => x"70", + 2216 => x"58", + 2217 => x"2e", + 2218 => x"83", + 2219 => x"91", + 2220 => x"55", + 2221 => x"81", + 2222 => x"07", + 2223 => x"2e", + 2224 => x"16", + 2225 => x"2e", + 2226 => x"88", + 2227 => x"91", + 2228 => x"56", + 2229 => x"51", + 2230 => x"91", + 2231 => x"54", + 2232 => x"08", + 2233 => x"9b", + 2234 => x"2e", + 2235 => x"83", + 2236 => x"73", + 2237 => x"0c", + 2238 => x"04", + 2239 => x"76", + 2240 => x"54", + 2241 => x"91", + 2242 => x"83", + 2243 => x"76", + 2244 => x"53", + 2245 => x"2e", + 2246 => x"90", + 2247 => x"51", + 2248 => x"91", + 2249 => x"90", + 2250 => x"53", + 2251 => x"88", + 2252 => x"0d", + 2253 => x"0d", + 2254 => x"83", + 2255 => x"54", + 2256 => x"55", + 2257 => x"3f", + 2258 => x"51", + 2259 => x"2e", + 2260 => x"8b", + 2261 => x"2a", + 2262 => x"51", + 2263 => x"86", + 2264 => x"f7", + 2265 => x"7d", + 2266 => x"75", + 2267 => x"98", + 2268 => x"2e", + 2269 => x"98", + 2270 => x"78", + 2271 => x"3f", + 2272 => x"08", + 2273 => x"88", + 2274 => x"38", + 2275 => x"70", + 2276 => x"73", + 2277 => x"58", + 2278 => x"8b", + 2279 => x"bf", + 2280 => x"ff", + 2281 => x"53", + 2282 => x"34", + 2283 => x"08", + 2284 => x"e5", + 2285 => x"81", + 2286 => x"2e", + 2287 => x"70", + 2288 => x"57", + 2289 => x"9e", + 2290 => x"2e", + 2291 => x"ca", + 2292 => x"df", + 2293 => x"72", + 2294 => x"81", + 2295 => x"76", + 2296 => x"2e", + 2297 => x"52", + 2298 => x"fc", + 2299 => x"88", + 2300 => x"ca", + 2301 => x"38", + 2302 => x"fe", + 2303 => x"39", + 2304 => x"16", + 2305 => x"ca", + 2306 => x"3d", + 2307 => x"3d", + 2308 => x"08", + 2309 => x"52", + 2310 => x"c5", + 2311 => x"88", + 2312 => x"ca", + 2313 => x"38", + 2314 => x"52", + 2315 => x"de", + 2316 => x"88", + 2317 => x"ca", + 2318 => x"38", + 2319 => x"ca", + 2320 => x"9c", + 2321 => x"ea", + 2322 => x"53", + 2323 => x"9c", + 2324 => x"ea", + 2325 => x"0b", + 2326 => x"74", + 2327 => x"0c", + 2328 => x"04", + 2329 => x"75", + 2330 => x"12", + 2331 => x"53", + 2332 => x"9a", + 2333 => x"88", + 2334 => x"9c", + 2335 => x"e5", + 2336 => x"0b", + 2337 => x"85", + 2338 => x"fa", + 2339 => x"7a", + 2340 => x"0b", + 2341 => x"98", + 2342 => x"2e", + 2343 => x"80", + 2344 => x"55", + 2345 => x"17", + 2346 => x"33", + 2347 => x"51", + 2348 => x"2e", + 2349 => x"85", + 2350 => x"06", + 2351 => x"e5", + 2352 => x"2e", + 2353 => x"8b", + 2354 => x"70", + 2355 => x"34", + 2356 => x"71", + 2357 => x"05", + 2358 => x"15", + 2359 => x"27", + 2360 => x"15", + 2361 => x"80", + 2362 => x"34", + 2363 => x"52", + 2364 => x"88", + 2365 => x"17", + 2366 => x"52", + 2367 => x"3f", + 2368 => x"08", + 2369 => x"12", + 2370 => x"3f", + 2371 => x"08", + 2372 => x"98", + 2373 => x"da", + 2374 => x"88", + 2375 => x"23", + 2376 => x"04", + 2377 => x"7f", + 2378 => x"5b", + 2379 => x"33", + 2380 => x"73", + 2381 => x"38", + 2382 => x"80", + 2383 => x"38", + 2384 => x"8c", + 2385 => x"08", + 2386 => x"aa", + 2387 => x"41", + 2388 => x"33", + 2389 => x"73", + 2390 => x"81", + 2391 => x"81", + 2392 => x"dc", + 2393 => x"70", + 2394 => x"07", + 2395 => x"73", + 2396 => x"88", + 2397 => x"70", + 2398 => x"73", + 2399 => x"38", + 2400 => x"ab", + 2401 => x"52", + 2402 => x"91", + 2403 => x"88", + 2404 => x"98", + 2405 => x"61", + 2406 => x"5a", + 2407 => x"a0", + 2408 => x"e7", + 2409 => x"70", + 2410 => x"79", + 2411 => x"73", + 2412 => x"81", + 2413 => x"38", + 2414 => x"33", + 2415 => x"ae", + 2416 => x"70", + 2417 => x"82", + 2418 => x"51", + 2419 => x"54", + 2420 => x"79", + 2421 => x"74", + 2422 => x"57", + 2423 => x"af", + 2424 => x"70", + 2425 => x"51", + 2426 => x"dc", + 2427 => x"73", + 2428 => x"38", + 2429 => x"82", + 2430 => x"19", + 2431 => x"54", + 2432 => x"82", + 2433 => x"54", + 2434 => x"78", + 2435 => x"81", + 2436 => x"54", + 2437 => x"81", + 2438 => x"af", + 2439 => x"77", + 2440 => x"70", + 2441 => x"25", + 2442 => x"07", + 2443 => x"51", + 2444 => x"2e", + 2445 => x"39", + 2446 => x"80", + 2447 => x"33", + 2448 => x"73", + 2449 => x"81", + 2450 => x"81", + 2451 => x"dc", + 2452 => x"70", + 2453 => x"07", + 2454 => x"73", + 2455 => x"b5", + 2456 => x"2e", + 2457 => x"83", + 2458 => x"76", + 2459 => x"07", + 2460 => x"2e", + 2461 => x"8b", + 2462 => x"77", + 2463 => x"30", + 2464 => x"71", + 2465 => x"53", + 2466 => x"55", + 2467 => x"38", + 2468 => x"5c", + 2469 => x"75", + 2470 => x"73", + 2471 => x"38", + 2472 => x"06", + 2473 => x"11", + 2474 => x"75", + 2475 => x"3f", + 2476 => x"08", + 2477 => x"38", + 2478 => x"33", + 2479 => x"54", + 2480 => x"e6", + 2481 => x"ca", + 2482 => x"2e", + 2483 => x"ff", + 2484 => x"74", + 2485 => x"38", + 2486 => x"75", + 2487 => x"17", + 2488 => x"57", + 2489 => x"a7", + 2490 => x"91", + 2491 => x"e5", + 2492 => x"ca", + 2493 => x"38", + 2494 => x"54", + 2495 => x"89", + 2496 => x"70", + 2497 => x"57", + 2498 => x"54", + 2499 => x"81", + 2500 => x"f7", + 2501 => x"7e", + 2502 => x"2e", + 2503 => x"33", + 2504 => x"e5", + 2505 => x"06", + 2506 => x"7a", + 2507 => x"a0", + 2508 => x"38", + 2509 => x"55", + 2510 => x"84", + 2511 => x"39", + 2512 => x"8b", + 2513 => x"7b", + 2514 => x"7a", + 2515 => x"3f", + 2516 => x"08", + 2517 => x"88", + 2518 => x"38", + 2519 => x"52", + 2520 => x"aa", + 2521 => x"88", + 2522 => x"ca", + 2523 => x"c2", + 2524 => x"08", + 2525 => x"55", + 2526 => x"ff", + 2527 => x"15", + 2528 => x"54", + 2529 => x"34", + 2530 => x"70", + 2531 => x"81", + 2532 => x"58", + 2533 => x"8b", + 2534 => x"74", + 2535 => x"3f", + 2536 => x"08", + 2537 => x"38", + 2538 => x"51", + 2539 => x"ff", + 2540 => x"ab", + 2541 => x"55", + 2542 => x"bb", + 2543 => x"2e", + 2544 => x"80", + 2545 => x"85", + 2546 => x"06", + 2547 => x"58", + 2548 => x"80", + 2549 => x"75", + 2550 => x"73", + 2551 => x"b5", + 2552 => x"0b", + 2553 => x"80", + 2554 => x"39", + 2555 => x"54", + 2556 => x"85", + 2557 => x"75", + 2558 => x"81", + 2559 => x"73", + 2560 => x"1b", + 2561 => x"2a", + 2562 => x"51", + 2563 => x"80", + 2564 => x"90", + 2565 => x"ff", + 2566 => x"05", + 2567 => x"f5", + 2568 => x"ca", + 2569 => x"1c", + 2570 => x"39", + 2571 => x"88", + 2572 => x"0d", + 2573 => x"0d", + 2574 => x"7b", + 2575 => x"73", + 2576 => x"55", + 2577 => x"2e", + 2578 => x"75", + 2579 => x"57", + 2580 => x"26", + 2581 => x"ba", + 2582 => x"70", + 2583 => x"ba", + 2584 => x"06", + 2585 => x"73", + 2586 => x"70", + 2587 => x"51", + 2588 => x"89", + 2589 => x"82", + 2590 => x"ff", + 2591 => x"56", + 2592 => x"2e", + 2593 => x"80", + 2594 => x"84", + 2595 => x"08", + 2596 => x"76", + 2597 => x"58", + 2598 => x"81", + 2599 => x"ff", + 2600 => x"53", + 2601 => x"26", + 2602 => x"13", + 2603 => x"06", + 2604 => x"9f", + 2605 => x"99", + 2606 => x"e0", + 2607 => x"ff", + 2608 => x"72", + 2609 => x"2a", + 2610 => x"72", + 2611 => x"06", + 2612 => x"ff", + 2613 => x"30", + 2614 => x"70", + 2615 => x"07", + 2616 => x"9f", + 2617 => x"54", + 2618 => x"80", + 2619 => x"81", + 2620 => x"59", + 2621 => x"25", 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x"86", + 2681 => x"ca", + 2682 => x"29", + 2683 => x"05", + 2684 => x"53", + 2685 => x"80", + 2686 => x"38", + 2687 => x"76", + 2688 => x"74", + 2689 => x"72", + 2690 => x"38", + 2691 => x"51", + 2692 => x"91", + 2693 => x"81", + 2694 => x"81", + 2695 => x"72", + 2696 => x"80", + 2697 => x"38", + 2698 => x"70", + 2699 => x"53", + 2700 => x"86", + 2701 => x"a7", + 2702 => x"34", + 2703 => x"34", + 2704 => x"14", + 2705 => x"b2", + 2706 => x"88", + 2707 => x"06", + 2708 => x"54", + 2709 => x"72", + 2710 => x"76", + 2711 => x"38", + 2712 => x"70", + 2713 => x"53", + 2714 => x"85", + 2715 => x"70", + 2716 => x"5b", + 2717 => x"91", + 2718 => x"81", + 2719 => x"76", + 2720 => x"81", + 2721 => x"38", + 2722 => x"56", + 2723 => x"83", + 2724 => x"70", + 2725 => x"80", + 2726 => x"83", + 2727 => x"dc", + 2728 => x"ca", + 2729 => x"76", + 2730 => x"05", + 2731 => x"16", + 2732 => x"56", + 2733 => x"d7", + 2734 => x"8d", + 2735 => x"72", + 2736 => x"54", + 2737 => x"57", + 2738 => x"95", + 2739 => x"73", + 2740 => x"3f", + 2741 => x"08", + 2742 => x"57", + 2743 => x"89", + 2744 => x"56", + 2745 => x"d7", + 2746 => x"76", + 2747 => x"f1", + 2748 => x"76", + 2749 => x"e9", + 2750 => x"51", + 2751 => x"91", + 2752 => x"83", + 2753 => x"53", + 2754 => x"2e", + 2755 => x"84", + 2756 => x"ca", + 2757 => x"da", + 2758 => x"88", + 2759 => x"ff", + 2760 => x"8d", + 2761 => x"14", + 2762 => x"3f", + 2763 => x"08", + 2764 => x"15", + 2765 => x"14", + 2766 => x"34", + 2767 => x"33", + 2768 => x"81", + 2769 => x"54", + 2770 => x"72", + 2771 => x"91", + 2772 => x"ff", + 2773 => x"29", + 2774 => x"33", + 2775 => x"72", + 2776 => x"72", + 2777 => x"38", + 2778 => x"06", + 2779 => x"2e", + 2780 => x"56", + 2781 => x"80", + 2782 => x"da", + 2783 => x"ca", + 2784 => x"91", + 2785 => x"88", + 2786 => x"8f", + 2787 => x"56", + 2788 => x"38", + 2789 => x"51", + 2790 => x"91", + 2791 => x"83", + 2792 => x"55", + 2793 => x"80", + 2794 => x"da", + 2795 => x"ca", + 2796 => x"80", + 2797 => x"da", + 2798 => x"ca", + 2799 => x"ff", + 2800 => x"8d", + 2801 => x"2e", + 2802 => x"88", + 2803 => x"14", + 2804 => x"05", + 2805 => x"75", + 2806 => x"38", + 2807 => x"52", + 2808 => x"51", + 2809 => x"3f", + 2810 => x"08", + 2811 => x"88", + 2812 => x"82", + 2813 => x"ca", + 2814 => x"ff", + 2815 => x"26", + 2816 => x"57", + 2817 => x"f5", + 2818 => x"82", + 2819 => x"f5", + 2820 => x"81", + 2821 => x"8d", + 2822 => x"2e", + 2823 => x"82", + 2824 => x"16", + 2825 => x"16", + 2826 => x"70", + 2827 => x"7a", + 2828 => x"0c", + 2829 => x"83", + 2830 => x"06", + 2831 => x"de", + 2832 => x"ae", + 2833 => x"88", + 2834 => x"ff", + 2835 => x"56", + 2836 => x"38", + 2837 => x"38", + 2838 => x"51", + 2839 => x"91", + 2840 => x"a8", + 2841 => x"82", + 2842 => x"39", + 2843 => x"80", + 2844 => x"38", + 2845 => x"15", + 2846 => x"53", + 2847 => x"8d", + 2848 => x"15", + 2849 => x"76", + 2850 => x"51", + 2851 => x"13", + 2852 => x"8d", + 2853 => x"15", + 2854 => x"c5", + 2855 => x"90", + 2856 => x"0b", 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x"76", + 2916 => x"06", + 2917 => x"13", + 2918 => x"c0", + 2919 => x"88", + 2920 => x"52", + 2921 => x"71", + 2922 => x"55", + 2923 => x"53", + 2924 => x"0c", + 2925 => x"ca", + 2926 => x"3d", + 2927 => x"3d", + 2928 => x"05", + 2929 => x"89", + 2930 => x"52", + 2931 => x"3f", + 2932 => x"0b", + 2933 => x"08", + 2934 => x"91", + 2935 => x"84", + 2936 => x"a4", + 2937 => x"55", + 2938 => x"2e", + 2939 => x"74", + 2940 => x"73", + 2941 => x"38", + 2942 => x"78", + 2943 => x"54", + 2944 => x"92", + 2945 => x"89", + 2946 => x"84", + 2947 => x"b0", + 2948 => x"88", + 2949 => x"91", + 2950 => x"88", + 2951 => x"eb", + 2952 => x"02", + 2953 => x"e7", + 2954 => x"59", + 2955 => x"80", + 2956 => x"38", + 2957 => x"70", + 2958 => x"d0", + 2959 => x"3d", + 2960 => x"58", + 2961 => x"91", + 2962 => x"55", + 2963 => x"08", + 2964 => x"7a", + 2965 => x"8c", + 2966 => x"56", + 2967 => x"91", + 2968 => x"55", + 2969 => x"08", + 2970 => x"80", + 2971 => x"70", + 2972 => x"57", + 2973 => x"83", + 2974 => x"77", + 2975 => x"73", + 2976 => x"ab", + 2977 => x"2e", + 2978 => x"84", + 2979 => x"06", + 2980 => x"51", + 2981 => x"91", + 2982 => x"55", + 2983 => x"b2", + 2984 => x"06", + 2985 => x"b8", + 2986 => x"2a", + 2987 => x"51", + 2988 => x"2e", + 2989 => x"55", + 2990 => x"77", + 2991 => x"74", + 2992 => x"77", + 2993 => x"81", + 2994 => x"73", + 2995 => x"af", + 2996 => x"7a", + 2997 => x"3f", + 2998 => x"08", + 2999 => x"b2", + 3000 => x"8e", + 3001 => x"ea", + 3002 => x"a0", + 3003 => x"34", + 3004 => x"52", + 3005 => x"bd", + 3006 => x"62", + 3007 => x"d4", + 3008 => x"54", + 3009 => x"15", + 3010 => x"2e", + 3011 => x"7a", + 3012 => x"51", + 3013 => x"75", + 3014 => x"d4", + 3015 => x"be", + 3016 => x"88", + 3017 => x"ca", + 3018 => x"ca", + 3019 => x"74", + 3020 => x"02", + 3021 => x"70", + 3022 => x"81", + 3023 => x"56", + 3024 => x"86", + 3025 => x"82", + 3026 => x"81", + 3027 => x"06", + 3028 => x"80", + 3029 => x"75", + 3030 => x"73", + 3031 => x"38", + 3032 => x"92", + 3033 => x"7a", + 3034 => x"3f", + 3035 => x"08", + 3036 => x"8c", + 3037 => x"55", + 3038 => x"08", + 3039 => x"77", + 3040 => x"81", + 3041 => x"73", + 3042 => x"38", + 3043 => x"07", + 3044 => x"11", + 3045 => x"0c", + 3046 => x"0c", + 3047 => x"52", + 3048 => x"3f", + 3049 => x"08", + 3050 => x"08", + 3051 => x"63", + 3052 => x"5a", + 3053 => x"91", + 3054 => x"91", + 3055 => x"8c", + 3056 => x"7a", + 3057 => x"17", + 3058 => x"23", + 3059 => x"34", + 3060 => x"1a", + 3061 => x"9c", + 3062 => x"0b", + 3063 => x"77", + 3064 => x"81", + 3065 => x"73", + 3066 => x"8d", + 3067 => x"88", + 3068 => x"81", + 3069 => x"ca", + 3070 => x"1a", + 3071 => x"22", + 3072 => x"7b", + 3073 => x"a8", + 3074 => x"78", + 3075 => x"3f", + 3076 => x"08", + 3077 => x"88", + 3078 => x"83", + 3079 => x"91", + 3080 => x"ff", + 3081 => x"06", + 3082 => x"55", + 3083 => x"56", + 3084 => x"76", + 3085 => x"51", + 3086 => x"27", + 3087 => x"70", + 3088 => x"5a", + 3089 => x"76", + 3090 => x"74", + 3091 => x"83", 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x"ca", + 3151 => x"2e", + 3152 => x"91", + 3153 => x"1a", + 3154 => x"59", + 3155 => x"2e", + 3156 => x"77", + 3157 => x"11", + 3158 => x"55", + 3159 => x"85", + 3160 => x"31", + 3161 => x"76", + 3162 => x"81", + 3163 => x"ca", + 3164 => x"ca", + 3165 => x"d7", + 3166 => x"11", + 3167 => x"74", + 3168 => x"38", + 3169 => x"77", + 3170 => x"78", + 3171 => x"84", + 3172 => x"16", + 3173 => x"08", + 3174 => x"2b", + 3175 => x"cf", + 3176 => x"89", + 3177 => x"39", + 3178 => x"0c", + 3179 => x"83", + 3180 => x"80", + 3181 => x"55", + 3182 => x"83", + 3183 => x"9c", + 3184 => x"7e", + 3185 => x"3f", + 3186 => x"08", + 3187 => x"75", + 3188 => x"08", + 3189 => x"1f", + 3190 => x"7c", + 3191 => x"3f", + 3192 => x"7e", + 3193 => x"0c", + 3194 => x"1b", + 3195 => x"1c", + 3196 => x"fd", + 3197 => x"56", + 3198 => x"88", + 3199 => x"0d", + 3200 => x"0d", + 3201 => x"64", + 3202 => x"58", + 3203 => x"90", + 3204 => x"52", + 3205 => x"d2", + 3206 => x"88", + 3207 => x"ca", + 3208 => x"38", + 3209 => x"55", + 3210 => x"86", + 3211 => x"83", + 3212 => x"18", + 3213 => x"2a", + 3214 => x"51", + 3215 => x"56", + 3216 => x"83", + 3217 => x"39", + 3218 => x"19", + 3219 => x"83", + 3220 => x"0b", + 3221 => x"81", + 3222 => x"39", + 3223 => x"7c", + 3224 => x"74", + 3225 => x"38", + 3226 => x"7b", + 3227 => x"ec", + 3228 => x"08", + 3229 => x"06", + 3230 => x"81", + 3231 => x"8a", + 3232 => x"05", + 3233 => x"06", + 3234 => x"bf", + 3235 => x"38", + 3236 => x"55", + 3237 => x"7a", + 3238 => x"98", + 3239 => x"77", + 3240 => x"3f", + 3241 => x"08", + 3242 => x"88", + 3243 => x"82", + 3244 => x"81", + 3245 => x"38", + 3246 => x"ff", + 3247 => x"98", + 3248 => x"18", + 3249 => x"74", + 3250 => x"7e", + 3251 => x"08", + 3252 => x"2e", + 3253 => x"8d", + 3254 => x"ce", + 3255 => x"ca", + 3256 => x"ee", + 3257 => x"08", + 3258 => x"d1", + 3259 => x"ca", + 3260 => x"2e", + 3261 => x"91", + 3262 => x"1b", + 3263 => x"5a", + 3264 => x"2e", + 3265 => x"78", + 3266 => x"11", + 3267 => x"55", + 3268 => x"85", + 3269 => x"31", + 3270 => x"76", + 3271 => x"81", + 3272 => x"c8", + 3273 => x"ca", + 3274 => x"a6", + 3275 => x"11", + 3276 => x"56", + 3277 => x"27", + 3278 => x"80", + 3279 => x"08", + 3280 => x"2b", + 3281 => x"b4", + 3282 => x"b5", + 3283 => x"80", + 3284 => x"34", + 3285 => x"56", + 3286 => x"8c", + 3287 => x"19", + 3288 => x"38", + 3289 => x"b6", + 3290 => x"88", + 3291 => x"38", + 3292 => x"12", + 3293 => x"9c", + 3294 => x"18", + 3295 => x"06", + 3296 => x"31", + 3297 => x"76", + 3298 => x"7b", + 3299 => x"08", + 3300 => x"cd", + 3301 => x"ca", + 3302 => x"b6", + 3303 => x"7c", + 3304 => x"08", + 3305 => x"1f", + 3306 => x"cb", + 3307 => x"55", + 3308 => x"16", + 3309 => x"31", + 3310 => x"7f", + 3311 => x"94", + 3312 => x"70", + 3313 => x"8c", + 3314 => x"58", + 3315 => x"76", + 3316 => x"75", + 3317 => x"19", + 3318 => x"39", + 3319 => x"80", + 3320 => x"74", + 3321 => x"80", + 3322 => x"ca", + 3323 => x"3d", + 3324 => x"3d", + 3325 => x"3d", + 3326 => x"70", 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x"71", + 3386 => x"0c", + 3387 => x"04", + 3388 => x"80", + 3389 => x"d0", + 3390 => x"3d", + 3391 => x"3f", + 3392 => x"08", + 3393 => x"88", + 3394 => x"38", + 3395 => x"52", + 3396 => x"05", + 3397 => x"3f", + 3398 => x"08", + 3399 => x"88", + 3400 => x"02", + 3401 => x"33", + 3402 => x"55", + 3403 => x"25", + 3404 => x"7a", + 3405 => x"54", + 3406 => x"a2", + 3407 => x"84", + 3408 => x"06", + 3409 => x"73", + 3410 => x"38", + 3411 => x"70", + 3412 => x"a8", + 3413 => x"88", + 3414 => x"0c", + 3415 => x"ca", + 3416 => x"2e", + 3417 => x"83", + 3418 => x"74", + 3419 => x"0c", + 3420 => x"04", + 3421 => x"6f", + 3422 => x"80", + 3423 => x"53", + 3424 => x"b8", + 3425 => x"3d", + 3426 => x"3f", + 3427 => x"08", + 3428 => x"88", + 3429 => x"38", + 3430 => x"7c", + 3431 => x"47", + 3432 => x"54", + 3433 => x"81", + 3434 => x"52", + 3435 => x"52", + 3436 => x"3f", + 3437 => x"08", + 3438 => x"88", + 3439 => x"38", + 3440 => x"51", + 3441 => x"91", + 3442 => x"57", + 3443 => x"08", + 3444 => x"69", + 3445 => x"da", + 3446 => x"ca", + 3447 => x"76", + 3448 => x"d5", + 3449 => x"ca", + 3450 => x"91", + 3451 => x"82", + 3452 => x"52", + 3453 => x"eb", + 3454 => x"88", + 3455 => x"ca", + 3456 => x"38", + 3457 => x"51", + 3458 => x"73", + 3459 => x"08", + 3460 => x"76", + 3461 => x"d6", + 3462 => x"ca", + 3463 => x"91", + 3464 => x"80", + 3465 => x"76", + 3466 => x"81", + 3467 => x"82", + 3468 => x"39", + 3469 => x"38", + 3470 => x"bc", + 3471 => x"51", + 3472 => x"76", + 3473 => x"11", + 3474 => x"51", + 3475 => x"73", + 3476 => x"38", + 3477 => x"55", + 3478 => x"16", + 3479 => x"56", + 3480 => x"38", + 3481 => x"73", + 3482 => x"90", + 3483 => x"2e", + 3484 => x"16", + 3485 => x"ff", + 3486 => x"ff", + 3487 => x"58", + 3488 => x"74", + 3489 => x"75", + 3490 => x"18", + 3491 => x"58", + 3492 => x"fe", + 3493 => x"7b", + 3494 => x"06", + 3495 => x"18", + 3496 => x"58", + 3497 => x"80", + 3498 => x"b8", + 3499 => x"29", + 3500 => x"05", + 3501 => x"33", + 3502 => x"56", + 3503 => x"2e", + 3504 => x"16", + 3505 => x"33", + 3506 => x"73", + 3507 => x"16", + 3508 => x"26", + 3509 => x"55", + 3510 => x"91", + 3511 => x"54", + 3512 => x"70", + 3513 => x"34", + 3514 => x"ec", + 3515 => x"70", + 3516 => x"34", + 3517 => x"09", + 3518 => x"38", + 3519 => x"39", + 3520 => x"19", + 3521 => x"33", + 3522 => x"05", + 3523 => x"78", + 3524 => x"80", + 3525 => x"91", + 3526 => x"9e", + 3527 => x"f7", + 3528 => x"7d", + 3529 => x"05", + 3530 => x"57", + 3531 => x"3f", + 3532 => x"08", + 3533 => x"88", + 3534 => x"38", + 3535 => x"53", + 3536 => x"38", + 3537 => x"54", + 3538 => x"92", + 3539 => x"33", + 3540 => x"70", + 3541 => x"54", + 3542 => x"38", + 3543 => x"15", + 3544 => x"70", + 3545 => x"58", + 3546 => x"82", + 3547 => x"8a", + 3548 => x"89", + 3549 => x"53", + 3550 => x"b7", + 3551 => x"ff", + 3552 => x"9b", + 3553 => x"ca", + 3554 => x"15", + 3555 => x"53", + 3556 => x"9b", + 3557 => x"ca", + 3558 => x"26", + 3559 => x"30", + 3560 => x"70", + 3561 => x"77", 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x"90", + 3621 => x"c0", + 3622 => x"90", + 3623 => x"83", + 3624 => x"72", + 3625 => x"38", + 3626 => x"08", + 3627 => x"77", + 3628 => x"80", + 3629 => x"ca", + 3630 => x"3d", + 3631 => x"3d", + 3632 => x"89", + 3633 => x"2e", + 3634 => x"80", + 3635 => x"fc", + 3636 => x"3d", + 3637 => x"e1", + 3638 => x"ca", + 3639 => x"91", + 3640 => x"80", + 3641 => x"76", + 3642 => x"75", + 3643 => x"3f", + 3644 => x"08", + 3645 => x"88", + 3646 => x"38", + 3647 => x"70", + 3648 => x"57", + 3649 => x"a2", + 3650 => x"33", + 3651 => x"70", + 3652 => x"55", + 3653 => x"2e", + 3654 => x"16", + 3655 => x"51", + 3656 => x"91", + 3657 => x"88", + 3658 => x"54", + 3659 => x"84", + 3660 => x"52", + 3661 => x"e5", + 3662 => x"88", + 3663 => x"84", + 3664 => x"06", + 3665 => x"55", + 3666 => x"80", + 3667 => x"80", + 3668 => x"54", + 3669 => x"88", + 3670 => x"0d", + 3671 => x"0d", + 3672 => x"fc", + 3673 => x"52", + 3674 => x"3f", + 3675 => x"08", + 3676 => x"ca", + 3677 => x"0c", + 3678 => x"04", + 3679 => x"77", + 3680 => x"fc", + 3681 => x"53", + 3682 => x"de", + 3683 => x"88", + 3684 => x"ca", + 3685 => x"df", + 3686 => x"38", + 3687 => x"08", + 3688 => x"cd", + 3689 => x"ca", + 3690 => x"80", + 3691 => x"ca", + 3692 => x"73", + 3693 => x"3f", + 3694 => x"08", + 3695 => x"88", + 3696 => x"09", + 3697 => x"38", + 3698 => x"39", + 3699 => x"08", + 3700 => x"52", + 3701 => x"b3", + 3702 => x"73", + 3703 => x"3f", + 3704 => x"08", + 3705 => x"30", + 3706 => x"9f", + 3707 => x"ca", + 3708 => x"51", + 3709 => x"72", + 3710 => x"0c", + 3711 => x"04", + 3712 => x"65", + 3713 => x"89", + 3714 => x"96", + 3715 => x"df", + 3716 => x"ca", + 3717 => x"91", + 3718 => x"b2", + 3719 => x"75", + 3720 => x"3f", + 3721 => x"08", + 3722 => x"88", + 3723 => x"02", + 3724 => x"33", + 3725 => x"55", + 3726 => x"25", + 3727 => x"55", + 3728 => x"80", + 3729 => x"76", + 3730 => x"d4", + 3731 => x"91", + 3732 => x"94", + 3733 => x"f0", + 3734 => x"65", + 3735 => x"53", + 3736 => x"05", + 3737 => x"51", + 3738 => x"91", + 3739 => x"5b", + 3740 => x"08", + 3741 => x"7c", + 3742 => x"08", + 3743 => x"fe", + 3744 => x"08", + 3745 => x"55", + 3746 => x"91", + 3747 => x"0c", + 3748 => x"81", + 3749 => x"39", + 3750 => x"c7", + 3751 => x"88", + 3752 => x"55", + 3753 => x"2e", + 3754 => x"bf", + 3755 => x"5f", + 3756 => x"92", + 3757 => x"51", + 3758 => x"91", + 3759 => x"ff", + 3760 => x"91", + 3761 => x"81", + 3762 => x"91", + 3763 => x"30", + 3764 => x"88", + 3765 => x"25", + 3766 => x"19", + 3767 => x"5a", + 3768 => x"08", + 3769 => x"38", + 3770 => x"a4", + 3771 => x"ca", + 3772 => x"58", + 3773 => x"77", + 3774 => x"7d", + 3775 => x"bf", + 3776 => x"ca", + 3777 => x"91", + 3778 => x"80", + 3779 => x"70", + 3780 => x"ff", + 3781 => x"56", + 3782 => x"2e", + 3783 => x"9e", + 3784 => x"51", + 3785 => x"3f", + 3786 => x"08", + 3787 => x"06", + 3788 => x"80", + 3789 => x"19", + 3790 => x"54", + 3791 => x"14", + 3792 => x"c5", + 3793 => x"88", + 3794 => x"06", + 3795 => x"80", + 3796 => x"19", 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x"18", + 3856 => x"74", + 3857 => x"0c", + 3858 => x"04", + 3859 => x"82", + 3860 => x"ff", + 3861 => x"a1", + 3862 => x"e4", + 3863 => x"88", + 3864 => x"ca", + 3865 => x"f5", + 3866 => x"a1", + 3867 => x"95", + 3868 => x"58", + 3869 => x"91", + 3870 => x"55", + 3871 => x"08", + 3872 => x"02", + 3873 => x"33", + 3874 => x"70", + 3875 => x"55", + 3876 => x"73", + 3877 => x"75", + 3878 => x"80", + 3879 => x"bd", + 3880 => x"d6", + 3881 => x"81", + 3882 => x"87", + 3883 => x"ad", + 3884 => x"78", + 3885 => x"3f", + 3886 => x"08", + 3887 => x"70", + 3888 => x"55", + 3889 => x"2e", + 3890 => x"78", + 3891 => x"88", + 3892 => x"08", + 3893 => x"38", + 3894 => x"ca", + 3895 => x"76", + 3896 => x"70", + 3897 => x"b5", + 3898 => x"88", + 3899 => x"ca", + 3900 => x"e9", + 3901 => x"88", + 3902 => x"51", + 3903 => x"91", + 3904 => x"55", + 3905 => x"08", + 3906 => x"55", + 3907 => x"91", + 3908 => x"84", + 3909 => x"91", + 3910 => x"80", + 3911 => x"51", + 3912 => x"91", + 3913 => x"91", + 3914 => x"30", + 3915 => x"88", + 3916 => x"25", + 3917 => x"75", + 3918 => x"38", + 3919 => x"8f", + 3920 => x"75", + 3921 => x"c1", + 3922 => x"ca", + 3923 => x"74", + 3924 => x"51", + 3925 => x"3f", + 3926 => x"08", + 3927 => x"ca", + 3928 => x"3d", + 3929 => x"3d", + 3930 => x"99", + 3931 => x"52", + 3932 => x"d8", + 3933 => x"ca", + 3934 => x"91", + 3935 => x"82", + 3936 => x"5e", + 3937 => x"3d", + 3938 => x"cf", + 3939 => x"ca", + 3940 => x"91", + 3941 => x"86", + 3942 => x"82", + 3943 => x"ca", + 3944 => x"2e", + 3945 => x"82", + 3946 => x"80", + 3947 => x"70", + 3948 => x"06", + 3949 => x"54", + 3950 => x"38", + 3951 => x"52", + 3952 => x"52", + 3953 => x"3f", + 3954 => x"08", + 3955 => x"91", + 3956 => x"83", + 3957 => x"91", + 3958 => x"81", + 3959 => x"06", + 3960 => x"54", + 3961 => x"08", + 3962 => x"81", + 3963 => x"81", + 3964 => x"39", + 3965 => x"38", + 3966 => x"08", + 3967 => x"c4", + 3968 => x"ca", + 3969 => x"91", + 3970 => x"81", + 3971 => x"53", + 3972 => x"19", + 3973 => x"8c", + 3974 => x"ae", + 3975 => x"34", + 3976 => x"0b", + 3977 => x"82", + 3978 => x"52", + 3979 => x"51", + 3980 => x"3f", + 3981 => x"b4", + 3982 => x"c9", + 3983 => x"53", + 3984 => x"53", + 3985 => x"51", + 3986 => x"3f", + 3987 => x"0b", + 3988 => x"34", + 3989 => x"80", + 3990 => x"51", + 3991 => x"78", + 3992 => x"83", + 3993 => x"51", + 3994 => x"91", + 3995 => x"54", + 3996 => x"08", + 3997 => x"88", + 3998 => x"64", + 3999 => x"ff", + 4000 => x"75", + 4001 => x"78", + 4002 => x"3f", + 4003 => x"0b", + 4004 => x"78", + 4005 => x"83", + 4006 => x"51", + 4007 => x"3f", + 4008 => x"08", + 4009 => x"80", + 4010 => x"76", + 4011 => x"ae", + 4012 => x"ca", + 4013 => x"3d", + 4014 => x"3d", + 4015 => x"84", + 4016 => x"f1", + 4017 => x"a8", + 4018 => x"05", + 4019 => x"51", + 4020 => x"91", + 4021 => x"55", + 4022 => x"08", + 4023 => x"78", + 4024 => x"08", + 4025 => x"70", + 4026 => x"b8", + 4027 => x"88", + 4028 => x"ca", + 4029 => x"b9", + 4030 => x"9b", + 4031 => x"a0", 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x"91", + 4091 => x"80", + 4092 => x"16", + 4093 => x"ae", + 4094 => x"06", + 4095 => x"53", + 4096 => x"51", + 4097 => x"78", + 4098 => x"83", + 4099 => x"39", + 4100 => x"08", + 4101 => x"51", + 4102 => x"91", + 4103 => x"55", + 4104 => x"08", + 4105 => x"51", + 4106 => x"3f", + 4107 => x"08", + 4108 => x"ca", + 4109 => x"3d", + 4110 => x"3d", + 4111 => x"db", + 4112 => x"84", + 4113 => x"05", + 4114 => x"82", + 4115 => x"d0", + 4116 => x"3d", + 4117 => x"3f", + 4118 => x"08", + 4119 => x"88", + 4120 => x"38", + 4121 => x"52", + 4122 => x"05", + 4123 => x"3f", + 4124 => x"08", + 4125 => x"88", + 4126 => x"02", + 4127 => x"33", + 4128 => x"54", + 4129 => x"aa", + 4130 => x"06", + 4131 => x"8b", + 4132 => x"06", + 4133 => x"07", + 4134 => x"56", + 4135 => x"34", + 4136 => x"0b", + 4137 => x"78", + 4138 => x"a9", + 4139 => x"88", + 4140 => x"91", + 4141 => x"95", + 4142 => x"ef", + 4143 => x"56", + 4144 => x"3d", + 4145 => x"94", + 4146 => x"f4", + 4147 => x"88", + 4148 => x"ca", + 4149 => x"cb", + 4150 => x"63", + 4151 => x"d4", + 4152 => x"c0", + 4153 => x"88", + 4154 => x"ca", + 4155 => x"38", + 4156 => x"05", + 4157 => x"06", + 4158 => x"73", + 4159 => x"16", + 4160 => x"22", + 4161 => x"07", + 4162 => x"1f", + 4163 => x"c2", + 4164 => x"81", + 4165 => x"34", + 4166 => x"b3", + 4167 => x"ca", + 4168 => x"74", + 4169 => x"0c", + 4170 => x"04", + 4171 => x"69", + 4172 => x"80", + 4173 => x"d0", + 4174 => x"3d", + 4175 => x"3f", + 4176 => x"08", + 4177 => x"08", + 4178 => x"ca", + 4179 => x"80", + 4180 => x"57", + 4181 => x"81", + 4182 => x"70", + 4183 => x"55", + 4184 => x"80", + 4185 => x"5d", + 4186 => x"52", + 4187 => x"52", + 4188 => x"a9", + 4189 => x"88", + 4190 => x"ca", + 4191 => x"d1", + 4192 => x"73", + 4193 => x"3f", + 4194 => x"08", + 4195 => x"88", + 4196 => x"91", + 4197 => x"91", + 4198 => x"65", + 4199 => x"78", + 4200 => x"7b", + 4201 => x"55", + 4202 => x"34", + 4203 => x"8a", + 4204 => x"38", + 4205 => x"1a", + 4206 => x"34", + 4207 => x"9e", + 4208 => x"70", + 4209 => x"51", + 4210 => x"a0", + 4211 => x"8e", + 4212 => x"2e", + 4213 => x"86", + 4214 => x"34", + 4215 => x"30", + 4216 => x"80", + 4217 => x"7a", + 4218 => x"c1", + 4219 => x"2e", + 4220 => x"a0", + 4221 => x"51", + 4222 => x"3f", + 4223 => x"08", + 4224 => x"88", + 4225 => x"7b", + 4226 => x"55", + 4227 => x"73", + 4228 => x"38", + 4229 => x"73", + 4230 => x"38", + 4231 => x"15", + 4232 => x"ff", + 4233 => x"91", + 4234 => x"7b", + 4235 => x"ca", + 4236 => x"3d", + 4237 => x"3d", + 4238 => x"9c", + 4239 => x"05", + 4240 => x"51", + 4241 => x"91", + 4242 => x"91", + 4243 => x"56", + 4244 => x"88", + 4245 => x"38", + 4246 => x"52", + 4247 => x"52", + 4248 => x"c0", + 4249 => x"70", + 4250 => x"ff", + 4251 => x"55", + 4252 => x"27", + 4253 => x"78", + 4254 => x"ff", + 4255 => x"05", + 4256 => x"55", + 4257 => x"3f", + 4258 => x"08", + 4259 => x"38", + 4260 => x"70", + 4261 => x"ff", + 4262 => x"91", + 4263 => x"80", + 4264 => x"74", + 4265 => x"07", + 4266 => x"4e", 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x"ca", + 4326 => x"2e", + 4327 => x"80", + 4328 => x"54", + 4329 => x"80", + 4330 => x"52", + 4331 => x"bd", + 4332 => x"ca", + 4333 => x"91", + 4334 => x"b1", + 4335 => x"91", + 4336 => x"52", + 4337 => x"ab", + 4338 => x"54", + 4339 => x"15", + 4340 => x"78", + 4341 => x"ff", + 4342 => x"79", + 4343 => x"83", + 4344 => x"51", + 4345 => x"3f", + 4346 => x"08", + 4347 => x"74", + 4348 => x"0c", + 4349 => x"04", + 4350 => x"60", + 4351 => x"05", + 4352 => x"33", + 4353 => x"05", + 4354 => x"40", + 4355 => x"da", + 4356 => x"88", + 4357 => x"ca", + 4358 => x"bd", + 4359 => x"33", + 4360 => x"b5", + 4361 => x"2e", + 4362 => x"1a", + 4363 => x"90", + 4364 => x"33", + 4365 => x"70", + 4366 => x"55", + 4367 => x"38", + 4368 => x"97", + 4369 => x"82", + 4370 => x"58", + 4371 => x"7e", + 4372 => x"70", + 4373 => x"55", + 4374 => x"56", + 4375 => x"8a", + 4376 => x"7d", + 4377 => x"70", + 4378 => x"2a", + 4379 => x"08", + 4380 => x"08", + 4381 => x"5d", + 4382 => x"77", + 4383 => x"98", + 4384 => x"26", + 4385 => x"57", + 4386 => x"59", + 4387 => x"52", + 4388 => x"ae", + 4389 => x"15", + 4390 => x"98", + 4391 => x"26", + 4392 => x"55", + 4393 => x"08", + 4394 => x"99", + 4395 => x"88", + 4396 => x"ff", + 4397 => x"ca", + 4398 => x"38", + 4399 => x"75", + 4400 => x"81", + 4401 => x"93", + 4402 => x"80", + 4403 => x"2e", + 4404 => x"ff", + 4405 => x"58", + 4406 => x"7d", + 4407 => x"38", + 4408 => x"55", + 4409 => x"b4", + 4410 => x"56", + 4411 => x"09", + 4412 => x"38", + 4413 => x"53", + 4414 => x"51", + 4415 => x"3f", + 4416 => x"08", + 4417 => x"88", + 4418 => x"38", + 4419 => x"ff", + 4420 => x"5c", + 4421 => x"84", + 4422 => x"5c", + 4423 => x"12", + 4424 => x"80", + 4425 => x"78", + 4426 => x"7c", + 4427 => x"90", + 4428 => x"c0", + 4429 => x"90", + 4430 => x"15", + 4431 => x"90", + 4432 => x"54", + 4433 => x"91", + 4434 => x"31", + 4435 => x"84", + 4436 => x"07", + 4437 => x"16", + 4438 => x"73", + 4439 => x"0c", + 4440 => x"04", + 4441 => x"6b", + 4442 => x"05", + 4443 => x"33", + 4444 => x"5a", + 4445 => x"bd", + 4446 => x"80", + 4447 => x"88", + 4448 => x"f8", + 4449 => x"88", + 4450 => x"91", + 4451 => x"70", + 4452 => x"74", + 4453 => x"38", + 4454 => x"91", + 4455 => x"81", + 4456 => x"81", + 4457 => x"ff", + 4458 => x"91", + 4459 => x"81", + 4460 => x"81", + 4461 => x"83", + 4462 => x"c0", + 4463 => x"2a", + 4464 => x"51", + 4465 => x"74", + 4466 => x"99", + 4467 => x"53", + 4468 => x"51", + 4469 => x"3f", + 4470 => x"08", + 4471 => x"55", + 4472 => x"92", + 4473 => x"80", + 4474 => x"38", + 4475 => x"06", + 4476 => x"2e", + 4477 => x"48", + 4478 => x"87", + 4479 => x"79", + 4480 => x"78", + 4481 => x"26", + 4482 => x"19", + 4483 => x"74", + 4484 => x"38", + 4485 => x"e4", + 4486 => x"2a", + 4487 => x"70", + 4488 => x"59", + 4489 => x"7a", + 4490 => x"56", + 4491 => x"80", + 4492 => x"51", + 4493 => x"74", + 4494 => x"99", + 4495 => x"53", + 4496 => x"51", + 4497 => x"3f", + 4498 => x"ca", + 4499 => x"ac", + 4500 => x"2a", + 4501 => x"91", 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x"74", + 4561 => x"38", + 4562 => x"ee", + 4563 => x"66", + 4564 => x"96", + 4565 => x"88", + 4566 => x"05", + 4567 => x"88", + 4568 => x"26", + 4569 => x"0b", + 4570 => x"08", + 4571 => x"88", + 4572 => x"11", + 4573 => x"05", + 4574 => x"83", + 4575 => x"2a", + 4576 => x"a0", + 4577 => x"7d", + 4578 => x"69", + 4579 => x"05", + 4580 => x"72", + 4581 => x"5c", + 4582 => x"59", + 4583 => x"2e", + 4584 => x"89", + 4585 => x"60", + 4586 => x"84", + 4587 => x"5d", + 4588 => x"18", + 4589 => x"68", + 4590 => x"74", + 4591 => x"af", + 4592 => x"31", + 4593 => x"53", + 4594 => x"52", + 4595 => x"9a", + 4596 => x"88", + 4597 => x"83", + 4598 => x"06", + 4599 => x"ca", + 4600 => x"ff", + 4601 => x"dd", + 4602 => x"83", + 4603 => x"2a", + 4604 => x"be", + 4605 => x"39", + 4606 => x"09", + 4607 => x"c5", + 4608 => x"f5", + 4609 => x"88", + 4610 => x"38", + 4611 => x"79", + 4612 => x"80", + 4613 => x"38", + 4614 => x"96", + 4615 => x"06", + 4616 => x"2e", + 4617 => x"5e", + 4618 => x"91", + 4619 => x"9f", + 4620 => x"38", + 4621 => x"38", + 4622 => x"81", + 4623 => x"fc", + 4624 => x"ab", + 4625 => x"7d", + 4626 => x"81", + 4627 => x"7d", + 4628 => x"78", + 4629 => x"74", + 4630 => x"8e", + 4631 => x"9c", + 4632 => x"53", + 4633 => x"51", + 4634 => x"3f", + 4635 => x"b8", + 4636 => x"51", + 4637 => x"3f", + 4638 => x"8b", + 4639 => x"a1", + 4640 => x"8d", + 4641 => x"83", + 4642 => x"52", + 4643 => x"ff", + 4644 => x"81", + 4645 => x"34", + 4646 => x"70", + 4647 => x"2a", + 4648 => x"54", + 4649 => x"1b", + 4650 => x"88", + 4651 => x"74", + 4652 => x"26", + 4653 => x"83", + 4654 => x"52", + 4655 => x"ff", + 4656 => x"8a", + 4657 => x"a0", + 4658 => x"a1", + 4659 => x"0b", + 4660 => x"bf", + 4661 => x"51", + 4662 => x"3f", + 4663 => x"9a", + 4664 => x"a0", + 4665 => x"52", + 4666 => x"ff", + 4667 => x"7d", + 4668 => x"81", + 4669 => x"38", + 4670 => x"0a", + 4671 => x"1b", + 4672 => x"ce", + 4673 => x"a4", + 4674 => x"a0", + 4675 => x"52", + 4676 => x"ff", + 4677 => x"81", + 4678 => x"51", + 4679 => x"3f", + 4680 => x"1b", + 4681 => x"8c", + 4682 => x"0b", + 4683 => x"34", + 4684 => x"c2", + 4685 => x"53", + 4686 => x"52", + 4687 => x"51", + 4688 => x"88", + 4689 => x"a7", + 4690 => x"a0", + 4691 => x"83", + 4692 => x"52", + 4693 => x"ff", + 4694 => x"ff", + 4695 => x"1c", + 4696 => x"a6", + 4697 => x"53", + 4698 => x"52", + 4699 => x"ff", + 4700 => x"82", + 4701 => x"83", + 4702 => x"52", + 4703 => x"b4", + 4704 => x"60", + 4705 => x"7e", + 4706 => x"d7", + 4707 => x"91", + 4708 => x"83", + 4709 => x"83", + 4710 => x"06", + 4711 => x"75", + 4712 => x"05", + 4713 => x"7e", + 4714 => x"b7", + 4715 => x"53", + 4716 => x"51", + 4717 => x"3f", + 4718 => x"a4", + 4719 => x"51", + 4720 => x"3f", + 4721 => x"e4", + 4722 => x"e4", + 4723 => x"9f", + 4724 => x"18", + 4725 => x"1b", + 4726 => x"f6", + 4727 => x"83", + 4728 => x"ff", + 4729 => x"82", + 4730 => x"78", + 4731 => x"c4", + 4732 => x"60", + 4733 => x"7a", + 4734 => x"ff", + 4735 => x"75", + 4736 => x"53", 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x"ff", + 4796 => x"83", + 4797 => x"77", + 4798 => x"0b", + 4799 => x"81", + 4800 => x"34", + 4801 => x"34", + 4802 => x"34", + 4803 => x"56", + 4804 => x"52", + 4805 => x"f4", + 4806 => x"0b", + 4807 => x"91", + 4808 => x"82", + 4809 => x"56", + 4810 => x"34", + 4811 => x"08", + 4812 => x"60", + 4813 => x"1b", + 4814 => x"96", + 4815 => x"83", + 4816 => x"ff", + 4817 => x"81", + 4818 => x"7a", + 4819 => x"ff", + 4820 => x"81", + 4821 => x"88", + 4822 => x"80", + 4823 => x"7e", + 4824 => x"e3", + 4825 => x"91", + 4826 => x"90", + 4827 => x"8e", + 4828 => x"81", + 4829 => x"91", + 4830 => x"56", + 4831 => x"88", + 4832 => x"0d", + 4833 => x"0d", + 4834 => x"93", + 4835 => x"38", + 4836 => x"91", + 4837 => x"52", + 4838 => x"91", + 4839 => x"81", + 4840 => x"bb", + 4841 => x"f9", + 4842 => x"f8", + 4843 => x"39", + 4844 => x"51", + 4845 => x"91", + 4846 => x"80", + 4847 => x"bc", + 4848 => x"dd", + 4849 => x"c0", + 4850 => x"39", + 4851 => x"51", + 4852 => x"91", + 4853 => x"80", + 4854 => x"bd", + 4855 => x"c1", + 4856 => x"98", + 4857 => x"91", + 4858 => x"b5", + 4859 => x"c8", + 4860 => x"91", + 4861 => x"a9", + 4862 => x"88", + 4863 => x"91", + 4864 => x"9d", + 4865 => x"bc", + 4866 => x"91", + 4867 => x"91", + 4868 => x"ec", + 4869 => x"91", + 4870 => x"85", + 4871 => x"90", + 4872 => x"fb", + 4873 => x"0d", + 4874 => x"0d", + 4875 => x"56", + 4876 => x"26", + 4877 => x"52", + 4878 => x"29", + 4879 => x"87", + 4880 => x"51", + 4881 => x"3f", + 4882 => x"08", + 4883 => x"fe", + 4884 => x"91", + 4885 => x"54", + 4886 => x"52", + 4887 => x"51", + 4888 => x"3f", + 4889 => x"04", + 4890 => x"7d", + 4891 => x"8c", + 4892 => x"05", + 4893 => x"15", + 4894 => x"5a", + 4895 => x"5c", + 4896 => x"bf", + 4897 => x"8c", + 4898 => x"bf", + 4899 => x"87", + 4900 => x"55", + 4901 => x"80", + 4902 => x"90", + 4903 => x"79", + 4904 => x"38", + 4905 => x"74", + 4906 => x"78", + 4907 => x"72", + 4908 => x"bf", + 4909 => x"8c", + 4910 => x"39", + 4911 => x"51", + 4912 => x"3f", + 4913 => x"80", + 4914 => x"16", + 4915 => x"27", + 4916 => x"08", + 4917 => x"c4", + 4918 => x"a7", + 4919 => x"91", + 4920 => x"ff", + 4921 => x"84", + 4922 => x"39", + 4923 => x"72", + 4924 => x"38", + 4925 => x"91", + 4926 => x"ff", + 4927 => x"89", + 4928 => x"ec", + 4929 => x"97", + 4930 => x"55", + 4931 => x"fa", + 4932 => x"80", + 4933 => x"f0", + 4934 => x"83", + 4935 => x"74", + 4936 => x"38", + 4937 => x"33", + 4938 => x"52", + 4939 => x"74", + 4940 => x"72", + 4941 => x"38", + 4942 => x"26", + 4943 => x"51", + 4944 => x"51", + 4945 => x"3f", + 4946 => x"d3", + 4947 => x"f4", + 4948 => x"cb", + 4949 => x"77", + 4950 => x"fe", + 4951 => x"91", + 4952 => x"98", + 4953 => x"2c", + 4954 => x"a0", + 4955 => x"06", + 4956 => x"fc", + 4957 => x"ca", + 4958 => x"2b", + 4959 => x"70", + 4960 => x"30", + 4961 => x"9f", + 4962 => x"56", + 4963 => x"9b", + 4964 => x"72", + 4965 => x"9b", + 4966 => x"06", + 4967 => x"53", + 4968 => x"1c", + 4969 => x"26", + 4970 => x"ff", + 4971 => x"ca", + 4972 => x"3d", + 4973 => x"3d", + 4974 => x"84", + 4975 => x"05", + 4976 => x"30", + 4977 => x"80", + 4978 => x"ff", + 4979 => x"51", + 4980 => x"5b", + 4981 => x"74", + 4982 => x"81", + 4983 => x"8c", + 4984 => x"57", + 4985 => x"91", + 4986 => x"56", + 4987 => x"08", + 4988 => x"ca", + 4989 => x"c0", + 4990 => x"91", + 4991 => x"59", + 4992 => x"05", + 4993 => x"53", + 4994 => x"51", + 4995 => x"91", + 4996 => x"56", + 4997 => x"08", + 4998 => x"55", + 4999 => x"89", + 5000 => x"75", + 5001 => x"d8", + 5002 => x"d8", + 5003 => x"e0", + 5004 => x"70", + 5005 => x"25", + 5006 => x"80", + 5007 => x"74", + 5008 => x"38", + 5009 => x"53", + 5010 => x"88", + 5011 => x"51", + 5012 => x"75", + 5013 => x"ca", + 5014 => x"3d", + 5015 => x"3d", + 5016 => x"84", + 5017 => x"33", + 5018 => x"57", + 5019 => x"52", + 5020 => x"c2", + 5021 => x"88", + 5022 => x"75", + 5023 => x"38", + 5024 => x"98", + 5025 => x"60", + 5026 => x"91", + 5027 => x"7e", + 5028 => x"77", + 5029 => x"88", + 5030 => x"39", + 5031 => x"91", + 5032 => x"89", + 5033 => x"fc", + 5034 => x"9b", + 5035 => x"c0", + 5036 => x"c0", + 5037 => x"ff", + 5038 => x"91", + 5039 => x"51", + 5040 => x"3f", + 5041 => x"54", + 5042 => x"53", + 5043 => x"33", + 5044 => x"a8", + 5045 => x"ab", + 5046 => x"2e", + 5047 => x"fe", + 5048 => x"3d", + 5049 => x"3d", + 5050 => x"96", + 5051 => x"ff", + 5052 => x"81", + 5053 => x"8c", + 5054 => x"c4", + 5055 => x"84", + 5056 => x"fe", + 5057 => x"72", + 5058 => x"81", + 5059 => x"71", + 5060 => x"38", + 5061 => x"f5", + 5062 => x"c0", + 5063 => x"f7", + 5064 => x"51", + 5065 => x"3f", + 5066 => x"70", + 5067 => x"52", + 5068 => x"95", + 5069 => x"fe", + 5070 => x"91", + 5071 => x"fe", + 5072 => x"80", + 5073 => x"bc", + 5074 => x"2a", + 5075 => x"51", + 5076 => x"2e", + 5077 => x"51", + 5078 => x"3f", + 5079 => x"51", + 5080 => x"3f", + 5081 => x"f5", + 5082 => x"84", + 5083 => x"06", + 5084 => x"80", + 5085 => x"81", + 5086 => x"88", + 5087 => x"98", + 5088 => x"80", + 5089 => x"fe", + 5090 => x"72", + 5091 => x"81", + 5092 => x"71", + 5093 => x"38", + 5094 => x"f4", + 5095 => x"c1", + 5096 => x"f6", + 5097 => x"51", + 5098 => x"3f", + 5099 => x"70", + 5100 => x"52", + 5101 => x"95", + 5102 => x"fe", + 5103 => x"91", + 5104 => x"fe", + 5105 => x"80", + 5106 => x"b8", + 5107 => x"2a", + 5108 => x"51", + 5109 => x"2e", + 5110 => x"51", + 5111 => x"3f", + 5112 => x"51", + 5113 => x"3f", + 5114 => x"f4", + 5115 => x"88", + 5116 => x"06", + 5117 => x"80", + 5118 => x"81", + 5119 => x"84", + 5120 => x"e8", + 5121 => x"fc", + 5122 => x"fe", + 5123 => x"fe", + 5124 => x"84", + 5125 => x"fa", + 5126 => x"70", + 5127 => x"55", + 5128 => x"2e", + 5129 => x"8e", + 5130 => x"0c", + 5131 => x"53", + 5132 => x"81", + 5133 => x"74", + 5134 => x"ff", + 5135 => x"53", + 5136 => x"83", + 5137 => x"74", + 5138 => x"38", + 5139 => x"75", + 5140 => x"53", + 5141 => x"09", + 5142 => x"38", + 5143 => x"81", + 5144 => x"80", + 5145 => x"29", + 5146 => x"05", + 5147 => x"70", + 5148 => x"fe", + 5149 => x"91", + 5150 => x"8b", + 5151 => x"33", + 5152 => x"2e", + 5153 => x"81", + 5154 => x"ff", + 5155 => x"95", + 5156 => x"38", + 5157 => x"91", + 5158 => x"88", + 5159 => x"cb", + 5160 => x"70", + 5161 => x"88", + 5162 => x"81", + 5163 => x"ff", + 5164 => x"91", + 5165 => x"81", + 5166 => x"78", + 5167 => x"81", + 5168 => x"91", + 5169 => x"99", + 5170 => x"59", + 5171 => x"3f", + 5172 => x"52", + 5173 => x"51", + 5174 => x"3f", + 5175 => x"08", + 5176 => x"38", + 5177 => x"51", + 5178 => x"81", + 5179 => x"91", + 5180 => x"fe", + 5181 => x"99", + 5182 => x"5a", + 5183 => x"80", + 5184 => x"fe", + 5185 => x"80", + 5186 => x"51", + 5187 => x"3f", + 5188 => x"f8", + 5189 => x"ff", + 5190 => x"88", + 5191 => x"70", + 5192 => x"59", + 5193 => x"2e", + 5194 => x"78", + 5195 => x"80", + 5196 => x"b0", + 5197 => x"38", + 5198 => x"aa", + 5199 => x"2e", + 5200 => x"78", + 5201 => x"38", + 5202 => x"ff", + 5203 => x"82", + 5204 => x"38", + 5205 => x"78", + 5206 => x"b8", + 5207 => x"2e", + 5208 => x"8e", + 5209 => x"bf", + 5210 => x"38", + 5211 => x"90", + 5212 => x"2e", + 5213 => x"78", + 5214 => x"fc", + 5215 => x"39", + 5216 => x"2e", + 5217 => x"78", + 5218 => x"88", + 5219 => x"b7", + 5220 => x"f8", + 5221 => x"38", + 5222 => x"24", + 5223 => x"80", + 5224 => x"cd", + 5225 => x"d1", + 5226 => x"78", + 5227 => x"8b", + 5228 => x"80", + 5229 => x"a8", + 5230 => x"39", + 5231 => x"2e", + 5232 => x"78", + 5233 => x"8c", + 5234 => x"fb", + 5235 => x"83", + 5236 => x"38", + 5237 => x"24", + 5238 => x"80", + 5239 => x"81", + 5240 => x"82", + 5241 => x"38", + 5242 => x"78", + 5243 => x"8d", + 5244 => x"81", + 5245 => x"f7", + 5246 => x"39", + 5247 => x"f4", + 5248 => x"f8", + 5249 => x"83", + 5250 => x"ca", + 5251 => x"38", + 5252 => x"51", + 5253 => x"b7", + 5254 => x"11", + 5255 => x"05", + 5256 => x"d4", + 5257 => x"88", + 5258 => x"88", + 5259 => x"25", + 5260 => x"43", + 5261 => x"05", + 5262 => x"80", + 5263 => x"51", + 5264 => x"3f", + 5265 => x"08", + 5266 => x"59", + 5267 => x"91", + 5268 => x"fe", + 5269 => x"81", + 5270 => x"39", + 5271 => x"51", + 5272 => x"b7", + 5273 => x"11", + 5274 => x"05", + 5275 => x"88", + 5276 => x"88", + 5277 => x"fc", + 5278 => x"53", + 5279 => x"80", + 5280 => x"51", + 5281 => x"3f", + 5282 => x"08", + 5283 => x"a0", + 5284 => x"39", + 5285 => x"f4", + 5286 => x"f8", + 5287 => x"82", + 5288 => x"ca", + 5289 => x"2e", + 5290 => x"89", + 5291 => x"38", + 5292 => x"f0", + 5293 => x"f8", + 5294 => x"82", + 5295 => x"ca", + 5296 => x"38", + 5297 => x"08", + 5298 => x"91", + 5299 => x"79", + 5300 => x"c5", + 5301 => x"cb", + 5302 => x"79", + 5303 => x"b4", + 5304 => x"b8", + 5305 => x"b5", + 5306 => x"ca", + 5307 => x"93", + 5308 => x"f8", + 5309 => x"a7", + 5310 => x"fb", + 5311 => x"3d", + 5312 => x"51", + 5313 => x"3f", + 5314 => x"08", + 5315 => x"f8", + 5316 => x"fe", + 5317 => x"81", + 5318 => x"88", + 5319 => x"51", + 5320 => x"80", + 5321 => x"3d", + 5322 => x"51", + 5323 => x"3f", + 5324 => x"08", + 5325 => x"f8", + 5326 => x"fe", + 5327 => x"91", + 5328 => x"b8", + 5329 => x"05", + 5330 => x"ea", + 5331 => x"ca", + 5332 => x"3d", + 5333 => x"52", + 5334 => x"bb", + 5335 => x"e4", + 5336 => x"bc", + 5337 => x"80", + 5338 => x"88", + 5339 => x"06", + 5340 => x"79", + 5341 => x"f5", + 5342 => x"ca", + 5343 => x"2e", + 5344 => x"91", + 5345 => x"51", + 5346 => x"fa", + 5347 => x"3d", + 5348 => x"53", + 5349 => x"51", + 5350 => x"3f", + 5351 => x"08", + 5352 => x"cb", + 5353 => x"fe", + 5354 => x"fe", + 5355 => x"ff", + 5356 => x"91", + 5357 => x"80", + 5358 => x"38", + 5359 => x"ec", + 5360 => x"f8", + 5361 => x"80", + 5362 => x"ca", + 5363 => x"38", + 5364 => x"08", + 5365 => x"ac", + 5366 => x"c3", + 5367 => x"5c", + 5368 => x"27", + 5369 => x"61", + 5370 => x"70", + 5371 => x"0c", + 5372 => x"f5", + 5373 => x"39", + 5374 => x"f4", + 5375 => x"f8", + 5376 => x"ff", + 5377 => x"ca", + 5378 => x"2e", + 5379 => x"b7", + 5380 => x"11", + 5381 => x"05", + 5382 => x"dc", + 5383 => x"88", + 5384 => x"f9", + 5385 => x"3d", + 5386 => x"53", + 5387 => x"51", + 5388 => x"3f", + 5389 => x"08", + 5390 => x"b3", + 5391 => x"b8", + 5392 => x"db", + 5393 => x"79", + 5394 => x"8c", + 5395 => x"79", + 5396 => x"5b", + 5397 => x"61", + 5398 => x"eb", + 5399 => x"fe", + 5400 => x"fe", + 5401 => x"fe", + 5402 => x"91", + 5403 => x"80", + 5404 => x"38", + 5405 => x"f0", + 5406 => x"f8", + 5407 => x"fe", + 5408 => x"ca", + 5409 => x"2e", + 5410 => x"b7", + 5411 => x"11", + 5412 => x"05", + 5413 => x"e0", + 5414 => x"88", + 5415 => x"f8", + 5416 => x"c3", + 5417 => x"f6", + 5418 => x"5a", + 5419 => x"a8", + 5420 => x"33", + 5421 => x"5a", + 5422 => x"2e", + 5423 => x"55", + 5424 => x"33", + 5425 => x"91", + 5426 => x"fe", + 5427 => x"81", + 5428 => x"05", + 5429 => x"39", + 5430 => x"51", + 5431 => x"b7", + 5432 => x"11", + 5433 => x"05", + 5434 => x"8c", + 5435 => x"88", + 5436 => x"38", + 5437 => x"33", + 5438 => x"2e", + 5439 => x"c6", + 5440 => x"b3", + 5441 => x"92", + 5442 => x"80", + 5443 => x"91", + 5444 => x"44", + 5445 => x"c7", + 5446 => x"78", + 5447 => x"c7", + 5448 => x"78", + 5449 => x"38", + 5450 => x"08", + 5451 => x"91", + 5452 => x"fc", + 5453 => x"b7", + 5454 => x"11", + 5455 => x"05", + 5456 => x"b4", + 5457 => x"88", + 5458 => x"38", + 5459 => x"33", + 5460 => x"2e", + 5461 => x"c6", + 5462 => x"b2", + 5463 => x"92", + 5464 => x"80", + 5465 => x"91", + 5466 => x"43", + 5467 => x"c7", + 5468 => x"78", + 5469 => x"c7", + 5470 => x"78", + 5471 => x"38", + 5472 => x"08", + 5473 => x"91", + 5474 => x"88", + 5475 => x"3d", + 5476 => x"53", + 5477 => x"51", + 5478 => x"3f", + 5479 => x"08", + 5480 => x"38", + 5481 => x"59", + 5482 => x"83", + 5483 => x"79", + 5484 => x"38", + 5485 => x"88", + 5486 => x"2e", + 5487 => x"42", + 5488 => x"51", + 5489 => x"3f", + 5490 => x"54", + 5491 => x"52", + 5492 => x"94", + 5493 => x"80", + 5494 => x"39", + 5495 => x"f4", + 5496 => x"f8", + 5497 => x"fc", + 5498 => x"ca", + 5499 => x"2e", + 5500 => x"b7", + 5501 => x"11", + 5502 => x"05", + 5503 => x"f8", + 5504 => x"88", + 5505 => x"a5", + 5506 => x"02", + 5507 => x"33", + 5508 => x"81", + 5509 => x"3d", + 5510 => x"53", + 5511 => x"51", + 5512 => x"3f", + 5513 => x"08", + 5514 => x"c3", + 5515 => x"33", + 5516 => x"c4", + 5517 => x"f9", + 5518 => x"f8", + 5519 => x"fe", + 5520 => x"79", + 5521 => x"59", + 5522 => x"f5", + 5523 => x"79", + 5524 => x"b7", + 5525 => x"11", + 5526 => x"05", + 5527 => x"98", + 5528 => x"88", + 5529 => x"91", + 5530 => x"02", + 5531 => x"33", + 5532 => x"81", + 5533 => x"b5", + 5534 => x"98", + 5535 => x"9f", + 5536 => x"39", + 5537 => x"e8", + 5538 => x"f8", + 5539 => x"fc", + 5540 => x"ca", + 5541 => x"2e", + 5542 => x"b7", + 5543 => x"11", + 5544 => x"05", + 5545 => x"c2", + 5546 => x"88", + 5547 => x"a6", + 5548 => x"02", + 5549 => x"79", + 5550 => x"5b", + 5551 => x"b7", + 5552 => x"11", + 5553 => x"05", + 5554 => x"9e", + 5555 => x"88", + 5556 => x"f4", + 5557 => x"70", + 5558 => x"91", + 5559 => x"fe", + 5560 => x"80", + 5561 => x"51", + 5562 => x"3f", + 5563 => x"33", + 5564 => x"2e", + 5565 => x"78", + 5566 => x"38", + 5567 => x"41", + 5568 => x"3d", + 5569 => x"53", + 5570 => x"51", + 5571 => x"3f", + 5572 => x"08", + 5573 => x"38", + 5574 => x"be", + 5575 => x"70", + 5576 => x"23", + 5577 => x"ae", + 5578 => x"98", + 5579 => x"ef", + 5580 => x"39", + 5581 => x"e8", + 5582 => x"f8", + 5583 => x"fb", + 5584 => x"ca", + 5585 => x"2e", + 5586 => x"b7", + 5587 => x"11", + 5588 => x"05", + 5589 => x"92", + 5590 => x"88", + 5591 => x"a1", + 5592 => x"71", + 5593 => x"84", + 5594 => x"3d", + 5595 => x"53", + 5596 => x"51", + 5597 => x"3f", + 5598 => x"08", + 5599 => x"ef", + 5600 => x"08", + 5601 => x"c4", + 5602 => x"f6", + 5603 => x"f8", + 5604 => x"fe", + 5605 => x"79", + 5606 => x"59", + 5607 => x"f2", + 5608 => x"79", + 5609 => x"b7", + 5610 => x"11", + 5611 => x"05", + 5612 => x"b6", + 5613 => x"88", + 5614 => x"99", + 5615 => x"60", + 5616 => x"ac", + 5617 => x"bb", + 5618 => x"71", + 5619 => x"84", + 5620 => x"ad", + 5621 => x"98", + 5622 => x"c3", + 5623 => x"39", + 5624 => x"51", + 5625 => x"3f", + 5626 => x"ef", + 5627 => x"ff", + 5628 => x"d0", + 5629 => x"a7", + 5630 => x"fe", + 5631 => x"f1", + 5632 => x"80", + 5633 => x"c0", + 5634 => x"84", + 5635 => x"87", + 5636 => x"0c", + 5637 => x"51", + 5638 => x"3f", + 5639 => x"91", + 5640 => x"fe", + 5641 => x"8c", + 5642 => x"87", + 5643 => x"0c", + 5644 => x"0b", + 5645 => x"94", + 5646 => x"39", + 5647 => x"f4", + 5648 => x"f8", + 5649 => x"f7", + 5650 => x"ca", + 5651 => x"2e", + 5652 => x"63", + 5653 => x"90", + 5654 => x"a7", + 5655 => x"78", + 5656 => x"fe", + 5657 => x"fe", + 5658 => x"fe", + 5659 => x"91", + 5660 => x"80", + 5661 => x"38", + 5662 => x"c5", + 5663 => x"f5", + 5664 => x"59", + 5665 => x"ca", + 5666 => x"91", + 5667 => x"80", + 5668 => x"38", + 5669 => x"08", + 5670 => x"c8", + 5671 => x"e3", + 5672 => x"39", + 5673 => x"51", + 5674 => x"3f", + 5675 => x"3f", + 5676 => x"91", + 5677 => x"fe", + 5678 => x"80", + 5679 => x"39", + 5680 => x"3f", + 5681 => x"64", + 5682 => x"59", + 5683 => x"f0", + 5684 => x"80", + 5685 => x"38", + 5686 => x"80", + 5687 => x"3d", + 5688 => x"51", + 5689 => x"3f", + 5690 => x"56", + 5691 => x"08", + 5692 => x"98", + 5693 => x"91", + 5694 => x"a3", + 5695 => x"5a", + 5696 => x"3f", + 5697 => x"58", + 5698 => x"57", + 5699 => x"81", + 5700 => x"05", + 5701 => x"91", + 5702 => x"91", + 5703 => x"79", + 5704 => x"3f", + 5705 => x"08", + 5706 => x"32", + 5707 => x"07", + 5708 => x"38", + 5709 => x"09", + 5710 => x"b3", + 5711 => x"ac", + 5712 => x"bf", + 5713 => x"39", + 5714 => x"80", + 5715 => x"bc", + 5716 => x"9b", + 5717 => x"98", + 5718 => x"9c", + 5719 => x"9c", + 5720 => x"e4", + 5721 => x"87", + 5722 => x"bc", + 5723 => x"94", + 5724 => x"c8", + 5725 => x"a7", + 5726 => x"e3", + 5727 => x"ea", + 5728 => x"ea", + 5729 => x"97", + 5730 => x"00", + 5731 => x"00", + 5732 => x"00", + 5733 => x"00", + 5734 => x"00", + 5735 => x"00", + 5736 => x"00", + 5737 => x"00", + 5738 => x"00", + 5739 => x"00", + 5740 => x"00", + 5741 => x"00", + 5742 => x"00", + 5743 => x"00", + 5744 => x"00", + 5745 => x"00", + 5746 => x"00", + 5747 => x"00", + 5748 => x"00", + 5749 => x"00", + 5750 => x"00", + 5751 => x"00", + 5752 => x"00", + 5753 => x"00", + 5754 => x"00", + 5755 => x"25", + 5756 => x"64", + 5757 => x"20", + 5758 => x"25", + 5759 => x"64", + 5760 => x"25", + 5761 => x"53", + 5762 => x"43", + 5763 => x"69", + 5764 => x"61", + 5765 => x"6e", + 5766 => x"20", + 5767 => x"6f", + 5768 => x"6f", + 5769 => x"6f", + 5770 => x"67", + 5771 => x"3a", + 5772 => x"76", + 5773 => x"73", + 5774 => x"70", + 5775 => x"65", + 5776 => x"64", + 5777 => x"20", + 5778 => x"49", + 5779 => x"20", + 5780 => x"4d", + 5781 => x"74", + 5782 => x"3d", + 5783 => x"58", + 5784 => x"69", + 5785 => x"25", + 5786 => x"29", + 5787 => x"20", + 5788 => x"42", + 5789 => x"20", + 5790 => x"61", + 5791 => x"25", + 5792 => x"2c", + 5793 => x"7a", + 5794 => x"30", + 5795 => x"2e", + 5796 => x"20", + 5797 => x"52", + 5798 => x"28", + 5799 => x"72", + 5800 => x"30", + 5801 => x"20", + 5802 => x"65", + 5803 => x"38", + 5804 => x"0a", + 5805 => x"20", + 5806 => x"49", + 5807 => x"4c", + 5808 => x"20", + 5809 => x"50", + 5810 => x"00", + 5811 => x"20", + 5812 => x"53", + 5813 => x"00", + 5814 => x"20", + 5815 => x"53", + 5816 => x"61", + 5817 => x"28", + 5818 => x"69", + 5819 => x"3d", + 5820 => x"58", + 5821 => x"00", + 5822 => x"20", + 5823 => x"49", + 5824 => x"52", + 5825 => x"54", + 5826 => x"4e", + 5827 => x"4c", + 5828 => x"0a", + 5829 => x"20", + 5830 => x"54", + 5831 => x"52", + 5832 => x"54", + 5833 => x"72", + 5834 => x"30", + 5835 => x"2e", + 5836 => x"41", + 5837 => x"65", + 5838 => x"73", + 5839 => x"20", + 5840 => x"43", + 5841 => x"52", + 5842 => x"74", + 5843 => x"63", + 5844 => x"20", + 5845 => x"72", + 5846 => x"20", + 5847 => x"30", + 5848 => x"00", + 5849 => x"20", + 5850 => x"43", + 5851 => x"4d", + 5852 => x"72", + 5853 => x"74", + 5854 => x"20", + 5855 => x"72", + 5856 => x"20", + 5857 => x"30", + 5858 => x"00", + 5859 => x"20", + 5860 => x"53", + 5861 => x"6b", + 5862 => x"61", + 5863 => x"41", + 5864 => x"65", + 5865 => x"20", + 5866 => x"20", + 5867 => x"30", + 5868 => x"00", + 5869 => x"20", + 5870 => x"5a", + 5871 => x"49", + 5872 => x"20", + 5873 => x"20", + 5874 => x"20", + 5875 => x"20", + 5876 => x"20", + 5877 => x"30", + 5878 => x"00", + 5879 => x"20", + 5880 => x"53", + 5881 => x"65", + 5882 => x"6c", + 5883 => x"20", + 5884 => x"71", + 5885 => x"20", + 5886 => x"20", + 5887 => x"30", + 5888 => x"00", + 5889 => x"53", + 5890 => x"6c", + 5891 => x"4d", + 5892 => x"75", + 5893 => x"46", + 5894 => x"00", + 5895 => x"45", + 5896 => x"45", + 5897 => x"69", + 5898 => x"55", + 5899 => x"6f", + 5900 => x"53", + 5901 => x"22", + 5902 => x"3a", + 5903 => x"3e", + 5904 => x"7c", + 5905 => x"46", + 5906 => x"46", + 5907 => x"32", + 5908 => x"eb", + 5909 => x"53", + 5910 => x"35", + 5911 => x"4e", + 5912 => x"41", + 5913 => x"20", + 5914 => x"41", + 5915 => x"20", + 5916 => x"4e", + 5917 => x"41", + 5918 => x"20", + 5919 => x"41", + 5920 => x"20", + 5921 => x"00", + 5922 => x"00", + 5923 => x"00", + 5924 => x"00", + 5925 => x"80", + 5926 => x"8e", + 5927 => x"45", + 5928 => x"49", + 5929 => x"90", + 5930 => x"99", + 5931 => x"59", + 5932 => x"9c", + 5933 => x"41", + 5934 => x"a5", + 5935 => x"a8", + 5936 => x"ac", + 5937 => x"b0", + 5938 => x"b4", + 5939 => x"b8", + 5940 => x"bc", + 5941 => x"c0", + 5942 => x"c4", + 5943 => x"c8", + 5944 => x"cc", + 5945 => x"d0", + 5946 => x"d4", + 5947 => x"d8", + 5948 => x"dc", + 5949 => x"e0", + 5950 => x"e4", + 5951 => x"e8", + 5952 => x"ec", + 5953 => x"f0", + 5954 => x"f4", + 5955 => x"f8", + 5956 => x"fc", + 5957 => x"2b", + 5958 => x"3d", + 5959 => x"5c", + 5960 => x"3c", + 5961 => x"7f", + 5962 => x"00", + 5963 => x"00", + 5964 => x"01", + 5965 => x"00", + 5966 => x"00", + 5967 => x"00", + 5968 => x"00", + 5969 => x"00", + 5970 => x"64", + 5971 => x"74", + 5972 => x"64", + 5973 => x"74", + 5974 => x"66", + 5975 => x"74", + 5976 => x"66", + 5977 => x"64", + 5978 => x"66", + 5979 => x"63", + 5980 => x"6d", + 5981 => x"61", + 5982 => x"6d", + 5983 => x"79", + 5984 => x"6d", + 5985 => x"66", + 5986 => x"6d", + 5987 => x"70", + 5988 => x"6d", + 5989 => x"6d", + 5990 => x"6d", + 5991 => x"68", + 5992 => x"68", + 5993 => x"68", + 5994 => x"68", + 5995 => x"63", + 5996 => x"00", + 5997 => x"6a", + 5998 => x"72", + 5999 => x"61", + 6000 => x"72", + 6001 => x"74", + 6002 => x"69", + 6003 => x"00", + 6004 => x"74", + 6005 => x"00", + 6006 => x"44", + 6007 => x"20", + 6008 => x"6f", + 6009 => x"49", + 6010 => x"72", + 6011 => x"20", + 6012 => x"6f", + 6013 => x"00", + 6014 => x"44", + 6015 => x"20", + 6016 => x"20", + 6017 => x"64", + 6018 => x"00", + 6019 => x"4e", + 6020 => x"69", + 6021 => x"66", + 6022 => x"64", + 6023 => x"4e", + 6024 => x"61", + 6025 => x"66", + 6026 => x"64", + 6027 => x"49", + 6028 => x"6c", + 6029 => x"66", + 6030 => x"6e", + 6031 => x"2e", + 6032 => x"41", + 6033 => x"73", + 6034 => x"65", + 6035 => x"64", + 6036 => x"46", + 6037 => x"20", + 6038 => x"65", + 6039 => x"20", + 6040 => x"73", + 6041 => x"0a", + 6042 => x"46", + 6043 => x"20", + 6044 => x"64", + 6045 => x"69", + 6046 => x"6c", + 6047 => x"0a", + 6048 => x"53", + 6049 => x"73", + 6050 => x"69", + 6051 => x"70", + 6052 => x"65", + 6053 => x"64", + 6054 => x"44", + 6055 => x"65", + 6056 => x"6d", + 6057 => x"20", + 6058 => x"69", + 6059 => x"6c", + 6060 => x"0a", + 6061 => x"44", + 6062 => x"20", + 6063 => x"20", + 6064 => x"62", + 6065 => x"2e", + 6066 => x"4e", + 6067 => x"6f", + 6068 => x"74", + 6069 => x"65", + 6070 => x"6c", + 6071 => x"73", + 6072 => x"20", + 6073 => x"6e", + 6074 => x"6e", + 6075 => x"73", + 6076 => x"00", + 6077 => x"46", + 6078 => x"61", + 6079 => x"62", + 6080 => x"65", + 6081 => x"00", + 6082 => x"54", + 6083 => x"6f", + 6084 => x"20", + 6085 => x"72", + 6086 => x"6f", + 6087 => x"61", + 6088 => x"6c", + 6089 => x"2e", + 6090 => x"46", + 6091 => x"20", + 6092 => x"6c", + 6093 => x"65", + 6094 => x"00", + 6095 => x"49", + 6096 => x"66", + 6097 => x"69", + 6098 => x"20", + 6099 => x"6f", + 6100 => x"0a", + 6101 => x"54", + 6102 => x"6d", + 6103 => x"20", + 6104 => x"6e", + 6105 => x"6c", + 6106 => x"0a", + 6107 => x"50", + 6108 => x"6d", + 6109 => x"72", + 6110 => x"6e", + 6111 => x"72", + 6112 => x"2e", + 6113 => x"53", + 6114 => x"65", + 6115 => x"0a", + 6116 => x"55", + 6117 => x"6f", + 6118 => x"65", + 6119 => x"72", + 6120 => x"0a", + 6121 => x"20", + 6122 => x"65", + 6123 => x"73", + 6124 => x"20", + 6125 => x"20", + 6126 => x"65", + 6127 => x"65", + 6128 => x"00", + 6129 => x"25", + 6130 => x"00", + 6131 => x"3a", + 6132 => x"25", + 6133 => x"00", + 6134 => x"20", + 6135 => x"20", + 6136 => x"00", + 6137 => x"25", + 6138 => x"00", + 6139 => x"20", + 6140 => x"20", + 6141 => x"7c", + 6142 => x"72", + 6143 => x"00", + 6144 => x"5a", + 6145 => x"41", + 6146 => x"0a", + 6147 => x"25", + 6148 => x"00", + 6149 => x"31", + 6150 => x"37", + 6151 => x"31", + 6152 => x"76", + 6153 => x"00", + 6154 => x"20", + 6155 => x"2c", + 6156 => x"76", + 6157 => x"32", + 6158 => x"25", + 6159 => x"73", + 6160 => x"0a", + 6161 => x"5a", + 6162 => x"41", + 6163 => x"74", + 6164 => x"75", + 6165 => x"48", + 6166 => x"6c", + 6167 => x"00", + 6168 => x"54", + 6169 => x"72", + 6170 => x"74", + 6171 => x"75", + 6172 => x"00", + 6173 => x"50", + 6174 => x"69", + 6175 => x"72", + 6176 => x"74", + 6177 => x"49", + 6178 => x"4c", + 6179 => x"20", + 6180 => x"65", + 6181 => x"70", + 6182 => x"49", + 6183 => x"4c", + 6184 => x"20", + 6185 => x"65", + 6186 => x"70", + 6187 => x"55", + 6188 => x"30", + 6189 => x"20", + 6190 => x"65", + 6191 => x"70", + 6192 => x"55", + 6193 => x"30", + 6194 => x"20", + 6195 => x"65", + 6196 => x"70", + 6197 => x"55", + 6198 => x"31", + 6199 => x"20", + 6200 => x"65", + 6201 => x"70", + 6202 => x"55", + 6203 => x"31", + 6204 => x"20", + 6205 => x"65", + 6206 => x"70", + 6207 => x"53", + 6208 => x"69", + 6209 => x"75", + 6210 => x"69", + 6211 => x"2e", + 6212 => x"00", + 6213 => x"45", + 6214 => x"6c", + 6215 => x"20", + 6216 => x"65", + 6217 => x"2e", + 6218 => x"30", + 6219 => x"46", + 6220 => x"65", + 6221 => x"6f", + 6222 => x"69", + 6223 => x"6c", + 6224 => x"20", + 6225 => x"63", + 6226 => x"20", + 6227 => x"70", + 6228 => x"73", + 6229 => x"6e", + 6230 => x"6d", + 6231 => x"61", + 6232 => x"2e", + 6233 => x"2a", + 6234 => x"42", + 6235 => x"64", + 6236 => x"20", + 6237 => x"0a", + 6238 => x"49", + 6239 => x"69", + 6240 => x"73", + 6241 => x"0a", + 6242 => x"46", + 6243 => x"65", + 6244 => x"6f", + 6245 => x"69", + 6246 => x"6c", + 6247 => x"2e", + 6248 => x"72", + 6249 => x"64", + 6250 => x"25", + 6251 => x"43", + 6252 => x"72", + 6253 => x"2e", + 6254 => x"43", + 6255 => x"69", + 6256 => x"2e", + 6257 => x"43", + 6258 => x"61", + 6259 => x"67", + 6260 => x"00", + 6261 => x"25", + 6262 => x"78", + 6263 => x"38", + 6264 => x"3e", + 6265 => x"6c", + 6266 => x"30", + 6267 => x"0a", + 6268 => x"44", + 6269 => x"20", + 6270 => x"6f", + 6271 => x"00", + 6272 => x"0a", + 6273 => x"70", + 6274 => x"65", + 6275 => x"25", + 6276 => x"20", + 6277 => x"58", + 6278 => x"3f", + 6279 => x"00", + 6280 => x"25", + 6281 => x"20", + 6282 => x"58", + 6283 => x"25", + 6284 => x"20", + 6285 => x"58", + 6286 => x"44", + 6287 => x"62", + 6288 => x"67", + 6289 => x"74", + 6290 => x"75", + 6291 => x"0a", + 6292 => x"45", + 6293 => x"6c", + 6294 => x"20", + 6295 => x"65", + 6296 => x"70", + 6297 => x"00", + 6298 => x"44", + 6299 => x"62", + 6300 => x"20", + 6301 => x"74", + 6302 => x"66", + 6303 => x"45", + 6304 => x"6c", + 6305 => x"20", + 6306 => x"74", + 6307 => x"66", + 6308 => x"45", + 6309 => x"75", + 6310 => x"67", + 6311 => x"64", + 6312 => x"20", + 6313 => x"78", + 6314 => x"2e", + 6315 => x"43", + 6316 => x"69", + 6317 => x"63", + 6318 => x"20", + 6319 => x"30", + 6320 => x"2e", + 6321 => x"00", + 6322 => x"43", + 6323 => x"20", + 6324 => x"75", + 6325 => x"64", + 6326 => x"64", + 6327 => x"25", + 6328 => x"0a", + 6329 => x"52", + 6330 => x"61", + 6331 => x"6e", + 6332 => x"70", + 6333 => x"63", + 6334 => x"6f", + 6335 => x"2e", + 6336 => x"43", + 6337 => x"20", + 6338 => x"6f", + 6339 => x"6e", + 6340 => x"2e", + 6341 => x"5a", + 6342 => x"62", + 6343 => x"25", + 6344 => x"25", + 6345 => x"73", + 6346 => x"00", + 6347 => x"42", + 6348 => x"63", + 6349 => x"61", + 6350 => x"0a", + 6351 => x"52", + 6352 => x"69", + 6353 => x"2e", + 6354 => x"45", + 6355 => x"6c", + 6356 => x"20", + 6357 => x"65", + 6358 => x"70", + 6359 => x"2e", + 6360 => x"00", + 6361 => x"00", + 6362 => x"00", + 6363 => x"00", + 6364 => x"00", + 6365 => x"00", + 6366 => x"00", + 6367 => x"00", + 6368 => x"00", + 6369 => x"00", + 6370 => x"00", + 6371 => x"05", + 6372 => x"00", + 6373 => x"01", + 6374 => x"80", + 6375 => x"01", + 6376 => x"00", + 6377 => x"01", + 6378 => x"00", + 6379 => x"01", + 6380 => x"00", + 6381 => x"00", + 6382 => x"00", + 6383 => x"01", + 6384 => x"00", + 6385 => x"00", + 6386 => x"00", + 6387 => x"01", + 6388 => x"00", + 6389 => x"00", + 6390 => x"00", + 6391 => x"01", + 6392 => x"00", + 6393 => x"00", + 6394 => x"00", + 6395 => x"01", + 6396 => x"00", + 6397 => x"00", + 6398 => x"00", + 6399 => x"01", + 6400 => x"00", + 6401 => x"00", + 6402 => x"00", + 6403 => x"01", + 6404 => x"00", + 6405 => x"00", + 6406 => x"00", + 6407 => x"01", + 6408 => x"00", + 6409 => x"00", + 6410 => x"00", + 6411 => x"01", + 6412 => x"00", + 6413 => x"00", + 6414 => x"00", + 6415 => x"01", + 6416 => x"00", + 6417 => x"00", + 6418 => x"00", + 6419 => x"01", + 6420 => x"00", + 6421 => x"00", + 6422 => x"00", + 6423 => x"01", + 6424 => x"00", + 6425 => x"00", + 6426 => x"00", + 6427 => x"01", + 6428 => x"00", + 6429 => x"00", + 6430 => x"00", + 6431 => x"01", + 6432 => x"00", + 6433 => x"00", + 6434 => x"00", + 6435 => x"01", + 6436 => x"00", + 6437 => x"00", + 6438 => x"00", + 6439 => x"01", + 6440 => x"00", + 6441 => x"00", + 6442 => x"00", + 6443 => x"01", + 6444 => x"00", + 6445 => x"00", + 6446 => x"00", + 6447 => x"01", + 6448 => x"00", + 6449 => x"00", + 6450 => x"00", + 6451 => x"01", + 6452 => x"00", + 6453 => x"00", + 6454 => x"00", + 6455 => x"01", + 6456 => x"00", + 6457 => x"00", + 6458 => x"00", + 6459 => x"01", + 6460 => x"00", + 6461 => x"00", + 6462 => x"00", + 6463 => x"01", + 6464 => x"00", + 6465 => x"00", + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; +end arch; diff --git a/zpu/devices/sysbus/BRAM/IOCP_ZPUTA_SinglePortBootBRAM.vhd b/zpu/devices/sysbus/BRAM/IOCP_ZPUTA_SinglePortBootBRAM.vhd new file mode 100644 index 0000000..3fcb9b3 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/IOCP_ZPUTA_SinglePortBootBRAM.vhd @@ -0,0 +1,31256 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use pkgs.config_pkg.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity SinglePortBootBRAM is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end SinglePortBootBRAM; + +architecture arch of SinglePortBootBRAM is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + 0 => x"88", + 1 => x"00", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"0b", + 10 => x"08", + 11 => x"8c", + 12 => x"04", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"08", + 17 => x"09", + 18 => x"05", + 19 => x"83", + 20 => x"52", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"08", + 25 => x"73", + 26 => x"81", + 27 => x"83", + 28 => x"06", + 29 => x"ff", + 30 => x"0b", + 31 => x"00", + 32 => x"05", + 33 => x"73", + 34 => x"06", + 35 => x"06", + 36 => x"06", + 37 => x"00", + 38 => x"00", + 39 => x"00", + 40 => x"73", + 41 => x"53", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"09", + 49 => x"06", + 50 => x"72", + 51 => x"72", + 52 => x"31", + 53 => x"06", + 54 => x"51", + 55 => x"00", + 56 => x"73", + 57 => x"53", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"88", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"2b", + 81 => x"04", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"06", + 89 => x"0b", + 90 => x"a7", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"ff", + 97 => x"2a", + 98 => x"0a", + 99 => x"05", + 100 => x"51", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"51", + 105 => x"83", + 106 => x"05", + 107 => x"2b", + 108 => x"72", + 109 => x"51", + 110 => x"00", + 111 => x"00", + 112 => x"05", + 113 => x"70", + 114 => x"06", + 115 => x"53", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"05", + 121 => x"70", + 122 => x"06", + 123 => x"06", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"05", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"81", + 137 => x"51", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"06", + 145 => x"06", + 146 => x"04", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"08", + 153 => x"09", + 154 => x"05", + 155 => x"2a", + 156 => x"52", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"08", + 161 => x"9f", + 162 => x"06", + 163 => x"08", + 164 => x"0b", + 165 => x"00", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"75", + 170 => x"89", + 171 => x"50", + 172 => x"90", + 173 => x"88", + 174 => x"00", + 175 => x"00", + 176 => x"08", + 177 => x"75", + 178 => x"8a", + 179 => x"50", + 180 => x"90", + 181 => x"88", + 182 => x"00", + 183 => x"00", + 184 => x"81", + 185 => x"0a", + 186 => x"05", + 187 => x"06", + 188 => x"74", + 189 => x"06", + 190 => x"51", + 191 => x"00", + 192 => x"81", + 193 => x"0a", + 194 => x"ff", + 195 => x"71", + 196 => x"72", + 197 => x"05", + 198 => x"51", + 199 => x"00", + 200 => x"04", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"52", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"72", + 233 => x"52", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"ff", + 249 => x"51", + 250 => x"00", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"04", + 257 => x"00", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"53", + 266 => x"00", + 267 => x"06", + 268 => x"09", + 269 => x"05", + 270 => x"2b", + 271 => x"06", + 272 => x"04", + 273 => x"72", + 274 => x"05", + 275 => x"05", + 276 => x"72", + 277 => x"53", + 278 => x"51", + 279 => x"04", + 280 => x"88", + 281 => x"00", + 282 => x"70", + 283 => x"8b", + 284 => x"70", + 285 => x"0c", + 286 => x"88", + 287 => x"99", + 288 => x"02", + 289 => x"3d", + 290 => x"94", + 291 => x"08", + 292 => x"88", + 293 => x"82", + 294 => x"08", + 295 => x"54", + 296 => x"94", + 297 => x"08", + 298 => x"fd", + 299 => x"53", + 300 => x"05", + 301 => x"08", + 302 => x"51", + 303 => x"88", + 304 => x"0c", + 305 => x"0d", + 306 => x"94", + 307 => x"0c", + 308 => x"80", + 309 => x"fc", + 310 => x"08", + 311 => x"80", + 312 => x"94", + 313 => x"08", + 314 => x"88", + 315 => x"0b", + 316 => x"05", + 317 => x"fc", + 318 => x"38", + 319 => x"08", + 320 => x"94", + 321 => x"08", + 322 => x"05", + 323 => x"8c", + 324 => x"25", + 325 => x"08", + 326 => x"30", + 327 => x"05", + 328 => x"94", + 329 => x"0c", + 330 => x"05", + 331 => x"81", + 332 => x"f0", + 333 => x"08", + 334 => x"94", + 335 => x"0c", + 336 => x"08", + 337 => x"52", + 338 => x"05", + 339 => x"a7", + 340 => x"70", + 341 => x"05", + 342 => x"08", + 343 => x"80", + 344 => x"94", + 345 => x"08", + 346 => x"f8", + 347 => x"08", + 348 => x"70", + 349 => x"89", + 350 => x"0c", + 351 => x"02", + 352 => x"3d", + 353 => x"94", + 354 => x"0c", + 355 => x"05", + 356 => x"93", + 357 => x"88", + 358 => x"94", + 359 => x"0c", + 360 => x"08", + 361 => x"94", + 362 => x"08", + 363 => x"38", + 364 => x"05", + 365 => x"08", + 366 => x"81", + 367 => x"8c", + 368 => x"94", + 369 => x"08", + 370 => x"88", + 371 => x"08", + 372 => x"54", + 373 => x"05", + 374 => x"8c", + 375 => x"f8", + 376 => x"94", + 377 => x"0c", + 378 => x"05", + 379 => x"0c", + 380 => x"0d", + 381 => x"94", + 382 => x"0c", + 383 => x"81", + 384 => x"fc", + 385 => x"0b", + 386 => x"05", + 387 => x"8c", + 388 => x"08", + 389 => x"27", + 390 => x"08", + 391 => x"80", + 392 => x"80", + 393 => x"8c", + 394 => x"99", + 395 => x"8c", + 396 => x"94", + 397 => x"0c", + 398 => x"05", + 399 => x"08", + 400 => x"c9", + 401 => x"fc", + 402 => x"2e", + 403 => x"94", + 404 => x"08", + 405 => x"05", + 406 => x"38", + 407 => x"05", + 408 => x"8c", + 409 => x"94", + 410 => x"0c", + 411 => x"05", + 412 => x"fc", + 413 => x"94", + 414 => x"0c", + 415 => x"05", + 416 => x"94", + 417 => x"0c", + 418 => x"05", + 419 => x"94", + 420 => x"0c", + 421 => x"94", + 422 => x"08", + 423 => x"38", + 424 => x"05", + 425 => x"08", + 426 => x"51", + 427 => x"08", + 428 => x"70", + 429 => x"05", + 430 => x"08", + 431 => x"88", + 432 => x"0d", + 433 => x"ff", + 434 => x"88", + 435 => x"92", + 436 => x"0b", + 437 => x"8c", + 438 => x"87", + 439 => x"0c", + 440 => x"8c", + 441 => x"06", + 442 => x"80", + 443 => x"87", + 444 => x"08", + 445 => x"38", + 446 => x"8c", + 447 => x"80", + 448 => x"93", + 449 => x"98", + 450 => x"70", + 451 => x"38", + 452 => x"0b", + 453 => x"0b", + 454 => x"a8", + 455 => x"83", + 456 => x"fa", + 457 => x"7b", + 458 => x"56", + 459 => x"0b", + 460 => x"33", + 461 => x"55", + 462 => x"75", + 463 => x"06", + 464 => x"85", + 465 => x"98", + 466 => x"87", + 467 => x"0c", + 468 => x"c0", + 469 => x"87", + 470 => x"08", + 471 => x"70", + 472 => x"52", + 473 => x"2e", + 474 => x"c0", + 475 => x"70", + 476 => x"76", + 477 => x"53", + 478 => x"2e", + 479 => x"80", + 480 => x"71", + 481 => x"05", + 482 => x"14", + 483 => x"55", + 484 => x"51", + 485 => x"8b", + 486 => x"98", + 487 => x"70", + 488 => x"87", + 489 => x"08", + 490 => x"38", + 491 => x"c0", + 492 => x"87", + 493 => x"08", + 494 => x"51", + 495 => x"38", + 496 => x"80", + 497 => x"52", + 498 => x"09", + 499 => x"38", + 500 => x"8c", + 501 => x"72", + 502 => x"06", + 503 => x"52", + 504 => x"88", + 505 => x"fe", + 506 => x"81", + 507 => x"33", + 508 => x"07", + 509 => x"51", + 510 => x"04", + 511 => x"75", + 512 => x"82", + 513 => x"90", + 514 => x"2b", + 515 => x"33", + 516 => x"88", + 517 => x"71", + 518 => x"52", + 519 => x"54", + 520 => x"0d", + 521 => x"0d", + 522 => x"0b", + 523 => x"57", + 524 => x"27", + 525 => x"76", + 526 => x"27", + 527 => x"75", + 528 => x"82", + 529 => x"74", + 530 => x"38", + 531 => x"74", + 532 => x"83", + 533 => x"76", + 534 => x"17", + 535 => x"88", + 536 => x"55", + 537 => x"88", + 538 => x"74", + 539 => x"3f", + 540 => x"ff", + 541 => x"ad", + 542 => x"76", + 543 => x"fc", + 544 => x"87", + 545 => x"08", + 546 => x"3d", + 547 => x"fd", + 548 => x"08", + 549 => x"51", + 550 => x"88", + 551 => x"06", + 552 => x"81", + 553 => x"0c", + 554 => x"04", + 555 => x"0b", + 556 => x"ac", + 557 => x"88", + 558 => x"05", + 559 => x"80", + 560 => x"27", + 561 => x"14", + 562 => x"29", + 563 => x"05", + 564 => x"88", + 565 => x"0d", + 566 => x"0d", + 567 => x"0b", + 568 => x"9f", + 569 => x"33", + 570 => x"71", + 571 => x"81", + 572 => x"94", + 573 => x"ef", + 574 => x"90", + 575 => x"14", + 576 => x"3f", + 577 => x"ff", + 578 => x"07", + 579 => x"3d", + 580 => x"3d", + 581 => x"0b", + 582 => x"08", + 583 => x"75", + 584 => x"08", + 585 => x"2e", + 586 => x"14", + 587 => x"85", + 588 => x"b0", + 589 => x"38", + 590 => x"71", + 591 => x"81", + 592 => x"90", + 593 => x"72", + 594 => x"72", + 595 => x"38", + 596 => x"d8", + 597 => x"52", + 598 => x"14", + 599 => x"90", + 600 => x"52", + 601 => x"86", + 602 => x"fa", + 603 => x"0b", + 604 => x"ac", + 605 => x"81", + 606 => x"ff", + 607 => x"54", + 608 => x"80", + 609 => x"90", + 610 => x"72", + 611 => x"52", + 612 => x"73", + 613 => x"71", + 614 => x"81", + 615 => x"0c", + 616 => x"53", + 617 => x"83", + 618 => x"22", + 619 => x"76", + 620 => x"b5", + 621 => x"33", + 622 => x"84", + 623 => x"71", + 624 => x"51", + 625 => x"81", + 626 => x"08", + 627 => x"83", + 628 => x"88", + 629 => x"96", + 630 => x"8c", + 631 => x"08", + 632 => x"3f", + 633 => x"16", + 634 => x"23", + 635 => x"88", + 636 => x"0d", + 637 => x"0d", + 638 => x"58", + 639 => x"33", + 640 => x"2e", + 641 => x"88", + 642 => x"70", + 643 => x"39", + 644 => x"56", + 645 => x"2e", + 646 => x"84", + 647 => x"43", + 648 => x"1d", + 649 => x"33", + 650 => x"9f", + 651 => x"7b", + 652 => x"3f", + 653 => x"80", + 654 => x"d3", + 655 => x"84", + 656 => x"58", + 657 => x"55", + 658 => x"81", + 659 => x"ff", + 660 => x"ff", + 661 => x"06", + 662 => x"70", + 663 => x"7f", + 664 => x"7a", + 665 => x"81", + 666 => x"13", + 667 => x"af", + 668 => x"a0", + 669 => x"80", + 670 => x"51", + 671 => x"5d", + 672 => x"80", + 673 => x"ae", + 674 => x"06", + 675 => x"55", + 676 => x"75", + 677 => x"80", + 678 => x"79", + 679 => x"30", + 680 => x"70", + 681 => x"07", + 682 => x"51", + 683 => x"75", + 684 => x"58", + 685 => x"ab", + 686 => x"19", + 687 => x"06", + 688 => x"5a", + 689 => x"75", + 690 => x"39", + 691 => x"0c", + 692 => x"a0", + 693 => x"81", + 694 => x"1a", + 695 => x"fc", + 696 => x"08", + 697 => x"a0", + 698 => x"70", + 699 => x"e0", + 700 => x"90", + 701 => x"7c", + 702 => x"3f", + 703 => x"88", + 704 => x"38", + 705 => x"74", + 706 => x"ee", + 707 => x"33", + 708 => x"70", + 709 => x"56", + 710 => x"38", + 711 => x"1e", + 712 => x"59", + 713 => x"ff", + 714 => x"ff", + 715 => x"79", + 716 => x"5b", + 717 => x"81", + 718 => x"71", + 719 => x"56", + 720 => x"2e", + 721 => x"39", + 722 => x"92", + 723 => x"fc", + 724 => x"8e", + 725 => x"56", + 726 => x"38", + 727 => x"56", + 728 => x"8b", + 729 => x"55", + 730 => x"8b", + 731 => x"84", + 732 => x"06", + 733 => x"74", + 734 => x"56", + 735 => x"56", + 736 => x"51", + 737 => x"88", + 738 => x"0c", + 739 => x"75", + 740 => x"3d", + 741 => x"3d", + 742 => x"59", + 743 => x"83", + 744 => x"52", + 745 => x"fb", + 746 => x"88", + 747 => x"38", + 748 => x"b3", + 749 => x"83", + 750 => x"55", + 751 => x"82", + 752 => x"09", + 753 => x"ce", + 754 => x"b6", + 755 => x"76", + 756 => x"3f", + 757 => x"88", + 758 => x"76", + 759 => x"3f", + 760 => x"ff", + 761 => x"74", + 762 => x"2e", + 763 => x"54", + 764 => x"77", + 765 => x"f6", + 766 => x"08", + 767 => x"94", + 768 => x"f7", + 769 => x"08", + 770 => x"06", + 771 => x"82", + 772 => x"38", + 773 => x"88", + 774 => x"0d", + 775 => x"0d", + 776 => x"0b", + 777 => x"9f", + 778 => x"9b", + 779 => x"81", + 780 => x"56", + 781 => x"38", + 782 => x"8d", + 783 => x"57", + 784 => x"3f", + 785 => x"ff", + 786 => x"81", + 787 => x"06", + 788 => x"54", + 789 => x"74", + 790 => x"f5", + 791 => x"08", + 792 => x"3d", + 793 => x"80", + 794 => x"95", + 795 => x"51", + 796 => x"88", + 797 => x"53", + 798 => x"fe", + 799 => x"08", + 800 => x"57", + 801 => x"09", + 802 => x"38", + 803 => x"99", + 804 => x"2e", + 805 => x"56", + 806 => x"a4", + 807 => x"79", + 808 => x"f4", + 809 => x"56", + 810 => x"fd", + 811 => x"e5", + 812 => x"b3", + 813 => x"83", + 814 => x"58", + 815 => x"95", + 816 => x"51", + 817 => x"88", + 818 => x"af", + 819 => x"71", + 820 => x"05", + 821 => x"54", + 822 => x"f6", + 823 => x"08", + 824 => x"06", + 825 => x"1a", + 826 => x"33", + 827 => x"95", + 828 => x"51", + 829 => x"88", + 830 => x"23", + 831 => x"05", + 832 => x"3f", + 833 => x"ff", + 834 => x"75", + 835 => x"3d", + 836 => x"f5", + 837 => x"08", + 838 => x"f5", + 839 => x"08", + 840 => x"06", + 841 => x"79", + 842 => x"22", + 843 => x"82", + 844 => x"72", + 845 => x"59", + 846 => x"ee", + 847 => x"08", + 848 => x"88", + 849 => x"08", + 850 => x"56", + 851 => x"df", + 852 => x"38", + 853 => x"ff", + 854 => x"85", + 855 => x"89", + 856 => x"76", + 857 => x"c1", + 858 => x"34", + 859 => x"09", + 860 => x"38", + 861 => x"05", + 862 => x"3f", + 863 => x"1a", + 864 => x"8c", + 865 => x"90", + 866 => x"83", + 867 => x"8c", + 868 => x"71", + 869 => x"94", + 870 => x"80", + 871 => x"34", + 872 => x"0b", + 873 => x"80", + 874 => x"0c", + 875 => x"04", + 876 => x"0b", + 877 => x"ac", + 878 => x"54", + 879 => x"80", + 880 => x"0b", + 881 => x"98", + 882 => x"45", + 883 => x"3d", + 884 => x"ec", + 885 => x"9d", + 886 => x"54", + 887 => x"c0", + 888 => x"33", + 889 => x"2e", + 890 => x"a7", + 891 => x"84", + 892 => x"06", + 893 => x"73", + 894 => x"38", + 895 => x"39", + 896 => x"d5", + 897 => x"a0", + 898 => x"3d", + 899 => x"f3", + 900 => x"08", + 901 => x"73", + 902 => x"81", + 903 => x"34", + 904 => x"98", + 905 => x"f6", + 906 => x"7f", + 907 => x"0b", + 908 => x"59", + 909 => x"80", + 910 => x"57", + 911 => x"81", + 912 => x"16", + 913 => x"55", + 914 => x"80", + 915 => x"38", + 916 => x"81", + 917 => x"39", + 918 => x"17", + 919 => x"81", + 920 => x"16", + 921 => x"08", + 922 => x"78", + 923 => x"74", + 924 => x"2e", + 925 => x"98", + 926 => x"83", + 927 => x"57", + 928 => x"38", + 929 => x"ff", + 930 => x"2a", + 931 => x"ff", + 932 => x"79", + 933 => x"87", + 934 => x"08", + 935 => x"a4", + 936 => x"f3", + 937 => x"08", + 938 => x"27", + 939 => x"74", + 940 => x"a4", + 941 => x"f3", + 942 => x"08", + 943 => x"80", + 944 => x"38", + 945 => x"a8", + 946 => x"16", + 947 => x"06", + 948 => x"31", + 949 => x"75", + 950 => x"77", + 951 => x"98", + 952 => x"ff", + 953 => x"16", + 954 => x"51", + 955 => x"88", + 956 => x"38", + 957 => x"15", + 958 => x"77", + 959 => x"08", + 960 => x"58", + 961 => x"fe", + 962 => x"19", + 963 => x"39", + 964 => x"88", + 965 => x"0d", + 966 => x"0d", + 967 => x"e4", + 968 => x"94", + 969 => x"90", + 970 => x"87", + 971 => x"0c", + 972 => x"0b", + 973 => x"84", + 974 => x"83", + 975 => x"94", + 976 => x"b0", + 977 => x"3f", + 978 => x"38", + 979 => x"fc", + 980 => x"08", + 981 => x"80", + 982 => x"87", + 983 => x"0c", + 984 => x"fc", + 985 => x"80", + 986 => x"fd", + 987 => x"08", + 988 => x"54", + 989 => x"86", + 990 => x"55", + 991 => x"80", + 992 => x"80", + 993 => x"00", + 994 => x"ff", + 995 => x"ff", + 996 => x"ff", + 997 => x"00", + 998 => x"54", + 999 => x"59", + 1000 => x"4d", + 1001 => x"00", + 1002 => x"00", + 2048 => x"c4", + 2049 => x"0b", + 2050 => x"04", + 2051 => x"ff", + 2052 => x"ff", + 2053 => x"ff", + 2054 => x"ff", + 2055 => x"ff", + 2056 => x"c4", + 2057 => x"0b", + 2058 => x"04", + 2059 => x"c4", + 2060 => x"0b", + 2061 => x"04", + 2062 => x"c4", + 2063 => x"0b", + 2064 => x"04", + 2065 => x"c4", + 2066 => x"0b", + 2067 => x"04", + 2068 => x"c4", + 2069 => x"0b", + 2070 => x"04", + 2071 => x"c5", + 2072 => x"0b", + 2073 => x"04", + 2074 => x"c5", + 2075 => x"0b", + 2076 => x"04", + 2077 => x"c5", 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=> x"d4", + 2196 => x"90", + 2197 => x"d4", + 2198 => x"8b", + 2199 => x"d4", + 2200 => x"90", + 2201 => x"d4", + 2202 => x"c4", + 2203 => x"d4", + 2204 => x"90", + 2205 => x"d4", + 2206 => x"a8", + 2207 => x"d4", + 2208 => x"90", + 2209 => x"d4", + 2210 => x"be", + 2211 => x"d4", + 2212 => x"90", + 2213 => x"d4", + 2214 => x"9d", + 2215 => x"d4", + 2216 => x"90", + 2217 => x"d4", + 2218 => x"b3", + 2219 => x"d4", + 2220 => x"90", + 2221 => x"d4", + 2222 => x"d7", + 2223 => x"d4", + 2224 => x"90", + 2225 => x"d4", + 2226 => x"80", + 2227 => x"d4", + 2228 => x"90", + 2229 => x"d4", + 2230 => x"ce", + 2231 => x"d4", + 2232 => x"90", + 2233 => x"d4", + 2234 => x"d8", + 2235 => x"d4", + 2236 => x"90", + 2237 => x"d4", + 2238 => x"90", + 2239 => x"d4", + 2240 => x"90", + 2241 => x"d4", + 2242 => x"ea", + 2243 => x"d4", + 2244 => x"90", + 2245 => x"d4", + 2246 => x"f2", + 2247 => x"d4", + 2248 => x"90", + 2249 => x"d4", + 2250 => x"e9", + 2251 => x"d4", + 2252 => x"90", + 2253 => x"d4", + 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x"d4", + 2372 => x"90", + 2373 => x"c8", + 2374 => x"cc", + 2375 => x"80", + 2376 => x"05", + 2377 => x"0b", + 2378 => x"04", + 2379 => x"51", + 2380 => x"04", + 2381 => x"93", + 2382 => x"82", + 2383 => x"fd", + 2384 => x"53", + 2385 => x"08", + 2386 => x"52", + 2387 => x"08", + 2388 => x"51", + 2389 => x"82", + 2390 => x"70", + 2391 => x"0c", + 2392 => x"0d", + 2393 => x"0c", + 2394 => x"d4", + 2395 => x"93", + 2396 => x"3d", + 2397 => x"82", + 2398 => x"8c", + 2399 => x"82", + 2400 => x"88", + 2401 => x"93", + 2402 => x"c8", + 2403 => x"93", + 2404 => x"85", + 2405 => x"93", + 2406 => x"82", + 2407 => x"02", + 2408 => x"0c", + 2409 => x"81", + 2410 => x"d4", + 2411 => x"0c", + 2412 => x"93", + 2413 => x"05", + 2414 => x"d4", + 2415 => x"08", + 2416 => x"08", + 2417 => x"27", + 2418 => x"93", + 2419 => x"05", + 2420 => x"ae", + 2421 => x"82", + 2422 => x"8c", + 2423 => x"a2", + 2424 => x"d4", + 2425 => x"08", + 2426 => x"d4", + 2427 => x"0c", + 2428 => x"08", + 2429 => x"10", + 2430 => x"08", + 2431 => x"ff", + 2432 => x"93", + 2433 => x"05", + 2434 => x"80", + 2435 => x"93", + 2436 => x"05", + 2437 => x"d4", + 2438 => x"08", + 2439 => x"82", + 2440 => x"88", + 2441 => x"93", + 2442 => x"05", + 2443 => x"93", + 2444 => x"05", + 2445 => x"d4", + 2446 => x"08", + 2447 => x"08", + 2448 => x"07", + 2449 => x"08", + 2450 => x"82", + 2451 => x"fc", + 2452 => x"2a", + 2453 => x"08", + 2454 => x"82", + 2455 => x"8c", + 2456 => x"2a", + 2457 => x"08", + 2458 => x"ff", + 2459 => x"93", + 2460 => x"05", + 2461 => x"93", + 2462 => x"d4", + 2463 => x"08", + 2464 => x"d4", + 2465 => x"0c", + 2466 => x"82", + 2467 => x"f8", + 2468 => x"82", + 2469 => x"f4", + 2470 => x"82", + 2471 => x"f4", + 2472 => x"93", + 2473 => x"3d", + 2474 => x"d4", + 2475 => x"3d", + 2476 => x"71", + 2477 => x"9f", + 2478 => x"55", + 2479 => x"72", + 2480 => x"74", + 2481 => x"70", + 2482 => x"38", + 2483 => x"71", + 2484 => x"38", + 2485 => x"81", + 2486 => x"ff", + 2487 => x"ff", + 2488 => x"06", + 2489 => x"82", + 2490 => x"86", + 2491 => x"74", + 2492 => x"75", + 2493 => x"90", + 2494 => x"54", + 2495 => x"27", + 2496 => x"71", + 2497 => x"53", + 2498 => x"70", + 2499 => x"0c", + 2500 => x"84", + 2501 => x"72", + 2502 => x"05", + 2503 => x"12", + 2504 => x"26", + 2505 => x"72", + 2506 => x"72", + 2507 => x"05", + 2508 => x"12", + 2509 => x"26", + 2510 => x"53", + 2511 => x"fb", + 2512 => x"79", + 2513 => x"83", + 2514 => x"52", + 2515 => x"71", + 2516 => x"54", + 2517 => x"73", + 2518 => x"c6", + 2519 => x"54", + 2520 => x"70", + 2521 => x"52", + 2522 => x"2e", + 2523 => x"33", + 2524 => x"2e", + 2525 => x"95", + 2526 => x"81", + 2527 => x"70", + 2528 => x"54", + 2529 => x"70", + 2530 => x"33", + 2531 => x"ff", + 2532 => x"ff", + 2533 => x"31", + 2534 => x"0c", + 2535 => x"3d", + 2536 => x"09", + 2537 => x"fd", + 2538 => x"70", + 2539 => x"81", + 2540 => x"51", + 2541 => x"38", + 2542 => x"16", + 2543 => x"56", + 2544 => x"08", + 2545 => x"73", + 2546 => x"ff", + 2547 => x"0b", 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x"a5", + 2607 => x"33", + 2608 => x"79", + 2609 => x"99", + 2610 => x"33", + 2611 => x"79", + 2612 => x"8d", + 2613 => x"22", + 2614 => x"79", + 2615 => x"81", + 2616 => x"1c", + 2617 => x"5b", + 2618 => x"26", + 2619 => x"8a", + 2620 => x"88", + 2621 => x"86", + 2622 => x"85", + 2623 => x"84", + 2624 => x"83", + 2625 => x"82", + 2626 => x"7b", + 2627 => x"f6", + 2628 => x"89", + 2629 => x"98", + 2630 => x"7b", + 2631 => x"87", + 2632 => x"0c", + 2633 => x"87", + 2634 => x"0c", + 2635 => x"87", + 2636 => x"0c", + 2637 => x"87", + 2638 => x"0c", + 2639 => x"87", + 2640 => x"0c", + 2641 => x"87", + 2642 => x"0c", + 2643 => x"87", + 2644 => x"0c", + 2645 => x"87", + 2646 => x"0c", + 2647 => x"80", + 2648 => x"93", + 2649 => x"3d", + 2650 => x"3d", + 2651 => x"87", + 2652 => x"5c", + 2653 => x"87", + 2654 => x"08", + 2655 => x"23", + 2656 => x"b8", + 2657 => x"82", + 2658 => x"c0", + 2659 => x"5b", + 2660 => x"34", + 2661 => x"b0", + 2662 => x"84", + 2663 => x"c0", + 2664 => x"5b", + 2665 => x"34", + 2666 => x"a8", + 2667 => x"86", + 2668 => x"c0", + 2669 => x"5b", + 2670 => x"23", + 2671 => x"a0", + 2672 => x"8a", + 2673 => x"7c", + 2674 => x"22", + 2675 => x"22", + 2676 => x"33", + 2677 => x"33", + 2678 => x"33", + 2679 => x"33", + 2680 => x"33", + 2681 => x"52", + 2682 => x"51", + 2683 => x"8d", + 2684 => x"80", + 2685 => x"8b", + 2686 => x"30", + 2687 => x"51", + 2688 => x"0b", + 2689 => x"c0", + 2690 => x"0d", + 2691 => x"0d", + 2692 => x"82", + 2693 => x"54", + 2694 => x"94", + 2695 => x"80", + 2696 => x"87", + 2697 => x"51", + 2698 => x"96", + 2699 => x"06", + 2700 => x"70", + 2701 => x"38", + 2702 => x"70", + 2703 => x"51", + 2704 => x"71", + 2705 => x"32", + 2706 => x"51", + 2707 => x"2e", + 2708 => x"93", + 2709 => x"06", + 2710 => x"ff", + 2711 => x"0b", + 2712 => x"33", + 2713 => x"94", + 2714 => x"80", + 2715 => x"87", + 2716 => x"52", + 2717 => x"73", + 2718 => x"0c", + 2719 => x"04", + 2720 => x"02", + 2721 => x"0b", + 2722 => x"c0", + 2723 => x"87", + 2724 => x"51", + 2725 => x"86", + 2726 => x"94", + 2727 => x"08", + 2728 => x"70", + 2729 => x"52", + 2730 => x"2e", + 2731 => x"91", + 2732 => x"06", + 2733 => x"d7", + 2734 => x"2a", + 2735 => x"81", + 2736 => x"70", + 2737 => x"38", + 2738 => x"70", + 2739 => x"51", + 2740 => x"38", + 2741 => x"8b", + 2742 => x"87", + 2743 => x"52", + 2744 => x"86", + 2745 => x"94", + 2746 => x"72", + 2747 => x"0d", + 2748 => x"0d", + 2749 => x"74", + 2750 => x"70", + 2751 => x"f7", + 2752 => x"81", + 2753 => x"0b", + 2754 => x"c0", + 2755 => x"87", + 2756 => x"51", + 2757 => x"86", + 2758 => x"94", + 2759 => x"08", + 2760 => x"70", + 2761 => x"52", + 2762 => x"2e", + 2763 => x"91", + 2764 => x"06", + 2765 => x"d7", + 2766 => x"2a", + 2767 => x"81", + 2768 => x"70", + 2769 => x"38", + 2770 => x"70", + 2771 => x"51", + 2772 => x"38", + 2773 => x"8b", + 2774 => x"87", + 2775 => x"52", + 2776 => x"86", + 2777 => x"94", + 2778 => x"72", + 2779 => x"74", + 2780 => x"70", + 2781 => x"75", + 2782 => x"0c", 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x"9e", + 2842 => x"0c", + 2843 => x"87", + 2844 => x"08", + 2845 => x"98", + 2846 => x"9e", + 2847 => x"0c", + 2848 => x"87", + 2849 => x"08", + 2850 => x"a0", + 2851 => x"9e", + 2852 => x"0c", + 2853 => x"52", + 2854 => x"13", + 2855 => x"87", + 2856 => x"08", + 2857 => x"81", + 2858 => x"34", + 2859 => x"80", + 2860 => x"9e", + 2861 => x"a0", + 2862 => x"52", + 2863 => x"2e", + 2864 => x"53", + 2865 => x"80", + 2866 => x"9e", + 2867 => x"81", + 2868 => x"51", + 2869 => x"80", + 2870 => x"81", + 2871 => x"8b", + 2872 => x"0b", + 2873 => x"88", + 2874 => x"c0", + 2875 => x"52", + 2876 => x"2e", + 2877 => x"52", + 2878 => x"f3", + 2879 => x"87", + 2880 => x"08", + 2881 => x"06", + 2882 => x"70", + 2883 => x"38", + 2884 => x"82", + 2885 => x"80", + 2886 => x"9e", + 2887 => x"88", + 2888 => x"52", + 2889 => x"2e", + 2890 => x"52", + 2891 => x"f5", + 2892 => x"87", + 2893 => x"08", + 2894 => x"06", + 2895 => x"70", + 2896 => x"38", + 2897 => x"82", + 2898 => x"80", + 2899 => x"9e", + 2900 => x"82", + 2901 => x"52", + 2902 => x"2e", + 2903 => x"52", + 2904 => x"f7", + 2905 => x"87", + 2906 => x"08", + 2907 => x"06", + 2908 => x"70", + 2909 => x"38", + 2910 => x"82", + 2911 => x"82", + 2912 => x"87", + 2913 => x"70", + 2914 => x"e0", + 2915 => x"2c", + 2916 => x"53", + 2917 => x"81", + 2918 => x"71", + 2919 => x"08", + 2920 => x"51", + 2921 => x"80", + 2922 => x"81", + 2923 => x"34", + 2924 => x"c0", + 2925 => x"70", + 2926 => x"52", + 2927 => x"2e", + 2928 => x"52", + 2929 => x"fb", + 2930 => x"9e", + 2931 => x"87", + 2932 => x"70", + 2933 => x"34", + 2934 => x"04", + 2935 => x"81", + 2936 => x"84", + 2937 => x"8b", + 2938 => x"73", + 2939 => x"38", + 2940 => x"51", + 2941 => x"81", + 2942 => x"84", + 2943 => x"8b", + 2944 => x"55", + 2945 => x"2e", + 2946 => x"15", + 2947 => x"8b", + 2948 => x"81", + 2949 => x"8a", + 2950 => x"8b", + 2951 => x"55", + 2952 => x"2e", + 2953 => x"15", + 2954 => x"15", + 2955 => x"f7", + 2956 => x"e9", + 2957 => x"f3", + 2958 => x"55", + 2959 => x"81", + 2960 => x"73", + 2961 => x"38", + 2962 => x"70", + 2963 => x"11", + 2964 => x"81", + 2965 => x"89", + 2966 => x"8b", + 2967 => x"73", + 2968 => x"38", + 2969 => x"51", + 2970 => x"82", + 2971 => x"54", + 2972 => x"88", + 2973 => x"fc", + 2974 => x"3f", + 2975 => x"33", + 2976 => x"2e", + 2977 => x"f8", + 2978 => x"97", + 2979 => x"f8", + 2980 => x"55", + 2981 => x"8c", + 2982 => x"33", + 2983 => x"94", + 2984 => x"3f", + 2985 => x"33", + 2986 => x"2e", + 2987 => x"f8", + 2988 => x"ef", + 2989 => x"fb", + 2990 => x"55", + 2991 => x"8c", + 2992 => x"33", + 2993 => x"d0", + 2994 => x"3f", + 2995 => x"51", + 2996 => x"82", + 2997 => x"70", + 2998 => x"52", + 2999 => x"f8", + 3000 => x"55", + 3001 => x"73", + 3002 => x"f9", + 3003 => x"ad", + 3004 => x"08", + 3005 => x"c8", + 3006 => x"3f", + 3007 => x"52", + 3008 => x"51", + 3009 => x"90", + 3010 => x"81", + 3011 => x"88", + 3012 => x"3d", + 3013 => x"3d", + 3014 => x"05", + 3015 => x"85", + 3016 => x"71", + 3017 => x"0b", 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x"d8", + 3077 => x"ff", + 3078 => x"82", + 3079 => x"84", + 3080 => x"fe", + 3081 => x"70", + 3082 => x"71", + 3083 => x"38", + 3084 => x"05", + 3085 => x"ff", + 3086 => x"33", + 3087 => x"38", + 3088 => x"04", + 3089 => x"76", + 3090 => x"08", + 3091 => x"d8", + 3092 => x"54", + 3093 => x"80", + 3094 => x"72", + 3095 => x"54", + 3096 => x"dc", + 3097 => x"52", + 3098 => x"73", + 3099 => x"0c", + 3100 => x"04", + 3101 => x"66", + 3102 => x"78", + 3103 => x"5a", + 3104 => x"80", + 3105 => x"38", + 3106 => x"88", + 3107 => x"fe", + 3108 => x"39", + 3109 => x"70", + 3110 => x"33", + 3111 => x"75", + 3112 => x"81", + 3113 => x"81", + 3114 => x"05", + 3115 => x"5d", + 3116 => x"ad", + 3117 => x"06", + 3118 => x"79", + 3119 => x"5b", + 3120 => x"75", + 3121 => x"81", + 3122 => x"7b", + 3123 => x"08", + 3124 => x"05", + 3125 => x"5c", + 3126 => x"39", + 3127 => x"72", + 3128 => x"38", + 3129 => x"16", + 3130 => x"70", + 3131 => x"33", + 3132 => x"57", + 3133 => x"27", + 3134 => x"80", + 3135 => x"30", + 3136 => x"80", + 3137 => x"cc", + 3138 => x"70", + 3139 => x"25", + 3140 => x"59", + 3141 => x"54", + 3142 => x"8c", + 3143 => x"07", + 3144 => x"05", + 3145 => x"5d", + 3146 => x"83", + 3147 => x"55", + 3148 => x"27", + 3149 => x"16", + 3150 => x"06", + 3151 => x"be", + 3152 => x"96", + 3153 => x"38", + 3154 => x"81", + 3155 => x"53", + 3156 => x"7b", + 3157 => x"08", + 3158 => x"80", + 3159 => x"54", + 3160 => x"8d", + 3161 => x"70", + 3162 => x"51", + 3163 => x"f5", + 3164 => x"2a", + 3165 => x"51", + 3166 => x"38", + 3167 => x"55", + 3168 => x"27", + 3169 => x"81", + 3170 => x"56", + 3171 => x"b0", + 3172 => x"38", + 3173 => x"55", + 3174 => x"26", + 3175 => x"51", + 3176 => x"73", + 3177 => x"53", + 3178 => x"fd", + 3179 => x"51", + 3180 => x"73", + 3181 => x"53", + 3182 => x"f2", + 3183 => x"39", + 3184 => x"83", + 3185 => x"5d", + 3186 => x"3f", + 3187 => x"82", + 3188 => x"88", + 3189 => x"8a", + 3190 => x"90", + 3191 => x"75", + 3192 => x"3f", + 3193 => x"7c", + 3194 => x"81", + 3195 => x"72", + 3196 => x"38", + 3197 => x"71", + 3198 => x"53", + 3199 => x"80", + 3200 => x"81", + 3201 => x"7b", + 3202 => x"08", + 3203 => x"89", + 3204 => x"1d", + 3205 => x"5d", + 3206 => x"c4", + 3207 => x"70", + 3208 => x"25", + 3209 => x"24", + 3210 => x"55", + 3211 => x"2e", + 3212 => x"30", + 3213 => x"5e", + 3214 => x"7a", + 3215 => x"e6", + 3216 => x"93", + 3217 => x"ff", + 3218 => x"77", + 3219 => x"e6", + 3220 => x"c8", + 3221 => x"75", + 3222 => x"74", + 3223 => x"81", + 3224 => x"54", + 3225 => x"f8", + 3226 => x"87", + 3227 => x"ff", + 3228 => x"96", + 3229 => x"e0", + 3230 => x"54", + 3231 => x"34", + 3232 => x"30", + 3233 => x"9f", + 3234 => x"74", + 3235 => x"51", + 3236 => x"ff", + 3237 => x"84", + 3238 => x"06", + 3239 => x"80", + 3240 => x"96", + 3241 => x"e0", + 3242 => x"73", + 3243 => x"58", + 3244 => x"06", + 3245 => x"55", + 3246 => x"a0", + 3247 => x"2a", + 3248 => x"51", + 3249 => x"38", + 3250 => x"55", + 3251 => x"27", + 3252 => x"81", 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x"53", + 3312 => x"8e", + 3313 => x"74", + 3314 => x"52", + 3315 => x"3f", + 3316 => x"74", + 3317 => x"38", + 3318 => x"74", + 3319 => x"b2", + 3320 => x"52", + 3321 => x"81", + 3322 => x"ff", + 3323 => x"f7", + 3324 => x"9e", + 3325 => x"52", + 3326 => x"8a", + 3327 => x"3f", + 3328 => x"82", + 3329 => x"88", + 3330 => x"fe", + 3331 => x"93", + 3332 => x"82", + 3333 => x"77", + 3334 => x"53", + 3335 => x"72", + 3336 => x"0c", + 3337 => x"04", + 3338 => x"7a", + 3339 => x"80", + 3340 => x"75", + 3341 => x"56", + 3342 => x"a0", + 3343 => x"06", + 3344 => x"08", + 3345 => x"0c", + 3346 => x"33", + 3347 => x"a0", + 3348 => x"73", + 3349 => x"81", + 3350 => x"81", + 3351 => x"76", + 3352 => x"70", + 3353 => x"58", + 3354 => x"09", + 3355 => x"d3", + 3356 => x"81", + 3357 => x"74", + 3358 => x"55", + 3359 => x"e2", + 3360 => x"73", + 3361 => x"09", + 3362 => x"38", + 3363 => x"14", + 3364 => x"08", + 3365 => x"54", + 3366 => x"39", + 3367 => x"81", + 3368 => x"75", + 3369 => x"56", + 3370 => x"39", + 3371 => x"74", + 3372 => x"38", + 3373 => x"80", + 3374 => x"89", + 3375 => x"38", + 3376 => x"d0", + 3377 => x"56", + 3378 => x"80", + 3379 => x"39", + 3380 => x"e1", + 3381 => x"80", + 3382 => x"57", + 3383 => x"74", + 3384 => x"38", + 3385 => x"27", + 3386 => x"14", + 3387 => x"06", + 3388 => x"14", + 3389 => x"06", + 3390 => x"74", + 3391 => x"f9", + 3392 => x"ff", + 3393 => x"89", + 3394 => x"38", + 3395 => x"c5", + 3396 => x"29", + 3397 => x"81", + 3398 => x"75", + 3399 => x"56", + 3400 => x"a0", + 3401 => x"38", + 3402 => x"84", + 3403 => x"56", + 3404 => x"81", + 3405 => x"93", + 3406 => x"3d", + 3407 => x"3d", + 3408 => x"5a", + 3409 => x"7a", + 3410 => x"70", + 3411 => x"58", + 3412 => x"09", + 3413 => x"38", + 3414 => x"05", + 3415 => x"08", + 3416 => x"53", + 3417 => x"f0", + 3418 => x"2e", + 3419 => x"8e", + 3420 => x"08", + 3421 => x"75", + 3422 => x"56", + 3423 => x"b0", + 3424 => x"06", + 3425 => x"74", + 3426 => x"75", + 3427 => x"70", + 3428 => x"73", + 3429 => x"9a", + 3430 => x"f8", + 3431 => x"06", + 3432 => x"0b", + 3433 => x"0c", + 3434 => x"33", + 3435 => x"80", + 3436 => x"75", + 3437 => x"76", + 3438 => x"70", + 3439 => x"57", + 3440 => x"56", + 3441 => x"81", + 3442 => x"14", + 3443 => x"88", + 3444 => x"27", + 3445 => x"f3", + 3446 => x"53", + 3447 => x"89", + 3448 => x"38", + 3449 => x"56", + 3450 => x"80", + 3451 => x"39", + 3452 => x"56", + 3453 => x"80", + 3454 => x"e0", + 3455 => x"38", + 3456 => x"81", + 3457 => x"53", + 3458 => x"81", + 3459 => x"53", + 3460 => x"8e", + 3461 => x"70", + 3462 => x"55", + 3463 => x"27", + 3464 => x"77", + 3465 => x"76", + 3466 => x"75", + 3467 => x"76", + 3468 => x"70", + 3469 => x"56", + 3470 => x"ff", + 3471 => x"80", + 3472 => x"75", + 3473 => x"79", + 3474 => x"75", + 3475 => x"0c", + 3476 => x"04", + 3477 => x"02", + 3478 => x"51", + 3479 => x"72", + 3480 => x"82", + 3481 => x"33", + 3482 => x"93", + 3483 => x"3d", + 3484 => x"3d", + 3485 => x"05", + 3486 => x"05", + 3487 => x"55", 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x"a2", + 3547 => x"80", + 3548 => x"75", + 3549 => x"d5", + 3550 => x"52", + 3551 => x"87", + 3552 => x"80", + 3553 => x"81", + 3554 => x"c0", + 3555 => x"53", + 3556 => x"82", + 3557 => x"71", + 3558 => x"1b", + 3559 => x"84", + 3560 => x"1e", + 3561 => x"06", + 3562 => x"7a", + 3563 => x"38", + 3564 => x"80", + 3565 => x"87", + 3566 => x"26", + 3567 => x"73", + 3568 => x"06", + 3569 => x"2e", + 3570 => x"52", + 3571 => x"82", + 3572 => x"90", + 3573 => x"f3", + 3574 => x"62", + 3575 => x"05", + 3576 => x"56", + 3577 => x"83", + 3578 => x"fc", + 3579 => x"93", + 3580 => x"06", + 3581 => x"71", + 3582 => x"80", + 3583 => x"98", + 3584 => x"2b", + 3585 => x"8c", + 3586 => x"92", + 3587 => x"41", + 3588 => x"56", + 3589 => x"87", + 3590 => x"19", + 3591 => x"52", + 3592 => x"80", + 3593 => x"70", + 3594 => x"81", + 3595 => x"54", + 3596 => x"8c", + 3597 => x"81", + 3598 => x"78", + 3599 => x"53", + 3600 => x"70", + 3601 => x"52", + 3602 => x"87", + 3603 => x"52", + 3604 => x"75", + 3605 => x"80", + 3606 => x"72", + 3607 => x"99", + 3608 => x"0c", + 3609 => x"8c", + 3610 => x"08", + 3611 => x"51", + 3612 => x"38", + 3613 => x"8d", + 3614 => x"70", + 3615 => x"84", + 3616 => x"5d", + 3617 => x"2e", + 3618 => x"fc", + 3619 => x"52", + 3620 => x"7d", + 3621 => x"fc", + 3622 => x"80", + 3623 => x"71", + 3624 => x"38", + 3625 => x"54", + 3626 => x"c8", + 3627 => x"0d", + 3628 => x"0d", + 3629 => x"05", + 3630 => x"02", + 3631 => x"05", + 3632 => x"55", + 3633 => x"8c", + 3634 => x"c8", + 3635 => x"52", + 3636 => x"bc", + 3637 => x"72", + 3638 => x"38", + 3639 => x"88", + 3640 => x"2e", + 3641 => x"39", + 3642 => x"9a", + 3643 => x"74", + 3644 => x"c0", + 3645 => x"70", + 3646 => x"94", + 3647 => x"0a", + 3648 => x"54", + 3649 => x"80", + 3650 => x"54", + 3651 => x"54", + 3652 => x"c8", + 3653 => x"0d", + 3654 => x"0d", + 3655 => x"81", + 3656 => x"88", + 3657 => x"82", + 3658 => x"52", + 3659 => x"3d", + 3660 => x"3d", + 3661 => x"11", + 3662 => x"33", + 3663 => x"71", + 3664 => x"81", + 3665 => x"07", + 3666 => x"88", + 3667 => x"93", + 3668 => x"54", + 3669 => x"85", + 3670 => x"ff", + 3671 => x"02", + 3672 => x"05", + 3673 => x"70", + 3674 => x"05", + 3675 => x"88", + 3676 => x"72", + 3677 => x"0d", + 3678 => x"0d", + 3679 => x"52", + 3680 => x"81", + 3681 => x"70", + 3682 => x"70", + 3683 => x"05", + 3684 => x"88", + 3685 => x"72", + 3686 => x"54", + 3687 => x"2a", + 3688 => x"34", + 3689 => x"04", + 3690 => x"76", + 3691 => x"54", + 3692 => x"2e", + 3693 => x"70", + 3694 => x"33", + 3695 => x"05", + 3696 => x"11", + 3697 => x"38", + 3698 => x"04", + 3699 => x"75", + 3700 => x"52", + 3701 => x"70", + 3702 => x"34", + 3703 => x"70", + 3704 => x"3d", + 3705 => x"3d", + 3706 => x"79", + 3707 => x"74", + 3708 => x"56", + 3709 => x"81", + 3710 => x"71", + 3711 => x"16", + 3712 => x"52", + 3713 => x"86", + 3714 => x"2e", + 3715 => x"82", + 3716 => x"86", + 3717 => x"fe", + 3718 => x"76", + 3719 => x"54", + 3720 => x"2e", + 3721 => x"73", + 3722 => x"81", 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x"3f", + 3782 => x"08", + 3783 => x"c8", + 3784 => x"38", + 3785 => x"74", + 3786 => x"81", + 3787 => x"38", + 3788 => x"59", + 3789 => x"09", + 3790 => x"e3", + 3791 => x"53", + 3792 => x"08", + 3793 => x"70", + 3794 => x"80", + 3795 => x"d5", + 3796 => x"17", + 3797 => x"3f", + 3798 => x"a4", + 3799 => x"51", + 3800 => x"86", + 3801 => x"f2", + 3802 => x"17", + 3803 => x"3f", + 3804 => x"52", + 3805 => x"51", + 3806 => x"8c", + 3807 => x"84", + 3808 => x"fb", + 3809 => x"17", + 3810 => x"70", + 3811 => x"79", + 3812 => x"52", + 3813 => x"51", + 3814 => x"77", + 3815 => x"80", + 3816 => x"81", + 3817 => x"fa", + 3818 => x"93", + 3819 => x"2e", + 3820 => x"58", + 3821 => x"c8", + 3822 => x"0d", + 3823 => x"0d", + 3824 => x"98", + 3825 => x"05", + 3826 => x"80", + 3827 => x"27", + 3828 => x"14", + 3829 => x"29", + 3830 => x"05", + 3831 => x"82", + 3832 => x"87", + 3833 => x"f9", + 3834 => x"7a", + 3835 => x"54", + 3836 => x"27", + 3837 => x"14", + 3838 => x"86", + 3839 => x"81", + 3840 => x"74", + 3841 => x"72", + 3842 => x"f5", + 3843 => x"24", + 3844 => x"81", + 3845 => x"81", + 3846 => x"83", + 3847 => x"38", + 3848 => x"74", + 3849 => x"70", + 3850 => x"16", + 3851 => x"74", + 3852 => x"93", + 3853 => x"c8", + 3854 => x"38", + 3855 => x"06", + 3856 => x"33", + 3857 => x"89", + 3858 => x"08", + 3859 => x"54", + 3860 => x"fc", + 3861 => x"93", + 3862 => x"fe", + 3863 => x"ff", + 3864 => x"11", + 3865 => x"2b", + 3866 => x"81", + 3867 => x"2a", + 3868 => x"51", + 3869 => x"e2", + 3870 => x"ff", + 3871 => x"da", + 3872 => x"2a", + 3873 => x"05", + 3874 => x"fc", + 3875 => x"93", + 3876 => x"c6", + 3877 => x"83", + 3878 => x"05", + 3879 => x"f8", + 3880 => x"93", + 3881 => x"ff", + 3882 => x"ae", + 3883 => x"2a", + 3884 => x"05", + 3885 => x"fc", + 3886 => x"93", + 3887 => x"38", + 3888 => x"83", + 3889 => x"05", + 3890 => x"f8", + 3891 => x"93", + 3892 => x"0a", + 3893 => x"39", + 3894 => x"82", + 3895 => x"89", + 3896 => x"f7", + 3897 => x"7d", + 3898 => x"55", + 3899 => x"74", + 3900 => x"38", + 3901 => x"08", + 3902 => x"38", + 3903 => x"72", + 3904 => x"a8", + 3905 => x"24", + 3906 => x"81", + 3907 => x"82", + 3908 => x"83", + 3909 => x"38", + 3910 => x"73", + 3911 => x"70", + 3912 => x"17", + 3913 => x"75", + 3914 => x"9b", + 3915 => x"c8", + 3916 => x"93", + 3917 => x"ea", + 3918 => x"ff", + 3919 => x"11", + 3920 => x"81", + 3921 => x"51", + 3922 => x"72", + 3923 => x"38", + 3924 => x"9f", + 3925 => x"33", + 3926 => x"07", + 3927 => x"78", + 3928 => x"83", + 3929 => x"89", + 3930 => x"08", + 3931 => x"51", + 3932 => x"82", + 3933 => x"57", + 3934 => x"08", + 3935 => x"78", + 3936 => x"15", + 3937 => x"81", + 3938 => x"2a", + 3939 => x"58", + 3940 => x"75", + 3941 => x"33", + 3942 => x"76", + 3943 => x"07", + 3944 => x"34", + 3945 => x"16", + 3946 => x"39", + 3947 => x"a4", + 3948 => x"52", + 3949 => x"8f", + 3950 => x"c8", + 3951 => x"93", + 3952 => x"de", + 3953 => x"ff", + 3954 => x"73", + 3955 => x"06", + 3956 => x"05", + 3957 => x"3f", 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x"07", + 4017 => x"16", + 4018 => x"98", + 4019 => x"26", + 4020 => x"80", + 4021 => x"93", + 4022 => x"3d", + 4023 => x"3d", + 4024 => x"71", + 4025 => x"5c", + 4026 => x"8c", + 4027 => x"77", + 4028 => x"38", + 4029 => x"78", + 4030 => x"81", + 4031 => x"7a", + 4032 => x"f9", + 4033 => x"55", + 4034 => x"c8", + 4035 => x"e9", + 4036 => x"c8", + 4037 => x"93", + 4038 => x"2e", + 4039 => x"82", + 4040 => x"55", + 4041 => x"82", + 4042 => x"26", + 4043 => x"7a", + 4044 => x"90", + 4045 => x"2e", + 4046 => x"80", + 4047 => x"2e", + 4048 => x"80", + 4049 => x"1b", + 4050 => x"08", + 4051 => x"38", + 4052 => x"52", + 4053 => x"8f", + 4054 => x"c8", + 4055 => x"5a", + 4056 => x"08", + 4057 => x"81", + 4058 => x"82", + 4059 => x"5a", + 4060 => x"70", + 4061 => x"07", + 4062 => x"7d", + 4063 => x"51", + 4064 => x"73", + 4065 => x"75", + 4066 => x"38", + 4067 => x"56", + 4068 => x"8a", + 4069 => x"1a", + 4070 => x"38", + 4071 => x"57", + 4072 => x"38", + 4073 => x"17", + 4074 => x"08", + 4075 => x"38", + 4076 => x"78", + 4077 => x"38", + 4078 => x"51", + 4079 => x"82", + 4080 => x"56", + 4081 => x"08", + 4082 => x"38", + 4083 => x"93", + 4084 => x"2e", + 4085 => x"86", + 4086 => x"c8", + 4087 => x"ff", + 4088 => x"70", + 4089 => x"25", + 4090 => x"51", + 4091 => x"73", + 4092 => x"76", + 4093 => x"81", + 4094 => x"38", + 4095 => x"f9", + 4096 => x"76", + 4097 => x"f9", + 4098 => x"93", + 4099 => x"93", + 4100 => x"70", + 4101 => x"08", + 4102 => x"7d", + 4103 => x"07", + 4104 => x"06", + 4105 => x"56", + 4106 => x"2e", + 4107 => x"53", + 4108 => x"51", + 4109 => x"82", + 4110 => x"56", + 4111 => x"76", + 4112 => x"98", + 4113 => x"05", + 4114 => x"08", + 4115 => x"38", + 4116 => x"ff", + 4117 => x"0c", + 4118 => x"81", + 4119 => x"84", + 4120 => x"39", + 4121 => x"81", + 4122 => x"89", + 4123 => x"89", + 4124 => x"85", + 4125 => x"76", + 4126 => x"93", + 4127 => x"3d", + 4128 => x"3d", + 4129 => x"52", + 4130 => x"3f", + 4131 => x"93", + 4132 => x"db", + 4133 => x"76", + 4134 => x"3f", + 4135 => x"08", + 4136 => x"08", + 4137 => x"5a", + 4138 => x"80", + 4139 => x"70", + 4140 => x"98", + 4141 => x"81", + 4142 => x"84", + 4143 => x"56", + 4144 => x"55", + 4145 => x"97", + 4146 => x"75", + 4147 => x"52", + 4148 => x"51", + 4149 => x"82", + 4150 => x"80", + 4151 => x"80", + 4152 => x"22", + 4153 => x"76", + 4154 => x"81", + 4155 => x"74", + 4156 => x"0c", + 4157 => x"04", + 4158 => x"7a", + 4159 => x"58", + 4160 => x"f0", + 4161 => x"8a", + 4162 => x"06", + 4163 => x"2e", + 4164 => x"58", + 4165 => x"74", + 4166 => x"88", + 4167 => x"73", + 4168 => x"33", + 4169 => x"27", + 4170 => x"16", + 4171 => x"9b", + 4172 => x"2a", + 4173 => x"88", + 4174 => x"58", + 4175 => x"81", + 4176 => x"16", + 4177 => x"0c", + 4178 => x"8a", + 4179 => x"89", + 4180 => x"72", + 4181 => x"38", + 4182 => x"51", + 4183 => x"82", + 4184 => x"54", + 4185 => x"08", + 4186 => x"38", + 4187 => x"93", + 4188 => x"8b", + 4189 => x"08", + 4190 => x"08", + 4191 => x"82", + 4192 => x"39", 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x"74", + 4252 => x"3f", + 4253 => x"08", + 4254 => x"82", + 4255 => x"80", + 4256 => x"38", + 4257 => x"93", + 4258 => x"2e", + 4259 => x"53", + 4260 => x"08", + 4261 => x"38", + 4262 => x"08", + 4263 => x"fb", + 4264 => x"53", + 4265 => x"08", + 4266 => x"94", + 4267 => x"52", + 4268 => x"89", + 4269 => x"c8", + 4270 => x"0c", + 4271 => x"0c", + 4272 => x"06", + 4273 => x"9c", + 4274 => x"53", + 4275 => x"c8", + 4276 => x"0d", + 4277 => x"0d", + 4278 => x"08", + 4279 => x"80", + 4280 => x"fc", + 4281 => x"93", + 4282 => x"82", + 4283 => x"80", + 4284 => x"93", + 4285 => x"98", + 4286 => x"77", + 4287 => x"3f", + 4288 => x"08", + 4289 => x"c8", + 4290 => x"38", + 4291 => x"08", + 4292 => x"70", + 4293 => x"55", + 4294 => x"2e", + 4295 => x"83", + 4296 => x"72", + 4297 => x"25", + 4298 => x"53", + 4299 => x"8b", + 4300 => x"57", + 4301 => x"9a", + 4302 => x"80", + 4303 => x"75", + 4304 => x"3f", + 4305 => x"08", + 4306 => x"c8", + 4307 => x"ff", + 4308 => x"84", + 4309 => x"06", + 4310 => x"54", + 4311 => x"c8", + 4312 => x"0d", + 4313 => x"0d", + 4314 => x"52", + 4315 => x"3f", + 4316 => x"08", + 4317 => x"06", + 4318 => x"51", + 4319 => x"83", + 4320 => x"06", + 4321 => x"14", + 4322 => x"3f", + 4323 => x"08", + 4324 => x"07", + 4325 => x"93", + 4326 => x"3d", + 4327 => x"3d", + 4328 => x"70", + 4329 => x"06", + 4330 => x"53", + 4331 => x"ab", + 4332 => x"33", + 4333 => x"83", + 4334 => x"06", + 4335 => x"90", + 4336 => x"15", + 4337 => x"3f", + 4338 => x"04", + 4339 => x"7b", + 4340 => x"84", + 4341 => x"58", + 4342 => x"80", + 4343 => x"38", + 4344 => x"52", + 4345 => x"df", + 4346 => x"c8", + 4347 => x"93", + 4348 => x"f1", + 4349 => x"08", + 4350 => x"53", + 4351 => x"84", + 4352 => x"39", + 4353 => x"8b", + 4354 => x"bf", + 4355 => x"ff", + 4356 => x"51", + 4357 => x"17", + 4358 => x"e5", + 4359 => x"76", + 4360 => x"30", + 4361 => x"9f", + 4362 => x"55", + 4363 => x"80", + 4364 => x"76", + 4365 => x"38", + 4366 => x"06", + 4367 => x"88", + 4368 => x"06", + 4369 => x"54", + 4370 => x"99", + 4371 => x"75", + 4372 => x"3f", + 4373 => x"08", + 4374 => x"c8", + 4375 => x"98", + 4376 => x"fc", + 4377 => x"2e", + 4378 => x"0b", + 4379 => x"77", + 4380 => x"0c", + 4381 => x"04", + 4382 => x"7a", + 4383 => x"56", + 4384 => x"51", + 4385 => x"82", + 4386 => x"54", + 4387 => x"08", + 4388 => x"86", + 4389 => x"80", + 4390 => x"16", + 4391 => x"51", + 4392 => x"82", + 4393 => x"57", + 4394 => x"08", + 4395 => x"9c", + 4396 => x"33", + 4397 => x"80", + 4398 => x"9c", + 4399 => x"11", + 4400 => x"55", + 4401 => x"17", + 4402 => x"33", + 4403 => x"70", + 4404 => x"55", + 4405 => x"38", + 4406 => x"16", + 4407 => x"ea", + 4408 => x"93", + 4409 => x"2e", + 4410 => x"52", + 4411 => x"dd", + 4412 => x"c8", + 4413 => x"93", + 4414 => x"2e", + 4415 => x"76", + 4416 => x"93", + 4417 => x"3d", + 4418 => x"3d", + 4419 => x"08", + 4420 => x"52", + 4421 => x"bd", + 4422 => x"c8", + 4423 => x"93", + 4424 => x"38", + 4425 => x"52", + 4426 => x"9b", + 4427 => x"c8", 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x"17", + 4487 => x"08", + 4488 => x"e5", + 4489 => x"93", + 4490 => x"17", + 4491 => x"0d", + 4492 => x"0d", + 4493 => x"7f", + 4494 => x"5a", + 4495 => x"a0", + 4496 => x"e7", + 4497 => x"70", + 4498 => x"79", + 4499 => x"73", + 4500 => x"81", + 4501 => x"38", + 4502 => x"33", + 4503 => x"ae", + 4504 => x"70", + 4505 => x"82", + 4506 => x"51", + 4507 => x"54", + 4508 => x"7a", + 4509 => x"74", + 4510 => x"58", + 4511 => x"af", + 4512 => x"77", + 4513 => x"70", + 4514 => x"06", + 4515 => x"51", + 4516 => x"74", + 4517 => x"38", + 4518 => x"a0", + 4519 => x"38", + 4520 => x"0c", + 4521 => x"76", + 4522 => x"a0", + 4523 => x"1c", + 4524 => x"82", + 4525 => x"17", + 4526 => x"19", + 4527 => x"a0", + 4528 => x"8c", + 4529 => x"32", + 4530 => x"80", + 4531 => x"30", + 4532 => x"71", + 4533 => x"53", + 4534 => x"55", + 4535 => x"b5", + 4536 => x"81", + 4537 => x"77", + 4538 => x"51", + 4539 => x"af", + 4540 => x"06", + 4541 => x"5a", + 4542 => x"70", + 4543 => x"55", + 4544 => x"2e", + 4545 => x"83", + 4546 => x"79", + 4547 => x"73", + 4548 => x"bc", + 4549 => x"32", + 4550 => x"80", + 4551 => x"27", + 4552 => x"54", + 4553 => x"a2", + 4554 => x"32", + 4555 => x"ae", + 4556 => x"72", + 4557 => x"9f", + 4558 => x"51", + 4559 => x"74", + 4560 => x"88", + 4561 => x"fe", + 4562 => x"98", + 4563 => x"80", + 4564 => x"75", + 4565 => x"81", + 4566 => x"33", + 4567 => x"51", + 4568 => x"82", + 4569 => x"80", + 4570 => x"78", + 4571 => x"81", + 4572 => x"59", + 4573 => x"d7", + 4574 => x"c8", + 4575 => x"89", + 4576 => x"54", + 4577 => x"86", + 4578 => x"80", + 4579 => x"18", + 4580 => x"34", + 4581 => x"11", + 4582 => x"74", + 4583 => x"58", + 4584 => x"75", + 4585 => x"f0", + 4586 => x"3f", + 4587 => x"08", + 4588 => x"ff", + 4589 => x"73", + 4590 => x"38", + 4591 => x"81", + 4592 => x"54", + 4593 => x"75", + 4594 => x"18", + 4595 => x"39", + 4596 => x"0c", + 4597 => x"80", + 4598 => x"7a", + 4599 => x"81", + 4600 => x"81", + 4601 => x"85", + 4602 => x"54", + 4603 => x"8d", + 4604 => x"86", + 4605 => x"86", + 4606 => x"80", + 4607 => x"1c", + 4608 => x"73", + 4609 => x"0c", + 4610 => x"04", + 4611 => x"78", + 4612 => x"56", + 4613 => x"33", + 4614 => x"72", + 4615 => x"38", + 4616 => x"7a", + 4617 => x"54", + 4618 => x"dc", + 4619 => x"81", + 4620 => x"06", + 4621 => x"2e", + 4622 => x"17", + 4623 => x"0c", + 4624 => x"1a", + 4625 => x"70", + 4626 => x"55", + 4627 => x"09", + 4628 => x"38", + 4629 => x"7a", + 4630 => x"54", + 4631 => x"dc", + 4632 => x"06", + 4633 => x"54", + 4634 => x"53", + 4635 => x"80", + 4636 => x"0c", + 4637 => x"51", + 4638 => x"26", + 4639 => x"80", + 4640 => x"34", + 4641 => x"51", + 4642 => x"82", + 4643 => x"55", + 4644 => x"85", + 4645 => x"39", + 4646 => x"05", + 4647 => x"fb", + 4648 => x"93", + 4649 => x"82", + 4650 => x"81", + 4651 => x"51", + 4652 => x"82", + 4653 => x"ab", + 4654 => x"55", + 4655 => x"08", + 4656 => x"c2", + 4657 => x"c8", + 4658 => x"09", + 4659 => x"ec", + 4660 => x"2a", + 4661 => x"51", + 4662 => x"2e", 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x"51", + 4722 => x"51", + 4723 => x"89", + 4724 => x"70", + 4725 => x"54", + 4726 => x"74", + 4727 => x"30", + 4728 => x"80", + 4729 => x"2a", + 4730 => x"53", + 4731 => x"b9", + 4732 => x"75", + 4733 => x"30", + 4734 => x"9f", + 4735 => x"2a", + 4736 => x"53", + 4737 => x"2e", + 4738 => x"18", + 4739 => x"25", + 4740 => x"8b", + 4741 => x"24", + 4742 => x"77", + 4743 => x"79", + 4744 => x"82", + 4745 => x"51", + 4746 => x"c8", + 4747 => x"0d", + 4748 => x"0d", + 4749 => x"0b", + 4750 => x"ff", + 4751 => x"0c", + 4752 => x"51", + 4753 => x"84", + 4754 => x"c8", + 4755 => x"38", + 4756 => x"51", + 4757 => x"82", + 4758 => x"83", + 4759 => x"54", + 4760 => x"82", + 4761 => x"09", + 4762 => x"e7", + 4763 => x"b4", + 4764 => x"55", + 4765 => x"2e", + 4766 => x"83", + 4767 => x"73", + 4768 => x"70", + 4769 => x"25", + 4770 => x"51", + 4771 => x"38", + 4772 => x"54", + 4773 => x"2e", + 4774 => x"b5", + 4775 => x"81", + 4776 => x"80", + 4777 => x"de", + 4778 => x"93", + 4779 => x"82", + 4780 => x"80", + 4781 => x"85", + 4782 => x"84", + 4783 => x"16", + 4784 => x"3f", + 4785 => x"08", + 4786 => x"c8", + 4787 => x"83", + 4788 => x"74", + 4789 => x"0c", + 4790 => x"04", + 4791 => x"60", + 4792 => x"80", + 4793 => x"58", + 4794 => x"0c", + 4795 => x"d5", + 4796 => x"c8", + 4797 => x"56", + 4798 => x"93", + 4799 => x"87", + 4800 => x"93", + 4801 => x"10", + 4802 => x"05", + 4803 => x"53", + 4804 => x"80", + 4805 => x"38", + 4806 => x"76", + 4807 => x"75", + 4808 => x"72", + 4809 => x"38", + 4810 => x"51", + 4811 => x"82", + 4812 => x"81", + 4813 => x"81", + 4814 => x"72", + 4815 => x"80", + 4816 => x"73", + 4817 => x"81", + 4818 => x"8a", + 4819 => x"cf", + 4820 => x"86", + 4821 => x"75", + 4822 => x"16", + 4823 => x"81", + 4824 => x"d6", + 4825 => x"93", + 4826 => x"ff", + 4827 => x"06", + 4828 => x"56", + 4829 => x"38", + 4830 => x"8f", + 4831 => x"2a", + 4832 => x"51", + 4833 => x"72", + 4834 => x"80", + 4835 => x"52", + 4836 => x"3f", + 4837 => x"08", + 4838 => x"57", + 4839 => x"09", + 4840 => x"e4", + 4841 => x"73", + 4842 => x"90", + 4843 => x"10", + 4844 => x"83", + 4845 => x"55", + 4846 => x"57", + 4847 => x"8d", + 4848 => x"16", + 4849 => x"3f", + 4850 => x"08", + 4851 => x"0c", + 4852 => x"83", + 4853 => x"38", + 4854 => x"3d", + 4855 => x"05", + 4856 => x"5b", + 4857 => x"79", + 4858 => x"38", + 4859 => x"51", + 4860 => x"82", + 4861 => x"81", + 4862 => x"81", + 4863 => x"38", + 4864 => x"83", + 4865 => x"38", + 4866 => x"84", + 4867 => x"38", + 4868 => x"81", + 4869 => x"38", + 4870 => x"d9", + 4871 => x"93", + 4872 => x"ff", + 4873 => x"8d", + 4874 => x"80", + 4875 => x"06", + 4876 => x"80", + 4877 => x"d9", + 4878 => x"93", + 4879 => x"ff", + 4880 => x"73", + 4881 => x"d8", + 4882 => x"e6", + 4883 => x"c8", + 4884 => x"9c", + 4885 => x"c4", + 4886 => x"16", + 4887 => x"15", + 4888 => x"53", + 4889 => x"81", + 4890 => x"38", + 4891 => x"74", + 4892 => x"c1", + 4893 => x"55", + 4894 => x"16", + 4895 => x"ff", + 4896 => x"72", + 4897 => x"38", + 4898 => x"06", + 4899 => x"2e", + 4900 => x"56", + 4901 => x"80", + 4902 => x"d8", + 4903 => x"93", + 4904 => x"16", + 4905 => x"c8", + 4906 => x"ff", + 4907 => x"53", + 4908 => x"83", + 4909 => x"c7", + 4910 => x"dd", + 4911 => x"c8", + 4912 => x"ff", + 4913 => x"8d", + 4914 => x"15", + 4915 => x"3f", + 4916 => x"08", + 4917 => x"15", + 4918 => x"3f", + 4919 => x"08", + 4920 => x"06", + 4921 => x"78", + 4922 => x"b3", + 4923 => x"22", + 4924 => x"84", + 4925 => x"56", + 4926 => x"73", + 4927 => x"38", + 4928 => x"52", + 4929 => x"51", + 4930 => x"3f", + 4931 => x"08", + 4932 => x"82", + 4933 => x"80", + 4934 => x"38", + 4935 => x"93", + 4936 => x"ff", + 4937 => x"26", + 4938 => x"57", + 4939 => x"f5", + 4940 => x"82", + 4941 => x"f5", + 4942 => x"81", + 4943 => x"76", + 4944 => x"db", + 4945 => x"98", + 4946 => x"a0", + 4947 => x"19", + 4948 => x"77", + 4949 => x"0c", + 4950 => x"09", + 4951 => x"38", + 4952 => x"51", + 4953 => x"82", + 4954 => x"83", + 4955 => x"53", + 4956 => x"82", + 4957 => x"15", + 4958 => x"56", + 4959 => x"38", + 4960 => x"51", + 4961 => x"82", + 4962 => x"a8", + 4963 => x"15", + 4964 => x"53", + 4965 => x"15", + 4966 => x"56", + 4967 => x"81", + 4968 => x"15", + 4969 => x"16", + 4970 => x"2e", + 4971 => x"88", + 4972 => x"08", + 4973 => x"39", + 4974 => x"10", + 4975 => x"05", + 4976 => x"98", + 4977 => x"06", + 4978 => x"83", + 4979 => x"2a", + 4980 => x"72", + 4981 => x"26", + 4982 => x"ff", + 4983 => x"0c", + 4984 => x"16", + 4985 => x"0b", + 4986 => x"76", + 4987 => x"81", + 4988 => x"38", + 4989 => x"51", + 4990 => x"82", + 4991 => x"83", + 4992 => x"53", + 4993 => x"09", + 4994 => x"f9", + 4995 => x"52", + 4996 => x"b3", + 4997 => x"c8", + 4998 => x"38", + 4999 => x"08", + 5000 => x"84", + 5001 => x"d5", + 5002 => x"93", + 5003 => x"ff", + 5004 => x"72", + 5005 => x"2e", + 5006 => x"80", + 5007 => x"15", + 5008 => x"3f", + 5009 => x"08", + 5010 => x"a4", + 5011 => x"81", + 5012 => x"84", + 5013 => x"d5", + 5014 => x"93", + 5015 => x"8a", + 5016 => x"2e", + 5017 => x"9d", + 5018 => x"15", + 5019 => x"3f", + 5020 => x"08", + 5021 => x"84", + 5022 => x"d5", + 5023 => x"93", + 5024 => x"16", + 5025 => x"34", + 5026 => x"22", + 5027 => x"72", + 5028 => x"23", + 5029 => x"23", + 5030 => x"16", + 5031 => x"75", + 5032 => x"0c", + 5033 => x"04", + 5034 => x"77", + 5035 => x"73", + 5036 => x"38", + 5037 => x"2e", + 5038 => x"08", + 5039 => x"53", + 5040 => x"a4", + 5041 => x"22", + 5042 => x"57", + 5043 => x"2e", + 5044 => x"94", + 5045 => x"33", + 5046 => x"3f", + 5047 => x"08", + 5048 => x"71", + 5049 => x"55", + 5050 => x"73", + 5051 => x"06", + 5052 => x"08", + 5053 => x"71", + 5054 => x"82", + 5055 => x"87", + 5056 => x"fa", + 5057 => x"ab", + 5058 => x"58", + 5059 => x"05", + 5060 => x"b1", + 5061 => x"c8", + 5062 => x"54", + 5063 => x"93", + 5064 => x"80", + 5065 => x"93", + 5066 => x"10", + 5067 => x"05", + 5068 => x"54", + 5069 => x"84", + 5070 => x"34", + 5071 => x"86", + 5072 => x"80", + 5073 => x"10", + 5074 => x"e4", + 5075 => x"0c", + 5076 => x"75", + 5077 => x"38", + 5078 => x"3d", + 5079 => x"05", + 5080 => x"3f", + 5081 => x"08", + 5082 => x"93", + 5083 => x"3d", + 5084 => x"3d", + 5085 => x"84", + 5086 => x"05", + 5087 => x"89", + 5088 => x"2e", + 5089 => x"76", + 5090 => x"54", + 5091 => x"05", + 5092 => x"84", + 5093 => x"f6", + 5094 => x"93", + 5095 => x"82", + 5096 => x"84", + 5097 => x"5c", + 5098 => x"3d", + 5099 => x"f0", + 5100 => x"93", + 5101 => x"82", + 5102 => x"92", + 5103 => x"d7", + 5104 => x"98", + 5105 => x"74", + 5106 => x"38", + 5107 => x"9c", + 5108 => x"80", + 5109 => x"38", + 5110 => x"9c", + 5111 => x"2e", + 5112 => x"8e", + 5113 => x"d4", + 5114 => x"9e", + 5115 => x"c8", + 5116 => x"88", + 5117 => x"39", + 5118 => x"33", + 5119 => x"74", + 5120 => x"38", + 5121 => x"39", + 5122 => x"70", + 5123 => x"55", + 5124 => x"83", + 5125 => x"75", + 5126 => x"76", + 5127 => x"81", + 5128 => x"74", + 5129 => x"a7", + 5130 => x"7a", + 5131 => x"3f", + 5132 => x"08", + 5133 => x"b2", + 5134 => x"8e", + 5135 => x"b9", + 5136 => x"a0", + 5137 => x"34", + 5138 => x"52", + 5139 => x"ce", + 5140 => x"62", + 5141 => x"d2", + 5142 => x"55", + 5143 => x"16", + 5144 => x"2e", + 5145 => x"7a", + 5146 => x"77", + 5147 => x"99", + 5148 => x"53", + 5149 => x"b3", + 5150 => x"c8", + 5151 => x"93", + 5152 => x"e6", + 5153 => x"7a", + 5154 => x"3f", + 5155 => x"08", + 5156 => x"8c", + 5157 => x"56", + 5158 => x"82", + 5159 => x"b2", + 5160 => x"84", + 5161 => x"06", + 5162 => x"74", + 5163 => x"38", + 5164 => x"39", + 5165 => x"70", + 5166 => x"55", + 5167 => x"8f", + 5168 => x"05", + 5169 => x"55", + 5170 => x"83", + 5171 => x"75", + 5172 => x"76", + 5173 => x"81", + 5174 => x"74", + 5175 => x"38", + 5176 => x"07", + 5177 => x"11", + 5178 => x"0c", + 5179 => x"0c", + 5180 => x"f6", + 5181 => x"74", + 5182 => x"3f", + 5183 => x"08", + 5184 => x"62", + 5185 => x"d0", + 5186 => x"93", + 5187 => x"19", + 5188 => x"0c", + 5189 => x"84", + 5190 => x"90", + 5191 => x"91", + 5192 => x"9c", + 5193 => x"94", + 5194 => x"80", + 5195 => x"a8", + 5196 => x"98", + 5197 => x"2a", + 5198 => x"51", + 5199 => x"2e", + 5200 => x"8c", + 5201 => x"2e", + 5202 => x"8c", + 5203 => x"19", + 5204 => x"11", + 5205 => x"2b", + 5206 => x"8c", + 5207 => x"5a", + 5208 => x"a5", + 5209 => x"77", + 5210 => x"3f", + 5211 => x"08", + 5212 => x"c8", + 5213 => x"83", + 5214 => x"76", + 5215 => x"81", + 5216 => x"81", + 5217 => x"31", + 5218 => x"70", + 5219 => x"25", + 5220 => x"26", + 5221 => x"55", + 5222 => x"76", + 5223 => x"75", + 5224 => x"78", + 5225 => x"55", + 5226 => x"b9", + 5227 => x"7a", + 5228 => x"3f", + 5229 => x"08", + 5230 => x"56", + 5231 => x"89", + 5232 => x"c8", + 5233 => x"9c", + 5234 => x"81", + 5235 => x"a8", + 5236 => x"81", + 5237 => x"55", + 5238 => x"82", + 5239 => x"80", + 5240 => x"81", + 5241 => x"2e", + 5242 => x"78", + 5243 => x"74", + 5244 => x"0c", + 5245 => x"04", + 5246 => x"7f", + 5247 => x"5f", + 5248 => x"80", + 5249 => x"3d", + 5250 => x"76", + 5251 => x"3f", + 5252 => x"08", + 5253 => x"c8", + 5254 => x"91", + 5255 => x"74", + 5256 => x"38", + 5257 => x"ae", + 5258 => x"33", + 5259 => x"87", + 5260 => x"2e", + 5261 => x"bd", + 5262 => x"91", + 5263 => x"56", + 5264 => x"81", + 5265 => x"34", + 5266 => x"8a", + 5267 => x"91", + 5268 => x"56", + 5269 => x"81", + 5270 => x"34", + 5271 => x"f6", + 5272 => x"91", + 5273 => x"56", + 5274 => x"81", + 5275 => x"34", + 5276 => x"e2", + 5277 => x"08", + 5278 => x"31", + 5279 => x"27", + 5280 => x"59", + 5281 => x"82", + 5282 => x"17", + 5283 => x"ff", + 5284 => x"74", + 5285 => x"7d", + 5286 => x"ff", + 5287 => x"2a", + 5288 => x"7a", + 5289 => x"87", + 5290 => x"08", + 5291 => x"98", + 5292 => x"76", + 5293 => x"3f", + 5294 => x"08", + 5295 => x"27", + 5296 => x"74", + 5297 => x"fb", + 5298 => x"18", + 5299 => x"08", + 5300 => x"d1", + 5301 => x"93", + 5302 => x"2e", + 5303 => x"82", + 5304 => x"1b", + 5305 => x"5b", + 5306 => x"2e", + 5307 => x"79", + 5308 => x"11", + 5309 => x"56", + 5310 => x"85", + 5311 => x"31", + 5312 => x"77", + 5313 => x"7d", + 5314 => x"52", + 5315 => x"3f", + 5316 => x"08", + 5317 => x"90", + 5318 => x"98", + 5319 => x"74", + 5320 => x"38", + 5321 => x"78", + 5322 => x"7a", + 5323 => x"84", + 5324 => x"17", + 5325 => x"80", + 5326 => x"cc", + 5327 => x"89", + 5328 => x"f9", + 5329 => x"08", + 5330 => x"c9", + 5331 => x"33", + 5332 => x"56", + 5333 => x"25", + 5334 => x"54", + 5335 => x"53", + 5336 => x"7d", + 5337 => x"52", + 5338 => x"3f", + 5339 => x"08", + 5340 => x"90", + 5341 => x"ff", + 5342 => x"90", + 5343 => x"54", + 5344 => x"17", + 5345 => x"11", + 5346 => x"c6", + 5347 => x"93", + 5348 => x"d7", + 5349 => x"18", + 5350 => x"08", + 5351 => x"84", + 5352 => x"57", + 5353 => x"27", + 5354 => x"56", + 5355 => x"17", + 5356 => x"06", + 5357 => x"52", + 5358 => x"ec", + 5359 => x"31", + 5360 => x"7e", + 5361 => x"94", + 5362 => x"94", + 5363 => x"59", + 5364 => x"38", + 5365 => x"82", + 5366 => x"8f", + 5367 => x"f3", + 5368 => x"62", + 5369 => x"5f", + 5370 => x"7d", + 5371 => x"fc", + 5372 => x"51", + 5373 => x"82", + 5374 => x"55", + 5375 => x"08", + 5376 => x"17", + 5377 => x"80", + 5378 => x"74", + 5379 => x"39", + 5380 => x"70", + 5381 => x"81", + 5382 => x"56", + 5383 => x"80", + 5384 => x"38", + 5385 => x"0b", + 5386 => x"82", + 5387 => x"39", + 5388 => x"18", + 5389 => x"83", + 5390 => x"0b", + 5391 => x"81", + 5392 => x"39", + 5393 => x"18", + 5394 => x"83", + 5395 => x"0b", + 5396 => x"81", + 5397 => x"39", + 5398 => x"18", + 5399 => x"83", + 5400 => x"17", + 5401 => x"74", + 5402 => x"27", + 5403 => x"17", + 5404 => x"78", + 5405 => x"8c", + 5406 => x"08", + 5407 => x"06", + 5408 => x"82", + 5409 => x"8a", + 5410 => x"05", + 5411 => x"06", + 5412 => x"80", + 5413 => x"96", + 5414 => x"08", + 5415 => x"38", + 5416 => x"51", + 5417 => x"82", + 5418 => x"55", + 5419 => x"17", + 5420 => x"51", + 5421 => x"82", + 5422 => x"55", + 5423 => x"82", + 5424 => x"81", + 5425 => x"38", + 5426 => x"fe", + 5427 => x"98", + 5428 => x"17", + 5429 => x"74", + 5430 => x"90", + 5431 => x"98", + 5432 => x"74", + 5433 => x"38", + 5434 => x"17", + 5435 => x"17", + 5436 => x"11", + 5437 => x"c5", + 5438 => x"93", + 5439 => x"ba", + 5440 => x"33", + 5441 => x"55", + 5442 => x"34", + 5443 => x"52", + 5444 => x"a9", + 5445 => x"c8", + 5446 => x"fe", + 5447 => x"93", + 5448 => x"79", + 5449 => x"58", + 5450 => x"80", + 5451 => x"1b", + 5452 => x"22", + 5453 => x"74", + 5454 => x"38", + 5455 => x"5a", + 5456 => x"53", + 5457 => x"81", + 5458 => x"55", + 5459 => x"82", + 5460 => x"fd", + 5461 => x"17", + 5462 => x"55", + 5463 => x"9b", + 5464 => x"53", + 5465 => x"29", + 5466 => x"17", + 5467 => x"3f", + 5468 => x"80", + 5469 => x"74", + 5470 => x"79", + 5471 => x"80", + 5472 => x"17", + 5473 => x"a1", + 5474 => x"08", + 5475 => x"27", + 5476 => x"54", + 5477 => x"17", + 5478 => x"11", + 5479 => x"c2", + 5480 => x"93", + 5481 => x"b0", + 5482 => x"18", + 5483 => x"08", + 5484 => x"84", + 5485 => x"57", + 5486 => x"27", + 5487 => x"56", + 5488 => x"52", + 5489 => x"83", + 5490 => x"a8", + 5491 => x"d8", + 5492 => x"33", + 5493 => x"55", + 5494 => x"34", + 5495 => x"7d", + 5496 => x"0c", + 5497 => x"19", + 5498 => x"94", + 5499 => x"1a", + 5500 => x"5d", + 5501 => x"27", + 5502 => x"55", + 5503 => x"0c", + 5504 => x"38", + 5505 => x"80", + 5506 => x"74", + 5507 => x"80", + 5508 => x"93", + 5509 => x"3d", + 5510 => x"3d", + 5511 => x"3d", + 5512 => x"70", + 5513 => x"80", + 5514 => x"c8", + 5515 => x"93", + 5516 => x"aa", + 5517 => x"33", + 5518 => x"70", + 5519 => x"56", + 5520 => x"2e", + 5521 => x"75", + 5522 => x"74", + 5523 => x"38", + 5524 => x"18", + 5525 => x"18", + 5526 => x"11", + 5527 => x"c2", + 5528 => x"55", + 5529 => x"08", + 5530 => x"90", + 5531 => x"ff", + 5532 => x"90", + 5533 => x"18", + 5534 => x"51", + 5535 => x"82", + 5536 => x"57", + 5537 => x"08", + 5538 => x"a4", + 5539 => x"11", + 5540 => x"56", + 5541 => x"17", + 5542 => x"08", + 5543 => x"77", + 5544 => x"fa", + 5545 => x"08", + 5546 => x"51", + 5547 => x"82", + 5548 => x"52", + 5549 => x"c5", + 5550 => x"52", + 5551 => x"c5", + 5552 => x"55", + 5553 => x"16", + 5554 => x"c8", + 5555 => x"93", + 5556 => x"19", + 5557 => x"06", + 5558 => x"90", + 5559 => x"55", + 5560 => x"c8", + 5561 => x"0d", + 5562 => x"0d", + 5563 => x"54", + 5564 => x"82", + 5565 => x"53", + 5566 => x"08", + 5567 => x"3d", + 5568 => x"73", + 5569 => x"3f", + 5570 => x"08", + 5571 => x"c8", + 5572 => x"82", + 5573 => x"74", + 5574 => x"93", + 5575 => x"3d", + 5576 => x"3d", + 5577 => x"51", + 5578 => x"8b", + 5579 => x"82", + 5580 => x"24", + 5581 => x"93", + 5582 => x"93", + 5583 => x"53", + 5584 => x"c8", + 5585 => x"0d", + 5586 => x"0d", + 5587 => x"3d", + 5588 => x"94", + 5589 => x"84", + 5590 => x"c8", + 5591 => x"93", + 5592 => x"df", + 5593 => x"63", + 5594 => x"d4", + 5595 => x"9c", + 5596 => x"c8", + 5597 => x"93", + 5598 => x"38", + 5599 => x"05", + 5600 => x"2b", + 5601 => x"80", + 5602 => x"76", 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x"52", + 5662 => x"d1", + 5663 => x"c8", + 5664 => x"93", + 5665 => x"2e", + 5666 => x"84", + 5667 => x"06", + 5668 => x"57", + 5669 => x"38", + 5670 => x"bc", + 5671 => x"05", + 5672 => x"3f", + 5673 => x"70", + 5674 => x"11", + 5675 => x"57", + 5676 => x"80", + 5677 => x"81", + 5678 => x"81", + 5679 => x"55", + 5680 => x"38", + 5681 => x"78", + 5682 => x"38", + 5683 => x"39", + 5684 => x"99", + 5685 => x"ff", + 5686 => x"08", + 5687 => x"70", + 5688 => x"56", + 5689 => x"33", + 5690 => x"eb", + 5691 => x"a3", + 5692 => x"55", + 5693 => x"34", + 5694 => x"fe", + 5695 => x"81", + 5696 => x"7c", + 5697 => x"06", + 5698 => x"19", + 5699 => x"11", + 5700 => x"74", + 5701 => x"82", + 5702 => x"70", + 5703 => x"fb", + 5704 => x"08", + 5705 => x"52", + 5706 => x"58", + 5707 => x"8d", + 5708 => x"70", + 5709 => x"51", + 5710 => x"f5", + 5711 => x"54", + 5712 => x"a5", + 5713 => x"77", + 5714 => x"38", + 5715 => x"73", + 5716 => x"81", + 5717 => x"81", + 5718 => x"78", + 5719 => x"ba", + 5720 => x"05", + 5721 => x"18", + 5722 => x"38", + 5723 => x"96", + 5724 => x"08", + 5725 => x"5a", + 5726 => x"7a", + 5727 => x"5c", + 5728 => x"26", + 5729 => x"7a", + 5730 => x"93", + 5731 => x"3d", + 5732 => x"3d", + 5733 => x"90", + 5734 => x"54", + 5735 => x"57", + 5736 => x"82", + 5737 => x"5a", + 5738 => x"08", + 5739 => x"17", + 5740 => x"80", + 5741 => x"79", + 5742 => x"39", + 5743 => x"78", + 5744 => x"90", + 5745 => x"81", + 5746 => x"06", + 5747 => x"74", + 5748 => x"17", + 5749 => x"17", + 5750 => x"70", + 5751 => x"5b", + 5752 => x"82", + 5753 => x"8a", + 5754 => x"89", + 5755 => x"55", + 5756 => x"b6", + 5757 => x"ff", + 5758 => x"96", + 5759 => x"93", + 5760 => x"17", + 5761 => x"53", + 5762 => x"96", + 5763 => x"93", + 5764 => x"26", + 5765 => x"30", + 5766 => x"18", + 5767 => x"18", + 5768 => x"18", + 5769 => x"80", + 5770 => x"17", + 5771 => x"be", + 5772 => x"76", + 5773 => x"3f", + 5774 => x"08", + 5775 => x"c8", + 5776 => x"09", + 5777 => x"38", + 5778 => x"18", + 5779 => x"82", + 5780 => x"93", + 5781 => x"2e", + 5782 => x"8b", + 5783 => x"91", + 5784 => x"55", + 5785 => x"82", + 5786 => x"88", + 5787 => x"98", + 5788 => x"80", + 5789 => x"38", + 5790 => x"80", + 5791 => x"79", + 5792 => x"08", + 5793 => x"0c", + 5794 => x"70", + 5795 => x"81", + 5796 => x"5d", + 5797 => x"2e", + 5798 => x"52", + 5799 => x"be", + 5800 => x"c8", + 5801 => x"93", + 5802 => x"38", + 5803 => x"08", + 5804 => x"75", + 5805 => x"c2", + 5806 => x"93", + 5807 => x"75", + 5808 => x"e1", + 5809 => x"27", + 5810 => x"55", + 5811 => x"76", + 5812 => x"82", + 5813 => x"34", + 5814 => x"d8", + 5815 => x"18", + 5816 => x"26", + 5817 => x"94", + 5818 => x"94", + 5819 => x"83", + 5820 => x"74", + 5821 => x"38", + 5822 => x"51", + 5823 => x"82", + 5824 => x"8b", + 5825 => x"91", + 5826 => x"55", + 5827 => x"77", + 5828 => x"93", + 5829 => x"5b", + 5830 => x"94", + 5831 => x"92", + 5832 => x"08", + 5833 => x"90", + 5834 => x"c0", + 5835 => x"90", + 5836 => x"17", + 5837 => x"06", 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x"93", + 5897 => x"17", + 5898 => x"85", + 5899 => x"38", + 5900 => x"14", + 5901 => x"23", + 5902 => x"51", + 5903 => x"82", + 5904 => x"55", + 5905 => x"09", + 5906 => x"38", + 5907 => x"80", + 5908 => x"80", + 5909 => x"54", + 5910 => x"c8", + 5911 => x"0d", + 5912 => x"0d", + 5913 => x"fc", + 5914 => x"52", + 5915 => x"3f", + 5916 => x"08", + 5917 => x"c8", + 5918 => x"82", + 5919 => x"74", + 5920 => x"93", + 5921 => x"3d", + 5922 => x"3d", + 5923 => x"89", + 5924 => x"54", + 5925 => x"54", + 5926 => x"82", + 5927 => x"53", + 5928 => x"08", + 5929 => x"74", + 5930 => x"93", + 5931 => x"73", + 5932 => x"3f", + 5933 => x"08", + 5934 => x"80", + 5935 => x"ce", + 5936 => x"93", + 5937 => x"82", + 5938 => x"84", + 5939 => x"06", + 5940 => x"53", + 5941 => x"74", + 5942 => x"d1", + 5943 => x"52", + 5944 => x"e9", + 5945 => x"c8", + 5946 => x"93", + 5947 => x"2e", + 5948 => x"83", + 5949 => x"72", + 5950 => x"0c", + 5951 => x"04", + 5952 => x"64", + 5953 => x"88", + 5954 => x"95", + 5955 => x"db", + 5956 => x"93", + 5957 => x"82", + 5958 => x"b5", + 5959 => x"73", + 5960 => x"3f", + 5961 => x"08", + 5962 => x"c8", + 5963 => x"02", + 5964 => x"33", + 5965 => x"55", + 5966 => x"25", + 5967 => x"55", + 5968 => x"80", + 5969 => x"75", + 5970 => x"d4", + 5971 => x"c1", + 5972 => x"93", + 5973 => x"3d", + 5974 => x"3d", + 5975 => x"55", + 5976 => x"90", + 5977 => x"52", + 5978 => x"da", + 5979 => x"93", + 5980 => x"82", + 5981 => x"82", + 5982 => x"74", + 5983 => x"98", + 5984 => x"05", + 5985 => x"15", + 5986 => x"93", + 5987 => x"08", + 5988 => x"e9", + 5989 => x"81", + 5990 => x"59", + 5991 => x"80", + 5992 => x"56", + 5993 => x"81", + 5994 => x"06", + 5995 => x"82", + 5996 => x"75", + 5997 => x"f0", + 5998 => x"bc", + 5999 => x"93", + 6000 => x"2e", + 6001 => x"93", + 6002 => x"2e", + 6003 => x"93", + 6004 => x"70", + 6005 => x"08", + 6006 => x"78", + 6007 => x"7d", + 6008 => x"54", + 6009 => x"76", + 6010 => x"80", + 6011 => x"98", + 6012 => x"12", + 6013 => x"54", + 6014 => x"98", + 6015 => x"81", + 6016 => x"58", + 6017 => x"3f", + 6018 => x"08", + 6019 => x"c8", + 6020 => x"38", + 6021 => x"51", + 6022 => x"2e", + 6023 => x"a0", + 6024 => x"b4", + 6025 => x"b5", + 6026 => x"93", + 6027 => x"ff", + 6028 => x"30", + 6029 => x"19", + 6030 => x"59", + 6031 => x"39", + 6032 => x"05", + 6033 => x"ea", + 6034 => x"c8", + 6035 => x"06", + 6036 => x"80", + 6037 => x"18", + 6038 => x"54", + 6039 => x"06", + 6040 => x"55", + 6041 => x"38", + 6042 => x"7a", + 6043 => x"0c", + 6044 => x"11", + 6045 => x"55", + 6046 => x"16", + 6047 => x"93", + 6048 => x"3d", + 6049 => x"3d", + 6050 => x"3d", + 6051 => x"70", + 6052 => x"94", + 6053 => x"c8", + 6054 => x"93", + 6055 => x"38", + 6056 => x"57", + 6057 => x"86", + 6058 => x"81", + 6059 => x"18", + 6060 => x"2a", + 6061 => x"51", + 6062 => x"56", + 6063 => x"81", + 6064 => x"18", + 6065 => x"08", + 6066 => x"38", + 6067 => x"9a", + 6068 => x"88", + 6069 => x"77", + 6070 => x"cf", + 6071 => x"c8", + 6072 => x"0b", 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x"81", + 6132 => x"56", + 6133 => x"3f", + 6134 => x"38", + 6135 => x"05", + 6136 => x"2a", + 6137 => x"51", + 6138 => x"80", + 6139 => x"86", + 6140 => x"95", + 6141 => x"98", + 6142 => x"f5", + 6143 => x"f7", + 6144 => x"98", + 6145 => x"73", + 6146 => x"38", + 6147 => x"39", + 6148 => x"05", + 6149 => x"54", + 6150 => x"83", + 6151 => x"75", + 6152 => x"6a", + 6153 => x"c6", + 6154 => x"93", + 6155 => x"84", + 6156 => x"05", + 6157 => x"2a", + 6158 => x"51", + 6159 => x"73", + 6160 => x"e5", + 6161 => x"9c", + 6162 => x"a5", + 6163 => x"55", + 6164 => x"08", + 6165 => x"d1", + 6166 => x"a0", + 6167 => x"91", + 6168 => x"76", + 6169 => x"a4", + 6170 => x"85", + 6171 => x"89", + 6172 => x"54", + 6173 => x"82", + 6174 => x"56", + 6175 => x"08", + 6176 => x"82", + 6177 => x"52", + 6178 => x"c0", + 6179 => x"c8", + 6180 => x"93", + 6181 => x"38", + 6182 => x"84", + 6183 => x"70", + 6184 => x"2c", + 6185 => x"56", + 6186 => x"dd", + 6187 => x"a8", + 6188 => x"bd", + 6189 => x"d4", + 6190 => x"a4", + 6191 => x"c8", + 6192 => x"c8", + 6193 => x"82", + 6194 => x"07", + 6195 => x"30", + 6196 => x"9f", + 6197 => x"52", + 6198 => x"56", + 6199 => x"9b", + 6200 => x"ac", + 6201 => x"89", + 6202 => x"76", + 6203 => x"d4", + 6204 => x"ba", + 6205 => x"93", + 6206 => x"75", + 6207 => x"51", + 6208 => x"3f", + 6209 => x"08", + 6210 => x"b0", + 6211 => x"e1", + 6212 => x"93", + 6213 => x"3d", + 6214 => x"3d", + 6215 => x"98", + 6216 => x"52", + 6217 => x"d3", + 6218 => x"93", + 6219 => x"82", + 6220 => x"82", + 6221 => x"5d", + 6222 => x"3d", + 6223 => x"cd", + 6224 => x"93", + 6225 => x"82", + 6226 => x"83", + 6227 => x"74", + 6228 => x"81", + 6229 => x"38", + 6230 => x"05", + 6231 => x"2a", + 6232 => x"51", + 6233 => x"80", + 6234 => x"86", + 6235 => x"2e", + 6236 => x"81", + 6237 => x"59", + 6238 => x"3d", + 6239 => x"ff", + 6240 => x"82", + 6241 => x"56", + 6242 => x"93", + 6243 => x"2e", + 6244 => x"83", + 6245 => x"75", + 6246 => x"81", + 6247 => x"82", + 6248 => x"2e", + 6249 => x"83", + 6250 => x"82", + 6251 => x"57", + 6252 => x"38", + 6253 => x"51", + 6254 => x"3f", + 6255 => x"08", + 6256 => x"c8", + 6257 => x"38", + 6258 => x"52", + 6259 => x"ff", + 6260 => x"77", + 6261 => x"b4", + 6262 => x"54", + 6263 => x"15", + 6264 => x"80", + 6265 => x"ff", + 6266 => x"75", + 6267 => x"52", + 6268 => x"aa", + 6269 => x"b4", + 6270 => x"d4", + 6271 => x"af", + 6272 => x"54", + 6273 => x"d5", + 6274 => x"53", + 6275 => x"52", + 6276 => x"8a", + 6277 => x"81", + 6278 => x"34", + 6279 => x"05", + 6280 => x"3f", + 6281 => x"08", + 6282 => x"c8", + 6283 => x"76", + 6284 => x"05", + 6285 => x"c1", + 6286 => x"63", + 6287 => x"c2", + 6288 => x"54", + 6289 => x"15", + 6290 => x"81", + 6291 => x"34", + 6292 => x"b1", + 6293 => x"93", + 6294 => x"8e", + 6295 => x"75", + 6296 => x"c4", + 6297 => x"b7", + 6298 => x"82", + 6299 => x"98", + 6300 => x"db", + 6301 => x"3d", + 6302 => x"cd", + 6303 => x"53", + 6304 => x"84", + 6305 => x"3d", + 6306 => x"3f", + 6307 => x"08", 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x"77", + 6367 => x"e5", + 6368 => x"c8", + 6369 => x"51", + 6370 => x"3f", + 6371 => x"93", + 6372 => x"2e", + 6373 => x"93", + 6374 => x"77", + 6375 => x"a7", + 6376 => x"c8", + 6377 => x"19", + 6378 => x"93", + 6379 => x"38", + 6380 => x"54", + 6381 => x"09", + 6382 => x"38", + 6383 => x"52", + 6384 => x"bf", + 6385 => x"54", + 6386 => x"15", + 6387 => x"38", + 6388 => x"05", + 6389 => x"3f", + 6390 => x"08", + 6391 => x"c8", + 6392 => x"77", + 6393 => x"a6", + 6394 => x"c8", + 6395 => x"82", + 6396 => x"a7", + 6397 => x"ed", + 6398 => x"80", + 6399 => x"02", + 6400 => x"df", + 6401 => x"57", + 6402 => x"3d", + 6403 => x"96", + 6404 => x"c8", + 6405 => x"c8", + 6406 => x"93", + 6407 => x"d4", + 6408 => x"65", + 6409 => x"d4", + 6410 => x"e0", + 6411 => x"c8", + 6412 => x"93", + 6413 => x"38", + 6414 => x"05", + 6415 => x"06", + 6416 => x"2e", + 6417 => x"55", + 6418 => x"75", + 6419 => x"71", + 6420 => x"33", + 6421 => x"74", + 6422 => x"57", + 6423 => x"8b", + 6424 => x"54", + 6425 => x"15", + 6426 => x"ff", + 6427 => x"82", + 6428 => x"55", + 6429 => x"c8", + 6430 => x"0d", + 6431 => x"0d", + 6432 => x"53", + 6433 => x"05", + 6434 => x"51", + 6435 => x"82", + 6436 => x"55", + 6437 => x"08", + 6438 => x"77", + 6439 => x"94", + 6440 => x"51", + 6441 => x"82", + 6442 => x"55", + 6443 => x"08", + 6444 => x"80", + 6445 => x"81", + 6446 => x"73", + 6447 => x"38", + 6448 => x"a9", + 6449 => x"22", + 6450 => x"70", + 6451 => x"07", + 6452 => x"7f", + 6453 => x"ff", + 6454 => x"77", + 6455 => x"83", + 6456 => x"51", + 6457 => x"3f", + 6458 => x"08", + 6459 => x"93", + 6460 => x"3d", + 6461 => x"3d", + 6462 => x"5c", + 6463 => x"98", + 6464 => x"52", + 6465 => x"cb", + 6466 => x"93", + 6467 => x"93", + 6468 => x"70", + 6469 => x"08", + 6470 => x"7b", + 6471 => x"07", + 6472 => x"06", + 6473 => x"56", + 6474 => x"2e", + 6475 => x"7b", + 6476 => x"80", + 6477 => x"70", + 6478 => x"b7", + 6479 => x"93", + 6480 => x"82", + 6481 => x"80", + 6482 => x"52", + 6483 => x"bc", + 6484 => x"93", + 6485 => x"82", + 6486 => x"bb", + 6487 => x"c8", + 6488 => x"c8", + 6489 => x"58", + 6490 => x"81", + 6491 => x"56", + 6492 => x"33", + 6493 => x"18", + 6494 => x"27", + 6495 => x"19", + 6496 => x"34", + 6497 => x"8f", + 6498 => x"79", + 6499 => x"51", + 6500 => x"a0", + 6501 => x"75", + 6502 => x"81", + 6503 => x"80", + 6504 => x"56", + 6505 => x"77", + 6506 => x"7c", + 6507 => x"07", + 6508 => x"06", + 6509 => x"55", + 6510 => x"bc", + 6511 => x"11", + 6512 => x"ff", + 6513 => x"82", + 6514 => x"56", + 6515 => x"08", + 6516 => x"70", + 6517 => x"80", + 6518 => x"83", + 6519 => x"80", + 6520 => x"84", + 6521 => x"a7", + 6522 => x"b4", + 6523 => x"a6", + 6524 => x"93", + 6525 => x"0c", + 6526 => x"c8", + 6527 => x"0d", + 6528 => x"0d", + 6529 => x"3d", + 6530 => x"52", + 6531 => x"c9", + 6532 => x"93", + 6533 => x"82", + 6534 => x"83", + 6535 => x"53", + 6536 => x"3d", + 6537 => x"51", + 6538 => x"3f", + 6539 => x"71", + 6540 => x"55", + 6541 => x"27", + 6542 => x"74", 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x"38", + 6602 => x"41", + 6603 => x"3d", + 6604 => x"ff", + 6605 => x"82", + 6606 => x"54", + 6607 => x"08", + 6608 => x"81", + 6609 => x"ff", + 6610 => x"82", + 6611 => x"54", + 6612 => x"08", + 6613 => x"80", + 6614 => x"8b", + 6615 => x"ff", + 6616 => x"65", + 6617 => x"c0", + 6618 => x"65", + 6619 => x"34", + 6620 => x"0b", + 6621 => x"77", + 6622 => x"92", + 6623 => x"c8", + 6624 => x"df", + 6625 => x"c8", + 6626 => x"09", + 6627 => x"d3", + 6628 => x"76", + 6629 => x"cb", + 6630 => x"9a", + 6631 => x"51", + 6632 => x"3f", + 6633 => x"08", + 6634 => x"c8", + 6635 => x"a0", + 6636 => x"c8", + 6637 => x"51", + 6638 => x"3f", + 6639 => x"0b", + 6640 => x"8b", + 6641 => x"ff", + 6642 => x"65", + 6643 => x"d8", + 6644 => x"81", + 6645 => x"34", + 6646 => x"a6", + 6647 => x"93", + 6648 => x"73", + 6649 => x"93", + 6650 => x"3d", + 6651 => x"3d", + 6652 => x"02", + 6653 => x"cf", + 6654 => x"3d", + 6655 => x"72", + 6656 => x"58", + 6657 => x"82", + 6658 => x"57", + 6659 => x"08", + 6660 => x"18", + 6661 => x"80", + 6662 => x"76", + 6663 => x"39", + 6664 => x"95", + 6665 => x"08", + 6666 => x"18", + 6667 => x"2a", + 6668 => x"51", + 6669 => x"90", + 6670 => x"82", + 6671 => x"57", + 6672 => x"81", + 6673 => x"39", + 6674 => x"22", + 6675 => x"70", + 6676 => x"58", + 6677 => x"f9", + 6678 => x"16", + 6679 => x"30", + 6680 => x"9f", + 6681 => x"c8", + 6682 => x"8c", + 6683 => x"52", + 6684 => x"80", + 6685 => x"27", + 6686 => x"14", + 6687 => x"83", + 6688 => x"78", + 6689 => x"80", + 6690 => x"77", + 6691 => x"d7", + 6692 => x"c8", + 6693 => x"61", + 6694 => x"98", + 6695 => x"26", + 6696 => x"55", + 6697 => x"ff", + 6698 => x"ff", + 6699 => x"38", + 6700 => x"81", + 6701 => x"7e", + 6702 => x"85", + 6703 => x"80", + 6704 => x"2e", + 6705 => x"c1", + 6706 => x"76", + 6707 => x"7b", + 6708 => x"38", + 6709 => x"55", + 6710 => x"b3", + 6711 => x"54", + 6712 => x"09", + 6713 => x"38", + 6714 => x"53", + 6715 => x"51", + 6716 => x"3f", + 6717 => x"08", + 6718 => x"c8", + 6719 => x"74", + 6720 => x"18", + 6721 => x"75", + 6722 => x"39", + 6723 => x"76", + 6724 => x"7f", + 6725 => x"0c", + 6726 => x"2e", + 6727 => x"88", + 6728 => x"8c", + 6729 => x"18", + 6730 => x"07", + 6731 => x"19", + 6732 => x"11", + 6733 => x"55", + 6734 => x"08", + 6735 => x"38", + 6736 => x"7e", + 6737 => x"0c", + 6738 => x"33", + 6739 => x"55", + 6740 => x"34", + 6741 => x"82", + 6742 => x"91", + 6743 => x"ea", + 6744 => x"02", + 6745 => x"e7", + 6746 => x"3d", + 6747 => x"ff", + 6748 => x"82", + 6749 => x"56", + 6750 => x"0b", + 6751 => x"08", + 6752 => x"38", + 6753 => x"08", + 6754 => x"93", + 6755 => x"74", + 6756 => x"87", + 6757 => x"55", + 6758 => x"75", + 6759 => x"5a", + 6760 => x"51", + 6761 => x"3f", + 6762 => x"08", + 6763 => x"70", + 6764 => x"56", + 6765 => x"8c", + 6766 => x"82", + 6767 => x"06", + 6768 => x"57", + 6769 => x"38", + 6770 => x"05", + 6771 => x"79", + 6772 => x"dd", + 6773 => x"c8", + 6774 => x"66", + 6775 => x"38", + 6776 => x"80", + 6777 => x"66", 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x"61", + 6837 => x"81", + 6838 => x"38", + 6839 => x"65", + 6840 => x"5c", + 6841 => x"81", + 6842 => x"71", + 6843 => x"56", + 6844 => x"2e", + 6845 => x"77", + 6846 => x"81", + 6847 => x"71", + 6848 => x"22", + 6849 => x"5b", + 6850 => x"86", + 6851 => x"27", + 6852 => x"52", + 6853 => x"f4", + 6854 => x"93", + 6855 => x"93", + 6856 => x"10", + 6857 => x"87", + 6858 => x"fe", + 6859 => x"82", + 6860 => x"5c", + 6861 => x"0b", + 6862 => x"17", + 6863 => x"ff", + 6864 => x"27", + 6865 => x"8e", + 6866 => x"39", + 6867 => x"65", + 6868 => x"5c", + 6869 => x"81", + 6870 => x"71", + 6871 => x"56", + 6872 => x"2e", + 6873 => x"77", + 6874 => x"81", + 6875 => x"71", + 6876 => x"22", + 6877 => x"5b", + 6878 => x"86", + 6879 => x"27", + 6880 => x"52", + 6881 => x"f3", + 6882 => x"93", + 6883 => x"84", + 6884 => x"93", + 6885 => x"f5", + 6886 => x"81", + 6887 => x"c8", + 6888 => x"11", + 6889 => x"83", + 6890 => x"42", + 6891 => x"1e", + 6892 => x"fe", + 6893 => x"82", + 6894 => x"5c", + 6895 => x"5b", + 6896 => x"51", + 6897 => x"3f", + 6898 => x"08", + 6899 => x"06", + 6900 => x"7c", + 6901 => x"68", + 6902 => x"69", + 6903 => x"06", + 6904 => x"58", + 6905 => x"61", + 6906 => x"81", + 6907 => x"76", + 6908 => x"41", + 6909 => x"76", + 6910 => x"90", + 6911 => x"65", + 6912 => x"74", + 6913 => x"be", + 6914 => x"31", + 6915 => x"53", + 6916 => x"52", + 6917 => x"9e", + 6918 => x"c8", + 6919 => x"83", + 6920 => x"06", + 6921 => x"93", + 6922 => x"ff", + 6923 => x"38", + 6924 => x"78", + 6925 => x"77", + 6926 => x"8e", + 6927 => x"39", + 6928 => x"09", + 6929 => x"d3", + 6930 => x"f5", + 6931 => x"38", + 6932 => x"78", + 6933 => x"80", + 6934 => x"38", + 6935 => x"f1", + 6936 => x"2a", + 6937 => x"74", + 6938 => x"38", + 6939 => x"e1", + 6940 => x"38", + 6941 => x"81", + 6942 => x"fc", + 6943 => x"57", + 6944 => x"75", + 6945 => x"93", + 6946 => x"38", + 6947 => x"81", + 6948 => x"fc", + 6949 => x"57", + 6950 => x"80", + 6951 => x"2e", + 6952 => x"83", + 6953 => x"75", + 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x"ec", + 7307 => x"f4", + 7308 => x"81", + 7309 => x"8b", + 7310 => x"52", + 7311 => x"d6", + 7312 => x"80", + 7313 => x"8c", + 7314 => x"33", + 7315 => x"94", + 7316 => x"c9", + 7317 => x"2e", + 7318 => x"f6", + 7319 => x"3d", + 7320 => x"3d", + 7321 => x"96", + 7322 => x"fe", + 7323 => x"81", + 7324 => x"ff", + 7325 => x"b0", + 7326 => x"f5", + 7327 => x"fe", + 7328 => x"72", + 7329 => x"81", + 7330 => x"71", + 7331 => x"38", + 7332 => x"ee", + 7333 => x"86", + 7334 => x"f0", + 7335 => x"51", + 7336 => x"3f", + 7337 => x"70", + 7338 => x"52", + 7339 => x"95", + 7340 => x"fe", + 7341 => x"82", + 7342 => x"fe", + 7343 => x"80", + 7344 => x"af", + 7345 => x"2a", + 7346 => x"51", + 7347 => x"2e", + 7348 => x"51", + 7349 => x"3f", + 7350 => x"51", + 7351 => x"3f", + 7352 => x"ee", + 7353 => x"84", + 7354 => x"06", + 7355 => x"80", + 7356 => x"81", + 7357 => x"fb", + 7358 => x"84", + 7359 => x"f1", + 7360 => x"fe", + 7361 => x"72", + 7362 => x"81", + 7363 => x"71", + 7364 => x"38", + 7365 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x"f8", + 7542 => x"e4", + 7543 => x"93", + 7544 => x"3d", + 7545 => x"52", + 7546 => x"fa", + 7547 => x"82", + 7548 => x"52", + 7549 => x"a7", + 7550 => x"c8", + 7551 => x"fc", + 7552 => x"93", + 7553 => x"f3", + 7554 => x"e5", + 7555 => x"fe", + 7556 => x"fe", + 7557 => x"82", + 7558 => x"b5", + 7559 => x"05", + 7560 => x"e4", + 7561 => x"93", + 7562 => x"3d", + 7563 => x"52", + 7564 => x"b2", + 7565 => x"c8", + 7566 => x"fe", + 7567 => x"59", + 7568 => x"3f", + 7569 => x"58", + 7570 => x"57", + 7571 => x"55", + 7572 => x"08", + 7573 => x"54", + 7574 => x"52", + 7575 => x"fb", + 7576 => x"c8", + 7577 => x"fc", + 7578 => x"93", + 7579 => x"f2", + 7580 => x"fd", + 7581 => x"98", + 7582 => x"a7", + 7583 => x"fe", + 7584 => x"fb", + 7585 => x"89", + 7586 => x"f3", + 7587 => x"51", + 7588 => x"3f", + 7589 => x"84", + 7590 => x"87", + 7591 => x"0c", + 7592 => x"0b", + 7593 => x"94", + 7594 => x"c8", + 7595 => x"f3", + 7596 => x"39", + 7597 => x"51", + 7598 => x"3f", + 7599 => x"0b", + 7600 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=> x"5c", + 7836 => x"5c", + 7837 => x"5c", + 7838 => x"5c", + 7839 => x"5c", + 7840 => x"5c", + 7841 => x"5c", + 7842 => x"5c", + 7843 => x"5c", + 7844 => x"5c", + 7845 => x"5c", + 7846 => x"5c", + 7847 => x"5c", + 7848 => x"5c", + 7849 => x"5c", + 7850 => x"5c", + 7851 => x"5c", + 7852 => x"5c", + 7853 => x"5c", + 7854 => x"5c", + 7855 => x"5c", + 7856 => x"5c", + 7857 => x"5c", + 7858 => x"5c", + 7859 => x"5c", + 7860 => x"5c", + 7861 => x"5c", + 7862 => x"5c", + 7863 => x"5c", + 7864 => x"5c", + 7865 => x"5c", + 7866 => x"d1", + 7867 => x"f6", + 7868 => x"5c", + 7869 => x"5c", + 7870 => x"5c", + 7871 => x"5c", + 7872 => x"5c", + 7873 => x"5c", + 7874 => x"5c", + 7875 => x"5c", + 7876 => x"39", + 7877 => x"48", + 7878 => x"5c", + 7879 => x"55", + 7880 => x"5c", + 7881 => x"71", + 7882 => x"25", + 7883 => x"64", + 7884 => x"3a", + 7885 => x"25", + 7886 => x"64", + 7887 => x"00", + 7888 => x"20", + 7889 => x"66", + 7890 => x"72", + 7891 => x"6f", + 7892 => x"00", + 7893 => x"72", + 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=> x"55", + 8071 => x"a7", + 8072 => x"ab", + 8073 => x"af", + 8074 => x"b3", + 8075 => x"b7", + 8076 => x"bb", + 8077 => x"bf", + 8078 => x"c3", + 8079 => x"c7", + 8080 => x"cb", + 8081 => x"cf", + 8082 => x"d3", + 8083 => x"d7", + 8084 => x"db", + 8085 => x"df", + 8086 => x"e3", + 8087 => x"e7", + 8088 => x"eb", + 8089 => x"ef", + 8090 => x"f3", + 8091 => x"f7", + 8092 => x"fb", + 8093 => x"ff", + 8094 => x"3b", + 8095 => x"2f", + 8096 => x"3a", + 8097 => x"7c", + 8098 => x"00", + 8099 => x"04", + 8100 => x"40", + 8101 => x"00", + 8102 => x"00", + 8103 => x"02", + 8104 => x"08", + 8105 => x"20", + 8106 => x"00", + 8107 => x"31", + 8108 => x"00", + 8109 => x"31", + 8110 => x"00", + 8111 => x"41", + 8112 => x"00", + 8113 => x"4b", + 8114 => x"20", + 8115 => x"54", + 8116 => x"53", + 8117 => x"00", + 8118 => x"4b", + 8119 => x"46", + 8120 => x"20", + 8121 => x"54", + 8122 => x"53", + 8123 => x"00", + 8124 => x"45", + 8125 => x"54", + 8126 => x"43", + 8127 => x"52", + 8128 => x"00", + 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x"65", + 8482 => x"00", + 8483 => x"25", + 8484 => x"00", + 8485 => x"00", + 8486 => x"61", + 8487 => x"6e", + 8488 => x"6e", + 8489 => x"72", + 8490 => x"73", + 8491 => x"00", + 8492 => x"62", + 8493 => x"67", + 8494 => x"74", + 8495 => x"75", + 8496 => x"0a", + 8497 => x"00", + 8498 => x"61", + 8499 => x"64", + 8500 => x"72", + 8501 => x"69", + 8502 => x"00", + 8503 => x"62", + 8504 => x"67", + 8505 => x"72", + 8506 => x"69", + 8507 => x"00", + 8508 => x"63", + 8509 => x"6e", + 8510 => x"6f", + 8511 => x"40", + 8512 => x"38", + 8513 => x"2e", + 8514 => x"00", + 8515 => x"6c", + 8516 => x"20", + 8517 => x"65", + 8518 => x"25", + 8519 => x"20", + 8520 => x"0a", + 8521 => x"00", + 8522 => x"6c", + 8523 => x"74", + 8524 => x"65", + 8525 => x"6f", + 8526 => x"28", + 8527 => x"2e", + 8528 => x"00", + 8529 => x"74", + 8530 => x"69", + 8531 => x"61", + 8532 => x"69", + 8533 => x"69", + 8534 => x"2e", + 8535 => x"00", + 8536 => x"64", + 8537 => x"62", + 8538 => x"69", + 8539 => x"2e", + 8540 => x"00", + 8541 => x"00", + 8542 => x"00", + 8543 => x"5c", + 8544 => x"25", + 8545 => x"73", + 8546 => x"00", + 8547 => x"20", + 8548 => x"6d", + 8549 => x"2e", + 8550 => x"00", + 8551 => x"6e", + 8552 => x"2e", + 8553 => x"00", + 8554 => x"62", + 8555 => x"67", + 8556 => x"74", + 8557 => x"75", + 8558 => x"2e", + 8559 => x"00", + 8560 => x"00", + 8561 => x"00", + 8562 => x"ff", + 8563 => x"00", + 8564 => x"ff", + 8565 => x"00", + 8566 => x"ff", + 8567 => x"00", + 8568 => x"00", + 8569 => x"00", + 8570 => x"00", + 8571 => x"00", + 8572 => x"01", + 8573 => x"01", + 8574 => x"01", + 8575 => x"00", + 8576 => x"00", + 8577 => x"00", + 8578 => x"3c", + 8579 => x"00", + 8580 => x"00", + 8581 => x"00", + 8582 => x"44", + 8583 => x"00", + 8584 => x"00", + 8585 => x"00", + 8586 => x"4c", + 8587 => x"00", + 8588 => x"00", + 8589 => x"00", + 8590 => x"54", + 8591 => x"00", + 8592 => x"00", + 8593 => x"00", + 8594 => x"5c", + 8595 => x"00", + 8596 => x"00", + 8597 => x"00", + 8598 => x"64", + 8599 => x"00", + 8600 => x"00", + 8601 => x"00", + 8602 => x"6c", + 8603 => x"00", + 8604 => x"00", + 8605 => x"00", + 8606 => x"74", + 8607 => x"00", + 8608 => x"00", + 8609 => x"00", + 8610 => x"7c", + 8611 => x"00", + 8612 => x"00", + 8613 => x"00", + 8614 => x"84", + 8615 => x"00", + 8616 => x"00", + 8617 => x"00", + 8618 => x"8c", + 8619 => x"00", + 8620 => x"00", + 8621 => x"00", + 8622 => x"94", + 8623 => x"00", + 8624 => x"00", + 8625 => x"00", + 8626 => x"9c", + 8627 => x"00", + 8628 => x"00", + 8629 => x"00", + 8630 => x"a4", + 8631 => x"00", + 8632 => x"00", + 8633 => x"00", + 8634 => x"ac", + 8635 => x"00", + 8636 => x"00", + 8637 => x"00", + 8638 => x"b4", + 8639 => x"00", + 8640 => x"00", + 8641 => x"00", + 8642 => x"c0", + 8643 => x"00", + 8644 => x"00", + 8645 => x"00", + 8646 => x"c8", + 8647 => x"00", + 8648 => x"00", + 8649 => x"00", + 8650 => x"d0", + 8651 => x"00", + 8652 => x"00", + 8653 => x"00", + 8654 => x"d8", + 8655 => x"00", + 8656 => x"00", + 8657 => x"00", + 8658 => x"e0", + 8659 => x"00", + 8660 => x"00", + 8661 => x"00", + 8662 => x"e8", + 8663 => x"00", + 8664 => x"00", + 8665 => x"00", + 8666 => x"f0", + 8667 => x"00", + 8668 => x"00", + 8669 => x"00", + 8670 => x"f8", + 8671 => x"00", + 8672 => x"00", + 8673 => x"00", + 8674 => x"00", + 8675 => x"00", + 8676 => x"00", + 8677 => x"00", + 8678 => x"08", + 8679 => x"00", + 8680 => x"00", + 8681 => x"00", + 8682 => x"10", + 8683 => x"00", + 8684 => x"00", + 8685 => x"00", + 8686 => x"18", + 8687 => x"00", + 8688 => x"00", + 8689 => x"00", + 8690 => x"1c", + 8691 => x"00", + 8692 => x"00", + 8693 => x"00", + 8694 => x"24", + 8695 => x"00", + 8696 => x"00", + 8697 => x"00", + 8698 => x"2c", + 8699 => x"00", + 8700 => x"00", + 8701 => x"00", + 8702 => x"34", + 8703 => x"00", + 8704 => x"00", + 8705 => x"00", + 8706 => x"3c", + 8707 => x"00", + 8708 => x"00", + 8709 => x"00", + 8710 => x"44", + 8711 => x"00", + 8712 => x"00", + 8713 => x"00", + 8714 => x"4c", + 8715 => x"00", + 8716 => x"00", + 8717 => x"00", + 8718 => x"50", + 8719 => x"00", + 8720 => x"00", + 8721 => x"00", + 8722 => x"58", + 8723 => x"00", + 8724 => x"00", + 8725 => x"00", + 8726 => x"64", + 8727 => x"00", + 8728 => x"00", + 8729 => x"00", + 8730 => x"6c", + 8731 => x"00", + 8732 => x"00", + 8733 => x"00", + 8734 => x"74", + 8735 => x"00", + 8736 => x"00", + 8737 => x"00", + 8738 => x"7c", + 8739 => x"00", + 8740 => x"00", + 8741 => x"00", + 8742 => x"84", + 8743 => x"00", + 8744 => x"00", + 8745 => x"00", + 8746 => x"88", + 8747 => x"00", + 8748 => x"00", + 8749 => x"00", + 8750 => x"8c", + 8751 => x"00", + 8752 => x"00", + 8753 => x"00", + 8754 => x"90", + 8755 => x"00", + 8756 => x"00", + 8757 => x"00", + 8758 => x"94", + 8759 => x"00", + 8760 => x"00", + 8761 => x"00", + 8762 => x"98", + 8763 => x"00", + 8764 => x"00", + 8765 => x"00", + 8766 => x"9c", + 8767 => x"00", + 8768 => x"00", + 8769 => x"00", + 8770 => x"a0", + 8771 => x"00", + 8772 => x"00", + 8773 => x"00", + 8774 => x"a4", + 8775 => x"00", + 8776 => x"00", + 8777 => x"00", + 8778 => x"a8", + 8779 => x"00", + 8780 => x"00", + 8781 => x"00", + 8782 => x"b0", + 8783 => x"00", + 8784 => x"00", + 8785 => x"00", + 8786 => x"bc", + 8787 => x"00", + 8788 => x"00", + 8789 => x"00", + 8790 => x"c4", + 8791 => x"00", + 8792 => x"00", + 8793 => x"00", + 8794 => x"c8", + 8795 => x"00", + 8796 => x"00", + 8797 => x"00", + 8798 => x"d0", + 8799 => x"00", + 8800 => x"00", + 8801 => x"00", + 8802 => x"d8", + 8803 => x"00", + 8804 => x"00", + 8805 => x"00", + 8806 => x"e0", + 8807 => x"00", + 8808 => x"00", + 8809 => x"00", + 8810 => x"e8", + 8811 => x"00", + 8812 => x"00", + 8813 => x"00", + 8814 => x"f0", + 8815 => x"00", + 8816 => x"00", + 8817 => x"00", + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + 0 => x"0b", + 1 => x"00", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"8c", + 9 => x"0b", + 10 => x"80", + 11 => x"0c", + 12 => x"0c", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"06", + 17 => x"06", + 18 => x"82", + 19 => x"2a", + 20 => x"06", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"06", + 25 => x"ff", + 26 => x"09", + 27 => x"05", + 28 => x"09", + 29 => x"ff", + 30 => x"0b", + 31 => x"04", + 32 => x"81", + 33 => x"73", + 34 => x"09", + 35 => x"73", + 36 => x"81", + 37 => x"04", + 38 => x"00", + 39 => x"00", + 40 => x"24", + 41 => x"07", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"81", + 50 => x"05", + 51 => x"0a", + 52 => x"0a", + 53 => x"81", + 54 => x"53", + 55 => x"00", + 56 => x"26", + 57 => x"07", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"51", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"9f", + 89 => x"05", + 90 => x"88", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"2a", + 97 => x"06", + 98 => x"09", + 99 => x"ff", + 100 => x"53", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"53", + 105 => x"73", + 106 => x"81", + 107 => x"83", + 108 => x"07", + 109 => x"0c", + 110 => x"00", + 111 => x"00", + 112 => x"81", + 113 => x"09", + 114 => x"09", + 115 => x"06", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"81", + 121 => x"09", + 122 => x"09", + 123 => x"81", + 124 => x"04", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"81", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"09", + 137 => x"53", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"09", + 146 => x"51", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"06", + 153 => x"06", + 154 => x"83", + 155 => x"10", + 156 => x"06", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"06", + 161 => x"0b", + 162 => x"83", + 163 => x"05", + 164 => x"0b", + 165 => x"04", + 166 => x"00", + 167 => x"00", + 168 => x"8c", + 169 => x"75", + 170 => x"0b", + 171 => x"50", + 172 => x"56", + 173 => x"0c", + 174 => x"04", + 175 => x"00", + 176 => x"8c", + 177 => x"75", + 178 => x"0b", + 179 => x"50", + 180 => x"56", + 181 => x"0c", + 182 => x"04", + 183 => x"00", + 184 => x"70", + 185 => x"06", + 186 => x"ff", + 187 => x"71", + 188 => x"72", + 189 => x"05", + 190 => x"51", + 191 => x"00", + 192 => x"70", + 193 => x"06", + 194 => x"06", + 195 => x"54", + 196 => x"09", + 197 => x"ff", + 198 => x"51", + 199 => x"00", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"05", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"05", + 233 => x"05", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"05", + 249 => x"53", + 250 => x"04", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"04", + 257 => x"00", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"10", + 266 => x"00", + 267 => x"ff", + 268 => x"06", + 269 => x"83", + 270 => x"10", + 271 => x"fc", + 272 => x"51", + 273 => x"80", + 274 => x"ff", + 275 => x"06", + 276 => x"52", + 277 => x"0a", + 278 => x"38", + 279 => x"51", + 280 => x"00", + 281 => x"00", + 282 => x"ac", + 283 => x"27", + 284 => x"71", + 285 => x"53", + 286 => x"04", + 287 => x"9e", + 288 => x"08", + 289 => x"fd", + 290 => x"53", + 291 => x"05", + 292 => x"08", + 293 => x"51", + 294 => x"88", + 295 => x"0c", + 296 => x"0d", + 297 => x"94", + 298 => x"0c", + 299 => x"81", + 300 => x"8c", + 301 => x"94", + 302 => x"08", + 303 => x"3f", + 304 => x"88", + 305 => x"3d", + 306 => x"04", + 307 => x"94", + 308 => x"0d", + 309 => x"08", + 310 => x"94", + 311 => x"08", + 312 => x"38", + 313 => x"05", + 314 => x"08", + 315 => x"80", + 316 => x"f4", + 317 => x"08", + 318 => x"88", + 319 => x"94", + 320 => x"0c", + 321 => x"05", + 322 => x"fc", + 323 => x"08", + 324 => x"80", + 325 => x"94", + 326 => x"08", + 327 => x"8c", + 328 => x"0b", + 329 => x"05", + 330 => x"fc", + 331 => x"38", + 332 => x"08", + 333 => x"94", + 334 => x"08", + 335 => x"05", + 336 => x"94", + 337 => x"08", + 338 => x"88", + 339 => x"81", + 340 => x"08", + 341 => x"f8", + 342 => x"94", + 343 => x"08", + 344 => x"38", + 345 => x"05", + 346 => x"08", + 347 => x"94", + 348 => x"08", + 349 => x"54", + 350 => x"94", + 351 => x"08", + 352 => x"fb", + 353 => x"0b", + 354 => x"05", + 355 => x"88", + 356 => x"25", + 357 => x"08", + 358 => x"30", + 359 => x"05", + 360 => x"94", + 361 => x"0c", + 362 => x"05", + 363 => x"8c", + 364 => x"8c", + 365 => x"94", + 366 => x"0c", + 367 => x"08", + 368 => x"52", + 369 => x"05", + 370 => x"3f", + 371 => x"94", + 372 => x"0c", + 373 => x"fc", + 374 => x"2e", + 375 => x"08", + 376 => x"30", + 377 => x"05", + 378 => x"f8", + 379 => x"88", + 380 => x"3d", + 381 => x"04", + 382 => x"94", + 383 => x"0d", + 384 => x"08", + 385 => x"80", + 386 => x"f8", + 387 => x"08", + 388 => x"94", + 389 => x"08", + 390 => x"94", + 391 => x"08", + 392 => x"38", + 393 => x"08", + 394 => x"24", + 395 => x"08", + 396 => x"10", + 397 => x"05", + 398 => x"fc", + 399 => x"94", + 400 => x"0c", + 401 => x"08", + 402 => x"80", + 403 => x"38", + 404 => x"05", + 405 => x"88", + 406 => x"a1", + 407 => x"88", + 408 => x"08", + 409 => x"31", + 410 => x"05", + 411 => x"f8", + 412 => x"08", + 413 => x"07", + 414 => x"05", + 415 => x"fc", + 416 => x"2a", + 417 => x"05", + 418 => x"8c", + 419 => x"2a", + 420 => x"05", + 421 => x"39", + 422 => x"05", + 423 => x"8f", + 424 => x"88", + 425 => x"94", + 426 => x"0c", + 427 => x"94", + 428 => x"08", + 429 => x"f4", + 430 => x"94", + 431 => x"08", + 432 => x"3d", + 433 => x"04", + 434 => x"81", + 435 => x"c0", + 436 => x"81", + 437 => x"92", + 438 => x"0b", + 439 => x"8c", + 440 => x"92", + 441 => x"82", + 442 => x"70", + 443 => x"38", + 444 => x"8c", + 445 => x"e9", + 446 => x"92", + 447 => x"80", + 448 => x"71", + 449 => x"c0", + 450 => x"51", + 451 => x"88", + 452 => x"0b", + 453 => x"34", + 454 => x"9f", + 455 => x"0c", + 456 => x"04", + 457 => x"78", + 458 => x"58", + 459 => x"0b", + 460 => x"a8", + 461 => x"52", + 462 => x"70", + 463 => x"81", + 464 => x"38", + 465 => x"c0", + 466 => x"79", + 467 => x"80", + 468 => x"87", + 469 => x"0c", + 470 => x"8c", + 471 => x"2a", + 472 => x"51", + 473 => x"80", + 474 => x"87", + 475 => x"08", + 476 => x"06", + 477 => x"52", + 478 => x"80", + 479 => x"70", + 480 => x"38", + 481 => x"81", + 482 => x"ff", + 483 => x"15", + 484 => x"06", + 485 => x"2e", + 486 => x"c0", + 487 => x"51", + 488 => x"38", + 489 => x"8c", + 490 => x"95", + 491 => x"87", + 492 => x"0c", + 493 => x"8c", + 494 => x"06", + 495 => x"f4", + 496 => x"fc", + 497 => x"52", + 498 => x"2e", + 499 => x"8f", + 500 => x"98", + 501 => x"70", + 502 => x"81", + 503 => x"81", + 504 => x"0c", + 505 => x"04", + 506 => x"74", + 507 => x"71", + 508 => x"2b", + 509 => x"53", + 510 => x"0d", + 511 => x"0d", + 512 => x"33", + 513 => x"71", + 514 => x"88", + 515 => x"14", + 516 => x"07", + 517 => x"33", + 518 => x"0c", + 519 => x"56", + 520 => x"3d", + 521 => x"3d", + 522 => x"0b", + 523 => x"08", + 524 => x"77", + 525 => x"38", + 526 => x"08", + 527 => x"38", + 528 => x"74", + 529 => x"38", + 530 => x"ae", + 531 => x"39", + 532 => x"10", + 533 => x"53", + 534 => x"8c", + 535 => x"52", + 536 => x"52", + 537 => x"3f", + 538 => x"38", + 539 => x"f8", + 540 => x"83", + 541 => x"55", + 542 => x"54", + 543 => x"83", + 544 => x"76", + 545 => x"17", + 546 => x"88", + 547 => x"55", + 548 => x"88", + 549 => x"74", + 550 => x"3f", + 551 => x"0a", + 552 => x"39", + 553 => x"88", + 554 => x"0d", + 555 => x"0d", + 556 => x"9f", + 557 => x"19", + 558 => x"fe", + 559 => x"54", + 560 => x"73", + 561 => x"82", + 562 => x"71", + 563 => x"08", + 564 => x"75", + 565 => x"3d", + 566 => x"3d", + 567 => x"80", + 568 => x"0b", + 569 => x"70", + 570 => x"53", + 571 => x"09", + 572 => x"38", + 573 => x"fd", + 574 => x"08", + 575 => x"9a", + 576 => x"e4", + 577 => x"83", + 578 => x"73", + 579 => x"85", + 580 => x"fc", + 581 => x"0b", + 582 => x"ac", + 583 => x"80", + 584 => x"15", + 585 => x"81", + 586 => x"88", + 587 => x"26", + 588 => x"52", + 589 => x"90", + 590 => x"52", + 591 => x"09", + 592 => x"38", + 593 => x"53", + 594 => x"0c", + 595 => x"8b", + 596 => x"fe", + 597 => x"08", + 598 => x"90", + 599 => x"71", + 600 => x"80", + 601 => x"0c", + 602 => x"04", + 603 => x"78", + 604 => x"9f", + 605 => x"22", + 606 => x"83", + 607 => x"57", + 608 => x"73", + 609 => x"38", + 610 => x"53", + 611 => x"83", + 612 => x"39", + 613 => x"52", + 614 => x"38", + 615 => x"16", + 616 => x"08", + 617 => x"38", + 618 => x"17", + 619 => x"73", + 620 => x"38", + 621 => x"16", + 622 => x"74", + 623 => x"52", + 624 => x"72", + 625 => x"3f", + 626 => x"88", + 627 => x"38", + 628 => x"08", + 629 => x"27", + 630 => x"08", + 631 => x"88", + 632 => x"c9", + 633 => x"90", + 634 => x"75", + 635 => x"71", + 636 => x"3d", + 637 => x"3d", + 638 => x"64", + 639 => x"75", + 640 => x"a0", + 641 => x"06", + 642 => x"16", + 643 => x"ef", + 644 => x"33", + 645 => x"af", + 646 => x"06", + 647 => x"16", + 648 => x"88", + 649 => x"70", + 650 => x"74", + 651 => x"38", + 652 => x"df", + 653 => x"56", + 654 => x"82", + 655 => x"3d", + 656 => x"70", + 657 => x"8a", + 658 => x"70", + 659 => x"34", + 660 => x"74", + 661 => x"81", + 662 => x"80", + 663 => x"88", + 664 => x"5a", + 665 => x"70", + 666 => x"60", + 667 => x"70", + 668 => x"30", + 669 => x"71", + 670 => x"51", + 671 => x"53", + 672 => x"74", + 673 => x"76", + 674 => x"81", + 675 => x"81", + 676 => x"27", + 677 => x"74", + 678 => x"38", + 679 => x"70", + 680 => x"32", + 681 => x"73", + 682 => x"53", + 683 => x"56", + 684 => x"88", + 685 => x"ff", + 686 => x"81", + 687 => x"ff", + 688 => x"53", + 689 => x"76", + 690 => x"98", + 691 => x"7f", + 692 => x"76", + 693 => x"38", + 694 => x"8b", + 695 => x"51", + 696 => x"88", + 697 => x"38", + 698 => x"22", + 699 => x"83", + 700 => x"55", + 701 => x"52", + 702 => x"a8", + 703 => x"57", + 704 => x"fb", + 705 => x"55", + 706 => x"80", + 707 => x"1d", + 708 => x"2a", + 709 => x"51", + 710 => x"b2", + 711 => x"84", + 712 => x"08", + 713 => x"58", + 714 => x"77", + 715 => x"38", + 716 => x"05", + 717 => x"70", + 718 => x"33", + 719 => x"52", + 720 => x"80", + 721 => x"86", + 722 => x"2e", + 723 => x"51", + 724 => x"ff", + 725 => x"08", + 726 => x"b4", + 727 => x"76", + 728 => x"08", + 729 => x"51", + 730 => x"38", + 731 => x"70", + 732 => x"81", + 733 => x"56", + 734 => x"83", + 735 => x"81", + 736 => x"7c", + 737 => x"3f", + 738 => x"1d", + 739 => x"39", + 740 => x"90", + 741 => x"f9", + 742 => x"7b", + 743 => x"54", + 744 => x"77", + 745 => x"f6", + 746 => x"56", + 747 => x"e7", + 748 => x"f8", + 749 => x"08", + 750 => x"06", + 751 => x"74", + 752 => x"2e", + 753 => x"80", + 754 => x"54", + 755 => x"52", + 756 => x"d0", + 757 => x"56", + 758 => x"38", + 759 => x"88", + 760 => x"83", + 761 => x"55", + 762 => x"c6", + 763 => x"82", + 764 => x"53", + 765 => x"51", + 766 => x"88", + 767 => x"08", + 768 => x"51", + 769 => x"88", + 770 => x"ff", + 771 => x"81", + 772 => x"83", + 773 => x"75", + 774 => x"3d", + 775 => x"3d", + 776 => x"80", + 777 => x"0b", + 778 => x"f5", + 779 => x"08", + 780 => x"82", + 781 => x"f2", + 782 => x"53", + 783 => x"53", + 784 => x"d3", + 785 => x"81", + 786 => x"76", + 787 => x"81", + 788 => x"90", + 789 => x"53", + 790 => x"51", + 791 => x"88", + 792 => x"8d", + 793 => x"74", + 794 => x"38", + 795 => x"05", + 796 => x"3f", + 797 => x"08", + 798 => x"5a", + 799 => x"88", + 800 => x"06", + 801 => x"2e", + 802 => x"86", + 803 => x"82", + 804 => x"80", + 805 => x"86", + 806 => x"39", + 807 => x"53", + 808 => x"51", + 809 => x"81", + 810 => x"81", + 811 => x"3d", + 812 => x"f6", + 813 => x"08", + 814 => x"06", + 815 => x"38", + 816 => x"05", + 817 => x"3f", + 818 => x"02", + 819 => x"78", + 820 => x"88", + 821 => x"70", + 822 => x"5b", + 823 => x"88", + 824 => x"ff", + 825 => x"8c", + 826 => x"3d", + 827 => x"34", + 828 => x"05", + 829 => x"3f", + 830 => x"1a", + 831 => x"e2", + 832 => x"e4", + 833 => x"83", + 834 => x"56", + 835 => x"95", + 836 => x"51", + 837 => x"88", + 838 => x"51", + 839 => x"88", + 840 => x"ff", + 841 => x"31", + 842 => x"1b", + 843 => x"2a", + 844 => x"56", + 845 => x"55", + 846 => x"55", + 847 => x"88", + 848 => x"70", + 849 => x"88", + 850 => x"05", + 851 => x"83", + 852 => x"83", + 853 => x"83", + 854 => x"27", + 855 => x"57", + 856 => x"56", + 857 => x"80", + 858 => x"79", + 859 => x"2e", + 860 => x"90", + 861 => x"fb", + 862 => x"81", + 863 => x"90", + 864 => x"39", + 865 => x"18", + 866 => x"79", + 867 => x"06", + 868 => x"19", + 869 => x"05", + 870 => x"55", + 871 => x"1a", + 872 => x"0b", + 873 => x"0c", + 874 => x"88", + 875 => x"0d", + 876 => x"0d", + 877 => x"9f", + 878 => x"85", + 879 => x"2e", + 880 => x"80", + 881 => x"34", + 882 => x"11", + 883 => x"89", + 884 => x"57", + 885 => x"f8", + 886 => x"08", + 887 => x"80", + 888 => x"3d", + 889 => x"80", + 890 => x"02", + 891 => x"70", + 892 => x"81", + 893 => x"57", + 894 => x"85", + 895 => x"a1", + 896 => x"f5", + 897 => x"08", + 898 => x"98", + 899 => x"51", + 900 => x"88", + 901 => x"0c", + 902 => x"0c", + 903 => x"16", + 904 => x"0c", + 905 => x"04", + 906 => x"7d", + 907 => x"0b", + 908 => x"08", + 909 => x"58", + 910 => x"85", + 911 => x"2e", + 912 => x"81", + 913 => x"06", + 914 => x"74", + 915 => x"c3", + 916 => x"74", + 917 => x"86", + 918 => x"81", + 919 => x"57", + 920 => x"9c", + 921 => x"17", + 922 => x"74", + 923 => x"38", + 924 => x"80", + 925 => x"38", + 926 => x"70", + 927 => x"56", + 928 => x"c7", + 929 => x"33", + 930 => x"89", + 931 => x"81", + 932 => x"55", + 933 => x"76", + 934 => x"16", + 935 => x"39", + 936 => x"51", + 937 => x"88", + 938 => x"75", + 939 => x"38", + 940 => x"0c", + 941 => x"51", + 942 => x"88", + 943 => x"08", + 944 => x"8f", + 945 => x"1a", + 946 => x"98", + 947 => x"ff", + 948 => x"71", + 949 => x"77", + 950 => x"38", + 951 => x"54", + 952 => x"83", + 953 => x"a8", + 954 => x"78", + 955 => x"3f", + 956 => x"e5", + 957 => x"08", + 958 => x"0c", + 959 => x"7b", + 960 => x"0c", + 961 => x"2e", + 962 => x"74", + 963 => x"e2", + 964 => x"76", + 965 => x"3d", + 966 => x"3d", + 967 => x"86", + 968 => x"c0", + 969 => x"9b", + 970 => x"0b", + 971 => x"9c", + 972 => x"83", + 973 => x"94", + 974 => x"80", + 975 => x"c0", + 976 => x"9f", + 977 => x"d6", + 978 => x"b8", + 979 => x"51", + 980 => x"88", + 981 => x"a0", + 982 => x"08", + 983 => x"88", + 984 => x"3d", + 985 => x"84", + 986 => x"51", + 987 => x"88", + 988 => x"75", + 989 => x"2e", + 990 => x"15", + 991 => x"a0", + 992 => x"04", + 993 => x"39", + 994 => x"ff", + 995 => x"ff", + 996 => x"00", + 997 => x"ff", + 998 => x"4f", + 999 => x"4e", + 1000 => x"4f", + 1001 => x"00", + 1002 => x"00", + 2048 => x"80", + 2049 => x"0b", + 2050 => x"95", + 2051 => x"ff", + 2052 => x"ff", + 2053 => x"ff", + 2054 => x"ff", + 2055 => x"ff", + 2056 => x"80", + 2057 => x"0b", + 2058 => x"85", + 2059 => x"80", + 2060 => x"0b", + 2061 => x"a5", + 2062 => x"80", + 2063 => x"0b", + 2064 => x"c5", + 2065 => x"80", + 2066 => x"0b", + 2067 => x"e5", + 2068 => x"80", + 2069 => x"0b", + 2070 => x"85", + 2071 => x"80", + 2072 => x"0b", + 2073 => x"a5", + 2074 => x"80", + 2075 => x"0b", + 2076 => x"c5", + 2077 => x"80", + 2078 => x"0b", + 2079 => x"e5", + 2080 => x"80", + 2081 => x"0b", + 2082 => x"85", + 2083 => x"80", + 2084 => x"0b", + 2085 => x"a5", + 2086 => x"80", + 2087 => x"0b", + 2088 => x"c5", + 2089 => x"80", + 2090 => x"0b", + 2091 => x"e5", + 2092 => x"80", + 2093 => x"0b", + 2094 => x"85", + 2095 => x"80", + 2096 => x"0b", + 2097 => x"a5", + 2098 => x"80", + 2099 => x"0b", + 2100 => x"c5", + 2101 => x"80", + 2102 => x"0b", + 2103 => x"e5", + 2104 => x"80", + 2105 => x"0b", + 2106 => x"85", + 2107 => x"80", + 2108 => x"0b", + 2109 => x"a5", + 2110 => x"80", + 2111 => x"0b", + 2112 => x"c5", + 2113 => x"80", + 2114 => x"0b", + 2115 => x"e5", + 2116 => x"80", + 2117 => x"0b", + 2118 => x"85", + 2119 => x"80", + 2120 => x"0b", + 2121 => x"a5", + 2122 => x"80", + 2123 => x"0b", + 2124 => x"c5", + 2125 => x"80", + 2126 => x"0b", + 2127 => x"e5", + 2128 => x"80", + 2129 => x"0b", + 2130 => x"85", + 2131 => x"00", + 2132 => x"00", + 2133 => x"00", + 2134 => x"00", + 2135 => x"00", + 2136 => x"00", + 2137 => x"00", + 2138 => x"00", + 2139 => x"00", + 2140 => x"00", + 2141 => x"00", + 2142 => x"00", + 2143 => x"00", + 2144 => x"00", + 2145 => x"00", + 2146 => x"00", + 2147 => x"00", + 2148 => x"00", + 2149 => x"00", + 2150 => x"00", + 2151 => x"00", + 2152 => x"00", + 2153 => x"00", + 2154 => x"00", + 2155 => x"00", + 2156 => x"00", + 2157 => x"00", + 2158 => x"00", + 2159 => x"00", + 2160 => x"00", + 2161 => x"00", + 2162 => x"00", + 2163 => x"00", + 2164 => x"00", + 2165 => x"00", + 2166 => x"00", + 2167 => x"00", + 2168 => x"00", + 2169 => x"00", + 2170 => x"00", + 2171 => x"00", + 2172 => x"00", + 2173 => x"00", + 2174 => x"00", + 2175 => x"00", + 2176 => x"c4", + 2177 => x"93", + 2178 => x"d5", + 2179 => x"93", + 2180 => x"80", + 2181 => x"93", + 2182 => x"df", + 2183 => x"93", + 2184 => x"80", + 2185 => x"93", + 2186 => x"e0", + 2187 => x"93", + 2188 => x"80", + 2189 => x"93", + 2190 => x"e0", + 2191 => x"93", + 2192 => x"80", + 2193 => x"93", + 2194 => x"e6", + 2195 => x"93", + 2196 => x"80", + 2197 => x"93", + 2198 => x"e8", + 2199 => x"93", + 2200 => x"80", + 2201 => x"93", + 2202 => x"e0", + 2203 => x"93", + 2204 => x"80", + 2205 => x"93", + 2206 => x"e8", + 2207 => x"93", + 2208 => x"80", + 2209 => x"93", + 2210 => x"ea", + 2211 => x"93", + 2212 => x"80", + 2213 => x"93", + 2214 => x"e6", + 2215 => x"93", + 2216 => x"80", + 2217 => x"93", + 2218 => x"e6", + 2219 => x"93", + 2220 => x"80", + 2221 => x"93", + 2222 => x"e6", + 2223 => x"93", + 2224 => x"80", + 2225 => x"93", + 2226 => x"d7", + 2227 => x"93", + 2228 => x"80", + 2229 => x"93", + 2230 => x"d7", + 2231 => x"93", + 2232 => x"80", + 2233 => x"93", + 2234 => x"cf", + 2235 => x"93", + 2236 => x"80", + 2237 => x"93", + 2238 => x"d1", + 2239 => x"93", + 2240 => x"80", + 2241 => x"93", + 2242 => x"d2", + 2243 => x"93", + 2244 => x"80", + 2245 => x"93", + 2246 => x"9e", + 2247 => x"93", + 2248 => x"80", + 2249 => x"93", + 2250 => x"ad", + 2251 => x"93", + 2252 => x"80", + 2253 => x"93", + 2254 => x"a3", + 2255 => x"93", + 2256 => x"80", + 2257 => x"93", + 2258 => x"a7", + 2259 => x"93", + 2260 => x"80", + 2261 => x"93", + 2262 => x"b3", + 2263 => x"93", + 2264 => x"80", + 2265 => x"93", + 2266 => x"bd", + 2267 => x"93", + 2268 => x"80", + 2269 => x"93", + 2270 => x"ac", + 2271 => x"93", + 2272 => x"80", + 2273 => x"93", + 2274 => x"b7", + 2275 => x"93", + 2276 => x"80", + 2277 => x"93", + 2278 => x"b8", + 2279 => x"93", + 2280 => x"80", + 2281 => x"93", + 2282 => x"b9", + 2283 => x"93", + 2284 => x"80", + 2285 => x"93", + 2286 => x"c2", + 2287 => x"93", + 2288 => x"80", + 2289 => x"93", + 2290 => x"bf", + 2291 => x"93", + 2292 => x"80", + 2293 => x"93", + 2294 => x"c4", + 2295 => x"93", + 2296 => x"80", + 2297 => x"93", + 2298 => x"ba", + 2299 => x"93", + 2300 => x"80", + 2301 => x"93", + 2302 => x"c7", + 2303 => x"93", + 2304 => x"80", + 2305 => x"93", + 2306 => x"c8", + 2307 => x"93", + 2308 => x"80", + 2309 => x"93", + 2310 => x"ae", + 2311 => x"93", + 2312 => x"80", + 2313 => x"93", + 2314 => x"ae", + 2315 => x"93", + 2316 => x"80", + 2317 => x"93", + 2318 => x"af", + 2319 => x"93", + 2320 => x"80", + 2321 => x"93", + 2322 => x"ba", + 2323 => x"93", + 2324 => x"80", + 2325 => x"93", + 2326 => x"c9", + 2327 => x"93", + 2328 => x"80", + 2329 => x"93", + 2330 => x"cc", + 2331 => x"93", + 2332 => x"80", + 2333 => x"93", + 2334 => x"cf", + 2335 => x"93", + 2336 => x"80", + 2337 => x"93", + 2338 => x"9e", + 2339 => x"93", + 2340 => x"80", + 2341 => x"93", + 2342 => x"d2", + 2343 => x"93", + 2344 => x"80", + 2345 => x"93", + 2346 => x"ed", + 2347 => x"93", + 2348 => x"80", + 2349 => x"93", + 2350 => x"ef", + 2351 => x"93", + 2352 => x"80", + 2353 => x"93", + 2354 => x"f1", + 2355 => x"93", + 2356 => x"80", + 2357 => x"93", + 2358 => x"d0", + 2359 => x"93", + 2360 => x"80", + 2361 => x"93", + 2362 => x"d0", + 2363 => x"93", + 2364 => x"80", + 2365 => x"93", + 2366 => x"d3", + 2367 => x"93", + 2368 => x"80", + 2369 => x"93", + 2370 => x"df", + 2371 => x"93", + 2372 => x"80", + 2373 => x"93", + 2374 => x"b6", + 2375 => x"38", + 2376 => x"84", + 2377 => x"0b", + 2378 => x"98", + 2379 => x"80", + 2380 => x"da", + 2381 => x"82", + 2382 => x"02", + 2383 => x"0c", + 2384 => x"80", + 2385 => x"d4", + 2386 => x"08", + 2387 => x"d4", + 2388 => x"08", + 2389 => x"3f", + 2390 => x"08", + 2391 => x"c8", + 2392 => x"3d", + 2393 => x"d4", + 2394 => x"93", + 2395 => x"82", + 2396 => x"fd", + 2397 => x"53", + 2398 => x"08", + 2399 => x"52", + 2400 => x"08", + 2401 => x"51", + 2402 => x"93", + 2403 => x"82", + 2404 => x"54", + 2405 => x"82", + 2406 => x"04", + 2407 => x"08", + 2408 => x"d4", + 2409 => x"0d", + 2410 => x"93", + 2411 => x"05", + 2412 => x"82", + 2413 => x"f8", + 2414 => x"93", + 2415 => x"05", + 2416 => x"d4", + 2417 => x"08", + 2418 => x"82", + 2419 => x"fc", + 2420 => x"2e", + 2421 => x"0b", + 2422 => x"08", + 2423 => x"24", + 2424 => x"93", + 2425 => x"05", + 2426 => x"93", + 2427 => x"05", + 2428 => x"d4", + 2429 => x"08", + 2430 => x"d4", + 2431 => x"0c", + 2432 => x"82", + 2433 => x"fc", + 2434 => x"2e", + 2435 => x"82", + 2436 => x"8c", + 2437 => x"93", + 2438 => x"05", + 2439 => x"38", + 2440 => x"08", + 2441 => x"82", + 2442 => x"8c", + 2443 => x"82", + 2444 => x"88", + 2445 => x"93", + 2446 => x"05", + 2447 => x"d4", + 2448 => x"08", + 2449 => x"d4", + 2450 => x"0c", + 2451 => x"08", + 2452 => x"81", + 2453 => x"d4", + 2454 => x"0c", + 2455 => x"08", + 2456 => x"81", + 2457 => x"d4", + 2458 => x"0c", + 2459 => x"82", + 2460 => x"90", + 2461 => x"2e", + 2462 => x"93", + 2463 => x"05", + 2464 => x"93", + 2465 => x"05", + 2466 => x"39", + 2467 => x"08", + 2468 => x"70", + 2469 => x"08", + 2470 => x"51", + 2471 => x"08", + 2472 => x"82", + 2473 => x"85", + 2474 => x"93", + 2475 => x"fc", + 2476 => x"79", + 2477 => x"05", + 2478 => x"57", + 2479 => x"83", + 2480 => x"38", + 2481 => x"51", + 2482 => x"a4", + 2483 => x"52", + 2484 => x"93", + 2485 => x"70", + 2486 => x"34", + 2487 => x"71", + 2488 => x"81", + 2489 => x"74", + 2490 => x"0c", + 2491 => x"04", + 2492 => x"2b", + 2493 => x"71", + 2494 => x"51", + 2495 => x"72", + 2496 => x"72", + 2497 => x"05", + 2498 => x"71", + 2499 => x"53", + 2500 => x"70", + 2501 => x"0c", + 2502 => x"84", + 2503 => x"f0", + 2504 => x"8f", + 2505 => x"83", + 2506 => x"38", + 2507 => x"84", + 2508 => x"fc", + 2509 => x"83", + 2510 => x"70", + 2511 => x"39", + 2512 => x"77", + 2513 => x"07", + 2514 => x"54", + 2515 => x"38", + 2516 => x"08", + 2517 => x"71", + 2518 => x"80", + 2519 => x"75", + 2520 => x"33", + 2521 => x"06", + 2522 => x"80", + 2523 => x"72", + 2524 => x"75", + 2525 => x"06", + 2526 => x"12", + 2527 => x"33", + 2528 => x"06", + 2529 => x"52", + 2530 => x"72", + 2531 => x"81", + 2532 => x"81", + 2533 => x"71", + 2534 => x"c8", + 2535 => x"87", + 2536 => x"71", + 2537 => x"fb", + 2538 => x"06", + 2539 => x"82", + 2540 => x"51", + 2541 => x"97", + 2542 => x"84", + 2543 => x"54", + 2544 => x"75", + 2545 => x"38", + 2546 => x"52", + 2547 => x"80", + 2548 => x"c8", + 2549 => x"0d", + 2550 => x"0d", + 2551 => x"52", + 2552 => x"52", + 2553 => x"82", + 2554 => x"81", + 2555 => x"07", + 2556 => x"52", + 2557 => x"e8", + 2558 => x"93", + 2559 => x"3d", + 2560 => x"3d", + 2561 => x"08", + 2562 => x"55", + 2563 => x"80", + 2564 => x"33", + 2565 => x"2e", + 2566 => x"8c", + 2567 => x"70", + 2568 => x"70", + 2569 => x"38", + 2570 => x"39", + 2571 => x"80", + 2572 => x"53", + 2573 => x"83", + 2574 => x"70", + 2575 => x"2a", + 2576 => x"51", + 2577 => x"71", + 2578 => x"a0", + 2579 => x"06", + 2580 => x"72", + 2581 => x"54", + 2582 => x"0c", + 2583 => x"82", + 2584 => x"86", + 2585 => x"fc", + 2586 => x"53", + 2587 => x"2e", + 2588 => x"3d", + 2589 => x"72", + 2590 => x"3f", + 2591 => x"08", + 2592 => x"53", + 2593 => x"53", + 2594 => x"c8", + 2595 => x"0d", + 2596 => x"0d", + 2597 => x"33", + 2598 => x"5c", + 2599 => x"8b", + 2600 => x"38", + 2601 => x"ff", + 2602 => x"5b", + 2603 => x"81", + 2604 => x"1c", + 2605 => x"5b", + 2606 => x"81", + 2607 => x"1c", + 2608 => x"5b", + 2609 => x"81", + 2610 => x"1c", + 2611 => x"5b", + 2612 => x"81", + 2613 => x"1c", + 2614 => x"5b", + 2615 => x"26", + 2616 => x"8a", + 2617 => x"87", + 2618 => x"e7", + 2619 => x"38", + 2620 => x"59", + 2621 => x"58", + 2622 => x"57", + 2623 => x"56", + 2624 => x"55", + 2625 => x"54", + 2626 => x"53", + 2627 => x"81", + 2628 => x"94", + 2629 => x"c0", + 2630 => x"81", + 2631 => x"22", + 2632 => x"bc", + 2633 => x"33", + 2634 => x"b8", + 2635 => x"33", + 2636 => x"b4", + 2637 => x"33", + 2638 => x"b0", + 2639 => x"33", + 2640 => x"ac", + 2641 => x"33", + 2642 => x"a8", + 2643 => x"22", + 2644 => x"a4", + 2645 => x"22", + 2646 => x"a0", + 2647 => x"0c", + 2648 => x"82", + 2649 => x"8d", + 2650 => x"f5", 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x"81", + 2710 => x"70", + 2711 => x"0b", + 2712 => x"c0", + 2713 => x"c0", + 2714 => x"70", + 2715 => x"38", + 2716 => x"90", + 2717 => x"0c", + 2718 => x"c8", + 2719 => x"0d", + 2720 => x"0d", + 2721 => x"33", + 2722 => x"8b", + 2723 => x"54", + 2724 => x"84", + 2725 => x"2e", + 2726 => x"c0", + 2727 => x"70", + 2728 => x"2a", + 2729 => x"51", + 2730 => x"80", + 2731 => x"71", + 2732 => x"81", + 2733 => x"70", + 2734 => x"96", + 2735 => x"70", + 2736 => x"51", + 2737 => x"8d", + 2738 => x"2a", + 2739 => x"51", + 2740 => x"bc", + 2741 => x"82", + 2742 => x"51", + 2743 => x"80", + 2744 => x"2e", + 2745 => x"c0", + 2746 => x"73", + 2747 => x"3d", + 2748 => x"3d", + 2749 => x"80", + 2750 => x"56", + 2751 => x"80", + 2752 => x"70", + 2753 => x"33", + 2754 => x"8b", + 2755 => x"55", + 2756 => x"84", + 2757 => x"2e", + 2758 => x"c0", + 2759 => x"70", + 2760 => x"2a", + 2761 => x"51", + 2762 => x"80", + 2763 => x"71", + 2764 => x"81", + 2765 => x"70", + 2766 => x"96", + 2767 => x"70", + 2768 => x"51", + 2769 => x"8d", + 2770 => x"2a", + 2771 => x"51", + 2772 => x"bc", + 2773 => x"82", + 2774 => x"51", + 2775 => x"80", + 2776 => x"2e", + 2777 => x"c0", + 2778 => x"74", + 2779 => x"16", + 2780 => x"56", + 2781 => x"38", + 2782 => x"c8", + 2783 => x"0d", + 2784 => x"0d", + 2785 => x"8b", + 2786 => x"87", + 2787 => x"51", + 2788 => x"86", + 2789 => x"94", + 2790 => x"08", + 2791 => x"70", + 2792 => x"51", + 2793 => x"2e", + 2794 => x"0b", + 2795 => x"33", + 2796 => x"94", + 2797 => x"80", + 2798 => x"87", + 2799 => x"52", + 2800 => x"81", + 2801 => x"93", + 2802 => x"83", + 2803 => x"ff", + 2804 => x"0b", + 2805 => x"33", + 2806 => x"94", + 2807 => x"80", + 2808 => x"87", + 2809 => x"52", + 2810 => x"82", + 2811 => x"06", + 2812 => x"ff", + 2813 => x"2e", + 2814 => x"0b", + 2815 => x"33", + 2816 => x"94", + 2817 => x"80", + 2818 => x"87", + 2819 => x"52", + 2820 => x"98", + 2821 => x"2c", + 2822 => x"71", + 2823 => x"0c", + 2824 => x"04", + 2825 => x"87", + 2826 => x"70", + 2827 => x"2a", + 2828 => x"52", + 2829 => x"2e", + 2830 => x"82", + 2831 => x"87", + 2832 => x"08", + 2833 => x"11", + 2834 => x"a0", + 2835 => x"52", + 2836 => x"c0", + 2837 => x"71", + 2838 => x"11", + 2839 => x"90", + 2840 => x"52", + 2841 => x"c0", + 2842 => x"71", + 2843 => x"11", + 2844 => x"98", + 2845 => x"52", + 2846 => x"c0", + 2847 => x"71", + 2848 => x"11", + 2849 => x"a8", + 2850 => x"52", + 2851 => x"c0", + 2852 => x"71", + 2853 => x"08", + 2854 => x"a4", + 2855 => x"12", + 2856 => x"84", + 2857 => x"51", + 2858 => x"13", + 2859 => x"52", + 2860 => x"c0", + 2861 => x"70", + 2862 => x"51", + 2863 => x"80", + 2864 => x"81", + 2865 => x"34", + 2866 => x"c0", + 2867 => x"70", + 2868 => x"06", + 2869 => x"70", + 2870 => x"38", + 2871 => x"82", + 2872 => x"80", + 2873 => x"9e", + 2874 => x"80", + 2875 => x"51", + 2876 => x"80", + 2877 => x"81", + 2878 => x"8b", + 2879 => x"0b", + 2880 => x"88", + 2881 => x"80", + 2882 => x"52", + 2883 => x"83", + 2884 => x"71", + 2885 => x"34", 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x"33", + 2945 => x"80", + 2946 => x"d7", + 2947 => x"82", + 2948 => x"52", + 2949 => x"51", + 2950 => x"82", + 2951 => x"33", + 2952 => x"80", + 2953 => x"de", + 2954 => x"da", + 2955 => x"81", + 2956 => x"89", + 2957 => x"8b", + 2958 => x"55", + 2959 => x"38", + 2960 => x"54", + 2961 => x"93", + 2962 => x"d8", + 2963 => x"fc", + 2964 => x"54", + 2965 => x"51", + 2966 => x"82", + 2967 => x"54", + 2968 => x"88", + 2969 => x"f0", + 2970 => x"3f", + 2971 => x"33", + 2972 => x"2e", + 2973 => x"f7", + 2974 => x"a8", + 2975 => x"f7", + 2976 => x"80", + 2977 => x"81", + 2978 => x"83", + 2979 => x"8b", + 2980 => x"55", + 2981 => x"2e", + 2982 => x"15", + 2983 => x"f8", + 2984 => x"fa", + 2985 => x"fa", + 2986 => x"80", + 2987 => x"81", + 2988 => x"82", + 2989 => x"8b", + 2990 => x"55", + 2991 => x"2e", + 2992 => x"15", + 2993 => x"f8", + 2994 => x"d2", + 2995 => x"ec", + 2996 => x"3f", + 2997 => x"70", + 2998 => x"05", + 2999 => x"81", + 3000 => x"55", + 3001 => x"3f", + 3002 => x"81", + 3003 => x"88", + 3004 => x"15", + 3005 => x"f9", + 3006 => x"a2", + 3007 => x"22", + 3008 => x"f0", + 3009 => x"3f", + 3010 => x"52", + 3011 => x"51", + 3012 => x"86", + 3013 => x"ff", + 3014 => x"8e", + 3015 => x"71", + 3016 => x"38", + 3017 => x"0b", + 3018 => x"c4", + 3019 => x"08", + 3020 => x"c0", + 3021 => x"3f", + 3022 => x"fa", + 3023 => x"b2", + 3024 => x"81", + 3025 => x"f7", + 3026 => x"39", + 3027 => x"51", + 3028 => x"91", + 3029 => x"dc", + 3030 => x"3f", + 3031 => x"fa", + 3032 => x"8e", + 3033 => x"0d", + 3034 => x"80", + 3035 => x"0b", + 3036 => x"84", + 3037 => x"3d", + 3038 => x"96", + 3039 => x"52", + 3040 => x"0c", + 3041 => x"70", + 3042 => x"0c", + 3043 => x"3d", + 3044 => x"3d", + 3045 => x"96", + 3046 => x"82", + 3047 => x"52", + 3048 => x"73", + 3049 => x"8c", + 3050 => x"70", + 3051 => x"0c", + 3052 => x"83", + 3053 => x"82", + 3054 => x"87", + 3055 => x"0c", + 3056 => x"0d", + 3057 => x"33", + 3058 => x"2e", + 3059 => x"85", + 3060 => x"ed", + 3061 => x"e0", + 3062 => x"95", + 3063 => x"e0", + 3064 => x"72", + 3065 => x"e0", + 3066 => x"82", + 3067 => x"92", + 3068 => x"d8", + 3069 => x"8a", + 3070 => x"82", + 3071 => x"52", + 3072 => x"3d", + 3073 => x"3d", + 3074 => x"05", + 3075 => x"d8", + 3076 => x"93", + 3077 => x"51", + 3078 => x"72", + 3079 => x"0c", + 3080 => x"04", + 3081 => x"74", + 3082 => x"53", + 3083 => x"91", + 3084 => x"81", + 3085 => x"51", + 3086 => x"72", + 3087 => x"f1", + 3088 => x"0d", + 3089 => x"0d", + 3090 => x"d8", + 3091 => x"93", + 3092 => x"33", + 3093 => x"71", + 3094 => x"38", + 3095 => x"05", + 3096 => x"fe", + 3097 => x"33", + 3098 => x"38", + 3099 => x"d8", + 3100 => x"0d", + 3101 => x"0d", + 3102 => x"59", + 3103 => x"05", + 3104 => x"75", + 3105 => x"92", + 3106 => x"2e", + 3107 => x"51", + 3108 => x"e8", + 3109 => x"7a", + 3110 => x"5c", + 3111 => x"5a", + 3112 => x"09", + 3113 => x"38", + 3114 => x"81", + 3115 => x"57", + 3116 => x"75", + 3117 => x"81", + 3118 => x"82", + 3119 => x"05", + 3120 => x"5d", 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x"a0", + 3180 => x"3f", + 3181 => x"55", + 3182 => x"26", + 3183 => x"bc", + 3184 => x"1d", + 3185 => x"53", + 3186 => x"f5", + 3187 => x"39", + 3188 => x"39", + 3189 => x"39", + 3190 => x"39", + 3191 => x"39", + 3192 => x"dd", + 3193 => x"39", + 3194 => x"70", + 3195 => x"53", + 3196 => x"8b", + 3197 => x"1d", + 3198 => x"5d", + 3199 => x"74", + 3200 => x"09", + 3201 => x"38", + 3202 => x"71", + 3203 => x"53", + 3204 => x"84", + 3205 => x"59", + 3206 => x"80", + 3207 => x"30", + 3208 => x"80", + 3209 => x"7b", + 3210 => x"52", + 3211 => x"80", + 3212 => x"76", + 3213 => x"07", + 3214 => x"58", + 3215 => x"51", + 3216 => x"82", + 3217 => x"81", + 3218 => x"53", + 3219 => x"e5", + 3220 => x"93", + 3221 => x"89", + 3222 => x"38", + 3223 => x"70", + 3224 => x"57", + 3225 => x"80", + 3226 => x"38", + 3227 => x"81", + 3228 => x"53", + 3229 => x"05", + 3230 => x"16", + 3231 => x"74", + 3232 => x"77", + 3233 => x"07", + 3234 => x"9f", + 3235 => x"51", + 3236 => x"72", + 3237 => x"7c", + 3238 => x"81", + 3239 => x"72", + 3240 => x"38", + 3241 => x"05", + 3242 => x"ad", + 3243 => x"18", + 3244 => x"81", + 3245 => x"b0", + 3246 => x"38", + 3247 => x"81", + 3248 => x"06", + 3249 => x"a3", + 3250 => x"15", + 3251 => x"7a", + 3252 => x"7c", + 3253 => x"06", + 3254 => x"f9", + 3255 => x"8b", + 3256 => x"15", + 3257 => x"73", + 3258 => x"ff", + 3259 => x"e0", + 3260 => x"33", + 3261 => x"f9", + 3262 => x"ef", + 3263 => x"15", + 3264 => x"7a", + 3265 => x"38", + 3266 => x"b5", + 3267 => x"15", + 3268 => x"73", + 3269 => x"fa", + 3270 => x"3d", + 3271 => x"3d", + 3272 => x"70", + 3273 => x"52", + 3274 => x"73", + 3275 => x"3f", + 3276 => x"04", + 3277 => x"74", + 3278 => x"0c", + 3279 => x"05", + 3280 => x"fa", + 3281 => x"93", + 3282 => x"80", + 3283 => x"0b", + 3284 => x"0c", + 3285 => x"04", + 3286 => x"82", + 3287 => x"76", + 3288 => x"0c", + 3289 => x"05", + 3290 => x"53", + 3291 => x"72", + 3292 => x"0c", + 3293 => x"04", + 3294 => x"78", + 3295 => x"80", + 3296 => x"dc", + 3297 => x"80", + 3298 => x"39", + 3299 => x"f3", + 3300 => x"82", + 3301 => x"52", + 3302 => x"93", + 3303 => x"ff", + 3304 => x"80", + 3305 => x"73", + 3306 => x"ca", + 3307 => x"32", + 3308 => x"30", + 3309 => x"9f", + 3310 => x"25", + 3311 => x"51", + 3312 => x"2e", + 3313 => x"15", + 3314 => x"06", + 3315 => x"f1", + 3316 => x"9f", + 3317 => x"bb", + 3318 => x"52", + 3319 => x"ff", + 3320 => x"15", + 3321 => x"34", + 3322 => x"81", + 3323 => x"55", + 3324 => x"ff", + 3325 => x"17", + 3326 => x"34", + 3327 => x"c1", + 3328 => x"72", + 3329 => x"0c", + 3330 => x"04", + 3331 => x"82", + 3332 => x"75", + 3333 => x"0c", + 3334 => x"52", + 3335 => x"3f", + 3336 => x"dc", + 3337 => x"0d", + 3338 => x"0d", + 3339 => x"55", + 3340 => x"0c", + 3341 => x"33", + 3342 => x"73", + 3343 => x"81", + 3344 => x"74", + 3345 => x"75", + 3346 => x"70", + 3347 => x"73", + 3348 => x"38", + 3349 => x"09", + 3350 => x"38", + 3351 => x"11", + 3352 => x"08", + 3353 => x"54", + 3354 => x"2e", + 3355 => x"80", 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x"81", + 3415 => x"74", + 3416 => x"55", + 3417 => x"2e", + 3418 => x"ad", + 3419 => x"06", + 3420 => x"75", + 3421 => x"0c", + 3422 => x"33", + 3423 => x"73", + 3424 => x"81", + 3425 => x"38", + 3426 => x"05", + 3427 => x"08", + 3428 => x"53", + 3429 => x"2e", + 3430 => x"80", + 3431 => x"81", + 3432 => x"90", + 3433 => x"76", + 3434 => x"70", + 3435 => x"57", + 3436 => x"82", + 3437 => x"05", + 3438 => x"08", + 3439 => x"54", + 3440 => x"81", + 3441 => x"27", + 3442 => x"d0", + 3443 => x"56", + 3444 => x"73", + 3445 => x"80", + 3446 => x"14", + 3447 => x"72", + 3448 => x"e8", + 3449 => x"80", + 3450 => x"39", + 3451 => x"dc", + 3452 => x"80", + 3453 => x"27", + 3454 => x"80", + 3455 => x"89", + 3456 => x"70", + 3457 => x"55", + 3458 => x"70", + 3459 => x"55", + 3460 => x"27", + 3461 => x"14", + 3462 => x"06", + 3463 => x"74", + 3464 => x"73", + 3465 => x"38", + 3466 => x"14", + 3467 => x"05", + 3468 => x"08", + 3469 => x"54", + 3470 => x"26", + 3471 => x"77", + 3472 => x"38", + 3473 => x"75", + 3474 => x"56", + 3475 => x"c8", + 3476 => x"0d", + 3477 => x"0d", + 3478 => x"33", + 3479 => x"70", + 3480 => x"38", + 3481 => x"11", + 3482 => x"82", + 3483 => x"83", + 3484 => x"fd", + 3485 => x"97", + 3486 => x"84", + 3487 => x"33", + 3488 => x"51", + 3489 => x"80", + 3490 => x"90", + 3491 => x"92", + 3492 => x"88", + 3493 => x"2e", + 3494 => x"88", + 3495 => x"0c", + 3496 => x"87", + 3497 => x"05", + 3498 => x"0c", + 3499 => x"c0", + 3500 => x"70", + 3501 => x"98", + 3502 => x"08", + 3503 => x"51", + 3504 => x"2e", + 3505 => x"08", + 3506 => x"38", + 3507 => x"87", + 3508 => x"05", + 3509 => x"80", + 3510 => x"51", + 3511 => x"87", + 3512 => x"08", + 3513 => x"2e", + 3514 => x"82", + 3515 => x"34", + 3516 => x"13", + 3517 => x"82", + 3518 => x"85", + 3519 => x"f2", + 3520 => x"63", + 3521 => x"05", + 3522 => x"33", + 3523 => x"58", + 3524 => x"5b", + 3525 => x"82", + 3526 => x"81", + 3527 => x"52", + 3528 => x"38", + 3529 => x"5d", + 3530 => x"8c", + 3531 => x"87", + 3532 => x"11", + 3533 => x"84", + 3534 => x"5c", + 3535 => x"85", + 3536 => x"c0", + 3537 => x"7c", + 3538 => x"84", + 3539 => x"08", + 3540 => x"70", + 3541 => x"53", + 3542 => x"2e", + 3543 => x"08", + 3544 => x"70", + 3545 => x"34", + 3546 => x"73", + 3547 => x"71", + 3548 => x"38", + 3549 => x"71", + 3550 => x"08", + 3551 => x"2e", + 3552 => x"84", + 3553 => x"38", + 3554 => x"87", + 3555 => x"1e", + 3556 => x"70", + 3557 => x"52", + 3558 => x"ff", + 3559 => x"39", + 3560 => x"81", + 3561 => x"ff", + 3562 => x"5c", + 3563 => x"90", + 3564 => x"80", + 3565 => x"71", + 3566 => x"7d", + 3567 => x"38", + 3568 => x"80", + 3569 => x"80", + 3570 => x"81", + 3571 => x"73", + 3572 => x"0c", + 3573 => x"04", + 3574 => x"60", + 3575 => x"8c", + 3576 => x"33", + 3577 => x"57", + 3578 => x"5a", + 3579 => x"82", + 3580 => x"81", + 3581 => x"52", + 3582 => x"38", + 3583 => x"c0", + 3584 => x"84", + 3585 => x"92", + 3586 => x"c0", + 3587 => x"72", + 3588 => x"5a", + 3589 => x"0c", + 3590 => x"80", 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x"81", + 3650 => x"80", + 3651 => x"84", + 3652 => x"93", + 3653 => x"3d", + 3654 => x"3d", + 3655 => x"33", + 3656 => x"70", + 3657 => x"07", + 3658 => x"0c", + 3659 => x"83", + 3660 => x"fd", + 3661 => x"83", + 3662 => x"12", + 3663 => x"2b", + 3664 => x"07", + 3665 => x"71", + 3666 => x"71", + 3667 => x"82", + 3668 => x"51", + 3669 => x"52", + 3670 => x"04", + 3671 => x"73", + 3672 => x"92", + 3673 => x"52", + 3674 => x"81", + 3675 => x"70", + 3676 => x"70", + 3677 => x"3d", + 3678 => x"3d", + 3679 => x"52", + 3680 => x"70", + 3681 => x"34", + 3682 => x"51", + 3683 => x"81", + 3684 => x"70", + 3685 => x"70", + 3686 => x"05", + 3687 => x"88", + 3688 => x"72", + 3689 => x"0d", + 3690 => x"0d", + 3691 => x"54", + 3692 => x"80", + 3693 => x"71", + 3694 => x"53", + 3695 => x"81", + 3696 => x"ff", + 3697 => x"ef", + 3698 => x"0d", + 3699 => x"0d", + 3700 => x"54", + 3701 => x"72", + 3702 => x"54", + 3703 => x"51", + 3704 => x"84", + 3705 => x"fc", + 3706 => x"77", + 3707 => x"53", + 3708 => x"05", + 3709 => x"70", + 3710 => x"33", + 3711 => x"ff", + 3712 => x"52", + 3713 => x"2e", + 3714 => x"80", + 3715 => x"71", + 3716 => x"0c", + 3717 => x"04", + 3718 => x"74", + 3719 => x"53", + 3720 => x"80", + 3721 => x"70", + 3722 => x"38", + 3723 => x"33", + 3724 => x"80", + 3725 => x"70", + 3726 => x"81", + 3727 => x"71", + 3728 => x"c8", + 3729 => x"0d", + 3730 => x"82", + 3731 => x"04", + 3732 => x"93", + 3733 => x"f9", + 3734 => x"56", + 3735 => x"17", + 3736 => x"74", + 3737 => x"d7", + 3738 => x"b0", + 3739 => x"b4", + 3740 => x"81", + 3741 => x"57", + 3742 => x"82", + 3743 => x"78", + 3744 => x"06", + 3745 => x"93", + 3746 => x"17", + 3747 => x"08", + 3748 => x"31", + 3749 => x"17", + 3750 => x"38", + 3751 => x"55", + 3752 => x"09", + 3753 => x"38", + 3754 => x"16", + 3755 => x"08", + 3756 => x"52", + 3757 => x"51", + 3758 => x"83", + 3759 => x"77", + 3760 => x"0c", + 3761 => x"04", + 3762 => x"78", + 3763 => x"80", + 3764 => x"08", + 3765 => x"38", + 3766 => x"fb", + 3767 => x"c8", + 3768 => x"93", + 3769 => x"38", + 3770 => x"53", + 3771 => x"81", + 3772 => x"f8", + 3773 => x"93", + 3774 => x"2e", + 3775 => x"55", + 3776 => x"b0", + 3777 => x"82", + 3778 => x"88", + 3779 => x"f8", + 3780 => x"70", + 3781 => x"bf", + 3782 => x"c8", + 3783 => x"93", + 3784 => x"91", + 3785 => x"55", + 3786 => x"09", + 3787 => x"f0", + 3788 => x"33", + 3789 => x"2e", + 3790 => x"80", + 3791 => x"80", + 3792 => x"c8", + 3793 => x"17", + 3794 => x"fd", + 3795 => x"d4", + 3796 => x"b2", + 3797 => x"84", + 3798 => x"85", + 3799 => x"75", + 3800 => x"3f", + 3801 => x"e4", + 3802 => x"98", + 3803 => x"8a", + 3804 => x"08", + 3805 => x"17", + 3806 => x"3f", + 3807 => x"52", + 3808 => x"51", + 3809 => x"a0", + 3810 => x"05", + 3811 => x"0c", + 3812 => x"75", + 3813 => x"33", + 3814 => x"3f", + 3815 => x"34", + 3816 => x"52", + 3817 => x"51", + 3818 => x"82", + 3819 => x"80", + 3820 => x"81", + 3821 => x"93", + 3822 => x"3d", + 3823 => x"3d", + 3824 => x"1a", + 3825 => x"fe", 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x"08", + 3885 => x"51", + 3886 => x"82", + 3887 => x"9b", + 3888 => x"2b", + 3889 => x"74", + 3890 => x"51", + 3891 => x"82", + 3892 => x"f0", + 3893 => x"83", + 3894 => x"75", + 3895 => x"0c", + 3896 => x"04", + 3897 => x"7b", + 3898 => x"55", + 3899 => x"81", + 3900 => x"af", + 3901 => x"16", + 3902 => x"a7", + 3903 => x"53", + 3904 => x"81", + 3905 => x"77", + 3906 => x"72", + 3907 => x"38", + 3908 => x"72", + 3909 => x"c9", + 3910 => x"39", + 3911 => x"14", + 3912 => x"a4", + 3913 => x"53", + 3914 => x"fb", + 3915 => x"93", + 3916 => x"82", + 3917 => x"81", + 3918 => x"83", + 3919 => x"b4", + 3920 => x"76", + 3921 => x"5b", + 3922 => x"57", + 3923 => x"8f", + 3924 => x"2b", + 3925 => x"78", + 3926 => x"71", + 3927 => x"76", + 3928 => x"0b", + 3929 => x"78", + 3930 => x"16", + 3931 => x"74", + 3932 => x"3f", + 3933 => x"08", + 3934 => x"c8", + 3935 => x"38", + 3936 => x"06", + 3937 => x"75", + 3938 => x"84", + 3939 => x"51", + 3940 => x"38", + 3941 => x"78", + 3942 => x"06", + 3943 => x"06", + 3944 => x"78", + 3945 => x"83", + 3946 => x"f7", + 3947 => x"2a", + 3948 => x"05", + 3949 => x"fa", + 3950 => x"93", + 3951 => x"82", + 3952 => x"80", + 3953 => x"83", + 3954 => x"52", + 3955 => x"ff", + 3956 => x"b4", + 3957 => x"84", + 3958 => x"83", + 3959 => x"c3", + 3960 => x"2a", + 3961 => x"05", + 3962 => x"f9", + 3963 => x"93", + 3964 => x"82", + 3965 => x"ab", + 3966 => x"0a", + 3967 => x"2b", + 3968 => x"76", + 3969 => x"70", + 3970 => x"56", + 3971 => x"82", + 3972 => x"8f", + 3973 => x"07", + 3974 => x"f6", + 3975 => x"0b", + 3976 => x"76", + 3977 => x"0c", + 3978 => x"04", + 3979 => x"79", + 3980 => x"08", + 3981 => x"57", + 3982 => x"88", + 3983 => x"08", + 3984 => x"38", + 3985 => x"8e", + 3986 => x"2e", + 3987 => x"53", + 3988 => x"51", + 3989 => x"82", + 3990 => x"56", + 3991 => x"08", + 3992 => x"93", + 3993 => x"80", + 3994 => x"56", + 3995 => x"82", + 3996 => x"56", + 3997 => x"73", + 3998 => x"fa", + 3999 => x"93", + 4000 => x"82", + 4001 => x"80", + 4002 => x"38", + 4003 => x"08", + 4004 => x"38", + 4005 => x"08", + 4006 => x"38", + 4007 => x"52", + 4008 => x"c0", + 4009 => x"c8", + 4010 => x"98", + 4011 => x"05", + 4012 => x"08", + 4013 => x"38", + 4014 => x"81", + 4015 => x"0c", + 4016 => x"81", + 4017 => x"84", + 4018 => x"54", + 4019 => x"76", + 4020 => x"38", + 4021 => x"82", + 4022 => x"89", + 4023 => x"f5", + 4024 => x"7f", + 4025 => x"5c", + 4026 => x"38", + 4027 => x"58", + 4028 => x"88", + 4029 => x"08", + 4030 => x"38", + 4031 => x"39", + 4032 => x"51", + 4033 => x"81", + 4034 => x"93", + 4035 => x"82", + 4036 => x"93", + 4037 => x"82", + 4038 => x"ff", + 4039 => x"38", + 4040 => x"08", + 4041 => x"08", + 4042 => x"08", + 4043 => x"38", + 4044 => x"55", + 4045 => x"75", + 4046 => x"38", + 4047 => x"7b", + 4048 => x"06", + 4049 => x"81", + 4050 => x"19", + 4051 => x"83", + 4052 => x"76", + 4053 => x"f9", + 4054 => x"93", + 4055 => x"80", + 4056 => x"c8", + 4057 => x"09", + 4058 => x"38", + 4059 => x"08", + 4060 => x"32", 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x"73", + 4120 => x"94", + 4121 => x"75", + 4122 => x"38", + 4123 => x"55", + 4124 => x"55", + 4125 => x"57", + 4126 => x"82", + 4127 => x"8d", + 4128 => x"f7", + 4129 => x"70", + 4130 => x"cb", + 4131 => x"82", + 4132 => x"80", + 4133 => x"52", + 4134 => x"a2", + 4135 => x"c8", + 4136 => x"c8", + 4137 => x"0c", + 4138 => x"53", + 4139 => x"17", + 4140 => x"f2", + 4141 => x"59", + 4142 => x"56", + 4143 => x"16", + 4144 => x"22", + 4145 => x"27", + 4146 => x"54", + 4147 => x"78", + 4148 => x"33", + 4149 => x"3f", + 4150 => x"08", + 4151 => x"38", + 4152 => x"18", + 4153 => x"74", + 4154 => x"38", + 4155 => x"55", + 4156 => x"c8", + 4157 => x"0d", + 4158 => x"0d", + 4159 => x"08", + 4160 => x"74", + 4161 => x"26", + 4162 => x"9f", + 4163 => x"80", + 4164 => x"82", + 4165 => x"39", + 4166 => x"0c", + 4167 => x"54", + 4168 => x"75", + 4169 => x"73", + 4170 => x"a8", + 4171 => x"73", + 4172 => x"85", + 4173 => x"0b", + 4174 => x"5a", + 4175 => x"27", + 4176 => x"a8", + 4177 => x"18", + 4178 => x"39", + 4179 => x"70", + 4180 => x"58", + 4181 => x"b6", + 4182 => x"76", + 4183 => x"3f", + 4184 => x"08", + 4185 => x"c8", + 4186 => x"bf", + 4187 => x"82", + 4188 => x"27", + 4189 => x"16", + 4190 => x"c8", + 4191 => x"38", + 4192 => x"c1", + 4193 => x"31", + 4194 => x"27", + 4195 => x"52", + 4196 => x"aa", + 4197 => x"c8", + 4198 => x"0c", + 4199 => x"0c", + 4200 => x"17", + 4201 => x"9d", + 4202 => x"81", + 4203 => x"74", + 4204 => x"18", + 4205 => x"18", + 4206 => x"ff", + 4207 => x"05", + 4208 => x"80", + 4209 => x"93", + 4210 => x"3d", + 4211 => x"3d", + 4212 => x"71", + 4213 => x"08", + 4214 => x"59", + 4215 => x"80", + 4216 => x"86", + 4217 => x"98", + 4218 => x"53", + 4219 => x"80", + 4220 => x"38", + 4221 => x"06", + 4222 => x"c1", + 4223 => x"08", + 4224 => x"16", + 4225 => x"08", + 4226 => x"85", + 4227 => x"22", + 4228 => x"73", + 4229 => x"38", + 4230 => x"0c", + 4231 => x"ad", + 4232 => x"22", + 4233 => x"89", + 4234 => x"53", + 4235 => x"38", + 4236 => x"52", + 4237 => x"b0", + 4238 => x"c8", + 4239 => x"53", + 4240 => x"93", + 4241 => x"81", + 4242 => x"53", + 4243 => x"08", + 4244 => x"f9", + 4245 => x"08", + 4246 => x"08", + 4247 => x"38", + 4248 => x"77", + 4249 => x"84", + 4250 => x"39", + 4251 => x"52", + 4252 => x"eb", + 4253 => x"c8", + 4254 => x"53", + 4255 => x"08", + 4256 => x"c9", + 4257 => x"82", + 4258 => x"81", + 4259 => x"81", + 4260 => x"c8", + 4261 => x"b5", + 4262 => x"c8", + 4263 => x"51", + 4264 => x"81", + 4265 => x"c8", + 4266 => x"73", + 4267 => x"73", + 4268 => x"f2", + 4269 => x"93", + 4270 => x"16", + 4271 => x"16", + 4272 => x"ff", + 4273 => x"05", + 4274 => x"80", + 4275 => x"93", + 4276 => x"3d", + 4277 => x"3d", + 4278 => x"71", + 4279 => x"56", + 4280 => x"51", + 4281 => x"82", + 4282 => x"54", + 4283 => x"08", + 4284 => x"82", + 4285 => x"57", + 4286 => x"52", + 4287 => x"c8", + 4288 => x"c8", + 4289 => x"93", + 4290 => x"c7", + 4291 => x"c8", + 4292 => x"08", + 4293 => x"54", + 4294 => x"e5", + 4295 => x"06", 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x"70", + 4355 => x"81", + 4356 => x"51", + 4357 => x"86", + 4358 => x"81", + 4359 => x"30", + 4360 => x"70", + 4361 => x"06", + 4362 => x"51", + 4363 => x"73", + 4364 => x"38", + 4365 => x"96", + 4366 => x"df", + 4367 => x"72", + 4368 => x"81", + 4369 => x"81", + 4370 => x"2e", + 4371 => x"52", + 4372 => x"fa", + 4373 => x"c8", + 4374 => x"93", + 4375 => x"38", + 4376 => x"fe", + 4377 => x"80", + 4378 => x"80", + 4379 => x"0c", + 4380 => x"c8", + 4381 => x"0d", + 4382 => x"0d", + 4383 => x"59", + 4384 => x"75", + 4385 => x"3f", + 4386 => x"08", + 4387 => x"c8", + 4388 => x"38", + 4389 => x"57", + 4390 => x"98", + 4391 => x"77", + 4392 => x"3f", + 4393 => x"08", + 4394 => x"c8", + 4395 => x"38", + 4396 => x"70", + 4397 => x"73", + 4398 => x"38", + 4399 => x"8b", + 4400 => x"06", + 4401 => x"86", + 4402 => x"15", + 4403 => x"2a", + 4404 => x"51", + 4405 => x"93", + 4406 => x"a0", + 4407 => x"51", + 4408 => x"82", + 4409 => x"80", + 4410 => x"80", + 4411 => x"f9", + 4412 => x"93", + 4413 => x"82", + 4414 => x"80", + 4415 => x"38", + 4416 => x"82", + 4417 => x"8a", + 4418 => x"fb", + 4419 => x"70", + 4420 => x"81", + 4421 => x"fb", + 4422 => x"93", + 4423 => x"82", + 4424 => x"b4", + 4425 => x"08", + 4426 => x"eb", + 4427 => x"93", + 4428 => x"82", + 4429 => x"a0", + 4430 => x"82", + 4431 => x"52", + 4432 => x"51", + 4433 => x"8b", + 4434 => x"52", + 4435 => x"51", + 4436 => x"81", + 4437 => x"34", + 4438 => x"c8", + 4439 => x"0d", + 4440 => x"0d", + 4441 => x"98", + 4442 => x"70", + 4443 => x"ea", + 4444 => x"93", + 4445 => x"82", + 4446 => x"8d", + 4447 => x"08", + 4448 => x"34", + 4449 => x"16", + 4450 => x"93", + 4451 => x"3d", + 4452 => x"3d", + 4453 => x"57", + 4454 => x"89", + 4455 => x"17", + 4456 => x"81", + 4457 => x"70", + 4458 => x"17", + 4459 => x"33", + 4460 => x"54", + 4461 => x"2e", + 4462 => x"85", + 4463 => x"06", + 4464 => x"e5", + 4465 => x"2e", + 4466 => x"8e", + 4467 => x"88", + 4468 => x"0b", + 4469 => x"81", + 4470 => x"15", + 4471 => x"72", + 4472 => x"81", + 4473 => x"74", + 4474 => x"75", + 4475 => x"52", + 4476 => x"13", + 4477 => x"08", + 4478 => x"33", + 4479 => x"9c", + 4480 => x"05", + 4481 => x"3f", + 4482 => x"08", + 4483 => x"17", + 4484 => x"51", + 4485 => x"82", + 4486 => x"86", + 4487 => x"17", + 4488 => x"51", + 4489 => x"82", + 4490 => x"84", + 4491 => x"3d", + 4492 => x"3d", + 4493 => x"08", + 4494 => x"5d", + 4495 => x"53", + 4496 => x"51", + 4497 => x"80", + 4498 => x"88", + 4499 => x"5a", + 4500 => x"09", + 4501 => x"df", + 4502 => x"70", + 4503 => x"71", + 4504 => x"30", + 4505 => x"73", + 4506 => x"51", + 4507 => x"57", + 4508 => x"38", + 4509 => x"75", + 4510 => x"18", + 4511 => x"75", + 4512 => x"30", + 4513 => x"32", + 4514 => x"73", + 4515 => x"53", + 4516 => x"55", + 4517 => x"89", + 4518 => x"75", + 4519 => x"e4", + 4520 => x"7c", + 4521 => x"a0", + 4522 => x"38", + 4523 => x"8b", + 4524 => x"54", + 4525 => x"78", + 4526 => x"81", + 4527 => x"54", + 4528 => x"82", + 4529 => x"af", + 4530 => x"77", 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x"54", + 4590 => x"89", + 4591 => x"70", + 4592 => x"57", + 4593 => x"54", + 4594 => x"81", + 4595 => x"e7", + 4596 => x"7c", + 4597 => x"77", + 4598 => x"38", + 4599 => x"73", + 4600 => x"09", + 4601 => x"38", + 4602 => x"84", + 4603 => x"27", + 4604 => x"39", + 4605 => x"39", + 4606 => x"39", + 4607 => x"8b", + 4608 => x"54", + 4609 => x"c8", + 4610 => x"0d", + 4611 => x"0d", + 4612 => x"58", + 4613 => x"70", + 4614 => x"55", + 4615 => x"83", + 4616 => x"80", + 4617 => x"51", + 4618 => x"80", + 4619 => x"38", + 4620 => x"74", + 4621 => x"80", + 4622 => x"94", + 4623 => x"17", + 4624 => x"81", + 4625 => x"7a", + 4626 => x"54", + 4627 => x"2e", + 4628 => x"83", + 4629 => x"80", + 4630 => x"51", + 4631 => x"80", + 4632 => x"81", + 4633 => x"81", + 4634 => x"07", + 4635 => x"38", + 4636 => x"17", + 4637 => x"33", + 4638 => x"9f", + 4639 => x"ff", + 4640 => x"17", + 4641 => x"75", + 4642 => x"3f", + 4643 => x"08", + 4644 => x"39", + 4645 => x"a5", + 4646 => x"84", + 4647 => x"51", + 4648 => x"82", + 4649 => x"55", + 4650 => x"08", + 4651 => x"75", + 4652 => x"3f", + 4653 => x"08", + 4654 => x"55", + 4655 => x"c8", + 4656 => x"80", + 4657 => x"93", + 4658 => x"2e", + 4659 => x"80", + 4660 => x"85", + 4661 => x"06", + 4662 => x"80", + 4663 => x"73", + 4664 => x"81", + 4665 => x"72", + 4666 => x"ad", + 4667 => x"0b", + 4668 => x"80", + 4669 => x"39", + 4670 => x"70", + 4671 => x"53", + 4672 => x"85", + 4673 => x"73", + 4674 => x"81", + 4675 => x"72", + 4676 => x"16", + 4677 => x"2a", + 4678 => x"51", + 4679 => x"80", + 4680 => x"38", + 4681 => x"83", + 4682 => x"b4", + 4683 => x"51", + 4684 => x"82", + 4685 => x"88", + 4686 => x"dd", + 4687 => x"93", + 4688 => x"3d", + 4689 => x"3d", + 4690 => x"ff", + 4691 => x"72", + 4692 => x"5a", + 4693 => x"81", + 4694 => x"70", + 4695 => x"33", + 4696 => x"70", + 4697 => x"26", + 4698 => x"06", + 4699 => x"53", + 4700 => x"72", + 4701 => x"81", + 4702 => x"38", + 4703 => x"11", + 4704 => x"89", + 4705 => x"82", + 4706 => x"ff", + 4707 => x"51", + 4708 => x"77", + 4709 => x"38", + 4710 => x"fb", + 4711 => x"77", + 4712 => x"70", + 4713 => x"57", + 4714 => x"70", + 4715 => x"33", + 4716 => x"05", + 4717 => x"9f", + 4718 => x"54", + 4719 => x"89", + 4720 => x"70", + 4721 => x"55", + 4722 => x"13", + 4723 => x"26", + 4724 => x"13", + 4725 => x"06", + 4726 => x"30", + 4727 => x"70", + 4728 => x"07", + 4729 => x"9f", + 4730 => x"55", + 4731 => x"ff", + 4732 => x"30", + 4733 => x"70", + 4734 => x"07", + 4735 => x"9f", + 4736 => x"55", + 4737 => x"80", + 4738 => x"81", + 4739 => x"78", + 4740 => x"38", + 4741 => x"83", + 4742 => x"77", + 4743 => x"5a", + 4744 => x"39", + 4745 => x"33", + 4746 => x"93", + 4747 => x"3d", + 4748 => x"3d", + 4749 => x"80", + 4750 => x"34", + 4751 => x"17", + 4752 => x"75", + 4753 => x"3f", + 4754 => x"93", + 4755 => x"84", + 4756 => x"16", + 4757 => x"3f", + 4758 => x"08", + 4759 => x"06", + 4760 => x"73", + 4761 => x"2e", + 4762 => x"80", + 4763 => x"0b", + 4764 => x"55", + 4765 => x"e9", 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x"51", + 4825 => x"82", + 4826 => x"81", + 4827 => x"81", + 4828 => x"83", + 4829 => x"a8", + 4830 => x"2e", + 4831 => x"82", + 4832 => x"06", + 4833 => x"56", + 4834 => x"38", + 4835 => x"75", + 4836 => x"9e", + 4837 => x"c8", + 4838 => x"06", + 4839 => x"2e", + 4840 => x"80", + 4841 => x"54", + 4842 => x"15", + 4843 => x"10", + 4844 => x"05", + 4845 => x"33", + 4846 => x"80", + 4847 => x"2e", + 4848 => x"fa", + 4849 => x"eb", + 4850 => x"c8", + 4851 => x"78", + 4852 => x"54", + 4853 => x"d0", + 4854 => x"8f", + 4855 => x"10", + 4856 => x"08", + 4857 => x"57", + 4858 => x"90", + 4859 => x"74", + 4860 => x"3f", + 4861 => x"08", + 4862 => x"57", + 4863 => x"89", + 4864 => x"54", + 4865 => x"d3", + 4866 => x"76", + 4867 => x"90", + 4868 => x"76", + 4869 => x"88", + 4870 => x"51", + 4871 => x"82", + 4872 => x"83", + 4873 => x"53", + 4874 => x"84", + 4875 => x"81", + 4876 => x"38", + 4877 => x"51", + 4878 => x"82", + 4879 => x"83", + 4880 => x"54", + 4881 => x"80", + 4882 => x"d9", + 4883 => x"93", + 4884 => x"73", + 4885 => x"80", + 4886 => x"82", + 4887 => x"c4", + 4888 => x"05", + 4889 => x"72", + 4890 => x"b4", + 4891 => x"33", + 4892 => x"80", + 4893 => x"52", + 4894 => x"8a", + 4895 => x"83", + 4896 => x"53", + 4897 => x"8b", + 4898 => x"73", + 4899 => x"80", + 4900 => x"8d", + 4901 => x"39", + 4902 => x"51", + 4903 => x"82", + 4904 => x"88", + 4905 => x"93", + 4906 => x"ff", + 4907 => x"06", + 4908 => x"72", + 4909 => x"80", + 4910 => x"d8", + 4911 => x"93", + 4912 => x"ff", + 4913 => x"72", + 4914 => x"d4", + 4915 => x"e3", + 4916 => x"c8", + 4917 => x"c2", + 4918 => x"be", + 4919 => x"c8", + 4920 => x"ff", + 4921 => x"56", + 4922 => x"83", + 4923 => x"15", + 4924 => x"71", + 4925 => x"59", + 4926 => x"77", + 4927 => x"a0", + 4928 => x"22", + 4929 => x"31", + 4930 => x"ab", + 4931 => x"c8", + 4932 => x"56", + 4933 => x"08", + 4934 => x"84", + 4935 => x"82", + 4936 => x"80", + 4937 => x"f5", + 4938 => x"83", + 4939 => x"ff", + 4940 => x"38", + 4941 => x"9f", + 4942 => x"38", + 4943 => x"56", + 4944 => x"82", + 4945 => x"13", + 4946 => x"79", + 4947 => x"79", + 4948 => x"0c", + 4949 => x"16", + 4950 => x"2e", + 4951 => x"b7", + 4952 => x"15", + 4953 => x"3f", + 4954 => x"08", + 4955 => x"06", + 4956 => x"72", + 4957 => x"88", + 4958 => x"8d", + 4959 => x"a0", + 4960 => x"15", + 4961 => x"3f", + 4962 => x"08", + 4963 => x"98", + 4964 => x"2b", + 4965 => x"88", + 4966 => x"8d", + 4967 => x"2e", + 4968 => x"a4", + 4969 => x"a8", + 4970 => x"82", + 4971 => x"06", + 4972 => x"15", + 4973 => x"94", + 4974 => x"08", + 4975 => x"08", + 4976 => x"2a", + 4977 => x"81", + 4978 => x"53", + 4979 => x"89", + 4980 => x"56", + 4981 => x"08", + 4982 => x"38", + 4983 => x"16", + 4984 => x"8c", + 4985 => x"80", + 4986 => x"34", + 4987 => x"09", + 4988 => x"92", + 4989 => x"15", + 4990 => x"3f", + 4991 => x"08", + 4992 => x"06", + 4993 => x"2e", + 4994 => x"80", + 4995 => x"1a", + 4996 => x"d9", + 4997 => x"93", + 4998 => x"ea", + 4999 => x"c8", + 5000 => x"34", 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x"fc", + 5060 => x"f4", + 5061 => x"93", + 5062 => x"8b", + 5063 => x"82", + 5064 => x"24", + 5065 => x"82", + 5066 => x"10", + 5067 => x"e4", + 5068 => x"51", + 5069 => x"2e", + 5070 => x"74", + 5071 => x"2e", + 5072 => x"54", + 5073 => x"74", + 5074 => x"93", + 5075 => x"71", + 5076 => x"54", + 5077 => x"92", + 5078 => x"89", + 5079 => x"84", + 5080 => x"f9", + 5081 => x"c8", + 5082 => x"82", + 5083 => x"88", + 5084 => x"eb", + 5085 => x"02", + 5086 => x"e7", + 5087 => x"58", + 5088 => x"80", + 5089 => x"38", + 5090 => x"70", + 5091 => x"d0", + 5092 => x"3d", + 5093 => x"57", + 5094 => x"82", + 5095 => x"56", + 5096 => x"08", + 5097 => x"7a", + 5098 => x"97", + 5099 => x"51", + 5100 => x"82", + 5101 => x"56", + 5102 => x"08", + 5103 => x"80", + 5104 => x"70", + 5105 => x"59", + 5106 => x"83", + 5107 => x"76", + 5108 => x"74", + 5109 => x"c3", + 5110 => x"2e", + 5111 => x"84", + 5112 => x"06", + 5113 => x"3d", + 5114 => x"ea", + 5115 => x"93", + 5116 => x"76", + 5117 => x"a0", + 5118 => x"05", + 5119 => x"55", + 5120 => x"85", + 5121 => x"90", + 5122 => x"2a", + 5123 => x"51", + 5124 => x"2e", + 5125 => x"56", + 5126 => x"38", + 5127 => x"70", + 5128 => x"55", + 5129 => x"81", + 5130 => x"52", + 5131 => x"b6", + 5132 => x"c8", + 5133 => x"88", + 5134 => x"62", + 5135 => x"d2", + 5136 => x"55", + 5137 => x"16", + 5138 => x"62", + 5139 => x"e6", + 5140 => x"52", + 5141 => x"51", + 5142 => x"7a", + 5143 => x"83", + 5144 => x"80", + 5145 => x"38", + 5146 => x"08", + 5147 => x"54", + 5148 => x"05", + 5149 => x"db", + 5150 => x"93", + 5151 => x"82", + 5152 => x"82", + 5153 => x"52", + 5154 => x"bc", + 5155 => x"c8", + 5156 => x"1b", + 5157 => x"56", + 5158 => x"75", + 5159 => x"02", + 5160 => x"70", + 5161 => x"81", + 5162 => x"59", + 5163 => x"85", + 5164 => x"9c", + 5165 => x"2a", + 5166 => x"51", + 5167 => x"2e", + 5168 => x"b2", + 5169 => x"06", + 5170 => x"2e", + 5171 => x"56", + 5172 => x"38", + 5173 => x"70", + 5174 => x"55", + 5175 => x"86", + 5176 => x"c0", + 5177 => x"b0", + 5178 => x"1a", + 5179 => x"1a", + 5180 => x"81", + 5181 => x"52", + 5182 => x"ea", + 5183 => x"c8", + 5184 => x"0c", + 5185 => x"51", + 5186 => x"82", + 5187 => x"8c", + 5188 => x"78", + 5189 => x"22", + 5190 => x"76", + 5191 => x"75", + 5192 => x"75", + 5193 => x"75", + 5194 => x"84", + 5195 => x"52", + 5196 => x"d1", + 5197 => x"85", + 5198 => x"06", + 5199 => x"80", + 5200 => x"38", + 5201 => x"80", + 5202 => x"38", + 5203 => x"94", + 5204 => x"8a", + 5205 => x"89", + 5206 => x"08", + 5207 => x"5d", + 5208 => x"55", + 5209 => x"52", + 5210 => x"fc", + 5211 => x"c8", + 5212 => x"93", + 5213 => x"26", + 5214 => x"56", + 5215 => x"09", + 5216 => x"38", + 5217 => x"7a", + 5218 => x"30", + 5219 => x"80", + 5220 => x"7d", + 5221 => x"51", + 5222 => x"38", + 5223 => x"0c", + 5224 => x"38", + 5225 => x"06", + 5226 => x"2e", + 5227 => x"52", + 5228 => x"8a", + 5229 => x"c8", + 5230 => x"82", + 5231 => x"78", + 5232 => x"93", + 5233 => x"70", + 5234 => x"55", + 5235 => x"53", + 5236 => x"7a", + 5237 => x"52", + 5238 => x"3f", + 5239 => x"08", + 5240 => x"38", + 5241 => x"80", + 5242 => x"80", + 5243 => x"55", + 5244 => x"c8", + 5245 => x"0d", + 5246 => x"0d", + 5247 => x"63", + 5248 => x"57", + 5249 => x"8f", + 5250 => x"52", + 5251 => x"99", + 5252 => x"c8", + 5253 => x"93", + 5254 => x"38", + 5255 => x"55", + 5256 => x"86", + 5257 => x"83", + 5258 => x"17", + 5259 => x"55", + 5260 => x"80", + 5261 => x"38", + 5262 => x"0b", + 5263 => x"82", + 5264 => x"39", + 5265 => x"18", + 5266 => x"83", + 5267 => x"0b", + 5268 => x"82", + 5269 => x"39", + 5270 => x"18", + 5271 => x"82", + 5272 => x"0b", + 5273 => x"81", + 5274 => x"39", + 5275 => x"18", + 5276 => x"82", + 5277 => x"17", + 5278 => x"08", + 5279 => x"79", + 5280 => x"74", + 5281 => x"2e", + 5282 => x"94", + 5283 => x"83", + 5284 => x"56", + 5285 => x"38", + 5286 => x"22", + 5287 => x"89", + 5288 => x"55", + 5289 => x"75", + 5290 => x"17", + 5291 => x"39", + 5292 => x"52", + 5293 => x"b0", + 5294 => x"c8", + 5295 => x"75", + 5296 => x"38", + 5297 => x"fe", + 5298 => x"98", + 5299 => x"17", + 5300 => x"51", + 5301 => x"82", + 5302 => x"80", + 5303 => x"38", + 5304 => x"08", + 5305 => x"2a", + 5306 => x"80", + 5307 => x"38", + 5308 => x"8a", + 5309 => x"56", + 5310 => x"27", + 5311 => x"7b", + 5312 => x"54", + 5313 => x"52", + 5314 => x"33", + 5315 => x"ef", + 5316 => x"c8", + 5317 => x"38", + 5318 => x"70", + 5319 => x"56", + 5320 => x"9b", + 5321 => x"08", + 5322 => x"74", + 5323 => x"38", + 5324 => x"a8", + 5325 => x"84", + 5326 => x"51", + 5327 => x"79", + 5328 => x"80", + 5329 => x"17", + 5330 => x"80", + 5331 => x"17", + 5332 => x"2b", + 5333 => x"80", + 5334 => x"81", + 5335 => x"08", + 5336 => x"52", + 5337 => x"33", + 5338 => x"ec", + 5339 => x"c8", + 5340 => x"38", + 5341 => x"80", + 5342 => x"74", + 5343 => x"81", + 5344 => x"a8", + 5345 => x"81", + 5346 => x"55", + 5347 => x"82", + 5348 => x"fd", + 5349 => x"9c", + 5350 => x"17", + 5351 => x"06", + 5352 => x"31", + 5353 => x"76", + 5354 => x"78", + 5355 => x"94", + 5356 => x"ff", + 5357 => x"05", + 5358 => x"cb", + 5359 => x"76", + 5360 => x"17", + 5361 => x"1d", + 5362 => x"18", + 5363 => x"5d", + 5364 => x"b7", + 5365 => x"75", + 5366 => x"0c", + 5367 => x"04", + 5368 => x"7f", + 5369 => x"5f", + 5370 => x"80", + 5371 => x"3d", + 5372 => x"76", + 5373 => x"3f", + 5374 => x"08", + 5375 => x"c8", + 5376 => x"91", + 5377 => x"74", + 5378 => x"38", + 5379 => x"82", + 5380 => x"33", + 5381 => x"70", + 5382 => x"56", + 5383 => x"74", + 5384 => x"ee", + 5385 => x"82", + 5386 => x"34", + 5387 => x"e2", + 5388 => x"91", + 5389 => x"56", + 5390 => x"81", + 5391 => x"34", + 5392 => x"ce", + 5393 => x"91", + 5394 => x"56", + 5395 => x"81", + 5396 => x"34", + 5397 => x"ba", + 5398 => x"91", + 5399 => x"56", + 5400 => x"94", + 5401 => x"55", + 5402 => x"08", + 5403 => x"94", + 5404 => x"59", + 5405 => x"83", + 5406 => x"17", + 5407 => x"ff", + 5408 => x"74", + 5409 => x"7d", + 5410 => x"ff", + 5411 => x"2a", + 5412 => x"7a", + 5413 => x"75", + 5414 => x"17", + 5415 => x"a3", + 5416 => x"76", + 5417 => x"3f", + 5418 => x"08", + 5419 => x"98", + 5420 => x"76", + 5421 => x"3f", + 5422 => x"08", + 5423 => x"2e", + 5424 => x"74", + 5425 => x"df", + 5426 => x"2e", + 5427 => x"74", + 5428 => x"88", + 5429 => x"38", + 5430 => x"0c", + 5431 => x"70", + 5432 => x"58", + 5433 => x"a5", + 5434 => x"9c", + 5435 => x"a8", + 5436 => x"81", + 5437 => x"55", + 5438 => x"82", + 5439 => x"fe", + 5440 => x"17", + 5441 => x"06", + 5442 => x"18", + 5443 => x"08", + 5444 => x"cd", + 5445 => x"93", + 5446 => x"2e", + 5447 => x"82", + 5448 => x"1b", + 5449 => x"5b", + 5450 => x"2e", + 5451 => x"79", + 5452 => x"11", + 5453 => x"56", + 5454 => x"85", + 5455 => x"31", + 5456 => x"77", + 5457 => x"7d", + 5458 => x"52", + 5459 => x"3f", + 5460 => x"08", + 5461 => x"9c", + 5462 => x"31", + 5463 => x"27", + 5464 => x"80", + 5465 => x"80", + 5466 => x"a8", + 5467 => x"b9", + 5468 => x"33", + 5469 => x"55", + 5470 => x"34", + 5471 => x"56", + 5472 => x"9c", + 5473 => x"2e", + 5474 => x"17", + 5475 => x"08", + 5476 => x"81", + 5477 => x"a8", + 5478 => x"81", + 5479 => x"55", + 5480 => x"82", + 5481 => x"fd", + 5482 => x"9c", + 5483 => x"17", + 5484 => x"06", + 5485 => x"31", + 5486 => x"76", + 5487 => x"78", + 5488 => x"7b", + 5489 => x"08", + 5490 => x"17", + 5491 => x"c7", + 5492 => x"17", + 5493 => x"07", + 5494 => x"18", + 5495 => x"31", + 5496 => x"7e", + 5497 => x"94", + 5498 => x"70", + 5499 => x"8c", + 5500 => x"58", + 5501 => x"76", + 5502 => x"75", + 5503 => x"18", + 5504 => x"f6", + 5505 => x"33", + 5506 => x"55", + 5507 => x"34", + 5508 => x"82", + 5509 => x"8f", + 5510 => x"f7", + 5511 => x"8c", + 5512 => x"53", + 5513 => x"f1", + 5514 => x"93", + 5515 => x"82", + 5516 => x"81", + 5517 => x"18", + 5518 => x"2a", + 5519 => x"51", + 5520 => x"80", + 5521 => x"38", + 5522 => x"55", + 5523 => x"a7", + 5524 => x"9c", + 5525 => x"a8", + 5526 => x"81", + 5527 => x"55", + 5528 => x"81", + 5529 => x"c8", + 5530 => x"38", + 5531 => x"80", + 5532 => x"74", + 5533 => x"a0", + 5534 => x"79", + 5535 => x"3f", + 5536 => x"08", + 5537 => x"c8", + 5538 => x"38", + 5539 => x"8b", + 5540 => x"07", + 5541 => x"8b", + 5542 => x"18", + 5543 => x"52", + 5544 => x"d9", + 5545 => x"18", + 5546 => x"16", + 5547 => x"3f", + 5548 => x"0a", + 5549 => x"51", + 5550 => x"76", + 5551 => x"51", + 5552 => x"79", + 5553 => x"83", + 5554 => x"51", + 5555 => x"82", + 5556 => x"90", + 5557 => x"bf", + 5558 => x"74", + 5559 => x"76", + 5560 => x"93", + 5561 => x"3d", + 5562 => x"3d", + 5563 => x"52", + 5564 => x"3f", + 5565 => x"08", + 5566 => x"c8", + 5567 => x"86", + 5568 => x"52", + 5569 => x"a1", + 5570 => x"c8", + 5571 => x"93", + 5572 => x"38", + 5573 => x"08", + 5574 => x"82", + 5575 => x"86", + 5576 => x"fe", + 5577 => x"3d", + 5578 => x"3f", + 5579 => x"0b", + 5580 => x"08", + 5581 => x"82", + 5582 => x"82", + 5583 => x"80", + 5584 => x"93", + 5585 => x"3d", + 5586 => x"3d", + 5587 => x"93", + 5588 => x"52", + 5589 => x"e7", + 5590 => x"93", + 5591 => x"82", + 5592 => x"80", + 5593 => x"58", + 5594 => x"3d", + 5595 => x"e1", + 5596 => x"93", + 5597 => x"82", + 5598 => x"be", + 5599 => x"c7", + 5600 => x"98", + 5601 => x"73", + 5602 => x"38", + 5603 => x"12", + 5604 => x"39", + 5605 => x"33", + 5606 => x"70", + 5607 => x"55", + 5608 => x"2e", + 5609 => x"7f", + 5610 => x"54", + 5611 => x"82", + 5612 => x"94", + 5613 => x"39", + 5614 => x"84", + 5615 => x"06", + 5616 => x"55", + 5617 => x"c8", + 5618 => x"0d", + 5619 => x"0d", + 5620 => x"a3", + 5621 => x"5c", + 5622 => x"80", + 5623 => x"ff", + 5624 => x"a2", + 5625 => x"f5", + 5626 => x"c8", + 5627 => x"93", + 5628 => x"93", + 5629 => x"7b", + 5630 => x"08", + 5631 => x"56", + 5632 => x"2e", + 5633 => x"96", + 5634 => x"3d", + 5635 => x"a0", + 5636 => x"d1", + 5637 => x"93", + 5638 => x"82", + 5639 => x"81", + 5640 => x"52", + 5641 => x"a0", + 5642 => x"c8", + 5643 => x"93", + 5644 => x"cb", + 5645 => x"7e", + 5646 => x"3f", + 5647 => x"08", + 5648 => x"7a", + 5649 => x"3f", + 5650 => x"08", + 5651 => x"c8", + 5652 => x"38", + 5653 => x"52", + 5654 => x"f1", + 5655 => x"c8", + 5656 => x"93", + 5657 => x"38", + 5658 => x"51", + 5659 => x"82", + 5660 => x"75", + 5661 => x"76", + 5662 => x"d2", + 5663 => x"93", + 5664 => x"82", + 5665 => x"80", + 5666 => x"76", + 5667 => x"81", + 5668 => x"82", + 5669 => x"ef", + 5670 => x"ff", + 5671 => x"d4", + 5672 => x"ee", + 5673 => x"3d", + 5674 => x"81", + 5675 => x"52", + 5676 => x"73", + 5677 => x"38", + 5678 => x"16", + 5679 => x"51", + 5680 => x"f4", + 5681 => x"54", + 5682 => x"85", + 5683 => x"af", + 5684 => x"2e", + 5685 => x"58", + 5686 => x"3d", + 5687 => x"18", + 5688 => x"58", + 5689 => x"14", + 5690 => x"75", + 5691 => x"19", + 5692 => x"11", + 5693 => x"74", + 5694 => x"74", + 5695 => x"76", + 5696 => x"78", + 5697 => x"81", + 5698 => x"ff", + 5699 => x"08", + 5700 => x"af", + 5701 => x"70", + 5702 => x"33", + 5703 => x"81", + 5704 => x"70", + 5705 => x"52", + 5706 => x"57", + 5707 => x"2e", + 5708 => x"16", + 5709 => x"33", + 5710 => x"73", + 5711 => x"16", + 5712 => x"26", + 5713 => x"58", + 5714 => x"94", + 5715 => x"54", + 5716 => x"70", + 5717 => x"34", + 5718 => x"75", + 5719 => x"38", + 5720 => x"81", + 5721 => x"81", + 5722 => x"83", + 5723 => x"76", + 5724 => x"3d", + 5725 => x"1a", + 5726 => x"33", + 5727 => x"05", + 5728 => x"79", + 5729 => x"80", + 5730 => x"82", + 5731 => x"a1", + 5732 => x"f4", + 5733 => x"60", + 5734 => x"05", + 5735 => x"59", + 5736 => x"3f", + 5737 => x"08", + 5738 => x"c8", + 5739 => x"91", + 5740 => x"79", + 5741 => x"38", + 5742 => x"f9", + 5743 => x"08", + 5744 => x"38", + 5745 => x"70", + 5746 => x"81", + 5747 => x"56", + 5748 => x"8c", + 5749 => x"94", + 5750 => x"80", + 5751 => x"0c", + 5752 => x"2e", + 5753 => x"7c", + 5754 => x"70", + 5755 => x"51", + 5756 => x"2e", + 5757 => x"52", + 5758 => x"ff", + 5759 => x"82", + 5760 => x"ff", + 5761 => x"70", + 5762 => x"ff", + 5763 => x"82", + 5764 => x"75", + 5765 => x"78", + 5766 => x"94", + 5767 => x"94", + 5768 => x"98", + 5769 => x"58", + 5770 => x"88", + 5771 => x"75", + 5772 => x"52", + 5773 => x"a7", + 5774 => x"c8", + 5775 => x"93", + 5776 => x"2e", + 5777 => x"8b", + 5778 => x"91", + 5779 => x"55", + 5780 => x"82", + 5781 => x"ff", + 5782 => x"06", + 5783 => x"0b", + 5784 => x"81", + 5785 => x"39", + 5786 => x"08", + 5787 => x"75", + 5788 => x"75", + 5789 => x"a1", + 5790 => x"27", + 5791 => x"77", + 5792 => x"18", + 5793 => x"19", + 5794 => x"33", + 5795 => x"70", + 5796 => x"57", + 5797 => x"80", + 5798 => x"75", + 5799 => x"c8", + 5800 => x"93", + 5801 => x"82", + 5802 => x"94", + 5803 => x"c8", + 5804 => x"39", + 5805 => x"51", + 5806 => x"82", + 5807 => x"56", + 5808 => x"81", + 5809 => x"76", + 5810 => x"7c", + 5811 => x"08", + 5812 => x"38", + 5813 => x"18", + 5814 => x"81", + 5815 => x"98", + 5816 => x"79", + 5817 => x"38", + 5818 => x"18", + 5819 => x"77", + 5820 => x"55", + 5821 => x"a1", + 5822 => x"7c", + 5823 => x"3f", + 5824 => x"08", + 5825 => x"0b", + 5826 => x"82", + 5827 => x"39", + 5828 => x"82", + 5829 => x"05", + 5830 => x"08", + 5831 => x"27", + 5832 => x"17", + 5833 => x"0c", + 5834 => x"80", + 5835 => x"74", + 5836 => x"94", + 5837 => x"ff", + 5838 => x"80", + 5839 => x"38", + 5840 => x"7b", + 5841 => x"38", + 5842 => x"70", + 5843 => x"5c", + 5844 => x"b0", + 5845 => x"9c", + 5846 => x"a8", + 5847 => x"81", + 5848 => x"55", + 5849 => x"3f", + 5850 => x"08", + 5851 => x"38", + 5852 => x"18", + 5853 => x"bd", + 5854 => x"33", + 5855 => x"55", + 5856 => x"34", + 5857 => x"53", + 5858 => x"7c", + 5859 => x"52", + 5860 => x"eb", + 5861 => x"c8", + 5862 => x"93", + 5863 => x"91", + 5864 => x"55", + 5865 => x"0b", + 5866 => x"81", + 5867 => x"7a", + 5868 => x"79", + 5869 => x"93", + 5870 => x"3d", + 5871 => x"3d", + 5872 => x"89", + 5873 => x"2e", + 5874 => x"80", + 5875 => x"fc", + 5876 => x"3d", + 5877 => x"de", + 5878 => x"93", + 5879 => x"82", + 5880 => x"80", + 5881 => x"76", + 5882 => x"75", + 5883 => x"3f", + 5884 => x"08", + 5885 => x"c8", + 5886 => x"38", + 5887 => x"70", + 5888 => x"57", + 5889 => x"a6", + 5890 => x"33", + 5891 => x"70", + 5892 => x"55", + 5893 => x"2e", + 5894 => x"16", + 5895 => x"51", + 5896 => x"82", + 5897 => x"88", + 5898 => x"39", + 5899 => x"95", + 5900 => x"86", + 5901 => x"17", + 5902 => x"75", + 5903 => x"3f", + 5904 => x"08", + 5905 => x"2e", + 5906 => x"83", + 5907 => x"74", + 5908 => x"38", + 5909 => x"74", + 5910 => x"93", + 5911 => x"3d", + 5912 => x"3d", + 5913 => x"3d", + 5914 => x"70", + 5915 => x"b9", + 5916 => x"c8", + 5917 => x"93", + 5918 => x"38", + 5919 => x"08", + 5920 => x"82", + 5921 => x"86", + 5922 => x"fb", + 5923 => x"79", + 5924 => x"05", + 5925 => x"56", + 5926 => x"3f", + 5927 => x"08", + 5928 => x"c8", + 5929 => x"38", + 5930 => x"82", + 5931 => x"52", + 5932 => x"c5", + 5933 => x"c8", + 5934 => x"39", + 5935 => x"51", + 5936 => x"82", + 5937 => x"53", + 5938 => x"08", + 5939 => x"81", + 5940 => x"80", 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x"82", + 6000 => x"ff", + 6001 => x"82", + 6002 => x"81", + 6003 => x"82", + 6004 => x"30", + 6005 => x"c8", + 6006 => x"25", + 6007 => x"18", + 6008 => x"58", + 6009 => x"08", + 6010 => x"38", + 6011 => x"7a", + 6012 => x"a4", + 6013 => x"57", + 6014 => x"74", + 6015 => x"52", + 6016 => x"52", + 6017 => x"c0", + 6018 => x"c8", + 6019 => x"93", + 6020 => x"d5", + 6021 => x"33", + 6022 => x"82", + 6023 => x"06", + 6024 => x"15", + 6025 => x"ff", + 6026 => x"82", + 6027 => x"83", + 6028 => x"70", + 6029 => x"25", + 6030 => x"58", + 6031 => x"9d", + 6032 => x"b4", + 6033 => x"b5", + 6034 => x"93", + 6035 => x"0a", + 6036 => x"70", + 6037 => x"84", + 6038 => x"51", + 6039 => x"ff", + 6040 => x"57", + 6041 => x"93", + 6042 => x"0c", + 6043 => x"12", + 6044 => x"84", + 6045 => x"07", + 6046 => x"84", + 6047 => x"82", + 6048 => x"90", + 6049 => x"f8", + 6050 => x"8b", + 6051 => x"53", + 6052 => x"e0", + 6053 => x"93", + 6054 => x"82", + 6055 => x"8a", + 6056 => x"33", + 6057 => x"2e", + 6058 => x"56", + 6059 => x"90", + 6060 => x"81", + 6061 => x"06", + 6062 => x"87", + 6063 => x"2e", + 6064 => x"94", + 6065 => x"19", + 6066 => x"bc", + 6067 => x"08", + 6068 => x"53", + 6069 => x"52", + 6070 => x"be", + 6071 => x"93", + 6072 => x"80", + 6073 => x"0c", + 6074 => x"98", + 6075 => x"77", + 6076 => x"f4", + 6077 => x"c8", + 6078 => x"c8", + 6079 => x"70", + 6080 => x"07", + 6081 => x"57", + 6082 => x"93", + 6083 => x"2e", + 6084 => x"83", + 6085 => x"76", + 6086 => x"55", + 6087 => x"08", + 6088 => x"98", + 6089 => x"75", + 6090 => x"ff", + 6091 => x"82", + 6092 => x"57", + 6093 => x"8c", + 6094 => x"18", + 6095 => x"07", + 6096 => x"19", + 6097 => x"38", + 6098 => x"55", + 6099 => x"ab", + 6100 => x"9c", + 6101 => x"a8", + 6102 => x"81", + 6103 => x"55", + 6104 => x"3f", + 6105 => x"08", + 6106 => x"38", + 6107 => x"39", + 6108 => x"80", + 6109 => x"74", + 6110 => x"76", + 6111 => x"38", + 6112 => x"34", + 6113 => x"39", + 6114 => x"82", + 6115 => x"8a", + 6116 => x"e3", + 6117 => x"fb", + 6118 => x"96", + 6119 => x"53", + 6120 => x"a4", + 6121 => x"3d", + 6122 => x"3f", + 6123 => x"08", + 6124 => x"c8", + 6125 => x"38", + 6126 => x"51", + 6127 => x"3f", + 6128 => x"52", + 6129 => x"05", + 6130 => x"3f", + 6131 => x"08", + 6132 => x"52", + 6133 => x"9a", + 6134 => x"ae", + 6135 => x"f7", + 6136 => x"85", + 6137 => x"06", + 6138 => x"73", + 6139 => x"38", + 6140 => x"82", + 6141 => x"fb", + 6142 => x"95", + 6143 => x"80", + 6144 => x"70", + 6145 => x"55", + 6146 => x"85", + 6147 => x"90", + 6148 => x"d2", + 6149 => x"06", + 6150 => x"2e", + 6151 => x"56", + 6152 => x"38", + 6153 => x"51", + 6154 => x"82", + 6155 => x"02", + 6156 => x"d2", + 6157 => x"84", + 6158 => x"06", + 6159 => x"57", + 6160 => x"80", + 6161 => x"fb", + 6162 => x"95", + 6163 => x"78", + 6164 => x"14", + 6165 => x"80", + 6166 => x"fb", + 6167 => x"95", + 6168 => x"59", + 6169 => x"fb", + 6170 => x"95", + 6171 => x"52", + 6172 => x"52", + 6173 => x"3f", + 6174 => x"08", + 6175 => x"c8", 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x"38", + 6235 => x"84", + 6236 => x"06", + 6237 => x"77", + 6238 => x"98", + 6239 => x"51", + 6240 => x"3f", + 6241 => x"08", + 6242 => x"82", + 6243 => x"75", + 6244 => x"06", + 6245 => x"55", + 6246 => x"09", + 6247 => x"38", + 6248 => x"ff", + 6249 => x"06", + 6250 => x"55", + 6251 => x"0a", + 6252 => x"aa", + 6253 => x"77", + 6254 => x"c7", + 6255 => x"c8", + 6256 => x"93", + 6257 => x"96", + 6258 => x"a0", + 6259 => x"51", + 6260 => x"3f", + 6261 => x"0b", + 6262 => x"77", + 6263 => x"bf", + 6264 => x"52", + 6265 => x"51", + 6266 => x"3f", + 6267 => x"18", + 6268 => x"c3", + 6269 => x"53", + 6270 => x"80", + 6271 => x"ff", + 6272 => x"77", + 6273 => x"80", + 6274 => x"7e", + 6275 => x"18", + 6276 => x"c3", + 6277 => x"54", + 6278 => x"15", + 6279 => x"d4", + 6280 => x"e7", + 6281 => x"c8", + 6282 => x"93", + 6283 => x"38", + 6284 => x"96", + 6285 => x"ae", + 6286 => x"53", + 6287 => x"51", + 6288 => x"63", + 6289 => x"8b", + 6290 => x"54", + 6291 => x"15", + 6292 => x"ff", + 6293 => x"82", + 6294 => x"55", + 6295 => x"53", + 6296 => x"3d", + 6297 => x"ff", + 6298 => x"74", + 6299 => x"0c", + 6300 => x"04", + 6301 => x"a8", + 6302 => x"51", + 6303 => x"82", + 6304 => x"ff", + 6305 => x"a8", + 6306 => x"d1", + 6307 => x"c8", + 6308 => x"93", + 6309 => x"d7", + 6310 => x"a8", + 6311 => x"a7", + 6312 => x"51", + 6313 => x"82", + 6314 => x"55", + 6315 => x"08", + 6316 => x"02", + 6317 => x"33", + 6318 => x"54", + 6319 => x"83", + 6320 => x"74", + 6321 => x"a0", + 6322 => x"08", + 6323 => x"ff", + 6324 => x"ff", + 6325 => x"ac", + 6326 => x"d4", + 6327 => x"3d", + 6328 => x"ff", + 6329 => x"a9", + 6330 => x"73", + 6331 => x"3f", + 6332 => x"08", + 6333 => x"c8", + 6334 => x"62", + 6335 => x"81", + 6336 => x"84", + 6337 => x"3d", + 6338 => x"38", + 6339 => x"84", + 6340 => x"06", + 6341 => x"a7", + 6342 => x"05", + 6343 => x"3f", + 6344 => x"08", + 6345 => x"c8", + 6346 => x"38", + 6347 => x"53", + 6348 => x"95", + 6349 => x"16", + 6350 => x"ed", + 6351 => x"05", + 6352 => x"34", + 6353 => x"70", + 6354 => x"81", + 6355 => x"57", + 6356 => x"76", + 6357 => x"73", + 6358 => x"77", + 6359 => x"83", + 6360 => x"16", + 6361 => x"2a", + 6362 => x"51", + 6363 => x"80", + 6364 => x"38", + 6365 => x"80", + 6366 => x"52", + 6367 => x"bf", + 6368 => x"93", + 6369 => x"77", + 6370 => x"b2", + 6371 => x"82", + 6372 => x"80", + 6373 => x"82", + 6374 => x"52", + 6375 => x"ae", + 6376 => x"93", + 6377 => x"d4", + 6378 => x"82", + 6379 => x"bf", + 6380 => x"33", + 6381 => x"2e", + 6382 => x"92", + 6383 => x"75", + 6384 => x"ff", + 6385 => x"77", + 6386 => x"83", + 6387 => x"9f", + 6388 => x"d4", + 6389 => x"89", + 6390 => x"c8", + 6391 => x"93", + 6392 => x"38", + 6393 => x"ae", + 6394 => x"93", + 6395 => x"74", + 6396 => x"0c", + 6397 => x"04", + 6398 => x"02", + 6399 => x"33", + 6400 => x"80", + 6401 => x"57", + 6402 => x"95", + 6403 => x"52", + 6404 => x"cd", + 6405 => x"93", + 6406 => x"82", + 6407 => x"80", + 6408 => x"5a", + 6409 => x"3d", + 6410 => x"c7", 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x"c8", + 6470 => x"25", + 6471 => x"7d", + 6472 => x"72", + 6473 => x"51", + 6474 => x"80", + 6475 => x"38", + 6476 => x"5f", + 6477 => x"3d", + 6478 => x"ff", + 6479 => x"82", + 6480 => x"56", + 6481 => x"08", + 6482 => x"81", + 6483 => x"ff", + 6484 => x"82", + 6485 => x"56", + 6486 => x"08", + 6487 => x"93", + 6488 => x"93", + 6489 => x"5c", + 6490 => x"17", + 6491 => x"1a", + 6492 => x"74", + 6493 => x"81", + 6494 => x"77", + 6495 => x"77", + 6496 => x"74", + 6497 => x"2e", + 6498 => x"18", + 6499 => x"33", + 6500 => x"73", + 6501 => x"38", + 6502 => x"09", + 6503 => x"38", + 6504 => x"80", + 6505 => x"70", + 6506 => x"25", + 6507 => x"7e", + 6508 => x"72", + 6509 => x"51", + 6510 => x"2e", + 6511 => x"a0", + 6512 => x"51", + 6513 => x"3f", + 6514 => x"08", + 6515 => x"c8", + 6516 => x"7b", + 6517 => x"54", + 6518 => x"73", + 6519 => x"38", + 6520 => x"73", + 6521 => x"38", + 6522 => x"18", + 6523 => x"ff", + 6524 => x"82", + 6525 => x"7b", + 6526 => x"93", + 6527 => x"3d", + 6528 => x"3d", + 6529 => x"9a", + 6530 => x"05", + 6531 => x"51", + 6532 => x"82", + 6533 => x"55", + 6534 => x"08", + 6535 => x"8b", + 6536 => x"9a", + 6537 => x"05", + 6538 => x"a1", + 6539 => x"70", + 6540 => x"57", + 6541 => x"74", + 6542 => x"38", + 6543 => x"81", + 6544 => x"81", + 6545 => x"56", + 6546 => x"3f", + 6547 => x"08", + 6548 => x"38", + 6549 => x"70", + 6550 => x"ff", + 6551 => x"82", + 6552 => x"80", + 6553 => x"75", + 6554 => x"07", + 6555 => x"4c", + 6556 => x"80", + 6557 => x"16", + 6558 => x"26", + 6559 => x"16", + 6560 => x"ff", + 6561 => x"80", + 6562 => x"87", + 6563 => x"f8", + 6564 => x"75", + 6565 => x"38", + 6566 => x"fc", + 6567 => x"a6", + 6568 => x"93", + 6569 => x"38", + 6570 => x"27", + 6571 => x"89", + 6572 => x"8b", + 6573 => x"27", + 6574 => x"55", + 6575 => x"81", + 6576 => x"93", + 6577 => x"77", + 6578 => x"05", + 6579 => x"55", + 6580 => x"34", + 6581 => x"9a", + 6582 => x"ff", + 6583 => x"75", + 6584 => x"17", + 6585 => x"56", + 6586 => x"9f", + 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x"3d", + 7645 => x"51", + 7646 => x"3f", + 7647 => x"56", + 7648 => x"08", + 7649 => x"f8", + 7650 => x"82", + 7651 => x"a0", + 7652 => x"59", + 7653 => x"3f", + 7654 => x"58", + 7655 => x"57", + 7656 => x"81", + 7657 => x"55", + 7658 => x"80", + 7659 => x"80", + 7660 => x"51", + 7661 => x"82", + 7662 => x"5e", + 7663 => x"7c", + 7664 => x"59", + 7665 => x"7d", + 7666 => x"81", + 7667 => x"38", + 7668 => x"51", + 7669 => x"3f", + 7670 => x"80", + 7671 => x"0b", + 7672 => x"34", + 7673 => x"e4", + 7674 => x"94", + 7675 => x"90", + 7676 => x"87", + 7677 => x"0c", + 7678 => x"0b", + 7679 => x"84", + 7680 => x"83", + 7681 => x"94", + 7682 => x"d4", + 7683 => x"93", + 7684 => x"d7", + 7685 => x"93", + 7686 => x"e8", + 7687 => x"ee", + 7688 => x"8b", + 7689 => x"e5", + 7690 => x"8b", + 7691 => x"ef", + 7692 => x"e4", + 7693 => x"ee", + 7694 => x"51", + 7695 => x"f7", + 7696 => x"04", + 7697 => x"2f", + 7698 => x"2f", + 7699 => x"2f", + 7700 => x"2f", + 7701 => x"2f", + 7702 => x"2f", + 7703 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x"77", + 7880 => x"77", + 7881 => x"74", + 7882 => x"2f", + 7883 => x"25", + 7884 => x"64", + 7885 => x"3a", + 7886 => x"25", + 7887 => x"0a", + 7888 => x"43", + 7889 => x"6e", + 7890 => x"75", + 7891 => x"69", + 7892 => x"00", + 7893 => x"66", + 7894 => x"20", + 7895 => x"20", + 7896 => x"66", + 7897 => x"00", + 7898 => x"44", + 7899 => x"63", + 7900 => x"69", + 7901 => x"65", + 7902 => x"74", + 7903 => x"0a", + 7904 => x"20", + 7905 => x"53", + 7906 => x"52", + 7907 => x"28", + 7908 => x"72", + 7909 => x"30", + 7910 => x"20", + 7911 => x"65", + 7912 => x"38", + 7913 => x"0a", + 7914 => x"20", + 7915 => x"41", + 7916 => x"53", + 7917 => x"74", + 7918 => x"38", + 7919 => x"53", + 7920 => x"3d", + 7921 => x"58", + 7922 => x"00", + 7923 => x"20", + 7924 => x"4d", + 7925 => x"74", + 7926 => x"3d", + 7927 => x"58", + 7928 => x"69", + 7929 => x"25", + 7930 => x"29", + 7931 => x"00", + 7932 => x"20", + 7933 => x"43", + 7934 => x"00", + 7935 => x"20", + 7936 => x"32", + 7937 => x"00", + 7938 => x"20", + 7939 => x"49", + 7940 => x"00", + 7941 => x"20", + 7942 => x"20", + 7943 => x"64", + 7944 => x"65", + 7945 => x"65", + 7946 => x"30", + 7947 => x"2e", + 7948 => x"00", + 7949 => x"20", + 7950 => x"54", + 7951 => x"55", + 7952 => x"43", + 7953 => x"52", + 7954 => x"45", + 7955 => x"00", + 7956 => x"20", + 7957 => x"4d", + 7958 => x"20", + 7959 => x"6d", + 7960 => x"3d", + 7961 => x"58", + 7962 => x"00", + 7963 => x"64", + 7964 => x"73", + 7965 => x"0a", + 7966 => x"20", + 7967 => x"55", + 7968 => x"73", + 7969 => x"56", + 7970 => x"6f", + 7971 => x"64", + 7972 => x"73", + 7973 => x"20", + 7974 => x"58", + 7975 => x"00", + 7976 => x"20", + 7977 => x"55", + 7978 => x"6d", + 7979 => x"20", + 7980 => x"72", + 7981 => x"64", + 7982 => x"73", + 7983 => x"20", + 7984 => x"58", + 7985 => x"00", + 7986 => x"20", + 7987 => x"61", + 7988 => x"53", + 7989 => x"74", + 7990 => x"64", + 7991 => x"73", + 7992 => x"20", + 7993 => x"20", + 7994 => x"58", + 7995 => x"00", + 7996 => x"20", + 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8232 => x"64", + 8233 => x"65", + 8234 => x"72", + 8235 => x"00", + 8236 => x"72", + 8237 => x"72", + 8238 => x"00", + 8239 => x"6c", + 8240 => x"00", + 8241 => x"70", + 8242 => x"73", + 8243 => x"74", + 8244 => x"73", + 8245 => x"00", + 8246 => x"6c", + 8247 => x"00", + 8248 => x"66", + 8249 => x"00", + 8250 => x"6d", + 8251 => x"00", + 8252 => x"73", + 8253 => x"00", + 8254 => x"73", + 8255 => x"72", + 8256 => x"0a", + 8257 => x"74", + 8258 => x"61", + 8259 => x"72", + 8260 => x"2e", + 8261 => x"00", + 8262 => x"73", + 8263 => x"6f", + 8264 => x"65", + 8265 => x"2e", + 8266 => x"00", + 8267 => x"20", + 8268 => x"65", + 8269 => x"75", + 8270 => x"0a", + 8271 => x"20", + 8272 => x"68", + 8273 => x"75", + 8274 => x"0a", + 8275 => x"76", + 8276 => x"64", + 8277 => x"6c", + 8278 => x"6d", + 8279 => x"00", + 8280 => x"63", + 8281 => x"20", + 8282 => x"69", + 8283 => x"0a", + 8284 => x"6c", + 8285 => x"6c", + 8286 => x"64", + 8287 => x"78", + 8288 => x"73", + 8289 => x"00", + 8290 => x"6c", + 8291 => x"61", + 8292 => x"65", + 8293 => x"76", + 8294 => x"64", + 8295 => x"00", + 8296 => x"20", + 8297 => x"77", + 8298 => x"65", + 8299 => x"6f", + 8300 => x"74", + 8301 => x"0a", + 8302 => x"69", + 8303 => x"6e", + 8304 => x"65", + 8305 => x"73", + 8306 => x"76", + 8307 => x"64", + 8308 => x"00", + 8309 => x"73", + 8310 => x"6f", + 8311 => x"6e", + 8312 => x"65", + 8313 => x"00", + 8314 => x"20", + 8315 => x"70", + 8316 => x"62", + 8317 => x"66", + 8318 => x"73", + 8319 => x"65", + 8320 => x"6f", + 8321 => x"20", + 8322 => x"64", + 8323 => x"2e", + 8324 => x"00", + 8325 => x"72", + 8326 => x"20", + 8327 => x"72", + 8328 => x"2e", + 8329 => x"00", + 8330 => x"6d", + 8331 => x"74", + 8332 => x"70", + 8333 => x"74", + 8334 => x"20", + 8335 => x"63", + 8336 => x"65", + 8337 => x"00", + 8338 => x"6c", + 8339 => x"73", + 8340 => x"63", + 8341 => x"2e", + 8342 => x"00", + 8343 => x"73", + 8344 => x"69", + 8345 => x"6e", + 8346 => x"65", + 8347 => x"79", + 8348 => x"00", + 8349 => x"6f", + 8350 => x"6e", + 8351 => x"70", + 8352 => x"66", + 8353 => x"73", + 8354 => x"00", + 8355 => x"72", + 8356 => x"74", + 8357 => x"20", + 8358 => x"6f", + 8359 => x"63", + 8360 => x"00", + 8361 => x"63", + 8362 => x"73", + 8363 => x"00", + 8364 => x"6b", + 8365 => x"6e", + 8366 => x"72", + 8367 => x"0a", + 8368 => x"6c", + 8369 => x"79", + 8370 => x"20", + 8371 => x"61", + 8372 => x"6c", + 8373 => x"79", + 8374 => x"2f", + 8375 => x"2e", + 8376 => x"00", + 8377 => x"61", + 8378 => x"00", + 8379 => x"55", + 8380 => x"00", + 8381 => x"2a", + 8382 => x"20", + 8383 => x"00", + 8384 => x"2f", + 8385 => x"32", + 8386 => x"00", + 8387 => x"2e", + 8388 => x"00", + 8389 => x"50", + 8390 => x"72", + 8391 => x"25", + 8392 => x"29", + 8393 => x"20", + 8394 => x"2a", + 8395 => x"00", + 8396 => x"55", + 8397 => x"49", + 8398 => x"72", + 8399 => x"74", + 8400 => x"6e", + 8401 => x"72", + 8402 => x"00", + 8403 => x"6d", + 8404 => x"69", + 8405 => x"72", + 8406 => x"74", + 8407 => x"00", + 8408 => x"32", + 8409 => x"74", + 8410 => x"75", + 8411 => x"00", + 8412 => x"43", + 8413 => x"52", + 8414 => x"6e", + 8415 => x"72", + 8416 => x"0a", + 8417 => x"43", + 8418 => x"57", + 8419 => x"6e", + 8420 => x"72", + 8421 => x"0a", + 8422 => x"52", + 8423 => x"52", + 8424 => x"6e", + 8425 => x"72", + 8426 => x"0a", + 8427 => x"52", + 8428 => x"54", + 8429 => x"6e", + 8430 => x"72", + 8431 => x"0a", + 8432 => x"52", + 8433 => x"52", + 8434 => x"6e", + 8435 => x"72", + 8436 => x"0a", + 8437 => x"52", + 8438 => x"54", + 8439 => x"6e", + 8440 => x"72", + 8441 => x"0a", + 8442 => x"74", + 8443 => x"67", + 8444 => x"20", + 8445 => x"65", + 8446 => x"2e", + 8447 => x"00", + 8448 => x"61", + 8449 => x"6e", + 8450 => x"69", + 8451 => x"2e", + 8452 => x"00", + 8453 => x"00", + 8454 => x"69", + 8455 => x"20", + 8456 => x"69", + 8457 => x"69", + 8458 => x"73", + 8459 => x"64", + 8460 => x"72", + 8461 => x"2c", + 8462 => x"65", + 8463 => x"20", + 8464 => x"74", + 8465 => x"6e", + 8466 => x"6c", + 8467 => x"00", + 8468 => x"00", + 8469 => x"64", + 8470 => x"73", + 8471 => x"64", + 8472 => x"00", + 8473 => x"69", + 8474 => x"6c", + 8475 => x"64", + 8476 => x"00", + 8477 => x"69", + 8478 => x"20", + 8479 => x"69", + 8480 => x"69", + 8481 => x"73", + 8482 => x"00", + 8483 => x"3d", + 8484 => x"00", + 8485 => x"3a", + 8486 => x"73", + 8487 => x"69", + 8488 => x"69", + 8489 => x"72", + 8490 => x"74", + 8491 => x"00", + 8492 => x"61", + 8493 => x"6e", + 8494 => x"6e", + 8495 => x"72", + 8496 => x"73", + 8497 => x"00", + 8498 => x"73", + 8499 => x"65", + 8500 => x"61", + 8501 => x"66", + 8502 => x"0a", + 8503 => x"61", + 8504 => x"6e", + 8505 => x"61", + 8506 => x"66", + 8507 => x"0a", + 8508 => x"65", + 8509 => x"69", + 8510 => x"63", + 8511 => x"20", + 8512 => x"30", + 8513 => x"2e", + 8514 => x"00", + 8515 => x"6c", + 8516 => x"67", + 8517 => x"64", + 8518 => x"20", + 8519 => x"78", + 8520 => x"2e", + 8521 => x"00", + 8522 => x"6c", + 8523 => x"65", + 8524 => x"6e", + 8525 => x"63", + 8526 => x"20", + 8527 => x"29", + 8528 => x"00", + 8529 => x"73", + 8530 => x"74", + 8531 => x"20", + 8532 => x"6c", + 8533 => x"74", + 8534 => x"2e", + 8535 => x"00", + 8536 => x"6c", + 8537 => x"65", + 8538 => x"74", + 8539 => x"2e", + 8540 => x"00", + 8541 => x"55", + 8542 => x"6e", + 8543 => x"3a", + 8544 => x"5c", + 8545 => x"25", + 8546 => x"00", + 8547 => x"64", + 8548 => x"6d", + 8549 => x"64", + 8550 => x"00", + 8551 => x"6e", + 8552 => x"67", + 8553 => x"0a", + 8554 => x"61", + 8555 => x"6e", + 8556 => x"6e", + 8557 => x"72", + 8558 => x"73", + 8559 => x"0a", + 8560 => x"00", + 8561 => x"00", + 8562 => x"7f", + 8563 => x"00", + 8564 => x"7f", + 8565 => x"00", + 8566 => x"7f", + 8567 => x"00", + 8568 => x"00", + 8569 => x"78", + 8570 => x"00", + 8571 => x"e1", + 8572 => x"01", + 8573 => x"01", + 8574 => x"01", + 8575 => x"00", + 8576 => x"00", + 8577 => x"00", + 8578 => x"7f", + 8579 => x"01", + 8580 => x"00", + 8581 => x"00", + 8582 => x"7f", + 8583 => x"01", + 8584 => x"00", + 8585 => x"00", + 8586 => x"7f", + 8587 => x"01", + 8588 => x"00", + 8589 => x"00", + 8590 => x"7f", + 8591 => x"01", + 8592 => x"00", + 8593 => x"00", + 8594 => x"7f", + 8595 => x"02", + 8596 => x"00", + 8597 => x"00", + 8598 => x"7f", + 8599 => x"02", + 8600 => x"00", + 8601 => x"00", + 8602 => x"7f", + 8603 => x"02", + 8604 => x"00", + 8605 => x"00", + 8606 => x"7f", + 8607 => x"02", + 8608 => x"00", + 8609 => x"00", + 8610 => x"7f", + 8611 => x"02", + 8612 => x"00", + 8613 => x"00", + 8614 => x"7f", + 8615 => x"02", + 8616 => x"00", + 8617 => x"00", + 8618 => x"7f", + 8619 => x"03", + 8620 => x"00", + 8621 => x"00", + 8622 => x"7f", + 8623 => x"03", + 8624 => x"00", + 8625 => x"00", + 8626 => x"7f", + 8627 => x"03", + 8628 => x"00", + 8629 => x"00", + 8630 => x"7f", + 8631 => x"03", + 8632 => x"00", + 8633 => x"00", + 8634 => x"7f", + 8635 => x"03", + 8636 => x"00", + 8637 => x"00", + 8638 => x"7f", + 8639 => x"03", + 8640 => x"00", + 8641 => x"00", + 8642 => x"7f", + 8643 => x"03", + 8644 => x"00", + 8645 => x"00", + 8646 => x"7f", + 8647 => x"03", + 8648 => x"00", + 8649 => x"00", + 8650 => x"7f", + 8651 => x"03", + 8652 => x"00", + 8653 => x"00", + 8654 => x"7f", + 8655 => x"03", + 8656 => x"00", + 8657 => x"00", + 8658 => x"7f", + 8659 => x"03", + 8660 => x"00", + 8661 => x"00", + 8662 => x"7f", + 8663 => x"03", + 8664 => x"00", + 8665 => x"00", + 8666 => x"7f", + 8667 => x"03", + 8668 => x"00", + 8669 => x"00", + 8670 => x"7f", + 8671 => x"03", + 8672 => x"00", + 8673 => x"00", + 8674 => x"80", + 8675 => x"03", + 8676 => x"00", + 8677 => x"00", + 8678 => x"80", + 8679 => x"03", + 8680 => x"00", + 8681 => x"00", + 8682 => x"80", + 8683 => x"03", + 8684 => x"00", + 8685 => x"00", + 8686 => x"80", + 8687 => x"03", + 8688 => x"00", + 8689 => x"00", + 8690 => x"80", + 8691 => x"03", + 8692 => x"00", + 8693 => x"00", + 8694 => x"80", + 8695 => x"03", + 8696 => x"00", + 8697 => x"00", + 8698 => x"80", + 8699 => x"03", + 8700 => x"00", + 8701 => x"00", + 8702 => x"80", + 8703 => x"03", + 8704 => x"00", + 8705 => x"00", + 8706 => x"80", + 8707 => x"03", + 8708 => x"00", + 8709 => x"00", + 8710 => x"80", + 8711 => x"03", + 8712 => x"00", + 8713 => x"00", + 8714 => x"80", + 8715 => x"03", + 8716 => x"00", + 8717 => x"00", + 8718 => x"80", + 8719 => x"03", + 8720 => x"00", + 8721 => x"00", + 8722 => x"80", + 8723 => x"03", + 8724 => x"00", + 8725 => x"00", + 8726 => x"80", + 8727 => x"03", + 8728 => x"00", + 8729 => x"00", + 8730 => x"80", + 8731 => x"03", + 8732 => x"00", + 8733 => x"00", + 8734 => x"80", + 8735 => x"04", + 8736 => x"00", + 8737 => x"00", + 8738 => x"80", + 8739 => x"04", + 8740 => x"00", + 8741 => x"00", + 8742 => x"80", + 8743 => x"04", + 8744 => x"00", + 8745 => x"00", + 8746 => x"80", + 8747 => x"04", + 8748 => x"00", + 8749 => x"00", + 8750 => x"80", + 8751 => x"04", + 8752 => x"00", + 8753 => x"00", + 8754 => x"80", + 8755 => x"05", + 8756 => x"00", + 8757 => x"00", + 8758 => x"80", + 8759 => x"05", + 8760 => x"00", + 8761 => x"00", + 8762 => x"80", + 8763 => x"05", + 8764 => x"00", + 8765 => x"00", + 8766 => x"80", + 8767 => x"05", + 8768 => x"00", + 8769 => x"00", + 8770 => x"80", + 8771 => x"05", + 8772 => x"00", + 8773 => x"00", + 8774 => x"80", + 8775 => x"05", + 8776 => x"00", + 8777 => x"00", + 8778 => x"80", + 8779 => x"06", + 8780 => x"00", + 8781 => x"00", + 8782 => x"80", + 8783 => x"06", + 8784 => x"00", + 8785 => x"00", + 8786 => x"80", + 8787 => x"07", + 8788 => x"00", + 8789 => x"00", + 8790 => x"80", + 8791 => x"07", + 8792 => x"00", + 8793 => x"00", + 8794 => x"80", + 8795 => x"08", + 8796 => x"00", + 8797 => x"00", + 8798 => x"80", + 8799 => x"08", + 8800 => x"00", + 8801 => x"00", + 8802 => x"80", + 8803 => x"08", + 8804 => x"00", + 8805 => x"00", + 8806 => x"80", + 8807 => x"08", + 8808 => x"00", + 8809 => x"00", + 8810 => x"80", + 8811 => x"08", + 8812 => x"00", + 8813 => x"00", + 8814 => x"80", + 8815 => x"08", + 8816 => x"00", + 8817 => x"00", + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + 0 => x"0b", + 1 => x"04", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"08", + 10 => x"88", + 11 => x"90", + 12 => x"88", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"fd", + 17 => x"83", + 18 => x"05", + 19 => x"2b", + 20 => x"ff", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"fd", + 25 => x"ff", + 26 => x"06", + 27 => x"82", + 28 => x"2b", + 29 => x"83", + 30 => x"0b", + 31 => x"a5", + 32 => x"09", + 33 => x"05", + 34 => x"06", + 35 => x"09", + 36 => x"0a", + 37 => x"51", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"2e", + 42 => x"04", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"73", + 49 => x"06", + 50 => x"81", + 51 => x"10", + 52 => x"10", + 53 => x"0a", + 54 => x"51", + 55 => x"00", + 56 => x"72", + 57 => x"2e", + 58 => x"04", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"04", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"0a", + 81 => x"53", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"81", + 90 => x"0b", + 91 => x"04", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"9f", + 98 => x"74", + 99 => x"06", + 100 => x"07", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"06", + 106 => x"09", + 107 => x"05", + 108 => x"2b", + 109 => x"06", + 110 => x"04", + 111 => x"00", + 112 => x"09", + 113 => x"05", + 114 => x"05", + 115 => x"81", + 116 => x"04", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"09", + 121 => x"05", + 122 => x"05", + 123 => x"09", + 124 => x"51", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"09", + 129 => x"04", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"09", + 145 => x"73", + 146 => x"53", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"fc", + 153 => x"83", + 154 => x"05", + 155 => x"10", + 156 => x"ff", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"fc", + 161 => x"0b", + 162 => x"73", + 163 => x"10", + 164 => x"0b", + 165 => x"ac", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"08", + 170 => x"0b", + 171 => x"2d", + 172 => x"08", + 173 => x"8c", + 174 => x"51", + 175 => x"00", + 176 => x"08", + 177 => x"08", + 178 => x"0b", + 179 => x"2d", + 180 => x"08", + 181 => x"8c", + 182 => x"51", + 183 => x"00", + 184 => x"09", + 185 => x"09", + 186 => x"06", + 187 => x"54", + 188 => x"09", + 189 => x"ff", + 190 => x"51", + 191 => x"00", + 192 => x"09", + 193 => x"09", + 194 => x"81", + 195 => x"70", + 196 => x"73", + 197 => x"05", + 198 => x"07", + 199 => x"04", + 200 => x"ff", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"81", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"84", + 233 => x"10", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"71", + 250 => x"0d", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"00", + 257 => x"00", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"10", + 266 => x"04", + 267 => x"81", + 268 => x"83", + 269 => x"05", + 270 => x"10", + 271 => x"72", + 272 => x"51", + 273 => x"72", + 274 => x"06", + 275 => x"72", + 276 => x"10", + 277 => x"10", + 278 => x"ed", + 279 => x"53", + 280 => x"04", + 281 => x"04", + 282 => x"9f", + 283 => x"dc", + 284 => x"80", + 285 => x"05", + 286 => x"eb", + 287 => x"51", + 288 => x"94", + 289 => x"0c", + 290 => x"80", + 291 => x"8c", + 292 => x"94", + 293 => x"08", + 294 => x"3f", + 295 => x"88", + 296 => x"3d", + 297 => x"04", + 298 => x"94", + 299 => x"0d", + 300 => x"08", + 301 => x"52", + 302 => x"05", + 303 => x"b9", + 304 => x"70", + 305 => x"85", + 306 => x"0c", + 307 => x"02", + 308 => x"3d", + 309 => x"94", + 310 => x"0c", + 311 => x"05", + 312 => x"ab", + 313 => x"88", + 314 => x"94", + 315 => x"0c", + 316 => x"08", + 317 => x"94", + 318 => x"08", + 319 => x"0b", + 320 => x"05", + 321 => x"f4", + 322 => x"08", + 323 => x"94", + 324 => x"08", + 325 => x"38", + 326 => x"05", + 327 => x"08", + 328 => x"80", + 329 => x"f0", + 330 => x"08", + 331 => x"88", + 332 => x"94", + 333 => x"0c", + 334 => x"05", + 335 => x"fc", + 336 => x"53", + 337 => x"05", + 338 => x"08", + 339 => x"51", + 340 => x"88", + 341 => x"08", + 342 => x"54", + 343 => x"05", + 344 => x"8c", + 345 => x"f8", + 346 => x"94", + 347 => x"0c", + 348 => x"05", + 349 => x"0c", + 350 => x"0d", + 351 => x"94", + 352 => x"0c", + 353 => x"80", + 354 => x"fc", + 355 => x"08", + 356 => x"80", + 357 => x"94", + 358 => x"08", + 359 => x"88", + 360 => x"0b", + 361 => x"05", + 362 => x"8c", + 363 => x"25", + 364 => x"08", + 365 => x"30", + 366 => x"05", + 367 => x"94", + 368 => x"08", + 369 => x"88", + 370 => x"ad", + 371 => x"70", + 372 => x"05", + 373 => x"08", + 374 => x"80", + 375 => x"94", + 376 => x"08", + 377 => x"f8", + 378 => x"08", + 379 => x"70", + 380 => x"87", + 381 => x"0c", + 382 => x"02", + 383 => x"3d", + 384 => x"94", + 385 => x"0c", + 386 => x"08", + 387 => x"94", + 388 => x"08", + 389 => x"05", + 390 => x"38", + 391 => x"05", + 392 => x"a3", + 393 => x"94", + 394 => x"08", + 395 => x"94", + 396 => x"08", + 397 => x"8c", + 398 => x"08", + 399 => x"10", + 400 => x"05", + 401 => x"94", + 402 => x"08", + 403 => x"c9", + 404 => x"8c", + 405 => x"08", + 406 => x"26", + 407 => x"08", + 408 => x"94", + 409 => x"08", + 410 => x"88", + 411 => x"08", + 412 => x"94", + 413 => x"08", + 414 => x"f8", + 415 => x"08", + 416 => x"81", + 417 => x"fc", + 418 => x"08", + 419 => x"81", + 420 => x"8c", + 421 => x"af", + 422 => x"90", + 423 => x"2e", + 424 => x"08", + 425 => x"70", + 426 => x"05", + 427 => x"39", + 428 => x"05", + 429 => x"08", + 430 => x"51", + 431 => x"05", + 432 => x"85", + 433 => x"0c", + 434 => x"0d", + 435 => x"87", + 436 => x"0c", + 437 => x"c0", + 438 => x"85", + 439 => x"98", + 440 => x"c0", + 441 => x"70", + 442 => x"51", + 443 => x"8a", + 444 => x"98", + 445 => x"70", + 446 => x"c0", + 447 => x"fc", + 448 => x"52", + 449 => x"87", + 450 => x"08", + 451 => x"2e", + 452 => x"0b", + 453 => x"a8", + 454 => x"0b", + 455 => x"88", + 456 => x"0d", + 457 => x"0d", + 458 => x"56", + 459 => x"0b", + 460 => x"9f", + 461 => x"06", + 462 => x"52", + 463 => x"09", + 464 => x"9e", + 465 => x"87", + 466 => x"0c", + 467 => x"92", + 468 => x"0b", + 469 => x"8c", + 470 => x"92", + 471 => x"85", + 472 => x"06", + 473 => x"70", + 474 => x"38", + 475 => x"84", + 476 => x"ff", + 477 => x"27", + 478 => x"73", + 479 => x"38", + 480 => x"8b", + 481 => x"70", + 482 => x"34", + 483 => x"81", + 484 => x"a2", + 485 => x"80", + 486 => x"87", + 487 => x"08", + 488 => x"b5", + 489 => x"98", + 490 => x"70", + 491 => x"0b", + 492 => x"8c", + 493 => x"92", + 494 => x"82", + 495 => x"70", + 496 => x"73", + 497 => x"06", + 498 => x"72", + 499 => x"06", + 500 => x"c0", + 501 => x"51", + 502 => x"09", + 503 => x"38", + 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x"fd", + 567 => x"54", + 568 => x"0b", + 569 => x"08", + 570 => x"53", + 571 => x"2e", + 572 => x"8c", + 573 => x"51", + 574 => x"88", + 575 => x"53", + 576 => x"fd", + 577 => x"08", + 578 => x"06", + 579 => x"0c", + 580 => x"04", + 581 => x"76", + 582 => x"9f", + 583 => x"55", + 584 => x"88", + 585 => x"72", + 586 => x"38", + 587 => x"73", + 588 => x"81", + 589 => x"72", + 590 => x"33", + 591 => x"2e", + 592 => x"85", + 593 => x"08", + 594 => x"16", + 595 => x"2e", + 596 => x"51", + 597 => x"88", + 598 => x"39", + 599 => x"52", + 600 => x"0c", + 601 => x"88", + 602 => x"0d", + 603 => x"0d", + 604 => x"0b", + 605 => x"71", + 606 => x"70", + 607 => x"06", + 608 => x"55", + 609 => x"88", + 610 => x"08", + 611 => x"38", + 612 => x"dc", + 613 => x"06", + 614 => x"cf", + 615 => x"90", + 616 => x"15", + 617 => x"8f", + 618 => x"84", + 619 => x"52", + 620 => x"bc", + 621 => x"82", + 622 => x"05", + 623 => x"06", + 624 => x"38", + 625 => x"df", + 626 => x"71", + 627 => x"a0", + 628 => x"88", + 629 => x"08", + 630 => x"88", + 631 => x"0c", + 632 => x"fd", + 633 => x"08", + 634 => x"73", + 635 => x"52", + 636 => x"88", + 637 => x"f2", + 638 => x"62", + 639 => x"5c", + 640 => x"74", + 641 => x"81", + 642 => x"81", + 643 => x"56", + 644 => x"70", + 645 => x"74", + 646 => x"81", + 647 => x"81", + 648 => x"0b", + 649 => x"62", + 650 => x"55", + 651 => x"8f", + 652 => x"fd", + 653 => x"08", + 654 => x"34", + 655 => x"93", + 656 => x"08", + 657 => x"5f", + 658 => x"76", + 659 => x"58", + 660 => x"55", + 661 => x"09", + 662 => x"38", + 663 => x"5b", + 664 => x"5f", + 665 => x"1c", + 666 => x"06", + 667 => x"33", + 668 => x"70", + 669 => x"27", + 670 => x"07", + 671 => x"5b", + 672 => x"55", + 673 => x"38", + 674 => x"09", + 675 => x"38", + 676 => x"7a", + 677 => x"55", + 678 => x"9f", + 679 => x"32", + 680 => x"ae", + 681 => x"70", + 682 => x"2a", + 683 => x"51", + 684 => x"38", + 685 => x"5a", + 686 => x"77", + 687 => x"81", + 688 => x"1c", + 689 => x"55", + 690 => x"ff", + 691 => x"1e", + 692 => x"55", + 693 => x"83", + 694 => x"74", + 695 => x"7b", + 696 => x"3f", + 697 => x"ef", + 698 => x"7b", + 699 => x"2b", + 700 => x"54", + 701 => x"08", + 702 => x"f8", + 703 => x"08", + 704 => x"80", + 705 => x"33", + 706 => x"2e", + 707 => x"8b", + 708 => x"83", + 709 => x"06", + 710 => x"74", + 711 => x"7d", + 712 => x"88", + 713 => x"5b", + 714 => x"58", + 715 => x"9a", + 716 => x"81", + 717 => x"79", + 718 => x"5b", + 719 => x"31", + 720 => x"75", + 721 => x"38", + 722 => x"80", + 723 => x"7b", + 724 => x"3f", + 725 => x"88", + 726 => x"08", + 727 => x"39", + 728 => x"1c", + 729 => x"33", + 730 => x"a5", + 731 => x"33", + 732 => x"70", + 733 => x"56", + 734 => x"38", + 735 => x"39", + 736 => x"39", + 737 => x"d3", + 738 => x"88", + 739 => x"af", + 740 => x"0c", + 741 => x"04", + 742 => x"79", + 743 => x"82", + 744 => x"53", + 745 => x"51", + 746 => x"83", + 747 => x"80", + 748 => x"51", + 749 => x"88", + 750 => x"ff", + 751 => x"56", + 752 => x"d5", + 753 => x"06", + 754 => x"75", + 755 => x"77", + 756 => x"f6", + 757 => x"08", + 758 => x"94", + 759 => x"f8", + 760 => x"08", + 761 => x"06", + 762 => x"82", + 763 => x"38", + 764 => x"d2", + 765 => x"76", + 766 => x"3f", + 767 => x"88", + 768 => x"76", + 769 => x"3f", + 770 => x"ff", + 771 => x"74", + 772 => x"2e", + 773 => x"56", + 774 => x"89", + 775 => x"ed", + 776 => x"59", + 777 => x"0b", + 778 => x"0c", + 779 => x"88", + 780 => x"55", + 781 => x"82", + 782 => x"75", + 783 => x"70", + 784 => x"fe", + 785 => x"08", + 786 => x"57", + 787 => x"09", + 788 => x"38", + 789 => x"be", + 790 => x"75", + 791 => x"3f", + 792 => x"38", + 793 => x"55", + 794 => x"ac", + 795 => x"e4", + 796 => x"8a", + 797 => x"88", + 798 => x"52", + 799 => x"3f", + 800 => x"ff", + 801 => x"83", + 802 => x"06", + 803 => x"56", + 804 => x"76", + 805 => x"38", + 806 => x"8f", + 807 => x"8d", + 808 => x"75", + 809 => x"3f", + 810 => x"08", + 811 => x"95", + 812 => x"51", + 813 => x"88", + 814 => x"ff", + 815 => x"8c", + 816 => x"f3", + 817 => x"b6", + 818 => x"58", + 819 => x"33", + 820 => x"02", + 821 => x"05", + 822 => x"59", + 823 => x"3f", + 824 => x"ff", + 825 => x"05", + 826 => x"8c", + 827 => x"1a", + 828 => x"e0", + 829 => x"f1", + 830 => x"84", + 831 => x"3d", + 832 => x"f5", + 833 => x"08", + 834 => x"06", + 835 => x"38", + 836 => x"05", + 837 => x"3f", + 838 => x"7a", + 839 => x"3f", + 840 => x"ff", + 841 => x"71", + 842 => x"84", + 843 => x"84", + 844 => x"33", + 845 => x"31", + 846 => x"51", + 847 => x"3f", + 848 => x"05", + 849 => x"0c", + 850 => x"8a", + 851 => x"74", + 852 => x"26", + 853 => x"57", + 854 => x"76", + 855 => x"83", + 856 => x"86", + 857 => x"2e", + 858 => x"76", + 859 => x"83", + 860 => x"06", + 861 => x"3d", + 862 => x"f5", + 863 => x"08", + 864 => x"88", + 865 => x"08", + 866 => x"0c", + 867 => x"ff", + 868 => x"08", + 869 => x"2a", + 870 => x"0c", + 871 => x"81", + 872 => x"0b", + 873 => x"ac", + 874 => x"75", + 875 => x"3d", + 876 => x"3d", + 877 => x"0b", + 878 => x"55", + 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x"08", + 942 => x"3f", + 943 => x"88", + 944 => x"ff", + 945 => x"08", + 946 => x"0c", + 947 => x"83", + 948 => x"80", + 949 => x"55", + 950 => x"83", + 951 => x"74", + 952 => x"08", + 953 => x"53", + 954 => x"52", + 955 => x"b5", + 956 => x"fe", + 957 => x"16", + 958 => x"17", + 959 => x"31", + 960 => x"7c", + 961 => x"80", + 962 => x"38", + 963 => x"fe", + 964 => x"57", + 965 => x"8c", + 966 => x"fb", + 967 => x"90", + 968 => x"87", + 969 => x"0c", + 970 => x"e4", + 971 => x"94", + 972 => x"80", + 973 => x"c0", + 974 => x"8c", + 975 => x"87", + 976 => x"0c", + 977 => x"f9", + 978 => x"08", + 979 => x"98", + 980 => x"3f", + 981 => x"38", + 982 => x"88", + 983 => x"98", + 984 => x"87", + 985 => x"53", + 986 => x"74", + 987 => x"3f", + 988 => x"38", + 989 => x"80", + 990 => x"73", + 991 => x"39", + 992 => x"73", + 993 => x"fb", + 994 => x"ff", + 995 => x"00", + 996 => x"ff", + 997 => x"ff", + 998 => x"4f", + 999 => x"49", + 1000 => x"52", + 1001 => x"00", + 1002 => x"00", + 2048 => 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=> x"38", + 2578 => x"70", + 2579 => x"81", + 2580 => x"80", + 2581 => x"05", + 2582 => x"75", + 2583 => x"70", + 2584 => x"0c", + 2585 => x"04", + 2586 => x"76", + 2587 => x"80", + 2588 => x"86", + 2589 => x"52", + 2590 => x"c4", + 2591 => x"c8", + 2592 => x"80", + 2593 => x"74", + 2594 => x"93", + 2595 => x"3d", + 2596 => x"3d", + 2597 => x"11", + 2598 => x"5b", + 2599 => x"79", + 2600 => x"bf", + 2601 => x"33", + 2602 => x"82", + 2603 => x"26", + 2604 => x"84", + 2605 => x"83", + 2606 => x"26", + 2607 => x"85", + 2608 => x"84", + 2609 => x"26", + 2610 => x"86", + 2611 => x"85", + 2612 => x"26", + 2613 => x"88", + 2614 => x"86", + 2615 => x"e7", + 2616 => x"38", + 2617 => x"5a", + 2618 => x"87", + 2619 => x"f3", + 2620 => x"22", + 2621 => x"22", + 2622 => x"33", + 2623 => x"33", + 2624 => x"33", + 2625 => x"33", + 2626 => x"33", + 2627 => x"52", + 2628 => x"51", + 2629 => x"87", + 2630 => x"5b", + 2631 => x"7b", + 2632 => x"98", + 2633 => x"1c", + 2634 => x"98", + 2635 => x"1c", + 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x"51", + 2989 => x"82", + 2990 => x"33", + 2991 => x"80", + 2992 => x"81", + 2993 => x"81", + 2994 => x"88", + 2995 => x"f8", + 2996 => x"d1", + 2997 => x"dc", + 2998 => x"84", + 2999 => x"54", + 3000 => x"53", + 3001 => x"b7", + 3002 => x"52", + 3003 => x"51", + 3004 => x"88", + 3005 => x"81", + 3006 => x"88", + 3007 => x"15", + 3008 => x"f9", + 3009 => x"97", + 3010 => x"08", + 3011 => x"98", + 3012 => x"3f", + 3013 => x"04", + 3014 => x"02", + 3015 => x"52", + 3016 => x"bb", + 3017 => x"10", + 3018 => x"f0", + 3019 => x"71", + 3020 => x"fa", + 3021 => x"bb", + 3022 => x"81", + 3023 => x"f7", + 3024 => x"39", + 3025 => x"51", + 3026 => x"9a", + 3027 => x"d8", + 3028 => x"3f", + 3029 => x"fa", + 3030 => x"97", + 3031 => x"81", + 3032 => x"f7", + 3033 => x"3d", + 3034 => x"88", + 3035 => x"80", + 3036 => x"96", + 3037 => x"ff", + 3038 => x"c0", + 3039 => x"08", + 3040 => x"72", + 3041 => x"07", + 3042 => x"80", + 3043 => x"83", + 3044 => x"ff", + 3045 => x"c0", + 3046 => x"08", + 3047 => x"0c", + 3048 => x"0c", + 3049 => x"82", + 3050 => x"06", + 3051 => x"80", + 3052 => x"51", + 3053 => x"04", + 3054 => x"08", + 3055 => x"84", + 3056 => x"3d", + 3057 => x"05", + 3058 => x"8a", + 3059 => x"06", + 3060 => x"51", + 3061 => x"93", + 3062 => x"2e", + 3063 => x"93", + 3064 => x"72", + 3065 => x"93", + 3066 => x"05", + 3067 => x"0c", + 3068 => x"93", + 3069 => x"2e", + 3070 => x"51", + 3071 => x"08", + 3072 => x"84", + 3073 => x"fe", + 3074 => x"97", + 3075 => x"93", + 3076 => x"82", + 3077 => x"54", + 3078 => x"3f", + 3079 => x"d8", + 3080 => x"0d", + 3081 => x"0d", + 3082 => x"53", + 3083 => x"2e", + 3084 => x"70", + 3085 => x"33", + 3086 => x"3f", + 3087 => x"71", + 3088 => x"3d", + 3089 => x"3d", + 3090 => x"93", + 3091 => x"82", + 3092 => x"71", + 3093 => x"53", + 3094 => x"91", + 3095 => x"81", + 3096 => x"51", + 3097 => x"72", + 3098 => x"f1", + 3099 => x"93", + 3100 => x"3d", + 3101 => x"3d", + 3102 => x"5d", + 3103 => x"81", + 3104 => x"56", + 3105 => x"85", + 3106 => x"a5", + 3107 => x"75", + 3108 => x"3f", + 3109 => x"70", + 3110 => x"05", + 3111 => x"5e", + 3112 => x"2e", + 3113 => x"8c", + 3114 => x"70", + 3115 => x"33", + 3116 => x"39", + 3117 => x"09", + 3118 => x"38", + 3119 => x"81", + 3120 => x"57", + 3121 => x"2e", + 3122 => x"92", + 3123 => x"1d", + 3124 => x"70", + 3125 => x"33", + 3126 => x"53", + 3127 => x"16", + 3128 => x"26", + 3129 => x"8a", + 3130 => x"05", + 3131 => x"05", + 3132 => x"11", + 3133 => x"89", + 3134 => x"38", + 3135 => x"32", + 3136 => x"72", + 3137 => x"78", + 3138 => x"70", + 3139 => x"07", + 3140 => x"07", + 3141 => x"52", + 3142 => x"80", + 3143 => x"7c", + 3144 => x"70", + 3145 => x"33", + 3146 => x"80", + 3147 => x"38", + 3148 => x"e0", + 3149 => x"38", + 3150 => x"81", + 3151 => x"53", + 3152 => x"53", + 3153 => x"81", + 3154 => x"10", + 3155 => x"dc", + 3156 => x"08", + 3157 => x"1d", + 3158 => x"5d", + 3159 => x"33", + 3160 => x"74", + 3161 => x"81", + 3162 => x"70", + 3163 => x"54", + 3164 => x"7c", + 3165 => x"81", + 3166 => x"72", + 3167 => x"81", + 3168 => x"72", + 3169 => x"38", + 3170 => x"81", + 3171 => x"51", + 3172 => x"75", + 3173 => x"81", + 3174 => x"79", + 3175 => x"38", + 3176 => x"81", + 3177 => x"15", + 3178 => x"7a", + 3179 => x"38", + 3180 => x"8e", + 3181 => x"15", + 3182 => x"73", + 3183 => x"fd", + 3184 => x"84", + 3185 => x"33", + 3186 => x"fb", + 3187 => x"ad", + 3188 => x"95", + 3189 => x"91", + 3190 => x"8d", + 3191 => x"89", + 3192 => x"fb", + 3193 => x"95", + 3194 => x"2a", + 3195 => x"51", + 3196 => x"2e", + 3197 => x"84", + 3198 => x"59", + 3199 => x"39", + 3200 => x"2e", + 3201 => x"8b", + 3202 => x"1d", + 3203 => x"5d", + 3204 => x"7b", + 3205 => x"08", + 3206 => x"74", + 3207 => x"70", + 3208 => x"07", + 3209 => x"80", + 3210 => x"51", + 3211 => x"72", + 3212 => x"38", + 3213 => x"90", + 3214 => x"80", + 3215 => x"76", + 3216 => x"3f", + 3217 => x"08", + 3218 => x"7b", + 3219 => x"55", + 3220 => x"82", + 3221 => x"57", + 3222 => x"99", + 3223 => x"16", + 3224 => x"06", + 3225 => x"75", + 3226 => x"89", + 3227 => x"70", + 3228 => x"56", + 3229 => x"78", + 3230 => x"b0", + 3231 => x"72", + 3232 => x"18", + 3233 => x"79", + 3234 => x"70", + 3235 => x"06", + 3236 => x"58", + 3237 => x"38", + 3238 => x"70", + 3239 => x"53", + 3240 => x"8e", + 3241 => x"78", + 3242 => x"53", + 3243 => x"81", + 3244 => x"7d", + 3245 => x"54", + 3246 => x"83", + 3247 => x"7c", + 3248 => x"81", + 3249 => x"72", + 3250 => x"81", + 3251 => x"72", + 3252 => x"38", + 3253 => x"81", + 3254 => x"51", + 3255 => x"75", + 3256 => x"81", + 3257 => x"79", + 3258 => x"38", + 3259 => x"3d", + 3260 => x"70", + 3261 => x"58", + 3262 => x"77", + 3263 => x"81", + 3264 => x"72", + 3265 => x"f5", + 3266 => x"f9", + 3267 => x"81", + 3268 => x"79", + 3269 => x"38", + 3270 => x"96", + 3271 => x"fd", + 3272 => x"3d", + 3273 => x"05", + 3274 => x"52", + 3275 => x"c6", + 3276 => x"0d", + 3277 => x"0d", + 3278 => x"e0", + 3279 => x"88", + 3280 => x"51", + 3281 => x"82", + 3282 => x"53", + 3283 => x"80", + 3284 => x"e0", + 3285 => x"0d", + 3286 => x"0d", + 3287 => x"08", + 3288 => x"d8", + 3289 => x"88", + 3290 => x"52", + 3291 => x"3f", + 3292 => x"d8", + 3293 => x"0d", + 3294 => x"0d", + 3295 => x"57", + 3296 => x"93", + 3297 => x"2e", + 3298 => x"86", + 3299 => x"80", + 3300 => x"55", + 3301 => x"08", + 3302 => x"82", + 3303 => x"81", + 3304 => x"73", + 3305 => x"38", + 3306 => x"80", + 3307 => x"88", + 3308 => x"76", + 3309 => x"07", + 3310 => x"80", + 3311 => x"54", + 3312 => x"80", + 3313 => x"ff", + 3314 => x"ff", + 3315 => x"f7", + 3316 => x"39", + 3317 => x"ff", + 3318 => x"16", + 3319 => x"25", + 3320 => x"76", + 3321 => x"72", + 3322 => x"74", + 3323 => x"52", + 3324 => x"3f", + 3325 => x"74", + 3326 => x"72", + 3327 => x"f7", + 3328 => x"53", + 3329 => x"c8", + 3330 => x"0d", + 3331 => x"0d", + 3332 => x"08", + 3333 => x"dc", + 3334 => x"76", + 3335 => x"d9", + 3336 => x"93", + 3337 => x"3d", + 3338 => x"3d", + 3339 => x"5a", + 3340 => x"7a", + 3341 => x"70", + 3342 => x"58", + 3343 => x"09", + 3344 => x"38", + 3345 => x"05", + 3346 => x"08", + 3347 => x"53", + 3348 => x"f0", + 3349 => x"2e", + 3350 => x"8e", + 3351 => x"08", + 3352 => x"75", + 3353 => x"56", + 3354 => x"b0", + 3355 => x"06", + 3356 => x"74", + 3357 => x"75", + 3358 => x"70", + 3359 => x"73", + 3360 => x"9a", + 3361 => x"f8", + 3362 => x"06", + 3363 => x"0b", + 3364 => x"0c", + 3365 => x"33", + 3366 => x"80", + 3367 => x"75", + 3368 => x"76", + 3369 => x"70", + 3370 => x"57", + 3371 => x"56", + 3372 => x"81", + 3373 => x"14", + 3374 => x"88", + 3375 => x"27", + 3376 => x"f3", + 3377 => x"53", + 3378 => x"89", + 3379 => x"38", + 3380 => x"56", + 3381 => x"80", + 3382 => x"39", + 3383 => x"56", + 3384 => x"80", + 3385 => x"e0", + 3386 => x"38", + 3387 => x"81", + 3388 => x"53", + 3389 => x"81", + 3390 => x"53", + 3391 => x"8e", + 3392 => x"70", + 3393 => x"55", + 3394 => x"27", + 3395 => x"77", + 3396 => x"76", + 3397 => x"75", + 3398 => x"76", + 3399 => x"70", + 3400 => x"56", + 3401 => x"ff", + 3402 => x"80", + 3403 => x"75", + 3404 => x"79", + 3405 => x"75", + 3406 => x"0c", + 3407 => x"04", + 3408 => x"7a", + 3409 => x"80", + 3410 => x"75", + 3411 => x"56", + 3412 => x"a0", + 3413 => x"06", + 3414 => x"08", + 3415 => x"0c", + 3416 => x"33", + 3417 => x"a0", + 3418 => x"73", + 3419 => x"81", + 3420 => x"81", + 3421 => x"76", + 3422 => x"70", + 3423 => x"58", + 3424 => x"09", + 3425 => x"d3", + 3426 => x"81", + 3427 => x"74", + 3428 => x"55", + 3429 => x"e2", + 3430 => x"73", + 3431 => x"09", + 3432 => x"38", + 3433 => x"14", + 3434 => x"08", + 3435 => x"54", + 3436 => x"39", + 3437 => x"81", + 3438 => x"75", + 3439 => x"56", + 3440 => x"39", + 3441 => x"74", + 3442 => x"38", + 3443 => x"80", + 3444 => x"89", + 3445 => x"38", + 3446 => x"d0", + 3447 => x"56", + 3448 => x"80", + 3449 => x"39", + 3450 => x"e1", + 3451 => x"80", + 3452 => x"57", + 3453 => x"74", + 3454 => x"38", + 3455 => x"27", + 3456 => x"14", + 3457 => x"06", + 3458 => x"14", + 3459 => x"06", + 3460 => x"74", + 3461 => x"f9", + 3462 => x"ff", + 3463 => x"89", + 3464 => x"38", + 3465 => x"c5", + 3466 => x"29", + 3467 => x"81", + 3468 => x"75", + 3469 => x"56", + 3470 => x"a0", + 3471 => x"38", + 3472 => x"84", + 3473 => x"56", + 3474 => x"81", + 3475 => x"93", + 3476 => x"3d", + 3477 => x"3d", + 3478 => x"05", + 3479 => x"52", + 3480 => x"87", + 3481 => x"84", + 3482 => x"71", + 3483 => x"0c", + 3484 => x"04", + 3485 => x"02", + 3486 => x"02", + 3487 => x"05", + 3488 => x"83", + 3489 => x"26", + 3490 => x"72", + 3491 => x"c0", + 3492 => x"51", + 3493 => x"80", + 3494 => x"81", + 3495 => x"71", + 3496 => x"29", + 3497 => x"8c", + 3498 => x"71", + 3499 => x"87", + 3500 => x"0c", + 3501 => x"c0", + 3502 => x"71", + 3503 => x"06", + 3504 => x"80", + 3505 => x"73", + 3506 => x"ef", + 3507 => x"29", + 3508 => x"8c", + 3509 => x"fc", + 3510 => x"53", + 3511 => x"38", + 3512 => x"8c", + 3513 => x"80", + 3514 => x"71", + 3515 => x"14", + 3516 => x"84", + 3517 => x"70", + 3518 => x"0c", + 3519 => x"04", + 3520 => x"61", + 3521 => x"8c", + 3522 => x"05", + 3523 => x"5d", + 3524 => x"52", + 3525 => x"3f", + 3526 => x"08", + 3527 => x"55", + 3528 => x"ac", + 3529 => x"58", + 3530 => x"98", + 3531 => x"2b", + 3532 => x"8c", + 3533 => x"92", + 3534 => x"42", + 3535 => x"56", + 3536 => x"87", + 3537 => x"1a", + 3538 => x"52", + 3539 => x"74", + 3540 => x"2a", + 3541 => x"51", + 3542 => x"80", + 3543 => x"78", + 3544 => x"78", + 3545 => x"5a", + 3546 => x"57", + 3547 => x"52", + 3548 => x"87", + 3549 => x"52", + 3550 => x"75", + 3551 => x"80", + 3552 => x"76", + 3553 => x"99", + 3554 => x"0c", + 3555 => x"8c", + 3556 => x"08", + 3557 => x"51", + 3558 => x"38", + 3559 => x"8d", + 3560 => x"1c", + 3561 => x"81", + 3562 => x"53", + 3563 => x"2e", + 3564 => x"fc", + 3565 => x"52", + 3566 => x"7e", + 3567 => x"80", + 3568 => x"80", + 3569 => x"71", + 3570 => x"38", + 3571 => x"54", + 3572 => x"c8", + 3573 => x"0d", + 3574 => x"0d", + 3575 => x"02", + 3576 => x"05", + 3577 => x"5c", + 3578 => x"52", + 3579 => x"3f", + 3580 => x"08", + 3581 => x"55", + 3582 => x"ae", + 3583 => x"87", + 3584 => x"73", + 3585 => x"c0", + 3586 => x"87", + 3587 => x"12", + 3588 => x"57", + 3589 => x"76", + 3590 => x"92", + 3591 => x"71", + 3592 => x"75", + 3593 => x"74", + 3594 => x"2a", + 3595 => x"51", + 3596 => x"80", + 3597 => x"76", + 3598 => x"58", + 3599 => x"81", + 3600 => x"81", + 3601 => x"06", + 3602 => x"80", + 3603 => x"75", + 3604 => x"d3", + 3605 => x"52", + 3606 => x"87", + 3607 => x"80", + 3608 => x"81", + 3609 => x"c0", + 3610 => x"53", + 3611 => x"82", + 3612 => x"71", + 3613 => x"1a", + 3614 => x"81", + 3615 => x"ff", + 3616 => x"1d", + 3617 => x"79", + 3618 => x"38", + 3619 => x"80", + 3620 => x"87", + 3621 => x"26", + 3622 => x"73", + 3623 => x"06", + 3624 => x"2e", + 3625 => x"52", + 3626 => x"82", + 3627 => x"8f", + 3628 => x"f7", + 3629 => x"02", + 3630 => x"05", + 3631 => x"05", + 3632 => x"71", + 3633 => x"56", + 3634 => x"82", + 3635 => x"81", + 3636 => x"54", + 3637 => x"81", + 3638 => x"2e", + 3639 => x"74", + 3640 => x"72", + 3641 => x"38", + 3642 => x"83", + 3643 => x"a0", + 3644 => x"29", + 3645 => x"8c", + 3646 => x"51", + 3647 => x"88", + 3648 => x"0c", + 3649 => x"39", + 3650 => x"0c", + 3651 => x"39", + 3652 => x"82", + 3653 => x"8b", + 3654 => x"ff", + 3655 => x"70", + 3656 => x"33", + 3657 => x"72", + 3658 => x"c8", + 3659 => x"52", + 3660 => x"04", + 3661 => x"75", + 3662 => x"82", + 3663 => x"90", + 3664 => x"2b", + 3665 => x"33", + 3666 => x"33", + 3667 => x"07", + 3668 => x"0c", + 3669 => x"54", + 3670 => x"0d", + 3671 => x"0d", + 3672 => x"05", + 3673 => x"52", + 3674 => x"70", + 3675 => x"34", + 3676 => x"51", + 3677 => x"83", + 3678 => x"ff", + 3679 => x"75", + 3680 => x"72", + 3681 => x"54", + 3682 => x"2a", + 3683 => x"70", + 3684 => x"34", + 3685 => x"51", + 3686 => x"81", + 3687 => x"70", + 3688 => x"70", + 3689 => x"3d", + 3690 => x"3d", + 3691 => x"77", + 3692 => x"70", + 3693 => x"38", + 3694 => x"05", + 3695 => x"70", + 3696 => x"34", + 3697 => x"70", + 3698 => x"3d", + 3699 => x"3d", + 3700 => x"76", + 3701 => x"72", + 3702 => x"05", + 3703 => x"11", + 3704 => x"38", + 3705 => x"04", + 3706 => x"78", + 3707 => x"56", + 3708 => x"81", + 3709 => x"74", + 3710 => x"56", + 3711 => x"31", + 3712 => x"52", + 3713 => x"80", + 3714 => x"71", + 3715 => x"38", + 3716 => x"c8", + 3717 => x"0d", + 3718 => x"0d", + 3719 => x"33", + 3720 => x"70", + 3721 => x"38", + 3722 => x"94", + 3723 => x"70", + 3724 => x"70", + 3725 => x"38", + 3726 => x"09", + 3727 => x"38", + 3728 => x"93", + 3729 => x"3d", + 3730 => x"0b", + 3731 => x"0c", + 3732 => x"82", + 3733 => x"04", + 3734 => x"79", + 3735 => x"83", + 3736 => x"58", + 3737 => x"80", + 3738 => x"54", + 3739 => x"53", + 3740 => x"53", + 3741 => x"52", + 3742 => x"3f", + 3743 => x"08", + 3744 => x"81", + 3745 => x"82", + 3746 => x"83", + 3747 => x"16", + 3748 => x"08", + 3749 => x"9c", + 3750 => x"a4", + 3751 => x"33", + 3752 => x"2e", + 3753 => x"98", + 3754 => x"b0", + 3755 => x"17", + 3756 => x"76", + 3757 => x"33", + 3758 => x"3f", + 3759 => x"58", + 3760 => x"c8", + 3761 => x"0d", + 3762 => x"0d", + 3763 => x"57", + 3764 => x"17", + 3765 => x"af", + 3766 => x"fe", + 3767 => x"93", + 3768 => x"82", + 3769 => x"9f", + 3770 => x"74", + 3771 => x"52", + 3772 => x"51", + 3773 => x"82", + 3774 => x"80", + 3775 => x"ff", + 3776 => x"74", + 3777 => x"75", + 3778 => x"0c", + 3779 => x"04", + 3780 => x"7a", + 3781 => x"fe", + 3782 => x"93", + 3783 => x"82", + 3784 => x"81", + 3785 => x"33", + 3786 => x"2e", + 3787 => x"80", + 3788 => x"17", + 3789 => x"81", + 3790 => x"06", + 3791 => x"84", + 3792 => x"93", + 3793 => x"b4", + 3794 => x"56", + 3795 => x"82", + 3796 => x"84", + 3797 => x"fc", + 3798 => x"8b", + 3799 => x"52", + 3800 => x"97", + 3801 => x"85", + 3802 => x"84", + 3803 => x"fc", + 3804 => x"17", + 3805 => x"9c", + 3806 => x"ff", + 3807 => x"08", + 3808 => x"17", + 3809 => x"3f", + 3810 => x"81", + 3811 => x"19", + 3812 => x"53", + 3813 => x"17", + 3814 => x"bd", + 3815 => x"18", + 3816 => x"80", + 3817 => x"33", + 3818 => x"3f", + 3819 => x"08", + 3820 => x"38", + 3821 => x"82", + 3822 => x"8a", + 3823 => x"fb", + 3824 => x"fe", + 3825 => x"08", + 3826 => x"56", + 3827 => x"74", + 3828 => x"38", + 3829 => x"70", + 3830 => x"16", + 3831 => x"53", + 3832 => x"c8", + 3833 => x"0d", + 3834 => x"0d", + 3835 => x"08", + 3836 => x"81", + 3837 => x"38", + 3838 => x"75", + 3839 => x"81", + 3840 => x"39", + 3841 => x"54", + 3842 => x"2e", + 3843 => x"72", + 3844 => x"38", + 3845 => x"8d", + 3846 => x"39", + 3847 => x"81", + 3848 => x"b6", + 3849 => x"2a", + 3850 => x"2a", + 3851 => x"05", + 3852 => x"57", + 3853 => x"82", + 3854 => x"81", + 3855 => x"83", + 3856 => x"b4", + 3857 => x"19", + 3858 => x"a4", + 3859 => x"55", + 3860 => x"59", + 3861 => x"3f", + 3862 => x"08", + 3863 => x"76", + 3864 => x"14", + 3865 => x"70", + 3866 => x"07", + 3867 => x"71", + 3868 => x"52", + 3869 => x"72", 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x"81", + 3929 => x"34", + 3930 => x"a4", + 3931 => x"52", + 3932 => x"d5", + 3933 => x"c8", + 3934 => x"93", + 3935 => x"a4", + 3936 => x"ff", + 3937 => x"11", + 3938 => x"78", + 3939 => x"55", + 3940 => x"8f", + 3941 => x"2a", + 3942 => x"8f", + 3943 => x"f0", + 3944 => x"73", + 3945 => x"0b", + 3946 => x"80", + 3947 => x"88", + 3948 => x"08", + 3949 => x"51", + 3950 => x"82", + 3951 => x"57", + 3952 => x"08", + 3953 => x"75", + 3954 => x"06", + 3955 => x"83", + 3956 => x"05", + 3957 => x"f7", + 3958 => x"0b", + 3959 => x"80", + 3960 => x"87", + 3961 => x"08", + 3962 => x"51", + 3963 => x"82", + 3964 => x"57", + 3965 => x"08", + 3966 => x"f0", + 3967 => x"82", + 3968 => x"06", + 3969 => x"05", + 3970 => x"54", + 3971 => x"3f", + 3972 => x"08", + 3973 => x"76", + 3974 => x"51", + 3975 => x"81", + 3976 => x"34", + 3977 => x"c8", + 3978 => x"0d", + 3979 => x"0d", + 3980 => x"72", + 3981 => x"55", + 3982 => x"27", + 3983 => x"15", + 3984 => x"86", + 3985 => x"81", + 3986 => x"80", + 3987 => x"ff", + 3988 => x"74", + 3989 => x"3f", + 3990 => x"08", + 3991 => x"c8", + 3992 => x"38", + 3993 => x"56", + 3994 => x"81", + 3995 => x"39", + 3996 => x"08", + 3997 => x"39", + 3998 => x"51", + 3999 => x"82", + 4000 => x"56", + 4001 => x"08", + 4002 => x"c9", + 4003 => x"c8", + 4004 => x"d2", + 4005 => x"c8", + 4006 => x"cf", + 4007 => x"73", + 4008 => x"fc", + 4009 => x"93", + 4010 => x"38", + 4011 => x"fe", + 4012 => x"15", + 4013 => x"93", + 4014 => x"08", + 4015 => x"16", + 4016 => x"33", + 4017 => x"73", + 4018 => x"75", + 4019 => x"08", + 4020 => x"a4", + 4021 => x"75", + 4022 => x"0c", + 4023 => x"04", + 4024 => x"7d", + 4025 => x"5b", + 4026 => x"95", + 4027 => x"08", + 4028 => x"2e", + 4029 => x"19", + 4030 => x"b7", + 4031 => x"b3", + 4032 => x"7b", + 4033 => x"3f", + 4034 => x"82", + 4035 => x"27", + 4036 => x"82", + 4037 => x"55", + 4038 => x"08", + 4039 => x"db", + 4040 => x"c8", + 4041 => x"19", + 4042 => x"c8", + 4043 => x"cb", + 4044 => x"80", + 4045 => x"08", + 4046 => x"bf", + 4047 => x"77", + 4048 => x"81", + 4049 => x"38", + 4050 => x"98", + 4051 => x"26", + 4052 => x"57", + 4053 => x"51", + 4054 => x"82", + 4055 => x"56", + 4056 => x"93", + 4057 => x"2e", + 4058 => x"86", + 4059 => x"c8", + 4060 => x"ff", + 4061 => x"70", + 4062 => x"25", + 4063 => x"79", + 4064 => x"56", + 4065 => x"f3", + 4066 => x"2e", + 4067 => x"19", + 4068 => x"76", + 4069 => x"75", + 4070 => x"27", + 4071 => x"58", + 4072 => x"80", + 4073 => x"57", + 4074 => x"98", + 4075 => x"26", + 4076 => x"57", + 4077 => x"81", + 4078 => x"52", + 4079 => x"a9", + 4080 => x"c8", + 4081 => x"93", + 4082 => x"2e", + 4083 => x"5a", + 4084 => x"08", + 4085 => x"81", + 4086 => x"82", + 4087 => x"5a", + 4088 => x"70", + 4089 => x"07", + 4090 => x"7d", + 4091 => x"56", + 4092 => x"ff", + 4093 => x"2e", + 4094 => x"ff", + 4095 => x"55", + 4096 => x"ff", + 4097 => x"78", + 4098 => x"3f", + 4099 => x"08", + 4100 => x"08", + 4101 => x"93", + 4102 => x"80", + 4103 => x"70", + 4104 => x"2a", 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x"72", + 4164 => x"38", + 4165 => x"ae", + 4166 => x"18", + 4167 => x"08", + 4168 => x"38", + 4169 => x"82", + 4170 => x"38", + 4171 => x"54", + 4172 => x"74", + 4173 => x"82", + 4174 => x"22", + 4175 => x"79", + 4176 => x"38", + 4177 => x"98", + 4178 => x"d1", + 4179 => x"22", + 4180 => x"54", + 4181 => x"26", + 4182 => x"52", + 4183 => x"89", + 4184 => x"c8", + 4185 => x"93", + 4186 => x"2e", + 4187 => x"0b", + 4188 => x"08", + 4189 => x"98", + 4190 => x"93", + 4191 => x"86", + 4192 => x"80", + 4193 => x"73", + 4194 => x"73", + 4195 => x"73", + 4196 => x"f4", + 4197 => x"93", + 4198 => x"18", + 4199 => x"18", + 4200 => x"98", + 4201 => x"2e", + 4202 => x"39", + 4203 => x"39", + 4204 => x"98", + 4205 => x"98", + 4206 => x"83", + 4207 => x"b4", + 4208 => x"0c", + 4209 => x"82", + 4210 => x"8a", + 4211 => x"f9", + 4212 => x"7b", + 4213 => x"13", + 4214 => x"59", + 4215 => x"f0", + 4216 => x"27", + 4217 => x"0b", + 4218 => x"84", + 4219 => x"08", + 4220 => x"da", + 4221 => x"ff", + 4222 => x"81", + 4223 => x"15", + 4224 => x"98", + 4225 => x"15", + 4226 => x"75", + 4227 => x"18", + 4228 => x"77", + 4229 => x"a6", + 4230 => x"16", + 4231 => x"81", + 4232 => x"17", + 4233 => x"77", + 4234 => x"51", + 4235 => x"8e", + 4236 => x"08", + 4237 => x"f3", + 4238 => x"93", + 4239 => x"82", + 4240 => x"82", + 4241 => x"27", + 4242 => x"81", + 4243 => x"c8", + 4244 => x"80", + 4245 => x"17", + 4246 => x"c8", + 4247 => x"cc", + 4248 => x"38", + 4249 => x"0c", + 4250 => x"e2", + 4251 => x"08", + 4252 => x"f8", + 4253 => x"93", + 4254 => x"87", + 4255 => x"c8", + 4256 => x"80", + 4257 => x"53", + 4258 => x"08", + 4259 => x"38", + 4260 => x"93", + 4261 => x"2e", + 4262 => x"93", + 4263 => x"76", + 4264 => x"3f", + 4265 => x"93", + 4266 => x"38", + 4267 => x"0c", + 4268 => x"51", + 4269 => x"82", + 4270 => x"98", + 4271 => x"90", + 4272 => x"83", + 4273 => x"b4", + 4274 => x"0c", + 4275 => x"82", + 4276 => x"89", + 4277 => x"f8", + 4278 => x"7c", + 4279 => x"5a", + 4280 => x"75", + 4281 => x"3f", + 4282 => x"08", + 4283 => x"c8", + 4284 => x"38", + 4285 => x"08", + 4286 => x"08", + 4287 => x"ef", + 4288 => x"93", + 4289 => x"82", + 4290 => x"80", + 4291 => x"93", + 4292 => x"17", + 4293 => x"51", + 4294 => x"81", + 4295 => x"81", + 4296 => x"81", + 4297 => x"70", + 4298 => x"07", + 4299 => x"80", + 4300 => x"81", + 4301 => x"79", + 4302 => x"83", + 4303 => x"81", + 4304 => x"fd", + 4305 => x"93", + 4306 => x"82", + 4307 => x"80", + 4308 => x"38", + 4309 => x"09", + 4310 => x"38", + 4311 => x"82", + 4312 => x"8a", + 4313 => x"fd", + 4314 => x"9a", + 4315 => x"eb", + 4316 => x"93", + 4317 => x"ff", + 4318 => x"70", + 4319 => x"53", + 4320 => x"09", + 4321 => x"38", + 4322 => x"eb", + 4323 => x"93", + 4324 => x"2b", + 4325 => x"72", + 4326 => x"0c", + 4327 => x"04", + 4328 => x"77", + 4329 => x"ff", + 4330 => x"9a", + 4331 => x"55", + 4332 => x"76", + 4333 => x"53", + 4334 => x"09", + 4335 => x"38", + 4336 => x"52", + 4337 => x"eb", + 4338 => x"3d", + 4339 => x"3d", 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x"db", + 4399 => x"08", + 4400 => x"bf", + 4401 => x"73", + 4402 => x"8b", + 4403 => x"83", + 4404 => x"06", + 4405 => x"73", + 4406 => x"53", + 4407 => x"74", + 4408 => x"3f", + 4409 => x"08", + 4410 => x"38", + 4411 => x"51", + 4412 => x"82", + 4413 => x"57", + 4414 => x"08", + 4415 => x"9c", + 4416 => x"73", + 4417 => x"0c", + 4418 => x"04", + 4419 => x"77", + 4420 => x"54", + 4421 => x"51", + 4422 => x"82", + 4423 => x"55", + 4424 => x"08", + 4425 => x"14", + 4426 => x"51", + 4427 => x"82", + 4428 => x"55", + 4429 => x"08", + 4430 => x"53", + 4431 => x"08", + 4432 => x"08", + 4433 => x"3f", + 4434 => x"14", + 4435 => x"08", + 4436 => x"3f", + 4437 => x"17", + 4438 => x"93", + 4439 => x"3d", + 4440 => x"3d", + 4441 => x"08", + 4442 => x"54", + 4443 => x"53", + 4444 => x"82", + 4445 => x"54", + 4446 => x"08", + 4447 => x"13", + 4448 => x"73", + 4449 => x"83", + 4450 => x"82", + 4451 => x"86", + 4452 => x"fa", + 4453 => x"7a", + 4454 => x"0b", + 4455 => x"98", + 4456 => x"2e", + 4457 => x"80", + 4458 => x"9c", + 4459 => x"70", + 4460 => x"56", + 4461 => x"a0", + 4462 => x"72", + 4463 => x"81", + 4464 => x"81", + 4465 => x"89", + 4466 => x"06", + 4467 => x"15", + 4468 => x"ae", + 4469 => x"34", + 4470 => x"75", + 4471 => x"52", + 4472 => x"34", + 4473 => x"8a", + 4474 => x"38", + 4475 => x"05", + 4476 => x"81", + 4477 => x"17", + 4478 => x"12", + 4479 => x"34", + 4480 => x"9c", + 4481 => x"ac", + 4482 => x"c8", + 4483 => x"9c", + 4484 => x"05", + 4485 => x"3f", + 4486 => x"08", + 4487 => x"9c", + 4488 => x"05", + 4489 => x"3f", + 4490 => x"08", + 4491 => x"88", + 4492 => x"f5", + 4493 => x"70", + 4494 => x"05", + 4495 => x"8b", + 4496 => x"7a", + 4497 => x"3f", + 4498 => x"58", + 4499 => x"55", + 4500 => x"2e", + 4501 => x"80", + 4502 => x"17", + 4503 => x"19", + 4504 => x"70", + 4505 => x"2a", + 4506 => x"07", + 4507 => x"59", + 4508 => x"8c", + 4509 => x"54", + 4510 => x"81", + 4511 => x"39", + 4512 => x"70", + 4513 => x"dc", + 4514 => x"70", + 4515 => x"2a", + 4516 => x"51", + 4517 => x"2e", + 4518 => x"54", + 4519 => x"82", + 4520 => x"19", + 4521 => x"54", + 4522 => x"83", + 4523 => x"73", + 4524 => x"80", + 4525 => x"39", + 4526 => x"33", + 4527 => x"57", + 4528 => x"27", + 4529 => x"75", + 4530 => x"30", + 4531 => x"32", + 4532 => x"80", + 4533 => x"25", + 4534 => x"56", + 4535 => x"80", + 4536 => x"84", + 4537 => x"57", + 4538 => x"70", + 4539 => x"5a", + 4540 => x"09", + 4541 => x"38", + 4542 => x"77", + 4543 => x"51", + 4544 => x"80", + 4545 => x"81", + 4546 => x"81", + 4547 => x"07", + 4548 => x"38", + 4549 => x"75", + 4550 => x"30", + 4551 => x"7a", + 4552 => x"51", + 4553 => x"80", + 4554 => x"79", + 4555 => x"30", + 4556 => x"70", + 4557 => x"25", + 4558 => x"07", + 4559 => x"51", + 4560 => x"b1", + 4561 => x"8b", + 4562 => x"39", + 4563 => x"54", + 4564 => x"8c", + 4565 => x"ff", + 4566 => x"f8", + 4567 => x"54", + 4568 => x"e6", + 4569 => x"c8", + 4570 => x"b9", + 4571 => x"70", + 4572 => x"71", + 4573 => x"54", + 4574 => x"82", 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x"38", + 4634 => x"74", + 4635 => x"d4", + 4636 => x"88", + 4637 => x"70", + 4638 => x"72", + 4639 => x"38", + 4640 => x"ab", + 4641 => x"52", + 4642 => x"ee", + 4643 => x"c8", + 4644 => x"aa", + 4645 => x"81", + 4646 => x"3d", + 4647 => x"75", + 4648 => x"3f", + 4649 => x"08", + 4650 => x"c8", + 4651 => x"38", + 4652 => x"c6", + 4653 => x"c8", + 4654 => x"33", + 4655 => x"93", + 4656 => x"2e", + 4657 => x"82", + 4658 => x"84", + 4659 => x"06", + 4660 => x"73", + 4661 => x"81", + 4662 => x"72", + 4663 => x"38", + 4664 => x"70", + 4665 => x"53", + 4666 => x"ff", + 4667 => x"80", + 4668 => x"34", + 4669 => x"c6", + 4670 => x"2a", + 4671 => x"51", + 4672 => x"38", + 4673 => x"39", + 4674 => x"70", + 4675 => x"53", + 4676 => x"86", + 4677 => x"84", + 4678 => x"06", + 4679 => x"72", + 4680 => x"f1", + 4681 => x"08", + 4682 => x"17", + 4683 => x"76", + 4684 => x"3f", + 4685 => x"08", + 4686 => x"fe", + 4687 => x"82", + 4688 => x"88", + 4689 => x"f6", + 4690 => x"59", + 4691 => x"70", + 4692 => x"56", + 4693 => x"2e", + 4694 => x"76", + 4695 => x"58", + 4696 => x"32", + 4697 => x"a0", + 4698 => x"2a", + 4699 => x"52", + 4700 => x"38", + 4701 => x"09", + 4702 => x"a9", + 4703 => x"d0", + 4704 => x"70", + 4705 => x"38", + 4706 => x"81", + 4707 => x"11", + 4708 => x"70", + 4709 => x"ff", + 4710 => x"81", + 4711 => x"58", + 4712 => x"1b", + 4713 => x"08", + 4714 => x"75", + 4715 => x"57", + 4716 => x"81", + 4717 => x"ff", + 4718 => x"54", + 4719 => x"26", + 4720 => x"14", + 4721 => x"06", + 4722 => x"9f", + 4723 => x"99", + 4724 => x"e0", + 4725 => x"ff", + 4726 => x"73", + 4727 => x"32", + 4728 => x"72", + 4729 => x"73", + 4730 => x"53", + 4731 => x"70", + 4732 => x"73", + 4733 => x"32", + 4734 => x"72", + 4735 => x"73", + 4736 => x"53", + 4737 => x"70", + 4738 => x"38", + 4739 => x"83", + 4740 => x"8c", + 4741 => x"77", + 4742 => x"38", + 4743 => x"0c", + 4744 => x"86", + 4745 => x"f8", + 4746 => x"82", + 4747 => x"8c", + 4748 => x"fb", + 4749 => x"56", + 4750 => x"17", + 4751 => x"b0", + 4752 => x"52", + 4753 => x"81", + 4754 => x"82", + 4755 => x"81", + 4756 => x"b2", + 4757 => x"c3", + 4758 => x"c8", + 4759 => x"ff", + 4760 => x"55", + 4761 => x"d5", + 4762 => x"06", + 4763 => x"80", + 4764 => x"33", + 4765 => x"81", + 4766 => x"81", + 4767 => x"81", + 4768 => x"eb", + 4769 => x"70", + 4770 => x"07", + 4771 => x"73", + 4772 => x"16", + 4773 => x"81", + 4774 => x"81", + 4775 => x"83", + 4776 => x"80", + 4777 => x"16", + 4778 => x"3f", + 4779 => x"08", + 4780 => x"c8", + 4781 => x"9d", + 4782 => x"81", + 4783 => x"81", + 4784 => x"de", + 4785 => x"93", + 4786 => x"82", + 4787 => x"80", + 4788 => x"82", + 4789 => x"93", + 4790 => x"3d", + 4791 => x"3d", + 4792 => x"84", + 4793 => x"05", + 4794 => x"80", + 4795 => x"51", + 4796 => x"82", + 4797 => x"58", + 4798 => x"0b", + 4799 => x"08", + 4800 => x"38", + 4801 => x"08", + 4802 => x"93", + 4803 => x"08", + 4804 => x"56", + 4805 => x"87", + 4806 => x"74", + 4807 => x"fe", + 4808 => x"54", + 4809 => x"2e", + 4810 => x"15", + 4811 => x"a6", + 4812 => x"c8", + 4813 => x"06", + 4814 => x"54", + 4815 => x"38", + 4816 => x"8f", + 4817 => x"2a", + 4818 => x"51", + 4819 => x"72", + 4820 => x"80", + 4821 => x"39", + 4822 => x"77", + 4823 => x"81", + 4824 => x"33", + 4825 => x"3f", + 4826 => x"08", + 4827 => x"70", + 4828 => x"54", + 4829 => x"86", + 4830 => x"80", + 4831 => x"73", + 4832 => x"81", + 4833 => x"8a", + 4834 => x"95", + 4835 => x"53", + 4836 => x"fd", + 4837 => x"93", + 4838 => x"ff", + 4839 => x"82", + 4840 => x"06", + 4841 => x"79", + 4842 => x"29", + 4843 => x"75", + 4844 => x"f0", + 4845 => x"12", + 4846 => x"56", + 4847 => x"77", + 4848 => x"83", + 4849 => x"da", + 4850 => x"93", + 4851 => x"76", + 4852 => x"14", + 4853 => x"27", + 4854 => x"54", + 4855 => x"10", + 4856 => x"11", + 4857 => x"83", + 4858 => x"2e", + 4859 => x"52", + 4860 => x"bf", + 4861 => x"c8", + 4862 => x"06", + 4863 => x"27", + 4864 => x"14", + 4865 => x"27", + 4866 => x"56", + 4867 => x"85", + 4868 => x"56", + 4869 => x"85", + 4870 => x"15", + 4871 => x"3f", + 4872 => x"08", + 4873 => x"06", + 4874 => x"72", + 4875 => x"09", + 4876 => x"ed", + 4877 => x"15", + 4878 => x"3f", + 4879 => x"08", + 4880 => x"06", + 4881 => x"38", + 4882 => x"51", + 4883 => x"82", + 4884 => x"54", + 4885 => x"0c", + 4886 => x"33", + 4887 => x"80", + 4888 => x"ff", + 4889 => x"56", + 4890 => x"84", + 4891 => x"15", + 4892 => x"29", + 4893 => x"33", + 4894 => x"72", + 4895 => x"72", + 4896 => x"06", + 4897 => x"2e", + 4898 => x"13", + 4899 => x"72", + 4900 => x"38", + 4901 => x"89", + 4902 => x"15", + 4903 => x"3f", + 4904 => x"08", + 4905 => x"82", + 4906 => x"83", + 4907 => x"8f", + 4908 => x"56", + 4909 => x"38", + 4910 => x"51", + 4911 => x"82", + 4912 => x"83", + 4913 => x"53", + 4914 => x"80", + 4915 => x"d8", + 4916 => x"93", + 4917 => x"80", + 4918 => x"d8", + 4919 => x"93", + 4920 => x"ff", + 4921 => x"8d", + 4922 => x"2e", + 4923 => x"88", + 4924 => x"1a", + 4925 => x"05", + 4926 => x"56", + 4927 => x"83", + 4928 => x"15", + 4929 => x"78", + 4930 => x"b0", + 4931 => x"93", + 4932 => x"8d", + 4933 => x"c8", + 4934 => x"83", + 4935 => x"57", + 4936 => x"08", + 4937 => x"ff", + 4938 => x"38", + 4939 => x"83", + 4940 => x"83", + 4941 => x"72", + 4942 => x"83", + 4943 => x"8d", + 4944 => x"2e", + 4945 => x"82", + 4946 => x"0c", + 4947 => x"0c", + 4948 => x"16", + 4949 => x"ac", + 4950 => x"83", + 4951 => x"06", + 4952 => x"de", + 4953 => x"b3", + 4954 => x"c8", + 4955 => x"ff", + 4956 => x"56", + 4957 => x"38", + 4958 => x"53", + 4959 => x"82", + 4960 => x"e0", + 4961 => x"ac", + 4962 => x"c8", + 4963 => x"0c", + 4964 => x"82", + 4965 => x"39", + 4966 => x"53", + 4967 => x"80", + 4968 => x"38", + 4969 => x"14", + 4970 => x"76", + 4971 => x"81", + 4972 => x"98", + 4973 => x"53", + 4974 => x"15", + 4975 => x"16", + 4976 => x"81", + 4977 => x"08", + 4978 => x"51", + 4979 => x"13", + 4980 => x"8d", + 4981 => x"16", + 4982 => x"c5", + 4983 => x"90", + 4984 => x"0b", + 4985 => x"ff", + 4986 => x"16", + 4987 => x"2e", + 4988 => x"81", + 4989 => x"e4", + 4990 => x"9f", + 4991 => x"c8", + 4992 => x"ff", + 4993 => x"81", + 4994 => x"06", + 4995 => x"81", + 4996 => x"51", + 4997 => x"82", + 4998 => x"80", + 4999 => x"93", + 5000 => x"16", + 5001 => x"15", + 5002 => x"3f", + 5003 => x"08", + 5004 => x"06", + 5005 => x"d4", + 5006 => x"81", + 5007 => x"38", + 5008 => x"d5", + 5009 => x"93", + 5010 => x"8b", + 5011 => x"2e", + 5012 => x"b3", + 5013 => x"15", + 5014 => x"3f", + 5015 => x"08", + 5016 => x"e4", + 5017 => x"81", + 5018 => x"84", + 5019 => x"d5", + 5020 => x"93", + 5021 => x"16", + 5022 => x"15", + 5023 => x"3f", + 5024 => x"08", + 5025 => x"76", + 5026 => x"93", + 5027 => x"05", + 5028 => x"93", + 5029 => x"86", + 5030 => x"0b", + 5031 => x"80", + 5032 => x"93", + 5033 => x"3d", + 5034 => x"3d", + 5035 => x"89", + 5036 => x"2e", + 5037 => x"08", + 5038 => x"38", + 5039 => x"33", + 5040 => x"80", + 5041 => x"84", + 5042 => x"14", + 5043 => x"71", + 5044 => x"81", + 5045 => x"81", + 5046 => x"ce", + 5047 => x"93", + 5048 => x"06", + 5049 => x"38", + 5050 => x"53", + 5051 => x"09", + 5052 => x"38", + 5053 => x"78", + 5054 => x"52", + 5055 => x"c8", + 5056 => x"0d", + 5057 => x"0d", + 5058 => x"33", + 5059 => x"3d", + 5060 => x"56", + 5061 => x"82", + 5062 => x"55", + 5063 => x"0b", + 5064 => x"08", + 5065 => x"38", + 5066 => x"08", + 5067 => x"93", + 5068 => x"08", + 5069 => x"80", + 5070 => x"80", + 5071 => x"80", + 5072 => x"78", + 5073 => x"34", + 5074 => x"82", + 5075 => x"79", + 5076 => x"75", + 5077 => x"2e", + 5078 => x"53", + 5079 => x"53", + 5080 => x"f6", + 5081 => x"93", + 5082 => x"73", + 5083 => x"0c", + 5084 => x"04", + 5085 => x"67", + 5086 => x"80", + 5087 => x"58", + 5088 => x"77", + 5089 => x"e9", + 5090 => x"06", + 5091 => x"3d", + 5092 => x"99", + 5093 => x"52", + 5094 => x"3f", + 5095 => x"08", + 5096 => x"c8", + 5097 => x"38", + 5098 => x"52", + 5099 => x"05", + 5100 => x"3f", + 5101 => x"08", + 5102 => x"c8", + 5103 => x"02", + 5104 => x"33", + 5105 => x"56", + 5106 => x"25", + 5107 => x"56", + 5108 => x"55", + 5109 => x"81", + 5110 => x"80", + 5111 => x"75", + 5112 => x"81", + 5113 => x"97", + 5114 => x"51", + 5115 => x"82", + 5116 => x"56", + 5117 => x"57", + 5118 => x"b2", + 5119 => x"06", + 5120 => x"2e", + 5121 => x"56", + 5122 => x"82", + 5123 => x"06", + 5124 => x"80", + 5125 => x"88", + 5126 => x"d0", + 5127 => x"2a", + 5128 => x"51", + 5129 => x"2e", + 5130 => x"62", + 5131 => x"e6", + 5132 => x"93", + 5133 => x"82", + 5134 => x"52", + 5135 => x"51", + 5136 => x"62", + 5137 => x"8b", + 5138 => x"53", + 5139 => x"51", + 5140 => x"75", + 5141 => x"05", + 5142 => x"3f", + 5143 => x"0b", + 5144 => x"78", + 5145 => x"e9", + 5146 => x"11", + 5147 => x"7a", + 5148 => x"d4", + 5149 => x"55", + 5150 => x"82", + 5151 => x"56", + 5152 => x"08", + 5153 => x"74", + 5154 => x"d4", + 5155 => x"93", + 5156 => x"ff", + 5157 => x"0c", + 5158 => x"39", + 5159 => x"38", + 5160 => x"33", + 5161 => x"70", + 5162 => x"56", + 5163 => x"2e", + 5164 => x"56", + 5165 => x"81", + 5166 => x"06", + 5167 => x"80", + 5168 => x"02", + 5169 => x"81", + 5170 => x"80", + 5171 => x"87", + 5172 => x"98", + 5173 => x"2a", + 5174 => x"51", + 5175 => x"2e", + 5176 => x"80", + 5177 => x"7a", + 5178 => x"a0", + 5179 => x"a4", + 5180 => x"75", + 5181 => x"62", + 5182 => x"e4", + 5183 => x"93", + 5184 => x"19", + 5185 => x"05", + 5186 => x"3f", + 5187 => x"08", + 5188 => x"74", + 5189 => x"15", + 5190 => x"23", + 5191 => x"34", + 5192 => x"34", + 5193 => x"0c", + 5194 => x"0c", + 5195 => x"75", + 5196 => x"51", + 5197 => x"76", + 5198 => x"81", + 5199 => x"74", + 5200 => x"a3", + 5201 => x"08", + 5202 => x"9b", + 5203 => x"08", + 5204 => x"7a", + 5205 => x"70", + 5206 => x"1b", + 5207 => x"08", + 5208 => x"51", + 5209 => x"76", + 5210 => x"d4", + 5211 => x"93", + 5212 => x"82", + 5213 => x"81", + 5214 => x"82", + 5215 => x"2e", + 5216 => x"83", + 5217 => x"78", + 5218 => x"75", + 5219 => x"07", + 5220 => x"7b", + 5221 => x"51", + 5222 => x"cb", + 5223 => x"19", + 5224 => x"c8", + 5225 => x"ff", + 5226 => x"80", + 5227 => x"76", + 5228 => x"d4", + 5229 => x"93", + 5230 => x"38", + 5231 => x"39", + 5232 => x"82", + 5233 => x"05", + 5234 => x"0c", + 5235 => x"74", + 5236 => x"52", + 5237 => x"33", + 5238 => x"a4", + 5239 => x"c8", + 5240 => x"83", + 5241 => x"75", + 5242 => x"38", + 5243 => x"75", + 5244 => x"93", + 5245 => x"3d", + 5246 => x"3d", + 5247 => x"64", + 5248 => x"5a", + 5249 => x"0c", + 5250 => x"05", + 5251 => x"f9", + 5252 => x"93", + 5253 => x"82", + 5254 => x"8a", + 5255 => x"33", + 5256 => x"2e", + 5257 => x"56", + 5258 => x"90", + 5259 => x"06", + 5260 => x"74", + 5261 => x"a0", + 5262 => x"82", + 5263 => x"34", + 5264 => x"94", + 5265 => x"91", + 5266 => x"56", + 5267 => x"82", + 5268 => x"34", + 5269 => x"80", + 5270 => x"91", + 5271 => x"56", + 5272 => x"81", + 5273 => x"34", + 5274 => x"ec", + 5275 => x"91", + 5276 => x"56", + 5277 => x"8c", + 5278 => x"18", + 5279 => x"74", + 5280 => x"38", + 5281 => x"80", + 5282 => x"38", + 5283 => x"70", + 5284 => x"56", + 5285 => x"83", + 5286 => x"11", + 5287 => x"77", + 5288 => x"5c", + 5289 => x"38", + 5290 => x"88", + 5291 => x"8f", + 5292 => x"08", + 5293 => x"d2", + 5294 => x"93", + 5295 => x"81", + 5296 => x"f7", + 5297 => x"2e", + 5298 => x"74", + 5299 => x"98", + 5300 => x"7d", + 5301 => x"3f", + 5302 => x"08", + 5303 => x"ef", + 5304 => x"c8", + 5305 => x"89", + 5306 => x"79", + 5307 => x"d7", + 5308 => x"7e", + 5309 => x"51", + 5310 => x"76", + 5311 => x"74", + 5312 => x"79", + 5313 => x"7b", + 5314 => x"11", + 5315 => x"c7", + 5316 => x"93", + 5317 => x"c1", + 5318 => x"33", + 5319 => x"56", + 5320 => x"25", + 5321 => x"17", + 5322 => x"55", + 5323 => x"90", + 5324 => x"53", + 5325 => x"74", + 5326 => x"1c", + 5327 => x"3f", + 5328 => x"56", + 5329 => x"9c", + 5330 => x"2e", + 5331 => x"90", + 5332 => x"98", + 5333 => x"74", + 5334 => x"38", + 5335 => x"17", + 5336 => x"17", + 5337 => x"11", + 5338 => x"c8", + 5339 => x"93", + 5340 => x"ef", + 5341 => x"33", + 5342 => x"55", + 5343 => x"34", + 5344 => x"53", + 5345 => x"7d", + 5346 => x"52", + 5347 => x"3f", + 5348 => x"08", + 5349 => x"77", + 5350 => x"94", + 5351 => x"ff", + 5352 => x"71", + 5353 => x"78", + 5354 => x"38", + 5355 => x"53", + 5356 => x"83", + 5357 => x"a8", + 5358 => x"51", + 5359 => x"78", + 5360 => x"08", + 5361 => x"76", + 5362 => x"08", + 5363 => x"0c", + 5364 => x"fd", + 5365 => x"56", + 5366 => x"c8", + 5367 => x"0d", + 5368 => x"0d", + 5369 => x"63", + 5370 => x"57", + 5371 => x"8f", + 5372 => x"52", + 5373 => x"b2", + 5374 => x"c8", + 5375 => x"93", + 5376 => x"38", + 5377 => x"55", + 5378 => x"86", + 5379 => x"84", + 5380 => x"17", + 5381 => x"2a", + 5382 => x"51", + 5383 => x"56", + 5384 => x"83", + 5385 => x"39", + 5386 => x"18", + 5387 => x"83", + 5388 => x"0b", + 5389 => x"81", + 5390 => x"39", + 5391 => x"18", + 5392 => x"83", + 5393 => x"0b", + 5394 => x"82", + 5395 => x"39", + 5396 => x"18", + 5397 => x"83", + 5398 => x"0b", + 5399 => x"81", + 5400 => x"39", + 5401 => x"19", + 5402 => x"18", + 5403 => x"38", + 5404 => x"09", + 5405 => x"2e", + 5406 => x"94", + 5407 => x"83", + 5408 => x"56", + 5409 => x"38", + 5410 => x"22", + 5411 => x"89", + 5412 => x"55", + 5413 => x"38", + 5414 => x"88", + 5415 => x"74", + 5416 => x"52", + 5417 => x"b8", + 5418 => x"c8", + 5419 => x"39", + 5420 => x"52", + 5421 => x"a8", + 5422 => x"c8", + 5423 => x"80", + 5424 => x"38", + 5425 => x"fe", + 5426 => x"ff", + 5427 => x"38", + 5428 => x"0c", + 5429 => x"85", + 5430 => x"18", + 5431 => x"33", + 5432 => x"56", + 5433 => x"25", + 5434 => x"54", + 5435 => x"53", + 5436 => x"7d", + 5437 => x"52", + 5438 => x"3f", + 5439 => x"08", + 5440 => x"90", + 5441 => x"ff", + 5442 => x"90", + 5443 => x"17", + 5444 => x"51", + 5445 => x"82", + 5446 => x"80", + 5447 => x"38", + 5448 => x"08", + 5449 => x"2a", + 5450 => x"80", + 5451 => x"38", + 5452 => x"8a", + 5453 => x"56", + 5454 => x"27", + 5455 => x"7b", + 5456 => x"54", + 5457 => x"52", + 5458 => x"33", + 5459 => x"89", + 5460 => x"c8", + 5461 => x"38", + 5462 => x"78", + 5463 => x"7a", + 5464 => x"84", + 5465 => x"84", + 5466 => x"52", + 5467 => x"c8", + 5468 => x"17", + 5469 => x"06", + 5470 => x"18", + 5471 => x"2b", + 5472 => x"39", + 5473 => x"78", + 5474 => x"94", + 5475 => x"18", + 5476 => x"38", + 5477 => x"53", + 5478 => x"7d", + 5479 => x"52", + 5480 => x"3f", + 5481 => x"08", + 5482 => x"77", + 5483 => x"94", + 5484 => x"ff", + 5485 => x"71", + 5486 => x"78", + 5487 => x"38", + 5488 => x"53", + 5489 => x"17", + 5490 => x"06", + 5491 => x"51", + 5492 => x"90", + 5493 => x"80", + 5494 => x"90", + 5495 => x"76", + 5496 => x"17", + 5497 => x"1d", + 5498 => x"18", + 5499 => x"0c", + 5500 => x"58", + 5501 => x"74", + 5502 => x"38", + 5503 => x"8c", + 5504 => x"fc", + 5505 => x"17", + 5506 => x"07", + 5507 => x"18", + 5508 => x"75", + 5509 => x"0c", + 5510 => x"04", + 5511 => x"7b", + 5512 => x"05", + 5513 => x"58", + 5514 => x"82", + 5515 => x"57", + 5516 => x"08", + 5517 => x"90", + 5518 => x"86", + 5519 => x"06", + 5520 => x"74", + 5521 => x"98", + 5522 => x"2b", + 5523 => x"25", + 5524 => x"54", + 5525 => x"53", + 5526 => x"79", + 5527 => x"52", + 5528 => x"3f", + 5529 => x"93", + 5530 => x"f6", + 5531 => x"33", + 5532 => x"55", + 5533 => x"34", + 5534 => x"52", + 5535 => x"c9", + 5536 => x"c8", + 5537 => x"93", + 5538 => x"d4", + 5539 => x"08", + 5540 => x"a0", + 5541 => x"74", + 5542 => x"88", + 5543 => x"75", + 5544 => x"51", + 5545 => x"8c", + 5546 => x"9c", + 5547 => x"cb", + 5548 => x"b2", + 5549 => x"16", + 5550 => x"3f", + 5551 => x"16", + 5552 => x"3f", + 5553 => x"0b", + 5554 => x"79", + 5555 => x"3f", + 5556 => x"08", + 5557 => x"81", + 5558 => x"57", + 5559 => x"34", + 5560 => x"82", + 5561 => x"8b", + 5562 => x"fc", + 5563 => x"70", + 5564 => x"a8", + 5565 => x"c8", + 5566 => x"93", + 5567 => x"38", + 5568 => x"05", + 5569 => x"ef", + 5570 => x"93", + 5571 => x"82", + 5572 => x"87", + 5573 => x"c8", + 5574 => x"72", + 5575 => x"0c", + 5576 => x"04", + 5577 => x"85", + 5578 => x"9b", + 5579 => x"80", + 5580 => x"c8", + 5581 => x"38", + 5582 => x"08", + 5583 => x"34", + 5584 => x"82", + 5585 => x"84", + 5586 => x"ef", + 5587 => x"53", + 5588 => x"05", + 5589 => x"51", + 5590 => x"82", + 5591 => x"55", + 5592 => x"08", + 5593 => x"76", + 5594 => x"93", + 5595 => x"51", + 5596 => x"82", + 5597 => x"55", + 5598 => x"08", + 5599 => x"80", + 5600 => x"70", + 5601 => x"56", + 5602 => x"89", + 5603 => x"94", + 5604 => x"a7", + 5605 => x"05", + 5606 => x"2a", + 5607 => x"51", + 5608 => x"80", + 5609 => x"76", + 5610 => x"52", + 5611 => x"3f", + 5612 => x"08", + 5613 => x"83", + 5614 => x"74", + 5615 => x"81", + 5616 => x"85", + 5617 => x"93", + 5618 => x"3d", + 5619 => x"3d", + 5620 => x"08", + 5621 => x"5b", + 5622 => x"34", + 5623 => x"3d", + 5624 => x"52", + 5625 => x"e5", + 5626 => x"93", + 5627 => x"82", + 5628 => x"83", + 5629 => x"46", + 5630 => x"11", + 5631 => x"68", + 5632 => x"80", + 5633 => x"38", + 5634 => x"94", + 5635 => x"5b", + 5636 => x"51", + 5637 => x"82", + 5638 => x"57", + 5639 => x"08", + 5640 => x"6b", + 5641 => x"c5", + 5642 => x"93", + 5643 => x"82", + 5644 => x"81", + 5645 => x"52", + 5646 => x"ab", + 5647 => x"c8", + 5648 => x"52", + 5649 => x"b2", + 5650 => x"c8", + 5651 => x"93", + 5652 => x"ac", + 5653 => x"80", + 5654 => x"d6", + 5655 => x"93", + 5656 => x"82", + 5657 => x"a4", + 5658 => x"7e", + 5659 => x"3f", + 5660 => x"08", + 5661 => x"38", + 5662 => x"51", + 5663 => x"82", + 5664 => x"57", + 5665 => x"08", + 5666 => x"38", + 5667 => x"09", + 5668 => x"38", + 5669 => x"81", + 5670 => x"3d", + 5671 => x"53", + 5672 => x"d9", + 5673 => x"93", + 5674 => x"12", + 5675 => x"51", + 5676 => x"56", + 5677 => x"8e", + 5678 => x"70", + 5679 => x"33", + 5680 => x"73", + 5681 => x"16", + 5682 => x"27", + 5683 => x"57", + 5684 => x"80", + 5685 => x"7d", + 5686 => x"a3", + 5687 => x"ff", + 5688 => x"57", + 5689 => x"81", + 5690 => x"34", + 5691 => x"ff", + 5692 => x"08", + 5693 => x"af", + 5694 => x"55", + 5695 => x"38", + 5696 => x"38", + 5697 => x"09", + 5698 => x"38", + 5699 => x"3d", + 5700 => x"59", + 5701 => x"80", + 5702 => x"f8", + 5703 => x"10", + 5704 => x"05", + 5705 => x"33", + 5706 => x"57", + 5707 => x"78", + 5708 => x"81", + 5709 => x"70", + 5710 => x"56", + 5711 => x"82", + 5712 => x"79", + 5713 => x"80", + 5714 => x"27", + 5715 => x"15", + 5716 => x"7a", + 5717 => x"5c", + 5718 => x"58", + 5719 => x"ee", + 5720 => x"70", + 5721 => x"34", + 5722 => x"77", + 5723 => x"57", + 5724 => x"a2", + 5725 => x"81", + 5726 => x"73", + 5727 => x"81", + 5728 => x"7b", + 5729 => x"38", + 5730 => x"76", + 5731 => x"0c", + 5732 => x"04", + 5733 => x"7e", + 5734 => x"fc", + 5735 => x"53", + 5736 => x"86", + 5737 => x"c8", + 5738 => x"93", + 5739 => x"38", + 5740 => x"5a", + 5741 => x"86", + 5742 => x"83", + 5743 => x"17", + 5744 => x"94", + 5745 => x"33", + 5746 => x"70", + 5747 => x"56", + 5748 => x"38", + 5749 => x"58", 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x"2e", + 5809 => x"81", + 5810 => x"38", + 5811 => x"15", + 5812 => x"8b", + 5813 => x"91", + 5814 => x"55", + 5815 => x"75", + 5816 => x"77", + 5817 => x"98", + 5818 => x"08", + 5819 => x"0c", + 5820 => x"06", + 5821 => x"2e", + 5822 => x"52", + 5823 => x"bf", + 5824 => x"c8", + 5825 => x"82", + 5826 => x"34", + 5827 => x"a6", + 5828 => x"2a", + 5829 => x"08", + 5830 => x"17", + 5831 => x"08", + 5832 => x"94", + 5833 => x"18", + 5834 => x"33", + 5835 => x"55", + 5836 => x"34", + 5837 => x"83", + 5838 => x"74", + 5839 => x"f4", + 5840 => x"08", + 5841 => x"ec", + 5842 => x"33", + 5843 => x"56", + 5844 => x"25", + 5845 => x"54", + 5846 => x"53", + 5847 => x"7c", + 5848 => x"52", + 5849 => x"f1", + 5850 => x"c8", + 5851 => x"8a", + 5852 => x"91", + 5853 => x"55", + 5854 => x"17", + 5855 => x"06", + 5856 => x"18", + 5857 => x"7a", + 5858 => x"52", + 5859 => x"33", + 5860 => x"b6", + 5861 => x"93", + 5862 => x"2e", + 5863 => x"0b", + 5864 => x"81", + 5865 => x"81", + 5866 => x"34", + 5867 => x"39", + 5868 => x"0c", + 5869 => x"82", + 5870 => x"8e", + 5871 => x"f9", + 5872 => x"56", + 5873 => x"80", + 5874 => x"38", + 5875 => x"3d", + 5876 => x"8a", + 5877 => x"51", + 5878 => x"82", + 5879 => x"55", + 5880 => x"08", + 5881 => x"77", + 5882 => x"52", + 5883 => x"9e", + 5884 => x"c8", + 5885 => x"93", + 5886 => x"ca", + 5887 => x"33", + 5888 => x"55", + 5889 => x"24", + 5890 => x"16", + 5891 => x"2a", + 5892 => x"51", + 5893 => x"80", + 5894 => x"9c", + 5895 => x"77", + 5896 => x"3f", + 5897 => x"08", + 5898 => x"83", + 5899 => x"74", + 5900 => x"54", + 5901 => x"84", + 5902 => x"52", + 5903 => x"ba", + 5904 => x"c8", + 5905 => x"84", + 5906 => x"06", + 5907 => x"55", + 5908 => x"84", + 5909 => x"0c", + 5910 => x"82", + 5911 => x"89", + 5912 => x"fc", + 5913 => x"87", + 5914 => x"53", + 5915 => x"e4", + 5916 => x"93", + 5917 => x"82", + 5918 => x"87", + 5919 => x"c8", + 5920 => x"72", + 5921 => x"0c", + 5922 => x"04", + 5923 => x"77", + 5924 => x"fc", + 5925 => x"53", + 5926 => x"8e", + 5927 => x"c8", + 5928 => x"93", + 5929 => x"d1", + 5930 => x"38", + 5931 => x"08", + 5932 => x"c8", + 5933 => x"93", + 5934 => x"bd", + 5935 => x"73", + 5936 => x"3f", + 5937 => x"08", + 5938 => x"c8", + 5939 => x"09", + 5940 => x"38", + 5941 => x"a1", + 5942 => x"73", + 5943 => x"3f", + 5944 => x"51", + 5945 => x"82", + 5946 => x"53", + 5947 => x"08", + 5948 => x"81", + 5949 => x"80", + 5950 => x"93", + 5951 => x"3d", + 5952 => x"3d", + 5953 => x"80", + 5954 => x"70", + 5955 => x"52", + 5956 => x"3f", + 5957 => x"08", + 5958 => x"c8", + 5959 => x"63", + 5960 => x"d5", + 5961 => x"93", + 5962 => x"82", + 5963 => x"a3", + 5964 => x"c7", + 5965 => x"98", + 5966 => x"73", + 5967 => x"38", + 5968 => x"39", + 5969 => x"8b", + 5970 => x"93", + 5971 => x"51", + 5972 => x"74", + 5973 => x"0c", + 5974 => x"04", + 5975 => x"61", + 5976 => x"80", + 5977 => x"ec", + 5978 => x"3d", + 5979 => x"3f", + 5980 => x"08", + 5981 => x"c8", + 5982 => x"38", + 5983 => x"73", + 5984 => x"08", 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x"90", + 6044 => x"7a", + 6045 => x"81", + 6046 => x"73", + 6047 => x"78", + 6048 => x"0c", + 6049 => x"04", + 6050 => x"7a", + 6051 => x"05", + 6052 => x"58", + 6053 => x"82", + 6054 => x"57", + 6055 => x"08", + 6056 => x"18", + 6057 => x"80", + 6058 => x"76", + 6059 => x"39", + 6060 => x"70", + 6061 => x"81", + 6062 => x"56", + 6063 => x"80", + 6064 => x"38", + 6065 => x"8c", + 6066 => x"81", + 6067 => x"18", + 6068 => x"80", + 6069 => x"08", + 6070 => x"ff", + 6071 => x"82", + 6072 => x"57", + 6073 => x"19", + 6074 => x"39", + 6075 => x"52", + 6076 => x"b9", + 6077 => x"93", + 6078 => x"93", + 6079 => x"32", + 6080 => x"72", + 6081 => x"52", + 6082 => x"82", + 6083 => x"81", + 6084 => x"06", + 6085 => x"57", + 6086 => x"78", + 6087 => x"16", + 6088 => x"38", + 6089 => x"53", + 6090 => x"51", + 6091 => x"3f", + 6092 => x"08", + 6093 => x"08", + 6094 => x"90", + 6095 => x"c0", + 6096 => x"90", + 6097 => x"b9", + 6098 => x"2b", + 6099 => x"25", + 6100 => x"54", + 6101 => x"53", + 6102 => x"78", + 6103 => x"52", + 6104 => x"f5", + 6105 => x"c8", + 6106 => x"85", + 6107 => x"8c", + 6108 => x"33", + 6109 => x"55", + 6110 => x"34", + 6111 => x"89", + 6112 => x"19", + 6113 => x"83", + 6114 => x"75", + 6115 => x"0c", + 6116 => x"04", + 6117 => x"81", + 6118 => x"ff", + 6119 => x"82", + 6120 => x"ff", + 6121 => x"a0", + 6122 => x"b2", + 6123 => x"c8", + 6124 => x"93", + 6125 => x"d3", + 6126 => x"90", + 6127 => x"b3", + 6128 => x"6f", + 6129 => x"d4", + 6130 => x"c2", + 6131 => x"c8", + 6132 => x"94", + 6133 => x"96", + 6134 => x"82", + 6135 => x"80", + 6136 => x"70", + 6137 => x"81", + 6138 => x"55", + 6139 => x"83", + 6140 => x"75", + 6141 => x"81", + 6142 => x"ff", + 6143 => x"02", + 6144 => x"33", + 6145 => x"55", + 6146 => x"25", + 6147 => x"56", + 6148 => x"80", + 6149 => x"81", + 6150 => x"80", + 6151 => x"87", + 6152 => x"e7", + 6153 => x"77", + 6154 => x"3f", + 6155 => x"08", + 6156 => x"80", + 6157 => x"70", + 6158 => x"81", + 6159 => x"56", + 6160 => x"2e", + 6161 => x"81", + 6162 => x"ff", + 6163 => x"87", + 6164 => x"94", + 6165 => x"2e", + 6166 => x"81", + 6167 => x"ff", + 6168 => x"77", + 6169 => x"81", + 6170 => x"ff", + 6171 => x"80", + 6172 => x"70", + 6173 => x"82", + 6174 => x"c8", + 6175 => x"93", + 6176 => x"87", + 6177 => x"c8", + 6178 => x"51", + 6179 => x"82", + 6180 => x"56", + 6181 => x"08", + 6182 => x"56", + 6183 => x"70", + 6184 => x"07", + 6185 => x"06", + 6186 => x"75", + 6187 => x"81", + 6188 => x"ff", + 6189 => x"9f", + 6190 => x"51", + 6191 => x"82", + 6192 => x"82", + 6193 => x"30", + 6194 => x"c8", + 6195 => x"25", + 6196 => x"7b", + 6197 => x"72", + 6198 => x"51", + 6199 => x"80", + 6200 => x"81", + 6201 => x"ff", + 6202 => x"80", + 6203 => x"9f", + 6204 => x"51", + 6205 => x"3f", + 6206 => x"08", + 6207 => x"38", + 6208 => x"b4", + 6209 => x"93", + 6210 => x"81", + 6211 => x"ff", + 6212 => x"75", + 6213 => x"0c", + 6214 => x"04", + 6215 => x"82", + 6216 => x"c0", + 6217 => x"3d", + 6218 => x"3f", + 6219 => x"08", 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x"83", + 6279 => x"3d", + 6280 => x"c5", + 6281 => x"93", + 6282 => x"82", + 6283 => x"af", + 6284 => x"63", + 6285 => x"ff", + 6286 => x"75", + 6287 => x"77", + 6288 => x"3f", + 6289 => x"0b", + 6290 => x"77", + 6291 => x"83", + 6292 => x"51", + 6293 => x"3f", + 6294 => x"08", + 6295 => x"80", + 6296 => x"98", + 6297 => x"51", + 6298 => x"3f", + 6299 => x"c8", + 6300 => x"0d", + 6301 => x"0d", + 6302 => x"05", + 6303 => x"3f", + 6304 => x"3d", + 6305 => x"52", + 6306 => x"d0", + 6307 => x"93", + 6308 => x"82", + 6309 => x"82", + 6310 => x"4c", + 6311 => x"52", + 6312 => x"05", + 6313 => x"3f", + 6314 => x"08", + 6315 => x"c8", + 6316 => x"38", + 6317 => x"05", + 6318 => x"06", + 6319 => x"2e", + 6320 => x"55", + 6321 => x"38", + 6322 => x"3d", + 6323 => x"3d", + 6324 => x"51", + 6325 => x"3f", + 6326 => x"3d", + 6327 => x"91", + 6328 => x"54", + 6329 => x"3f", + 6330 => x"52", + 6331 => x"9e", + 6332 => x"c8", + 6333 => x"93", + 6334 => x"38", + 6335 => x"09", + 6336 => x"38", + 6337 => x"a1", + 6338 => x"83", + 6339 => x"74", + 6340 => x"81", + 6341 => x"38", + 6342 => x"a8", + 6343 => x"ec", + 6344 => x"c8", + 6345 => x"93", + 6346 => x"c4", + 6347 => x"93", + 6348 => x"ff", + 6349 => x"8d", + 6350 => x"ac", + 6351 => x"ab", + 6352 => x"17", + 6353 => x"33", + 6354 => x"70", + 6355 => x"55", + 6356 => x"38", + 6357 => x"54", + 6358 => x"34", + 6359 => x"0b", + 6360 => x"8b", + 6361 => x"84", + 6362 => x"06", + 6363 => x"73", + 6364 => x"db", + 6365 => x"2e", + 6366 => x"75", + 6367 => x"ff", + 6368 => x"82", + 6369 => x"52", + 6370 => x"b0", + 6371 => x"55", + 6372 => x"08", + 6373 => x"38", + 6374 => x"08", + 6375 => x"ff", + 6376 => x"82", + 6377 => x"80", + 6378 => x"55", + 6379 => x"08", + 6380 => x"16", + 6381 => x"ae", + 6382 => x"06", + 6383 => x"53", + 6384 => x"51", + 6385 => x"3f", + 6386 => x"0b", + 6387 => x"74", + 6388 => x"3d", + 6389 => x"c3", + 6390 => x"93", + 6391 => x"82", + 6392 => x"8c", + 6393 => x"ff", + 6394 => x"82", + 6395 => x"55", + 6396 => x"c8", + 6397 => x"0d", + 6398 => x"0d", + 6399 => x"05", + 6400 => x"05", + 6401 => x"33", + 6402 => x"53", + 6403 => x"05", + 6404 => x"51", + 6405 => x"82", + 6406 => x"55", + 6407 => x"08", + 6408 => x"78", + 6409 => x"95", + 6410 => x"51", + 6411 => x"82", + 6412 => x"55", + 6413 => x"08", + 6414 => x"80", + 6415 => x"81", + 6416 => x"73", + 6417 => x"38", + 6418 => x"aa", + 6419 => x"06", + 6420 => x"8b", + 6421 => x"06", + 6422 => x"07", + 6423 => x"56", + 6424 => x"34", + 6425 => x"0b", + 6426 => x"78", + 6427 => x"a0", + 6428 => x"c8", + 6429 => x"82", + 6430 => x"95", + 6431 => x"ee", + 6432 => x"56", + 6433 => x"3d", + 6434 => x"95", + 6435 => x"ce", + 6436 => x"c8", + 6437 => x"93", + 6438 => x"d3", + 6439 => x"64", + 6440 => x"d4", + 6441 => x"e6", + 6442 => x"c8", + 6443 => x"93", + 6444 => x"38", + 6445 => x"05", + 6446 => x"06", + 6447 => x"2e", + 6448 => x"55", + 6449 => x"86", + 6450 => x"17", + 6451 => x"2b", + 6452 => x"57", + 6453 => x"05", + 6454 => x"9f", + 6455 => x"81", + 6456 => x"34", + 6457 => x"ac", + 6458 => x"93", + 6459 => x"74", + 6460 => x"0c", + 6461 => x"04", + 6462 => x"69", + 6463 => x"80", + 6464 => x"d0", + 6465 => x"3d", + 6466 => x"3f", + 6467 => x"08", + 6468 => x"08", + 6469 => x"93", + 6470 => x"80", + 6471 => x"70", + 6472 => x"2a", + 6473 => x"57", + 6474 => x"74", + 6475 => x"f6", + 6476 => x"80", + 6477 => x"8d", + 6478 => x"54", + 6479 => x"3f", + 6480 => x"08", + 6481 => x"c8", + 6482 => x"38", + 6483 => x"51", + 6484 => x"3f", + 6485 => x"08", + 6486 => x"c8", + 6487 => x"82", + 6488 => x"82", + 6489 => x"65", + 6490 => x"79", + 6491 => x"7a", + 6492 => x"55", + 6493 => x"34", + 6494 => x"8a", + 6495 => x"38", + 6496 => x"80", + 6497 => x"80", + 6498 => x"ff", + 6499 => x"70", + 6500 => x"58", + 6501 => x"e8", + 6502 => x"2e", + 6503 => x"86", + 6504 => x"34", + 6505 => x"30", + 6506 => x"80", + 6507 => x"70", + 6508 => x"2a", + 6509 => x"56", + 6510 => x"80", + 6511 => x"7b", + 6512 => x"53", + 6513 => x"81", + 6514 => x"c8", + 6515 => x"93", + 6516 => x"38", + 6517 => x"51", + 6518 => x"58", + 6519 => x"8b", + 6520 => x"58", + 6521 => x"83", + 6522 => x"7b", + 6523 => x"51", + 6524 => x"3f", + 6525 => x"08", + 6526 => x"82", + 6527 => x"98", + 6528 => x"e8", + 6529 => x"53", + 6530 => x"b8", + 6531 => x"3d", + 6532 => x"3f", + 6533 => x"08", + 6534 => x"c8", + 6535 => x"38", + 6536 => x"52", + 6537 => x"bc", + 6538 => x"a7", + 6539 => x"6b", + 6540 => x"52", + 6541 => x"9f", + 6542 => x"b5", + 6543 => x"6b", + 6544 => x"70", + 6545 => x"52", + 6546 => x"fe", + 6547 => x"c8", + 6548 => x"a2", + 6549 => x"33", + 6550 => x"54", + 6551 => x"3f", + 6552 => x"08", + 6553 => x"38", + 6554 => x"74", + 6555 => x"05", + 6556 => x"39", + 6557 => x"9f", + 6558 => x"99", + 6559 => x"e0", + 6560 => x"ff", + 6561 => x"54", + 6562 => x"27", + 6563 => x"fa", + 6564 => x"56", + 6565 => x"a3", + 6566 => x"81", + 6567 => x"ff", + 6568 => x"82", + 6569 => x"93", + 6570 => x"76", + 6571 => x"76", + 6572 => x"38", + 6573 => x"77", + 6574 => x"86", + 6575 => x"39", + 6576 => x"27", + 6577 => x"3d", + 6578 => x"bc", + 6579 => x"2a", + 6580 => x"75", + 6581 => x"57", + 6582 => x"05", + 6583 => x"54", + 6584 => x"81", + 6585 => x"33", + 6586 => x"73", + 6587 => x"cd", + 6588 => x"33", + 6589 => x"73", + 6590 => x"81", + 6591 => x"80", + 6592 => x"02", + 6593 => x"78", + 6594 => x"51", + 6595 => x"73", + 6596 => x"81", + 6597 => x"ff", + 6598 => x"80", + 6599 => x"76", + 6600 => x"51", + 6601 => x"2e", + 6602 => x"5f", + 6603 => x"52", + 6604 => x"52", + 6605 => x"c2", + 6606 => x"c8", + 6607 => x"93", + 6608 => x"a1", + 6609 => x"74", + 6610 => x"82", + 6611 => x"c8", + 6612 => x"93", + 6613 => x"38", + 6614 => x"91", + 6615 => x"9a", + 6616 => x"05", + 6617 => x"ff", + 6618 => x"86", + 6619 => x"e5", + 6620 => x"54", + 6621 => x"15", + 6622 => x"ff", + 6623 => x"82", + 6624 => x"54", + 6625 => x"82", + 6626 => x"84", + 6627 => x"06", + 6628 => x"80", + 6629 => x"2e", + 6630 => x"81", + 6631 => x"d4", + 6632 => x"b6", + 6633 => x"93", + 6634 => x"82", + 6635 => x"b5", + 6636 => x"82", + 6637 => x"52", + 6638 => x"a4", + 6639 => x"54", + 6640 => x"15", + 6641 => x"9a", + 6642 => x"05", + 6643 => x"ff", + 6644 => x"77", + 6645 => x"83", + 6646 => x"51", + 6647 => x"3f", + 6648 => x"08", + 6649 => x"74", + 6650 => x"0c", + 6651 => x"04", + 6652 => x"61", + 6653 => x"05", + 6654 => x"33", + 6655 => x"05", + 6656 => x"5e", + 6657 => x"a2", + 6658 => x"c8", + 6659 => x"93", + 6660 => x"38", + 6661 => x"57", + 6662 => x"86", + 6663 => x"82", + 6664 => x"80", + 6665 => x"8c", + 6666 => x"38", + 6667 => x"70", + 6668 => x"81", + 6669 => x"55", + 6670 => x"87", + 6671 => x"39", + 6672 => x"89", + 6673 => x"81", + 6674 => x"8a", + 6675 => x"89", + 6676 => x"7d", + 6677 => x"54", + 6678 => x"3f", + 6679 => x"06", + 6680 => x"72", + 6681 => x"82", + 6682 => x"05", + 6683 => x"08", + 6684 => x"55", + 6685 => x"81", + 6686 => x"38", + 6687 => x"79", + 6688 => x"82", + 6689 => x"56", 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x"d3", + 6749 => x"c8", + 6750 => x"57", + 6751 => x"93", + 6752 => x"8c", + 6753 => x"93", + 6754 => x"10", + 6755 => x"05", + 6756 => x"80", + 6757 => x"74", + 6758 => x"75", + 6759 => x"ff", + 6760 => x"52", + 6761 => x"99", + 6762 => x"93", + 6763 => x"ff", + 6764 => x"06", + 6765 => x"57", + 6766 => x"38", + 6767 => x"70", + 6768 => x"55", + 6769 => x"8c", + 6770 => x"3d", + 6771 => x"83", + 6772 => x"ff", + 6773 => x"82", + 6774 => x"98", + 6775 => x"2e", + 6776 => x"82", + 6777 => x"8c", + 6778 => x"05", + 6779 => x"74", + 6780 => x"38", + 6781 => x"80", + 6782 => x"2e", + 6783 => x"78", + 6784 => x"77", + 6785 => x"26", + 6786 => x"18", + 6787 => x"74", + 6788 => x"38", + 6789 => x"be", + 6790 => x"77", + 6791 => x"98", + 6792 => x"c8", + 6793 => x"54", + 6794 => x"58", + 6795 => x"3f", + 6796 => x"08", + 6797 => x"c8", + 6798 => x"30", + 6799 => x"80", + 6800 => x"c8", + 6801 => x"82", + 6802 => x"07", + 6803 => x"07", + 6804 => x"58", + 6805 => x"57", + 6806 => x"38", + 6807 => x"05", + 6808 => x"79", + 6809 => x"cb", + 6810 => x"82", + 6811 => x"8a", + 6812 => x"83", + 6813 => x"06", + 6814 => x"44", + 6815 => x"09", + 6816 => x"38", + 6817 => x"57", + 6818 => x"8a", + 6819 => x"64", + 6820 => x"57", + 6821 => x"27", + 6822 => x"93", + 6823 => x"80", + 6824 => x"38", + 6825 => x"70", + 6826 => x"55", + 6827 => x"95", + 6828 => x"06", + 6829 => x"2e", + 6830 => x"81", + 6831 => x"85", + 6832 => x"8f", + 6833 => x"06", + 6834 => x"82", + 6835 => x"2e", + 6836 => x"77", + 6837 => x"2e", + 6838 => x"80", + 6839 => x"b4", + 6840 => x"2a", + 6841 => x"81", + 6842 => x"9c", + 6843 => x"52", + 6844 => x"74", + 6845 => x"38", + 6846 => x"98", + 6847 => x"79", + 6848 => x"18", + 6849 => x"57", + 6850 => x"80", + 6851 => x"76", + 6852 => x"38", + 6853 => x"51", + 6854 => x"3f", + 6855 => x"08", + 6856 => x"08", + 6857 => x"7f", + 6858 => x"52", + 6859 => x"88", + 6860 => x"c8", + 6861 => x"5b", + 6862 => x"80", + 6863 => x"43", + 6864 => x"0a", + 6865 => x"8b", + 6866 => x"89", + 6867 => x"b4", + 6868 => x"2a", + 6869 => x"81", + 6870 => x"8c", + 6871 => x"52", + 6872 => x"74", + 6873 => x"38", + 6874 => x"98", + 6875 => x"79", + 6876 => x"18", + 6877 => x"57", + 6878 => x"80", + 6879 => x"76", + 6880 => x"38", + 6881 => x"51", + 6882 => x"3f", + 6883 => x"08", + 6884 => x"57", + 6885 => x"08", + 6886 => x"92", + 6887 => x"82", + 6888 => x"83", + 6889 => x"72", + 6890 => x"51", + 6891 => x"52", + 6892 => x"05", + 6893 => x"80", + 6894 => x"c8", + 6895 => x"7e", + 6896 => x"80", + 6897 => x"f2", + 6898 => x"93", + 6899 => x"ff", + 6900 => x"63", + 6901 => x"64", + 6902 => x"ff", + 6903 => x"70", + 6904 => x"31", + 6905 => x"57", + 6906 => x"2e", + 6907 => x"89", + 6908 => x"60", + 6909 => x"84", + 6910 => x"5c", + 6911 => x"16", + 6912 => x"51", + 6913 => x"26", + 6914 => x"65", + 6915 => x"31", + 6916 => x"64", + 6917 => x"fe", + 6918 => x"82", + 6919 => x"56", + 6920 => x"09", + 6921 => x"38", + 6922 => x"08", + 6923 => x"26", + 6924 => x"89", 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x"3f", + 6984 => x"05", + 6985 => x"98", + 6986 => x"98", + 6987 => x"ff", + 6988 => x"51", + 6989 => x"3f", + 6990 => x"1f", + 6991 => x"bb", + 6992 => x"2e", + 6993 => x"80", + 6994 => x"88", + 6995 => x"80", + 6996 => x"ff", + 6997 => x"7b", + 6998 => x"51", + 6999 => x"3f", + 7000 => x"1f", + 7001 => x"93", + 7002 => x"b0", + 7003 => x"97", + 7004 => x"52", + 7005 => x"ff", + 7006 => x"ff", + 7007 => x"c0", + 7008 => x"7f", + 7009 => x"34", + 7010 => x"fb", + 7011 => x"c7", + 7012 => x"98", + 7013 => x"39", + 7014 => x"0a", + 7015 => x"51", + 7016 => x"3f", + 7017 => x"ff", + 7018 => x"1f", + 7019 => x"ad", + 7020 => x"7f", + 7021 => x"a9", + 7022 => x"34", + 7023 => x"fb", + 7024 => x"1f", + 7025 => x"e2", + 7026 => x"d5", + 7027 => x"1f", + 7028 => x"89", + 7029 => x"63", + 7030 => x"79", + 7031 => x"f9", + 7032 => x"82", + 7033 => x"83", + 7034 => x"83", + 7035 => x"06", + 7036 => x"81", + 7037 => x"05", + 7038 => x"79", + 7039 => x"d9", + 7040 => x"80", + 7041 => x"ff", + 7042 => x"84", + 7043 => x"d2", + 7044 => x"ff", + 7045 => x"86", + 7046 => x"f2", + 7047 => x"1f", + 7048 => x"d7", + 7049 => x"52", + 7050 => x"51", + 7051 => x"3f", + 7052 => x"ec", + 7053 => x"96", + 7054 => x"d4", + 7055 => x"fe", + 7056 => x"96", + 7057 => x"54", + 7058 => x"53", + 7059 => x"51", + 7060 => x"3f", + 7061 => x"81", + 7062 => x"52", + 7063 => x"92", + 7064 => x"53", + 7065 => x"51", + 7066 => x"3f", + 7067 => x"5b", + 7068 => x"09", + 7069 => x"38", + 7070 => x"51", + 7071 => x"3f", + 7072 => x"1f", + 7073 => x"f3", + 7074 => x"52", + 7075 => x"ff", + 7076 => x"95", + 7077 => x"ff", + 7078 => x"81", + 7079 => x"f8", + 7080 => x"7e", + 7081 => x"d3", + 7082 => x"60", + 7083 => x"26", + 7084 => x"57", + 7085 => x"53", + 7086 => x"51", + 7087 => x"3f", + 7088 => x"08", + 7089 => x"7d", + 7090 => x"7e", + 7091 => x"fe", + 7092 => x"75", + 7093 => x"56", + 7094 => x"81", + 7095 => x"80", + 7096 => x"38", + 7097 => x"83", + 7098 => x"62", + 7099 => x"74", + 7100 => x"38", + 7101 => x"54", + 7102 => x"52", + 7103 => x"91", + 7104 => x"93", + 7105 => x"c8", + 7106 => x"75", + 7107 => x"56", + 7108 => x"8c", + 7109 => x"2e", + 7110 => x"57", + 7111 => x"ff", + 7112 => x"84", + 7113 => x"2e", + 7114 => x"57", + 7115 => x"81", + 7116 => x"80", + 7117 => x"53", + 7118 => x"51", + 7119 => x"3f", + 7120 => x"52", + 7121 => x"51", + 7122 => x"3f", + 7123 => x"56", + 7124 => x"81", + 7125 => x"34", + 7126 => x"17", + 7127 => x"17", + 7128 => x"17", + 7129 => x"05", + 7130 => x"c1", + 7131 => x"fe", + 7132 => x"fe", + 7133 => x"34", + 7134 => x"08", + 7135 => x"07", + 7136 => x"17", + 7137 => x"c8", + 7138 => x"34", + 7139 => x"c6", + 7140 => x"93", + 7141 => x"52", + 7142 => x"51", + 7143 => x"3f", + 7144 => x"53", + 7145 => x"51", + 7146 => x"3f", + 7147 => x"93", + 7148 => x"38", + 7149 => x"52", + 7150 => x"91", + 7151 => x"57", + 7152 => x"08", + 7153 => x"39", + 7154 => x"39", + 7155 => x"39", + 7156 => x"39", + 7157 => x"82", + 7158 => x"98", + 7159 => x"ff", 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=> x"65", + 7983 => x"3d", + 7984 => x"38", + 7985 => x"00", + 7986 => x"20", + 7987 => x"74", + 7988 => x"20", + 7989 => x"72", + 7990 => x"64", + 7991 => x"73", + 7992 => x"20", + 7993 => x"3d", + 7994 => x"38", + 7995 => x"00", + 7996 => x"20", + 7997 => x"50", + 7998 => x"64", + 7999 => x"20", + 8000 => x"20", + 8001 => x"20", + 8002 => x"20", + 8003 => x"3d", + 8004 => x"38", + 8005 => x"00", + 8006 => x"20", + 8007 => x"79", + 8008 => x"6d", + 8009 => x"6f", + 8010 => x"46", + 8011 => x"20", + 8012 => x"20", + 8013 => x"3d", + 8014 => x"38", + 8015 => x"00", + 8016 => x"6d", + 8017 => x"00", + 8018 => x"65", + 8019 => x"6d", + 8020 => x"6c", + 8021 => x"00", + 8022 => x"56", + 8023 => x"56", + 8024 => x"6e", + 8025 => x"6e", + 8026 => x"77", + 8027 => x"44", + 8028 => x"2a", + 8029 => x"3b", + 8030 => x"3f", + 8031 => x"7f", + 8032 => x"41", + 8033 => x"41", + 8034 => x"00", + 8035 => x"0a", + 8036 => x"0a", + 8037 => x"0a", + 8038 => x"0a", + 8039 => x"0a", + 8040 => x"0a", + 8041 => x"0a", + 8042 => x"0a", + 8043 => x"0a", + 8044 => x"30", + 8045 => x"fe", + 8046 => x"44", + 8047 => x"2e", + 8048 => x"4f", + 8049 => x"4d", + 8050 => x"20", + 8051 => x"54", + 8052 => x"20", + 8053 => x"4f", + 8054 => x"4d", + 8055 => x"20", + 8056 => x"54", + 8057 => x"20", + 8058 => x"00", + 8059 => x"00", + 8060 => x"00", + 8061 => x"00", + 8062 => x"9a", + 8063 => x"41", + 8064 => x"45", + 8065 => x"49", + 8066 => x"92", + 8067 => x"4f", + 8068 => x"99", + 8069 => x"9d", + 8070 => x"49", + 8071 => x"a5", + 8072 => x"a9", + 8073 => x"ad", + 8074 => x"b1", + 8075 => x"b5", + 8076 => x"b9", + 8077 => x"bd", + 8078 => x"c1", + 8079 => x"c5", + 8080 => x"c9", + 8081 => x"cd", + 8082 => x"d1", + 8083 => x"d5", + 8084 => x"d9", + 8085 => x"dd", + 8086 => x"e1", + 8087 => x"e5", + 8088 => x"e9", + 8089 => x"ed", + 8090 => x"f1", + 8091 => x"f5", + 8092 => x"f9", + 8093 => x"fd", + 8094 => x"2e", + 8095 => x"5b", + 8096 => x"22", + 8097 => x"3e", + 8098 => x"00", + 8099 => x"01", + 8100 => x"10", + 8101 => x"00", + 8102 => x"00", + 8103 => x"01", + 8104 => x"04", + 8105 => x"10", + 8106 => x"00", + 8107 => x"41", + 8108 => x"00", + 8109 => x"41", + 8110 => x"00", + 8111 => x"78", + 8112 => x"00", + 8113 => x"49", + 8114 => x"49", + 8115 => x"4f", + 8116 => x"4f", + 8117 => x"00", + 8118 => x"49", + 8119 => x"42", + 8120 => x"45", + 8121 => x"4f", + 8122 => x"4f", + 8123 => x"00", + 8124 => x"49", + 8125 => x"59", + 8126 => x"4d", + 8127 => x"4e", + 8128 => x"4c", + 8129 => x"45", + 8130 => x"59", + 8131 => x"41", + 8132 => x"41", + 8133 => x"00", + 8134 => x"45", + 8135 => x"4e", + 8136 => x"58", + 8137 => x"54", + 8138 => x"00", + 8139 => x"49", + 8140 => x"43", + 8141 => x"41", + 8142 => x"00", + 8143 => x"64", + 8144 => x"00", + 8145 => x"69", + 8146 => x"00", + 8147 => x"73", + 8148 => x"00", + 8149 => x"69", + 8150 => x"6c", + 8151 => x"64", + 8152 => x"00", + 8153 => x"65", + 8154 => x"00", + 8155 => x"72", + 8156 => x"00", + 8157 => x"77", + 8158 => x"65", + 8159 => x"66", + 8160 => x"00", + 8161 => x"6c", + 8162 => x"00", + 8163 => x"69", + 8164 => x"00", + 8165 => x"6f", + 8166 => x"00", + 8167 => x"63", + 8168 => x"65", + 8169 => x"73", + 8170 => x"00", + 8171 => x"72", + 8172 => x"00", + 8173 => x"69", + 8174 => x"65", + 8175 => x"00", + 8176 => x"77", + 8177 => x"65", + 8178 => x"74", + 8179 => x"63", + 8180 => x"61", + 8181 => x"63", + 8182 => x"61", + 8183 => x"00", + 8184 => x"74", + 8185 => x"00", + 8186 => x"72", + 8187 => x"6d", + 8188 => x"64", + 8189 => x"00", + 8190 => x"6d", + 8191 => x"72", + 8192 => x"73", + 8193 => x"00", + 8194 => x"64", + 8195 => x"00", + 8196 => x"63", + 8197 => x"00", + 8198 => x"63", + 8199 => x"63", + 8200 => x"61", + 8201 => x"78", + 8202 => x"63", + 8203 => x"6c", + 8204 => x"00", + 8205 => x"65", + 8206 => x"00", + 8207 => x"73", + 8208 => x"00", + 8209 => x"64", + 8210 => x"00", + 8211 => x"63", + 8212 => x"64", + 8213 => x"65", + 8214 => x"73", + 8215 => x"64", + 8216 => x"00", + 8217 => x"6c", + 8218 => x"6c", + 8219 => x"6d", + 8220 => x"00", + 8221 => x"63", + 8222 => x"00", + 8223 => x"64", + 8224 => x"00", + 8225 => x"65", + 8226 => x"65", + 8227 => x"65", + 8228 => x"69", + 8229 => x"69", + 8230 => x"72", + 8231 => x"74", + 8232 => x"66", + 8233 => x"66", + 8234 => x"68", + 8235 => x"00", + 8236 => x"6f", + 8237 => x"61", + 8238 => x"00", + 8239 => x"61", + 8240 => x"00", + 8241 => x"6d", + 8242 => x"65", + 8243 => x"72", + 8244 => x"65", + 8245 => x"00", + 8246 => x"65", + 8247 => x"00", + 8248 => x"6e", + 8249 => x"00", + 8250 => x"69", + 8251 => x"00", + 8252 => x"65", + 8253 => x"00", + 8254 => x"69", + 8255 => x"45", + 8256 => x"72", + 8257 => x"6e", + 8258 => x"6e", + 8259 => x"65", + 8260 => x"72", + 8261 => x"00", + 8262 => x"69", + 8263 => x"6e", + 8264 => x"72", + 8265 => x"79", + 8266 => x"00", + 8267 => x"6f", + 8268 => x"6c", + 8269 => x"6f", + 8270 => x"2e", + 8271 => x"6f", + 8272 => x"74", + 8273 => x"6f", + 8274 => x"2e", + 8275 => x"6e", + 8276 => x"69", + 8277 => x"69", + 8278 => x"61", + 8279 => x"0a", + 8280 => x"63", + 8281 => x"73", + 8282 => x"6e", + 8283 => x"2e", + 8284 => x"69", + 8285 => x"61", + 8286 => x"61", + 8287 => x"65", + 8288 => x"74", + 8289 => x"00", + 8290 => x"69", + 8291 => x"68", + 8292 => x"6c", + 8293 => x"6e", + 8294 => x"69", + 8295 => x"00", + 8296 => x"44", + 8297 => x"20", + 8298 => x"74", + 8299 => x"72", + 8300 => x"63", + 8301 => x"2e", + 8302 => x"72", + 8303 => x"20", + 8304 => x"62", + 8305 => x"69", + 8306 => x"6e", + 8307 => x"69", + 8308 => x"00", + 8309 => x"69", + 8310 => x"6e", + 8311 => x"65", + 8312 => x"6c", + 8313 => x"0a", + 8314 => x"6f", + 8315 => x"6d", + 8316 => x"69", + 8317 => x"20", + 8318 => x"65", + 8319 => x"74", + 8320 => x"66", + 8321 => x"64", + 8322 => x"20", + 8323 => x"6b", + 8324 => x"00", + 8325 => x"6f", + 8326 => x"74", + 8327 => x"6f", + 8328 => x"64", + 8329 => x"00", + 8330 => x"69", + 8331 => x"75", + 8332 => x"6f", + 8333 => x"61", + 8334 => x"6e", + 8335 => x"6e", + 8336 => x"6c", + 8337 => x"0a", + 8338 => x"69", + 8339 => x"69", + 8340 => x"6f", + 8341 => x"64", + 8342 => x"00", + 8343 => x"6e", + 8344 => x"66", + 8345 => x"65", + 8346 => x"6d", + 8347 => x"72", + 8348 => x"00", + 8349 => x"6f", + 8350 => x"61", + 8351 => x"6f", + 8352 => x"20", + 8353 => x"65", + 8354 => x"00", + 8355 => x"61", + 8356 => x"65", + 8357 => x"73", + 8358 => x"63", + 8359 => x"65", + 8360 => x"0a", + 8361 => x"75", + 8362 => x"73", + 8363 => x"00", + 8364 => x"6e", + 8365 => x"77", + 8366 => x"72", + 8367 => x"2e", + 8368 => x"25", + 8369 => x"62", + 8370 => x"73", + 8371 => x"20", + 8372 => x"25", + 8373 => x"62", + 8374 => x"73", + 8375 => x"63", + 8376 => x"00", + 8377 => x"65", + 8378 => x"00", + 8379 => x"50", + 8380 => x"00", + 8381 => x"2a", + 8382 => x"73", + 8383 => x"00", + 8384 => x"38", + 8385 => x"2f", + 8386 => x"39", + 8387 => x"31", + 8388 => x"00", + 8389 => x"5a", + 8390 => x"20", + 8391 => x"20", + 8392 => x"78", + 8393 => x"73", + 8394 => x"20", + 8395 => x"0a", + 8396 => x"50", + 8397 => x"20", + 8398 => x"65", + 8399 => x"70", + 8400 => x"61", + 8401 => x"65", + 8402 => x"00", + 8403 => x"69", + 8404 => x"20", + 8405 => x"65", + 8406 => x"70", + 8407 => x"00", + 8408 => x"53", + 8409 => x"6e", + 8410 => x"72", + 8411 => x"0a", + 8412 => x"4f", + 8413 => x"20", + 8414 => x"69", + 8415 => x"72", + 8416 => x"74", + 8417 => x"4f", + 8418 => x"20", + 8419 => x"69", + 8420 => x"72", + 8421 => x"74", + 8422 => x"41", + 8423 => x"20", + 8424 => x"69", + 8425 => x"72", + 8426 => x"74", + 8427 => x"41", + 8428 => x"20", + 8429 => x"69", + 8430 => x"72", + 8431 => x"74", + 8432 => x"41", + 8433 => x"20", + 8434 => x"69", + 8435 => x"72", + 8436 => x"74", + 8437 => x"41", + 8438 => x"20", + 8439 => x"69", + 8440 => x"72", + 8441 => x"74", + 8442 => x"65", + 8443 => x"6e", + 8444 => x"70", + 8445 => x"6d", + 8446 => x"2e", + 8447 => x"00", + 8448 => x"6e", + 8449 => x"69", + 8450 => x"74", + 8451 => x"72", + 8452 => x"0a", + 8453 => x"3a", + 8454 => x"61", + 8455 => x"64", + 8456 => x"20", + 8457 => x"74", + 8458 => x"69", + 8459 => x"73", + 8460 => x"61", + 8461 => x"30", + 8462 => x"6c", + 8463 => x"65", + 8464 => x"69", + 8465 => x"61", + 8466 => x"6c", + 8467 => x"0a", + 8468 => x"20", + 8469 => x"61", + 8470 => x"69", + 8471 => x"69", + 8472 => x"00", + 8473 => x"6e", + 8474 => x"61", + 8475 => x"65", + 8476 => x"00", + 8477 => x"61", + 8478 => x"64", + 8479 => x"20", + 8480 => x"74", + 8481 => x"69", + 8482 => x"0a", + 8483 => x"63", + 8484 => x"0a", + 8485 => x"75", + 8486 => x"69", + 8487 => x"6c", + 8488 => x"20", + 8489 => x"65", + 8490 => x"70", + 8491 => x"00", + 8492 => x"6e", + 8493 => x"69", + 8494 => x"69", + 8495 => x"72", + 8496 => x"74", + 8497 => x"00", + 8498 => x"69", + 8499 => x"6c", + 8500 => x"75", + 8501 => x"20", + 8502 => x"6f", + 8503 => x"6e", + 8504 => x"69", + 8505 => x"75", + 8506 => x"20", + 8507 => x"6f", + 8508 => x"78", + 8509 => x"74", + 8510 => x"20", + 8511 => x"65", + 8512 => x"25", + 8513 => x"20", + 8514 => x"0a", + 8515 => x"61", + 8516 => x"6e", + 8517 => x"6f", + 8518 => x"40", + 8519 => x"38", + 8520 => x"2e", + 8521 => x"00", + 8522 => x"61", + 8523 => x"72", + 8524 => x"72", + 8525 => x"20", + 8526 => x"65", + 8527 => x"64", + 8528 => x"00", + 8529 => x"65", + 8530 => x"72", + 8531 => x"67", + 8532 => x"70", + 8533 => x"61", + 8534 => x"6e", + 8535 => x"0a", + 8536 => x"6f", + 8537 => x"72", + 8538 => x"6f", + 8539 => x"67", + 8540 => x"0a", + 8541 => x"50", + 8542 => x"69", + 8543 => x"64", + 8544 => x"73", + 8545 => x"2e", + 8546 => x"00", + 8547 => x"61", + 8548 => x"6f", + 8549 => x"6e", + 8550 => x"00", + 8551 => x"75", + 8552 => x"6e", + 8553 => x"2e", + 8554 => x"6e", + 8555 => x"69", + 8556 => x"69", + 8557 => x"72", + 8558 => x"74", + 8559 => x"2e", + 8560 => x"00", + 8561 => x"00", + 8562 => x"00", + 8563 => x"00", + 8564 => x"00", + 8565 => x"01", + 8566 => x"00", + 8567 => x"00", + 8568 => x"00", + 8569 => x"00", + 8570 => x"00", + 8571 => x"f5", + 8572 => x"01", + 8573 => x"01", + 8574 => x"01", + 8575 => x"00", + 8576 => x"00", + 8577 => x"00", + 8578 => x"00", + 8579 => x"01", + 8580 => x"00", + 8581 => x"00", + 8582 => x"00", + 8583 => x"02", + 8584 => x"00", + 8585 => x"00", + 8586 => x"00", + 8587 => x"03", + 8588 => x"00", + 8589 => x"00", + 8590 => x"00", + 8591 => x"04", + 8592 => x"00", + 8593 => x"00", + 8594 => x"00", + 8595 => x"0a", + 8596 => x"00", + 8597 => x"00", + 8598 => x"00", + 8599 => x"0b", + 8600 => x"00", + 8601 => x"00", + 8602 => x"00", + 8603 => x"0c", + 8604 => x"00", + 8605 => x"00", + 8606 => x"00", + 8607 => x"0d", + 8608 => x"00", + 8609 => x"00", + 8610 => x"00", + 8611 => x"0e", + 8612 => x"00", + 8613 => x"00", + 8614 => x"00", + 8615 => x"0f", + 8616 => x"00", + 8617 => x"00", + 8618 => x"00", + 8619 => x"14", + 8620 => x"00", + 8621 => x"00", + 8622 => x"00", + 8623 => x"17", + 8624 => x"00", + 8625 => x"00", + 8626 => x"00", + 8627 => x"18", + 8628 => x"00", + 8629 => x"00", + 8630 => x"00", + 8631 => x"19", + 8632 => x"00", + 8633 => x"00", + 8634 => x"00", + 8635 => x"1a", + 8636 => x"00", + 8637 => x"00", + 8638 => x"00", + 8639 => x"1c", + 8640 => x"00", + 8641 => x"00", + 8642 => x"00", + 8643 => x"1d", + 8644 => x"00", + 8645 => x"00", + 8646 => x"00", + 8647 => x"1e", + 8648 => x"00", + 8649 => x"00", + 8650 => x"00", + 8651 => x"22", + 8652 => x"00", + 8653 => x"00", + 8654 => x"00", + 8655 => x"23", + 8656 => x"00", + 8657 => x"00", + 8658 => x"00", + 8659 => x"24", + 8660 => x"00", + 8661 => x"00", + 8662 => x"00", + 8663 => x"1f", + 8664 => x"00", + 8665 => x"00", + 8666 => x"00", + 8667 => x"20", + 8668 => x"00", + 8669 => x"00", + 8670 => x"00", + 8671 => x"21", + 8672 => x"00", + 8673 => x"00", + 8674 => x"00", + 8675 => x"15", + 8676 => x"00", + 8677 => x"00", + 8678 => x"00", + 8679 => x"16", + 8680 => x"00", + 8681 => x"00", + 8682 => x"00", + 8683 => x"1b", + 8684 => x"00", + 8685 => x"00", + 8686 => x"00", + 8687 => x"25", + 8688 => x"00", + 8689 => x"00", + 8690 => x"00", + 8691 => x"2d", + 8692 => x"00", + 8693 => x"00", + 8694 => x"00", + 8695 => x"2e", + 8696 => x"00", + 8697 => x"00", + 8698 => x"00", + 8699 => x"2b", + 8700 => x"00", + 8701 => x"00", + 8702 => x"00", + 8703 => x"30", + 8704 => x"00", + 8705 => x"00", + 8706 => x"00", + 8707 => x"2f", + 8708 => x"00", + 8709 => x"00", + 8710 => x"00", + 8711 => x"2c", + 8712 => x"00", + 8713 => x"00", + 8714 => x"00", + 8715 => x"26", + 8716 => x"00", + 8717 => x"00", + 8718 => x"00", + 8719 => x"27", + 8720 => x"00", + 8721 => x"00", + 8722 => x"00", + 8723 => x"28", + 8724 => x"00", + 8725 => x"00", + 8726 => x"00", + 8727 => x"29", + 8728 => x"00", + 8729 => x"00", + 8730 => x"00", + 8731 => x"2a", + 8732 => x"00", + 8733 => x"00", + 8734 => x"00", + 8735 => x"3c", + 8736 => x"00", + 8737 => x"00", + 8738 => x"00", + 8739 => x"3d", + 8740 => x"00", + 8741 => x"00", + 8742 => x"00", + 8743 => x"3e", + 8744 => x"00", + 8745 => x"00", + 8746 => x"00", + 8747 => x"3f", + 8748 => x"00", + 8749 => x"00", + 8750 => x"00", + 8751 => x"40", + 8752 => x"00", + 8753 => x"00", + 8754 => x"00", + 8755 => x"50", + 8756 => x"00", + 8757 => x"00", + 8758 => x"00", + 8759 => x"51", + 8760 => x"00", + 8761 => x"00", + 8762 => x"00", + 8763 => x"52", + 8764 => x"00", + 8765 => x"00", + 8766 => x"00", + 8767 => x"53", + 8768 => x"00", + 8769 => x"00", + 8770 => x"00", + 8771 => x"54", + 8772 => x"00", + 8773 => x"00", + 8774 => x"00", + 8775 => x"55", + 8776 => x"00", + 8777 => x"00", + 8778 => x"00", + 8779 => x"64", + 8780 => x"00", + 8781 => x"00", + 8782 => x"00", + 8783 => x"65", + 8784 => x"00", + 8785 => x"00", + 8786 => x"00", + 8787 => x"79", + 8788 => x"00", + 8789 => x"00", + 8790 => x"00", + 8791 => x"78", + 8792 => x"00", + 8793 => x"00", + 8794 => x"00", + 8795 => x"82", + 8796 => x"00", + 8797 => x"00", + 8798 => x"00", + 8799 => x"83", + 8800 => x"00", + 8801 => x"00", + 8802 => x"00", + 8803 => x"84", + 8804 => x"00", + 8805 => x"00", + 8806 => x"00", + 8807 => x"85", + 8808 => x"00", + 8809 => x"00", + 8810 => x"00", + 8811 => x"86", + 8812 => x"00", + 8813 => x"00", + 8814 => x"00", + 8815 => x"87", + 8816 => x"00", + 8817 => x"00", + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + 0 => x"0b", + 1 => x"e9", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"88", + 9 => x"90", + 10 => x"0b", + 11 => x"2d", + 12 => x"0c", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"71", + 17 => x"72", + 18 => x"81", + 19 => x"83", + 20 => x"ff", + 21 => x"04", + 22 => x"00", + 23 => x"00", + 24 => x"71", + 25 => x"83", + 26 => x"83", + 27 => x"05", + 28 => x"2b", + 29 => x"73", + 30 => x"0b", + 31 => x"83", + 32 => x"72", + 33 => x"72", + 34 => x"09", + 35 => x"73", + 36 => x"07", + 37 => x"53", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"73", + 42 => x"51", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"71", + 50 => x"09", + 51 => x"0a", + 52 => x"0a", + 53 => x"05", + 54 => x"51", + 55 => x"04", + 56 => x"72", + 57 => x"73", + 58 => x"51", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"c4", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"0a", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"09", + 90 => x"0b", + 91 => x"05", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"73", + 98 => x"09", + 99 => x"81", + 100 => x"06", + 101 => x"04", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"04", + 106 => x"06", + 107 => x"82", + 108 => x"0b", + 109 => x"fc", + 110 => x"51", + 111 => x"00", + 112 => x"72", + 113 => x"72", + 114 => x"81", + 115 => x"0a", + 116 => x"51", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"72", + 121 => x"72", + 122 => x"81", + 123 => x"0a", + 124 => x"53", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"71", + 129 => x"52", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"04", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"73", + 146 => x"07", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"71", + 153 => x"72", + 154 => x"81", + 155 => x"10", + 156 => x"81", + 157 => x"04", + 158 => x"00", + 159 => x"00", + 160 => x"71", + 161 => x"0b", + 162 => x"88", + 163 => x"10", + 164 => x"06", + 165 => x"88", + 166 => x"00", + 167 => x"00", + 168 => x"88", + 169 => x"90", + 170 => x"0b", + 171 => x"cb", + 172 => x"88", + 173 => x"0c", + 174 => x"0c", + 175 => x"00", + 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x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"05", + 250 => x"02", + 251 => x"00", + 252 => x"00", + 253 => x"00", + 254 => x"00", + 255 => x"00", + 256 => x"00", + 257 => x"04", + 258 => x"10", + 259 => x"10", + 260 => x"10", + 261 => x"10", + 262 => x"10", + 263 => x"10", + 264 => x"10", + 265 => x"10", + 266 => x"51", + 267 => x"73", + 268 => x"73", + 269 => x"81", + 270 => x"10", + 271 => x"07", + 272 => x"0c", + 273 => x"72", + 274 => x"81", + 275 => x"09", + 276 => x"71", + 277 => x"0a", + 278 => x"72", + 279 => x"51", + 280 => x"80", + 281 => x"e2", + 282 => x"00", + 283 => x"9f", + 284 => x"38", + 285 => x"84", + 286 => x"88", + 287 => x"e2", + 288 => x"04", + 289 => x"94", + 290 => x"0d", + 291 => x"08", + 292 => x"52", + 293 => x"05", + 294 => x"de", + 295 => x"70", + 296 => x"85", + 297 => x"0c", + 298 => x"02", + 299 => x"3d", + 300 => x"94", + 301 => x"08", + 302 => x"88", + 303 => x"82", + 304 => x"08", + 305 => x"54", + 306 => x"94", + 307 => x"08", + 308 => x"f9", + 309 => x"0b", + 310 => x"05", + 311 => x"88", + 312 => x"25", + 313 => x"08", + 314 => x"30", + 315 => x"05", + 316 => x"94", + 317 => x"0c", + 318 => x"05", + 319 => x"81", + 320 => x"f4", + 321 => x"08", + 322 => x"94", + 323 => x"0c", + 324 => x"05", + 325 => x"ab", + 326 => x"8c", + 327 => x"94", + 328 => x"0c", + 329 => x"08", + 330 => x"94", + 331 => x"08", + 332 => x"0b", + 333 => x"05", + 334 => x"f0", + 335 => x"08", + 336 => x"80", + 337 => x"8c", + 338 => x"94", + 339 => x"08", + 340 => x"3f", + 341 => x"94", + 342 => x"0c", + 343 => x"fc", + 344 => x"2e", + 345 => x"08", + 346 => x"30", + 347 => x"05", + 348 => x"f8", + 349 => x"88", + 350 => x"3d", + 351 => x"04", + 352 => x"94", + 353 => x"0d", + 354 => x"08", + 355 => x"94", + 356 => x"08", + 357 => x"38", + 358 => x"05", + 359 => x"08", + 360 => x"81", + 361 => x"fc", + 362 => x"08", + 363 => x"80", + 364 => x"94", + 365 => x"08", + 366 => x"8c", + 367 => x"53", + 368 => x"05", + 369 => x"08", + 370 => x"51", + 371 => x"08", + 372 => x"f8", + 373 => x"94", + 374 => x"08", + 375 => x"38", + 376 => x"05", + 377 => x"08", + 378 => x"94", + 379 => x"08", + 380 => x"54", + 381 => x"94", + 382 => x"08", + 383 => x"fd", + 384 => x"0b", + 385 => x"05", + 386 => x"94", + 387 => x"0c", + 388 => x"05", + 389 => x"88", + 390 => x"ac", + 391 => x"fc", + 392 => x"2e", + 393 => x"0b", + 394 => x"05", + 395 => x"38", + 396 => x"05", + 397 => x"08", + 398 => x"94", + 399 => x"08", + 400 => x"fc", + 401 => x"39", + 402 => x"05", + 403 => x"80", + 404 => x"08", + 405 => x"94", + 406 => x"08", + 407 => x"94", + 408 => x"08", + 409 => x"05", + 410 => x"08", + 411 => x"94", + 412 => x"08", + 413 => x"05", + 414 => x"08", + 415 => x"94", + 416 => x"08", + 417 => x"08", + 418 => x"94", + 419 => x"08", + 420 => x"08", + 421 => x"ff", + 422 => x"08", + 423 => x"80", + 424 => x"94", + 425 => x"08", + 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x"ff", + 489 => x"c0", + 490 => x"51", + 491 => x"81", + 492 => x"92", + 493 => x"c0", + 494 => x"70", + 495 => x"51", + 496 => x"80", + 497 => x"80", + 498 => x"70", + 499 => x"81", + 500 => x"87", + 501 => x"08", + 502 => x"2e", + 503 => x"83", + 504 => x"71", + 505 => x"3d", + 506 => x"3d", + 507 => x"11", + 508 => x"71", + 509 => x"88", + 510 => x"84", + 511 => x"fd", + 512 => x"83", + 513 => x"12", + 514 => x"2b", + 515 => x"07", + 516 => x"70", + 517 => x"2b", + 518 => x"07", + 519 => x"53", + 520 => x"52", + 521 => x"04", + 522 => x"79", + 523 => x"9f", + 524 => x"57", + 525 => x"80", + 526 => x"88", + 527 => x"80", + 528 => x"33", + 529 => x"2e", + 530 => x"83", + 531 => x"80", + 532 => x"54", + 533 => x"fe", + 534 => x"88", + 535 => x"08", + 536 => x"3d", + 537 => x"fd", + 538 => x"08", + 539 => x"51", + 540 => x"88", + 541 => x"ff", + 542 => x"39", + 543 => x"82", + 544 => x"06", + 545 => x"2a", + 546 => x"05", + 547 => x"70", + 548 => x"92", + 549 => x"8e", + 550 => x"fe", + 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x"8f", + 614 => x"80", + 615 => x"13", + 616 => x"8c", + 617 => x"72", + 618 => x"0b", + 619 => x"57", + 620 => x"27", + 621 => x"39", + 622 => x"ff", + 623 => x"2a", + 624 => x"a8", + 625 => x"fc", + 626 => x"52", + 627 => x"27", + 628 => x"52", + 629 => x"17", + 630 => x"38", + 631 => x"16", + 632 => x"51", + 633 => x"88", + 634 => x"0c", + 635 => x"80", + 636 => x"0c", + 637 => x"04", + 638 => x"60", + 639 => x"5e", + 640 => x"55", + 641 => x"09", + 642 => x"38", + 643 => x"44", + 644 => x"62", + 645 => x"56", + 646 => x"09", + 647 => x"38", + 648 => x"80", + 649 => x"0c", + 650 => x"51", + 651 => x"26", + 652 => x"51", + 653 => x"88", + 654 => x"7d", + 655 => x"39", + 656 => x"1d", + 657 => x"5a", + 658 => x"a0", + 659 => x"05", + 660 => x"15", + 661 => x"2e", + 662 => x"ef", + 663 => x"59", + 664 => x"08", + 665 => x"81", + 666 => x"ff", + 667 => x"70", + 668 => x"32", + 669 => x"73", + 670 => x"25", + 671 => x"52", + 672 => x"57", + 673 => x"c7", + 674 => x"2e", + 675 => x"83", + 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x"08", + 739 => x"fd", + 740 => x"88", + 741 => x"0d", + 742 => x"0d", + 743 => x"57", + 744 => x"fe", + 745 => x"76", + 746 => x"3f", + 747 => x"08", + 748 => x"76", + 749 => x"3f", + 750 => x"ff", + 751 => x"82", + 752 => x"d4", + 753 => x"81", + 754 => x"38", + 755 => x"53", + 756 => x"51", + 757 => x"88", + 758 => x"08", + 759 => x"51", + 760 => x"88", + 761 => x"ff", + 762 => x"81", + 763 => x"a9", + 764 => x"80", + 765 => x"52", + 766 => x"aa", + 767 => x"56", + 768 => x"38", + 769 => x"e2", + 770 => x"83", + 771 => x"55", + 772 => x"c6", + 773 => x"81", + 774 => x"0c", + 775 => x"04", + 776 => x"65", + 777 => x"0b", + 778 => x"ac", + 779 => x"3f", + 780 => x"06", + 781 => x"74", + 782 => x"74", + 783 => x"3d", + 784 => x"5a", + 785 => x"88", + 786 => x"06", + 787 => x"2e", + 788 => x"b3", + 789 => x"83", + 790 => x"52", + 791 => x"c6", + 792 => x"ab", + 793 => x"33", + 794 => x"2e", + 795 => x"3d", + 796 => x"f7", + 797 => x"08", + 798 => x"76", + 799 => x"99", + 800 => x"81", + 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x"88", + 864 => x"0c", + 865 => x"19", + 866 => x"1a", + 867 => x"ff", + 868 => x"1a", + 869 => x"84", + 870 => x"1b", + 871 => x"0b", + 872 => x"78", + 873 => x"9f", + 874 => x"56", + 875 => x"95", + 876 => x"ea", + 877 => x"0b", + 878 => x"08", + 879 => x"74", + 880 => x"df", + 881 => x"81", + 882 => x"3d", + 883 => x"69", + 884 => x"70", + 885 => x"05", + 886 => x"3f", + 887 => x"88", + 888 => x"38", + 889 => x"54", + 890 => x"93", + 891 => x"05", + 892 => x"2a", + 893 => x"51", + 894 => x"80", + 895 => x"83", + 896 => x"75", + 897 => x"3f", + 898 => x"16", + 899 => x"dc", + 900 => x"eb", + 901 => x"9c", + 902 => x"98", + 903 => x"0b", + 904 => x"73", + 905 => x"3d", + 906 => x"3d", + 907 => x"7e", + 908 => x"9f", + 909 => x"5b", + 910 => x"7b", + 911 => x"75", + 912 => x"d1", + 913 => x"33", + 914 => x"84", + 915 => x"2e", + 916 => x"91", + 917 => x"17", + 918 => x"80", + 919 => x"34", + 920 => x"b1", + 921 => x"08", + 922 => x"31", + 923 => x"27", + 924 => x"58", + 925 => x"81", + 926 => x"16", + 927 => x"ff", + 928 => x"74", + 929 => x"82", + 930 => x"05", + 931 => x"06", + 932 => x"06", + 933 => x"9e", + 934 => x"38", + 935 => x"55", + 936 => x"16", + 937 => x"80", + 938 => x"55", + 939 => x"ff", + 940 => x"a4", + 941 => x"16", + 942 => x"f3", + 943 => x"55", + 944 => x"2e", + 945 => x"88", + 946 => x"17", + 947 => x"08", + 948 => x"84", + 949 => x"51", + 950 => x"27", + 951 => x"55", + 952 => x"16", + 953 => x"06", + 954 => x"08", + 955 => x"f0", + 956 => x"08", + 957 => x"98", + 958 => x"98", + 959 => x"75", + 960 => x"16", + 961 => x"78", + 962 => x"e8", + 963 => x"59", + 964 => x"80", + 965 => x"0c", + 966 => x"04", + 967 => x"9b", + 968 => x"0b", + 969 => x"8c", + 970 => x"86", + 971 => x"c0", + 972 => x"8c", + 973 => x"87", + 974 => x"0c", + 975 => x"0b", + 976 => x"94", + 977 => x"51", + 978 => x"88", + 979 => x"9f", + 980 => x"df", + 981 => x"ae", + 982 => x"0b", + 983 => x"c0", + 984 => x"55", + 985 => x"05", + 986 => x"52", + 987 => x"ba", + 988 => x"8d", + 989 => x"73", + 990 => x"38", + 991 => x"e4", + 992 => x"54", + 993 => x"54", + 994 => x"00", + 995 => x"ff", + 996 => x"ff", + 997 => x"ff", + 998 => x"42", + 999 => x"54", + 1000 => x"2e", + 1001 => x"00", + 1002 => x"01", + 2048 => x"0b", + 2049 => x"80", + 2050 => x"80", + 2051 => x"ff", + 2052 => x"ff", + 2053 => x"ff", + 2054 => x"ff", + 2055 => x"ff", + 2056 => x"0b", + 2057 => x"80", + 2058 => x"80", + 2059 => x"0b", + 2060 => x"95", + 2061 => x"80", + 2062 => x"0b", + 2063 => x"b5", + 2064 => x"80", + 2065 => x"0b", + 2066 => x"d5", + 2067 => x"80", + 2068 => x"0b", + 2069 => x"f5", + 2070 => x"80", + 2071 => x"0b", + 2072 => x"95", + 2073 => x"80", + 2074 => x"0b", + 2075 => x"b5", + 2076 => x"80", + 2077 => x"0b", + 2078 => x"d5", + 2079 => x"80", + 2080 => x"0b", + 2081 => x"f5", + 2082 => x"80", + 2083 => x"0b", + 2084 => x"95", + 2085 => x"80", + 2086 => x"0b", + 2087 => x"b5", + 2088 => x"80", + 2089 => x"0b", + 2090 => x"d5", + 2091 => x"80", + 2092 => x"0b", + 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x"0c", + 2211 => x"2d", + 2212 => x"08", + 2213 => x"04", + 2214 => x"0c", + 2215 => x"2d", + 2216 => x"08", + 2217 => x"04", + 2218 => x"0c", + 2219 => x"2d", + 2220 => x"08", + 2221 => x"04", + 2222 => x"0c", + 2223 => x"2d", + 2224 => x"08", + 2225 => x"04", + 2226 => x"0c", + 2227 => x"2d", + 2228 => x"08", + 2229 => x"04", + 2230 => x"0c", + 2231 => x"2d", + 2232 => x"08", + 2233 => x"04", + 2234 => x"0c", + 2235 => x"2d", + 2236 => x"08", + 2237 => x"04", + 2238 => x"0c", + 2239 => x"2d", + 2240 => x"08", + 2241 => x"04", + 2242 => x"0c", + 2243 => x"2d", + 2244 => x"08", + 2245 => x"04", + 2246 => x"0c", + 2247 => x"2d", + 2248 => x"08", + 2249 => x"04", + 2250 => x"0c", + 2251 => x"2d", + 2252 => x"08", + 2253 => x"04", + 2254 => x"0c", + 2255 => x"2d", + 2256 => x"08", + 2257 => x"04", + 2258 => x"0c", + 2259 => x"2d", + 2260 => x"08", + 2261 => x"04", + 2262 => x"0c", + 2263 => x"2d", + 2264 => x"08", + 2265 => x"04", + 2266 => x"0c", + 2267 => x"2d", + 2268 => x"08", + 2269 => x"04", + 2270 => x"0c", + 2271 => x"2d", + 2272 => x"08", + 2273 => x"04", + 2274 => x"0c", + 2275 => x"2d", + 2276 => x"08", + 2277 => x"04", + 2278 => x"0c", + 2279 => x"2d", + 2280 => x"08", + 2281 => x"04", + 2282 => x"0c", + 2283 => x"2d", + 2284 => x"08", + 2285 => x"04", + 2286 => x"0c", + 2287 => x"2d", + 2288 => x"08", + 2289 => x"04", + 2290 => x"0c", + 2291 => x"2d", + 2292 => x"08", + 2293 => x"04", + 2294 => x"0c", + 2295 => x"2d", + 2296 => x"08", + 2297 => x"04", + 2298 => x"0c", + 2299 => x"2d", + 2300 => x"08", + 2301 => x"04", + 2302 => x"0c", + 2303 => x"2d", + 2304 => x"08", + 2305 => x"04", + 2306 => x"0c", + 2307 => x"2d", + 2308 => x"08", + 2309 => x"04", + 2310 => x"0c", + 2311 => x"2d", + 2312 => x"08", + 2313 => x"04", + 2314 => x"0c", + 2315 => x"2d", + 2316 => x"08", + 2317 => x"04", + 2318 => x"0c", + 2319 => x"2d", + 2320 => x"08", + 2321 => x"04", + 2322 => x"0c", + 2323 => x"2d", + 2324 => x"08", + 2325 => x"04", + 2326 => x"0c", + 2327 => x"2d", + 2328 => x"08", + 2329 => x"04", + 2330 => x"0c", + 2331 => x"2d", + 2332 => x"08", + 2333 => x"04", + 2334 => x"0c", + 2335 => x"2d", + 2336 => x"08", + 2337 => x"04", + 2338 => x"0c", + 2339 => x"2d", + 2340 => x"08", + 2341 => x"04", + 2342 => x"0c", + 2343 => x"2d", + 2344 => x"08", + 2345 => x"04", + 2346 => x"0c", + 2347 => x"2d", + 2348 => x"08", + 2349 => x"04", + 2350 => x"0c", + 2351 => x"2d", + 2352 => x"08", + 2353 => x"04", + 2354 => x"0c", + 2355 => x"2d", + 2356 => x"08", + 2357 => x"04", + 2358 => x"0c", + 2359 => x"2d", + 2360 => x"08", + 2361 => x"04", + 2362 => x"0c", + 2363 => x"2d", + 2364 => x"08", + 2365 => x"04", + 2366 => x"0c", + 2367 => x"2d", + 2368 => x"08", + 2369 => x"04", + 2370 => x"0c", + 2371 => x"2d", + 2372 => x"08", + 2373 => x"04", + 2374 => x"70", + 2375 => x"27", + 2376 => x"71", + 2377 => x"53", + 2378 => x"80", + 2379 => x"80", + 2380 => x"81", + 2381 => x"3c", + 2382 => x"d4", + 2383 => x"93", + 2384 => x"3d", + 2385 => x"82", + 2386 => x"8c", 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x"0c", + 2446 => x"08", + 2447 => x"82", + 2448 => x"fc", + 2449 => x"82", + 2450 => x"f8", + 2451 => x"93", + 2452 => x"05", + 2453 => x"82", + 2454 => x"fc", + 2455 => x"93", + 2456 => x"05", + 2457 => x"82", + 2458 => x"8c", + 2459 => x"95", + 2460 => x"d4", + 2461 => x"08", + 2462 => x"38", + 2463 => x"08", + 2464 => x"70", + 2465 => x"08", + 2466 => x"51", + 2467 => x"93", + 2468 => x"05", + 2469 => x"93", + 2470 => x"05", + 2471 => x"93", + 2472 => x"05", + 2473 => x"c8", + 2474 => x"0d", + 2475 => x"0c", + 2476 => x"0d", + 2477 => x"02", + 2478 => x"05", + 2479 => x"53", + 2480 => x"27", + 2481 => x"83", + 2482 => x"80", + 2483 => x"ff", + 2484 => x"ff", + 2485 => x"73", + 2486 => x"05", + 2487 => x"12", + 2488 => x"2e", + 2489 => x"ef", + 2490 => x"93", + 2491 => x"3d", + 2492 => x"74", + 2493 => x"07", + 2494 => x"2b", + 2495 => x"51", + 2496 => x"a5", + 2497 => x"70", + 2498 => x"0c", + 2499 => x"84", + 2500 => x"72", + 2501 => x"05", + 2502 => x"71", + 2503 => x"53", + 2504 => x"52", + 2505 => x"dd", + 2506 => x"27", + 2507 => x"71", + 2508 => x"53", + 2509 => x"52", + 2510 => x"f2", + 2511 => x"ff", + 2512 => x"3d", + 2513 => x"70", + 2514 => x"06", + 2515 => x"70", + 2516 => x"73", + 2517 => x"56", + 2518 => x"08", + 2519 => x"38", + 2520 => x"52", + 2521 => x"81", + 2522 => x"54", + 2523 => x"9d", + 2524 => x"55", + 2525 => x"09", + 2526 => x"38", + 2527 => x"14", + 2528 => x"81", + 2529 => x"56", + 2530 => x"e5", + 2531 => x"55", + 2532 => x"06", + 2533 => x"06", + 2534 => x"82", + 2535 => x"52", + 2536 => x"0d", + 2537 => x"70", + 2538 => x"ff", + 2539 => x"f8", + 2540 => x"80", + 2541 => x"51", + 2542 => x"84", + 2543 => x"71", + 2544 => x"54", + 2545 => x"2e", + 2546 => x"75", + 2547 => x"94", + 2548 => x"82", + 2549 => x"87", + 2550 => x"fe", + 2551 => x"70", + 2552 => x"88", + 2553 => x"9b", + 2554 => x"c8", + 2555 => x"06", + 2556 => x"14", + 2557 => x"73", + 2558 => x"71", + 2559 => x"0c", + 2560 => x"04", + 2561 => x"76", + 2562 => x"53", + 2563 => x"80", + 2564 => x"38", + 2565 => x"70", + 2566 => x"81", + 2567 => x"81", + 2568 => x"52", + 2569 => x"2e", + 2570 => x"52", + 2571 => x"12", + 2572 => x"33", + 2573 => x"a0", + 2574 => x"81", + 2575 => x"70", + 2576 => x"06", + 2577 => x"e6", + 2578 => x"51", + 2579 => x"09", + 2580 => x"38", + 2581 => x"81", + 2582 => x"71", + 2583 => x"51", + 2584 => x"c8", + 2585 => x"0d", + 2586 => x"0d", + 2587 => x"08", + 2588 => x"38", + 2589 => x"05", + 2590 => x"99", + 2591 => x"93", + 2592 => x"38", + 2593 => x"39", + 2594 => x"82", + 2595 => x"86", + 2596 => x"f5", + 2597 => x"82", + 2598 => x"05", + 2599 => x"5b", + 2600 => x"81", + 2601 => x"1c", + 2602 => x"5a", + 2603 => x"9e", + 2604 => x"38", + 2605 => x"5a", + 2606 => x"97", + 2607 => x"38", + 2608 => x"5a", + 2609 => x"bb", + 2610 => x"38", + 2611 => x"5a", + 2612 => x"bb", + 2613 => x"38", + 2614 => x"5a", + 2615 => x"87", + 2616 => x"80", + 2617 => x"22", + 2618 => x"79", + 2619 => x"80", + 2620 => x"1c", + 2621 => x"1c", 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x"54", + 2681 => x"53", + 2682 => x"81", + 2683 => x"92", + 2684 => x"3d", + 2685 => x"3d", + 2686 => x"05", + 2687 => x"70", + 2688 => x"51", + 2689 => x"0b", + 2690 => x"34", + 2691 => x"04", + 2692 => x"75", + 2693 => x"8b", + 2694 => x"54", + 2695 => x"84", + 2696 => x"2e", + 2697 => x"c0", + 2698 => x"70", + 2699 => x"2a", + 2700 => x"51", + 2701 => x"80", + 2702 => x"71", + 2703 => x"81", + 2704 => x"70", + 2705 => x"96", + 2706 => x"70", + 2707 => x"51", + 2708 => x"8d", + 2709 => x"2a", + 2710 => x"51", + 2711 => x"bc", + 2712 => x"82", + 2713 => x"51", + 2714 => x"80", + 2715 => x"2e", + 2716 => x"c0", + 2717 => x"73", + 2718 => x"82", + 2719 => x"85", + 2720 => x"fd", + 2721 => x"97", + 2722 => x"0b", + 2723 => x"33", + 2724 => x"c0", + 2725 => x"72", + 2726 => x"38", + 2727 => x"94", + 2728 => x"70", + 2729 => x"81", + 2730 => x"52", + 2731 => x"8c", + 2732 => x"2a", + 2733 => x"51", + 2734 => x"38", + 2735 => x"81", + 2736 => x"06", + 2737 => x"80", + 2738 => x"71", + 2739 => x"81", + 2740 => x"70", + 2741 => x"0b", + 2742 => x"c0", + 2743 => x"c0", + 2744 => x"70", + 2745 => x"38", + 2746 => x"90", + 2747 => x"0c", + 2748 => x"04", + 2749 => x"77", + 2750 => x"33", + 2751 => x"76", + 2752 => x"38", + 2753 => x"05", + 2754 => x"0b", + 2755 => x"33", + 2756 => x"c0", + 2757 => x"72", + 2758 => x"38", + 2759 => x"94", + 2760 => x"70", + 2761 => x"81", + 2762 => x"52", + 2763 => x"8c", + 2764 => x"2a", + 2765 => x"51", + 2766 => x"38", + 2767 => x"81", + 2768 => x"06", + 2769 => x"80", + 2770 => x"71", + 2771 => x"81", + 2772 => x"70", + 2773 => x"0b", + 2774 => x"c0", + 2775 => x"c0", + 2776 => x"70", + 2777 => x"38", + 2778 => x"90", + 2779 => x"0c", + 2780 => x"33", + 2781 => x"ff", + 2782 => x"82", + 2783 => x"87", + 2784 => x"ff", + 2785 => x"0b", + 2786 => x"33", + 2787 => x"94", + 2788 => x"80", + 2789 => x"87", + 2790 => x"51", + 2791 => x"82", + 2792 => x"06", + 2793 => x"70", + 2794 => x"38", + 2795 => x"8b", + 2796 => x"87", + 2797 => x"52", + 2798 => x"86", + 2799 => x"94", + 2800 => x"08", + 2801 => x"06", + 2802 => x"0c", + 2803 => x"0d", + 2804 => x"0d", + 2805 => x"8b", + 2806 => x"87", + 2807 => x"52", + 2808 => x"86", + 2809 => x"94", + 2810 => x"08", + 2811 => x"70", + 2812 => x"51", + 2813 => x"70", + 2814 => x"38", + 2815 => x"8b", + 2816 => x"87", + 2817 => x"52", + 2818 => x"86", + 2819 => x"94", + 2820 => x"08", + 2821 => x"70", + 2822 => x"53", + 2823 => x"93", + 2824 => x"3d", + 2825 => x"3d", + 2826 => x"9e", + 2827 => x"70", + 2828 => x"06", + 2829 => x"70", + 2830 => x"9f", + 2831 => x"c4", + 2832 => x"9e", + 2833 => x"0c", + 2834 => x"c0", + 2835 => x"71", + 2836 => x"11", + 2837 => x"8c", + 2838 => x"52", + 2839 => x"c0", + 2840 => x"71", + 2841 => x"11", + 2842 => x"94", + 2843 => x"52", + 2844 => x"c0", + 2845 => x"71", + 2846 => x"11", + 2847 => x"a4", + 2848 => x"52", + 2849 => x"c0", + 2850 => x"71", + 2851 => x"11", + 2852 => x"ac", + 2853 => x"52", + 2854 => x"52", + 2855 => x"23", + 2856 => x"c0", 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x"06", + 2916 => x"51", + 2917 => x"70", + 2918 => x"05", + 2919 => x"54", + 2920 => x"70", + 2921 => x"52", + 2922 => x"2e", + 2923 => x"52", + 2924 => x"80", + 2925 => x"9e", + 2926 => x"88", + 2927 => x"52", + 2928 => x"83", + 2929 => x"71", + 2930 => x"34", + 2931 => x"88", + 2932 => x"06", + 2933 => x"82", + 2934 => x"85", + 2935 => x"fc", + 2936 => x"f6", + 2937 => x"be", + 2938 => x"f0", + 2939 => x"80", + 2940 => x"81", + 2941 => x"84", + 2942 => x"f6", + 2943 => x"a6", + 2944 => x"f1", + 2945 => x"55", + 2946 => x"91", + 2947 => x"08", + 2948 => x"c4", + 2949 => x"f7", + 2950 => x"84", + 2951 => x"f2", + 2952 => x"55", + 2953 => x"90", + 2954 => x"08", + 2955 => x"08", + 2956 => x"a8", + 2957 => x"3f", + 2958 => x"70", + 2959 => x"73", + 2960 => x"15", + 2961 => x"80", + 2962 => x"82", + 2963 => x"08", + 2964 => x"08", + 2965 => x"f7", + 2966 => x"c4", + 2967 => x"f5", + 2968 => x"80", + 2969 => x"81", + 2970 => x"83", + 2971 => x"8b", + 2972 => x"73", + 2973 => x"38", + 2974 => x"51", + 2975 => x"82", + 2976 => x"54", + 2977 => x"88", + 2978 => x"88", + 2979 => x"3f", + 2980 => x"70", + 2981 => x"73", + 2982 => x"38", + 2983 => x"52", + 2984 => x"51", + 2985 => x"82", + 2986 => x"54", + 2987 => x"88", + 2988 => x"b4", + 2989 => x"3f", + 2990 => x"70", + 2991 => x"73", + 2992 => x"38", + 2993 => x"52", + 2994 => x"51", + 2995 => x"81", + 2996 => x"82", + 2997 => x"8b", + 2998 => x"70", + 2999 => x"08", + 3000 => x"f8", + 3001 => x"88", + 3002 => x"08", + 3003 => x"a0", + 3004 => x"3f", + 3005 => x"52", + 3006 => x"51", + 3007 => x"8c", + 3008 => x"81", + 3009 => x"88", + 3010 => x"15", + 3011 => x"fa", + 3012 => x"8c", + 3013 => x"0d", + 3014 => x"0d", + 3015 => x"33", + 3016 => x"26", + 3017 => x"10", + 3018 => x"81", + 3019 => x"52", + 3020 => x"81", + 3021 => x"f7", + 3022 => x"39", + 3023 => x"51", + 3024 => x"a3", + 3025 => x"d0", + 3026 => x"3f", + 3027 => x"fa", + 3028 => x"a0", + 3029 => x"81", + 3030 => x"f7", + 3031 => x"39", + 3032 => x"51", + 3033 => x"83", + 3034 => x"71", + 3035 => x"04", + 3036 => x"c0", + 3037 => x"04", + 3038 => x"87", + 3039 => x"70", + 3040 => x"80", + 3041 => x"74", + 3042 => x"8c", + 3043 => x"0c", + 3044 => x"04", + 3045 => x"87", + 3046 => x"70", + 3047 => x"80", + 3048 => x"72", + 3049 => x"70", + 3050 => x"08", + 3051 => x"8c", + 3052 => x"0c", + 3053 => x"0d", + 3054 => x"80", + 3055 => x"96", + 3056 => x"fe", + 3057 => x"93", + 3058 => x"72", + 3059 => x"81", + 3060 => x"8d", + 3061 => x"82", + 3062 => x"80", + 3063 => x"82", + 3064 => x"52", + 3065 => x"82", + 3066 => x"81", + 3067 => x"e0", + 3068 => x"82", + 3069 => x"80", + 3070 => x"72", + 3071 => x"d8", + 3072 => x"2d", + 3073 => x"04", + 3074 => x"02", + 3075 => x"82", + 3076 => x"76", + 3077 => x"0c", + 3078 => x"a7", + 3079 => x"93", + 3080 => x"3d", + 3081 => x"3d", + 3082 => x"33", + 3083 => x"80", + 3084 => x"72", + 3085 => x"54", + 3086 => x"87", + 3087 => x"52", + 3088 => x"84", + 3089 => x"fd", + 3090 => x"82", + 3091 => x"77", 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x"70", + 3151 => x"56", + 3152 => x"15", + 3153 => x"26", + 3154 => x"72", + 3155 => x"f0", + 3156 => x"72", + 3157 => x"84", + 3158 => x"57", + 3159 => x"75", + 3160 => x"72", + 3161 => x"38", + 3162 => x"16", + 3163 => x"54", + 3164 => x"38", + 3165 => x"70", + 3166 => x"53", + 3167 => x"73", + 3168 => x"53", + 3169 => x"99", + 3170 => x"2a", + 3171 => x"a0", + 3172 => x"3f", + 3173 => x"73", + 3174 => x"53", + 3175 => x"ef", + 3176 => x"fd", + 3177 => x"81", + 3178 => x"72", + 3179 => x"ce", + 3180 => x"fc", + 3181 => x"81", + 3182 => x"79", + 3183 => x"38", + 3184 => x"7b", + 3185 => x"12", + 3186 => x"53", + 3187 => x"fd", + 3188 => x"5b", + 3189 => x"5b", + 3190 => x"5b", + 3191 => x"5b", + 3192 => x"51", + 3193 => x"fd", + 3194 => x"82", + 3195 => x"06", + 3196 => x"80", + 3197 => x"7b", + 3198 => x"08", + 3199 => x"9c", + 3200 => x"c4", + 3201 => x"06", + 3202 => x"84", + 3203 => x"59", + 3204 => x"39", + 3205 => x"71", + 3206 => x"53", + 3207 => x"32", + 3208 => x"72", + 3209 => x"70", + 3210 => x"06", + 3211 => x"53", + 3212 => x"88", + 3213 => x"7d", + 3214 => x"57", + 3215 => x"52", + 3216 => x"a8", + 3217 => x"c8", + 3218 => x"06", + 3219 => x"52", + 3220 => x"3f", + 3221 => x"08", + 3222 => x"27", + 3223 => x"a7", + 3224 => x"ff", + 3225 => x"54", + 3226 => x"2e", + 3227 => x"14", + 3228 => x"06", + 3229 => x"3d", + 3230 => x"05", + 3231 => x"54", + 3232 => x"81", + 3233 => x"70", + 3234 => x"2a", + 3235 => x"27", + 3236 => x"54", + 3237 => x"a6", + 3238 => x"2a", + 3239 => x"51", + 3240 => x"2e", + 3241 => x"3d", + 3242 => x"05", + 3243 => x"34", + 3244 => x"77", + 3245 => x"54", + 3246 => x"72", + 3247 => x"55", + 3248 => x"70", + 3249 => x"53", + 3250 => x"73", + 3251 => x"53", + 3252 => x"99", + 3253 => x"2a", + 3254 => x"74", + 3255 => x"3f", + 3256 => x"73", + 3257 => x"53", + 3258 => x"ef", + 3259 => x"97", + 3260 => x"11", + 3261 => x"54", + 3262 => x"3f", + 3263 => x"73", + 3264 => x"53", + 3265 => x"fa", + 3266 => x"51", + 3267 => x"73", + 3268 => x"53", + 3269 => x"f2", + 3270 => x"39", + 3271 => x"04", + 3272 => x"86", + 3273 => x"84", + 3274 => x"55", + 3275 => x"fa", + 3276 => x"3d", + 3277 => x"3d", + 3278 => x"93", + 3279 => x"3d", + 3280 => x"75", + 3281 => x"3f", + 3282 => x"08", + 3283 => x"34", + 3284 => x"93", + 3285 => x"3d", + 3286 => x"3d", + 3287 => x"d8", + 3288 => x"93", + 3289 => x"3d", + 3290 => x"77", + 3291 => x"87", + 3292 => x"93", + 3293 => x"3d", + 3294 => x"3d", + 3295 => x"57", + 3296 => x"82", + 3297 => x"73", + 3298 => x"38", + 3299 => x"53", + 3300 => x"80", + 3301 => x"dc", + 3302 => x"2d", + 3303 => x"08", + 3304 => x"54", + 3305 => x"e6", + 3306 => x"2e", + 3307 => x"73", + 3308 => x"30", + 3309 => x"78", + 3310 => x"72", + 3311 => x"52", + 3312 => x"72", + 3313 => x"38", + 3314 => x"81", + 3315 => x"55", + 3316 => x"c1", + 3317 => x"25", + 3318 => x"ff", + 3319 => x"72", + 3320 => x"38", + 3321 => x"73", + 3322 => x"15", + 3323 => x"06", + 3324 => x"cf", + 3325 => x"39", + 3326 => x"80", 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x"80", + 3386 => x"89", + 3387 => x"70", + 3388 => x"55", + 3389 => x"70", + 3390 => x"55", + 3391 => x"27", + 3392 => x"14", + 3393 => x"06", + 3394 => x"74", + 3395 => x"73", + 3396 => x"38", + 3397 => x"14", + 3398 => x"05", + 3399 => x"08", + 3400 => x"54", + 3401 => x"26", + 3402 => x"77", + 3403 => x"38", + 3404 => x"75", + 3405 => x"56", + 3406 => x"c8", + 3407 => x"0d", + 3408 => x"0d", + 3409 => x"55", + 3410 => x"0c", + 3411 => x"33", + 3412 => x"73", + 3413 => x"81", + 3414 => x"74", + 3415 => x"75", + 3416 => x"70", + 3417 => x"73", + 3418 => x"38", + 3419 => x"09", + 3420 => x"38", + 3421 => x"11", + 3422 => x"08", + 3423 => x"54", + 3424 => x"2e", + 3425 => x"80", + 3426 => x"08", + 3427 => x"0c", + 3428 => x"33", + 3429 => x"80", + 3430 => x"38", + 3431 => x"2e", + 3432 => x"a1", + 3433 => x"81", + 3434 => x"75", + 3435 => x"56", + 3436 => x"c1", + 3437 => x"08", + 3438 => x"0c", + 3439 => x"33", + 3440 => x"b1", + 3441 => x"a0", + 3442 => x"82", + 3443 => x"53", + 3444 => x"57", + 3445 => x"9d", + 3446 => x"39", + 3447 => x"80", + 3448 => x"26", + 3449 => x"8b", + 3450 => x"80", + 3451 => x"56", + 3452 => x"8a", + 3453 => x"a0", + 3454 => x"c5", + 3455 => x"74", + 3456 => x"e0", + 3457 => x"ff", + 3458 => x"d0", + 3459 => x"ff", + 3460 => x"90", + 3461 => x"38", + 3462 => x"81", + 3463 => x"53", + 3464 => x"c5", + 3465 => x"27", + 3466 => x"76", + 3467 => x"08", + 3468 => x"0c", + 3469 => x"33", + 3470 => x"73", + 3471 => x"bd", + 3472 => x"2e", + 3473 => x"30", + 3474 => x"0c", + 3475 => x"82", + 3476 => x"8a", + 3477 => x"ff", + 3478 => x"8f", + 3479 => x"81", + 3480 => x"26", + 3481 => x"8c", + 3482 => x"52", + 3483 => x"c8", + 3484 => x"0d", + 3485 => x"0d", + 3486 => x"33", + 3487 => x"9b", + 3488 => x"53", + 3489 => x"81", + 3490 => x"38", + 3491 => x"87", + 3492 => x"05", + 3493 => x"73", + 3494 => x"38", + 3495 => x"71", + 3496 => x"90", + 3497 => x"92", + 3498 => x"81", + 3499 => x"0b", + 3500 => x"8c", + 3501 => x"87", + 3502 => x"54", + 3503 => x"82", + 3504 => x"70", + 3505 => x"38", + 3506 => x"70", + 3507 => x"90", + 3508 => x"92", + 3509 => x"08", + 3510 => x"06", + 3511 => x"92", + 3512 => x"98", + 3513 => x"70", + 3514 => x"38", + 3515 => x"84", + 3516 => x"8c", + 3517 => x"51", + 3518 => x"c8", + 3519 => x"0d", + 3520 => x"0d", + 3521 => x"02", + 3522 => x"c3", + 3523 => x"41", + 3524 => x"73", + 3525 => x"bf", + 3526 => x"c8", + 3527 => x"7b", + 3528 => x"81", + 3529 => x"70", + 3530 => x"c0", + 3531 => x"84", + 3532 => x"92", + 3533 => x"c0", + 3534 => x"72", + 3535 => x"5b", + 3536 => x"0c", + 3537 => x"80", + 3538 => x"0c", + 3539 => x"0c", + 3540 => x"85", + 3541 => x"06", + 3542 => x"71", + 3543 => x"38", + 3544 => x"71", + 3545 => x"05", + 3546 => x"17", + 3547 => x"06", + 3548 => x"2e", + 3549 => x"08", + 3550 => x"38", + 3551 => x"71", + 3552 => x"38", + 3553 => x"2e", + 3554 => x"75", + 3555 => x"92", + 3556 => x"72", + 3557 => x"06", + 3558 => x"f7", + 3559 => x"5b", + 3560 => x"80", + 3561 => x"70", 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x"71", + 3621 => x"7c", + 3622 => x"38", + 3623 => x"80", + 3624 => x"80", + 3625 => x"81", + 3626 => x"73", + 3627 => x"0c", + 3628 => x"04", + 3629 => x"7d", + 3630 => x"af", + 3631 => x"88", + 3632 => x"33", + 3633 => x"56", + 3634 => x"3f", + 3635 => x"08", + 3636 => x"83", + 3637 => x"38", + 3638 => x"74", + 3639 => x"72", + 3640 => x"38", + 3641 => x"8a", + 3642 => x"72", + 3643 => x"38", + 3644 => x"90", + 3645 => x"92", + 3646 => x"08", + 3647 => x"39", + 3648 => x"76", + 3649 => x"8b", + 3650 => x"76", + 3651 => x"83", + 3652 => x"73", + 3653 => x"0c", + 3654 => x"04", + 3655 => x"73", + 3656 => x"12", + 3657 => x"2b", + 3658 => x"93", + 3659 => x"52", + 3660 => x"0d", + 3661 => x"0d", + 3662 => x"33", + 3663 => x"71", + 3664 => x"88", + 3665 => x"14", + 3666 => x"74", + 3667 => x"2b", + 3668 => x"c8", + 3669 => x"56", + 3670 => x"3d", + 3671 => x"3d", + 3672 => x"84", + 3673 => x"22", + 3674 => x"72", + 3675 => x"54", + 3676 => x"2a", + 3677 => x"34", + 3678 => x"04", + 3679 => x"73", + 3680 => x"70", + 3681 => x"05", + 3682 => x"88", + 3683 => x"72", + 3684 => x"54", + 3685 => x"2a", + 3686 => x"70", + 3687 => x"34", + 3688 => x"51", + 3689 => x"83", + 3690 => x"fe", + 3691 => x"75", + 3692 => x"51", + 3693 => x"93", + 3694 => x"81", + 3695 => x"73", + 3696 => x"55", + 3697 => x"51", + 3698 => x"84", + 3699 => x"fe", + 3700 => x"77", + 3701 => x"53", + 3702 => x"81", + 3703 => x"ff", + 3704 => x"f4", + 3705 => x"0d", + 3706 => x"0d", + 3707 => x"56", + 3708 => x"70", + 3709 => x"33", + 3710 => x"05", + 3711 => x"71", + 3712 => x"56", + 3713 => x"72", + 3714 => x"38", + 3715 => x"e2", + 3716 => x"93", + 3717 => x"3d", + 3718 => x"3d", + 3719 => x"71", + 3720 => x"52", + 3721 => x"99", + 3722 => x"2e", + 3723 => x"12", + 3724 => x"52", + 3725 => x"89", + 3726 => x"2e", + 3727 => x"ee", + 3728 => x"82", + 3729 => x"84", + 3730 => x"80", + 3731 => x"c8", + 3732 => x"0b", + 3733 => x"0c", + 3734 => x"0d", + 3735 => x"0b", + 3736 => x"56", + 3737 => x"2e", + 3738 => x"81", + 3739 => x"08", + 3740 => x"70", + 3741 => x"33", + 3742 => x"de", + 3743 => x"c8", + 3744 => x"09", + 3745 => x"38", + 3746 => x"08", + 3747 => x"b0", + 3748 => x"17", + 3749 => x"74", + 3750 => x"27", + 3751 => x"16", + 3752 => x"82", + 3753 => x"06", + 3754 => x"54", + 3755 => x"9c", + 3756 => x"53", + 3757 => x"16", + 3758 => x"9e", + 3759 => x"81", + 3760 => x"93", + 3761 => x"3d", + 3762 => x"3d", + 3763 => x"56", + 3764 => x"b0", + 3765 => x"2e", + 3766 => x"51", + 3767 => x"82", + 3768 => x"56", + 3769 => x"08", + 3770 => x"54", + 3771 => x"17", + 3772 => x"33", + 3773 => x"3f", + 3774 => x"08", + 3775 => x"38", + 3776 => x"56", + 3777 => x"0c", + 3778 => x"c8", + 3779 => x"0d", + 3780 => x"0d", + 3781 => x"57", + 3782 => x"82", + 3783 => x"58", + 3784 => x"08", + 3785 => x"76", + 3786 => x"83", + 3787 => x"06", + 3788 => x"84", + 3789 => x"78", + 3790 => x"81", + 3791 => x"38", + 3792 => x"82", + 3793 => x"52", + 3794 => x"52", + 3795 => x"3f", + 3796 => x"52", + 3797 => x"51", + 3798 => x"84", + 3799 => x"d2", + 3800 => x"fc", + 3801 => x"8a", + 3802 => x"52", + 3803 => x"51", + 3804 => x"90", + 3805 => x"84", + 3806 => x"fb", + 3807 => x"17", + 3808 => x"a0", + 3809 => x"f4", + 3810 => x"08", + 3811 => x"b0", + 3812 => x"55", + 3813 => x"81", + 3814 => x"f8", + 3815 => x"84", + 3816 => x"53", + 3817 => x"17", + 3818 => x"88", + 3819 => x"c8", + 3820 => x"83", + 3821 => x"77", + 3822 => x"0c", + 3823 => x"04", + 3824 => x"77", + 3825 => x"12", + 3826 => x"55", + 3827 => x"56", + 3828 => x"8d", + 3829 => x"22", + 3830 => x"ac", + 3831 => x"57", + 3832 => x"93", + 3833 => x"3d", + 3834 => x"3d", + 3835 => x"70", + 3836 => x"55", + 3837 => x"88", + 3838 => x"08", + 3839 => x"38", + 3840 => x"d9", + 3841 => x"33", + 3842 => x"82", + 3843 => x"38", + 3844 => x"89", + 3845 => x"2e", + 3846 => x"bf", + 3847 => x"2e", + 3848 => x"81", + 3849 => x"81", + 3850 => x"89", + 3851 => x"08", + 3852 => x"52", + 3853 => x"3f", + 3854 => x"08", + 3855 => x"76", + 3856 => x"14", + 3857 => x"81", + 3858 => x"2a", + 3859 => x"05", + 3860 => x"59", + 3861 => x"f2", + 3862 => x"c8", + 3863 => x"38", + 3864 => x"06", + 3865 => x"33", + 3866 => x"7a", + 3867 => x"06", + 3868 => x"5a", + 3869 => x"53", + 3870 => x"38", + 3871 => x"06", + 3872 => x"39", + 3873 => x"a4", + 3874 => x"52", + 3875 => x"ba", + 3876 => x"c8", + 3877 => x"38", + 3878 => x"ff", + 3879 => x"b4", + 3880 => x"f8", + 3881 => x"c8", + 3882 => x"ff", + 3883 => x"39", + 3884 => x"a4", + 3885 => x"52", + 3886 => x"8e", + 3887 => x"c8", + 3888 => x"74", + 3889 => x"fc", + 3890 => x"b4", + 3891 => x"e5", + 3892 => x"c8", + 3893 => x"06", + 3894 => x"81", + 3895 => x"93", + 3896 => x"3d", + 3897 => x"3d", + 3898 => x"7f", + 3899 => x"82", + 3900 => x"27", + 3901 => x"73", + 3902 => x"27", + 3903 => x"74", + 3904 => x"77", + 3905 => x"38", + 3906 => x"89", + 3907 => x"2e", + 3908 => x"91", + 3909 => x"2e", + 3910 => x"82", + 3911 => x"81", + 3912 => x"89", + 3913 => x"08", + 3914 => x"52", + 3915 => x"3f", + 3916 => x"08", + 3917 => x"c8", + 3918 => x"38", + 3919 => x"06", + 3920 => x"81", + 3921 => x"06", + 3922 => x"58", + 3923 => x"80", + 3924 => x"75", + 3925 => x"f0", + 3926 => x"8f", + 3927 => x"58", + 3928 => x"34", + 3929 => x"16", + 3930 => x"2a", + 3931 => x"05", + 3932 => x"fa", + 3933 => x"93", + 3934 => x"82", + 3935 => x"81", + 3936 => x"83", + 3937 => x"b4", + 3938 => x"06", + 3939 => x"57", + 3940 => x"72", + 3941 => x"88", + 3942 => x"57", + 3943 => x"81", + 3944 => x"54", + 3945 => x"81", + 3946 => x"34", + 3947 => x"73", + 3948 => x"16", + 3949 => x"74", + 3950 => x"3f", + 3951 => x"08", + 3952 => x"c8", + 3953 => x"38", + 3954 => x"ff", + 3955 => x"14", + 3956 => x"75", + 3957 => x"51", + 3958 => x"81", + 3959 => x"34", + 3960 => x"73", + 3961 => x"16", + 3962 => x"74", + 3963 => x"3f", + 3964 => x"08", + 3965 => x"c8", + 3966 => x"75", + 3967 => x"74", + 3968 => x"fc", + 3969 => x"b4", + 3970 => x"51", + 3971 => x"a5", + 3972 => x"c8", + 3973 => x"06", + 3974 => x"72", + 3975 => x"3f", + 3976 => x"16", + 3977 => x"93", + 3978 => x"3d", + 3979 => x"3d", + 3980 => x"7d", + 3981 => x"58", + 3982 => x"74", + 3983 => x"98", + 3984 => x"26", + 3985 => x"56", + 3986 => x"75", + 3987 => x"38", + 3988 => x"52", + 3989 => x"8e", + 3990 => x"c8", + 3991 => x"93", + 3992 => x"f4", + 3993 => x"82", + 3994 => x"39", + 3995 => x"e8", + 3996 => x"c8", + 3997 => x"e0", + 3998 => x"76", + 3999 => x"3f", + 4000 => x"08", + 4001 => x"c8", + 4002 => x"80", + 4003 => x"93", + 4004 => x"2e", + 4005 => x"93", + 4006 => x"2e", + 4007 => x"53", + 4008 => x"51", + 4009 => x"82", + 4010 => x"c5", + 4011 => x"08", + 4012 => x"90", + 4013 => x"27", + 4014 => x"15", + 4015 => x"90", + 4016 => x"15", + 4017 => x"54", + 4018 => x"34", + 4019 => x"15", + 4020 => x"ff", + 4021 => x"56", + 4022 => x"c8", + 4023 => x"0d", + 4024 => x"0d", + 4025 => x"08", + 4026 => x"7a", + 4027 => x"19", + 4028 => x"80", + 4029 => x"98", + 4030 => x"26", + 4031 => x"58", + 4032 => x"52", + 4033 => x"e2", + 4034 => x"74", + 4035 => x"08", + 4036 => x"38", + 4037 => x"08", + 4038 => x"c8", + 4039 => x"82", + 4040 => x"93", + 4041 => x"98", + 4042 => x"93", + 4043 => x"82", + 4044 => x"58", + 4045 => x"19", + 4046 => x"82", + 4047 => x"57", + 4048 => x"09", + 4049 => x"db", + 4050 => x"57", + 4051 => x"77", + 4052 => x"82", + 4053 => x"7b", + 4054 => x"3f", + 4055 => x"08", + 4056 => x"82", + 4057 => x"81", + 4058 => x"06", + 4059 => x"93", + 4060 => x"75", + 4061 => x"30", + 4062 => x"80", + 4063 => x"07", + 4064 => x"52", + 4065 => x"81", + 4066 => x"80", + 4067 => x"8c", + 4068 => x"81", + 4069 => x"38", + 4070 => x"08", + 4071 => x"75", + 4072 => x"76", + 4073 => x"77", + 4074 => x"57", + 4075 => x"77", + 4076 => x"82", + 4077 => x"26", + 4078 => x"76", + 4079 => x"f8", + 4080 => x"93", + 4081 => x"82", + 4082 => x"80", + 4083 => x"80", + 4084 => x"c8", + 4085 => x"09", + 4086 => x"38", + 4087 => x"08", + 4088 => x"32", + 4089 => x"72", + 4090 => x"70", + 4091 => x"52", + 4092 => x"80", + 4093 => x"78", + 4094 => x"06", + 4095 => x"80", + 4096 => x"39", + 4097 => x"52", + 4098 => x"da", + 4099 => x"c8", + 4100 => x"c8", + 4101 => x"82", + 4102 => x"07", + 4103 => x"30", + 4104 => x"9f", + 4105 => x"52", + 4106 => x"56", + 4107 => x"8f", + 4108 => x"7a", + 4109 => x"f9", + 4110 => x"93", + 4111 => x"75", + 4112 => x"8c", + 4113 => x"19", + 4114 => x"54", + 4115 => x"74", + 4116 => x"90", + 4117 => x"05", + 4118 => x"84", + 4119 => x"07", + 4120 => x"1a", + 4121 => x"ff", + 4122 => x"2e", + 4123 => x"39", + 4124 => x"39", + 4125 => x"39", + 4126 => x"55", + 4127 => x"c8", + 4128 => x"0d", + 4129 => x"0d", + 4130 => x"57", + 4131 => x"81", + 4132 => x"c8", + 4133 => x"38", + 4134 => x"51", + 4135 => x"82", + 4136 => x"82", + 4137 => x"b0", + 4138 => x"84", + 4139 => x"52", + 4140 => x"52", + 4141 => x"3f", + 4142 => x"58", + 4143 => x"39", + 4144 => x"8a", + 4145 => x"75", + 4146 => x"38", + 4147 => x"1a", + 4148 => x"81", + 4149 => x"ee", + 4150 => x"93", + 4151 => x"2e", + 4152 => x"0b", + 4153 => x"56", + 4154 => x"2e", + 4155 => x"58", + 4156 => x"82", + 4157 => x"8b", + 4158 => x"f8", + 4159 => x"7c", + 4160 => x"56", + 4161 => x"80", + 4162 => x"38", + 4163 => x"53", + 4164 => x"86", + 4165 => x"81", + 4166 => x"90", + 4167 => x"17", + 4168 => x"aa", + 4169 => x"53", + 4170 => x"85", + 4171 => x"08", + 4172 => x"38", + 4173 => x"53", + 4174 => x"17", + 4175 => x"72", + 4176 => x"83", + 4177 => x"08", + 4178 => x"80", + 4179 => x"16", + 4180 => x"2b", + 4181 => x"75", + 4182 => x"73", + 4183 => x"f5", + 4184 => x"93", + 4185 => x"82", + 4186 => x"ff", + 4187 => x"81", + 4188 => x"c8", + 4189 => x"38", + 4190 => x"82", + 4191 => x"26", + 4192 => x"58", + 4193 => x"74", + 4194 => x"74", + 4195 => x"38", + 4196 => x"51", + 4197 => x"82", + 4198 => x"98", + 4199 => x"94", + 4200 => x"58", + 4201 => x"80", + 4202 => x"85", + 4203 => x"97", + 4204 => x"2a", + 4205 => x"05", + 4206 => x"74", + 4207 => x"16", + 4208 => x"18", + 4209 => x"77", + 4210 => x"0c", + 4211 => x"04", + 4212 => x"79", + 4213 => x"90", + 4214 => x"05", + 4215 => x"55", + 4216 => x"76", + 4217 => x"80", + 4218 => x"0c", + 4219 => x"15", + 4220 => x"81", + 4221 => x"83", + 4222 => x"73", + 4223 => x"98", + 4224 => x"05", + 4225 => x"94", + 4226 => x"38", + 4227 => x"88", + 4228 => x"53", + 4229 => x"81", + 4230 => x"98", + 4231 => x"53", + 4232 => x"8a", + 4233 => x"11", + 4234 => x"06", + 4235 => x"81", + 4236 => x"15", + 4237 => x"51", + 4238 => x"82", + 4239 => x"54", + 4240 => x"0b", + 4241 => x"08", + 4242 => x"38", + 4243 => x"93", + 4244 => x"2e", + 4245 => x"98", + 4246 => x"93", + 4247 => x"80", + 4248 => x"8a", + 4249 => x"16", + 4250 => x"80", + 4251 => x"15", + 4252 => x"51", + 4253 => x"82", + 4254 => x"54", + 4255 => x"93", + 4256 => x"2e", + 4257 => x"82", + 4258 => x"c8", + 4259 => x"bf", + 4260 => x"82", + 4261 => x"ff", + 4262 => x"82", + 4263 => x"52", + 4264 => x"e1", + 4265 => x"82", + 4266 => x"a3", + 4267 => x"16", + 4268 => x"76", + 4269 => x"3f", + 4270 => x"08", + 4271 => x"75", + 4272 => x"75", + 4273 => x"17", + 4274 => x"16", + 4275 => x"72", + 4276 => x"0c", + 4277 => x"04", + 4278 => x"7a", + 4279 => x"5a", + 4280 => x"52", + 4281 => x"93", + 4282 => x"c8", + 4283 => x"93", + 4284 => x"e1", + 4285 => x"c8", + 4286 => x"16", + 4287 => x"51", + 4288 => x"82", + 4289 => x"54", + 4290 => x"08", + 4291 => x"82", + 4292 => x"9c", + 4293 => x"33", + 4294 => x"72", + 4295 => x"09", + 4296 => x"38", + 4297 => x"30", + 4298 => x"76", + 4299 => x"72", + 4300 => x"38", + 4301 => x"76", + 4302 => x"38", + 4303 => x"57", + 4304 => x"51", + 4305 => x"82", + 4306 => x"54", + 4307 => x"08", + 4308 => x"a6", + 4309 => x"2e", + 4310 => x"83", + 4311 => x"73", + 4312 => x"0c", + 4313 => x"04", + 4314 => x"76", + 4315 => x"54", + 4316 => x"82", + 4317 => x"83", + 4318 => x"76", + 4319 => x"53", + 4320 => x"2e", + 4321 => x"90", + 4322 => x"51", + 4323 => x"82", + 4324 => x"90", + 4325 => x"53", + 4326 => x"c8", + 4327 => x"0d", + 4328 => x"0d", + 4329 => x"83", + 4330 => x"54", + 4331 => x"55", + 4332 => x"3f", + 4333 => x"51", + 4334 => x"2e", + 4335 => x"8b", + 4336 => x"2a", + 4337 => x"51", + 4338 => x"86", + 4339 => x"f7", + 4340 => x"7d", + 4341 => x"76", + 4342 => x"98", + 4343 => x"2e", + 4344 => x"98", + 4345 => x"78", + 4346 => x"3f", + 4347 => x"08", + 4348 => x"c8", + 4349 => x"38", + 4350 => x"70", + 4351 => x"74", + 4352 => x"58", + 4353 => x"9c", + 4354 => x"11", + 4355 => x"06", + 4356 => x"06", + 4357 => x"53", + 4358 => x"34", + 4359 => x"32", + 4360 => x"ae", + 4361 => x"70", + 4362 => x"2a", + 4363 => x"51", + 4364 => x"2e", + 4365 => x"8f", + 4366 => x"80", + 4367 => x"54", + 4368 => x"2e", + 4369 => x"83", + 4370 => x"73", + 4371 => x"38", + 4372 => x"51", + 4373 => x"82", + 4374 => x"58", + 4375 => x"08", + 4376 => x"16", + 4377 => x"38", + 4378 => x"86", + 4379 => x"98", + 4380 => x"82", + 4381 => x"8b", + 4382 => x"f8", + 4383 => x"70", + 4384 => x"80", + 4385 => x"f8", + 4386 => x"93", + 4387 => x"82", + 4388 => x"80", + 4389 => x"39", + 4390 => x"e6", + 4391 => x"08", + 4392 => x"ec", + 4393 => x"93", + 4394 => x"82", + 4395 => x"80", + 4396 => x"16", + 4397 => x"51", + 4398 => x"2e", + 4399 => x"16", + 4400 => x"33", + 4401 => x"55", + 4402 => x"34", + 4403 => x"70", + 4404 => x"81", + 4405 => x"59", + 4406 => x"8b", + 4407 => x"52", + 4408 => x"85", + 4409 => x"c8", + 4410 => x"96", + 4411 => x"75", + 4412 => x"3f", + 4413 => x"08", + 4414 => x"c8", + 4415 => x"ff", + 4416 => x"54", + 4417 => x"c8", + 4418 => x"0d", + 4419 => x"0d", + 4420 => x"57", + 4421 => x"73", + 4422 => x"3f", + 4423 => x"08", + 4424 => x"c8", + 4425 => x"98", + 4426 => x"75", + 4427 => x"3f", + 4428 => x"08", + 4429 => x"c8", + 4430 => x"a0", + 4431 => x"c8", + 4432 => x"14", + 4433 => x"87", + 4434 => x"a0", + 4435 => x"14", + 4436 => x"d7", + 4437 => x"83", + 4438 => x"82", + 4439 => x"87", + 4440 => x"fc", + 4441 => x"70", + 4442 => x"08", + 4443 => x"56", + 4444 => x"3f", + 4445 => x"08", + 4446 => x"c8", + 4447 => x"9c", + 4448 => x"e5", + 4449 => x"0b", + 4450 => x"73", + 4451 => x"0c", + 4452 => x"04", + 4453 => x"78", + 4454 => x"80", + 4455 => x"34", + 4456 => x"80", + 4457 => x"38", + 4458 => x"55", + 4459 => x"14", + 4460 => x"16", + 4461 => x"72", + 4462 => x"38", + 4463 => x"09", + 4464 => x"38", + 4465 => x"73", + 4466 => x"81", + 4467 => x"75", + 4468 => x"52", + 4469 => x"13", + 4470 => x"55", + 4471 => x"05", + 4472 => x"13", + 4473 => x"55", + 4474 => x"c0", + 4475 => x"88", + 4476 => x"0b", + 4477 => x"9c", + 4478 => x"8b", + 4479 => x"17", + 4480 => x"08", + 4481 => x"e6", + 4482 => x"93", + 4483 => x"0c", + 4484 => x"96", + 4485 => x"84", + 4486 => x"c8", + 4487 => x"23", + 4488 => x"98", + 4489 => x"f4", + 4490 => x"c8", + 4491 => x"23", + 4492 => x"04", + 4493 => x"7e", + 4494 => x"a0", + 4495 => x"5c", + 4496 => x"52", + 4497 => x"87", + 4498 => x"58", + 4499 => x"33", + 4500 => x"ae", + 4501 => x"06", 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x"81", + 4561 => x"58", + 4562 => x"ed", + 4563 => x"2b", + 4564 => x"25", + 4565 => x"80", + 4566 => x"fb", + 4567 => x"57", + 4568 => x"e5", + 4569 => x"93", + 4570 => x"2e", + 4571 => x"17", + 4572 => x"19", + 4573 => x"56", + 4574 => x"3f", + 4575 => x"08", + 4576 => x"38", + 4577 => x"73", + 4578 => x"38", + 4579 => x"f6", + 4580 => x"54", + 4581 => x"81", + 4582 => x"55", + 4583 => x"34", + 4584 => x"fe", + 4585 => x"52", + 4586 => x"51", + 4587 => x"82", + 4588 => x"80", + 4589 => x"9f", + 4590 => x"99", + 4591 => x"e0", + 4592 => x"ff", + 4593 => x"7a", + 4594 => x"74", + 4595 => x"58", + 4596 => x"76", + 4597 => x"86", + 4598 => x"2e", + 4599 => x"33", + 4600 => x"e5", + 4601 => x"06", + 4602 => x"7b", + 4603 => x"a0", + 4604 => x"38", + 4605 => x"54", + 4606 => x"54", + 4607 => x"54", + 4608 => x"34", + 4609 => x"82", + 4610 => x"8d", + 4611 => x"fa", + 4612 => x"70", + 4613 => x"80", + 4614 => x"51", + 4615 => x"af", + 4616 => x"81", + 4617 => x"70", + 4618 => x"54", + 4619 => x"2e", + 4620 => x"54", + 4621 => x"53", + 4622 => x"8c", + 4623 => x"08", + 4624 => x"b3", + 4625 => x"5a", + 4626 => x"33", + 4627 => x"72", + 4628 => x"81", + 4629 => x"81", + 4630 => x"70", + 4631 => x"54", + 4632 => x"2e", + 4633 => x"83", + 4634 => x"74", + 4635 => x"72", + 4636 => x"0b", + 4637 => x"79", + 4638 => x"53", + 4639 => x"9b", + 4640 => x"0b", + 4641 => x"80", + 4642 => x"f0", + 4643 => x"93", + 4644 => x"81", + 4645 => x"55", + 4646 => x"89", + 4647 => x"52", + 4648 => x"90", + 4649 => x"c8", + 4650 => x"93", + 4651 => x"8f", + 4652 => x"f7", + 4653 => x"93", + 4654 => x"17", + 4655 => x"82", + 4656 => x"80", + 4657 => x"38", + 4658 => x"08", + 4659 => x"81", + 4660 => x"38", + 4661 => x"70", + 4662 => x"53", + 4663 => x"9a", + 4664 => x"2a", + 4665 => x"51", + 4666 => x"2e", + 4667 => x"ff", + 4668 => x"17", + 4669 => x"80", + 4670 => x"82", + 4671 => x"06", + 4672 => x"bb", + 4673 => x"b7", + 4674 => x"2a", + 4675 => x"51", + 4676 => x"38", + 4677 => x"70", + 4678 => x"81", + 4679 => x"54", + 4680 => x"fe", + 4681 => x"16", + 4682 => x"06", + 4683 => x"52", + 4684 => x"b4", + 4685 => x"c8", + 4686 => x"0c", + 4687 => x"74", + 4688 => x"0c", + 4689 => x"04", + 4690 => x"7c", + 4691 => x"08", + 4692 => x"59", + 4693 => x"80", + 4694 => x"38", + 4695 => x"05", + 4696 => x"ba", + 4697 => x"72", + 4698 => x"9f", + 4699 => x"51", + 4700 => x"e8", + 4701 => x"2e", + 4702 => x"81", + 4703 => x"33", + 4704 => x"52", + 4705 => x"92", + 4706 => x"72", + 4707 => x"d0", + 4708 => x"51", + 4709 => x"80", + 4710 => x"0b", + 4711 => x"5c", + 4712 => x"10", + 4713 => x"7a", + 4714 => x"51", + 4715 => x"05", + 4716 => x"70", + 4717 => x"33", + 4718 => x"53", + 4719 => x"99", + 4720 => x"e0", + 4721 => x"ff", + 4722 => x"ff", + 4723 => x"70", + 4724 => x"38", + 4725 => x"81", + 4726 => x"51", + 4727 => x"74", + 4728 => x"70", + 4729 => x"25", + 4730 => x"06", + 4731 => x"51", + 4732 => x"38", + 4733 => x"78", + 4734 => x"70", + 4735 => x"2a", + 4736 => x"07", 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x"7f", + 4796 => x"3f", + 4797 => x"08", + 4798 => x"80", + 4799 => x"c8", + 4800 => x"9e", + 4801 => x"c8", + 4802 => x"82", + 4803 => x"70", + 4804 => x"8c", + 4805 => x"2e", + 4806 => x"74", + 4807 => x"81", + 4808 => x"33", + 4809 => x"80", + 4810 => x"81", + 4811 => x"d6", + 4812 => x"93", + 4813 => x"ff", + 4814 => x"06", + 4815 => x"99", + 4816 => x"2e", + 4817 => x"82", + 4818 => x"06", + 4819 => x"56", + 4820 => x"38", + 4821 => x"ca", + 4822 => x"34", + 4823 => x"34", + 4824 => x"15", + 4825 => x"8d", + 4826 => x"c8", + 4827 => x"06", + 4828 => x"54", + 4829 => x"72", + 4830 => x"76", + 4831 => x"38", + 4832 => x"70", + 4833 => x"53", + 4834 => x"86", + 4835 => x"70", + 4836 => x"5a", + 4837 => x"82", + 4838 => x"81", + 4839 => x"76", + 4840 => x"81", + 4841 => x"38", + 4842 => x"90", + 4843 => x"3d", + 4844 => x"05", + 4845 => x"f6", + 4846 => x"59", + 4847 => x"72", + 4848 => x"38", + 4849 => x"51", + 4850 => x"82", + 4851 => x"57", + 4852 => x"81", + 4853 => x"74", + 4854 => x"80", + 4855 => x"74", + 4856 => x"f0", + 4857 => x"53", + 4858 => x"80", + 4859 => x"79", + 4860 => x"fc", + 4861 => x"93", + 4862 => x"ff", + 4863 => x"77", + 4864 => x"81", + 4865 => x"74", + 4866 => x"81", + 4867 => x"2e", + 4868 => x"8d", + 4869 => x"26", + 4870 => x"bf", + 4871 => x"fc", + 4872 => x"c8", + 4873 => x"ff", + 4874 => x"56", + 4875 => x"2e", + 4876 => x"84", + 4877 => x"ca", + 4878 => x"e0", + 4879 => x"c8", + 4880 => x"ff", + 4881 => x"8d", + 4882 => x"15", + 4883 => x"3f", + 4884 => x"08", + 4885 => x"16", + 4886 => x"15", + 4887 => x"34", + 4888 => x"33", + 4889 => x"8d", + 4890 => x"26", + 4891 => x"82", + 4892 => x"71", + 4893 => x"17", + 4894 => x"53", + 4895 => x"23", + 4896 => x"ff", + 4897 => x"80", + 4898 => x"ff", + 4899 => x"53", + 4900 => x"86", + 4901 => x"84", + 4902 => x"c5", + 4903 => x"fc", + 4904 => x"c8", + 4905 => x"23", + 4906 => x"08", + 4907 => x"06", + 4908 => x"8d", + 4909 => x"ea", + 4910 => x"15", + 4911 => x"3f", + 4912 => x"08", + 4913 => x"06", + 4914 => x"38", + 4915 => x"51", + 4916 => x"82", + 4917 => x"53", + 4918 => x"51", + 4919 => x"82", + 4920 => x"83", + 4921 => x"59", + 4922 => x"80", + 4923 => x"38", + 4924 => x"74", + 4925 => x"2a", + 4926 => x"8d", + 4927 => x"26", + 4928 => x"8a", + 4929 => x"72", + 4930 => x"ff", + 4931 => x"82", + 4932 => x"53", + 4933 => x"93", + 4934 => x"2e", + 4935 => x"80", + 4936 => x"c8", + 4937 => x"ff", + 4938 => x"83", + 4939 => x"72", + 4940 => x"26", + 4941 => x"57", + 4942 => x"26", + 4943 => x"57", + 4944 => x"80", + 4945 => x"38", + 4946 => x"16", + 4947 => x"16", + 4948 => x"a4", + 4949 => x"1a", + 4950 => x"76", + 4951 => x"81", + 4952 => x"80", + 4953 => x"d7", + 4954 => x"93", + 4955 => x"ff", + 4956 => x"8d", + 4957 => x"aa", + 4958 => x"22", + 4959 => x"72", + 4960 => x"80", + 4961 => x"d7", + 4962 => x"93", + 4963 => x"16", + 4964 => x"08", + 4965 => x"b6", + 4966 => x"22", + 4967 => x"72", + 4968 => x"fe", + 4969 => x"08", + 4970 => x"0c", + 4971 => x"09", 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x"80", + 5031 => x"0c", + 5032 => x"82", + 5033 => x"8f", + 5034 => x"fb", + 5035 => x"54", + 5036 => x"80", + 5037 => x"73", + 5038 => x"af", + 5039 => x"70", + 5040 => x"71", + 5041 => x"38", + 5042 => x"86", + 5043 => x"52", + 5044 => x"09", + 5045 => x"38", + 5046 => x"51", + 5047 => x"82", + 5048 => x"81", + 5049 => x"83", + 5050 => x"80", + 5051 => x"2e", + 5052 => x"84", + 5053 => x"53", + 5054 => x"0c", + 5055 => x"93", + 5056 => x"3d", + 5057 => x"3d", + 5058 => x"05", + 5059 => x"89", + 5060 => x"52", + 5061 => x"3f", + 5062 => x"08", + 5063 => x"80", + 5064 => x"c8", + 5065 => x"c4", + 5066 => x"c8", + 5067 => x"82", + 5068 => x"70", + 5069 => x"73", + 5070 => x"38", + 5071 => x"78", + 5072 => x"38", + 5073 => x"74", + 5074 => x"10", + 5075 => x"05", + 5076 => x"54", + 5077 => x"80", + 5078 => x"80", + 5079 => x"70", + 5080 => x"51", + 5081 => x"82", + 5082 => x"54", + 5083 => x"c8", + 5084 => x"0d", + 5085 => x"0d", + 5086 => x"05", + 5087 => x"33", + 5088 => x"55", + 5089 => x"84", + 5090 => x"bf", + 5091 => x"98", + 5092 => x"53", + 5093 => x"05", + 5094 => x"c3", + 5095 => x"c8", + 5096 => x"93", + 5097 => x"c5", + 5098 => x"68", + 5099 => x"d4", + 5100 => x"db", + 5101 => x"c8", + 5102 => x"93", + 5103 => x"38", + 5104 => x"05", + 5105 => x"2b", + 5106 => x"80", + 5107 => x"86", + 5108 => x"06", + 5109 => x"2e", + 5110 => x"75", + 5111 => x"38", + 5112 => x"09", + 5113 => x"38", + 5114 => x"05", + 5115 => x"3f", + 5116 => x"08", + 5117 => x"07", + 5118 => x"02", + 5119 => x"91", + 5120 => x"80", + 5121 => x"87", + 5122 => x"76", + 5123 => x"81", + 5124 => x"74", + 5125 => x"38", + 5126 => x"83", + 5127 => x"83", + 5128 => x"06", + 5129 => x"80", + 5130 => x"38", + 5131 => x"51", + 5132 => x"82", + 5133 => x"59", + 5134 => x"0a", + 5135 => x"05", + 5136 => x"3f", + 5137 => x"0b", + 5138 => x"75", + 5139 => x"7a", + 5140 => x"3f", + 5141 => x"9c", + 5142 => x"a0", + 5143 => x"81", + 5144 => x"34", + 5145 => x"80", + 5146 => x"b0", + 5147 => x"55", + 5148 => x"3d", + 5149 => x"51", + 5150 => x"3f", + 5151 => x"08", + 5152 => x"c8", + 5153 => x"38", + 5154 => x"51", + 5155 => x"82", + 5156 => x"7b", + 5157 => x"12", + 5158 => x"b6", + 5159 => x"cd", + 5160 => x"05", + 5161 => x"2a", + 5162 => x"51", + 5163 => x"80", + 5164 => x"84", + 5165 => x"76", + 5166 => x"81", + 5167 => x"74", + 5168 => x"38", + 5169 => x"33", + 5170 => x"74", + 5171 => x"38", + 5172 => x"82", + 5173 => x"83", + 5174 => x"06", + 5175 => x"80", + 5176 => x"76", + 5177 => x"57", + 5178 => x"08", + 5179 => x"63", + 5180 => x"55", + 5181 => x"38", + 5182 => x"51", + 5183 => x"82", + 5184 => x"88", + 5185 => x"9c", + 5186 => x"a9", + 5187 => x"c8", + 5188 => x"0c", + 5189 => x"86", + 5190 => x"19", + 5191 => x"19", + 5192 => x"19", + 5193 => x"19", + 5194 => x"19", + 5195 => x"53", + 5196 => x"18", + 5197 => x"3f", + 5198 => x"70", + 5199 => x"55", + 5200 => x"81", + 5201 => x"18", + 5202 => x"81", + 5203 => x"18", + 5204 => x"0c", + 5205 => x"22", + 5206 => x"88", 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x"0b", + 5266 => x"81", + 5267 => x"39", + 5268 => x"18", + 5269 => x"83", + 5270 => x"0b", + 5271 => x"81", + 5272 => x"39", + 5273 => x"18", + 5274 => x"82", + 5275 => x"0b", + 5276 => x"81", + 5277 => x"39", + 5278 => x"94", + 5279 => x"55", + 5280 => x"83", + 5281 => x"78", + 5282 => x"cb", + 5283 => x"08", + 5284 => x"06", + 5285 => x"82", + 5286 => x"8a", + 5287 => x"05", + 5288 => x"06", + 5289 => x"a8", + 5290 => x"38", + 5291 => x"55", + 5292 => x"17", + 5293 => x"51", + 5294 => x"82", + 5295 => x"55", + 5296 => x"fe", + 5297 => x"ff", + 5298 => x"38", + 5299 => x"0c", + 5300 => x"52", + 5301 => x"e8", + 5302 => x"c8", + 5303 => x"fe", + 5304 => x"93", + 5305 => x"79", + 5306 => x"58", + 5307 => x"80", + 5308 => x"1b", + 5309 => x"22", + 5310 => x"74", + 5311 => x"38", + 5312 => x"5a", + 5313 => x"53", + 5314 => x"81", + 5315 => x"55", + 5316 => x"82", + 5317 => x"fe", + 5318 => x"17", + 5319 => x"2b", + 5320 => x"80", + 5321 => x"9c", + 5322 => x"31", + 5323 => x"27", + 5324 => x"80", + 5325 => x"52", + 5326 => x"29", + 5327 => x"eb", + 5328 => x"2b", + 5329 => x"39", + 5330 => x"78", + 5331 => x"38", + 5332 => x"70", + 5333 => x"56", + 5334 => x"a5", + 5335 => x"9c", + 5336 => x"a8", + 5337 => x"81", + 5338 => x"55", + 5339 => x"82", + 5340 => x"fd", + 5341 => x"17", + 5342 => x"06", + 5343 => x"18", + 5344 => x"77", + 5345 => x"52", + 5346 => x"33", + 5347 => x"f1", + 5348 => x"c8", + 5349 => x"38", + 5350 => x"0c", + 5351 => x"83", + 5352 => x"80", + 5353 => x"55", + 5354 => x"83", + 5355 => x"75", + 5356 => x"08", + 5357 => x"17", + 5358 => x"7b", + 5359 => x"3f", + 5360 => x"7d", + 5361 => x"0c", + 5362 => x"19", + 5363 => x"1a", + 5364 => x"78", + 5365 => x"80", + 5366 => x"93", + 5367 => x"3d", + 5368 => x"3d", + 5369 => x"64", + 5370 => x"5a", + 5371 => x"0c", + 5372 => x"05", + 5373 => x"f5", + 5374 => x"93", + 5375 => x"82", + 5376 => x"8a", + 5377 => x"33", + 5378 => x"2e", + 5379 => x"56", + 5380 => x"90", + 5381 => x"81", + 5382 => x"06", + 5383 => x"87", + 5384 => x"2e", + 5385 => x"bd", + 5386 => x"91", + 5387 => x"56", + 5388 => x"81", + 5389 => x"34", + 5390 => x"d8", + 5391 => x"91", + 5392 => x"56", + 5393 => x"82", + 5394 => x"34", + 5395 => x"c4", + 5396 => x"91", + 5397 => x"56", + 5398 => x"81", + 5399 => x"34", + 5400 => x"b0", + 5401 => x"08", + 5402 => x"94", + 5403 => x"86", + 5404 => x"08", + 5405 => x"80", + 5406 => x"38", + 5407 => x"70", + 5408 => x"56", + 5409 => x"a8", + 5410 => x"11", + 5411 => x"77", + 5412 => x"5c", + 5413 => x"c6", + 5414 => x"38", + 5415 => x"55", + 5416 => x"7a", + 5417 => x"d4", + 5418 => x"93", + 5419 => x"8f", + 5420 => x"08", + 5421 => x"d4", + 5422 => x"93", + 5423 => x"74", + 5424 => x"c3", + 5425 => x"2e", + 5426 => x"74", + 5427 => x"e3", + 5428 => x"18", + 5429 => x"08", + 5430 => x"88", + 5431 => x"17", + 5432 => x"2b", + 5433 => x"80", + 5434 => x"81", + 5435 => x"08", + 5436 => x"52", + 5437 => x"33", + 5438 => x"de", + 5439 => x"c8", + 5440 => x"38", + 5441 => x"80", + 5442 => x"74", + 5443 => x"98", + 5444 => x"7d", + 5445 => x"3f", + 5446 => x"08", + 5447 => x"a7", + 5448 => x"c8", + 5449 => x"89", + 5450 => x"79", + 5451 => x"d5", + 5452 => x"7e", + 5453 => x"51", + 5454 => x"76", + 5455 => x"74", + 5456 => x"79", + 5457 => x"7b", + 5458 => x"11", + 5459 => x"c5", + 5460 => x"93", + 5461 => x"f9", + 5462 => x"08", + 5463 => x"74", + 5464 => x"38", + 5465 => x"74", + 5466 => x"1c", + 5467 => x"51", + 5468 => x"90", + 5469 => x"ff", + 5470 => x"90", + 5471 => x"89", + 5472 => x"db", + 5473 => x"08", + 5474 => x"38", + 5475 => x"8c", + 5476 => x"98", + 5477 => x"77", + 5478 => x"52", + 5479 => x"33", + 5480 => x"dd", + 5481 => x"c8", + 5482 => x"38", + 5483 => x"0c", + 5484 => x"83", + 5485 => x"80", + 5486 => x"55", + 5487 => x"83", + 5488 => x"75", + 5489 => x"94", + 5490 => x"ff", + 5491 => x"05", + 5492 => x"3f", + 5493 => x"ff", + 5494 => x"74", + 5495 => x"78", + 5496 => x"08", + 5497 => x"76", + 5498 => x"08", + 5499 => x"1b", + 5500 => x"08", + 5501 => x"59", + 5502 => x"83", + 5503 => x"74", + 5504 => x"78", + 5505 => x"90", + 5506 => x"c0", + 5507 => x"90", + 5508 => x"56", + 5509 => x"c8", + 5510 => x"0d", + 5511 => x"0d", + 5512 => x"fc", + 5513 => x"52", + 5514 => x"3f", + 5515 => x"08", + 5516 => x"c8", + 5517 => x"38", + 5518 => x"70", + 5519 => x"81", + 5520 => x"56", + 5521 => x"81", + 5522 => x"98", + 5523 => x"80", + 5524 => x"81", + 5525 => x"08", + 5526 => x"52", + 5527 => x"33", + 5528 => x"f6", + 5529 => x"82", + 5530 => x"80", + 5531 => x"18", + 5532 => x"06", + 5533 => x"19", + 5534 => x"08", + 5535 => x"c8", + 5536 => x"93", + 5537 => x"82", + 5538 => x"80", + 5539 => x"18", + 5540 => x"33", + 5541 => x"56", + 5542 => x"34", + 5543 => x"53", + 5544 => x"08", + 5545 => x"3f", + 5546 => x"52", + 5547 => x"c5", + 5548 => x"88", + 5549 => x"96", + 5550 => x"c0", + 5551 => x"92", + 5552 => x"9a", + 5553 => x"81", + 5554 => x"34", + 5555 => x"c1", + 5556 => x"c8", + 5557 => x"33", + 5558 => x"56", + 5559 => x"19", + 5560 => x"74", + 5561 => x"0c", + 5562 => x"04", + 5563 => x"76", + 5564 => x"fe", + 5565 => x"93", + 5566 => x"82", + 5567 => x"9c", + 5568 => x"fc", + 5569 => x"51", + 5570 => x"82", + 5571 => x"53", + 5572 => x"08", + 5573 => x"93", + 5574 => x"0c", + 5575 => x"c8", + 5576 => x"0d", + 5577 => x"0d", + 5578 => x"e4", + 5579 => x"53", + 5580 => x"93", + 5581 => x"8b", + 5582 => x"c8", + 5583 => x"f8", + 5584 => x"72", + 5585 => x"0c", + 5586 => x"04", + 5587 => x"80", + 5588 => x"d0", + 5589 => x"3d", + 5590 => x"3f", + 5591 => x"08", + 5592 => x"c8", + 5593 => x"38", + 5594 => x"52", + 5595 => x"05", + 5596 => x"3f", + 5597 => x"08", + 5598 => x"c8", + 5599 => x"02", + 5600 => x"33", + 5601 => x"55", + 5602 => x"25", + 5603 => x"7a", + 5604 => x"54", + 5605 => x"a2", + 5606 => x"84", + 5607 => x"06", + 5608 => x"73", + 5609 => x"38", + 5610 => x"70", + 5611 => x"b8", + 5612 => x"c8", + 5613 => x"0c", + 5614 => x"55", + 5615 => x"09", + 5616 => x"38", + 5617 => x"82", + 5618 => x"93", + 5619 => x"e1", + 5620 => x"3d", + 5621 => x"08", + 5622 => x"7a", + 5623 => x"a1", + 5624 => x"05", + 5625 => x"51", + 5626 => x"82", + 5627 => x"57", + 5628 => x"08", + 5629 => x"7e", + 5630 => x"94", + 5631 => x"55", + 5632 => x"74", + 5633 => x"f9", + 5634 => x"70", + 5635 => x"5e", + 5636 => x"7a", + 5637 => x"3f", + 5638 => x"08", + 5639 => x"c8", + 5640 => x"38", + 5641 => x"51", + 5642 => x"82", + 5643 => x"57", + 5644 => x"08", + 5645 => x"6c", + 5646 => x"d6", + 5647 => x"93", + 5648 => x"76", + 5649 => x"d1", + 5650 => x"93", + 5651 => x"82", + 5652 => x"81", + 5653 => x"54", + 5654 => x"51", + 5655 => x"82", + 5656 => x"57", + 5657 => x"08", + 5658 => x"52", + 5659 => x"f8", + 5660 => x"c8", + 5661 => x"95", + 5662 => x"73", + 5663 => x"3f", + 5664 => x"08", + 5665 => x"c8", + 5666 => x"cc", + 5667 => x"2e", + 5668 => x"83", + 5669 => x"76", + 5670 => x"a1", + 5671 => x"11", + 5672 => x"51", + 5673 => x"76", + 5674 => x"79", + 5675 => x"33", + 5676 => x"55", + 5677 => x"2e", + 5678 => x"16", + 5679 => x"11", + 5680 => x"56", + 5681 => x"81", + 5682 => x"74", + 5683 => x"91", + 5684 => x"75", + 5685 => x"38", + 5686 => x"19", + 5687 => x"11", + 5688 => x"1b", + 5689 => x"59", + 5690 => x"75", + 5691 => x"38", + 5692 => x"3d", + 5693 => x"59", + 5694 => x"67", + 5695 => x"91", + 5696 => x"85", + 5697 => x"2e", + 5698 => x"8c", + 5699 => x"a3", + 5700 => x"55", + 5701 => x"34", + 5702 => x"93", + 5703 => x"10", + 5704 => x"e8", + 5705 => x"70", + 5706 => x"57", + 5707 => x"73", + 5708 => x"38", + 5709 => x"16", + 5710 => x"55", + 5711 => x"38", + 5712 => x"73", + 5713 => x"38", + 5714 => x"76", + 5715 => x"77", + 5716 => x"33", + 5717 => x"05", + 5718 => x"18", + 5719 => x"26", + 5720 => x"7a", + 5721 => x"5c", + 5722 => x"58", + 5723 => x"91", + 5724 => x"38", + 5725 => x"19", + 5726 => x"54", + 5727 => x"70", + 5728 => x"34", + 5729 => x"ec", + 5730 => x"34", + 5731 => x"c8", + 5732 => x"0d", + 5733 => x"0d", + 5734 => x"3d", + 5735 => x"71", + 5736 => x"ea", + 5737 => x"93", + 5738 => x"82", + 5739 => x"8a", + 5740 => x"33", + 5741 => x"2e", + 5742 => x"55", + 5743 => x"8c", + 5744 => x"27", + 5745 => x"17", + 5746 => x"2a", + 5747 => x"51", + 5748 => x"85", + 5749 => x"08", + 5750 => x"08", + 5751 => x"94", + 5752 => x"77", + 5753 => x"b3", + 5754 => x"11", + 5755 => x"2b", + 5756 => x"75", + 5757 => x"38", + 5758 => x"18", + 5759 => x"b9", + 5760 => x"c8", + 5761 => x"7a", + 5762 => x"57", + 5763 => x"a9", + 5764 => x"c8", + 5765 => x"95", + 5766 => x"76", + 5767 => x"0c", + 5768 => x"08", + 5769 => x"08", + 5770 => x"c9", + 5771 => x"08", + 5772 => x"38", + 5773 => x"51", + 5774 => x"82", + 5775 => x"56", + 5776 => x"08", + 5777 => x"81", + 5778 => x"82", + 5779 => x"34", + 5780 => x"e3", + 5781 => x"c8", + 5782 => x"09", + 5783 => x"38", + 5784 => x"18", + 5785 => x"82", + 5786 => x"93", + 5787 => x"18", + 5788 => x"18", + 5789 => x"2e", + 5790 => x"78", + 5791 => x"ea", + 5792 => x"31", + 5793 => x"1a", + 5794 => x"90", + 5795 => x"81", + 5796 => x"06", + 5797 => x"58", + 5798 => x"9a", + 5799 => x"76", + 5800 => x"3f", + 5801 => x"08", + 5802 => x"c8", + 5803 => x"82", + 5804 => x"58", + 5805 => x"52", + 5806 => x"ae", + 5807 => x"c8", + 5808 => x"ff", + 5809 => x"38", + 5810 => x"8a", + 5811 => x"98", + 5812 => x"26", + 5813 => x"0b", + 5814 => x"82", + 5815 => x"39", + 5816 => x"0c", + 5817 => x"ff", + 5818 => x"17", + 5819 => x"18", + 5820 => x"ff", + 5821 => x"80", + 5822 => x"75", + 5823 => x"c1", + 5824 => x"93", + 5825 => x"38", + 5826 => x"18", + 5827 => x"81", + 5828 => x"89", + 5829 => x"c8", + 5830 => x"8c", + 5831 => x"18", + 5832 => x"38", + 5833 => x"8c", + 5834 => x"17", + 5835 => x"07", + 5836 => x"18", + 5837 => x"08", + 5838 => x"55", + 5839 => x"80", + 5840 => x"17", + 5841 => x"80", + 5842 => x"17", + 5843 => x"2b", + 5844 => x"80", + 5845 => x"81", + 5846 => x"08", + 5847 => x"52", + 5848 => x"33", + 5849 => x"b8", + 5850 => x"93", + 5851 => x"2e", + 5852 => x"0b", + 5853 => x"81", + 5854 => x"90", + 5855 => x"ff", + 5856 => x"90", + 5857 => x"54", + 5858 => x"17", + 5859 => x"11", + 5860 => x"ff", + 5861 => x"82", + 5862 => x"80", + 5863 => x"81", + 5864 => x"34", + 5865 => x"39", + 5866 => x"18", + 5867 => x"87", + 5868 => x"18", + 5869 => x"74", + 5870 => x"0c", + 5871 => x"04", + 5872 => x"79", + 5873 => x"75", + 5874 => x"8f", + 5875 => x"89", + 5876 => x"52", + 5877 => x"05", + 5878 => x"3f", + 5879 => x"08", + 5880 => x"c8", + 5881 => x"38", + 5882 => x"7a", + 5883 => x"d8", + 5884 => x"93", + 5885 => x"82", + 5886 => x"80", + 5887 => x"16", + 5888 => x"2b", + 5889 => x"74", + 5890 => x"86", + 5891 => x"84", + 5892 => x"06", + 5893 => x"73", + 5894 => x"38", + 5895 => x"52", + 5896 => x"c4", + 5897 => x"c8", + 5898 => x"0c", + 5899 => x"55", + 5900 => x"77", + 5901 => x"22", + 5902 => x"74", + 5903 => x"c9", + 5904 => x"93", + 5905 => x"74", + 5906 => x"81", + 5907 => x"85", + 5908 => x"2e", + 5909 => x"76", + 5910 => x"73", + 5911 => x"0c", + 5912 => x"04", + 5913 => x"76", + 5914 => x"05", + 5915 => x"54", + 5916 => x"82", + 5917 => x"53", + 5918 => x"08", + 5919 => x"93", + 5920 => x"0c", + 5921 => x"c8", + 5922 => x"0d", + 5923 => x"0d", + 5924 => x"3d", + 5925 => x"71", + 5926 => x"e4", + 5927 => x"93", + 5928 => x"82", + 5929 => x"80", + 5930 => x"92", + 5931 => x"c8", + 5932 => x"51", + 5933 => x"82", + 5934 => x"53", + 5935 => x"52", + 5936 => x"8b", + 5937 => x"c8", + 5938 => x"93", + 5939 => x"2e", + 5940 => x"83", + 5941 => x"72", + 5942 => x"52", + 5943 => x"b4", + 5944 => x"73", + 5945 => x"3f", + 5946 => x"08", + 5947 => x"c8", + 5948 => x"09", + 5949 => x"38", + 5950 => x"82", + 5951 => x"87", + 5952 => x"ef", + 5953 => x"56", + 5954 => x"3d", + 5955 => x"3d", + 5956 => x"cb", + 5957 => x"c8", + 5958 => x"93", + 5959 => x"38", + 5960 => x"51", + 5961 => x"82", + 5962 => x"55", + 5963 => x"08", + 5964 => x"80", + 5965 => x"70", + 5966 => x"57", + 5967 => x"85", + 5968 => x"90", + 5969 => x"2e", + 5970 => x"52", + 5971 => x"05", + 5972 => x"3f", + 5973 => x"c8", + 5974 => x"0d", + 5975 => x"0d", + 5976 => x"5a", + 5977 => x"3d", + 5978 => x"91", + 5979 => x"ef", + 5980 => x"c8", + 5981 => x"93", + 5982 => x"84", + 5983 => x"0c", + 5984 => x"11", + 5985 => x"55", + 5986 => x"08", + 5987 => x"38", + 5988 => x"7a", + 5989 => x"39", + 5990 => x"cf", + 5991 => x"81", + 5992 => x"7b", + 5993 => x"56", + 5994 => x"2e", + 5995 => x"80", + 5996 => x"75", + 5997 => x"52", + 5998 => x"05", + 5999 => x"aa", + 6000 => x"c8", + 6001 => x"d0", + 6002 => x"c8", + 6003 => x"cd", + 6004 => x"c8", + 6005 => x"82", + 6006 => x"07", + 6007 => x"05", + 6008 => x"53", + 6009 => x"98", + 6010 => x"26", + 6011 => x"fb", + 6012 => x"11", + 6013 => x"08", + 6014 => x"80", + 6015 => x"38", + 6016 => x"18", + 6017 => x"ff", + 6018 => x"82", + 6019 => x"59", + 6020 => x"08", + 6021 => x"7a", + 6022 => x"54", + 6023 => x"09", + 6024 => x"38", + 6025 => x"05", + 6026 => x"f0", + 6027 => x"c8", + 6028 => x"ff", + 6029 => x"70", + 6030 => x"82", + 6031 => x"51", + 6032 => x"7a", + 6033 => x"51", + 6034 => x"3f", + 6035 => x"08", + 6036 => x"70", + 6037 => x"25", + 6038 => x"58", + 6039 => x"74", + 6040 => x"ff", + 6041 => x"75", + 6042 => x"76", + 6043 => x"77", + 6044 => x"54", + 6045 => x"33", + 6046 => x"55", + 6047 => x"34", + 6048 => x"c8", + 6049 => x"0d", + 6050 => x"0d", + 6051 => x"fc", + 6052 => x"52", + 6053 => x"3f", + 6054 => x"08", + 6055 => x"c8", + 6056 => x"91", + 6057 => x"76", + 6058 => x"38", + 6059 => x"dc", + 6060 => x"33", + 6061 => x"70", + 6062 => x"56", + 6063 => x"74", + 6064 => x"c8", + 6065 => x"08", + 6066 => x"27", + 6067 => x"94", + 6068 => x"38", + 6069 => x"18", + 6070 => x"51", + 6071 => x"3f", + 6072 => x"08", + 6073 => x"88", + 6074 => x"ca", + 6075 => x"08", + 6076 => x"ff", + 6077 => x"82", + 6078 => x"82", + 6079 => x"ff", + 6080 => x"70", + 6081 => x"25", + 6082 => x"56", + 6083 => x"08", + 6084 => x"81", + 6085 => x"82", + 6086 => x"38", + 6087 => x"98", + 6088 => x"92", + 6089 => x"08", + 6090 => x"77", + 6091 => x"fe", + 6092 => x"c8", + 6093 => x"18", + 6094 => x"0c", + 6095 => x"80", + 6096 => x"74", + 6097 => x"76", + 6098 => x"98", + 6099 => x"80", + 6100 => x"81", + 6101 => x"08", + 6102 => x"52", + 6103 => x"33", + 6104 => x"b0", + 6105 => x"93", + 6106 => x"2e", + 6107 => x"57", + 6108 => x"18", + 6109 => x"06", + 6110 => x"19", + 6111 => x"2e", + 6112 => x"91", + 6113 => x"56", + 6114 => x"56", + 6115 => x"c8", + 6116 => x"0d", + 6117 => x"0d", + 6118 => x"51", + 6119 => x"3f", + 6120 => x"3d", + 6121 => x"52", + 6122 => x"d6", + 6123 => x"93", + 6124 => x"82", + 6125 => x"82", + 6126 => x"fb", + 6127 => x"96", + 6128 => x"44", + 6129 => x"3d", + 6130 => x"d0", + 6131 => x"93", + 6132 => x"fb", + 6133 => x"ff", + 6134 => x"75", + 6135 => x"02", + 6136 => x"33", + 6137 => x"70", + 6138 => x"55", + 6139 => x"2e", + 6140 => x"56", + 6141 => x"38", + 6142 => x"51", + 6143 => x"3f", + 6144 => x"05", + 6145 => x"2b", + 6146 => x"80", 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x"b6", + 6206 => x"c8", + 6207 => x"8c", + 6208 => x"ff", + 6209 => x"82", + 6210 => x"56", + 6211 => x"51", + 6212 => x"3f", + 6213 => x"c8", + 6214 => x"0d", + 6215 => x"0d", + 6216 => x"3d", + 6217 => x"99", + 6218 => x"b3", + 6219 => x"c8", + 6220 => x"93", + 6221 => x"b5", + 6222 => x"68", + 6223 => x"d4", + 6224 => x"cb", + 6225 => x"c8", + 6226 => x"93", + 6227 => x"38", + 6228 => x"84", + 6229 => x"06", + 6230 => x"02", + 6231 => x"33", + 6232 => x"70", + 6233 => x"55", + 6234 => x"2e", + 6235 => x"55", + 6236 => x"09", + 6237 => x"f5", + 6238 => x"80", + 6239 => x"c4", + 6240 => x"ba", + 6241 => x"93", + 6242 => x"80", + 6243 => x"c8", + 6244 => x"09", + 6245 => x"38", + 6246 => x"81", + 6247 => x"06", + 6248 => x"55", + 6249 => x"09", + 6250 => x"38", + 6251 => x"88", + 6252 => x"74", + 6253 => x"75", + 6254 => x"ff", + 6255 => x"82", + 6256 => x"55", + 6257 => x"08", + 6258 => x"8b", + 6259 => x"b4", + 6260 => x"af", + 6261 => x"54", + 6262 => x"15", + 6263 => x"90", + 6264 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x"79", + 7146 => x"ae", + 7147 => x"82", + 7148 => x"a3", + 7149 => x"80", + 7150 => x"ff", + 7151 => x"81", + 7152 => x"c8", + 7153 => x"8d", + 7154 => x"8b", + 7155 => x"87", + 7156 => x"83", + 7157 => x"76", + 7158 => x"0c", + 7159 => x"04", + 7160 => x"73", + 7161 => x"26", + 7162 => x"71", + 7163 => x"f1", + 7164 => x"71", + 7165 => x"81", + 7166 => x"80", + 7167 => x"d4", + 7168 => x"84", + 7169 => x"9e", + 7170 => x"39", + 7171 => x"51", + 7172 => x"3f", + 7173 => x"82", + 7174 => x"ff", + 7175 => x"81", + 7176 => x"82", + 7177 => x"ff", + 7178 => x"a8", + 7179 => x"cc", + 7180 => x"f2", + 7181 => x"39", + 7182 => x"51", + 7183 => x"3f", + 7184 => x"82", + 7185 => x"fe", + 7186 => x"81", + 7187 => x"83", + 7188 => x"ff", + 7189 => x"fc", + 7190 => x"a0", + 7191 => x"c6", + 7192 => x"39", + 7193 => x"51", + 7194 => x"3f", + 7195 => x"82", + 7196 => x"fe", + 7197 => x"80", + 7198 => x"83", + 7199 => x"ff", + 7200 => x"d0", + 7201 => x"94", + 7202 => x"9a", + 7203 => x"39", + 7204 => x"51", + 7205 => x"3f", + 7206 => x"84", + 7207 => x"ff", + 7208 => x"39", + 7209 => x"51", + 7210 => x"3f", + 7211 => x"84", + 7212 => x"fe", + 7213 => x"39", + 7214 => x"51", + 7215 => x"3f", + 7216 => x"85", + 7217 => x"fe", + 7218 => x"39", + 7219 => x"51", + 7220 => x"3f", + 7221 => x"04", + 7222 => x"77", + 7223 => x"74", + 7224 => x"93", + 7225 => x"75", + 7226 => x"51", + 7227 => x"3f", + 7228 => x"08", + 7229 => x"87", + 7230 => x"51", + 7231 => x"3f", + 7232 => x"08", + 7233 => x"fe", + 7234 => x"82", + 7235 => x"55", + 7236 => x"53", + 7237 => x"85", + 7238 => x"84", + 7239 => x"3d", + 7240 => x"ec", + 7241 => x"97", + 7242 => x"99", + 7243 => x"88", + 7244 => x"05", + 7245 => x"30", + 7246 => x"80", + 7247 => x"75", + 7248 => x"59", + 7249 => x"58", + 7250 => x"81", + 7251 => x"53", + 7252 => x"96", + 7253 => x"05", + 7254 => x"99", + 7255 => x"c8", + 7256 => x"93", + 7257 => x"38", + 7258 => x"08", + 7259 => x"88", + 7260 => x"c8", + 7261 => x"96", + 7262 => x"11", + 7263 => x"80", + 7264 => x"fb", + 7265 => x"c0", + 7266 => x"93", + 7267 => x"82", + 7268 => x"8e", + 7269 => x"2e", + 7270 => x"19", + 7271 => x"59", + 7272 => x"96", + 7273 => x"05", + 7274 => x"3f", + 7275 => x"79", + 7276 => x"7b", + 7277 => x"2a", + 7278 => x"57", + 7279 => x"80", + 7280 => x"82", + 7281 => x"87", + 7282 => x"08", + 7283 => x"fe", + 7284 => x"55", + 7285 => x"c8", + 7286 => x"3d", + 7287 => x"3d", + 7288 => x"05", + 7289 => x"7d", + 7290 => x"53", + 7291 => x"51", + 7292 => x"82", + 7293 => x"a4", + 7294 => x"2e", + 7295 => x"81", + 7296 => x"98", + 7297 => x"60", + 7298 => x"c8", + 7299 => x"7e", + 7300 => x"82", + 7301 => x"59", + 7302 => x"04", + 7303 => x"c8", + 7304 => x"0d", + 7305 => x"0d", + 7306 => x"33", + 7307 => x"53", + 7308 => x"52", + 7309 => x"e8", + 7310 => x"e8", + 7311 => x"55", + 7312 => x"3f", + 7313 => x"54", + 7314 => x"53", + 7315 => x"52", + 7316 => x"51", + 7317 => x"3f", + 7318 => x"85", + 7319 => x"ff", + 7320 => x"0d", + 7321 => x"0d", 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x"52", + 7381 => x"95", + 7382 => x"fe", + 7383 => x"82", + 7384 => x"fe", + 7385 => x"80", + 7386 => x"8a", + 7387 => x"2a", + 7388 => x"51", + 7389 => x"2e", + 7390 => x"51", + 7391 => x"3f", + 7392 => x"51", + 7393 => x"3f", + 7394 => x"ec", + 7395 => x"f8", + 7396 => x"3d", + 7397 => x"3d", + 7398 => x"08", + 7399 => x"57", + 7400 => x"80", + 7401 => x"39", + 7402 => x"85", + 7403 => x"80", + 7404 => x"15", + 7405 => x"33", + 7406 => x"a0", + 7407 => x"81", + 7408 => x"70", + 7409 => x"06", + 7410 => x"e6", + 7411 => x"53", + 7412 => x"09", + 7413 => x"38", + 7414 => x"81", + 7415 => x"80", + 7416 => x"29", + 7417 => x"05", + 7418 => x"70", + 7419 => x"fe", + 7420 => x"82", + 7421 => x"8b", + 7422 => x"33", + 7423 => x"2e", + 7424 => x"81", + 7425 => x"ff", + 7426 => x"bb", + 7427 => x"38", + 7428 => x"82", + 7429 => x"88", + 7430 => x"ce", + 7431 => x"70", + 7432 => x"72", + 7433 => x"5e", + 7434 => x"81", + 7435 => x"ff", + 7436 => x"82", + 7437 => x"81", + 7438 => x"78", + 7439 => x"81", + 7440 => x"82", + 7441 => x"96", + 7442 => x"59", + 7443 => x"3f", + 7444 => x"52", + 7445 => x"51", + 7446 => x"3f", + 7447 => x"08", + 7448 => x"2e", + 7449 => x"88", + 7450 => x"fd", + 7451 => x"39", + 7452 => x"5c", + 7453 => x"51", + 7454 => x"3f", + 7455 => x"43", + 7456 => x"70", + 7457 => x"52", + 7458 => x"e4", + 7459 => x"52", + 7460 => x"fd", + 7461 => x"3d", + 7462 => x"51", + 7463 => x"82", + 7464 => x"90", + 7465 => x"2c", + 7466 => x"81", + 7467 => x"af", + 7468 => x"10", + 7469 => x"05", + 7470 => x"04", + 7471 => x"f4", + 7472 => x"f8", + 7473 => x"fe", + 7474 => x"93", + 7475 => x"38", + 7476 => x"51", + 7477 => x"3f", + 7478 => x"b4", + 7479 => x"11", + 7480 => x"05", + 7481 => x"c3", + 7482 => x"c8", + 7483 => x"88", + 7484 => x"25", + 7485 => x"40", + 7486 => x"33", + 7487 => x"c3", + 7488 => x"ff", + 7489 => x"82", + 7490 => x"81", + 7491 => x"78", + 7492 => x"88", + 7493 => x"f6", + 7494 => x"5d", + 7495 => x"82", + 7496 => x"fe", + 7497 => x"fe", + 7498 => x"3d", + 7499 => x"53", + 7500 => x"51", + 7501 => x"3f", + 7502 => x"08", + 7503 => x"b4", + 7504 => x"80", + 7505 => x"c3", + 7506 => x"ff", + 7507 => x"82", + 7508 => x"52", + 7509 => x"51", + 7510 => x"3f", + 7511 => x"b4", + 7512 => x"11", + 7513 => x"05", + 7514 => x"bf", + 7515 => x"c8", + 7516 => x"87", + 7517 => x"26", + 7518 => x"b4", + 7519 => x"11", + 7520 => x"05", + 7521 => x"a3", + 7522 => x"c8", + 7523 => x"82", + 7524 => x"40", + 7525 => x"89", + 7526 => x"3d", + 7527 => x"fe", + 7528 => x"02", + 7529 => x"53", + 7530 => x"84", + 7531 => x"a0", + 7532 => x"ff", + 7533 => x"82", + 7534 => x"80", + 7535 => x"82", + 7536 => x"51", + 7537 => x"fd", + 7538 => x"88", + 7539 => x"f4", + 7540 => x"5c", + 7541 => x"b4", + 7542 => x"05", + 7543 => x"a4", + 7544 => x"c8", + 7545 => x"fe", + 7546 => x"5b", + 7547 => x"3f", + 7548 => x"93", + 7549 => x"7a", + 7550 => x"3f", + 7551 => x"08", + 7552 => x"f0", + 7553 => x"c8", + 7554 => x"d4", + 7555 => x"39", + 7556 => x"f8", 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x"fe", + 7616 => x"fe", + 7617 => x"82", + 7618 => x"80", + 7619 => x"38", + 7620 => x"8a", + 7621 => x"f8", + 7622 => x"59", + 7623 => x"93", + 7624 => x"82", + 7625 => x"80", + 7626 => x"38", + 7627 => x"08", + 7628 => x"a8", + 7629 => x"e8", + 7630 => x"39", + 7631 => x"51", + 7632 => x"3f", + 7633 => x"3f", + 7634 => x"82", + 7635 => x"fe", + 7636 => x"80", + 7637 => x"39", + 7638 => x"3f", + 7639 => x"61", + 7640 => x"59", + 7641 => x"fa", + 7642 => x"7c", + 7643 => x"80", + 7644 => x"38", + 7645 => x"f8", + 7646 => x"e1", + 7647 => x"8a", + 7648 => x"93", + 7649 => x"82", + 7650 => x"80", + 7651 => x"fc", + 7652 => x"70", + 7653 => x"f7", + 7654 => x"8b", + 7655 => x"93", + 7656 => x"56", + 7657 => x"42", + 7658 => x"54", + 7659 => x"53", + 7660 => x"52", + 7661 => x"a6", + 7662 => x"c8", + 7663 => x"81", + 7664 => x"32", + 7665 => x"8a", + 7666 => x"2e", + 7667 => x"f9", + 7668 => x"8b", + 7669 => x"f6", + 7670 => x"98", + 7671 => x"0d", + 7672 => x"93", + 7673 => x"90", + 7674 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8673 => x"00", + 8674 => x"00", + 8675 => x"00", + 8676 => x"00", + 8677 => x"00", + 8678 => x"00", + 8679 => x"00", + 8680 => x"00", + 8681 => x"00", + 8682 => x"00", + 8683 => x"00", + 8684 => x"00", + 8685 => x"00", + 8686 => x"00", + 8687 => x"00", + 8688 => x"00", + 8689 => x"00", + 8690 => x"00", + 8691 => x"00", + 8692 => x"00", + 8693 => x"00", + 8694 => x"00", + 8695 => x"00", + 8696 => x"00", + 8697 => x"00", + 8698 => x"00", + 8699 => x"01", + 8700 => x"00", + 8701 => x"00", + 8702 => x"00", + 8703 => x"01", + 8704 => x"00", + 8705 => x"00", + 8706 => x"00", + 8707 => x"00", + 8708 => x"00", + 8709 => x"00", + 8710 => x"00", + 8711 => x"00", + 8712 => x"00", + 8713 => x"00", + 8714 => x"00", + 8715 => x"00", + 8716 => x"00", + 8717 => x"00", + 8718 => x"00", + 8719 => x"00", + 8720 => x"00", + 8721 => x"00", + 8722 => x"00", + 8723 => x"00", + 8724 => x"00", + 8725 => x"00", + 8726 => x"00", + 8727 => x"00", + 8728 => x"00", + 8729 => x"00", + 8730 => x"00", + 8731 => x"00", + 8732 => x"00", + 8733 => x"00", + 8734 => x"00", + 8735 => x"00", + 8736 => x"00", + 8737 => x"00", + 8738 => x"00", + 8739 => x"00", + 8740 => x"00", + 8741 => x"00", + 8742 => x"00", + 8743 => x"00", + 8744 => x"00", + 8745 => x"00", + 8746 => x"00", + 8747 => x"00", + 8748 => x"00", + 8749 => x"00", + 8750 => x"00", + 8751 => x"00", + 8752 => x"00", + 8753 => x"00", + 8754 => x"00", + 8755 => x"01", + 8756 => x"00", + 8757 => x"00", + 8758 => x"00", + 8759 => x"01", + 8760 => x"00", + 8761 => x"00", + 8762 => x"00", + 8763 => x"00", + 8764 => x"00", + 8765 => x"00", + 8766 => x"00", + 8767 => x"00", + 8768 => x"00", + 8769 => x"00", + 8770 => x"00", + 8771 => x"01", + 8772 => x"00", + 8773 => x"00", + 8774 => x"00", + 8775 => x"01", + 8776 => x"00", + 8777 => x"00", + 8778 => x"00", + 8779 => x"00", + 8780 => x"00", + 8781 => x"00", + 8782 => x"00", + 8783 => x"00", + 8784 => x"00", + 8785 => x"00", + 8786 => x"00", + 8787 => x"01", + 8788 => x"00", + 8789 => x"00", + 8790 => x"00", + 8791 => x"01", + 8792 => x"00", + 8793 => x"00", + 8794 => x"00", + 8795 => x"01", + 8796 => x"00", + 8797 => x"00", + 8798 => x"00", + 8799 => x"01", + 8800 => x"00", + 8801 => x"00", + 8802 => x"00", + 8803 => x"00", + 8804 => x"00", + 8805 => x"00", + 8806 => x"00", + 8807 => x"01", + 8808 => x"00", + 8809 => x"00", + 8810 => x"00", + 8811 => x"00", + 8812 => x"00", + 8813 => x"00", + 8814 => x"00", + 8815 => x"01", + 8816 => x"00", + 8817 => x"00", + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; +end arch; diff --git a/zpu/devices/sysbus/BRAM/IOCP_zOS_BootROM.vhd b/zpu/devices/sysbus/BRAM/IOCP_zOS_BootROM.vhd new file mode 100644 index 0000000..df7fa64 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/IOCP_zOS_BootROM.vhd @@ -0,0 +1,9500 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com +-- Modified by Philip Smart 02/2019 for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity BootROM is +port ( + clk : in std_logic; + areset : in std_logic := '0'; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + memBRead : out std_logic_vector(WORD_32BIT_RANGE) +); +end BootROM; + +architecture arch of BootROM is + +type ram_type is array(natural range 0 to (2**(SOC_MAX_ADDR_BRAM_BIT-2))-1) of std_logic_vector(WORD_32BIT_RANGE); + +shared variable ram : ram_type := +( + 0 => x"0b0b0b88", + 1 => x"e0040000", + 2 => x"00000000", + 3 => x"00000000", + 4 => x"00000000", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"88088c08", + 9 => x"90080b0b", + 10 => x"0b888008", + 11 => x"2d900c8c", + 12 => x"0c880c04", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a50400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"09810572", + 51 => x"0a100a72", + 52 => x"0a100a31", + 53 => x"050a8106", + 54 => x"51515351", + 55 => x"04000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b88", + 73 => x"c4040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b88a7", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"04067383", + 106 => x"06098105", + 107 => x"8205832b", + 108 => x"0b2b0772", + 109 => x"fc060c51", + 110 => x"51040000", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b0b9f", + 162 => x"d0738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"88ac0400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"88088c08", + 169 => x"90087575", + 170 => x"0b0b0b89", + 171 => x"cf2d5050", + 172 => x"88085690", + 173 => x"0c8c0c88", + 174 => x"0c510400", + 175 => x"00000000", + 176 => x"88088c08", + 177 => x"90087575", + 178 => x"0b0b0b8b", + 179 => x"812d5050", + 180 => x"88085690", + 181 => x"0c8c0c88", + 182 => x"0c510400", + 183 => x"00000000", + 184 => x"72097081", + 185 => x"0509060a", + 186 => x"8106ff05", + 187 => x"70547106", + 188 => x"73097274", + 189 => x"05ff0506", + 190 => x"07515151", + 191 => x"04000000", + 192 => x"72097081", + 193 => x"0509060a", + 194 => x"098106ff", + 195 => x"05705471", + 196 => x"06730972", + 197 => x"7405ff05", + 198 => x"06075151", + 199 => x"51040000", + 200 => x"05ff0504", + 201 => x"00000000", + 202 => x"00000000", + 203 => x"00000000", + 204 => x"00000000", + 205 => x"00000000", + 206 => x"00000000", + 207 => x"00000000", + 208 => x"04000000", + 209 => x"00000000", + 210 => x"00000000", + 211 => x"00000000", + 212 => x"00000000", + 213 => x"00000000", + 214 => x"00000000", + 215 => x"00000000", + 216 => x"71810552", + 217 => x"04000000", + 218 => x"00000000", + 219 => x"00000000", + 220 => x"00000000", + 221 => x"00000000", + 222 => x"00000000", + 223 => x"00000000", + 224 => x"04000000", + 225 => x"00000000", + 226 => x"00000000", + 227 => x"00000000", + 228 => x"00000000", + 229 => x"00000000", + 230 => x"00000000", + 231 => x"00000000", + 232 => x"02840572", + 233 => x"10100552", + 234 => x"04000000", + 235 => x"00000000", + 236 => x"00000000", + 237 => x"00000000", + 238 => x"00000000", + 239 => x"00000000", + 240 => x"00000000", + 241 => x"00000000", + 242 => x"00000000", + 243 => x"00000000", + 244 => x"00000000", + 245 => x"00000000", + 246 => x"00000000", + 247 => x"00000000", + 248 => x"717105ff", + 249 => x"05715351", + 250 => x"020d0400", + 251 => x"00000000", + 252 => x"00000000", + 253 => x"00000000", + 254 => x"00000000", + 255 => x"00000000", + 256 => x"00000404", + 257 => x"04000000", + 258 => x"10101010", + 259 => x"10101010", + 260 => x"10101010", + 261 => x"10101010", + 262 => x"10101010", + 263 => x"10101010", + 264 => x"10101010", + 265 => x"10101053", + 266 => x"51040000", + 267 => x"7381ff06", + 268 => x"73830609", + 269 => x"81058305", + 270 => x"1010102b", + 271 => x"0772fc06", + 272 => x"0c515104", + 273 => x"72728072", + 274 => x"8106ff05", + 275 => x"09720605", + 276 => x"71105272", + 277 => x"0a100a53", + 278 => x"72ed3851", + 279 => x"51535104", + 280 => x"9ff470a0", + 281 => x"a4278e38", + 282 => x"80717084", + 283 => x"05530c0b", + 284 => x"0b0b88e2", + 285 => x"0488fe51", + 286 => x"9e9d0400", + 287 => x"80040088", + 288 => x"fe040000", + 289 => x"00940802", + 290 => x"940cfd3d", + 291 => x"0d805394", + 292 => x"088c0508", + 293 => x"52940888", + 294 => x"05085182", + 295 => x"de3f8808", + 296 => x"70880c54", + 297 => x"853d0d94", + 298 => x"0c049408", + 299 => x"02940cfd", + 300 => x"3d0d8153", + 301 => x"94088c05", + 302 => x"08529408", + 303 => x"88050851", + 304 => x"82b93f88", + 305 => x"0870880c", + 306 => x"54853d0d", + 307 => x"940c0494", + 308 => x"0802940c", + 309 => x"f93d0d80", + 310 => x"0b9408fc", + 311 => x"050c9408", + 312 => x"88050880", + 313 => x"25ab3894", + 314 => x"08880508", + 315 => x"30940888", + 316 => x"050c800b", + 317 => x"9408f405", + 318 => x"0c9408fc", + 319 => x"05088838", + 320 => x"810b9408", + 321 => x"f4050c94", + 322 => x"08f40508", + 323 => x"9408fc05", + 324 => x"0c94088c", + 325 => x"05088025", + 326 => x"ab389408", + 327 => x"8c050830", + 328 => x"94088c05", + 329 => x"0c800b94", + 330 => x"08f0050c", + 331 => x"9408fc05", + 332 => x"08883881", + 333 => x"0b9408f0", + 334 => x"050c9408", + 335 => x"f0050894", + 336 => x"08fc050c", + 337 => x"80539408", + 338 => x"8c050852", + 339 => x"94088805", + 340 => x"085181a7", + 341 => x"3f880870", + 342 => x"9408f805", + 343 => x"0c549408", + 344 => x"fc050880", + 345 => x"2e8c3894", + 346 => x"08f80508", + 347 => x"309408f8", + 348 => x"050c9408", + 349 => x"f8050870", + 350 => x"880c5489", + 351 => x"3d0d940c", + 352 => x"04940802", + 353 => x"940cfb3d", + 354 => x"0d800b94", + 355 => x"08fc050c", + 356 => x"94088805", + 357 => x"08802593", + 358 => x"38940888", + 359 => x"05083094", + 360 => x"0888050c", + 361 => x"810b9408", + 362 => x"fc050c94", + 363 => x"088c0508", + 364 => x"80258c38", + 365 => x"94088c05", + 366 => x"08309408", + 367 => x"8c050c81", + 368 => x"5394088c", + 369 => x"05085294", + 370 => x"08880508", + 371 => x"51ad3f88", + 372 => x"08709408", + 373 => x"f8050c54", + 374 => x"9408fc05", + 375 => x"08802e8c", + 376 => x"389408f8", + 377 => x"05083094", + 378 => x"08f8050c", + 379 => x"9408f805", + 380 => x"0870880c", + 381 => x"54873d0d", + 382 => x"940c0494", + 383 => x"0802940c", + 384 => x"fd3d0d81", + 385 => x"0b9408fc", + 386 => x"050c800b", + 387 => x"9408f805", + 388 => x"0c94088c", + 389 => x"05089408", + 390 => x"88050827", + 391 => x"ac389408", + 392 => x"fc050880", + 393 => x"2ea33880", + 394 => x"0b94088c", + 395 => x"05082499", + 396 => x"3894088c", + 397 => x"05081094", + 398 => x"088c050c", + 399 => x"9408fc05", + 400 => x"08109408", + 401 => x"fc050cc9", + 402 => x"399408fc", + 403 => x"0508802e", + 404 => x"80c93894", + 405 => x"088c0508", + 406 => x"94088805", + 407 => x"0826a138", + 408 => x"94088805", + 409 => x"0894088c", + 410 => x"05083194", + 411 => x"0888050c", + 412 => x"9408f805", + 413 => x"089408fc", + 414 => x"05080794", + 415 => x"08f8050c", + 416 => x"9408fc05", + 417 => x"08812a94", + 418 => x"08fc050c", + 419 => x"94088c05", + 420 => x"08812a94", + 421 => x"088c050c", + 422 => x"ffaf3994", + 423 => x"08900508", + 424 => x"802e8f38", + 425 => x"94088805", + 426 => x"08709408", + 427 => x"f4050c51", + 428 => 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x"32000000", + 10204 => x"ebfe904d", + 10205 => x"53444f53", + 10206 => x"352e3000", + 10207 => x"4e4f204e", + 10208 => x"414d4520", + 10209 => x"20202046", + 10210 => x"41543332", + 10211 => x"20202000", + 10212 => x"4e4f204e", + 10213 => x"414d4520", + 10214 => x"20202046", + 10215 => x"41542020", + 10216 => x"20202000", + 10217 => x"00007f50", + 10218 => x"00000000", + 10219 => x"00000000", + 10220 => x"00000000", + 10221 => x"809a4541", + 10222 => x"8e418f80", + 10223 => x"45454549", + 10224 => x"49498e8f", + 10225 => x"9092924f", + 10226 => x"994f5555", + 10227 => x"59999a9b", + 10228 => x"9c9d9e9f", + 10229 => x"41494f55", + 10230 => x"a5a5a6a7", + 10231 => x"a8a9aaab", + 10232 => x"acadaeaf", + 10233 => x"b0b1b2b3", + 10234 => x"b4b5b6b7", + 10235 => x"b8b9babb", + 10236 => x"bcbdbebf", + 10237 => x"c0c1c2c3", + 10238 => x"c4c5c6c7", + 10239 => x"c8c9cacb", + 10240 => x"cccdcecf", + 10241 => x"d0d1d2d3", + 10242 => x"d4d5d6d7", + 10243 => x"d8d9dadb", + 10244 => x"dcdddedf", + 10245 => x"e0e1e2e3", + 10246 => x"e4e5e6e7", + 10247 => x"e8e9eaeb", + 10248 => x"ecedeeef", + 10249 => x"f0f1f2f3", + 10250 => x"f4f5f6f7", + 10251 => x"f8f9fafb", + 10252 => x"fcfdfeff", + 10253 => x"2b2e2c3b", + 10254 => x"3d5b5d2f", + 10255 => x"5c222a3a", + 10256 => x"3c3e3f7c", + 10257 => x"7f000000", + 10258 => x"00010004", + 10259 => x"00100040", + 10260 => x"01000200", + 10261 => x"00000000", + 10262 => x"00010002", + 10263 => x"00040008", + 10264 => x"00100020", + 10265 => x"00000000", + 10266 => x"00000000", + 10267 => x"000074c8", + 10268 => x"01020100", + 10269 => x"00000000", + 10270 => x"00000000", + 10271 => x"000074d0", + 10272 => x"01040100", + 10273 => x"00000000", + 10274 => x"00000000", + 10275 => x"000074d8", + 10276 => x"01140300", + 10277 => x"00000000", + 10278 => x"00000000", + 10279 => x"000074e0", + 10280 => x"012b0300", + 10281 => x"00000000", + 10282 => x"00000000", + 10283 => x"000074e8", + 10284 => x"01300300", + 10285 => x"00000000", + 10286 => x"00000000", + 10287 => x"000074f0", + 10288 => x"013c0400", + 10289 => x"00000000", + 10290 => x"00000000", + 10291 => x"000074f8", + 10292 => x"013d0400", + 10293 => x"00000000", + 10294 => x"00000000", + 10295 => x"00007500", + 10296 => x"013f0400", + 10297 => x"00000000", + 10298 => x"00000000", + 10299 => x"00007508", + 10300 => x"01400400", + 10301 => x"00000000", + 10302 => x"00000000", + 10303 => x"00007510", + 10304 => x"01410400", + 10305 => x"00000000", + 10306 => x"00000000", + 10307 => x"00007514", + 10308 => x"01420400", + 10309 => x"00000000", + 10310 => x"00000000", + 10311 => x"00007518", + 10312 => x"01430400", + 10313 => x"00000000", + 10314 => x"00000000", + 10315 => x"0000751c", + 10316 => x"01500500", + 10317 => x"00000000", + 10318 => x"00000000", + 10319 => x"00007520", + 10320 => x"01510500", + 10321 => x"00000000", + 10322 => x"00000000", + 10323 => x"00007524", + 10324 => x"01540500", + 10325 => x"00000000", + 10326 => x"00000000", + 10327 => x"00007528", + 10328 => x"01550500", + 10329 => x"00000000", + 10330 => x"00000000", + 10331 => x"0000752c", + 10332 => x"01790700", + 10333 => x"00000000", + 10334 => x"00000000", + 10335 => x"00007534", + 10336 => x"01780700", + 10337 => x"00000000", + 10338 => x"00000000", + 10339 => x"00007538", + 10340 => x"01820800", + 10341 => x"00000000", + 10342 => x"00000000", + 10343 => x"00007540", + 10344 => x"01830800", + 10345 => x"00000000", + 10346 => x"00000000", + 10347 => x"00007548", + 10348 => x"01850800", + 10349 => x"00000000", + 10350 => x"00000000", + 10351 => x"00007550", + 10352 => x"01870800", + 10353 => x"00000000", + 10354 => x"00000000", + 10355 => x"00007558", + 10356 => x"018c0900", + 10357 => x"00000000", + 10358 => x"00000000", + 10359 => x"00007560", + 10360 => x"018d0900", + 10361 => x"00000000", + 10362 => x"00000000", + 10363 => x"00007568", + 10364 => x"018e0900", + 10365 => x"00000000", + 10366 => x"00000000", + 10367 => x"00007570", + 10368 => x"018f0900", + 10369 => x"00000000", + 10370 => x"00000000", + 10371 => x"00000000", + 10372 => x"00000000", + 10373 => x"00007fff", + 10374 => x"00000000", + 10375 => x"00007fff", + 10376 => x"00010000", + 10377 => x"00007fff", + 10378 => x"00010000", + 10379 => x"00810000", + 10380 => x"01000000", + 10381 => x"017fffff", + 10382 => x"00000000", + 10383 => x"00000000", + 10384 => x"00007800", + 10385 => x"00000000", + 10386 => x"05f5e100", + 10387 => x"05f5e100", + 10388 => x"05f5e100", + 10389 => x"00000000", + 10390 => x"01010101", + 10391 => x"01010101", + 10392 => x"01011001", + 10393 => x"01000000", + 10394 => x"00000000", + 10395 => x"00000000", + 10396 => x"00000000", + 10397 => x"00000000", + 10398 => x"00000000", + 10399 => x"00000000", + 10400 => x"00000000", + 10401 => x"00000000", + 10402 => x"00000000", + 10403 => x"00000000", + 10404 => x"00000000", + 10405 => x"00000000", + 10406 => x"00000000", + 10407 => x"00000000", + 10408 => x"00000000", + 10409 => x"00000000", + 10410 => x"00000000", + 10411 => x"00000000", + 10412 => x"00000000", + 10413 => x"00000000", + 10414 => x"00000000", + 10415 => x"00000000", + 10416 => x"00000000", + 10417 => x"00000000", + 10418 => x"00007ed4", + 10419 => x"01000000", + 10420 => x"00007edc", + 10421 => x"01000000", + 10422 => x"00007ee4", + 10423 => x"02000000", + 10424 => x"00000000", + 10425 => x"00000000", + 10426 => x"01000000", + others => x"00000000" + ); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + + +end arch; + diff --git a/zpu/devices/sysbus/BRAM/SinglePortBRAM.vhd b/zpu/devices/sysbus/BRAM/SinglePortBRAM.vhd new file mode 120000 index 0000000..304a91f --- /dev/null +++ b/zpu/devices/sysbus/BRAM/SinglePortBRAM.vhd @@ -0,0 +1 @@ +SinglePortBRAM.vhd.uninitialized \ No newline at end of file diff --git a/zpu/devices/sysbus/BRAM/SinglePortBRAM.vhd.uninitialized b/zpu/devices/sysbus/BRAM/SinglePortBRAM.vhd.uninitialized new file mode 100644 index 0000000..025780a --- /dev/null +++ b/zpu/devices/sysbus/BRAM/SinglePortBRAM.vhd.uninitialized @@ -0,0 +1,161 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity SinglePortBRAM is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end SinglePortBRAM; + +architecture arch of SinglePortBRAM is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + others => X"00" + ); + shared variable RAM1 : ramArray := + ( + others => X"00" + ); + shared variable RAM2 : ramArray := + ( + others => X"00" + ); + shared variable RAM3 : ramArray := + ( + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; +end arch; diff --git a/zpu/devices/sysbus/BRAM/SinglePortBootBRAM.vhd b/zpu/devices/sysbus/BRAM/SinglePortBootBRAM.vhd new file mode 120000 index 0000000..31b56af --- /dev/null +++ b/zpu/devices/sysbus/BRAM/SinglePortBootBRAM.vhd @@ -0,0 +1 @@ +zOS_SinglePortBootBRAM.vhd \ No newline at end of file diff --git a/zpu/devices/sysbus/BRAM/ZPUTA_BootROM.vhd b/zpu/devices/sysbus/BRAM/ZPUTA_BootROM.vhd new file mode 100644 index 0000000..b06cd31 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/ZPUTA_BootROM.vhd @@ -0,0 +1,7220 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com +-- Modified by Philip Smart 02/2019 for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity BootROM is +port ( + clk : in std_logic; + areset : in std_logic := '0'; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + memBRead : out std_logic_vector(WORD_32BIT_RANGE) +); +end BootROM; + +architecture arch of BootROM is + +type ram_type is array(natural range 0 to (2**(SOC_MAX_ADDR_BRAM_BIT-2))-1) of std_logic_vector(WORD_32BIT_RANGE); + +shared variable ram : ram_type := +( + 0 => x"0b0b0b92", + 1 => x"d8040000", + 2 => x"00000000", + 3 => x"00000000", + 4 => x"00000000", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"88088c08", + 9 => x"90088880", + 10 => x"082d900c", + 11 => x"8c0c880c", + 12 => x"04000000", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a50400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"09810572", + 51 => x"0a100a72", + 52 => x"0a100a31", + 53 => x"050a8106", + 54 => x"51515351", + 55 => x"04000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b92", + 73 => x"bc040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b929f", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"04067383", + 106 => x"06098105", + 107 => x"8205832b", + 108 => x"0b2b0772", + 109 => x"fc060c51", + 110 => x"51040000", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => 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x"000067b0", + 7077 => x"01430400", + 7078 => x"00000000", + 7079 => x"00000000", + 7080 => x"000067b4", + 7081 => x"01500500", + 7082 => x"00000000", + 7083 => x"00000000", + 7084 => x"000067b8", + 7085 => x"01510500", + 7086 => x"00000000", + 7087 => x"00000000", + 7088 => x"000067bc", + 7089 => x"01540500", + 7090 => x"00000000", + 7091 => x"00000000", + 7092 => x"000067c0", + 7093 => x"01550500", + 7094 => x"00000000", + 7095 => x"00000000", + 7096 => x"000067c4", + 7097 => x"01790700", + 7098 => x"00000000", + 7099 => x"00000000", + 7100 => x"000067cc", + 7101 => x"01780700", + 7102 => x"00000000", + 7103 => x"00000000", + 7104 => x"000067d0", + 7105 => x"01820800", + 7106 => x"00000000", + 7107 => x"00000000", + 7108 => x"000067d8", + 7109 => x"01830800", + 7110 => x"00000000", + 7111 => x"00000000", + 7112 => x"000067e0", + 7113 => x"01850800", + 7114 => x"00000000", + 7115 => x"00000000", + 7116 => x"000067e8", + 7117 => x"01870800", + 7118 => x"00000000", + 7119 => x"00000000", + others => x"00000000" + ); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + + +end arch; + diff --git a/zpu/devices/sysbus/BRAM/ZPUTA_DualPortBootBRAM.vhd b/zpu/devices/sysbus/BRAM/ZPUTA_DualPortBootBRAM.vhd new file mode 100644 index 0000000..03953f2 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/ZPUTA_DualPortBootBRAM.vhd @@ -0,0 +1,28702 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity DualPortBootBRAM is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + + memBAddr : in std_logic_vector(addrbits-1 downto 2); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBRead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end DualPortBootBRAM; + +architecture arch of DualPortBootBRAM is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + 0 => x"92", + 1 => x"00", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"80", + 10 => x"0c", + 11 => x"0c", + 12 => x"00", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"08", + 17 => x"09", + 18 => x"05", + 19 => x"83", + 20 => x"52", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"08", + 25 => x"73", + 26 => x"81", + 27 => x"83", + 28 => x"06", + 29 => x"ff", + 30 => x"0b", + 31 => x"00", + 32 => x"05", + 33 => x"73", + 34 => x"06", + 35 => x"06", + 36 => x"06", + 37 => x"00", + 38 => x"00", + 39 => x"00", + 40 => x"73", + 41 => x"53", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"09", + 49 => x"06", + 50 => x"72", + 51 => x"72", + 52 => x"31", + 53 => x"06", + 54 => x"51", + 55 => x"00", + 56 => x"73", + 57 => x"53", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"92", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"2b", + 81 => x"04", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"06", + 89 => x"0b", + 90 => x"9f", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"ff", + 97 => x"2a", + 98 => x"0a", + 99 => x"05", + 100 => x"51", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"51", + 105 => x"83", + 106 => x"05", + 107 => x"2b", + 108 => x"72", + 109 => x"51", + 110 => x"00", + 111 => x"00", + 112 => x"05", + 113 => x"70", + 114 => x"06", + 115 => x"53", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"05", + 121 => x"70", + 122 => x"06", + 123 => x"06", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"05", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"81", + 137 => x"51", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"06", + 145 => x"06", + 146 => x"04", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"08", + 153 => x"09", + 154 => x"05", + 155 => x"2a", + 156 => x"52", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"08", + 161 => x"c5", + 162 => x"06", + 163 => x"08", + 164 => x"0b", + 165 => x"00", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"75", + 170 => x"93", + 171 => x"50", + 172 => x"90", + 173 => x"88", + 174 => x"00", + 175 => x"00", + 176 => x"08", + 177 => x"75", + 178 => x"95", + 179 => x"50", + 180 => x"90", + 181 => x"88", + 182 => x"00", + 183 => x"00", + 184 => x"81", + 185 => x"0a", + 186 => x"05", + 187 => x"06", + 188 => x"74", + 189 => x"06", + 190 => x"51", + 191 => x"00", + 192 => x"81", + 193 => x"0a", + 194 => x"ff", + 195 => x"71", + 196 => x"72", + 197 => x"05", + 198 => x"51", + 199 => x"00", + 200 => x"04", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"52", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"72", + 233 => x"52", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"ff", + 249 => x"51", + 250 => x"ff", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"00", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"8c", + 265 => x"0b", + 266 => x"04", + 267 => x"8c", + 268 => x"0b", + 269 => x"04", + 270 => x"8c", + 271 => x"0b", + 272 => x"04", + 273 => x"8c", + 274 => x"0b", + 275 => x"04", + 276 => x"8c", + 277 => x"0b", + 278 => x"04", + 279 => x"8d", + 280 => x"0b", + 281 => x"04", + 282 => x"8d", + 283 => x"0b", + 284 => x"04", + 285 => x"8d", + 286 => x"0b", + 287 => x"04", + 288 => x"8d", + 289 => x"0b", + 290 => x"04", + 291 => x"8e", + 292 => x"0b", + 293 => x"04", + 294 => x"8e", + 295 => x"0b", + 296 => x"04", + 297 => x"8e", + 298 => x"0b", + 299 => x"04", + 300 => x"8e", + 301 => x"0b", + 302 => x"04", + 303 => x"8f", + 304 => x"0b", + 305 => x"04", + 306 => x"8f", + 307 => x"0b", + 308 => x"04", + 309 => x"8f", + 310 => x"0b", + 311 => x"04", + 312 => x"8f", + 313 => x"0b", + 314 => x"04", + 315 => x"90", + 316 => x"0b", + 317 => x"04", + 318 => x"90", + 319 => x"0b", + 320 => x"04", + 321 => x"90", + 322 => x"0b", + 323 => x"04", + 324 => x"90", + 325 => x"0b", + 326 => x"04", + 327 => x"91", + 328 => x"0b", + 329 => x"04", + 330 => x"91", + 331 => x"0b", + 332 => x"04", + 333 => x"91", + 334 => x"0b", + 335 => x"04", + 336 => x"91", + 337 => x"0b", + 338 => x"04", + 339 => x"ff", + 340 => x"ff", + 341 => x"ff", + 342 => x"ff", + 343 => x"ff", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"81", + 385 => x"cc", + 386 => x"2d", + 387 => x"08", + 388 => x"04", + 389 => x"0c", + 390 => x"81", + 391 => x"84", + 392 => x"81", + 393 => x"ae", + 394 => x"de", + 395 => x"80", + 396 => x"de", + 397 => x"bf", + 398 => x"cc", + 399 => x"90", + 400 => x"cc", + 401 => x"2d", + 402 => x"08", + 403 => x"04", + 404 => x"0c", + 405 => x"81", + 406 => x"84", + 407 => x"81", + 408 => x"ae", + 409 => x"de", + 410 => x"80", + 411 => x"de", + 412 => x"98", + 413 => x"cc", + 414 => x"90", + 415 => x"cc", + 416 => x"2d", + 417 => x"08", + 418 => x"04", + 419 => x"0c", + 420 => x"81", + 421 => x"84", + 422 => x"81", + 423 => x"b4", + 424 => x"de", + 425 => x"80", + 426 => x"de", + 427 => x"dd", + 428 => x"cc", + 429 => x"90", + 430 => x"cc", + 431 => x"2d", + 432 => x"08", + 433 => x"04", + 434 => x"0c", + 435 => x"81", + 436 => x"84", + 437 => x"81", + 438 => x"9b", + 439 => x"de", + 440 => x"80", + 441 => x"de", + 442 => x"dd", + 443 => x"cc", + 444 => x"90", + 445 => x"cc", + 446 => x"2d", + 447 => x"08", + 448 => x"04", + 449 => x"0c", + 450 => x"2d", + 451 => x"08", + 452 => x"04", + 453 => x"0c", + 454 => x"2d", + 455 => x"08", + 456 => x"04", + 457 => x"0c", + 458 => x"2d", + 459 => x"08", + 460 => x"04", + 461 => x"0c", + 462 => x"2d", + 463 => x"08", + 464 => x"04", + 465 => x"0c", + 466 => x"2d", + 467 => x"08", + 468 => x"04", + 469 => x"0c", + 470 => x"2d", + 471 => x"08", + 472 => x"04", + 473 => x"0c", + 474 => x"2d", + 475 => x"08", + 476 => x"04", + 477 => x"0c", + 478 => x"2d", + 479 => x"08", + 480 => x"04", + 481 => x"0c", + 482 => x"2d", + 483 => x"08", + 484 => x"04", + 485 => x"0c", + 486 => x"2d", + 487 => x"08", + 488 => x"04", + 489 => x"0c", + 490 => x"2d", + 491 => x"08", + 492 => x"04", + 493 => x"0c", + 494 => x"2d", + 495 => x"08", + 496 => x"04", + 497 => x"0c", + 498 => x"2d", + 499 => x"08", + 500 => x"04", + 501 => x"0c", + 502 => x"2d", + 503 => x"08", + 504 => x"04", + 505 => x"0c", + 506 => x"2d", + 507 => x"08", + 508 => x"04", + 509 => x"0c", + 510 => x"2d", + 511 => x"08", + 512 => x"04", + 513 => x"0c", + 514 => x"2d", + 515 => x"08", + 516 => x"04", + 517 => x"0c", + 518 => x"2d", + 519 => x"08", + 520 => x"04", + 521 => x"0c", + 522 => x"2d", + 523 => x"08", + 524 => x"04", + 525 => x"0c", + 526 => x"2d", + 527 => x"08", + 528 => x"04", + 529 => x"0c", + 530 => x"2d", + 531 => x"08", + 532 => x"04", + 533 => x"0c", + 534 => x"2d", + 535 => x"08", + 536 => x"04", + 537 => x"0c", + 538 => x"2d", + 539 => x"08", + 540 => x"04", + 541 => x"0c", + 542 => x"2d", + 543 => x"08", + 544 => x"04", + 545 => x"0c", + 546 => x"2d", + 547 => x"08", + 548 => x"04", + 549 => x"0c", + 550 => x"81", + 551 => x"84", + 552 => x"81", + 553 => x"bd", + 554 => x"de", + 555 => x"80", + 556 => x"de", + 557 => x"e7", + 558 => x"cc", + 559 => x"90", + 560 => x"cc", + 561 => x"2d", + 562 => x"08", + 563 => x"04", + 564 => x"0c", + 565 => x"81", + 566 => x"84", + 567 => x"81", + 568 => x"9f", + 569 => x"de", + 570 => x"80", + 571 => x"de", + 572 => x"a5", + 573 => x"de", + 574 => x"80", + 575 => x"04", + 576 => x"10", + 577 => x"10", + 578 => x"10", + 579 => x"10", + 580 => x"10", + 581 => x"10", + 582 => x"10", + 583 => x"53", + 584 => x"00", + 585 => x"06", + 586 => x"09", + 587 => x"05", + 588 => x"2b", + 589 => x"06", + 590 => x"04", + 591 => x"72", + 592 => x"05", + 593 => x"05", + 594 => x"72", + 595 => x"53", + 596 => x"51", + 597 => x"04", + 598 => x"70", + 599 => x"27", + 600 => x"71", + 601 => x"53", + 602 => x"0b", + 603 => x"8c", + 604 => x"c4", + 605 => x"81", + 606 => x"02", + 607 => x"0c", + 608 => x"80", + 609 => x"cc", + 610 => x"08", + 611 => x"cc", + 612 => x"08", + 613 => x"3f", + 614 => x"08", + 615 => x"c0", + 616 => x"3d", + 617 => x"cc", + 618 => x"de", + 619 => x"81", + 620 => x"fd", + 621 => x"53", + 622 => x"08", + 623 => x"52", + 624 => x"08", + 625 => x"51", + 626 => x"81", + 627 => x"70", + 628 => x"0c", + 629 => x"0d", + 630 => x"0c", + 631 => x"cc", + 632 => x"de", + 633 => x"3d", + 634 => x"81", + 635 => x"fc", + 636 => x"de", + 637 => x"05", + 638 => x"b9", + 639 => x"cc", + 640 => x"08", + 641 => x"cc", + 642 => x"0c", + 643 => x"de", + 644 => x"05", + 645 => x"cc", + 646 => x"08", + 647 => x"0b", + 648 => x"08", + 649 => x"81", + 650 => x"f4", + 651 => x"de", + 652 => x"05", + 653 => x"cc", + 654 => x"08", + 655 => x"38", + 656 => x"08", + 657 => x"30", + 658 => x"08", + 659 => x"80", + 660 => x"cc", + 661 => x"0c", + 662 => x"08", + 663 => x"8a", + 664 => x"81", + 665 => x"f0", + 666 => x"de", + 667 => x"05", + 668 => x"cc", + 669 => x"0c", + 670 => x"de", + 671 => x"05", + 672 => x"de", + 673 => x"05", + 674 => x"df", + 675 => x"c0", + 676 => x"de", + 677 => x"05", + 678 => x"de", + 679 => x"05", + 680 => x"90", + 681 => x"cc", + 682 => x"08", + 683 => x"cc", + 684 => x"0c", + 685 => x"08", + 686 => x"70", + 687 => x"0c", + 688 => x"0d", + 689 => x"0c", + 690 => x"cc", + 691 => x"de", + 692 => x"3d", + 693 => x"81", + 694 => x"fc", + 695 => x"de", + 696 => x"05", + 697 => x"99", + 698 => x"cc", + 699 => x"08", + 700 => x"cc", + 701 => x"0c", + 702 => x"de", + 703 => x"05", + 704 => x"cc", + 705 => x"08", + 706 => x"38", + 707 => x"08", + 708 => x"30", + 709 => x"08", + 710 => x"81", + 711 => x"cc", + 712 => x"08", + 713 => x"cc", + 714 => x"08", + 715 => x"81", + 716 => x"70", + 717 => x"08", + 718 => x"54", + 719 => x"08", + 720 => x"80", + 721 => x"81", + 722 => x"f8", + 723 => x"81", + 724 => x"f8", + 725 => x"de", + 726 => x"05", + 727 => x"de", + 728 => x"87", + 729 => x"de", + 730 => x"81", + 731 => x"02", + 732 => x"0c", + 733 => x"81", + 734 => x"cc", + 735 => x"0c", + 736 => x"de", + 737 => x"05", + 738 => x"cc", + 739 => x"08", + 740 => x"08", + 741 => x"27", + 742 => x"de", + 743 => x"05", + 744 => x"ae", + 745 => x"81", + 746 => x"8c", + 747 => x"a2", + 748 => x"cc", + 749 => x"08", + 750 => x"cc", + 751 => x"0c", + 752 => x"08", + 753 => x"10", + 754 => x"08", + 755 => x"ff", + 756 => x"de", + 757 => x"05", + 758 => x"80", + 759 => x"de", + 760 => x"05", + 761 => x"cc", + 762 => x"08", + 763 => x"81", + 764 => x"88", + 765 => x"de", + 766 => x"05", + 767 => x"de", + 768 => x"05", + 769 => x"cc", + 770 => x"08", + 771 => x"08", + 772 => x"07", + 773 => x"08", + 774 => x"81", + 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x"2e", + 1024 => x"93", + 1025 => x"06", + 1026 => x"ff", + 1027 => x"81", + 1028 => x"87", + 1029 => x"52", + 1030 => x"86", + 1031 => x"94", + 1032 => x"72", + 1033 => x"de", + 1034 => x"3d", + 1035 => x"3d", + 1036 => x"05", + 1037 => x"81", + 1038 => x"70", + 1039 => x"57", + 1040 => x"c0", + 1041 => x"74", + 1042 => x"38", + 1043 => x"94", + 1044 => x"70", + 1045 => x"81", + 1046 => x"52", + 1047 => x"8c", + 1048 => x"2a", + 1049 => x"51", + 1050 => x"38", + 1051 => x"70", + 1052 => x"51", + 1053 => x"8d", + 1054 => x"2a", + 1055 => x"51", + 1056 => x"be", + 1057 => x"ff", + 1058 => x"c0", + 1059 => x"70", + 1060 => x"38", + 1061 => x"90", + 1062 => x"0c", + 1063 => x"04", + 1064 => x"79", + 1065 => x"33", + 1066 => x"06", + 1067 => x"70", + 1068 => x"fe", + 1069 => x"ff", + 1070 => x"0b", + 1071 => x"88", + 1072 => x"ff", + 1073 => x"55", + 1074 => x"94", + 1075 => x"80", + 1076 => x"87", + 1077 => x"51", + 1078 => x"96", + 1079 => x"06", + 1080 => x"70", + 1081 => x"38", + 1082 => x"70", + 1083 => x"51", + 1084 => x"72", + 1085 => x"81", + 1086 => x"70", + 1087 => x"38", + 1088 => x"70", + 1089 => x"51", + 1090 => x"38", + 1091 => x"06", + 1092 => x"94", + 1093 => x"80", + 1094 => x"87", + 1095 => x"52", + 1096 => x"81", + 1097 => x"70", + 1098 => x"53", + 1099 => x"ff", + 1100 => x"81", + 1101 => x"89", + 1102 => x"fe", + 1103 => x"0b", + 1104 => x"33", + 1105 => x"06", + 1106 => x"c0", + 1107 => x"72", + 1108 => x"38", + 1109 => x"94", + 1110 => x"70", + 1111 => x"81", + 1112 => x"51", + 1113 => x"e2", + 1114 => x"ff", + 1115 => x"c0", + 1116 => x"70", + 1117 => x"38", + 1118 => x"90", + 1119 => x"70", + 1120 => x"81", + 1121 => x"51", + 1122 => x"04", + 1123 => x"0b", + 1124 => x"88", + 1125 => x"ff", + 1126 => x"87", + 1127 => x"52", + 1128 => x"86", + 1129 => x"94", + 1130 => x"08", + 1131 => x"70", + 1132 => x"51", + 1133 => x"70", + 1134 => x"38", + 1135 => x"06", + 1136 => x"94", + 1137 => x"80", + 1138 => x"87", + 1139 => x"52", + 1140 => x"98", + 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x"c0", + 1259 => x"70", + 1260 => x"51", + 1261 => x"80", + 1262 => x"81", + 1263 => x"db", + 1264 => x"c0", + 1265 => x"70", + 1266 => x"70", + 1267 => x"51", + 1268 => x"db", + 1269 => x"0b", + 1270 => x"90", + 1271 => x"80", + 1272 => x"52", + 1273 => x"83", + 1274 => x"71", + 1275 => x"34", + 1276 => x"90", + 1277 => x"f0", + 1278 => x"2a", + 1279 => x"70", + 1280 => x"34", + 1281 => x"c0", + 1282 => x"70", + 1283 => x"52", + 1284 => x"2e", + 1285 => x"52", + 1286 => x"df", + 1287 => x"9e", + 1288 => x"87", + 1289 => x"70", + 1290 => x"34", + 1291 => x"04", + 1292 => x"81", + 1293 => x"86", + 1294 => x"db", + 1295 => x"73", + 1296 => x"38", + 1297 => x"51", + 1298 => x"81", + 1299 => x"85", + 1300 => x"db", + 1301 => x"73", + 1302 => x"38", + 1303 => x"08", + 1304 => x"08", + 1305 => x"81", + 1306 => x"8b", + 1307 => x"db", + 1308 => x"73", + 1309 => x"38", + 1310 => x"08", + 1311 => x"08", + 1312 => x"81", + 1313 => x"8b", + 1314 => x"db", + 1315 => x"73", + 1316 => x"38", + 1317 => x"08", + 1318 => x"08", + 1319 => x"81", + 1320 => x"8a", + 1321 => x"db", + 1322 => x"73", + 1323 => x"38", + 1324 => x"08", + 1325 => x"08", + 1326 => x"81", + 1327 => x"8a", + 1328 => x"db", + 1329 => x"73", + 1330 => x"38", + 1331 => x"08", + 1332 => x"08", + 1333 => x"81", + 1334 => x"8a", + 1335 => x"db", + 1336 => x"73", + 1337 => x"38", + 1338 => x"33", + 1339 => x"c8", + 1340 => x"3f", + 1341 => x"33", + 1342 => x"2e", + 1343 => x"db", + 1344 => x"81", + 1345 => x"8a", + 1346 => x"db", + 1347 => x"73", + 1348 => x"38", + 1349 => x"33", + 1350 => x"88", + 1351 => x"3f", + 1352 => x"33", + 1353 => x"2e", + 1354 => x"c9", + 1355 => x"8f", + 1356 => x"d3", + 1357 => x"80", + 1358 => x"81", + 1359 => x"83", + 1360 => x"db", + 1361 => x"73", + 1362 => x"38", + 1363 => x"51", + 1364 => x"81", + 1365 => x"54", + 1366 => x"88", + 1367 => x"d4", + 1368 => x"3f", + 1369 => x"33", + 1370 => x"2e", + 1371 => x"c9", + 1372 => x"cb", + 1373 => x"ec", + 1374 => x"3f", + 1375 => x"08", + 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x"14", + 1494 => x"3f", + 1495 => x"3d", + 1496 => x"3d", + 1497 => x"de", + 1498 => x"81", + 1499 => x"56", + 1500 => x"70", + 1501 => x"53", + 1502 => x"2e", + 1503 => x"81", + 1504 => x"81", + 1505 => x"da", + 1506 => x"74", + 1507 => x"0c", + 1508 => x"04", + 1509 => x"66", + 1510 => x"78", + 1511 => x"5a", + 1512 => x"80", + 1513 => x"38", + 1514 => x"09", + 1515 => x"de", + 1516 => x"7a", + 1517 => x"5c", + 1518 => x"5b", + 1519 => x"09", + 1520 => x"38", + 1521 => x"39", + 1522 => x"09", + 1523 => x"38", + 1524 => x"70", + 1525 => x"33", + 1526 => x"2e", + 1527 => x"92", + 1528 => x"19", + 1529 => x"70", + 1530 => x"33", + 1531 => x"53", + 1532 => x"16", + 1533 => x"26", + 1534 => x"88", + 1535 => x"05", + 1536 => x"05", + 1537 => x"05", + 1538 => x"5b", + 1539 => x"80", + 1540 => x"30", + 1541 => x"80", + 1542 => x"cc", + 1543 => x"70", + 1544 => x"25", + 1545 => x"54", + 1546 => x"53", + 1547 => x"8c", + 1548 => x"07", + 1549 => x"05", + 1550 => x"5a", + 1551 => x"83", + 1552 => x"54", + 1553 => x"27", + 1554 => x"16", + 1555 => x"06", + 1556 => x"80", + 1557 => x"aa", + 1558 => x"cf", + 1559 => x"73", + 1560 => x"81", + 1561 => x"80", + 1562 => x"38", + 1563 => x"2e", + 1564 => x"81", + 1565 => x"80", + 1566 => x"8a", + 1567 => x"39", + 1568 => x"2e", + 1569 => x"73", + 1570 => x"8a", + 1571 => x"d3", + 1572 => x"80", + 1573 => x"80", + 1574 => x"ee", + 1575 => x"39", + 1576 => x"71", + 1577 => x"53", + 1578 => x"54", + 1579 => x"2e", + 1580 => x"15", + 1581 => x"33", + 1582 => x"72", + 1583 => x"81", + 1584 => x"39", + 1585 => x"56", + 1586 => x"27", + 1587 => x"51", + 1588 => x"75", + 1589 => x"72", + 1590 => x"38", + 1591 => x"df", + 1592 => x"16", + 1593 => x"7b", + 1594 => x"38", + 1595 => x"f2", + 1596 => x"77", + 1597 => x"12", + 1598 => x"53", + 1599 => x"5c", + 1600 => x"5c", + 1601 => x"5c", + 1602 => x"5c", + 1603 => x"51", + 1604 => x"fd", + 1605 => x"82", + 1606 => x"06", + 1607 => x"80", + 1608 => x"77", + 1609 => x"53", + 1610 => x"18", + 1611 => x"72", + 1612 => x"c4", + 1613 => x"70", + 1614 => x"25", + 1615 => x"55", + 1616 => x"8d", + 1617 => x"2e", + 1618 => x"30", + 1619 => x"5b", + 1620 => x"8f", + 1621 => x"7b", + 1622 => x"e0", + 1623 => x"de", + 1624 => x"ff", + 1625 => x"75", + 1626 => x"8b", + 1627 => x"c0", + 1628 => x"74", + 1629 => x"a7", + 1630 => x"80", + 1631 => x"38", + 1632 => x"72", + 1633 => x"54", + 1634 => x"72", + 1635 => x"05", + 1636 => x"17", + 1637 => x"77", + 1638 => x"51", + 1639 => x"9f", + 1640 => x"72", + 1641 => x"79", + 1642 => x"81", + 1643 => x"72", + 1644 => x"38", + 1645 => x"05", + 1646 => x"ad", + 1647 => x"17", + 1648 => x"81", + 1649 => x"b0", + 1650 => x"38", + 1651 => x"81", + 1652 => x"06", + 1653 => x"9f", + 1654 => x"55", + 1655 => x"97", + 1656 => x"f9", + 1657 => x"81", + 1658 => x"8b", + 1659 => x"16", + 1660 => x"73", + 1661 => x"96", + 1662 => x"e0", + 1663 => x"17", + 1664 => x"33", + 1665 => x"f9", + 1666 => x"f2", + 1667 => x"16", + 1668 => x"7b", + 1669 => x"38", + 1670 => x"c6", + 1671 => x"96", + 1672 => x"fd", + 1673 => x"3d", + 1674 => x"05", + 1675 => x"52", + 1676 => x"e0", + 1677 => x"0d", + 1678 => x"0d", + 1679 => x"d8", + 1680 => x"88", + 1681 => x"51", + 1682 => x"81", + 1683 => x"53", + 1684 => x"80", + 1685 => x"d8", + 1686 => x"0d", + 1687 => x"0d", + 1688 => x"08", + 1689 => x"d0", + 1690 => x"88", + 1691 => x"52", + 1692 => x"3f", + 1693 => x"d0", + 1694 => x"0d", + 1695 => x"0d", + 1696 => x"de", + 1697 => x"56", + 1698 => x"80", + 1699 => x"2e", + 1700 => x"81", + 1701 => x"52", + 1702 => x"de", + 1703 => x"ff", + 1704 => x"80", + 1705 => x"38", + 1706 => x"b9", + 1707 => x"32", + 1708 => x"80", + 1709 => x"52", + 1710 => x"8b", + 1711 => x"2e", + 1712 => x"14", + 1713 => x"9f", + 1714 => x"38", + 1715 => x"73", + 1716 => x"38", + 1717 => x"72", + 1718 => x"14", + 1719 => x"f8", + 1720 => x"af", + 1721 => x"52", + 1722 => x"8a", + 1723 => x"3f", + 1724 => x"81", + 1725 => x"87", + 1726 => x"fe", + 1727 => x"de", + 1728 => x"81", + 1729 => x"77", + 1730 => x"53", + 1731 => x"72", + 1732 => x"0c", + 1733 => x"04", + 1734 => x"7a", + 1735 => x"80", + 1736 => x"58", + 1737 => x"33", + 1738 => x"a0", + 1739 => x"06", + 1740 => x"13", + 1741 => x"39", + 1742 => x"09", + 1743 => x"38", + 1744 => x"11", + 1745 => x"08", + 1746 => x"54", + 1747 => x"2e", + 1748 => x"80", + 1749 => x"08", + 1750 => x"0c", + 1751 => x"33", + 1752 => x"80", + 1753 => x"38", + 1754 => x"80", + 1755 => x"38", + 1756 => x"57", + 1757 => x"0c", + 1758 => x"33", + 1759 => x"39", + 1760 => x"74", + 1761 => x"38", + 1762 => x"80", + 1763 => x"89", + 1764 => x"38", + 1765 => x"d0", + 1766 => x"55", + 1767 => x"80", + 1768 => x"39", + 1769 => x"d9", + 1770 => x"80", + 1771 => x"27", + 1772 => x"80", + 1773 => x"89", + 1774 => x"70", + 1775 => x"55", + 1776 => x"70", + 1777 => x"55", + 1778 => x"27", + 1779 => x"14", + 1780 => x"06", + 1781 => x"74", + 1782 => x"73", + 1783 => x"38", + 1784 => x"14", + 1785 => x"05", + 1786 => x"08", + 1787 => x"54", + 1788 => x"39", + 1789 => x"84", + 1790 => x"55", + 1791 => x"81", + 1792 => x"de", + 1793 => x"3d", + 1794 => x"3d", + 1795 => x"5a", + 1796 => x"7a", + 1797 => x"08", + 1798 => x"53", + 1799 => x"09", + 1800 => x"38", + 1801 => x"0c", + 1802 => x"ad", + 1803 => x"06", + 1804 => x"76", + 1805 => x"0c", + 1806 => x"33", + 1807 => x"73", + 1808 => x"81", + 1809 => x"38", + 1810 => x"05", + 1811 => x"08", + 1812 => x"53", + 1813 => x"2e", + 1814 => x"57", + 1815 => x"2e", + 1816 => x"39", + 1817 => x"13", + 1818 => x"08", + 1819 => x"53", + 1820 => x"55", + 1821 => x"80", + 1822 => x"14", + 1823 => x"88", + 1824 => x"27", + 1825 => x"eb", + 1826 => x"53", + 1827 => x"89", + 1828 => x"38", + 1829 => x"55", + 1830 => x"8a", + 1831 => x"a0", + 1832 => x"c2", + 1833 => x"74", + 1834 => x"e0", + 1835 => x"ff", + 1836 => x"d0", + 1837 => x"ff", + 1838 => x"90", + 1839 => x"38", + 1840 => x"81", + 1841 => x"53", + 1842 => x"ca", + 1843 => x"27", + 1844 => x"77", + 1845 => x"08", + 1846 => x"0c", + 1847 => x"33", + 1848 => x"ff", + 1849 => x"80", + 1850 => x"74", + 1851 => x"79", + 1852 => x"74", + 1853 => x"0c", + 1854 => x"04", + 1855 => x"02", + 1856 => x"51", + 1857 => x"72", + 1858 => x"81", + 1859 => x"33", + 1860 => x"de", + 1861 => x"3d", + 1862 => x"3d", + 1863 => x"05", + 1864 => x"05", + 1865 => x"56", + 1866 => x"72", + 1867 => x"e0", + 1868 => x"2b", + 1869 => x"8c", + 1870 => x"88", + 1871 => x"2e", + 1872 => x"88", + 1873 => x"0c", + 1874 => x"8c", + 1875 => x"71", + 1876 => x"87", + 1877 => x"0c", + 1878 => x"08", + 1879 => x"51", + 1880 => x"2e", + 1881 => x"c0", + 1882 => x"51", + 1883 => x"71", + 1884 => x"80", + 1885 => x"92", + 1886 => x"98", + 1887 => x"70", + 1888 => x"38", + 1889 => x"e8", + 1890 => x"db", + 1891 => x"51", + 1892 => x"c0", + 1893 => x"0d", + 1894 => x"0d", + 1895 => x"02", + 1896 => x"05", + 1897 => x"58", + 1898 => x"52", + 1899 => x"3f", + 1900 => x"08", + 1901 => x"54", + 1902 => x"be", + 1903 => x"75", + 1904 => x"c0", + 1905 => x"87", + 1906 => x"12", + 1907 => x"84", + 1908 => x"40", + 1909 => x"85", + 1910 => x"98", + 1911 => x"7d", + 1912 => x"0c", + 1913 => x"85", + 1914 => x"06", + 1915 => x"71", + 1916 => x"38", + 1917 => x"71", + 1918 => x"05", + 1919 => x"19", + 1920 => x"a2", + 1921 => x"71", + 1922 => x"38", + 1923 => x"83", + 1924 => x"38", + 1925 => x"8a", + 1926 => x"98", + 1927 => x"71", + 1928 => x"c0", + 1929 => x"52", + 1930 => x"87", + 1931 => x"80", + 1932 => x"81", + 1933 => x"c0", + 1934 => x"53", + 1935 => x"82", + 1936 => x"71", + 1937 => x"1a", + 1938 => x"84", + 1939 => x"19", + 1940 => x"06", + 1941 => x"79", + 1942 => x"38", + 1943 => x"80", + 1944 => x"87", + 1945 => x"26", + 1946 => x"73", + 1947 => x"06", + 1948 => x"2e", + 1949 => x"52", + 1950 => x"81", + 1951 => x"8f", + 1952 => x"f3", + 1953 => x"62", + 1954 => x"05", + 1955 => x"57", + 1956 => x"83", + 1957 => x"52", + 1958 => x"3f", + 1959 => x"08", + 1960 => x"54", + 1961 => x"2e", + 1962 => x"81", + 1963 => x"74", + 1964 => x"c0", + 1965 => x"87", + 1966 => x"12", + 1967 => x"84", + 1968 => x"5f", + 1969 => x"0b", + 1970 => x"8c", + 1971 => x"0c", + 1972 => x"80", + 1973 => x"70", + 1974 => x"81", + 1975 => x"54", + 1976 => x"8c", + 1977 => x"81", + 1978 => x"7c", + 1979 => x"58", + 1980 => x"70", + 1981 => x"52", + 1982 => x"8a", + 1983 => x"98", + 1984 => x"71", + 1985 => x"c0", + 1986 => x"52", + 1987 => x"87", + 1988 => x"80", + 1989 => x"81", + 1990 => x"c0", + 1991 => x"53", + 1992 => x"82", + 1993 => x"71", + 1994 => x"19", + 1995 => x"81", + 1996 => x"ff", + 1997 => x"19", + 1998 => x"78", + 1999 => x"38", + 2000 => x"80", + 2001 => x"87", + 2002 => x"26", + 2003 => x"73", + 2004 => x"06", + 2005 => x"2e", + 2006 => x"52", + 2007 => x"81", + 2008 => x"8f", + 2009 => x"f6", + 2010 => x"02", + 2011 => x"05", + 2012 => x"05", + 2013 => x"71", + 2014 => x"57", + 2015 => x"81", + 2016 => x"81", + 2017 => x"54", + 2018 => x"38", + 2019 => x"c0", + 2020 => x"81", + 2021 => x"2e", + 2022 => x"71", + 2023 => x"38", + 2024 => x"87", + 2025 => x"11", + 2026 => x"80", + 2027 => x"80", + 2028 => x"83", + 2029 => x"38", + 2030 => x"72", + 2031 => x"2a", + 2032 => x"51", + 2033 => x"80", + 2034 => x"87", + 2035 => x"08", + 2036 => x"38", + 2037 => x"8c", + 2038 => x"96", + 2039 => x"0c", + 2040 => x"8c", + 2041 => x"08", + 2042 => x"51", + 2043 => x"38", + 2044 => x"56", + 2045 => x"80", + 2046 => x"85", + 2047 => x"77", + 2048 => x"83", + 2049 => x"75", + 2050 => x"de", + 2051 => x"3d", + 2052 => x"3d", + 2053 => x"11", + 2054 => x"71", + 2055 => x"81", + 2056 => x"53", + 2057 => x"0d", + 2058 => x"0d", + 2059 => x"33", + 2060 => x"71", + 2061 => x"88", + 2062 => x"14", + 2063 => x"07", + 2064 => x"33", + 2065 => x"de", + 2066 => x"53", + 2067 => x"52", + 2068 => x"04", + 2069 => x"73", + 2070 => x"92", + 2071 => x"52", + 2072 => x"81", + 2073 => x"70", + 2074 => x"70", + 2075 => x"3d", + 2076 => x"3d", + 2077 => x"52", + 2078 => x"70", + 2079 => x"34", + 2080 => x"51", + 2081 => x"81", + 2082 => x"70", + 2083 => x"70", + 2084 => x"05", + 2085 => x"88", + 2086 => x"72", + 2087 => x"0d", + 2088 => x"0d", + 2089 => x"54", + 2090 => x"80", + 2091 => x"71", + 2092 => x"53", + 2093 => x"81", + 2094 => x"ff", + 2095 => x"39", + 2096 => x"04", + 2097 => x"75", + 2098 => x"52", + 2099 => x"70", + 2100 => x"34", + 2101 => x"70", + 2102 => x"3d", + 2103 => x"3d", + 2104 => x"79", + 2105 => x"74", + 2106 => x"56", + 2107 => x"81", + 2108 => x"71", + 2109 => x"16", + 2110 => x"52", + 2111 => x"86", + 2112 => x"2e", + 2113 => x"81", + 2114 => x"86", + 2115 => x"fe", + 2116 => x"76", + 2117 => x"39", + 2118 => x"8a", + 2119 => x"51", + 2120 => x"71", + 2121 => x"33", + 2122 => x"0c", + 2123 => x"04", + 2124 => x"de", + 2125 => x"80", + 2126 => x"c0", + 2127 => x"3d", + 2128 => x"80", + 2129 => x"33", + 2130 => x"7a", + 2131 => x"38", + 2132 => x"16", + 2133 => x"16", + 2134 => x"17", + 2135 => x"fa", + 2136 => x"de", + 2137 => x"2e", + 2138 => x"b7", + 2139 => x"c0", + 2140 => x"34", + 2141 => x"70", + 2142 => x"31", + 2143 => x"59", + 2144 => x"77", + 2145 => x"82", + 2146 => x"74", + 2147 => x"81", + 2148 => x"81", + 2149 => x"53", + 2150 => x"16", + 2151 => x"e3", + 2152 => x"81", + 2153 => x"de", + 2154 => x"3d", + 2155 => x"3d", + 2156 => x"56", + 2157 => x"74", + 2158 => x"2e", + 2159 => x"51", + 2160 => x"81", + 2161 => x"57", + 2162 => x"08", + 2163 => x"54", + 2164 => x"16", + 2165 => x"33", + 2166 => x"3f", + 2167 => x"08", + 2168 => x"38", + 2169 => x"57", + 2170 => x"0c", + 2171 => x"c0", + 2172 => x"0d", + 2173 => x"0d", + 2174 => x"57", + 2175 => x"81", + 2176 => x"58", + 2177 => x"08", + 2178 => x"76", + 2179 => x"83", + 2180 => x"06", + 2181 => x"84", + 2182 => x"78", + 2183 => x"81", + 2184 => x"38", + 2185 => x"81", + 2186 => x"52", + 2187 => x"52", + 2188 => x"3f", + 2189 => x"52", + 2190 => x"51", + 2191 => x"84", + 2192 => x"d2", + 2193 => x"fc", + 2194 => x"8a", + 2195 => x"52", + 2196 => x"51", + 2197 => x"90", + 2198 => x"84", + 2199 => x"fc", + 2200 => x"17", + 2201 => x"a0", + 2202 => x"86", + 2203 => x"08", + 2204 => x"b0", + 2205 => x"55", + 2206 => x"81", + 2207 => x"f8", + 2208 => x"84", + 2209 => x"53", + 2210 => x"17", + 2211 => x"d7", + 2212 => x"c0", + 2213 => x"83", + 2214 => x"77", + 2215 => x"0c", + 2216 => x"04", + 2217 => x"77", + 2218 => x"12", + 2219 => x"55", + 2220 => x"56", + 2221 => x"8d", + 2222 => x"22", + 2223 => x"ac", + 2224 => x"57", + 2225 => x"de", + 2226 => x"3d", + 2227 => x"3d", + 2228 => x"70", + 2229 => x"57", + 2230 => x"81", + 2231 => x"98", + 2232 => x"81", + 2233 => x"74", + 2234 => x"72", + 2235 => x"f5", + 2236 => x"24", + 2237 => x"81", + 2238 => x"81", + 2239 => x"83", + 2240 => x"38", + 2241 => x"76", + 2242 => x"70", + 2243 => x"16", + 2244 => x"74", + 2245 => x"96", + 2246 => x"c0", + 2247 => x"38", + 2248 => x"06", + 2249 => x"33", + 2250 => x"89", + 2251 => x"08", + 2252 => x"54", + 2253 => x"fc", + 2254 => x"de", + 2255 => x"fe", + 2256 => x"ff", + 2257 => x"11", + 2258 => x"2b", + 2259 => x"81", + 2260 => x"2a", + 2261 => x"51", + 2262 => x"e2", + 2263 => x"ff", + 2264 => x"da", + 2265 => x"2a", + 2266 => x"05", + 2267 => x"fc", + 2268 => x"de", + 2269 => x"c6", + 2270 => x"83", + 2271 => x"05", + 2272 => x"f9", + 2273 => x"de", + 2274 => x"ff", + 2275 => x"ae", + 2276 => x"2a", + 2277 => x"05", + 2278 => x"fc", + 2279 => x"de", + 2280 => x"38", + 2281 => x"83", + 2282 => x"05", + 2283 => x"f8", + 2284 => x"de", + 2285 => x"0a", + 2286 => x"39", + 2287 => x"81", + 2288 => x"89", + 2289 => x"f8", + 2290 => x"7c", + 2291 => x"56", + 2292 => x"77", + 2293 => x"38", + 2294 => x"08", + 2295 => x"38", + 2296 => x"72", + 2297 => x"9d", + 2298 => x"24", + 2299 => x"81", + 2300 => x"82", + 2301 => x"83", + 2302 => x"38", + 2303 => x"76", + 2304 => x"70", + 2305 => x"18", + 2306 => x"76", + 2307 => x"9e", + 2308 => x"c0", + 2309 => x"de", + 2310 => x"d9", + 2311 => x"ff", + 2312 => x"05", + 2313 => x"81", + 2314 => x"54", + 2315 => x"80", + 2316 => x"77", + 2317 => x"f0", + 2318 => x"8f", + 2319 => x"51", + 2320 => x"34", + 2321 => x"17", + 2322 => x"2a", + 2323 => x"05", + 2324 => x"fa", + 2325 => x"de", + 2326 => x"81", + 2327 => x"81", + 2328 => x"83", + 2329 => x"b4", + 2330 => x"2a", + 2331 => x"8f", + 2332 => x"2a", + 2333 => x"f0", + 2334 => x"06", + 2335 => x"72", + 2336 => x"ec", + 2337 => x"2a", + 2338 => x"05", + 2339 => x"fa", + 2340 => x"de", + 2341 => x"81", + 2342 => x"80", + 2343 => x"83", + 2344 => x"52", + 2345 => x"fe", + 2346 => x"b4", + 2347 => x"a4", + 2348 => x"76", + 2349 => x"17", + 2350 => x"75", + 2351 => x"3f", + 2352 => x"08", + 2353 => x"c0", + 2354 => x"77", + 2355 => x"77", + 2356 => x"fc", + 2357 => x"b4", + 2358 => x"51", + 2359 => x"c9", + 2360 => x"c0", + 2361 => x"06", + 2362 => x"72", + 2363 => x"3f", + 2364 => x"17", + 2365 => x"de", + 2366 => x"3d", + 2367 => x"3d", + 2368 => x"7e", + 2369 => x"56", + 2370 => x"75", + 2371 => x"74", + 2372 => x"27", + 2373 => x"80", + 2374 => x"ff", + 2375 => x"75", + 2376 => x"3f", + 2377 => x"08", + 2378 => x"c0", + 2379 => x"38", + 2380 => x"54", + 2381 => x"81", + 2382 => x"39", + 2383 => x"08", + 2384 => x"39", + 2385 => x"51", + 2386 => x"81", + 2387 => x"58", + 2388 => x"08", + 2389 => x"c7", + 2390 => x"c0", + 2391 => x"d2", + 2392 => x"c0", + 2393 => x"cf", + 2394 => x"74", + 2395 => x"fc", + 2396 => x"de", + 2397 => x"38", + 2398 => x"fe", + 2399 => x"08", + 2400 => x"74", + 2401 => x"38", + 2402 => x"17", + 2403 => x"33", + 2404 => x"73", + 2405 => x"77", + 2406 => x"26", + 2407 => x"80", + 2408 => x"de", + 2409 => x"3d", + 2410 => x"3d", + 2411 => x"71", + 2412 => x"5b", + 2413 => x"8c", + 2414 => x"77", + 2415 => x"38", + 2416 => x"78", + 2417 => x"81", + 2418 => x"79", + 2419 => x"f9", + 2420 => x"55", + 2421 => x"c0", + 2422 => x"e0", + 2423 => x"c0", + 2424 => x"de", + 2425 => x"2e", + 2426 => x"98", + 2427 => x"de", + 2428 => x"82", + 2429 => x"58", + 2430 => x"70", + 2431 => x"80", + 2432 => x"38", + 2433 => x"09", + 2434 => x"e2", + 2435 => x"56", + 2436 => x"76", + 2437 => x"82", + 2438 => x"7a", + 2439 => x"3f", + 2440 => x"de", + 2441 => x"2e", + 2442 => x"86", + 2443 => x"c0", + 2444 => x"de", + 2445 => x"70", + 2446 => x"07", + 2447 => x"7c", + 2448 => x"c0", + 2449 => x"51", + 2450 => x"81", + 2451 => x"de", + 2452 => x"2e", + 2453 => x"17", + 2454 => x"74", + 2455 => x"73", + 2456 => x"27", + 2457 => x"58", + 2458 => x"80", + 2459 => x"56", + 2460 => x"98", + 2461 => x"26", + 2462 => x"56", + 2463 => x"81", + 2464 => x"52", + 2465 => x"c6", + 2466 => x"c0", + 2467 => x"b8", + 2468 => x"81", + 2469 => x"81", + 2470 => x"06", + 2471 => x"de", + 2472 => x"81", + 2473 => x"09", + 2474 => x"72", + 2475 => x"70", + 2476 => x"51", + 2477 => x"80", + 2478 => x"78", + 2479 => x"06", + 2480 => x"73", + 2481 => x"39", + 2482 => x"52", + 2483 => x"f7", + 2484 => x"c0", + 2485 => x"c0", + 2486 => x"81", + 2487 => x"07", + 2488 => x"55", + 2489 => x"2e", + 2490 => x"80", + 2491 => x"75", + 2492 => x"76", + 2493 => x"3f", + 2494 => x"08", + 2495 => x"38", + 2496 => x"0c", + 2497 => x"fe", + 2498 => x"08", + 2499 => x"74", + 2500 => x"ff", + 2501 => x"0c", + 2502 => x"81", + 2503 => x"84", + 2504 => x"39", + 2505 => x"81", + 2506 => x"8c", + 2507 => x"8c", + 2508 => x"c0", + 2509 => x"39", + 2510 => x"55", + 2511 => x"c0", + 2512 => x"0d", + 2513 => x"0d", + 2514 => x"55", + 2515 => x"81", + 2516 => x"58", + 2517 => x"de", + 2518 => x"d8", + 2519 => x"74", + 2520 => x"3f", + 2521 => x"08", + 2522 => x"08", + 2523 => x"59", + 2524 => x"77", + 2525 => x"70", + 2526 => x"c8", + 2527 => x"84", + 2528 => x"56", + 2529 => x"58", + 2530 => x"97", + 2531 => x"75", + 2532 => x"52", + 2533 => x"51", + 2534 => x"81", + 2535 => x"80", + 2536 => x"8a", + 2537 => x"32", + 2538 => x"72", + 2539 => x"2a", + 2540 => x"56", + 2541 => x"c0", + 2542 => x"0d", + 2543 => x"0d", + 2544 => x"08", + 2545 => x"74", + 2546 => x"26", + 2547 => x"74", + 2548 => x"72", + 2549 => x"74", + 2550 => x"88", + 2551 => x"73", + 2552 => x"33", + 2553 => x"27", + 2554 => x"16", + 2555 => x"9b", + 2556 => x"2a", + 2557 => x"88", + 2558 => x"58", + 2559 => x"80", + 2560 => x"16", + 2561 => x"0c", + 2562 => x"8a", + 2563 => x"89", + 2564 => x"72", + 2565 => x"38", + 2566 => x"51", + 2567 => x"81", + 2568 => x"54", + 2569 => x"08", + 2570 => x"38", + 2571 => x"de", + 2572 => x"8b", + 2573 => x"08", + 2574 => x"08", + 2575 => x"82", + 2576 => x"74", + 2577 => x"cb", + 2578 => x"75", + 2579 => x"3f", + 2580 => x"08", + 2581 => x"73", + 2582 => x"98", + 2583 => x"82", + 2584 => x"2e", + 2585 => x"39", + 2586 => x"39", + 2587 => x"13", + 2588 => x"74", + 2589 => x"16", + 2590 => x"18", + 2591 => x"77", + 2592 => x"0c", + 2593 => x"04", + 2594 => x"7a", + 2595 => x"12", + 2596 => x"59", + 2597 => x"80", + 2598 => x"86", + 2599 => x"98", + 2600 => x"14", + 2601 => x"55", + 2602 => x"81", + 2603 => x"83", + 2604 => x"77", + 2605 => x"81", + 2606 => x"0c", + 2607 => x"55", + 2608 => x"76", + 2609 => x"17", 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x"c0", + 2669 => x"38", + 2670 => x"08", + 2671 => x"70", + 2672 => x"58", + 2673 => x"2e", + 2674 => x"83", + 2675 => x"81", + 2676 => x"55", + 2677 => x"81", + 2678 => x"07", + 2679 => x"2e", + 2680 => x"16", + 2681 => x"2e", + 2682 => x"88", + 2683 => x"81", + 2684 => x"56", + 2685 => x"51", + 2686 => x"81", + 2687 => x"54", + 2688 => x"08", + 2689 => x"9b", + 2690 => x"2e", + 2691 => x"83", + 2692 => x"73", + 2693 => x"0c", + 2694 => x"04", + 2695 => x"76", + 2696 => x"54", + 2697 => x"81", + 2698 => x"83", + 2699 => x"76", + 2700 => x"53", + 2701 => x"2e", + 2702 => x"90", + 2703 => x"51", + 2704 => x"81", + 2705 => x"90", + 2706 => x"53", + 2707 => x"c0", + 2708 => x"0d", + 2709 => x"0d", + 2710 => x"83", + 2711 => x"54", + 2712 => x"55", + 2713 => x"3f", + 2714 => x"51", + 2715 => x"2e", + 2716 => x"8b", + 2717 => x"2a", + 2718 => x"51", + 2719 => x"86", + 2720 => x"f7", + 2721 => x"7d", + 2722 => x"75", + 2723 => x"98", + 2724 => x"2e", + 2725 => x"98", + 2726 => x"78", + 2727 => x"3f", + 2728 => x"08", + 2729 => x"c0", + 2730 => x"38", + 2731 => x"70", + 2732 => x"73", + 2733 => x"58", + 2734 => x"8b", + 2735 => x"bf", + 2736 => x"ff", + 2737 => x"53", + 2738 => x"34", + 2739 => x"08", + 2740 => x"e5", + 2741 => x"81", + 2742 => x"2e", + 2743 => x"70", + 2744 => x"57", + 2745 => x"9e", + 2746 => x"2e", + 2747 => x"de", + 2748 => x"df", + 2749 => x"72", + 2750 => x"81", + 2751 => x"76", + 2752 => x"2e", + 2753 => x"52", + 2754 => x"fc", + 2755 => x"c0", + 2756 => x"de", + 2757 => x"38", + 2758 => x"fe", + 2759 => x"39", + 2760 => x"16", + 2761 => x"de", + 2762 => x"3d", + 2763 => x"3d", + 2764 => x"08", + 2765 => x"52", + 2766 => x"c5", + 2767 => x"c0", + 2768 => x"de", + 2769 => x"38", + 2770 => x"52", + 2771 => x"de", + 2772 => x"c0", + 2773 => x"de", + 2774 => x"38", + 2775 => x"de", + 2776 => x"9c", + 2777 => x"ea", + 2778 => x"53", + 2779 => x"9c", + 2780 => x"ea", + 2781 => x"0b", + 2782 => x"74", + 2783 => x"0c", + 2784 => x"04", + 2785 => x"75", + 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x"33", + 2904 => x"73", + 2905 => x"81", + 2906 => x"81", + 2907 => x"dc", + 2908 => x"70", + 2909 => x"07", + 2910 => x"73", + 2911 => x"b5", + 2912 => x"2e", + 2913 => x"83", + 2914 => x"76", + 2915 => x"07", + 2916 => x"2e", + 2917 => x"8b", + 2918 => x"77", + 2919 => x"30", + 2920 => x"71", + 2921 => x"53", + 2922 => x"55", + 2923 => x"38", + 2924 => x"5c", + 2925 => x"75", + 2926 => x"73", + 2927 => x"38", + 2928 => x"06", + 2929 => x"11", + 2930 => x"75", + 2931 => x"3f", + 2932 => x"08", + 2933 => x"38", + 2934 => x"33", + 2935 => x"54", + 2936 => x"e6", + 2937 => x"de", + 2938 => x"2e", + 2939 => x"ff", + 2940 => x"74", + 2941 => x"38", + 2942 => x"75", + 2943 => x"17", + 2944 => x"57", + 2945 => x"a7", + 2946 => x"81", + 2947 => x"e5", + 2948 => x"de", + 2949 => x"38", + 2950 => x"54", + 2951 => x"89", + 2952 => x"70", + 2953 => x"57", + 2954 => x"54", + 2955 => x"81", + 2956 => x"f7", + 2957 => x"7e", + 2958 => x"2e", + 2959 => x"33", + 2960 => x"e5", + 2961 => x"06", + 2962 => x"7a", + 2963 => x"a0", + 2964 => x"38", + 2965 => x"55", + 2966 => x"84", + 2967 => x"39", + 2968 => x"8b", + 2969 => x"7b", + 2970 => x"7a", + 2971 => x"3f", + 2972 => x"08", + 2973 => x"c0", + 2974 => x"38", + 2975 => x"52", + 2976 => x"aa", + 2977 => x"c0", + 2978 => x"de", + 2979 => x"c2", + 2980 => x"08", + 2981 => x"55", + 2982 => x"ff", + 2983 => x"15", + 2984 => x"54", + 2985 => x"34", + 2986 => x"70", + 2987 => x"81", + 2988 => x"58", + 2989 => x"8b", + 2990 => x"74", + 2991 => x"3f", + 2992 => x"08", + 2993 => x"38", + 2994 => x"51", + 2995 => x"ff", + 2996 => x"ab", + 2997 => x"55", + 2998 => x"bb", + 2999 => x"2e", + 3000 => x"80", + 3001 => x"85", + 3002 => x"06", + 3003 => x"58", + 3004 => x"80", + 3005 => x"75", + 3006 => x"73", + 3007 => x"b5", + 3008 => x"0b", + 3009 => x"80", + 3010 => x"39", + 3011 => x"54", + 3012 => x"85", + 3013 => x"75", + 3014 => x"81", + 3015 => x"73", + 3016 => x"1b", + 3017 => x"2a", + 3018 => x"51", + 3019 => x"80", + 3020 => x"90", + 3021 => x"ff", + 3022 => x"05", + 3023 => x"f5", + 3024 => x"de", + 3025 => x"1c", + 3026 => x"39", + 3027 => x"c0", + 3028 => x"0d", + 3029 => x"0d", + 3030 => x"7b", + 3031 => x"73", + 3032 => x"55", + 3033 => x"2e", + 3034 => x"75", + 3035 => x"57", + 3036 => x"26", + 3037 => x"ba", + 3038 => x"70", + 3039 => x"ba", + 3040 => x"06", + 3041 => x"73", + 3042 => x"70", + 3043 => x"51", + 3044 => x"89", + 3045 => x"82", + 3046 => x"ff", + 3047 => x"56", + 3048 => x"2e", + 3049 => x"80", + 3050 => x"a4", + 3051 => x"08", + 3052 => x"76", + 3053 => x"58", + 3054 => x"81", + 3055 => x"ff", + 3056 => x"53", + 3057 => x"26", + 3058 => x"13", + 3059 => x"06", + 3060 => x"9f", + 3061 => x"99", + 3062 => x"e0", + 3063 => x"ff", + 3064 => x"72", + 3065 => x"2a", + 3066 => x"72", + 3067 => x"06", + 3068 => x"ff", + 3069 => x"30", + 3070 => x"70", + 3071 => x"07", + 3072 => x"9f", + 3073 => x"54", + 3074 => x"80", + 3075 => x"81", + 3076 => x"59", + 3077 => x"25", + 3078 => x"8b", + 3079 => x"24", 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x"29", + 3139 => x"05", + 3140 => x"53", + 3141 => x"80", + 3142 => x"38", + 3143 => x"76", + 3144 => x"74", + 3145 => x"72", + 3146 => x"38", + 3147 => x"51", + 3148 => x"81", + 3149 => x"81", + 3150 => x"81", + 3151 => x"72", + 3152 => x"80", + 3153 => x"38", + 3154 => x"70", + 3155 => x"53", + 3156 => x"86", + 3157 => x"a7", + 3158 => x"34", + 3159 => x"34", + 3160 => x"14", + 3161 => x"b2", + 3162 => x"c0", + 3163 => x"06", + 3164 => x"54", + 3165 => x"72", + 3166 => x"76", + 3167 => x"38", + 3168 => x"70", + 3169 => x"53", + 3170 => x"85", + 3171 => x"70", + 3172 => x"5b", + 3173 => x"81", + 3174 => x"81", + 3175 => x"76", + 3176 => x"81", + 3177 => x"38", + 3178 => x"56", + 3179 => x"83", + 3180 => x"70", + 3181 => x"80", + 3182 => x"83", + 3183 => x"dc", + 3184 => x"de", + 3185 => x"76", + 3186 => x"05", + 3187 => x"16", + 3188 => x"56", + 3189 => x"d7", + 3190 => x"8d", + 3191 => x"72", + 3192 => x"54", + 3193 => x"57", + 3194 => x"95", + 3195 => x"73", + 3196 => x"3f", + 3197 => x"08", + 3198 => x"57", + 3199 => x"89", + 3200 => x"56", + 3201 => x"d7", + 3202 => x"76", + 3203 => x"f1", + 3204 => x"76", + 3205 => x"e9", + 3206 => x"51", + 3207 => x"81", + 3208 => x"83", + 3209 => x"53", + 3210 => x"2e", + 3211 => x"84", + 3212 => x"ca", + 3213 => x"da", + 3214 => x"c0", + 3215 => x"ff", + 3216 => x"8d", + 3217 => x"14", + 3218 => x"3f", + 3219 => x"08", + 3220 => x"15", + 3221 => x"14", + 3222 => x"34", + 3223 => x"33", + 3224 => x"81", + 3225 => x"54", + 3226 => x"72", + 3227 => x"91", + 3228 => x"ff", + 3229 => x"29", + 3230 => x"33", + 3231 => x"72", + 3232 => x"72", + 3233 => x"38", + 3234 => x"06", + 3235 => x"2e", + 3236 => x"56", + 3237 => x"80", + 3238 => x"da", + 3239 => x"de", + 3240 => x"81", + 3241 => x"88", + 3242 => x"8f", + 3243 => x"56", + 3244 => x"38", + 3245 => x"51", + 3246 => x"81", + 3247 => x"83", + 3248 => x"55", + 3249 => x"80", + 3250 => x"da", + 3251 => x"de", + 3252 => x"80", + 3253 => x"da", + 3254 => x"de", + 3255 => x"ff", + 3256 => x"8d", + 3257 => x"2e", + 3258 => x"88", + 3259 => x"14", + 3260 => x"05", + 3261 => x"75", + 3262 => x"38", + 3263 => x"52", + 3264 => x"51", + 3265 => x"3f", + 3266 => x"08", + 3267 => x"c0", + 3268 => x"82", + 3269 => x"de", + 3270 => x"ff", + 3271 => x"26", + 3272 => x"57", + 3273 => x"f5", + 3274 => x"82", + 3275 => x"f5", + 3276 => x"81", + 3277 => x"8d", + 3278 => x"2e", + 3279 => x"82", + 3280 => x"16", + 3281 => x"16", + 3282 => x"70", + 3283 => x"7a", + 3284 => x"0c", + 3285 => x"83", + 3286 => x"06", + 3287 => x"de", + 3288 => x"ae", + 3289 => x"c0", + 3290 => x"ff", + 3291 => x"56", + 3292 => x"38", + 3293 => x"38", + 3294 => x"51", + 3295 => x"81", + 3296 => x"a8", + 3297 => x"82", + 3298 => x"39", + 3299 => x"80", + 3300 => x"38", + 3301 => x"15", + 3302 => x"53", + 3303 => x"8d", + 3304 => x"15", + 3305 => x"76", + 3306 => x"51", + 3307 => x"13", + 3308 => x"8d", + 3309 => x"15", + 3310 => x"c5", + 3311 => x"90", + 3312 => x"0b", + 3313 => x"ff", + 3314 => x"15", + 3315 => x"2e", + 3316 => x"81", + 3317 => x"e4", + 3318 => x"b6", + 3319 => x"c0", + 3320 => x"ff", + 3321 => x"81", + 3322 => x"06", + 3323 => x"81", + 3324 => x"51", + 3325 => x"81", + 3326 => x"80", + 3327 => x"de", + 3328 => x"15", + 3329 => x"14", + 3330 => x"3f", + 3331 => x"08", + 3332 => x"06", + 3333 => x"d4", + 3334 => x"81", + 3335 => x"38", + 3336 => x"d8", + 3337 => x"de", + 3338 => x"8b", + 3339 => x"2e", + 3340 => x"b3", + 3341 => x"14", + 3342 => x"3f", + 3343 => x"08", + 3344 => x"e4", + 3345 => x"81", + 3346 => x"84", + 3347 => x"d7", + 3348 => x"de", + 3349 => x"15", + 3350 => x"14", + 3351 => x"3f", + 3352 => x"08", + 3353 => x"76", + 3354 => x"de", + 3355 => x"05", + 3356 => x"de", + 3357 => x"86", + 3358 => x"0b", + 3359 => x"80", + 3360 => x"de", + 3361 => x"3d", + 3362 => x"3d", + 3363 => x"89", + 3364 => x"2e", + 3365 => x"08", + 3366 => x"2e", + 3367 => x"33", + 3368 => x"2e", + 3369 => x"13", + 3370 => x"22", + 3371 => x"76", + 3372 => x"06", + 3373 => x"13", + 3374 => x"c0", + 3375 => x"c0", + 3376 => x"52", + 3377 => x"71", + 3378 => x"55", + 3379 => x"53", + 3380 => x"0c", + 3381 => x"de", + 3382 => x"3d", + 3383 => x"3d", + 3384 => x"05", + 3385 => x"89", + 3386 => x"52", + 3387 => x"3f", + 3388 => x"0b", + 3389 => x"08", + 3390 => x"81", + 3391 => x"84", + 3392 => x"dc", + 3393 => x"55", + 3394 => x"2e", + 3395 => x"74", + 3396 => x"73", + 3397 => x"38", + 3398 => x"78", + 3399 => x"54", + 3400 => x"92", + 3401 => x"89", + 3402 => x"84", + 3403 => x"b0", + 3404 => x"c0", + 3405 => x"81", + 3406 => x"88", + 3407 => x"eb", + 3408 => x"02", + 3409 => x"e7", + 3410 => x"59", + 3411 => x"80", + 3412 => x"38", + 3413 => x"70", + 3414 => x"d0", + 3415 => x"3d", + 3416 => x"58", + 3417 => x"81", + 3418 => x"55", + 3419 => x"08", + 3420 => x"7a", + 3421 => x"8c", + 3422 => x"56", + 3423 => x"81", + 3424 => x"55", + 3425 => x"08", + 3426 => x"80", + 3427 => x"70", + 3428 => x"57", + 3429 => x"83", + 3430 => x"77", + 3431 => x"73", + 3432 => x"ab", + 3433 => x"2e", + 3434 => x"84", + 3435 => x"06", + 3436 => x"51", + 3437 => x"81", + 3438 => x"55", + 3439 => x"b2", + 3440 => x"06", + 3441 => x"b8", + 3442 => x"2a", + 3443 => x"51", + 3444 => x"2e", + 3445 => x"55", + 3446 => x"77", + 3447 => x"74", + 3448 => x"77", + 3449 => x"81", + 3450 => x"73", + 3451 => x"af", + 3452 => x"7a", + 3453 => x"3f", + 3454 => x"08", + 3455 => x"b2", + 3456 => x"8e", + 3457 => x"ea", + 3458 => x"a0", + 3459 => x"34", + 3460 => x"52", + 3461 => x"bd", + 3462 => x"62", + 3463 => x"d4", + 3464 => x"54", + 3465 => x"15", + 3466 => x"2e", + 3467 => x"7a", + 3468 => x"51", + 3469 => x"75", + 3470 => x"d4", + 3471 => x"be", + 3472 => x"c0", + 3473 => x"de", + 3474 => x"ca", + 3475 => x"74", + 3476 => x"02", + 3477 => x"70", + 3478 => x"81", + 3479 => x"56", + 3480 => x"86", + 3481 => x"82", + 3482 => x"81", + 3483 => x"06", + 3484 => x"80", + 3485 => x"75", + 3486 => x"73", + 3487 => x"38", + 3488 => x"92", + 3489 => x"7a", + 3490 => x"3f", + 3491 => x"08", + 3492 => x"8c", + 3493 => x"55", + 3494 => x"08", + 3495 => x"77", + 3496 => x"81", + 3497 => x"73", + 3498 => x"38", + 3499 => x"07", + 3500 => x"11", + 3501 => x"0c", + 3502 => x"0c", + 3503 => x"52", + 3504 => x"3f", + 3505 => x"08", + 3506 => x"08", + 3507 => x"63", + 3508 => x"5a", + 3509 => x"81", + 3510 => x"81", + 3511 => x"8c", + 3512 => x"7a", + 3513 => x"17", + 3514 => x"23", + 3515 => x"34", + 3516 => x"1a", + 3517 => x"9c", + 3518 => x"0b", + 3519 => x"77", + 3520 => x"81", + 3521 => x"73", + 3522 => x"8d", + 3523 => x"c0", + 3524 => x"81", + 3525 => x"de", + 3526 => x"1a", + 3527 => x"22", + 3528 => x"7b", + 3529 => x"a8", + 3530 => x"78", + 3531 => x"3f", + 3532 => x"08", + 3533 => x"c0", + 3534 => x"83", + 3535 => x"81", + 3536 => x"ff", + 3537 => x"06", + 3538 => x"55", + 3539 => x"56", + 3540 => x"76", + 3541 => x"51", + 3542 => x"27", + 3543 => x"70", + 3544 => x"5a", + 3545 => x"76", + 3546 => x"74", + 3547 => x"83", + 3548 => x"73", + 3549 => x"38", + 3550 => x"51", + 3551 => x"81", + 3552 => x"85", + 3553 => x"8e", + 3554 => x"2a", + 3555 => x"08", + 3556 => x"0c", + 3557 => x"79", + 3558 => x"73", + 3559 => x"0c", + 3560 => x"04", + 3561 => x"60", + 3562 => x"40", + 3563 => x"80", + 3564 => x"3d", + 3565 => x"78", + 3566 => x"3f", + 3567 => x"08", + 3568 => x"c0", + 3569 => x"91", + 3570 => x"74", + 3571 => x"38", + 3572 => x"c4", + 3573 => x"33", + 3574 => x"87", + 3575 => x"2e", + 3576 => x"95", + 3577 => x"91", + 3578 => x"56", + 3579 => x"81", + 3580 => x"34", + 3581 => x"a0", + 3582 => x"08", + 3583 => x"31", + 3584 => x"27", + 3585 => x"5c", + 3586 => x"82", + 3587 => x"19", + 3588 => x"ff", + 3589 => x"74", + 3590 => x"7e", + 3591 => x"ff", + 3592 => x"2a", + 3593 => x"79", + 3594 => x"87", + 3595 => x"08", + 3596 => x"98", + 3597 => x"78", + 3598 => x"3f", + 3599 => x"08", + 3600 => x"27", + 3601 => x"74", + 3602 => x"a3", + 3603 => x"1a", + 3604 => x"08", + 3605 => x"d4", + 3606 => x"de", + 3607 => x"2e", + 3608 => x"81", + 3609 => x"1a", + 3610 => x"59", + 3611 => x"2e", + 3612 => x"77", + 3613 => x"11", + 3614 => x"55", + 3615 => x"85", + 3616 => x"31", + 3617 => x"76", + 3618 => x"81", + 3619 => x"ca", + 3620 => x"de", + 3621 => x"d7", + 3622 => x"11", + 3623 => x"74", + 3624 => x"38", + 3625 => x"77", + 3626 => x"78", + 3627 => x"84", + 3628 => x"16", + 3629 => x"08", + 3630 => x"2b", + 3631 => x"cf", + 3632 => x"89", + 3633 => x"39", + 3634 => x"0c", + 3635 => x"83", + 3636 => x"80", + 3637 => x"55", + 3638 => x"83", + 3639 => x"9c", + 3640 => x"7e", + 3641 => x"3f", + 3642 => x"08", + 3643 => x"75", + 3644 => x"08", + 3645 => x"1f", + 3646 => x"7c", + 3647 => x"3f", + 3648 => x"7e", + 3649 => x"0c", + 3650 => x"1b", + 3651 => x"1c", + 3652 => x"fd", + 3653 => x"56", + 3654 => x"c0", + 3655 => x"0d", + 3656 => x"0d", + 3657 => x"64", + 3658 => x"58", + 3659 => x"90", + 3660 => x"52", + 3661 => x"d2", + 3662 => x"c0", + 3663 => x"de", + 3664 => x"38", + 3665 => x"55", + 3666 => x"86", + 3667 => x"83", + 3668 => x"18", + 3669 => x"2a", + 3670 => x"51", + 3671 => x"56", + 3672 => x"83", + 3673 => x"39", + 3674 => x"19", + 3675 => x"83", + 3676 => x"0b", + 3677 => x"81", + 3678 => x"39", + 3679 => x"7c", + 3680 => x"74", + 3681 => x"38", + 3682 => x"7b", + 3683 => x"ec", + 3684 => x"08", + 3685 => x"06", + 3686 => x"81", + 3687 => x"8a", + 3688 => x"05", + 3689 => x"06", + 3690 => x"bf", + 3691 => x"38", + 3692 => x"55", + 3693 => x"7a", + 3694 => x"98", + 3695 => x"77", + 3696 => x"3f", + 3697 => x"08", + 3698 => x"c0", + 3699 => x"82", + 3700 => x"81", + 3701 => x"38", + 3702 => x"ff", + 3703 => x"98", + 3704 => x"18", + 3705 => x"74", + 3706 => x"7e", + 3707 => x"08", + 3708 => x"2e", + 3709 => x"8d", + 3710 => x"ce", + 3711 => x"de", + 3712 => x"ee", + 3713 => x"08", + 3714 => x"d1", + 3715 => x"de", + 3716 => x"2e", + 3717 => x"81", + 3718 => x"1b", + 3719 => x"5a", + 3720 => x"2e", + 3721 => x"78", + 3722 => x"11", + 3723 => x"55", + 3724 => x"85", + 3725 => x"31", + 3726 => x"76", + 3727 => x"81", + 3728 => x"c8", + 3729 => x"de", + 3730 => x"a6", + 3731 => x"11", + 3732 => x"56", + 3733 => x"27", + 3734 => x"80", + 3735 => x"08", + 3736 => x"2b", + 3737 => x"b4", + 3738 => x"b5", + 3739 => x"80", + 3740 => x"34", + 3741 => x"56", + 3742 => x"8c", + 3743 => x"19", + 3744 => x"38", + 3745 => x"b6", + 3746 => x"c0", + 3747 => x"38", + 3748 => x"12", + 3749 => x"9c", + 3750 => x"18", + 3751 => x"06", + 3752 => x"31", + 3753 => x"76", + 3754 => x"7b", + 3755 => x"08", + 3756 => x"cd", + 3757 => x"de", + 3758 => x"b6", + 3759 => x"7c", + 3760 => x"08", + 3761 => x"1f", + 3762 => x"cb", + 3763 => x"55", + 3764 => x"16", + 3765 => x"31", + 3766 => x"7f", + 3767 => x"94", + 3768 => x"70", + 3769 => x"8c", + 3770 => x"58", + 3771 => x"76", + 3772 => x"75", + 3773 => x"19", + 3774 => x"39", + 3775 => x"80", + 3776 => x"74", + 3777 => x"80", + 3778 => x"de", + 3779 => x"3d", + 3780 => x"3d", + 3781 => x"3d", + 3782 => x"70", + 3783 => x"ea", + 3784 => x"c0", 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x"04", + 3844 => x"80", + 3845 => x"d0", + 3846 => x"3d", + 3847 => x"3f", + 3848 => x"08", + 3849 => x"c0", + 3850 => x"38", + 3851 => x"52", + 3852 => x"05", + 3853 => x"3f", + 3854 => x"08", + 3855 => x"c0", + 3856 => x"02", + 3857 => x"33", + 3858 => x"55", + 3859 => x"25", + 3860 => x"7a", + 3861 => x"54", + 3862 => x"a2", + 3863 => x"84", + 3864 => x"06", + 3865 => x"73", + 3866 => x"38", + 3867 => x"70", + 3868 => x"a8", + 3869 => x"c0", + 3870 => x"0c", + 3871 => x"de", + 3872 => x"2e", + 3873 => x"83", + 3874 => x"74", + 3875 => x"0c", + 3876 => x"04", + 3877 => x"6f", + 3878 => x"80", + 3879 => x"53", + 3880 => x"b8", + 3881 => x"3d", + 3882 => x"3f", + 3883 => x"08", + 3884 => x"c0", + 3885 => x"38", + 3886 => x"7c", + 3887 => x"47", + 3888 => x"54", + 3889 => x"81", + 3890 => x"52", + 3891 => x"52", + 3892 => x"3f", + 3893 => x"08", + 3894 => x"c0", + 3895 => x"38", + 3896 => x"51", + 3897 => x"81", + 3898 => x"57", + 3899 => x"08", + 3900 => x"69", + 3901 => x"da", + 3902 => x"de", + 3903 => x"76", + 3904 => x"d5", + 3905 => x"de", + 3906 => x"81", + 3907 => x"82", + 3908 => x"52", + 3909 => x"eb", + 3910 => x"c0", + 3911 => x"de", + 3912 => x"38", + 3913 => x"51", + 3914 => x"73", + 3915 => x"08", + 3916 => x"76", + 3917 => x"d6", + 3918 => x"de", + 3919 => x"81", + 3920 => x"80", + 3921 => x"76", + 3922 => x"81", + 3923 => x"82", + 3924 => x"39", + 3925 => x"38", + 3926 => x"bc", + 3927 => x"51", + 3928 => x"76", + 3929 => x"11", + 3930 => x"51", + 3931 => x"73", + 3932 => x"38", + 3933 => x"55", + 3934 => x"16", + 3935 => x"56", + 3936 => x"38", + 3937 => x"73", + 3938 => x"90", + 3939 => x"2e", + 3940 => x"16", + 3941 => x"ff", + 3942 => x"ff", + 3943 => x"58", + 3944 => x"74", + 3945 => x"75", + 3946 => x"18", + 3947 => x"58", + 3948 => x"fe", + 3949 => x"7b", + 3950 => x"06", + 3951 => x"18", + 3952 => x"58", + 3953 => x"80", + 3954 => x"f0", + 3955 => x"29", + 3956 => x"05", + 3957 => x"33", + 3958 => x"56", + 3959 => x"2e", + 3960 => x"16", + 3961 => x"33", + 3962 => x"73", + 3963 => x"16", + 3964 => x"26", + 3965 => x"55", + 3966 => x"91", + 3967 => x"54", + 3968 => x"70", + 3969 => x"34", + 3970 => x"ec", + 3971 => x"70", + 3972 => x"34", + 3973 => x"09", + 3974 => x"38", + 3975 => x"39", + 3976 => x"19", + 3977 => x"33", + 3978 => x"05", + 3979 => x"78", + 3980 => x"80", + 3981 => x"81", + 3982 => x"9e", + 3983 => x"f7", + 3984 => x"7d", + 3985 => x"05", + 3986 => x"57", + 3987 => x"3f", + 3988 => x"08", + 3989 => x"c0", + 3990 => x"38", + 3991 => x"53", + 3992 => x"38", + 3993 => x"54", + 3994 => x"92", + 3995 => x"33", + 3996 => x"70", + 3997 => x"54", + 3998 => x"38", + 3999 => x"15", + 4000 => x"70", + 4001 => x"58", + 4002 => x"82", + 4003 => x"8a", + 4004 => x"89", + 4005 => x"53", + 4006 => x"b7", + 4007 => x"ff", + 4008 => x"95", + 4009 => x"de", + 4010 => x"15", + 4011 => x"53", + 4012 => x"95", + 4013 => x"de", + 4014 => x"26", + 4015 => x"30", + 4016 => x"70", + 4017 => x"77", + 4018 => x"18", + 4019 => x"51", + 4020 => x"88", + 4021 => x"73", + 4022 => x"52", + 4023 => x"ca", + 4024 => x"c0", + 4025 => x"de", + 4026 => x"2e", + 4027 => x"81", + 4028 => x"ff", + 4029 => x"38", + 4030 => x"08", + 4031 => x"73", + 4032 => x"73", + 4033 => x"9c", + 4034 => x"27", + 4035 => x"75", + 4036 => x"16", + 4037 => x"17", + 4038 => x"33", + 4039 => x"70", + 4040 => x"55", + 4041 => x"80", + 4042 => x"73", + 4043 => x"cc", + 4044 => x"de", + 4045 => x"81", + 4046 => x"94", + 4047 => x"c0", + 4048 => x"39", + 4049 => x"51", + 4050 => x"81", + 4051 => x"54", + 4052 => x"be", + 4053 => x"27", + 4054 => x"53", + 4055 => x"08", + 4056 => x"73", + 4057 => x"ff", + 4058 => x"15", + 4059 => x"16", + 4060 => x"ff", + 4061 => x"80", + 4062 => x"73", + 4063 => x"c6", + 4064 => x"de", + 4065 => x"38", + 4066 => x"16", + 4067 => x"80", + 4068 => x"0b", + 4069 => x"81", + 4070 => x"75", + 4071 => x"de", + 4072 => x"58", + 4073 => x"54", + 4074 => x"74", + 4075 => x"73", + 4076 => x"90", + 4077 => x"c0", + 4078 => x"90", + 4079 => x"83", + 4080 => x"72", + 4081 => x"38", + 4082 => x"08", + 4083 => x"77", + 4084 => x"80", + 4085 => x"de", + 4086 => x"3d", + 4087 => x"3d", + 4088 => x"89", + 4089 => x"2e", + 4090 => x"80", + 4091 => x"fc", + 4092 => x"3d", + 4093 => x"e1", + 4094 => x"de", + 4095 => x"81", + 4096 => x"80", + 4097 => x"76", + 4098 => x"75", + 4099 => x"3f", + 4100 => x"08", + 4101 => x"c0", + 4102 => x"38", + 4103 => x"70", + 4104 => x"57", + 4105 => x"a2", + 4106 => x"33", + 4107 => x"70", + 4108 => x"55", + 4109 => x"2e", + 4110 => x"16", + 4111 => x"51", + 4112 => x"81", + 4113 => x"88", + 4114 => x"54", + 4115 => x"84", + 4116 => x"52", + 4117 => x"e5", + 4118 => x"c0", + 4119 => x"84", + 4120 => x"06", + 4121 => x"55", + 4122 => x"80", + 4123 => x"80", + 4124 => x"54", + 4125 => x"c0", + 4126 => x"0d", + 4127 => x"0d", + 4128 => x"fc", + 4129 => x"52", + 4130 => x"3f", + 4131 => x"08", + 4132 => x"de", + 4133 => x"0c", + 4134 => x"04", + 4135 => x"77", + 4136 => x"fc", + 4137 => x"53", + 4138 => x"de", + 4139 => x"c0", + 4140 => x"de", + 4141 => x"df", + 4142 => x"38", + 4143 => x"08", + 4144 => x"cd", + 4145 => x"de", + 4146 => x"80", + 4147 => x"de", + 4148 => x"73", + 4149 => x"3f", + 4150 => x"08", + 4151 => x"c0", + 4152 => x"09", + 4153 => x"38", + 4154 => x"39", + 4155 => x"08", + 4156 => x"52", + 4157 => x"b3", + 4158 => x"73", + 4159 => x"3f", + 4160 => x"08", + 4161 => x"30", + 4162 => x"9f", + 4163 => x"de", + 4164 => x"51", + 4165 => x"72", + 4166 => x"0c", + 4167 => x"04", + 4168 => x"65", + 4169 => x"89", + 4170 => x"96", + 4171 => x"df", + 4172 => x"de", + 4173 => x"81", + 4174 => x"b2", + 4175 => x"75", + 4176 => x"3f", + 4177 => x"08", + 4178 => x"c0", + 4179 => x"02", + 4180 => x"33", + 4181 => x"55", + 4182 => x"25", + 4183 => x"55", + 4184 => x"80", + 4185 => x"76", + 4186 => x"d4", + 4187 => x"81", + 4188 => x"94", + 4189 => x"f0", + 4190 => x"65", + 4191 => x"53", + 4192 => x"05", + 4193 => x"51", + 4194 => x"81", + 4195 => x"5b", + 4196 => x"08", + 4197 => x"7c", + 4198 => x"08", + 4199 => x"fe", + 4200 => x"08", + 4201 => x"55", + 4202 => x"91", + 4203 => x"0c", + 4204 => x"81", + 4205 => x"39", + 4206 => x"c7", + 4207 => x"c0", + 4208 => x"55", + 4209 => x"2e", + 4210 => x"bf", + 4211 => x"5f", + 4212 => x"92", + 4213 => x"51", + 4214 => x"81", + 4215 => x"ff", + 4216 => x"81", + 4217 => x"81", + 4218 => x"81", + 4219 => x"30", + 4220 => x"c0", + 4221 => x"25", + 4222 => x"19", + 4223 => x"5a", + 4224 => x"08", + 4225 => x"38", + 4226 => x"a4", + 4227 => x"de", + 4228 => x"58", + 4229 => x"77", + 4230 => x"7d", + 4231 => x"bf", + 4232 => x"de", + 4233 => x"81", + 4234 => x"80", + 4235 => x"70", + 4236 => x"ff", + 4237 => x"56", + 4238 => x"2e", + 4239 => x"9e", + 4240 => x"51", + 4241 => x"3f", + 4242 => x"08", + 4243 => x"06", + 4244 => x"80", + 4245 => x"19", + 4246 => x"54", + 4247 => x"14", + 4248 => x"c5", + 4249 => x"c0", + 4250 => x"06", + 4251 => x"80", + 4252 => x"19", + 4253 => x"54", + 4254 => x"06", + 4255 => x"79", + 4256 => x"78", + 4257 => x"79", + 4258 => x"84", + 4259 => x"07", + 4260 => x"84", + 4261 => x"81", + 4262 => x"92", + 4263 => x"f9", + 4264 => x"8a", + 4265 => x"53", + 4266 => x"e3", + 4267 => x"de", + 4268 => x"81", + 4269 => x"81", + 4270 => x"17", + 4271 => x"81", + 4272 => x"17", + 4273 => x"2a", + 4274 => x"51", + 4275 => x"55", + 4276 => x"81", + 4277 => x"17", + 4278 => x"8c", + 4279 => x"81", + 4280 => x"9b", + 4281 => x"c0", + 4282 => x"17", + 4283 => x"51", + 4284 => x"81", + 4285 => x"74", + 4286 => x"56", + 4287 => x"98", + 4288 => x"76", + 4289 => x"c6", + 4290 => x"c0", + 4291 => x"09", + 4292 => x"38", + 4293 => x"de", + 4294 => x"2e", + 4295 => x"85", + 4296 => x"a3", + 4297 => x"38", + 4298 => x"de", + 4299 => x"15", + 4300 => x"38", + 4301 => x"53", + 4302 => x"08", + 4303 => x"c3", + 4304 => x"de", + 4305 => x"94", + 4306 => x"18", + 4307 => x"33", + 4308 => x"54", + 4309 => x"34", + 4310 => x"85", + 4311 => x"18", + 4312 => x"74", + 4313 => x"0c", + 4314 => x"04", + 4315 => x"82", + 4316 => x"ff", + 4317 => x"a1", + 4318 => x"e4", + 4319 => x"c0", + 4320 => x"de", + 4321 => x"f5", + 4322 => x"a1", + 4323 => x"95", + 4324 => x"58", + 4325 => x"81", + 4326 => x"55", + 4327 => x"08", + 4328 => x"02", + 4329 => x"33", + 4330 => x"70", + 4331 => x"55", + 4332 => x"73", + 4333 => x"75", + 4334 => x"80", + 4335 => x"bd", + 4336 => x"d6", + 4337 => x"81", + 4338 => x"87", + 4339 => x"ad", + 4340 => x"78", + 4341 => x"3f", + 4342 => x"08", + 4343 => x"70", + 4344 => x"55", + 4345 => x"2e", + 4346 => x"78", + 4347 => x"c0", + 4348 => x"08", + 4349 => x"38", + 4350 => x"de", + 4351 => x"76", + 4352 => x"70", + 4353 => x"b5", + 4354 => x"c0", + 4355 => x"de", + 4356 => x"e9", + 4357 => x"c0", + 4358 => x"51", + 4359 => x"81", + 4360 => x"55", + 4361 => x"08", + 4362 => x"55", + 4363 => x"81", + 4364 => x"84", + 4365 => x"81", + 4366 => x"80", + 4367 => x"51", + 4368 => x"81", + 4369 => x"81", + 4370 => x"30", + 4371 => x"c0", + 4372 => x"25", + 4373 => x"75", + 4374 => x"38", + 4375 => x"8f", + 4376 => x"75", + 4377 => x"c1", + 4378 => x"de", + 4379 => x"74", + 4380 => x"51", + 4381 => x"3f", + 4382 => x"08", + 4383 => x"de", + 4384 => x"3d", + 4385 => x"3d", + 4386 => x"99", + 4387 => x"52", + 4388 => x"d8", + 4389 => x"de", + 4390 => x"81", + 4391 => x"82", + 4392 => x"5e", + 4393 => x"3d", + 4394 => x"cf", + 4395 => x"de", + 4396 => x"81", + 4397 => x"86", + 4398 => x"82", + 4399 => x"de", + 4400 => x"2e", + 4401 => x"82", + 4402 => x"80", + 4403 => x"70", + 4404 => x"06", + 4405 => x"54", + 4406 => x"38", + 4407 => x"52", + 4408 => x"52", + 4409 => x"3f", + 4410 => x"08", + 4411 => x"81", + 4412 => x"83", + 4413 => x"81", + 4414 => x"81", + 4415 => x"06", + 4416 => x"54", + 4417 => x"08", + 4418 => x"81", + 4419 => x"81", + 4420 => x"39", + 4421 => x"38", + 4422 => x"08", + 4423 => x"c4", + 4424 => x"de", + 4425 => x"81", + 4426 => x"81", + 4427 => x"53", + 4428 => x"19", + 4429 => x"8c", + 4430 => x"ae", + 4431 => x"34", + 4432 => x"0b", + 4433 => x"82", + 4434 => x"52", + 4435 => x"51", + 4436 => x"3f", + 4437 => x"b4", + 4438 => x"c9", + 4439 => x"53", + 4440 => x"53", + 4441 => x"51", + 4442 => x"3f", + 4443 => x"0b", + 4444 => x"34", + 4445 => x"80", + 4446 => x"51", + 4447 => x"78", + 4448 => x"83", + 4449 => x"51", + 4450 => x"81", + 4451 => x"54", + 4452 => x"08", + 4453 => x"88", + 4454 => x"64", + 4455 => x"ff", + 4456 => x"75", + 4457 => x"78", + 4458 => x"3f", + 4459 => x"0b", + 4460 => x"78", + 4461 => x"83", + 4462 => x"51", + 4463 => x"3f", + 4464 => x"08", + 4465 => x"80", + 4466 => x"76", + 4467 => x"ae", + 4468 => x"de", + 4469 => x"3d", + 4470 => x"3d", + 4471 => x"84", + 4472 => x"f1", + 4473 => x"a8", + 4474 => x"05", + 4475 => x"51", + 4476 => x"81", + 4477 => x"55", + 4478 => x"08", + 4479 => x"78", + 4480 => x"08", + 4481 => x"70", + 4482 => x"b8", + 4483 => x"c0", + 4484 => x"de", + 4485 => x"b9", + 4486 => x"9b", + 4487 => x"a0", + 4488 => x"55", + 4489 => x"38", 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x"16", + 4549 => x"ae", + 4550 => x"06", + 4551 => x"53", + 4552 => x"51", + 4553 => x"78", + 4554 => x"83", + 4555 => x"39", + 4556 => x"08", + 4557 => x"51", + 4558 => x"81", + 4559 => x"55", + 4560 => x"08", + 4561 => x"51", + 4562 => x"3f", + 4563 => x"08", + 4564 => x"de", + 4565 => x"3d", + 4566 => x"3d", + 4567 => x"db", + 4568 => x"84", + 4569 => x"05", + 4570 => x"82", + 4571 => x"d0", + 4572 => x"3d", + 4573 => x"3f", + 4574 => x"08", + 4575 => x"c0", + 4576 => x"38", + 4577 => x"52", + 4578 => x"05", + 4579 => x"3f", + 4580 => x"08", + 4581 => x"c0", + 4582 => x"02", + 4583 => x"33", + 4584 => x"54", + 4585 => x"aa", + 4586 => x"06", + 4587 => x"8b", + 4588 => x"06", + 4589 => x"07", + 4590 => x"56", + 4591 => x"34", + 4592 => x"0b", + 4593 => x"78", + 4594 => x"a9", + 4595 => x"c0", + 4596 => x"81", + 4597 => x"95", + 4598 => x"ef", + 4599 => x"56", + 4600 => x"3d", + 4601 => x"94", + 4602 => x"f4", + 4603 => x"c0", + 4604 => x"de", + 4605 => x"cb", + 4606 => x"63", + 4607 => x"d4", + 4608 => x"c0", + 4609 => x"c0", + 4610 => x"de", + 4611 => x"38", + 4612 => x"05", + 4613 => x"06", + 4614 => x"73", + 4615 => x"16", + 4616 => x"22", + 4617 => x"07", + 4618 => x"1f", + 4619 => x"c2", + 4620 => x"81", + 4621 => x"34", + 4622 => x"b3", + 4623 => x"de", + 4624 => x"74", + 4625 => x"0c", + 4626 => x"04", + 4627 => x"69", + 4628 => x"80", + 4629 => x"d0", + 4630 => x"3d", + 4631 => x"3f", + 4632 => x"08", + 4633 => x"08", + 4634 => x"de", + 4635 => x"80", + 4636 => x"57", + 4637 => x"81", + 4638 => x"70", + 4639 => x"55", + 4640 => x"80", + 4641 => x"5d", + 4642 => x"52", + 4643 => x"52", + 4644 => x"a9", + 4645 => x"c0", + 4646 => x"de", + 4647 => x"d1", + 4648 => x"73", + 4649 => x"3f", + 4650 => x"08", + 4651 => x"c0", + 4652 => x"81", + 4653 => x"81", + 4654 => x"65", + 4655 => x"78", + 4656 => x"7b", + 4657 => x"55", + 4658 => x"34", + 4659 => x"8a", + 4660 => x"38", + 4661 => x"1a", + 4662 => x"34", + 4663 => x"9e", + 4664 => x"70", + 4665 => x"51", + 4666 => x"a0", + 4667 => x"8e", + 4668 => x"2e", + 4669 => x"86", + 4670 => x"34", + 4671 => x"30", + 4672 => x"80", + 4673 => x"7a", + 4674 => x"c1", + 4675 => x"2e", + 4676 => x"a0", + 4677 => x"51", + 4678 => x"3f", + 4679 => x"08", + 4680 => x"c0", + 4681 => x"7b", + 4682 => x"55", + 4683 => x"73", + 4684 => x"38", + 4685 => x"73", + 4686 => x"38", + 4687 => x"15", + 4688 => x"ff", + 4689 => x"81", + 4690 => x"7b", + 4691 => x"de", + 4692 => x"3d", + 4693 => x"3d", + 4694 => x"9c", + 4695 => x"05", + 4696 => x"51", + 4697 => x"81", + 4698 => x"81", + 4699 => x"56", + 4700 => x"c0", + 4701 => x"38", + 4702 => x"52", + 4703 => x"52", + 4704 => x"c0", + 4705 => x"70", + 4706 => x"ff", + 4707 => x"55", + 4708 => x"27", + 4709 => x"78", + 4710 => x"ff", + 4711 => x"05", + 4712 => x"55", + 4713 => x"3f", + 4714 => x"08", + 4715 => x"38", + 4716 => x"70", + 4717 => x"ff", + 4718 => x"81", + 4719 => x"80", + 4720 => x"74", + 4721 => x"07", + 4722 => x"4e", + 4723 => x"81", + 4724 => x"55", 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x"80", + 4784 => x"54", + 4785 => x"80", + 4786 => x"52", + 4787 => x"bd", + 4788 => x"de", + 4789 => x"81", + 4790 => x"b1", + 4791 => x"81", + 4792 => x"52", + 4793 => x"ab", + 4794 => x"54", + 4795 => x"15", + 4796 => x"78", + 4797 => x"ff", + 4798 => x"79", + 4799 => x"83", + 4800 => x"51", + 4801 => x"3f", + 4802 => x"08", + 4803 => x"74", + 4804 => x"0c", + 4805 => x"04", + 4806 => x"60", + 4807 => x"05", + 4808 => x"33", + 4809 => x"05", + 4810 => x"40", + 4811 => x"da", + 4812 => x"c0", + 4813 => x"de", + 4814 => x"bd", + 4815 => x"33", + 4816 => x"b5", + 4817 => x"2e", + 4818 => x"1a", + 4819 => x"90", + 4820 => x"33", + 4821 => x"70", + 4822 => x"55", + 4823 => x"38", + 4824 => x"97", + 4825 => x"82", + 4826 => x"58", + 4827 => x"7e", + 4828 => x"70", + 4829 => x"55", + 4830 => x"56", + 4831 => x"f7", + 4832 => x"7d", + 4833 => x"70", + 4834 => x"2a", + 4835 => x"08", + 4836 => x"08", + 4837 => x"5d", + 4838 => x"77", + 4839 => x"98", + 4840 => x"26", + 4841 => x"57", + 4842 => x"59", + 4843 => x"52", + 4844 => x"ae", + 4845 => x"15", + 4846 => x"98", + 4847 => x"26", + 4848 => x"55", + 4849 => x"08", + 4850 => x"99", + 4851 => x"c0", + 4852 => x"ff", + 4853 => x"de", + 4854 => x"38", + 4855 => x"75", + 4856 => x"81", + 4857 => x"93", + 4858 => x"80", + 4859 => x"2e", + 4860 => x"ff", + 4861 => x"58", + 4862 => x"7d", + 4863 => x"38", + 4864 => x"55", + 4865 => x"b4", + 4866 => x"56", + 4867 => x"09", + 4868 => x"38", + 4869 => x"53", + 4870 => x"51", + 4871 => x"3f", + 4872 => x"08", + 4873 => x"c0", + 4874 => x"38", + 4875 => x"ff", + 4876 => x"5c", + 4877 => x"84", + 4878 => x"5c", + 4879 => x"12", + 4880 => x"80", + 4881 => x"78", + 4882 => x"7c", + 4883 => x"90", + 4884 => x"c0", + 4885 => x"90", + 4886 => x"15", + 4887 => x"90", + 4888 => x"54", + 4889 => x"91", + 4890 => x"31", + 4891 => x"84", + 4892 => x"07", + 4893 => x"16", + 4894 => x"73", + 4895 => x"0c", + 4896 => x"04", + 4897 => x"6b", + 4898 => x"05", + 4899 => x"33", + 4900 => x"5a", + 4901 => x"bd", + 4902 => x"80", + 4903 => x"c0", + 4904 => x"f8", + 4905 => x"c0", + 4906 => x"81", + 4907 => x"70", + 4908 => x"74", + 4909 => x"38", + 4910 => x"81", + 4911 => x"81", + 4912 => x"81", + 4913 => x"ff", + 4914 => x"81", + 4915 => x"81", + 4916 => x"81", + 4917 => x"83", + 4918 => x"c0", + 4919 => x"2a", + 4920 => x"51", + 4921 => x"74", + 4922 => x"99", + 4923 => x"53", + 4924 => x"51", + 4925 => x"3f", + 4926 => x"08", + 4927 => x"55", + 4928 => x"92", + 4929 => x"80", + 4930 => x"38", + 4931 => x"06", + 4932 => x"2e", + 4933 => x"48", + 4934 => x"87", + 4935 => x"79", + 4936 => x"78", + 4937 => x"26", + 4938 => x"19", + 4939 => x"74", + 4940 => x"38", + 4941 => x"e4", + 4942 => x"2a", + 4943 => x"70", + 4944 => x"59", + 4945 => x"7a", + 4946 => x"56", + 4947 => x"80", + 4948 => x"51", + 4949 => x"74", + 4950 => x"99", + 4951 => x"53", + 4952 => x"51", + 4953 => x"3f", + 4954 => x"de", + 4955 => x"ac", + 4956 => x"2a", + 4957 => x"81", + 4958 => x"43", + 4959 => x"83", + 4960 => x"66", + 4961 => x"60", + 4962 => x"90", + 4963 => x"31", + 4964 => x"80", + 4965 => x"8a", + 4966 => x"56", + 4967 => x"26", + 4968 => x"77", + 4969 => x"81", + 4970 => x"74", + 4971 => x"38", + 4972 => x"55", + 4973 => x"83", + 4974 => x"81", + 4975 => x"80", + 4976 => x"38", + 4977 => x"55", + 4978 => x"5e", + 4979 => x"89", + 4980 => x"5a", + 4981 => x"09", + 4982 => x"e1", + 4983 => x"38", + 4984 => x"57", + 4985 => x"ce", + 4986 => x"5a", + 4987 => x"9d", + 4988 => x"26", + 4989 => x"ce", + 4990 => x"10", + 4991 => x"22", + 4992 => x"74", + 4993 => x"38", + 4994 => x"ee", + 4995 => x"66", + 4996 => x"e3", + 4997 => x"c0", + 4998 => x"84", + 4999 => x"89", + 5000 => x"a0", + 5001 => x"81", + 5002 => x"fc", + 5003 => x"56", + 5004 => x"f0", + 5005 => x"80", + 5006 => x"d3", + 5007 => x"38", + 5008 => x"57", + 5009 => x"ce", + 5010 => x"5a", + 5011 => x"9d", + 5012 => x"26", + 5013 => x"ce", + 5014 => x"10", + 5015 => x"22", + 5016 => x"74", + 5017 => x"38", + 5018 => x"ee", + 5019 => x"66", + 5020 => x"83", + 5021 => x"c0", + 5022 => x"05", + 5023 => x"c0", + 5024 => x"26", + 5025 => x"0b", + 5026 => x"08", + 5027 => x"c0", + 5028 => x"11", + 5029 => x"05", + 5030 => x"83", + 5031 => x"2a", + 5032 => x"a0", + 5033 => x"7d", + 5034 => x"69", + 5035 => x"05", + 5036 => x"72", + 5037 => x"5c", + 5038 => x"59", + 5039 => x"2e", + 5040 => x"89", + 5041 => x"60", + 5042 => x"84", + 5043 => x"5d", + 5044 => x"18", + 5045 => x"68", + 5046 => x"74", + 5047 => x"af", + 5048 => x"31", + 5049 => x"53", + 5050 => x"52", + 5051 => x"87", + 5052 => x"c0", + 5053 => x"83", + 5054 => x"06", + 5055 => x"de", + 5056 => x"ff", + 5057 => x"dd", + 5058 => x"83", + 5059 => x"2a", + 5060 => x"be", + 5061 => x"39", + 5062 => x"09", + 5063 => x"c5", + 5064 => x"f5", + 5065 => x"c0", + 5066 => x"38", + 5067 => x"79", + 5068 => x"80", + 5069 => x"38", + 5070 => x"96", + 5071 => x"06", + 5072 => x"2e", + 5073 => x"5e", + 5074 => x"81", + 5075 => x"9f", + 5076 => x"38", + 5077 => x"38", + 5078 => x"81", + 5079 => x"fc", + 5080 => x"ab", + 5081 => x"7d", + 5082 => x"81", + 5083 => x"7d", + 5084 => x"78", + 5085 => x"74", + 5086 => x"8e", + 5087 => x"9c", + 5088 => x"53", + 5089 => x"51", + 5090 => x"3f", + 5091 => x"cc", + 5092 => x"51", + 5093 => x"3f", + 5094 => x"8b", + 5095 => x"a1", + 5096 => x"8d", + 5097 => x"83", + 5098 => x"52", + 5099 => x"ff", + 5100 => x"81", + 5101 => x"34", + 5102 => x"70", + 5103 => x"2a", + 5104 => x"54", + 5105 => x"1b", + 5106 => x"88", + 5107 => x"74", + 5108 => x"26", + 5109 => x"83", + 5110 => x"52", + 5111 => x"ff", + 5112 => x"8a", + 5113 => x"a0", + 5114 => x"a1", + 5115 => x"0b", + 5116 => x"bf", + 5117 => x"51", + 5118 => x"3f", + 5119 => x"9a", + 5120 => x"a0", + 5121 => x"52", + 5122 => x"ff", + 5123 => x"7d", + 5124 => x"81", + 5125 => x"38", + 5126 => x"0a", + 5127 => x"1b", + 5128 => x"ce", + 5129 => x"a4", + 5130 => x"a0", + 5131 => x"52", + 5132 => x"ff", + 5133 => x"81", + 5134 => x"51", + 5135 => x"3f", + 5136 => x"1b", + 5137 => x"8c", + 5138 => x"0b", + 5139 => x"34", + 5140 => x"c2", + 5141 => x"53", + 5142 => x"52", + 5143 => x"51", + 5144 => x"88", + 5145 => x"a7", + 5146 => x"a0", + 5147 => x"83", + 5148 => x"52", + 5149 => x"ff", + 5150 => x"ff", + 5151 => x"1c", + 5152 => x"a6", + 5153 => x"53", + 5154 => x"52", + 5155 => x"ff", + 5156 => x"82", + 5157 => x"83", + 5158 => x"52", + 5159 => x"b4", + 5160 => x"60", + 5161 => x"7e", + 5162 => x"d7", + 5163 => x"81", + 5164 => x"83", + 5165 => x"83", + 5166 => x"06", + 5167 => x"75", + 5168 => x"05", + 5169 => x"7e", + 5170 => x"b7", + 5171 => x"53", + 5172 => x"51", + 5173 => x"3f", + 5174 => x"a4", + 5175 => x"51", + 5176 => x"3f", + 5177 => x"e4", + 5178 => x"e4", + 5179 => x"9f", + 5180 => x"18", + 5181 => x"1b", + 5182 => x"f6", + 5183 => x"83", + 5184 => x"ff", + 5185 => x"82", + 5186 => x"78", + 5187 => x"c4", + 5188 => x"60", + 5189 => x"7a", + 5190 => x"ff", + 5191 => x"75", + 5192 => x"53", + 5193 => x"51", + 5194 => x"3f", + 5195 => x"52", + 5196 => x"9f", + 5197 => x"56", + 5198 => x"83", + 5199 => x"06", + 5200 => x"52", + 5201 => x"9e", + 5202 => x"52", + 5203 => x"ff", + 5204 => x"f0", + 5205 => x"1b", + 5206 => x"87", + 5207 => x"55", + 5208 => x"83", + 5209 => x"74", + 5210 => x"ff", + 5211 => x"7c", + 5212 => x"74", + 5213 => x"38", + 5214 => x"54", + 5215 => x"52", + 5216 => x"99", + 5217 => x"de", + 5218 => x"87", + 5219 => x"53", + 5220 => x"08", + 5221 => x"ff", + 5222 => x"76", + 5223 => x"31", + 5224 => x"cd", + 5225 => x"58", + 5226 => x"ff", + 5227 => x"55", + 5228 => x"83", + 5229 => x"61", + 5230 => x"26", + 5231 => x"57", + 5232 => x"53", + 5233 => x"51", + 5234 => x"3f", + 5235 => x"08", + 5236 => x"76", + 5237 => x"31", + 5238 => x"db", + 5239 => x"7d", + 5240 => x"38", + 5241 => x"83", + 5242 => x"8a", + 5243 => x"7d", + 5244 => x"38", + 5245 => x"81", + 5246 => x"80", + 5247 => x"80", + 5248 => x"7a", + 5249 => x"bc", + 5250 => x"d5", + 5251 => x"ff", + 5252 => x"83", + 5253 => x"77", + 5254 => x"0b", + 5255 => x"81", + 5256 => x"34", + 5257 => x"34", + 5258 => x"34", + 5259 => x"56", + 5260 => x"52", + 5261 => x"ee", + 5262 => x"0b", + 5263 => x"81", + 5264 => x"82", + 5265 => x"56", + 5266 => x"34", + 5267 => x"08", + 5268 => x"60", + 5269 => x"1b", + 5270 => x"96", + 5271 => x"83", + 5272 => x"ff", + 5273 => x"81", + 5274 => x"7a", + 5275 => x"ff", + 5276 => x"81", + 5277 => x"c0", + 5278 => x"80", + 5279 => x"7e", + 5280 => x"e3", + 5281 => x"81", + 5282 => x"90", + 5283 => x"8e", + 5284 => x"81", + 5285 => x"81", + 5286 => x"56", + 5287 => x"c0", + 5288 => x"0d", + 5289 => x"0d", + 5290 => x"59", + 5291 => x"ff", + 5292 => x"57", + 5293 => x"b4", + 5294 => x"f8", + 5295 => x"81", + 5296 => x"52", + 5297 => x"dc", + 5298 => x"2e", + 5299 => x"9c", + 5300 => x"33", + 5301 => x"2e", + 5302 => x"76", + 5303 => x"58", + 5304 => x"57", + 5305 => x"09", + 5306 => x"38", + 5307 => x"78", + 5308 => x"38", + 5309 => x"81", + 5310 => x"8d", + 5311 => x"ff", + 5312 => x"52", + 5313 => x"81", + 5314 => x"84", + 5315 => x"94", + 5316 => x"08", + 5317 => x"f0", + 5318 => x"39", + 5319 => x"51", + 5320 => x"81", + 5321 => x"80", + 5322 => x"d0", + 5323 => x"eb", + 5324 => x"b4", + 5325 => x"39", + 5326 => x"51", + 5327 => x"81", + 5328 => x"80", + 5329 => x"d0", + 5330 => x"cf", + 5331 => x"80", + 5332 => x"39", + 5333 => x"51", + 5334 => x"81", + 5335 => x"bb", + 5336 => x"cc", + 5337 => x"81", + 5338 => x"af", + 5339 => x"8c", + 5340 => x"81", + 5341 => x"a3", + 5342 => x"c0", + 5343 => x"81", + 5344 => x"97", + 5345 => x"ec", + 5346 => x"81", + 5347 => x"8b", + 5348 => x"9c", + 5349 => x"81", + 5350 => x"ff", + 5351 => x"83", + 5352 => x"fb", + 5353 => x"79", + 5354 => x"87", + 5355 => x"38", + 5356 => x"87", + 5357 => x"91", + 5358 => x"52", + 5359 => x"eb", + 5360 => x"de", + 5361 => x"75", + 5362 => x"ab", + 5363 => x"c0", + 5364 => x"53", + 5365 => x"d3", + 5366 => x"8c", + 5367 => x"3d", + 5368 => x"3d", + 5369 => x"61", + 5370 => x"80", + 5371 => x"73", + 5372 => x"5f", + 5373 => x"5c", + 5374 => x"52", + 5375 => x"51", + 5376 => x"3f", + 5377 => x"51", + 5378 => x"3f", + 5379 => x"77", + 5380 => x"38", + 5381 => x"89", + 5382 => x"2e", + 5383 => x"c6", + 5384 => x"53", + 5385 => x"8e", + 5386 => x"52", + 5387 => x"51", + 5388 => x"3f", + 5389 => x"d3", + 5390 => x"86", + 5391 => x"15", + 5392 => x"39", + 5393 => x"72", + 5394 => x"38", + 5395 => x"81", + 5396 => x"ff", + 5397 => x"89", + 5398 => x"f0", + 5399 => x"df", + 5400 => x"55", + 5401 => x"16", + 5402 => x"27", + 5403 => x"33", + 5404 => x"fc", + 5405 => x"ab", + 5406 => x"81", + 5407 => x"ff", + 5408 => x"81", + 5409 => x"51", + 5410 => x"3f", + 5411 => x"81", + 5412 => x"ff", + 5413 => x"80", + 5414 => x"27", + 5415 => x"16", + 5416 => x"72", + 5417 => x"53", + 5418 => x"90", + 5419 => x"2e", + 5420 => x"80", + 5421 => x"38", + 5422 => x"39", + 5423 => x"f5", + 5424 => x"15", + 5425 => x"81", + 5426 => x"ff", + 5427 => x"76", + 5428 => x"5a", + 5429 => x"b4", + 5430 => x"c0", + 5431 => x"70", + 5432 => x"55", + 5433 => x"09", + 5434 => x"38", + 5435 => x"3f", + 5436 => x"08", + 5437 => x"98", + 5438 => x"32", + 5439 => x"72", + 5440 => x"51", + 5441 => x"55", + 5442 => x"8c", + 5443 => x"38", + 5444 => x"09", + 5445 => x"38", + 5446 => x"39", + 5447 => x"72", + 5448 => x"d6", + 5449 => x"72", + 5450 => x"0c", + 5451 => x"04", + 5452 => x"66", + 5453 => x"80", + 5454 => x"69", + 5455 => x"74", + 5456 => x"70", + 5457 => x"27", + 5458 => x"58", + 5459 => x"93", + 5460 => x"fc", + 5461 => x"75", + 5462 => x"70", + 5463 => x"bf", + 5464 => x"de", + 5465 => x"81", + 5466 => x"b8", + 5467 => x"c0", + 5468 => x"98", + 5469 => x"de", + 5470 => x"96", + 5471 => x"54", + 5472 => x"77", + 5473 => x"c4", + 5474 => x"de", + 5475 => x"81", + 5476 => x"90", + 5477 => x"74", + 5478 => x"38", + 5479 => x"19", + 5480 => x"39", + 5481 => x"05", + 5482 => x"3f", + 5483 => x"77", + 5484 => x"51", + 5485 => x"2e", + 5486 => x"80", + 5487 => x"81", + 5488 => x"87", + 5489 => x"08", + 5490 => x"fb", + 5491 => x"57", + 5492 => x"c0", + 5493 => x"0d", + 5494 => x"0d", + 5495 => x"05", + 5496 => x"57", + 5497 => x"80", + 5498 => x"79", + 5499 => x"3f", + 5500 => x"08", + 5501 => x"80", + 5502 => x"75", + 5503 => x"38", + 5504 => x"55", + 5505 => x"de", + 5506 => x"52", + 5507 => x"2d", + 5508 => x"08", + 5509 => x"77", + 5510 => x"de", + 5511 => x"3d", + 5512 => x"3d", + 5513 => x"05", + 5514 => x"98", + 5515 => x"a0", + 5516 => x"87", + 5517 => x"db", + 5518 => x"ff", + 5519 => x"81", + 5520 => x"81", + 5521 => x"81", + 5522 => x"52", + 5523 => x"51", + 5524 => x"3f", + 5525 => x"85", + 5526 => x"d4", + 5527 => x"0d", + 5528 => x"0d", + 5529 => x"80", + 5530 => x"80", + 5531 => x"51", + 5532 => x"3f", + 5533 => x"51", + 5534 => x"3f", + 5535 => x"f2", + 5536 => x"81", + 5537 => x"06", + 5538 => x"80", + 5539 => x"81", + 5540 => x"8c", + 5541 => x"f8", + 5542 => x"84", + 5543 => x"fe", + 5544 => x"72", + 5545 => x"81", + 5546 => x"71", + 5547 => x"38", + 5548 => x"f1", + 5549 => x"d5", + 5550 => x"f3", + 5551 => x"51", + 5552 => x"3f", + 5553 => x"70", + 5554 => x"52", + 5555 => x"95", + 5556 => x"fe", + 5557 => x"81", + 5558 => x"fe", + 5559 => x"80", + 5560 => x"bc", + 5561 => x"2a", + 5562 => x"51", + 5563 => x"2e", + 5564 => x"51", + 5565 => x"3f", + 5566 => x"51", + 5567 => x"3f", + 5568 => x"f1", + 5569 => x"85", + 5570 => x"06", + 5571 => x"80", + 5572 => x"81", + 5573 => x"88", + 5574 => x"c4", + 5575 => x"80", + 5576 => x"fe", + 5577 => x"72", + 5578 => x"81", + 5579 => x"71", + 5580 => x"38", + 5581 => x"f0", + 5582 => x"d5", + 5583 => x"f2", + 5584 => x"51", + 5585 => x"3f", + 5586 => x"70", + 5587 => x"52", + 5588 => x"95", + 5589 => x"fe", + 5590 => x"81", + 5591 => x"fe", + 5592 => x"80", + 5593 => x"b8", + 5594 => x"2a", + 5595 => x"51", + 5596 => x"2e", + 5597 => x"51", + 5598 => x"3f", + 5599 => x"51", + 5600 => x"3f", + 5601 => x"f0", + 5602 => x"fe", + 5603 => x"3d", + 5604 => x"3d", + 5605 => x"08", + 5606 => x"57", + 5607 => x"80", + 5608 => x"39", + 5609 => x"85", + 5610 => x"80", + 5611 => x"14", + 5612 => x"33", + 5613 => x"06", + 5614 => x"74", + 5615 => x"38", + 5616 => x"80", + 5617 => x"72", + 5618 => x"81", + 5619 => x"72", + 5620 => x"81", + 5621 => x"80", + 5622 => x"05", + 5623 => x"56", + 5624 => x"81", + 5625 => x"77", + 5626 => x"08", + 5627 => x"ea", + 5628 => x"de", + 5629 => x"38", + 5630 => x"53", + 5631 => x"ff", + 5632 => x"16", + 5633 => x"06", + 5634 => x"76", + 5635 => x"ff", + 5636 => x"de", + 5637 => x"3d", + 5638 => x"3d", + 5639 => x"70", + 5640 => x"80", + 5641 => x"fe", + 5642 => x"81", + 5643 => x"54", + 5644 => x"81", + 5645 => x"c0", + 5646 => x"c4", + 5647 => x"ff", + 5648 => x"c0", + 5649 => x"81", + 5650 => x"07", + 5651 => x"71", + 5652 => x"54", + 5653 => x"ec", + 5654 => x"ec", + 5655 => x"81", + 5656 => x"06", + 5657 => x"f5", + 5658 => x"52", + 5659 => x"b5", + 5660 => x"c0", + 5661 => x"8c", + 5662 => x"c0", + 5663 => x"fd", + 5664 => x"39", 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x"24", + 5724 => x"b0", + 5725 => x"38", + 5726 => x"84", + 5727 => x"b3", + 5728 => x"c1", + 5729 => x"38", + 5730 => x"2e", + 5731 => x"8f", + 5732 => x"80", + 5733 => x"f3", + 5734 => x"d5", + 5735 => x"78", + 5736 => x"8d", + 5737 => x"80", + 5738 => x"38", + 5739 => x"2e", + 5740 => x"8e", + 5741 => x"80", + 5742 => x"a1", + 5743 => x"d4", + 5744 => x"38", + 5745 => x"78", + 5746 => x"8e", + 5747 => x"81", + 5748 => x"38", + 5749 => x"2e", + 5750 => x"78", + 5751 => x"8d", + 5752 => x"cf", + 5753 => x"83", + 5754 => x"38", + 5755 => x"2e", + 5756 => x"8e", + 5757 => x"3d", + 5758 => x"53", + 5759 => x"51", + 5760 => x"3f", + 5761 => x"08", + 5762 => x"d7", + 5763 => x"a7", + 5764 => x"fe", + 5765 => x"fe", + 5766 => x"ff", + 5767 => x"81", + 5768 => x"80", + 5769 => x"81", + 5770 => x"38", + 5771 => x"80", + 5772 => x"52", + 5773 => x"05", + 5774 => x"85", + 5775 => x"de", + 5776 => x"ff", + 5777 => x"8e", + 5778 => x"a0", + 5779 => x"ef", + 5780 => x"fd", + 5781 => x"d7", + 5782 => x"a8", + 5783 => x"fe", + 5784 => x"fe", + 5785 => x"ff", + 5786 => x"81", + 5787 => x"80", + 5788 => x"38", + 5789 => x"52", + 5790 => x"05", + 5791 => x"89", + 5792 => x"de", + 5793 => x"81", + 5794 => x"8c", + 5795 => x"3d", + 5796 => x"53", + 5797 => x"51", + 5798 => x"3f", + 5799 => x"08", + 5800 => x"38", + 5801 => x"fc", + 5802 => x"3d", + 5803 => x"53", + 5804 => x"51", + 5805 => x"3f", + 5806 => x"08", + 5807 => x"de", + 5808 => x"63", + 5809 => x"d0", + 5810 => x"fe", + 5811 => x"02", + 5812 => x"33", + 5813 => x"63", + 5814 => x"81", + 5815 => x"51", + 5816 => x"3f", + 5817 => x"08", + 5818 => x"81", + 5819 => x"fe", + 5820 => x"81", + 5821 => x"39", + 5822 => x"f8", + 5823 => x"e5", + 5824 => x"de", + 5825 => x"3d", + 5826 => x"52", + 5827 => x"a3", + 5828 => x"81", + 5829 => x"52", + 5830 => x"94", + 5831 => x"39", + 5832 => x"f8", + 5833 => x"e5", + 5834 => x"de", + 5835 => x"3d", + 5836 => x"52", + 5837 => x"fb", + 5838 => x"c0", + 5839 => x"fe", + 5840 => x"5a", + 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x"ed", + 5959 => x"d7", + 5960 => x"e0", + 5961 => x"fe", + 5962 => x"fe", + 5963 => x"fe", + 5964 => x"81", + 5965 => x"80", + 5966 => x"38", + 5967 => x"f0", + 5968 => x"f8", + 5969 => x"fb", + 5970 => x"de", + 5971 => x"2e", + 5972 => x"59", + 5973 => x"05", + 5974 => x"63", + 5975 => x"b7", + 5976 => x"11", + 5977 => x"05", + 5978 => x"ac", + 5979 => x"c0", + 5980 => x"f7", + 5981 => x"70", + 5982 => x"81", + 5983 => x"fe", + 5984 => x"80", + 5985 => x"51", + 5986 => x"3f", + 5987 => x"33", + 5988 => x"2e", + 5989 => x"9f", + 5990 => x"38", + 5991 => x"f0", + 5992 => x"f8", + 5993 => x"fa", + 5994 => x"de", + 5995 => x"2e", + 5996 => x"59", + 5997 => x"05", + 5998 => x"63", + 5999 => x"ff", + 6000 => x"d8", + 6001 => x"f2", + 6002 => x"aa", + 6003 => x"fe", + 6004 => x"fe", + 6005 => x"fe", + 6006 => x"81", + 6007 => x"80", + 6008 => x"38", + 6009 => x"e4", + 6010 => x"f8", + 6011 => x"fc", + 6012 => x"de", + 6013 => x"2e", + 6014 => x"59", + 6015 => x"22", + 6016 => x"05", + 6017 => x"41", + 6018 => x"e4", + 6019 => x"f8", + 6020 => x"fb", + 6021 => x"de", + 6022 => x"38", + 6023 => x"60", + 6024 => x"52", + 6025 => x"51", + 6026 => x"3f", + 6027 => x"79", + 6028 => x"c9", + 6029 => x"79", + 6030 => x"ae", + 6031 => x"38", + 6032 => x"87", + 6033 => x"05", + 6034 => x"b7", + 6035 => x"11", + 6036 => x"05", + 6037 => x"b2", + 6038 => x"c0", + 6039 => x"92", + 6040 => x"02", + 6041 => x"79", + 6042 => x"5b", + 6043 => x"ff", + 6044 => x"d8", + 6045 => x"f1", + 6046 => x"a3", + 6047 => x"fe", + 6048 => x"fe", + 6049 => x"fe", + 6050 => x"81", + 6051 => x"80", + 6052 => x"38", + 6053 => x"e4", + 6054 => x"f8", + 6055 => x"fa", + 6056 => x"de", + 6057 => x"2e", + 6058 => x"60", + 6059 => x"60", + 6060 => x"b7", + 6061 => x"11", + 6062 => x"05", + 6063 => x"ca", + 6064 => x"c0", + 6065 => x"f4", + 6066 => x"70", + 6067 => x"81", + 6068 => x"fe", + 6069 => x"80", + 6070 => x"51", + 6071 => x"3f", + 6072 => x"33", + 6073 => x"2e", + 6074 => x"9f", + 6075 => x"38", + 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x"db", + 6194 => x"78", + 6195 => x"fe", + 6196 => x"fe", + 6197 => x"fe", + 6198 => x"81", + 6199 => x"80", + 6200 => x"38", + 6201 => x"d9", + 6202 => x"f2", + 6203 => x"59", + 6204 => x"de", + 6205 => x"81", + 6206 => x"80", + 6207 => x"38", + 6208 => x"08", + 6209 => x"dc", + 6210 => x"97", + 6211 => x"39", + 6212 => x"51", + 6213 => x"3f", + 6214 => x"3f", + 6215 => x"81", + 6216 => x"fe", + 6217 => x"80", + 6218 => x"39", + 6219 => x"3f", + 6220 => x"64", + 6221 => x"59", + 6222 => x"ef", + 6223 => x"80", + 6224 => x"38", + 6225 => x"06", + 6226 => x"80", + 6227 => x"38", + 6228 => x"f8", + 6229 => x"d8", + 6230 => x"de", + 6231 => x"5d", + 6232 => x"2e", + 6233 => x"82", + 6234 => x"7b", + 6235 => x"38", + 6236 => x"7b", + 6237 => x"38", + 6238 => x"81", + 6239 => x"7a", + 6240 => x"ac", + 6241 => x"81", + 6242 => x"b7", + 6243 => x"05", + 6244 => x"a5", + 6245 => x"81", + 6246 => x"b7", + 6247 => x"05", + 6248 => x"95", + 6249 => x"7a", + 6250 => x"ac", + 6251 => x"81", + 6252 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x"20", + 6429 => x"54", + 6430 => x"72", + 6431 => x"3d", + 6432 => x"64", + 6433 => x"00", + 6434 => x"20", + 6435 => x"52", + 6436 => x"52", + 6437 => x"43", + 6438 => x"6e", + 6439 => x"3d", + 6440 => x"64", + 6441 => x"00", + 6442 => x"20", + 6443 => x"48", + 6444 => x"45", + 6445 => x"53", + 6446 => x"00", + 6447 => x"20", + 6448 => x"49", + 6449 => x"00", + 6450 => x"20", + 6451 => x"54", + 6452 => x"00", + 6453 => x"20", + 6454 => x"0a", + 6455 => x"00", + 6456 => x"20", + 6457 => x"0a", + 6458 => x"00", + 6459 => x"72", + 6460 => x"65", + 6461 => x"00", + 6462 => x"20", + 6463 => x"20", + 6464 => x"65", + 6465 => x"65", + 6466 => x"72", + 6467 => x"64", + 6468 => x"73", + 6469 => x"25", + 6470 => x"0a", + 6471 => x"00", + 6472 => x"20", + 6473 => x"20", + 6474 => x"6f", + 6475 => x"53", + 6476 => x"74", + 6477 => x"64", + 6478 => x"73", + 6479 => x"25", + 6480 => x"0a", + 6481 => x"00", + 6482 => x"20", + 6483 => x"63", + 6484 => x"74", + 6485 => x"20", + 6486 => x"72", + 6487 => x"20", + 6488 => x"20", + 6489 => x"25", + 6490 => x"0a", + 6491 => x"00", + 6492 => x"63", + 6493 => x"00", + 6494 => x"20", + 6495 => x"20", + 6496 => x"20", + 6497 => x"20", + 6498 => x"20", + 6499 => x"20", + 6500 => x"20", + 6501 => x"25", + 6502 => x"0a", + 6503 => x"00", + 6504 => x"20", + 6505 => x"74", + 6506 => x"43", + 6507 => x"6b", + 6508 => x"65", + 6509 => x"20", + 6510 => x"20", + 6511 => x"25", + 6512 => x"30", + 6513 => x"48", + 6514 => x"00", + 6515 => x"20", + 6516 => x"41", + 6517 => x"6c", + 6518 => x"20", + 6519 => x"71", + 6520 => x"20", + 6521 => x"20", + 6522 => x"25", + 6523 => x"30", + 6524 => x"48", + 6525 => x"00", + 6526 => x"20", + 6527 => x"68", + 6528 => x"65", + 6529 => x"52", + 6530 => x"43", + 6531 => x"6b", + 6532 => x"65", + 6533 => x"25", + 6534 => x"30", + 6535 => x"48", + 6536 => x"00", + 6537 => x"6c", + 6538 => x"00", + 6539 => x"69", + 6540 => x"00", + 6541 => x"78", + 6542 => x"00", + 6543 => x"00", + 6544 => x"6d", + 6545 => x"00", + 6546 => x"6e", + 6547 => x"00", + 6548 => x"00", + 6549 => x"2c", + 6550 => x"3d", + 6551 => x"5d", + 6552 => x"00", + 6553 => x"00", + 6554 => x"33", + 6555 => x"00", + 6556 => x"4d", + 6557 => x"53", + 6558 => x"00", + 6559 => x"4e", + 6560 => x"20", + 6561 => x"46", + 6562 => x"32", + 6563 => x"00", + 6564 => x"4e", + 6565 => x"20", + 6566 => x"46", + 6567 => x"20", + 6568 => x"00", + 6569 => x"50", + 6570 => x"00", + 6571 => x"00", + 6572 => x"00", + 6573 => x"41", + 6574 => x"80", + 6575 => x"49", + 6576 => x"8f", + 6577 => x"4f", + 6578 => x"55", + 6579 => x"9b", + 6580 => x"9f", + 6581 => x"55", + 6582 => x"a7", + 6583 => x"ab", + 6584 => x"af", + 6585 => x"b3", + 6586 => x"b7", + 6587 => x"bb", + 6588 => x"bf", + 6589 => x"c3", + 6590 => x"c7", + 6591 => x"cb", + 6592 => x"cf", + 6593 => x"d3", + 6594 => x"d7", + 6595 => x"db", + 6596 => x"df", + 6597 => x"e3", + 6598 => x"e7", + 6599 => x"eb", + 6600 => x"ef", + 6601 => x"f3", + 6602 => x"f7", + 6603 => x"fb", + 6604 => x"ff", + 6605 => x"3b", + 6606 => x"2f", + 6607 => x"3a", + 6608 => x"7c", + 6609 => x"00", + 6610 => x"04", + 6611 => x"40", + 6612 => x"00", + 6613 => x"00", + 6614 => x"02", + 6615 => x"08", + 6616 => x"20", + 6617 => x"00", + 6618 => x"69", + 6619 => x"00", + 6620 => x"63", + 6621 => x"00", + 6622 => x"69", + 6623 => x"00", + 6624 => x"61", + 6625 => x"00", + 6626 => x"65", + 6627 => x"00", + 6628 => x"65", + 6629 => x"00", + 6630 => x"6d", + 6631 => x"00", + 6632 => x"63", + 6633 => x"00", + 6634 => x"00", + 6635 => x"00", + 6636 => x"00", + 6637 => x"00", + 6638 => x"00", + 6639 => x"00", + 6640 => x"00", + 6641 => x"6c", + 6642 => x"00", + 6643 => x"00", + 6644 => x"74", + 6645 => x"00", + 6646 => x"65", + 6647 => x"00", + 6648 => x"6f", + 6649 => x"00", + 6650 => x"74", + 6651 => x"00", + 6652 => x"6b", + 6653 => x"72", + 6654 => x"00", + 6655 => x"65", + 6656 => x"6c", + 6657 => x"72", + 6658 => x"0a", + 6659 => x"00", + 6660 => x"6b", + 6661 => x"74", + 6662 => x"61", + 6663 => x"0a", + 6664 => x"00", + 6665 => x"66", + 6666 => x"20", + 6667 => x"6e", + 6668 => x"00", + 6669 => x"70", + 6670 => x"20", + 6671 => x"6e", + 6672 => x"00", + 6673 => x"61", + 6674 => x"20", + 6675 => x"65", + 6676 => x"65", + 6677 => x"00", + 6678 => x"65", + 6679 => x"64", + 6680 => x"65", + 6681 => x"00", + 6682 => x"65", + 6683 => x"72", + 6684 => x"79", + 6685 => x"69", + 6686 => x"2e", + 6687 => x"00", + 6688 => x"65", + 6689 => x"6e", + 6690 => x"20", + 6691 => x"61", + 6692 => x"2e", + 6693 => x"00", + 6694 => x"69", + 6695 => x"72", + 6696 => x"20", + 6697 => x"74", + 6698 => x"65", + 6699 => x"00", + 6700 => x"76", + 6701 => x"75", + 6702 => x"72", + 6703 => x"20", + 6704 => x"61", + 6705 => x"2e", + 6706 => x"00", + 6707 => x"6b", + 6708 => x"74", + 6709 => x"61", + 6710 => x"64", + 6711 => x"00", + 6712 => x"63", + 6713 => x"61", + 6714 => x"6c", + 6715 => x"69", + 6716 => x"79", + 6717 => x"6d", + 6718 => x"75", + 6719 => x"6f", + 6720 => x"69", + 6721 => x"0a", + 6722 => x"00", + 6723 => x"6d", + 6724 => x"61", + 6725 => x"74", + 6726 => x"0a", + 6727 => x"00", + 6728 => x"65", + 6729 => x"2c", + 6730 => x"65", + 6731 => x"69", + 6732 => x"63", + 6733 => x"65", + 6734 => x"64", + 6735 => x"00", + 6736 => x"65", + 6737 => x"20", + 6738 => x"6b", + 6739 => x"0a", + 6740 => x"00", + 6741 => x"75", + 6742 => x"63", + 6743 => x"74", + 6744 => x"6d", + 6745 => x"2e", + 6746 => x"00", + 6747 => x"20", + 6748 => x"79", + 6749 => x"65", + 6750 => x"69", + 6751 => x"2e", + 6752 => x"00", + 6753 => x"61", + 6754 => x"65", + 6755 => x"69", + 6756 => x"72", + 6757 => x"74", + 6758 => x"00", + 6759 => x"63", + 6760 => x"2e", + 6761 => x"00", + 6762 => x"6e", + 6763 => x"20", + 6764 => x"6f", + 6765 => x"00", + 6766 => x"75", + 6767 => x"74", + 6768 => x"25", + 6769 => x"74", + 6770 => x"75", + 6771 => x"74", + 6772 => x"73", + 6773 => x"0a", + 6774 => x"00", + 6775 => x"58", + 6776 => x"00", + 6777 => x"00", + 6778 => x"58", + 6779 => x"00", + 6780 => x"20", + 6781 => x"20", + 6782 => x"00", + 6783 => x"58", + 6784 => x"00", + 6785 => x"00", + 6786 => x"00", + 6787 => x"00", + 6788 => x"64", + 6789 => x"00", + 6790 => x"54", + 6791 => x"00", + 6792 => x"20", + 6793 => x"28", + 6794 => x"00", + 6795 => x"31", + 6796 => x"30", + 6797 => x"00", + 6798 => x"34", + 6799 => x"00", + 6800 => x"55", + 6801 => x"65", + 6802 => x"30", + 6803 => x"20", + 6804 => x"25", + 6805 => x"2a", + 6806 => x"00", + 6807 => x"54", + 6808 => x"6e", + 6809 => x"72", + 6810 => x"20", + 6811 => x"64", + 6812 => x"0a", + 6813 => x"00", + 6814 => x"65", + 6815 => x"6e", + 6816 => x"72", + 6817 => x"0a", + 6818 => x"00", + 6819 => x"20", + 6820 => x"65", + 6821 => x"70", + 6822 => x"00", + 6823 => x"54", + 6824 => x"44", + 6825 => x"74", + 6826 => x"75", + 6827 => x"00", + 6828 => x"54", + 6829 => x"52", + 6830 => x"74", + 6831 => x"75", + 6832 => x"00", + 6833 => x"54", + 6834 => x"58", + 6835 => x"74", + 6836 => x"75", + 6837 => x"00", + 6838 => x"54", + 6839 => x"58", + 6840 => x"74", + 6841 => x"75", + 6842 => x"00", + 6843 => x"54", + 6844 => x"58", + 6845 => x"74", + 6846 => x"75", + 6847 => x"00", + 6848 => x"54", + 6849 => x"58", + 6850 => x"74", + 6851 => x"75", + 6852 => x"00", + 6853 => x"74", + 6854 => x"20", + 6855 => x"74", + 6856 => x"72", + 6857 => x"0a", + 6858 => x"00", + 6859 => x"62", + 6860 => x"67", + 6861 => x"6d", + 6862 => x"2e", + 6863 => x"00", + 6864 => x"6f", + 6865 => x"63", + 6866 => x"74", + 6867 => x"00", + 6868 => x"00", + 6869 => x"6c", + 6870 => x"74", + 6871 => x"6e", + 6872 => x"61", + 6873 => x"65", + 6874 => x"20", + 6875 => x"64", + 6876 => x"20", + 6877 => x"61", + 6878 => x"69", + 6879 => x"20", + 6880 => x"75", + 6881 => x"79", + 6882 => x"00", + 6883 => x"00", + 6884 => x"20", + 6885 => x"6b", + 6886 => x"21", + 6887 => x"00", + 6888 => x"74", + 6889 => x"69", + 6890 => x"2e", + 6891 => x"00", + 6892 => x"6c", + 6893 => x"74", + 6894 => x"6e", + 6895 => x"61", + 6896 => x"65", + 6897 => x"00", + 6898 => x"25", + 6899 => x"00", + 6900 => x"00", + 6901 => x"61", + 6902 => x"67", + 6903 => x"2e", + 6904 => x"00", + 6905 => x"70", + 6906 => x"6d", + 6907 => x"0a", + 6908 => x"00", + 6909 => x"6d", + 6910 => x"74", + 6911 => x"00", + 6912 => x"58", + 6913 => x"32", + 6914 => x"00", + 6915 => x"0a", + 6916 => x"00", + 6917 => x"58", + 6918 => x"34", + 6919 => x"00", + 6920 => x"58", + 6921 => x"38", + 6922 => x"00", + 6923 => x"72", + 6924 => x"6e", + 6925 => x"0a", + 6926 => x"00", + 6927 => x"6c", + 6928 => x"25", + 6929 => x"78", + 6930 => x"00", + 6931 => x"61", + 6932 => x"6e", + 6933 => x"6e", + 6934 => x"72", + 6935 => x"73", + 6936 => x"00", + 6937 => x"62", + 6938 => x"67", + 6939 => x"74", + 6940 => x"75", + 6941 => x"0a", + 6942 => x"00", + 6943 => x"61", + 6944 => x"64", + 6945 => x"72", + 6946 => x"69", + 6947 => x"00", + 6948 => x"62", + 6949 => x"67", + 6950 => x"72", + 6951 => x"69", + 6952 => x"00", + 6953 => x"63", + 6954 => x"6e", + 6955 => x"6f", + 6956 => x"40", + 6957 => x"38", + 6958 => x"2e", + 6959 => x"00", + 6960 => x"6c", + 6961 => x"20", + 6962 => x"65", + 6963 => x"25", + 6964 => x"20", + 6965 => x"0a", + 6966 => x"00", + 6967 => x"6c", + 6968 => x"74", + 6969 => x"65", + 6970 => x"6f", + 6971 => x"28", + 6972 => x"2e", + 6973 => x"00", + 6974 => x"74", + 6975 => x"69", + 6976 => x"61", + 6977 => x"69", + 6978 => x"69", + 6979 => x"2e", + 6980 => x"00", + 6981 => x"64", + 6982 => x"62", + 6983 => x"69", + 6984 => x"2e", + 6985 => x"00", + 6986 => x"00", + 6987 => x"00", + 6988 => x"5c", + 6989 => x"25", + 6990 => x"73", + 6991 => x"00", + 6992 => x"5c", + 6993 => x"25", + 6994 => x"00", + 6995 => x"5c", + 6996 => x"00", + 6997 => x"20", + 6998 => x"6d", + 6999 => x"2e", + 7000 => x"00", + 7001 => x"6e", + 7002 => x"2e", + 7003 => x"00", + 7004 => x"62", + 7005 => x"67", + 7006 => x"74", + 7007 => x"75", + 7008 => x"2e", + 7009 => x"00", + 7010 => x"00", + 7011 => x"00", + 7012 => x"ff", + 7013 => x"00", + 7014 => x"ff", + 7015 => x"00", + 7016 => x"ff", + 7017 => x"00", + 7018 => x"00", + 7019 => x"00", + 7020 => x"ff", + 7021 => x"00", + 7022 => x"00", + 7023 => x"00", + 7024 => x"00", + 7025 => x"00", + 7026 => x"00", + 7027 => x"00", + 7028 => x"00", + 7029 => x"01", + 7030 => x"01", + 7031 => x"01", + 7032 => x"00", + 7033 => x"00", + 7034 => x"00", + 7035 => x"00", + 7036 => x"68", + 7037 => x"00", + 7038 => x"00", + 7039 => x"00", + 7040 => x"70", + 7041 => x"00", + 7042 => x"00", + 7043 => x"00", + 7044 => x"78", + 7045 => x"00", + 7046 => x"00", + 7047 => x"00", + 7048 => x"80", + 7049 => x"00", + 7050 => x"00", + 7051 => x"00", + 7052 => x"88", + 7053 => x"00", + 7054 => x"00", + 7055 => x"00", + 7056 => x"90", + 7057 => x"00", + 7058 => x"00", + 7059 => x"00", + 7060 => x"98", + 7061 => x"00", + 7062 => x"00", + 7063 => x"00", + 7064 => x"a0", + 7065 => x"00", + 7066 => x"00", + 7067 => x"00", + 7068 => x"a8", + 7069 => x"00", + 7070 => x"00", + 7071 => x"00", + 7072 => x"ac", + 7073 => x"00", + 7074 => x"00", + 7075 => x"00", + 7076 => x"b0", + 7077 => x"00", + 7078 => x"00", + 7079 => x"00", + 7080 => x"b4", + 7081 => x"00", + 7082 => x"00", + 7083 => x"00", + 7084 => x"b8", + 7085 => x"00", + 7086 => x"00", + 7087 => x"00", + 7088 => x"bc", + 7089 => x"00", + 7090 => x"00", + 7091 => x"00", + 7092 => x"c0", + 7093 => x"00", + 7094 => x"00", + 7095 => x"00", + 7096 => x"c4", + 7097 => x"00", + 7098 => x"00", + 7099 => x"00", + 7100 => x"cc", + 7101 => x"00", + 7102 => x"00", + 7103 => x"00", + 7104 => x"d0", + 7105 => x"00", + 7106 => x"00", + 7107 => x"00", + 7108 => x"d8", + 7109 => x"00", + 7110 => x"00", + 7111 => x"00", + 7112 => x"e0", + 7113 => x"00", + 7114 => x"00", + 7115 => x"00", + 7116 => x"e8", + 7117 => x"00", + 7118 => x"00", + 7119 => x"00", + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + 0 => x"0b", + 1 => x"00", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"8c", + 9 => x"88", + 10 => x"90", + 11 => x"88", + 12 => x"00", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"06", + 17 => x"06", + 18 => x"82", + 19 => x"2a", + 20 => x"06", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"06", + 25 => x"ff", + 26 => x"09", + 27 => x"05", + 28 => x"09", + 29 => x"ff", + 30 => x"0b", + 31 => x"04", + 32 => x"81", + 33 => x"73", + 34 => x"09", + 35 => x"73", + 36 => x"81", + 37 => x"04", + 38 => x"00", + 39 => x"00", + 40 => x"24", + 41 => x"07", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"81", + 50 => x"05", + 51 => x"0a", + 52 => x"0a", + 53 => x"81", + 54 => x"53", + 55 => x"00", + 56 => x"26", + 57 => x"07", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"51", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"9f", + 89 => x"05", + 90 => x"92", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"2a", + 97 => x"06", + 98 => x"09", + 99 => x"ff", + 100 => x"53", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"53", + 105 => x"73", + 106 => x"81", + 107 => x"83", + 108 => x"07", + 109 => x"0c", + 110 => x"00", + 111 => x"00", + 112 => x"81", + 113 => x"09", + 114 => x"09", + 115 => x"06", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"81", + 121 => x"09", + 122 => x"09", + 123 => x"81", + 124 => x"04", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"81", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"09", + 137 => x"53", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"09", + 146 => x"51", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"06", + 153 => x"06", + 154 => x"83", + 155 => x"10", + 156 => x"06", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"06", + 161 => x"81", + 162 => x"83", + 163 => x"05", + 164 => x"0b", + 165 => x"04", + 166 => x"00", + 167 => x"00", + 168 => x"8c", + 169 => x"75", + 170 => x"0b", + 171 => x"50", + 172 => x"56", + 173 => x"0c", + 174 => x"04", + 175 => x"00", + 176 => x"8c", + 177 => x"75", + 178 => x"0b", + 179 => x"50", + 180 => x"56", + 181 => x"0c", + 182 => x"04", + 183 => x"00", + 184 => x"70", + 185 => x"06", + 186 => x"ff", + 187 => x"71", + 188 => x"72", + 189 => x"05", + 190 => x"51", + 191 => x"00", + 192 => x"70", + 193 => x"06", + 194 => x"06", + 195 => x"54", + 196 => x"09", + 197 => x"ff", + 198 => x"51", + 199 => x"00", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"05", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"05", + 233 => x"05", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"05", + 249 => x"53", + 250 => x"04", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"06", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"0b", + 265 => x"0b", + 266 => x"85", + 267 => x"0b", + 268 => x"0b", + 269 => x"a3", + 270 => x"0b", + 271 => x"0b", + 272 => x"c1", + 273 => x"0b", + 274 => x"0b", + 275 => x"df", + 276 => x"0b", + 277 => x"0b", + 278 => x"fd", + 279 => x"0b", + 280 => x"0b", + 281 => x"9b", + 282 => x"0b", + 283 => x"0b", + 284 => x"b9", + 285 => x"0b", + 286 => x"0b", + 287 => x"d7", + 288 => x"0b", + 289 => x"0b", + 290 => x"f5", + 291 => x"0b", + 292 => x"0b", + 293 => x"94", + 294 => x"0b", + 295 => x"0b", + 296 => x"b4", + 297 => x"0b", + 298 => x"0b", + 299 => x"d4", + 300 => x"0b", + 301 => x"0b", + 302 => x"f4", + 303 => x"0b", + 304 => x"0b", + 305 => x"94", + 306 => x"0b", + 307 => x"0b", + 308 => x"b4", + 309 => x"0b", + 310 => x"0b", + 311 => x"d4", + 312 => x"0b", + 313 => x"0b", + 314 => x"f4", + 315 => x"0b", + 316 => x"0b", + 317 => x"94", + 318 => x"0b", + 319 => x"0b", + 320 => x"b4", + 321 => x"0b", + 322 => x"0b", + 323 => x"d4", + 324 => x"0b", + 325 => x"0b", + 326 => x"f4", + 327 => x"0b", + 328 => x"0b", + 329 => x"94", + 330 => x"0b", + 331 => x"0b", + 332 => x"b2", + 333 => x"0b", + 334 => x"0b", + 335 => x"d0", + 336 => x"0b", + 337 => x"0b", + 338 => x"ee", + 339 => x"ff", + 340 => x"ff", + 341 => x"ff", + 342 => x"ff", + 343 => x"ff", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"8c", + 385 => x"de", + 386 => x"ae", + 387 => x"cc", + 388 => x"90", + 389 => x"cc", + 390 => x"2d", + 391 => x"08", + 392 => x"04", + 393 => x"0c", + 394 => x"81", + 395 => x"84", + 396 => x"81", + 397 => x"ae", + 398 => x"de", + 399 => x"80", + 400 => x"de", + 401 => x"fd", + 402 => x"cc", + 403 => x"90", + 404 => x"cc", + 405 => x"2d", + 406 => x"08", + 407 => x"04", + 408 => x"0c", + 409 => x"81", + 410 => x"84", + 411 => x"81", + 412 => x"b6", + 413 => x"de", + 414 => x"80", + 415 => x"de", + 416 => x"8a", + 417 => x"cc", + 418 => x"90", + 419 => x"cc", + 420 => x"2d", + 421 => x"08", + 422 => x"04", + 423 => x"0c", + 424 => x"81", + 425 => x"84", + 426 => x"81", + 427 => x"b4", + 428 => x"de", + 429 => x"80", + 430 => x"de", + 431 => x"bb", + 432 => x"cc", + 433 => x"90", + 434 => x"cc", + 435 => x"2d", + 436 => x"08", + 437 => x"04", + 438 => x"0c", + 439 => x"81", + 440 => x"84", + 441 => x"81", + 442 => x"9c", + 443 => x"de", + 444 => x"80", + 445 => x"de", + 446 => x"90", + 447 => x"cc", + 448 => x"90", + 449 => x"cc", + 450 => x"bf", + 451 => x"cc", + 452 => x"90", + 453 => x"cc", + 454 => x"b0", + 455 => x"cc", + 456 => x"90", + 457 => x"cc", + 458 => x"a4", + 459 => x"cc", + 460 => x"90", + 461 => x"cc", + 462 => x"a1", + 463 => x"cc", + 464 => x"90", + 465 => x"cc", + 466 => x"bf", + 467 => x"cc", + 468 => x"90", + 469 => x"cc", + 470 => x"9f", + 471 => x"cc", + 472 => x"90", + 473 => x"cc", + 474 => x"92", + 475 => x"cc", + 476 => x"90", + 477 => x"cc", + 478 => x"de", + 479 => x"cc", + 480 => x"90", + 481 => x"cc", + 482 => x"fd", + 483 => x"cc", + 484 => x"90", + 485 => x"cc", + 486 => x"9c", + 487 => x"cc", + 488 => x"90", + 489 => x"cc", + 490 => x"86", + 491 => x"cc", + 492 => x"90", + 493 => x"cc", + 494 => x"ec", + 495 => x"cc", + 496 => x"90", + 497 => x"cc", + 498 => x"da", + 499 => x"cc", + 500 => x"90", + 501 => x"cc", + 502 => x"a0", + 503 => x"cc", + 504 => x"90", + 505 => x"cc", + 506 => x"da", + 507 => x"cc", + 508 => x"90", + 509 => x"cc", + 510 => x"db", + 511 => x"cc", + 512 => x"90", + 513 => x"cc", + 514 => x"90", + 515 => x"cc", + 516 => x"90", + 517 => x"cc", + 518 => x"e9", + 519 => x"cc", + 520 => x"90", + 521 => x"cc", + 522 => x"94", + 523 => x"cc", + 524 => x"90", + 525 => x"cc", + 526 => x"f7", + 527 => x"cc", + 528 => x"90", + 529 => x"cc", + 530 => x"cc", + 531 => x"cc", + 532 => x"90", + 533 => x"cc", + 534 => x"d6", + 535 => x"cc", + 536 => x"90", + 537 => x"cc", + 538 => x"98", + 539 => x"cc", + 540 => x"90", + 541 => x"cc", + 542 => x"de", + 543 => x"cc", + 544 => x"90", + 545 => x"cc", + 546 => x"84", + 547 => x"cc", + 548 => x"90", + 549 => x"cc", + 550 => x"2d", + 551 => x"08", + 552 => x"04", + 553 => x"0c", + 554 => x"81", + 555 => x"84", + 556 => x"81", + 557 => x"be", + 558 => x"de", + 559 => x"80", + 560 => x"de", + 561 => x"d1", + 562 => x"cc", + 563 => x"90", + 564 => x"cc", + 565 => x"2d", + 566 => x"08", + 567 => x"04", + 568 => x"0c", + 569 => x"81", + 570 => x"84", + 571 => x"81", + 572 => x"81", + 573 => x"81", + 574 => x"84", + 575 => x"3c", + 576 => x"10", + 577 => x"10", + 578 => x"10", + 579 => x"10", + 580 => x"10", + 581 => x"10", + 582 => x"10", + 583 => x"10", + 584 => x"00", + 585 => x"ff", + 586 => x"06", + 587 => x"83", + 588 => x"10", + 589 => x"fc", + 590 => x"51", + 591 => x"80", + 592 => x"ff", + 593 => x"06", + 594 => x"52", + 595 => x"0a", + 596 => x"38", + 597 => x"51", + 598 => x"c0", + 599 => x"ec", + 600 => x"80", + 601 => x"05", + 602 => x"0b", + 603 => x"04", + 604 => x"81", + 605 => x"00", + 606 => x"08", + 607 => x"cc", + 608 => x"0d", + 609 => x"de", + 610 => x"05", + 611 => x"de", + 612 => x"05", + 613 => x"d4", + 614 => x"c0", + 615 => x"de", + 616 => x"85", + 617 => x"de", + 618 => x"81", + 619 => x"02", + 620 => x"0c", + 621 => x"81", + 622 => x"cc", + 623 => x"08", + 624 => x"cc", + 625 => x"08", + 626 => x"3f", + 627 => x"08", + 628 => x"c0", + 629 => x"3d", + 630 => x"cc", + 631 => x"de", + 632 => x"81", + 633 => x"f9", + 634 => x"0b", + 635 => x"08", + 636 => x"81", + 637 => x"88", + 638 => x"25", + 639 => x"de", + 640 => x"05", + 641 => x"de", + 642 => x"05", + 643 => x"81", + 644 => x"f4", + 645 => x"de", + 646 => x"05", + 647 => x"81", + 648 => x"cc", + 649 => x"0c", + 650 => x"08", + 651 => x"81", + 652 => x"fc", + 653 => x"de", + 654 => x"05", + 655 => x"b9", + 656 => x"cc", + 657 => x"08", + 658 => x"cc", + 659 => x"0c", + 660 => x"de", + 661 => x"05", + 662 => x"cc", + 663 => x"08", + 664 => x"0b", + 665 => x"08", + 666 => x"81", + 667 => x"f0", + 668 => x"de", + 669 => x"05", + 670 => x"81", + 671 => x"8c", + 672 => x"81", + 673 => x"88", + 674 => x"81", + 675 => x"de", + 676 => x"81", + 677 => x"f8", + 678 => x"81", + 679 => x"fc", + 680 => x"2e", + 681 => x"de", + 682 => x"05", + 683 => x"de", + 684 => x"05", + 685 => x"cc", + 686 => x"08", + 687 => x"c0", + 688 => x"3d", + 689 => x"cc", + 690 => x"de", + 691 => x"81", + 692 => x"fb", + 693 => x"0b", + 694 => x"08", + 695 => x"81", + 696 => x"88", + 697 => x"25", + 698 => x"de", + 699 => x"05", + 700 => x"de", + 701 => x"05", + 702 => x"81", + 703 => x"fc", + 704 => x"de", + 705 => x"05", + 706 => x"90", + 707 => x"cc", + 708 => x"08", + 709 => x"cc", + 710 => x"0c", + 711 => x"de", + 712 => x"05", + 713 => x"de", + 714 => x"05", + 715 => x"3f", + 716 => x"08", + 717 => x"cc", + 718 => x"0c", + 719 => x"cc", + 720 => x"08", + 721 => x"38", + 722 => x"08", + 723 => x"30", + 724 => x"08", + 725 => x"81", + 726 => x"f8", + 727 => x"81", + 728 => x"54", + 729 => x"81", + 730 => x"04", + 731 => x"08", + 732 => x"cc", + 733 => x"0d", + 734 => x"de", + 735 => x"05", + 736 => x"81", + 737 => x"f8", + 738 => x"de", + 739 => x"05", + 740 => x"cc", + 741 => x"08", + 742 => x"81", + 743 => x"fc", + 744 => x"2e", + 745 => x"0b", + 746 => x"08", + 747 => x"24", + 748 => x"de", + 749 => x"05", + 750 => x"de", + 751 => x"05", + 752 => x"cc", + 753 => x"08", + 754 => x"cc", + 755 => x"0c", + 756 => x"81", + 757 => x"fc", + 758 => x"2e", + 759 => x"81", + 760 => x"8c", + 761 => x"de", + 762 => x"05", + 763 => x"38", + 764 => x"08", + 765 => x"81", + 766 => x"8c", + 767 => x"81", + 768 => x"88", + 769 => x"de", + 770 => x"05", + 771 => x"cc", + 772 => x"08", + 773 => x"cc", + 774 => x"0c", + 775 => x"08", + 776 => x"81", + 777 => x"cc", + 778 => x"0c", + 779 => x"08", + 780 => x"81", + 781 => x"cc", + 782 => x"0c", + 783 => x"81", + 784 => x"90", + 785 => x"2e", + 786 => x"de", + 787 => x"05", + 788 => x"de", + 789 => x"05", + 790 => x"39", + 791 => x"08", + 792 => x"70", + 793 => x"08", + 794 => x"51", + 795 => x"08", + 796 => x"81", + 797 => x"85", + 798 => x"de", + 799 => x"fc", + 800 => x"79", + 801 => x"05", + 802 => x"57", + 803 => x"83", + 804 => x"38", + 805 => x"51", + 806 => x"a4", + 807 => x"52", + 808 => x"93", + 809 => x"70", + 810 => x"34", + 811 => x"71", + 812 => x"81", + 813 => x"74", + 814 => x"0c", + 815 => x"04", + 816 => x"2b", + 817 => x"71", + 818 => x"51", + 819 => x"72", + 820 => x"72", + 821 => x"05", + 822 => x"71", + 823 => x"53", + 824 => x"70", + 825 => x"0c", + 826 => x"84", + 827 => x"f0", + 828 => x"8f", + 829 => x"83", + 830 => x"38", + 831 => x"84", + 832 => x"fc", + 833 => x"83", + 834 => x"70", + 835 => x"39", + 836 => x"77", + 837 => x"07", + 838 => x"54", + 839 => x"38", + 840 => x"08", + 841 => x"71", + 842 => x"80", + 843 => x"75", + 844 => x"33", + 845 => x"06", + 846 => x"80", + 847 => x"72", + 848 => x"75", + 849 => x"06", + 850 => x"12", + 851 => x"33", + 852 => x"06", + 853 => x"52", + 854 => x"72", + 855 => x"81", + 856 => x"81", + 857 => x"71", + 858 => x"c0", + 859 => x"87", + 860 => x"71", + 861 => x"fb", + 862 => x"06", + 863 => x"82", + 864 => x"51", + 865 => x"97", + 866 => x"84", + 867 => x"54", + 868 => x"75", + 869 => x"38", + 870 => x"52", + 871 => x"80", + 872 => x"c0", + 873 => x"0d", + 874 => x"0d", + 875 => x"53", + 876 => x"52", + 877 => x"81", + 878 => x"81", + 879 => x"07", + 880 => x"52", + 881 => x"e8", + 882 => x"de", + 883 => x"3d", + 884 => x"3d", + 885 => x"08", + 886 => x"56", + 887 => x"80", + 888 => x"33", + 889 => x"2e", + 890 => x"86", + 891 => x"52", + 892 => x"53", + 893 => x"13", + 894 => x"33", + 895 => x"06", + 896 => x"70", + 897 => x"38", + 898 => x"80", + 899 => x"74", + 900 => x"81", + 901 => x"70", + 902 => x"81", + 903 => x"80", + 904 => x"05", + 905 => x"76", + 906 => x"70", + 907 => x"0c", + 908 => x"04", + 909 => x"76", + 910 => x"80", + 911 => x"86", + 912 => x"52", + 913 => x"c3", + 914 => x"c0", + 915 => x"80", + 916 => x"74", + 917 => x"de", + 918 => x"3d", + 919 => x"3d", + 920 => x"11", + 921 => x"52", + 922 => x"70", + 923 => x"98", + 924 => x"33", + 925 => x"82", + 926 => x"26", + 927 => x"84", + 928 => x"83", + 929 => x"26", + 930 => x"85", + 931 => x"84", + 932 => x"26", + 933 => x"86", + 934 => x"85", + 935 => x"26", + 936 => x"88", + 937 => x"86", + 938 => x"e7", + 939 => x"38", + 940 => x"54", + 941 => x"87", + 942 => x"cc", + 943 => x"87", + 944 => x"0c", + 945 => x"c0", + 946 => x"82", + 947 => x"c0", + 948 => x"83", + 949 => x"c0", + 950 => x"84", + 951 => x"c0", + 952 => x"85", + 953 => x"c0", + 954 => x"86", + 955 => x"c0", + 956 => x"74", + 957 => x"a4", + 958 => x"c0", + 959 => x"80", + 960 => x"98", + 961 => x"52", + 962 => x"c0", + 963 => x"0d", + 964 => x"0d", + 965 => x"c0", + 966 => x"81", + 967 => x"c0", + 968 => x"5e", + 969 => x"87", + 970 => x"08", + 971 => x"1c", + 972 => x"98", + 973 => x"79", + 974 => x"87", + 975 => x"08", + 976 => x"1c", + 977 => x"98", + 978 => x"79", + 979 => x"87", + 980 => x"08", + 981 => x"1c", + 982 => x"98", + 983 => x"7b", + 984 => x"87", + 985 => x"08", + 986 => x"1c", + 987 => x"0c", + 988 => x"ff", + 989 => x"83", + 990 => x"58", + 991 => x"57", + 992 => x"56", + 993 => x"55", + 994 => x"54", + 995 => x"53", + 996 => x"ff", + 997 => x"c6", + 998 => x"88", + 999 => x"0d", + 1000 => x"0d", + 1001 => x"33", + 1002 => x"9f", + 1003 => x"52", + 1004 => x"81", + 1005 => x"83", + 1006 => x"fb", + 1007 => x"0b", + 1008 => x"88", + 1009 => x"ff", + 1010 => x"56", + 1011 => x"84", + 1012 => x"2e", + 1013 => x"c0", + 1014 => x"70", + 1015 => x"2a", + 1016 => x"53", + 1017 => x"80", + 1018 => x"71", + 1019 => x"81", + 1020 => x"70", + 1021 => x"81", + 1022 => x"06", + 1023 => x"80", + 1024 => x"71", + 1025 => x"81", + 1026 => x"70", + 1027 => x"73", + 1028 => x"51", + 1029 => x"80", + 1030 => x"2e", + 1031 => x"c0", + 1032 => x"75", + 1033 => x"81", + 1034 => x"87", + 1035 => x"fb", + 1036 => x"9f", + 1037 => x"0b", + 1038 => x"33", + 1039 => x"06", + 1040 => x"87", + 1041 => x"51", + 1042 => x"86", + 1043 => x"94", + 1044 => x"08", + 1045 => x"70", + 1046 => x"54", + 1047 => x"2e", + 1048 => x"91", + 1049 => x"06", + 1050 => x"d7", + 1051 => x"32", + 1052 => x"51", + 1053 => x"2e", + 1054 => x"93", + 1055 => x"06", + 1056 => x"ff", + 1057 => x"81", + 1058 => x"87", + 1059 => x"52", + 1060 => x"86", + 1061 => x"94", + 1062 => x"72", + 1063 => x"0d", + 1064 => x"0d", + 1065 => x"74", + 1066 => x"ff", + 1067 => x"57", + 1068 => x"80", + 1069 => x"81", + 1070 => x"15", + 1071 => x"db", + 1072 => x"81", + 1073 => x"57", + 1074 => x"c0", + 1075 => x"75", + 1076 => x"38", + 1077 => x"94", + 1078 => x"70", + 1079 => x"81", + 1080 => x"52", + 1081 => x"8c", + 1082 => x"2a", + 1083 => x"51", + 1084 => x"38", + 1085 => x"70", + 1086 => x"51", + 1087 => x"8d", + 1088 => x"2a", + 1089 => x"51", + 1090 => x"be", + 1091 => x"ff", + 1092 => x"c0", + 1093 => x"70", + 1094 => x"38", + 1095 => x"90", + 1096 => x"0c", + 1097 => x"33", + 1098 => x"06", + 1099 => x"70", + 1100 => x"76", + 1101 => x"0c", + 1102 => x"04", + 1103 => x"0b", + 1104 => x"88", + 1105 => x"ff", + 1106 => x"87", + 1107 => x"51", + 1108 => x"86", + 1109 => x"94", + 1110 => x"08", + 1111 => x"70", + 1112 => x"51", + 1113 => x"2e", + 1114 => x"81", + 1115 => x"87", + 1116 => x"52", + 1117 => x"86", + 1118 => x"94", + 1119 => x"08", + 1120 => x"06", + 1121 => x"0c", + 1122 => x"0d", + 1123 => x"0d", + 1124 => x"db", + 1125 => x"81", + 1126 => x"53", + 1127 => x"84", + 1128 => x"2e", + 1129 => x"c0", + 1130 => x"71", + 1131 => x"2a", + 1132 => x"51", + 1133 => x"52", + 1134 => x"a0", + 1135 => x"ff", + 1136 => x"c0", + 1137 => x"70", + 1138 => x"38", + 1139 => x"90", + 1140 => x"70", + 1141 => x"98", + 1142 => x"51", + 1143 => x"c0", + 1144 => x"0d", + 1145 => x"0d", + 1146 => x"80", + 1147 => x"2a", + 1148 => x"51", + 1149 => x"84", + 1150 => x"c0", + 1151 => x"81", + 1152 => x"87", + 1153 => x"08", + 1154 => x"0c", + 1155 => x"94", + 1156 => x"94", + 1157 => x"9e", + 1158 => x"db", + 1159 => x"c0", + 1160 => x"81", + 1161 => x"87", + 1162 => x"08", + 1163 => x"0c", + 1164 => x"ac", + 1165 => x"a4", + 1166 => x"9e", + 1167 => x"db", + 1168 => x"c0", + 1169 => x"81", + 1170 => x"87", + 1171 => x"08", + 1172 => x"0c", + 1173 => x"bc", + 1174 => x"b4", + 1175 => x"9e", + 1176 => x"db", + 1177 => x"c0", + 1178 => x"81", + 1179 => x"87", + 1180 => x"08", + 1181 => x"db", + 1182 => x"c0", + 1183 => x"81", + 1184 => x"87", + 1185 => x"08", + 1186 => x"0c", + 1187 => x"8c", + 1188 => x"cc", + 1189 => x"81", + 1190 => x"80", + 1191 => x"9e", + 1192 => x"84", + 1193 => x"51", + 1194 => x"80", + 1195 => x"81", + 1196 => x"db", + 1197 => x"0b", + 1198 => x"90", + 1199 => x"80", + 1200 => x"52", + 1201 => x"2e", + 1202 => x"52", + 1203 => x"d2", + 1204 => x"87", + 1205 => x"08", + 1206 => x"0a", + 1207 => x"52", + 1208 => x"83", + 1209 => x"71", + 1210 => x"34", + 1211 => x"c0", + 1212 => x"70", + 1213 => x"06", + 1214 => x"70", + 1215 => x"38", + 1216 => x"81", + 1217 => x"80", + 1218 => x"9e", + 1219 => x"a0", + 1220 => x"51", + 1221 => x"80", + 1222 => x"81", + 1223 => x"db", + 1224 => x"0b", + 1225 => x"90", + 1226 => x"80", + 1227 => x"52", + 1228 => x"2e", + 1229 => x"52", + 1230 => x"d6", + 1231 => x"87", + 1232 => x"08", + 1233 => x"80", + 1234 => x"52", + 1235 => x"83", + 1236 => x"71", + 1237 => x"34", + 1238 => x"c0", + 1239 => x"70", + 1240 => x"06", + 1241 => x"70", + 1242 => x"38", + 1243 => x"81", + 1244 => x"80", + 1245 => x"9e", + 1246 => x"81", + 1247 => x"51", + 1248 => x"80", + 1249 => x"81", + 1250 => x"db", + 1251 => x"0b", + 1252 => x"90", + 1253 => x"c0", + 1254 => x"52", + 1255 => x"2e", + 1256 => x"52", + 1257 => x"da", + 1258 => x"87", + 1259 => x"08", + 1260 => x"06", + 1261 => x"70", + 1262 => x"38", + 1263 => x"81", + 1264 => x"87", + 1265 => x"08", + 1266 => x"06", + 1267 => x"51", + 1268 => x"81", + 1269 => x"80", + 1270 => x"9e", + 1271 => x"84", + 1272 => x"52", + 1273 => x"2e", + 1274 => x"52", + 1275 => x"dd", + 1276 => x"9e", + 1277 => x"83", + 1278 => x"84", + 1279 => x"51", + 1280 => x"de", + 1281 => x"87", + 1282 => x"08", + 1283 => x"51", + 1284 => x"80", + 1285 => x"81", + 1286 => x"db", + 1287 => x"c0", + 1288 => x"70", + 1289 => x"51", + 1290 => x"e0", + 1291 => x"0d", + 1292 => x"0d", + 1293 => x"51", + 1294 => x"81", + 1295 => x"54", + 1296 => x"88", + 1297 => x"90", + 1298 => x"3f", + 1299 => x"51", + 1300 => x"81", + 1301 => x"54", + 1302 => x"93", + 1303 => x"ac", + 1304 => x"b0", + 1305 => x"52", + 1306 => x"51", + 1307 => x"81", + 1308 => x"54", + 1309 => x"93", + 1310 => x"a4", + 1311 => x"a8", + 1312 => x"52", + 1313 => x"51", + 1314 => x"81", + 1315 => x"54", + 1316 => x"93", + 1317 => x"8c", + 1318 => x"90", + 1319 => x"52", + 1320 => x"51", + 1321 => x"81", + 1322 => x"54", + 1323 => x"93", + 1324 => x"94", + 1325 => x"98", + 1326 => x"52", + 1327 => x"51", + 1328 => x"81", + 1329 => x"54", + 1330 => x"93", + 1331 => x"9c", + 1332 => x"a0", + 1333 => x"52", + 1334 => x"51", + 1335 => x"81", + 1336 => x"54", + 1337 => x"8d", + 1338 => x"dc", + 1339 => x"c8", + 1340 => x"b0", + 1341 => x"df", + 1342 => x"80", + 1343 => x"81", + 1344 => x"52", + 1345 => x"51", + 1346 => x"81", + 1347 => x"54", + 1348 => x"8d", + 1349 => x"de", + 1350 => x"c9", + 1351 => x"84", + 1352 => x"d1", + 1353 => x"80", + 1354 => x"81", + 1355 => x"84", + 1356 => x"db", + 1357 => x"73", + 1358 => x"38", + 1359 => x"51", + 1360 => x"81", + 1361 => x"54", + 1362 => x"88", + 1363 => x"c8", + 1364 => x"3f", + 1365 => x"33", + 1366 => x"2e", + 1367 => x"c9", + 1368 => x"dc", + 1369 => x"da", + 1370 => x"80", + 1371 => x"81", + 1372 => x"83", + 1373 => x"c9", + 1374 => x"c4", + 1375 => x"b4", + 1376 => x"c9", + 1377 => x"9c", + 1378 => x"b8", + 1379 => x"ca", + 1380 => x"90", + 1381 => x"bc", + 1382 => x"ca", + 1383 => x"84", + 1384 => x"f0", + 1385 => x"3f", + 1386 => x"22", + 1387 => x"f8", + 1388 => x"3f", + 1389 => x"08", + 1390 => x"c0", + 1391 => x"e7", + 1392 => x"de", + 1393 => x"84", + 1394 => x"71", + 1395 => x"81", + 1396 => x"52", + 1397 => x"51", + 1398 => x"81", + 1399 => x"54", + 1400 => x"a8", + 1401 => x"c8", + 1402 => x"84", + 1403 => x"51", + 1404 => x"81", + 1405 => x"bd", + 1406 => x"76", + 1407 => x"54", + 1408 => x"08", + 1409 => x"cc", + 1410 => x"3f", + 1411 => x"33", + 1412 => x"2e", + 1413 => x"db", + 1414 => x"bd", + 1415 => x"75", + 1416 => x"3f", + 1417 => x"08", + 1418 => x"29", + 1419 => x"54", + 1420 => x"c0", + 1421 => x"cb", + 1422 => x"e8", + 1423 => x"9c", + 1424 => x"3f", + 1425 => x"04", + 1426 => x"02", + 1427 => x"ff", + 1428 => x"84", + 1429 => x"71", + 1430 => x"c6", + 1431 => x"71", + 1432 => x"cc", + 1433 => x"39", + 1434 => x"51", + 1435 => x"cc", + 1436 => x"39", + 1437 => x"51", + 1438 => x"cc", + 1439 => x"39", + 1440 => x"51", + 1441 => x"84", + 1442 => x"71", + 1443 => x"04", + 1444 => x"c0", + 1445 => x"04", + 1446 => x"87", + 1447 => x"70", + 1448 => x"80", + 1449 => x"74", + 1450 => x"db", + 1451 => x"0c", + 1452 => x"04", + 1453 => x"87", + 1454 => x"70", + 1455 => x"e4", + 1456 => x"72", + 1457 => x"70", + 1458 => x"08", + 1459 => x"db", + 1460 => x"0c", + 1461 => x"0d", + 1462 => x"e4", + 1463 => x"96", + 1464 => x"fe", + 1465 => x"93", + 1466 => x"72", + 1467 => x"81", + 1468 => x"8d", + 1469 => x"81", + 1470 => x"52", + 1471 => x"90", + 1472 => x"34", + 1473 => x"08", + 1474 => x"de", + 1475 => x"39", + 1476 => x"08", + 1477 => x"2e", + 1478 => x"51", + 1479 => x"3d", + 1480 => x"3d", + 1481 => x"05", + 1482 => x"d0", + 1483 => x"de", + 1484 => x"51", + 1485 => x"72", + 1486 => x"0c", + 1487 => x"04", + 1488 => x"75", + 1489 => x"70", + 1490 => x"53", + 1491 => x"2e", + 1492 => x"81", + 1493 => x"81", + 1494 => x"87", + 1495 => x"85", + 1496 => x"fc", + 1497 => x"81", + 1498 => x"78", + 1499 => x"0c", + 1500 => x"33", + 1501 => x"06", + 1502 => x"80", + 1503 => x"72", + 1504 => x"51", + 1505 => x"fe", + 1506 => x"39", + 1507 => x"d0", + 1508 => x"0d", + 1509 => x"0d", + 1510 => x"59", + 1511 => x"05", + 1512 => x"75", + 1513 => x"f8", + 1514 => x"2e", + 1515 => x"82", + 1516 => x"70", + 1517 => x"05", + 1518 => x"5b", + 1519 => x"2e", + 1520 => x"85", + 1521 => x"8b", + 1522 => x"2e", + 1523 => x"8a", + 1524 => x"78", + 1525 => x"5a", + 1526 => x"aa", + 1527 => x"06", + 1528 => x"84", + 1529 => x"7b", + 1530 => x"5d", + 1531 => x"59", + 1532 => x"d0", + 1533 => x"89", + 1534 => x"7a", + 1535 => x"10", + 1536 => x"d0", + 1537 => x"81", + 1538 => x"57", + 1539 => x"75", + 1540 => x"70", + 1541 => x"07", + 1542 => x"80", + 1543 => x"30", + 1544 => x"80", + 1545 => x"53", + 1546 => x"55", + 1547 => x"2e", + 1548 => x"84", + 1549 => x"81", + 1550 => x"57", + 1551 => x"2e", + 1552 => x"75", + 1553 => x"76", + 1554 => x"e0", + 1555 => x"ff", + 1556 => x"73", + 1557 => x"81", + 1558 => x"80", + 1559 => x"38", + 1560 => x"2e", + 1561 => x"73", + 1562 => x"8b", + 1563 => x"c2", + 1564 => x"38", + 1565 => x"73", + 1566 => x"81", + 1567 => x"8f", + 1568 => x"d5", + 1569 => x"38", + 1570 => x"24", + 1571 => x"80", + 1572 => x"38", + 1573 => x"73", + 1574 => x"80", + 1575 => x"ef", + 1576 => x"19", + 1577 => x"59", + 1578 => x"33", + 1579 => x"75", + 1580 => x"81", + 1581 => x"70", + 1582 => x"55", + 1583 => x"79", + 1584 => x"90", + 1585 => x"16", + 1586 => x"7b", + 1587 => x"a0", + 1588 => x"3f", + 1589 => x"53", + 1590 => x"e9", + 1591 => x"fc", + 1592 => x"81", + 1593 => x"72", + 1594 => x"b0", + 1595 => x"fb", + 1596 => x"39", + 1597 => x"83", + 1598 => x"59", + 1599 => x"82", + 1600 => x"88", + 1601 => x"8a", + 1602 => x"90", + 1603 => x"75", + 1604 => x"3f", + 1605 => x"79", + 1606 => x"81", + 1607 => x"72", + 1608 => x"38", + 1609 => x"59", + 1610 => x"84", + 1611 => x"58", + 1612 => x"80", + 1613 => x"30", + 1614 => x"80", + 1615 => x"55", + 1616 => x"25", + 1617 => x"80", + 1618 => x"74", + 1619 => x"07", + 1620 => x"0b", + 1621 => x"57", + 1622 => x"51", + 1623 => x"81", + 1624 => x"81", + 1625 => x"53", + 1626 => x"e0", + 1627 => x"de", + 1628 => x"89", + 1629 => x"38", + 1630 => x"75", + 1631 => x"84", + 1632 => x"53", + 1633 => x"06", + 1634 => x"53", + 1635 => x"81", + 1636 => x"81", + 1637 => x"70", + 1638 => x"2a", + 1639 => x"76", + 1640 => x"38", + 1641 => x"38", + 1642 => x"70", + 1643 => x"53", + 1644 => x"8e", + 1645 => x"77", + 1646 => x"53", + 1647 => x"81", + 1648 => x"7a", + 1649 => x"55", + 1650 => x"83", + 1651 => x"79", + 1652 => x"81", + 1653 => x"72", + 1654 => x"17", + 1655 => x"27", + 1656 => x"51", + 1657 => x"75", + 1658 => x"72", + 1659 => x"81", + 1660 => x"7a", + 1661 => x"38", + 1662 => x"05", + 1663 => x"ff", + 1664 => x"70", + 1665 => x"57", + 1666 => x"76", + 1667 => x"81", + 1668 => x"72", + 1669 => x"84", + 1670 => x"f9", + 1671 => x"39", + 1672 => x"04", + 1673 => x"86", + 1674 => x"84", + 1675 => x"55", + 1676 => x"fa", + 1677 => x"3d", + 1678 => x"3d", + 1679 => x"de", + 1680 => x"3d", + 1681 => x"75", + 1682 => x"3f", + 1683 => x"08", + 1684 => x"34", + 1685 => x"de", + 1686 => x"3d", + 1687 => x"3d", + 1688 => x"d0", + 1689 => x"de", + 1690 => x"3d", + 1691 => x"77", + 1692 => x"a1", + 1693 => x"de", + 1694 => x"3d", + 1695 => x"3d", + 1696 => x"81", + 1697 => x"70", + 1698 => x"55", + 1699 => x"80", + 1700 => x"38", + 1701 => x"08", + 1702 => x"81", + 1703 => x"81", + 1704 => x"72", + 1705 => x"cb", + 1706 => x"2e", + 1707 => x"88", + 1708 => x"70", + 1709 => x"51", + 1710 => x"2e", + 1711 => x"80", + 1712 => x"ff", + 1713 => x"39", + 1714 => x"c8", + 1715 => x"52", + 1716 => x"c0", + 1717 => x"52", + 1718 => x"81", + 1719 => x"51", + 1720 => x"ff", + 1721 => x"15", + 1722 => x"34", + 1723 => x"f3", + 1724 => x"72", + 1725 => x"0c", + 1726 => x"04", + 1727 => x"81", + 1728 => x"75", + 1729 => x"0c", + 1730 => x"52", + 1731 => x"3f", + 1732 => x"d4", + 1733 => x"0d", + 1734 => x"0d", + 1735 => x"56", + 1736 => x"0c", + 1737 => x"70", + 1738 => x"73", + 1739 => x"81", + 1740 => x"81", + 1741 => x"ed", + 1742 => x"2e", + 1743 => x"8e", + 1744 => x"08", + 1745 => x"76", + 1746 => x"56", + 1747 => x"b0", + 1748 => x"06", + 1749 => x"75", + 1750 => x"76", + 1751 => x"70", + 1752 => x"73", + 1753 => x"8b", + 1754 => x"73", + 1755 => x"85", + 1756 => x"82", + 1757 => x"76", + 1758 => x"70", + 1759 => x"ac", + 1760 => x"a0", + 1761 => x"fa", + 1762 => x"53", + 1763 => x"57", + 1764 => x"98", + 1765 => x"39", + 1766 => x"80", + 1767 => x"26", + 1768 => x"86", + 1769 => x"80", + 1770 => x"57", + 1771 => x"74", + 1772 => x"38", + 1773 => x"27", + 1774 => x"14", + 1775 => x"06", + 1776 => x"14", + 1777 => x"06", + 1778 => x"74", + 1779 => x"f9", + 1780 => x"ff", + 1781 => x"89", + 1782 => x"38", + 1783 => x"c5", + 1784 => x"29", + 1785 => x"81", + 1786 => x"76", + 1787 => x"56", + 1788 => x"ba", + 1789 => x"2e", + 1790 => x"30", + 1791 => x"0c", + 1792 => x"81", + 1793 => x"8a", + 1794 => x"f8", + 1795 => x"7c", + 1796 => x"70", + 1797 => x"75", + 1798 => x"55", + 1799 => x"2e", + 1800 => x"87", + 1801 => x"76", + 1802 => x"73", + 1803 => x"81", + 1804 => x"81", + 1805 => x"77", + 1806 => x"70", + 1807 => x"58", + 1808 => x"09", + 1809 => x"c2", + 1810 => x"81", + 1811 => x"75", + 1812 => x"55", + 1813 => x"e2", + 1814 => x"90", + 1815 => x"f8", + 1816 => x"8f", + 1817 => x"81", + 1818 => x"75", + 1819 => x"55", + 1820 => x"81", + 1821 => x"27", + 1822 => x"d0", + 1823 => x"55", + 1824 => x"73", + 1825 => x"80", + 1826 => x"14", + 1827 => x"72", + 1828 => x"e0", + 1829 => x"80", + 1830 => x"39", + 1831 => x"55", + 1832 => x"80", + 1833 => x"e0", + 1834 => x"38", + 1835 => x"81", + 1836 => x"53", + 1837 => x"81", + 1838 => x"53", + 1839 => x"8e", + 1840 => x"70", + 1841 => x"55", + 1842 => x"27", + 1843 => x"77", + 1844 => x"74", + 1845 => x"76", + 1846 => x"77", + 1847 => x"70", + 1848 => x"55", + 1849 => x"77", + 1850 => x"38", + 1851 => x"74", + 1852 => x"55", + 1853 => x"c0", + 1854 => x"0d", + 1855 => x"0d", + 1856 => x"33", + 1857 => x"70", + 1858 => x"38", + 1859 => x"11", + 1860 => x"81", + 1861 => x"83", + 1862 => x"fc", + 1863 => x"9b", + 1864 => x"84", + 1865 => x"33", + 1866 => x"51", + 1867 => x"80", + 1868 => x"84", + 1869 => x"92", + 1870 => x"51", + 1871 => x"80", + 1872 => x"81", + 1873 => x"72", + 1874 => x"92", + 1875 => x"81", + 1876 => x"0b", + 1877 => x"8c", + 1878 => x"71", + 1879 => x"06", + 1880 => x"80", + 1881 => x"87", + 1882 => x"08", + 1883 => x"38", + 1884 => x"80", + 1885 => x"71", + 1886 => x"c0", + 1887 => x"51", + 1888 => x"87", + 1889 => x"db", + 1890 => x"81", + 1891 => x"33", + 1892 => x"de", + 1893 => x"3d", + 1894 => x"3d", + 1895 => x"64", + 1896 => x"bf", + 1897 => x"40", + 1898 => x"74", + 1899 => x"cd", + 1900 => x"c0", + 1901 => x"7a", + 1902 => x"81", + 1903 => x"72", + 1904 => x"87", + 1905 => x"11", + 1906 => x"8c", + 1907 => x"92", + 1908 => x"5a", + 1909 => x"58", + 1910 => x"c0", + 1911 => x"76", + 1912 => x"76", + 1913 => x"70", + 1914 => x"81", + 1915 => x"54", + 1916 => x"8e", + 1917 => x"52", + 1918 => x"81", + 1919 => x"81", + 1920 => x"74", + 1921 => x"53", + 1922 => x"83", + 1923 => x"78", + 1924 => x"8f", + 1925 => x"2e", + 1926 => x"c0", + 1927 => x"52", + 1928 => x"87", + 1929 => x"08", + 1930 => x"2e", + 1931 => x"84", + 1932 => x"38", + 1933 => x"87", + 1934 => x"15", + 1935 => x"70", + 1936 => x"52", + 1937 => x"ff", + 1938 => x"39", + 1939 => x"81", + 1940 => x"ff", + 1941 => x"57", + 1942 => x"90", + 1943 => x"80", + 1944 => x"71", + 1945 => x"78", + 1946 => x"38", + 1947 => x"80", + 1948 => x"80", + 1949 => x"81", + 1950 => x"72", + 1951 => x"0c", + 1952 => x"04", + 1953 => x"60", + 1954 => x"8c", + 1955 => x"33", + 1956 => x"5b", + 1957 => x"74", + 1958 => x"e1", + 1959 => x"c0", + 1960 => x"79", + 1961 => x"78", + 1962 => x"06", + 1963 => x"77", + 1964 => x"87", + 1965 => x"11", + 1966 => x"8c", + 1967 => x"92", + 1968 => x"59", + 1969 => x"85", + 1970 => x"98", + 1971 => x"7d", + 1972 => x"0c", + 1973 => x"08", + 1974 => x"70", + 1975 => x"53", + 1976 => x"2e", + 1977 => x"70", + 1978 => x"33", + 1979 => x"18", + 1980 => x"2a", + 1981 => x"51", + 1982 => x"2e", + 1983 => x"c0", + 1984 => x"52", + 1985 => x"87", + 1986 => x"08", + 1987 => x"2e", + 1988 => x"84", + 1989 => x"38", + 1990 => x"87", + 1991 => x"15", + 1992 => x"70", + 1993 => x"52", + 1994 => x"ff", + 1995 => x"39", + 1996 => x"81", + 1997 => x"80", + 1998 => x"52", + 1999 => x"90", + 2000 => x"80", + 2001 => x"71", + 2002 => x"7a", + 2003 => x"38", + 2004 => x"80", + 2005 => x"80", + 2006 => x"81", + 2007 => x"72", + 2008 => x"0c", + 2009 => x"04", + 2010 => x"7e", + 2011 => x"b3", + 2012 => x"88", + 2013 => x"33", + 2014 => x"56", + 2015 => x"3f", + 2016 => x"08", + 2017 => x"83", + 2018 => x"fe", + 2019 => x"87", + 2020 => x"0c", + 2021 => x"76", + 2022 => x"38", + 2023 => x"93", + 2024 => x"2b", + 2025 => x"8c", + 2026 => x"71", + 2027 => x"38", + 2028 => x"71", + 2029 => x"c6", + 2030 => x"39", + 2031 => x"81", + 2032 => x"06", + 2033 => x"71", + 2034 => x"38", + 2035 => x"8c", + 2036 => x"e8", + 2037 => x"98", + 2038 => x"71", + 2039 => x"73", + 2040 => x"92", + 2041 => x"72", + 2042 => x"06", + 2043 => x"f7", + 2044 => x"80", + 2045 => x"88", + 2046 => x"0c", + 2047 => x"80", + 2048 => x"56", + 2049 => x"56", + 2050 => x"81", + 2051 => x"8c", + 2052 => x"fe", + 2053 => x"81", + 2054 => x"33", + 2055 => x"07", + 2056 => x"0c", + 2057 => x"3d", + 2058 => x"3d", + 2059 => x"11", + 2060 => x"33", + 2061 => x"71", + 2062 => x"81", + 2063 => x"72", + 2064 => x"75", + 2065 => x"81", + 2066 => x"52", + 2067 => x"54", + 2068 => x"0d", + 2069 => x"0d", + 2070 => x"05", + 2071 => x"52", + 2072 => x"70", + 2073 => x"34", + 2074 => x"51", + 2075 => x"83", + 2076 => x"ff", + 2077 => x"75", + 2078 => x"72", + 2079 => x"54", + 2080 => x"2a", + 2081 => x"70", + 2082 => x"34", + 2083 => x"51", + 2084 => x"81", + 2085 => x"70", + 2086 => x"70", + 2087 => x"3d", + 2088 => x"3d", + 2089 => x"77", + 2090 => x"70", + 2091 => x"38", + 2092 => x"05", + 2093 => x"70", + 2094 => x"34", + 2095 => x"eb", + 2096 => x"0d", + 2097 => x"0d", + 2098 => x"54", + 2099 => x"72", + 2100 => x"54", + 2101 => x"51", + 2102 => x"84", + 2103 => x"fc", + 2104 => x"77", + 2105 => x"53", + 2106 => x"05", + 2107 => x"70", + 2108 => x"33", + 2109 => x"ff", + 2110 => x"52", + 2111 => x"2e", + 2112 => x"80", + 2113 => x"71", + 2114 => x"0c", + 2115 => x"04", + 2116 => x"74", + 2117 => x"89", + 2118 => x"2e", + 2119 => x"11", + 2120 => x"52", + 2121 => x"70", + 2122 => x"c0", + 2123 => x"0d", + 2124 => x"81", + 2125 => x"04", + 2126 => x"de", + 2127 => x"f7", + 2128 => x"56", + 2129 => x"17", + 2130 => x"74", + 2131 => x"d6", + 2132 => x"b0", + 2133 => x"b4", + 2134 => x"81", + 2135 => x"59", + 2136 => x"81", + 2137 => x"7a", + 2138 => x"06", + 2139 => x"de", + 2140 => x"17", + 2141 => x"08", + 2142 => x"08", + 2143 => x"08", + 2144 => x"74", + 2145 => x"38", + 2146 => x"55", + 2147 => x"09", + 2148 => x"38", + 2149 => x"18", + 2150 => x"81", + 2151 => x"f9", + 2152 => x"39", + 2153 => x"81", + 2154 => x"8b", + 2155 => x"fa", + 2156 => x"7a", + 2157 => x"57", + 2158 => x"08", + 2159 => x"75", + 2160 => x"3f", + 2161 => x"08", + 2162 => x"c0", + 2163 => x"81", + 2164 => x"b4", + 2165 => x"16", + 2166 => x"be", + 2167 => x"c0", + 2168 => x"85", + 2169 => x"81", + 2170 => x"17", + 2171 => x"de", + 2172 => x"3d", + 2173 => x"3d", + 2174 => x"52", + 2175 => x"3f", + 2176 => x"08", + 2177 => x"c0", + 2178 => x"38", + 2179 => x"74", + 2180 => x"81", + 2181 => x"38", + 2182 => x"59", + 2183 => x"09", + 2184 => x"e3", + 2185 => x"53", + 2186 => x"08", + 2187 => x"70", + 2188 => x"91", + 2189 => x"d5", + 2190 => x"17", + 2191 => x"3f", + 2192 => x"a4", + 2193 => x"51", + 2194 => x"86", + 2195 => x"f2", + 2196 => x"17", + 2197 => x"3f", + 2198 => x"52", + 2199 => x"51", + 2200 => x"8c", + 2201 => x"84", + 2202 => x"fc", + 2203 => x"17", + 2204 => x"70", + 2205 => x"79", + 2206 => x"52", + 2207 => x"51", + 2208 => x"77", + 2209 => x"80", + 2210 => x"81", + 2211 => x"f9", + 2212 => x"de", + 2213 => x"2e", + 2214 => x"58", + 2215 => x"c0", + 2216 => x"0d", + 2217 => x"0d", + 2218 => x"98", + 2219 => x"05", + 2220 => x"80", + 2221 => x"27", + 2222 => x"14", + 2223 => x"29", + 2224 => x"05", + 2225 => x"81", + 2226 => x"87", + 2227 => x"f9", + 2228 => x"7a", + 2229 => x"54", + 2230 => x"27", + 2231 => x"76", + 2232 => x"27", + 2233 => x"ff", + 2234 => x"58", + 2235 => x"80", + 2236 => x"82", + 2237 => x"72", + 2238 => x"38", + 2239 => x"72", + 2240 => x"8e", + 2241 => x"39", + 2242 => x"17", + 2243 => x"a4", + 2244 => x"53", + 2245 => x"fd", + 2246 => x"de", + 2247 => x"9f", + 2248 => x"ff", + 2249 => x"11", + 2250 => x"70", + 2251 => x"18", + 2252 => x"76", + 2253 => x"53", + 2254 => x"81", + 2255 => x"80", + 2256 => x"83", + 2257 => x"b4", + 2258 => x"88", + 2259 => x"79", + 2260 => x"84", + 2261 => x"58", + 2262 => x"80", + 2263 => x"9f", + 2264 => x"80", + 2265 => x"88", + 2266 => x"08", + 2267 => x"51", + 2268 => x"81", + 2269 => x"80", + 2270 => x"10", + 2271 => x"74", + 2272 => x"51", + 2273 => x"81", + 2274 => x"83", + 2275 => x"58", + 2276 => x"87", + 2277 => x"08", + 2278 => x"51", + 2279 => x"81", + 2280 => x"9b", + 2281 => x"2b", + 2282 => x"74", + 2283 => x"51", + 2284 => x"81", + 2285 => x"f0", + 2286 => x"83", + 2287 => x"77", + 2288 => x"0c", + 2289 => x"04", + 2290 => x"7a", + 2291 => x"58", + 2292 => x"81", + 2293 => x"9e", + 2294 => x"17", + 2295 => x"96", + 2296 => x"53", + 2297 => x"81", + 2298 => x"79", + 2299 => x"72", + 2300 => x"38", + 2301 => x"72", + 2302 => x"b8", + 2303 => x"39", + 2304 => x"17", + 2305 => x"a4", + 2306 => x"53", + 2307 => x"fb", + 2308 => x"de", + 2309 => x"81", + 2310 => x"81", + 2311 => x"83", + 2312 => x"b4", + 2313 => x"78", + 2314 => x"56", + 2315 => x"76", + 2316 => x"38", + 2317 => x"9f", + 2318 => x"33", + 2319 => x"07", + 2320 => x"74", + 2321 => x"83", + 2322 => x"89", + 2323 => x"08", + 2324 => x"51", + 2325 => x"81", + 2326 => x"59", + 2327 => x"08", + 2328 => x"74", + 2329 => x"16", + 2330 => x"84", + 2331 => x"76", + 2332 => x"88", + 2333 => x"81", + 2334 => x"8f", + 2335 => x"53", + 2336 => x"80", + 2337 => x"88", + 2338 => x"08", + 2339 => x"51", + 2340 => x"81", + 2341 => x"59", + 2342 => x"08", + 2343 => x"77", + 2344 => x"06", + 2345 => x"83", + 2346 => x"05", + 2347 => x"f7", + 2348 => x"39", + 2349 => x"a4", + 2350 => x"52", + 2351 => x"ef", + 2352 => x"c0", + 2353 => x"de", + 2354 => x"38", + 2355 => x"06", + 2356 => x"83", + 2357 => x"18", + 2358 => x"54", + 2359 => x"f6", + 2360 => x"de", + 2361 => x"0a", + 2362 => x"52", + 2363 => x"83", + 2364 => x"83", + 2365 => x"81", + 2366 => x"8a", + 2367 => x"f8", + 2368 => x"7c", + 2369 => x"59", + 2370 => x"81", + 2371 => x"38", + 2372 => x"08", + 2373 => x"73", + 2374 => x"38", + 2375 => x"52", + 2376 => x"a4", + 2377 => x"c0", + 2378 => x"de", + 2379 => x"f2", + 2380 => x"82", + 2381 => x"39", + 2382 => x"e6", + 2383 => x"c0", + 2384 => x"de", + 2385 => x"78", + 2386 => x"3f", + 2387 => x"08", + 2388 => x"c0", + 2389 => x"80", + 2390 => x"de", + 2391 => x"2e", + 2392 => x"de", + 2393 => x"2e", + 2394 => x"53", + 2395 => x"51", + 2396 => x"81", + 2397 => x"c5", + 2398 => x"08", + 2399 => x"18", + 2400 => x"57", + 2401 => x"90", + 2402 => x"90", + 2403 => x"16", + 2404 => x"54", + 2405 => x"34", + 2406 => x"78", + 2407 => x"38", + 2408 => x"81", + 2409 => x"8a", + 2410 => x"f6", + 2411 => x"7e", + 2412 => x"5b", + 2413 => x"38", + 2414 => x"58", + 2415 => x"88", + 2416 => x"08", + 2417 => x"38", + 2418 => x"39", + 2419 => x"51", + 2420 => x"81", + 2421 => x"de", + 2422 => x"82", + 2423 => x"de", + 2424 => x"81", + 2425 => x"ff", + 2426 => x"38", + 2427 => x"81", + 2428 => x"26", + 2429 => x"79", + 2430 => x"08", + 2431 => x"73", + 2432 => x"b9", + 2433 => x"2e", + 2434 => x"80", + 2435 => x"1a", + 2436 => x"08", + 2437 => x"38", + 2438 => x"52", + 2439 => x"af", + 2440 => x"81", + 2441 => x"81", + 2442 => x"06", + 2443 => x"de", + 2444 => x"81", + 2445 => x"09", + 2446 => x"72", + 2447 => x"70", + 2448 => x"de", + 2449 => x"51", + 2450 => x"73", + 2451 => x"81", + 2452 => x"80", + 2453 => x"8c", + 2454 => x"81", + 2455 => x"38", + 2456 => x"08", + 2457 => x"73", + 2458 => x"75", + 2459 => x"77", + 2460 => x"56", + 2461 => x"76", + 2462 => x"82", + 2463 => x"26", + 2464 => x"75", + 2465 => x"f8", + 2466 => x"de", + 2467 => x"2e", + 2468 => x"59", + 2469 => x"08", + 2470 => x"81", + 2471 => x"81", + 2472 => x"59", + 2473 => x"08", + 2474 => x"70", + 2475 => x"25", + 2476 => x"51", + 2477 => x"73", + 2478 => x"75", + 2479 => x"81", + 2480 => x"38", + 2481 => x"f5", + 2482 => x"75", + 2483 => x"f9", + 2484 => x"de", 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x"3d", + 2544 => x"71", + 2545 => x"57", + 2546 => x"0a", + 2547 => x"38", + 2548 => x"53", + 2549 => x"38", + 2550 => x"0c", + 2551 => x"54", + 2552 => x"75", + 2553 => x"73", + 2554 => x"a8", + 2555 => x"73", + 2556 => x"85", + 2557 => x"0b", + 2558 => x"5a", + 2559 => x"27", + 2560 => x"a8", + 2561 => x"18", + 2562 => x"39", + 2563 => x"70", + 2564 => x"58", + 2565 => x"b2", + 2566 => x"76", + 2567 => x"3f", + 2568 => x"08", + 2569 => x"c0", + 2570 => x"bd", + 2571 => x"81", + 2572 => x"27", + 2573 => x"16", + 2574 => x"c0", + 2575 => x"38", + 2576 => x"39", + 2577 => x"55", + 2578 => x"52", + 2579 => x"d5", + 2580 => x"c0", + 2581 => x"0c", + 2582 => x"0c", + 2583 => x"53", + 2584 => x"80", + 2585 => x"85", + 2586 => x"94", + 2587 => x"2a", + 2588 => x"0c", + 2589 => x"06", + 2590 => x"9c", + 2591 => x"58", + 2592 => x"c0", + 2593 => x"0d", + 2594 => x"0d", + 2595 => x"90", + 2596 => x"05", + 2597 => x"f0", + 2598 => x"27", + 2599 => x"0b", + 2600 => x"98", + 2601 => x"84", + 2602 => x"2e", + 2603 => x"76", + 2604 => x"58", + 2605 => x"38", + 2606 => x"15", + 2607 => x"08", + 2608 => x"38", + 2609 => x"88", + 2610 => x"53", + 2611 => x"81", + 2612 => x"c0", + 2613 => x"22", + 2614 => x"89", + 2615 => x"72", + 2616 => x"74", + 2617 => x"f3", + 2618 => x"de", + 2619 => x"82", + 2620 => x"81", + 2621 => x"27", + 2622 => x"81", + 2623 => x"c0", + 2624 => x"80", + 2625 => x"16", + 2626 => x"c0", + 2627 => x"ca", + 2628 => x"38", + 2629 => x"0c", + 2630 => x"dd", + 2631 => x"08", + 2632 => x"f9", + 2633 => x"de", + 2634 => x"87", + 2635 => x"c0", + 2636 => x"80", + 2637 => x"55", + 2638 => x"08", + 2639 => x"38", + 2640 => x"de", + 2641 => x"2e", + 2642 => x"de", + 2643 => x"75", + 2644 => x"3f", + 2645 => x"08", + 2646 => x"94", + 2647 => x"52", + 2648 => x"c1", + 2649 => x"c0", + 2650 => x"0c", + 2651 => x"0c", + 2652 => x"05", + 2653 => x"80", + 2654 => x"de", + 2655 => x"3d", + 2656 => x"3d", + 2657 => x"71", + 2658 => x"57", + 2659 => x"51", + 2660 => x"81", + 2661 => x"54", + 2662 => x"08", + 2663 => x"81", + 2664 => x"56", + 2665 => x"52", + 2666 => x"83", + 2667 => x"c0", + 2668 => x"de", + 2669 => x"d2", + 2670 => x"c0", + 2671 => x"08", + 2672 => x"54", + 2673 => x"e5", + 2674 => x"06", + 2675 => x"58", + 2676 => x"08", + 2677 => x"38", + 2678 => x"75", + 2679 => x"80", + 2680 => x"81", + 2681 => x"7a", + 2682 => x"06", + 2683 => x"39", + 2684 => x"08", + 2685 => x"76", + 2686 => x"3f", + 2687 => x"08", + 2688 => x"c0", + 2689 => x"ff", + 2690 => x"84", + 2691 => x"06", + 2692 => x"54", + 2693 => x"c0", + 2694 => x"0d", + 2695 => x"0d", + 2696 => x"52", + 2697 => x"3f", + 2698 => x"08", + 2699 => x"06", + 2700 => x"51", + 2701 => x"83", + 2702 => x"06", + 2703 => x"14", + 2704 => x"3f", + 2705 => x"08", + 2706 => x"07", + 2707 => x"de", + 2708 => x"3d", + 2709 => x"3d", + 2710 => x"70", + 2711 => x"06", + 2712 => x"53", + 2713 => x"ed", + 2714 => x"33", + 2715 => x"83", + 2716 => x"06", + 2717 => x"90", + 2718 => x"15", + 2719 => x"3f", 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x"8b", + 2779 => x"52", + 2780 => x"51", + 2781 => x"81", + 2782 => x"34", + 2783 => x"c0", + 2784 => x"0d", + 2785 => x"0d", + 2786 => x"98", + 2787 => x"70", + 2788 => x"ec", + 2789 => x"de", + 2790 => x"38", + 2791 => x"53", + 2792 => x"81", + 2793 => x"34", + 2794 => x"04", + 2795 => x"78", + 2796 => x"80", + 2797 => x"34", + 2798 => x"80", + 2799 => x"38", + 2800 => x"18", + 2801 => x"9c", + 2802 => x"70", + 2803 => x"56", + 2804 => x"a0", + 2805 => x"71", + 2806 => x"81", + 2807 => x"81", + 2808 => x"89", + 2809 => x"06", + 2810 => x"73", + 2811 => x"55", + 2812 => x"55", + 2813 => x"81", + 2814 => x"81", + 2815 => x"74", + 2816 => x"75", + 2817 => x"52", + 2818 => x"13", + 2819 => x"08", + 2820 => x"33", + 2821 => x"9c", + 2822 => x"11", + 2823 => x"8a", + 2824 => x"c0", + 2825 => x"96", + 2826 => x"e7", + 2827 => x"c0", + 2828 => x"23", + 2829 => x"e7", + 2830 => x"de", + 2831 => x"17", + 2832 => x"0d", + 2833 => x"0d", + 2834 => x"5e", + 2835 => x"70", + 2836 => x"55", + 2837 => x"83", + 2838 => x"73", + 2839 => x"91", + 2840 => x"2e", + 2841 => x"1d", + 2842 => x"0c", + 2843 => x"15", + 2844 => x"70", + 2845 => x"56", + 2846 => x"09", + 2847 => x"38", + 2848 => x"80", + 2849 => x"30", + 2850 => x"78", + 2851 => x"54", + 2852 => x"73", + 2853 => x"60", + 2854 => x"54", + 2855 => x"96", + 2856 => x"0b", + 2857 => x"80", + 2858 => x"f6", + 2859 => x"de", + 2860 => x"85", + 2861 => x"3d", + 2862 => x"5c", + 2863 => x"53", + 2864 => x"51", + 2865 => x"80", + 2866 => x"88", + 2867 => x"5c", + 2868 => x"09", + 2869 => x"d4", + 2870 => x"70", + 2871 => x"71", + 2872 => x"30", + 2873 => x"73", + 2874 => x"51", + 2875 => x"57", + 2876 => x"38", + 2877 => x"75", + 2878 => x"17", + 2879 => x"75", + 2880 => x"30", + 2881 => x"51", + 2882 => x"80", + 2883 => x"38", + 2884 => x"87", + 2885 => x"26", + 2886 => x"77", + 2887 => x"a4", + 2888 => x"27", + 2889 => x"a0", + 2890 => x"39", + 2891 => x"33", + 2892 => x"57", + 2893 => x"27", + 2894 => x"75", + 2895 => x"30", + 2896 => x"32", + 2897 => x"80", + 2898 => x"25", + 2899 => x"56", + 2900 => x"80", + 2901 => x"84", + 2902 => x"58", + 2903 => x"70", + 2904 => x"55", + 2905 => x"09", + 2906 => x"38", + 2907 => x"80", + 2908 => x"30", + 2909 => x"77", + 2910 => x"54", + 2911 => x"81", + 2912 => x"ae", + 2913 => x"06", + 2914 => x"54", + 2915 => x"74", + 2916 => x"80", + 2917 => x"7b", + 2918 => x"30", + 2919 => x"70", + 2920 => x"25", + 2921 => x"07", + 2922 => x"51", + 2923 => x"a7", + 2924 => x"8b", + 2925 => x"39", + 2926 => x"54", + 2927 => x"8c", + 2928 => x"ff", + 2929 => x"b4", + 2930 => x"54", + 2931 => x"e1", + 2932 => x"c0", + 2933 => x"b2", + 2934 => x"70", + 2935 => x"71", + 2936 => x"54", + 2937 => x"81", + 2938 => x"80", + 2939 => x"38", + 2940 => x"76", + 2941 => x"df", + 2942 => x"54", + 2943 => x"81", + 2944 => x"55", + 2945 => x"34", + 2946 => x"52", + 2947 => x"51", + 2948 => x"81", + 2949 => x"bf", + 2950 => x"16", + 2951 => x"26", + 2952 => x"16", + 2953 => x"06", + 2954 => x"17", + 2955 => x"34", + 2956 => x"fd", + 2957 => x"19", + 2958 => x"80", + 2959 => x"79", + 2960 => x"81", + 2961 => x"81", + 2962 => x"85", + 2963 => x"54", + 2964 => x"8f", + 2965 => x"86", + 2966 => x"39", + 2967 => x"f3", + 2968 => x"73", + 2969 => x"80", + 2970 => x"52", + 2971 => x"ce", + 2972 => x"c0", + 2973 => x"de", + 2974 => x"d7", + 2975 => x"08", + 2976 => x"e6", + 2977 => x"de", + 2978 => x"81", + 2979 => x"80", + 2980 => x"1b", + 2981 => x"55", + 2982 => x"2e", + 2983 => x"8b", + 2984 => x"06", + 2985 => x"1c", + 2986 => x"33", + 2987 => x"70", + 2988 => x"55", + 2989 => x"38", + 2990 => x"52", + 2991 => x"9f", + 2992 => x"c0", + 2993 => x"8b", + 2994 => x"7a", + 2995 => x"3f", + 2996 => x"75", + 2997 => x"57", + 2998 => x"2e", + 2999 => x"84", + 3000 => x"06", + 3001 => x"75", + 3002 => x"81", + 3003 => x"2a", + 3004 => x"73", + 3005 => x"38", + 3006 => x"54", + 3007 => x"fb", + 3008 => x"80", + 3009 => x"34", + 3010 => x"c1", + 3011 => x"06", + 3012 => x"38", + 3013 => x"39", + 3014 => x"70", + 3015 => x"54", + 3016 => x"86", + 3017 => x"84", + 3018 => x"06", + 3019 => x"73", + 3020 => x"38", + 3021 => x"83", + 3022 => x"b4", + 3023 => x"51", + 3024 => x"81", + 3025 => x"88", + 3026 => x"ea", + 3027 => x"de", + 3028 => x"3d", + 3029 => x"3d", + 3030 => x"ff", + 3031 => x"71", + 3032 => x"5c", + 3033 => x"80", + 3034 => x"38", + 3035 => x"05", + 3036 => x"a0", + 3037 => x"71", + 3038 => x"38", + 3039 => x"71", + 3040 => x"81", + 3041 => x"38", + 3042 => x"11", + 3043 => x"06", + 3044 => x"70", + 3045 => x"38", + 3046 => x"81", + 3047 => x"05", + 3048 => x"76", + 3049 => x"38", + 3050 => x"cd", + 3051 => x"77", + 3052 => x"57", + 3053 => x"05", + 3054 => x"70", + 3055 => x"33", + 3056 => x"53", + 3057 => x"99", + 3058 => x"e0", + 3059 => x"ff", + 3060 => x"ff", + 3061 => x"70", + 3062 => x"38", + 3063 => x"81", + 3064 => x"51", + 3065 => x"9f", + 3066 => x"72", + 3067 => x"81", + 3068 => x"70", + 3069 => x"72", + 3070 => x"32", + 3071 => x"72", + 3072 => x"73", + 3073 => x"53", + 3074 => x"70", + 3075 => x"38", + 3076 => x"19", + 3077 => x"75", + 3078 => x"38", + 3079 => x"83", + 3080 => x"74", + 3081 => x"59", + 3082 => x"39", + 3083 => x"33", + 3084 => x"de", + 3085 => x"3d", + 3086 => x"3d", + 3087 => x"80", + 3088 => x"34", + 3089 => x"17", + 3090 => x"75", + 3091 => x"3f", + 3092 => x"de", + 3093 => x"80", + 3094 => x"16", + 3095 => x"3f", + 3096 => x"08", + 3097 => x"06", + 3098 => x"73", + 3099 => x"2e", + 3100 => x"80", + 3101 => x"0b", + 3102 => x"56", + 3103 => x"e9", + 3104 => x"06", + 3105 => x"57", + 3106 => x"32", + 3107 => x"80", + 3108 => x"51", + 3109 => x"8a", + 3110 => x"e8", + 3111 => x"06", + 3112 => x"53", + 3113 => x"52", + 3114 => x"51", + 3115 => x"81", + 3116 => x"55", + 3117 => x"08", + 3118 => x"38", + 3119 => x"cc", + 3120 => x"86", + 3121 => x"97", + 3122 => x"c0", + 3123 => x"de", + 3124 => x"2e", + 3125 => x"55", + 3126 => x"c0", + 3127 => x"0d", + 3128 => x"0d", + 3129 => x"05", + 3130 => x"33", + 3131 => x"75", + 3132 => x"fc", + 3133 => x"de", + 3134 => x"8b", + 3135 => x"81", + 3136 => x"24", + 3137 => x"81", + 3138 => x"84", + 3139 => x"dc", + 3140 => x"55", + 3141 => x"73", + 3142 => x"e6", + 3143 => x"0c", + 3144 => x"06", + 3145 => x"57", + 3146 => x"ae", + 3147 => x"33", + 3148 => x"3f", + 3149 => x"08", + 3150 => x"70", + 3151 => x"55", + 3152 => x"76", + 3153 => x"b8", + 3154 => x"2a", + 3155 => x"51", + 3156 => x"72", + 3157 => x"86", + 3158 => x"74", + 3159 => x"15", + 3160 => x"81", + 3161 => x"d7", + 3162 => x"de", + 3163 => x"ff", + 3164 => x"06", + 3165 => x"56", + 3166 => x"38", + 3167 => x"8f", + 3168 => x"2a", + 3169 => x"51", + 3170 => x"72", + 3171 => x"80", + 3172 => x"52", + 3173 => x"3f", + 3174 => x"08", + 3175 => x"57", + 3176 => x"09", + 3177 => x"e2", + 3178 => x"74", + 3179 => x"56", + 3180 => x"33", + 3181 => x"72", + 3182 => x"38", + 3183 => x"51", + 3184 => x"81", + 3185 => x"57", + 3186 => x"84", + 3187 => x"ff", + 3188 => x"56", + 3189 => x"25", + 3190 => x"0b", + 3191 => x"56", + 3192 => x"05", + 3193 => x"83", + 3194 => x"2e", + 3195 => x"52", + 3196 => x"c6", + 3197 => x"c0", + 3198 => x"06", + 3199 => x"27", + 3200 => x"16", + 3201 => x"27", + 3202 => x"56", + 3203 => x"84", + 3204 => x"56", + 3205 => x"84", + 3206 => x"14", + 3207 => x"3f", + 3208 => x"08", + 3209 => x"06", + 3210 => x"80", + 3211 => x"06", + 3212 => x"80", + 3213 => x"db", + 3214 => x"de", + 3215 => x"ff", + 3216 => x"77", + 3217 => x"d8", + 3218 => x"de", + 3219 => x"c0", + 3220 => x"9c", + 3221 => x"c4", + 3222 => x"15", + 3223 => x"14", + 3224 => x"70", + 3225 => x"51", + 3226 => x"56", + 3227 => x"84", + 3228 => x"81", + 3229 => x"71", + 3230 => x"16", + 3231 => x"53", + 3232 => x"23", + 3233 => x"8b", + 3234 => x"73", + 3235 => x"80", + 3236 => x"8d", + 3237 => x"39", + 3238 => x"51", + 3239 => x"81", + 3240 => x"53", + 3241 => x"08", + 3242 => x"72", + 3243 => x"8d", + 3244 => x"ce", + 3245 => x"14", + 3246 => x"3f", + 3247 => x"08", + 3248 => x"06", + 3249 => x"38", + 3250 => x"51", + 3251 => x"81", + 3252 => x"55", + 3253 => x"51", + 3254 => x"81", + 3255 => x"83", + 3256 => x"53", + 3257 => x"80", + 3258 => x"38", + 3259 => x"78", + 3260 => x"2a", + 3261 => x"78", + 3262 => x"86", + 3263 => x"22", + 3264 => x"31", + 3265 => x"f0", + 3266 => x"c0", + 3267 => x"de", + 3268 => x"2e", + 3269 => x"81", + 3270 => x"80", + 3271 => x"f5", + 3272 => x"83", + 3273 => x"ff", + 3274 => x"38", + 3275 => x"9f", + 3276 => x"38", + 3277 => x"39", + 3278 => x"80", + 3279 => x"38", + 3280 => x"98", + 3281 => x"a0", + 3282 => x"1c", + 3283 => x"0c", + 3284 => x"17", + 3285 => x"76", + 3286 => x"81", + 3287 => x"80", + 3288 => x"d9", + 3289 => x"de", + 3290 => x"ff", + 3291 => x"8d", + 3292 => x"8e", + 3293 => x"8a", + 3294 => x"14", + 3295 => x"3f", + 3296 => x"08", + 3297 => x"74", + 3298 => x"a2", + 3299 => x"79", + 3300 => x"ee", + 3301 => x"a8", + 3302 => x"15", + 3303 => x"2e", + 3304 => x"10", + 3305 => x"2a", + 3306 => x"05", + 3307 => x"ff", + 3308 => x"53", + 3309 => x"9c", + 3310 => x"81", + 3311 => x"0b", + 3312 => x"ff", + 3313 => x"0c", + 3314 => x"84", + 3315 => x"83", + 3316 => x"06", + 3317 => x"80", + 3318 => x"d8", + 3319 => x"de", + 3320 => x"ff", + 3321 => x"72", + 3322 => x"81", + 3323 => x"38", + 3324 => x"73", + 3325 => x"3f", + 3326 => x"08", + 3327 => x"81", + 3328 => x"84", + 3329 => x"b2", + 3330 => x"87", + 3331 => x"c0", + 3332 => x"ff", + 3333 => x"82", + 3334 => x"09", + 3335 => x"c8", + 3336 => x"51", + 3337 => x"81", + 3338 => x"84", + 3339 => x"d2", + 3340 => x"06", + 3341 => x"98", + 3342 => x"ee", + 3343 => x"c0", + 3344 => x"85", + 3345 => x"09", + 3346 => x"38", + 3347 => x"51", + 3348 => x"81", + 3349 => x"90", + 3350 => x"a0", + 3351 => x"ca", + 3352 => x"c0", + 3353 => x"0c", + 3354 => x"81", + 3355 => x"81", + 3356 => x"81", + 3357 => x"72", + 3358 => x"80", + 3359 => x"0c", + 3360 => x"81", + 3361 => x"90", + 3362 => x"fb", + 3363 => x"54", + 3364 => x"80", + 3365 => x"73", + 3366 => x"80", + 3367 => x"72", + 3368 => x"80", + 3369 => x"86", + 3370 => x"15", + 3371 => x"71", + 3372 => x"81", + 3373 => x"81", + 3374 => x"d0", + 3375 => x"de", + 3376 => x"06", + 3377 => x"38", + 3378 => x"54", + 3379 => x"80", + 3380 => x"71", + 3381 => x"81", + 3382 => x"87", + 3383 => x"fa", + 3384 => x"ab", + 3385 => x"58", + 3386 => x"05", + 3387 => x"e6", + 3388 => x"80", + 3389 => x"c0", + 3390 => x"38", + 3391 => x"08", + 3392 => x"de", + 3393 => x"08", + 3394 => x"80", + 3395 => x"80", + 3396 => x"54", + 3397 => x"84", + 3398 => x"34", + 3399 => x"75", + 3400 => x"2e", + 3401 => x"53", + 3402 => x"53", + 3403 => x"f7", + 3404 => x"de", + 3405 => x"73", + 3406 => x"0c", + 3407 => x"04", + 3408 => x"67", + 3409 => x"80", + 3410 => x"59", + 3411 => x"78", + 3412 => x"c8", + 3413 => x"06", + 3414 => x"3d", + 3415 => x"99", + 3416 => x"52", + 3417 => x"3f", + 3418 => x"08", + 3419 => x"c0", + 3420 => x"38", + 3421 => x"52", + 3422 => x"52", + 3423 => x"3f", + 3424 => x"08", + 3425 => x"c0", + 3426 => x"02", + 3427 => x"33", + 3428 => x"55", + 3429 => x"25", + 3430 => x"55", + 3431 => x"54", + 3432 => x"81", + 3433 => x"80", + 3434 => x"74", + 3435 => x"81", + 3436 => x"75", + 3437 => x"3f", + 3438 => x"08", + 3439 => x"02", + 3440 => x"91", + 3441 => x"81", + 3442 => x"82", + 3443 => x"06", + 3444 => x"80", + 3445 => x"88", + 3446 => x"39", + 3447 => x"58", + 3448 => x"38", + 3449 => x"70", + 3450 => x"54", + 3451 => x"81", + 3452 => x"52", + 3453 => x"a5", + 3454 => x"c0", + 3455 => x"88", + 3456 => x"62", + 3457 => x"d4", + 3458 => x"54", + 3459 => x"15", + 3460 => x"62", + 3461 => x"e8", + 3462 => x"52", + 3463 => x"51", + 3464 => x"7a", + 3465 => x"83", + 3466 => x"80", + 3467 => x"38", + 3468 => x"08", + 3469 => x"53", + 3470 => x"3d", + 3471 => x"dd", + 3472 => x"de", + 3473 => x"81", + 3474 => x"82", + 3475 => x"39", + 3476 => x"38", + 3477 => x"33", + 3478 => x"70", + 3479 => x"55", + 3480 => x"2e", + 3481 => x"55", + 3482 => x"77", + 3483 => x"81", + 3484 => x"73", + 3485 => x"38", + 3486 => x"54", + 3487 => x"a0", + 3488 => x"82", + 3489 => x"52", + 3490 => x"a3", + 3491 => x"c0", + 3492 => x"18", + 3493 => x"55", + 3494 => x"c0", + 3495 => x"38", + 3496 => x"70", + 3497 => x"54", + 3498 => x"86", + 3499 => x"c0", + 3500 => x"b0", + 3501 => x"1b", + 3502 => x"1b", + 3503 => x"70", + 3504 => x"d9", + 3505 => x"c0", + 3506 => x"c0", + 3507 => x"0c", + 3508 => x"52", + 3509 => x"3f", + 3510 => x"08", + 3511 => x"08", + 3512 => x"77", + 3513 => x"86", + 3514 => x"1a", + 3515 => x"1a", + 3516 => x"91", + 3517 => x"0b", + 3518 => x"80", + 3519 => x"0c", + 3520 => x"70", + 3521 => x"54", + 3522 => x"81", + 3523 => x"de", + 3524 => x"2e", + 3525 => x"81", + 3526 => x"94", + 3527 => x"17", + 3528 => x"2b", + 3529 => x"57", + 3530 => x"52", + 3531 => x"9f", + 3532 => x"c0", + 3533 => x"de", + 3534 => x"26", + 3535 => x"55", + 3536 => x"08", + 3537 => x"81", + 3538 => x"79", + 3539 => x"31", + 3540 => x"70", + 3541 => x"25", + 3542 => x"76", + 3543 => x"81", + 3544 => x"55", + 3545 => x"38", + 3546 => x"0c", + 3547 => x"75", + 3548 => x"54", + 3549 => x"a2", + 3550 => x"7a", + 3551 => x"3f", + 3552 => x"08", + 3553 => x"55", + 3554 => x"89", + 3555 => x"c0", + 3556 => x"1a", + 3557 => x"80", + 3558 => x"54", + 3559 => x"c0", + 3560 => x"0d", + 3561 => x"0d", + 3562 => x"64", + 3563 => x"59", + 3564 => x"90", + 3565 => x"52", + 3566 => x"cf", + 3567 => x"c0", + 3568 => x"de", + 3569 => x"38", + 3570 => x"55", + 3571 => x"86", + 3572 => x"82", + 3573 => x"19", + 3574 => x"55", + 3575 => x"80", + 3576 => x"38", + 3577 => x"0b", + 3578 => x"82", + 3579 => x"39", + 3580 => x"1a", + 3581 => x"82", + 3582 => x"19", + 3583 => x"08", + 3584 => x"7c", + 3585 => x"74", + 3586 => x"2e", + 3587 => x"94", + 3588 => x"83", + 3589 => x"56", + 3590 => x"38", + 3591 => x"22", + 3592 => x"89", + 3593 => x"55", + 3594 => x"75", + 3595 => x"19", + 3596 => x"39", + 3597 => x"52", + 3598 => x"93", + 3599 => x"c0", + 3600 => x"75", + 3601 => x"38", + 3602 => x"ff", + 3603 => x"98", + 3604 => x"19", + 3605 => x"51", + 3606 => x"81", + 3607 => x"80", + 3608 => x"38", + 3609 => x"08", + 3610 => x"2a", + 3611 => x"80", + 3612 => x"38", + 3613 => x"8a", + 3614 => x"5c", + 3615 => x"27", + 3616 => x"7a", + 3617 => x"54", + 3618 => x"52", + 3619 => x"51", + 3620 => x"81", + 3621 => x"fe", + 3622 => x"83", + 3623 => x"56", + 3624 => x"9f", + 3625 => x"08", + 3626 => x"74", + 3627 => x"38", + 3628 => x"b4", + 3629 => x"16", + 3630 => x"89", + 3631 => x"51", + 3632 => x"77", + 3633 => x"b9", + 3634 => x"1a", + 3635 => x"08", + 3636 => x"84", + 3637 => x"57", + 3638 => x"27", + 3639 => x"56", + 3640 => x"52", + 3641 => x"c7", + 3642 => x"c0", + 3643 => x"38", + 3644 => x"19", + 3645 => x"06", + 3646 => x"52", + 3647 => x"a2", + 3648 => x"31", + 3649 => x"7f", + 3650 => x"94", + 3651 => x"94", + 3652 => x"5c", + 3653 => x"80", + 3654 => x"de", + 3655 => x"3d", + 3656 => x"3d", + 3657 => x"65", + 3658 => x"5d", + 3659 => x"0c", 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x"08", + 3719 => x"2a", + 3720 => x"80", + 3721 => x"38", + 3722 => x"8a", + 3723 => x"5b", + 3724 => x"27", + 3725 => x"7b", + 3726 => x"54", + 3727 => x"52", + 3728 => x"51", + 3729 => x"81", + 3730 => x"fe", + 3731 => x"b0", + 3732 => x"31", + 3733 => x"79", + 3734 => x"84", + 3735 => x"16", + 3736 => x"89", + 3737 => x"52", + 3738 => x"cc", + 3739 => x"55", + 3740 => x"16", + 3741 => x"2b", + 3742 => x"39", + 3743 => x"94", + 3744 => x"93", + 3745 => x"cd", + 3746 => x"de", + 3747 => x"e3", + 3748 => x"b0", + 3749 => x"76", + 3750 => x"94", + 3751 => x"ff", + 3752 => x"71", + 3753 => x"7b", + 3754 => x"38", + 3755 => x"18", + 3756 => x"51", + 3757 => x"81", + 3758 => x"fd", + 3759 => x"53", + 3760 => x"18", + 3761 => x"06", + 3762 => x"51", + 3763 => x"7e", + 3764 => x"83", + 3765 => x"76", + 3766 => x"17", + 3767 => x"1e", + 3768 => x"18", + 3769 => x"0c", + 3770 => x"58", + 3771 => x"74", + 3772 => x"38", + 3773 => x"8c", + 3774 => x"90", + 3775 => x"33", + 3776 => x"55", + 3777 => x"34", + 3778 => x"81", + 3779 => x"90", + 3780 => x"f8", + 3781 => x"8b", + 3782 => x"53", + 3783 => x"f2", + 3784 => x"de", + 3785 => x"81", + 3786 => x"80", + 3787 => x"16", + 3788 => x"2a", + 3789 => x"51", + 3790 => x"80", + 3791 => x"38", + 3792 => x"52", + 3793 => x"e7", + 3794 => x"c0", + 3795 => x"de", + 3796 => x"d4", + 3797 => x"08", + 3798 => x"a0", + 3799 => x"73", + 3800 => x"88", + 3801 => x"74", + 3802 => x"51", + 3803 => x"8c", + 3804 => x"9c", + 3805 => x"fb", + 3806 => x"b2", + 3807 => x"15", + 3808 => x"3f", + 3809 => x"15", + 3810 => x"3f", + 3811 => x"0b", + 3812 => x"78", + 3813 => x"3f", + 3814 => x"08", + 3815 => x"81", + 3816 => x"57", + 3817 => x"34", + 3818 => x"c0", + 3819 => x"0d", + 3820 => x"0d", + 3821 => x"54", + 3822 => x"81", + 3823 => x"53", + 3824 => x"08", + 3825 => x"3d", + 3826 => x"73", + 3827 => x"3f", + 3828 => x"08", + 3829 => x"c0", + 3830 => x"81", + 3831 => x"74", + 3832 => x"de", + 3833 => x"3d", + 3834 => x"3d", + 3835 => x"51", + 3836 => x"8b", + 3837 => x"81", + 3838 => x"24", + 3839 => x"de", + 3840 => x"de", + 3841 => x"52", + 3842 => x"c0", + 3843 => x"0d", + 3844 => x"0d", + 3845 => x"3d", + 3846 => x"94", + 3847 => x"c1", + 3848 => x"c0", + 3849 => x"de", + 3850 => x"e0", + 3851 => x"63", + 3852 => x"d4", + 3853 => x"8d", + 3854 => x"c0", + 3855 => x"de", + 3856 => x"38", + 3857 => x"05", + 3858 => x"2b", + 3859 => x"80", + 3860 => x"76", + 3861 => x"0c", + 3862 => x"02", + 3863 => x"70", + 3864 => x"81", + 3865 => x"56", + 3866 => x"9e", + 3867 => x"53", + 3868 => x"db", + 3869 => x"de", + 3870 => x"15", + 3871 => x"81", + 3872 => x"84", + 3873 => x"06", + 3874 => x"55", + 3875 => x"c0", + 3876 => x"0d", + 3877 => x"0d", + 3878 => x"5b", + 3879 => x"80", + 3880 => x"ff", + 3881 => x"9f", + 3882 => x"b5", + 3883 => x"c0", + 3884 => x"de", + 3885 => x"fc", + 3886 => x"7a", + 3887 => x"08", + 3888 => x"64", + 3889 => x"2e", + 3890 => x"a0", + 3891 => x"70", + 3892 => x"ea", + 3893 => x"c0", + 3894 => x"de", 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x"34", + 3954 => x"de", + 3955 => x"84", + 3956 => x"a4", + 3957 => x"70", + 3958 => x"56", + 3959 => x"76", + 3960 => x"81", + 3961 => x"70", + 3962 => x"56", + 3963 => x"82", + 3964 => x"78", + 3965 => x"80", + 3966 => x"27", + 3967 => x"19", + 3968 => x"7a", + 3969 => x"5c", + 3970 => x"55", + 3971 => x"7a", + 3972 => x"5c", + 3973 => x"2e", + 3974 => x"85", + 3975 => x"94", + 3976 => x"81", + 3977 => x"73", + 3978 => x"81", + 3979 => x"7a", + 3980 => x"38", + 3981 => x"76", + 3982 => x"0c", + 3983 => x"04", + 3984 => x"7b", + 3985 => x"fc", + 3986 => x"53", + 3987 => x"bb", + 3988 => x"c0", + 3989 => x"de", + 3990 => x"fa", + 3991 => x"33", + 3992 => x"f2", + 3993 => x"08", + 3994 => x"27", + 3995 => x"15", + 3996 => x"2a", + 3997 => x"51", + 3998 => x"83", + 3999 => x"94", + 4000 => x"80", + 4001 => x"0c", + 4002 => x"2e", + 4003 => x"79", + 4004 => x"70", + 4005 => x"51", + 4006 => x"2e", + 4007 => x"52", + 4008 => x"ff", + 4009 => x"81", + 4010 => x"ff", + 4011 => x"70", + 4012 => x"ff", + 4013 => x"81", + 4014 => x"73", + 4015 => x"76", + 4016 => x"06", + 4017 => x"0c", + 4018 => x"98", + 4019 => x"58", + 4020 => x"39", + 4021 => x"54", + 4022 => x"73", + 4023 => x"cd", + 4024 => x"de", + 4025 => x"81", + 4026 => x"81", + 4027 => x"38", + 4028 => x"08", + 4029 => x"9b", + 4030 => x"c0", + 4031 => x"0c", + 4032 => x"0c", + 4033 => x"81", + 4034 => x"76", + 4035 => x"38", + 4036 => x"94", + 4037 => x"94", + 4038 => x"16", + 4039 => x"2a", + 4040 => x"51", + 4041 => x"72", + 4042 => x"38", + 4043 => x"51", + 4044 => x"81", + 4045 => x"54", + 4046 => x"08", + 4047 => x"de", + 4048 => x"a7", + 4049 => x"74", + 4050 => x"3f", + 4051 => x"08", + 4052 => x"2e", + 4053 => x"74", + 4054 => x"79", + 4055 => x"14", + 4056 => x"38", + 4057 => x"0c", + 4058 => x"94", + 4059 => x"94", + 4060 => x"83", + 4061 => x"72", + 4062 => x"38", + 4063 => x"51", + 4064 => x"81", + 4065 => x"94", + 4066 => x"91", + 4067 => x"53", + 4068 => x"81", + 4069 => x"34", + 4070 => x"39", + 4071 => x"81", + 4072 => x"05", + 4073 => x"08", + 4074 => x"08", + 4075 => x"38", + 4076 => x"0c", + 4077 => x"80", + 4078 => x"72", + 4079 => x"73", + 4080 => x"53", + 4081 => x"8c", + 4082 => x"16", + 4083 => x"38", + 4084 => x"0c", + 4085 => x"81", + 4086 => x"8b", + 4087 => x"f9", + 4088 => x"56", + 4089 => x"80", + 4090 => x"38", + 4091 => x"3d", + 4092 => x"8a", + 4093 => x"51", + 4094 => x"81", + 4095 => x"55", + 4096 => x"08", + 4097 => x"77", + 4098 => x"52", + 4099 => x"b5", + 4100 => x"c0", + 4101 => x"de", + 4102 => x"c3", + 4103 => x"33", + 4104 => x"55", + 4105 => x"24", + 4106 => x"16", + 4107 => x"2a", + 4108 => x"51", + 4109 => x"80", + 4110 => x"9c", + 4111 => x"77", + 4112 => x"3f", + 4113 => x"08", + 4114 => x"77", + 4115 => x"22", + 4116 => x"74", + 4117 => x"ce", + 4118 => x"de", + 4119 => x"74", + 4120 => x"81", + 4121 => x"85", + 4122 => x"74", + 4123 => x"38", + 4124 => x"74", + 4125 => x"de", + 4126 => x"3d", + 4127 => x"3d", + 4128 => x"3d", + 4129 => x"70", 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x"0c", + 4189 => x"04", + 4190 => x"63", + 4191 => x"80", + 4192 => x"ec", + 4193 => x"3d", + 4194 => x"3f", + 4195 => x"08", + 4196 => x"c0", + 4197 => x"38", + 4198 => x"73", + 4199 => x"08", + 4200 => x"13", + 4201 => x"58", + 4202 => x"26", + 4203 => x"7c", + 4204 => x"39", + 4205 => x"cc", + 4206 => x"81", + 4207 => x"de", + 4208 => x"33", + 4209 => x"81", + 4210 => x"06", + 4211 => x"75", + 4212 => x"52", + 4213 => x"05", + 4214 => x"3f", + 4215 => x"08", + 4216 => x"38", + 4217 => x"08", + 4218 => x"38", + 4219 => x"08", + 4220 => x"de", + 4221 => x"80", + 4222 => x"81", + 4223 => x"59", + 4224 => x"14", + 4225 => x"ca", + 4226 => x"39", + 4227 => x"81", + 4228 => x"57", + 4229 => x"38", + 4230 => x"18", + 4231 => x"ff", + 4232 => x"81", + 4233 => x"5b", + 4234 => x"08", + 4235 => x"7c", + 4236 => x"12", + 4237 => x"52", + 4238 => x"82", + 4239 => x"06", + 4240 => x"14", + 4241 => x"cb", + 4242 => x"c0", + 4243 => x"ff", + 4244 => x"70", + 4245 => x"82", + 4246 => x"51", + 4247 => x"b4", + 4248 => x"bb", + 4249 => x"de", + 4250 => x"0a", + 4251 => x"70", + 4252 => x"84", + 4253 => x"51", + 4254 => x"ff", + 4255 => x"56", + 4256 => x"38", + 4257 => x"7c", + 4258 => x"0c", + 4259 => x"81", + 4260 => x"74", + 4261 => x"7a", + 4262 => x"0c", + 4263 => x"04", + 4264 => x"79", + 4265 => x"05", + 4266 => x"57", + 4267 => x"81", + 4268 => x"56", + 4269 => x"08", + 4270 => x"91", + 4271 => x"75", + 4272 => x"90", + 4273 => x"81", + 4274 => x"06", + 4275 => x"87", + 4276 => x"2e", + 4277 => x"94", + 4278 => x"73", + 4279 => x"27", + 4280 => x"73", + 4281 => x"de", + 4282 => x"88", + 4283 => x"76", + 4284 => x"3f", + 4285 => x"08", + 4286 => x"0c", + 4287 => x"39", + 4288 => x"52", + 4289 => x"bf", + 4290 => x"de", + 4291 => x"2e", + 4292 => x"83", + 4293 => x"81", + 4294 => x"81", + 4295 => x"06", + 4296 => x"56", + 4297 => x"a0", + 4298 => x"81", + 4299 => x"98", + 4300 => x"94", + 4301 => x"08", + 4302 => x"c0", + 4303 => x"51", + 4304 => x"81", + 4305 => x"56", + 4306 => x"8c", + 4307 => x"17", + 4308 => x"07", + 4309 => x"18", + 4310 => x"2e", + 4311 => x"91", + 4312 => x"55", + 4313 => x"c0", + 4314 => x"0d", + 4315 => x"0d", + 4316 => x"3d", + 4317 => x"52", + 4318 => x"da", + 4319 => x"de", + 4320 => x"81", + 4321 => x"81", + 4322 => x"45", + 4323 => x"52", + 4324 => x"52", + 4325 => x"3f", + 4326 => x"08", + 4327 => x"c0", + 4328 => x"38", + 4329 => x"05", + 4330 => x"2a", + 4331 => x"51", + 4332 => x"55", + 4333 => x"38", + 4334 => x"54", + 4335 => x"81", + 4336 => x"80", + 4337 => x"70", + 4338 => x"54", + 4339 => x"81", + 4340 => x"52", + 4341 => x"c5", + 4342 => x"c0", + 4343 => x"2a", + 4344 => x"51", + 4345 => x"80", + 4346 => x"38", + 4347 => x"de", + 4348 => x"15", + 4349 => x"86", + 4350 => x"81", + 4351 => x"5c", + 4352 => x"3d", + 4353 => x"c7", + 4354 => x"de", + 4355 => x"81", + 4356 => x"80", + 4357 => x"de", + 4358 => x"73", + 4359 => x"3f", + 4360 => x"08", + 4361 => x"c0", + 4362 => x"87", + 4363 => x"39", + 4364 => x"08", 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x"51", + 4424 => x"81", + 4425 => x"54", + 4426 => x"08", + 4427 => x"8b", + 4428 => x"b4", + 4429 => x"b7", + 4430 => x"54", + 4431 => x"15", + 4432 => x"90", + 4433 => x"34", + 4434 => x"0a", + 4435 => x"19", + 4436 => x"9f", + 4437 => x"78", + 4438 => x"51", + 4439 => x"a0", + 4440 => x"11", + 4441 => x"05", + 4442 => x"b6", + 4443 => x"ae", + 4444 => x"15", + 4445 => x"78", + 4446 => x"53", + 4447 => x"3f", + 4448 => x"0b", + 4449 => x"77", + 4450 => x"3f", + 4451 => x"08", + 4452 => x"c0", + 4453 => x"82", + 4454 => x"52", + 4455 => x"51", + 4456 => x"3f", + 4457 => x"52", + 4458 => x"aa", + 4459 => x"90", + 4460 => x"34", + 4461 => x"0b", + 4462 => x"78", + 4463 => x"b6", + 4464 => x"c0", + 4465 => x"39", + 4466 => x"52", + 4467 => x"be", + 4468 => x"81", + 4469 => x"99", + 4470 => x"da", + 4471 => x"3d", + 4472 => x"d2", + 4473 => x"53", + 4474 => x"84", + 4475 => x"3d", + 4476 => x"3f", + 4477 => x"08", + 4478 => x"c0", + 4479 => x"38", + 4480 => x"3d", + 4481 => x"3d", + 4482 => x"cc", + 4483 => x"de", + 4484 => x"81", + 4485 => x"82", + 4486 => x"81", + 4487 => x"81", + 4488 => x"86", + 4489 => x"aa", + 4490 => x"a4", + 4491 => x"a8", + 4492 => x"05", + 4493 => x"ea", + 4494 => x"77", + 4495 => x"70", + 4496 => x"b4", + 4497 => x"3d", + 4498 => x"51", + 4499 => x"81", + 4500 => x"55", + 4501 => x"08", + 4502 => x"6f", + 4503 => x"06", + 4504 => x"a2", + 4505 => x"92", + 4506 => x"81", + 4507 => x"de", + 4508 => x"2e", + 4509 => x"81", + 4510 => x"51", + 4511 => x"81", + 4512 => x"55", + 4513 => x"08", + 4514 => x"68", + 4515 => x"a8", + 4516 => x"05", + 4517 => x"51", + 4518 => x"3f", + 4519 => x"33", + 4520 => x"8b", + 4521 => x"84", + 4522 => x"06", + 4523 => x"73", + 4524 => x"a0", + 4525 => x"8b", + 4526 => x"54", + 4527 => x"15", + 4528 => x"33", + 4529 => x"70", + 4530 => x"55", + 4531 => x"2e", + 4532 => x"6e", + 4533 => x"df", + 4534 => x"78", + 4535 => x"3f", + 4536 => x"08", + 4537 => x"ff", + 4538 => x"82", + 4539 => x"c0", + 4540 => x"80", + 4541 => x"de", + 4542 => x"78", + 4543 => x"af", + 4544 => x"c0", + 4545 => x"d4", + 4546 => x"55", + 4547 => x"08", + 4548 => x"81", + 4549 => x"73", + 4550 => x"81", + 4551 => x"63", + 4552 => x"76", + 4553 => x"3f", + 4554 => x"0b", + 4555 => x"87", + 4556 => x"c0", + 4557 => x"77", + 4558 => x"3f", + 4559 => x"08", + 4560 => x"c0", + 4561 => x"78", + 4562 => x"aa", + 4563 => x"c0", + 4564 => x"81", + 4565 => x"a8", + 4566 => x"ed", + 4567 => x"80", + 4568 => x"02", + 4569 => x"df", + 4570 => x"57", + 4571 => x"3d", + 4572 => x"96", + 4573 => x"e9", + 4574 => x"c0", + 4575 => x"de", + 4576 => x"cf", + 4577 => x"65", + 4578 => x"d4", + 4579 => x"b5", + 4580 => x"c0", + 4581 => x"de", + 4582 => x"38", + 4583 => x"05", + 4584 => x"06", + 4585 => x"73", + 4586 => x"a7", + 4587 => x"09", + 4588 => x"71", + 4589 => x"06", + 4590 => x"55", + 4591 => x"15", + 4592 => x"81", + 4593 => x"34", + 4594 => x"b4", + 4595 => x"de", + 4596 => x"74", + 4597 => x"0c", + 4598 => x"04", + 4599 => x"64", + 4600 => x"93", + 4601 => x"52", + 4602 => x"d1", + 4603 => x"de", + 4604 => x"81", + 4605 => x"80", + 4606 => x"58", + 4607 => x"3d", + 4608 => x"c8", + 4609 => x"de", + 4610 => x"81", + 4611 => x"b4", + 4612 => x"c7", + 4613 => x"a0", + 4614 => x"55", + 4615 => x"84", + 4616 => x"17", + 4617 => x"2b", + 4618 => x"96", + 4619 => x"b0", + 4620 => x"54", + 4621 => x"15", + 4622 => x"ff", + 4623 => x"81", + 4624 => x"55", + 4625 => x"c0", + 4626 => x"0d", + 4627 => x"0d", + 4628 => x"5a", + 4629 => x"3d", + 4630 => x"99", + 4631 => x"81", + 4632 => x"c0", + 4633 => x"c0", + 4634 => x"81", + 4635 => x"07", + 4636 => x"55", + 4637 => x"2e", + 4638 => x"81", + 4639 => x"55", + 4640 => x"2e", + 4641 => x"7b", + 4642 => x"80", + 4643 => x"70", + 4644 => x"be", + 4645 => x"de", + 4646 => x"81", + 4647 => x"80", + 4648 => x"52", + 4649 => x"dc", + 4650 => x"c0", + 4651 => x"de", + 4652 => x"38", + 4653 => x"08", + 4654 => x"08", + 4655 => x"56", + 4656 => x"19", + 4657 => x"59", + 4658 => x"74", + 4659 => x"56", + 4660 => x"ec", + 4661 => x"75", + 4662 => x"74", + 4663 => x"2e", + 4664 => x"16", + 4665 => x"33", + 4666 => x"73", + 4667 => x"38", + 4668 => x"84", + 4669 => x"06", + 4670 => x"7a", + 4671 => x"76", + 4672 => x"07", + 4673 => x"54", + 4674 => x"80", + 4675 => x"80", + 4676 => x"7b", + 4677 => x"53", + 4678 => x"93", + 4679 => x"c0", + 4680 => x"de", + 4681 => x"38", + 4682 => x"55", + 4683 => x"56", + 4684 => x"8b", + 4685 => x"56", + 4686 => x"83", + 4687 => x"75", + 4688 => x"51", + 4689 => x"3f", + 4690 => x"08", + 4691 => x"81", + 4692 => x"98", + 4693 => x"e6", + 4694 => x"53", + 4695 => x"b8", + 4696 => x"3d", + 4697 => x"3f", + 4698 => x"08", + 4699 => x"08", + 4700 => x"de", + 4701 => x"98", + 4702 => x"a0", + 4703 => x"70", + 4704 => x"ae", + 4705 => x"6d", + 4706 => x"81", + 4707 => x"57", + 4708 => x"74", + 4709 => x"38", + 4710 => x"81", + 4711 => x"81", + 4712 => x"52", + 4713 => x"89", + 4714 => x"c0", + 4715 => x"a5", + 4716 => x"33", + 4717 => x"54", + 4718 => x"3f", + 4719 => x"08", + 4720 => x"38", + 4721 => x"76", + 4722 => x"05", + 4723 => x"39", + 4724 => x"08", + 4725 => x"15", + 4726 => x"ff", + 4727 => x"73", + 4728 => x"38", + 4729 => x"83", + 4730 => x"56", + 4731 => x"75", + 4732 => x"81", + 4733 => x"33", + 4734 => x"2e", + 4735 => x"52", + 4736 => x"51", + 4737 => x"3f", + 4738 => x"08", + 4739 => x"ff", + 4740 => x"38", + 4741 => x"88", + 4742 => x"8a", + 4743 => x"38", + 4744 => x"ec", + 4745 => x"75", + 4746 => x"74", + 4747 => x"73", + 4748 => x"05", + 4749 => x"17", + 4750 => x"70", + 4751 => x"34", + 4752 => x"70", + 4753 => x"ff", + 4754 => x"55", + 4755 => x"26", + 4756 => x"8b", + 4757 => x"86", + 4758 => x"e5", + 4759 => x"38", + 4760 => x"99", + 4761 => x"05", + 4762 => x"70", + 4763 => x"73", + 4764 => x"81", + 4765 => x"ff", + 4766 => x"ed", + 4767 => x"80", + 4768 => x"91", + 4769 => x"55", + 4770 => x"3f", + 4771 => x"08", + 4772 => x"c0", + 4773 => x"38", + 4774 => x"51", + 4775 => x"3f", + 4776 => x"08", + 4777 => x"c0", + 4778 => x"76", + 4779 => x"67", + 4780 => x"34", + 4781 => x"81", + 4782 => x"84", + 4783 => x"06", + 4784 => x"80", + 4785 => x"2e", + 4786 => x"81", + 4787 => x"ff", + 4788 => x"81", + 4789 => x"54", + 4790 => x"08", + 4791 => x"53", + 4792 => x"08", + 4793 => x"ff", + 4794 => x"67", + 4795 => x"8b", + 4796 => x"53", + 4797 => x"51", + 4798 => x"3f", + 4799 => x"0b", + 4800 => x"79", + 4801 => x"ee", + 4802 => x"c0", + 4803 => x"55", + 4804 => x"c0", + 4805 => x"0d", + 4806 => x"0d", + 4807 => x"88", + 4808 => x"05", + 4809 => x"fc", + 4810 => x"54", + 4811 => x"d2", + 4812 => x"de", + 4813 => x"81", + 4814 => x"82", + 4815 => x"1a", + 4816 => x"82", + 4817 => x"80", + 4818 => x"8c", + 4819 => x"78", + 4820 => x"1a", + 4821 => x"2a", + 4822 => x"51", + 4823 => x"90", + 4824 => x"82", + 4825 => x"58", + 4826 => x"81", + 4827 => x"39", + 4828 => x"22", + 4829 => x"70", + 4830 => x"56", + 4831 => x"fb", + 4832 => x"14", + 4833 => x"30", + 4834 => x"9f", + 4835 => x"c0", + 4836 => x"19", + 4837 => x"5a", + 4838 => x"81", + 4839 => x"38", + 4840 => x"77", + 4841 => x"82", + 4842 => x"56", + 4843 => x"74", + 4844 => x"ff", + 4845 => x"81", + 4846 => x"55", + 4847 => x"75", + 4848 => x"82", + 4849 => x"c0", + 4850 => x"ff", + 4851 => x"de", + 4852 => x"2e", + 4853 => x"81", + 4854 => x"8e", + 4855 => x"56", + 4856 => x"09", + 4857 => x"38", + 4858 => x"59", + 4859 => x"77", + 4860 => x"06", + 4861 => x"87", + 4862 => x"39", + 4863 => x"ba", + 4864 => x"55", + 4865 => x"2e", + 4866 => x"15", + 4867 => x"2e", + 4868 => x"83", + 4869 => x"75", + 4870 => x"7e", + 4871 => x"a8", + 4872 => x"c0", + 4873 => x"de", + 4874 => x"ce", + 4875 => x"16", + 4876 => x"56", + 4877 => x"38", + 4878 => x"19", + 4879 => x"8c", + 4880 => x"7d", + 4881 => x"38", + 4882 => x"0c", + 4883 => x"0c", + 4884 => x"80", + 4885 => x"73", + 4886 => x"98", + 4887 => x"05", + 4888 => x"57", + 4889 => x"26", + 4890 => x"7b", + 4891 => x"0c", + 4892 => x"81", + 4893 => x"84", + 4894 => x"54", + 4895 => x"c0", + 4896 => x"0d", + 4897 => x"0d", + 4898 => x"88", + 4899 => x"05", + 4900 => x"54", + 4901 => x"c5", + 4902 => x"56", + 4903 => x"de", + 4904 => x"8b", + 4905 => x"de", + 4906 => x"29", + 4907 => x"05", + 4908 => x"55", + 4909 => x"84", + 4910 => x"34", + 4911 => x"08", + 4912 => x"5f", + 4913 => x"51", + 4914 => x"3f", + 4915 => x"08", + 4916 => x"70", + 4917 => x"57", + 4918 => x"8b", + 4919 => x"82", + 4920 => x"06", + 4921 => x"56", + 4922 => x"38", + 4923 => x"05", + 4924 => x"7e", + 4925 => x"f0", + 4926 => x"c0", + 4927 => x"67", + 4928 => x"2e", + 4929 => x"82", + 4930 => x"8b", + 4931 => x"75", + 4932 => x"80", + 4933 => x"81", + 4934 => x"2e", + 4935 => x"80", + 4936 => x"38", + 4937 => x"0a", + 4938 => x"ff", + 4939 => x"55", + 4940 => x"86", + 4941 => x"8a", + 4942 => x"89", + 4943 => x"2a", + 4944 => x"77", + 4945 => x"59", + 4946 => x"81", + 4947 => x"70", + 4948 => x"07", + 4949 => x"56", + 4950 => x"38", + 4951 => x"05", + 4952 => x"7e", + 4953 => x"80", + 4954 => x"81", + 4955 => x"8a", + 4956 => x"83", + 4957 => x"06", + 4958 => x"08", + 4959 => x"74", + 4960 => x"41", + 4961 => x"56", + 4962 => x"8a", + 4963 => x"61", + 4964 => x"55", + 4965 => x"27", + 4966 => x"93", + 4967 => x"80", + 4968 => x"38", + 4969 => x"70", + 4970 => x"43", + 4971 => x"95", + 4972 => x"06", + 4973 => x"2e", + 4974 => x"77", + 4975 => x"74", + 4976 => x"83", + 4977 => x"06", + 4978 => x"82", + 4979 => x"2e", + 4980 => x"78", + 4981 => x"2e", + 4982 => x"80", + 4983 => x"ae", + 4984 => x"2a", + 4985 => x"81", + 4986 => x"56", + 4987 => x"2e", + 4988 => x"77", + 4989 => x"81", + 4990 => x"79", + 4991 => x"70", + 4992 => x"5a", + 4993 => x"86", + 4994 => x"27", + 4995 => x"52", + 4996 => x"f6", + 4997 => x"de", + 4998 => x"29", + 4999 => x"70", + 5000 => x"55", + 5001 => x"0b", + 5002 => x"08", + 5003 => x"05", + 5004 => x"ff", + 5005 => x"27", + 5006 => x"88", + 5007 => x"ae", + 5008 => x"2a", + 5009 => x"81", + 5010 => x"56", + 5011 => x"2e", + 5012 => x"77", + 5013 => x"81", + 5014 => x"79", + 5015 => x"70", + 5016 => x"5a", + 5017 => x"86", + 5018 => x"27", + 5019 => x"52", + 5020 => x"f6", + 5021 => x"de", + 5022 => x"84", + 5023 => x"de", + 5024 => x"f5", + 5025 => x"81", + 5026 => x"c0", + 5027 => x"de", + 5028 => x"71", + 5029 => x"83", + 5030 => x"5e", + 5031 => x"89", + 5032 => x"5c", + 5033 => x"1c", + 5034 => x"05", + 5035 => x"ff", + 5036 => x"70", + 5037 => x"31", + 5038 => x"57", + 5039 => x"83", + 5040 => x"06", + 5041 => x"1c", + 5042 => x"5c", + 5043 => x"1d", + 5044 => x"29", + 5045 => x"31", + 5046 => x"55", + 5047 => x"87", + 5048 => x"7c", + 5049 => x"7a", + 5050 => x"31", + 5051 => x"f5", + 5052 => x"de", + 5053 => x"7d", + 5054 => x"81", + 5055 => x"81", + 5056 => x"83", + 5057 => x"80", + 5058 => x"87", + 5059 => x"81", + 5060 => x"fd", + 5061 => x"f8", + 5062 => x"2e", + 5063 => x"80", + 5064 => x"ff", + 5065 => x"de", + 5066 => x"a0", + 5067 => x"38", + 5068 => x"74", + 5069 => x"86", + 5070 => x"fd", + 5071 => x"81", + 5072 => x"80", + 5073 => x"83", + 5074 => x"39", + 5075 => x"08", + 5076 => x"92", + 5077 => x"b8", + 5078 => x"59", + 5079 => x"27", + 5080 => x"86", + 5081 => x"55", + 5082 => x"09", + 5083 => x"38", + 5084 => x"f5", + 5085 => x"38", + 5086 => x"55", + 5087 => x"86", + 5088 => x"80", + 5089 => x"7a", + 5090 => x"b9", + 5091 => x"81", + 5092 => x"7a", + 5093 => x"8a", + 5094 => x"52", + 5095 => x"ff", + 5096 => x"79", + 5097 => x"7b", + 5098 => x"06", + 5099 => x"51", + 5100 => x"3f", + 5101 => x"1c", + 5102 => x"32", + 5103 => x"96", + 5104 => x"06", + 5105 => x"91", + 5106 => x"a1", + 5107 => x"55", + 5108 => x"ff", + 5109 => x"74", + 5110 => x"06", + 5111 => x"51", + 5112 => x"3f", + 5113 => x"52", + 5114 => x"ff", + 5115 => x"f8", + 5116 => x"34", + 5117 => x"1b", + 5118 => x"d9", + 5119 => x"52", + 5120 => x"ff", + 5121 => x"60", + 5122 => x"51", + 5123 => x"3f", + 5124 => x"09", + 5125 => x"cb", + 5126 => x"b2", + 5127 => x"c3", + 5128 => x"a0", + 5129 => x"52", + 5130 => x"ff", + 5131 => x"82", + 5132 => x"51", + 5133 => x"3f", + 5134 => x"1b", + 5135 => x"95", + 5136 => x"b2", + 5137 => x"a0", + 5138 => x"80", + 5139 => x"1c", + 5140 => x"80", + 5141 => x"93", + 5142 => x"fc", + 5143 => x"1b", + 5144 => x"82", + 5145 => x"52", + 5146 => x"ff", + 5147 => x"7c", + 5148 => x"06", + 5149 => x"51", + 5150 => x"3f", + 5151 => x"a4", + 5152 => x"0b", + 5153 => x"93", + 5154 => x"90", + 5155 => x"51", + 5156 => x"3f", + 5157 => x"52", + 5158 => x"70", + 5159 => x"9f", + 5160 => x"54", + 5161 => x"52", + 5162 => x"9b", + 5163 => x"56", + 5164 => x"08", + 5165 => x"7d", + 5166 => x"81", + 5167 => x"38", + 5168 => x"86", + 5169 => x"52", + 5170 => x"9b", + 5171 => x"80", + 5172 => x"7a", + 5173 => x"ed", + 5174 => x"85", + 5175 => x"7a", + 5176 => x"8f", + 5177 => x"85", + 5178 => x"83", + 5179 => x"ff", + 5180 => x"ff", + 5181 => x"e8", + 5182 => x"9e", + 5183 => x"52", + 5184 => x"51", + 5185 => x"3f", + 5186 => x"52", + 5187 => x"9e", + 5188 => x"54", + 5189 => x"53", + 5190 => x"51", + 5191 => x"3f", + 5192 => x"16", + 5193 => x"7e", + 5194 => x"d8", + 5195 => x"80", + 5196 => x"ff", + 5197 => x"7f", + 5198 => x"7d", + 5199 => x"81", + 5200 => x"f8", + 5201 => x"ff", + 5202 => x"ff", + 5203 => x"51", + 5204 => x"3f", + 5205 => x"88", + 5206 => x"39", + 5207 => x"f8", + 5208 => x"2e", + 5209 => x"55", + 5210 => x"51", + 5211 => x"3f", + 5212 => x"57", + 5213 => x"83", + 5214 => x"76", + 5215 => x"7a", + 5216 => x"ff", + 5217 => x"81", + 5218 => x"82", + 5219 => x"80", + 5220 => x"c0", + 5221 => x"51", + 5222 => x"3f", + 5223 => x"78", + 5224 => x"74", + 5225 => x"18", + 5226 => x"2e", + 5227 => x"79", + 5228 => x"2e", + 5229 => x"55", + 5230 => x"62", + 5231 => x"74", + 5232 => x"75", + 5233 => x"7e", + 5234 => x"b8", + 5235 => x"c0", + 5236 => x"38", + 5237 => x"78", + 5238 => x"74", + 5239 => x"56", + 5240 => x"93", + 5241 => x"66", + 5242 => x"26", + 5243 => x"56", + 5244 => x"83", + 5245 => x"64", + 5246 => x"77", + 5247 => x"84", + 5248 => x"52", + 5249 => x"9d", + 5250 => x"d4", + 5251 => x"51", + 5252 => x"3f", + 5253 => x"55", + 5254 => x"81", + 5255 => x"34", + 5256 => x"16", + 5257 => x"16", + 5258 => x"16", + 5259 => x"05", + 5260 => x"c1", + 5261 => x"fe", + 5262 => x"fe", + 5263 => x"34", + 5264 => x"08", + 5265 => x"07", + 5266 => x"16", + 5267 => x"c0", + 5268 => x"34", + 5269 => x"c6", + 5270 => x"9c", + 5271 => x"52", + 5272 => x"51", + 5273 => x"3f", + 5274 => x"53", + 5275 => x"51", + 5276 => x"3f", + 5277 => x"de", + 5278 => x"38", + 5279 => x"52", + 5280 => x"99", + 5281 => x"56", + 5282 => x"08", + 5283 => x"39", + 5284 => x"39", + 5285 => x"39", + 5286 => x"08", + 5287 => x"de", + 5288 => x"3d", + 5289 => x"3d", + 5290 => x"5b", + 5291 => x"60", + 5292 => x"57", + 5293 => x"25", + 5294 => x"3d", + 5295 => x"55", + 5296 => x"15", + 5297 => x"c9", + 5298 => x"81", + 5299 => x"06", + 5300 => x"3d", + 5301 => x"8d", + 5302 => x"74", + 5303 => x"05", + 5304 => x"17", + 5305 => x"2e", + 5306 => x"c9", + 5307 => x"34", + 5308 => x"83", + 5309 => x"74", + 5310 => x"0c", + 5311 => x"04", + 5312 => x"73", + 5313 => x"26", + 5314 => x"71", + 5315 => x"c6", + 5316 => x"71", + 5317 => x"cf", + 5318 => x"80", + 5319 => x"fc", + 5320 => x"39", + 5321 => x"51", + 5322 => x"81", + 5323 => x"80", + 5324 => x"d0", + 5325 => x"e4", + 5326 => x"c4", + 5327 => x"39", + 5328 => x"51", + 5329 => x"81", + 5330 => x"80", + 5331 => x"d1", + 5332 => x"c8", + 5333 => x"98", + 5334 => x"39", + 5335 => x"51", + 5336 => x"d1", + 5337 => x"39", + 5338 => x"51", + 5339 => x"d2", + 5340 => x"39", + 5341 => x"51", + 5342 => x"d2", + 5343 => x"39", + 5344 => x"51", + 5345 => x"d2", + 5346 => x"39", + 5347 => x"51", + 5348 => x"d3", + 5349 => x"39", + 5350 => x"51", + 5351 => x"3f", + 5352 => x"04", + 5353 => x"77", + 5354 => x"74", + 5355 => x"8a", + 5356 => x"75", + 5357 => x"51", + 5358 => x"e8", + 5359 => x"fe", + 5360 => x"81", + 5361 => x"52", + 5362 => x"eb", + 5363 => x"de", + 5364 => x"79", + 5365 => x"81", + 5366 => x"ff", + 5367 => x"87", + 5368 => x"f5", + 5369 => x"7f", + 5370 => x"05", + 5371 => x"33", + 5372 => x"66", + 5373 => x"5a", + 5374 => x"78", + 5375 => x"dc", + 5376 => x"a0", + 5377 => x"e4", + 5378 => x"b4", + 5379 => x"74", + 5380 => x"fc", + 5381 => x"2e", + 5382 => x"a0", + 5383 => x"80", + 5384 => x"16", + 5385 => x"27", + 5386 => x"22", + 5387 => x"e8", + 5388 => x"f0", + 5389 => x"81", + 5390 => x"ff", + 5391 => x"82", + 5392 => x"c3", + 5393 => x"53", + 5394 => x"8e", + 5395 => x"52", + 5396 => x"51", + 5397 => x"3f", + 5398 => x"d3", + 5399 => x"85", + 5400 => x"15", + 5401 => x"74", + 5402 => x"78", + 5403 => x"72", + 5404 => x"d3", + 5405 => x"8b", + 5406 => x"39", + 5407 => x"51", + 5408 => x"3f", + 5409 => x"a0", + 5410 => x"af", + 5411 => x"39", + 5412 => x"51", + 5413 => x"3f", + 5414 => x"77", + 5415 => x"74", + 5416 => x"79", + 5417 => x"55", + 5418 => x"27", + 5419 => x"80", + 5420 => x"73", + 5421 => x"85", + 5422 => x"83", + 5423 => x"fe", + 5424 => x"81", + 5425 => x"39", + 5426 => x"51", + 5427 => x"3f", + 5428 => x"1a", + 5429 => x"f9", + 5430 => x"de", + 5431 => x"2b", + 5432 => x"51", + 5433 => x"2e", + 5434 => x"a5", + 5435 => x"9d", + 5436 => x"c0", + 5437 => x"70", + 5438 => x"a0", + 5439 => x"70", + 5440 => x"2a", + 5441 => x"51", + 5442 => x"2e", + 5443 => x"dd", + 5444 => x"2e", + 5445 => x"85", + 5446 => x"8c", + 5447 => x"53", + 5448 => x"fd", + 5449 => x"53", + 5450 => x"c0", + 5451 => x"0d", + 5452 => x"0d", + 5453 => x"05", + 5454 => x"33", + 5455 => x"70", + 5456 => x"25", + 5457 => x"74", + 5458 => x"51", + 5459 => x"56", + 5460 => x"80", + 5461 => x"53", + 5462 => x"3d", + 5463 => x"ff", + 5464 => x"81", + 5465 => x"56", + 5466 => x"08", + 5467 => x"de", + 5468 => x"c0", + 5469 => x"81", + 5470 => x"59", + 5471 => x"05", + 5472 => x"53", + 5473 => x"51", + 5474 => x"81", + 5475 => x"56", + 5476 => x"08", + 5477 => x"55", + 5478 => x"89", + 5479 => x"75", + 5480 => x"d8", + 5481 => x"d8", + 5482 => x"85", + 5483 => x"70", + 5484 => x"25", + 5485 => x"80", + 5486 => x"74", + 5487 => x"38", + 5488 => x"53", + 5489 => x"88", + 5490 => x"51", + 5491 => x"75", + 5492 => x"de", + 5493 => x"3d", + 5494 => x"3d", + 5495 => x"84", + 5496 => x"33", + 5497 => x"57", + 5498 => x"52", + 5499 => x"c1", + 5500 => x"c0", + 5501 => x"75", + 5502 => x"38", + 5503 => x"98", + 5504 => x"60", + 5505 => x"81", + 5506 => x"7e", + 5507 => x"77", + 5508 => x"c0", + 5509 => x"39", + 5510 => x"81", + 5511 => x"89", + 5512 => x"fc", + 5513 => x"9b", + 5514 => x"d4", + 5515 => x"d4", + 5516 => x"ff", + 5517 => x"81", + 5518 => x"51", + 5519 => x"3f", + 5520 => x"54", + 5521 => x"53", + 5522 => x"33", + 5523 => x"c0", + 5524 => x"d0", + 5525 => x"2e", + 5526 => x"fb", + 5527 => x"3d", + 5528 => x"3d", + 5529 => x"96", + 5530 => x"ff", + 5531 => x"81", + 5532 => x"ad", + 5533 => x"dc", + 5534 => x"a5", + 5535 => x"fe", + 5536 => x"72", + 5537 => x"81", + 5538 => x"71", + 5539 => x"38", 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x"a5", + 5599 => x"80", + 5600 => x"9d", + 5601 => x"fe", + 5602 => x"fe", + 5603 => x"84", + 5604 => x"fa", + 5605 => x"70", + 5606 => x"55", + 5607 => x"2e", + 5608 => x"8e", + 5609 => x"0c", + 5610 => x"53", + 5611 => x"81", + 5612 => x"74", + 5613 => x"ff", + 5614 => x"53", + 5615 => x"83", + 5616 => x"74", + 5617 => x"38", + 5618 => x"75", + 5619 => x"53", + 5620 => x"09", + 5621 => x"38", + 5622 => x"81", + 5623 => x"80", + 5624 => x"29", + 5625 => x"05", + 5626 => x"70", + 5627 => x"fe", + 5628 => x"81", + 5629 => x"8b", + 5630 => x"33", + 5631 => x"2e", + 5632 => x"81", + 5633 => x"ff", + 5634 => x"94", + 5635 => x"38", + 5636 => x"81", + 5637 => x"88", + 5638 => x"fb", + 5639 => x"79", + 5640 => x"56", + 5641 => x"51", + 5642 => x"3f", + 5643 => x"33", + 5644 => x"38", + 5645 => x"d6", + 5646 => x"f5", + 5647 => x"b9", + 5648 => x"de", + 5649 => x"70", + 5650 => x"08", + 5651 => x"82", + 5652 => x"51", + 5653 => x"db", + 5654 => x"db", + 5655 => x"73", + 5656 => x"81", + 5657 => x"81", + 5658 => x"74", + 5659 => x"f4", + 5660 => x"de", + 5661 => x"2e", + 5662 => x"de", + 5663 => x"fe", + 5664 => x"8e", + 5665 => x"c4", + 5666 => x"3f", + 5667 => x"db", + 5668 => x"db", + 5669 => x"73", + 5670 => x"81", + 5671 => x"74", + 5672 => x"ff", + 5673 => x"80", + 5674 => x"c0", + 5675 => x"0d", + 5676 => x"0d", + 5677 => x"81", + 5678 => x"40", + 5679 => x"7c", + 5680 => x"d7", + 5681 => x"c0", + 5682 => x"06", + 5683 => x"2e", + 5684 => x"a2", + 5685 => x"d0", + 5686 => x"70", + 5687 => x"82", + 5688 => x"53", + 5689 => x"df", + 5690 => x"b7", + 5691 => x"de", + 5692 => x"2e", + 5693 => x"d6", + 5694 => x"bc", + 5695 => x"40", + 5696 => x"8c", + 5697 => x"b8", + 5698 => x"70", + 5699 => x"f8", + 5700 => x"fe", + 5701 => x"3d", + 5702 => x"51", + 5703 => x"81", + 5704 => x"90", + 5705 => x"2c", + 5706 => x"80", + 5707 => x"ce", + 5708 => x"c3", + 5709 => x"38", + 5710 => x"83", + 5711 => x"ab", + 5712 => x"78", + 5713 => x"af", + 5714 => x"24", + 5715 => x"80", + 5716 => x"38", + 5717 => x"78", + 5718 => x"82", + 5719 => x"2e", + 5720 => x"8f", + 5721 => x"80", + 5722 => x"87", + 5723 => x"c0", + 5724 => x"78", + 5725 => x"a9", + 5726 => x"2e", + 5727 => x"8f", + 5728 => x"80", + 5729 => x"9e", + 5730 => x"c2", + 5731 => x"38", + 5732 => x"78", + 5733 => x"8d", + 5734 => x"80", + 5735 => x"38", + 5736 => x"2e", + 5737 => x"78", + 5738 => x"8b", + 5739 => x"c5", + 5740 => x"38", + 5741 => x"78", + 5742 => x"8d", + 5743 => x"80", + 5744 => x"ab", + 5745 => x"39", + 5746 => x"2e", + 5747 => x"78", + 5748 => x"92", + 5749 => x"f8", + 5750 => x"38", + 5751 => x"2e", + 5752 => x"8e", + 5753 => x"81", + 5754 => x"b4", + 5755 => x"85", + 5756 => x"38", + 5757 => x"b7", + 5758 => x"11", + 5759 => x"05", + 5760 => x"95", + 5761 => x"c0", + 5762 => x"81", + 5763 => x"90", + 5764 => x"3d", + 5765 => x"53", + 5766 => x"51", + 5767 => x"3f", + 5768 => x"08", + 5769 => x"38", + 5770 => x"83", + 5771 => x"02", + 5772 => x"33", + 5773 => x"cf", + 5774 => x"ff", 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x"fe", + 5834 => x"81", + 5835 => x"b8", + 5836 => x"05", + 5837 => x"e5", + 5838 => x"de", + 5839 => x"3d", + 5840 => x"52", + 5841 => x"ec", + 5842 => x"c0", + 5843 => x"fe", + 5844 => x"59", + 5845 => x"3f", + 5846 => x"58", + 5847 => x"57", + 5848 => x"55", + 5849 => x"08", + 5850 => x"54", + 5851 => x"52", + 5852 => x"e6", + 5853 => x"c0", + 5854 => x"fb", + 5855 => x"de", + 5856 => x"ee", + 5857 => x"f9", + 5858 => x"fe", + 5859 => x"fe", + 5860 => x"fe", + 5861 => x"81", + 5862 => x"80", + 5863 => x"38", + 5864 => x"f0", + 5865 => x"f8", + 5866 => x"fe", + 5867 => x"de", + 5868 => x"2e", + 5869 => x"b7", + 5870 => x"11", + 5871 => x"05", + 5872 => x"d5", + 5873 => x"c0", + 5874 => x"81", + 5875 => x"42", + 5876 => x"51", + 5877 => x"3f", + 5878 => x"5a", + 5879 => x"88", + 5880 => x"59", + 5881 => x"84", + 5882 => x"7a", + 5883 => x"38", + 5884 => x"b7", + 5885 => x"11", + 5886 => x"05", + 5887 => x"99", + 5888 => x"c0", + 5889 => x"38", + 5890 => x"33", + 5891 => x"2e", + 5892 => x"db", + 5893 => x"80", + 5894 => x"db", + 5895 => x"78", + 5896 => x"38", + 5897 => x"08", + 5898 => x"81", + 5899 => x"59", + 5900 => x"88", + 5901 => x"9c", + 5902 => x"39", + 5903 => x"33", + 5904 => x"2e", + 5905 => x"db", + 5906 => x"9a", + 5907 => x"d2", + 5908 => x"80", + 5909 => x"81", + 5910 => x"44", + 5911 => x"db", + 5912 => x"80", + 5913 => x"3d", + 5914 => x"53", + 5915 => x"51", + 5916 => x"3f", + 5917 => x"08", + 5918 => x"81", + 5919 => x"59", + 5920 => x"89", + 5921 => x"90", + 5922 => x"cc", + 5923 => x"d5", + 5924 => x"80", + 5925 => x"81", + 5926 => x"43", + 5927 => x"db", + 5928 => x"78", + 5929 => x"38", + 5930 => x"08", + 5931 => x"81", + 5932 => x"59", + 5933 => x"88", + 5934 => x"a8", + 5935 => x"39", + 5936 => x"33", + 5937 => x"2e", + 5938 => x"db", + 5939 => x"88", + 5940 => x"bc", + 5941 => x"43", + 5942 => x"ec", + 5943 => x"f8", + 5944 => x"fc", + 5945 => x"de", + 5946 => x"2e", + 5947 => x"62", + 5948 => x"88", + 5949 => x"81", + 5950 => x"2e", + 5951 => x"80", + 5952 => x"79", + 5953 => x"38", + 5954 => x"d7", + 5955 => x"f4", + 5956 => x"55", + 5957 => x"53", + 5958 => x"51", + 5959 => x"81", + 5960 => x"86", + 5961 => x"3d", + 5962 => x"53", + 5963 => x"51", + 5964 => x"3f", + 5965 => x"08", + 5966 => x"c5", + 5967 => x"fe", + 5968 => x"fe", + 5969 => x"fe", + 5970 => x"81", + 5971 => x"80", + 5972 => x"63", + 5973 => x"cb", + 5974 => x"34", + 5975 => x"44", + 5976 => x"f0", + 5977 => x"f8", + 5978 => x"fb", + 5979 => x"de", + 5980 => x"38", + 5981 => x"63", + 5982 => x"52", + 5983 => x"51", + 5984 => x"3f", + 5985 => x"79", + 5986 => x"f2", + 5987 => x"79", + 5988 => x"ae", + 5989 => x"38", + 5990 => x"a0", + 5991 => x"fe", + 5992 => x"fe", + 5993 => x"fe", + 5994 => x"81", + 5995 => x"80", + 5996 => x"63", + 5997 => x"cb", + 5998 => x"34", + 5999 => x"44", + 6000 => x"81", + 6001 => x"fe", + 6002 => x"ff", + 6003 => x"3d", + 6004 => x"53", + 6005 => x"51", + 6006 => x"3f", + 6007 => x"08", + 6008 => x"9d", + 6009 => x"fe", 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x"51", + 6069 => x"3f", + 6070 => x"79", + 6071 => x"9e", + 6072 => x"79", + 6073 => x"ae", + 6074 => x"38", + 6075 => x"9c", + 6076 => x"fe", + 6077 => x"fe", + 6078 => x"fe", + 6079 => x"81", + 6080 => x"80", + 6081 => x"60", + 6082 => x"59", + 6083 => x"41", + 6084 => x"81", + 6085 => x"fe", + 6086 => x"ff", + 6087 => x"3d", + 6088 => x"53", + 6089 => x"51", + 6090 => x"3f", + 6091 => x"08", + 6092 => x"81", + 6093 => x"59", + 6094 => x"89", + 6095 => x"8c", + 6096 => x"cd", + 6097 => x"d5", + 6098 => x"80", + 6099 => x"81", + 6100 => x"44", + 6101 => x"db", + 6102 => x"78", + 6103 => x"38", + 6104 => x"08", + 6105 => x"81", + 6106 => x"59", + 6107 => x"88", + 6108 => x"a4", + 6109 => x"39", + 6110 => x"33", + 6111 => x"2e", + 6112 => x"db", + 6113 => x"89", + 6114 => x"bc", + 6115 => x"05", + 6116 => x"fe", + 6117 => x"fe", + 6118 => x"fe", + 6119 => x"81", + 6120 => x"80", + 6121 => x"db", + 6122 => x"78", + 6123 => x"38", + 6124 => x"08", + 6125 => x"39", + 6126 => x"33", + 6127 => x"2e", + 6128 => x"db", + 6129 => x"bb", + 6130 => x"d6", + 6131 => x"80", + 6132 => x"81", + 6133 => x"43", + 6134 => x"db", + 6135 => x"78", + 6136 => x"38", + 6137 => x"08", + 6138 => x"81", + 6139 => x"59", + 6140 => x"88", + 6141 => x"b0", + 6142 => x"39", + 6143 => x"08", + 6144 => x"b7", + 6145 => x"11", + 6146 => x"05", + 6147 => x"89", + 6148 => x"c0", + 6149 => x"81", + 6150 => x"42", + 6151 => x"51", + 6152 => x"3f", + 6153 => x"63", + 6154 => x"79", + 6155 => x"62", + 6156 => x"06", + 6157 => x"53", + 6158 => x"d8", + 6159 => x"f3", + 6160 => x"1a", + 6161 => x"81", + 6162 => x"b9", + 6163 => x"cc", + 6164 => x"ec", + 6165 => x"fe", + 6166 => x"f1", + 6167 => x"d8", + 6168 => x"ed", + 6169 => x"51", + 6170 => x"3f", + 6171 => x"84", + 6172 => x"87", + 6173 => x"0c", + 6174 => x"0b", + 6175 => x"94", + 6176 => x"fc", + 6177 => x"b8", + 6178 => x"39", + 6179 => x"51", + 6180 => x"3f", + 6181 => x"0b", + 6182 => x"84", + 6183 => x"83", + 6184 => x"94", + 6185 => x"d9", + 6186 => x"fe", + 6187 => x"fe", + 6188 => x"fe", + 6189 => x"81", + 6190 => x"80", + 6191 => x"38", + 6192 => x"d9", + 6193 => x"f2", + 6194 => x"59", + 6195 => x"3d", + 6196 => x"53", + 6197 => x"51", + 6198 => x"3f", + 6199 => x"08", + 6200 => x"9d", + 6201 => x"81", + 6202 => x"fe", + 6203 => x"63", + 6204 => x"81", + 6205 => x"5e", + 6206 => x"08", + 6207 => x"81", + 6208 => x"c0", + 6209 => x"d9", + 6210 => x"f2", + 6211 => x"f1", + 6212 => x"f8", + 6213 => x"a8", + 6214 => x"e5", + 6215 => x"39", + 6216 => x"51", + 6217 => x"3f", + 6218 => x"a0", + 6219 => x"81", + 6220 => x"39", + 6221 => x"51", + 6222 => x"2e", + 6223 => x"7c", + 6224 => x"dc", + 6225 => x"60", + 6226 => x"78", + 6227 => x"d0", + 6228 => x"fe", + 6229 => x"fe", + 6230 => x"81", + 6231 => x"7a", + 6232 => x"82", + 6233 => x"7b", + 6234 => x"38", + 6235 => x"8c", + 6236 => x"39", + 6237 => x"b0", + 6238 => x"39", + 6239 => x"56", + 6240 => x"da", + 6241 => x"53", + 6242 => x"52", + 6243 => x"b0", + 6244 => x"f1", + 6245 => x"39", + 6246 => x"52", + 6247 => x"b0", + 6248 => x"f1", + 6249 => x"39", + 6250 => x"da", + 6251 => x"53", + 6252 => x"52", + 6253 => x"b0", + 6254 => x"f0", + 6255 => x"39", + 6256 => x"53", + 6257 => x"52", + 6258 => x"b0", + 6259 => x"f0", + 6260 => x"db", + 6261 => x"de", + 6262 => x"56", + 6263 => x"46", + 6264 => x"80", + 6265 => x"80", + 6266 => x"80", + 6267 => x"ff", + 6268 => x"e7", + 6269 => x"de", + 6270 => x"de", + 6271 => x"70", + 6272 => x"07", + 6273 => x"5b", + 6274 => x"83", + 6275 => x"78", + 6276 => x"38", + 6277 => x"81", + 6278 => x"59", + 6279 => x"38", + 6280 => x"7d", + 6281 => x"59", + 6282 => x"7d", + 6283 => x"81", + 6284 => x"38", + 6285 => x"51", + 6286 => x"3f", + 6287 => x"fc", + 6288 => x"0b", + 6289 => x"34", + 6290 => x"8c", + 6291 => x"55", + 6292 => x"52", + 6293 => x"ce", + 6294 => x"de", + 6295 => x"2b", + 6296 => x"53", + 6297 => x"52", + 6298 => x"ce", + 6299 => x"81", + 6300 => x"07", + 6301 => x"c0", + 6302 => x"08", + 6303 => x"84", + 6304 => x"51", + 6305 => x"3f", + 6306 => x"08", + 6307 => x"08", + 6308 => x"84", + 6309 => x"51", + 6310 => x"3f", + 6311 => x"c0", + 6312 => x"0c", + 6313 => x"0b", + 6314 => x"84", + 6315 => x"83", + 6316 => x"94", + 6317 => x"ba", + 6318 => x"d0", + 6319 => x"0b", + 6320 => x"0c", + 6321 => x"3f", + 6322 => x"3f", + 6323 => x"51", + 6324 => x"3f", + 6325 => x"51", + 6326 => x"3f", + 6327 => x"51", + 6328 => x"3f", + 6329 => x"bb", + 6330 => x"3f", + 6331 => x"00", + 6332 => x"ff", + 6333 => x"ff", + 6334 => x"00", + 6335 => x"ff", + 6336 => x"16", + 6337 => x"16", + 6338 => x"16", + 6339 => x"16", + 6340 => x"16", + 6341 => x"53", + 6342 => x"53", + 6343 => x"53", + 6344 => x"53", + 6345 => x"53", + 6346 => x"53", + 6347 => x"53", + 6348 => x"53", + 6349 => x"53", + 6350 => x"53", + 6351 => x"53", + 6352 => x"53", + 6353 => x"53", + 6354 => x"53", + 6355 => x"53", + 6356 => x"53", + 6357 => x"53", + 6358 => x"53", + 6359 => x"53", + 6360 => x"53", + 6361 => x"2f", + 6362 => x"25", + 6363 => x"64", + 6364 => x"3a", + 6365 => x"25", + 6366 => x"0a", + 6367 => x"43", + 6368 => x"6e", + 6369 => x"75", + 6370 => x"69", + 6371 => x"00", + 6372 => x"66", + 6373 => x"20", + 6374 => x"20", + 6375 => x"66", + 6376 => x"00", + 6377 => x"44", + 6378 => x"63", + 6379 => x"69", + 6380 => x"65", + 6381 => x"74", + 6382 => x"0a", + 6383 => x"20", + 6384 => x"20", + 6385 => x"41", + 6386 => x"28", + 6387 => x"58", + 6388 => x"38", + 6389 => x"0a", + 6390 => x"20", + 6391 => x"52", + 6392 => x"20", + 6393 => x"28", + 6394 => x"58", + 6395 => x"38", + 6396 => x"0a", + 6397 => x"20", + 6398 => x"53", + 6399 => x"52", + 6400 => x"28", + 6401 => x"58", + 6402 => x"38", + 6403 => x"0a", + 6404 => x"20", + 6405 => x"41", + 6406 => x"20", + 6407 => x"28", + 6408 => x"58", + 6409 => x"38", + 6410 => x"0a", + 6411 => x"20", + 6412 => x"4d", + 6413 => x"20", + 6414 => x"28", + 6415 => x"58", + 6416 => x"38", + 6417 => x"0a", + 6418 => x"20", + 6419 => x"20", + 6420 => x"44", + 6421 => x"28", + 6422 => x"69", + 6423 => x"20", + 6424 => x"32", + 6425 => x"0a", + 6426 => x"20", + 6427 => x"4d", + 6428 => x"20", + 6429 => x"28", + 6430 => x"65", + 6431 => x"20", + 6432 => x"32", + 6433 => x"0a", + 6434 => x"20", + 6435 => x"54", + 6436 => x"54", + 6437 => x"28", + 6438 => x"6e", + 6439 => x"73", + 6440 => x"32", + 6441 => x"0a", + 6442 => x"20", + 6443 => x"53", + 6444 => x"4e", + 6445 => x"55", + 6446 => x"00", + 6447 => x"20", + 6448 => x"20", + 6449 => x"0a", + 6450 => x"20", + 6451 => x"43", + 6452 => x"00", + 6453 => x"20", + 6454 => x"32", + 6455 => x"00", + 6456 => x"20", + 6457 => x"49", + 6458 => x"00", + 6459 => x"64", + 6460 => x"73", + 6461 => x"0a", + 6462 => x"20", + 6463 => x"55", + 6464 => x"73", + 6465 => x"56", + 6466 => x"6f", + 6467 => x"64", + 6468 => x"73", + 6469 => x"20", + 6470 => x"58", + 6471 => x"00", + 6472 => x"20", + 6473 => x"55", + 6474 => x"6d", + 6475 => x"20", + 6476 => x"72", + 6477 => x"64", + 6478 => x"73", + 6479 => x"20", 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x"00", + 6539 => x"64", + 6540 => x"00", + 6541 => x"65", + 6542 => x"00", + 6543 => x"4f", + 6544 => x"4f", + 6545 => x"00", + 6546 => x"6b", + 6547 => x"6e", + 6548 => x"00", + 6549 => x"2b", + 6550 => x"3c", + 6551 => x"5b", + 6552 => x"00", + 6553 => x"54", + 6554 => x"54", + 6555 => x"00", + 6556 => x"90", + 6557 => x"4f", + 6558 => x"30", + 6559 => x"20", + 6560 => x"45", + 6561 => x"20", + 6562 => x"33", + 6563 => x"20", + 6564 => x"20", + 6565 => x"45", + 6566 => x"20", + 6567 => x"20", + 6568 => x"20", + 6569 => x"66", + 6570 => x"00", + 6571 => x"00", + 6572 => x"00", + 6573 => x"45", + 6574 => x"8f", + 6575 => x"45", + 6576 => x"8e", + 6577 => x"92", + 6578 => x"55", + 6579 => x"9a", + 6580 => x"9e", + 6581 => x"4f", + 6582 => x"a6", + 6583 => x"aa", + 6584 => x"ae", + 6585 => x"b2", + 6586 => x"b6", + 6587 => x"ba", + 6588 => x"be", + 6589 => x"c2", + 6590 => x"c6", + 6591 => x"ca", + 6592 => x"ce", + 6593 => x"d2", + 6594 => x"d6", + 6595 => x"da", + 6596 => x"de", + 6597 => x"e2", + 6598 => x"e6", + 6599 => x"ea", + 6600 => x"ee", + 6601 => x"f2", + 6602 => x"f6", + 6603 => x"fa", + 6604 => x"fe", + 6605 => x"2c", + 6606 => x"5d", + 6607 => x"2a", + 6608 => x"3f", + 6609 => x"00", + 6610 => x"00", + 6611 => x"00", + 6612 => x"02", + 6613 => x"00", + 6614 => x"00", + 6615 => x"00", + 6616 => x"00", + 6617 => x"00", + 6618 => x"6e", + 6619 => x"00", + 6620 => x"6f", + 6621 => x"00", + 6622 => x"6e", + 6623 => x"00", + 6624 => x"6f", + 6625 => x"00", + 6626 => x"78", + 6627 => x"00", + 6628 => x"6c", + 6629 => x"00", + 6630 => x"75", + 6631 => x"00", + 6632 => x"72", + 6633 => x"00", + 6634 => x"62", + 6635 => x"68", + 6636 => x"77", + 6637 => x"64", + 6638 => x"65", + 6639 => x"64", + 6640 => x"65", + 6641 => x"6c", + 6642 => x"00", + 6643 => x"70", + 6644 => x"73", + 6645 => x"74", + 6646 => x"73", + 6647 => x"00", + 6648 => x"66", + 6649 => x"00", + 6650 => x"73", + 6651 => x"00", + 6652 => x"73", + 6653 => x"72", + 6654 => x"0a", + 6655 => x"74", + 6656 => x"61", + 6657 => x"72", + 6658 => x"2e", + 6659 => x"00", + 6660 => x"73", + 6661 => x"6f", + 6662 => x"65", + 6663 => x"2e", + 6664 => x"00", + 6665 => x"20", + 6666 => x"65", + 6667 => x"75", + 6668 => x"0a", + 6669 => x"20", + 6670 => x"68", + 6671 => x"75", + 6672 => x"0a", + 6673 => x"76", + 6674 => x"64", + 6675 => x"6c", + 6676 => x"6d", + 6677 => x"00", + 6678 => x"63", + 6679 => x"20", + 6680 => x"69", + 6681 => x"0a", + 6682 => x"6c", + 6683 => x"6c", + 6684 => x"64", + 6685 => x"78", + 6686 => x"73", + 6687 => x"00", + 6688 => x"6c", + 6689 => x"61", + 6690 => x"65", + 6691 => x"76", + 6692 => x"64", + 6693 => x"00", + 6694 => x"20", + 6695 => x"77", + 6696 => x"65", + 6697 => x"6f", + 6698 => x"74", + 6699 => x"0a", + 6700 => x"69", + 6701 => x"6e", + 6702 => x"65", + 6703 => x"73", + 6704 => x"76", + 6705 => x"64", + 6706 => x"00", + 6707 => x"73", + 6708 => x"6f", + 6709 => x"6e", + 6710 => x"65", + 6711 => x"00", + 6712 => x"20", + 6713 => x"70", + 6714 => x"62", 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x"2e", + 6774 => x"00", + 6775 => x"38", + 6776 => x"00", + 6777 => x"20", + 6778 => x"34", + 6779 => x"00", + 6780 => x"20", + 6781 => x"20", + 6782 => x"00", + 6783 => x"32", + 6784 => x"00", + 6785 => x"00", + 6786 => x"00", + 6787 => x"0a", + 6788 => x"61", + 6789 => x"00", + 6790 => x"55", + 6791 => x"00", + 6792 => x"2a", + 6793 => x"20", + 6794 => x"00", + 6795 => x"2f", + 6796 => x"32", + 6797 => x"00", + 6798 => x"2e", + 6799 => x"00", + 6800 => x"50", + 6801 => x"72", + 6802 => x"25", + 6803 => x"29", + 6804 => x"20", + 6805 => x"2a", + 6806 => x"00", + 6807 => x"55", + 6808 => x"49", + 6809 => x"72", + 6810 => x"74", + 6811 => x"6e", + 6812 => x"72", + 6813 => x"00", + 6814 => x"6d", + 6815 => x"69", + 6816 => x"72", + 6817 => x"74", + 6818 => x"00", + 6819 => x"32", + 6820 => x"74", + 6821 => x"75", + 6822 => x"00", + 6823 => x"43", + 6824 => x"52", + 6825 => x"6e", + 6826 => x"72", + 6827 => x"0a", + 6828 => x"43", + 6829 => x"57", + 6830 => x"6e", + 6831 => x"72", + 6832 => x"0a", + 6833 => x"52", + 6834 => x"52", + 6835 => x"6e", + 6836 => x"72", + 6837 => x"0a", + 6838 => x"52", + 6839 => x"54", + 6840 => x"6e", + 6841 => x"72", + 6842 => x"0a", + 6843 => x"52", + 6844 => x"52", + 6845 => x"6e", + 6846 => x"72", + 6847 => x"0a", + 6848 => x"52", + 6849 => x"54", + 6850 => x"6e", + 6851 => x"72", + 6852 => x"0a", + 6853 => x"74", + 6854 => x"67", + 6855 => x"20", + 6856 => x"65", + 6857 => x"2e", + 6858 => x"00", + 6859 => x"61", + 6860 => x"6e", + 6861 => x"69", + 6862 => x"2e", + 6863 => x"00", + 6864 => x"74", + 6865 => x"65", + 6866 => x"61", + 6867 => x"00", + 6868 => x"00", + 6869 => x"69", + 6870 => x"20", + 6871 => x"69", + 6872 => x"69", + 6873 => x"73", + 6874 => x"64", + 6875 => x"72", + 6876 => x"2c", + 6877 => x"65", + 6878 => x"20", + 6879 => x"74", + 6880 => x"6e", + 6881 => x"6c", + 6882 => x"00", + 6883 => x"00", + 6884 => x"64", + 6885 => x"73", + 6886 => x"64", + 6887 => x"00", + 6888 => x"69", + 6889 => x"6c", + 6890 => x"64", + 6891 => x"00", + 6892 => x"69", + 6893 => x"20", + 6894 => x"69", + 6895 => x"69", + 6896 => x"73", + 6897 => x"00", + 6898 => x"3d", + 6899 => x"00", + 6900 => x"3a", + 6901 => x"65", + 6902 => x"6e", + 6903 => x"2e", + 6904 => x"00", + 6905 => x"6d", + 6906 => x"65", + 6907 => x"79", + 6908 => x"00", + 6909 => x"6f", + 6910 => x"65", + 6911 => x"0a", + 6912 => x"38", + 6913 => x"30", + 6914 => x"00", + 6915 => x"3f", + 6916 => x"00", + 6917 => x"38", + 6918 => x"30", + 6919 => x"00", + 6920 => x"38", + 6921 => x"30", + 6922 => x"00", + 6923 => x"61", + 6924 => x"69", + 6925 => x"2e", + 6926 => x"00", + 6927 => x"38", + 6928 => x"3e", + 6929 => x"6c", + 6930 => x"00", + 6931 => x"73", + 6932 => x"69", + 6933 => x"69", + 6934 => x"72", + 6935 => x"74", + 6936 => x"00", + 6937 => x"61", + 6938 => x"6e", + 6939 => x"6e", + 6940 => x"72", + 6941 => x"73", + 6942 => x"00", + 6943 => x"73", + 6944 => x"65", + 6945 => x"61", + 6946 => x"66", + 6947 => x"0a", + 6948 => x"61", + 6949 => x"6e", + 6950 => x"61", + 6951 => x"66", + 6952 => x"0a", + 6953 => x"65", + 6954 => x"69", + 6955 => x"63", + 6956 => x"20", + 6957 => x"30", + 6958 => x"2e", + 6959 => x"00", + 6960 => x"6c", + 6961 => x"67", + 6962 => x"64", + 6963 => x"20", + 6964 => x"78", + 6965 => x"2e", + 6966 => x"00", + 6967 => x"6c", + 6968 => x"65", + 6969 => x"6e", + 6970 => x"63", + 6971 => x"20", + 6972 => x"29", + 6973 => x"00", + 6974 => x"73", + 6975 => x"74", + 6976 => x"20", + 6977 => x"6c", + 6978 => x"74", + 6979 => x"2e", + 6980 => x"00", + 6981 => x"6c", + 6982 => x"65", + 6983 => x"74", + 6984 => x"2e", + 6985 => x"00", + 6986 => x"55", + 6987 => x"6e", + 6988 => x"3a", + 6989 => x"5c", + 6990 => x"25", + 6991 => x"00", + 6992 => x"3a", + 6993 => x"5c", + 6994 => x"00", + 6995 => x"3a", + 6996 => x"00", + 6997 => x"64", + 6998 => x"6d", + 6999 => x"64", + 7000 => x"00", + 7001 => x"6e", + 7002 => x"67", + 7003 => x"0a", + 7004 => x"61", + 7005 => x"6e", + 7006 => x"6e", + 7007 => x"72", + 7008 => x"73", + 7009 => x"0a", + 7010 => x"00", + 7011 => x"00", + 7012 => x"7f", + 7013 => x"00", + 7014 => x"7f", + 7015 => x"00", + 7016 => x"7f", + 7017 => x"00", + 7018 => x"00", + 7019 => x"00", + 7020 => x"ff", + 7021 => x"00", + 7022 => x"00", + 7023 => x"78", + 7024 => x"00", + 7025 => x"e1", + 7026 => x"e1", + 7027 => x"e1", + 7028 => x"00", + 7029 => x"01", + 7030 => x"01", + 7031 => x"10", + 7032 => x"00", + 7033 => x"00", + 7034 => x"00", + 7035 => x"00", + 7036 => x"67", + 7037 => x"01", + 7038 => x"00", + 7039 => x"00", + 7040 => x"67", + 7041 => x"01", + 7042 => x"00", + 7043 => x"00", + 7044 => x"67", + 7045 => x"03", + 7046 => x"00", + 7047 => x"00", + 7048 => x"67", + 7049 => x"03", + 7050 => x"00", + 7051 => x"00", + 7052 => x"67", + 7053 => x"03", + 7054 => x"00", + 7055 => x"00", + 7056 => x"67", + 7057 => x"04", + 7058 => x"00", + 7059 => x"00", + 7060 => x"67", + 7061 => x"04", + 7062 => x"00", + 7063 => x"00", + 7064 => x"67", + 7065 => x"04", + 7066 => x"00", + 7067 => x"00", + 7068 => x"67", + 7069 => x"04", + 7070 => x"00", + 7071 => x"00", + 7072 => x"67", + 7073 => x"04", + 7074 => x"00", + 7075 => x"00", + 7076 => x"67", + 7077 => x"04", + 7078 => x"00", + 7079 => x"00", + 7080 => x"67", + 7081 => x"05", + 7082 => x"00", + 7083 => x"00", + 7084 => x"67", + 7085 => x"05", + 7086 => x"00", + 7087 => x"00", + 7088 => x"67", + 7089 => x"05", + 7090 => x"00", + 7091 => x"00", + 7092 => x"67", + 7093 => x"05", + 7094 => x"00", + 7095 => x"00", + 7096 => x"67", + 7097 => x"07", + 7098 => x"00", + 7099 => x"00", + 7100 => x"67", + 7101 => x"07", + 7102 => x"00", + 7103 => x"00", + 7104 => x"67", + 7105 => x"08", + 7106 => x"00", + 7107 => x"00", + 7108 => x"67", + 7109 => x"08", + 7110 => x"00", + 7111 => x"00", + 7112 => x"67", + 7113 => x"08", + 7114 => x"00", + 7115 => x"00", + 7116 => x"67", + 7117 => x"08", + 7118 => x"00", + 7119 => x"00", + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + 0 => x"0b", + 1 => x"04", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"08", + 10 => x"2d", + 11 => x"0c", + 12 => x"00", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"fd", + 17 => x"83", + 18 => x"05", + 19 => x"2b", + 20 => x"ff", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"fd", + 25 => x"ff", + 26 => x"06", + 27 => x"82", + 28 => x"2b", + 29 => x"83", + 30 => x"0b", + 31 => x"a5", + 32 => x"09", + 33 => x"05", + 34 => x"06", + 35 => x"09", + 36 => x"0a", + 37 => x"51", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"2e", + 42 => x"04", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"73", + 49 => x"06", + 50 => x"81", + 51 => x"10", + 52 => x"10", + 53 => x"0a", + 54 => x"51", + 55 => x"00", + 56 => x"72", + 57 => x"2e", + 58 => x"04", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"04", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"0a", + 81 => x"53", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"81", + 90 => x"0b", + 91 => x"04", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"9f", + 98 => x"74", + 99 => x"06", + 100 => x"07", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"06", + 106 => x"09", + 107 => x"05", + 108 => x"2b", + 109 => x"06", + 110 => x"04", + 111 => x"00", + 112 => x"09", + 113 => x"05", + 114 => x"05", + 115 => x"81", + 116 => x"04", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"09", + 121 => x"05", + 122 => x"05", + 123 => x"09", + 124 => x"51", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"09", + 129 => x"04", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"09", + 145 => x"73", + 146 => x"53", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"fc", + 153 => x"83", + 154 => x"05", + 155 => x"10", + 156 => x"ff", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"fc", + 161 => x"0b", + 162 => x"73", + 163 => x"10", + 164 => x"0b", + 165 => x"a4", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"08", + 170 => x"0b", + 171 => x"2d", + 172 => x"08", + 173 => x"8c", + 174 => x"51", + 175 => x"00", + 176 => x"08", + 177 => x"08", + 178 => x"0b", + 179 => x"2d", + 180 => x"08", + 181 => x"8c", + 182 => x"51", + 183 => x"00", + 184 => x"09", + 185 => x"09", + 186 => x"06", + 187 => x"54", + 188 => x"09", + 189 => x"ff", + 190 => x"51", + 191 => x"00", + 192 => x"09", + 193 => x"09", + 194 => x"81", + 195 => x"70", + 196 => x"73", + 197 => x"05", + 198 => x"07", + 199 => x"04", + 200 => x"ff", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"81", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"84", + 233 => x"10", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"71", + 250 => x"0d", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"00", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"0b", + 265 => x"04", + 266 => x"8c", + 267 => x"0b", + 268 => x"04", + 269 => x"8c", + 270 => x"0b", + 271 => x"04", + 272 => x"8c", + 273 => x"0b", + 274 => x"04", + 275 => x"8c", + 276 => x"0b", + 277 => x"04", + 278 => x"8c", + 279 => x"0b", + 280 => x"04", + 281 => x"8d", + 282 => x"0b", + 283 => x"04", + 284 => x"8d", + 285 => x"0b", + 286 => x"04", + 287 => x"8d", + 288 => x"0b", + 289 => x"04", + 290 => x"8d", + 291 => x"0b", + 292 => x"04", + 293 => x"8e", + 294 => x"0b", + 295 => x"04", + 296 => x"8e", + 297 => x"0b", + 298 => x"04", + 299 => x"8e", + 300 => x"0b", + 301 => x"04", + 302 => x"8e", + 303 => x"0b", + 304 => x"04", + 305 => x"8f", + 306 => x"0b", + 307 => x"04", + 308 => x"8f", + 309 => x"0b", + 310 => x"04", + 311 => x"8f", + 312 => x"0b", + 313 => x"04", + 314 => x"8f", + 315 => x"0b", + 316 => x"04", + 317 => x"90", + 318 => x"0b", + 319 => x"04", + 320 => x"90", + 321 => x"0b", + 322 => x"04", + 323 => x"90", + 324 => x"0b", + 325 => x"04", + 326 => x"90", + 327 => x"0b", + 328 => x"04", + 329 => x"91", + 330 => x"0b", + 331 => x"04", + 332 => x"91", + 333 => x"0b", + 334 => x"04", + 335 => x"91", + 336 => x"0b", + 337 => x"04", + 338 => x"91", + 339 => x"ff", + 340 => x"ff", + 341 => x"ff", + 342 => x"ff", + 343 => x"ff", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"00", + 385 => x"81", + 386 => x"a0", + 387 => x"de", + 388 => x"80", + 389 => x"de", + 390 => x"e2", + 391 => x"cc", + 392 => x"90", + 393 => x"cc", + 394 => x"2d", + 395 => x"08", + 396 => x"04", + 397 => x"0c", + 398 => x"81", + 399 => x"84", + 400 => x"81", + 401 => x"b4", + 402 => x"de", + 403 => x"80", + 404 => x"de", + 405 => x"fb", + 406 => x"cc", + 407 => x"90", + 408 => x"cc", + 409 => x"2d", + 410 => x"08", + 411 => x"04", + 412 => x"0c", + 413 => x"81", + 414 => x"84", + 415 => x"81", + 416 => x"b8", + 417 => x"de", + 418 => x"80", + 419 => x"de", + 420 => x"a3", + 421 => x"cc", + 422 => x"90", + 423 => x"cc", + 424 => x"2d", + 425 => x"08", + 426 => x"04", + 427 => x"0c", + 428 => x"81", + 429 => x"84", + 430 => x"81", + 431 => x"a2", + 432 => x"de", + 433 => x"80", + 434 => x"de", + 435 => x"8c", + 436 => x"cc", + 437 => x"90", + 438 => x"cc", + 439 => x"2d", + 440 => x"08", + 441 => x"04", + 442 => x"0c", + 443 => x"81", + 444 => x"84", + 445 => x"81", + 446 => x"9e", + 447 => x"de", + 448 => x"80", + 449 => x"de", + 450 => x"ea", + 451 => x"de", + 452 => x"80", + 453 => x"de", + 454 => x"f7", + 455 => x"de", + 456 => x"80", + 457 => x"de", + 458 => x"ef", + 459 => x"de", + 460 => x"80", + 461 => x"de", + 462 => x"f2", + 463 => x"de", + 464 => x"80", + 465 => x"de", + 466 => x"fc", + 467 => x"de", + 468 => x"80", + 469 => x"de", + 470 => x"85", + 471 => x"de", + 472 => x"80", + 473 => x"de", + 474 => x"f6", + 475 => x"de", + 476 => x"80", + 477 => x"de", + 478 => x"ff", + 479 => x"de", + 480 => x"80", + 481 => x"de", + 482 => x"80", + 483 => x"de", + 484 => x"80", + 485 => x"de", + 486 => x"81", + 487 => x"de", + 488 => x"80", + 489 => x"de", + 490 => x"89", + 491 => x"de", + 492 => x"80", + 493 => x"de", + 494 => x"86", + 495 => x"de", + 496 => x"80", + 497 => x"de", + 498 => x"8b", + 499 => x"de", + 500 => x"80", + 501 => x"de", + 502 => x"82", + 503 => x"de", + 504 => x"80", + 505 => x"de", + 506 => x"8e", + 507 => x"de", + 508 => x"80", + 509 => x"de", + 510 => x"8f", + 511 => x"de", + 512 => x"80", + 513 => x"de", + 514 => x"f8", + 515 => x"de", + 516 => x"80", + 517 => x"de", + 518 => x"f7", + 519 => x"de", + 520 => x"80", + 521 => x"de", + 522 => x"f9", + 523 => x"de", + 524 => x"80", + 525 => x"de", + 526 => x"82", + 527 => x"de", + 528 => x"80", + 529 => x"de", + 530 => x"90", + 531 => x"de", + 532 => x"80", + 533 => x"de", + 534 => x"92", + 535 => x"de", + 536 => x"80", + 537 => x"de", + 538 => x"96", + 539 => x"de", + 540 => x"80", + 541 => x"de", + 542 => x"e9", + 543 => x"de", + 544 => x"80", + 545 => x"de", + 546 => x"99", + 547 => x"de", + 548 => x"80", + 549 => x"de", + 550 => x"99", + 551 => x"cc", + 552 => x"90", + 553 => x"cc", + 554 => x"2d", + 555 => x"08", + 556 => x"04", + 557 => x"0c", + 558 => x"81", + 559 => x"84", + 560 => x"81", + 561 => x"9b", + 562 => x"de", + 563 => x"80", + 564 => x"de", + 565 => x"b3", + 566 => x"cc", + 567 => x"90", + 568 => x"cc", + 569 => x"2d", + 570 => x"08", + 571 => x"04", + 572 => x"0c", + 573 => x"2d", + 574 => x"08", + 575 => x"04", + 576 => x"10", + 577 => x"10", + 578 => x"10", + 579 => x"10", + 580 => x"10", + 581 => x"10", + 582 => x"10", + 583 => x"10", + 584 => x"04", + 585 => x"81", + 586 => x"83", + 587 => x"05", + 588 => x"10", + 589 => x"72", + 590 => x"51", + 591 => x"72", + 592 => x"06", + 593 => x"72", + 594 => x"10", + 595 => x"10", + 596 => x"ed", + 597 => x"53", + 598 => x"de", + 599 => x"f5", + 600 => x"38", + 601 => x"84", + 602 => x"0b", + 603 => x"db", + 604 => x"51", + 605 => x"04", + 606 => x"cc", + 607 => x"de", + 608 => x"3d", + 609 => x"81", + 610 => x"8c", + 611 => x"81", + 612 => x"88", + 613 => x"83", + 614 => x"de", + 615 => x"81", + 616 => x"54", + 617 => x"81", + 618 => x"04", + 619 => x"08", + 620 => x"cc", + 621 => x"0d", + 622 => x"de", + 623 => x"05", + 624 => x"de", + 625 => x"05", + 626 => x"a1", + 627 => x"c0", + 628 => x"de", + 629 => x"85", + 630 => x"de", + 631 => x"81", + 632 => x"02", + 633 => x"0c", + 634 => x"80", + 635 => x"cc", + 636 => x"0c", + 637 => x"08", + 638 => x"80", + 639 => x"81", + 640 => x"88", + 641 => x"81", + 642 => x"88", + 643 => x"0b", + 644 => x"08", + 645 => x"81", + 646 => x"fc", + 647 => x"38", + 648 => x"de", + 649 => x"05", + 650 => x"cc", + 651 => x"08", + 652 => x"08", + 653 => x"81", + 654 => x"8c", + 655 => x"25", + 656 => x"de", + 657 => x"05", + 658 => x"de", + 659 => x"05", + 660 => x"81", + 661 => x"f0", + 662 => x"de", + 663 => x"05", + 664 => x"81", + 665 => x"cc", + 666 => x"0c", + 667 => x"08", + 668 => x"81", + 669 => x"fc", + 670 => x"53", + 671 => x"08", + 672 => x"52", + 673 => x"08", + 674 => x"51", + 675 => x"81", + 676 => x"70", + 677 => x"08", + 678 => x"54", + 679 => x"08", + 680 => x"80", + 681 => x"81", + 682 => x"f8", + 683 => x"81", + 684 => x"f8", + 685 => x"de", + 686 => x"05", + 687 => x"de", + 688 => x"89", + 689 => x"de", + 690 => x"81", + 691 => x"02", + 692 => x"0c", + 693 => x"80", + 694 => x"cc", + 695 => x"0c", + 696 => x"08", + 697 => x"80", + 698 => x"81", + 699 => x"88", + 700 => x"81", + 701 => x"88", + 702 => x"0b", + 703 => x"08", + 704 => x"81", + 705 => x"8c", + 706 => x"25", + 707 => x"de", + 708 => x"05", + 709 => x"de", + 710 => x"05", + 711 => x"81", + 712 => x"8c", + 713 => x"81", + 714 => x"88", + 715 => x"bd", + 716 => x"c0", + 717 => x"de", + 718 => x"05", + 719 => x"de", + 720 => x"05", + 721 => x"90", + 722 => x"cc", + 723 => x"08", + 724 => x"cc", + 725 => x"0c", + 726 => x"08", + 727 => x"70", + 728 => x"0c", + 729 => x"0d", + 730 => x"0c", + 731 => x"cc", + 732 => x"de", + 733 => x"3d", + 734 => x"81", + 735 => x"fc", + 736 => x"0b", + 737 => x"08", + 738 => x"81", + 739 => x"8c", + 740 => x"de", + 741 => x"05", + 742 => x"38", + 743 => x"08", + 744 => x"80", + 745 => x"80", + 746 => x"cc", + 747 => x"08", + 748 => x"81", + 749 => x"8c", + 750 => x"81", + 751 => x"8c", + 752 => x"de", + 753 => x"05", + 754 => x"de", + 755 => x"05", + 756 => x"39", + 757 => x"08", + 758 => x"80", + 759 => x"38", + 760 => x"08", + 761 => x"81", + 762 => x"88", + 763 => x"ad", + 764 => x"cc", + 765 => x"08", + 766 => x"08", + 767 => x"31", + 768 => x"08", + 769 => x"81", + 770 => x"f8", + 771 => x"de", + 772 => x"05", + 773 => x"de", + 774 => x"05", + 775 => x"cc", + 776 => x"08", + 777 => x"de", + 778 => x"05", + 779 => x"cc", + 780 => x"08", + 781 => x"de", + 782 => x"05", + 783 => x"39", + 784 => x"08", + 785 => x"80", + 786 => x"81", + 787 => x"88", + 788 => x"81", + 789 => x"f4", + 790 => x"91", + 791 => x"cc", + 792 => x"08", + 793 => x"cc", + 794 => x"0c", + 795 => x"cc", + 796 => x"08", + 797 => x"0c", + 798 => x"81", + 799 => x"04", + 800 => x"76", + 801 => x"8c", + 802 => x"33", + 803 => x"55", + 804 => x"8a", + 805 => x"06", + 806 => x"2e", + 807 => x"12", + 808 => x"2e", + 809 => x"73", + 810 => x"55", + 811 => x"52", + 812 => x"09", + 813 => x"38", + 814 => x"c0", + 815 => x"0d", + 816 => x"88", + 817 => x"70", + 818 => x"07", + 819 => x"8f", + 820 => x"38", + 821 => x"84", + 822 => x"72", + 823 => x"05", + 824 => x"71", + 825 => x"53", + 826 => x"70", + 827 => x"0c", + 828 => x"71", + 829 => x"38", + 830 => x"90", + 831 => x"70", + 832 => x"0c", + 833 => x"71", + 834 => x"38", + 835 => x"8e", + 836 => x"0d", + 837 => x"72", + 838 => x"53", + 839 => x"93", + 840 => x"73", + 841 => x"54", + 842 => x"2e", + 843 => x"73", + 844 => x"71", + 845 => x"ff", + 846 => x"70", + 847 => x"38", + 848 => x"70", + 849 => x"81", + 850 => x"81", + 851 => x"71", + 852 => x"ff", + 853 => x"54", + 854 => x"38", + 855 => x"73", + 856 => x"75", + 857 => x"71", + 858 => x"de", + 859 => x"52", + 860 => x"04", + 861 => x"f7", + 862 => x"14", + 863 => x"84", + 864 => x"06", + 865 => x"70", + 866 => x"14", + 867 => x"08", + 868 => x"71", + 869 => x"dc", + 870 => x"54", + 871 => x"39", + 872 => x"de", + 873 => x"3d", + 874 => x"3d", + 875 => x"83", + 876 => x"2b", + 877 => x"3f", + 878 => x"08", + 879 => x"72", + 880 => x"54", + 881 => x"25", + 882 => x"81", + 883 => x"84", + 884 => x"fb", + 885 => x"70", + 886 => x"53", + 887 => x"2e", + 888 => x"71", + 889 => x"a0", + 890 => x"06", + 891 => x"12", + 892 => x"71", + 893 => x"81", + 894 => x"73", + 895 => x"ff", + 896 => x"55", + 897 => x"83", + 898 => x"70", + 899 => x"38", + 900 => x"73", + 901 => x"51", + 902 => x"09", + 903 => x"38", + 904 => x"81", + 905 => x"72", + 906 => x"51", + 907 => x"c0", + 908 => x"0d", + 909 => x"0d", + 910 => x"08", + 911 => x"38", + 912 => x"05", + 913 => x"9b", + 914 => x"de", + 915 => x"38", + 916 => x"39", + 917 => x"81", + 918 => x"86", + 919 => x"fc", + 920 => x"82", + 921 => x"05", + 922 => x"52", + 923 => x"81", + 924 => x"13", + 925 => x"51", + 926 => x"9e", + 927 => x"38", + 928 => x"51", + 929 => x"97", + 930 => x"38", + 931 => x"51", + 932 => x"bb", + 933 => x"38", + 934 => x"51", + 935 => x"bb", + 936 => x"38", + 937 => x"55", + 938 => x"87", + 939 => x"d9", + 940 => x"22", + 941 => x"73", + 942 => x"80", + 943 => x"0b", + 944 => x"9c", + 945 => x"87", + 946 => x"0c", + 947 => x"87", + 948 => x"0c", + 949 => x"87", + 950 => x"0c", + 951 => x"87", + 952 => x"0c", + 953 => x"87", + 954 => x"0c", + 955 => x"87", + 956 => x"0c", + 957 => x"98", + 958 => x"87", + 959 => x"0c", + 960 => x"c0", + 961 => x"80", + 962 => x"de", + 963 => x"3d", + 964 => x"3d", + 965 => x"87", + 966 => x"5d", + 967 => x"87", + 968 => x"08", + 969 => x"23", + 970 => x"b8", + 971 => x"82", + 972 => x"c0", + 973 => x"5a", + 974 => x"34", + 975 => x"b0", + 976 => x"84", + 977 => x"c0", + 978 => x"5a", + 979 => x"34", + 980 => x"a8", + 981 => x"86", + 982 => x"c0", + 983 => x"5c", + 984 => x"23", + 985 => x"a0", + 986 => x"8a", + 987 => x"7d", + 988 => x"ff", + 989 => x"7b", + 990 => x"06", + 991 => x"33", + 992 => x"33", + 993 => x"33", + 994 => x"33", + 995 => x"33", + 996 => x"ff", + 997 => x"81", + 998 => x"95", + 999 => x"3d", + 1000 => x"3d", + 1001 => x"05", + 1002 => x"70", + 1003 => x"52", + 1004 => x"0b", + 1005 => x"34", + 1006 => x"04", + 1007 => x"77", + 1008 => x"db", + 1009 => x"81", + 1010 => x"55", + 1011 => x"94", + 1012 => x"80", + 1013 => x"87", + 1014 => x"51", + 1015 => x"96", + 1016 => x"06", + 1017 => x"70", + 1018 => x"38", + 1019 => x"70", + 1020 => x"51", + 1021 => x"72", + 1022 => x"81", + 1023 => x"70", + 1024 => x"38", + 1025 => x"70", + 1026 => x"51", + 1027 => x"38", + 1028 => x"06", + 1029 => x"94", + 1030 => x"80", + 1031 => x"87", + 1032 => x"52", + 1033 => x"75", + 1034 => x"0c", + 1035 => x"04", + 1036 => x"02", + 1037 => x"0b", + 1038 => x"88", + 1039 => x"ff", + 1040 => x"56", + 1041 => x"84", + 1042 => x"2e", + 1043 => x"c0", + 1044 => x"70", + 1045 => x"2a", + 1046 => x"53", + 1047 => x"80", + 1048 => x"71", + 1049 => x"81", + 1050 => x"70", + 1051 => x"81", + 1052 => x"06", + 1053 => x"80", + 1054 => x"71", + 1055 => x"81", + 1056 => x"70", + 1057 => x"73", + 1058 => x"51", + 1059 => x"80", + 1060 => x"2e", + 1061 => x"c0", + 1062 => x"75", + 1063 => x"3d", + 1064 => x"3d", + 1065 => x"80", + 1066 => x"81", + 1067 => x"53", + 1068 => x"2e", + 1069 => x"71", + 1070 => x"81", + 1071 => x"81", + 1072 => x"70", + 1073 => x"59", + 1074 => x"87", + 1075 => x"51", + 1076 => x"86", + 1077 => x"94", + 1078 => x"08", + 1079 => x"70", + 1080 => x"54", + 1081 => x"2e", + 1082 => x"91", + 1083 => x"06", + 1084 => x"d7", + 1085 => x"32", + 1086 => x"51", + 1087 => x"2e", + 1088 => x"93", + 1089 => x"06", + 1090 => x"ff", + 1091 => x"81", + 1092 => x"87", + 1093 => x"52", + 1094 => x"86", + 1095 => x"94", + 1096 => x"72", + 1097 => x"74", + 1098 => x"ff", + 1099 => x"57", + 1100 => x"38", + 1101 => x"c0", + 1102 => x"0d", + 1103 => x"0d", + 1104 => x"db", + 1105 => x"81", + 1106 => x"52", + 1107 => x"84", + 1108 => x"2e", + 1109 => x"c0", + 1110 => x"70", + 1111 => x"2a", + 1112 => x"51", + 1113 => x"80", + 1114 => x"71", + 1115 => x"51", + 1116 => x"80", + 1117 => x"2e", + 1118 => x"c0", + 1119 => x"71", + 1120 => x"ff", + 1121 => x"c0", + 1122 => x"3d", + 1123 => x"3d", + 1124 => x"81", + 1125 => x"70", + 1126 => x"52", + 1127 => x"94", + 1128 => x"80", + 1129 => x"87", + 1130 => x"52", + 1131 => x"82", + 1132 => x"06", + 1133 => x"ff", + 1134 => x"2e", + 1135 => x"81", + 1136 => x"87", + 1137 => x"52", + 1138 => x"86", + 1139 => x"94", + 1140 => x"08", + 1141 => x"70", + 1142 => x"53", + 1143 => x"de", + 1144 => x"3d", + 1145 => x"3d", + 1146 => x"9e", + 1147 => x"9c", + 1148 => x"51", + 1149 => x"2e", + 1150 => x"87", + 1151 => x"08", + 1152 => x"0c", + 1153 => x"a8", + 1154 => x"90", + 1155 => x"9e", + 1156 => x"db", + 1157 => x"c0", + 1158 => x"81", + 1159 => x"87", + 1160 => x"08", + 1161 => x"0c", + 1162 => x"a0", + 1163 => x"a0", + 1164 => x"9e", + 1165 => x"db", + 1166 => x"c0", + 1167 => x"81", + 1168 => x"87", + 1169 => x"08", + 1170 => x"0c", + 1171 => x"b8", + 1172 => x"b0", + 1173 => x"9e", + 1174 => x"db", + 1175 => x"c0", + 1176 => x"81", + 1177 => x"87", + 1178 => x"08", + 1179 => x"0c", + 1180 => x"80", + 1181 => x"81", + 1182 => x"87", + 1183 => x"08", + 1184 => x"0c", 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x"71", + 1244 => x"34", + 1245 => x"c0", + 1246 => x"70", + 1247 => x"06", + 1248 => x"70", + 1249 => x"38", + 1250 => x"81", + 1251 => x"80", + 1252 => x"9e", + 1253 => x"80", + 1254 => x"51", + 1255 => x"80", + 1256 => x"81", + 1257 => x"db", + 1258 => x"0b", + 1259 => x"90", + 1260 => x"80", + 1261 => x"52", + 1262 => x"83", + 1263 => x"71", + 1264 => x"34", + 1265 => x"90", + 1266 => x"80", + 1267 => x"2a", + 1268 => x"70", + 1269 => x"34", + 1270 => x"c0", + 1271 => x"70", + 1272 => x"51", + 1273 => x"80", + 1274 => x"81", + 1275 => x"db", + 1276 => x"c0", + 1277 => x"70", + 1278 => x"70", + 1279 => x"51", + 1280 => x"db", + 1281 => x"0b", + 1282 => x"90", + 1283 => x"06", + 1284 => x"70", + 1285 => x"38", + 1286 => x"81", + 1287 => x"87", + 1288 => x"08", + 1289 => x"51", + 1290 => x"db", + 1291 => x"3d", + 1292 => x"3d", + 1293 => x"fc", + 1294 => x"3f", + 1295 => x"33", + 1296 => x"2e", + 1297 => x"c7", + 1298 => x"f5", + 1299 => x"a4", + 1300 => x"3f", + 1301 => x"33", + 1302 => x"2e", + 1303 => x"db", + 1304 => x"db", + 1305 => x"54", + 1306 => x"bc", + 1307 => x"3f", + 1308 => x"33", + 1309 => x"2e", + 1310 => x"db", + 1311 => x"db", + 1312 => x"54", + 1313 => x"d8", + 1314 => x"3f", + 1315 => x"33", + 1316 => x"2e", + 1317 => x"db", + 1318 => x"db", + 1319 => x"54", + 1320 => x"f4", + 1321 => x"3f", + 1322 => x"33", + 1323 => x"2e", + 1324 => x"db", + 1325 => x"db", + 1326 => x"54", + 1327 => x"90", + 1328 => x"3f", + 1329 => x"33", + 1330 => x"2e", + 1331 => x"db", + 1332 => x"db", + 1333 => x"54", + 1334 => x"ac", + 1335 => x"3f", + 1336 => x"33", + 1337 => x"2e", + 1338 => x"db", + 1339 => x"81", + 1340 => x"8a", + 1341 => x"db", + 1342 => x"73", + 1343 => x"38", + 1344 => x"33", + 1345 => x"e8", + 1346 => x"3f", + 1347 => x"33", + 1348 => x"2e", + 1349 => x"db", + 1350 => x"81", + 1351 => x"8a", + 1352 => x"db", + 1353 => x"73", + 1354 => x"38", + 1355 => x"51", + 1356 => x"81", + 1357 => x"54", + 1358 => x"88", + 1359 => x"bc", + 1360 => x"3f", + 1361 => x"33", + 1362 => x"2e", + 1363 => x"c9", + 1364 => x"ed", + 1365 => x"d9", + 1366 => x"80", + 1367 => x"81", + 1368 => x"83", + 1369 => x"db", + 1370 => x"73", + 1371 => x"38", + 1372 => x"51", + 1373 => x"81", + 1374 => x"83", + 1375 => x"db", + 1376 => x"81", + 1377 => x"89", + 1378 => x"db", + 1379 => x"81", + 1380 => x"89", + 1381 => x"db", + 1382 => x"81", + 1383 => x"89", + 1384 => x"ca", + 1385 => x"fa", + 1386 => x"c0", + 1387 => x"ca", + 1388 => x"f1", + 1389 => x"c4", + 1390 => x"84", + 1391 => x"51", + 1392 => x"81", + 1393 => x"bd", + 1394 => x"76", + 1395 => x"54", + 1396 => x"08", + 1397 => x"a0", + 1398 => x"3f", + 1399 => x"33", + 1400 => x"2e", + 1401 => x"db", + 1402 => x"bd", + 1403 => x"75", + 1404 => x"3f", + 1405 => x"08", + 1406 => x"29", + 1407 => x"54", + 1408 => x"c0", + 1409 => x"cb", + 1410 => x"99", + 1411 => x"d2", + 1412 => x"80", + 1413 => x"81", + 1414 => x"56", + 1415 => x"52", + 1416 => x"d5", + 1417 => x"c0", + 1418 => x"c0", + 1419 => x"31", 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x"72", + 1479 => x"84", + 1480 => x"fe", + 1481 => x"97", + 1482 => x"de", + 1483 => x"81", + 1484 => x"54", + 1485 => x"3f", + 1486 => x"d0", + 1487 => x"0d", + 1488 => x"0d", + 1489 => x"33", + 1490 => x"06", + 1491 => x"80", + 1492 => x"72", + 1493 => x"51", + 1494 => x"ff", + 1495 => x"39", + 1496 => x"04", + 1497 => x"77", + 1498 => x"08", + 1499 => x"d0", + 1500 => x"73", + 1501 => x"ff", + 1502 => x"71", + 1503 => x"38", + 1504 => x"06", + 1505 => x"54", + 1506 => x"e7", + 1507 => x"de", + 1508 => x"3d", + 1509 => x"3d", + 1510 => x"59", + 1511 => x"81", + 1512 => x"56", + 1513 => x"84", + 1514 => x"a5", + 1515 => x"06", + 1516 => x"80", + 1517 => x"81", + 1518 => x"58", + 1519 => x"b0", + 1520 => x"06", + 1521 => x"5a", + 1522 => x"ad", + 1523 => x"06", + 1524 => x"5a", + 1525 => x"05", + 1526 => x"75", + 1527 => x"81", + 1528 => x"77", + 1529 => x"08", + 1530 => x"05", + 1531 => x"5d", + 1532 => x"39", + 1533 => x"72", + 1534 => x"38", + 1535 => x"7b", + 1536 => x"05", + 1537 => x"70", + 1538 => x"33", + 1539 => x"39", + 1540 => x"32", + 1541 => x"72", + 1542 => x"78", + 1543 => x"70", + 1544 => x"07", + 1545 => x"07", + 1546 => x"51", + 1547 => x"80", + 1548 => x"79", + 1549 => x"70", + 1550 => x"33", + 1551 => x"80", + 1552 => x"38", + 1553 => x"e0", + 1554 => x"38", + 1555 => x"81", + 1556 => x"53", + 1557 => x"2e", + 1558 => x"73", + 1559 => x"a2", + 1560 => x"c3", + 1561 => x"38", + 1562 => x"24", + 1563 => x"80", + 1564 => x"8c", + 1565 => x"39", + 1566 => x"2e", + 1567 => x"81", + 1568 => x"80", + 1569 => x"80", + 1570 => x"d5", + 1571 => x"73", + 1572 => x"8e", + 1573 => x"39", + 1574 => x"2e", + 1575 => x"80", + 1576 => x"84", + 1577 => x"56", + 1578 => x"74", + 1579 => x"72", + 1580 => x"38", + 1581 => x"15", + 1582 => x"54", + 1583 => x"38", + 1584 => x"56", + 1585 => x"81", + 1586 => x"72", + 1587 => x"38", + 1588 => x"90", + 1589 => x"06", + 1590 => x"2e", + 1591 => x"51", + 1592 => x"74", + 1593 => x"53", + 1594 => x"fd", + 1595 => x"51", + 1596 => x"ef", + 1597 => x"19", + 1598 => x"53", + 1599 => x"39", + 1600 => x"39", + 1601 => x"39", + 1602 => x"39", + 1603 => x"39", + 1604 => x"d0", + 1605 => x"39", + 1606 => x"70", + 1607 => x"53", + 1608 => x"88", + 1609 => x"19", + 1610 => x"39", + 1611 => x"54", + 1612 => x"74", + 1613 => x"70", + 1614 => x"07", + 1615 => x"55", + 1616 => x"80", + 1617 => x"72", + 1618 => x"38", + 1619 => x"90", + 1620 => x"80", + 1621 => x"5e", + 1622 => x"74", + 1623 => x"3f", + 1624 => x"08", + 1625 => x"7c", + 1626 => x"54", + 1627 => x"81", + 1628 => x"55", + 1629 => x"92", + 1630 => x"53", + 1631 => x"2e", + 1632 => x"14", + 1633 => x"ff", + 1634 => x"14", + 1635 => x"70", + 1636 => x"34", + 1637 => x"30", + 1638 => x"9f", + 1639 => x"57", + 1640 => x"85", + 1641 => x"b1", + 1642 => x"2a", + 1643 => x"51", + 1644 => x"2e", + 1645 => x"3d", + 1646 => x"05", + 1647 => x"34", + 1648 => x"76", + 1649 => x"54", + 1650 => x"72", + 1651 => x"54", + 1652 => x"70", + 1653 => x"56", + 1654 => x"81", + 1655 => x"7b", + 1656 => x"73", + 1657 => x"3f", + 1658 => x"53", + 1659 => x"74", + 1660 => x"53", + 1661 => x"eb", + 1662 => x"77", + 1663 => x"53", + 1664 => x"14", + 1665 => x"54", + 1666 => x"3f", + 1667 => x"74", + 1668 => x"53", + 1669 => x"fb", + 1670 => x"51", + 1671 => x"ef", + 1672 => x"0d", + 1673 => x"0d", + 1674 => x"70", + 1675 => x"08", + 1676 => x"51", + 1677 => x"85", + 1678 => x"fe", + 1679 => x"81", + 1680 => x"85", + 1681 => x"52", + 1682 => x"ca", + 1683 => x"d8", + 1684 => x"73", + 1685 => x"81", + 1686 => x"84", + 1687 => x"fd", + 1688 => x"de", + 1689 => x"81", + 1690 => x"87", + 1691 => x"53", + 1692 => x"fa", + 1693 => x"81", + 1694 => x"85", + 1695 => x"fb", + 1696 => x"79", + 1697 => x"08", + 1698 => x"57", + 1699 => x"71", + 1700 => x"e0", + 1701 => x"d4", + 1702 => x"2d", + 1703 => x"08", + 1704 => x"53", + 1705 => x"80", + 1706 => x"8d", + 1707 => x"72", + 1708 => x"30", + 1709 => x"51", + 1710 => x"80", + 1711 => x"71", + 1712 => x"38", + 1713 => x"97", + 1714 => x"25", + 1715 => x"16", + 1716 => x"25", + 1717 => x"14", + 1718 => x"34", + 1719 => x"72", + 1720 => x"3f", + 1721 => x"73", + 1722 => x"72", + 1723 => x"f7", + 1724 => x"53", + 1725 => x"c0", + 1726 => x"0d", + 1727 => x"0d", + 1728 => x"08", + 1729 => x"d4", + 1730 => x"76", + 1731 => x"ef", + 1732 => x"de", + 1733 => x"3d", + 1734 => x"3d", + 1735 => x"5a", + 1736 => x"7a", + 1737 => x"08", + 1738 => x"53", + 1739 => x"09", + 1740 => x"38", + 1741 => x"0c", + 1742 => x"ad", + 1743 => x"06", + 1744 => x"76", + 1745 => x"0c", + 1746 => x"33", + 1747 => x"73", + 1748 => x"81", + 1749 => x"38", + 1750 => x"05", + 1751 => x"08", + 1752 => x"53", + 1753 => x"2e", + 1754 => x"57", + 1755 => x"2e", + 1756 => x"39", + 1757 => x"13", + 1758 => x"08", + 1759 => x"53", + 1760 => x"55", + 1761 => x"80", + 1762 => x"14", + 1763 => x"88", + 1764 => x"27", + 1765 => x"eb", + 1766 => x"53", + 1767 => x"89", + 1768 => x"38", + 1769 => x"55", + 1770 => x"8a", + 1771 => x"a0", + 1772 => x"c2", + 1773 => x"74", + 1774 => x"e0", + 1775 => x"ff", + 1776 => x"d0", + 1777 => x"ff", + 1778 => x"90", + 1779 => x"38", + 1780 => x"81", + 1781 => x"53", + 1782 => x"ca", + 1783 => x"27", + 1784 => x"77", + 1785 => x"08", + 1786 => x"0c", + 1787 => x"33", + 1788 => x"ff", + 1789 => x"80", + 1790 => x"74", + 1791 => x"79", + 1792 => x"74", + 1793 => x"0c", + 1794 => x"04", + 1795 => x"7a", + 1796 => x"80", + 1797 => x"58", + 1798 => x"33", + 1799 => x"a0", + 1800 => x"06", + 1801 => x"13", + 1802 => x"39", + 1803 => x"09", + 1804 => x"38", + 1805 => x"11", + 1806 => x"08", + 1807 => x"54", + 1808 => x"2e", + 1809 => x"80", + 1810 => x"08", + 1811 => x"0c", + 1812 => x"33", + 1813 => x"80", + 1814 => x"38", + 1815 => x"80", + 1816 => x"38", + 1817 => x"57", + 1818 => x"0c", + 1819 => x"33", + 1820 => x"39", + 1821 => x"74", + 1822 => x"38", + 1823 => x"80", + 1824 => x"89", + 1825 => x"38", + 1826 => x"d0", + 1827 => x"55", + 1828 => x"80", + 1829 => x"39", + 1830 => x"d9", + 1831 => x"80", + 1832 => x"27", + 1833 => x"80", + 1834 => x"89", + 1835 => x"70", + 1836 => x"55", + 1837 => x"70", + 1838 => x"55", + 1839 => x"27", + 1840 => x"14", + 1841 => x"06", + 1842 => x"74", + 1843 => x"73", + 1844 => x"38", + 1845 => x"14", + 1846 => x"05", + 1847 => x"08", + 1848 => x"54", + 1849 => x"39", + 1850 => x"84", + 1851 => x"55", + 1852 => x"81", + 1853 => x"de", + 1854 => x"3d", + 1855 => x"3d", + 1856 => x"05", + 1857 => x"52", + 1858 => x"87", + 1859 => x"e8", + 1860 => x"71", + 1861 => x"0c", + 1862 => x"04", + 1863 => x"02", + 1864 => x"02", + 1865 => x"05", + 1866 => x"83", + 1867 => x"26", + 1868 => x"72", + 1869 => x"c0", + 1870 => x"53", + 1871 => x"74", + 1872 => x"38", + 1873 => x"73", + 1874 => x"c0", + 1875 => x"51", + 1876 => x"85", + 1877 => x"98", + 1878 => x"52", + 1879 => x"82", + 1880 => x"70", + 1881 => x"38", + 1882 => x"8c", + 1883 => x"ec", + 1884 => x"fc", + 1885 => x"52", + 1886 => x"87", + 1887 => x"08", + 1888 => x"2e", + 1889 => x"81", + 1890 => x"34", + 1891 => x"13", + 1892 => x"81", + 1893 => x"86", + 1894 => x"f3", + 1895 => x"62", + 1896 => x"05", + 1897 => x"57", + 1898 => x"83", + 1899 => x"fe", + 1900 => x"de", + 1901 => x"06", + 1902 => x"71", + 1903 => x"71", + 1904 => x"2b", + 1905 => x"80", + 1906 => x"92", + 1907 => x"c0", + 1908 => x"41", + 1909 => x"5a", + 1910 => x"87", + 1911 => x"0c", + 1912 => x"84", + 1913 => x"08", + 1914 => x"70", + 1915 => x"53", + 1916 => x"2e", + 1917 => x"08", + 1918 => x"70", + 1919 => x"34", + 1920 => x"80", + 1921 => x"53", + 1922 => x"2e", + 1923 => x"53", + 1924 => x"26", + 1925 => x"80", + 1926 => x"87", + 1927 => x"08", + 1928 => x"38", + 1929 => x"8c", + 1930 => x"80", + 1931 => x"78", + 1932 => x"99", + 1933 => x"0c", + 1934 => x"8c", + 1935 => x"08", + 1936 => x"51", + 1937 => x"38", + 1938 => x"8d", + 1939 => x"17", + 1940 => x"81", + 1941 => x"53", + 1942 => x"2e", + 1943 => x"fc", + 1944 => x"52", + 1945 => x"7d", + 1946 => x"ed", + 1947 => x"80", + 1948 => x"71", + 1949 => x"38", + 1950 => x"53", + 1951 => x"c0", + 1952 => x"0d", + 1953 => x"0d", + 1954 => x"02", + 1955 => x"05", + 1956 => x"58", + 1957 => x"80", + 1958 => x"fc", + 1959 => x"de", + 1960 => x"06", + 1961 => x"71", + 1962 => x"81", + 1963 => x"38", + 1964 => x"2b", + 1965 => x"80", + 1966 => x"92", + 1967 => x"c0", + 1968 => x"40", + 1969 => x"5a", + 1970 => x"c0", + 1971 => x"76", + 1972 => x"76", + 1973 => x"75", + 1974 => x"2a", + 1975 => x"51", + 1976 => x"80", + 1977 => x"7a", + 1978 => x"5c", + 1979 => x"81", + 1980 => x"81", + 1981 => x"06", + 1982 => x"80", + 1983 => x"87", + 1984 => x"08", + 1985 => x"38", + 1986 => x"8c", + 1987 => x"80", + 1988 => x"77", + 1989 => x"99", + 1990 => x"0c", + 1991 => x"8c", + 1992 => x"08", + 1993 => x"51", + 1994 => x"38", + 1995 => x"8d", + 1996 => x"70", + 1997 => x"84", + 1998 => x"5b", + 1999 => x"2e", + 2000 => x"fc", + 2001 => x"52", + 2002 => x"7d", + 2003 => x"f8", + 2004 => x"80", + 2005 => x"71", + 2006 => x"38", + 2007 => x"53", + 2008 => x"c0", + 2009 => x"0d", + 2010 => x"0d", + 2011 => x"05", + 2012 => x"02", + 2013 => x"05", + 2014 => x"54", + 2015 => x"fe", + 2016 => x"c0", + 2017 => x"53", + 2018 => x"80", + 2019 => x"0b", + 2020 => x"8c", + 2021 => x"71", + 2022 => x"dc", + 2023 => x"24", + 2024 => x"84", + 2025 => x"92", + 2026 => x"54", + 2027 => x"8d", + 2028 => x"39", + 2029 => x"80", + 2030 => x"cb", + 2031 => x"70", + 2032 => x"81", + 2033 => x"52", + 2034 => x"8a", + 2035 => x"98", + 2036 => x"71", + 2037 => x"c0", + 2038 => x"52", + 2039 => x"81", + 2040 => x"c0", + 2041 => x"53", + 2042 => x"82", + 2043 => x"71", + 2044 => x"39", + 2045 => x"39", + 2046 => x"77", + 2047 => x"81", + 2048 => x"72", + 2049 => x"84", + 2050 => x"73", + 2051 => x"0c", + 2052 => x"04", + 2053 => x"74", + 2054 => x"71", + 2055 => x"2b", + 2056 => x"c0", + 2057 => x"84", + 2058 => x"fd", + 2059 => x"83", + 2060 => x"12", + 2061 => x"2b", + 2062 => x"07", + 2063 => x"70", + 2064 => x"2b", + 2065 => x"07", + 2066 => x"0c", + 2067 => x"56", + 2068 => x"3d", + 2069 => x"3d", + 2070 => x"84", + 2071 => x"22", + 2072 => x"72", + 2073 => x"54", + 2074 => x"2a", + 2075 => x"34", + 2076 => x"04", + 2077 => x"73", + 2078 => x"70", + 2079 => x"05", + 2080 => x"88", + 2081 => x"72", + 2082 => x"54", + 2083 => x"2a", + 2084 => x"70", + 2085 => x"34", + 2086 => x"51", + 2087 => x"83", + 2088 => x"fe", + 2089 => x"75", + 2090 => x"51", + 2091 => x"92", + 2092 => x"81", + 2093 => x"73", + 2094 => x"55", + 2095 => x"51", + 2096 => x"3d", + 2097 => x"3d", + 2098 => x"76", + 2099 => x"72", + 2100 => x"05", + 2101 => x"11", + 2102 => x"38", + 2103 => x"04", + 2104 => x"78", + 2105 => x"56", + 2106 => x"81", + 2107 => x"74", + 2108 => x"56", + 2109 => x"31", + 2110 => x"52", + 2111 => x"80", + 2112 => x"71", + 2113 => x"38", + 2114 => x"c0", + 2115 => x"0d", + 2116 => x"0d", + 2117 => x"51", + 2118 => x"73", + 2119 => x"81", + 2120 => x"33", + 2121 => x"38", + 2122 => x"de", + 2123 => x"3d", + 2124 => x"0b", + 2125 => x"0c", + 2126 => x"81", + 2127 => x"04", + 2128 => x"7b", + 2129 => x"83", + 2130 => x"5a", + 2131 => x"80", + 2132 => x"54", + 2133 => x"53", + 2134 => x"53", + 2135 => x"52", + 2136 => x"3f", + 2137 => x"08", + 2138 => x"81", + 2139 => x"81", + 2140 => x"83", + 2141 => x"16", + 2142 => x"18", + 2143 => x"18", + 2144 => x"58", + 2145 => x"9f", + 2146 => x"33", + 2147 => x"2e", + 2148 => x"93", + 2149 => x"76", + 2150 => x"52", + 2151 => x"51", + 2152 => x"83", + 2153 => x"79", + 2154 => x"0c", + 2155 => x"04", + 2156 => x"78", + 2157 => x"80", + 2158 => x"17", + 2159 => x"38", + 2160 => x"fc", + 2161 => x"c0", + 2162 => x"de", + 2163 => x"38", + 2164 => x"53", + 2165 => x"81", + 2166 => x"f7", + 2167 => x"de", + 2168 => x"2e", + 2169 => x"55", + 2170 => x"b0", + 2171 => x"81", + 2172 => x"88", + 2173 => x"f8", + 2174 => x"70", + 2175 => x"c0", + 2176 => x"c0", + 2177 => x"de", + 2178 => x"91", + 2179 => x"55", + 2180 => x"09", + 2181 => x"f0", + 2182 => x"33", + 2183 => x"2e", + 2184 => x"80", + 2185 => x"80", + 2186 => x"c0", + 2187 => x"17", + 2188 => x"fd", + 2189 => x"d4", + 2190 => x"b2", + 2191 => x"96", + 2192 => x"85", + 2193 => x"75", + 2194 => x"3f", + 2195 => x"e4", + 2196 => x"98", + 2197 => x"9c", + 2198 => x"08", + 2199 => x"17", + 2200 => x"3f", + 2201 => x"52", + 2202 => x"51", + 2203 => x"a0", + 2204 => x"05", + 2205 => x"0c", + 2206 => x"75", + 2207 => x"33", + 2208 => x"3f", + 2209 => x"34", + 2210 => x"52", + 2211 => x"51", + 2212 => x"81", + 2213 => x"80", + 2214 => x"81", + 2215 => x"de", + 2216 => x"3d", + 2217 => x"3d", + 2218 => x"1a", + 2219 => x"fe", + 2220 => x"54", + 2221 => x"73", + 2222 => x"8a", + 2223 => x"71", + 2224 => x"08", + 2225 => x"75", + 2226 => x"0c", + 2227 => x"04", + 2228 => x"7a", + 2229 => x"56", + 2230 => x"77", + 2231 => x"38", + 2232 => x"08", + 2233 => x"38", + 2234 => x"54", + 2235 => x"2e", + 2236 => x"72", + 2237 => x"38", + 2238 => x"8d", + 2239 => x"39", + 2240 => x"81", + 2241 => x"b6", + 2242 => x"2a", + 2243 => x"2a", + 2244 => x"05", + 2245 => x"55", + 2246 => x"81", + 2247 => x"81", + 2248 => x"83", + 2249 => x"b4", + 2250 => x"17", + 2251 => x"a4", + 2252 => x"55", + 2253 => x"57", + 2254 => x"3f", + 2255 => x"08", + 2256 => x"74", + 2257 => x"14", + 2258 => x"70", + 2259 => x"07", + 2260 => x"71", + 2261 => x"52", + 2262 => x"72", + 2263 => x"75", + 2264 => x"58", + 2265 => x"76", + 2266 => x"15", + 2267 => x"73", + 2268 => x"3f", + 2269 => x"08", + 2270 => x"76", + 2271 => x"06", + 2272 => x"05", + 2273 => x"3f", + 2274 => x"08", + 2275 => x"06", + 2276 => x"76", + 2277 => x"15", + 2278 => x"73", + 2279 => x"3f", + 2280 => x"08", + 2281 => x"82", + 2282 => x"06", + 2283 => x"05", + 2284 => x"3f", + 2285 => x"08", + 2286 => x"58", + 2287 => x"58", + 2288 => x"c0", + 2289 => x"0d", + 2290 => x"0d", + 2291 => x"5a", + 2292 => x"59", + 2293 => x"82", + 2294 => x"98", + 2295 => x"82", + 2296 => x"33", + 2297 => x"2e", + 2298 => x"72", + 2299 => x"38", + 2300 => x"8d", + 2301 => x"39", + 2302 => x"81", + 2303 => x"f7", + 2304 => x"2a", + 2305 => x"2a", + 2306 => x"05", + 2307 => x"55", + 2308 => x"81", + 2309 => x"59", + 2310 => x"08", + 2311 => x"74", + 2312 => x"16", + 2313 => x"16", + 2314 => x"59", + 2315 => x"53", + 2316 => x"8f", + 2317 => x"2b", + 2318 => x"74", + 2319 => x"71", + 2320 => x"72", + 2321 => x"0b", + 2322 => x"74", + 2323 => x"17", + 2324 => x"75", + 2325 => x"3f", + 2326 => x"08", + 2327 => x"c0", + 2328 => x"38", + 2329 => x"06", + 2330 => x"78", + 2331 => x"54", + 2332 => x"77", + 2333 => x"33", + 2334 => x"71", + 2335 => x"51", + 2336 => x"34", + 2337 => x"76", + 2338 => x"17", + 2339 => x"75", + 2340 => x"3f", + 2341 => x"08", + 2342 => x"c0", + 2343 => x"38", + 2344 => x"ff", + 2345 => x"10", + 2346 => x"76", + 2347 => x"51", + 2348 => x"be", + 2349 => x"2a", + 2350 => x"05", + 2351 => x"f9", + 2352 => x"de", + 2353 => x"81", + 2354 => x"ab", + 2355 => x"0a", + 2356 => x"2b", + 2357 => x"70", + 2358 => x"70", + 2359 => x"54", + 2360 => x"81", + 2361 => x"8f", + 2362 => x"07", + 2363 => x"f7", + 2364 => x"0b", + 2365 => x"78", + 2366 => x"0c", + 2367 => x"04", + 2368 => x"7a", + 2369 => x"08", + 2370 => x"59", + 2371 => x"a4", + 2372 => x"17", + 2373 => x"38", + 2374 => x"aa", + 2375 => x"73", + 2376 => x"fd", + 2377 => x"de", + 2378 => x"81", + 2379 => x"80", + 2380 => x"39", + 2381 => x"eb", + 2382 => x"80", + 2383 => x"de", + 2384 => x"80", + 2385 => x"52", + 2386 => x"84", + 2387 => x"c0", + 2388 => x"de", + 2389 => x"2e", + 2390 => x"81", + 2391 => x"81", + 2392 => x"81", + 2393 => x"ff", + 2394 => x"80", + 2395 => x"75", + 2396 => x"3f", + 2397 => x"08", + 2398 => x"16", + 2399 => x"90", + 2400 => x"55", + 2401 => x"27", + 2402 => x"15", + 2403 => x"84", + 2404 => x"07", + 2405 => x"17", + 2406 => x"76", + 2407 => x"a6", + 2408 => x"73", + 2409 => x"0c", + 2410 => x"04", + 2411 => x"7c", + 2412 => x"59", + 2413 => x"95", + 2414 => x"08", + 2415 => x"2e", + 2416 => x"17", + 2417 => x"b2", + 2418 => x"ae", + 2419 => x"7a", + 2420 => x"3f", + 2421 => x"81", + 2422 => x"27", + 2423 => x"81", + 2424 => x"55", + 2425 => x"08", + 2426 => x"d2", + 2427 => x"08", + 2428 => x"08", + 2429 => x"38", + 2430 => x"17", + 2431 => x"54", + 2432 => x"82", + 2433 => x"7a", + 2434 => x"06", + 2435 => x"81", + 2436 => x"17", + 2437 => x"83", + 2438 => x"75", + 2439 => x"f9", + 2440 => x"59", + 2441 => x"08", + 2442 => x"81", + 2443 => x"81", + 2444 => x"59", + 2445 => x"08", + 2446 => x"70", + 2447 => x"25", + 2448 => x"81", + 2449 => x"54", + 2450 => x"55", + 2451 => x"38", + 2452 => x"08", + 2453 => x"38", + 2454 => x"54", + 2455 => x"90", + 2456 => x"18", + 2457 => x"38", + 2458 => x"39", + 2459 => x"38", + 2460 => x"16", + 2461 => x"08", + 2462 => x"38", + 2463 => x"78", + 2464 => x"38", + 2465 => x"51", + 2466 => x"81", + 2467 => x"80", + 2468 => x"80", + 2469 => x"c0", + 2470 => x"09", + 2471 => x"38", + 2472 => x"08", + 2473 => x"c0", + 2474 => x"30", + 2475 => x"80", + 2476 => x"07", + 2477 => x"55", + 2478 => x"38", + 2479 => x"09", + 2480 => x"ae", + 2481 => x"80", + 2482 => x"53", + 2483 => x"51", + 2484 => x"81", + 2485 => x"81", + 2486 => x"30", + 2487 => x"c0", + 2488 => x"25", + 2489 => x"79", + 2490 => x"38", + 2491 => x"8f", + 2492 => x"79", + 2493 => x"f9", + 2494 => x"de", + 2495 => x"74", + 2496 => x"8c", + 2497 => x"17", + 2498 => x"90", + 2499 => x"54", + 2500 => x"86", + 2501 => x"90", + 2502 => x"17", + 2503 => x"54", + 2504 => x"34", + 2505 => x"56", + 2506 => x"90", + 2507 => x"80", + 2508 => x"81", + 2509 => x"55", + 2510 => x"56", + 2511 => x"81", + 2512 => x"8c", + 2513 => x"f8", + 2514 => x"70", + 2515 => x"f0", + 2516 => x"c0", + 2517 => x"56", + 2518 => x"08", + 2519 => x"7b", + 2520 => x"f6", + 2521 => x"de", + 2522 => x"de", + 2523 => x"17", + 2524 => x"80", + 2525 => x"b4", + 2526 => x"57", + 2527 => x"77", + 2528 => x"81", + 2529 => x"15", + 2530 => x"78", + 2531 => x"81", + 2532 => x"53", + 2533 => x"15", + 2534 => x"e9", + 2535 => x"c0", + 2536 => x"df", + 2537 => x"22", + 2538 => x"30", + 2539 => x"70", + 2540 => x"51", + 2541 => x"81", + 2542 => x"8a", + 2543 => x"f8", + 2544 => x"7c", + 2545 => x"56", + 2546 => x"80", + 2547 => x"f1", + 2548 => x"06", + 2549 => x"e9", + 2550 => x"18", + 2551 => x"08", + 2552 => x"38", + 2553 => x"82", + 2554 => x"38", + 2555 => x"54", + 2556 => x"74", + 2557 => x"82", + 2558 => x"22", + 2559 => x"79", + 2560 => x"38", + 2561 => x"98", + 2562 => x"cd", + 2563 => x"22", + 2564 => x"54", + 2565 => x"26", + 2566 => x"52", + 2567 => x"b0", + 2568 => x"c0", + 2569 => x"de", + 2570 => x"2e", + 2571 => x"0b", + 2572 => x"08", + 2573 => x"98", + 2574 => x"de", + 2575 => x"85", + 2576 => x"bd", + 2577 => x"31", + 2578 => x"73", + 2579 => x"f4", + 2580 => x"de", + 2581 => x"18", + 2582 => x"18", + 2583 => x"08", + 2584 => x"72", + 2585 => x"38", + 2586 => x"58", + 2587 => x"89", + 2588 => x"18", + 2589 => x"ff", + 2590 => x"05", + 2591 => x"80", + 2592 => x"de", + 2593 => x"3d", + 2594 => x"3d", + 2595 => x"08", + 2596 => x"a0", + 2597 => x"54", + 2598 => x"77", + 2599 => x"80", + 2600 => x"0c", + 2601 => x"53", + 2602 => x"80", + 2603 => x"38", + 2604 => x"06", + 2605 => x"b5", + 2606 => x"98", + 2607 => x"14", + 2608 => x"92", + 2609 => x"2a", + 2610 => x"56", + 2611 => x"26", + 2612 => x"80", + 2613 => x"16", + 2614 => x"77", + 2615 => x"53", + 2616 => x"38", + 2617 => x"51", + 2618 => x"81", + 2619 => x"53", + 2620 => x"0b", + 2621 => x"08", + 2622 => x"38", + 2623 => x"de", + 2624 => x"2e", + 2625 => x"98", + 2626 => x"de", + 2627 => x"80", + 2628 => x"8a", + 2629 => x"15", + 2630 => x"80", + 2631 => x"14", + 2632 => x"51", + 2633 => x"81", + 2634 => x"53", + 2635 => x"de", + 2636 => x"2e", + 2637 => x"82", + 2638 => x"c0", + 2639 => x"ba", + 2640 => x"81", + 2641 => x"ff", + 2642 => x"81", + 2643 => x"52", + 2644 => x"f3", + 2645 => x"c0", + 2646 => x"72", + 2647 => x"72", + 2648 => x"f2", + 2649 => x"de", + 2650 => x"15", + 2651 => x"15", + 2652 => x"b4", + 2653 => x"0c", + 2654 => x"81", + 2655 => x"8a", + 2656 => x"f7", + 2657 => x"7d", + 2658 => x"5b", + 2659 => x"76", + 2660 => x"3f", + 2661 => x"08", + 2662 => x"c0", + 2663 => x"38", + 2664 => x"08", + 2665 => x"08", + 2666 => x"f0", + 2667 => x"de", + 2668 => x"81", + 2669 => x"80", + 2670 => x"de", + 2671 => x"18", + 2672 => x"51", + 2673 => x"81", + 2674 => x"81", + 2675 => x"81", + 2676 => x"c0", + 2677 => x"83", + 2678 => x"77", + 2679 => x"72", + 2680 => x"38", + 2681 => x"75", + 2682 => x"81", + 2683 => x"a5", + 2684 => x"c0", + 2685 => x"52", + 2686 => x"8e", + 2687 => x"c0", + 2688 => x"de", + 2689 => x"2e", + 2690 => x"73", + 2691 => x"81", + 2692 => x"87", + 2693 => x"de", + 2694 => x"3d", + 2695 => x"3d", + 2696 => x"11", + 2697 => x"ec", + 2698 => x"c0", + 2699 => x"ff", + 2700 => x"33", + 2701 => x"71", + 2702 => x"81", + 2703 => x"94", + 2704 => x"d0", + 2705 => x"c0", + 2706 => x"73", + 2707 => x"81", + 2708 => x"85", + 2709 => x"fc", + 2710 => x"79", + 2711 => x"ff", + 2712 => x"12", + 2713 => x"eb", + 2714 => x"70", + 2715 => x"72", + 2716 => x"81", + 2717 => x"73", + 2718 => x"94", + 2719 => x"d6", + 2720 => x"0d", + 2721 => x"0d", + 2722 => x"55", + 2723 => x"5a", + 2724 => x"08", + 2725 => x"8a", + 2726 => x"08", + 2727 => x"ee", + 2728 => x"de", + 2729 => x"81", + 2730 => x"80", + 2731 => x"15", + 2732 => x"55", + 2733 => x"38", + 2734 => x"e6", + 2735 => x"33", + 2736 => x"70", + 2737 => x"58", + 2738 => x"86", + 2739 => x"de", + 2740 => x"73", + 2741 => x"83", + 2742 => x"73", + 2743 => x"38", + 2744 => x"06", + 2745 => x"80", + 2746 => x"75", + 2747 => x"38", + 2748 => x"08", + 2749 => x"54", + 2750 => x"2e", + 2751 => x"83", + 2752 => x"73", + 2753 => x"38", + 2754 => x"51", + 2755 => x"81", + 2756 => x"58", + 2757 => x"08", + 2758 => x"15", + 2759 => x"38", + 2760 => x"0b", + 2761 => x"77", + 2762 => x"0c", + 2763 => x"04", + 2764 => x"77", + 2765 => x"54", + 2766 => x"51", + 2767 => x"81", + 2768 => x"55", + 2769 => x"08", + 2770 => x"14", + 2771 => x"51", + 2772 => x"81", + 2773 => x"55", + 2774 => x"08", + 2775 => x"53", + 2776 => x"08", + 2777 => x"08", + 2778 => x"3f", + 2779 => x"14", + 2780 => x"08", + 2781 => x"3f", + 2782 => x"17", + 2783 => x"de", + 2784 => x"3d", + 2785 => x"3d", + 2786 => x"08", + 2787 => x"54", + 2788 => x"53", + 2789 => x"81", + 2790 => x"8d", + 2791 => x"08", + 2792 => x"34", + 2793 => x"15", + 2794 => x"0d", + 2795 => x"0d", + 2796 => x"57", + 2797 => x"17", + 2798 => x"08", + 2799 => x"82", + 2800 => x"89", + 2801 => x"55", + 2802 => x"14", + 2803 => x"16", + 2804 => x"71", + 2805 => x"38", + 2806 => x"09", + 2807 => x"38", + 2808 => x"73", + 2809 => x"81", + 2810 => x"ae", + 2811 => x"05", + 2812 => x"15", + 2813 => x"70", + 2814 => x"34", + 2815 => x"8a", + 2816 => x"38", + 2817 => x"05", + 2818 => x"81", + 2819 => x"17", + 2820 => x"12", + 2821 => x"34", + 2822 => x"9c", + 2823 => x"e8", + 2824 => x"de", + 2825 => x"0c", + 2826 => x"e7", + 2827 => x"de", + 2828 => x"17", + 2829 => x"51", + 2830 => x"81", + 2831 => x"84", + 2832 => x"3d", + 2833 => x"3d", + 2834 => x"08", + 2835 => x"61", + 2836 => x"55", + 2837 => x"2e", + 2838 => x"55", + 2839 => x"2e", + 2840 => x"80", + 2841 => x"94", + 2842 => x"1c", + 2843 => x"81", + 2844 => x"61", + 2845 => x"56", + 2846 => x"2e", + 2847 => x"83", + 2848 => x"73", + 2849 => x"70", + 2850 => x"25", + 2851 => x"51", + 2852 => x"38", + 2853 => x"0c", + 2854 => x"51", + 2855 => x"26", + 2856 => x"80", + 2857 => x"34", + 2858 => x"51", + 2859 => x"81", + 2860 => x"55", + 2861 => x"91", + 2862 => x"1d", + 2863 => x"8b", + 2864 => x"79", + 2865 => x"3f", + 2866 => x"57", + 2867 => x"55", + 2868 => x"2e", + 2869 => x"80", + 2870 => x"18", + 2871 => x"1a", + 2872 => x"70", + 2873 => x"2a", + 2874 => x"07", + 2875 => x"5a", + 2876 => x"8c", + 2877 => x"54", + 2878 => x"81", + 2879 => x"39", + 2880 => x"70", + 2881 => x"2a", + 2882 => x"75", + 2883 => x"8c", + 2884 => x"2e", + 2885 => x"a0", + 2886 => x"38", + 2887 => x"0c", + 2888 => x"76", + 2889 => x"38", + 2890 => x"b8", + 2891 => x"70", + 2892 => x"5a", + 2893 => x"76", + 2894 => x"38", + 2895 => x"70", + 2896 => x"dc", + 2897 => x"72", + 2898 => x"80", + 2899 => x"51", + 2900 => x"73", + 2901 => x"38", + 2902 => x"18", + 2903 => x"1a", + 2904 => x"55", + 2905 => x"2e", + 2906 => x"83", + 2907 => x"73", + 2908 => x"70", + 2909 => x"25", + 2910 => x"51", + 2911 => x"38", + 2912 => x"75", + 2913 => x"81", + 2914 => x"81", + 2915 => x"27", + 2916 => x"73", + 2917 => x"38", + 2918 => x"70", + 2919 => x"32", + 2920 => x"80", + 2921 => x"2a", + 2922 => x"56", + 2923 => x"81", + 2924 => x"57", + 2925 => x"f5", + 2926 => x"2b", + 2927 => x"25", + 2928 => x"80", + 2929 => x"cd", + 2930 => x"57", + 2931 => x"e6", + 2932 => x"de", + 2933 => x"2e", + 2934 => x"18", + 2935 => x"1a", + 2936 => x"56", + 2937 => x"3f", + 2938 => x"08", + 2939 => x"e8", + 2940 => x"54", + 2941 => x"80", + 2942 => x"17", + 2943 => x"34", + 2944 => x"11", + 2945 => x"74", + 2946 => x"75", + 2947 => x"d4", + 2948 => x"3f", + 2949 => x"08", + 2950 => x"9f", + 2951 => x"99", + 2952 => x"e0", + 2953 => x"ff", + 2954 => x"79", + 2955 => x"74", + 2956 => x"57", + 2957 => x"77", + 2958 => x"76", + 2959 => x"38", + 2960 => x"73", + 2961 => x"09", + 2962 => x"38", + 2963 => x"84", + 2964 => x"27", + 2965 => x"39", + 2966 => x"f2", + 2967 => x"80", + 2968 => x"54", + 2969 => x"34", + 2970 => x"58", + 2971 => x"f2", + 2972 => x"de", + 2973 => x"81", + 2974 => x"80", + 2975 => x"1b", + 2976 => x"51", + 2977 => x"81", + 2978 => x"56", + 2979 => x"08", + 2980 => x"9c", + 2981 => x"33", + 2982 => x"80", + 2983 => x"38", + 2984 => x"bf", + 2985 => x"86", + 2986 => x"15", + 2987 => x"2a", + 2988 => x"51", + 2989 => x"92", + 2990 => x"79", + 2991 => x"e4", + 2992 => x"de", + 2993 => x"2e", + 2994 => x"52", + 2995 => x"ba", + 2996 => x"39", + 2997 => x"33", + 2998 => x"80", + 2999 => x"74", + 3000 => x"81", + 3001 => x"38", + 3002 => x"70", + 3003 => x"82", + 3004 => x"54", + 3005 => x"96", + 3006 => x"06", + 3007 => x"2e", + 3008 => x"ff", + 3009 => x"1c", + 3010 => x"80", + 3011 => x"81", + 3012 => x"ba", + 3013 => x"b6", + 3014 => x"2a", + 3015 => x"51", + 3016 => x"38", + 3017 => x"70", + 3018 => x"81", + 3019 => x"55", + 3020 => x"e1", + 3021 => x"08", + 3022 => x"1d", + 3023 => x"7c", + 3024 => x"3f", + 3025 => x"08", + 3026 => x"fa", + 3027 => x"81", + 3028 => x"8f", + 3029 => x"f6", + 3030 => x"5b", + 3031 => x"70", + 3032 => x"59", + 3033 => x"73", + 3034 => x"c6", + 3035 => x"81", + 3036 => x"70", + 3037 => x"52", + 3038 => x"8d", + 3039 => x"38", + 3040 => x"09", + 3041 => x"a5", + 3042 => x"d0", + 3043 => x"ff", + 3044 => x"53", + 3045 => x"91", + 3046 => x"73", + 3047 => x"d0", + 3048 => x"71", + 3049 => x"f7", + 3050 => x"81", + 3051 => x"55", + 3052 => x"55", + 3053 => x"81", + 3054 => x"74", + 3055 => x"56", + 3056 => x"12", + 3057 => x"70", + 3058 => x"38", + 3059 => x"81", + 3060 => x"51", + 3061 => x"51", + 3062 => x"89", + 3063 => x"70", + 3064 => x"53", + 3065 => x"70", + 3066 => x"51", + 3067 => x"09", + 3068 => x"38", + 3069 => x"38", + 3070 => x"77", + 3071 => x"70", + 3072 => x"2a", + 3073 => x"07", + 3074 => x"51", + 3075 => x"8f", + 3076 => x"84", + 3077 => x"83", + 3078 => x"94", + 3079 => x"74", + 3080 => x"38", + 3081 => x"0c", + 3082 => x"86", + 3083 => x"f0", + 3084 => x"81", + 3085 => x"8c", + 3086 => x"fa", + 3087 => x"56", + 3088 => x"17", + 3089 => x"b0", + 3090 => x"52", + 3091 => x"e0", + 3092 => x"81", + 3093 => x"81", + 3094 => x"b2", + 3095 => x"b4", + 3096 => x"c0", + 3097 => x"ff", + 3098 => x"55", + 3099 => x"d5", + 3100 => x"06", + 3101 => x"80", + 3102 => x"33", + 3103 => x"81", + 3104 => x"81", + 3105 => x"81", + 3106 => x"eb", + 3107 => x"70", + 3108 => x"07", + 3109 => x"73", + 3110 => x"81", + 3111 => x"81", + 3112 => x"83", + 3113 => x"e4", + 3114 => x"16", + 3115 => x"3f", + 3116 => x"08", + 3117 => x"c0", + 3118 => x"9d", + 3119 => x"81", + 3120 => x"81", + 3121 => x"e0", + 3122 => x"de", + 3123 => x"81", + 3124 => x"80", + 3125 => x"82", + 3126 => x"de", + 3127 => x"3d", + 3128 => x"3d", + 3129 => x"84", + 3130 => x"05", + 3131 => x"80", + 3132 => x"51", + 3133 => x"81", + 3134 => x"58", + 3135 => x"0b", + 3136 => x"08", + 3137 => x"38", + 3138 => x"08", + 3139 => x"de", + 3140 => x"08", + 3141 => x"56", + 3142 => x"86", + 3143 => x"75", + 3144 => x"fe", + 3145 => x"54", + 3146 => x"2e", + 3147 => x"14", + 3148 => x"ca", + 3149 => x"c0", + 3150 => x"06", + 3151 => x"54", + 3152 => x"38", + 3153 => x"86", + 3154 => x"82", + 3155 => x"06", + 3156 => x"56", + 3157 => x"38", + 3158 => x"80", + 3159 => x"81", + 3160 => x"52", + 3161 => x"51", + 3162 => x"81", + 3163 => x"81", + 3164 => x"81", + 3165 => x"83", + 3166 => x"87", + 3167 => x"2e", + 3168 => x"82", + 3169 => x"06", + 3170 => x"56", + 3171 => x"38", + 3172 => x"74", + 3173 => x"a3", + 3174 => x"c0", + 3175 => x"06", + 3176 => x"2e", + 3177 => x"80", + 3178 => x"3d", + 3179 => x"83", + 3180 => x"15", + 3181 => x"53", + 3182 => x"8d", + 3183 => x"15", + 3184 => x"3f", + 3185 => x"08", + 3186 => x"70", + 3187 => x"0c", + 3188 => x"16", + 3189 => x"80", + 3190 => x"80", + 3191 => x"54", + 3192 => x"84", + 3193 => x"5b", + 3194 => x"80", + 3195 => x"7a", + 3196 => x"fc", + 3197 => x"de", + 3198 => x"ff", + 3199 => x"77", + 3200 => x"81", + 3201 => x"76", + 3202 => x"81", + 3203 => x"2e", + 3204 => x"8d", + 3205 => x"26", + 3206 => x"bf", + 3207 => x"f4", + 3208 => x"c0", + 3209 => x"ff", + 3210 => x"84", + 3211 => x"81", + 3212 => x"38", + 3213 => x"51", + 3214 => x"81", + 3215 => x"83", + 3216 => x"58", + 3217 => x"80", + 3218 => x"db", + 3219 => x"de", + 3220 => x"77", + 3221 => x"80", + 3222 => x"82", + 3223 => x"c4", + 3224 => x"11", + 3225 => x"06", + 3226 => x"8d", + 3227 => x"26", + 3228 => x"74", + 3229 => x"78", + 3230 => x"c1", + 3231 => x"59", + 3232 => x"15", + 3233 => x"2e", + 3234 => x"13", + 3235 => x"72", + 3236 => x"38", + 3237 => x"eb", + 3238 => x"14", + 3239 => x"3f", + 3240 => x"08", + 3241 => x"c0", + 3242 => x"23", + 3243 => x"57", + 3244 => x"83", + 3245 => x"c7", + 3246 => x"d8", + 3247 => x"c0", + 3248 => x"ff", + 3249 => x"8d", + 3250 => x"14", + 3251 => x"3f", + 3252 => x"08", + 3253 => x"14", + 3254 => x"3f", + 3255 => x"08", + 3256 => x"06", + 3257 => x"72", + 3258 => x"97", + 3259 => x"22", + 3260 => x"84", + 3261 => x"5a", + 3262 => x"83", + 3263 => x"14", + 3264 => x"79", + 3265 => x"ac", + 3266 => x"de", + 3267 => x"81", + 3268 => x"80", + 3269 => x"38", + 3270 => x"08", + 3271 => x"ff", + 3272 => x"38", + 3273 => x"83", + 3274 => x"83", + 3275 => x"74", + 3276 => x"85", + 3277 => x"89", + 3278 => x"76", + 3279 => x"c3", + 3280 => x"70", + 3281 => x"7b", + 3282 => x"73", + 3283 => x"17", + 3284 => x"ac", + 3285 => x"55", + 3286 => x"09", + 3287 => x"38", + 3288 => x"51", + 3289 => x"81", + 3290 => x"83", + 3291 => x"53", + 3292 => x"82", + 3293 => x"82", + 3294 => x"e0", + 3295 => x"ab", + 3296 => x"c0", + 3297 => x"0c", + 3298 => x"53", + 3299 => x"56", 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x"23", + 3359 => x"15", + 3360 => x"75", + 3361 => x"0c", + 3362 => x"04", + 3363 => x"77", + 3364 => x"73", + 3365 => x"38", + 3366 => x"72", + 3367 => x"38", + 3368 => x"71", + 3369 => x"38", + 3370 => x"84", + 3371 => x"52", + 3372 => x"09", + 3373 => x"38", + 3374 => x"51", + 3375 => x"81", + 3376 => x"81", + 3377 => x"88", + 3378 => x"08", + 3379 => x"39", + 3380 => x"73", + 3381 => x"74", + 3382 => x"0c", + 3383 => x"04", + 3384 => x"02", + 3385 => x"7a", + 3386 => x"fc", + 3387 => x"f4", + 3388 => x"54", + 3389 => x"de", + 3390 => x"bc", + 3391 => x"c0", + 3392 => x"81", + 3393 => x"70", + 3394 => x"73", + 3395 => x"38", + 3396 => x"78", + 3397 => x"2e", + 3398 => x"74", + 3399 => x"0c", + 3400 => x"80", + 3401 => x"80", + 3402 => x"70", + 3403 => x"51", + 3404 => x"81", + 3405 => x"54", + 3406 => x"c0", + 3407 => x"0d", + 3408 => x"0d", + 3409 => x"05", + 3410 => x"33", + 3411 => x"54", + 3412 => x"84", + 3413 => x"bf", + 3414 => x"98", + 3415 => x"53", + 3416 => x"05", + 3417 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=> x"39", + 4123 => x"84", + 4124 => x"0c", + 4125 => x"81", + 4126 => x"89", + 4127 => x"fc", + 4128 => x"87", + 4129 => x"53", + 4130 => x"e7", + 4131 => x"de", + 4132 => x"38", + 4133 => x"08", + 4134 => x"3d", + 4135 => x"3d", + 4136 => x"89", + 4137 => x"54", + 4138 => x"54", + 4139 => x"81", + 4140 => x"53", + 4141 => x"08", + 4142 => x"74", + 4143 => x"de", + 4144 => x"73", + 4145 => x"3f", + 4146 => x"08", + 4147 => x"39", + 4148 => x"08", + 4149 => x"d3", + 4150 => x"de", + 4151 => x"81", + 4152 => x"84", + 4153 => x"06", + 4154 => x"53", + 4155 => x"de", + 4156 => x"38", + 4157 => x"51", + 4158 => x"72", + 4159 => x"cf", + 4160 => x"de", + 4161 => x"32", + 4162 => x"72", + 4163 => x"70", + 4164 => x"08", + 4165 => x"54", + 4166 => x"de", + 4167 => x"3d", + 4168 => x"3d", + 4169 => x"80", + 4170 => x"70", + 4171 => x"52", + 4172 => x"3f", + 4173 => x"08", + 4174 => x"c0", + 4175 => x"64", + 4176 => x"d6", + 4177 => x"de", + 4178 => x"81", + 4179 => x"a0", + 4180 => x"cb", + 4181 => x"98", + 4182 => x"73", + 4183 => x"38", + 4184 => x"39", + 4185 => x"88", + 4186 => x"75", + 4187 => x"3f", + 4188 => x"c0", + 4189 => x"0d", + 4190 => x"0d", + 4191 => x"5c", + 4192 => x"3d", + 4193 => x"93", + 4194 => x"d6", + 4195 => x"c0", + 4196 => x"de", + 4197 => x"80", + 4198 => x"0c", + 4199 => x"11", + 4200 => x"90", + 4201 => x"56", + 4202 => x"74", + 4203 => x"75", + 4204 => x"e4", + 4205 => x"81", + 4206 => x"5b", + 4207 => x"81", + 4208 => x"75", + 4209 => x"73", + 4210 => x"81", + 4211 => x"82", + 4212 => x"76", + 4213 => x"f0", + 4214 => x"f4", + 4215 => x"c0", + 4216 => x"d1", + 4217 => x"c0", + 4218 => x"ce", + 4219 => x"c0", + 4220 => x"81", + 4221 => x"07", + 4222 => x"05", + 4223 => x"53", + 4224 => x"98", + 4225 => x"26", + 4226 => x"f9", + 4227 => x"08", + 4228 => x"08", + 4229 => x"98", + 4230 => x"81", + 4231 => x"58", + 4232 => x"3f", + 4233 => x"08", + 4234 => x"c0", + 4235 => x"38", + 4236 => x"77", + 4237 => x"5d", + 4238 => x"74", + 4239 => x"81", + 4240 => x"b4", + 4241 => x"bb", + 4242 => x"de", + 4243 => x"ff", + 4244 => x"30", + 4245 => x"1b", + 4246 => x"5b", + 4247 => x"39", + 4248 => x"ff", + 4249 => x"81", + 4250 => x"f0", + 4251 => x"30", + 4252 => x"1b", + 4253 => x"5b", + 4254 => x"83", + 4255 => x"58", + 4256 => x"92", + 4257 => x"0c", + 4258 => x"12", + 4259 => x"33", + 4260 => x"54", + 4261 => x"34", + 4262 => x"c0", + 4263 => x"0d", + 4264 => x"0d", + 4265 => x"fc", + 4266 => x"52", + 4267 => x"3f", + 4268 => x"08", + 4269 => x"c0", + 4270 => x"38", + 4271 => x"56", + 4272 => x"38", + 4273 => x"70", + 4274 => x"81", + 4275 => x"55", + 4276 => x"80", + 4277 => x"38", + 4278 => x"54", + 4279 => x"08", + 4280 => x"38", + 4281 => x"81", + 4282 => x"53", + 4283 => x"52", + 4284 => x"8c", + 4285 => x"c0", + 4286 => x"19", + 4287 => x"c9", + 4288 => x"08", + 4289 => x"ff", + 4290 => x"81", + 4291 => x"ff", + 4292 => x"06", + 4293 => x"56", + 4294 => x"08", + 4295 => x"81", + 4296 => x"82", + 4297 => x"75", + 4298 => x"54", + 4299 => x"08", + 4300 => x"27", + 4301 => x"17", + 4302 => x"de", + 4303 => x"76", + 4304 => x"3f", + 4305 => x"08", + 4306 => x"08", + 4307 => x"90", + 4308 => x"c0", + 4309 => x"90", + 4310 => x"80", + 4311 => x"75", + 4312 => x"75", + 4313 => x"de", + 4314 => x"3d", + 4315 => x"3d", + 4316 => x"a0", + 4317 => x"05", + 4318 => x"51", + 4319 => x"81", + 4320 => x"55", + 4321 => x"08", + 4322 => x"78", + 4323 => x"08", + 4324 => x"70", + 4325 => x"ae", + 4326 => x"c0", + 4327 => x"de", + 4328 => x"db", + 4329 => x"fb", + 4330 => x"85", + 4331 => x"06", + 4332 => x"86", + 4333 => x"c7", + 4334 => x"2b", + 4335 => x"24", + 4336 => x"02", + 4337 => x"33", + 4338 => x"58", + 4339 => x"76", + 4340 => x"6b", + 4341 => x"cc", + 4342 => x"de", + 4343 => x"84", + 4344 => x"06", + 4345 => x"73", + 4346 => x"d4", + 4347 => x"81", + 4348 => x"94", + 4349 => x"81", + 4350 => x"5a", + 4351 => x"08", + 4352 => x"8a", + 4353 => x"54", + 4354 => x"81", + 4355 => x"55", + 4356 => x"08", + 4357 => x"81", + 4358 => x"52", + 4359 => x"e5", + 4360 => x"c0", + 4361 => x"de", + 4362 => x"38", + 4363 => x"cf", + 4364 => x"c0", + 4365 => x"88", + 4366 => x"c0", + 4367 => x"38", + 4368 => x"c2", + 4369 => x"c0", + 4370 => x"c0", + 4371 => x"81", + 4372 => x"07", + 4373 => x"55", + 4374 => x"2e", + 4375 => x"80", + 4376 => x"80", + 4377 => x"77", + 4378 => x"3f", + 4379 => x"08", + 4380 => x"38", + 4381 => x"ba", + 4382 => x"de", + 4383 => x"74", + 4384 => x"0c", + 4385 => x"04", + 4386 => x"82", + 4387 => x"c0", + 4388 => x"3d", + 4389 => x"3f", + 4390 => x"08", + 4391 => x"c0", + 4392 => x"38", + 4393 => x"52", + 4394 => x"52", + 4395 => x"3f", + 4396 => x"08", + 4397 => x"c0", + 4398 => x"88", + 4399 => x"39", + 4400 => x"08", + 4401 => x"81", + 4402 => x"38", + 4403 => x"05", + 4404 => x"2a", + 4405 => x"55", + 4406 => x"81", + 4407 => x"5a", + 4408 => x"3d", + 4409 => x"c1", + 4410 => x"de", + 4411 => x"55", + 4412 => x"c0", + 4413 => x"87", + 4414 => x"c0", + 4415 => x"09", + 4416 => x"38", + 4417 => x"de", + 4418 => x"2e", + 4419 => x"86", + 4420 => x"81", + 4421 => x"81", + 4422 => x"de", + 4423 => x"78", + 4424 => x"3f", + 4425 => x"08", + 4426 => x"c0", + 4427 => x"38", + 4428 => x"52", + 4429 => x"ff", + 4430 => x"78", + 4431 => x"b4", + 4432 => x"54", + 4433 => x"15", + 4434 => x"b2", + 4435 => x"ca", + 4436 => x"b6", + 4437 => x"53", + 4438 => x"53", + 4439 => x"3f", + 4440 => x"b4", + 4441 => x"d4", + 4442 => x"b6", + 4443 => x"54", + 4444 => x"d5", + 4445 => x"53", + 4446 => x"11", + 4447 => x"d7", + 4448 => x"81", + 4449 => x"34", + 4450 => x"a4", + 4451 => x"c0", + 4452 => x"de", + 4453 => x"38", + 4454 => x"0a", + 4455 => x"05", + 4456 => x"d0", + 4457 => x"64", + 4458 => x"c9", + 4459 => x"54", + 4460 => x"15", + 4461 => x"81", + 4462 => x"34", + 4463 => x"b8", + 4464 => x"de", + 4465 => x"8b", + 4466 => x"75", + 4467 => x"ff", + 4468 => x"73", + 4469 => x"0c", + 4470 => x"04", + 4471 => x"a9", + 4472 => x"51", + 4473 => x"82", + 4474 => x"ff", + 4475 => x"a9", + 4476 => x"ee", + 4477 => x"c0", + 4478 => x"de", + 4479 => x"d3", + 4480 => x"a9", + 4481 => x"9d", + 4482 => x"58", + 4483 => x"81", + 4484 => x"55", + 4485 => x"08", + 4486 => x"02", + 4487 => x"33", + 4488 => x"54", + 4489 => x"82", + 4490 => x"53", + 4491 => x"52", + 4492 => x"88", + 4493 => x"b4", + 4494 => x"53", + 4495 => x"3d", + 4496 => x"ff", + 4497 => x"aa", + 4498 => x"73", + 4499 => x"3f", + 4500 => x"08", + 4501 => x"c0", + 4502 => x"63", + 4503 => x"81", + 4504 => x"65", + 4505 => x"2e", + 4506 => x"55", + 4507 => x"81", + 4508 => x"84", + 4509 => x"06", + 4510 => x"73", + 4511 => x"3f", + 4512 => x"08", + 4513 => x"c0", + 4514 => x"38", + 4515 => x"53", + 4516 => x"95", + 4517 => x"16", + 4518 => x"87", + 4519 => x"05", + 4520 => x"34", + 4521 => x"70", + 4522 => x"81", + 4523 => x"55", + 4524 => x"74", + 4525 => x"73", + 4526 => x"78", + 4527 => x"83", + 4528 => x"16", + 4529 => x"2a", + 4530 => x"51", + 4531 => x"80", + 4532 => x"38", + 4533 => x"80", + 4534 => x"52", + 4535 => x"be", + 4536 => x"c0", + 4537 => x"51", + 4538 => x"3f", + 4539 => x"de", + 4540 => x"2e", + 4541 => x"81", + 4542 => x"52", + 4543 => x"b5", + 4544 => x"de", + 4545 => x"80", + 4546 => x"58", + 4547 => x"c0", + 4548 => x"38", + 4549 => x"54", + 4550 => x"09", + 4551 => x"38", + 4552 => x"52", + 4553 => x"af", + 4554 => x"81", + 4555 => x"34", + 4556 => x"de", + 4557 => x"38", + 4558 => x"ca", + 4559 => x"c0", + 4560 => x"de", + 4561 => x"38", + 4562 => x"b5", + 4563 => x"de", + 4564 => x"74", + 4565 => x"0c", + 4566 => x"04", + 4567 => x"02", + 4568 => x"33", + 4569 => x"80", + 4570 => x"57", + 4571 => x"95", + 4572 => x"52", + 4573 => x"d2", + 4574 => x"de", + 4575 => x"81", + 4576 => x"80", + 4577 => x"5a", + 4578 => x"3d", + 4579 => x"c9", + 4580 => x"de", + 4581 => x"81", + 4582 => x"b8", + 4583 => x"cf", + 4584 => x"a0", + 4585 => x"55", + 4586 => x"75", + 4587 => x"71", + 4588 => x"33", + 4589 => x"74", + 4590 => x"57", + 4591 => x"8b", + 4592 => x"54", + 4593 => x"15", + 4594 => x"ff", + 4595 => x"81", + 4596 => x"55", + 4597 => x"c0", + 4598 => x"0d", + 4599 => x"0d", + 4600 => x"53", + 4601 => x"05", + 4602 => x"51", + 4603 => x"81", + 4604 => x"55", + 4605 => x"08", + 4606 => x"76", + 4607 => x"93", + 4608 => x"51", + 4609 => x"81", + 4610 => x"55", + 4611 => x"08", + 4612 => x"80", + 4613 => x"81", + 4614 => x"86", + 4615 => x"38", + 4616 => x"86", + 4617 => x"90", + 4618 => x"54", + 4619 => x"ff", + 4620 => x"76", + 4621 => x"83", + 4622 => x"51", + 4623 => x"3f", + 4624 => x"08", + 4625 => x"de", + 4626 => x"3d", + 4627 => x"3d", + 4628 => x"5c", + 4629 => x"98", + 4630 => x"52", + 4631 => x"d1", + 4632 => x"de", + 4633 => x"de", + 4634 => x"70", + 4635 => x"08", + 4636 => x"51", + 4637 => x"80", + 4638 => x"38", + 4639 => x"06", + 4640 => x"80", + 4641 => x"38", + 4642 => x"5f", + 4643 => x"3d", + 4644 => x"ff", + 4645 => x"81", + 4646 => x"57", + 4647 => x"08", + 4648 => x"74", + 4649 => x"c3", + 4650 => x"de", + 4651 => x"81", + 4652 => x"bf", + 4653 => x"c0", + 4654 => x"c0", + 4655 => x"59", + 4656 => x"81", + 4657 => x"56", + 4658 => x"33", + 4659 => x"16", + 4660 => x"27", + 4661 => x"56", + 4662 => x"80", + 4663 => x"80", + 4664 => x"ff", + 4665 => x"70", + 4666 => x"56", + 4667 => x"e8", + 4668 => x"76", + 4669 => x"81", + 4670 => x"80", + 4671 => x"57", + 4672 => x"78", + 4673 => x"51", + 4674 => x"2e", + 4675 => x"73", + 4676 => x"38", + 4677 => x"08", + 4678 => x"b1", + 4679 => x"de", + 4680 => x"81", + 4681 => x"a7", + 4682 => x"33", + 4683 => x"c3", + 4684 => x"2e", + 4685 => x"e4", + 4686 => x"2e", + 4687 => x"56", + 4688 => x"05", + 4689 => x"e3", + 4690 => x"c0", + 4691 => x"76", + 4692 => x"0c", + 4693 => x"04", + 4694 => x"82", + 4695 => x"ff", + 4696 => x"9d", + 4697 => x"fa", + 4698 => x"c0", + 4699 => x"c0", + 4700 => x"81", + 4701 => x"83", + 4702 => x"53", + 4703 => x"3d", + 4704 => x"ff", + 4705 => x"73", + 4706 => x"70", + 4707 => x"52", + 4708 => x"9f", + 4709 => x"bc", + 4710 => x"74", + 4711 => x"6d", + 4712 => x"70", + 4713 => x"af", + 4714 => x"de", + 4715 => x"2e", + 4716 => x"70", + 4717 => x"57", + 4718 => x"fd", + 4719 => x"c0", + 4720 => x"8d", + 4721 => x"2b", + 4722 => x"81", + 4723 => x"86", + 4724 => x"c0", + 4725 => x"9f", + 4726 => x"ff", + 4727 => x"54", + 4728 => x"8a", + 4729 => x"70", + 4730 => x"06", + 4731 => x"ff", + 4732 => x"38", + 4733 => x"15", + 4734 => x"80", + 4735 => x"74", + 4736 => x"b4", + 4737 => x"89", + 4738 => x"c0", + 4739 => x"81", + 4740 => x"88", + 4741 => x"26", + 4742 => x"39", + 4743 => x"86", + 4744 => x"81", + 4745 => x"ff", + 4746 => x"38", + 4747 => x"54", + 4748 => x"81", + 4749 => x"81", + 4750 => x"78", + 4751 => x"5a", + 4752 => x"6d", + 4753 => x"81", + 4754 => x"57", + 4755 => x"9f", + 4756 => x"38", + 4757 => x"54", + 4758 => x"81", + 4759 => x"b1", + 4760 => x"2e", + 4761 => x"a7", + 4762 => x"15", + 4763 => x"54", + 4764 => x"09", + 4765 => x"38", + 4766 => x"76", + 4767 => x"41", + 4768 => x"52", + 4769 => x"52", + 4770 => x"b3", + 4771 => x"c0", + 4772 => x"de", + 4773 => x"f7", + 4774 => x"74", + 4775 => x"e5", + 4776 => x"c0", + 4777 => x"de", + 4778 => x"38", + 4779 => x"38", + 4780 => x"74", + 4781 => x"39", + 4782 => x"08", + 4783 => x"81", + 4784 => x"38", + 4785 => x"74", + 4786 => x"38", + 4787 => x"51", + 4788 => x"3f", + 4789 => x"08", + 4790 => x"c0", + 4791 => x"a0", + 4792 => x"c0", + 4793 => x"51", + 4794 => x"3f", + 4795 => x"0b", + 4796 => x"8b", + 4797 => x"67", + 4798 => x"a7", + 4799 => x"81", + 4800 => x"34", + 4801 => x"ad", + 4802 => x"de", + 4803 => x"73", + 4804 => x"de", + 4805 => x"3d", + 4806 => x"3d", + 4807 => x"02", + 4808 => x"cb", + 4809 => x"3d", + 4810 => x"72", + 4811 => x"5a", + 4812 => x"81", + 4813 => x"58", + 4814 => x"08", + 4815 => x"91", + 4816 => x"77", + 4817 => x"7c", + 4818 => x"38", + 4819 => x"59", + 4820 => x"90", + 4821 => x"81", + 4822 => x"06", + 4823 => x"73", + 4824 => x"54", + 4825 => x"82", + 4826 => x"39", + 4827 => x"8b", + 4828 => x"11", + 4829 => x"2b", + 4830 => x"54", + 4831 => x"fe", + 4832 => x"ff", + 4833 => x"70", + 4834 => x"07", + 4835 => x"de", + 4836 => x"8c", + 4837 => x"40", + 4838 => x"55", + 4839 => x"88", + 4840 => x"08", + 4841 => x"38", + 4842 => x"77", + 4843 => x"56", + 4844 => x"51", + 4845 => x"3f", + 4846 => x"55", + 4847 => x"08", + 4848 => x"38", + 4849 => x"de", + 4850 => x"2e", + 4851 => x"81", + 4852 => x"ff", + 4853 => x"38", + 4854 => x"08", + 4855 => x"16", + 4856 => x"2e", + 4857 => x"87", + 4858 => x"74", + 4859 => x"74", + 4860 => x"81", + 4861 => x"38", + 4862 => x"ff", + 4863 => x"2e", + 4864 => x"7b", + 4865 => x"80", + 4866 => x"81", + 4867 => x"81", + 4868 => x"06", + 4869 => x"56", + 4870 => x"52", + 4871 => x"af", + 4872 => x"de", + 4873 => x"81", + 4874 => x"80", + 4875 => x"81", + 4876 => x"56", + 4877 => x"d3", + 4878 => x"ff", + 4879 => x"7c", + 4880 => x"55", + 4881 => x"b3", + 4882 => x"1b", + 4883 => x"1b", + 4884 => x"33", + 4885 => x"54", + 4886 => x"34", + 4887 => x"fe", + 4888 => x"08", + 4889 => x"74", + 4890 => x"75", + 4891 => x"16", + 4892 => x"33", + 4893 => x"73", + 4894 => x"77", + 4895 => x"de", + 4896 => x"3d", + 4897 => x"3d", + 4898 => x"02", + 4899 => x"eb", + 4900 => x"3d", + 4901 => x"59", + 4902 => x"8b", + 4903 => x"81", + 4904 => x"24", + 4905 => x"81", + 4906 => x"84", + 4907 => x"dc", + 4908 => x"51", + 4909 => x"2e", + 4910 => x"75", + 4911 => x"c0", + 4912 => x"06", + 4913 => x"7e", + 4914 => x"d0", + 4915 => x"c0", + 4916 => x"06", + 4917 => x"56", + 4918 => x"74", + 4919 => x"76", + 4920 => x"81", + 4921 => x"8a", + 4922 => x"b2", + 4923 => x"fc", + 4924 => x"52", + 4925 => x"a4", + 4926 => x"de", + 4927 => x"38", + 4928 => x"80", + 4929 => x"74", + 4930 => x"26", + 4931 => x"15", + 4932 => x"74", + 4933 => x"38", + 4934 => x"80", + 4935 => x"84", + 4936 => x"92", + 4937 => x"80", + 4938 => x"38", + 4939 => x"06", + 4940 => x"2e", + 4941 => x"56", + 4942 => x"78", + 4943 => x"89", + 4944 => x"2b", + 4945 => x"43", + 4946 => x"38", + 4947 => x"30", + 4948 => x"77", + 4949 => x"91", + 4950 => x"c2", + 4951 => x"f8", + 4952 => x"52", + 4953 => x"a4", + 4954 => x"56", + 4955 => x"08", + 4956 => x"77", + 4957 => x"77", + 4958 => x"c0", + 4959 => x"45", + 4960 => x"bf", + 4961 => x"8e", + 4962 => x"26", + 4963 => x"74", + 4964 => x"48", + 4965 => x"75", + 4966 => x"38", + 4967 => x"81", + 4968 => x"fa", + 4969 => x"2a", + 4970 => x"56", + 4971 => x"2e", + 4972 => x"87", + 4973 => x"82", + 4974 => x"38", + 4975 => x"55", + 4976 => x"83", + 4977 => x"81", + 4978 => x"56", + 4979 => x"80", + 4980 => x"38", + 4981 => x"83", + 4982 => x"06", + 4983 => x"78", + 4984 => x"91", + 4985 => x"0b", + 4986 => x"22", + 4987 => x"80", + 4988 => x"74", + 4989 => x"38", + 4990 => x"56", + 4991 => x"17", + 4992 => x"57", + 4993 => x"2e", + 4994 => x"75", + 4995 => x"79", + 4996 => x"fe", + 4997 => x"81", + 4998 => x"84", + 4999 => x"05", + 5000 => x"5e", + 5001 => x"80", + 5002 => x"c0", + 5003 => x"8a", + 5004 => x"fd", + 5005 => x"75", + 5006 => x"38", + 5007 => x"78", + 5008 => x"8c", + 5009 => x"0b", + 5010 => x"22", + 5011 => x"80", + 5012 => x"74", + 5013 => x"38", + 5014 => x"56", + 5015 => x"17", + 5016 => x"57", + 5017 => x"2e", + 5018 => x"75", + 5019 => x"79", + 5020 => x"fe", + 5021 => x"81", + 5022 => x"10", + 5023 => x"81", + 5024 => x"9f", + 5025 => x"38", + 5026 => x"de", + 5027 => x"81", + 5028 => x"05", + 5029 => x"2a", + 5030 => x"56", + 5031 => x"17", + 5032 => x"81", + 5033 => x"60", + 5034 => x"65", + 5035 => x"12", + 5036 => x"30", + 5037 => x"74", + 5038 => x"59", + 5039 => x"7d", + 5040 => x"81", + 5041 => x"76", + 5042 => x"41", + 5043 => x"76", + 5044 => x"90", + 5045 => x"62", + 5046 => x"51", + 5047 => x"26", + 5048 => x"75", + 5049 => x"31", + 5050 => x"65", + 5051 => x"fe", + 5052 => x"81", + 5053 => x"58", + 5054 => x"09", + 5055 => x"38", + 5056 => x"08", + 5057 => x"26", + 5058 => x"78", + 5059 => x"79", + 5060 => x"78", + 5061 => x"86", + 5062 => x"82", + 5063 => x"06", + 5064 => x"83", + 5065 => x"81", + 5066 => x"27", + 5067 => x"8f", + 5068 => x"55", + 5069 => x"26", + 5070 => x"59", + 5071 => x"62", + 5072 => x"74", + 5073 => x"38", + 5074 => x"88", + 5075 => x"c0", + 5076 => x"26", + 5077 => x"86", + 5078 => x"1a", + 5079 => x"79", + 5080 => x"38", + 5081 => x"80", + 5082 => x"2e", + 5083 => x"83", + 5084 => x"9f", + 5085 => x"8b", + 5086 => x"06", + 5087 => x"74", + 5088 => x"84", + 5089 => x"52", + 5090 => x"a2", + 5091 => x"53", + 5092 => x"52", + 5093 => x"a2", + 5094 => x"80", + 5095 => x"51", + 5096 => x"3f", + 5097 => x"34", + 5098 => x"ff", + 5099 => x"1b", + 5100 => x"a2", + 5101 => x"90", + 5102 => x"83", + 5103 => x"70", + 5104 => x"80", + 5105 => x"55", + 5106 => x"ff", + 5107 => x"66", + 5108 => x"ff", + 5109 => x"38", + 5110 => x"ff", + 5111 => x"1b", + 5112 => x"f2", + 5113 => x"74", + 5114 => x"51", + 5115 => x"3f", + 5116 => x"1c", + 5117 => x"98", + 5118 => x"a0", + 5119 => x"ff", + 5120 => x"51", + 5121 => x"3f", + 5122 => x"1b", + 5123 => x"e4", + 5124 => x"2e", + 5125 => x"80", + 5126 => x"88", + 5127 => x"80", + 5128 => x"ff", + 5129 => x"7c", + 5130 => x"51", + 5131 => x"3f", + 5132 => x"1b", + 5133 => x"bc", + 5134 => x"b0", + 5135 => x"a0", + 5136 => x"52", + 5137 => x"ff", + 5138 => x"ff", + 5139 => x"c0", + 5140 => x"0b", + 5141 => x"34", + 5142 => x"cc", + 5143 => x"c7", + 5144 => x"39", + 5145 => x"0a", + 5146 => x"51", + 5147 => x"3f", + 5148 => x"ff", + 5149 => x"1b", + 5150 => x"da", + 5151 => x"0b", + 5152 => x"a9", + 5153 => x"34", + 5154 => x"cd", + 5155 => x"1b", + 5156 => x"8f", + 5157 => x"d5", + 5158 => x"1b", + 5159 => x"ff", + 5160 => x"81", + 5161 => x"7a", + 5162 => x"ff", + 5163 => x"81", + 5164 => x"c0", + 5165 => x"38", + 5166 => x"09", + 5167 => x"ee", + 5168 => x"60", + 5169 => x"7a", + 5170 => x"ff", + 5171 => x"84", + 5172 => x"52", + 5173 => x"9f", + 5174 => x"8b", + 5175 => x"52", + 5176 => x"9f", + 5177 => x"8a", + 5178 => x"52", + 5179 => x"51", + 5180 => x"3f", + 5181 => x"83", + 5182 => x"ff", + 5183 => x"82", + 5184 => x"1b", + 5185 => x"ec", + 5186 => x"d5", + 5187 => x"ff", + 5188 => x"75", + 5189 => x"05", + 5190 => x"7e", + 5191 => x"e5", + 5192 => x"60", + 5193 => x"52", + 5194 => x"9a", + 5195 => x"53", + 5196 => x"51", + 5197 => x"3f", + 5198 => x"58", + 5199 => x"09", + 5200 => x"38", + 5201 => x"51", + 5202 => x"3f", + 5203 => x"1b", + 5204 => x"a0", + 5205 => x"52", + 5206 => x"91", + 5207 => x"ff", + 5208 => x"81", + 5209 => x"f8", + 5210 => x"7a", + 5211 => x"84", + 5212 => x"61", + 5213 => x"26", + 5214 => x"57", + 5215 => x"53", + 5216 => x"51", + 5217 => x"3f", + 5218 => x"08", + 5219 => x"84", + 5220 => x"de", + 5221 => x"7a", + 5222 => x"aa", + 5223 => x"75", + 5224 => x"56", + 5225 => x"81", + 5226 => x"80", + 5227 => x"38", + 5228 => x"83", + 5229 => x"63", + 5230 => x"74", + 5231 => x"38", + 5232 => x"54", + 5233 => x"52", + 5234 => x"99", + 5235 => x"de", + 5236 => x"c1", + 5237 => x"75", + 5238 => x"56", + 5239 => x"8c", + 5240 => x"2e", + 5241 => x"56", + 5242 => x"ff", + 5243 => x"84", + 5244 => x"2e", + 5245 => x"56", + 5246 => x"58", + 5247 => x"38", + 5248 => x"77", + 5249 => x"ff", + 5250 => x"82", + 5251 => x"78", + 5252 => x"c2", + 5253 => x"1b", + 5254 => x"34", + 5255 => x"16", + 5256 => x"82", + 5257 => x"83", + 5258 => x"84", + 5259 => x"67", + 5260 => x"fd", + 5261 => x"51", + 5262 => x"3f", + 5263 => x"16", + 5264 => x"c0", + 5265 => x"bf", + 5266 => x"86", + 5267 => x"de", + 5268 => x"16", + 5269 => x"83", + 5270 => x"ff", + 5271 => x"66", + 5272 => x"1b", + 5273 => x"8c", + 5274 => x"77", + 5275 => x"7e", + 5276 => x"91", + 5277 => x"81", + 5278 => x"a2", + 5279 => x"80", + 5280 => x"ff", + 5281 => x"81", + 5282 => x"c0", + 5283 => x"89", + 5284 => x"8a", + 5285 => x"86", + 5286 => x"c0", + 5287 => x"81", + 5288 => x"99", + 5289 => x"f5", + 5290 => x"60", + 5291 => x"79", + 5292 => x"5a", + 5293 => x"78", + 5294 => x"8d", + 5295 => x"55", + 5296 => x"fc", + 5297 => x"51", + 5298 => x"7a", + 5299 => x"81", + 5300 => x"8c", + 5301 => x"74", + 5302 => x"38", + 5303 => x"81", + 5304 => x"81", + 5305 => x"8a", + 5306 => x"06", + 5307 => x"76", + 5308 => x"76", + 5309 => x"55", + 5310 => x"c0", + 5311 => x"0d", + 5312 => x"0d", + 5313 => x"93", + 5314 => x"38", + 5315 => x"81", + 5316 => x"52", + 5317 => x"81", + 5318 => x"81", + 5319 => x"cf", + 5320 => x"f9", + 5321 => x"90", + 5322 => x"39", + 5323 => x"51", + 5324 => x"81", + 5325 => x"80", + 5326 => x"d0", + 5327 => x"dd", + 5328 => x"d8", + 5329 => x"39", + 5330 => x"51", + 5331 => x"81", + 5332 => x"80", + 5333 => x"d1", + 5334 => x"c1", + 5335 => x"b0", + 5336 => x"81", + 5337 => x"b5", + 5338 => x"e0", + 5339 => x"81", + 5340 => x"a9", + 5341 => x"a0", + 5342 => x"81", + 5343 => x"9d", + 5344 => x"d4", + 5345 => x"81", + 5346 => x"91", + 5347 => x"84", + 5348 => x"81", + 5349 => x"85", + 5350 => x"a8", + 5351 => x"a1", + 5352 => x"0d", + 5353 => x"0d", + 5354 => x"56", + 5355 => x"26", + 5356 => x"52", + 5357 => x"29", + 5358 => x"87", + 5359 => x"51", + 5360 => x"3f", + 5361 => x"08", + 5362 => x"fe", + 5363 => x"81", + 5364 => x"54", + 5365 => x"52", + 5366 => x"51", + 5367 => x"3f", + 5368 => x"04", + 5369 => x"7d", + 5370 => x"8c", + 5371 => x"05", + 5372 => x"15", + 5373 => x"5a", + 5374 => x"5c", + 5375 => x"d3", + 5376 => x"8c", + 5377 => x"d3", + 5378 => x"86", + 5379 => x"55", + 5380 => x"80", + 5381 => x"90", + 5382 => x"79", + 5383 => x"38", + 5384 => x"74", + 5385 => x"78", + 5386 => x"72", + 5387 => x"d3", + 5388 => x"8b", + 5389 => x"39", + 5390 => x"51", + 5391 => x"3f", + 5392 => x"80", + 5393 => x"16", + 5394 => x"27", + 5395 => x"08", + 5396 => x"dc", + 5397 => x"cd", + 5398 => x"81", + 5399 => x"ff", + 5400 => x"84", + 5401 => x"39", + 5402 => x"72", + 5403 => x"38", + 5404 => x"81", + 5405 => x"ff", + 5406 => x"89", + 5407 => x"84", + 5408 => x"bd", + 5409 => x"55", + 5410 => x"f6", + 5411 => x"80", + 5412 => x"88", + 5413 => x"a9", + 5414 => x"74", + 5415 => x"38", + 5416 => x"33", + 5417 => x"52", + 5418 => x"74", + 5419 => x"72", + 5420 => x"38", + 5421 => x"26", + 5422 => x"51", + 5423 => x"51", + 5424 => x"3f", + 5425 => x"d3", + 5426 => x"8c", + 5427 => x"f1", + 5428 => x"77", + 5429 => x"fe", + 5430 => x"81", + 5431 => x"98", + 5432 => x"2c", + 5433 => x"a0", + 5434 => x"06", + 5435 => x"f9", + 5436 => x"de", + 5437 => x"2b", + 5438 => x"70", + 5439 => x"30", + 5440 => x"9f", + 5441 => x"56", + 5442 => x"9b", + 5443 => x"72", + 5444 => x"9b", + 5445 => x"06", + 5446 => x"53", + 5447 => x"1c", + 5448 => x"26", + 5449 => x"ff", + 5450 => x"de", + 5451 => x"3d", + 5452 => x"3d", + 5453 => x"84", + 5454 => x"05", + 5455 => x"30", + 5456 => x"80", + 5457 => x"ff", + 5458 => x"51", + 5459 => x"5b", + 5460 => x"74", + 5461 => x"81", + 5462 => x"8c", + 5463 => x"57", + 5464 => x"3f", + 5465 => x"08", + 5466 => x"c0", + 5467 => x"81", + 5468 => x"87", + 5469 => x"0c", + 5470 => x"08", + 5471 => x"d4", + 5472 => x"80", + 5473 => x"76", + 5474 => x"3f", + 5475 => x"08", + 5476 => x"c0", + 5477 => x"7a", + 5478 => x"2e", + 5479 => x"19", + 5480 => x"59", + 5481 => x"3d", + 5482 => x"cc", + 5483 => x"30", + 5484 => x"80", + 5485 => x"79", + 5486 => x"38", + 5487 => x"90", + 5488 => x"90", + 5489 => x"98", + 5490 => x"78", + 5491 => x"3f", + 5492 => x"81", + 5493 => x"96", + 5494 => x"f9", + 5495 => x"02", + 5496 => x"05", + 5497 => x"ff", + 5498 => x"7a", + 5499 => x"fe", + 5500 => x"de", + 5501 => x"38", + 5502 => x"88", + 5503 => x"2e", + 5504 => x"39", + 5505 => x"54", + 5506 => x"53", + 5507 => x"51", + 5508 => x"de", + 5509 => x"83", + 5510 => x"76", + 5511 => x"0c", + 5512 => x"04", + 5513 => x"02", + 5514 => x"81", + 5515 => x"81", + 5516 => x"55", + 5517 => x"3f", + 5518 => x"22", + 5519 => x"89", + 5520 => x"ac", + 5521 => x"b8", + 5522 => x"c1", + 5523 => x"d4", + 5524 => x"87", + 5525 => x"80", + 5526 => x"fe", + 5527 => x"86", + 5528 => x"fe", + 5529 => x"c0", + 5530 => x"53", + 5531 => x"3f", + 5532 => x"f2", + 5533 => x"d4", + 5534 => x"f4", + 5535 => x"51", + 5536 => x"3f", + 5537 => x"70", + 5538 => x"52", + 5539 => x"95", + 5540 => x"fe", + 5541 => x"81", + 5542 => x"fe", + 5543 => x"80", + 5544 => x"fe", + 5545 => x"2a", + 5546 => x"51", + 5547 => x"2e", + 5548 => x"51", + 5549 => x"3f", + 5550 => x"51", + 5551 => x"3f", + 5552 => x"f1", + 5553 => x"83", + 5554 => x"06", + 5555 => x"80", + 5556 => x"81", + 5557 => x"ca", + 5558 => x"9c", + 5559 => x"c2", + 5560 => x"fe", + 5561 => x"72", + 5562 => x"81", + 5563 => x"71", + 5564 => x"38", + 5565 => x"f1", + 5566 => x"d5", + 5567 => x"f3", + 5568 => x"51", + 5569 => x"3f", + 5570 => x"70", + 5571 => x"52", + 5572 => x"95", + 5573 => x"fe", + 5574 => x"81", + 5575 => x"fe", + 5576 => x"80", + 5577 => x"fa", + 5578 => x"2a", + 5579 => x"51", + 5580 => x"2e", + 5581 => x"51", + 5582 => x"3f", + 5583 => x"51", + 5584 => x"3f", + 5585 => x"f0", + 5586 => x"87", + 5587 => x"06", + 5588 => x"80", + 5589 => x"81", + 5590 => x"c6", + 5591 => x"ec", + 5592 => x"be", + 5593 => x"fe", + 5594 => x"72", + 5595 => x"81", + 5596 => x"71", + 5597 => x"38", + 5598 => x"f0", + 5599 => x"d6", + 5600 => x"f2", + 5601 => x"51", + 5602 => x"3f", + 5603 => x"3f", + 5604 => x"04", + 5605 => x"78", + 5606 => x"55", + 5607 => x"80", + 5608 => x"38", + 5609 => x"77", + 5610 => x"33", + 5611 => x"39", + 5612 => x"80", + 5613 => x"81", + 5614 => x"57", + 5615 => x"2e", + 5616 => x"53", + 5617 => x"84", + 5618 => x"38", + 5619 => x"06", + 5620 => x"2e", + 5621 => x"88", + 5622 => x"70", + 5623 => x"34", + 5624 => x"90", + 5625 => x"f0", + 5626 => x"53", + 5627 => x"55", + 5628 => x"3f", + 5629 => x"08", + 5630 => x"15", + 5631 => x"81", + 5632 => x"38", + 5633 => x"81", + 5634 => x"53", + 5635 => x"d2", + 5636 => x"72", + 5637 => x"0c", + 5638 => x"04", + 5639 => x"77", + 5640 => x"56", + 5641 => x"75", + 5642 => x"d4", + 5643 => x"ec", + 5644 => x"a7", + 5645 => x"81", + 5646 => x"81", + 5647 => x"ff", + 5648 => x"81", + 5649 => x"30", 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x"80", + 5709 => x"dc", + 5710 => x"2e", + 5711 => x"78", + 5712 => x"38", + 5713 => x"81", + 5714 => x"82", + 5715 => x"78", + 5716 => x"ae", + 5717 => x"39", + 5718 => x"82", + 5719 => x"94", + 5720 => x"38", + 5721 => x"78", + 5722 => x"85", + 5723 => x"80", + 5724 => x"38", + 5725 => x"83", + 5726 => x"bc", + 5727 => x"38", + 5728 => x"78", + 5729 => x"87", + 5730 => x"80", + 5731 => x"bf", + 5732 => x"39", + 5733 => x"2e", + 5734 => x"78", + 5735 => x"a9", + 5736 => x"d0", + 5737 => x"38", + 5738 => x"24", + 5739 => x"80", + 5740 => x"eb", + 5741 => x"39", + 5742 => x"2e", + 5743 => x"78", + 5744 => x"8d", + 5745 => x"ed", + 5746 => x"82", + 5747 => x"38", + 5748 => x"24", + 5749 => x"80", + 5750 => x"ce", + 5751 => x"f9", + 5752 => x"38", + 5753 => x"78", + 5754 => x"8e", + 5755 => x"81", + 5756 => x"ba", + 5757 => x"39", + 5758 => x"f4", + 5759 => x"f8", + 5760 => x"82", + 5761 => x"de", + 5762 => x"38", + 5763 => x"51", + 5764 => x"b7", + 5765 => x"11", + 5766 => x"05", + 5767 => x"fa", + 5768 => x"c0", + 5769 => x"88", + 5770 => x"25", + 5771 => x"43", + 5772 => x"05", + 5773 => x"80", + 5774 => x"51", + 5775 => x"3f", + 5776 => x"08", + 5777 => x"59", + 5778 => x"81", + 5779 => x"fe", + 5780 => x"81", + 5781 => x"39", + 5782 => x"51", + 5783 => x"b7", + 5784 => x"11", + 5785 => x"05", + 5786 => x"ae", + 5787 => x"c0", + 5788 => x"fd", + 5789 => x"53", + 5790 => x"80", + 5791 => x"51", + 5792 => x"3f", + 5793 => x"08", + 5794 => x"c8", + 5795 => x"39", + 5796 => x"f4", + 5797 => x"f8", + 5798 => x"80", + 5799 => x"de", + 5800 => x"2e", + 5801 => x"89", + 5802 => x"38", + 5803 => x"f0", + 5804 => x"f8", + 5805 => x"80", + 5806 => x"de", + 5807 => x"38", + 5808 => x"08", + 5809 => x"81", + 5810 => x"79", + 5811 => x"eb", + 5812 => x"cb", + 5813 => x"79", + 5814 => x"b4", + 5815 => x"f0", + 5816 => x"b3", + 5817 => x"de", + 5818 => x"93", + 5819 => x"a0", + 5820 => x"cd", + 5821 => x"fc", + 5822 => x"3d", + 5823 => x"51", + 5824 => x"3f", + 5825 => x"08", + 5826 => x"f8", + 5827 => x"fe", + 5828 => x"81", + 5829 => x"c0", + 5830 => x"51", + 5831 => x"80", + 5832 => x"3d", + 5833 => x"51", + 5834 => x"3f", + 5835 => x"08", + 5836 => x"f8", + 5837 => x"fe", + 5838 => x"81", + 5839 => x"b8", + 5840 => x"05", + 5841 => x"e5", + 5842 => x"de", + 5843 => x"3d", + 5844 => x"52", + 5845 => x"dd", + 5846 => x"8c", + 5847 => x"f4", + 5848 => x"80", + 5849 => x"c0", + 5850 => x"06", + 5851 => x"79", + 5852 => x"f4", + 5853 => x"de", + 5854 => x"2e", + 5855 => x"81", + 5856 => x"51", + 5857 => x"fa", + 5858 => x"3d", + 5859 => x"53", + 5860 => x"51", + 5861 => x"3f", + 5862 => x"08", + 5863 => x"e2", + 5864 => x"fe", + 5865 => x"fe", + 5866 => x"fe", + 5867 => x"81", + 5868 => x"80", + 5869 => x"38", + 5870 => x"ec", + 5871 => x"f8", + 5872 => x"fe", + 5873 => x"de", + 5874 => x"38", + 5875 => x"08", + 5876 => x"d4", + 5877 => x"e9", + 5878 => x"5c", + 5879 => x"27", + 5880 => x"61", + 5881 => x"70", + 5882 => x"0c", + 5883 => x"f5", + 5884 => x"39", + 5885 => x"f4", + 5886 => x"f8", + 5887 => x"fe", + 5888 => x"de", + 5889 => x"df", + 5890 => x"d4", + 5891 => x"80", + 5892 => x"81", + 5893 => x"44", + 5894 => x"81", + 5895 => x"59", + 5896 => x"88", + 5897 => x"94", + 5898 => x"39", + 5899 => x"33", + 5900 => x"2e", + 5901 => x"db", + 5902 => x"ab", + 5903 => x"d7", + 5904 => x"80", + 5905 => x"81", + 5906 => x"44", + 5907 => x"db", + 5908 => x"78", + 5909 => x"38", + 5910 => x"08", + 5911 => x"81", + 5912 => x"fc", + 5913 => x"b7", + 5914 => x"11", + 5915 => x"05", + 5916 => x"a6", + 5917 => x"c0", + 5918 => x"38", + 5919 => x"33", + 5920 => x"2e", + 5921 => x"db", + 5922 => x"80", + 5923 => x"db", + 5924 => x"78", + 5925 => x"38", + 5926 => x"08", + 5927 => x"81", + 5928 => x"59", + 5929 => x"88", + 5930 => x"a0", + 5931 => x"39", + 5932 => x"33", + 5933 => x"2e", + 5934 => x"db", + 5935 => x"99", + 5936 => x"d2", + 5937 => x"80", + 5938 => x"81", + 5939 => x"43", + 5940 => x"db", + 5941 => x"05", + 5942 => x"fe", + 5943 => x"fe", + 5944 => x"fe", + 5945 => x"81", + 5946 => x"80", + 5947 => x"80", + 5948 => x"79", + 5949 => x"38", + 5950 => x"90", + 5951 => x"78", + 5952 => x"38", + 5953 => x"83", + 5954 => x"81", + 5955 => x"fe", + 5956 => x"a0", + 5957 => x"61", + 5958 => x"63", + 5959 => x"3f", + 5960 => x"51", + 5961 => x"b7", + 5962 => x"11", + 5963 => x"05", + 5964 => x"e6", + 5965 => x"c0", + 5966 => x"f7", + 5967 => x"3d", + 5968 => x"53", + 5969 => x"51", + 5970 => x"3f", + 5971 => x"08", + 5972 => x"38", + 5973 => x"80", + 5974 => x"79", + 5975 => x"05", + 5976 => x"fe", + 5977 => x"fe", + 5978 => x"fe", + 5979 => x"81", + 5980 => x"e0", + 5981 => x"39", + 5982 => x"54", + 5983 => x"80", + 5984 => x"a1", + 5985 => x"52", + 5986 => x"f9", + 5987 => x"45", + 5988 => x"78", + 5989 => x"ea", + 5990 => x"27", + 5991 => x"3d", + 5992 => x"53", + 5993 => x"51", + 5994 => x"3f", + 5995 => x"08", + 5996 => x"38", + 5997 => x"80", + 5998 => x"79", + 5999 => x"05", + 6000 => x"39", + 6001 => x"51", + 6002 => x"3f", + 6003 => x"b7", + 6004 => x"11", + 6005 => x"05", + 6006 => x"b0", + 6007 => x"c0", + 6008 => x"f6", + 6009 => x"3d", + 6010 => x"53", + 6011 => x"51", + 6012 => x"3f", + 6013 => x"08", + 6014 => x"38", + 6015 => x"be", + 6016 => x"70", + 6017 => x"23", + 6018 => x"3d", + 6019 => x"53", + 6020 => x"51", + 6021 => x"3f", + 6022 => x"08", + 6023 => x"e2", + 6024 => x"22", + 6025 => x"d8", + 6026 => x"f7", + 6027 => x"f8", + 6028 => x"fe", + 6029 => x"79", + 6030 => x"59", + 6031 => x"f5", + 6032 => x"9f", + 6033 => x"60", + 6034 => x"d5", + 6035 => x"fe", + 6036 => x"fe", + 6037 => x"fe", + 6038 => x"81", + 6039 => x"80", + 6040 => x"60", + 6041 => x"05", + 6042 => x"82", + 6043 => x"78", + 6044 => x"39", + 6045 => x"51", + 6046 => x"3f", + 6047 => x"b7", + 6048 => x"11", + 6049 => x"05", + 6050 => x"80", + 6051 => x"c0", + 6052 => x"f4", + 6053 => x"3d", + 6054 => x"53", + 6055 => x"51", + 6056 => x"3f", + 6057 => x"08", + 6058 => x"38", + 6059 => x"0c", + 6060 => x"05", + 6061 => x"fe", + 6062 => x"fe", + 6063 => x"fe", + 6064 => x"81", + 6065 => x"e4", + 6066 => x"39", + 6067 => x"54", + 6068 => x"a0", + 6069 => x"cd", + 6070 => x"52", + 6071 => x"f7", + 6072 => x"45", + 6073 => x"78", + 6074 => x"96", + 6075 => x"27", + 6076 => x"3d", + 6077 => x"53", + 6078 => x"51", + 6079 => x"3f", + 6080 => x"08", + 6081 => x"38", + 6082 => x"0c", + 6083 => x"05", + 6084 => x"39", + 6085 => x"51", + 6086 => x"3f", + 6087 => x"b7", + 6088 => x"11", + 6089 => x"05", + 6090 => x"ee", + 6091 => x"c0", + 6092 => x"38", + 6093 => x"33", + 6094 => x"2e", + 6095 => x"db", + 6096 => x"80", + 6097 => x"db", + 6098 => x"78", + 6099 => x"38", + 6100 => x"08", + 6101 => x"81", + 6102 => x"59", + 6103 => x"88", + 6104 => x"9c", + 6105 => x"39", + 6106 => x"33", + 6107 => x"2e", + 6108 => x"db", + 6109 => x"9a", + 6110 => x"d2", + 6111 => x"80", + 6112 => x"81", + 6113 => x"44", + 6114 => x"db", + 6115 => x"80", + 6116 => x"3d", + 6117 => x"53", + 6118 => x"51", + 6119 => x"3f", + 6120 => x"08", + 6121 => x"81", + 6122 => x"59", + 6123 => x"89", + 6124 => x"90", + 6125 => x"cc", + 6126 => x"d5", + 6127 => x"80", + 6128 => x"81", + 6129 => x"43", + 6130 => x"db", + 6131 => x"78", + 6132 => x"38", + 6133 => x"08", + 6134 => x"81", + 6135 => x"59", + 6136 => x"88", + 6137 => x"a8", + 6138 => x"39", + 6139 => x"33", + 6140 => x"2e", + 6141 => x"db", + 6142 => x"88", + 6143 => x"bc", + 6144 => x"43", + 6145 => x"ec", + 6146 => x"f8", + 6147 => x"f6", + 6148 => x"de", + 6149 => x"38", + 6150 => x"08", + 6151 => x"ac", + 6152 => x"9d", + 6153 => x"79", + 6154 => x"38", + 6155 => x"78", + 6156 => x"81", + 6157 => x"78", + 6158 => x"81", + 6159 => x"fe", + 6160 => x"84", + 6161 => x"39", + 6162 => x"51", + 6163 => x"d8", + 6164 => x"ed", + 6165 => x"51", + 6166 => x"3f", + 6167 => x"81", + 6168 => x"fe", + 6169 => x"a2", + 6170 => x"ad", + 6171 => x"39", + 6172 => x"0b", + 6173 => x"84", + 6174 => x"81", + 6175 => x"94", + 6176 => x"d8", + 6177 => x"ed", + 6178 => x"f6", + 6179 => x"90", + 6180 => x"ad", + 6181 => x"83", + 6182 => x"94", + 6183 => x"80", + 6184 => x"c0", + 6185 => x"f0", + 6186 => x"3d", + 6187 => x"53", + 6188 => x"51", + 6189 => x"3f", + 6190 => x"08", + 6191 => x"c2", + 6192 => x"81", + 6193 => x"fe", + 6194 => x"63", + 6195 => x"b7", + 6196 => x"11", + 6197 => x"05", + 6198 => x"be", + 6199 => x"c0", + 6200 => x"f0", + 6201 => x"52", + 6202 => x"51", + 6203 => x"3f", + 6204 => x"2d", + 6205 => x"08", + 6206 => x"c0", + 6207 => x"f0", + 6208 => x"de", + 6209 => x"81", + 6210 => x"fe", + 6211 => x"ef", + 6212 => x"d9", + 6213 => x"ec", + 6214 => x"bd", + 6215 => x"e2", + 6216 => x"94", + 6217 => x"99", + 6218 => x"ff", + 6219 => x"e6", + 6220 => x"ce", + 6221 => x"33", + 6222 => x"80", + 6223 => x"38", + 6224 => x"81", + 6225 => x"70", + 6226 => x"5a", + 6227 => x"81", + 6228 => x"3d", + 6229 => x"51", + 6230 => x"3f", + 6231 => x"08", + 6232 => x"7b", + 6233 => x"38", + 6234 => x"89", + 6235 => x"2e", + 6236 => x"cd", + 6237 => x"2e", + 6238 => x"c5", + 6239 => x"a8", + 6240 => x"81", + 6241 => x"80", + 6242 => x"b0", + 6243 => x"ff", + 6244 => x"fe", + 6245 => x"bb", + 6246 => x"d0", + 6247 => x"ff", + 6248 => x"fe", + 6249 => x"ab", + 6250 => x"81", + 6251 => x"80", + 6252 => x"c0", + 6253 => x"ff", + 6254 => x"fe", + 6255 => x"93", + 6256 => x"80", + 6257 => x"cc", + 6258 => x"ff", + 6259 => x"fe", + 6260 => x"81", + 6261 => x"81", + 6262 => x"80", + 6263 => x"11", + 6264 => x"55", + 6265 => x"80", + 6266 => x"80", + 6267 => x"3d", + 6268 => x"51", + 6269 => x"81", + 6270 => x"81", + 6271 => x"09", + 6272 => x"72", + 6273 => x"51", + 6274 => x"7b", + 6275 => x"38", + 6276 => x"8d", + 6277 => x"70", + 6278 => x"5d", + 6279 => x"c3", + 6280 => x"32", + 6281 => x"07", + 6282 => x"38", + 6283 => x"09", + 6284 => x"ce", + 6285 => x"d4", + 6286 => x"e9", + 6287 => x"39", + 6288 => x"80", + 6289 => x"f4", + 6290 => x"94", + 6291 => x"54", + 6292 => x"80", + 6293 => x"fe", + 6294 => x"81", + 6295 => x"90", + 6296 => x"55", + 6297 => x"80", + 6298 => x"fe", + 6299 => x"72", + 6300 => x"08", + 6301 => x"87", + 6302 => x"70", + 6303 => x"87", + 6304 => x"72", + 6305 => x"f1", + 6306 => x"c0", + 6307 => x"75", + 6308 => x"87", + 6309 => x"73", + 6310 => x"dd", + 6311 => x"de", + 6312 => x"75", + 6313 => x"83", + 6314 => x"94", + 6315 => x"80", + 6316 => x"c0", + 6317 => x"9f", + 6318 => x"de", + 6319 => x"bb", + 6320 => x"d4", + 6321 => x"9e", + 6322 => x"c5", + 6323 => x"e4", + 6324 => x"ce", + 6325 => x"f0", + 6326 => x"e5", + 6327 => x"e1", + 6328 => x"a8", + 6329 => x"e6", + 6330 => x"c6", + 6331 => x"00", + 6332 => x"ff", + 6333 => x"00", + 6334 => x"ff", + 6335 => x"ff", + 6336 => x"00", + 6337 => x"00", + 6338 => x"00", + 6339 => x"00", + 6340 => x"00", + 6341 => x"00", + 6342 => x"00", + 6343 => x"00", + 6344 => x"00", + 6345 => x"00", + 6346 => x"00", + 6347 => x"00", + 6348 => x"00", + 6349 => x"00", + 6350 => x"00", + 6351 => x"00", + 6352 => x"00", + 6353 => x"00", + 6354 => x"00", + 6355 => x"00", + 6356 => x"00", + 6357 => x"00", + 6358 => x"00", + 6359 => x"00", + 6360 => x"00", + 6361 => x"64", + 6362 => x"2f", + 6363 => x"25", + 6364 => x"64", + 6365 => x"2e", + 6366 => x"64", + 6367 => x"6f", + 6368 => x"6f", + 6369 => x"67", + 6370 => x"74", + 6371 => x"00", + 6372 => x"28", + 6373 => x"6d", + 6374 => x"43", + 6375 => x"6e", + 6376 => x"29", + 6377 => x"0a", + 6378 => x"69", + 6379 => x"20", + 6380 => x"6c", + 6381 => x"6e", + 6382 => x"3a", + 6383 => x"20", + 6384 => x"42", + 6385 => x"52", + 6386 => x"20", + 6387 => x"38", + 6388 => x"30", + 6389 => x"2e", + 6390 => x"20", + 6391 => x"44", + 6392 => x"20", + 6393 => x"20", + 6394 => x"38", + 6395 => x"30", + 6396 => x"2e", + 6397 => x"20", + 6398 => x"4e", + 6399 => x"42", + 6400 => x"20", + 6401 => x"38", + 6402 => x"30", + 6403 => x"2e", + 6404 => x"20", + 6405 => x"52", + 6406 => x"20", + 6407 => x"20", + 6408 => x"38", + 6409 => x"30", + 6410 => x"2e", + 6411 => x"20", + 6412 => x"41", + 6413 => x"20", + 6414 => x"20", + 6415 => x"38", + 6416 => x"30", + 6417 => x"2e", + 6418 => x"20", + 6419 => x"44", + 6420 => x"52", + 6421 => x"20", + 6422 => x"76", + 6423 => x"73", + 6424 => x"30", + 6425 => x"2e", + 6426 => x"20", + 6427 => x"49", + 6428 => x"31", + 6429 => x"20", + 6430 => x"6d", + 6431 => x"20", + 6432 => x"30", + 6433 => x"2e", + 6434 => x"20", + 6435 => x"4e", + 6436 => x"43", + 6437 => x"20", + 6438 => x"61", + 6439 => x"6c", + 6440 => x"30", + 6441 => x"2e", + 6442 => x"20", + 6443 => x"49", + 6444 => x"4f", + 6445 => x"42", + 6446 => x"00", + 6447 => x"20", + 6448 => x"42", + 6449 => x"43", + 6450 => x"20", + 6451 => x"4f", + 6452 => x"0a", + 6453 => x"20", + 6454 => x"53", + 6455 => x"00", + 6456 => x"20", + 6457 => x"50", + 6458 => x"00", + 6459 => x"64", + 6460 => x"73", + 6461 => x"3a", + 6462 => x"20", + 6463 => x"50", + 6464 => x"65", + 6465 => x"20", + 6466 => x"74", + 6467 => x"41", + 6468 => x"65", + 6469 => x"3d", + 6470 => x"38", + 6471 => x"00", + 6472 => x"20", + 6473 => x"50", + 6474 => x"65", + 6475 => x"79", + 6476 => x"61", + 6477 => x"41", + 6478 => x"65", + 6479 => x"3d", + 6480 => x"38", + 6481 => x"00", + 6482 => x"20", + 6483 => x"74", + 6484 => x"20", + 6485 => x"72", + 6486 => x"64", + 6487 => x"73", + 6488 => x"20", + 6489 => x"3d", + 6490 => x"38", + 6491 => x"00", + 6492 => x"69", + 6493 => x"0a", + 6494 => x"20", + 6495 => x"50", + 6496 => x"64", + 6497 => x"20", + 6498 => x"20", + 6499 => x"20", + 6500 => x"20", + 6501 => x"3d", + 6502 => x"34", + 6503 => x"00", + 6504 => x"20", + 6505 => x"79", + 6506 => x"6d", + 6507 => x"6f", + 6508 => x"46", + 6509 => x"20", + 6510 => x"20", + 6511 => x"3d", + 6512 => x"2e", + 6513 => x"64", + 6514 => x"0a", + 6515 => x"20", + 6516 => x"44", + 6517 => x"20", + 6518 => x"63", + 6519 => x"72", + 6520 => x"20", + 6521 => x"20", + 6522 => x"3d", + 6523 => x"2e", + 6524 => x"64", + 6525 => x"0a", + 6526 => x"20", + 6527 => x"69", + 6528 => x"6f", + 6529 => x"53", + 6530 => x"4d", + 6531 => x"6f", + 6532 => x"46", + 6533 => x"3d", + 6534 => x"2e", + 6535 => x"64", + 6536 => x"0a", + 6537 => x"6d", + 6538 => x"00", + 6539 => x"65", + 6540 => x"6d", + 6541 => x"6c", + 6542 => x"00", + 6543 => x"56", + 6544 => x"56", + 6545 => x"6e", + 6546 => x"6e", + 6547 => x"77", + 6548 => x"44", + 6549 => x"2a", + 6550 => x"3b", + 6551 => x"3f", + 6552 => x"7f", + 6553 => x"41", + 6554 => x"41", + 6555 => x"00", + 6556 => x"fe", + 6557 => x"44", + 6558 => x"2e", + 6559 => x"4f", + 6560 => x"4d", + 6561 => x"20", + 6562 => x"54", + 6563 => x"20", + 6564 => x"4f", + 6565 => x"4d", + 6566 => x"20", + 6567 => x"54", + 6568 => x"20", + 6569 => x"00", + 6570 => x"00", + 6571 => x"00", + 6572 => x"00", + 6573 => x"9a", + 6574 => x"41", + 6575 => x"45", + 6576 => x"49", + 6577 => x"92", + 6578 => x"4f", + 6579 => x"99", + 6580 => x"9d", + 6581 => x"49", + 6582 => x"a5", + 6583 => x"a9", + 6584 => x"ad", + 6585 => x"b1", + 6586 => x"b5", + 6587 => x"b9", + 6588 => x"bd", + 6589 => x"c1", + 6590 => x"c5", + 6591 => x"c9", + 6592 => x"cd", + 6593 => x"d1", + 6594 => x"d5", + 6595 => x"d9", + 6596 => x"dd", + 6597 => x"e1", + 6598 => x"e5", + 6599 => x"e9", + 6600 => x"ed", + 6601 => x"f1", + 6602 => x"f5", + 6603 => x"f9", + 6604 => x"fd", + 6605 => x"2e", + 6606 => x"5b", + 6607 => x"22", + 6608 => x"3e", + 6609 => x"00", + 6610 => x"01", + 6611 => x"10", + 6612 => x"00", + 6613 => x"00", + 6614 => x"01", + 6615 => x"04", + 6616 => x"10", + 6617 => x"00", + 6618 => x"69", + 6619 => x"00", + 6620 => x"69", + 6621 => x"6c", + 6622 => x"69", + 6623 => x"00", + 6624 => x"6c", + 6625 => x"00", + 6626 => x"65", + 6627 => x"00", + 6628 => x"63", + 6629 => x"72", + 6630 => x"64", + 6631 => x"00", + 6632 => x"73", + 6633 => x"00", + 6634 => x"65", + 6635 => x"65", + 6636 => x"65", + 6637 => x"69", + 6638 => x"69", + 6639 => x"66", + 6640 => x"66", + 6641 => x"61", + 6642 => x"00", + 6643 => x"6d", + 6644 => x"65", + 6645 => x"72", + 6646 => x"65", + 6647 => x"00", + 6648 => x"6e", + 6649 => x"00", + 6650 => x"65", + 6651 => x"00", + 6652 => x"69", + 6653 => x"45", + 6654 => x"72", + 6655 => x"6e", + 6656 => x"6e", + 6657 => x"65", + 6658 => x"72", + 6659 => x"00", + 6660 => x"69", + 6661 => x"6e", + 6662 => x"72", + 6663 => x"79", + 6664 => x"00", + 6665 => x"6f", + 6666 => x"6c", + 6667 => x"6f", + 6668 => x"2e", + 6669 => x"6f", + 6670 => x"74", + 6671 => x"6f", + 6672 => x"2e", + 6673 => x"6e", + 6674 => x"69", + 6675 => x"69", + 6676 => x"61", + 6677 => x"0a", + 6678 => x"63", + 6679 => x"73", + 6680 => x"6e", + 6681 => x"2e", + 6682 => x"69", + 6683 => x"61", + 6684 => x"61", + 6685 => x"65", + 6686 => x"74", + 6687 => x"00", + 6688 => x"69", + 6689 => x"68", + 6690 => x"6c", + 6691 => x"6e", + 6692 => x"69", + 6693 => x"00", + 6694 => x"44", + 6695 => x"20", + 6696 => x"74", + 6697 => x"72", + 6698 => x"63", + 6699 => x"2e", + 6700 => x"72", + 6701 => x"20", + 6702 => x"62", + 6703 => x"69", + 6704 => x"6e", + 6705 => x"69", + 6706 => x"00", + 6707 => x"69", + 6708 => x"6e", + 6709 => x"65", + 6710 => x"6c", + 6711 => x"0a", + 6712 => x"6f", + 6713 => x"6d", + 6714 => x"69", + 6715 => x"20", + 6716 => x"65", + 6717 => x"74", + 6718 => x"66", + 6719 => x"64", + 6720 => x"20", + 6721 => x"6b", + 6722 => x"00", + 6723 => x"6f", + 6724 => x"74", + 6725 => x"6f", + 6726 => x"64", + 6727 => x"00", + 6728 => x"69", + 6729 => x"75", + 6730 => x"6f", + 6731 => x"61", + 6732 => x"6e", + 6733 => x"6e", + 6734 => x"6c", + 6735 => x"0a", + 6736 => x"69", + 6737 => x"69", + 6738 => x"6f", + 6739 => x"64", + 6740 => x"00", + 6741 => x"6e", + 6742 => x"66", + 6743 => x"65", + 6744 => x"6d", + 6745 => x"72", + 6746 => x"00", + 6747 => x"6f", + 6748 => x"61", + 6749 => x"6f", + 6750 => x"20", + 6751 => x"65", + 6752 => x"00", + 6753 => x"61", + 6754 => x"65", + 6755 => x"73", + 6756 => x"63", + 6757 => x"65", + 6758 => x"0a", + 6759 => x"75", + 6760 => x"73", + 6761 => x"00", + 6762 => x"6e", + 6763 => x"77", + 6764 => x"72", + 6765 => x"2e", + 6766 => x"25", + 6767 => x"62", + 6768 => x"73", + 6769 => x"20", + 6770 => x"25", + 6771 => x"62", + 6772 => x"73", + 6773 => x"63", + 6774 => x"00", + 6775 => x"30", + 6776 => x"00", + 6777 => x"20", + 6778 => x"30", + 6779 => x"00", + 6780 => x"20", + 6781 => x"20", + 6782 => x"00", + 6783 => x"30", + 6784 => x"00", + 6785 => x"20", + 6786 => x"7c", + 6787 => x"0d", + 6788 => x"65", + 6789 => x"00", + 6790 => x"50", + 6791 => x"00", + 6792 => x"2a", + 6793 => x"73", + 6794 => x"00", + 6795 => x"39", + 6796 => x"2f", + 6797 => x"39", + 6798 => x"31", + 6799 => x"00", + 6800 => x"5a", + 6801 => x"20", + 6802 => x"20", + 6803 => x"78", + 6804 => x"73", + 6805 => x"20", + 6806 => x"0a", + 6807 => x"50", + 6808 => x"20", + 6809 => x"65", + 6810 => x"70", + 6811 => x"61", + 6812 => x"65", + 6813 => x"00", + 6814 => x"69", + 6815 => x"20", + 6816 => x"65", + 6817 => x"70", + 6818 => x"00", + 6819 => x"53", + 6820 => x"6e", + 6821 => x"72", + 6822 => x"0a", + 6823 => x"4f", + 6824 => x"20", + 6825 => x"69", + 6826 => x"72", + 6827 => x"74", + 6828 => x"4f", + 6829 => x"20", + 6830 => x"69", + 6831 => x"72", + 6832 => x"74", + 6833 => x"41", + 6834 => x"20", + 6835 => x"69", + 6836 => x"72", + 6837 => x"74", + 6838 => x"41", + 6839 => x"20", + 6840 => x"69", + 6841 => x"72", + 6842 => x"74", + 6843 => x"41", + 6844 => x"20", + 6845 => x"69", + 6846 => x"72", + 6847 => x"74", + 6848 => x"41", + 6849 => x"20", + 6850 => x"69", + 6851 => x"72", + 6852 => x"74", + 6853 => x"65", + 6854 => x"6e", + 6855 => x"70", + 6856 => x"6d", + 6857 => x"2e", + 6858 => x"00", + 6859 => x"6e", + 6860 => x"69", + 6861 => x"74", + 6862 => x"72", + 6863 => x"0a", + 6864 => x"75", + 6865 => x"78", + 6866 => x"62", + 6867 => x"00", + 6868 => x"3a", + 6869 => x"61", + 6870 => x"64", + 6871 => x"20", + 6872 => x"74", + 6873 => x"69", + 6874 => x"73", + 6875 => x"61", + 6876 => x"30", + 6877 => x"6c", + 6878 => x"65", + 6879 => x"69", + 6880 => x"61", + 6881 => x"6c", + 6882 => x"0a", + 6883 => x"20", + 6884 => x"61", + 6885 => x"69", + 6886 => x"69", + 6887 => x"00", + 6888 => x"6e", + 6889 => x"61", + 6890 => x"65", + 6891 => x"00", + 6892 => x"61", + 6893 => x"64", + 6894 => x"20", + 6895 => x"74", + 6896 => x"69", + 6897 => x"0a", + 6898 => x"63", + 6899 => x"0a", + 6900 => x"75", + 6901 => x"6c", + 6902 => x"69", + 6903 => x"2e", + 6904 => x"00", + 6905 => x"75", + 6906 => x"4d", + 6907 => x"72", + 6908 => x"00", + 6909 => x"43", + 6910 => x"6c", + 6911 => x"2e", + 6912 => x"30", + 6913 => x"25", + 6914 => x"2d", + 6915 => x"3f", + 6916 => x"00", + 6917 => x"30", + 6918 => x"25", + 6919 => x"2d", + 6920 => x"30", + 6921 => x"25", + 6922 => x"2d", + 6923 => x"65", + 6924 => x"68", + 6925 => x"2e", + 6926 => x"00", + 6927 => x"30", + 6928 => x"2d", + 6929 => x"38", + 6930 => x"00", + 6931 => x"69", + 6932 => x"6c", + 6933 => x"20", + 6934 => x"65", + 6935 => x"70", + 6936 => x"00", + 6937 => x"6e", + 6938 => x"69", + 6939 => x"69", + 6940 => x"72", + 6941 => x"74", + 6942 => x"00", + 6943 => x"69", + 6944 => x"6c", + 6945 => x"75", + 6946 => x"20", + 6947 => x"6f", + 6948 => x"6e", + 6949 => x"69", + 6950 => x"75", + 6951 => x"20", + 6952 => x"6f", + 6953 => x"78", + 6954 => x"74", + 6955 => x"20", + 6956 => x"65", + 6957 => x"25", + 6958 => x"20", + 6959 => x"0a", + 6960 => x"61", + 6961 => x"6e", + 6962 => x"6f", + 6963 => x"40", + 6964 => x"38", + 6965 => x"2e", + 6966 => x"00", + 6967 => x"61", + 6968 => x"72", + 6969 => x"72", + 6970 => x"20", + 6971 => x"65", + 6972 => x"64", + 6973 => x"00", + 6974 => x"65", + 6975 => x"72", + 6976 => x"67", + 6977 => x"70", + 6978 => x"61", + 6979 => x"6e", + 6980 => x"0a", + 6981 => x"6f", + 6982 => x"72", + 6983 => x"6f", + 6984 => x"67", + 6985 => x"0a", + 6986 => x"50", + 6987 => x"69", + 6988 => x"64", + 6989 => x"73", + 6990 => x"2e", + 6991 => x"00", + 6992 => x"64", + 6993 => x"73", + 6994 => x"00", + 6995 => x"64", + 6996 => x"73", + 6997 => x"61", + 6998 => x"6f", + 6999 => x"6e", + 7000 => x"00", + 7001 => x"75", + 7002 => x"6e", + 7003 => x"2e", + 7004 => x"6e", + 7005 => x"69", + 7006 => x"69", + 7007 => x"72", + 7008 => x"74", + 7009 => x"2e", + 7010 => x"00", + 7011 => x"00", + 7012 => x"00", + 7013 => x"00", + 7014 => x"00", + 7015 => x"01", + 7016 => x"00", + 7017 => x"01", + 7018 => x"81", + 7019 => x"00", + 7020 => x"7f", + 7021 => x"00", + 7022 => x"00", + 7023 => x"00", + 7024 => x"00", + 7025 => x"f5", + 7026 => x"f5", + 7027 => x"f5", + 7028 => x"00", + 7029 => x"01", + 7030 => x"01", + 7031 => x"01", + 7032 => x"00", + 7033 => x"00", + 7034 => x"00", + 7035 => x"00", + 7036 => x"00", + 7037 => x"02", + 7038 => x"00", + 7039 => x"00", + 7040 => x"00", + 7041 => x"04", + 7042 => x"00", + 7043 => x"00", + 7044 => x"00", + 7045 => x"14", + 7046 => x"00", + 7047 => x"00", + 7048 => x"00", + 7049 => x"2b", + 7050 => x"00", + 7051 => x"00", + 7052 => x"00", + 7053 => x"30", + 7054 => x"00", + 7055 => x"00", + 7056 => x"00", + 7057 => x"3c", + 7058 => x"00", + 7059 => x"00", + 7060 => x"00", + 7061 => x"40", + 7062 => x"00", + 7063 => x"00", + 7064 => x"00", + 7065 => x"45", + 7066 => x"00", + 7067 => x"00", + 7068 => x"00", + 7069 => x"41", + 7070 => x"00", + 7071 => x"00", + 7072 => x"00", + 7073 => x"42", + 7074 => x"00", + 7075 => x"00", + 7076 => x"00", + 7077 => x"43", + 7078 => x"00", + 7079 => x"00", + 7080 => x"00", + 7081 => x"50", + 7082 => x"00", + 7083 => x"00", + 7084 => x"00", + 7085 => x"51", + 7086 => x"00", + 7087 => x"00", + 7088 => x"00", + 7089 => x"54", + 7090 => x"00", + 7091 => x"00", + 7092 => x"00", + 7093 => x"55", + 7094 => x"00", + 7095 => x"00", + 7096 => x"00", + 7097 => x"79", + 7098 => x"00", + 7099 => x"00", + 7100 => x"00", + 7101 => x"78", + 7102 => x"00", + 7103 => x"00", + 7104 => x"00", + 7105 => x"82", + 7106 => x"00", + 7107 => x"00", + 7108 => x"00", + 7109 => x"83", + 7110 => x"00", + 7111 => x"00", + 7112 => x"00", + 7113 => x"85", + 7114 => x"00", + 7115 => x"00", + 7116 => x"00", + 7117 => x"87", + 7118 => x"00", + 7119 => x"00", + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + 0 => x"0b", + 1 => x"d8", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"88", + 9 => x"90", + 10 => x"08", + 11 => x"8c", + 12 => x"04", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"71", + 17 => x"72", + 18 => x"81", + 19 => x"83", + 20 => x"ff", + 21 => x"04", + 22 => x"00", + 23 => x"00", + 24 => x"71", + 25 => x"83", + 26 => x"83", + 27 => x"05", + 28 => x"2b", + 29 => x"73", + 30 => x"0b", + 31 => x"83", + 32 => x"72", + 33 => x"72", + 34 => x"09", + 35 => x"73", + 36 => x"07", + 37 => x"53", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"73", + 42 => x"51", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"71", + 50 => x"09", + 51 => x"0a", + 52 => x"0a", + 53 => x"05", + 54 => x"51", + 55 => x"04", + 56 => x"72", + 57 => x"73", + 58 => x"51", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"bc", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"0a", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"09", + 90 => x"0b", + 91 => x"05", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"73", + 98 => x"09", + 99 => x"81", + 100 => x"06", + 101 => x"04", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"04", + 106 => x"06", + 107 => x"82", + 108 => x"0b", + 109 => x"fc", + 110 => x"51", + 111 => x"00", + 112 => x"72", + 113 => x"72", + 114 => x"81", + 115 => x"0a", + 116 => x"51", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"72", + 121 => x"72", + 122 => x"81", + 123 => x"0a", + 124 => x"53", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"71", + 129 => x"52", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"04", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"73", + 146 => x"07", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"71", + 153 => x"72", + 154 => x"81", + 155 => x"10", + 156 => x"81", + 157 => x"04", + 158 => x"00", + 159 => x"00", + 160 => x"71", + 161 => x"0b", + 162 => x"f0", + 163 => x"10", + 164 => x"06", + 165 => x"92", + 166 => x"00", + 167 => x"00", + 168 => x"88", + 169 => x"90", + 170 => x"0b", + 171 => x"dd", + 172 => x"88", + 173 => x"0c", + 174 => x"0c", + 175 => x"00", + 176 => x"88", + 177 => x"90", + 178 => x"0b", + 179 => x"c9", + 180 => x"88", + 181 => x"0c", + 182 => x"0c", + 183 => x"00", + 184 => x"72", + 185 => x"05", + 186 => x"81", + 187 => x"70", + 188 => x"73", + 189 => x"05", + 190 => x"07", + 191 => x"04", + 192 => x"72", + 193 => x"05", + 194 => x"09", + 195 => x"05", + 196 => x"06", + 197 => x"74", + 198 => x"06", + 199 => x"51", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"04", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"71", + 217 => x"04", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"04", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"02", + 233 => x"10", + 234 => x"04", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"05", + 250 => x"02", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"00", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"0b", + 265 => x"81", + 266 => x"0b", + 267 => x"0b", + 268 => x"94", + 269 => x"0b", + 270 => x"0b", + 271 => x"b2", + 272 => x"0b", + 273 => x"0b", + 274 => x"d0", + 275 => x"0b", + 276 => x"0b", + 277 => x"ee", + 278 => x"0b", + 279 => x"0b", + 280 => x"8c", + 281 => x"0b", + 282 => x"0b", + 283 => x"aa", + 284 => x"0b", + 285 => x"0b", + 286 => x"c8", + 287 => x"0b", + 288 => x"0b", + 289 => x"e6", + 290 => x"0b", + 291 => x"0b", + 292 => x"84", + 293 => x"0b", + 294 => x"0b", + 295 => x"a4", + 296 => x"0b", + 297 => x"0b", + 298 => x"c4", + 299 => x"0b", + 300 => x"0b", + 301 => x"e4", + 302 => x"0b", + 303 => x"0b", + 304 => x"84", + 305 => x"0b", + 306 => x"0b", + 307 => x"a4", + 308 => x"0b", + 309 => x"0b", + 310 => x"c4", + 311 => x"0b", + 312 => x"0b", + 313 => x"e4", + 314 => x"0b", + 315 => x"0b", + 316 => x"84", + 317 => x"0b", + 318 => x"0b", + 319 => x"a4", + 320 => x"0b", + 321 => x"0b", + 322 => x"c4", + 323 => x"0b", + 324 => x"0b", + 325 => x"e4", + 326 => x"0b", + 327 => x"0b", + 328 => x"84", + 329 => x"0b", + 330 => x"0b", + 331 => x"a3", + 332 => x"0b", + 333 => x"0b", + 334 => x"c1", + 335 => x"0b", + 336 => x"0b", + 337 => x"df", + 338 => x"0b", + 339 => x"ff", + 340 => x"ff", + 341 => x"ff", + 342 => x"ff", + 343 => x"ff", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"04", + 385 => x"04", + 386 => x"0c", + 387 => x"81", + 388 => x"84", + 389 => x"81", + 390 => x"ad", + 391 => x"de", + 392 => x"80", + 393 => x"de", + 394 => x"a1", + 395 => x"cc", + 396 => x"90", + 397 => x"cc", + 398 => x"2d", + 399 => x"08", + 400 => x"04", + 401 => x"0c", + 402 => x"81", + 403 => x"84", + 404 => x"81", + 405 => x"b5", + 406 => x"de", + 407 => x"80", + 408 => x"de", + 409 => x"e2", + 410 => x"cc", + 411 => x"90", + 412 => x"cc", + 413 => x"2d", + 414 => x"08", + 415 => x"04", + 416 => x"0c", + 417 => x"81", + 418 => x"84", + 419 => x"81", + 420 => x"b4", + 421 => x"de", + 422 => x"80", + 423 => x"de", + 424 => x"b9", + 425 => x"cc", + 426 => x"90", + 427 => x"cc", + 428 => x"2d", + 429 => x"08", + 430 => x"04", + 431 => x"0c", + 432 => x"81", + 433 => x"84", + 434 => x"81", + 435 => x"a3", + 436 => x"de", + 437 => x"80", + 438 => x"de", + 439 => x"a8", + 440 => x"cc", + 441 => x"90", + 442 => x"cc", + 443 => x"2d", + 444 => x"08", + 445 => x"04", + 446 => x"0c", + 447 => x"81", + 448 => x"84", + 449 => x"81", + 450 => x"80", + 451 => x"81", + 452 => x"84", + 453 => x"81", + 454 => x"80", + 455 => x"81", + 456 => x"84", + 457 => x"81", + 458 => x"80", + 459 => x"81", + 460 => x"84", + 461 => x"81", + 462 => x"80", + 463 => x"81", + 464 => x"84", + 465 => x"81", + 466 => x"80", + 467 => x"81", + 468 => x"84", + 469 => x"81", + 470 => x"81", + 471 => x"81", + 472 => x"84", + 473 => x"81", + 474 => x"80", + 475 => x"81", + 476 => x"84", + 477 => x"81", + 478 => x"80", + 479 => x"81", + 480 => x"84", + 481 => x"81", + 482 => x"81", + 483 => x"81", + 484 => x"84", + 485 => x"81", + 486 => x"81", + 487 => x"81", + 488 => x"84", + 489 => x"81", + 490 => x"81", + 491 => x"81", + 492 => x"84", + 493 => x"81", + 494 => x"81", + 495 => x"81", + 496 => x"84", + 497 => x"81", + 498 => x"81", + 499 => x"81", + 500 => x"84", + 501 => x"81", + 502 => x"81", + 503 => x"81", + 504 => x"84", + 505 => x"81", + 506 => x"81", + 507 => x"81", + 508 => x"84", + 509 => x"81", + 510 => x"81", + 511 => x"81", + 512 => x"84", + 513 => x"81", + 514 => x"80", + 515 => x"81", + 516 => x"84", + 517 => x"81", + 518 => x"80", + 519 => x"81", + 520 => x"84", + 521 => x"81", + 522 => x"80", + 523 => x"81", + 524 => x"84", + 525 => x"81", + 526 => x"81", + 527 => x"81", + 528 => x"84", + 529 => x"81", + 530 => x"81", + 531 => x"81", + 532 => x"84", + 533 => x"81", + 534 => x"81", + 535 => x"81", + 536 => x"84", + 537 => x"81", + 538 => x"81", + 539 => x"81", + 540 => x"84", + 541 => x"81", + 542 => x"80", + 543 => x"81", + 544 => x"84", + 545 => x"81", + 546 => x"81", + 547 => x"81", + 548 => x"84", + 549 => x"81", + 550 => x"bb", + 551 => x"de", + 552 => x"80", + 553 => x"de", + 554 => x"83", + 555 => x"cc", + 556 => x"90", + 557 => x"cc", + 558 => x"2d", + 559 => x"08", + 560 => x"04", + 561 => x"0c", + 562 => x"81", + 563 => x"84", + 564 => x"81", + 565 => x"9c", + 566 => x"de", + 567 => x"80", + 568 => x"de", + 569 => x"a0", + 570 => x"cc", + 571 => x"90", + 572 => x"cc", + 573 => x"ff", + 574 => x"cc", + 575 => x"90", + 576 => x"10", + 577 => x"10", + 578 => x"10", + 579 => x"10", + 580 => x"10", + 581 => x"10", + 582 => x"10", + 583 => x"10", + 584 => x"51", + 585 => x"73", + 586 => x"73", + 587 => x"81", + 588 => x"10", + 589 => x"07", + 590 => x"0c", + 591 => x"72", + 592 => x"81", + 593 => x"09", + 594 => x"71", + 595 => x"0a", + 596 => x"72", + 597 => x"51", + 598 => x"81", + 599 => x"81", + 600 => x"8e", + 601 => x"70", + 602 => x"0c", + 603 => x"92", + 604 => x"81", + 605 => x"be", + 606 => x"de", + 607 => x"81", + 608 => x"fd", + 609 => x"53", + 610 => x"08", + 611 => x"52", + 612 => x"08", + 613 => x"51", + 614 => x"81", + 615 => x"70", + 616 => x"0c", + 617 => x"0d", + 618 => x"0c", + 619 => x"cc", + 620 => x"de", + 621 => x"3d", + 622 => x"81", + 623 => x"8c", + 624 => x"81", + 625 => x"88", + 626 => x"83", + 627 => x"de", + 628 => x"81", + 629 => x"54", + 630 => x"81", + 631 => x"04", + 632 => x"08", + 633 => x"cc", + 634 => x"0d", + 635 => x"de", + 636 => x"05", + 637 => x"cc", + 638 => x"08", + 639 => x"38", + 640 => x"08", + 641 => x"30", + 642 => x"08", + 643 => x"80", + 644 => x"cc", + 645 => x"0c", + 646 => x"08", + 647 => x"8a", + 648 => x"81", + 649 => x"f4", + 650 => x"de", + 651 => x"05", + 652 => x"cc", + 653 => x"0c", + 654 => x"08", + 655 => x"80", + 656 => x"81", + 657 => x"8c", + 658 => x"81", + 659 => x"8c", + 660 => x"0b", + 661 => x"08", + 662 => x"81", + 663 => x"fc", + 664 => x"38", + 665 => x"de", + 666 => x"05", + 667 => x"cc", + 668 => x"08", + 669 => x"08", + 670 => x"80", + 671 => x"cc", + 672 => x"08", + 673 => x"cc", + 674 => x"08", + 675 => x"3f", + 676 => x"08", + 677 => x"cc", + 678 => x"0c", + 679 => x"cc", + 680 => x"08", + 681 => x"38", + 682 => x"08", + 683 => x"30", + 684 => x"08", + 685 => x"81", + 686 => x"f8", + 687 => x"81", + 688 => x"54", + 689 => x"81", + 690 => x"04", + 691 => x"08", + 692 => x"cc", + 693 => x"0d", + 694 => x"de", + 695 => x"05", + 696 => x"cc", + 697 => x"08", + 698 => x"38", + 699 => x"08", + 700 => x"30", + 701 => x"08", + 702 => x"81", + 703 => x"cc", + 704 => x"0c", + 705 => x"08", + 706 => x"80", + 707 => x"81", + 708 => x"8c", + 709 => x"81", + 710 => x"8c", + 711 => x"53", + 712 => x"08", + 713 => x"52", + 714 => x"08", + 715 => x"51", + 716 => x"de", + 717 => x"81", + 718 => x"f8", + 719 => x"81", + 720 => x"fc", + 721 => x"2e", + 722 => x"de", + 723 => x"05", + 724 => x"de", + 725 => x"05", + 726 => x"cc", + 727 => x"08", + 728 => x"c0", + 729 => x"3d", + 730 => x"cc", + 731 => x"de", + 732 => x"81", + 733 => x"fd", + 734 => x"0b", + 735 => x"08", + 736 => x"80", + 737 => x"cc", + 738 => x"0c", + 739 => x"08", + 740 => x"81", + 741 => x"88", + 742 => x"b9", + 743 => x"cc", + 744 => x"08", + 745 => x"38", + 746 => x"de", + 747 => x"05", + 748 => x"38", + 749 => x"08", + 750 => x"10", + 751 => x"08", + 752 => x"81", + 753 => x"fc", + 754 => x"81", + 755 => x"fc", + 756 => x"b8", + 757 => x"cc", + 758 => x"08", + 759 => x"e1", + 760 => x"cc", + 761 => x"08", + 762 => x"08", + 763 => x"26", + 764 => x"de", + 765 => x"05", + 766 => x"cc", + 767 => x"08", + 768 => x"cc", + 769 => x"0c", + 770 => x"08", + 771 => x"81", + 772 => x"fc", + 773 => x"81", + 774 => x"f8", + 775 => x"de", + 776 => x"05", + 777 => x"81", + 778 => x"fc", + 779 => x"de", + 780 => x"05", + 781 => x"81", + 782 => x"8c", + 783 => x"95", + 784 => x"cc", + 785 => x"08", + 786 => x"38", + 787 => x"08", + 788 => x"70", + 789 => x"08", + 790 => x"51", + 791 => x"de", + 792 => x"05", + 793 => x"de", + 794 => x"05", + 795 => x"de", + 796 => x"05", + 797 => x"c0", + 798 => x"0d", + 799 => x"0c", + 800 => x"0d", + 801 => x"02", + 802 => x"05", + 803 => x"53", + 804 => x"27", + 805 => x"83", + 806 => x"80", + 807 => x"ff", + 808 => x"ff", + 809 => x"73", + 810 => x"05", + 811 => x"12", + 812 => x"2e", + 813 => x"ef", + 814 => x"de", + 815 => x"3d", + 816 => x"74", + 817 => x"07", + 818 => x"2b", + 819 => x"51", + 820 => x"a5", + 821 => x"70", + 822 => x"0c", + 823 => x"84", + 824 => x"72", + 825 => x"05", + 826 => x"71", + 827 => x"53", + 828 => x"52", + 829 => x"dd", + 830 => x"27", + 831 => x"71", + 832 => x"53", + 833 => x"52", + 834 => x"f2", + 835 => x"ff", + 836 => x"3d", + 837 => x"70", + 838 => x"06", + 839 => x"70", + 840 => x"73", + 841 => x"56", + 842 => x"08", + 843 => x"38", + 844 => x"52", + 845 => x"81", + 846 => x"54", + 847 => x"9d", + 848 => x"55", + 849 => x"09", + 850 => x"38", + 851 => x"14", + 852 => x"81", + 853 => x"56", + 854 => x"e5", + 855 => x"55", + 856 => x"06", + 857 => x"06", + 858 => x"81", + 859 => x"52", + 860 => x"0d", + 861 => x"70", + 862 => x"ff", + 863 => x"f8", + 864 => x"80", + 865 => x"51", + 866 => x"84", + 867 => x"71", + 868 => x"54", + 869 => x"2e", + 870 => x"75", + 871 => x"94", + 872 => x"81", + 873 => x"87", + 874 => x"fe", + 875 => x"52", + 876 => x"88", + 877 => x"86", + 878 => x"c0", + 879 => x"06", + 880 => x"14", + 881 => x"80", + 882 => x"71", + 883 => x"0c", + 884 => x"04", + 885 => x"77", + 886 => x"53", + 887 => x"80", + 888 => x"38", + 889 => x"70", + 890 => x"81", + 891 => x"81", + 892 => x"39", + 893 => x"39", + 894 => x"80", + 895 => x"81", + 896 => x"55", + 897 => x"2e", + 898 => x"55", + 899 => x"84", + 900 => x"38", + 901 => x"06", + 902 => x"2e", + 903 => x"88", + 904 => x"70", + 905 => x"34", + 906 => x"71", + 907 => x"de", + 908 => x"3d", + 909 => x"3d", + 910 => x"72", + 911 => x"91", + 912 => x"fc", + 913 => x"51", + 914 => x"81", + 915 => x"85", + 916 => x"83", + 917 => x"72", + 918 => x"0c", + 919 => x"04", + 920 => x"76", + 921 => x"ff", + 922 => x"81", + 923 => x"26", + 924 => x"83", + 925 => x"05", + 926 => x"70", + 927 => x"8a", + 928 => x"33", + 929 => x"70", + 930 => x"fe", + 931 => x"33", + 932 => x"70", + 933 => x"f2", + 934 => x"33", + 935 => x"70", + 936 => x"e6", + 937 => x"22", + 938 => x"74", + 939 => x"80", + 940 => x"13", + 941 => x"52", + 942 => x"26", + 943 => x"81", + 944 => x"98", + 945 => x"22", + 946 => x"bc", + 947 => x"33", + 948 => x"b8", + 949 => x"33", + 950 => x"b4", + 951 => x"33", + 952 => x"b0", + 953 => x"33", + 954 => x"ac", + 955 => x"33", + 956 => x"a8", + 957 => x"c0", + 958 => x"73", + 959 => x"a0", + 960 => x"87", + 961 => x"0c", + 962 => x"81", + 963 => x"86", + 964 => x"f3", + 965 => x"5b", + 966 => x"9c", + 967 => x"0c", + 968 => x"bc", + 969 => x"7b", + 970 => x"98", + 971 => x"79", + 972 => x"87", + 973 => x"08", + 974 => x"1c", + 975 => x"98", + 976 => x"79", + 977 => x"87", + 978 => x"08", + 979 => x"1c", + 980 => x"98", + 981 => x"79", + 982 => x"87", + 983 => x"08", + 984 => x"1c", + 985 => x"98", + 986 => x"79", + 987 => x"80", + 988 => x"83", + 989 => x"59", + 990 => x"ff", + 991 => x"1b", + 992 => x"1b", + 993 => x"1b", + 994 => x"1b", + 995 => x"1b", + 996 => x"83", + 997 => x"52", + 998 => x"51", + 999 => x"8f", + 1000 => x"ff", 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x"94", + 1060 => x"80", + 1061 => x"87", + 1062 => x"52", + 1063 => x"87", + 1064 => x"f9", + 1065 => x"54", + 1066 => x"70", + 1067 => x"53", + 1068 => x"77", + 1069 => x"38", + 1070 => x"06", + 1071 => x"0b", + 1072 => x"33", + 1073 => x"06", + 1074 => x"58", + 1075 => x"84", + 1076 => x"2e", + 1077 => x"c0", + 1078 => x"70", + 1079 => x"2a", + 1080 => x"53", + 1081 => x"80", + 1082 => x"71", + 1083 => x"81", + 1084 => x"70", + 1085 => x"81", + 1086 => x"06", + 1087 => x"80", + 1088 => x"71", + 1089 => x"81", + 1090 => x"70", + 1091 => x"74", + 1092 => x"51", + 1093 => x"80", + 1094 => x"2e", + 1095 => x"c0", + 1096 => x"77", + 1097 => x"17", + 1098 => x"81", + 1099 => x"53", + 1100 => x"84", + 1101 => x"de", + 1102 => x"3d", + 1103 => x"3d", + 1104 => x"81", + 1105 => x"70", + 1106 => x"54", + 1107 => x"94", + 1108 => x"80", + 1109 => x"87", + 1110 => x"51", + 1111 => x"82", + 1112 => x"06", + 1113 => x"70", + 1114 => x"38", + 1115 => x"06", + 1116 => x"94", + 1117 => x"80", + 1118 => x"87", + 1119 => x"52", + 1120 => x"81", + 1121 => x"de", + 1122 => x"84", + 1123 => x"fe", + 1124 => x"0b", + 1125 => x"33", + 1126 => x"06", + 1127 => x"c0", + 1128 => x"70", + 1129 => x"38", + 1130 => x"94", + 1131 => x"70", + 1132 => x"81", + 1133 => x"51", + 1134 => x"80", + 1135 => x"72", + 1136 => x"51", + 1137 => x"80", + 1138 => x"2e", + 1139 => x"c0", + 1140 => x"71", + 1141 => x"2b", + 1142 => x"51", + 1143 => x"81", + 1144 => x"84", + 1145 => x"ff", + 1146 => x"c0", + 1147 => x"70", + 1148 => x"06", + 1149 => x"80", + 1150 => x"38", + 1151 => x"a4", + 1152 => x"8c", + 1153 => x"9e", + 1154 => x"db", + 1155 => x"c0", + 1156 => x"81", + 1157 => x"87", + 1158 => x"08", + 1159 => x"0c", + 1160 => x"9c", + 1161 => x"9c", + 1162 => x"9e", + 1163 => x"db", + 1164 => x"c0", + 1165 => x"81", + 1166 => x"87", + 1167 => x"08", + 1168 => x"0c", + 1169 => x"b4", + 1170 => x"ac", + 1171 => x"9e", + 1172 => x"db", + 1173 => x"c0", + 1174 => x"81", + 1175 => x"87", + 1176 => x"08", + 1177 => x"0c", + 1178 => x"c4", + 1179 => x"bc", + 1180 => x"9e", + 1181 => x"70", + 1182 => x"23", + 1183 => x"84", + 1184 => x"c4", + 1185 => x"9e", + 1186 => x"db", + 1187 => x"c0", + 1188 => x"81", + 1189 => x"81", + 1190 => x"d0", + 1191 => x"87", + 1192 => x"08", + 1193 => x"0a", + 1194 => x"52", + 1195 => x"83", + 1196 => x"71", + 1197 => x"34", + 1198 => x"c0", + 1199 => x"70", + 1200 => x"06", + 1201 => x"70", + 1202 => x"38", + 1203 => x"81", + 1204 => x"80", + 1205 => x"9e", + 1206 => x"90", + 1207 => x"51", + 1208 => x"80", + 1209 => x"81", + 1210 => x"db", + 1211 => x"0b", + 1212 => x"90", + 1213 => x"80", + 1214 => x"52", + 1215 => x"2e", + 1216 => x"52", + 1217 => x"d4", + 1218 => x"87", + 1219 => x"08", + 1220 => x"80", + 1221 => x"52", + 1222 => x"83", + 1223 => x"71", + 1224 => x"34", + 1225 => x"c0", + 1226 => x"70", + 1227 => x"06", + 1228 => x"70", + 1229 => x"38", + 1230 => x"81", + 1231 => x"80", + 1232 => x"9e", + 1233 => x"84", + 1234 => x"51", + 1235 => x"80", + 1236 => x"81", + 1237 => x"db", + 1238 => x"0b", + 1239 => x"90", + 1240 => x"80", + 1241 => x"52", + 1242 => x"2e", + 1243 => x"52", + 1244 => x"d8", + 1245 => x"87", + 1246 => x"08", + 1247 => x"80", + 1248 => x"52", + 1249 => x"83", + 1250 => x"71", + 1251 => x"34", + 1252 => x"c0", + 1253 => x"70", + 1254 => x"06", + 1255 => x"70", + 1256 => x"38", + 1257 => x"81", + 1258 => x"80", + 1259 => x"9e", + 1260 => x"a0", + 1261 => x"52", + 1262 => x"2e", + 1263 => x"52", + 1264 => x"db", + 1265 => x"9e", + 1266 => x"98", + 1267 => x"8a", + 1268 => x"51", + 1269 => x"dc", + 1270 => x"87", + 1271 => x"08", + 1272 => x"06", + 1273 => x"70", + 1274 => x"38", + 1275 => x"81", + 1276 => x"87", + 1277 => x"08", + 1278 => x"06", + 1279 => x"51", + 1280 => x"81", + 1281 => x"80", + 1282 => x"9e", + 1283 => x"88", + 1284 => x"52", + 1285 => x"83", + 1286 => x"71", + 1287 => x"34", + 1288 => x"90", + 1289 => x"06", + 1290 => x"81", + 1291 => x"83", + 1292 => x"fb", + 1293 => x"c6", + 1294 => x"86", + 1295 => x"d0", + 1296 => x"80", + 1297 => x"81", + 1298 => x"85", + 1299 => x"c7", + 1300 => x"ee", + 1301 => x"d2", + 1302 => x"80", + 1303 => x"81", + 1304 => x"81", + 1305 => x"11", + 1306 => x"c7", + 1307 => x"b6", + 1308 => x"d7", + 1309 => x"80", + 1310 => x"81", + 1311 => x"81", + 1312 => x"11", + 1313 => x"c7", + 1314 => x"9a", + 1315 => x"d4", + 1316 => x"80", + 1317 => x"81", + 1318 => x"81", + 1319 => x"11", + 1320 => x"c7", + 1321 => x"fe", + 1322 => x"d5", + 1323 => x"80", + 1324 => x"81", + 1325 => x"81", + 1326 => x"11", + 1327 => x"c8", + 1328 => x"e2", + 1329 => x"d6", + 1330 => x"80", + 1331 => x"81", + 1332 => x"81", + 1333 => x"11", + 1334 => x"c8", + 1335 => x"c6", + 1336 => x"db", + 1337 => x"80", + 1338 => x"81", + 1339 => x"52", + 1340 => x"51", + 1341 => x"81", + 1342 => x"54", + 1343 => x"8d", + 1344 => x"e0", + 1345 => x"c8", + 1346 => x"9a", + 1347 => x"dd", + 1348 => x"80", + 1349 => x"81", + 1350 => x"52", + 1351 => x"51", + 1352 => x"81", + 1353 => x"54", + 1354 => x"88", + 1355 => x"a8", + 1356 => x"3f", + 1357 => x"33", + 1358 => x"2e", + 1359 => x"c9", + 1360 => x"fe", + 1361 => x"d8", + 1362 => x"80", + 1363 => x"81", + 1364 => x"83", + 1365 => x"db", + 1366 => x"73", + 1367 => x"38", + 1368 => x"51", + 1369 => x"81", + 1370 => x"54", + 1371 => x"88", + 1372 => x"e0", + 1373 => x"3f", + 1374 => x"51", + 1375 => x"81", + 1376 => x"52", + 1377 => x"51", + 1378 => x"81", + 1379 => x"52", + 1380 => x"51", + 1381 => x"81", + 1382 => x"52", + 1383 => x"51", + 1384 => x"81", + 1385 => x"f5", + 1386 => x"db", + 1387 => x"81", + 1388 => x"88", + 1389 => x"db", + 1390 => x"bd", + 1391 => x"75", + 1392 => x"3f", + 1393 => x"08", + 1394 => x"29", + 1395 => x"54", + 1396 => x"c0", + 1397 => x"cb", + 1398 => x"ca", + 1399 => x"d7", + 1400 => x"80", + 1401 => x"81", + 1402 => x"56", + 1403 => x"52", + 1404 => x"86", + 1405 => x"c0", + 1406 => x"c0", + 1407 => x"31", + 1408 => x"de", + 1409 => x"81", + 1410 => x"88", + 1411 => x"db", + 1412 => x"73", + 1413 => x"38", + 1414 => x"08", + 1415 => x"c0", + 1416 => x"e6", + 1417 => x"de", + 1418 => x"84", + 1419 => x"71", + 1420 => x"81", + 1421 => x"52", + 1422 => x"51", + 1423 => x"81", + 1424 => x"81", + 1425 => x"3d", + 1426 => x"3d", + 1427 => x"05", + 1428 => x"52", + 1429 => x"aa", + 1430 => x"29", + 1431 => x"05", + 1432 => x"04", + 1433 => x"51", + 1434 => x"cc", + 1435 => x"39", + 1436 => x"51", + 1437 => x"cc", + 1438 => x"39", + 1439 => x"51", + 1440 => x"cc", + 1441 => x"9b", + 1442 => x"0d", + 1443 => x"80", + 1444 => x"0b", + 1445 => x"84", + 1446 => x"3d", + 1447 => x"96", + 1448 => x"52", + 1449 => x"0c", + 1450 => x"70", + 1451 => x"0c", + 1452 => x"3d", + 1453 => x"3d", + 1454 => x"96", + 1455 => x"81", + 1456 => x"52", + 1457 => x"73", + 1458 => x"db", + 1459 => x"70", + 1460 => x"0c", + 1461 => x"83", + 1462 => x"81", + 1463 => x"87", + 1464 => x"0c", + 1465 => x"0d", + 1466 => x"33", + 1467 => x"2e", + 1468 => x"85", + 1469 => x"ed", + 1470 => x"d8", + 1471 => x"80", + 1472 => x"72", + 1473 => x"de", + 1474 => x"05", + 1475 => x"0c", + 1476 => x"de", + 1477 => x"71", + 1478 => x"38", + 1479 => x"2d", + 1480 => x"04", + 1481 => x"02", + 1482 => x"81", + 1483 => x"76", + 1484 => x"0c", + 1485 => x"ad", + 1486 => x"de", + 1487 => x"3d", + 1488 => x"3d", + 1489 => x"73", + 1490 => x"ff", + 1491 => x"71", + 1492 => x"38", + 1493 => x"06", + 1494 => x"54", + 1495 => x"e7", + 1496 => x"0d", + 1497 => x"0d", + 1498 => x"d0", + 1499 => x"de", + 1500 => x"54", + 1501 => x"81", + 1502 => x"53", + 1503 => x"8e", + 1504 => x"ff", + 1505 => x"14", + 1506 => x"3f", + 1507 => x"81", + 1508 => x"86", + 1509 => x"ec", + 1510 => x"68", + 1511 => x"70", + 1512 => x"33", + 1513 => x"2e", + 1514 => x"75", + 1515 => x"81", + 1516 => x"38", + 1517 => x"70", + 1518 => x"33", + 1519 => x"75", + 1520 => x"81", + 1521 => x"81", + 1522 => x"75", + 1523 => x"81", + 1524 => x"82", + 1525 => x"81", + 1526 => x"56", + 1527 => x"09", + 1528 => x"38", + 1529 => x"71", + 1530 => x"81", + 1531 => x"59", + 1532 => x"9d", + 1533 => x"53", + 1534 => x"95", + 1535 => x"29", + 1536 => x"76", + 1537 => x"79", + 1538 => x"5b", + 1539 => x"e5", + 1540 => x"ec", + 1541 => x"70", + 1542 => x"25", + 1543 => x"32", + 1544 => x"72", + 1545 => x"73", + 1546 => x"58", + 1547 => x"73", + 1548 => x"38", + 1549 => x"79", + 1550 => x"5b", + 1551 => x"75", + 1552 => x"de", + 1553 => x"80", + 1554 => x"89", + 1555 => x"70", + 1556 => x"55", + 1557 => x"cf", + 1558 => x"38", + 1559 => x"24", + 1560 => x"80", + 1561 => x"8e", + 1562 => x"c3", + 1563 => x"73", + 1564 => x"81", + 1565 => x"99", + 1566 => x"c4", + 1567 => x"38", + 1568 => x"73", + 1569 => x"81", + 1570 => x"80", + 1571 => x"38", + 1572 => x"2e", + 1573 => x"f9", + 1574 => x"d8", + 1575 => x"38", + 1576 => x"77", + 1577 => x"08", + 1578 => x"80", + 1579 => x"55", + 1580 => x"8d", + 1581 => x"70", + 1582 => x"51", + 1583 => x"f5", + 1584 => x"2a", + 1585 => x"74", + 1586 => x"53", + 1587 => x"8f", + 1588 => x"fc", + 1589 => x"81", + 1590 => x"80", + 1591 => x"73", + 1592 => x"3f", + 1593 => x"56", + 1594 => x"27", + 1595 => x"a0", + 1596 => x"3f", + 1597 => x"84", + 1598 => x"33", + 1599 => x"93", + 1600 => x"95", + 1601 => x"91", + 1602 => x"8d", + 1603 => x"89", + 1604 => x"fb", + 1605 => x"86", + 1606 => x"2a", + 1607 => x"51", + 1608 => x"2e", + 1609 => x"84", + 1610 => x"86", + 1611 => x"78", + 1612 => x"08", + 1613 => x"32", + 1614 => x"72", + 1615 => x"51", + 1616 => x"74", + 1617 => x"38", + 1618 => x"88", + 1619 => x"7a", + 1620 => x"55", + 1621 => x"3d", + 1622 => x"52", + 1623 => x"cd", + 1624 => x"c0", + 1625 => x"06", + 1626 => x"52", + 1627 => x"3f", + 1628 => x"08", + 1629 => x"27", + 1630 => x"14", + 1631 => x"f8", + 1632 => x"87", + 1633 => x"81", + 1634 => x"b0", + 1635 => x"7d", + 1636 => x"5f", + 1637 => x"75", + 1638 => x"07", + 1639 => x"54", + 1640 => x"26", + 1641 => x"ff", + 1642 => x"84", + 1643 => x"06", + 1644 => x"80", + 1645 => x"96", + 1646 => x"e0", + 1647 => x"73", + 1648 => x"57", + 1649 => x"06", + 1650 => x"54", + 1651 => x"a0", + 1652 => x"2a", + 1653 => x"54", + 1654 => x"38", + 1655 => x"76", + 1656 => x"38", + 1657 => x"fd", + 1658 => x"06", + 1659 => x"38", + 1660 => x"56", + 1661 => x"26", + 1662 => x"3d", + 1663 => x"05", + 1664 => x"ff", + 1665 => x"53", + 1666 => x"d9", + 1667 => x"38", + 1668 => x"56", + 1669 => x"27", + 1670 => x"a0", + 1671 => x"3f", + 1672 => x"3d", + 1673 => x"3d", + 1674 => x"70", + 1675 => x"52", + 1676 => x"73", + 1677 => x"3f", + 1678 => x"04", + 1679 => x"74", + 1680 => x"0c", + 1681 => x"05", + 1682 => x"fa", + 1683 => x"de", + 1684 => x"80", + 1685 => x"0b", + 1686 => x"0c", + 1687 => x"04", + 1688 => x"81", + 1689 => x"76", + 1690 => x"0c", + 1691 => x"05", + 1692 => x"53", + 1693 => x"72", + 1694 => x"0c", + 1695 => x"04", + 1696 => x"77", + 1697 => x"d4", + 1698 => x"54", + 1699 => x"54", + 1700 => x"80", + 1701 => x"de", + 1702 => x"71", + 1703 => x"c0", + 1704 => x"06", + 1705 => x"2e", + 1706 => x"72", + 1707 => x"38", + 1708 => x"70", + 1709 => x"25", + 1710 => x"73", + 1711 => x"38", + 1712 => x"86", + 1713 => x"54", + 1714 => x"73", + 1715 => x"ff", + 1716 => x"72", + 1717 => x"74", + 1718 => x"72", + 1719 => x"54", + 1720 => x"81", + 1721 => x"39", + 1722 => x"80", + 1723 => x"51", + 1724 => x"81", + 1725 => x"de", + 1726 => x"3d", + 1727 => x"3d", + 1728 => x"d4", + 1729 => x"de", + 1730 => x"53", + 1731 => x"fe", + 1732 => x"81", + 1733 => x"84", + 1734 => x"f8", + 1735 => x"7c", + 1736 => x"70", + 1737 => x"75", + 1738 => x"55", + 1739 => x"2e", + 1740 => x"87", + 1741 => x"76", + 1742 => x"73", + 1743 => x"81", + 1744 => x"81", + 1745 => x"77", + 1746 => x"70", + 1747 => x"58", + 1748 => x"09", + 1749 => x"c2", + 1750 => x"81", + 1751 => x"75", + 1752 => x"55", + 1753 => x"e2", + 1754 => x"90", + 1755 => x"f8", + 1756 => x"8f", + 1757 => x"81", + 1758 => x"75", + 1759 => x"55", + 1760 => x"81", + 1761 => x"27", + 1762 => x"d0", + 1763 => x"55", + 1764 => x"73", + 1765 => x"80", + 1766 => x"14", + 1767 => x"72", + 1768 => x"e0", + 1769 => x"80", + 1770 => x"39", + 1771 => x"55", + 1772 => x"80", + 1773 => x"e0", + 1774 => x"38", + 1775 => x"81", + 1776 => x"53", + 1777 => x"81", + 1778 => x"53", + 1779 => x"8e", + 1780 => x"70", + 1781 => x"55", + 1782 => x"27", + 1783 => x"77", + 1784 => x"74", + 1785 => x"76", + 1786 => x"77", + 1787 => x"70", + 1788 => x"55", + 1789 => x"77", + 1790 => x"38", + 1791 => x"74", + 1792 => x"55", + 1793 => x"c0", + 1794 => x"0d", + 1795 => x"0d", + 1796 => x"56", + 1797 => x"0c", + 1798 => x"70", + 1799 => x"73", + 1800 => x"81", + 1801 => x"81", + 1802 => x"ed", + 1803 => x"2e", + 1804 => x"8e", + 1805 => x"08", + 1806 => x"76", + 1807 => x"56", + 1808 => x"b0", + 1809 => x"06", + 1810 => x"75", + 1811 => x"76", + 1812 => x"70", + 1813 => x"73", + 1814 => x"8b", + 1815 => x"73", + 1816 => x"85", + 1817 => x"82", + 1818 => x"76", + 1819 => x"70", + 1820 => x"ac", + 1821 => x"a0", + 1822 => x"fa", + 1823 => x"53", + 1824 => x"57", + 1825 => x"98", + 1826 => x"39", + 1827 => x"80", + 1828 => x"26", + 1829 => x"86", + 1830 => x"80", + 1831 => x"57", + 1832 => x"74", + 1833 => x"38", + 1834 => x"27", + 1835 => x"14", + 1836 => x"06", + 1837 => x"14", + 1838 => x"06", + 1839 => x"74", + 1840 => x"f9", + 1841 => x"ff", + 1842 => x"89", + 1843 => x"38", + 1844 => x"c5", + 1845 => x"29", + 1846 => x"81", + 1847 => x"76", + 1848 => x"56", + 1849 => x"ba", + 1850 => x"2e", + 1851 => x"30", + 1852 => x"0c", + 1853 => x"81", + 1854 => x"8a", + 1855 => x"ff", + 1856 => x"8f", + 1857 => x"81", + 1858 => x"26", + 1859 => x"db", + 1860 => x"52", + 1861 => x"c0", + 1862 => x"0d", + 1863 => x"0d", + 1864 => x"33", + 1865 => x"9f", + 1866 => x"53", + 1867 => x"81", + 1868 => x"38", + 1869 => x"87", + 1870 => x"11", + 1871 => x"54", + 1872 => x"84", + 1873 => x"54", + 1874 => x"87", + 1875 => x"11", + 1876 => x"0c", + 1877 => x"c0", + 1878 => x"70", + 1879 => x"70", + 1880 => x"51", + 1881 => x"8a", + 1882 => x"98", + 1883 => x"70", + 1884 => x"08", + 1885 => x"06", + 1886 => x"38", + 1887 => x"8c", + 1888 => x"80", + 1889 => x"71", + 1890 => x"14", + 1891 => x"e8", + 1892 => x"70", + 1893 => x"0c", + 1894 => x"04", + 1895 => x"60", + 1896 => x"8c", + 1897 => x"33", + 1898 => x"5b", + 1899 => x"5a", + 1900 => x"81", + 1901 => x"81", + 1902 => x"52", + 1903 => x"38", + 1904 => x"84", + 1905 => x"92", + 1906 => x"c0", + 1907 => x"87", + 1908 => x"13", + 1909 => x"57", + 1910 => x"0b", + 1911 => x"8c", + 1912 => x"0c", + 1913 => x"75", + 1914 => x"2a", + 1915 => x"51", + 1916 => x"80", + 1917 => x"7b", + 1918 => x"7b", + 1919 => x"5d", + 1920 => x"59", + 1921 => x"06", + 1922 => x"73", + 1923 => x"81", + 1924 => x"ff", + 1925 => x"72", + 1926 => x"38", + 1927 => x"8c", + 1928 => x"c3", + 1929 => x"98", + 1930 => x"71", + 1931 => x"38", + 1932 => x"2e", + 1933 => x"76", + 1934 => x"92", + 1935 => x"72", + 1936 => x"06", + 1937 => x"f7", + 1938 => x"5a", + 1939 => x"80", + 1940 => x"70", + 1941 => x"5a", + 1942 => x"80", + 1943 => x"73", + 1944 => x"06", + 1945 => x"38", + 1946 => x"fe", + 1947 => x"fc", + 1948 => x"52", + 1949 => x"83", + 1950 => x"71", + 1951 => x"de", + 1952 => x"3d", + 1953 => x"3d", + 1954 => x"64", + 1955 => x"bf", + 1956 => x"40", + 1957 => x"59", + 1958 => x"58", + 1959 => x"81", + 1960 => x"81", + 1961 => x"52", + 1962 => x"09", + 1963 => x"b1", + 1964 => x"84", + 1965 => x"92", + 1966 => x"c0", + 1967 => x"87", + 1968 => x"13", + 1969 => x"56", + 1970 => x"87", + 1971 => x"0c", + 1972 => x"82", + 1973 => x"58", + 1974 => x"84", + 1975 => x"06", + 1976 => x"71", + 1977 => x"38", + 1978 => x"05", + 1979 => x"0c", + 1980 => x"73", + 1981 => x"81", + 1982 => x"71", + 1983 => x"38", + 1984 => x"8c", + 1985 => x"d0", + 1986 => x"98", + 1987 => x"71", + 1988 => x"38", + 1989 => x"2e", + 1990 => x"76", + 1991 => x"92", + 1992 => x"72", + 1993 => x"06", + 1994 => x"f7", + 1995 => x"59", + 1996 => x"1a", + 1997 => x"06", + 1998 => x"59", + 1999 => x"80", + 2000 => x"73", + 2001 => x"06", + 2002 => x"38", + 2003 => x"fe", + 2004 => x"fc", + 2005 => x"52", + 2006 => x"83", + 2007 => x"71", + 2008 => x"de", + 2009 => x"3d", + 2010 => x"3d", + 2011 => x"84", + 2012 => x"33", + 2013 => x"b7", + 2014 => x"54", + 2015 => x"fa", + 2016 => x"de", + 2017 => x"06", + 2018 => x"72", + 2019 => x"85", + 2020 => x"98", + 2021 => x"56", + 2022 => x"80", + 2023 => x"76", + 2024 => x"74", + 2025 => x"c0", + 2026 => x"54", + 2027 => x"2e", + 2028 => x"d4", + 2029 => x"2e", + 2030 => x"80", + 2031 => x"08", + 2032 => x"70", + 2033 => x"51", + 2034 => x"2e", + 2035 => x"c0", + 2036 => x"52", + 2037 => x"87", + 2038 => x"08", + 2039 => x"38", + 2040 => x"87", + 2041 => x"14", + 2042 => x"70", + 2043 => x"52", + 2044 => x"96", + 2045 => x"92", + 2046 => x"0a", + 2047 => x"39", + 2048 => x"0c", + 2049 => x"39", + 2050 => x"54", + 2051 => x"c0", + 2052 => x"0d", + 2053 => x"0d", + 2054 => x"33", + 2055 => x"88", + 2056 => x"de", + 2057 => x"51", + 2058 => x"04", + 2059 => x"75", + 2060 => x"82", + 2061 => x"90", + 2062 => x"2b", + 2063 => x"33", + 2064 => x"88", + 2065 => x"71", + 2066 => x"c0", + 2067 => x"54", + 2068 => x"85", + 2069 => x"ff", + 2070 => x"02", + 2071 => x"05", + 2072 => x"70", + 2073 => x"05", + 2074 => x"88", + 2075 => x"72", + 2076 => x"0d", + 2077 => x"0d", + 2078 => x"52", + 2079 => x"81", + 2080 => x"70", + 2081 => x"70", + 2082 => x"05", + 2083 => x"88", + 2084 => x"72", + 2085 => x"54", + 2086 => x"2a", + 2087 => x"34", + 2088 => x"04", + 2089 => x"76", + 2090 => x"54", + 2091 => x"2e", + 2092 => x"70", + 2093 => x"33", + 2094 => x"05", + 2095 => x"11", + 2096 => x"84", + 2097 => x"fe", + 2098 => x"77", + 2099 => x"53", + 2100 => x"81", + 2101 => x"ff", + 2102 => x"f4", + 2103 => x"0d", + 2104 => x"0d", + 2105 => x"56", + 2106 => x"70", + 2107 => x"33", + 2108 => x"05", + 2109 => x"71", + 2110 => x"56", + 2111 => x"72", + 2112 => x"38", + 2113 => x"e2", + 2114 => x"de", + 2115 => x"3d", + 2116 => x"3d", + 2117 => x"54", + 2118 => x"71", + 2119 => x"38", + 2120 => x"70", + 2121 => x"f3", + 2122 => x"81", + 2123 => x"84", + 2124 => x"80", + 2125 => x"c0", + 2126 => x"0b", + 2127 => x"0c", + 2128 => x"0d", + 2129 => x"0b", + 2130 => x"56", + 2131 => x"2e", + 2132 => x"81", + 2133 => x"08", + 2134 => x"70", + 2135 => x"33", + 2136 => x"a2", + 2137 => x"c0", + 2138 => x"09", + 2139 => x"38", + 2140 => x"08", + 2141 => x"b0", + 2142 => x"a4", + 2143 => x"9c", + 2144 => x"56", + 2145 => x"27", + 2146 => x"16", + 2147 => x"82", + 2148 => x"06", + 2149 => x"54", + 2150 => x"78", + 2151 => x"33", + 2152 => x"3f", + 2153 => x"5a", + 2154 => x"c0", + 2155 => x"0d", + 2156 => x"0d", + 2157 => x"56", + 2158 => x"b0", + 2159 => x"af", + 2160 => x"fe", + 2161 => x"de", + 2162 => x"81", + 2163 => x"9f", + 2164 => x"74", + 2165 => x"52", + 2166 => x"51", + 2167 => x"81", + 2168 => x"80", + 2169 => x"ff", + 2170 => x"74", + 2171 => x"76", + 2172 => x"0c", + 2173 => x"04", + 2174 => x"7a", + 2175 => x"fe", + 2176 => x"de", + 2177 => x"81", + 2178 => x"81", + 2179 => x"33", + 2180 => x"2e", + 2181 => x"80", + 2182 => x"17", + 2183 => x"81", + 2184 => x"06", + 2185 => x"84", + 2186 => x"de", + 2187 => x"b4", + 2188 => x"56", + 2189 => x"82", + 2190 => x"84", + 2191 => x"fc", + 2192 => x"8b", + 2193 => x"52", + 2194 => x"a9", + 2195 => x"85", + 2196 => x"84", + 2197 => x"fc", + 2198 => x"17", + 2199 => x"9c", + 2200 => x"91", + 2201 => x"08", + 2202 => x"17", + 2203 => x"3f", + 2204 => x"81", + 2205 => x"19", + 2206 => x"53", + 2207 => x"17", + 2208 => x"82", + 2209 => x"18", + 2210 => x"80", + 2211 => x"33", + 2212 => x"3f", + 2213 => x"08", + 2214 => x"38", + 2215 => x"81", + 2216 => x"8a", + 2217 => x"fb", + 2218 => x"fe", + 2219 => x"08", + 2220 => x"56", + 2221 => x"74", + 2222 => x"38", + 2223 => x"75", + 2224 => x"16", + 2225 => x"53", + 2226 => x"c0", + 2227 => x"0d", + 2228 => x"0d", + 2229 => x"08", + 2230 => x"81", + 2231 => x"df", + 2232 => x"15", + 2233 => x"d7", + 2234 => x"33", + 2235 => x"82", + 2236 => x"38", + 2237 => x"89", + 2238 => x"2e", + 2239 => x"bf", + 2240 => x"2e", + 2241 => x"81", + 2242 => x"81", + 2243 => x"89", + 2244 => x"08", + 2245 => x"52", + 2246 => x"3f", + 2247 => x"08", + 2248 => x"74", + 2249 => x"14", + 2250 => x"81", + 2251 => x"2a", + 2252 => x"05", + 2253 => x"57", + 2254 => x"f5", + 2255 => x"c0", + 2256 => x"38", + 2257 => x"06", + 2258 => x"33", + 2259 => x"78", + 2260 => x"06", + 2261 => x"5c", + 2262 => x"53", + 2263 => x"38", + 2264 => x"06", + 2265 => x"39", + 2266 => x"a4", + 2267 => x"52", + 2268 => x"bd", + 2269 => x"c0", + 2270 => x"38", + 2271 => x"fe", + 2272 => x"b4", + 2273 => x"8d", + 2274 => x"c0", + 2275 => x"ff", + 2276 => x"39", + 2277 => x"a4", + 2278 => x"52", + 2279 => x"91", + 2280 => x"c0", + 2281 => x"76", + 2282 => x"fc", + 2283 => x"b4", + 2284 => x"f8", + 2285 => x"c0", + 2286 => x"06", + 2287 => x"81", + 2288 => x"de", + 2289 => x"3d", + 2290 => x"3d", + 2291 => x"7e", + 2292 => x"82", + 2293 => x"27", + 2294 => x"76", + 2295 => x"27", + 2296 => x"75", + 2297 => x"79", + 2298 => x"38", + 2299 => x"89", + 2300 => x"2e", + 2301 => x"80", + 2302 => x"2e", + 2303 => x"81", + 2304 => x"81", + 2305 => x"89", + 2306 => x"08", + 2307 => x"52", + 2308 => x"3f", + 2309 => x"08", + 2310 => x"c0", + 2311 => x"38", + 2312 => x"06", + 2313 => x"81", + 2314 => x"06", + 2315 => x"77", + 2316 => x"2e", + 2317 => x"84", + 2318 => x"06", + 2319 => x"06", + 2320 => x"53", + 2321 => x"81", + 2322 => x"34", + 2323 => x"a4", + 2324 => x"52", + 2325 => x"d9", + 2326 => x"c0", + 2327 => x"de", + 2328 => x"94", + 2329 => x"ff", + 2330 => x"05", + 2331 => x"54", + 2332 => x"38", + 2333 => x"74", + 2334 => x"06", + 2335 => x"07", + 2336 => x"74", + 2337 => x"39", + 2338 => x"a4", + 2339 => x"52", + 2340 => x"9d", + 2341 => x"c0", + 2342 => x"de", + 2343 => x"d8", + 2344 => x"ff", + 2345 => x"76", + 2346 => x"06", + 2347 => x"05", + 2348 => x"3f", + 2349 => x"87", + 2350 => x"08", + 2351 => x"51", + 2352 => x"81", + 2353 => x"59", + 2354 => x"08", + 2355 => x"f0", + 2356 => x"82", + 2357 => x"06", + 2358 => x"05", + 2359 => x"54", + 2360 => x"3f", + 2361 => x"08", + 2362 => x"74", + 2363 => x"51", + 2364 => x"81", + 2365 => x"34", + 2366 => x"c0", + 2367 => x"0d", + 2368 => x"0d", + 2369 => x"72", + 2370 => x"56", + 2371 => x"27", + 2372 => x"98", + 2373 => x"9d", + 2374 => x"2e", + 2375 => x"53", + 2376 => x"51", + 2377 => x"81", + 2378 => x"54", + 2379 => x"08", + 2380 => x"93", + 2381 => x"80", + 2382 => x"54", + 2383 => x"81", + 2384 => x"54", + 2385 => x"74", + 2386 => x"fb", + 2387 => x"de", + 2388 => x"81", + 2389 => x"80", + 2390 => x"38", + 2391 => x"08", + 2392 => x"38", + 2393 => x"08", + 2394 => x"38", + 2395 => x"52", + 2396 => x"d6", + 2397 => x"c0", + 2398 => x"98", + 2399 => x"11", + 2400 => x"57", + 2401 => x"74", + 2402 => x"81", + 2403 => x"0c", + 2404 => x"81", + 2405 => x"84", + 2406 => x"55", + 2407 => x"ff", + 2408 => x"54", + 2409 => x"c0", + 2410 => x"0d", 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x"de", + 2470 => x"2e", + 2471 => x"86", + 2472 => x"c0", + 2473 => x"de", + 2474 => x"70", + 2475 => x"07", + 2476 => x"7c", + 2477 => x"55", + 2478 => x"f8", + 2479 => x"2e", + 2480 => x"ff", + 2481 => x"55", + 2482 => x"ff", + 2483 => x"76", + 2484 => x"3f", + 2485 => x"08", + 2486 => x"08", + 2487 => x"de", + 2488 => x"80", + 2489 => x"55", + 2490 => x"94", + 2491 => x"2e", + 2492 => x"53", + 2493 => x"51", + 2494 => x"81", + 2495 => x"55", + 2496 => x"75", + 2497 => x"98", + 2498 => x"05", + 2499 => x"56", + 2500 => x"26", + 2501 => x"15", + 2502 => x"84", + 2503 => x"07", + 2504 => x"18", + 2505 => x"ff", + 2506 => x"2e", + 2507 => x"39", + 2508 => x"39", + 2509 => x"08", + 2510 => x"81", + 2511 => x"74", + 2512 => x"0c", + 2513 => x"04", + 2514 => x"7a", + 2515 => x"f3", + 2516 => x"de", + 2517 => x"81", + 2518 => x"c0", + 2519 => x"38", + 2520 => x"51", + 2521 => x"81", + 2522 => x"81", + 2523 => x"b0", + 2524 => x"84", + 2525 => x"52", + 2526 => x"52", + 2527 => x"3f", + 2528 => x"39", + 2529 => x"8a", + 2530 => x"75", + 2531 => x"38", + 2532 => x"19", + 2533 => x"81", + 2534 => x"ed", + 2535 => x"de", + 2536 => x"2e", + 2537 => x"15", + 2538 => x"70", + 2539 => x"07", + 2540 => x"53", + 2541 => x"75", + 2542 => x"0c", + 2543 => x"04", + 2544 => x"7a", + 2545 => x"58", + 2546 => x"f0", + 2547 => x"80", + 2548 => x"9f", + 2549 => x"80", + 2550 => x"90", + 2551 => x"17", + 2552 => x"aa", + 2553 => x"53", + 2554 => x"88", + 2555 => x"08", + 2556 => x"38", + 2557 => x"53", + 2558 => x"17", + 2559 => x"72", + 2560 => x"fe", + 2561 => x"08", + 2562 => x"80", + 2563 => x"16", + 2564 => x"2b", + 2565 => x"75", + 2566 => x"73", + 2567 => x"f5", + 2568 => x"de", + 2569 => x"81", + 2570 => x"ff", + 2571 => x"81", + 2572 => x"c0", + 2573 => x"38", + 2574 => x"81", + 2575 => x"26", + 2576 => x"58", + 2577 => x"73", + 2578 => x"39", + 2579 => x"51", + 2580 => x"81", + 2581 => x"98", + 2582 => x"94", + 2583 => x"17", + 2584 => x"58", + 2585 => x"9a", + 2586 => x"81", + 2587 => x"74", + 2588 => x"98", + 2589 => x"83", + 2590 => x"b4", + 2591 => x"0c", + 2592 => x"81", + 2593 => x"8a", + 2594 => x"f8", + 2595 => x"70", + 2596 => x"08", + 2597 => x"57", + 2598 => x"0a", + 2599 => x"38", + 2600 => x"15", + 2601 => x"08", + 2602 => x"72", + 2603 => x"cb", + 2604 => x"ff", + 2605 => x"81", + 2606 => x"13", + 2607 => x"94", + 2608 => x"74", + 2609 => x"85", + 2610 => x"22", + 2611 => x"73", + 2612 => x"38", + 2613 => x"8a", + 2614 => x"05", + 2615 => x"06", + 2616 => x"8a", + 2617 => x"73", + 2618 => x"3f", + 2619 => x"08", + 2620 => x"81", + 2621 => x"c0", + 2622 => x"ff", + 2623 => x"81", + 2624 => x"ff", + 2625 => x"38", + 2626 => x"81", + 2627 => x"26", + 2628 => x"7b", + 2629 => x"98", + 2630 => x"55", + 2631 => x"94", + 2632 => x"73", + 2633 => x"3f", + 2634 => x"08", + 2635 => x"81", + 2636 => x"80", + 2637 => x"38", + 2638 => x"de", + 2639 => x"2e", + 2640 => x"55", + 2641 => x"08", + 2642 => x"38", + 2643 => x"08", + 2644 => x"fb", + 2645 => x"de", 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x"eb", + 2705 => x"de", + 2706 => x"2b", + 2707 => x"72", + 2708 => x"0c", + 2709 => x"04", + 2710 => x"77", + 2711 => x"ff", + 2712 => x"9a", + 2713 => x"55", + 2714 => x"76", + 2715 => x"53", + 2716 => x"09", + 2717 => x"38", + 2718 => x"52", + 2719 => x"eb", + 2720 => x"3d", + 2721 => x"3d", + 2722 => x"5b", + 2723 => x"08", + 2724 => x"15", + 2725 => x"81", + 2726 => x"15", + 2727 => x"51", + 2728 => x"81", + 2729 => x"58", + 2730 => x"08", + 2731 => x"9c", + 2732 => x"33", + 2733 => x"86", + 2734 => x"80", + 2735 => x"13", + 2736 => x"06", + 2737 => x"06", + 2738 => x"72", + 2739 => x"81", + 2740 => x"53", + 2741 => x"2e", + 2742 => x"53", + 2743 => x"a9", + 2744 => x"74", + 2745 => x"72", + 2746 => x"38", + 2747 => x"99", + 2748 => x"c0", + 2749 => x"06", + 2750 => x"88", + 2751 => x"06", + 2752 => x"54", + 2753 => x"a0", + 2754 => x"74", + 2755 => x"3f", + 2756 => x"08", + 2757 => x"c0", + 2758 => x"98", + 2759 => x"fa", + 2760 => x"80", + 2761 => x"0c", + 2762 => x"c0", + 2763 => x"0d", + 2764 => x"0d", + 2765 => x"57", + 2766 => x"73", + 2767 => x"3f", + 2768 => x"08", + 2769 => x"c0", + 2770 => x"98", + 2771 => x"75", + 2772 => x"3f", + 2773 => x"08", + 2774 => x"c0", + 2775 => x"a0", + 2776 => x"c0", + 2777 => x"14", + 2778 => x"db", + 2779 => x"a0", + 2780 => x"14", + 2781 => x"ac", + 2782 => x"83", + 2783 => x"81", + 2784 => x"87", + 2785 => x"fd", + 2786 => x"70", + 2787 => x"08", + 2788 => x"55", + 2789 => x"3f", + 2790 => x"08", + 2791 => x"13", + 2792 => x"73", + 2793 => x"83", + 2794 => x"3d", + 2795 => x"3d", + 2796 => x"57", + 2797 => x"89", + 2798 => x"17", + 2799 => x"81", + 2800 => x"70", + 2801 => x"55", + 2802 => x"08", + 2803 => x"81", + 2804 => x"52", + 2805 => x"a8", + 2806 => x"2e", + 2807 => x"84", + 2808 => x"52", + 2809 => x"09", + 2810 => x"38", + 2811 => x"81", + 2812 => x"81", + 2813 => x"73", + 2814 => x"55", + 2815 => x"55", + 2816 => x"c5", + 2817 => x"88", + 2818 => x"0b", + 2819 => x"9c", + 2820 => x"8b", + 2821 => x"17", + 2822 => x"08", + 2823 => x"52", + 2824 => x"81", + 2825 => x"76", + 2826 => x"51", + 2827 => x"81", + 2828 => x"86", + 2829 => x"12", + 2830 => x"3f", + 2831 => x"08", + 2832 => x"88", + 2833 => x"f3", + 2834 => x"70", + 2835 => x"80", + 2836 => x"51", + 2837 => x"af", + 2838 => x"81", + 2839 => x"dc", + 2840 => x"74", + 2841 => x"38", + 2842 => x"88", + 2843 => x"39", + 2844 => x"80", + 2845 => x"56", + 2846 => x"af", + 2847 => x"06", + 2848 => x"56", + 2849 => x"32", + 2850 => x"80", + 2851 => x"51", + 2852 => x"dc", + 2853 => x"1c", + 2854 => x"33", + 2855 => x"9f", + 2856 => x"ff", + 2857 => x"1c", + 2858 => x"7a", + 2859 => x"3f", + 2860 => x"08", + 2861 => x"39", + 2862 => x"a0", + 2863 => x"5e", + 2864 => x"52", + 2865 => x"ff", + 2866 => x"59", + 2867 => x"33", + 2868 => x"ae", + 2869 => x"06", + 2870 => x"78", + 2871 => x"81", + 2872 => x"32", + 2873 => x"9f", + 2874 => x"26", + 2875 => x"53", + 2876 => x"73", + 2877 => x"17", + 2878 => x"34", + 2879 => x"db", + 2880 => x"32", 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x"80", + 2940 => x"1c", + 2941 => x"27", + 2942 => x"79", + 2943 => x"74", + 2944 => x"7a", + 2945 => x"74", + 2946 => x"39", + 2947 => x"cc", + 2948 => x"fe", + 2949 => x"c0", + 2950 => x"ff", + 2951 => x"73", + 2952 => x"38", + 2953 => x"81", + 2954 => x"54", + 2955 => x"75", + 2956 => x"17", + 2957 => x"39", + 2958 => x"0c", + 2959 => x"99", + 2960 => x"54", + 2961 => x"2e", + 2962 => x"84", + 2963 => x"34", + 2964 => x"76", + 2965 => x"8b", + 2966 => x"81", + 2967 => x"56", + 2968 => x"80", + 2969 => x"1b", + 2970 => x"08", + 2971 => x"51", + 2972 => x"81", + 2973 => x"56", + 2974 => x"08", + 2975 => x"98", + 2976 => x"76", + 2977 => x"3f", + 2978 => x"08", + 2979 => x"c0", + 2980 => x"38", + 2981 => x"70", + 2982 => x"73", + 2983 => x"be", + 2984 => x"33", + 2985 => x"73", + 2986 => x"8b", + 2987 => x"83", + 2988 => x"06", + 2989 => x"73", + 2990 => x"53", + 2991 => x"51", + 2992 => x"81", + 2993 => x"80", + 2994 => x"75", + 2995 => x"f3", + 2996 => x"9f", + 2997 => x"1c", + 2998 => x"74", + 2999 => x"38", + 3000 => x"09", + 3001 => x"e7", + 3002 => x"2a", + 3003 => x"77", + 3004 => x"51", + 3005 => x"2e", + 3006 => x"81", + 3007 => x"80", + 3008 => x"38", + 3009 => x"ab", + 3010 => x"55", + 3011 => x"75", + 3012 => x"73", + 3013 => x"55", + 3014 => x"82", + 3015 => x"06", + 3016 => x"ab", + 3017 => x"33", + 3018 => x"70", + 3019 => x"55", + 3020 => x"2e", + 3021 => x"1b", + 3022 => x"06", + 3023 => x"52", + 3024 => x"db", + 3025 => x"c0", + 3026 => x"0c", + 3027 => x"74", + 3028 => x"0c", + 3029 => x"04", + 3030 => x"7c", + 3031 => x"08", + 3032 => x"55", + 3033 => x"59", + 3034 => x"81", + 3035 => x"70", + 3036 => x"33", + 3037 => x"52", + 3038 => x"2e", + 3039 => x"ee", + 3040 => x"2e", + 3041 => x"81", + 3042 => x"33", + 3043 => x"81", + 3044 => x"52", + 3045 => x"26", + 3046 => x"14", + 3047 => x"06", + 3048 => x"52", + 3049 => x"80", + 3050 => x"0b", + 3051 => x"59", + 3052 => x"7a", + 3053 => x"70", + 3054 => x"33", + 3055 => x"05", + 3056 => x"9f", + 3057 => x"53", + 3058 => x"89", + 3059 => x"70", + 3060 => x"54", + 3061 => x"12", + 3062 => x"26", + 3063 => x"12", + 3064 => x"06", + 3065 => x"30", + 3066 => x"51", + 3067 => x"2e", + 3068 => x"85", + 3069 => x"be", + 3070 => x"74", + 3071 => x"30", + 3072 => x"9f", + 3073 => x"2a", + 3074 => x"54", + 3075 => x"2e", + 3076 => x"15", + 3077 => x"55", + 3078 => x"ff", + 3079 => x"39", + 3080 => x"86", + 3081 => x"7c", + 3082 => x"51", + 3083 => x"de", + 3084 => x"70", + 3085 => x"0c", + 3086 => x"04", + 3087 => x"78", + 3088 => x"83", + 3089 => x"0b", + 3090 => x"79", + 3091 => x"e2", + 3092 => x"55", + 3093 => x"08", + 3094 => x"84", + 3095 => x"df", + 3096 => x"de", + 3097 => x"ff", + 3098 => x"83", + 3099 => x"d4", + 3100 => x"81", + 3101 => x"38", + 3102 => x"17", + 3103 => x"74", + 3104 => x"09", + 3105 => x"38", + 3106 => x"81", + 3107 => x"30", + 3108 => x"79", + 3109 => x"54", + 3110 => x"74", + 3111 => x"09", + 3112 => x"38", + 3113 => x"cc", + 3114 => x"ea", + 3115 => x"b1", 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x"de", + 3175 => x"ff", + 3176 => x"82", + 3177 => x"06", + 3178 => x"8c", + 3179 => x"58", + 3180 => x"f6", + 3181 => x"58", + 3182 => x"2e", + 3183 => x"fa", + 3184 => x"e8", + 3185 => x"c0", + 3186 => x"78", + 3187 => x"5a", + 3188 => x"90", + 3189 => x"75", + 3190 => x"38", + 3191 => x"3d", + 3192 => x"70", + 3193 => x"08", + 3194 => x"7a", + 3195 => x"38", + 3196 => x"51", + 3197 => x"81", + 3198 => x"81", + 3199 => x"81", + 3200 => x"38", + 3201 => x"83", + 3202 => x"38", + 3203 => x"84", + 3204 => x"38", + 3205 => x"81", + 3206 => x"38", + 3207 => x"db", + 3208 => x"de", + 3209 => x"ff", + 3210 => x"72", + 3211 => x"09", + 3212 => x"d0", + 3213 => x"14", + 3214 => x"3f", + 3215 => x"08", + 3216 => x"06", + 3217 => x"38", + 3218 => x"51", + 3219 => x"81", + 3220 => x"58", + 3221 => x"0c", + 3222 => x"33", + 3223 => x"80", + 3224 => x"ff", + 3225 => x"ff", + 3226 => x"55", + 3227 => x"81", + 3228 => x"38", + 3229 => x"06", + 3230 => x"80", + 3231 => x"52", + 3232 => x"8a", + 3233 => x"80", + 3234 => x"ff", + 3235 => x"53", + 3236 => x"86", + 3237 => x"83", + 3238 => x"c5", + 3239 => x"f5", + 3240 => x"c0", + 3241 => x"de", + 3242 => x"15", + 3243 => x"06", + 3244 => x"76", + 3245 => x"80", + 3246 => x"da", + 3247 => x"de", + 3248 => x"ff", + 3249 => x"74", + 3250 => x"d4", + 3251 => x"dc", + 3252 => x"c0", + 3253 => x"c2", + 3254 => x"b9", + 3255 => x"c0", + 3256 => x"ff", + 3257 => x"56", + 3258 => x"83", + 3259 => x"14", + 3260 => x"71", + 3261 => x"5a", + 3262 => x"26", + 3263 => x"8a", + 3264 => x"74", + 3265 => x"ff", + 3266 => x"81", + 3267 => x"55", + 3268 => x"08", + 3269 => x"ec", + 3270 => x"c0", + 3271 => x"ff", + 3272 => x"83", + 3273 => x"74", + 3274 => x"26", + 3275 => x"57", + 3276 => x"26", + 3277 => x"57", + 3278 => x"56", + 3279 => x"82", + 3280 => x"15", + 3281 => x"0c", + 3282 => x"0c", + 3283 => x"a4", + 3284 => x"1d", + 3285 => x"54", + 3286 => x"2e", + 3287 => x"af", + 3288 => x"14", + 3289 => x"3f", + 3290 => x"08", + 3291 => x"06", + 3292 => x"72", + 3293 => x"79", + 3294 => x"80", + 3295 => x"d9", + 3296 => x"de", + 3297 => x"15", + 3298 => x"2b", + 3299 => x"8d", + 3300 => x"2e", + 3301 => x"77", + 3302 => x"0c", + 3303 => x"76", + 3304 => x"38", + 3305 => x"70", + 3306 => x"81", + 3307 => x"53", + 3308 => x"89", + 3309 => x"56", + 3310 => x"08", + 3311 => x"38", + 3312 => x"15", + 3313 => x"8c", + 3314 => x"80", + 3315 => x"34", + 3316 => x"09", + 3317 => x"92", + 3318 => x"14", + 3319 => x"3f", + 3320 => x"08", + 3321 => x"06", + 3322 => x"2e", + 3323 => x"80", + 3324 => x"1b", + 3325 => x"db", + 3326 => x"de", + 3327 => x"ea", + 3328 => x"c0", + 3329 => x"34", + 3330 => x"51", + 3331 => x"81", + 3332 => x"83", + 3333 => x"53", + 3334 => x"d5", + 3335 => x"06", + 3336 => x"b4", + 3337 => x"84", + 3338 => x"c0", + 3339 => x"85", + 3340 => x"09", + 3341 => x"38", + 3342 => x"51", + 3343 => x"81", + 3344 => x"86", + 3345 => x"f2", + 3346 => x"06", + 3347 => x"9c", + 3348 => x"d8", + 3349 => x"c0", + 3350 => x"0c", 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x"84", + 3410 => x"05", + 3411 => x"89", + 3412 => x"2e", + 3413 => x"77", + 3414 => x"54", + 3415 => x"05", + 3416 => x"84", + 3417 => x"f6", + 3418 => x"de", + 3419 => x"81", + 3420 => x"84", + 3421 => x"5c", + 3422 => x"3d", + 3423 => x"ed", + 3424 => x"de", + 3425 => x"81", + 3426 => x"92", + 3427 => x"d7", + 3428 => x"98", + 3429 => x"73", + 3430 => x"38", + 3431 => x"9c", + 3432 => x"80", + 3433 => x"38", + 3434 => x"95", + 3435 => x"2e", + 3436 => x"aa", + 3437 => x"ea", + 3438 => x"de", + 3439 => x"9e", + 3440 => x"05", + 3441 => x"54", + 3442 => x"38", + 3443 => x"70", + 3444 => x"54", + 3445 => x"8e", + 3446 => x"83", + 3447 => x"88", + 3448 => x"83", + 3449 => x"83", + 3450 => x"06", + 3451 => x"80", + 3452 => x"38", + 3453 => x"51", + 3454 => x"81", + 3455 => x"56", + 3456 => x"0a", + 3457 => x"05", + 3458 => x"3f", + 3459 => x"0b", + 3460 => x"80", + 3461 => x"7a", + 3462 => x"3f", + 3463 => x"9c", + 3464 => x"d1", + 3465 => x"81", + 3466 => x"34", + 3467 => x"80", + 3468 => x"b0", + 3469 => x"54", + 3470 => x"52", + 3471 => x"05", + 3472 => x"3f", + 3473 => x"08", + 3474 => x"c0", + 3475 => x"38", + 3476 => x"82", + 3477 => x"b2", + 3478 => x"84", + 3479 => x"06", + 3480 => x"73", + 3481 => x"38", + 3482 => x"ad", + 3483 => x"2a", + 3484 => x"51", + 3485 => x"2e", + 3486 => x"81", + 3487 => x"80", + 3488 => x"87", + 3489 => x"39", + 3490 => x"51", + 3491 => x"81", + 3492 => x"7b", + 3493 => x"12", + 3494 => x"81", + 3495 => x"81", + 3496 => x"83", + 3497 => x"06", + 3498 => x"80", + 3499 => x"77", + 3500 => x"58", + 3501 => x"08", + 3502 => x"63", + 3503 => x"63", + 3504 => x"57", + 3505 => x"81", + 3506 => x"81", + 3507 => x"88", + 3508 => x"9c", + 3509 => x"d2", + 3510 => x"de", + 3511 => x"de", + 3512 => x"1b", + 3513 => x"0c", + 3514 => x"22", + 3515 => x"77", + 3516 => x"80", + 3517 => x"34", + 3518 => x"1a", + 3519 => x"94", + 3520 => x"85", + 3521 => x"06", + 3522 => x"80", + 3523 => x"38", + 3524 => x"08", + 3525 => x"84", + 3526 => x"c0", + 3527 => x"0c", + 3528 => x"70", + 3529 => x"52", + 3530 => x"39", + 3531 => x"51", + 3532 => x"81", + 3533 => x"57", + 3534 => x"08", + 3535 => x"38", + 3536 => x"de", + 3537 => x"2e", + 3538 => x"83", + 3539 => x"75", + 3540 => x"74", + 3541 => x"07", + 3542 => x"54", + 3543 => x"8a", + 3544 => x"75", + 3545 => x"73", + 3546 => x"98", + 3547 => x"a9", + 3548 => x"ff", + 3549 => x"80", + 3550 => x"76", + 3551 => x"d6", + 3552 => x"de", + 3553 => x"38", + 3554 => x"39", + 3555 => x"81", + 3556 => x"05", + 3557 => x"84", + 3558 => x"0c", + 3559 => x"81", + 3560 => x"97", + 3561 => x"f2", + 3562 => x"63", + 3563 => x"40", + 3564 => x"7e", + 3565 => x"fc", + 3566 => x"51", + 3567 => x"81", + 3568 => x"55", + 3569 => x"08", + 3570 => x"19", + 3571 => x"80", + 3572 => x"74", + 3573 => x"39", + 3574 => x"81", + 3575 => x"56", + 3576 => x"82", + 3577 => x"39", + 3578 => x"1a", + 3579 => x"82", + 3580 => x"0b", + 3581 => x"81", + 3582 => x"39", + 3583 => x"94", + 3584 => x"55", + 3585 => x"83", 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x"53", + 3645 => x"83", + 3646 => x"b4", + 3647 => x"51", + 3648 => x"7b", + 3649 => x"08", + 3650 => x"76", + 3651 => x"08", + 3652 => x"0c", + 3653 => x"f3", + 3654 => x"75", + 3655 => x"0c", + 3656 => x"04", + 3657 => x"60", + 3658 => x"40", + 3659 => x"80", + 3660 => x"3d", + 3661 => x"77", + 3662 => x"3f", + 3663 => x"08", + 3664 => x"c0", + 3665 => x"91", + 3666 => x"74", + 3667 => x"38", + 3668 => x"b8", + 3669 => x"33", + 3670 => x"70", + 3671 => x"56", + 3672 => x"74", + 3673 => x"a4", + 3674 => x"82", + 3675 => x"34", + 3676 => x"98", + 3677 => x"91", + 3678 => x"56", + 3679 => x"94", + 3680 => x"11", + 3681 => x"76", + 3682 => x"75", + 3683 => x"80", + 3684 => x"38", + 3685 => x"70", + 3686 => x"56", + 3687 => x"fd", + 3688 => x"11", + 3689 => x"77", + 3690 => x"5c", + 3691 => x"38", + 3692 => x"88", + 3693 => x"74", + 3694 => x"52", + 3695 => x"18", + 3696 => x"51", + 3697 => x"81", + 3698 => x"55", + 3699 => x"08", + 3700 => x"ab", + 3701 => x"2e", + 3702 => x"74", + 3703 => x"95", + 3704 => x"19", + 3705 => x"08", + 3706 => x"88", + 3707 => x"55", + 3708 => x"9c", + 3709 => x"09", + 3710 => x"38", + 3711 => x"c1", + 3712 => x"c0", + 3713 => x"38", + 3714 => x"52", + 3715 => x"97", + 3716 => x"c0", + 3717 => x"fe", + 3718 => x"de", + 3719 => x"7c", + 3720 => x"57", + 3721 => x"80", + 3722 => x"1b", + 3723 => x"22", + 3724 => x"75", + 3725 => x"38", + 3726 => x"59", + 3727 => x"53", + 3728 => x"1a", + 3729 => x"be", + 3730 => x"c0", + 3731 => x"38", + 3732 => x"08", + 3733 => x"56", + 3734 => x"9b", + 3735 => x"53", + 3736 => x"77", + 3737 => x"7d", + 3738 => x"16", + 3739 => x"3f", + 3740 => x"0b", + 3741 => x"78", + 3742 => x"80", + 3743 => x"18", + 3744 => x"08", + 3745 => x"7e", + 3746 => x"3f", + 3747 => x"08", + 3748 => x"7e", + 3749 => x"0c", + 3750 => x"19", + 3751 => x"08", + 3752 => x"84", + 3753 => x"57", + 3754 => x"27", + 3755 => x"56", + 3756 => x"52", + 3757 => x"f9", + 3758 => x"c0", + 3759 => x"38", + 3760 => x"52", + 3761 => x"83", + 3762 => x"b4", + 3763 => x"d4", + 3764 => x"81", + 3765 => x"34", + 3766 => x"7e", + 3767 => x"0c", + 3768 => x"1a", + 3769 => x"94", + 3770 => x"1b", + 3771 => x"5e", + 3772 => x"27", + 3773 => x"55", + 3774 => x"0c", + 3775 => x"90", + 3776 => x"c0", + 3777 => x"90", + 3778 => x"56", + 3779 => x"c0", + 3780 => x"0d", + 3781 => x"0d", + 3782 => x"fc", + 3783 => x"52", + 3784 => x"3f", + 3785 => x"08", + 3786 => x"c0", + 3787 => x"38", + 3788 => x"70", + 3789 => x"81", + 3790 => x"55", + 3791 => x"80", + 3792 => x"16", + 3793 => x"51", + 3794 => x"81", + 3795 => x"57", + 3796 => x"08", + 3797 => x"a4", + 3798 => x"11", + 3799 => x"55", + 3800 => x"16", + 3801 => x"08", + 3802 => x"75", + 3803 => x"e8", + 3804 => x"08", + 3805 => x"51", + 3806 => x"82", + 3807 => x"52", + 3808 => x"c9", + 3809 => x"52", + 3810 => x"c9", + 3811 => x"54", + 3812 => x"15", + 3813 => x"cc", + 3814 => x"de", + 3815 => x"17", + 3816 => x"06", + 3817 => x"90", + 3818 => x"81", + 3819 => x"8a", + 3820 => x"fc", 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x"7a", + 3880 => x"9e", + 3881 => x"05", + 3882 => x"51", + 3883 => x"81", + 3884 => x"57", + 3885 => x"08", + 3886 => x"7b", + 3887 => x"94", + 3888 => x"55", + 3889 => x"73", + 3890 => x"ed", + 3891 => x"93", + 3892 => x"55", + 3893 => x"81", + 3894 => x"57", + 3895 => x"08", + 3896 => x"68", + 3897 => x"c9", + 3898 => x"de", + 3899 => x"81", + 3900 => x"82", + 3901 => x"52", + 3902 => x"a3", + 3903 => x"c0", + 3904 => x"52", + 3905 => x"b8", + 3906 => x"c0", + 3907 => x"de", + 3908 => x"a2", + 3909 => x"74", + 3910 => x"3f", + 3911 => x"08", + 3912 => x"c0", + 3913 => x"69", + 3914 => x"d9", + 3915 => x"81", + 3916 => x"2e", + 3917 => x"52", + 3918 => x"cf", + 3919 => x"c0", + 3920 => x"de", + 3921 => x"2e", + 3922 => x"84", + 3923 => x"06", + 3924 => x"57", + 3925 => x"76", + 3926 => x"9e", + 3927 => x"05", + 3928 => x"dc", + 3929 => x"90", + 3930 => x"81", + 3931 => x"56", + 3932 => x"80", + 3933 => x"02", + 3934 => x"81", + 3935 => x"70", + 3936 => x"56", + 3937 => x"81", + 3938 => x"78", + 3939 => x"38", + 3940 => x"99", + 3941 => x"81", + 3942 => x"18", + 3943 => x"18", + 3944 => x"58", + 3945 => x"33", + 3946 => x"ee", + 3947 => x"6f", + 3948 => x"af", + 3949 => x"8d", + 3950 => x"2e", + 3951 => x"8a", + 3952 => x"6f", + 3953 => x"af", + 3954 => x"0b", + 3955 => x"33", + 3956 => x"81", + 3957 => x"70", + 3958 => x"52", + 3959 => x"56", + 3960 => x"8d", + 3961 => x"70", + 3962 => x"51", + 3963 => x"f5", + 3964 => x"54", + 3965 => x"a7", + 3966 => x"74", + 3967 => x"38", + 3968 => x"73", + 3969 => x"81", + 3970 => x"81", + 3971 => x"39", + 3972 => x"81", + 3973 => x"74", + 3974 => x"81", + 3975 => x"91", + 3976 => x"6e", + 3977 => x"59", + 3978 => x"7a", + 3979 => x"5c", + 3980 => x"26", + 3981 => x"7a", + 3982 => x"de", + 3983 => x"3d", + 3984 => x"3d", + 3985 => x"8d", + 3986 => x"54", + 3987 => x"55", + 3988 => x"81", + 3989 => x"53", + 3990 => x"08", + 3991 => x"91", + 3992 => x"72", + 3993 => x"8c", + 3994 => x"73", + 3995 => x"38", + 3996 => x"70", + 3997 => x"81", + 3998 => x"57", + 3999 => x"73", + 4000 => x"08", + 4001 => x"94", + 4002 => x"75", + 4003 => x"97", + 4004 => x"11", + 4005 => x"2b", + 4006 => x"73", + 4007 => x"38", + 4008 => x"16", + 4009 => x"d2", + 4010 => x"c0", + 4011 => x"78", + 4012 => x"55", + 4013 => x"c2", + 4014 => x"c0", + 4015 => x"96", + 4016 => x"70", + 4017 => x"94", + 4018 => x"71", + 4019 => x"08", + 4020 => x"53", + 4021 => x"15", + 4022 => x"a6", + 4023 => x"74", + 4024 => x"3f", + 4025 => x"08", + 4026 => x"c0", + 4027 => x"81", + 4028 => x"de", + 4029 => x"2e", + 4030 => x"81", + 4031 => x"88", + 4032 => x"98", + 4033 => x"80", + 4034 => x"38", + 4035 => x"80", + 4036 => x"77", + 4037 => x"08", + 4038 => x"0c", + 4039 => x"70", + 4040 => x"81", + 4041 => x"5a", + 4042 => x"2e", + 4043 => x"52", + 4044 => x"f9", + 4045 => x"c0", + 4046 => x"de", + 4047 => x"38", + 4048 => x"08", + 4049 => x"73", + 4050 => x"c7", + 4051 => x"de", + 4052 => x"73", + 4053 => x"38", + 4054 => x"af", + 4055 => x"73", + 4056 => x"27", + 4057 => x"98", + 4058 => x"a0", + 4059 => x"08", + 4060 => x"0c", + 4061 => x"06", + 4062 => x"2e", + 4063 => x"52", + 4064 => x"a3", + 4065 => x"c0", + 4066 => x"82", + 4067 => x"34", + 4068 => x"c4", + 4069 => x"91", + 4070 => x"53", + 4071 => x"89", + 4072 => x"c0", + 4073 => x"94", + 4074 => x"8c", + 4075 => x"27", + 4076 => x"8c", + 4077 => x"15", + 4078 => x"07", + 4079 => x"16", + 4080 => x"ff", + 4081 => x"80", + 4082 => x"77", + 4083 => x"2e", + 4084 => x"9c", + 4085 => x"53", + 4086 => x"c0", + 4087 => x"0d", + 4088 => x"0d", + 4089 => x"54", + 4090 => x"81", + 4091 => x"53", + 4092 => x"05", + 4093 => x"84", + 4094 => x"e7", + 4095 => x"c0", + 4096 => x"de", + 4097 => x"ea", + 4098 => x"0c", + 4099 => x"51", + 4100 => x"81", + 4101 => x"55", + 4102 => x"08", + 4103 => x"ab", + 4104 => x"98", + 4105 => x"80", + 4106 => x"38", + 4107 => x"70", + 4108 => x"81", + 4109 => x"57", + 4110 => x"ad", + 4111 => x"08", + 4112 => x"d3", + 4113 => x"de", + 4114 => x"17", + 4115 => x"86", + 4116 => x"17", + 4117 => x"75", + 4118 => x"3f", + 4119 => x"08", + 4120 => x"2e", + 4121 => x"85", + 4122 => x"86", + 4123 => x"2e", + 4124 => x"76", + 4125 => x"73", + 4126 => x"0c", + 4127 => x"04", + 4128 => x"76", + 4129 => x"05", + 4130 => x"53", + 4131 => x"81", + 4132 => x"87", + 4133 => x"c0", + 4134 => x"86", + 4135 => x"fb", + 4136 => x"79", + 4137 => x"05", + 4138 => x"56", + 4139 => x"3f", + 4140 => x"08", + 4141 => x"c0", + 4142 => x"38", + 4143 => x"81", + 4144 => x"52", + 4145 => x"f8", + 4146 => x"c0", + 4147 => x"ca", + 4148 => x"c0", + 4149 => x"51", + 4150 => x"81", + 4151 => x"53", + 4152 => x"08", + 4153 => x"81", + 4154 => x"80", + 4155 => x"81", + 4156 => x"a6", + 4157 => x"73", + 4158 => x"3f", + 4159 => x"51", + 4160 => x"81", + 4161 => x"84", + 4162 => x"70", + 4163 => x"2c", + 4164 => x"c0", + 4165 => x"51", + 4166 => x"81", + 4167 => x"87", + 4168 => x"ee", + 4169 => x"57", + 4170 => x"3d", + 4171 => x"3d", + 4172 => x"af", + 4173 => x"c0", + 4174 => x"de", + 4175 => x"38", + 4176 => x"51", + 4177 => x"81", + 4178 => x"55", + 4179 => x"08", + 4180 => x"80", + 4181 => x"70", + 4182 => x"58", + 4183 => x"85", + 4184 => x"8d", + 4185 => x"2e", + 4186 => x"52", + 4187 => x"be", + 4188 => x"de", + 4189 => x"3d", + 4190 => x"3d", + 4191 => x"55", + 4192 => x"92", + 4193 => x"52", + 4194 => x"de", + 4195 => x"de", + 4196 => x"81", + 4197 => x"82", + 4198 => x"74", + 4199 => x"98", + 4200 => x"11", + 4201 => x"59", + 4202 => x"75", + 4203 => x"38", + 4204 => x"81", + 4205 => x"5b", + 4206 => x"82", + 4207 => x"39", + 4208 => x"08", + 4209 => x"59", + 4210 => x"09", + 4211 => x"38", + 4212 => x"57", + 4213 => x"3d", + 4214 => x"c1", + 4215 => x"de", + 4216 => x"2e", + 4217 => x"de", + 4218 => x"2e", + 4219 => x"de", + 4220 => x"70", + 4221 => x"08", + 4222 => x"7a", + 4223 => x"7f", + 4224 => x"54", + 4225 => x"77", + 4226 => x"80", + 4227 => x"15", + 4228 => x"c0", + 4229 => x"75", + 4230 => x"52", + 4231 => x"52", + 4232 => x"8d", + 4233 => x"c0", + 4234 => x"de", + 4235 => x"d6", + 4236 => x"33", + 4237 => x"1a", + 4238 => x"54", + 4239 => x"09", + 4240 => x"38", + 4241 => x"ff", + 4242 => x"81", + 4243 => x"83", + 4244 => x"70", + 4245 => x"25", + 4246 => x"59", + 4247 => x"9b", + 4248 => x"51", + 4249 => x"3f", + 4250 => x"08", + 4251 => x"70", + 4252 => x"25", + 4253 => x"59", + 4254 => x"75", + 4255 => x"7a", + 4256 => x"ff", + 4257 => x"7c", + 4258 => x"90", + 4259 => x"11", + 4260 => x"56", + 4261 => x"15", + 4262 => x"de", + 4263 => x"3d", + 4264 => x"3d", + 4265 => x"3d", + 4266 => x"70", + 4267 => x"dd", + 4268 => x"c0", + 4269 => x"de", + 4270 => x"a8", + 4271 => x"33", + 4272 => x"a0", + 4273 => x"33", + 4274 => x"70", + 4275 => x"55", + 4276 => x"73", + 4277 => x"8e", + 4278 => x"08", + 4279 => x"18", + 4280 => x"80", + 4281 => x"38", + 4282 => x"08", + 4283 => x"08", + 4284 => x"c4", + 4285 => x"de", + 4286 => x"88", + 4287 => x"80", + 4288 => x"17", + 4289 => x"51", + 4290 => x"3f", + 4291 => x"08", + 4292 => x"81", + 4293 => x"81", + 4294 => x"c0", + 4295 => x"09", + 4296 => x"38", + 4297 => x"39", + 4298 => x"77", + 4299 => x"c0", + 4300 => x"08", + 4301 => x"98", + 4302 => x"81", + 4303 => x"52", + 4304 => x"bd", + 4305 => x"c0", + 4306 => x"17", + 4307 => x"0c", + 4308 => x"80", + 4309 => x"73", + 4310 => x"75", + 4311 => x"38", + 4312 => x"34", + 4313 => x"81", + 4314 => x"89", + 4315 => x"e2", + 4316 => x"53", + 4317 => x"a4", + 4318 => x"3d", + 4319 => x"3f", + 4320 => x"08", + 4321 => x"c0", + 4322 => x"38", + 4323 => x"3d", + 4324 => x"3d", + 4325 => x"d1", + 4326 => x"de", + 4327 => x"81", + 4328 => x"81", + 4329 => x"80", + 4330 => x"70", + 4331 => x"81", + 4332 => x"56", + 4333 => x"81", + 4334 => x"98", + 4335 => x"74", + 4336 => x"38", + 4337 => x"05", + 4338 => x"06", + 4339 => x"55", + 4340 => x"38", + 4341 => x"51", + 4342 => x"81", + 4343 => x"74", + 4344 => x"81", + 4345 => x"56", + 4346 => x"80", + 4347 => x"54", + 4348 => x"08", + 4349 => x"2e", + 4350 => x"73", + 4351 => x"c0", + 4352 => x"52", + 4353 => x"52", + 4354 => x"3f", + 4355 => x"08", + 4356 => x"c0", + 4357 => x"38", + 4358 => x"08", + 4359 => x"cc", + 4360 => x"de", + 4361 => x"81", + 4362 => x"86", + 4363 => x"80", + 4364 => x"de", + 4365 => x"2e", + 4366 => x"de", + 4367 => x"c0", + 4368 => x"ce", + 4369 => x"de", + 4370 => x"de", + 4371 => x"70", + 4372 => x"08", + 4373 => x"51", + 4374 => x"80", + 4375 => x"73", + 4376 => x"38", + 4377 => x"52", + 4378 => x"95", + 4379 => x"c0", + 4380 => x"8c", + 4381 => x"ff", + 4382 => x"81", + 4383 => x"55", + 4384 => x"c0", + 4385 => x"0d", + 4386 => x"0d", + 4387 => x"3d", + 4388 => x"9a", + 4389 => x"cb", + 4390 => x"c0", + 4391 => x"de", + 4392 => x"b0", + 4393 => x"69", + 4394 => x"70", + 4395 => x"97", + 4396 => x"c0", + 4397 => x"de", + 4398 => x"38", + 4399 => x"94", + 4400 => x"c0", + 4401 => x"09", + 4402 => x"88", + 4403 => x"df", + 4404 => x"85", + 4405 => x"51", + 4406 => x"74", + 4407 => x"78", + 4408 => x"8a", + 4409 => x"57", + 4410 => x"81", + 4411 => x"75", + 4412 => x"de", + 4413 => x"38", + 4414 => x"de", + 4415 => x"2e", + 4416 => x"83", + 4417 => x"81", + 4418 => x"ff", + 4419 => x"06", + 4420 => x"54", + 4421 => x"73", + 4422 => x"81", + 4423 => x"52", + 4424 => x"a4", + 4425 => x"c0", + 4426 => x"de", + 4427 => x"9a", + 4428 => x"a0", + 4429 => x"51", + 4430 => x"3f", + 4431 => x"0b", + 4432 => x"78", + 4433 => x"bf", + 4434 => x"88", + 4435 => x"80", + 4436 => x"ff", + 4437 => x"75", + 4438 => x"11", + 4439 => x"f8", + 4440 => x"78", + 4441 => x"80", + 4442 => x"ff", + 4443 => x"78", + 4444 => x"80", + 4445 => x"7f", + 4446 => x"d4", + 4447 => x"c9", + 4448 => x"54", + 4449 => x"15", + 4450 => x"cb", + 4451 => x"de", + 4452 => x"81", + 4453 => x"b2", + 4454 => x"b2", + 4455 => x"96", + 4456 => x"b5", + 4457 => x"53", + 4458 => x"51", + 4459 => x"64", + 4460 => x"8b", + 4461 => x"54", + 4462 => x"15", + 4463 => x"ff", + 4464 => x"81", + 4465 => x"54", + 4466 => x"53", + 4467 => x"51", + 4468 => x"3f", + 4469 => x"c0", + 4470 => x"0d", + 4471 => x"0d", + 4472 => x"05", + 4473 => x"3f", + 4474 => x"3d", + 4475 => x"52", + 4476 => x"d5", + 4477 => x"de", + 4478 => x"81", + 4479 => x"82", + 4480 => x"4d", + 4481 => x"52", + 4482 => x"52", + 4483 => x"3f", + 4484 => x"08", + 4485 => x"c0", + 4486 => x"38", + 4487 => x"05", + 4488 => x"06", + 4489 => x"73", + 4490 => x"a0", + 4491 => x"08", + 4492 => x"ff", + 4493 => x"ff", + 4494 => x"ac", + 4495 => x"92", + 4496 => x"54", + 4497 => x"3f", + 4498 => x"52", + 4499 => x"f7", + 4500 => x"c0", + 4501 => x"de", + 4502 => x"38", + 4503 => x"09", + 4504 => x"38", + 4505 => x"08", + 4506 => x"88", + 4507 => x"39", + 4508 => x"08", + 4509 => x"81", + 4510 => x"38", + 4511 => x"b1", + 4512 => x"c0", + 4513 => x"de", + 4514 => x"c8", + 4515 => x"93", + 4516 => x"ff", + 4517 => x"8d", + 4518 => x"b4", + 4519 => x"af", + 4520 => x"17", + 4521 => x"33", + 4522 => x"70", + 4523 => x"55", + 4524 => x"38", + 4525 => x"54", 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x"81", + 4585 => x"86", + 4586 => x"38", + 4587 => x"61", + 4588 => x"12", + 4589 => x"7a", + 4590 => x"51", + 4591 => x"74", + 4592 => x"78", + 4593 => x"83", + 4594 => x"51", + 4595 => x"3f", + 4596 => x"08", + 4597 => x"de", + 4598 => x"3d", + 4599 => x"3d", + 4600 => x"82", + 4601 => x"d0", + 4602 => x"3d", + 4603 => x"3f", + 4604 => x"08", + 4605 => x"c0", + 4606 => x"38", + 4607 => x"52", + 4608 => x"05", + 4609 => x"3f", + 4610 => x"08", + 4611 => x"c0", + 4612 => x"02", + 4613 => x"33", + 4614 => x"54", + 4615 => x"a6", + 4616 => x"22", + 4617 => x"71", + 4618 => x"53", + 4619 => x"51", + 4620 => x"3f", + 4621 => x"0b", + 4622 => x"76", + 4623 => x"b8", + 4624 => x"c0", + 4625 => x"81", + 4626 => x"93", + 4627 => x"ea", + 4628 => x"6b", + 4629 => x"53", + 4630 => x"05", + 4631 => x"51", + 4632 => x"81", + 4633 => x"81", + 4634 => x"30", + 4635 => x"c0", + 4636 => x"25", + 4637 => x"79", + 4638 => x"85", + 4639 => x"75", + 4640 => x"73", + 4641 => x"f9", + 4642 => x"80", + 4643 => x"8d", + 4644 => x"54", + 4645 => x"3f", + 4646 => x"08", + 4647 => x"c0", + 4648 => x"38", + 4649 => x"51", + 4650 => x"81", + 4651 => x"57", + 4652 => x"08", + 4653 => x"de", + 4654 => x"de", + 4655 => x"5b", + 4656 => x"18", + 4657 => x"18", + 4658 => x"74", + 4659 => x"81", + 4660 => x"78", + 4661 => x"8b", + 4662 => x"54", + 4663 => x"75", + 4664 => x"38", + 4665 => x"1b", + 4666 => x"55", + 4667 => x"2e", + 4668 => x"39", + 4669 => x"09", + 4670 => x"38", + 4671 => x"80", + 4672 => x"70", + 4673 => x"25", + 4674 => x"80", + 4675 => x"38", + 4676 => x"bc", + 4677 => x"11", + 4678 => x"ff", + 4679 => x"81", + 4680 => x"57", + 4681 => x"08", + 4682 => x"70", + 4683 => x"80", + 4684 => x"83", + 4685 => x"80", + 4686 => x"84", + 4687 => x"a7", + 4688 => x"b4", + 4689 => x"ad", + 4690 => x"de", + 4691 => x"0c", + 4692 => x"c0", + 4693 => x"0d", + 4694 => x"0d", + 4695 => x"3d", + 4696 => x"52", + 4697 => x"ce", + 4698 => x"de", + 4699 => x"de", + 4700 => x"54", + 4701 => x"08", + 4702 => x"8b", + 4703 => x"8b", + 4704 => x"59", + 4705 => x"3f", + 4706 => x"33", + 4707 => x"06", + 4708 => x"57", + 4709 => x"81", + 4710 => x"58", + 4711 => x"06", + 4712 => x"4e", + 4713 => x"ff", + 4714 => x"81", + 4715 => x"80", + 4716 => x"6c", + 4717 => x"53", + 4718 => x"ae", + 4719 => x"de", + 4720 => x"2e", + 4721 => x"88", + 4722 => x"6d", + 4723 => x"55", + 4724 => x"de", + 4725 => x"ff", + 4726 => x"83", + 4727 => x"51", + 4728 => x"26", + 4729 => x"15", + 4730 => x"ff", + 4731 => x"80", + 4732 => x"87", + 4733 => x"b4", + 4734 => x"74", + 4735 => x"38", + 4736 => x"ce", + 4737 => x"ae", + 4738 => x"de", + 4739 => x"38", + 4740 => x"27", + 4741 => x"89", + 4742 => x"8b", + 4743 => x"27", + 4744 => x"55", + 4745 => x"81", + 4746 => x"8f", + 4747 => x"2a", + 4748 => x"70", + 4749 => x"34", + 4750 => x"74", + 4751 => x"05", + 4752 => x"17", + 4753 => x"70", + 4754 => x"52", + 4755 => x"73", + 4756 => x"c8", + 4757 => x"33", + 4758 => x"73", + 4759 => x"81", + 4760 => x"80", + 4761 => x"02", + 4762 => x"76", + 4763 => x"51", + 4764 => x"2e", + 4765 => x"87", + 4766 => x"57", + 4767 => x"79", + 4768 => x"80", + 4769 => x"70", + 4770 => x"ba", + 4771 => x"de", + 4772 => x"81", + 4773 => x"80", + 4774 => x"52", + 4775 => x"bf", + 4776 => x"de", + 4777 => x"81", + 4778 => x"8d", + 4779 => x"c4", + 4780 => x"e5", + 4781 => x"c6", + 4782 => x"c0", + 4783 => x"09", + 4784 => x"cc", + 4785 => x"76", + 4786 => x"c4", + 4787 => x"74", + 4788 => x"b0", + 4789 => x"c0", + 4790 => x"de", + 4791 => x"38", + 4792 => x"de", + 4793 => x"67", + 4794 => x"db", + 4795 => x"88", + 4796 => x"34", + 4797 => x"52", + 4798 => x"ab", + 4799 => x"54", + 4800 => x"15", + 4801 => x"ff", + 4802 => x"81", + 4803 => x"54", + 4804 => x"81", + 4805 => x"9c", + 4806 => x"f2", + 4807 => x"62", + 4808 => x"80", + 4809 => x"93", + 4810 => x"55", + 4811 => x"5e", + 4812 => x"3f", + 4813 => x"08", + 4814 => x"c0", + 4815 => x"38", + 4816 => x"58", + 4817 => x"38", + 4818 => x"97", + 4819 => x"08", + 4820 => x"38", + 4821 => x"70", + 4822 => x"81", + 4823 => x"55", + 4824 => x"87", + 4825 => x"39", + 4826 => x"90", + 4827 => x"82", + 4828 => x"8a", + 4829 => x"89", + 4830 => x"7f", + 4831 => x"56", + 4832 => x"3f", + 4833 => x"06", + 4834 => x"72", + 4835 => x"81", + 4836 => x"05", + 4837 => x"7c", + 4838 => x"55", + 4839 => x"27", + 4840 => x"16", + 4841 => x"83", + 4842 => x"76", + 4843 => x"80", + 4844 => x"79", + 4845 => x"99", + 4846 => x"7f", + 4847 => x"14", + 4848 => x"83", + 4849 => x"81", + 4850 => x"81", + 4851 => x"38", + 4852 => x"08", + 4853 => x"95", + 4854 => x"c0", + 4855 => x"81", + 4856 => x"7b", + 4857 => x"06", + 4858 => x"39", + 4859 => x"56", + 4860 => x"09", + 4861 => x"b9", + 4862 => x"80", + 4863 => x"80", + 4864 => x"78", + 4865 => x"7a", + 4866 => x"38", + 4867 => x"73", + 4868 => x"81", + 4869 => x"ff", + 4870 => x"74", + 4871 => x"ff", + 4872 => x"81", + 4873 => x"58", + 4874 => x"08", + 4875 => x"74", + 4876 => x"16", + 4877 => x"73", + 4878 => x"39", + 4879 => x"7e", + 4880 => x"0c", + 4881 => x"2e", + 4882 => x"88", + 4883 => x"8c", + 4884 => x"1a", + 4885 => x"07", + 4886 => x"1b", + 4887 => x"08", + 4888 => x"16", + 4889 => x"75", + 4890 => x"38", + 4891 => x"90", + 4892 => x"15", + 4893 => x"54", + 4894 => x"34", + 4895 => x"81", + 4896 => x"90", + 4897 => x"e9", + 4898 => x"6d", + 4899 => x"80", + 4900 => x"9d", + 4901 => x"5c", + 4902 => x"3f", + 4903 => x"0b", + 4904 => x"08", + 4905 => x"38", + 4906 => x"08", + 4907 => x"de", + 4908 => x"08", + 4909 => x"80", + 4910 => x"80", + 4911 => x"de", + 4912 => x"ff", + 4913 => x"52", + 4914 => x"a0", + 4915 => x"de", + 4916 => x"ff", + 4917 => x"06", + 4918 => x"56", + 4919 => x"38", + 4920 => x"70", + 4921 => x"55", + 4922 => x"8b", + 4923 => x"3d", + 4924 => x"83", + 4925 => x"ff", + 4926 => x"81", + 4927 => x"99", + 4928 => x"74", + 4929 => x"38", + 4930 => x"80", + 4931 => x"ff", + 4932 => x"55", + 4933 => x"83", + 4934 => x"78", + 4935 => x"38", + 4936 => x"26", + 4937 => x"81", + 4938 => x"8b", + 4939 => x"79", + 4940 => x"80", + 4941 => x"93", + 4942 => x"39", + 4943 => x"6e", + 4944 => x"89", + 4945 => x"48", + 4946 => x"83", + 4947 => x"61", + 4948 => x"25", + 4949 => x"55", + 4950 => x"8a", + 4951 => x"3d", + 4952 => x"81", + 4953 => x"ff", + 4954 => x"81", + 4955 => x"c0", + 4956 => x"38", + 4957 => x"70", + 4958 => x"de", + 4959 => x"56", + 4960 => x"38", + 4961 => x"55", + 4962 => x"75", + 4963 => x"38", + 4964 => x"70", + 4965 => x"ff", + 4966 => x"83", + 4967 => x"78", + 4968 => x"89", + 4969 => x"81", + 4970 => x"06", + 4971 => x"80", + 4972 => x"77", + 4973 => x"74", + 4974 => x"8d", + 4975 => x"06", + 4976 => x"2e", + 4977 => x"77", + 4978 => x"93", + 4979 => x"74", + 4980 => x"cb", + 4981 => x"7d", + 4982 => x"81", + 4983 => x"38", + 4984 => x"66", + 4985 => x"81", + 4986 => x"d8", + 4987 => x"74", + 4988 => x"38", + 4989 => x"98", + 4990 => x"d8", + 4991 => x"82", + 4992 => x"57", + 4993 => x"80", + 4994 => x"76", + 4995 => x"38", + 4996 => x"51", + 4997 => x"3f", + 4998 => x"08", + 4999 => x"87", + 5000 => x"2a", + 5001 => x"5c", + 5002 => x"de", + 5003 => x"80", + 5004 => x"44", + 5005 => x"0a", + 5006 => x"ec", + 5007 => x"39", + 5008 => x"66", + 5009 => x"81", + 5010 => x"c8", + 5011 => x"74", + 5012 => x"38", + 5013 => x"98", + 5014 => x"c8", + 5015 => x"82", + 5016 => x"57", + 5017 => x"80", + 5018 => x"76", + 5019 => x"38", + 5020 => x"51", + 5021 => x"3f", + 5022 => x"08", + 5023 => x"57", + 5024 => x"08", + 5025 => x"96", + 5026 => x"81", + 5027 => x"10", + 5028 => x"08", + 5029 => x"72", + 5030 => x"59", + 5031 => x"ff", + 5032 => x"5d", + 5033 => x"44", + 5034 => x"11", + 5035 => x"70", + 5036 => x"71", + 5037 => x"06", + 5038 => x"52", + 5039 => x"40", + 5040 => x"09", + 5041 => x"38", + 5042 => x"18", + 5043 => x"39", + 5044 => x"79", + 5045 => x"70", + 5046 => x"58", + 5047 => x"76", + 5048 => x"38", + 5049 => x"7d", + 5050 => x"70", + 5051 => x"55", + 5052 => x"3f", + 5053 => x"08", + 5054 => x"2e", + 5055 => x"9b", + 5056 => x"c0", + 5057 => x"f5", + 5058 => x"38", + 5059 => x"38", + 5060 => x"59", + 5061 => x"38", + 5062 => x"7d", + 5063 => x"81", + 5064 => x"38", + 5065 => x"0b", + 5066 => x"08", + 5067 => x"78", + 5068 => x"1a", + 5069 => x"c0", + 5070 => x"74", + 5071 => x"39", + 5072 => x"55", + 5073 => x"8f", + 5074 => x"fd", + 5075 => x"de", + 5076 => x"f5", + 5077 => x"78", + 5078 => x"79", + 5079 => x"80", + 5080 => x"f1", + 5081 => x"39", + 5082 => x"81", + 5083 => x"06", + 5084 => x"55", + 5085 => x"27", + 5086 => x"81", + 5087 => x"56", + 5088 => x"38", + 5089 => x"80", + 5090 => x"ff", + 5091 => x"8b", + 5092 => x"f0", + 5093 => x"ff", + 5094 => x"84", + 5095 => x"1b", + 5096 => x"b3", + 5097 => x"1c", + 5098 => x"ff", + 5099 => x"8e", + 5100 => x"a1", + 5101 => x"0b", + 5102 => x"7d", + 5103 => x"30", + 5104 => x"84", + 5105 => x"51", + 5106 => x"51", + 5107 => x"3f", + 5108 => x"83", + 5109 => x"90", + 5110 => x"ff", + 5111 => x"93", + 5112 => x"a0", + 5113 => x"39", + 5114 => x"1b", + 5115 => x"85", + 5116 => x"95", + 5117 => x"52", + 5118 => x"ff", + 5119 => x"81", + 5120 => x"1b", + 5121 => x"cf", + 5122 => x"9c", + 5123 => x"a0", + 5124 => x"83", + 5125 => x"06", + 5126 => x"82", + 5127 => x"52", + 5128 => x"51", + 5129 => x"3f", + 5130 => x"1b", + 5131 => x"c5", + 5132 => x"ac", + 5133 => x"a0", + 5134 => x"52", + 5135 => x"ff", + 5136 => x"86", + 5137 => x"51", + 5138 => x"3f", + 5139 => x"80", + 5140 => x"a9", + 5141 => x"1c", + 5142 => x"81", + 5143 => x"80", + 5144 => x"ae", + 5145 => x"b2", + 5146 => x"1b", + 5147 => x"85", + 5148 => x"ff", + 5149 => x"96", + 5150 => x"9f", + 5151 => x"80", + 5152 => x"34", + 5153 => x"1c", + 5154 => x"81", + 5155 => x"ab", + 5156 => x"a0", + 5157 => x"d4", + 5158 => x"fe", + 5159 => x"59", + 5160 => x"3f", + 5161 => x"53", + 5162 => x"51", + 5163 => x"3f", + 5164 => x"de", + 5165 => x"e7", + 5166 => x"2e", + 5167 => x"80", + 5168 => x"54", + 5169 => x"53", + 5170 => x"51", + 5171 => x"3f", + 5172 => x"80", + 5173 => x"ff", + 5174 => x"84", + 5175 => x"d2", + 5176 => x"ff", + 5177 => x"86", + 5178 => x"f2", + 5179 => x"1b", + 5180 => x"81", + 5181 => x"52", + 5182 => x"51", + 5183 => x"3f", + 5184 => x"ec", + 5185 => x"9e", + 5186 => x"d4", + 5187 => x"51", + 5188 => x"3f", + 5189 => x"87", + 5190 => x"52", + 5191 => x"9a", + 5192 => x"54", + 5193 => x"7a", + 5194 => x"ff", + 5195 => x"65", + 5196 => x"7a", + 5197 => x"8f", + 5198 => x"80", + 5199 => x"2e", + 5200 => x"9a", + 5201 => x"7a", + 5202 => x"a9", + 5203 => x"84", + 5204 => x"9e", + 5205 => x"0a", + 5206 => x"51", + 5207 => x"ff", + 5208 => x"7d", + 5209 => x"38", + 5210 => x"52", + 5211 => x"9e", + 5212 => x"55", + 5213 => x"62", + 5214 => x"74", + 5215 => x"75", + 5216 => x"7e", + 5217 => x"fe", + 5218 => x"c0", + 5219 => x"38", + 5220 => x"81", + 5221 => x"52", + 5222 => x"9e", + 5223 => x"16", + 5224 => x"56", + 5225 => x"38", + 5226 => x"77", + 5227 => x"8d", + 5228 => x"7d", + 5229 => x"38", + 5230 => x"57", + 5231 => x"83", + 5232 => x"76", + 5233 => x"7a", + 5234 => x"ff", + 5235 => x"81", + 5236 => x"81", + 5237 => x"16", + 5238 => x"56", + 5239 => x"38", + 5240 => x"83", + 5241 => x"86", + 5242 => x"ff", + 5243 => x"38", + 5244 => x"82", + 5245 => x"81", + 5246 => x"06", + 5247 => x"fe", + 5248 => x"53", + 5249 => x"51", + 5250 => x"3f", + 5251 => x"52", + 5252 => x"9c", + 5253 => x"be", + 5254 => x"75", + 5255 => x"81", + 5256 => x"0b", + 5257 => x"77", + 5258 => x"75", + 5259 => x"60", + 5260 => x"80", + 5261 => x"75", + 5262 => x"be", + 5263 => x"85", + 5264 => x"de", + 5265 => x"2a", + 5266 => x"75", + 5267 => x"81", + 5268 => x"87", + 5269 => x"52", + 5270 => x"51", + 5271 => x"3f", + 5272 => x"ca", + 5273 => x"9c", + 5274 => x"54", + 5275 => x"52", + 5276 => x"98", + 5277 => x"56", + 5278 => x"08", + 5279 => x"53", + 5280 => x"51", + 5281 => x"3f", + 5282 => x"de", + 5283 => x"38", + 5284 => x"56", + 5285 => x"56", + 5286 => x"de", + 5287 => x"75", + 5288 => x"0c", + 5289 => x"04", + 5290 => x"7d", + 5291 => x"80", + 5292 => x"05", + 5293 => x"76", + 5294 => x"38", + 5295 => x"11", + 5296 => x"53", + 5297 => x"79", + 5298 => x"3f", + 5299 => x"09", + 5300 => x"38", + 5301 => x"55", + 5302 => x"db", + 5303 => x"70", + 5304 => x"34", + 5305 => x"74", + 5306 => x"81", + 5307 => x"80", + 5308 => x"55", + 5309 => x"76", + 5310 => x"de", + 5311 => x"3d", + 5312 => x"3d", + 5313 => x"71", + 5314 => x"8e", + 5315 => x"29", + 5316 => x"05", + 5317 => x"04", + 5318 => x"51", + 5319 => x"81", + 5320 => x"80", + 5321 => x"d0", + 5322 => x"f2", + 5323 => x"a4", + 5324 => x"39", + 5325 => x"51", + 5326 => x"81", + 5327 => x"80", + 5328 => x"d0", + 5329 => x"d6", + 5330 => x"e8", + 5331 => x"39", + 5332 => x"51", + 5333 => x"81", + 5334 => x"80", + 5335 => x"d1", + 5336 => x"39", + 5337 => x"51", + 5338 => x"d1", + 5339 => x"39", + 5340 => x"51", + 5341 => x"d2", + 5342 => x"39", + 5343 => x"51", + 5344 => x"d2", + 5345 => x"39", + 5346 => x"51", + 5347 => x"d3", + 5348 => x"39", + 5349 => x"51", + 5350 => x"d3", + 5351 => x"87", + 5352 => x"3d", + 5353 => x"3d", + 5354 => x"56", + 5355 => x"e7", + 5356 => x"74", + 5357 => x"e8", + 5358 => x"39", + 5359 => x"74", + 5360 => x"b6", + 5361 => x"c0", + 5362 => x"51", + 5363 => x"3f", + 5364 => x"08", + 5365 => x"75", + 5366 => x"b8", + 5367 => x"c6", + 5368 => x"0d", + 5369 => x"0d", + 5370 => x"02", + 5371 => x"c7", + 5372 => x"73", + 5373 => x"5d", + 5374 => x"5c", + 5375 => x"81", + 5376 => x"ff", + 5377 => x"81", + 5378 => x"ff", + 5379 => x"80", + 5380 => x"27", + 5381 => x"79", + 5382 => x"38", + 5383 => x"a7", + 5384 => x"39", + 5385 => x"72", + 5386 => x"38", + 5387 => x"81", + 5388 => x"ff", + 5389 => x"89", + 5390 => x"f4", + 5391 => x"82", + 5392 => x"55", + 5393 => x"74", + 5394 => x"78", + 5395 => x"72", + 5396 => x"d3", + 5397 => x"8b", + 5398 => x"39", + 5399 => x"51", + 5400 => x"3f", + 5401 => x"a1", + 5402 => x"53", + 5403 => x"8e", + 5404 => x"52", + 5405 => x"51", + 5406 => x"3f", + 5407 => x"d4", + 5408 => x"85", + 5409 => x"15", + 5410 => x"fe", + 5411 => x"ff", + 5412 => x"d4", + 5413 => x"85", + 5414 => x"55", + 5415 => x"aa", + 5416 => x"70", + 5417 => x"26", + 5418 => x"9f", + 5419 => x"38", + 5420 => x"8b", + 5421 => x"fe", + 5422 => x"73", + 5423 => x"a0", + 5424 => x"f9", + 5425 => x"55", + 5426 => x"d4", + 5427 => x"84", + 5428 => x"16", + 5429 => x"56", + 5430 => x"3f", + 5431 => x"08", + 5432 => x"98", + 5433 => x"74", + 5434 => x"81", + 5435 => x"fe", + 5436 => x"81", + 5437 => x"98", + 5438 => x"2c", + 5439 => x"70", + 5440 => x"07", + 5441 => x"56", + 5442 => x"74", + 5443 => x"38", + 5444 => x"74", + 5445 => x"81", + 5446 => x"80", + 5447 => x"7a", + 5448 => x"76", + 5449 => x"38", + 5450 => x"81", + 5451 => x"8d", + 5452 => x"ec", + 5453 => x"02", + 5454 => x"e3", + 5455 => x"72", + 5456 => x"07", + 5457 => x"87", + 5458 => x"07", + 5459 => x"5a", + 5460 => x"57", + 5461 => x"38", + 5462 => x"52", + 5463 => x"52", + 5464 => x"de", + 5465 => x"c0", + 5466 => x"de", + 5467 => x"38", + 5468 => x"08", + 5469 => x"88", + 5470 => x"c0", + 5471 => x"3d", + 5472 => x"84", + 5473 => x"52", + 5474 => x"9b", + 5475 => x"c0", + 5476 => x"de", + 5477 => x"38", + 5478 => x"80", + 5479 => x"74", + 5480 => x"59", + 5481 => x"96", + 5482 => x"51", + 5483 => x"75", + 5484 => x"07", + 5485 => x"55", + 5486 => x"95", + 5487 => x"2e", + 5488 => x"d4", + 5489 => x"c0", + 5490 => x"52", + 5491 => x"d6", + 5492 => x"76", + 5493 => x"0c", + 5494 => x"04", + 5495 => x"7b", + 5496 => x"b3", + 5497 => x"58", + 5498 => x"53", + 5499 => x"51", + 5500 => x"81", + 5501 => x"a4", + 5502 => x"2e", + 5503 => x"81", + 5504 => x"98", + 5505 => x"7f", + 5506 => x"c0", + 5507 => x"7d", + 5508 => x"81", + 5509 => x"57", + 5510 => x"04", + 5511 => x"c0", + 5512 => x"0d", + 5513 => x"0d", + 5514 => x"33", + 5515 => x"53", + 5516 => x"52", + 5517 => x"ee", + 5518 => x"c0", + 5519 => x"80", + 5520 => x"d4", + 5521 => x"d4", + 5522 => x"db", + 5523 => x"81", + 5524 => x"ff", + 5525 => x"74", + 5526 => x"38", + 5527 => x"3f", + 5528 => x"04", + 5529 => x"87", + 5530 => x"08", + 5531 => x"a2", + 5532 => x"fe", + 5533 => x"81", + 5534 => x"fe", + 5535 => x"80", + 5536 => x"9f", + 5537 => x"2a", + 5538 => x"51", + 5539 => x"2e", + 5540 => x"51", + 5541 => x"3f", + 5542 => x"51", + 5543 => x"3f", + 5544 => x"f1", + 5545 => x"82", + 5546 => x"06", + 5547 => x"80", + 5548 => x"81", + 5549 => x"eb", + 5550 => x"8c", + 5551 => x"e3", + 5552 => x"fe", + 5553 => x"72", + 5554 => x"81", + 5555 => x"71", + 5556 => x"38", + 5557 => x"f1", + 5558 => x"d5", + 5559 => x"f3", + 5560 => x"51", + 5561 => x"3f", + 5562 => x"70", + 5563 => x"52", + 5564 => x"95", + 5565 => x"fe", + 5566 => x"81", + 5567 => x"fe", + 5568 => x"80", + 5569 => x"9b", + 5570 => x"2a", + 5571 => x"51", + 5572 => x"2e", + 5573 => x"51", + 5574 => x"3f", + 5575 => x"51", + 5576 => x"3f", + 5577 => x"f0", + 5578 => x"86", + 5579 => x"06", + 5580 => x"80", + 5581 => x"81", + 5582 => x"e7", + 5583 => x"d8", + 5584 => x"df", + 5585 => x"fe", + 5586 => x"72", + 5587 => x"81", + 5588 => x"71", + 5589 => x"38", + 5590 => x"f0", + 5591 => x"d5", + 5592 => x"f2", + 5593 => x"51", + 5594 => x"3f", + 5595 => x"70", + 5596 => x"52", + 5597 => x"95", + 5598 => x"fe", + 5599 => x"81", + 5600 => x"fe", + 5601 => x"80", + 5602 => x"97", + 5603 => x"cb", + 5604 => x"0d", + 5605 => x"0d", + 5606 => x"70", + 5607 => x"73", + 5608 => x"f0", + 5609 => x"73", + 5610 => x"15", + 5611 => x"e4", + 5612 => x"54", + 5613 => x"70", + 5614 => x"57", + 5615 => x"a0", + 5616 => x"81", + 5617 => x"2e", + 5618 => x"e5", + 5619 => x"ff", + 5620 => x"a0", + 5621 => x"06", + 5622 => x"74", + 5623 => x"56", + 5624 => x"75", + 5625 => x"db", + 5626 => x"08", + 5627 => x"52", + 5628 => x"9e", + 5629 => x"c0", + 5630 => x"84", + 5631 => x"72", + 5632 => x"a3", + 5633 => x"70", + 5634 => x"57", + 5635 => x"27", + 5636 => x"53", + 5637 => x"c0", + 5638 => x"0d", + 5639 => x"0d", + 5640 => x"55", + 5641 => x"52", + 5642 => x"e8", + 5643 => x"db", + 5644 => x"73", + 5645 => x"53", + 5646 => x"52", + 5647 => x"51", + 5648 => x"3f", + 5649 => x"08", + 5650 => x"de", + 5651 => x"80", + 5652 => x"31", + 5653 => x"73", + 5654 => x"34", + 5655 => x"33", + 5656 => x"2e", + 5657 => x"ac", + 5658 => x"c4", + 5659 => x"75", + 5660 => x"3f", + 5661 => x"08", + 5662 => x"38", + 5663 => x"08", + 5664 => x"be", + 5665 => x"81", + 5666 => x"c6", + 5667 => x"0b", + 5668 => x"34", + 5669 => x"33", + 5670 => x"2e", + 5671 => x"89", + 5672 => x"75", + 5673 => x"d8", + 5674 => x"81", + 5675 => x"87", + 5676 => x"cb", + 5677 => x"70", + 5678 => x"c0", + 5679 => x"81", + 5680 => x"ff", + 5681 => x"81", + 5682 => x"81", + 5683 => x"78", + 5684 => x"81", + 5685 => x"81", + 5686 => x"99", + 5687 => x"59", + 5688 => x"3f", + 5689 => x"52", + 5690 => x"51", + 5691 => x"3f", + 5692 => x"08", + 5693 => x"38", + 5694 => x"51", + 5695 => x"81", + 5696 => x"81", + 5697 => x"fe", + 5698 => x"99", + 5699 => x"5a", + 5700 => x"79", + 5701 => x"3f", + 5702 => x"f8", + 5703 => x"f5", + 5704 => x"c0", + 5705 => x"70", + 5706 => x"59", + 5707 => x"2e", + 5708 => x"78", + 5709 => x"80", + 5710 => x"ab", + 5711 => x"38", + 5712 => x"a4", + 5713 => x"2e", + 5714 => x"78", + 5715 => x"38", + 5716 => x"ff", + 5717 => x"de", + 5718 => x"2e", + 5719 => x"78", + 5720 => x"ad", + 5721 => x"39", + 5722 => x"2e", + 5723 => x"78", + 5724 => x"90", + 5725 => x"2e", + 5726 => x"78", + 5727 => x"8b", + 5728 => x"39", + 5729 => x"2e", + 5730 => x"78", + 5731 => x"88", + 5732 => x"a2", + 5733 => x"d5", + 5734 => x"38", + 5735 => x"24", + 5736 => x"80", + 5737 => x"a7", + 5738 => x"d0", + 5739 => x"78", + 5740 => x"8a", + 5741 => x"fe", + 5742 => x"d1", + 5743 => x"38", + 5744 => x"2e", + 5745 => x"8e", + 5746 => x"81", + 5747 => x"c3", + 5748 => x"82", + 5749 => x"78", + 5750 => x"8d", + 5751 => x"80", + 5752 => x"ec", + 5753 => x"39", + 5754 => x"2e", + 5755 => x"78", + 5756 => x"8e", + 5757 => x"be", + 5758 => x"fe", + 5759 => x"fe", + 5760 => x"ff", + 5761 => x"81", + 5762 => x"88", + 5763 => x"90", + 5764 => x"39", + 5765 => x"f0", + 5766 => x"f8", + 5767 => x"81", + 5768 => x"de", + 5769 => x"2e", + 5770 => x"63", + 5771 => x"80", + 5772 => x"cb", + 5773 => x"02", + 5774 => x"33", + 5775 => x"dd", + 5776 => x"c0", + 5777 => x"06", + 5778 => x"38", + 5779 => x"51", + 5780 => x"3f", + 5781 => x"ab", + 5782 => x"b0", + 5783 => x"39", + 5784 => x"f4", + 5785 => x"f8", + 5786 => x"81", + 5787 => x"de", + 5788 => x"2e", + 5789 => x"80", + 5790 => x"02", + 5791 => x"33", + 5792 => x"e6", + 5793 => x"c0", + 5794 => x"d7", + 5795 => x"fc", + 5796 => x"fe", + 5797 => x"fe", + 5798 => x"ff", + 5799 => x"81", + 5800 => x"80", + 5801 => x"63", + 5802 => x"d7", + 5803 => x"fe", + 5804 => x"fe", + 5805 => x"ff", + 5806 => x"81", + 5807 => x"86", + 5808 => x"c0", + 5809 => x"53", + 5810 => x"52", + 5811 => x"fe", + 5812 => x"80", + 5813 => x"53", + 5814 => x"84", + 5815 => x"df", + 5816 => x"ff", + 5817 => x"81", + 5818 => x"81", + 5819 => x"d7", + 5820 => x"f8", + 5821 => x"5d", + 5822 => x"b7", + 5823 => x"05", + 5824 => x"d0", + 5825 => x"c0", + 5826 => x"fe", + 5827 => x"5b", + 5828 => x"3f", + 5829 => x"de", + 5830 => x"7a", + 5831 => x"3f", + 5832 => x"b7", + 5833 => x"05", + 5834 => x"a8", + 5835 => x"c0", + 5836 => x"fe", + 5837 => x"5b", + 5838 => x"3f", + 5839 => x"08", + 5840 => x"f8", + 5841 => x"fe", + 5842 => x"81", + 5843 => x"b8", + 5844 => x"05", + 5845 => x"e5", + 5846 => x"db", + 5847 => x"de", + 5848 => x"56", + 5849 => x"de", + 5850 => x"ff", + 5851 => x"53", + 5852 => x"51", + 5853 => x"81", + 5854 => x"80", + 5855 => x"38", + 5856 => x"08", + 5857 => x"3f", + 5858 => x"b7", + 5859 => x"11", + 5860 => x"05", + 5861 => x"83", + 5862 => x"c0", + 5863 => x"fa", + 5864 => x"3d", + 5865 => x"53", + 5866 => x"51", + 5867 => x"3f", + 5868 => x"08", + 5869 => x"cb", + 5870 => x"fe", + 5871 => x"fe", + 5872 => x"fe", + 5873 => x"81", + 5874 => x"86", + 5875 => x"c0", + 5876 => x"d7", + 5877 => x"f6", + 5878 => x"63", + 5879 => x"7b", + 5880 => x"38", + 5881 => x"7a", + 5882 => x"5c", + 5883 => x"26", + 5884 => x"d5", + 5885 => x"fe", + 5886 => x"fe", + 5887 => x"fe", + 5888 => x"81", + 5889 => x"80", + 5890 => x"db", + 5891 => x"78", + 5892 => x"38", + 5893 => x"08", + 5894 => x"39", + 5895 => x"33", + 5896 => x"2e", + 5897 => x"db", + 5898 => x"bc", + 5899 => x"d6", + 5900 => x"80", + 5901 => x"81", + 5902 => x"44", + 5903 => x"db", + 5904 => x"78", + 5905 => x"38", + 5906 => x"08", + 5907 => x"81", + 5908 => x"59", + 5909 => x"88", + 5910 => x"ac", + 5911 => x"39", + 5912 => x"08", + 5913 => x"44", + 5914 => x"f0", + 5915 => x"f8", + 5916 => x"fd", + 5917 => x"de", + 5918 => x"de", + 5919 => x"d4", + 5920 => x"80", + 5921 => x"81", + 5922 => x"43", + 5923 => x"81", + 5924 => x"59", + 5925 => x"88", + 5926 => x"98", + 5927 => x"39", + 5928 => x"33", + 5929 => x"2e", + 5930 => x"db", + 5931 => x"aa", + 5932 => x"d7", + 5933 => x"80", + 5934 => x"81", + 5935 => x"43", + 5936 => x"db", + 5937 => x"78", + 5938 => x"38", + 5939 => x"08", + 5940 => x"81", + 5941 => x"88", + 5942 => x"3d", + 5943 => x"53", + 5944 => x"51", + 5945 => x"3f", + 5946 => x"08", + 5947 => x"38", + 5948 => x"59", + 5949 => x"83", + 5950 => x"79", + 5951 => x"38", + 5952 => x"88", + 5953 => x"2e", + 5954 => x"42", + 5955 => x"51", + 5956 => x"3f", + 5957 => x"54", + 5958 => x"52", + 5959 => x"c5", + 5960 => x"f4", + 5961 => x"39", + 5962 => x"f4", + 5963 => x"f8", + 5964 => x"fb", + 5965 => x"de", + 5966 => x"2e", + 5967 => x"b7", + 5968 => x"11", + 5969 => x"05", + 5970 => x"cf", + 5971 => x"c0", + 5972 => x"a5", + 5973 => x"02", + 5974 => x"33", + 5975 => x"81", + 5976 => x"3d", + 5977 => x"53", + 5978 => x"51", + 5979 => x"3f", + 5980 => x"08", + 5981 => x"8b", + 5982 => x"33", + 5983 => x"d8", + 5984 => x"f9", + 5985 => x"f8", + 5986 => x"fe", + 5987 => x"79", + 5988 => x"59", + 5989 => x"f6", + 5990 => x"79", + 5991 => x"b7", + 5992 => x"11", + 5993 => x"05", + 5994 => x"ef", + 5995 => x"c0", + 5996 => x"91", + 5997 => x"02", + 5998 => x"33", + 5999 => x"81", + 6000 => x"b5", + 6001 => x"8c", + 6002 => x"f6", + 6003 => x"39", + 6004 => x"e8", + 6005 => x"f8", + 6006 => x"fc", + 6007 => x"de", + 6008 => x"2e", + 6009 => x"b7", + 6010 => x"11", + 6011 => x"05", + 6012 => x"99", + 6013 => x"c0", + 6014 => x"a6", + 6015 => x"02", + 6016 => x"79", + 6017 => x"5b", + 6018 => x"b7", + 6019 => x"11", + 6020 => x"05", + 6021 => x"f5", + 6022 => x"c0", + 6023 => x"f5", + 6024 => x"70", + 6025 => x"81", + 6026 => x"fe", + 6027 => x"80", + 6028 => x"51", + 6029 => x"3f", + 6030 => x"33", + 6031 => x"2e", + 6032 => x"78", + 6033 => x"38", + 6034 => x"41", + 6035 => x"3d", + 6036 => x"53", + 6037 => x"51", + 6038 => x"3f", + 6039 => x"08", + 6040 => x"38", + 6041 => x"be", + 6042 => x"70", + 6043 => x"23", + 6044 => x"ae", + 6045 => x"8c", + 6046 => x"c6", + 6047 => x"39", + 6048 => x"e8", + 6049 => x"f8", + 6050 => x"fb", + 6051 => x"de", + 6052 => x"2e", + 6053 => x"b7", + 6054 => x"11", + 6055 => x"05", + 6056 => x"e9", + 6057 => x"c0", + 6058 => x"a1", + 6059 => x"71", + 6060 => x"84", + 6061 => x"3d", + 6062 => x"53", + 6063 => x"51", + 6064 => x"3f", + 6065 => x"08", + 6066 => x"b7", + 6067 => x"08", + 6068 => x"d8", + 6069 => x"f6", + 6070 => x"f8", + 6071 => x"fe", + 6072 => x"79", + 6073 => x"59", + 6074 => x"f4", + 6075 => x"79", + 6076 => x"b7", + 6077 => x"11", + 6078 => x"05", + 6079 => x"8d", + 6080 => x"c0", + 6081 => x"8d", + 6082 => x"71", + 6083 => x"84", + 6084 => x"b9", + 6085 => x"8c", + 6086 => x"a6", + 6087 => x"39", + 6088 => x"f4", + 6089 => x"f8", + 6090 => x"f7", + 6091 => x"de", + 6092 => x"df", + 6093 => x"d4", + 6094 => x"80", + 6095 => x"81", + 6096 => x"44", + 6097 => x"81", + 6098 => x"59", + 6099 => x"88", + 6100 => x"94", + 6101 => x"39", + 6102 => x"33", + 6103 => x"2e", + 6104 => x"db", + 6105 => x"ab", + 6106 => x"d7", + 6107 => x"80", + 6108 => x"81", + 6109 => x"44", + 6110 => x"db", + 6111 => x"78", + 6112 => x"38", + 6113 => x"08", + 6114 => x"81", + 6115 => x"fc", + 6116 => x"b7", + 6117 => x"11", + 6118 => x"05", + 6119 => x"fb", + 6120 => x"c0", + 6121 => x"38", + 6122 => x"33", + 6123 => x"2e", + 6124 => x"db", + 6125 => x"80", + 6126 => x"db", + 6127 => x"78", + 6128 => x"38", + 6129 => x"08", + 6130 => x"81", + 6131 => x"59", + 6132 => x"88", + 6133 => x"a0", + 6134 => x"39", + 6135 => x"33", + 6136 => x"2e", + 6137 => x"db", + 6138 => x"99", + 6139 => x"d2", + 6140 => x"80", + 6141 => x"81", + 6142 => x"43", + 6143 => x"db", + 6144 => x"05", + 6145 => x"fe", + 6146 => x"fe", + 6147 => x"fe", + 6148 => x"81", + 6149 => x"86", + 6150 => x"c0", + 6151 => x"d8", + 6152 => x"ee", + 6153 => x"5a", + 6154 => x"9d", + 6155 => x"59", + 6156 => x"09", + 6157 => x"38", + 6158 => x"52", + 6159 => x"51", + 6160 => x"3f", + 6161 => x"e0", + 6162 => x"9c", + 6163 => x"81", + 6164 => x"fe", + 6165 => x"82", + 6166 => x"da", + 6167 => x"39", + 6168 => x"51", + 6169 => x"3f", + 6170 => x"ec", + 6171 => x"93", + 6172 => x"81", + 6173 => x"94", + 6174 => x"80", + 6175 => x"c0", + 6176 => x"81", + 6177 => x"fe", + 6178 => x"f0", + 6179 => x"d9", + 6180 => x"ed", + 6181 => x"80", + 6182 => x"c0", + 6183 => x"8c", + 6184 => x"87", + 6185 => x"0c", + 6186 => x"b7", + 6187 => x"11", + 6188 => x"05", + 6189 => x"e3", + 6190 => x"c0", + 6191 => x"f0", + 6192 => x"52", + 6193 => x"51", + 6194 => x"3f", + 6195 => x"04", + 6196 => x"f4", + 6197 => x"f8", + 6198 => x"f4", + 6199 => x"de", + 6200 => x"2e", + 6201 => x"63", + 6202 => x"c0", + 6203 => x"b6", + 6204 => x"78", + 6205 => x"c0", + 6206 => x"de", + 6207 => x"2e", + 6208 => x"81", + 6209 => x"52", + 6210 => x"51", + 6211 => x"3f", + 6212 => x"81", + 6213 => x"fe", + 6214 => x"fe", + 6215 => x"ef", + 6216 => x"da", + 6217 => x"ec", + 6218 => x"59", + 6219 => x"fe", + 6220 => x"ef", + 6221 => x"70", + 6222 => x"78", + 6223 => x"c3", + 6224 => x"2e", + 6225 => x"81", + 6226 => x"5a", + 6227 => x"2e", + 6228 => x"b7", + 6229 => x"05", + 6230 => x"f8", + 6231 => x"c0", + 6232 => x"5b", + 6233 => x"b2", + 6234 => x"24", + 6235 => x"81", + 6236 => x"80", + 6237 => x"83", + 6238 => x"80", + 6239 => x"da", + 6240 => x"55", + 6241 => x"54", + 6242 => x"da", + 6243 => x"3d", + 6244 => x"51", + 6245 => x"3f", + 6246 => x"da", + 6247 => x"3d", + 6248 => x"51", + 6249 => x"3f", + 6250 => x"55", + 6251 => x"54", + 6252 => x"da", + 6253 => x"3d", + 6254 => x"51", + 6255 => x"3f", + 6256 => x"54", + 6257 => x"da", + 6258 => x"3d", + 6259 => x"51", + 6260 => x"3f", + 6261 => x"58", + 6262 => x"57", + 6263 => x"81", + 6264 => x"05", + 6265 => x"84", + 6266 => x"84", + 6267 => x"b7", + 6268 => x"05", + 6269 => x"3f", + 6270 => x"08", + 6271 => x"08", + 6272 => x"70", + 6273 => x"25", + 6274 => x"5e", + 6275 => x"92", + 6276 => x"2e", + 6277 => x"1c", + 6278 => x"06", + 6279 => x"fe", + 6280 => x"81", + 6281 => x"32", + 6282 => x"8a", + 6283 => x"2e", + 6284 => x"ed", + 6285 => x"da", + 6286 => x"ef", + 6287 => x"c3", + 6288 => x"0d", + 6289 => x"de", + 6290 => x"c0", + 6291 => x"08", + 6292 => x"84", + 6293 => x"51", + 6294 => x"3f", + 6295 => x"08", + 6296 => x"08", + 6297 => x"84", + 6298 => x"51", + 6299 => x"3f", + 6300 => x"c0", + 6301 => x"0c", + 6302 => x"9c", + 6303 => x"55", + 6304 => x"52", + 6305 => x"cd", + 6306 => x"de", + 6307 => x"2b", + 6308 => x"53", + 6309 => x"52", + 6310 => x"cd", + 6311 => x"81", + 6312 => x"07", + 6313 => x"80", + 6314 => x"c0", + 6315 => x"8c", + 6316 => x"87", + 6317 => x"0c", + 6318 => x"81", + 6319 => x"a2", + 6320 => x"de", + 6321 => x"de", + 6322 => x"e7", + 6323 => x"da", + 6324 => x"db", + 6325 => x"da", + 6326 => x"e8", + 6327 => x"ac", + 6328 => x"e7", + 6329 => x"51", + 6330 => x"eb", + 6331 => x"04", + 6332 => x"00", + 6333 => x"ff", + 6334 => x"ff", + 6335 => x"ff", + 6336 => x"00", + 6337 => x"00", + 6338 => x"00", + 6339 => x"00", + 6340 => x"00", + 6341 => x"00", + 6342 => x"00", + 6343 => x"00", + 6344 => x"00", + 6345 => x"00", + 6346 => x"00", + 6347 => x"00", + 6348 => x"00", + 6349 => x"00", + 6350 => x"00", + 6351 => x"00", + 6352 => x"00", + 6353 => x"00", + 6354 => x"00", + 6355 => x"00", + 6356 => x"00", + 6357 => x"00", + 6358 => x"00", + 6359 => x"00", + 6360 => x"00", + 6361 => x"25", + 6362 => x"64", + 6363 => x"20", + 6364 => x"25", + 6365 => x"64", + 6366 => x"25", + 6367 => x"53", + 6368 => x"43", + 6369 => x"69", + 6370 => x"61", + 6371 => x"6e", + 6372 => x"20", + 6373 => x"6f", + 6374 => x"6f", + 6375 => x"6f", + 6376 => x"67", + 6377 => x"3a", + 6378 => x"76", + 6379 => x"73", + 6380 => x"70", + 6381 => x"65", + 6382 => x"64", + 6383 => x"20", + 6384 => x"57", + 6385 => x"44", + 6386 => x"20", + 6387 => x"30", + 6388 => x"25", + 6389 => x"29", + 6390 => x"20", + 6391 => x"53", + 6392 => x"4d", + 6393 => x"20", + 6394 => x"30", + 6395 => x"25", + 6396 => x"29", + 6397 => x"20", + 6398 => x"49", + 6399 => x"20", + 6400 => x"4d", + 6401 => x"30", + 6402 => x"25", + 6403 => x"29", + 6404 => x"20", + 6405 => x"42", + 6406 => x"20", + 6407 => x"20", + 6408 => x"30", + 6409 => x"25", + 6410 => x"29", + 6411 => x"20", + 6412 => x"52", + 6413 => x"20", + 6414 => x"20", + 6415 => x"30", + 6416 => x"25", + 6417 => x"29", + 6418 => x"20", + 6419 => x"53", + 6420 => x"41", + 6421 => x"20", + 6422 => x"65", + 6423 => x"65", + 6424 => x"25", + 6425 => x"29", + 6426 => x"20", + 6427 => x"54", + 6428 => x"52", + 6429 => x"20", + 6430 => x"69", + 6431 => x"73", + 6432 => x"25", + 6433 => x"29", + 6434 => x"20", + 6435 => x"49", + 6436 => x"20", + 6437 => x"4c", + 6438 => x"68", + 6439 => x"65", + 6440 => x"25", + 6441 => x"29", + 6442 => x"20", + 6443 => x"57", + 6444 => x"42", + 6445 => x"20", + 6446 => x"0a", + 6447 => x"20", + 6448 => x"57", + 6449 => x"32", + 6450 => x"20", + 6451 => x"49", + 6452 => x"4c", + 6453 => x"20", + 6454 => x"50", + 6455 => x"00", + 6456 => x"20", + 6457 => x"53", + 6458 => x"00", + 6459 => x"41", + 6460 => x"65", + 6461 => x"73", + 6462 => x"20", + 6463 => x"43", + 6464 => x"52", + 6465 => x"74", + 6466 => x"63", + 6467 => x"20", + 6468 => x"72", + 6469 => x"20", + 6470 => x"30", + 6471 => x"00", + 6472 => x"20", + 6473 => x"43", + 6474 => x"4d", + 6475 => x"72", + 6476 => x"74", + 6477 => x"20", + 6478 => x"72", + 6479 => x"20", + 6480 => x"30", + 6481 => x"00", + 6482 => x"20", + 6483 => x"53", + 6484 => x"6b", + 6485 => x"61", + 6486 => x"41", + 6487 => x"65", + 6488 => x"20", + 6489 => x"20", + 6490 => x"30", + 6491 => x"00", + 6492 => x"4d", + 6493 => x"3a", + 6494 => x"20", + 6495 => x"5a", + 6496 => x"49", + 6497 => x"20", + 6498 => x"20", + 6499 => x"20", + 6500 => x"20", + 6501 => x"20", + 6502 => x"30", + 6503 => x"00", + 6504 => x"20", + 6505 => x"53", + 6506 => x"65", + 6507 => x"6c", + 6508 => x"20", + 6509 => x"71", + 6510 => x"20", + 6511 => x"20", + 6512 => x"64", + 6513 => x"34", + 6514 => x"7a", + 6515 => x"20", + 6516 => x"53", + 6517 => x"4d", + 6518 => x"6f", + 6519 => x"46", + 6520 => x"20", + 6521 => x"20", + 6522 => x"20", + 6523 => x"64", + 6524 => x"34", + 6525 => x"7a", + 6526 => x"20", + 6527 => x"57", + 6528 => x"62", + 6529 => x"20", + 6530 => x"41", + 6531 => x"6c", + 6532 => x"20", + 6533 => x"71", + 6534 => x"64", + 6535 => x"34", + 6536 => x"7a", + 6537 => x"53", + 6538 => x"6c", + 6539 => x"4d", + 6540 => x"75", + 6541 => x"46", + 6542 => x"00", + 6543 => x"45", + 6544 => x"45", + 6545 => x"69", + 6546 => x"55", + 6547 => x"6f", + 6548 => x"53", + 6549 => x"22", + 6550 => x"3a", + 6551 => x"3e", + 6552 => x"7c", + 6553 => x"46", + 6554 => x"46", + 6555 => x"32", + 6556 => x"eb", + 6557 => x"53", + 6558 => x"35", + 6559 => x"4e", + 6560 => x"41", + 6561 => x"20", + 6562 => x"41", + 6563 => x"20", + 6564 => x"4e", + 6565 => x"41", + 6566 => x"20", + 6567 => x"41", + 6568 => x"20", + 6569 => x"00", + 6570 => x"00", + 6571 => x"00", + 6572 => x"00", + 6573 => x"80", + 6574 => x"8e", + 6575 => x"45", + 6576 => x"49", + 6577 => x"90", + 6578 => x"99", + 6579 => x"59", + 6580 => x"9c", + 6581 => x"41", + 6582 => x"a5", + 6583 => x"a8", + 6584 => x"ac", + 6585 => x"b0", + 6586 => x"b4", + 6587 => x"b8", + 6588 => x"bc", + 6589 => x"c0", + 6590 => x"c4", + 6591 => x"c8", + 6592 => x"cc", + 6593 => x"d0", + 6594 => x"d4", + 6595 => x"d8", + 6596 => x"dc", + 6597 => x"e0", + 6598 => x"e4", + 6599 => x"e8", + 6600 => x"ec", + 6601 => x"f0", + 6602 => x"f4", + 6603 => x"f8", + 6604 => x"fc", + 6605 => x"2b", + 6606 => x"3d", + 6607 => x"5c", + 6608 => x"3c", + 6609 => x"7f", + 6610 => x"00", + 6611 => x"00", + 6612 => x"01", + 6613 => x"00", + 6614 => x"00", + 6615 => x"00", + 6616 => x"00", + 6617 => x"00", + 6618 => x"64", + 6619 => x"74", + 6620 => x"64", + 6621 => x"74", + 6622 => x"66", + 6623 => x"74", + 6624 => x"66", + 6625 => x"64", + 6626 => x"66", + 6627 => x"63", + 6628 => x"6d", + 6629 => x"61", + 6630 => x"6d", + 6631 => x"70", + 6632 => x"6d", + 6633 => x"68", + 6634 => x"6d", + 6635 => x"6d", + 6636 => x"6d", + 6637 => x"68", + 6638 => x"68", + 6639 => x"68", + 6640 => x"68", + 6641 => x"63", + 6642 => x"00", + 6643 => x"6a", + 6644 => x"72", + 6645 => x"61", + 6646 => x"72", + 6647 => x"74", + 6648 => x"69", + 6649 => x"00", + 6650 => x"74", + 6651 => x"00", + 6652 => x"44", + 6653 => x"20", + 6654 => x"6f", + 6655 => x"49", + 6656 => x"72", + 6657 => x"20", + 6658 => x"6f", + 6659 => x"00", + 6660 => x"44", + 6661 => x"20", + 6662 => x"20", + 6663 => x"64", + 6664 => x"00", + 6665 => x"4e", + 6666 => x"69", + 6667 => x"66", + 6668 => x"64", + 6669 => x"4e", + 6670 => x"61", + 6671 => x"66", + 6672 => x"64", + 6673 => x"49", + 6674 => x"6c", + 6675 => x"66", + 6676 => x"6e", + 6677 => x"2e", + 6678 => x"41", + 6679 => x"73", + 6680 => x"65", + 6681 => x"64", + 6682 => x"46", + 6683 => x"20", + 6684 => x"65", + 6685 => x"20", + 6686 => x"73", + 6687 => x"0a", + 6688 => x"46", + 6689 => x"20", + 6690 => x"64", + 6691 => x"69", + 6692 => x"6c", + 6693 => x"0a", + 6694 => x"53", + 6695 => x"73", + 6696 => x"69", + 6697 => x"70", + 6698 => x"65", + 6699 => x"64", + 6700 => x"44", + 6701 => x"65", + 6702 => x"6d", + 6703 => x"20", + 6704 => x"69", + 6705 => x"6c", + 6706 => x"0a", + 6707 => x"44", + 6708 => x"20", + 6709 => x"20", + 6710 => x"62", + 6711 => x"2e", + 6712 => x"4e", + 6713 => x"6f", + 6714 => x"74", + 6715 => x"65", + 6716 => x"6c", + 6717 => x"73", + 6718 => x"20", + 6719 => x"6e", + 6720 => x"6e", + 6721 => x"73", + 6722 => x"00", + 6723 => x"46", + 6724 => x"61", + 6725 => x"62", + 6726 => x"65", + 6727 => x"00", + 6728 => x"54", + 6729 => x"6f", + 6730 => x"20", + 6731 => x"72", + 6732 => x"6f", + 6733 => x"61", + 6734 => x"6c", + 6735 => x"2e", + 6736 => x"46", + 6737 => x"20", + 6738 => x"6c", + 6739 => x"65", + 6740 => x"00", + 6741 => x"49", + 6742 => x"66", + 6743 => x"69", + 6744 => x"20", + 6745 => x"6f", + 6746 => x"0a", + 6747 => x"54", + 6748 => x"6d", + 6749 => x"20", + 6750 => x"6e", + 6751 => x"6c", + 6752 => x"0a", + 6753 => x"50", + 6754 => x"6d", + 6755 => x"72", + 6756 => x"6e", + 6757 => x"72", + 6758 => x"2e", + 6759 => x"53", + 6760 => x"65", + 6761 => x"0a", + 6762 => x"55", + 6763 => x"6f", + 6764 => x"65", + 6765 => x"72", + 6766 => x"0a", + 6767 => x"20", + 6768 => x"65", + 6769 => x"73", + 6770 => x"20", + 6771 => x"20", + 6772 => x"65", + 6773 => x"65", + 6774 => x"00", + 6775 => x"25", + 6776 => x"00", + 6777 => x"3a", + 6778 => x"25", + 6779 => x"00", + 6780 => x"20", + 6781 => x"20", + 6782 => x"00", + 6783 => x"25", + 6784 => x"00", + 6785 => x"20", + 6786 => x"20", + 6787 => x"7c", + 6788 => x"72", + 6789 => x"00", + 6790 => x"5a", + 6791 => x"41", + 6792 => x"0a", + 6793 => x"25", + 6794 => x"00", + 6795 => x"32", + 6796 => x"32", + 6797 => x"31", + 6798 => x"76", + 6799 => x"00", + 6800 => x"20", + 6801 => x"2c", + 6802 => x"76", + 6803 => x"32", + 6804 => x"25", + 6805 => x"73", + 6806 => x"0a", + 6807 => x"5a", + 6808 => x"41", + 6809 => x"74", + 6810 => x"75", + 6811 => x"48", + 6812 => x"6c", + 6813 => x"00", + 6814 => x"54", + 6815 => x"72", + 6816 => x"74", + 6817 => x"75", + 6818 => x"00", + 6819 => x"50", + 6820 => x"69", + 6821 => x"72", + 6822 => x"74", + 6823 => x"49", + 6824 => x"4c", + 6825 => x"20", + 6826 => x"65", + 6827 => x"70", + 6828 => x"49", + 6829 => x"4c", + 6830 => x"20", + 6831 => x"65", + 6832 => x"70", + 6833 => x"55", + 6834 => x"30", + 6835 => x"20", + 6836 => x"65", + 6837 => x"70", + 6838 => x"55", + 6839 => x"30", + 6840 => x"20", + 6841 => x"65", + 6842 => x"70", + 6843 => x"55", + 6844 => x"31", + 6845 => x"20", + 6846 => x"65", + 6847 => x"70", + 6848 => x"55", + 6849 => x"31", + 6850 => x"20", + 6851 => x"65", + 6852 => x"70", + 6853 => x"53", + 6854 => x"69", + 6855 => x"75", + 6856 => x"69", + 6857 => x"2e", + 6858 => x"00", + 6859 => x"45", + 6860 => x"6c", + 6861 => x"20", + 6862 => x"65", + 6863 => x"2e", + 6864 => x"61", + 6865 => x"65", + 6866 => x"2e", + 6867 => x"00", + 6868 => x"30", + 6869 => x"46", + 6870 => x"65", + 6871 => x"6f", + 6872 => x"69", + 6873 => x"6c", + 6874 => x"20", + 6875 => x"63", + 6876 => x"20", + 6877 => x"70", + 6878 => x"73", + 6879 => x"6e", + 6880 => x"6d", + 6881 => x"61", + 6882 => x"2e", + 6883 => x"2a", + 6884 => x"42", + 6885 => x"64", + 6886 => x"20", + 6887 => x"0a", + 6888 => x"49", + 6889 => x"69", + 6890 => x"73", + 6891 => x"0a", + 6892 => x"46", + 6893 => x"65", + 6894 => x"6f", + 6895 => x"69", + 6896 => x"6c", + 6897 => x"2e", + 6898 => x"72", + 6899 => x"64", + 6900 => x"25", + 6901 => x"43", + 6902 => x"72", + 6903 => x"2e", + 6904 => x"00", + 6905 => x"44", + 6906 => x"20", + 6907 => x"6f", + 6908 => x"00", + 6909 => x"0a", + 6910 => x"70", + 6911 => x"65", + 6912 => x"25", + 6913 => x"20", + 6914 => x"58", + 6915 => x"3f", + 6916 => x"00", + 6917 => x"25", + 6918 => x"20", + 6919 => x"58", + 6920 => x"25", + 6921 => x"20", + 6922 => x"58", + 6923 => x"53", + 6924 => x"63", + 6925 => x"67", + 6926 => x"00", + 6927 => x"25", + 6928 => x"78", + 6929 => x"30", + 6930 => x"0a", + 6931 => x"44", + 6932 => x"62", + 6933 => x"67", + 6934 => x"74", + 6935 => x"75", + 6936 => x"0a", + 6937 => x"45", + 6938 => x"6c", + 6939 => x"20", + 6940 => x"65", + 6941 => x"70", + 6942 => x"00", + 6943 => x"44", + 6944 => x"62", + 6945 => x"20", + 6946 => x"74", + 6947 => x"66", + 6948 => x"45", + 6949 => x"6c", + 6950 => x"20", + 6951 => x"74", + 6952 => x"66", + 6953 => x"45", + 6954 => x"75", + 6955 => x"67", + 6956 => x"64", + 6957 => x"20", + 6958 => x"78", + 6959 => x"2e", + 6960 => x"43", + 6961 => x"69", + 6962 => x"63", + 6963 => x"20", + 6964 => x"30", + 6965 => x"2e", + 6966 => x"00", + 6967 => x"43", + 6968 => x"20", + 6969 => x"75", + 6970 => x"64", + 6971 => x"64", + 6972 => x"25", + 6973 => x"0a", + 6974 => x"52", + 6975 => x"61", + 6976 => x"6e", + 6977 => x"70", + 6978 => x"63", + 6979 => x"6f", + 6980 => x"2e", + 6981 => x"43", + 6982 => x"20", + 6983 => x"6f", + 6984 => x"6e", + 6985 => x"2e", + 6986 => x"5a", + 6987 => x"62", + 6988 => x"25", + 6989 => x"25", + 6990 => x"73", + 6991 => x"00", + 6992 => x"25", + 6993 => x"25", + 6994 => x"73", + 6995 => x"25", + 6996 => x"25", + 6997 => x"42", + 6998 => x"63", + 6999 => x"61", + 7000 => x"0a", + 7001 => x"52", + 7002 => x"69", + 7003 => x"2e", + 7004 => x"45", + 7005 => x"6c", + 7006 => x"20", + 7007 => x"65", + 7008 => x"70", + 7009 => x"2e", + 7010 => x"00", + 7011 => x"00", + 7012 => x"00", + 7013 => x"00", + 7014 => x"00", + 7015 => x"00", + 7016 => x"00", + 7017 => x"00", + 7018 => x"00", + 7019 => x"01", + 7020 => x"01", + 7021 => x"00", + 7022 => x"00", + 7023 => x"00", + 7024 => x"00", + 7025 => x"05", + 7026 => x"05", + 7027 => x"05", + 7028 => x"00", + 7029 => x"01", + 7030 => x"01", + 7031 => x"01", + 7032 => x"01", + 7033 => x"00", + 7034 => x"01", + 7035 => x"00", + 7036 => x"00", + 7037 => x"01", + 7038 => x"00", + 7039 => x"00", + 7040 => x"00", + 7041 => x"01", + 7042 => x"00", + 7043 => x"00", + 7044 => x"00", + 7045 => x"01", + 7046 => x"00", + 7047 => x"00", + 7048 => x"00", + 7049 => x"01", + 7050 => x"00", + 7051 => x"00", + 7052 => x"00", + 7053 => x"01", + 7054 => x"00", + 7055 => x"00", + 7056 => x"00", + 7057 => x"01", + 7058 => x"00", + 7059 => x"00", + 7060 => x"00", + 7061 => x"01", + 7062 => x"00", + 7063 => x"00", + 7064 => x"00", + 7065 => x"01", + 7066 => x"00", + 7067 => x"00", + 7068 => x"00", + 7069 => x"01", + 7070 => x"00", + 7071 => x"00", + 7072 => x"00", + 7073 => x"01", + 7074 => x"00", + 7075 => x"00", + 7076 => x"00", + 7077 => x"01", + 7078 => x"00", + 7079 => x"00", + 7080 => x"00", + 7081 => x"01", + 7082 => x"00", + 7083 => x"00", + 7084 => x"00", + 7085 => x"01", + 7086 => x"00", + 7087 => x"00", + 7088 => x"00", + 7089 => x"01", + 7090 => x"00", + 7091 => x"00", + 7092 => x"00", + 7093 => x"01", + 7094 => x"00", + 7095 => x"00", + 7096 => x"00", + 7097 => x"01", + 7098 => x"00", + 7099 => x"00", + 7100 => x"00", + 7101 => x"01", + 7102 => x"00", + 7103 => x"00", + 7104 => x"00", + 7105 => x"01", + 7106 => x"00", + 7107 => x"00", + 7108 => x"00", + 7109 => x"01", + 7110 => x"00", + 7111 => x"00", + 7112 => x"00", + 7113 => x"01", + 7114 => x"00", + 7115 => x"00", + 7116 => x"00", + 7117 => x"01", + 7118 => x"00", + 7119 => x"00", + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 0 - Port B - bits 7 downto 0 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM0(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(7 downto 0); + memBRead(7 downto 0) <= memBWrite(7 downto 0); + else + memBRead(7 downto 0) <= RAM0(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 1 - Port B - bits 15 downto 8 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM1(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(15 downto 8); + memBRead(15 downto 8) <= memBWrite(15 downto 8); + else + memBRead(15 downto 8) <= RAM1(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 2 - Port B - bits 23 downto 16 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM2(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(23 downto 16); + memBRead(23 downto 16) <= memBWrite(23 downto 16); + else + memBRead(23 downto 16) <= RAM2(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 3 - Port B - bits 31 downto 24 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM3(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(31 downto 24); + memBRead(31 downto 24) <= memBWrite(31 downto 24); + else + memBRead(31 downto 24) <= RAM3(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + +end arch; diff --git a/zpu/devices/sysbus/BRAM/ZPUTA_SinglePortBRAM.vhd b/zpu/devices/sysbus/BRAM/ZPUTA_SinglePortBRAM.vhd new file mode 100644 index 0000000..82eb0c2 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/ZPUTA_SinglePortBRAM.vhd @@ -0,0 +1,26028 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity SinglePortBRAM is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end SinglePortBRAM; + +architecture arch of SinglePortBRAM is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + 0 => x"84", + 1 => x"0b", + 2 => x"04", + 3 => x"ff", + 4 => x"ff", + 5 => x"ff", + 6 => x"ff", + 7 => x"ff", + 8 => x"84", + 9 => x"0b", + 10 => x"04", + 11 => x"84", + 12 => x"0b", + 13 => x"04", + 14 => x"84", + 15 => x"0b", + 16 => x"04", + 17 => x"84", + 18 => x"0b", + 19 => x"04", + 20 => x"84", + 21 => x"0b", + 22 => x"04", + 23 => x"85", + 24 => x"0b", + 25 => x"04", + 26 => x"85", + 27 => x"0b", + 28 => x"04", + 29 => x"85", + 30 => x"0b", + 31 => x"04", + 32 => x"86", + 33 => x"0b", + 34 => x"04", + 35 => x"86", + 36 => x"0b", + 37 => x"04", + 38 => x"86", + 39 => x"0b", + 40 => x"04", + 41 => x"86", + 42 => x"0b", + 43 => x"04", + 44 => x"87", + 45 => x"0b", + 46 => x"04", + 47 => x"87", + 48 => x"0b", + 49 => x"04", + 50 => x"87", + 51 => x"0b", + 52 => x"04", + 53 => x"87", + 54 => x"0b", + 55 => x"04", + 56 => x"88", + 57 => x"0b", + 58 => x"04", + 59 => x"88", + 60 => x"0b", + 61 => x"04", + 62 => x"88", + 63 => x"0b", + 64 => x"04", + 65 => x"88", + 66 => x"0b", + 67 => x"04", + 68 => x"89", + 69 => x"0b", + 70 => x"04", + 71 => x"89", + 72 => x"0b", + 73 => x"04", + 74 => x"89", + 75 => x"0b", + 76 => x"04", + 77 => x"8a", + 78 => x"0b", + 79 => x"04", + 80 => x"8a", + 81 => x"0b", + 82 => x"04", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"00", + 89 => x"00", + 90 => x"00", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"00", + 97 => x"00", + 98 => x"00", + 99 => x"00", + 100 => x"00", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"00", + 105 => x"00", + 106 => x"00", + 107 => x"00", + 108 => x"00", + 109 => x"00", + 110 => x"00", + 111 => x"00", + 112 => x"00", + 113 => x"00", + 114 => x"00", + 115 => x"00", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"00", + 121 => x"00", + 122 => x"00", + 123 => x"00", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"80", + 129 => x"94", + 130 => x"8f", + 131 => x"94", + 132 => x"80", + 133 => x"ca", + 134 => x"9f", + 135 => x"ca", + 136 => x"c0", + 137 => x"91", + 138 => x"90", + 139 => x"91", + 140 => x"88", + 141 => x"04", + 142 => x"0c", + 143 => x"2d", + 144 => x"08", + 145 => x"90", + 146 => x"94", + 147 => x"da", + 148 => x"94", + 149 => x"80", + 150 => x"ca", + 151 => x"a7", + 152 => x"ca", + 153 => x"c0", + 154 => x"91", + 155 => x"90", + 156 => x"91", + 157 => x"88", + 158 => x"04", + 159 => x"0c", + 160 => x"2d", + 161 => x"08", + 162 => x"90", + 163 => x"94", + 164 => x"e7", + 165 => x"94", + 166 => x"80", + 167 => x"ca", + 168 => x"a6", + 169 => x"ca", + 170 => x"c0", + 171 => x"91", + 172 => x"90", + 173 => x"91", + 174 => x"88", + 175 => x"04", + 176 => x"0c", + 177 => x"2d", + 178 => x"08", + 179 => x"90", + 180 => x"94", + 181 => x"9c", + 182 => x"94", + 183 => x"80", + 184 => x"ca", + 185 => x"97", + 186 => x"ca", + 187 => x"c0", + 188 => x"91", + 189 => x"90", + 190 => x"91", + 191 => x"88", + 192 => x"04", + 193 => x"0c", + 194 => x"2d", + 195 => x"08", + 196 => x"90", + 197 => x"94", + 198 => x"f1", + 199 => x"94", + 200 => x"80", + 201 => x"ca", + 202 => x"dc", + 203 => x"ca", + 204 => x"c0", + 205 => x"91", + 206 => x"90", + 207 => x"91", + 208 => x"88", + 209 => x"04", + 210 => x"0c", + 211 => x"2d", + 212 => x"08", + 213 => x"90", + 214 => x"94", + 215 => x"fe", + 216 => x"94", + 217 => x"80", + 218 => x"ca", + 219 => x"ee", + 220 => x"ca", + 221 => x"c0", + 222 => x"91", + 223 => x"90", + 224 => x"91", + 225 => x"88", + 226 => x"04", + 227 => x"0c", + 228 => x"2d", + 229 => x"08", + 230 => x"90", + 231 => x"94", + 232 => x"bb", + 233 => x"94", + 234 => x"80", + 235 => x"ca", + 236 => x"f2", + 237 => x"ca", + 238 => x"c0", + 239 => x"91", + 240 => x"90", + 241 => x"91", + 242 => x"88", + 243 => x"04", + 244 => x"0c", + 245 => x"2d", + 246 => x"08", + 247 => x"90", + 248 => x"94", + 249 => x"c9", + 250 => x"94", + 251 => x"80", + 252 => x"ca", + 253 => x"fd", + 254 => x"ca", + 255 => x"c0", + 256 => x"91", + 257 => x"90", + 258 => x"91", + 259 => x"88", + 260 => x"04", + 261 => x"0c", + 262 => x"2d", + 263 => x"08", + 264 => x"90", + 265 => x"94", + 266 => x"b8", + 267 => x"94", + 268 => x"80", + 269 => x"ca", + 270 => x"e9", + 271 => x"ca", + 272 => x"c0", + 273 => x"91", + 274 => x"90", + 275 => x"91", + 276 => x"88", + 277 => x"04", + 278 => x"0c", + 279 => x"2d", + 280 => x"08", + 281 => x"90", + 282 => x"94", + 283 => x"d4", + 284 => x"94", + 285 => x"80", + 286 => x"ca", + 287 => x"82", + 288 => x"ca", + 289 => x"c0", + 290 => x"91", + 291 => x"91", + 292 => x"91", + 293 => x"88", + 294 => x"04", + 295 => x"0c", + 296 => x"2d", + 297 => x"08", + 298 => x"90", + 299 => x"94", + 300 => x"bb", + 301 => x"94", + 302 => x"80", + 303 => x"ca", + 304 => x"8a", + 305 => x"ca", + 306 => x"c0", + 307 => x"91", + 308 => x"90", + 309 => x"91", + 310 => x"88", + 311 => x"04", + 312 => x"0c", + 313 => x"2d", + 314 => x"08", + 315 => x"90", + 316 => x"94", + 317 => x"c4", + 318 => x"94", + 319 => x"80", + 320 => x"ca", + 321 => x"90", + 322 => x"ca", + 323 => x"c0", + 324 => x"91", + 325 => x"90", + 326 => x"91", + 327 => x"88", + 328 => x"04", + 329 => x"0c", + 330 => x"2d", + 331 => x"08", + 332 => x"90", + 333 => x"94", + 334 => x"82", + 335 => x"94", + 336 => x"80", + 337 => x"ca", + 338 => x"e1", + 339 => x"38", + 340 => x"84", + 341 => x"0b", + 342 => x"c9", + 343 => x"80", + 344 => x"c5", + 345 => x"91", + 346 => x"02", + 347 => x"0c", + 348 => x"80", + 349 => x"94", + 350 => x"08", + 351 => x"94", + 352 => x"08", + 353 => x"3f", + 354 => x"08", + 355 => x"88", + 356 => x"3d", + 357 => x"94", + 358 => x"ca", + 359 => x"91", + 360 => x"fd", + 361 => x"53", + 362 => x"08", + 363 => x"52", + 364 => x"08", + 365 => x"51", + 366 => x"ca", + 367 => x"91", + 368 => x"54", + 369 => x"91", + 370 => x"04", + 371 => x"08", + 372 => x"94", + 373 => x"0d", + 374 => x"ca", + 375 => x"05", + 376 => x"91", + 377 => x"f8", + 378 => x"ca", + 379 => x"05", + 380 => x"94", + 381 => x"08", + 382 => x"91", + 383 => x"fc", + 384 => x"2e", + 385 => x"0b", + 386 => x"08", + 387 => x"24", + 388 => x"ca", + 389 => x"05", + 390 => x"ca", + 391 => x"05", + 392 => x"94", + 393 => x"08", + 394 => x"94", + 395 => x"0c", + 396 => x"91", + 397 => x"fc", + 398 => x"2e", + 399 => x"91", + 400 => x"8c", + 401 => x"ca", + 402 => x"05", + 403 => x"38", + 404 => x"08", + 405 => x"91", + 406 => x"8c", + 407 => x"91", + 408 => x"88", + 409 => x"ca", + 410 => x"05", + 411 => x"94", + 412 => x"08", + 413 => x"94", + 414 => x"0c", + 415 => x"08", + 416 => x"81", + 417 => x"94", + 418 => x"0c", + 419 => x"08", + 420 => x"81", + 421 => x"94", + 422 => x"0c", + 423 => x"91", + 424 => x"90", + 425 => x"2e", + 426 => x"ca", + 427 => x"05", + 428 => x"ca", + 429 => x"05", + 430 => x"39", + 431 => x"08", + 432 => x"70", + 433 => x"08", + 434 => x"51", + 435 => x"08", + 436 => x"91", + 437 => x"85", + 438 => x"ca", + 439 => x"fc", + 440 => x"79", + 441 => x"05", + 442 => x"57", + 443 => x"83", + 444 => x"38", + 445 => x"51", + 446 => x"a4", + 447 => x"52", + 448 => x"93", + 449 => x"70", + 450 => x"34", + 451 => x"71", + 452 => x"81", + 453 => x"74", + 454 => x"0c", + 455 => x"04", + 456 => x"2b", + 457 => x"71", + 458 => x"51", + 459 => x"72", + 460 => x"72", + 461 => x"05", + 462 => x"71", + 463 => x"53", + 464 => x"70", + 465 => x"0c", + 466 => x"84", + 467 => x"f0", + 468 => x"8f", + 469 => x"83", + 470 => x"38", + 471 => x"84", + 472 => x"fc", + 473 => x"83", + 474 => x"70", + 475 => x"39", + 476 => x"77", + 477 => x"07", + 478 => x"54", + 479 => x"38", + 480 => x"08", + 481 => x"71", + 482 => x"80", + 483 => x"75", + 484 => x"33", + 485 => x"06", + 486 => x"80", + 487 => x"72", + 488 => x"75", + 489 => x"06", + 490 => x"12", + 491 => x"33", + 492 => x"06", + 493 => x"52", + 494 => x"72", + 495 => x"81", + 496 => x"81", + 497 => x"71", + 498 => x"88", + 499 => x"87", + 500 => x"71", + 501 => x"fb", + 502 => x"06", + 503 => x"82", + 504 => x"51", + 505 => x"97", + 506 => x"84", + 507 => x"54", + 508 => x"75", + 509 => x"38", + 510 => x"52", + 511 => x"80", + 512 => x"88", + 513 => x"0d", + 514 => x"0d", + 515 => x"53", + 516 => x"52", + 517 => x"91", + 518 => x"81", + 519 => x"07", + 520 => x"52", + 521 => x"e8", + 522 => x"ca", + 523 => x"3d", + 524 => x"3d", + 525 => x"08", + 526 => x"56", + 527 => x"80", + 528 => x"33", + 529 => x"2e", + 530 => x"86", + 531 => x"52", + 532 => x"53", + 533 => x"13", + 534 => x"33", + 535 => x"06", + 536 => x"70", + 537 => x"38", + 538 => x"80", + 539 => x"74", + 540 => x"81", + 541 => x"70", + 542 => x"81", + 543 => x"80", + 544 => x"05", + 545 => x"76", + 546 => x"70", + 547 => x"0c", + 548 => x"04", + 549 => x"76", + 550 => x"80", + 551 => x"86", + 552 => x"52", + 553 => x"bf", + 554 => x"88", + 555 => x"80", + 556 => x"74", + 557 => x"ca", + 558 => x"3d", + 559 => x"3d", + 560 => x"11", + 561 => x"52", + 562 => x"70", + 563 => x"98", + 564 => x"33", + 565 => x"82", + 566 => x"26", + 567 => x"84", + 568 => x"83", + 569 => x"26", + 570 => x"85", + 571 => x"84", + 572 => x"26", + 573 => x"86", + 574 => x"85", + 575 => x"26", + 576 => x"88", + 577 => x"86", + 578 => x"e7", + 579 => x"38", + 580 => x"54", + 581 => x"87", + 582 => x"cc", + 583 => x"87", + 584 => x"0c", + 585 => x"c0", + 586 => x"82", + 587 => x"c0", + 588 => x"83", + 589 => x"c0", + 590 => x"84", + 591 => x"c0", + 592 => x"85", + 593 => x"c0", + 594 => x"86", + 595 => x"c0", + 596 => x"74", + 597 => x"a4", + 598 => x"c0", + 599 => x"80", + 600 => x"98", + 601 => x"52", + 602 => x"88", + 603 => x"0d", + 604 => x"0d", + 605 => x"c0", + 606 => x"81", + 607 => x"c0", + 608 => x"5e", + 609 => x"87", + 610 => x"08", + 611 => x"1c", + 612 => x"98", + 613 => x"79", + 614 => x"87", + 615 => x"08", + 616 => x"1c", + 617 => x"98", + 618 => x"79", + 619 => x"87", + 620 => x"08", + 621 => x"1c", + 622 => x"98", + 623 => x"7b", + 624 => x"87", + 625 => x"08", + 626 => x"1c", + 627 => x"0c", + 628 => x"ff", + 629 => x"83", + 630 => x"58", + 631 => x"57", + 632 => x"56", + 633 => x"55", + 634 => x"54", + 635 => x"53", + 636 => x"ff", + 637 => x"b3", + 638 => x"84", + 639 => x"0d", + 640 => x"0d", + 641 => x"33", + 642 => x"9f", + 643 => x"52", + 644 => x"91", + 645 => x"83", + 646 => x"fb", + 647 => x"0b", + 648 => x"e0", + 649 => x"ff", + 650 => x"56", + 651 => x"84", + 652 => x"2e", + 653 => x"c0", + 654 => x"70", + 655 => x"2a", + 656 => x"53", + 657 => x"80", + 658 => x"71", + 659 => x"81", + 660 => x"70", + 661 => x"81", + 662 => x"06", + 663 => x"80", + 664 => x"71", + 665 => x"81", + 666 => x"70", + 667 => x"73", + 668 => x"51", + 669 => x"80", + 670 => x"2e", + 671 => x"c0", + 672 => x"75", + 673 => x"91", + 674 => x"87", + 675 => x"fb", + 676 => x"9f", + 677 => x"0b", + 678 => x"33", + 679 => x"06", + 680 => x"87", + 681 => x"51", + 682 => x"86", + 683 => x"94", + 684 => x"08", + 685 => x"70", + 686 => x"54", + 687 => x"2e", + 688 => x"91", + 689 => x"06", + 690 => x"d7", + 691 => x"32", + 692 => x"51", + 693 => x"2e", + 694 => x"93", + 695 => x"06", + 696 => x"ff", + 697 => x"81", + 698 => x"87", + 699 => x"52", + 700 => x"86", + 701 => x"94", + 702 => x"72", + 703 => x"0d", + 704 => x"0d", + 705 => x"74", + 706 => x"ff", + 707 => x"57", + 708 => x"80", + 709 => x"81", + 710 => x"15", + 711 => x"c6", + 712 => x"81", + 713 => x"57", + 714 => x"c0", + 715 => x"75", + 716 => x"38", + 717 => x"94", + 718 => x"70", + 719 => x"81", + 720 => x"52", + 721 => x"8c", + 722 => x"2a", + 723 => x"51", + 724 => x"38", + 725 => x"70", + 726 => x"51", + 727 => x"8d", + 728 => x"2a", + 729 => x"51", + 730 => x"be", + 731 => x"ff", + 732 => x"c0", + 733 => x"70", + 734 => x"38", + 735 => x"90", + 736 => x"0c", + 737 => x"33", + 738 => x"06", + 739 => x"70", + 740 => x"76", + 741 => x"0c", + 742 => x"04", + 743 => x"0b", + 744 => x"e0", + 745 => x"ff", + 746 => x"87", + 747 => x"51", + 748 => x"86", + 749 => x"94", + 750 => x"08", + 751 => x"70", + 752 => x"51", + 753 => x"2e", + 754 => x"81", + 755 => x"87", + 756 => x"52", + 757 => x"86", + 758 => x"94", + 759 => x"08", + 760 => x"06", + 761 => x"0c", + 762 => x"0d", + 763 => x"0d", + 764 => x"c6", + 765 => x"81", + 766 => x"53", + 767 => x"84", + 768 => x"2e", + 769 => x"c0", + 770 => x"71", + 771 => x"2a", + 772 => x"51", + 773 => x"52", + 774 => x"a0", + 775 => x"ff", + 776 => x"c0", + 777 => x"70", + 778 => x"38", + 779 => x"90", + 780 => x"70", + 781 => x"98", + 782 => x"51", + 783 => x"88", + 784 => x"0d", + 785 => x"0d", + 786 => x"80", + 787 => x"2a", + 788 => x"51", + 789 => x"83", + 790 => x"c0", + 791 => x"91", + 792 => x"87", + 793 => x"08", + 794 => x"0c", + 795 => x"8c", + 796 => x"ec", + 797 => x"9e", + 798 => x"c6", + 799 => x"c0", + 800 => x"91", + 801 => x"87", + 802 => x"08", + 803 => x"0c", + 804 => x"a4", + 805 => x"fc", + 806 => x"9e", + 807 => x"c7", + 808 => x"c0", + 809 => x"91", + 810 => x"87", + 811 => x"08", + 812 => x"c7", + 813 => x"c0", + 814 => x"91", + 815 => x"81", + 816 => x"90", + 817 => x"87", + 818 => x"08", + 819 => x"06", + 820 => x"70", + 821 => x"38", + 822 => x"91", + 823 => x"80", + 824 => x"9e", + 825 => x"81", + 826 => x"51", + 827 => x"80", + 828 => x"81", + 829 => x"c7", + 830 => x"0b", + 831 => x"88", + 832 => x"c0", + 833 => x"52", + 834 => x"2e", + 835 => x"52", + 836 => x"93", + 837 => x"87", + 838 => x"08", + 839 => x"06", + 840 => x"70", + 841 => x"38", + 842 => x"91", + 843 => x"80", + 844 => x"9e", + 845 => x"88", + 846 => x"52", + 847 => x"2e", + 848 => x"52", + 849 => x"95", + 850 => x"87", + 851 => x"08", + 852 => x"06", + 853 => x"70", + 854 => x"38", + 855 => x"91", + 856 => x"80", + 857 => x"9e", + 858 => x"82", + 859 => x"52", + 860 => x"2e", + 861 => x"52", + 862 => x"97", + 863 => x"87", + 864 => x"08", + 865 => x"06", + 866 => x"70", + 867 => x"38", + 868 => x"91", + 869 => x"87", + 870 => x"08", + 871 => x"06", + 872 => x"51", + 873 => x"91", + 874 => x"80", + 875 => x"9e", + 876 => x"90", + 877 => x"52", + 878 => x"83", + 879 => x"71", + 880 => x"34", + 881 => x"c0", + 882 => x"70", + 883 => x"52", + 884 => x"2e", + 885 => x"52", + 886 => x"9b", + 887 => x"9e", + 888 => x"87", + 889 => x"70", + 890 => x"34", + 891 => x"04", + 892 => x"91", + 893 => x"84", + 894 => x"c7", + 895 => x"73", + 896 => x"38", + 897 => x"51", + 898 => x"91", + 899 => x"84", + 900 => x"c7", + 901 => x"73", + 902 => x"38", + 903 => x"08", + 904 => x"e4", + 905 => x"b4", + 906 => x"d4", + 907 => x"92", + 908 => x"80", + 909 => x"91", + 910 => x"53", + 911 => x"08", + 912 => x"ec", + 913 => x"3f", + 914 => x"33", + 915 => x"38", + 916 => x"33", + 917 => x"2e", + 918 => x"c6", + 919 => x"91", + 920 => x"52", + 921 => x"51", + 922 => x"91", + 923 => x"54", + 924 => x"88", + 925 => x"b4", + 926 => x"3f", + 927 => x"33", + 928 => x"2e", + 929 => x"b5", + 930 => x"90", + 931 => x"97", + 932 => x"80", + 933 => x"91", + 934 => x"82", + 935 => x"c7", + 936 => x"73", + 937 => x"38", + 938 => x"33", + 939 => x"d8", + 940 => x"3f", + 941 => x"33", + 942 => x"2e", + 943 => x"b5", + 944 => x"d8", + 945 => x"9b", + 946 => x"80", + 947 => x"91", + 948 => x"52", + 949 => x"51", + 950 => x"91", + 951 => x"82", + 952 => x"c6", + 953 => x"91", + 954 => x"88", + 955 => x"c7", + 956 => x"91", + 957 => x"88", + 958 => x"c7", + 959 => x"91", + 960 => x"87", + 961 => x"c7", + 962 => x"91", + 963 => x"87", + 964 => x"c7", + 965 => x"91", + 966 => x"87", + 967 => x"3d", + 968 => x"3d", + 969 => x"05", + 970 => x"52", + 971 => x"ac", + 972 => x"29", + 973 => x"b3", + 974 => x"71", + 975 => x"b8", + 976 => x"39", + 977 => x"51", + 978 => x"b8", + 979 => x"39", + 980 => x"51", + 981 => x"b8", + 982 => x"39", + 983 => x"51", + 984 => x"84", + 985 => x"71", + 986 => x"04", + 987 => x"c0", + 988 => x"04", + 989 => x"87", + 990 => x"70", + 991 => x"80", + 992 => x"74", + 993 => x"c7", + 994 => x"0c", + 995 => x"04", + 996 => x"87", + 997 => x"70", + 998 => x"a0", + 999 => x"72", + 1000 => x"70", + 1001 => x"08", + 1002 => x"c7", + 1003 => x"0c", + 1004 => x"0d", + 1005 => x"a0", + 1006 => x"96", + 1007 => x"fe", + 1008 => x"93", + 1009 => x"72", + 1010 => x"81", + 1011 => x"8d", + 1012 => x"91", + 1013 => x"52", + 1014 => x"90", + 1015 => x"34", + 1016 => x"08", + 1017 => x"ca", + 1018 => x"39", + 1019 => x"08", + 1020 => x"2e", + 1021 => x"51", + 1022 => x"3d", + 1023 => x"3d", + 1024 => x"05", + 1025 => x"98", + 1026 => x"ca", + 1027 => x"51", + 1028 => x"72", + 1029 => x"0c", + 1030 => x"04", + 1031 => x"75", + 1032 => x"70", + 1033 => x"53", + 1034 => x"2e", + 1035 => x"81", + 1036 => x"81", + 1037 => x"87", + 1038 => x"85", + 1039 => x"fc", + 1040 => x"91", + 1041 => x"78", + 1042 => x"0c", + 1043 => x"33", + 1044 => x"06", + 1045 => x"80", + 1046 => x"72", + 1047 => x"51", + 1048 => x"fe", + 1049 => x"39", + 1050 => x"98", + 1051 => x"0d", + 1052 => x"0d", + 1053 => x"59", + 1054 => x"05", + 1055 => x"75", + 1056 => x"f8", + 1057 => x"2e", + 1058 => x"82", + 1059 => x"70", + 1060 => x"05", + 1061 => x"5b", + 1062 => x"2e", + 1063 => x"85", + 1064 => x"8b", + 1065 => x"2e", + 1066 => x"8a", + 1067 => x"78", + 1068 => x"5a", + 1069 => x"aa", + 1070 => x"06", + 1071 => x"84", + 1072 => x"7b", + 1073 => x"5d", + 1074 => x"59", + 1075 => x"d0", + 1076 => x"89", + 1077 => x"7a", + 1078 => x"10", + 1079 => x"d0", + 1080 => x"81", + 1081 => x"57", + 1082 => x"75", + 1083 => x"70", + 1084 => x"07", + 1085 => x"80", + 1086 => x"30", + 1087 => x"80", + 1088 => x"53", + 1089 => x"55", + 1090 => x"2e", + 1091 => x"84", + 1092 => x"81", + 1093 => x"57", + 1094 => x"2e", + 1095 => x"75", + 1096 => x"76", + 1097 => x"e0", + 1098 => x"ff", + 1099 => x"73", + 1100 => x"81", + 1101 => x"80", + 1102 => x"38", + 1103 => x"2e", + 1104 => x"73", + 1105 => x"8b", + 1106 => x"c2", + 1107 => x"38", + 1108 => x"73", + 1109 => x"81", + 1110 => x"8f", + 1111 => x"d5", + 1112 => x"38", + 1113 => x"24", + 1114 => x"80", + 1115 => x"38", + 1116 => x"73", + 1117 => x"80", + 1118 => x"ef", + 1119 => x"19", + 1120 => x"59", + 1121 => x"33", + 1122 => x"75", + 1123 => x"81", + 1124 => x"70", + 1125 => x"55", + 1126 => x"79", + 1127 => x"90", + 1128 => x"16", + 1129 => x"7b", + 1130 => x"a0", + 1131 => x"3f", + 1132 => x"53", + 1133 => x"e9", + 1134 => x"fc", + 1135 => x"81", + 1136 => x"72", + 1137 => x"b0", + 1138 => x"fb", + 1139 => x"39", + 1140 => x"83", + 1141 => x"59", + 1142 => x"82", + 1143 => x"88", + 1144 => x"8a", + 1145 => x"90", + 1146 => x"75", + 1147 => x"3f", + 1148 => x"79", + 1149 => x"81", + 1150 => x"72", + 1151 => x"38", + 1152 => x"59", + 1153 => x"84", + 1154 => x"58", + 1155 => x"80", + 1156 => x"30", + 1157 => x"80", + 1158 => x"55", + 1159 => x"25", + 1160 => x"80", + 1161 => x"74", + 1162 => x"07", + 1163 => x"0b", + 1164 => x"57", + 1165 => x"51", + 1166 => x"91", + 1167 => x"81", + 1168 => x"53", + 1169 => x"e6", + 1170 => x"ca", + 1171 => x"89", + 1172 => x"38", + 1173 => x"75", + 1174 => x"84", + 1175 => x"53", + 1176 => x"06", + 1177 => x"53", + 1178 => x"81", + 1179 => x"81", + 1180 => x"70", + 1181 => x"2a", + 1182 => x"76", + 1183 => x"38", + 1184 => x"38", + 1185 => x"70", + 1186 => x"53", + 1187 => x"8e", + 1188 => x"77", + 1189 => x"53", + 1190 => x"81", + 1191 => x"7a", + 1192 => x"55", + 1193 => x"83", + 1194 => x"79", + 1195 => x"81", + 1196 => x"72", + 1197 => x"17", + 1198 => x"27", + 1199 => x"51", + 1200 => x"75", + 1201 => x"72", + 1202 => x"81", + 1203 => x"7a", + 1204 => x"38", + 1205 => x"05", + 1206 => x"ff", + 1207 => x"70", + 1208 => x"57", + 1209 => x"76", + 1210 => x"81", + 1211 => x"72", + 1212 => x"84", + 1213 => x"f9", + 1214 => x"39", + 1215 => x"04", + 1216 => x"86", + 1217 => x"84", + 1218 => x"55", + 1219 => x"fa", + 1220 => x"3d", + 1221 => x"3d", + 1222 => x"ca", + 1223 => x"3d", + 1224 => x"75", + 1225 => x"3f", + 1226 => x"08", + 1227 => x"34", + 1228 => x"ca", + 1229 => x"3d", + 1230 => x"3d", + 1231 => x"98", + 1232 => x"ca", + 1233 => x"3d", + 1234 => x"77", + 1235 => x"a1", + 1236 => x"ca", + 1237 => x"3d", + 1238 => x"3d", + 1239 => x"91", + 1240 => x"70", + 1241 => x"55", + 1242 => x"80", + 1243 => x"38", + 1244 => x"08", + 1245 => x"91", + 1246 => x"81", + 1247 => x"72", + 1248 => x"cb", + 1249 => x"2e", + 1250 => x"88", + 1251 => x"70", + 1252 => x"51", + 1253 => x"2e", + 1254 => x"80", + 1255 => x"ff", + 1256 => x"39", + 1257 => x"c8", + 1258 => x"52", + 1259 => x"c0", + 1260 => x"52", + 1261 => x"81", + 1262 => x"51", + 1263 => x"ff", + 1264 => x"15", + 1265 => x"34", + 1266 => x"f3", + 1267 => x"72", + 1268 => x"0c", + 1269 => x"04", + 1270 => x"91", + 1271 => x"75", + 1272 => x"0c", + 1273 => x"52", + 1274 => x"3f", + 1275 => x"9c", + 1276 => x"0d", + 1277 => x"0d", + 1278 => x"56", + 1279 => x"0c", + 1280 => x"70", + 1281 => x"73", + 1282 => x"81", + 1283 => x"81", + 1284 => x"ed", + 1285 => x"2e", + 1286 => x"8e", + 1287 => x"08", + 1288 => x"76", + 1289 => x"56", + 1290 => x"b0", + 1291 => x"06", + 1292 => x"75", + 1293 => x"76", + 1294 => x"70", + 1295 => x"73", + 1296 => x"8b", + 1297 => x"73", + 1298 => x"85", + 1299 => x"82", + 1300 => x"76", + 1301 => x"70", + 1302 => x"ac", + 1303 => x"a0", + 1304 => x"fa", + 1305 => x"53", + 1306 => x"57", + 1307 => x"98", + 1308 => x"39", + 1309 => x"80", + 1310 => x"26", + 1311 => x"86", + 1312 => x"80", + 1313 => x"57", + 1314 => x"74", + 1315 => x"38", + 1316 => x"27", + 1317 => x"14", + 1318 => x"06", + 1319 => x"14", + 1320 => x"06", + 1321 => x"74", + 1322 => x"f9", + 1323 => x"ff", + 1324 => x"89", + 1325 => x"38", + 1326 => x"c5", + 1327 => x"29", + 1328 => x"81", + 1329 => x"76", + 1330 => x"56", + 1331 => x"ba", + 1332 => x"2e", + 1333 => x"30", + 1334 => x"0c", + 1335 => x"91", + 1336 => x"8a", + 1337 => x"f8", + 1338 => x"7c", + 1339 => x"70", + 1340 => x"75", + 1341 => x"55", + 1342 => x"2e", + 1343 => x"87", + 1344 => x"76", + 1345 => x"73", + 1346 => x"81", + 1347 => x"81", + 1348 => x"77", + 1349 => x"70", + 1350 => x"58", + 1351 => x"09", + 1352 => x"c2", + 1353 => x"81", + 1354 => x"75", + 1355 => x"55", + 1356 => x"e2", + 1357 => x"90", + 1358 => x"f8", + 1359 => x"8f", + 1360 => x"81", + 1361 => x"75", + 1362 => x"55", + 1363 => x"81", + 1364 => x"27", + 1365 => x"d0", + 1366 => x"55", + 1367 => x"73", + 1368 => x"80", + 1369 => x"14", + 1370 => x"72", + 1371 => x"e0", + 1372 => x"80", + 1373 => x"39", + 1374 => x"55", + 1375 => x"80", + 1376 => x"e0", + 1377 => x"38", + 1378 => x"81", + 1379 => x"53", + 1380 => x"81", + 1381 => x"53", + 1382 => x"8e", + 1383 => x"70", + 1384 => x"55", + 1385 => x"27", + 1386 => x"77", + 1387 => x"74", + 1388 => x"76", + 1389 => x"77", + 1390 => x"70", + 1391 => x"55", + 1392 => x"77", + 1393 => x"38", + 1394 => x"74", + 1395 => x"55", + 1396 => x"88", + 1397 => x"0d", + 1398 => x"0d", + 1399 => x"33", + 1400 => x"70", + 1401 => x"38", + 1402 => x"11", + 1403 => x"91", + 1404 => x"83", + 1405 => x"fc", + 1406 => x"9b", + 1407 => x"84", + 1408 => x"33", + 1409 => x"51", + 1410 => x"80", + 1411 => x"84", + 1412 => x"92", + 1413 => x"51", + 1414 => x"80", + 1415 => x"81", + 1416 => x"72", + 1417 => x"92", + 1418 => x"81", + 1419 => x"0b", + 1420 => x"8c", + 1421 => x"71", + 1422 => x"06", + 1423 => x"80", + 1424 => x"87", + 1425 => x"08", + 1426 => x"38", + 1427 => x"80", + 1428 => x"71", + 1429 => x"c0", + 1430 => x"51", + 1431 => x"87", + 1432 => x"c7", + 1433 => x"91", + 1434 => x"33", + 1435 => x"ca", + 1436 => x"3d", + 1437 => x"3d", + 1438 => x"64", + 1439 => x"bf", + 1440 => x"40", + 1441 => x"74", + 1442 => x"cd", + 1443 => x"88", + 1444 => x"7a", + 1445 => x"81", + 1446 => x"72", + 1447 => x"87", + 1448 => x"11", + 1449 => x"8c", + 1450 => x"92", + 1451 => x"5a", + 1452 => x"58", + 1453 => x"c0", + 1454 => x"76", + 1455 => x"76", + 1456 => x"70", + 1457 => x"81", + 1458 => x"54", + 1459 => x"8e", + 1460 => x"52", + 1461 => x"81", + 1462 => x"81", + 1463 => x"74", + 1464 => x"53", + 1465 => x"83", + 1466 => x"78", + 1467 => x"8f", + 1468 => x"2e", + 1469 => x"c0", + 1470 => x"52", + 1471 => x"87", + 1472 => x"08", + 1473 => x"2e", + 1474 => x"84", + 1475 => x"38", + 1476 => x"87", + 1477 => x"15", + 1478 => x"70", + 1479 => x"52", + 1480 => x"ff", + 1481 => x"39", + 1482 => x"81", + 1483 => x"ff", + 1484 => x"57", + 1485 => x"90", + 1486 => x"80", + 1487 => x"71", + 1488 => x"78", + 1489 => x"38", + 1490 => x"80", + 1491 => x"80", + 1492 => x"81", + 1493 => x"72", + 1494 => x"0c", + 1495 => x"04", + 1496 => x"60", + 1497 => x"8c", + 1498 => x"33", + 1499 => x"5b", + 1500 => x"74", + 1501 => x"e1", + 1502 => x"88", + 1503 => x"79", + 1504 => x"78", + 1505 => x"06", + 1506 => x"77", + 1507 => x"87", + 1508 => x"11", + 1509 => x"8c", + 1510 => x"92", + 1511 => x"59", + 1512 => x"85", + 1513 => x"98", + 1514 => x"7d", + 1515 => x"0c", + 1516 => x"08", + 1517 => x"70", + 1518 => x"53", + 1519 => x"2e", + 1520 => x"70", + 1521 => x"33", + 1522 => x"18", + 1523 => x"2a", + 1524 => x"51", + 1525 => x"2e", + 1526 => x"c0", + 1527 => x"52", + 1528 => x"87", + 1529 => x"08", + 1530 => x"2e", + 1531 => x"84", + 1532 => x"38", + 1533 => x"87", + 1534 => x"15", + 1535 => x"70", + 1536 => x"52", + 1537 => x"ff", + 1538 => x"39", + 1539 => x"81", + 1540 => x"80", + 1541 => x"52", + 1542 => x"90", + 1543 => x"80", + 1544 => x"71", + 1545 => x"7a", + 1546 => x"38", + 1547 => x"80", + 1548 => x"80", + 1549 => x"81", + 1550 => x"72", + 1551 => x"0c", + 1552 => x"04", + 1553 => x"7e", + 1554 => x"b3", + 1555 => x"88", + 1556 => x"33", + 1557 => x"56", + 1558 => x"3f", + 1559 => x"08", + 1560 => x"83", + 1561 => x"fe", + 1562 => x"87", + 1563 => x"0c", + 1564 => x"76", + 1565 => x"38", + 1566 => x"93", + 1567 => x"2b", + 1568 => x"8c", + 1569 => x"71", + 1570 => x"38", + 1571 => x"71", + 1572 => x"c6", + 1573 => x"39", + 1574 => x"81", + 1575 => x"06", + 1576 => x"71", + 1577 => x"38", + 1578 => x"8c", + 1579 => x"e8", + 1580 => x"98", + 1581 => x"71", + 1582 => x"73", + 1583 => x"92", + 1584 => x"72", + 1585 => x"06", + 1586 => x"f7", + 1587 => x"80", + 1588 => x"88", + 1589 => x"0c", + 1590 => x"80", + 1591 => x"56", + 1592 => x"56", + 1593 => x"91", + 1594 => x"8c", + 1595 => x"fe", + 1596 => x"81", + 1597 => x"33", + 1598 => x"07", + 1599 => x"0c", + 1600 => x"3d", + 1601 => x"3d", + 1602 => x"11", + 1603 => x"33", + 1604 => x"71", + 1605 => x"81", + 1606 => x"72", + 1607 => x"75", + 1608 => x"91", + 1609 => x"52", + 1610 => x"54", + 1611 => x"0d", + 1612 => x"0d", + 1613 => x"05", + 1614 => x"52", + 1615 => x"70", + 1616 => x"34", + 1617 => x"51", + 1618 => x"83", + 1619 => x"ff", + 1620 => x"75", + 1621 => x"72", + 1622 => x"54", + 1623 => x"2a", + 1624 => x"70", + 1625 => x"34", + 1626 => x"51", + 1627 => x"81", + 1628 => x"70", + 1629 => x"70", + 1630 => x"3d", + 1631 => x"3d", + 1632 => x"77", + 1633 => x"70", + 1634 => x"38", + 1635 => x"05", + 1636 => x"70", + 1637 => x"34", + 1638 => x"eb", + 1639 => x"0d", + 1640 => x"0d", + 1641 => x"54", + 1642 => x"72", + 1643 => x"54", + 1644 => x"51", + 1645 => x"84", + 1646 => x"fc", + 1647 => x"77", + 1648 => x"53", + 1649 => x"05", + 1650 => x"70", + 1651 => x"33", + 1652 => x"ff", + 1653 => x"52", + 1654 => x"2e", + 1655 => x"80", + 1656 => x"71", + 1657 => x"0c", + 1658 => x"04", + 1659 => x"74", + 1660 => x"89", + 1661 => x"2e", + 1662 => x"11", + 1663 => x"52", + 1664 => x"70", + 1665 => x"88", + 1666 => x"0d", + 1667 => x"91", + 1668 => x"04", + 1669 => x"ca", + 1670 => x"f7", + 1671 => x"56", + 1672 => x"17", + 1673 => x"74", + 1674 => x"d6", + 1675 => x"b0", + 1676 => x"b4", + 1677 => x"81", + 1678 => x"59", + 1679 => x"91", + 1680 => x"7a", + 1681 => x"06", + 1682 => x"ca", + 1683 => x"17", + 1684 => x"08", + 1685 => x"08", + 1686 => x"08", + 1687 => x"74", + 1688 => x"38", + 1689 => x"55", + 1690 => x"09", + 1691 => x"38", + 1692 => x"18", + 1693 => x"81", + 1694 => x"f9", + 1695 => x"39", + 1696 => x"91", + 1697 => x"8b", + 1698 => x"fa", + 1699 => x"7a", + 1700 => x"57", + 1701 => x"08", + 1702 => x"75", + 1703 => x"3f", + 1704 => x"08", + 1705 => x"88", + 1706 => x"81", + 1707 => x"b4", + 1708 => x"16", + 1709 => x"be", + 1710 => x"88", + 1711 => x"85", + 1712 => x"81", + 1713 => x"17", + 1714 => x"ca", + 1715 => x"3d", + 1716 => x"3d", + 1717 => x"52", + 1718 => x"3f", + 1719 => x"08", + 1720 => x"88", + 1721 => x"38", + 1722 => x"74", + 1723 => x"81", + 1724 => x"38", + 1725 => x"59", + 1726 => x"09", + 1727 => x"e3", + 1728 => x"53", + 1729 => x"08", + 1730 => x"70", + 1731 => x"91", + 1732 => x"d5", + 1733 => x"17", + 1734 => x"3f", + 1735 => x"a4", + 1736 => x"51", + 1737 => x"86", + 1738 => x"f2", + 1739 => x"17", + 1740 => x"3f", + 1741 => x"52", + 1742 => x"51", + 1743 => x"8c", + 1744 => x"84", + 1745 => x"fc", + 1746 => x"17", + 1747 => x"70", + 1748 => x"79", + 1749 => x"52", + 1750 => x"51", + 1751 => x"77", + 1752 => x"80", + 1753 => x"81", + 1754 => x"f9", + 1755 => x"ca", + 1756 => x"2e", + 1757 => x"58", + 1758 => x"88", + 1759 => x"0d", + 1760 => x"0d", + 1761 => x"98", + 1762 => x"05", + 1763 => x"80", + 1764 => x"27", + 1765 => x"14", + 1766 => x"29", + 1767 => x"05", + 1768 => x"91", + 1769 => x"87", + 1770 => x"f9", + 1771 => x"7a", + 1772 => x"54", + 1773 => x"27", + 1774 => x"76", + 1775 => x"27", + 1776 => x"ff", + 1777 => x"58", + 1778 => x"80", + 1779 => x"82", + 1780 => x"72", + 1781 => x"38", + 1782 => x"72", + 1783 => x"8e", + 1784 => x"39", + 1785 => x"17", + 1786 => x"a4", + 1787 => x"53", + 1788 => x"fd", + 1789 => x"ca", + 1790 => x"9f", + 1791 => x"ff", + 1792 => x"11", + 1793 => x"70", + 1794 => x"18", + 1795 => x"76", + 1796 => x"53", + 1797 => x"91", + 1798 => x"80", + 1799 => x"83", + 1800 => x"b4", + 1801 => x"88", + 1802 => x"79", + 1803 => x"84", + 1804 => x"58", + 1805 => x"80", + 1806 => x"9f", + 1807 => x"80", + 1808 => x"88", + 1809 => x"08", + 1810 => x"51", + 1811 => x"91", + 1812 => x"80", + 1813 => x"10", + 1814 => x"74", + 1815 => x"51", + 1816 => x"91", + 1817 => x"83", + 1818 => x"58", + 1819 => x"87", + 1820 => x"08", + 1821 => x"51", + 1822 => x"91", + 1823 => x"9b", + 1824 => x"2b", + 1825 => x"74", + 1826 => x"51", + 1827 => x"91", + 1828 => x"f0", + 1829 => x"83", + 1830 => x"77", + 1831 => x"0c", + 1832 => x"04", + 1833 => x"7a", + 1834 => x"58", + 1835 => x"81", + 1836 => x"9e", + 1837 => x"17", + 1838 => x"96", + 1839 => x"53", + 1840 => x"81", + 1841 => x"79", + 1842 => x"72", + 1843 => x"38", + 1844 => x"72", + 1845 => x"b8", + 1846 => x"39", + 1847 => x"17", + 1848 => x"a4", + 1849 => x"53", + 1850 => x"fb", + 1851 => x"ca", + 1852 => x"91", + 1853 => x"81", + 1854 => x"83", + 1855 => x"b4", + 1856 => x"78", + 1857 => x"56", + 1858 => x"76", + 1859 => x"38", + 1860 => x"9f", + 1861 => x"33", + 1862 => x"07", + 1863 => x"74", + 1864 => x"83", + 1865 => x"89", + 1866 => x"08", + 1867 => x"51", + 1868 => x"91", + 1869 => x"59", + 1870 => x"08", + 1871 => x"74", + 1872 => x"16", + 1873 => x"84", + 1874 => x"76", + 1875 => x"88", + 1876 => x"81", + 1877 => x"8f", + 1878 => x"53", + 1879 => x"80", + 1880 => x"88", + 1881 => x"08", + 1882 => x"51", + 1883 => x"91", + 1884 => x"59", + 1885 => x"08", + 1886 => x"77", + 1887 => x"06", + 1888 => x"83", + 1889 => x"05", + 1890 => x"f7", + 1891 => x"39", + 1892 => x"a4", + 1893 => x"52", + 1894 => x"ef", + 1895 => x"88", + 1896 => x"ca", + 1897 => x"38", + 1898 => x"06", + 1899 => x"83", + 1900 => x"18", + 1901 => x"54", + 1902 => x"f6", + 1903 => x"ca", + 1904 => x"0a", + 1905 => x"52", + 1906 => x"83", + 1907 => x"83", + 1908 => x"91", + 1909 => x"8a", + 1910 => x"f8", + 1911 => x"7c", + 1912 => x"59", + 1913 => x"81", + 1914 => x"38", + 1915 => x"08", + 1916 => x"73", + 1917 => x"38", + 1918 => x"52", + 1919 => x"a4", + 1920 => x"88", + 1921 => x"ca", + 1922 => x"f2", + 1923 => x"82", + 1924 => x"39", + 1925 => x"e6", + 1926 => x"88", + 1927 => x"de", + 1928 => x"78", + 1929 => x"3f", + 1930 => x"08", + 1931 => x"88", + 1932 => x"80", + 1933 => x"ca", + 1934 => x"2e", + 1935 => x"ca", + 1936 => x"2e", + 1937 => x"53", + 1938 => x"51", + 1939 => x"91", + 1940 => x"c5", + 1941 => x"08", + 1942 => x"18", + 1943 => x"57", + 1944 => x"90", + 1945 => x"90", + 1946 => x"16", + 1947 => x"54", + 1948 => x"34", + 1949 => x"78", + 1950 => x"38", + 1951 => x"91", + 1952 => x"8a", + 1953 => x"f6", + 1954 => x"7e", + 1955 => x"5b", + 1956 => x"38", + 1957 => x"58", + 1958 => x"88", + 1959 => x"08", + 1960 => x"38", + 1961 => x"39", + 1962 => x"51", + 1963 => x"81", + 1964 => x"ca", + 1965 => x"82", + 1966 => x"ca", + 1967 => x"91", + 1968 => x"ff", + 1969 => x"38", + 1970 => x"91", + 1971 => x"26", + 1972 => x"79", + 1973 => x"08", + 1974 => x"73", + 1975 => x"b9", + 1976 => x"2e", + 1977 => x"80", + 1978 => x"1a", + 1979 => x"08", + 1980 => x"38", + 1981 => x"52", + 1982 => x"af", + 1983 => x"91", + 1984 => x"81", + 1985 => x"06", + 1986 => x"ca", + 1987 => x"91", + 1988 => x"09", + 1989 => x"72", + 1990 => x"70", + 1991 => x"ca", + 1992 => x"51", + 1993 => x"73", + 1994 => x"91", + 1995 => x"80", + 1996 => x"8c", + 1997 => x"81", + 1998 => x"38", + 1999 => x"08", + 2000 => x"73", + 2001 => x"75", + 2002 => x"77", + 2003 => x"56", + 2004 => x"76", + 2005 => x"82", + 2006 => x"26", + 2007 => x"75", + 2008 => x"f8", + 2009 => x"ca", + 2010 => x"2e", + 2011 => x"59", + 2012 => x"08", + 2013 => x"81", + 2014 => x"91", + 2015 => x"59", + 2016 => x"08", + 2017 => x"70", + 2018 => x"25", + 2019 => x"51", + 2020 => x"73", + 2021 => x"75", + 2022 => x"81", + 2023 => x"38", + 2024 => x"f5", + 2025 => x"75", + 2026 => x"f9", + 2027 => x"ca", + 2028 => x"ca", + 2029 => x"70", + 2030 => x"08", + 2031 => x"51", + 2032 => x"80", + 2033 => x"73", + 2034 => x"38", + 2035 => x"52", + 2036 => x"d0", + 2037 => x"88", + 2038 => x"a5", + 2039 => x"18", + 2040 => x"08", + 2041 => x"18", + 2042 => x"74", + 2043 => x"38", + 2044 => x"18", + 2045 => x"33", + 2046 => x"73", + 2047 => x"97", + 2048 => x"74", + 2049 => x"38", + 2050 => x"55", + 2051 => x"ca", + 2052 => x"85", + 2053 => x"75", + 2054 => x"ca", + 2055 => x"3d", + 2056 => x"3d", + 2057 => x"52", + 2058 => x"3f", + 2059 => x"08", + 2060 => x"91", + 2061 => x"80", + 2062 => x"52", + 2063 => x"c1", + 2064 => x"88", + 2065 => x"88", + 2066 => x"0c", + 2067 => x"53", + 2068 => x"15", + 2069 => x"f2", + 2070 => x"56", + 2071 => x"16", + 2072 => x"22", + 2073 => x"27", + 2074 => x"54", + 2075 => x"76", + 2076 => x"33", + 2077 => x"3f", + 2078 => x"08", + 2079 => x"38", + 2080 => x"76", + 2081 => x"70", + 2082 => x"9f", + 2083 => x"56", + 2084 => x"ca", + 2085 => x"3d", + 2086 => x"3d", + 2087 => x"71", + 2088 => x"57", + 2089 => x"0a", + 2090 => x"38", + 2091 => x"53", + 2092 => x"38", + 2093 => x"0c", + 2094 => x"54", + 2095 => x"75", + 2096 => x"73", + 2097 => x"a8", + 2098 => x"73", + 2099 => x"85", + 2100 => x"0b", + 2101 => x"5a", + 2102 => x"27", + 2103 => x"a8", + 2104 => x"18", + 2105 => x"39", + 2106 => x"70", + 2107 => x"58", + 2108 => x"b2", + 2109 => x"76", + 2110 => x"3f", + 2111 => x"08", + 2112 => x"88", + 2113 => x"bd", + 2114 => x"91", + 2115 => x"27", + 2116 => x"16", + 2117 => x"88", + 2118 => x"38", + 2119 => x"39", + 2120 => x"55", + 2121 => x"52", + 2122 => x"d5", + 2123 => x"88", + 2124 => x"0c", + 2125 => x"0c", + 2126 => x"53", + 2127 => x"80", + 2128 => x"85", + 2129 => x"94", + 2130 => x"2a", + 2131 => x"0c", + 2132 => x"06", + 2133 => x"9c", + 2134 => x"58", + 2135 => x"88", + 2136 => x"0d", + 2137 => x"0d", + 2138 => x"90", + 2139 => x"05", + 2140 => x"f0", + 2141 => x"27", + 2142 => x"0b", + 2143 => x"98", + 2144 => x"84", + 2145 => x"2e", + 2146 => x"76", + 2147 => x"58", + 2148 => x"38", + 2149 => x"15", + 2150 => x"08", + 2151 => x"38", + 2152 => x"88", + 2153 => x"53", + 2154 => x"81", + 2155 => x"c0", + 2156 => x"22", + 2157 => x"89", + 2158 => x"72", + 2159 => x"74", + 2160 => x"f3", + 2161 => x"ca", + 2162 => x"82", + 2163 => x"91", + 2164 => x"27", + 2165 => x"81", + 2166 => x"88", + 2167 => x"80", + 2168 => x"16", + 2169 => x"88", + 2170 => x"ca", + 2171 => x"38", + 2172 => x"0c", + 2173 => x"dd", + 2174 => x"08", + 2175 => x"f9", + 2176 => x"ca", + 2177 => x"87", + 2178 => x"88", + 2179 => x"80", + 2180 => x"55", + 2181 => x"08", + 2182 => x"38", + 2183 => x"ca", + 2184 => x"2e", + 2185 => x"ca", + 2186 => x"75", + 2187 => x"3f", + 2188 => x"08", + 2189 => x"94", + 2190 => x"52", + 2191 => x"c1", + 2192 => x"88", + 2193 => x"0c", + 2194 => x"0c", + 2195 => x"05", + 2196 => x"80", + 2197 => x"ca", + 2198 => x"3d", + 2199 => x"3d", + 2200 => x"71", + 2201 => x"57", + 2202 => x"51", + 2203 => x"91", + 2204 => x"54", + 2205 => x"08", + 2206 => x"91", + 2207 => x"56", + 2208 => x"52", + 2209 => x"83", + 2210 => x"88", + 2211 => x"ca", + 2212 => x"d2", + 2213 => x"88", + 2214 => x"08", + 2215 => x"54", + 2216 => x"e5", + 2217 => x"06", + 2218 => x"58", + 2219 => x"08", + 2220 => x"38", + 2221 => x"75", + 2222 => x"80", + 2223 => x"81", + 2224 => x"7a", + 2225 => x"06", + 2226 => x"39", + 2227 => x"08", + 2228 => x"76", + 2229 => x"3f", + 2230 => x"08", + 2231 => x"88", + 2232 => x"ff", + 2233 => x"84", + 2234 => x"06", + 2235 => x"54", + 2236 => x"88", + 2237 => x"0d", + 2238 => x"0d", + 2239 => x"52", + 2240 => x"3f", + 2241 => x"08", + 2242 => x"06", + 2243 => x"51", + 2244 => x"83", + 2245 => x"06", + 2246 => x"14", + 2247 => x"3f", + 2248 => x"08", + 2249 => x"07", + 2250 => x"ca", + 2251 => x"3d", + 2252 => x"3d", + 2253 => x"70", + 2254 => x"06", + 2255 => x"53", + 2256 => x"ed", + 2257 => x"33", + 2258 => x"83", + 2259 => x"06", + 2260 => x"90", + 2261 => x"15", + 2262 => x"3f", + 2263 => x"04", + 2264 => x"7b", + 2265 => x"84", + 2266 => x"58", + 2267 => x"80", + 2268 => x"38", + 2269 => x"52", + 2270 => x"8f", + 2271 => x"88", + 2272 => x"ca", + 2273 => x"f5", + 2274 => x"08", + 2275 => x"53", + 2276 => x"84", + 2277 => x"39", + 2278 => x"70", + 2279 => x"81", + 2280 => x"51", + 2281 => x"16", + 2282 => x"88", + 2283 => x"81", + 2284 => x"38", + 2285 => x"ae", + 2286 => x"81", + 2287 => x"54", + 2288 => x"2e", + 2289 => x"8f", + 2290 => x"91", + 2291 => x"76", + 2292 => x"54", + 2293 => x"09", + 2294 => x"38", + 2295 => x"7a", + 2296 => x"80", + 2297 => x"fa", + 2298 => x"ca", + 2299 => x"91", + 2300 => x"89", + 2301 => x"08", + 2302 => x"86", + 2303 => x"98", + 2304 => x"91", + 2305 => x"8b", + 2306 => x"fb", + 2307 => x"70", + 2308 => x"81", + 2309 => x"fc", + 2310 => x"ca", + 2311 => x"91", + 2312 => x"b4", + 2313 => x"08", + 2314 => x"ec", + 2315 => x"ca", + 2316 => x"91", + 2317 => x"a0", + 2318 => x"91", + 2319 => x"52", + 2320 => x"51", + 2321 => x"8b", + 2322 => x"52", + 2323 => x"51", + 2324 => x"81", + 2325 => x"34", + 2326 => x"88", + 2327 => x"0d", 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x"15", + 2387 => x"70", + 2388 => x"56", + 2389 => x"09", + 2390 => x"38", + 2391 => x"80", + 2392 => x"30", + 2393 => x"78", + 2394 => x"54", + 2395 => x"73", + 2396 => x"60", + 2397 => x"54", + 2398 => x"96", + 2399 => x"0b", + 2400 => x"80", + 2401 => x"f6", + 2402 => x"ca", + 2403 => x"85", + 2404 => x"3d", + 2405 => x"5c", + 2406 => x"53", + 2407 => x"51", + 2408 => x"80", + 2409 => x"88", + 2410 => x"5c", + 2411 => x"09", + 2412 => x"d4", + 2413 => x"70", + 2414 => x"71", + 2415 => x"30", + 2416 => x"73", + 2417 => x"51", + 2418 => x"57", + 2419 => x"38", + 2420 => x"75", + 2421 => x"17", + 2422 => x"75", + 2423 => x"30", + 2424 => x"51", + 2425 => x"80", + 2426 => x"38", + 2427 => x"87", + 2428 => x"26", + 2429 => x"77", + 2430 => x"a4", + 2431 => x"27", + 2432 => x"a0", + 2433 => x"39", + 2434 => x"33", + 2435 => x"57", + 2436 => x"27", + 2437 => x"75", + 2438 => x"30", + 2439 => x"32", + 2440 => x"80", + 2441 => x"25", + 2442 => x"56", + 2443 => x"80", + 2444 => x"84", + 2445 => x"58", + 2446 => x"70", + 2447 => x"55", + 2448 => x"09", + 2449 => x"38", + 2450 => x"80", + 2451 => x"30", + 2452 => x"77", + 2453 => x"54", + 2454 => x"81", + 2455 => x"ae", + 2456 => x"06", + 2457 => x"54", + 2458 => x"74", + 2459 => x"80", + 2460 => x"7b", + 2461 => x"30", + 2462 => x"70", + 2463 => x"25", + 2464 => x"07", + 2465 => x"51", + 2466 => x"a7", + 2467 => x"8b", + 2468 => x"39", + 2469 => x"54", + 2470 => x"8c", + 2471 => x"ff", + 2472 => x"94", + 2473 => x"54", + 2474 => x"e1", + 2475 => x"88", + 2476 => x"b2", + 2477 => x"70", + 2478 => x"71", + 2479 => x"54", + 2480 => x"91", + 2481 => x"80", + 2482 => x"38", + 2483 => x"76", + 2484 => x"df", + 2485 => x"54", + 2486 => x"81", + 2487 => x"55", + 2488 => x"34", + 2489 => x"52", + 2490 => x"51", + 2491 => x"91", + 2492 => x"bf", + 2493 => x"16", + 2494 => x"26", + 2495 => x"16", + 2496 => x"06", + 2497 => x"17", + 2498 => x"34", + 2499 => x"fd", + 2500 => x"19", + 2501 => x"80", + 2502 => x"79", + 2503 => x"81", + 2504 => x"81", + 2505 => x"85", + 2506 => x"54", + 2507 => x"8f", + 2508 => x"86", + 2509 => x"39", + 2510 => x"f3", + 2511 => x"73", + 2512 => x"80", + 2513 => x"52", + 2514 => x"ce", + 2515 => x"88", + 2516 => x"ca", + 2517 => x"d7", + 2518 => x"08", + 2519 => x"e6", + 2520 => x"ca", + 2521 => x"91", + 2522 => x"80", + 2523 => x"1b", + 2524 => x"55", + 2525 => x"2e", + 2526 => x"8b", + 2527 => x"06", + 2528 => x"1c", + 2529 => x"33", + 2530 => x"70", + 2531 => x"55", + 2532 => x"38", + 2533 => x"52", + 2534 => x"9f", + 2535 => x"88", + 2536 => x"8b", + 2537 => x"7a", + 2538 => x"3f", + 2539 => x"75", + 2540 => x"57", + 2541 => x"2e", + 2542 => x"84", + 2543 => x"06", + 2544 => x"75", + 2545 => x"81", + 2546 => x"2a", + 2547 => x"73", + 2548 => x"38", + 2549 => x"54", + 2550 => x"fb", + 2551 => x"80", + 2552 => x"34", + 2553 => x"c1", + 2554 => x"06", + 2555 => x"38", + 2556 => x"39", + 2557 => x"70", + 2558 => x"54", + 2559 => x"86", + 2560 => x"84", + 2561 => x"06", + 2562 => x"73", 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x"38", + 2622 => x"83", + 2623 => x"74", + 2624 => x"59", + 2625 => x"39", + 2626 => x"33", + 2627 => x"ca", + 2628 => x"3d", + 2629 => x"3d", + 2630 => x"80", + 2631 => x"34", + 2632 => x"17", + 2633 => x"75", + 2634 => x"3f", + 2635 => x"ca", + 2636 => x"80", + 2637 => x"16", + 2638 => x"3f", + 2639 => x"08", + 2640 => x"06", + 2641 => x"73", + 2642 => x"2e", + 2643 => x"80", + 2644 => x"0b", + 2645 => x"56", + 2646 => x"e9", + 2647 => x"06", + 2648 => x"57", + 2649 => x"32", + 2650 => x"80", + 2651 => x"51", + 2652 => x"8a", + 2653 => x"e8", + 2654 => x"06", + 2655 => x"53", + 2656 => x"52", + 2657 => x"51", + 2658 => x"91", + 2659 => x"55", + 2660 => x"08", + 2661 => x"38", + 2662 => x"b8", + 2663 => x"86", + 2664 => x"97", + 2665 => x"88", + 2666 => x"ca", + 2667 => x"2e", + 2668 => x"55", + 2669 => x"88", + 2670 => x"0d", + 2671 => x"0d", + 2672 => x"05", + 2673 => x"33", + 2674 => x"75", + 2675 => x"fc", + 2676 => x"ca", + 2677 => x"8b", + 2678 => x"91", + 2679 => x"24", + 2680 => x"91", + 2681 => x"84", + 2682 => x"a4", + 2683 => x"55", + 2684 => x"73", + 2685 => x"e6", + 2686 => x"0c", + 2687 => x"06", + 2688 => x"57", + 2689 => x"ae", + 2690 => x"33", + 2691 => x"3f", + 2692 => x"08", + 2693 => x"70", + 2694 => x"55", + 2695 => x"76", + 2696 => x"b8", + 2697 => x"2a", + 2698 => x"51", + 2699 => x"72", + 2700 => x"86", + 2701 => x"74", + 2702 => x"15", + 2703 => x"81", + 2704 => x"d7", + 2705 => x"ca", + 2706 => x"ff", + 2707 => x"06", + 2708 => x"56", + 2709 => x"38", + 2710 => x"8f", + 2711 => x"2a", + 2712 => x"51", + 2713 => x"72", + 2714 => x"80", + 2715 => x"52", + 2716 => x"3f", + 2717 => x"08", + 2718 => x"57", + 2719 => x"09", + 2720 => x"e2", + 2721 => x"74", + 2722 => x"56", + 2723 => x"33", + 2724 => x"72", + 2725 => x"38", + 2726 => x"51", + 2727 => x"91", + 2728 => x"57", + 2729 => x"84", + 2730 => x"ff", + 2731 => x"56", + 2732 => x"25", + 2733 => x"0b", + 2734 => x"56", + 2735 => x"05", + 2736 => x"83", + 2737 => x"2e", + 2738 => x"52", + 2739 => x"c6", + 2740 => x"88", + 2741 => x"06", + 2742 => x"27", + 2743 => x"16", + 2744 => x"27", + 2745 => x"56", + 2746 => x"84", + 2747 => x"56", + 2748 => x"84", + 2749 => x"14", + 2750 => x"3f", + 2751 => x"08", + 2752 => x"06", + 2753 => x"80", + 2754 => x"06", + 2755 => x"80", + 2756 => x"db", + 2757 => x"ca", + 2758 => x"ff", + 2759 => x"77", + 2760 => x"d8", + 2761 => x"de", + 2762 => x"88", + 2763 => x"9c", + 2764 => x"c4", + 2765 => x"15", + 2766 => x"14", + 2767 => x"70", + 2768 => x"51", + 2769 => x"56", + 2770 => x"84", + 2771 => x"81", + 2772 => x"71", + 2773 => x"16", + 2774 => x"53", + 2775 => x"23", + 2776 => x"8b", + 2777 => x"73", + 2778 => x"80", + 2779 => x"8d", + 2780 => x"39", + 2781 => x"51", + 2782 => x"91", + 2783 => x"53", + 2784 => x"08", + 2785 => x"72", + 2786 => x"8d", + 2787 => x"ce", + 2788 => x"14", + 2789 => x"3f", + 2790 => x"08", + 2791 => x"06", + 2792 => x"38", + 2793 => x"51", + 2794 => x"91", + 2795 => x"55", + 2796 => x"51", + 2797 => x"91", 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x"0c", + 2857 => x"84", + 2858 => x"83", + 2859 => x"06", + 2860 => x"80", + 2861 => x"d8", + 2862 => x"ca", + 2863 => x"ff", + 2864 => x"72", + 2865 => x"81", + 2866 => x"38", + 2867 => x"73", + 2868 => x"3f", + 2869 => x"08", + 2870 => x"91", + 2871 => x"84", + 2872 => x"b2", + 2873 => x"87", + 2874 => x"88", + 2875 => x"ff", + 2876 => x"82", + 2877 => x"09", + 2878 => x"c8", + 2879 => x"51", + 2880 => x"91", + 2881 => x"84", + 2882 => x"d2", + 2883 => x"06", + 2884 => x"98", + 2885 => x"ee", + 2886 => x"88", + 2887 => x"85", + 2888 => x"09", + 2889 => x"38", + 2890 => x"51", + 2891 => x"91", + 2892 => x"90", + 2893 => x"a0", + 2894 => x"ca", + 2895 => x"88", + 2896 => x"0c", + 2897 => x"91", + 2898 => x"81", + 2899 => x"91", + 2900 => x"72", + 2901 => x"80", + 2902 => x"0c", + 2903 => x"91", + 2904 => x"90", + 2905 => x"fb", + 2906 => x"54", + 2907 => x"80", + 2908 => x"73", + 2909 => x"80", + 2910 => x"72", + 2911 => x"80", + 2912 => x"86", + 2913 => x"15", + 2914 => x"71", + 2915 => x"81", + 2916 => x"81", + 2917 => x"d0", + 2918 => x"ca", + 2919 => x"06", + 2920 => x"38", + 2921 => x"54", + 2922 => x"80", + 2923 => x"71", + 2924 => x"91", + 2925 => x"87", + 2926 => x"fa", + 2927 => x"ab", + 2928 => x"58", + 2929 => x"05", + 2930 => x"e6", + 2931 => x"80", + 2932 => x"88", + 2933 => x"38", + 2934 => x"08", + 2935 => x"ca", + 2936 => x"08", + 2937 => x"80", + 2938 => x"80", + 2939 => x"54", + 2940 => x"84", + 2941 => x"34", + 2942 => x"75", + 2943 => x"2e", + 2944 => x"53", + 2945 => x"53", + 2946 => x"f7", + 2947 => x"ca", + 2948 => x"73", + 2949 => x"0c", + 2950 => x"04", + 2951 => x"67", + 2952 => x"80", + 2953 => x"59", + 2954 => x"78", + 2955 => x"c8", + 2956 => x"06", + 2957 => x"3d", + 2958 => x"99", + 2959 => x"52", + 2960 => x"3f", + 2961 => x"08", + 2962 => x"88", + 2963 => x"38", + 2964 => x"52", + 2965 => x"52", + 2966 => x"3f", + 2967 => x"08", + 2968 => x"88", + 2969 => x"02", + 2970 => x"33", + 2971 => x"55", + 2972 => x"25", + 2973 => x"55", + 2974 => x"54", + 2975 => x"81", + 2976 => x"80", + 2977 => x"74", + 2978 => x"81", + 2979 => x"75", + 2980 => x"3f", + 2981 => x"08", + 2982 => x"02", + 2983 => x"91", + 2984 => x"81", + 2985 => x"82", + 2986 => x"06", + 2987 => x"80", + 2988 => x"88", + 2989 => x"39", + 2990 => x"58", + 2991 => x"38", + 2992 => x"70", + 2993 => x"54", + 2994 => x"81", + 2995 => x"52", + 2996 => x"a5", + 2997 => x"88", + 2998 => x"88", + 2999 => x"62", + 3000 => x"d4", + 3001 => x"54", + 3002 => x"15", + 3003 => x"62", + 3004 => x"e8", + 3005 => x"52", + 3006 => x"51", + 3007 => x"7a", + 3008 => x"83", + 3009 => x"80", + 3010 => x"38", + 3011 => x"08", + 3012 => x"53", + 3013 => x"3d", + 3014 => x"dd", + 3015 => x"ca", + 3016 => x"91", + 3017 => x"82", + 3018 => x"39", + 3019 => x"38", + 3020 => x"33", + 3021 => x"70", + 3022 => x"55", + 3023 => x"2e", + 3024 => x"55", + 3025 => x"77", + 3026 => x"81", + 3027 => x"73", + 3028 => x"38", + 3029 => x"54", + 3030 => x"a0", + 3031 => x"82", + 3032 => x"52", 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x"54", + 3092 => x"a2", + 3093 => x"7a", + 3094 => x"3f", + 3095 => x"08", + 3096 => x"55", + 3097 => x"89", + 3098 => x"88", + 3099 => x"1a", + 3100 => x"80", + 3101 => x"54", + 3102 => x"88", + 3103 => x"0d", + 3104 => x"0d", + 3105 => x"64", + 3106 => x"59", + 3107 => x"90", + 3108 => x"52", + 3109 => x"cf", + 3110 => x"88", + 3111 => x"ca", + 3112 => x"38", + 3113 => x"55", + 3114 => x"86", + 3115 => x"82", + 3116 => x"19", + 3117 => x"55", + 3118 => x"80", + 3119 => x"38", + 3120 => x"0b", + 3121 => x"82", + 3122 => x"39", + 3123 => x"1a", + 3124 => x"82", + 3125 => x"19", + 3126 => x"08", + 3127 => x"7c", + 3128 => x"74", + 3129 => x"2e", + 3130 => x"94", + 3131 => x"83", + 3132 => x"56", + 3133 => x"38", + 3134 => x"22", + 3135 => x"89", + 3136 => x"55", + 3137 => x"75", + 3138 => x"19", + 3139 => x"39", + 3140 => x"52", + 3141 => x"93", + 3142 => x"88", + 3143 => x"75", + 3144 => x"38", + 3145 => x"ff", + 3146 => x"98", + 3147 => x"19", + 3148 => x"51", + 3149 => x"91", + 3150 => x"80", + 3151 => x"38", + 3152 => x"08", + 3153 => x"2a", + 3154 => x"80", + 3155 => x"38", + 3156 => x"8a", + 3157 => x"5c", + 3158 => x"27", + 3159 => x"7a", + 3160 => x"54", + 3161 => x"52", + 3162 => x"51", + 3163 => x"91", + 3164 => x"fe", + 3165 => x"83", + 3166 => x"56", + 3167 => x"9f", + 3168 => x"08", + 3169 => x"74", + 3170 => x"38", + 3171 => x"b4", + 3172 => x"16", + 3173 => x"89", + 3174 => x"51", + 3175 => x"77", + 3176 => x"b9", + 3177 => x"1a", + 3178 => x"08", + 3179 => x"84", + 3180 => x"57", + 3181 => x"27", + 3182 => x"56", + 3183 => x"52", + 3184 => x"c7", + 3185 => x"88", + 3186 => x"38", + 3187 => x"19", + 3188 => x"06", + 3189 => x"52", + 3190 => x"a2", + 3191 => x"31", + 3192 => x"7f", + 3193 => x"94", + 3194 => x"94", + 3195 => x"5c", + 3196 => x"80", + 3197 => x"ca", + 3198 => x"3d", + 3199 => x"3d", + 3200 => x"65", + 3201 => x"5d", + 3202 => x"0c", + 3203 => x"05", + 3204 => x"f6", + 3205 => x"ca", + 3206 => x"91", + 3207 => x"8a", + 3208 => x"33", + 3209 => x"2e", + 3210 => x"56", + 3211 => x"90", + 3212 => x"81", + 3213 => x"06", + 3214 => x"87", + 3215 => x"2e", + 3216 => x"95", + 3217 => x"91", + 3218 => x"56", + 3219 => x"81", + 3220 => x"34", + 3221 => x"8e", + 3222 => x"08", + 3223 => x"56", + 3224 => x"84", + 3225 => x"5c", + 3226 => x"82", + 3227 => x"18", + 3228 => x"ff", + 3229 => x"74", + 3230 => x"7e", + 3231 => x"ff", + 3232 => x"2a", + 3233 => x"7a", + 3234 => x"8c", + 3235 => x"08", + 3236 => x"38", + 3237 => x"39", + 3238 => x"52", + 3239 => x"e7", + 3240 => x"88", + 3241 => x"ca", + 3242 => x"2e", + 3243 => x"74", + 3244 => x"91", + 3245 => x"2e", + 3246 => x"74", + 3247 => x"88", + 3248 => x"38", + 3249 => x"0c", + 3250 => x"15", + 3251 => x"08", + 3252 => x"06", + 3253 => x"51", + 3254 => x"91", + 3255 => x"fe", + 3256 => x"18", + 3257 => x"51", + 3258 => x"91", + 3259 => x"80", + 3260 => x"38", + 3261 => x"08", + 3262 => x"2a", + 3263 => x"80", + 3264 => x"38", + 3265 => x"8a", + 3266 => x"5b", + 3267 => x"27", + 3268 => x"7b", + 3269 => x"54", + 3270 => x"52", + 3271 => x"51", + 3272 => x"91", + 3273 => x"fe", + 3274 => x"b0", + 3275 => x"31", + 3276 => x"79", + 3277 => x"84", + 3278 => x"16", + 3279 => x"89", + 3280 => x"52", + 3281 => x"cc", + 3282 => x"55", + 3283 => x"16", + 3284 => x"2b", + 3285 => x"39", + 3286 => x"94", + 3287 => x"93", + 3288 => x"cd", + 3289 => x"ca", + 3290 => x"e3", + 3291 => x"b0", + 3292 => x"76", + 3293 => x"94", + 3294 => x"ff", + 3295 => x"71", + 3296 => x"7b", + 3297 => x"38", + 3298 => x"18", + 3299 => x"51", + 3300 => x"91", + 3301 => x"fd", + 3302 => x"53", + 3303 => x"18", + 3304 => x"06", + 3305 => x"51", + 3306 => x"7e", + 3307 => x"83", + 3308 => x"76", + 3309 => x"17", + 3310 => x"1e", + 3311 => x"18", + 3312 => x"0c", + 3313 => x"58", + 3314 => x"74", + 3315 => x"38", + 3316 => x"8c", + 3317 => x"90", + 3318 => x"33", + 3319 => x"55", + 3320 => x"34", + 3321 => x"91", + 3322 => x"90", + 3323 => x"f8", + 3324 => x"8b", + 3325 => x"53", + 3326 => x"f2", + 3327 => x"ca", + 3328 => x"91", + 3329 => x"80", + 3330 => x"16", + 3331 => x"2a", + 3332 => x"51", + 3333 => x"80", + 3334 => x"38", + 3335 => x"52", + 3336 => x"e7", + 3337 => x"88", + 3338 => x"ca", + 3339 => x"d4", + 3340 => x"08", + 3341 => x"a0", + 3342 => x"73", + 3343 => x"88", + 3344 => x"74", + 3345 => x"51", + 3346 => x"8c", + 3347 => x"9c", + 3348 => x"fb", + 3349 => x"b2", + 3350 => x"15", + 3351 => x"3f", + 3352 => x"15", + 3353 => x"3f", + 3354 => x"0b", + 3355 => x"78", + 3356 => x"3f", + 3357 => x"08", + 3358 => x"81", + 3359 => x"57", + 3360 => x"34", + 3361 => x"88", + 3362 => x"0d", + 3363 => x"0d", + 3364 => x"54", + 3365 => x"91", + 3366 => x"53", + 3367 => x"08", + 3368 => x"3d", + 3369 => x"73", + 3370 => x"3f", + 3371 => x"08", + 3372 => x"88", + 3373 => x"91", + 3374 => x"74", + 3375 => x"ca", + 3376 => x"3d", + 3377 => x"3d", + 3378 => x"51", + 3379 => x"8b", + 3380 => x"91", + 3381 => x"24", + 3382 => x"ca", + 3383 => x"ca", + 3384 => x"52", + 3385 => x"88", + 3386 => x"0d", + 3387 => x"0d", + 3388 => x"3d", + 3389 => x"94", + 3390 => x"c1", + 3391 => x"88", + 3392 => x"ca", + 3393 => x"e0", + 3394 => x"63", + 3395 => x"d4", + 3396 => x"8d", + 3397 => x"88", + 3398 => x"ca", + 3399 => x"38", + 3400 => x"05", + 3401 => x"2b", + 3402 => x"80", + 3403 => x"76", + 3404 => x"0c", + 3405 => x"02", + 3406 => x"70", + 3407 => x"81", + 3408 => x"56", + 3409 => x"9e", + 3410 => x"53", + 3411 => x"db", + 3412 => x"ca", + 3413 => x"15", + 3414 => x"91", + 3415 => x"84", + 3416 => x"06", + 3417 => x"55", + 3418 => x"88", + 3419 => x"0d", + 3420 => x"0d", + 3421 => x"5b", + 3422 => x"80", + 3423 => x"ff", + 3424 => x"9f", + 3425 => x"b5", + 3426 => x"88", + 3427 => x"ca", + 3428 => x"fc", + 3429 => x"7a", + 3430 => x"08", + 3431 => x"64", + 3432 => x"2e", + 3433 => x"a0", + 3434 => x"70", + 3435 => x"ea", + 3436 => x"88", + 3437 => x"ca", + 3438 => x"d4", + 3439 => x"7b", + 3440 => x"3f", + 3441 => x"08", + 3442 => x"88", + 3443 => x"38", + 3444 => x"51", + 3445 => x"91", + 3446 => x"45", + 3447 => x"51", + 3448 => x"91", + 3449 => x"57", + 3450 => x"08", + 3451 => x"80", + 3452 => x"da", + 3453 => x"ca", + 3454 => x"91", + 3455 => x"a4", + 3456 => x"7b", + 3457 => x"3f", + 3458 => x"88", + 3459 => x"38", + 3460 => x"51", + 3461 => x"91", + 3462 => x"57", + 3463 => x"08", + 3464 => x"38", + 3465 => x"09", + 3466 => x"38", + 3467 => x"e0", + 3468 => x"dc", + 3469 => x"ff", + 3470 => x"74", + 3471 => x"3f", + 3472 => x"78", + 3473 => x"33", + 3474 => x"56", + 3475 => x"91", + 3476 => x"05", + 3477 => x"81", + 3478 => x"56", + 3479 => x"f5", + 3480 => x"54", + 3481 => x"81", + 3482 => x"80", + 3483 => x"78", + 3484 => x"55", + 3485 => x"11", + 3486 => x"18", + 3487 => x"58", + 3488 => x"34", + 3489 => x"ff", + 3490 => x"55", + 3491 => x"34", + 3492 => x"77", + 3493 => x"81", + 3494 => x"ff", + 3495 => x"55", + 3496 => x"34", + 3497 => x"ca", + 3498 => x"84", + 3499 => x"84", + 3500 => x"70", + 3501 => x"56", + 3502 => x"76", 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x"98", + 3562 => x"58", + 3563 => x"39", + 3564 => x"54", + 3565 => x"73", + 3566 => x"cd", + 3567 => x"ca", + 3568 => x"91", + 3569 => x"81", + 3570 => x"38", + 3571 => x"08", + 3572 => x"9b", + 3573 => x"88", + 3574 => x"0c", + 3575 => x"0c", + 3576 => x"81", + 3577 => x"76", + 3578 => x"38", + 3579 => x"94", + 3580 => x"94", + 3581 => x"16", + 3582 => x"2a", + 3583 => x"51", + 3584 => x"72", + 3585 => x"38", + 3586 => x"51", + 3587 => x"91", + 3588 => x"54", + 3589 => x"08", + 3590 => x"ca", + 3591 => x"a7", + 3592 => x"74", + 3593 => x"3f", + 3594 => x"08", + 3595 => x"2e", + 3596 => x"74", + 3597 => x"79", + 3598 => x"14", + 3599 => x"38", + 3600 => x"0c", + 3601 => x"94", + 3602 => x"94", + 3603 => x"83", + 3604 => x"72", + 3605 => x"38", + 3606 => x"51", + 3607 => x"91", + 3608 => x"94", + 3609 => x"91", + 3610 => x"53", + 3611 => x"81", + 3612 => x"34", + 3613 => x"39", + 3614 => x"91", + 3615 => x"05", + 3616 => x"08", + 3617 => x"08", + 3618 => x"38", + 3619 => x"0c", + 3620 => x"80", + 3621 => x"72", + 3622 => x"73", + 3623 => x"53", + 3624 => x"8c", + 3625 => x"16", + 3626 => x"38", + 3627 => x"0c", + 3628 => x"91", + 3629 => x"8b", + 3630 => x"f9", + 3631 => x"56", + 3632 => x"80", + 3633 => x"38", + 3634 => x"3d", + 3635 => x"8a", + 3636 => x"51", + 3637 => x"91", + 3638 => x"55", + 3639 => x"08", + 3640 => x"77", + 3641 => x"52", + 3642 => x"b5", + 3643 => x"88", + 3644 => x"ca", + 3645 => x"c3", + 3646 => x"33", + 3647 => x"55", + 3648 => x"24", + 3649 => x"16", + 3650 => x"2a", + 3651 => x"51", + 3652 => x"80", + 3653 => x"9c", + 3654 => x"77", + 3655 => x"3f", + 3656 => x"08", + 3657 => x"77", + 3658 => x"22", + 3659 => x"74", + 3660 => x"ce", + 3661 => x"ca", + 3662 => x"74", + 3663 => x"81", + 3664 => x"85", + 3665 => x"74", + 3666 => x"38", + 3667 => x"74", + 3668 => x"ca", + 3669 => x"3d", + 3670 => x"3d", + 3671 => x"3d", + 3672 => x"70", + 3673 => x"ff", + 3674 => x"88", + 3675 => x"91", + 3676 => x"73", + 3677 => x"0d", + 3678 => x"0d", + 3679 => x"3d", + 3680 => x"71", + 3681 => x"e7", + 3682 => x"ca", + 3683 => x"91", + 3684 => x"80", + 3685 => x"93", + 3686 => x"88", + 3687 => x"51", + 3688 => x"91", + 3689 => x"53", + 3690 => x"91", + 3691 => x"52", + 3692 => x"ac", + 3693 => x"88", + 3694 => x"ca", + 3695 => x"2e", + 3696 => x"85", + 3697 => x"87", + 3698 => x"88", + 3699 => x"74", + 3700 => x"d5", + 3701 => x"52", + 3702 => x"89", + 3703 => x"88", + 3704 => x"70", + 3705 => x"07", + 3706 => x"91", + 3707 => x"06", + 3708 => x"54", + 3709 => x"88", + 3710 => x"0d", + 3711 => x"0d", + 3712 => x"53", + 3713 => x"53", + 3714 => x"56", + 3715 => x"91", + 3716 => x"55", + 3717 => x"08", + 3718 => x"52", + 3719 => x"81", + 3720 => x"88", + 3721 => x"ca", + 3722 => x"38", + 3723 => x"05", + 3724 => x"2b", + 3725 => x"80", + 3726 => x"86", + 3727 => x"76", + 3728 => x"38", + 3729 => x"51", + 3730 => x"74", + 3731 => x"0c", + 3732 => x"04", + 3733 => x"63", + 3734 => x"80", + 3735 => x"ec", + 3736 => x"3d", + 3737 => x"3f", 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x"51", + 3797 => x"ff", + 3798 => x"56", + 3799 => x"38", + 3800 => x"7c", + 3801 => x"0c", + 3802 => x"81", + 3803 => x"74", + 3804 => x"7a", + 3805 => x"0c", + 3806 => x"04", + 3807 => x"79", + 3808 => x"05", + 3809 => x"57", + 3810 => x"91", + 3811 => x"56", + 3812 => x"08", + 3813 => x"91", + 3814 => x"75", + 3815 => x"90", + 3816 => x"81", + 3817 => x"06", + 3818 => x"87", + 3819 => x"2e", + 3820 => x"94", + 3821 => x"73", + 3822 => x"27", + 3823 => x"73", + 3824 => x"ca", + 3825 => x"88", + 3826 => x"76", + 3827 => x"3f", + 3828 => x"08", + 3829 => x"0c", + 3830 => x"39", + 3831 => x"52", + 3832 => x"bf", + 3833 => x"ca", + 3834 => x"2e", + 3835 => x"83", + 3836 => x"91", + 3837 => x"81", + 3838 => x"06", + 3839 => x"56", + 3840 => x"a0", + 3841 => x"91", + 3842 => x"98", + 3843 => x"94", + 3844 => x"08", + 3845 => x"88", + 3846 => x"51", + 3847 => x"91", + 3848 => x"56", + 3849 => x"8c", + 3850 => x"17", + 3851 => x"07", + 3852 => x"18", + 3853 => x"2e", + 3854 => x"91", + 3855 => x"55", + 3856 => x"88", + 3857 => x"0d", + 3858 => x"0d", + 3859 => x"3d", + 3860 => x"52", + 3861 => x"da", + 3862 => x"ca", + 3863 => x"91", + 3864 => x"81", + 3865 => x"45", + 3866 => x"52", + 3867 => x"52", + 3868 => x"3f", + 3869 => x"08", + 3870 => x"88", + 3871 => x"38", + 3872 => x"05", + 3873 => x"2a", + 3874 => x"51", + 3875 => x"55", + 3876 => x"38", + 3877 => x"54", + 3878 => x"81", + 3879 => x"80", + 3880 => x"70", + 3881 => x"54", + 3882 => x"81", + 3883 => x"52", + 3884 => x"c5", + 3885 => x"88", + 3886 => x"2a", + 3887 => x"51", + 3888 => x"80", + 3889 => x"38", + 3890 => x"ca", + 3891 => x"15", + 3892 => x"86", + 3893 => x"91", + 3894 => x"5c", + 3895 => x"3d", + 3896 => x"c7", + 3897 => x"ca", + 3898 => x"91", + 3899 => x"80", + 3900 => x"ca", + 3901 => x"73", + 3902 => x"3f", + 3903 => x"08", + 3904 => x"88", + 3905 => x"87", + 3906 => x"39", + 3907 => x"08", + 3908 => x"38", + 3909 => x"08", + 3910 => x"77", + 3911 => x"3f", + 3912 => x"08", + 3913 => x"08", + 3914 => x"ca", + 3915 => x"80", + 3916 => x"55", + 3917 => x"94", + 3918 => x"2e", + 3919 => x"53", + 3920 => x"51", + 3921 => x"91", + 3922 => x"55", + 3923 => x"78", + 3924 => x"fe", + 3925 => x"88", + 3926 => x"91", + 3927 => x"a0", + 3928 => x"e9", + 3929 => x"53", + 3930 => x"05", + 3931 => x"51", + 3932 => x"91", + 3933 => x"54", + 3934 => x"08", + 3935 => x"78", + 3936 => x"8e", + 3937 => x"58", + 3938 => x"91", + 3939 => x"54", + 3940 => x"08", + 3941 => x"54", + 3942 => x"91", + 3943 => x"84", + 3944 => x"06", + 3945 => x"02", + 3946 => x"33", + 3947 => x"81", + 3948 => x"86", + 3949 => x"f6", + 3950 => x"74", + 3951 => x"70", + 3952 => x"c3", + 3953 => x"88", + 3954 => x"56", + 3955 => x"08", + 3956 => x"54", + 3957 => x"08", + 3958 => x"81", + 3959 => x"82", + 3960 => x"88", + 3961 => x"09", + 3962 => x"38", + 3963 => x"b4", + 3964 => x"b0", + 3965 => x"88", + 3966 => x"51", + 3967 => x"91", + 3968 => x"54", + 3969 => x"08", + 3970 => x"8b", + 3971 => x"b4", + 3972 => x"b7", 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x"86", + 4032 => x"aa", + 4033 => x"a4", + 4034 => x"a8", + 4035 => x"05", + 4036 => x"ea", + 4037 => x"77", + 4038 => x"70", + 4039 => x"b4", + 4040 => x"3d", + 4041 => x"51", + 4042 => x"91", + 4043 => x"55", + 4044 => x"08", + 4045 => x"6f", + 4046 => x"06", + 4047 => x"a2", + 4048 => x"92", + 4049 => x"81", + 4050 => x"ca", + 4051 => x"2e", + 4052 => x"81", + 4053 => x"51", + 4054 => x"91", + 4055 => x"55", + 4056 => x"08", + 4057 => x"68", + 4058 => x"a8", + 4059 => x"05", + 4060 => x"51", + 4061 => x"3f", + 4062 => x"33", + 4063 => x"8b", + 4064 => x"84", + 4065 => x"06", + 4066 => x"73", + 4067 => x"a0", + 4068 => x"8b", + 4069 => x"54", + 4070 => x"15", + 4071 => x"33", + 4072 => x"70", + 4073 => x"55", + 4074 => x"2e", + 4075 => x"6e", + 4076 => x"df", + 4077 => x"78", + 4078 => x"3f", + 4079 => x"08", + 4080 => x"ff", + 4081 => x"82", + 4082 => x"88", + 4083 => x"80", + 4084 => x"ca", + 4085 => x"78", + 4086 => x"af", + 4087 => x"88", + 4088 => x"d4", + 4089 => x"55", + 4090 => x"08", + 4091 => x"81", + 4092 => x"73", + 4093 => x"81", + 4094 => x"63", + 4095 => x"76", + 4096 => x"3f", + 4097 => x"0b", + 4098 => x"87", + 4099 => x"88", + 4100 => x"77", + 4101 => x"3f", + 4102 => x"08", + 4103 => x"88", + 4104 => x"78", + 4105 => x"aa", + 4106 => x"88", + 4107 => x"91", + 4108 => x"a8", + 4109 => x"ed", + 4110 => x"80", + 4111 => x"02", + 4112 => x"df", + 4113 => x"57", + 4114 => x"3d", + 4115 => x"96", + 4116 => x"e9", + 4117 => x"88", + 4118 => x"ca", + 4119 => x"cf", + 4120 => x"65", + 4121 => x"d4", + 4122 => x"b5", + 4123 => x"88", + 4124 => x"ca", + 4125 => x"38", + 4126 => x"05", + 4127 => x"06", + 4128 => x"73", + 4129 => x"a7", + 4130 => x"09", + 4131 => x"71", + 4132 => x"06", + 4133 => x"55", + 4134 => x"15", + 4135 => x"81", + 4136 => x"34", + 4137 => x"b4", + 4138 => x"ca", + 4139 => x"74", + 4140 => x"0c", + 4141 => x"04", + 4142 => x"64", + 4143 => x"93", + 4144 => x"52", + 4145 => x"d1", + 4146 => x"ca", + 4147 => x"91", + 4148 => x"80", + 4149 => x"58", + 4150 => x"3d", + 4151 => x"c8", + 4152 => x"ca", + 4153 => x"91", + 4154 => x"b4", + 4155 => x"c7", + 4156 => x"a0", + 4157 => x"55", + 4158 => x"84", + 4159 => x"17", + 4160 => x"2b", + 4161 => x"96", + 4162 => x"b0", + 4163 => x"54", + 4164 => x"15", + 4165 => x"ff", + 4166 => x"91", + 4167 => x"55", + 4168 => x"88", + 4169 => x"0d", + 4170 => x"0d", + 4171 => x"5a", + 4172 => x"3d", + 4173 => x"99", + 4174 => x"81", + 4175 => x"88", + 4176 => x"88", + 4177 => x"91", + 4178 => x"07", + 4179 => x"55", + 4180 => x"2e", + 4181 => x"81", + 4182 => x"55", + 4183 => x"2e", + 4184 => x"7b", + 4185 => x"80", + 4186 => x"70", + 4187 => x"be", + 4188 => x"ca", + 4189 => x"91", + 4190 => x"80", + 4191 => x"52", + 4192 => x"dc", + 4193 => x"88", + 4194 => x"ca", + 4195 => x"38", + 4196 => x"08", + 4197 => x"08", + 4198 => x"56", + 4199 => x"19", + 4200 => x"59", + 4201 => x"74", + 4202 => x"56", + 4203 => x"ec", + 4204 => x"75", + 4205 => x"74", + 4206 => x"2e", + 4207 => x"16", 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x"39", + 4267 => x"08", + 4268 => x"15", + 4269 => x"ff", + 4270 => x"73", + 4271 => x"38", + 4272 => x"83", + 4273 => x"56", + 4274 => x"75", + 4275 => x"91", + 4276 => x"33", + 4277 => x"2e", + 4278 => x"52", + 4279 => x"51", + 4280 => x"3f", + 4281 => x"08", + 4282 => x"ff", + 4283 => x"38", + 4284 => x"88", + 4285 => x"8a", + 4286 => x"38", + 4287 => x"ec", + 4288 => x"75", + 4289 => x"74", + 4290 => x"73", + 4291 => x"05", + 4292 => x"17", + 4293 => x"70", + 4294 => x"34", + 4295 => x"70", + 4296 => x"ff", + 4297 => x"55", + 4298 => x"26", + 4299 => x"8b", + 4300 => x"86", + 4301 => x"e5", + 4302 => x"38", + 4303 => x"99", + 4304 => x"05", + 4305 => x"70", + 4306 => x"73", + 4307 => x"81", + 4308 => x"ff", + 4309 => x"ed", + 4310 => x"80", + 4311 => x"91", + 4312 => x"55", + 4313 => x"3f", + 4314 => x"08", + 4315 => x"88", + 4316 => x"38", + 4317 => x"51", + 4318 => x"3f", + 4319 => x"08", + 4320 => x"88", + 4321 => x"76", + 4322 => x"67", + 4323 => x"34", + 4324 => x"91", + 4325 => x"84", + 4326 => x"06", + 4327 => x"80", + 4328 => x"2e", + 4329 => x"81", + 4330 => x"ff", + 4331 => x"91", + 4332 => x"54", + 4333 => x"08", + 4334 => x"53", + 4335 => x"08", + 4336 => x"ff", + 4337 => x"67", + 4338 => x"8b", + 4339 => x"53", + 4340 => x"51", + 4341 => x"3f", + 4342 => x"0b", + 4343 => x"79", + 4344 => x"ee", + 4345 => x"88", + 4346 => x"55", + 4347 => x"88", + 4348 => x"0d", + 4349 => x"0d", + 4350 => x"88", + 4351 => x"05", + 4352 => x"fc", + 4353 => x"54", + 4354 => x"d2", + 4355 => x"ca", + 4356 => x"91", + 4357 => x"82", + 4358 => x"1a", + 4359 => x"82", + 4360 => x"80", + 4361 => x"8c", + 4362 => x"78", + 4363 => x"1a", + 4364 => x"2a", + 4365 => x"51", + 4366 => x"90", + 4367 => x"82", + 4368 => x"58", + 4369 => x"81", + 4370 => x"39", + 4371 => x"22", + 4372 => x"70", + 4373 => x"56", + 4374 => x"82", + 4375 => x"14", + 4376 => x"30", + 4377 => x"9f", + 4378 => x"88", + 4379 => x"19", + 4380 => x"5a", + 4381 => x"81", + 4382 => x"38", + 4383 => x"77", + 4384 => x"82", + 4385 => x"56", + 4386 => x"74", + 4387 => x"ff", + 4388 => x"81", + 4389 => x"55", + 4390 => x"75", + 4391 => x"82", + 4392 => x"88", + 4393 => x"ff", + 4394 => x"ca", + 4395 => x"2e", + 4396 => x"91", + 4397 => x"8e", + 4398 => x"56", + 4399 => x"09", + 4400 => x"38", + 4401 => x"59", + 4402 => x"77", + 4403 => x"06", + 4404 => x"87", + 4405 => x"39", + 4406 => x"ba", + 4407 => x"55", + 4408 => x"2e", + 4409 => x"15", + 4410 => x"2e", + 4411 => x"83", + 4412 => x"75", + 4413 => x"7e", + 4414 => x"a8", + 4415 => x"88", + 4416 => x"ca", + 4417 => x"ce", + 4418 => x"16", + 4419 => x"56", + 4420 => x"38", + 4421 => x"19", + 4422 => x"8c", + 4423 => x"7d", + 4424 => x"38", + 4425 => x"0c", + 4426 => x"0c", + 4427 => x"80", + 4428 => x"73", + 4429 => x"98", + 4430 => x"05", + 4431 => x"57", + 4432 => x"26", + 4433 => x"7b", + 4434 => x"0c", + 4435 => x"81", + 4436 => x"84", + 4437 => x"54", + 4438 => x"88", + 4439 => x"0d", + 4440 => x"0d", + 4441 => x"88", + 4442 => x"05", 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x"08", + 4502 => x"74", + 4503 => x"41", + 4504 => x"56", + 4505 => x"8a", + 4506 => x"61", + 4507 => x"55", + 4508 => x"27", + 4509 => x"93", + 4510 => x"80", + 4511 => x"38", + 4512 => x"70", + 4513 => x"43", + 4514 => x"95", + 4515 => x"06", + 4516 => x"2e", + 4517 => x"77", + 4518 => x"74", + 4519 => x"83", + 4520 => x"06", + 4521 => x"82", + 4522 => x"2e", + 4523 => x"78", + 4524 => x"2e", + 4525 => x"80", + 4526 => x"ae", + 4527 => x"2a", + 4528 => x"91", + 4529 => x"56", + 4530 => x"2e", + 4531 => x"77", + 4532 => x"91", + 4533 => x"79", + 4534 => x"70", + 4535 => x"5a", + 4536 => x"86", + 4537 => x"27", + 4538 => x"52", + 4539 => x"fc", + 4540 => x"ca", + 4541 => x"29", + 4542 => x"70", + 4543 => x"55", + 4544 => x"0b", + 4545 => x"08", + 4546 => x"05", + 4547 => x"ff", + 4548 => x"27", + 4549 => x"88", + 4550 => x"ae", + 4551 => x"2a", + 4552 => x"91", + 4553 => x"56", + 4554 => x"2e", + 4555 => x"77", + 4556 => x"91", + 4557 => x"79", + 4558 => x"70", + 4559 => x"5a", + 4560 => x"86", + 4561 => x"27", + 4562 => x"52", + 4563 => x"fc", + 4564 => x"ca", + 4565 => x"84", + 4566 => x"ca", + 4567 => x"f5", + 4568 => x"81", + 4569 => x"88", + 4570 => x"ca", + 4571 => x"71", + 4572 => x"83", + 4573 => x"5e", + 4574 => x"89", + 4575 => x"5c", + 4576 => x"1c", + 4577 => x"05", + 4578 => x"ff", + 4579 => x"70", + 4580 => x"31", + 4581 => x"57", + 4582 => x"83", + 4583 => x"06", + 4584 => x"1c", + 4585 => x"5c", + 4586 => x"1d", + 4587 => x"29", + 4588 => x"31", + 4589 => x"55", + 4590 => x"87", + 4591 => x"7c", + 4592 => x"7a", + 4593 => x"31", + 4594 => x"fb", + 4595 => x"ca", + 4596 => x"7d", + 4597 => x"81", + 4598 => x"91", + 4599 => x"83", + 4600 => x"80", + 4601 => x"87", + 4602 => x"81", + 4603 => x"fd", + 4604 => x"f8", + 4605 => x"2e", + 4606 => x"80", + 4607 => x"ff", + 4608 => x"ca", + 4609 => x"a0", + 4610 => x"38", + 4611 => x"74", + 4612 => x"86", + 4613 => x"fd", + 4614 => x"81", + 4615 => x"80", + 4616 => x"83", + 4617 => x"39", + 4618 => x"08", + 4619 => x"92", + 4620 => x"b8", + 4621 => x"59", + 4622 => x"27", + 4623 => x"86", + 4624 => x"55", + 4625 => x"09", + 4626 => x"38", + 4627 => x"f5", + 4628 => x"38", + 4629 => x"55", + 4630 => x"86", + 4631 => x"80", + 4632 => x"7a", + 4633 => x"b9", + 4634 => x"91", + 4635 => x"7a", + 4636 => x"8a", + 4637 => x"52", + 4638 => x"ff", + 4639 => x"79", + 4640 => x"7b", + 4641 => x"06", + 4642 => x"51", + 4643 => x"3f", + 4644 => x"1c", + 4645 => x"32", + 4646 => x"96", + 4647 => x"06", + 4648 => x"91", + 4649 => x"a1", + 4650 => x"55", + 4651 => x"ff", + 4652 => x"74", + 4653 => x"06", + 4654 => x"51", + 4655 => x"3f", + 4656 => x"52", + 4657 => x"ff", + 4658 => x"f8", + 4659 => x"34", + 4660 => x"1b", + 4661 => x"d9", + 4662 => x"52", + 4663 => x"ff", + 4664 => x"60", + 4665 => x"51", + 4666 => x"3f", + 4667 => x"09", + 4668 => x"cb", + 4669 => x"b2", + 4670 => x"c3", + 4671 => x"a0", + 4672 => x"52", + 4673 => x"ff", + 4674 => x"82", + 4675 => x"51", + 4676 => x"3f", + 4677 => x"1b", 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x"7e", + 4737 => x"d8", + 4738 => x"80", + 4739 => x"ff", + 4740 => x"7f", + 4741 => x"7d", + 4742 => x"81", + 4743 => x"f8", + 4744 => x"ff", + 4745 => x"ff", + 4746 => x"51", + 4747 => x"3f", + 4748 => x"88", + 4749 => x"39", + 4750 => x"f8", + 4751 => x"2e", + 4752 => x"55", + 4753 => x"51", + 4754 => x"3f", + 4755 => x"57", + 4756 => x"83", + 4757 => x"76", + 4758 => x"7a", + 4759 => x"ff", + 4760 => x"91", + 4761 => x"82", + 4762 => x"80", + 4763 => x"88", + 4764 => x"51", + 4765 => x"3f", + 4766 => x"78", + 4767 => x"74", + 4768 => x"18", + 4769 => x"2e", + 4770 => x"79", + 4771 => x"2e", + 4772 => x"55", + 4773 => x"62", + 4774 => x"74", + 4775 => x"75", + 4776 => x"7e", + 4777 => x"b8", + 4778 => x"88", + 4779 => x"38", + 4780 => x"78", + 4781 => x"74", + 4782 => x"56", + 4783 => x"93", + 4784 => x"66", + 4785 => x"26", + 4786 => x"56", + 4787 => x"83", + 4788 => x"64", + 4789 => x"77", + 4790 => x"84", + 4791 => x"52", + 4792 => x"9d", + 4793 => x"d4", + 4794 => x"51", + 4795 => x"3f", + 4796 => x"55", + 4797 => x"81", + 4798 => x"34", + 4799 => x"16", + 4800 => x"16", + 4801 => x"16", + 4802 => x"05", + 4803 => x"c1", + 4804 => x"fe", + 4805 => x"fe", + 4806 => x"34", + 4807 => x"08", + 4808 => x"07", + 4809 => x"16", + 4810 => x"88", + 4811 => x"34", + 4812 => x"c6", + 4813 => x"9c", + 4814 => x"52", + 4815 => x"51", + 4816 => x"3f", + 4817 => x"53", + 4818 => x"51", + 4819 => x"3f", + 4820 => x"ca", + 4821 => x"38", + 4822 => x"52", + 4823 => x"99", + 4824 => x"56", + 4825 => x"08", + 4826 => x"39", + 4827 => x"39", + 4828 => x"39", + 4829 => x"08", + 4830 => x"ca", + 4831 => x"3d", + 4832 => x"3d", + 4833 => x"71", + 4834 => x"8e", + 4835 => x"29", + 4836 => x"05", + 4837 => x"04", + 4838 => x"51", + 4839 => x"91", + 4840 => x"80", + 4841 => x"bb", + 4842 => x"f2", + 4843 => x"8c", + 4844 => x"39", + 4845 => x"51", + 4846 => x"91", + 4847 => x"80", + 4848 => x"bc", + 4849 => x"d6", + 4850 => x"d0", + 4851 => x"39", + 4852 => x"51", + 4853 => x"91", + 4854 => x"80", + 4855 => x"bd", + 4856 => x"39", + 4857 => x"51", + 4858 => x"bd", + 4859 => x"39", + 4860 => x"51", + 4861 => x"be", + 4862 => x"39", + 4863 => x"51", + 4864 => x"be", + 4865 => x"39", + 4866 => x"51", + 4867 => x"be", + 4868 => x"39", + 4869 => x"51", + 4870 => x"bf", + 4871 => x"87", + 4872 => x"3d", + 4873 => x"3d", + 4874 => x"56", + 4875 => x"e7", + 4876 => x"74", + 4877 => x"e8", + 4878 => x"39", + 4879 => x"74", + 4880 => x"a3", + 4881 => x"88", + 4882 => x"51", + 4883 => x"3f", + 4884 => x"08", + 4885 => x"75", + 4886 => x"a0", + 4887 => x"a0", + 4888 => x"0d", + 4889 => x"0d", + 4890 => x"02", + 4891 => x"c7", + 4892 => x"73", + 4893 => x"5d", + 4894 => x"5c", + 4895 => x"91", + 4896 => x"ff", + 4897 => x"91", + 4898 => x"ff", + 4899 => x"80", + 4900 => x"27", + 4901 => x"79", + 4902 => x"38", + 4903 => x"a7", + 4904 => x"39", + 4905 => x"72", + 4906 => x"38", + 4907 => x"91", + 4908 => x"ff", + 4909 => x"89", + 4910 => x"dc", + 4911 => x"dc", + 4912 => x"55", + 4913 => x"74", + 4914 => x"78", + 4915 => x"72", + 4916 => x"bf", + 4917 => x"8c", + 4918 => x"39", + 4919 => x"51", + 4920 => x"3f", + 4921 => x"a1", + 4922 => x"53", + 4923 => x"8e", + 4924 => x"52", + 4925 => x"51", + 4926 => x"3f", + 4927 => x"bf", + 4928 => x"86", + 4929 => x"15", + 4930 => x"fe", + 4931 => x"ff", + 4932 => x"bf", + 4933 => x"86", + 4934 => x"55", + 4935 => x"aa", + 4936 => x"70", + 4937 => x"26", + 4938 => x"9f", + 4939 => x"38", + 4940 => x"8b", + 4941 => x"fe", + 4942 => x"73", + 4943 => x"a0", + 4944 => x"d7", + 4945 => x"55", + 4946 => x"bf", + 4947 => x"85", + 4948 => x"16", + 4949 => x"56", + 4950 => x"3f", + 4951 => x"08", + 4952 => x"98", + 4953 => x"74", + 4954 => x"81", + 4955 => x"fe", + 4956 => x"91", + 4957 => x"98", + 4958 => x"2c", + 4959 => x"70", + 4960 => x"07", + 4961 => x"56", + 4962 => x"74", + 4963 => x"38", + 4964 => x"74", + 4965 => x"81", + 4966 => x"80", + 4967 => x"7a", + 4968 => x"76", + 4969 => x"38", + 4970 => x"91", + 4971 => x"8d", + 4972 => x"ec", + 4973 => x"02", + 4974 => x"e3", + 4975 => x"72", + 4976 => x"07", + 4977 => x"87", + 4978 => x"07", + 4979 => x"5a", + 4980 => x"57", + 4981 => x"38", + 4982 => x"52", + 4983 => x"52", + 4984 => x"3f", + 4985 => x"08", + 4986 => x"88", + 4987 => x"91", + 4988 => x"87", + 4989 => x"0c", + 4990 => x"08", + 4991 => x"d4", + 4992 => x"80", + 4993 => x"76", + 4994 => x"3f", + 4995 => x"08", + 4996 => x"88", + 4997 => x"7a", + 4998 => x"2e", + 4999 => x"19", + 5000 => x"59", + 5001 => x"3d", + 5002 => x"cc", + 5003 => x"30", + 5004 => x"80", + 5005 => x"79", + 5006 => x"38", + 5007 => x"90", + 5008 => x"f8", + 5009 => x"98", + 5010 => x"78", + 5011 => x"3f", + 5012 => x"91", + 5013 => x"96", + 5014 => x"f9", + 5015 => x"02", + 5016 => x"05", + 5017 => x"ff", + 5018 => x"7a", + 5019 => x"fe", + 5020 => x"ca", + 5021 => x"38", + 5022 => x"88", + 5023 => x"2e", + 5024 => x"39", + 5025 => x"54", + 5026 => x"53", + 5027 => x"51", + 5028 => x"ca", + 5029 => x"83", + 5030 => x"76", + 5031 => x"0c", + 5032 => x"04", + 5033 => x"02", + 5034 => x"91", + 5035 => x"91", + 5036 => x"55", + 5037 => x"3f", + 5038 => x"22", + 5039 => x"e2", + 5040 => x"94", + 5041 => x"a0", + 5042 => x"89", + 5043 => x"c0", + 5044 => x"88", + 5045 => x"80", + 5046 => x"fe", + 5047 => x"86", + 5048 => x"fe", + 5049 => x"c0", + 5050 => x"53", + 5051 => x"3f", + 5052 => x"f6", + 5053 => x"c0", + 5054 => x"f8", + 5055 => x"51", + 5056 => x"3f", + 5057 => x"70", + 5058 => x"52", + 5059 => x"95", + 5060 => x"fe", + 5061 => x"91", + 5062 => x"fe", + 5063 => x"80", + 5064 => x"dd", + 5065 => x"2a", + 5066 => x"51", + 5067 => x"2e", + 5068 => x"51", + 5069 => x"3f", + 5070 => x"51", + 5071 => x"3f", + 5072 => x"f5", + 5073 => x"83", + 5074 => x"06", + 5075 => x"80", + 5076 => x"81", + 5077 => x"a9", + 5078 => x"84", + 5079 => x"a1", + 5080 => x"fe", + 5081 => x"72", + 5082 => x"81", + 5083 => x"71", + 5084 => x"38", + 5085 => x"f5", + 5086 => x"c1", + 5087 => x"f7", + 5088 => x"51", + 5089 => x"3f", + 5090 => x"70", + 5091 => x"52", + 5092 => x"95", + 5093 => x"fe", + 5094 => x"91", + 5095 => x"fe", + 5096 => x"80", + 5097 => x"d9", + 5098 => x"2a", + 5099 => x"51", + 5100 => x"2e", + 5101 => x"51", + 5102 => x"3f", + 5103 => x"51", + 5104 => x"3f", + 5105 => x"f4", + 5106 => x"87", + 5107 => x"06", + 5108 => x"80", + 5109 => x"81", + 5110 => x"a5", + 5111 => x"d4", + 5112 => x"9d", + 5113 => x"fe", + 5114 => x"72", + 5115 => x"81", + 5116 => x"71", + 5117 => x"38", + 5118 => x"f4", + 5119 => x"c1", + 5120 => x"f5", + 5121 => x"51", + 5122 => x"3f", + 5123 => x"3f", + 5124 => x"04", + 5125 => x"78", + 5126 => x"55", + 5127 => x"80", + 5128 => x"38", + 5129 => x"77", + 5130 => x"33", + 5131 => x"39", + 5132 => x"80", + 5133 => x"81", + 5134 => x"57", + 5135 => x"2e", + 5136 => x"53", + 5137 => x"84", + 5138 => x"38", + 5139 => x"06", + 5140 => x"2e", + 5141 => x"88", + 5142 => x"70", + 5143 => x"34", + 5144 => x"90", + 5145 => x"a8", + 5146 => x"53", + 5147 => x"55", + 5148 => x"3f", + 5149 => x"08", + 5150 => x"15", + 5151 => x"81", + 5152 => x"38", + 5153 => x"81", + 5154 => x"53", + 5155 => x"d2", + 5156 => x"72", + 5157 => x"0c", + 5158 => x"04", + 5159 => x"80", + 5160 => x"e1", + 5161 => x"5c", + 5162 => x"51", + 5163 => x"3f", + 5164 => x"08", + 5165 => x"59", + 5166 => x"09", + 5167 => x"38", + 5168 => x"52", + 5169 => x"52", + 5170 => x"ca", + 5171 => x"78", + 5172 => x"b8", + 5173 => x"e3", + 5174 => x"88", + 5175 => x"88", + 5176 => x"ac", + 5177 => x"39", + 5178 => x"5c", + 5179 => x"51", + 5180 => x"3f", + 5181 => x"46", + 5182 => x"53", + 5183 => x"51", + 5184 => x"3f", + 5185 => x"64", + 5186 => x"ce", + 5187 => x"fe", + 5188 => x"fd", + 5189 => x"ca", + 5190 => x"2b", + 5191 => x"51", + 5192 => x"c2", + 5193 => x"38", + 5194 => x"24", + 5195 => x"78", + 5196 => x"ef", + 5197 => x"24", + 5198 => x"84", + 5199 => x"38", + 5200 => x"90", + 5201 => x"2e", + 5202 => x"78", + 5203 => x"a9", + 5204 => x"39", + 5205 => x"82", + 5206 => x"ab", + 5207 => x"38", + 5208 => x"78", + 5209 => x"f2", + 5210 => x"24", + 5211 => x"bc", + 5212 => x"38", + 5213 => x"84", + 5214 => x"c8", + 5215 => x"c0", + 5216 => x"38", + 5217 => x"2e", + 5218 => x"8e", + 5219 => x"80", + 5220 => x"a5", + 5221 => x"f8", + 5222 => x"78", + 5223 => x"8c", + 5224 => x"80", + 5225 => x"38", + 5226 => x"2e", + 5227 => x"78", + 5228 => x"8c", + 5229 => x"8c", + 5230 => x"d4", + 5231 => x"38", + 5232 => x"2e", + 5233 => x"8d", + 5234 => x"81", + 5235 => x"e0", + 5236 => x"83", + 5237 => x"78", + 5238 => x"8d", + 5239 => x"81", + 5240 => x"bd", + 5241 => x"39", + 5242 => x"2e", + 5243 => x"78", + 5244 => x"fd", + 5245 => x"cc", + 5246 => x"fe", + 5247 => x"fe", + 5248 => x"ff", + 5249 => x"91", + 5250 => x"88", + 5251 => x"e8", + 5252 => x"39", + 5253 => x"f0", + 5254 => x"f8", + 5255 => x"83", + 5256 => x"ca", + 5257 => x"2e", + 5258 => x"63", + 5259 => x"80", + 5260 => x"cb", + 5261 => x"02", + 5262 => x"33", + 5263 => x"b7", + 5264 => x"88", + 5265 => x"06", + 5266 => x"38", + 5267 => x"51", + 5268 => x"3f", + 5269 => x"94", + 5270 => x"88", + 5271 => x"39", + 5272 => x"f4", + 5273 => x"f8", + 5274 => x"83", + 5275 => x"ca", + 5276 => x"2e", + 5277 => x"80", + 5278 => x"02", + 5279 => x"33", + 5280 => x"c0", + 5281 => x"88", + 5282 => x"c3", + 5283 => x"8a", + 5284 => x"fe", + 5285 => x"fe", + 5286 => x"ff", + 5287 => x"91", + 5288 => x"80", + 5289 => x"63", + 5290 => x"c0", + 5291 => x"fe", + 5292 => x"fe", + 5293 => x"ff", + 5294 => x"91", + 5295 => x"86", + 5296 => x"88", + 5297 => x"53", + 5298 => x"52", + 5299 => x"80", + 5300 => x"80", + 5301 => x"53", + 5302 => x"84", + 5303 => x"cb", + 5304 => x"ff", + 5305 => x"91", + 5306 => x"81", + 5307 => x"c2", + 5308 => x"fa", + 5309 => x"5c", + 5310 => x"b7", + 5311 => x"05", + 5312 => x"ae", + 5313 => x"88", + 5314 => x"fe", + 5315 => x"5b", + 5316 => x"3f", + 5317 => x"ca", + 5318 => x"7a", + 5319 => x"3f", + 5320 => x"b7", + 5321 => x"05", + 5322 => x"86", + 5323 => x"88", + 5324 => x"fe", + 5325 => x"5b", + 5326 => x"3f", + 5327 => x"08", + 5328 => x"f8", + 5329 => x"fe", + 5330 => x"91", + 5331 => x"b8", + 5332 => x"05", + 5333 => x"ea", + 5334 => x"c6", + 5335 => x"ca", + 5336 => x"56", + 5337 => x"ca", + 5338 => x"ff", + 5339 => x"53", + 5340 => x"51", + 5341 => x"91", + 5342 => x"80", + 5343 => x"38", + 5344 => x"08", + 5345 => x"3f", + 5346 => x"b7", + 5347 => x"11", + 5348 => x"05", + 5349 => x"dd", + 5350 => x"88", + 5351 => x"fa", + 5352 => x"3d", + 5353 => x"53", + 5354 => x"51", + 5355 => x"3f", + 5356 => x"08", + 5357 => x"b4", + 5358 => x"fe", + 5359 => x"fe", + 5360 => x"ff", + 5361 => x"91", + 5362 => x"86", + 5363 => x"88", + 5364 => x"c3", + 5365 => x"f8", + 5366 => x"63", + 5367 => x"7b", + 5368 => x"38", + 5369 => x"7a", + 5370 => x"5c", + 5371 => x"26", + 5372 => x"e1", + 5373 => x"fe", + 5374 => x"fe", + 5375 => x"fe", + 5376 => x"91", + 5377 => x"80", + 5378 => x"38", + 5379 => x"f0", + 5380 => x"f8", + 5381 => x"ff", + 5382 => x"ca", + 5383 => x"2e", + 5384 => x"b7", + 5385 => x"11", + 5386 => x"05", + 5387 => x"c5", + 5388 => x"88", + 5389 => x"f9", + 5390 => x"c3", + 5391 => x"f7", + 5392 => x"5a", + 5393 => x"81", + 5394 => x"59", + 5395 => x"05", + 5396 => x"34", + 5397 => x"42", + 5398 => x"3d", + 5399 => x"53", + 5400 => x"51", + 5401 => x"3f", + 5402 => x"08", + 5403 => x"fc", + 5404 => x"fe", + 5405 => x"fe", + 5406 => x"fe", + 5407 => x"91", + 5408 => x"80", + 5409 => x"38", + 5410 => x"ec", + 5411 => x"f8", + 5412 => x"fe", + 5413 => x"ca", + 5414 => x"2e", + 5415 => x"91", + 5416 => x"fe", + 5417 => x"63", + 5418 => x"27", + 5419 => x"70", + 5420 => x"41", + 5421 => x"7f", + 5422 => x"78", + 5423 => x"79", + 5424 => x"52", + 5425 => x"51", + 5426 => x"3f", + 5427 => x"81", + 5428 => x"d5", + 5429 => x"f4", + 5430 => x"39", + 5431 => x"f4", + 5432 => x"f8", + 5433 => x"fe", + 5434 => x"ca", + 5435 => x"c4", + 5436 => x"91", + 5437 => x"80", + 5438 => x"91", + 5439 => x"44", + 5440 => x"c7", + 5441 => x"78", + 5442 => x"38", + 5443 => x"08", + 5444 => x"91", + 5445 => x"59", + 5446 => x"91", + 5447 => x"59", + 5448 => x"88", + 5449 => x"f4", + 5450 => x"39", + 5451 => x"08", + 5452 => x"44", + 5453 => x"f0", + 5454 => x"f8", + 5455 => x"fd", + 5456 => x"ca", + 5457 => x"c3", + 5458 => x"91", + 5459 => x"80", + 5460 => x"91", + 5461 => x"43", + 5462 => x"c7", + 5463 => x"78", + 5464 => x"38", + 5465 => x"08", + 5466 => x"91", + 5467 => x"59", + 5468 => x"91", + 5469 => x"59", + 5470 => x"88", + 5471 => x"f8", + 5472 => x"39", + 5473 => x"08", + 5474 => x"b7", + 5475 => x"11", + 5476 => x"05", + 5477 => x"dd", + 5478 => x"88", + 5479 => x"9b", + 5480 => x"5b", + 5481 => x"2e", + 5482 => x"59", + 5483 => x"8d", + 5484 => x"2e", + 5485 => x"a0", + 5486 => x"88", + 5487 => x"f0", + 5488 => x"d8", + 5489 => x"63", + 5490 => x"62", + 5491 => x"ed", + 5492 => x"c4", + 5493 => x"bd", + 5494 => x"fe", + 5495 => x"fe", + 5496 => x"fe", + 5497 => x"91", + 5498 => x"80", + 5499 => x"38", + 5500 => x"f0", + 5501 => x"f8", + 5502 => x"fb", + 5503 => x"ca", + 5504 => x"2e", + 5505 => x"59", + 5506 => x"05", + 5507 => x"63", + 5508 => x"b7", + 5509 => x"11", + 5510 => x"05", + 5511 => x"d5", + 5512 => x"88", + 5513 => x"f5", + 5514 => x"70", + 5515 => x"91", + 5516 => x"fe", + 5517 => x"80", + 5518 => x"51", + 5519 => x"3f", + 5520 => x"33", + 5521 => x"2e", + 5522 => x"9f", + 5523 => x"38", + 5524 => x"f0", + 5525 => x"f8", + 5526 => x"fb", + 5527 => x"ca", + 5528 => x"2e", + 5529 => x"59", + 5530 => x"05", + 5531 => x"63", + 5532 => x"ff", + 5533 => x"c4", + 5534 => x"f3", + 5535 => x"aa", + 5536 => x"fe", + 5537 => x"fe", + 5538 => x"fe", + 5539 => x"91", + 5540 => x"80", + 5541 => x"38", + 5542 => x"e4", + 5543 => x"f8", + 5544 => x"fc", + 5545 => x"ca", + 5546 => x"2e", + 5547 => x"59", + 5548 => x"22", + 5549 => x"05", + 5550 => x"41", + 5551 => x"e4", + 5552 => x"f8", + 5553 => x"fc", + 5554 => x"ca", + 5555 => x"38", + 5556 => x"60", + 5557 => x"52", + 5558 => x"51", + 5559 => x"3f", + 5560 => x"79", + 5561 => x"f2", + 5562 => x"79", + 5563 => x"ae", + 5564 => x"38", + 5565 => x"87", + 5566 => x"05", + 5567 => x"b7", + 5568 => x"11", + 5569 => x"05", + 5570 => x"db", + 5571 => x"88", + 5572 => x"92", + 5573 => x"02", + 5574 => x"79", + 5575 => x"5b", + 5576 => x"ff", + 5577 => x"c4", + 5578 => x"f1", + 5579 => x"a3", + 5580 => x"fe", + 5581 => x"fe", + 5582 => x"fe", + 5583 => x"91", + 5584 => x"80", + 5585 => x"38", + 5586 => x"e4", + 5587 => x"f8", + 5588 => x"fb", + 5589 => x"ca", + 5590 => x"2e", + 5591 => x"60", + 5592 => x"60", + 5593 => x"b7", + 5594 => x"11", + 5595 => x"05", + 5596 => x"f3", + 5597 => x"88", + 5598 => x"f2", + 5599 => x"70", + 5600 => x"91", + 5601 => x"fe", + 5602 => x"80", + 5603 => x"51", + 5604 => x"3f", + 5605 => x"33", + 5606 => x"2e", + 5607 => x"9f", + 5608 => x"38", + 5609 => x"e4", + 5610 => x"f8", + 5611 => x"fa", + 5612 => x"ca", + 5613 => x"2e", + 5614 => x"53", + 5615 => x"c4", + 5616 => x"f6", + 5617 => x"60", + 5618 => x"60", + 5619 => x"ff", + 5620 => x"c4", + 5621 => x"f0", + 5622 => x"a2", + 5623 => x"b8", + 5624 => x"b8", + 5625 => x"fe", + 5626 => x"f1", + 5627 => x"c4", + 5628 => x"f0", + 5629 => x"51", + 5630 => x"3f", + 5631 => x"84", + 5632 => x"87", + 5633 => x"0c", + 5634 => x"0b", + 5635 => x"94", + 5636 => x"e8", + 5637 => x"84", + 5638 => x"39", + 5639 => x"51", + 5640 => x"3f", + 5641 => x"0b", + 5642 => x"84", + 5643 => x"83", + 5644 => x"94", + 5645 => x"b4", + 5646 => x"fe", + 5647 => x"fe", + 5648 => x"fe", + 5649 => x"91", + 5650 => x"80", + 5651 => x"38", + 5652 => x"c5", + 5653 => x"f5", + 5654 => x"59", + 5655 => x"3d", + 5656 => x"53", + 5657 => x"51", + 5658 => x"3f", + 5659 => x"08", + 5660 => x"f8", + 5661 => x"91", + 5662 => x"fe", + 5663 => x"63", + 5664 => x"91", + 5665 => x"5e", + 5666 => x"08", + 5667 => x"dc", + 5668 => x"88", + 5669 => x"c5", + 5670 => x"f4", + 5671 => x"cc", + 5672 => x"e4", + 5673 => x"f4", + 5674 => x"d4", + 5675 => x"39", + 5676 => x"51", + 5677 => x"3f", + 5678 => x"a0", + 5679 => x"b0", + 5680 => x"39", + 5681 => x"51", + 5682 => x"2e", + 5683 => x"7b", + 5684 => x"d2", + 5685 => x"2e", + 5686 => x"b7", + 5687 => x"05", + 5688 => x"ce", + 5689 => x"94", + 5690 => x"88", + 5691 => x"c6", + 5692 => x"53", + 5693 => x"52", + 5694 => x"52", + 5695 => x"96", + 5696 => x"e4", + 5697 => x"bc", + 5698 => x"64", + 5699 => x"81", + 5700 => x"54", + 5701 => x"53", + 5702 => x"52", + 5703 => x"bb", + 5704 => x"88", + 5705 => x"81", + 5706 => x"32", + 5707 => x"8a", + 5708 => x"2e", + 5709 => x"ef", + 5710 => x"c6", + 5711 => x"f3", + 5712 => x"a8", + 5713 => x"0d", + 5714 => x"ca", + 5715 => x"94", + 5716 => x"ca", + 5717 => x"97", + 5718 => x"ca", + 5719 => x"e5", + 5720 => x"ec", + 5721 => x"c6", + 5722 => x"e3", + 5723 => x"c6", + 5724 => x"ed", + 5725 => x"9d", + 5726 => x"eb", + 5727 => x"51", + 5728 => x"ee", + 5729 => x"04", + 5730 => x"3e", + 5731 => x"44", + 5732 => x"4a", + 5733 => x"50", + 5734 => x"56", + 5735 => x"14", + 5736 => x"98", + 5737 => x"9f", + 5738 => x"a6", + 5739 => x"ad", + 5740 => x"b4", + 5741 => x"bb", + 5742 => x"c2", + 5743 => x"c9", + 5744 => x"d0", + 5745 => x"d7", + 5746 => x"de", + 5747 => x"e4", + 5748 => x"ea", + 5749 => x"f0", + 5750 => x"f6", + 5751 => x"fc", + 5752 => x"02", + 5753 => x"08", + 5754 => x"0e", + 5755 => x"25", + 5756 => x"64", + 5757 => x"3a", + 5758 => x"25", + 5759 => x"64", + 5760 => x"00", + 5761 => x"20", + 5762 => x"66", + 5763 => x"72", + 5764 => x"6f", + 5765 => x"00", + 5766 => x"72", + 5767 => x"53", + 5768 => x"63", + 5769 => x"69", + 5770 => x"00", + 5771 => x"65", + 5772 => x"65", + 5773 => x"6d", + 5774 => x"6d", + 5775 => x"65", + 5776 => x"00", + 5777 => x"20", + 5778 => x"4e", + 5779 => x"41", + 5780 => x"53", + 5781 => x"74", + 5782 => x"38", + 5783 => x"53", + 5784 => x"3d", + 5785 => x"58", + 5786 => x"00", + 5787 => x"20", + 5788 => x"4d", + 5789 => x"74", + 5790 => x"3d", + 5791 => x"58", + 5792 => x"69", + 5793 => x"25", + 5794 => x"29", + 5795 => x"00", + 5796 => x"20", + 5797 => x"20", + 5798 => x"61", + 5799 => x"25", + 5800 => x"2c", + 5801 => x"7a", + 5802 => x"30", + 5803 => x"2e", + 5804 => x"00", + 5805 => x"20", + 5806 => x"54", + 5807 => x"00", + 5808 => x"20", + 5809 => x"0a", + 5810 => x"00", + 5811 => x"20", + 5812 => x"0a", + 5813 => x"00", + 5814 => x"20", + 5815 => x"43", + 5816 => x"20", + 5817 => x"76", + 5818 => x"73", + 5819 => x"32", + 5820 => x"0a", + 5821 => x"00", + 5822 => x"20", + 5823 => x"45", + 5824 => x"50", + 5825 => x"4f", + 5826 => x"4f", + 5827 => x"52", + 5828 => x"00", + 5829 => x"20", + 5830 => x"45", + 5831 => x"28", + 5832 => x"65", + 5833 => x"25", + 5834 => x"29", + 5835 => x"00", + 5836 => x"72", + 5837 => x"65", + 5838 => x"00", + 5839 => x"20", + 5840 => x"20", + 5841 => x"65", + 5842 => x"65", + 5843 => x"72", + 5844 => x"64", + 5845 => x"73", + 5846 => x"25", + 5847 => x"0a", + 5848 => x"00", + 5849 => x"20", + 5850 => x"20", + 5851 => x"6f", + 5852 => x"53", + 5853 => x"74", + 5854 => x"64", + 5855 => x"73", + 5856 => x"25", + 5857 => x"0a", + 5858 => x"00", + 5859 => x"20", + 5860 => x"63", + 5861 => x"74", + 5862 => x"20", + 5863 => x"72", + 5864 => x"20", + 5865 => x"20", + 5866 => x"25", + 5867 => x"0a", + 5868 => x"00", + 5869 => x"20", + 5870 => x"20", + 5871 => x"20", + 5872 => x"20", + 5873 => x"20", + 5874 => x"20", + 5875 => x"20", + 5876 => x"25", + 5877 => x"0a", + 5878 => x"00", + 5879 => x"20", + 5880 => x"74", + 5881 => x"43", + 5882 => x"6b", + 5883 => x"65", + 5884 => x"20", + 5885 => x"20", + 5886 => x"25", + 5887 => x"0a", + 5888 => x"00", + 5889 => x"6c", + 5890 => x"00", + 5891 => x"69", + 5892 => x"00", + 5893 => x"78", + 5894 => x"00", + 5895 => x"00", + 5896 => x"6d", + 5897 => x"00", + 5898 => x"6e", + 5899 => x"00", + 5900 => x"00", + 5901 => x"2c", + 5902 => x"3d", + 5903 => x"5d", + 5904 => x"00", + 5905 => x"00", + 5906 => x"33", + 5907 => x"00", + 5908 => x"4d", + 5909 => x"53", + 5910 => x"00", + 5911 => x"4e", + 5912 => x"20", + 5913 => x"46", + 5914 => x"32", + 5915 => x"00", + 5916 => x"4e", + 5917 => x"20", + 5918 => x"46", + 5919 => x"20", + 5920 => x"00", + 5921 => x"30", + 5922 => x"00", + 5923 => x"00", + 5924 => x"00", + 5925 => x"41", + 5926 => x"80", + 5927 => x"49", + 5928 => x"8f", + 5929 => x"4f", + 5930 => x"55", + 5931 => x"9b", + 5932 => x"9f", + 5933 => x"55", + 5934 => x"a7", + 5935 => x"ab", + 5936 => x"af", + 5937 => x"b3", + 5938 => x"b7", + 5939 => x"bb", + 5940 => x"bf", + 5941 => x"c3", + 5942 => x"c7", + 5943 => x"cb", + 5944 => x"cf", + 5945 => x"d3", + 5946 => x"d7", + 5947 => x"db", + 5948 => x"df", + 5949 => x"e3", + 5950 => x"e7", + 5951 => x"eb", + 5952 => x"ef", + 5953 => x"f3", + 5954 => x"f7", + 5955 => x"fb", + 5956 => x"ff", + 5957 => x"3b", + 5958 => x"2f", + 5959 => x"3a", + 5960 => x"7c", + 5961 => x"00", + 5962 => x"04", + 5963 => x"40", + 5964 => x"00", + 5965 => x"00", + 5966 => x"02", + 5967 => x"08", + 5968 => x"20", + 5969 => x"00", + 5970 => x"69", + 5971 => x"00", + 5972 => x"63", + 5973 => x"00", + 5974 => x"69", + 5975 => x"00", + 5976 => x"61", + 5977 => x"00", + 5978 => x"65", + 5979 => x"00", + 5980 => x"65", + 5981 => x"00", + 5982 => x"70", + 5983 => x"00", + 5984 => x"66", + 5985 => x"00", + 5986 => x"6d", + 5987 => x"00", + 5988 => x"00", + 5989 => x"00", + 5990 => x"00", + 5991 => x"00", + 5992 => x"00", + 5993 => x"00", + 5994 => x"00", + 5995 => x"6c", + 5996 => x"00", + 5997 => x"00", + 5998 => x"74", + 5999 => x"00", + 6000 => x"65", + 6001 => x"00", + 6002 => x"6f", + 6003 => x"00", + 6004 => x"74", + 6005 => x"00", + 6006 => x"6b", + 6007 => x"72", + 6008 => x"00", + 6009 => x"65", + 6010 => x"6c", + 6011 => x"72", + 6012 => x"0a", + 6013 => x"00", + 6014 => x"6b", + 6015 => x"74", + 6016 => x"61", + 6017 => x"0a", + 6018 => x"00", + 6019 => x"66", + 6020 => x"20", + 6021 => x"6e", + 6022 => x"00", + 6023 => x"70", + 6024 => x"20", + 6025 => x"6e", + 6026 => x"00", + 6027 => x"61", + 6028 => x"20", + 6029 => x"65", + 6030 => x"65", + 6031 => x"00", + 6032 => x"65", + 6033 => x"64", + 6034 => x"65", + 6035 => x"00", + 6036 => x"65", + 6037 => x"72", + 6038 => x"79", + 6039 => x"69", + 6040 => x"2e", + 6041 => x"00", + 6042 => x"65", + 6043 => x"6e", + 6044 => x"20", + 6045 => x"61", + 6046 => x"2e", + 6047 => x"00", + 6048 => x"69", + 6049 => x"72", + 6050 => x"20", + 6051 => x"74", + 6052 => x"65", + 6053 => x"00", + 6054 => x"76", + 6055 => x"75", + 6056 => x"72", + 6057 => x"20", + 6058 => x"61", + 6059 => x"2e", + 6060 => x"00", + 6061 => x"6b", + 6062 => x"74", + 6063 => x"61", + 6064 => x"64", + 6065 => x"00", + 6066 => x"63", + 6067 => x"61", + 6068 => x"6c", + 6069 => x"69", + 6070 => x"79", + 6071 => x"6d", + 6072 => x"75", + 6073 => x"6f", + 6074 => x"69", + 6075 => x"0a", + 6076 => x"00", + 6077 => x"6d", + 6078 => x"61", + 6079 => x"74", + 6080 => x"0a", + 6081 => x"00", + 6082 => x"65", + 6083 => x"2c", + 6084 => x"65", + 6085 => x"69", + 6086 => x"63", + 6087 => x"65", + 6088 => x"64", + 6089 => x"00", + 6090 => x"65", + 6091 => x"20", + 6092 => x"6b", + 6093 => x"0a", + 6094 => x"00", + 6095 => x"75", + 6096 => x"63", + 6097 => x"74", + 6098 => x"6d", + 6099 => x"2e", + 6100 => x"00", + 6101 => x"20", + 6102 => x"79", + 6103 => x"65", + 6104 => x"69", + 6105 => x"2e", + 6106 => x"00", + 6107 => x"61", + 6108 => x"65", + 6109 => x"69", + 6110 => x"72", + 6111 => x"74", + 6112 => x"00", + 6113 => x"63", + 6114 => x"2e", + 6115 => x"00", + 6116 => x"6e", + 6117 => x"20", + 6118 => x"6f", + 6119 => x"00", + 6120 => x"75", + 6121 => x"74", + 6122 => x"25", + 6123 => x"74", + 6124 => x"75", + 6125 => x"74", + 6126 => x"73", + 6127 => x"0a", + 6128 => x"00", + 6129 => x"58", + 6130 => x"00", + 6131 => x"00", + 6132 => x"58", + 6133 => x"00", + 6134 => x"20", + 6135 => x"20", + 6136 => x"00", + 6137 => x"58", + 6138 => x"00", + 6139 => x"00", + 6140 => x"00", + 6141 => x"00", + 6142 => x"64", + 6143 => x"00", + 6144 => x"54", + 6145 => x"00", + 6146 => x"20", + 6147 => x"28", + 6148 => x"00", + 6149 => x"30", + 6150 => x"30", + 6151 => x"00", + 6152 => x"33", + 6153 => x"00", + 6154 => x"55", + 6155 => x"65", + 6156 => x"30", + 6157 => x"20", + 6158 => x"25", + 6159 => x"2a", + 6160 => x"00", + 6161 => x"54", + 6162 => x"6e", + 6163 => x"72", + 6164 => x"20", + 6165 => x"64", + 6166 => x"0a", + 6167 => x"00", + 6168 => x"65", + 6169 => x"6e", + 6170 => x"72", + 6171 => x"0a", + 6172 => x"00", + 6173 => x"20", + 6174 => x"65", + 6175 => x"70", + 6176 => x"00", + 6177 => x"54", + 6178 => x"44", + 6179 => x"74", + 6180 => x"75", + 6181 => x"00", + 6182 => x"54", + 6183 => x"52", + 6184 => x"74", + 6185 => x"75", + 6186 => x"00", + 6187 => x"54", + 6188 => x"58", + 6189 => x"74", + 6190 => x"75", + 6191 => x"00", + 6192 => x"54", + 6193 => x"58", + 6194 => x"74", + 6195 => x"75", + 6196 => x"00", + 6197 => x"54", + 6198 => x"58", + 6199 => x"74", + 6200 => x"75", + 6201 => x"00", + 6202 => x"54", + 6203 => x"58", + 6204 => x"74", + 6205 => x"75", + 6206 => x"00", + 6207 => x"74", + 6208 => x"20", + 6209 => x"74", + 6210 => x"72", + 6211 => x"0a", + 6212 => x"00", + 6213 => x"62", + 6214 => x"67", + 6215 => x"6d", + 6216 => x"2e", + 6217 => x"00", + 6218 => x"00", + 6219 => x"6c", + 6220 => x"74", + 6221 => x"6e", + 6222 => x"61", + 6223 => x"65", + 6224 => x"20", + 6225 => x"64", + 6226 => x"20", + 6227 => x"61", + 6228 => x"69", + 6229 => x"20", + 6230 => x"75", + 6231 => x"79", + 6232 => x"00", + 6233 => x"00", + 6234 => x"20", + 6235 => x"6b", + 6236 => x"21", + 6237 => x"00", + 6238 => x"74", + 6239 => x"69", + 6240 => x"2e", + 6241 => x"00", + 6242 => x"6c", + 6243 => x"74", + 6244 => x"6e", + 6245 => x"61", + 6246 => x"65", + 6247 => x"00", + 6248 => x"25", + 6249 => x"00", + 6250 => x"00", + 6251 => x"61", + 6252 => x"67", + 6253 => x"00", + 6254 => x"79", + 6255 => x"2e", + 6256 => x"00", + 6257 => x"70", + 6258 => x"6e", + 6259 => x"2e", + 6260 => x"00", + 6261 => x"6c", + 6262 => x"30", + 6263 => x"2d", + 6264 => x"38", + 6265 => x"25", + 6266 => x"29", + 6267 => x"00", + 6268 => x"70", + 6269 => x"6d", + 6270 => x"0a", + 6271 => x"00", + 6272 => x"6d", + 6273 => x"74", + 6274 => x"00", + 6275 => x"58", + 6276 => x"32", + 6277 => x"00", + 6278 => x"0a", + 6279 => x"00", + 6280 => x"58", + 6281 => x"34", + 6282 => x"00", + 6283 => x"58", + 6284 => x"38", + 6285 => x"00", + 6286 => x"61", + 6287 => x"6e", + 6288 => x"6e", + 6289 => x"72", + 6290 => x"73", + 6291 => x"00", + 6292 => x"62", + 6293 => x"67", + 6294 => x"74", + 6295 => x"75", + 6296 => x"0a", + 6297 => x"00", + 6298 => x"61", + 6299 => x"64", + 6300 => x"72", + 6301 => x"69", + 6302 => x"00", + 6303 => x"62", + 6304 => x"67", + 6305 => x"72", + 6306 => x"69", + 6307 => x"00", + 6308 => x"63", + 6309 => x"6e", + 6310 => x"6f", + 6311 => x"40", + 6312 => x"38", + 6313 => x"2e", + 6314 => x"00", + 6315 => x"6c", + 6316 => x"20", + 6317 => x"65", + 6318 => x"25", + 6319 => x"20", + 6320 => x"0a", + 6321 => x"00", + 6322 => x"6c", + 6323 => x"74", + 6324 => x"65", + 6325 => x"6f", + 6326 => x"28", + 6327 => x"2e", + 6328 => x"00", + 6329 => x"74", + 6330 => x"69", + 6331 => x"61", + 6332 => x"69", + 6333 => x"69", + 6334 => x"2e", + 6335 => x"00", + 6336 => x"64", + 6337 => x"62", + 6338 => x"69", + 6339 => x"2e", + 6340 => x"00", + 6341 => x"00", + 6342 => x"00", + 6343 => x"5c", + 6344 => x"25", + 6345 => x"73", + 6346 => x"00", + 6347 => x"20", + 6348 => x"6d", + 6349 => x"2e", + 6350 => x"00", + 6351 => x"6e", + 6352 => x"2e", + 6353 => x"00", + 6354 => x"62", + 6355 => x"67", + 6356 => x"74", + 6357 => x"75", + 6358 => x"2e", + 6359 => x"00", + 6360 => x"00", + 6361 => x"00", + 6362 => x"ff", + 6363 => x"00", + 6364 => x"ff", + 6365 => x"00", + 6366 => x"ff", + 6367 => x"00", + 6368 => x"00", + 6369 => x"00", + 6370 => x"00", + 6371 => x"00", + 6372 => x"01", + 6373 => x"01", + 6374 => x"01", + 6375 => x"00", + 6376 => x"00", + 6377 => x"00", + 6378 => x"48", + 6379 => x"00", + 6380 => x"00", + 6381 => x"00", + 6382 => x"50", + 6383 => x"00", + 6384 => x"00", + 6385 => x"00", + 6386 => x"58", + 6387 => x"00", + 6388 => x"00", + 6389 => x"00", + 6390 => x"60", + 6391 => x"00", + 6392 => x"00", + 6393 => x"00", + 6394 => x"68", + 6395 => x"00", + 6396 => x"00", + 6397 => x"00", + 6398 => x"70", + 6399 => x"00", + 6400 => x"00", + 6401 => x"00", + 6402 => x"78", + 6403 => x"00", + 6404 => x"00", + 6405 => x"00", + 6406 => x"80", + 6407 => x"00", + 6408 => x"00", + 6409 => x"00", + 6410 => x"88", + 6411 => x"00", + 6412 => x"00", + 6413 => x"00", + 6414 => x"90", + 6415 => x"00", + 6416 => x"00", + 6417 => x"00", + 6418 => x"94", + 6419 => x"00", + 6420 => x"00", + 6421 => x"00", + 6422 => x"98", + 6423 => x"00", + 6424 => x"00", + 6425 => x"00", + 6426 => x"9c", + 6427 => x"00", + 6428 => x"00", + 6429 => x"00", + 6430 => x"a0", + 6431 => x"00", + 6432 => x"00", + 6433 => x"00", + 6434 => x"a4", + 6435 => x"00", + 6436 => x"00", + 6437 => x"00", + 6438 => x"a8", + 6439 => x"00", + 6440 => x"00", + 6441 => x"00", + 6442 => x"ac", + 6443 => x"00", + 6444 => x"00", + 6445 => x"00", + 6446 => x"b4", + 6447 => x"00", + 6448 => x"00", + 6449 => x"00", + 6450 => x"b8", + 6451 => x"00", + 6452 => x"00", + 6453 => x"00", + 6454 => x"c0", + 6455 => x"00", + 6456 => x"00", + 6457 => x"00", + 6458 => x"c8", + 6459 => x"00", + 6460 => x"00", + 6461 => x"00", + 6462 => x"d0", + 6463 => x"00", + 6464 => x"00", + 6465 => x"00", + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + 0 => x"90", + 1 => x"0b", + 2 => x"c6", + 3 => x"ff", + 4 => x"ff", + 5 => x"ff", + 6 => x"ff", + 7 => x"ff", + 8 => x"90", + 9 => x"0b", + 10 => x"85", + 11 => x"90", + 12 => x"0b", + 13 => x"a7", + 14 => x"90", + 15 => x"0b", + 16 => x"c9", + 17 => x"90", + 18 => x"0b", + 19 => x"eb", + 20 => x"90", + 21 => x"0b", + 22 => x"8d", + 23 => x"90", + 24 => x"0b", + 25 => x"af", + 26 => x"90", + 27 => x"0b", + 28 => x"d1", + 29 => x"90", + 30 => x"0b", + 31 => x"f3", + 32 => x"90", + 33 => x"0b", + 34 => x"95", + 35 => x"90", + 36 => x"0b", + 37 => x"b7", + 38 => x"90", + 39 => x"0b", + 40 => x"d9", + 41 => x"90", + 42 => x"0b", + 43 => x"fb", + 44 => x"90", + 45 => x"0b", + 46 => x"9d", + 47 => x"90", + 48 => x"0b", + 49 => x"bf", + 50 => x"90", + 51 => x"0b", + 52 => x"e1", + 53 => x"90", + 54 => x"0b", + 55 => x"83", + 56 => x"90", + 57 => x"0b", + 58 => x"a5", + 59 => x"90", + 60 => x"0b", + 61 => x"c7", + 62 => x"90", + 63 => x"0b", + 64 => x"e9", + 65 => x"90", + 66 => x"0b", + 67 => x"8b", + 68 => x"90", + 69 => x"0b", + 70 => x"ad", + 71 => x"90", + 72 => x"0b", + 73 => x"cf", + 74 => x"90", + 75 => x"0b", + 76 => x"f1", + 77 => x"90", + 78 => x"0b", + 79 => x"93", + 80 => x"90", + 81 => x"0b", + 82 => x"b5", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"00", + 89 => x"00", + 90 => x"00", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"00", + 97 => x"00", + 98 => x"00", + 99 => x"00", + 100 => x"00", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"00", + 105 => x"00", + 106 => x"00", + 107 => x"00", + 108 => x"00", + 109 => x"00", + 110 => x"00", + 111 => x"00", + 112 => x"00", + 113 => x"00", + 114 => x"00", + 115 => x"00", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"00", + 121 => x"00", + 122 => x"00", + 123 => x"00", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"84", + 129 => x"ca", + 130 => x"95", + 131 => x"ca", + 132 => x"c0", + 133 => x"91", + 134 => x"90", + 135 => x"91", + 136 => x"88", + 137 => x"04", + 138 => x"0c", + 139 => x"2d", + 140 => x"08", + 141 => x"90", + 142 => x"94", + 143 => x"9c", + 144 => x"94", + 145 => x"80", + 146 => x"ca", + 147 => x"a6", + 148 => x"ca", + 149 => x"c0", + 150 => x"91", + 151 => x"90", + 152 => x"91", + 153 => x"88", + 154 => x"04", + 155 => x"0c", + 156 => x"2d", + 157 => x"08", + 158 => x"90", + 159 => x"94", + 160 => x"f5", + 161 => x"94", + 162 => x"80", + 163 => x"ca", + 164 => x"a9", + 165 => x"ca", + 166 => x"c0", + 167 => x"91", + 168 => x"90", + 169 => x"91", + 170 => x"88", + 171 => x"04", + 172 => x"0c", + 173 => x"2d", + 174 => x"08", + 175 => x"90", + 176 => x"94", + 177 => x"ba", + 178 => x"94", + 179 => x"80", + 180 => x"ca", + 181 => x"97", + 182 => x"ca", + 183 => x"c0", + 184 => x"91", + 185 => x"90", + 186 => x"91", + 187 => x"88", + 188 => x"04", + 189 => x"0c", + 190 => x"2d", + 191 => x"08", + 192 => x"90", + 193 => x"94", + 194 => x"be", + 195 => x"94", + 196 => x"80", + 197 => x"ca", + 198 => x"92", + 199 => x"ca", + 200 => x"c0", + 201 => x"91", + 202 => x"90", + 203 => x"91", + 204 => x"88", + 205 => x"04", + 206 => x"0c", + 207 => x"2d", + 208 => x"08", + 209 => x"90", + 210 => x"94", + 211 => x"81", + 212 => x"94", + 213 => x"80", + 214 => x"ca", + 215 => x"e3", + 216 => x"ca", + 217 => x"c0", + 218 => x"91", + 219 => x"90", + 220 => x"91", + 221 => x"88", + 222 => x"04", + 223 => x"0c", + 224 => x"2d", + 225 => x"08", + 226 => x"90", + 227 => x"94", + 228 => x"ef", + 229 => x"94", + 230 => x"80", + 231 => x"ca", + 232 => x"f1", + 233 => x"ca", + 234 => x"c0", + 235 => x"91", + 236 => x"90", + 237 => x"91", + 238 => x"88", + 239 => x"04", + 240 => x"0c", + 241 => x"2d", + 242 => x"08", + 243 => x"90", + 244 => x"94", + 245 => x"e3", + 246 => x"94", + 247 => x"80", + 248 => x"ca", + 249 => x"f8", + 250 => x"ca", + 251 => x"c0", + 252 => x"91", + 253 => x"90", + 254 => x"91", + 255 => x"88", + 256 => x"04", + 257 => x"0c", + 258 => x"2d", + 259 => x"08", + 260 => x"90", + 261 => x"94", + 262 => x"b7", + 263 => x"94", + 264 => x"80", + 265 => x"ca", + 266 => x"81", + 267 => x"ca", + 268 => x"c0", + 269 => x"91", + 270 => x"90", + 271 => x"91", + 272 => x"88", + 273 => x"04", + 274 => x"0c", + 275 => x"2d", + 276 => x"08", + 277 => x"90", + 278 => x"94", + 279 => x"f1", + 280 => x"94", + 281 => x"80", + 282 => x"ca", + 283 => x"f4", + 284 => x"ca", + 285 => x"c0", + 286 => x"91", + 287 => x"91", + 288 => x"91", + 289 => x"88", + 290 => x"04", + 291 => x"0c", + 292 => x"2d", + 293 => x"08", + 294 => x"90", + 295 => x"94", + 296 => x"f5", + 297 => x"94", + 298 => x"80", + 299 => x"ca", + 300 => x"db", + 301 => x"ca", + 302 => x"c0", + 303 => x"91", + 304 => x"91", + 305 => x"91", + 306 => x"88", + 307 => x"04", + 308 => x"0c", + 309 => x"2d", + 310 => x"08", + 311 => x"90", + 312 => x"94", + 313 => x"e0", + 314 => x"94", + 315 => x"80", + 316 => x"ca", + 317 => x"b0", + 318 => x"ca", + 319 => x"c0", + 320 => x"91", + 321 => x"90", + 322 => x"91", + 323 => x"88", + 324 => x"04", + 325 => x"0c", + 326 => x"2d", + 327 => x"08", + 328 => x"90", + 329 => x"94", + 330 => x"81", + 331 => x"94", + 332 => x"80", + 333 => x"ca", + 334 => x"97", + 335 => x"ca", + 336 => x"c0", + 337 => x"91", + 338 => x"91", + 339 => x"8e", + 340 => x"70", + 341 => x"0c", + 342 => x"8a", + 343 => x"84", + 344 => x"b2", + 345 => x"04", + 346 => x"08", + 347 => x"94", + 348 => x"0d", + 349 => x"ca", + 350 => x"05", + 351 => x"ca", + 352 => x"05", + 353 => x"c5", + 354 => x"88", + 355 => x"ca", + 356 => x"85", + 357 => x"ca", + 358 => x"91", + 359 => x"02", + 360 => x"0c", + 361 => x"81", + 362 => x"94", + 363 => x"08", + 364 => x"94", + 365 => x"08", + 366 => x"91", + 367 => x"70", + 368 => x"0c", + 369 => x"0d", + 370 => x"0c", + 371 => x"94", + 372 => x"ca", + 373 => x"3d", + 374 => x"91", + 375 => x"fc", + 376 => x"0b", + 377 => x"08", + 378 => x"91", + 379 => x"8c", + 380 => x"ca", + 381 => x"05", + 382 => x"38", + 383 => x"08", + 384 => x"80", + 385 => x"80", + 386 => x"94", + 387 => x"08", + 388 => x"91", + 389 => x"8c", + 390 => x"91", + 391 => x"8c", + 392 => x"ca", + 393 => x"05", + 394 => x"ca", + 395 => x"05", + 396 => x"39", + 397 => x"08", + 398 => x"80", + 399 => x"38", + 400 => x"08", + 401 => x"91", + 402 => x"88", + 403 => x"ad", + 404 => x"94", + 405 => x"08", + 406 => x"08", + 407 => x"31", + 408 => x"08", + 409 => x"91", + 410 => x"f8", + 411 => x"ca", + 412 => x"05", + 413 => x"ca", + 414 => x"05", + 415 => x"94", + 416 => x"08", + 417 => x"ca", + 418 => x"05", + 419 => x"94", + 420 => x"08", + 421 => x"ca", + 422 => x"05", + 423 => x"39", + 424 => x"08", + 425 => x"80", + 426 => x"91", + 427 => x"88", + 428 => x"91", + 429 => x"f4", + 430 => x"91", + 431 => x"94", + 432 => x"08", + 433 => x"94", + 434 => x"0c", + 435 => x"94", + 436 => x"08", + 437 => x"0c", + 438 => x"91", + 439 => x"04", + 440 => x"76", + 441 => x"8c", + 442 => x"33", + 443 => x"55", + 444 => x"8a", + 445 => x"06", + 446 => x"2e", + 447 => x"12", + 448 => x"2e", + 449 => x"73", + 450 => x"55", + 451 => x"52", + 452 => x"09", + 453 => x"38", + 454 => x"88", + 455 => x"0d", + 456 => x"88", + 457 => x"70", + 458 => x"07", + 459 => x"8f", + 460 => x"38", + 461 => x"84", + 462 => x"72", + 463 => x"05", + 464 => x"71", + 465 => x"53", + 466 => x"70", + 467 => x"0c", + 468 => x"71", + 469 => x"38", + 470 => x"90", + 471 => x"70", + 472 => x"0c", + 473 => x"71", + 474 => x"38", + 475 => x"8e", + 476 => x"0d", + 477 => x"72", + 478 => x"53", + 479 => x"93", + 480 => x"73", + 481 => x"54", + 482 => x"2e", + 483 => x"73", + 484 => x"71", + 485 => x"ff", + 486 => x"70", + 487 => x"38", + 488 => x"70", + 489 => x"81", + 490 => x"81", + 491 => x"71", + 492 => x"ff", + 493 => x"54", + 494 => x"38", + 495 => x"73", + 496 => x"75", + 497 => x"71", + 498 => x"ca", + 499 => x"52", + 500 => x"04", + 501 => x"f7", + 502 => x"14", + 503 => x"84", + 504 => x"06", + 505 => x"70", + 506 => x"14", + 507 => x"08", + 508 => x"71", + 509 => x"dc", + 510 => x"54", + 511 => x"39", + 512 => x"ca", + 513 => x"3d", + 514 => x"3d", + 515 => x"83", + 516 => x"2b", + 517 => x"3f", + 518 => x"08", + 519 => x"72", + 520 => x"54", + 521 => x"25", + 522 => x"91", + 523 => x"84", + 524 => x"fb", + 525 => x"70", + 526 => x"53", + 527 => x"2e", + 528 => x"71", + 529 => x"a0", + 530 => x"06", + 531 => x"12", + 532 => x"71", + 533 => x"81", + 534 => x"73", + 535 => x"ff", + 536 => x"55", + 537 => x"83", + 538 => x"70", + 539 => x"38", + 540 => x"73", + 541 => x"51", + 542 => x"09", + 543 => x"38", + 544 => x"81", + 545 => x"72", + 546 => x"51", + 547 => x"88", + 548 => x"0d", + 549 => x"0d", + 550 => x"08", + 551 => x"38", + 552 => x"05", + 553 => x"98", + 554 => x"ca", + 555 => x"38", + 556 => x"39", + 557 => x"91", + 558 => x"86", + 559 => x"fc", + 560 => x"82", + 561 => x"05", + 562 => x"52", + 563 => x"81", + 564 => x"13", + 565 => x"51", + 566 => x"9e", + 567 => x"38", + 568 => x"51", + 569 => x"97", + 570 => x"38", + 571 => x"51", + 572 => x"bb", + 573 => x"38", + 574 => x"51", + 575 => x"bb", + 576 => x"38", + 577 => x"55", + 578 => x"87", + 579 => x"d9", + 580 => x"22", + 581 => x"73", + 582 => x"80", + 583 => x"0b", + 584 => x"9c", + 585 => x"87", + 586 => x"0c", + 587 => x"87", + 588 => x"0c", + 589 => x"87", + 590 => x"0c", + 591 => x"87", + 592 => x"0c", + 593 => x"87", + 594 => x"0c", + 595 => x"87", + 596 => x"0c", + 597 => x"98", + 598 => x"87", + 599 => x"0c", + 600 => x"c0", + 601 => x"80", + 602 => x"ca", + 603 => x"3d", + 604 => x"3d", + 605 => x"87", + 606 => x"5d", + 607 => x"87", + 608 => x"08", + 609 => x"23", + 610 => x"b8", + 611 => x"82", + 612 => x"c0", + 613 => x"5a", + 614 => x"34", + 615 => x"b0", + 616 => x"84", + 617 => x"c0", + 618 => x"5a", + 619 => x"34", + 620 => x"a8", + 621 => x"86", + 622 => x"c0", + 623 => x"5c", + 624 => x"23", + 625 => x"a0", + 626 => x"8a", + 627 => x"7d", + 628 => x"ff", + 629 => x"7b", + 630 => x"06", + 631 => x"33", + 632 => x"33", + 633 => x"33", + 634 => x"33", + 635 => x"33", + 636 => x"ff", + 637 => x"91", + 638 => x"92", + 639 => x"3d", + 640 => x"3d", + 641 => x"05", + 642 => x"70", + 643 => x"52", + 644 => x"0b", + 645 => x"34", + 646 => x"04", + 647 => x"77", + 648 => x"c6", + 649 => x"81", + 650 => x"55", + 651 => x"94", + 652 => x"80", + 653 => x"87", + 654 => x"51", + 655 => x"96", + 656 => x"06", + 657 => x"70", + 658 => x"38", + 659 => x"70", + 660 => x"51", + 661 => x"72", + 662 => x"81", + 663 => x"70", + 664 => x"38", + 665 => x"70", + 666 => x"51", + 667 => x"38", + 668 => x"06", + 669 => x"94", + 670 => x"80", + 671 => x"87", + 672 => x"52", + 673 => x"75", + 674 => x"0c", + 675 => x"04", + 676 => x"02", + 677 => x"0b", + 678 => x"e0", + 679 => x"ff", + 680 => x"56", + 681 => x"84", + 682 => x"2e", + 683 => x"c0", + 684 => x"70", + 685 => x"2a", + 686 => x"53", + 687 => x"80", + 688 => x"71", + 689 => x"81", + 690 => x"70", + 691 => x"81", + 692 => x"06", + 693 => x"80", + 694 => x"71", + 695 => x"81", + 696 => x"70", + 697 => x"73", + 698 => x"51", + 699 => x"80", + 700 => x"2e", + 701 => x"c0", + 702 => x"75", + 703 => x"3d", + 704 => x"3d", + 705 => x"80", + 706 => x"81", + 707 => x"53", + 708 => x"2e", + 709 => x"71", + 710 => x"81", + 711 => x"91", + 712 => x"70", + 713 => x"59", + 714 => x"87", + 715 => x"51", + 716 => x"86", + 717 => x"94", + 718 => x"08", + 719 => x"70", + 720 => x"54", + 721 => x"2e", + 722 => x"91", + 723 => x"06", + 724 => x"d7", + 725 => x"32", + 726 => x"51", + 727 => x"2e", + 728 => x"93", + 729 => x"06", + 730 => x"ff", + 731 => x"81", + 732 => x"87", + 733 => x"52", + 734 => x"86", + 735 => x"94", + 736 => x"72", + 737 => x"74", + 738 => x"ff", + 739 => x"57", + 740 => x"38", + 741 => x"88", + 742 => x"0d", + 743 => x"0d", + 744 => x"c6", + 745 => x"81", + 746 => x"52", + 747 => x"84", + 748 => x"2e", + 749 => x"c0", + 750 => x"70", + 751 => x"2a", + 752 => x"51", + 753 => x"80", + 754 => x"71", + 755 => x"51", + 756 => x"80", + 757 => x"2e", + 758 => x"c0", + 759 => x"71", + 760 => x"ff", + 761 => x"88", + 762 => x"3d", + 763 => x"3d", + 764 => x"91", + 765 => x"70", + 766 => x"52", + 767 => x"94", + 768 => x"80", + 769 => x"87", + 770 => x"52", + 771 => x"82", + 772 => x"06", + 773 => x"ff", + 774 => x"2e", + 775 => x"81", + 776 => x"87", + 777 => x"52", + 778 => x"86", + 779 => x"94", + 780 => x"08", + 781 => x"70", + 782 => x"53", + 783 => x"ca", + 784 => x"3d", + 785 => x"3d", + 786 => x"9e", + 787 => x"9c", + 788 => x"51", + 789 => x"2e", + 790 => x"87", + 791 => x"08", + 792 => x"0c", + 793 => x"a0", + 794 => x"e8", + 795 => x"9e", + 796 => x"c6", + 797 => x"c0", + 798 => x"91", + 799 => x"87", + 800 => x"08", + 801 => x"0c", + 802 => x"98", + 803 => x"f8", + 804 => x"9e", + 805 => x"c6", + 806 => x"c0", + 807 => x"91", + 808 => x"87", + 809 => x"08", + 810 => x"0c", + 811 => x"80", + 812 => x"91", + 813 => x"87", + 814 => x"08", + 815 => x"0c", + 816 => x"c7", + 817 => x"0b", + 818 => x"88", + 819 => x"80", + 820 => x"52", + 821 => x"83", + 822 => x"71", + 823 => x"34", + 824 => x"c0", + 825 => x"70", + 826 => x"06", + 827 => x"70", + 828 => x"38", + 829 => x"91", + 830 => x"80", + 831 => x"9e", + 832 => x"80", + 833 => x"51", + 834 => x"80", + 835 => x"81", + 836 => x"c7", + 837 => x"0b", + 838 => x"88", + 839 => x"80", + 840 => x"52", + 841 => x"83", + 842 => x"71", + 843 => x"34", + 844 => x"c0", + 845 => x"70", + 846 => x"51", + 847 => x"80", + 848 => x"81", + 849 => x"c7", + 850 => x"0b", + 851 => x"88", + 852 => x"80", + 853 => x"52", + 854 => x"83", + 855 => x"71", + 856 => x"34", + 857 => x"c0", + 858 => x"70", + 859 => x"51", + 860 => x"80", + 861 => x"81", + 862 => x"c7", + 863 => x"0b", + 864 => x"88", + 865 => x"80", + 866 => x"52", + 867 => x"83", + 868 => x"71", + 869 => x"34", + 870 => x"88", + 871 => x"e0", + 872 => x"2c", + 873 => x"70", + 874 => x"34", + 875 => x"c0", + 876 => x"70", + 877 => x"52", + 878 => x"2e", + 879 => x"52", + 880 => x"9a", + 881 => x"87", + 882 => x"08", + 883 => x"51", + 884 => x"80", + 885 => x"81", + 886 => x"c7", + 887 => x"c0", + 888 => x"70", + 889 => x"51", + 890 => x"9c", + 891 => x"0d", + 892 => x"0d", + 893 => x"51", + 894 => x"91", + 895 => x"54", + 896 => x"88", + 897 => x"98", + 898 => x"3f", + 899 => x"51", + 900 => x"91", + 901 => x"54", + 902 => x"92", + 903 => x"e8", + 904 => x"c6", + 905 => x"91", + 906 => x"89", + 907 => x"c7", + 908 => x"73", + 909 => x"38", + 910 => x"08", + 911 => x"ec", + 912 => x"b4", + 913 => x"b9", + 914 => x"93", + 915 => x"8b", + 916 => x"94", + 917 => x"80", + 918 => x"91", + 919 => x"53", + 920 => x"08", + 921 => x"90", + 922 => x"3f", + 923 => x"33", + 924 => x"2e", + 925 => x"b5", + 926 => x"a1", + 927 => x"96", + 928 => x"80", + 929 => x"91", + 930 => x"83", + 931 => x"c7", + 932 => x"73", + 933 => x"38", + 934 => x"51", + 935 => x"91", + 936 => x"54", + 937 => x"8d", + 938 => x"99", + 939 => x"b5", + 940 => x"cd", + 941 => x"9a", + 942 => x"80", + 943 => x"91", + 944 => x"82", + 945 => x"c7", + 946 => x"73", + 947 => x"38", + 948 => x"33", + 949 => x"94", + 950 => x"3f", + 951 => x"51", + 952 => x"91", + 953 => x"52", + 954 => x"51", + 955 => x"91", + 956 => x"52", + 957 => x"51", + 958 => x"91", + 959 => x"52", + 960 => x"51", + 961 => x"91", + 962 => x"52", + 963 => x"51", + 964 => x"91", + 965 => x"52", + 966 => x"51", + 967 => x"85", + 968 => x"fe", + 969 => x"92", + 970 => x"05", + 971 => x"26", + 972 => x"84", + 973 => x"91", + 974 => x"52", + 975 => x"91", + 976 => x"9d", + 977 => x"8c", + 978 => x"91", + 979 => x"91", + 980 => x"9c", + 981 => x"91", + 982 => x"85", + 983 => x"a8", + 984 => x"3f", + 985 => x"04", + 986 => x"0c", + 987 => x"87", + 988 => x"0c", + 989 => x"0d", + 990 => x"84", + 991 => x"52", + 992 => x"70", + 993 => x"91", + 994 => x"72", + 995 => x"0d", + 996 => x"0d", + 997 => x"84", + 998 => x"c7", + 999 => x"80", + 1000 => x"09", + 1001 => x"a0", + 1002 => x"91", + 1003 => x"73", + 1004 => x"3d", + 1005 => x"c7", + 1006 => x"c0", + 1007 => x"04", + 1008 => x"02", + 1009 => x"53", + 1010 => x"09", + 1011 => x"38", + 1012 => x"3f", + 1013 => x"08", + 1014 => x"2e", + 1015 => x"72", + 1016 => x"a0", + 1017 => x"91", + 1018 => x"8f", + 1019 => x"98", + 1020 => x"80", + 1021 => x"72", + 1022 => x"84", + 1023 => x"fe", + 1024 => x"97", + 1025 => x"ca", + 1026 => x"91", + 1027 => x"54", + 1028 => x"3f", + 1029 => x"98", + 1030 => x"0d", + 1031 => x"0d", + 1032 => x"33", + 1033 => x"06", + 1034 => x"80", + 1035 => x"72", + 1036 => x"51", + 1037 => x"ff", + 1038 => x"39", + 1039 => x"04", + 1040 => x"77", + 1041 => x"08", + 1042 => x"98", + 1043 => x"73", + 1044 => x"ff", + 1045 => x"71", + 1046 => x"38", + 1047 => x"06", + 1048 => x"54", + 1049 => x"e7", + 1050 => x"ca", + 1051 => x"3d", + 1052 => x"3d", + 1053 => x"59", + 1054 => x"81", + 1055 => x"56", + 1056 => x"84", + 1057 => x"a5", + 1058 => x"06", + 1059 => x"80", + 1060 => x"81", + 1061 => x"58", + 1062 => x"b0", + 1063 => x"06", + 1064 => x"5a", + 1065 => x"ad", + 1066 => x"06", + 1067 => x"5a", + 1068 => x"05", + 1069 => x"75", + 1070 => x"81", + 1071 => x"77", + 1072 => x"08", + 1073 => x"05", + 1074 => x"5d", + 1075 => x"39", + 1076 => x"72", + 1077 => x"38", + 1078 => x"7b", + 1079 => x"05", + 1080 => x"70", + 1081 => x"33", + 1082 => x"39", + 1083 => x"32", + 1084 => x"72", + 1085 => x"78", + 1086 => x"70", + 1087 => x"07", + 1088 => x"07", + 1089 => x"51", + 1090 => x"80", + 1091 => x"79", + 1092 => x"70", + 1093 => x"33", + 1094 => x"80", + 1095 => x"38", + 1096 => x"e0", + 1097 => x"38", + 1098 => x"81", + 1099 => x"53", + 1100 => x"2e", + 1101 => x"73", + 1102 => x"a2", + 1103 => x"c3", + 1104 => x"38", + 1105 => x"24", + 1106 => x"80", + 1107 => x"8c", + 1108 => x"39", + 1109 => x"2e", + 1110 => x"81", + 1111 => x"80", + 1112 => x"80", + 1113 => x"d5", + 1114 => x"73", + 1115 => x"8e", + 1116 => x"39", + 1117 => x"2e", + 1118 => x"80", + 1119 => x"84", + 1120 => x"56", + 1121 => x"74", + 1122 => x"72", + 1123 => x"38", + 1124 => x"15", + 1125 => x"54", + 1126 => x"38", + 1127 => x"56", + 1128 => x"81", + 1129 => x"72", + 1130 => x"38", + 1131 => x"90", + 1132 => x"06", + 1133 => x"2e", + 1134 => x"51", + 1135 => x"74", + 1136 => x"53", + 1137 => x"fd", + 1138 => x"51", + 1139 => x"ef", + 1140 => x"19", + 1141 => x"53", + 1142 => x"39", + 1143 => x"39", + 1144 => x"39", + 1145 => x"39", + 1146 => x"39", + 1147 => x"d0", + 1148 => x"39", + 1149 => x"70", + 1150 => x"53", + 1151 => x"88", + 1152 => x"19", + 1153 => x"39", + 1154 => x"54", + 1155 => x"74", + 1156 => x"70", + 1157 => x"07", + 1158 => x"55", + 1159 => x"80", + 1160 => x"72", + 1161 => x"38", + 1162 => x"90", + 1163 => x"80", + 1164 => x"5e", + 1165 => x"74", + 1166 => x"3f", + 1167 => x"08", + 1168 => x"7c", + 1169 => x"54", + 1170 => x"91", + 1171 => x"55", + 1172 => x"92", + 1173 => x"53", + 1174 => x"2e", + 1175 => x"14", + 1176 => x"ff", + 1177 => x"14", + 1178 => x"70", + 1179 => x"34", + 1180 => x"30", + 1181 => x"9f", + 1182 => x"57", + 1183 => x"85", + 1184 => x"b1", + 1185 => x"2a", + 1186 => x"51", + 1187 => x"2e", + 1188 => x"3d", + 1189 => x"05", + 1190 => x"34", + 1191 => x"76", + 1192 => x"54", + 1193 => x"72", + 1194 => x"54", + 1195 => x"70", + 1196 => x"56", + 1197 => x"81", + 1198 => x"7b", + 1199 => x"73", + 1200 => x"3f", + 1201 => x"53", + 1202 => x"74", + 1203 => x"53", + 1204 => x"eb", + 1205 => x"77", + 1206 => x"53", + 1207 => x"14", + 1208 => x"54", + 1209 => x"3f", + 1210 => x"74", + 1211 => x"53", + 1212 => x"fb", + 1213 => x"51", + 1214 => x"ef", + 1215 => x"0d", + 1216 => x"0d", + 1217 => x"70", + 1218 => x"08", + 1219 => x"51", + 1220 => x"85", + 1221 => x"fe", + 1222 => x"91", + 1223 => x"85", + 1224 => x"52", + 1225 => x"ca", + 1226 => x"a0", + 1227 => x"73", + 1228 => x"91", + 1229 => x"84", + 1230 => x"fd", + 1231 => x"ca", + 1232 => x"91", + 1233 => x"87", + 1234 => x"53", + 1235 => x"fa", + 1236 => x"91", + 1237 => x"85", + 1238 => x"fb", + 1239 => x"79", + 1240 => x"08", + 1241 => x"57", + 1242 => x"71", + 1243 => x"e0", + 1244 => x"9c", + 1245 => x"2d", + 1246 => x"08", + 1247 => x"53", + 1248 => x"80", + 1249 => x"8d", + 1250 => x"72", + 1251 => x"30", + 1252 => x"51", + 1253 => x"80", + 1254 => x"71", + 1255 => x"38", + 1256 => x"97", + 1257 => x"25", + 1258 => x"16", + 1259 => x"25", + 1260 => x"14", + 1261 => x"34", + 1262 => x"72", + 1263 => x"3f", + 1264 => x"73", + 1265 => x"72", + 1266 => x"f7", + 1267 => x"53", + 1268 => x"88", + 1269 => x"0d", + 1270 => x"0d", + 1271 => x"08", + 1272 => x"9c", + 1273 => x"76", + 1274 => x"ef", + 1275 => x"ca", + 1276 => x"3d", + 1277 => x"3d", + 1278 => x"5a", + 1279 => x"7a", + 1280 => x"08", + 1281 => x"53", + 1282 => x"09", + 1283 => x"38", + 1284 => x"0c", + 1285 => x"ad", + 1286 => x"06", + 1287 => x"76", + 1288 => x"0c", + 1289 => x"33", + 1290 => x"73", + 1291 => x"81", + 1292 => x"38", + 1293 => x"05", + 1294 => x"08", + 1295 => x"53", + 1296 => x"2e", + 1297 => x"57", + 1298 => x"2e", + 1299 => x"39", + 1300 => x"13", + 1301 => x"08", + 1302 => x"53", + 1303 => x"55", + 1304 => x"80", + 1305 => x"14", + 1306 => x"88", + 1307 => x"27", + 1308 => x"eb", + 1309 => x"53", + 1310 => x"89", + 1311 => x"38", + 1312 => x"55", + 1313 => x"8a", + 1314 => x"a0", + 1315 => x"c2", + 1316 => x"74", + 1317 => x"e0", + 1318 => x"ff", + 1319 => x"d0", + 1320 => x"ff", + 1321 => x"90", + 1322 => x"38", + 1323 => x"81", + 1324 => x"53", + 1325 => x"ca", + 1326 => x"27", + 1327 => x"77", + 1328 => x"08", + 1329 => x"0c", + 1330 => x"33", + 1331 => x"ff", + 1332 => x"80", + 1333 => x"74", + 1334 => x"79", + 1335 => x"74", + 1336 => x"0c", + 1337 => x"04", + 1338 => x"7a", + 1339 => x"80", + 1340 => x"58", + 1341 => x"33", + 1342 => x"a0", + 1343 => x"06", + 1344 => x"13", + 1345 => x"39", + 1346 => x"09", + 1347 => x"38", + 1348 => x"11", + 1349 => x"08", + 1350 => x"54", + 1351 => x"2e", + 1352 => x"80", + 1353 => x"08", + 1354 => x"0c", + 1355 => x"33", + 1356 => x"80", + 1357 => x"38", + 1358 => x"80", + 1359 => x"38", + 1360 => x"57", + 1361 => x"0c", + 1362 => x"33", + 1363 => x"39", + 1364 => x"74", + 1365 => x"38", + 1366 => x"80", + 1367 => x"89", + 1368 => x"38", + 1369 => x"d0", + 1370 => x"55", + 1371 => x"80", + 1372 => x"39", + 1373 => x"d9", + 1374 => x"80", + 1375 => x"27", + 1376 => x"80", + 1377 => x"89", + 1378 => x"70", + 1379 => x"55", + 1380 => x"70", + 1381 => x"55", + 1382 => x"27", + 1383 => x"14", + 1384 => x"06", + 1385 => x"74", + 1386 => x"73", + 1387 => x"38", + 1388 => x"14", + 1389 => x"05", + 1390 => x"08", + 1391 => x"54", + 1392 => x"39", + 1393 => x"84", + 1394 => x"55", + 1395 => x"81", + 1396 => x"ca", + 1397 => x"3d", + 1398 => x"3d", + 1399 => x"05", + 1400 => x"52", + 1401 => x"87", + 1402 => x"a4", + 1403 => x"71", + 1404 => x"0c", + 1405 => x"04", + 1406 => x"02", + 1407 => x"02", + 1408 => x"05", + 1409 => x"83", + 1410 => x"26", + 1411 => x"72", + 1412 => x"c0", + 1413 => x"53", + 1414 => x"74", + 1415 => x"38", + 1416 => x"73", + 1417 => x"c0", + 1418 => x"51", + 1419 => x"85", + 1420 => x"98", + 1421 => x"52", + 1422 => x"82", + 1423 => x"70", + 1424 => x"38", + 1425 => x"8c", + 1426 => x"ec", + 1427 => x"fc", + 1428 => x"52", + 1429 => x"87", + 1430 => x"08", + 1431 => x"2e", + 1432 => x"91", + 1433 => x"34", + 1434 => x"13", + 1435 => x"91", + 1436 => x"86", + 1437 => x"f3", + 1438 => x"62", + 1439 => x"05", + 1440 => x"57", + 1441 => x"83", + 1442 => x"fe", + 1443 => x"ca", + 1444 => x"06", + 1445 => x"71", + 1446 => x"71", + 1447 => x"2b", + 1448 => x"80", + 1449 => x"92", + 1450 => x"c0", + 1451 => x"41", + 1452 => x"5a", + 1453 => x"87", + 1454 => x"0c", + 1455 => x"84", + 1456 => x"08", + 1457 => x"70", + 1458 => x"53", + 1459 => x"2e", + 1460 => x"08", + 1461 => x"70", + 1462 => x"34", + 1463 => x"80", + 1464 => x"53", + 1465 => x"2e", + 1466 => x"53", + 1467 => x"26", + 1468 => x"80", + 1469 => x"87", + 1470 => x"08", + 1471 => x"38", + 1472 => x"8c", + 1473 => x"80", + 1474 => x"78", + 1475 => x"99", + 1476 => x"0c", + 1477 => x"8c", + 1478 => x"08", + 1479 => x"51", + 1480 => x"38", + 1481 => x"8d", + 1482 => x"17", + 1483 => x"81", + 1484 => x"53", + 1485 => x"2e", + 1486 => x"fc", + 1487 => x"52", + 1488 => x"7d", + 1489 => x"ed", + 1490 => x"80", + 1491 => x"71", + 1492 => x"38", + 1493 => x"53", + 1494 => x"88", + 1495 => x"0d", + 1496 => x"0d", + 1497 => x"02", + 1498 => x"05", + 1499 => x"58", + 1500 => x"80", + 1501 => x"fc", + 1502 => x"ca", + 1503 => x"06", + 1504 => x"71", + 1505 => x"81", + 1506 => x"38", + 1507 => x"2b", + 1508 => x"80", + 1509 => x"92", + 1510 => x"c0", + 1511 => x"40", + 1512 => x"5a", + 1513 => x"c0", + 1514 => x"76", + 1515 => x"76", + 1516 => x"75", + 1517 => x"2a", + 1518 => x"51", + 1519 => x"80", + 1520 => x"7a", + 1521 => x"5c", + 1522 => x"81", + 1523 => x"81", + 1524 => x"06", + 1525 => x"80", + 1526 => x"87", + 1527 => x"08", + 1528 => x"38", + 1529 => x"8c", + 1530 => x"80", + 1531 => x"77", + 1532 => x"99", + 1533 => x"0c", + 1534 => x"8c", + 1535 => x"08", + 1536 => x"51", + 1537 => x"38", + 1538 => x"8d", + 1539 => x"70", + 1540 => x"84", + 1541 => x"5b", + 1542 => x"2e", + 1543 => x"fc", + 1544 => x"52", + 1545 => x"7d", + 1546 => x"f8", + 1547 => x"80", + 1548 => x"71", + 1549 => x"38", + 1550 => x"53", + 1551 => x"88", + 1552 => x"0d", + 1553 => x"0d", + 1554 => x"05", + 1555 => x"02", + 1556 => x"05", + 1557 => x"54", + 1558 => x"fe", + 1559 => x"88", + 1560 => x"53", + 1561 => x"80", + 1562 => x"0b", + 1563 => x"8c", + 1564 => x"71", + 1565 => x"dc", + 1566 => x"24", + 1567 => x"84", + 1568 => x"92", + 1569 => x"54", + 1570 => x"8d", + 1571 => x"39", + 1572 => x"80", + 1573 => x"cb", + 1574 => x"70", + 1575 => x"81", + 1576 => x"52", + 1577 => x"8a", + 1578 => x"98", + 1579 => x"71", + 1580 => x"c0", + 1581 => x"52", + 1582 => x"81", + 1583 => x"c0", + 1584 => x"53", + 1585 => x"82", + 1586 => x"71", + 1587 => x"39", + 1588 => x"39", + 1589 => x"77", + 1590 => x"81", + 1591 => x"72", + 1592 => x"84", + 1593 => x"73", + 1594 => x"0c", + 1595 => x"04", + 1596 => x"74", + 1597 => x"71", + 1598 => x"2b", + 1599 => x"88", + 1600 => x"84", + 1601 => x"fd", + 1602 => x"83", + 1603 => x"12", + 1604 => x"2b", + 1605 => x"07", + 1606 => x"70", + 1607 => x"2b", + 1608 => x"07", + 1609 => x"0c", + 1610 => x"56", + 1611 => x"3d", + 1612 => x"3d", + 1613 => x"84", + 1614 => x"22", + 1615 => x"72", + 1616 => x"54", + 1617 => x"2a", + 1618 => x"34", + 1619 => x"04", + 1620 => x"73", + 1621 => x"70", + 1622 => x"05", + 1623 => x"88", + 1624 => x"72", + 1625 => x"54", + 1626 => x"2a", + 1627 => x"70", + 1628 => x"34", + 1629 => x"51", + 1630 => x"83", + 1631 => x"fe", + 1632 => x"75", + 1633 => x"51", + 1634 => x"92", + 1635 => x"81", + 1636 => x"73", + 1637 => x"55", + 1638 => x"51", + 1639 => x"3d", + 1640 => x"3d", + 1641 => x"76", + 1642 => x"72", + 1643 => x"05", + 1644 => x"11", + 1645 => x"38", + 1646 => x"04", + 1647 => x"78", + 1648 => x"56", + 1649 => x"81", + 1650 => x"74", + 1651 => x"56", + 1652 => x"31", + 1653 => x"52", + 1654 => x"80", + 1655 => x"71", + 1656 => x"38", + 1657 => x"88", + 1658 => x"0d", + 1659 => x"0d", + 1660 => x"51", + 1661 => x"73", + 1662 => x"81", + 1663 => x"33", + 1664 => x"38", + 1665 => x"ca", + 1666 => x"3d", + 1667 => x"0b", + 1668 => x"0c", + 1669 => x"91", + 1670 => x"04", + 1671 => x"7b", + 1672 => x"83", + 1673 => x"5a", + 1674 => x"80", + 1675 => x"54", + 1676 => x"53", + 1677 => x"53", + 1678 => x"52", + 1679 => x"3f", + 1680 => x"08", + 1681 => x"81", + 1682 => x"91", + 1683 => x"83", + 1684 => x"16", + 1685 => x"18", + 1686 => x"18", + 1687 => x"58", + 1688 => x"9f", + 1689 => x"33", + 1690 => x"2e", + 1691 => x"93", + 1692 => x"76", + 1693 => x"52", + 1694 => x"51", + 1695 => x"83", + 1696 => x"79", + 1697 => x"0c", + 1698 => x"04", + 1699 => x"78", + 1700 => x"80", + 1701 => x"17", + 1702 => x"38", + 1703 => x"fc", + 1704 => x"88", + 1705 => x"ca", + 1706 => x"38", + 1707 => x"53", + 1708 => x"81", + 1709 => x"f7", + 1710 => x"ca", + 1711 => x"2e", + 1712 => x"55", + 1713 => x"b0", + 1714 => x"91", + 1715 => x"88", + 1716 => x"f8", + 1717 => x"70", + 1718 => x"c0", + 1719 => x"88", + 1720 => x"ca", + 1721 => x"91", + 1722 => x"55", + 1723 => x"09", + 1724 => x"f0", + 1725 => x"33", + 1726 => x"2e", + 1727 => x"80", + 1728 => x"80", + 1729 => x"88", + 1730 => x"17", + 1731 => x"fd", + 1732 => x"d4", + 1733 => x"b2", + 1734 => x"96", + 1735 => x"85", + 1736 => x"75", + 1737 => x"3f", + 1738 => x"e4", + 1739 => x"98", + 1740 => x"9c", + 1741 => x"08", + 1742 => x"17", + 1743 => x"3f", + 1744 => x"52", + 1745 => x"51", + 1746 => x"a0", + 1747 => x"05", + 1748 => x"0c", + 1749 => x"75", + 1750 => x"33", + 1751 => x"3f", + 1752 => x"34", + 1753 => x"52", + 1754 => x"51", + 1755 => x"91", + 1756 => x"80", + 1757 => x"81", + 1758 => x"ca", + 1759 => x"3d", + 1760 => x"3d", + 1761 => x"1a", + 1762 => x"fe", + 1763 => x"54", + 1764 => x"73", + 1765 => x"8a", + 1766 => x"71", + 1767 => x"08", + 1768 => x"75", + 1769 => x"0c", + 1770 => x"04", + 1771 => x"7a", + 1772 => x"56", + 1773 => x"77", + 1774 => x"38", + 1775 => x"08", + 1776 => x"38", + 1777 => x"54", + 1778 => x"2e", + 1779 => x"72", + 1780 => x"38", + 1781 => x"8d", + 1782 => x"39", + 1783 => x"81", + 1784 => x"b6", + 1785 => x"2a", + 1786 => x"2a", + 1787 => x"05", + 1788 => x"55", + 1789 => x"91", + 1790 => x"81", + 1791 => x"83", + 1792 => x"b4", + 1793 => x"17", + 1794 => x"a4", + 1795 => x"55", + 1796 => x"57", + 1797 => x"3f", + 1798 => x"08", + 1799 => x"74", + 1800 => x"14", + 1801 => x"70", + 1802 => x"07", + 1803 => x"71", + 1804 => x"52", + 1805 => x"72", + 1806 => x"75", + 1807 => x"58", + 1808 => x"76", + 1809 => x"15", + 1810 => x"73", + 1811 => x"3f", + 1812 => x"08", + 1813 => x"76", + 1814 => x"06", + 1815 => x"05", + 1816 => x"3f", + 1817 => x"08", + 1818 => x"06", + 1819 => x"76", + 1820 => x"15", + 1821 => x"73", + 1822 => x"3f", + 1823 => x"08", + 1824 => x"82", + 1825 => x"06", + 1826 => x"05", + 1827 => x"3f", + 1828 => x"08", + 1829 => x"58", + 1830 => x"58", + 1831 => x"88", + 1832 => x"0d", + 1833 => x"0d", + 1834 => x"5a", + 1835 => x"59", + 1836 => x"82", + 1837 => x"98", + 1838 => x"82", + 1839 => x"33", + 1840 => x"2e", + 1841 => x"72", + 1842 => x"38", + 1843 => x"8d", + 1844 => x"39", + 1845 => x"81", + 1846 => x"f7", + 1847 => x"2a", + 1848 => x"2a", + 1849 => x"05", + 1850 => x"55", + 1851 => x"91", + 1852 => x"59", + 1853 => x"08", + 1854 => x"74", + 1855 => x"16", + 1856 => x"16", + 1857 => x"59", + 1858 => x"53", + 1859 => x"8f", + 1860 => x"2b", + 1861 => x"74", + 1862 => x"71", + 1863 => x"72", + 1864 => x"0b", + 1865 => x"74", + 1866 => x"17", + 1867 => x"75", + 1868 => x"3f", + 1869 => x"08", + 1870 => x"88", + 1871 => x"38", + 1872 => x"06", + 1873 => x"78", + 1874 => x"54", + 1875 => x"77", + 1876 => x"33", + 1877 => x"71", + 1878 => x"51", + 1879 => x"34", + 1880 => x"76", + 1881 => x"17", + 1882 => x"75", + 1883 => x"3f", + 1884 => x"08", + 1885 => x"88", + 1886 => x"38", + 1887 => x"ff", + 1888 => x"10", + 1889 => x"76", + 1890 => x"51", + 1891 => x"be", + 1892 => x"2a", + 1893 => x"05", + 1894 => x"f9", + 1895 => x"ca", + 1896 => x"91", + 1897 => x"ab", + 1898 => x"0a", + 1899 => x"2b", + 1900 => x"70", + 1901 => x"70", + 1902 => x"54", + 1903 => x"91", + 1904 => x"8f", + 1905 => x"07", + 1906 => x"f7", + 1907 => x"0b", + 1908 => x"78", + 1909 => x"0c", + 1910 => x"04", + 1911 => x"7a", + 1912 => x"08", + 1913 => x"59", + 1914 => x"a4", + 1915 => x"17", + 1916 => x"38", + 1917 => x"aa", + 1918 => x"73", + 1919 => x"fd", + 1920 => x"ca", + 1921 => x"91", + 1922 => x"80", + 1923 => x"39", + 1924 => x"eb", + 1925 => x"80", + 1926 => x"ca", + 1927 => x"80", + 1928 => x"52", + 1929 => x"84", + 1930 => x"88", + 1931 => x"ca", + 1932 => x"2e", + 1933 => x"91", + 1934 => x"81", + 1935 => x"91", + 1936 => x"ff", + 1937 => x"80", + 1938 => x"75", + 1939 => x"3f", + 1940 => x"08", + 1941 => x"16", + 1942 => x"90", + 1943 => x"55", + 1944 => x"27", + 1945 => x"15", + 1946 => x"84", + 1947 => x"07", + 1948 => x"17", + 1949 => x"76", + 1950 => x"a6", + 1951 => x"73", + 1952 => x"0c", + 1953 => x"04", + 1954 => x"7c", + 1955 => x"59", + 1956 => x"95", + 1957 => x"08", + 1958 => x"2e", + 1959 => x"17", + 1960 => x"b2", + 1961 => x"ae", + 1962 => x"7a", + 1963 => x"3f", + 1964 => x"91", + 1965 => x"27", + 1966 => x"91", + 1967 => x"55", + 1968 => x"08", + 1969 => x"d2", + 1970 => x"08", + 1971 => x"08", + 1972 => x"38", + 1973 => x"17", + 1974 => x"54", + 1975 => x"82", + 1976 => x"7a", + 1977 => x"06", + 1978 => x"81", + 1979 => x"17", + 1980 => x"83", + 1981 => x"75", + 1982 => x"f9", + 1983 => x"59", + 1984 => x"08", + 1985 => x"81", + 1986 => x"91", + 1987 => x"59", + 1988 => x"08", + 1989 => x"70", + 1990 => x"25", + 1991 => x"91", + 1992 => x"54", + 1993 => x"55", + 1994 => x"38", + 1995 => x"08", + 1996 => x"38", + 1997 => x"54", + 1998 => x"90", + 1999 => x"18", + 2000 => x"38", + 2001 => x"39", + 2002 => x"38", + 2003 => x"16", + 2004 => x"08", + 2005 => x"38", + 2006 => x"78", + 2007 => x"38", + 2008 => x"51", + 2009 => x"91", + 2010 => x"80", + 2011 => x"80", + 2012 => x"88", + 2013 => x"09", + 2014 => x"38", + 2015 => x"08", + 2016 => x"88", + 2017 => x"30", + 2018 => x"80", + 2019 => x"07", + 2020 => x"55", + 2021 => x"38", + 2022 => x"09", + 2023 => x"ae", + 2024 => x"80", + 2025 => x"53", + 2026 => x"51", + 2027 => x"91", + 2028 => x"91", + 2029 => x"30", + 2030 => x"88", + 2031 => x"25", + 2032 => x"79", + 2033 => x"38", + 2034 => x"8f", + 2035 => x"79", + 2036 => x"f9", + 2037 => x"ca", + 2038 => x"74", + 2039 => x"8c", + 2040 => x"17", + 2041 => x"90", + 2042 => x"54", + 2043 => x"86", + 2044 => x"90", + 2045 => x"17", + 2046 => x"54", + 2047 => x"34", + 2048 => x"56", + 2049 => x"90", + 2050 => x"80", + 2051 => x"91", + 2052 => x"55", + 2053 => x"56", + 2054 => x"91", + 2055 => x"8c", + 2056 => x"f8", + 2057 => x"70", + 2058 => x"f0", + 2059 => x"88", + 2060 => x"56", + 2061 => x"08", + 2062 => x"7b", + 2063 => x"f6", + 2064 => x"ca", + 2065 => x"ca", + 2066 => x"17", + 2067 => x"80", + 2068 => x"b4", + 2069 => x"57", + 2070 => x"77", + 2071 => x"81", + 2072 => x"15", + 2073 => x"78", + 2074 => x"81", + 2075 => x"53", + 2076 => x"15", + 2077 => x"e9", + 2078 => x"88", + 2079 => x"df", + 2080 => x"22", + 2081 => x"30", + 2082 => x"70", + 2083 => x"51", + 2084 => x"91", + 2085 => x"8a", + 2086 => x"f8", + 2087 => x"7c", + 2088 => x"56", + 2089 => x"80", + 2090 => x"f1", + 2091 => x"06", + 2092 => x"e9", + 2093 => x"18", + 2094 => x"08", + 2095 => x"38", + 2096 => x"82", + 2097 => x"38", + 2098 => x"54", + 2099 => x"74", + 2100 => x"82", + 2101 => x"22", + 2102 => x"79", + 2103 => x"38", + 2104 => x"98", + 2105 => x"cd", + 2106 => x"22", + 2107 => x"54", + 2108 => x"26", + 2109 => x"52", + 2110 => x"b0", + 2111 => x"88", + 2112 => x"ca", + 2113 => x"2e", + 2114 => x"0b", + 2115 => x"08", + 2116 => x"98", + 2117 => x"ca", + 2118 => x"85", + 2119 => x"bd", + 2120 => x"31", + 2121 => x"73", + 2122 => x"f4", + 2123 => x"ca", + 2124 => x"18", + 2125 => x"18", + 2126 => x"08", + 2127 => x"72", + 2128 => x"38", + 2129 => x"58", + 2130 => x"89", + 2131 => x"18", + 2132 => x"ff", + 2133 => x"05", + 2134 => x"80", + 2135 => x"ca", + 2136 => x"3d", + 2137 => x"3d", + 2138 => x"08", + 2139 => x"a0", + 2140 => x"54", + 2141 => x"77", + 2142 => x"80", + 2143 => x"0c", + 2144 => x"53", + 2145 => x"80", + 2146 => x"38", + 2147 => x"06", + 2148 => x"b5", + 2149 => x"98", + 2150 => x"14", + 2151 => x"92", + 2152 => x"2a", + 2153 => x"56", + 2154 => x"26", + 2155 => x"80", + 2156 => x"16", + 2157 => x"77", + 2158 => x"53", + 2159 => x"38", + 2160 => x"51", + 2161 => x"91", + 2162 => x"53", + 2163 => x"0b", + 2164 => x"08", + 2165 => x"38", + 2166 => x"ca", + 2167 => x"2e", + 2168 => x"98", + 2169 => x"ca", + 2170 => x"80", + 2171 => x"8a", + 2172 => x"15", + 2173 => x"80", + 2174 => x"14", + 2175 => x"51", + 2176 => x"91", + 2177 => x"53", + 2178 => x"ca", + 2179 => x"2e", + 2180 => x"82", + 2181 => x"88", + 2182 => x"ba", + 2183 => x"91", + 2184 => x"ff", + 2185 => x"91", + 2186 => x"52", + 2187 => x"f3", + 2188 => x"88", + 2189 => x"72", + 2190 => x"72", + 2191 => x"f2", + 2192 => x"ca", + 2193 => x"15", + 2194 => x"15", + 2195 => x"b4", + 2196 => x"0c", + 2197 => x"91", + 2198 => x"8a", + 2199 => x"f7", + 2200 => x"7d", + 2201 => x"5b", + 2202 => x"76", + 2203 => x"3f", + 2204 => x"08", + 2205 => x"88", + 2206 => x"38", + 2207 => x"08", + 2208 => x"08", + 2209 => x"f0", + 2210 => x"ca", + 2211 => x"91", + 2212 => x"80", + 2213 => x"ca", + 2214 => x"18", + 2215 => x"51", + 2216 => x"81", + 2217 => x"81", + 2218 => x"81", + 2219 => x"88", + 2220 => x"83", + 2221 => x"77", + 2222 => x"72", + 2223 => x"38", + 2224 => x"75", + 2225 => x"81", + 2226 => x"a5", + 2227 => x"88", + 2228 => x"52", + 2229 => x"8e", + 2230 => x"88", + 2231 => x"ca", + 2232 => x"2e", + 2233 => x"73", + 2234 => x"81", + 2235 => x"87", + 2236 => x"ca", + 2237 => x"3d", + 2238 => x"3d", + 2239 => x"11", + 2240 => x"ec", + 2241 => x"88", + 2242 => x"ff", + 2243 => x"33", + 2244 => x"71", + 2245 => x"81", + 2246 => x"94", + 2247 => x"d0", + 2248 => x"88", + 2249 => x"73", + 2250 => x"91", + 2251 => x"85", + 2252 => x"fc", + 2253 => x"79", + 2254 => x"ff", + 2255 => x"12", + 2256 => x"eb", + 2257 => x"70", + 2258 => x"72", + 2259 => x"81", + 2260 => x"73", + 2261 => x"94", + 2262 => x"d6", + 2263 => x"0d", + 2264 => x"0d", + 2265 => x"55", + 2266 => x"5a", + 2267 => x"08", + 2268 => x"8a", + 2269 => x"08", + 2270 => x"ee", + 2271 => x"ca", + 2272 => x"91", + 2273 => x"80", + 2274 => x"15", + 2275 => x"55", + 2276 => x"38", + 2277 => x"e6", + 2278 => x"33", + 2279 => x"70", + 2280 => x"58", + 2281 => x"86", + 2282 => x"ca", + 2283 => x"73", + 2284 => x"83", + 2285 => x"73", + 2286 => x"38", + 2287 => x"06", + 2288 => x"80", + 2289 => x"75", + 2290 => x"38", + 2291 => x"08", + 2292 => x"54", + 2293 => x"2e", + 2294 => x"83", + 2295 => x"73", + 2296 => x"38", + 2297 => x"51", + 2298 => x"91", + 2299 => x"58", + 2300 => x"08", + 2301 => x"15", + 2302 => x"38", + 2303 => x"0b", + 2304 => x"77", + 2305 => x"0c", + 2306 => x"04", + 2307 => x"77", + 2308 => x"54", + 2309 => x"51", + 2310 => x"91", + 2311 => x"55", + 2312 => x"08", + 2313 => x"14", + 2314 => x"51", + 2315 => x"91", + 2316 => x"55", + 2317 => x"08", + 2318 => x"53", + 2319 => x"08", + 2320 => x"08", + 2321 => x"3f", + 2322 => x"14", + 2323 => x"08", + 2324 => x"3f", + 2325 => x"17", + 2326 => x"ca", + 2327 => x"3d", + 2328 => x"3d", + 2329 => x"08", + 2330 => x"54", + 2331 => x"53", + 2332 => x"91", + 2333 => x"8d", + 2334 => x"08", + 2335 => x"34", + 2336 => x"15", + 2337 => x"0d", + 2338 => x"0d", + 2339 => x"57", + 2340 => x"17", + 2341 => x"08", + 2342 => x"82", + 2343 => x"89", + 2344 => x"55", + 2345 => x"14", + 2346 => x"16", + 2347 => x"71", + 2348 => x"38", + 2349 => x"09", + 2350 => x"38", + 2351 => x"73", + 2352 => x"81", + 2353 => x"ae", + 2354 => x"05", + 2355 => x"15", + 2356 => x"70", + 2357 => x"34", + 2358 => x"8a", + 2359 => x"38", + 2360 => x"05", + 2361 => x"81", + 2362 => x"17", + 2363 => x"12", + 2364 => x"34", + 2365 => x"9c", + 2366 => x"e8", + 2367 => x"ca", + 2368 => x"0c", + 2369 => x"e7", + 2370 => x"ca", + 2371 => x"17", + 2372 => x"51", + 2373 => x"91", + 2374 => x"84", + 2375 => x"3d", + 2376 => x"3d", + 2377 => x"08", + 2378 => x"61", + 2379 => x"55", + 2380 => x"2e", + 2381 => x"55", + 2382 => x"2e", + 2383 => x"80", + 2384 => x"94", + 2385 => x"1c", + 2386 => x"81", + 2387 => x"61", + 2388 => x"56", + 2389 => x"2e", + 2390 => x"83", + 2391 => x"73", + 2392 => x"70", + 2393 => x"25", + 2394 => x"51", + 2395 => x"38", + 2396 => x"0c", + 2397 => x"51", + 2398 => x"26", + 2399 => x"80", + 2400 => x"34", + 2401 => x"51", + 2402 => x"91", + 2403 => x"55", + 2404 => x"91", + 2405 => x"1d", + 2406 => x"8b", + 2407 => x"79", + 2408 => x"3f", + 2409 => x"57", + 2410 => x"55", + 2411 => x"2e", + 2412 => x"80", + 2413 => x"18", + 2414 => x"1a", + 2415 => x"70", + 2416 => x"2a", + 2417 => x"07", + 2418 => x"5a", + 2419 => x"8c", + 2420 => x"54", + 2421 => x"81", + 2422 => x"39", + 2423 => x"70", + 2424 => x"2a", + 2425 => x"75", + 2426 => x"8c", + 2427 => x"2e", + 2428 => x"a0", + 2429 => x"38", + 2430 => x"0c", + 2431 => x"76", + 2432 => x"38", + 2433 => x"b8", + 2434 => x"70", + 2435 => x"5a", + 2436 => x"76", + 2437 => x"38", + 2438 => x"70", + 2439 => x"dc", + 2440 => x"72", + 2441 => x"80", + 2442 => x"51", + 2443 => x"73", + 2444 => x"38", + 2445 => x"18", + 2446 => x"1a", + 2447 => x"55", + 2448 => x"2e", + 2449 => x"83", + 2450 => x"73", + 2451 => x"70", + 2452 => x"25", + 2453 => x"51", + 2454 => x"38", + 2455 => x"75", + 2456 => x"81", + 2457 => x"81", + 2458 => x"27", + 2459 => x"73", + 2460 => x"38", + 2461 => x"70", + 2462 => x"32", + 2463 => x"80", + 2464 => x"2a", + 2465 => x"56", + 2466 => x"81", + 2467 => x"57", + 2468 => x"f5", + 2469 => x"2b", + 2470 => x"25", + 2471 => x"80", + 2472 => x"b9", + 2473 => x"57", + 2474 => x"e6", + 2475 => x"ca", + 2476 => x"2e", + 2477 => x"18", + 2478 => x"1a", + 2479 => x"56", + 2480 => x"3f", + 2481 => x"08", + 2482 => x"e8", + 2483 => x"54", + 2484 => x"80", + 2485 => x"17", + 2486 => x"34", + 2487 => x"11", + 2488 => x"74", + 2489 => x"75", + 2490 => x"b4", + 2491 => x"3f", + 2492 => x"08", + 2493 => x"9f", + 2494 => x"99", + 2495 => x"e0", + 2496 => x"ff", + 2497 => x"79", + 2498 => x"74", + 2499 => x"57", + 2500 => x"77", + 2501 => x"76", + 2502 => x"38", + 2503 => x"73", + 2504 => x"09", + 2505 => x"38", + 2506 => x"84", + 2507 => x"27", + 2508 => x"39", + 2509 => x"f2", + 2510 => x"80", + 2511 => x"54", + 2512 => x"34", + 2513 => x"58", + 2514 => x"f2", + 2515 => x"ca", + 2516 => x"91", + 2517 => x"80", + 2518 => x"1b", + 2519 => x"51", + 2520 => x"91", + 2521 => x"56", + 2522 => x"08", + 2523 => x"9c", + 2524 => x"33", + 2525 => x"80", + 2526 => x"38", + 2527 => x"bf", + 2528 => x"86", + 2529 => x"15", + 2530 => x"2a", + 2531 => x"51", + 2532 => x"92", + 2533 => x"79", + 2534 => x"e4", + 2535 => x"ca", + 2536 => x"2e", + 2537 => x"52", + 2538 => x"ba", + 2539 => x"39", + 2540 => x"33", + 2541 => x"80", + 2542 => x"74", + 2543 => x"81", + 2544 => x"38", + 2545 => x"70", + 2546 => x"82", + 2547 => x"54", + 2548 => x"96", + 2549 => x"06", + 2550 => x"2e", + 2551 => x"ff", + 2552 => x"1c", + 2553 => x"80", + 2554 => x"81", + 2555 => x"ba", + 2556 => x"b6", + 2557 => x"2a", + 2558 => x"51", + 2559 => x"38", + 2560 => x"70", + 2561 => x"81", + 2562 => x"55", + 2563 => x"e1", + 2564 => x"08", + 2565 => x"1d", + 2566 => x"7c", + 2567 => x"3f", + 2568 => x"08", + 2569 => x"fa", + 2570 => x"91", + 2571 => x"8f", + 2572 => x"f6", + 2573 => x"5b", + 2574 => x"70", + 2575 => x"59", + 2576 => x"73", + 2577 => x"c6", + 2578 => x"81", + 2579 => x"70", + 2580 => x"52", + 2581 => x"8d", + 2582 => x"38", + 2583 => x"09", + 2584 => x"a5", + 2585 => x"d0", + 2586 => x"ff", + 2587 => x"53", + 2588 => x"91", + 2589 => x"73", + 2590 => x"d0", + 2591 => x"71", + 2592 => x"f7", + 2593 => x"91", + 2594 => x"55", + 2595 => x"55", + 2596 => x"81", + 2597 => x"74", + 2598 => x"56", + 2599 => x"12", + 2600 => x"70", + 2601 => x"38", + 2602 => x"81", + 2603 => x"51", + 2604 => x"51", + 2605 => x"89", + 2606 => x"70", + 2607 => x"53", + 2608 => x"70", + 2609 => x"51", + 2610 => x"09", + 2611 => x"38", + 2612 => x"38", + 2613 => x"77", + 2614 => x"70", + 2615 => x"2a", + 2616 => x"07", + 2617 => x"51", + 2618 => x"8f", + 2619 => x"84", + 2620 => x"83", + 2621 => x"94", + 2622 => x"74", + 2623 => x"38", + 2624 => x"0c", + 2625 => x"86", + 2626 => x"b8", + 2627 => x"91", + 2628 => x"8c", + 2629 => x"fa", + 2630 => x"56", + 2631 => x"17", + 2632 => x"b0", + 2633 => x"52", + 2634 => x"e0", + 2635 => x"91", + 2636 => x"81", + 2637 => x"b2", + 2638 => x"b4", + 2639 => x"88", + 2640 => x"ff", + 2641 => x"55", + 2642 => x"d5", + 2643 => x"06", + 2644 => x"80", + 2645 => x"33", + 2646 => x"81", + 2647 => x"81", + 2648 => x"81", + 2649 => x"eb", + 2650 => x"70", + 2651 => x"07", + 2652 => x"73", + 2653 => x"81", + 2654 => x"81", + 2655 => x"83", + 2656 => x"c4", + 2657 => x"16", + 2658 => x"3f", + 2659 => x"08", + 2660 => x"88", + 2661 => x"9d", + 2662 => x"91", + 2663 => x"81", + 2664 => x"e0", + 2665 => x"ca", + 2666 => x"91", + 2667 => x"80", + 2668 => x"82", + 2669 => x"ca", + 2670 => x"3d", + 2671 => x"3d", + 2672 => x"84", + 2673 => x"05", + 2674 => x"80", + 2675 => x"51", + 2676 => x"91", + 2677 => x"58", + 2678 => x"0b", + 2679 => x"08", + 2680 => x"38", + 2681 => x"08", + 2682 => x"ca", + 2683 => x"08", + 2684 => x"56", + 2685 => x"86", + 2686 => x"75", + 2687 => x"fe", + 2688 => x"54", + 2689 => x"2e", + 2690 => x"14", + 2691 => x"ca", + 2692 => x"88", + 2693 => x"06", + 2694 => x"54", + 2695 => x"38", + 2696 => x"86", + 2697 => x"82", + 2698 => x"06", + 2699 => x"56", + 2700 => x"38", + 2701 => x"80", + 2702 => x"81", + 2703 => x"52", + 2704 => x"51", + 2705 => x"91", + 2706 => x"81", + 2707 => x"81", + 2708 => x"83", + 2709 => x"87", + 2710 => x"2e", + 2711 => x"82", + 2712 => x"06", + 2713 => x"56", + 2714 => x"38", + 2715 => x"74", + 2716 => x"a3", + 2717 => x"88", + 2718 => x"06", + 2719 => x"2e", + 2720 => x"80", + 2721 => x"3d", + 2722 => x"83", + 2723 => x"15", + 2724 => x"53", + 2725 => x"8d", + 2726 => x"15", + 2727 => x"3f", + 2728 => x"08", + 2729 => x"70", + 2730 => x"0c", + 2731 => x"16", + 2732 => x"80", + 2733 => x"80", + 2734 => x"54", + 2735 => x"84", + 2736 => x"5b", + 2737 => x"80", + 2738 => x"7a", + 2739 => x"fc", + 2740 => x"ca", + 2741 => x"ff", + 2742 => x"77", + 2743 => x"81", + 2744 => x"76", + 2745 => x"81", + 2746 => x"2e", + 2747 => x"8d", + 2748 => x"26", + 2749 => x"bf", + 2750 => x"f4", + 2751 => x"88", + 2752 => x"ff", + 2753 => x"84", + 2754 => x"81", + 2755 => x"38", + 2756 => x"51", + 2757 => x"91", + 2758 => x"83", + 2759 => x"58", + 2760 => x"80", + 2761 => x"db", + 2762 => x"ca", + 2763 => x"77", + 2764 => x"80", + 2765 => x"82", + 2766 => x"c4", + 2767 => x"11", + 2768 => x"06", + 2769 => x"8d", + 2770 => x"26", + 2771 => x"74", + 2772 => x"78", + 2773 => x"c1", + 2774 => x"59", + 2775 => x"15", + 2776 => x"2e", + 2777 => x"13", + 2778 => x"72", + 2779 => x"38", + 2780 => x"eb", + 2781 => x"14", + 2782 => x"3f", + 2783 => x"08", + 2784 => x"88", + 2785 => x"23", + 2786 => x"57", + 2787 => x"83", + 2788 => x"c7", + 2789 => x"d8", + 2790 => x"88", + 2791 => x"ff", + 2792 => x"8d", + 2793 => x"14", + 2794 => x"3f", + 2795 => x"08", + 2796 => x"14", + 2797 => x"3f", + 2798 => x"08", + 2799 => x"06", + 2800 => x"72", + 2801 => x"97", + 2802 => x"22", + 2803 => x"84", + 2804 => x"5a", + 2805 => x"83", + 2806 => x"14", + 2807 => x"79", + 2808 => x"b3", + 2809 => x"ca", + 2810 => x"91", + 2811 => x"80", + 2812 => x"38", + 2813 => x"08", + 2814 => x"ff", + 2815 => x"38", + 2816 => x"83", + 2817 => x"83", + 2818 => x"74", + 2819 => x"85", + 2820 => x"89", + 2821 => x"76", + 2822 => x"c3", + 2823 => x"70", + 2824 => x"7b", + 2825 => x"73", + 2826 => x"17", + 2827 => x"ac", + 2828 => x"55", + 2829 => x"09", + 2830 => x"38", + 2831 => x"51", + 2832 => x"91", + 2833 => x"83", + 2834 => x"53", + 2835 => x"82", + 2836 => x"82", + 2837 => x"e0", + 2838 => x"ab", + 2839 => x"88", + 2840 => x"0c", + 2841 => x"53", + 2842 => x"56", + 2843 => x"81", + 2844 => x"13", + 2845 => x"74", + 2846 => x"82", + 2847 => x"74", + 2848 => x"81", + 2849 => x"06", + 2850 => x"83", + 2851 => x"2a", + 2852 => x"72", + 2853 => x"26", + 2854 => x"ff", + 2855 => x"0c", + 2856 => x"15", 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x"09", + 2916 => x"38", + 2917 => x"51", + 2918 => x"91", + 2919 => x"81", + 2920 => x"88", + 2921 => x"08", + 2922 => x"39", + 2923 => x"73", + 2924 => x"74", + 2925 => x"0c", + 2926 => x"04", + 2927 => x"02", + 2928 => x"7a", + 2929 => x"fc", + 2930 => x"f4", + 2931 => x"54", + 2932 => x"ca", + 2933 => x"bc", + 2934 => x"88", + 2935 => x"91", + 2936 => x"70", + 2937 => x"73", + 2938 => x"38", + 2939 => x"78", + 2940 => x"2e", + 2941 => x"74", + 2942 => x"0c", + 2943 => x"80", + 2944 => x"80", + 2945 => x"70", + 2946 => x"51", + 2947 => x"91", + 2948 => x"54", + 2949 => x"88", + 2950 => x"0d", + 2951 => x"0d", + 2952 => x"05", + 2953 => x"33", + 2954 => x"54", + 2955 => x"84", + 2956 => x"bf", + 2957 => x"98", + 2958 => x"53", + 2959 => x"05", + 2960 => x"fa", + 2961 => x"88", + 2962 => x"ca", + 2963 => x"a4", + 2964 => x"68", + 2965 => x"70", + 2966 => x"c6", + 2967 => x"88", + 2968 => x"ca", + 2969 => x"38", + 2970 => x"05", + 2971 => x"2b", + 2972 => x"80", + 2973 => x"86", + 2974 => x"06", + 2975 => x"2e", + 2976 => x"74", + 2977 => x"38", + 2978 => x"09", + 2979 => x"38", + 2980 => x"f8", + 2981 => x"88", + 2982 => x"39", + 2983 => x"33", + 2984 => x"73", + 2985 => x"77", + 2986 => x"81", + 2987 => x"73", + 2988 => x"38", + 2989 => x"bc", + 2990 => x"07", + 2991 => x"b4", + 2992 => x"2a", + 2993 => x"51", + 2994 => x"2e", + 2995 => x"62", + 2996 => x"e8", + 2997 => x"ca", + 2998 => x"82", + 2999 => x"52", + 3000 => x"51", + 3001 => x"62", + 3002 => x"8b", + 3003 => x"53", + 3004 => x"51", + 3005 => x"80", + 3006 => x"05", + 3007 => x"3f", + 3008 => x"0b", + 3009 => x"75", + 3010 => x"f1", + 3011 => x"11", + 3012 => x"80", + 3013 => x"97", + 3014 => x"51", + 3015 => x"91", + 3016 => x"55", + 3017 => x"08", + 3018 => x"b7", + 3019 => x"c4", + 3020 => x"05", + 3021 => x"2a", + 3022 => x"51", + 3023 => x"80", + 3024 => x"84", + 3025 => x"39", + 3026 => x"70", + 3027 => x"54", + 3028 => x"a9", + 3029 => x"06", + 3030 => x"2e", + 3031 => x"55", + 3032 => x"73", + 3033 => x"d6", + 3034 => x"ca", + 3035 => x"ff", + 3036 => x"0c", + 3037 => x"ca", + 3038 => x"f8", + 3039 => x"2a", + 3040 => x"51", + 3041 => x"2e", + 3042 => x"80", + 3043 => x"7a", + 3044 => x"a0", + 3045 => x"a4", + 3046 => x"53", + 3047 => x"e6", + 3048 => x"ca", + 3049 => x"ca", + 3050 => x"1b", + 3051 => x"05", + 3052 => x"d3", + 3053 => x"88", + 3054 => x"88", + 3055 => x"0c", + 3056 => x"56", + 3057 => x"84", + 3058 => x"90", + 3059 => x"0b", + 3060 => x"80", + 3061 => x"0c", + 3062 => x"1a", + 3063 => x"2a", + 3064 => x"51", + 3065 => x"2e", + 3066 => x"91", + 3067 => x"80", + 3068 => x"38", + 3069 => x"08", + 3070 => x"8a", + 3071 => x"89", + 3072 => x"59", + 3073 => x"76", + 3074 => x"d7", + 3075 => x"ca", + 3076 => x"91", + 3077 => x"81", + 3078 => x"82", + 3079 => x"88", + 3080 => x"09", + 3081 => x"38", + 3082 => x"78", + 3083 => x"30", + 3084 => x"80", + 3085 => x"77", + 3086 => x"38", + 3087 => x"06", + 3088 => x"c3", + 3089 => x"1a", + 3090 => x"38", + 3091 => x"06", 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x"08", + 3151 => x"83", + 3152 => x"88", + 3153 => x"89", + 3154 => x"77", + 3155 => x"d6", + 3156 => x"7f", + 3157 => x"58", + 3158 => x"75", + 3159 => x"75", + 3160 => x"77", + 3161 => x"7c", + 3162 => x"33", + 3163 => x"3f", + 3164 => x"08", + 3165 => x"7e", + 3166 => x"56", + 3167 => x"2e", + 3168 => x"16", + 3169 => x"55", + 3170 => x"94", + 3171 => x"53", + 3172 => x"b0", + 3173 => x"31", + 3174 => x"05", + 3175 => x"3f", + 3176 => x"56", + 3177 => x"9c", + 3178 => x"19", + 3179 => x"06", + 3180 => x"31", + 3181 => x"76", + 3182 => x"7b", + 3183 => x"08", + 3184 => x"d1", + 3185 => x"ca", + 3186 => x"81", + 3187 => x"94", + 3188 => x"ff", + 3189 => x"05", + 3190 => x"cf", + 3191 => x"76", + 3192 => x"17", + 3193 => x"1e", + 3194 => x"18", + 3195 => x"5e", + 3196 => x"39", + 3197 => x"91", + 3198 => x"90", + 3199 => x"f2", + 3200 => x"63", + 3201 => x"40", + 3202 => x"7e", + 3203 => x"fc", + 3204 => x"51", + 3205 => x"91", + 3206 => x"55", + 3207 => x"08", + 3208 => x"18", + 3209 => x"80", + 3210 => x"74", + 3211 => x"39", + 3212 => x"70", + 3213 => x"81", + 3214 => x"56", + 3215 => x"80", + 3216 => x"38", + 3217 => x"0b", + 3218 => x"82", + 3219 => x"39", + 3220 => x"19", + 3221 => x"83", + 3222 => x"18", + 3223 => x"56", + 3224 => x"27", + 3225 => x"09", + 3226 => x"2e", + 3227 => x"94", + 3228 => x"83", + 3229 => x"56", + 3230 => x"38", + 3231 => x"22", + 3232 => x"89", + 3233 => x"55", + 3234 => x"75", + 3235 => x"18", + 3236 => x"9c", + 3237 => x"85", + 3238 => x"08", + 3239 => x"d7", + 3240 => x"ca", + 3241 => x"91", + 3242 => x"80", + 3243 => x"38", + 3244 => x"ff", + 3245 => x"ff", + 3246 => x"38", + 3247 => x"0c", + 3248 => x"85", + 3249 => x"19", + 3250 => x"b0", + 3251 => x"19", + 3252 => x"81", + 3253 => x"74", + 3254 => x"3f", + 3255 => x"08", + 3256 => x"98", + 3257 => x"7e", + 3258 => x"3f", + 3259 => x"08", + 3260 => x"d2", + 3261 => x"88", + 3262 => x"89", + 3263 => x"78", + 3264 => x"d5", + 3265 => x"7f", + 3266 => x"58", + 3267 => x"75", + 3268 => x"75", + 3269 => x"78", + 3270 => x"7c", + 3271 => x"33", + 3272 => x"3f", + 3273 => x"08", + 3274 => x"7e", + 3275 => x"78", + 3276 => x"74", + 3277 => x"38", + 3278 => x"b0", + 3279 => x"31", + 3280 => x"05", + 3281 => x"51", + 3282 => x"7e", + 3283 => x"83", + 3284 => x"89", + 3285 => x"db", + 3286 => x"08", + 3287 => x"26", + 3288 => x"51", + 3289 => x"91", + 3290 => x"fd", + 3291 => x"77", + 3292 => x"55", + 3293 => x"0c", + 3294 => x"83", + 3295 => x"80", + 3296 => x"55", + 3297 => x"83", + 3298 => x"9c", + 3299 => x"7e", + 3300 => x"3f", + 3301 => x"08", + 3302 => x"75", + 3303 => x"94", + 3304 => x"ff", + 3305 => x"05", + 3306 => x"3f", + 3307 => x"0b", + 3308 => x"7b", + 3309 => x"08", + 3310 => x"76", + 3311 => x"08", + 3312 => x"1c", + 3313 => x"08", + 3314 => x"5c", + 3315 => x"83", + 3316 => x"74", + 3317 => x"fd", + 3318 => x"18", + 3319 => x"07", + 3320 => x"19", + 3321 => x"75", + 3322 => x"0c", + 3323 => x"04", + 3324 => x"7a", + 3325 => x"05", + 3326 => x"56", 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x"ca", + 3386 => x"3d", + 3387 => x"3d", + 3388 => x"93", + 3389 => x"52", + 3390 => x"e9", + 3391 => x"ca", + 3392 => x"91", + 3393 => x"80", + 3394 => x"58", + 3395 => x"3d", + 3396 => x"e0", + 3397 => x"ca", + 3398 => x"91", + 3399 => x"bc", + 3400 => x"c7", + 3401 => x"98", + 3402 => x"73", + 3403 => x"38", + 3404 => x"12", + 3405 => x"39", + 3406 => x"33", + 3407 => x"70", + 3408 => x"55", + 3409 => x"2e", + 3410 => x"7f", + 3411 => x"54", + 3412 => x"91", + 3413 => x"94", + 3414 => x"39", + 3415 => x"08", + 3416 => x"81", + 3417 => x"85", + 3418 => x"ca", + 3419 => x"3d", + 3420 => x"3d", + 3421 => x"5b", + 3422 => x"34", + 3423 => x"3d", + 3424 => x"52", + 3425 => x"e8", + 3426 => x"ca", + 3427 => x"91", + 3428 => x"82", + 3429 => x"43", + 3430 => x"11", + 3431 => x"58", + 3432 => x"80", + 3433 => x"38", + 3434 => x"3d", + 3435 => x"d5", + 3436 => x"ca", + 3437 => x"91", + 3438 => x"82", + 3439 => x"52", + 3440 => x"c8", + 3441 => x"88", + 3442 => x"ca", + 3443 => x"c1", + 3444 => x"7b", + 3445 => x"3f", + 3446 => x"08", + 3447 => x"74", + 3448 => x"3f", + 3449 => x"08", + 3450 => x"88", + 3451 => x"38", + 3452 => x"51", + 3453 => x"91", + 3454 => x"57", + 3455 => x"08", + 3456 => x"52", + 3457 => x"f2", + 3458 => x"ca", + 3459 => x"a6", + 3460 => x"74", + 3461 => x"3f", + 3462 => x"08", + 3463 => x"88", + 3464 => x"cc", + 3465 => x"2e", + 3466 => x"86", + 3467 => x"81", + 3468 => x"81", + 3469 => x"3d", + 3470 => x"52", + 3471 => x"c9", + 3472 => x"3d", + 3473 => x"11", + 3474 => x"5a", + 3475 => x"2e", + 3476 => x"b9", + 3477 => x"16", + 3478 => x"33", + 3479 => x"73", + 3480 => x"16", + 3481 => x"26", + 3482 => x"75", + 3483 => x"38", + 3484 => x"05", + 3485 => x"6f", + 3486 => x"ff", + 3487 => x"55", + 3488 => x"74", + 3489 => x"38", + 3490 => x"11", + 3491 => x"74", + 3492 => x"39", + 3493 => x"09", + 3494 => x"38", + 3495 => x"11", + 3496 => x"74", + 3497 => x"91", + 3498 => x"70", + 3499 => x"b9", + 3500 => x"08", + 3501 => x"5c", + 3502 => x"73", + 3503 => x"38", + 3504 => x"1a", + 3505 => x"55", + 3506 => x"38", + 3507 => x"73", + 3508 => x"38", + 3509 => x"76", + 3510 => x"74", + 3511 => x"33", + 3512 => x"05", + 3513 => x"15", + 3514 => x"ba", + 3515 => x"05", + 3516 => x"ff", + 3517 => x"06", + 3518 => x"57", + 3519 => x"18", + 3520 => x"54", + 3521 => x"70", + 3522 => x"34", + 3523 => x"ee", + 3524 => x"34", + 3525 => x"88", + 3526 => x"0d", + 3527 => x"0d", + 3528 => x"3d", + 3529 => x"71", + 3530 => x"ec", + 3531 => x"ca", + 3532 => x"91", + 3533 => x"82", + 3534 => x"15", + 3535 => x"82", + 3536 => x"15", + 3537 => x"76", + 3538 => x"90", + 3539 => x"81", + 3540 => x"06", + 3541 => x"72", + 3542 => x"56", + 3543 => x"54", + 3544 => x"17", + 3545 => x"78", + 3546 => x"38", + 3547 => x"22", + 3548 => x"59", + 3549 => x"78", + 3550 => x"76", + 3551 => x"51", + 3552 => x"3f", + 3553 => x"08", + 3554 => x"54", + 3555 => x"53", + 3556 => x"3f", + 3557 => x"08", + 3558 => x"38", + 3559 => x"75", + 3560 => x"18", + 3561 => x"31", + 3562 => x"57", + 3563 => x"b1", + 3564 => x"08", + 3565 => x"38", + 3566 => x"51", + 3567 => x"91", + 3568 => x"54", + 3569 => x"08", + 3570 => x"9a", + 3571 => x"88", + 3572 => x"81", + 3573 => x"ca", + 3574 => x"16", + 3575 => x"16", + 3576 => x"2e", + 3577 => x"76", + 3578 => x"dc", + 3579 => x"31", + 3580 => x"18", + 3581 => x"90", + 3582 => x"81", + 3583 => x"06", + 3584 => x"56", + 3585 => x"9a", + 3586 => x"74", + 3587 => x"3f", + 3588 => x"08", + 3589 => x"88", + 3590 => x"91", + 3591 => x"56", + 3592 => x"52", + 3593 => x"84", + 3594 => x"88", + 3595 => x"ff", + 3596 => x"81", + 3597 => x"38", + 3598 => x"98", + 3599 => x"a6", + 3600 => x"16", + 3601 => x"39", + 3602 => x"16", + 3603 => x"75", + 3604 => x"53", + 3605 => x"aa", + 3606 => x"79", + 3607 => x"3f", + 3608 => x"08", + 3609 => x"0b", + 3610 => x"82", + 3611 => x"39", + 3612 => x"16", + 3613 => x"bb", + 3614 => x"2a", + 3615 => x"08", + 3616 => x"15", + 3617 => x"15", + 3618 => x"90", + 3619 => x"16", + 3620 => x"33", + 3621 => x"53", + 3622 => x"34", + 3623 => x"06", + 3624 => x"2e", + 3625 => x"9c", + 3626 => x"85", + 3627 => x"16", + 3628 => x"72", + 3629 => x"0c", + 3630 => x"04", + 3631 => x"79", + 3632 => x"75", + 3633 => x"8a", + 3634 => x"89", + 3635 => x"52", + 3636 => x"05", + 3637 => x"3f", + 3638 => x"08", + 3639 => x"88", + 3640 => x"38", + 3641 => x"7a", + 3642 => x"d8", + 3643 => x"ca", + 3644 => x"91", + 3645 => x"80", + 3646 => x"16", + 3647 => x"2b", + 3648 => x"74", + 3649 => x"86", + 3650 => x"84", + 3651 => x"06", + 3652 => x"73", + 3653 => x"38", + 3654 => x"52", + 3655 => x"da", + 3656 => x"88", + 3657 => x"0c", + 3658 => x"14", + 3659 => x"23", + 3660 => x"51", + 3661 => x"91", + 3662 => x"55", + 3663 => x"09", + 3664 => x"38", + 3665 => x"39", + 3666 => x"84", + 3667 => x"0c", + 3668 => x"91", + 3669 => x"89", + 3670 => x"fc", + 3671 => x"87", + 3672 => x"53", + 3673 => x"e7", + 3674 => x"ca", + 3675 => x"38", + 3676 => x"08", + 3677 => x"3d", + 3678 => x"3d", + 3679 => x"89", + 3680 => x"54", + 3681 => x"54", + 3682 => x"91", + 3683 => x"53", + 3684 => x"08", + 3685 => x"74", + 3686 => x"ca", + 3687 => x"73", + 3688 => x"3f", + 3689 => x"08", + 3690 => x"39", + 3691 => x"08", + 3692 => x"d3", + 3693 => x"ca", + 3694 => x"91", + 3695 => x"84", + 3696 => x"06", + 3697 => x"53", + 3698 => x"ca", + 3699 => x"38", + 3700 => x"51", + 3701 => x"72", + 3702 => x"cf", + 3703 => x"ca", + 3704 => x"32", + 3705 => x"72", + 3706 => x"70", + 3707 => x"08", + 3708 => x"54", + 3709 => x"ca", + 3710 => x"3d", + 3711 => x"3d", + 3712 => x"80", + 3713 => x"70", + 3714 => x"52", + 3715 => x"3f", + 3716 => x"08", + 3717 => x"88", + 3718 => x"64", + 3719 => x"d6", + 3720 => x"ca", + 3721 => x"91", + 3722 => x"a0", + 3723 => x"cb", + 3724 => x"98", + 3725 => x"73", + 3726 => x"38", + 3727 => x"39", + 3728 => x"88", + 3729 => x"75", + 3730 => x"3f", + 3731 => x"88", + 3732 => x"0d", + 3733 => x"0d", + 3734 => x"5c", + 3735 => x"3d", + 3736 => x"93", + 3737 => x"d6", + 3738 => x"88", + 3739 => x"ca", + 3740 => x"80", + 3741 => x"0c", + 3742 => x"11", + 3743 => x"90", + 3744 => x"56", + 3745 => x"74", + 3746 => x"75", + 3747 => x"e4", + 3748 => x"81", + 3749 => x"5b", + 3750 => x"91", + 3751 => x"75", + 3752 => x"73", + 3753 => x"81", + 3754 => x"82", + 3755 => x"76", + 3756 => x"f0", + 3757 => x"f4", + 3758 => x"88", + 3759 => x"d1", + 3760 => x"88", + 3761 => x"ce", + 3762 => x"88", + 3763 => x"91", + 3764 => x"07", + 3765 => x"05", + 3766 => x"53", + 3767 => x"98", + 3768 => x"26", + 3769 => x"f9", + 3770 => x"08", + 3771 => x"08", + 3772 => x"98", + 3773 => x"81", + 3774 => x"58", + 3775 => x"3f", + 3776 => x"08", + 3777 => x"88", + 3778 => x"38", + 3779 => x"77", + 3780 => x"5d", + 3781 => x"74", + 3782 => x"81", + 3783 => x"b4", + 3784 => x"bb", + 3785 => x"ca", + 3786 => x"ff", + 3787 => x"30", + 3788 => x"1b", + 3789 => x"5b", + 3790 => x"39", + 3791 => x"ff", + 3792 => x"91", + 3793 => x"f0", + 3794 => x"30", + 3795 => x"1b", + 3796 => x"5b", + 3797 => x"83", + 3798 => x"58", + 3799 => x"92", + 3800 => x"0c", + 3801 => x"12", + 3802 => x"33", + 3803 => x"54", + 3804 => x"34", + 3805 => x"88", + 3806 => x"0d", + 3807 => x"0d", + 3808 => x"fc", + 3809 => x"52", + 3810 => x"3f", + 3811 => x"08", + 3812 => x"88", + 3813 => x"38", + 3814 => x"56", + 3815 => x"38", + 3816 => x"70", + 3817 => x"81", + 3818 => x"55", + 3819 => x"80", + 3820 => x"38", + 3821 => x"54", + 3822 => x"08", + 3823 => x"38", + 3824 => x"91", + 3825 => x"53", + 3826 => x"52", + 3827 => x"8c", + 3828 => x"88", + 3829 => x"19", + 3830 => x"c9", + 3831 => x"08", + 3832 => x"ff", + 3833 => x"91", + 3834 => x"ff", + 3835 => x"06", + 3836 => x"56", + 3837 => x"08", + 3838 => x"81", + 3839 => x"82", + 3840 => x"75", + 3841 => x"54", + 3842 => x"08", + 3843 => x"27", + 3844 => x"17", + 3845 => x"ca", + 3846 => x"76", + 3847 => x"3f", + 3848 => x"08", + 3849 => x"08", + 3850 => x"90", + 3851 => x"c0", + 3852 => x"90", + 3853 => x"80", + 3854 => x"75", + 3855 => x"75", + 3856 => x"ca", + 3857 => x"3d", + 3858 => x"3d", + 3859 => x"a0", + 3860 => x"05", + 3861 => x"51", + 3862 => x"91", + 3863 => x"55", + 3864 => x"08", + 3865 => x"78", + 3866 => x"08", + 3867 => x"70", + 3868 => x"ae", + 3869 => x"88", + 3870 => x"ca", + 3871 => x"db", + 3872 => x"fb", + 3873 => x"85", + 3874 => x"06", + 3875 => x"86", + 3876 => x"c7", + 3877 => x"2b", + 3878 => x"24", + 3879 => x"02", + 3880 => x"33", + 3881 => x"58", + 3882 => x"76", + 3883 => x"6b", + 3884 => x"cc", + 3885 => x"ca", + 3886 => x"84", + 3887 => x"06", + 3888 => x"73", + 3889 => x"d4", + 3890 => x"91", + 3891 => x"94", + 3892 => x"81", + 3893 => x"5a", + 3894 => x"08", + 3895 => x"8a", + 3896 => x"54", + 3897 => x"91", + 3898 => x"55", + 3899 => x"08", + 3900 => x"91", + 3901 => x"52", + 3902 => x"e5", + 3903 => x"88", + 3904 => x"ca", + 3905 => x"38", + 3906 => x"cf", + 3907 => x"88", + 3908 => x"88", + 3909 => x"88", + 3910 => x"38", + 3911 => x"c2", + 3912 => x"88", + 3913 => x"88", + 3914 => x"91", + 3915 => x"07", + 3916 => x"55", + 3917 => x"2e", + 3918 => x"80", + 3919 => x"80", + 3920 => x"77", + 3921 => x"3f", + 3922 => x"08", + 3923 => x"38", + 3924 => x"ba", + 3925 => x"ca", + 3926 => x"74", + 3927 => x"0c", + 3928 => x"04", + 3929 => x"82", + 3930 => x"c0", + 3931 => x"3d", + 3932 => x"3f", + 3933 => x"08", + 3934 => x"88", + 3935 => x"38", + 3936 => x"52", + 3937 => x"52", + 3938 => x"3f", + 3939 => x"08", + 3940 => x"88", + 3941 => x"88", + 3942 => x"39", + 3943 => x"08", + 3944 => x"81", + 3945 => x"38", + 3946 => x"05", + 3947 => x"2a", + 3948 => x"55", + 3949 => x"81", + 3950 => x"5a", + 3951 => x"3d", + 3952 => x"c1", + 3953 => x"ca", + 3954 => x"55", + 3955 => x"88", + 3956 => x"87", + 3957 => x"88", + 3958 => x"09", + 3959 => x"38", + 3960 => x"ca", + 3961 => x"2e", + 3962 => x"86", + 3963 => x"81", + 3964 => x"81", + 3965 => x"ca", + 3966 => x"78", + 3967 => x"3f", + 3968 => x"08", + 3969 => x"88", + 3970 => x"38", + 3971 => x"52", + 3972 => x"ff", + 3973 => x"78", + 3974 => x"b4", + 3975 => x"54", + 3976 => x"15", + 3977 => x"b2", + 3978 => x"ca", + 3979 => x"b6", + 3980 => x"53", + 3981 => x"53", + 3982 => x"3f", + 3983 => x"b4", + 3984 => x"d4", + 3985 => x"b6", + 3986 => x"54", + 3987 => x"d5", + 3988 => x"53", + 3989 => x"11", + 3990 => x"d7", + 3991 => x"81", + 3992 => x"34", + 3993 => x"a4", + 3994 => x"88", + 3995 => x"ca", + 3996 => x"38", + 3997 => x"0a", + 3998 => x"05", + 3999 => x"d0", + 4000 => x"64", + 4001 => x"c9", + 4002 => x"54", + 4003 => x"15", + 4004 => x"81", + 4005 => x"34", + 4006 => x"b8", + 4007 => x"ca", + 4008 => x"8b", + 4009 => x"75", + 4010 => x"ff", + 4011 => x"73", + 4012 => x"0c", + 4013 => x"04", + 4014 => x"a9", + 4015 => x"51", + 4016 => x"82", + 4017 => x"ff", + 4018 => x"a9", + 4019 => x"ee", + 4020 => x"88", + 4021 => x"ca", + 4022 => x"d3", + 4023 => x"a9", + 4024 => x"9d", + 4025 => x"58", + 4026 => x"91", + 4027 => x"55", + 4028 => x"08", + 4029 => x"02", + 4030 => x"33", + 4031 => x"54", + 4032 => x"82", + 4033 => x"53", + 4034 => x"52", + 4035 => x"88", + 4036 => x"b4", + 4037 => x"53", + 4038 => x"3d", + 4039 => x"ff", + 4040 => x"aa", + 4041 => x"73", + 4042 => x"3f", + 4043 => x"08", + 4044 => x"88", + 4045 => x"63", + 4046 => x"81", + 4047 => x"65", + 4048 => x"2e", + 4049 => x"55", + 4050 => x"91", + 4051 => x"84", + 4052 => x"06", + 4053 => x"73", + 4054 => x"3f", + 4055 => x"08", + 4056 => x"88", + 4057 => x"38", + 4058 => x"53", + 4059 => x"95", + 4060 => x"16", + 4061 => x"87", + 4062 => x"05", + 4063 => x"34", + 4064 => x"70", + 4065 => x"81", + 4066 => x"55", + 4067 => x"74", + 4068 => x"73", + 4069 => x"78", + 4070 => x"83", + 4071 => x"16", + 4072 => x"2a", + 4073 => x"51", + 4074 => x"80", + 4075 => x"38", + 4076 => x"80", + 4077 => x"52", + 4078 => x"be", + 4079 => x"88", + 4080 => x"51", + 4081 => x"3f", + 4082 => x"ca", + 4083 => x"2e", + 4084 => x"91", + 4085 => x"52", + 4086 => x"b5", + 4087 => x"ca", + 4088 => x"80", + 4089 => x"58", + 4090 => x"88", + 4091 => x"38", + 4092 => x"54", + 4093 => x"09", + 4094 => x"38", + 4095 => x"52", + 4096 => x"af", + 4097 => x"81", + 4098 => x"34", + 4099 => x"ca", + 4100 => x"38", + 4101 => x"ca", + 4102 => x"88", + 4103 => x"ca", + 4104 => x"38", + 4105 => x"b5", + 4106 => x"ca", + 4107 => x"74", + 4108 => x"0c", + 4109 => x"04", + 4110 => x"02", + 4111 => x"33", + 4112 => x"80", + 4113 => x"57", + 4114 => x"95", + 4115 => x"52", + 4116 => x"d2", + 4117 => x"ca", + 4118 => x"91", + 4119 => x"80", + 4120 => x"5a", + 4121 => x"3d", + 4122 => x"c9", + 4123 => x"ca", + 4124 => x"91", + 4125 => x"b8", + 4126 => x"cf", + 4127 => x"a0", + 4128 => x"55", + 4129 => x"75", + 4130 => x"71", + 4131 => x"33", + 4132 => x"74", + 4133 => x"57", + 4134 => x"8b", + 4135 => x"54", + 4136 => x"15", + 4137 => x"ff", + 4138 => x"91", + 4139 => x"55", + 4140 => x"88", + 4141 => x"0d", + 4142 => x"0d", + 4143 => x"53", + 4144 => x"05", + 4145 => x"51", + 4146 => x"91", + 4147 => x"55", + 4148 => x"08", + 4149 => x"76", + 4150 => x"93", + 4151 => x"51", + 4152 => x"91", + 4153 => x"55", + 4154 => x"08", + 4155 => x"80", + 4156 => x"81", + 4157 => x"86", + 4158 => x"38", + 4159 => x"86", + 4160 => x"90", + 4161 => x"54", + 4162 => x"ff", + 4163 => x"76", + 4164 => x"83", + 4165 => x"51", + 4166 => x"3f", + 4167 => x"08", + 4168 => x"ca", + 4169 => x"3d", + 4170 => x"3d", + 4171 => x"5c", + 4172 => x"98", + 4173 => x"52", + 4174 => x"d1", + 4175 => x"ca", + 4176 => x"ca", + 4177 => x"70", + 4178 => x"08", + 4179 => x"51", + 4180 => x"80", + 4181 => x"38", + 4182 => x"06", + 4183 => x"80", + 4184 => x"38", + 4185 => x"5f", + 4186 => x"3d", + 4187 => x"ff", + 4188 => x"91", + 4189 => x"57", + 4190 => x"08", + 4191 => x"74", + 4192 => x"c3", + 4193 => x"ca", + 4194 => x"91", + 4195 => x"bf", + 4196 => x"88", + 4197 => x"88", + 4198 => x"59", + 4199 => x"81", + 4200 => x"56", + 4201 => x"33", + 4202 => x"16", + 4203 => x"27", + 4204 => x"56", + 4205 => x"80", + 4206 => x"80", + 4207 => x"ff", + 4208 => x"70", + 4209 => x"56", + 4210 => x"e8", + 4211 => x"76", + 4212 => x"81", + 4213 => x"80", + 4214 => x"57", + 4215 => x"78", + 4216 => x"51", + 4217 => x"2e", + 4218 => x"73", + 4219 => x"38", + 4220 => x"08", + 4221 => x"b1", + 4222 => x"ca", + 4223 => x"91", + 4224 => x"a7", + 4225 => x"33", + 4226 => x"c3", + 4227 => x"2e", + 4228 => x"e4", + 4229 => x"2e", + 4230 => x"56", + 4231 => x"05", + 4232 => x"e3", + 4233 => x"88", + 4234 => x"76", + 4235 => x"0c", + 4236 => x"04", + 4237 => x"82", + 4238 => x"ff", + 4239 => x"9d", + 4240 => x"fa", + 4241 => x"88", + 4242 => x"88", + 4243 => x"91", + 4244 => x"83", + 4245 => x"53", + 4246 => x"3d", + 4247 => x"ff", + 4248 => x"73", + 4249 => x"70", + 4250 => x"52", + 4251 => x"9f", + 4252 => x"bc", + 4253 => x"74", + 4254 => x"6d", + 4255 => x"70", + 4256 => x"af", + 4257 => x"ca", + 4258 => x"2e", + 4259 => x"70", + 4260 => x"57", + 4261 => x"fd", + 4262 => x"88", + 4263 => x"8d", + 4264 => x"2b", + 4265 => x"81", + 4266 => x"86", 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x"08", + 4326 => x"81", + 4327 => x"38", + 4328 => x"74", + 4329 => x"38", + 4330 => x"51", + 4331 => x"3f", + 4332 => x"08", + 4333 => x"88", + 4334 => x"a0", + 4335 => x"88", + 4336 => x"51", + 4337 => x"3f", + 4338 => x"0b", + 4339 => x"8b", + 4340 => x"67", + 4341 => x"a7", + 4342 => x"81", + 4343 => x"34", + 4344 => x"ad", + 4345 => x"ca", + 4346 => x"73", + 4347 => x"ca", + 4348 => x"3d", + 4349 => x"3d", + 4350 => x"02", + 4351 => x"cb", + 4352 => x"3d", + 4353 => x"72", + 4354 => x"5a", + 4355 => x"91", + 4356 => x"58", + 4357 => x"08", + 4358 => x"91", + 4359 => x"77", + 4360 => x"7c", + 4361 => x"38", + 4362 => x"59", + 4363 => x"90", + 4364 => x"81", + 4365 => x"06", + 4366 => x"73", + 4367 => x"54", + 4368 => x"82", + 4369 => x"39", + 4370 => x"8b", + 4371 => x"11", + 4372 => x"2b", + 4373 => x"54", + 4374 => x"ff", + 4375 => x"ff", + 4376 => x"70", + 4377 => x"07", + 4378 => x"ca", + 4379 => x"8c", + 4380 => x"40", + 4381 => x"55", + 4382 => x"88", + 4383 => x"08", + 4384 => x"38", + 4385 => x"77", + 4386 => x"56", + 4387 => x"51", + 4388 => x"3f", + 4389 => x"55", + 4390 => x"08", + 4391 => x"38", + 4392 => x"ca", + 4393 => x"2e", + 4394 => x"91", + 4395 => x"ff", + 4396 => x"38", + 4397 => x"08", + 4398 => x"16", + 4399 => x"2e", + 4400 => x"87", + 4401 => x"74", + 4402 => x"74", + 4403 => x"81", + 4404 => x"38", + 4405 => x"ff", + 4406 => x"2e", + 4407 => x"7b", + 4408 => x"80", + 4409 => x"81", + 4410 => x"81", + 4411 => x"06", + 4412 => x"56", + 4413 => x"52", + 4414 => x"af", + 4415 => x"ca", + 4416 => x"91", + 4417 => x"80", + 4418 => x"81", + 4419 => x"56", + 4420 => x"d3", + 4421 => x"ff", + 4422 => x"7c", + 4423 => x"55", + 4424 => x"b3", + 4425 => x"1b", + 4426 => x"1b", + 4427 => x"33", + 4428 => x"54", + 4429 => x"34", + 4430 => x"fe", + 4431 => x"08", + 4432 => x"74", + 4433 => x"75", + 4434 => x"16", + 4435 => x"33", + 4436 => x"73", + 4437 => x"77", + 4438 => x"ca", + 4439 => x"3d", + 4440 => x"3d", + 4441 => x"02", + 4442 => x"eb", + 4443 => x"3d", + 4444 => x"59", + 4445 => x"8b", + 4446 => x"91", + 4447 => x"24", + 4448 => x"91", + 4449 => x"84", + 4450 => x"a4", + 4451 => x"51", + 4452 => x"2e", + 4453 => x"75", + 4454 => x"88", + 4455 => x"06", + 4456 => x"7e", + 4457 => x"d0", + 4458 => x"88", + 4459 => x"06", + 4460 => x"56", + 4461 => x"74", + 4462 => x"76", + 4463 => x"81", + 4464 => x"8a", + 4465 => x"b2", + 4466 => x"fc", + 4467 => x"52", + 4468 => x"a4", + 4469 => x"ca", + 4470 => x"38", + 4471 => x"80", + 4472 => x"74", + 4473 => x"26", + 4474 => x"15", + 4475 => x"74", + 4476 => x"38", + 4477 => x"80", + 4478 => x"84", + 4479 => x"92", + 4480 => x"80", + 4481 => x"38", + 4482 => x"06", + 4483 => x"2e", + 4484 => x"56", + 4485 => x"78", + 4486 => x"89", + 4487 => x"2b", + 4488 => x"43", + 4489 => x"38", + 4490 => x"30", + 4491 => x"77", + 4492 => x"91", + 4493 => x"c2", + 4494 => x"f8", + 4495 => x"52", + 4496 => x"a4", + 4497 => x"56", + 4498 => x"08", + 4499 => x"77", + 4500 => x"77", + 4501 => x"88", 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x"2e", + 4561 => x"75", + 4562 => x"79", + 4563 => x"fe", + 4564 => x"91", + 4565 => x"10", + 4566 => x"91", + 4567 => x"9f", + 4568 => x"38", + 4569 => x"ca", + 4570 => x"91", + 4571 => x"05", + 4572 => x"2a", + 4573 => x"56", + 4574 => x"17", + 4575 => x"81", + 4576 => x"60", + 4577 => x"65", + 4578 => x"12", + 4579 => x"30", + 4580 => x"74", + 4581 => x"59", + 4582 => x"7d", + 4583 => x"81", + 4584 => x"76", + 4585 => x"41", + 4586 => x"76", + 4587 => x"90", + 4588 => x"62", + 4589 => x"51", + 4590 => x"26", + 4591 => x"75", + 4592 => x"31", + 4593 => x"65", + 4594 => x"fe", + 4595 => x"91", + 4596 => x"58", + 4597 => x"09", + 4598 => x"38", + 4599 => x"08", + 4600 => x"26", + 4601 => x"78", + 4602 => x"79", + 4603 => x"78", + 4604 => x"86", + 4605 => x"82", + 4606 => x"06", + 4607 => x"83", + 4608 => x"91", + 4609 => x"27", + 4610 => x"8f", + 4611 => x"55", + 4612 => x"26", + 4613 => x"59", + 4614 => x"62", + 4615 => x"74", + 4616 => x"38", + 4617 => x"88", + 4618 => x"88", + 4619 => x"26", + 4620 => x"86", + 4621 => x"1a", + 4622 => x"79", + 4623 => x"38", + 4624 => x"80", + 4625 => x"2e", + 4626 => x"83", + 4627 => x"9f", + 4628 => x"8b", + 4629 => x"06", + 4630 => x"74", + 4631 => x"84", + 4632 => x"52", + 4633 => x"a2", + 4634 => x"53", + 4635 => x"52", + 4636 => x"a2", + 4637 => x"80", + 4638 => x"51", + 4639 => x"3f", + 4640 => x"34", + 4641 => x"ff", + 4642 => x"1b", + 4643 => x"a2", + 4644 => x"90", + 4645 => x"83", + 4646 => x"70", + 4647 => x"80", + 4648 => x"55", + 4649 => x"ff", + 4650 => x"66", + 4651 => x"ff", + 4652 => x"38", + 4653 => x"ff", + 4654 => x"1b", + 4655 => x"f2", + 4656 => x"74", + 4657 => x"51", + 4658 => x"3f", + 4659 => x"1c", + 4660 => x"98", + 4661 => x"a0", + 4662 => x"ff", + 4663 => x"51", + 4664 => x"3f", + 4665 => x"1b", + 4666 => x"e4", + 4667 => x"2e", + 4668 => x"80", + 4669 => x"88", + 4670 => x"80", + 4671 => x"ff", + 4672 => x"7c", + 4673 => x"51", + 4674 => x"3f", + 4675 => x"1b", + 4676 => x"bc", + 4677 => x"b0", + 4678 => x"a0", + 4679 => x"52", + 4680 => x"ff", + 4681 => x"ff", + 4682 => x"c0", + 4683 => x"0b", + 4684 => x"34", + 4685 => x"b8", + 4686 => x"c7", + 4687 => x"39", + 4688 => x"0a", + 4689 => x"51", + 4690 => x"3f", + 4691 => x"ff", + 4692 => x"1b", + 4693 => x"da", + 4694 => x"0b", + 4695 => x"a9", + 4696 => x"34", + 4697 => x"b8", + 4698 => x"1b", + 4699 => x"8f", + 4700 => x"d5", + 4701 => x"1b", + 4702 => x"ff", + 4703 => x"81", + 4704 => x"7a", + 4705 => x"ff", + 4706 => x"81", + 4707 => x"88", + 4708 => x"38", + 4709 => x"09", + 4710 => x"ee", + 4711 => x"60", + 4712 => x"7a", + 4713 => x"ff", + 4714 => x"84", + 4715 => x"52", + 4716 => x"9f", + 4717 => x"8b", + 4718 => x"52", + 4719 => x"9f", + 4720 => x"8a", + 4721 => x"52", + 4722 => x"51", + 4723 => x"3f", + 4724 => x"83", + 4725 => x"ff", + 4726 => x"82", + 4727 => x"1b", + 4728 => x"ec", + 4729 => x"d5", + 4730 => x"ff", + 4731 => x"75", + 4732 => x"05", + 4733 => x"7e", + 4734 => x"e5", + 4735 => x"60", + 4736 => x"52", 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x"c2", + 4796 => x"1b", + 4797 => x"34", + 4798 => x"16", + 4799 => x"82", + 4800 => x"83", + 4801 => x"84", + 4802 => x"67", + 4803 => x"fd", + 4804 => x"51", + 4805 => x"3f", + 4806 => x"16", + 4807 => x"88", + 4808 => x"bf", + 4809 => x"86", + 4810 => x"ca", + 4811 => x"16", + 4812 => x"83", + 4813 => x"ff", + 4814 => x"66", + 4815 => x"1b", + 4816 => x"8c", + 4817 => x"77", + 4818 => x"7e", + 4819 => x"91", + 4820 => x"91", + 4821 => x"a2", + 4822 => x"80", + 4823 => x"ff", + 4824 => x"81", + 4825 => x"88", + 4826 => x"89", + 4827 => x"8a", + 4828 => x"86", + 4829 => x"88", + 4830 => x"91", + 4831 => x"99", + 4832 => x"ff", + 4833 => x"52", + 4834 => x"81", + 4835 => x"84", + 4836 => x"9c", + 4837 => x"08", + 4838 => x"d8", + 4839 => x"39", + 4840 => x"51", + 4841 => x"91", + 4842 => x"80", + 4843 => x"bc", + 4844 => x"eb", + 4845 => x"9c", + 4846 => x"39", + 4847 => x"51", + 4848 => x"91", + 4849 => x"80", + 4850 => x"bc", + 4851 => x"cf", + 4852 => x"e8", + 4853 => x"39", + 4854 => x"51", + 4855 => x"91", + 4856 => x"bb", + 4857 => x"b4", + 4858 => x"91", + 4859 => x"af", + 4860 => x"f4", + 4861 => x"91", + 4862 => x"a3", + 4863 => x"a8", + 4864 => x"91", + 4865 => x"97", + 4866 => x"d4", + 4867 => x"91", + 4868 => x"8b", + 4869 => x"84", + 4870 => x"91", + 4871 => x"ff", + 4872 => x"83", + 4873 => x"fb", + 4874 => x"79", + 4875 => x"87", + 4876 => x"38", + 4877 => x"87", + 4878 => x"91", + 4879 => x"52", + 4880 => x"f2", + 4881 => x"ca", + 4882 => x"75", + 4883 => x"98", + 4884 => x"88", + 4885 => x"53", + 4886 => x"bf", + 4887 => x"8d", + 4888 => x"3d", + 4889 => x"3d", + 4890 => x"61", + 4891 => x"80", + 4892 => x"73", + 4893 => x"5f", + 4894 => x"5c", + 4895 => x"52", + 4896 => x"51", + 4897 => x"3f", + 4898 => x"51", + 4899 => x"3f", + 4900 => x"77", + 4901 => x"38", + 4902 => x"89", + 4903 => x"2e", + 4904 => x"c6", + 4905 => x"53", + 4906 => x"8e", + 4907 => x"52", + 4908 => x"51", + 4909 => x"3f", + 4910 => x"bf", + 4911 => x"86", + 4912 => x"15", + 4913 => x"39", + 4914 => x"72", + 4915 => x"38", + 4916 => x"91", + 4917 => x"ff", + 4918 => x"89", + 4919 => x"d8", + 4920 => x"b9", + 4921 => x"55", + 4922 => x"16", + 4923 => x"27", + 4924 => x"33", + 4925 => x"e4", + 4926 => x"85", + 4927 => x"91", + 4928 => x"ff", + 4929 => x"81", + 4930 => x"51", + 4931 => x"3f", + 4932 => x"91", + 4933 => x"ff", + 4934 => x"80", + 4935 => x"27", + 4936 => x"16", + 4937 => x"72", + 4938 => x"53", + 4939 => x"90", + 4940 => x"2e", + 4941 => x"80", + 4942 => x"38", + 4943 => x"39", + 4944 => x"f9", + 4945 => x"15", + 4946 => x"91", + 4947 => x"ff", + 4948 => x"76", + 4949 => x"5a", + 4950 => x"92", + 4951 => x"88", + 4952 => x"70", + 4953 => x"55", + 4954 => x"09", + 4955 => x"38", + 4956 => x"3f", + 4957 => x"08", + 4958 => x"98", + 4959 => x"32", + 4960 => x"72", + 4961 => x"51", + 4962 => x"55", + 4963 => x"8c", + 4964 => x"38", + 4965 => x"09", + 4966 => x"38", + 4967 => x"39", + 4968 => x"72", + 4969 => x"d6", + 4970 => x"72", + 4971 => x"0c", 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x"04", + 5031 => x"88", + 5032 => x"0d", + 5033 => x"0d", + 5034 => x"33", + 5035 => x"53", + 5036 => x"52", + 5037 => x"c9", + 5038 => x"88", + 5039 => x"80", + 5040 => x"c0", + 5041 => x"c0", + 5042 => x"c7", + 5043 => x"91", + 5044 => x"ff", + 5045 => x"74", + 5046 => x"38", + 5047 => x"3f", + 5048 => x"04", + 5049 => x"87", + 5050 => x"08", + 5051 => x"fd", + 5052 => x"fe", + 5053 => x"91", + 5054 => x"fe", + 5055 => x"80", + 5056 => x"fe", + 5057 => x"2a", + 5058 => x"51", + 5059 => x"2e", + 5060 => x"51", + 5061 => x"3f", + 5062 => x"51", + 5063 => x"3f", + 5064 => x"f5", + 5065 => x"82", + 5066 => x"06", + 5067 => x"80", + 5068 => x"81", + 5069 => x"ca", + 5070 => x"f4", + 5071 => x"c2", + 5072 => x"fe", + 5073 => x"72", + 5074 => x"81", + 5075 => x"71", + 5076 => x"38", + 5077 => x"f5", + 5078 => x"c1", + 5079 => x"f7", + 5080 => x"51", + 5081 => x"3f", + 5082 => x"70", + 5083 => x"52", + 5084 => x"95", + 5085 => x"fe", + 5086 => x"91", + 5087 => x"fe", + 5088 => x"80", + 5089 => x"fa", + 5090 => x"2a", + 5091 => x"51", + 5092 => x"2e", + 5093 => x"51", + 5094 => x"3f", + 5095 => x"51", + 5096 => x"3f", + 5097 => x"f4", + 5098 => x"86", + 5099 => x"06", + 5100 => x"80", + 5101 => x"81", + 5102 => x"c6", + 5103 => x"c0", + 5104 => x"be", + 5105 => x"fe", + 5106 => x"72", + 5107 => x"81", + 5108 => x"71", + 5109 => x"38", + 5110 => x"f4", + 5111 => x"c1", + 5112 => x"f6", + 5113 => x"51", + 5114 => x"3f", + 5115 => x"70", + 5116 => x"52", + 5117 => x"95", + 5118 => x"fe", + 5119 => x"91", + 5120 => x"fe", + 5121 => x"80", + 5122 => x"f6", + 5123 => x"a6", + 5124 => x"0d", + 5125 => x"0d", + 5126 => x"70", + 5127 => x"73", + 5128 => x"f0", + 5129 => x"73", + 5130 => x"15", + 5131 => x"e4", + 5132 => x"54", + 5133 => x"70", + 5134 => x"57", + 5135 => x"a0", + 5136 => x"81", + 5137 => x"2e", + 5138 => x"e5", + 5139 => x"ff", + 5140 => x"a0", + 5141 => x"06", + 5142 => x"74", + 5143 => x"56", + 5144 => x"75", + 5145 => x"c7", + 5146 => x"08", + 5147 => x"52", + 5148 => x"fd", + 5149 => x"88", + 5150 => x"84", + 5151 => x"72", + 5152 => x"a3", + 5153 => x"70", + 5154 => x"57", + 5155 => x"27", + 5156 => x"53", + 5157 => x"88", + 5158 => x"0d", + 5159 => x"0d", + 5160 => x"91", + 5161 => x"5e", + 5162 => x"7b", + 5163 => x"c8", + 5164 => x"88", + 5165 => x"06", + 5166 => x"2e", + 5167 => x"a2", + 5168 => x"a8", + 5169 => x"70", + 5170 => x"84", + 5171 => x"53", + 5172 => x"cb", + 5173 => x"b9", + 5174 => x"ca", + 5175 => x"2e", + 5176 => x"c2", + 5177 => x"d7", + 5178 => x"5e", + 5179 => x"e4", + 5180 => x"a9", + 5181 => x"70", + 5182 => x"f8", + 5183 => x"79", + 5184 => x"dc", + 5185 => x"52", + 5186 => x"84", + 5187 => x"3d", + 5188 => x"51", + 5189 => x"91", + 5190 => x"90", + 5191 => x"2c", + 5192 => x"80", + 5193 => x"da", + 5194 => x"c2", + 5195 => x"38", + 5196 => x"83", + 5197 => x"b0", + 5198 => x"78", + 5199 => x"a1", + 5200 => x"24", + 5201 => x"80", + 5202 => x"38", + 5203 => x"81", + 5204 => x"f1", + 5205 => x"2e", + 5206 => x"78", + 5207 => x"9c", + 5208 => x"39", + 5209 => x"85", + 5210 => x"bf", + 5211 => x"78", + 5212 => x"98", + 5213 => x"2e", + 5214 => x"8e", + 5215 => x"80", + 5216 => x"d9", + 5217 => x"c1", + 5218 => x"38", + 5219 => x"78", + 5220 => x"8d", + 5221 => x"80", + 5222 => x"38", + 5223 => x"2e", + 5224 => x"78", + 5225 => x"92", + 5226 => x"c3", + 5227 => x"38", + 5228 => x"2e", + 5229 => x"8e", + 5230 => x"80", + 5231 => x"c0", + 5232 => x"d5", + 5233 => x"38", + 5234 => x"78", + 5235 => x"8d", + 5236 => x"81", + 5237 => x"38", + 5238 => x"2e", + 5239 => x"78", + 5240 => x"8d", + 5241 => x"dd", + 5242 => x"85", + 5243 => x"38", + 5244 => x"2e", + 5245 => x"8d", + 5246 => x"3d", + 5247 => x"53", + 5248 => x"51", + 5249 => x"3f", + 5250 => x"08", + 5251 => x"c2", + 5252 => x"ab", + 5253 => x"fe", + 5254 => x"fe", + 5255 => x"ff", + 5256 => x"91", + 5257 => x"80", + 5258 => x"81", + 5259 => x"38", + 5260 => x"80", + 5261 => x"52", + 5262 => x"05", + 5263 => x"87", + 5264 => x"ca", + 5265 => x"ff", + 5266 => x"8e", + 5267 => x"f8", + 5268 => x"c9", + 5269 => x"fd", + 5270 => x"c3", + 5271 => x"b6", + 5272 => x"fe", + 5273 => x"fe", + 5274 => x"ff", + 5275 => x"91", + 5276 => x"80", + 5277 => x"38", + 5278 => x"52", + 5279 => x"05", + 5280 => x"8b", + 5281 => x"ca", + 5282 => x"91", + 5283 => x"8c", + 5284 => x"3d", + 5285 => x"53", + 5286 => x"51", + 5287 => x"3f", + 5288 => x"08", + 5289 => x"38", + 5290 => x"fc", + 5291 => x"3d", + 5292 => x"53", + 5293 => x"51", + 5294 => x"3f", + 5295 => x"08", + 5296 => x"ca", + 5297 => x"63", + 5298 => x"a8", + 5299 => x"ff", + 5300 => x"02", + 5301 => x"33", + 5302 => x"63", + 5303 => x"91", + 5304 => x"51", + 5305 => x"3f", + 5306 => x"08", + 5307 => x"91", + 5308 => x"fe", + 5309 => x"81", + 5310 => x"39", + 5311 => x"f8", + 5312 => x"ea", + 5313 => x"ca", + 5314 => x"3d", + 5315 => x"52", + 5316 => x"81", + 5317 => x"91", + 5318 => x"52", + 5319 => x"94", + 5320 => x"39", + 5321 => x"f8", + 5322 => x"ea", + 5323 => x"ca", + 5324 => x"3d", + 5325 => x"52", + 5326 => x"d9", + 5327 => x"88", + 5328 => x"fe", + 5329 => x"5a", + 5330 => x"3f", + 5331 => x"08", + 5332 => x"f8", + 5333 => x"fe", + 5334 => x"91", + 5335 => x"91", + 5336 => x"80", + 5337 => x"91", + 5338 => x"81", + 5339 => x"78", + 5340 => x"7a", + 5341 => x"3f", + 5342 => x"08", + 5343 => x"ed", + 5344 => x"88", + 5345 => x"fb", + 5346 => x"39", + 5347 => x"f4", + 5348 => x"f8", + 5349 => x"80", + 5350 => x"ca", + 5351 => x"2e", + 5352 => x"b7", + 5353 => x"11", + 5354 => x"05", + 5355 => x"c6", + 5356 => x"88", + 5357 => x"fa", + 5358 => x"3d", + 5359 => x"53", + 5360 => x"51", + 5361 => x"3f", + 5362 => x"08", + 5363 => x"ca", + 5364 => x"91", + 5365 => x"fe", + 5366 => x"63", + 5367 => x"79", + 5368 => x"f2", + 5369 => x"78", + 5370 => x"05", + 5371 => x"7a", + 5372 => x"81", + 5373 => x"3d", + 5374 => x"53", + 5375 => x"51", + 5376 => x"3f", + 5377 => x"08", + 5378 => x"e1", + 5379 => x"fe", + 5380 => x"fe", + 5381 => x"fe", + 5382 => x"91", + 5383 => x"80", + 5384 => x"38", + 5385 => x"ec", + 5386 => x"f8", + 5387 => x"ff", + 5388 => x"ca", + 5389 => x"2e", + 5390 => x"91", + 5391 => x"fe", + 5392 => x"63", + 5393 => x"27", + 5394 => x"61", + 5395 => x"81", + 5396 => x"79", + 5397 => x"05", + 5398 => x"b7", + 5399 => x"11", + 5400 => x"05", + 5401 => x"8e", + 5402 => x"88", + 5403 => x"f8", + 5404 => x"3d", + 5405 => x"53", + 5406 => x"51", + 5407 => x"3f", + 5408 => x"08", + 5409 => x"e5", + 5410 => x"fe", + 5411 => x"fe", + 5412 => x"fe", + 5413 => x"91", + 5414 => x"80", + 5415 => x"38", + 5416 => x"51", + 5417 => x"3f", + 5418 => x"63", + 5419 => x"61", + 5420 => x"33", + 5421 => x"78", + 5422 => x"38", + 5423 => x"54", + 5424 => x"79", + 5425 => x"d4", + 5426 => x"b5", + 5427 => x"62", + 5428 => x"5a", + 5429 => x"c2", + 5430 => x"ba", + 5431 => x"fe", + 5432 => x"fe", + 5433 => x"fe", + 5434 => x"91", + 5435 => x"80", + 5436 => x"c7", + 5437 => x"78", + 5438 => x"38", + 5439 => x"08", + 5440 => x"91", + 5441 => x"59", + 5442 => x"88", + 5443 => x"ec", + 5444 => x"39", + 5445 => x"33", + 5446 => x"38", + 5447 => x"33", + 5448 => x"2e", + 5449 => x"c6", + 5450 => x"89", + 5451 => x"84", + 5452 => x"05", + 5453 => x"fe", + 5454 => x"fe", + 5455 => x"fe", + 5456 => x"91", + 5457 => x"80", + 5458 => x"c7", + 5459 => x"78", + 5460 => x"38", + 5461 => x"08", + 5462 => x"91", + 5463 => x"59", + 5464 => x"88", + 5465 => x"f0", + 5466 => x"39", + 5467 => x"33", + 5468 => x"38", + 5469 => x"33", + 5470 => x"2e", + 5471 => x"c6", + 5472 => x"88", + 5473 => x"84", + 5474 => x"43", + 5475 => x"ec", + 5476 => x"f8", + 5477 => x"fc", + 5478 => x"ca", + 5479 => x"2e", + 5480 => x"62", + 5481 => x"88", + 5482 => x"81", + 5483 => x"2e", + 5484 => x"80", + 5485 => x"79", + 5486 => x"38", + 5487 => x"c3", + 5488 => x"f4", + 5489 => x"55", + 5490 => x"53", + 5491 => x"51", + 5492 => x"91", + 5493 => x"84", + 5494 => x"3d", + 5495 => x"53", + 5496 => x"51", + 5497 => x"3f", + 5498 => x"08", + 5499 => x"fd", + 5500 => x"fe", + 5501 => x"fe", + 5502 => x"fe", + 5503 => x"91", + 5504 => x"80", + 5505 => x"63", + 5506 => x"cb", + 5507 => x"34", + 5508 => x"44", + 5509 => x"f0", + 5510 => x"f8", + 5511 => x"fb", + 5512 => x"ca", + 5513 => x"38", + 5514 => x"63", + 5515 => x"52", + 5516 => x"51", + 5517 => x"3f", + 5518 => x"79", + 5519 => x"9b", + 5520 => x"79", + 5521 => x"ae", + 5522 => x"38", + 5523 => x"a0", + 5524 => x"fe", + 5525 => x"fe", + 5526 => x"fe", + 5527 => x"91", + 5528 => x"80", + 5529 => x"63", + 5530 => x"cb", + 5531 => x"34", + 5532 => x"44", + 5533 => x"91", + 5534 => x"fe", + 5535 => x"ff", + 5536 => x"3d", + 5537 => x"53", + 5538 => x"51", + 5539 => x"3f", + 5540 => x"08", + 5541 => x"d5", + 5542 => x"fe", + 5543 => x"fe", + 5544 => x"fe", + 5545 => x"91", + 5546 => x"80", + 5547 => x"60", + 5548 => x"05", + 5549 => x"82", + 5550 => x"78", + 5551 => x"fe", + 5552 => x"fe", + 5553 => x"fe", + 5554 => x"91", + 5555 => x"df", + 5556 => x"39", + 5557 => x"54", + 5558 => x"a0", + 5559 => x"a1", + 5560 => x"52", + 5561 => x"f8", + 5562 => x"45", + 5563 => x"78", + 5564 => x"f9", + 5565 => x"26", + 5566 => x"84", + 5567 => x"39", + 5568 => x"e4", + 5569 => x"f8", + 5570 => x"fb", + 5571 => x"ca", + 5572 => x"2e", + 5573 => x"59", + 5574 => x"22", + 5575 => x"05", + 5576 => x"41", + 5577 => x"91", + 5578 => x"fe", + 5579 => x"ff", + 5580 => x"3d", + 5581 => x"53", + 5582 => x"51", + 5583 => x"3f", + 5584 => x"08", + 5585 => x"a5", + 5586 => x"fe", + 5587 => x"fe", + 5588 => x"fe", + 5589 => x"91", + 5590 => x"80", + 5591 => x"60", + 5592 => x"59", + 5593 => x"41", + 5594 => x"e4", + 5595 => x"f8", + 5596 => x"fa", + 5597 => x"ca", + 5598 => x"38", + 5599 => x"60", + 5600 => x"52", + 5601 => x"51", + 5602 => x"3f", + 5603 => x"79", + 5604 => x"c7", + 5605 => x"79", + 5606 => x"ae", + 5607 => x"38", + 5608 => x"a8", + 5609 => x"fe", + 5610 => x"fe", + 5611 => x"fe", + 5612 => x"91", + 5613 => x"80", + 5614 => x"7f", + 5615 => x"91", + 5616 => x"fe", + 5617 => x"60", + 5618 => x"59", + 5619 => x"41", + 5620 => x"91", + 5621 => x"fe", + 5622 => x"ff", + 5623 => x"c4", + 5624 => x"f0", + 5625 => x"51", + 5626 => x"3f", + 5627 => x"91", + 5628 => x"fe", + 5629 => x"a2", + 5630 => x"f9", + 5631 => x"39", + 5632 => x"0b", + 5633 => x"84", + 5634 => x"81", + 5635 => x"94", + 5636 => x"c4", + 5637 => x"f0", + 5638 => x"d1", + 5639 => x"fc", + 5640 => x"f9", + 5641 => x"83", + 5642 => x"94", + 5643 => x"80", + 5644 => x"c0", + 5645 => x"f1", + 5646 => x"3d", + 5647 => x"53", + 5648 => x"51", + 5649 => x"3f", + 5650 => x"08", + 5651 => x"9d", + 5652 => x"91", + 5653 => x"fe", + 5654 => x"63", + 5655 => x"b7", + 5656 => x"11", + 5657 => x"05", + 5658 => x"8a", + 5659 => x"88", + 5660 => x"f0", + 5661 => x"52", + 5662 => x"51", + 5663 => x"3f", + 5664 => x"2d", + 5665 => x"08", + 5666 => x"88", + 5667 => x"f0", + 5668 => x"ca", + 5669 => x"91", + 5670 => x"fe", + 5671 => x"f0", + 5672 => x"c5", + 5673 => x"ee", + 5674 => x"ce", + 5675 => x"bd", + 5676 => x"80", + 5677 => x"e5", + 5678 => x"ff", + 5679 => x"ea", + 5680 => x"a9", + 5681 => x"33", + 5682 => x"80", + 5683 => x"38", + 5684 => x"80", + 5685 => x"80", + 5686 => x"38", + 5687 => x"f8", + 5688 => x"de", + 5689 => x"c6", + 5690 => x"ca", + 5691 => x"91", + 5692 => x"80", + 5693 => x"9c", + 5694 => x"70", + 5695 => x"f4", + 5696 => x"c6", + 5697 => x"ca", + 5698 => x"56", + 5699 => x"46", + 5700 => x"80", + 5701 => x"0a", + 5702 => x"0a", + 5703 => x"ea", + 5704 => x"ca", + 5705 => x"7c", + 5706 => x"81", + 5707 => x"78", + 5708 => x"ff", + 5709 => x"06", + 5710 => x"91", + 5711 => x"fe", + 5712 => x"ef", + 5713 => x"3d", + 5714 => x"91", + 5715 => x"90", + 5716 => x"91", + 5717 => x"90", + 5718 => x"91", + 5719 => x"fe", + 5720 => x"fe", + 5721 => x"91", + 5722 => x"fe", + 5723 => x"91", + 5724 => x"fe", + 5725 => x"91", + 5726 => x"fe", + 5727 => x"81", + 5728 => x"3f", + 5729 => x"80", + 5730 => x"0f", + 5731 => x"0f", + 5732 => x"0f", + 5733 => x"0f", + 5734 => x"0f", + 5735 => x"4c", + 5736 => x"4b", + 5737 => x"4b", + 5738 => x"4b", + 5739 => x"4b", + 5740 => x"4b", + 5741 => x"4b", + 5742 => x"4b", + 5743 => x"4b", + 5744 => x"4b", + 5745 => x"4b", + 5746 => x"4b", + 5747 => x"4b", + 5748 => x"4b", + 5749 => x"4b", + 5750 => x"4b", + 5751 => x"4b", + 5752 => x"4c", + 5753 => x"4c", + 5754 => x"4c", + 5755 => x"2f", + 5756 => x"25", + 5757 => x"64", + 5758 => x"3a", + 5759 => x"25", + 5760 => x"0a", + 5761 => x"43", + 5762 => x"6e", + 5763 => x"75", + 5764 => x"69", + 5765 => x"00", + 5766 => x"66", + 5767 => x"20", + 5768 => x"20", + 5769 => x"66", + 5770 => x"00", + 5771 => x"44", + 5772 => x"63", + 5773 => x"69", + 5774 => x"65", + 5775 => x"74", + 5776 => x"0a", + 5777 => x"20", + 5778 => x"53", + 5779 => x"52", + 5780 => x"28", + 5781 => x"72", + 5782 => x"30", + 5783 => x"20", + 5784 => x"65", + 5785 => x"38", + 5786 => x"0a", + 5787 => x"20", + 5788 => x"41", + 5789 => x"53", + 5790 => x"74", + 5791 => x"38", + 5792 => x"53", + 5793 => x"3d", + 5794 => x"58", + 5795 => x"00", + 5796 => x"20", + 5797 => x"4d", + 5798 => x"74", + 5799 => x"3d", + 5800 => x"58", + 5801 => x"69", + 5802 => x"25", + 5803 => x"29", + 5804 => x"00", + 5805 => x"20", + 5806 => x"43", + 5807 => x"00", + 5808 => x"20", + 5809 => x"32", + 5810 => x"00", + 5811 => x"20", + 5812 => x"49", + 5813 => x"00", + 5814 => x"20", + 5815 => x"20", + 5816 => x"64", + 5817 => x"65", + 5818 => x"65", + 5819 => x"30", + 5820 => x"2e", + 5821 => x"00", + 5822 => x"20", + 5823 => x"54", + 5824 => x"55", + 5825 => x"43", + 5826 => x"52", + 5827 => x"45", + 5828 => x"00", + 5829 => x"20", + 5830 => x"4d", + 5831 => x"20", + 5832 => x"6d", + 5833 => x"3d", + 5834 => x"58", + 5835 => x"00", + 5836 => x"64", + 5837 => x"73", + 5838 => x"0a", + 5839 => x"20", + 5840 => x"55", + 5841 => x"73", + 5842 => x"56", + 5843 => x"6f", + 5844 => x"64", + 5845 => x"73", + 5846 => x"20", + 5847 => x"58", + 5848 => x"00", + 5849 => x"20", + 5850 => x"55", + 5851 => x"6d", + 5852 => x"20", + 5853 => x"72", + 5854 => x"64", + 5855 => x"73", + 5856 => x"20", + 5857 => x"58", + 5858 => x"00", + 5859 => x"20", + 5860 => x"61", + 5861 => x"53", + 5862 => x"74", + 5863 => x"64", + 5864 => x"73", + 5865 => x"20", + 5866 => x"20", + 5867 => x"58", + 5868 => x"00", + 5869 => x"20", + 5870 => x"55", + 5871 => x"20", + 5872 => x"20", + 5873 => x"20", + 5874 => x"20", + 5875 => x"20", + 5876 => x"20", + 5877 => x"58", + 5878 => x"00", + 5879 => x"20", + 5880 => x"73", + 5881 => x"20", + 5882 => x"63", + 5883 => x"72", + 5884 => x"20", + 5885 => x"20", + 5886 => x"20", + 5887 => x"58", + 5888 => x"00", + 5889 => x"61", + 5890 => x"00", + 5891 => x"64", + 5892 => x"00", + 5893 => x"65", + 5894 => x"00", + 5895 => x"4f", + 5896 => x"4f", + 5897 => x"00", + 5898 => x"6b", + 5899 => x"6e", + 5900 => x"00", + 5901 => x"2b", + 5902 => x"3c", + 5903 => x"5b", + 5904 => x"00", + 5905 => x"54", + 5906 => x"54", + 5907 => x"00", + 5908 => x"90", + 5909 => x"4f", + 5910 => x"30", + 5911 => x"20", + 5912 => x"45", + 5913 => x"20", + 5914 => x"33", + 5915 => x"20", + 5916 => x"20", + 5917 => x"45", + 5918 => x"20", + 5919 => x"20", + 5920 => x"20", + 5921 => x"5c", + 5922 => x"00", + 5923 => x"00", + 5924 => x"00", + 5925 => x"45", + 5926 => x"8f", + 5927 => x"45", + 5928 => x"8e", + 5929 => x"92", + 5930 => x"55", + 5931 => x"9a", + 5932 => x"9e", + 5933 => x"4f", + 5934 => x"a6", + 5935 => x"aa", + 5936 => x"ae", + 5937 => x"b2", + 5938 => x"b6", + 5939 => x"ba", + 5940 => x"be", + 5941 => x"c2", + 5942 => x"c6", + 5943 => x"ca", + 5944 => x"ce", + 5945 => x"d2", + 5946 => x"d6", + 5947 => x"da", + 5948 => x"de", + 5949 => x"e2", + 5950 => x"e6", + 5951 => x"ea", + 5952 => x"ee", + 5953 => x"f2", + 5954 => x"f6", + 5955 => x"fa", + 5956 => x"fe", + 5957 => x"2c", + 5958 => x"5d", + 5959 => x"2a", + 5960 => x"3f", + 5961 => x"00", + 5962 => x"00", + 5963 => x"00", + 5964 => x"02", + 5965 => x"00", + 5966 => x"00", + 5967 => x"00", + 5968 => x"00", + 5969 => x"00", + 5970 => x"6e", + 5971 => x"00", + 5972 => x"6f", + 5973 => x"00", + 5974 => x"6e", + 5975 => x"00", + 5976 => x"6f", + 5977 => x"00", + 5978 => x"78", + 5979 => x"00", + 5980 => x"6c", + 5981 => x"00", + 5982 => x"6f", + 5983 => x"00", + 5984 => x"69", + 5985 => x"00", + 5986 => x"75", + 5987 => x"00", + 5988 => x"62", + 5989 => x"68", + 5990 => x"77", + 5991 => x"64", + 5992 => x"65", + 5993 => x"64", + 5994 => x"65", + 5995 => x"6c", + 5996 => x"00", + 5997 => x"70", + 5998 => x"73", + 5999 => x"74", + 6000 => x"73", + 6001 => x"00", + 6002 => x"66", + 6003 => x"00", + 6004 => x"73", + 6005 => x"00", + 6006 => x"73", + 6007 => x"72", + 6008 => x"0a", + 6009 => x"74", + 6010 => x"61", + 6011 => x"72", + 6012 => x"2e", + 6013 => x"00", + 6014 => x"73", + 6015 => x"6f", + 6016 => x"65", + 6017 => x"2e", + 6018 => x"00", + 6019 => x"20", + 6020 => x"65", + 6021 => x"75", + 6022 => x"0a", + 6023 => x"20", + 6024 => x"68", + 6025 => x"75", + 6026 => x"0a", + 6027 => x"76", + 6028 => x"64", + 6029 => x"6c", + 6030 => x"6d", + 6031 => x"00", + 6032 => x"63", + 6033 => x"20", + 6034 => x"69", + 6035 => x"0a", + 6036 => x"6c", + 6037 => x"6c", + 6038 => x"64", + 6039 => x"78", + 6040 => x"73", + 6041 => x"00", + 6042 => x"6c", + 6043 => x"61", + 6044 => x"65", + 6045 => x"76", + 6046 => x"64", + 6047 => x"00", + 6048 => x"20", + 6049 => x"77", + 6050 => x"65", + 6051 => x"6f", + 6052 => x"74", + 6053 => x"0a", + 6054 => x"69", + 6055 => x"6e", + 6056 => x"65", + 6057 => x"73", + 6058 => x"76", + 6059 => x"64", + 6060 => x"00", + 6061 => x"73", + 6062 => x"6f", + 6063 => x"6e", + 6064 => x"65", + 6065 => x"00", + 6066 => x"20", + 6067 => x"70", + 6068 => x"62", + 6069 => x"66", + 6070 => x"73", + 6071 => x"65", + 6072 => x"6f", + 6073 => x"20", + 6074 => x"64", + 6075 => x"2e", + 6076 => x"00", + 6077 => x"72", + 6078 => x"20", + 6079 => x"72", + 6080 => x"2e", + 6081 => x"00", + 6082 => x"6d", + 6083 => x"74", + 6084 => x"70", + 6085 => x"74", + 6086 => x"20", + 6087 => x"63", + 6088 => x"65", + 6089 => x"00", + 6090 => x"6c", + 6091 => x"73", + 6092 => x"63", + 6093 => x"2e", + 6094 => x"00", + 6095 => x"73", + 6096 => x"69", + 6097 => x"6e", + 6098 => x"65", + 6099 => x"79", + 6100 => x"00", + 6101 => x"6f", + 6102 => x"6e", + 6103 => x"70", + 6104 => x"66", + 6105 => x"73", + 6106 => x"00", + 6107 => x"72", + 6108 => x"74", + 6109 => x"20", + 6110 => x"6f", + 6111 => x"63", + 6112 => x"00", + 6113 => x"63", + 6114 => x"73", + 6115 => x"00", + 6116 => x"6b", + 6117 => x"6e", + 6118 => x"72", + 6119 => x"0a", + 6120 => x"6c", + 6121 => x"79", + 6122 => x"20", + 6123 => x"61", + 6124 => x"6c", + 6125 => x"79", + 6126 => x"2f", + 6127 => x"2e", + 6128 => x"00", + 6129 => x"38", + 6130 => x"00", + 6131 => x"20", + 6132 => x"34", + 6133 => x"00", + 6134 => x"20", + 6135 => x"20", + 6136 => x"00", + 6137 => x"32", + 6138 => x"00", + 6139 => x"00", + 6140 => x"00", + 6141 => x"0a", + 6142 => x"61", + 6143 => x"00", + 6144 => x"55", + 6145 => x"00", + 6146 => x"2a", + 6147 => x"20", + 6148 => x"00", + 6149 => x"2f", + 6150 => x"32", + 6151 => x"00", + 6152 => x"2e", + 6153 => x"00", + 6154 => x"50", + 6155 => x"72", + 6156 => x"25", + 6157 => x"29", + 6158 => x"20", + 6159 => x"2a", + 6160 => x"00", + 6161 => x"55", + 6162 => x"49", + 6163 => x"72", + 6164 => x"74", + 6165 => x"6e", + 6166 => x"72", + 6167 => x"00", + 6168 => x"6d", + 6169 => x"69", + 6170 => x"72", + 6171 => x"74", + 6172 => x"00", + 6173 => x"32", + 6174 => x"74", + 6175 => x"75", + 6176 => x"00", + 6177 => x"43", + 6178 => x"52", + 6179 => x"6e", + 6180 => x"72", + 6181 => x"0a", + 6182 => x"43", + 6183 => x"57", + 6184 => x"6e", + 6185 => x"72", + 6186 => x"0a", + 6187 => x"52", + 6188 => x"52", + 6189 => x"6e", + 6190 => x"72", + 6191 => x"0a", + 6192 => x"52", + 6193 => x"54", + 6194 => x"6e", + 6195 => x"72", + 6196 => x"0a", + 6197 => x"52", + 6198 => x"52", + 6199 => x"6e", + 6200 => x"72", + 6201 => x"0a", + 6202 => x"52", + 6203 => x"54", + 6204 => x"6e", + 6205 => x"72", + 6206 => x"0a", + 6207 => x"74", + 6208 => x"67", + 6209 => x"20", + 6210 => x"65", + 6211 => x"2e", + 6212 => x"00", + 6213 => x"61", + 6214 => x"6e", + 6215 => x"69", + 6216 => x"2e", + 6217 => x"00", + 6218 => x"00", + 6219 => x"69", + 6220 => x"20", + 6221 => x"69", + 6222 => x"69", + 6223 => x"73", + 6224 => x"64", + 6225 => x"72", + 6226 => x"2c", + 6227 => x"65", + 6228 => x"20", + 6229 => x"74", + 6230 => x"6e", + 6231 => x"6c", + 6232 => x"00", + 6233 => x"00", + 6234 => x"64", + 6235 => x"73", + 6236 => x"64", + 6237 => x"00", + 6238 => x"69", + 6239 => x"6c", + 6240 => x"64", + 6241 => x"00", + 6242 => x"69", + 6243 => x"20", + 6244 => x"69", + 6245 => x"69", + 6246 => x"73", + 6247 => x"00", + 6248 => x"3d", + 6249 => x"00", + 6250 => x"3a", + 6251 => x"65", + 6252 => x"6e", + 6253 => x"2e", + 6254 => x"70", + 6255 => x"67", + 6256 => x"00", + 6257 => x"6d", + 6258 => x"69", + 6259 => x"2e", + 6260 => x"00", + 6261 => x"38", + 6262 => x"25", + 6263 => x"29", + 6264 => x"30", + 6265 => x"28", + 6266 => x"78", + 6267 => x"00", + 6268 => x"6d", + 6269 => x"65", + 6270 => x"79", + 6271 => x"00", + 6272 => x"6f", + 6273 => x"65", + 6274 => x"0a", + 6275 => x"38", + 6276 => x"30", + 6277 => x"00", + 6278 => x"3f", + 6279 => x"00", + 6280 => x"38", + 6281 => x"30", + 6282 => x"00", + 6283 => x"38", + 6284 => x"30", + 6285 => x"00", + 6286 => x"73", + 6287 => x"69", + 6288 => x"69", + 6289 => x"72", + 6290 => x"74", + 6291 => x"00", + 6292 => x"61", + 6293 => x"6e", + 6294 => x"6e", + 6295 => x"72", + 6296 => x"73", + 6297 => x"00", + 6298 => x"73", + 6299 => x"65", + 6300 => x"61", + 6301 => x"66", + 6302 => x"0a", + 6303 => x"61", + 6304 => x"6e", + 6305 => x"61", + 6306 => x"66", + 6307 => x"0a", + 6308 => x"65", + 6309 => x"69", + 6310 => x"63", + 6311 => x"20", + 6312 => x"30", + 6313 => x"2e", + 6314 => x"00", + 6315 => x"6c", + 6316 => x"67", + 6317 => x"64", + 6318 => x"20", + 6319 => x"78", + 6320 => x"2e", + 6321 => x"00", + 6322 => x"6c", + 6323 => x"65", + 6324 => x"6e", + 6325 => x"63", + 6326 => x"20", + 6327 => x"29", + 6328 => x"00", + 6329 => x"73", + 6330 => x"74", + 6331 => x"20", + 6332 => x"6c", + 6333 => x"74", + 6334 => x"2e", + 6335 => x"00", + 6336 => x"6c", + 6337 => x"65", + 6338 => x"74", + 6339 => x"2e", + 6340 => x"00", + 6341 => x"55", + 6342 => x"6e", + 6343 => x"3a", + 6344 => x"5c", + 6345 => x"25", + 6346 => x"00", + 6347 => x"64", + 6348 => x"6d", + 6349 => x"64", + 6350 => x"00", + 6351 => x"6e", + 6352 => x"67", + 6353 => x"0a", + 6354 => x"61", + 6355 => x"6e", + 6356 => x"6e", + 6357 => x"72", + 6358 => x"73", + 6359 => x"0a", + 6360 => x"00", + 6361 => x"00", + 6362 => x"7f", + 6363 => x"00", + 6364 => x"7f", + 6365 => x"00", + 6366 => x"7f", + 6367 => x"00", + 6368 => x"00", + 6369 => x"78", + 6370 => x"00", + 6371 => x"e1", + 6372 => x"01", + 6373 => x"01", + 6374 => x"01", + 6375 => x"00", + 6376 => x"00", + 6377 => x"00", + 6378 => x"5d", + 6379 => x"01", + 6380 => x"00", + 6381 => x"00", + 6382 => x"5d", + 6383 => x"01", + 6384 => x"00", + 6385 => x"00", + 6386 => x"5d", + 6387 => x"03", + 6388 => x"00", + 6389 => x"00", + 6390 => x"5d", + 6391 => x"03", + 6392 => x"00", + 6393 => x"00", + 6394 => x"5d", + 6395 => x"03", + 6396 => x"00", + 6397 => x"00", + 6398 => x"5d", + 6399 => x"04", + 6400 => x"00", + 6401 => x"00", + 6402 => x"5d", + 6403 => x"04", + 6404 => x"00", + 6405 => x"00", + 6406 => x"5d", + 6407 => x"04", + 6408 => x"00", + 6409 => x"00", + 6410 => x"5d", + 6411 => x"04", + 6412 => x"00", + 6413 => x"00", + 6414 => x"5d", + 6415 => x"04", + 6416 => x"00", + 6417 => x"00", + 6418 => x"5d", + 6419 => x"04", + 6420 => x"00", + 6421 => x"00", + 6422 => x"5d", + 6423 => x"04", + 6424 => x"00", + 6425 => x"00", + 6426 => x"5d", + 6427 => x"05", + 6428 => x"00", + 6429 => x"00", + 6430 => x"5d", + 6431 => x"05", + 6432 => x"00", + 6433 => x"00", + 6434 => x"5d", + 6435 => x"05", + 6436 => x"00", + 6437 => x"00", + 6438 => x"5d", + 6439 => x"05", + 6440 => x"00", + 6441 => x"00", + 6442 => x"5d", + 6443 => x"07", + 6444 => x"00", + 6445 => x"00", + 6446 => x"5d", + 6447 => x"07", + 6448 => x"00", + 6449 => x"00", + 6450 => x"5d", + 6451 => x"08", + 6452 => x"00", + 6453 => x"00", + 6454 => x"5d", + 6455 => x"08", + 6456 => x"00", + 6457 => x"00", + 6458 => x"5d", + 6459 => x"08", + 6460 => x"00", + 6461 => x"00", + 6462 => x"5d", + 6463 => x"08", + 6464 => x"00", + 6465 => x"00", + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + 0 => x"0b", + 1 => x"0b", + 2 => x"8a", + 3 => x"ff", + 4 => x"ff", + 5 => x"ff", + 6 => x"ff", + 7 => x"ff", + 8 => x"0b", + 9 => x"04", + 10 => x"84", + 11 => x"0b", + 12 => x"04", + 13 => x"84", + 14 => x"0b", + 15 => x"04", + 16 => x"84", + 17 => x"0b", + 18 => x"04", + 19 => x"84", + 20 => x"0b", + 21 => x"04", + 22 => x"85", + 23 => x"0b", + 24 => x"04", + 25 => x"85", + 26 => x"0b", + 27 => x"04", + 28 => x"85", + 29 => x"0b", + 30 => x"04", + 31 => x"85", + 32 => x"0b", + 33 => x"04", + 34 => x"86", + 35 => x"0b", + 36 => x"04", + 37 => x"86", + 38 => x"0b", + 39 => x"04", + 40 => x"86", + 41 => x"0b", + 42 => x"04", + 43 => x"86", + 44 => x"0b", + 45 => x"04", + 46 => x"87", + 47 => x"0b", + 48 => x"04", + 49 => x"87", + 50 => x"0b", + 51 => x"04", + 52 => x"87", + 53 => x"0b", + 54 => x"04", + 55 => x"88", + 56 => x"0b", + 57 => x"04", + 58 => x"88", + 59 => x"0b", + 60 => x"04", + 61 => x"88", + 62 => x"0b", + 63 => x"04", + 64 => x"88", + 65 => x"0b", + 66 => x"04", + 67 => x"89", + 68 => x"0b", + 69 => x"04", + 70 => x"89", + 71 => x"0b", + 72 => x"04", + 73 => x"89", + 74 => x"0b", + 75 => x"04", + 76 => x"89", + 77 => x"0b", + 78 => x"04", + 79 => x"8a", + 80 => x"0b", + 81 => x"04", + 82 => x"8a", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"00", + 89 => x"00", + 90 => x"00", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"00", + 97 => x"00", + 98 => x"00", + 99 => x"00", + 100 => x"00", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"00", + 105 => x"00", + 106 => x"00", + 107 => x"00", + 108 => x"00", + 109 => x"00", + 110 => x"00", + 111 => x"00", + 112 => x"00", + 113 => x"00", + 114 => x"00", + 115 => x"00", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"00", + 121 => x"00", + 122 => x"00", + 123 => x"00", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"90", + 129 => x"91", + 130 => x"90", + 131 => x"91", + 132 => x"88", + 133 => x"04", + 134 => x"0c", + 135 => x"2d", + 136 => x"08", + 137 => x"90", + 138 => x"94", + 139 => x"fe", + 140 => x"94", + 141 => x"80", + 142 => x"ca", + 143 => x"a0", + 144 => x"ca", + 145 => x"c0", + 146 => x"91", + 147 => x"90", + 148 => x"91", + 149 => x"88", + 150 => x"04", + 151 => x"0c", + 152 => x"2d", + 153 => x"08", + 154 => x"90", + 155 => x"94", + 156 => x"bf", + 157 => x"94", + 158 => x"80", + 159 => x"ca", + 160 => x"a7", + 161 => x"ca", + 162 => x"c0", + 163 => x"91", + 164 => x"90", + 165 => x"91", + 166 => x"88", + 167 => x"04", + 168 => x"0c", + 169 => x"2d", + 170 => x"08", + 171 => x"90", + 172 => x"94", + 173 => x"96", + 174 => x"94", + 175 => x"80", + 176 => x"ca", + 177 => x"a6", + 178 => x"ca", + 179 => x"c0", + 180 => x"91", + 181 => x"90", + 182 => x"91", + 183 => x"88", + 184 => x"04", + 185 => x"0c", + 186 => x"2d", + 187 => x"08", + 188 => x"90", + 189 => x"94", + 190 => x"89", + 191 => x"94", + 192 => x"80", + 193 => x"ca", + 194 => x"91", + 195 => x"ca", + 196 => x"c0", + 197 => x"91", + 198 => x"90", + 199 => x"91", + 200 => x"88", + 201 => x"04", + 202 => x"0c", + 203 => x"2d", + 204 => x"08", + 205 => x"90", + 206 => x"94", + 207 => x"8d", + 208 => x"94", + 209 => x"80", + 210 => x"ca", + 211 => x"e1", + 212 => x"ca", + 213 => x"c0", + 214 => x"91", + 215 => x"90", + 216 => x"91", + 217 => x"88", + 218 => x"04", + 219 => x"0c", + 220 => x"2d", + 221 => x"08", + 222 => x"90", + 223 => x"94", + 224 => x"fc", + 225 => x"94", + 226 => x"80", + 227 => x"ca", + 228 => x"e7", + 229 => x"ca", + 230 => x"c0", + 231 => x"91", + 232 => x"90", + 233 => x"91", + 234 => x"88", + 235 => x"04", + 236 => x"0c", + 237 => x"2d", + 238 => x"08", + 239 => x"90", + 240 => x"94", + 241 => x"f9", + 242 => x"94", + 243 => x"80", + 244 => x"ca", + 245 => x"fa", + 246 => x"ca", + 247 => x"c0", + 248 => x"91", + 249 => x"90", + 250 => x"91", + 251 => x"88", + 252 => x"04", + 253 => x"0c", + 254 => x"2d", + 255 => x"08", + 256 => x"90", + 257 => x"94", + 258 => x"fd", + 259 => x"94", + 260 => x"80", + 261 => x"ca", + 262 => x"80", + 263 => x"ca", + 264 => x"c0", + 265 => x"91", + 266 => x"91", + 267 => x"91", + 268 => x"88", + 269 => x"04", + 270 => x"0c", + 271 => x"2d", + 272 => x"08", + 273 => x"90", + 274 => x"94", + 275 => x"c6", + 276 => x"94", + 277 => x"80", + 278 => x"ca", + 279 => x"ea", + 280 => x"ca", + 281 => x"c0", + 282 => x"91", + 283 => x"90", + 284 => x"91", + 285 => x"88", + 286 => x"04", + 287 => x"0c", + 288 => x"2d", + 289 => x"08", + 290 => x"90", + 291 => x"94", + 292 => x"b3", + 293 => x"94", + 294 => x"80", + 295 => x"ca", + 296 => x"87", + 297 => x"ca", + 298 => x"c0", + 299 => x"91", + 300 => x"90", + 301 => x"91", + 302 => x"88", + 303 => x"04", + 304 => x"0c", + 305 => x"2d", + 306 => x"08", + 307 => x"90", + 308 => x"94", + 309 => x"f6", + 310 => x"94", + 311 => x"80", + 312 => x"ca", + 313 => x"ae", + 314 => x"ca", + 315 => x"c0", + 316 => x"91", + 317 => x"90", + 318 => x"91", + 319 => x"88", + 320 => x"04", + 321 => x"0c", + 322 => x"2d", + 323 => x"08", + 324 => x"90", + 325 => x"94", + 326 => x"94", + 327 => x"94", + 328 => x"80", + 329 => x"ca", + 330 => x"94", + 331 => x"ca", + 332 => x"c0", + 333 => x"91", + 334 => x"91", + 335 => x"91", + 336 => x"88", + 337 => x"04", + 338 => x"70", + 339 => x"27", + 340 => x"71", + 341 => x"53", + 342 => x"90", + 343 => x"90", + 344 => x"91", + 345 => x"3c", + 346 => x"94", + 347 => x"ca", + 348 => x"3d", + 349 => x"91", + 350 => x"8c", + 351 => x"91", + 352 => x"88", + 353 => x"80", + 354 => x"ca", + 355 => x"91", + 356 => x"54", + 357 => x"91", + 358 => x"04", + 359 => x"08", + 360 => x"94", + 361 => x"0d", + 362 => x"ca", + 363 => x"05", + 364 => x"ca", + 365 => x"05", + 366 => x"3f", + 367 => x"08", + 368 => x"88", + 369 => x"3d", + 370 => x"94", + 371 => x"ca", + 372 => x"91", + 373 => x"fd", + 374 => x"0b", + 375 => x"08", + 376 => x"80", + 377 => x"94", + 378 => x"0c", + 379 => x"08", + 380 => x"91", + 381 => x"88", + 382 => x"b9", + 383 => x"94", + 384 => x"08", + 385 => x"38", + 386 => x"ca", + 387 => x"05", + 388 => x"38", + 389 => x"08", + 390 => x"10", + 391 => x"08", + 392 => x"91", + 393 => x"fc", + 394 => x"91", + 395 => x"fc", + 396 => x"b8", + 397 => x"94", + 398 => x"08", + 399 => x"e1", + 400 => x"94", + 401 => x"08", + 402 => x"08", + 403 => x"26", + 404 => x"ca", + 405 => x"05", + 406 => x"94", + 407 => x"08", + 408 => x"94", + 409 => x"0c", + 410 => x"08", + 411 => x"91", + 412 => x"fc", + 413 => x"91", + 414 => x"f8", + 415 => x"ca", + 416 => x"05", + 417 => x"91", + 418 => x"fc", + 419 => x"ca", + 420 => x"05", + 421 => x"91", + 422 => x"8c", + 423 => x"95", + 424 => x"94", + 425 => x"08", + 426 => x"38", + 427 => x"08", + 428 => x"70", + 429 => x"08", + 430 => x"51", + 431 => x"ca", + 432 => x"05", + 433 => x"ca", + 434 => x"05", + 435 => x"ca", + 436 => x"05", + 437 => x"88", + 438 => x"0d", + 439 => x"0c", + 440 => x"0d", + 441 => x"02", + 442 => x"05", + 443 => x"53", + 444 => x"27", + 445 => x"83", + 446 => x"80", + 447 => x"ff", + 448 => x"ff", + 449 => x"73", + 450 => x"05", + 451 => x"12", + 452 => x"2e", + 453 => x"ef", + 454 => x"ca", + 455 => x"3d", + 456 => x"74", + 457 => x"07", + 458 => x"2b", + 459 => x"51", + 460 => x"a5", + 461 => x"70", + 462 => x"0c", + 463 => x"84", + 464 => x"72", + 465 => x"05", + 466 => x"71", + 467 => x"53", + 468 => x"52", + 469 => x"dd", + 470 => x"27", + 471 => x"71", + 472 => x"53", + 473 => x"52", + 474 => x"f2", + 475 => x"ff", + 476 => x"3d", + 477 => x"70", + 478 => x"06", + 479 => x"70", + 480 => x"73", + 481 => x"56", + 482 => x"08", + 483 => x"38", + 484 => x"52", + 485 => x"81", + 486 => x"54", + 487 => x"9d", + 488 => x"55", + 489 => x"09", + 490 => x"38", + 491 => x"14", + 492 => x"81", + 493 => x"56", + 494 => x"e5", + 495 => x"55", + 496 => x"06", + 497 => x"06", + 498 => x"91", + 499 => x"52", + 500 => x"0d", + 501 => x"70", + 502 => x"ff", + 503 => x"f8", + 504 => x"80", + 505 => x"51", + 506 => x"84", + 507 => x"71", + 508 => x"54", + 509 => x"2e", + 510 => x"75", + 511 => x"94", + 512 => x"91", + 513 => x"87", + 514 => x"fe", + 515 => x"52", + 516 => x"88", + 517 => x"86", + 518 => x"88", + 519 => x"06", + 520 => x"14", + 521 => x"80", + 522 => x"71", + 523 => x"0c", + 524 => x"04", + 525 => x"77", + 526 => x"53", + 527 => x"80", + 528 => x"38", + 529 => x"70", + 530 => x"81", + 531 => x"81", + 532 => x"39", + 533 => x"39", + 534 => x"80", + 535 => x"81", + 536 => x"55", + 537 => x"2e", + 538 => x"55", + 539 => x"84", + 540 => x"38", + 541 => x"06", + 542 => x"2e", + 543 => x"88", + 544 => x"70", + 545 => x"34", + 546 => x"71", + 547 => x"ca", + 548 => x"3d", + 549 => x"3d", + 550 => x"72", + 551 => x"91", + 552 => x"fc", + 553 => x"51", + 554 => x"91", + 555 => x"85", + 556 => x"83", + 557 => x"72", + 558 => x"0c", + 559 => x"04", + 560 => x"76", + 561 => x"ff", + 562 => x"81", + 563 => x"26", + 564 => x"83", + 565 => x"05", + 566 => x"70", + 567 => x"8a", + 568 => x"33", + 569 => x"70", + 570 => x"fe", + 571 => x"33", + 572 => x"70", + 573 => x"f2", + 574 => x"33", + 575 => x"70", + 576 => x"e6", + 577 => x"22", + 578 => x"74", + 579 => x"80", + 580 => x"13", + 581 => x"52", + 582 => x"26", + 583 => x"81", + 584 => x"98", + 585 => x"22", + 586 => x"bc", + 587 => x"33", + 588 => x"b8", + 589 => x"33", + 590 => x"b4", + 591 => x"33", + 592 => x"b0", + 593 => x"33", + 594 => x"ac", + 595 => x"33", + 596 => x"a8", + 597 => x"c0", + 598 => x"73", + 599 => x"a0", + 600 => x"87", + 601 => x"0c", + 602 => x"91", + 603 => x"86", + 604 => x"f3", + 605 => x"5b", + 606 => x"9c", + 607 => x"0c", + 608 => x"bc", + 609 => x"7b", + 610 => x"98", + 611 => x"79", + 612 => x"87", + 613 => x"08", + 614 => x"1c", + 615 => x"98", + 616 => x"79", + 617 => x"87", + 618 => x"08", + 619 => x"1c", + 620 => x"98", + 621 => x"79", + 622 => x"87", + 623 => x"08", + 624 => x"1c", + 625 => x"98", + 626 => x"79", + 627 => x"80", + 628 => x"83", + 629 => x"59", + 630 => x"ff", + 631 => x"1b", + 632 => x"1b", + 633 => x"1b", + 634 => x"1b", + 635 => x"1b", + 636 => x"83", + 637 => x"52", + 638 => x"51", + 639 => x"8f", + 640 => x"ff", + 641 => x"8f", + 642 => x"30", + 643 => x"51", + 644 => x"0b", + 645 => x"e0", + 646 => x"0d", + 647 => x"0d", + 648 => x"91", + 649 => x"70", + 650 => x"57", + 651 => x"c0", + 652 => x"74", + 653 => x"38", + 654 => x"94", + 655 => x"70", + 656 => x"81", + 657 => x"52", + 658 => x"8c", + 659 => x"2a", + 660 => x"51", + 661 => x"38", + 662 => x"70", + 663 => x"51", + 664 => x"8d", + 665 => x"2a", + 666 => x"51", + 667 => x"be", + 668 => x"ff", + 669 => x"c0", + 670 => x"70", + 671 => x"38", + 672 => x"90", + 673 => x"0c", + 674 => x"88", + 675 => x"0d", + 676 => x"0d", + 677 => x"33", + 678 => x"c6", + 679 => x"81", + 680 => x"55", + 681 => x"94", + 682 => x"80", + 683 => x"87", + 684 => x"51", + 685 => x"96", + 686 => x"06", + 687 => x"70", + 688 => x"38", + 689 => x"70", + 690 => x"51", + 691 => x"72", + 692 => x"81", + 693 => x"70", + 694 => x"38", + 695 => x"70", + 696 => x"51", + 697 => x"38", + 698 => x"06", + 699 => x"94", + 700 => x"80", + 701 => x"87", + 702 => x"52", + 703 => x"87", + 704 => x"f9", + 705 => x"54", + 706 => x"70", + 707 => x"53", + 708 => x"77", + 709 => x"38", + 710 => x"06", + 711 => x"0b", + 712 => x"33", + 713 => x"06", + 714 => x"58", + 715 => x"84", + 716 => x"2e", + 717 => x"c0", + 718 => x"70", + 719 => x"2a", + 720 => x"53", + 721 => x"80", + 722 => x"71", + 723 => x"81", + 724 => x"70", + 725 => x"81", + 726 => x"06", + 727 => x"80", + 728 => x"71", + 729 => x"81", + 730 => x"70", + 731 => x"74", + 732 => x"51", + 733 => x"80", + 734 => x"2e", + 735 => x"c0", + 736 => x"77", + 737 => x"17", + 738 => x"81", + 739 => x"53", + 740 => x"84", + 741 => x"ca", + 742 => x"3d", + 743 => x"3d", + 744 => x"91", + 745 => x"70", + 746 => x"54", + 747 => x"94", + 748 => x"80", + 749 => x"87", + 750 => x"51", + 751 => x"82", + 752 => x"06", + 753 => x"70", + 754 => x"38", + 755 => x"06", + 756 => x"94", + 757 => x"80", + 758 => x"87", + 759 => x"52", + 760 => x"81", + 761 => x"ca", + 762 => x"84", + 763 => x"fe", + 764 => x"0b", + 765 => x"33", + 766 => x"06", + 767 => x"c0", + 768 => x"70", + 769 => x"38", + 770 => x"94", + 771 => x"70", + 772 => x"81", + 773 => x"51", + 774 => x"80", + 775 => x"72", + 776 => x"51", + 777 => x"80", + 778 => x"2e", + 779 => x"c0", + 780 => x"71", + 781 => x"2b", + 782 => x"51", + 783 => x"91", + 784 => x"84", + 785 => x"ff", + 786 => x"c0", + 787 => x"70", + 788 => x"06", + 789 => x"80", + 790 => x"38", + 791 => x"9c", + 792 => x"e4", + 793 => x"9e", + 794 => x"c6", + 795 => x"c0", + 796 => x"91", + 797 => x"87", + 798 => x"08", + 799 => x"0c", + 800 => x"94", + 801 => x"f4", + 802 => x"9e", + 803 => x"c6", + 804 => x"c0", + 805 => x"91", + 806 => x"87", + 807 => x"08", + 808 => x"0c", + 809 => x"ac", + 810 => x"84", + 811 => x"9e", + 812 => x"70", + 813 => x"23", + 814 => x"84", + 815 => x"8c", + 816 => x"91", + 817 => x"80", + 818 => x"9e", + 819 => x"a0", + 820 => x"52", + 821 => x"2e", + 822 => x"52", + 823 => x"91", + 824 => x"87", + 825 => x"08", + 826 => x"80", + 827 => x"52", + 828 => x"83", + 829 => x"71", + 830 => x"34", + 831 => x"c0", + 832 => x"70", + 833 => x"06", + 834 => x"70", + 835 => x"38", + 836 => x"91", + 837 => x"80", + 838 => x"9e", + 839 => x"90", + 840 => x"52", + 841 => x"2e", + 842 => x"52", + 843 => x"94", + 844 => x"87", + 845 => x"08", + 846 => x"06", + 847 => x"70", + 848 => x"38", + 849 => x"91", + 850 => x"80", + 851 => x"9e", + 852 => x"84", + 853 => x"52", + 854 => x"2e", + 855 => x"52", + 856 => x"96", + 857 => x"87", + 858 => x"08", + 859 => x"06", + 860 => x"70", + 861 => x"38", + 862 => x"91", + 863 => x"80", + 864 => x"9e", + 865 => x"81", + 866 => x"52", + 867 => x"2e", + 868 => x"52", + 869 => x"98", + 870 => x"9e", + 871 => x"80", + 872 => x"86", + 873 => x"51", + 874 => x"99", + 875 => x"87", + 876 => x"08", + 877 => x"51", + 878 => x"80", + 879 => x"81", + 880 => x"c7", + 881 => x"0b", + 882 => x"88", + 883 => x"06", + 884 => x"70", + 885 => x"38", + 886 => x"91", + 887 => x"87", + 888 => x"08", + 889 => x"51", + 890 => x"c7", + 891 => x"3d", + 892 => x"3d", + 893 => x"84", + 894 => x"3f", + 895 => x"33", + 896 => x"2e", + 897 => x"b4", + 898 => x"92", + 899 => x"ac", + 900 => x"3f", + 901 => x"33", + 902 => x"2e", + 903 => x"c6", + 904 => x"91", + 905 => x"52", + 906 => x"51", + 907 => x"91", + 908 => x"54", + 909 => x"92", + 910 => x"f0", + 911 => x"c6", + 912 => x"91", + 913 => x"89", + 914 => x"c7", + 915 => x"73", + 916 => x"c7", + 917 => x"73", + 918 => x"38", + 919 => x"08", + 920 => x"f4", + 921 => x"b5", + 922 => x"96", + 923 => x"95", + 924 => x"80", + 925 => x"91", + 926 => x"83", + 927 => x"c7", + 928 => x"73", + 929 => x"38", + 930 => x"51", + 931 => x"91", + 932 => x"54", + 933 => x"88", + 934 => x"cc", + 935 => x"3f", + 936 => x"33", + 937 => x"2e", + 938 => x"c7", + 939 => x"91", + 940 => x"88", + 941 => x"c7", + 942 => x"73", + 943 => x"38", + 944 => x"51", + 945 => x"91", + 946 => x"54", + 947 => x"8d", + 948 => x"9c", + 949 => x"b6", + 950 => x"a6", + 951 => x"b0", + 952 => x"3f", + 953 => x"08", + 954 => x"bc", + 955 => x"3f", + 956 => x"08", + 957 => x"e4", + 958 => x"3f", + 959 => x"08", + 960 => x"8c", + 961 => x"3f", + 962 => x"22", + 963 => x"b4", + 964 => x"3f", + 965 => x"08", + 966 => x"dc", + 967 => x"3f", + 968 => x"04", + 969 => x"02", + 970 => x"ff", + 971 => x"84", + 972 => x"71", + 973 => x"0b", + 974 => x"05", + 975 => x"04", + 976 => x"51", + 977 => x"b8", + 978 => x"39", + 979 => x"51", + 980 => x"b8", + 981 => x"39", + 982 => x"51", + 983 => x"b8", + 984 => x"9f", + 985 => x"0d", + 986 => x"80", + 987 => x"0b", + 988 => x"84", + 989 => x"3d", + 990 => x"96", + 991 => x"52", + 992 => x"0c", + 993 => x"70", + 994 => x"0c", + 995 => x"3d", + 996 => x"3d", + 997 => x"96", + 998 => x"91", + 999 => x"52", + 1000 => x"73", + 1001 => x"c7", + 1002 => x"70", + 1003 => x"0c", + 1004 => x"83", + 1005 => x"91", + 1006 => x"87", + 1007 => x"0c", + 1008 => x"0d", + 1009 => x"33", + 1010 => x"2e", + 1011 => x"85", + 1012 => x"ed", + 1013 => x"a0", + 1014 => x"80", + 1015 => x"72", + 1016 => x"ca", + 1017 => x"05", + 1018 => x"0c", + 1019 => x"ca", + 1020 => x"71", + 1021 => x"38", + 1022 => x"2d", + 1023 => x"04", + 1024 => x"02", + 1025 => x"91", + 1026 => x"76", + 1027 => x"0c", + 1028 => x"ad", + 1029 => x"ca", + 1030 => x"3d", + 1031 => x"3d", + 1032 => x"73", + 1033 => x"ff", + 1034 => x"71", + 1035 => x"38", + 1036 => x"06", + 1037 => x"54", + 1038 => x"e7", + 1039 => x"0d", + 1040 => x"0d", + 1041 => x"98", + 1042 => x"ca", + 1043 => x"54", + 1044 => x"81", + 1045 => x"53", + 1046 => x"8e", + 1047 => x"ff", + 1048 => x"14", + 1049 => x"3f", + 1050 => x"91", + 1051 => x"86", + 1052 => x"ec", + 1053 => x"68", + 1054 => x"70", + 1055 => x"33", + 1056 => x"2e", + 1057 => x"75", + 1058 => x"81", + 1059 => x"38", + 1060 => x"70", + 1061 => x"33", + 1062 => x"75", + 1063 => x"81", + 1064 => x"81", + 1065 => x"75", + 1066 => x"81", + 1067 => x"82", + 1068 => x"81", + 1069 => x"56", + 1070 => x"09", + 1071 => x"38", + 1072 => x"71", + 1073 => x"81", + 1074 => x"59", + 1075 => x"9d", + 1076 => x"53", + 1077 => x"95", + 1078 => x"29", + 1079 => x"76", + 1080 => x"79", + 1081 => x"5b", + 1082 => x"e5", + 1083 => x"ec", + 1084 => x"70", + 1085 => x"25", + 1086 => x"32", + 1087 => x"72", + 1088 => x"73", + 1089 => x"58", + 1090 => x"73", + 1091 => x"38", + 1092 => x"79", + 1093 => x"5b", + 1094 => x"75", + 1095 => x"de", + 1096 => x"80", + 1097 => x"89", + 1098 => x"70", + 1099 => x"55", + 1100 => x"cf", + 1101 => x"38", + 1102 => x"24", + 1103 => x"80", + 1104 => x"8e", + 1105 => x"c3", + 1106 => x"73", + 1107 => x"81", + 1108 => x"99", + 1109 => x"c4", + 1110 => x"38", + 1111 => x"73", + 1112 => x"81", + 1113 => x"80", + 1114 => x"38", + 1115 => x"2e", + 1116 => x"f9", + 1117 => x"d8", + 1118 => x"38", + 1119 => x"77", + 1120 => x"08", + 1121 => x"80", + 1122 => x"55", + 1123 => x"8d", + 1124 => x"70", + 1125 => x"51", + 1126 => x"f5", + 1127 => x"2a", + 1128 => x"74", + 1129 => x"53", + 1130 => x"8f", + 1131 => x"fc", + 1132 => x"81", + 1133 => x"80", + 1134 => x"73", + 1135 => x"3f", + 1136 => x"56", + 1137 => x"27", + 1138 => x"a0", + 1139 => x"3f", + 1140 => x"84", + 1141 => x"33", + 1142 => x"93", + 1143 => x"95", + 1144 => x"91", + 1145 => x"8d", + 1146 => x"89", + 1147 => x"fb", + 1148 => x"86", + 1149 => x"2a", + 1150 => x"51", + 1151 => x"2e", + 1152 => x"84", + 1153 => x"86", + 1154 => x"78", + 1155 => x"08", + 1156 => x"32", + 1157 => x"72", + 1158 => x"51", + 1159 => x"74", + 1160 => x"38", + 1161 => x"88", + 1162 => x"7a", + 1163 => x"55", + 1164 => x"3d", + 1165 => x"52", + 1166 => x"e0", + 1167 => x"88", + 1168 => x"06", + 1169 => x"52", + 1170 => x"3f", + 1171 => x"08", + 1172 => x"27", + 1173 => x"14", + 1174 => x"f8", + 1175 => x"87", + 1176 => x"81", + 1177 => x"b0", + 1178 => x"7d", + 1179 => x"5f", + 1180 => x"75", + 1181 => x"07", + 1182 => x"54", + 1183 => x"26", + 1184 => x"ff", + 1185 => x"84", + 1186 => x"06", + 1187 => x"80", + 1188 => x"96", + 1189 => x"e0", + 1190 => x"73", + 1191 => x"57", + 1192 => x"06", + 1193 => x"54", + 1194 => x"a0", + 1195 => x"2a", + 1196 => x"54", + 1197 => x"38", + 1198 => x"76", + 1199 => x"38", + 1200 => x"fd", + 1201 => x"06", + 1202 => x"38", + 1203 => x"56", + 1204 => x"26", + 1205 => x"3d", + 1206 => x"05", + 1207 => x"ff", + 1208 => x"53", + 1209 => x"d9", + 1210 => x"38", + 1211 => x"56", + 1212 => x"27", + 1213 => x"a0", + 1214 => x"3f", + 1215 => x"3d", + 1216 => x"3d", + 1217 => x"70", + 1218 => x"52", + 1219 => x"73", + 1220 => x"3f", + 1221 => x"04", + 1222 => x"74", + 1223 => x"0c", + 1224 => x"05", + 1225 => x"fa", + 1226 => x"ca", + 1227 => x"80", + 1228 => x"0b", + 1229 => x"0c", + 1230 => x"04", + 1231 => x"91", + 1232 => x"76", + 1233 => x"0c", + 1234 => x"05", + 1235 => x"53", + 1236 => x"72", + 1237 => x"0c", + 1238 => x"04", + 1239 => x"77", + 1240 => x"9c", + 1241 => x"54", + 1242 => x"54", + 1243 => x"80", + 1244 => x"ca", + 1245 => x"71", + 1246 => x"88", + 1247 => x"06", + 1248 => x"2e", + 1249 => x"72", + 1250 => x"38", + 1251 => x"70", + 1252 => x"25", + 1253 => x"73", + 1254 => x"38", + 1255 => x"86", + 1256 => x"54", + 1257 => x"73", + 1258 => x"ff", + 1259 => x"72", + 1260 => x"74", + 1261 => x"72", + 1262 => x"54", + 1263 => x"81", + 1264 => x"39", + 1265 => x"80", + 1266 => x"51", + 1267 => x"81", + 1268 => x"ca", + 1269 => x"3d", + 1270 => x"3d", + 1271 => x"9c", + 1272 => x"ca", + 1273 => x"53", + 1274 => x"fe", + 1275 => x"91", + 1276 => x"84", + 1277 => x"f8", + 1278 => x"7c", + 1279 => x"70", + 1280 => x"75", + 1281 => x"55", + 1282 => x"2e", + 1283 => x"87", + 1284 => x"76", + 1285 => x"73", + 1286 => x"81", + 1287 => x"81", + 1288 => x"77", + 1289 => x"70", + 1290 => x"58", + 1291 => x"09", + 1292 => x"c2", + 1293 => x"81", + 1294 => x"75", + 1295 => x"55", + 1296 => x"e2", + 1297 => x"90", + 1298 => x"f8", + 1299 => x"8f", + 1300 => x"81", + 1301 => x"75", + 1302 => x"55", + 1303 => x"81", + 1304 => x"27", + 1305 => x"d0", + 1306 => x"55", + 1307 => x"73", + 1308 => x"80", + 1309 => x"14", + 1310 => x"72", + 1311 => x"e0", + 1312 => x"80", + 1313 => x"39", + 1314 => x"55", + 1315 => x"80", + 1316 => x"e0", + 1317 => x"38", + 1318 => x"81", + 1319 => x"53", + 1320 => x"81", + 1321 => x"53", + 1322 => x"8e", + 1323 => x"70", + 1324 => x"55", + 1325 => x"27", + 1326 => x"77", + 1327 => x"74", + 1328 => x"76", + 1329 => x"77", + 1330 => x"70", + 1331 => x"55", + 1332 => x"77", + 1333 => x"38", + 1334 => x"74", + 1335 => x"55", + 1336 => x"88", + 1337 => x"0d", + 1338 => x"0d", + 1339 => x"56", + 1340 => x"0c", + 1341 => x"70", + 1342 => x"73", + 1343 => x"81", + 1344 => x"81", + 1345 => x"ed", + 1346 => x"2e", + 1347 => x"8e", + 1348 => x"08", + 1349 => x"76", + 1350 => x"56", + 1351 => x"b0", + 1352 => x"06", + 1353 => x"75", + 1354 => x"76", + 1355 => x"70", + 1356 => x"73", + 1357 => x"8b", + 1358 => x"73", + 1359 => x"85", + 1360 => x"82", + 1361 => x"76", + 1362 => x"70", + 1363 => x"ac", + 1364 => x"a0", + 1365 => x"fa", + 1366 => x"53", + 1367 => x"57", + 1368 => x"98", + 1369 => x"39", + 1370 => x"80", + 1371 => x"26", + 1372 => x"86", + 1373 => x"80", + 1374 => x"57", + 1375 => x"74", + 1376 => x"38", + 1377 => x"27", + 1378 => x"14", + 1379 => x"06", + 1380 => x"14", + 1381 => x"06", + 1382 => x"74", + 1383 => x"f9", + 1384 => x"ff", + 1385 => x"89", + 1386 => x"38", + 1387 => x"c5", + 1388 => x"29", + 1389 => x"81", + 1390 => x"76", + 1391 => x"56", + 1392 => x"ba", + 1393 => x"2e", + 1394 => x"30", + 1395 => x"0c", + 1396 => x"91", + 1397 => x"8a", + 1398 => x"ff", + 1399 => x"8f", + 1400 => x"81", + 1401 => x"26", + 1402 => x"c7", + 1403 => x"52", + 1404 => x"88", + 1405 => x"0d", + 1406 => x"0d", + 1407 => x"33", + 1408 => x"9f", + 1409 => x"53", + 1410 => x"81", + 1411 => x"38", + 1412 => x"87", + 1413 => x"11", + 1414 => x"54", + 1415 => x"84", + 1416 => x"54", + 1417 => x"87", + 1418 => x"11", + 1419 => x"0c", + 1420 => x"c0", + 1421 => x"70", + 1422 => x"70", + 1423 => x"51", + 1424 => x"8a", + 1425 => x"98", + 1426 => x"70", + 1427 => x"08", + 1428 => x"06", + 1429 => x"38", + 1430 => x"8c", + 1431 => x"80", + 1432 => x"71", + 1433 => x"14", + 1434 => x"a4", + 1435 => x"70", + 1436 => x"0c", + 1437 => x"04", + 1438 => x"60", + 1439 => x"8c", + 1440 => x"33", + 1441 => x"5b", + 1442 => x"5a", + 1443 => x"91", + 1444 => x"81", + 1445 => x"52", + 1446 => x"38", + 1447 => x"84", + 1448 => x"92", + 1449 => x"c0", + 1450 => x"87", + 1451 => x"13", + 1452 => x"57", + 1453 => x"0b", + 1454 => x"8c", + 1455 => x"0c", + 1456 => x"75", + 1457 => x"2a", + 1458 => x"51", + 1459 => x"80", + 1460 => x"7b", + 1461 => x"7b", + 1462 => x"5d", + 1463 => x"59", + 1464 => x"06", + 1465 => x"73", + 1466 => x"81", + 1467 => x"ff", + 1468 => x"72", + 1469 => x"38", + 1470 => x"8c", + 1471 => x"c3", + 1472 => x"98", + 1473 => x"71", + 1474 => x"38", + 1475 => x"2e", + 1476 => x"76", + 1477 => x"92", + 1478 => x"72", + 1479 => x"06", + 1480 => x"f7", + 1481 => x"5a", + 1482 => x"80", + 1483 => x"70", + 1484 => x"5a", + 1485 => x"80", + 1486 => x"73", + 1487 => x"06", + 1488 => x"38", + 1489 => x"fe", + 1490 => x"fc", + 1491 => x"52", + 1492 => x"83", + 1493 => x"71", + 1494 => x"ca", + 1495 => x"3d", + 1496 => x"3d", + 1497 => x"64", + 1498 => x"bf", + 1499 => x"40", + 1500 => x"59", + 1501 => x"58", + 1502 => x"91", + 1503 => x"81", + 1504 => x"52", + 1505 => x"09", + 1506 => x"b1", + 1507 => x"84", + 1508 => x"92", + 1509 => x"c0", + 1510 => x"87", + 1511 => x"13", + 1512 => x"56", + 1513 => x"87", + 1514 => x"0c", + 1515 => x"82", + 1516 => x"58", + 1517 => x"84", + 1518 => x"06", + 1519 => x"71", + 1520 => x"38", + 1521 => x"05", + 1522 => x"0c", + 1523 => x"73", + 1524 => x"81", + 1525 => x"71", + 1526 => x"38", + 1527 => x"8c", + 1528 => x"d0", + 1529 => x"98", + 1530 => x"71", + 1531 => x"38", + 1532 => x"2e", + 1533 => x"76", + 1534 => x"92", + 1535 => x"72", + 1536 => x"06", + 1537 => x"f7", + 1538 => x"59", + 1539 => x"1a", + 1540 => x"06", + 1541 => x"59", + 1542 => x"80", + 1543 => x"73", + 1544 => x"06", + 1545 => x"38", + 1546 => x"fe", + 1547 => x"fc", + 1548 => x"52", + 1549 => x"83", + 1550 => x"71", + 1551 => x"ca", + 1552 => x"3d", + 1553 => x"3d", + 1554 => x"84", + 1555 => x"33", + 1556 => x"b7", + 1557 => x"54", + 1558 => x"fa", + 1559 => x"ca", + 1560 => x"06", + 1561 => x"72", + 1562 => x"85", + 1563 => x"98", + 1564 => x"56", + 1565 => x"80", + 1566 => x"76", + 1567 => x"74", + 1568 => x"c0", + 1569 => x"54", + 1570 => x"2e", + 1571 => x"d4", + 1572 => x"2e", + 1573 => x"80", + 1574 => x"08", + 1575 => x"70", + 1576 => x"51", + 1577 => x"2e", + 1578 => x"c0", + 1579 => x"52", + 1580 => x"87", + 1581 => x"08", + 1582 => x"38", + 1583 => x"87", + 1584 => x"14", + 1585 => x"70", + 1586 => x"52", + 1587 => x"96", + 1588 => x"92", + 1589 => x"0a", + 1590 => x"39", + 1591 => x"0c", + 1592 => x"39", + 1593 => x"54", + 1594 => x"88", + 1595 => x"0d", + 1596 => x"0d", + 1597 => x"33", + 1598 => x"88", + 1599 => x"ca", + 1600 => x"51", + 1601 => x"04", + 1602 => x"75", + 1603 => x"82", + 1604 => x"90", + 1605 => x"2b", + 1606 => x"33", + 1607 => x"88", + 1608 => x"71", + 1609 => x"88", + 1610 => x"54", + 1611 => x"85", + 1612 => x"ff", + 1613 => x"02", + 1614 => x"05", + 1615 => x"70", + 1616 => x"05", + 1617 => x"88", + 1618 => x"72", + 1619 => x"0d", + 1620 => x"0d", + 1621 => x"52", + 1622 => x"81", + 1623 => x"70", + 1624 => x"70", + 1625 => x"05", + 1626 => x"88", + 1627 => x"72", + 1628 => x"54", + 1629 => x"2a", + 1630 => x"34", + 1631 => x"04", + 1632 => x"76", + 1633 => x"54", + 1634 => x"2e", + 1635 => x"70", + 1636 => x"33", + 1637 => x"05", + 1638 => x"11", + 1639 => x"84", + 1640 => x"fe", + 1641 => x"77", + 1642 => x"53", + 1643 => x"81", + 1644 => x"ff", + 1645 => x"f4", + 1646 => x"0d", + 1647 => x"0d", + 1648 => x"56", + 1649 => x"70", + 1650 => x"33", + 1651 => x"05", + 1652 => x"71", + 1653 => x"56", + 1654 => x"72", + 1655 => x"38", + 1656 => x"e2", + 1657 => x"ca", + 1658 => x"3d", + 1659 => x"3d", + 1660 => x"54", + 1661 => x"71", + 1662 => x"38", + 1663 => x"70", + 1664 => x"f3", + 1665 => x"91", + 1666 => x"84", + 1667 => x"80", + 1668 => x"88", + 1669 => x"0b", + 1670 => x"0c", + 1671 => x"0d", + 1672 => x"0b", + 1673 => x"56", + 1674 => x"2e", + 1675 => x"81", + 1676 => x"08", + 1677 => x"70", + 1678 => x"33", + 1679 => x"a2", + 1680 => x"88", + 1681 => x"09", + 1682 => x"38", + 1683 => x"08", + 1684 => x"b0", + 1685 => x"a4", + 1686 => x"9c", + 1687 => x"56", + 1688 => x"27", + 1689 => x"16", + 1690 => x"82", + 1691 => x"06", + 1692 => x"54", + 1693 => x"78", + 1694 => x"33", + 1695 => x"3f", + 1696 => x"5a", + 1697 => x"88", + 1698 => x"0d", + 1699 => x"0d", + 1700 => x"56", + 1701 => x"b0", + 1702 => x"af", + 1703 => x"fe", + 1704 => x"ca", + 1705 => x"91", + 1706 => x"9f", + 1707 => x"74", + 1708 => x"52", + 1709 => x"51", + 1710 => x"91", + 1711 => x"80", + 1712 => x"ff", + 1713 => x"74", + 1714 => x"76", + 1715 => x"0c", + 1716 => x"04", + 1717 => x"7a", + 1718 => x"fe", + 1719 => x"ca", + 1720 => x"91", + 1721 => x"81", + 1722 => x"33", + 1723 => x"2e", + 1724 => x"80", + 1725 => x"17", + 1726 => x"81", + 1727 => x"06", + 1728 => x"84", + 1729 => x"ca", + 1730 => x"b4", + 1731 => x"56", + 1732 => x"82", + 1733 => x"84", + 1734 => x"fc", + 1735 => x"8b", + 1736 => x"52", + 1737 => x"a9", + 1738 => x"85", + 1739 => x"84", + 1740 => x"fc", + 1741 => x"17", + 1742 => x"9c", + 1743 => x"91", + 1744 => x"08", + 1745 => x"17", + 1746 => x"3f", + 1747 => x"81", + 1748 => x"19", + 1749 => x"53", + 1750 => x"17", + 1751 => x"82", + 1752 => x"18", + 1753 => x"80", + 1754 => x"33", + 1755 => x"3f", + 1756 => x"08", + 1757 => x"38", + 1758 => x"91", + 1759 => x"8a", + 1760 => x"fb", + 1761 => x"fe", + 1762 => x"08", + 1763 => x"56", + 1764 => x"74", + 1765 => x"38", + 1766 => x"75", + 1767 => x"16", + 1768 => x"53", + 1769 => x"88", + 1770 => x"0d", + 1771 => x"0d", + 1772 => x"08", + 1773 => x"81", + 1774 => x"df", + 1775 => x"15", + 1776 => x"d7", + 1777 => x"33", + 1778 => x"82", + 1779 => x"38", + 1780 => x"89", + 1781 => x"2e", + 1782 => x"bf", + 1783 => x"2e", + 1784 => x"81", + 1785 => x"81", + 1786 => x"89", + 1787 => x"08", + 1788 => x"52", + 1789 => x"3f", + 1790 => x"08", + 1791 => x"74", + 1792 => x"14", + 1793 => x"81", + 1794 => x"2a", + 1795 => x"05", + 1796 => x"57", + 1797 => x"f5", + 1798 => x"88", + 1799 => x"38", + 1800 => x"06", + 1801 => x"33", + 1802 => x"78", + 1803 => x"06", + 1804 => x"5c", + 1805 => x"53", + 1806 => x"38", + 1807 => x"06", + 1808 => x"39", + 1809 => x"a4", + 1810 => x"52", + 1811 => x"bd", + 1812 => x"88", + 1813 => x"38", + 1814 => x"fe", + 1815 => x"b4", + 1816 => x"8d", + 1817 => x"88", + 1818 => x"ff", + 1819 => x"39", + 1820 => x"a4", + 1821 => x"52", + 1822 => x"91", + 1823 => x"88", + 1824 => x"76", + 1825 => x"fc", + 1826 => x"b4", + 1827 => x"f8", + 1828 => x"88", + 1829 => x"06", + 1830 => x"81", + 1831 => x"ca", + 1832 => x"3d", + 1833 => x"3d", + 1834 => x"7e", + 1835 => x"82", + 1836 => x"27", + 1837 => x"76", + 1838 => x"27", + 1839 => x"75", + 1840 => x"79", + 1841 => x"38", + 1842 => x"89", + 1843 => x"2e", + 1844 => x"80", + 1845 => x"2e", + 1846 => x"81", + 1847 => x"81", + 1848 => x"89", + 1849 => x"08", + 1850 => x"52", + 1851 => x"3f", + 1852 => x"08", + 1853 => x"88", + 1854 => x"38", + 1855 => x"06", + 1856 => x"81", + 1857 => x"06", + 1858 => x"77", + 1859 => x"2e", + 1860 => x"84", + 1861 => x"06", + 1862 => x"06", + 1863 => x"53", + 1864 => x"81", + 1865 => x"34", + 1866 => x"a4", + 1867 => x"52", + 1868 => x"d9", + 1869 => x"88", + 1870 => x"ca", + 1871 => x"94", + 1872 => x"ff", + 1873 => x"05", + 1874 => x"54", + 1875 => x"38", + 1876 => x"74", + 1877 => x"06", + 1878 => x"07", + 1879 => x"74", + 1880 => x"39", + 1881 => x"a4", + 1882 => x"52", + 1883 => x"9d", + 1884 => x"88", + 1885 => x"ca", + 1886 => x"d8", + 1887 => x"ff", + 1888 => x"76", + 1889 => x"06", + 1890 => x"05", + 1891 => x"3f", + 1892 => x"87", + 1893 => x"08", + 1894 => x"51", + 1895 => x"91", + 1896 => x"59", + 1897 => x"08", + 1898 => x"f0", + 1899 => x"82", + 1900 => x"06", + 1901 => x"05", + 1902 => x"54", + 1903 => x"3f", + 1904 => x"08", + 1905 => x"74", + 1906 => x"51", + 1907 => x"81", + 1908 => x"34", + 1909 => x"88", + 1910 => x"0d", + 1911 => x"0d", + 1912 => x"72", + 1913 => x"56", + 1914 => x"27", + 1915 => x"98", + 1916 => x"9d", + 1917 => x"2e", + 1918 => x"53", + 1919 => x"51", + 1920 => x"91", + 1921 => x"54", + 1922 => x"08", + 1923 => x"93", + 1924 => x"80", + 1925 => x"54", + 1926 => x"91", + 1927 => x"54", + 1928 => x"74", + 1929 => x"fb", + 1930 => x"ca", + 1931 => x"91", + 1932 => x"80", + 1933 => x"38", + 1934 => x"08", + 1935 => x"38", + 1936 => x"08", + 1937 => x"38", + 1938 => x"52", + 1939 => x"d6", + 1940 => x"88", + 1941 => x"98", + 1942 => x"11", + 1943 => x"57", + 1944 => x"74", + 1945 => x"81", + 1946 => x"0c", + 1947 => x"81", + 1948 => x"84", + 1949 => x"55", + 1950 => x"ff", + 1951 => x"54", + 1952 => x"88", + 1953 => x"0d", + 1954 => x"0d", + 1955 => x"08", + 1956 => x"79", + 1957 => x"17", + 1958 => x"80", + 1959 => x"98", + 1960 => x"26", + 1961 => x"58", + 1962 => x"52", + 1963 => x"fd", + 1964 => x"74", + 1965 => x"08", + 1966 => x"38", + 1967 => x"08", + 1968 => x"88", + 1969 => x"82", + 1970 => x"17", + 1971 => x"88", + 1972 => x"c7", + 1973 => x"90", + 1974 => x"56", + 1975 => x"2e", + 1976 => x"77", + 1977 => x"81", + 1978 => x"38", + 1979 => x"98", + 1980 => x"26", + 1981 => x"56", + 1982 => x"51", + 1983 => x"80", + 1984 => x"88", + 1985 => x"09", + 1986 => x"38", + 1987 => x"08", + 1988 => x"88", + 1989 => x"30", + 1990 => x"80", + 1991 => x"07", + 1992 => x"08", + 1993 => x"55", + 1994 => x"ef", + 1995 => x"88", + 1996 => x"95", + 1997 => x"08", + 1998 => x"27", + 1999 => x"98", + 2000 => x"89", + 2001 => x"85", + 2002 => x"db", + 2003 => x"81", + 2004 => x"17", + 2005 => x"89", + 2006 => x"75", + 2007 => x"ac", + 2008 => x"7a", + 2009 => x"3f", + 2010 => x"08", + 2011 => x"38", + 2012 => x"ca", + 2013 => x"2e", + 2014 => x"86", + 2015 => x"88", + 2016 => x"ca", + 2017 => x"70", + 2018 => x"07", + 2019 => x"7c", + 2020 => x"55", + 2021 => x"f8", + 2022 => x"2e", + 2023 => x"ff", + 2024 => x"55", + 2025 => x"ff", + 2026 => x"76", + 2027 => x"3f", + 2028 => x"08", + 2029 => x"08", + 2030 => x"ca", + 2031 => x"80", + 2032 => x"55", + 2033 => x"94", + 2034 => x"2e", + 2035 => x"53", + 2036 => x"51", + 2037 => x"91", + 2038 => x"55", + 2039 => x"75", + 2040 => x"98", + 2041 => x"05", + 2042 => x"56", + 2043 => x"26", + 2044 => x"15", + 2045 => x"84", + 2046 => x"07", + 2047 => x"18", + 2048 => x"ff", + 2049 => x"2e", + 2050 => x"39", + 2051 => x"39", + 2052 => x"08", + 2053 => x"81", + 2054 => x"74", + 2055 => x"0c", + 2056 => x"04", + 2057 => x"7a", + 2058 => x"f3", + 2059 => x"ca", + 2060 => x"81", + 2061 => x"88", + 2062 => x"38", + 2063 => x"51", + 2064 => x"91", + 2065 => x"91", + 2066 => x"b0", + 2067 => x"84", + 2068 => x"52", + 2069 => x"52", + 2070 => x"3f", + 2071 => x"39", + 2072 => x"8a", + 2073 => x"75", + 2074 => x"38", + 2075 => x"19", + 2076 => x"81", + 2077 => x"ed", + 2078 => x"ca", + 2079 => x"2e", + 2080 => x"15", + 2081 => x"70", + 2082 => x"07", + 2083 => x"53", + 2084 => x"75", + 2085 => x"0c", + 2086 => x"04", + 2087 => x"7a", + 2088 => x"58", + 2089 => x"f0", + 2090 => x"80", + 2091 => x"9f", + 2092 => x"80", + 2093 => x"90", + 2094 => x"17", + 2095 => x"aa", + 2096 => x"53", + 2097 => x"88", + 2098 => x"08", + 2099 => x"38", + 2100 => x"53", + 2101 => x"17", + 2102 => x"72", + 2103 => x"fe", + 2104 => x"08", + 2105 => x"80", + 2106 => x"16", + 2107 => x"2b", + 2108 => x"75", + 2109 => x"73", + 2110 => x"f5", + 2111 => x"ca", + 2112 => x"91", + 2113 => x"ff", + 2114 => x"81", + 2115 => x"88", + 2116 => x"38", + 2117 => x"91", + 2118 => x"26", + 2119 => x"58", + 2120 => x"73", + 2121 => x"39", + 2122 => x"51", + 2123 => x"91", + 2124 => x"98", + 2125 => x"94", + 2126 => x"17", + 2127 => x"58", + 2128 => x"9a", + 2129 => x"81", + 2130 => x"74", + 2131 => x"98", + 2132 => x"83", + 2133 => x"b4", + 2134 => x"0c", + 2135 => x"91", + 2136 => x"8a", + 2137 => x"f8", + 2138 => x"70", + 2139 => x"08", + 2140 => x"57", + 2141 => x"0a", + 2142 => x"38", + 2143 => x"15", + 2144 => x"08", + 2145 => x"72", + 2146 => x"cb", + 2147 => x"ff", + 2148 => x"81", + 2149 => x"13", + 2150 => x"94", + 2151 => x"74", + 2152 => x"85", + 2153 => x"22", + 2154 => x"73", + 2155 => x"38", + 2156 => x"8a", + 2157 => x"05", + 2158 => x"06", + 2159 => x"8a", + 2160 => x"73", + 2161 => x"3f", + 2162 => x"08", + 2163 => x"81", + 2164 => x"88", + 2165 => x"ff", + 2166 => x"91", + 2167 => x"ff", + 2168 => x"38", + 2169 => x"91", + 2170 => x"26", + 2171 => x"7b", + 2172 => x"98", + 2173 => x"55", + 2174 => x"94", + 2175 => x"73", + 2176 => x"3f", + 2177 => x"08", + 2178 => x"91", + 2179 => x"80", + 2180 => x"38", + 2181 => x"ca", + 2182 => x"2e", + 2183 => x"55", + 2184 => x"08", + 2185 => x"38", + 2186 => x"08", + 2187 => x"fb", + 2188 => x"ca", + 2189 => x"38", + 2190 => x"0c", + 2191 => x"51", + 2192 => x"91", + 2193 => x"98", + 2194 => x"90", + 2195 => x"16", + 2196 => x"15", + 2197 => x"74", + 2198 => x"0c", + 2199 => x"04", + 2200 => x"7b", + 2201 => x"5b", + 2202 => x"52", + 2203 => x"ac", + 2204 => x"88", + 2205 => x"ca", + 2206 => x"ec", + 2207 => x"88", + 2208 => x"17", + 2209 => x"51", + 2210 => x"91", + 2211 => x"54", + 2212 => x"08", + 2213 => x"91", + 2214 => x"9c", + 2215 => x"33", + 2216 => x"72", + 2217 => x"09", + 2218 => x"38", + 2219 => x"ca", + 2220 => x"72", + 2221 => x"55", + 2222 => x"53", + 2223 => x"8e", + 2224 => x"56", + 2225 => x"09", + 2226 => x"38", + 2227 => x"ca", + 2228 => x"81", + 2229 => x"fd", + 2230 => x"ca", + 2231 => x"91", + 2232 => x"80", + 2233 => x"38", + 2234 => x"09", + 2235 => x"38", + 2236 => x"91", + 2237 => x"8b", + 2238 => x"fd", + 2239 => x"9a", + 2240 => x"eb", + 2241 => x"ca", + 2242 => x"ff", + 2243 => x"70", + 2244 => x"53", + 2245 => x"09", + 2246 => x"38", + 2247 => x"eb", + 2248 => x"ca", + 2249 => x"2b", + 2250 => x"72", + 2251 => x"0c", + 2252 => x"04", + 2253 => x"77", + 2254 => x"ff", + 2255 => x"9a", + 2256 => x"55", + 2257 => x"76", + 2258 => x"53", + 2259 => x"09", + 2260 => x"38", + 2261 => x"52", + 2262 => x"eb", + 2263 => x"3d", + 2264 => x"3d", + 2265 => x"5b", + 2266 => x"08", + 2267 => x"15", + 2268 => x"81", + 2269 => x"15", + 2270 => x"51", + 2271 => x"91", + 2272 => x"58", + 2273 => x"08", + 2274 => x"9c", + 2275 => x"33", + 2276 => x"86", + 2277 => x"80", + 2278 => x"13", + 2279 => x"06", + 2280 => x"06", + 2281 => x"72", + 2282 => x"91", + 2283 => x"53", + 2284 => x"2e", + 2285 => x"53", + 2286 => x"a9", + 2287 => x"74", + 2288 => x"72", + 2289 => x"38", + 2290 => x"99", + 2291 => x"88", + 2292 => x"06", + 2293 => x"88", + 2294 => x"06", + 2295 => x"54", + 2296 => x"a0", + 2297 => x"74", + 2298 => x"3f", + 2299 => x"08", + 2300 => x"88", + 2301 => x"98", + 2302 => x"fa", + 2303 => x"80", + 2304 => x"0c", + 2305 => x"88", + 2306 => x"0d", + 2307 => x"0d", + 2308 => x"57", + 2309 => x"73", + 2310 => x"3f", + 2311 => x"08", + 2312 => x"88", + 2313 => x"98", + 2314 => x"75", + 2315 => x"3f", + 2316 => x"08", + 2317 => x"88", + 2318 => x"a0", + 2319 => x"88", + 2320 => x"14", + 2321 => x"db", + 2322 => x"a0", + 2323 => x"14", + 2324 => x"ac", + 2325 => x"83", + 2326 => x"91", + 2327 => x"87", + 2328 => x"fd", + 2329 => x"70", + 2330 => x"08", + 2331 => x"55", + 2332 => x"3f", + 2333 => x"08", + 2334 => x"13", + 2335 => x"73", + 2336 => x"83", + 2337 => x"3d", + 2338 => x"3d", + 2339 => x"57", + 2340 => x"89", + 2341 => x"17", + 2342 => x"81", + 2343 => x"70", + 2344 => x"55", + 2345 => x"08", + 2346 => x"81", + 2347 => x"52", + 2348 => x"a8", + 2349 => x"2e", + 2350 => x"84", + 2351 => x"52", + 2352 => x"09", + 2353 => x"38", + 2354 => x"81", + 2355 => x"81", + 2356 => x"73", + 2357 => x"55", + 2358 => x"55", + 2359 => x"c5", + 2360 => x"88", + 2361 => x"0b", + 2362 => x"9c", + 2363 => x"8b", + 2364 => x"17", + 2365 => x"08", + 2366 => x"52", + 2367 => x"91", + 2368 => x"76", + 2369 => x"51", + 2370 => x"91", + 2371 => x"86", + 2372 => x"12", + 2373 => x"3f", + 2374 => x"08", + 2375 => x"88", + 2376 => x"f3", + 2377 => x"70", + 2378 => x"80", + 2379 => x"51", + 2380 => x"af", + 2381 => x"81", + 2382 => x"dc", + 2383 => x"74", + 2384 => x"38", + 2385 => x"88", + 2386 => x"39", + 2387 => x"80", + 2388 => x"56", + 2389 => x"af", + 2390 => x"06", + 2391 => x"56", + 2392 => x"32", + 2393 => x"80", + 2394 => x"51", + 2395 => x"dc", + 2396 => x"1c", + 2397 => x"33", + 2398 => x"9f", + 2399 => x"ff", + 2400 => x"1c", + 2401 => x"7a", + 2402 => x"3f", + 2403 => x"08", + 2404 => x"39", + 2405 => x"a0", + 2406 => x"5e", + 2407 => x"52", + 2408 => x"ff", + 2409 => x"59", + 2410 => x"33", + 2411 => x"ae", + 2412 => x"06", + 2413 => x"78", + 2414 => x"81", + 2415 => x"32", + 2416 => x"9f", + 2417 => x"26", + 2418 => x"53", + 2419 => x"73", + 2420 => x"17", + 2421 => x"34", + 2422 => x"db", + 2423 => x"32", + 2424 => x"9f", + 2425 => x"54", + 2426 => x"2e", + 2427 => x"80", + 2428 => x"75", + 2429 => x"bd", + 2430 => x"7e", + 2431 => x"a0", + 2432 => x"bd", + 2433 => x"82", + 2434 => x"18", + 2435 => x"1a", + 2436 => x"a0", + 2437 => x"fc", + 2438 => x"32", + 2439 => x"80", + 2440 => x"30", + 2441 => x"71", + 2442 => x"51", + 2443 => x"55", + 2444 => x"ac", + 2445 => x"81", + 2446 => x"78", + 2447 => x"51", + 2448 => x"af", + 2449 => x"06", + 2450 => x"55", + 2451 => x"32", + 2452 => x"80", + 2453 => x"51", + 2454 => x"db", + 2455 => x"39", + 2456 => x"09", + 2457 => x"38", + 2458 => x"7c", + 2459 => x"54", + 2460 => x"a2", + 2461 => x"32", + 2462 => x"ae", + 2463 => x"72", + 2464 => x"9f", + 2465 => x"51", + 2466 => x"74", + 2467 => x"88", + 2468 => x"fe", + 2469 => x"98", + 2470 => x"80", + 2471 => x"75", + 2472 => x"91", + 2473 => x"33", + 2474 => x"51", + 2475 => x"91", + 2476 => x"80", + 2477 => x"78", + 2478 => x"81", + 2479 => x"5a", + 2480 => x"d2", + 2481 => x"88", + 2482 => x"80", + 2483 => x"1c", + 2484 => x"27", + 2485 => x"79", + 2486 => x"74", + 2487 => x"7a", + 2488 => x"74", + 2489 => x"39", + 2490 => x"b8", + 2491 => x"fe", + 2492 => x"88", + 2493 => x"ff", + 2494 => x"73", + 2495 => x"38", + 2496 => x"81", + 2497 => x"54", + 2498 => x"75", + 2499 => x"17", + 2500 => x"39", + 2501 => x"0c", + 2502 => x"99", + 2503 => x"54", + 2504 => x"2e", + 2505 => x"84", + 2506 => x"34", + 2507 => x"76", + 2508 => x"8b", + 2509 => x"81", + 2510 => x"56", + 2511 => x"80", + 2512 => x"1b", + 2513 => x"08", + 2514 => x"51", + 2515 => x"91", + 2516 => x"56", + 2517 => x"08", + 2518 => x"98", + 2519 => x"76", + 2520 => x"3f", + 2521 => x"08", + 2522 => x"88", + 2523 => x"38", + 2524 => x"70", + 2525 => x"73", + 2526 => x"be", + 2527 => x"33", + 2528 => x"73", + 2529 => x"8b", + 2530 => x"83", + 2531 => x"06", + 2532 => x"73", + 2533 => x"53", + 2534 => x"51", + 2535 => x"91", + 2536 => x"80", + 2537 => x"75", + 2538 => x"f3", + 2539 => x"9f", + 2540 => x"1c", + 2541 => x"74", + 2542 => x"38", + 2543 => x"09", + 2544 => x"e7", + 2545 => x"2a", + 2546 => x"77", + 2547 => x"51", + 2548 => x"2e", + 2549 => x"81", + 2550 => x"80", + 2551 => x"38", + 2552 => x"ab", + 2553 => x"55", + 2554 => x"75", + 2555 => x"73", + 2556 => x"55", + 2557 => x"82", + 2558 => x"06", + 2559 => x"ab", + 2560 => x"33", + 2561 => x"70", + 2562 => x"55", + 2563 => x"2e", + 2564 => x"1b", + 2565 => x"06", + 2566 => x"52", + 2567 => x"db", + 2568 => x"88", + 2569 => x"0c", + 2570 => x"74", + 2571 => x"0c", + 2572 => x"04", + 2573 => x"7c", + 2574 => x"08", + 2575 => x"55", + 2576 => x"59", + 2577 => x"81", + 2578 => x"70", + 2579 => x"33", + 2580 => x"52", + 2581 => x"2e", + 2582 => x"ee", + 2583 => x"2e", + 2584 => x"81", + 2585 => x"33", + 2586 => x"81", + 2587 => x"52", + 2588 => x"26", + 2589 => x"14", + 2590 => x"06", + 2591 => x"52", + 2592 => x"80", + 2593 => x"0b", + 2594 => x"59", + 2595 => x"7a", + 2596 => x"70", + 2597 => x"33", + 2598 => x"05", + 2599 => x"9f", + 2600 => x"53", + 2601 => x"89", + 2602 => x"70", + 2603 => x"54", + 2604 => x"12", + 2605 => x"26", + 2606 => x"12", + 2607 => x"06", + 2608 => x"30", + 2609 => x"51", + 2610 => x"2e", + 2611 => x"85", + 2612 => x"be", + 2613 => x"74", + 2614 => x"30", + 2615 => x"9f", + 2616 => x"2a", + 2617 => x"54", + 2618 => x"2e", + 2619 => x"15", + 2620 => x"55", + 2621 => x"ff", + 2622 => x"39", + 2623 => x"86", + 2624 => x"7c", + 2625 => x"51", + 2626 => x"ca", + 2627 => x"70", + 2628 => x"0c", + 2629 => x"04", + 2630 => x"78", + 2631 => x"83", + 2632 => x"0b", + 2633 => x"79", + 2634 => x"e2", + 2635 => x"55", + 2636 => x"08", + 2637 => x"84", + 2638 => x"df", + 2639 => x"ca", + 2640 => x"ff", + 2641 => x"83", + 2642 => x"d4", + 2643 => x"81", + 2644 => x"38", + 2645 => x"17", + 2646 => x"74", + 2647 => x"09", + 2648 => x"38", + 2649 => x"81", + 2650 => x"30", + 2651 => x"79", + 2652 => x"54", + 2653 => x"74", + 2654 => x"09", + 2655 => x"38", + 2656 => x"b8", + 2657 => x"ea", + 2658 => x"b1", + 2659 => x"88", + 2660 => x"ca", + 2661 => x"2e", + 2662 => x"53", + 2663 => x"52", + 2664 => x"51", + 2665 => x"91", + 2666 => x"55", + 2667 => x"08", + 2668 => x"38", + 2669 => x"91", + 2670 => x"88", + 2671 => x"f2", + 2672 => x"02", + 2673 => x"cb", + 2674 => x"55", + 2675 => x"60", + 2676 => x"3f", + 2677 => x"08", + 2678 => x"80", + 2679 => x"88", + 2680 => x"fc", + 2681 => x"88", + 2682 => x"91", + 2683 => x"70", + 2684 => x"8c", + 2685 => x"2e", + 2686 => x"73", + 2687 => x"81", + 2688 => x"33", + 2689 => x"80", + 2690 => x"81", + 2691 => x"d7", + 2692 => x"ca", + 2693 => x"ff", + 2694 => x"06", + 2695 => x"98", + 2696 => x"2e", + 2697 => x"74", + 2698 => x"81", + 2699 => x"8a", + 2700 => x"ac", + 2701 => x"39", + 2702 => x"77", + 2703 => x"81", + 2704 => x"33", + 2705 => x"3f", + 2706 => x"08", + 2707 => x"70", + 2708 => x"55", + 2709 => x"86", + 2710 => x"80", + 2711 => x"74", + 2712 => x"81", + 2713 => x"8a", + 2714 => x"f4", + 2715 => x"53", + 2716 => x"fd", + 2717 => x"ca", + 2718 => x"ff", + 2719 => x"82", + 2720 => x"06", + 2721 => x"8c", + 2722 => x"58", + 2723 => x"f6", + 2724 => x"58", + 2725 => x"2e", + 2726 => x"fa", + 2727 => x"e8", + 2728 => x"88", + 2729 => x"78", + 2730 => x"5a", + 2731 => x"90", + 2732 => x"75", + 2733 => x"38", + 2734 => x"3d", + 2735 => x"70", + 2736 => x"08", + 2737 => x"7a", + 2738 => x"38", + 2739 => x"51", + 2740 => x"91", + 2741 => x"81", + 2742 => x"81", + 2743 => x"38", + 2744 => x"83", + 2745 => x"38", + 2746 => x"84", + 2747 => x"38", + 2748 => x"81", + 2749 => x"38", + 2750 => x"db", + 2751 => x"ca", + 2752 => x"ff", + 2753 => x"72", + 2754 => x"09", + 2755 => x"d0", + 2756 => x"14", + 2757 => x"3f", + 2758 => x"08", + 2759 => x"06", + 2760 => x"38", + 2761 => x"51", + 2762 => x"91", + 2763 => x"58", + 2764 => x"0c", + 2765 => x"33", + 2766 => x"80", + 2767 => x"ff", + 2768 => x"ff", + 2769 => x"55", + 2770 => x"81", + 2771 => x"38", + 2772 => x"06", + 2773 => x"80", + 2774 => x"52", + 2775 => x"8a", + 2776 => x"80", + 2777 => x"ff", + 2778 => x"53", + 2779 => x"86", + 2780 => x"83", + 2781 => x"c5", + 2782 => x"f5", + 2783 => x"88", + 2784 => x"ca", + 2785 => x"15", + 2786 => x"06", + 2787 => x"76", + 2788 => x"80", + 2789 => x"da", + 2790 => x"ca", + 2791 => x"ff", + 2792 => x"74", + 2793 => x"d4", + 2794 => x"dc", + 2795 => x"88", + 2796 => x"c2", + 2797 => x"b9", + 2798 => x"88", + 2799 => x"ff", + 2800 => x"56", + 2801 => x"83", + 2802 => x"14", + 2803 => x"71", + 2804 => x"5a", + 2805 => x"26", + 2806 => x"8a", + 2807 => x"74", + 2808 => x"ff", + 2809 => x"91", + 2810 => x"55", + 2811 => x"08", + 2812 => x"ec", + 2813 => x"88", + 2814 => x"ff", + 2815 => x"83", + 2816 => x"74", + 2817 => x"26", + 2818 => x"57", + 2819 => x"26", + 2820 => x"57", + 2821 => x"56", + 2822 => x"82", + 2823 => x"15", + 2824 => x"0c", + 2825 => x"0c", + 2826 => x"a4", + 2827 => x"1d", + 2828 => x"54", + 2829 => x"2e", + 2830 => x"af", + 2831 => x"14", + 2832 => x"3f", + 2833 => x"08", + 2834 => x"06", + 2835 => x"72", + 2836 => x"79", + 2837 => x"80", + 2838 => x"d9", + 2839 => x"ca", + 2840 => x"15", + 2841 => x"2b", + 2842 => x"8d", + 2843 => x"2e", + 2844 => x"77", + 2845 => x"0c", + 2846 => x"76", + 2847 => x"38", + 2848 => x"70", + 2849 => x"81", + 2850 => x"53", + 2851 => x"89", + 2852 => x"56", + 2853 => x"08", + 2854 => x"38", + 2855 => x"15", + 2856 => x"8c", + 2857 => x"80", + 2858 => x"34", + 2859 => x"09", + 2860 => x"92", + 2861 => x"14", + 2862 => x"3f", + 2863 => x"08", + 2864 => x"06", + 2865 => x"2e", + 2866 => x"80", + 2867 => x"1b", + 2868 => x"db", + 2869 => x"ca", + 2870 => x"ea", + 2871 => x"88", + 2872 => x"34", + 2873 => x"51", + 2874 => x"91", + 2875 => x"83", + 2876 => x"53", + 2877 => x"d5", + 2878 => x"06", + 2879 => x"b4", + 2880 => x"84", + 2881 => x"88", + 2882 => x"85", + 2883 => x"09", + 2884 => x"38", + 2885 => x"51", + 2886 => x"91", + 2887 => x"86", + 2888 => x"f2", + 2889 => x"06", + 2890 => x"9c", + 2891 => x"d8", + 2892 => x"88", + 2893 => x"0c", + 2894 => x"51", + 2895 => x"91", + 2896 => x"8c", + 2897 => x"74", + 2898 => x"b4", + 2899 => x"53", + 2900 => x"b4", + 2901 => x"15", + 2902 => x"94", + 2903 => x"56", + 2904 => x"88", + 2905 => x"0d", + 2906 => x"0d", + 2907 => x"55", + 2908 => x"b9", + 2909 => x"53", + 2910 => x"b1", + 2911 => x"52", + 2912 => x"a9", + 2913 => x"22", + 2914 => x"57", + 2915 => x"2e", + 2916 => x"99", + 2917 => x"33", + 2918 => x"3f", + 2919 => x"08", + 2920 => x"71", + 2921 => x"74", + 2922 => x"83", + 2923 => x"78", + 2924 => x"52", + 2925 => x"88", + 2926 => x"0d", + 2927 => x"0d", + 2928 => x"33", + 2929 => x"3d", + 2930 => x"56", + 2931 => x"8b", + 2932 => x"91", + 2933 => x"24", + 2934 => x"ca", + 2935 => x"29", + 2936 => x"05", + 2937 => x"55", + 2938 => x"84", + 2939 => x"34", + 2940 => x"80", + 2941 => x"80", + 2942 => x"75", + 2943 => x"75", + 2944 => x"38", + 2945 => x"3d", + 2946 => x"05", + 2947 => x"3f", + 2948 => x"08", + 2949 => x"ca", + 2950 => x"3d", + 2951 => x"3d", + 2952 => x"84", + 2953 => x"05", + 2954 => x"89", + 2955 => x"2e", + 2956 => x"77", + 2957 => x"54", + 2958 => x"05", + 2959 => x"84", + 2960 => x"f6", + 2961 => x"ca", + 2962 => x"91", + 2963 => x"84", + 2964 => x"5c", + 2965 => x"3d", + 2966 => x"ed", + 2967 => x"ca", + 2968 => x"91", + 2969 => x"92", + 2970 => x"d7", + 2971 => x"98", + 2972 => x"73", + 2973 => x"38", + 2974 => x"9c", + 2975 => x"80", + 2976 => x"38", + 2977 => x"95", + 2978 => x"2e", + 2979 => x"aa", + 2980 => x"ea", + 2981 => x"ca", + 2982 => x"9e", + 2983 => x"05", + 2984 => x"54", + 2985 => x"38", + 2986 => x"70", + 2987 => x"54", + 2988 => x"8e", + 2989 => x"83", + 2990 => x"88", + 2991 => x"83", + 2992 => x"83", + 2993 => x"06", + 2994 => x"80", + 2995 => x"38", + 2996 => x"51", + 2997 => x"91", + 2998 => x"56", + 2999 => x"0a", + 3000 => x"05", + 3001 => x"3f", + 3002 => x"0b", + 3003 => x"80", + 3004 => x"7a", + 3005 => x"3f", + 3006 => x"9c", + 3007 => x"d1", + 3008 => x"81", + 3009 => x"34", + 3010 => x"80", + 3011 => x"b0", + 3012 => x"54", + 3013 => x"52", + 3014 => x"05", + 3015 => x"3f", + 3016 => x"08", + 3017 => x"88", + 3018 => x"38", + 3019 => x"82", + 3020 => x"b2", + 3021 => x"84", + 3022 => x"06", + 3023 => x"73", + 3024 => x"38", + 3025 => x"ad", + 3026 => x"2a", + 3027 => x"51", + 3028 => x"2e", + 3029 => x"81", + 3030 => x"80", + 3031 => x"87", + 3032 => x"39", + 3033 => x"51", + 3034 => x"91", + 3035 => x"7b", + 3036 => x"12", + 3037 => x"91", + 3038 => x"81", + 3039 => x"83", + 3040 => x"06", + 3041 => x"80", + 3042 => x"77", + 3043 => x"58", + 3044 => x"08", + 3045 => x"63", + 3046 => x"63", + 3047 => x"57", + 3048 => x"91", + 3049 => x"91", + 3050 => x"88", + 3051 => x"9c", + 3052 => x"d2", + 3053 => x"ca", + 3054 => x"ca", + 3055 => x"1b", + 3056 => x"0c", + 3057 => x"22", + 3058 => x"77", + 3059 => x"80", + 3060 => x"34", + 3061 => x"1a", + 3062 => x"94", + 3063 => x"85", + 3064 => x"06", + 3065 => x"80", + 3066 => x"38", + 3067 => x"08", + 3068 => x"84", + 3069 => x"88", + 3070 => x"0c", + 3071 => x"70", + 3072 => x"52", + 3073 => x"39", + 3074 => x"51", + 3075 => x"91", + 3076 => x"57", + 3077 => x"08", + 3078 => x"38", + 3079 => x"ca", + 3080 => x"2e", + 3081 => x"83", + 3082 => x"75", + 3083 => x"74", + 3084 => x"07", + 3085 => x"54", + 3086 => x"8a", + 3087 => x"75", + 3088 => x"73", + 3089 => x"98", + 3090 => x"a9", + 3091 => x"ff", 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x"88", + 3151 => x"ff", + 3152 => x"ca", + 3153 => x"7c", + 3154 => x"57", + 3155 => x"80", + 3156 => x"1a", + 3157 => x"22", + 3158 => x"75", + 3159 => x"38", + 3160 => x"58", + 3161 => x"53", + 3162 => x"1b", + 3163 => x"88", + 3164 => x"88", + 3165 => x"38", + 3166 => x"33", + 3167 => x"80", + 3168 => x"b0", + 3169 => x"31", + 3170 => x"27", + 3171 => x"80", + 3172 => x"52", + 3173 => x"77", + 3174 => x"7d", + 3175 => x"e0", + 3176 => x"2b", + 3177 => x"76", + 3178 => x"94", + 3179 => x"ff", + 3180 => x"71", + 3181 => x"7b", + 3182 => x"38", + 3183 => x"19", + 3184 => x"51", + 3185 => x"91", + 3186 => x"fe", + 3187 => x"53", + 3188 => x"83", + 3189 => x"b4", + 3190 => x"51", + 3191 => x"7b", + 3192 => x"08", + 3193 => x"76", + 3194 => x"08", + 3195 => x"0c", + 3196 => x"f3", + 3197 => x"75", + 3198 => x"0c", + 3199 => x"04", + 3200 => x"60", + 3201 => x"40", + 3202 => x"80", + 3203 => x"3d", + 3204 => x"77", + 3205 => x"3f", + 3206 => x"08", + 3207 => x"88", + 3208 => x"91", + 3209 => x"74", + 3210 => x"38", + 3211 => x"b8", + 3212 => x"33", + 3213 => x"70", + 3214 => x"56", + 3215 => x"74", + 3216 => x"a4", + 3217 => x"82", + 3218 => x"34", + 3219 => x"98", + 3220 => x"91", + 3221 => x"56", + 3222 => x"94", + 3223 => x"11", + 3224 => x"76", + 3225 => x"75", + 3226 => x"80", + 3227 => x"38", + 3228 => x"70", + 3229 => x"56", + 3230 => x"fd", + 3231 => x"11", + 3232 => x"77", + 3233 => x"5c", + 3234 => x"38", + 3235 => x"88", + 3236 => x"74", + 3237 => x"52", + 3238 => x"18", + 3239 => x"51", + 3240 => x"91", + 3241 => x"55", + 3242 => x"08", + 3243 => x"ab", + 3244 => x"2e", + 3245 => x"74", + 3246 => x"95", + 3247 => x"19", + 3248 => x"08", + 3249 => x"88", + 3250 => x"55", + 3251 => x"9c", + 3252 => x"09", + 3253 => x"38", + 3254 => x"c1", + 3255 => x"88", + 3256 => x"38", + 3257 => x"52", + 3258 => x"97", + 3259 => x"88", + 3260 => x"fe", + 3261 => x"ca", + 3262 => x"7c", + 3263 => x"57", + 3264 => x"80", + 3265 => x"1b", + 3266 => x"22", + 3267 => x"75", + 3268 => x"38", + 3269 => x"59", + 3270 => x"53", + 3271 => x"1a", + 3272 => x"be", + 3273 => x"88", + 3274 => x"38", + 3275 => x"08", + 3276 => x"56", + 3277 => x"9b", + 3278 => x"53", + 3279 => x"77", + 3280 => x"7d", + 3281 => x"16", + 3282 => x"3f", + 3283 => x"0b", + 3284 => x"78", + 3285 => x"80", + 3286 => x"18", + 3287 => x"08", + 3288 => x"7e", + 3289 => x"3f", + 3290 => x"08", + 3291 => x"7e", + 3292 => x"0c", + 3293 => x"19", + 3294 => x"08", + 3295 => x"84", + 3296 => x"57", + 3297 => x"27", + 3298 => x"56", + 3299 => x"52", + 3300 => x"f9", + 3301 => x"88", + 3302 => x"38", + 3303 => x"52", + 3304 => x"83", + 3305 => x"b4", + 3306 => x"d4", + 3307 => x"81", + 3308 => x"34", + 3309 => x"7e", + 3310 => x"0c", + 3311 => x"1a", + 3312 => x"94", + 3313 => x"1b", + 3314 => x"5e", + 3315 => x"27", + 3316 => x"55", + 3317 => x"0c", + 3318 => x"90", + 3319 => x"c0", + 3320 => x"90", + 3321 => x"56", + 3322 => x"88", + 3323 => x"0d", + 3324 => x"0d", + 3325 => x"fc", + 3326 => x"52", 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x"91", + 3386 => x"83", + 3387 => x"ef", + 3388 => x"53", + 3389 => x"05", + 3390 => x"51", + 3391 => x"91", + 3392 => x"55", + 3393 => x"08", + 3394 => x"76", + 3395 => x"93", + 3396 => x"51", + 3397 => x"91", + 3398 => x"55", + 3399 => x"08", + 3400 => x"80", + 3401 => x"70", + 3402 => x"56", + 3403 => x"89", + 3404 => x"94", + 3405 => x"b2", + 3406 => x"05", + 3407 => x"2a", + 3408 => x"51", + 3409 => x"80", + 3410 => x"76", + 3411 => x"52", + 3412 => x"3f", + 3413 => x"08", + 3414 => x"8e", + 3415 => x"88", + 3416 => x"09", + 3417 => x"38", + 3418 => x"91", + 3419 => x"93", + 3420 => x"e4", + 3421 => x"6f", + 3422 => x"7a", + 3423 => x"9e", + 3424 => x"05", + 3425 => x"51", + 3426 => x"91", + 3427 => x"57", + 3428 => x"08", + 3429 => x"7b", + 3430 => x"94", + 3431 => x"55", + 3432 => x"73", + 3433 => x"ed", + 3434 => x"93", + 3435 => x"55", + 3436 => x"91", + 3437 => x"57", + 3438 => x"08", + 3439 => x"68", + 3440 => x"c9", + 3441 => x"ca", + 3442 => x"91", + 3443 => x"82", + 3444 => x"52", + 3445 => x"a3", + 3446 => x"88", + 3447 => x"52", + 3448 => x"b8", + 3449 => x"88", + 3450 => x"ca", + 3451 => x"a2", + 3452 => x"74", + 3453 => x"3f", + 3454 => x"08", + 3455 => x"88", + 3456 => x"69", + 3457 => x"d9", + 3458 => x"91", + 3459 => x"2e", + 3460 => x"52", + 3461 => x"cf", + 3462 => x"88", + 3463 => x"ca", + 3464 => x"2e", + 3465 => x"84", + 3466 => x"06", + 3467 => x"57", + 3468 => x"76", + 3469 => x"9e", + 3470 => x"05", + 3471 => x"dc", + 3472 => x"90", + 3473 => x"81", + 3474 => x"56", + 3475 => x"80", + 3476 => x"02", + 3477 => x"81", + 3478 => x"70", + 3479 => x"56", + 3480 => x"81", + 3481 => x"78", + 3482 => x"38", + 3483 => x"99", + 3484 => x"81", + 3485 => x"18", + 3486 => x"18", + 3487 => x"58", + 3488 => x"33", + 3489 => x"ee", + 3490 => x"6f", + 3491 => x"af", + 3492 => x"8d", + 3493 => x"2e", + 3494 => x"8a", + 3495 => x"6f", + 3496 => x"af", + 3497 => x"0b", + 3498 => x"33", + 3499 => x"91", + 3500 => x"70", + 3501 => x"52", + 3502 => x"56", + 3503 => x"8d", + 3504 => x"70", + 3505 => x"51", + 3506 => x"f5", + 3507 => x"54", + 3508 => x"a7", + 3509 => x"74", + 3510 => x"38", + 3511 => x"73", + 3512 => x"81", + 3513 => x"81", + 3514 => x"39", + 3515 => x"81", + 3516 => x"74", + 3517 => x"81", + 3518 => x"91", + 3519 => x"6e", + 3520 => x"59", + 3521 => x"7a", + 3522 => x"5c", + 3523 => x"26", + 3524 => x"7a", + 3525 => x"ca", + 3526 => x"3d", + 3527 => x"3d", + 3528 => x"8d", + 3529 => x"54", + 3530 => x"55", + 3531 => x"91", + 3532 => x"53", + 3533 => x"08", + 3534 => x"91", + 3535 => x"72", + 3536 => x"8c", + 3537 => x"73", + 3538 => x"38", + 3539 => x"70", + 3540 => x"81", + 3541 => x"57", + 3542 => x"73", + 3543 => x"08", + 3544 => x"94", + 3545 => x"75", + 3546 => x"97", + 3547 => x"11", + 3548 => x"2b", + 3549 => x"73", + 3550 => x"38", + 3551 => x"16", + 3552 => x"e5", + 3553 => x"88", + 3554 => x"78", + 3555 => x"55", + 3556 => x"d5", + 3557 => x"88", + 3558 => x"96", + 3559 => x"70", + 3560 => x"94", + 3561 => x"71", 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x"15", + 3621 => x"07", + 3622 => x"16", + 3623 => x"ff", + 3624 => x"80", + 3625 => x"77", + 3626 => x"2e", + 3627 => x"9c", + 3628 => x"53", + 3629 => x"88", + 3630 => x"0d", + 3631 => x"0d", + 3632 => x"54", + 3633 => x"81", + 3634 => x"53", + 3635 => x"05", + 3636 => x"84", + 3637 => x"e7", + 3638 => x"88", + 3639 => x"ca", + 3640 => x"ea", + 3641 => x"0c", + 3642 => x"51", + 3643 => x"91", + 3644 => x"55", + 3645 => x"08", + 3646 => x"ab", + 3647 => x"98", + 3648 => x"80", + 3649 => x"38", + 3650 => x"70", + 3651 => x"81", + 3652 => x"57", + 3653 => x"ad", + 3654 => x"08", + 3655 => x"d3", + 3656 => x"ca", + 3657 => x"17", + 3658 => x"86", + 3659 => x"17", + 3660 => x"75", + 3661 => x"3f", + 3662 => x"08", + 3663 => x"2e", + 3664 => x"85", + 3665 => x"86", + 3666 => x"2e", + 3667 => x"76", + 3668 => x"73", + 3669 => x"0c", + 3670 => x"04", + 3671 => x"76", + 3672 => x"05", + 3673 => x"53", + 3674 => x"91", + 3675 => x"87", + 3676 => x"88", + 3677 => x"86", + 3678 => x"fb", + 3679 => x"79", + 3680 => x"05", + 3681 => x"56", + 3682 => x"3f", + 3683 => x"08", + 3684 => x"88", + 3685 => x"38", + 3686 => x"91", + 3687 => x"52", + 3688 => x"f8", + 3689 => x"88", + 3690 => x"ca", + 3691 => x"88", + 3692 => x"51", + 3693 => x"91", + 3694 => x"53", + 3695 => x"08", + 3696 => x"81", + 3697 => x"80", + 3698 => x"91", + 3699 => x"a6", + 3700 => x"73", + 3701 => x"3f", + 3702 => x"51", + 3703 => x"91", + 3704 => x"84", + 3705 => x"70", + 3706 => x"2c", + 3707 => x"88", + 3708 => x"51", + 3709 => x"91", + 3710 => x"87", + 3711 => x"ee", + 3712 => x"57", + 3713 => x"3d", + 3714 => x"3d", + 3715 => x"af", + 3716 => x"88", + 3717 => x"ca", + 3718 => x"38", + 3719 => x"51", + 3720 => x"91", + 3721 => x"55", + 3722 => x"08", + 3723 => x"80", + 3724 => x"70", + 3725 => x"58", + 3726 => x"85", + 3727 => x"8d", + 3728 => x"2e", + 3729 => x"52", + 3730 => x"be", + 3731 => x"ca", + 3732 => x"3d", + 3733 => x"3d", + 3734 => x"55", + 3735 => x"92", + 3736 => x"52", + 3737 => x"de", + 3738 => x"ca", + 3739 => x"91", + 3740 => x"82", + 3741 => x"74", + 3742 => x"98", + 3743 => x"11", + 3744 => x"59", + 3745 => x"75", + 3746 => x"38", + 3747 => x"81", + 3748 => x"5b", + 3749 => x"82", + 3750 => x"39", + 3751 => x"08", + 3752 => x"59", + 3753 => x"09", + 3754 => x"38", + 3755 => x"57", + 3756 => x"3d", + 3757 => x"c1", + 3758 => x"ca", + 3759 => x"2e", + 3760 => x"ca", + 3761 => x"2e", + 3762 => x"ca", + 3763 => x"70", + 3764 => x"08", + 3765 => x"7a", + 3766 => x"7f", + 3767 => x"54", + 3768 => x"77", + 3769 => x"80", + 3770 => x"15", + 3771 => x"88", + 3772 => x"75", + 3773 => x"52", + 3774 => x"52", + 3775 => x"8d", + 3776 => x"88", + 3777 => x"ca", + 3778 => x"d6", + 3779 => x"33", + 3780 => x"1a", + 3781 => x"54", + 3782 => x"09", + 3783 => x"38", + 3784 => x"ff", + 3785 => x"91", + 3786 => x"83", + 3787 => x"70", + 3788 => x"25", + 3789 => x"59", + 3790 => x"9b", + 3791 => x"51", + 3792 => x"3f", + 3793 => x"08", + 3794 => x"70", + 3795 => x"25", + 3796 => x"59", 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x"34", + 3856 => x"91", + 3857 => x"89", + 3858 => x"e2", + 3859 => x"53", + 3860 => x"a4", + 3861 => x"3d", + 3862 => x"3f", + 3863 => x"08", + 3864 => x"88", + 3865 => x"38", + 3866 => x"3d", + 3867 => x"3d", + 3868 => x"d1", + 3869 => x"ca", + 3870 => x"91", + 3871 => x"81", + 3872 => x"80", + 3873 => x"70", + 3874 => x"81", + 3875 => x"56", + 3876 => x"81", + 3877 => x"98", + 3878 => x"74", + 3879 => x"38", + 3880 => x"05", + 3881 => x"06", + 3882 => x"55", + 3883 => x"38", + 3884 => x"51", + 3885 => x"91", + 3886 => x"74", + 3887 => x"81", + 3888 => x"56", + 3889 => x"80", + 3890 => x"54", + 3891 => x"08", + 3892 => x"2e", + 3893 => x"73", + 3894 => x"88", + 3895 => x"52", + 3896 => x"52", + 3897 => x"3f", + 3898 => x"08", + 3899 => x"88", + 3900 => x"38", + 3901 => x"08", + 3902 => x"cc", + 3903 => x"ca", + 3904 => x"91", + 3905 => x"86", + 3906 => x"80", + 3907 => x"ca", + 3908 => x"2e", + 3909 => x"ca", + 3910 => x"c0", + 3911 => x"ce", + 3912 => x"ca", + 3913 => x"ca", + 3914 => x"70", + 3915 => x"08", + 3916 => x"51", + 3917 => x"80", + 3918 => x"73", + 3919 => x"38", + 3920 => x"52", + 3921 => x"95", + 3922 => x"88", + 3923 => x"8c", + 3924 => x"ff", + 3925 => x"91", + 3926 => x"55", + 3927 => x"88", + 3928 => x"0d", + 3929 => x"0d", + 3930 => x"3d", + 3931 => x"9a", + 3932 => x"cb", + 3933 => x"88", + 3934 => x"ca", + 3935 => x"b0", + 3936 => x"69", + 3937 => x"70", + 3938 => x"97", + 3939 => x"88", + 3940 => x"ca", + 3941 => x"38", + 3942 => x"94", + 3943 => x"88", + 3944 => x"09", + 3945 => x"88", + 3946 => x"df", + 3947 => x"85", + 3948 => x"51", + 3949 => x"74", + 3950 => x"78", + 3951 => x"8a", + 3952 => x"57", + 3953 => x"91", + 3954 => x"75", + 3955 => x"ca", + 3956 => x"38", + 3957 => x"ca", + 3958 => x"2e", + 3959 => x"83", + 3960 => x"91", + 3961 => x"ff", + 3962 => x"06", + 3963 => x"54", + 3964 => x"73", + 3965 => x"91", + 3966 => x"52", + 3967 => x"a4", + 3968 => x"88", + 3969 => x"ca", + 3970 => x"9a", + 3971 => x"a0", + 3972 => x"51", + 3973 => x"3f", + 3974 => x"0b", + 3975 => x"78", + 3976 => x"bf", + 3977 => x"88", + 3978 => x"80", + 3979 => x"ff", + 3980 => x"75", + 3981 => x"11", + 3982 => x"f8", + 3983 => x"78", + 3984 => x"80", + 3985 => x"ff", + 3986 => x"78", + 3987 => x"80", + 3988 => x"7f", + 3989 => x"d4", + 3990 => x"c9", + 3991 => x"54", + 3992 => x"15", + 3993 => x"cb", + 3994 => x"ca", + 3995 => x"91", + 3996 => x"b2", + 3997 => x"b2", + 3998 => x"96", + 3999 => x"b5", + 4000 => x"53", + 4001 => x"51", + 4002 => x"64", + 4003 => x"8b", + 4004 => x"54", + 4005 => x"15", + 4006 => x"ff", + 4007 => x"91", + 4008 => x"54", + 4009 => x"53", + 4010 => x"51", + 4011 => x"3f", + 4012 => x"88", + 4013 => x"0d", + 4014 => x"0d", + 4015 => x"05", + 4016 => x"3f", + 4017 => x"3d", + 4018 => x"52", + 4019 => x"d5", + 4020 => x"ca", + 4021 => x"91", + 4022 => x"82", + 4023 => x"4d", + 4024 => x"52", + 4025 => x"52", + 4026 => x"3f", + 4027 => x"08", + 4028 => x"88", + 4029 => x"38", + 4030 => x"05", + 4031 => x"06", + 4032 => x"73", + 4033 => x"a0", + 4034 => x"08", + 4035 => x"ff", + 4036 => x"ff", + 4037 => x"ac", + 4038 => x"92", + 4039 => x"54", + 4040 => x"3f", + 4041 => x"52", + 4042 => x"f7", + 4043 => x"88", + 4044 => x"ca", + 4045 => x"38", + 4046 => x"09", + 4047 => x"38", + 4048 => x"08", + 4049 => x"88", + 4050 => x"39", + 4051 => x"08", + 4052 => x"81", + 4053 => x"38", + 4054 => x"b1", + 4055 => x"88", + 4056 => x"ca", + 4057 => x"c8", + 4058 => x"93", + 4059 => x"ff", + 4060 => x"8d", + 4061 => x"b4", + 4062 => x"af", + 4063 => x"17", + 4064 => x"33", + 4065 => x"70", + 4066 => x"55", + 4067 => x"38", + 4068 => x"54", + 4069 => x"34", + 4070 => x"0b", + 4071 => x"8b", + 4072 => x"84", + 4073 => x"06", + 4074 => x"73", + 4075 => x"e5", + 4076 => x"2e", + 4077 => x"75", + 4078 => x"c6", + 4079 => x"ca", + 4080 => x"78", + 4081 => x"bb", + 4082 => x"91", + 4083 => x"80", + 4084 => x"38", + 4085 => x"08", + 4086 => x"ff", + 4087 => x"91", + 4088 => x"79", + 4089 => x"58", + 4090 => x"ca", + 4091 => x"c0", + 4092 => x"33", + 4093 => x"2e", + 4094 => x"99", + 4095 => x"75", + 4096 => x"c6", + 4097 => x"54", + 4098 => x"15", + 4099 => x"91", + 4100 => x"9c", + 4101 => x"c8", + 4102 => x"ca", + 4103 => x"91", + 4104 => x"8c", + 4105 => x"ff", + 4106 => x"91", + 4107 => x"55", + 4108 => x"88", + 4109 => x"0d", + 4110 => x"0d", + 4111 => x"05", + 4112 => x"05", + 4113 => x"33", + 4114 => x"53", + 4115 => x"05", + 4116 => x"51", + 4117 => x"91", + 4118 => x"55", + 4119 => x"08", + 4120 => x"78", + 4121 => x"95", + 4122 => x"51", + 4123 => x"91", + 4124 => x"55", + 4125 => x"08", + 4126 => x"80", + 4127 => x"81", + 4128 => x"86", + 4129 => x"38", + 4130 => x"61", + 4131 => x"12", + 4132 => x"7a", + 4133 => x"51", + 4134 => x"74", + 4135 => x"78", + 4136 => x"83", + 4137 => x"51", + 4138 => x"3f", + 4139 => x"08", + 4140 => x"ca", + 4141 => x"3d", + 4142 => x"3d", + 4143 => x"82", + 4144 => x"d0", + 4145 => x"3d", + 4146 => x"3f", + 4147 => x"08", + 4148 => x"88", + 4149 => x"38", + 4150 => x"52", + 4151 => x"05", + 4152 => x"3f", + 4153 => x"08", + 4154 => x"88", + 4155 => x"02", + 4156 => x"33", + 4157 => x"54", + 4158 => x"a6", + 4159 => x"22", + 4160 => x"71", + 4161 => x"53", + 4162 => x"51", + 4163 => x"3f", + 4164 => x"0b", + 4165 => x"76", + 4166 => x"b8", + 4167 => x"88", + 4168 => x"91", + 4169 => x"93", + 4170 => x"ea", + 4171 => x"6b", + 4172 => x"53", + 4173 => x"05", + 4174 => x"51", + 4175 => x"91", + 4176 => x"91", + 4177 => x"30", + 4178 => x"88", + 4179 => x"25", + 4180 => x"79", + 4181 => x"85", + 4182 => x"75", + 4183 => x"73", + 4184 => x"f9", + 4185 => x"80", + 4186 => x"8d", + 4187 => x"54", + 4188 => x"3f", + 4189 => x"08", + 4190 => x"88", + 4191 => x"38", + 4192 => x"51", + 4193 => x"91", + 4194 => x"57", + 4195 => x"08", + 4196 => x"ca", + 4197 => x"ca", + 4198 => x"5b", + 4199 => x"18", + 4200 => x"18", + 4201 => x"74", + 4202 => x"81", + 4203 => x"78", + 4204 => x"8b", + 4205 => x"54", + 4206 => x"75", + 4207 => x"38", + 4208 => x"1b", + 4209 => x"55", + 4210 => x"2e", + 4211 => x"39", + 4212 => x"09", + 4213 => x"38", + 4214 => x"80", + 4215 => x"70", + 4216 => x"25", + 4217 => x"80", + 4218 => x"38", + 4219 => x"bc", + 4220 => x"11", + 4221 => x"ff", + 4222 => x"91", + 4223 => x"57", + 4224 => x"08", + 4225 => x"70", + 4226 => x"80", + 4227 => x"83", + 4228 => x"80", + 4229 => x"84", + 4230 => x"a7", + 4231 => x"b4", + 4232 => x"ad", + 4233 => x"ca", + 4234 => x"0c", + 4235 => x"88", + 4236 => x"0d", + 4237 => x"0d", + 4238 => x"3d", + 4239 => x"52", + 4240 => x"ce", + 4241 => x"ca", + 4242 => x"ca", + 4243 => x"54", + 4244 => x"08", + 4245 => x"8b", + 4246 => x"8b", + 4247 => x"59", + 4248 => x"3f", + 4249 => x"33", + 4250 => x"06", + 4251 => x"57", + 4252 => x"81", + 4253 => x"58", + 4254 => x"06", + 4255 => x"4e", + 4256 => x"ff", + 4257 => x"91", + 4258 => x"80", + 4259 => x"6c", + 4260 => x"53", + 4261 => x"ae", + 4262 => x"ca", + 4263 => x"2e", + 4264 => x"88", + 4265 => x"6d", + 4266 => x"55", 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x"88", + 4326 => x"09", + 4327 => x"cc", + 4328 => x"76", + 4329 => x"c4", + 4330 => x"74", + 4331 => x"b0", + 4332 => x"88", + 4333 => x"ca", + 4334 => x"38", + 4335 => x"ca", + 4336 => x"67", + 4337 => x"db", + 4338 => x"88", + 4339 => x"34", + 4340 => x"52", + 4341 => x"ab", + 4342 => x"54", + 4343 => x"15", + 4344 => x"ff", + 4345 => x"91", + 4346 => x"54", + 4347 => x"91", + 4348 => x"9c", + 4349 => x"f2", + 4350 => x"62", + 4351 => x"80", + 4352 => x"93", + 4353 => x"55", + 4354 => x"5e", + 4355 => x"3f", + 4356 => x"08", + 4357 => x"88", + 4358 => x"38", + 4359 => x"58", + 4360 => x"38", + 4361 => x"97", + 4362 => x"08", + 4363 => x"38", + 4364 => x"70", + 4365 => x"81", + 4366 => x"55", + 4367 => x"87", + 4368 => x"39", + 4369 => x"90", + 4370 => x"82", + 4371 => x"8a", + 4372 => x"89", + 4373 => x"7f", + 4374 => x"56", + 4375 => x"3f", + 4376 => x"06", + 4377 => x"72", + 4378 => x"91", + 4379 => x"05", + 4380 => x"7c", + 4381 => x"55", + 4382 => x"27", + 4383 => x"16", + 4384 => x"83", + 4385 => x"76", + 4386 => x"80", + 4387 => x"79", + 4388 => x"99", + 4389 => x"7f", + 4390 => x"14", + 4391 => x"83", + 4392 => x"91", + 4393 => x"81", + 4394 => x"38", + 4395 => x"08", + 4396 => x"95", + 4397 => x"88", + 4398 => x"81", + 4399 => x"7b", + 4400 => x"06", + 4401 => x"39", + 4402 => x"56", + 4403 => x"09", + 4404 => x"b9", + 4405 => x"80", + 4406 => x"80", + 4407 => x"78", + 4408 => x"7a", + 4409 => x"38", + 4410 => x"73", + 4411 => x"81", + 4412 => x"ff", + 4413 => x"74", + 4414 => x"ff", + 4415 => x"91", + 4416 => x"58", + 4417 => x"08", + 4418 => x"74", + 4419 => x"16", + 4420 => x"73", + 4421 => x"39", + 4422 => x"7e", + 4423 => x"0c", + 4424 => x"2e", + 4425 => x"88", + 4426 => x"8c", + 4427 => x"1a", + 4428 => x"07", + 4429 => x"1b", + 4430 => x"08", + 4431 => x"16", + 4432 => x"75", + 4433 => x"38", + 4434 => x"90", + 4435 => x"15", + 4436 => x"54", + 4437 => x"34", + 4438 => x"91", + 4439 => x"90", + 4440 => x"e9", + 4441 => x"6d", + 4442 => x"80", + 4443 => x"9d", + 4444 => x"5c", + 4445 => x"3f", + 4446 => x"0b", + 4447 => x"08", + 4448 => x"38", + 4449 => x"08", + 4450 => x"ca", + 4451 => x"08", + 4452 => x"80", + 4453 => x"80", + 4454 => x"ca", + 4455 => x"ff", + 4456 => x"52", + 4457 => x"a0", + 4458 => x"ca", + 4459 => x"ff", + 4460 => x"06", + 4461 => x"56", + 4462 => x"38", + 4463 => x"70", + 4464 => x"55", + 4465 => x"8b", + 4466 => x"3d", + 4467 => x"83", + 4468 => x"ff", + 4469 => x"91", + 4470 => x"99", + 4471 => x"74", + 4472 => x"38", + 4473 => x"80", + 4474 => x"ff", + 4475 => x"55", + 4476 => x"83", + 4477 => x"78", + 4478 => x"38", + 4479 => x"26", + 4480 => x"81", + 4481 => x"8b", + 4482 => x"79", + 4483 => x"80", + 4484 => x"93", + 4485 => x"39", + 4486 => x"6e", + 4487 => x"89", + 4488 => x"48", + 4489 => x"83", + 4490 => x"61", + 4491 => x"25", + 4492 => x"55", + 4493 => x"8a", + 4494 => x"3d", + 4495 => x"81", + 4496 => x"ff", + 4497 => x"81", + 4498 => x"88", + 4499 => x"38", + 4500 => x"70", + 4501 => x"ca", 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x"80", + 4561 => x"76", + 4562 => x"38", + 4563 => x"51", + 4564 => x"3f", + 4565 => x"08", + 4566 => x"57", + 4567 => x"08", + 4568 => x"96", + 4569 => x"91", + 4570 => x"10", + 4571 => x"08", + 4572 => x"72", + 4573 => x"59", + 4574 => x"ff", + 4575 => x"5d", + 4576 => x"44", + 4577 => x"11", + 4578 => x"70", + 4579 => x"71", + 4580 => x"06", + 4581 => x"52", + 4582 => x"40", + 4583 => x"09", + 4584 => x"38", + 4585 => x"18", + 4586 => x"39", + 4587 => x"79", + 4588 => x"70", + 4589 => x"58", + 4590 => x"76", + 4591 => x"38", + 4592 => x"7d", + 4593 => x"70", + 4594 => x"55", + 4595 => x"3f", + 4596 => x"08", + 4597 => x"2e", + 4598 => x"9b", + 4599 => x"88", + 4600 => x"f5", + 4601 => x"38", + 4602 => x"38", + 4603 => x"59", + 4604 => x"38", + 4605 => x"7d", + 4606 => x"81", + 4607 => x"38", + 4608 => x"0b", + 4609 => x"08", + 4610 => x"78", + 4611 => x"1a", + 4612 => x"c0", + 4613 => x"74", + 4614 => x"39", + 4615 => x"55", + 4616 => x"8f", + 4617 => x"fd", + 4618 => x"ca", + 4619 => x"f5", + 4620 => x"78", + 4621 => x"79", + 4622 => x"80", + 4623 => x"f1", + 4624 => x"39", + 4625 => x"81", + 4626 => x"06", + 4627 => x"55", + 4628 => x"27", + 4629 => x"81", + 4630 => x"56", + 4631 => x"38", + 4632 => x"80", + 4633 => x"ff", + 4634 => x"8b", + 4635 => x"d0", + 4636 => x"ff", + 4637 => x"84", + 4638 => x"1b", + 4639 => x"b3", + 4640 => x"1c", + 4641 => x"ff", + 4642 => x"8e", + 4643 => x"a1", + 4644 => x"0b", + 4645 => x"7d", + 4646 => x"30", + 4647 => x"84", + 4648 => x"51", + 4649 => x"51", + 4650 => x"3f", + 4651 => x"83", + 4652 => x"90", + 4653 => x"ff", + 4654 => x"93", + 4655 => x"a0", + 4656 => x"39", + 4657 => x"1b", + 4658 => x"85", + 4659 => x"95", + 4660 => x"52", + 4661 => x"ff", + 4662 => x"81", + 4663 => x"1b", + 4664 => x"cf", + 4665 => x"9c", + 4666 => x"a0", + 4667 => x"83", + 4668 => x"06", + 4669 => x"82", + 4670 => x"52", + 4671 => x"51", + 4672 => x"3f", + 4673 => x"1b", + 4674 => x"c5", + 4675 => x"ac", + 4676 => x"a0", + 4677 => x"52", + 4678 => x"ff", + 4679 => x"86", + 4680 => x"51", + 4681 => x"3f", + 4682 => x"80", + 4683 => x"a9", + 4684 => x"1c", + 4685 => x"91", + 4686 => x"80", + 4687 => x"ae", + 4688 => x"b2", + 4689 => x"1b", + 4690 => x"85", + 4691 => x"ff", + 4692 => x"96", + 4693 => x"9f", + 4694 => x"80", + 4695 => x"34", + 4696 => x"1c", + 4697 => x"91", + 4698 => x"ab", + 4699 => x"a0", + 4700 => x"d4", + 4701 => x"fe", + 4702 => x"59", + 4703 => x"3f", + 4704 => x"53", + 4705 => x"51", + 4706 => x"3f", + 4707 => x"ca", + 4708 => x"e7", + 4709 => x"2e", + 4710 => x"80", + 4711 => x"54", + 4712 => x"53", + 4713 => x"51", + 4714 => x"3f", + 4715 => x"80", + 4716 => x"ff", + 4717 => x"84", + 4718 => x"d2", + 4719 => x"ff", + 4720 => x"86", + 4721 => x"f2", + 4722 => x"1b", + 4723 => x"81", + 4724 => x"52", + 4725 => x"51", + 4726 => x"3f", + 4727 => x"ec", + 4728 => x"9e", + 4729 => x"d4", + 4730 => x"51", + 4731 => x"3f", + 4732 => x"87", + 4733 => x"52", + 4734 => x"9a", + 4735 => x"54", + 4736 => x"7a", + 4737 => x"ff", + 4738 => x"65", + 4739 => x"7a", + 4740 => x"8f", + 4741 => x"80", + 4742 => x"2e", + 4743 => x"9a", + 4744 => x"7a", + 4745 => x"a9", + 4746 => x"84", + 4747 => x"9e", + 4748 => x"0a", + 4749 => x"51", + 4750 => x"ff", + 4751 => x"7d", + 4752 => x"38", + 4753 => x"52", + 4754 => x"9e", + 4755 => x"55", + 4756 => x"62", + 4757 => x"74", + 4758 => x"75", + 4759 => x"7e", + 4760 => x"fe", + 4761 => x"88", + 4762 => x"38", + 4763 => x"91", + 4764 => x"52", + 4765 => x"9e", + 4766 => x"16", + 4767 => x"56", + 4768 => x"38", + 4769 => x"77", + 4770 => x"8d", + 4771 => x"7d", + 4772 => x"38", + 4773 => x"57", + 4774 => x"83", + 4775 => x"76", + 4776 => x"7a", + 4777 => x"ff", + 4778 => x"91", + 4779 => x"81", + 4780 => x"16", + 4781 => x"56", + 4782 => x"38", + 4783 => x"83", + 4784 => x"86", + 4785 => x"ff", + 4786 => x"38", + 4787 => x"82", + 4788 => x"81", + 4789 => x"06", + 4790 => x"fe", + 4791 => x"53", + 4792 => x"51", + 4793 => x"3f", + 4794 => x"52", + 4795 => x"9c", + 4796 => x"be", + 4797 => x"75", + 4798 => x"81", + 4799 => x"0b", + 4800 => x"77", + 4801 => x"75", + 4802 => x"60", + 4803 => x"80", + 4804 => x"75", + 4805 => x"d1", + 4806 => x"85", + 4807 => x"ca", + 4808 => x"2a", + 4809 => x"75", + 4810 => x"91", + 4811 => x"87", + 4812 => x"52", + 4813 => x"51", + 4814 => x"3f", + 4815 => x"ca", + 4816 => x"9c", + 4817 => x"54", + 4818 => x"52", + 4819 => x"98", + 4820 => x"56", + 4821 => x"08", + 4822 => x"53", + 4823 => x"51", + 4824 => x"3f", + 4825 => x"ca", + 4826 => x"38", + 4827 => x"56", + 4828 => x"56", + 4829 => x"ca", + 4830 => x"75", + 4831 => x"0c", + 4832 => x"04", + 4833 => x"73", + 4834 => x"26", + 4835 => x"71", + 4836 => x"b3", + 4837 => x"71", + 4838 => x"bb", + 4839 => x"80", + 4840 => x"e4", + 4841 => x"39", + 4842 => x"51", + 4843 => x"91", + 4844 => x"80", + 4845 => x"bc", + 4846 => x"e4", + 4847 => x"ac", + 4848 => x"39", + 4849 => x"51", + 4850 => x"91", + 4851 => x"80", + 4852 => x"bc", + 4853 => x"c8", + 4854 => x"80", + 4855 => x"39", + 4856 => x"51", + 4857 => x"bd", + 4858 => x"39", + 4859 => x"51", + 4860 => x"bd", + 4861 => x"39", + 4862 => x"51", + 4863 => x"be", + 4864 => x"39", + 4865 => x"51", + 4866 => x"be", + 4867 => x"39", + 4868 => x"51", + 4869 => x"bf", + 4870 => x"39", + 4871 => x"51", + 4872 => x"3f", + 4873 => x"04", + 4874 => x"77", + 4875 => x"74", + 4876 => x"8a", + 4877 => x"75", + 4878 => x"51", + 4879 => x"e8", + 4880 => x"fe", + 4881 => x"91", + 4882 => x"52", + 4883 => x"f2", + 4884 => x"ca", + 4885 => x"79", + 4886 => x"91", + 4887 => x"ff", + 4888 => x"87", + 4889 => x"f5", + 4890 => x"7f", + 4891 => x"05", + 4892 => x"33", + 4893 => x"66", + 4894 => x"5a", + 4895 => x"78", + 4896 => x"c4", + 4897 => x"fa", + 4898 => x"cc", + 4899 => x"8e", + 4900 => x"74", + 4901 => x"fc", + 4902 => x"2e", + 4903 => x"a0", + 4904 => x"80", + 4905 => x"16", + 4906 => x"27", + 4907 => x"22", + 4908 => x"d0", + 4909 => x"ca", + 4910 => x"91", + 4911 => x"ff", + 4912 => x"82", + 4913 => x"c3", + 4914 => x"53", + 4915 => x"8e", + 4916 => x"52", + 4917 => x"51", + 4918 => x"3f", + 4919 => x"bf", + 4920 => x"86", + 4921 => x"15", + 4922 => x"74", + 4923 => x"78", + 4924 => x"72", + 4925 => x"bf", + 4926 => x"8c", + 4927 => x"39", + 4928 => x"51", + 4929 => x"3f", + 4930 => x"a0", + 4931 => x"8d", + 4932 => x"39", + 4933 => x"51", + 4934 => x"3f", + 4935 => x"77", + 4936 => x"74", + 4937 => x"79", + 4938 => x"55", + 4939 => x"27", + 4940 => x"80", + 4941 => x"73", + 4942 => x"85", + 4943 => x"83", + 4944 => x"fe", + 4945 => x"81", + 4946 => x"39", + 4947 => x"51", + 4948 => x"3f", + 4949 => x"1a", + 4950 => x"fd", + 4951 => x"ca", + 4952 => x"2b", + 4953 => x"51", + 4954 => x"2e", + 4955 => x"a5", + 4956 => x"fb", + 4957 => x"88", + 4958 => x"70", + 4959 => x"a0", + 4960 => x"70", + 4961 => x"2a", + 4962 => x"51", + 4963 => x"2e", + 4964 => x"dd", + 4965 => x"2e", + 4966 => x"85", + 4967 => x"8c", + 4968 => x"53", + 4969 => x"fd", + 4970 => x"53", + 4971 => x"88", + 4972 => x"0d", + 4973 => x"0d", + 4974 => x"05", + 4975 => x"33", + 4976 => x"70", + 4977 => x"25", + 4978 => x"74", + 4979 => x"51", + 4980 => x"56", + 4981 => x"80", + 4982 => x"53", + 4983 => x"3d", + 4984 => x"c0", + 4985 => x"ca", + 4986 => x"91", + 4987 => x"b8", + 4988 => x"88", + 4989 => x"98", + 4990 => x"ca", + 4991 => x"96", + 4992 => x"54", + 4993 => x"77", + 4994 => x"c4", + 4995 => x"ca", + 4996 => x"91", + 4997 => x"90", + 4998 => x"74", + 4999 => x"38", + 5000 => x"19", + 5001 => x"39", + 5002 => x"05", + 5003 => x"3f", + 5004 => x"77", + 5005 => x"51", + 5006 => x"2e", + 5007 => x"80", + 5008 => x"91", + 5009 => x"87", + 5010 => x"08", + 5011 => x"fb", + 5012 => x"57", + 5013 => x"88", + 5014 => x"0d", + 5015 => x"0d", + 5016 => x"05", + 5017 => x"57", + 5018 => x"80", + 5019 => x"79", + 5020 => x"3f", + 5021 => x"08", + 5022 => x"80", + 5023 => x"75", + 5024 => x"38", + 5025 => x"55", + 5026 => x"ca", + 5027 => x"52", + 5028 => x"2d", + 5029 => x"08", + 5030 => x"77", + 5031 => x"ca", + 5032 => x"3d", + 5033 => x"3d", + 5034 => x"05", + 5035 => x"80", + 5036 => x"88", + 5037 => x"88", + 5038 => x"c7", + 5039 => x"ff", + 5040 => x"91", + 5041 => x"91", + 5042 => x"91", + 5043 => x"52", + 5044 => x"51", + 5045 => x"3f", + 5046 => x"85", + 5047 => x"92", + 5048 => x"0d", + 5049 => x"0d", + 5050 => x"80", + 5051 => x"80", + 5052 => x"51", + 5053 => x"3f", + 5054 => x"51", + 5055 => x"3f", + 5056 => x"f5", + 5057 => x"81", + 5058 => x"06", + 5059 => x"80", + 5060 => x"81", + 5061 => x"eb", + 5062 => x"e0", + 5063 => x"e3", + 5064 => x"fe", + 5065 => x"72", + 5066 => x"81", + 5067 => x"71", + 5068 => x"38", + 5069 => x"f5", + 5070 => x"c0", + 5071 => x"f7", + 5072 => x"51", + 5073 => x"3f", + 5074 => x"70", + 5075 => x"52", + 5076 => x"95", + 5077 => x"fe", + 5078 => x"91", + 5079 => x"fe", + 5080 => x"80", + 5081 => x"9b", + 5082 => x"2a", + 5083 => x"51", + 5084 => x"2e", + 5085 => x"51", + 5086 => x"3f", + 5087 => x"51", + 5088 => x"3f", + 5089 => x"f4", + 5090 => x"85", + 5091 => x"06", + 5092 => x"80", + 5093 => x"81", + 5094 => x"e7", + 5095 => x"ac", + 5096 => x"df", + 5097 => x"fe", + 5098 => x"72", + 5099 => x"81", + 5100 => x"71", + 5101 => x"38", + 5102 => x"f4", + 5103 => x"c1", + 5104 => x"f6", + 5105 => x"51", + 5106 => x"3f", + 5107 => x"70", + 5108 => x"52", + 5109 => x"95", + 5110 => x"fe", + 5111 => x"91", + 5112 => x"fe", + 5113 => x"80", + 5114 => x"97", + 5115 => x"2a", + 5116 => x"51", + 5117 => x"2e", + 5118 => x"51", + 5119 => x"3f", + 5120 => x"51", + 5121 => x"3f", + 5122 => x"f3", + 5123 => x"ff", + 5124 => x"3d", + 5125 => x"3d", + 5126 => x"08", + 5127 => x"57", + 5128 => x"80", + 5129 => x"39", + 5130 => x"85", + 5131 => x"80", + 5132 => x"14", + 5133 => x"33", + 5134 => x"06", + 5135 => x"74", + 5136 => x"38", + 5137 => x"80", + 5138 => x"72", + 5139 => x"81", + 5140 => x"72", + 5141 => x"81", + 5142 => x"80", + 5143 => x"05", + 5144 => x"56", + 5145 => x"91", + 5146 => x"77", + 5147 => x"08", + 5148 => x"ed", + 5149 => x"ca", + 5150 => x"38", + 5151 => x"53", + 5152 => x"ff", + 5153 => x"16", + 5154 => x"06", + 5155 => x"76", + 5156 => x"ff", + 5157 => x"ca", + 5158 => x"3d", + 5159 => x"3d", + 5160 => x"71", + 5161 => x"0c", + 5162 => x"52", + 5163 => x"8a", + 5164 => x"ca", + 5165 => x"ff", + 5166 => x"7c", + 5167 => x"06", + 5168 => x"c2", + 5169 => x"3d", + 5170 => x"ff", + 5171 => x"7b", + 5172 => x"91", + 5173 => x"ff", + 5174 => x"91", + 5175 => x"7c", + 5176 => x"91", + 5177 => x"90", + 5178 => x"70", + 5179 => x"c2", + 5180 => x"fe", + 5181 => x"3d", + 5182 => x"80", + 5183 => x"52", + 5184 => x"eb", + 5185 => x"f8", + 5186 => x"ff", + 5187 => x"b7", + 5188 => x"05", + 5189 => x"3f", + 5190 => x"08", + 5191 => x"90", + 5192 => x"78", + 5193 => x"8a", + 5194 => x"80", + 5195 => x"e0", + 5196 => x"2e", + 5197 => x"78", + 5198 => x"38", + 5199 => x"82", + 5200 => x"84", + 5201 => x"78", + 5202 => x"a2", + 5203 => x"2e", + 5204 => x"8e", + 5205 => x"94", + 5206 => x"38", + 5207 => x"83", + 5208 => x"e2", + 5209 => x"2e", + 5210 => x"78", + 5211 => x"38", + 5212 => x"84", + 5213 => x"bd", + 5214 => x"38", + 5215 => x"78", + 5216 => x"86", + 5217 => x"80", + 5218 => x"cf", + 5219 => x"39", + 5220 => x"2e", + 5221 => x"78", + 5222 => x"b0", + 5223 => x"d1", + 5224 => x"38", + 5225 => x"24", + 5226 => x"80", + 5227 => x"83", + 5228 => x"d0", + 5229 => x"38", + 5230 => x"78", + 5231 => x"8c", + 5232 => x"80", + 5233 => x"d6", + 5234 => x"39", + 5235 => x"2e", + 5236 => x"78", + 5237 => x"92", + 5238 => x"f9", + 5239 => x"38", + 5240 => x"2e", + 5241 => x"8d", + 5242 => x"81", + 5243 => x"cf", + 5244 => x"87", + 5245 => x"38", + 5246 => x"b7", + 5247 => x"11", + 5248 => x"05", + 5249 => x"ef", + 5250 => x"88", + 5251 => x"91", + 5252 => x"8e", + 5253 => x"3d", + 5254 => x"53", + 5255 => x"51", + 5256 => x"3f", + 5257 => x"08", + 5258 => x"38", + 5259 => x"83", + 5260 => x"02", + 5261 => x"33", + 5262 => x"cf", + 5263 => x"ff", + 5264 => x"91", + 5265 => x"81", + 5266 => x"78", + 5267 => x"c2", + 5268 => x"fb", + 5269 => x"5d", + 5270 => x"91", + 5271 => x"8b", + 5272 => x"3d", + 5273 => x"53", + 5274 => x"51", + 5275 => x"3f", + 5276 => x"08", + 5277 => x"f6", + 5278 => x"80", + 5279 => x"cf", + 5280 => x"ff", + 5281 => x"91", + 5282 => x"52", + 5283 => x"51", + 5284 => x"b7", + 5285 => x"11", + 5286 => x"05", + 5287 => x"d7", + 5288 => x"88", + 5289 => x"87", + 5290 => x"26", + 5291 => x"b7", + 5292 => x"11", + 5293 => x"05", + 5294 => x"bb", + 5295 => x"88", + 5296 => x"91", + 5297 => x"43", + 5298 => x"c3", + 5299 => x"51", + 5300 => x"3f", + 5301 => x"05", + 5302 => x"52", + 5303 => x"29", + 5304 => x"05", + 5305 => x"d5", + 5306 => x"88", + 5307 => x"38", + 5308 => x"51", + 5309 => x"3f", + 5310 => x"f2", + 5311 => x"fe", + 5312 => x"fe", + 5313 => x"91", + 5314 => x"b8", + 5315 => x"05", + 5316 => x"eb", + 5317 => x"53", + 5318 => x"08", + 5319 => x"f5", + 5320 => x"d5", + 5321 => x"fe", + 5322 => x"fe", + 5323 => x"91", + 5324 => x"b8", + 5325 => x"05", + 5326 => x"ea", + 5327 => x"ca", + 5328 => x"3d", + 5329 => x"52", + 5330 => x"ca", + 5331 => x"88", + 5332 => x"fe", + 5333 => x"59", + 5334 => x"3f", + 5335 => x"58", + 5336 => x"57", + 5337 => x"55", + 5338 => x"08", + 5339 => x"54", + 5340 => x"52", + 5341 => x"e5", + 5342 => x"88", + 5343 => x"fa", + 5344 => x"ca", + 5345 => x"ef", + 5346 => x"e2", + 5347 => x"fe", + 5348 => x"fe", + 5349 => x"ff", + 5350 => x"91", + 5351 => x"80", + 5352 => x"38", + 5353 => x"f0", + 5354 => x"f8", + 5355 => x"80", + 5356 => x"ca", + 5357 => x"2e", + 5358 => x"b7", + 5359 => x"11", + 5360 => x"05", + 5361 => x"af", + 5362 => x"88", + 5363 => x"91", + 5364 => x"42", + 5365 => x"51", + 5366 => x"3f", + 5367 => x"5a", + 5368 => x"81", + 5369 => x"59", + 5370 => x"84", + 5371 => x"7a", + 5372 => x"38", + 5373 => x"b7", + 5374 => x"11", + 5375 => x"05", + 5376 => x"f3", + 5377 => x"88", + 5378 => x"f9", + 5379 => x"3d", + 5380 => x"53", + 5381 => x"51", + 5382 => x"3f", + 5383 => x"08", + 5384 => x"ca", + 5385 => x"fe", + 5386 => x"fe", + 5387 => x"fe", + 5388 => x"91", + 5389 => x"80", + 5390 => x"38", + 5391 => x"51", + 5392 => x"3f", + 5393 => x"63", + 5394 => x"38", + 5395 => x"70", + 5396 => x"33", + 5397 => x"81", + 5398 => x"39", + 5399 => x"f4", + 5400 => x"f8", + 5401 => x"ff", + 5402 => x"ca", + 5403 => x"2e", + 5404 => x"b7", + 5405 => x"11", + 5406 => x"05", + 5407 => x"f7", + 5408 => x"88", + 5409 => x"f8", + 5410 => x"3d", + 5411 => x"53", + 5412 => x"51", + 5413 => x"3f", + 5414 => x"08", + 5415 => x"ce", + 5416 => x"c4", + 5417 => x"f6", + 5418 => x"79", + 5419 => x"38", + 5420 => x"7b", + 5421 => x"5b", + 5422 => x"92", + 5423 => x"7a", + 5424 => x"53", + 5425 => x"c3", + 5426 => x"fc", + 5427 => x"1a", + 5428 => x"43", + 5429 => x"91", + 5430 => x"86", + 5431 => x"3d", + 5432 => x"53", + 5433 => x"51", + 5434 => x"3f", + 5435 => x"08", + 5436 => x"91", + 5437 => x"59", + 5438 => x"88", + 5439 => x"e4", + 5440 => x"39", + 5441 => x"33", + 5442 => x"2e", + 5443 => x"c6", + 5444 => x"a2", + 5445 => x"93", + 5446 => x"8b", + 5447 => x"94", + 5448 => x"80", + 5449 => x"91", + 5450 => x"44", + 5451 => x"c7", + 5452 => x"80", + 5453 => x"3d", + 5454 => x"53", + 5455 => x"51", + 5456 => x"3f", + 5457 => x"08", + 5458 => x"91", + 5459 => x"59", + 5460 => x"88", + 5461 => x"e8", + 5462 => x"39", + 5463 => x"33", + 5464 => x"2e", + 5465 => x"c6", + 5466 => x"a1", + 5467 => x"93", + 5468 => x"8b", + 5469 => x"94", + 5470 => x"80", + 5471 => x"91", + 5472 => x"43", + 5473 => x"c7", + 5474 => x"05", + 5475 => x"fe", + 5476 => x"fe", + 5477 => x"fe", + 5478 => x"91", + 5479 => x"80", + 5480 => x"80", + 5481 => x"79", + 5482 => x"38", + 5483 => x"90", + 5484 => x"78", + 5485 => x"38", + 5486 => x"83", + 5487 => x"91", + 5488 => x"fe", + 5489 => x"a0", + 5490 => x"61", + 5491 => x"63", + 5492 => x"3f", + 5493 => x"51", + 5494 => x"b7", + 5495 => x"11", + 5496 => x"05", + 5497 => x"8f", + 5498 => x"88", + 5499 => x"f5", + 5500 => x"3d", + 5501 => x"53", + 5502 => x"51", + 5503 => x"3f", + 5504 => x"08", + 5505 => x"38", + 5506 => x"80", + 5507 => x"79", + 5508 => x"05", + 5509 => x"fe", + 5510 => x"fe", + 5511 => x"fe", + 5512 => x"91", + 5513 => x"e0", + 5514 => x"39", + 5515 => x"54", + 5516 => x"8c", + 5517 => x"ca", + 5518 => x"52", + 5519 => x"fa", + 5520 => x"45", + 5521 => x"78", + 5522 => x"a2", + 5523 => x"27", + 5524 => x"3d", + 5525 => x"53", + 5526 => x"51", + 5527 => x"3f", + 5528 => x"08", + 5529 => x"38", + 5530 => x"80", + 5531 => x"79", + 5532 => x"05", + 5533 => x"39", + 5534 => x"51", + 5535 => x"3f", + 5536 => x"b7", + 5537 => x"11", + 5538 => x"05", + 5539 => x"d9", + 5540 => x"88", + 5541 => x"f4", + 5542 => x"3d", + 5543 => x"53", + 5544 => x"51", + 5545 => x"3f", + 5546 => x"08", + 5547 => x"38", + 5548 => x"be", + 5549 => x"70", + 5550 => x"23", + 5551 => x"3d", + 5552 => x"53", + 5553 => x"51", + 5554 => x"3f", + 5555 => x"08", + 5556 => x"9a", + 5557 => x"22", + 5558 => x"c4", + 5559 => x"f8", + 5560 => x"f8", + 5561 => x"fe", + 5562 => x"79", + 5563 => x"59", + 5564 => x"f3", + 5565 => x"9f", + 5566 => x"60", + 5567 => x"d5", + 5568 => x"fe", + 5569 => x"fe", + 5570 => x"fe", + 5571 => x"91", + 5572 => x"80", + 5573 => x"60", + 5574 => x"05", + 5575 => x"82", + 5576 => x"78", + 5577 => x"39", + 5578 => x"51", + 5579 => x"3f", + 5580 => x"b7", + 5581 => x"11", + 5582 => x"05", + 5583 => x"a9", + 5584 => x"88", + 5585 => x"f3", + 5586 => x"3d", + 5587 => x"53", + 5588 => x"51", + 5589 => x"3f", + 5590 => x"08", + 5591 => x"38", + 5592 => x"0c", + 5593 => x"05", + 5594 => x"fe", + 5595 => x"fe", + 5596 => x"fe", + 5597 => x"91", + 5598 => x"e4", + 5599 => x"39", + 5600 => x"54", + 5601 => x"ac", + 5602 => x"f6", + 5603 => x"52", + 5604 => x"f7", + 5605 => x"45", + 5606 => x"78", + 5607 => x"ce", + 5608 => x"27", + 5609 => x"3d", + 5610 => x"53", + 5611 => x"51", + 5612 => x"3f", + 5613 => x"08", + 5614 => x"38", + 5615 => x"52", + 5616 => x"51", + 5617 => x"3f", + 5618 => x"0c", + 5619 => x"05", + 5620 => x"39", + 5621 => x"51", + 5622 => x"3f", + 5623 => x"91", + 5624 => x"fe", + 5625 => x"82", + 5626 => x"a6", + 5627 => x"39", + 5628 => x"51", + 5629 => x"3f", + 5630 => x"ee", + 5631 => x"ee", + 5632 => x"81", + 5633 => x"94", + 5634 => x"80", + 5635 => x"c0", + 5636 => x"91", + 5637 => x"fe", + 5638 => x"f1", + 5639 => x"c4", + 5640 => x"ef", + 5641 => x"80", + 5642 => x"c0", + 5643 => x"8c", + 5644 => x"87", + 5645 => x"0c", + 5646 => x"b7", + 5647 => x"11", + 5648 => x"05", + 5649 => x"af", + 5650 => x"88", + 5651 => x"f1", + 5652 => x"52", + 5653 => x"51", + 5654 => x"3f", + 5655 => x"04", + 5656 => x"f4", + 5657 => x"f8", + 5658 => x"f7", + 5659 => x"ca", + 5660 => x"2e", + 5661 => x"63", + 5662 => x"ac", + 5663 => x"82", + 5664 => x"78", + 5665 => x"88", + 5666 => x"ca", + 5667 => x"2e", + 5668 => x"91", + 5669 => x"52", + 5670 => x"51", + 5671 => x"3f", + 5672 => x"91", + 5673 => x"fe", + 5674 => x"fe", + 5675 => x"f0", + 5676 => x"c6", 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x"04", + 5736 => x"04", + 5737 => x"04", + 5738 => x"04", + 5739 => x"04", + 5740 => x"04", + 5741 => x"04", + 5742 => x"04", + 5743 => x"04", + 5744 => x"04", + 5745 => x"04", + 5746 => x"04", + 5747 => x"04", + 5748 => x"04", + 5749 => x"04", + 5750 => x"04", + 5751 => x"04", + 5752 => x"04", + 5753 => x"04", + 5754 => x"04", + 5755 => x"64", + 5756 => x"2f", + 5757 => x"25", + 5758 => x"64", + 5759 => x"2e", + 5760 => x"64", + 5761 => x"6f", + 5762 => x"6f", + 5763 => x"67", + 5764 => x"74", + 5765 => x"00", + 5766 => x"28", + 5767 => x"6d", + 5768 => x"43", + 5769 => x"6e", + 5770 => x"29", + 5771 => x"0a", + 5772 => x"69", + 5773 => x"20", + 5774 => x"6c", + 5775 => x"6e", + 5776 => x"3a", + 5777 => x"20", + 5778 => x"4e", + 5779 => x"42", + 5780 => x"20", + 5781 => x"61", + 5782 => x"25", + 5783 => x"2c", + 5784 => x"7a", + 5785 => x"30", + 5786 => x"2e", + 5787 => x"20", + 5788 => x"52", + 5789 => x"28", + 5790 => x"72", + 5791 => x"30", + 5792 => x"20", + 5793 => x"65", + 5794 => x"38", + 5795 => x"0a", + 5796 => x"20", + 5797 => x"41", + 5798 => x"53", + 5799 => x"74", + 5800 => x"38", + 5801 => x"53", + 5802 => x"3d", + 5803 => x"58", + 5804 => x"00", + 5805 => x"20", + 5806 => x"4f", + 5807 => x"0a", + 5808 => x"20", + 5809 => x"53", + 5810 => x"00", + 5811 => x"20", + 5812 => x"50", + 5813 => x"00", + 5814 => x"20", + 5815 => x"44", + 5816 => x"72", + 5817 => x"44", + 5818 => x"63", + 5819 => x"25", + 5820 => x"29", + 5821 => x"00", + 5822 => x"20", + 5823 => x"4e", + 5824 => x"52", + 5825 => x"20", + 5826 => x"54", + 5827 => x"4c", + 5828 => x"00", + 5829 => x"20", + 5830 => x"49", + 5831 => x"31", + 5832 => x"69", + 5833 => x"73", + 5834 => x"31", + 5835 => x"0a", + 5836 => x"64", + 5837 => x"73", + 5838 => x"3a", + 5839 => x"20", + 5840 => x"50", + 5841 => x"65", + 5842 => x"20", + 5843 => x"74", + 5844 => x"41", + 5845 => x"65", + 5846 => x"3d", + 5847 => x"38", + 5848 => x"00", + 5849 => x"20", + 5850 => x"50", + 5851 => x"65", + 5852 => x"79", + 5853 => x"61", + 5854 => x"41", + 5855 => x"65", + 5856 => x"3d", + 5857 => x"38", + 5858 => x"00", + 5859 => x"20", + 5860 => x"74", + 5861 => x"20", + 5862 => x"72", + 5863 => x"64", + 5864 => x"73", + 5865 => x"20", + 5866 => x"3d", + 5867 => x"38", + 5868 => x"00", + 5869 => x"20", + 5870 => x"50", + 5871 => x"64", + 5872 => x"20", + 5873 => x"20", + 5874 => x"20", + 5875 => x"20", + 5876 => x"3d", + 5877 => x"38", + 5878 => x"00", + 5879 => x"20", + 5880 => x"79", + 5881 => x"6d", + 5882 => x"6f", + 5883 => x"46", + 5884 => x"20", + 5885 => x"20", + 5886 => x"3d", + 5887 => x"38", + 5888 => x"00", + 5889 => x"6d", + 5890 => x"00", + 5891 => x"65", + 5892 => x"6d", + 5893 => x"6c", + 5894 => x"00", + 5895 => x"56", + 5896 => x"56", + 5897 => x"6e", + 5898 => x"6e", + 5899 => x"77", + 5900 => x"44", + 5901 => x"2a", + 5902 => x"3b", + 5903 => x"3f", + 5904 => x"7f", + 5905 => x"41", + 5906 => x"41", + 5907 => x"00", + 5908 => x"fe", + 5909 => x"44", + 5910 => x"2e", + 5911 => x"4f", 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x"69", + 5971 => x"00", + 5972 => x"69", + 5973 => x"6c", + 5974 => x"69", + 5975 => x"00", + 5976 => x"6c", + 5977 => x"00", + 5978 => x"65", + 5979 => x"00", + 5980 => x"63", + 5981 => x"72", + 5982 => x"63", + 5983 => x"00", + 5984 => x"64", + 5985 => x"00", + 5986 => x"64", + 5987 => x"00", + 5988 => x"65", + 5989 => x"65", + 5990 => x"65", + 5991 => x"69", + 5992 => x"69", + 5993 => x"66", + 5994 => x"66", + 5995 => x"61", + 5996 => x"00", + 5997 => x"6d", + 5998 => x"65", + 5999 => x"72", + 6000 => x"65", + 6001 => x"00", + 6002 => x"6e", + 6003 => x"00", + 6004 => x"65", + 6005 => x"00", + 6006 => x"69", + 6007 => x"45", + 6008 => x"72", + 6009 => x"6e", + 6010 => x"6e", + 6011 => x"65", + 6012 => x"72", + 6013 => x"00", + 6014 => x"69", + 6015 => x"6e", + 6016 => x"72", + 6017 => x"79", + 6018 => x"00", + 6019 => x"6f", + 6020 => x"6c", + 6021 => x"6f", + 6022 => x"2e", + 6023 => x"6f", + 6024 => x"74", + 6025 => x"6f", + 6026 => x"2e", + 6027 => x"6e", + 6028 => x"69", + 6029 => x"69", + 6030 => x"61", + 6031 => x"0a", + 6032 => x"63", + 6033 => x"73", + 6034 => x"6e", + 6035 => x"2e", + 6036 => x"69", + 6037 => x"61", + 6038 => x"61", + 6039 => x"65", + 6040 => x"74", + 6041 => x"00", + 6042 => x"69", + 6043 => x"68", + 6044 => x"6c", + 6045 => x"6e", + 6046 => x"69", + 6047 => x"00", + 6048 => x"44", + 6049 => x"20", + 6050 => x"74", + 6051 => x"72", + 6052 => x"63", + 6053 => x"2e", + 6054 => x"72", + 6055 => x"20", + 6056 => x"62", + 6057 => x"69", + 6058 => x"6e", + 6059 => x"69", + 6060 => x"00", + 6061 => x"69", + 6062 => x"6e", + 6063 => x"65", + 6064 => x"6c", + 6065 => x"0a", + 6066 => x"6f", + 6067 => x"6d", + 6068 => x"69", + 6069 => x"20", + 6070 => x"65", + 6071 => x"74", + 6072 => x"66", + 6073 => x"64", + 6074 => x"20", + 6075 => x"6b", + 6076 => x"00", + 6077 => x"6f", + 6078 => x"74", + 6079 => x"6f", + 6080 => x"64", + 6081 => x"00", + 6082 => x"69", + 6083 => x"75", + 6084 => x"6f", + 6085 => x"61", + 6086 => x"6e", + 6087 => x"6e", + 6088 => x"6c", + 6089 => x"0a", + 6090 => x"69", + 6091 => x"69", + 6092 => x"6f", + 6093 => x"64", + 6094 => x"00", + 6095 => x"6e", + 6096 => x"66", + 6097 => x"65", + 6098 => x"6d", + 6099 => x"72", + 6100 => x"00", + 6101 => x"6f", + 6102 => x"61", + 6103 => x"6f", + 6104 => x"20", + 6105 => x"65", + 6106 => x"00", + 6107 => x"61", + 6108 => x"65", + 6109 => x"73", + 6110 => x"63", + 6111 => x"65", + 6112 => x"0a", + 6113 => x"75", + 6114 => x"73", + 6115 => x"00", + 6116 => x"6e", + 6117 => x"77", + 6118 => x"72", + 6119 => x"2e", + 6120 => x"25", + 6121 => x"62", + 6122 => x"73", + 6123 => x"20", + 6124 => x"25", + 6125 => x"62", + 6126 => x"73", + 6127 => x"63", + 6128 => x"00", + 6129 => x"30", + 6130 => x"00", + 6131 => x"20", + 6132 => x"30", + 6133 => x"00", + 6134 => x"20", + 6135 => x"20", + 6136 => x"00", + 6137 => x"30", + 6138 => x"00", + 6139 => x"20", + 6140 => x"7c", + 6141 => x"0d", + 6142 => x"65", + 6143 => x"00", + 6144 => x"50", + 6145 => x"00", + 6146 => x"2a", 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x"72", + 6206 => x"74", + 6207 => x"65", + 6208 => x"6e", + 6209 => x"70", + 6210 => x"6d", + 6211 => x"2e", + 6212 => x"00", + 6213 => x"6e", + 6214 => x"69", + 6215 => x"74", + 6216 => x"72", + 6217 => x"0a", + 6218 => x"3a", + 6219 => x"61", + 6220 => x"64", + 6221 => x"20", + 6222 => x"74", + 6223 => x"69", + 6224 => x"73", + 6225 => x"61", + 6226 => x"30", + 6227 => x"6c", + 6228 => x"65", + 6229 => x"69", + 6230 => x"61", + 6231 => x"6c", + 6232 => x"0a", + 6233 => x"20", + 6234 => x"61", + 6235 => x"69", + 6236 => x"69", + 6237 => x"00", + 6238 => x"6e", + 6239 => x"61", + 6240 => x"65", + 6241 => x"00", + 6242 => x"61", + 6243 => x"64", + 6244 => x"20", + 6245 => x"74", + 6246 => x"69", + 6247 => x"0a", + 6248 => x"63", + 6249 => x"0a", + 6250 => x"75", + 6251 => x"6c", + 6252 => x"69", + 6253 => x"2e", + 6254 => x"6f", + 6255 => x"6e", + 6256 => x"2e", + 6257 => x"6f", + 6258 => x"72", + 6259 => x"2e", + 6260 => x"00", + 6261 => x"30", + 6262 => x"28", + 6263 => x"78", + 6264 => x"25", + 6265 => x"78", + 6266 => x"38", + 6267 => x"00", + 6268 => x"75", + 6269 => x"4d", + 6270 => x"72", + 6271 => x"00", + 6272 => x"43", + 6273 => x"6c", + 6274 => x"2e", + 6275 => x"30", + 6276 => x"25", + 6277 => x"2d", + 6278 => x"3f", + 6279 => x"00", + 6280 => x"30", + 6281 => x"25", + 6282 => x"2d", + 6283 => x"30", + 6284 => x"25", + 6285 => x"2d", + 6286 => x"69", + 6287 => x"6c", + 6288 => x"20", + 6289 => x"65", + 6290 => x"70", + 6291 => x"00", + 6292 => x"6e", + 6293 => x"69", + 6294 => x"69", + 6295 => x"72", + 6296 => x"74", + 6297 => x"00", + 6298 => x"69", + 6299 => x"6c", + 6300 => x"75", + 6301 => x"20", + 6302 => x"6f", + 6303 => x"6e", + 6304 => x"69", + 6305 => x"75", + 6306 => x"20", + 6307 => x"6f", + 6308 => x"78", + 6309 => x"74", + 6310 => x"20", + 6311 => x"65", + 6312 => x"25", + 6313 => x"20", + 6314 => x"0a", + 6315 => x"61", + 6316 => x"6e", + 6317 => x"6f", + 6318 => x"40", + 6319 => x"38", + 6320 => x"2e", + 6321 => x"00", + 6322 => x"61", + 6323 => x"72", + 6324 => x"72", + 6325 => x"20", + 6326 => x"65", + 6327 => x"64", + 6328 => x"00", + 6329 => x"65", + 6330 => x"72", + 6331 => x"67", + 6332 => x"70", + 6333 => x"61", + 6334 => x"6e", + 6335 => x"0a", + 6336 => x"6f", + 6337 => x"72", + 6338 => x"6f", + 6339 => x"67", + 6340 => x"0a", + 6341 => x"50", + 6342 => x"69", + 6343 => x"64", + 6344 => x"73", + 6345 => x"2e", + 6346 => x"00", + 6347 => x"61", + 6348 => x"6f", + 6349 => x"6e", + 6350 => x"00", + 6351 => x"75", + 6352 => x"6e", + 6353 => x"2e", + 6354 => x"6e", + 6355 => x"69", + 6356 => x"69", + 6357 => x"72", + 6358 => x"74", + 6359 => x"2e", + 6360 => x"00", + 6361 => x"00", + 6362 => x"00", + 6363 => x"00", + 6364 => x"00", + 6365 => x"01", + 6366 => x"00", + 6367 => x"00", + 6368 => x"00", + 6369 => x"00", + 6370 => x"00", + 6371 => x"f5", + 6372 => x"01", + 6373 => x"01", + 6374 => x"01", + 6375 => x"00", + 6376 => x"00", + 6377 => x"00", + 6378 => x"04", + 6379 => x"02", + 6380 => x"00", + 6381 => x"00", + 6382 => x"04", + 6383 => x"04", + 6384 => x"00", + 6385 => x"00", + 6386 => x"04", + 6387 => x"14", + 6388 => x"00", + 6389 => x"00", + 6390 => x"04", + 6391 => x"2b", + 6392 => x"00", + 6393 => x"00", + 6394 => x"04", + 6395 => x"30", + 6396 => x"00", + 6397 => x"00", + 6398 => x"04", + 6399 => x"3c", + 6400 => x"00", + 6401 => x"00", + 6402 => x"04", + 6403 => x"3d", + 6404 => x"00", + 6405 => x"00", + 6406 => x"04", + 6407 => x"3f", + 6408 => x"00", + 6409 => x"00", + 6410 => x"04", + 6411 => x"40", + 6412 => x"00", + 6413 => x"00", + 6414 => x"04", + 6415 => x"41", + 6416 => x"00", + 6417 => x"00", + 6418 => x"04", + 6419 => x"42", + 6420 => x"00", + 6421 => x"00", + 6422 => x"04", + 6423 => x"43", + 6424 => x"00", + 6425 => x"00", + 6426 => x"04", + 6427 => x"50", + 6428 => x"00", + 6429 => x"00", + 6430 => x"04", + 6431 => x"51", + 6432 => x"00", + 6433 => x"00", + 6434 => x"04", + 6435 => x"54", + 6436 => x"00", + 6437 => x"00", + 6438 => x"04", + 6439 => x"55", + 6440 => x"00", + 6441 => x"00", + 6442 => x"04", + 6443 => x"79", + 6444 => x"00", + 6445 => x"00", + 6446 => x"04", + 6447 => x"78", + 6448 => x"00", + 6449 => x"00", + 6450 => x"04", + 6451 => x"82", + 6452 => x"00", + 6453 => x"00", + 6454 => x"04", + 6455 => x"83", + 6456 => x"00", + 6457 => x"00", + 6458 => x"04", + 6459 => x"85", + 6460 => x"00", + 6461 => x"00", + 6462 => x"04", + 6463 => x"87", + 6464 => x"00", + 6465 => x"00", + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + 0 => x"0b", + 1 => x"80", + 2 => x"90", + 3 => x"ff", + 4 => x"ff", + 5 => x"ff", + 6 => x"ff", + 7 => x"ff", + 8 => x"0b", + 9 => x"80", + 10 => x"90", + 11 => x"0b", + 12 => x"96", + 13 => x"90", + 14 => x"0b", + 15 => x"b8", + 16 => x"90", + 17 => x"0b", + 18 => x"da", + 19 => x"90", + 20 => x"0b", + 21 => x"fc", + 22 => x"90", + 23 => x"0b", + 24 => x"9e", + 25 => x"90", + 26 => x"0b", + 27 => x"c0", + 28 => x"90", + 29 => x"0b", + 30 => x"e2", + 31 => x"90", + 32 => x"0b", + 33 => x"84", + 34 => x"90", + 35 => x"0b", + 36 => x"a6", + 37 => x"90", + 38 => x"0b", + 39 => x"c8", + 40 => x"90", + 41 => x"0b", + 42 => x"ea", + 43 => x"90", + 44 => x"0b", + 45 => x"8c", + 46 => x"90", + 47 => x"0b", + 48 => x"ae", + 49 => x"90", + 50 => x"0b", + 51 => x"d0", + 52 => x"90", + 53 => x"0b", + 54 => x"f2", + 55 => x"90", + 56 => x"0b", + 57 => x"94", + 58 => x"90", + 59 => x"0b", + 60 => x"b6", + 61 => x"90", + 62 => x"0b", + 63 => x"d8", + 64 => x"90", + 65 => x"0b", + 66 => x"fa", + 67 => x"90", + 68 => x"0b", + 69 => x"9c", + 70 => x"90", + 71 => x"0b", + 72 => x"be", + 73 => x"90", + 74 => x"0b", + 75 => x"e0", + 76 => x"90", + 77 => x"0b", + 78 => x"82", + 79 => x"90", + 80 => x"0b", + 81 => x"a4", + 82 => x"90", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"00", + 89 => x"00", + 90 => x"00", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"00", + 97 => x"00", + 98 => x"00", + 99 => x"00", + 100 => x"00", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"00", + 105 => x"00", + 106 => x"00", + 107 => x"00", + 108 => x"00", + 109 => x"00", + 110 => x"00", + 111 => x"00", + 112 => x"00", + 113 => x"00", + 114 => x"00", + 115 => x"00", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"00", + 121 => x"00", + 122 => x"00", + 123 => x"00", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"00", + 129 => x"04", + 130 => x"0c", + 131 => x"2d", + 132 => x"08", + 133 => x"90", + 134 => x"94", + 135 => x"bf", + 136 => x"94", + 137 => x"80", + 138 => x"ca", + 139 => x"9f", + 140 => x"ca", + 141 => x"c0", + 142 => x"91", + 143 => x"90", + 144 => x"91", + 145 => x"88", + 146 => x"04", + 147 => x"0c", + 148 => x"2d", + 149 => x"08", + 150 => x"90", + 151 => x"94", + 152 => x"d8", + 153 => x"94", + 154 => x"80", + 155 => x"ca", + 156 => x"a0", + 157 => x"ca", + 158 => x"c0", + 159 => x"91", + 160 => x"90", + 161 => x"91", + 162 => x"88", + 163 => x"04", + 164 => x"0c", + 165 => x"2d", + 166 => x"08", + 167 => x"90", + 168 => x"94", + 169 => x"80", + 170 => x"94", + 171 => x"80", + 172 => x"ca", + 173 => x"a6", + 174 => x"ca", + 175 => x"c0", + 176 => x"91", + 177 => x"90", + 178 => x"91", + 179 => x"88", + 180 => x"04", + 181 => x"0c", + 182 => x"2d", + 183 => x"08", + 184 => x"90", + 185 => x"94", + 186 => x"ed", + 187 => x"94", + 188 => x"80", + 189 => x"ca", + 190 => x"90", + 191 => x"ca", + 192 => x"c0", + 193 => x"91", + 194 => x"90", + 195 => x"91", + 196 => x"88", + 197 => x"04", + 198 => x"0c", + 199 => x"2d", + 200 => x"08", + 201 => x"90", + 202 => x"94", + 203 => x"9c", + 204 => x"94", + 205 => x"80", + 206 => x"ca", + 207 => x"e9", + 208 => x"ca", + 209 => x"c0", + 210 => x"91", + 211 => x"90", + 212 => x"91", + 213 => x"88", + 214 => x"04", + 215 => x"0c", + 216 => x"2d", + 217 => x"08", + 218 => x"90", + 219 => x"94", + 220 => x"9c", + 221 => x"94", + 222 => x"80", + 223 => x"ca", + 224 => x"f6", + 225 => x"ca", + 226 => x"c0", + 227 => x"91", + 228 => x"90", + 229 => x"91", + 230 => x"88", + 231 => x"04", + 232 => x"0c", + 233 => x"2d", + 234 => x"08", + 235 => x"90", + 236 => x"94", + 237 => x"da", + 238 => x"94", + 239 => x"80", + 240 => x"ca", + 241 => x"f2", + 242 => x"ca", + 243 => x"c0", + 244 => x"91", + 245 => x"90", + 246 => x"91", + 247 => x"88", + 248 => x"04", + 249 => x"0c", + 250 => x"2d", + 251 => x"08", + 252 => x"90", + 253 => x"94", + 254 => x"b7", + 255 => x"94", + 256 => x"80", + 257 => x"ca", + 258 => x"f3", + 259 => x"ca", + 260 => x"c0", + 261 => x"91", + 262 => x"91", + 263 => x"91", + 264 => x"88", + 265 => x"04", + 266 => x"0c", + 267 => x"2d", + 268 => x"08", + 269 => x"90", + 270 => x"94", + 271 => x"ed", + 272 => x"94", + 273 => x"80", + 274 => x"ca", + 275 => x"e9", + 276 => x"ca", + 277 => x"c0", + 278 => x"91", + 279 => x"90", + 280 => x"91", + 281 => x"88", + 282 => x"04", + 283 => x"0c", + 284 => x"2d", + 285 => x"08", + 286 => x"90", + 287 => x"94", + 288 => x"a9", + 289 => x"94", + 290 => x"80", + 291 => x"ca", + 292 => x"84", + 293 => x"ca", + 294 => x"c0", + 295 => x"91", + 296 => x"91", + 297 => x"91", + 298 => x"88", + 299 => x"04", + 300 => x"0c", + 301 => x"2d", + 302 => x"08", + 303 => x"90", + 304 => x"94", + 305 => x"e1", + 306 => x"94", + 307 => x"80", + 308 => x"ca", + 309 => x"ac", + 310 => x"ca", + 311 => x"c0", + 312 => x"91", + 313 => x"90", + 314 => x"91", + 315 => x"88", + 316 => x"04", + 317 => x"0c", + 318 => x"2d", + 319 => x"08", + 320 => x"90", + 321 => x"94", + 322 => x"b2", + 323 => x"94", + 324 => x"80", + 325 => x"ca", + 326 => x"91", + 327 => x"ca", + 328 => x"c0", + 329 => x"91", + 330 => x"90", + 331 => x"91", + 332 => x"88", + 333 => x"04", + 334 => x"0c", + 335 => x"2d", + 336 => x"08", + 337 => x"90", + 338 => x"88", + 339 => x"8c", + 340 => x"80", + 341 => x"05", + 342 => x"0b", + 343 => x"04", + 344 => x"51", + 345 => x"04", + 346 => x"ca", + 347 => x"91", + 348 => x"fd", + 349 => x"53", + 350 => x"08", + 351 => x"52", + 352 => x"08", + 353 => x"51", + 354 => x"91", + 355 => x"70", + 356 => x"0c", + 357 => x"0d", + 358 => x"0c", + 359 => x"94", + 360 => x"ca", + 361 => x"3d", + 362 => x"91", + 363 => x"8c", + 364 => x"91", + 365 => x"88", + 366 => x"93", + 367 => x"88", + 368 => x"ca", + 369 => x"85", + 370 => x"ca", + 371 => x"91", + 372 => x"02", + 373 => x"0c", + 374 => x"81", + 375 => x"94", + 376 => x"0c", + 377 => x"ca", + 378 => x"05", + 379 => x"94", + 380 => x"08", + 381 => x"08", + 382 => x"27", + 383 => x"ca", + 384 => x"05", + 385 => x"ae", + 386 => x"91", + 387 => x"8c", + 388 => x"a2", + 389 => x"94", + 390 => x"08", + 391 => x"94", + 392 => x"0c", + 393 => x"08", + 394 => x"10", + 395 => x"08", + 396 => x"ff", + 397 => x"ca", + 398 => x"05", + 399 => x"80", + 400 => x"ca", + 401 => x"05", + 402 => x"94", + 403 => x"08", + 404 => x"91", + 405 => x"88", + 406 => x"ca", + 407 => x"05", + 408 => x"ca", + 409 => x"05", + 410 => x"94", + 411 => x"08", + 412 => x"08", + 413 => x"07", + 414 => x"08", + 415 => x"91", + 416 => x"fc", + 417 => x"2a", + 418 => x"08", + 419 => x"91", + 420 => x"8c", + 421 => x"2a", + 422 => x"08", + 423 => x"ff", + 424 => x"ca", + 425 => x"05", + 426 => x"93", + 427 => x"94", + 428 => x"08", + 429 => x"94", + 430 => x"0c", + 431 => x"91", + 432 => x"f8", + 433 => x"91", + 434 => x"f4", + 435 => x"91", + 436 => x"f4", + 437 => x"ca", + 438 => x"3d", + 439 => x"94", + 440 => x"3d", + 441 => x"71", + 442 => x"9f", + 443 => x"55", + 444 => x"72", + 445 => x"74", + 446 => x"70", + 447 => x"38", + 448 => x"71", + 449 => x"38", + 450 => x"81", + 451 => x"ff", + 452 => x"ff", + 453 => x"06", + 454 => x"91", + 455 => x"86", + 456 => x"74", + 457 => x"75", + 458 => x"90", + 459 => x"54", + 460 => x"27", + 461 => x"71", + 462 => x"53", + 463 => x"70", + 464 => x"0c", + 465 => x"84", + 466 => x"72", + 467 => x"05", + 468 => x"12", + 469 => x"26", + 470 => x"72", + 471 => x"72", + 472 => x"05", + 473 => x"12", + 474 => x"26", + 475 => x"53", + 476 => x"fb", + 477 => x"79", + 478 => x"83", + 479 => x"52", + 480 => x"71", + 481 => x"54", + 482 => x"73", + 483 => x"c6", + 484 => x"54", + 485 => x"70", + 486 => x"52", + 487 => x"2e", + 488 => x"33", + 489 => x"2e", + 490 => x"95", + 491 => x"81", + 492 => x"70", + 493 => x"54", + 494 => x"70", + 495 => x"33", + 496 => x"ff", + 497 => x"ff", + 498 => x"31", + 499 => x"0c", + 500 => x"3d", + 501 => x"09", + 502 => x"fd", + 503 => x"70", + 504 => x"81", + 505 => x"51", + 506 => x"38", + 507 => x"16", + 508 => x"56", + 509 => x"08", + 510 => x"73", + 511 => x"ff", + 512 => x"0b", + 513 => x"0c", + 514 => x"04", + 515 => x"80", + 516 => x"71", + 517 => x"87", + 518 => x"ca", + 519 => x"ff", + 520 => x"ff", + 521 => x"72", + 522 => x"38", + 523 => x"88", + 524 => x"0d", + 525 => x"0d", + 526 => x"70", + 527 => x"71", + 528 => x"ca", + 529 => x"51", + 530 => x"09", + 531 => x"38", + 532 => x"f1", + 533 => x"84", + 534 => x"53", + 535 => x"70", + 536 => x"53", + 537 => x"a0", + 538 => x"81", + 539 => x"2e", + 540 => x"e5", + 541 => x"ff", + 542 => x"a0", + 543 => x"06", + 544 => x"73", + 545 => x"55", + 546 => x"0c", + 547 => x"91", + 548 => x"87", + 549 => x"fc", + 550 => x"53", + 551 => x"2e", + 552 => x"3d", + 553 => x"72", + 554 => x"3f", + 555 => x"08", + 556 => x"53", + 557 => x"53", + 558 => x"88", + 559 => x"0d", + 560 => x"0d", + 561 => x"33", + 562 => x"53", + 563 => x"8b", + 564 => x"38", + 565 => x"ff", + 566 => x"52", + 567 => x"81", + 568 => x"13", + 569 => x"52", + 570 => x"80", + 571 => x"13", + 572 => x"52", + 573 => x"80", + 574 => x"13", + 575 => x"52", + 576 => x"80", + 577 => x"13", + 578 => x"52", + 579 => x"26", + 580 => x"8a", + 581 => x"87", + 582 => x"e7", + 583 => x"38", + 584 => x"c0", + 585 => x"72", + 586 => x"98", + 587 => x"13", + 588 => x"98", + 589 => x"13", + 590 => x"98", + 591 => x"13", + 592 => x"98", + 593 => x"13", + 594 => x"98", + 595 => x"13", + 596 => x"98", + 597 => x"87", + 598 => x"0c", + 599 => x"98", + 600 => x"0b", + 601 => x"9c", + 602 => x"71", + 603 => x"0c", + 604 => x"04", + 605 => x"7f", + 606 => x"98", + 607 => x"7d", + 608 => x"98", + 609 => x"7d", + 610 => x"c0", + 611 => x"5a", + 612 => x"34", + 613 => x"b4", + 614 => x"83", + 615 => x"c0", + 616 => x"5a", + 617 => x"34", + 618 => x"ac", + 619 => x"85", + 620 => x"c0", + 621 => x"5a", + 622 => x"34", + 623 => x"a4", + 624 => x"88", + 625 => x"c0", + 626 => x"5a", + 627 => x"23", + 628 => x"79", + 629 => x"06", + 630 => x"ff", + 631 => x"86", + 632 => x"85", + 633 => x"84", + 634 => x"83", + 635 => x"82", + 636 => x"7d", + 637 => x"06", + 638 => x"ec", + 639 => x"3f", + 640 => x"04", + 641 => x"02", + 642 => x"70", + 643 => x"2a", + 644 => x"70", + 645 => x"c6", + 646 => x"3d", + 647 => x"3d", + 648 => x"0b", + 649 => x"33", + 650 => x"06", + 651 => x"87", + 652 => x"51", + 653 => x"86", + 654 => x"94", + 655 => x"08", + 656 => x"70", + 657 => x"54", + 658 => x"2e", + 659 => x"91", + 660 => x"06", + 661 => x"d7", + 662 => x"32", + 663 => x"51", + 664 => x"2e", + 665 => x"93", + 666 => x"06", + 667 => x"ff", + 668 => x"81", + 669 => x"87", + 670 => x"52", + 671 => x"86", + 672 => x"94", + 673 => x"72", + 674 => x"ca", + 675 => x"3d", + 676 => x"3d", + 677 => x"05", + 678 => x"91", + 679 => x"70", + 680 => x"57", + 681 => x"c0", + 682 => x"74", + 683 => x"38", + 684 => x"94", + 685 => x"70", + 686 => x"81", + 687 => x"52", + 688 => x"8c", + 689 => x"2a", + 690 => x"51", + 691 => x"38", + 692 => x"70", + 693 => x"51", + 694 => x"8d", + 695 => x"2a", + 696 => x"51", + 697 => x"be", + 698 => x"ff", + 699 => x"c0", + 700 => x"70", + 701 => x"38", + 702 => x"90", + 703 => x"0c", + 704 => x"04", + 705 => x"79", + 706 => x"33", + 707 => x"06", + 708 => x"70", + 709 => x"fe", + 710 => x"ff", + 711 => x"0b", + 712 => x"e0", + 713 => x"ff", + 714 => x"55", + 715 => x"94", + 716 => x"80", + 717 => x"87", + 718 => x"51", + 719 => x"96", + 720 => x"06", + 721 => x"70", + 722 => x"38", + 723 => x"70", + 724 => x"51", + 725 => x"72", + 726 => x"81", + 727 => x"70", + 728 => x"38", + 729 => x"70", + 730 => x"51", + 731 => x"38", + 732 => x"06", + 733 => x"94", + 734 => x"80", + 735 => x"87", + 736 => x"52", + 737 => x"81", + 738 => x"70", + 739 => x"53", + 740 => x"ff", + 741 => x"91", + 742 => x"89", + 743 => x"fe", + 744 => x"0b", + 745 => x"33", + 746 => x"06", + 747 => x"c0", + 748 => x"72", + 749 => x"38", + 750 => x"94", + 751 => x"70", + 752 => x"81", + 753 => x"51", + 754 => x"e2", + 755 => x"ff", + 756 => x"c0", + 757 => x"70", + 758 => x"38", + 759 => x"90", + 760 => x"70", + 761 => x"91", + 762 => x"51", + 763 => x"04", + 764 => x"0b", + 765 => x"e0", + 766 => x"ff", + 767 => x"87", + 768 => x"52", + 769 => x"86", + 770 => x"94", + 771 => x"08", + 772 => x"70", + 773 => x"51", + 774 => x"70", + 775 => x"38", + 776 => x"06", + 777 => x"94", + 778 => x"80", + 779 => x"87", + 780 => x"52", + 781 => x"98", + 782 => x"2c", + 783 => x"71", + 784 => x"0c", + 785 => x"04", + 786 => x"87", + 787 => x"08", + 788 => x"8a", + 789 => x"70", + 790 => x"93", + 791 => x"9e", + 792 => x"c6", + 793 => x"c0", + 794 => x"91", + 795 => x"87", + 796 => x"08", + 797 => x"0c", + 798 => x"90", + 799 => x"f0", + 800 => x"9e", + 801 => x"c6", + 802 => x"c0", + 803 => x"91", + 804 => x"87", + 805 => x"08", + 806 => x"0c", + 807 => x"a8", + 808 => x"80", + 809 => x"9e", + 810 => x"c7", + 811 => x"c0", + 812 => x"51", + 813 => x"88", + 814 => x"9e", + 815 => x"c7", + 816 => x"0b", + 817 => x"34", + 818 => x"c0", + 819 => x"70", + 820 => x"51", + 821 => x"80", + 822 => x"81", + 823 => x"c7", + 824 => x"0b", + 825 => x"88", + 826 => x"80", + 827 => x"52", + 828 => x"2e", + 829 => x"52", + 830 => x"92", + 831 => x"87", + 832 => x"08", + 833 => x"80", + 834 => x"52", + 835 => x"83", + 836 => x"71", + 837 => x"34", + 838 => x"c0", + 839 => x"70", + 840 => x"51", + 841 => x"80", + 842 => x"81", + 843 => x"c7", + 844 => x"0b", + 845 => x"88", + 846 => x"80", + 847 => x"52", + 848 => x"83", + 849 => x"71", + 850 => x"34", + 851 => x"c0", + 852 => x"70", + 853 => x"51", + 854 => x"80", + 855 => x"81", + 856 => x"c7", + 857 => x"0b", + 858 => x"88", + 859 => x"80", + 860 => x"52", + 861 => x"83", + 862 => x"71", + 863 => x"34", + 864 => x"c0", + 865 => x"70", + 866 => x"51", + 867 => x"80", + 868 => x"81", + 869 => x"c7", + 870 => x"c0", + 871 => x"70", + 872 => x"70", + 873 => x"51", + 874 => x"c7", + 875 => x"0b", + 876 => x"88", + 877 => x"06", + 878 => x"70", + 879 => x"38", + 880 => x"91", + 881 => x"80", + 882 => x"9e", + 883 => x"88", + 884 => x"52", + 885 => x"83", + 886 => x"71", + 887 => x"34", + 888 => x"88", + 889 => x"06", + 890 => x"91", + 891 => x"83", + 892 => x"fd", + 893 => x"b4", + 894 => x"a3", + 895 => x"90", + 896 => x"80", + 897 => x"91", + 898 => x"84", + 899 => x"b4", + 900 => x"8b", + 901 => x"91", + 902 => x"80", + 903 => x"91", + 904 => x"53", + 905 => x"08", + 906 => x"c4", + 907 => x"3f", + 908 => x"33", + 909 => x"2e", + 910 => x"c6", + 911 => x"91", + 912 => x"52", + 913 => x"51", + 914 => x"91", + 915 => x"54", + 916 => x"91", + 917 => x"54", + 918 => x"92", + 919 => x"f8", + 920 => x"c6", + 921 => x"91", + 922 => x"89", + 923 => x"c7", + 924 => x"73", + 925 => x"38", + 926 => x"51", + 927 => x"91", + 928 => x"54", + 929 => x"88", + 930 => x"c0", + 931 => x"3f", + 932 => x"33", + 933 => x"2e", + 934 => x"b5", + 935 => x"ff", + 936 => x"98", + 937 => x"80", + 938 => x"91", + 939 => x"52", + 940 => x"51", + 941 => x"91", + 942 => x"54", + 943 => x"88", + 944 => x"f8", + 945 => x"3f", + 946 => x"33", + 947 => x"2e", + 948 => x"c7", + 949 => x"91", + 950 => x"88", + 951 => x"b6", + 952 => x"bb", + 953 => x"fc", + 954 => x"b6", + 955 => x"93", + 956 => x"80", + 957 => x"b6", + 958 => x"87", + 959 => x"84", + 960 => x"b7", + 961 => x"fb", + 962 => x"88", + 963 => x"b7", + 964 => x"ef", + 965 => x"8c", + 966 => x"b7", + 967 => x"e3", + 968 => x"0d", + 969 => x"0d", + 970 => x"33", + 971 => x"71", + 972 => x"38", + 973 => x"0b", + 974 => x"88", + 975 => x"08", + 976 => x"84", + 977 => x"91", + 978 => x"97", + 979 => x"94", + 980 => x"91", + 981 => x"8b", + 982 => x"a0", + 983 => x"91", + 984 => x"f7", + 985 => x"3d", + 986 => x"88", + 987 => x"80", + 988 => x"96", + 989 => x"ff", + 990 => x"c0", + 991 => x"08", + 992 => x"72", + 993 => x"07", + 994 => x"a0", + 995 => x"83", + 996 => x"ff", + 997 => x"c0", + 998 => x"08", + 999 => x"0c", + 1000 => x"0c", + 1001 => x"91", + 1002 => x"06", + 1003 => x"a0", + 1004 => x"51", + 1005 => x"04", + 1006 => x"08", + 1007 => x"84", + 1008 => x"3d", + 1009 => x"05", + 1010 => x"8a", + 1011 => x"06", + 1012 => x"51", + 1013 => x"ca", + 1014 => x"71", + 1015 => x"38", + 1016 => x"91", + 1017 => x"81", + 1018 => x"a0", + 1019 => x"91", + 1020 => x"52", + 1021 => x"85", + 1022 => x"71", + 1023 => x"0d", + 1024 => x"0d", + 1025 => x"33", + 1026 => x"08", + 1027 => x"98", + 1028 => x"ff", + 1029 => x"91", + 1030 => x"84", + 1031 => x"fd", + 1032 => x"54", + 1033 => x"81", + 1034 => x"53", + 1035 => x"8e", + 1036 => x"ff", + 1037 => x"14", + 1038 => x"3f", + 1039 => x"3d", + 1040 => x"3d", + 1041 => x"ca", + 1042 => x"91", + 1043 => x"56", + 1044 => x"70", + 1045 => x"53", + 1046 => x"2e", + 1047 => x"81", + 1048 => x"81", + 1049 => x"da", + 1050 => x"74", + 1051 => x"0c", + 1052 => x"04", + 1053 => x"66", + 1054 => x"78", + 1055 => x"5a", + 1056 => x"80", + 1057 => x"38", + 1058 => x"09", + 1059 => x"de", + 1060 => x"7a", + 1061 => x"5c", + 1062 => x"5b", + 1063 => x"09", + 1064 => x"38", + 1065 => x"39", + 1066 => x"09", + 1067 => x"38", + 1068 => x"70", + 1069 => x"33", + 1070 => x"2e", + 1071 => x"92", + 1072 => x"19", + 1073 => x"70", + 1074 => x"33", + 1075 => x"53", + 1076 => x"16", + 1077 => x"26", + 1078 => x"88", + 1079 => x"05", + 1080 => x"05", + 1081 => x"05", + 1082 => x"5b", + 1083 => x"80", + 1084 => x"30", + 1085 => x"80", + 1086 => x"cc", + 1087 => x"70", + 1088 => x"25", + 1089 => x"54", + 1090 => x"53", + 1091 => x"8c", + 1092 => x"07", + 1093 => x"05", + 1094 => x"5a", + 1095 => x"83", + 1096 => x"54", + 1097 => x"27", + 1098 => x"16", + 1099 => x"06", + 1100 => x"80", + 1101 => x"aa", + 1102 => x"cf", + 1103 => x"73", + 1104 => x"81", + 1105 => x"80", + 1106 => x"38", + 1107 => x"2e", + 1108 => x"81", + 1109 => x"80", + 1110 => x"8a", + 1111 => x"39", + 1112 => x"2e", + 1113 => x"73", + 1114 => x"8a", + 1115 => x"d3", + 1116 => x"80", + 1117 => x"80", + 1118 => x"ee", + 1119 => x"39", + 1120 => x"71", + 1121 => x"53", + 1122 => x"54", + 1123 => x"2e", + 1124 => x"15", + 1125 => x"33", + 1126 => x"72", + 1127 => x"81", + 1128 => x"39", + 1129 => x"56", + 1130 => x"27", + 1131 => x"51", + 1132 => x"75", + 1133 => x"72", + 1134 => x"38", + 1135 => x"df", + 1136 => x"16", + 1137 => x"7b", + 1138 => x"38", + 1139 => x"f2", + 1140 => x"77", + 1141 => x"12", + 1142 => x"53", + 1143 => x"5c", + 1144 => x"5c", + 1145 => x"5c", + 1146 => x"5c", + 1147 => x"51", + 1148 => x"fd", + 1149 => x"82", + 1150 => x"06", + 1151 => x"80", + 1152 => x"77", + 1153 => x"53", + 1154 => x"18", + 1155 => x"72", + 1156 => x"c4", + 1157 => x"70", + 1158 => x"25", + 1159 => x"55", + 1160 => x"8d", + 1161 => x"2e", + 1162 => x"30", + 1163 => x"5b", + 1164 => x"8f", + 1165 => x"7b", + 1166 => x"e6", + 1167 => x"ca", + 1168 => x"ff", + 1169 => x"75", + 1170 => x"9e", + 1171 => x"88", + 1172 => x"74", + 1173 => x"a7", + 1174 => x"80", + 1175 => x"38", + 1176 => x"72", + 1177 => x"54", + 1178 => x"72", + 1179 => x"05", + 1180 => x"17", + 1181 => x"77", + 1182 => x"51", + 1183 => x"9f", + 1184 => x"72", + 1185 => x"79", + 1186 => x"81", + 1187 => x"72", + 1188 => x"38", + 1189 => x"05", + 1190 => x"ad", + 1191 => x"17", + 1192 => x"81", + 1193 => x"b0", + 1194 => x"38", + 1195 => x"81", + 1196 => x"06", + 1197 => x"9f", + 1198 => x"55", + 1199 => x"97", + 1200 => x"f9", + 1201 => x"81", + 1202 => x"8b", + 1203 => x"16", + 1204 => x"73", + 1205 => x"96", + 1206 => x"e0", + 1207 => x"17", + 1208 => x"33", + 1209 => x"f9", + 1210 => x"f2", + 1211 => x"16", + 1212 => x"7b", + 1213 => x"38", + 1214 => x"c6", + 1215 => x"96", + 1216 => x"fd", + 1217 => x"3d", + 1218 => x"05", + 1219 => x"52", + 1220 => x"e0", + 1221 => x"0d", + 1222 => x"0d", + 1223 => x"a0", + 1224 => x"88", + 1225 => x"51", + 1226 => x"91", + 1227 => x"53", + 1228 => x"80", + 1229 => x"a0", + 1230 => x"0d", + 1231 => x"0d", + 1232 => x"08", + 1233 => x"98", + 1234 => x"88", + 1235 => x"52", + 1236 => x"3f", + 1237 => x"98", + 1238 => x"0d", + 1239 => x"0d", + 1240 => x"ca", + 1241 => x"56", + 1242 => x"80", + 1243 => x"2e", + 1244 => x"91", + 1245 => x"52", + 1246 => x"ca", + 1247 => x"ff", + 1248 => x"80", + 1249 => x"38", + 1250 => x"b9", + 1251 => x"32", + 1252 => x"80", + 1253 => x"52", + 1254 => x"8b", + 1255 => x"2e", + 1256 => x"14", + 1257 => x"9f", + 1258 => x"38", + 1259 => x"73", + 1260 => x"38", + 1261 => x"72", + 1262 => x"14", + 1263 => x"f8", + 1264 => x"af", + 1265 => x"52", + 1266 => x"8a", + 1267 => x"3f", + 1268 => x"91", + 1269 => x"87", + 1270 => x"fe", + 1271 => x"ca", + 1272 => x"91", + 1273 => x"77", + 1274 => x"53", + 1275 => x"72", + 1276 => x"0c", + 1277 => x"04", + 1278 => x"7a", + 1279 => x"80", + 1280 => x"58", + 1281 => x"33", + 1282 => x"a0", + 1283 => x"06", + 1284 => x"13", + 1285 => x"39", + 1286 => x"09", + 1287 => x"38", + 1288 => x"11", + 1289 => x"08", + 1290 => x"54", + 1291 => x"2e", + 1292 => x"80", + 1293 => x"08", + 1294 => x"0c", + 1295 => x"33", + 1296 => x"80", + 1297 => x"38", + 1298 => x"80", + 1299 => x"38", + 1300 => x"57", + 1301 => x"0c", + 1302 => x"33", + 1303 => x"39", + 1304 => x"74", + 1305 => x"38", + 1306 => x"80", + 1307 => x"89", + 1308 => x"38", + 1309 => x"d0", + 1310 => x"55", + 1311 => x"80", + 1312 => x"39", + 1313 => x"d9", + 1314 => x"80", + 1315 => x"27", + 1316 => x"80", + 1317 => x"89", + 1318 => x"70", + 1319 => x"55", + 1320 => x"70", + 1321 => x"55", + 1322 => x"27", + 1323 => x"14", + 1324 => x"06", + 1325 => x"74", + 1326 => x"73", + 1327 => x"38", + 1328 => x"14", + 1329 => x"05", + 1330 => x"08", + 1331 => x"54", + 1332 => x"39", + 1333 => x"84", + 1334 => x"55", + 1335 => x"81", + 1336 => x"ca", + 1337 => x"3d", + 1338 => x"3d", + 1339 => x"5a", + 1340 => x"7a", + 1341 => x"08", + 1342 => x"53", + 1343 => x"09", + 1344 => x"38", + 1345 => x"0c", + 1346 => x"ad", + 1347 => x"06", + 1348 => x"76", + 1349 => x"0c", + 1350 => x"33", + 1351 => x"73", + 1352 => x"81", + 1353 => x"38", + 1354 => x"05", + 1355 => x"08", + 1356 => x"53", + 1357 => x"2e", + 1358 => x"57", + 1359 => x"2e", + 1360 => x"39", + 1361 => x"13", + 1362 => x"08", + 1363 => x"53", + 1364 => x"55", + 1365 => x"80", + 1366 => x"14", + 1367 => x"88", + 1368 => x"27", + 1369 => x"eb", + 1370 => x"53", + 1371 => x"89", + 1372 => x"38", + 1373 => x"55", + 1374 => x"8a", + 1375 => x"a0", + 1376 => x"c2", + 1377 => x"74", + 1378 => x"e0", + 1379 => x"ff", + 1380 => x"d0", + 1381 => x"ff", + 1382 => x"90", + 1383 => x"38", + 1384 => x"81", + 1385 => x"53", + 1386 => x"ca", + 1387 => x"27", + 1388 => x"77", + 1389 => x"08", + 1390 => x"0c", + 1391 => x"33", + 1392 => x"ff", + 1393 => x"80", + 1394 => x"74", + 1395 => x"79", + 1396 => x"74", + 1397 => x"0c", + 1398 => x"04", + 1399 => x"02", + 1400 => x"51", + 1401 => x"72", + 1402 => x"91", + 1403 => x"33", + 1404 => x"ca", + 1405 => x"3d", + 1406 => x"3d", + 1407 => x"05", + 1408 => x"05", + 1409 => x"56", + 1410 => x"72", + 1411 => x"e0", + 1412 => x"2b", + 1413 => x"8c", + 1414 => x"88", + 1415 => x"2e", + 1416 => x"88", + 1417 => x"0c", + 1418 => x"8c", + 1419 => x"71", + 1420 => x"87", + 1421 => x"0c", + 1422 => x"08", + 1423 => x"51", + 1424 => x"2e", + 1425 => x"c0", + 1426 => x"51", + 1427 => x"71", + 1428 => x"80", + 1429 => x"92", + 1430 => x"98", + 1431 => x"70", + 1432 => x"38", + 1433 => x"a4", + 1434 => x"c7", + 1435 => x"51", + 1436 => x"88", + 1437 => x"0d", + 1438 => x"0d", + 1439 => x"02", + 1440 => x"05", + 1441 => x"58", + 1442 => x"52", + 1443 => x"3f", + 1444 => x"08", + 1445 => x"54", + 1446 => x"be", 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x"2e", + 1506 => x"81", + 1507 => x"74", + 1508 => x"c0", + 1509 => x"87", + 1510 => x"12", + 1511 => x"84", + 1512 => x"5f", + 1513 => x"0b", + 1514 => x"8c", + 1515 => x"0c", + 1516 => x"80", + 1517 => x"70", + 1518 => x"81", + 1519 => x"54", + 1520 => x"8c", + 1521 => x"81", + 1522 => x"7c", + 1523 => x"58", + 1524 => x"70", + 1525 => x"52", + 1526 => x"8a", + 1527 => x"98", + 1528 => x"71", + 1529 => x"c0", + 1530 => x"52", + 1531 => x"87", + 1532 => x"80", + 1533 => x"81", + 1534 => x"c0", + 1535 => x"53", + 1536 => x"82", + 1537 => x"71", + 1538 => x"19", + 1539 => x"81", + 1540 => x"ff", + 1541 => x"19", + 1542 => x"78", + 1543 => x"38", + 1544 => x"80", + 1545 => x"87", + 1546 => x"26", + 1547 => x"73", + 1548 => x"06", + 1549 => x"2e", + 1550 => x"52", + 1551 => x"91", + 1552 => x"8f", + 1553 => x"f6", + 1554 => x"02", + 1555 => x"05", + 1556 => x"05", + 1557 => x"71", + 1558 => x"57", + 1559 => x"91", + 1560 => x"81", + 1561 => x"54", + 1562 => x"38", + 1563 => x"c0", + 1564 => x"81", + 1565 => x"2e", + 1566 => x"71", + 1567 => x"38", + 1568 => x"87", + 1569 => x"11", + 1570 => x"80", + 1571 => x"80", + 1572 => x"83", + 1573 => x"38", + 1574 => x"72", + 1575 => x"2a", + 1576 => x"51", + 1577 => x"80", + 1578 => x"87", + 1579 => x"08", + 1580 => x"38", + 1581 => x"8c", + 1582 => x"96", + 1583 => x"0c", + 1584 => x"8c", + 1585 => x"08", + 1586 => x"51", + 1587 => x"38", + 1588 => x"56", + 1589 => x"80", + 1590 => x"85", + 1591 => x"77", + 1592 => x"83", + 1593 => x"75", + 1594 => x"ca", + 1595 => x"3d", + 1596 => x"3d", + 1597 => x"11", + 1598 => x"71", + 1599 => x"91", + 1600 => x"53", + 1601 => x"0d", + 1602 => x"0d", + 1603 => x"33", + 1604 => x"71", + 1605 => x"88", + 1606 => x"14", + 1607 => x"07", + 1608 => x"33", + 1609 => x"ca", + 1610 => x"53", + 1611 => x"52", + 1612 => x"04", + 1613 => x"73", + 1614 => x"92", + 1615 => x"52", + 1616 => x"81", + 1617 => x"70", + 1618 => x"70", + 1619 => x"3d", + 1620 => x"3d", + 1621 => x"52", + 1622 => x"70", + 1623 => x"34", + 1624 => x"51", + 1625 => x"81", + 1626 => x"70", + 1627 => x"70", + 1628 => x"05", + 1629 => x"88", + 1630 => x"72", + 1631 => x"0d", + 1632 => x"0d", + 1633 => x"54", + 1634 => x"80", + 1635 => x"71", + 1636 => x"53", + 1637 => x"81", + 1638 => x"ff", + 1639 => x"39", + 1640 => x"04", + 1641 => x"75", + 1642 => x"52", + 1643 => x"70", + 1644 => x"34", + 1645 => x"70", + 1646 => x"3d", + 1647 => x"3d", + 1648 => x"79", + 1649 => x"74", + 1650 => x"56", + 1651 => x"81", + 1652 => x"71", + 1653 => x"16", + 1654 => x"52", + 1655 => x"86", + 1656 => x"2e", + 1657 => x"91", + 1658 => x"86", + 1659 => x"fe", + 1660 => x"76", + 1661 => x"39", + 1662 => x"8a", + 1663 => x"51", + 1664 => x"71", + 1665 => x"33", + 1666 => x"0c", + 1667 => x"04", + 1668 => x"ca", + 1669 => x"80", + 1670 => x"88", + 1671 => x"3d", + 1672 => x"80", + 1673 => x"33", + 1674 => x"7a", + 1675 => x"38", + 1676 => x"16", + 1677 => x"16", + 1678 => x"17", + 1679 => x"fa", + 1680 => x"ca", + 1681 => x"2e", + 1682 => x"b7", + 1683 => x"88", + 1684 => x"34", + 1685 => x"70", + 1686 => x"31", + 1687 => x"59", + 1688 => x"77", + 1689 => x"82", + 1690 => x"74", + 1691 => x"81", + 1692 => x"81", + 1693 => x"53", + 1694 => x"16", + 1695 => x"e3", + 1696 => x"81", + 1697 => x"ca", + 1698 => x"3d", + 1699 => x"3d", + 1700 => x"56", + 1701 => x"74", + 1702 => x"2e", + 1703 => x"51", + 1704 => x"91", + 1705 => x"57", + 1706 => x"08", + 1707 => x"54", + 1708 => x"16", + 1709 => x"33", + 1710 => x"3f", + 1711 => x"08", + 1712 => x"38", + 1713 => x"57", + 1714 => x"0c", + 1715 => x"88", + 1716 => x"0d", + 1717 => x"0d", + 1718 => x"57", + 1719 => x"91", + 1720 => x"58", + 1721 => x"08", + 1722 => x"76", + 1723 => x"83", + 1724 => x"06", + 1725 => x"84", + 1726 => x"78", + 1727 => x"81", + 1728 => x"38", + 1729 => x"91", + 1730 => x"52", + 1731 => x"52", + 1732 => x"3f", + 1733 => x"52", + 1734 => x"51", + 1735 => x"84", + 1736 => x"d2", + 1737 => x"fc", + 1738 => x"8a", + 1739 => x"52", + 1740 => x"51", + 1741 => x"90", + 1742 => x"84", + 1743 => x"fc", + 1744 => x"17", + 1745 => x"a0", + 1746 => x"86", + 1747 => x"08", + 1748 => x"b0", + 1749 => x"55", + 1750 => x"81", + 1751 => x"f8", + 1752 => x"84", + 1753 => x"53", + 1754 => x"17", + 1755 => x"d7", + 1756 => x"88", + 1757 => x"83", + 1758 => x"77", + 1759 => x"0c", + 1760 => x"04", + 1761 => x"77", + 1762 => x"12", + 1763 => x"55", + 1764 => x"56", + 1765 => x"8d", + 1766 => x"22", + 1767 => x"ac", + 1768 => x"57", + 1769 => x"ca", + 1770 => x"3d", + 1771 => x"3d", + 1772 => x"70", + 1773 => x"57", + 1774 => x"81", + 1775 => x"98", + 1776 => x"81", + 1777 => x"74", + 1778 => x"72", + 1779 => x"f5", + 1780 => x"24", + 1781 => x"81", + 1782 => x"81", + 1783 => x"83", + 1784 => x"38", + 1785 => x"76", + 1786 => x"70", + 1787 => x"16", + 1788 => x"74", + 1789 => x"96", + 1790 => x"88", + 1791 => x"38", + 1792 => x"06", + 1793 => x"33", + 1794 => x"89", + 1795 => x"08", + 1796 => x"54", + 1797 => x"fc", + 1798 => x"ca", + 1799 => x"fe", + 1800 => x"ff", + 1801 => x"11", + 1802 => x"2b", + 1803 => x"81", + 1804 => x"2a", + 1805 => x"51", + 1806 => x"e2", + 1807 => x"ff", + 1808 => x"da", + 1809 => x"2a", + 1810 => x"05", + 1811 => x"fc", + 1812 => x"ca", + 1813 => x"c6", + 1814 => x"83", + 1815 => x"05", + 1816 => x"f9", + 1817 => x"ca", + 1818 => x"ff", + 1819 => x"ae", + 1820 => x"2a", + 1821 => x"05", + 1822 => x"fc", + 1823 => x"ca", + 1824 => x"38", + 1825 => x"83", + 1826 => x"05", + 1827 => x"f8", + 1828 => x"ca", + 1829 => x"0a", + 1830 => x"39", + 1831 => x"91", + 1832 => x"89", + 1833 => x"f8", + 1834 => x"7c", + 1835 => x"56", + 1836 => x"77", + 1837 => x"38", + 1838 => x"08", + 1839 => x"38", + 1840 => x"72", + 1841 => x"9d", + 1842 => x"24", + 1843 => x"81", + 1844 => x"82", + 1845 => x"83", + 1846 => x"38", + 1847 => x"76", + 1848 => x"70", + 1849 => x"18", + 1850 => x"76", + 1851 => x"9e", + 1852 => x"88", + 1853 => x"ca", + 1854 => x"d9", + 1855 => x"ff", + 1856 => x"05", + 1857 => x"81", + 1858 => x"54", + 1859 => x"80", + 1860 => x"77", + 1861 => x"f0", + 1862 => x"8f", + 1863 => x"51", + 1864 => x"34", + 1865 => x"17", + 1866 => x"2a", + 1867 => x"05", + 1868 => x"fa", + 1869 => x"ca", + 1870 => x"91", + 1871 => x"81", + 1872 => x"83", + 1873 => x"b4", + 1874 => x"2a", + 1875 => x"8f", + 1876 => x"2a", + 1877 => x"f0", + 1878 => x"06", + 1879 => x"72", + 1880 => x"ec", + 1881 => x"2a", + 1882 => x"05", + 1883 => x"fa", + 1884 => x"ca", + 1885 => x"91", + 1886 => x"80", + 1887 => x"83", + 1888 => x"52", + 1889 => x"fe", + 1890 => x"b4", + 1891 => x"a4", + 1892 => x"76", + 1893 => x"17", + 1894 => x"75", + 1895 => x"3f", + 1896 => x"08", + 1897 => x"88", + 1898 => x"77", + 1899 => x"77", + 1900 => x"fc", + 1901 => x"b4", + 1902 => x"51", + 1903 => x"c9", + 1904 => x"88", + 1905 => x"06", + 1906 => x"72", + 1907 => x"3f", + 1908 => x"17", + 1909 => x"ca", + 1910 => x"3d", + 1911 => x"3d", + 1912 => x"7e", + 1913 => x"56", + 1914 => x"75", + 1915 => x"74", + 1916 => x"27", + 1917 => x"80", + 1918 => x"ff", + 1919 => x"75", + 1920 => x"3f", + 1921 => x"08", + 1922 => x"88", + 1923 => x"38", + 1924 => x"54", + 1925 => x"81", + 1926 => x"39", + 1927 => x"08", + 1928 => x"39", + 1929 => x"51", + 1930 => x"91", + 1931 => x"58", + 1932 => x"08", + 1933 => x"c7", + 1934 => x"88", + 1935 => x"d2", + 1936 => x"88", + 1937 => x"cf", + 1938 => x"74", + 1939 => x"fc", + 1940 => x"ca", + 1941 => x"38", + 1942 => x"fe", + 1943 => x"08", + 1944 => x"74", + 1945 => x"38", + 1946 => x"17", + 1947 => x"33", + 1948 => x"73", + 1949 => x"77", + 1950 => x"26", + 1951 => x"80", + 1952 => x"ca", + 1953 => x"3d", + 1954 => x"3d", + 1955 => x"71", + 1956 => x"5b", + 1957 => x"8c", + 1958 => x"77", + 1959 => x"38", + 1960 => x"78", + 1961 => x"81", + 1962 => x"79", + 1963 => x"f9", + 1964 => x"55", + 1965 => x"88", + 1966 => x"e0", + 1967 => x"88", + 1968 => x"ca", + 1969 => x"2e", + 1970 => x"98", + 1971 => x"ca", + 1972 => x"82", + 1973 => x"58", + 1974 => x"70", + 1975 => x"80", + 1976 => x"38", + 1977 => x"09", + 1978 => x"e2", + 1979 => x"56", + 1980 => x"76", + 1981 => x"82", + 1982 => x"7a", + 1983 => x"3f", + 1984 => x"ca", + 1985 => x"2e", + 1986 => x"86", + 1987 => x"88", + 1988 => x"ca", + 1989 => x"70", + 1990 => x"07", + 1991 => x"7c", + 1992 => x"88", + 1993 => x"51", + 1994 => x"81", + 1995 => x"ca", + 1996 => x"2e", + 1997 => x"17", + 1998 => x"74", + 1999 => x"73", + 2000 => x"27", + 2001 => x"58", + 2002 => x"80", + 2003 => x"56", + 2004 => x"98", + 2005 => x"26", + 2006 => x"56", + 2007 => x"81", + 2008 => x"52", + 2009 => x"c6", + 2010 => x"88", + 2011 => x"b8", + 2012 => x"91", + 2013 => x"81", + 2014 => x"06", + 2015 => x"ca", + 2016 => x"91", + 2017 => x"09", + 2018 => x"72", + 2019 => x"70", + 2020 => x"51", + 2021 => x"80", + 2022 => x"78", + 2023 => x"06", + 2024 => x"73", + 2025 => x"39", + 2026 => x"52", + 2027 => x"f7", + 2028 => x"88", + 2029 => x"88", + 2030 => x"91", + 2031 => x"07", + 2032 => x"55", + 2033 => x"2e", + 2034 => x"80", + 2035 => x"75", + 2036 => x"76", + 2037 => x"3f", + 2038 => x"08", + 2039 => x"38", + 2040 => x"0c", + 2041 => x"fe", + 2042 => x"08", + 2043 => x"74", + 2044 => x"ff", + 2045 => x"0c", + 2046 => x"81", + 2047 => x"84", + 2048 => x"39", + 2049 => x"81", + 2050 => x"8c", + 2051 => x"8c", + 2052 => x"88", + 2053 => x"39", + 2054 => x"55", + 2055 => x"88", + 2056 => x"0d", + 2057 => x"0d", + 2058 => x"55", + 2059 => x"91", + 2060 => x"58", + 2061 => x"ca", + 2062 => x"d8", + 2063 => x"74", + 2064 => x"3f", + 2065 => x"08", + 2066 => x"08", + 2067 => x"59", + 2068 => x"77", + 2069 => x"70", + 2070 => x"c8", + 2071 => x"84", + 2072 => x"56", + 2073 => x"58", + 2074 => x"97", + 2075 => x"75", + 2076 => x"52", + 2077 => x"51", + 2078 => x"91", + 2079 => x"80", + 2080 => x"8a", + 2081 => x"32", + 2082 => x"72", + 2083 => x"2a", + 2084 => x"56", + 2085 => x"88", + 2086 => x"0d", + 2087 => x"0d", + 2088 => x"08", + 2089 => x"74", + 2090 => x"26", + 2091 => x"74", + 2092 => x"72", + 2093 => x"74", + 2094 => x"88", + 2095 => x"73", + 2096 => x"33", + 2097 => x"27", + 2098 => x"16", + 2099 => x"9b", + 2100 => x"2a", + 2101 => x"88", + 2102 => x"58", + 2103 => x"80", + 2104 => x"16", + 2105 => x"0c", + 2106 => x"8a", + 2107 => x"89", + 2108 => x"72", + 2109 => x"38", + 2110 => x"51", + 2111 => x"91", + 2112 => x"54", + 2113 => x"08", + 2114 => x"38", + 2115 => x"ca", + 2116 => x"8b", + 2117 => x"08", + 2118 => x"08", + 2119 => x"82", + 2120 => x"74", + 2121 => x"cb", + 2122 => x"75", + 2123 => x"3f", + 2124 => x"08", + 2125 => x"73", + 2126 => x"98", + 2127 => x"82", + 2128 => x"2e", + 2129 => x"39", + 2130 => x"39", + 2131 => x"13", + 2132 => x"74", + 2133 => x"16", + 2134 => x"18", + 2135 => x"77", + 2136 => x"0c", + 2137 => x"04", + 2138 => x"7a", + 2139 => x"12", + 2140 => x"59", + 2141 => x"80", + 2142 => x"86", + 2143 => x"98", + 2144 => x"14", + 2145 => x"55", + 2146 => x"81", + 2147 => x"83", + 2148 => x"77", + 2149 => x"81", + 2150 => x"0c", + 2151 => x"55", + 2152 => x"76", + 2153 => x"17", + 2154 => x"74", + 2155 => x"9b", + 2156 => x"39", + 2157 => x"ff", + 2158 => x"2a", + 2159 => x"81", + 2160 => x"52", + 2161 => x"e6", + 2162 => x"88", + 2163 => x"55", + 2164 => x"ca", + 2165 => x"80", + 2166 => x"55", + 2167 => x"08", + 2168 => x"f4", + 2169 => x"08", + 2170 => x"08", + 2171 => x"38", + 2172 => x"77", + 2173 => x"84", + 2174 => x"39", + 2175 => x"52", + 2176 => x"86", + 2177 => x"88", + 2178 => x"55", + 2179 => x"08", + 2180 => x"c4", + 2181 => x"91", + 2182 => x"81", + 2183 => x"81", + 2184 => x"88", + 2185 => x"b0", + 2186 => x"88", + 2187 => x"51", + 2188 => x"91", + 2189 => x"a0", + 2190 => x"15", + 2191 => x"75", + 2192 => x"3f", + 2193 => x"08", + 2194 => x"76", + 2195 => x"77", + 2196 => x"9c", + 2197 => x"55", + 2198 => x"88", + 2199 => x"0d", + 2200 => x"0d", + 2201 => x"08", + 2202 => x"80", + 2203 => x"fc", + 2204 => x"ca", + 2205 => x"91", + 2206 => x"80", + 2207 => x"ca", + 2208 => x"98", + 2209 => x"78", + 2210 => x"3f", + 2211 => x"08", + 2212 => x"88", + 2213 => x"38", + 2214 => x"08", + 2215 => x"70", + 2216 => x"58", + 2217 => x"2e", + 2218 => x"83", + 2219 => x"91", + 2220 => x"55", + 2221 => x"81", + 2222 => x"07", + 2223 => x"2e", + 2224 => x"16", + 2225 => x"2e", + 2226 => x"88", + 2227 => x"91", + 2228 => x"56", + 2229 => x"51", + 2230 => x"91", + 2231 => x"54", + 2232 => x"08", + 2233 => x"9b", + 2234 => x"2e", + 2235 => x"83", + 2236 => x"73", + 2237 => x"0c", + 2238 => x"04", + 2239 => x"76", + 2240 => x"54", + 2241 => x"91", + 2242 => x"83", + 2243 => x"76", + 2244 => x"53", + 2245 => x"2e", + 2246 => x"90", + 2247 => x"51", + 2248 => x"91", + 2249 => x"90", + 2250 => x"53", + 2251 => x"88", + 2252 => x"0d", + 2253 => x"0d", + 2254 => x"83", + 2255 => x"54", + 2256 => x"55", + 2257 => x"3f", + 2258 => x"51", + 2259 => x"2e", + 2260 => x"8b", + 2261 => x"2a", + 2262 => x"51", + 2263 => x"86", + 2264 => x"f7", + 2265 => x"7d", + 2266 => x"75", + 2267 => x"98", + 2268 => x"2e", + 2269 => x"98", + 2270 => x"78", + 2271 => x"3f", + 2272 => x"08", + 2273 => x"88", + 2274 => x"38", + 2275 => x"70", + 2276 => x"73", + 2277 => x"58", + 2278 => x"8b", + 2279 => x"bf", + 2280 => x"ff", + 2281 => x"53", + 2282 => x"34", + 2283 => x"08", + 2284 => x"e5", + 2285 => x"81", + 2286 => x"2e", + 2287 => x"70", + 2288 => x"57", + 2289 => x"9e", + 2290 => x"2e", + 2291 => x"ca", + 2292 => x"df", + 2293 => x"72", + 2294 => x"81", + 2295 => x"76", + 2296 => x"2e", + 2297 => x"52", + 2298 => x"fc", + 2299 => x"88", + 2300 => x"ca", + 2301 => x"38", + 2302 => x"fe", + 2303 => x"39", + 2304 => x"16", + 2305 => x"ca", + 2306 => x"3d", + 2307 => x"3d", + 2308 => x"08", + 2309 => x"52", + 2310 => x"c5", + 2311 => x"88", + 2312 => x"ca", + 2313 => x"38", + 2314 => x"52", + 2315 => x"de", + 2316 => x"88", + 2317 => x"ca", + 2318 => x"38", + 2319 => x"ca", + 2320 => x"9c", + 2321 => x"ea", + 2322 => x"53", + 2323 => x"9c", + 2324 => x"ea", + 2325 => x"0b", + 2326 => x"74", + 2327 => x"0c", + 2328 => x"04", + 2329 => x"75", + 2330 => x"12", + 2331 => x"53", + 2332 => x"9a", + 2333 => x"88", + 2334 => x"9c", + 2335 => x"e5", + 2336 => x"0b", + 2337 => x"85", + 2338 => x"fa", + 2339 => x"7a", + 2340 => x"0b", + 2341 => x"98", + 2342 => x"2e", + 2343 => x"80", + 2344 => x"55", + 2345 => x"17", + 2346 => x"33", + 2347 => x"51", + 2348 => x"2e", + 2349 => x"85", + 2350 => x"06", + 2351 => x"e5", + 2352 => x"2e", + 2353 => x"8b", + 2354 => x"70", + 2355 => x"34", + 2356 => x"71", + 2357 => x"05", + 2358 => x"15", + 2359 => x"27", + 2360 => x"15", + 2361 => x"80", + 2362 => x"34", + 2363 => x"52", + 2364 => x"88", + 2365 => x"17", + 2366 => x"52", + 2367 => x"3f", + 2368 => x"08", + 2369 => x"12", + 2370 => x"3f", + 2371 => x"08", + 2372 => x"98", + 2373 => x"da", + 2374 => x"88", + 2375 => x"23", + 2376 => x"04", + 2377 => x"7f", + 2378 => x"5b", + 2379 => x"33", + 2380 => x"73", + 2381 => x"38", + 2382 => x"80", + 2383 => x"38", + 2384 => x"8c", + 2385 => x"08", + 2386 => x"aa", + 2387 => x"41", + 2388 => x"33", + 2389 => x"73", + 2390 => x"81", + 2391 => x"81", + 2392 => x"dc", + 2393 => x"70", + 2394 => x"07", + 2395 => x"73", + 2396 => x"88", + 2397 => x"70", + 2398 => x"73", + 2399 => x"38", + 2400 => x"ab", + 2401 => x"52", + 2402 => x"91", + 2403 => x"88", + 2404 => x"98", + 2405 => x"61", + 2406 => x"5a", + 2407 => x"a0", + 2408 => x"e7", + 2409 => x"70", + 2410 => x"79", + 2411 => x"73", + 2412 => x"81", + 2413 => x"38", + 2414 => x"33", + 2415 => x"ae", + 2416 => x"70", + 2417 => x"82", + 2418 => x"51", + 2419 => x"54", + 2420 => x"79", + 2421 => x"74", + 2422 => x"57", + 2423 => x"af", + 2424 => x"70", + 2425 => x"51", + 2426 => x"dc", + 2427 => x"73", + 2428 => x"38", + 2429 => x"82", + 2430 => x"19", + 2431 => x"54", + 2432 => x"82", + 2433 => x"54", + 2434 => x"78", + 2435 => x"81", + 2436 => x"54", + 2437 => x"81", + 2438 => x"af", + 2439 => x"77", + 2440 => x"70", + 2441 => x"25", + 2442 => x"07", + 2443 => x"51", + 2444 => x"2e", + 2445 => x"39", + 2446 => x"80", + 2447 => x"33", + 2448 => x"73", + 2449 => x"81", + 2450 => x"81", + 2451 => x"dc", + 2452 => x"70", + 2453 => x"07", + 2454 => x"73", + 2455 => x"b5", + 2456 => x"2e", + 2457 => x"83", + 2458 => x"76", + 2459 => x"07", + 2460 => x"2e", + 2461 => x"8b", + 2462 => x"77", + 2463 => x"30", + 2464 => x"71", + 2465 => x"53", + 2466 => x"55", + 2467 => x"38", + 2468 => x"5c", + 2469 => x"75", + 2470 => x"73", + 2471 => x"38", + 2472 => x"06", + 2473 => x"11", + 2474 => x"75", + 2475 => x"3f", + 2476 => x"08", + 2477 => x"38", + 2478 => x"33", + 2479 => x"54", + 2480 => x"e6", + 2481 => x"ca", + 2482 => x"2e", + 2483 => x"ff", + 2484 => x"74", + 2485 => x"38", + 2486 => x"75", + 2487 => x"17", + 2488 => x"57", + 2489 => x"a7", + 2490 => x"91", + 2491 => x"e5", + 2492 => x"ca", + 2493 => x"38", + 2494 => x"54", + 2495 => x"89", + 2496 => x"70", + 2497 => x"57", + 2498 => x"54", + 2499 => x"81", + 2500 => x"f7", + 2501 => x"7e", + 2502 => x"2e", + 2503 => x"33", + 2504 => x"e5", + 2505 => x"06", + 2506 => x"7a", + 2507 => x"a0", + 2508 => x"38", + 2509 => x"55", + 2510 => x"84", + 2511 => x"39", + 2512 => x"8b", + 2513 => x"7b", + 2514 => x"7a", + 2515 => x"3f", + 2516 => x"08", + 2517 => x"88", + 2518 => x"38", + 2519 => x"52", + 2520 => x"aa", + 2521 => x"88", + 2522 => x"ca", + 2523 => x"c2", + 2524 => x"08", + 2525 => x"55", + 2526 => x"ff", + 2527 => x"15", + 2528 => x"54", + 2529 => x"34", + 2530 => x"70", + 2531 => x"81", + 2532 => x"58", + 2533 => x"8b", + 2534 => x"74", + 2535 => x"3f", + 2536 => x"08", + 2537 => x"38", + 2538 => x"51", + 2539 => x"ff", + 2540 => x"ab", + 2541 => x"55", + 2542 => x"bb", + 2543 => x"2e", + 2544 => x"80", + 2545 => x"85", + 2546 => x"06", + 2547 => x"58", + 2548 => x"80", + 2549 => x"75", + 2550 => x"73", + 2551 => x"b5", + 2552 => x"0b", + 2553 => x"80", + 2554 => x"39", + 2555 => x"54", + 2556 => x"85", + 2557 => x"75", + 2558 => x"81", + 2559 => x"73", + 2560 => x"1b", + 2561 => x"2a", + 2562 => x"51", + 2563 => x"80", + 2564 => x"90", + 2565 => x"ff", + 2566 => x"05", + 2567 => x"f5", + 2568 => x"ca", + 2569 => x"1c", + 2570 => x"39", + 2571 => x"88", + 2572 => x"0d", + 2573 => x"0d", + 2574 => x"7b", + 2575 => x"73", + 2576 => x"55", + 2577 => x"2e", + 2578 => x"75", + 2579 => x"57", + 2580 => x"26", + 2581 => x"ba", + 2582 => x"70", + 2583 => x"ba", + 2584 => x"06", + 2585 => x"73", + 2586 => x"70", + 2587 => x"51", + 2588 => x"89", + 2589 => x"82", + 2590 => x"ff", + 2591 => x"56", + 2592 => x"2e", + 2593 => x"80", + 2594 => x"84", + 2595 => x"08", + 2596 => x"76", + 2597 => x"58", + 2598 => x"81", + 2599 => x"ff", + 2600 => x"53", + 2601 => x"26", + 2602 => x"13", + 2603 => x"06", + 2604 => x"9f", + 2605 => x"99", + 2606 => x"e0", + 2607 => x"ff", + 2608 => x"72", + 2609 => x"2a", + 2610 => x"72", + 2611 => x"06", + 2612 => x"ff", + 2613 => x"30", + 2614 => x"70", + 2615 => x"07", + 2616 => x"9f", + 2617 => x"54", + 2618 => x"80", + 2619 => x"81", + 2620 => x"59", + 2621 => x"25", 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x"86", + 2681 => x"ca", + 2682 => x"29", + 2683 => x"05", + 2684 => x"53", + 2685 => x"80", + 2686 => x"38", + 2687 => x"76", + 2688 => x"74", + 2689 => x"72", + 2690 => x"38", + 2691 => x"51", + 2692 => x"91", + 2693 => x"81", + 2694 => x"81", + 2695 => x"72", + 2696 => x"80", + 2697 => x"38", + 2698 => x"70", + 2699 => x"53", + 2700 => x"86", + 2701 => x"a7", + 2702 => x"34", + 2703 => x"34", + 2704 => x"14", + 2705 => x"b2", + 2706 => x"88", + 2707 => x"06", + 2708 => x"54", + 2709 => x"72", + 2710 => x"76", + 2711 => x"38", + 2712 => x"70", + 2713 => x"53", + 2714 => x"85", + 2715 => x"70", + 2716 => x"5b", + 2717 => x"91", + 2718 => x"81", + 2719 => x"76", + 2720 => x"81", + 2721 => x"38", + 2722 => x"56", + 2723 => x"83", + 2724 => x"70", + 2725 => x"80", + 2726 => x"83", + 2727 => x"dc", + 2728 => x"ca", + 2729 => x"76", + 2730 => x"05", + 2731 => x"16", + 2732 => x"56", + 2733 => x"d7", + 2734 => x"8d", + 2735 => x"72", + 2736 => x"54", + 2737 => x"57", + 2738 => x"95", + 2739 => x"73", + 2740 => x"3f", + 2741 => x"08", + 2742 => x"57", + 2743 => x"89", + 2744 => x"56", + 2745 => x"d7", + 2746 => x"76", + 2747 => x"f1", + 2748 => x"76", + 2749 => x"e9", + 2750 => x"51", + 2751 => x"91", + 2752 => x"83", + 2753 => x"53", + 2754 => x"2e", + 2755 => x"84", + 2756 => x"ca", + 2757 => x"da", + 2758 => x"88", + 2759 => x"ff", + 2760 => x"8d", + 2761 => x"14", + 2762 => x"3f", + 2763 => x"08", + 2764 => x"15", + 2765 => x"14", + 2766 => x"34", + 2767 => x"33", + 2768 => x"81", + 2769 => x"54", + 2770 => x"72", + 2771 => x"91", + 2772 => x"ff", + 2773 => x"29", + 2774 => x"33", + 2775 => x"72", + 2776 => x"72", + 2777 => x"38", + 2778 => x"06", + 2779 => x"2e", + 2780 => x"56", + 2781 => x"80", + 2782 => x"da", + 2783 => x"ca", + 2784 => x"91", + 2785 => x"88", + 2786 => x"8f", + 2787 => x"56", + 2788 => x"38", + 2789 => x"51", + 2790 => x"91", + 2791 => x"83", + 2792 => x"55", + 2793 => x"80", + 2794 => x"da", + 2795 => x"ca", + 2796 => x"80", + 2797 => x"da", + 2798 => x"ca", + 2799 => x"ff", + 2800 => x"8d", + 2801 => x"2e", + 2802 => x"88", + 2803 => x"14", + 2804 => x"05", + 2805 => x"75", + 2806 => x"38", + 2807 => x"52", + 2808 => x"51", + 2809 => x"3f", + 2810 => x"08", + 2811 => x"88", + 2812 => x"82", + 2813 => x"ca", + 2814 => x"ff", + 2815 => x"26", + 2816 => x"57", + 2817 => x"f5", + 2818 => x"82", + 2819 => x"f5", + 2820 => x"81", + 2821 => x"8d", + 2822 => x"2e", + 2823 => x"82", + 2824 => x"16", + 2825 => x"16", + 2826 => x"70", + 2827 => x"7a", + 2828 => x"0c", + 2829 => x"83", + 2830 => x"06", + 2831 => x"de", + 2832 => x"ae", + 2833 => x"88", + 2834 => x"ff", + 2835 => x"56", + 2836 => x"38", + 2837 => x"38", + 2838 => x"51", + 2839 => x"91", + 2840 => x"a8", + 2841 => x"82", + 2842 => x"39", + 2843 => x"80", + 2844 => x"38", + 2845 => x"15", + 2846 => x"53", + 2847 => x"8d", + 2848 => x"15", + 2849 => x"76", + 2850 => x"51", + 2851 => x"13", + 2852 => x"8d", + 2853 => x"15", + 2854 => x"c5", + 2855 => x"90", + 2856 => x"0b", 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x"76", + 2916 => x"06", + 2917 => x"13", + 2918 => x"c0", + 2919 => x"88", + 2920 => x"52", + 2921 => x"71", + 2922 => x"55", + 2923 => x"53", + 2924 => x"0c", + 2925 => x"ca", + 2926 => x"3d", + 2927 => x"3d", + 2928 => x"05", + 2929 => x"89", + 2930 => x"52", + 2931 => x"3f", + 2932 => x"0b", + 2933 => x"08", + 2934 => x"91", + 2935 => x"84", + 2936 => x"a4", + 2937 => x"55", + 2938 => x"2e", + 2939 => x"74", + 2940 => x"73", + 2941 => x"38", + 2942 => x"78", + 2943 => x"54", + 2944 => x"92", + 2945 => x"89", + 2946 => x"84", + 2947 => x"b0", + 2948 => x"88", + 2949 => x"91", + 2950 => x"88", + 2951 => x"eb", + 2952 => x"02", + 2953 => x"e7", + 2954 => x"59", + 2955 => x"80", + 2956 => x"38", + 2957 => x"70", + 2958 => x"d0", + 2959 => x"3d", + 2960 => x"58", + 2961 => x"91", + 2962 => x"55", + 2963 => x"08", + 2964 => x"7a", + 2965 => x"8c", + 2966 => x"56", + 2967 => x"91", + 2968 => x"55", + 2969 => x"08", + 2970 => x"80", + 2971 => x"70", + 2972 => x"57", + 2973 => x"83", + 2974 => x"77", + 2975 => x"73", + 2976 => x"ab", + 2977 => x"2e", + 2978 => x"84", + 2979 => x"06", + 2980 => x"51", + 2981 => x"91", + 2982 => x"55", + 2983 => x"b2", + 2984 => x"06", + 2985 => x"b8", + 2986 => x"2a", + 2987 => x"51", + 2988 => x"2e", + 2989 => x"55", + 2990 => x"77", + 2991 => x"74", + 2992 => x"77", + 2993 => x"81", + 2994 => x"73", + 2995 => x"af", + 2996 => x"7a", + 2997 => x"3f", + 2998 => x"08", + 2999 => x"b2", + 3000 => x"8e", + 3001 => x"ea", + 3002 => x"a0", + 3003 => x"34", + 3004 => x"52", + 3005 => x"bd", + 3006 => x"62", + 3007 => x"d4", + 3008 => x"54", + 3009 => x"15", + 3010 => x"2e", + 3011 => x"7a", + 3012 => x"51", + 3013 => x"75", + 3014 => x"d4", + 3015 => x"be", + 3016 => x"88", + 3017 => x"ca", + 3018 => x"ca", + 3019 => x"74", + 3020 => x"02", + 3021 => x"70", + 3022 => x"81", + 3023 => x"56", + 3024 => x"86", + 3025 => x"82", + 3026 => x"81", + 3027 => x"06", + 3028 => x"80", + 3029 => x"75", + 3030 => x"73", + 3031 => x"38", + 3032 => x"92", + 3033 => x"7a", + 3034 => x"3f", + 3035 => x"08", + 3036 => x"8c", + 3037 => x"55", + 3038 => x"08", + 3039 => x"77", + 3040 => x"81", + 3041 => x"73", + 3042 => x"38", + 3043 => x"07", + 3044 => x"11", + 3045 => x"0c", + 3046 => x"0c", + 3047 => x"52", + 3048 => x"3f", + 3049 => x"08", + 3050 => x"08", + 3051 => x"63", + 3052 => x"5a", + 3053 => x"91", + 3054 => x"91", + 3055 => x"8c", + 3056 => x"7a", + 3057 => x"17", + 3058 => x"23", + 3059 => x"34", + 3060 => x"1a", + 3061 => x"9c", + 3062 => x"0b", + 3063 => x"77", + 3064 => x"81", + 3065 => x"73", + 3066 => x"8d", + 3067 => x"88", + 3068 => x"81", + 3069 => x"ca", + 3070 => x"1a", + 3071 => x"22", + 3072 => x"7b", + 3073 => x"a8", + 3074 => x"78", + 3075 => x"3f", + 3076 => x"08", + 3077 => x"88", + 3078 => x"83", + 3079 => x"91", + 3080 => x"ff", + 3081 => x"06", + 3082 => x"55", + 3083 => x"56", + 3084 => x"76", + 3085 => x"51", + 3086 => x"27", + 3087 => x"70", + 3088 => x"5a", + 3089 => x"76", + 3090 => x"74", + 3091 => x"83", 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x"ca", + 3151 => x"2e", + 3152 => x"91", + 3153 => x"1a", + 3154 => x"59", + 3155 => x"2e", + 3156 => x"77", + 3157 => x"11", + 3158 => x"55", + 3159 => x"85", + 3160 => x"31", + 3161 => x"76", + 3162 => x"81", + 3163 => x"ca", + 3164 => x"ca", + 3165 => x"d7", + 3166 => x"11", + 3167 => x"74", + 3168 => x"38", + 3169 => x"77", + 3170 => x"78", + 3171 => x"84", + 3172 => x"16", + 3173 => x"08", + 3174 => x"2b", + 3175 => x"cf", + 3176 => x"89", + 3177 => x"39", + 3178 => x"0c", + 3179 => x"83", + 3180 => x"80", + 3181 => x"55", + 3182 => x"83", + 3183 => x"9c", + 3184 => x"7e", + 3185 => x"3f", + 3186 => x"08", + 3187 => x"75", + 3188 => x"08", + 3189 => x"1f", + 3190 => x"7c", + 3191 => x"3f", + 3192 => x"7e", + 3193 => x"0c", + 3194 => x"1b", + 3195 => x"1c", + 3196 => x"fd", + 3197 => x"56", + 3198 => x"88", + 3199 => x"0d", + 3200 => x"0d", + 3201 => x"64", + 3202 => x"58", + 3203 => x"90", + 3204 => x"52", + 3205 => x"d2", + 3206 => x"88", + 3207 => x"ca", + 3208 => x"38", + 3209 => x"55", + 3210 => x"86", + 3211 => x"83", + 3212 => x"18", + 3213 => x"2a", + 3214 => x"51", + 3215 => x"56", + 3216 => x"83", + 3217 => x"39", + 3218 => x"19", + 3219 => x"83", + 3220 => x"0b", + 3221 => x"81", + 3222 => x"39", + 3223 => x"7c", + 3224 => x"74", + 3225 => x"38", + 3226 => x"7b", + 3227 => x"ec", + 3228 => x"08", + 3229 => x"06", + 3230 => x"81", + 3231 => x"8a", + 3232 => x"05", + 3233 => x"06", + 3234 => x"bf", + 3235 => x"38", + 3236 => x"55", + 3237 => x"7a", + 3238 => x"98", + 3239 => x"77", + 3240 => x"3f", + 3241 => x"08", + 3242 => x"88", + 3243 => x"82", + 3244 => x"81", + 3245 => x"38", + 3246 => x"ff", + 3247 => x"98", + 3248 => x"18", + 3249 => x"74", + 3250 => x"7e", + 3251 => x"08", + 3252 => x"2e", + 3253 => x"8d", + 3254 => x"ce", + 3255 => x"ca", + 3256 => x"ee", + 3257 => x"08", + 3258 => x"d1", + 3259 => x"ca", + 3260 => x"2e", + 3261 => x"91", + 3262 => x"1b", + 3263 => x"5a", + 3264 => x"2e", + 3265 => x"78", + 3266 => x"11", + 3267 => x"55", + 3268 => x"85", + 3269 => x"31", + 3270 => x"76", + 3271 => x"81", + 3272 => x"c8", + 3273 => x"ca", + 3274 => x"a6", + 3275 => x"11", + 3276 => x"56", + 3277 => x"27", + 3278 => x"80", + 3279 => x"08", + 3280 => x"2b", + 3281 => x"b4", + 3282 => x"b5", + 3283 => x"80", + 3284 => x"34", + 3285 => x"56", + 3286 => x"8c", + 3287 => x"19", + 3288 => x"38", + 3289 => x"b6", + 3290 => x"88", + 3291 => x"38", + 3292 => x"12", + 3293 => x"9c", + 3294 => x"18", + 3295 => x"06", + 3296 => x"31", + 3297 => x"76", + 3298 => x"7b", + 3299 => x"08", + 3300 => x"cd", + 3301 => x"ca", + 3302 => x"b6", + 3303 => x"7c", + 3304 => x"08", + 3305 => x"1f", + 3306 => x"cb", + 3307 => x"55", + 3308 => x"16", + 3309 => x"31", + 3310 => x"7f", + 3311 => x"94", + 3312 => x"70", + 3313 => x"8c", + 3314 => x"58", + 3315 => x"76", + 3316 => x"75", + 3317 => x"19", + 3318 => x"39", + 3319 => x"80", + 3320 => x"74", + 3321 => x"80", + 3322 => x"ca", + 3323 => x"3d", + 3324 => x"3d", + 3325 => x"3d", + 3326 => x"70", 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x"71", + 3386 => x"0c", + 3387 => x"04", + 3388 => x"80", + 3389 => x"d0", + 3390 => x"3d", + 3391 => x"3f", + 3392 => x"08", + 3393 => x"88", + 3394 => x"38", + 3395 => x"52", + 3396 => x"05", + 3397 => x"3f", + 3398 => x"08", + 3399 => x"88", + 3400 => x"02", + 3401 => x"33", + 3402 => x"55", + 3403 => x"25", + 3404 => x"7a", + 3405 => x"54", + 3406 => x"a2", + 3407 => x"84", + 3408 => x"06", + 3409 => x"73", + 3410 => x"38", + 3411 => x"70", + 3412 => x"a8", + 3413 => x"88", + 3414 => x"0c", + 3415 => x"ca", + 3416 => x"2e", + 3417 => x"83", + 3418 => x"74", + 3419 => x"0c", + 3420 => x"04", + 3421 => x"6f", + 3422 => x"80", + 3423 => x"53", + 3424 => x"b8", + 3425 => x"3d", + 3426 => x"3f", + 3427 => x"08", + 3428 => x"88", + 3429 => x"38", + 3430 => x"7c", + 3431 => x"47", + 3432 => x"54", + 3433 => x"81", + 3434 => x"52", + 3435 => x"52", + 3436 => x"3f", + 3437 => x"08", + 3438 => x"88", + 3439 => x"38", + 3440 => x"51", + 3441 => x"91", + 3442 => x"57", + 3443 => x"08", + 3444 => x"69", + 3445 => x"da", + 3446 => x"ca", + 3447 => x"76", + 3448 => x"d5", + 3449 => x"ca", + 3450 => x"91", + 3451 => x"82", + 3452 => x"52", + 3453 => x"eb", + 3454 => x"88", + 3455 => x"ca", + 3456 => x"38", + 3457 => x"51", + 3458 => x"73", + 3459 => x"08", + 3460 => x"76", + 3461 => x"d6", + 3462 => x"ca", + 3463 => x"91", + 3464 => x"80", + 3465 => x"76", + 3466 => x"81", + 3467 => x"82", + 3468 => x"39", + 3469 => x"38", + 3470 => x"bc", + 3471 => x"51", + 3472 => x"76", + 3473 => x"11", + 3474 => x"51", + 3475 => x"73", + 3476 => x"38", + 3477 => x"55", + 3478 => x"16", + 3479 => x"56", + 3480 => x"38", + 3481 => x"73", + 3482 => x"90", + 3483 => x"2e", + 3484 => x"16", + 3485 => x"ff", + 3486 => x"ff", + 3487 => x"58", + 3488 => x"74", + 3489 => x"75", + 3490 => x"18", + 3491 => x"58", + 3492 => x"fe", + 3493 => x"7b", + 3494 => x"06", + 3495 => x"18", + 3496 => x"58", + 3497 => x"80", + 3498 => x"b8", + 3499 => x"29", + 3500 => x"05", + 3501 => x"33", + 3502 => x"56", + 3503 => x"2e", + 3504 => x"16", + 3505 => x"33", + 3506 => x"73", + 3507 => x"16", + 3508 => x"26", + 3509 => x"55", + 3510 => x"91", + 3511 => x"54", + 3512 => x"70", + 3513 => x"34", + 3514 => x"ec", + 3515 => x"70", + 3516 => x"34", + 3517 => x"09", + 3518 => x"38", + 3519 => x"39", + 3520 => x"19", + 3521 => x"33", + 3522 => x"05", + 3523 => x"78", + 3524 => x"80", + 3525 => x"91", + 3526 => x"9e", + 3527 => x"f7", + 3528 => x"7d", + 3529 => x"05", + 3530 => x"57", + 3531 => x"3f", + 3532 => x"08", + 3533 => x"88", + 3534 => x"38", + 3535 => x"53", + 3536 => x"38", + 3537 => x"54", + 3538 => x"92", + 3539 => x"33", + 3540 => x"70", + 3541 => x"54", + 3542 => x"38", + 3543 => x"15", + 3544 => x"70", + 3545 => x"58", + 3546 => x"82", + 3547 => x"8a", + 3548 => x"89", + 3549 => x"53", + 3550 => x"b7", + 3551 => x"ff", + 3552 => x"9b", + 3553 => x"ca", + 3554 => x"15", + 3555 => x"53", + 3556 => x"9b", + 3557 => x"ca", + 3558 => x"26", + 3559 => x"30", + 3560 => x"70", + 3561 => x"77", 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x"90", + 3621 => x"c0", + 3622 => x"90", + 3623 => x"83", + 3624 => x"72", + 3625 => x"38", + 3626 => x"08", + 3627 => x"77", + 3628 => x"80", + 3629 => x"ca", + 3630 => x"3d", + 3631 => x"3d", + 3632 => x"89", + 3633 => x"2e", + 3634 => x"80", + 3635 => x"fc", + 3636 => x"3d", + 3637 => x"e1", + 3638 => x"ca", + 3639 => x"91", + 3640 => x"80", + 3641 => x"76", + 3642 => x"75", + 3643 => x"3f", + 3644 => x"08", + 3645 => x"88", + 3646 => x"38", + 3647 => x"70", + 3648 => x"57", + 3649 => x"a2", + 3650 => x"33", + 3651 => x"70", + 3652 => x"55", + 3653 => x"2e", + 3654 => x"16", + 3655 => x"51", + 3656 => x"91", + 3657 => x"88", + 3658 => x"54", + 3659 => x"84", + 3660 => x"52", + 3661 => x"e5", + 3662 => x"88", + 3663 => x"84", + 3664 => x"06", + 3665 => x"55", + 3666 => x"80", + 3667 => x"80", + 3668 => x"54", + 3669 => x"88", + 3670 => x"0d", + 3671 => x"0d", + 3672 => x"fc", + 3673 => x"52", + 3674 => x"3f", + 3675 => x"08", + 3676 => x"ca", + 3677 => x"0c", + 3678 => x"04", + 3679 => x"77", + 3680 => x"fc", + 3681 => x"53", + 3682 => x"de", + 3683 => x"88", + 3684 => x"ca", + 3685 => x"df", + 3686 => x"38", + 3687 => x"08", + 3688 => x"cd", + 3689 => x"ca", + 3690 => x"80", + 3691 => x"ca", + 3692 => x"73", + 3693 => x"3f", + 3694 => x"08", + 3695 => x"88", + 3696 => x"09", + 3697 => x"38", + 3698 => x"39", + 3699 => x"08", + 3700 => x"52", + 3701 => x"b3", + 3702 => x"73", + 3703 => x"3f", + 3704 => x"08", + 3705 => x"30", + 3706 => x"9f", + 3707 => x"ca", + 3708 => x"51", + 3709 => x"72", + 3710 => x"0c", + 3711 => x"04", + 3712 => x"65", + 3713 => x"89", + 3714 => x"96", + 3715 => x"df", + 3716 => x"ca", + 3717 => x"91", + 3718 => x"b2", + 3719 => x"75", + 3720 => x"3f", + 3721 => x"08", + 3722 => x"88", + 3723 => x"02", + 3724 => x"33", + 3725 => x"55", + 3726 => x"25", + 3727 => x"55", + 3728 => x"80", + 3729 => x"76", + 3730 => x"d4", + 3731 => x"91", + 3732 => x"94", + 3733 => x"f0", + 3734 => x"65", + 3735 => x"53", + 3736 => x"05", + 3737 => x"51", + 3738 => x"91", + 3739 => x"5b", + 3740 => x"08", + 3741 => x"7c", + 3742 => x"08", + 3743 => x"fe", + 3744 => x"08", + 3745 => x"55", + 3746 => x"91", + 3747 => x"0c", + 3748 => x"81", + 3749 => x"39", + 3750 => x"c7", + 3751 => x"88", + 3752 => x"55", + 3753 => x"2e", + 3754 => x"bf", + 3755 => x"5f", + 3756 => x"92", + 3757 => x"51", + 3758 => x"91", + 3759 => x"ff", + 3760 => x"91", + 3761 => x"81", + 3762 => x"91", + 3763 => x"30", + 3764 => x"88", + 3765 => x"25", + 3766 => x"19", + 3767 => x"5a", + 3768 => x"08", + 3769 => x"38", + 3770 => x"a4", + 3771 => x"ca", + 3772 => x"58", + 3773 => x"77", + 3774 => x"7d", + 3775 => x"bf", + 3776 => x"ca", + 3777 => x"91", + 3778 => x"80", + 3779 => x"70", + 3780 => x"ff", + 3781 => x"56", + 3782 => x"2e", + 3783 => x"9e", + 3784 => x"51", + 3785 => x"3f", + 3786 => x"08", + 3787 => x"06", + 3788 => x"80", + 3789 => x"19", + 3790 => x"54", + 3791 => x"14", + 3792 => x"c5", + 3793 => x"88", + 3794 => x"06", + 3795 => x"80", + 3796 => x"19", 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x"18", + 3856 => x"74", + 3857 => x"0c", + 3858 => x"04", + 3859 => x"82", + 3860 => x"ff", + 3861 => x"a1", + 3862 => x"e4", + 3863 => x"88", + 3864 => x"ca", + 3865 => x"f5", + 3866 => x"a1", + 3867 => x"95", + 3868 => x"58", + 3869 => x"91", + 3870 => x"55", + 3871 => x"08", + 3872 => x"02", + 3873 => x"33", + 3874 => x"70", + 3875 => x"55", + 3876 => x"73", + 3877 => x"75", + 3878 => x"80", + 3879 => x"bd", + 3880 => x"d6", + 3881 => x"81", + 3882 => x"87", + 3883 => x"ad", + 3884 => x"78", + 3885 => x"3f", + 3886 => x"08", + 3887 => x"70", + 3888 => x"55", + 3889 => x"2e", + 3890 => x"78", + 3891 => x"88", + 3892 => x"08", + 3893 => x"38", + 3894 => x"ca", + 3895 => x"76", + 3896 => x"70", + 3897 => x"b5", + 3898 => x"88", + 3899 => x"ca", + 3900 => x"e9", + 3901 => x"88", + 3902 => x"51", + 3903 => x"91", + 3904 => x"55", + 3905 => x"08", + 3906 => x"55", + 3907 => x"91", + 3908 => x"84", + 3909 => x"91", + 3910 => x"80", + 3911 => x"51", + 3912 => x"91", + 3913 => x"91", + 3914 => x"30", + 3915 => x"88", + 3916 => x"25", + 3917 => x"75", + 3918 => x"38", + 3919 => x"8f", + 3920 => x"75", + 3921 => x"c1", + 3922 => x"ca", + 3923 => x"74", + 3924 => x"51", + 3925 => x"3f", + 3926 => x"08", + 3927 => x"ca", + 3928 => x"3d", + 3929 => x"3d", + 3930 => x"99", + 3931 => x"52", + 3932 => x"d8", + 3933 => x"ca", + 3934 => x"91", + 3935 => x"82", + 3936 => x"5e", + 3937 => x"3d", + 3938 => x"cf", + 3939 => x"ca", + 3940 => x"91", + 3941 => x"86", + 3942 => x"82", + 3943 => x"ca", + 3944 => x"2e", + 3945 => x"82", + 3946 => x"80", + 3947 => x"70", + 3948 => x"06", + 3949 => x"54", + 3950 => x"38", + 3951 => x"52", + 3952 => x"52", + 3953 => x"3f", + 3954 => x"08", + 3955 => x"91", + 3956 => x"83", + 3957 => x"91", + 3958 => x"81", + 3959 => x"06", + 3960 => x"54", + 3961 => x"08", + 3962 => x"81", + 3963 => x"81", + 3964 => x"39", + 3965 => x"38", + 3966 => x"08", + 3967 => x"c4", + 3968 => x"ca", + 3969 => x"91", + 3970 => x"81", + 3971 => x"53", + 3972 => x"19", + 3973 => x"8c", + 3974 => x"ae", + 3975 => x"34", + 3976 => x"0b", + 3977 => x"82", + 3978 => x"52", + 3979 => x"51", + 3980 => x"3f", + 3981 => x"b4", + 3982 => x"c9", + 3983 => x"53", + 3984 => x"53", + 3985 => x"51", + 3986 => x"3f", + 3987 => x"0b", + 3988 => x"34", + 3989 => x"80", + 3990 => x"51", + 3991 => x"78", + 3992 => x"83", + 3993 => x"51", + 3994 => x"91", + 3995 => x"54", + 3996 => x"08", + 3997 => x"88", + 3998 => x"64", + 3999 => x"ff", + 4000 => x"75", + 4001 => x"78", + 4002 => x"3f", + 4003 => x"0b", + 4004 => x"78", + 4005 => x"83", + 4006 => x"51", + 4007 => x"3f", + 4008 => x"08", + 4009 => x"80", + 4010 => x"76", + 4011 => x"ae", + 4012 => x"ca", + 4013 => x"3d", + 4014 => x"3d", + 4015 => x"84", + 4016 => x"f1", + 4017 => x"a8", + 4018 => x"05", + 4019 => x"51", + 4020 => x"91", + 4021 => x"55", + 4022 => x"08", + 4023 => x"78", + 4024 => x"08", + 4025 => x"70", + 4026 => x"b8", + 4027 => x"88", + 4028 => x"ca", + 4029 => x"b9", + 4030 => x"9b", + 4031 => x"a0", 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x"91", + 4091 => x"80", + 4092 => x"16", + 4093 => x"ae", + 4094 => x"06", + 4095 => x"53", + 4096 => x"51", + 4097 => x"78", + 4098 => x"83", + 4099 => x"39", + 4100 => x"08", + 4101 => x"51", + 4102 => x"91", + 4103 => x"55", + 4104 => x"08", + 4105 => x"51", + 4106 => x"3f", + 4107 => x"08", + 4108 => x"ca", + 4109 => x"3d", + 4110 => x"3d", + 4111 => x"db", + 4112 => x"84", + 4113 => x"05", + 4114 => x"82", + 4115 => x"d0", + 4116 => x"3d", + 4117 => x"3f", + 4118 => x"08", + 4119 => x"88", + 4120 => x"38", + 4121 => x"52", + 4122 => x"05", + 4123 => x"3f", + 4124 => x"08", + 4125 => x"88", + 4126 => x"02", + 4127 => x"33", + 4128 => x"54", + 4129 => x"aa", + 4130 => x"06", + 4131 => x"8b", + 4132 => x"06", + 4133 => x"07", + 4134 => x"56", + 4135 => x"34", + 4136 => x"0b", + 4137 => x"78", + 4138 => x"a9", + 4139 => x"88", + 4140 => x"91", + 4141 => x"95", + 4142 => x"ef", + 4143 => x"56", + 4144 => x"3d", + 4145 => x"94", + 4146 => x"f4", + 4147 => x"88", + 4148 => x"ca", + 4149 => x"cb", + 4150 => x"63", + 4151 => x"d4", + 4152 => x"c0", + 4153 => x"88", + 4154 => x"ca", + 4155 => x"38", + 4156 => x"05", + 4157 => x"06", + 4158 => x"73", + 4159 => x"16", + 4160 => x"22", + 4161 => x"07", + 4162 => x"1f", + 4163 => x"c2", + 4164 => x"81", + 4165 => x"34", + 4166 => x"b3", + 4167 => x"ca", + 4168 => x"74", + 4169 => x"0c", + 4170 => x"04", + 4171 => x"69", + 4172 => x"80", + 4173 => x"d0", + 4174 => x"3d", + 4175 => x"3f", + 4176 => x"08", + 4177 => x"08", + 4178 => x"ca", + 4179 => x"80", + 4180 => x"57", + 4181 => x"81", + 4182 => x"70", + 4183 => x"55", + 4184 => x"80", + 4185 => x"5d", + 4186 => x"52", + 4187 => x"52", + 4188 => x"a9", + 4189 => x"88", + 4190 => x"ca", + 4191 => x"d1", + 4192 => x"73", + 4193 => x"3f", + 4194 => x"08", + 4195 => x"88", + 4196 => x"91", + 4197 => x"91", + 4198 => x"65", + 4199 => x"78", + 4200 => x"7b", + 4201 => x"55", + 4202 => x"34", + 4203 => x"8a", + 4204 => x"38", + 4205 => x"1a", + 4206 => x"34", + 4207 => x"9e", + 4208 => x"70", + 4209 => x"51", + 4210 => x"a0", + 4211 => x"8e", + 4212 => x"2e", + 4213 => x"86", + 4214 => x"34", + 4215 => x"30", + 4216 => x"80", + 4217 => x"7a", + 4218 => x"c1", + 4219 => x"2e", + 4220 => x"a0", + 4221 => x"51", + 4222 => x"3f", + 4223 => x"08", + 4224 => x"88", + 4225 => x"7b", + 4226 => x"55", + 4227 => x"73", + 4228 => x"38", + 4229 => x"73", + 4230 => x"38", + 4231 => x"15", + 4232 => x"ff", + 4233 => x"91", + 4234 => x"7b", + 4235 => x"ca", + 4236 => x"3d", + 4237 => x"3d", + 4238 => x"9c", + 4239 => x"05", + 4240 => x"51", + 4241 => x"91", + 4242 => x"91", + 4243 => x"56", + 4244 => x"88", + 4245 => x"38", + 4246 => x"52", + 4247 => x"52", + 4248 => x"c0", + 4249 => x"70", + 4250 => x"ff", + 4251 => x"55", + 4252 => x"27", + 4253 => x"78", + 4254 => x"ff", + 4255 => x"05", + 4256 => x"55", + 4257 => x"3f", + 4258 => x"08", + 4259 => x"38", + 4260 => x"70", + 4261 => x"ff", + 4262 => x"91", + 4263 => x"80", + 4264 => x"74", + 4265 => x"07", + 4266 => x"4e", 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x"ca", + 4326 => x"2e", + 4327 => x"80", + 4328 => x"54", + 4329 => x"80", + 4330 => x"52", + 4331 => x"bd", + 4332 => x"ca", + 4333 => x"91", + 4334 => x"b1", + 4335 => x"91", + 4336 => x"52", + 4337 => x"ab", + 4338 => x"54", + 4339 => x"15", + 4340 => x"78", + 4341 => x"ff", + 4342 => x"79", + 4343 => x"83", + 4344 => x"51", + 4345 => x"3f", + 4346 => x"08", + 4347 => x"74", + 4348 => x"0c", + 4349 => x"04", + 4350 => x"60", + 4351 => x"05", + 4352 => x"33", + 4353 => x"05", + 4354 => x"40", + 4355 => x"da", + 4356 => x"88", + 4357 => x"ca", + 4358 => x"bd", + 4359 => x"33", + 4360 => x"b5", + 4361 => x"2e", + 4362 => x"1a", + 4363 => x"90", + 4364 => x"33", + 4365 => x"70", + 4366 => x"55", + 4367 => x"38", + 4368 => x"97", + 4369 => x"82", + 4370 => x"58", + 4371 => x"7e", + 4372 => x"70", + 4373 => x"55", + 4374 => x"56", + 4375 => x"8a", + 4376 => x"7d", + 4377 => x"70", + 4378 => x"2a", + 4379 => x"08", + 4380 => x"08", + 4381 => x"5d", + 4382 => x"77", + 4383 => x"98", + 4384 => x"26", + 4385 => x"57", + 4386 => x"59", + 4387 => x"52", + 4388 => x"ae", + 4389 => x"15", + 4390 => x"98", + 4391 => x"26", + 4392 => x"55", + 4393 => x"08", + 4394 => x"99", + 4395 => x"88", + 4396 => x"ff", + 4397 => x"ca", + 4398 => x"38", + 4399 => x"75", + 4400 => x"81", + 4401 => x"93", + 4402 => x"80", + 4403 => x"2e", + 4404 => x"ff", + 4405 => x"58", + 4406 => x"7d", + 4407 => x"38", + 4408 => x"55", + 4409 => x"b4", + 4410 => x"56", + 4411 => x"09", + 4412 => x"38", + 4413 => x"53", + 4414 => x"51", + 4415 => x"3f", + 4416 => x"08", + 4417 => x"88", + 4418 => x"38", + 4419 => x"ff", + 4420 => x"5c", + 4421 => x"84", + 4422 => x"5c", + 4423 => x"12", + 4424 => x"80", + 4425 => x"78", + 4426 => x"7c", + 4427 => x"90", + 4428 => x"c0", + 4429 => x"90", + 4430 => x"15", + 4431 => x"90", + 4432 => x"54", + 4433 => x"91", + 4434 => x"31", + 4435 => x"84", + 4436 => x"07", + 4437 => x"16", + 4438 => x"73", + 4439 => x"0c", + 4440 => x"04", + 4441 => x"6b", + 4442 => x"05", + 4443 => x"33", + 4444 => x"5a", + 4445 => x"bd", + 4446 => x"80", + 4447 => x"88", + 4448 => x"f8", + 4449 => x"88", + 4450 => x"91", + 4451 => x"70", + 4452 => x"74", + 4453 => x"38", + 4454 => x"91", + 4455 => x"81", + 4456 => x"81", + 4457 => x"ff", + 4458 => x"91", + 4459 => x"81", + 4460 => x"81", + 4461 => x"83", + 4462 => x"c0", + 4463 => x"2a", + 4464 => x"51", + 4465 => x"74", + 4466 => x"99", + 4467 => x"53", + 4468 => x"51", + 4469 => x"3f", + 4470 => x"08", + 4471 => x"55", + 4472 => x"92", + 4473 => x"80", + 4474 => x"38", + 4475 => x"06", + 4476 => x"2e", + 4477 => x"48", + 4478 => x"87", + 4479 => x"79", + 4480 => x"78", + 4481 => x"26", + 4482 => x"19", + 4483 => x"74", + 4484 => x"38", + 4485 => x"e4", + 4486 => x"2a", + 4487 => x"70", + 4488 => x"59", + 4489 => x"7a", + 4490 => x"56", + 4491 => x"80", + 4492 => x"51", + 4493 => x"74", + 4494 => x"99", + 4495 => x"53", + 4496 => x"51", + 4497 => x"3f", + 4498 => x"ca", + 4499 => x"ac", + 4500 => x"2a", + 4501 => x"91", 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x"74", + 4561 => x"38", + 4562 => x"ee", + 4563 => x"66", + 4564 => x"96", + 4565 => x"88", + 4566 => x"05", + 4567 => x"88", + 4568 => x"26", + 4569 => x"0b", + 4570 => x"08", + 4571 => x"88", + 4572 => x"11", + 4573 => x"05", + 4574 => x"83", + 4575 => x"2a", + 4576 => x"a0", + 4577 => x"7d", + 4578 => x"69", + 4579 => x"05", + 4580 => x"72", + 4581 => x"5c", + 4582 => x"59", + 4583 => x"2e", + 4584 => x"89", + 4585 => x"60", + 4586 => x"84", + 4587 => x"5d", + 4588 => x"18", + 4589 => x"68", + 4590 => x"74", + 4591 => x"af", + 4592 => x"31", + 4593 => x"53", + 4594 => x"52", + 4595 => x"9a", + 4596 => x"88", + 4597 => x"83", + 4598 => x"06", + 4599 => x"ca", + 4600 => x"ff", + 4601 => x"dd", + 4602 => x"83", + 4603 => x"2a", + 4604 => x"be", + 4605 => x"39", + 4606 => x"09", + 4607 => x"c5", + 4608 => x"f5", + 4609 => x"88", + 4610 => x"38", + 4611 => x"79", + 4612 => x"80", + 4613 => x"38", + 4614 => x"96", + 4615 => x"06", + 4616 => x"2e", + 4617 => x"5e", + 4618 => x"91", + 4619 => x"9f", + 4620 => x"38", + 4621 => x"38", + 4622 => x"81", + 4623 => x"fc", + 4624 => x"ab", + 4625 => x"7d", + 4626 => x"81", + 4627 => x"7d", + 4628 => x"78", + 4629 => x"74", + 4630 => x"8e", + 4631 => x"9c", + 4632 => x"53", + 4633 => x"51", + 4634 => x"3f", + 4635 => x"b8", + 4636 => x"51", + 4637 => x"3f", + 4638 => x"8b", + 4639 => x"a1", + 4640 => x"8d", + 4641 => x"83", + 4642 => x"52", + 4643 => x"ff", + 4644 => x"81", + 4645 => x"34", + 4646 => x"70", + 4647 => x"2a", + 4648 => x"54", + 4649 => x"1b", + 4650 => x"88", + 4651 => x"74", + 4652 => x"26", + 4653 => x"83", + 4654 => x"52", + 4655 => x"ff", + 4656 => x"8a", + 4657 => x"a0", + 4658 => x"a1", + 4659 => x"0b", + 4660 => x"bf", + 4661 => x"51", + 4662 => x"3f", + 4663 => x"9a", + 4664 => x"a0", + 4665 => x"52", + 4666 => x"ff", + 4667 => x"7d", + 4668 => x"81", + 4669 => x"38", + 4670 => x"0a", + 4671 => x"1b", + 4672 => x"ce", + 4673 => x"a4", + 4674 => x"a0", + 4675 => x"52", + 4676 => x"ff", + 4677 => x"81", + 4678 => x"51", + 4679 => x"3f", + 4680 => x"1b", + 4681 => x"8c", + 4682 => x"0b", + 4683 => x"34", + 4684 => x"c2", + 4685 => x"53", + 4686 => x"52", + 4687 => x"51", + 4688 => x"88", + 4689 => x"a7", + 4690 => x"a0", + 4691 => x"83", + 4692 => x"52", + 4693 => x"ff", + 4694 => x"ff", + 4695 => x"1c", + 4696 => x"a6", + 4697 => x"53", + 4698 => x"52", + 4699 => x"ff", + 4700 => x"82", + 4701 => x"83", + 4702 => x"52", + 4703 => x"b4", + 4704 => x"60", + 4705 => x"7e", + 4706 => x"d7", + 4707 => x"91", + 4708 => x"83", + 4709 => x"83", + 4710 => x"06", + 4711 => x"75", + 4712 => x"05", + 4713 => x"7e", + 4714 => x"b7", + 4715 => x"53", + 4716 => x"51", + 4717 => x"3f", + 4718 => x"a4", + 4719 => x"51", + 4720 => x"3f", + 4721 => x"e4", + 4722 => x"e4", + 4723 => x"9f", + 4724 => x"18", + 4725 => x"1b", + 4726 => x"f6", + 4727 => x"83", + 4728 => x"ff", + 4729 => x"82", + 4730 => x"78", + 4731 => x"c4", + 4732 => x"60", + 4733 => x"7a", + 4734 => x"ff", + 4735 => x"75", + 4736 => x"53", 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x"ff", + 4796 => x"83", + 4797 => x"77", + 4798 => x"0b", + 4799 => x"81", + 4800 => x"34", + 4801 => x"34", + 4802 => x"34", + 4803 => x"56", + 4804 => x"52", + 4805 => x"f4", + 4806 => x"0b", + 4807 => x"91", + 4808 => x"82", + 4809 => x"56", + 4810 => x"34", + 4811 => x"08", + 4812 => x"60", + 4813 => x"1b", + 4814 => x"96", + 4815 => x"83", + 4816 => x"ff", + 4817 => x"81", + 4818 => x"7a", + 4819 => x"ff", + 4820 => x"81", + 4821 => x"88", + 4822 => x"80", + 4823 => x"7e", + 4824 => x"e3", + 4825 => x"91", + 4826 => x"90", + 4827 => x"8e", + 4828 => x"81", + 4829 => x"91", + 4830 => x"56", + 4831 => x"88", + 4832 => x"0d", + 4833 => x"0d", + 4834 => x"93", + 4835 => x"38", + 4836 => x"91", + 4837 => x"52", + 4838 => x"91", + 4839 => x"81", + 4840 => x"bb", + 4841 => x"f9", + 4842 => x"f8", + 4843 => x"39", + 4844 => x"51", + 4845 => x"91", + 4846 => x"80", + 4847 => x"bc", + 4848 => x"dd", + 4849 => x"c0", + 4850 => x"39", + 4851 => x"51", + 4852 => x"91", + 4853 => x"80", + 4854 => x"bd", + 4855 => x"c1", + 4856 => x"98", + 4857 => x"91", + 4858 => x"b5", + 4859 => x"c8", + 4860 => x"91", + 4861 => x"a9", + 4862 => x"88", + 4863 => x"91", + 4864 => x"9d", + 4865 => x"bc", + 4866 => x"91", + 4867 => x"91", + 4868 => x"ec", + 4869 => x"91", + 4870 => x"85", + 4871 => x"90", + 4872 => x"fb", + 4873 => x"0d", + 4874 => x"0d", + 4875 => x"56", + 4876 => x"26", + 4877 => x"52", + 4878 => x"29", + 4879 => x"87", + 4880 => x"51", + 4881 => x"3f", + 4882 => x"08", + 4883 => x"fe", + 4884 => x"91", + 4885 => x"54", + 4886 => x"52", + 4887 => x"51", + 4888 => x"3f", + 4889 => x"04", + 4890 => x"7d", + 4891 => x"8c", + 4892 => x"05", + 4893 => x"15", + 4894 => x"5a", + 4895 => x"5c", + 4896 => x"bf", + 4897 => x"8c", + 4898 => x"bf", + 4899 => x"87", + 4900 => x"55", + 4901 => x"80", + 4902 => x"90", + 4903 => x"79", + 4904 => x"38", + 4905 => x"74", + 4906 => x"78", + 4907 => x"72", + 4908 => x"bf", + 4909 => x"8c", + 4910 => x"39", + 4911 => x"51", + 4912 => x"3f", + 4913 => x"80", + 4914 => x"16", + 4915 => x"27", + 4916 => x"08", + 4917 => x"c4", + 4918 => x"a7", + 4919 => x"91", + 4920 => x"ff", + 4921 => x"84", + 4922 => x"39", + 4923 => x"72", + 4924 => x"38", + 4925 => x"91", + 4926 => x"ff", + 4927 => x"89", + 4928 => x"ec", + 4929 => x"97", + 4930 => x"55", + 4931 => x"fa", + 4932 => x"80", + 4933 => x"f0", + 4934 => x"83", + 4935 => x"74", + 4936 => x"38", + 4937 => x"33", + 4938 => x"52", + 4939 => x"74", + 4940 => x"72", + 4941 => x"38", + 4942 => x"26", + 4943 => x"51", + 4944 => x"51", + 4945 => x"3f", + 4946 => x"d3", + 4947 => x"f4", + 4948 => x"cb", + 4949 => x"77", + 4950 => x"fe", + 4951 => x"91", + 4952 => x"98", + 4953 => x"2c", + 4954 => x"a0", + 4955 => x"06", + 4956 => x"fc", + 4957 => x"ca", + 4958 => x"2b", + 4959 => x"70", + 4960 => x"30", + 4961 => x"9f", + 4962 => x"56", + 4963 => x"9b", + 4964 => x"72", + 4965 => x"9b", + 4966 => x"06", + 4967 => x"53", + 4968 => x"1c", + 4969 => x"26", + 4970 => x"ff", + 4971 => x"ca", + 4972 => x"3d", + 4973 => x"3d", + 4974 => x"84", + 4975 => x"05", + 4976 => x"30", + 4977 => x"80", + 4978 => x"ff", + 4979 => x"51", + 4980 => x"5b", + 4981 => x"74", + 4982 => x"81", + 4983 => x"8c", + 4984 => x"57", + 4985 => x"91", + 4986 => x"56", + 4987 => x"08", + 4988 => x"ca", + 4989 => x"c0", + 4990 => x"91", + 4991 => x"59", + 4992 => x"05", + 4993 => x"53", + 4994 => x"51", + 4995 => x"91", + 4996 => x"56", + 4997 => x"08", + 4998 => x"55", + 4999 => x"89", + 5000 => x"75", + 5001 => x"d8", + 5002 => x"d8", + 5003 => x"e0", + 5004 => x"70", + 5005 => x"25", + 5006 => x"80", + 5007 => x"74", + 5008 => x"38", + 5009 => x"53", + 5010 => x"88", + 5011 => x"51", + 5012 => x"75", + 5013 => x"ca", + 5014 => x"3d", + 5015 => x"3d", + 5016 => x"84", + 5017 => x"33", + 5018 => x"57", + 5019 => x"52", + 5020 => x"c2", + 5021 => x"88", + 5022 => x"75", + 5023 => x"38", + 5024 => x"98", + 5025 => x"60", + 5026 => x"91", + 5027 => x"7e", + 5028 => x"77", + 5029 => x"88", + 5030 => x"39", + 5031 => x"91", + 5032 => x"89", + 5033 => x"fc", + 5034 => x"9b", + 5035 => x"c0", + 5036 => x"c0", + 5037 => x"ff", + 5038 => x"91", + 5039 => x"51", + 5040 => x"3f", + 5041 => x"54", + 5042 => x"53", + 5043 => x"33", + 5044 => x"a8", + 5045 => x"ab", + 5046 => x"2e", + 5047 => x"fe", + 5048 => x"3d", + 5049 => x"3d", + 5050 => x"96", + 5051 => x"ff", + 5052 => x"81", + 5053 => x"8c", + 5054 => x"c4", + 5055 => x"84", + 5056 => x"fe", + 5057 => x"72", + 5058 => x"81", + 5059 => x"71", + 5060 => x"38", + 5061 => x"f5", + 5062 => x"c0", + 5063 => x"f7", + 5064 => x"51", + 5065 => x"3f", + 5066 => x"70", + 5067 => x"52", + 5068 => x"95", + 5069 => x"fe", + 5070 => x"91", + 5071 => x"fe", + 5072 => x"80", + 5073 => x"bc", + 5074 => x"2a", + 5075 => x"51", + 5076 => x"2e", + 5077 => x"51", + 5078 => x"3f", + 5079 => x"51", + 5080 => x"3f", + 5081 => x"f5", + 5082 => x"84", + 5083 => x"06", + 5084 => x"80", + 5085 => x"81", + 5086 => x"88", + 5087 => x"98", + 5088 => x"80", + 5089 => x"fe", + 5090 => x"72", + 5091 => x"81", + 5092 => x"71", + 5093 => x"38", + 5094 => x"f4", + 5095 => x"c1", + 5096 => x"f6", + 5097 => x"51", + 5098 => x"3f", + 5099 => x"70", + 5100 => x"52", + 5101 => x"95", + 5102 => x"fe", + 5103 => x"91", + 5104 => x"fe", + 5105 => x"80", + 5106 => x"b8", + 5107 => x"2a", + 5108 => x"51", + 5109 => x"2e", + 5110 => x"51", + 5111 => x"3f", + 5112 => x"51", + 5113 => x"3f", + 5114 => x"f4", + 5115 => x"88", + 5116 => x"06", + 5117 => x"80", + 5118 => x"81", + 5119 => x"84", + 5120 => x"e8", + 5121 => x"fc", + 5122 => x"fe", + 5123 => x"fe", + 5124 => x"84", + 5125 => x"fa", + 5126 => x"70", + 5127 => x"55", + 5128 => x"2e", + 5129 => x"8e", + 5130 => x"0c", + 5131 => x"53", + 5132 => x"81", + 5133 => x"74", + 5134 => x"ff", + 5135 => x"53", + 5136 => x"83", + 5137 => x"74", + 5138 => x"38", + 5139 => x"75", + 5140 => x"53", + 5141 => x"09", + 5142 => x"38", + 5143 => x"81", + 5144 => x"80", + 5145 => x"29", + 5146 => x"05", + 5147 => x"70", + 5148 => x"fe", + 5149 => x"91", + 5150 => x"8b", + 5151 => x"33", + 5152 => x"2e", + 5153 => x"81", + 5154 => x"ff", + 5155 => x"95", + 5156 => x"38", + 5157 => x"91", + 5158 => x"88", + 5159 => x"cb", + 5160 => x"70", + 5161 => x"88", + 5162 => x"81", + 5163 => x"ff", + 5164 => x"91", + 5165 => x"81", + 5166 => x"78", + 5167 => x"81", + 5168 => x"91", + 5169 => x"99", + 5170 => x"59", + 5171 => x"3f", + 5172 => x"52", + 5173 => x"51", + 5174 => x"3f", + 5175 => x"08", + 5176 => x"38", + 5177 => x"51", + 5178 => x"81", + 5179 => x"91", + 5180 => x"fe", + 5181 => x"99", + 5182 => x"5a", + 5183 => x"80", + 5184 => x"fe", + 5185 => x"80", + 5186 => x"51", + 5187 => x"3f", + 5188 => x"f8", + 5189 => x"ff", + 5190 => x"88", + 5191 => x"70", + 5192 => x"59", + 5193 => x"2e", + 5194 => x"78", + 5195 => x"80", + 5196 => x"b0", + 5197 => x"38", + 5198 => x"aa", + 5199 => x"2e", + 5200 => x"78", + 5201 => x"38", + 5202 => x"ff", + 5203 => x"82", + 5204 => x"38", + 5205 => x"78", + 5206 => x"b8", + 5207 => x"2e", + 5208 => x"8e", + 5209 => x"bf", + 5210 => x"38", + 5211 => x"90", + 5212 => x"2e", + 5213 => x"78", + 5214 => x"fc", + 5215 => x"39", + 5216 => x"2e", + 5217 => x"78", + 5218 => x"88", + 5219 => x"b7", + 5220 => x"f8", + 5221 => x"38", + 5222 => x"24", + 5223 => x"80", + 5224 => x"cd", + 5225 => x"d1", + 5226 => x"78", + 5227 => x"8b", + 5228 => x"80", + 5229 => x"a8", + 5230 => x"39", + 5231 => x"2e", + 5232 => x"78", + 5233 => x"8c", + 5234 => x"fb", + 5235 => x"83", + 5236 => x"38", + 5237 => x"24", + 5238 => x"80", + 5239 => x"81", + 5240 => x"82", + 5241 => x"38", + 5242 => x"78", + 5243 => x"8d", + 5244 => x"81", + 5245 => x"f7", + 5246 => x"39", + 5247 => x"f4", + 5248 => x"f8", + 5249 => x"83", + 5250 => x"ca", + 5251 => x"38", + 5252 => x"51", + 5253 => x"b7", + 5254 => x"11", + 5255 => x"05", + 5256 => x"d4", + 5257 => x"88", + 5258 => x"88", + 5259 => x"25", + 5260 => x"43", + 5261 => x"05", + 5262 => x"80", + 5263 => x"51", + 5264 => x"3f", + 5265 => x"08", + 5266 => x"59", + 5267 => x"91", + 5268 => x"fe", + 5269 => x"81", + 5270 => x"39", + 5271 => x"51", + 5272 => x"b7", + 5273 => x"11", + 5274 => x"05", + 5275 => x"88", + 5276 => x"88", + 5277 => x"fc", + 5278 => x"53", + 5279 => x"80", + 5280 => x"51", + 5281 => x"3f", + 5282 => x"08", + 5283 => x"a0", + 5284 => x"39", + 5285 => x"f4", + 5286 => x"f8", + 5287 => x"82", + 5288 => x"ca", + 5289 => x"2e", + 5290 => x"89", + 5291 => x"38", + 5292 => x"f0", + 5293 => x"f8", + 5294 => x"82", + 5295 => x"ca", + 5296 => x"38", + 5297 => x"08", + 5298 => x"91", + 5299 => x"79", + 5300 => x"c5", + 5301 => x"cb", + 5302 => x"79", + 5303 => x"b4", + 5304 => x"b8", + 5305 => x"b5", + 5306 => x"ca", + 5307 => x"93", + 5308 => x"f8", + 5309 => x"a7", + 5310 => x"fb", + 5311 => x"3d", + 5312 => x"51", + 5313 => x"3f", + 5314 => x"08", + 5315 => x"f8", + 5316 => x"fe", + 5317 => x"81", + 5318 => x"88", + 5319 => x"51", + 5320 => x"80", + 5321 => x"3d", + 5322 => x"51", + 5323 => x"3f", + 5324 => x"08", + 5325 => x"f8", + 5326 => x"fe", + 5327 => x"91", + 5328 => x"b8", + 5329 => x"05", + 5330 => x"ea", + 5331 => x"ca", + 5332 => x"3d", + 5333 => x"52", + 5334 => x"bb", + 5335 => x"e4", + 5336 => x"bc", + 5337 => x"80", + 5338 => x"88", + 5339 => x"06", + 5340 => x"79", + 5341 => x"f5", + 5342 => x"ca", + 5343 => x"2e", + 5344 => x"91", + 5345 => x"51", + 5346 => x"fa", + 5347 => x"3d", + 5348 => x"53", + 5349 => x"51", + 5350 => x"3f", + 5351 => x"08", + 5352 => x"cb", + 5353 => x"fe", + 5354 => x"fe", + 5355 => x"ff", + 5356 => x"91", + 5357 => x"80", + 5358 => x"38", + 5359 => x"ec", + 5360 => x"f8", + 5361 => x"80", + 5362 => x"ca", + 5363 => x"38", + 5364 => x"08", + 5365 => x"ac", + 5366 => x"c3", + 5367 => x"5c", + 5368 => x"27", + 5369 => x"61", + 5370 => x"70", + 5371 => x"0c", + 5372 => x"f5", + 5373 => x"39", + 5374 => x"f4", + 5375 => x"f8", + 5376 => x"ff", + 5377 => x"ca", + 5378 => x"2e", + 5379 => x"b7", + 5380 => x"11", + 5381 => x"05", + 5382 => x"dc", + 5383 => x"88", + 5384 => x"f9", + 5385 => x"3d", + 5386 => x"53", + 5387 => x"51", + 5388 => x"3f", + 5389 => x"08", + 5390 => x"b3", + 5391 => x"b8", + 5392 => x"db", + 5393 => x"79", + 5394 => x"8c", + 5395 => x"79", + 5396 => x"5b", + 5397 => x"61", + 5398 => x"eb", + 5399 => x"fe", + 5400 => x"fe", + 5401 => x"fe", + 5402 => x"91", + 5403 => x"80", + 5404 => x"38", + 5405 => x"f0", + 5406 => x"f8", + 5407 => x"fe", + 5408 => x"ca", + 5409 => x"2e", + 5410 => x"b7", + 5411 => x"11", + 5412 => x"05", + 5413 => x"e0", + 5414 => x"88", + 5415 => x"f8", + 5416 => x"c3", + 5417 => x"f6", + 5418 => x"5a", + 5419 => x"a8", + 5420 => x"33", + 5421 => x"5a", + 5422 => x"2e", + 5423 => x"55", + 5424 => x"33", + 5425 => x"91", + 5426 => x"fe", + 5427 => x"81", + 5428 => x"05", + 5429 => x"39", + 5430 => x"51", + 5431 => x"b7", + 5432 => x"11", + 5433 => x"05", + 5434 => x"8c", + 5435 => x"88", + 5436 => x"38", + 5437 => x"33", + 5438 => x"2e", + 5439 => x"c6", + 5440 => x"b3", + 5441 => x"92", + 5442 => x"80", + 5443 => x"91", + 5444 => x"44", + 5445 => x"c7", + 5446 => x"78", + 5447 => x"c7", + 5448 => x"78", + 5449 => x"38", + 5450 => x"08", + 5451 => x"91", + 5452 => x"fc", + 5453 => x"b7", + 5454 => x"11", + 5455 => x"05", + 5456 => x"b4", + 5457 => x"88", + 5458 => x"38", + 5459 => x"33", + 5460 => x"2e", + 5461 => x"c6", + 5462 => x"b2", + 5463 => x"92", + 5464 => x"80", + 5465 => x"91", + 5466 => x"43", + 5467 => x"c7", + 5468 => x"78", + 5469 => x"c7", + 5470 => x"78", + 5471 => x"38", + 5472 => x"08", + 5473 => x"91", + 5474 => x"88", + 5475 => x"3d", + 5476 => x"53", + 5477 => x"51", + 5478 => x"3f", + 5479 => x"08", + 5480 => x"38", + 5481 => x"59", + 5482 => x"83", + 5483 => x"79", + 5484 => x"38", + 5485 => x"88", + 5486 => x"2e", + 5487 => x"42", + 5488 => x"51", + 5489 => x"3f", + 5490 => x"54", + 5491 => x"52", + 5492 => x"94", + 5493 => x"80", + 5494 => x"39", + 5495 => x"f4", + 5496 => x"f8", + 5497 => x"fc", + 5498 => x"ca", + 5499 => x"2e", + 5500 => x"b7", + 5501 => x"11", + 5502 => x"05", + 5503 => x"f8", + 5504 => x"88", + 5505 => x"a5", + 5506 => x"02", + 5507 => x"33", + 5508 => x"81", + 5509 => x"3d", + 5510 => x"53", + 5511 => x"51", + 5512 => x"3f", + 5513 => x"08", + 5514 => x"c3", + 5515 => x"33", + 5516 => x"c4", + 5517 => x"f9", + 5518 => x"f8", + 5519 => x"fe", + 5520 => x"79", + 5521 => x"59", + 5522 => x"f5", + 5523 => x"79", + 5524 => x"b7", + 5525 => x"11", + 5526 => x"05", + 5527 => x"98", + 5528 => x"88", + 5529 => x"91", + 5530 => x"02", + 5531 => x"33", + 5532 => x"81", + 5533 => x"b5", + 5534 => x"98", + 5535 => x"9f", + 5536 => x"39", + 5537 => x"e8", + 5538 => x"f8", + 5539 => x"fc", + 5540 => x"ca", + 5541 => x"2e", + 5542 => x"b7", + 5543 => x"11", + 5544 => x"05", + 5545 => x"c2", + 5546 => x"88", + 5547 => x"a6", + 5548 => x"02", + 5549 => x"79", + 5550 => x"5b", + 5551 => x"b7", + 5552 => x"11", + 5553 => x"05", + 5554 => x"9e", + 5555 => x"88", + 5556 => x"f4", + 5557 => x"70", + 5558 => x"91", + 5559 => x"fe", + 5560 => x"80", + 5561 => x"51", + 5562 => x"3f", + 5563 => x"33", + 5564 => x"2e", + 5565 => x"78", + 5566 => x"38", + 5567 => x"41", + 5568 => x"3d", + 5569 => x"53", + 5570 => x"51", + 5571 => x"3f", + 5572 => x"08", + 5573 => x"38", + 5574 => x"be", + 5575 => x"70", + 5576 => x"23", + 5577 => x"ae", + 5578 => x"98", + 5579 => x"ef", + 5580 => x"39", + 5581 => x"e8", + 5582 => x"f8", + 5583 => x"fb", + 5584 => x"ca", + 5585 => x"2e", + 5586 => x"b7", + 5587 => x"11", + 5588 => x"05", + 5589 => x"92", + 5590 => x"88", + 5591 => x"a1", + 5592 => x"71", + 5593 => x"84", + 5594 => x"3d", + 5595 => x"53", + 5596 => x"51", + 5597 => x"3f", + 5598 => x"08", + 5599 => x"ef", + 5600 => x"08", + 5601 => x"c4", + 5602 => x"f6", + 5603 => x"f8", + 5604 => x"fe", + 5605 => x"79", + 5606 => x"59", + 5607 => x"f2", + 5608 => x"79", + 5609 => x"b7", + 5610 => x"11", + 5611 => x"05", + 5612 => x"b6", + 5613 => x"88", + 5614 => x"99", + 5615 => x"60", + 5616 => x"ac", + 5617 => x"bb", + 5618 => x"71", + 5619 => x"84", + 5620 => x"ad", + 5621 => x"98", + 5622 => x"c3", + 5623 => x"39", + 5624 => x"51", + 5625 => x"3f", + 5626 => x"ef", + 5627 => x"ff", + 5628 => x"d0", + 5629 => x"a7", + 5630 => x"fe", + 5631 => x"f1", + 5632 => x"80", + 5633 => x"c0", + 5634 => x"84", + 5635 => x"87", + 5636 => x"0c", + 5637 => x"51", + 5638 => x"3f", + 5639 => x"91", + 5640 => x"fe", + 5641 => x"8c", + 5642 => x"87", + 5643 => x"0c", + 5644 => x"0b", + 5645 => x"94", + 5646 => x"39", + 5647 => x"f4", + 5648 => x"f8", + 5649 => x"f7", + 5650 => x"ca", + 5651 => x"2e", + 5652 => x"63", + 5653 => x"90", + 5654 => x"a7", + 5655 => x"78", + 5656 => x"fe", + 5657 => x"fe", + 5658 => x"fe", + 5659 => x"91", + 5660 => x"80", + 5661 => x"38", + 5662 => x"c5", + 5663 => x"f5", + 5664 => x"59", + 5665 => x"ca", + 5666 => x"91", + 5667 => x"80", + 5668 => x"38", + 5669 => x"08", + 5670 => x"c8", + 5671 => x"e3", + 5672 => x"39", + 5673 => x"51", + 5674 => x"3f", + 5675 => x"3f", + 5676 => x"91", + 5677 => x"fe", + 5678 => x"80", + 5679 => x"39", + 5680 => x"3f", + 5681 => x"64", + 5682 => x"59", + 5683 => x"f0", + 5684 => x"80", + 5685 => x"38", + 5686 => x"80", + 5687 => x"3d", + 5688 => x"51", + 5689 => x"3f", + 5690 => x"56", + 5691 => x"08", + 5692 => x"98", + 5693 => x"91", + 5694 => x"a3", + 5695 => x"5a", + 5696 => x"3f", + 5697 => x"58", + 5698 => x"57", + 5699 => x"81", + 5700 => x"05", + 5701 => x"91", + 5702 => x"91", + 5703 => x"79", + 5704 => x"3f", + 5705 => x"08", + 5706 => x"32", + 5707 => x"07", + 5708 => x"38", + 5709 => x"09", + 5710 => x"b3", + 5711 => x"ac", + 5712 => x"bf", + 5713 => x"39", + 5714 => x"80", + 5715 => x"bc", + 5716 => x"9b", + 5717 => x"98", + 5718 => x"9c", + 5719 => x"9c", + 5720 => x"e4", + 5721 => x"87", + 5722 => x"bc", + 5723 => x"94", + 5724 => x"c8", + 5725 => x"a7", + 5726 => x"e3", + 5727 => x"ea", + 5728 => x"ea", + 5729 => x"97", + 5730 => x"00", + 5731 => x"00", + 5732 => x"00", + 5733 => x"00", + 5734 => x"00", + 5735 => x"00", + 5736 => x"00", + 5737 => x"00", + 5738 => x"00", + 5739 => x"00", + 5740 => x"00", + 5741 => x"00", + 5742 => x"00", + 5743 => x"00", + 5744 => x"00", + 5745 => x"00", + 5746 => x"00", + 5747 => x"00", + 5748 => x"00", + 5749 => x"00", + 5750 => x"00", + 5751 => x"00", + 5752 => x"00", + 5753 => x"00", + 5754 => x"00", + 5755 => x"25", + 5756 => x"64", + 5757 => x"20", + 5758 => x"25", + 5759 => x"64", + 5760 => x"25", + 5761 => x"53", + 5762 => x"43", + 5763 => x"69", + 5764 => x"61", + 5765 => x"6e", + 5766 => x"20", + 5767 => x"6f", + 5768 => x"6f", + 5769 => x"6f", + 5770 => x"67", + 5771 => x"3a", + 5772 => x"76", + 5773 => x"73", + 5774 => x"70", + 5775 => x"65", + 5776 => x"64", + 5777 => x"20", + 5778 => x"49", + 5779 => x"20", + 5780 => x"4d", + 5781 => x"74", + 5782 => x"3d", + 5783 => x"58", + 5784 => x"69", + 5785 => x"25", + 5786 => x"29", + 5787 => x"20", + 5788 => x"42", + 5789 => x"20", + 5790 => x"61", + 5791 => x"25", + 5792 => x"2c", + 5793 => x"7a", + 5794 => x"30", + 5795 => x"2e", + 5796 => x"20", + 5797 => x"52", + 5798 => x"28", + 5799 => x"72", + 5800 => x"30", + 5801 => x"20", + 5802 => x"65", + 5803 => x"38", + 5804 => x"0a", + 5805 => x"20", + 5806 => x"49", + 5807 => x"4c", + 5808 => x"20", + 5809 => x"50", + 5810 => x"00", + 5811 => x"20", + 5812 => x"53", + 5813 => x"00", + 5814 => x"20", + 5815 => x"53", + 5816 => x"61", + 5817 => x"28", + 5818 => x"69", + 5819 => x"3d", + 5820 => x"58", + 5821 => x"00", + 5822 => x"20", + 5823 => x"49", + 5824 => x"52", + 5825 => x"54", + 5826 => x"4e", + 5827 => x"4c", + 5828 => x"0a", + 5829 => x"20", + 5830 => x"54", + 5831 => x"52", + 5832 => x"54", + 5833 => x"72", + 5834 => x"30", + 5835 => x"2e", + 5836 => x"41", + 5837 => x"65", + 5838 => x"73", + 5839 => x"20", + 5840 => x"43", + 5841 => x"52", + 5842 => x"74", + 5843 => x"63", + 5844 => x"20", + 5845 => x"72", + 5846 => x"20", + 5847 => x"30", + 5848 => x"00", + 5849 => x"20", + 5850 => x"43", + 5851 => x"4d", + 5852 => x"72", + 5853 => x"74", + 5854 => x"20", + 5855 => x"72", + 5856 => x"20", + 5857 => x"30", + 5858 => x"00", + 5859 => x"20", + 5860 => x"53", + 5861 => x"6b", + 5862 => x"61", + 5863 => x"41", + 5864 => x"65", + 5865 => x"20", + 5866 => x"20", + 5867 => x"30", + 5868 => x"00", + 5869 => x"20", + 5870 => x"5a", + 5871 => x"49", + 5872 => x"20", + 5873 => x"20", + 5874 => x"20", + 5875 => x"20", + 5876 => x"20", + 5877 => x"30", + 5878 => x"00", + 5879 => x"20", + 5880 => x"53", + 5881 => x"65", + 5882 => x"6c", + 5883 => x"20", + 5884 => x"71", + 5885 => x"20", + 5886 => x"20", + 5887 => x"30", + 5888 => x"00", + 5889 => x"53", + 5890 => x"6c", + 5891 => x"4d", + 5892 => x"75", + 5893 => x"46", + 5894 => x"00", + 5895 => x"45", + 5896 => x"45", + 5897 => x"69", + 5898 => x"55", + 5899 => x"6f", + 5900 => x"53", + 5901 => x"22", + 5902 => x"3a", + 5903 => x"3e", + 5904 => x"7c", + 5905 => x"46", + 5906 => x"46", + 5907 => x"32", + 5908 => x"eb", + 5909 => x"53", + 5910 => x"35", + 5911 => x"4e", + 5912 => x"41", + 5913 => x"20", + 5914 => x"41", + 5915 => x"20", + 5916 => x"4e", + 5917 => x"41", + 5918 => x"20", + 5919 => x"41", + 5920 => x"20", + 5921 => x"00", + 5922 => x"00", + 5923 => x"00", + 5924 => x"00", + 5925 => x"80", + 5926 => x"8e", + 5927 => x"45", + 5928 => x"49", + 5929 => x"90", + 5930 => x"99", + 5931 => x"59", + 5932 => x"9c", + 5933 => x"41", + 5934 => x"a5", + 5935 => x"a8", + 5936 => x"ac", + 5937 => x"b0", + 5938 => x"b4", + 5939 => x"b8", + 5940 => x"bc", + 5941 => x"c0", + 5942 => x"c4", + 5943 => x"c8", + 5944 => x"cc", + 5945 => x"d0", + 5946 => x"d4", + 5947 => x"d8", + 5948 => x"dc", + 5949 => x"e0", + 5950 => x"e4", + 5951 => x"e8", + 5952 => x"ec", + 5953 => x"f0", + 5954 => x"f4", + 5955 => x"f8", + 5956 => x"fc", + 5957 => x"2b", + 5958 => x"3d", + 5959 => x"5c", + 5960 => x"3c", + 5961 => x"7f", + 5962 => x"00", + 5963 => x"00", + 5964 => x"01", + 5965 => x"00", + 5966 => x"00", + 5967 => x"00", + 5968 => x"00", + 5969 => x"00", + 5970 => x"64", + 5971 => x"74", + 5972 => x"64", + 5973 => x"74", + 5974 => x"66", + 5975 => x"74", + 5976 => x"66", + 5977 => x"64", + 5978 => x"66", + 5979 => x"63", + 5980 => x"6d", + 5981 => x"61", + 5982 => x"6d", + 5983 => x"79", + 5984 => x"6d", + 5985 => x"66", + 5986 => x"6d", + 5987 => x"70", + 5988 => x"6d", + 5989 => x"6d", + 5990 => x"6d", + 5991 => x"68", + 5992 => x"68", + 5993 => x"68", + 5994 => x"68", + 5995 => x"63", + 5996 => x"00", + 5997 => x"6a", + 5998 => x"72", + 5999 => x"61", + 6000 => x"72", + 6001 => x"74", + 6002 => x"69", + 6003 => x"00", + 6004 => x"74", + 6005 => x"00", + 6006 => x"44", + 6007 => x"20", + 6008 => x"6f", + 6009 => x"49", + 6010 => x"72", + 6011 => x"20", + 6012 => x"6f", + 6013 => x"00", + 6014 => x"44", + 6015 => x"20", + 6016 => x"20", + 6017 => x"64", + 6018 => x"00", + 6019 => x"4e", + 6020 => x"69", + 6021 => x"66", + 6022 => x"64", + 6023 => x"4e", + 6024 => x"61", + 6025 => x"66", + 6026 => x"64", + 6027 => x"49", + 6028 => x"6c", + 6029 => x"66", + 6030 => x"6e", + 6031 => x"2e", + 6032 => x"41", + 6033 => x"73", + 6034 => x"65", + 6035 => x"64", + 6036 => x"46", + 6037 => x"20", + 6038 => x"65", + 6039 => x"20", + 6040 => x"73", + 6041 => x"0a", + 6042 => x"46", + 6043 => x"20", + 6044 => x"64", + 6045 => x"69", + 6046 => x"6c", + 6047 => x"0a", + 6048 => x"53", + 6049 => x"73", + 6050 => x"69", + 6051 => x"70", + 6052 => x"65", + 6053 => x"64", + 6054 => x"44", + 6055 => x"65", + 6056 => x"6d", + 6057 => x"20", + 6058 => x"69", + 6059 => x"6c", + 6060 => x"0a", + 6061 => x"44", + 6062 => x"20", + 6063 => x"20", + 6064 => x"62", + 6065 => x"2e", + 6066 => x"4e", + 6067 => x"6f", + 6068 => x"74", + 6069 => x"65", + 6070 => x"6c", + 6071 => x"73", + 6072 => x"20", + 6073 => x"6e", + 6074 => x"6e", + 6075 => x"73", + 6076 => x"00", + 6077 => x"46", + 6078 => x"61", + 6079 => x"62", + 6080 => x"65", + 6081 => x"00", + 6082 => x"54", + 6083 => x"6f", + 6084 => x"20", + 6085 => x"72", + 6086 => x"6f", + 6087 => x"61", + 6088 => x"6c", + 6089 => x"2e", + 6090 => x"46", + 6091 => x"20", + 6092 => x"6c", + 6093 => x"65", + 6094 => x"00", + 6095 => x"49", + 6096 => x"66", + 6097 => x"69", + 6098 => x"20", + 6099 => x"6f", + 6100 => x"0a", + 6101 => x"54", + 6102 => x"6d", + 6103 => x"20", + 6104 => x"6e", + 6105 => x"6c", + 6106 => x"0a", + 6107 => x"50", + 6108 => x"6d", + 6109 => x"72", + 6110 => x"6e", + 6111 => x"72", + 6112 => x"2e", + 6113 => x"53", + 6114 => x"65", + 6115 => x"0a", + 6116 => x"55", + 6117 => x"6f", + 6118 => x"65", + 6119 => x"72", + 6120 => x"0a", + 6121 => x"20", + 6122 => x"65", + 6123 => x"73", + 6124 => x"20", + 6125 => x"20", + 6126 => x"65", + 6127 => x"65", + 6128 => x"00", + 6129 => x"25", + 6130 => x"00", + 6131 => x"3a", + 6132 => x"25", + 6133 => x"00", + 6134 => x"20", + 6135 => x"20", + 6136 => x"00", + 6137 => x"25", + 6138 => x"00", + 6139 => x"20", + 6140 => x"20", + 6141 => x"7c", + 6142 => x"72", + 6143 => x"00", + 6144 => x"5a", + 6145 => x"41", + 6146 => x"0a", + 6147 => x"25", + 6148 => x"00", + 6149 => x"31", + 6150 => x"37", + 6151 => x"31", + 6152 => x"76", + 6153 => x"00", + 6154 => x"20", + 6155 => x"2c", + 6156 => x"76", + 6157 => x"32", + 6158 => x"25", + 6159 => x"73", + 6160 => x"0a", + 6161 => x"5a", + 6162 => x"41", + 6163 => x"74", + 6164 => x"75", + 6165 => x"48", + 6166 => x"6c", + 6167 => x"00", + 6168 => x"54", + 6169 => x"72", + 6170 => x"74", + 6171 => x"75", + 6172 => x"00", + 6173 => x"50", + 6174 => x"69", + 6175 => x"72", + 6176 => x"74", + 6177 => x"49", + 6178 => x"4c", + 6179 => x"20", + 6180 => x"65", + 6181 => x"70", + 6182 => x"49", + 6183 => x"4c", + 6184 => x"20", + 6185 => x"65", + 6186 => x"70", + 6187 => x"55", + 6188 => x"30", + 6189 => x"20", + 6190 => x"65", + 6191 => x"70", + 6192 => x"55", + 6193 => x"30", + 6194 => x"20", + 6195 => x"65", + 6196 => x"70", + 6197 => x"55", + 6198 => x"31", + 6199 => x"20", + 6200 => x"65", + 6201 => x"70", + 6202 => x"55", + 6203 => x"31", + 6204 => x"20", + 6205 => x"65", + 6206 => x"70", + 6207 => x"53", + 6208 => x"69", + 6209 => x"75", + 6210 => x"69", + 6211 => x"2e", + 6212 => x"00", + 6213 => x"45", + 6214 => x"6c", + 6215 => x"20", + 6216 => x"65", + 6217 => x"2e", + 6218 => x"30", + 6219 => x"46", + 6220 => x"65", + 6221 => x"6f", + 6222 => x"69", + 6223 => x"6c", + 6224 => x"20", + 6225 => x"63", + 6226 => x"20", + 6227 => x"70", + 6228 => x"73", + 6229 => x"6e", + 6230 => x"6d", + 6231 => x"61", + 6232 => x"2e", + 6233 => x"2a", + 6234 => x"42", + 6235 => x"64", + 6236 => x"20", + 6237 => x"0a", + 6238 => x"49", + 6239 => x"69", + 6240 => x"73", + 6241 => x"0a", + 6242 => x"46", + 6243 => x"65", + 6244 => x"6f", + 6245 => x"69", + 6246 => x"6c", + 6247 => x"2e", + 6248 => x"72", + 6249 => x"64", + 6250 => x"25", + 6251 => x"43", + 6252 => x"72", + 6253 => x"2e", + 6254 => x"43", + 6255 => x"69", + 6256 => x"2e", + 6257 => x"43", + 6258 => x"61", + 6259 => x"67", + 6260 => x"00", + 6261 => x"25", + 6262 => x"78", + 6263 => x"38", + 6264 => x"3e", + 6265 => x"6c", + 6266 => x"30", + 6267 => x"0a", + 6268 => x"44", + 6269 => x"20", + 6270 => x"6f", + 6271 => x"00", + 6272 => x"0a", + 6273 => x"70", + 6274 => x"65", + 6275 => x"25", + 6276 => x"20", + 6277 => x"58", + 6278 => x"3f", + 6279 => x"00", + 6280 => x"25", + 6281 => x"20", + 6282 => x"58", + 6283 => x"25", + 6284 => x"20", + 6285 => x"58", + 6286 => x"44", + 6287 => x"62", + 6288 => x"67", + 6289 => x"74", + 6290 => x"75", + 6291 => x"0a", + 6292 => x"45", + 6293 => x"6c", + 6294 => x"20", + 6295 => x"65", + 6296 => x"70", + 6297 => x"00", + 6298 => x"44", + 6299 => x"62", + 6300 => x"20", + 6301 => x"74", + 6302 => x"66", + 6303 => x"45", + 6304 => x"6c", + 6305 => x"20", + 6306 => x"74", + 6307 => x"66", + 6308 => x"45", + 6309 => x"75", + 6310 => x"67", + 6311 => x"64", + 6312 => x"20", + 6313 => x"78", + 6314 => x"2e", + 6315 => x"43", + 6316 => x"69", + 6317 => x"63", + 6318 => x"20", + 6319 => x"30", + 6320 => x"2e", + 6321 => x"00", + 6322 => x"43", + 6323 => x"20", + 6324 => x"75", + 6325 => x"64", + 6326 => x"64", + 6327 => x"25", + 6328 => x"0a", + 6329 => x"52", + 6330 => x"61", + 6331 => x"6e", + 6332 => x"70", + 6333 => x"63", + 6334 => x"6f", + 6335 => x"2e", + 6336 => x"43", + 6337 => x"20", + 6338 => x"6f", + 6339 => x"6e", + 6340 => x"2e", + 6341 => x"5a", + 6342 => x"62", + 6343 => x"25", + 6344 => x"25", + 6345 => x"73", + 6346 => x"00", + 6347 => x"42", + 6348 => x"63", + 6349 => x"61", + 6350 => x"0a", + 6351 => x"52", + 6352 => x"69", + 6353 => x"2e", + 6354 => x"45", + 6355 => x"6c", + 6356 => x"20", + 6357 => x"65", + 6358 => x"70", + 6359 => x"2e", + 6360 => x"00", + 6361 => x"00", + 6362 => x"00", + 6363 => x"00", + 6364 => x"00", + 6365 => x"00", + 6366 => x"00", + 6367 => x"00", + 6368 => x"00", + 6369 => x"00", + 6370 => x"00", + 6371 => x"05", + 6372 => x"00", + 6373 => x"01", + 6374 => x"80", + 6375 => x"01", + 6376 => x"00", + 6377 => x"01", + 6378 => x"00", + 6379 => x"01", + 6380 => x"00", + 6381 => x"00", + 6382 => x"00", + 6383 => x"01", + 6384 => x"00", + 6385 => x"00", + 6386 => x"00", + 6387 => x"01", + 6388 => x"00", + 6389 => x"00", + 6390 => x"00", + 6391 => x"01", + 6392 => x"00", + 6393 => x"00", + 6394 => x"00", + 6395 => x"01", + 6396 => x"00", + 6397 => x"00", + 6398 => x"00", + 6399 => x"01", + 6400 => x"00", + 6401 => x"00", + 6402 => x"00", + 6403 => x"01", + 6404 => x"00", + 6405 => x"00", + 6406 => x"00", + 6407 => x"01", + 6408 => x"00", + 6409 => x"00", + 6410 => x"00", + 6411 => x"01", + 6412 => x"00", + 6413 => x"00", + 6414 => x"00", + 6415 => x"01", + 6416 => x"00", + 6417 => x"00", + 6418 => x"00", + 6419 => x"01", + 6420 => x"00", + 6421 => x"00", + 6422 => x"00", + 6423 => x"01", + 6424 => x"00", + 6425 => x"00", + 6426 => x"00", + 6427 => x"01", + 6428 => x"00", + 6429 => x"00", + 6430 => x"00", + 6431 => x"01", + 6432 => x"00", + 6433 => x"00", + 6434 => x"00", + 6435 => x"01", + 6436 => x"00", + 6437 => x"00", + 6438 => x"00", + 6439 => x"01", + 6440 => x"00", + 6441 => x"00", + 6442 => x"00", + 6443 => x"01", + 6444 => x"00", + 6445 => x"00", + 6446 => x"00", + 6447 => x"01", + 6448 => x"00", + 6449 => x"00", + 6450 => x"00", + 6451 => x"01", + 6452 => x"00", + 6453 => x"00", + 6454 => x"00", + 6455 => x"01", + 6456 => x"00", + 6457 => x"00", + 6458 => x"00", + 6459 => x"01", + 6460 => x"00", + 6461 => x"00", + 6462 => x"00", + 6463 => x"01", + 6464 => x"00", + 6465 => x"00", + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; +end arch; diff --git a/zpu/devices/sysbus/BRAM/ZPUTA_SinglePortBootBRAM.vhd b/zpu/devices/sysbus/BRAM/ZPUTA_SinglePortBootBRAM.vhd new file mode 100644 index 0000000..70f8997 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/ZPUTA_SinglePortBootBRAM.vhd @@ -0,0 +1,28644 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity SinglePortBootBRAM is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end SinglePortBootBRAM; + +architecture arch of SinglePortBootBRAM is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + 0 => x"92", + 1 => x"00", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"80", + 10 => x"0c", + 11 => x"0c", + 12 => x"00", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"08", + 17 => x"09", + 18 => x"05", + 19 => x"83", + 20 => x"52", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"08", + 25 => x"73", + 26 => x"81", + 27 => x"83", + 28 => x"06", + 29 => x"ff", + 30 => x"0b", + 31 => x"00", + 32 => x"05", + 33 => x"73", + 34 => x"06", + 35 => x"06", + 36 => x"06", + 37 => x"00", + 38 => x"00", + 39 => x"00", + 40 => x"73", + 41 => x"53", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"09", + 49 => x"06", + 50 => x"72", + 51 => x"72", + 52 => x"31", + 53 => x"06", + 54 => x"51", + 55 => x"00", + 56 => x"73", + 57 => x"53", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"92", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"2b", + 81 => x"04", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"06", + 89 => x"0b", + 90 => x"9f", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"ff", + 97 => x"2a", + 98 => x"0a", + 99 => x"05", + 100 => x"51", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"51", + 105 => x"83", + 106 => x"05", + 107 => x"2b", + 108 => x"72", + 109 => x"51", + 110 => x"00", + 111 => x"00", + 112 => x"05", + 113 => x"70", + 114 => x"06", + 115 => x"53", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"05", + 121 => x"70", + 122 => x"06", + 123 => x"06", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"05", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"81", + 137 => x"51", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"06", + 145 => x"06", + 146 => x"04", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"08", + 153 => x"09", + 154 => x"05", + 155 => x"2a", + 156 => x"52", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"08", + 161 => x"c5", + 162 => x"06", + 163 => x"08", + 164 => x"0b", + 165 => x"00", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"75", + 170 => x"93", + 171 => x"50", + 172 => x"90", + 173 => x"88", + 174 => x"00", + 175 => x"00", + 176 => x"08", + 177 => x"75", + 178 => x"95", + 179 => x"50", + 180 => x"90", + 181 => x"88", + 182 => x"00", + 183 => x"00", + 184 => x"81", + 185 => x"0a", + 186 => x"05", + 187 => x"06", + 188 => x"74", + 189 => x"06", + 190 => x"51", + 191 => x"00", + 192 => x"81", + 193 => x"0a", + 194 => x"ff", + 195 => x"71", + 196 => x"72", + 197 => x"05", + 198 => x"51", + 199 => x"00", + 200 => x"04", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"52", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"72", + 233 => x"52", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"ff", + 249 => x"51", + 250 => x"ff", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"00", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"8c", + 265 => x"0b", + 266 => x"04", + 267 => x"8c", + 268 => x"0b", + 269 => x"04", + 270 => x"8c", + 271 => x"0b", + 272 => x"04", + 273 => x"8c", + 274 => x"0b", + 275 => x"04", + 276 => x"8c", + 277 => x"0b", + 278 => x"04", + 279 => x"8d", + 280 => x"0b", + 281 => x"04", + 282 => x"8d", + 283 => x"0b", + 284 => x"04", + 285 => x"8d", + 286 => x"0b", + 287 => x"04", + 288 => x"8d", + 289 => x"0b", + 290 => x"04", + 291 => x"8e", + 292 => x"0b", + 293 => x"04", + 294 => x"8e", + 295 => x"0b", + 296 => x"04", + 297 => x"8e", + 298 => x"0b", + 299 => x"04", + 300 => x"8e", + 301 => x"0b", + 302 => x"04", + 303 => x"8f", + 304 => x"0b", + 305 => x"04", + 306 => x"8f", + 307 => x"0b", + 308 => x"04", + 309 => x"8f", + 310 => x"0b", + 311 => x"04", + 312 => x"8f", + 313 => x"0b", + 314 => x"04", + 315 => x"90", + 316 => x"0b", + 317 => x"04", + 318 => x"90", + 319 => x"0b", + 320 => x"04", + 321 => x"90", + 322 => x"0b", + 323 => x"04", + 324 => x"90", + 325 => x"0b", + 326 => x"04", + 327 => x"91", + 328 => x"0b", + 329 => x"04", + 330 => x"91", + 331 => x"0b", + 332 => x"04", + 333 => x"91", + 334 => x"0b", + 335 => x"04", + 336 => x"91", + 337 => x"0b", + 338 => x"04", + 339 => x"ff", + 340 => x"ff", + 341 => x"ff", + 342 => x"ff", + 343 => x"ff", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"81", + 385 => x"cc", + 386 => x"2d", + 387 => x"08", + 388 => x"04", + 389 => x"0c", + 390 => x"81", + 391 => x"84", + 392 => x"81", + 393 => x"ae", + 394 => x"de", + 395 => x"80", + 396 => x"de", + 397 => x"bf", + 398 => x"cc", + 399 => x"90", + 400 => x"cc", + 401 => x"2d", + 402 => x"08", + 403 => x"04", + 404 => x"0c", + 405 => x"81", + 406 => x"84", + 407 => x"81", + 408 => x"ae", + 409 => x"de", + 410 => x"80", + 411 => x"de", + 412 => x"98", + 413 => x"cc", + 414 => x"90", + 415 => x"cc", + 416 => x"2d", + 417 => x"08", + 418 => x"04", + 419 => x"0c", + 420 => x"81", + 421 => x"84", + 422 => x"81", + 423 => x"b4", + 424 => x"de", + 425 => x"80", + 426 => x"de", + 427 => x"dd", + 428 => x"cc", + 429 => x"90", + 430 => x"cc", + 431 => x"2d", + 432 => x"08", + 433 => x"04", + 434 => x"0c", + 435 => x"81", + 436 => x"84", + 437 => x"81", + 438 => x"9b", + 439 => x"de", + 440 => x"80", + 441 => x"de", + 442 => x"dd", + 443 => x"cc", + 444 => x"90", + 445 => x"cc", + 446 => x"2d", + 447 => x"08", + 448 => x"04", + 449 => x"0c", + 450 => x"2d", + 451 => x"08", + 452 => x"04", + 453 => x"0c", + 454 => x"2d", + 455 => x"08", + 456 => x"04", + 457 => x"0c", + 458 => x"2d", + 459 => x"08", + 460 => x"04", + 461 => x"0c", + 462 => x"2d", + 463 => x"08", + 464 => x"04", + 465 => x"0c", + 466 => x"2d", + 467 => x"08", + 468 => x"04", + 469 => x"0c", + 470 => x"2d", + 471 => x"08", + 472 => x"04", + 473 => x"0c", + 474 => x"2d", + 475 => x"08", + 476 => x"04", + 477 => x"0c", + 478 => x"2d", + 479 => x"08", + 480 => x"04", + 481 => x"0c", + 482 => x"2d", + 483 => x"08", + 484 => x"04", + 485 => x"0c", + 486 => x"2d", + 487 => x"08", + 488 => x"04", + 489 => x"0c", + 490 => x"2d", + 491 => x"08", + 492 => x"04", + 493 => x"0c", + 494 => x"2d", + 495 => x"08", + 496 => x"04", + 497 => x"0c", + 498 => x"2d", + 499 => x"08", + 500 => x"04", + 501 => x"0c", + 502 => x"2d", + 503 => x"08", + 504 => x"04", + 505 => x"0c", + 506 => x"2d", + 507 => x"08", + 508 => x"04", + 509 => x"0c", + 510 => x"2d", + 511 => x"08", + 512 => x"04", + 513 => x"0c", + 514 => x"2d", + 515 => x"08", + 516 => x"04", + 517 => x"0c", + 518 => x"2d", + 519 => x"08", + 520 => x"04", + 521 => x"0c", + 522 => x"2d", + 523 => x"08", + 524 => x"04", + 525 => x"0c", + 526 => x"2d", + 527 => x"08", + 528 => x"04", + 529 => x"0c", + 530 => x"2d", + 531 => x"08", + 532 => x"04", + 533 => x"0c", + 534 => x"2d", + 535 => x"08", + 536 => x"04", + 537 => x"0c", + 538 => x"2d", + 539 => x"08", + 540 => x"04", + 541 => x"0c", + 542 => x"2d", + 543 => x"08", + 544 => x"04", + 545 => x"0c", + 546 => x"2d", + 547 => x"08", + 548 => x"04", + 549 => x"0c", + 550 => x"81", + 551 => x"84", + 552 => x"81", + 553 => x"bd", + 554 => x"de", + 555 => x"80", + 556 => x"de", + 557 => x"e7", + 558 => x"cc", + 559 => x"90", + 560 => x"cc", + 561 => x"2d", + 562 => x"08", + 563 => x"04", + 564 => x"0c", + 565 => x"81", + 566 => x"84", + 567 => x"81", + 568 => x"9f", + 569 => x"de", + 570 => x"80", + 571 => x"de", + 572 => x"a5", + 573 => x"de", + 574 => x"80", + 575 => x"04", + 576 => x"10", + 577 => x"10", + 578 => x"10", + 579 => x"10", + 580 => x"10", + 581 => x"10", + 582 => x"10", + 583 => x"53", + 584 => x"00", + 585 => x"06", + 586 => x"09", + 587 => x"05", + 588 => x"2b", + 589 => x"06", + 590 => x"04", + 591 => x"72", + 592 => x"05", + 593 => x"05", + 594 => x"72", + 595 => x"53", + 596 => x"51", + 597 => x"04", + 598 => x"70", + 599 => x"27", + 600 => x"71", + 601 => x"53", + 602 => x"0b", + 603 => x"8c", + 604 => x"c4", + 605 => x"81", + 606 => x"02", + 607 => x"0c", + 608 => x"80", + 609 => x"cc", + 610 => x"08", + 611 => x"cc", + 612 => x"08", + 613 => x"3f", + 614 => x"08", + 615 => x"c0", + 616 => x"3d", + 617 => x"cc", + 618 => x"de", + 619 => x"81", + 620 => x"fd", + 621 => x"53", + 622 => x"08", + 623 => x"52", + 624 => x"08", + 625 => x"51", + 626 => x"81", + 627 => x"70", + 628 => x"0c", + 629 => x"0d", + 630 => x"0c", + 631 => x"cc", + 632 => x"de", + 633 => x"3d", + 634 => x"81", + 635 => x"fc", + 636 => x"de", + 637 => x"05", + 638 => x"b9", + 639 => x"cc", + 640 => x"08", + 641 => x"cc", + 642 => x"0c", + 643 => x"de", + 644 => x"05", + 645 => x"cc", + 646 => x"08", + 647 => x"0b", + 648 => x"08", + 649 => x"81", + 650 => x"f4", + 651 => x"de", + 652 => x"05", + 653 => x"cc", + 654 => x"08", + 655 => x"38", + 656 => x"08", + 657 => x"30", + 658 => x"08", + 659 => x"80", + 660 => x"cc", + 661 => x"0c", + 662 => x"08", + 663 => x"8a", + 664 => x"81", + 665 => x"f0", + 666 => x"de", + 667 => x"05", + 668 => x"cc", + 669 => x"0c", + 670 => x"de", + 671 => x"05", + 672 => x"de", + 673 => x"05", + 674 => x"df", + 675 => x"c0", + 676 => x"de", + 677 => x"05", + 678 => x"de", + 679 => x"05", + 680 => x"90", + 681 => x"cc", + 682 => x"08", + 683 => x"cc", + 684 => x"0c", + 685 => x"08", + 686 => x"70", + 687 => x"0c", + 688 => x"0d", + 689 => x"0c", + 690 => x"cc", + 691 => x"de", + 692 => x"3d", + 693 => x"81", + 694 => x"fc", + 695 => x"de", + 696 => x"05", + 697 => x"99", + 698 => x"cc", + 699 => x"08", + 700 => x"cc", + 701 => x"0c", + 702 => x"de", + 703 => x"05", + 704 => x"cc", + 705 => x"08", + 706 => x"38", + 707 => x"08", + 708 => x"30", + 709 => x"08", + 710 => x"81", + 711 => x"cc", + 712 => x"08", + 713 => x"cc", + 714 => x"08", + 715 => x"81", + 716 => x"70", + 717 => x"08", + 718 => x"54", + 719 => x"08", + 720 => x"80", + 721 => x"81", + 722 => x"f8", + 723 => x"81", + 724 => x"f8", + 725 => x"de", + 726 => x"05", + 727 => x"de", + 728 => x"87", + 729 => x"de", + 730 => x"81", + 731 => x"02", + 732 => x"0c", + 733 => x"81", + 734 => x"cc", + 735 => x"0c", + 736 => x"de", + 737 => x"05", + 738 => x"cc", + 739 => x"08", + 740 => x"08", + 741 => x"27", + 742 => x"de", + 743 => x"05", + 744 => x"ae", + 745 => x"81", + 746 => x"8c", + 747 => x"a2", + 748 => x"cc", + 749 => x"08", + 750 => x"cc", + 751 => x"0c", + 752 => x"08", + 753 => x"10", + 754 => x"08", + 755 => x"ff", + 756 => x"de", + 757 => x"05", + 758 => x"80", + 759 => x"de", + 760 => x"05", + 761 => x"cc", + 762 => x"08", + 763 => x"81", + 764 => x"88", + 765 => x"de", + 766 => x"05", + 767 => x"de", + 768 => x"05", + 769 => x"cc", + 770 => x"08", + 771 => x"08", + 772 => x"07", + 773 => x"08", + 774 => x"81", + 775 => x"fc", + 776 => x"2a", + 777 => x"08", + 778 => x"81", + 779 => x"8c", + 780 => x"2a", + 781 => x"08", + 782 => x"ff", + 783 => x"de", + 784 => x"05", + 785 => x"93", + 786 => x"cc", + 787 => x"08", + 788 => x"cc", + 789 => x"0c", + 790 => x"81", + 791 => x"f8", + 792 => x"81", + 793 => x"f4", + 794 => x"81", + 795 => x"f4", + 796 => x"de", + 797 => x"3d", + 798 => x"cc", + 799 => x"3d", + 800 => x"71", + 801 => x"9f", + 802 => x"55", + 803 => x"72", + 804 => x"74", + 805 => x"70", + 806 => x"38", + 807 => x"71", + 808 => x"38", + 809 => x"81", + 810 => x"ff", + 811 => x"ff", + 812 => x"06", + 813 => x"81", + 814 => x"86", + 815 => x"74", + 816 => x"75", + 817 => x"90", + 818 => x"54", + 819 => x"27", + 820 => x"71", + 821 => x"53", + 822 => x"70", + 823 => x"0c", + 824 => x"84", + 825 => x"72", + 826 => x"05", + 827 => x"12", + 828 => x"26", + 829 => x"72", + 830 => x"72", + 831 => x"05", + 832 => x"12", + 833 => x"26", + 834 => x"53", + 835 => x"fb", + 836 => x"79", + 837 => x"83", + 838 => x"52", + 839 => x"71", + 840 => x"54", + 841 => x"73", + 842 => x"c6", + 843 => x"54", + 844 => x"70", + 845 => x"52", + 846 => x"2e", + 847 => x"33", + 848 => x"2e", + 849 => x"95", + 850 => x"81", + 851 => x"70", + 852 => x"54", + 853 => x"70", + 854 => x"33", + 855 => x"ff", + 856 => x"ff", + 857 => x"31", + 858 => x"0c", + 859 => x"3d", + 860 => x"09", + 861 => x"fd", + 862 => x"70", + 863 => x"81", + 864 => x"51", + 865 => x"38", + 866 => x"16", + 867 => x"56", + 868 => x"08", + 869 => x"73", + 870 => x"ff", + 871 => x"0b", + 872 => x"0c", + 873 => x"04", + 874 => x"80", + 875 => x"71", + 876 => x"87", + 877 => x"de", + 878 => x"ff", + 879 => x"ff", + 880 => x"72", + 881 => x"38", + 882 => x"c0", + 883 => x"0d", + 884 => x"0d", + 885 => x"70", + 886 => x"71", + 887 => x"ca", + 888 => x"51", + 889 => x"09", + 890 => x"38", + 891 => x"f1", + 892 => x"84", + 893 => x"53", + 894 => x"70", + 895 => x"53", + 896 => x"a0", + 897 => x"81", + 898 => x"2e", + 899 => x"e5", + 900 => x"ff", + 901 => x"a0", + 902 => x"06", + 903 => x"73", + 904 => x"55", + 905 => x"0c", + 906 => x"81", + 907 => x"87", + 908 => x"fc", + 909 => x"53", + 910 => x"2e", + 911 => x"3d", + 912 => x"72", + 913 => x"3f", + 914 => x"08", + 915 => x"53", + 916 => x"53", + 917 => x"c0", + 918 => x"0d", + 919 => x"0d", + 920 => x"33", + 921 => x"53", + 922 => x"8b", + 923 => x"38", + 924 => x"ff", + 925 => x"52", + 926 => x"81", + 927 => x"13", + 928 => x"52", + 929 => x"80", + 930 => x"13", + 931 => x"52", + 932 => x"80", + 933 => x"13", + 934 => x"52", + 935 => x"80", + 936 => x"13", + 937 => x"52", + 938 => x"26", + 939 => x"8a", + 940 => x"87", + 941 => x"e7", + 942 => x"38", + 943 => x"c0", + 944 => x"72", + 945 => x"98", + 946 => x"13", + 947 => x"98", + 948 => x"13", + 949 => x"98", + 950 => x"13", + 951 => x"98", + 952 => x"13", + 953 => x"98", + 954 => x"13", + 955 => x"98", + 956 => x"87", + 957 => x"0c", + 958 => x"98", + 959 => x"0b", + 960 => x"9c", + 961 => x"71", + 962 => x"0c", + 963 => x"04", + 964 => x"7f", + 965 => x"98", + 966 => x"7d", + 967 => x"98", + 968 => x"7d", + 969 => x"c0", + 970 => x"5a", + 971 => x"34", + 972 => x"b4", + 973 => x"83", + 974 => x"c0", + 975 => x"5a", + 976 => x"34", + 977 => x"ac", + 978 => x"85", + 979 => x"c0", + 980 => x"5a", + 981 => x"34", + 982 => x"a4", + 983 => x"88", + 984 => x"c0", + 985 => x"5a", + 986 => x"23", + 987 => x"79", + 988 => x"06", + 989 => x"ff", + 990 => x"86", + 991 => x"85", + 992 => x"84", + 993 => x"83", + 994 => x"82", + 995 => x"7d", + 996 => x"06", + 997 => x"e4", + 998 => x"3f", + 999 => x"04", + 1000 => x"02", + 1001 => x"70", + 1002 => x"2a", + 1003 => x"70", + 1004 => x"db", + 1005 => x"3d", + 1006 => x"3d", + 1007 => x"0b", + 1008 => x"33", + 1009 => x"06", + 1010 => x"87", + 1011 => x"51", + 1012 => x"86", + 1013 => x"94", + 1014 => x"08", + 1015 => x"70", + 1016 => x"54", + 1017 => x"2e", + 1018 => x"91", + 1019 => x"06", + 1020 => x"d7", + 1021 => x"32", + 1022 => x"51", + 1023 => x"2e", + 1024 => x"93", + 1025 => x"06", + 1026 => x"ff", + 1027 => x"81", + 1028 => x"87", + 1029 => x"52", + 1030 => x"86", + 1031 => x"94", + 1032 => x"72", + 1033 => x"de", + 1034 => x"3d", + 1035 => x"3d", + 1036 => x"05", + 1037 => x"81", + 1038 => x"70", + 1039 => x"57", + 1040 => x"c0", + 1041 => x"74", + 1042 => x"38", + 1043 => x"94", + 1044 => x"70", + 1045 => x"81", + 1046 => x"52", + 1047 => x"8c", + 1048 => x"2a", + 1049 => x"51", + 1050 => x"38", + 1051 => x"70", + 1052 => x"51", + 1053 => x"8d", + 1054 => x"2a", + 1055 => x"51", + 1056 => x"be", + 1057 => x"ff", + 1058 => x"c0", + 1059 => x"70", + 1060 => x"38", + 1061 => x"90", + 1062 => x"0c", + 1063 => x"04", + 1064 => x"79", + 1065 => x"33", + 1066 => x"06", + 1067 => x"70", + 1068 => x"fe", + 1069 => x"ff", + 1070 => x"0b", + 1071 => x"88", + 1072 => x"ff", + 1073 => x"55", + 1074 => x"94", + 1075 => x"80", + 1076 => x"87", + 1077 => x"51", + 1078 => x"96", + 1079 => x"06", + 1080 => x"70", + 1081 => x"38", + 1082 => x"70", + 1083 => x"51", + 1084 => x"72", + 1085 => x"81", + 1086 => x"70", + 1087 => x"38", + 1088 => x"70", + 1089 => x"51", + 1090 => x"38", + 1091 => x"06", + 1092 => x"94", + 1093 => x"80", + 1094 => x"87", + 1095 => x"52", + 1096 => x"81", + 1097 => x"70", + 1098 => x"53", + 1099 => x"ff", + 1100 => x"81", + 1101 => x"89", + 1102 => x"fe", + 1103 => x"0b", + 1104 => x"33", + 1105 => x"06", + 1106 => x"c0", + 1107 => x"72", + 1108 => x"38", + 1109 => x"94", + 1110 => x"70", + 1111 => x"81", + 1112 => x"51", + 1113 => x"e2", + 1114 => x"ff", + 1115 => x"c0", + 1116 => x"70", + 1117 => x"38", + 1118 => x"90", + 1119 => x"70", + 1120 => x"81", + 1121 => x"51", + 1122 => x"04", + 1123 => x"0b", + 1124 => x"88", + 1125 => x"ff", + 1126 => x"87", + 1127 => x"52", + 1128 => x"86", + 1129 => x"94", + 1130 => x"08", + 1131 => x"70", + 1132 => x"51", + 1133 => x"70", + 1134 => x"38", + 1135 => x"06", + 1136 => x"94", + 1137 => x"80", + 1138 => x"87", + 1139 => x"52", + 1140 => x"98", + 1141 => x"2c", + 1142 => x"71", + 1143 => x"0c", + 1144 => x"04", + 1145 => x"87", + 1146 => x"08", + 1147 => x"8a", + 1148 => x"70", + 1149 => x"b4", + 1150 => x"9e", + 1151 => x"db", + 1152 => x"c0", + 1153 => x"81", + 1154 => x"87", + 1155 => x"08", + 1156 => x"0c", + 1157 => x"98", + 1158 => x"98", + 1159 => x"9e", + 1160 => x"db", + 1161 => x"c0", + 1162 => x"81", + 1163 => x"87", + 1164 => x"08", + 1165 => x"0c", + 1166 => x"b0", + 1167 => x"a8", + 1168 => x"9e", + 1169 => x"db", + 1170 => x"c0", + 1171 => x"81", + 1172 => x"87", + 1173 => x"08", + 1174 => x"0c", + 1175 => x"c0", + 1176 => x"b8", + 1177 => x"9e", + 1178 => x"db", + 1179 => x"c0", + 1180 => x"51", + 1181 => x"c0", + 1182 => x"9e", + 1183 => x"db", + 1184 => x"c0", + 1185 => x"81", + 1186 => x"87", + 1187 => x"08", + 1188 => x"0c", + 1189 => x"db", + 1190 => x"0b", + 1191 => x"90", + 1192 => x"80", + 1193 => x"52", + 1194 => x"2e", + 1195 => x"52", + 1196 => x"d1", + 1197 => x"87", + 1198 => x"08", + 1199 => x"0a", + 1200 => x"52", + 1201 => x"83", + 1202 => x"71", + 1203 => x"34", + 1204 => x"c0", + 1205 => x"70", + 1206 => x"06", + 1207 => x"70", + 1208 => x"38", + 1209 => x"81", + 1210 => x"80", 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x"0b", + 1270 => x"90", + 1271 => x"80", + 1272 => x"52", + 1273 => x"83", + 1274 => x"71", + 1275 => x"34", + 1276 => x"90", + 1277 => x"f0", + 1278 => x"2a", + 1279 => x"70", + 1280 => x"34", + 1281 => x"c0", + 1282 => x"70", + 1283 => x"52", + 1284 => x"2e", + 1285 => x"52", + 1286 => x"df", + 1287 => x"9e", + 1288 => x"87", + 1289 => x"70", + 1290 => x"34", + 1291 => x"04", + 1292 => x"81", + 1293 => x"86", + 1294 => x"db", + 1295 => x"73", + 1296 => x"38", + 1297 => x"51", + 1298 => x"81", + 1299 => x"85", + 1300 => x"db", + 1301 => x"73", + 1302 => x"38", + 1303 => x"08", + 1304 => x"08", + 1305 => x"81", + 1306 => x"8b", + 1307 => x"db", + 1308 => x"73", + 1309 => x"38", + 1310 => x"08", + 1311 => x"08", + 1312 => x"81", + 1313 => x"8b", + 1314 => x"db", + 1315 => x"73", + 1316 => x"38", + 1317 => x"08", + 1318 => x"08", + 1319 => x"81", + 1320 => x"8a", + 1321 => x"db", + 1322 => x"73", + 1323 => x"38", + 1324 => x"08", + 1325 => x"08", + 1326 => x"81", + 1327 => x"8a", + 1328 => x"db", + 1329 => x"73", + 1330 => x"38", + 1331 => x"08", + 1332 => x"08", + 1333 => x"81", + 1334 => x"8a", + 1335 => x"db", + 1336 => x"73", + 1337 => x"38", + 1338 => x"33", + 1339 => x"c8", + 1340 => x"3f", + 1341 => x"33", + 1342 => x"2e", + 1343 => x"db", + 1344 => x"81", + 1345 => x"8a", + 1346 => x"db", + 1347 => x"73", + 1348 => x"38", + 1349 => x"33", + 1350 => x"88", + 1351 => x"3f", + 1352 => x"33", + 1353 => x"2e", + 1354 => x"c9", + 1355 => x"8f", + 1356 => x"d3", + 1357 => x"80", + 1358 => x"81", + 1359 => x"83", + 1360 => x"db", + 1361 => x"73", + 1362 => x"38", + 1363 => x"51", + 1364 => x"81", + 1365 => x"54", + 1366 => x"88", + 1367 => x"d4", + 1368 => x"3f", + 1369 => x"33", + 1370 => x"2e", + 1371 => x"c9", + 1372 => x"cb", + 1373 => x"ec", + 1374 => x"3f", + 1375 => x"08", + 1376 => x"f8", + 1377 => x"3f", + 1378 => x"08", + 1379 => x"a0", + 1380 => x"3f", + 1381 => x"08", + 1382 => x"c8", + 1383 => x"3f", + 1384 => x"51", + 1385 => x"81", + 1386 => x"52", + 1387 => x"51", + 1388 => x"81", + 1389 => x"56", + 1390 => x"52", + 1391 => x"b7", + 1392 => x"c0", + 1393 => x"c0", + 1394 => x"31", + 1395 => x"de", + 1396 => x"81", + 1397 => x"88", + 1398 => x"db", + 1399 => x"73", + 1400 => x"38", + 1401 => x"08", + 1402 => x"c0", + 1403 => x"e7", + 1404 => x"de", + 1405 => x"84", + 1406 => x"71", + 1407 => x"81", + 1408 => x"52", + 1409 => x"51", + 1410 => x"81", + 1411 => x"54", + 1412 => x"a8", + 1413 => x"cc", + 1414 => x"84", + 1415 => x"51", + 1416 => x"81", + 1417 => x"bd", + 1418 => x"76", + 1419 => x"54", + 1420 => x"08", + 1421 => x"f8", + 1422 => x"3f", + 1423 => x"51", + 1424 => x"87", + 1425 => x"fe", + 1426 => x"92", + 1427 => x"05", + 1428 => x"26", + 1429 => x"84", + 1430 => x"80", + 1431 => x"08", + 1432 => x"a4", + 1433 => x"81", + 1434 => x"97", + 1435 => x"b4", + 1436 => x"81", + 1437 => x"8b", + 1438 => x"c0", + 1439 => x"81", + 1440 => x"f4", + 1441 => x"3d", + 1442 => x"88", + 1443 => x"80", + 1444 => x"96", + 1445 => x"ff", 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x"81", + 1505 => x"da", + 1506 => x"74", + 1507 => x"0c", + 1508 => x"04", + 1509 => x"66", + 1510 => x"78", + 1511 => x"5a", + 1512 => x"80", + 1513 => x"38", + 1514 => x"09", + 1515 => x"de", + 1516 => x"7a", + 1517 => x"5c", + 1518 => x"5b", + 1519 => x"09", + 1520 => x"38", + 1521 => x"39", + 1522 => x"09", + 1523 => x"38", + 1524 => x"70", + 1525 => x"33", + 1526 => x"2e", + 1527 => x"92", + 1528 => x"19", + 1529 => x"70", + 1530 => x"33", + 1531 => x"53", + 1532 => x"16", + 1533 => x"26", + 1534 => x"88", + 1535 => x"05", + 1536 => x"05", + 1537 => x"05", + 1538 => x"5b", + 1539 => x"80", + 1540 => x"30", + 1541 => x"80", + 1542 => x"cc", + 1543 => x"70", + 1544 => x"25", + 1545 => x"54", + 1546 => x"53", + 1547 => x"8c", + 1548 => x"07", + 1549 => x"05", + 1550 => x"5a", + 1551 => x"83", + 1552 => x"54", + 1553 => x"27", + 1554 => x"16", + 1555 => x"06", + 1556 => x"80", + 1557 => x"aa", + 1558 => x"cf", + 1559 => x"73", + 1560 => x"81", + 1561 => x"80", + 1562 => x"38", + 1563 => x"2e", + 1564 => x"81", + 1565 => x"80", + 1566 => x"8a", + 1567 => x"39", + 1568 => x"2e", + 1569 => x"73", + 1570 => x"8a", + 1571 => x"d3", + 1572 => x"80", + 1573 => x"80", + 1574 => x"ee", + 1575 => x"39", + 1576 => x"71", + 1577 => x"53", + 1578 => x"54", + 1579 => x"2e", + 1580 => x"15", + 1581 => x"33", + 1582 => x"72", + 1583 => x"81", + 1584 => x"39", + 1585 => x"56", + 1586 => x"27", + 1587 => x"51", + 1588 => x"75", + 1589 => x"72", + 1590 => x"38", + 1591 => x"df", + 1592 => x"16", + 1593 => x"7b", + 1594 => x"38", + 1595 => x"f2", + 1596 => x"77", + 1597 => x"12", + 1598 => x"53", + 1599 => x"5c", + 1600 => x"5c", + 1601 => x"5c", + 1602 => x"5c", + 1603 => x"51", + 1604 => x"fd", + 1605 => x"82", + 1606 => x"06", + 1607 => x"80", + 1608 => x"77", + 1609 => x"53", + 1610 => x"18", + 1611 => x"72", + 1612 => x"c4", + 1613 => x"70", + 1614 => x"25", + 1615 => x"55", + 1616 => x"8d", + 1617 => x"2e", + 1618 => x"30", + 1619 => x"5b", + 1620 => x"8f", + 1621 => x"7b", + 1622 => x"e0", + 1623 => x"de", + 1624 => x"ff", + 1625 => x"75", + 1626 => x"8b", + 1627 => x"c0", + 1628 => x"74", + 1629 => x"a7", + 1630 => x"80", + 1631 => x"38", + 1632 => x"72", + 1633 => x"54", + 1634 => x"72", + 1635 => x"05", + 1636 => x"17", + 1637 => x"77", + 1638 => x"51", + 1639 => x"9f", + 1640 => x"72", + 1641 => x"79", + 1642 => x"81", + 1643 => x"72", + 1644 => x"38", + 1645 => x"05", + 1646 => x"ad", + 1647 => x"17", + 1648 => x"81", + 1649 => x"b0", + 1650 => x"38", + 1651 => x"81", + 1652 => x"06", + 1653 => x"9f", + 1654 => x"55", + 1655 => x"97", + 1656 => x"f9", + 1657 => x"81", + 1658 => x"8b", + 1659 => x"16", + 1660 => x"73", + 1661 => x"96", + 1662 => x"e0", + 1663 => x"17", + 1664 => x"33", + 1665 => x"f9", + 1666 => x"f2", + 1667 => x"16", + 1668 => x"7b", + 1669 => x"38", + 1670 => x"c6", + 1671 => x"96", + 1672 => x"fd", + 1673 => x"3d", + 1674 => x"05", + 1675 => x"52", + 1676 => x"e0", + 1677 => x"0d", + 1678 => x"0d", + 1679 => x"d8", + 1680 => x"88", + 1681 => x"51", + 1682 => x"81", + 1683 => x"53", + 1684 => x"80", + 1685 => x"d8", + 1686 => x"0d", + 1687 => x"0d", + 1688 => x"08", + 1689 => x"d0", + 1690 => x"88", + 1691 => x"52", + 1692 => x"3f", + 1693 => x"d0", + 1694 => x"0d", + 1695 => x"0d", + 1696 => x"de", + 1697 => x"56", + 1698 => x"80", + 1699 => x"2e", + 1700 => x"81", + 1701 => x"52", + 1702 => x"de", + 1703 => x"ff", + 1704 => x"80", + 1705 => x"38", + 1706 => x"b9", + 1707 => x"32", + 1708 => x"80", + 1709 => x"52", + 1710 => x"8b", + 1711 => x"2e", + 1712 => x"14", + 1713 => x"9f", + 1714 => x"38", + 1715 => x"73", + 1716 => x"38", + 1717 => x"72", + 1718 => x"14", + 1719 => x"f8", + 1720 => x"af", + 1721 => x"52", + 1722 => x"8a", + 1723 => x"3f", + 1724 => x"81", + 1725 => x"87", + 1726 => x"fe", + 1727 => x"de", + 1728 => x"81", + 1729 => x"77", + 1730 => x"53", + 1731 => x"72", + 1732 => x"0c", + 1733 => x"04", + 1734 => x"7a", + 1735 => x"80", + 1736 => x"58", + 1737 => x"33", + 1738 => x"a0", + 1739 => x"06", + 1740 => x"13", + 1741 => x"39", + 1742 => x"09", + 1743 => x"38", + 1744 => x"11", + 1745 => x"08", + 1746 => x"54", + 1747 => x"2e", + 1748 => x"80", + 1749 => x"08", + 1750 => x"0c", + 1751 => x"33", + 1752 => x"80", + 1753 => x"38", + 1754 => x"80", + 1755 => x"38", + 1756 => x"57", + 1757 => x"0c", + 1758 => x"33", + 1759 => x"39", + 1760 => x"74", + 1761 => x"38", + 1762 => x"80", + 1763 => x"89", + 1764 => x"38", + 1765 => x"d0", + 1766 => x"55", + 1767 => x"80", + 1768 => x"39", + 1769 => x"d9", + 1770 => x"80", + 1771 => x"27", + 1772 => x"80", + 1773 => x"89", + 1774 => x"70", + 1775 => x"55", + 1776 => x"70", + 1777 => x"55", + 1778 => x"27", + 1779 => x"14", + 1780 => x"06", + 1781 => x"74", + 1782 => x"73", + 1783 => x"38", + 1784 => x"14", + 1785 => x"05", + 1786 => x"08", + 1787 => x"54", + 1788 => x"39", + 1789 => x"84", + 1790 => x"55", + 1791 => x"81", + 1792 => x"de", + 1793 => x"3d", + 1794 => x"3d", + 1795 => x"5a", + 1796 => x"7a", + 1797 => x"08", + 1798 => x"53", + 1799 => x"09", + 1800 => x"38", + 1801 => x"0c", + 1802 => x"ad", + 1803 => x"06", + 1804 => x"76", + 1805 => x"0c", + 1806 => x"33", + 1807 => x"73", + 1808 => x"81", + 1809 => x"38", + 1810 => x"05", + 1811 => x"08", + 1812 => x"53", + 1813 => x"2e", + 1814 => x"57", + 1815 => x"2e", + 1816 => x"39", + 1817 => x"13", + 1818 => x"08", + 1819 => x"53", + 1820 => x"55", + 1821 => x"80", + 1822 => x"14", + 1823 => x"88", + 1824 => x"27", + 1825 => x"eb", + 1826 => x"53", + 1827 => x"89", + 1828 => x"38", + 1829 => x"55", + 1830 => x"8a", + 1831 => x"a0", + 1832 => x"c2", + 1833 => x"74", + 1834 => x"e0", + 1835 => x"ff", + 1836 => x"d0", + 1837 => x"ff", + 1838 => x"90", + 1839 => x"38", + 1840 => x"81", + 1841 => x"53", + 1842 => x"ca", + 1843 => x"27", + 1844 => x"77", + 1845 => x"08", + 1846 => x"0c", + 1847 => x"33", + 1848 => x"ff", + 1849 => x"80", + 1850 => x"74", + 1851 => x"79", + 1852 => x"74", + 1853 => x"0c", + 1854 => x"04", + 1855 => x"02", + 1856 => x"51", + 1857 => x"72", + 1858 => x"81", + 1859 => x"33", + 1860 => x"de", + 1861 => x"3d", + 1862 => x"3d", + 1863 => x"05", + 1864 => x"05", + 1865 => x"56", + 1866 => x"72", + 1867 => x"e0", + 1868 => x"2b", + 1869 => x"8c", + 1870 => x"88", + 1871 => x"2e", + 1872 => x"88", + 1873 => x"0c", + 1874 => x"8c", + 1875 => x"71", + 1876 => x"87", + 1877 => x"0c", + 1878 => x"08", + 1879 => x"51", + 1880 => x"2e", + 1881 => x"c0", + 1882 => x"51", + 1883 => x"71", + 1884 => x"80", + 1885 => x"92", + 1886 => x"98", + 1887 => x"70", + 1888 => x"38", + 1889 => x"e8", + 1890 => x"db", + 1891 => x"51", + 1892 => x"c0", + 1893 => x"0d", + 1894 => x"0d", + 1895 => x"02", + 1896 => x"05", + 1897 => x"58", + 1898 => x"52", + 1899 => x"3f", + 1900 => x"08", + 1901 => x"54", + 1902 => x"be", + 1903 => x"75", + 1904 => x"c0", + 1905 => x"87", + 1906 => x"12", + 1907 => x"84", + 1908 => x"40", + 1909 => x"85", + 1910 => x"98", + 1911 => x"7d", + 1912 => x"0c", + 1913 => x"85", + 1914 => x"06", + 1915 => x"71", + 1916 => x"38", + 1917 => x"71", + 1918 => x"05", + 1919 => x"19", + 1920 => x"a2", + 1921 => x"71", + 1922 => x"38", + 1923 => x"83", + 1924 => x"38", + 1925 => x"8a", + 1926 => x"98", + 1927 => x"71", + 1928 => x"c0", + 1929 => x"52", + 1930 => x"87", + 1931 => x"80", + 1932 => x"81", + 1933 => x"c0", + 1934 => x"53", + 1935 => x"82", + 1936 => x"71", + 1937 => x"1a", + 1938 => x"84", + 1939 => x"19", + 1940 => x"06", + 1941 => x"79", + 1942 => x"38", + 1943 => x"80", + 1944 => x"87", + 1945 => x"26", + 1946 => x"73", + 1947 => x"06", + 1948 => x"2e", + 1949 => x"52", + 1950 => x"81", + 1951 => x"8f", + 1952 => x"f3", + 1953 => x"62", + 1954 => x"05", + 1955 => x"57", + 1956 => x"83", + 1957 => x"52", + 1958 => x"3f", + 1959 => x"08", + 1960 => x"54", + 1961 => x"2e", + 1962 => x"81", + 1963 => x"74", + 1964 => x"c0", + 1965 => x"87", + 1966 => x"12", + 1967 => x"84", + 1968 => x"5f", + 1969 => x"0b", + 1970 => x"8c", + 1971 => x"0c", + 1972 => x"80", + 1973 => x"70", + 1974 => x"81", + 1975 => x"54", + 1976 => x"8c", + 1977 => x"81", + 1978 => x"7c", + 1979 => x"58", + 1980 => x"70", + 1981 => x"52", + 1982 => x"8a", + 1983 => x"98", + 1984 => x"71", + 1985 => x"c0", + 1986 => x"52", + 1987 => x"87", + 1988 => x"80", + 1989 => x"81", + 1990 => x"c0", + 1991 => x"53", + 1992 => x"82", + 1993 => x"71", + 1994 => x"19", + 1995 => x"81", + 1996 => x"ff", + 1997 => x"19", + 1998 => x"78", + 1999 => x"38", + 2000 => x"80", + 2001 => x"87", + 2002 => x"26", + 2003 => x"73", + 2004 => x"06", + 2005 => x"2e", + 2006 => x"52", + 2007 => x"81", + 2008 => x"8f", + 2009 => x"f6", + 2010 => x"02", + 2011 => x"05", + 2012 => x"05", + 2013 => x"71", + 2014 => x"57", + 2015 => x"81", + 2016 => x"81", + 2017 => x"54", + 2018 => x"38", + 2019 => x"c0", + 2020 => x"81", + 2021 => x"2e", + 2022 => x"71", + 2023 => x"38", + 2024 => x"87", + 2025 => x"11", + 2026 => x"80", + 2027 => x"80", + 2028 => x"83", + 2029 => x"38", + 2030 => x"72", + 2031 => x"2a", + 2032 => x"51", + 2033 => x"80", + 2034 => x"87", + 2035 => x"08", + 2036 => x"38", + 2037 => x"8c", + 2038 => x"96", + 2039 => x"0c", + 2040 => x"8c", + 2041 => x"08", + 2042 => x"51", + 2043 => x"38", + 2044 => x"56", + 2045 => x"80", + 2046 => x"85", + 2047 => x"77", + 2048 => x"83", + 2049 => x"75", + 2050 => x"de", + 2051 => x"3d", + 2052 => x"3d", + 2053 => x"11", + 2054 => x"71", + 2055 => x"81", + 2056 => x"53", + 2057 => x"0d", + 2058 => x"0d", + 2059 => x"33", + 2060 => x"71", + 2061 => x"88", + 2062 => x"14", + 2063 => x"07", + 2064 => x"33", + 2065 => x"de", + 2066 => x"53", + 2067 => x"52", + 2068 => x"04", + 2069 => x"73", + 2070 => x"92", + 2071 => x"52", + 2072 => x"81", + 2073 => x"70", + 2074 => x"70", + 2075 => x"3d", + 2076 => x"3d", + 2077 => x"52", + 2078 => x"70", + 2079 => x"34", + 2080 => x"51", + 2081 => x"81", + 2082 => x"70", + 2083 => x"70", + 2084 => x"05", + 2085 => x"88", + 2086 => x"72", + 2087 => x"0d", + 2088 => x"0d", + 2089 => x"54", + 2090 => x"80", + 2091 => x"71", + 2092 => x"53", + 2093 => x"81", + 2094 => x"ff", + 2095 => x"39", + 2096 => x"04", + 2097 => x"75", + 2098 => x"52", + 2099 => x"70", + 2100 => x"34", + 2101 => x"70", + 2102 => x"3d", + 2103 => x"3d", + 2104 => x"79", + 2105 => x"74", + 2106 => x"56", + 2107 => x"81", + 2108 => x"71", + 2109 => x"16", + 2110 => x"52", + 2111 => x"86", + 2112 => x"2e", + 2113 => x"81", + 2114 => x"86", + 2115 => x"fe", + 2116 => x"76", + 2117 => x"39", + 2118 => x"8a", + 2119 => x"51", + 2120 => x"71", + 2121 => x"33", + 2122 => x"0c", + 2123 => x"04", + 2124 => x"de", + 2125 => x"80", + 2126 => x"c0", + 2127 => x"3d", + 2128 => x"80", + 2129 => x"33", + 2130 => x"7a", + 2131 => x"38", + 2132 => x"16", + 2133 => x"16", + 2134 => x"17", + 2135 => x"fa", + 2136 => x"de", + 2137 => x"2e", + 2138 => x"b7", + 2139 => x"c0", + 2140 => x"34", + 2141 => x"70", + 2142 => x"31", + 2143 => x"59", + 2144 => x"77", + 2145 => x"82", + 2146 => x"74", + 2147 => x"81", + 2148 => x"81", + 2149 => x"53", + 2150 => x"16", + 2151 => x"e3", + 2152 => x"81", + 2153 => x"de", + 2154 => x"3d", + 2155 => x"3d", + 2156 => x"56", + 2157 => x"74", + 2158 => x"2e", + 2159 => x"51", + 2160 => x"81", + 2161 => x"57", + 2162 => x"08", + 2163 => x"54", + 2164 => x"16", + 2165 => x"33", + 2166 => x"3f", + 2167 => x"08", + 2168 => x"38", + 2169 => x"57", + 2170 => x"0c", + 2171 => x"c0", + 2172 => x"0d", + 2173 => x"0d", + 2174 => x"57", + 2175 => x"81", + 2176 => x"58", + 2177 => x"08", + 2178 => x"76", + 2179 => x"83", + 2180 => x"06", + 2181 => x"84", + 2182 => x"78", + 2183 => x"81", + 2184 => x"38", + 2185 => x"81", + 2186 => x"52", + 2187 => x"52", + 2188 => x"3f", + 2189 => x"52", + 2190 => x"51", + 2191 => x"84", + 2192 => x"d2", + 2193 => x"fc", + 2194 => x"8a", + 2195 => x"52", + 2196 => x"51", + 2197 => x"90", + 2198 => x"84", + 2199 => x"fc", + 2200 => x"17", + 2201 => x"a0", + 2202 => x"86", + 2203 => x"08", + 2204 => x"b0", + 2205 => x"55", + 2206 => x"81", + 2207 => x"f8", + 2208 => x"84", + 2209 => x"53", + 2210 => x"17", + 2211 => x"d7", + 2212 => x"c0", + 2213 => x"83", + 2214 => x"77", + 2215 => x"0c", + 2216 => x"04", + 2217 => x"77", + 2218 => x"12", + 2219 => x"55", + 2220 => x"56", + 2221 => x"8d", + 2222 => x"22", + 2223 => x"ac", + 2224 => x"57", + 2225 => x"de", + 2226 => x"3d", + 2227 => x"3d", + 2228 => x"70", + 2229 => x"57", + 2230 => x"81", + 2231 => x"98", + 2232 => x"81", + 2233 => x"74", + 2234 => x"72", + 2235 => x"f5", + 2236 => x"24", + 2237 => x"81", + 2238 => x"81", + 2239 => x"83", + 2240 => x"38", + 2241 => x"76", + 2242 => x"70", + 2243 => x"16", + 2244 => x"74", + 2245 => x"96", + 2246 => x"c0", + 2247 => x"38", + 2248 => x"06", + 2249 => x"33", + 2250 => x"89", + 2251 => x"08", + 2252 => x"54", + 2253 => x"fc", + 2254 => x"de", + 2255 => x"fe", + 2256 => x"ff", + 2257 => x"11", + 2258 => x"2b", + 2259 => x"81", + 2260 => x"2a", + 2261 => x"51", + 2262 => x"e2", + 2263 => x"ff", + 2264 => x"da", + 2265 => x"2a", + 2266 => x"05", + 2267 => x"fc", + 2268 => x"de", + 2269 => x"c6", + 2270 => x"83", + 2271 => x"05", + 2272 => x"f9", + 2273 => x"de", + 2274 => x"ff", + 2275 => x"ae", + 2276 => x"2a", + 2277 => x"05", + 2278 => x"fc", + 2279 => x"de", + 2280 => x"38", + 2281 => x"83", + 2282 => x"05", + 2283 => x"f8", + 2284 => x"de", + 2285 => x"0a", + 2286 => x"39", + 2287 => x"81", + 2288 => x"89", + 2289 => x"f8", + 2290 => x"7c", + 2291 => x"56", + 2292 => x"77", + 2293 => x"38", + 2294 => x"08", + 2295 => x"38", + 2296 => x"72", + 2297 => x"9d", + 2298 => x"24", + 2299 => x"81", + 2300 => x"82", + 2301 => x"83", + 2302 => x"38", + 2303 => x"76", + 2304 => x"70", + 2305 => x"18", + 2306 => x"76", + 2307 => x"9e", + 2308 => x"c0", + 2309 => x"de", + 2310 => x"d9", + 2311 => x"ff", + 2312 => x"05", + 2313 => x"81", + 2314 => x"54", + 2315 => x"80", + 2316 => x"77", + 2317 => x"f0", + 2318 => x"8f", + 2319 => x"51", + 2320 => x"34", + 2321 => x"17", + 2322 => x"2a", + 2323 => x"05", + 2324 => x"fa", + 2325 => x"de", + 2326 => x"81", + 2327 => x"81", + 2328 => x"83", + 2329 => x"b4", + 2330 => x"2a", + 2331 => x"8f", + 2332 => x"2a", + 2333 => x"f0", + 2334 => x"06", + 2335 => x"72", + 2336 => x"ec", + 2337 => x"2a", + 2338 => x"05", + 2339 => x"fa", + 2340 => x"de", + 2341 => x"81", + 2342 => x"80", + 2343 => x"83", + 2344 => x"52", + 2345 => x"fe", + 2346 => x"b4", + 2347 => x"a4", + 2348 => x"76", + 2349 => x"17", + 2350 => x"75", + 2351 => x"3f", + 2352 => x"08", + 2353 => x"c0", + 2354 => x"77", + 2355 => x"77", + 2356 => x"fc", + 2357 => x"b4", + 2358 => x"51", + 2359 => x"c9", + 2360 => x"c0", + 2361 => x"06", + 2362 => x"72", + 2363 => x"3f", + 2364 => x"17", + 2365 => x"de", + 2366 => x"3d", + 2367 => x"3d", + 2368 => x"7e", + 2369 => x"56", + 2370 => x"75", + 2371 => x"74", + 2372 => x"27", + 2373 => x"80", + 2374 => x"ff", + 2375 => x"75", + 2376 => x"3f", + 2377 => x"08", + 2378 => x"c0", + 2379 => x"38", + 2380 => x"54", + 2381 => x"81", + 2382 => x"39", + 2383 => x"08", + 2384 => x"39", + 2385 => x"51", + 2386 => x"81", + 2387 => x"58", + 2388 => x"08", + 2389 => x"c7", + 2390 => x"c0", + 2391 => x"d2", + 2392 => x"c0", + 2393 => x"cf", + 2394 => x"74", + 2395 => x"fc", + 2396 => x"de", + 2397 => x"38", + 2398 => x"fe", + 2399 => x"08", + 2400 => x"74", + 2401 => x"38", + 2402 => x"17", + 2403 => x"33", + 2404 => x"73", + 2405 => x"77", + 2406 => x"26", + 2407 => x"80", + 2408 => x"de", + 2409 => x"3d", + 2410 => x"3d", + 2411 => x"71", + 2412 => x"5b", + 2413 => x"8c", + 2414 => x"77", + 2415 => x"38", + 2416 => x"78", + 2417 => x"81", + 2418 => x"79", + 2419 => x"f9", + 2420 => x"55", + 2421 => x"c0", + 2422 => x"e0", + 2423 => x"c0", + 2424 => x"de", + 2425 => x"2e", + 2426 => x"98", + 2427 => x"de", + 2428 => x"82", + 2429 => x"58", + 2430 => x"70", + 2431 => x"80", + 2432 => x"38", + 2433 => x"09", + 2434 => x"e2", + 2435 => x"56", + 2436 => x"76", + 2437 => x"82", + 2438 => x"7a", + 2439 => x"3f", + 2440 => x"de", + 2441 => x"2e", + 2442 => x"86", + 2443 => x"c0", + 2444 => x"de", + 2445 => x"70", + 2446 => x"07", + 2447 => x"7c", + 2448 => x"c0", + 2449 => x"51", + 2450 => x"81", + 2451 => x"de", + 2452 => x"2e", + 2453 => x"17", + 2454 => x"74", + 2455 => x"73", + 2456 => x"27", + 2457 => x"58", + 2458 => x"80", + 2459 => x"56", + 2460 => x"98", + 2461 => x"26", + 2462 => x"56", + 2463 => x"81", + 2464 => x"52", + 2465 => x"c6", + 2466 => x"c0", + 2467 => x"b8", + 2468 => x"81", + 2469 => x"81", + 2470 => x"06", + 2471 => x"de", + 2472 => x"81", + 2473 => x"09", + 2474 => x"72", + 2475 => x"70", + 2476 => x"51", + 2477 => x"80", + 2478 => x"78", + 2479 => x"06", + 2480 => x"73", + 2481 => x"39", + 2482 => x"52", + 2483 => x"f7", + 2484 => x"c0", + 2485 => x"c0", + 2486 => x"81", + 2487 => x"07", + 2488 => x"55", + 2489 => x"2e", + 2490 => x"80", + 2491 => x"75", + 2492 => x"76", + 2493 => x"3f", + 2494 => x"08", + 2495 => x"38", + 2496 => x"0c", + 2497 => x"fe", + 2498 => x"08", + 2499 => x"74", + 2500 => x"ff", + 2501 => x"0c", + 2502 => x"81", + 2503 => x"84", + 2504 => x"39", + 2505 => x"81", + 2506 => x"8c", + 2507 => x"8c", + 2508 => x"c0", + 2509 => x"39", + 2510 => x"55", + 2511 => x"c0", + 2512 => x"0d", + 2513 => x"0d", + 2514 => x"55", + 2515 => x"81", + 2516 => x"58", + 2517 => x"de", + 2518 => x"d8", + 2519 => x"74", + 2520 => x"3f", + 2521 => x"08", + 2522 => x"08", + 2523 => x"59", + 2524 => x"77", + 2525 => x"70", + 2526 => x"c8", + 2527 => x"84", + 2528 => x"56", + 2529 => x"58", + 2530 => x"97", + 2531 => x"75", + 2532 => x"52", + 2533 => x"51", + 2534 => x"81", + 2535 => x"80", + 2536 => x"8a", + 2537 => x"32", + 2538 => x"72", + 2539 => x"2a", + 2540 => x"56", + 2541 => x"c0", + 2542 => x"0d", + 2543 => x"0d", + 2544 => x"08", + 2545 => x"74", + 2546 => x"26", + 2547 => x"74", + 2548 => x"72", + 2549 => x"74", + 2550 => x"88", + 2551 => x"73", + 2552 => x"33", + 2553 => x"27", + 2554 => x"16", + 2555 => x"9b", + 2556 => x"2a", + 2557 => x"88", + 2558 => x"58", + 2559 => x"80", + 2560 => x"16", + 2561 => x"0c", + 2562 => x"8a", + 2563 => x"89", + 2564 => x"72", + 2565 => x"38", + 2566 => x"51", + 2567 => x"81", + 2568 => x"54", + 2569 => x"08", + 2570 => x"38", + 2571 => x"de", + 2572 => x"8b", + 2573 => x"08", + 2574 => x"08", + 2575 => x"82", + 2576 => x"74", + 2577 => x"cb", + 2578 => x"75", + 2579 => x"3f", + 2580 => x"08", + 2581 => x"73", + 2582 => x"98", + 2583 => x"82", + 2584 => x"2e", + 2585 => x"39", + 2586 => x"39", + 2587 => x"13", + 2588 => x"74", + 2589 => x"16", + 2590 => x"18", + 2591 => x"77", + 2592 => x"0c", + 2593 => x"04", + 2594 => x"7a", + 2595 => x"12", + 2596 => x"59", + 2597 => x"80", + 2598 => x"86", + 2599 => x"98", + 2600 => x"14", + 2601 => x"55", + 2602 => x"81", + 2603 => x"83", + 2604 => x"77", + 2605 => x"81", + 2606 => x"0c", + 2607 => x"55", + 2608 => x"76", + 2609 => x"17", + 2610 => x"74", + 2611 => x"9b", + 2612 => x"39", + 2613 => x"ff", + 2614 => x"2a", + 2615 => x"81", + 2616 => x"52", + 2617 => x"e6", + 2618 => x"c0", + 2619 => x"55", + 2620 => x"de", + 2621 => x"80", + 2622 => x"55", + 2623 => x"08", + 2624 => x"f4", + 2625 => x"08", + 2626 => x"08", + 2627 => x"38", + 2628 => x"77", + 2629 => x"84", + 2630 => x"39", + 2631 => x"52", + 2632 => x"86", + 2633 => x"c0", + 2634 => x"55", + 2635 => x"08", + 2636 => x"c4", + 2637 => x"81", + 2638 => x"81", + 2639 => x"81", + 2640 => x"c0", + 2641 => x"b0", + 2642 => x"c0", + 2643 => x"51", + 2644 => x"81", + 2645 => x"a0", + 2646 => x"15", + 2647 => x"75", + 2648 => x"3f", + 2649 => x"08", + 2650 => x"76", + 2651 => x"77", + 2652 => x"9c", + 2653 => x"55", + 2654 => x"c0", + 2655 => x"0d", + 2656 => x"0d", + 2657 => x"08", + 2658 => x"80", + 2659 => x"fc", + 2660 => x"de", + 2661 => x"81", + 2662 => x"80", + 2663 => x"de", + 2664 => x"98", + 2665 => x"78", + 2666 => x"3f", + 2667 => x"08", + 2668 => x"c0", + 2669 => x"38", + 2670 => x"08", + 2671 => x"70", + 2672 => x"58", + 2673 => x"2e", + 2674 => x"83", + 2675 => x"81", + 2676 => x"55", + 2677 => x"81", + 2678 => x"07", + 2679 => x"2e", + 2680 => x"16", + 2681 => x"2e", + 2682 => x"88", + 2683 => x"81", + 2684 => x"56", + 2685 => x"51", + 2686 => x"81", + 2687 => x"54", + 2688 => x"08", + 2689 => x"9b", + 2690 => x"2e", + 2691 => x"83", + 2692 => x"73", + 2693 => x"0c", + 2694 => x"04", + 2695 => x"76", + 2696 => x"54", + 2697 => x"81", + 2698 => x"83", + 2699 => x"76", + 2700 => x"53", + 2701 => x"2e", + 2702 => x"90", + 2703 => x"51", + 2704 => x"81", + 2705 => x"90", + 2706 => x"53", + 2707 => x"c0", + 2708 => x"0d", + 2709 => x"0d", + 2710 => x"83", + 2711 => x"54", + 2712 => x"55", + 2713 => x"3f", + 2714 => x"51", + 2715 => x"2e", + 2716 => x"8b", + 2717 => x"2a", + 2718 => x"51", + 2719 => x"86", + 2720 => x"f7", + 2721 => x"7d", + 2722 => x"75", + 2723 => x"98", + 2724 => x"2e", + 2725 => x"98", + 2726 => x"78", + 2727 => x"3f", + 2728 => x"08", + 2729 => x"c0", + 2730 => x"38", + 2731 => x"70", + 2732 => x"73", + 2733 => x"58", + 2734 => x"8b", + 2735 => x"bf", + 2736 => x"ff", + 2737 => x"53", + 2738 => x"34", + 2739 => x"08", + 2740 => x"e5", + 2741 => x"81", + 2742 => x"2e", + 2743 => x"70", + 2744 => x"57", + 2745 => x"9e", + 2746 => x"2e", + 2747 => x"de", + 2748 => x"df", + 2749 => x"72", + 2750 => x"81", + 2751 => x"76", + 2752 => x"2e", + 2753 => x"52", + 2754 => x"fc", + 2755 => x"c0", + 2756 => x"de", + 2757 => x"38", + 2758 => x"fe", + 2759 => x"39", + 2760 => x"16", + 2761 => x"de", + 2762 => x"3d", + 2763 => x"3d", + 2764 => x"08", + 2765 => x"52", + 2766 => x"c5", + 2767 => x"c0", + 2768 => x"de", + 2769 => x"38", + 2770 => x"52", + 2771 => x"de", + 2772 => x"c0", + 2773 => x"de", + 2774 => x"38", + 2775 => x"de", + 2776 => x"9c", + 2777 => x"ea", + 2778 => x"53", + 2779 => x"9c", + 2780 => x"ea", + 2781 => x"0b", + 2782 => x"74", + 2783 => x"0c", + 2784 => x"04", + 2785 => x"75", + 2786 => x"12", + 2787 => x"53", + 2788 => x"9a", + 2789 => x"c0", + 2790 => x"9c", + 2791 => x"e5", + 2792 => x"0b", + 2793 => x"85", + 2794 => x"fa", + 2795 => x"7a", + 2796 => x"0b", + 2797 => x"98", + 2798 => x"2e", + 2799 => x"80", + 2800 => x"55", + 2801 => x"17", + 2802 => x"33", + 2803 => x"51", + 2804 => x"2e", + 2805 => x"85", + 2806 => x"06", + 2807 => x"e5", + 2808 => x"2e", + 2809 => x"8b", + 2810 => x"70", + 2811 => x"34", + 2812 => x"71", + 2813 => x"05", + 2814 => x"15", + 2815 => x"27", + 2816 => x"15", + 2817 => x"80", + 2818 => x"34", + 2819 => x"52", + 2820 => x"88", + 2821 => x"17", + 2822 => x"52", + 2823 => x"3f", + 2824 => x"08", + 2825 => x"12", + 2826 => x"3f", + 2827 => x"08", + 2828 => x"98", + 2829 => x"da", + 2830 => x"c0", + 2831 => x"23", + 2832 => x"04", + 2833 => x"7f", + 2834 => x"5b", + 2835 => x"33", + 2836 => x"73", + 2837 => x"38", + 2838 => x"80", + 2839 => x"38", + 2840 => x"8c", + 2841 => x"08", + 2842 => x"aa", + 2843 => x"41", + 2844 => x"33", + 2845 => x"73", + 2846 => x"81", + 2847 => x"81", + 2848 => x"dc", + 2849 => x"70", + 2850 => x"07", + 2851 => x"73", + 2852 => x"88", + 2853 => x"70", + 2854 => x"73", + 2855 => x"38", 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x"76", + 2915 => x"07", + 2916 => x"2e", + 2917 => x"8b", + 2918 => x"77", + 2919 => x"30", + 2920 => x"71", + 2921 => x"53", + 2922 => x"55", + 2923 => x"38", + 2924 => x"5c", + 2925 => x"75", + 2926 => x"73", + 2927 => x"38", + 2928 => x"06", + 2929 => x"11", + 2930 => x"75", + 2931 => x"3f", + 2932 => x"08", + 2933 => x"38", + 2934 => x"33", + 2935 => x"54", + 2936 => x"e6", + 2937 => x"de", + 2938 => x"2e", + 2939 => x"ff", + 2940 => x"74", + 2941 => x"38", + 2942 => x"75", + 2943 => x"17", + 2944 => x"57", + 2945 => x"a7", + 2946 => x"81", + 2947 => x"e5", + 2948 => x"de", + 2949 => x"38", + 2950 => x"54", + 2951 => x"89", + 2952 => x"70", + 2953 => x"57", + 2954 => x"54", + 2955 => x"81", + 2956 => x"f7", + 2957 => x"7e", + 2958 => x"2e", + 2959 => x"33", + 2960 => x"e5", + 2961 => x"06", + 2962 => x"7a", + 2963 => x"a0", + 2964 => x"38", + 2965 => x"55", + 2966 => x"84", + 2967 => x"39", + 2968 => x"8b", + 2969 => x"7b", + 2970 => x"7a", + 2971 => x"3f", + 2972 => x"08", + 2973 => x"c0", + 2974 => x"38", + 2975 => x"52", + 2976 => x"aa", + 2977 => x"c0", + 2978 => x"de", + 2979 => x"c2", + 2980 => x"08", + 2981 => x"55", + 2982 => x"ff", + 2983 => x"15", + 2984 => x"54", + 2985 => x"34", + 2986 => x"70", + 2987 => x"81", + 2988 => x"58", + 2989 => x"8b", + 2990 => x"74", + 2991 => x"3f", + 2992 => x"08", + 2993 => x"38", + 2994 => x"51", + 2995 => x"ff", + 2996 => x"ab", + 2997 => x"55", + 2998 => x"bb", + 2999 => x"2e", + 3000 => x"80", + 3001 => x"85", + 3002 => x"06", + 3003 => x"58", + 3004 => x"80", + 3005 => x"75", + 3006 => x"73", + 3007 => x"b5", + 3008 => x"0b", + 3009 => x"80", + 3010 => x"39", + 3011 => x"54", + 3012 => x"85", + 3013 => x"75", + 3014 => x"81", + 3015 => x"73", + 3016 => x"1b", + 3017 => x"2a", + 3018 => x"51", + 3019 => x"80", + 3020 => x"90", + 3021 => x"ff", + 3022 => x"05", + 3023 => x"f5", + 3024 => x"de", + 3025 => x"1c", + 3026 => x"39", + 3027 => x"c0", + 3028 => x"0d", + 3029 => x"0d", + 3030 => x"7b", + 3031 => x"73", + 3032 => x"55", + 3033 => x"2e", + 3034 => x"75", + 3035 => x"57", + 3036 => x"26", + 3037 => x"ba", + 3038 => x"70", + 3039 => x"ba", + 3040 => x"06", + 3041 => x"73", + 3042 => x"70", + 3043 => x"51", + 3044 => x"89", + 3045 => x"82", + 3046 => x"ff", + 3047 => x"56", + 3048 => x"2e", + 3049 => x"80", + 3050 => x"a4", + 3051 => x"08", + 3052 => x"76", + 3053 => x"58", + 3054 => x"81", + 3055 => x"ff", + 3056 => x"53", + 3057 => x"26", + 3058 => x"13", + 3059 => x"06", + 3060 => x"9f", + 3061 => x"99", + 3062 => x"e0", + 3063 => x"ff", + 3064 => x"72", + 3065 => x"2a", + 3066 => x"72", + 3067 => x"06", + 3068 => x"ff", + 3069 => x"30", + 3070 => x"70", + 3071 => x"07", + 3072 => x"9f", + 3073 => x"54", + 3074 => x"80", + 3075 => x"81", + 3076 => x"59", + 3077 => x"25", + 3078 => x"8b", + 3079 => x"24", + 3080 => x"76", + 3081 => x"78", + 3082 => x"81", + 3083 => x"51", + 3084 => x"c0", + 3085 => x"0d", + 3086 => x"0d", + 3087 => x"0b", + 3088 => x"ff", + 3089 => x"0c", + 3090 => x"51", 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x"81", + 3150 => x"81", + 3151 => x"72", + 3152 => x"80", + 3153 => x"38", + 3154 => x"70", + 3155 => x"53", + 3156 => x"86", + 3157 => x"a7", + 3158 => x"34", + 3159 => x"34", + 3160 => x"14", + 3161 => x"b2", + 3162 => x"c0", + 3163 => x"06", + 3164 => x"54", + 3165 => x"72", + 3166 => x"76", + 3167 => x"38", + 3168 => x"70", + 3169 => x"53", + 3170 => x"85", + 3171 => x"70", + 3172 => x"5b", + 3173 => x"81", + 3174 => x"81", + 3175 => x"76", + 3176 => x"81", + 3177 => x"38", + 3178 => x"56", + 3179 => x"83", + 3180 => x"70", + 3181 => x"80", + 3182 => x"83", + 3183 => x"dc", + 3184 => x"de", + 3185 => x"76", + 3186 => x"05", + 3187 => x"16", + 3188 => x"56", + 3189 => x"d7", + 3190 => x"8d", + 3191 => x"72", + 3192 => x"54", + 3193 => x"57", + 3194 => x"95", + 3195 => x"73", + 3196 => x"3f", + 3197 => x"08", + 3198 => x"57", + 3199 => x"89", + 3200 => x"56", + 3201 => x"d7", + 3202 => x"76", + 3203 => x"f1", + 3204 => x"76", + 3205 => x"e9", + 3206 => x"51", + 3207 => x"81", + 3208 => x"83", + 3209 => x"53", + 3210 => x"2e", + 3211 => x"84", + 3212 => x"ca", + 3213 => x"da", + 3214 => x"c0", + 3215 => x"ff", + 3216 => x"8d", + 3217 => x"14", + 3218 => x"3f", + 3219 => x"08", + 3220 => x"15", + 3221 => x"14", + 3222 => x"34", + 3223 => x"33", + 3224 => x"81", + 3225 => x"54", + 3226 => x"72", + 3227 => x"91", + 3228 => x"ff", + 3229 => x"29", + 3230 => x"33", + 3231 => x"72", + 3232 => x"72", + 3233 => x"38", + 3234 => x"06", + 3235 => x"2e", + 3236 => x"56", + 3237 => x"80", + 3238 => x"da", + 3239 => x"de", + 3240 => x"81", + 3241 => x"88", + 3242 => x"8f", + 3243 => x"56", + 3244 => x"38", + 3245 => x"51", + 3246 => x"81", + 3247 => x"83", + 3248 => x"55", + 3249 => x"80", + 3250 => x"da", + 3251 => x"de", + 3252 => x"80", + 3253 => x"da", + 3254 => x"de", + 3255 => x"ff", + 3256 => x"8d", + 3257 => x"2e", + 3258 => x"88", + 3259 => x"14", + 3260 => x"05", + 3261 => x"75", + 3262 => x"38", + 3263 => x"52", + 3264 => x"51", + 3265 => x"3f", + 3266 => x"08", + 3267 => x"c0", + 3268 => x"82", + 3269 => x"de", + 3270 => x"ff", + 3271 => x"26", + 3272 => x"57", + 3273 => x"f5", + 3274 => x"82", + 3275 => x"f5", + 3276 => x"81", + 3277 => x"8d", + 3278 => x"2e", + 3279 => x"82", + 3280 => x"16", + 3281 => x"16", + 3282 => x"70", + 3283 => x"7a", + 3284 => x"0c", + 3285 => x"83", + 3286 => x"06", + 3287 => x"de", + 3288 => x"ae", + 3289 => x"c0", + 3290 => x"ff", + 3291 => x"56", + 3292 => x"38", + 3293 => x"38", + 3294 => x"51", + 3295 => x"81", + 3296 => x"a8", + 3297 => x"82", + 3298 => x"39", + 3299 => x"80", + 3300 => x"38", + 3301 => x"15", + 3302 => x"53", + 3303 => x"8d", + 3304 => x"15", + 3305 => x"76", + 3306 => x"51", + 3307 => x"13", + 3308 => x"8d", + 3309 => x"15", + 3310 => x"c5", + 3311 => x"90", + 3312 => x"0b", + 3313 => x"ff", + 3314 => x"15", + 3315 => x"2e", + 3316 => x"81", + 3317 => x"e4", + 3318 => x"b6", + 3319 => x"c0", + 3320 => x"ff", + 3321 => x"81", + 3322 => x"06", + 3323 => x"81", + 3324 => x"51", + 3325 => x"81", + 3326 => x"80", + 3327 => x"de", + 3328 => x"15", + 3329 => x"14", + 3330 => x"3f", + 3331 => x"08", + 3332 => x"06", + 3333 => x"d4", + 3334 => x"81", + 3335 => x"38", + 3336 => x"d8", + 3337 => x"de", + 3338 => x"8b", + 3339 => x"2e", + 3340 => x"b3", + 3341 => x"14", + 3342 => x"3f", + 3343 => x"08", + 3344 => x"e4", + 3345 => x"81", + 3346 => x"84", + 3347 => x"d7", + 3348 => x"de", + 3349 => x"15", + 3350 => x"14", + 3351 => x"3f", + 3352 => x"08", + 3353 => x"76", + 3354 => x"de", + 3355 => x"05", + 3356 => x"de", + 3357 => x"86", + 3358 => x"0b", + 3359 => x"80", + 3360 => x"de", + 3361 => x"3d", + 3362 => x"3d", + 3363 => x"89", + 3364 => x"2e", + 3365 => x"08", + 3366 => x"2e", + 3367 => x"33", + 3368 => x"2e", + 3369 => x"13", + 3370 => x"22", + 3371 => x"76", + 3372 => x"06", + 3373 => x"13", + 3374 => x"c0", + 3375 => x"c0", + 3376 => x"52", + 3377 => x"71", + 3378 => x"55", + 3379 => x"53", + 3380 => x"0c", + 3381 => x"de", + 3382 => x"3d", + 3383 => x"3d", + 3384 => x"05", + 3385 => x"89", + 3386 => x"52", + 3387 => x"3f", + 3388 => x"0b", + 3389 => x"08", + 3390 => x"81", + 3391 => x"84", + 3392 => x"dc", + 3393 => x"55", + 3394 => x"2e", + 3395 => x"74", + 3396 => x"73", + 3397 => x"38", + 3398 => x"78", + 3399 => x"54", + 3400 => x"92", + 3401 => x"89", + 3402 => x"84", + 3403 => x"b0", + 3404 => x"c0", + 3405 => x"81", + 3406 => x"88", + 3407 => x"eb", + 3408 => x"02", + 3409 => x"e7", + 3410 => x"59", + 3411 => x"80", + 3412 => x"38", + 3413 => x"70", + 3414 => x"d0", + 3415 => x"3d", + 3416 => x"58", + 3417 => x"81", + 3418 => x"55", + 3419 => x"08", + 3420 => x"7a", + 3421 => x"8c", + 3422 => x"56", + 3423 => x"81", + 3424 => x"55", + 3425 => x"08", + 3426 => x"80", + 3427 => x"70", + 3428 => x"57", + 3429 => x"83", + 3430 => x"77", + 3431 => x"73", + 3432 => x"ab", + 3433 => x"2e", + 3434 => x"84", + 3435 => x"06", + 3436 => x"51", + 3437 => x"81", + 3438 => x"55", + 3439 => x"b2", + 3440 => x"06", + 3441 => x"b8", + 3442 => x"2a", + 3443 => x"51", + 3444 => x"2e", + 3445 => x"55", + 3446 => x"77", + 3447 => x"74", + 3448 => x"77", + 3449 => x"81", + 3450 => x"73", + 3451 => x"af", + 3452 => x"7a", + 3453 => x"3f", + 3454 => x"08", + 3455 => x"b2", + 3456 => x"8e", + 3457 => x"ea", + 3458 => x"a0", + 3459 => x"34", + 3460 => x"52", + 3461 => x"bd", + 3462 => x"62", + 3463 => x"d4", + 3464 => x"54", + 3465 => x"15", + 3466 => x"2e", + 3467 => x"7a", + 3468 => x"51", + 3469 => x"75", + 3470 => x"d4", + 3471 => x"be", + 3472 => x"c0", + 3473 => x"de", + 3474 => x"ca", + 3475 => x"74", + 3476 => x"02", + 3477 => x"70", + 3478 => x"81", + 3479 => x"56", + 3480 => x"86", + 3481 => x"82", + 3482 => x"81", + 3483 => x"06", + 3484 => x"80", + 3485 => x"75", + 3486 => x"73", + 3487 => x"38", + 3488 => x"92", + 3489 => x"7a", + 3490 => x"3f", + 3491 => x"08", + 3492 => x"8c", + 3493 => x"55", + 3494 => x"08", + 3495 => x"77", + 3496 => x"81", + 3497 => x"73", + 3498 => x"38", + 3499 => x"07", + 3500 => x"11", + 3501 => x"0c", + 3502 => x"0c", + 3503 => x"52", + 3504 => x"3f", + 3505 => x"08", + 3506 => x"08", + 3507 => x"63", + 3508 => x"5a", + 3509 => x"81", + 3510 => x"81", + 3511 => x"8c", + 3512 => x"7a", + 3513 => x"17", + 3514 => x"23", + 3515 => x"34", + 3516 => x"1a", + 3517 => x"9c", + 3518 => x"0b", + 3519 => x"77", + 3520 => x"81", + 3521 => x"73", + 3522 => x"8d", + 3523 => x"c0", + 3524 => x"81", + 3525 => x"de", + 3526 => x"1a", + 3527 => x"22", + 3528 => x"7b", + 3529 => x"a8", + 3530 => x"78", + 3531 => x"3f", + 3532 => x"08", + 3533 => x"c0", + 3534 => x"83", + 3535 => x"81", + 3536 => x"ff", + 3537 => x"06", + 3538 => x"55", + 3539 => x"56", + 3540 => x"76", + 3541 => x"51", + 3542 => x"27", + 3543 => x"70", + 3544 => x"5a", + 3545 => x"76", + 3546 => x"74", + 3547 => x"83", + 3548 => x"73", + 3549 => x"38", + 3550 => x"51", + 3551 => x"81", + 3552 => x"85", + 3553 => x"8e", + 3554 => x"2a", + 3555 => x"08", + 3556 => x"0c", + 3557 => x"79", + 3558 => x"73", + 3559 => x"0c", + 3560 => x"04", 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x"ca", + 3620 => x"de", + 3621 => x"d7", + 3622 => x"11", + 3623 => x"74", + 3624 => x"38", + 3625 => x"77", + 3626 => x"78", + 3627 => x"84", + 3628 => x"16", + 3629 => x"08", + 3630 => x"2b", + 3631 => x"cf", + 3632 => x"89", + 3633 => x"39", + 3634 => x"0c", + 3635 => x"83", + 3636 => x"80", + 3637 => x"55", + 3638 => x"83", + 3639 => x"9c", + 3640 => x"7e", + 3641 => x"3f", + 3642 => x"08", + 3643 => x"75", + 3644 => x"08", + 3645 => x"1f", + 3646 => x"7c", + 3647 => x"3f", + 3648 => x"7e", + 3649 => x"0c", + 3650 => x"1b", + 3651 => x"1c", + 3652 => x"fd", + 3653 => x"56", + 3654 => x"c0", + 3655 => x"0d", + 3656 => x"0d", + 3657 => x"64", + 3658 => x"58", + 3659 => x"90", + 3660 => x"52", + 3661 => x"d2", + 3662 => x"c0", + 3663 => x"de", + 3664 => x"38", + 3665 => x"55", + 3666 => x"86", + 3667 => x"83", + 3668 => x"18", + 3669 => x"2a", + 3670 => x"51", + 3671 => x"56", + 3672 => x"83", + 3673 => x"39", + 3674 => x"19", + 3675 => x"83", + 3676 => x"0b", + 3677 => x"81", + 3678 => x"39", + 3679 => x"7c", + 3680 => x"74", + 3681 => x"38", + 3682 => x"7b", + 3683 => x"ec", + 3684 => x"08", + 3685 => x"06", + 3686 => x"81", + 3687 => x"8a", + 3688 => x"05", + 3689 => x"06", + 3690 => x"bf", + 3691 => x"38", + 3692 => x"55", + 3693 => x"7a", + 3694 => x"98", + 3695 => x"77", + 3696 => x"3f", + 3697 => x"08", + 3698 => x"c0", + 3699 => x"82", + 3700 => x"81", + 3701 => x"38", + 3702 => x"ff", + 3703 => x"98", + 3704 => x"18", + 3705 => x"74", + 3706 => x"7e", + 3707 => x"08", + 3708 => x"2e", + 3709 => x"8d", + 3710 => x"ce", + 3711 => x"de", + 3712 => x"ee", + 3713 => x"08", + 3714 => x"d1", + 3715 => x"de", + 3716 => x"2e", + 3717 => x"81", + 3718 => x"1b", + 3719 => x"5a", + 3720 => x"2e", + 3721 => x"78", + 3722 => x"11", + 3723 => x"55", + 3724 => x"85", + 3725 => x"31", + 3726 => x"76", + 3727 => x"81", + 3728 => x"c8", + 3729 => x"de", + 3730 => x"a6", + 3731 => x"11", + 3732 => x"56", + 3733 => x"27", + 3734 => x"80", + 3735 => x"08", + 3736 => x"2b", + 3737 => x"b4", + 3738 => x"b5", + 3739 => x"80", + 3740 => x"34", + 3741 => x"56", + 3742 => x"8c", + 3743 => x"19", + 3744 => x"38", + 3745 => x"b6", + 3746 => x"c0", + 3747 => x"38", + 3748 => x"12", + 3749 => x"9c", + 3750 => x"18", + 3751 => x"06", + 3752 => x"31", + 3753 => x"76", + 3754 => x"7b", + 3755 => x"08", + 3756 => x"cd", + 3757 => x"de", + 3758 => x"b6", + 3759 => x"7c", + 3760 => x"08", + 3761 => x"1f", + 3762 => x"cb", + 3763 => x"55", + 3764 => x"16", + 3765 => x"31", + 3766 => x"7f", + 3767 => x"94", + 3768 => x"70", + 3769 => x"8c", + 3770 => x"58", + 3771 => x"76", + 3772 => x"75", + 3773 => x"19", + 3774 => x"39", + 3775 => x"80", + 3776 => x"74", + 3777 => x"80", + 3778 => x"de", + 3779 => x"3d", + 3780 => x"3d", + 3781 => x"3d", + 3782 => x"70", + 3783 => x"ea", + 3784 => x"c0", + 3785 => x"de", + 3786 => x"fb", + 3787 => x"33", + 3788 => x"70", + 3789 => x"55", + 3790 => x"2e", + 3791 => x"a0", + 3792 => x"78", + 3793 => x"3f", + 3794 => x"08", + 3795 => x"c0", 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x"08", + 3855 => x"c0", + 3856 => x"02", + 3857 => x"33", + 3858 => x"55", + 3859 => x"25", + 3860 => x"7a", + 3861 => x"54", + 3862 => x"a2", + 3863 => x"84", + 3864 => x"06", + 3865 => x"73", + 3866 => x"38", + 3867 => x"70", + 3868 => x"a8", + 3869 => x"c0", + 3870 => x"0c", + 3871 => x"de", + 3872 => x"2e", + 3873 => x"83", + 3874 => x"74", + 3875 => x"0c", + 3876 => x"04", + 3877 => x"6f", + 3878 => x"80", + 3879 => x"53", + 3880 => x"b8", + 3881 => x"3d", + 3882 => x"3f", + 3883 => x"08", + 3884 => x"c0", + 3885 => x"38", + 3886 => x"7c", + 3887 => x"47", + 3888 => x"54", + 3889 => x"81", + 3890 => x"52", + 3891 => x"52", + 3892 => x"3f", + 3893 => x"08", + 3894 => x"c0", + 3895 => x"38", + 3896 => x"51", + 3897 => x"81", + 3898 => x"57", + 3899 => x"08", + 3900 => x"69", + 3901 => x"da", + 3902 => x"de", + 3903 => x"76", + 3904 => x"d5", + 3905 => x"de", + 3906 => x"81", + 3907 => x"82", + 3908 => x"52", + 3909 => x"eb", + 3910 => x"c0", + 3911 => x"de", + 3912 => x"38", + 3913 => x"51", + 3914 => x"73", + 3915 => x"08", + 3916 => x"76", + 3917 => x"d6", + 3918 => x"de", + 3919 => x"81", + 3920 => x"80", + 3921 => x"76", + 3922 => x"81", + 3923 => x"82", + 3924 => x"39", + 3925 => x"38", + 3926 => x"bc", + 3927 => x"51", + 3928 => x"76", + 3929 => x"11", + 3930 => x"51", + 3931 => x"73", + 3932 => x"38", + 3933 => x"55", + 3934 => x"16", + 3935 => x"56", + 3936 => x"38", + 3937 => x"73", + 3938 => x"90", + 3939 => x"2e", + 3940 => x"16", + 3941 => x"ff", + 3942 => x"ff", + 3943 => x"58", + 3944 => x"74", + 3945 => x"75", + 3946 => x"18", + 3947 => x"58", + 3948 => x"fe", + 3949 => x"7b", + 3950 => x"06", + 3951 => x"18", + 3952 => x"58", + 3953 => x"80", + 3954 => x"f0", + 3955 => x"29", + 3956 => x"05", + 3957 => x"33", + 3958 => x"56", + 3959 => x"2e", + 3960 => x"16", + 3961 => x"33", + 3962 => x"73", + 3963 => x"16", + 3964 => x"26", + 3965 => x"55", + 3966 => x"91", + 3967 => x"54", + 3968 => x"70", + 3969 => x"34", + 3970 => x"ec", + 3971 => x"70", + 3972 => x"34", + 3973 => x"09", + 3974 => x"38", + 3975 => x"39", + 3976 => x"19", + 3977 => x"33", + 3978 => x"05", + 3979 => x"78", + 3980 => x"80", + 3981 => x"81", + 3982 => x"9e", + 3983 => x"f7", + 3984 => x"7d", + 3985 => x"05", + 3986 => x"57", + 3987 => x"3f", + 3988 => x"08", + 3989 => x"c0", + 3990 => x"38", + 3991 => x"53", + 3992 => x"38", + 3993 => x"54", + 3994 => x"92", + 3995 => x"33", + 3996 => x"70", + 3997 => x"54", + 3998 => x"38", + 3999 => x"15", + 4000 => x"70", + 4001 => x"58", + 4002 => x"82", + 4003 => x"8a", + 4004 => x"89", + 4005 => x"53", + 4006 => x"b7", + 4007 => x"ff", + 4008 => x"95", + 4009 => x"de", + 4010 => x"15", + 4011 => x"53", + 4012 => x"95", + 4013 => x"de", + 4014 => x"26", + 4015 => x"30", + 4016 => x"70", + 4017 => x"77", + 4018 => x"18", + 4019 => x"51", + 4020 => x"88", + 4021 => x"73", + 4022 => x"52", + 4023 => x"ca", + 4024 => x"c0", + 4025 => x"de", + 4026 => x"2e", + 4027 => x"81", + 4028 => x"ff", + 4029 => x"38", + 4030 => x"08", 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x"2e", + 4090 => x"80", + 4091 => x"fc", + 4092 => x"3d", + 4093 => x"e1", + 4094 => x"de", + 4095 => x"81", + 4096 => x"80", + 4097 => x"76", + 4098 => x"75", + 4099 => x"3f", + 4100 => x"08", + 4101 => x"c0", + 4102 => x"38", + 4103 => x"70", + 4104 => x"57", + 4105 => x"a2", + 4106 => x"33", + 4107 => x"70", + 4108 => x"55", + 4109 => x"2e", + 4110 => x"16", + 4111 => x"51", + 4112 => x"81", + 4113 => x"88", + 4114 => x"54", + 4115 => x"84", + 4116 => x"52", + 4117 => x"e5", + 4118 => x"c0", + 4119 => x"84", + 4120 => x"06", + 4121 => x"55", + 4122 => x"80", + 4123 => x"80", + 4124 => x"54", + 4125 => x"c0", + 4126 => x"0d", + 4127 => x"0d", + 4128 => x"fc", + 4129 => x"52", + 4130 => x"3f", + 4131 => x"08", + 4132 => x"de", + 4133 => x"0c", + 4134 => x"04", + 4135 => x"77", + 4136 => x"fc", + 4137 => x"53", + 4138 => x"de", + 4139 => x"c0", + 4140 => x"de", + 4141 => x"df", + 4142 => x"38", + 4143 => x"08", + 4144 => x"cd", + 4145 => x"de", + 4146 => x"80", + 4147 => x"de", + 4148 => x"73", + 4149 => x"3f", + 4150 => x"08", + 4151 => x"c0", + 4152 => x"09", + 4153 => x"38", + 4154 => x"39", + 4155 => x"08", + 4156 => x"52", + 4157 => x"b3", + 4158 => x"73", + 4159 => x"3f", + 4160 => x"08", + 4161 => x"30", + 4162 => x"9f", + 4163 => x"de", + 4164 => x"51", + 4165 => x"72", + 4166 => x"0c", + 4167 => x"04", + 4168 => x"65", + 4169 => x"89", + 4170 => x"96", + 4171 => x"df", + 4172 => x"de", + 4173 => x"81", + 4174 => x"b2", + 4175 => x"75", + 4176 => x"3f", + 4177 => x"08", + 4178 => x"c0", + 4179 => x"02", + 4180 => x"33", + 4181 => x"55", + 4182 => x"25", + 4183 => x"55", + 4184 => x"80", + 4185 => x"76", + 4186 => x"d4", + 4187 => x"81", + 4188 => x"94", + 4189 => x"f0", + 4190 => x"65", + 4191 => x"53", + 4192 => x"05", + 4193 => x"51", + 4194 => x"81", + 4195 => x"5b", + 4196 => x"08", + 4197 => x"7c", + 4198 => x"08", + 4199 => x"fe", + 4200 => x"08", + 4201 => x"55", + 4202 => x"91", + 4203 => x"0c", + 4204 => x"81", + 4205 => x"39", + 4206 => x"c7", + 4207 => x"c0", + 4208 => x"55", + 4209 => x"2e", + 4210 => x"bf", + 4211 => x"5f", + 4212 => x"92", + 4213 => x"51", + 4214 => x"81", + 4215 => x"ff", + 4216 => x"81", + 4217 => x"81", + 4218 => x"81", + 4219 => x"30", + 4220 => x"c0", + 4221 => x"25", + 4222 => x"19", + 4223 => x"5a", + 4224 => x"08", + 4225 => x"38", + 4226 => x"a4", + 4227 => x"de", + 4228 => x"58", + 4229 => x"77", + 4230 => x"7d", + 4231 => x"bf", + 4232 => x"de", + 4233 => x"81", + 4234 => x"80", + 4235 => x"70", + 4236 => x"ff", + 4237 => x"56", + 4238 => x"2e", + 4239 => x"9e", + 4240 => x"51", + 4241 => x"3f", + 4242 => x"08", + 4243 => x"06", + 4244 => x"80", + 4245 => x"19", + 4246 => x"54", + 4247 => x"14", + 4248 => x"c5", + 4249 => x"c0", + 4250 => x"06", + 4251 => x"80", + 4252 => x"19", + 4253 => x"54", + 4254 => x"06", + 4255 => x"79", + 4256 => x"78", + 4257 => x"79", + 4258 => x"84", + 4259 => x"07", + 4260 => x"84", + 4261 => x"81", + 4262 => x"92", + 4263 => x"f9", + 4264 => x"8a", + 4265 => x"53", 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x"58", + 4325 => x"81", + 4326 => x"55", + 4327 => x"08", + 4328 => x"02", + 4329 => x"33", + 4330 => x"70", + 4331 => x"55", + 4332 => x"73", + 4333 => x"75", + 4334 => x"80", + 4335 => x"bd", + 4336 => x"d6", + 4337 => x"81", + 4338 => x"87", + 4339 => x"ad", + 4340 => x"78", + 4341 => x"3f", + 4342 => x"08", + 4343 => x"70", + 4344 => x"55", + 4345 => x"2e", + 4346 => x"78", + 4347 => x"c0", + 4348 => x"08", + 4349 => x"38", + 4350 => x"de", + 4351 => x"76", + 4352 => x"70", + 4353 => x"b5", + 4354 => x"c0", + 4355 => x"de", + 4356 => x"e9", + 4357 => x"c0", + 4358 => x"51", + 4359 => x"81", + 4360 => x"55", + 4361 => x"08", + 4362 => x"55", + 4363 => x"81", + 4364 => x"84", + 4365 => x"81", + 4366 => x"80", + 4367 => x"51", + 4368 => x"81", + 4369 => x"81", + 4370 => x"30", + 4371 => x"c0", + 4372 => x"25", + 4373 => x"75", + 4374 => x"38", + 4375 => x"8f", + 4376 => x"75", + 4377 => x"c1", + 4378 => x"de", + 4379 => x"74", + 4380 => x"51", + 4381 => x"3f", + 4382 => x"08", + 4383 => x"de", + 4384 => x"3d", + 4385 => x"3d", + 4386 => x"99", + 4387 => x"52", + 4388 => x"d8", + 4389 => x"de", + 4390 => x"81", + 4391 => x"82", + 4392 => x"5e", + 4393 => x"3d", + 4394 => x"cf", + 4395 => x"de", + 4396 => x"81", + 4397 => x"86", + 4398 => x"82", + 4399 => x"de", + 4400 => x"2e", + 4401 => x"82", + 4402 => x"80", + 4403 => x"70", + 4404 => x"06", + 4405 => x"54", + 4406 => x"38", + 4407 => x"52", + 4408 => x"52", + 4409 => x"3f", + 4410 => x"08", + 4411 => x"81", + 4412 => x"83", + 4413 => x"81", + 4414 => x"81", + 4415 => x"06", + 4416 => x"54", + 4417 => x"08", + 4418 => x"81", + 4419 => x"81", + 4420 => x"39", + 4421 => x"38", + 4422 => x"08", + 4423 => x"c4", + 4424 => x"de", + 4425 => x"81", + 4426 => x"81", + 4427 => x"53", + 4428 => x"19", + 4429 => x"8c", + 4430 => x"ae", + 4431 => x"34", + 4432 => x"0b", + 4433 => x"82", + 4434 => x"52", + 4435 => x"51", + 4436 => x"3f", + 4437 => x"b4", + 4438 => x"c9", + 4439 => x"53", + 4440 => x"53", + 4441 => x"51", + 4442 => x"3f", + 4443 => x"0b", + 4444 => x"34", + 4445 => x"80", + 4446 => x"51", + 4447 => x"78", + 4448 => x"83", + 4449 => x"51", + 4450 => x"81", + 4451 => x"54", + 4452 => x"08", + 4453 => x"88", + 4454 => x"64", + 4455 => x"ff", + 4456 => x"75", + 4457 => x"78", + 4458 => x"3f", + 4459 => x"0b", + 4460 => x"78", + 4461 => x"83", + 4462 => x"51", + 4463 => x"3f", + 4464 => x"08", + 4465 => x"80", + 4466 => x"76", + 4467 => x"ae", + 4468 => x"de", + 4469 => x"3d", + 4470 => x"3d", + 4471 => x"84", + 4472 => x"f1", + 4473 => x"a8", + 4474 => x"05", + 4475 => x"51", + 4476 => x"81", + 4477 => x"55", + 4478 => x"08", + 4479 => x"78", + 4480 => x"08", + 4481 => x"70", + 4482 => x"b8", + 4483 => x"c0", + 4484 => x"de", + 4485 => x"b9", + 4486 => x"9b", + 4487 => x"a0", + 4488 => x"55", + 4489 => x"38", + 4490 => x"3d", + 4491 => x"3d", + 4492 => x"51", + 4493 => x"3f", + 4494 => x"52", + 4495 => x"52", + 4496 => x"dd", + 4497 => x"08", + 4498 => x"cb", + 4499 => x"de", + 4500 => x"81", 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x"55", + 4560 => x"08", + 4561 => x"51", + 4562 => x"3f", + 4563 => x"08", + 4564 => x"de", + 4565 => x"3d", + 4566 => x"3d", + 4567 => x"db", + 4568 => x"84", + 4569 => x"05", + 4570 => x"82", + 4571 => x"d0", + 4572 => x"3d", + 4573 => x"3f", + 4574 => x"08", + 4575 => x"c0", + 4576 => x"38", + 4577 => x"52", + 4578 => x"05", + 4579 => x"3f", + 4580 => x"08", + 4581 => x"c0", + 4582 => x"02", + 4583 => x"33", + 4584 => x"54", + 4585 => x"aa", + 4586 => x"06", + 4587 => x"8b", + 4588 => x"06", + 4589 => x"07", + 4590 => x"56", + 4591 => x"34", + 4592 => x"0b", + 4593 => x"78", + 4594 => x"a9", + 4595 => x"c0", + 4596 => x"81", + 4597 => x"95", + 4598 => x"ef", + 4599 => x"56", + 4600 => x"3d", + 4601 => x"94", + 4602 => x"f4", + 4603 => x"c0", + 4604 => x"de", + 4605 => x"cb", + 4606 => x"63", + 4607 => x"d4", + 4608 => x"c0", + 4609 => x"c0", + 4610 => x"de", + 4611 => x"38", + 4612 => x"05", + 4613 => x"06", + 4614 => x"73", + 4615 => x"16", + 4616 => x"22", + 4617 => x"07", + 4618 => x"1f", + 4619 => x"c2", + 4620 => x"81", + 4621 => x"34", + 4622 => x"b3", + 4623 => x"de", + 4624 => x"74", + 4625 => x"0c", + 4626 => x"04", + 4627 => x"69", + 4628 => x"80", + 4629 => x"d0", + 4630 => x"3d", + 4631 => x"3f", + 4632 => x"08", + 4633 => x"08", + 4634 => x"de", + 4635 => x"80", + 4636 => x"57", + 4637 => x"81", + 4638 => x"70", + 4639 => x"55", + 4640 => x"80", + 4641 => x"5d", + 4642 => x"52", + 4643 => x"52", + 4644 => x"a9", + 4645 => x"c0", + 4646 => x"de", + 4647 => x"d1", + 4648 => x"73", + 4649 => x"3f", + 4650 => x"08", + 4651 => x"c0", + 4652 => x"81", + 4653 => x"81", + 4654 => x"65", + 4655 => x"78", + 4656 => x"7b", + 4657 => x"55", + 4658 => x"34", + 4659 => x"8a", + 4660 => x"38", + 4661 => x"1a", + 4662 => x"34", + 4663 => x"9e", + 4664 => x"70", + 4665 => x"51", + 4666 => x"a0", + 4667 => x"8e", + 4668 => x"2e", + 4669 => x"86", + 4670 => x"34", + 4671 => x"30", + 4672 => x"80", + 4673 => x"7a", + 4674 => x"c1", + 4675 => x"2e", + 4676 => x"a0", + 4677 => x"51", + 4678 => x"3f", + 4679 => x"08", + 4680 => x"c0", + 4681 => x"7b", + 4682 => x"55", + 4683 => x"73", + 4684 => x"38", + 4685 => x"73", + 4686 => x"38", + 4687 => x"15", + 4688 => x"ff", + 4689 => x"81", + 4690 => x"7b", + 4691 => x"de", + 4692 => x"3d", + 4693 => x"3d", + 4694 => x"9c", + 4695 => x"05", + 4696 => x"51", + 4697 => x"81", + 4698 => x"81", + 4699 => x"56", + 4700 => x"c0", + 4701 => x"38", + 4702 => x"52", + 4703 => x"52", + 4704 => x"c0", + 4705 => x"70", + 4706 => x"ff", + 4707 => x"55", + 4708 => x"27", + 4709 => x"78", + 4710 => x"ff", + 4711 => x"05", + 4712 => x"55", + 4713 => x"3f", + 4714 => x"08", + 4715 => x"38", + 4716 => x"70", + 4717 => x"ff", + 4718 => x"81", + 4719 => x"80", + 4720 => x"74", + 4721 => x"07", + 4722 => x"4e", + 4723 => x"81", + 4724 => x"55", + 4725 => x"70", + 4726 => x"06", + 4727 => x"99", + 4728 => x"e0", + 4729 => x"ff", + 4730 => x"54", + 4731 => x"27", + 4732 => x"cc", + 4733 => x"55", + 4734 => x"a3", + 4735 => x"81", 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x"54", + 4795 => x"15", + 4796 => x"78", + 4797 => x"ff", + 4798 => x"79", + 4799 => x"83", + 4800 => x"51", + 4801 => x"3f", + 4802 => x"08", + 4803 => x"74", + 4804 => x"0c", + 4805 => x"04", + 4806 => x"60", + 4807 => x"05", + 4808 => x"33", + 4809 => x"05", + 4810 => x"40", + 4811 => x"da", + 4812 => x"c0", + 4813 => x"de", + 4814 => x"bd", + 4815 => x"33", + 4816 => x"b5", + 4817 => x"2e", + 4818 => x"1a", + 4819 => x"90", + 4820 => x"33", + 4821 => x"70", + 4822 => x"55", + 4823 => x"38", + 4824 => x"97", + 4825 => x"82", + 4826 => x"58", + 4827 => x"7e", + 4828 => x"70", + 4829 => x"55", + 4830 => x"56", + 4831 => x"f7", + 4832 => x"7d", + 4833 => x"70", + 4834 => x"2a", + 4835 => x"08", + 4836 => x"08", + 4837 => x"5d", + 4838 => x"77", + 4839 => x"98", + 4840 => x"26", + 4841 => x"57", + 4842 => x"59", + 4843 => x"52", + 4844 => x"ae", + 4845 => x"15", + 4846 => x"98", + 4847 => x"26", + 4848 => x"55", + 4849 => x"08", + 4850 => x"99", + 4851 => x"c0", + 4852 => x"ff", + 4853 => x"de", + 4854 => x"38", + 4855 => x"75", + 4856 => x"81", + 4857 => x"93", + 4858 => x"80", + 4859 => x"2e", + 4860 => x"ff", + 4861 => x"58", + 4862 => x"7d", + 4863 => x"38", + 4864 => x"55", + 4865 => x"b4", + 4866 => x"56", + 4867 => x"09", + 4868 => x"38", + 4869 => x"53", + 4870 => x"51", + 4871 => x"3f", + 4872 => x"08", + 4873 => x"c0", + 4874 => x"38", + 4875 => x"ff", + 4876 => x"5c", + 4877 => x"84", + 4878 => x"5c", + 4879 => x"12", + 4880 => x"80", + 4881 => x"78", + 4882 => x"7c", + 4883 => x"90", + 4884 => x"c0", + 4885 => x"90", + 4886 => x"15", + 4887 => x"90", + 4888 => x"54", + 4889 => x"91", + 4890 => x"31", + 4891 => x"84", + 4892 => x"07", + 4893 => x"16", + 4894 => x"73", + 4895 => x"0c", + 4896 => x"04", + 4897 => x"6b", + 4898 => x"05", + 4899 => x"33", + 4900 => x"5a", + 4901 => x"bd", + 4902 => x"80", + 4903 => x"c0", + 4904 => x"f8", + 4905 => x"c0", + 4906 => x"81", + 4907 => x"70", + 4908 => x"74", + 4909 => x"38", + 4910 => x"81", + 4911 => x"81", + 4912 => x"81", + 4913 => x"ff", + 4914 => x"81", + 4915 => x"81", + 4916 => x"81", + 4917 => x"83", + 4918 => x"c0", + 4919 => x"2a", + 4920 => x"51", + 4921 => x"74", + 4922 => x"99", + 4923 => x"53", + 4924 => x"51", + 4925 => x"3f", + 4926 => x"08", + 4927 => x"55", + 4928 => x"92", + 4929 => x"80", + 4930 => x"38", + 4931 => x"06", + 4932 => x"2e", + 4933 => x"48", + 4934 => x"87", + 4935 => x"79", + 4936 => x"78", + 4937 => x"26", + 4938 => x"19", + 4939 => x"74", + 4940 => x"38", + 4941 => x"e4", + 4942 => x"2a", + 4943 => x"70", + 4944 => x"59", + 4945 => x"7a", + 4946 => x"56", + 4947 => x"80", + 4948 => x"51", + 4949 => x"74", + 4950 => x"99", + 4951 => x"53", + 4952 => x"51", + 4953 => x"3f", + 4954 => x"de", + 4955 => x"ac", + 4956 => x"2a", + 4957 => x"81", + 4958 => x"43", + 4959 => x"83", + 4960 => x"66", + 4961 => x"60", + 4962 => x"90", + 4963 => x"31", + 4964 => x"80", + 4965 => x"8a", + 4966 => x"56", + 4967 => x"26", + 4968 => x"77", + 4969 => x"81", + 4970 => x"74", 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x"05", + 5030 => x"83", + 5031 => x"2a", + 5032 => x"a0", + 5033 => x"7d", + 5034 => x"69", + 5035 => x"05", + 5036 => x"72", + 5037 => x"5c", + 5038 => x"59", + 5039 => x"2e", + 5040 => x"89", + 5041 => x"60", + 5042 => x"84", + 5043 => x"5d", + 5044 => x"18", + 5045 => x"68", + 5046 => x"74", + 5047 => x"af", + 5048 => x"31", + 5049 => x"53", + 5050 => x"52", + 5051 => x"87", + 5052 => x"c0", + 5053 => x"83", + 5054 => x"06", + 5055 => x"de", + 5056 => x"ff", + 5057 => x"dd", + 5058 => x"83", + 5059 => x"2a", + 5060 => x"be", + 5061 => x"39", + 5062 => x"09", + 5063 => x"c5", + 5064 => x"f5", + 5065 => x"c0", + 5066 => x"38", + 5067 => x"79", + 5068 => x"80", + 5069 => x"38", + 5070 => x"96", + 5071 => x"06", + 5072 => x"2e", + 5073 => x"5e", + 5074 => x"81", + 5075 => x"9f", + 5076 => x"38", + 5077 => x"38", + 5078 => x"81", + 5079 => x"fc", + 5080 => x"ab", + 5081 => x"7d", + 5082 => x"81", + 5083 => x"7d", + 5084 => x"78", + 5085 => x"74", + 5086 => x"8e", + 5087 => x"9c", + 5088 => x"53", + 5089 => x"51", + 5090 => x"3f", + 5091 => x"cc", + 5092 => x"51", + 5093 => x"3f", + 5094 => x"8b", + 5095 => x"a1", + 5096 => x"8d", + 5097 => x"83", + 5098 => x"52", + 5099 => x"ff", + 5100 => x"81", + 5101 => x"34", + 5102 => x"70", + 5103 => x"2a", + 5104 => x"54", + 5105 => x"1b", + 5106 => x"88", + 5107 => x"74", + 5108 => x"26", + 5109 => x"83", + 5110 => x"52", + 5111 => x"ff", + 5112 => x"8a", + 5113 => x"a0", + 5114 => x"a1", + 5115 => x"0b", + 5116 => x"bf", + 5117 => x"51", + 5118 => x"3f", + 5119 => x"9a", + 5120 => x"a0", + 5121 => x"52", + 5122 => x"ff", + 5123 => x"7d", + 5124 => x"81", + 5125 => x"38", + 5126 => x"0a", + 5127 => x"1b", + 5128 => x"ce", + 5129 => x"a4", + 5130 => x"a0", + 5131 => x"52", + 5132 => x"ff", + 5133 => x"81", + 5134 => x"51", + 5135 => x"3f", + 5136 => x"1b", + 5137 => x"8c", + 5138 => x"0b", + 5139 => x"34", + 5140 => x"c2", + 5141 => x"53", + 5142 => x"52", + 5143 => x"51", + 5144 => x"88", + 5145 => x"a7", + 5146 => x"a0", + 5147 => x"83", + 5148 => x"52", + 5149 => x"ff", + 5150 => x"ff", + 5151 => x"1c", + 5152 => x"a6", + 5153 => x"53", + 5154 => x"52", + 5155 => x"ff", + 5156 => x"82", + 5157 => x"83", + 5158 => x"52", + 5159 => x"b4", + 5160 => x"60", + 5161 => x"7e", + 5162 => x"d7", + 5163 => x"81", + 5164 => x"83", + 5165 => x"83", + 5166 => x"06", + 5167 => x"75", + 5168 => x"05", + 5169 => x"7e", + 5170 => x"b7", + 5171 => x"53", + 5172 => x"51", + 5173 => x"3f", + 5174 => x"a4", + 5175 => x"51", + 5176 => x"3f", + 5177 => x"e4", + 5178 => x"e4", + 5179 => x"9f", + 5180 => x"18", + 5181 => x"1b", + 5182 => x"f6", + 5183 => x"83", + 5184 => x"ff", + 5185 => x"82", + 5186 => x"78", + 5187 => x"c4", + 5188 => x"60", + 5189 => x"7a", + 5190 => x"ff", + 5191 => x"75", + 5192 => x"53", + 5193 => x"51", + 5194 => x"3f", + 5195 => x"52", + 5196 => x"9f", + 5197 => x"56", + 5198 => x"83", + 5199 => x"06", + 5200 => x"52", + 5201 => x"9e", + 5202 => x"52", + 5203 => x"ff", + 5204 => x"f0", + 5205 => x"1b", + 5206 => x"87", + 5207 => x"55", + 5208 => x"83", + 5209 => x"74", + 5210 => x"ff", + 5211 => x"7c", + 5212 => x"74", + 5213 => x"38", + 5214 => x"54", + 5215 => x"52", + 5216 => x"99", + 5217 => x"de", + 5218 => x"87", + 5219 => x"53", + 5220 => x"08", + 5221 => x"ff", + 5222 => x"76", + 5223 => x"31", + 5224 => x"cd", + 5225 => x"58", + 5226 => x"ff", + 5227 => x"55", + 5228 => x"83", + 5229 => x"61", + 5230 => x"26", + 5231 => x"57", + 5232 => x"53", + 5233 => x"51", + 5234 => x"3f", + 5235 => x"08", + 5236 => x"76", + 5237 => x"31", + 5238 => x"db", + 5239 => x"7d", + 5240 => x"38", + 5241 => x"83", + 5242 => x"8a", + 5243 => x"7d", + 5244 => x"38", + 5245 => x"81", + 5246 => x"80", + 5247 => x"80", + 5248 => x"7a", + 5249 => x"bc", + 5250 => x"d5", + 5251 => x"ff", + 5252 => x"83", + 5253 => x"77", + 5254 => x"0b", + 5255 => x"81", + 5256 => x"34", + 5257 => x"34", + 5258 => x"34", + 5259 => x"56", + 5260 => x"52", + 5261 => x"ee", + 5262 => x"0b", + 5263 => x"81", + 5264 => x"82", + 5265 => x"56", + 5266 => x"34", + 5267 => x"08", + 5268 => x"60", + 5269 => x"1b", + 5270 => x"96", + 5271 => x"83", + 5272 => x"ff", + 5273 => x"81", + 5274 => x"7a", + 5275 => x"ff", + 5276 => x"81", + 5277 => x"c0", + 5278 => x"80", + 5279 => x"7e", + 5280 => x"e3", + 5281 => x"81", + 5282 => x"90", + 5283 => x"8e", + 5284 => x"81", + 5285 => x"81", + 5286 => x"56", + 5287 => x"c0", + 5288 => x"0d", + 5289 => x"0d", + 5290 => x"59", + 5291 => x"ff", + 5292 => x"57", + 5293 => x"b4", + 5294 => x"f8", + 5295 => x"81", + 5296 => x"52", + 5297 => x"dc", + 5298 => x"2e", + 5299 => x"9c", + 5300 => x"33", + 5301 => x"2e", + 5302 => x"76", + 5303 => x"58", + 5304 => x"57", + 5305 => x"09", + 5306 => x"38", + 5307 => x"78", + 5308 => x"38", + 5309 => x"81", + 5310 => x"8d", + 5311 => x"ff", + 5312 => x"52", + 5313 => x"81", + 5314 => x"84", + 5315 => x"94", + 5316 => x"08", + 5317 => x"f0", + 5318 => x"39", + 5319 => x"51", + 5320 => x"81", + 5321 => x"80", + 5322 => x"d0", + 5323 => x"eb", + 5324 => x"b4", + 5325 => x"39", + 5326 => x"51", + 5327 => x"81", + 5328 => x"80", + 5329 => x"d0", + 5330 => x"cf", + 5331 => x"80", + 5332 => x"39", + 5333 => x"51", + 5334 => x"81", + 5335 => x"bb", + 5336 => x"cc", + 5337 => x"81", + 5338 => x"af", + 5339 => x"8c", + 5340 => x"81", + 5341 => x"a3", + 5342 => x"c0", + 5343 => x"81", + 5344 => x"97", + 5345 => x"ec", + 5346 => x"81", + 5347 => x"8b", + 5348 => x"9c", + 5349 => x"81", + 5350 => x"ff", + 5351 => x"83", + 5352 => x"fb", + 5353 => x"79", + 5354 => x"87", + 5355 => x"38", + 5356 => x"87", + 5357 => x"91", + 5358 => x"52", + 5359 => x"eb", + 5360 => x"de", + 5361 => x"75", + 5362 => x"ab", + 5363 => x"c0", + 5364 => x"53", + 5365 => x"d3", + 5366 => x"8c", + 5367 => x"3d", + 5368 => x"3d", + 5369 => x"61", + 5370 => x"80", + 5371 => x"73", + 5372 => x"5f", + 5373 => x"5c", + 5374 => x"52", + 5375 => x"51", + 5376 => x"3f", + 5377 => x"51", + 5378 => x"3f", + 5379 => x"77", + 5380 => x"38", + 5381 => x"89", + 5382 => x"2e", + 5383 => x"c6", + 5384 => x"53", + 5385 => x"8e", + 5386 => x"52", + 5387 => x"51", + 5388 => x"3f", + 5389 => x"d3", + 5390 => x"86", + 5391 => x"15", + 5392 => x"39", + 5393 => x"72", + 5394 => x"38", + 5395 => x"81", + 5396 => x"ff", + 5397 => x"89", + 5398 => x"f0", + 5399 => x"df", + 5400 => x"55", + 5401 => x"16", + 5402 => x"27", + 5403 => x"33", + 5404 => x"fc", + 5405 => x"ab", + 5406 => x"81", + 5407 => x"ff", + 5408 => x"81", + 5409 => x"51", + 5410 => x"3f", + 5411 => x"81", + 5412 => x"ff", + 5413 => x"80", + 5414 => x"27", + 5415 => x"16", + 5416 => x"72", + 5417 => x"53", + 5418 => x"90", + 5419 => x"2e", + 5420 => x"80", + 5421 => x"38", + 5422 => x"39", + 5423 => x"f5", + 5424 => x"15", + 5425 => x"81", + 5426 => x"ff", + 5427 => x"76", + 5428 => x"5a", + 5429 => x"b4", + 5430 => x"c0", + 5431 => x"70", + 5432 => x"55", + 5433 => x"09", + 5434 => x"38", + 5435 => x"3f", + 5436 => x"08", + 5437 => x"98", + 5438 => x"32", + 5439 => x"72", + 5440 => x"51", + 5441 => x"55", + 5442 => x"8c", + 5443 => x"38", + 5444 => x"09", + 5445 => x"38", + 5446 => x"39", + 5447 => x"72", + 5448 => x"d6", + 5449 => x"72", + 5450 => x"0c", + 5451 => x"04", + 5452 => x"66", + 5453 => x"80", + 5454 => x"69", + 5455 => x"74", + 5456 => x"70", + 5457 => x"27", + 5458 => x"58", + 5459 => x"93", + 5460 => x"fc", + 5461 => x"75", + 5462 => x"70", + 5463 => x"bf", + 5464 => x"de", + 5465 => x"81", + 5466 => x"b8", + 5467 => x"c0", + 5468 => x"98", + 5469 => x"de", + 5470 => x"96", + 5471 => x"54", + 5472 => x"77", + 5473 => x"c4", + 5474 => x"de", + 5475 => x"81", + 5476 => x"90", + 5477 => x"74", + 5478 => x"38", + 5479 => x"19", + 5480 => x"39", + 5481 => x"05", + 5482 => x"3f", + 5483 => x"77", + 5484 => x"51", + 5485 => x"2e", + 5486 => x"80", + 5487 => x"81", + 5488 => x"87", + 5489 => x"08", + 5490 => x"fb", + 5491 => x"57", + 5492 => x"c0", + 5493 => x"0d", + 5494 => x"0d", + 5495 => x"05", + 5496 => x"57", + 5497 => x"80", + 5498 => x"79", + 5499 => x"3f", + 5500 => x"08", + 5501 => x"80", + 5502 => x"75", + 5503 => x"38", + 5504 => x"55", + 5505 => x"de", + 5506 => x"52", + 5507 => x"2d", + 5508 => x"08", + 5509 => x"77", + 5510 => x"de", + 5511 => x"3d", + 5512 => x"3d", + 5513 => x"05", + 5514 => x"98", + 5515 => x"a0", + 5516 => x"87", + 5517 => x"db", + 5518 => x"ff", + 5519 => x"81", + 5520 => x"81", + 5521 => x"81", + 5522 => x"52", + 5523 => x"51", + 5524 => x"3f", + 5525 => x"85", + 5526 => x"d4", + 5527 => x"0d", + 5528 => x"0d", + 5529 => x"80", + 5530 => x"80", + 5531 => x"51", + 5532 => x"3f", + 5533 => x"51", + 5534 => x"3f", + 5535 => x"f2", + 5536 => x"81", + 5537 => x"06", + 5538 => x"80", + 5539 => x"81", + 5540 => x"8c", + 5541 => x"f8", + 5542 => x"84", + 5543 => x"fe", + 5544 => x"72", + 5545 => x"81", + 5546 => x"71", + 5547 => x"38", + 5548 => x"f1", + 5549 => x"d5", + 5550 => x"f3", + 5551 => x"51", + 5552 => x"3f", + 5553 => x"70", + 5554 => x"52", + 5555 => x"95", + 5556 => x"fe", + 5557 => x"81", + 5558 => x"fe", + 5559 => x"80", + 5560 => x"bc", + 5561 => x"2a", + 5562 => x"51", + 5563 => x"2e", + 5564 => x"51", + 5565 => x"3f", + 5566 => x"51", + 5567 => x"3f", + 5568 => x"f1", + 5569 => x"85", + 5570 => x"06", + 5571 => x"80", + 5572 => x"81", + 5573 => x"88", + 5574 => x"c4", + 5575 => x"80", + 5576 => x"fe", + 5577 => x"72", + 5578 => x"81", + 5579 => x"71", + 5580 => x"38", + 5581 => x"f0", + 5582 => x"d5", + 5583 => x"f2", + 5584 => x"51", + 5585 => x"3f", + 5586 => x"70", + 5587 => x"52", + 5588 => x"95", + 5589 => x"fe", + 5590 => x"81", + 5591 => x"fe", + 5592 => x"80", + 5593 => x"b8", + 5594 => x"2a", + 5595 => x"51", + 5596 => x"2e", + 5597 => x"51", + 5598 => x"3f", + 5599 => x"51", + 5600 => x"3f", + 5601 => x"f0", + 5602 => x"fe", + 5603 => x"3d", + 5604 => x"3d", + 5605 => x"08", + 5606 => x"57", + 5607 => x"80", + 5608 => x"39", + 5609 => x"85", + 5610 => x"80", + 5611 => x"14", + 5612 => x"33", + 5613 => x"06", + 5614 => x"74", + 5615 => x"38", + 5616 => x"80", + 5617 => x"72", + 5618 => x"81", + 5619 => x"72", + 5620 => x"81", + 5621 => x"80", + 5622 => x"05", + 5623 => x"56", + 5624 => x"81", + 5625 => x"77", + 5626 => x"08", + 5627 => x"ea", + 5628 => x"de", + 5629 => x"38", + 5630 => x"53", + 5631 => x"ff", + 5632 => x"16", + 5633 => x"06", + 5634 => x"76", + 5635 => x"ff", + 5636 => x"de", + 5637 => x"3d", + 5638 => x"3d", + 5639 => x"70", + 5640 => x"80", + 5641 => x"fe", + 5642 => x"81", + 5643 => x"54", + 5644 => x"81", + 5645 => x"c0", + 5646 => x"c4", + 5647 => x"ff", + 5648 => x"c0", + 5649 => x"81", + 5650 => x"07", + 5651 => x"71", + 5652 => x"54", + 5653 => x"ec", + 5654 => x"ec", + 5655 => x"81", + 5656 => x"06", + 5657 => x"f5", + 5658 => x"52", + 5659 => x"b5", + 5660 => x"c0", + 5661 => x"8c", + 5662 => x"c0", + 5663 => x"fd", + 5664 => x"39", + 5665 => x"51", + 5666 => x"82", + 5667 => x"ec", + 5668 => x"ec", + 5669 => x"82", + 5670 => x"06", + 5671 => x"52", + 5672 => x"83", + 5673 => x"0b", + 5674 => x"0c", + 5675 => x"04", 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x"d5", + 5735 => x"78", + 5736 => x"8d", + 5737 => x"80", + 5738 => x"38", + 5739 => x"2e", + 5740 => x"8e", + 5741 => x"80", + 5742 => x"a1", + 5743 => x"d4", + 5744 => x"38", + 5745 => x"78", + 5746 => x"8e", + 5747 => x"81", + 5748 => x"38", + 5749 => x"2e", + 5750 => x"78", + 5751 => x"8d", + 5752 => x"cf", + 5753 => x"83", + 5754 => x"38", + 5755 => x"2e", + 5756 => x"8e", + 5757 => x"3d", + 5758 => x"53", + 5759 => x"51", + 5760 => x"3f", + 5761 => x"08", + 5762 => x"d7", + 5763 => x"a7", + 5764 => x"fe", + 5765 => x"fe", + 5766 => x"ff", + 5767 => x"81", + 5768 => x"80", + 5769 => x"81", + 5770 => x"38", + 5771 => x"80", + 5772 => x"52", + 5773 => x"05", + 5774 => x"85", + 5775 => x"de", + 5776 => x"ff", + 5777 => x"8e", + 5778 => x"a0", + 5779 => x"ef", + 5780 => x"fd", + 5781 => x"d7", + 5782 => x"a8", + 5783 => x"fe", + 5784 => x"fe", + 5785 => x"ff", + 5786 => x"81", + 5787 => x"80", + 5788 => x"38", + 5789 => x"52", + 5790 => x"05", + 5791 => x"89", + 5792 => x"de", + 5793 => x"81", + 5794 => x"8c", + 5795 => x"3d", + 5796 => x"53", + 5797 => x"51", + 5798 => x"3f", + 5799 => x"08", + 5800 => x"38", + 5801 => x"fc", + 5802 => x"3d", + 5803 => x"53", + 5804 => x"51", + 5805 => x"3f", + 5806 => x"08", + 5807 => x"de", + 5808 => x"63", + 5809 => x"d0", + 5810 => x"fe", + 5811 => x"02", + 5812 => x"33", + 5813 => x"63", + 5814 => x"81", + 5815 => x"51", + 5816 => x"3f", + 5817 => x"08", + 5818 => x"81", + 5819 => x"fe", + 5820 => x"81", + 5821 => x"39", + 5822 => x"f8", + 5823 => x"e5", + 5824 => x"de", + 5825 => x"3d", + 5826 => x"52", + 5827 => x"a3", + 5828 => x"81", + 5829 => x"52", + 5830 => x"94", + 5831 => x"39", + 5832 => x"f8", + 5833 => x"e5", + 5834 => x"de", + 5835 => x"3d", + 5836 => x"52", + 5837 => x"fb", + 5838 => x"c0", + 5839 => x"fe", + 5840 => x"5a", + 5841 => x"3f", + 5842 => x"08", + 5843 => x"f8", + 5844 => x"fe", + 5845 => x"81", + 5846 => x"81", + 5847 => x"80", + 5848 => x"81", + 5849 => x"81", + 5850 => x"78", + 5851 => x"7a", + 5852 => x"3f", + 5853 => x"08", + 5854 => x"84", + 5855 => x"c0", + 5856 => x"fb", + 5857 => x"39", + 5858 => x"f4", + 5859 => x"f8", + 5860 => x"ff", + 5861 => x"de", + 5862 => x"2e", + 5863 => x"b7", + 5864 => x"11", + 5865 => x"05", + 5866 => x"ec", + 5867 => x"c0", + 5868 => x"fa", + 5869 => x"3d", + 5870 => x"53", + 5871 => x"51", + 5872 => x"3f", + 5873 => x"08", + 5874 => x"de", + 5875 => x"81", + 5876 => x"fe", + 5877 => x"63", + 5878 => x"79", + 5879 => x"e6", + 5880 => x"78", + 5881 => x"05", + 5882 => x"7a", + 5883 => x"88", + 5884 => x"3d", + 5885 => x"53", + 5886 => x"51", + 5887 => x"3f", + 5888 => x"08", + 5889 => x"81", + 5890 => x"59", + 5891 => x"89", + 5892 => x"8c", + 5893 => x"cd", + 5894 => x"d5", + 5895 => x"80", + 5896 => x"81", + 5897 => x"44", + 5898 => x"db", + 5899 => x"78", + 5900 => x"38", + 5901 => x"08", + 5902 => x"81", + 5903 => x"59", + 5904 => x"88", + 5905 => x"a4", + 5906 => x"39", + 5907 => x"33", + 5908 => x"2e", + 5909 => x"db", + 5910 => x"89", + 5911 => x"bc", + 5912 => x"05", + 5913 => x"fe", + 5914 => x"fe", + 5915 => x"fe", + 5916 => x"81", + 5917 => x"80", + 5918 => x"db", + 5919 => x"78", + 5920 => x"38", + 5921 => x"08", + 5922 => x"39", + 5923 => x"33", + 5924 => x"2e", + 5925 => x"db", + 5926 => x"bb", + 5927 => x"d6", + 5928 => x"80", + 5929 => x"81", + 5930 => x"43", + 5931 => x"db", + 5932 => x"78", + 5933 => x"38", + 5934 => x"08", + 5935 => x"81", + 5936 => x"59", + 5937 => x"88", + 5938 => x"b0", + 5939 => x"39", + 5940 => x"08", + 5941 => x"b7", + 5942 => x"11", + 5943 => x"05", + 5944 => x"b4", + 5945 => x"c0", + 5946 => x"9b", + 5947 => x"5b", + 5948 => x"2e", + 5949 => x"59", + 5950 => x"8d", + 5951 => x"2e", + 5952 => x"a0", + 5953 => x"88", + 5954 => x"e4", + 5955 => x"af", + 5956 => x"63", + 5957 => x"62", + 5958 => x"ed", + 5959 => x"d7", + 5960 => x"e0", + 5961 => x"fe", + 5962 => x"fe", + 5963 => x"fe", + 5964 => x"81", + 5965 => x"80", + 5966 => x"38", + 5967 => x"f0", + 5968 => x"f8", + 5969 => x"fb", + 5970 => x"de", + 5971 => x"2e", + 5972 => x"59", + 5973 => x"05", + 5974 => x"63", + 5975 => x"b7", + 5976 => x"11", + 5977 => x"05", + 5978 => x"ac", + 5979 => x"c0", + 5980 => x"f7", + 5981 => x"70", + 5982 => x"81", + 5983 => x"fe", + 5984 => x"80", + 5985 => x"51", + 5986 => x"3f", + 5987 => x"33", + 5988 => x"2e", + 5989 => x"9f", + 5990 => x"38", + 5991 => x"f0", + 5992 => x"f8", + 5993 => x"fa", + 5994 => x"de", + 5995 => x"2e", + 5996 => x"59", + 5997 => x"05", + 5998 => x"63", + 5999 => x"ff", + 6000 => x"d8", + 6001 => x"f2", + 6002 => x"aa", + 6003 => x"fe", + 6004 => x"fe", + 6005 => x"fe", + 6006 => x"81", + 6007 => x"80", + 6008 => x"38", + 6009 => x"e4", + 6010 => x"f8", + 6011 => x"fc", + 6012 => x"de", + 6013 => x"2e", + 6014 => x"59", + 6015 => x"22", + 6016 => x"05", + 6017 => x"41", + 6018 => x"e4", + 6019 => x"f8", + 6020 => x"fb", + 6021 => x"de", + 6022 => x"38", + 6023 => x"60", + 6024 => x"52", + 6025 => x"51", + 6026 => x"3f", + 6027 => x"79", + 6028 => x"c9", + 6029 => x"79", + 6030 => x"ae", + 6031 => x"38", + 6032 => x"87", + 6033 => x"05", + 6034 => x"b7", + 6035 => x"11", + 6036 => x"05", + 6037 => x"b2", + 6038 => x"c0", + 6039 => x"92", + 6040 => x"02", + 6041 => x"79", + 6042 => x"5b", + 6043 => x"ff", + 6044 => x"d8", + 6045 => x"f1", + 6046 => x"a3", + 6047 => x"fe", + 6048 => x"fe", + 6049 => x"fe", + 6050 => x"81", + 6051 => x"80", + 6052 => x"38", + 6053 => x"e4", + 6054 => x"f8", + 6055 => x"fa", + 6056 => x"de", + 6057 => x"2e", + 6058 => x"60", + 6059 => x"60", + 6060 => x"b7", + 6061 => x"11", + 6062 => x"05", + 6063 => x"ca", + 6064 => x"c0", + 6065 => x"f4", + 6066 => x"70", + 6067 => x"81", + 6068 => x"fe", + 6069 => x"80", + 6070 => x"51", + 6071 => x"3f", + 6072 => x"33", + 6073 => x"2e", + 6074 => x"9f", + 6075 => x"38", + 6076 => x"e4", + 6077 => x"f8", + 6078 => x"fa", + 6079 => x"de", + 6080 => x"2e", + 6081 => x"60", + 6082 => x"60", + 6083 => x"ff", + 6084 => x"d8", + 6085 => x"f0", + 6086 => x"ae", + 6087 => x"fe", + 6088 => x"fe", + 6089 => x"fe", + 6090 => x"81", + 6091 => x"80", + 6092 => x"db", + 6093 => x"78", + 6094 => x"38", + 6095 => x"08", + 6096 => x"39", + 6097 => x"33", + 6098 => x"2e", + 6099 => x"db", + 6100 => x"bc", + 6101 => x"d6", + 6102 => x"80", + 6103 => x"81", + 6104 => x"44", + 6105 => x"db", + 6106 => x"78", + 6107 => x"38", + 6108 => x"08", + 6109 => x"81", + 6110 => x"59", + 6111 => x"88", + 6112 => x"ac", + 6113 => x"39", + 6114 => x"08", + 6115 => x"44", + 6116 => x"f0", + 6117 => x"f8", + 6118 => x"f6", + 6119 => x"de", + 6120 => x"de", + 6121 => x"d4", + 6122 => x"80", + 6123 => x"81", + 6124 => x"43", + 6125 => x"81", + 6126 => x"59", + 6127 => x"88", + 6128 => x"98", + 6129 => x"39", + 6130 => x"33", + 6131 => x"2e", + 6132 => x"db", + 6133 => x"aa", + 6134 => x"d7", + 6135 => x"80", + 6136 => x"81", + 6137 => x"43", + 6138 => x"db", + 6139 => x"78", + 6140 => x"38", + 6141 => x"08", + 6142 => x"81", + 6143 => x"88", + 6144 => x"3d", + 6145 => x"53", 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x"de", + 6205 => x"81", + 6206 => x"80", + 6207 => x"38", + 6208 => x"08", + 6209 => x"dc", + 6210 => x"97", + 6211 => x"39", + 6212 => x"51", + 6213 => x"3f", + 6214 => x"3f", + 6215 => x"81", + 6216 => x"fe", + 6217 => x"80", + 6218 => x"39", + 6219 => x"3f", + 6220 => x"64", + 6221 => x"59", + 6222 => x"ef", + 6223 => x"80", + 6224 => x"38", + 6225 => x"06", + 6226 => x"80", + 6227 => x"38", + 6228 => x"f8", + 6229 => x"d8", + 6230 => x"de", + 6231 => x"5d", + 6232 => x"2e", + 6233 => x"82", + 6234 => x"7b", + 6235 => x"38", + 6236 => x"7b", + 6237 => x"38", + 6238 => x"81", + 6239 => x"7a", + 6240 => x"ac", + 6241 => x"81", + 6242 => x"b7", + 6243 => x"05", + 6244 => x"a5", + 6245 => x"81", + 6246 => x"b7", + 6247 => x"05", + 6248 => x"95", + 6249 => x"7a", + 6250 => x"ac", + 6251 => x"81", + 6252 => x"b7", + 6253 => x"05", + 6254 => x"fd", + 6255 => x"7a", + 6256 => x"81", + 6257 => x"b7", + 6258 => x"05", + 6259 => x"e9", + 6260 => x"8c", + 6261 => x"f4", + 6262 => x"64", + 6263 => x"81", + 6264 => x"54", + 6265 => x"53", + 6266 => x"52", + 6267 => x"b0", + 6268 => x"e5", + 6269 => x"c0", + 6270 => x"c0", + 6271 => x"30", + 6272 => x"80", + 6273 => x"5b", + 6274 => x"26", + 6275 => x"80", + 6276 => x"81", + 6277 => x"ff", + 6278 => x"7b", + 6279 => x"7e", + 6280 => x"81", + 6281 => x"78", + 6282 => x"ff", + 6283 => x"06", + 6284 => x"81", + 6285 => x"fe", + 6286 => x"ed", + 6287 => x"3d", + 6288 => x"81", + 6289 => x"87", + 6290 => x"70", + 6291 => x"87", + 6292 => x"72", + 6293 => x"9f", + 6294 => x"c0", + 6295 => x"75", + 6296 => x"87", + 6297 => x"73", + 6298 => x"8b", + 6299 => x"de", + 6300 => x"75", + 6301 => x"94", + 6302 => x"54", + 6303 => x"80", + 6304 => x"fe", + 6305 => x"81", + 6306 => x"90", + 6307 => x"55", + 6308 => x"80", + 6309 => x"fe", + 6310 => x"72", + 6311 => x"08", + 6312 => x"8c", + 6313 => x"87", + 6314 => x"0c", + 6315 => x"0b", + 6316 => x"94", + 6317 => x"0b", + 6318 => x"0c", + 6319 => x"81", + 6320 => x"fe", + 6321 => x"fe", + 6322 => x"81", + 6323 => x"fe", + 6324 => x"81", + 6325 => x"fe", + 6326 => x"81", + 6327 => x"fe", + 6328 => x"81", + 6329 => x"3f", + 6330 => x"80", + 6331 => x"00", + 6332 => x"ff", + 6333 => x"ff", + 6334 => x"ff", + 6335 => x"00", + 6336 => x"61", + 6337 => x"67", + 6338 => x"6d", + 6339 => x"73", + 6340 => x"79", + 6341 => x"91", + 6342 => x"15", + 6343 => x"1c", + 6344 => x"23", + 6345 => x"2a", + 6346 => x"31", + 6347 => x"38", + 6348 => x"3f", + 6349 => x"46", + 6350 => x"4d", + 6351 => x"54", + 6352 => x"5b", + 6353 => x"61", + 6354 => x"67", + 6355 => x"6d", + 6356 => x"73", + 6357 => x"79", + 6358 => x"7f", + 6359 => x"85", + 6360 => x"8b", + 6361 => x"25", + 6362 => x"64", + 6363 => x"3a", + 6364 => x"25", + 6365 => x"64", + 6366 => x"00", + 6367 => x"20", + 6368 => x"66", + 6369 => x"72", + 6370 => x"6f", + 6371 => x"00", + 6372 => x"72", + 6373 => x"53", + 6374 => x"63", + 6375 => x"69", + 6376 => x"00", + 6377 => x"65", + 6378 => x"65", + 6379 => x"6d", + 6380 => x"6d", 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x"3d", + 6440 => x"64", + 6441 => x"00", + 6442 => x"20", + 6443 => x"48", + 6444 => x"45", + 6445 => x"53", + 6446 => x"00", + 6447 => x"20", + 6448 => x"49", + 6449 => x"00", + 6450 => x"20", + 6451 => x"54", + 6452 => x"00", + 6453 => x"20", + 6454 => x"0a", + 6455 => x"00", + 6456 => x"20", + 6457 => x"0a", + 6458 => x"00", + 6459 => x"72", + 6460 => x"65", + 6461 => x"00", + 6462 => x"20", + 6463 => x"20", + 6464 => x"65", + 6465 => x"65", + 6466 => x"72", + 6467 => x"64", + 6468 => x"73", + 6469 => x"25", + 6470 => x"0a", + 6471 => x"00", + 6472 => x"20", + 6473 => x"20", + 6474 => x"6f", + 6475 => x"53", + 6476 => x"74", + 6477 => x"64", + 6478 => x"73", + 6479 => x"25", + 6480 => x"0a", + 6481 => x"00", + 6482 => x"20", + 6483 => x"63", + 6484 => x"74", + 6485 => x"20", + 6486 => x"72", + 6487 => x"20", + 6488 => x"20", + 6489 => x"25", + 6490 => x"0a", + 6491 => x"00", + 6492 => x"63", + 6493 => x"00", + 6494 => x"20", + 6495 => x"20", + 6496 => x"20", + 6497 => x"20", + 6498 => x"20", + 6499 => x"20", + 6500 => x"20", + 6501 => x"25", + 6502 => x"0a", + 6503 => x"00", + 6504 => x"20", + 6505 => x"74", + 6506 => x"43", + 6507 => x"6b", + 6508 => x"65", + 6509 => x"20", + 6510 => x"20", + 6511 => x"25", + 6512 => x"30", + 6513 => x"48", + 6514 => x"00", + 6515 => x"20", + 6516 => x"41", + 6517 => x"6c", + 6518 => x"20", + 6519 => x"71", + 6520 => x"20", + 6521 => x"20", + 6522 => x"25", + 6523 => x"30", + 6524 => x"48", + 6525 => x"00", + 6526 => x"20", + 6527 => x"68", + 6528 => x"65", + 6529 => x"52", + 6530 => x"43", + 6531 => x"6b", + 6532 => x"65", + 6533 => x"25", + 6534 => x"30", + 6535 => x"48", + 6536 => x"00", + 6537 => x"6c", + 6538 => x"00", + 6539 => x"69", + 6540 => x"00", + 6541 => x"78", + 6542 => x"00", + 6543 => x"00", + 6544 => x"6d", + 6545 => x"00", + 6546 => x"6e", + 6547 => x"00", + 6548 => x"00", + 6549 => x"2c", + 6550 => x"3d", + 6551 => x"5d", + 6552 => x"00", + 6553 => x"00", + 6554 => x"33", + 6555 => x"00", + 6556 => x"4d", + 6557 => x"53", + 6558 => x"00", + 6559 => x"4e", + 6560 => x"20", + 6561 => x"46", + 6562 => x"32", + 6563 => x"00", + 6564 => x"4e", + 6565 => x"20", + 6566 => x"46", + 6567 => x"20", + 6568 => x"00", + 6569 => x"50", + 6570 => x"00", + 6571 => x"00", + 6572 => x"00", + 6573 => x"41", + 6574 => x"80", + 6575 => x"49", + 6576 => x"8f", + 6577 => x"4f", + 6578 => x"55", + 6579 => x"9b", + 6580 => x"9f", + 6581 => x"55", + 6582 => x"a7", + 6583 => x"ab", + 6584 => x"af", + 6585 => x"b3", + 6586 => x"b7", + 6587 => x"bb", + 6588 => x"bf", + 6589 => x"c3", + 6590 => x"c7", + 6591 => x"cb", + 6592 => x"cf", + 6593 => x"d3", + 6594 => x"d7", + 6595 => x"db", + 6596 => x"df", + 6597 => x"e3", + 6598 => x"e7", + 6599 => x"eb", + 6600 => x"ef", + 6601 => x"f3", + 6602 => x"f7", + 6603 => x"fb", + 6604 => x"ff", + 6605 => x"3b", + 6606 => x"2f", + 6607 => x"3a", + 6608 => x"7c", + 6609 => x"00", + 6610 => x"04", + 6611 => x"40", + 6612 => x"00", + 6613 => x"00", + 6614 => x"02", + 6615 => x"08", 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x"20", + 6675 => x"65", + 6676 => x"65", + 6677 => x"00", + 6678 => x"65", + 6679 => x"64", + 6680 => x"65", + 6681 => x"00", + 6682 => x"65", + 6683 => x"72", + 6684 => x"79", + 6685 => x"69", + 6686 => x"2e", + 6687 => x"00", + 6688 => x"65", + 6689 => x"6e", + 6690 => x"20", + 6691 => x"61", + 6692 => x"2e", + 6693 => x"00", + 6694 => x"69", + 6695 => x"72", + 6696 => x"20", + 6697 => x"74", + 6698 => x"65", + 6699 => x"00", + 6700 => x"76", + 6701 => x"75", + 6702 => x"72", + 6703 => x"20", + 6704 => x"61", + 6705 => x"2e", + 6706 => x"00", + 6707 => x"6b", + 6708 => x"74", + 6709 => x"61", + 6710 => x"64", + 6711 => x"00", + 6712 => x"63", + 6713 => x"61", + 6714 => x"6c", + 6715 => x"69", + 6716 => x"79", + 6717 => x"6d", + 6718 => x"75", + 6719 => x"6f", + 6720 => x"69", + 6721 => x"0a", + 6722 => x"00", + 6723 => x"6d", + 6724 => x"61", + 6725 => x"74", + 6726 => x"0a", + 6727 => x"00", + 6728 => x"65", + 6729 => x"2c", + 6730 => x"65", + 6731 => x"69", + 6732 => x"63", + 6733 => x"65", + 6734 => x"64", + 6735 => x"00", + 6736 => x"65", + 6737 => x"20", + 6738 => x"6b", + 6739 => x"0a", + 6740 => x"00", + 6741 => x"75", + 6742 => x"63", + 6743 => x"74", + 6744 => x"6d", + 6745 => x"2e", + 6746 => x"00", + 6747 => x"20", + 6748 => x"79", + 6749 => x"65", + 6750 => x"69", + 6751 => x"2e", + 6752 => x"00", + 6753 => x"61", + 6754 => x"65", + 6755 => x"69", + 6756 => x"72", + 6757 => x"74", + 6758 => x"00", + 6759 => x"63", + 6760 => x"2e", + 6761 => x"00", + 6762 => x"6e", + 6763 => x"20", + 6764 => x"6f", + 6765 => x"00", + 6766 => x"75", + 6767 => x"74", + 6768 => x"25", + 6769 => x"74", + 6770 => x"75", + 6771 => x"74", + 6772 => x"73", + 6773 => x"0a", + 6774 => x"00", + 6775 => x"58", + 6776 => x"00", + 6777 => x"00", + 6778 => x"58", + 6779 => x"00", + 6780 => x"20", + 6781 => x"20", + 6782 => x"00", + 6783 => x"58", + 6784 => x"00", + 6785 => x"00", + 6786 => x"00", + 6787 => x"00", + 6788 => x"64", + 6789 => x"00", + 6790 => x"54", + 6791 => x"00", + 6792 => x"20", + 6793 => x"28", + 6794 => x"00", + 6795 => x"31", + 6796 => x"30", + 6797 => x"00", + 6798 => x"34", + 6799 => x"00", + 6800 => x"55", + 6801 => x"65", + 6802 => x"30", + 6803 => x"20", + 6804 => x"25", + 6805 => x"2a", + 6806 => x"00", + 6807 => x"54", + 6808 => x"6e", + 6809 => x"72", + 6810 => x"20", + 6811 => x"64", + 6812 => x"0a", + 6813 => x"00", + 6814 => x"65", + 6815 => x"6e", + 6816 => x"72", + 6817 => x"0a", + 6818 => x"00", + 6819 => x"20", + 6820 => x"65", + 6821 => x"70", + 6822 => x"00", + 6823 => x"54", + 6824 => x"44", + 6825 => x"74", + 6826 => x"75", + 6827 => x"00", + 6828 => x"54", + 6829 => x"52", + 6830 => x"74", + 6831 => x"75", + 6832 => x"00", + 6833 => x"54", + 6834 => x"58", + 6835 => x"74", + 6836 => x"75", + 6837 => x"00", + 6838 => x"54", + 6839 => x"58", + 6840 => x"74", + 6841 => x"75", + 6842 => x"00", + 6843 => x"54", + 6844 => x"58", + 6845 => x"74", + 6846 => x"75", + 6847 => x"00", + 6848 => x"54", + 6849 => x"58", + 6850 => x"74", + 6851 => x"75", + 6852 => x"00", + 6853 => x"74", + 6854 => x"20", + 6855 => x"74", + 6856 => x"72", + 6857 => x"0a", + 6858 => x"00", + 6859 => x"62", + 6860 => x"67", + 6861 => x"6d", + 6862 => x"2e", + 6863 => x"00", + 6864 => x"6f", + 6865 => x"63", + 6866 => x"74", + 6867 => x"00", + 6868 => x"00", + 6869 => x"6c", + 6870 => x"74", + 6871 => x"6e", + 6872 => x"61", + 6873 => x"65", + 6874 => x"20", + 6875 => x"64", + 6876 => x"20", + 6877 => x"61", + 6878 => x"69", + 6879 => x"20", + 6880 => x"75", + 6881 => x"79", + 6882 => x"00", + 6883 => x"00", + 6884 => x"20", + 6885 => x"6b", + 6886 => x"21", + 6887 => x"00", + 6888 => x"74", + 6889 => x"69", + 6890 => x"2e", + 6891 => x"00", + 6892 => x"6c", + 6893 => x"74", + 6894 => x"6e", + 6895 => x"61", + 6896 => x"65", + 6897 => x"00", + 6898 => x"25", + 6899 => x"00", + 6900 => x"00", + 6901 => x"61", + 6902 => x"67", + 6903 => x"2e", + 6904 => x"00", + 6905 => x"70", + 6906 => x"6d", + 6907 => x"0a", + 6908 => x"00", + 6909 => x"6d", + 6910 => x"74", + 6911 => x"00", + 6912 => x"58", + 6913 => x"32", + 6914 => x"00", + 6915 => x"0a", + 6916 => x"00", + 6917 => x"58", + 6918 => x"34", + 6919 => x"00", + 6920 => x"58", + 6921 => x"38", + 6922 => x"00", + 6923 => x"72", + 6924 => x"6e", + 6925 => x"0a", + 6926 => x"00", + 6927 => x"6c", + 6928 => x"25", + 6929 => x"78", + 6930 => x"00", + 6931 => x"61", + 6932 => x"6e", + 6933 => x"6e", + 6934 => x"72", + 6935 => x"73", + 6936 => x"00", + 6937 => x"62", + 6938 => x"67", + 6939 => x"74", + 6940 => x"75", + 6941 => x"0a", + 6942 => x"00", + 6943 => x"61", + 6944 => x"64", + 6945 => x"72", + 6946 => x"69", + 6947 => x"00", + 6948 => x"62", + 6949 => x"67", + 6950 => x"72", + 6951 => x"69", + 6952 => x"00", + 6953 => x"63", + 6954 => x"6e", + 6955 => x"6f", + 6956 => x"40", + 6957 => x"38", + 6958 => x"2e", + 6959 => x"00", + 6960 => x"6c", + 6961 => x"20", + 6962 => x"65", + 6963 => x"25", + 6964 => x"20", + 6965 => x"0a", + 6966 => x"00", + 6967 => x"6c", + 6968 => x"74", + 6969 => x"65", + 6970 => x"6f", + 6971 => x"28", + 6972 => x"2e", + 6973 => x"00", + 6974 => x"74", + 6975 => x"69", + 6976 => x"61", + 6977 => x"69", + 6978 => x"69", + 6979 => x"2e", + 6980 => x"00", + 6981 => x"64", + 6982 => x"62", + 6983 => x"69", + 6984 => x"2e", + 6985 => x"00", + 6986 => x"00", + 6987 => x"00", + 6988 => x"5c", + 6989 => x"25", + 6990 => x"73", + 6991 => x"00", + 6992 => x"5c", + 6993 => x"25", + 6994 => x"00", + 6995 => x"5c", + 6996 => x"00", + 6997 => x"20", + 6998 => x"6d", + 6999 => x"2e", + 7000 => x"00", + 7001 => x"6e", + 7002 => x"2e", + 7003 => x"00", + 7004 => x"62", + 7005 => x"67", + 7006 => x"74", + 7007 => x"75", + 7008 => x"2e", + 7009 => x"00", + 7010 => x"00", + 7011 => x"00", + 7012 => x"ff", + 7013 => x"00", + 7014 => x"ff", + 7015 => x"00", + 7016 => x"ff", + 7017 => x"00", + 7018 => x"00", + 7019 => x"00", + 7020 => x"ff", + 7021 => x"00", + 7022 => x"00", + 7023 => x"00", + 7024 => x"00", + 7025 => x"00", + 7026 => x"00", + 7027 => x"00", + 7028 => x"00", + 7029 => x"01", + 7030 => x"01", + 7031 => x"01", + 7032 => x"00", + 7033 => x"00", + 7034 => x"00", + 7035 => x"00", + 7036 => x"68", + 7037 => x"00", + 7038 => x"00", + 7039 => x"00", + 7040 => x"70", + 7041 => x"00", + 7042 => x"00", + 7043 => x"00", + 7044 => x"78", + 7045 => x"00", + 7046 => x"00", + 7047 => x"00", + 7048 => x"80", + 7049 => x"00", + 7050 => x"00", + 7051 => x"00", + 7052 => x"88", + 7053 => x"00", + 7054 => x"00", + 7055 => x"00", + 7056 => x"90", + 7057 => x"00", + 7058 => x"00", + 7059 => x"00", + 7060 => x"98", + 7061 => x"00", + 7062 => x"00", + 7063 => x"00", + 7064 => x"a0", + 7065 => x"00", + 7066 => x"00", + 7067 => x"00", + 7068 => x"a8", + 7069 => x"00", + 7070 => x"00", + 7071 => x"00", + 7072 => x"ac", + 7073 => x"00", + 7074 => x"00", + 7075 => x"00", + 7076 => x"b0", + 7077 => x"00", + 7078 => x"00", + 7079 => x"00", + 7080 => x"b4", + 7081 => x"00", + 7082 => x"00", + 7083 => x"00", + 7084 => x"b8", + 7085 => x"00", + 7086 => x"00", + 7087 => x"00", + 7088 => x"bc", + 7089 => x"00", + 7090 => x"00", + 7091 => x"00", + 7092 => x"c0", + 7093 => x"00", + 7094 => x"00", + 7095 => x"00", + 7096 => x"c4", + 7097 => x"00", + 7098 => x"00", + 7099 => x"00", + 7100 => x"cc", + 7101 => x"00", + 7102 => x"00", + 7103 => x"00", + 7104 => x"d0", + 7105 => x"00", + 7106 => x"00", + 7107 => x"00", + 7108 => x"d8", + 7109 => x"00", + 7110 => x"00", + 7111 => x"00", + 7112 => x"e0", + 7113 => x"00", + 7114 => x"00", + 7115 => x"00", + 7116 => x"e8", + 7117 => x"00", + 7118 => x"00", + 7119 => x"00", + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + 0 => x"0b", + 1 => x"00", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"8c", + 9 => x"88", + 10 => x"90", + 11 => x"88", + 12 => x"00", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"06", + 17 => x"06", + 18 => x"82", + 19 => x"2a", + 20 => x"06", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"06", + 25 => x"ff", + 26 => x"09", + 27 => x"05", + 28 => x"09", + 29 => x"ff", + 30 => x"0b", + 31 => x"04", + 32 => x"81", + 33 => x"73", + 34 => x"09", + 35 => x"73", + 36 => x"81", + 37 => x"04", + 38 => x"00", + 39 => x"00", + 40 => x"24", + 41 => x"07", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"81", + 50 => x"05", + 51 => x"0a", + 52 => x"0a", + 53 => x"81", + 54 => x"53", + 55 => x"00", + 56 => x"26", + 57 => x"07", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"51", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"9f", + 89 => x"05", + 90 => x"92", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"2a", + 97 => x"06", + 98 => x"09", + 99 => x"ff", + 100 => x"53", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"53", + 105 => x"73", + 106 => x"81", + 107 => x"83", + 108 => x"07", + 109 => x"0c", + 110 => x"00", + 111 => x"00", + 112 => x"81", + 113 => x"09", + 114 => x"09", + 115 => x"06", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"81", + 121 => x"09", + 122 => x"09", + 123 => x"81", + 124 => x"04", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"81", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"09", + 137 => x"53", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"09", + 146 => x"51", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"06", + 153 => x"06", + 154 => x"83", + 155 => x"10", + 156 => x"06", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"06", + 161 => x"81", + 162 => x"83", + 163 => x"05", + 164 => x"0b", + 165 => x"04", + 166 => x"00", + 167 => x"00", + 168 => x"8c", + 169 => x"75", + 170 => x"0b", + 171 => x"50", + 172 => x"56", + 173 => x"0c", + 174 => x"04", + 175 => x"00", + 176 => x"8c", + 177 => x"75", + 178 => x"0b", + 179 => x"50", + 180 => x"56", + 181 => x"0c", + 182 => x"04", + 183 => x"00", + 184 => x"70", + 185 => x"06", + 186 => x"ff", + 187 => x"71", + 188 => x"72", + 189 => x"05", + 190 => x"51", + 191 => x"00", + 192 => x"70", + 193 => x"06", + 194 => x"06", + 195 => x"54", + 196 => x"09", + 197 => x"ff", + 198 => x"51", + 199 => x"00", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"05", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"05", + 233 => x"05", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"05", + 249 => x"53", + 250 => x"04", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"06", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"0b", + 265 => x"0b", + 266 => x"85", + 267 => x"0b", + 268 => x"0b", + 269 => x"a3", + 270 => x"0b", + 271 => x"0b", + 272 => x"c1", + 273 => x"0b", + 274 => x"0b", + 275 => x"df", + 276 => x"0b", + 277 => x"0b", + 278 => x"fd", + 279 => x"0b", + 280 => x"0b", + 281 => x"9b", + 282 => x"0b", + 283 => x"0b", + 284 => x"b9", + 285 => x"0b", + 286 => x"0b", + 287 => x"d7", + 288 => x"0b", + 289 => x"0b", + 290 => x"f5", + 291 => x"0b", + 292 => x"0b", + 293 => x"94", + 294 => x"0b", + 295 => x"0b", + 296 => x"b4", + 297 => x"0b", + 298 => x"0b", + 299 => x"d4", + 300 => x"0b", + 301 => x"0b", + 302 => x"f4", + 303 => x"0b", + 304 => x"0b", + 305 => x"94", + 306 => x"0b", + 307 => x"0b", + 308 => x"b4", + 309 => x"0b", + 310 => x"0b", + 311 => x"d4", + 312 => x"0b", + 313 => x"0b", + 314 => x"f4", + 315 => x"0b", + 316 => x"0b", + 317 => x"94", + 318 => x"0b", + 319 => x"0b", + 320 => x"b4", + 321 => x"0b", + 322 => x"0b", + 323 => x"d4", + 324 => x"0b", + 325 => x"0b", + 326 => x"f4", + 327 => x"0b", + 328 => x"0b", + 329 => x"94", + 330 => x"0b", + 331 => x"0b", + 332 => x"b2", + 333 => x"0b", + 334 => x"0b", + 335 => x"d0", + 336 => x"0b", + 337 => x"0b", + 338 => x"ee", + 339 => x"ff", + 340 => x"ff", + 341 => x"ff", + 342 => x"ff", + 343 => x"ff", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"8c", + 385 => x"de", + 386 => x"ae", + 387 => x"cc", + 388 => x"90", + 389 => x"cc", + 390 => x"2d", + 391 => x"08", + 392 => x"04", + 393 => x"0c", + 394 => x"81", + 395 => x"84", + 396 => x"81", + 397 => x"ae", + 398 => x"de", + 399 => x"80", + 400 => x"de", + 401 => x"fd", + 402 => x"cc", + 403 => x"90", + 404 => x"cc", + 405 => x"2d", + 406 => x"08", + 407 => x"04", + 408 => x"0c", + 409 => x"81", + 410 => x"84", + 411 => x"81", + 412 => x"b6", + 413 => x"de", + 414 => x"80", + 415 => x"de", + 416 => x"8a", + 417 => x"cc", + 418 => x"90", + 419 => x"cc", + 420 => x"2d", + 421 => x"08", + 422 => x"04", + 423 => x"0c", + 424 => x"81", + 425 => x"84", + 426 => x"81", + 427 => x"b4", + 428 => x"de", + 429 => x"80", + 430 => x"de", + 431 => x"bb", + 432 => x"cc", + 433 => x"90", + 434 => x"cc", + 435 => x"2d", + 436 => x"08", + 437 => x"04", + 438 => x"0c", + 439 => x"81", + 440 => x"84", + 441 => x"81", + 442 => x"9c", + 443 => x"de", + 444 => x"80", + 445 => x"de", + 446 => x"90", + 447 => x"cc", + 448 => x"90", + 449 => x"cc", + 450 => x"bf", + 451 => x"cc", + 452 => x"90", + 453 => x"cc", + 454 => x"b0", + 455 => x"cc", + 456 => x"90", + 457 => x"cc", + 458 => x"a4", + 459 => x"cc", + 460 => x"90", + 461 => x"cc", + 462 => x"a1", + 463 => x"cc", + 464 => x"90", + 465 => x"cc", + 466 => x"bf", + 467 => x"cc", + 468 => x"90", + 469 => x"cc", + 470 => x"9f", + 471 => x"cc", + 472 => x"90", + 473 => x"cc", + 474 => x"92", + 475 => x"cc", + 476 => x"90", + 477 => x"cc", + 478 => x"de", + 479 => x"cc", + 480 => x"90", + 481 => x"cc", + 482 => x"fd", + 483 => x"cc", + 484 => x"90", + 485 => x"cc", + 486 => x"9c", + 487 => x"cc", + 488 => x"90", + 489 => x"cc", + 490 => x"86", + 491 => x"cc", + 492 => x"90", + 493 => x"cc", + 494 => x"ec", + 495 => x"cc", + 496 => x"90", + 497 => x"cc", + 498 => x"da", + 499 => x"cc", + 500 => x"90", + 501 => x"cc", + 502 => x"a0", + 503 => x"cc", + 504 => x"90", + 505 => x"cc", + 506 => x"da", + 507 => x"cc", + 508 => x"90", + 509 => x"cc", + 510 => x"db", + 511 => x"cc", + 512 => x"90", + 513 => x"cc", + 514 => x"90", + 515 => x"cc", + 516 => x"90", + 517 => x"cc", + 518 => x"e9", + 519 => x"cc", + 520 => x"90", + 521 => x"cc", + 522 => x"94", + 523 => x"cc", + 524 => x"90", + 525 => x"cc", + 526 => x"f7", + 527 => x"cc", + 528 => x"90", + 529 => x"cc", + 530 => x"cc", + 531 => x"cc", + 532 => x"90", + 533 => x"cc", + 534 => x"d6", + 535 => x"cc", + 536 => x"90", + 537 => x"cc", + 538 => x"98", + 539 => x"cc", + 540 => x"90", + 541 => x"cc", + 542 => x"de", + 543 => x"cc", + 544 => x"90", + 545 => x"cc", + 546 => x"84", + 547 => x"cc", + 548 => x"90", + 549 => x"cc", + 550 => x"2d", + 551 => x"08", + 552 => x"04", + 553 => x"0c", + 554 => x"81", + 555 => x"84", + 556 => x"81", + 557 => x"be", + 558 => x"de", + 559 => x"80", + 560 => x"de", + 561 => x"d1", + 562 => x"cc", + 563 => x"90", + 564 => x"cc", + 565 => x"2d", + 566 => x"08", + 567 => x"04", + 568 => x"0c", + 569 => x"81", + 570 => x"84", + 571 => x"81", + 572 => x"81", + 573 => x"81", + 574 => x"84", + 575 => x"3c", + 576 => x"10", + 577 => x"10", + 578 => x"10", + 579 => x"10", + 580 => x"10", + 581 => x"10", + 582 => x"10", + 583 => x"10", + 584 => x"00", + 585 => x"ff", + 586 => x"06", + 587 => x"83", + 588 => x"10", + 589 => x"fc", + 590 => x"51", + 591 => x"80", + 592 => x"ff", + 593 => x"06", + 594 => x"52", + 595 => x"0a", + 596 => x"38", + 597 => x"51", + 598 => x"c0", + 599 => x"ec", + 600 => x"80", + 601 => x"05", + 602 => x"0b", + 603 => x"04", + 604 => x"81", + 605 => x"00", + 606 => x"08", + 607 => x"cc", + 608 => x"0d", + 609 => x"de", + 610 => x"05", + 611 => x"de", + 612 => x"05", + 613 => x"d4", + 614 => x"c0", + 615 => x"de", + 616 => x"85", + 617 => x"de", + 618 => x"81", + 619 => x"02", + 620 => x"0c", + 621 => x"81", + 622 => x"cc", + 623 => x"08", + 624 => x"cc", + 625 => x"08", + 626 => x"3f", + 627 => x"08", + 628 => x"c0", + 629 => x"3d", + 630 => x"cc", + 631 => x"de", + 632 => x"81", + 633 => x"f9", + 634 => x"0b", + 635 => x"08", + 636 => x"81", + 637 => x"88", + 638 => x"25", + 639 => x"de", + 640 => x"05", + 641 => x"de", + 642 => x"05", + 643 => x"81", + 644 => x"f4", + 645 => x"de", + 646 => x"05", + 647 => x"81", + 648 => x"cc", + 649 => x"0c", + 650 => x"08", + 651 => x"81", + 652 => x"fc", + 653 => x"de", + 654 => x"05", + 655 => x"b9", + 656 => x"cc", + 657 => x"08", + 658 => x"cc", + 659 => x"0c", + 660 => x"de", + 661 => x"05", + 662 => x"cc", + 663 => x"08", + 664 => x"0b", + 665 => x"08", + 666 => x"81", + 667 => x"f0", + 668 => x"de", + 669 => x"05", + 670 => x"81", + 671 => x"8c", + 672 => x"81", + 673 => x"88", + 674 => x"81", + 675 => x"de", + 676 => x"81", + 677 => x"f8", + 678 => x"81", + 679 => x"fc", + 680 => x"2e", + 681 => x"de", + 682 => x"05", + 683 => x"de", + 684 => x"05", + 685 => x"cc", + 686 => x"08", + 687 => x"c0", + 688 => x"3d", + 689 => x"cc", + 690 => x"de", + 691 => x"81", + 692 => x"fb", + 693 => x"0b", + 694 => x"08", + 695 => x"81", + 696 => x"88", + 697 => x"25", + 698 => x"de", + 699 => x"05", + 700 => x"de", + 701 => x"05", + 702 => x"81", + 703 => x"fc", + 704 => x"de", + 705 => x"05", + 706 => x"90", + 707 => x"cc", + 708 => x"08", + 709 => x"cc", + 710 => x"0c", + 711 => x"de", + 712 => x"05", + 713 => x"de", + 714 => x"05", + 715 => x"3f", + 716 => x"08", + 717 => x"cc", + 718 => x"0c", + 719 => x"cc", + 720 => x"08", + 721 => x"38", + 722 => x"08", + 723 => x"30", + 724 => x"08", + 725 => x"81", + 726 => x"f8", + 727 => x"81", + 728 => x"54", + 729 => x"81", + 730 => x"04", + 731 => x"08", + 732 => x"cc", + 733 => x"0d", + 734 => x"de", + 735 => x"05", + 736 => x"81", + 737 => x"f8", + 738 => x"de", + 739 => x"05", + 740 => x"cc", + 741 => x"08", + 742 => x"81", + 743 => x"fc", + 744 => x"2e", + 745 => x"0b", + 746 => x"08", + 747 => x"24", + 748 => x"de", + 749 => x"05", + 750 => x"de", + 751 => x"05", + 752 => x"cc", + 753 => x"08", + 754 => x"cc", + 755 => x"0c", + 756 => x"81", + 757 => x"fc", + 758 => x"2e", + 759 => x"81", + 760 => x"8c", + 761 => x"de", + 762 => x"05", + 763 => x"38", + 764 => x"08", + 765 => x"81", + 766 => x"8c", + 767 => x"81", + 768 => x"88", + 769 => x"de", + 770 => x"05", + 771 => x"cc", + 772 => x"08", + 773 => x"cc", + 774 => x"0c", + 775 => x"08", + 776 => x"81", + 777 => x"cc", + 778 => x"0c", + 779 => x"08", + 780 => x"81", + 781 => x"cc", + 782 => x"0c", + 783 => x"81", + 784 => x"90", + 785 => x"2e", + 786 => x"de", + 787 => x"05", + 788 => x"de", + 789 => x"05", + 790 => x"39", + 791 => x"08", + 792 => x"70", + 793 => x"08", + 794 => x"51", + 795 => x"08", + 796 => x"81", + 797 => x"85", + 798 => x"de", + 799 => x"fc", + 800 => x"79", + 801 => x"05", + 802 => x"57", + 803 => x"83", + 804 => x"38", + 805 => x"51", + 806 => x"a4", + 807 => x"52", + 808 => x"93", + 809 => x"70", + 810 => x"34", + 811 => x"71", + 812 => x"81", + 813 => x"74", + 814 => x"0c", + 815 => x"04", + 816 => x"2b", + 817 => x"71", + 818 => x"51", + 819 => x"72", + 820 => x"72", + 821 => x"05", + 822 => x"71", + 823 => x"53", + 824 => x"70", + 825 => x"0c", + 826 => x"84", + 827 => x"f0", + 828 => x"8f", + 829 => x"83", + 830 => x"38", + 831 => x"84", + 832 => x"fc", + 833 => x"83", + 834 => x"70", + 835 => x"39", + 836 => x"77", + 837 => x"07", + 838 => x"54", + 839 => x"38", + 840 => x"08", + 841 => x"71", + 842 => x"80", + 843 => x"75", + 844 => x"33", + 845 => x"06", + 846 => x"80", + 847 => x"72", + 848 => x"75", + 849 => x"06", + 850 => x"12", + 851 => x"33", + 852 => x"06", + 853 => x"52", + 854 => x"72", + 855 => x"81", + 856 => x"81", + 857 => x"71", + 858 => x"c0", + 859 => x"87", + 860 => x"71", + 861 => x"fb", + 862 => x"06", + 863 => x"82", + 864 => x"51", + 865 => x"97", + 866 => x"84", + 867 => x"54", + 868 => x"75", + 869 => x"38", + 870 => x"52", + 871 => x"80", + 872 => x"c0", + 873 => x"0d", + 874 => x"0d", + 875 => x"53", + 876 => x"52", + 877 => x"81", + 878 => x"81", + 879 => x"07", + 880 => x"52", + 881 => x"e8", + 882 => x"de", + 883 => x"3d", + 884 => x"3d", + 885 => x"08", + 886 => x"56", + 887 => x"80", + 888 => x"33", + 889 => x"2e", + 890 => x"86", + 891 => x"52", + 892 => x"53", + 893 => x"13", + 894 => x"33", + 895 => x"06", + 896 => x"70", + 897 => x"38", + 898 => x"80", + 899 => x"74", + 900 => x"81", + 901 => x"70", + 902 => x"81", + 903 => x"80", + 904 => x"05", + 905 => x"76", + 906 => x"70", + 907 => x"0c", + 908 => x"04", + 909 => x"76", + 910 => x"80", + 911 => x"86", + 912 => x"52", + 913 => x"c3", + 914 => x"c0", + 915 => x"80", + 916 => x"74", + 917 => x"de", + 918 => x"3d", + 919 => x"3d", + 920 => x"11", + 921 => x"52", + 922 => x"70", + 923 => x"98", + 924 => x"33", + 925 => x"82", + 926 => x"26", + 927 => x"84", + 928 => x"83", + 929 => x"26", + 930 => x"85", + 931 => x"84", + 932 => x"26", + 933 => x"86", + 934 => x"85", + 935 => x"26", + 936 => x"88", + 937 => x"86", + 938 => x"e7", + 939 => x"38", + 940 => x"54", + 941 => x"87", + 942 => x"cc", + 943 => x"87", + 944 => x"0c", + 945 => x"c0", + 946 => x"82", + 947 => x"c0", + 948 => x"83", + 949 => x"c0", + 950 => x"84", + 951 => x"c0", + 952 => x"85", + 953 => x"c0", + 954 => x"86", + 955 => x"c0", + 956 => x"74", + 957 => x"a4", + 958 => x"c0", + 959 => x"80", + 960 => x"98", + 961 => x"52", + 962 => x"c0", + 963 => x"0d", + 964 => x"0d", + 965 => x"c0", + 966 => x"81", + 967 => x"c0", + 968 => x"5e", + 969 => x"87", + 970 => x"08", + 971 => x"1c", + 972 => x"98", + 973 => x"79", + 974 => x"87", + 975 => x"08", + 976 => x"1c", + 977 => x"98", + 978 => x"79", + 979 => x"87", + 980 => x"08", + 981 => x"1c", + 982 => x"98", + 983 => x"7b", + 984 => x"87", + 985 => x"08", + 986 => x"1c", + 987 => x"0c", + 988 => x"ff", + 989 => x"83", + 990 => x"58", + 991 => x"57", + 992 => x"56", + 993 => x"55", + 994 => x"54", + 995 => x"53", + 996 => x"ff", + 997 => x"c6", + 998 => x"88", + 999 => x"0d", + 1000 => x"0d", + 1001 => x"33", + 1002 => x"9f", + 1003 => x"52", + 1004 => x"81", + 1005 => x"83", + 1006 => x"fb", + 1007 => x"0b", + 1008 => x"88", + 1009 => x"ff", + 1010 => x"56", + 1011 => x"84", + 1012 => x"2e", + 1013 => x"c0", + 1014 => x"70", + 1015 => x"2a", + 1016 => x"53", + 1017 => x"80", + 1018 => x"71", + 1019 => x"81", + 1020 => x"70", + 1021 => x"81", + 1022 => x"06", + 1023 => x"80", + 1024 => x"71", + 1025 => x"81", + 1026 => x"70", + 1027 => x"73", + 1028 => x"51", + 1029 => x"80", + 1030 => x"2e", + 1031 => x"c0", + 1032 => x"75", + 1033 => x"81", + 1034 => x"87", + 1035 => x"fb", + 1036 => x"9f", + 1037 => x"0b", + 1038 => x"33", + 1039 => x"06", + 1040 => x"87", + 1041 => x"51", + 1042 => x"86", + 1043 => x"94", + 1044 => x"08", + 1045 => x"70", + 1046 => x"54", + 1047 => x"2e", + 1048 => x"91", + 1049 => x"06", + 1050 => x"d7", + 1051 => x"32", + 1052 => x"51", + 1053 => x"2e", + 1054 => x"93", + 1055 => x"06", + 1056 => x"ff", + 1057 => x"81", + 1058 => x"87", + 1059 => x"52", + 1060 => x"86", + 1061 => x"94", + 1062 => x"72", + 1063 => x"0d", + 1064 => x"0d", + 1065 => x"74", + 1066 => x"ff", + 1067 => x"57", + 1068 => x"80", + 1069 => x"81", + 1070 => x"15", + 1071 => x"db", + 1072 => x"81", + 1073 => x"57", + 1074 => x"c0", + 1075 => x"75", + 1076 => x"38", + 1077 => x"94", + 1078 => x"70", + 1079 => x"81", + 1080 => x"52", + 1081 => x"8c", + 1082 => x"2a", + 1083 => x"51", + 1084 => x"38", + 1085 => x"70", + 1086 => x"51", + 1087 => x"8d", + 1088 => x"2a", + 1089 => x"51", + 1090 => x"be", + 1091 => x"ff", + 1092 => x"c0", + 1093 => x"70", + 1094 => x"38", + 1095 => x"90", + 1096 => x"0c", + 1097 => x"33", + 1098 => x"06", + 1099 => x"70", + 1100 => x"76", + 1101 => x"0c", + 1102 => x"04", + 1103 => x"0b", + 1104 => x"88", + 1105 => x"ff", + 1106 => x"87", + 1107 => x"51", + 1108 => x"86", + 1109 => x"94", + 1110 => x"08", + 1111 => x"70", + 1112 => x"51", + 1113 => x"2e", + 1114 => x"81", + 1115 => x"87", + 1116 => x"52", + 1117 => x"86", + 1118 => x"94", + 1119 => x"08", + 1120 => x"06", + 1121 => x"0c", + 1122 => x"0d", + 1123 => x"0d", + 1124 => x"db", + 1125 => x"81", + 1126 => x"53", + 1127 => x"84", + 1128 => x"2e", + 1129 => x"c0", + 1130 => x"71", + 1131 => x"2a", + 1132 => x"51", + 1133 => x"52", + 1134 => x"a0", + 1135 => x"ff", + 1136 => x"c0", + 1137 => x"70", + 1138 => x"38", + 1139 => x"90", + 1140 => x"70", + 1141 => x"98", + 1142 => x"51", + 1143 => x"c0", + 1144 => x"0d", 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x"d2", + 1204 => x"87", + 1205 => x"08", + 1206 => x"0a", + 1207 => x"52", + 1208 => x"83", + 1209 => x"71", + 1210 => x"34", + 1211 => x"c0", + 1212 => x"70", + 1213 => x"06", + 1214 => x"70", + 1215 => x"38", + 1216 => x"81", + 1217 => x"80", + 1218 => x"9e", + 1219 => x"a0", + 1220 => x"51", + 1221 => x"80", + 1222 => x"81", + 1223 => x"db", + 1224 => x"0b", + 1225 => x"90", + 1226 => x"80", + 1227 => x"52", + 1228 => x"2e", + 1229 => x"52", + 1230 => x"d6", + 1231 => x"87", + 1232 => x"08", + 1233 => x"80", + 1234 => x"52", + 1235 => x"83", + 1236 => x"71", + 1237 => x"34", + 1238 => x"c0", + 1239 => x"70", + 1240 => x"06", + 1241 => x"70", + 1242 => x"38", + 1243 => x"81", + 1244 => x"80", + 1245 => x"9e", + 1246 => x"81", + 1247 => x"51", + 1248 => x"80", + 1249 => x"81", + 1250 => x"db", + 1251 => x"0b", + 1252 => x"90", + 1253 => x"c0", + 1254 => x"52", + 1255 => x"2e", + 1256 => x"52", + 1257 => x"da", + 1258 => x"87", + 1259 => x"08", + 1260 => x"06", + 1261 => x"70", + 1262 => x"38", + 1263 => x"81", + 1264 => x"87", + 1265 => x"08", + 1266 => x"06", + 1267 => x"51", + 1268 => x"81", + 1269 => x"80", + 1270 => x"9e", + 1271 => x"84", + 1272 => x"52", + 1273 => x"2e", + 1274 => x"52", + 1275 => x"dd", + 1276 => x"9e", + 1277 => x"83", + 1278 => x"84", + 1279 => x"51", + 1280 => x"de", + 1281 => x"87", + 1282 => x"08", + 1283 => x"51", + 1284 => x"80", + 1285 => x"81", + 1286 => x"db", + 1287 => x"c0", + 1288 => x"70", + 1289 => x"51", + 1290 => x"e0", + 1291 => x"0d", + 1292 => x"0d", + 1293 => x"51", + 1294 => x"81", + 1295 => x"54", + 1296 => x"88", + 1297 => x"90", + 1298 => x"3f", + 1299 => x"51", + 1300 => x"81", + 1301 => x"54", + 1302 => x"93", + 1303 => x"ac", + 1304 => x"b0", + 1305 => x"52", + 1306 => x"51", + 1307 => x"81", + 1308 => x"54", + 1309 => x"93", + 1310 => x"a4", + 1311 => x"a8", + 1312 => x"52", + 1313 => x"51", + 1314 => x"81", + 1315 => x"54", + 1316 => x"93", + 1317 => x"8c", + 1318 => x"90", + 1319 => x"52", + 1320 => x"51", + 1321 => x"81", + 1322 => x"54", + 1323 => x"93", + 1324 => x"94", + 1325 => x"98", + 1326 => x"52", + 1327 => x"51", + 1328 => x"81", + 1329 => x"54", + 1330 => x"93", + 1331 => x"9c", + 1332 => x"a0", + 1333 => x"52", + 1334 => x"51", + 1335 => x"81", + 1336 => x"54", + 1337 => x"8d", + 1338 => x"dc", + 1339 => x"c8", + 1340 => x"b0", + 1341 => x"df", + 1342 => x"80", + 1343 => x"81", + 1344 => x"52", + 1345 => x"51", + 1346 => x"81", + 1347 => x"54", + 1348 => x"8d", + 1349 => x"de", + 1350 => x"c9", + 1351 => x"84", + 1352 => x"d1", + 1353 => x"80", + 1354 => x"81", + 1355 => x"84", + 1356 => x"db", + 1357 => x"73", + 1358 => x"38", + 1359 => x"51", + 1360 => x"81", + 1361 => x"54", + 1362 => x"88", + 1363 => x"c8", + 1364 => x"3f", + 1365 => x"33", + 1366 => x"2e", + 1367 => x"c9", + 1368 => x"dc", + 1369 => x"da", + 1370 => x"80", + 1371 => x"81", + 1372 => x"83", + 1373 => x"c9", + 1374 => x"c4", + 1375 => x"b4", + 1376 => x"c9", + 1377 => x"9c", + 1378 => x"b8", + 1379 => x"ca", + 1380 => x"90", + 1381 => x"bc", + 1382 => x"ca", + 1383 => x"84", + 1384 => x"f0", + 1385 => x"3f", + 1386 => x"22", + 1387 => x"f8", + 1388 => x"3f", + 1389 => x"08", + 1390 => x"c0", + 1391 => x"e7", + 1392 => x"de", + 1393 => x"84", + 1394 => x"71", + 1395 => x"81", + 1396 => x"52", + 1397 => x"51", + 1398 => x"81", + 1399 => x"54", + 1400 => x"a8", + 1401 => x"c8", + 1402 => x"84", + 1403 => x"51", + 1404 => x"81", + 1405 => x"bd", + 1406 => x"76", + 1407 => x"54", + 1408 => x"08", + 1409 => x"cc", + 1410 => x"3f", + 1411 => x"33", + 1412 => x"2e", + 1413 => x"db", + 1414 => x"bd", + 1415 => x"75", + 1416 => x"3f", + 1417 => x"08", + 1418 => x"29", + 1419 => x"54", + 1420 => x"c0", + 1421 => x"cb", + 1422 => x"e8", + 1423 => x"9c", + 1424 => x"3f", + 1425 => x"04", + 1426 => x"02", + 1427 => x"ff", + 1428 => x"84", + 1429 => x"71", + 1430 => x"c6", + 1431 => x"71", + 1432 => x"cc", + 1433 => x"39", + 1434 => x"51", + 1435 => x"cc", + 1436 => x"39", + 1437 => x"51", + 1438 => x"cc", + 1439 => x"39", + 1440 => x"51", + 1441 => x"84", + 1442 => x"71", + 1443 => x"04", + 1444 => x"c0", + 1445 => x"04", + 1446 => x"87", + 1447 => x"70", + 1448 => x"80", + 1449 => x"74", + 1450 => x"db", + 1451 => x"0c", + 1452 => x"04", + 1453 => x"87", + 1454 => x"70", + 1455 => x"e4", + 1456 => x"72", + 1457 => x"70", + 1458 => x"08", + 1459 => x"db", + 1460 => x"0c", + 1461 => x"0d", + 1462 => x"e4", + 1463 => x"96", + 1464 => x"fe", + 1465 => x"93", + 1466 => x"72", + 1467 => x"81", + 1468 => x"8d", + 1469 => x"81", + 1470 => x"52", + 1471 => x"90", + 1472 => x"34", + 1473 => x"08", + 1474 => x"de", + 1475 => x"39", + 1476 => x"08", + 1477 => x"2e", + 1478 => x"51", + 1479 => x"3d", + 1480 => x"3d", + 1481 => x"05", + 1482 => x"d0", + 1483 => x"de", + 1484 => x"51", + 1485 => x"72", + 1486 => x"0c", + 1487 => x"04", + 1488 => x"75", + 1489 => x"70", + 1490 => x"53", + 1491 => x"2e", + 1492 => x"81", + 1493 => x"81", + 1494 => x"87", + 1495 => x"85", + 1496 => x"fc", + 1497 => x"81", + 1498 => x"78", + 1499 => x"0c", + 1500 => x"33", + 1501 => x"06", + 1502 => x"80", + 1503 => x"72", + 1504 => x"51", + 1505 => x"fe", + 1506 => x"39", + 1507 => x"d0", + 1508 => x"0d", + 1509 => x"0d", + 1510 => x"59", + 1511 => x"05", + 1512 => x"75", + 1513 => x"f8", + 1514 => x"2e", + 1515 => x"82", + 1516 => x"70", + 1517 => x"05", + 1518 => x"5b", + 1519 => x"2e", + 1520 => x"85", + 1521 => x"8b", + 1522 => x"2e", + 1523 => x"8a", + 1524 => x"78", + 1525 => x"5a", + 1526 => x"aa", + 1527 => x"06", + 1528 => x"84", + 1529 => x"7b", + 1530 => x"5d", + 1531 => x"59", + 1532 => x"d0", + 1533 => x"89", + 1534 => x"7a", + 1535 => x"10", + 1536 => x"d0", + 1537 => x"81", + 1538 => x"57", + 1539 => x"75", + 1540 => x"70", + 1541 => x"07", + 1542 => x"80", + 1543 => x"30", + 1544 => x"80", + 1545 => x"53", + 1546 => x"55", + 1547 => x"2e", + 1548 => x"84", + 1549 => x"81", + 1550 => x"57", + 1551 => x"2e", + 1552 => x"75", + 1553 => x"76", + 1554 => x"e0", + 1555 => x"ff", + 1556 => x"73", + 1557 => x"81", + 1558 => x"80", + 1559 => x"38", + 1560 => x"2e", + 1561 => x"73", + 1562 => x"8b", + 1563 => x"c2", + 1564 => x"38", + 1565 => x"73", + 1566 => x"81", + 1567 => x"8f", + 1568 => x"d5", + 1569 => x"38", + 1570 => x"24", + 1571 => x"80", + 1572 => x"38", + 1573 => x"73", + 1574 => x"80", + 1575 => x"ef", + 1576 => x"19", + 1577 => x"59", + 1578 => x"33", + 1579 => x"75", + 1580 => x"81", + 1581 => x"70", + 1582 => x"55", + 1583 => x"79", + 1584 => x"90", + 1585 => x"16", + 1586 => x"7b", + 1587 => x"a0", + 1588 => x"3f", + 1589 => x"53", + 1590 => x"e9", + 1591 => x"fc", + 1592 => x"81", + 1593 => x"72", + 1594 => x"b0", + 1595 => x"fb", + 1596 => x"39", + 1597 => x"83", + 1598 => x"59", + 1599 => x"82", + 1600 => x"88", + 1601 => x"8a", + 1602 => x"90", + 1603 => x"75", + 1604 => x"3f", + 1605 => x"79", + 1606 => x"81", + 1607 => x"72", + 1608 => x"38", + 1609 => x"59", + 1610 => x"84", + 1611 => x"58", + 1612 => x"80", + 1613 => x"30", + 1614 => x"80", + 1615 => x"55", + 1616 => x"25", + 1617 => x"80", + 1618 => x"74", + 1619 => x"07", + 1620 => x"0b", + 1621 => x"57", + 1622 => x"51", + 1623 => x"81", + 1624 => x"81", + 1625 => x"53", + 1626 => x"e0", + 1627 => x"de", + 1628 => x"89", + 1629 => x"38", + 1630 => x"75", + 1631 => x"84", + 1632 => x"53", + 1633 => x"06", + 1634 => x"53", + 1635 => x"81", + 1636 => x"81", + 1637 => x"70", + 1638 => x"2a", + 1639 => x"76", + 1640 => x"38", + 1641 => x"38", + 1642 => x"70", + 1643 => x"53", + 1644 => x"8e", + 1645 => x"77", + 1646 => x"53", + 1647 => x"81", + 1648 => x"7a", + 1649 => x"55", + 1650 => x"83", + 1651 => x"79", + 1652 => x"81", + 1653 => x"72", + 1654 => x"17", + 1655 => x"27", + 1656 => x"51", + 1657 => x"75", + 1658 => x"72", + 1659 => x"81", + 1660 => x"7a", + 1661 => x"38", + 1662 => x"05", + 1663 => x"ff", + 1664 => x"70", + 1665 => x"57", + 1666 => x"76", + 1667 => x"81", + 1668 => x"72", + 1669 => x"84", + 1670 => x"f9", + 1671 => x"39", + 1672 => x"04", + 1673 => x"86", + 1674 => x"84", + 1675 => x"55", + 1676 => x"fa", + 1677 => x"3d", + 1678 => x"3d", + 1679 => x"de", + 1680 => x"3d", + 1681 => x"75", + 1682 => x"3f", + 1683 => x"08", + 1684 => x"34", + 1685 => x"de", + 1686 => x"3d", + 1687 => x"3d", + 1688 => x"d0", + 1689 => x"de", + 1690 => x"3d", + 1691 => x"77", + 1692 => x"a1", + 1693 => x"de", + 1694 => x"3d", + 1695 => x"3d", + 1696 => x"81", + 1697 => x"70", + 1698 => x"55", + 1699 => x"80", + 1700 => x"38", + 1701 => x"08", + 1702 => x"81", + 1703 => x"81", + 1704 => x"72", + 1705 => x"cb", + 1706 => x"2e", + 1707 => x"88", + 1708 => x"70", + 1709 => x"51", + 1710 => x"2e", + 1711 => x"80", + 1712 => x"ff", + 1713 => x"39", + 1714 => x"c8", + 1715 => x"52", + 1716 => x"c0", + 1717 => x"52", + 1718 => x"81", + 1719 => x"51", + 1720 => x"ff", + 1721 => x"15", + 1722 => x"34", + 1723 => x"f3", + 1724 => x"72", + 1725 => x"0c", + 1726 => x"04", + 1727 => x"81", + 1728 => x"75", + 1729 => x"0c", + 1730 => x"52", + 1731 => x"3f", + 1732 => x"d4", + 1733 => x"0d", + 1734 => x"0d", + 1735 => x"56", + 1736 => x"0c", + 1737 => x"70", + 1738 => x"73", + 1739 => x"81", + 1740 => x"81", + 1741 => x"ed", + 1742 => x"2e", + 1743 => x"8e", + 1744 => x"08", + 1745 => x"76", + 1746 => x"56", + 1747 => x"b0", + 1748 => x"06", + 1749 => x"75", + 1750 => x"76", + 1751 => x"70", + 1752 => x"73", + 1753 => x"8b", + 1754 => x"73", + 1755 => x"85", + 1756 => x"82", + 1757 => x"76", + 1758 => x"70", + 1759 => x"ac", + 1760 => x"a0", + 1761 => x"fa", + 1762 => x"53", + 1763 => x"57", + 1764 => x"98", + 1765 => x"39", + 1766 => x"80", + 1767 => x"26", + 1768 => x"86", + 1769 => x"80", + 1770 => x"57", + 1771 => x"74", + 1772 => x"38", + 1773 => x"27", + 1774 => x"14", + 1775 => x"06", + 1776 => x"14", + 1777 => x"06", + 1778 => x"74", + 1779 => x"f9", + 1780 => x"ff", + 1781 => x"89", + 1782 => x"38", + 1783 => x"c5", + 1784 => x"29", + 1785 => x"81", + 1786 => x"76", + 1787 => x"56", + 1788 => x"ba", + 1789 => x"2e", + 1790 => x"30", + 1791 => x"0c", + 1792 => x"81", + 1793 => x"8a", + 1794 => x"f8", + 1795 => x"7c", + 1796 => x"70", + 1797 => x"75", + 1798 => x"55", + 1799 => x"2e", + 1800 => x"87", + 1801 => x"76", + 1802 => x"73", + 1803 => x"81", + 1804 => x"81", + 1805 => x"77", + 1806 => x"70", + 1807 => x"58", + 1808 => x"09", + 1809 => x"c2", + 1810 => x"81", + 1811 => x"75", + 1812 => x"55", + 1813 => x"e2", + 1814 => x"90", + 1815 => x"f8", + 1816 => x"8f", + 1817 => x"81", + 1818 => x"75", + 1819 => x"55", + 1820 => x"81", + 1821 => x"27", + 1822 => x"d0", + 1823 => x"55", + 1824 => x"73", + 1825 => x"80", + 1826 => x"14", + 1827 => x"72", + 1828 => x"e0", + 1829 => x"80", + 1830 => x"39", + 1831 => x"55", + 1832 => x"80", + 1833 => x"e0", + 1834 => x"38", + 1835 => x"81", + 1836 => x"53", + 1837 => x"81", + 1838 => x"53", + 1839 => x"8e", + 1840 => x"70", + 1841 => x"55", + 1842 => x"27", + 1843 => x"77", + 1844 => x"74", + 1845 => x"76", + 1846 => x"77", + 1847 => x"70", + 1848 => x"55", + 1849 => x"77", + 1850 => x"38", + 1851 => x"74", + 1852 => x"55", + 1853 => x"c0", + 1854 => x"0d", + 1855 => x"0d", + 1856 => x"33", + 1857 => x"70", + 1858 => x"38", + 1859 => x"11", + 1860 => x"81", + 1861 => x"83", + 1862 => x"fc", + 1863 => x"9b", + 1864 => x"84", + 1865 => x"33", + 1866 => x"51", + 1867 => x"80", + 1868 => x"84", + 1869 => x"92", + 1870 => x"51", + 1871 => x"80", + 1872 => x"81", + 1873 => x"72", + 1874 => x"92", + 1875 => x"81", + 1876 => x"0b", + 1877 => x"8c", + 1878 => x"71", + 1879 => x"06", + 1880 => x"80", + 1881 => x"87", + 1882 => x"08", + 1883 => x"38", + 1884 => x"80", + 1885 => x"71", + 1886 => x"c0", + 1887 => x"51", + 1888 => x"87", + 1889 => x"db", + 1890 => x"81", + 1891 => x"33", + 1892 => x"de", + 1893 => x"3d", + 1894 => x"3d", + 1895 => x"64", + 1896 => x"bf", + 1897 => x"40", + 1898 => x"74", + 1899 => x"cd", + 1900 => x"c0", + 1901 => x"7a", + 1902 => x"81", + 1903 => x"72", + 1904 => x"87", + 1905 => x"11", + 1906 => x"8c", + 1907 => x"92", + 1908 => x"5a", + 1909 => x"58", + 1910 => x"c0", + 1911 => x"76", + 1912 => x"76", + 1913 => x"70", + 1914 => x"81", + 1915 => x"54", + 1916 => x"8e", + 1917 => x"52", + 1918 => x"81", + 1919 => x"81", + 1920 => x"74", + 1921 => x"53", + 1922 => x"83", + 1923 => x"78", + 1924 => x"8f", + 1925 => x"2e", + 1926 => x"c0", + 1927 => x"52", + 1928 => x"87", + 1929 => x"08", + 1930 => x"2e", + 1931 => x"84", + 1932 => x"38", + 1933 => x"87", + 1934 => x"15", + 1935 => x"70", + 1936 => x"52", + 1937 => x"ff", + 1938 => x"39", + 1939 => x"81", + 1940 => x"ff", + 1941 => x"57", + 1942 => x"90", + 1943 => x"80", + 1944 => x"71", + 1945 => x"78", + 1946 => x"38", + 1947 => x"80", + 1948 => x"80", + 1949 => x"81", + 1950 => x"72", + 1951 => x"0c", + 1952 => x"04", + 1953 => x"60", + 1954 => x"8c", + 1955 => x"33", + 1956 => x"5b", + 1957 => x"74", + 1958 => x"e1", + 1959 => x"c0", + 1960 => x"79", + 1961 => x"78", + 1962 => x"06", + 1963 => x"77", + 1964 => x"87", + 1965 => x"11", + 1966 => x"8c", + 1967 => x"92", + 1968 => x"59", + 1969 => x"85", + 1970 => x"98", + 1971 => x"7d", + 1972 => x"0c", + 1973 => x"08", + 1974 => x"70", + 1975 => x"53", + 1976 => x"2e", + 1977 => x"70", + 1978 => x"33", + 1979 => x"18", + 1980 => x"2a", + 1981 => x"51", + 1982 => x"2e", + 1983 => x"c0", + 1984 => x"52", + 1985 => x"87", + 1986 => x"08", + 1987 => x"2e", + 1988 => x"84", + 1989 => x"38", + 1990 => x"87", + 1991 => x"15", + 1992 => x"70", + 1993 => x"52", + 1994 => x"ff", + 1995 => x"39", + 1996 => x"81", + 1997 => x"80", + 1998 => x"52", + 1999 => x"90", + 2000 => x"80", + 2001 => x"71", + 2002 => x"7a", + 2003 => x"38", + 2004 => x"80", + 2005 => x"80", + 2006 => x"81", + 2007 => x"72", + 2008 => x"0c", + 2009 => x"04", + 2010 => x"7e", + 2011 => x"b3", + 2012 => x"88", + 2013 => x"33", + 2014 => x"56", + 2015 => x"3f", + 2016 => x"08", + 2017 => x"83", + 2018 => x"fe", + 2019 => x"87", + 2020 => x"0c", + 2021 => x"76", + 2022 => x"38", + 2023 => x"93", + 2024 => x"2b", + 2025 => x"8c", + 2026 => x"71", + 2027 => x"38", + 2028 => x"71", + 2029 => x"c6", + 2030 => x"39", + 2031 => x"81", + 2032 => x"06", + 2033 => x"71", + 2034 => x"38", + 2035 => x"8c", + 2036 => x"e8", + 2037 => x"98", + 2038 => x"71", + 2039 => x"73", + 2040 => x"92", + 2041 => x"72", + 2042 => x"06", + 2043 => x"f7", + 2044 => x"80", + 2045 => x"88", + 2046 => x"0c", + 2047 => x"80", + 2048 => x"56", + 2049 => x"56", + 2050 => x"81", + 2051 => x"8c", + 2052 => x"fe", + 2053 => x"81", + 2054 => x"33", + 2055 => x"07", + 2056 => x"0c", + 2057 => x"3d", + 2058 => x"3d", + 2059 => x"11", + 2060 => x"33", + 2061 => x"71", + 2062 => x"81", + 2063 => x"72", + 2064 => x"75", + 2065 => x"81", + 2066 => x"52", + 2067 => x"54", + 2068 => x"0d", + 2069 => x"0d", + 2070 => x"05", + 2071 => x"52", + 2072 => x"70", + 2073 => x"34", + 2074 => x"51", + 2075 => x"83", + 2076 => x"ff", + 2077 => x"75", + 2078 => x"72", + 2079 => x"54", + 2080 => x"2a", + 2081 => x"70", + 2082 => x"34", + 2083 => x"51", + 2084 => x"81", + 2085 => x"70", + 2086 => x"70", + 2087 => x"3d", + 2088 => x"3d", + 2089 => x"77", + 2090 => x"70", + 2091 => x"38", + 2092 => x"05", + 2093 => x"70", + 2094 => x"34", + 2095 => x"eb", + 2096 => x"0d", + 2097 => x"0d", + 2098 => x"54", + 2099 => x"72", + 2100 => x"54", + 2101 => x"51", + 2102 => x"84", + 2103 => x"fc", + 2104 => x"77", + 2105 => x"53", + 2106 => x"05", + 2107 => x"70", + 2108 => x"33", + 2109 => x"ff", + 2110 => x"52", + 2111 => x"2e", + 2112 => x"80", + 2113 => x"71", + 2114 => x"0c", + 2115 => x"04", + 2116 => x"74", + 2117 => x"89", + 2118 => x"2e", + 2119 => x"11", + 2120 => x"52", + 2121 => x"70", + 2122 => x"c0", + 2123 => x"0d", + 2124 => x"81", + 2125 => x"04", + 2126 => x"de", + 2127 => x"f7", + 2128 => x"56", + 2129 => x"17", + 2130 => x"74", + 2131 => x"d6", + 2132 => x"b0", + 2133 => x"b4", + 2134 => x"81", + 2135 => x"59", + 2136 => x"81", + 2137 => x"7a", + 2138 => x"06", + 2139 => x"de", + 2140 => x"17", + 2141 => x"08", + 2142 => x"08", + 2143 => x"08", + 2144 => x"74", + 2145 => x"38", + 2146 => x"55", + 2147 => x"09", + 2148 => x"38", + 2149 => x"18", + 2150 => x"81", + 2151 => x"f9", + 2152 => x"39", + 2153 => x"81", + 2154 => x"8b", + 2155 => x"fa", + 2156 => x"7a", + 2157 => x"57", + 2158 => x"08", + 2159 => x"75", + 2160 => x"3f", + 2161 => x"08", + 2162 => x"c0", + 2163 => x"81", + 2164 => x"b4", + 2165 => x"16", + 2166 => x"be", + 2167 => x"c0", + 2168 => x"85", + 2169 => x"81", + 2170 => x"17", + 2171 => x"de", + 2172 => x"3d", + 2173 => x"3d", + 2174 => x"52", + 2175 => x"3f", + 2176 => x"08", + 2177 => x"c0", + 2178 => x"38", + 2179 => x"74", + 2180 => x"81", + 2181 => x"38", + 2182 => x"59", + 2183 => x"09", + 2184 => x"e3", + 2185 => x"53", + 2186 => x"08", + 2187 => x"70", + 2188 => x"91", + 2189 => x"d5", + 2190 => x"17", + 2191 => x"3f", + 2192 => x"a4", + 2193 => x"51", + 2194 => x"86", + 2195 => x"f2", + 2196 => x"17", + 2197 => x"3f", + 2198 => x"52", + 2199 => x"51", + 2200 => x"8c", + 2201 => x"84", + 2202 => x"fc", + 2203 => x"17", + 2204 => x"70", + 2205 => x"79", + 2206 => x"52", + 2207 => x"51", + 2208 => x"77", + 2209 => x"80", + 2210 => x"81", + 2211 => x"f9", + 2212 => x"de", + 2213 => x"2e", + 2214 => x"58", + 2215 => x"c0", + 2216 => x"0d", + 2217 => x"0d", + 2218 => x"98", + 2219 => x"05", + 2220 => x"80", + 2221 => x"27", + 2222 => x"14", + 2223 => x"29", + 2224 => x"05", + 2225 => x"81", + 2226 => x"87", + 2227 => x"f9", + 2228 => x"7a", + 2229 => x"54", + 2230 => x"27", + 2231 => x"76", + 2232 => x"27", + 2233 => x"ff", + 2234 => x"58", + 2235 => x"80", + 2236 => x"82", + 2237 => x"72", + 2238 => x"38", + 2239 => x"72", + 2240 => x"8e", + 2241 => x"39", + 2242 => x"17", + 2243 => x"a4", + 2244 => x"53", + 2245 => x"fd", + 2246 => x"de", + 2247 => x"9f", + 2248 => x"ff", + 2249 => x"11", + 2250 => x"70", + 2251 => x"18", + 2252 => x"76", + 2253 => x"53", + 2254 => x"81", + 2255 => x"80", + 2256 => x"83", + 2257 => x"b4", + 2258 => x"88", + 2259 => x"79", + 2260 => x"84", + 2261 => x"58", + 2262 => x"80", + 2263 => x"9f", + 2264 => x"80", + 2265 => x"88", + 2266 => x"08", + 2267 => x"51", + 2268 => x"81", + 2269 => x"80", + 2270 => x"10", + 2271 => x"74", + 2272 => x"51", + 2273 => x"81", + 2274 => x"83", + 2275 => x"58", + 2276 => x"87", + 2277 => x"08", + 2278 => x"51", + 2279 => x"81", + 2280 => x"9b", + 2281 => x"2b", + 2282 => x"74", + 2283 => x"51", + 2284 => x"81", + 2285 => x"f0", + 2286 => x"83", + 2287 => x"77", + 2288 => x"0c", + 2289 => x"04", + 2290 => x"7a", + 2291 => x"58", + 2292 => x"81", + 2293 => x"9e", + 2294 => x"17", + 2295 => x"96", + 2296 => x"53", + 2297 => x"81", + 2298 => x"79", + 2299 => x"72", + 2300 => x"38", + 2301 => x"72", + 2302 => x"b8", + 2303 => x"39", + 2304 => x"17", + 2305 => x"a4", + 2306 => x"53", + 2307 => x"fb", + 2308 => x"de", + 2309 => x"81", + 2310 => x"81", + 2311 => x"83", + 2312 => x"b4", + 2313 => x"78", + 2314 => x"56", + 2315 => x"76", + 2316 => x"38", + 2317 => x"9f", + 2318 => x"33", + 2319 => x"07", + 2320 => x"74", + 2321 => x"83", + 2322 => x"89", + 2323 => x"08", + 2324 => x"51", + 2325 => x"81", + 2326 => x"59", + 2327 => x"08", + 2328 => x"74", + 2329 => x"16", + 2330 => x"84", + 2331 => x"76", + 2332 => x"88", + 2333 => x"81", + 2334 => x"8f", + 2335 => x"53", + 2336 => x"80", + 2337 => x"88", + 2338 => x"08", + 2339 => x"51", + 2340 => x"81", + 2341 => x"59", + 2342 => x"08", + 2343 => x"77", + 2344 => x"06", + 2345 => x"83", + 2346 => x"05", + 2347 => x"f7", + 2348 => x"39", + 2349 => x"a4", + 2350 => x"52", + 2351 => x"ef", + 2352 => x"c0", + 2353 => x"de", + 2354 => x"38", + 2355 => x"06", + 2356 => x"83", + 2357 => x"18", + 2358 => x"54", + 2359 => x"f6", + 2360 => x"de", + 2361 => x"0a", + 2362 => x"52", + 2363 => x"83", + 2364 => x"83", + 2365 => x"81", + 2366 => x"8a", + 2367 => x"f8", + 2368 => x"7c", + 2369 => x"59", + 2370 => x"81", + 2371 => x"38", + 2372 => x"08", + 2373 => x"73", + 2374 => x"38", + 2375 => x"52", + 2376 => x"a4", + 2377 => x"c0", + 2378 => x"de", + 2379 => x"f2", + 2380 => x"82", + 2381 => x"39", + 2382 => x"e6", + 2383 => x"c0", + 2384 => x"de", + 2385 => x"78", + 2386 => x"3f", + 2387 => x"08", + 2388 => x"c0", + 2389 => x"80", + 2390 => x"de", + 2391 => x"2e", + 2392 => x"de", + 2393 => x"2e", + 2394 => x"53", + 2395 => x"51", + 2396 => x"81", + 2397 => x"c5", + 2398 => x"08", + 2399 => x"18", + 2400 => x"57", + 2401 => x"90", + 2402 => x"90", + 2403 => x"16", + 2404 => x"54", + 2405 => x"34", + 2406 => x"78", + 2407 => x"38", + 2408 => x"81", + 2409 => x"8a", + 2410 => x"f6", + 2411 => x"7e", + 2412 => x"5b", + 2413 => x"38", + 2414 => x"58", + 2415 => x"88", + 2416 => x"08", + 2417 => x"38", + 2418 => x"39", + 2419 => x"51", + 2420 => x"81", + 2421 => x"de", + 2422 => x"82", + 2423 => x"de", + 2424 => x"81", + 2425 => x"ff", + 2426 => x"38", + 2427 => x"81", + 2428 => x"26", + 2429 => x"79", + 2430 => x"08", + 2431 => x"73", + 2432 => x"b9", + 2433 => x"2e", + 2434 => x"80", + 2435 => x"1a", + 2436 => x"08", + 2437 => x"38", + 2438 => x"52", + 2439 => x"af", + 2440 => x"81", + 2441 => x"81", + 2442 => x"06", + 2443 => x"de", + 2444 => x"81", + 2445 => x"09", + 2446 => x"72", + 2447 => x"70", + 2448 => x"de", + 2449 => x"51", + 2450 => x"73", + 2451 => x"81", + 2452 => x"80", + 2453 => x"8c", + 2454 => x"81", + 2455 => x"38", + 2456 => x"08", + 2457 => x"73", + 2458 => x"75", + 2459 => x"77", + 2460 => x"56", + 2461 => x"76", + 2462 => x"82", + 2463 => x"26", + 2464 => x"75", + 2465 => x"f8", + 2466 => x"de", + 2467 => x"2e", + 2468 => x"59", + 2469 => x"08", + 2470 => x"81", + 2471 => x"81", + 2472 => x"59", + 2473 => x"08", + 2474 => x"70", + 2475 => x"25", + 2476 => x"51", + 2477 => x"73", + 2478 => x"75", + 2479 => x"81", + 2480 => x"38", + 2481 => x"f5", + 2482 => x"75", + 2483 => x"f9", + 2484 => x"de", + 2485 => x"de", + 2486 => x"70", + 2487 => x"08", + 2488 => x"51", + 2489 => x"80", + 2490 => x"73", + 2491 => x"38", + 2492 => x"52", + 2493 => x"d0", + 2494 => x"c0", + 2495 => x"a5", + 2496 => x"18", + 2497 => x"08", + 2498 => x"18", + 2499 => x"74", + 2500 => x"38", + 2501 => x"18", + 2502 => x"33", + 2503 => x"73", + 2504 => x"97", + 2505 => x"74", + 2506 => x"38", + 2507 => x"55", + 2508 => x"de", + 2509 => x"85", + 2510 => x"75", + 2511 => x"de", + 2512 => x"3d", + 2513 => x"3d", + 2514 => x"52", + 2515 => x"3f", + 2516 => x"08", + 2517 => x"81", + 2518 => x"80", + 2519 => x"52", + 2520 => x"c1", + 2521 => x"c0", + 2522 => x"c0", + 2523 => x"0c", + 2524 => x"53", + 2525 => x"15", + 2526 => x"f2", + 2527 => x"56", + 2528 => x"16", + 2529 => x"22", + 2530 => x"27", + 2531 => x"54", + 2532 => x"76", + 2533 => x"33", + 2534 => x"3f", + 2535 => x"08", + 2536 => x"38", + 2537 => x"76", + 2538 => x"70", + 2539 => x"9f", + 2540 => x"56", + 2541 => x"de", + 2542 => x"3d", + 2543 => x"3d", + 2544 => x"71", + 2545 => x"57", + 2546 => x"0a", + 2547 => x"38", + 2548 => x"53", + 2549 => x"38", + 2550 => x"0c", + 2551 => x"54", + 2552 => x"75", + 2553 => x"73", + 2554 => x"a8", + 2555 => x"73", + 2556 => x"85", + 2557 => x"0b", + 2558 => x"5a", + 2559 => x"27", + 2560 => x"a8", + 2561 => x"18", + 2562 => x"39", + 2563 => x"70", + 2564 => x"58", + 2565 => x"b2", + 2566 => x"76", + 2567 => x"3f", + 2568 => x"08", + 2569 => x"c0", + 2570 => x"bd", + 2571 => x"81", + 2572 => x"27", + 2573 => x"16", + 2574 => x"c0", + 2575 => x"38", + 2576 => x"39", + 2577 => x"55", + 2578 => x"52", + 2579 => x"d5", + 2580 => x"c0", + 2581 => x"0c", + 2582 => x"0c", + 2583 => x"53", + 2584 => x"80", + 2585 => x"85", + 2586 => x"94", + 2587 => x"2a", + 2588 => x"0c", + 2589 => x"06", + 2590 => x"9c", + 2591 => x"58", + 2592 => x"c0", + 2593 => x"0d", + 2594 => x"0d", + 2595 => x"90", + 2596 => x"05", + 2597 => x"f0", + 2598 => x"27", + 2599 => x"0b", + 2600 => x"98", + 2601 => x"84", + 2602 => x"2e", + 2603 => x"76", + 2604 => x"58", + 2605 => x"38", + 2606 => x"15", + 2607 => x"08", + 2608 => x"38", + 2609 => x"88", + 2610 => x"53", + 2611 => x"81", + 2612 => x"c0", + 2613 => x"22", + 2614 => x"89", + 2615 => x"72", + 2616 => x"74", + 2617 => x"f3", + 2618 => x"de", + 2619 => x"82", + 2620 => x"81", + 2621 => x"27", + 2622 => x"81", + 2623 => x"c0", + 2624 => x"80", + 2625 => x"16", + 2626 => x"c0", + 2627 => x"ca", + 2628 => x"38", + 2629 => x"0c", + 2630 => x"dd", + 2631 => x"08", + 2632 => x"f9", + 2633 => x"de", + 2634 => x"87", + 2635 => x"c0", + 2636 => x"80", + 2637 => x"55", + 2638 => x"08", + 2639 => x"38", + 2640 => x"de", + 2641 => x"2e", + 2642 => x"de", + 2643 => x"75", + 2644 => x"3f", + 2645 => x"08", + 2646 => x"94", + 2647 => x"52", + 2648 => x"c1", + 2649 => x"c0", + 2650 => x"0c", + 2651 => x"0c", + 2652 => x"05", + 2653 => x"80", + 2654 => x"de", + 2655 => x"3d", + 2656 => x"3d", + 2657 => x"71", + 2658 => x"57", + 2659 => x"51", + 2660 => x"81", + 2661 => x"54", + 2662 => x"08", + 2663 => x"81", + 2664 => x"56", + 2665 => x"52", + 2666 => x"83", + 2667 => x"c0", + 2668 => x"de", + 2669 => x"d2", + 2670 => x"c0", + 2671 => x"08", + 2672 => x"54", + 2673 => x"e5", + 2674 => x"06", + 2675 => x"58", + 2676 => x"08", + 2677 => x"38", + 2678 => x"75", + 2679 => x"80", + 2680 => x"81", + 2681 => x"7a", + 2682 => x"06", + 2683 => x"39", + 2684 => x"08", + 2685 => x"76", + 2686 => x"3f", + 2687 => x"08", + 2688 => x"c0", + 2689 => x"ff", + 2690 => x"84", + 2691 => x"06", + 2692 => x"54", + 2693 => x"c0", + 2694 => x"0d", + 2695 => x"0d", + 2696 => x"52", + 2697 => x"3f", + 2698 => x"08", + 2699 => x"06", + 2700 => x"51", + 2701 => x"83", + 2702 => x"06", + 2703 => x"14", + 2704 => x"3f", + 2705 => x"08", + 2706 => x"07", + 2707 => x"de", + 2708 => x"3d", + 2709 => x"3d", + 2710 => x"70", + 2711 => x"06", + 2712 => x"53", + 2713 => x"ed", + 2714 => x"33", + 2715 => x"83", + 2716 => x"06", + 2717 => x"90", + 2718 => x"15", + 2719 => x"3f", + 2720 => x"04", + 2721 => x"7b", + 2722 => x"84", + 2723 => x"58", + 2724 => x"80", + 2725 => x"38", + 2726 => x"52", + 2727 => x"8f", + 2728 => x"c0", + 2729 => x"de", + 2730 => x"f5", + 2731 => x"08", + 2732 => x"53", + 2733 => x"84", + 2734 => x"39", + 2735 => x"70", + 2736 => x"81", + 2737 => x"51", + 2738 => x"16", + 2739 => x"c0", + 2740 => x"81", + 2741 => x"38", + 2742 => x"ae", + 2743 => x"81", + 2744 => x"54", + 2745 => x"2e", + 2746 => x"8f", + 2747 => x"81", + 2748 => x"76", + 2749 => x"54", + 2750 => x"09", + 2751 => x"38", + 2752 => x"7a", + 2753 => x"80", + 2754 => x"fa", + 2755 => x"de", + 2756 => x"81", + 2757 => x"89", + 2758 => x"08", + 2759 => x"86", + 2760 => x"98", + 2761 => x"81", + 2762 => x"8b", + 2763 => x"fb", + 2764 => x"70", + 2765 => x"81", + 2766 => x"fc", + 2767 => x"de", + 2768 => x"81", + 2769 => x"b4", + 2770 => x"08", + 2771 => x"ec", + 2772 => x"de", + 2773 => x"81", + 2774 => x"a0", + 2775 => x"81", + 2776 => x"52", + 2777 => x"51", + 2778 => x"8b", + 2779 => x"52", + 2780 => x"51", + 2781 => x"81", + 2782 => x"34", + 2783 => x"c0", + 2784 => x"0d", + 2785 => x"0d", + 2786 => x"98", + 2787 => x"70", + 2788 => x"ec", + 2789 => x"de", + 2790 => x"38", + 2791 => x"53", + 2792 => x"81", + 2793 => x"34", + 2794 => x"04", + 2795 => x"78", + 2796 => x"80", + 2797 => x"34", + 2798 => x"80", + 2799 => x"38", + 2800 => x"18", + 2801 => x"9c", + 2802 => x"70", + 2803 => x"56", + 2804 => x"a0", + 2805 => x"71", + 2806 => x"81", + 2807 => x"81", + 2808 => x"89", + 2809 => x"06", + 2810 => x"73", + 2811 => x"55", + 2812 => x"55", + 2813 => x"81", + 2814 => x"81", + 2815 => x"74", + 2816 => x"75", + 2817 => x"52", + 2818 => x"13", + 2819 => x"08", + 2820 => x"33", + 2821 => x"9c", + 2822 => x"11", + 2823 => x"8a", + 2824 => x"c0", + 2825 => x"96", + 2826 => x"e7", + 2827 => x"c0", + 2828 => x"23", + 2829 => x"e7", + 2830 => x"de", + 2831 => x"17", + 2832 => x"0d", + 2833 => x"0d", + 2834 => x"5e", + 2835 => x"70", + 2836 => x"55", + 2837 => x"83", + 2838 => x"73", + 2839 => x"91", + 2840 => x"2e", + 2841 => x"1d", + 2842 => x"0c", + 2843 => x"15", + 2844 => x"70", + 2845 => x"56", + 2846 => x"09", + 2847 => x"38", + 2848 => x"80", + 2849 => x"30", + 2850 => x"78", + 2851 => x"54", + 2852 => x"73", + 2853 => x"60", + 2854 => x"54", + 2855 => x"96", + 2856 => x"0b", + 2857 => x"80", + 2858 => x"f6", + 2859 => x"de", + 2860 => x"85", + 2861 => x"3d", + 2862 => x"5c", + 2863 => x"53", + 2864 => x"51", + 2865 => x"80", + 2866 => x"88", + 2867 => x"5c", + 2868 => x"09", + 2869 => x"d4", + 2870 => x"70", + 2871 => x"71", + 2872 => x"30", + 2873 => x"73", + 2874 => x"51", + 2875 => x"57", + 2876 => x"38", + 2877 => x"75", + 2878 => x"17", + 2879 => x"75", + 2880 => x"30", + 2881 => x"51", + 2882 => x"80", + 2883 => x"38", + 2884 => x"87", + 2885 => x"26", + 2886 => x"77", + 2887 => x"a4", + 2888 => x"27", + 2889 => x"a0", + 2890 => x"39", + 2891 => x"33", + 2892 => x"57", + 2893 => x"27", + 2894 => x"75", + 2895 => x"30", + 2896 => x"32", + 2897 => x"80", + 2898 => x"25", + 2899 => x"56", + 2900 => x"80", + 2901 => x"84", + 2902 => x"58", + 2903 => x"70", + 2904 => x"55", + 2905 => x"09", + 2906 => x"38", + 2907 => x"80", + 2908 => x"30", + 2909 => x"77", + 2910 => x"54", + 2911 => x"81", + 2912 => x"ae", + 2913 => x"06", + 2914 => x"54", + 2915 => x"74", + 2916 => x"80", + 2917 => x"7b", + 2918 => x"30", + 2919 => x"70", + 2920 => x"25", + 2921 => x"07", + 2922 => x"51", + 2923 => x"a7", + 2924 => x"8b", + 2925 => x"39", + 2926 => x"54", + 2927 => x"8c", + 2928 => x"ff", + 2929 => x"b4", + 2930 => x"54", + 2931 => x"e1", + 2932 => x"c0", + 2933 => x"b2", + 2934 => x"70", + 2935 => x"71", + 2936 => x"54", + 2937 => x"81", + 2938 => x"80", + 2939 => x"38", + 2940 => x"76", + 2941 => x"df", + 2942 => x"54", + 2943 => x"81", + 2944 => x"55", + 2945 => x"34", + 2946 => x"52", + 2947 => x"51", + 2948 => x"81", + 2949 => x"bf", + 2950 => x"16", + 2951 => x"26", + 2952 => x"16", + 2953 => x"06", + 2954 => x"17", + 2955 => x"34", + 2956 => x"fd", + 2957 => x"19", + 2958 => x"80", + 2959 => x"79", + 2960 => x"81", + 2961 => x"81", + 2962 => x"85", + 2963 => x"54", + 2964 => x"8f", + 2965 => x"86", + 2966 => x"39", + 2967 => x"f3", + 2968 => x"73", + 2969 => x"80", + 2970 => x"52", + 2971 => x"ce", + 2972 => x"c0", + 2973 => x"de", + 2974 => x"d7", + 2975 => x"08", + 2976 => x"e6", + 2977 => x"de", + 2978 => x"81", + 2979 => x"80", + 2980 => x"1b", + 2981 => x"55", + 2982 => x"2e", + 2983 => x"8b", + 2984 => x"06", + 2985 => x"1c", + 2986 => x"33", + 2987 => x"70", + 2988 => x"55", + 2989 => x"38", + 2990 => x"52", + 2991 => x"9f", + 2992 => x"c0", + 2993 => x"8b", + 2994 => x"7a", + 2995 => x"3f", + 2996 => x"75", + 2997 => x"57", + 2998 => x"2e", + 2999 => x"84", + 3000 => x"06", + 3001 => x"75", + 3002 => x"81", + 3003 => x"2a", + 3004 => x"73", + 3005 => x"38", + 3006 => x"54", + 3007 => x"fb", + 3008 => x"80", + 3009 => x"34", + 3010 => x"c1", + 3011 => x"06", + 3012 => x"38", + 3013 => x"39", + 3014 => x"70", + 3015 => x"54", + 3016 => x"86", + 3017 => x"84", + 3018 => x"06", + 3019 => x"73", + 3020 => x"38", + 3021 => x"83", + 3022 => x"b4", + 3023 => x"51", + 3024 => x"81", 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x"33", + 3084 => x"de", + 3085 => x"3d", + 3086 => x"3d", + 3087 => x"80", + 3088 => x"34", + 3089 => x"17", + 3090 => x"75", + 3091 => x"3f", + 3092 => x"de", + 3093 => x"80", + 3094 => x"16", + 3095 => x"3f", + 3096 => x"08", + 3097 => x"06", + 3098 => x"73", + 3099 => x"2e", + 3100 => x"80", + 3101 => x"0b", + 3102 => x"56", + 3103 => x"e9", + 3104 => x"06", + 3105 => x"57", + 3106 => x"32", + 3107 => x"80", + 3108 => x"51", + 3109 => x"8a", + 3110 => x"e8", + 3111 => x"06", + 3112 => x"53", + 3113 => x"52", + 3114 => x"51", + 3115 => x"81", + 3116 => x"55", + 3117 => x"08", + 3118 => x"38", + 3119 => x"cc", + 3120 => x"86", + 3121 => x"97", + 3122 => x"c0", + 3123 => x"de", + 3124 => x"2e", + 3125 => x"55", + 3126 => x"c0", + 3127 => x"0d", + 3128 => x"0d", + 3129 => x"05", + 3130 => x"33", + 3131 => x"75", + 3132 => x"fc", + 3133 => x"de", + 3134 => x"8b", + 3135 => x"81", + 3136 => x"24", + 3137 => x"81", + 3138 => x"84", + 3139 => x"dc", + 3140 => x"55", + 3141 => x"73", + 3142 => x"e6", + 3143 => x"0c", + 3144 => x"06", + 3145 => x"57", + 3146 => x"ae", + 3147 => x"33", + 3148 => x"3f", + 3149 => x"08", + 3150 => x"70", + 3151 => x"55", + 3152 => x"76", + 3153 => x"b8", + 3154 => x"2a", + 3155 => x"51", + 3156 => x"72", + 3157 => x"86", + 3158 => x"74", + 3159 => x"15", + 3160 => x"81", + 3161 => x"d7", + 3162 => x"de", + 3163 => x"ff", + 3164 => x"06", + 3165 => x"56", + 3166 => x"38", + 3167 => x"8f", + 3168 => x"2a", + 3169 => x"51", + 3170 => x"72", + 3171 => x"80", + 3172 => x"52", + 3173 => x"3f", + 3174 => x"08", + 3175 => x"57", + 3176 => x"09", + 3177 => x"e2", + 3178 => x"74", + 3179 => x"56", + 3180 => x"33", + 3181 => x"72", + 3182 => x"38", + 3183 => x"51", + 3184 => x"81", + 3185 => x"57", + 3186 => x"84", + 3187 => x"ff", + 3188 => x"56", + 3189 => x"25", + 3190 => x"0b", + 3191 => x"56", + 3192 => x"05", + 3193 => x"83", + 3194 => x"2e", + 3195 => x"52", + 3196 => x"c6", + 3197 => x"c0", + 3198 => x"06", + 3199 => x"27", + 3200 => x"16", + 3201 => x"27", + 3202 => x"56", + 3203 => x"84", + 3204 => x"56", + 3205 => x"84", + 3206 => x"14", + 3207 => x"3f", + 3208 => x"08", + 3209 => x"06", + 3210 => x"80", + 3211 => x"06", + 3212 => x"80", + 3213 => x"db", + 3214 => x"de", + 3215 => x"ff", + 3216 => x"77", + 3217 => x"d8", + 3218 => x"de", + 3219 => x"c0", + 3220 => x"9c", + 3221 => x"c4", + 3222 => x"15", + 3223 => x"14", + 3224 => x"70", + 3225 => x"51", + 3226 => x"56", + 3227 => x"84", + 3228 => x"81", + 3229 => x"71", + 3230 => x"16", + 3231 => x"53", + 3232 => x"23", + 3233 => x"8b", + 3234 => x"73", + 3235 => x"80", + 3236 => x"8d", + 3237 => x"39", + 3238 => x"51", + 3239 => x"81", + 3240 => x"53", + 3241 => x"08", + 3242 => x"72", + 3243 => x"8d", + 3244 => x"ce", + 3245 => x"14", + 3246 => x"3f", + 3247 => x"08", + 3248 => x"06", + 3249 => x"38", + 3250 => x"51", + 3251 => x"81", + 3252 => x"55", + 3253 => x"51", + 3254 => x"81", + 3255 => x"83", + 3256 => x"53", + 3257 => x"80", + 3258 => x"38", + 3259 => x"78", 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x"d8", + 3319 => x"de", + 3320 => x"ff", + 3321 => x"72", + 3322 => x"81", + 3323 => x"38", + 3324 => x"73", + 3325 => x"3f", + 3326 => x"08", + 3327 => x"81", + 3328 => x"84", + 3329 => x"b2", + 3330 => x"87", + 3331 => x"c0", + 3332 => x"ff", + 3333 => x"82", + 3334 => x"09", + 3335 => x"c8", + 3336 => x"51", + 3337 => x"81", + 3338 => x"84", + 3339 => x"d2", + 3340 => x"06", + 3341 => x"98", + 3342 => x"ee", + 3343 => x"c0", + 3344 => x"85", + 3345 => x"09", + 3346 => x"38", + 3347 => x"51", + 3348 => x"81", + 3349 => x"90", + 3350 => x"a0", + 3351 => x"ca", + 3352 => x"c0", + 3353 => x"0c", + 3354 => x"81", + 3355 => x"81", + 3356 => x"81", + 3357 => x"72", + 3358 => x"80", + 3359 => x"0c", + 3360 => x"81", + 3361 => x"90", + 3362 => x"fb", + 3363 => x"54", + 3364 => x"80", + 3365 => x"73", + 3366 => x"80", + 3367 => x"72", + 3368 => x"80", + 3369 => x"86", + 3370 => x"15", + 3371 => x"71", + 3372 => x"81", + 3373 => x"81", + 3374 => x"d0", + 3375 => x"de", + 3376 => x"06", + 3377 => x"38", + 3378 => x"54", + 3379 => x"80", + 3380 => x"71", + 3381 => x"81", + 3382 => x"87", + 3383 => x"fa", + 3384 => x"ab", + 3385 => x"58", + 3386 => x"05", + 3387 => x"e6", + 3388 => x"80", + 3389 => x"c0", + 3390 => x"38", + 3391 => x"08", + 3392 => x"de", + 3393 => x"08", + 3394 => x"80", + 3395 => x"80", + 3396 => x"54", + 3397 => x"84", + 3398 => x"34", + 3399 => x"75", + 3400 => x"2e", + 3401 => x"53", + 3402 => x"53", + 3403 => x"f7", + 3404 => x"de", + 3405 => x"73", + 3406 => x"0c", + 3407 => x"04", + 3408 => x"67", + 3409 => x"80", + 3410 => x"59", + 3411 => x"78", + 3412 => x"c8", + 3413 => x"06", + 3414 => x"3d", + 3415 => x"99", + 3416 => x"52", + 3417 => x"3f", + 3418 => x"08", + 3419 => x"c0", + 3420 => x"38", + 3421 => x"52", + 3422 => x"52", + 3423 => x"3f", + 3424 => x"08", + 3425 => x"c0", + 3426 => x"02", + 3427 => x"33", + 3428 => x"55", + 3429 => x"25", + 3430 => x"55", + 3431 => x"54", + 3432 => x"81", + 3433 => x"80", + 3434 => x"74", + 3435 => x"81", + 3436 => x"75", + 3437 => x"3f", + 3438 => x"08", + 3439 => x"02", + 3440 => x"91", + 3441 => x"81", + 3442 => x"82", + 3443 => x"06", + 3444 => x"80", + 3445 => x"88", + 3446 => x"39", + 3447 => x"58", + 3448 => x"38", + 3449 => x"70", + 3450 => x"54", + 3451 => x"81", + 3452 => x"52", + 3453 => x"a5", + 3454 => x"c0", + 3455 => x"88", + 3456 => x"62", + 3457 => x"d4", + 3458 => x"54", + 3459 => x"15", + 3460 => x"62", + 3461 => x"e8", + 3462 => x"52", + 3463 => x"51", + 3464 => x"7a", + 3465 => x"83", + 3466 => x"80", + 3467 => x"38", + 3468 => x"08", + 3469 => x"53", + 3470 => x"3d", + 3471 => x"dd", + 3472 => x"de", + 3473 => x"81", + 3474 => x"82", + 3475 => x"39", + 3476 => x"38", + 3477 => x"33", + 3478 => x"70", + 3479 => x"55", + 3480 => x"2e", + 3481 => x"55", + 3482 => x"77", + 3483 => x"81", + 3484 => x"73", + 3485 => x"38", + 3486 => x"54", + 3487 => x"a0", + 3488 => x"82", + 3489 => x"52", + 3490 => x"a3", + 3491 => x"c0", + 3492 => x"18", + 3493 => x"55", + 3494 => x"c0", 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x"55", + 3554 => x"89", + 3555 => x"c0", + 3556 => x"1a", + 3557 => x"80", + 3558 => x"54", + 3559 => x"c0", + 3560 => x"0d", + 3561 => x"0d", + 3562 => x"64", + 3563 => x"59", + 3564 => x"90", + 3565 => x"52", + 3566 => x"cf", + 3567 => x"c0", + 3568 => x"de", + 3569 => x"38", + 3570 => x"55", + 3571 => x"86", + 3572 => x"82", + 3573 => x"19", + 3574 => x"55", + 3575 => x"80", + 3576 => x"38", + 3577 => x"0b", + 3578 => x"82", + 3579 => x"39", + 3580 => x"1a", + 3581 => x"82", + 3582 => x"19", + 3583 => x"08", + 3584 => x"7c", + 3585 => x"74", + 3586 => x"2e", + 3587 => x"94", + 3588 => x"83", + 3589 => x"56", + 3590 => x"38", + 3591 => x"22", + 3592 => x"89", + 3593 => x"55", + 3594 => x"75", + 3595 => x"19", + 3596 => x"39", + 3597 => x"52", + 3598 => x"93", + 3599 => x"c0", + 3600 => x"75", + 3601 => x"38", + 3602 => x"ff", + 3603 => x"98", + 3604 => x"19", + 3605 => x"51", + 3606 => x"81", + 3607 => x"80", + 3608 => x"38", + 3609 => x"08", + 3610 => x"2a", + 3611 => x"80", + 3612 => x"38", + 3613 => x"8a", + 3614 => x"5c", + 3615 => x"27", + 3616 => x"7a", + 3617 => x"54", + 3618 => x"52", + 3619 => x"51", + 3620 => x"81", + 3621 => x"fe", + 3622 => x"83", + 3623 => x"56", + 3624 => x"9f", + 3625 => x"08", + 3626 => x"74", + 3627 => x"38", + 3628 => x"b4", + 3629 => x"16", + 3630 => x"89", + 3631 => x"51", + 3632 => x"77", + 3633 => x"b9", + 3634 => x"1a", + 3635 => x"08", + 3636 => x"84", + 3637 => x"57", + 3638 => x"27", + 3639 => x"56", + 3640 => x"52", + 3641 => x"c7", + 3642 => x"c0", + 3643 => x"38", + 3644 => x"19", + 3645 => x"06", + 3646 => x"52", + 3647 => x"a2", + 3648 => x"31", + 3649 => x"7f", + 3650 => x"94", + 3651 => x"94", + 3652 => x"5c", + 3653 => x"80", + 3654 => x"de", + 3655 => x"3d", + 3656 => x"3d", + 3657 => x"65", + 3658 => x"5d", + 3659 => x"0c", + 3660 => x"05", + 3661 => x"f6", + 3662 => x"de", + 3663 => x"81", + 3664 => x"8a", + 3665 => x"33", + 3666 => x"2e", + 3667 => x"56", + 3668 => x"90", + 3669 => x"81", + 3670 => x"06", + 3671 => x"87", + 3672 => x"2e", + 3673 => x"95", + 3674 => x"91", + 3675 => x"56", + 3676 => x"81", + 3677 => x"34", + 3678 => x"8e", + 3679 => x"08", + 3680 => x"56", + 3681 => x"84", + 3682 => x"5c", + 3683 => x"82", + 3684 => x"18", + 3685 => x"ff", + 3686 => x"74", + 3687 => x"7e", + 3688 => x"ff", + 3689 => x"2a", + 3690 => x"7a", + 3691 => x"8c", + 3692 => x"08", + 3693 => x"38", + 3694 => x"39", + 3695 => x"52", + 3696 => x"e7", + 3697 => x"c0", + 3698 => x"de", + 3699 => x"2e", + 3700 => x"74", + 3701 => x"91", + 3702 => x"2e", + 3703 => x"74", + 3704 => x"88", + 3705 => x"38", + 3706 => x"0c", + 3707 => x"15", + 3708 => x"08", + 3709 => x"06", + 3710 => x"51", + 3711 => x"81", + 3712 => x"fe", + 3713 => x"18", + 3714 => x"51", + 3715 => x"81", + 3716 => x"80", + 3717 => x"38", + 3718 => x"08", + 3719 => x"2a", + 3720 => x"80", + 3721 => x"38", + 3722 => x"8a", + 3723 => x"5b", + 3724 => x"27", + 3725 => x"7b", + 3726 => x"54", + 3727 => x"52", + 3728 => x"51", + 3729 => x"81", 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x"2a", + 3789 => x"51", + 3790 => x"80", + 3791 => x"38", + 3792 => x"52", + 3793 => x"e7", + 3794 => x"c0", + 3795 => x"de", + 3796 => x"d4", + 3797 => x"08", + 3798 => x"a0", + 3799 => x"73", + 3800 => x"88", + 3801 => x"74", + 3802 => x"51", + 3803 => x"8c", + 3804 => x"9c", + 3805 => x"fb", + 3806 => x"b2", + 3807 => x"15", + 3808 => x"3f", + 3809 => x"15", + 3810 => x"3f", + 3811 => x"0b", + 3812 => x"78", + 3813 => x"3f", + 3814 => x"08", + 3815 => x"81", + 3816 => x"57", + 3817 => x"34", + 3818 => x"c0", + 3819 => x"0d", + 3820 => x"0d", + 3821 => x"54", + 3822 => x"81", + 3823 => x"53", + 3824 => x"08", + 3825 => x"3d", + 3826 => x"73", + 3827 => x"3f", + 3828 => x"08", + 3829 => x"c0", + 3830 => x"81", + 3831 => x"74", + 3832 => x"de", + 3833 => x"3d", + 3834 => x"3d", + 3835 => x"51", + 3836 => x"8b", + 3837 => x"81", + 3838 => x"24", + 3839 => x"de", + 3840 => x"de", + 3841 => x"52", + 3842 => x"c0", + 3843 => x"0d", + 3844 => x"0d", + 3845 => x"3d", + 3846 => x"94", + 3847 => x"c1", + 3848 => x"c0", + 3849 => x"de", + 3850 => x"e0", + 3851 => x"63", + 3852 => x"d4", + 3853 => x"8d", + 3854 => x"c0", + 3855 => x"de", + 3856 => x"38", + 3857 => x"05", + 3858 => x"2b", + 3859 => x"80", + 3860 => x"76", + 3861 => x"0c", + 3862 => x"02", + 3863 => x"70", + 3864 => x"81", + 3865 => x"56", + 3866 => x"9e", + 3867 => x"53", + 3868 => x"db", + 3869 => x"de", + 3870 => x"15", + 3871 => x"81", + 3872 => x"84", + 3873 => x"06", + 3874 => x"55", + 3875 => x"c0", + 3876 => x"0d", + 3877 => x"0d", + 3878 => x"5b", + 3879 => x"80", + 3880 => x"ff", + 3881 => x"9f", + 3882 => x"b5", + 3883 => x"c0", + 3884 => x"de", + 3885 => x"fc", + 3886 => x"7a", + 3887 => x"08", + 3888 => x"64", + 3889 => x"2e", + 3890 => x"a0", + 3891 => x"70", + 3892 => x"ea", + 3893 => x"c0", + 3894 => x"de", + 3895 => x"d4", + 3896 => x"7b", + 3897 => x"3f", + 3898 => x"08", + 3899 => x"c0", + 3900 => x"38", + 3901 => x"51", + 3902 => x"81", + 3903 => x"45", + 3904 => x"51", + 3905 => x"81", + 3906 => x"57", + 3907 => x"08", + 3908 => x"80", + 3909 => x"da", + 3910 => x"de", + 3911 => x"81", + 3912 => x"a4", + 3913 => x"7b", + 3914 => x"3f", + 3915 => x"c0", + 3916 => x"38", + 3917 => x"51", + 3918 => x"81", + 3919 => x"57", + 3920 => x"08", + 3921 => x"38", + 3922 => x"09", + 3923 => x"38", + 3924 => x"e0", + 3925 => x"dc", + 3926 => x"ff", + 3927 => x"74", + 3928 => x"3f", + 3929 => x"78", + 3930 => x"33", + 3931 => x"56", + 3932 => x"91", + 3933 => x"05", + 3934 => x"81", + 3935 => x"56", + 3936 => x"f5", + 3937 => x"54", + 3938 => x"81", + 3939 => x"80", + 3940 => x"78", + 3941 => x"55", + 3942 => x"11", + 3943 => x"18", + 3944 => x"58", + 3945 => x"34", + 3946 => x"ff", + 3947 => x"55", + 3948 => x"34", + 3949 => x"77", + 3950 => x"81", + 3951 => x"ff", + 3952 => x"55", + 3953 => x"34", + 3954 => x"de", + 3955 => x"84", + 3956 => x"a4", + 3957 => x"70", + 3958 => x"56", + 3959 => x"76", + 3960 => x"81", + 3961 => x"70", + 3962 => x"56", + 3963 => x"82", + 3964 => x"78", + 3965 => x"80", + 3966 => x"27", + 3967 => x"19", + 3968 => x"7a", + 3969 => x"5c", + 3970 => x"55", + 3971 => x"7a", + 3972 => x"5c", + 3973 => x"2e", + 3974 => x"85", + 3975 => x"94", + 3976 => x"81", + 3977 => x"73", + 3978 => x"81", + 3979 => x"7a", + 3980 => x"38", + 3981 => x"76", + 3982 => x"0c", + 3983 => x"04", + 3984 => x"7b", + 3985 => x"fc", + 3986 => x"53", + 3987 => x"bb", + 3988 => x"c0", + 3989 => x"de", + 3990 => x"fa", + 3991 => x"33", + 3992 => x"f2", + 3993 => x"08", + 3994 => x"27", + 3995 => x"15", + 3996 => x"2a", + 3997 => x"51", + 3998 => x"83", + 3999 => x"94", + 4000 => x"80", + 4001 => x"0c", + 4002 => x"2e", + 4003 => x"79", + 4004 => x"70", + 4005 => x"51", + 4006 => x"2e", + 4007 => x"52", + 4008 => x"ff", + 4009 => x"81", + 4010 => x"ff", + 4011 => x"70", + 4012 => x"ff", + 4013 => x"81", + 4014 => x"73", + 4015 => x"76", + 4016 => x"06", + 4017 => x"0c", + 4018 => x"98", + 4019 => x"58", + 4020 => x"39", + 4021 => x"54", + 4022 => x"73", + 4023 => x"cd", + 4024 => x"de", + 4025 => x"81", + 4026 => x"81", + 4027 => x"38", + 4028 => x"08", + 4029 => x"9b", + 4030 => x"c0", + 4031 => x"0c", + 4032 => x"0c", + 4033 => x"81", + 4034 => x"76", + 4035 => x"38", + 4036 => x"94", + 4037 => x"94", + 4038 => x"16", + 4039 => x"2a", + 4040 => x"51", + 4041 => x"72", + 4042 => x"38", + 4043 => x"51", + 4044 => x"81", + 4045 => x"54", + 4046 => x"08", + 4047 => x"de", + 4048 => x"a7", + 4049 => x"74", + 4050 => x"3f", + 4051 => x"08", + 4052 => x"2e", + 4053 => x"74", + 4054 => x"79", + 4055 => x"14", + 4056 => x"38", + 4057 => x"0c", + 4058 => x"94", + 4059 => x"94", + 4060 => x"83", + 4061 => x"72", + 4062 => x"38", + 4063 => x"51", + 4064 => x"81", + 4065 => x"94", + 4066 => x"91", + 4067 => x"53", + 4068 => x"81", + 4069 => x"34", + 4070 => x"39", + 4071 => x"81", + 4072 => x"05", + 4073 => x"08", + 4074 => x"08", + 4075 => x"38", + 4076 => x"0c", + 4077 => x"80", + 4078 => x"72", + 4079 => x"73", + 4080 => x"53", + 4081 => x"8c", + 4082 => x"16", + 4083 => x"38", + 4084 => x"0c", + 4085 => x"81", + 4086 => x"8b", + 4087 => x"f9", + 4088 => x"56", + 4089 => x"80", + 4090 => x"38", + 4091 => x"3d", + 4092 => x"8a", + 4093 => x"51", + 4094 => x"81", + 4095 => x"55", + 4096 => x"08", + 4097 => x"77", + 4098 => x"52", + 4099 => x"b5", + 4100 => x"c0", + 4101 => x"de", + 4102 => x"c3", + 4103 => x"33", + 4104 => x"55", + 4105 => x"24", + 4106 => x"16", + 4107 => x"2a", + 4108 => x"51", + 4109 => x"80", + 4110 => x"9c", + 4111 => x"77", + 4112 => x"3f", + 4113 => x"08", + 4114 => x"77", + 4115 => x"22", + 4116 => x"74", + 4117 => x"ce", + 4118 => x"de", + 4119 => x"74", + 4120 => x"81", + 4121 => x"85", + 4122 => x"74", + 4123 => x"38", + 4124 => x"74", + 4125 => x"de", + 4126 => x"3d", + 4127 => x"3d", + 4128 => x"3d", + 4129 => x"70", + 4130 => x"ff", + 4131 => x"c0", + 4132 => x"81", + 4133 => x"73", + 4134 => x"0d", + 4135 => x"0d", + 4136 => x"3d", + 4137 => x"71", + 4138 => x"e7", + 4139 => x"de", + 4140 => x"81", + 4141 => x"80", + 4142 => x"93", + 4143 => x"c0", + 4144 => x"51", + 4145 => x"81", + 4146 => x"53", + 4147 => x"81", + 4148 => x"52", + 4149 => x"ac", + 4150 => x"c0", + 4151 => x"de", + 4152 => x"2e", + 4153 => x"85", + 4154 => x"87", + 4155 => x"c0", + 4156 => x"74", + 4157 => x"d5", + 4158 => x"52", + 4159 => x"89", + 4160 => x"c0", + 4161 => x"70", + 4162 => x"07", + 4163 => x"81", + 4164 => x"06", + 4165 => x"54", + 4166 => x"c0", + 4167 => x"0d", + 4168 => x"0d", + 4169 => x"53", + 4170 => x"53", + 4171 => x"56", + 4172 => x"81", + 4173 => x"55", + 4174 => x"08", + 4175 => x"52", + 4176 => x"81", + 4177 => x"c0", + 4178 => x"de", + 4179 => x"38", + 4180 => x"05", + 4181 => x"2b", + 4182 => x"80", + 4183 => x"86", + 4184 => x"76", + 4185 => x"38", + 4186 => x"51", + 4187 => x"74", + 4188 => x"0c", + 4189 => x"04", + 4190 => x"63", + 4191 => x"80", + 4192 => x"ec", + 4193 => x"3d", + 4194 => x"3f", + 4195 => x"08", + 4196 => x"c0", + 4197 => x"38", + 4198 => x"73", + 4199 => x"08", + 4200 => x"13", + 4201 => x"58", + 4202 => x"26", + 4203 => x"7c", + 4204 => x"39", + 4205 => x"cc", + 4206 => x"81", + 4207 => x"de", + 4208 => x"33", + 4209 => x"81", + 4210 => x"06", + 4211 => x"75", + 4212 => x"52", + 4213 => x"05", + 4214 => x"3f", + 4215 => x"08", + 4216 => x"38", + 4217 => x"08", + 4218 => x"38", + 4219 => x"08", + 4220 => x"de", + 4221 => x"80", + 4222 => x"81", + 4223 => x"59", + 4224 => x"14", + 4225 => x"ca", + 4226 => x"39", + 4227 => x"81", + 4228 => x"57", + 4229 => x"38", + 4230 => x"18", + 4231 => x"ff", + 4232 => x"81", + 4233 => x"5b", + 4234 => x"08", + 4235 => x"7c", + 4236 => x"12", + 4237 => x"52", + 4238 => x"82", + 4239 => x"06", + 4240 => x"14", + 4241 => x"cb", + 4242 => x"c0", + 4243 => x"ff", + 4244 => x"70", + 4245 => x"82", + 4246 => x"51", + 4247 => x"b4", + 4248 => x"bb", + 4249 => x"de", + 4250 => x"0a", + 4251 => x"70", + 4252 => x"84", + 4253 => x"51", + 4254 => x"ff", + 4255 => x"56", + 4256 => x"38", + 4257 => x"7c", + 4258 => x"0c", + 4259 => x"81", + 4260 => x"74", + 4261 => x"7a", + 4262 => x"0c", + 4263 => x"04", + 4264 => x"79", + 4265 => x"05", + 4266 => x"57", + 4267 => x"81", + 4268 => x"56", + 4269 => x"08", + 4270 => x"91", + 4271 => x"75", + 4272 => x"90", + 4273 => x"81", + 4274 => x"06", + 4275 => x"87", + 4276 => x"2e", + 4277 => x"94", + 4278 => x"73", + 4279 => x"27", + 4280 => x"73", + 4281 => x"de", + 4282 => x"88", + 4283 => x"76", + 4284 => x"3f", + 4285 => x"08", + 4286 => x"0c", + 4287 => x"39", + 4288 => x"52", + 4289 => x"bf", + 4290 => x"de", + 4291 => x"2e", + 4292 => x"83", + 4293 => x"81", + 4294 => x"81", + 4295 => x"06", + 4296 => x"56", + 4297 => x"a0", + 4298 => x"81", + 4299 => x"98", + 4300 => x"94", + 4301 => x"08", + 4302 => x"c0", + 4303 => x"51", + 4304 => x"81", + 4305 => x"56", + 4306 => x"8c", + 4307 => x"17", + 4308 => x"07", + 4309 => x"18", + 4310 => x"2e", + 4311 => x"91", + 4312 => x"55", + 4313 => x"c0", + 4314 => x"0d", + 4315 => x"0d", + 4316 => x"3d", + 4317 => x"52", + 4318 => x"da", + 4319 => x"de", + 4320 => x"81", + 4321 => x"81", + 4322 => x"45", + 4323 => x"52", + 4324 => x"52", + 4325 => x"3f", + 4326 => x"08", + 4327 => x"c0", + 4328 => x"38", + 4329 => x"05", + 4330 => x"2a", + 4331 => x"51", + 4332 => x"55", + 4333 => x"38", + 4334 => x"54", + 4335 => x"81", + 4336 => x"80", + 4337 => x"70", + 4338 => x"54", + 4339 => x"81", + 4340 => x"52", + 4341 => x"c5", + 4342 => x"c0", + 4343 => x"2a", + 4344 => x"51", + 4345 => x"80", + 4346 => x"38", + 4347 => x"de", + 4348 => x"15", + 4349 => x"86", + 4350 => x"81", + 4351 => x"5c", + 4352 => x"3d", + 4353 => x"c7", + 4354 => x"de", + 4355 => x"81", + 4356 => x"80", + 4357 => x"de", + 4358 => x"73", + 4359 => x"3f", + 4360 => x"08", + 4361 => x"c0", + 4362 => x"87", + 4363 => x"39", + 4364 => x"08", + 4365 => x"38", + 4366 => x"08", + 4367 => x"77", + 4368 => x"3f", + 4369 => x"08", + 4370 => x"08", + 4371 => x"de", + 4372 => x"80", + 4373 => x"55", + 4374 => x"94", + 4375 => x"2e", + 4376 => x"53", + 4377 => x"51", + 4378 => x"81", + 4379 => x"55", + 4380 => x"78", + 4381 => x"fe", + 4382 => x"c0", + 4383 => x"81", + 4384 => x"a0", + 4385 => x"e9", + 4386 => x"53", + 4387 => x"05", + 4388 => x"51", + 4389 => x"81", + 4390 => x"54", + 4391 => x"08", + 4392 => x"78", + 4393 => x"8e", + 4394 => x"58", + 4395 => x"81", + 4396 => x"54", + 4397 => x"08", + 4398 => x"54", + 4399 => x"81", + 4400 => x"84", + 4401 => x"06", + 4402 => x"02", + 4403 => x"33", + 4404 => x"81", + 4405 => x"86", + 4406 => x"f6", + 4407 => x"74", + 4408 => x"70", + 4409 => x"c3", + 4410 => x"c0", + 4411 => x"56", + 4412 => x"08", + 4413 => x"54", + 4414 => x"08", + 4415 => x"81", + 4416 => x"82", + 4417 => x"c0", + 4418 => x"09", + 4419 => x"38", + 4420 => x"b4", + 4421 => x"b0", + 4422 => x"c0", + 4423 => x"51", + 4424 => x"81", + 4425 => x"54", + 4426 => x"08", + 4427 => x"8b", + 4428 => x"b4", + 4429 => x"b7", + 4430 => x"54", + 4431 => x"15", + 4432 => x"90", + 4433 => x"34", + 4434 => x"0a", + 4435 => x"19", + 4436 => x"9f", + 4437 => x"78", + 4438 => x"51", + 4439 => x"a0", + 4440 => x"11", + 4441 => x"05", + 4442 => x"b6", + 4443 => x"ae", + 4444 => x"15", + 4445 => x"78", + 4446 => x"53", + 4447 => x"3f", + 4448 => x"0b", + 4449 => x"77", + 4450 => x"3f", + 4451 => x"08", + 4452 => x"c0", + 4453 => x"82", + 4454 => x"52", + 4455 => x"51", + 4456 => x"3f", + 4457 => x"52", + 4458 => x"aa", + 4459 => x"90", + 4460 => x"34", + 4461 => x"0b", + 4462 => x"78", + 4463 => x"b6", + 4464 => x"c0", + 4465 => x"39", + 4466 => x"52", + 4467 => x"be", + 4468 => x"81", + 4469 => x"99", + 4470 => x"da", + 4471 => x"3d", + 4472 => x"d2", + 4473 => x"53", + 4474 => x"84", + 4475 => x"3d", + 4476 => x"3f", + 4477 => x"08", + 4478 => x"c0", + 4479 => x"38", + 4480 => x"3d", + 4481 => x"3d", + 4482 => x"cc", + 4483 => x"de", + 4484 => x"81", + 4485 => x"82", + 4486 => x"81", + 4487 => x"81", + 4488 => x"86", + 4489 => x"aa", + 4490 => x"a4", + 4491 => x"a8", + 4492 => x"05", + 4493 => x"ea", + 4494 => x"77", + 4495 => x"70", + 4496 => x"b4", + 4497 => x"3d", + 4498 => x"51", + 4499 => x"81", + 4500 => x"55", + 4501 => x"08", + 4502 => x"6f", + 4503 => x"06", + 4504 => x"a2", + 4505 => x"92", + 4506 => x"81", + 4507 => x"de", + 4508 => x"2e", + 4509 => x"81", + 4510 => x"51", + 4511 => x"81", + 4512 => x"55", + 4513 => x"08", + 4514 => x"68", + 4515 => x"a8", + 4516 => x"05", + 4517 => x"51", + 4518 => x"3f", + 4519 => x"33", + 4520 => x"8b", + 4521 => x"84", + 4522 => x"06", + 4523 => x"73", + 4524 => x"a0", + 4525 => x"8b", + 4526 => x"54", + 4527 => x"15", + 4528 => x"33", + 4529 => x"70", + 4530 => x"55", + 4531 => x"2e", + 4532 => x"6e", + 4533 => x"df", + 4534 => x"78", + 4535 => x"3f", + 4536 => x"08", + 4537 => x"ff", + 4538 => x"82", + 4539 => x"c0", + 4540 => x"80", + 4541 => x"de", + 4542 => x"78", + 4543 => x"af", + 4544 => x"c0", + 4545 => x"d4", + 4546 => x"55", + 4547 => x"08", + 4548 => x"81", + 4549 => x"73", + 4550 => x"81", + 4551 => x"63", + 4552 => x"76", + 4553 => x"3f", + 4554 => x"0b", + 4555 => x"87", + 4556 => x"c0", + 4557 => x"77", + 4558 => x"3f", + 4559 => x"08", + 4560 => x"c0", + 4561 => x"78", + 4562 => x"aa", + 4563 => x"c0", + 4564 => x"81", + 4565 => x"a8", + 4566 => x"ed", + 4567 => x"80", + 4568 => x"02", + 4569 => x"df", + 4570 => x"57", + 4571 => x"3d", + 4572 => x"96", + 4573 => x"e9", + 4574 => x"c0", + 4575 => x"de", + 4576 => x"cf", + 4577 => x"65", + 4578 => x"d4", + 4579 => x"b5", + 4580 => x"c0", + 4581 => x"de", + 4582 => x"38", + 4583 => x"05", + 4584 => x"06", + 4585 => x"73", + 4586 => x"a7", + 4587 => x"09", + 4588 => x"71", + 4589 => x"06", + 4590 => x"55", + 4591 => x"15", + 4592 => x"81", + 4593 => x"34", + 4594 => x"b4", + 4595 => x"de", + 4596 => x"74", + 4597 => x"0c", + 4598 => x"04", + 4599 => x"64", + 4600 => x"93", + 4601 => x"52", + 4602 => x"d1", + 4603 => x"de", + 4604 => x"81", + 4605 => x"80", + 4606 => x"58", + 4607 => x"3d", + 4608 => x"c8", + 4609 => x"de", + 4610 => x"81", + 4611 => x"b4", + 4612 => x"c7", + 4613 => x"a0", + 4614 => x"55", + 4615 => x"84", + 4616 => x"17", + 4617 => x"2b", + 4618 => x"96", + 4619 => x"b0", + 4620 => x"54", + 4621 => x"15", + 4622 => x"ff", + 4623 => x"81", + 4624 => x"55", + 4625 => x"c0", + 4626 => x"0d", + 4627 => x"0d", + 4628 => x"5a", + 4629 => x"3d", + 4630 => x"99", + 4631 => x"81", + 4632 => x"c0", + 4633 => x"c0", + 4634 => x"81", + 4635 => x"07", + 4636 => x"55", + 4637 => x"2e", + 4638 => x"81", + 4639 => x"55", + 4640 => x"2e", + 4641 => x"7b", + 4642 => x"80", + 4643 => x"70", + 4644 => x"be", + 4645 => x"de", + 4646 => x"81", + 4647 => x"80", + 4648 => x"52", + 4649 => x"dc", + 4650 => x"c0", + 4651 => x"de", + 4652 => x"38", + 4653 => x"08", + 4654 => x"08", + 4655 => x"56", + 4656 => x"19", + 4657 => x"59", + 4658 => x"74", + 4659 => x"56", + 4660 => x"ec", + 4661 => x"75", + 4662 => x"74", + 4663 => x"2e", + 4664 => x"16", + 4665 => x"33", + 4666 => x"73", + 4667 => x"38", + 4668 => x"84", + 4669 => x"06", + 4670 => x"7a", + 4671 => x"76", + 4672 => x"07", + 4673 => x"54", + 4674 => x"80", + 4675 => x"80", + 4676 => x"7b", + 4677 => x"53", + 4678 => x"93", + 4679 => x"c0", + 4680 => x"de", + 4681 => x"38", + 4682 => x"55", + 4683 => x"56", + 4684 => x"8b", + 4685 => x"56", + 4686 => x"83", + 4687 => x"75", + 4688 => x"51", + 4689 => x"3f", + 4690 => x"08", + 4691 => x"81", + 4692 => x"98", + 4693 => x"e6", + 4694 => x"53", + 4695 => x"b8", + 4696 => x"3d", + 4697 => x"3f", + 4698 => x"08", + 4699 => x"08", + 4700 => x"de", + 4701 => x"98", + 4702 => x"a0", + 4703 => x"70", + 4704 => x"ae", + 4705 => x"6d", + 4706 => x"81", + 4707 => x"57", + 4708 => x"74", + 4709 => x"38", + 4710 => x"81", + 4711 => x"81", + 4712 => x"52", + 4713 => x"89", + 4714 => x"c0", + 4715 => x"a5", + 4716 => x"33", + 4717 => x"54", + 4718 => x"3f", + 4719 => x"08", + 4720 => x"38", + 4721 => x"76", + 4722 => x"05", + 4723 => x"39", + 4724 => x"08", + 4725 => x"15", + 4726 => x"ff", + 4727 => x"73", + 4728 => x"38", + 4729 => x"83", + 4730 => x"56", + 4731 => x"75", + 4732 => x"81", + 4733 => x"33", + 4734 => x"2e", + 4735 => x"52", + 4736 => x"51", + 4737 => x"3f", + 4738 => x"08", + 4739 => x"ff", + 4740 => x"38", + 4741 => x"88", + 4742 => x"8a", + 4743 => x"38", + 4744 => x"ec", + 4745 => x"75", + 4746 => x"74", + 4747 => x"73", + 4748 => x"05", + 4749 => x"17", + 4750 => x"70", + 4751 => x"34", + 4752 => x"70", + 4753 => x"ff", + 4754 => x"55", + 4755 => x"26", + 4756 => x"8b", + 4757 => x"86", + 4758 => x"e5", + 4759 => x"38", + 4760 => x"99", + 4761 => x"05", + 4762 => x"70", + 4763 => x"73", + 4764 => x"81", + 4765 => x"ff", + 4766 => x"ed", + 4767 => x"80", + 4768 => x"91", + 4769 => x"55", + 4770 => x"3f", + 4771 => x"08", + 4772 => x"c0", + 4773 => x"38", + 4774 => x"51", + 4775 => x"3f", + 4776 => x"08", + 4777 => x"c0", + 4778 => x"76", + 4779 => x"67", + 4780 => x"34", + 4781 => x"81", + 4782 => x"84", + 4783 => x"06", + 4784 => x"80", + 4785 => x"2e", + 4786 => x"81", + 4787 => x"ff", + 4788 => x"81", + 4789 => x"54", + 4790 => x"08", + 4791 => x"53", + 4792 => x"08", + 4793 => x"ff", + 4794 => x"67", + 4795 => x"8b", + 4796 => x"53", + 4797 => x"51", + 4798 => x"3f", + 4799 => x"0b", + 4800 => x"79", + 4801 => x"ee", + 4802 => x"c0", + 4803 => x"55", + 4804 => x"c0", + 4805 => x"0d", + 4806 => x"0d", + 4807 => x"88", + 4808 => x"05", + 4809 => x"fc", + 4810 => x"54", + 4811 => x"d2", + 4812 => x"de", + 4813 => x"81", + 4814 => x"82", + 4815 => x"1a", + 4816 => x"82", + 4817 => x"80", + 4818 => x"8c", + 4819 => x"78", + 4820 => x"1a", + 4821 => x"2a", + 4822 => x"51", + 4823 => x"90", + 4824 => x"82", + 4825 => x"58", + 4826 => x"81", + 4827 => x"39", + 4828 => x"22", + 4829 => x"70", + 4830 => x"56", + 4831 => x"fb", + 4832 => x"14", + 4833 => x"30", + 4834 => x"9f", + 4835 => x"c0", + 4836 => x"19", + 4837 => x"5a", + 4838 => x"81", + 4839 => x"38", + 4840 => x"77", + 4841 => x"82", + 4842 => x"56", + 4843 => x"74", + 4844 => x"ff", + 4845 => x"81", + 4846 => x"55", + 4847 => x"75", + 4848 => x"82", + 4849 => x"c0", + 4850 => x"ff", + 4851 => x"de", + 4852 => x"2e", + 4853 => x"81", + 4854 => x"8e", + 4855 => x"56", + 4856 => x"09", + 4857 => x"38", + 4858 => x"59", + 4859 => x"77", + 4860 => x"06", + 4861 => x"87", + 4862 => x"39", + 4863 => x"ba", + 4864 => x"55", + 4865 => x"2e", + 4866 => x"15", + 4867 => x"2e", + 4868 => x"83", + 4869 => x"75", + 4870 => x"7e", + 4871 => x"a8", + 4872 => x"c0", + 4873 => x"de", + 4874 => x"ce", + 4875 => x"16", + 4876 => x"56", + 4877 => x"38", + 4878 => x"19", + 4879 => x"8c", + 4880 => x"7d", + 4881 => x"38", + 4882 => x"0c", + 4883 => x"0c", + 4884 => x"80", + 4885 => x"73", + 4886 => x"98", + 4887 => x"05", + 4888 => x"57", + 4889 => x"26", + 4890 => x"7b", + 4891 => x"0c", + 4892 => x"81", + 4893 => x"84", + 4894 => x"54", + 4895 => x"c0", + 4896 => x"0d", + 4897 => x"0d", + 4898 => x"88", + 4899 => x"05", + 4900 => x"54", + 4901 => x"c5", + 4902 => x"56", + 4903 => x"de", + 4904 => x"8b", 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x"61", + 4964 => x"55", + 4965 => x"27", + 4966 => x"93", + 4967 => x"80", + 4968 => x"38", + 4969 => x"70", + 4970 => x"43", + 4971 => x"95", + 4972 => x"06", + 4973 => x"2e", + 4974 => x"77", + 4975 => x"74", + 4976 => x"83", + 4977 => x"06", + 4978 => x"82", + 4979 => x"2e", + 4980 => x"78", + 4981 => x"2e", + 4982 => x"80", + 4983 => x"ae", + 4984 => x"2a", + 4985 => x"81", + 4986 => x"56", + 4987 => x"2e", + 4988 => x"77", + 4989 => x"81", + 4990 => x"79", + 4991 => x"70", + 4992 => x"5a", + 4993 => x"86", + 4994 => x"27", + 4995 => x"52", + 4996 => x"f6", + 4997 => x"de", + 4998 => x"29", + 4999 => x"70", + 5000 => x"55", + 5001 => x"0b", + 5002 => x"08", + 5003 => x"05", + 5004 => x"ff", + 5005 => x"27", + 5006 => x"88", + 5007 => x"ae", + 5008 => x"2a", + 5009 => x"81", + 5010 => x"56", + 5011 => x"2e", + 5012 => x"77", + 5013 => x"81", + 5014 => x"79", + 5015 => x"70", + 5016 => x"5a", + 5017 => x"86", + 5018 => x"27", + 5019 => x"52", + 5020 => x"f6", + 5021 => x"de", + 5022 => x"84", + 5023 => x"de", + 5024 => x"f5", + 5025 => x"81", + 5026 => x"c0", + 5027 => x"de", + 5028 => x"71", + 5029 => x"83", + 5030 => x"5e", + 5031 => x"89", + 5032 => x"5c", + 5033 => x"1c", + 5034 => x"05", + 5035 => x"ff", + 5036 => x"70", + 5037 => x"31", + 5038 => x"57", + 5039 => x"83", + 5040 => x"06", + 5041 => x"1c", + 5042 => x"5c", + 5043 => x"1d", + 5044 => x"29", + 5045 => x"31", + 5046 => x"55", + 5047 => x"87", + 5048 => x"7c", + 5049 => x"7a", + 5050 => x"31", + 5051 => x"f5", + 5052 => x"de", + 5053 => x"7d", + 5054 => x"81", + 5055 => x"81", + 5056 => x"83", + 5057 => x"80", + 5058 => x"87", + 5059 => x"81", + 5060 => x"fd", + 5061 => x"f8", + 5062 => x"2e", + 5063 => x"80", + 5064 => x"ff", + 5065 => x"de", + 5066 => x"a0", + 5067 => x"38", + 5068 => x"74", + 5069 => x"86", + 5070 => x"fd", + 5071 => x"81", + 5072 => x"80", + 5073 => x"83", + 5074 => x"39", + 5075 => x"08", + 5076 => x"92", + 5077 => x"b8", + 5078 => x"59", + 5079 => x"27", + 5080 => x"86", + 5081 => x"55", + 5082 => x"09", + 5083 => x"38", + 5084 => x"f5", + 5085 => x"38", + 5086 => x"55", + 5087 => x"86", + 5088 => x"80", + 5089 => x"7a", + 5090 => x"b9", + 5091 => x"81", + 5092 => x"7a", + 5093 => x"8a", + 5094 => x"52", + 5095 => x"ff", + 5096 => x"79", + 5097 => x"7b", + 5098 => x"06", + 5099 => x"51", + 5100 => x"3f", + 5101 => x"1c", + 5102 => x"32", + 5103 => x"96", + 5104 => x"06", + 5105 => x"91", + 5106 => x"a1", + 5107 => x"55", + 5108 => x"ff", + 5109 => x"74", + 5110 => x"06", + 5111 => x"51", + 5112 => x"3f", + 5113 => x"52", + 5114 => x"ff", + 5115 => x"f8", + 5116 => x"34", + 5117 => x"1b", + 5118 => x"d9", + 5119 => x"52", + 5120 => x"ff", + 5121 => x"60", + 5122 => x"51", + 5123 => x"3f", + 5124 => x"09", + 5125 => x"cb", + 5126 => x"b2", + 5127 => x"c3", + 5128 => x"a0", + 5129 => x"52", + 5130 => x"ff", + 5131 => x"82", + 5132 => x"51", + 5133 => x"3f", + 5134 => x"1b", + 5135 => x"95", + 5136 => x"b2", + 5137 => x"a0", + 5138 => x"80", + 5139 => x"1c", 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x"7d", + 5199 => x"81", + 5200 => x"f8", + 5201 => x"ff", + 5202 => x"ff", + 5203 => x"51", + 5204 => x"3f", + 5205 => x"88", + 5206 => x"39", + 5207 => x"f8", + 5208 => x"2e", + 5209 => x"55", + 5210 => x"51", + 5211 => x"3f", + 5212 => x"57", + 5213 => x"83", + 5214 => x"76", + 5215 => x"7a", + 5216 => x"ff", + 5217 => x"81", + 5218 => x"82", + 5219 => x"80", + 5220 => x"c0", + 5221 => x"51", + 5222 => x"3f", + 5223 => x"78", + 5224 => x"74", + 5225 => x"18", + 5226 => x"2e", + 5227 => x"79", + 5228 => x"2e", + 5229 => x"55", + 5230 => x"62", + 5231 => x"74", + 5232 => x"75", + 5233 => x"7e", + 5234 => x"b8", + 5235 => x"c0", + 5236 => x"38", + 5237 => x"78", + 5238 => x"74", + 5239 => x"56", + 5240 => x"93", + 5241 => x"66", + 5242 => x"26", + 5243 => x"56", + 5244 => x"83", + 5245 => x"64", + 5246 => x"77", + 5247 => x"84", + 5248 => x"52", + 5249 => x"9d", + 5250 => x"d4", + 5251 => x"51", + 5252 => x"3f", + 5253 => x"55", + 5254 => x"81", + 5255 => x"34", + 5256 => x"16", + 5257 => x"16", + 5258 => x"16", + 5259 => x"05", + 5260 => x"c1", + 5261 => x"fe", + 5262 => x"fe", + 5263 => x"34", + 5264 => x"08", + 5265 => x"07", + 5266 => x"16", + 5267 => x"c0", + 5268 => x"34", + 5269 => x"c6", + 5270 => x"9c", + 5271 => x"52", + 5272 => x"51", + 5273 => x"3f", + 5274 => x"53", + 5275 => x"51", + 5276 => x"3f", + 5277 => x"de", + 5278 => x"38", + 5279 => x"52", + 5280 => x"99", + 5281 => x"56", + 5282 => x"08", + 5283 => x"39", + 5284 => x"39", + 5285 => x"39", + 5286 => x"08", + 5287 => x"de", + 5288 => x"3d", + 5289 => x"3d", + 5290 => x"5b", + 5291 => x"60", + 5292 => x"57", + 5293 => x"25", + 5294 => x"3d", + 5295 => x"55", + 5296 => x"15", + 5297 => x"c9", + 5298 => x"81", + 5299 => x"06", + 5300 => x"3d", + 5301 => x"8d", + 5302 => x"74", + 5303 => x"05", + 5304 => x"17", + 5305 => x"2e", + 5306 => x"c9", + 5307 => x"34", + 5308 => x"83", + 5309 => x"74", + 5310 => x"0c", + 5311 => x"04", + 5312 => x"73", + 5313 => x"26", + 5314 => x"71", + 5315 => x"c6", + 5316 => x"71", + 5317 => x"cf", + 5318 => x"80", + 5319 => x"fc", + 5320 => x"39", + 5321 => x"51", + 5322 => x"81", + 5323 => x"80", + 5324 => x"d0", + 5325 => x"e4", + 5326 => x"c4", + 5327 => x"39", + 5328 => x"51", + 5329 => x"81", + 5330 => x"80", + 5331 => x"d1", + 5332 => x"c8", + 5333 => x"98", + 5334 => x"39", + 5335 => x"51", + 5336 => x"d1", + 5337 => x"39", + 5338 => x"51", + 5339 => x"d2", + 5340 => x"39", + 5341 => x"51", + 5342 => x"d2", + 5343 => x"39", + 5344 => x"51", + 5345 => x"d2", + 5346 => x"39", + 5347 => x"51", + 5348 => x"d3", + 5349 => x"39", + 5350 => x"51", + 5351 => x"3f", + 5352 => x"04", + 5353 => x"77", + 5354 => x"74", + 5355 => x"8a", + 5356 => x"75", + 5357 => x"51", + 5358 => x"e8", + 5359 => x"fe", + 5360 => x"81", + 5361 => x"52", + 5362 => x"eb", + 5363 => x"de", + 5364 => x"79", + 5365 => x"81", + 5366 => x"ff", + 5367 => x"87", + 5368 => x"f5", + 5369 => x"7f", + 5370 => x"05", + 5371 => x"33", + 5372 => x"66", + 5373 => x"5a", + 5374 => x"78", + 5375 => x"dc", + 5376 => x"a0", + 5377 => x"e4", + 5378 => x"b4", + 5379 => x"74", + 5380 => x"fc", + 5381 => x"2e", + 5382 => x"a0", + 5383 => x"80", + 5384 => x"16", + 5385 => x"27", + 5386 => x"22", + 5387 => x"e8", + 5388 => x"f0", + 5389 => x"81", + 5390 => x"ff", + 5391 => x"82", + 5392 => x"c3", + 5393 => x"53", + 5394 => x"8e", + 5395 => x"52", + 5396 => x"51", + 5397 => x"3f", + 5398 => x"d3", + 5399 => x"85", + 5400 => x"15", + 5401 => x"74", + 5402 => x"78", + 5403 => x"72", + 5404 => x"d3", + 5405 => x"8b", + 5406 => x"39", + 5407 => x"51", + 5408 => x"3f", + 5409 => x"a0", + 5410 => x"af", + 5411 => x"39", + 5412 => x"51", + 5413 => x"3f", + 5414 => x"77", + 5415 => x"74", + 5416 => x"79", + 5417 => x"55", + 5418 => x"27", + 5419 => x"80", + 5420 => x"73", + 5421 => x"85", + 5422 => x"83", + 5423 => x"fe", + 5424 => x"81", + 5425 => x"39", + 5426 => x"51", + 5427 => x"3f", + 5428 => x"1a", + 5429 => x"f9", + 5430 => x"de", + 5431 => x"2b", + 5432 => x"51", + 5433 => x"2e", + 5434 => x"a5", + 5435 => x"9d", + 5436 => x"c0", + 5437 => x"70", + 5438 => x"a0", + 5439 => x"70", + 5440 => x"2a", + 5441 => x"51", + 5442 => x"2e", + 5443 => x"dd", + 5444 => x"2e", + 5445 => x"85", + 5446 => x"8c", + 5447 => x"53", + 5448 => x"fd", + 5449 => x"53", + 5450 => x"c0", + 5451 => x"0d", + 5452 => x"0d", + 5453 => x"05", + 5454 => x"33", + 5455 => x"70", + 5456 => x"25", + 5457 => x"74", + 5458 => x"51", + 5459 => x"56", + 5460 => x"80", + 5461 => x"53", + 5462 => x"3d", + 5463 => x"ff", + 5464 => x"81", + 5465 => x"56", + 5466 => x"08", + 5467 => x"de", + 5468 => x"c0", + 5469 => x"81", + 5470 => x"59", + 5471 => x"05", + 5472 => x"53", + 5473 => x"51", + 5474 => x"81", + 5475 => x"56", + 5476 => x"08", + 5477 => x"55", + 5478 => x"89", + 5479 => x"75", + 5480 => x"d8", + 5481 => x"d8", + 5482 => x"85", + 5483 => x"70", + 5484 => x"25", + 5485 => x"80", + 5486 => x"74", + 5487 => x"38", + 5488 => x"53", + 5489 => x"88", + 5490 => x"51", + 5491 => x"75", + 5492 => x"de", + 5493 => x"3d", + 5494 => x"3d", + 5495 => x"84", + 5496 => x"33", + 5497 => x"57", + 5498 => x"52", + 5499 => x"c1", + 5500 => x"c0", + 5501 => x"75", + 5502 => x"38", + 5503 => x"98", + 5504 => x"60", + 5505 => x"81", + 5506 => x"7e", + 5507 => x"77", + 5508 => x"c0", + 5509 => x"39", + 5510 => x"81", + 5511 => x"89", + 5512 => x"fc", + 5513 => x"9b", + 5514 => x"d4", + 5515 => x"d4", + 5516 => x"ff", + 5517 => x"81", + 5518 => x"51", + 5519 => x"3f", + 5520 => x"54", + 5521 => x"53", + 5522 => x"33", + 5523 => x"c0", + 5524 => x"d0", + 5525 => x"2e", + 5526 => x"fb", + 5527 => x"3d", + 5528 => x"3d", + 5529 => x"96", + 5530 => x"ff", + 5531 => x"81", + 5532 => x"ad", + 5533 => x"dc", + 5534 => x"a5", + 5535 => x"fe", + 5536 => x"72", + 5537 => x"81", + 5538 => x"71", + 5539 => x"38", + 5540 => x"f2", + 5541 => x"d4", + 5542 => x"f4", + 5543 => x"51", + 5544 => x"3f", + 5545 => x"70", + 5546 => x"52", + 5547 => x"95", + 5548 => x"fe", + 5549 => x"81", + 5550 => x"fe", + 5551 => x"80", + 5552 => x"dd", + 5553 => x"2a", + 5554 => x"51", + 5555 => x"2e", + 5556 => x"51", + 5557 => x"3f", + 5558 => x"51", + 5559 => x"3f", + 5560 => x"f1", + 5561 => x"84", + 5562 => x"06", + 5563 => x"80", + 5564 => x"81", + 5565 => x"a9", + 5566 => x"b0", + 5567 => x"a1", + 5568 => x"fe", + 5569 => x"72", + 5570 => x"81", + 5571 => x"71", + 5572 => x"38", + 5573 => x"f1", + 5574 => x"d5", + 5575 => x"f3", + 5576 => x"51", + 5577 => x"3f", + 5578 => x"70", + 5579 => x"52", + 5580 => x"95", + 5581 => x"fe", + 5582 => x"81", + 5583 => x"fe", + 5584 => x"80", + 5585 => x"d9", + 5586 => x"2a", + 5587 => x"51", + 5588 => x"2e", + 5589 => x"51", + 5590 => x"3f", + 5591 => x"51", + 5592 => x"3f", + 5593 => x"f0", + 5594 => x"88", + 5595 => x"06", + 5596 => x"80", + 5597 => x"81", + 5598 => x"a5", + 5599 => x"80", + 5600 => x"9d", + 5601 => x"fe", + 5602 => x"fe", + 5603 => x"84", + 5604 => x"fa", + 5605 => x"70", + 5606 => x"55", + 5607 => x"2e", + 5608 => x"8e", + 5609 => x"0c", + 5610 => x"53", + 5611 => x"81", + 5612 => x"74", + 5613 => x"ff", + 5614 => x"53", + 5615 => x"83", + 5616 => x"74", + 5617 => x"38", + 5618 => x"75", + 5619 => x"53", + 5620 => x"09", + 5621 => x"38", + 5622 => x"81", + 5623 => x"80", + 5624 => x"29", + 5625 => x"05", + 5626 => x"70", + 5627 => x"fe", + 5628 => x"81", + 5629 => x"8b", + 5630 => x"33", + 5631 => x"2e", + 5632 => x"81", + 5633 => x"ff", + 5634 => x"94", + 5635 => x"38", + 5636 => x"81", + 5637 => x"88", + 5638 => x"fb", + 5639 => x"79", + 5640 => x"56", + 5641 => x"51", + 5642 => x"3f", + 5643 => x"33", + 5644 => x"38", + 5645 => x"d6", + 5646 => x"f5", + 5647 => x"b9", + 5648 => x"de", + 5649 => x"70", + 5650 => x"08", + 5651 => x"82", + 5652 => x"51", + 5653 => x"db", + 5654 => x"db", + 5655 => x"73", + 5656 => x"81", + 5657 => x"81", + 5658 => x"74", + 5659 => x"f4", + 5660 => x"de", + 5661 => x"2e", + 5662 => x"de", + 5663 => x"fe", + 5664 => x"8e", + 5665 => x"c4", + 5666 => x"3f", + 5667 => x"db", + 5668 => x"db", + 5669 => x"73", + 5670 => x"81", + 5671 => x"74", + 5672 => x"ff", + 5673 => x"80", + 5674 => x"c0", + 5675 => x"0d", + 5676 => x"0d", + 5677 => x"81", + 5678 => x"40", + 5679 => x"7c", + 5680 => x"d7", + 5681 => x"c0", + 5682 => x"06", + 5683 => x"2e", + 5684 => x"a2", + 5685 => x"d0", + 5686 => x"70", + 5687 => x"82", + 5688 => x"53", + 5689 => x"df", + 5690 => x"b7", + 5691 => x"de", + 5692 => x"2e", + 5693 => x"d6", + 5694 => x"bc", + 5695 => x"40", + 5696 => x"8c", + 5697 => x"b8", + 5698 => x"70", + 5699 => x"f8", + 5700 => x"fe", + 5701 => x"3d", + 5702 => x"51", + 5703 => x"81", + 5704 => x"90", + 5705 => x"2c", + 5706 => x"80", + 5707 => x"ce", + 5708 => x"c3", + 5709 => x"38", + 5710 => x"83", + 5711 => x"ab", + 5712 => x"78", + 5713 => x"af", + 5714 => x"24", + 5715 => x"80", + 5716 => x"38", + 5717 => x"78", + 5718 => x"82", + 5719 => x"2e", + 5720 => x"8f", + 5721 => x"80", + 5722 => x"87", + 5723 => x"c0", + 5724 => x"78", + 5725 => x"a9", + 5726 => x"2e", + 5727 => x"8f", + 5728 => x"80", + 5729 => x"9e", + 5730 => x"c2", + 5731 => x"38", + 5732 => x"78", + 5733 => x"8d", + 5734 => x"80", + 5735 => x"38", + 5736 => x"2e", + 5737 => x"78", + 5738 => x"8b", + 5739 => x"c5", + 5740 => x"38", + 5741 => x"78", + 5742 => x"8d", + 5743 => x"80", + 5744 => x"ab", + 5745 => x"39", + 5746 => x"2e", + 5747 => x"78", + 5748 => x"92", + 5749 => x"f8", + 5750 => x"38", + 5751 => x"2e", + 5752 => x"8e", + 5753 => x"81", + 5754 => x"b4", + 5755 => x"85", + 5756 => x"38", + 5757 => x"b7", + 5758 => x"11", + 5759 => x"05", + 5760 => x"95", + 5761 => x"c0", + 5762 => x"81", + 5763 => x"90", + 5764 => x"3d", + 5765 => x"53", + 5766 => x"51", + 5767 => x"3f", + 5768 => x"08", + 5769 => x"38", + 5770 => x"83", + 5771 => x"02", + 5772 => x"33", + 5773 => x"cf", + 5774 => x"ff", + 5775 => x"81", + 5776 => x"81", + 5777 => x"78", + 5778 => x"d7", + 5779 => x"f9", + 5780 => x"5f", + 5781 => x"81", + 5782 => x"8c", + 5783 => x"3d", + 5784 => x"53", + 5785 => x"51", + 5786 => x"3f", + 5787 => x"08", + 5788 => x"8d", + 5789 => x"80", + 5790 => x"cf", + 5791 => x"ff", + 5792 => x"81", + 5793 => x"52", + 5794 => x"51", + 5795 => x"b7", + 5796 => x"11", + 5797 => x"05", + 5798 => x"fd", + 5799 => x"c0", + 5800 => x"87", + 5801 => x"26", + 5802 => x"b7", + 5803 => x"11", + 5804 => x"05", + 5805 => x"e1", + 5806 => x"c0", + 5807 => x"81", + 5808 => x"43", + 5809 => x"d7", + 5810 => x"51", + 5811 => x"3f", + 5812 => x"05", + 5813 => x"52", + 5814 => x"29", + 5815 => x"05", + 5816 => x"fb", + 5817 => x"c0", + 5818 => x"38", + 5819 => x"51", + 5820 => x"3f", + 5821 => x"89", + 5822 => x"fe", + 5823 => x"fe", + 5824 => x"81", + 5825 => x"b8", + 5826 => x"05", + 5827 => x"e6", + 5828 => x"53", + 5829 => x"08", + 5830 => x"f4", + 5831 => x"d5", + 5832 => x"fe", + 5833 => x"fe", + 5834 => x"81", + 5835 => x"b8", + 5836 => x"05", + 5837 => x"e5", + 5838 => x"de", + 5839 => x"3d", + 5840 => x"52", + 5841 => x"ec", + 5842 => x"c0", + 5843 => x"fe", + 5844 => x"59", + 5845 => x"3f", + 5846 => x"58", + 5847 => x"57", + 5848 => x"55", + 5849 => x"08", + 5850 => x"54", + 5851 => x"52", + 5852 => x"e6", + 5853 => x"c0", + 5854 => x"fb", + 5855 => x"de", + 5856 => x"ee", + 5857 => x"f9", + 5858 => x"fe", + 5859 => x"fe", + 5860 => x"fe", + 5861 => x"81", + 5862 => x"80", + 5863 => x"38", + 5864 => x"f0", + 5865 => x"f8", + 5866 => x"fe", + 5867 => x"de", + 5868 => x"2e", + 5869 => x"b7", + 5870 => x"11", + 5871 => x"05", + 5872 => x"d5", + 5873 => x"c0", + 5874 => x"81", + 5875 => x"42", + 5876 => x"51", + 5877 => x"3f", + 5878 => x"5a", + 5879 => x"88", + 5880 => x"59", + 5881 => x"84", + 5882 => x"7a", + 5883 => x"38", + 5884 => x"b7", + 5885 => x"11", + 5886 => x"05", + 5887 => x"99", + 5888 => x"c0", + 5889 => x"38", + 5890 => x"33", + 5891 => x"2e", + 5892 => x"db", + 5893 => x"80", + 5894 => x"db", + 5895 => x"78", + 5896 => x"38", + 5897 => x"08", + 5898 => x"81", + 5899 => x"59", + 5900 => x"88", + 5901 => x"9c", + 5902 => x"39", + 5903 => x"33", + 5904 => x"2e", + 5905 => x"db", + 5906 => x"9a", + 5907 => x"d2", + 5908 => x"80", + 5909 => x"81", + 5910 => x"44", + 5911 => x"db", + 5912 => x"80", + 5913 => x"3d", + 5914 => x"53", + 5915 => x"51", + 5916 => x"3f", + 5917 => x"08", + 5918 => x"81", + 5919 => x"59", + 5920 => x"89", + 5921 => x"90", + 5922 => x"cc", + 5923 => x"d5", + 5924 => x"80", + 5925 => x"81", + 5926 => x"43", + 5927 => x"db", + 5928 => x"78", + 5929 => x"38", + 5930 => x"08", + 5931 => x"81", + 5932 => x"59", + 5933 => x"88", + 5934 => x"a8", + 5935 => x"39", + 5936 => x"33", + 5937 => x"2e", + 5938 => x"db", + 5939 => x"88", + 5940 => x"bc", + 5941 => x"43", + 5942 => x"ec", + 5943 => x"f8", + 5944 => x"fc", + 5945 => x"de", + 5946 => x"2e", + 5947 => x"62", + 5948 => x"88", + 5949 => x"81", + 5950 => x"2e", + 5951 => x"80", + 5952 => x"79", + 5953 => x"38", + 5954 => x"d7", + 5955 => x"f4", + 5956 => x"55", + 5957 => x"53", + 5958 => x"51", + 5959 => x"81", + 5960 => x"86", + 5961 => x"3d", + 5962 => x"53", + 5963 => x"51", + 5964 => x"3f", + 5965 => x"08", + 5966 => x"c5", + 5967 => x"fe", + 5968 => x"fe", + 5969 => x"fe", + 5970 => x"81", + 5971 => x"80", + 5972 => x"63", + 5973 => x"cb", + 5974 => x"34", + 5975 => x"44", + 5976 => x"f0", + 5977 => x"f8", + 5978 => x"fb", + 5979 => x"de", + 5980 => x"38", + 5981 => x"63", + 5982 => x"52", + 5983 => x"51", + 5984 => x"3f", + 5985 => x"79", + 5986 => x"f2", + 5987 => x"79", + 5988 => x"ae", + 5989 => x"38", + 5990 => x"a0", + 5991 => x"fe", + 5992 => x"fe", + 5993 => x"fe", + 5994 => x"81", + 5995 => x"80", + 5996 => x"63", + 5997 => x"cb", + 5998 => x"34", + 5999 => x"44", + 6000 => x"81", + 6001 => x"fe", + 6002 => x"ff", + 6003 => x"3d", + 6004 => x"53", + 6005 => x"51", + 6006 => x"3f", + 6007 => x"08", + 6008 => x"9d", + 6009 => x"fe", + 6010 => x"fe", + 6011 => x"fe", + 6012 => x"81", + 6013 => x"80", + 6014 => x"60", + 6015 => x"05", + 6016 => x"82", + 6017 => x"78", + 6018 => x"fe", + 6019 => x"fe", + 6020 => x"fe", + 6021 => x"81", + 6022 => x"df", + 6023 => x"39", + 6024 => x"54", + 6025 => x"94", + 6026 => x"f8", + 6027 => x"52", + 6028 => x"f8", + 6029 => x"45", + 6030 => x"78", + 6031 => x"c1", + 6032 => x"26", + 6033 => x"82", + 6034 => x"39", + 6035 => x"e4", + 6036 => x"f8", + 6037 => x"fb", + 6038 => x"de", + 6039 => x"2e", + 6040 => x"59", + 6041 => x"22", + 6042 => x"05", + 6043 => x"41", + 6044 => x"81", + 6045 => x"fe", + 6046 => x"ff", + 6047 => x"3d", + 6048 => x"53", + 6049 => x"51", + 6050 => x"3f", + 6051 => x"08", + 6052 => x"ed", + 6053 => x"fe", + 6054 => x"fe", + 6055 => x"fe", + 6056 => x"81", + 6057 => x"80", + 6058 => x"60", + 6059 => x"59", + 6060 => x"41", + 6061 => x"e4", + 6062 => x"f8", + 6063 => x"fa", + 6064 => x"de", + 6065 => x"38", + 6066 => x"60", + 6067 => x"52", + 6068 => x"51", + 6069 => x"3f", + 6070 => x"79", + 6071 => x"9e", + 6072 => x"79", + 6073 => x"ae", + 6074 => x"38", + 6075 => x"9c", + 6076 => x"fe", + 6077 => x"fe", + 6078 => x"fe", + 6079 => x"81", + 6080 => x"80", + 6081 => x"60", + 6082 => x"59", + 6083 => x"41", + 6084 => x"81", + 6085 => x"fe", + 6086 => x"ff", + 6087 => x"3d", + 6088 => x"53", + 6089 => x"51", + 6090 => x"3f", + 6091 => x"08", + 6092 => x"81", + 6093 => x"59", + 6094 => x"89", + 6095 => x"8c", + 6096 => x"cd", + 6097 => x"d5", + 6098 => x"80", + 6099 => x"81", + 6100 => x"44", + 6101 => x"db", + 6102 => x"78", + 6103 => x"38", + 6104 => x"08", + 6105 => x"81", + 6106 => x"59", + 6107 => x"88", + 6108 => x"a4", + 6109 => x"39", + 6110 => x"33", + 6111 => x"2e", + 6112 => x"db", + 6113 => x"89", + 6114 => x"bc", + 6115 => x"05", + 6116 => x"fe", + 6117 => x"fe", + 6118 => x"fe", + 6119 => x"81", + 6120 => x"80", + 6121 => x"db", + 6122 => x"78", + 6123 => x"38", + 6124 => x"08", + 6125 => x"39", + 6126 => x"33", + 6127 => x"2e", + 6128 => x"db", + 6129 => x"bb", + 6130 => x"d6", + 6131 => x"80", + 6132 => x"81", + 6133 => x"43", + 6134 => x"db", + 6135 => x"78", + 6136 => x"38", + 6137 => x"08", + 6138 => x"81", + 6139 => x"59", + 6140 => x"88", + 6141 => x"b0", + 6142 => x"39", + 6143 => x"08", + 6144 => x"b7", + 6145 => x"11", + 6146 => x"05", + 6147 => x"89", + 6148 => x"c0", + 6149 => x"81", + 6150 => x"42", + 6151 => x"51", + 6152 => x"3f", + 6153 => x"63", + 6154 => x"79", + 6155 => x"62", + 6156 => x"06", + 6157 => x"53", + 6158 => x"d8", + 6159 => x"f3", + 6160 => x"1a", + 6161 => x"81", + 6162 => x"b9", + 6163 => x"cc", + 6164 => x"ec", + 6165 => x"fe", + 6166 => x"f1", + 6167 => x"d8", + 6168 => x"ed", + 6169 => x"51", + 6170 => x"3f", + 6171 => x"84", + 6172 => x"87", + 6173 => x"0c", + 6174 => x"0b", + 6175 => x"94", + 6176 => x"fc", + 6177 => x"b8", + 6178 => x"39", + 6179 => x"51", + 6180 => x"3f", + 6181 => x"0b", + 6182 => x"84", + 6183 => x"83", + 6184 => x"94", + 6185 => x"d9", + 6186 => x"fe", + 6187 => x"fe", + 6188 => x"fe", + 6189 => x"81", + 6190 => x"80", + 6191 => x"38", + 6192 => x"d9", + 6193 => x"f2", + 6194 => x"59", + 6195 => x"3d", + 6196 => x"53", + 6197 => x"51", + 6198 => x"3f", + 6199 => x"08", + 6200 => x"9d", + 6201 => x"81", + 6202 => x"fe", + 6203 => x"63", + 6204 => x"81", + 6205 => x"5e", + 6206 => x"08", + 6207 => x"81", + 6208 => x"c0", + 6209 => x"d9", + 6210 => x"f2", + 6211 => x"f1", + 6212 => x"f8", + 6213 => x"a8", + 6214 => x"e5", + 6215 => x"39", + 6216 => x"51", + 6217 => x"3f", + 6218 => x"a0", + 6219 => x"81", + 6220 => x"39", + 6221 => x"51", + 6222 => x"2e", + 6223 => x"7c", + 6224 => x"dc", + 6225 => x"60", + 6226 => x"78", + 6227 => x"d0", + 6228 => x"fe", + 6229 => x"fe", + 6230 => x"81", + 6231 => x"7a", + 6232 => x"82", + 6233 => x"7b", + 6234 => x"38", + 6235 => x"8c", + 6236 => x"39", + 6237 => x"b0", + 6238 => x"39", + 6239 => x"56", + 6240 => x"da", + 6241 => x"53", + 6242 => x"52", + 6243 => x"b0", + 6244 => x"f1", + 6245 => x"39", + 6246 => x"52", + 6247 => x"b0", + 6248 => x"f1", + 6249 => x"39", + 6250 => x"da", + 6251 => x"53", + 6252 => x"52", + 6253 => x"b0", + 6254 => x"f0", + 6255 => x"39", + 6256 => x"53", + 6257 => x"52", + 6258 => x"b0", + 6259 => x"f0", + 6260 => x"db", + 6261 => x"de", + 6262 => x"56", + 6263 => x"46", + 6264 => x"80", + 6265 => x"80", + 6266 => x"80", + 6267 => x"ff", + 6268 => x"e7", + 6269 => x"de", + 6270 => x"de", + 6271 => x"70", + 6272 => x"07", + 6273 => x"5b", + 6274 => x"83", + 6275 => x"78", + 6276 => x"38", + 6277 => x"81", + 6278 => x"59", + 6279 => x"38", + 6280 => x"7d", + 6281 => x"59", + 6282 => x"7d", + 6283 => x"81", + 6284 => x"38", + 6285 => x"51", + 6286 => x"3f", + 6287 => x"fc", + 6288 => x"0b", + 6289 => x"34", + 6290 => x"8c", + 6291 => x"55", + 6292 => x"52", + 6293 => x"ce", + 6294 => x"de", + 6295 => x"2b", + 6296 => x"53", + 6297 => x"52", + 6298 => x"ce", + 6299 => x"81", + 6300 => x"07", + 6301 => x"c0", + 6302 => x"08", + 6303 => x"84", + 6304 => x"51", + 6305 => x"3f", + 6306 => x"08", + 6307 => x"08", + 6308 => x"84", + 6309 => x"51", + 6310 => x"3f", + 6311 => x"c0", + 6312 => x"0c", + 6313 => x"0b", + 6314 => x"84", + 6315 => x"83", + 6316 => x"94", + 6317 => x"ba", + 6318 => x"d0", + 6319 => x"0b", + 6320 => x"0c", + 6321 => x"3f", + 6322 => x"3f", + 6323 => x"51", + 6324 => x"3f", + 6325 => x"51", + 6326 => x"3f", + 6327 => x"51", + 6328 => x"3f", + 6329 => x"bb", + 6330 => x"3f", + 6331 => x"00", + 6332 => x"ff", + 6333 => x"ff", + 6334 => x"00", + 6335 => x"ff", + 6336 => x"16", + 6337 => x"16", + 6338 => x"16", + 6339 => x"16", + 6340 => x"16", + 6341 => x"53", + 6342 => x"53", + 6343 => x"53", + 6344 => x"53", + 6345 => x"53", + 6346 => x"53", + 6347 => x"53", + 6348 => x"53", + 6349 => x"53", + 6350 => x"53", + 6351 => x"53", + 6352 => x"53", + 6353 => x"53", + 6354 => x"53", + 6355 => x"53", + 6356 => x"53", + 6357 => x"53", + 6358 => x"53", + 6359 => x"53", + 6360 => x"53", + 6361 => x"2f", + 6362 => x"25", + 6363 => x"64", + 6364 => x"3a", + 6365 => x"25", + 6366 => x"0a", + 6367 => x"43", + 6368 => x"6e", + 6369 => x"75", + 6370 => x"69", + 6371 => x"00", + 6372 => x"66", + 6373 => x"20", + 6374 => x"20", + 6375 => x"66", + 6376 => x"00", + 6377 => x"44", + 6378 => x"63", + 6379 => x"69", + 6380 => x"65", + 6381 => x"74", + 6382 => x"0a", + 6383 => x"20", + 6384 => x"20", + 6385 => x"41", + 6386 => x"28", + 6387 => x"58", + 6388 => x"38", + 6389 => x"0a", + 6390 => x"20", + 6391 => x"52", + 6392 => x"20", + 6393 => x"28", + 6394 => x"58", + 6395 => x"38", + 6396 => x"0a", + 6397 => x"20", + 6398 => x"53", + 6399 => x"52", + 6400 => x"28", + 6401 => x"58", + 6402 => x"38", + 6403 => x"0a", + 6404 => x"20", + 6405 => x"41", + 6406 => x"20", + 6407 => x"28", + 6408 => x"58", + 6409 => x"38", + 6410 => x"0a", + 6411 => x"20", + 6412 => x"4d", + 6413 => x"20", + 6414 => x"28", + 6415 => x"58", + 6416 => x"38", + 6417 => x"0a", + 6418 => x"20", + 6419 => x"20", + 6420 => x"44", + 6421 => x"28", + 6422 => x"69", + 6423 => x"20", + 6424 => x"32", + 6425 => x"0a", + 6426 => x"20", + 6427 => x"4d", + 6428 => x"20", + 6429 => x"28", + 6430 => x"65", + 6431 => x"20", + 6432 => x"32", + 6433 => x"0a", + 6434 => x"20", + 6435 => x"54", + 6436 => x"54", + 6437 => x"28", + 6438 => x"6e", + 6439 => x"73", + 6440 => x"32", + 6441 => x"0a", + 6442 => x"20", + 6443 => x"53", + 6444 => x"4e", + 6445 => x"55", + 6446 => x"00", + 6447 => x"20", + 6448 => x"20", + 6449 => x"0a", + 6450 => x"20", + 6451 => x"43", + 6452 => x"00", + 6453 => x"20", + 6454 => x"32", + 6455 => x"00", + 6456 => x"20", + 6457 => x"49", + 6458 => x"00", + 6459 => x"64", + 6460 => x"73", + 6461 => x"0a", + 6462 => x"20", + 6463 => x"55", + 6464 => x"73", + 6465 => x"56", + 6466 => x"6f", + 6467 => x"64", + 6468 => x"73", + 6469 => x"20", + 6470 => x"58", + 6471 => x"00", + 6472 => x"20", + 6473 => x"55", + 6474 => x"6d", + 6475 => x"20", + 6476 => x"72", + 6477 => x"64", + 6478 => x"73", + 6479 => x"20", + 6480 => x"58", + 6481 => x"00", + 6482 => x"20", + 6483 => x"61", + 6484 => x"53", + 6485 => x"74", + 6486 => x"64", + 6487 => x"73", + 6488 => x"20", + 6489 => x"20", + 6490 => x"58", + 6491 => x"00", + 6492 => x"73", + 6493 => x"00", + 6494 => x"20", + 6495 => x"55", + 6496 => x"20", + 6497 => x"20", + 6498 => x"20", + 6499 => x"20", + 6500 => x"20", + 6501 => x"20", + 6502 => x"58", + 6503 => x"00", + 6504 => x"20", + 6505 => x"73", + 6506 => x"20", + 6507 => x"63", + 6508 => x"72", + 6509 => x"20", + 6510 => x"20", + 6511 => x"20", + 6512 => x"25", + 6513 => x"4d", + 6514 => x"00", + 6515 => x"20", + 6516 => x"52", + 6517 => x"43", + 6518 => x"6b", + 6519 => x"65", + 6520 => x"20", + 6521 => x"20", + 6522 => x"20", + 6523 => x"25", + 6524 => x"4d", + 6525 => x"00", + 6526 => x"20", + 6527 => x"73", + 6528 => x"6e", + 6529 => x"44", + 6530 => x"20", + 6531 => x"63", + 6532 => x"72", + 6533 => x"20", + 6534 => x"25", + 6535 => x"4d", + 6536 => x"00", + 6537 => x"61", + 6538 => x"00", + 6539 => x"64", + 6540 => x"00", + 6541 => x"65", + 6542 => x"00", + 6543 => x"4f", + 6544 => x"4f", + 6545 => x"00", + 6546 => x"6b", + 6547 => x"6e", + 6548 => x"00", + 6549 => x"2b", + 6550 => x"3c", + 6551 => x"5b", + 6552 => x"00", + 6553 => x"54", + 6554 => x"54", + 6555 => x"00", + 6556 => x"90", + 6557 => x"4f", + 6558 => x"30", + 6559 => x"20", + 6560 => x"45", + 6561 => x"20", + 6562 => x"33", + 6563 => x"20", + 6564 => x"20", + 6565 => x"45", + 6566 => x"20", + 6567 => x"20", + 6568 => x"20", + 6569 => x"66", + 6570 => x"00", + 6571 => x"00", + 6572 => x"00", + 6573 => x"45", + 6574 => x"8f", + 6575 => x"45", + 6576 => x"8e", + 6577 => x"92", + 6578 => x"55", + 6579 => x"9a", + 6580 => x"9e", + 6581 => x"4f", + 6582 => x"a6", + 6583 => x"aa", + 6584 => x"ae", + 6585 => x"b2", + 6586 => x"b6", + 6587 => x"ba", + 6588 => x"be", + 6589 => x"c2", + 6590 => x"c6", + 6591 => x"ca", + 6592 => x"ce", + 6593 => x"d2", + 6594 => x"d6", + 6595 => x"da", + 6596 => x"de", + 6597 => x"e2", + 6598 => x"e6", + 6599 => x"ea", + 6600 => x"ee", + 6601 => x"f2", + 6602 => x"f6", + 6603 => x"fa", + 6604 => x"fe", + 6605 => x"2c", + 6606 => x"5d", + 6607 => x"2a", + 6608 => x"3f", + 6609 => x"00", + 6610 => x"00", + 6611 => x"00", + 6612 => x"02", + 6613 => x"00", + 6614 => x"00", + 6615 => x"00", + 6616 => x"00", + 6617 => x"00", + 6618 => x"6e", + 6619 => x"00", + 6620 => x"6f", + 6621 => x"00", + 6622 => x"6e", + 6623 => x"00", + 6624 => x"6f", + 6625 => x"00", + 6626 => x"78", + 6627 => x"00", + 6628 => x"6c", + 6629 => x"00", + 6630 => x"75", + 6631 => x"00", + 6632 => x"72", + 6633 => x"00", + 6634 => x"62", + 6635 => x"68", + 6636 => x"77", + 6637 => x"64", + 6638 => x"65", + 6639 => x"64", + 6640 => x"65", + 6641 => x"6c", + 6642 => x"00", + 6643 => x"70", + 6644 => x"73", + 6645 => x"74", + 6646 => x"73", + 6647 => x"00", + 6648 => x"66", + 6649 => x"00", + 6650 => x"73", + 6651 => x"00", + 6652 => x"73", + 6653 => x"72", + 6654 => x"0a", + 6655 => x"74", + 6656 => x"61", + 6657 => x"72", + 6658 => x"2e", + 6659 => x"00", + 6660 => x"73", + 6661 => x"6f", + 6662 => x"65", + 6663 => x"2e", + 6664 => x"00", + 6665 => x"20", + 6666 => x"65", + 6667 => x"75", + 6668 => x"0a", + 6669 => x"20", + 6670 => x"68", + 6671 => x"75", + 6672 => x"0a", + 6673 => x"76", + 6674 => x"64", + 6675 => x"6c", + 6676 => x"6d", + 6677 => x"00", + 6678 => x"63", + 6679 => x"20", + 6680 => x"69", + 6681 => x"0a", + 6682 => x"6c", + 6683 => x"6c", + 6684 => x"64", + 6685 => x"78", + 6686 => x"73", + 6687 => x"00", + 6688 => x"6c", + 6689 => x"61", + 6690 => x"65", + 6691 => x"76", + 6692 => x"64", + 6693 => x"00", + 6694 => x"20", + 6695 => x"77", + 6696 => x"65", + 6697 => x"6f", + 6698 => x"74", + 6699 => x"0a", + 6700 => x"69", + 6701 => x"6e", + 6702 => x"65", + 6703 => x"73", + 6704 => x"76", + 6705 => x"64", + 6706 => x"00", + 6707 => x"73", + 6708 => x"6f", + 6709 => x"6e", + 6710 => x"65", + 6711 => x"00", + 6712 => x"20", + 6713 => x"70", + 6714 => x"62", + 6715 => x"66", + 6716 => x"73", + 6717 => x"65", + 6718 => x"6f", + 6719 => x"20", + 6720 => x"64", + 6721 => x"2e", + 6722 => x"00", + 6723 => x"72", + 6724 => x"20", + 6725 => x"72", + 6726 => x"2e", + 6727 => x"00", + 6728 => x"6d", + 6729 => x"74", + 6730 => x"70", + 6731 => x"74", + 6732 => x"20", + 6733 => x"63", + 6734 => x"65", + 6735 => x"00", + 6736 => x"6c", + 6737 => x"73", + 6738 => x"63", + 6739 => x"2e", + 6740 => x"00", + 6741 => x"73", + 6742 => x"69", + 6743 => x"6e", + 6744 => x"65", + 6745 => x"79", + 6746 => x"00", + 6747 => x"6f", + 6748 => x"6e", + 6749 => x"70", + 6750 => x"66", + 6751 => x"73", + 6752 => x"00", + 6753 => x"72", + 6754 => x"74", + 6755 => x"20", + 6756 => x"6f", + 6757 => x"63", + 6758 => x"00", + 6759 => x"63", + 6760 => x"73", + 6761 => x"00", + 6762 => x"6b", + 6763 => x"6e", + 6764 => x"72", + 6765 => x"0a", + 6766 => x"6c", + 6767 => x"79", + 6768 => x"20", + 6769 => x"61", + 6770 => x"6c", + 6771 => x"79", + 6772 => x"2f", + 6773 => x"2e", + 6774 => x"00", + 6775 => x"38", + 6776 => x"00", + 6777 => x"20", + 6778 => x"34", + 6779 => x"00", + 6780 => x"20", + 6781 => x"20", + 6782 => x"00", + 6783 => x"32", + 6784 => x"00", + 6785 => x"00", + 6786 => x"00", + 6787 => x"0a", + 6788 => x"61", + 6789 => x"00", + 6790 => x"55", + 6791 => x"00", + 6792 => x"2a", + 6793 => x"20", + 6794 => x"00", + 6795 => x"2f", + 6796 => x"32", + 6797 => x"00", + 6798 => x"2e", + 6799 => x"00", + 6800 => x"50", + 6801 => x"72", + 6802 => x"25", + 6803 => x"29", + 6804 => x"20", + 6805 => x"2a", + 6806 => x"00", + 6807 => x"55", + 6808 => x"49", + 6809 => x"72", + 6810 => x"74", + 6811 => x"6e", + 6812 => x"72", + 6813 => x"00", + 6814 => x"6d", + 6815 => x"69", + 6816 => x"72", + 6817 => x"74", + 6818 => x"00", + 6819 => x"32", + 6820 => x"74", + 6821 => x"75", + 6822 => x"00", + 6823 => x"43", + 6824 => x"52", + 6825 => x"6e", + 6826 => x"72", + 6827 => x"0a", + 6828 => x"43", + 6829 => x"57", + 6830 => x"6e", + 6831 => x"72", + 6832 => x"0a", + 6833 => x"52", + 6834 => x"52", + 6835 => x"6e", + 6836 => x"72", + 6837 => x"0a", + 6838 => x"52", + 6839 => x"54", + 6840 => x"6e", + 6841 => x"72", + 6842 => x"0a", + 6843 => x"52", + 6844 => x"52", + 6845 => x"6e", + 6846 => x"72", + 6847 => x"0a", + 6848 => x"52", + 6849 => x"54", + 6850 => x"6e", + 6851 => x"72", + 6852 => x"0a", + 6853 => x"74", + 6854 => x"67", + 6855 => x"20", + 6856 => x"65", + 6857 => x"2e", + 6858 => x"00", + 6859 => x"61", + 6860 => x"6e", + 6861 => x"69", + 6862 => x"2e", + 6863 => x"00", + 6864 => x"74", + 6865 => x"65", + 6866 => x"61", + 6867 => x"00", + 6868 => x"00", + 6869 => x"69", + 6870 => x"20", + 6871 => x"69", + 6872 => x"69", + 6873 => x"73", + 6874 => x"64", + 6875 => x"72", + 6876 => x"2c", + 6877 => x"65", + 6878 => x"20", + 6879 => x"74", + 6880 => x"6e", + 6881 => x"6c", + 6882 => x"00", + 6883 => x"00", + 6884 => x"64", + 6885 => x"73", + 6886 => x"64", + 6887 => x"00", + 6888 => x"69", + 6889 => x"6c", + 6890 => x"64", + 6891 => x"00", + 6892 => x"69", + 6893 => x"20", + 6894 => x"69", + 6895 => x"69", + 6896 => x"73", + 6897 => x"00", + 6898 => x"3d", + 6899 => x"00", + 6900 => x"3a", + 6901 => x"65", + 6902 => x"6e", + 6903 => x"2e", + 6904 => x"00", + 6905 => x"6d", + 6906 => x"65", + 6907 => x"79", + 6908 => x"00", + 6909 => x"6f", + 6910 => x"65", + 6911 => x"0a", + 6912 => x"38", + 6913 => x"30", + 6914 => x"00", + 6915 => x"3f", + 6916 => x"00", + 6917 => x"38", + 6918 => x"30", + 6919 => x"00", + 6920 => x"38", + 6921 => x"30", + 6922 => x"00", + 6923 => x"61", + 6924 => x"69", + 6925 => x"2e", + 6926 => x"00", + 6927 => x"38", + 6928 => x"3e", + 6929 => x"6c", + 6930 => x"00", + 6931 => x"73", + 6932 => x"69", + 6933 => x"69", + 6934 => x"72", + 6935 => x"74", + 6936 => x"00", + 6937 => x"61", + 6938 => x"6e", + 6939 => x"6e", + 6940 => x"72", + 6941 => x"73", + 6942 => x"00", + 6943 => x"73", + 6944 => x"65", + 6945 => x"61", + 6946 => x"66", + 6947 => x"0a", + 6948 => x"61", + 6949 => x"6e", + 6950 => x"61", + 6951 => x"66", + 6952 => x"0a", + 6953 => x"65", + 6954 => x"69", + 6955 => x"63", + 6956 => x"20", + 6957 => x"30", + 6958 => x"2e", + 6959 => x"00", + 6960 => x"6c", + 6961 => x"67", + 6962 => x"64", + 6963 => x"20", + 6964 => x"78", + 6965 => x"2e", + 6966 => x"00", + 6967 => x"6c", + 6968 => x"65", + 6969 => x"6e", + 6970 => x"63", + 6971 => x"20", + 6972 => x"29", + 6973 => x"00", + 6974 => x"73", + 6975 => x"74", + 6976 => x"20", + 6977 => x"6c", + 6978 => x"74", + 6979 => x"2e", + 6980 => x"00", + 6981 => x"6c", + 6982 => x"65", + 6983 => x"74", + 6984 => x"2e", + 6985 => x"00", + 6986 => x"55", + 6987 => x"6e", + 6988 => x"3a", + 6989 => x"5c", + 6990 => x"25", + 6991 => x"00", + 6992 => x"3a", + 6993 => x"5c", + 6994 => x"00", + 6995 => x"3a", + 6996 => x"00", + 6997 => x"64", + 6998 => x"6d", + 6999 => x"64", + 7000 => x"00", + 7001 => x"6e", + 7002 => x"67", + 7003 => x"0a", + 7004 => x"61", + 7005 => x"6e", + 7006 => x"6e", + 7007 => x"72", + 7008 => x"73", + 7009 => x"0a", + 7010 => x"00", + 7011 => x"00", + 7012 => x"7f", + 7013 => x"00", + 7014 => x"7f", + 7015 => x"00", + 7016 => x"7f", + 7017 => x"00", + 7018 => x"00", + 7019 => x"00", + 7020 => x"ff", + 7021 => x"00", + 7022 => x"00", + 7023 => x"78", + 7024 => x"00", + 7025 => x"e1", + 7026 => x"e1", + 7027 => x"e1", + 7028 => x"00", + 7029 => x"01", + 7030 => x"01", + 7031 => x"10", + 7032 => x"00", + 7033 => x"00", + 7034 => x"00", + 7035 => x"00", + 7036 => x"67", + 7037 => x"01", + 7038 => x"00", + 7039 => x"00", + 7040 => x"67", + 7041 => x"01", + 7042 => x"00", + 7043 => x"00", + 7044 => x"67", + 7045 => x"03", + 7046 => x"00", + 7047 => x"00", + 7048 => x"67", + 7049 => x"03", + 7050 => x"00", + 7051 => x"00", + 7052 => x"67", + 7053 => x"03", + 7054 => x"00", + 7055 => x"00", + 7056 => x"67", + 7057 => x"04", + 7058 => x"00", + 7059 => x"00", + 7060 => x"67", + 7061 => x"04", + 7062 => x"00", + 7063 => x"00", + 7064 => x"67", + 7065 => x"04", + 7066 => x"00", + 7067 => x"00", + 7068 => x"67", + 7069 => x"04", + 7070 => x"00", + 7071 => x"00", + 7072 => x"67", + 7073 => x"04", + 7074 => x"00", + 7075 => x"00", + 7076 => x"67", + 7077 => x"04", + 7078 => x"00", + 7079 => x"00", + 7080 => x"67", + 7081 => x"05", + 7082 => x"00", + 7083 => x"00", + 7084 => x"67", + 7085 => x"05", + 7086 => x"00", + 7087 => x"00", + 7088 => x"67", + 7089 => x"05", + 7090 => x"00", + 7091 => x"00", + 7092 => x"67", + 7093 => x"05", + 7094 => x"00", + 7095 => x"00", + 7096 => x"67", + 7097 => x"07", + 7098 => x"00", + 7099 => x"00", + 7100 => x"67", + 7101 => x"07", + 7102 => x"00", + 7103 => x"00", + 7104 => x"67", + 7105 => x"08", + 7106 => x"00", + 7107 => x"00", + 7108 => x"67", + 7109 => x"08", + 7110 => x"00", + 7111 => x"00", + 7112 => x"67", + 7113 => x"08", + 7114 => x"00", + 7115 => x"00", + 7116 => x"67", + 7117 => x"08", + 7118 => x"00", + 7119 => x"00", + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + 0 => x"0b", + 1 => x"04", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"08", + 10 => x"2d", + 11 => x"0c", + 12 => x"00", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"fd", + 17 => x"83", + 18 => x"05", + 19 => x"2b", + 20 => x"ff", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"fd", + 25 => x"ff", + 26 => x"06", + 27 => x"82", + 28 => x"2b", + 29 => x"83", + 30 => x"0b", + 31 => x"a5", + 32 => x"09", + 33 => x"05", + 34 => x"06", + 35 => x"09", + 36 => x"0a", + 37 => x"51", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"2e", + 42 => x"04", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"73", + 49 => x"06", + 50 => x"81", + 51 => x"10", + 52 => x"10", + 53 => x"0a", + 54 => x"51", + 55 => x"00", + 56 => x"72", + 57 => x"2e", + 58 => x"04", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"04", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"0a", + 81 => x"53", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"81", + 90 => x"0b", + 91 => x"04", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"9f", + 98 => x"74", + 99 => x"06", + 100 => x"07", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"06", + 106 => x"09", + 107 => x"05", + 108 => x"2b", + 109 => x"06", + 110 => x"04", + 111 => x"00", + 112 => x"09", + 113 => x"05", + 114 => x"05", + 115 => x"81", + 116 => x"04", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"09", + 121 => x"05", + 122 => x"05", + 123 => x"09", + 124 => x"51", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"09", + 129 => x"04", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"09", + 145 => x"73", + 146 => x"53", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"fc", + 153 => x"83", + 154 => x"05", + 155 => x"10", + 156 => x"ff", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"fc", + 161 => x"0b", + 162 => x"73", + 163 => x"10", + 164 => x"0b", + 165 => x"a4", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"08", + 170 => x"0b", + 171 => x"2d", + 172 => x"08", + 173 => x"8c", + 174 => x"51", + 175 => x"00", + 176 => x"08", + 177 => x"08", + 178 => x"0b", + 179 => x"2d", + 180 => x"08", + 181 => x"8c", + 182 => x"51", + 183 => x"00", + 184 => x"09", + 185 => x"09", + 186 => x"06", + 187 => x"54", + 188 => x"09", + 189 => x"ff", + 190 => x"51", + 191 => x"00", + 192 => x"09", + 193 => x"09", + 194 => x"81", + 195 => x"70", + 196 => x"73", + 197 => x"05", + 198 => x"07", + 199 => x"04", + 200 => x"ff", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => 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x"10", + 584 => x"04", + 585 => x"81", + 586 => x"83", + 587 => x"05", + 588 => x"10", + 589 => x"72", + 590 => x"51", + 591 => x"72", + 592 => x"06", + 593 => x"72", + 594 => x"10", + 595 => x"10", + 596 => x"ed", + 597 => x"53", + 598 => x"de", + 599 => x"f5", + 600 => x"38", + 601 => x"84", + 602 => x"0b", + 603 => x"db", + 604 => x"51", + 605 => x"04", + 606 => x"cc", + 607 => x"de", + 608 => x"3d", + 609 => x"81", + 610 => x"8c", + 611 => x"81", + 612 => x"88", + 613 => x"83", + 614 => x"de", + 615 => x"81", + 616 => x"54", + 617 => x"81", + 618 => x"04", + 619 => x"08", + 620 => x"cc", + 621 => x"0d", + 622 => x"de", + 623 => x"05", + 624 => x"de", + 625 => x"05", + 626 => x"a1", + 627 => x"c0", + 628 => x"de", + 629 => x"85", + 630 => x"de", + 631 => x"81", + 632 => x"02", + 633 => x"0c", + 634 => x"80", + 635 => x"cc", + 636 => x"0c", + 637 => x"08", + 638 => x"80", + 639 => x"81", + 640 => x"88", + 641 => x"81", + 642 => x"88", + 643 => x"0b", + 644 => x"08", + 645 => x"81", + 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x"70", + 1020 => x"51", + 1021 => x"72", + 1022 => x"81", + 1023 => x"70", + 1024 => x"38", + 1025 => x"70", + 1026 => x"51", + 1027 => x"38", + 1028 => x"06", + 1029 => x"94", + 1030 => x"80", + 1031 => x"87", + 1032 => x"52", + 1033 => x"75", + 1034 => x"0c", + 1035 => x"04", + 1036 => x"02", + 1037 => x"0b", + 1038 => x"88", + 1039 => x"ff", + 1040 => x"56", + 1041 => x"84", + 1042 => x"2e", + 1043 => x"c0", + 1044 => x"70", + 1045 => x"2a", + 1046 => x"53", + 1047 => x"80", + 1048 => x"71", + 1049 => x"81", + 1050 => x"70", + 1051 => x"81", + 1052 => x"06", + 1053 => x"80", + 1054 => x"71", + 1055 => x"81", + 1056 => x"70", + 1057 => x"73", + 1058 => x"51", + 1059 => x"80", + 1060 => x"2e", + 1061 => x"c0", + 1062 => x"75", + 1063 => x"3d", + 1064 => x"3d", + 1065 => x"80", + 1066 => x"81", + 1067 => x"53", + 1068 => x"2e", + 1069 => x"71", + 1070 => x"81", + 1071 => x"81", + 1072 => x"70", + 1073 => x"59", + 1074 => x"87", + 1075 => x"51", + 1076 => x"86", + 1077 => x"94", + 1078 => x"08", + 1079 => x"70", + 1080 => x"54", + 1081 => x"2e", + 1082 => x"91", + 1083 => x"06", + 1084 => x"d7", + 1085 => x"32", + 1086 => x"51", + 1087 => x"2e", + 1088 => x"93", + 1089 => x"06", + 1090 => x"ff", + 1091 => x"81", + 1092 => x"87", + 1093 => x"52", + 1094 => x"86", + 1095 => x"94", + 1096 => x"72", + 1097 => x"74", + 1098 => x"ff", + 1099 => x"57", + 1100 => x"38", + 1101 => x"c0", + 1102 => x"0d", + 1103 => x"0d", + 1104 => x"db", + 1105 => x"81", + 1106 => x"52", + 1107 => x"84", + 1108 => x"2e", + 1109 => x"c0", + 1110 => x"70", + 1111 => x"2a", + 1112 => x"51", + 1113 => x"80", + 1114 => x"71", + 1115 => x"51", + 1116 => x"80", + 1117 => x"2e", + 1118 => x"c0", + 1119 => x"71", + 1120 => x"ff", + 1121 => x"c0", + 1122 => x"3d", + 1123 => x"3d", + 1124 => x"81", + 1125 => x"70", + 1126 => x"52", + 1127 => x"94", + 1128 => x"80", + 1129 => x"87", + 1130 => x"52", + 1131 => x"82", + 1132 => x"06", + 1133 => x"ff", + 1134 => x"2e", + 1135 => x"81", + 1136 => x"87", + 1137 => x"52", + 1138 => x"86", + 1139 => x"94", + 1140 => x"08", + 1141 => x"70", + 1142 => x"53", + 1143 => x"de", + 1144 => x"3d", + 1145 => x"3d", + 1146 => x"9e", + 1147 => x"9c", + 1148 => x"51", + 1149 => x"2e", + 1150 => x"87", + 1151 => x"08", + 1152 => x"0c", + 1153 => x"a8", + 1154 => x"90", + 1155 => x"9e", + 1156 => x"db", + 1157 => x"c0", + 1158 => x"81", + 1159 => x"87", + 1160 => x"08", + 1161 => x"0c", + 1162 => x"a0", + 1163 => x"a0", + 1164 => x"9e", + 1165 => x"db", + 1166 => x"c0", + 1167 => x"81", + 1168 => x"87", + 1169 => x"08", + 1170 => x"0c", + 1171 => x"b8", + 1172 => x"b0", + 1173 => x"9e", + 1174 => x"db", + 1175 => x"c0", + 1176 => x"81", + 1177 => x"87", + 1178 => x"08", + 1179 => x"0c", + 1180 => x"80", + 1181 => x"81", + 1182 => x"87", + 1183 => x"08", + 1184 => x"0c", + 1185 => x"88", + 1186 => x"c8", + 1187 => x"9e", + 1188 => x"db", + 1189 => x"0b", + 1190 => x"34", + 1191 => x"c0", + 1192 => x"70", + 1193 => x"06", + 1194 => x"70", + 1195 => x"38", + 1196 => x"81", + 1197 => x"80", + 1198 => x"9e", + 1199 => x"88", + 1200 => x"51", + 1201 => x"80", + 1202 => x"81", + 1203 => x"db", + 1204 => x"0b", + 1205 => x"90", + 1206 => x"80", + 1207 => x"52", + 1208 => x"2e", + 1209 => x"52", + 1210 => x"d3", + 1211 => x"87", + 1212 => x"08", + 1213 => x"80", + 1214 => x"52", + 1215 => x"83", + 1216 => x"71", + 1217 => x"34", + 1218 => x"c0", + 1219 => x"70", + 1220 => x"06", + 1221 => x"70", + 1222 => x"38", + 1223 => x"81", + 1224 => x"80", + 1225 => x"9e", + 1226 => x"90", + 1227 => x"51", + 1228 => x"80", + 1229 => x"81", + 1230 => x"db", + 1231 => x"0b", + 1232 => x"90", + 1233 => x"80", + 1234 => x"52", + 1235 => x"2e", + 1236 => x"52", + 1237 => x"d7", + 1238 => x"87", + 1239 => x"08", + 1240 => x"80", + 1241 => x"52", + 1242 => x"83", + 1243 => x"71", + 1244 => x"34", + 1245 => x"c0", + 1246 => x"70", + 1247 => x"06", + 1248 => x"70", + 1249 => x"38", + 1250 => x"81", + 1251 => x"80", + 1252 => x"9e", + 1253 => x"80", + 1254 => x"51", + 1255 => x"80", + 1256 => x"81", + 1257 => x"db", + 1258 => x"0b", + 1259 => x"90", + 1260 => x"80", + 1261 => x"52", + 1262 => x"83", + 1263 => x"71", + 1264 => x"34", + 1265 => x"90", + 1266 => x"80", + 1267 => x"2a", + 1268 => x"70", + 1269 => x"34", + 1270 => x"c0", + 1271 => x"70", + 1272 => x"51", + 1273 => x"80", + 1274 => x"81", + 1275 => x"db", + 1276 => x"c0", + 1277 => x"70", + 1278 => x"70", + 1279 => x"51", + 1280 => x"db", + 1281 => x"0b", + 1282 => x"90", + 1283 => x"06", + 1284 => x"70", + 1285 => x"38", + 1286 => x"81", + 1287 => x"87", + 1288 => x"08", + 1289 => x"51", + 1290 => x"db", + 1291 => x"3d", + 1292 => x"3d", + 1293 => x"fc", + 1294 => x"3f", + 1295 => x"33", + 1296 => x"2e", + 1297 => x"c7", + 1298 => x"f5", + 1299 => x"a4", + 1300 => x"3f", + 1301 => x"33", + 1302 => x"2e", + 1303 => x"db", + 1304 => x"db", + 1305 => x"54", + 1306 => x"bc", + 1307 => x"3f", + 1308 => x"33", + 1309 => x"2e", + 1310 => x"db", + 1311 => x"db", + 1312 => x"54", + 1313 => x"d8", + 1314 => x"3f", + 1315 => x"33", + 1316 => x"2e", + 1317 => x"db", + 1318 => x"db", + 1319 => x"54", + 1320 => x"f4", + 1321 => x"3f", + 1322 => x"33", + 1323 => x"2e", + 1324 => x"db", + 1325 => x"db", + 1326 => x"54", + 1327 => x"90", + 1328 => x"3f", + 1329 => x"33", + 1330 => x"2e", + 1331 => x"db", + 1332 => x"db", + 1333 => x"54", + 1334 => x"ac", + 1335 => x"3f", + 1336 => x"33", + 1337 => x"2e", + 1338 => x"db", + 1339 => x"81", + 1340 => x"8a", + 1341 => x"db", + 1342 => x"73", + 1343 => x"38", + 1344 => x"33", + 1345 => x"e8", + 1346 => x"3f", + 1347 => x"33", + 1348 => x"2e", + 1349 => x"db", + 1350 => x"81", + 1351 => x"8a", + 1352 => x"db", + 1353 => x"73", + 1354 => x"38", + 1355 => x"51", + 1356 => x"81", + 1357 => x"54", + 1358 => x"88", + 1359 => x"bc", + 1360 => x"3f", + 1361 => x"33", + 1362 => x"2e", + 1363 => x"c9", + 1364 => x"ed", + 1365 => x"d9", + 1366 => x"80", + 1367 => x"81", + 1368 => x"83", + 1369 => x"db", + 1370 => x"73", + 1371 => x"38", + 1372 => x"51", + 1373 => x"81", + 1374 => x"83", + 1375 => x"db", + 1376 => x"81", + 1377 => x"89", + 1378 => x"db", + 1379 => x"81", + 1380 => x"89", + 1381 => x"db", + 1382 => x"81", + 1383 => x"89", + 1384 => x"ca", + 1385 => x"fa", + 1386 => x"c0", + 1387 => x"ca", + 1388 => x"f1", + 1389 => x"c4", + 1390 => x"84", + 1391 => x"51", + 1392 => x"81", + 1393 => x"bd", + 1394 => x"76", + 1395 => x"54", + 1396 => x"08", + 1397 => x"a0", + 1398 => x"3f", + 1399 => x"33", + 1400 => x"2e", + 1401 => x"db", + 1402 => x"bd", + 1403 => x"75", + 1404 => x"3f", + 1405 => x"08", + 1406 => x"29", + 1407 => x"54", + 1408 => x"c0", + 1409 => x"cb", + 1410 => x"99", + 1411 => x"d2", + 1412 => x"80", + 1413 => x"81", + 1414 => x"56", + 1415 => x"52", + 1416 => x"d5", + 1417 => x"c0", + 1418 => x"c0", + 1419 => x"31", + 1420 => x"de", + 1421 => x"81", + 1422 => x"87", + 1423 => x"d7", + 1424 => x"fd", + 1425 => x"0d", + 1426 => x"0d", + 1427 => x"33", + 1428 => x"71", + 1429 => x"38", + 1430 => x"81", + 1431 => x"52", + 1432 => x"81", + 1433 => x"9d", + 1434 => x"ac", + 1435 => x"81", + 1436 => x"91", + 1437 => x"bc", + 1438 => x"81", + 1439 => x"85", + 1440 => x"c8", + 1441 => x"3f", + 1442 => x"04", + 1443 => x"0c", + 1444 => x"87", + 1445 => x"0c", + 1446 => x"0d", + 1447 => x"84", + 1448 => x"52", + 1449 => x"70", + 1450 => x"81", + 1451 => x"72", + 1452 => x"0d", + 1453 => x"0d", + 1454 => x"84", + 1455 => x"db", + 1456 => x"80", + 1457 => x"09", + 1458 => x"e4", + 1459 => x"81", + 1460 => x"73", + 1461 => x"3d", + 1462 => x"db", + 1463 => x"c0", + 1464 => x"04", + 1465 => x"02", + 1466 => x"53", + 1467 => x"09", + 1468 => x"38", + 1469 => x"3f", + 1470 => x"08", + 1471 => x"2e", + 1472 => x"72", + 1473 => x"d8", + 1474 => x"81", + 1475 => x"8f", + 1476 => x"d0", + 1477 => x"80", + 1478 => x"72", + 1479 => x"84", + 1480 => x"fe", + 1481 => x"97", + 1482 => x"de", + 1483 => x"81", + 1484 => x"54", + 1485 => x"3f", + 1486 => x"d0", + 1487 => x"0d", + 1488 => x"0d", + 1489 => x"33", + 1490 => x"06", + 1491 => x"80", + 1492 => x"72", + 1493 => x"51", + 1494 => x"ff", + 1495 => x"39", + 1496 => x"04", + 1497 => x"77", + 1498 => x"08", + 1499 => x"d0", + 1500 => x"73", + 1501 => x"ff", + 1502 => x"71", + 1503 => x"38", + 1504 => x"06", + 1505 => x"54", + 1506 => x"e7", + 1507 => x"de", + 1508 => x"3d", + 1509 => x"3d", + 1510 => x"59", + 1511 => x"81", + 1512 => x"56", + 1513 => x"84", + 1514 => x"a5", + 1515 => x"06", + 1516 => x"80", + 1517 => x"81", + 1518 => x"58", + 1519 => x"b0", + 1520 => x"06", + 1521 => x"5a", + 1522 => x"ad", + 1523 => x"06", + 1524 => x"5a", + 1525 => x"05", + 1526 => x"75", + 1527 => x"81", + 1528 => x"77", + 1529 => x"08", + 1530 => x"05", + 1531 => x"5d", + 1532 => x"39", + 1533 => x"72", + 1534 => x"38", + 1535 => x"7b", + 1536 => x"05", + 1537 => x"70", + 1538 => x"33", + 1539 => x"39", + 1540 => x"32", + 1541 => x"72", + 1542 => x"78", + 1543 => x"70", + 1544 => x"07", + 1545 => x"07", + 1546 => x"51", + 1547 => x"80", + 1548 => x"79", + 1549 => x"70", + 1550 => x"33", + 1551 => x"80", + 1552 => x"38", + 1553 => x"e0", + 1554 => x"38", + 1555 => x"81", + 1556 => x"53", + 1557 => x"2e", + 1558 => x"73", + 1559 => x"a2", + 1560 => x"c3", + 1561 => x"38", + 1562 => x"24", + 1563 => x"80", + 1564 => x"8c", + 1565 => x"39", + 1566 => x"2e", + 1567 => x"81", + 1568 => x"80", + 1569 => x"80", + 1570 => x"d5", + 1571 => x"73", + 1572 => x"8e", + 1573 => x"39", + 1574 => x"2e", + 1575 => x"80", + 1576 => x"84", + 1577 => x"56", + 1578 => x"74", + 1579 => x"72", + 1580 => x"38", + 1581 => x"15", + 1582 => x"54", + 1583 => x"38", + 1584 => x"56", + 1585 => x"81", + 1586 => x"72", + 1587 => x"38", + 1588 => x"90", + 1589 => x"06", + 1590 => x"2e", + 1591 => x"51", + 1592 => x"74", + 1593 => x"53", + 1594 => x"fd", + 1595 => x"51", + 1596 => x"ef", + 1597 => x"19", + 1598 => x"53", + 1599 => x"39", + 1600 => x"39", + 1601 => x"39", + 1602 => x"39", + 1603 => x"39", + 1604 => x"d0", + 1605 => x"39", + 1606 => x"70", + 1607 => x"53", + 1608 => x"88", + 1609 => x"19", + 1610 => x"39", + 1611 => x"54", + 1612 => x"74", + 1613 => x"70", + 1614 => x"07", + 1615 => x"55", + 1616 => x"80", + 1617 => x"72", + 1618 => x"38", + 1619 => x"90", + 1620 => x"80", + 1621 => x"5e", + 1622 => x"74", + 1623 => x"3f", + 1624 => x"08", + 1625 => x"7c", + 1626 => x"54", + 1627 => x"81", + 1628 => x"55", + 1629 => x"92", + 1630 => x"53", + 1631 => x"2e", + 1632 => x"14", + 1633 => x"ff", + 1634 => x"14", + 1635 => x"70", + 1636 => x"34", + 1637 => x"30", + 1638 => x"9f", + 1639 => x"57", + 1640 => x"85", + 1641 => x"b1", + 1642 => x"2a", + 1643 => x"51", + 1644 => x"2e", + 1645 => x"3d", + 1646 => x"05", + 1647 => x"34", + 1648 => x"76", + 1649 => x"54", + 1650 => x"72", + 1651 => x"54", + 1652 => x"70", + 1653 => x"56", + 1654 => x"81", + 1655 => x"7b", + 1656 => x"73", + 1657 => x"3f", + 1658 => x"53", + 1659 => x"74", + 1660 => x"53", + 1661 => x"eb", + 1662 => x"77", + 1663 => x"53", + 1664 => x"14", + 1665 => x"54", + 1666 => x"3f", + 1667 => x"74", + 1668 => x"53", + 1669 => x"fb", + 1670 => x"51", + 1671 => x"ef", + 1672 => x"0d", + 1673 => x"0d", + 1674 => x"70", + 1675 => x"08", + 1676 => x"51", + 1677 => x"85", + 1678 => x"fe", + 1679 => x"81", + 1680 => x"85", + 1681 => x"52", + 1682 => x"ca", + 1683 => x"d8", + 1684 => x"73", + 1685 => x"81", + 1686 => x"84", + 1687 => x"fd", + 1688 => x"de", + 1689 => x"81", + 1690 => x"87", + 1691 => x"53", + 1692 => x"fa", + 1693 => x"81", + 1694 => x"85", + 1695 => x"fb", + 1696 => x"79", + 1697 => x"08", + 1698 => x"57", + 1699 => x"71", + 1700 => x"e0", + 1701 => x"d4", + 1702 => x"2d", + 1703 => x"08", + 1704 => x"53", + 1705 => x"80", + 1706 => x"8d", + 1707 => x"72", + 1708 => x"30", + 1709 => x"51", + 1710 => x"80", + 1711 => x"71", + 1712 => x"38", + 1713 => x"97", + 1714 => x"25", + 1715 => x"16", + 1716 => x"25", + 1717 => x"14", + 1718 => x"34", + 1719 => x"72", + 1720 => x"3f", + 1721 => x"73", + 1722 => x"72", + 1723 => x"f7", + 1724 => x"53", + 1725 => x"c0", + 1726 => x"0d", + 1727 => x"0d", + 1728 => x"08", + 1729 => x"d4", + 1730 => x"76", + 1731 => x"ef", + 1732 => x"de", + 1733 => x"3d", + 1734 => x"3d", + 1735 => x"5a", + 1736 => x"7a", + 1737 => x"08", + 1738 => x"53", + 1739 => x"09", + 1740 => x"38", + 1741 => x"0c", + 1742 => x"ad", + 1743 => x"06", + 1744 => x"76", + 1745 => x"0c", + 1746 => x"33", + 1747 => x"73", + 1748 => x"81", + 1749 => x"38", + 1750 => x"05", + 1751 => x"08", + 1752 => x"53", + 1753 => x"2e", + 1754 => x"57", + 1755 => x"2e", + 1756 => x"39", + 1757 => x"13", + 1758 => x"08", + 1759 => x"53", + 1760 => x"55", + 1761 => x"80", + 1762 => x"14", + 1763 => x"88", + 1764 => x"27", + 1765 => x"eb", + 1766 => x"53", + 1767 => x"89", + 1768 => x"38", + 1769 => x"55", + 1770 => x"8a", + 1771 => x"a0", + 1772 => x"c2", + 1773 => x"74", + 1774 => x"e0", + 1775 => x"ff", + 1776 => x"d0", + 1777 => x"ff", + 1778 => x"90", + 1779 => x"38", + 1780 => x"81", + 1781 => x"53", + 1782 => x"ca", + 1783 => x"27", + 1784 => x"77", + 1785 => x"08", + 1786 => x"0c", + 1787 => x"33", + 1788 => x"ff", + 1789 => x"80", + 1790 => x"74", + 1791 => x"79", + 1792 => x"74", + 1793 => x"0c", + 1794 => x"04", + 1795 => x"7a", + 1796 => x"80", + 1797 => x"58", + 1798 => x"33", + 1799 => x"a0", + 1800 => x"06", + 1801 => x"13", + 1802 => x"39", + 1803 => x"09", + 1804 => x"38", + 1805 => x"11", + 1806 => x"08", + 1807 => x"54", + 1808 => x"2e", + 1809 => x"80", + 1810 => x"08", + 1811 => x"0c", + 1812 => x"33", + 1813 => x"80", + 1814 => x"38", + 1815 => x"80", + 1816 => x"38", + 1817 => x"57", + 1818 => x"0c", + 1819 => x"33", + 1820 => x"39", + 1821 => x"74", + 1822 => x"38", + 1823 => x"80", + 1824 => x"89", + 1825 => x"38", + 1826 => x"d0", + 1827 => x"55", + 1828 => x"80", + 1829 => x"39", + 1830 => x"d9", + 1831 => x"80", + 1832 => x"27", + 1833 => x"80", + 1834 => x"89", + 1835 => x"70", + 1836 => x"55", + 1837 => x"70", + 1838 => x"55", + 1839 => x"27", + 1840 => x"14", + 1841 => x"06", + 1842 => x"74", + 1843 => x"73", + 1844 => x"38", + 1845 => x"14", + 1846 => x"05", + 1847 => x"08", + 1848 => x"54", + 1849 => x"39", + 1850 => x"84", + 1851 => x"55", + 1852 => x"81", + 1853 => x"de", + 1854 => x"3d", + 1855 => x"3d", + 1856 => x"05", + 1857 => x"52", + 1858 => x"87", + 1859 => x"e8", + 1860 => x"71", + 1861 => x"0c", + 1862 => x"04", + 1863 => x"02", + 1864 => x"02", + 1865 => x"05", + 1866 => x"83", + 1867 => x"26", + 1868 => x"72", + 1869 => x"c0", + 1870 => x"53", + 1871 => x"74", + 1872 => x"38", + 1873 => x"73", + 1874 => x"c0", + 1875 => x"51", + 1876 => x"85", + 1877 => x"98", + 1878 => x"52", + 1879 => x"82", + 1880 => x"70", + 1881 => x"38", + 1882 => x"8c", + 1883 => x"ec", + 1884 => x"fc", + 1885 => x"52", + 1886 => x"87", + 1887 => x"08", + 1888 => x"2e", + 1889 => x"81", + 1890 => x"34", + 1891 => x"13", + 1892 => x"81", + 1893 => x"86", + 1894 => x"f3", + 1895 => x"62", + 1896 => x"05", + 1897 => x"57", + 1898 => x"83", + 1899 => x"fe", + 1900 => x"de", + 1901 => x"06", + 1902 => x"71", + 1903 => x"71", + 1904 => x"2b", + 1905 => x"80", + 1906 => x"92", + 1907 => x"c0", + 1908 => x"41", + 1909 => x"5a", + 1910 => x"87", + 1911 => x"0c", + 1912 => x"84", + 1913 => x"08", + 1914 => x"70", + 1915 => x"53", + 1916 => x"2e", + 1917 => x"08", + 1918 => x"70", + 1919 => x"34", + 1920 => x"80", + 1921 => x"53", + 1922 => x"2e", + 1923 => x"53", + 1924 => x"26", + 1925 => x"80", + 1926 => x"87", + 1927 => x"08", + 1928 => x"38", + 1929 => x"8c", + 1930 => x"80", + 1931 => x"78", + 1932 => x"99", + 1933 => x"0c", + 1934 => x"8c", + 1935 => x"08", + 1936 => x"51", + 1937 => x"38", + 1938 => x"8d", + 1939 => x"17", + 1940 => x"81", + 1941 => x"53", + 1942 => x"2e", + 1943 => x"fc", + 1944 => x"52", + 1945 => x"7d", + 1946 => x"ed", + 1947 => x"80", + 1948 => x"71", + 1949 => x"38", + 1950 => x"53", + 1951 => x"c0", + 1952 => x"0d", + 1953 => x"0d", + 1954 => x"02", + 1955 => x"05", + 1956 => x"58", + 1957 => x"80", + 1958 => x"fc", + 1959 => x"de", + 1960 => x"06", + 1961 => x"71", + 1962 => x"81", + 1963 => x"38", + 1964 => x"2b", + 1965 => x"80", + 1966 => x"92", + 1967 => x"c0", + 1968 => x"40", + 1969 => x"5a", + 1970 => x"c0", + 1971 => x"76", + 1972 => x"76", + 1973 => x"75", + 1974 => x"2a", + 1975 => x"51", + 1976 => x"80", + 1977 => x"7a", + 1978 => x"5c", + 1979 => x"81", + 1980 => x"81", + 1981 => x"06", + 1982 => x"80", + 1983 => x"87", + 1984 => x"08", + 1985 => x"38", + 1986 => x"8c", + 1987 => x"80", + 1988 => x"77", + 1989 => x"99", + 1990 => x"0c", + 1991 => x"8c", + 1992 => x"08", + 1993 => x"51", + 1994 => x"38", + 1995 => x"8d", + 1996 => x"70", + 1997 => x"84", + 1998 => x"5b", + 1999 => x"2e", + 2000 => x"fc", + 2001 => x"52", + 2002 => x"7d", + 2003 => x"f8", + 2004 => x"80", + 2005 => x"71", + 2006 => x"38", + 2007 => x"53", + 2008 => x"c0", + 2009 => x"0d", + 2010 => x"0d", + 2011 => x"05", + 2012 => x"02", + 2013 => x"05", + 2014 => x"54", + 2015 => x"fe", + 2016 => x"c0", + 2017 => x"53", + 2018 => x"80", + 2019 => x"0b", + 2020 => x"8c", + 2021 => x"71", + 2022 => x"dc", + 2023 => x"24", + 2024 => x"84", + 2025 => x"92", + 2026 => x"54", + 2027 => x"8d", + 2028 => x"39", + 2029 => x"80", + 2030 => x"cb", + 2031 => x"70", + 2032 => x"81", + 2033 => x"52", + 2034 => x"8a", + 2035 => x"98", + 2036 => x"71", + 2037 => x"c0", + 2038 => x"52", + 2039 => x"81", + 2040 => x"c0", + 2041 => x"53", + 2042 => x"82", + 2043 => x"71", + 2044 => x"39", + 2045 => x"39", + 2046 => x"77", + 2047 => x"81", + 2048 => x"72", + 2049 => x"84", + 2050 => x"73", + 2051 => x"0c", + 2052 => x"04", + 2053 => x"74", + 2054 => x"71", + 2055 => x"2b", + 2056 => x"c0", + 2057 => x"84", + 2058 => x"fd", + 2059 => x"83", + 2060 => x"12", + 2061 => x"2b", + 2062 => x"07", + 2063 => x"70", + 2064 => x"2b", + 2065 => x"07", + 2066 => x"0c", + 2067 => x"56", + 2068 => x"3d", + 2069 => x"3d", + 2070 => x"84", + 2071 => x"22", + 2072 => x"72", + 2073 => x"54", + 2074 => x"2a", + 2075 => x"34", + 2076 => x"04", + 2077 => x"73", + 2078 => x"70", + 2079 => x"05", + 2080 => x"88", + 2081 => x"72", + 2082 => x"54", + 2083 => x"2a", + 2084 => x"70", + 2085 => x"34", + 2086 => x"51", + 2087 => x"83", + 2088 => x"fe", + 2089 => x"75", + 2090 => x"51", + 2091 => x"92", + 2092 => x"81", + 2093 => x"73", + 2094 => x"55", + 2095 => x"51", + 2096 => x"3d", + 2097 => x"3d", + 2098 => x"76", + 2099 => x"72", + 2100 => x"05", + 2101 => x"11", + 2102 => x"38", + 2103 => x"04", + 2104 => x"78", + 2105 => x"56", + 2106 => x"81", + 2107 => x"74", + 2108 => x"56", + 2109 => x"31", + 2110 => x"52", + 2111 => x"80", + 2112 => x"71", + 2113 => x"38", + 2114 => x"c0", + 2115 => x"0d", + 2116 => x"0d", + 2117 => x"51", + 2118 => x"73", + 2119 => x"81", + 2120 => x"33", + 2121 => x"38", + 2122 => x"de", + 2123 => x"3d", + 2124 => x"0b", + 2125 => x"0c", + 2126 => x"81", + 2127 => x"04", + 2128 => x"7b", + 2129 => x"83", + 2130 => x"5a", + 2131 => x"80", + 2132 => x"54", + 2133 => x"53", + 2134 => x"53", + 2135 => x"52", + 2136 => x"3f", + 2137 => x"08", + 2138 => x"81", + 2139 => x"81", + 2140 => x"83", + 2141 => x"16", + 2142 => x"18", + 2143 => x"18", + 2144 => x"58", + 2145 => x"9f", + 2146 => x"33", + 2147 => x"2e", + 2148 => x"93", + 2149 => x"76", + 2150 => x"52", + 2151 => x"51", + 2152 => x"83", + 2153 => x"79", + 2154 => x"0c", + 2155 => x"04", + 2156 => x"78", + 2157 => x"80", + 2158 => x"17", + 2159 => x"38", + 2160 => x"fc", + 2161 => x"c0", + 2162 => x"de", + 2163 => x"38", + 2164 => x"53", + 2165 => x"81", + 2166 => x"f7", + 2167 => x"de", + 2168 => x"2e", + 2169 => x"55", + 2170 => x"b0", + 2171 => x"81", + 2172 => x"88", + 2173 => x"f8", + 2174 => x"70", + 2175 => x"c0", + 2176 => x"c0", + 2177 => x"de", + 2178 => x"91", + 2179 => x"55", + 2180 => x"09", + 2181 => x"f0", + 2182 => x"33", + 2183 => x"2e", + 2184 => x"80", + 2185 => x"80", + 2186 => x"c0", + 2187 => x"17", + 2188 => x"fd", + 2189 => x"d4", + 2190 => x"b2", + 2191 => x"96", + 2192 => x"85", + 2193 => x"75", + 2194 => x"3f", + 2195 => x"e4", + 2196 => x"98", + 2197 => x"9c", + 2198 => x"08", + 2199 => x"17", + 2200 => x"3f", + 2201 => x"52", + 2202 => x"51", + 2203 => x"a0", + 2204 => x"05", + 2205 => x"0c", + 2206 => x"75", + 2207 => x"33", + 2208 => x"3f", + 2209 => x"34", + 2210 => x"52", + 2211 => x"51", + 2212 => x"81", + 2213 => x"80", + 2214 => x"81", + 2215 => x"de", + 2216 => x"3d", + 2217 => x"3d", + 2218 => x"1a", + 2219 => x"fe", + 2220 => x"54", + 2221 => x"73", + 2222 => x"8a", + 2223 => x"71", + 2224 => x"08", + 2225 => x"75", + 2226 => x"0c", + 2227 => x"04", + 2228 => x"7a", + 2229 => x"56", + 2230 => x"77", + 2231 => x"38", + 2232 => x"08", + 2233 => x"38", + 2234 => x"54", + 2235 => x"2e", + 2236 => x"72", + 2237 => x"38", + 2238 => x"8d", + 2239 => x"39", + 2240 => x"81", + 2241 => x"b6", + 2242 => x"2a", + 2243 => x"2a", + 2244 => x"05", + 2245 => x"55", + 2246 => x"81", + 2247 => x"81", + 2248 => x"83", + 2249 => x"b4", + 2250 => x"17", + 2251 => x"a4", + 2252 => x"55", + 2253 => x"57", + 2254 => x"3f", + 2255 => x"08", + 2256 => x"74", + 2257 => x"14", + 2258 => x"70", + 2259 => x"07", + 2260 => x"71", + 2261 => x"52", + 2262 => x"72", + 2263 => x"75", + 2264 => x"58", + 2265 => x"76", + 2266 => x"15", + 2267 => x"73", + 2268 => x"3f", + 2269 => x"08", + 2270 => x"76", + 2271 => x"06", + 2272 => x"05", + 2273 => x"3f", + 2274 => x"08", + 2275 => x"06", + 2276 => x"76", + 2277 => x"15", + 2278 => x"73", + 2279 => x"3f", + 2280 => x"08", + 2281 => x"82", + 2282 => x"06", + 2283 => x"05", + 2284 => x"3f", + 2285 => x"08", + 2286 => x"58", + 2287 => x"58", + 2288 => x"c0", + 2289 => x"0d", + 2290 => x"0d", + 2291 => x"5a", + 2292 => x"59", + 2293 => x"82", + 2294 => x"98", + 2295 => x"82", + 2296 => x"33", + 2297 => x"2e", + 2298 => x"72", + 2299 => x"38", + 2300 => x"8d", + 2301 => x"39", + 2302 => x"81", + 2303 => x"f7", + 2304 => x"2a", + 2305 => x"2a", + 2306 => x"05", + 2307 => x"55", + 2308 => x"81", + 2309 => x"59", + 2310 => x"08", + 2311 => x"74", + 2312 => x"16", + 2313 => x"16", + 2314 => x"59", + 2315 => x"53", + 2316 => x"8f", + 2317 => x"2b", + 2318 => x"74", + 2319 => x"71", + 2320 => x"72", + 2321 => x"0b", + 2322 => x"74", + 2323 => x"17", + 2324 => x"75", + 2325 => x"3f", + 2326 => x"08", + 2327 => x"c0", + 2328 => x"38", + 2329 => x"06", + 2330 => x"78", + 2331 => x"54", + 2332 => x"77", + 2333 => x"33", + 2334 => x"71", + 2335 => x"51", + 2336 => x"34", + 2337 => x"76", + 2338 => x"17", + 2339 => x"75", + 2340 => x"3f", + 2341 => x"08", + 2342 => x"c0", + 2343 => x"38", + 2344 => x"ff", + 2345 => x"10", + 2346 => x"76", + 2347 => x"51", + 2348 => x"be", + 2349 => x"2a", + 2350 => x"05", + 2351 => x"f9", + 2352 => x"de", + 2353 => x"81", + 2354 => x"ab", + 2355 => x"0a", + 2356 => x"2b", + 2357 => x"70", + 2358 => x"70", + 2359 => x"54", + 2360 => x"81", + 2361 => x"8f", + 2362 => x"07", + 2363 => x"f7", + 2364 => x"0b", + 2365 => x"78", + 2366 => x"0c", + 2367 => x"04", + 2368 => x"7a", + 2369 => x"08", + 2370 => x"59", + 2371 => x"a4", + 2372 => x"17", + 2373 => x"38", + 2374 => x"aa", + 2375 => x"73", + 2376 => x"fd", + 2377 => x"de", + 2378 => x"81", + 2379 => x"80", + 2380 => x"39", + 2381 => x"eb", + 2382 => x"80", + 2383 => x"de", + 2384 => x"80", + 2385 => x"52", + 2386 => x"84", + 2387 => x"c0", + 2388 => x"de", + 2389 => x"2e", + 2390 => x"81", + 2391 => x"81", + 2392 => x"81", + 2393 => x"ff", + 2394 => x"80", + 2395 => x"75", + 2396 => x"3f", + 2397 => x"08", + 2398 => x"16", + 2399 => x"90", + 2400 => x"55", + 2401 => x"27", + 2402 => x"15", + 2403 => x"84", + 2404 => x"07", + 2405 => x"17", + 2406 => x"76", + 2407 => x"a6", + 2408 => x"73", + 2409 => x"0c", + 2410 => x"04", + 2411 => x"7c", + 2412 => x"59", + 2413 => x"95", + 2414 => x"08", + 2415 => x"2e", + 2416 => x"17", + 2417 => x"b2", + 2418 => x"ae", + 2419 => x"7a", + 2420 => x"3f", + 2421 => x"81", + 2422 => x"27", + 2423 => x"81", + 2424 => x"55", + 2425 => x"08", + 2426 => x"d2", + 2427 => x"08", + 2428 => x"08", + 2429 => x"38", + 2430 => x"17", + 2431 => x"54", + 2432 => x"82", + 2433 => x"7a", + 2434 => x"06", + 2435 => x"81", + 2436 => x"17", + 2437 => x"83", + 2438 => x"75", + 2439 => x"f9", + 2440 => x"59", + 2441 => x"08", + 2442 => x"81", + 2443 => x"81", + 2444 => x"59", + 2445 => x"08", + 2446 => x"70", + 2447 => x"25", + 2448 => x"81", + 2449 => x"54", + 2450 => x"55", + 2451 => x"38", + 2452 => x"08", + 2453 => x"38", + 2454 => x"54", + 2455 => x"90", + 2456 => x"18", + 2457 => x"38", + 2458 => x"39", + 2459 => x"38", + 2460 => x"16", + 2461 => x"08", + 2462 => x"38", + 2463 => x"78", + 2464 => x"38", + 2465 => x"51", + 2466 => x"81", + 2467 => x"80", + 2468 => x"80", + 2469 => x"c0", + 2470 => x"09", + 2471 => x"38", + 2472 => x"08", + 2473 => x"c0", + 2474 => x"30", + 2475 => x"80", + 2476 => x"07", + 2477 => x"55", + 2478 => x"38", + 2479 => x"09", + 2480 => x"ae", + 2481 => x"80", + 2482 => x"53", + 2483 => x"51", + 2484 => x"81", + 2485 => x"81", + 2486 => x"30", + 2487 => x"c0", + 2488 => x"25", + 2489 => x"79", + 2490 => x"38", + 2491 => x"8f", + 2492 => x"79", + 2493 => x"f9", + 2494 => x"de", + 2495 => x"74", + 2496 => x"8c", + 2497 => x"17", + 2498 => x"90", + 2499 => x"54", + 2500 => x"86", + 2501 => x"90", + 2502 => x"17", + 2503 => x"54", + 2504 => x"34", + 2505 => x"56", + 2506 => x"90", + 2507 => x"80", + 2508 => x"81", + 2509 => x"55", + 2510 => x"56", + 2511 => x"81", + 2512 => x"8c", + 2513 => x"f8", + 2514 => x"70", + 2515 => x"f0", + 2516 => x"c0", + 2517 => x"56", + 2518 => x"08", + 2519 => x"7b", + 2520 => x"f6", + 2521 => x"de", + 2522 => x"de", + 2523 => x"17", + 2524 => x"80", + 2525 => x"b4", + 2526 => x"57", + 2527 => x"77", + 2528 => x"81", + 2529 => x"15", + 2530 => x"78", + 2531 => x"81", + 2532 => x"53", + 2533 => x"15", + 2534 => x"e9", + 2535 => x"c0", + 2536 => x"df", + 2537 => x"22", + 2538 => x"30", + 2539 => x"70", + 2540 => x"51", + 2541 => x"81", + 2542 => x"8a", + 2543 => x"f8", + 2544 => x"7c", + 2545 => x"56", + 2546 => x"80", + 2547 => x"f1", + 2548 => x"06", + 2549 => x"e9", + 2550 => x"18", + 2551 => x"08", + 2552 => x"38", + 2553 => x"82", + 2554 => x"38", + 2555 => x"54", + 2556 => x"74", + 2557 => x"82", + 2558 => x"22", + 2559 => x"79", + 2560 => x"38", + 2561 => x"98", + 2562 => x"cd", + 2563 => x"22", + 2564 => x"54", + 2565 => x"26", + 2566 => x"52", + 2567 => x"b0", + 2568 => x"c0", + 2569 => x"de", + 2570 => x"2e", + 2571 => x"0b", + 2572 => x"08", + 2573 => x"98", + 2574 => x"de", + 2575 => x"85", + 2576 => x"bd", + 2577 => x"31", + 2578 => x"73", + 2579 => x"f4", + 2580 => x"de", + 2581 => x"18", + 2582 => x"18", + 2583 => x"08", + 2584 => x"72", + 2585 => x"38", + 2586 => x"58", + 2587 => x"89", + 2588 => x"18", + 2589 => x"ff", + 2590 => x"05", + 2591 => x"80", + 2592 => x"de", + 2593 => x"3d", + 2594 => x"3d", + 2595 => x"08", + 2596 => x"a0", + 2597 => x"54", + 2598 => x"77", + 2599 => x"80", + 2600 => x"0c", + 2601 => x"53", + 2602 => x"80", + 2603 => x"38", + 2604 => x"06", + 2605 => x"b5", + 2606 => x"98", + 2607 => x"14", + 2608 => x"92", + 2609 => x"2a", + 2610 => x"56", + 2611 => x"26", + 2612 => x"80", + 2613 => x"16", + 2614 => x"77", + 2615 => x"53", + 2616 => x"38", + 2617 => x"51", + 2618 => x"81", + 2619 => x"53", + 2620 => x"0b", + 2621 => x"08", + 2622 => x"38", + 2623 => x"de", + 2624 => x"2e", + 2625 => x"98", + 2626 => x"de", + 2627 => x"80", + 2628 => x"8a", + 2629 => x"15", + 2630 => x"80", + 2631 => x"14", + 2632 => x"51", + 2633 => x"81", + 2634 => x"53", + 2635 => x"de", + 2636 => x"2e", + 2637 => x"82", + 2638 => x"c0", + 2639 => x"ba", + 2640 => x"81", + 2641 => x"ff", + 2642 => x"81", + 2643 => x"52", + 2644 => x"f3", + 2645 => x"c0", + 2646 => x"72", + 2647 => x"72", + 2648 => x"f2", + 2649 => x"de", + 2650 => x"15", + 2651 => x"15", + 2652 => x"b4", + 2653 => x"0c", + 2654 => x"81", + 2655 => x"8a", + 2656 => x"f7", + 2657 => x"7d", + 2658 => x"5b", + 2659 => x"76", + 2660 => x"3f", + 2661 => x"08", + 2662 => x"c0", + 2663 => x"38", + 2664 => x"08", + 2665 => x"08", + 2666 => x"f0", + 2667 => x"de", + 2668 => x"81", + 2669 => x"80", + 2670 => x"de", + 2671 => x"18", + 2672 => x"51", + 2673 => x"81", + 2674 => x"81", + 2675 => x"81", + 2676 => x"c0", + 2677 => x"83", + 2678 => x"77", + 2679 => x"72", + 2680 => x"38", + 2681 => x"75", + 2682 => x"81", + 2683 => x"a5", + 2684 => x"c0", + 2685 => x"52", + 2686 => x"8e", + 2687 => x"c0", + 2688 => x"de", + 2689 => x"2e", + 2690 => x"73", + 2691 => x"81", + 2692 => x"87", + 2693 => x"de", + 2694 => x"3d", + 2695 => x"3d", + 2696 => x"11", + 2697 => x"ec", + 2698 => x"c0", + 2699 => x"ff", + 2700 => x"33", + 2701 => x"71", + 2702 => x"81", + 2703 => x"94", + 2704 => x"d0", + 2705 => x"c0", + 2706 => x"73", + 2707 => x"81", + 2708 => x"85", + 2709 => x"fc", + 2710 => x"79", + 2711 => x"ff", + 2712 => x"12", + 2713 => x"eb", + 2714 => x"70", + 2715 => x"72", + 2716 => x"81", + 2717 => x"73", + 2718 => x"94", + 2719 => x"d6", + 2720 => x"0d", + 2721 => x"0d", + 2722 => x"55", + 2723 => x"5a", + 2724 => x"08", + 2725 => x"8a", + 2726 => x"08", + 2727 => x"ee", + 2728 => x"de", + 2729 => x"81", + 2730 => x"80", + 2731 => x"15", + 2732 => x"55", + 2733 => x"38", + 2734 => x"e6", + 2735 => x"33", + 2736 => x"70", + 2737 => x"58", + 2738 => x"86", + 2739 => x"de", + 2740 => x"73", + 2741 => x"83", + 2742 => x"73", + 2743 => x"38", + 2744 => x"06", + 2745 => x"80", + 2746 => x"75", + 2747 => x"38", + 2748 => x"08", + 2749 => x"54", + 2750 => x"2e", + 2751 => x"83", + 2752 => x"73", + 2753 => x"38", + 2754 => x"51", + 2755 => x"81", + 2756 => x"58", + 2757 => x"08", + 2758 => x"15", + 2759 => x"38", + 2760 => x"0b", + 2761 => x"77", + 2762 => x"0c", + 2763 => x"04", + 2764 => x"77", + 2765 => x"54", + 2766 => x"51", + 2767 => x"81", + 2768 => x"55", + 2769 => x"08", + 2770 => x"14", + 2771 => x"51", + 2772 => x"81", + 2773 => x"55", + 2774 => x"08", + 2775 => x"53", + 2776 => x"08", + 2777 => x"08", + 2778 => x"3f", + 2779 => x"14", + 2780 => x"08", + 2781 => x"3f", + 2782 => x"17", + 2783 => x"de", + 2784 => x"3d", + 2785 => x"3d", + 2786 => x"08", + 2787 => x"54", + 2788 => x"53", + 2789 => x"81", + 2790 => x"8d", + 2791 => x"08", + 2792 => x"34", + 2793 => x"15", + 2794 => x"0d", + 2795 => x"0d", + 2796 => x"57", + 2797 => x"17", + 2798 => x"08", + 2799 => x"82", + 2800 => x"89", + 2801 => x"55", + 2802 => x"14", + 2803 => x"16", + 2804 => x"71", + 2805 => x"38", + 2806 => x"09", + 2807 => x"38", + 2808 => x"73", + 2809 => x"81", + 2810 => x"ae", + 2811 => x"05", + 2812 => x"15", + 2813 => x"70", + 2814 => x"34", + 2815 => x"8a", + 2816 => x"38", + 2817 => x"05", + 2818 => x"81", + 2819 => x"17", + 2820 => x"12", + 2821 => x"34", + 2822 => x"9c", + 2823 => x"e8", + 2824 => x"de", + 2825 => x"0c", + 2826 => x"e7", + 2827 => x"de", + 2828 => x"17", + 2829 => x"51", + 2830 => x"81", + 2831 => x"84", + 2832 => x"3d", + 2833 => x"3d", + 2834 => x"08", + 2835 => x"61", + 2836 => x"55", + 2837 => x"2e", + 2838 => x"55", + 2839 => x"2e", + 2840 => x"80", + 2841 => x"94", + 2842 => x"1c", + 2843 => x"81", + 2844 => x"61", + 2845 => x"56", + 2846 => x"2e", + 2847 => x"83", + 2848 => x"73", + 2849 => x"70", + 2850 => x"25", + 2851 => x"51", + 2852 => x"38", + 2853 => x"0c", + 2854 => x"51", + 2855 => x"26", + 2856 => x"80", + 2857 => x"34", + 2858 => x"51", + 2859 => x"81", + 2860 => x"55", + 2861 => x"91", + 2862 => x"1d", + 2863 => x"8b", + 2864 => x"79", + 2865 => x"3f", + 2866 => x"57", + 2867 => x"55", + 2868 => x"2e", + 2869 => x"80", + 2870 => x"18", + 2871 => x"1a", + 2872 => x"70", + 2873 => x"2a", + 2874 => x"07", + 2875 => x"5a", + 2876 => x"8c", + 2877 => x"54", + 2878 => x"81", + 2879 => x"39", + 2880 => x"70", + 2881 => x"2a", + 2882 => x"75", + 2883 => x"8c", + 2884 => x"2e", + 2885 => x"a0", + 2886 => x"38", + 2887 => x"0c", + 2888 => x"76", + 2889 => x"38", + 2890 => x"b8", + 2891 => x"70", + 2892 => x"5a", + 2893 => x"76", + 2894 => x"38", + 2895 => x"70", + 2896 => x"dc", + 2897 => x"72", + 2898 => x"80", + 2899 => x"51", + 2900 => x"73", + 2901 => x"38", + 2902 => x"18", + 2903 => x"1a", + 2904 => x"55", + 2905 => x"2e", + 2906 => x"83", + 2907 => x"73", + 2908 => x"70", + 2909 => x"25", + 2910 => x"51", + 2911 => x"38", + 2912 => x"75", + 2913 => x"81", + 2914 => x"81", + 2915 => x"27", + 2916 => x"73", + 2917 => x"38", + 2918 => x"70", + 2919 => x"32", + 2920 => x"80", + 2921 => x"2a", + 2922 => x"56", + 2923 => x"81", + 2924 => x"57", + 2925 => x"f5", + 2926 => x"2b", + 2927 => x"25", + 2928 => x"80", + 2929 => x"cd", + 2930 => x"57", + 2931 => x"e6", + 2932 => x"de", + 2933 => x"2e", + 2934 => x"18", + 2935 => x"1a", + 2936 => x"56", + 2937 => x"3f", + 2938 => x"08", + 2939 => x"e8", + 2940 => x"54", + 2941 => x"80", + 2942 => x"17", + 2943 => x"34", + 2944 => x"11", + 2945 => x"74", + 2946 => x"75", + 2947 => x"d4", + 2948 => x"3f", + 2949 => x"08", + 2950 => x"9f", + 2951 => x"99", + 2952 => x"e0", + 2953 => x"ff", + 2954 => x"79", + 2955 => x"74", + 2956 => x"57", + 2957 => x"77", + 2958 => x"76", + 2959 => x"38", + 2960 => x"73", + 2961 => x"09", + 2962 => x"38", + 2963 => x"84", + 2964 => x"27", + 2965 => x"39", + 2966 => x"f2", + 2967 => x"80", + 2968 => x"54", + 2969 => x"34", + 2970 => x"58", + 2971 => x"f2", + 2972 => x"de", + 2973 => x"81", + 2974 => x"80", + 2975 => x"1b", + 2976 => x"51", + 2977 => x"81", + 2978 => x"56", + 2979 => x"08", + 2980 => x"9c", + 2981 => x"33", + 2982 => x"80", + 2983 => x"38", + 2984 => x"bf", + 2985 => x"86", + 2986 => x"15", + 2987 => x"2a", + 2988 => x"51", + 2989 => x"92", + 2990 => x"79", + 2991 => x"e4", + 2992 => x"de", + 2993 => x"2e", + 2994 => x"52", + 2995 => x"ba", + 2996 => x"39", + 2997 => x"33", + 2998 => x"80", + 2999 => x"74", + 3000 => x"81", + 3001 => x"38", + 3002 => x"70", + 3003 => x"82", + 3004 => x"54", + 3005 => x"96", + 3006 => x"06", + 3007 => x"2e", + 3008 => x"ff", + 3009 => x"1c", + 3010 => x"80", + 3011 => x"81", + 3012 => x"ba", + 3013 => x"b6", + 3014 => x"2a", + 3015 => x"51", + 3016 => x"38", + 3017 => x"70", + 3018 => x"81", + 3019 => x"55", + 3020 => x"e1", + 3021 => x"08", + 3022 => x"1d", + 3023 => x"7c", + 3024 => x"3f", + 3025 => x"08", + 3026 => x"fa", + 3027 => x"81", + 3028 => x"8f", + 3029 => x"f6", + 3030 => x"5b", + 3031 => x"70", + 3032 => x"59", + 3033 => x"73", + 3034 => x"c6", + 3035 => x"81", + 3036 => x"70", + 3037 => x"52", + 3038 => x"8d", + 3039 => x"38", + 3040 => x"09", + 3041 => x"a5", + 3042 => x"d0", + 3043 => x"ff", + 3044 => x"53", + 3045 => x"91", + 3046 => x"73", + 3047 => x"d0", + 3048 => x"71", + 3049 => x"f7", + 3050 => x"81", + 3051 => x"55", + 3052 => x"55", + 3053 => x"81", + 3054 => x"74", + 3055 => x"56", + 3056 => x"12", + 3057 => x"70", + 3058 => x"38", + 3059 => x"81", + 3060 => x"51", + 3061 => x"51", + 3062 => x"89", + 3063 => x"70", + 3064 => x"53", + 3065 => x"70", + 3066 => x"51", + 3067 => x"09", + 3068 => x"38", + 3069 => x"38", + 3070 => x"77", + 3071 => x"70", + 3072 => x"2a", + 3073 => x"07", + 3074 => x"51", + 3075 => x"8f", + 3076 => x"84", + 3077 => x"83", + 3078 => x"94", + 3079 => x"74", + 3080 => x"38", + 3081 => x"0c", + 3082 => x"86", + 3083 => x"f0", + 3084 => x"81", + 3085 => x"8c", + 3086 => x"fa", + 3087 => x"56", + 3088 => x"17", + 3089 => x"b0", + 3090 => x"52", + 3091 => x"e0", + 3092 => x"81", + 3093 => x"81", + 3094 => x"b2", + 3095 => x"b4", + 3096 => x"c0", + 3097 => x"ff", + 3098 => x"55", + 3099 => x"d5", + 3100 => x"06", + 3101 => x"80", + 3102 => x"33", + 3103 => x"81", + 3104 => x"81", + 3105 => x"81", + 3106 => x"eb", + 3107 => x"70", + 3108 => x"07", + 3109 => x"73", + 3110 => x"81", + 3111 => x"81", + 3112 => x"83", + 3113 => x"e4", + 3114 => x"16", + 3115 => x"3f", + 3116 => x"08", + 3117 => x"c0", + 3118 => x"9d", + 3119 => x"81", + 3120 => x"81", + 3121 => x"e0", + 3122 => x"de", + 3123 => x"81", + 3124 => x"80", + 3125 => x"82", + 3126 => x"de", + 3127 => x"3d", + 3128 => x"3d", + 3129 => x"84", + 3130 => x"05", + 3131 => x"80", + 3132 => x"51", + 3133 => x"81", + 3134 => x"58", + 3135 => x"0b", + 3136 => x"08", + 3137 => x"38", + 3138 => x"08", + 3139 => x"de", + 3140 => x"08", + 3141 => x"56", + 3142 => x"86", + 3143 => x"75", + 3144 => x"fe", + 3145 => x"54", + 3146 => x"2e", + 3147 => x"14", + 3148 => x"ca", + 3149 => x"c0", + 3150 => x"06", + 3151 => x"54", + 3152 => x"38", + 3153 => x"86", + 3154 => x"82", + 3155 => x"06", + 3156 => x"56", + 3157 => x"38", + 3158 => x"80", + 3159 => x"81", + 3160 => x"52", + 3161 => x"51", + 3162 => x"81", + 3163 => x"81", + 3164 => x"81", + 3165 => x"83", + 3166 => x"87", + 3167 => x"2e", + 3168 => x"82", + 3169 => x"06", + 3170 => x"56", + 3171 => x"38", + 3172 => x"74", + 3173 => x"a3", + 3174 => x"c0", + 3175 => x"06", + 3176 => x"2e", + 3177 => x"80", + 3178 => x"3d", + 3179 => x"83", + 3180 => x"15", + 3181 => x"53", + 3182 => x"8d", + 3183 => x"15", + 3184 => x"3f", + 3185 => x"08", + 3186 => x"70", + 3187 => x"0c", + 3188 => x"16", + 3189 => x"80", + 3190 => x"80", + 3191 => x"54", + 3192 => x"84", + 3193 => x"5b", + 3194 => x"80", + 3195 => x"7a", + 3196 => x"fc", + 3197 => x"de", + 3198 => x"ff", + 3199 => x"77", + 3200 => x"81", + 3201 => x"76", + 3202 => x"81", + 3203 => x"2e", + 3204 => x"8d", + 3205 => x"26", + 3206 => x"bf", + 3207 => x"f4", + 3208 => x"c0", + 3209 => x"ff", + 3210 => x"84", + 3211 => x"81", + 3212 => x"38", + 3213 => x"51", + 3214 => x"81", + 3215 => x"83", + 3216 => x"58", + 3217 => x"80", + 3218 => x"db", + 3219 => x"de", + 3220 => x"77", + 3221 => x"80", + 3222 => x"82", + 3223 => x"c4", + 3224 => x"11", + 3225 => x"06", + 3226 => x"8d", + 3227 => x"26", + 3228 => x"74", + 3229 => x"78", + 3230 => x"c1", + 3231 => x"59", + 3232 => x"15", + 3233 => x"2e", + 3234 => x"13", + 3235 => x"72", + 3236 => x"38", + 3237 => x"eb", + 3238 => x"14", + 3239 => x"3f", + 3240 => x"08", + 3241 => x"c0", + 3242 => x"23", + 3243 => x"57", + 3244 => x"83", + 3245 => x"c7", + 3246 => x"d8", + 3247 => x"c0", + 3248 => x"ff", + 3249 => x"8d", + 3250 => x"14", + 3251 => x"3f", + 3252 => x"08", + 3253 => x"14", + 3254 => x"3f", + 3255 => x"08", + 3256 => x"06", + 3257 => x"72", + 3258 => x"97", + 3259 => x"22", + 3260 => x"84", + 3261 => x"5a", + 3262 => x"83", + 3263 => x"14", + 3264 => x"79", + 3265 => x"ac", + 3266 => x"de", + 3267 => x"81", + 3268 => x"80", + 3269 => x"38", + 3270 => x"08", + 3271 => x"ff", + 3272 => x"38", + 3273 => x"83", + 3274 => x"83", + 3275 => x"74", + 3276 => x"85", + 3277 => x"89", + 3278 => x"76", + 3279 => x"c3", + 3280 => x"70", + 3281 => x"7b", + 3282 => x"73", + 3283 => x"17", + 3284 => x"ac", + 3285 => x"55", + 3286 => x"09", + 3287 => x"38", + 3288 => x"51", + 3289 => x"81", + 3290 => x"83", + 3291 => x"53", + 3292 => x"82", + 3293 => x"82", + 3294 => x"e0", + 3295 => x"ab", + 3296 => x"c0", + 3297 => x"0c", + 3298 => x"53", + 3299 => x"56", + 3300 => x"81", + 3301 => x"13", + 3302 => x"74", + 3303 => x"82", + 3304 => x"74", + 3305 => x"81", + 3306 => x"06", + 3307 => x"83", + 3308 => x"2a", + 3309 => x"72", + 3310 => x"26", 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x"38", + 3370 => x"84", + 3371 => x"52", + 3372 => x"09", + 3373 => x"38", + 3374 => x"51", + 3375 => x"81", + 3376 => x"81", + 3377 => x"88", + 3378 => x"08", + 3379 => x"39", + 3380 => x"73", + 3381 => x"74", + 3382 => x"0c", + 3383 => x"04", + 3384 => x"02", + 3385 => x"7a", + 3386 => x"fc", + 3387 => x"f4", + 3388 => x"54", + 3389 => x"de", + 3390 => x"bc", + 3391 => x"c0", + 3392 => x"81", + 3393 => x"70", + 3394 => x"73", + 3395 => x"38", + 3396 => x"78", + 3397 => x"2e", + 3398 => x"74", + 3399 => x"0c", + 3400 => x"80", + 3401 => x"80", + 3402 => x"70", + 3403 => x"51", + 3404 => x"81", + 3405 => x"54", + 3406 => x"c0", + 3407 => x"0d", + 3408 => x"0d", + 3409 => x"05", + 3410 => x"33", + 3411 => x"54", + 3412 => x"84", + 3413 => x"bf", + 3414 => x"98", + 3415 => x"53", + 3416 => x"05", + 3417 => x"fa", + 3418 => x"c0", + 3419 => x"de", + 3420 => x"a4", + 3421 => x"68", + 3422 => x"70", + 3423 => x"c6", + 3424 => x"c0", + 3425 => x"de", + 3426 => x"38", + 3427 => x"05", + 3428 => x"2b", + 3429 => x"80", + 3430 => x"86", + 3431 => x"06", + 3432 => x"2e", + 3433 => x"74", + 3434 => x"38", + 3435 => x"09", + 3436 => x"38", + 3437 => x"f8", + 3438 => x"c0", + 3439 => x"39", + 3440 => x"33", + 3441 => x"73", + 3442 => x"77", + 3443 => x"81", + 3444 => x"73", + 3445 => x"38", + 3446 => x"bc", + 3447 => x"07", + 3448 => x"b4", + 3449 => x"2a", + 3450 => x"51", + 3451 => x"2e", + 3452 => x"62", + 3453 => x"e8", + 3454 => x"de", + 3455 => x"82", + 3456 => x"52", + 3457 => x"51", + 3458 => x"62", + 3459 => x"8b", + 3460 => x"53", + 3461 => x"51", + 3462 => x"80", + 3463 => x"05", + 3464 => x"3f", + 3465 => x"0b", + 3466 => x"75", + 3467 => x"f1", + 3468 => x"11", + 3469 => x"80", + 3470 => x"97", + 3471 => x"51", + 3472 => x"81", + 3473 => x"55", + 3474 => x"08", + 3475 => x"b7", + 3476 => x"c4", + 3477 => x"05", + 3478 => x"2a", + 3479 => x"51", + 3480 => x"80", + 3481 => x"84", + 3482 => x"39", + 3483 => x"70", + 3484 => x"54", + 3485 => x"a9", + 3486 => x"06", + 3487 => x"2e", + 3488 => x"55", + 3489 => x"73", + 3490 => x"d6", + 3491 => x"de", + 3492 => x"ff", + 3493 => x"0c", + 3494 => x"de", + 3495 => x"f8", + 3496 => x"2a", + 3497 => x"51", + 3498 => x"2e", + 3499 => x"80", + 3500 => x"7a", + 3501 => x"a0", + 3502 => x"a4", + 3503 => x"53", + 3504 => x"e6", + 3505 => x"de", + 3506 => x"de", + 3507 => x"1b", + 3508 => x"05", + 3509 => x"d3", + 3510 => x"c0", + 3511 => x"c0", + 3512 => x"0c", + 3513 => x"56", + 3514 => x"84", + 3515 => x"90", + 3516 => x"0b", + 3517 => x"80", + 3518 => x"0c", + 3519 => x"1a", + 3520 => x"2a", + 3521 => x"51", + 3522 => x"2e", + 3523 => x"81", + 3524 => x"80", + 3525 => x"38", + 3526 => x"08", + 3527 => x"8a", + 3528 => x"89", + 3529 => x"59", + 3530 => x"76", + 3531 => x"d7", + 3532 => x"de", + 3533 => x"81", + 3534 => x"81", + 3535 => x"82", + 3536 => x"c0", + 3537 => x"09", + 3538 => x"38", + 3539 => x"78", + 3540 => x"30", + 3541 => x"80", + 3542 => x"77", + 3543 => x"38", + 3544 => x"06", + 3545 => x"c3", + 3546 => x"1a", + 3547 => x"38", + 3548 => x"06", + 3549 => x"2e", + 3550 => x"52", + 3551 => x"a6", + 3552 => x"c0", + 3553 => x"82", + 3554 => x"75", + 3555 => x"de", + 3556 => x"9c", + 3557 => x"39", + 3558 => x"74", + 3559 => x"de", + 3560 => x"3d", + 3561 => x"3d", + 3562 => x"65", + 3563 => x"5d", + 3564 => x"0c", + 3565 => x"05", + 3566 => x"f9", + 3567 => x"de", + 3568 => x"81", + 3569 => x"8a", + 3570 => x"33", + 3571 => x"2e", + 3572 => x"56", + 3573 => x"90", + 3574 => x"06", + 3575 => x"74", + 3576 => x"b6", + 3577 => x"82", + 3578 => x"34", + 3579 => x"aa", + 3580 => x"91", + 3581 => x"56", + 3582 => x"8c", + 3583 => x"1a", + 3584 => x"74", + 3585 => x"38", + 3586 => x"80", + 3587 => x"38", + 3588 => x"70", + 3589 => x"56", + 3590 => x"b2", + 3591 => x"11", + 3592 => x"77", + 3593 => x"5b", + 3594 => x"38", + 3595 => x"88", + 3596 => x"8f", + 3597 => x"08", + 3598 => x"d5", + 3599 => x"de", + 3600 => x"81", + 3601 => x"9f", + 3602 => x"2e", + 3603 => x"74", + 3604 => x"98", + 3605 => x"7e", + 3606 => x"3f", + 3607 => x"08", + 3608 => x"83", + 3609 => x"c0", + 3610 => x"89", + 3611 => x"77", + 3612 => x"d6", + 3613 => x"7f", + 3614 => x"58", + 3615 => x"75", + 3616 => x"75", + 3617 => x"77", + 3618 => x"7c", + 3619 => x"33", + 3620 => x"3f", + 3621 => x"08", + 3622 => x"7e", + 3623 => x"56", + 3624 => x"2e", + 3625 => x"16", + 3626 => x"55", + 3627 => x"94", + 3628 => x"53", + 3629 => x"b0", + 3630 => x"31", + 3631 => x"05", + 3632 => x"3f", + 3633 => x"56", + 3634 => x"9c", + 3635 => x"19", + 3636 => x"06", + 3637 => x"31", + 3638 => x"76", + 3639 => x"7b", + 3640 => x"08", + 3641 => x"d1", + 3642 => x"de", + 3643 => x"81", + 3644 => x"94", + 3645 => x"ff", + 3646 => x"05", + 3647 => x"cf", + 3648 => x"76", + 3649 => x"17", + 3650 => x"1e", + 3651 => x"18", + 3652 => x"5e", + 3653 => x"39", + 3654 => x"81", + 3655 => x"90", + 3656 => x"f2", + 3657 => x"63", + 3658 => x"40", + 3659 => x"7e", + 3660 => x"fc", + 3661 => x"51", + 3662 => x"81", + 3663 => x"55", + 3664 => x"08", + 3665 => x"18", + 3666 => x"80", + 3667 => x"74", + 3668 => x"39", + 3669 => x"70", + 3670 => x"81", + 3671 => x"56", + 3672 => x"80", + 3673 => x"38", + 3674 => x"0b", + 3675 => x"82", + 3676 => x"39", + 3677 => x"19", + 3678 => x"83", + 3679 => x"18", + 3680 => x"56", + 3681 => x"27", + 3682 => x"09", + 3683 => x"2e", + 3684 => x"94", + 3685 => x"83", + 3686 => x"56", + 3687 => x"38", + 3688 => x"22", + 3689 => x"89", + 3690 => x"55", + 3691 => x"75", + 3692 => x"18", + 3693 => x"9c", + 3694 => x"85", + 3695 => x"08", + 3696 => x"d7", + 3697 => x"de", + 3698 => x"81", + 3699 => x"80", + 3700 => x"38", + 3701 => x"ff", + 3702 => x"ff", + 3703 => x"38", + 3704 => x"0c", + 3705 => x"85", + 3706 => x"19", + 3707 => x"b0", + 3708 => x"19", + 3709 => x"81", + 3710 => x"74", + 3711 => x"3f", + 3712 => x"08", + 3713 => x"98", + 3714 => x"7e", + 3715 => x"3f", + 3716 => x"08", + 3717 => x"d2", + 3718 => x"c0", + 3719 => x"89", + 3720 => x"78", + 3721 => x"d5", + 3722 => x"7f", + 3723 => x"58", + 3724 => x"75", + 3725 => x"75", + 3726 => x"78", + 3727 => x"7c", + 3728 => x"33", + 3729 => x"3f", + 3730 => x"08", + 3731 => x"7e", + 3732 => x"78", + 3733 => x"74", + 3734 => x"38", + 3735 => x"b0", + 3736 => x"31", + 3737 => x"05", + 3738 => x"51", + 3739 => x"7e", + 3740 => x"83", + 3741 => x"89", + 3742 => x"db", + 3743 => x"08", + 3744 => x"26", + 3745 => x"51", + 3746 => x"81", + 3747 => x"fd", + 3748 => x"77", + 3749 => x"55", + 3750 => x"0c", + 3751 => x"83", + 3752 => x"80", + 3753 => x"55", + 3754 => x"83", + 3755 => x"9c", + 3756 => x"7e", + 3757 => x"3f", + 3758 => x"08", + 3759 => x"75", + 3760 => x"94", + 3761 => x"ff", + 3762 => x"05", + 3763 => x"3f", + 3764 => x"0b", + 3765 => x"7b", + 3766 => x"08", + 3767 => x"76", + 3768 => x"08", + 3769 => x"1c", + 3770 => x"08", + 3771 => x"5c", + 3772 => x"83", + 3773 => x"74", + 3774 => x"fd", + 3775 => x"18", + 3776 => x"07", + 3777 => x"19", + 3778 => x"75", + 3779 => x"0c", + 3780 => x"04", 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x"81", + 3840 => x"81", + 3841 => x"80", + 3842 => x"de", + 3843 => x"3d", + 3844 => x"3d", + 3845 => x"93", + 3846 => x"52", + 3847 => x"e9", + 3848 => x"de", + 3849 => x"81", + 3850 => x"80", + 3851 => x"58", + 3852 => x"3d", + 3853 => x"e0", + 3854 => x"de", + 3855 => x"81", + 3856 => x"bc", + 3857 => x"c7", + 3858 => x"98", + 3859 => x"73", + 3860 => x"38", + 3861 => x"12", + 3862 => x"39", + 3863 => x"33", + 3864 => x"70", + 3865 => x"55", + 3866 => x"2e", + 3867 => x"7f", + 3868 => x"54", + 3869 => x"81", + 3870 => x"94", + 3871 => x"39", + 3872 => x"08", + 3873 => x"81", + 3874 => x"85", + 3875 => x"de", + 3876 => x"3d", + 3877 => x"3d", + 3878 => x"5b", + 3879 => x"34", + 3880 => x"3d", + 3881 => x"52", + 3882 => x"e8", + 3883 => x"de", + 3884 => x"81", + 3885 => x"82", + 3886 => x"43", + 3887 => x"11", + 3888 => x"58", + 3889 => x"80", + 3890 => x"38", + 3891 => x"3d", + 3892 => x"d5", + 3893 => x"de", + 3894 => x"81", + 3895 => x"82", + 3896 => x"52", + 3897 => x"c8", + 3898 => x"c0", + 3899 => x"de", + 3900 => x"c1", + 3901 => x"7b", + 3902 => x"3f", + 3903 => x"08", + 3904 => x"74", + 3905 => x"3f", + 3906 => x"08", + 3907 => x"c0", + 3908 => x"38", + 3909 => x"51", + 3910 => x"81", + 3911 => x"57", + 3912 => x"08", + 3913 => x"52", + 3914 => x"f2", + 3915 => x"de", + 3916 => x"a6", + 3917 => x"74", + 3918 => x"3f", + 3919 => x"08", + 3920 => x"c0", + 3921 => x"cc", + 3922 => x"2e", + 3923 => x"86", + 3924 => x"81", + 3925 => x"81", + 3926 => x"3d", + 3927 => x"52", + 3928 => x"c9", + 3929 => x"3d", + 3930 => x"11", + 3931 => x"5a", + 3932 => x"2e", + 3933 => x"b9", + 3934 => x"16", + 3935 => x"33", + 3936 => x"73", + 3937 => x"16", + 3938 => x"26", + 3939 => x"75", + 3940 => x"38", + 3941 => x"05", + 3942 => x"6f", + 3943 => x"ff", + 3944 => x"55", + 3945 => x"74", + 3946 => x"38", + 3947 => x"11", + 3948 => x"74", + 3949 => x"39", + 3950 => x"09", + 3951 => x"38", + 3952 => x"11", + 3953 => x"74", + 3954 => x"81", + 3955 => x"70", + 3956 => x"cd", + 3957 => x"08", + 3958 => x"5c", + 3959 => x"73", + 3960 => x"38", + 3961 => x"1a", + 3962 => x"55", + 3963 => x"38", + 3964 => x"73", + 3965 => x"38", + 3966 => x"76", + 3967 => x"74", + 3968 => x"33", + 3969 => x"05", + 3970 => x"15", + 3971 => x"ba", + 3972 => x"05", + 3973 => x"ff", + 3974 => x"06", + 3975 => x"57", + 3976 => x"18", + 3977 => x"54", + 3978 => x"70", + 3979 => x"34", + 3980 => x"ee", + 3981 => x"34", + 3982 => x"c0", + 3983 => x"0d", + 3984 => x"0d", + 3985 => x"3d", + 3986 => x"71", + 3987 => x"ec", + 3988 => x"de", + 3989 => x"81", + 3990 => x"82", + 3991 => x"15", + 3992 => x"82", + 3993 => x"15", + 3994 => x"76", + 3995 => x"90", + 3996 => x"81", + 3997 => x"06", + 3998 => x"72", + 3999 => x"56", + 4000 => x"54", + 4001 => x"17", + 4002 => x"78", + 4003 => x"38", + 4004 => x"22", + 4005 => x"59", + 4006 => x"78", + 4007 => x"76", + 4008 => x"51", + 4009 => x"3f", + 4010 => x"08", + 4011 => x"54", + 4012 => x"53", + 4013 => x"3f", + 4014 => x"08", + 4015 => x"38", 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x"15", + 4075 => x"90", + 4076 => x"16", + 4077 => x"33", + 4078 => x"53", + 4079 => x"34", + 4080 => x"06", + 4081 => x"2e", + 4082 => x"9c", + 4083 => x"85", + 4084 => x"16", + 4085 => x"72", + 4086 => x"0c", + 4087 => x"04", + 4088 => x"79", + 4089 => x"75", + 4090 => x"8a", + 4091 => x"89", + 4092 => x"52", + 4093 => x"05", + 4094 => x"3f", + 4095 => x"08", + 4096 => x"c0", + 4097 => x"38", + 4098 => x"7a", + 4099 => x"d8", + 4100 => x"de", + 4101 => x"81", + 4102 => x"80", + 4103 => x"16", + 4104 => x"2b", + 4105 => x"74", + 4106 => x"86", + 4107 => x"84", + 4108 => x"06", + 4109 => x"73", + 4110 => x"38", + 4111 => x"52", + 4112 => x"da", + 4113 => x"c0", + 4114 => x"0c", + 4115 => x"14", + 4116 => x"23", + 4117 => x"51", + 4118 => x"81", + 4119 => x"55", + 4120 => x"09", + 4121 => x"38", + 4122 => x"39", + 4123 => x"84", + 4124 => x"0c", + 4125 => x"81", + 4126 => x"89", + 4127 => x"fc", + 4128 => x"87", + 4129 => x"53", + 4130 => x"e7", + 4131 => x"de", + 4132 => x"38", + 4133 => x"08", + 4134 => x"3d", + 4135 => x"3d", + 4136 => x"89", + 4137 => x"54", + 4138 => x"54", + 4139 => x"81", + 4140 => x"53", + 4141 => x"08", + 4142 => x"74", + 4143 => x"de", + 4144 => x"73", + 4145 => x"3f", + 4146 => x"08", + 4147 => x"39", + 4148 => x"08", + 4149 => x"d3", + 4150 => x"de", + 4151 => x"81", + 4152 => x"84", + 4153 => x"06", + 4154 => x"53", + 4155 => x"de", + 4156 => x"38", + 4157 => x"51", + 4158 => x"72", + 4159 => x"cf", + 4160 => x"de", + 4161 => x"32", + 4162 => x"72", + 4163 => x"70", + 4164 => x"08", + 4165 => x"54", + 4166 => x"de", + 4167 => x"3d", + 4168 => x"3d", + 4169 => x"80", + 4170 => x"70", + 4171 => x"52", + 4172 => x"3f", + 4173 => x"08", + 4174 => x"c0", + 4175 => x"64", + 4176 => x"d6", + 4177 => x"de", + 4178 => x"81", + 4179 => x"a0", + 4180 => x"cb", + 4181 => x"98", + 4182 => x"73", + 4183 => x"38", + 4184 => x"39", + 4185 => x"88", + 4186 => x"75", + 4187 => x"3f", + 4188 => x"c0", + 4189 => x"0d", + 4190 => x"0d", + 4191 => x"5c", + 4192 => x"3d", + 4193 => x"93", + 4194 => x"d6", + 4195 => x"c0", + 4196 => x"de", + 4197 => x"80", + 4198 => x"0c", + 4199 => x"11", + 4200 => x"90", + 4201 => x"56", + 4202 => x"74", + 4203 => x"75", + 4204 => x"e4", + 4205 => x"81", + 4206 => x"5b", + 4207 => x"81", + 4208 => x"75", + 4209 => x"73", + 4210 => x"81", + 4211 => x"82", + 4212 => x"76", + 4213 => x"f0", + 4214 => x"f4", + 4215 => x"c0", + 4216 => x"d1", + 4217 => x"c0", + 4218 => x"ce", + 4219 => x"c0", + 4220 => x"81", + 4221 => x"07", + 4222 => x"05", + 4223 => x"53", + 4224 => x"98", + 4225 => x"26", + 4226 => x"f9", + 4227 => x"08", + 4228 => x"08", + 4229 => x"98", + 4230 => x"81", + 4231 => x"58", + 4232 => x"3f", + 4233 => x"08", + 4234 => x"c0", + 4235 => x"38", + 4236 => x"77", + 4237 => x"5d", + 4238 => x"74", + 4239 => x"81", + 4240 => x"b4", + 4241 => x"bb", + 4242 => x"de", + 4243 => x"ff", + 4244 => x"30", + 4245 => x"1b", + 4246 => x"5b", + 4247 => x"39", + 4248 => x"ff", + 4249 => x"81", + 4250 => x"f0", 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x"90", + 4310 => x"80", + 4311 => x"75", + 4312 => x"75", + 4313 => x"de", + 4314 => x"3d", + 4315 => x"3d", + 4316 => x"a0", + 4317 => x"05", + 4318 => x"51", + 4319 => x"81", + 4320 => x"55", + 4321 => x"08", + 4322 => x"78", + 4323 => x"08", + 4324 => x"70", + 4325 => x"ae", + 4326 => x"c0", + 4327 => x"de", + 4328 => x"db", + 4329 => x"fb", + 4330 => x"85", + 4331 => x"06", + 4332 => x"86", + 4333 => x"c7", + 4334 => x"2b", + 4335 => x"24", + 4336 => x"02", + 4337 => x"33", + 4338 => x"58", + 4339 => x"76", + 4340 => x"6b", + 4341 => x"cc", + 4342 => x"de", + 4343 => x"84", + 4344 => x"06", + 4345 => x"73", + 4346 => x"d4", + 4347 => x"81", + 4348 => x"94", + 4349 => x"81", + 4350 => x"5a", + 4351 => x"08", + 4352 => x"8a", + 4353 => x"54", + 4354 => x"81", + 4355 => x"55", + 4356 => x"08", + 4357 => x"81", + 4358 => x"52", + 4359 => x"e5", + 4360 => x"c0", + 4361 => x"de", + 4362 => x"38", + 4363 => x"cf", + 4364 => x"c0", + 4365 => x"88", + 4366 => x"c0", + 4367 => x"38", + 4368 => x"c2", + 4369 => x"c0", + 4370 => x"c0", + 4371 => x"81", + 4372 => x"07", + 4373 => x"55", + 4374 => x"2e", + 4375 => x"80", + 4376 => x"80", + 4377 => x"77", + 4378 => x"3f", + 4379 => x"08", + 4380 => x"38", + 4381 => x"ba", + 4382 => x"de", + 4383 => x"74", + 4384 => x"0c", + 4385 => x"04", + 4386 => x"82", + 4387 => x"c0", + 4388 => x"3d", + 4389 => x"3f", + 4390 => x"08", + 4391 => x"c0", + 4392 => x"38", + 4393 => x"52", + 4394 => x"52", + 4395 => x"3f", + 4396 => x"08", + 4397 => x"c0", + 4398 => x"88", + 4399 => x"39", + 4400 => x"08", + 4401 => x"81", + 4402 => x"38", + 4403 => x"05", + 4404 => x"2a", + 4405 => x"55", + 4406 => x"81", + 4407 => x"5a", + 4408 => x"3d", + 4409 => x"c1", + 4410 => x"de", + 4411 => x"55", + 4412 => x"c0", + 4413 => x"87", + 4414 => x"c0", + 4415 => x"09", + 4416 => x"38", + 4417 => x"de", + 4418 => x"2e", + 4419 => x"86", + 4420 => x"81", + 4421 => x"81", + 4422 => x"de", + 4423 => x"78", + 4424 => x"3f", + 4425 => x"08", + 4426 => x"c0", + 4427 => x"38", + 4428 => x"52", + 4429 => x"ff", + 4430 => x"78", + 4431 => x"b4", + 4432 => x"54", + 4433 => x"15", + 4434 => x"b2", + 4435 => x"ca", + 4436 => x"b6", + 4437 => x"53", + 4438 => x"53", + 4439 => x"3f", + 4440 => x"b4", + 4441 => x"d4", + 4442 => x"b6", + 4443 => x"54", + 4444 => x"d5", + 4445 => x"53", + 4446 => x"11", + 4447 => x"d7", + 4448 => x"81", + 4449 => x"34", + 4450 => x"a4", + 4451 => x"c0", + 4452 => x"de", + 4453 => x"38", + 4454 => x"0a", + 4455 => x"05", + 4456 => x"d0", + 4457 => x"64", + 4458 => x"c9", + 4459 => x"54", + 4460 => x"15", + 4461 => x"81", + 4462 => x"34", + 4463 => x"b8", + 4464 => x"de", + 4465 => x"8b", + 4466 => x"75", + 4467 => x"ff", + 4468 => x"73", + 4469 => x"0c", + 4470 => x"04", + 4471 => x"a9", + 4472 => x"51", + 4473 => x"82", + 4474 => x"ff", + 4475 => x"a9", + 4476 => x"ee", + 4477 => x"c0", + 4478 => x"de", + 4479 => x"d3", + 4480 => x"a9", + 4481 => x"9d", + 4482 => x"58", + 4483 => x"81", + 4484 => x"55", + 4485 => x"08", + 4486 => x"02", + 4487 => x"33", + 4488 => x"54", + 4489 => x"82", + 4490 => x"53", + 4491 => x"52", + 4492 => x"88", + 4493 => x"b4", + 4494 => x"53", + 4495 => x"3d", + 4496 => x"ff", + 4497 => x"aa", + 4498 => x"73", + 4499 => x"3f", + 4500 => x"08", + 4501 => x"c0", + 4502 => x"63", + 4503 => x"81", + 4504 => x"65", + 4505 => x"2e", + 4506 => x"55", + 4507 => x"81", + 4508 => x"84", + 4509 => x"06", + 4510 => x"73", + 4511 => x"3f", + 4512 => x"08", + 4513 => x"c0", + 4514 => x"38", + 4515 => x"53", + 4516 => x"95", + 4517 => x"16", + 4518 => x"87", + 4519 => x"05", + 4520 => x"34", + 4521 => x"70", + 4522 => x"81", + 4523 => x"55", + 4524 => x"74", + 4525 => x"73", + 4526 => x"78", + 4527 => x"83", + 4528 => x"16", + 4529 => x"2a", + 4530 => x"51", + 4531 => x"80", + 4532 => x"38", + 4533 => x"80", + 4534 => x"52", + 4535 => x"be", + 4536 => x"c0", + 4537 => x"51", + 4538 => x"3f", + 4539 => x"de", + 4540 => x"2e", + 4541 => x"81", + 4542 => x"52", + 4543 => x"b5", + 4544 => x"de", + 4545 => x"80", + 4546 => x"58", + 4547 => x"c0", + 4548 => x"38", + 4549 => x"54", + 4550 => x"09", + 4551 => x"38", + 4552 => x"52", + 4553 => x"af", + 4554 => x"81", + 4555 => x"34", + 4556 => x"de", + 4557 => x"38", + 4558 => x"ca", + 4559 => x"c0", + 4560 => x"de", + 4561 => x"38", + 4562 => x"b5", + 4563 => x"de", + 4564 => x"74", + 4565 => x"0c", + 4566 => x"04", + 4567 => x"02", + 4568 => x"33", + 4569 => x"80", + 4570 => x"57", + 4571 => x"95", + 4572 => x"52", + 4573 => x"d2", + 4574 => x"de", + 4575 => x"81", + 4576 => x"80", + 4577 => x"5a", + 4578 => x"3d", + 4579 => x"c9", + 4580 => x"de", + 4581 => x"81", + 4582 => x"b8", + 4583 => x"cf", + 4584 => x"a0", + 4585 => x"55", + 4586 => x"75", + 4587 => x"71", + 4588 => x"33", + 4589 => x"74", + 4590 => x"57", + 4591 => x"8b", + 4592 => x"54", + 4593 => x"15", + 4594 => x"ff", + 4595 => x"81", + 4596 => x"55", + 4597 => x"c0", + 4598 => x"0d", + 4599 => x"0d", + 4600 => x"53", + 4601 => x"05", + 4602 => x"51", + 4603 => x"81", + 4604 => x"55", + 4605 => x"08", + 4606 => x"76", + 4607 => x"93", + 4608 => x"51", + 4609 => x"81", + 4610 => x"55", + 4611 => x"08", + 4612 => x"80", + 4613 => x"81", + 4614 => x"86", + 4615 => x"38", + 4616 => x"86", + 4617 => x"90", + 4618 => x"54", + 4619 => x"ff", + 4620 => x"76", + 4621 => x"83", + 4622 => x"51", + 4623 => x"3f", + 4624 => x"08", + 4625 => x"de", + 4626 => x"3d", + 4627 => x"3d", + 4628 => x"5c", + 4629 => x"98", + 4630 => x"52", + 4631 => x"d1", + 4632 => x"de", + 4633 => x"de", + 4634 => x"70", + 4635 => x"08", + 4636 => x"51", + 4637 => x"80", + 4638 => x"38", + 4639 => x"06", + 4640 => x"80", + 4641 => x"38", + 4642 => x"5f", + 4643 => x"3d", + 4644 => x"ff", + 4645 => x"81", + 4646 => x"57", + 4647 => x"08", + 4648 => x"74", + 4649 => x"c3", + 4650 => x"de", + 4651 => x"81", + 4652 => x"bf", + 4653 => x"c0", + 4654 => x"c0", + 4655 => x"59", + 4656 => x"81", + 4657 => x"56", + 4658 => x"33", + 4659 => x"16", + 4660 => x"27", + 4661 => x"56", + 4662 => x"80", + 4663 => x"80", + 4664 => x"ff", + 4665 => x"70", + 4666 => x"56", + 4667 => x"e8", + 4668 => x"76", + 4669 => x"81", + 4670 => x"80", + 4671 => x"57", + 4672 => x"78", + 4673 => x"51", + 4674 => x"2e", + 4675 => x"73", + 4676 => x"38", + 4677 => x"08", + 4678 => x"b1", + 4679 => x"de", + 4680 => x"81", + 4681 => x"a7", + 4682 => x"33", + 4683 => x"c3", + 4684 => x"2e", + 4685 => x"e4", + 4686 => x"2e", + 4687 => x"56", + 4688 => x"05", + 4689 => x"e3", + 4690 => x"c0", + 4691 => x"76", + 4692 => x"0c", + 4693 => x"04", + 4694 => x"82", + 4695 => x"ff", + 4696 => x"9d", + 4697 => x"fa", + 4698 => x"c0", + 4699 => x"c0", + 4700 => x"81", + 4701 => x"83", + 4702 => x"53", + 4703 => x"3d", + 4704 => x"ff", + 4705 => x"73", + 4706 => x"70", + 4707 => x"52", + 4708 => x"9f", + 4709 => x"bc", + 4710 => x"74", + 4711 => x"6d", + 4712 => x"70", + 4713 => x"af", + 4714 => x"de", + 4715 => x"2e", + 4716 => x"70", + 4717 => x"57", + 4718 => x"fd", + 4719 => x"c0", + 4720 => x"8d", + 4721 => x"2b", + 4722 => x"81", + 4723 => x"86", + 4724 => x"c0", + 4725 => x"9f", + 4726 => x"ff", + 4727 => x"54", + 4728 => x"8a", + 4729 => x"70", + 4730 => x"06", + 4731 => x"ff", + 4732 => x"38", + 4733 => x"15", + 4734 => x"80", + 4735 => x"74", + 4736 => x"b4", + 4737 => x"89", + 4738 => x"c0", + 4739 => x"81", + 4740 => x"88", + 4741 => x"26", + 4742 => x"39", + 4743 => x"86", + 4744 => x"81", + 4745 => x"ff", + 4746 => x"38", + 4747 => x"54", + 4748 => x"81", + 4749 => x"81", + 4750 => x"78", + 4751 => x"5a", + 4752 => x"6d", + 4753 => x"81", + 4754 => x"57", + 4755 => x"9f", + 4756 => x"38", + 4757 => x"54", + 4758 => x"81", + 4759 => x"b1", + 4760 => x"2e", + 4761 => x"a7", + 4762 => x"15", + 4763 => x"54", + 4764 => x"09", + 4765 => x"38", + 4766 => x"76", + 4767 => x"41", + 4768 => x"52", + 4769 => x"52", + 4770 => x"b3", + 4771 => x"c0", + 4772 => x"de", + 4773 => x"f7", + 4774 => x"74", + 4775 => x"e5", + 4776 => x"c0", + 4777 => x"de", + 4778 => x"38", + 4779 => x"38", + 4780 => x"74", + 4781 => x"39", + 4782 => x"08", + 4783 => x"81", + 4784 => x"38", + 4785 => x"74", + 4786 => x"38", + 4787 => x"51", + 4788 => x"3f", + 4789 => x"08", + 4790 => x"c0", + 4791 => x"a0", + 4792 => x"c0", + 4793 => x"51", + 4794 => x"3f", + 4795 => x"0b", + 4796 => x"8b", + 4797 => x"67", + 4798 => x"a7", + 4799 => x"81", + 4800 => x"34", + 4801 => x"ad", + 4802 => x"de", + 4803 => x"73", + 4804 => x"de", + 4805 => x"3d", + 4806 => x"3d", + 4807 => x"02", + 4808 => x"cb", + 4809 => x"3d", + 4810 => x"72", + 4811 => x"5a", + 4812 => x"81", + 4813 => x"58", + 4814 => x"08", + 4815 => x"91", + 4816 => x"77", + 4817 => x"7c", + 4818 => x"38", + 4819 => x"59", + 4820 => x"90", + 4821 => x"81", + 4822 => x"06", + 4823 => x"73", + 4824 => x"54", + 4825 => x"82", + 4826 => x"39", + 4827 => x"8b", + 4828 => x"11", + 4829 => x"2b", + 4830 => x"54", + 4831 => x"fe", + 4832 => x"ff", + 4833 => x"70", + 4834 => x"07", + 4835 => x"de", + 4836 => x"8c", + 4837 => x"40", + 4838 => x"55", + 4839 => x"88", + 4840 => x"08", + 4841 => x"38", + 4842 => x"77", + 4843 => x"56", + 4844 => x"51", + 4845 => x"3f", + 4846 => x"55", + 4847 => x"08", + 4848 => x"38", + 4849 => x"de", + 4850 => x"2e", + 4851 => x"81", + 4852 => x"ff", + 4853 => x"38", + 4854 => x"08", + 4855 => x"16", + 4856 => x"2e", + 4857 => x"87", + 4858 => x"74", + 4859 => x"74", + 4860 => x"81", + 4861 => x"38", + 4862 => x"ff", + 4863 => x"2e", + 4864 => x"7b", + 4865 => x"80", + 4866 => x"81", + 4867 => x"81", + 4868 => x"06", + 4869 => x"56", + 4870 => x"52", + 4871 => x"af", + 4872 => x"de", + 4873 => x"81", + 4874 => x"80", + 4875 => x"81", + 4876 => x"56", + 4877 => x"d3", + 4878 => x"ff", + 4879 => x"7c", + 4880 => x"55", + 4881 => x"b3", + 4882 => x"1b", + 4883 => x"1b", + 4884 => x"33", + 4885 => x"54", + 4886 => x"34", + 4887 => x"fe", + 4888 => x"08", + 4889 => x"74", + 4890 => x"75", + 4891 => x"16", + 4892 => x"33", + 4893 => x"73", + 4894 => x"77", + 4895 => x"de", + 4896 => x"3d", + 4897 => x"3d", + 4898 => x"02", + 4899 => x"eb", + 4900 => x"3d", + 4901 => x"59", + 4902 => x"8b", + 4903 => x"81", + 4904 => x"24", + 4905 => x"81", + 4906 => x"84", + 4907 => x"dc", + 4908 => x"51", + 4909 => x"2e", + 4910 => x"75", + 4911 => x"c0", + 4912 => x"06", + 4913 => x"7e", + 4914 => x"d0", + 4915 => x"c0", + 4916 => x"06", + 4917 => x"56", + 4918 => x"74", + 4919 => x"76", + 4920 => x"81", + 4921 => x"8a", + 4922 => x"b2", + 4923 => x"fc", + 4924 => x"52", + 4925 => x"a4", + 4926 => x"de", + 4927 => x"38", + 4928 => x"80", + 4929 => x"74", + 4930 => x"26", + 4931 => x"15", + 4932 => x"74", + 4933 => x"38", + 4934 => x"80", + 4935 => x"84", + 4936 => x"92", + 4937 => x"80", + 4938 => x"38", + 4939 => x"06", + 4940 => x"2e", + 4941 => x"56", + 4942 => x"78", + 4943 => x"89", + 4944 => x"2b", + 4945 => x"43", + 4946 => x"38", + 4947 => x"30", + 4948 => x"77", + 4949 => x"91", + 4950 => x"c2", + 4951 => x"f8", + 4952 => x"52", + 4953 => x"a4", + 4954 => x"56", + 4955 => x"08", + 4956 => x"77", + 4957 => x"77", + 4958 => x"c0", + 4959 => x"45", + 4960 => x"bf", + 4961 => x"8e", + 4962 => x"26", + 4963 => x"74", + 4964 => x"48", + 4965 => x"75", + 4966 => x"38", + 4967 => x"81", + 4968 => x"fa", + 4969 => x"2a", + 4970 => x"56", + 4971 => x"2e", + 4972 => x"87", + 4973 => x"82", + 4974 => x"38", + 4975 => x"55", + 4976 => x"83", + 4977 => x"81", + 4978 => x"56", + 4979 => x"80", + 4980 => x"38", + 4981 => x"83", + 4982 => x"06", + 4983 => x"78", + 4984 => x"91", + 4985 => x"0b", + 4986 => x"22", + 4987 => x"80", + 4988 => x"74", + 4989 => x"38", + 4990 => x"56", + 4991 => x"17", + 4992 => x"57", + 4993 => x"2e", + 4994 => x"75", + 4995 => x"79", + 4996 => x"fe", + 4997 => x"81", + 4998 => x"84", + 4999 => x"05", + 5000 => x"5e", + 5001 => x"80", + 5002 => x"c0", + 5003 => x"8a", + 5004 => x"fd", + 5005 => x"75", + 5006 => x"38", + 5007 => x"78", + 5008 => x"8c", + 5009 => x"0b", + 5010 => x"22", + 5011 => x"80", + 5012 => x"74", + 5013 => x"38", + 5014 => x"56", + 5015 => x"17", + 5016 => x"57", + 5017 => x"2e", + 5018 => x"75", + 5019 => x"79", + 5020 => x"fe", + 5021 => x"81", + 5022 => x"10", + 5023 => x"81", + 5024 => x"9f", + 5025 => x"38", + 5026 => x"de", + 5027 => x"81", + 5028 => x"05", + 5029 => x"2a", + 5030 => x"56", + 5031 => x"17", + 5032 => x"81", + 5033 => x"60", + 5034 => x"65", + 5035 => x"12", + 5036 => x"30", + 5037 => x"74", + 5038 => x"59", + 5039 => x"7d", + 5040 => x"81", + 5041 => x"76", + 5042 => x"41", + 5043 => x"76", + 5044 => x"90", + 5045 => x"62", + 5046 => x"51", + 5047 => x"26", + 5048 => x"75", + 5049 => x"31", + 5050 => x"65", + 5051 => x"fe", + 5052 => x"81", + 5053 => x"58", + 5054 => x"09", + 5055 => x"38", + 5056 => x"08", + 5057 => x"26", + 5058 => x"78", + 5059 => x"79", + 5060 => x"78", + 5061 => x"86", + 5062 => x"82", + 5063 => x"06", + 5064 => x"83", + 5065 => x"81", + 5066 => x"27", + 5067 => x"8f", + 5068 => x"55", + 5069 => x"26", + 5070 => x"59", + 5071 => x"62", + 5072 => x"74", + 5073 => x"38", + 5074 => x"88", + 5075 => x"c0", + 5076 => x"26", + 5077 => x"86", + 5078 => x"1a", + 5079 => x"79", + 5080 => x"38", + 5081 => x"80", + 5082 => x"2e", + 5083 => x"83", + 5084 => x"9f", + 5085 => x"8b", + 5086 => x"06", + 5087 => x"74", + 5088 => x"84", + 5089 => x"52", + 5090 => x"a2", + 5091 => x"53", + 5092 => x"52", + 5093 => x"a2", + 5094 => x"80", + 5095 => x"51", + 5096 => x"3f", + 5097 => x"34", + 5098 => x"ff", + 5099 => x"1b", + 5100 => x"a2", + 5101 => x"90", + 5102 => x"83", + 5103 => x"70", + 5104 => x"80", + 5105 => x"55", + 5106 => x"ff", + 5107 => x"66", + 5108 => x"ff", + 5109 => x"38", + 5110 => x"ff", + 5111 => x"1b", + 5112 => x"f2", + 5113 => x"74", + 5114 => x"51", + 5115 => x"3f", + 5116 => x"1c", + 5117 => x"98", + 5118 => x"a0", + 5119 => x"ff", + 5120 => x"51", + 5121 => x"3f", + 5122 => x"1b", + 5123 => x"e4", + 5124 => x"2e", + 5125 => x"80", + 5126 => x"88", + 5127 => x"80", + 5128 => x"ff", + 5129 => x"7c", + 5130 => x"51", + 5131 => x"3f", + 5132 => x"1b", + 5133 => x"bc", + 5134 => x"b0", + 5135 => x"a0", + 5136 => x"52", + 5137 => x"ff", + 5138 => x"ff", + 5139 => x"c0", + 5140 => x"0b", + 5141 => x"34", + 5142 => x"cc", + 5143 => x"c7", + 5144 => x"39", + 5145 => x"0a", + 5146 => x"51", + 5147 => x"3f", + 5148 => x"ff", + 5149 => x"1b", + 5150 => x"da", + 5151 => x"0b", + 5152 => x"a9", + 5153 => x"34", + 5154 => x"cd", + 5155 => x"1b", + 5156 => x"8f", + 5157 => x"d5", + 5158 => x"1b", + 5159 => x"ff", + 5160 => x"81", + 5161 => x"7a", + 5162 => x"ff", + 5163 => x"81", + 5164 => x"c0", + 5165 => x"38", + 5166 => x"09", + 5167 => x"ee", + 5168 => x"60", + 5169 => x"7a", + 5170 => x"ff", + 5171 => x"84", + 5172 => x"52", + 5173 => x"9f", + 5174 => x"8b", + 5175 => x"52", + 5176 => x"9f", + 5177 => x"8a", + 5178 => x"52", + 5179 => x"51", + 5180 => x"3f", + 5181 => x"83", + 5182 => x"ff", + 5183 => x"82", + 5184 => x"1b", + 5185 => x"ec", + 5186 => x"d5", + 5187 => x"ff", + 5188 => x"75", + 5189 => x"05", + 5190 => x"7e", + 5191 => x"e5", + 5192 => x"60", + 5193 => x"52", + 5194 => x"9a", + 5195 => x"53", + 5196 => x"51", + 5197 => x"3f", + 5198 => x"58", + 5199 => x"09", + 5200 => x"38", + 5201 => x"51", + 5202 => x"3f", + 5203 => x"1b", + 5204 => x"a0", + 5205 => x"52", + 5206 => x"91", + 5207 => x"ff", + 5208 => x"81", + 5209 => x"f8", + 5210 => x"7a", + 5211 => x"84", + 5212 => x"61", + 5213 => x"26", + 5214 => x"57", + 5215 => x"53", + 5216 => x"51", + 5217 => x"3f", + 5218 => x"08", + 5219 => x"84", + 5220 => x"de", + 5221 => x"7a", + 5222 => x"aa", + 5223 => x"75", + 5224 => x"56", + 5225 => x"81", + 5226 => x"80", + 5227 => x"38", + 5228 => x"83", + 5229 => x"63", + 5230 => x"74", + 5231 => x"38", + 5232 => x"54", + 5233 => x"52", + 5234 => x"99", + 5235 => x"de", + 5236 => x"c1", + 5237 => x"75", + 5238 => x"56", + 5239 => x"8c", + 5240 => x"2e", + 5241 => x"56", + 5242 => x"ff", + 5243 => x"84", + 5244 => x"2e", + 5245 => x"56", + 5246 => x"58", + 5247 => x"38", + 5248 => x"77", + 5249 => x"ff", + 5250 => x"82", + 5251 => x"78", + 5252 => x"c2", + 5253 => x"1b", + 5254 => x"34", + 5255 => x"16", + 5256 => x"82", + 5257 => x"83", + 5258 => x"84", + 5259 => x"67", + 5260 => x"fd", + 5261 => x"51", + 5262 => x"3f", + 5263 => x"16", + 5264 => x"c0", + 5265 => x"bf", + 5266 => x"86", + 5267 => x"de", + 5268 => x"16", + 5269 => x"83", + 5270 => x"ff", + 5271 => x"66", + 5272 => x"1b", + 5273 => x"8c", + 5274 => x"77", + 5275 => x"7e", + 5276 => x"91", + 5277 => x"81", + 5278 => x"a2", + 5279 => x"80", + 5280 => x"ff", + 5281 => x"81", + 5282 => x"c0", + 5283 => x"89", + 5284 => x"8a", + 5285 => x"86", + 5286 => x"c0", + 5287 => x"81", + 5288 => x"99", + 5289 => x"f5", + 5290 => x"60", + 5291 => x"79", + 5292 => x"5a", + 5293 => x"78", + 5294 => x"8d", + 5295 => x"55", + 5296 => x"fc", + 5297 => x"51", + 5298 => x"7a", + 5299 => x"81", + 5300 => x"8c", + 5301 => x"74", + 5302 => x"38", + 5303 => x"81", + 5304 => x"81", + 5305 => x"8a", + 5306 => x"06", + 5307 => x"76", + 5308 => x"76", + 5309 => x"55", + 5310 => x"c0", + 5311 => x"0d", + 5312 => x"0d", + 5313 => x"93", + 5314 => x"38", + 5315 => x"81", + 5316 => x"52", + 5317 => x"81", + 5318 => x"81", + 5319 => x"cf", + 5320 => x"f9", + 5321 => x"90", + 5322 => x"39", + 5323 => x"51", + 5324 => x"81", + 5325 => x"80", + 5326 => x"d0", + 5327 => x"dd", + 5328 => x"d8", + 5329 => x"39", + 5330 => x"51", + 5331 => x"81", + 5332 => x"80", + 5333 => x"d1", + 5334 => x"c1", + 5335 => x"b0", + 5336 => x"81", + 5337 => x"b5", + 5338 => x"e0", + 5339 => x"81", + 5340 => x"a9", + 5341 => x"a0", + 5342 => x"81", + 5343 => x"9d", + 5344 => x"d4", + 5345 => x"81", + 5346 => x"91", + 5347 => x"84", + 5348 => x"81", + 5349 => x"85", + 5350 => x"a8", + 5351 => x"a1", + 5352 => x"0d", + 5353 => x"0d", + 5354 => x"56", + 5355 => x"26", + 5356 => x"52", + 5357 => x"29", + 5358 => x"87", + 5359 => x"51", + 5360 => x"3f", + 5361 => x"08", + 5362 => x"fe", + 5363 => x"81", + 5364 => x"54", + 5365 => x"52", + 5366 => x"51", + 5367 => x"3f", + 5368 => x"04", + 5369 => x"7d", + 5370 => x"8c", + 5371 => x"05", + 5372 => x"15", + 5373 => x"5a", + 5374 => x"5c", + 5375 => x"d3", + 5376 => x"8c", + 5377 => x"d3", + 5378 => x"86", + 5379 => x"55", + 5380 => x"80", + 5381 => x"90", + 5382 => x"79", + 5383 => x"38", + 5384 => x"74", + 5385 => x"78", + 5386 => x"72", + 5387 => x"d3", + 5388 => x"8b", + 5389 => x"39", + 5390 => x"51", + 5391 => x"3f", + 5392 => x"80", + 5393 => x"16", + 5394 => x"27", + 5395 => x"08", + 5396 => x"dc", + 5397 => x"cd", + 5398 => x"81", + 5399 => x"ff", + 5400 => x"84", + 5401 => x"39", + 5402 => x"72", + 5403 => x"38", + 5404 => x"81", + 5405 => x"ff", + 5406 => x"89", + 5407 => x"84", + 5408 => x"bd", + 5409 => x"55", + 5410 => x"f6", + 5411 => x"80", + 5412 => x"88", + 5413 => x"a9", + 5414 => x"74", + 5415 => x"38", + 5416 => x"33", + 5417 => x"52", + 5418 => x"74", + 5419 => x"72", + 5420 => x"38", + 5421 => x"26", + 5422 => x"51", + 5423 => x"51", + 5424 => x"3f", + 5425 => x"d3", + 5426 => x"8c", + 5427 => x"f1", + 5428 => x"77", + 5429 => x"fe", + 5430 => x"81", + 5431 => x"98", + 5432 => x"2c", + 5433 => x"a0", + 5434 => x"06", + 5435 => x"f9", + 5436 => x"de", + 5437 => x"2b", + 5438 => x"70", + 5439 => x"30", + 5440 => x"9f", + 5441 => x"56", + 5442 => x"9b", + 5443 => x"72", + 5444 => x"9b", + 5445 => x"06", + 5446 => x"53", + 5447 => x"1c", + 5448 => x"26", + 5449 => x"ff", + 5450 => x"de", + 5451 => x"3d", + 5452 => x"3d", + 5453 => x"84", + 5454 => x"05", + 5455 => x"30", + 5456 => x"80", + 5457 => x"ff", + 5458 => x"51", + 5459 => x"5b", + 5460 => x"74", + 5461 => x"81", + 5462 => x"8c", + 5463 => x"57", + 5464 => x"3f", + 5465 => x"08", + 5466 => x"c0", + 5467 => x"81", + 5468 => x"87", + 5469 => x"0c", + 5470 => x"08", + 5471 => x"d4", + 5472 => x"80", + 5473 => x"76", + 5474 => x"3f", + 5475 => x"08", + 5476 => x"c0", + 5477 => x"7a", + 5478 => x"2e", + 5479 => x"19", + 5480 => x"59", + 5481 => x"3d", + 5482 => x"cc", + 5483 => x"30", + 5484 => x"80", + 5485 => x"79", + 5486 => x"38", + 5487 => x"90", + 5488 => x"90", + 5489 => x"98", + 5490 => x"78", + 5491 => x"3f", + 5492 => x"81", + 5493 => x"96", + 5494 => x"f9", + 5495 => x"02", + 5496 => x"05", + 5497 => x"ff", + 5498 => x"7a", + 5499 => x"fe", + 5500 => x"de", + 5501 => x"38", + 5502 => x"88", + 5503 => x"2e", + 5504 => x"39", + 5505 => x"54", + 5506 => x"53", + 5507 => x"51", + 5508 => x"de", + 5509 => x"83", + 5510 => x"76", + 5511 => x"0c", + 5512 => x"04", + 5513 => x"02", + 5514 => x"81", + 5515 => x"81", + 5516 => x"55", + 5517 => x"3f", + 5518 => x"22", + 5519 => x"89", + 5520 => x"ac", + 5521 => x"b8", + 5522 => x"c1", + 5523 => x"d4", + 5524 => x"87", + 5525 => x"80", + 5526 => x"fe", + 5527 => x"86", + 5528 => x"fe", + 5529 => x"c0", + 5530 => x"53", + 5531 => x"3f", + 5532 => x"f2", + 5533 => x"d4", + 5534 => x"f4", + 5535 => x"51", + 5536 => x"3f", + 5537 => x"70", + 5538 => x"52", + 5539 => x"95", + 5540 => x"fe", + 5541 => x"81", + 5542 => x"fe", + 5543 => x"80", + 5544 => x"fe", + 5545 => x"2a", + 5546 => x"51", + 5547 => x"2e", + 5548 => x"51", + 5549 => x"3f", + 5550 => x"51", + 5551 => x"3f", + 5552 => x"f1", + 5553 => x"83", + 5554 => x"06", + 5555 => x"80", + 5556 => x"81", + 5557 => x"ca", + 5558 => x"9c", + 5559 => x"c2", + 5560 => x"fe", + 5561 => x"72", + 5562 => x"81", + 5563 => x"71", + 5564 => x"38", + 5565 => x"f1", + 5566 => x"d5", + 5567 => x"f3", + 5568 => x"51", + 5569 => x"3f", + 5570 => x"70", + 5571 => x"52", + 5572 => x"95", + 5573 => x"fe", + 5574 => x"81", + 5575 => x"fe", + 5576 => x"80", + 5577 => x"fa", + 5578 => x"2a", + 5579 => x"51", + 5580 => x"2e", + 5581 => x"51", + 5582 => x"3f", + 5583 => x"51", + 5584 => x"3f", + 5585 => x"f0", + 5586 => x"87", + 5587 => x"06", + 5588 => x"80", + 5589 => x"81", + 5590 => x"c6", + 5591 => x"ec", + 5592 => x"be", + 5593 => x"fe", + 5594 => x"72", + 5595 => x"81", + 5596 => x"71", + 5597 => x"38", + 5598 => x"f0", + 5599 => x"d6", + 5600 => x"f2", + 5601 => x"51", + 5602 => x"3f", + 5603 => x"3f", + 5604 => x"04", + 5605 => x"78", + 5606 => x"55", + 5607 => x"80", + 5608 => x"38", + 5609 => x"77", + 5610 => x"33", + 5611 => x"39", + 5612 => x"80", + 5613 => x"81", + 5614 => x"57", + 5615 => x"2e", + 5616 => x"53", + 5617 => x"84", + 5618 => x"38", + 5619 => x"06", + 5620 => x"2e", + 5621 => x"88", + 5622 => x"70", + 5623 => x"34", + 5624 => x"90", + 5625 => x"f0", + 5626 => x"53", + 5627 => x"55", + 5628 => x"3f", + 5629 => x"08", + 5630 => x"15", + 5631 => x"81", + 5632 => x"38", + 5633 => x"81", + 5634 => x"53", + 5635 => x"d2", + 5636 => x"72", + 5637 => x"0c", + 5638 => x"04", + 5639 => x"77", + 5640 => x"56", + 5641 => x"75", + 5642 => x"d4", + 5643 => x"ec", + 5644 => x"a7", + 5645 => x"81", + 5646 => x"81", + 5647 => x"ff", + 5648 => x"81", + 5649 => x"30", + 5650 => x"c0", + 5651 => x"25", + 5652 => x"51", + 5653 => x"81", + 5654 => x"81", + 5655 => x"54", + 5656 => x"09", + 5657 => x"38", + 5658 => x"53", + 5659 => x"51", + 5660 => x"81", + 5661 => x"80", + 5662 => x"81", + 5663 => x"51", + 5664 => x"3f", + 5665 => x"f5", + 5666 => x"a6", + 5667 => x"81", + 5668 => x"81", + 5669 => x"54", + 5670 => x"09", + 5671 => x"38", + 5672 => x"51", + 5673 => x"3f", + 5674 => x"de", + 5675 => x"3d", + 5676 => x"3d", + 5677 => x"71", + 5678 => x"0c", + 5679 => x"52", + 5680 => x"88", + 5681 => x"de", + 5682 => x"ff", + 5683 => x"7d", + 5684 => x"06", + 5685 => x"d6", + 5686 => x"3d", + 5687 => x"ff", + 5688 => x"7c", + 5689 => x"81", + 5690 => x"ff", + 5691 => x"81", + 5692 => x"7d", + 5693 => x"81", + 5694 => x"92", + 5695 => x"70", + 5696 => x"d7", + 5697 => x"fc", + 5698 => x"3d", + 5699 => x"80", + 5700 => x"51", + 5701 => x"b7", + 5702 => x"05", + 5703 => x"3f", + 5704 => x"08", + 5705 => x"90", + 5706 => x"78", + 5707 => x"8a", + 5708 => x"80", + 5709 => x"dc", + 5710 => x"2e", + 5711 => x"78", + 5712 => x"38", + 5713 => x"81", + 5714 => x"82", + 5715 => x"78", + 5716 => x"ae", + 5717 => x"39", + 5718 => x"82", + 5719 => x"94", + 5720 => x"38", + 5721 => x"78", + 5722 => x"85", + 5723 => x"80", + 5724 => x"38", + 5725 => x"83", + 5726 => x"bc", + 5727 => x"38", + 5728 => x"78", + 5729 => x"87", + 5730 => x"80", + 5731 => x"bf", + 5732 => x"39", + 5733 => x"2e", + 5734 => x"78", + 5735 => x"a9", + 5736 => x"d0", + 5737 => x"38", + 5738 => x"24", + 5739 => x"80", + 5740 => x"eb", + 5741 => x"39", + 5742 => x"2e", + 5743 => x"78", + 5744 => x"8d", + 5745 => x"ed", + 5746 => x"82", + 5747 => x"38", + 5748 => x"24", + 5749 => x"80", + 5750 => x"ce", + 5751 => x"f9", + 5752 => x"38", + 5753 => x"78", + 5754 => x"8e", + 5755 => x"81", + 5756 => x"ba", + 5757 => x"39", + 5758 => x"f4", + 5759 => x"f8", + 5760 => x"82", + 5761 => x"de", + 5762 => x"38", + 5763 => x"51", + 5764 => x"b7", + 5765 => x"11", + 5766 => x"05", + 5767 => x"fa", + 5768 => x"c0", + 5769 => x"88", + 5770 => x"25", + 5771 => x"43", + 5772 => x"05", + 5773 => x"80", + 5774 => x"51", + 5775 => x"3f", + 5776 => x"08", + 5777 => x"59", + 5778 => x"81", + 5779 => x"fe", + 5780 => x"81", + 5781 => x"39", + 5782 => x"51", + 5783 => x"b7", + 5784 => x"11", + 5785 => x"05", + 5786 => x"ae", + 5787 => x"c0", + 5788 => x"fd", + 5789 => x"53", + 5790 => x"80", + 5791 => x"51", + 5792 => x"3f", + 5793 => x"08", + 5794 => x"c8", + 5795 => x"39", + 5796 => x"f4", + 5797 => x"f8", + 5798 => x"80", + 5799 => x"de", + 5800 => x"2e", + 5801 => x"89", + 5802 => x"38", + 5803 => x"f0", + 5804 => x"f8", + 5805 => x"80", + 5806 => x"de", + 5807 => x"38", + 5808 => x"08", + 5809 => x"81", + 5810 => x"79", + 5811 => x"eb", + 5812 => x"cb", + 5813 => x"79", + 5814 => x"b4", + 5815 => x"f0", + 5816 => x"b3", + 5817 => x"de", + 5818 => x"93", + 5819 => x"a0", + 5820 => x"cd", + 5821 => x"fc", + 5822 => x"3d", + 5823 => x"51", + 5824 => x"3f", + 5825 => x"08", + 5826 => x"f8", + 5827 => x"fe", + 5828 => x"81", + 5829 => x"c0", + 5830 => x"51", + 5831 => x"80", + 5832 => x"3d", + 5833 => x"51", + 5834 => x"3f", + 5835 => x"08", + 5836 => x"f8", + 5837 => x"fe", + 5838 => x"81", + 5839 => x"b8", + 5840 => x"05", + 5841 => x"e5", + 5842 => x"de", + 5843 => x"3d", + 5844 => x"52", + 5845 => x"dd", + 5846 => x"8c", + 5847 => x"f4", + 5848 => x"80", + 5849 => x"c0", + 5850 => x"06", + 5851 => x"79", + 5852 => x"f4", + 5853 => x"de", + 5854 => x"2e", + 5855 => x"81", + 5856 => x"51", + 5857 => x"fa", + 5858 => x"3d", + 5859 => x"53", + 5860 => x"51", + 5861 => x"3f", + 5862 => x"08", + 5863 => x"e2", + 5864 => x"fe", + 5865 => x"fe", + 5866 => x"fe", + 5867 => x"81", + 5868 => x"80", + 5869 => x"38", + 5870 => x"ec", + 5871 => x"f8", + 5872 => x"fe", + 5873 => x"de", + 5874 => x"38", + 5875 => x"08", + 5876 => x"d4", + 5877 => x"e9", + 5878 => x"5c", + 5879 => x"27", + 5880 => x"61", + 5881 => x"70", + 5882 => x"0c", + 5883 => x"f5", + 5884 => x"39", + 5885 => x"f4", + 5886 => x"f8", + 5887 => x"fe", + 5888 => x"de", + 5889 => x"df", + 5890 => x"d4", + 5891 => x"80", + 5892 => x"81", + 5893 => x"44", + 5894 => x"81", + 5895 => x"59", + 5896 => x"88", + 5897 => x"94", + 5898 => x"39", + 5899 => x"33", + 5900 => x"2e", + 5901 => x"db", + 5902 => x"ab", + 5903 => x"d7", + 5904 => x"80", + 5905 => x"81", + 5906 => x"44", + 5907 => x"db", + 5908 => x"78", + 5909 => x"38", + 5910 => x"08", + 5911 => x"81", + 5912 => x"fc", + 5913 => x"b7", + 5914 => x"11", + 5915 => x"05", + 5916 => x"a6", + 5917 => x"c0", + 5918 => x"38", + 5919 => x"33", + 5920 => x"2e", + 5921 => x"db", + 5922 => x"80", + 5923 => x"db", + 5924 => x"78", + 5925 => x"38", + 5926 => x"08", + 5927 => x"81", + 5928 => x"59", + 5929 => x"88", + 5930 => x"a0", + 5931 => x"39", + 5932 => x"33", + 5933 => x"2e", + 5934 => x"db", + 5935 => x"99", + 5936 => x"d2", + 5937 => x"80", + 5938 => x"81", + 5939 => x"43", + 5940 => x"db", + 5941 => x"05", + 5942 => x"fe", + 5943 => x"fe", + 5944 => x"fe", + 5945 => x"81", + 5946 => x"80", + 5947 => x"80", + 5948 => x"79", + 5949 => x"38", + 5950 => x"90", + 5951 => x"78", + 5952 => x"38", + 5953 => x"83", + 5954 => x"81", + 5955 => x"fe", + 5956 => x"a0", + 5957 => x"61", + 5958 => x"63", + 5959 => x"3f", + 5960 => x"51", + 5961 => x"b7", + 5962 => x"11", + 5963 => x"05", + 5964 => x"e6", + 5965 => x"c0", + 5966 => x"f7", + 5967 => x"3d", + 5968 => x"53", + 5969 => x"51", + 5970 => x"3f", + 5971 => x"08", + 5972 => x"38", + 5973 => x"80", + 5974 => x"79", + 5975 => x"05", + 5976 => x"fe", + 5977 => x"fe", + 5978 => x"fe", + 5979 => x"81", + 5980 => x"e0", + 5981 => x"39", + 5982 => x"54", + 5983 => x"80", + 5984 => x"a1", + 5985 => x"52", + 5986 => x"f9", + 5987 => x"45", + 5988 => x"78", + 5989 => x"ea", + 5990 => x"27", + 5991 => x"3d", + 5992 => x"53", + 5993 => x"51", + 5994 => x"3f", + 5995 => x"08", + 5996 => x"38", + 5997 => x"80", + 5998 => x"79", + 5999 => x"05", + 6000 => x"39", + 6001 => x"51", + 6002 => x"3f", + 6003 => x"b7", + 6004 => x"11", + 6005 => x"05", + 6006 => x"b0", + 6007 => x"c0", + 6008 => x"f6", + 6009 => x"3d", + 6010 => x"53", + 6011 => x"51", + 6012 => x"3f", + 6013 => x"08", + 6014 => x"38", + 6015 => x"be", + 6016 => x"70", + 6017 => x"23", + 6018 => x"3d", + 6019 => x"53", + 6020 => x"51", + 6021 => x"3f", + 6022 => x"08", + 6023 => x"e2", + 6024 => x"22", + 6025 => x"d8", + 6026 => x"f7", + 6027 => x"f8", + 6028 => x"fe", + 6029 => x"79", + 6030 => x"59", + 6031 => x"f5", + 6032 => x"9f", + 6033 => x"60", + 6034 => x"d5", + 6035 => x"fe", + 6036 => x"fe", + 6037 => x"fe", + 6038 => x"81", + 6039 => x"80", + 6040 => x"60", + 6041 => x"05", + 6042 => x"82", + 6043 => x"78", + 6044 => x"39", + 6045 => x"51", + 6046 => x"3f", + 6047 => x"b7", + 6048 => x"11", + 6049 => x"05", + 6050 => x"80", + 6051 => x"c0", + 6052 => x"f4", + 6053 => x"3d", + 6054 => x"53", + 6055 => x"51", + 6056 => x"3f", + 6057 => x"08", + 6058 => x"38", + 6059 => x"0c", + 6060 => x"05", + 6061 => x"fe", + 6062 => x"fe", + 6063 => x"fe", + 6064 => x"81", + 6065 => x"e4", + 6066 => x"39", + 6067 => x"54", + 6068 => x"a0", + 6069 => x"cd", + 6070 => x"52", + 6071 => x"f7", + 6072 => x"45", + 6073 => x"78", + 6074 => x"96", + 6075 => x"27", + 6076 => x"3d", + 6077 => x"53", + 6078 => x"51", + 6079 => x"3f", + 6080 => x"08", + 6081 => x"38", + 6082 => x"0c", + 6083 => x"05", + 6084 => x"39", + 6085 => x"51", + 6086 => x"3f", + 6087 => x"b7", + 6088 => x"11", + 6089 => x"05", + 6090 => x"ee", + 6091 => x"c0", + 6092 => x"38", + 6093 => x"33", + 6094 => x"2e", + 6095 => x"db", + 6096 => x"80", + 6097 => x"db", + 6098 => x"78", + 6099 => x"38", + 6100 => x"08", + 6101 => x"81", + 6102 => x"59", + 6103 => x"88", + 6104 => x"9c", + 6105 => x"39", + 6106 => x"33", + 6107 => x"2e", + 6108 => x"db", + 6109 => x"9a", + 6110 => x"d2", + 6111 => x"80", + 6112 => x"81", + 6113 => x"44", + 6114 => x"db", + 6115 => x"80", + 6116 => x"3d", + 6117 => x"53", + 6118 => x"51", + 6119 => x"3f", + 6120 => x"08", + 6121 => x"81", + 6122 => x"59", + 6123 => x"89", + 6124 => x"90", + 6125 => x"cc", + 6126 => x"d5", + 6127 => x"80", + 6128 => x"81", + 6129 => x"43", + 6130 => x"db", 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x"3f", + 6190 => x"08", + 6191 => x"c2", + 6192 => x"81", + 6193 => x"fe", + 6194 => x"63", + 6195 => x"b7", + 6196 => x"11", + 6197 => x"05", + 6198 => x"be", + 6199 => x"c0", + 6200 => x"f0", + 6201 => x"52", + 6202 => x"51", + 6203 => x"3f", + 6204 => x"2d", + 6205 => x"08", + 6206 => x"c0", + 6207 => x"f0", + 6208 => x"de", + 6209 => x"81", + 6210 => x"fe", + 6211 => x"ef", + 6212 => x"d9", + 6213 => x"ec", + 6214 => x"bd", + 6215 => x"e2", + 6216 => x"94", + 6217 => x"99", + 6218 => x"ff", + 6219 => x"e6", + 6220 => x"ce", + 6221 => x"33", + 6222 => x"80", + 6223 => x"38", + 6224 => x"81", + 6225 => x"70", + 6226 => x"5a", + 6227 => x"81", + 6228 => x"3d", + 6229 => x"51", + 6230 => x"3f", + 6231 => x"08", + 6232 => x"7b", + 6233 => x"38", + 6234 => x"89", + 6235 => x"2e", + 6236 => x"cd", + 6237 => x"2e", + 6238 => x"c5", + 6239 => x"a8", + 6240 => x"81", + 6241 => x"80", + 6242 => x"b0", + 6243 => x"ff", + 6244 => x"fe", + 6245 => x"bb", + 6246 => x"d0", + 6247 => x"ff", + 6248 => x"fe", + 6249 => x"ab", + 6250 => x"81", + 6251 => x"80", + 6252 => x"c0", + 6253 => x"ff", + 6254 => x"fe", + 6255 => x"93", + 6256 => x"80", + 6257 => x"cc", + 6258 => x"ff", + 6259 => x"fe", + 6260 => x"81", + 6261 => x"81", + 6262 => x"80", + 6263 => x"11", + 6264 => x"55", + 6265 => x"80", + 6266 => x"80", + 6267 => x"3d", + 6268 => x"51", + 6269 => x"81", + 6270 => x"81", + 6271 => x"09", + 6272 => x"72", + 6273 => x"51", + 6274 => x"7b", + 6275 => x"38", + 6276 => x"8d", + 6277 => x"70", + 6278 => x"5d", + 6279 => x"c3", + 6280 => x"32", + 6281 => x"07", + 6282 => x"38", + 6283 => x"09", + 6284 => x"ce", + 6285 => x"d4", + 6286 => x"e9", + 6287 => x"39", + 6288 => x"80", + 6289 => x"f4", + 6290 => x"94", + 6291 => x"54", + 6292 => x"80", + 6293 => x"fe", + 6294 => x"81", + 6295 => x"90", + 6296 => x"55", + 6297 => x"80", + 6298 => x"fe", + 6299 => x"72", + 6300 => x"08", + 6301 => x"87", + 6302 => x"70", + 6303 => x"87", + 6304 => x"72", + 6305 => x"f1", + 6306 => x"c0", + 6307 => x"75", + 6308 => x"87", + 6309 => x"73", + 6310 => x"dd", + 6311 => x"de", + 6312 => x"75", + 6313 => x"83", + 6314 => x"94", + 6315 => x"80", + 6316 => x"c0", + 6317 => x"9f", + 6318 => x"de", + 6319 => x"bb", + 6320 => x"d4", + 6321 => x"9e", + 6322 => x"c5", + 6323 => x"e4", + 6324 => x"ce", + 6325 => x"f0", + 6326 => x"e5", + 6327 => x"e1", + 6328 => x"a8", + 6329 => x"e6", + 6330 => x"c6", + 6331 => x"00", + 6332 => x"ff", + 6333 => x"00", + 6334 => x"ff", + 6335 => x"ff", + 6336 => x"00", + 6337 => x"00", + 6338 => x"00", + 6339 => x"00", + 6340 => x"00", + 6341 => x"00", + 6342 => x"00", + 6343 => x"00", + 6344 => x"00", + 6345 => x"00", + 6346 => x"00", + 6347 => x"00", + 6348 => x"00", + 6349 => x"00", + 6350 => x"00", + 6351 => x"00", + 6352 => x"00", + 6353 => x"00", + 6354 => x"00", + 6355 => x"00", + 6356 => x"00", + 6357 => x"00", + 6358 => x"00", + 6359 => x"00", + 6360 => x"00", + 6361 => x"64", + 6362 => x"2f", + 6363 => x"25", + 6364 => x"64", + 6365 => x"2e", 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x"30", + 6425 => x"2e", + 6426 => x"20", + 6427 => x"49", + 6428 => x"31", + 6429 => x"20", + 6430 => x"6d", + 6431 => x"20", + 6432 => x"30", + 6433 => x"2e", + 6434 => x"20", + 6435 => x"4e", + 6436 => x"43", + 6437 => x"20", + 6438 => x"61", + 6439 => x"6c", + 6440 => x"30", + 6441 => x"2e", + 6442 => x"20", + 6443 => x"49", + 6444 => x"4f", + 6445 => x"42", + 6446 => x"00", + 6447 => x"20", + 6448 => x"42", + 6449 => x"43", + 6450 => x"20", + 6451 => x"4f", + 6452 => x"0a", + 6453 => x"20", + 6454 => x"53", + 6455 => x"00", + 6456 => x"20", + 6457 => x"50", + 6458 => x"00", + 6459 => x"64", + 6460 => x"73", + 6461 => x"3a", + 6462 => x"20", + 6463 => x"50", + 6464 => x"65", + 6465 => x"20", + 6466 => x"74", + 6467 => x"41", + 6468 => x"65", + 6469 => x"3d", + 6470 => x"38", + 6471 => x"00", + 6472 => x"20", + 6473 => x"50", + 6474 => x"65", + 6475 => x"79", + 6476 => x"61", + 6477 => x"41", + 6478 => x"65", + 6479 => x"3d", + 6480 => x"38", + 6481 => x"00", + 6482 => x"20", + 6483 => x"74", + 6484 => x"20", + 6485 => x"72", + 6486 => x"64", + 6487 => x"73", + 6488 => x"20", + 6489 => x"3d", + 6490 => x"38", + 6491 => x"00", + 6492 => x"69", + 6493 => x"0a", + 6494 => x"20", + 6495 => x"50", + 6496 => x"64", + 6497 => x"20", + 6498 => x"20", + 6499 => x"20", + 6500 => x"20", + 6501 => x"3d", + 6502 => x"34", + 6503 => x"00", + 6504 => x"20", + 6505 => x"79", + 6506 => x"6d", + 6507 => x"6f", + 6508 => x"46", + 6509 => x"20", + 6510 => x"20", + 6511 => x"3d", + 6512 => x"2e", + 6513 => x"64", + 6514 => x"0a", + 6515 => x"20", + 6516 => x"44", + 6517 => x"20", + 6518 => x"63", + 6519 => x"72", + 6520 => x"20", + 6521 => x"20", + 6522 => x"3d", + 6523 => x"2e", + 6524 => x"64", + 6525 => x"0a", + 6526 => x"20", + 6527 => x"69", + 6528 => x"6f", + 6529 => x"53", + 6530 => x"4d", + 6531 => x"6f", + 6532 => x"46", + 6533 => x"3d", + 6534 => x"2e", + 6535 => x"64", + 6536 => x"0a", + 6537 => x"6d", + 6538 => x"00", + 6539 => x"65", + 6540 => x"6d", + 6541 => x"6c", + 6542 => x"00", + 6543 => x"56", + 6544 => x"56", + 6545 => x"6e", + 6546 => x"6e", + 6547 => x"77", + 6548 => x"44", + 6549 => x"2a", + 6550 => x"3b", + 6551 => x"3f", + 6552 => x"7f", + 6553 => x"41", + 6554 => x"41", + 6555 => x"00", + 6556 => x"fe", + 6557 => x"44", + 6558 => x"2e", + 6559 => x"4f", + 6560 => x"4d", + 6561 => x"20", + 6562 => x"54", + 6563 => x"20", + 6564 => x"4f", + 6565 => x"4d", + 6566 => x"20", + 6567 => x"54", + 6568 => x"20", + 6569 => x"00", + 6570 => x"00", + 6571 => x"00", + 6572 => x"00", + 6573 => x"9a", + 6574 => x"41", + 6575 => x"45", + 6576 => x"49", + 6577 => x"92", + 6578 => x"4f", + 6579 => x"99", + 6580 => x"9d", + 6581 => x"49", + 6582 => x"a5", + 6583 => x"a9", + 6584 => x"ad", + 6585 => x"b1", + 6586 => x"b5", + 6587 => x"b9", + 6588 => x"bd", + 6589 => x"c1", + 6590 => x"c5", + 6591 => x"c9", + 6592 => x"cd", + 6593 => x"d1", + 6594 => x"d5", + 6595 => x"d9", + 6596 => x"dd", + 6597 => x"e1", + 6598 => x"e5", + 6599 => x"e9", + 6600 => x"ed", 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x"00", + 6660 => x"69", + 6661 => x"6e", + 6662 => x"72", + 6663 => x"79", + 6664 => x"00", + 6665 => x"6f", + 6666 => x"6c", + 6667 => x"6f", + 6668 => x"2e", + 6669 => x"6f", + 6670 => x"74", + 6671 => x"6f", + 6672 => x"2e", + 6673 => x"6e", + 6674 => x"69", + 6675 => x"69", + 6676 => x"61", + 6677 => x"0a", + 6678 => x"63", + 6679 => x"73", + 6680 => x"6e", + 6681 => x"2e", + 6682 => x"69", + 6683 => x"61", + 6684 => x"61", + 6685 => x"65", + 6686 => x"74", + 6687 => x"00", + 6688 => x"69", + 6689 => x"68", + 6690 => x"6c", + 6691 => x"6e", + 6692 => x"69", + 6693 => x"00", + 6694 => x"44", + 6695 => x"20", + 6696 => x"74", + 6697 => x"72", + 6698 => x"63", + 6699 => x"2e", + 6700 => x"72", + 6701 => x"20", + 6702 => x"62", + 6703 => x"69", + 6704 => x"6e", + 6705 => x"69", + 6706 => x"00", + 6707 => x"69", + 6708 => x"6e", + 6709 => x"65", + 6710 => x"6c", + 6711 => x"0a", + 6712 => x"6f", + 6713 => x"6d", + 6714 => x"69", + 6715 => x"20", + 6716 => x"65", + 6717 => x"74", + 6718 => x"66", + 6719 => x"64", + 6720 => x"20", + 6721 => x"6b", + 6722 => x"00", + 6723 => x"6f", + 6724 => x"74", + 6725 => x"6f", + 6726 => x"64", + 6727 => x"00", + 6728 => x"69", + 6729 => x"75", + 6730 => x"6f", + 6731 => x"61", + 6732 => x"6e", + 6733 => x"6e", + 6734 => x"6c", + 6735 => x"0a", + 6736 => x"69", + 6737 => x"69", + 6738 => x"6f", + 6739 => x"64", + 6740 => x"00", + 6741 => x"6e", + 6742 => x"66", + 6743 => x"65", + 6744 => x"6d", + 6745 => x"72", + 6746 => x"00", + 6747 => x"6f", + 6748 => x"61", + 6749 => x"6f", + 6750 => x"20", + 6751 => x"65", + 6752 => x"00", + 6753 => x"61", + 6754 => x"65", + 6755 => x"73", + 6756 => x"63", + 6757 => x"65", + 6758 => x"0a", + 6759 => x"75", + 6760 => x"73", + 6761 => x"00", + 6762 => x"6e", + 6763 => x"77", + 6764 => x"72", + 6765 => x"2e", + 6766 => x"25", + 6767 => x"62", + 6768 => x"73", + 6769 => x"20", + 6770 => x"25", + 6771 => x"62", + 6772 => x"73", + 6773 => x"63", + 6774 => x"00", + 6775 => x"30", + 6776 => x"00", + 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x"20", + 6895 => x"74", + 6896 => x"69", + 6897 => x"0a", + 6898 => x"63", + 6899 => x"0a", + 6900 => x"75", + 6901 => x"6c", + 6902 => x"69", + 6903 => x"2e", + 6904 => x"00", + 6905 => x"75", + 6906 => x"4d", + 6907 => x"72", + 6908 => x"00", + 6909 => x"43", + 6910 => x"6c", + 6911 => x"2e", + 6912 => x"30", + 6913 => x"25", + 6914 => x"2d", + 6915 => x"3f", + 6916 => x"00", + 6917 => x"30", + 6918 => x"25", + 6919 => x"2d", + 6920 => x"30", + 6921 => x"25", + 6922 => x"2d", + 6923 => x"65", + 6924 => x"68", + 6925 => x"2e", + 6926 => x"00", + 6927 => x"30", + 6928 => x"2d", + 6929 => x"38", + 6930 => x"00", + 6931 => x"69", + 6932 => x"6c", + 6933 => x"20", + 6934 => x"65", + 6935 => x"70", + 6936 => x"00", + 6937 => x"6e", + 6938 => x"69", + 6939 => x"69", + 6940 => x"72", + 6941 => x"74", + 6942 => x"00", + 6943 => x"69", + 6944 => x"6c", + 6945 => x"75", + 6946 => x"20", + 6947 => x"6f", + 6948 => x"6e", + 6949 => x"69", + 6950 => x"75", + 6951 => x"20", + 6952 => x"6f", + 6953 => x"78", + 6954 => x"74", + 6955 => x"20", + 6956 => x"65", + 6957 => x"25", + 6958 => x"20", + 6959 => x"0a", + 6960 => x"61", + 6961 => x"6e", + 6962 => x"6f", + 6963 => x"40", + 6964 => x"38", + 6965 => x"2e", + 6966 => x"00", + 6967 => x"61", + 6968 => x"72", + 6969 => x"72", + 6970 => x"20", + 6971 => x"65", + 6972 => x"64", + 6973 => x"00", + 6974 => x"65", + 6975 => x"72", + 6976 => x"67", + 6977 => x"70", + 6978 => x"61", + 6979 => x"6e", + 6980 => x"0a", + 6981 => x"6f", + 6982 => x"72", + 6983 => x"6f", + 6984 => x"67", + 6985 => x"0a", + 6986 => x"50", + 6987 => x"69", + 6988 => x"64", + 6989 => x"73", + 6990 => x"2e", + 6991 => x"00", + 6992 => x"64", + 6993 => x"73", + 6994 => x"00", + 6995 => x"64", + 6996 => x"73", + 6997 => x"61", + 6998 => x"6f", + 6999 => x"6e", + 7000 => x"00", + 7001 => x"75", + 7002 => x"6e", + 7003 => x"2e", + 7004 => x"6e", + 7005 => x"69", + 7006 => x"69", + 7007 => x"72", + 7008 => x"74", + 7009 => x"2e", + 7010 => x"00", + 7011 => x"00", + 7012 => x"00", + 7013 => x"00", + 7014 => x"00", + 7015 => x"01", + 7016 => x"00", + 7017 => x"01", + 7018 => x"81", + 7019 => x"00", + 7020 => x"7f", + 7021 => x"00", + 7022 => x"00", + 7023 => x"00", + 7024 => x"00", + 7025 => x"f5", + 7026 => x"f5", + 7027 => x"f5", + 7028 => x"00", + 7029 => x"01", + 7030 => x"01", + 7031 => x"01", + 7032 => x"00", + 7033 => x"00", + 7034 => x"00", + 7035 => x"00", + 7036 => x"00", + 7037 => x"02", + 7038 => x"00", + 7039 => x"00", + 7040 => x"00", + 7041 => x"04", + 7042 => x"00", + 7043 => x"00", + 7044 => x"00", + 7045 => x"14", + 7046 => x"00", + 7047 => x"00", + 7048 => x"00", + 7049 => x"2b", + 7050 => x"00", + 7051 => x"00", + 7052 => x"00", + 7053 => x"30", + 7054 => x"00", + 7055 => x"00", + 7056 => x"00", + 7057 => x"3c", + 7058 => x"00", + 7059 => x"00", + 7060 => x"00", + 7061 => x"40", + 7062 => x"00", + 7063 => x"00", + 7064 => x"00", + 7065 => x"45", + 7066 => x"00", + 7067 => x"00", + 7068 => x"00", + 7069 => x"41", + 7070 => x"00", + 7071 => x"00", + 7072 => x"00", + 7073 => x"42", + 7074 => x"00", + 7075 => x"00", + 7076 => x"00", + 7077 => x"43", + 7078 => x"00", + 7079 => x"00", + 7080 => x"00", + 7081 => x"50", + 7082 => x"00", + 7083 => x"00", + 7084 => x"00", + 7085 => x"51", + 7086 => x"00", + 7087 => x"00", + 7088 => x"00", + 7089 => x"54", + 7090 => x"00", + 7091 => x"00", + 7092 => x"00", + 7093 => x"55", + 7094 => x"00", + 7095 => x"00", + 7096 => x"00", + 7097 => x"79", + 7098 => x"00", + 7099 => x"00", + 7100 => x"00", + 7101 => x"78", + 7102 => x"00", + 7103 => x"00", + 7104 => x"00", + 7105 => x"82", + 7106 => x"00", + 7107 => x"00", + 7108 => x"00", + 7109 => x"83", + 7110 => x"00", + 7111 => x"00", + 7112 => x"00", + 7113 => x"85", + 7114 => x"00", + 7115 => x"00", + 7116 => x"00", + 7117 => x"87", + 7118 => x"00", + 7119 => x"00", + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + 0 => x"0b", + 1 => x"d8", + 2 => x"00", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"88", + 9 => x"90", + 10 => x"08", + 11 => x"8c", + 12 => x"04", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"71", + 17 => x"72", + 18 => x"81", + 19 => x"83", + 20 => x"ff", + 21 => x"04", + 22 => x"00", + 23 => x"00", + 24 => x"71", + 25 => x"83", + 26 => x"83", + 27 => x"05", + 28 => x"2b", + 29 => x"73", + 30 => x"0b", + 31 => x"83", + 32 => x"72", + 33 => x"72", + 34 => x"09", + 35 => x"73", + 36 => x"07", + 37 => x"53", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"73", + 42 => x"51", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"71", + 50 => x"09", + 51 => x"0a", + 52 => x"0a", + 53 => x"05", + 54 => x"51", + 55 => x"04", + 56 => x"72", + 57 => x"73", + 58 => x"51", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"bc", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"0a", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"09", + 90 => x"0b", + 91 => x"05", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"73", + 98 => x"09", + 99 => x"81", + 100 => x"06", + 101 => x"04", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"04", + 106 => x"06", + 107 => x"82", + 108 => x"0b", + 109 => x"fc", + 110 => x"51", + 111 => x"00", + 112 => x"72", + 113 => x"72", + 114 => x"81", + 115 => x"0a", + 116 => x"51", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"72", + 121 => x"72", + 122 => x"81", + 123 => x"0a", + 124 => x"53", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"71", + 129 => x"52", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"04", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"73", + 146 => x"07", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"71", + 153 => x"72", + 154 => x"81", + 155 => x"10", + 156 => x"81", + 157 => x"04", + 158 => x"00", + 159 => x"00", + 160 => x"71", + 161 => x"0b", + 162 => x"f0", + 163 => x"10", + 164 => x"06", + 165 => x"92", + 166 => x"00", + 167 => x"00", + 168 => x"88", + 169 => x"90", + 170 => x"0b", + 171 => x"dd", + 172 => x"88", + 173 => x"0c", + 174 => x"0c", + 175 => x"00", + 176 => x"88", + 177 => x"90", + 178 => x"0b", + 179 => x"c9", + 180 => x"88", + 181 => x"0c", + 182 => x"0c", + 183 => x"00", + 184 => x"72", + 185 => x"05", + 186 => x"81", + 187 => x"70", + 188 => x"73", + 189 => x"05", + 190 => x"07", + 191 => x"04", + 192 => x"72", + 193 => x"05", + 194 => x"09", + 195 => x"05", + 196 => x"06", + 197 => x"74", + 198 => x"06", + 199 => x"51", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"04", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"71", + 217 => x"04", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"04", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"02", + 233 => x"10", + 234 => x"04", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"05", + 250 => x"02", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"00", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"0b", + 265 => x"81", + 266 => x"0b", + 267 => x"0b", + 268 => x"94", + 269 => x"0b", + 270 => x"0b", + 271 => x"b2", + 272 => x"0b", + 273 => x"0b", + 274 => x"d0", + 275 => x"0b", + 276 => x"0b", + 277 => x"ee", + 278 => x"0b", + 279 => x"0b", + 280 => x"8c", + 281 => x"0b", + 282 => x"0b", + 283 => x"aa", + 284 => x"0b", + 285 => x"0b", + 286 => x"c8", + 287 => x"0b", + 288 => x"0b", + 289 => x"e6", + 290 => x"0b", + 291 => x"0b", + 292 => x"84", + 293 => x"0b", + 294 => x"0b", + 295 => x"a4", + 296 => x"0b", + 297 => x"0b", + 298 => x"c4", + 299 => x"0b", + 300 => x"0b", + 301 => x"e4", + 302 => x"0b", + 303 => x"0b", + 304 => x"84", + 305 => x"0b", + 306 => x"0b", + 307 => x"a4", + 308 => x"0b", + 309 => x"0b", + 310 => x"c4", + 311 => x"0b", + 312 => x"0b", + 313 => x"e4", + 314 => x"0b", + 315 => x"0b", + 316 => x"84", + 317 => x"0b", + 318 => x"0b", + 319 => x"a4", + 320 => x"0b", + 321 => x"0b", + 322 => x"c4", + 323 => x"0b", + 324 => x"0b", + 325 => x"e4", + 326 => x"0b", + 327 => x"0b", + 328 => x"84", + 329 => x"0b", + 330 => x"0b", + 331 => x"a3", + 332 => x"0b", + 333 => x"0b", + 334 => x"c1", + 335 => x"0b", + 336 => x"0b", + 337 => x"df", + 338 => x"0b", + 339 => x"ff", + 340 => x"ff", + 341 => x"ff", + 342 => x"ff", + 343 => x"ff", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"04", + 385 => x"04", + 386 => x"0c", + 387 => x"81", + 388 => x"84", + 389 => x"81", + 390 => x"ad", + 391 => x"de", + 392 => x"80", + 393 => x"de", + 394 => x"a1", + 395 => x"cc", + 396 => x"90", + 397 => x"cc", + 398 => x"2d", + 399 => x"08", + 400 => x"04", + 401 => x"0c", + 402 => x"81", + 403 => x"84", + 404 => x"81", + 405 => x"b5", + 406 => x"de", + 407 => x"80", + 408 => x"de", + 409 => x"e2", + 410 => x"cc", + 411 => x"90", + 412 => x"cc", + 413 => x"2d", + 414 => x"08", + 415 => x"04", + 416 => x"0c", + 417 => x"81", + 418 => x"84", + 419 => x"81", + 420 => x"b4", + 421 => x"de", + 422 => x"80", + 423 => x"de", + 424 => x"b9", + 425 => x"cc", + 426 => x"90", + 427 => x"cc", + 428 => x"2d", + 429 => x"08", + 430 => x"04", + 431 => x"0c", + 432 => x"81", + 433 => x"84", + 434 => x"81", + 435 => x"a3", + 436 => x"de", + 437 => x"80", + 438 => x"de", + 439 => x"a8", + 440 => x"cc", + 441 => x"90", + 442 => x"cc", + 443 => x"2d", + 444 => x"08", + 445 => x"04", + 446 => x"0c", + 447 => x"81", + 448 => x"84", + 449 => x"81", + 450 => x"80", + 451 => x"81", + 452 => x"84", + 453 => x"81", + 454 => x"80", + 455 => x"81", + 456 => x"84", + 457 => x"81", + 458 => x"80", + 459 => x"81", + 460 => x"84", + 461 => x"81", + 462 => x"80", + 463 => x"81", + 464 => x"84", + 465 => x"81", + 466 => x"80", + 467 => x"81", + 468 => x"84", + 469 => x"81", + 470 => x"81", + 471 => x"81", + 472 => x"84", + 473 => x"81", + 474 => x"80", + 475 => x"81", + 476 => x"84", + 477 => x"81", + 478 => x"80", + 479 => x"81", + 480 => x"84", + 481 => x"81", + 482 => x"81", + 483 => x"81", + 484 => x"84", + 485 => x"81", + 486 => x"81", + 487 => x"81", + 488 => x"84", + 489 => x"81", + 490 => x"81", + 491 => x"81", + 492 => x"84", + 493 => x"81", + 494 => x"81", + 495 => x"81", + 496 => x"84", + 497 => x"81", + 498 => x"81", + 499 => x"81", + 500 => x"84", + 501 => x"81", + 502 => x"81", + 503 => x"81", + 504 => x"84", + 505 => x"81", + 506 => x"81", + 507 => x"81", + 508 => x"84", + 509 => x"81", + 510 => x"81", + 511 => x"81", + 512 => x"84", + 513 => x"81", + 514 => x"80", + 515 => x"81", + 516 => x"84", + 517 => x"81", + 518 => x"80", + 519 => x"81", + 520 => x"84", + 521 => x"81", + 522 => x"80", + 523 => x"81", + 524 => x"84", + 525 => x"81", + 526 => x"81", + 527 => x"81", + 528 => x"84", + 529 => x"81", + 530 => x"81", + 531 => x"81", + 532 => x"84", + 533 => x"81", + 534 => x"81", + 535 => x"81", + 536 => x"84", + 537 => x"81", + 538 => x"81", + 539 => x"81", + 540 => x"84", + 541 => x"81", + 542 => x"80", + 543 => x"81", + 544 => x"84", + 545 => x"81", + 546 => x"81", + 547 => x"81", + 548 => x"84", + 549 => x"81", + 550 => x"bb", + 551 => x"de", + 552 => x"80", + 553 => x"de", + 554 => x"83", + 555 => x"cc", + 556 => x"90", + 557 => x"cc", + 558 => x"2d", + 559 => x"08", + 560 => x"04", + 561 => x"0c", + 562 => x"81", + 563 => x"84", + 564 => x"81", + 565 => x"9c", + 566 => x"de", + 567 => x"80", + 568 => x"de", + 569 => x"a0", + 570 => x"cc", + 571 => x"90", + 572 => x"cc", + 573 => x"ff", + 574 => x"cc", + 575 => x"90", + 576 => x"10", + 577 => x"10", + 578 => x"10", + 579 => x"10", + 580 => x"10", + 581 => x"10", + 582 => x"10", + 583 => x"10", + 584 => x"51", + 585 => x"73", + 586 => x"73", + 587 => x"81", + 588 => x"10", + 589 => x"07", + 590 => x"0c", + 591 => x"72", + 592 => x"81", + 593 => x"09", + 594 => x"71", + 595 => x"0a", + 596 => x"72", + 597 => x"51", + 598 => x"81", + 599 => x"81", + 600 => x"8e", + 601 => x"70", + 602 => x"0c", + 603 => x"92", + 604 => x"81", + 605 => x"be", + 606 => x"de", + 607 => x"81", + 608 => x"fd", + 609 => x"53", + 610 => x"08", + 611 => x"52", + 612 => x"08", + 613 => x"51", + 614 => x"81", + 615 => x"70", + 616 => x"0c", + 617 => x"0d", + 618 => x"0c", + 619 => x"cc", + 620 => x"de", + 621 => x"3d", + 622 => x"81", + 623 => x"8c", + 624 => x"81", + 625 => x"88", + 626 => x"83", + 627 => x"de", + 628 => x"81", + 629 => x"54", + 630 => x"81", + 631 => x"04", + 632 => x"08", + 633 => x"cc", + 634 => x"0d", + 635 => x"de", + 636 => x"05", + 637 => x"cc", + 638 => x"08", + 639 => x"38", + 640 => x"08", + 641 => x"30", + 642 => x"08", + 643 => x"80", + 644 => x"cc", + 645 => x"0c", + 646 => x"08", + 647 => x"8a", + 648 => x"81", + 649 => x"f4", + 650 => x"de", + 651 => x"05", + 652 => x"cc", + 653 => x"0c", + 654 => x"08", + 655 => x"80", + 656 => x"81", + 657 => x"8c", + 658 => x"81", + 659 => x"8c", + 660 => x"0b", + 661 => x"08", + 662 => x"81", + 663 => x"fc", + 664 => x"38", + 665 => x"de", + 666 => x"05", + 667 => x"cc", + 668 => x"08", + 669 => x"08", + 670 => x"80", + 671 => x"cc", + 672 => x"08", + 673 => x"cc", + 674 => x"08", + 675 => x"3f", + 676 => x"08", + 677 => x"cc", + 678 => x"0c", + 679 => x"cc", + 680 => x"08", + 681 => x"38", + 682 => x"08", + 683 => x"30", + 684 => x"08", + 685 => x"81", + 686 => x"f8", + 687 => x"81", + 688 => x"54", + 689 => x"81", + 690 => x"04", + 691 => x"08", + 692 => x"cc", + 693 => x"0d", + 694 => x"de", + 695 => x"05", + 696 => x"cc", + 697 => x"08", + 698 => x"38", + 699 => x"08", + 700 => x"30", + 701 => x"08", + 702 => x"81", + 703 => x"cc", + 704 => x"0c", + 705 => x"08", + 706 => x"80", + 707 => x"81", + 708 => x"8c", + 709 => x"81", + 710 => x"8c", + 711 => x"53", + 712 => x"08", + 713 => x"52", + 714 => x"08", + 715 => x"51", + 716 => x"de", + 717 => x"81", + 718 => x"f8", + 719 => x"81", + 720 => x"fc", + 721 => x"2e", + 722 => x"de", + 723 => x"05", + 724 => x"de", + 725 => x"05", + 726 => x"cc", + 727 => x"08", + 728 => x"c0", + 729 => x"3d", + 730 => x"cc", + 731 => x"de", + 732 => x"81", + 733 => x"fd", + 734 => x"0b", + 735 => x"08", + 736 => x"80", + 737 => x"cc", + 738 => x"0c", + 739 => x"08", + 740 => x"81", + 741 => x"88", + 742 => x"b9", + 743 => x"cc", + 744 => x"08", + 745 => x"38", + 746 => x"de", + 747 => x"05", + 748 => x"38", + 749 => x"08", + 750 => x"10", + 751 => x"08", + 752 => x"81", + 753 => x"fc", + 754 => x"81", + 755 => x"fc", + 756 => x"b8", + 757 => x"cc", + 758 => x"08", + 759 => x"e1", + 760 => x"cc", + 761 => x"08", + 762 => x"08", + 763 => x"26", + 764 => x"de", + 765 => x"05", + 766 => x"cc", + 767 => x"08", + 768 => x"cc", + 769 => x"0c", + 770 => x"08", + 771 => x"81", + 772 => x"fc", + 773 => x"81", + 774 => x"f8", + 775 => x"de", + 776 => x"05", + 777 => x"81", + 778 => x"fc", + 779 => x"de", + 780 => x"05", + 781 => x"81", + 782 => x"8c", + 783 => x"95", + 784 => x"cc", + 785 => x"08", + 786 => x"38", + 787 => x"08", + 788 => x"70", + 789 => x"08", + 790 => x"51", + 791 => x"de", + 792 => x"05", + 793 => x"de", + 794 => x"05", + 795 => x"de", + 796 => x"05", + 797 => x"c0", + 798 => x"0d", + 799 => x"0c", + 800 => x"0d", + 801 => x"02", + 802 => x"05", + 803 => x"53", + 804 => x"27", + 805 => x"83", + 806 => x"80", + 807 => x"ff", + 808 => x"ff", + 809 => x"73", + 810 => x"05", + 811 => x"12", + 812 => x"2e", + 813 => x"ef", + 814 => x"de", + 815 => x"3d", + 816 => x"74", + 817 => x"07", + 818 => x"2b", + 819 => x"51", + 820 => x"a5", + 821 => x"70", + 822 => x"0c", + 823 => x"84", + 824 => x"72", + 825 => x"05", + 826 => x"71", + 827 => x"53", + 828 => x"52", + 829 => x"dd", + 830 => x"27", + 831 => x"71", + 832 => x"53", + 833 => x"52", + 834 => x"f2", + 835 => x"ff", + 836 => x"3d", + 837 => x"70", + 838 => x"06", + 839 => x"70", + 840 => x"73", + 841 => x"56", + 842 => x"08", + 843 => x"38", + 844 => x"52", + 845 => x"81", + 846 => x"54", + 847 => x"9d", + 848 => x"55", + 849 => x"09", + 850 => x"38", + 851 => x"14", + 852 => x"81", + 853 => x"56", + 854 => x"e5", + 855 => x"55", + 856 => x"06", + 857 => x"06", + 858 => x"81", + 859 => x"52", + 860 => x"0d", + 861 => x"70", + 862 => x"ff", + 863 => x"f8", + 864 => x"80", + 865 => x"51", + 866 => x"84", + 867 => x"71", + 868 => x"54", + 869 => x"2e", + 870 => x"75", + 871 => x"94", + 872 => x"81", + 873 => x"87", + 874 => x"fe", + 875 => x"52", + 876 => x"88", + 877 => x"86", + 878 => x"c0", + 879 => x"06", + 880 => x"14", + 881 => x"80", + 882 => x"71", + 883 => x"0c", + 884 => x"04", + 885 => x"77", + 886 => x"53", + 887 => x"80", + 888 => x"38", + 889 => x"70", + 890 => x"81", + 891 => x"81", + 892 => x"39", + 893 => x"39", + 894 => x"80", + 895 => x"81", + 896 => x"55", + 897 => x"2e", + 898 => x"55", + 899 => x"84", + 900 => x"38", + 901 => x"06", + 902 => x"2e", + 903 => x"88", + 904 => x"70", + 905 => x"34", + 906 => x"71", + 907 => x"de", + 908 => x"3d", + 909 => x"3d", + 910 => x"72", + 911 => x"91", + 912 => x"fc", + 913 => x"51", + 914 => x"81", + 915 => x"85", + 916 => x"83", + 917 => x"72", + 918 => x"0c", + 919 => x"04", + 920 => x"76", + 921 => x"ff", + 922 => x"81", + 923 => x"26", + 924 => x"83", + 925 => x"05", + 926 => x"70", + 927 => x"8a", + 928 => x"33", + 929 => x"70", + 930 => x"fe", + 931 => x"33", + 932 => x"70", + 933 => x"f2", + 934 => x"33", + 935 => x"70", + 936 => x"e6", + 937 => x"22", + 938 => x"74", + 939 => x"80", + 940 => x"13", + 941 => x"52", + 942 => x"26", + 943 => x"81", + 944 => x"98", + 945 => x"22", + 946 => x"bc", + 947 => x"33", + 948 => x"b8", + 949 => x"33", + 950 => x"b4", + 951 => x"33", + 952 => x"b0", + 953 => x"33", + 954 => x"ac", + 955 => x"33", + 956 => x"a8", + 957 => x"c0", + 958 => x"73", + 959 => x"a0", + 960 => x"87", + 961 => x"0c", + 962 => x"81", + 963 => x"86", + 964 => x"f3", + 965 => x"5b", + 966 => x"9c", + 967 => x"0c", + 968 => x"bc", + 969 => x"7b", + 970 => x"98", + 971 => x"79", + 972 => x"87", + 973 => x"08", + 974 => x"1c", + 975 => x"98", + 976 => x"79", + 977 => x"87", + 978 => x"08", + 979 => x"1c", + 980 => x"98", + 981 => x"79", + 982 => x"87", + 983 => x"08", + 984 => x"1c", + 985 => x"98", + 986 => x"79", + 987 => x"80", + 988 => x"83", + 989 => x"59", + 990 => x"ff", + 991 => x"1b", + 992 => x"1b", + 993 => x"1b", + 994 => x"1b", + 995 => x"1b", + 996 => x"83", + 997 => x"52", + 998 => x"51", + 999 => x"8f", + 1000 => x"ff", + 1001 => x"8f", + 1002 => x"30", + 1003 => x"51", + 1004 => x"0b", + 1005 => x"88", + 1006 => x"0d", + 1007 => x"0d", + 1008 => x"81", + 1009 => x"70", + 1010 => x"57", + 1011 => x"c0", + 1012 => x"74", + 1013 => x"38", + 1014 => x"94", + 1015 => x"70", + 1016 => x"81", + 1017 => x"52", + 1018 => x"8c", + 1019 => x"2a", + 1020 => x"51", + 1021 => x"38", + 1022 => x"70", + 1023 => x"51", + 1024 => x"8d", + 1025 => x"2a", + 1026 => x"51", + 1027 => x"be", + 1028 => x"ff", + 1029 => x"c0", + 1030 => x"70", + 1031 => x"38", + 1032 => x"90", + 1033 => x"0c", + 1034 => x"c0", + 1035 => x"0d", + 1036 => x"0d", + 1037 => x"33", + 1038 => x"db", + 1039 => x"81", + 1040 => x"55", + 1041 => x"94", + 1042 => x"80", + 1043 => x"87", + 1044 => x"51", + 1045 => x"96", + 1046 => x"06", + 1047 => x"70", + 1048 => x"38", + 1049 => x"70", + 1050 => x"51", + 1051 => x"72", + 1052 => x"81", + 1053 => x"70", + 1054 => x"38", + 1055 => x"70", + 1056 => x"51", + 1057 => x"38", + 1058 => x"06", + 1059 => x"94", + 1060 => x"80", + 1061 => x"87", + 1062 => x"52", + 1063 => x"87", + 1064 => x"f9", + 1065 => x"54", + 1066 => x"70", + 1067 => x"53", + 1068 => x"77", + 1069 => x"38", + 1070 => x"06", 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x"38", + 1130 => x"94", + 1131 => x"70", + 1132 => x"81", + 1133 => x"51", + 1134 => x"80", + 1135 => x"72", + 1136 => x"51", + 1137 => x"80", + 1138 => x"2e", + 1139 => x"c0", + 1140 => x"71", + 1141 => x"2b", + 1142 => x"51", + 1143 => x"81", + 1144 => x"84", + 1145 => x"ff", + 1146 => x"c0", + 1147 => x"70", + 1148 => x"06", + 1149 => x"80", + 1150 => x"38", + 1151 => x"a4", + 1152 => x"8c", + 1153 => x"9e", + 1154 => x"db", + 1155 => x"c0", + 1156 => x"81", + 1157 => x"87", + 1158 => x"08", + 1159 => x"0c", + 1160 => x"9c", + 1161 => x"9c", + 1162 => x"9e", + 1163 => x"db", + 1164 => x"c0", + 1165 => x"81", + 1166 => x"87", + 1167 => x"08", + 1168 => x"0c", + 1169 => x"b4", + 1170 => x"ac", + 1171 => x"9e", + 1172 => x"db", + 1173 => x"c0", + 1174 => x"81", + 1175 => x"87", + 1176 => x"08", + 1177 => x"0c", + 1178 => x"c4", + 1179 => x"bc", + 1180 => x"9e", + 1181 => x"70", + 1182 => x"23", + 1183 => x"84", + 1184 => x"c4", + 1185 => x"9e", + 1186 => x"db", + 1187 => x"c0", + 1188 => x"81", + 1189 => x"81", + 1190 => x"d0", + 1191 => x"87", + 1192 => x"08", + 1193 => x"0a", + 1194 => x"52", + 1195 => x"83", + 1196 => x"71", + 1197 => x"34", + 1198 => x"c0", + 1199 => x"70", + 1200 => x"06", + 1201 => x"70", + 1202 => x"38", + 1203 => x"81", + 1204 => x"80", + 1205 => x"9e", + 1206 => x"90", + 1207 => x"51", + 1208 => x"80", + 1209 => x"81", + 1210 => x"db", + 1211 => x"0b", + 1212 => x"90", + 1213 => x"80", + 1214 => x"52", + 1215 => x"2e", + 1216 => x"52", + 1217 => x"d4", + 1218 => x"87", + 1219 => x"08", + 1220 => x"80", + 1221 => x"52", + 1222 => x"83", + 1223 => x"71", + 1224 => x"34", + 1225 => x"c0", + 1226 => x"70", + 1227 => x"06", + 1228 => x"70", + 1229 => x"38", + 1230 => x"81", + 1231 => x"80", + 1232 => x"9e", + 1233 => x"84", + 1234 => x"51", + 1235 => x"80", + 1236 => x"81", + 1237 => x"db", + 1238 => x"0b", + 1239 => x"90", + 1240 => x"80", + 1241 => x"52", + 1242 => x"2e", + 1243 => x"52", + 1244 => x"d8", + 1245 => x"87", + 1246 => x"08", + 1247 => x"80", + 1248 => x"52", + 1249 => x"83", + 1250 => x"71", + 1251 => x"34", + 1252 => x"c0", + 1253 => x"70", + 1254 => x"06", + 1255 => x"70", + 1256 => x"38", + 1257 => x"81", + 1258 => x"80", + 1259 => x"9e", + 1260 => x"a0", + 1261 => x"52", + 1262 => x"2e", + 1263 => x"52", + 1264 => x"db", + 1265 => x"9e", + 1266 => x"98", + 1267 => x"8a", + 1268 => x"51", + 1269 => x"dc", + 1270 => x"87", + 1271 => x"08", + 1272 => x"06", + 1273 => x"70", + 1274 => x"38", + 1275 => x"81", + 1276 => x"87", + 1277 => x"08", + 1278 => x"06", + 1279 => x"51", + 1280 => x"81", + 1281 => x"80", + 1282 => x"9e", + 1283 => x"88", + 1284 => x"52", + 1285 => x"83", + 1286 => x"71", + 1287 => x"34", + 1288 => x"90", + 1289 => x"06", + 1290 => x"81", + 1291 => x"83", + 1292 => x"fb", + 1293 => x"c6", + 1294 => x"86", + 1295 => x"d0", + 1296 => x"80", + 1297 => x"81", + 1298 => x"85", + 1299 => x"c7", + 1300 => x"ee", + 1301 => x"d2", + 1302 => x"80", + 1303 => x"81", + 1304 => x"81", + 1305 => x"11", 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x"83", + 1365 => x"db", + 1366 => x"73", + 1367 => x"38", + 1368 => x"51", + 1369 => x"81", + 1370 => x"54", + 1371 => x"88", + 1372 => x"e0", + 1373 => x"3f", + 1374 => x"51", + 1375 => x"81", + 1376 => x"52", + 1377 => x"51", + 1378 => x"81", + 1379 => x"52", + 1380 => x"51", + 1381 => x"81", + 1382 => x"52", + 1383 => x"51", + 1384 => x"81", + 1385 => x"f5", + 1386 => x"db", + 1387 => x"81", + 1388 => x"88", + 1389 => x"db", + 1390 => x"bd", + 1391 => x"75", + 1392 => x"3f", + 1393 => x"08", + 1394 => x"29", + 1395 => x"54", + 1396 => x"c0", + 1397 => x"cb", + 1398 => x"ca", + 1399 => x"d7", + 1400 => x"80", + 1401 => x"81", + 1402 => x"56", + 1403 => x"52", + 1404 => x"86", + 1405 => x"c0", + 1406 => x"c0", + 1407 => x"31", + 1408 => x"de", + 1409 => x"81", + 1410 => x"88", + 1411 => x"db", + 1412 => x"73", + 1413 => x"38", + 1414 => x"08", + 1415 => x"c0", + 1416 => x"e6", + 1417 => x"de", + 1418 => x"84", + 1419 => x"71", + 1420 => x"81", + 1421 => x"52", + 1422 => x"51", + 1423 => x"81", + 1424 => x"81", + 1425 => x"3d", + 1426 => x"3d", + 1427 => x"05", + 1428 => x"52", + 1429 => x"aa", + 1430 => x"29", + 1431 => x"05", + 1432 => x"04", + 1433 => x"51", + 1434 => x"cc", + 1435 => x"39", + 1436 => x"51", + 1437 => x"cc", + 1438 => x"39", + 1439 => x"51", + 1440 => x"cc", + 1441 => x"9b", + 1442 => x"0d", + 1443 => x"80", + 1444 => x"0b", + 1445 => x"84", + 1446 => x"3d", + 1447 => x"96", + 1448 => x"52", + 1449 => x"0c", + 1450 => x"70", + 1451 => x"0c", + 1452 => x"3d", + 1453 => x"3d", + 1454 => x"96", + 1455 => x"81", + 1456 => x"52", + 1457 => x"73", + 1458 => x"db", + 1459 => x"70", + 1460 => x"0c", + 1461 => x"83", + 1462 => x"81", + 1463 => x"87", + 1464 => x"0c", + 1465 => x"0d", + 1466 => x"33", + 1467 => x"2e", + 1468 => x"85", + 1469 => x"ed", + 1470 => x"d8", + 1471 => x"80", + 1472 => x"72", + 1473 => x"de", + 1474 => x"05", + 1475 => x"0c", + 1476 => x"de", + 1477 => x"71", + 1478 => x"38", + 1479 => x"2d", + 1480 => x"04", + 1481 => x"02", + 1482 => x"81", + 1483 => x"76", + 1484 => x"0c", + 1485 => x"ad", + 1486 => x"de", + 1487 => x"3d", + 1488 => x"3d", + 1489 => x"73", + 1490 => x"ff", + 1491 => x"71", + 1492 => x"38", + 1493 => x"06", + 1494 => x"54", + 1495 => x"e7", + 1496 => x"0d", + 1497 => x"0d", + 1498 => x"d0", + 1499 => x"de", + 1500 => x"54", + 1501 => x"81", + 1502 => x"53", + 1503 => x"8e", + 1504 => x"ff", + 1505 => x"14", + 1506 => x"3f", + 1507 => x"81", + 1508 => x"86", + 1509 => x"ec", + 1510 => x"68", + 1511 => x"70", + 1512 => x"33", + 1513 => x"2e", + 1514 => x"75", + 1515 => x"81", + 1516 => x"38", + 1517 => x"70", + 1518 => x"33", + 1519 => x"75", + 1520 => x"81", + 1521 => x"81", + 1522 => x"75", + 1523 => x"81", + 1524 => x"82", + 1525 => x"81", + 1526 => x"56", + 1527 => x"09", + 1528 => x"38", + 1529 => x"71", + 1530 => x"81", + 1531 => x"59", + 1532 => x"9d", + 1533 => x"53", + 1534 => x"95", + 1535 => x"29", + 1536 => x"76", + 1537 => x"79", + 1538 => x"5b", + 1539 => x"e5", + 1540 => x"ec", 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x"93", + 1600 => x"95", + 1601 => x"91", + 1602 => x"8d", + 1603 => x"89", + 1604 => x"fb", + 1605 => x"86", + 1606 => x"2a", + 1607 => x"51", + 1608 => x"2e", + 1609 => x"84", + 1610 => x"86", + 1611 => x"78", + 1612 => x"08", + 1613 => x"32", + 1614 => x"72", + 1615 => x"51", + 1616 => x"74", + 1617 => x"38", + 1618 => x"88", + 1619 => x"7a", + 1620 => x"55", + 1621 => x"3d", + 1622 => x"52", + 1623 => x"cd", + 1624 => x"c0", + 1625 => x"06", + 1626 => x"52", + 1627 => x"3f", + 1628 => x"08", + 1629 => x"27", + 1630 => x"14", + 1631 => x"f8", + 1632 => x"87", + 1633 => x"81", + 1634 => x"b0", + 1635 => x"7d", + 1636 => x"5f", + 1637 => x"75", + 1638 => x"07", + 1639 => x"54", + 1640 => x"26", + 1641 => x"ff", + 1642 => x"84", + 1643 => x"06", + 1644 => x"80", + 1645 => x"96", + 1646 => x"e0", + 1647 => x"73", + 1648 => x"57", + 1649 => x"06", + 1650 => x"54", + 1651 => x"a0", + 1652 => x"2a", + 1653 => x"54", + 1654 => x"38", + 1655 => x"76", + 1656 => x"38", + 1657 => x"fd", + 1658 => x"06", + 1659 => x"38", + 1660 => x"56", + 1661 => x"26", + 1662 => x"3d", + 1663 => x"05", + 1664 => x"ff", + 1665 => x"53", + 1666 => x"d9", + 1667 => x"38", + 1668 => x"56", + 1669 => x"27", + 1670 => x"a0", + 1671 => x"3f", + 1672 => x"3d", + 1673 => x"3d", + 1674 => x"70", + 1675 => x"52", + 1676 => x"73", + 1677 => x"3f", + 1678 => x"04", + 1679 => x"74", + 1680 => x"0c", + 1681 => x"05", + 1682 => x"fa", + 1683 => x"de", + 1684 => x"80", + 1685 => x"0b", + 1686 => x"0c", + 1687 => x"04", + 1688 => x"81", + 1689 => x"76", + 1690 => x"0c", + 1691 => x"05", + 1692 => x"53", + 1693 => x"72", + 1694 => x"0c", + 1695 => x"04", + 1696 => x"77", + 1697 => x"d4", + 1698 => x"54", + 1699 => x"54", + 1700 => x"80", + 1701 => x"de", + 1702 => x"71", + 1703 => x"c0", + 1704 => x"06", + 1705 => x"2e", + 1706 => x"72", + 1707 => x"38", + 1708 => x"70", + 1709 => x"25", + 1710 => x"73", + 1711 => x"38", + 1712 => x"86", + 1713 => x"54", + 1714 => x"73", + 1715 => x"ff", + 1716 => x"72", + 1717 => x"74", + 1718 => x"72", + 1719 => x"54", + 1720 => x"81", + 1721 => x"39", + 1722 => x"80", + 1723 => x"51", + 1724 => x"81", + 1725 => x"de", + 1726 => x"3d", + 1727 => x"3d", + 1728 => x"d4", + 1729 => x"de", + 1730 => x"53", + 1731 => x"fe", + 1732 => x"81", + 1733 => x"84", + 1734 => x"f8", + 1735 => x"7c", + 1736 => x"70", + 1737 => x"75", + 1738 => x"55", + 1739 => x"2e", + 1740 => x"87", + 1741 => x"76", + 1742 => x"73", + 1743 => x"81", + 1744 => x"81", + 1745 => x"77", + 1746 => x"70", + 1747 => x"58", + 1748 => x"09", + 1749 => x"c2", + 1750 => x"81", + 1751 => x"75", + 1752 => x"55", + 1753 => x"e2", + 1754 => x"90", + 1755 => x"f8", + 1756 => x"8f", + 1757 => x"81", + 1758 => x"75", + 1759 => x"55", + 1760 => x"81", + 1761 => x"27", + 1762 => x"d0", + 1763 => x"55", + 1764 => x"73", + 1765 => x"80", + 1766 => x"14", + 1767 => x"72", + 1768 => x"e0", + 1769 => x"80", + 1770 => x"39", + 1771 => x"55", + 1772 => x"80", + 1773 => x"e0", + 1774 => x"38", + 1775 => x"81", + 1776 => x"53", + 1777 => x"81", + 1778 => x"53", + 1779 => x"8e", + 1780 => x"70", + 1781 => x"55", + 1782 => x"27", + 1783 => x"77", + 1784 => x"74", + 1785 => x"76", + 1786 => x"77", + 1787 => x"70", + 1788 => x"55", + 1789 => x"77", + 1790 => x"38", + 1791 => x"74", + 1792 => x"55", + 1793 => x"c0", + 1794 => x"0d", + 1795 => x"0d", + 1796 => x"56", + 1797 => x"0c", + 1798 => x"70", + 1799 => x"73", + 1800 => x"81", + 1801 => x"81", + 1802 => x"ed", + 1803 => x"2e", + 1804 => x"8e", + 1805 => x"08", + 1806 => x"76", + 1807 => x"56", + 1808 => x"b0", + 1809 => x"06", + 1810 => x"75", + 1811 => x"76", + 1812 => x"70", + 1813 => x"73", + 1814 => x"8b", + 1815 => x"73", + 1816 => x"85", + 1817 => x"82", + 1818 => x"76", + 1819 => x"70", + 1820 => x"ac", + 1821 => x"a0", + 1822 => x"fa", + 1823 => x"53", + 1824 => x"57", + 1825 => x"98", + 1826 => x"39", + 1827 => x"80", + 1828 => x"26", + 1829 => x"86", + 1830 => x"80", + 1831 => x"57", + 1832 => x"74", + 1833 => x"38", + 1834 => x"27", + 1835 => x"14", + 1836 => x"06", + 1837 => x"14", + 1838 => x"06", + 1839 => x"74", + 1840 => x"f9", + 1841 => x"ff", + 1842 => x"89", + 1843 => x"38", + 1844 => x"c5", + 1845 => x"29", + 1846 => x"81", + 1847 => x"76", + 1848 => x"56", + 1849 => x"ba", + 1850 => x"2e", + 1851 => x"30", + 1852 => x"0c", + 1853 => x"81", + 1854 => x"8a", + 1855 => x"ff", + 1856 => x"8f", + 1857 => x"81", + 1858 => x"26", + 1859 => x"db", + 1860 => x"52", + 1861 => x"c0", + 1862 => x"0d", + 1863 => x"0d", + 1864 => x"33", + 1865 => x"9f", + 1866 => x"53", + 1867 => x"81", + 1868 => x"38", + 1869 => x"87", + 1870 => x"11", + 1871 => x"54", + 1872 => x"84", + 1873 => x"54", + 1874 => x"87", + 1875 => x"11", + 1876 => x"0c", + 1877 => x"c0", + 1878 => x"70", + 1879 => x"70", + 1880 => x"51", + 1881 => x"8a", + 1882 => x"98", + 1883 => x"70", + 1884 => x"08", + 1885 => x"06", + 1886 => x"38", + 1887 => x"8c", + 1888 => x"80", + 1889 => x"71", + 1890 => x"14", + 1891 => x"e8", + 1892 => x"70", + 1893 => x"0c", + 1894 => x"04", + 1895 => x"60", + 1896 => x"8c", + 1897 => x"33", + 1898 => x"5b", + 1899 => x"5a", + 1900 => x"81", + 1901 => x"81", + 1902 => x"52", + 1903 => x"38", + 1904 => x"84", + 1905 => x"92", + 1906 => x"c0", + 1907 => x"87", + 1908 => x"13", + 1909 => x"57", + 1910 => x"0b", + 1911 => x"8c", + 1912 => x"0c", + 1913 => x"75", + 1914 => x"2a", + 1915 => x"51", + 1916 => x"80", + 1917 => x"7b", + 1918 => x"7b", + 1919 => x"5d", + 1920 => x"59", + 1921 => x"06", + 1922 => x"73", + 1923 => x"81", + 1924 => x"ff", + 1925 => x"72", + 1926 => x"38", + 1927 => x"8c", + 1928 => x"c3", + 1929 => x"98", + 1930 => x"71", + 1931 => x"38", + 1932 => x"2e", + 1933 => x"76", + 1934 => x"92", + 1935 => x"72", + 1936 => x"06", + 1937 => x"f7", + 1938 => x"5a", + 1939 => x"80", + 1940 => x"70", + 1941 => x"5a", + 1942 => x"80", + 1943 => x"73", + 1944 => x"06", + 1945 => x"38", + 1946 => x"fe", + 1947 => x"fc", + 1948 => x"52", + 1949 => x"83", + 1950 => x"71", + 1951 => x"de", + 1952 => x"3d", + 1953 => x"3d", + 1954 => x"64", + 1955 => x"bf", + 1956 => x"40", + 1957 => x"59", + 1958 => x"58", + 1959 => x"81", + 1960 => x"81", + 1961 => x"52", + 1962 => x"09", + 1963 => x"b1", + 1964 => x"84", + 1965 => x"92", + 1966 => x"c0", + 1967 => x"87", + 1968 => x"13", + 1969 => x"56", + 1970 => x"87", + 1971 => x"0c", + 1972 => x"82", + 1973 => x"58", + 1974 => x"84", + 1975 => x"06", + 1976 => x"71", + 1977 => x"38", + 1978 => x"05", + 1979 => x"0c", + 1980 => x"73", + 1981 => x"81", + 1982 => x"71", + 1983 => x"38", + 1984 => x"8c", + 1985 => x"d0", + 1986 => x"98", + 1987 => x"71", + 1988 => x"38", + 1989 => x"2e", + 1990 => x"76", + 1991 => x"92", + 1992 => x"72", + 1993 => x"06", + 1994 => x"f7", + 1995 => x"59", + 1996 => x"1a", + 1997 => x"06", + 1998 => x"59", + 1999 => x"80", + 2000 => x"73", + 2001 => x"06", + 2002 => x"38", + 2003 => x"fe", + 2004 => x"fc", + 2005 => x"52", + 2006 => x"83", + 2007 => x"71", + 2008 => x"de", + 2009 => x"3d", + 2010 => x"3d", + 2011 => x"84", + 2012 => x"33", + 2013 => x"b7", + 2014 => x"54", + 2015 => x"fa", + 2016 => x"de", + 2017 => x"06", + 2018 => x"72", + 2019 => x"85", + 2020 => x"98", + 2021 => x"56", + 2022 => x"80", + 2023 => x"76", + 2024 => x"74", + 2025 => x"c0", + 2026 => x"54", + 2027 => x"2e", + 2028 => x"d4", + 2029 => x"2e", + 2030 => x"80", + 2031 => x"08", + 2032 => x"70", + 2033 => x"51", + 2034 => x"2e", + 2035 => x"c0", + 2036 => x"52", + 2037 => x"87", + 2038 => x"08", + 2039 => x"38", + 2040 => x"87", + 2041 => x"14", + 2042 => x"70", + 2043 => x"52", + 2044 => x"96", + 2045 => x"92", + 2046 => x"0a", + 2047 => x"39", + 2048 => x"0c", + 2049 => x"39", + 2050 => x"54", + 2051 => x"c0", + 2052 => x"0d", + 2053 => x"0d", + 2054 => x"33", + 2055 => x"88", + 2056 => x"de", + 2057 => x"51", + 2058 => x"04", + 2059 => x"75", + 2060 => x"82", + 2061 => x"90", + 2062 => x"2b", + 2063 => x"33", + 2064 => x"88", + 2065 => x"71", + 2066 => x"c0", + 2067 => x"54", + 2068 => x"85", + 2069 => x"ff", + 2070 => x"02", + 2071 => x"05", + 2072 => x"70", + 2073 => x"05", + 2074 => x"88", + 2075 => x"72", + 2076 => x"0d", + 2077 => x"0d", + 2078 => x"52", + 2079 => x"81", + 2080 => x"70", + 2081 => x"70", + 2082 => x"05", + 2083 => x"88", + 2084 => x"72", + 2085 => x"54", + 2086 => x"2a", + 2087 => x"34", + 2088 => x"04", + 2089 => x"76", + 2090 => x"54", + 2091 => x"2e", + 2092 => x"70", + 2093 => x"33", + 2094 => x"05", + 2095 => x"11", + 2096 => x"84", + 2097 => x"fe", + 2098 => x"77", + 2099 => x"53", + 2100 => x"81", + 2101 => x"ff", + 2102 => x"f4", + 2103 => x"0d", + 2104 => x"0d", + 2105 => x"56", + 2106 => x"70", + 2107 => x"33", + 2108 => x"05", + 2109 => x"71", + 2110 => x"56", + 2111 => x"72", + 2112 => x"38", + 2113 => x"e2", + 2114 => x"de", + 2115 => x"3d", + 2116 => x"3d", + 2117 => x"54", + 2118 => x"71", + 2119 => x"38", + 2120 => x"70", + 2121 => x"f3", + 2122 => x"81", + 2123 => x"84", + 2124 => x"80", + 2125 => x"c0", + 2126 => x"0b", + 2127 => x"0c", + 2128 => x"0d", + 2129 => x"0b", + 2130 => x"56", + 2131 => x"2e", + 2132 => x"81", + 2133 => x"08", + 2134 => x"70", + 2135 => x"33", + 2136 => x"a2", + 2137 => x"c0", + 2138 => x"09", + 2139 => x"38", + 2140 => x"08", + 2141 => x"b0", + 2142 => x"a4", + 2143 => x"9c", + 2144 => x"56", + 2145 => x"27", + 2146 => x"16", + 2147 => x"82", + 2148 => x"06", + 2149 => x"54", + 2150 => x"78", + 2151 => x"33", + 2152 => x"3f", + 2153 => x"5a", + 2154 => x"c0", + 2155 => x"0d", + 2156 => x"0d", + 2157 => x"56", + 2158 => x"b0", + 2159 => x"af", + 2160 => x"fe", + 2161 => x"de", + 2162 => x"81", + 2163 => x"9f", + 2164 => x"74", + 2165 => x"52", + 2166 => x"51", + 2167 => x"81", + 2168 => x"80", + 2169 => x"ff", + 2170 => x"74", + 2171 => x"76", + 2172 => x"0c", + 2173 => x"04", + 2174 => x"7a", + 2175 => x"fe", + 2176 => x"de", + 2177 => x"81", + 2178 => x"81", + 2179 => x"33", + 2180 => x"2e", + 2181 => x"80", + 2182 => x"17", + 2183 => x"81", + 2184 => x"06", + 2185 => x"84", + 2186 => x"de", + 2187 => x"b4", + 2188 => x"56", + 2189 => x"82", + 2190 => x"84", + 2191 => x"fc", + 2192 => x"8b", + 2193 => x"52", + 2194 => x"a9", + 2195 => x"85", + 2196 => x"84", + 2197 => x"fc", + 2198 => x"17", + 2199 => x"9c", + 2200 => x"91", + 2201 => x"08", + 2202 => x"17", + 2203 => x"3f", + 2204 => x"81", + 2205 => x"19", + 2206 => x"53", + 2207 => x"17", + 2208 => x"82", + 2209 => x"18", + 2210 => x"80", + 2211 => x"33", + 2212 => x"3f", + 2213 => x"08", + 2214 => x"38", + 2215 => x"81", + 2216 => x"8a", + 2217 => x"fb", + 2218 => x"fe", + 2219 => x"08", + 2220 => x"56", + 2221 => x"74", + 2222 => x"38", + 2223 => x"75", + 2224 => x"16", + 2225 => x"53", + 2226 => x"c0", + 2227 => x"0d", + 2228 => x"0d", + 2229 => x"08", + 2230 => x"81", + 2231 => x"df", + 2232 => x"15", + 2233 => x"d7", + 2234 => x"33", + 2235 => x"82", + 2236 => x"38", + 2237 => x"89", + 2238 => x"2e", + 2239 => x"bf", + 2240 => x"2e", + 2241 => x"81", + 2242 => x"81", + 2243 => x"89", + 2244 => x"08", + 2245 => x"52", + 2246 => x"3f", + 2247 => x"08", + 2248 => x"74", + 2249 => x"14", + 2250 => x"81", + 2251 => x"2a", + 2252 => x"05", + 2253 => x"57", + 2254 => x"f5", + 2255 => x"c0", + 2256 => x"38", + 2257 => x"06", + 2258 => x"33", + 2259 => x"78", + 2260 => x"06", + 2261 => x"5c", + 2262 => x"53", + 2263 => x"38", + 2264 => x"06", + 2265 => x"39", + 2266 => x"a4", + 2267 => x"52", + 2268 => x"bd", + 2269 => x"c0", + 2270 => x"38", + 2271 => x"fe", + 2272 => x"b4", + 2273 => x"8d", + 2274 => x"c0", + 2275 => x"ff", + 2276 => x"39", + 2277 => x"a4", + 2278 => x"52", + 2279 => x"91", + 2280 => x"c0", + 2281 => x"76", + 2282 => x"fc", + 2283 => x"b4", + 2284 => x"f8", + 2285 => x"c0", + 2286 => x"06", + 2287 => x"81", + 2288 => x"de", + 2289 => x"3d", + 2290 => x"3d", + 2291 => x"7e", + 2292 => x"82", + 2293 => x"27", + 2294 => x"76", + 2295 => x"27", + 2296 => x"75", + 2297 => x"79", + 2298 => x"38", + 2299 => x"89", + 2300 => x"2e", + 2301 => x"80", + 2302 => x"2e", + 2303 => x"81", + 2304 => x"81", + 2305 => x"89", + 2306 => x"08", + 2307 => x"52", + 2308 => x"3f", + 2309 => x"08", + 2310 => x"c0", + 2311 => x"38", + 2312 => x"06", + 2313 => x"81", + 2314 => x"06", + 2315 => x"77", + 2316 => x"2e", + 2317 => x"84", + 2318 => x"06", + 2319 => x"06", + 2320 => x"53", + 2321 => x"81", + 2322 => x"34", + 2323 => x"a4", + 2324 => x"52", + 2325 => x"d9", + 2326 => x"c0", + 2327 => x"de", + 2328 => x"94", + 2329 => x"ff", + 2330 => x"05", + 2331 => x"54", + 2332 => x"38", + 2333 => x"74", + 2334 => x"06", + 2335 => x"07", + 2336 => x"74", + 2337 => x"39", + 2338 => x"a4", + 2339 => x"52", + 2340 => x"9d", + 2341 => x"c0", + 2342 => x"de", + 2343 => x"d8", + 2344 => x"ff", + 2345 => x"76", + 2346 => x"06", + 2347 => x"05", + 2348 => x"3f", + 2349 => x"87", + 2350 => x"08", + 2351 => x"51", + 2352 => x"81", + 2353 => x"59", + 2354 => x"08", + 2355 => x"f0", + 2356 => x"82", + 2357 => x"06", + 2358 => x"05", + 2359 => x"54", + 2360 => x"3f", + 2361 => x"08", + 2362 => x"74", + 2363 => x"51", + 2364 => x"81", + 2365 => x"34", + 2366 => x"c0", + 2367 => x"0d", + 2368 => x"0d", + 2369 => x"72", + 2370 => x"56", + 2371 => x"27", + 2372 => x"98", + 2373 => x"9d", + 2374 => x"2e", + 2375 => x"53", + 2376 => x"51", + 2377 => x"81", + 2378 => x"54", + 2379 => x"08", + 2380 => x"93", + 2381 => x"80", + 2382 => x"54", + 2383 => x"81", + 2384 => x"54", + 2385 => x"74", + 2386 => x"fb", + 2387 => x"de", + 2388 => x"81", + 2389 => x"80", + 2390 => x"38", + 2391 => x"08", + 2392 => x"38", + 2393 => x"08", + 2394 => x"38", + 2395 => x"52", + 2396 => x"d6", + 2397 => x"c0", + 2398 => x"98", + 2399 => x"11", + 2400 => x"57", + 2401 => x"74", + 2402 => x"81", + 2403 => x"0c", + 2404 => x"81", + 2405 => x"84", + 2406 => x"55", + 2407 => x"ff", + 2408 => x"54", + 2409 => x"c0", + 2410 => x"0d", + 2411 => x"0d", + 2412 => x"08", + 2413 => x"79", + 2414 => x"17", + 2415 => x"80", + 2416 => x"98", + 2417 => x"26", + 2418 => x"58", + 2419 => x"52", + 2420 => x"fd", + 2421 => x"74", + 2422 => x"08", + 2423 => x"38", + 2424 => x"08", + 2425 => x"c0", + 2426 => x"82", + 2427 => x"17", + 2428 => x"c0", + 2429 => x"c7", + 2430 => x"90", + 2431 => x"56", + 2432 => x"2e", + 2433 => x"77", + 2434 => x"81", + 2435 => x"38", + 2436 => x"98", + 2437 => x"26", + 2438 => x"56", + 2439 => x"51", + 2440 => x"80", + 2441 => x"c0", + 2442 => x"09", + 2443 => x"38", + 2444 => x"08", + 2445 => x"c0", + 2446 => x"30", + 2447 => x"80", + 2448 => x"07", + 2449 => x"08", + 2450 => x"55", + 2451 => x"ef", + 2452 => x"c0", + 2453 => x"95", + 2454 => x"08", + 2455 => x"27", + 2456 => x"98", + 2457 => x"89", + 2458 => x"85", + 2459 => x"db", + 2460 => x"81", + 2461 => x"17", + 2462 => x"89", + 2463 => x"75", + 2464 => x"ac", + 2465 => x"7a", + 2466 => x"3f", + 2467 => x"08", + 2468 => x"38", + 2469 => x"de", + 2470 => x"2e", + 2471 => x"86", + 2472 => x"c0", + 2473 => x"de", + 2474 => x"70", + 2475 => x"07", + 2476 => x"7c", + 2477 => x"55", + 2478 => x"f8", + 2479 => x"2e", + 2480 => x"ff", + 2481 => x"55", + 2482 => x"ff", + 2483 => x"76", + 2484 => x"3f", + 2485 => x"08", + 2486 => x"08", + 2487 => x"de", + 2488 => x"80", + 2489 => x"55", + 2490 => x"94", + 2491 => x"2e", + 2492 => x"53", + 2493 => x"51", + 2494 => x"81", + 2495 => x"55", + 2496 => x"75", + 2497 => x"98", + 2498 => x"05", + 2499 => x"56", + 2500 => x"26", + 2501 => x"15", + 2502 => x"84", + 2503 => x"07", + 2504 => x"18", + 2505 => x"ff", + 2506 => x"2e", + 2507 => x"39", + 2508 => x"39", + 2509 => x"08", + 2510 => x"81", + 2511 => x"74", + 2512 => x"0c", + 2513 => x"04", + 2514 => x"7a", + 2515 => x"f3", + 2516 => x"de", + 2517 => x"81", + 2518 => x"c0", + 2519 => x"38", + 2520 => x"51", + 2521 => x"81", + 2522 => x"81", + 2523 => x"b0", + 2524 => x"84", + 2525 => x"52", + 2526 => x"52", + 2527 => x"3f", + 2528 => x"39", + 2529 => x"8a", + 2530 => x"75", + 2531 => x"38", + 2532 => x"19", + 2533 => x"81", + 2534 => x"ed", + 2535 => x"de", + 2536 => x"2e", + 2537 => x"15", + 2538 => x"70", + 2539 => x"07", + 2540 => x"53", + 2541 => x"75", + 2542 => x"0c", + 2543 => x"04", + 2544 => x"7a", + 2545 => x"58", + 2546 => x"f0", + 2547 => x"80", + 2548 => x"9f", + 2549 => x"80", + 2550 => x"90", + 2551 => x"17", + 2552 => x"aa", + 2553 => x"53", + 2554 => x"88", + 2555 => x"08", + 2556 => x"38", + 2557 => x"53", + 2558 => x"17", + 2559 => x"72", + 2560 => x"fe", + 2561 => x"08", + 2562 => x"80", + 2563 => x"16", + 2564 => x"2b", + 2565 => x"75", + 2566 => x"73", + 2567 => x"f5", + 2568 => x"de", + 2569 => x"81", + 2570 => x"ff", + 2571 => x"81", + 2572 => x"c0", + 2573 => x"38", + 2574 => x"81", + 2575 => x"26", + 2576 => x"58", + 2577 => x"73", + 2578 => x"39", + 2579 => x"51", + 2580 => x"81", + 2581 => x"98", + 2582 => x"94", + 2583 => x"17", + 2584 => x"58", + 2585 => x"9a", + 2586 => x"81", + 2587 => x"74", + 2588 => x"98", + 2589 => x"83", + 2590 => x"b4", + 2591 => x"0c", + 2592 => x"81", + 2593 => x"8a", + 2594 => x"f8", + 2595 => x"70", + 2596 => x"08", + 2597 => x"57", + 2598 => x"0a", + 2599 => x"38", + 2600 => x"15", + 2601 => x"08", + 2602 => x"72", + 2603 => x"cb", + 2604 => x"ff", + 2605 => x"81", + 2606 => x"13", + 2607 => x"94", + 2608 => x"74", + 2609 => x"85", + 2610 => x"22", + 2611 => x"73", + 2612 => x"38", + 2613 => x"8a", + 2614 => x"05", + 2615 => x"06", + 2616 => x"8a", + 2617 => x"73", + 2618 => x"3f", + 2619 => x"08", + 2620 => x"81", + 2621 => x"c0", + 2622 => x"ff", + 2623 => x"81", + 2624 => x"ff", + 2625 => x"38", + 2626 => x"81", + 2627 => x"26", + 2628 => x"7b", + 2629 => x"98", + 2630 => x"55", + 2631 => x"94", + 2632 => x"73", + 2633 => x"3f", + 2634 => x"08", + 2635 => x"81", + 2636 => x"80", + 2637 => x"38", + 2638 => x"de", + 2639 => x"2e", + 2640 => x"55", + 2641 => x"08", + 2642 => x"38", + 2643 => x"08", + 2644 => x"fb", + 2645 => x"de", + 2646 => x"38", + 2647 => x"0c", + 2648 => x"51", + 2649 => x"81", + 2650 => x"98", + 2651 => x"90", + 2652 => x"16", + 2653 => x"15", + 2654 => x"74", + 2655 => x"0c", + 2656 => x"04", + 2657 => x"7b", + 2658 => x"5b", + 2659 => x"52", + 2660 => x"ac", + 2661 => x"c0", + 2662 => x"de", + 2663 => x"ec", + 2664 => x"c0", + 2665 => x"17", + 2666 => x"51", + 2667 => x"81", + 2668 => x"54", + 2669 => x"08", + 2670 => x"81", + 2671 => x"9c", + 2672 => x"33", + 2673 => x"72", + 2674 => x"09", + 2675 => x"38", + 2676 => x"de", + 2677 => x"72", + 2678 => x"55", + 2679 => x"53", + 2680 => x"8e", + 2681 => x"56", + 2682 => x"09", + 2683 => x"38", + 2684 => x"de", + 2685 => x"81", + 2686 => x"fd", + 2687 => x"de", + 2688 => x"81", + 2689 => x"80", + 2690 => x"38", + 2691 => x"09", + 2692 => x"38", + 2693 => x"81", + 2694 => x"8b", + 2695 => x"fd", + 2696 => x"9a", + 2697 => x"eb", + 2698 => x"de", + 2699 => x"ff", + 2700 => x"70", + 2701 => x"53", + 2702 => x"09", + 2703 => x"38", + 2704 => x"eb", + 2705 => x"de", + 2706 => x"2b", + 2707 => x"72", + 2708 => x"0c", + 2709 => x"04", + 2710 => x"77", + 2711 => x"ff", + 2712 => x"9a", + 2713 => x"55", + 2714 => x"76", + 2715 => x"53", + 2716 => x"09", + 2717 => x"38", + 2718 => x"52", + 2719 => x"eb", + 2720 => x"3d", + 2721 => x"3d", + 2722 => x"5b", + 2723 => x"08", + 2724 => x"15", + 2725 => x"81", + 2726 => x"15", + 2727 => x"51", + 2728 => x"81", + 2729 => x"58", + 2730 => x"08", + 2731 => x"9c", + 2732 => x"33", + 2733 => x"86", + 2734 => x"80", + 2735 => x"13", + 2736 => x"06", + 2737 => x"06", + 2738 => x"72", + 2739 => x"81", + 2740 => x"53", + 2741 => x"2e", + 2742 => x"53", + 2743 => x"a9", + 2744 => x"74", + 2745 => x"72", + 2746 => x"38", + 2747 => x"99", + 2748 => x"c0", + 2749 => x"06", + 2750 => x"88", + 2751 => x"06", + 2752 => x"54", + 2753 => x"a0", + 2754 => x"74", + 2755 => x"3f", + 2756 => x"08", + 2757 => x"c0", + 2758 => x"98", + 2759 => x"fa", + 2760 => x"80", + 2761 => x"0c", + 2762 => x"c0", + 2763 => x"0d", + 2764 => x"0d", + 2765 => x"57", + 2766 => x"73", + 2767 => x"3f", + 2768 => x"08", + 2769 => x"c0", + 2770 => x"98", + 2771 => x"75", + 2772 => x"3f", + 2773 => x"08", + 2774 => x"c0", + 2775 => x"a0", + 2776 => x"c0", + 2777 => x"14", + 2778 => x"db", + 2779 => x"a0", + 2780 => x"14", + 2781 => x"ac", + 2782 => x"83", + 2783 => x"81", + 2784 => x"87", + 2785 => x"fd", + 2786 => x"70", + 2787 => x"08", + 2788 => x"55", + 2789 => x"3f", + 2790 => x"08", + 2791 => x"13", + 2792 => x"73", + 2793 => x"83", + 2794 => x"3d", + 2795 => x"3d", + 2796 => x"57", + 2797 => x"89", + 2798 => x"17", + 2799 => x"81", + 2800 => x"70", + 2801 => x"55", + 2802 => x"08", + 2803 => x"81", + 2804 => x"52", + 2805 => x"a8", + 2806 => x"2e", + 2807 => x"84", + 2808 => x"52", + 2809 => x"09", + 2810 => x"38", + 2811 => x"81", + 2812 => x"81", + 2813 => x"73", + 2814 => x"55", + 2815 => x"55", + 2816 => x"c5", + 2817 => x"88", + 2818 => x"0b", + 2819 => x"9c", + 2820 => x"8b", + 2821 => x"17", + 2822 => x"08", + 2823 => x"52", + 2824 => x"81", + 2825 => x"76", + 2826 => x"51", + 2827 => x"81", + 2828 => x"86", + 2829 => x"12", + 2830 => x"3f", + 2831 => x"08", + 2832 => x"88", + 2833 => x"f3", + 2834 => x"70", + 2835 => x"80", + 2836 => x"51", + 2837 => x"af", + 2838 => x"81", + 2839 => x"dc", + 2840 => x"74", + 2841 => x"38", + 2842 => x"88", + 2843 => x"39", + 2844 => x"80", + 2845 => x"56", + 2846 => x"af", + 2847 => x"06", + 2848 => x"56", + 2849 => x"32", + 2850 => x"80", + 2851 => x"51", + 2852 => x"dc", + 2853 => x"1c", + 2854 => x"33", + 2855 => x"9f", + 2856 => x"ff", + 2857 => x"1c", + 2858 => x"7a", + 2859 => x"3f", + 2860 => x"08", + 2861 => x"39", + 2862 => x"a0", + 2863 => x"5e", + 2864 => x"52", + 2865 => x"ff", + 2866 => x"59", + 2867 => x"33", + 2868 => x"ae", + 2869 => x"06", + 2870 => x"78", + 2871 => x"81", + 2872 => x"32", + 2873 => x"9f", + 2874 => x"26", + 2875 => x"53", + 2876 => x"73", + 2877 => x"17", + 2878 => x"34", + 2879 => x"db", + 2880 => x"32", + 2881 => x"9f", + 2882 => x"54", + 2883 => x"2e", + 2884 => x"80", + 2885 => x"75", + 2886 => x"bd", + 2887 => x"7e", + 2888 => x"a0", + 2889 => x"bd", + 2890 => x"82", + 2891 => x"18", + 2892 => x"1a", + 2893 => x"a0", + 2894 => x"fc", + 2895 => x"32", + 2896 => x"80", + 2897 => x"30", + 2898 => x"71", + 2899 => x"51", + 2900 => x"55", + 2901 => x"ac", + 2902 => x"81", + 2903 => x"78", + 2904 => x"51", + 2905 => x"af", + 2906 => x"06", + 2907 => x"55", + 2908 => x"32", + 2909 => x"80", + 2910 => x"51", + 2911 => x"db", + 2912 => x"39", + 2913 => x"09", + 2914 => x"38", + 2915 => x"7c", + 2916 => x"54", + 2917 => x"a2", + 2918 => x"32", + 2919 => x"ae", + 2920 => x"72", + 2921 => x"9f", + 2922 => x"51", + 2923 => x"74", + 2924 => x"88", + 2925 => x"fe", + 2926 => x"98", + 2927 => x"80", + 2928 => x"75", + 2929 => x"81", + 2930 => x"33", + 2931 => x"51", + 2932 => x"81", + 2933 => x"80", + 2934 => x"78", + 2935 => x"81", + 2936 => x"5a", + 2937 => x"d2", + 2938 => x"c0", + 2939 => x"80", + 2940 => x"1c", + 2941 => x"27", + 2942 => x"79", + 2943 => x"74", + 2944 => x"7a", + 2945 => x"74", + 2946 => x"39", + 2947 => x"cc", + 2948 => x"fe", + 2949 => x"c0", + 2950 => x"ff", + 2951 => x"73", + 2952 => x"38", + 2953 => x"81", + 2954 => x"54", + 2955 => x"75", + 2956 => x"17", + 2957 => x"39", + 2958 => x"0c", + 2959 => x"99", + 2960 => x"54", + 2961 => x"2e", + 2962 => x"84", + 2963 => x"34", + 2964 => x"76", + 2965 => x"8b", + 2966 => x"81", + 2967 => x"56", + 2968 => x"80", + 2969 => x"1b", + 2970 => x"08", + 2971 => x"51", + 2972 => x"81", + 2973 => x"56", + 2974 => x"08", + 2975 => x"98", + 2976 => x"76", + 2977 => x"3f", + 2978 => x"08", + 2979 => x"c0", + 2980 => x"38", + 2981 => x"70", + 2982 => x"73", + 2983 => x"be", + 2984 => x"33", + 2985 => x"73", + 2986 => x"8b", + 2987 => x"83", + 2988 => x"06", + 2989 => x"73", + 2990 => x"53", + 2991 => x"51", + 2992 => x"81", + 2993 => x"80", + 2994 => x"75", + 2995 => x"f3", + 2996 => x"9f", + 2997 => x"1c", + 2998 => x"74", + 2999 => x"38", + 3000 => x"09", + 3001 => x"e7", + 3002 => x"2a", + 3003 => x"77", + 3004 => x"51", + 3005 => x"2e", + 3006 => x"81", + 3007 => x"80", + 3008 => x"38", + 3009 => x"ab", + 3010 => x"55", + 3011 => x"75", + 3012 => x"73", + 3013 => x"55", + 3014 => x"82", + 3015 => x"06", + 3016 => x"ab", + 3017 => x"33", + 3018 => x"70", + 3019 => x"55", + 3020 => x"2e", + 3021 => x"1b", + 3022 => x"06", + 3023 => x"52", + 3024 => x"db", + 3025 => x"c0", + 3026 => x"0c", + 3027 => x"74", + 3028 => x"0c", + 3029 => x"04", + 3030 => x"7c", + 3031 => x"08", + 3032 => x"55", + 3033 => x"59", + 3034 => x"81", + 3035 => x"70", + 3036 => x"33", + 3037 => x"52", + 3038 => x"2e", + 3039 => x"ee", + 3040 => x"2e", + 3041 => x"81", + 3042 => x"33", + 3043 => x"81", + 3044 => x"52", + 3045 => x"26", + 3046 => x"14", + 3047 => x"06", + 3048 => x"52", + 3049 => x"80", + 3050 => x"0b", + 3051 => x"59", + 3052 => x"7a", + 3053 => x"70", + 3054 => x"33", + 3055 => x"05", + 3056 => x"9f", + 3057 => x"53", + 3058 => x"89", + 3059 => x"70", + 3060 => x"54", + 3061 => x"12", + 3062 => x"26", + 3063 => x"12", + 3064 => x"06", + 3065 => x"30", + 3066 => x"51", + 3067 => x"2e", + 3068 => x"85", + 3069 => x"be", + 3070 => x"74", + 3071 => x"30", + 3072 => x"9f", + 3073 => x"2a", + 3074 => x"54", + 3075 => x"2e", + 3076 => x"15", + 3077 => x"55", + 3078 => x"ff", + 3079 => x"39", + 3080 => x"86", + 3081 => x"7c", + 3082 => x"51", + 3083 => x"de", + 3084 => x"70", + 3085 => x"0c", + 3086 => x"04", + 3087 => x"78", + 3088 => x"83", + 3089 => x"0b", + 3090 => x"79", + 3091 => x"e2", + 3092 => x"55", + 3093 => x"08", + 3094 => x"84", + 3095 => x"df", + 3096 => x"de", + 3097 => x"ff", + 3098 => x"83", + 3099 => x"d4", + 3100 => x"81", + 3101 => x"38", + 3102 => x"17", + 3103 => x"74", + 3104 => x"09", + 3105 => x"38", + 3106 => x"81", + 3107 => x"30", + 3108 => x"79", + 3109 => x"54", + 3110 => x"74", + 3111 => x"09", + 3112 => x"38", + 3113 => x"cc", + 3114 => x"ea", + 3115 => x"b1", + 3116 => x"c0", + 3117 => x"de", + 3118 => x"2e", + 3119 => x"53", + 3120 => x"52", + 3121 => x"51", + 3122 => x"81", + 3123 => x"55", + 3124 => x"08", + 3125 => x"38", + 3126 => x"81", + 3127 => x"88", + 3128 => x"f2", + 3129 => x"02", + 3130 => x"cb", + 3131 => x"55", + 3132 => x"60", + 3133 => x"3f", + 3134 => x"08", + 3135 => x"80", + 3136 => x"c0", + 3137 => x"fc", + 3138 => x"c0", + 3139 => x"81", + 3140 => x"70", + 3141 => x"8c", + 3142 => x"2e", + 3143 => x"73", + 3144 => x"81", + 3145 => x"33", + 3146 => x"80", + 3147 => x"81", + 3148 => x"d7", + 3149 => x"de", + 3150 => x"ff", + 3151 => x"06", + 3152 => x"98", + 3153 => x"2e", + 3154 => x"74", + 3155 => x"81", + 3156 => x"8a", + 3157 => x"ac", + 3158 => x"39", + 3159 => x"77", + 3160 => x"81", + 3161 => x"33", + 3162 => x"3f", + 3163 => x"08", + 3164 => x"70", + 3165 => x"55", + 3166 => x"86", + 3167 => x"80", + 3168 => x"74", + 3169 => x"81", + 3170 => x"8a", + 3171 => x"f4", + 3172 => x"53", + 3173 => x"fd", + 3174 => x"de", + 3175 => x"ff", + 3176 => x"82", + 3177 => x"06", + 3178 => x"8c", + 3179 => x"58", + 3180 => x"f6", + 3181 => x"58", + 3182 => x"2e", + 3183 => x"fa", + 3184 => x"e8", + 3185 => x"c0", + 3186 => x"78", + 3187 => x"5a", + 3188 => x"90", + 3189 => x"75", + 3190 => x"38", + 3191 => x"3d", + 3192 => x"70", + 3193 => x"08", + 3194 => x"7a", + 3195 => x"38", + 3196 => x"51", + 3197 => x"81", + 3198 => x"81", + 3199 => x"81", + 3200 => x"38", + 3201 => x"83", + 3202 => x"38", + 3203 => x"84", + 3204 => x"38", + 3205 => x"81", + 3206 => x"38", + 3207 => x"db", + 3208 => x"de", + 3209 => x"ff", + 3210 => x"72", + 3211 => x"09", + 3212 => x"d0", + 3213 => x"14", + 3214 => x"3f", + 3215 => x"08", + 3216 => x"06", + 3217 => x"38", + 3218 => x"51", + 3219 => x"81", + 3220 => x"58", + 3221 => x"0c", + 3222 => x"33", + 3223 => x"80", + 3224 => x"ff", + 3225 => x"ff", + 3226 => x"55", + 3227 => x"81", + 3228 => x"38", + 3229 => x"06", + 3230 => x"80", + 3231 => x"52", + 3232 => x"8a", + 3233 => x"80", + 3234 => x"ff", + 3235 => x"53", + 3236 => x"86", + 3237 => x"83", + 3238 => x"c5", + 3239 => x"f5", + 3240 => x"c0", + 3241 => x"de", + 3242 => x"15", + 3243 => x"06", + 3244 => x"76", + 3245 => x"80", + 3246 => x"da", + 3247 => x"de", + 3248 => x"ff", + 3249 => x"74", + 3250 => x"d4", + 3251 => x"dc", + 3252 => x"c0", + 3253 => x"c2", + 3254 => x"b9", + 3255 => x"c0", + 3256 => x"ff", + 3257 => x"56", + 3258 => x"83", + 3259 => x"14", + 3260 => x"71", + 3261 => x"5a", + 3262 => x"26", + 3263 => x"8a", + 3264 => x"74", + 3265 => x"ff", + 3266 => x"81", + 3267 => x"55", + 3268 => x"08", + 3269 => x"ec", + 3270 => x"c0", + 3271 => x"ff", + 3272 => x"83", + 3273 => x"74", + 3274 => x"26", + 3275 => x"57", + 3276 => x"26", + 3277 => x"57", + 3278 => x"56", + 3279 => x"82", + 3280 => x"15", + 3281 => x"0c", + 3282 => x"0c", + 3283 => x"a4", + 3284 => x"1d", + 3285 => x"54", + 3286 => x"2e", + 3287 => x"af", + 3288 => x"14", + 3289 => x"3f", + 3290 => x"08", + 3291 => x"06", + 3292 => x"72", + 3293 => x"79", + 3294 => x"80", + 3295 => x"d9", + 3296 => x"de", + 3297 => x"15", + 3298 => x"2b", + 3299 => x"8d", + 3300 => x"2e", + 3301 => x"77", + 3302 => x"0c", + 3303 => x"76", + 3304 => x"38", + 3305 => x"70", + 3306 => x"81", + 3307 => x"53", + 3308 => x"89", + 3309 => x"56", + 3310 => x"08", + 3311 => x"38", + 3312 => x"15", + 3313 => x"8c", + 3314 => x"80", + 3315 => x"34", + 3316 => x"09", + 3317 => x"92", + 3318 => x"14", + 3319 => x"3f", + 3320 => x"08", + 3321 => x"06", + 3322 => x"2e", + 3323 => x"80", + 3324 => x"1b", + 3325 => x"db", + 3326 => x"de", + 3327 => x"ea", + 3328 => x"c0", + 3329 => x"34", + 3330 => x"51", + 3331 => x"81", + 3332 => x"83", + 3333 => x"53", + 3334 => x"d5", + 3335 => x"06", + 3336 => x"b4", + 3337 => x"84", + 3338 => x"c0", + 3339 => x"85", + 3340 => x"09", + 3341 => x"38", + 3342 => x"51", + 3343 => x"81", + 3344 => x"86", + 3345 => x"f2", + 3346 => x"06", + 3347 => x"9c", + 3348 => x"d8", + 3349 => x"c0", + 3350 => x"0c", + 3351 => x"51", + 3352 => x"81", + 3353 => x"8c", + 3354 => x"74", + 3355 => x"ec", + 3356 => x"53", + 3357 => x"ec", + 3358 => x"15", + 3359 => x"94", + 3360 => x"56", + 3361 => x"c0", + 3362 => x"0d", + 3363 => x"0d", + 3364 => x"55", + 3365 => x"b9", + 3366 => x"53", + 3367 => x"b1", + 3368 => x"52", + 3369 => x"a9", + 3370 => x"22", + 3371 => x"57", + 3372 => x"2e", + 3373 => x"99", + 3374 => x"33", + 3375 => x"3f", + 3376 => x"08", + 3377 => x"71", + 3378 => x"74", + 3379 => x"83", + 3380 => x"78", + 3381 => x"52", + 3382 => x"c0", + 3383 => x"0d", + 3384 => x"0d", + 3385 => x"33", + 3386 => x"3d", + 3387 => x"56", + 3388 => x"8b", + 3389 => x"81", + 3390 => x"24", + 3391 => x"de", + 3392 => x"29", + 3393 => x"05", + 3394 => x"55", + 3395 => x"84", + 3396 => x"34", + 3397 => x"80", + 3398 => x"80", + 3399 => x"75", + 3400 => x"75", + 3401 => x"38", + 3402 => x"3d", + 3403 => x"05", + 3404 => x"3f", + 3405 => x"08", + 3406 => x"de", + 3407 => x"3d", + 3408 => x"3d", + 3409 => x"84", + 3410 => x"05", + 3411 => x"89", + 3412 => x"2e", + 3413 => x"77", + 3414 => x"54", + 3415 => x"05", + 3416 => x"84", + 3417 => x"f6", + 3418 => x"de", + 3419 => x"81", + 3420 => x"84", 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x"06", + 3480 => x"73", + 3481 => x"38", + 3482 => x"ad", + 3483 => x"2a", + 3484 => x"51", + 3485 => x"2e", + 3486 => x"81", + 3487 => x"80", + 3488 => x"87", + 3489 => x"39", + 3490 => x"51", + 3491 => x"81", + 3492 => x"7b", + 3493 => x"12", + 3494 => x"81", + 3495 => x"81", + 3496 => x"83", + 3497 => x"06", + 3498 => x"80", + 3499 => x"77", + 3500 => x"58", + 3501 => x"08", + 3502 => x"63", + 3503 => x"63", + 3504 => x"57", + 3505 => x"81", + 3506 => x"81", + 3507 => x"88", + 3508 => x"9c", + 3509 => x"d2", + 3510 => x"de", + 3511 => x"de", + 3512 => x"1b", + 3513 => x"0c", + 3514 => x"22", + 3515 => x"77", + 3516 => x"80", + 3517 => x"34", + 3518 => x"1a", + 3519 => x"94", + 3520 => x"85", + 3521 => x"06", + 3522 => x"80", + 3523 => x"38", + 3524 => x"08", + 3525 => x"84", + 3526 => x"c0", + 3527 => x"0c", + 3528 => x"70", + 3529 => x"52", + 3530 => x"39", + 3531 => x"51", + 3532 => x"81", + 3533 => x"57", + 3534 => x"08", + 3535 => x"38", + 3536 => x"de", + 3537 => x"2e", + 3538 => x"83", + 3539 => x"75", + 3540 => x"74", + 3541 => x"07", + 3542 => x"54", + 3543 => x"8a", + 3544 => x"75", + 3545 => x"73", + 3546 => x"98", + 3547 => x"a9", + 3548 => x"ff", + 3549 => x"80", + 3550 => x"76", + 3551 => x"d6", + 3552 => x"de", + 3553 => x"38", + 3554 => x"39", + 3555 => x"81", + 3556 => x"05", + 3557 => x"84", + 3558 => x"0c", + 3559 => x"81", + 3560 => x"97", + 3561 => x"f2", + 3562 => x"63", + 3563 => x"40", + 3564 => x"7e", + 3565 => x"fc", + 3566 => x"51", + 3567 => x"81", + 3568 => x"55", + 3569 => x"08", + 3570 => x"19", + 3571 => x"80", + 3572 => x"74", + 3573 => x"39", + 3574 => x"81", + 3575 => x"56", + 3576 => x"82", + 3577 => x"39", + 3578 => x"1a", + 3579 => x"82", + 3580 => x"0b", + 3581 => x"81", + 3582 => x"39", + 3583 => x"94", + 3584 => x"55", + 3585 => x"83", + 3586 => x"7b", + 3587 => x"89", + 3588 => x"08", + 3589 => x"06", + 3590 => x"81", + 3591 => x"8a", + 3592 => x"05", + 3593 => x"06", + 3594 => x"a8", + 3595 => x"38", + 3596 => x"55", + 3597 => x"19", + 3598 => x"51", + 3599 => x"81", + 3600 => x"55", + 3601 => x"ff", + 3602 => x"ff", + 3603 => x"38", + 3604 => x"0c", + 3605 => x"52", + 3606 => x"cb", + 3607 => x"c0", + 3608 => x"ff", + 3609 => x"de", + 3610 => x"7c", + 3611 => x"57", + 3612 => x"80", + 3613 => x"1a", + 3614 => x"22", + 3615 => x"75", + 3616 => x"38", + 3617 => x"58", + 3618 => x"53", + 3619 => x"1b", + 3620 => x"88", + 3621 => x"c0", + 3622 => x"38", + 3623 => x"33", + 3624 => x"80", + 3625 => x"b0", + 3626 => x"31", + 3627 => x"27", + 3628 => x"80", + 3629 => x"52", + 3630 => x"77", + 3631 => x"7d", + 3632 => x"e0", + 3633 => x"2b", + 3634 => x"76", + 3635 => x"94", + 3636 => x"ff", + 3637 => x"71", + 3638 => x"7b", + 3639 => x"38", + 3640 => x"19", + 3641 => x"51", + 3642 => x"81", + 3643 => x"fe", + 3644 => x"53", + 3645 => x"83", + 3646 => x"b4", + 3647 => x"51", + 3648 => x"7b", + 3649 => x"08", + 3650 => x"76", + 3651 => x"08", + 3652 => x"0c", + 3653 => x"f3", + 3654 => x"75", + 3655 => x"0c", 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x"52", + 3715 => x"97", + 3716 => x"c0", + 3717 => x"fe", + 3718 => x"de", + 3719 => x"7c", + 3720 => x"57", + 3721 => x"80", + 3722 => x"1b", + 3723 => x"22", + 3724 => x"75", + 3725 => x"38", + 3726 => x"59", + 3727 => x"53", + 3728 => x"1a", + 3729 => x"be", + 3730 => x"c0", + 3731 => x"38", + 3732 => x"08", + 3733 => x"56", + 3734 => x"9b", + 3735 => x"53", + 3736 => x"77", + 3737 => x"7d", + 3738 => x"16", + 3739 => x"3f", + 3740 => x"0b", + 3741 => x"78", + 3742 => x"80", + 3743 => x"18", + 3744 => x"08", + 3745 => x"7e", + 3746 => x"3f", + 3747 => x"08", + 3748 => x"7e", + 3749 => x"0c", + 3750 => x"19", + 3751 => x"08", + 3752 => x"84", + 3753 => x"57", + 3754 => x"27", + 3755 => x"56", + 3756 => x"52", + 3757 => x"f9", + 3758 => x"c0", + 3759 => x"38", + 3760 => x"52", + 3761 => x"83", + 3762 => x"b4", + 3763 => x"d4", + 3764 => x"81", + 3765 => x"34", + 3766 => x"7e", + 3767 => x"0c", + 3768 => x"1a", + 3769 => x"94", + 3770 => x"1b", + 3771 => x"5e", + 3772 => x"27", + 3773 => x"55", + 3774 => x"0c", + 3775 => x"90", + 3776 => x"c0", + 3777 => x"90", + 3778 => x"56", + 3779 => x"c0", + 3780 => x"0d", + 3781 => x"0d", + 3782 => x"fc", + 3783 => x"52", + 3784 => x"3f", + 3785 => x"08", + 3786 => x"c0", + 3787 => x"38", + 3788 => x"70", + 3789 => x"81", + 3790 => x"55", + 3791 => x"80", + 3792 => x"16", + 3793 => x"51", + 3794 => x"81", + 3795 => x"57", + 3796 => x"08", + 3797 => x"a4", + 3798 => x"11", + 3799 => x"55", + 3800 => x"16", + 3801 => x"08", + 3802 => x"75", + 3803 => x"e8", + 3804 => x"08", + 3805 => x"51", + 3806 => x"82", + 3807 => x"52", + 3808 => x"c9", + 3809 => x"52", + 3810 => x"c9", + 3811 => x"54", + 3812 => x"15", + 3813 => x"cc", + 3814 => x"de", + 3815 => x"17", + 3816 => x"06", + 3817 => x"90", + 3818 => x"81", + 3819 => x"8a", + 3820 => x"fc", + 3821 => x"70", + 3822 => x"d9", + 3823 => x"c0", + 3824 => x"de", + 3825 => x"38", + 3826 => x"05", + 3827 => x"f1", + 3828 => x"de", + 3829 => x"81", + 3830 => x"87", + 3831 => x"c0", + 3832 => x"72", + 3833 => x"0c", + 3834 => x"04", + 3835 => x"84", + 3836 => x"e4", + 3837 => x"80", + 3838 => x"c0", + 3839 => x"38", + 3840 => x"08", + 3841 => x"34", + 3842 => x"81", + 3843 => x"83", + 3844 => x"ef", + 3845 => x"53", + 3846 => x"05", + 3847 => x"51", + 3848 => x"81", + 3849 => x"55", + 3850 => x"08", + 3851 => x"76", + 3852 => x"93", + 3853 => x"51", + 3854 => x"81", + 3855 => x"55", + 3856 => x"08", + 3857 => x"80", + 3858 => x"70", + 3859 => x"56", + 3860 => x"89", + 3861 => x"94", + 3862 => x"b2", + 3863 => x"05", + 3864 => x"2a", + 3865 => x"51", + 3866 => x"80", + 3867 => x"76", + 3868 => x"52", + 3869 => x"3f", + 3870 => x"08", + 3871 => x"8e", + 3872 => x"c0", + 3873 => x"09", + 3874 => x"38", + 3875 => x"81", + 3876 => x"93", + 3877 => x"e4", + 3878 => x"6f", + 3879 => x"7a", + 3880 => x"9e", + 3881 => x"05", + 3882 => x"51", + 3883 => x"81", + 3884 => x"57", + 3885 => x"08", + 3886 => x"7b", + 3887 => x"94", + 3888 => x"55", + 3889 => x"73", + 3890 => x"ed", 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x"8d", + 3950 => x"2e", + 3951 => x"8a", + 3952 => x"6f", + 3953 => x"af", + 3954 => x"0b", + 3955 => x"33", + 3956 => x"81", + 3957 => x"70", + 3958 => x"52", + 3959 => x"56", + 3960 => x"8d", + 3961 => x"70", + 3962 => x"51", + 3963 => x"f5", + 3964 => x"54", + 3965 => x"a7", + 3966 => x"74", + 3967 => x"38", + 3968 => x"73", + 3969 => x"81", + 3970 => x"81", + 3971 => x"39", + 3972 => x"81", + 3973 => x"74", + 3974 => x"81", + 3975 => x"91", + 3976 => x"6e", + 3977 => x"59", + 3978 => x"7a", + 3979 => x"5c", + 3980 => x"26", + 3981 => x"7a", + 3982 => x"de", + 3983 => x"3d", + 3984 => x"3d", + 3985 => x"8d", + 3986 => x"54", + 3987 => x"55", + 3988 => x"81", + 3989 => x"53", + 3990 => x"08", + 3991 => x"91", + 3992 => x"72", + 3993 => x"8c", + 3994 => x"73", + 3995 => x"38", + 3996 => x"70", + 3997 => x"81", + 3998 => x"57", + 3999 => x"73", + 4000 => x"08", + 4001 => x"94", + 4002 => x"75", + 4003 => x"97", + 4004 => x"11", + 4005 => x"2b", + 4006 => x"73", + 4007 => x"38", + 4008 => x"16", + 4009 => x"d2", + 4010 => x"c0", + 4011 => x"78", + 4012 => x"55", + 4013 => x"c2", + 4014 => x"c0", + 4015 => x"96", + 4016 => x"70", + 4017 => x"94", + 4018 => x"71", + 4019 => x"08", + 4020 => x"53", + 4021 => x"15", + 4022 => x"a6", + 4023 => x"74", + 4024 => x"3f", + 4025 => x"08", + 4026 => x"c0", + 4027 => x"81", + 4028 => x"de", + 4029 => x"2e", + 4030 => x"81", + 4031 => x"88", + 4032 => x"98", + 4033 => x"80", + 4034 => x"38", + 4035 => x"80", + 4036 => x"77", + 4037 => x"08", + 4038 => x"0c", + 4039 => x"70", + 4040 => x"81", + 4041 => x"5a", + 4042 => x"2e", + 4043 => x"52", + 4044 => x"f9", + 4045 => x"c0", + 4046 => x"de", + 4047 => x"38", + 4048 => x"08", + 4049 => x"73", + 4050 => x"c7", + 4051 => x"de", + 4052 => x"73", + 4053 => x"38", + 4054 => x"af", + 4055 => x"73", + 4056 => x"27", + 4057 => x"98", + 4058 => x"a0", + 4059 => x"08", + 4060 => x"0c", + 4061 => x"06", + 4062 => x"2e", + 4063 => x"52", + 4064 => x"a3", + 4065 => x"c0", + 4066 => x"82", + 4067 => x"34", + 4068 => x"c4", + 4069 => x"91", + 4070 => x"53", + 4071 => x"89", + 4072 => x"c0", + 4073 => x"94", + 4074 => x"8c", + 4075 => x"27", + 4076 => x"8c", + 4077 => x"15", + 4078 => x"07", + 4079 => x"16", + 4080 => x"ff", + 4081 => x"80", + 4082 => x"77", + 4083 => x"2e", + 4084 => x"9c", + 4085 => x"53", + 4086 => x"c0", + 4087 => x"0d", + 4088 => x"0d", + 4089 => x"54", + 4090 => x"81", + 4091 => x"53", + 4092 => x"05", + 4093 => x"84", + 4094 => x"e7", + 4095 => x"c0", + 4096 => x"de", + 4097 => x"ea", + 4098 => x"0c", + 4099 => x"51", + 4100 => x"81", + 4101 => x"55", + 4102 => x"08", + 4103 => x"ab", + 4104 => x"98", + 4105 => x"80", + 4106 => x"38", + 4107 => x"70", + 4108 => x"81", + 4109 => x"57", + 4110 => x"ad", + 4111 => x"08", + 4112 => x"d3", + 4113 => x"de", + 4114 => x"17", + 4115 => x"86", + 4116 => x"17", + 4117 => x"75", + 4118 => x"3f", + 4119 => x"08", + 4120 => x"2e", + 4121 => x"85", + 4122 => x"86", + 4123 => x"2e", + 4124 => x"76", + 4125 => x"73", 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x"8d", + 4185 => x"2e", + 4186 => x"52", + 4187 => x"be", + 4188 => x"de", + 4189 => x"3d", + 4190 => x"3d", + 4191 => x"55", + 4192 => x"92", + 4193 => x"52", + 4194 => x"de", + 4195 => x"de", + 4196 => x"81", + 4197 => x"82", + 4198 => x"74", + 4199 => x"98", + 4200 => x"11", + 4201 => x"59", + 4202 => x"75", + 4203 => x"38", + 4204 => x"81", + 4205 => x"5b", + 4206 => x"82", + 4207 => x"39", + 4208 => x"08", + 4209 => x"59", + 4210 => x"09", + 4211 => x"38", + 4212 => x"57", + 4213 => x"3d", + 4214 => x"c1", + 4215 => x"de", + 4216 => x"2e", + 4217 => x"de", + 4218 => x"2e", + 4219 => x"de", + 4220 => x"70", + 4221 => x"08", + 4222 => x"7a", + 4223 => x"7f", + 4224 => x"54", + 4225 => x"77", + 4226 => x"80", + 4227 => x"15", + 4228 => x"c0", + 4229 => x"75", + 4230 => x"52", + 4231 => x"52", + 4232 => x"8d", + 4233 => x"c0", + 4234 => x"de", + 4235 => x"d6", + 4236 => x"33", + 4237 => x"1a", + 4238 => x"54", + 4239 => x"09", + 4240 => x"38", + 4241 => x"ff", + 4242 => x"81", + 4243 => x"83", + 4244 => x"70", + 4245 => x"25", + 4246 => x"59", + 4247 => x"9b", + 4248 => x"51", + 4249 => x"3f", + 4250 => x"08", + 4251 => x"70", + 4252 => x"25", + 4253 => x"59", + 4254 => x"75", + 4255 => x"7a", + 4256 => x"ff", + 4257 => x"7c", + 4258 => x"90", + 4259 => x"11", + 4260 => x"56", + 4261 => x"15", + 4262 => x"de", + 4263 => x"3d", + 4264 => x"3d", + 4265 => x"3d", + 4266 => x"70", + 4267 => x"dd", + 4268 => x"c0", + 4269 => x"de", + 4270 => x"a8", + 4271 => x"33", + 4272 => x"a0", + 4273 => x"33", + 4274 => x"70", + 4275 => x"55", + 4276 => x"73", + 4277 => x"8e", + 4278 => x"08", + 4279 => x"18", + 4280 => x"80", + 4281 => x"38", + 4282 => x"08", + 4283 => x"08", + 4284 => x"c4", + 4285 => x"de", + 4286 => x"88", + 4287 => x"80", + 4288 => x"17", + 4289 => x"51", + 4290 => x"3f", + 4291 => x"08", + 4292 => x"81", + 4293 => x"81", + 4294 => x"c0", + 4295 => x"09", + 4296 => x"38", + 4297 => x"39", + 4298 => x"77", + 4299 => x"c0", + 4300 => x"08", + 4301 => x"98", + 4302 => x"81", + 4303 => x"52", + 4304 => x"bd", + 4305 => x"c0", + 4306 => x"17", + 4307 => x"0c", + 4308 => x"80", + 4309 => x"73", + 4310 => x"75", + 4311 => x"38", + 4312 => x"34", + 4313 => x"81", + 4314 => x"89", + 4315 => x"e2", + 4316 => x"53", + 4317 => x"a4", + 4318 => x"3d", + 4319 => x"3f", + 4320 => x"08", + 4321 => x"c0", + 4322 => x"38", + 4323 => x"3d", + 4324 => x"3d", + 4325 => x"d1", + 4326 => x"de", + 4327 => x"81", + 4328 => x"81", + 4329 => x"80", + 4330 => x"70", + 4331 => x"81", + 4332 => x"56", + 4333 => x"81", + 4334 => x"98", + 4335 => x"74", + 4336 => x"38", + 4337 => x"05", + 4338 => x"06", + 4339 => x"55", + 4340 => x"38", + 4341 => x"51", + 4342 => x"81", + 4343 => x"74", + 4344 => x"81", + 4345 => x"56", + 4346 => x"80", + 4347 => x"54", + 4348 => x"08", + 4349 => x"2e", + 4350 => x"73", + 4351 => x"c0", + 4352 => x"52", + 4353 => x"52", + 4354 => x"3f", + 4355 => x"08", + 4356 => x"c0", + 4357 => x"38", + 4358 => x"08", + 4359 => x"cc", + 4360 => x"de", + 4361 => x"81", + 4362 => x"86", + 4363 => x"80", + 4364 => x"de", + 4365 => x"2e", + 4366 => x"de", + 4367 => x"c0", + 4368 => x"ce", + 4369 => x"de", + 4370 => x"de", + 4371 => x"70", + 4372 => x"08", + 4373 => x"51", + 4374 => x"80", + 4375 => x"73", + 4376 => x"38", + 4377 => x"52", + 4378 => x"95", + 4379 => x"c0", + 4380 => x"8c", + 4381 => x"ff", + 4382 => x"81", + 4383 => x"55", + 4384 => x"c0", + 4385 => x"0d", + 4386 => x"0d", + 4387 => x"3d", + 4388 => x"9a", + 4389 => x"cb", + 4390 => x"c0", + 4391 => x"de", + 4392 => x"b0", + 4393 => x"69", + 4394 => x"70", + 4395 => x"97", + 4396 => x"c0", + 4397 => x"de", + 4398 => x"38", + 4399 => x"94", + 4400 => x"c0", + 4401 => x"09", + 4402 => x"88", + 4403 => x"df", + 4404 => x"85", + 4405 => x"51", + 4406 => x"74", + 4407 => x"78", + 4408 => x"8a", + 4409 => x"57", + 4410 => x"81", + 4411 => x"75", + 4412 => x"de", + 4413 => x"38", + 4414 => x"de", + 4415 => x"2e", + 4416 => x"83", + 4417 => x"81", + 4418 => x"ff", + 4419 => x"06", + 4420 => x"54", + 4421 => x"73", + 4422 => x"81", + 4423 => x"52", + 4424 => x"a4", + 4425 => x"c0", + 4426 => x"de", + 4427 => x"9a", + 4428 => x"a0", + 4429 => x"51", + 4430 => x"3f", + 4431 => x"0b", + 4432 => x"78", + 4433 => x"bf", + 4434 => x"88", + 4435 => x"80", + 4436 => x"ff", + 4437 => x"75", + 4438 => x"11", + 4439 => x"f8", + 4440 => x"78", + 4441 => x"80", + 4442 => x"ff", + 4443 => x"78", + 4444 => x"80", + 4445 => x"7f", + 4446 => x"d4", + 4447 => x"c9", + 4448 => x"54", + 4449 => x"15", + 4450 => x"cb", + 4451 => x"de", + 4452 => x"81", + 4453 => x"b2", + 4454 => x"b2", + 4455 => x"96", + 4456 => x"b5", + 4457 => x"53", + 4458 => x"51", + 4459 => x"64", + 4460 => x"8b", + 4461 => x"54", + 4462 => x"15", + 4463 => x"ff", + 4464 => x"81", + 4465 => x"54", + 4466 => x"53", + 4467 => x"51", + 4468 => x"3f", + 4469 => x"c0", + 4470 => x"0d", + 4471 => x"0d", + 4472 => x"05", + 4473 => x"3f", + 4474 => x"3d", + 4475 => x"52", + 4476 => x"d5", + 4477 => x"de", + 4478 => x"81", + 4479 => x"82", + 4480 => x"4d", + 4481 => x"52", + 4482 => x"52", + 4483 => x"3f", + 4484 => x"08", + 4485 => x"c0", + 4486 => x"38", + 4487 => x"05", + 4488 => x"06", + 4489 => x"73", + 4490 => x"a0", + 4491 => x"08", + 4492 => x"ff", + 4493 => x"ff", + 4494 => x"ac", + 4495 => x"92", + 4496 => x"54", + 4497 => x"3f", + 4498 => x"52", + 4499 => x"f7", + 4500 => x"c0", + 4501 => x"de", + 4502 => x"38", + 4503 => x"09", + 4504 => x"38", + 4505 => x"08", + 4506 => x"88", + 4507 => x"39", + 4508 => x"08", + 4509 => x"81", + 4510 => x"38", + 4511 => x"b1", + 4512 => x"c0", + 4513 => x"de", + 4514 => x"c8", + 4515 => x"93", + 4516 => x"ff", + 4517 => x"8d", + 4518 => x"b4", + 4519 => x"af", + 4520 => x"17", + 4521 => x"33", + 4522 => x"70", + 4523 => x"55", + 4524 => x"38", + 4525 => x"54", + 4526 => x"34", + 4527 => x"0b", + 4528 => x"8b", + 4529 => x"84", + 4530 => x"06", + 4531 => x"73", + 4532 => x"e5", + 4533 => x"2e", + 4534 => x"75", + 4535 => x"c6", + 4536 => x"de", + 4537 => x"78", + 4538 => x"bb", + 4539 => x"81", + 4540 => x"80", + 4541 => x"38", + 4542 => x"08", + 4543 => x"ff", + 4544 => x"81", + 4545 => x"79", + 4546 => x"58", + 4547 => x"de", + 4548 => x"c0", + 4549 => x"33", + 4550 => x"2e", + 4551 => x"99", + 4552 => x"75", + 4553 => x"c6", + 4554 => x"54", + 4555 => x"15", + 4556 => x"81", + 4557 => x"9c", + 4558 => x"c8", + 4559 => x"de", + 4560 => x"81", + 4561 => x"8c", + 4562 => x"ff", + 4563 => x"81", + 4564 => x"55", + 4565 => x"c0", + 4566 => x"0d", + 4567 => x"0d", + 4568 => x"05", + 4569 => x"05", + 4570 => x"33", + 4571 => x"53", + 4572 => x"05", + 4573 => x"51", + 4574 => x"81", + 4575 => x"55", + 4576 => x"08", + 4577 => x"78", + 4578 => x"95", + 4579 => x"51", + 4580 => x"81", + 4581 => x"55", + 4582 => x"08", + 4583 => x"80", + 4584 => x"81", + 4585 => x"86", + 4586 => x"38", + 4587 => x"61", + 4588 => x"12", + 4589 => x"7a", + 4590 => x"51", + 4591 => x"74", + 4592 => x"78", + 4593 => x"83", + 4594 => x"51", + 4595 => x"3f", + 4596 => x"08", + 4597 => x"de", + 4598 => x"3d", + 4599 => x"3d", + 4600 => x"82", + 4601 => x"d0", + 4602 => x"3d", + 4603 => x"3f", + 4604 => x"08", + 4605 => x"c0", + 4606 => x"38", + 4607 => x"52", + 4608 => x"05", + 4609 => x"3f", + 4610 => x"08", + 4611 => x"c0", + 4612 => x"02", + 4613 => x"33", + 4614 => x"54", + 4615 => x"a6", + 4616 => x"22", + 4617 => x"71", + 4618 => x"53", + 4619 => x"51", + 4620 => x"3f", + 4621 => x"0b", + 4622 => x"76", + 4623 => x"b8", + 4624 => x"c0", + 4625 => x"81", + 4626 => x"93", + 4627 => x"ea", + 4628 => x"6b", + 4629 => x"53", + 4630 => x"05", + 4631 => x"51", + 4632 => x"81", + 4633 => x"81", + 4634 => x"30", + 4635 => x"c0", + 4636 => x"25", + 4637 => x"79", + 4638 => x"85", + 4639 => x"75", + 4640 => x"73", + 4641 => x"f9", + 4642 => x"80", + 4643 => x"8d", + 4644 => x"54", + 4645 => x"3f", + 4646 => x"08", + 4647 => x"c0", + 4648 => x"38", + 4649 => x"51", + 4650 => x"81", + 4651 => x"57", + 4652 => x"08", + 4653 => x"de", + 4654 => x"de", + 4655 => x"5b", + 4656 => x"18", + 4657 => x"18", + 4658 => x"74", + 4659 => x"81", + 4660 => x"78", + 4661 => x"8b", + 4662 => x"54", + 4663 => x"75", + 4664 => x"38", + 4665 => x"1b", + 4666 => x"55", + 4667 => x"2e", + 4668 => x"39", + 4669 => x"09", + 4670 => x"38", + 4671 => x"80", + 4672 => x"70", + 4673 => x"25", + 4674 => x"80", + 4675 => x"38", + 4676 => x"bc", + 4677 => x"11", + 4678 => x"ff", + 4679 => x"81", + 4680 => x"57", + 4681 => x"08", + 4682 => x"70", + 4683 => x"80", + 4684 => x"83", + 4685 => x"80", + 4686 => x"84", + 4687 => x"a7", + 4688 => x"b4", + 4689 => x"ad", + 4690 => x"de", + 4691 => x"0c", + 4692 => x"c0", + 4693 => x"0d", + 4694 => x"0d", + 4695 => x"3d", + 4696 => x"52", + 4697 => x"ce", + 4698 => x"de", + 4699 => x"de", + 4700 => x"54", + 4701 => x"08", + 4702 => x"8b", + 4703 => x"8b", + 4704 => x"59", + 4705 => x"3f", + 4706 => x"33", + 4707 => x"06", + 4708 => x"57", + 4709 => x"81", + 4710 => x"58", + 4711 => x"06", + 4712 => x"4e", + 4713 => x"ff", + 4714 => x"81", + 4715 => x"80", + 4716 => x"6c", + 4717 => x"53", + 4718 => x"ae", + 4719 => x"de", + 4720 => x"2e", + 4721 => x"88", + 4722 => x"6d", + 4723 => x"55", + 4724 => x"de", + 4725 => x"ff", + 4726 => x"83", + 4727 => x"51", + 4728 => x"26", + 4729 => x"15", + 4730 => x"ff", + 4731 => x"80", + 4732 => x"87", + 4733 => x"b4", + 4734 => x"74", + 4735 => x"38", + 4736 => x"ce", + 4737 => x"ae", + 4738 => x"de", + 4739 => x"38", + 4740 => x"27", + 4741 => x"89", + 4742 => x"8b", + 4743 => x"27", + 4744 => x"55", + 4745 => x"81", + 4746 => x"8f", + 4747 => x"2a", + 4748 => x"70", + 4749 => x"34", + 4750 => x"74", + 4751 => x"05", + 4752 => x"17", + 4753 => x"70", + 4754 => x"52", + 4755 => x"73", + 4756 => x"c8", + 4757 => x"33", + 4758 => x"73", + 4759 => x"81", + 4760 => x"80", + 4761 => x"02", + 4762 => x"76", + 4763 => x"51", + 4764 => x"2e", + 4765 => x"87", + 4766 => x"57", + 4767 => x"79", + 4768 => x"80", + 4769 => x"70", + 4770 => x"ba", + 4771 => x"de", + 4772 => x"81", + 4773 => x"80", + 4774 => x"52", + 4775 => x"bf", + 4776 => x"de", + 4777 => x"81", + 4778 => x"8d", + 4779 => x"c4", + 4780 => x"e5", + 4781 => x"c6", + 4782 => x"c0", + 4783 => x"09", + 4784 => x"cc", + 4785 => x"76", + 4786 => x"c4", + 4787 => x"74", + 4788 => x"b0", + 4789 => x"c0", + 4790 => x"de", + 4791 => x"38", + 4792 => x"de", + 4793 => x"67", + 4794 => x"db", + 4795 => x"88", + 4796 => x"34", + 4797 => x"52", + 4798 => x"ab", + 4799 => x"54", + 4800 => x"15", + 4801 => x"ff", + 4802 => x"81", + 4803 => x"54", + 4804 => x"81", + 4805 => x"9c", + 4806 => x"f2", + 4807 => x"62", + 4808 => x"80", + 4809 => x"93", + 4810 => x"55", + 4811 => x"5e", + 4812 => x"3f", + 4813 => x"08", + 4814 => x"c0", + 4815 => x"38", + 4816 => x"58", + 4817 => x"38", + 4818 => x"97", + 4819 => x"08", + 4820 => x"38", + 4821 => x"70", + 4822 => x"81", + 4823 => x"55", + 4824 => x"87", + 4825 => x"39", + 4826 => x"90", + 4827 => x"82", + 4828 => x"8a", + 4829 => x"89", + 4830 => x"7f", + 4831 => x"56", + 4832 => x"3f", + 4833 => x"06", + 4834 => x"72", + 4835 => x"81", + 4836 => x"05", + 4837 => x"7c", + 4838 => x"55", + 4839 => x"27", + 4840 => x"16", + 4841 => x"83", + 4842 => x"76", + 4843 => x"80", + 4844 => x"79", + 4845 => x"99", + 4846 => x"7f", + 4847 => x"14", + 4848 => x"83", + 4849 => x"81", + 4850 => x"81", + 4851 => x"38", + 4852 => x"08", + 4853 => x"95", + 4854 => x"c0", + 4855 => x"81", + 4856 => x"7b", + 4857 => x"06", + 4858 => x"39", + 4859 => x"56", + 4860 => x"09", + 4861 => x"b9", + 4862 => x"80", + 4863 => x"80", + 4864 => x"78", + 4865 => x"7a", + 4866 => x"38", + 4867 => x"73", + 4868 => x"81", + 4869 => x"ff", + 4870 => x"74", + 4871 => x"ff", + 4872 => x"81", + 4873 => x"58", + 4874 => x"08", + 4875 => x"74", + 4876 => x"16", + 4877 => x"73", + 4878 => x"39", + 4879 => x"7e", + 4880 => x"0c", + 4881 => x"2e", + 4882 => x"88", + 4883 => x"8c", + 4884 => x"1a", + 4885 => x"07", + 4886 => x"1b", + 4887 => x"08", + 4888 => x"16", + 4889 => x"75", + 4890 => x"38", + 4891 => x"90", + 4892 => x"15", + 4893 => x"54", + 4894 => x"34", + 4895 => x"81", + 4896 => x"90", + 4897 => x"e9", + 4898 => x"6d", + 4899 => x"80", + 4900 => x"9d", + 4901 => x"5c", + 4902 => x"3f", + 4903 => x"0b", + 4904 => x"08", + 4905 => x"38", + 4906 => x"08", + 4907 => x"de", + 4908 => x"08", + 4909 => x"80", + 4910 => x"80", + 4911 => x"de", + 4912 => x"ff", + 4913 => x"52", + 4914 => x"a0", + 4915 => x"de", + 4916 => x"ff", + 4917 => x"06", + 4918 => x"56", + 4919 => x"38", + 4920 => x"70", + 4921 => x"55", + 4922 => x"8b", + 4923 => x"3d", + 4924 => x"83", + 4925 => x"ff", + 4926 => x"81", + 4927 => x"99", + 4928 => x"74", + 4929 => x"38", + 4930 => x"80", + 4931 => x"ff", + 4932 => x"55", + 4933 => x"83", + 4934 => x"78", + 4935 => x"38", + 4936 => x"26", + 4937 => x"81", + 4938 => x"8b", + 4939 => x"79", + 4940 => x"80", + 4941 => x"93", + 4942 => x"39", + 4943 => x"6e", + 4944 => x"89", + 4945 => x"48", + 4946 => x"83", + 4947 => x"61", + 4948 => x"25", + 4949 => x"55", + 4950 => x"8a", + 4951 => x"3d", + 4952 => x"81", + 4953 => x"ff", + 4954 => x"81", + 4955 => x"c0", + 4956 => x"38", + 4957 => x"70", + 4958 => x"de", + 4959 => x"56", + 4960 => x"38", + 4961 => x"55", + 4962 => x"75", + 4963 => x"38", + 4964 => x"70", + 4965 => x"ff", + 4966 => x"83", + 4967 => x"78", + 4968 => x"89", + 4969 => x"81", + 4970 => x"06", + 4971 => x"80", + 4972 => x"77", + 4973 => x"74", + 4974 => x"8d", + 4975 => x"06", + 4976 => x"2e", + 4977 => x"77", + 4978 => x"93", + 4979 => x"74", + 4980 => x"cb", + 4981 => x"7d", + 4982 => x"81", + 4983 => x"38", + 4984 => x"66", + 4985 => x"81", + 4986 => x"d8", + 4987 => x"74", + 4988 => x"38", + 4989 => x"98", + 4990 => x"d8", + 4991 => x"82", + 4992 => x"57", + 4993 => x"80", + 4994 => x"76", + 4995 => x"38", + 4996 => x"51", + 4997 => x"3f", + 4998 => x"08", + 4999 => x"87", + 5000 => x"2a", + 5001 => x"5c", + 5002 => x"de", + 5003 => x"80", + 5004 => x"44", + 5005 => x"0a", + 5006 => x"ec", + 5007 => x"39", + 5008 => x"66", + 5009 => x"81", + 5010 => x"c8", + 5011 => x"74", + 5012 => x"38", + 5013 => x"98", + 5014 => x"c8", + 5015 => x"82", + 5016 => x"57", + 5017 => x"80", + 5018 => x"76", + 5019 => x"38", + 5020 => x"51", + 5021 => x"3f", + 5022 => x"08", + 5023 => x"57", + 5024 => x"08", + 5025 => x"96", + 5026 => x"81", + 5027 => x"10", + 5028 => x"08", + 5029 => x"72", + 5030 => x"59", + 5031 => x"ff", + 5032 => x"5d", + 5033 => x"44", + 5034 => x"11", + 5035 => x"70", + 5036 => x"71", + 5037 => x"06", + 5038 => x"52", + 5039 => x"40", + 5040 => x"09", + 5041 => x"38", + 5042 => x"18", + 5043 => x"39", + 5044 => x"79", + 5045 => x"70", + 5046 => x"58", + 5047 => x"76", + 5048 => x"38", + 5049 => x"7d", + 5050 => x"70", + 5051 => x"55", + 5052 => x"3f", + 5053 => x"08", + 5054 => x"2e", + 5055 => x"9b", + 5056 => x"c0", + 5057 => x"f5", + 5058 => x"38", + 5059 => x"38", + 5060 => x"59", + 5061 => x"38", + 5062 => x"7d", + 5063 => x"81", + 5064 => x"38", + 5065 => x"0b", + 5066 => x"08", + 5067 => x"78", + 5068 => x"1a", + 5069 => x"c0", + 5070 => x"74", + 5071 => x"39", + 5072 => x"55", + 5073 => x"8f", + 5074 => x"fd", + 5075 => x"de", + 5076 => x"f5", + 5077 => x"78", + 5078 => x"79", + 5079 => x"80", + 5080 => x"f1", + 5081 => x"39", + 5082 => x"81", + 5083 => x"06", + 5084 => x"55", + 5085 => x"27", + 5086 => x"81", + 5087 => x"56", + 5088 => x"38", + 5089 => x"80", + 5090 => x"ff", + 5091 => x"8b", + 5092 => x"f0", + 5093 => x"ff", + 5094 => x"84", + 5095 => x"1b", + 5096 => x"b3", + 5097 => x"1c", + 5098 => x"ff", + 5099 => x"8e", + 5100 => x"a1", + 5101 => x"0b", + 5102 => x"7d", + 5103 => x"30", + 5104 => x"84", + 5105 => x"51", + 5106 => x"51", + 5107 => x"3f", + 5108 => x"83", + 5109 => x"90", + 5110 => x"ff", + 5111 => x"93", + 5112 => x"a0", + 5113 => x"39", + 5114 => x"1b", + 5115 => x"85", + 5116 => x"95", + 5117 => x"52", + 5118 => x"ff", + 5119 => x"81", + 5120 => x"1b", + 5121 => x"cf", + 5122 => x"9c", + 5123 => x"a0", + 5124 => x"83", + 5125 => x"06", + 5126 => x"82", + 5127 => x"52", + 5128 => x"51", + 5129 => x"3f", + 5130 => x"1b", + 5131 => x"c5", + 5132 => x"ac", + 5133 => x"a0", + 5134 => x"52", + 5135 => x"ff", + 5136 => x"86", + 5137 => x"51", + 5138 => x"3f", + 5139 => x"80", + 5140 => x"a9", + 5141 => x"1c", + 5142 => x"81", + 5143 => x"80", + 5144 => x"ae", + 5145 => x"b2", + 5146 => x"1b", + 5147 => x"85", + 5148 => x"ff", + 5149 => x"96", + 5150 => x"9f", + 5151 => x"80", + 5152 => x"34", + 5153 => x"1c", + 5154 => x"81", + 5155 => x"ab", + 5156 => x"a0", + 5157 => x"d4", + 5158 => x"fe", + 5159 => x"59", + 5160 => x"3f", + 5161 => x"53", + 5162 => x"51", + 5163 => x"3f", + 5164 => x"de", + 5165 => x"e7", + 5166 => x"2e", + 5167 => x"80", + 5168 => x"54", + 5169 => x"53", + 5170 => x"51", + 5171 => x"3f", + 5172 => x"80", + 5173 => x"ff", + 5174 => x"84", + 5175 => x"d2", + 5176 => x"ff", + 5177 => x"86", + 5178 => x"f2", + 5179 => x"1b", + 5180 => x"81", + 5181 => x"52", + 5182 => x"51", + 5183 => x"3f", + 5184 => x"ec", + 5185 => x"9e", + 5186 => x"d4", + 5187 => x"51", + 5188 => x"3f", + 5189 => x"87", + 5190 => x"52", + 5191 => x"9a", + 5192 => x"54", + 5193 => x"7a", + 5194 => x"ff", + 5195 => x"65", + 5196 => x"7a", + 5197 => x"8f", + 5198 => x"80", + 5199 => x"2e", + 5200 => x"9a", + 5201 => x"7a", + 5202 => x"a9", + 5203 => x"84", + 5204 => x"9e", + 5205 => x"0a", + 5206 => x"51", + 5207 => x"ff", + 5208 => x"7d", + 5209 => x"38", + 5210 => x"52", + 5211 => x"9e", + 5212 => x"55", + 5213 => x"62", + 5214 => x"74", + 5215 => x"75", + 5216 => x"7e", + 5217 => x"fe", + 5218 => x"c0", + 5219 => x"38", + 5220 => x"81", + 5221 => x"52", + 5222 => x"9e", + 5223 => x"16", + 5224 => x"56", + 5225 => x"38", + 5226 => x"77", + 5227 => x"8d", + 5228 => x"7d", + 5229 => x"38", + 5230 => x"57", + 5231 => x"83", + 5232 => x"76", + 5233 => x"7a", + 5234 => x"ff", + 5235 => x"81", + 5236 => x"81", + 5237 => x"16", + 5238 => x"56", + 5239 => x"38", + 5240 => x"83", + 5241 => x"86", + 5242 => x"ff", + 5243 => x"38", + 5244 => x"82", + 5245 => x"81", + 5246 => x"06", + 5247 => x"fe", + 5248 => x"53", + 5249 => x"51", + 5250 => x"3f", + 5251 => x"52", + 5252 => x"9c", + 5253 => x"be", + 5254 => x"75", + 5255 => x"81", + 5256 => x"0b", + 5257 => x"77", + 5258 => x"75", + 5259 => x"60", + 5260 => x"80", + 5261 => x"75", + 5262 => x"be", + 5263 => x"85", + 5264 => x"de", + 5265 => x"2a", + 5266 => x"75", + 5267 => x"81", + 5268 => x"87", + 5269 => x"52", + 5270 => x"51", + 5271 => x"3f", + 5272 => x"ca", + 5273 => x"9c", + 5274 => x"54", + 5275 => x"52", + 5276 => x"98", + 5277 => x"56", + 5278 => x"08", + 5279 => x"53", + 5280 => x"51", + 5281 => x"3f", + 5282 => x"de", + 5283 => x"38", + 5284 => x"56", + 5285 => x"56", + 5286 => x"de", + 5287 => x"75", + 5288 => x"0c", + 5289 => x"04", + 5290 => x"7d", + 5291 => x"80", + 5292 => x"05", + 5293 => x"76", + 5294 => x"38", + 5295 => x"11", + 5296 => x"53", + 5297 => x"79", + 5298 => x"3f", + 5299 => x"09", + 5300 => x"38", + 5301 => x"55", + 5302 => x"db", + 5303 => x"70", + 5304 => x"34", + 5305 => x"74", + 5306 => x"81", + 5307 => x"80", + 5308 => x"55", + 5309 => x"76", + 5310 => x"de", + 5311 => x"3d", + 5312 => x"3d", + 5313 => x"71", + 5314 => x"8e", + 5315 => x"29", + 5316 => x"05", + 5317 => x"04", + 5318 => x"51", + 5319 => x"81", + 5320 => x"80", + 5321 => x"d0", + 5322 => x"f2", + 5323 => x"a4", + 5324 => x"39", + 5325 => x"51", + 5326 => x"81", + 5327 => x"80", + 5328 => x"d0", + 5329 => x"d6", + 5330 => x"e8", + 5331 => x"39", + 5332 => x"51", + 5333 => x"81", + 5334 => x"80", + 5335 => x"d1", + 5336 => x"39", + 5337 => x"51", + 5338 => x"d1", + 5339 => x"39", + 5340 => x"51", + 5341 => x"d2", + 5342 => x"39", + 5343 => x"51", + 5344 => x"d2", + 5345 => x"39", + 5346 => x"51", + 5347 => x"d3", + 5348 => x"39", + 5349 => x"51", + 5350 => x"d3", + 5351 => x"87", + 5352 => x"3d", + 5353 => x"3d", + 5354 => x"56", + 5355 => x"e7", + 5356 => x"74", + 5357 => x"e8", + 5358 => x"39", + 5359 => x"74", + 5360 => x"b6", + 5361 => x"c0", + 5362 => x"51", + 5363 => x"3f", + 5364 => x"08", + 5365 => x"75", + 5366 => x"b8", + 5367 => x"c6", + 5368 => x"0d", + 5369 => x"0d", + 5370 => x"02", + 5371 => x"c7", + 5372 => x"73", + 5373 => x"5d", + 5374 => x"5c", + 5375 => x"81", + 5376 => x"ff", + 5377 => x"81", + 5378 => x"ff", + 5379 => x"80", + 5380 => x"27", + 5381 => x"79", + 5382 => x"38", + 5383 => x"a7", + 5384 => x"39", + 5385 => x"72", + 5386 => x"38", + 5387 => x"81", + 5388 => x"ff", + 5389 => x"89", + 5390 => x"f4", + 5391 => x"82", + 5392 => x"55", + 5393 => x"74", + 5394 => x"78", + 5395 => x"72", + 5396 => x"d3", + 5397 => x"8b", + 5398 => x"39", + 5399 => x"51", + 5400 => x"3f", + 5401 => x"a1", + 5402 => x"53", + 5403 => x"8e", + 5404 => x"52", + 5405 => x"51", + 5406 => x"3f", + 5407 => x"d4", + 5408 => x"85", + 5409 => x"15", + 5410 => x"fe", + 5411 => x"ff", + 5412 => x"d4", + 5413 => x"85", + 5414 => x"55", + 5415 => x"aa", + 5416 => x"70", + 5417 => x"26", + 5418 => x"9f", + 5419 => x"38", + 5420 => x"8b", + 5421 => x"fe", + 5422 => x"73", + 5423 => x"a0", + 5424 => x"f9", + 5425 => x"55", + 5426 => x"d4", + 5427 => x"84", + 5428 => x"16", + 5429 => x"56", + 5430 => x"3f", + 5431 => x"08", + 5432 => x"98", + 5433 => x"74", + 5434 => x"81", + 5435 => x"fe", + 5436 => x"81", + 5437 => x"98", + 5438 => x"2c", + 5439 => x"70", + 5440 => x"07", + 5441 => x"56", + 5442 => x"74", + 5443 => x"38", + 5444 => x"74", + 5445 => x"81", + 5446 => x"80", + 5447 => x"7a", + 5448 => x"76", + 5449 => x"38", + 5450 => x"81", + 5451 => x"8d", + 5452 => x"ec", + 5453 => x"02", + 5454 => x"e3", + 5455 => x"72", + 5456 => x"07", + 5457 => x"87", + 5458 => x"07", + 5459 => x"5a", + 5460 => x"57", + 5461 => x"38", + 5462 => x"52", + 5463 => x"52", + 5464 => x"de", + 5465 => x"c0", + 5466 => x"de", + 5467 => x"38", + 5468 => x"08", + 5469 => x"88", + 5470 => x"c0", + 5471 => x"3d", + 5472 => x"84", + 5473 => x"52", + 5474 => x"9b", + 5475 => x"c0", + 5476 => x"de", + 5477 => x"38", + 5478 => x"80", + 5479 => x"74", + 5480 => x"59", + 5481 => x"96", + 5482 => x"51", + 5483 => x"75", + 5484 => x"07", + 5485 => x"55", + 5486 => x"95", + 5487 => x"2e", + 5488 => x"d4", + 5489 => x"c0", + 5490 => x"52", + 5491 => x"d6", + 5492 => x"76", + 5493 => x"0c", + 5494 => x"04", + 5495 => x"7b", + 5496 => x"b3", + 5497 => x"58", + 5498 => x"53", + 5499 => x"51", + 5500 => x"81", + 5501 => x"a4", + 5502 => x"2e", + 5503 => x"81", + 5504 => x"98", + 5505 => x"7f", + 5506 => x"c0", + 5507 => x"7d", + 5508 => x"81", + 5509 => x"57", + 5510 => x"04", + 5511 => x"c0", + 5512 => x"0d", + 5513 => x"0d", + 5514 => x"33", + 5515 => x"53", + 5516 => x"52", + 5517 => x"ee", + 5518 => x"c0", + 5519 => x"80", + 5520 => x"d4", + 5521 => x"d4", + 5522 => x"db", + 5523 => x"81", + 5524 => x"ff", + 5525 => x"74", + 5526 => x"38", + 5527 => x"3f", + 5528 => x"04", + 5529 => x"87", + 5530 => x"08", + 5531 => x"a2", + 5532 => x"fe", + 5533 => x"81", + 5534 => x"fe", + 5535 => x"80", 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x"3f", + 5595 => x"70", + 5596 => x"52", + 5597 => x"95", + 5598 => x"fe", + 5599 => x"81", + 5600 => x"fe", + 5601 => x"80", + 5602 => x"97", + 5603 => x"cb", + 5604 => x"0d", + 5605 => x"0d", + 5606 => x"70", + 5607 => x"73", + 5608 => x"f0", + 5609 => x"73", + 5610 => x"15", + 5611 => x"e4", + 5612 => x"54", + 5613 => x"70", + 5614 => x"57", + 5615 => x"a0", + 5616 => x"81", + 5617 => x"2e", + 5618 => x"e5", + 5619 => x"ff", + 5620 => x"a0", + 5621 => x"06", + 5622 => x"74", + 5623 => x"56", + 5624 => x"75", + 5625 => x"db", + 5626 => x"08", + 5627 => x"52", + 5628 => x"9e", + 5629 => x"c0", + 5630 => x"84", + 5631 => x"72", + 5632 => x"a3", + 5633 => x"70", + 5634 => x"57", + 5635 => x"27", + 5636 => x"53", + 5637 => x"c0", + 5638 => x"0d", + 5639 => x"0d", + 5640 => x"55", + 5641 => x"52", + 5642 => x"e8", + 5643 => x"db", + 5644 => x"73", + 5645 => x"53", + 5646 => x"52", + 5647 => x"51", + 5648 => x"3f", + 5649 => x"08", + 5650 => x"de", + 5651 => x"80", + 5652 => x"31", + 5653 => x"73", + 5654 => x"34", + 5655 => x"33", + 5656 => x"2e", + 5657 => x"ac", + 5658 => x"c4", + 5659 => x"75", + 5660 => x"3f", + 5661 => x"08", + 5662 => x"38", + 5663 => x"08", + 5664 => x"be", + 5665 => x"81", + 5666 => x"c6", + 5667 => x"0b", + 5668 => x"34", + 5669 => x"33", + 5670 => x"2e", + 5671 => x"89", + 5672 => x"75", + 5673 => x"d8", + 5674 => x"81", + 5675 => x"87", + 5676 => x"cb", + 5677 => x"70", + 5678 => x"c0", + 5679 => x"81", + 5680 => x"ff", + 5681 => x"81", + 5682 => x"81", + 5683 => x"78", + 5684 => x"81", + 5685 => x"81", + 5686 => x"99", + 5687 => x"59", + 5688 => x"3f", + 5689 => x"52", + 5690 => x"51", + 5691 => x"3f", + 5692 => x"08", + 5693 => x"38", + 5694 => x"51", + 5695 => x"81", + 5696 => x"81", + 5697 => x"fe", + 5698 => x"99", + 5699 => x"5a", + 5700 => x"79", + 5701 => x"3f", + 5702 => x"f8", + 5703 => x"f5", + 5704 => x"c0", + 5705 => x"70", + 5706 => x"59", + 5707 => x"2e", + 5708 => x"78", + 5709 => x"80", + 5710 => x"ab", + 5711 => x"38", + 5712 => x"a4", + 5713 => x"2e", + 5714 => x"78", + 5715 => x"38", + 5716 => x"ff", + 5717 => x"de", + 5718 => x"2e", + 5719 => x"78", + 5720 => x"ad", + 5721 => x"39", + 5722 => x"2e", + 5723 => x"78", + 5724 => x"90", + 5725 => x"2e", + 5726 => x"78", + 5727 => x"8b", + 5728 => x"39", + 5729 => x"2e", + 5730 => x"78", + 5731 => x"88", + 5732 => x"a2", + 5733 => x"d5", + 5734 => x"38", + 5735 => x"24", + 5736 => x"80", + 5737 => x"a7", + 5738 => x"d0", + 5739 => x"78", + 5740 => x"8a", + 5741 => x"fe", + 5742 => x"d1", + 5743 => x"38", + 5744 => x"2e", + 5745 => x"8e", + 5746 => x"81", + 5747 => x"c3", + 5748 => x"82", + 5749 => x"78", + 5750 => x"8d", + 5751 => x"80", + 5752 => x"ec", + 5753 => x"39", + 5754 => x"2e", + 5755 => x"78", + 5756 => x"8e", + 5757 => x"be", + 5758 => x"fe", + 5759 => x"fe", + 5760 => x"ff", + 5761 => x"81", + 5762 => x"88", + 5763 => x"90", + 5764 => x"39", + 5765 => x"f0", + 5766 => x"f8", + 5767 => x"81", + 5768 => x"de", + 5769 => x"2e", + 5770 => x"63", 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x"de", + 5830 => x"7a", + 5831 => x"3f", + 5832 => x"b7", + 5833 => x"05", + 5834 => x"a8", + 5835 => x"c0", + 5836 => x"fe", + 5837 => x"5b", + 5838 => x"3f", + 5839 => x"08", + 5840 => x"f8", + 5841 => x"fe", + 5842 => x"81", + 5843 => x"b8", + 5844 => x"05", + 5845 => x"e5", + 5846 => x"db", + 5847 => x"de", + 5848 => x"56", + 5849 => x"de", + 5850 => x"ff", + 5851 => x"53", + 5852 => x"51", + 5853 => x"81", + 5854 => x"80", + 5855 => x"38", + 5856 => x"08", + 5857 => x"3f", + 5858 => x"b7", + 5859 => x"11", + 5860 => x"05", + 5861 => x"83", + 5862 => x"c0", + 5863 => x"fa", + 5864 => x"3d", + 5865 => x"53", + 5866 => x"51", + 5867 => x"3f", + 5868 => x"08", + 5869 => x"cb", + 5870 => x"fe", + 5871 => x"fe", + 5872 => x"fe", + 5873 => x"81", + 5874 => x"86", + 5875 => x"c0", + 5876 => x"d7", + 5877 => x"f6", + 5878 => x"63", + 5879 => x"7b", + 5880 => x"38", + 5881 => x"7a", + 5882 => x"5c", + 5883 => x"26", + 5884 => x"d5", + 5885 => x"fe", + 5886 => x"fe", + 5887 => x"fe", + 5888 => x"81", + 5889 => x"80", + 5890 => x"db", + 5891 => x"78", + 5892 => x"38", + 5893 => x"08", + 5894 => x"39", + 5895 => x"33", + 5896 => x"2e", + 5897 => x"db", + 5898 => x"bc", + 5899 => x"d6", + 5900 => x"80", + 5901 => x"81", + 5902 => x"44", + 5903 => x"db", + 5904 => x"78", + 5905 => x"38", + 5906 => x"08", + 5907 => x"81", + 5908 => x"59", + 5909 => x"88", + 5910 => x"ac", + 5911 => x"39", + 5912 => x"08", + 5913 => x"44", + 5914 => x"f0", + 5915 => x"f8", + 5916 => x"fd", + 5917 => x"de", + 5918 => x"de", + 5919 => x"d4", + 5920 => x"80", + 5921 => x"81", + 5922 => x"43", + 5923 => x"81", + 5924 => x"59", + 5925 => x"88", + 5926 => x"98", + 5927 => x"39", + 5928 => x"33", + 5929 => x"2e", + 5930 => x"db", + 5931 => x"aa", + 5932 => x"d7", + 5933 => x"80", + 5934 => x"81", + 5935 => x"43", + 5936 => x"db", + 5937 => x"78", + 5938 => x"38", + 5939 => x"08", + 5940 => x"81", + 5941 => x"88", + 5942 => x"3d", + 5943 => x"53", + 5944 => x"51", + 5945 => x"3f", + 5946 => x"08", + 5947 => x"38", + 5948 => x"59", + 5949 => x"83", + 5950 => x"79", + 5951 => x"38", + 5952 => x"88", + 5953 => x"2e", + 5954 => x"42", + 5955 => x"51", + 5956 => x"3f", + 5957 => x"54", + 5958 => x"52", + 5959 => x"c5", + 5960 => x"f4", + 5961 => x"39", + 5962 => x"f4", + 5963 => x"f8", + 5964 => x"fb", + 5965 => x"de", + 5966 => x"2e", + 5967 => x"b7", + 5968 => x"11", + 5969 => x"05", + 5970 => x"cf", + 5971 => x"c0", + 5972 => x"a5", + 5973 => x"02", + 5974 => x"33", + 5975 => x"81", + 5976 => x"3d", + 5977 => x"53", + 5978 => x"51", + 5979 => x"3f", + 5980 => x"08", + 5981 => x"8b", + 5982 => x"33", + 5983 => x"d8", + 5984 => x"f9", + 5985 => x"f8", + 5986 => x"fe", + 5987 => x"79", + 5988 => x"59", + 5989 => x"f6", + 5990 => x"79", + 5991 => x"b7", + 5992 => x"11", + 5993 => x"05", + 5994 => x"ef", + 5995 => x"c0", + 5996 => x"91", + 5997 => x"02", + 5998 => x"33", + 5999 => x"81", + 6000 => x"b5", + 6001 => x"8c", + 6002 => x"f6", + 6003 => x"39", + 6004 => x"e8", + 6005 => x"f8", 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x"3f", + 6065 => x"08", + 6066 => x"b7", + 6067 => x"08", + 6068 => x"d8", + 6069 => x"f6", + 6070 => x"f8", + 6071 => x"fe", + 6072 => x"79", + 6073 => x"59", + 6074 => x"f4", + 6075 => x"79", + 6076 => x"b7", + 6077 => x"11", + 6078 => x"05", + 6079 => x"8d", + 6080 => x"c0", + 6081 => x"8d", + 6082 => x"71", + 6083 => x"84", + 6084 => x"b9", + 6085 => x"8c", + 6086 => x"a6", + 6087 => x"39", + 6088 => x"f4", + 6089 => x"f8", + 6090 => x"f7", + 6091 => x"de", + 6092 => x"df", + 6093 => x"d4", + 6094 => x"80", + 6095 => x"81", + 6096 => x"44", + 6097 => x"81", + 6098 => x"59", + 6099 => x"88", + 6100 => x"94", + 6101 => x"39", + 6102 => x"33", + 6103 => x"2e", + 6104 => x"db", + 6105 => x"ab", + 6106 => x"d7", + 6107 => x"80", + 6108 => x"81", + 6109 => x"44", + 6110 => x"db", + 6111 => x"78", + 6112 => x"38", + 6113 => x"08", + 6114 => x"81", + 6115 => x"fc", + 6116 => x"b7", + 6117 => x"11", + 6118 => x"05", + 6119 => x"fb", + 6120 => x"c0", + 6121 => x"38", + 6122 => x"33", + 6123 => x"2e", + 6124 => x"db", + 6125 => x"80", + 6126 => x"db", + 6127 => x"78", + 6128 => x"38", + 6129 => x"08", + 6130 => x"81", + 6131 => x"59", + 6132 => x"88", + 6133 => x"a0", + 6134 => x"39", + 6135 => x"33", + 6136 => x"2e", + 6137 => x"db", + 6138 => x"99", + 6139 => x"d2", + 6140 => x"80", + 6141 => x"81", + 6142 => x"43", + 6143 => x"db", + 6144 => x"05", + 6145 => x"fe", + 6146 => x"fe", + 6147 => x"fe", + 6148 => x"81", + 6149 => x"86", + 6150 => x"c0", + 6151 => x"d8", + 6152 => x"ee", + 6153 => x"5a", + 6154 => x"9d", + 6155 => x"59", + 6156 => x"09", + 6157 => x"38", + 6158 => x"52", + 6159 => x"51", + 6160 => x"3f", + 6161 => x"e0", + 6162 => x"9c", + 6163 => x"81", + 6164 => x"fe", + 6165 => x"82", + 6166 => x"da", + 6167 => x"39", + 6168 => x"51", + 6169 => x"3f", + 6170 => x"ec", + 6171 => x"93", + 6172 => x"81", + 6173 => x"94", + 6174 => x"80", + 6175 => x"c0", + 6176 => x"81", + 6177 => x"fe", + 6178 => x"f0", + 6179 => x"d9", + 6180 => x"ed", + 6181 => x"80", + 6182 => x"c0", + 6183 => x"8c", + 6184 => x"87", + 6185 => x"0c", + 6186 => x"b7", + 6187 => x"11", + 6188 => x"05", + 6189 => x"e3", + 6190 => x"c0", + 6191 => x"f0", + 6192 => x"52", + 6193 => x"51", + 6194 => x"3f", + 6195 => x"04", + 6196 => x"f4", + 6197 => x"f8", + 6198 => x"f4", + 6199 => x"de", + 6200 => x"2e", + 6201 => x"63", + 6202 => x"c0", + 6203 => x"b6", + 6204 => x"78", + 6205 => x"c0", + 6206 => x"de", + 6207 => x"2e", + 6208 => x"81", + 6209 => x"52", + 6210 => x"51", + 6211 => x"3f", + 6212 => x"81", + 6213 => x"fe", + 6214 => x"fe", + 6215 => x"ef", + 6216 => x"da", + 6217 => x"ec", + 6218 => x"59", + 6219 => x"fe", + 6220 => x"ef", + 6221 => x"70", + 6222 => x"78", + 6223 => x"c3", + 6224 => x"2e", + 6225 => x"81", + 6226 => x"5a", + 6227 => x"2e", + 6228 => x"b7", + 6229 => x"05", + 6230 => x"f8", + 6231 => x"c0", + 6232 => x"5b", + 6233 => x"b2", + 6234 => x"24", + 6235 => x"81", + 6236 => x"80", + 6237 => x"83", + 6238 => x"80", + 6239 => x"da", + 6240 => x"55", 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6417 => x"29", + 6418 => x"20", + 6419 => x"53", + 6420 => x"41", + 6421 => x"20", + 6422 => x"65", + 6423 => x"65", + 6424 => x"25", + 6425 => x"29", + 6426 => x"20", + 6427 => x"54", + 6428 => x"52", + 6429 => x"20", + 6430 => x"69", + 6431 => x"73", + 6432 => x"25", + 6433 => x"29", + 6434 => x"20", + 6435 => x"49", + 6436 => x"20", + 6437 => x"4c", + 6438 => x"68", + 6439 => x"65", + 6440 => x"25", + 6441 => x"29", + 6442 => x"20", + 6443 => x"57", + 6444 => x"42", + 6445 => x"20", + 6446 => x"0a", + 6447 => x"20", + 6448 => x"57", + 6449 => x"32", + 6450 => x"20", + 6451 => x"49", + 6452 => x"4c", + 6453 => x"20", + 6454 => x"50", + 6455 => x"00", + 6456 => x"20", + 6457 => x"53", + 6458 => x"00", + 6459 => x"41", + 6460 => x"65", + 6461 => x"73", + 6462 => x"20", + 6463 => x"43", + 6464 => x"52", + 6465 => x"74", + 6466 => x"63", + 6467 => x"20", + 6468 => x"72", + 6469 => x"20", + 6470 => x"30", + 6471 => x"00", + 6472 => x"20", + 6473 => x"43", + 6474 => x"4d", + 6475 => x"72", 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x"64", + 6535 => x"34", + 6536 => x"7a", + 6537 => x"53", + 6538 => x"6c", + 6539 => x"4d", + 6540 => x"75", + 6541 => x"46", + 6542 => x"00", + 6543 => x"45", + 6544 => x"45", + 6545 => x"69", + 6546 => x"55", + 6547 => x"6f", + 6548 => x"53", + 6549 => x"22", + 6550 => x"3a", + 6551 => x"3e", + 6552 => x"7c", + 6553 => x"46", + 6554 => x"46", + 6555 => x"32", + 6556 => x"eb", + 6557 => x"53", + 6558 => x"35", + 6559 => x"4e", + 6560 => x"41", + 6561 => x"20", + 6562 => x"41", + 6563 => x"20", + 6564 => x"4e", + 6565 => x"41", + 6566 => x"20", + 6567 => x"41", + 6568 => x"20", + 6569 => x"00", + 6570 => x"00", + 6571 => x"00", + 6572 => x"00", + 6573 => x"80", + 6574 => x"8e", + 6575 => x"45", + 6576 => x"49", + 6577 => x"90", + 6578 => x"99", + 6579 => x"59", + 6580 => x"9c", + 6581 => x"41", + 6582 => x"a5", + 6583 => x"a8", + 6584 => x"ac", + 6585 => x"b0", + 6586 => x"b4", + 6587 => x"b8", + 6588 => x"bc", + 6589 => x"c0", + 6590 => x"c4", + 6591 => x"c8", + 6592 => x"cc", + 6593 => x"d0", + 6594 => x"d4", + 6595 => x"d8", + 6596 => x"dc", + 6597 => x"e0", + 6598 => x"e4", + 6599 => x"e8", + 6600 => x"ec", + 6601 => x"f0", + 6602 => x"f4", + 6603 => x"f8", + 6604 => x"fc", + 6605 => x"2b", + 6606 => x"3d", + 6607 => x"5c", + 6608 => x"3c", + 6609 => x"7f", + 6610 => x"00", + 6611 => x"00", + 6612 => x"01", + 6613 => x"00", + 6614 => x"00", + 6615 => x"00", + 6616 => x"00", + 6617 => x"00", + 6618 => x"64", + 6619 => x"74", + 6620 => x"64", + 6621 => x"74", + 6622 => x"66", + 6623 => x"74", + 6624 => x"66", + 6625 => x"64", + 6626 => x"66", + 6627 => x"63", + 6628 => x"6d", + 6629 => x"61", + 6630 => x"6d", + 6631 => x"70", + 6632 => x"6d", + 6633 => x"68", + 6634 => x"6d", + 6635 => x"6d", + 6636 => x"6d", + 6637 => x"68", + 6638 => x"68", + 6639 => x"68", + 6640 => x"68", + 6641 => x"63", + 6642 => x"00", + 6643 => x"6a", + 6644 => x"72", + 6645 => x"61", + 6646 => x"72", + 6647 => x"74", + 6648 => x"69", + 6649 => x"00", + 6650 => x"74", + 6651 => x"00", + 6652 => x"44", + 6653 => x"20", + 6654 => x"6f", + 6655 => x"49", + 6656 => x"72", + 6657 => x"20", + 6658 => x"6f", + 6659 => x"00", + 6660 => x"44", + 6661 => x"20", + 6662 => x"20", + 6663 => x"64", + 6664 => x"00", + 6665 => x"4e", + 6666 => x"69", + 6667 => x"66", + 6668 => x"64", + 6669 => x"4e", + 6670 => x"61", + 6671 => x"66", + 6672 => x"64", + 6673 => x"49", + 6674 => x"6c", + 6675 => x"66", + 6676 => x"6e", + 6677 => x"2e", + 6678 => x"41", + 6679 => x"73", + 6680 => x"65", + 6681 => x"64", + 6682 => x"46", + 6683 => x"20", + 6684 => x"65", + 6685 => x"20", + 6686 => x"73", + 6687 => x"0a", + 6688 => x"46", + 6689 => x"20", + 6690 => x"64", + 6691 => x"69", + 6692 => x"6c", + 6693 => x"0a", + 6694 => x"53", + 6695 => x"73", + 6696 => x"69", + 6697 => x"70", + 6698 => x"65", + 6699 => x"64", + 6700 => x"44", + 6701 => x"65", + 6702 => x"6d", + 6703 => x"20", + 6704 => x"69", + 6705 => x"6c", + 6706 => x"0a", + 6707 => x"44", + 6708 => x"20", + 6709 => x"20", + 6710 => x"62", + 6711 => x"2e", + 6712 => x"4e", + 6713 => x"6f", + 6714 => x"74", + 6715 => x"65", + 6716 => x"6c", + 6717 => x"73", + 6718 => x"20", + 6719 => x"6e", + 6720 => x"6e", + 6721 => x"73", + 6722 => x"00", + 6723 => x"46", + 6724 => x"61", + 6725 => x"62", + 6726 => x"65", + 6727 => x"00", + 6728 => x"54", + 6729 => x"6f", + 6730 => x"20", + 6731 => x"72", + 6732 => x"6f", + 6733 => x"61", + 6734 => x"6c", + 6735 => x"2e", + 6736 => x"46", + 6737 => x"20", + 6738 => x"6c", + 6739 => x"65", + 6740 => x"00", + 6741 => x"49", + 6742 => x"66", + 6743 => x"69", + 6744 => x"20", + 6745 => x"6f", + 6746 => x"0a", + 6747 => x"54", + 6748 => x"6d", + 6749 => x"20", + 6750 => x"6e", + 6751 => x"6c", + 6752 => x"0a", + 6753 => x"50", + 6754 => x"6d", + 6755 => x"72", + 6756 => x"6e", + 6757 => x"72", + 6758 => x"2e", + 6759 => x"53", + 6760 => x"65", + 6761 => x"0a", + 6762 => x"55", + 6763 => x"6f", + 6764 => x"65", + 6765 => x"72", + 6766 => x"0a", + 6767 => x"20", + 6768 => x"65", + 6769 => x"73", + 6770 => x"20", + 6771 => x"20", + 6772 => x"65", + 6773 => x"65", + 6774 => x"00", + 6775 => x"25", + 6776 => x"00", + 6777 => x"3a", + 6778 => x"25", + 6779 => x"00", + 6780 => x"20", + 6781 => x"20", + 6782 => x"00", + 6783 => x"25", + 6784 => x"00", + 6785 => x"20", + 6786 => x"20", + 6787 => x"7c", + 6788 => x"72", + 6789 => x"00", + 6790 => x"5a", + 6791 => x"41", + 6792 => x"0a", + 6793 => x"25", + 6794 => x"00", + 6795 => x"32", + 6796 => x"32", + 6797 => x"31", + 6798 => x"76", + 6799 => x"00", + 6800 => x"20", + 6801 => x"2c", + 6802 => x"76", + 6803 => x"32", + 6804 => x"25", + 6805 => x"73", + 6806 => x"0a", + 6807 => x"5a", + 6808 => x"41", + 6809 => x"74", + 6810 => x"75", + 6811 => x"48", + 6812 => x"6c", + 6813 => x"00", + 6814 => x"54", + 6815 => x"72", + 6816 => x"74", + 6817 => x"75", + 6818 => x"00", + 6819 => x"50", + 6820 => x"69", + 6821 => x"72", + 6822 => x"74", + 6823 => x"49", + 6824 => x"4c", + 6825 => x"20", + 6826 => x"65", + 6827 => x"70", + 6828 => x"49", + 6829 => x"4c", + 6830 => x"20", + 6831 => x"65", + 6832 => x"70", + 6833 => x"55", + 6834 => x"30", + 6835 => x"20", + 6836 => x"65", + 6837 => x"70", + 6838 => x"55", + 6839 => x"30", + 6840 => x"20", + 6841 => x"65", + 6842 => x"70", + 6843 => x"55", + 6844 => x"31", + 6845 => x"20", + 6846 => x"65", + 6847 => x"70", + 6848 => x"55", + 6849 => x"31", + 6850 => x"20", + 6851 => x"65", + 6852 => x"70", + 6853 => x"53", + 6854 => x"69", + 6855 => x"75", + 6856 => x"69", + 6857 => x"2e", + 6858 => x"00", + 6859 => x"45", + 6860 => x"6c", + 6861 => x"20", + 6862 => x"65", + 6863 => x"2e", + 6864 => x"61", + 6865 => x"65", + 6866 => x"2e", + 6867 => x"00", + 6868 => x"30", + 6869 => x"46", + 6870 => x"65", + 6871 => x"6f", + 6872 => x"69", + 6873 => x"6c", + 6874 => x"20", + 6875 => x"63", + 6876 => x"20", + 6877 => x"70", + 6878 => x"73", + 6879 => x"6e", + 6880 => x"6d", + 6881 => x"61", + 6882 => x"2e", + 6883 => x"2a", + 6884 => x"42", + 6885 => x"64", + 6886 => x"20", + 6887 => x"0a", + 6888 => x"49", + 6889 => x"69", + 6890 => x"73", + 6891 => x"0a", + 6892 => x"46", + 6893 => x"65", + 6894 => x"6f", + 6895 => x"69", + 6896 => x"6c", + 6897 => x"2e", + 6898 => x"72", + 6899 => x"64", + 6900 => x"25", + 6901 => x"43", + 6902 => x"72", + 6903 => x"2e", + 6904 => x"00", + 6905 => x"44", + 6906 => x"20", + 6907 => x"6f", + 6908 => x"00", + 6909 => x"0a", + 6910 => x"70", + 6911 => x"65", + 6912 => x"25", + 6913 => x"20", + 6914 => x"58", + 6915 => x"3f", + 6916 => x"00", + 6917 => x"25", + 6918 => x"20", + 6919 => x"58", + 6920 => x"25", + 6921 => x"20", + 6922 => x"58", + 6923 => x"53", + 6924 => x"63", + 6925 => x"67", + 6926 => x"00", + 6927 => x"25", + 6928 => x"78", + 6929 => x"30", + 6930 => x"0a", + 6931 => x"44", + 6932 => x"62", + 6933 => x"67", + 6934 => x"74", + 6935 => x"75", + 6936 => x"0a", + 6937 => x"45", + 6938 => x"6c", + 6939 => x"20", + 6940 => x"65", + 6941 => x"70", + 6942 => x"00", + 6943 => x"44", + 6944 => x"62", + 6945 => x"20", + 6946 => x"74", + 6947 => x"66", + 6948 => x"45", + 6949 => x"6c", + 6950 => x"20", + 6951 => x"74", + 6952 => x"66", + 6953 => x"45", + 6954 => x"75", + 6955 => x"67", + 6956 => x"64", + 6957 => x"20", + 6958 => x"78", + 6959 => x"2e", + 6960 => x"43", + 6961 => x"69", + 6962 => x"63", + 6963 => x"20", + 6964 => x"30", + 6965 => x"2e", + 6966 => x"00", + 6967 => x"43", + 6968 => x"20", + 6969 => x"75", + 6970 => x"64", + 6971 => x"64", + 6972 => x"25", + 6973 => x"0a", + 6974 => x"52", + 6975 => x"61", + 6976 => x"6e", + 6977 => x"70", + 6978 => x"63", + 6979 => x"6f", + 6980 => x"2e", + 6981 => x"43", + 6982 => x"20", + 6983 => x"6f", + 6984 => x"6e", + 6985 => x"2e", + 6986 => x"5a", + 6987 => x"62", + 6988 => x"25", + 6989 => x"25", + 6990 => x"73", + 6991 => x"00", + 6992 => x"25", + 6993 => x"25", + 6994 => x"73", + 6995 => x"25", + 6996 => x"25", + 6997 => x"42", + 6998 => x"63", + 6999 => x"61", + 7000 => x"0a", + 7001 => x"52", + 7002 => x"69", + 7003 => x"2e", + 7004 => x"45", + 7005 => x"6c", + 7006 => x"20", + 7007 => x"65", + 7008 => x"70", + 7009 => x"2e", + 7010 => x"00", + 7011 => x"00", + 7012 => x"00", + 7013 => x"00", + 7014 => x"00", + 7015 => x"00", + 7016 => x"00", + 7017 => x"00", + 7018 => x"00", + 7019 => x"01", + 7020 => x"01", + 7021 => x"00", + 7022 => x"00", + 7023 => x"00", + 7024 => x"00", + 7025 => x"05", + 7026 => x"05", + 7027 => x"05", + 7028 => x"00", + 7029 => x"01", + 7030 => x"01", + 7031 => x"01", + 7032 => x"01", + 7033 => x"00", + 7034 => x"01", + 7035 => x"00", + 7036 => x"00", + 7037 => x"01", + 7038 => x"00", + 7039 => x"00", + 7040 => x"00", + 7041 => x"01", + 7042 => x"00", + 7043 => x"00", + 7044 => x"00", + 7045 => x"01", + 7046 => x"00", + 7047 => x"00", + 7048 => x"00", + 7049 => x"01", + 7050 => x"00", + 7051 => x"00", + 7052 => x"00", + 7053 => x"01", + 7054 => x"00", + 7055 => x"00", + 7056 => x"00", + 7057 => x"01", + 7058 => x"00", + 7059 => x"00", + 7060 => x"00", + 7061 => x"01", + 7062 => x"00", + 7063 => x"00", + 7064 => x"00", + 7065 => x"01", + 7066 => x"00", + 7067 => x"00", + 7068 => x"00", + 7069 => x"01", + 7070 => x"00", + 7071 => x"00", + 7072 => x"00", + 7073 => x"01", + 7074 => x"00", + 7075 => x"00", + 7076 => x"00", + 7077 => x"01", + 7078 => x"00", + 7079 => x"00", + 7080 => x"00", + 7081 => x"01", + 7082 => x"00", + 7083 => x"00", + 7084 => x"00", + 7085 => x"01", + 7086 => x"00", + 7087 => x"00", + 7088 => x"00", + 7089 => x"01", + 7090 => x"00", + 7091 => x"00", + 7092 => x"00", + 7093 => x"01", + 7094 => x"00", + 7095 => x"00", + 7096 => x"00", + 7097 => x"01", + 7098 => x"00", + 7099 => x"00", + 7100 => x"00", + 7101 => x"01", + 7102 => x"00", + 7103 => x"00", + 7104 => x"00", + 7105 => x"01", + 7106 => x"00", + 7107 => x"00", + 7108 => x"00", + 7109 => x"01", + 7110 => x"00", + 7111 => x"00", + 7112 => x"00", + 7113 => x"01", + 7114 => x"00", + 7115 => x"00", + 7116 => x"00", + 7117 => x"01", + 7118 => x"00", + 7119 => x"00", + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; +end arch; diff --git a/zpu/devices/sysbus/BRAM/byteaddr_dp_32bit_bram_tmpl.vhd b/zpu/devices/sysbus/BRAM/byteaddr_dp_32bit_bram_tmpl.vhd new file mode 100644 index 0000000..5170387 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/byteaddr_dp_32bit_bram_tmpl.vhd @@ -0,0 +1,226 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity byteaddr_dp_32bit_bram is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + + memBAddr : in std_logic_vector(addrbits-1 downto 2); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBRead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end byteaddr_dp_32bit_bram; + +architecture arch of byteaddr_dp_32bit_bram is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 0 - Port B - bits 7 downto 0 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM0(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(7 downto 0); + memBRead(7 downto 0) <= memBWrite(7 downto 0); + else + memBRead(7 downto 0) <= RAM0(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 1 - Port B - bits 15 downto 8 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM1(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(15 downto 8); + memBRead(15 downto 8) <= memBWrite(15 downto 8); + else + memBRead(15 downto 8) <= RAM1(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 2 - Port B - bits 23 downto 16 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM2(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(23 downto 16); + memBRead(23 downto 16) <= memBWrite(23 downto 16); + else + memBRead(23 downto 16) <= RAM2(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 3 - Port B - bits 31 downto 24 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM3(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(31 downto 24); + memBRead(31 downto 24) <= memBWrite(31 downto 24); + else + memBRead(31 downto 24) <= RAM3(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + +end arch; diff --git a/zpu/devices/sysbus/BRAM/byteaddr_sp_32bit_bram_tmpl.vhd b/zpu/devices/sysbus/BRAM/byteaddr_sp_32bit_bram_tmpl.vhd new file mode 100644 index 0000000..96e63e6 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/byteaddr_sp_32bit_bram_tmpl.vhd @@ -0,0 +1,168 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity byteaddr_sp_32bit_bram is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end byteaddr_sp_32bit_bram; + +architecture arch of byteaddr_sp_32bit_bram is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; +end arch; diff --git a/zpu/devices/sysbus/BRAM/dualport_rom_epilogue_byteaddr.vhd b/zpu/devices/sysbus/BRAM/dualport_rom_epilogue_byteaddr.vhd new file mode 100644 index 0000000..196e4c3 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/dualport_rom_epilogue_byteaddr.vhd @@ -0,0 +1,40 @@ + others => x"00000000" +); + +begin + + process (clk) + begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') then + -- Memory writes are 32bit (default), 16bit or 8 bit. + -- + if (memAWriteByte = '1') then + ram(to_integer(unsigned(memAAddr(addrbits-1 downto 2))))(((wordBytes-1-to_integer(unsigned(memAAddr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(memAAddr(byteBits-1 downto 0))))*8) := memAWrite(7 downto 0); + elsif (memAWriteHalfWord = '1') then + ram(to_integer(unsigned(memAAddr(addrbits-1 downto 2))))(((wordBytes-1-to_integer(unsigned(memAAddr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(memAAddr(byteBits-1 downto 1))))*16) := memAWrite(15 downto 0); + else + ram(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := memAWrite; + end if; + memARead <= memAWrite; + else + -- Memory reads are always 32bit. + memARead <= ram(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + process (clk) + begin + if (clk'event and clk = '1') then + -- 2nd port reads and writes are always 32bit. + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; +end arch; + diff --git a/zpu/devices/sysbus/BRAM/dualport_rom_prologue_byteaddr.vhd b/zpu/devices/sysbus/BRAM/dualport_rom_prologue_byteaddr.vhd new file mode 100644 index 0000000..bb88424 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/dualport_rom_prologue_byteaddr.vhd @@ -0,0 +1,71 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com +-- Modified by Philip Smart 02/2019 for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity dualportram is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + + memBAddr : in std_logic_vector(addrbits-1 downto 2); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBRead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end dualportram; + +architecture arch of dualportram is + +type ram_type is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(WORD_32BIT_RANGE); + +shared variable ram : ram_type := +( diff --git a/zpu/devices/sysbus/BRAM/rom_epilogue.vhd b/zpu/devices/sysbus/BRAM/rom_epilogue.vhd new file mode 100644 index 0000000..7d67dda --- /dev/null +++ b/zpu/devices/sysbus/BRAM/rom_epilogue.vhd @@ -0,0 +1,36 @@ + others => x"00000000" + ); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + + +end arch; + diff --git a/zpu/devices/sysbus/BRAM/rom_epilogue_byteaddr.vhd b/zpu/devices/sysbus/BRAM/rom_epilogue_byteaddr.vhd new file mode 100644 index 0000000..cb5573f --- /dev/null +++ b/zpu/devices/sysbus/BRAM/rom_epilogue_byteaddr.vhd @@ -0,0 +1,44 @@ + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + -- Memory writes are 32bit (default), 16bit or 8 bit. + -- + if (memAWriteEnable = '1') then + if (memAWriteByte = '1') then + ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE))))(((wordBytes-1-to_integer(unsigned(memAAddr(byteBits-1 downto 0))))*8+7) downto (wordBytes-1-to_integer(unsigned(memAAddr(byteBits-1 downto 0))))*8) := memAWrite(7 downto 0); + elsif (memAWriteWord = '1') then + ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE))))(((wordBytes-1-to_integer(unsigned(memAAddr(byteBits-1 downto 1))))*16+15) downto (wordBytes-1-to_integer(unsigned(memAAddr(byteBits-1 downto 1))))*16) := memAWrite(15 downto 0); + else + ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))) := memAWrite; + end if; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + + +end arch; + diff --git a/zpu/devices/sysbus/BRAM/rom_prologue.vhd b/zpu/devices/sysbus/BRAM/rom_prologue.vhd new file mode 100644 index 0000000..14597b6 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/rom_prologue.vhd @@ -0,0 +1,64 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com +-- Modified by Philip Smart 02/2019 for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity dualportram is +port ( + clk : in std_logic; + areset : in std_logic := '0'; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + memBRead : out std_logic_vector(WORD_32BIT_RANGE) +); +end dualportram; + +architecture arch of dualportram is + +type ram_type is array(natural range 0 to (2**(SOC_MAX_ADDR_BRAM_BIT-2))-1) of std_logic_vector(WORD_32BIT_RANGE); + +shared variable ram : ram_type := +( diff --git a/zpu/devices/sysbus/BRAM/rom_prologue_byteaddr.vhd b/zpu/devices/sysbus/BRAM/rom_prologue_byteaddr.vhd new file mode 100644 index 0000000..2e700ec --- /dev/null +++ b/zpu/devices/sysbus/BRAM/rom_prologue_byteaddr.vhd @@ -0,0 +1,67 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com +-- Modified by Philip Smart 02/2019 for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity dualportram is +port ( + clk : in std_logic; + areset : in std_logic := '0'; + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteWord : in std_logic; + memAAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBRead : out std_logic_vector(WORD_32BIT_RANGE) +); +end dualportram; + +architecture arch of dualportram is + +type ram_type is array(natural range 0 to (2**(SOC_MAX_ADDR_BRAM_BIT-2))-1) of std_logic_vector(WORD_32BIT_RANGE); + +shared variable ram : ram_type := +( diff --git a/zpu/devices/sysbus/BRAM/zOS_BootROM.vhd b/zpu/devices/sysbus/BRAM/zOS_BootROM.vhd new file mode 100644 index 0000000..29c4595 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/zOS_BootROM.vhd @@ -0,0 +1,8479 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com +-- Modified by Philip Smart 02/2019 for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity BootROM is +port ( + clk : in std_logic; + areset : in std_logic := '0'; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(ADDR_32BIT_BRAM_RANGE); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + memBRead : out std_logic_vector(WORD_32BIT_RANGE) +); +end BootROM; + +architecture arch of BootROM is + +type ram_type is array(natural range 0 to (2**(SOC_MAX_ADDR_BRAM_BIT-2))-1) of std_logic_vector(WORD_32BIT_RANGE); + +shared variable ram : ram_type := +( + 0 => x"0b0b83ff", + 1 => x"f80d0b0b", + 2 => x"0b939b04", + 3 => x"00000000", + 4 => x"00000000", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"88088c08", + 9 => x"90088880", + 10 => x"082d900c", + 11 => x"8c0c880c", + 12 => x"04000000", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a50400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"09810572", + 51 => x"0a100a72", + 52 => x"0a100a31", + 53 => x"050a8106", + 54 => x"51515351", + 55 => x"04000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b92", + 73 => x"ff040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b92e2", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"04067383", + 106 => x"06098105", + 107 => x"8205832b", + 108 => x"0b2b0772", + 109 => x"fc060c51", + 110 => x"51040000", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b81e7", + 162 => x"fc738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"92e70400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"88088c08", + 169 => x"90087575", + 170 => x"0b0b0b99", + 171 => x"fb2d5050", + 172 => x"88085690", + 173 => x"0c8c0c88", + 174 => x"0c510400", + 175 => x"00000000", + 176 => x"88088c08", + 177 => x"90087575", + 178 => x"0b0b0b9b", + 179 => x"e72d5050", + 180 => x"88085690", + 181 => x"0c8c0c88", + 182 => x"0c510400", + 183 => x"00000000", + 184 => x"72097081", + 185 => x"0509060a", + 186 => x"8106ff05", + 187 => x"70547106", + 188 => x"73097274", + 189 => x"05ff0506", + 190 => x"07515151", + 191 => x"04000000", + 192 => x"72097081", + 193 => x"0509060a", + 194 => x"098106ff", + 195 => x"05705471", + 196 => x"06730972", + 197 => x"7405ff05", + 198 => x"06075151", + 199 => x"51040000", + 200 => x"05ff0504", + 201 => x"00000000", + 202 => x"00000000", + 203 => x"00000000", + 204 => x"00000000", + 205 => x"00000000", + 206 => x"00000000", + 207 => x"00000000", + 208 => x"04000000", + 209 => x"00000000", + 210 => x"00000000", + 211 => x"00000000", + 212 => x"00000000", + 213 => x"00000000", + 214 => x"00000000", + 215 => x"00000000", + 216 => x"71810552", + 217 => x"04000000", + 218 => x"00000000", + 219 => x"00000000", + 220 => x"00000000", + 221 => x"00000000", + 222 => x"00000000", + 223 => x"00000000", + 224 => x"04000000", + 225 => x"00000000", + 226 => x"00000000", + 227 => x"00000000", + 228 => x"00000000", + 229 => x"00000000", + 230 => x"00000000", + 231 => x"00000000", + 232 => x"02840572", + 233 => x"10100552", + 234 => x"04000000", + 235 => x"00000000", + 236 => x"00000000", + 237 => x"00000000", + 238 => x"00000000", + 239 => x"00000000", + 240 => x"00000000", + 241 => x"00000000", + 242 => x"00000000", + 243 => x"00000000", + 244 => x"00000000", + 245 => x"00000000", + 246 => x"00000000", + 247 => x"00000000", + 248 => x"717105ff", + 249 => x"05715351", + 250 => x"020d04ff", + 251 => x"ffffffff", + 252 => x"ffffffff", + 253 => x"ffffffff", + 254 => x"ffffffff", + 255 => x"ffffffff", + 256 => x"00000600", + 257 => x"ffffffff", + 258 => x"ffffffff", + 259 => x"ffffffff", + 260 => x"ffffffff", + 261 => x"ffffffff", + 262 => x"ffffffff", + 263 => x"ffffffff", + 264 => x"0b0b0b8c", + 265 => x"81040b0b", + 266 => x"0b8c8504", + 267 => x"0b0b0b8c", + 268 => x"95040b0b", + 269 => x"0b8ca504", + 270 => x"0b0b0b8c", + 271 => x"b5040b0b", + 272 => x"0b8cc504", + 273 => x"0b0b0b8c", + 274 => x"d5040b0b", + 275 => x"0b8ce504", + 276 => x"0b0b0b8c", + 277 => x"f5040b0b", + 278 => x"0b8d8504", + 279 => x"0b0b0b8d", + 280 => x"95040b0b", + 281 => x"0b8da504", + 282 => x"0b0b0b8d", + 283 => x"b5040b0b", + 284 => x"0b8dc504", + 285 => x"0b0b0b8d", + 286 => x"d5040b0b", + 287 => x"0b8de504", + 288 => x"0b0b0b8d", + 289 => x"f5040b0b", + 290 => x"0b8e8404", + 291 => x"0b0b0b8e", + 292 => x"93040b0b", + 293 => x"0b8ea204", + 294 => x"0b0b0b8e", + 295 => x"b2040b0b", + 296 => x"0b8ec204", + 297 => x"0b0b0b8e", + 298 => x"d2040b0b", + 299 => x"0b8ee204", + 300 => x"0b0b0b8e", + 301 => x"f2040b0b", + 302 => x"0b8f8204", + 303 => x"0b0b0b8f", + 304 => x"92040b0b", + 305 => x"0b8fa204", + 306 => x"0b0b0b8f", + 307 => x"b2040b0b", + 308 => x"0b8fc204", + 309 => x"0b0b0b8f", + 310 => x"d2040b0b", + 311 => x"0b8fe204", + 312 => x"0b0b0b8f", + 313 => x"f2040b0b", + 314 => x"0b908204", + 315 => x"0b0b0b90", + 316 => x"92040b0b", + 317 => x"0b90a204", + 318 => x"0b0b0b90", + 319 => x"b2040b0b", + 320 => x"0b90c204", + 321 => x"0b0b0b90", + 322 => x"d2040b0b", + 323 => x"0b90e204", + 324 => x"0b0b0b90", + 325 => x"f2040b0b", + 326 => x"0b918204", + 327 => x"0b0b0b91", + 328 => x"92040b0b", + 329 => x"0b91a204", + 330 => x"0b0b0b91", + 331 => x"b2040b0b", + 332 => x"0b91c204", + 333 => x"0b0b0b91", + 334 => x"d2040b0b", + 335 => x"0b91e204", + 336 => x"0b0b0b91", + 337 => x"f2040b0b", + 338 => x"0b928204", + 339 => x"0b0b0b92", + 340 => x"91040b0b", + 341 => x"0b92a004", + 342 => x"0b0b0b92", + 343 => x"b004ffff", + 344 => x"ffffffff", + 345 => x"ffffffff", + 346 => x"ffffffff", + 347 => x"ffffffff", + 348 => x"ffffffff", + 349 => x"ffffffff", + 350 => x"ffffffff", + 351 => x"ffffffff", + 352 => x"ffffffff", + 353 => x"ffffffff", + 354 => x"ffffffff", + 355 => x"ffffffff", + 356 => x"ffffffff", + 357 => x"ffffffff", + 358 => x"ffffffff", + 359 => x"ffffffff", + 360 => x"ffffffff", + 361 => x"ffffffff", + 362 => x"ffffffff", + 363 => x"ffffffff", + 364 => x"ffffffff", + 365 => x"ffffffff", + 366 => x"ffffffff", + 367 => x"ffffffff", + 368 => x"ffffffff", + 369 => x"ffffffff", + 370 => x"ffffffff", + 371 => x"ffffffff", + 372 => x"ffffffff", + 373 => x"ffffffff", + 374 => x"ffffffff", + 375 => x"ffffffff", + 376 => x"ffffffff", + 377 => x"ffffffff", + 378 => x"ffffffff", + 379 => x"ffffffff", + 380 => x"ffffffff", + 381 => x"ffffffff", + 382 => x"ffffffff", + 383 => x"ffffffff", + 384 => x"04008c81", + 385 => x"048285f8", + 386 => x"0c80c18c", + 387 => x"2d8285f8", + 388 => x"0882a090", + 389 => x"048285f8", + 390 => x"0c80ce8e", + 391 => x"2d8285f8", + 392 => x"0882a090", + 393 => x"048285f8", + 394 => x"0c80cecd", + 395 => x"2d8285f8", + 396 => x"0882a090", + 397 => x"048285f8", + 398 => x"0c80ceeb", + 399 => x"2d8285f8", + 400 => x"0882a090", + 401 => x"048285f8", + 402 => x"0c80d5b5", + 403 => x"2d8285f8", + 404 => x"0882a090", + 405 => x"048285f8", + 406 => x"0c80d6b6", + 407 => x"2d8285f8", + 408 => x"0882a090", + 409 => x"048285f8", + 410 => x"0c80cf8e", + 411 => x"2d8285f8", + 412 => x"0882a090", + 413 => x"048285f8", + 414 => x"0c80d6d3", + 415 => x"2d8285f8", + 416 => x"0882a090", + 417 => x"048285f8", + 418 => x"0c80d8cf", + 419 => x"2d8285f8", + 420 => x"0882a090", + 421 => x"048285f8", + 422 => x"0c80d4db", + 423 => x"2d8285f8", + 424 => x"0882a090", + 425 => x"048285f8", + 426 => x"0c80cfc0", + 427 => x"2d8285f8", + 428 => x"0882a090", + 429 => x"048285f8", + 430 => x"0c80d4f1", + 431 => x"2d8285f8", + 432 => x"0882a090", + 433 => x"048285f8", + 434 => x"0c80d595", + 435 => x"2d8285f8", + 436 => x"0882a090", + 437 => x"048285f8", + 438 => x"0c80c395", + 439 => x"2d8285f8", + 440 => x"0882a090", + 441 => x"048285f8", + 442 => x"0c80c3e4", + 443 => x"2d8285f8", + 444 => x"0882a090", + 445 => x"048285f8", + 446 => x"0cbbc42d", + 447 => x"8285f808", + 448 => x"82a09004", + 449 => x"8285f80c", + 450 => x"bdbd2d82", + 451 => x"85f80882", + 452 => x"a0900482", + 453 => x"85f80cbe", + 454 => x"f02d8285", + 455 => x"f80882a0", + 456 => x"90048285", + 457 => x"f80c81aa", + 458 => x"bc2d8285", + 459 => x"f80882a0", + 460 => x"90048285", + 461 => x"f80c81b7", + 462 => x"af2d8285", + 463 => x"f80882a0", + 464 => x"90048285", + 465 => x"f80c81af", + 466 => x"a32d8285", + 467 => x"f80882a0", + 468 => x"90048285", + 469 => x"f80c81b2", + 470 => x"a02d8285", + 471 => x"f80882a0", + 472 => x"90048285", + 473 => x"f80c81bc", + 474 => x"bd2d8285", + 475 => x"f80882a0", + 476 => x"90048285", + 477 => x"f80c81c5", + 478 => x"a82d8285", + 479 => x"f80882a0", + 480 => x"90048285", + 481 => x"f80c81b6", + 482 => x"912d8285", + 483 => x"f80882a0", + 484 => x"90048285", + 485 => x"f80c81bf", + 486 => x"de2d8285", + 487 => x"f80882a0", + 488 => x"90048285", + 489 => x"f80c81c0", + 490 => x"fd2d8285", + 491 => x"f80882a0", + 492 => x"90048285", + 493 => x"f80c81c1", + 494 => x"9c2d8285", + 495 => x"f80882a0", + 496 => x"90048285", + 497 => x"f80c81c9", + 498 => x"912d8285", + 499 => x"f80882a0", + 500 => x"90048285", + 501 => x"f80c81c6", + 502 => x"f52d8285", + 503 => x"f80882a0", + 504 => x"90048285", + 505 => x"f80c81cb", + 506 => x"e52d8285", + 507 => x"f80882a0", + 508 => x"90048285", + 509 => x"f80c81c2", + 510 => x"a22d8285", + 511 => x"f80882a0", + 512 => x"90048285", + 513 => x"f80c81ce", + 514 => x"e52d8285", + 515 => x"f80882a0", + 516 => x"90048285", + 517 => x"f80c81cf", + 518 => x"e62d8285", + 519 => x"f80882a0", + 520 => x"90048285", + 521 => x"f80c81b8", + 522 => x"8f2d8285", + 523 => x"f80882a0", + 524 => x"90048285", + 525 => x"f80c81b7", + 526 => x"e82d8285", + 527 => x"f80882a0", + 528 => x"90048285", + 529 => x"f80c81b9", + 530 => x"932d8285", + 531 => x"f80882a0", + 532 => x"90048285", + 533 => x"f80c81c2", + 534 => x"f92d8285", + 535 => x"f80882a0", + 536 => x"90048285", + 537 => x"f80c81d0", + 538 => x"d72d8285", + 539 => x"f80882a0", + 540 => x"90048285", + 541 => x"f80c81d2", + 542 => x"e52d8285", + 543 => x"f80882a0", + 544 => x"90048285", + 545 => x"f80c81d6", + 546 => x"a72d8285", + 547 => x"f80882a0", + 548 => x"90048285", + 549 => x"f80c81a9", + 550 => x"db2d8285", + 551 => x"f80882a0", + 552 => x"90048285", + 553 => x"f80c81d9", + 554 => x"952d8285", + 555 => x"f80882a0", + 556 => x"90048285", + 557 => x"f80c81e7", + 558 => x"d92d8285", + 559 => x"f80882a0", + 560 => x"90048285", + 561 => x"f80c81e5", + 562 => x"c02d8285", + 563 => x"f80882a0", + 564 => x"90048285", + 565 => x"f80c80fa", + 566 => x"e82d8285", + 567 => x"f80882a0", + 568 => x"90048285", + 569 => x"f80c80fc", + 570 => x"d22d8285", + 571 => x"f80882a0", + 572 => x"90048285", + 573 => x"f80c80fe", + 574 => x"b62d8285", + 575 => x"f80882a0", + 576 => x"90048285", + 577 => x"f80cbbed", + 578 => x"2d8285f8", + 579 => x"0882a090", + 580 => x"048285f8", + 581 => x"0cbd932d", + 582 => x"8285f808", + 583 => x"82a09004", + 584 => x"8285f80c", + 585 => x"80c0802d", + 586 => x"8285f808", + 587 => x"82a09004", + 588 => x"8285f80c", + 589 => x"a1fd2d82", + 590 => x"85f80882", + 591 => x"a090043c", + 592 => x"04000010", + 593 => x"10101010", + 594 => x"10101010", + 595 => x"10101010", + 596 => x"10101010", + 597 => x"10101010", + 598 => x"10101010", + 599 => x"10101010", + 600 => x"10105351", + 601 => x"04000073", + 602 => x"81ff0673", + 603 => x"83060981", + 604 => x"05830510", + 605 => x"10102b07", + 606 => x"72fc060c", + 607 => x"51510472", + 608 => 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x"20202020", + 7980 => x"20202020", + 7981 => x"20202020", + 7982 => x"203d2025", + 7983 => x"3034580a", + 7984 => x"00000000", + 7985 => x"20202020", + 7986 => x"53797374", + 7987 => x"656d2043", + 7988 => x"6c6f636b", + 7989 => x"20467265", + 7990 => x"71202020", + 7991 => x"20202020", + 7992 => x"203d2025", + 7993 => x"642e2530", + 7994 => x"34644d48", + 7995 => x"7a0a0000", + 7996 => x"20202020", + 7997 => x"53445241", + 7998 => x"4d20436c", + 7999 => x"6f636b20", + 8000 => x"46726571", + 8001 => x"20202020", + 8002 => x"20202020", + 8003 => x"203d2025", + 8004 => x"642e2530", + 8005 => x"34644d48", + 8006 => x"7a0a0000", + 8007 => x"20202020", + 8008 => x"57697368", + 8009 => x"626f6e65", + 8010 => x"20534452", + 8011 => x"414d2043", + 8012 => x"6c6f636b", + 8013 => x"20467265", + 8014 => x"713d2025", + 8015 => x"642e2530", + 8016 => x"34644d48", + 8017 => x"7a0a0000", + 8018 => x"536d616c", + 8019 => x"6c000000", + 8020 => x"4d656469", + 8021 => x"756d0000", + 8022 => x"466c6578", + 8023 => x"00000000", + 8024 => x"45564f00", + 8025 => x"45564f6d", + 8026 => x"696e0000", + 8027 => x"556e6b6e", + 8028 => x"6f776e00", + 8029 => x"00007ed0", + 8030 => x"01000000", + 8031 => x"00000002", + 8032 => x"00007ecc", + 8033 => x"01000000", + 8034 => x"00000003", + 8035 => x"00007ec8", + 8036 => x"01000000", + 8037 => x"00000004", + 8038 => x"00007ec4", + 8039 => x"01000000", + 8040 => x"00000005", + 8041 => x"00007ec0", + 8042 => x"01000000", + 8043 => x"00000006", + 8044 => x"00007ebc", + 8045 => x"01000000", + 8046 => x"00000007", + 8047 => x"00007eb8", + 8048 => x"01000000", + 8049 => x"00000001", + 8050 => x"00007eb4", + 8051 => x"01000000", + 8052 => x"00000008", + 8053 => x"00007eb0", + 8054 => x"01000000", + 8055 => x"0000000b", + 8056 => x"00007eac", + 8057 => x"01000000", + 8058 => x"00000009", + 8059 => x"00007ea8", + 8060 => x"01000000", + 8061 => x"0000000a", + 8062 => x"00007ea4", + 8063 => x"04000000", + 8064 => x"0000000d", + 8065 => x"00007ea0", + 8066 => x"04000000", + 8067 => x"0000000c", + 8068 => x"00007e9c", + 8069 => x"04000000", + 8070 => x"0000000e", + 8071 => x"00007e98", + 8072 => x"03000000", + 8073 => x"0000000f", + 8074 => x"00007e94", + 8075 => x"04000000", + 8076 => x"0000000f", + 8077 => x"00007e90", + 8078 => x"04000000", + 8079 => x"00000010", + 8080 => x"00007e8c", + 8081 => x"04000000", + 8082 => x"00000011", + 8083 => x"00007e88", + 8084 => x"03000000", + 8085 => x"00000012", + 8086 => x"00007e84", + 8087 => x"03000000", + 8088 => x"00000013", + 8089 => x"00007e80", + 8090 => x"03000000", + 8091 => x"00000014", + 8092 => x"00007e7c", + 8093 => x"03000000", + 8094 => x"00000015", + 8095 => x"1b5b4400", + 8096 => x"1b5b4300", + 8097 => x"1b5b4200", + 8098 => x"1b5b4100", + 8099 => x"1b5b367e", + 8100 => x"1b5b357e", + 8101 => x"1b5b347e", + 8102 => x"1b304600", + 8103 => x"1b5b337e", + 8104 => x"1b5b327e", + 8105 => x"1b5b317e", + 8106 => x"10000000", + 8107 => x"0e000000", + 8108 => x"0d000000", + 8109 => x"0b000000", + 8110 => x"08000000", + 8111 => x"06000000", + 8112 => x"05000000", + 8113 => x"04000000", + 8114 => x"03000000", + 8115 => x"02000000", + 8116 => x"01000000", + 8117 => x"68697374", + 8118 => x"6f727900", + 8119 => x"68697374", + 8120 => x"00000000", + 8121 => x"21000000", + 8122 => x"25303464", + 8123 => x"20202573", + 8124 => x"0a000000", + 8125 => x"4661696c", + 8126 => x"65642074", + 8127 => x"6f207265", + 8128 => x"73657420", + 8129 => x"74686520", + 8130 => x"68697374", + 8131 => x"6f727920", + 8132 => x"66696c65", + 8133 => x"20746f20", + 8134 => x"454f462e", + 8135 => x"0a000000", + 8136 => x"43616e6e", + 8137 => x"6f74206f", + 8138 => x"70656e2f", + 8139 => x"63726561", + 8140 => x"74652068", + 8141 => x"6973746f", + 8142 => x"72792066", + 8143 => x"696c652c", + 8144 => x"20646973", + 8145 => x"61626c69", + 8146 => x"6e672e0a", + 8147 => x"00000000", + 8148 => x"53440000", + 8149 => x"222a2b2c", + 8150 => x"3a3b3c3d", + 8151 => x"3e3f5b5d", + 8152 => x"7c7f0000", + 8153 => x"46415400", + 8154 => x"46415433", + 8155 => x"32000000", + 8156 => x"ebfe904d", + 8157 => x"53444f53", + 8158 => x"352e3000", + 8159 => x"4e4f204e", + 8160 => x"414d4520", + 8161 => x"20202046", + 8162 => x"41543332", + 8163 => x"20202000", + 8164 => x"4e4f204e", + 8165 => x"414d4520", + 8166 => x"20202046", + 8167 => x"41542020", + 8168 => x"20202000", + 8169 => x"00007f50", + 8170 => x"00000000", + 8171 => x"00000000", + 8172 => x"00000000", + 8173 => x"809a4541", + 8174 => x"8e418f80", + 8175 => x"45454549", + 8176 => x"49498e8f", + 8177 => x"9092924f", + 8178 => x"994f5555", + 8179 => x"59999a9b", + 8180 => x"9c9d9e9f", + 8181 => x"41494f55", + 8182 => x"a5a5a6a7", + 8183 => x"a8a9aaab", + 8184 => x"acadaeaf", + 8185 => x"b0b1b2b3", + 8186 => x"b4b5b6b7", + 8187 => x"b8b9babb", + 8188 => x"bcbdbebf", + 8189 => x"c0c1c2c3", + 8190 => x"c4c5c6c7", + 8191 => x"c8c9cacb", + 8192 => x"cccdcecf", + 8193 => x"d0d1d2d3", + 8194 => x"d4d5d6d7", + 8195 => x"d8d9dadb", + 8196 => x"dcdddedf", + 8197 => x"e0e1e2e3", + 8198 => x"e4e5e6e7", + 8199 => x"e8e9eaeb", + 8200 => x"ecedeeef", + 8201 => x"f0f1f2f3", + 8202 => x"f4f5f6f7", + 8203 => x"f8f9fafb", + 8204 => x"fcfdfeff", + 8205 => x"2b2e2c3b", + 8206 => x"3d5b5d2f", + 8207 => x"5c222a3a", + 8208 => x"3c3e3f7c", + 8209 => x"7f000000", + 8210 => x"00010004", + 8211 => x"00100040", + 8212 => x"01000200", + 8213 => x"00000000", + 8214 => x"00010002", + 8215 => x"00040008", + 8216 => x"00100020", + 8217 => x"00000000", + 8218 => x"00000000", + 8219 => x"000074c8", + 8220 => x"01020100", + 8221 => x"00000000", + 8222 => x"00000000", + 8223 => x"000074d0", + 8224 => x"01040100", + 8225 => x"00000000", + 8226 => x"00000000", + 8227 => x"000074d8", + 8228 => x"01140300", + 8229 => x"00000000", + 8230 => x"00000000", + 8231 => x"000074e0", + 8232 => x"012b0300", + 8233 => x"00000000", + 8234 => x"00000000", + 8235 => x"000074e8", + 8236 => x"01300300", + 8237 => x"00000000", + 8238 => x"00000000", + 8239 => x"000074f0", + 8240 => x"013c0400", + 8241 => x"00000000", + 8242 => x"00000000", + 8243 => x"000074f8", + 8244 => x"013d0400", + 8245 => x"00000000", + 8246 => x"00000000", + 8247 => x"00007500", + 8248 => x"013f0400", + 8249 => x"00000000", + 8250 => x"00000000", + 8251 => x"00007508", + 8252 => x"01400400", + 8253 => x"00000000", + 8254 => x"00000000", + 8255 => x"00007510", + 8256 => x"01410400", + 8257 => x"00000000", + 8258 => x"00000000", + 8259 => x"00007514", + 8260 => x"01420400", + 8261 => x"00000000", + 8262 => x"00000000", + 8263 => x"00007518", + 8264 => x"01430400", + 8265 => x"00000000", + 8266 => x"00000000", + 8267 => x"0000751c", + 8268 => x"01500500", + 8269 => x"00000000", + 8270 => x"00000000", + 8271 => x"00007520", + 8272 => x"01510500", + 8273 => x"00000000", + 8274 => x"00000000", + 8275 => x"00007524", + 8276 => x"01540500", + 8277 => x"00000000", + 8278 => x"00000000", + 8279 => x"00007528", + 8280 => x"01550500", + 8281 => x"00000000", + 8282 => x"00000000", + 8283 => x"0000752c", + 8284 => x"01790700", + 8285 => x"00000000", + 8286 => x"00000000", + 8287 => x"00007534", + 8288 => x"01780700", + 8289 => x"00000000", + 8290 => x"00000000", + 8291 => x"00007538", + 8292 => x"01820800", + 8293 => x"00000000", + 8294 => x"00000000", + 8295 => x"00007540", + 8296 => x"01830800", + 8297 => x"00000000", + 8298 => x"00000000", + 8299 => x"00007548", + 8300 => x"01850800", + 8301 => x"00000000", + 8302 => x"00000000", + 8303 => x"00007550", + 8304 => x"01870800", + 8305 => x"00000000", + 8306 => x"00000000", + 8307 => x"00007558", + 8308 => x"018c0900", + 8309 => x"00000000", + 8310 => x"00000000", + 8311 => x"00007560", + 8312 => x"018d0900", + 8313 => x"00000000", + 8314 => x"00000000", + 8315 => x"00007568", + 8316 => x"018e0900", + 8317 => x"00000000", + 8318 => x"00000000", + 8319 => x"00007570", + 8320 => x"018f0900", + 8321 => x"00000000", + 8322 => x"00000000", + 8323 => x"00000000", + 8324 => x"00000000", + 8325 => x"00007fff", + 8326 => x"00000000", + 8327 => x"00007fff", + 8328 => x"00010000", + 8329 => x"00007fff", + 8330 => x"00010000", + 8331 => x"00810000", + 8332 => x"01000000", + 8333 => x"017fffff", + 8334 => x"00000000", + 8335 => x"00000000", + 8336 => x"00007800", + 8337 => x"00000000", + 8338 => x"05f5e100", + 8339 => x"05f5e100", + 8340 => x"05f5e100", + 8341 => x"00000000", + 8342 => x"01010101", + 8343 => x"01010101", + 8344 => x"01011001", + 8345 => x"01000000", + 8346 => x"00000000", + 8347 => x"00000000", + 8348 => x"00000000", + 8349 => x"00000000", + 8350 => x"00000000", + 8351 => x"00000000", + 8352 => x"00000000", + 8353 => x"00000000", + 8354 => x"00000000", + 8355 => x"00000000", + 8356 => x"00000000", + 8357 => x"00000000", + 8358 => x"00000000", + 8359 => x"00000000", + 8360 => x"00000000", + 8361 => x"00000000", + 8362 => x"00000000", + 8363 => x"00000000", + 8364 => x"00000000", + 8365 => x"00000000", + 8366 => x"00000000", + 8367 => x"00000000", + 8368 => x"00000000", + 8369 => x"00000000", + 8370 => x"00007ed4", + 8371 => x"01000000", + 8372 => x"00007edc", + 8373 => x"01000000", + 8374 => x"00007ee4", + 8375 => x"02000000", + 8376 => x"00000000", + 8377 => x"00000000", + 8378 => x"01000000", + others => x"00000000" + ); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))); + end if; + end if; +end process; + + +end arch; + diff --git a/zpu/devices/sysbus/BRAM/zOS_DualPortBootBRAM.vhd b/zpu/devices/sysbus/BRAM/zOS_DualPortBootBRAM.vhd new file mode 100644 index 0000000..7c61bbf --- /dev/null +++ b/zpu/devices/sysbus/BRAM/zOS_DualPortBootBRAM.vhd @@ -0,0 +1,33738 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity DualPortBootBRAM is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + + memBAddr : in std_logic_vector(addrbits-1 downto 2); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBRead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end DualPortBootBRAM; + +architecture arch of DualPortBootBRAM is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + 0 => x"ff", + 1 => x"0b", + 2 => x"04", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"80", + 10 => x"0c", + 11 => x"0c", + 12 => x"00", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"08", + 17 => x"09", + 18 => x"05", + 19 => x"83", + 20 => x"52", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"08", + 25 => x"73", + 26 => x"81", + 27 => x"83", + 28 => x"06", + 29 => x"ff", + 30 => x"0b", + 31 => x"00", + 32 => x"05", + 33 => x"73", + 34 => x"06", + 35 => x"06", + 36 => x"06", + 37 => x"00", + 38 => x"00", + 39 => x"00", + 40 => x"73", + 41 => x"53", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"09", + 49 => x"06", + 50 => x"72", + 51 => x"72", + 52 => x"31", + 53 => x"06", + 54 => x"51", + 55 => x"00", + 56 => x"73", + 57 => x"53", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"92", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"2b", + 81 => x"04", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"06", + 89 => x"0b", + 90 => x"e2", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"ff", + 97 => x"2a", + 98 => x"0a", + 99 => x"05", + 100 => x"51", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"51", + 105 => x"83", + 106 => x"05", + 107 => x"2b", + 108 => x"72", + 109 => x"51", + 110 => x"00", + 111 => x"00", + 112 => x"05", + 113 => x"70", + 114 => x"06", + 115 => x"53", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"05", + 121 => x"70", + 122 => x"06", + 123 => x"06", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"05", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"81", + 137 => x"51", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"06", + 145 => x"06", + 146 => x"04", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"08", + 153 => x"09", + 154 => x"05", + 155 => x"2a", + 156 => x"52", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"08", + 161 => x"e7", + 162 => x"06", + 163 => x"08", + 164 => x"0b", + 165 => x"00", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"75", + 170 => x"99", + 171 => x"50", + 172 => x"90", + 173 => x"88", + 174 => x"00", + 175 => x"00", + 176 => x"08", + 177 => x"75", + 178 => x"9b", + 179 => x"50", + 180 => x"90", + 181 => x"88", + 182 => x"00", + 183 => x"00", + 184 => x"81", + 185 => x"0a", + 186 => x"05", + 187 => x"06", + 188 => x"74", + 189 => x"06", + 190 => x"51", + 191 => x"00", + 192 => x"81", + 193 => x"0a", + 194 => x"ff", + 195 => x"71", + 196 => x"72", + 197 => x"05", + 198 => x"51", + 199 => x"00", + 200 => x"04", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"52", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"72", + 233 => x"52", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"ff", + 249 => x"51", + 250 => x"ff", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"00", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"8c", + 265 => x"0b", + 266 => x"04", + 267 => x"8c", + 268 => x"0b", + 269 => x"04", + 270 => x"8c", + 271 => x"0b", + 272 => x"04", + 273 => x"8c", + 274 => x"0b", + 275 => x"04", + 276 => x"8c", + 277 => x"0b", + 278 => x"04", + 279 => x"8d", + 280 => x"0b", + 281 => x"04", + 282 => x"8d", + 283 => x"0b", + 284 => x"04", + 285 => x"8d", + 286 => x"0b", + 287 => x"04", + 288 => x"8d", + 289 => x"0b", + 290 => x"04", + 291 => x"8e", + 292 => x"0b", + 293 => x"04", + 294 => x"8e", + 295 => x"0b", + 296 => x"04", + 297 => x"8e", + 298 => x"0b", + 299 => x"04", + 300 => x"8e", + 301 => x"0b", + 302 => x"04", + 303 => x"8f", + 304 => x"0b", + 305 => x"04", + 306 => x"8f", + 307 => x"0b", + 308 => x"04", + 309 => x"8f", + 310 => x"0b", + 311 => x"04", + 312 => x"8f", + 313 => x"0b", + 314 => x"04", + 315 => x"90", + 316 => x"0b", + 317 => x"04", + 318 => x"90", + 319 => x"0b", + 320 => x"04", + 321 => x"90", + 322 => x"0b", + 323 => x"04", + 324 => x"90", + 325 => x"0b", + 326 => x"04", + 327 => x"91", + 328 => x"0b", + 329 => x"04", + 330 => x"91", + 331 => x"0b", + 332 => x"04", + 333 => x"91", + 334 => x"0b", + 335 => x"04", + 336 => x"91", + 337 => x"0b", + 338 => x"04", + 339 => x"92", + 340 => x"0b", + 341 => x"04", + 342 => x"92", + 343 => x"ff", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"81", + 385 => x"f8", + 386 => x"8c", + 387 => x"f8", + 388 => x"90", + 389 => x"f8", + 390 => x"8e", + 391 => x"f8", + 392 => x"90", + 393 => x"f8", + 394 => x"cd", + 395 => x"f8", + 396 => x"90", + 397 => x"f8", + 398 => x"eb", + 399 => x"f8", + 400 => x"90", + 401 => x"f8", + 402 => x"b5", + 403 => x"f8", + 404 => x"90", + 405 => x"f8", + 406 => x"b6", + 407 => x"f8", + 408 => x"90", + 409 => x"f8", + 410 => x"8e", + 411 => x"f8", + 412 => x"90", + 413 => x"f8", + 414 => x"d3", + 415 => x"f8", + 416 => x"90", + 417 => x"f8", + 418 => x"cf", + 419 => x"f8", + 420 => x"90", + 421 => x"f8", + 422 => x"db", + 423 => x"f8", + 424 => x"90", + 425 => x"f8", + 426 => x"c0", + 427 => x"f8", + 428 => x"90", + 429 => x"f8", + 430 => x"f1", + 431 => x"f8", + 432 => x"90", + 433 => x"f8", + 434 => x"95", + 435 => x"f8", + 436 => x"90", + 437 => x"f8", + 438 => x"95", + 439 => x"f8", + 440 => x"90", + 441 => x"f8", + 442 => x"e4", + 443 => x"f8", + 444 => x"90", + 445 => x"f8", + 446 => x"2d", + 447 => x"08", + 448 => x"04", + 449 => x"0c", + 450 => x"82", + 451 => x"82", + 452 => x"82", + 453 => x"be", + 454 => x"85", + 455 => x"a0", + 456 => x"85", + 457 => x"aa", + 458 => x"85", + 459 => x"a0", + 460 => x"85", + 461 => x"b7", + 462 => x"85", + 463 => x"a0", + 464 => x"85", + 465 => x"af", + 466 => x"85", + 467 => x"a0", + 468 => x"85", + 469 => x"b2", + 470 => x"85", + 471 => x"a0", + 472 => x"85", + 473 => x"bc", + 474 => x"85", + 475 => x"a0", + 476 => x"85", + 477 => x"c5", + 478 => x"85", + 479 => x"a0", + 480 => x"85", + 481 => x"b6", + 482 => x"85", + 483 => x"a0", + 484 => x"85", + 485 => x"bf", + 486 => x"85", + 487 => x"a0", + 488 => x"85", + 489 => x"c0", + 490 => x"85", + 491 => x"a0", + 492 => x"85", + 493 => x"c1", + 494 => x"85", + 495 => x"a0", + 496 => x"85", + 497 => x"c9", + 498 => x"85", + 499 => x"a0", + 500 => x"85", + 501 => x"c6", + 502 => x"85", + 503 => x"a0", + 504 => x"85", + 505 => x"cb", + 506 => x"85", + 507 => x"a0", + 508 => x"85", + 509 => x"c2", + 510 => x"85", + 511 => x"a0", + 512 => x"85", + 513 => x"ce", + 514 => x"85", + 515 => x"a0", + 516 => x"85", + 517 => x"cf", + 518 => x"85", + 519 => x"a0", + 520 => x"85", + 521 => x"b8", + 522 => x"85", + 523 => x"a0", + 524 => x"85", + 525 => x"b7", + 526 => x"85", + 527 => x"a0", + 528 => x"85", + 529 => x"b9", + 530 => x"85", + 531 => x"a0", + 532 => x"85", + 533 => x"c2", + 534 => x"85", + 535 => x"a0", + 536 => x"85", + 537 => x"d0", + 538 => x"85", + 539 => x"a0", + 540 => x"85", + 541 => x"d2", + 542 => x"85", + 543 => x"a0", + 544 => x"85", + 545 => x"d6", + 546 => x"85", + 547 => x"a0", + 548 => x"85", + 549 => x"a9", + 550 => x"85", + 551 => x"a0", + 552 => x"85", + 553 => x"d9", + 554 => x"85", + 555 => x"a0", + 556 => x"85", + 557 => x"e7", + 558 => x"85", + 559 => x"a0", + 560 => x"85", + 561 => x"e5", + 562 => x"85", + 563 => x"a0", + 564 => x"85", + 565 => x"fa", + 566 => x"85", + 567 => x"a0", + 568 => x"85", + 569 => x"fc", + 570 => x"85", + 571 => x"a0", + 572 => x"85", + 573 => x"fe", + 574 => x"85", + 575 => x"a0", + 576 => x"85", + 577 => x"ed", + 578 => x"f8", + 579 => x"90", + 580 => x"f8", + 581 => x"2d", + 582 => x"08", + 583 => x"04", + 584 => x"0c", + 585 => x"2d", + 586 => x"08", + 587 => x"04", + 588 => x"0c", + 589 => x"82", + 590 => x"82", + 591 => x"3c", + 592 => x"10", + 593 => x"10", + 594 => x"10", + 595 => x"10", + 596 => x"10", + 597 => x"10", + 598 => x"10", + 599 => x"10", + 600 => x"51", + 601 => x"73", + 602 => x"73", + 603 => x"81", + 604 => x"10", + 605 => x"07", + 606 => x"0c", + 607 => x"72", + 608 => x"81", + 609 => x"09", + 610 => x"71", + 611 => x"0a", + 612 => x"72", + 613 => x"51", + 614 => x"82", + 615 => x"82", + 616 => x"8e", + 617 => x"70", + 618 => x"0c", + 619 => x"93", + 620 => x"81", + 621 => x"04", + 622 => x"f8", + 623 => x"85", + 624 => x"3d", + 625 => x"f8", + 626 => x"08", + 627 => x"08", + 628 => x"82", + 629 => x"fc", + 630 => x"71", + 631 => x"f8", + 632 => x"08", + 633 => x"85", + 634 => x"05", + 635 => x"ff", + 636 => x"70", + 637 => x"38", + 638 => x"85", + 639 => x"05", + 640 => x"82", + 641 => x"fc", + 642 => x"85", + 643 => x"05", + 644 => x"f8", + 645 => x"08", + 646 => x"85", + 647 => x"84", + 648 => x"85", + 649 => x"82", + 650 => x"02", + 651 => x"0c", + 652 => x"82", + 653 => x"88", + 654 => x"85", + 655 => x"05", + 656 => x"f8", + 657 => x"08", + 658 => x"82", + 659 => x"8c", + 660 => x"05", + 661 => x"08", + 662 => x"82", + 663 => x"fc", + 664 => x"51", + 665 => x"82", + 666 => x"fc", + 667 => x"05", + 668 => x"08", + 669 => x"70", + 670 => x"51", + 671 => x"84", + 672 => x"39", + 673 => x"08", + 674 => x"70", + 675 => x"0c", + 676 => x"0d", + 677 => x"0c", + 678 => x"f8", + 679 => x"85", + 680 => x"3d", + 681 => x"f8", + 682 => x"08", + 683 => x"08", + 684 => x"82", + 685 => x"8c", + 686 => x"85", + 687 => x"05", + 688 => x"f8", + 689 => x"08", + 690 => x"e5", + 691 => x"f8", + 692 => x"08", + 693 => x"85", + 694 => x"05", + 695 => x"f8", + 696 => x"08", + 697 => x"85", + 698 => x"05", + 699 => x"f8", + 700 => x"08", + 701 => x"38", + 702 => x"08", + 703 => x"51", + 704 => x"85", + 705 => x"05", + 706 => x"82", + 707 => x"f8", + 708 => x"85", + 709 => x"05", + 710 => x"71", + 711 => x"85", + 712 => x"05", + 713 => x"82", + 714 => x"fc", + 715 => x"ad", + 716 => x"f8", + 717 => x"08", + 718 => x"ec", + 719 => x"3d", + 720 => x"f8", + 721 => x"85", + 722 => x"82", + 723 => x"fd", + 724 => x"85", + 725 => x"05", + 726 => x"81", + 727 => x"85", + 728 => x"05", + 729 => x"33", + 730 => x"08", + 731 => x"81", + 732 => x"f8", + 733 => x"0c", + 734 => x"08", + 735 => x"70", + 736 => x"ff", + 737 => x"54", + 738 => x"2e", + 739 => x"ce", + 740 => x"f8", + 741 => x"08", + 742 => x"82", + 743 => x"88", + 744 => x"05", + 745 => x"08", + 746 => x"70", + 747 => x"51", + 748 => x"38", + 749 => x"85", + 750 => x"05", + 751 => x"39", + 752 => x"08", + 753 => x"ff", + 754 => x"f8", + 755 => x"0c", + 756 => x"08", + 757 => x"80", + 758 => x"ff", + 759 => x"85", + 760 => x"05", + 761 => x"80", + 762 => x"85", + 763 => x"05", + 764 => x"52", + 765 => x"38", + 766 => x"85", + 767 => x"05", + 768 => x"39", + 769 => x"08", + 770 => x"ff", + 771 => x"f8", + 772 => x"0c", + 773 => x"08", + 774 => x"70", + 775 => x"70", + 776 => x"0b", + 777 => x"08", + 778 => x"ae", + 779 => x"f8", + 780 => x"08", + 781 => x"85", + 782 => x"05", + 783 => x"72", + 784 => x"82", + 785 => x"fc", + 786 => x"55", + 787 => x"8a", + 788 => x"82", + 789 => x"fc", + 790 => x"85", + 791 => x"05", + 792 => x"ec", + 793 => x"0d", + 794 => x"0c", + 795 => x"f8", + 796 => x"85", + 797 => x"3d", + 798 => x"f8", + 799 => x"08", + 800 => x"08", + 801 => x"82", + 802 => x"90", + 803 => x"2e", + 804 => x"82", + 805 => x"90", + 806 => x"05", + 807 => x"08", + 808 => x"82", + 809 => x"90", + 810 => x"05", + 811 => x"08", + 812 => x"82", + 813 => x"90", + 814 => x"2e", + 815 => x"85", + 816 => x"05", + 817 => x"82", + 818 => x"fc", + 819 => x"52", + 820 => x"82", + 821 => x"fc", + 822 => x"05", + 823 => x"08", + 824 => x"ff", + 825 => x"85", + 826 => x"05", + 827 => x"85", + 828 => x"84", + 829 => x"85", + 830 => x"82", + 831 => x"02", + 832 => x"0c", + 833 => x"80", + 834 => x"f8", + 835 => x"0c", + 836 => x"08", + 837 => x"80", + 838 => x"82", + 839 => x"88", + 840 => x"82", + 841 => x"88", + 842 => x"0b", + 843 => x"08", + 844 => x"82", + 845 => x"fc", + 846 => x"38", + 847 => x"85", + 848 => x"05", + 849 => x"f8", + 850 => x"08", + 851 => x"08", + 852 => x"82", + 853 => x"8c", + 854 => x"25", + 855 => x"85", + 856 => x"05", + 857 => x"85", + 858 => x"05", + 859 => x"82", + 860 => x"f0", + 861 => x"85", + 862 => x"05", + 863 => x"81", + 864 => x"f8", + 865 => x"0c", + 866 => x"08", + 867 => x"82", + 868 => x"fc", + 869 => x"53", + 870 => x"08", + 871 => x"52", + 872 => x"08", + 873 => x"51", + 874 => x"82", + 875 => x"70", + 876 => x"08", + 877 => x"54", + 878 => x"08", + 879 => x"80", + 880 => x"82", + 881 => x"f8", + 882 => x"82", + 883 => x"f8", + 884 => x"85", + 885 => x"05", + 886 => x"85", + 887 => x"89", + 888 => x"85", + 889 => x"82", + 890 => x"02", + 891 => x"0c", + 892 => x"80", + 893 => x"f8", + 894 => x"0c", + 895 => x"08", + 896 => x"80", + 897 => x"82", + 898 => x"88", + 899 => x"82", + 900 => x"88", + 901 => x"0b", + 902 => x"08", + 903 => x"82", + 904 => x"8c", + 905 => x"25", + 906 => x"85", + 907 => x"05", + 908 => x"85", + 909 => x"05", + 910 => x"82", + 911 => x"8c", + 912 => x"82", + 913 => x"88", + 914 => x"82", + 915 => x"85", + 916 => x"82", + 917 => x"f8", + 918 => x"82", + 919 => x"fc", + 920 => x"2e", + 921 => x"85", + 922 => x"05", + 923 => x"85", + 924 => x"05", + 925 => x"f8", + 926 => x"08", + 927 => x"ec", + 928 => x"3d", + 929 => x"f8", + 930 => x"85", + 931 => x"82", + 932 => x"ff", + 933 => x"0b", + 934 => x"08", + 935 => x"82", + 936 => x"88", + 937 => x"06", + 938 => x"09", + 939 => x"f8", + 940 => x"08", + 941 => x"f8", + 942 => x"08", + 943 => x"f8", + 944 => x"0c", + 945 => x"08", + 946 => x"81", + 947 => x"f8", + 948 => x"0c", + 949 => x"08", + 950 => x"10", + 951 => x"08", + 952 => x"51", + 953 => x"82", + 954 => x"88", + 955 => x"2e", + 956 => x"ab", + 957 => x"f8", + 958 => x"08", + 959 => x"ec", + 960 => x"3d", + 961 => x"f8", + 962 => x"85", + 963 => x"82", + 964 => x"fd", + 965 => x"53", + 966 => x"08", + 967 => x"52", + 968 => x"08", + 969 => x"51", + 970 => x"82", + 971 => x"70", + 972 => x"0c", + 973 => x"0d", + 974 => x"0c", + 975 => x"f8", + 976 => x"85", + 977 => x"3d", + 978 => x"82", + 979 => x"8c", + 980 => x"82", + 981 => x"88", + 982 => x"93", + 983 => x"ec", + 984 => x"85", + 985 => x"85", + 986 => x"85", + 987 => x"82", + 988 => x"02", + 989 => x"0c", + 990 => x"81", + 991 => x"f8", + 992 => x"0c", + 993 => x"85", + 994 => x"05", + 995 => x"f8", + 996 => x"08", + 997 => x"08", + 998 => x"27", + 999 => x"85", + 1000 => x"05", + 1001 => x"ae", + 1002 => x"82", + 1003 => x"8c", + 1004 => x"a2", + 1005 => x"f8", + 1006 => x"08", + 1007 => x"f8", + 1008 => x"0c", + 1009 => x"08", + 1010 => x"10", + 1011 => x"08", + 1012 => x"ff", + 1013 => x"85", + 1014 => x"05", + 1015 => x"80", + 1016 => x"85", + 1017 => x"05", + 1018 => x"f8", + 1019 => x"08", + 1020 => x"82", + 1021 => x"88", + 1022 => x"85", + 1023 => x"05", + 1024 => x"85", + 1025 => x"05", + 1026 => x"f8", + 1027 => x"08", + 1028 => x"08", + 1029 => x"07", + 1030 => x"08", + 1031 => x"82", + 1032 => x"fc", + 1033 => x"2a", + 1034 => x"08", + 1035 => x"82", + 1036 => x"8c", + 1037 => x"2a", + 1038 => x"08", + 1039 => x"ff", + 1040 => x"85", + 1041 => x"05", + 1042 => x"93", + 1043 => x"f8", + 1044 => x"08", + 1045 => x"f8", + 1046 => x"0c", + 1047 => x"82", + 1048 => x"f8", + 1049 => x"82", + 1050 => x"f4", + 1051 => x"82", + 1052 => x"f4", + 1053 => x"85", + 1054 => x"3d", + 1055 => x"f8", + 1056 => x"3d", + 1057 => x"08", + 1058 => x"58", + 1059 => x"80", + 1060 => x"39", + 1061 => x"f2", + 1062 => x"85", + 1063 => x"78", + 1064 => x"33", + 1065 => x"39", + 1066 => x"73", + 1067 => x"81", + 1068 => x"81", + 1069 => x"39", + 1070 => x"84", + 1071 => x"ec", + 1072 => x"52", + 1073 => x"3f", + 1074 => x"08", + 1075 => x"75", + 1076 => x"f2", + 1077 => x"ec", + 1078 => x"84", + 1079 => x"73", + 1080 => x"b0", + 1081 => x"70", + 1082 => x"58", + 1083 => x"27", + 1084 => x"54", + 1085 => x"ec", + 1086 => x"0d", + 1087 => x"0d", + 1088 => x"93", + 1089 => x"38", + 1090 => x"52", + 1091 => x"12", + 1092 => x"ea", + 1093 => x"80", + 1094 => x"80", + 1095 => x"39", + 1096 => x"51", + 1097 => x"81", + 1098 => x"80", + 1099 => x"eb", + 1100 => x"e4", + 1101 => x"c8", + 1102 => x"39", + 1103 => x"51", + 1104 => x"81", + 1105 => x"80", + 1106 => x"ec", + 1107 => x"c8", + 1108 => x"9c", + 1109 => x"39", + 1110 => x"51", + 1111 => x"ec", + 1112 => x"39", + 1113 => x"51", + 1114 => x"ed", + 1115 => x"39", + 1116 => x"51", + 1117 => x"ed", + 1118 => x"39", + 1119 => x"51", + 1120 => x"ed", + 1121 => x"39", + 1122 => x"51", + 1123 => x"ee", + 1124 => x"39", + 1125 => x"51", + 1126 => x"83", + 1127 => x"fb", + 1128 => x"79", + 1129 => x"87", + 1130 => x"38", + 1131 => x"75", + 1132 => x"3f", + 1133 => x"85", + 1134 => x"90", + 1135 => x"52", + 1136 => x"c6", + 1137 => x"ec", + 1138 => x"51", + 1139 => x"82", + 1140 => x"54", + 1141 => x"52", + 1142 => x"51", + 1143 => x"87", + 1144 => x"ec", + 1145 => x"02", + 1146 => x"e3", + 1147 => x"57", + 1148 => x"09", + 1149 => x"7a", + 1150 => x"51", + 1151 => x"78", + 1152 => x"ff", + 1153 => x"81", + 1154 => x"07", + 1155 => x"06", + 1156 => x"56", + 1157 => x"38", + 1158 => x"52", + 1159 => x"52", + 1160 => x"98", + 1161 => x"ec", + 1162 => x"85", + 1163 => x"38", + 1164 => x"08", + 1165 => x"88", + 1166 => x"ec", + 1167 => x"3d", + 1168 => x"84", + 1169 => x"52", + 1170 => x"8a", + 1171 => x"85", + 1172 => x"82", + 1173 => x"90", + 1174 => x"74", + 1175 => x"38", + 1176 => x"19", + 1177 => x"39", + 1178 => x"05", + 1179 => x"bf", + 1180 => x"81", + 1181 => x"07", + 1182 => x"09", + 1183 => x"9f", + 1184 => x"51", + 1185 => x"74", + 1186 => x"38", + 1187 => x"53", + 1188 => x"88", + 1189 => x"51", + 1190 => x"76", + 1191 => x"85", + 1192 => x"3d", + 1193 => x"3d", + 1194 => x"84", + 1195 => x"33", + 1196 => x"57", + 1197 => x"52", + 1198 => x"a7", + 1199 => x"ec", + 1200 => x"75", + 1201 => x"38", + 1202 => x"98", + 1203 => x"60", + 1204 => x"82", + 1205 => x"7e", + 1206 => x"77", + 1207 => x"ec", + 1208 => x"39", + 1209 => x"82", + 1210 => x"89", + 1211 => x"f3", + 1212 => x"61", + 1213 => x"05", + 1214 => x"33", + 1215 => x"68", + 1216 => x"5c", + 1217 => x"7a", + 1218 => x"e8", + 1219 => x"3f", + 1220 => x"51", + 1221 => x"80", + 1222 => x"27", + 1223 => x"7b", + 1224 => x"38", + 1225 => x"a4", + 1226 => x"39", + 1227 => x"72", + 1228 => x"38", + 1229 => x"81", + 1230 => x"ae", + 1231 => x"39", + 1232 => x"51", + 1233 => x"82", + 1234 => x"39", + 1235 => x"72", + 1236 => x"38", + 1237 => x"81", + 1238 => x"ad", + 1239 => x"39", + 1240 => x"51", + 1241 => x"84", + 1242 => x"39", + 1243 => x"72", + 1244 => x"38", + 1245 => x"81", + 1246 => x"ad", + 1247 => x"39", + 1248 => x"51", + 1249 => x"81", + 1250 => x"51", + 1251 => x"ff", + 1252 => x"ef", + 1253 => x"d3", + 1254 => x"74", + 1255 => x"38", + 1256 => x"33", + 1257 => x"56", + 1258 => x"83", + 1259 => x"80", + 1260 => x"27", + 1261 => x"53", + 1262 => x"70", + 1263 => x"51", + 1264 => x"2e", + 1265 => x"80", + 1266 => x"38", + 1267 => x"39", + 1268 => x"ba", + 1269 => x"55", + 1270 => x"ef", + 1271 => x"8b", + 1272 => x"79", + 1273 => x"9b", + 1274 => x"85", + 1275 => x"2b", + 1276 => x"51", + 1277 => x"2e", + 1278 => x"ae", + 1279 => x"3f", + 1280 => x"08", + 1281 => x"98", + 1282 => x"32", + 1283 => x"05", + 1284 => x"70", + 1285 => x"70", + 1286 => x"75", + 1287 => x"58", + 1288 => x"51", + 1289 => x"24", + 1290 => x"9b", + 1291 => x"06", + 1292 => x"53", + 1293 => x"1e", + 1294 => x"26", + 1295 => x"ff", + 1296 => x"85", + 1297 => x"3d", + 1298 => x"3d", + 1299 => x"05", + 1300 => x"9c", + 1301 => x"a0", + 1302 => x"ff", + 1303 => x"c4", + 1304 => x"d1", + 1305 => x"ac", + 1306 => x"b8", + 1307 => x"c5", + 1308 => x"ef", + 1309 => x"e3", + 1310 => x"2e", + 1311 => x"86", + 1312 => x"0d", + 1313 => x"0d", + 1314 => x"80", + 1315 => x"ec", + 1316 => x"96", + 1317 => x"ef", + 1318 => x"e0", + 1319 => x"96", + 1320 => x"81", + 1321 => x"06", + 1322 => x"80", + 1323 => x"81", + 1324 => x"3f", + 1325 => x"51", + 1326 => x"80", + 1327 => x"3f", + 1328 => x"70", + 1329 => x"52", + 1330 => x"92", + 1331 => x"96", + 1332 => x"f0", + 1333 => x"a4", + 1334 => x"96", + 1335 => x"83", + 1336 => x"06", + 1337 => x"80", + 1338 => x"81", + 1339 => x"3f", + 1340 => x"51", + 1341 => x"80", + 1342 => x"3f", + 1343 => x"70", + 1344 => x"52", + 1345 => x"92", + 1346 => x"95", + 1347 => x"f0", + 1348 => x"e8", + 1349 => x"95", + 1350 => x"85", + 1351 => x"06", + 1352 => x"80", + 1353 => x"81", + 1354 => x"3f", + 1355 => x"51", + 1356 => x"80", + 1357 => x"3f", + 1358 => x"70", + 1359 => x"52", + 1360 => x"92", + 1361 => x"95", + 1362 => x"f0", + 1363 => x"ac", + 1364 => x"95", + 1365 => x"87", + 1366 => x"06", + 1367 => x"80", + 1368 => x"81", + 1369 => x"3f", + 1370 => x"51", + 1371 => x"80", + 1372 => x"3f", + 1373 => x"70", + 1374 => x"52", + 1375 => x"92", + 1376 => x"94", + 1377 => x"f0", + 1378 => x"f0", + 1379 => x"94", + 1380 => x"f0", + 1381 => x"0d", + 1382 => x"0d", + 1383 => x"05", + 1384 => x"70", + 1385 => x"80", + 1386 => x"ed", + 1387 => x"0b", + 1388 => x"33", + 1389 => x"38", + 1390 => x"f1", + 1391 => x"9c", + 1392 => x"fe", + 1393 => x"85", + 1394 => x"81", + 1395 => x"85", + 1396 => x"80", + 1397 => x"31", + 1398 => x"73", + 1399 => x"80", + 1400 => x"0b", + 1401 => x"33", + 1402 => x"2e", + 1403 => x"af", + 1404 => x"cc", + 1405 => x"75", + 1406 => x"c4", + 1407 => x"ec", + 1408 => x"8b", + 1409 => x"ec", + 1410 => x"df", + 1411 => x"82", + 1412 => x"81", + 1413 => x"82", + 1414 => x"82", + 1415 => x"0b", + 1416 => x"e8", + 1417 => x"82", + 1418 => x"06", + 1419 => x"f1", + 1420 => x"52", + 1421 => x"92", + 1422 => x"82", + 1423 => x"87", + 1424 => x"ce", + 1425 => x"70", + 1426 => x"c8", + 1427 => x"81", + 1428 => x"80", + 1429 => x"82", + 1430 => x"81", + 1431 => x"78", + 1432 => x"81", + 1433 => x"81", + 1434 => x"96", + 1435 => x"59", + 1436 => x"7c", + 1437 => x"82", + 1438 => x"80", + 1439 => x"82", + 1440 => x"7d", + 1441 => x"81", + 1442 => x"8d", + 1443 => x"70", + 1444 => x"f2", + 1445 => x"d3", + 1446 => x"70", + 1447 => x"f8", + 1448 => x"fd", + 1449 => x"3d", + 1450 => x"51", + 1451 => x"82", + 1452 => x"90", + 1453 => x"2c", + 1454 => x"80", + 1455 => x"9c", + 1456 => x"c2", + 1457 => x"78", + 1458 => x"d1", + 1459 => x"24", + 1460 => x"80", + 1461 => x"38", + 1462 => x"80", + 1463 => x"bb", + 1464 => x"c0", + 1465 => x"38", + 1466 => x"24", + 1467 => x"78", + 1468 => x"8a", + 1469 => x"39", + 1470 => x"2e", + 1471 => x"78", + 1472 => x"92", + 1473 => x"c3", + 1474 => x"38", + 1475 => x"2e", + 1476 => x"8a", + 1477 => x"81", + 1478 => x"ed", + 1479 => x"83", + 1480 => x"78", + 1481 => x"89", + 1482 => x"ef", + 1483 => x"85", + 1484 => x"38", + 1485 => x"b4", + 1486 => x"11", + 1487 => x"05", + 1488 => x"3f", + 1489 => x"08", + 1490 => x"c6", + 1491 => x"fe", + 1492 => x"ff", + 1493 => x"a7", + 1494 => x"85", + 1495 => x"2e", + 1496 => x"b4", + 1497 => x"11", + 1498 => x"05", + 1499 => x"3f", + 1500 => x"08", + 1501 => x"85", + 1502 => x"81", + 1503 => x"9f", + 1504 => x"63", + 1505 => x"7b", + 1506 => x"38", + 1507 => x"7a", + 1508 => x"5c", + 1509 => x"26", + 1510 => x"d8", + 1511 => x"ff", + 1512 => x"ff", + 1513 => x"a7", + 1514 => x"85", + 1515 => x"2e", + 1516 => x"b4", + 1517 => x"11", + 1518 => x"05", + 1519 => x"3f", + 1520 => x"08", + 1521 => x"ca", + 1522 => x"fe", + 1523 => x"ff", + 1524 => x"a6", + 1525 => x"85", + 1526 => x"2e", + 1527 => x"81", + 1528 => x"9f", + 1529 => x"5a", + 1530 => x"81", + 1531 => x"59", + 1532 => x"05", + 1533 => x"34", + 1534 => x"42", + 1535 => x"3d", + 1536 => x"53", + 1537 => x"51", + 1538 => x"82", + 1539 => x"80", + 1540 => x"38", + 1541 => x"fc", + 1542 => x"84", + 1543 => x"b3", + 1544 => x"ec", + 1545 => x"fc", + 1546 => x"3d", + 1547 => x"53", + 1548 => x"51", + 1549 => x"82", + 1550 => x"80", + 1551 => x"38", + 1552 => x"51", + 1553 => x"63", + 1554 => x"27", + 1555 => x"70", + 1556 => x"5e", + 1557 => x"7c", + 1558 => x"78", + 1559 => x"79", + 1560 => x"52", + 1561 => x"51", + 1562 => x"81", + 1563 => x"05", + 1564 => x"39", + 1565 => x"51", + 1566 => x"b4", + 1567 => x"11", + 1568 => x"05", + 1569 => x"3f", + 1570 => x"08", + 1571 => x"82", + 1572 => x"59", + 1573 => x"89", + 1574 => x"90", + 1575 => x"cd", + 1576 => x"d9", + 1577 => x"80", + 1578 => x"82", + 1579 => x"44", + 1580 => x"84", + 1581 => x"78", + 1582 => x"38", + 1583 => x"08", + 1584 => x"82", + 1585 => x"59", + 1586 => x"88", + 1587 => x"a8", + 1588 => x"39", + 1589 => x"33", + 1590 => x"2e", + 1591 => x"84", + 1592 => x"89", + 1593 => x"c0", + 1594 => x"05", + 1595 => x"fe", + 1596 => x"ff", + 1597 => x"a4", + 1598 => x"85", + 1599 => x"de", + 1600 => x"d8", + 1601 => x"80", + 1602 => x"82", + 1603 => x"43", + 1604 => x"82", + 1605 => x"59", + 1606 => x"88", + 1607 => x"9c", + 1608 => x"39", + 1609 => x"33", + 1610 => x"2e", + 1611 => x"84", + 1612 => x"aa", + 1613 => x"db", + 1614 => x"80", + 1615 => x"82", + 1616 => x"43", + 1617 => x"84", + 1618 => x"78", + 1619 => x"38", + 1620 => x"08", + 1621 => x"82", + 1622 => x"88", + 1623 => x"3d", + 1624 => x"53", + 1625 => x"51", + 1626 => x"82", + 1627 => x"80", + 1628 => x"80", + 1629 => x"7a", + 1630 => x"38", + 1631 => x"90", + 1632 => x"81", + 1633 => x"07", + 1634 => x"7f", + 1635 => x"5a", + 1636 => x"2e", + 1637 => x"a0", + 1638 => x"88", + 1639 => x"dc", + 1640 => x"3f", + 1641 => x"54", + 1642 => x"52", + 1643 => x"bf", + 1644 => x"ec", + 1645 => x"3f", + 1646 => x"b4", + 1647 => x"11", + 1648 => x"05", + 1649 => x"3f", + 1650 => x"08", + 1651 => x"c2", + 1652 => x"fe", + 1653 => x"ff", + 1654 => x"a2", + 1655 => x"85", + 1656 => x"2e", + 1657 => x"59", + 1658 => x"05", + 1659 => x"63", + 1660 => x"b4", + 1661 => x"11", + 1662 => x"05", + 1663 => x"3f", + 1664 => x"08", + 1665 => x"8a", + 1666 => x"33", + 1667 => x"f2", + 1668 => x"c7", + 1669 => x"52", + 1670 => x"99", + 1671 => x"79", + 1672 => x"ae", + 1673 => x"38", + 1674 => x"9f", + 1675 => x"fe", + 1676 => x"ff", + 1677 => x"a2", + 1678 => x"85", + 1679 => x"2e", + 1680 => x"59", + 1681 => x"05", + 1682 => x"63", + 1683 => x"ff", + 1684 => x"f3", + 1685 => x"93", + 1686 => x"39", + 1687 => x"f4", + 1688 => x"84", + 1689 => x"e7", + 1690 => x"ec", + 1691 => x"f8", + 1692 => x"3d", + 1693 => x"53", + 1694 => x"51", + 1695 => x"82", + 1696 => x"80", + 1697 => x"60", + 1698 => x"05", + 1699 => x"82", + 1700 => x"78", + 1701 => x"fe", + 1702 => x"ff", + 1703 => x"a3", + 1704 => x"85", + 1705 => x"38", + 1706 => x"60", + 1707 => x"52", + 1708 => x"51", + 1709 => x"80", + 1710 => x"51", + 1711 => x"79", + 1712 => x"59", + 1713 => x"f7", + 1714 => x"9f", + 1715 => x"60", + 1716 => x"d7", + 1717 => x"fe", + 1718 => x"ff", + 1719 => x"a2", + 1720 => x"85", + 1721 => x"2e", + 1722 => x"59", + 1723 => x"22", + 1724 => x"05", + 1725 => x"41", + 1726 => x"81", + 1727 => x"98", + 1728 => x"a7", + 1729 => x"fe", + 1730 => x"ff", + 1731 => x"a2", + 1732 => x"85", + 1733 => x"2e", + 1734 => x"b4", + 1735 => x"11", + 1736 => x"05", + 1737 => x"3f", + 1738 => x"08", + 1739 => x"38", + 1740 => x"0c", + 1741 => x"05", + 1742 => x"fe", + 1743 => x"ff", + 1744 => x"a2", + 1745 => x"85", + 1746 => x"38", + 1747 => x"60", + 1748 => x"52", + 1749 => x"51", + 1750 => x"80", + 1751 => x"51", + 1752 => x"79", + 1753 => x"59", + 1754 => x"f6", + 1755 => x"79", + 1756 => x"b4", + 1757 => x"11", + 1758 => x"05", + 1759 => x"3f", + 1760 => x"08", + 1761 => x"38", + 1762 => x"0c", + 1763 => x"05", + 1764 => x"39", + 1765 => x"51", + 1766 => x"ff", + 1767 => x"3d", + 1768 => x"53", + 1769 => x"51", + 1770 => x"82", + 1771 => x"80", + 1772 => x"38", + 1773 => x"f3", + 1774 => x"9f", + 1775 => x"78", + 1776 => x"ff", + 1777 => x"ff", + 1778 => x"9f", + 1779 => x"85", + 1780 => x"2e", + 1781 => x"63", + 1782 => x"c0", + 1783 => x"3f", + 1784 => x"2d", + 1785 => x"08", + 1786 => x"a6", + 1787 => x"ec", + 1788 => x"f3", + 1789 => x"e3", + 1790 => x"39", + 1791 => x"51", + 1792 => x"db", + 1793 => x"8a", + 1794 => x"94", + 1795 => x"3f", + 1796 => x"ab", + 1797 => x"3f", + 1798 => x"79", + 1799 => x"59", + 1800 => x"f4", + 1801 => x"7d", + 1802 => x"80", + 1803 => x"38", + 1804 => x"84", + 1805 => x"b5", + 1806 => x"ec", + 1807 => x"5b", + 1808 => x"b1", + 1809 => x"24", + 1810 => x"81", + 1811 => x"80", + 1812 => x"83", + 1813 => x"80", + 1814 => x"f4", + 1815 => x"55", + 1816 => x"54", + 1817 => x"f4", + 1818 => x"3d", + 1819 => x"51", + 1820 => x"b8", + 1821 => x"d0", + 1822 => x"ff", + 1823 => x"9b", + 1824 => x"39", + 1825 => x"f4", + 1826 => x"53", + 1827 => x"52", + 1828 => x"b0", + 1829 => x"d9", + 1830 => x"7b", + 1831 => x"81", + 1832 => x"b4", + 1833 => x"05", + 1834 => x"3f", + 1835 => x"58", + 1836 => x"57", + 1837 => x"55", + 1838 => x"a0", + 1839 => x"a0", + 1840 => x"3d", + 1841 => x"51", + 1842 => x"82", + 1843 => x"82", + 1844 => x"09", + 1845 => x"05", + 1846 => x"80", + 1847 => x"5b", + 1848 => x"7a", + 1849 => x"38", + 1850 => x"7a", + 1851 => x"80", + 1852 => x"81", + 1853 => x"ff", + 1854 => x"7a", + 1855 => x"7d", + 1856 => x"81", + 1857 => x"78", + 1858 => x"ff", + 1859 => x"06", + 1860 => x"81", + 1861 => x"9a", + 1862 => x"f6", + 1863 => x"0d", + 1864 => x"85", + 1865 => x"c0", + 1866 => x"08", + 1867 => x"84", + 1868 => x"51", + 1869 => x"82", + 1870 => x"90", + 1871 => x"55", + 1872 => x"80", + 1873 => x"e3", + 1874 => x"82", + 1875 => x"07", + 1876 => x"c0", + 1877 => x"08", + 1878 => x"84", + 1879 => x"51", + 1880 => x"82", + 1881 => x"90", + 1882 => x"55", + 1883 => x"80", + 1884 => x"e3", + 1885 => x"82", + 1886 => x"07", + 1887 => x"80", + 1888 => x"c0", + 1889 => x"8c", + 1890 => x"87", + 1891 => x"0c", + 1892 => x"0b", + 1893 => x"0c", + 1894 => x"0b", + 1895 => x"0c", + 1896 => x"92", + 1897 => x"f4", + 1898 => x"bf", + 1899 => x"f0", + 1900 => x"3f", + 1901 => x"92", + 1902 => x"51", + 1903 => x"f1", + 1904 => x"04", + 1905 => x"80", + 1906 => x"71", + 1907 => x"87", + 1908 => x"85", + 1909 => x"ff", + 1910 => x"ff", + 1911 => x"72", + 1912 => x"38", + 1913 => x"ec", + 1914 => x"0d", + 1915 => x"0d", + 1916 => x"54", + 1917 => x"52", + 1918 => x"2e", + 1919 => x"72", + 1920 => x"a0", + 1921 => x"06", + 1922 => x"13", + 1923 => x"72", + 1924 => x"a2", + 1925 => x"06", + 1926 => x"13", + 1927 => x"72", + 1928 => x"2e", + 1929 => x"9f", + 1930 => x"81", + 1931 => x"72", + 1932 => x"70", + 1933 => x"38", + 1934 => x"80", + 1935 => x"73", + 1936 => x"39", + 1937 => x"80", + 1938 => x"54", + 1939 => x"83", + 1940 => x"70", + 1941 => x"38", + 1942 => x"80", + 1943 => x"54", + 1944 => x"09", + 1945 => x"38", + 1946 => x"a2", + 1947 => x"81", + 1948 => x"25", + 1949 => x"51", + 1950 => x"2e", + 1951 => x"72", + 1952 => x"54", + 1953 => x"0c", + 1954 => x"82", + 1955 => x"86", + 1956 => x"fc", + 1957 => x"53", + 1958 => x"2e", + 1959 => x"3d", + 1960 => x"72", + 1961 => x"3f", + 1962 => x"08", + 1963 => x"53", + 1964 => x"53", + 1965 => x"ec", + 1966 => x"0d", + 1967 => x"0d", + 1968 => x"33", + 1969 => x"53", + 1970 => x"8b", + 1971 => x"38", + 1972 => x"ff", + 1973 => x"52", + 1974 => x"81", + 1975 => x"13", + 1976 => x"52", + 1977 => x"80", + 1978 => x"13", + 1979 => x"52", + 1980 => x"80", + 1981 => x"13", + 1982 => x"52", + 1983 => x"80", + 1984 => x"13", + 1985 => x"52", + 1986 => x"26", + 1987 => x"8a", + 1988 => x"87", + 1989 => x"e7", + 1990 => x"38", + 1991 => x"c0", + 1992 => x"72", + 1993 => x"98", + 1994 => x"13", + 1995 => x"98", + 1996 => x"13", + 1997 => x"98", + 1998 => x"13", + 1999 => x"98", + 2000 => x"13", + 2001 => x"98", + 2002 => x"13", + 2003 => x"98", + 2004 => x"87", + 2005 => x"0c", + 2006 => x"98", + 2007 => x"0b", + 2008 => x"9c", + 2009 => x"71", + 2010 => x"0c", + 2011 => x"04", + 2012 => x"7f", + 2013 => x"98", + 2014 => x"7d", + 2015 => x"98", + 2016 => x"7d", + 2017 => x"c0", + 2018 => x"5a", + 2019 => x"34", + 2020 => x"b4", + 2021 => x"83", + 2022 => x"c0", + 2023 => x"5a", + 2024 => x"34", + 2025 => x"ac", + 2026 => x"85", + 2027 => x"c0", + 2028 => x"5a", + 2029 => x"34", + 2030 => x"a4", + 2031 => x"88", + 2032 => x"c0", + 2033 => x"5a", + 2034 => x"23", + 2035 => x"79", + 2036 => x"06", + 2037 => x"ff", + 2038 => x"86", + 2039 => x"85", + 2040 => x"84", + 2041 => x"83", + 2042 => x"82", + 2043 => x"7d", + 2044 => x"06", + 2045 => x"88", + 2046 => x"3f", + 2047 => x"04", + 2048 => x"02", + 2049 => x"70", + 2050 => x"70", + 2051 => x"52", + 2052 => x"84", + 2053 => x"3d", + 2054 => x"3d", + 2055 => x"84", + 2056 => x"81", + 2057 => x"55", + 2058 => x"94", + 2059 => x"80", + 2060 => x"87", + 2061 => x"51", + 2062 => x"96", + 2063 => x"06", + 2064 => x"70", + 2065 => x"38", + 2066 => x"70", + 2067 => x"51", + 2068 => x"72", + 2069 => x"81", + 2070 => x"70", + 2071 => x"38", + 2072 => x"70", + 2073 => x"51", + 2074 => x"38", + 2075 => x"06", + 2076 => x"94", + 2077 => x"80", + 2078 => x"87", + 2079 => x"52", + 2080 => x"75", + 2081 => x"0c", + 2082 => x"04", + 2083 => x"02", + 2084 => x"82", + 2085 => x"70", + 2086 => x"57", + 2087 => x"c0", + 2088 => x"74", + 2089 => x"38", + 2090 => x"94", + 2091 => x"70", + 2092 => x"81", + 2093 => x"52", + 2094 => x"8c", + 2095 => x"2a", + 2096 => x"51", + 2097 => x"38", + 2098 => x"70", + 2099 => x"51", + 2100 => x"8d", + 2101 => x"2a", + 2102 => x"51", + 2103 => x"be", + 2104 => x"ff", + 2105 => x"c0", + 2106 => x"70", + 2107 => x"38", + 2108 => x"90", + 2109 => x"0c", + 2110 => x"04", + 2111 => x"79", + 2112 => x"33", + 2113 => x"06", + 2114 => x"70", + 2115 => x"fc", + 2116 => x"ff", + 2117 => x"82", + 2118 => x"70", + 2119 => x"59", + 2120 => x"87", + 2121 => x"51", + 2122 => x"86", + 2123 => x"94", + 2124 => x"08", + 2125 => x"70", + 2126 => x"54", + 2127 => x"2e", + 2128 => x"91", + 2129 => x"06", + 2130 => x"d7", + 2131 => x"32", + 2132 => x"51", + 2133 => x"2e", + 2134 => x"93", + 2135 => x"06", + 2136 => x"ff", + 2137 => x"81", + 2138 => x"87", + 2139 => x"52", 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x"a8", + 2199 => x"94", + 2200 => x"9e", + 2201 => x"84", + 2202 => x"c0", + 2203 => x"82", + 2204 => x"87", + 2205 => x"08", + 2206 => x"0c", + 2207 => x"a0", + 2208 => x"a4", + 2209 => x"9e", + 2210 => x"84", + 2211 => x"c0", + 2212 => x"82", + 2213 => x"87", + 2214 => x"08", + 2215 => x"0c", + 2216 => x"b8", + 2217 => x"b4", + 2218 => x"9e", + 2219 => x"84", + 2220 => x"c0", + 2221 => x"82", + 2222 => x"87", + 2223 => x"08", + 2224 => x"0c", + 2225 => x"80", + 2226 => x"82", + 2227 => x"87", + 2228 => x"08", + 2229 => x"0c", + 2230 => x"88", + 2231 => x"cc", + 2232 => x"9e", + 2233 => x"84", + 2234 => x"0b", + 2235 => x"34", + 2236 => x"c0", + 2237 => x"70", + 2238 => x"06", + 2239 => x"70", + 2240 => x"38", + 2241 => x"82", + 2242 => x"80", + 2243 => x"9e", + 2244 => x"88", + 2245 => x"51", + 2246 => x"80", + 2247 => x"81", + 2248 => x"84", + 2249 => x"0b", + 2250 => x"90", + 2251 => x"80", + 2252 => x"52", + 2253 => x"2e", + 2254 => x"52", + 2255 => x"d7", + 2256 => x"87", + 2257 => x"08", + 2258 => x"80", + 2259 => x"52", + 2260 => x"83", + 2261 => x"71", + 2262 => x"34", + 2263 => x"c0", + 2264 => x"70", + 2265 => x"06", + 2266 => x"70", + 2267 => x"38", + 2268 => x"82", + 2269 => x"80", + 2270 => x"9e", + 2271 => x"90", + 2272 => x"51", + 2273 => x"80", + 2274 => x"81", + 2275 => x"84", + 2276 => x"0b", + 2277 => x"90", + 2278 => x"80", + 2279 => x"52", + 2280 => x"2e", + 2281 => x"52", + 2282 => x"db", + 2283 => x"87", + 2284 => x"08", + 2285 => x"80", + 2286 => x"52", + 2287 => x"83", + 2288 => x"71", + 2289 => x"34", + 2290 => x"c0", + 2291 => x"70", + 2292 => x"06", + 2293 => x"70", + 2294 => x"38", + 2295 => x"82", + 2296 => x"80", + 2297 => x"9e", + 2298 => x"80", + 2299 => x"51", + 2300 => x"80", + 2301 => x"81", + 2302 => x"84", + 2303 => x"0b", + 2304 => x"90", + 2305 => x"80", + 2306 => x"52", + 2307 => x"83", + 2308 => x"71", + 2309 => x"34", + 2310 => x"90", + 2311 => x"80", + 2312 => x"2a", + 2313 => x"70", + 2314 => x"34", + 2315 => x"c0", + 2316 => x"70", + 2317 => x"51", + 2318 => x"80", + 2319 => x"81", + 2320 => x"84", + 2321 => x"c0", + 2322 => x"70", + 2323 => x"70", + 2324 => x"51", + 2325 => x"84", + 2326 => x"0b", + 2327 => x"90", + 2328 => x"06", + 2329 => x"70", + 2330 => x"38", + 2331 => x"82", + 2332 => x"87", + 2333 => x"08", + 2334 => x"51", + 2335 => x"84", + 2336 => x"3d", + 2337 => x"3d", + 2338 => x"a0", + 2339 => x"3f", + 2340 => x"33", + 2341 => x"2e", + 2342 => x"f5", + 2343 => x"cb", + 2344 => x"c8", + 2345 => x"3f", + 2346 => x"33", + 2347 => x"2e", + 2348 => x"84", + 2349 => x"84", + 2350 => x"54", + 2351 => x"e0", + 2352 => x"3f", + 2353 => x"33", + 2354 => x"2e", + 2355 => x"84", + 2356 => x"84", + 2357 => x"54", + 2358 => x"fc", + 2359 => x"3f", + 2360 => x"33", + 2361 => x"2e", + 2362 => x"84", + 2363 => x"84", + 2364 => x"54", + 2365 => x"98", + 2366 => x"3f", + 2367 => x"33", + 2368 => x"2e", + 2369 => x"84", + 2370 => x"84", + 2371 => x"54", + 2372 => x"b4", + 2373 => x"3f", + 2374 => x"33", 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x"d3", + 2434 => x"c8", + 2435 => x"84", + 2436 => x"51", + 2437 => x"82", + 2438 => x"54", + 2439 => x"52", + 2440 => x"08", + 2441 => x"3f", + 2442 => x"ec", + 2443 => x"73", + 2444 => x"c4", + 2445 => x"3f", + 2446 => x"33", + 2447 => x"2e", + 2448 => x"84", + 2449 => x"bd", + 2450 => x"74", + 2451 => x"3f", + 2452 => x"08", + 2453 => x"c0", + 2454 => x"ec", + 2455 => x"aa", + 2456 => x"85", + 2457 => x"53", + 2458 => x"f9", + 2459 => x"eb", + 2460 => x"d6", + 2461 => x"80", + 2462 => x"82", + 2463 => x"55", + 2464 => x"52", + 2465 => x"82", + 2466 => x"ec", + 2467 => x"84", + 2468 => x"85", + 2469 => x"cf", + 2470 => x"82", + 2471 => x"31", + 2472 => x"81", + 2473 => x"87", + 2474 => x"f2", + 2475 => x"bb", + 2476 => x"0d", + 2477 => x"0d", + 2478 => x"33", + 2479 => x"71", + 2480 => x"38", + 2481 => x"52", + 2482 => x"12", + 2483 => x"fa", + 2484 => x"39", + 2485 => x"51", + 2486 => x"fa", + 2487 => x"39", + 2488 => x"51", + 2489 => x"fa", + 2490 => x"39", + 2491 => x"51", + 2492 => x"84", + 2493 => x"71", + 2494 => x"04", + 2495 => x"c0", + 2496 => x"04", + 2497 => x"08", + 2498 => x"84", + 2499 => x"3d", + 2500 => x"05", + 2501 => x"8a", + 2502 => x"06", + 2503 => x"51", + 2504 => x"9c", + 2505 => x"71", + 2506 => x"38", + 2507 => x"82", + 2508 => x"81", + 2509 => x"fc", + 2510 => x"82", + 2511 => x"52", + 2512 => x"85", + 2513 => x"71", + 2514 => x"0d", + 2515 => x"0d", + 2516 => x"33", + 2517 => x"08", + 2518 => x"f4", + 2519 => x"ff", + 2520 => x"82", + 2521 => x"84", + 2522 => x"fd", + 2523 => x"54", + 2524 => x"81", + 2525 => x"53", + 2526 => x"8e", + 2527 => x"ff", + 2528 => x"14", + 2529 => x"3f", + 2530 => x"3d", + 2531 => x"3d", + 2532 => x"9c", + 2533 => x"82", + 2534 => x"56", + 2535 => x"70", + 2536 => x"53", + 2537 => x"2e", + 2538 => x"81", + 2539 => x"81", + 2540 => x"da", + 2541 => x"74", + 2542 => x"0c", + 2543 => x"04", + 2544 => x"66", + 2545 => x"78", + 2546 => x"5a", + 2547 => x"80", + 2548 => x"38", + 2549 => x"09", + 2550 => x"e4", + 2551 => x"7a", + 2552 => x"5c", + 2553 => x"5b", + 2554 => x"09", + 2555 => x"38", + 2556 => x"39", + 2557 => x"09", + 2558 => x"38", + 2559 => x"70", + 2560 => x"33", + 2561 => x"2e", + 2562 => x"92", + 2563 => x"19", + 2564 => x"70", + 2565 => x"33", + 2566 => x"53", + 2567 => x"16", + 2568 => x"26", + 2569 => x"83", + 2570 => x"7c", + 2571 => x"05", + 2572 => x"05", + 2573 => x"5d", + 2574 => x"39", + 2575 => x"32", + 2576 => x"05", + 2577 => x"80", + 2578 => x"cc", + 2579 => x"81", + 2580 => x"07", + 2581 => x"07", + 2582 => x"51", + 2583 => x"80", + 2584 => x"79", + 2585 => x"70", + 2586 => x"33", + 2587 => x"80", + 2588 => x"38", + 2589 => x"e0", + 2590 => x"38", + 2591 => x"81", + 2592 => x"53", + 2593 => x"2e", + 2594 => x"73", + 2595 => x"a2", + 2596 => x"c3", + 2597 => x"38", + 2598 => x"24", + 2599 => x"80", + 2600 => x"8c", + 2601 => x"39", + 2602 => x"2e", + 2603 => x"81", + 2604 => x"80", + 2605 => x"80", + 2606 => x"d5", + 2607 => x"73", + 2608 => x"8e", + 2609 => x"39", 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x"2e", + 2669 => x"14", + 2670 => x"ff", + 2671 => x"14", + 2672 => x"70", + 2673 => x"34", + 2674 => x"09", + 2675 => x"77", + 2676 => x"51", + 2677 => x"9f", + 2678 => x"72", + 2679 => x"79", + 2680 => x"81", + 2681 => x"72", + 2682 => x"38", + 2683 => x"05", + 2684 => x"ad", + 2685 => x"17", + 2686 => x"81", + 2687 => x"b0", + 2688 => x"38", + 2689 => x"81", + 2690 => x"06", + 2691 => x"9f", + 2692 => x"55", + 2693 => x"97", + 2694 => x"f9", + 2695 => x"81", + 2696 => x"8b", + 2697 => x"16", + 2698 => x"73", + 2699 => x"96", + 2700 => x"e0", + 2701 => x"17", + 2702 => x"33", + 2703 => x"f9", + 2704 => x"f2", + 2705 => x"16", + 2706 => x"7b", + 2707 => x"38", + 2708 => x"ba", + 2709 => x"96", + 2710 => x"fd", + 2711 => x"3d", + 2712 => x"05", + 2713 => x"52", + 2714 => x"d4", + 2715 => x"0d", + 2716 => x"0d", + 2717 => x"fc", + 2718 => x"88", + 2719 => x"51", + 2720 => x"82", + 2721 => x"53", + 2722 => x"80", + 2723 => x"fc", + 2724 => x"0d", + 2725 => x"0d", + 2726 => x"08", + 2727 => x"f4", + 2728 => x"88", + 2729 => x"52", + 2730 => x"3f", + 2731 => x"f4", + 2732 => x"0d", + 2733 => x"0d", + 2734 => x"9c", + 2735 => x"56", + 2736 => x"80", + 2737 => x"2e", + 2738 => x"82", + 2739 => x"52", + 2740 => x"85", + 2741 => x"ff", + 2742 => x"80", + 2743 => x"38", + 2744 => x"bc", + 2745 => x"32", + 2746 => x"05", + 2747 => x"51", + 2748 => x"80", + 2749 => x"71", + 2750 => x"38", + 2751 => x"98", + 2752 => x"25", + 2753 => x"16", + 2754 => x"25", + 2755 => x"74", + 2756 => x"72", + 2757 => x"54", + 2758 => x"f2", + 2759 => x"39", + 2760 => x"80", + 2761 => x"51", + 2762 => x"81", + 2763 => x"85", + 2764 => x"3d", + 2765 => x"3d", + 2766 => x"f8", + 2767 => x"9c", + 2768 => x"53", + 2769 => x"fe", + 2770 => x"82", + 2771 => x"84", + 2772 => x"f8", + 2773 => x"7c", + 2774 => x"70", + 2775 => x"75", + 2776 => x"55", + 2777 => x"2e", + 2778 => x"87", + 2779 => x"76", + 2780 => x"73", + 2781 => x"81", + 2782 => x"81", + 2783 => x"77", + 2784 => x"70", + 2785 => x"58", + 2786 => x"09", + 2787 => x"c2", + 2788 => x"81", + 2789 => x"75", + 2790 => x"55", + 2791 => x"e2", + 2792 => x"90", + 2793 => x"f8", + 2794 => x"8f", + 2795 => x"81", + 2796 => x"75", + 2797 => x"55", + 2798 => x"81", + 2799 => x"27", + 2800 => x"d0", + 2801 => x"55", + 2802 => x"73", + 2803 => x"80", + 2804 => x"14", + 2805 => x"72", + 2806 => x"ea", + 2807 => x"80", + 2808 => x"39", + 2809 => x"55", + 2810 => x"80", + 2811 => x"e0", + 2812 => x"38", + 2813 => x"81", + 2814 => x"53", + 2815 => x"81", + 2816 => x"53", + 2817 => x"8e", + 2818 => x"70", + 2819 => x"55", + 2820 => x"27", + 2821 => x"77", + 2822 => x"76", + 2823 => x"c4", + 2824 => x"85", + 2825 => x"76", + 2826 => x"77", + 2827 => x"70", + 2828 => x"55", + 2829 => x"77", + 2830 => x"38", + 2831 => x"05", + 2832 => x"0c", + 2833 => x"82", + 2834 => x"8a", + 2835 => x"f8", + 2836 => x"7c", + 2837 => x"70", + 2838 => x"75", + 2839 => x"55", + 2840 => x"2e", + 2841 => x"87", + 2842 => x"76", + 2843 => x"73", + 2844 => x"81", + 2845 => x"81", + 2846 => x"77", + 2847 => x"70", + 2848 => x"58", + 2849 => x"09", + 2850 => x"c2", + 2851 => x"81", + 2852 => x"75", + 2853 => x"55", + 2854 => x"e2", + 2855 => x"90", + 2856 => x"f8", + 2857 => x"8f", + 2858 => x"81", + 2859 => x"75", + 2860 => x"55", + 2861 => x"81", + 2862 => x"27", + 2863 => x"d0", + 2864 => x"55", + 2865 => x"73", + 2866 => x"80", + 2867 => x"14", + 2868 => x"72", + 2869 => x"ea", + 2870 => x"80", + 2871 => x"39", + 2872 => x"55", + 2873 => x"80", + 2874 => x"e0", + 2875 => x"38", + 2876 => x"81", + 2877 => x"53", + 2878 => x"81", + 2879 => x"53", + 2880 => x"8e", + 2881 => x"70", + 2882 => x"55", + 2883 => x"27", + 2884 => x"77", + 2885 => x"76", + 2886 => x"c2", + 2887 => x"85", + 2888 => x"76", + 2889 => x"77", + 2890 => x"70", + 2891 => x"55", + 2892 => x"77", + 2893 => x"38", + 2894 => x"05", + 2895 => x"0c", + 2896 => x"82", + 2897 => x"8a", + 2898 => x"fd", + 2899 => x"98", + 2900 => x"2c", + 2901 => x"70", + 2902 => x"10", + 2903 => x"2b", + 2904 => x"55", + 2905 => x"0b", + 2906 => x"12", + 2907 => x"72", + 2908 => x"38", + 2909 => x"f4", + 2910 => x"02", + 2911 => x"05", + 2912 => x"52", + 2913 => x"70", + 2914 => x"81", + 2915 => x"81", + 2916 => x"71", + 2917 => x"0c", + 2918 => x"04", + 2919 => x"78", + 2920 => x"9f", + 2921 => x"33", + 2922 => x"71", + 2923 => x"38", + 2924 => x"da", + 2925 => x"f2", + 2926 => x"51", + 2927 => x"72", + 2928 => x"52", + 2929 => x"71", + 2930 => x"52", + 2931 => x"51", + 2932 => x"73", + 2933 => x"3d", + 2934 => x"3d", + 2935 => x"84", + 2936 => x"33", + 2937 => x"bb", + 2938 => x"85", + 2939 => x"82", + 2940 => x"ec", + 2941 => x"59", + 2942 => x"59", + 2943 => x"86", + 2944 => x"9a", + 2945 => x"85", + 2946 => x"82", + 2947 => x"ec", + 2948 => x"70", + 2949 => x"56", + 2950 => x"3f", + 2951 => x"08", + 2952 => x"85", + 2953 => x"82", + 2954 => x"ec", + 2955 => x"56", + 2956 => x"2e", + 2957 => x"53", + 2958 => x"51", + 2959 => x"3f", + 2960 => x"33", + 2961 => x"74", + 2962 => x"34", + 2963 => x"06", + 2964 => x"27", + 2965 => x"0b", + 2966 => x"34", + 2967 => x"b6", + 2968 => x"c0", + 2969 => x"80", + 2970 => x"82", + 2971 => x"55", + 2972 => x"8c", + 2973 => x"54", + 2974 => x"52", + 2975 => x"d5", + 2976 => x"85", + 2977 => x"8a", + 2978 => x"cd", + 2979 => x"c0", + 2980 => x"d8", + 2981 => x"3d", + 2982 => x"3d", + 2983 => x"ec", + 2984 => x"72", + 2985 => x"80", + 2986 => x"71", + 2987 => x"3f", + 2988 => x"ff", + 2989 => x"54", + 2990 => x"25", + 2991 => x"0b", + 2992 => x"34", + 2993 => x"08", + 2994 => x"2e", + 2995 => x"51", + 2996 => x"3f", + 2997 => x"08", + 2998 => x"3f", + 2999 => x"85", + 3000 => x"3d", + 3001 => x"3d", + 3002 => x"80", + 3003 => x"c0", + 3004 => x"de", + 3005 => x"85", + 3006 => x"d2", + 3007 => x"c0", + 3008 => x"f8", + 3009 => x"70", + 3010 => x"87", + 3011 => x"85", + 3012 => x"2e", + 3013 => x"51", + 3014 => x"3f", + 3015 => x"08", + 3016 => x"82", + 3017 => x"25", + 3018 => x"85", + 3019 => x"05", + 3020 => x"55", + 3021 => x"75", + 3022 => x"81", + 3023 => x"e8", + 3024 => x"97", + 3025 => x"2e", + 3026 => x"ff", + 3027 => x"3d", + 3028 => x"3d", + 3029 => x"08", + 3030 => x"5a", + 3031 => x"58", + 3032 => x"82", + 3033 => x"51", + 3034 => x"3f", + 3035 => x"08", + 3036 => x"ff", + 3037 => x"c0", + 3038 => x"80", + 3039 => x"3d", + 3040 => x"81", + 3041 => x"82", + 3042 => x"80", + 3043 => x"75", + 3044 => x"a5", + 3045 => x"ec", + 3046 => x"58", + 3047 => x"82", + 3048 => x"25", + 3049 => x"85", + 3050 => x"05", + 3051 => x"55", + 3052 => x"74", + 3053 => x"81", + 3054 => x"07", + 3055 => x"55", + 3056 => x"2e", + 3057 => x"ff", + 3058 => x"85", + 3059 => x"11", + 3060 => x"80", + 3061 => x"82", + 3062 => x"80", + 3063 => x"81", + 3064 => x"ef", + 3065 => x"77", + 3066 => x"06", + 3067 => x"52", + 3068 => x"b4", + 3069 => x"51", + 3070 => x"3f", + 3071 => x"54", + 3072 => x"08", + 3073 => x"58", + 3074 => x"ec", + 3075 => x"0d", + 3076 => x"0d", + 3077 => x"5c", + 3078 => x"57", + 3079 => x"73", + 3080 => x"81", + 3081 => x"78", + 3082 => x"56", + 3083 => x"98", + 3084 => x"70", + 3085 => x"33", + 3086 => x"73", + 3087 => x"81", + 3088 => x"75", + 3089 => x"38", + 3090 => x"83", + 3091 => x"c8", + 3092 => x"53", + 3093 => x"b2", + 3094 => x"85", + 3095 => x"79", + 3096 => x"51", + 3097 => x"3f", + 3098 => x"08", + 3099 => x"84", + 3100 => x"73", + 3101 => x"38", + 3102 => x"88", + 3103 => x"fc", + 3104 => x"39", + 3105 => x"8c", + 3106 => x"53", + 3107 => x"f5", + 3108 => x"85", + 3109 => x"2e", + 3110 => x"1b", + 3111 => x"77", + 3112 => x"3f", + 3113 => x"08", + 3114 => x"54", + 3115 => x"91", + 3116 => x"70", + 3117 => x"56", + 3118 => x"27", + 3119 => x"80", + 3120 => x"85", + 3121 => x"3d", + 3122 => x"3d", + 3123 => x"08", + 3124 => x"b4", + 3125 => x"5f", + 3126 => x"af", + 3127 => x"85", + 3128 => x"85", + 3129 => x"5b", + 3130 => x"38", + 3131 => x"bc", + 3132 => x"73", + 3133 => x"55", + 3134 => x"81", + 3135 => x"70", + 3136 => x"56", + 3137 => x"81", + 3138 => x"51", + 3139 => x"82", + 3140 => x"82", + 3141 => x"82", + 3142 => x"80", + 3143 => x"38", + 3144 => x"52", + 3145 => x"08", + 3146 => x"90", + 3147 => x"ec", + 3148 => x"8b", + 3149 => x"a0", + 3150 => x"3f", + 3151 => x"82", + 3152 => x"5b", + 3153 => x"08", + 3154 => x"52", + 3155 => x"52", + 3156 => x"ec", + 3157 => x"ec", + 3158 => x"85", + 3159 => x"2e", + 3160 => x"80", + 3161 => x"85", + 3162 => x"ff", + 3163 => x"82", + 3164 => x"55", + 3165 => x"85", + 3166 => x"a9", + 3167 => x"ec", + 3168 => x"70", + 3169 => x"80", + 3170 => x"53", + 3171 => x"06", + 3172 => x"f8", + 3173 => x"1b", + 3174 => x"06", + 3175 => x"7b", + 3176 => x"80", + 3177 => x"2e", + 3178 => x"ff", + 3179 => x"39", + 3180 => x"bc", + 3181 => x"38", + 3182 => x"08", + 3183 => x"38", + 3184 => x"8f", + 3185 => x"9c", + 3186 => x"ec", + 3187 => x"70", + 3188 => x"59", + 3189 => x"ee", + 3190 => x"ff", + 3191 => x"84", + 3192 => x"2b", + 3193 => x"82", + 3194 => x"70", + 3195 => x"97", + 3196 => x"2c", + 3197 => x"2b", + 3198 => x"11", + 3199 => x"33", + 3200 => x"51", + 3201 => x"59", + 3202 => x"56", + 3203 => x"80", + 3204 => x"74", + 3205 => x"ff", + 3206 => x"2b", + 3207 => x"51", + 3208 => x"75", + 3209 => x"38", + 3210 => x"52", + 3211 => x"9b", + 3212 => x"ec", + 3213 => x"06", + 3214 => x"2e", + 3215 => x"82", + 3216 => x"81", + 3217 => x"81", + 3218 => x"2b", + 3219 => x"70", + 3220 => x"53", + 3221 => x"73", + 3222 => x"38", + 3223 => x"52", + 3224 => x"e7", + 3225 => x"ec", + 3226 => x"06", + 3227 => x"38", + 3228 => x"56", + 3229 => x"80", + 3230 => x"1c", + 3231 => x"9d", + 3232 => x"98", + 3233 => x"2c", + 3234 => x"33", + 3235 => x"70", + 3236 => x"10", + 3237 => x"2b", + 3238 => x"11", + 3239 => x"53", + 3240 => x"51", + 3241 => x"2e", + 3242 => x"fe", + 3243 => x"fa", + 3244 => x"7d", + 3245 => x"82", + 3246 => x"80", + 3247 => x"80", + 3248 => x"75", + 3249 => x"34", + 3250 => x"80", + 3251 => x"3d", + 3252 => x"0c", + 3253 => x"95", + 3254 => x"38", + 3255 => x"54", + 3256 => x"14", + 3257 => x"9d", + 3258 => x"75", + 3259 => x"d3", + 3260 => x"88", + 3261 => x"74", + 3262 => x"73", + 3263 => x"98", + 3264 => x"75", + 3265 => x"38", + 3266 => x"73", + 3267 => x"34", + 3268 => x"98", + 3269 => x"2c", + 3270 => x"33", + 3271 => x"54", + 3272 => x"e4", + 3273 => x"8c", + 3274 => x"56", + 3275 => x"9d", + 3276 => x"1a", + 3277 => x"33", + 3278 => x"9d", + 3279 => x"73", + 3280 => x"38", + 3281 => x"73", + 3282 => x"34", + 3283 => x"33", + 3284 => x"98", + 3285 => x"2c", + 3286 => x"33", + 3287 => x"54", + 3288 => x"9f", + 3289 => x"70", + 3290 => x"e7", + 3291 => x"15", + 3292 => x"70", + 3293 => x"9d", + 3294 => x"51", + 3295 => x"75", + 3296 => x"82", + 3297 => x"70", + 3298 => x"98", + 3299 => x"88", + 3300 => x"56", + 3301 => x"25", + 3302 => x"88", + 3303 => x"3f", + 3304 => x"98", + 3305 => x"2c", + 3306 => x"33", + 3307 => x"54", + 3308 => x"e7", + 3309 => x"39", + 3310 => x"80", + 3311 => x"34", + 3312 => x"53", + 3313 => x"f3", + 3314 => x"d0", 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x"ec", + 3374 => x"0d", + 3375 => x"8c", + 3376 => x"80", + 3377 => x"38", + 3378 => x"c2", + 3379 => x"8c", + 3380 => x"54", + 3381 => x"8c", + 3382 => x"ff", + 3383 => x"39", + 3384 => x"33", + 3385 => x"33", + 3386 => x"75", + 3387 => x"38", + 3388 => x"73", + 3389 => x"34", + 3390 => x"70", + 3391 => x"81", + 3392 => x"51", + 3393 => x"25", + 3394 => x"1a", + 3395 => x"33", + 3396 => x"33", + 3397 => x"3f", + 3398 => x"98", + 3399 => x"2c", + 3400 => x"33", + 3401 => x"54", + 3402 => x"de", + 3403 => x"e3", + 3404 => x"9d", + 3405 => x"98", + 3406 => x"2c", + 3407 => x"33", + 3408 => x"57", + 3409 => x"f8", + 3410 => x"51", + 3411 => x"81", + 3412 => x"2b", + 3413 => x"82", + 3414 => x"59", + 3415 => x"75", + 3416 => x"38", + 3417 => x"82", + 3418 => x"70", + 3419 => x"82", + 3420 => x"59", + 3421 => x"77", + 3422 => x"38", + 3423 => x"73", + 3424 => x"34", + 3425 => x"33", + 3426 => x"82", + 3427 => x"8c", + 3428 => x"ff", + 3429 => x"88", + 3430 => x"54", + 3431 => x"dc", + 3432 => x"39", + 3433 => x"53", + 3434 => x"f3", + 3435 => x"ec", + 3436 => x"82", + 3437 => x"80", + 3438 => x"88", + 3439 => x"39", + 3440 => x"82", + 3441 => x"55", + 3442 => x"a6", + 3443 => x"ff", + 3444 => x"82", + 3445 => x"82", + 3446 => x"82", + 3447 => x"81", + 3448 => x"05", + 3449 => x"79", + 3450 => x"ad", + 3451 => x"81", + 3452 => x"82", + 3453 => x"ec", + 3454 => x"08", + 3455 => x"74", + 3456 => x"38", + 3457 => x"a7", + 3458 => x"85", + 3459 => x"9d", + 3460 => x"85", + 3461 => x"ff", + 3462 => x"53", + 3463 => x"51", + 3464 => x"3f", + 3465 => x"80", + 3466 => x"08", + 3467 => x"2e", + 3468 => x"74", + 3469 => x"81", + 3470 => x"7a", + 3471 => x"81", + 3472 => x"82", + 3473 => x"55", + 3474 => x"a4", + 3475 => x"ff", + 3476 => x"82", + 3477 => x"82", + 3478 => x"82", + 3479 => x"81", + 3480 => x"05", + 3481 => x"79", + 3482 => x"ad", + 3483 => x"39", + 3484 => x"82", + 3485 => x"08", + 3486 => x"80", + 3487 => x"74", + 3488 => x"b5", + 3489 => x"ec", + 3490 => x"88", + 3491 => x"ec", + 3492 => x"06", + 3493 => x"74", + 3494 => x"ff", + 3495 => x"81", + 3496 => x"81", + 3497 => x"89", + 3498 => x"9d", + 3499 => x"7a", + 3500 => x"8c", + 3501 => x"88", + 3502 => x"51", + 3503 => x"f6", + 3504 => x"9d", + 3505 => x"81", + 3506 => x"9d", + 3507 => x"56", + 3508 => x"27", + 3509 => x"81", + 3510 => x"82", + 3511 => x"74", + 3512 => x"52", + 3513 => x"3f", + 3514 => x"82", + 3515 => x"54", + 3516 => x"f5", + 3517 => x"51", + 3518 => x"82", + 3519 => x"ff", + 3520 => x"82", + 3521 => x"f5", + 3522 => x"3d", + 3523 => x"f4", + 3524 => x"e4", + 3525 => x"0b", + 3526 => x"23", + 3527 => x"80", + 3528 => x"f4", + 3529 => x"c5", + 3530 => x"e4", + 3531 => x"58", + 3532 => x"81", + 3533 => x"15", + 3534 => x"e4", + 3535 => x"84", + 3536 => x"85", + 3537 => x"85", + 3538 => x"77", + 3539 => x"76", + 3540 => x"82", + 3541 => x"82", + 3542 => x"ff", + 3543 => x"80", + 3544 => x"ff", + 3545 => x"88", + 3546 => x"55", + 3547 => x"17", + 3548 => x"17", + 3549 => x"e0", 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x"72", + 3609 => x"33", + 3610 => x"71", + 3611 => x"83", + 3612 => x"5b", + 3613 => x"52", + 3614 => x"12", + 3615 => x"33", + 3616 => x"07", + 3617 => x"54", + 3618 => x"70", + 3619 => x"73", + 3620 => x"82", + 3621 => x"70", + 3622 => x"33", + 3623 => x"71", + 3624 => x"83", + 3625 => x"59", + 3626 => x"05", + 3627 => x"87", + 3628 => x"88", + 3629 => x"88", + 3630 => x"56", + 3631 => x"13", + 3632 => x"13", + 3633 => x"e4", + 3634 => x"33", + 3635 => x"71", + 3636 => x"70", + 3637 => x"06", + 3638 => x"53", + 3639 => x"53", + 3640 => x"70", + 3641 => x"87", + 3642 => x"f9", + 3643 => x"a6", + 3644 => x"85", + 3645 => x"83", + 3646 => x"70", + 3647 => x"33", + 3648 => x"07", + 3649 => x"53", + 3650 => x"58", + 3651 => x"33", + 3652 => x"71", + 3653 => x"90", + 3654 => x"5a", + 3655 => x"71", + 3656 => x"f6", + 3657 => x"fe", + 3658 => x"85", + 3659 => x"17", + 3660 => x"12", + 3661 => x"2b", + 3662 => x"07", + 3663 => x"33", + 3664 => x"71", + 3665 => x"70", + 3666 => x"ff", + 3667 => x"52", + 3668 => x"57", + 3669 => x"05", + 3670 => x"54", + 3671 => x"13", + 3672 => x"13", + 3673 => x"e4", + 3674 => x"70", + 3675 => x"33", + 3676 => x"71", + 3677 => x"56", + 3678 => x"72", + 3679 => x"81", + 3680 => x"88", + 3681 => x"81", + 3682 => x"70", + 3683 => x"51", + 3684 => x"72", + 3685 => x"81", + 3686 => x"3d", + 3687 => x"3d", + 3688 => x"e4", + 3689 => x"05", + 3690 => x"70", + 3691 => x"11", + 3692 => x"83", + 3693 => x"8b", + 3694 => x"2b", + 3695 => x"59", + 3696 => x"73", + 3697 => x"81", + 3698 => x"88", + 3699 => x"8c", + 3700 => x"22", + 3701 => x"88", + 3702 => x"53", + 3703 => x"73", + 3704 => x"14", + 3705 => x"e4", + 3706 => x"70", + 3707 => x"33", + 3708 => x"71", + 3709 => x"56", + 3710 => x"72", + 3711 => x"33", + 3712 => x"71", + 3713 => x"70", + 3714 => x"55", + 3715 => x"82", + 3716 => x"83", + 3717 => x"85", + 3718 => x"82", + 3719 => x"12", + 3720 => x"2b", + 3721 => x"ec", + 3722 => x"87", + 3723 => x"f7", + 3724 => x"82", + 3725 => x"31", + 3726 => x"83", + 3727 => x"70", + 3728 => x"fd", + 3729 => x"85", + 3730 => x"83", + 3731 => x"82", + 3732 => x"12", + 3733 => x"2b", + 3734 => x"07", + 3735 => x"33", + 3736 => x"71", + 3737 => x"90", + 3738 => x"42", + 3739 => x"5b", + 3740 => x"54", + 3741 => x"8d", + 3742 => x"80", + 3743 => x"fe", + 3744 => x"84", + 3745 => x"33", + 3746 => x"71", + 3747 => x"83", + 3748 => x"11", + 3749 => x"53", + 3750 => x"55", + 3751 => x"34", + 3752 => x"06", + 3753 => x"14", + 3754 => x"e4", + 3755 => x"84", + 3756 => x"13", + 3757 => x"2b", + 3758 => x"2a", + 3759 => x"56", + 3760 => x"16", + 3761 => x"16", + 3762 => x"e4", + 3763 => x"80", + 3764 => x"34", + 3765 => x"14", + 3766 => x"e4", + 3767 => x"84", + 3768 => x"85", + 3769 => x"85", + 3770 => x"70", + 3771 => x"33", + 3772 => x"07", + 3773 => x"80", + 3774 => x"2a", + 3775 => x"56", + 3776 => x"34", + 3777 => x"34", + 3778 => x"04", + 3779 => x"73", + 3780 => x"e4", + 3781 => x"f7", + 3782 => x"80", + 3783 => x"71", + 3784 => x"3f", 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x"ff", + 3844 => x"88", + 3845 => x"56", + 3846 => x"15", + 3847 => x"ff", + 3848 => x"85", + 3849 => x"85", + 3850 => x"83", + 3851 => x"72", + 3852 => x"33", + 3853 => x"71", + 3854 => x"70", + 3855 => x"5b", + 3856 => x"56", + 3857 => x"19", + 3858 => x"19", + 3859 => x"e4", + 3860 => x"84", + 3861 => x"12", + 3862 => x"2b", + 3863 => x"07", + 3864 => x"55", + 3865 => x"78", + 3866 => x"76", + 3867 => x"82", + 3868 => x"70", + 3869 => x"84", + 3870 => x"12", + 3871 => x"2b", + 3872 => x"2a", + 3873 => x"52", + 3874 => x"84", + 3875 => x"85", + 3876 => x"85", + 3877 => x"84", + 3878 => x"82", + 3879 => x"8d", + 3880 => x"fe", + 3881 => x"52", + 3882 => x"08", + 3883 => x"da", + 3884 => x"71", + 3885 => x"38", + 3886 => x"ec", + 3887 => x"ec", + 3888 => x"82", + 3889 => x"84", + 3890 => x"ff", + 3891 => x"8f", + 3892 => x"81", + 3893 => x"26", + 3894 => x"85", + 3895 => x"52", + 3896 => x"ec", + 3897 => x"0d", + 3898 => x"0d", + 3899 => x"33", + 3900 => x"9f", + 3901 => x"53", + 3902 => x"81", + 3903 => x"38", + 3904 => x"87", + 3905 => x"11", + 3906 => x"54", + 3907 => x"84", + 3908 => x"54", + 3909 => x"87", + 3910 => x"11", + 3911 => x"0c", + 3912 => x"c0", + 3913 => x"70", + 3914 => x"70", + 3915 => x"51", + 3916 => x"8a", + 3917 => x"98", + 3918 => x"70", + 3919 => x"08", + 3920 => x"06", + 3921 => x"38", + 3922 => x"8c", + 3923 => x"80", + 3924 => x"71", + 3925 => x"14", + 3926 => x"e8", + 3927 => x"70", + 3928 => x"0c", + 3929 => x"04", + 3930 => x"60", + 3931 => x"8c", + 3932 => x"33", + 3933 => x"5b", + 3934 => x"5a", + 3935 => x"82", + 3936 => x"81", + 3937 => x"52", + 3938 => x"38", + 3939 => x"84", + 3940 => x"92", + 3941 => x"c0", + 3942 => x"87", + 3943 => x"13", + 3944 => x"57", + 3945 => x"0b", + 3946 => x"8c", + 3947 => x"0c", + 3948 => x"75", + 3949 => x"2a", + 3950 => x"51", + 3951 => x"80", + 3952 => x"7b", + 3953 => x"7b", + 3954 => x"5d", + 3955 => x"59", + 3956 => x"06", + 3957 => x"73", + 3958 => x"81", + 3959 => x"ff", + 3960 => x"72", + 3961 => x"38", + 3962 => x"8c", + 3963 => x"c3", + 3964 => x"98", + 3965 => x"71", + 3966 => x"38", + 3967 => x"2e", + 3968 => x"76", + 3969 => x"92", + 3970 => x"72", + 3971 => x"06", + 3972 => x"f7", + 3973 => x"5a", + 3974 => x"80", + 3975 => x"70", + 3976 => x"5a", + 3977 => x"80", + 3978 => x"73", + 3979 => x"06", + 3980 => x"38", + 3981 => x"fe", + 3982 => x"fc", + 3983 => x"52", + 3984 => x"83", + 3985 => x"71", + 3986 => x"85", + 3987 => x"3d", + 3988 => x"3d", + 3989 => x"64", + 3990 => x"bf", + 3991 => x"40", + 3992 => x"59", + 3993 => x"58", + 3994 => x"82", + 3995 => x"81", + 3996 => x"52", + 3997 => x"09", + 3998 => x"b1", + 3999 => x"84", + 4000 => x"92", + 4001 => x"c0", + 4002 => x"87", + 4003 => x"13", + 4004 => x"56", + 4005 => x"87", + 4006 => x"0c", + 4007 => x"82", + 4008 => x"58", + 4009 => x"84", + 4010 => x"06", + 4011 => x"71", + 4012 => x"38", + 4013 => x"05", + 4014 => x"0c", + 4015 => x"73", + 4016 => x"81", + 4017 => x"71", + 4018 => x"38", + 4019 => x"8c", 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x"52", + 4079 => x"96", + 4080 => x"92", + 4081 => x"0a", + 4082 => x"39", + 4083 => x"0c", + 4084 => x"39", + 4085 => x"54", + 4086 => x"ec", + 4087 => x"0d", + 4088 => x"0d", + 4089 => x"33", + 4090 => x"88", + 4091 => x"85", + 4092 => x"51", + 4093 => x"04", + 4094 => x"75", + 4095 => x"82", + 4096 => x"90", + 4097 => x"2b", + 4098 => x"33", + 4099 => x"88", + 4100 => x"71", + 4101 => x"ec", + 4102 => x"54", + 4103 => x"85", + 4104 => x"ff", + 4105 => x"02", + 4106 => x"05", + 4107 => x"70", + 4108 => x"05", + 4109 => x"88", + 4110 => x"72", + 4111 => x"0d", + 4112 => x"0d", + 4113 => x"52", + 4114 => x"81", + 4115 => x"70", + 4116 => x"70", + 4117 => x"05", + 4118 => x"88", + 4119 => x"72", + 4120 => x"54", + 4121 => x"2a", + 4122 => x"34", + 4123 => x"04", + 4124 => x"76", + 4125 => x"54", + 4126 => x"2e", + 4127 => x"70", + 4128 => x"33", + 4129 => x"05", + 4130 => x"11", + 4131 => x"84", + 4132 => x"fe", + 4133 => x"77", + 4134 => x"53", + 4135 => x"81", + 4136 => x"ff", + 4137 => x"f4", + 4138 => x"0d", + 4139 => x"0d", + 4140 => x"56", + 4141 => x"70", + 4142 => x"33", + 4143 => x"05", + 4144 => x"71", + 4145 => x"56", + 4146 => x"72", + 4147 => x"38", + 4148 => x"e2", + 4149 => x"85", + 4150 => x"3d", + 4151 => x"3d", + 4152 => x"54", + 4153 => x"71", + 4154 => x"38", + 4155 => x"70", + 4156 => x"f3", + 4157 => x"82", + 4158 => x"84", + 4159 => x"80", + 4160 => x"ec", + 4161 => x"0b", + 4162 => x"0c", + 4163 => x"0d", + 4164 => x"0b", + 4165 => x"56", + 4166 => x"2e", + 4167 => x"81", + 4168 => x"08", + 4169 => x"70", + 4170 => x"33", + 4171 => x"a2", + 4172 => x"ec", + 4173 => x"09", + 4174 => x"38", + 4175 => x"08", + 4176 => x"b0", + 4177 => x"a4", + 4178 => x"9c", + 4179 => x"56", + 4180 => x"27", + 4181 => x"16", + 4182 => x"82", + 4183 => x"06", + 4184 => x"54", + 4185 => x"78", + 4186 => x"33", + 4187 => x"3f", + 4188 => x"5a", + 4189 => x"ec", + 4190 => x"0d", + 4191 => x"0d", + 4192 => x"56", + 4193 => x"b0", + 4194 => x"af", + 4195 => x"fe", + 4196 => x"85", + 4197 => x"82", + 4198 => x"9f", + 4199 => x"74", + 4200 => x"52", + 4201 => x"51", + 4202 => x"82", + 4203 => x"80", + 4204 => x"ff", + 4205 => x"74", + 4206 => x"76", + 4207 => x"0c", + 4208 => x"04", + 4209 => x"7a", + 4210 => x"fe", + 4211 => x"85", + 4212 => x"82", + 4213 => x"81", + 4214 => x"33", + 4215 => x"2e", + 4216 => x"80", + 4217 => x"17", + 4218 => x"81", + 4219 => x"06", + 4220 => x"84", + 4221 => x"85", + 4222 => x"b4", + 4223 => x"56", + 4224 => x"82", + 4225 => x"84", + 4226 => x"fc", + 4227 => x"8b", + 4228 => x"52", + 4229 => x"a9", + 4230 => x"85", + 4231 => x"84", + 4232 => x"fc", + 4233 => x"17", + 4234 => x"9c", + 4235 => x"91", + 4236 => x"08", + 4237 => x"17", + 4238 => x"3f", + 4239 => x"81", + 4240 => x"19", + 4241 => x"53", + 4242 => x"17", + 4243 => x"82", + 4244 => x"18", + 4245 => x"80", + 4246 => x"33", + 4247 => x"3f", + 4248 => x"08", + 4249 => x"38", + 4250 => x"82", + 4251 => x"8a", + 4252 => x"fb", + 4253 => x"fe", + 4254 => x"08", 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x"76", + 4314 => x"15", + 4315 => x"73", + 4316 => x"3f", + 4317 => x"08", + 4318 => x"82", + 4319 => x"06", + 4320 => x"05", + 4321 => x"3f", + 4322 => x"08", + 4323 => x"58", + 4324 => x"58", + 4325 => x"ec", + 4326 => x"0d", + 4327 => x"0d", + 4328 => x"5a", + 4329 => x"59", + 4330 => x"82", + 4331 => x"98", + 4332 => x"82", + 4333 => x"33", + 4334 => x"2e", + 4335 => x"72", + 4336 => x"38", + 4337 => x"8d", + 4338 => x"39", + 4339 => x"81", + 4340 => x"f7", + 4341 => x"2a", + 4342 => x"2a", + 4343 => x"05", + 4344 => x"55", + 4345 => x"82", + 4346 => x"59", + 4347 => x"08", + 4348 => x"74", + 4349 => x"16", + 4350 => x"16", + 4351 => x"59", + 4352 => x"53", + 4353 => x"8f", + 4354 => x"2b", + 4355 => x"74", + 4356 => x"71", + 4357 => x"72", + 4358 => x"0b", + 4359 => x"74", + 4360 => x"17", + 4361 => x"75", + 4362 => x"3f", + 4363 => x"08", + 4364 => x"ec", + 4365 => x"38", + 4366 => x"06", + 4367 => x"78", + 4368 => x"54", + 4369 => x"77", + 4370 => x"33", + 4371 => x"71", + 4372 => x"51", + 4373 => x"34", + 4374 => x"76", + 4375 => x"17", + 4376 => x"75", + 4377 => x"3f", + 4378 => x"08", + 4379 => x"ec", + 4380 => x"38", + 4381 => x"ff", + 4382 => x"10", + 4383 => x"76", + 4384 => x"51", + 4385 => x"be", + 4386 => x"2a", + 4387 => x"05", + 4388 => x"f9", + 4389 => x"85", + 4390 => x"82", + 4391 => x"ab", + 4392 => x"0a", + 4393 => x"2b", + 4394 => x"70", + 4395 => x"70", + 4396 => x"54", + 4397 => x"82", + 4398 => x"8f", + 4399 => x"07", + 4400 => x"f6", + 4401 => x"0b", + 4402 => x"78", + 4403 => x"0c", + 4404 => x"04", + 4405 => x"7a", + 4406 => x"08", + 4407 => x"59", + 4408 => x"a4", + 4409 => x"17", + 4410 => x"38", + 4411 => x"aa", + 4412 => x"73", + 4413 => x"fd", + 4414 => x"85", + 4415 => x"82", + 4416 => x"80", + 4417 => x"39", + 4418 => x"eb", + 4419 => x"80", + 4420 => x"85", + 4421 => x"80", + 4422 => x"52", + 4423 => x"84", + 4424 => x"ec", + 4425 => x"85", + 4426 => x"2e", + 4427 => x"82", + 4428 => x"81", + 4429 => x"82", + 4430 => x"ff", + 4431 => x"80", + 4432 => x"75", + 4433 => x"3f", + 4434 => x"08", + 4435 => x"16", + 4436 => x"90", + 4437 => x"55", + 4438 => x"27", + 4439 => x"15", + 4440 => x"84", + 4441 => x"07", + 4442 => x"17", + 4443 => x"76", + 4444 => x"a6", + 4445 => x"73", + 4446 => x"0c", + 4447 => x"04", + 4448 => x"7c", + 4449 => x"59", + 4450 => x"95", + 4451 => x"08", + 4452 => x"2e", + 4453 => x"17", + 4454 => x"b2", + 4455 => x"ae", + 4456 => x"7a", + 4457 => x"3f", + 4458 => x"82", + 4459 => x"27", + 4460 => x"82", + 4461 => x"55", + 4462 => x"08", + 4463 => x"d8", + 4464 => x"08", + 4465 => x"08", + 4466 => x"38", + 4467 => x"17", + 4468 => x"54", + 4469 => x"82", + 4470 => x"7a", + 4471 => x"06", + 4472 => x"81", + 4473 => x"17", + 4474 => x"83", + 4475 => x"75", + 4476 => x"f9", + 4477 => x"59", + 4478 => x"08", + 4479 => x"81", + 4480 => x"82", + 4481 => x"59", + 4482 => x"08", + 4483 => x"81", + 4484 => x"07", + 4485 => x"7c", + 4486 => x"ec", + 4487 => x"51", + 4488 => x"81", + 4489 => x"85", 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x"39", + 4549 => x"55", + 4550 => x"ec", + 4551 => x"0d", + 4552 => x"0d", + 4553 => x"55", + 4554 => x"82", + 4555 => x"58", + 4556 => x"85", + 4557 => x"da", + 4558 => x"74", + 4559 => x"3f", + 4560 => x"08", + 4561 => x"08", + 4562 => x"59", + 4563 => x"77", + 4564 => x"70", + 4565 => x"bb", + 4566 => x"84", + 4567 => x"56", + 4568 => x"58", + 4569 => x"97", + 4570 => x"75", + 4571 => x"52", + 4572 => x"51", + 4573 => x"82", + 4574 => x"80", + 4575 => x"8a", + 4576 => x"32", + 4577 => x"05", + 4578 => x"70", + 4579 => x"51", + 4580 => x"82", + 4581 => x"8a", + 4582 => x"f8", + 4583 => x"7c", + 4584 => x"56", + 4585 => x"80", + 4586 => x"f1", + 4587 => x"06", + 4588 => x"e9", + 4589 => x"18", + 4590 => x"08", + 4591 => x"38", + 4592 => x"82", + 4593 => x"38", + 4594 => x"54", + 4595 => x"74", + 4596 => x"82", + 4597 => x"22", + 4598 => x"79", + 4599 => x"38", + 4600 => x"98", + 4601 => x"cd", + 4602 => x"22", + 4603 => x"54", + 4604 => x"26", + 4605 => x"52", + 4606 => x"a8", + 4607 => x"ec", + 4608 => x"85", + 4609 => x"2e", + 4610 => x"0b", + 4611 => x"08", + 4612 => x"98", + 4613 => x"85", + 4614 => x"85", + 4615 => x"bd", + 4616 => x"31", + 4617 => x"73", + 4618 => x"f4", + 4619 => x"85", + 4620 => x"18", + 4621 => x"18", + 4622 => x"08", + 4623 => x"72", + 4624 => x"38", + 4625 => x"58", + 4626 => x"89", + 4627 => x"18", + 4628 => x"ff", + 4629 => x"05", + 4630 => x"80", + 4631 => x"85", + 4632 => x"3d", + 4633 => x"3d", + 4634 => x"08", + 4635 => x"a0", + 4636 => x"54", + 4637 => x"77", + 4638 => x"80", + 4639 => x"0c", + 4640 => x"53", + 4641 => x"80", + 4642 => x"38", + 4643 => x"06", + 4644 => x"b5", + 4645 => x"98", + 4646 => x"14", + 4647 => x"92", + 4648 => x"2a", + 4649 => x"56", + 4650 => x"26", + 4651 => x"80", + 4652 => x"16", + 4653 => x"77", + 4654 => x"53", + 4655 => x"38", + 4656 => x"51", + 4657 => x"82", + 4658 => x"53", + 4659 => x"0b", + 4660 => x"08", + 4661 => x"38", + 4662 => x"85", + 4663 => x"2e", + 4664 => x"98", + 4665 => x"85", + 4666 => x"80", + 4667 => x"8a", + 4668 => x"15", + 4669 => x"80", + 4670 => x"14", + 4671 => x"51", + 4672 => x"82", + 4673 => x"53", + 4674 => x"85", + 4675 => x"2e", + 4676 => x"82", + 4677 => x"ec", + 4678 => x"ba", + 4679 => x"82", + 4680 => x"ff", + 4681 => x"82", + 4682 => x"52", + 4683 => x"f1", + 4684 => x"ec", + 4685 => x"72", + 4686 => x"72", + 4687 => x"f2", + 4688 => x"85", + 4689 => x"15", + 4690 => x"15", + 4691 => x"b4", + 4692 => x"0c", + 4693 => x"82", + 4694 => x"8a", + 4695 => x"f7", + 4696 => x"7d", + 4697 => x"5b", + 4698 => x"76", + 4699 => x"3f", + 4700 => x"08", + 4701 => x"ec", + 4702 => x"38", + 4703 => x"08", + 4704 => x"08", + 4705 => x"ef", + 4706 => x"85", + 4707 => x"82", + 4708 => x"80", + 4709 => x"85", + 4710 => x"18", + 4711 => x"51", + 4712 => x"81", + 4713 => x"81", + 4714 => x"81", + 4715 => x"ec", + 4716 => x"83", + 4717 => x"77", + 4718 => x"72", + 4719 => x"38", + 4720 => x"75", + 4721 => x"81", + 4722 => x"a5", + 4723 => x"ec", + 4724 => x"52", + 4725 => x"8e", + 4726 => x"ec", + 4727 => x"85", + 4728 => x"2e", + 4729 => x"73", + 4730 => x"81", + 4731 => x"87", + 4732 => x"85", + 4733 => x"3d", + 4734 => x"3d", + 4735 => x"11", + 4736 => x"dd", + 4737 => x"ec", + 4738 => x"ff", + 4739 => x"33", + 4740 => x"71", + 4741 => x"81", + 4742 => x"94", + 4743 => x"c1", + 4744 => x"ec", + 4745 => x"73", + 4746 => x"82", + 4747 => x"85", + 4748 => x"fc", + 4749 => x"79", + 4750 => x"ff", + 4751 => x"12", + 4752 => x"eb", + 4753 => x"70", + 4754 => x"72", + 4755 => x"81", + 4756 => x"73", + 4757 => x"94", + 4758 => x"c7", + 4759 => x"0d", + 4760 => x"0d", + 4761 => x"55", + 4762 => x"5a", + 4763 => x"08", + 4764 => x"8a", + 4765 => x"08", + 4766 => x"ee", + 4767 => x"85", + 4768 => x"82", + 4769 => x"80", + 4770 => x"15", + 4771 => x"55", + 4772 => x"38", + 4773 => x"e6", + 4774 => x"33", + 4775 => x"70", + 4776 => x"58", + 4777 => x"86", + 4778 => x"85", + 4779 => x"73", + 4780 => x"83", + 4781 => x"73", + 4782 => x"38", + 4783 => x"06", + 4784 => x"80", + 4785 => x"75", + 4786 => x"38", + 4787 => x"08", + 4788 => x"54", + 4789 => x"2e", + 4790 => x"83", + 4791 => x"73", + 4792 => x"38", + 4793 => x"51", + 4794 => x"82", + 4795 => x"58", + 4796 => x"08", + 4797 => x"15", + 4798 => x"38", + 4799 => x"0b", + 4800 => x"77", + 4801 => x"0c", + 4802 => x"04", + 4803 => x"77", + 4804 => x"54", + 4805 => x"51", + 4806 => x"82", + 4807 => x"55", + 4808 => x"08", + 4809 => x"14", + 4810 => x"51", + 4811 => x"82", + 4812 => x"55", + 4813 => x"08", + 4814 => x"53", + 4815 => x"08", + 4816 => x"08", + 4817 => x"3f", + 4818 => x"14", + 4819 => x"08", + 4820 => x"3f", + 4821 => x"17", + 4822 => x"85", + 4823 => x"3d", + 4824 => x"3d", + 4825 => x"08", + 4826 => x"54", + 4827 => x"53", + 4828 => x"82", + 4829 => x"8d", + 4830 => x"08", + 4831 => x"34", + 4832 => x"15", + 4833 => x"0d", + 4834 => x"0d", + 4835 => x"57", + 4836 => x"17", + 4837 => x"08", + 4838 => x"82", + 4839 => x"89", + 4840 => x"55", + 4841 => x"14", + 4842 => x"16", + 4843 => x"71", + 4844 => x"38", + 4845 => x"09", + 4846 => x"38", + 4847 => x"73", + 4848 => x"81", + 4849 => x"ae", + 4850 => x"05", + 4851 => x"15", + 4852 => x"70", + 4853 => x"34", + 4854 => x"8a", + 4855 => x"38", + 4856 => x"05", + 4857 => x"81", + 4858 => x"17", + 4859 => x"12", + 4860 => x"34", + 4861 => x"9c", + 4862 => x"e7", + 4863 => x"85", + 4864 => x"0c", + 4865 => x"e7", + 4866 => x"85", + 4867 => x"17", + 4868 => x"51", + 4869 => x"82", + 4870 => x"84", + 4871 => x"3d", + 4872 => x"3d", + 4873 => x"08", + 4874 => x"61", + 4875 => x"55", + 4876 => x"2e", + 4877 => x"55", + 4878 => x"2e", + 4879 => x"80", + 4880 => x"94", + 4881 => x"1c", + 4882 => x"81", + 4883 => x"61", + 4884 => x"56", + 4885 => x"2e", + 4886 => x"83", + 4887 => x"73", + 4888 => x"70", + 4889 => x"70", + 4890 => x"07", + 4891 => x"73", + 4892 => x"88", + 4893 => x"70", + 4894 => x"73", + 4895 => x"38", + 4896 => x"ab", + 4897 => x"52", + 4898 => x"8f", + 4899 => x"ec", + 4900 => x"a6", + 4901 => x"61", + 4902 => x"5a", + 4903 => x"a0", + 4904 => x"e7", + 4905 => x"70", + 4906 => x"79", + 4907 => x"73", + 4908 => x"81", + 4909 => x"38", + 4910 => x"33", + 4911 => x"ae", + 4912 => x"81", + 4913 => x"2a", + 4914 => x"07", + 4915 => x"5a", + 4916 => x"8c", + 4917 => x"54", + 4918 => x"81", + 4919 => x"39", + 4920 => x"70", + 4921 => x"70", + 4922 => x"51", + 4923 => x"dc", + 4924 => x"73", + 4925 => x"38", + 4926 => x"82", + 4927 => x"19", + 4928 => x"54", + 4929 => x"82", + 4930 => x"54", + 4931 => x"78", + 4932 => x"81", + 4933 => x"54", + 4934 => x"82", + 4935 => x"af", + 4936 => x"81", + 4937 => x"dc", + 4938 => x"81", + 4939 => x"25", + 4940 => x"07", + 4941 => x"51", + 4942 => x"2e", + 4943 => x"39", + 4944 => x"80", + 4945 => x"33", + 4946 => x"73", + 4947 => x"81", + 4948 => x"81", + 4949 => x"dc", + 4950 => x"81", + 4951 => x"25", + 4952 => x"51", + 4953 => x"38", + 4954 => x"75", + 4955 => x"81", + 4956 => x"81", + 4957 => x"27", + 4958 => x"73", + 4959 => x"38", + 4960 => x"70", + 4961 => x"77", + 4962 => x"09", + 4963 => x"80", + 4964 => x"2a", + 4965 => x"56", + 4966 => x"81", + 4967 => x"57", + 4968 => x"eb", + 4969 => x"2b", + 4970 => x"25", + 4971 => x"80", + 4972 => x"ff", + 4973 => x"57", + 4974 => x"e6", + 4975 => x"85", + 4976 => x"2e", + 4977 => x"18", + 4978 => x"1a", + 4979 => x"56", + 4980 => x"3f", + 4981 => x"08", + 4982 => x"e8", + 4983 => x"54", + 4984 => x"80", + 4985 => x"17", + 4986 => x"34", + 4987 => x"11", + 4988 => x"74", + 4989 => x"75", + 4990 => x"d4", + 4991 => x"3f", + 4992 => x"08", + 4993 => x"9f", + 4994 => x"99", + 4995 => x"e0", + 4996 => x"ff", + 4997 => x"79", + 4998 => x"74", + 4999 => x"57", + 5000 => x"77", + 5001 => x"76", + 5002 => x"38", + 5003 => x"73", + 5004 => x"09", + 5005 => x"38", + 5006 => x"84", + 5007 => x"27", + 5008 => x"39", + 5009 => x"f2", + 5010 => x"80", + 5011 => x"54", + 5012 => x"34", + 5013 => x"58", + 5014 => x"f2", + 5015 => x"85", + 5016 => x"82", + 5017 => x"80", + 5018 => x"1b", + 5019 => x"51", + 5020 => x"82", + 5021 => x"56", + 5022 => x"08", + 5023 => x"9c", + 5024 => x"33", + 5025 => x"80", + 5026 => x"38", + 5027 => x"bf", + 5028 => x"86", + 5029 => x"15", + 5030 => x"2a", + 5031 => x"51", + 5032 => x"92", + 5033 => x"79", + 5034 => x"e4", + 5035 => x"85", + 5036 => x"2e", + 5037 => x"52", + 5038 => x"aa", + 5039 => x"39", + 5040 => x"33", + 5041 => x"80", + 5042 => x"74", + 5043 => x"81", + 5044 => x"38", + 5045 => x"70", + 5046 => x"82", + 5047 => x"54", + 5048 => x"96", + 5049 => x"06", + 5050 => x"2e", + 5051 => x"ff", + 5052 => x"1c", + 5053 => x"80", + 5054 => x"81", + 5055 => x"ba", + 5056 => x"b6", + 5057 => x"2a", + 5058 => x"51", + 5059 => x"38", + 5060 => x"70", + 5061 => x"81", + 5062 => x"55", + 5063 => x"e1", + 5064 => x"08", + 5065 => x"1d", + 5066 => x"7c", + 5067 => x"3f", + 5068 => x"08", + 5069 => x"fa", + 5070 => x"82", + 5071 => x"8f", + 5072 => x"f6", + 5073 => x"5b", + 5074 => x"70", + 5075 => x"59", + 5076 => x"73", + 5077 => x"cc", + 5078 => x"81", + 5079 => x"70", + 5080 => x"52", + 5081 => x"8d", + 5082 => x"38", + 5083 => x"09", + 5084 => x"ab", + 5085 => x"d0", + 5086 => x"ff", + 5087 => x"53", + 5088 => x"91", + 5089 => x"73", + 5090 => x"d0", + 5091 => x"71", + 5092 => x"fd", + 5093 => x"81", + 5094 => x"55", + 5095 => x"55", + 5096 => x"81", + 5097 => x"74", + 5098 => x"56", + 5099 => x"12", + 5100 => x"70", + 5101 => x"38", + 5102 => x"81", + 5103 => x"51", + 5104 => x"51", + 5105 => x"89", + 5106 => x"70", + 5107 => x"53", + 5108 => x"81", + 5109 => x"2a", + 5110 => x"72", + 5111 => x"06", + 5112 => x"ff", + 5113 => x"09", + 5114 => x"77", + 5115 => x"81", + 5116 => x"07", + 5117 => x"9f", + 5118 => x"54", + 5119 => x"80", + 5120 => x"81", + 5121 => x"59", + 5122 => x"25", + 5123 => x"8b", + 5124 => x"24", + 5125 => x"76", + 5126 => x"78", + 5127 => x"82", + 5128 => x"51", + 5129 => x"ec", + 5130 => x"0d", + 5131 => x"0d", + 5132 => x"0b", + 5133 => x"ff", + 5134 => x"0c", + 5135 => x"51", + 5136 => x"84", + 5137 => x"ec", + 5138 => x"38", + 5139 => x"51", + 5140 => x"82", + 5141 => x"83", + 5142 => x"54", + 5143 => x"82", + 5144 => x"09", + 5145 => x"e5", + 5146 => x"b4", + 5147 => x"57", + 5148 => x"2e", + 5149 => x"83", + 5150 => x"74", + 5151 => x"70", + 5152 => x"70", + 5153 => x"07", + 5154 => x"73", + 5155 => x"81", + 5156 => x"81", + 5157 => x"83", + 5158 => x"e4", + 5159 => x"16", + 5160 => x"3f", + 5161 => x"08", + 5162 => x"ec", + 5163 => x"9d", + 5164 => x"81", + 5165 => x"81", + 5166 => x"df", + 5167 => x"85", + 5168 => x"82", + 5169 => x"80", + 5170 => x"82", + 5171 => x"85", + 5172 => x"3d", + 5173 => x"3d", + 5174 => x"84", + 5175 => x"05", + 5176 => x"80", + 5177 => x"51", + 5178 => x"82", + 5179 => x"58", + 5180 => x"0b", + 5181 => x"08", + 5182 => x"38", + 5183 => x"08", + 5184 => x"9d", + 5185 => x"55", + 5186 => x"73", + 5187 => x"ee", + 5188 => x"0c", + 5189 => x"06", + 5190 => x"57", + 5191 => x"ae", + 5192 => x"33", + 5193 => x"3f", + 5194 => x"08", + 5195 => x"70", + 5196 => x"55", + 5197 => x"76", + 5198 => x"c0", + 5199 => x"2a", + 5200 => x"51", + 5201 => x"72", + 5202 => x"86", + 5203 => x"74", + 5204 => x"15", + 5205 => x"81", + 5206 => x"d7", + 5207 => x"85", + 5208 => x"ff", + 5209 => x"06", + 5210 => x"56", + 5211 => x"38", + 5212 => x"8f", + 5213 => x"2a", + 5214 => x"51", + 5215 => x"72", + 5216 => x"80", + 5217 => x"52", + 5218 => x"3f", + 5219 => x"08", + 5220 => x"57", + 5221 => x"09", + 5222 => x"e2", + 5223 => x"74", + 5224 => x"56", + 5225 => x"33", + 5226 => x"72", + 5227 => x"38", + 5228 => x"51", + 5229 => x"82", + 5230 => x"57", + 5231 => x"84", + 5232 => x"ff", + 5233 => x"56", + 5234 => x"25", + 5235 => x"0b", + 5236 => x"56", + 5237 => x"05", + 5238 => x"83", + 5239 => x"2e", + 5240 => x"52", + 5241 => x"c5", + 5242 => x"ec", + 5243 => x"06", + 5244 => x"27", + 5245 => x"16", + 5246 => x"27", + 5247 => x"56", + 5248 => x"84", + 5249 => x"56", + 5250 => x"84", + 5251 => x"14", + 5252 => x"3f", + 5253 => x"08", + 5254 => x"06", + 5255 => x"80", + 5256 => x"06", + 5257 => x"80", + 5258 => x"db", + 5259 => x"85", + 5260 => x"ff", + 5261 => x"77", + 5262 => x"d8", + 5263 => x"b8", + 5264 => x"ec", + 5265 => x"9c", + 5266 => x"c4", + 5267 => x"15", + 5268 => x"14", + 5269 => x"70", + 5270 => x"51", + 5271 => x"56", + 5272 => x"84", + 5273 => x"81", + 5274 => x"77", + 5275 => x"9a", + 5276 => x"ec", + 5277 => x"15", + 5278 => x"72", + 5279 => x"72", + 5280 => x"38", + 5281 => x"06", + 5282 => x"2e", + 5283 => x"56", + 5284 => x"80", + 5285 => x"da", + 5286 => x"85", + 5287 => x"82", + 5288 => x"88", + 5289 => x"8f", + 5290 => x"56", + 5291 => x"38", + 5292 => x"51", + 5293 => x"82", + 5294 => x"83", + 5295 => x"55", + 5296 => x"80", + 5297 => x"da", + 5298 => x"85", + 5299 => x"80", + 5300 => x"da", + 5301 => x"85", + 5302 => x"ff", + 5303 => x"8d", + 5304 => x"2e", + 5305 => x"88", + 5306 => x"1b", + 5307 => x"05", + 5308 => x"75", + 5309 => x"38", + 5310 => x"52", + 5311 => x"51", + 5312 => x"3f", + 5313 => x"08", + 5314 => x"ec", + 5315 => x"82", + 5316 => x"85", + 5317 => x"ff", + 5318 => x"26", + 5319 => x"57", + 5320 => x"f5", + 5321 => x"82", + 5322 => x"f5", + 5323 => x"81", + 5324 => x"8d", + 5325 => x"2e", + 5326 => x"82", + 5327 => x"16", + 5328 => x"16", + 5329 => x"70", + 5330 => x"7a", + 5331 => x"0c", + 5332 => x"83", + 5333 => x"06", + 5334 => x"de", + 5335 => x"81", + 5336 => x"ec", + 5337 => x"ff", + 5338 => x"56", + 5339 => x"38", + 5340 => x"38", + 5341 => x"51", + 5342 => x"82", + 5343 => x"a8", + 5344 => x"82", + 5345 => x"39", + 5346 => x"80", + 5347 => x"38", + 5348 => x"15", + 5349 => x"53", + 5350 => x"8e", + 5351 => x"75", + 5352 => x"76", + 5353 => x"51", + 5354 => x"ff", + 5355 => x"53", + 5356 => x"9c", + 5357 => x"81", + 5358 => x"0b", + 5359 => x"ff", + 5360 => x"0c", + 5361 => x"84", + 5362 => x"83", + 5363 => x"06", + 5364 => x"80", + 5365 => x"d8", + 5366 => x"85", + 5367 => x"ff", + 5368 => x"72", + 5369 => x"81", + 5370 => x"38", + 5371 => x"73", + 5372 => x"3f", + 5373 => x"08", + 5374 => x"82", + 5375 => x"84", + 5376 => x"b2", + 5377 => x"d9", + 5378 => x"ec", + 5379 => x"ff", + 5380 => x"82", + 5381 => x"09", + 5382 => x"c8", + 5383 => x"51", + 5384 => x"82", + 5385 => x"84", + 5386 => x"d2", + 5387 => x"06", + 5388 => x"98", + 5389 => x"c0", + 5390 => x"ec", + 5391 => x"85", + 5392 => x"09", + 5393 => x"38", + 5394 => x"51", + 5395 => x"82", + 5396 => x"90", + 5397 => x"a0", + 5398 => x"9c", + 5399 => x"ec", + 5400 => x"0c", + 5401 => x"82", + 5402 => x"81", + 5403 => x"82", + 5404 => x"72", + 5405 => x"80", + 5406 => x"0c", + 5407 => x"82", + 5408 => x"91", + 5409 => x"fb", + 5410 => x"54", + 5411 => x"80", + 5412 => x"73", + 5413 => x"80", + 5414 => x"72", + 5415 => x"80", + 5416 => x"86", + 5417 => x"15", + 5418 => x"71", + 5419 => x"81", + 5420 => x"81", + 5421 => x"d0", + 5422 => x"85", + 5423 => x"06", + 5424 => x"38", + 5425 => x"54", + 5426 => x"80", + 5427 => x"71", + 5428 => x"82", + 5429 => x"87", + 5430 => x"fa", + 5431 => x"ab", + 5432 => x"58", + 5433 => x"05", + 5434 => x"d7", + 5435 => x"80", + 5436 => x"ec", + 5437 => x"38", + 5438 => x"08", + 5439 => x"9d", + 5440 => x"08", + 5441 => x"80", + 5442 => x"80", + 5443 => x"54", + 5444 => x"84", + 5445 => x"34", + 5446 => x"75", + 5447 => x"2e", + 5448 => x"53", + 5449 => x"53", + 5450 => x"f7", + 5451 => x"85", + 5452 => x"73", + 5453 => x"0c", + 5454 => x"04", + 5455 => x"67", + 5456 => x"80", + 5457 => x"59", + 5458 => x"78", + 5459 => x"ca", + 5460 => x"06", + 5461 => x"3d", + 5462 => x"99", + 5463 => x"52", + 5464 => x"3f", + 5465 => x"08", + 5466 => x"ec", + 5467 => x"38", + 5468 => x"52", + 5469 => x"52", + 5470 => x"3f", + 5471 => x"08", + 5472 => x"ec", + 5473 => x"02", + 5474 => x"33", + 5475 => x"55", + 5476 => x"25", + 5477 => x"55", + 5478 => x"54", + 5479 => x"81", + 5480 => x"80", + 5481 => x"74", + 5482 => x"81", + 5483 => x"75", + 5484 => x"3f", + 5485 => x"08", + 5486 => x"02", + 5487 => x"91", + 5488 => x"81", + 5489 => x"82", + 5490 => x"06", + 5491 => x"80", + 5492 => x"88", + 5493 => x"39", + 5494 => x"58", + 5495 => x"38", + 5496 => x"70", + 5497 => x"54", + 5498 => x"81", + 5499 => x"52", + 5500 => x"86", + 5501 => x"ec", + 5502 => x"88", + 5503 => x"62", + 5504 => x"d4", + 5505 => x"54", + 5506 => x"15", + 5507 => x"62", + 5508 => x"e8", + 5509 => x"52", + 5510 => x"51", + 5511 => x"7a", + 5512 => x"83", + 5513 => x"80", + 5514 => x"38", + 5515 => x"08", + 5516 => x"53", + 5517 => x"3d", + 5518 => x"dd", + 5519 => x"85", + 5520 => x"82", + 5521 => x"82", + 5522 => x"39", + 5523 => x"38", + 5524 => x"33", + 5525 => x"70", + 5526 => x"55", + 5527 => x"2e", + 5528 => x"55", + 5529 => x"77", + 5530 => x"81", + 5531 => x"73", + 5532 => x"38", + 5533 => x"54", + 5534 => x"a0", + 5535 => x"82", + 5536 => x"52", + 5537 => x"f5", + 5538 => x"ec", + 5539 => x"18", + 5540 => x"55", + 5541 => x"ec", + 5542 => x"38", + 5543 => x"70", + 5544 => x"54", + 5545 => x"86", + 5546 => x"c0", + 5547 => x"b0", + 5548 => x"1b", + 5549 => x"1b", + 5550 => x"70", + 5551 => x"ba", + 5552 => x"ec", + 5553 => x"ec", + 5554 => x"0c", + 5555 => x"52", + 5556 => x"3f", + 5557 => x"08", + 5558 => x"08", + 5559 => x"77", + 5560 => x"86", + 5561 => x"1a", + 5562 => x"1a", + 5563 => x"91", + 5564 => x"0b", + 5565 => x"80", + 5566 => x"0c", + 5567 => x"70", + 5568 => x"54", + 5569 => x"81", + 5570 => x"85", + 5571 => x"2e", + 5572 => x"82", + 5573 => x"94", + 5574 => x"17", + 5575 => x"2b", + 5576 => x"57", + 5577 => x"52", + 5578 => x"f8", + 5579 => x"ec", + 5580 => x"85", + 5581 => x"26", + 5582 => x"55", + 5583 => x"08", + 5584 => x"81", + 5585 => x"79", + 5586 => x"31", + 5587 => x"81", + 5588 => x"07", + 5589 => x"54", + 5590 => x"8a", + 5591 => x"75", + 5592 => x"73", + 5593 => x"98", + 5594 => x"a9", + 5595 => x"ff", + 5596 => x"80", + 5597 => x"76", + 5598 => x"d5", + 5599 => x"85", + 5600 => x"38", + 5601 => x"39", + 5602 => x"82", + 5603 => x"05", + 5604 => x"84", + 5605 => x"0c", + 5606 => x"82", + 5607 => x"97", + 5608 => x"f2", + 5609 => x"63", + 5610 => x"40", + 5611 => x"7e", + 5612 => x"fc", + 5613 => x"51", + 5614 => x"82", + 5615 => x"55", + 5616 => x"08", + 5617 => x"19", + 5618 => x"80", + 5619 => x"74", + 5620 => x"39", + 5621 => x"81", + 5622 => x"56", + 5623 => x"82", + 5624 => x"39", + 5625 => x"1a", + 5626 => x"82", + 5627 => x"0b", + 5628 => x"81", + 5629 => x"39", + 5630 => x"94", + 5631 => x"55", + 5632 => x"83", + 5633 => x"7b", + 5634 => x"89", + 5635 => x"08", + 5636 => x"06", + 5637 => x"81", + 5638 => x"8a", + 5639 => x"05", + 5640 => x"06", + 5641 => x"a8", + 5642 => x"38", + 5643 => x"55", + 5644 => x"19", + 5645 => x"51", + 5646 => x"82", + 5647 => x"55", + 5648 => x"ff", + 5649 => x"ff", + 5650 => x"38", + 5651 => x"0c", + 5652 => x"52", + 5653 => x"9b", + 5654 => x"ec", + 5655 => x"ff", + 5656 => x"85", + 5657 => x"7c", + 5658 => x"57", + 5659 => x"80", + 5660 => x"1a", + 5661 => x"22", + 5662 => x"75", + 5663 => x"38", + 5664 => x"58", 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x"98", + 5724 => x"91", + 5725 => x"56", + 5726 => x"94", + 5727 => x"11", + 5728 => x"76", + 5729 => x"75", + 5730 => x"80", + 5731 => x"38", + 5732 => x"70", + 5733 => x"56", + 5734 => x"fd", + 5735 => x"11", + 5736 => x"77", + 5737 => x"5c", + 5738 => x"38", + 5739 => x"88", + 5740 => x"74", + 5741 => x"52", + 5742 => x"18", + 5743 => x"51", + 5744 => x"82", + 5745 => x"55", + 5746 => x"08", + 5747 => x"ab", + 5748 => x"2e", + 5749 => x"74", + 5750 => x"95", + 5751 => x"19", + 5752 => x"08", + 5753 => x"88", + 5754 => x"55", + 5755 => x"9c", + 5756 => x"09", + 5757 => x"38", + 5758 => x"91", + 5759 => x"ec", + 5760 => x"38", + 5761 => x"52", + 5762 => x"e7", + 5763 => x"ec", + 5764 => x"fe", + 5765 => x"85", + 5766 => x"7c", + 5767 => x"57", + 5768 => x"80", + 5769 => x"1b", + 5770 => x"22", + 5771 => x"75", + 5772 => x"38", + 5773 => x"59", + 5774 => x"53", + 5775 => x"1a", + 5776 => x"8e", + 5777 => x"ec", + 5778 => x"38", + 5779 => x"08", + 5780 => x"56", + 5781 => x"9b", + 5782 => x"53", + 5783 => x"77", + 5784 => x"7d", + 5785 => x"16", + 5786 => x"3f", + 5787 => x"0b", + 5788 => x"78", + 5789 => x"80", + 5790 => x"18", + 5791 => x"08", + 5792 => x"7e", + 5793 => x"3f", + 5794 => x"08", + 5795 => x"7e", + 5796 => x"0c", + 5797 => x"19", + 5798 => x"08", + 5799 => x"84", + 5800 => x"57", + 5801 => x"27", + 5802 => x"56", + 5803 => x"52", + 5804 => x"c9", + 5805 => x"ec", + 5806 => x"38", + 5807 => x"52", + 5808 => x"83", + 5809 => x"b4", + 5810 => x"a4", + 5811 => x"81", + 5812 => x"34", + 5813 => x"7e", + 5814 => x"0c", + 5815 => x"1a", + 5816 => x"94", + 5817 => x"1b", + 5818 => x"5e", + 5819 => x"27", + 5820 => x"55", + 5821 => x"0c", + 5822 => x"90", + 5823 => x"c0", + 5824 => x"90", + 5825 => x"56", + 5826 => x"ec", + 5827 => x"0d", + 5828 => x"0d", + 5829 => x"fc", + 5830 => x"52", + 5831 => x"3f", + 5832 => x"08", + 5833 => x"ec", + 5834 => x"38", + 5835 => x"70", + 5836 => x"81", + 5837 => x"55", + 5838 => x"80", + 5839 => x"16", + 5840 => x"51", + 5841 => x"82", + 5842 => x"57", + 5843 => x"08", + 5844 => x"a4", + 5845 => x"11", + 5846 => x"55", + 5847 => x"16", + 5848 => x"08", + 5849 => x"75", + 5850 => x"c7", + 5851 => x"08", + 5852 => x"51", + 5853 => x"82", + 5854 => x"52", + 5855 => x"c9", + 5856 => x"52", + 5857 => x"c9", + 5858 => x"54", + 5859 => x"15", + 5860 => x"cc", + 5861 => x"85", + 5862 => x"17", + 5863 => x"06", + 5864 => x"90", + 5865 => x"82", + 5866 => x"8a", + 5867 => x"fc", + 5868 => x"70", + 5869 => x"d9", + 5870 => x"ec", + 5871 => x"85", + 5872 => x"38", + 5873 => x"05", + 5874 => x"f1", + 5875 => x"85", + 5876 => x"82", + 5877 => x"87", + 5878 => x"ec", + 5879 => x"72", + 5880 => x"0c", + 5881 => x"04", + 5882 => x"84", + 5883 => x"d3", + 5884 => x"80", + 5885 => x"ec", + 5886 => x"38", + 5887 => x"08", + 5888 => x"34", + 5889 => x"82", + 5890 => x"83", + 5891 => x"ef", + 5892 => x"53", + 5893 => x"05", + 5894 => x"51", + 5895 => x"82", + 5896 => x"55", + 5897 => x"08", + 5898 => x"76", + 5899 => x"93", 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x"08", + 5959 => x"ec", + 5960 => x"69", + 5961 => x"d9", + 5962 => x"82", + 5963 => x"2e", + 5964 => x"52", + 5965 => x"ae", + 5966 => x"ec", + 5967 => x"85", + 5968 => x"2e", + 5969 => x"84", + 5970 => x"06", + 5971 => x"57", + 5972 => x"76", + 5973 => x"9e", + 5974 => x"05", + 5975 => x"dc", + 5976 => x"90", + 5977 => x"81", + 5978 => x"56", + 5979 => x"80", + 5980 => x"02", + 5981 => x"81", + 5982 => x"70", + 5983 => x"56", + 5984 => x"81", + 5985 => x"78", + 5986 => x"38", + 5987 => x"99", + 5988 => x"81", + 5989 => x"18", + 5990 => x"18", + 5991 => x"58", + 5992 => x"33", + 5993 => x"ee", + 5994 => x"6f", + 5995 => x"af", + 5996 => x"8d", + 5997 => x"2e", + 5998 => x"8a", + 5999 => x"6f", + 6000 => x"af", + 6001 => x"0b", + 6002 => x"33", + 6003 => x"81", + 6004 => x"08", + 6005 => x"5c", + 6006 => x"73", + 6007 => x"38", + 6008 => x"1a", + 6009 => x"55", + 6010 => x"38", + 6011 => x"73", + 6012 => x"38", + 6013 => x"76", + 6014 => x"74", + 6015 => x"33", + 6016 => x"05", + 6017 => x"15", + 6018 => x"ba", + 6019 => x"05", + 6020 => x"ff", + 6021 => x"06", + 6022 => x"57", + 6023 => x"18", + 6024 => x"54", + 6025 => x"70", + 6026 => x"34", + 6027 => x"ee", + 6028 => x"34", + 6029 => x"ec", + 6030 => x"0d", + 6031 => x"0d", + 6032 => x"3d", + 6033 => x"71", + 6034 => x"ec", + 6035 => x"85", + 6036 => x"82", + 6037 => x"82", + 6038 => x"15", + 6039 => x"82", + 6040 => x"15", + 6041 => x"76", + 6042 => x"90", + 6043 => x"81", + 6044 => x"06", + 6045 => x"72", + 6046 => x"56", + 6047 => x"54", + 6048 => x"17", + 6049 => x"78", + 6050 => x"38", + 6051 => x"22", + 6052 => x"59", + 6053 => x"78", + 6054 => x"76", + 6055 => x"51", + 6056 => x"3f", + 6057 => x"08", + 6058 => x"54", + 6059 => x"53", + 6060 => x"3f", + 6061 => x"08", + 6062 => x"38", + 6063 => x"05", + 6064 => x"70", + 6065 => x"77", + 6066 => x"18", + 6067 => x"51", + 6068 => x"88", + 6069 => x"73", + 6070 => x"52", + 6071 => x"a0", + 6072 => x"ec", + 6073 => x"85", + 6074 => x"2e", + 6075 => x"82", + 6076 => x"ff", + 6077 => x"38", + 6078 => x"08", + 6079 => x"73", + 6080 => x"73", + 6081 => x"9c", + 6082 => x"27", + 6083 => x"75", + 6084 => x"16", + 6085 => x"17", + 6086 => x"33", + 6087 => x"70", + 6088 => x"55", + 6089 => x"80", + 6090 => x"73", + 6091 => x"cc", + 6092 => x"85", + 6093 => x"82", + 6094 => x"94", + 6095 => x"ec", + 6096 => x"39", + 6097 => x"51", + 6098 => x"82", + 6099 => x"54", + 6100 => x"be", + 6101 => x"27", + 6102 => x"53", + 6103 => x"08", + 6104 => x"73", + 6105 => x"ff", + 6106 => x"15", + 6107 => x"16", + 6108 => x"ff", + 6109 => x"80", + 6110 => x"73", + 6111 => x"c5", + 6112 => x"85", + 6113 => x"38", + 6114 => x"16", + 6115 => x"80", + 6116 => x"0b", + 6117 => x"81", + 6118 => x"75", + 6119 => x"85", + 6120 => x"58", + 6121 => x"54", + 6122 => x"74", + 6123 => x"73", + 6124 => x"90", + 6125 => x"c0", + 6126 => x"90", + 6127 => x"83", + 6128 => x"72", + 6129 => x"38", + 6130 => x"08", + 6131 => x"77", + 6132 => x"80", + 6133 => x"85", + 6134 => x"3d", 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x"85", + 6194 => x"80", + 6195 => x"85", + 6196 => x"73", + 6197 => x"3f", + 6198 => x"08", + 6199 => x"ec", + 6200 => x"09", + 6201 => x"38", + 6202 => x"39", + 6203 => x"08", + 6204 => x"52", + 6205 => x"91", + 6206 => x"73", + 6207 => x"3f", + 6208 => x"08", + 6209 => x"09", + 6210 => x"72", + 6211 => x"70", + 6212 => x"08", + 6213 => x"54", + 6214 => x"85", + 6215 => x"3d", + 6216 => x"3d", + 6217 => x"80", + 6218 => x"70", + 6219 => x"52", + 6220 => x"3f", + 6221 => x"08", + 6222 => x"ec", + 6223 => x"64", + 6224 => x"d5", + 6225 => x"85", + 6226 => x"82", + 6227 => x"a0", + 6228 => x"cb", + 6229 => x"98", + 6230 => x"73", + 6231 => x"38", + 6232 => x"39", + 6233 => x"88", + 6234 => x"75", + 6235 => x"3f", + 6236 => x"ec", + 6237 => x"0d", + 6238 => x"0d", + 6239 => x"5c", + 6240 => x"3d", + 6241 => x"93", + 6242 => x"ca", + 6243 => x"ec", + 6244 => x"85", + 6245 => x"87", + 6246 => x"0c", + 6247 => x"11", + 6248 => x"90", + 6249 => x"56", + 6250 => x"74", + 6251 => x"75", + 6252 => x"eb", + 6253 => x"81", + 6254 => x"5b", + 6255 => x"82", + 6256 => x"75", + 6257 => x"73", + 6258 => x"81", + 6259 => x"38", + 6260 => x"57", + 6261 => x"3d", + 6262 => x"c1", + 6263 => x"85", + 6264 => x"2e", + 6265 => x"85", + 6266 => x"2e", + 6267 => x"85", + 6268 => x"81", + 6269 => x"85", + 6270 => x"80", + 6271 => x"81", + 6272 => x"59", + 6273 => x"14", + 6274 => x"c8", + 6275 => x"39", + 6276 => x"82", + 6277 => x"57", + 6278 => x"38", + 6279 => x"18", + 6280 => x"ff", + 6281 => x"82", + 6282 => x"5b", + 6283 => x"08", + 6284 => x"7c", + 6285 => x"12", + 6286 => x"52", + 6287 => x"82", + 6288 => x"06", + 6289 => x"14", + 6290 => x"95", + 6291 => x"ec", + 6292 => x"ff", + 6293 => x"81", + 6294 => x"25", + 6295 => x"59", + 6296 => x"9d", + 6297 => x"51", + 6298 => x"3f", + 6299 => x"08", + 6300 => x"70", + 6301 => x"70", + 6302 => x"84", + 6303 => x"51", + 6304 => x"ff", + 6305 => x"56", + 6306 => x"38", + 6307 => x"7c", + 6308 => x"0c", + 6309 => x"81", + 6310 => x"74", + 6311 => x"7a", + 6312 => x"0c", + 6313 => x"04", + 6314 => x"79", + 6315 => x"05", + 6316 => x"57", + 6317 => x"82", + 6318 => x"56", + 6319 => x"08", + 6320 => x"91", + 6321 => x"75", + 6322 => x"90", + 6323 => x"81", + 6324 => x"06", + 6325 => x"87", + 6326 => x"2e", + 6327 => x"94", + 6328 => x"73", + 6329 => x"27", + 6330 => x"73", + 6331 => x"85", + 6332 => x"88", + 6333 => x"76", + 6334 => x"3f", + 6335 => x"08", + 6336 => x"0c", + 6337 => x"39", + 6338 => x"52", + 6339 => x"bf", + 6340 => x"85", + 6341 => x"2e", + 6342 => x"83", + 6343 => x"82", + 6344 => x"81", + 6345 => x"06", + 6346 => x"56", + 6347 => x"a0", + 6348 => x"82", + 6349 => x"98", + 6350 => x"94", + 6351 => x"08", + 6352 => x"ec", + 6353 => x"51", + 6354 => x"82", + 6355 => x"56", + 6356 => x"8c", + 6357 => x"17", + 6358 => x"07", + 6359 => x"18", + 6360 => x"2e", + 6361 => x"91", + 6362 => x"55", + 6363 => x"ec", + 6364 => x"0d", + 6365 => x"0d", + 6366 => x"3d", + 6367 => x"52", + 6368 => x"da", + 6369 => x"85", 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x"e0", + 6429 => x"ec", + 6430 => x"8c", + 6431 => x"ff", + 6432 => x"82", + 6433 => x"55", + 6434 => x"ec", + 6435 => x"0d", + 6436 => x"0d", + 6437 => x"3d", + 6438 => x"9a", + 6439 => x"b6", + 6440 => x"ec", + 6441 => x"85", + 6442 => x"b0", + 6443 => x"69", + 6444 => x"70", + 6445 => x"ea", + 6446 => x"ec", + 6447 => x"85", + 6448 => x"38", + 6449 => x"94", + 6450 => x"ec", + 6451 => x"09", + 6452 => x"88", + 6453 => x"df", + 6454 => x"85", + 6455 => x"51", + 6456 => x"74", + 6457 => x"78", + 6458 => x"8a", + 6459 => x"57", + 6460 => x"82", + 6461 => x"75", + 6462 => x"85", + 6463 => x"38", + 6464 => x"85", + 6465 => x"2e", + 6466 => x"83", + 6467 => x"82", + 6468 => x"ff", + 6469 => x"06", + 6470 => x"54", + 6471 => x"73", + 6472 => x"82", + 6473 => x"52", + 6474 => x"f5", + 6475 => x"ec", + 6476 => x"85", + 6477 => x"9a", + 6478 => x"a0", + 6479 => x"51", + 6480 => x"3f", + 6481 => x"0b", + 6482 => x"78", + 6483 => x"bf", + 6484 => x"88", + 6485 => x"80", + 6486 => x"ff", + 6487 => x"75", + 6488 => x"11", + 6489 => x"cb", + 6490 => x"78", + 6491 => x"80", + 6492 => x"ff", + 6493 => x"78", + 6494 => x"80", + 6495 => x"7f", + 6496 => x"d4", + 6497 => x"c9", + 6498 => x"54", + 6499 => x"15", + 6500 => x"ca", + 6501 => x"85", + 6502 => x"82", + 6503 => x"b2", + 6504 => x"b2", + 6505 => x"96", + 6506 => x"b5", + 6507 => x"53", + 6508 => x"51", + 6509 => x"64", + 6510 => x"8b", + 6511 => x"54", + 6512 => x"15", + 6513 => x"ff", + 6514 => x"82", + 6515 => x"54", + 6516 => x"53", + 6517 => x"51", + 6518 => x"3f", + 6519 => x"ec", + 6520 => x"0d", + 6521 => x"0d", + 6522 => x"05", + 6523 => x"3f", + 6524 => x"3d", + 6525 => x"52", + 6526 => x"d5", + 6527 => x"85", + 6528 => x"82", + 6529 => x"82", + 6530 => x"4d", + 6531 => x"52", + 6532 => x"52", + 6533 => x"3f", + 6534 => x"08", + 6535 => x"ec", + 6536 => x"38", + 6537 => x"05", + 6538 => x"06", + 6539 => x"73", + 6540 => x"a0", + 6541 => x"08", + 6542 => x"ff", + 6543 => x"ff", + 6544 => x"ac", + 6545 => x"92", + 6546 => x"54", + 6547 => x"3f", + 6548 => x"52", + 6549 => x"ca", + 6550 => x"ec", + 6551 => x"85", + 6552 => x"38", + 6553 => x"09", + 6554 => x"38", + 6555 => x"08", + 6556 => x"88", + 6557 => x"39", + 6558 => x"08", + 6559 => x"81", + 6560 => x"38", + 6561 => x"84", + 6562 => x"ec", + 6563 => x"85", + 6564 => x"c8", + 6565 => x"93", + 6566 => x"ff", + 6567 => x"8d", + 6568 => x"b3", + 6569 => x"af", + 6570 => x"17", + 6571 => x"33", + 6572 => x"70", + 6573 => x"55", + 6574 => x"38", + 6575 => x"54", + 6576 => x"34", + 6577 => x"0b", + 6578 => x"8b", + 6579 => x"84", + 6580 => x"06", + 6581 => x"73", + 6582 => x"e5", + 6583 => x"2e", + 6584 => x"75", + 6585 => x"c6", + 6586 => x"85", + 6587 => x"78", + 6588 => x"ff", + 6589 => x"82", + 6590 => x"80", + 6591 => x"38", + 6592 => x"08", + 6593 => x"ff", + 6594 => x"82", + 6595 => x"79", + 6596 => x"58", + 6597 => x"85", + 6598 => x"c0", + 6599 => x"33", + 6600 => x"2e", + 6601 => x"99", + 6602 => x"75", + 6603 => x"c6", + 6604 => x"54", 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x"33", + 6664 => x"54", + 6665 => x"a6", + 6666 => x"22", + 6667 => x"71", + 6668 => x"53", + 6669 => x"51", + 6670 => x"3f", + 6671 => x"0b", + 6672 => x"76", + 6673 => x"fc", + 6674 => x"ec", + 6675 => x"82", + 6676 => x"93", + 6677 => x"ea", + 6678 => x"6b", + 6679 => x"53", + 6680 => x"05", + 6681 => x"51", + 6682 => x"82", + 6683 => x"82", + 6684 => x"09", + 6685 => x"82", + 6686 => x"07", + 6687 => x"55", + 6688 => x"2e", + 6689 => x"81", + 6690 => x"55", + 6691 => x"2e", + 6692 => x"7b", + 6693 => x"80", + 6694 => x"70", + 6695 => x"bd", + 6696 => x"85", + 6697 => x"82", + 6698 => x"80", + 6699 => x"52", + 6700 => x"ad", + 6701 => x"ec", + 6702 => x"85", + 6703 => x"38", + 6704 => x"08", + 6705 => x"08", + 6706 => x"56", + 6707 => x"19", + 6708 => x"59", + 6709 => x"74", + 6710 => x"56", + 6711 => x"ec", + 6712 => x"75", + 6713 => x"74", + 6714 => x"2e", + 6715 => x"16", + 6716 => x"33", + 6717 => x"73", + 6718 => x"38", + 6719 => x"84", + 6720 => x"06", + 6721 => x"7a", + 6722 => x"76", + 6723 => x"70", + 6724 => x"25", + 6725 => x"80", + 6726 => x"38", + 6727 => x"bc", + 6728 => x"11", + 6729 => x"ff", + 6730 => x"82", + 6731 => x"57", + 6732 => x"08", + 6733 => x"70", + 6734 => x"80", + 6735 => x"83", + 6736 => x"80", + 6737 => x"84", + 6738 => x"a7", + 6739 => x"b4", + 6740 => x"ad", + 6741 => x"85", + 6742 => x"0c", + 6743 => x"ec", + 6744 => x"0d", + 6745 => x"0d", + 6746 => x"3d", + 6747 => x"52", + 6748 => x"ce", + 6749 => x"85", + 6750 => x"85", + 6751 => x"54", + 6752 => x"08", + 6753 => x"8b", + 6754 => x"8b", + 6755 => x"59", + 6756 => x"3f", + 6757 => x"33", + 6758 => x"06", + 6759 => x"57", + 6760 => x"81", + 6761 => x"58", + 6762 => x"06", + 6763 => x"4e", + 6764 => x"ff", + 6765 => x"82", + 6766 => x"80", + 6767 => x"6c", + 6768 => x"53", + 6769 => x"ae", + 6770 => x"85", + 6771 => x"2e", + 6772 => x"88", + 6773 => x"6d", + 6774 => x"55", + 6775 => x"85", + 6776 => x"ff", + 6777 => x"83", + 6778 => x"51", + 6779 => x"26", + 6780 => x"15", + 6781 => x"ff", + 6782 => x"80", + 6783 => x"87", + 6784 => x"b4", + 6785 => x"74", + 6786 => x"38", + 6787 => x"80", + 6788 => x"ad", + 6789 => x"85", + 6790 => x"38", + 6791 => x"27", + 6792 => x"89", + 6793 => x"8b", + 6794 => x"27", + 6795 => x"55", + 6796 => x"81", + 6797 => x"8f", + 6798 => x"2a", + 6799 => x"70", + 6800 => x"34", + 6801 => x"74", + 6802 => x"05", + 6803 => x"17", + 6804 => x"70", + 6805 => x"52", + 6806 => x"73", + 6807 => x"c8", + 6808 => x"33", + 6809 => x"73", + 6810 => x"81", + 6811 => x"80", + 6812 => x"02", + 6813 => x"76", + 6814 => x"51", + 6815 => x"2e", + 6816 => x"87", + 6817 => x"57", + 6818 => x"79", + 6819 => x"80", + 6820 => x"70", + 6821 => x"ba", + 6822 => x"85", + 6823 => x"82", + 6824 => x"80", + 6825 => x"52", + 6826 => x"bf", + 6827 => x"85", + 6828 => x"82", + 6829 => x"8d", + 6830 => x"c4", + 6831 => x"e5", + 6832 => x"c6", + 6833 => x"ec", + 6834 => x"09", + 6835 => x"cc", + 6836 => x"76", + 6837 => x"c4", + 6838 => x"74", + 6839 => x"ff", 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7721 => x"00", + 7722 => x"62", + 7723 => x"67", + 7724 => x"6d", + 7725 => x"2e", + 7726 => x"00", + 7727 => x"6f", + 7728 => x"63", + 7729 => x"74", + 7730 => x"00", + 7731 => x"2e", + 7732 => x"00", + 7733 => x"00", + 7734 => x"6c", + 7735 => x"74", + 7736 => x"6e", + 7737 => x"61", + 7738 => x"65", + 7739 => x"20", + 7740 => x"64", + 7741 => x"20", + 7742 => x"61", + 7743 => x"69", + 7744 => x"20", + 7745 => x"75", + 7746 => x"79", + 7747 => x"00", + 7748 => x"00", + 7749 => x"61", + 7750 => x"67", + 7751 => x"2e", + 7752 => x"00", + 7753 => x"79", + 7754 => x"2e", + 7755 => x"00", + 7756 => x"70", + 7757 => x"6e", + 7758 => x"2e", + 7759 => x"00", + 7760 => x"6c", + 7761 => x"30", + 7762 => x"2d", + 7763 => x"38", + 7764 => x"25", + 7765 => x"29", + 7766 => x"00", + 7767 => x"70", + 7768 => x"6d", + 7769 => x"0a", + 7770 => x"00", + 7771 => x"6d", + 7772 => x"74", + 7773 => x"00", + 7774 => x"58", + 7775 => x"32", + 7776 => x"00", + 7777 => x"0a", + 7778 => x"00", + 7779 => x"58", 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x"74", + 7839 => x"75", + 7840 => x"2e", + 7841 => x"00", + 7842 => x"25", + 7843 => x"64", + 7844 => x"3a", + 7845 => x"25", + 7846 => x"64", + 7847 => x"00", + 7848 => x"20", + 7849 => x"66", + 7850 => x"72", + 7851 => x"6f", + 7852 => x"00", + 7853 => x"72", + 7854 => x"53", + 7855 => x"63", + 7856 => x"69", + 7857 => x"00", + 7858 => x"65", + 7859 => x"65", + 7860 => x"6d", + 7861 => x"6d", + 7862 => x"65", + 7863 => x"00", + 7864 => x"20", + 7865 => x"53", + 7866 => x"4d", + 7867 => x"25", + 7868 => x"3a", + 7869 => x"58", + 7870 => x"00", + 7871 => x"20", + 7872 => x"41", + 7873 => x"20", + 7874 => x"25", + 7875 => x"3a", + 7876 => x"58", + 7877 => x"00", + 7878 => x"20", + 7879 => x"4e", + 7880 => x"41", + 7881 => x"25", + 7882 => x"3a", + 7883 => x"58", + 7884 => x"00", + 7885 => x"20", + 7886 => x"4d", + 7887 => x"20", + 7888 => x"25", + 7889 => x"3a", + 7890 => x"58", + 7891 => x"00", + 7892 => x"20", + 7893 => x"20", + 7894 => x"20", + 7895 => x"25", + 7896 => x"3a", + 7897 => x"58", + 7898 => x"00", + 7899 => x"20", + 7900 => x"43", + 7901 => x"20", + 7902 => x"44", + 7903 => x"63", + 7904 => x"3d", + 7905 => x"64", + 7906 => x"00", + 7907 => x"20", + 7908 => x"45", + 7909 => x"20", + 7910 => x"54", + 7911 => x"72", + 7912 => x"3d", + 7913 => x"64", + 7914 => x"00", + 7915 => x"20", + 7916 => x"52", + 7917 => x"52", + 7918 => x"43", + 7919 => x"6e", + 7920 => x"3d", + 7921 => x"64", + 7922 => x"00", + 7923 => x"20", + 7924 => x"48", + 7925 => x"45", + 7926 => x"53", + 7927 => x"00", + 7928 => x"20", + 7929 => x"49", + 7930 => x"00", + 7931 => x"20", + 7932 => x"54", + 7933 => x"00", + 7934 => x"20", + 7935 => x"0a", + 7936 => x"00", + 7937 => x"20", + 7938 => x"0a", + 7939 => x"00", + 7940 => x"72", + 7941 => x"65", + 7942 => x"00", + 7943 => x"20", + 7944 => x"20", + 7945 => x"65", + 7946 => x"65", + 7947 => x"72", + 7948 => x"64", + 7949 => x"73", + 7950 => x"25", + 7951 => x"0a", + 7952 => x"00", + 7953 => x"20", + 7954 => x"20", + 7955 => x"6f", + 7956 => x"53", + 7957 => x"74", + 7958 => x"64", + 7959 => x"73", + 7960 => x"25", + 7961 => x"0a", + 7962 => x"00", + 7963 => x"20", + 7964 => x"63", + 7965 => x"74", + 7966 => x"20", + 7967 => x"72", + 7968 => x"20", + 7969 => x"20", + 7970 => x"25", + 7971 => x"0a", + 7972 => x"00", + 7973 => x"63", + 7974 => x"00", + 7975 => x"20", + 7976 => x"20", + 7977 => x"20", + 7978 => x"20", + 7979 => x"20", + 7980 => x"20", + 7981 => x"20", + 7982 => x"25", + 7983 => x"0a", + 7984 => x"00", + 7985 => x"20", + 7986 => x"74", + 7987 => x"43", + 7988 => x"6b", + 7989 => x"65", + 7990 => x"20", + 7991 => x"20", + 7992 => x"25", + 7993 => x"30", + 7994 => x"48", + 7995 => x"00", + 7996 => x"20", + 7997 => x"41", + 7998 => x"6c", + 7999 => x"20", + 8000 => x"71", + 8001 => x"20", + 8002 => x"20", + 8003 => x"25", + 8004 => x"30", + 8005 => x"48", + 8006 => x"00", + 8007 => x"20", + 8008 => x"68", + 8009 => x"65", + 8010 => x"52", + 8011 => x"43", + 8012 => x"6b", + 8013 => x"65", + 8014 => x"25", + 8015 => x"30", + 8016 => x"48", + 8017 => x"00", + 8018 => x"6c", + 8019 => x"00", + 8020 => x"69", + 8021 => x"00", + 8022 => x"78", + 8023 => x"00", + 8024 => x"00", + 8025 => x"6d", + 8026 => x"00", + 8027 => x"6e", + 8028 => x"00", + 8029 => x"d0", + 8030 => x"00", + 8031 => x"02", + 8032 => x"cc", + 8033 => x"00", + 8034 => x"03", + 8035 => x"c8", + 8036 => x"00", + 8037 => x"04", + 8038 => x"c4", + 8039 => x"00", + 8040 => x"05", + 8041 => x"c0", + 8042 => x"00", + 8043 => x"06", + 8044 => x"bc", + 8045 => x"00", + 8046 => x"07", + 8047 => x"b8", + 8048 => x"00", + 8049 => x"01", + 8050 => x"b4", + 8051 => x"00", + 8052 => x"08", + 8053 => x"b0", + 8054 => x"00", + 8055 => x"0b", + 8056 => x"ac", + 8057 => x"00", + 8058 => x"09", + 8059 => x"a8", + 8060 => x"00", + 8061 => x"0a", + 8062 => x"a4", + 8063 => x"00", + 8064 => x"0d", + 8065 => x"a0", + 8066 => x"00", + 8067 => x"0c", + 8068 => x"9c", + 8069 => x"00", + 8070 => x"0e", + 8071 => x"98", + 8072 => x"00", + 8073 => x"0f", + 8074 => x"94", + 8075 => x"00", + 8076 => x"0f", + 8077 => x"90", + 8078 => x"00", + 8079 => x"10", + 8080 => x"8c", + 8081 => x"00", + 8082 => x"11", + 8083 => x"88", + 8084 => x"00", + 8085 => x"12", + 8086 => x"84", + 8087 => x"00", + 8088 => x"13", + 8089 => x"80", + 8090 => x"00", + 8091 => x"14", + 8092 => x"7c", + 8093 => x"00", + 8094 => x"15", + 8095 => x"00", + 8096 => x"00", + 8097 => x"00", + 8098 => x"00", + 8099 => x"7e", + 8100 => x"7e", + 8101 => x"7e", + 8102 => x"00", + 8103 => x"7e", + 8104 => x"7e", + 8105 => x"7e", + 8106 => x"00", + 8107 => x"00", + 8108 => x"00", + 8109 => x"00", + 8110 => x"00", + 8111 => x"00", + 8112 => x"00", + 8113 => x"00", + 8114 => x"00", + 8115 => x"00", + 8116 => x"00", + 8117 => x"74", + 8118 => x"00", + 8119 => x"74", + 8120 => x"00", + 8121 => x"00", + 8122 => x"64", + 8123 => x"73", + 8124 => x"00", + 8125 => x"6c", + 8126 => x"74", + 8127 => x"65", + 8128 => x"20", + 8129 => x"20", + 8130 => x"74", + 8131 => x"20", + 8132 => x"65", + 8133 => x"20", + 8134 => x"2e", + 8135 => x"00", + 8136 => x"6e", + 8137 => x"6f", + 8138 => x"2f", + 8139 => x"61", + 8140 => x"68", + 8141 => x"6f", + 8142 => x"66", + 8143 => x"2c", + 8144 => x"73", + 8145 => x"69", + 8146 => x"0a", + 8147 => x"00", + 8148 => x"00", + 8149 => x"2c", + 8150 => x"3d", + 8151 => x"5d", + 8152 => x"00", + 8153 => x"00", + 8154 => x"33", + 8155 => x"00", + 8156 => x"4d", + 8157 => x"53", + 8158 => x"00", + 8159 => x"4e", + 8160 => x"20", + 8161 => x"46", + 8162 => x"32", + 8163 => x"00", + 8164 => x"4e", + 8165 => x"20", + 8166 => x"46", + 8167 => x"20", + 8168 => x"00", + 8169 => x"50", + 8170 => x"00", + 8171 => x"00", + 8172 => x"00", + 8173 => x"41", + 8174 => x"80", + 8175 => x"49", + 8176 => x"8f", + 8177 => x"4f", + 8178 => x"55", + 8179 => x"9b", + 8180 => x"9f", + 8181 => x"55", + 8182 => x"a7", + 8183 => x"ab", + 8184 => x"af", + 8185 => x"b3", + 8186 => x"b7", + 8187 => x"bb", + 8188 => x"bf", + 8189 => x"c3", + 8190 => x"c7", + 8191 => x"cb", + 8192 => x"cf", + 8193 => x"d3", + 8194 => x"d7", + 8195 => x"db", + 8196 => x"df", + 8197 => x"e3", + 8198 => x"e7", + 8199 => x"eb", + 8200 => x"ef", + 8201 => x"f3", + 8202 => x"f7", + 8203 => x"fb", + 8204 => x"ff", + 8205 => x"3b", + 8206 => x"2f", + 8207 => x"3a", + 8208 => x"7c", + 8209 => x"00", + 8210 => x"04", + 8211 => x"40", + 8212 => x"00", + 8213 => x"00", + 8214 => x"02", + 8215 => x"08", + 8216 => x"20", + 8217 => x"00", + 8218 => x"00", + 8219 => x"c8", + 8220 => x"00", + 8221 => x"00", + 8222 => x"00", + 8223 => x"d0", + 8224 => x"00", + 8225 => x"00", + 8226 => x"00", + 8227 => x"d8", + 8228 => x"00", + 8229 => x"00", + 8230 => x"00", + 8231 => x"e0", + 8232 => x"00", + 8233 => x"00", + 8234 => x"00", + 8235 => x"e8", + 8236 => x"00", + 8237 => x"00", + 8238 => x"00", + 8239 => x"f0", + 8240 => x"00", + 8241 => x"00", + 8242 => x"00", + 8243 => x"f8", + 8244 => x"00", + 8245 => x"00", + 8246 => x"00", + 8247 => x"00", + 8248 => x"00", + 8249 => x"00", + 8250 => x"00", + 8251 => x"08", + 8252 => x"00", + 8253 => x"00", + 8254 => x"00", + 8255 => x"10", + 8256 => x"00", + 8257 => x"00", + 8258 => x"00", + 8259 => x"14", + 8260 => x"00", + 8261 => x"00", + 8262 => x"00", + 8263 => x"18", + 8264 => x"00", + 8265 => x"00", + 8266 => x"00", + 8267 => x"1c", + 8268 => x"00", + 8269 => x"00", + 8270 => x"00", + 8271 => x"20", + 8272 => x"00", + 8273 => x"00", + 8274 => x"00", + 8275 => x"24", + 8276 => x"00", + 8277 => x"00", + 8278 => x"00", + 8279 => x"28", + 8280 => x"00", + 8281 => x"00", + 8282 => x"00", + 8283 => x"2c", + 8284 => x"00", + 8285 => x"00", + 8286 => x"00", + 8287 => x"34", + 8288 => x"00", + 8289 => x"00", + 8290 => x"00", + 8291 => x"38", + 8292 => x"00", + 8293 => x"00", + 8294 => x"00", + 8295 => x"40", + 8296 => x"00", + 8297 => x"00", + 8298 => x"00", + 8299 => x"48", + 8300 => x"00", + 8301 => x"00", + 8302 => x"00", + 8303 => x"50", + 8304 => x"00", + 8305 => x"00", + 8306 => x"00", + 8307 => x"58", + 8308 => x"00", + 8309 => x"00", + 8310 => x"00", + 8311 => x"60", + 8312 => x"00", + 8313 => x"00", + 8314 => x"00", + 8315 => x"68", + 8316 => x"00", + 8317 => x"00", + 8318 => x"00", + 8319 => x"70", + 8320 => x"00", + 8321 => x"00", + 8322 => x"00", + 8323 => x"00", + 8324 => x"00", + 8325 => x"ff", + 8326 => x"00", + 8327 => x"ff", + 8328 => x"00", + 8329 => x"ff", + 8330 => x"00", + 8331 => x"00", + 8332 => x"00", + 8333 => x"ff", + 8334 => x"00", + 8335 => x"00", + 8336 => x"00", + 8337 => x"00", + 8338 => x"00", + 8339 => x"00", + 8340 => x"00", + 8341 => x"00", + 8342 => x"01", + 8343 => x"01", + 8344 => x"01", + 8345 => x"00", + 8346 => x"00", + 8347 => x"00", + 8348 => x"00", + 8349 => x"00", + 8350 => x"00", + 8351 => x"00", + 8352 => x"00", + 8353 => x"00", + 8354 => x"00", + 8355 => x"00", + 8356 => x"00", + 8357 => x"00", + 8358 => x"00", + 8359 => x"00", + 8360 => x"00", + 8361 => x"00", + 8362 => x"00", + 8363 => x"00", + 8364 => x"00", + 8365 => x"00", + 8366 => x"00", + 8367 => x"00", + 8368 => x"00", + 8369 => x"00", + 8370 => x"d4", + 8371 => x"00", + 8372 => x"dc", + 8373 => x"00", + 8374 => x"e4", + 8375 => x"00", + 8376 => x"00", + 8377 => x"00", + 8378 => x"00", + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + 0 => x"83", + 1 => x"0b", + 2 => x"9b", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"8c", + 9 => x"88", + 10 => x"90", + 11 => x"88", + 12 => x"00", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"06", + 17 => x"06", + 18 => x"82", + 19 => x"2a", + 20 => x"06", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"06", + 25 => x"ff", + 26 => x"09", + 27 => x"05", + 28 => x"09", + 29 => x"ff", + 30 => x"0b", + 31 => x"04", + 32 => x"81", + 33 => x"73", + 34 => x"09", + 35 => x"73", + 36 => x"81", + 37 => x"04", + 38 => x"00", + 39 => x"00", + 40 => x"24", + 41 => x"07", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"81", + 50 => x"05", + 51 => x"0a", + 52 => x"0a", + 53 => x"81", + 54 => x"53", + 55 => x"00", + 56 => x"26", + 57 => x"07", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"51", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"9f", + 89 => x"05", + 90 => x"92", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"2a", + 97 => x"06", + 98 => x"09", + 99 => x"ff", + 100 => x"53", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"53", + 105 => x"73", + 106 => x"81", + 107 => x"83", + 108 => x"07", + 109 => x"0c", + 110 => x"00", + 111 => x"00", + 112 => x"81", + 113 => x"09", + 114 => x"09", + 115 => x"06", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"81", + 121 => x"09", + 122 => x"09", + 123 => x"81", + 124 => x"04", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"81", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"09", + 137 => x"53", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"09", + 146 => x"51", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"06", + 153 => x"06", + 154 => x"83", + 155 => x"10", + 156 => x"06", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"06", + 161 => x"81", + 162 => x"83", + 163 => x"05", + 164 => x"0b", + 165 => x"04", + 166 => x"00", + 167 => x"00", + 168 => x"8c", + 169 => x"75", + 170 => x"0b", + 171 => x"50", + 172 => x"56", + 173 => x"0c", + 174 => x"04", + 175 => x"00", + 176 => x"8c", + 177 => x"75", + 178 => x"0b", + 179 => x"50", + 180 => x"56", + 181 => x"0c", + 182 => x"04", + 183 => x"00", + 184 => x"70", + 185 => x"06", + 186 => x"ff", + 187 => x"71", + 188 => x"72", + 189 => x"05", + 190 => x"51", + 191 => x"00", + 192 => x"70", + 193 => x"06", + 194 => x"06", + 195 => x"54", + 196 => x"09", + 197 => x"ff", + 198 => x"51", + 199 => x"00", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"05", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"05", + 233 => x"05", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"05", + 249 => x"53", + 250 => x"04", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"06", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"0b", + 265 => x"0b", + 266 => x"85", + 267 => x"0b", + 268 => x"0b", + 269 => x"a5", + 270 => x"0b", + 271 => x"0b", + 272 => x"c5", + 273 => x"0b", + 274 => x"0b", + 275 => x"e5", + 276 => x"0b", + 277 => x"0b", + 278 => x"85", + 279 => x"0b", + 280 => x"0b", + 281 => x"a5", + 282 => x"0b", + 283 => x"0b", + 284 => x"c5", + 285 => x"0b", + 286 => x"0b", + 287 => x"e5", + 288 => x"0b", + 289 => x"0b", + 290 => x"84", + 291 => x"0b", + 292 => x"0b", + 293 => x"a2", + 294 => x"0b", + 295 => x"0b", + 296 => x"c2", + 297 => x"0b", + 298 => x"0b", + 299 => x"e2", + 300 => x"0b", + 301 => x"0b", + 302 => x"82", + 303 => x"0b", + 304 => x"0b", + 305 => x"a2", + 306 => x"0b", + 307 => x"0b", + 308 => x"c2", + 309 => x"0b", + 310 => x"0b", + 311 => x"e2", + 312 => x"0b", + 313 => x"0b", + 314 => x"82", + 315 => x"0b", + 316 => x"0b", + 317 => x"a2", + 318 => x"0b", + 319 => x"0b", + 320 => x"c2", + 321 => x"0b", + 322 => x"0b", + 323 => x"e2", + 324 => x"0b", + 325 => x"0b", + 326 => x"82", + 327 => x"0b", + 328 => x"0b", + 329 => x"a2", + 330 => x"0b", + 331 => x"0b", + 332 => x"c2", + 333 => x"0b", + 334 => x"0b", + 335 => x"e2", + 336 => x"0b", + 337 => x"0b", + 338 => x"82", + 339 => x"0b", + 340 => x"0b", + 341 => x"a0", + 342 => x"0b", + 343 => x"ff", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"8c", + 385 => x"85", + 386 => x"c1", + 387 => x"85", + 388 => x"a0", + 389 => x"85", + 390 => x"ce", + 391 => x"85", + 392 => x"a0", + 393 => x"85", + 394 => x"ce", + 395 => x"85", + 396 => x"a0", + 397 => x"85", + 398 => x"ce", + 399 => x"85", + 400 => x"a0", + 401 => x"85", + 402 => x"d5", + 403 => x"85", + 404 => x"a0", + 405 => x"85", + 406 => x"d6", + 407 => x"85", + 408 => x"a0", + 409 => x"85", + 410 => x"cf", + 411 => x"85", + 412 => x"a0", + 413 => x"85", + 414 => x"d6", + 415 => x"85", + 416 => x"a0", + 417 => x"85", + 418 => x"d8", + 419 => x"85", + 420 => x"a0", + 421 => x"85", + 422 => x"d4", + 423 => x"85", + 424 => x"a0", + 425 => x"85", + 426 => x"cf", + 427 => x"85", + 428 => x"a0", + 429 => x"85", + 430 => x"d4", + 431 => x"85", + 432 => x"a0", + 433 => x"85", + 434 => x"d5", + 435 => x"85", + 436 => x"a0", + 437 => x"85", + 438 => x"c3", + 439 => x"85", + 440 => x"a0", + 441 => x"85", + 442 => x"c3", + 443 => x"85", + 444 => x"a0", + 445 => x"85", + 446 => x"c4", + 447 => x"f8", + 448 => x"90", + 449 => x"f8", + 450 => x"2d", + 451 => x"08", + 452 => x"04", + 453 => x"0c", + 454 => x"82", + 455 => x"82", + 456 => x"82", + 457 => x"81", + 458 => x"82", + 459 => x"82", + 460 => x"82", + 461 => x"81", + 462 => x"82", + 463 => x"82", + 464 => x"82", + 465 => x"81", + 466 => x"82", + 467 => x"82", + 468 => x"82", + 469 => x"81", + 470 => x"82", + 471 => x"82", + 472 => x"82", + 473 => x"81", + 474 => x"82", + 475 => x"82", + 476 => x"82", + 477 => x"81", + 478 => x"82", + 479 => x"82", + 480 => x"82", + 481 => x"81", + 482 => x"82", + 483 => x"82", + 484 => x"82", + 485 => x"81", + 486 => x"82", + 487 => x"82", + 488 => x"82", + 489 => x"81", + 490 => x"82", + 491 => x"82", + 492 => x"82", + 493 => x"81", + 494 => x"82", + 495 => x"82", + 496 => x"82", + 497 => x"81", + 498 => x"82", + 499 => x"82", + 500 => x"82", + 501 => x"81", + 502 => x"82", + 503 => x"82", + 504 => x"82", + 505 => x"81", + 506 => x"82", + 507 => x"82", + 508 => x"82", + 509 => x"81", + 510 => x"82", + 511 => x"82", + 512 => x"82", + 513 => x"81", + 514 => x"82", + 515 => x"82", + 516 => x"82", + 517 => x"81", + 518 => x"82", + 519 => x"82", + 520 => x"82", + 521 => x"81", + 522 => x"82", + 523 => x"82", + 524 => x"82", + 525 => x"81", + 526 => x"82", + 527 => x"82", + 528 => x"82", + 529 => x"81", + 530 => x"82", + 531 => x"82", + 532 => x"82", + 533 => x"81", + 534 => x"82", + 535 => x"82", + 536 => x"82", + 537 => x"81", + 538 => x"82", + 539 => x"82", + 540 => x"82", + 541 => x"81", + 542 => x"82", + 543 => x"82", + 544 => x"82", + 545 => x"81", + 546 => x"82", + 547 => x"82", + 548 => x"82", + 549 => x"81", + 550 => x"82", + 551 => x"82", + 552 => x"82", + 553 => x"81", + 554 => x"82", + 555 => x"82", + 556 => x"82", + 557 => x"81", + 558 => x"82", + 559 => x"82", + 560 => x"82", + 561 => x"81", + 562 => x"82", + 563 => x"82", + 564 => x"82", + 565 => x"80", + 566 => x"82", + 567 => x"82", + 568 => x"82", + 569 => x"80", + 570 => x"82", + 571 => x"82", + 572 => x"82", + 573 => x"80", + 574 => x"82", + 575 => x"82", + 576 => x"82", + 577 => x"bb", + 578 => x"85", + 579 => x"a0", + 580 => x"85", + 581 => x"93", + 582 => x"f8", + 583 => x"90", + 584 => x"f8", + 585 => x"80", + 586 => x"f8", + 587 => x"90", + 588 => x"f8", + 589 => x"2d", + 590 => x"08", + 591 => x"04", + 592 => x"00", + 593 => x"10", + 594 => x"10", + 595 => x"10", + 596 => x"10", + 597 => x"10", + 598 => x"10", + 599 => x"10", + 600 => x"53", + 601 => x"00", + 602 => x"06", + 603 => x"09", + 604 => x"05", + 605 => x"2b", + 606 => x"06", + 607 => x"04", + 608 => x"72", + 609 => x"05", + 610 => x"05", + 611 => x"72", + 612 => x"53", + 613 => x"51", + 614 => x"04", + 615 => x"70", + 616 => x"27", + 617 => x"71", + 618 => x"53", + 619 => x"0b", + 620 => x"8c", + 621 => x"9d", + 622 => x"85", + 623 => x"82", + 624 => x"fe", + 625 => x"85", + 626 => x"05", + 627 => x"f8", + 628 => x"0c", + 629 => x"08", + 630 => x"52", + 631 => x"85", + 632 => x"05", + 633 => x"82", + 634 => x"fc", + 635 => x"81", + 636 => x"51", + 637 => x"83", + 638 => x"82", + 639 => x"fc", + 640 => x"05", + 641 => x"08", + 642 => x"82", + 643 => x"fc", + 644 => x"85", + 645 => x"05", + 646 => x"82", + 647 => x"51", + 648 => x"82", + 649 => x"04", + 650 => x"08", + 651 => x"f8", + 652 => x"0d", + 653 => x"08", + 654 => x"82", + 655 => x"fc", + 656 => x"85", + 657 => x"05", + 658 => x"33", + 659 => x"08", + 660 => x"81", + 661 => x"f8", + 662 => x"0c", + 663 => x"08", + 664 => x"53", + 665 => x"34", + 666 => x"08", + 667 => x"81", + 668 => x"f8", + 669 => x"0c", + 670 => x"06", + 671 => x"2e", + 672 => x"be", + 673 => x"f8", + 674 => x"08", + 675 => x"ec", + 676 => x"3d", + 677 => x"f8", + 678 => x"85", + 679 => x"82", + 680 => x"fd", + 681 => x"85", + 682 => x"05", + 683 => x"f8", + 684 => x"0c", + 685 => x"08", + 686 => x"82", + 687 => x"f8", + 688 => x"85", + 689 => x"05", + 690 => x"80", + 691 => x"85", + 692 => x"05", + 693 => x"82", + 694 => x"90", + 695 => x"85", + 696 => x"05", + 697 => x"82", + 698 => x"90", + 699 => x"85", + 700 => x"05", + 701 => x"ba", + 702 => x"f8", + 703 => x"08", + 704 => x"82", + 705 => x"f8", + 706 => x"05", + 707 => x"08", + 708 => x"82", + 709 => x"fc", + 710 => x"52", + 711 => x"82", + 712 => x"fc", + 713 => x"05", + 714 => x"08", + 715 => x"ff", + 716 => x"85", + 717 => x"05", + 718 => x"85", + 719 => x"85", + 720 => x"85", + 721 => x"82", + 722 => x"02", + 723 => x"0c", + 724 => x"82", + 725 => x"90", + 726 => x"2e", + 727 => x"82", + 728 => x"8c", + 729 => x"71", + 730 => x"f8", + 731 => x"08", + 732 => x"85", + 733 => x"05", + 734 => x"f8", + 735 => x"08", + 736 => x"81", + 737 => x"54", + 738 => x"71", + 739 => x"80", + 740 => x"85", + 741 => x"05", + 742 => x"33", + 743 => x"08", + 744 => x"81", + 745 => x"f8", + 746 => x"0c", + 747 => x"06", + 748 => x"8d", + 749 => x"82", + 750 => x"fc", + 751 => x"9b", + 752 => x"f8", + 753 => x"08", + 754 => x"85", + 755 => x"05", + 756 => x"f8", + 757 => x"08", + 758 => x"38", + 759 => x"82", + 760 => x"90", + 761 => x"2e", + 762 => x"82", + 763 => x"88", + 764 => x"33", + 765 => x"8d", + 766 => x"82", + 767 => x"fc", + 768 => x"d7", + 769 => x"f8", + 770 => x"08", + 771 => x"85", + 772 => x"05", + 773 => x"f8", + 774 => x"08", + 775 => x"52", + 776 => x"81", + 777 => x"f8", + 778 => x"0c", + 779 => x"85", + 780 => x"05", + 781 => x"82", + 782 => x"8c", + 783 => x"33", + 784 => x"70", + 785 => x"08", + 786 => x"53", + 787 => x"53", + 788 => x"0b", + 789 => x"08", + 790 => x"82", + 791 => x"fc", + 792 => x"85", + 793 => x"3d", + 794 => x"f8", + 795 => x"85", + 796 => x"82", + 797 => x"fe", + 798 => x"85", + 799 => x"05", + 800 => x"f8", + 801 => x"0c", + 802 => x"08", + 803 => x"80", + 804 => x"38", + 805 => x"08", + 806 => x"81", + 807 => x"f8", + 808 => x"0c", + 809 => x"08", + 810 => x"ff", + 811 => x"f8", + 812 => x"0c", + 813 => x"08", + 814 => x"80", + 815 => x"82", + 816 => x"8c", + 817 => x"70", + 818 => x"08", + 819 => x"52", + 820 => x"34", + 821 => x"08", + 822 => x"81", + 823 => x"f8", + 824 => x"0c", + 825 => x"82", + 826 => x"88", + 827 => x"82", + 828 => x"51", + 829 => x"82", + 830 => x"04", + 831 => x"08", + 832 => x"f8", + 833 => x"0d", + 834 => x"85", + 835 => x"05", + 836 => x"f8", + 837 => x"08", + 838 => x"38", + 839 => x"08", + 840 => x"30", + 841 => x"08", + 842 => x"80", + 843 => x"f8", + 844 => x"0c", + 845 => x"08", + 846 => x"8a", + 847 => x"82", + 848 => x"f4", + 849 => x"85", + 850 => x"05", + 851 => x"f8", + 852 => x"0c", + 853 => x"08", + 854 => x"80", + 855 => x"82", + 856 => x"8c", + 857 => x"82", + 858 => x"8c", + 859 => x"0b", + 860 => x"08", + 861 => x"82", + 862 => x"fc", + 863 => x"38", + 864 => x"85", + 865 => x"05", + 866 => x"f8", + 867 => x"08", + 868 => x"08", + 869 => x"80", + 870 => x"f8", + 871 => x"08", + 872 => x"f8", + 873 => x"08", + 874 => x"3f", + 875 => x"08", + 876 => x"f8", + 877 => x"0c", + 878 => x"f8", + 879 => x"08", + 880 => x"38", + 881 => x"08", + 882 => x"30", + 883 => x"08", + 884 => x"82", + 885 => x"f8", + 886 => x"82", + 887 => x"54", + 888 => x"82", + 889 => x"04", + 890 => x"08", + 891 => x"f8", + 892 => x"0d", + 893 => x"85", + 894 => x"05", + 895 => x"f8", + 896 => x"08", + 897 => x"38", + 898 => x"08", + 899 => x"30", + 900 => x"08", + 901 => x"81", + 902 => x"f8", + 903 => x"0c", + 904 => x"08", + 905 => x"80", + 906 => x"82", + 907 => x"8c", + 908 => x"82", + 909 => x"8c", + 910 => x"53", + 911 => x"08", + 912 => x"52", + 913 => x"08", + 914 => x"51", + 915 => x"82", + 916 => x"70", + 917 => x"08", + 918 => x"54", + 919 => x"08", + 920 => x"80", + 921 => x"82", + 922 => x"f8", + 923 => x"82", + 924 => x"f8", + 925 => x"85", + 926 => x"05", + 927 => x"85", + 928 => x"87", + 929 => x"85", + 930 => x"82", + 931 => x"02", + 932 => x"0c", + 933 => x"80", + 934 => x"f8", + 935 => x"0c", + 936 => x"08", + 937 => x"81", + 938 => x"70", + 939 => x"85", + 940 => x"05", + 941 => x"85", + 942 => x"05", + 943 => x"85", + 944 => x"05", + 945 => x"f8", + 946 => x"08", + 947 => x"85", + 948 => x"05", + 949 => x"f8", + 950 => x"08", + 951 => x"f8", + 952 => x"0c", + 953 => x"51", + 954 => x"08", + 955 => x"80", + 956 => x"ff", + 957 => x"85", + 958 => x"05", + 959 => x"85", + 960 => x"83", + 961 => x"85", + 962 => x"82", + 963 => x"02", + 964 => x"0c", + 965 => x"80", + 966 => x"f8", + 967 => x"08", + 968 => x"f8", + 969 => x"08", + 970 => x"3f", + 971 => x"08", + 972 => x"ec", + 973 => x"3d", + 974 => x"f8", + 975 => x"85", + 976 => x"82", + 977 => x"fd", + 978 => x"53", + 979 => x"08", + 980 => x"52", + 981 => x"08", + 982 => x"51", + 983 => x"85", + 984 => x"82", + 985 => x"54", + 986 => x"82", + 987 => x"04", + 988 => x"08", + 989 => x"f8", + 990 => x"0d", + 991 => x"85", + 992 => x"05", + 993 => x"82", + 994 => x"f8", + 995 => x"85", + 996 => x"05", + 997 => x"f8", + 998 => x"08", + 999 => x"82", + 1000 => x"fc", + 1001 => x"2e", + 1002 => x"0b", + 1003 => x"08", + 1004 => x"24", + 1005 => x"85", + 1006 => x"05", + 1007 => x"85", + 1008 => x"05", + 1009 => x"f8", + 1010 => x"08", + 1011 => x"f8", + 1012 => x"0c", + 1013 => x"82", + 1014 => x"fc", + 1015 => x"2e", + 1016 => x"82", + 1017 => x"8c", + 1018 => x"85", + 1019 => x"05", + 1020 => x"38", + 1021 => x"08", + 1022 => x"82", + 1023 => x"8c", + 1024 => x"82", + 1025 => x"88", + 1026 => x"85", + 1027 => x"05", + 1028 => x"f8", + 1029 => x"08", + 1030 => x"f8", + 1031 => x"0c", + 1032 => x"08", + 1033 => x"81", + 1034 => x"f8", + 1035 => x"0c", + 1036 => x"08", + 1037 => x"81", + 1038 => x"f8", + 1039 => x"0c", + 1040 => x"82", + 1041 => x"90", + 1042 => x"2e", + 1043 => x"85", + 1044 => x"05", + 1045 => x"85", + 1046 => x"05", + 1047 => x"39", + 1048 => x"08", + 1049 => x"70", + 1050 => x"08", + 1051 => x"51", + 1052 => x"08", + 1053 => x"82", + 1054 => x"85", + 1055 => x"85", + 1056 => x"f9", + 1057 => x"70", + 1058 => x"56", + 1059 => x"2e", + 1060 => x"95", + 1061 => x"51", + 1062 => x"82", + 1063 => x"15", + 1064 => x"16", + 1065 => x"cd", + 1066 => x"54", + 1067 => x"09", + 1068 => x"38", + 1069 => x"f1", + 1070 => x"76", + 1071 => x"80", + 1072 => x"08", + 1073 => x"f2", + 1074 => x"ec", + 1075 => x"52", + 1076 => x"f4", + 1077 => x"85", + 1078 => x"38", + 1079 => x"54", + 1080 => x"ff", + 1081 => x"17", + 1082 => x"06", + 1083 => x"77", + 1084 => x"ff", + 1085 => x"85", + 1086 => x"3d", + 1087 => x"3d", + 1088 => x"71", + 1089 => x"8d", + 1090 => x"2b", + 1091 => x"8c", + 1092 => x"81", + 1093 => x"81", + 1094 => x"eb", + 1095 => x"f9", + 1096 => x"94", + 1097 => x"39", + 1098 => x"51", + 1099 => x"81", + 1100 => x"80", + 1101 => x"eb", + 1102 => x"dd", + 1103 => x"dc", + 1104 => x"39", + 1105 => x"51", + 1106 => x"81", + 1107 => x"80", + 1108 => x"ec", + 1109 => x"c1", + 1110 => x"b4", + 1111 => x"81", + 1112 => x"b5", + 1113 => x"e4", + 1114 => x"81", + 1115 => x"a9", + 1116 => x"a4", + 1117 => x"81", + 1118 => x"9d", + 1119 => x"d8", + 1120 => x"81", + 1121 => x"91", + 1122 => x"88", + 1123 => x"81", + 1124 => x"85", + 1125 => x"ac", + 1126 => x"3f", + 1127 => x"04", + 1128 => x"77", + 1129 => x"74", + 1130 => x"92", + 1131 => x"52", + 1132 => x"d7", + 1133 => x"82", + 1134 => x"51", + 1135 => x"e8", + 1136 => x"fa", + 1137 => x"85", + 1138 => x"75", + 1139 => x"3f", + 1140 => x"08", + 1141 => x"75", + 1142 => x"bc", + 1143 => x"3f", + 1144 => x"04", + 1145 => x"66", + 1146 => x"80", + 1147 => x"5b", + 1148 => x"78", + 1149 => x"70", + 1150 => x"25", + 1151 => x"59", + 1152 => x"87", + 1153 => x"38", + 1154 => x"76", + 1155 => x"ff", + 1156 => x"93", + 1157 => x"86", + 1158 => x"76", + 1159 => x"70", + 1160 => x"86", + 1161 => x"85", + 1162 => x"82", + 1163 => x"b9", + 1164 => x"ec", + 1165 => x"98", + 1166 => x"85", + 1167 => x"96", + 1168 => x"54", + 1169 => x"77", + 1170 => x"81", + 1171 => x"82", + 1172 => x"57", + 1173 => x"08", + 1174 => x"55", + 1175 => x"89", + 1176 => x"75", + 1177 => x"d7", + 1178 => x"d8", + 1179 => x"92", + 1180 => x"09", + 1181 => x"78", + 1182 => x"7b", + 1183 => x"70", + 1184 => x"06", + 1185 => x"56", + 1186 => x"90", + 1187 => x"e0", + 1188 => x"98", + 1189 => x"78", + 1190 => x"3f", + 1191 => x"82", + 1192 => x"96", + 1193 => x"f9", + 1194 => x"02", + 1195 => x"05", + 1196 => x"ff", + 1197 => x"7a", + 1198 => x"fe", + 1199 => x"85", + 1200 => x"38", + 1201 => x"88", + 1202 => x"2e", + 1203 => x"39", + 1204 => x"54", + 1205 => x"53", + 1206 => x"51", + 1207 => x"85", + 1208 => x"83", + 1209 => x"76", + 1210 => x"0c", + 1211 => x"04", + 1212 => x"7f", + 1213 => x"8c", + 1214 => x"05", + 1215 => x"15", + 1216 => x"5c", + 1217 => x"5e", + 1218 => x"ee", + 1219 => x"cc", + 1220 => x"f0", + 1221 => x"3f", + 1222 => x"79", + 1223 => x"38", + 1224 => x"89", + 1225 => x"2e", + 1226 => x"c1", + 1227 => x"53", + 1228 => x"8d", + 1229 => x"52", + 1230 => x"51", + 1231 => x"88", + 1232 => x"80", + 1233 => x"3f", + 1234 => x"bf", + 1235 => x"53", + 1236 => x"8d", + 1237 => x"52", + 1238 => x"51", + 1239 => x"88", + 1240 => x"fc", + 1241 => x"3f", + 1242 => x"9f", + 1243 => x"53", + 1244 => x"8d", + 1245 => x"52", + 1246 => x"51", + 1247 => x"88", + 1248 => x"90", + 1249 => x"3f", + 1250 => x"a0", + 1251 => x"3f", + 1252 => x"81", + 1253 => x"a7", + 1254 => x"55", + 1255 => x"bb", + 1256 => x"70", + 1257 => x"80", + 1258 => x"27", + 1259 => x"56", + 1260 => x"74", + 1261 => x"81", + 1262 => x"06", + 1263 => x"06", + 1264 => x"80", + 1265 => x"73", + 1266 => x"85", + 1267 => x"83", + 1268 => x"a6", + 1269 => x"15", + 1270 => x"81", + 1271 => x"a7", + 1272 => x"18", + 1273 => x"58", + 1274 => x"82", + 1275 => x"98", + 1276 => x"2c", + 1277 => x"a0", + 1278 => x"06", + 1279 => x"e5", + 1280 => x"ec", + 1281 => x"70", + 1282 => x"a0", + 1283 => x"81", + 1284 => x"32", + 1285 => x"05", + 1286 => x"73", + 1287 => x"51", + 1288 => x"57", + 1289 => x"73", + 1290 => x"76", + 1291 => x"81", + 1292 => x"80", + 1293 => x"7c", + 1294 => x"78", + 1295 => x"38", + 1296 => x"82", + 1297 => x"8f", + 1298 => x"fc", + 1299 => x"9b", + 1300 => x"ef", + 1301 => x"ef", + 1302 => x"ab", + 1303 => x"84", + 1304 => x"a4", + 1305 => x"ef", + 1306 => x"ef", + 1307 => x"84", + 1308 => x"81", + 1309 => x"ab", + 1310 => x"80", + 1311 => x"a0", + 1312 => x"3d", + 1313 => x"3d", + 1314 => x"96", + 1315 => x"a4", + 1316 => x"51", + 1317 => x"81", + 1318 => x"98", + 1319 => x"51", + 1320 => x"72", + 1321 => x"81", + 1322 => x"71", + 1323 => x"38", + 1324 => x"cd", + 1325 => x"f4", + 1326 => x"3f", + 1327 => x"c1", + 1328 => x"2a", + 1329 => x"51", + 1330 => x"2e", + 1331 => x"51", + 1332 => x"81", + 1333 => x"98", + 1334 => x"51", + 1335 => x"72", + 1336 => x"81", + 1337 => x"71", + 1338 => x"38", + 1339 => x"91", + 1340 => x"98", + 1341 => x"3f", + 1342 => x"85", + 1343 => x"2a", + 1344 => x"51", + 1345 => x"2e", + 1346 => x"51", + 1347 => x"81", + 1348 => x"97", + 1349 => x"51", + 1350 => x"72", + 1351 => x"81", + 1352 => x"71", + 1353 => x"38", + 1354 => x"d5", + 1355 => x"c0", + 1356 => x"3f", + 1357 => x"c9", + 1358 => x"2a", + 1359 => x"51", + 1360 => x"2e", + 1361 => x"51", + 1362 => x"81", + 1363 => x"97", + 1364 => x"51", + 1365 => x"72", + 1366 => x"81", + 1367 => x"71", + 1368 => x"38", + 1369 => x"99", + 1370 => x"e8", + 1371 => x"3f", + 1372 => x"8d", + 1373 => x"2a", + 1374 => x"51", + 1375 => x"2e", + 1376 => x"51", + 1377 => x"81", + 1378 => x"96", + 1379 => x"51", + 1380 => x"a2", + 1381 => x"3d", + 1382 => x"3d", + 1383 => x"84", + 1384 => x"33", + 1385 => x"56", + 1386 => x"51", + 1387 => x"0b", + 1388 => x"e8", + 1389 => x"ab", + 1390 => x"81", + 1391 => x"82", + 1392 => x"80", + 1393 => x"82", + 1394 => x"09", + 1395 => x"82", + 1396 => x"07", + 1397 => x"71", + 1398 => x"54", + 1399 => x"82", + 1400 => x"0b", + 1401 => x"e8", + 1402 => x"81", + 1403 => x"06", + 1404 => x"9c", + 1405 => x"52", + 1406 => x"b9", + 1407 => x"85", + 1408 => x"2e", + 1409 => x"85", + 1410 => x"a2", + 1411 => x"39", + 1412 => x"51", + 1413 => x"3f", + 1414 => x"0b", + 1415 => x"34", + 1416 => x"80", + 1417 => x"73", + 1418 => x"81", + 1419 => x"81", + 1420 => x"74", + 1421 => x"b5", + 1422 => x"0b", + 1423 => x"0c", + 1424 => x"04", + 1425 => x"80", + 1426 => x"9c", + 1427 => x"5d", + 1428 => x"51", + 1429 => x"3f", + 1430 => x"08", + 1431 => x"59", + 1432 => x"09", + 1433 => x"38", + 1434 => x"52", + 1435 => x"52", + 1436 => x"3f", + 1437 => x"52", + 1438 => x"51", + 1439 => x"3f", + 1440 => x"08", + 1441 => x"38", + 1442 => x"51", + 1443 => x"81", + 1444 => x"81", + 1445 => x"a1", + 1446 => x"3d", + 1447 => x"80", + 1448 => x"51", + 1449 => x"b4", + 1450 => x"05", + 1451 => x"3f", + 1452 => x"08", + 1453 => x"90", + 1454 => x"78", + 1455 => x"87", + 1456 => x"80", + 1457 => x"38", + 1458 => x"81", + 1459 => x"bd", + 1460 => x"78", + 1461 => x"bb", + 1462 => x"2e", + 1463 => x"8a", + 1464 => x"80", + 1465 => x"94", + 1466 => x"c0", + 1467 => x"38", + 1468 => x"82", + 1469 => x"a4", + 1470 => x"f9", + 1471 => x"38", + 1472 => x"24", + 1473 => x"80", + 1474 => x"fa", + 1475 => x"f8", + 1476 => x"38", + 1477 => x"78", + 1478 => x"89", + 1479 => x"81", + 1480 => x"38", + 1481 => x"2e", + 1482 => x"89", + 1483 => x"81", + 1484 => x"e2", + 1485 => x"39", + 1486 => x"80", + 1487 => x"84", + 1488 => x"90", + 1489 => x"ec", + 1490 => x"fe", + 1491 => x"3d", + 1492 => x"53", + 1493 => x"51", + 1494 => x"82", + 1495 => x"80", + 1496 => x"38", + 1497 => x"f8", + 1498 => x"84", + 1499 => x"e4", + 1500 => x"ec", + 1501 => x"82", + 1502 => x"42", + 1503 => x"51", + 1504 => x"63", + 1505 => x"79", + 1506 => x"e9", + 1507 => x"78", + 1508 => x"05", + 1509 => x"7a", + 1510 => x"81", + 1511 => x"3d", + 1512 => x"53", + 1513 => x"51", + 1514 => x"82", + 1515 => x"80", + 1516 => x"38", + 1517 => x"fc", + 1518 => x"84", + 1519 => x"94", + 1520 => x"ec", + 1521 => x"fd", + 1522 => x"3d", + 1523 => x"53", + 1524 => x"51", + 1525 => x"82", + 1526 => x"80", + 1527 => x"38", + 1528 => x"51", + 1529 => x"63", + 1530 => x"27", + 1531 => x"61", + 1532 => x"81", + 1533 => x"79", + 1534 => x"05", + 1535 => x"b4", + 1536 => x"11", + 1537 => x"05", + 1538 => x"3f", + 1539 => x"08", + 1540 => x"ff", + 1541 => x"fe", + 1542 => x"ff", + 1543 => x"a6", + 1544 => x"85", + 1545 => x"2e", + 1546 => x"b4", + 1547 => x"11", + 1548 => x"05", + 1549 => x"3f", + 1550 => x"08", + 1551 => x"d3", + 1552 => x"b0", + 1553 => x"3f", + 1554 => x"63", + 1555 => x"61", + 1556 => x"33", + 1557 => x"78", + 1558 => x"38", + 1559 => x"54", + 1560 => x"79", + 1561 => x"c0", + 1562 => x"3f", + 1563 => x"81", + 1564 => x"d6", + 1565 => x"d8", + 1566 => x"39", + 1567 => x"80", + 1568 => x"84", + 1569 => x"cc", + 1570 => x"ec", + 1571 => x"38", + 1572 => x"33", + 1573 => x"2e", + 1574 => x"84", + 1575 => x"80", + 1576 => x"84", + 1577 => x"78", + 1578 => x"38", + 1579 => x"08", + 1580 => x"82", + 1581 => x"59", + 1582 => x"88", + 1583 => x"a0", + 1584 => x"39", + 1585 => x"33", + 1586 => x"2e", + 1587 => x"84", + 1588 => x"9a", + 1589 => x"d6", + 1590 => x"80", + 1591 => x"82", + 1592 => x"44", + 1593 => x"84", + 1594 => x"80", + 1595 => x"3d", + 1596 => x"53", + 1597 => x"51", + 1598 => x"82", + 1599 => x"80", + 1600 => x"84", + 1601 => x"78", + 1602 => x"38", + 1603 => x"08", + 1604 => x"39", + 1605 => x"33", + 1606 => x"2e", + 1607 => x"84", + 1608 => x"bb", + 1609 => x"da", + 1610 => x"80", + 1611 => x"82", + 1612 => x"43", + 1613 => x"84", + 1614 => x"78", + 1615 => x"38", + 1616 => x"08", + 1617 => x"82", + 1618 => x"59", + 1619 => x"88", + 1620 => x"b4", + 1621 => x"39", + 1622 => x"08", + 1623 => x"b4", + 1624 => x"11", + 1625 => x"05", + 1626 => x"3f", + 1627 => x"08", + 1628 => x"38", + 1629 => x"5c", + 1630 => x"83", + 1631 => x"7a", + 1632 => x"09", + 1633 => x"72", + 1634 => x"70", + 1635 => x"51", + 1636 => x"80", + 1637 => x"7a", + 1638 => x"38", + 1639 => x"f2", + 1640 => x"c8", + 1641 => x"63", + 1642 => x"62", + 1643 => x"f2", + 1644 => x"f2", + 1645 => x"b4", + 1646 => x"39", + 1647 => x"80", + 1648 => x"84", + 1649 => x"8c", + 1650 => x"ec", + 1651 => x"f9", + 1652 => x"3d", + 1653 => x"53", + 1654 => x"51", + 1655 => x"82", + 1656 => x"80", + 1657 => x"63", + 1658 => x"cb", + 1659 => x"34", + 1660 => x"44", + 1661 => x"fc", + 1662 => x"84", + 1663 => x"d4", + 1664 => x"ec", + 1665 => x"f9", + 1666 => x"70", + 1667 => x"81", + 1668 => x"a0", + 1669 => x"f8", + 1670 => x"a1", + 1671 => x"45", + 1672 => x"78", + 1673 => x"eb", + 1674 => x"27", + 1675 => x"3d", + 1676 => x"53", + 1677 => x"51", + 1678 => x"82", + 1679 => x"80", + 1680 => x"63", + 1681 => x"cb", + 1682 => x"34", + 1683 => x"44", + 1684 => x"81", + 1685 => x"9a", + 1686 => x"ae", + 1687 => x"fe", + 1688 => x"ff", + 1689 => x"a3", + 1690 => x"85", + 1691 => x"2e", + 1692 => x"b4", + 1693 => x"11", + 1694 => x"05", + 1695 => x"3f", + 1696 => x"08", + 1697 => x"38", + 1698 => x"be", + 1699 => x"70", + 1700 => x"23", + 1701 => x"3d", + 1702 => x"53", + 1703 => x"51", + 1704 => x"82", + 1705 => x"e0", + 1706 => x"39", + 1707 => x"54", + 1708 => x"8c", + 1709 => x"3f", + 1710 => x"79", + 1711 => x"3f", + 1712 => x"33", + 1713 => x"2e", + 1714 => x"78", + 1715 => x"38", + 1716 => x"41", + 1717 => x"3d", + 1718 => x"53", + 1719 => x"51", + 1720 => x"82", + 1721 => x"80", + 1722 => x"60", + 1723 => x"05", + 1724 => x"82", + 1725 => x"78", + 1726 => x"39", + 1727 => x"51", + 1728 => x"ff", + 1729 => x"3d", + 1730 => x"53", + 1731 => x"51", + 1732 => x"82", + 1733 => x"80", + 1734 => x"38", + 1735 => x"f0", + 1736 => x"84", + 1737 => x"a8", + 1738 => x"ec", + 1739 => x"a0", + 1740 => x"71", + 1741 => x"84", + 1742 => x"3d", + 1743 => x"53", + 1744 => x"51", + 1745 => x"82", + 1746 => x"e5", + 1747 => x"39", + 1748 => x"54", + 1749 => x"98", + 1750 => x"3f", + 1751 => x"79", + 1752 => x"3f", + 1753 => x"33", + 1754 => x"2e", + 1755 => x"9f", + 1756 => x"38", + 1757 => x"f0", + 1758 => x"84", + 1759 => x"d0", + 1760 => x"ec", + 1761 => x"8d", + 1762 => x"71", + 1763 => x"84", + 1764 => x"bc", + 1765 => x"84", + 1766 => x"3f", + 1767 => x"b4", + 1768 => x"11", + 1769 => x"05", + 1770 => x"3f", + 1771 => x"08", + 1772 => x"df", + 1773 => x"81", + 1774 => x"9d", + 1775 => x"59", + 1776 => x"3d", + 1777 => x"53", + 1778 => x"51", + 1779 => x"82", + 1780 => x"80", + 1781 => x"38", + 1782 => x"f3", + 1783 => x"fc", + 1784 => x"78", + 1785 => x"ec", + 1786 => x"f5", + 1787 => x"85", + 1788 => x"81", + 1789 => x"9c", + 1790 => x"97", + 1791 => x"f8", + 1792 => x"3f", + 1793 => x"f5", + 1794 => x"f4", + 1795 => x"dc", + 1796 => x"ff", + 1797 => x"ef", + 1798 => x"39", + 1799 => x"33", + 1800 => x"2e", + 1801 => x"7d", + 1802 => x"78", + 1803 => x"d0", + 1804 => x"ff", + 1805 => x"83", + 1806 => x"85", + 1807 => x"81", + 1808 => x"2e", + 1809 => x"82", + 1810 => x"7a", + 1811 => x"38", + 1812 => x"7a", + 1813 => x"38", + 1814 => x"81", + 1815 => x"7b", + 1816 => x"ac", + 1817 => x"81", + 1818 => x"b4", + 1819 => x"05", + 1820 => x"3f", + 1821 => x"f4", + 1822 => x"3d", + 1823 => x"51", + 1824 => x"a9", + 1825 => x"81", + 1826 => x"80", + 1827 => x"c0", + 1828 => x"ff", + 1829 => x"9b", + 1830 => x"39", + 1831 => x"53", + 1832 => x"52", + 1833 => x"b0", + 1834 => x"c6", + 1835 => x"90", + 1836 => x"fc", + 1837 => x"64", + 1838 => x"82", + 1839 => x"82", + 1840 => x"b4", + 1841 => x"05", + 1842 => x"3f", + 1843 => x"08", + 1844 => x"08", + 1845 => x"81", + 1846 => x"07", + 1847 => x"5b", + 1848 => x"5a", + 1849 => x"83", + 1850 => x"78", + 1851 => x"78", + 1852 => x"38", + 1853 => x"81", + 1854 => x"59", + 1855 => x"38", + 1856 => x"7d", + 1857 => x"59", + 1858 => x"7e", + 1859 => x"81", + 1860 => x"38", + 1861 => x"51", + 1862 => x"f2", + 1863 => x"3d", + 1864 => x"82", + 1865 => x"87", + 1866 => x"70", + 1867 => x"87", + 1868 => x"72", + 1869 => x"3f", + 1870 => x"08", + 1871 => x"08", + 1872 => x"84", + 1873 => x"51", + 1874 => x"72", + 1875 => x"08", + 1876 => x"87", + 1877 => x"70", + 1878 => x"87", + 1879 => x"72", + 1880 => x"3f", + 1881 => x"08", + 1882 => x"08", + 1883 => x"84", + 1884 => x"51", + 1885 => x"72", + 1886 => x"08", + 1887 => x"8c", + 1888 => x"87", + 1889 => x"0c", + 1890 => x"0b", + 1891 => x"94", + 1892 => x"9a", + 1893 => x"f4", + 1894 => x"95", + 1895 => x"f8", + 1896 => x"3f", + 1897 => x"81", + 1898 => x"93", + 1899 => x"f4", + 1900 => x"b8", + 1901 => x"51", + 1902 => x"81", + 1903 => x"3f", + 1904 => x"80", + 1905 => x"0d", + 1906 => x"53", + 1907 => x"52", + 1908 => x"82", + 1909 => x"81", + 1910 => x"07", + 1911 => x"52", + 1912 => x"e8", + 1913 => x"85", + 1914 => x"3d", + 1915 => x"3d", + 1916 => x"08", + 1917 => x"73", + 1918 => x"74", + 1919 => x"38", + 1920 => x"70", + 1921 => x"81", + 1922 => x"81", + 1923 => x"39", + 1924 => x"70", + 1925 => x"81", + 1926 => x"81", + 1927 => x"54", + 1928 => x"81", + 1929 => x"06", + 1930 => x"39", + 1931 => x"80", + 1932 => x"54", + 1933 => x"83", + 1934 => x"70", + 1935 => x"38", + 1936 => x"98", + 1937 => x"52", + 1938 => x"52", + 1939 => x"2e", + 1940 => x"54", + 1941 => x"84", + 1942 => x"38", + 1943 => x"52", + 1944 => x"2e", + 1945 => x"83", + 1946 => x"70", + 1947 => x"09", + 1948 => x"80", + 1949 => x"51", + 1950 => x"80", + 1951 => x"80", + 1952 => x"05", + 1953 => x"75", + 1954 => x"70", + 1955 => x"0c", + 1956 => x"04", + 1957 => x"76", + 1958 => x"80", + 1959 => x"86", + 1960 => x"52", + 1961 => x"a8", + 1962 => x"ec", + 1963 => x"80", + 1964 => x"74", + 1965 => x"85", + 1966 => x"3d", + 1967 => x"3d", + 1968 => x"11", + 1969 => x"52", + 1970 => x"70", + 1971 => x"98", + 1972 => x"33", + 1973 => x"82", + 1974 => x"26", + 1975 => x"84", + 1976 => x"83", + 1977 => x"26", + 1978 => x"85", + 1979 => x"84", + 1980 => x"26", + 1981 => x"86", + 1982 => x"85", + 1983 => x"26", + 1984 => x"88", + 1985 => x"86", + 1986 => x"e7", + 1987 => x"38", + 1988 => x"54", + 1989 => x"87", + 1990 => x"cc", + 1991 => x"87", + 1992 => x"0c", + 1993 => x"c0", + 1994 => x"82", + 1995 => x"c0", + 1996 => x"83", + 1997 => x"c0", + 1998 => x"84", + 1999 => x"c0", + 2000 => x"85", + 2001 => x"c0", + 2002 => x"86", + 2003 => x"c0", + 2004 => x"74", + 2005 => x"a4", + 2006 => x"c0", + 2007 => x"80", + 2008 => x"98", + 2009 => x"52", + 2010 => x"ec", + 2011 => x"0d", + 2012 => x"0d", + 2013 => x"c0", + 2014 => x"81", + 2015 => x"c0", + 2016 => x"5e", + 2017 => x"87", + 2018 => x"08", + 2019 => x"1c", + 2020 => x"98", + 2021 => x"79", + 2022 => x"87", + 2023 => x"08", + 2024 => x"1c", + 2025 => x"98", + 2026 => x"79", + 2027 => x"87", + 2028 => x"08", + 2029 => x"1c", + 2030 => x"98", + 2031 => x"7b", + 2032 => x"87", + 2033 => x"08", + 2034 => x"1c", + 2035 => x"0c", + 2036 => x"ff", + 2037 => x"83", + 2038 => x"58", + 2039 => x"57", + 2040 => x"56", + 2041 => x"55", + 2042 => x"54", + 2043 => x"53", + 2044 => x"ff", + 2045 => x"f5", + 2046 => x"e0", + 2047 => x"0d", + 2048 => x"0d", + 2049 => x"33", + 2050 => x"05", + 2051 => x"51", + 2052 => x"82", + 2053 => x"83", + 2054 => x"fb", + 2055 => x"82", + 2056 => x"70", + 2057 => x"57", + 2058 => x"c0", + 2059 => x"74", + 2060 => x"38", + 2061 => x"94", + 2062 => x"70", + 2063 => x"81", + 2064 => x"52", + 2065 => x"8c", + 2066 => x"2a", + 2067 => x"51", + 2068 => x"38", + 2069 => x"70", + 2070 => x"51", + 2071 => x"8d", + 2072 => x"2a", + 2073 => x"51", + 2074 => x"be", + 2075 => x"ff", + 2076 => x"c0", + 2077 => x"70", + 2078 => x"38", + 2079 => x"90", + 2080 => x"0c", + 2081 => x"ec", + 2082 => x"0d", + 2083 => x"0d", + 2084 => x"33", + 2085 => x"33", + 2086 => x"06", + 2087 => x"87", + 2088 => x"51", + 2089 => x"86", + 2090 => x"94", + 2091 => x"08", + 2092 => x"70", + 2093 => x"54", + 2094 => x"2e", + 2095 => x"91", + 2096 => x"06", + 2097 => x"d7", + 2098 => x"32", + 2099 => x"51", + 2100 => x"2e", + 2101 => x"93", + 2102 => x"06", + 2103 => x"ff", + 2104 => x"81", + 2105 => x"87", + 2106 => x"52", + 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x"c0", + 2225 => x"9e", + 2226 => x"70", + 2227 => x"23", + 2228 => x"84", + 2229 => x"c8", + 2230 => x"9e", + 2231 => x"84", + 2232 => x"c0", + 2233 => x"82", + 2234 => x"81", + 2235 => x"d4", + 2236 => x"87", + 2237 => x"08", + 2238 => x"0a", + 2239 => x"52", + 2240 => x"83", + 2241 => x"71", + 2242 => x"34", + 2243 => x"c0", + 2244 => x"70", + 2245 => x"06", + 2246 => x"70", + 2247 => x"38", + 2248 => x"82", + 2249 => x"80", + 2250 => x"9e", + 2251 => x"90", + 2252 => x"51", + 2253 => x"80", + 2254 => x"81", + 2255 => x"84", + 2256 => x"0b", + 2257 => x"90", + 2258 => x"80", + 2259 => x"52", + 2260 => x"2e", + 2261 => x"52", + 2262 => x"d8", + 2263 => x"87", + 2264 => x"08", + 2265 => x"80", + 2266 => x"52", + 2267 => x"83", + 2268 => x"71", + 2269 => x"34", + 2270 => x"c0", + 2271 => x"70", + 2272 => x"06", + 2273 => x"70", + 2274 => x"38", + 2275 => x"82", + 2276 => x"80", + 2277 => x"9e", + 2278 => x"84", + 2279 => x"51", + 2280 => x"80", + 2281 => x"81", + 2282 => x"84", + 2283 => x"0b", + 2284 => x"90", + 2285 => x"80", + 2286 => x"52", + 2287 => x"2e", + 2288 => x"52", + 2289 => x"dc", + 2290 => x"87", + 2291 => x"08", + 2292 => x"80", + 2293 => x"52", + 2294 => x"83", + 2295 => x"71", + 2296 => x"34", + 2297 => x"c0", + 2298 => x"70", + 2299 => x"06", + 2300 => x"70", + 2301 => x"38", + 2302 => x"82", + 2303 => x"80", + 2304 => x"9e", + 2305 => x"a0", + 2306 => x"52", + 2307 => x"2e", + 2308 => x"52", + 2309 => x"df", + 2310 => x"9e", + 2311 => x"98", + 2312 => x"8a", + 2313 => x"51", + 2314 => x"e0", + 2315 => x"87", + 2316 => x"08", + 2317 => x"06", + 2318 => x"70", + 2319 => x"38", + 2320 => x"82", + 2321 => x"87", + 2322 => x"08", + 2323 => x"06", + 2324 => x"51", + 2325 => x"82", + 2326 => x"80", + 2327 => x"9e", + 2328 => x"88", + 2329 => x"52", + 2330 => x"83", + 2331 => x"71", + 2332 => x"34", + 2333 => x"90", + 2334 => x"06", + 2335 => x"82", + 2336 => x"83", + 2337 => x"fc", + 2338 => x"f5", + 2339 => x"dc", + 2340 => x"d4", + 2341 => x"80", + 2342 => x"81", + 2343 => x"85", + 2344 => x"f5", + 2345 => x"c4", + 2346 => x"d6", + 2347 => x"80", + 2348 => x"82", + 2349 => x"82", + 2350 => x"11", + 2351 => x"f5", + 2352 => x"98", + 2353 => x"db", + 2354 => x"80", + 2355 => x"82", + 2356 => x"82", + 2357 => x"11", + 2358 => x"f5", + 2359 => x"fc", + 2360 => x"d8", + 2361 => x"80", + 2362 => x"82", + 2363 => x"82", + 2364 => x"11", + 2365 => x"f6", + 2366 => x"e0", + 2367 => x"d9", + 2368 => x"80", + 2369 => x"82", + 2370 => x"82", + 2371 => x"11", + 2372 => x"f6", + 2373 => x"c4", + 2374 => x"da", + 2375 => x"80", + 2376 => x"82", + 2377 => x"82", + 2378 => x"11", + 2379 => x"f6", + 2380 => x"a8", + 2381 => x"df", + 2382 => x"80", + 2383 => x"82", + 2384 => x"52", + 2385 => x"51", + 2386 => x"82", + 2387 => x"54", + 2388 => x"8d", + 2389 => x"e4", + 2390 => x"f7", + 2391 => x"fc", + 2392 => x"e1", + 2393 => x"80", + 2394 => x"82", + 2395 => x"52", + 2396 => x"51", + 2397 => x"82", + 2398 => x"54", + 2399 => x"88", + 2400 => x"cc", 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x"87", + 2460 => x"84", + 2461 => x"73", + 2462 => x"38", + 2463 => x"08", + 2464 => x"c0", + 2465 => x"d1", + 2466 => x"85", + 2467 => x"bd", + 2468 => x"82", + 2469 => x"51", + 2470 => x"74", + 2471 => x"08", + 2472 => x"52", + 2473 => x"51", + 2474 => x"81", + 2475 => x"81", + 2476 => x"3d", + 2477 => x"3d", + 2478 => x"05", + 2479 => x"52", + 2480 => x"a9", + 2481 => x"2b", + 2482 => x"dc", + 2483 => x"81", + 2484 => x"9d", + 2485 => x"d0", + 2486 => x"81", + 2487 => x"91", + 2488 => x"e0", + 2489 => x"81", + 2490 => x"85", + 2491 => x"ec", + 2492 => x"3f", + 2493 => x"04", + 2494 => x"0c", + 2495 => x"87", + 2496 => x"0c", + 2497 => x"e8", + 2498 => x"96", + 2499 => x"fe", + 2500 => x"93", + 2501 => x"72", + 2502 => x"81", + 2503 => x"8d", + 2504 => x"82", + 2505 => x"52", + 2506 => x"90", + 2507 => x"34", + 2508 => x"08", + 2509 => x"9c", + 2510 => x"39", + 2511 => x"08", + 2512 => x"2e", + 2513 => x"51", + 2514 => x"3d", + 2515 => x"3d", + 2516 => x"05", + 2517 => x"f4", + 2518 => x"9c", + 2519 => x"51", + 2520 => x"72", + 2521 => x"0c", + 2522 => x"04", + 2523 => x"75", + 2524 => x"70", + 2525 => x"53", + 2526 => x"2e", + 2527 => x"81", + 2528 => x"81", + 2529 => x"87", + 2530 => x"85", + 2531 => x"fc", + 2532 => x"82", + 2533 => x"78", + 2534 => x"0c", + 2535 => x"33", + 2536 => x"06", + 2537 => x"80", + 2538 => x"72", + 2539 => x"51", + 2540 => x"fe", + 2541 => x"39", + 2542 => x"f4", + 2543 => x"0d", + 2544 => x"0d", + 2545 => x"59", + 2546 => x"05", + 2547 => x"75", + 2548 => x"84", + 2549 => x"2e", + 2550 => x"82", + 2551 => x"70", + 2552 => x"05", + 2553 => x"5b", + 2554 => x"2e", + 2555 => x"85", + 2556 => x"8b", + 2557 => x"2e", + 2558 => x"8a", + 2559 => x"78", + 2560 => x"5a", + 2561 => x"aa", + 2562 => x"06", + 2563 => x"84", + 2564 => x"7b", + 2565 => x"5d", + 2566 => x"59", + 2567 => x"d0", + 2568 => x"89", + 2569 => x"7a", + 2570 => x"11", + 2571 => x"d0", + 2572 => x"81", + 2573 => x"59", + 2574 => x"e3", + 2575 => x"ec", + 2576 => x"81", + 2577 => x"07", + 2578 => x"80", + 2579 => x"09", + 2580 => x"72", + 2581 => x"73", + 2582 => x"58", + 2583 => x"73", + 2584 => x"38", + 2585 => x"79", + 2586 => x"5b", + 2587 => x"75", + 2588 => x"e4", + 2589 => x"80", + 2590 => x"89", + 2591 => x"70", + 2592 => x"55", + 2593 => x"cf", + 2594 => x"38", + 2595 => x"24", + 2596 => x"80", + 2597 => x"8e", + 2598 => x"c3", + 2599 => x"73", + 2600 => x"81", + 2601 => x"99", + 2602 => x"c4", + 2603 => x"38", + 2604 => x"73", + 2605 => x"81", + 2606 => x"80", + 2607 => x"38", + 2608 => x"2e", + 2609 => x"f9", + 2610 => x"d8", + 2611 => x"38", + 2612 => x"77", + 2613 => x"08", + 2614 => x"80", + 2615 => x"55", + 2616 => x"8d", + 2617 => x"70", + 2618 => x"51", + 2619 => x"f5", + 2620 => x"2a", + 2621 => x"74", + 2622 => x"53", + 2623 => x"8f", + 2624 => x"fc", + 2625 => x"81", + 2626 => x"80", + 2627 => x"73", + 2628 => x"3f", + 2629 => x"56", + 2630 => x"27", + 2631 => x"a0", + 2632 => x"3f", + 2633 => x"84", + 2634 => x"33", + 2635 => x"93", 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x"51", + 2695 => x"75", + 2696 => x"72", + 2697 => x"81", + 2698 => x"7a", + 2699 => x"38", + 2700 => x"05", + 2701 => x"ff", + 2702 => x"70", + 2703 => x"57", + 2704 => x"76", + 2705 => x"81", + 2706 => x"72", + 2707 => x"f8", + 2708 => x"f9", + 2709 => x"39", + 2710 => x"04", + 2711 => x"86", + 2712 => x"84", + 2713 => x"55", + 2714 => x"fa", + 2715 => x"3d", + 2716 => x"3d", + 2717 => x"9c", + 2718 => x"3d", + 2719 => x"75", + 2720 => x"3f", + 2721 => x"08", + 2722 => x"34", + 2723 => x"9c", + 2724 => x"3d", + 2725 => x"3d", + 2726 => x"f4", + 2727 => x"9c", + 2728 => x"3d", + 2729 => x"77", + 2730 => x"95", + 2731 => x"9c", + 2732 => x"3d", + 2733 => x"3d", + 2734 => x"82", + 2735 => x"70", + 2736 => x"55", + 2737 => x"80", + 2738 => x"38", + 2739 => x"08", + 2740 => x"82", + 2741 => x"81", + 2742 => x"72", + 2743 => x"ce", + 2744 => x"2e", + 2745 => x"88", + 2746 => x"81", + 2747 => x"25", + 2748 => x"73", + 2749 => x"38", + 2750 => x"86", + 2751 => x"54", + 2752 => x"73", + 2753 => x"ff", + 2754 => x"72", + 2755 => x"38", + 2756 => x"72", + 2757 => x"14", + 2758 => x"f7", + 2759 => x"ac", + 2760 => x"52", + 2761 => x"8a", + 2762 => x"3f", + 2763 => x"82", + 2764 => x"87", + 2765 => x"fe", + 2766 => x"9c", + 2767 => x"82", + 2768 => x"77", + 2769 => x"53", + 2770 => x"72", + 2771 => x"0c", + 2772 => x"04", + 2773 => x"7a", + 2774 => x"80", + 2775 => x"58", + 2776 => x"33", + 2777 => x"a0", + 2778 => x"06", + 2779 => x"13", + 2780 => x"39", + 2781 => x"09", + 2782 => x"38", + 2783 => x"11", + 2784 => x"08", + 2785 => x"54", + 2786 => x"2e", + 2787 => x"80", + 2788 => x"08", + 2789 => x"0c", + 2790 => x"33", + 2791 => x"80", + 2792 => x"38", + 2793 => x"80", + 2794 => x"38", + 2795 => x"57", + 2796 => x"0c", + 2797 => x"33", + 2798 => x"39", + 2799 => x"74", + 2800 => x"38", + 2801 => x"80", + 2802 => x"89", + 2803 => x"38", + 2804 => x"d0", + 2805 => x"55", + 2806 => x"80", + 2807 => x"39", + 2808 => x"e3", + 2809 => x"80", + 2810 => x"27", + 2811 => x"80", + 2812 => x"89", + 2813 => x"70", + 2814 => x"55", + 2815 => x"70", + 2816 => x"55", + 2817 => x"27", + 2818 => x"14", + 2819 => x"06", + 2820 => x"74", + 2821 => x"73", + 2822 => x"38", + 2823 => x"51", + 2824 => x"82", + 2825 => x"14", + 2826 => x"05", + 2827 => x"08", + 2828 => x"54", + 2829 => x"39", + 2830 => x"86", + 2831 => x"81", + 2832 => x"79", + 2833 => x"74", + 2834 => x"0c", + 2835 => x"04", + 2836 => x"7a", + 2837 => x"80", + 2838 => x"58", + 2839 => x"33", + 2840 => x"a0", + 2841 => x"06", + 2842 => x"13", + 2843 => x"39", + 2844 => x"09", + 2845 => x"38", + 2846 => x"11", + 2847 => x"08", + 2848 => x"54", + 2849 => x"2e", + 2850 => x"80", + 2851 => x"08", + 2852 => x"0c", + 2853 => x"33", + 2854 => x"80", + 2855 => x"38", + 2856 => x"80", + 2857 => x"38", + 2858 => x"57", + 2859 => x"0c", + 2860 => x"33", + 2861 => x"39", + 2862 => x"74", + 2863 => x"38", + 2864 => x"80", + 2865 => x"89", + 2866 => x"38", + 2867 => x"d0", + 2868 => x"55", + 2869 => x"80", + 2870 => x"39", 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x"34", + 2930 => x"06", + 2931 => x"76", + 2932 => x"3f", + 2933 => x"86", + 2934 => x"f6", + 2935 => x"02", + 2936 => x"05", + 2937 => x"05", + 2938 => x"82", + 2939 => x"70", + 2940 => x"84", + 2941 => x"51", + 2942 => x"58", + 2943 => x"2e", + 2944 => x"51", + 2945 => x"82", + 2946 => x"70", + 2947 => x"84", + 2948 => x"1a", + 2949 => x"51", + 2950 => x"88", + 2951 => x"ec", + 2952 => x"82", + 2953 => x"70", + 2954 => x"84", + 2955 => x"51", + 2956 => x"80", + 2957 => x"75", + 2958 => x"74", + 2959 => x"da", + 2960 => x"c4", + 2961 => x"55", + 2962 => x"c4", + 2963 => x"ff", + 2964 => x"75", + 2965 => x"80", + 2966 => x"c4", + 2967 => x"2e", + 2968 => x"85", + 2969 => x"75", + 2970 => x"38", + 2971 => x"33", + 2972 => x"38", + 2973 => x"05", + 2974 => x"78", + 2975 => x"80", + 2976 => x"82", + 2977 => x"52", + 2978 => x"8a", + 2979 => x"85", + 2980 => x"80", + 2981 => x"8c", + 2982 => x"fd", + 2983 => x"84", + 2984 => x"54", + 2985 => x"71", + 2986 => x"38", + 2987 => x"dd", + 2988 => x"0c", + 2989 => x"14", + 2990 => x"80", + 2991 => x"80", + 2992 => x"c4", + 2993 => x"c0", + 2994 => x"80", + 2995 => x"71", + 2996 => x"dc", + 2997 => x"c0", + 2998 => x"b1", + 2999 => x"82", + 3000 => x"85", + 3001 => x"dc", + 3002 => x"57", + 3003 => x"85", + 3004 => x"80", + 3005 => x"82", + 3006 => x"80", + 3007 => x"85", + 3008 => x"80", + 3009 => x"3d", + 3010 => x"81", + 3011 => x"82", + 3012 => x"80", + 3013 => x"75", + 3014 => x"9e", + 3015 => x"ec", + 3016 => x"0b", + 3017 => x"08", + 3018 => x"82", + 3019 => x"ff", + 3020 => x"55", + 3021 => x"34", + 3022 => x"52", + 3023 => x"fd", + 3024 => x"f6", + 3025 => x"ff", + 3026 => x"06", + 3027 => x"a6", + 3028 => x"d9", + 3029 => x"3d", + 3030 => x"08", + 3031 => x"70", + 3032 => x"52", + 3033 => x"08", + 3034 => x"d2", + 3035 => x"ec", + 3036 => x"38", + 3037 => x"85", + 3038 => x"55", + 3039 => x"8b", + 3040 => x"56", + 3041 => x"3f", + 3042 => x"08", + 3043 => x"38", + 3044 => x"b4", + 3045 => x"85", + 3046 => x"18", + 3047 => x"0b", + 3048 => x"08", + 3049 => x"82", + 3050 => x"ff", + 3051 => x"55", + 3052 => x"34", + 3053 => x"09", + 3054 => x"72", + 3055 => x"51", + 3056 => x"77", + 3057 => x"73", + 3058 => x"82", + 3059 => x"8c", + 3060 => x"51", + 3061 => x"3f", + 3062 => x"08", + 3063 => x"38", + 3064 => x"51", + 3065 => x"78", + 3066 => x"81", + 3067 => x"75", + 3068 => x"ff", + 3069 => x"79", + 3070 => x"be", + 3071 => x"08", + 3072 => x"ec", + 3073 => x"80", + 3074 => x"85", + 3075 => x"3d", + 3076 => x"3d", + 3077 => x"71", + 3078 => x"33", + 3079 => x"58", + 3080 => x"09", + 3081 => x"38", + 3082 => x"05", + 3083 => x"27", + 3084 => x"17", + 3085 => x"71", + 3086 => x"55", + 3087 => x"09", + 3088 => x"38", + 3089 => x"ea", + 3090 => x"74", + 3091 => x"85", + 3092 => x"08", + 3093 => x"ff", + 3094 => x"82", + 3095 => x"53", + 3096 => x"08", + 3097 => x"df", + 3098 => x"ec", + 3099 => x"38", + 3100 => x"54", + 3101 => x"88", + 3102 => x"2e", + 3103 => x"39", + 3104 => x"be", + 3105 => x"5a", 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x"08", + 3165 => x"82", + 3166 => x"25", + 3167 => x"85", + 3168 => x"05", + 3169 => x"55", + 3170 => x"80", + 3171 => x"ff", + 3172 => x"51", + 3173 => x"81", + 3174 => x"ff", + 3175 => x"93", + 3176 => x"38", + 3177 => x"ff", + 3178 => x"06", + 3179 => x"86", + 3180 => x"85", + 3181 => x"8c", + 3182 => x"c0", + 3183 => x"84", + 3184 => x"3f", + 3185 => x"e0", + 3186 => x"85", + 3187 => x"2b", + 3188 => x"51", + 3189 => x"2e", + 3190 => x"81", + 3191 => x"9d", + 3192 => x"98", + 3193 => x"2c", + 3194 => x"33", + 3195 => x"70", + 3196 => x"98", + 3197 => x"82", + 3198 => x"f4", + 3199 => x"70", + 3200 => x"51", + 3201 => x"51", + 3202 => x"81", + 3203 => x"2e", + 3204 => x"77", + 3205 => x"38", + 3206 => x"98", + 3207 => x"2c", + 3208 => x"80", + 3209 => x"cb", + 3210 => x"74", + 3211 => x"f6", + 3212 => x"85", + 3213 => x"ff", + 3214 => x"80", + 3215 => x"74", + 3216 => x"34", + 3217 => x"39", + 3218 => x"98", + 3219 => x"2c", + 3220 => x"06", + 3221 => x"54", + 3222 => x"97", + 3223 => x"74", + 3224 => x"f5", + 3225 => x"85", + 3226 => x"ff", + 3227 => x"cf", + 3228 => x"80", + 3229 => x"2e", + 3230 => x"81", + 3231 => x"82", + 3232 => x"73", + 3233 => x"98", + 3234 => x"80", + 3235 => x"2b", + 3236 => x"70", + 3237 => x"82", + 3238 => x"f8", + 3239 => x"52", + 3240 => x"58", + 3241 => x"77", + 3242 => x"06", + 3243 => x"81", + 3244 => x"08", + 3245 => x"0b", + 3246 => x"34", + 3247 => x"9d", + 3248 => x"39", + 3249 => x"84", + 3250 => x"9d", + 3251 => x"af", + 3252 => x"7d", + 3253 => x"73", + 3254 => x"e8", + 3255 => x"2b", + 3256 => x"f0", + 3257 => x"82", + 3258 => x"56", + 3259 => x"fd", + 3260 => x"9d", + 3261 => x"75", + 3262 => x"38", + 3263 => x"70", + 3264 => x"55", + 3265 => x"9e", + 3266 => x"54", + 3267 => x"15", + 3268 => x"70", + 3269 => x"98", + 3270 => x"8c", + 3271 => x"56", + 3272 => x"25", + 3273 => x"9d", + 3274 => x"11", + 3275 => x"82", + 3276 => x"73", + 3277 => x"3d", + 3278 => x"82", + 3279 => x"54", + 3280 => x"89", + 3281 => x"54", + 3282 => x"88", + 3283 => x"8c", + 3284 => x"70", + 3285 => x"98", + 3286 => x"88", + 3287 => x"56", + 3288 => x"25", + 3289 => x"1a", + 3290 => x"54", + 3291 => x"81", + 3292 => x"2b", + 3293 => x"82", + 3294 => x"5a", + 3295 => x"76", + 3296 => x"38", + 3297 => x"33", + 3298 => x"70", + 3299 => x"9d", + 3300 => x"51", + 3301 => x"76", + 3302 => x"38", + 3303 => x"ef", + 3304 => x"70", + 3305 => x"98", + 3306 => x"88", + 3307 => x"56", + 3308 => x"24", + 3309 => x"8c", + 3310 => x"34", + 3311 => x"1b", + 3312 => x"8c", + 3313 => x"81", + 3314 => x"f3", + 3315 => x"d9", + 3316 => x"8c", + 3317 => x"ff", + 3318 => x"73", + 3319 => x"e4", + 3320 => x"88", + 3321 => x"54", + 3322 => x"88", + 3323 => x"54", + 3324 => x"8c", + 3325 => x"e6", + 3326 => x"9d", + 3327 => x"98", + 3328 => x"2c", + 3329 => x"33", + 3330 => x"57", + 3331 => x"a4", + 3332 => x"54", + 3333 => x"74", + 3334 => x"51", + 3335 => x"81", + 3336 => x"2b", + 3337 => x"82", + 3338 => x"59", + 3339 => x"75", + 3340 => x"38", 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x"98", + 3400 => x"88", + 3401 => x"56", + 3402 => x"24", + 3403 => x"51", + 3404 => x"82", + 3405 => x"70", + 3406 => x"98", + 3407 => x"88", + 3408 => x"56", + 3409 => x"24", + 3410 => x"88", + 3411 => x"3f", + 3412 => x"98", + 3413 => x"2c", + 3414 => x"33", + 3415 => x"54", + 3416 => x"e7", + 3417 => x"39", + 3418 => x"33", + 3419 => x"06", + 3420 => x"33", + 3421 => x"74", + 3422 => x"c8", + 3423 => x"54", + 3424 => x"8c", + 3425 => x"70", + 3426 => x"e3", + 3427 => x"9d", + 3428 => x"81", + 3429 => x"9d", + 3430 => x"56", + 3431 => x"26", + 3432 => x"a0", + 3433 => x"8c", + 3434 => x"81", + 3435 => x"ef", + 3436 => x"0b", + 3437 => x"34", + 3438 => x"9d", + 3439 => x"84", + 3440 => x"38", + 3441 => x"08", + 3442 => x"2e", + 3443 => x"51", + 3444 => x"3f", + 3445 => x"08", + 3446 => x"34", + 3447 => x"08", + 3448 => x"81", + 3449 => x"52", + 3450 => x"a9", + 3451 => x"5b", + 3452 => x"7a", + 3453 => x"84", + 3454 => x"11", + 3455 => x"54", + 3456 => x"a7", + 3457 => x"ff", + 3458 => x"82", + 3459 => x"82", + 3460 => x"82", + 3461 => x"81", + 3462 => x"05", + 3463 => x"79", + 3464 => x"f6", + 3465 => x"54", + 3466 => x"73", + 3467 => x"80", + 3468 => x"38", + 3469 => x"a7", + 3470 => x"39", + 3471 => x"09", + 3472 => x"38", + 3473 => x"08", + 3474 => x"2e", + 3475 => x"51", + 3476 => x"3f", + 3477 => x"08", + 3478 => x"34", + 3479 => x"08", + 3480 => x"81", + 3481 => x"52", + 3482 => x"a8", + 3483 => x"c2", + 3484 => x"2b", + 3485 => x"11", + 3486 => x"74", + 3487 => x"38", + 3488 => x"a6", + 3489 => x"85", + 3490 => x"9d", + 3491 => x"85", + 3492 => x"ff", + 3493 => x"53", + 3494 => x"51", + 3495 => x"3f", + 3496 => x"73", + 3497 => x"5b", + 3498 => x"82", + 3499 => x"74", + 3500 => x"9d", + 3501 => x"9d", + 3502 => x"79", + 3503 => x"3f", + 3504 => x"82", + 3505 => x"70", + 3506 => x"82", + 3507 => x"59", + 3508 => x"77", + 3509 => x"38", + 3510 => x"73", + 3511 => x"34", + 3512 => x"33", + 3513 => x"a7", + 3514 => x"39", + 3515 => x"33", + 3516 => x"2e", + 3517 => x"88", + 3518 => x"3f", + 3519 => x"33", + 3520 => x"73", + 3521 => x"34", + 3522 => x"f9", + 3523 => x"df", + 3524 => x"85", + 3525 => x"80", + 3526 => x"e0", + 3527 => x"53", + 3528 => x"df", + 3529 => x"aa", + 3530 => x"85", + 3531 => x"80", + 3532 => x"34", + 3533 => x"81", + 3534 => x"85", + 3535 => x"77", + 3536 => x"76", + 3537 => x"82", + 3538 => x"54", + 3539 => x"34", + 3540 => x"34", + 3541 => x"08", + 3542 => x"22", + 3543 => x"80", + 3544 => x"83", + 3545 => x"70", + 3546 => x"51", + 3547 => x"88", + 3548 => x"89", + 3549 => x"85", + 3550 => x"83", + 3551 => x"e4", + 3552 => x"05", + 3553 => x"77", + 3554 => x"76", + 3555 => x"89", + 3556 => x"ff", + 3557 => x"52", + 3558 => x"72", + 3559 => x"fb", + 3560 => x"82", + 3561 => x"ff", + 3562 => x"51", + 3563 => x"85", + 3564 => x"3d", + 3565 => x"3d", + 3566 => x"05", + 3567 => x"05", + 3568 => x"71", + 3569 => x"e4", + 3570 => x"2b", + 3571 => x"83", + 3572 => x"70", + 3573 => x"33", + 3574 => x"07", + 3575 => x"ae", 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x"70", + 3635 => x"33", + 3636 => x"07", + 3637 => x"ff", + 3638 => x"2a", + 3639 => x"53", + 3640 => x"34", + 3641 => x"34", + 3642 => x"04", + 3643 => x"02", + 3644 => x"82", + 3645 => x"71", + 3646 => x"11", + 3647 => x"12", + 3648 => x"2b", + 3649 => x"2b", + 3650 => x"55", + 3651 => x"70", + 3652 => x"33", + 3653 => x"71", + 3654 => x"53", + 3655 => x"55", + 3656 => x"80", + 3657 => x"51", + 3658 => x"82", + 3659 => x"70", + 3660 => x"81", + 3661 => x"8b", + 3662 => x"2b", + 3663 => x"70", + 3664 => x"33", + 3665 => x"07", + 3666 => x"8f", + 3667 => x"51", + 3668 => x"53", + 3669 => x"72", + 3670 => x"2a", + 3671 => x"82", + 3672 => x"83", + 3673 => x"85", + 3674 => x"17", + 3675 => x"12", + 3676 => x"2b", + 3677 => x"07", + 3678 => x"55", + 3679 => x"33", + 3680 => x"71", + 3681 => x"70", + 3682 => x"06", + 3683 => x"57", + 3684 => x"52", + 3685 => x"71", + 3686 => x"89", + 3687 => x"fb", + 3688 => x"85", + 3689 => x"84", + 3690 => x"22", + 3691 => x"72", + 3692 => x"33", + 3693 => x"71", + 3694 => x"83", + 3695 => x"5b", + 3696 => x"52", + 3697 => x"33", + 3698 => x"71", + 3699 => x"02", + 3700 => x"05", + 3701 => x"70", + 3702 => x"51", + 3703 => x"71", + 3704 => x"81", + 3705 => x"85", + 3706 => x"15", + 3707 => x"12", + 3708 => x"2b", + 3709 => x"07", + 3710 => x"52", + 3711 => x"12", + 3712 => x"33", + 3713 => x"07", + 3714 => x"54", + 3715 => x"70", + 3716 => x"72", + 3717 => x"82", + 3718 => x"14", + 3719 => x"83", + 3720 => x"88", + 3721 => x"85", + 3722 => x"54", + 3723 => x"04", + 3724 => x"7b", + 3725 => x"08", + 3726 => x"70", + 3727 => x"06", + 3728 => x"53", + 3729 => x"82", + 3730 => x"76", + 3731 => x"11", + 3732 => x"83", + 3733 => x"8b", + 3734 => x"2b", + 3735 => x"70", + 3736 => x"33", + 3737 => x"71", + 3738 => x"53", + 3739 => x"53", + 3740 => x"59", + 3741 => x"25", + 3742 => x"80", + 3743 => x"51", + 3744 => x"81", + 3745 => x"14", + 3746 => x"33", + 3747 => x"71", + 3748 => x"76", + 3749 => x"2a", + 3750 => x"58", + 3751 => x"14", + 3752 => x"ff", + 3753 => x"87", + 3754 => x"85", + 3755 => x"19", + 3756 => x"85", + 3757 => x"88", + 3758 => x"88", + 3759 => x"5b", + 3760 => x"84", + 3761 => x"85", + 3762 => x"85", + 3763 => x"53", + 3764 => x"14", + 3765 => x"87", + 3766 => x"85", + 3767 => x"76", + 3768 => x"75", + 3769 => x"82", + 3770 => x"18", + 3771 => x"12", + 3772 => x"2b", + 3773 => x"80", + 3774 => x"88", + 3775 => x"55", + 3776 => x"74", + 3777 => x"15", + 3778 => x"0d", + 3779 => x"0d", + 3780 => x"85", + 3781 => x"38", + 3782 => x"71", + 3783 => x"38", + 3784 => x"8c", + 3785 => x"0d", + 3786 => x"0d", + 3787 => x"58", + 3788 => x"82", + 3789 => x"83", + 3790 => x"82", + 3791 => x"84", + 3792 => x"12", + 3793 => x"2b", + 3794 => x"59", + 3795 => x"81", + 3796 => x"75", + 3797 => x"cc", + 3798 => x"2b", + 3799 => x"33", + 3800 => x"71", + 3801 => x"70", + 3802 => x"06", + 3803 => x"83", + 3804 => x"70", + 3805 => x"53", + 3806 => x"55", + 3807 => x"8a", + 3808 => x"2e", + 3809 => x"78", + 3810 => x"15", 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x"1d", + 3870 => x"85", + 3871 => x"88", + 3872 => x"88", + 3873 => x"5f", + 3874 => x"73", + 3875 => x"75", + 3876 => x"82", + 3877 => x"1b", + 3878 => x"73", + 3879 => x"0c", + 3880 => x"04", + 3881 => x"74", + 3882 => x"e4", + 3883 => x"f4", + 3884 => x"53", + 3885 => x"8b", + 3886 => x"fc", + 3887 => x"85", + 3888 => x"72", + 3889 => x"0c", + 3890 => x"04", + 3891 => x"02", + 3892 => x"51", + 3893 => x"72", + 3894 => x"82", + 3895 => x"33", + 3896 => x"85", + 3897 => x"3d", + 3898 => x"3d", + 3899 => x"05", + 3900 => x"05", + 3901 => x"56", + 3902 => x"72", + 3903 => x"e0", + 3904 => x"2b", + 3905 => x"8c", + 3906 => x"88", + 3907 => x"2e", + 3908 => x"88", + 3909 => x"0c", + 3910 => x"8c", + 3911 => x"71", + 3912 => x"87", + 3913 => x"0c", + 3914 => x"08", + 3915 => x"51", + 3916 => x"2e", + 3917 => x"c0", + 3918 => x"51", + 3919 => x"71", + 3920 => x"80", + 3921 => x"92", + 3922 => x"98", + 3923 => x"70", + 3924 => x"38", + 3925 => x"e8", + 3926 => x"85", + 3927 => x"51", + 3928 => x"ec", + 3929 => x"0d", + 3930 => x"0d", + 3931 => x"02", + 3932 => x"05", + 3933 => x"58", + 3934 => x"52", + 3935 => x"3f", + 3936 => x"08", + 3937 => x"54", + 3938 => x"be", + 3939 => x"75", + 3940 => x"c0", + 3941 => x"87", + 3942 => x"12", + 3943 => x"84", + 3944 => x"40", + 3945 => x"85", + 3946 => x"98", + 3947 => x"7d", + 3948 => x"0c", + 3949 => x"85", + 3950 => x"06", + 3951 => x"71", + 3952 => x"38", + 3953 => x"71", + 3954 => x"05", + 3955 => x"19", + 3956 => x"a2", + 3957 => x"71", + 3958 => x"38", + 3959 => x"83", + 3960 => x"38", + 3961 => x"8a", + 3962 => x"98", + 3963 => x"71", + 3964 => x"c0", + 3965 => x"52", + 3966 => x"87", + 3967 => x"80", + 3968 => x"81", + 3969 => x"c0", + 3970 => x"53", + 3971 => x"82", + 3972 => x"71", + 3973 => x"1a", + 3974 => x"84", + 3975 => x"19", + 3976 => x"06", + 3977 => x"79", + 3978 => x"38", + 3979 => x"80", + 3980 => x"87", + 3981 => x"26", + 3982 => x"73", + 3983 => x"06", + 3984 => x"2e", + 3985 => x"52", + 3986 => x"82", + 3987 => x"8f", + 3988 => x"f3", + 3989 => x"62", + 3990 => x"05", + 3991 => x"57", + 3992 => x"83", + 3993 => x"52", + 3994 => x"3f", + 3995 => x"08", + 3996 => x"54", + 3997 => x"2e", + 3998 => x"81", + 3999 => x"74", + 4000 => x"c0", + 4001 => x"87", + 4002 => x"12", + 4003 => x"84", + 4004 => x"5f", + 4005 => x"0b", + 4006 => x"8c", + 4007 => x"0c", + 4008 => x"80", + 4009 => x"70", + 4010 => x"81", + 4011 => x"54", + 4012 => x"8c", + 4013 => x"81", + 4014 => x"7c", + 4015 => x"58", + 4016 => x"70", + 4017 => x"52", + 4018 => x"8a", + 4019 => x"98", + 4020 => x"71", + 4021 => x"c0", + 4022 => x"52", + 4023 => x"87", + 4024 => x"80", + 4025 => x"81", + 4026 => x"c0", + 4027 => x"53", + 4028 => x"82", + 4029 => x"71", + 4030 => x"19", + 4031 => x"81", + 4032 => x"ff", + 4033 => x"19", + 4034 => x"78", + 4035 => x"38", + 4036 => x"80", + 4037 => x"87", + 4038 => x"26", + 4039 => x"73", + 4040 => x"06", + 4041 => x"2e", + 4042 => x"52", + 4043 => x"82", + 4044 => x"8f", + 4045 => x"fa", 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x"04", + 4105 => x"73", + 4106 => x"92", + 4107 => x"52", + 4108 => x"81", + 4109 => x"70", + 4110 => x"70", + 4111 => x"3d", + 4112 => x"3d", + 4113 => x"52", + 4114 => x"70", + 4115 => x"34", + 4116 => x"51", + 4117 => x"81", + 4118 => x"70", + 4119 => x"70", + 4120 => x"05", + 4121 => x"88", + 4122 => x"72", + 4123 => x"0d", + 4124 => x"0d", + 4125 => x"54", + 4126 => x"80", + 4127 => x"71", + 4128 => x"53", + 4129 => x"81", + 4130 => x"ff", + 4131 => x"39", + 4132 => x"04", + 4133 => x"75", + 4134 => x"52", + 4135 => x"70", + 4136 => x"34", + 4137 => x"70", + 4138 => x"3d", + 4139 => x"3d", + 4140 => x"79", + 4141 => x"74", + 4142 => x"56", + 4143 => x"81", + 4144 => x"71", + 4145 => x"16", + 4146 => x"52", + 4147 => x"86", + 4148 => x"2e", + 4149 => x"82", + 4150 => x"86", + 4151 => x"fe", + 4152 => x"76", + 4153 => x"39", + 4154 => x"8a", + 4155 => x"51", + 4156 => x"71", + 4157 => x"33", + 4158 => x"0c", + 4159 => x"04", + 4160 => x"85", + 4161 => x"80", + 4162 => x"ec", + 4163 => x"3d", + 4164 => x"80", + 4165 => x"33", + 4166 => x"7a", + 4167 => x"38", + 4168 => x"16", + 4169 => x"16", + 4170 => x"17", + 4171 => x"fa", + 4172 => x"85", + 4173 => x"2e", + 4174 => x"b7", + 4175 => x"ec", + 4176 => x"34", + 4177 => x"70", + 4178 => x"31", + 4179 => x"59", + 4180 => x"77", + 4181 => x"82", + 4182 => x"74", + 4183 => x"81", + 4184 => x"81", + 4185 => x"53", + 4186 => x"16", + 4187 => x"e3", + 4188 => x"81", + 4189 => x"85", + 4190 => x"3d", + 4191 => x"3d", + 4192 => x"56", + 4193 => x"74", + 4194 => x"2e", + 4195 => x"51", + 4196 => x"82", + 4197 => x"57", + 4198 => x"08", + 4199 => x"54", + 4200 => x"16", + 4201 => x"33", + 4202 => x"3f", + 4203 => x"08", + 4204 => x"38", + 4205 => x"57", + 4206 => x"0c", + 4207 => x"ec", + 4208 => x"0d", + 4209 => x"0d", + 4210 => x"57", + 4211 => x"82", + 4212 => x"58", + 4213 => x"08", + 4214 => x"76", + 4215 => x"83", + 4216 => x"06", + 4217 => x"84", + 4218 => x"78", + 4219 => x"81", + 4220 => x"38", + 4221 => x"82", + 4222 => x"52", + 4223 => x"52", + 4224 => x"3f", + 4225 => x"52", + 4226 => x"51", + 4227 => x"84", + 4228 => x"d2", + 4229 => x"fc", + 4230 => x"8a", + 4231 => x"52", + 4232 => x"51", + 4233 => x"90", + 4234 => x"84", + 4235 => x"fc", + 4236 => x"17", + 4237 => x"a0", + 4238 => x"86", + 4239 => x"08", + 4240 => x"b0", + 4241 => x"55", + 4242 => x"81", + 4243 => x"f8", + 4244 => x"84", + 4245 => x"53", + 4246 => x"17", + 4247 => x"d7", + 4248 => x"ec", + 4249 => x"83", + 4250 => x"77", + 4251 => x"0c", + 4252 => x"04", + 4253 => x"77", + 4254 => x"12", + 4255 => x"55", + 4256 => x"56", + 4257 => x"94", + 4258 => x"22", + 4259 => x"ff", + 4260 => x"ac", + 4261 => x"85", + 4262 => x"56", + 4263 => x"ec", + 4264 => x"0d", + 4265 => x"0d", + 4266 => x"08", + 4267 => x"81", + 4268 => x"df", + 4269 => x"15", + 4270 => x"d7", + 4271 => x"33", + 4272 => x"82", + 4273 => x"38", + 4274 => x"89", + 4275 => x"2e", + 4276 => x"bf", + 4277 => x"2e", + 4278 => x"81", + 4279 => x"81", + 4280 => x"89", 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x"2e", + 4340 => x"81", + 4341 => x"81", + 4342 => x"89", + 4343 => x"08", + 4344 => x"52", + 4345 => x"3f", + 4346 => x"08", + 4347 => x"ec", + 4348 => x"38", + 4349 => x"06", + 4350 => x"81", + 4351 => x"06", + 4352 => x"77", + 4353 => x"2e", + 4354 => x"84", + 4355 => x"06", + 4356 => x"06", + 4357 => x"53", + 4358 => x"81", + 4359 => x"34", + 4360 => x"a4", + 4361 => x"52", + 4362 => x"d2", + 4363 => x"ec", + 4364 => x"85", + 4365 => x"94", + 4366 => x"ff", + 4367 => x"05", + 4368 => x"54", + 4369 => x"38", + 4370 => x"74", + 4371 => x"06", + 4372 => x"07", + 4373 => x"74", + 4374 => x"39", + 4375 => x"a4", + 4376 => x"52", + 4377 => x"96", + 4378 => x"ec", + 4379 => x"85", + 4380 => x"d8", + 4381 => x"ff", + 4382 => x"76", + 4383 => x"06", + 4384 => x"05", + 4385 => x"3f", + 4386 => x"87", + 4387 => x"08", + 4388 => x"51", + 4389 => x"82", + 4390 => x"59", + 4391 => x"08", + 4392 => x"f0", + 4393 => x"82", + 4394 => x"06", + 4395 => x"05", + 4396 => x"54", + 4397 => x"3f", + 4398 => x"08", + 4399 => x"74", + 4400 => x"51", + 4401 => x"81", + 4402 => x"34", + 4403 => x"ec", + 4404 => x"0d", + 4405 => x"0d", + 4406 => x"72", + 4407 => x"56", + 4408 => x"27", + 4409 => x"98", + 4410 => x"9d", + 4411 => x"2e", + 4412 => x"53", + 4413 => x"51", + 4414 => x"82", + 4415 => x"54", + 4416 => x"08", + 4417 => x"93", + 4418 => x"80", + 4419 => x"54", + 4420 => x"82", + 4421 => x"54", + 4422 => x"74", + 4423 => x"fb", + 4424 => x"85", + 4425 => x"82", + 4426 => x"80", + 4427 => x"38", + 4428 => x"08", + 4429 => x"38", + 4430 => x"08", + 4431 => x"38", + 4432 => x"52", + 4433 => x"d6", + 4434 => x"ec", + 4435 => x"98", + 4436 => x"11", + 4437 => x"57", + 4438 => x"74", + 4439 => x"81", + 4440 => x"0c", + 4441 => x"81", + 4442 => x"84", + 4443 => x"55", + 4444 => x"ff", + 4445 => x"54", + 4446 => x"ec", + 4447 => x"0d", + 4448 => x"0d", + 4449 => x"08", + 4450 => x"79", + 4451 => x"17", + 4452 => x"80", + 4453 => x"98", + 4454 => x"26", + 4455 => x"58", + 4456 => x"52", + 4457 => x"fd", + 4458 => x"74", + 4459 => x"08", + 4460 => x"38", + 4461 => x"08", + 4462 => x"ec", + 4463 => x"82", + 4464 => x"17", + 4465 => x"ec", + 4466 => x"cd", + 4467 => x"90", + 4468 => x"56", + 4469 => x"2e", + 4470 => x"77", + 4471 => x"81", + 4472 => x"38", + 4473 => x"98", + 4474 => x"26", + 4475 => x"56", + 4476 => x"51", + 4477 => x"80", + 4478 => x"ec", + 4479 => x"09", + 4480 => x"38", + 4481 => x"08", + 4482 => x"ec", + 4483 => x"09", + 4484 => x"72", + 4485 => x"70", + 4486 => x"85", + 4487 => x"51", + 4488 => x"73", + 4489 => x"82", + 4490 => x"80", + 4491 => x"8c", + 4492 => x"81", + 4493 => x"38", + 4494 => x"08", + 4495 => x"73", + 4496 => x"75", + 4497 => x"77", + 4498 => x"56", + 4499 => x"76", + 4500 => x"82", + 4501 => x"26", + 4502 => x"75", + 4503 => x"f8", + 4504 => x"85", + 4505 => x"2e", + 4506 => x"59", + 4507 => x"08", + 4508 => x"81", + 4509 => x"82", + 4510 => x"59", + 4511 => x"08", + 4512 => x"81", + 4513 => x"07", + 4514 => x"7c", + 4515 => x"55", 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x"08", + 4575 => x"38", + 4576 => x"76", + 4577 => x"81", + 4578 => x"07", + 4579 => x"53", + 4580 => x"75", + 4581 => x"0c", + 4582 => x"04", + 4583 => x"7a", + 4584 => x"58", + 4585 => x"f0", + 4586 => x"80", + 4587 => x"9f", + 4588 => x"80", + 4589 => x"90", + 4590 => x"17", + 4591 => x"aa", + 4592 => x"53", + 4593 => x"88", + 4594 => x"08", + 4595 => x"38", + 4596 => x"53", + 4597 => x"17", + 4598 => x"72", + 4599 => x"fe", + 4600 => x"08", + 4601 => x"80", + 4602 => x"16", + 4603 => x"2b", + 4604 => x"75", + 4605 => x"73", + 4606 => x"f5", + 4607 => x"85", + 4608 => x"82", + 4609 => x"ff", + 4610 => x"81", + 4611 => x"ec", + 4612 => x"38", + 4613 => x"82", + 4614 => x"26", + 4615 => x"58", + 4616 => x"73", + 4617 => x"39", + 4618 => x"51", + 4619 => x"82", + 4620 => x"98", + 4621 => x"94", + 4622 => x"17", + 4623 => x"58", + 4624 => x"9a", + 4625 => x"81", + 4626 => x"74", + 4627 => x"98", + 4628 => x"83", + 4629 => x"b4", + 4630 => x"0c", + 4631 => x"82", + 4632 => x"8a", + 4633 => x"f8", + 4634 => x"70", + 4635 => x"08", + 4636 => x"57", + 4637 => x"0a", + 4638 => x"38", + 4639 => x"15", + 4640 => x"08", + 4641 => x"72", + 4642 => x"cb", + 4643 => x"ff", + 4644 => x"81", + 4645 => x"13", + 4646 => x"94", + 4647 => x"74", + 4648 => x"85", + 4649 => x"22", + 4650 => x"73", + 4651 => x"38", + 4652 => x"8a", + 4653 => x"05", + 4654 => x"06", + 4655 => x"8a", + 4656 => x"73", + 4657 => x"3f", + 4658 => x"08", + 4659 => x"81", + 4660 => x"ec", + 4661 => x"ff", + 4662 => x"82", + 4663 => x"ff", + 4664 => x"38", + 4665 => x"82", + 4666 => x"26", + 4667 => x"7b", + 4668 => x"98", + 4669 => x"55", + 4670 => x"94", + 4671 => x"73", + 4672 => x"3f", + 4673 => x"08", + 4674 => x"82", + 4675 => x"80", + 4676 => x"38", + 4677 => x"85", + 4678 => x"2e", + 4679 => x"55", + 4680 => x"08", + 4681 => x"38", + 4682 => x"08", + 4683 => x"fb", + 4684 => x"85", + 4685 => x"38", + 4686 => x"0c", + 4687 => x"51", + 4688 => x"82", + 4689 => x"98", + 4690 => x"90", + 4691 => x"16", + 4692 => x"15", + 4693 => x"74", + 4694 => x"0c", + 4695 => x"04", + 4696 => x"7b", + 4697 => x"5b", + 4698 => x"52", + 4699 => x"ac", + 4700 => x"ec", + 4701 => x"85", + 4702 => x"ec", + 4703 => x"ec", + 4704 => x"17", + 4705 => x"51", + 4706 => x"82", + 4707 => x"54", + 4708 => x"08", + 4709 => x"82", + 4710 => x"9c", + 4711 => x"33", + 4712 => x"72", + 4713 => x"09", + 4714 => x"38", + 4715 => x"85", + 4716 => x"72", + 4717 => x"55", + 4718 => x"53", + 4719 => x"8e", + 4720 => x"56", + 4721 => x"09", + 4722 => x"38", + 4723 => x"85", + 4724 => x"81", + 4725 => x"fd", + 4726 => x"85", + 4727 => x"82", + 4728 => x"80", + 4729 => x"38", + 4730 => x"09", + 4731 => x"38", + 4732 => x"82", + 4733 => x"8b", + 4734 => x"fd", + 4735 => x"9a", + 4736 => x"eb", + 4737 => x"85", + 4738 => x"ff", + 4739 => x"70", + 4740 => x"53", + 4741 => x"09", + 4742 => x"38", + 4743 => x"eb", + 4744 => x"85", + 4745 => x"2b", + 4746 => x"72", + 4747 => x"0c", + 4748 => x"04", + 4749 => x"77", + 4750 => x"ff", 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x"98", + 4810 => x"75", + 4811 => x"3f", + 4812 => x"08", + 4813 => x"ec", + 4814 => x"a0", + 4815 => x"ec", + 4816 => x"14", + 4817 => x"cc", + 4818 => x"a0", + 4819 => x"14", + 4820 => x"9d", + 4821 => x"83", + 4822 => x"82", + 4823 => x"87", + 4824 => x"fd", + 4825 => x"70", + 4826 => x"08", + 4827 => x"55", + 4828 => x"3f", + 4829 => x"08", + 4830 => x"13", + 4831 => x"73", + 4832 => x"83", + 4833 => x"3d", + 4834 => x"3d", + 4835 => x"57", + 4836 => x"89", + 4837 => x"17", + 4838 => x"81", + 4839 => x"70", + 4840 => x"55", + 4841 => x"08", + 4842 => x"81", + 4843 => x"52", + 4844 => x"a8", + 4845 => x"2e", + 4846 => x"84", + 4847 => x"52", + 4848 => x"09", + 4849 => x"38", + 4850 => x"81", + 4851 => x"81", + 4852 => x"73", + 4853 => x"55", + 4854 => x"55", + 4855 => x"c5", + 4856 => x"88", + 4857 => x"0b", + 4858 => x"9c", + 4859 => x"8b", + 4860 => x"17", + 4861 => x"08", + 4862 => x"52", + 4863 => x"82", + 4864 => x"76", + 4865 => x"51", + 4866 => x"82", + 4867 => x"86", + 4868 => x"12", + 4869 => x"3f", + 4870 => x"08", + 4871 => x"88", + 4872 => x"f3", + 4873 => x"70", + 4874 => x"80", + 4875 => x"51", + 4876 => x"af", + 4877 => x"81", + 4878 => x"dc", + 4879 => x"74", + 4880 => x"38", + 4881 => x"88", + 4882 => x"39", + 4883 => x"80", + 4884 => x"56", + 4885 => x"af", + 4886 => x"06", + 4887 => x"56", + 4888 => x"32", + 4889 => x"05", + 4890 => x"78", + 4891 => x"54", + 4892 => x"73", + 4893 => x"60", + 4894 => x"54", + 4895 => x"96", + 4896 => x"0b", + 4897 => x"80", + 4898 => x"f6", + 4899 => x"85", + 4900 => x"85", + 4901 => x"3d", + 4902 => x"5c", + 4903 => x"53", + 4904 => x"51", + 4905 => x"80", + 4906 => x"88", + 4907 => x"5c", + 4908 => x"09", + 4909 => x"d8", + 4910 => x"70", + 4911 => x"71", + 4912 => x"09", + 4913 => x"9f", + 4914 => x"26", + 4915 => x"53", + 4916 => x"73", + 4917 => x"17", + 4918 => x"34", + 4919 => x"d9", + 4920 => x"32", + 4921 => x"05", + 4922 => x"51", + 4923 => x"80", + 4924 => x"38", + 4925 => x"87", + 4926 => x"26", + 4927 => x"77", + 4928 => x"a4", + 4929 => x"27", + 4930 => x"a0", + 4931 => x"39", + 4932 => x"33", + 4933 => x"57", + 4934 => x"27", + 4935 => x"75", + 4936 => x"09", + 4937 => x"80", + 4938 => x"09", + 4939 => x"80", + 4940 => x"25", + 4941 => x"56", + 4942 => x"80", + 4943 => x"84", + 4944 => x"58", + 4945 => x"70", + 4946 => x"55", + 4947 => x"09", + 4948 => x"38", + 4949 => x"80", + 4950 => x"09", + 4951 => x"80", + 4952 => x"51", + 4953 => x"d9", + 4954 => x"39", + 4955 => x"09", + 4956 => x"38", + 4957 => x"7c", + 4958 => x"54", + 4959 => x"a6", + 4960 => x"32", + 4961 => x"05", + 4962 => x"70", + 4963 => x"72", + 4964 => x"9f", + 4965 => x"51", + 4966 => x"74", + 4967 => x"88", + 4968 => x"fe", + 4969 => x"98", + 4970 => x"80", + 4971 => x"75", + 4972 => x"81", + 4973 => x"33", + 4974 => x"51", + 4975 => x"82", + 4976 => x"80", + 4977 => x"78", + 4978 => x"81", + 4979 => x"5a", + 4980 => x"b3", + 4981 => x"ec", + 4982 => x"80", + 4983 => x"1c", + 4984 => x"27", + 4985 => x"79", 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x"e7", + 5045 => x"2a", + 5046 => x"77", + 5047 => x"51", + 5048 => x"2e", + 5049 => x"81", + 5050 => x"80", + 5051 => x"38", + 5052 => x"ab", + 5053 => x"55", + 5054 => x"75", + 5055 => x"73", + 5056 => x"55", + 5057 => x"82", + 5058 => x"06", + 5059 => x"ab", + 5060 => x"33", + 5061 => x"70", + 5062 => x"55", + 5063 => x"2e", + 5064 => x"1b", + 5065 => x"06", + 5066 => x"52", + 5067 => x"cb", + 5068 => x"ec", + 5069 => x"0c", + 5070 => x"74", + 5071 => x"0c", + 5072 => x"04", + 5073 => x"7c", + 5074 => x"08", + 5075 => x"55", + 5076 => x"59", + 5077 => x"81", + 5078 => x"70", + 5079 => x"33", + 5080 => x"52", + 5081 => x"2e", + 5082 => x"ee", + 5083 => x"2e", + 5084 => x"81", + 5085 => x"33", + 5086 => x"81", + 5087 => x"52", + 5088 => x"26", + 5089 => x"14", + 5090 => x"06", + 5091 => x"52", + 5092 => x"80", + 5093 => x"0b", + 5094 => x"59", + 5095 => x"7a", + 5096 => x"70", + 5097 => x"33", + 5098 => x"05", + 5099 => x"9f", + 5100 => x"53", + 5101 => x"89", + 5102 => x"70", + 5103 => x"54", + 5104 => x"12", + 5105 => x"26", + 5106 => x"12", + 5107 => x"06", + 5108 => x"09", + 5109 => x"9f", + 5110 => x"72", + 5111 => x"81", + 5112 => x"70", + 5113 => x"72", + 5114 => x"74", + 5115 => x"09", + 5116 => x"72", + 5117 => x"73", + 5118 => x"53", + 5119 => x"70", + 5120 => x"38", + 5121 => x"19", + 5122 => x"75", + 5123 => x"38", + 5124 => x"83", + 5125 => x"74", + 5126 => x"59", + 5127 => x"39", + 5128 => x"33", + 5129 => x"85", + 5130 => x"3d", + 5131 => x"3d", + 5132 => x"80", + 5133 => x"34", + 5134 => x"17", + 5135 => x"75", + 5136 => x"3f", + 5137 => x"85", + 5138 => x"82", + 5139 => x"16", + 5140 => x"3f", + 5141 => x"08", + 5142 => x"06", + 5143 => x"73", + 5144 => x"2e", + 5145 => x"80", + 5146 => x"0b", + 5147 => x"56", + 5148 => x"e9", + 5149 => x"06", + 5150 => x"57", + 5151 => x"32", + 5152 => x"05", + 5153 => x"79", + 5154 => x"54", + 5155 => x"74", + 5156 => x"09", + 5157 => x"38", + 5158 => x"fe", + 5159 => x"ea", + 5160 => x"8a", + 5161 => x"ec", + 5162 => x"85", + 5163 => x"2e", + 5164 => x"53", + 5165 => x"52", + 5166 => x"51", + 5167 => x"82", + 5168 => x"55", + 5169 => x"08", + 5170 => x"38", + 5171 => x"82", + 5172 => x"88", + 5173 => x"f1", + 5174 => x"02", + 5175 => x"cf", + 5176 => x"55", + 5177 => x"61", + 5178 => x"3f", + 5179 => x"08", + 5180 => x"80", + 5181 => x"ec", + 5182 => x"83", + 5183 => x"ec", + 5184 => x"82", + 5185 => x"08", + 5186 => x"56", + 5187 => x"86", + 5188 => x"75", + 5189 => x"fe", + 5190 => x"54", + 5191 => x"2e", + 5192 => x"14", + 5193 => x"a4", + 5194 => x"ec", + 5195 => x"06", + 5196 => x"54", + 5197 => x"38", + 5198 => x"86", + 5199 => x"82", + 5200 => x"06", + 5201 => x"56", + 5202 => x"38", + 5203 => x"80", + 5204 => x"81", + 5205 => x"52", + 5206 => x"51", + 5207 => x"82", + 5208 => x"81", + 5209 => x"81", + 5210 => x"83", + 5211 => x"8f", + 5212 => x"2e", + 5213 => x"82", + 5214 => x"06", + 5215 => x"56", + 5216 => x"38", + 5217 => x"74", + 5218 => x"a2", + 5219 => x"ec", + 5220 => x"06", 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x"23", + 5280 => x"8b", + 5281 => x"73", + 5282 => x"80", + 5283 => x"8d", + 5284 => x"39", + 5285 => x"51", + 5286 => x"82", + 5287 => x"53", + 5288 => x"08", + 5289 => x"72", + 5290 => x"8d", + 5291 => x"cf", + 5292 => x"14", + 5293 => x"3f", + 5294 => x"08", + 5295 => x"06", + 5296 => x"38", + 5297 => x"51", + 5298 => x"82", + 5299 => x"55", + 5300 => x"51", + 5301 => x"82", + 5302 => x"83", + 5303 => x"5a", + 5304 => x"80", + 5305 => x"38", + 5306 => x"78", + 5307 => x"2a", + 5308 => x"78", + 5309 => x"87", + 5310 => x"22", + 5311 => x"31", + 5312 => x"87", + 5313 => x"ec", + 5314 => x"85", + 5315 => x"2e", + 5316 => x"82", + 5317 => x"80", + 5318 => x"f5", + 5319 => x"83", + 5320 => x"ff", + 5321 => x"38", + 5322 => x"9f", + 5323 => x"38", + 5324 => x"39", + 5325 => x"80", + 5326 => x"38", + 5327 => x"98", + 5328 => x"a0", + 5329 => x"1d", + 5330 => x"0c", + 5331 => x"17", + 5332 => x"76", + 5333 => x"81", + 5334 => x"80", + 5335 => x"d9", + 5336 => x"85", + 5337 => x"ff", + 5338 => x"8d", + 5339 => x"8f", + 5340 => x"8b", + 5341 => x"14", + 5342 => x"3f", + 5343 => x"08", + 5344 => x"74", + 5345 => x"a3", + 5346 => x"7a", + 5347 => x"ef", + 5348 => x"a8", + 5349 => x"15", + 5350 => x"2e", + 5351 => x"10", + 5352 => x"2a", + 5353 => x"11", + 5354 => x"83", + 5355 => x"2a", + 5356 => x"72", + 5357 => x"26", + 5358 => x"ff", + 5359 => x"0c", + 5360 => x"15", + 5361 => x"0b", + 5362 => x"76", + 5363 => x"81", + 5364 => x"38", + 5365 => x"51", + 5366 => x"82", + 5367 => x"83", + 5368 => x"53", + 5369 => x"09", + 5370 => x"f9", + 5371 => x"52", + 5372 => x"8a", + 5373 => x"ec", + 5374 => x"38", + 5375 => x"08", + 5376 => x"84", + 5377 => x"d7", + 5378 => x"85", + 5379 => x"ff", + 5380 => x"72", + 5381 => x"2e", + 5382 => x"80", + 5383 => x"14", + 5384 => x"3f", + 5385 => x"08", + 5386 => x"a4", + 5387 => x"81", + 5388 => x"84", + 5389 => x"d7", + 5390 => x"85", + 5391 => x"8a", + 5392 => x"2e", + 5393 => x"9d", + 5394 => x"14", + 5395 => x"3f", + 5396 => x"08", + 5397 => x"84", + 5398 => x"d7", + 5399 => x"85", + 5400 => x"15", + 5401 => x"34", + 5402 => x"22", + 5403 => x"72", + 5404 => x"23", + 5405 => x"23", + 5406 => x"15", + 5407 => x"75", + 5408 => x"0c", + 5409 => x"04", + 5410 => x"77", + 5411 => x"73", + 5412 => x"38", + 5413 => x"72", + 5414 => x"38", + 5415 => x"71", + 5416 => x"38", + 5417 => x"84", + 5418 => x"52", + 5419 => x"09", + 5420 => x"38", + 5421 => x"51", + 5422 => x"82", + 5423 => x"81", + 5424 => x"88", + 5425 => x"08", + 5426 => x"39", + 5427 => x"73", + 5428 => x"74", + 5429 => x"0c", + 5430 => x"04", + 5431 => x"02", + 5432 => x"7a", + 5433 => x"fc", + 5434 => x"f4", + 5435 => x"54", + 5436 => x"85", + 5437 => x"bc", + 5438 => x"ec", + 5439 => x"82", + 5440 => x"70", + 5441 => x"73", + 5442 => x"38", + 5443 => x"78", + 5444 => x"2e", + 5445 => x"74", + 5446 => x"0c", + 5447 => x"80", + 5448 => x"80", + 5449 => x"70", + 5450 => x"51", + 5451 => x"82", + 5452 => x"54", + 5453 => x"ec", + 5454 => x"0d", + 5455 => x"0d", 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x"f1", + 5515 => x"11", + 5516 => x"80", + 5517 => x"97", + 5518 => x"51", + 5519 => x"82", + 5520 => x"55", + 5521 => x"08", + 5522 => x"b7", + 5523 => x"c6", + 5524 => x"05", + 5525 => x"2a", + 5526 => x"51", + 5527 => x"80", + 5528 => x"84", + 5529 => x"39", + 5530 => x"70", + 5531 => x"54", + 5532 => x"a9", + 5533 => x"06", + 5534 => x"2e", + 5535 => x"55", + 5536 => x"73", + 5537 => x"d5", + 5538 => x"85", + 5539 => x"ff", + 5540 => x"0c", + 5541 => x"85", + 5542 => x"fa", + 5543 => x"2a", + 5544 => x"51", + 5545 => x"2e", + 5546 => x"80", + 5547 => x"7a", + 5548 => x"a0", + 5549 => x"a4", + 5550 => x"53", + 5551 => x"e6", + 5552 => x"85", + 5553 => x"85", + 5554 => x"1b", + 5555 => x"05", + 5556 => x"a5", + 5557 => x"ec", + 5558 => x"ec", + 5559 => x"0c", + 5560 => x"56", + 5561 => x"84", + 5562 => x"90", + 5563 => x"0b", + 5564 => x"80", + 5565 => x"0c", + 5566 => x"1a", + 5567 => x"2a", + 5568 => x"51", + 5569 => x"2e", + 5570 => x"82", + 5571 => x"80", + 5572 => x"38", + 5573 => x"08", + 5574 => x"8a", + 5575 => x"89", + 5576 => x"59", + 5577 => x"76", + 5578 => x"d6", + 5579 => x"85", + 5580 => x"82", + 5581 => x"81", + 5582 => x"82", + 5583 => x"ec", + 5584 => x"09", + 5585 => x"38", + 5586 => x"78", + 5587 => x"09", + 5588 => x"76", + 5589 => x"51", + 5590 => x"27", + 5591 => x"70", + 5592 => x"5a", + 5593 => x"76", + 5594 => x"74", + 5595 => x"83", + 5596 => x"73", + 5597 => x"38", + 5598 => x"51", + 5599 => x"82", + 5600 => x"85", + 5601 => x"8e", + 5602 => x"2a", + 5603 => x"08", + 5604 => x"0c", + 5605 => x"79", + 5606 => x"73", + 5607 => x"0c", + 5608 => x"04", + 5609 => x"60", + 5610 => x"40", + 5611 => x"80", + 5612 => x"3d", + 5613 => x"78", + 5614 => x"3f", + 5615 => x"08", + 5616 => x"ec", + 5617 => x"91", + 5618 => x"74", + 5619 => x"38", + 5620 => x"c4", + 5621 => x"33", + 5622 => x"87", + 5623 => x"2e", + 5624 => x"95", + 5625 => x"91", + 5626 => x"56", + 5627 => x"81", + 5628 => x"34", + 5629 => x"a0", + 5630 => x"08", + 5631 => x"31", + 5632 => x"27", + 5633 => x"5c", + 5634 => x"82", + 5635 => x"19", + 5636 => x"ff", + 5637 => x"74", + 5638 => x"7e", + 5639 => x"ff", + 5640 => x"2a", + 5641 => x"79", + 5642 => x"87", + 5643 => x"08", + 5644 => x"98", + 5645 => x"78", + 5646 => x"3f", + 5647 => x"08", + 5648 => x"27", + 5649 => x"74", + 5650 => x"a3", + 5651 => x"1a", + 5652 => x"08", + 5653 => x"d4", + 5654 => x"85", + 5655 => x"2e", + 5656 => x"82", + 5657 => x"1a", + 5658 => x"59", + 5659 => x"2e", + 5660 => x"77", + 5661 => x"11", + 5662 => x"55", + 5663 => x"85", + 5664 => x"31", + 5665 => x"76", + 5666 => x"81", + 5667 => x"c9", + 5668 => x"85", + 5669 => x"d7", + 5670 => x"11", + 5671 => x"74", + 5672 => x"38", + 5673 => x"77", + 5674 => x"78", + 5675 => x"84", + 5676 => x"16", + 5677 => x"08", + 5678 => x"2b", + 5679 => x"cf", + 5680 => x"89", + 5681 => x"39", + 5682 => x"0c", + 5683 => x"83", + 5684 => x"80", + 5685 => x"55", + 5686 => x"83", + 5687 => x"9c", + 5688 => x"7e", + 5689 => x"3f", + 5690 => x"08", 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x"38", + 5750 => x"ff", + 5751 => x"98", + 5752 => x"18", + 5753 => x"74", + 5754 => x"7e", + 5755 => x"08", + 5756 => x"2e", + 5757 => x"8d", + 5758 => x"ce", + 5759 => x"85", + 5760 => x"ee", + 5761 => x"08", + 5762 => x"d0", + 5763 => x"85", + 5764 => x"2e", + 5765 => x"82", + 5766 => x"1b", + 5767 => x"5a", + 5768 => x"2e", + 5769 => x"78", + 5770 => x"11", + 5771 => x"55", + 5772 => x"85", + 5773 => x"31", + 5774 => x"76", + 5775 => x"81", + 5776 => x"c8", + 5777 => x"85", + 5778 => x"a6", + 5779 => x"11", + 5780 => x"56", + 5781 => x"27", + 5782 => x"80", + 5783 => x"08", + 5784 => x"2b", + 5785 => x"b4", + 5786 => x"85", + 5787 => x"80", + 5788 => x"34", + 5789 => x"56", + 5790 => x"8c", + 5791 => x"19", + 5792 => x"38", + 5793 => x"86", + 5794 => x"ec", + 5795 => x"38", + 5796 => x"12", + 5797 => x"9c", + 5798 => x"18", + 5799 => x"06", + 5800 => x"31", + 5801 => x"76", + 5802 => x"7b", + 5803 => x"08", + 5804 => x"cd", + 5805 => x"85", + 5806 => x"b6", + 5807 => x"7c", + 5808 => x"08", + 5809 => x"1f", + 5810 => x"cb", + 5811 => x"55", + 5812 => x"16", + 5813 => x"31", + 5814 => x"7f", + 5815 => x"94", + 5816 => x"70", + 5817 => x"8c", + 5818 => x"58", + 5819 => x"76", + 5820 => x"75", + 5821 => x"19", + 5822 => x"39", + 5823 => x"80", + 5824 => x"74", + 5825 => x"80", + 5826 => x"85", + 5827 => x"3d", + 5828 => x"3d", + 5829 => x"3d", + 5830 => x"70", + 5831 => x"e8", + 5832 => x"ec", + 5833 => x"85", + 5834 => x"fb", + 5835 => x"33", + 5836 => x"70", + 5837 => x"55", + 5838 => x"2e", + 5839 => x"a0", + 5840 => x"78", + 5841 => x"3f", + 5842 => x"08", + 5843 => x"ec", + 5844 => x"38", + 5845 => x"8b", + 5846 => x"07", + 5847 => x"8b", + 5848 => x"16", + 5849 => x"52", + 5850 => x"dd", + 5851 => x"16", + 5852 => x"15", + 5853 => x"3f", + 5854 => x"0a", + 5855 => x"51", + 5856 => x"76", + 5857 => x"51", + 5858 => x"78", + 5859 => x"83", + 5860 => x"51", + 5861 => x"82", + 5862 => x"90", + 5863 => x"bf", + 5864 => x"73", + 5865 => x"76", + 5866 => x"0c", + 5867 => x"04", + 5868 => x"76", + 5869 => x"fe", + 5870 => x"85", + 5871 => x"82", + 5872 => x"9c", + 5873 => x"fc", + 5874 => x"51", + 5875 => x"82", + 5876 => x"53", + 5877 => x"08", + 5878 => x"85", + 5879 => x"0c", + 5880 => x"ec", + 5881 => x"0d", + 5882 => x"0d", + 5883 => x"e6", + 5884 => x"52", + 5885 => x"85", + 5886 => x"8b", + 5887 => x"ec", + 5888 => x"a4", + 5889 => x"71", + 5890 => x"0c", + 5891 => x"04", + 5892 => x"80", + 5893 => x"d0", + 5894 => x"3d", + 5895 => x"3f", + 5896 => x"08", + 5897 => x"ec", + 5898 => x"38", + 5899 => x"52", + 5900 => x"05", + 5901 => x"3f", + 5902 => x"08", + 5903 => x"ec", + 5904 => x"02", + 5905 => x"33", + 5906 => x"55", + 5907 => x"25", + 5908 => x"7a", + 5909 => x"54", + 5910 => x"a2", + 5911 => x"84", + 5912 => x"06", + 5913 => x"73", + 5914 => x"38", + 5915 => x"70", + 5916 => x"87", + 5917 => x"ec", + 5918 => x"0c", + 5919 => x"85", + 5920 => x"2e", + 5921 => x"83", + 5922 => x"74", + 5923 => x"0c", + 5924 => x"04", + 5925 => x"6f", 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x"38", + 5985 => x"73", + 5986 => x"8f", + 5987 => x"2e", + 5988 => x"16", + 5989 => x"ff", + 5990 => x"ff", + 5991 => x"58", + 5992 => x"74", + 5993 => x"75", + 5994 => x"18", + 5995 => x"58", + 5996 => x"fe", + 5997 => x"7b", + 5998 => x"06", + 5999 => x"18", + 6000 => x"58", + 6001 => x"80", + 6002 => x"a4", + 6003 => x"2b", + 6004 => x"11", + 6005 => x"52", + 6006 => x"56", + 6007 => x"8d", + 6008 => x"70", + 6009 => x"51", + 6010 => x"f5", + 6011 => x"54", + 6012 => x"a7", + 6013 => x"74", + 6014 => x"38", + 6015 => x"73", + 6016 => x"81", + 6017 => x"81", + 6018 => x"39", + 6019 => x"81", + 6020 => x"74", + 6021 => x"81", + 6022 => x"91", + 6023 => x"6e", + 6024 => x"59", + 6025 => x"7a", + 6026 => x"5c", + 6027 => x"26", + 6028 => x"7a", + 6029 => x"85", + 6030 => x"3d", + 6031 => x"3d", + 6032 => x"8d", + 6033 => x"54", + 6034 => x"55", + 6035 => x"82", + 6036 => x"53", + 6037 => x"08", + 6038 => x"91", + 6039 => x"72", + 6040 => x"8c", + 6041 => x"73", + 6042 => x"38", + 6043 => x"70", + 6044 => x"81", + 6045 => x"57", + 6046 => x"73", + 6047 => x"08", + 6048 => x"94", + 6049 => x"75", + 6050 => x"99", + 6051 => x"11", + 6052 => x"2b", + 6053 => x"73", + 6054 => x"38", + 6055 => x"16", + 6056 => x"e7", + 6057 => x"ec", + 6058 => x"78", + 6059 => x"55", + 6060 => x"d7", + 6061 => x"ec", + 6062 => x"98", + 6063 => x"81", + 6064 => x"06", + 6065 => x"0c", + 6066 => x"98", + 6067 => x"58", + 6068 => x"39", + 6069 => x"54", + 6070 => x"73", + 6071 => x"cd", + 6072 => x"85", + 6073 => x"82", + 6074 => x"81", + 6075 => x"38", + 6076 => x"08", + 6077 => x"9b", + 6078 => x"ec", + 6079 => x"0c", + 6080 => x"0c", + 6081 => x"81", + 6082 => x"76", + 6083 => x"38", + 6084 => x"94", + 6085 => x"94", + 6086 => x"16", + 6087 => x"2a", + 6088 => x"51", + 6089 => x"72", + 6090 => x"38", + 6091 => x"51", + 6092 => x"82", + 6093 => x"54", + 6094 => x"08", + 6095 => x"85", + 6096 => x"a7", + 6097 => x"74", + 6098 => x"3f", + 6099 => x"08", + 6100 => x"2e", + 6101 => x"74", + 6102 => x"79", + 6103 => x"14", + 6104 => x"38", + 6105 => x"0c", + 6106 => x"94", + 6107 => x"94", + 6108 => x"83", + 6109 => x"72", + 6110 => x"38", + 6111 => x"51", + 6112 => x"82", + 6113 => x"94", + 6114 => x"91", + 6115 => x"53", + 6116 => x"81", + 6117 => x"34", + 6118 => x"39", + 6119 => x"82", + 6120 => x"05", + 6121 => x"08", + 6122 => x"08", + 6123 => x"38", + 6124 => x"0c", + 6125 => x"80", + 6126 => x"72", + 6127 => x"73", + 6128 => x"53", + 6129 => x"8c", + 6130 => x"16", + 6131 => x"38", + 6132 => x"0c", + 6133 => x"82", + 6134 => x"8b", + 6135 => x"f9", + 6136 => x"56", + 6137 => x"80", + 6138 => x"38", + 6139 => x"3d", + 6140 => x"8a", + 6141 => x"51", + 6142 => x"82", + 6143 => x"55", + 6144 => x"08", + 6145 => x"77", + 6146 => x"52", + 6147 => x"93", + 6148 => x"ec", + 6149 => x"85", + 6150 => x"c3", + 6151 => x"33", + 6152 => x"55", + 6153 => x"24", + 6154 => x"16", + 6155 => x"2a", + 6156 => x"51", + 6157 => x"80", + 6158 => x"9c", + 6159 => x"77", + 6160 => x"3f", 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x"3d", + 6220 => x"a3", + 6221 => x"ec", + 6222 => x"85", + 6223 => x"38", + 6224 => x"51", + 6225 => x"82", + 6226 => x"55", + 6227 => x"08", + 6228 => x"80", + 6229 => x"70", + 6230 => x"58", + 6231 => x"85", + 6232 => x"8d", + 6233 => x"2e", + 6234 => x"52", + 6235 => x"9a", + 6236 => x"85", + 6237 => x"3d", + 6238 => x"3d", + 6239 => x"55", + 6240 => x"92", + 6241 => x"52", + 6242 => x"de", + 6243 => x"85", + 6244 => x"82", + 6245 => x"82", + 6246 => x"74", + 6247 => x"98", + 6248 => x"11", + 6249 => x"59", + 6250 => x"75", + 6251 => x"38", + 6252 => x"81", + 6253 => x"5b", + 6254 => x"82", + 6255 => x"39", + 6256 => x"08", + 6257 => x"59", + 6258 => x"09", + 6259 => x"c1", + 6260 => x"5f", + 6261 => x"92", + 6262 => x"51", + 6263 => x"82", + 6264 => x"ff", + 6265 => x"82", + 6266 => x"81", + 6267 => x"82", + 6268 => x"09", + 6269 => x"82", + 6270 => x"07", + 6271 => x"05", + 6272 => x"53", + 6273 => x"98", + 6274 => x"26", + 6275 => x"fd", + 6276 => x"08", + 6277 => x"08", + 6278 => x"98", + 6279 => x"81", + 6280 => x"58", + 6281 => x"3f", + 6282 => x"08", + 6283 => x"ec", + 6284 => x"38", + 6285 => x"77", + 6286 => x"5d", + 6287 => x"74", + 6288 => x"81", + 6289 => x"b4", + 6290 => x"bb", + 6291 => x"85", + 6292 => x"ff", + 6293 => x"09", + 6294 => x"80", + 6295 => x"19", + 6296 => x"54", + 6297 => x"14", + 6298 => x"8d", + 6299 => x"ec", + 6300 => x"06", + 6301 => x"05", + 6302 => x"1b", + 6303 => x"5b", + 6304 => x"83", + 6305 => x"58", + 6306 => x"8e", + 6307 => x"0c", + 6308 => x"12", + 6309 => x"33", + 6310 => x"54", + 6311 => x"34", + 6312 => x"ec", + 6313 => x"0d", + 6314 => x"0d", + 6315 => x"fc", + 6316 => x"52", + 6317 => x"3f", + 6318 => x"08", + 6319 => x"ec", + 6320 => x"38", + 6321 => x"56", + 6322 => x"38", + 6323 => x"70", + 6324 => x"81", + 6325 => x"55", + 6326 => x"80", + 6327 => x"38", + 6328 => x"54", + 6329 => x"08", + 6330 => x"38", + 6331 => x"82", + 6332 => x"53", + 6333 => x"52", + 6334 => x"d9", + 6335 => x"ec", + 6336 => x"19", + 6337 => x"c9", + 6338 => x"08", + 6339 => x"ff", + 6340 => x"82", + 6341 => x"ff", + 6342 => x"06", + 6343 => x"56", + 6344 => x"08", + 6345 => x"81", + 6346 => x"82", + 6347 => x"75", + 6348 => x"54", + 6349 => x"08", + 6350 => x"27", + 6351 => x"17", + 6352 => x"85", + 6353 => x"76", + 6354 => x"3f", + 6355 => x"08", + 6356 => x"08", + 6357 => x"90", + 6358 => x"c0", + 6359 => x"90", + 6360 => x"80", + 6361 => x"75", + 6362 => x"75", + 6363 => x"85", + 6364 => x"3d", + 6365 => x"3d", + 6366 => x"a0", + 6367 => x"05", + 6368 => x"51", + 6369 => x"82", + 6370 => x"55", + 6371 => x"08", + 6372 => x"78", + 6373 => x"08", + 6374 => x"70", + 6375 => x"83", + 6376 => x"ec", + 6377 => x"85", + 6378 => x"dd", + 6379 => x"fb", + 6380 => x"85", + 6381 => x"06", + 6382 => x"86", + 6383 => x"c9", + 6384 => x"2b", + 6385 => x"24", + 6386 => x"02", + 6387 => x"33", + 6388 => x"58", + 6389 => x"76", + 6390 => x"6b", + 6391 => x"cc", + 6392 => x"85", + 6393 => x"84", + 6394 => x"06", + 6395 => x"73", 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x"70", + 6455 => x"06", + 6456 => x"54", + 6457 => x"38", + 6458 => x"52", + 6459 => x"52", + 6460 => x"3f", + 6461 => x"08", + 6462 => x"82", + 6463 => x"83", + 6464 => x"82", + 6465 => x"81", + 6466 => x"06", + 6467 => x"54", + 6468 => x"08", + 6469 => x"81", + 6470 => x"81", + 6471 => x"39", + 6472 => x"38", + 6473 => x"08", + 6474 => x"c3", + 6475 => x"85", + 6476 => x"82", + 6477 => x"81", + 6478 => x"53", + 6479 => x"19", + 6480 => x"d0", + 6481 => x"ae", + 6482 => x"34", + 6483 => x"0b", + 6484 => x"82", + 6485 => x"52", + 6486 => x"51", + 6487 => x"3f", + 6488 => x"b4", + 6489 => x"c9", + 6490 => x"53", + 6491 => x"53", + 6492 => x"51", + 6493 => x"3f", + 6494 => x"0b", + 6495 => x"34", + 6496 => x"80", + 6497 => x"51", + 6498 => x"78", + 6499 => x"83", + 6500 => x"51", + 6501 => x"82", + 6502 => x"54", + 6503 => x"08", + 6504 => x"88", + 6505 => x"64", + 6506 => x"ff", + 6507 => x"75", + 6508 => x"78", + 6509 => x"3f", + 6510 => x"0b", + 6511 => x"78", + 6512 => x"83", + 6513 => x"51", + 6514 => x"3f", + 6515 => x"08", + 6516 => x"80", + 6517 => x"76", + 6518 => x"f9", + 6519 => x"85", + 6520 => x"3d", + 6521 => x"3d", + 6522 => x"84", + 6523 => x"d4", + 6524 => x"a8", + 6525 => x"05", + 6526 => x"51", + 6527 => x"82", + 6528 => x"55", + 6529 => x"08", + 6530 => x"78", + 6531 => x"08", + 6532 => x"70", + 6533 => x"8b", + 6534 => x"ec", + 6535 => x"85", + 6536 => x"b9", + 6537 => x"9b", + 6538 => x"a0", + 6539 => x"55", + 6540 => x"38", + 6541 => x"3d", + 6542 => x"3d", + 6543 => x"51", + 6544 => x"3f", + 6545 => x"52", + 6546 => x"52", + 6547 => x"a1", + 6548 => x"08", + 6549 => x"cb", + 6550 => x"85", + 6551 => x"82", + 6552 => x"95", + 6553 => x"2e", + 6554 => x"88", + 6555 => x"3d", + 6556 => x"38", + 6557 => x"e5", + 6558 => x"ec", + 6559 => x"09", + 6560 => x"b8", + 6561 => x"c9", + 6562 => x"85", + 6563 => x"82", + 6564 => x"81", + 6565 => x"56", + 6566 => x"3d", + 6567 => x"52", + 6568 => x"ff", + 6569 => x"02", + 6570 => x"8b", + 6571 => x"16", + 6572 => x"2a", + 6573 => x"51", + 6574 => x"89", + 6575 => x"07", + 6576 => x"17", + 6577 => x"81", + 6578 => x"34", + 6579 => x"70", + 6580 => x"81", + 6581 => x"55", + 6582 => x"80", + 6583 => x"64", + 6584 => x"38", + 6585 => x"51", + 6586 => x"82", + 6587 => x"52", + 6588 => x"b6", + 6589 => x"55", + 6590 => x"08", + 6591 => x"dd", + 6592 => x"ec", + 6593 => x"51", + 6594 => x"3f", + 6595 => x"08", + 6596 => x"11", + 6597 => x"82", + 6598 => x"80", + 6599 => x"16", + 6600 => x"ae", + 6601 => x"06", + 6602 => x"53", + 6603 => x"51", + 6604 => x"78", + 6605 => x"83", + 6606 => x"39", + 6607 => x"08", + 6608 => x"51", + 6609 => x"82", + 6610 => x"55", + 6611 => x"08", + 6612 => x"51", + 6613 => x"3f", + 6614 => x"08", + 6615 => x"85", + 6616 => x"3d", + 6617 => x"3d", + 6618 => x"db", + 6619 => x"84", + 6620 => x"05", + 6621 => x"82", + 6622 => x"d0", + 6623 => x"3d", + 6624 => x"3f", + 6625 => x"08", + 6626 => x"ec", + 6627 => x"38", + 6628 => x"52", + 6629 => x"05", + 6630 => x"3f", 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x"38", + 6690 => x"06", + 6691 => x"80", + 6692 => x"38", + 6693 => x"5f", + 6694 => x"3d", + 6695 => x"ff", + 6696 => x"82", + 6697 => x"57", + 6698 => x"08", + 6699 => x"74", + 6700 => x"c3", + 6701 => x"85", + 6702 => x"82", + 6703 => x"bf", + 6704 => x"ec", + 6705 => x"ec", + 6706 => x"59", + 6707 => x"81", + 6708 => x"56", + 6709 => x"33", + 6710 => x"16", + 6711 => x"27", + 6712 => x"56", + 6713 => x"80", + 6714 => x"80", + 6715 => x"ff", + 6716 => x"70", + 6717 => x"56", + 6718 => x"e8", + 6719 => x"76", + 6720 => x"81", + 6721 => x"80", + 6722 => x"57", + 6723 => x"05", + 6724 => x"80", + 6725 => x"7a", + 6726 => x"c1", + 6727 => x"2e", + 6728 => x"a0", + 6729 => x"51", + 6730 => x"3f", + 6731 => x"08", + 6732 => x"ec", + 6733 => x"7b", + 6734 => x"55", + 6735 => x"73", + 6736 => x"38", + 6737 => x"73", + 6738 => x"38", + 6739 => x"15", + 6740 => x"ff", + 6741 => x"82", + 6742 => x"7b", + 6743 => x"85", + 6744 => x"3d", + 6745 => x"3d", + 6746 => x"9c", + 6747 => x"05", + 6748 => x"51", + 6749 => x"82", + 6750 => x"82", + 6751 => x"56", + 6752 => x"ec", + 6753 => x"38", + 6754 => x"52", + 6755 => x"52", + 6756 => x"80", + 6757 => x"70", + 6758 => x"ff", + 6759 => x"55", + 6760 => x"27", + 6761 => x"78", + 6762 => x"ff", + 6763 => x"05", + 6764 => x"55", + 6765 => x"3f", + 6766 => x"08", + 6767 => x"38", + 6768 => x"70", + 6769 => x"ff", + 6770 => x"82", + 6771 => x"80", + 6772 => x"74", + 6773 => x"07", + 6774 => x"4e", + 6775 => x"82", + 6776 => x"55", + 6777 => x"70", + 6778 => x"06", + 6779 => x"99", + 6780 => x"e0", + 6781 => x"ff", + 6782 => x"54", + 6783 => x"27", + 6784 => x"fe", + 6785 => x"55", + 6786 => x"a3", + 6787 => x"82", + 6788 => x"ff", + 6789 => x"82", + 6790 => x"93", + 6791 => x"75", + 6792 => x"76", + 6793 => x"38", + 6794 => x"77", + 6795 => x"86", + 6796 => x"39", + 6797 => x"27", + 6798 => x"88", + 6799 => x"78", + 6800 => x"5a", + 6801 => x"57", + 6802 => x"81", + 6803 => x"81", + 6804 => x"33", + 6805 => x"06", + 6806 => x"57", + 6807 => x"fe", + 6808 => x"3d", + 6809 => x"55", + 6810 => x"2e", + 6811 => x"76", + 6812 => x"38", + 6813 => x"55", + 6814 => x"33", + 6815 => x"a0", + 6816 => x"06", + 6817 => x"17", + 6818 => x"38", + 6819 => x"43", + 6820 => x"3d", + 6821 => x"ff", + 6822 => x"82", + 6823 => x"54", + 6824 => x"08", + 6825 => x"81", + 6826 => x"ff", + 6827 => x"82", + 6828 => x"54", + 6829 => x"08", + 6830 => x"80", + 6831 => x"54", + 6832 => x"80", + 6833 => x"85", + 6834 => x"2e", + 6835 => x"80", + 6836 => x"54", + 6837 => x"80", + 6838 => x"52", + 6839 => x"bc", + 6840 => x"85", + 6841 => x"82", + 6842 => x"b1", + 6843 => x"82", + 6844 => x"52", + 6845 => x"ab", + 6846 => x"54", + 6847 => x"15", + 6848 => x"78", + 6849 => x"ff", + 6850 => x"79", + 6851 => x"83", + 6852 => x"51", + 6853 => x"3f", + 6854 => x"08", + 6855 => x"74", + 6856 => x"0c", + 6857 => x"04", + 6858 => x"60", + 6859 => x"05", + 6860 => x"33", + 6861 => x"05", + 6862 => x"40", + 6863 => x"c8", + 6864 => x"ec", + 6865 => x"85", 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x"85", + 6925 => x"82", + 6926 => x"80", + 6927 => x"81", + 6928 => x"56", + 6929 => x"d3", + 6930 => x"ff", + 6931 => x"7c", + 6932 => x"55", + 6933 => x"b3", + 6934 => x"1b", + 6935 => x"1b", + 6936 => x"33", + 6937 => x"54", + 6938 => x"34", + 6939 => x"fe", + 6940 => x"08", + 6941 => x"74", + 6942 => x"75", + 6943 => x"16", + 6944 => x"33", + 6945 => x"73", + 6946 => x"77", + 6947 => x"85", + 6948 => x"3d", + 6949 => x"3d", + 6950 => x"02", + 6951 => x"eb", + 6952 => x"3d", + 6953 => x"59", + 6954 => x"8b", + 6955 => x"82", + 6956 => x"24", + 6957 => x"82", + 6958 => x"82", + 6959 => x"90", + 6960 => x"55", + 6961 => x"84", + 6962 => x"34", + 6963 => x"08", + 6964 => x"5f", + 6965 => x"51", + 6966 => x"3f", + 6967 => x"08", + 6968 => x"70", + 6969 => x"57", + 6970 => x"8b", + 6971 => x"82", + 6972 => x"06", + 6973 => x"56", + 6974 => x"38", + 6975 => x"05", + 6976 => x"7e", + 6977 => x"af", + 6978 => x"ec", + 6979 => x"67", + 6980 => x"2e", + 6981 => x"82", + 6982 => x"8b", + 6983 => x"75", + 6984 => x"80", + 6985 => x"81", + 6986 => x"2e", + 6987 => x"80", + 6988 => x"38", + 6989 => x"0a", + 6990 => x"ff", + 6991 => x"55", + 6992 => x"86", + 6993 => x"8a", + 6994 => x"89", + 6995 => x"2a", + 6996 => x"77", + 6997 => x"59", + 6998 => x"81", + 6999 => x"81", + 7000 => x"25", + 7001 => x"55", + 7002 => x"8a", + 7003 => x"3d", + 7004 => x"81", + 7005 => x"ff", + 7006 => x"81", + 7007 => x"ec", + 7008 => x"38", + 7009 => x"70", + 7010 => x"85", + 7011 => x"56", + 7012 => x"38", + 7013 => x"55", + 7014 => x"75", + 7015 => x"38", + 7016 => x"70", + 7017 => x"ff", + 7018 => x"8c", + 7019 => x"78", + 7020 => x"8a", + 7021 => x"81", + 7022 => x"06", + 7023 => x"80", + 7024 => x"77", + 7025 => x"74", + 7026 => x"94", + 7027 => x"06", + 7028 => x"2e", + 7029 => x"77", + 7030 => x"93", + 7031 => x"74", + 7032 => x"d4", + 7033 => x"7d", + 7034 => x"81", + 7035 => x"38", + 7036 => x"66", + 7037 => x"81", + 7038 => x"d8", + 7039 => x"74", + 7040 => x"38", + 7041 => x"98", + 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7747 => x"00", + 7748 => x"00", + 7749 => x"65", + 7750 => x"6e", + 7751 => x"2e", + 7752 => x"00", + 7753 => x"70", + 7754 => x"67", + 7755 => x"00", + 7756 => x"6d", + 7757 => x"69", + 7758 => x"2e", + 7759 => x"00", + 7760 => x"38", + 7761 => x"25", + 7762 => x"29", + 7763 => x"30", + 7764 => x"28", + 7765 => x"78", + 7766 => x"00", + 7767 => x"6d", + 7768 => x"65", + 7769 => x"79", + 7770 => x"00", + 7771 => x"6f", + 7772 => x"65", + 7773 => x"0a", + 7774 => x"38", + 7775 => x"30", + 7776 => x"00", + 7777 => x"3f", + 7778 => x"00", + 7779 => x"38", + 7780 => x"30", + 7781 => x"00", + 7782 => x"38", + 7783 => x"30", + 7784 => x"00", + 7785 => x"65", + 7786 => x"69", + 7787 => x"63", + 7788 => x"20", + 7789 => x"30", + 7790 => x"2e", + 7791 => x"00", + 7792 => x"6c", + 7793 => x"67", + 7794 => x"64", + 7795 => x"20", + 7796 => x"78", + 7797 => x"2e", + 7798 => x"00", + 7799 => x"6c", + 7800 => x"65", + 7801 => x"6e", + 7802 => x"63", + 7803 => x"20", + 7804 => x"29", + 7805 => x"00", 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x"20", + 7865 => x"20", + 7866 => x"41", + 7867 => x"28", + 7868 => x"58", + 7869 => x"38", + 7870 => x"0a", + 7871 => x"20", + 7872 => x"52", + 7873 => x"20", + 7874 => x"28", + 7875 => x"58", + 7876 => x"38", + 7877 => x"0a", + 7878 => x"20", + 7879 => x"53", + 7880 => x"52", + 7881 => x"28", + 7882 => x"58", + 7883 => x"38", + 7884 => x"0a", + 7885 => x"20", + 7886 => x"41", + 7887 => x"20", + 7888 => x"28", + 7889 => x"58", + 7890 => x"38", + 7891 => x"0a", + 7892 => x"20", + 7893 => x"4d", + 7894 => x"20", + 7895 => x"28", + 7896 => x"58", + 7897 => x"38", + 7898 => x"0a", + 7899 => x"20", + 7900 => x"20", + 7901 => x"44", + 7902 => x"28", + 7903 => x"69", + 7904 => x"20", + 7905 => x"32", + 7906 => x"0a", + 7907 => x"20", + 7908 => x"4d", + 7909 => x"20", + 7910 => x"28", + 7911 => x"65", + 7912 => x"20", + 7913 => x"32", + 7914 => x"0a", + 7915 => x"20", + 7916 => x"54", + 7917 => x"54", + 7918 => x"28", + 7919 => x"6e", + 7920 => x"73", + 7921 => x"32", + 7922 => x"0a", + 7923 => x"20", + 7924 => x"53", + 7925 => x"4e", + 7926 => x"55", + 7927 => x"00", + 7928 => x"20", + 7929 => x"20", + 7930 => x"0a", + 7931 => x"20", + 7932 => x"43", + 7933 => x"00", + 7934 => x"20", + 7935 => x"32", + 7936 => x"00", + 7937 => x"20", + 7938 => x"49", + 7939 => x"00", + 7940 => x"64", + 7941 => x"73", + 7942 => x"0a", + 7943 => x"20", + 7944 => x"55", + 7945 => x"73", + 7946 => x"56", + 7947 => x"6f", + 7948 => x"64", + 7949 => x"73", + 7950 => x"20", + 7951 => x"58", + 7952 => x"00", + 7953 => x"20", + 7954 => x"55", + 7955 => x"6d", + 7956 => x"20", + 7957 => x"72", + 7958 => x"64", + 7959 => x"73", + 7960 => x"20", + 7961 => x"58", + 7962 => x"00", + 7963 => x"20", + 7964 => x"61", + 7965 => x"53", + 7966 => x"74", + 7967 => x"64", + 7968 => x"73", + 7969 => x"20", + 7970 => x"20", + 7971 => x"58", + 7972 => x"00", + 7973 => x"73", + 7974 => x"00", + 7975 => x"20", + 7976 => x"55", + 7977 => x"20", + 7978 => x"20", + 7979 => x"20", + 7980 => x"20", + 7981 => x"20", + 7982 => x"20", + 7983 => x"58", + 7984 => x"00", + 7985 => x"20", + 7986 => x"73", + 7987 => x"20", + 7988 => x"63", + 7989 => x"72", + 7990 => x"20", + 7991 => x"20", + 7992 => x"20", + 7993 => x"25", + 7994 => x"4d", + 7995 => x"00", + 7996 => x"20", + 7997 => x"52", + 7998 => x"43", + 7999 => x"6b", + 8000 => x"65", + 8001 => x"20", + 8002 => x"20", + 8003 => x"20", + 8004 => x"25", + 8005 => x"4d", + 8006 => x"00", + 8007 => x"20", + 8008 => x"73", + 8009 => x"6e", + 8010 => x"44", + 8011 => x"20", + 8012 => x"63", + 8013 => x"72", + 8014 => x"20", + 8015 => x"25", + 8016 => x"4d", + 8017 => x"00", + 8018 => x"61", + 8019 => x"00", + 8020 => x"64", + 8021 => x"00", + 8022 => x"65", + 8023 => x"00", + 8024 => x"4f", + 8025 => x"4f", + 8026 => x"00", + 8027 => x"6b", + 8028 => x"6e", + 8029 => x"7e", + 8030 => x"00", + 8031 => x"00", + 8032 => x"7e", + 8033 => x"00", + 8034 => x"00", + 8035 => x"7e", + 8036 => x"00", + 8037 => x"00", + 8038 => x"7e", + 8039 => x"00", + 8040 => x"00", + 8041 => x"7e", + 8042 => x"00", + 8043 => x"00", + 8044 => x"7e", + 8045 => x"00", + 8046 => x"00", + 8047 => x"7e", + 8048 => x"00", + 8049 => x"00", + 8050 => x"7e", + 8051 => x"00", + 8052 => x"00", + 8053 => x"7e", + 8054 => x"00", + 8055 => x"00", + 8056 => x"7e", + 8057 => x"00", + 8058 => x"00", + 8059 => x"7e", + 8060 => x"00", + 8061 => x"00", + 8062 => x"7e", + 8063 => x"00", + 8064 => x"00", + 8065 => x"7e", + 8066 => x"00", + 8067 => x"00", + 8068 => x"7e", + 8069 => x"00", + 8070 => x"00", + 8071 => x"7e", + 8072 => x"00", + 8073 => x"00", + 8074 => x"7e", + 8075 => x"00", + 8076 => x"00", + 8077 => x"7e", + 8078 => x"00", + 8079 => x"00", + 8080 => x"7e", + 8081 => x"00", + 8082 => x"00", + 8083 => x"7e", + 8084 => x"00", + 8085 => x"00", + 8086 => x"7e", + 8087 => x"00", + 8088 => x"00", + 8089 => x"7e", + 8090 => x"00", + 8091 => x"00", + 8092 => x"7e", + 8093 => x"00", + 8094 => x"00", + 8095 => x"44", + 8096 => x"43", + 8097 => x"42", + 8098 => x"41", + 8099 => x"36", + 8100 => x"35", + 8101 => x"34", + 8102 => x"46", + 8103 => x"33", + 8104 => x"32", + 8105 => x"31", + 8106 => x"00", + 8107 => x"00", + 8108 => x"00", + 8109 => x"00", + 8110 => x"00", + 8111 => x"00", + 8112 => x"00", + 8113 => x"00", + 8114 => x"00", + 8115 => x"00", + 8116 => x"00", + 8117 => x"73", + 8118 => x"79", + 8119 => x"73", + 8120 => x"00", + 8121 => x"00", + 8122 => x"34", + 8123 => x"25", + 8124 => x"00", + 8125 => x"69", + 8126 => x"20", + 8127 => x"72", + 8128 => x"74", + 8129 => x"65", + 8130 => x"73", + 8131 => x"79", + 8132 => x"6c", + 8133 => x"6f", + 8134 => x"46", + 8135 => x"00", + 8136 => x"6e", + 8137 => x"20", + 8138 => x"6e", + 8139 => x"65", + 8140 => x"20", + 8141 => x"74", + 8142 => x"20", + 8143 => x"65", + 8144 => x"69", + 8145 => x"6c", + 8146 => x"2e", + 8147 => x"00", + 8148 => x"00", + 8149 => x"2b", + 8150 => x"3c", + 8151 => x"5b", + 8152 => x"00", + 8153 => x"54", + 8154 => x"54", + 8155 => x"00", + 8156 => x"90", + 8157 => x"4f", + 8158 => x"30", + 8159 => x"20", + 8160 => x"45", + 8161 => x"20", + 8162 => x"33", + 8163 => x"20", + 8164 => x"20", + 8165 => x"45", + 8166 => x"20", + 8167 => x"20", + 8168 => x"20", + 8169 => x"7f", + 8170 => x"00", + 8171 => x"00", + 8172 => x"00", + 8173 => x"45", + 8174 => x"8f", + 8175 => x"45", + 8176 => x"8e", + 8177 => x"92", + 8178 => x"55", + 8179 => x"9a", + 8180 => x"9e", + 8181 => x"4f", + 8182 => x"a6", + 8183 => x"aa", + 8184 => x"ae", + 8185 => x"b2", + 8186 => x"b6", + 8187 => x"ba", + 8188 => x"be", + 8189 => x"c2", + 8190 => x"c6", + 8191 => x"ca", + 8192 => x"ce", + 8193 => x"d2", + 8194 => x"d6", + 8195 => x"da", + 8196 => x"de", + 8197 => x"e2", + 8198 => x"e6", + 8199 => x"ea", + 8200 => x"ee", + 8201 => x"f2", + 8202 => x"f6", + 8203 => x"fa", + 8204 => x"fe", + 8205 => x"2c", + 8206 => x"5d", + 8207 => x"2a", + 8208 => x"3f", + 8209 => x"00", + 8210 => x"00", + 8211 => x"00", + 8212 => x"02", + 8213 => x"00", + 8214 => x"00", + 8215 => x"00", + 8216 => x"00", + 8217 => x"00", + 8218 => x"00", + 8219 => x"74", + 8220 => x"01", + 8221 => x"00", + 8222 => x"00", + 8223 => x"74", + 8224 => x"01", + 8225 => x"00", + 8226 => x"00", + 8227 => x"74", + 8228 => x"03", + 8229 => x"00", + 8230 => x"00", + 8231 => x"74", + 8232 => x"03", + 8233 => x"00", + 8234 => x"00", + 8235 => x"74", + 8236 => x"03", + 8237 => x"00", + 8238 => x"00", + 8239 => x"74", + 8240 => x"04", + 8241 => x"00", + 8242 => x"00", + 8243 => x"74", + 8244 => x"04", + 8245 => x"00", + 8246 => x"00", + 8247 => x"75", + 8248 => x"04", + 8249 => x"00", + 8250 => x"00", + 8251 => x"75", + 8252 => x"04", + 8253 => x"00", + 8254 => x"00", + 8255 => x"75", + 8256 => x"04", + 8257 => x"00", + 8258 => x"00", + 8259 => x"75", + 8260 => x"04", + 8261 => x"00", + 8262 => x"00", + 8263 => x"75", + 8264 => x"04", + 8265 => x"00", + 8266 => x"00", + 8267 => x"75", + 8268 => x"05", + 8269 => x"00", + 8270 => x"00", + 8271 => x"75", + 8272 => x"05", + 8273 => x"00", + 8274 => x"00", + 8275 => x"75", + 8276 => x"05", + 8277 => x"00", + 8278 => x"00", + 8279 => x"75", + 8280 => x"05", + 8281 => x"00", + 8282 => x"00", + 8283 => x"75", + 8284 => x"07", + 8285 => x"00", + 8286 => x"00", + 8287 => x"75", + 8288 => x"07", + 8289 => x"00", + 8290 => x"00", + 8291 => x"75", + 8292 => x"08", + 8293 => x"00", + 8294 => x"00", + 8295 => x"75", + 8296 => x"08", + 8297 => x"00", + 8298 => x"00", + 8299 => x"75", + 8300 => x"08", + 8301 => x"00", + 8302 => x"00", + 8303 => x"75", + 8304 => x"08", + 8305 => x"00", + 8306 => x"00", + 8307 => x"75", + 8308 => x"09", + 8309 => x"00", + 8310 => x"00", + 8311 => x"75", + 8312 => x"09", + 8313 => x"00", + 8314 => x"00", + 8315 => x"75", + 8316 => x"09", + 8317 => x"00", + 8318 => x"00", + 8319 => x"75", + 8320 => x"09", + 8321 => x"00", + 8322 => x"00", + 8323 => x"00", + 8324 => x"00", + 8325 => x"7f", + 8326 => x"00", + 8327 => x"7f", + 8328 => x"00", + 8329 => x"7f", + 8330 => x"00", + 8331 => x"00", + 8332 => x"00", + 8333 => x"ff", + 8334 => x"00", + 8335 => x"00", + 8336 => x"78", + 8337 => x"00", + 8338 => x"e1", + 8339 => x"e1", + 8340 => x"e1", + 8341 => x"00", + 8342 => x"01", + 8343 => x"01", + 8344 => x"10", + 8345 => x"00", + 8346 => x"00", + 8347 => x"00", + 8348 => x"00", + 8349 => x"00", + 8350 => x"00", + 8351 => x"00", + 8352 => x"00", + 8353 => x"00", + 8354 => x"00", + 8355 => x"00", + 8356 => x"00", + 8357 => x"00", + 8358 => x"00", + 8359 => x"00", + 8360 => x"00", + 8361 => x"00", + 8362 => x"00", + 8363 => x"00", + 8364 => x"00", + 8365 => x"00", + 8366 => x"00", + 8367 => x"00", + 8368 => x"00", + 8369 => x"00", + 8370 => x"7e", + 8371 => x"00", + 8372 => x"7e", + 8373 => x"00", + 8374 => x"7e", + 8375 => x"00", + 8376 => x"00", + 8377 => x"00", + 8378 => x"00", + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + 0 => x"0b", + 1 => x"0d", + 2 => x"93", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"08", + 10 => x"2d", + 11 => x"0c", + 12 => x"00", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"fd", + 17 => x"83", + 18 => x"05", + 19 => x"2b", + 20 => x"ff", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"fd", + 25 => x"ff", + 26 => x"06", + 27 => x"82", + 28 => x"2b", + 29 => x"83", + 30 => x"0b", + 31 => x"a5", + 32 => x"09", + 33 => x"05", + 34 => x"06", + 35 => x"09", + 36 => x"0a", + 37 => x"51", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"2e", + 42 => x"04", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"73", + 49 => x"06", + 50 => x"81", + 51 => x"10", + 52 => x"10", + 53 => x"0a", + 54 => x"51", + 55 => x"00", + 56 => x"72", + 57 => x"2e", + 58 => x"04", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"04", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"0a", + 81 => x"53", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"81", + 90 => x"0b", + 91 => x"04", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"9f", + 98 => x"74", + 99 => x"06", + 100 => x"07", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"06", + 106 => x"09", + 107 => x"05", + 108 => x"2b", + 109 => x"06", + 110 => x"04", + 111 => x"00", + 112 => x"09", + 113 => x"05", + 114 => x"05", + 115 => x"81", + 116 => x"04", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"09", + 121 => x"05", + 122 => x"05", + 123 => x"09", + 124 => x"51", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"09", + 129 => x"04", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"09", + 145 => x"73", + 146 => x"53", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"fc", + 153 => x"83", + 154 => x"05", + 155 => x"10", + 156 => x"ff", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"fc", + 161 => x"0b", + 162 => x"73", + 163 => x"10", + 164 => x"0b", + 165 => x"e7", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"08", + 170 => x"0b", + 171 => x"2d", + 172 => x"08", + 173 => x"8c", + 174 => x"51", + 175 => x"00", + 176 => x"08", + 177 => x"08", + 178 => x"0b", + 179 => x"2d", + 180 => x"08", + 181 => x"8c", + 182 => x"51", + 183 => x"00", + 184 => x"09", + 185 => x"09", + 186 => x"06", + 187 => x"54", + 188 => x"09", + 189 => x"ff", + 190 => x"51", + 191 => x"00", + 192 => x"09", + 193 => x"09", + 194 => x"81", + 195 => x"70", + 196 => x"73", + 197 => x"05", + 198 => x"07", + 199 => x"04", + 200 => x"ff", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"81", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"84", + 233 => x"10", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"71", + 250 => x"0d", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"00", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"0b", + 265 => x"04", + 266 => x"8c", + 267 => x"0b", + 268 => x"04", + 269 => x"8c", + 270 => x"0b", + 271 => x"04", + 272 => x"8c", + 273 => x"0b", + 274 => x"04", + 275 => x"8c", + 276 => x"0b", + 277 => x"04", + 278 => x"8d", + 279 => x"0b", + 280 => x"04", + 281 => x"8d", + 282 => x"0b", + 283 => x"04", + 284 => x"8d", + 285 => x"0b", + 286 => x"04", + 287 => x"8d", + 288 => x"0b", + 289 => x"04", + 290 => x"8e", + 291 => x"0b", + 292 => x"04", + 293 => x"8e", + 294 => x"0b", + 295 => x"04", + 296 => x"8e", + 297 => x"0b", + 298 => x"04", + 299 => x"8e", + 300 => x"0b", + 301 => x"04", + 302 => x"8f", + 303 => x"0b", + 304 => x"04", + 305 => x"8f", + 306 => x"0b", + 307 => x"04", + 308 => x"8f", + 309 => x"0b", + 310 => x"04", + 311 => x"8f", + 312 => x"0b", + 313 => x"04", + 314 => x"90", + 315 => x"0b", + 316 => x"04", + 317 => x"90", + 318 => x"0b", + 319 => x"04", + 320 => x"90", + 321 => x"0b", + 322 => x"04", + 323 => x"90", + 324 => x"0b", + 325 => x"04", + 326 => x"91", + 327 => x"0b", + 328 => x"04", + 329 => x"91", + 330 => x"0b", + 331 => x"04", + 332 => x"91", + 333 => x"0b", + 334 => x"04", + 335 => x"91", + 336 => x"0b", + 337 => x"04", + 338 => x"92", + 339 => x"0b", + 340 => x"04", + 341 => x"92", + 342 => x"0b", + 343 => x"04", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"00", + 385 => x"82", + 386 => x"80", + 387 => x"82", + 388 => x"82", + 389 => x"82", + 390 => x"80", + 391 => x"82", + 392 => x"82", + 393 => x"82", + 394 => x"80", + 395 => x"82", + 396 => x"82", + 397 => x"82", + 398 => x"80", + 399 => x"82", + 400 => x"82", + 401 => x"82", + 402 => x"80", + 403 => x"82", + 404 => x"82", + 405 => x"82", + 406 => x"80", + 407 => x"82", + 408 => x"82", + 409 => x"82", + 410 => x"80", + 411 => x"82", + 412 => x"82", + 413 => x"82", + 414 => x"80", + 415 => x"82", + 416 => x"82", + 417 => x"82", + 418 => x"80", + 419 => x"82", + 420 => x"82", + 421 => x"82", + 422 => x"80", + 423 => x"82", + 424 => x"82", + 425 => x"82", + 426 => x"80", + 427 => x"82", + 428 => x"82", + 429 => x"82", + 430 => x"80", + 431 => x"82", + 432 => x"82", + 433 => x"82", + 434 => x"80", + 435 => x"82", + 436 => x"82", + 437 => x"82", + 438 => x"80", + 439 => x"82", + 440 => x"82", + 441 => x"82", + 442 => x"80", + 443 => x"82", + 444 => x"82", + 445 => x"82", + 446 => x"bb", + 447 => x"85", + 448 => x"a0", + 449 => x"85", + 450 => x"bd", + 451 => x"f8", + 452 => x"90", + 453 => x"f8", + 454 => x"2d", + 455 => x"08", + 456 => x"04", + 457 => x"0c", + 458 => x"2d", + 459 => x"08", + 460 => x"04", + 461 => x"0c", + 462 => x"2d", + 463 => x"08", + 464 => x"04", + 465 => x"0c", + 466 => x"2d", + 467 => x"08", + 468 => x"04", + 469 => x"0c", + 470 => x"2d", + 471 => x"08", + 472 => x"04", + 473 => x"0c", + 474 => x"2d", + 475 => x"08", + 476 => x"04", + 477 => x"0c", + 478 => x"2d", + 479 => x"08", + 480 => x"04", + 481 => x"0c", + 482 => x"2d", + 483 => x"08", + 484 => x"04", + 485 => x"0c", + 486 => x"2d", + 487 => x"08", + 488 => x"04", + 489 => x"0c", + 490 => x"2d", + 491 => x"08", + 492 => x"04", + 493 => x"0c", + 494 => x"2d", + 495 => x"08", + 496 => x"04", + 497 => x"0c", + 498 => x"2d", + 499 => x"08", + 500 => x"04", + 501 => x"0c", + 502 => x"2d", + 503 => x"08", + 504 => x"04", + 505 => x"0c", + 506 => x"2d", + 507 => x"08", + 508 => x"04", + 509 => x"0c", + 510 => x"2d", + 511 => x"08", + 512 => x"04", + 513 => x"0c", + 514 => x"2d", + 515 => x"08", + 516 => x"04", + 517 => x"0c", + 518 => x"2d", + 519 => x"08", + 520 => x"04", + 521 => x"0c", + 522 => x"2d", + 523 => x"08", + 524 => x"04", + 525 => x"0c", + 526 => x"2d", + 527 => x"08", + 528 => x"04", + 529 => x"0c", + 530 => x"2d", + 531 => x"08", + 532 => x"04", + 533 => x"0c", + 534 => x"2d", + 535 => x"08", + 536 => x"04", + 537 => x"0c", + 538 => x"2d", + 539 => x"08", + 540 => x"04", + 541 => x"0c", + 542 => x"2d", + 543 => x"08", + 544 => x"04", + 545 => x"0c", + 546 => x"2d", + 547 => x"08", + 548 => x"04", + 549 => x"0c", + 550 => x"2d", + 551 => x"08", + 552 => x"04", + 553 => x"0c", + 554 => x"2d", + 555 => x"08", + 556 => x"04", + 557 => x"0c", + 558 => x"2d", + 559 => x"08", + 560 => x"04", + 561 => x"0c", + 562 => x"2d", + 563 => x"08", + 564 => x"04", + 565 => x"0c", + 566 => x"2d", + 567 => x"08", + 568 => x"04", + 569 => x"0c", + 570 => x"2d", + 571 => x"08", + 572 => x"04", + 573 => x"0c", + 574 => x"2d", + 575 => x"08", + 576 => x"04", + 577 => x"0c", + 578 => x"82", + 579 => x"82", + 580 => x"82", + 581 => x"bd", + 582 => x"85", + 583 => x"a0", + 584 => x"85", + 585 => x"c0", + 586 => x"85", + 587 => x"a0", + 588 => x"85", + 589 => x"fd", + 590 => x"f8", + 591 => x"90", + 592 => x"00", + 593 => x"10", + 594 => x"10", + 595 => x"10", + 596 => x"10", + 597 => x"10", + 598 => x"10", + 599 => x"10", + 600 => x"10", + 601 => x"00", + 602 => x"ff", + 603 => x"06", + 604 => x"83", + 605 => x"10", + 606 => x"fc", + 607 => x"51", + 608 => x"80", + 609 => x"ff", + 610 => x"06", + 611 => x"52", + 612 => x"0a", + 613 => x"38", + 614 => x"51", + 615 => x"ec", + 616 => x"a8", + 617 => x"80", + 618 => x"05", + 619 => x"0b", + 620 => x"04", + 621 => x"ba", + 622 => x"82", + 623 => x"02", + 624 => x"0c", + 625 => x"82", + 626 => x"88", + 627 => x"85", + 628 => x"05", + 629 => x"f8", + 630 => x"08", + 631 => x"82", + 632 => x"fc", + 633 => x"05", + 634 => x"08", + 635 => x"70", + 636 => x"51", + 637 => x"2e", + 638 => x"39", + 639 => x"08", + 640 => x"ff", + 641 => x"f8", + 642 => x"0c", + 643 => x"08", + 644 => x"82", + 645 => x"88", + 646 => x"70", + 647 => x"0c", + 648 => x"0d", + 649 => x"0c", + 650 => x"f8", + 651 => x"85", + 652 => x"3d", + 653 => x"f8", + 654 => x"08", + 655 => x"08", + 656 => x"82", + 657 => x"8c", + 658 => x"71", + 659 => x"f8", + 660 => x"08", + 661 => x"85", + 662 => x"05", + 663 => x"f8", + 664 => x"08", + 665 => x"72", + 666 => x"f8", + 667 => x"08", + 668 => x"85", + 669 => x"05", + 670 => x"ff", + 671 => x"80", + 672 => x"ff", + 673 => x"85", + 674 => x"05", + 675 => x"85", + 676 => x"84", + 677 => x"85", + 678 => x"82", + 679 => x"02", + 680 => x"0c", + 681 => x"82", + 682 => x"88", + 683 => x"85", + 684 => x"05", + 685 => x"f8", + 686 => x"08", + 687 => x"08", + 688 => x"82", + 689 => x"90", + 690 => x"2e", + 691 => x"82", + 692 => x"90", + 693 => x"05", + 694 => x"08", + 695 => x"82", + 696 => x"90", + 697 => x"05", + 698 => x"08", + 699 => x"82", + 700 => x"90", + 701 => x"2e", + 702 => x"85", + 703 => x"05", + 704 => x"33", + 705 => x"08", + 706 => x"81", + 707 => x"f8", + 708 => x"0c", + 709 => x"08", + 710 => x"52", + 711 => x"34", + 712 => x"08", + 713 => x"81", + 714 => x"f8", + 715 => x"0c", + 716 => x"82", + 717 => x"88", + 718 => x"82", + 719 => x"51", + 720 => x"82", + 721 => x"04", + 722 => x"08", + 723 => x"f8", + 724 => x"0d", + 725 => x"08", + 726 => x"80", + 727 => x"38", + 728 => x"08", + 729 => x"52", + 730 => x"85", + 731 => x"05", + 732 => x"82", + 733 => x"8c", + 734 => x"85", + 735 => x"05", + 736 => x"72", + 737 => x"53", + 738 => x"71", + 739 => x"38", + 740 => x"82", + 741 => x"88", + 742 => x"71", + 743 => x"f8", + 744 => x"08", + 745 => x"85", + 746 => x"05", + 747 => x"ff", + 748 => x"70", + 749 => x"0b", + 750 => x"08", + 751 => x"81", + 752 => x"85", + 753 => x"05", + 754 => x"82", + 755 => x"90", + 756 => x"85", + 757 => x"05", + 758 => x"84", + 759 => x"39", + 760 => x"08", + 761 => x"80", + 762 => x"38", + 763 => x"08", + 764 => x"70", + 765 => x"70", + 766 => x"0b", + 767 => x"08", + 768 => x"80", + 769 => x"85", + 770 => x"05", + 771 => x"82", + 772 => x"8c", + 773 => x"85", + 774 => x"05", + 775 => x"52", + 776 => x"38", + 777 => x"85", + 778 => x"05", + 779 => x"82", + 780 => x"88", + 781 => x"33", + 782 => x"08", + 783 => x"70", + 784 => x"31", + 785 => x"f8", + 786 => x"0c", + 787 => x"52", + 788 => x"80", + 789 => x"f8", + 790 => x"0c", + 791 => x"08", + 792 => x"82", + 793 => x"85", + 794 => x"85", + 795 => x"82", + 796 => x"02", + 797 => x"0c", + 798 => x"82", + 799 => x"88", + 800 => x"85", + 801 => x"05", + 802 => x"f8", + 803 => x"08", + 804 => x"d4", + 805 => x"f8", + 806 => x"08", + 807 => x"85", + 808 => x"05", + 809 => x"f8", + 810 => x"08", + 811 => x"85", + 812 => x"05", + 813 => x"f8", + 814 => x"08", + 815 => x"38", + 816 => x"08", + 817 => x"51", + 818 => x"f8", + 819 => x"08", + 820 => x"71", + 821 => x"f8", + 822 => x"08", + 823 => x"85", + 824 => x"05", + 825 => x"39", + 826 => x"08", + 827 => x"70", + 828 => x"0c", + 829 => x"0d", + 830 => x"0c", + 831 => x"f8", + 832 => x"85", + 833 => x"3d", + 834 => x"82", + 835 => x"fc", + 836 => x"85", + 837 => x"05", + 838 => x"b9", + 839 => x"f8", + 840 => x"08", + 841 => x"f8", + 842 => x"0c", + 843 => x"85", + 844 => x"05", + 845 => x"f8", + 846 => x"08", + 847 => x"0b", + 848 => x"08", + 849 => x"82", + 850 => x"f4", + 851 => x"85", + 852 => x"05", + 853 => x"f8", + 854 => x"08", + 855 => x"38", + 856 => x"08", + 857 => x"30", + 858 => x"08", + 859 => x"80", + 860 => x"f8", + 861 => x"0c", + 862 => x"08", + 863 => x"8a", + 864 => x"82", + 865 => x"f0", + 866 => x"85", + 867 => x"05", + 868 => x"f8", + 869 => x"0c", + 870 => x"85", + 871 => x"05", + 872 => x"85", + 873 => x"05", + 874 => x"c5", + 875 => x"ec", + 876 => x"85", + 877 => x"05", + 878 => x"85", + 879 => x"05", + 880 => x"90", + 881 => x"f8", + 882 => x"08", + 883 => x"f8", + 884 => x"0c", + 885 => x"08", + 886 => x"70", + 887 => x"0c", + 888 => x"0d", + 889 => x"0c", + 890 => x"f8", + 891 => x"85", + 892 => x"3d", + 893 => x"82", + 894 => x"fc", + 895 => x"85", + 896 => x"05", + 897 => x"99", + 898 => x"f8", + 899 => x"08", + 900 => x"f8", + 901 => x"0c", + 902 => x"85", + 903 => x"05", + 904 => x"f8", + 905 => x"08", + 906 => x"38", + 907 => x"08", + 908 => x"30", + 909 => x"08", + 910 => x"81", + 911 => x"f8", + 912 => x"08", + 913 => x"f8", + 914 => x"08", + 915 => x"3f", + 916 => x"08", + 917 => x"f8", + 918 => x"0c", + 919 => x"f8", + 920 => x"08", + 921 => x"38", + 922 => x"08", + 923 => x"30", + 924 => x"08", + 925 => x"82", + 926 => x"f8", + 927 => x"82", + 928 => x"54", + 929 => x"82", + 930 => x"04", + 931 => x"08", + 932 => x"f8", + 933 => x"0d", + 934 => x"85", + 935 => x"05", + 936 => x"f8", + 937 => x"08", + 938 => x"11", + 939 => x"82", + 940 => x"8c", + 941 => x"82", + 942 => x"fc", + 943 => x"82", + 944 => x"fc", + 945 => x"85", + 946 => x"05", + 947 => x"82", + 948 => x"88", + 949 => x"85", + 950 => x"05", + 951 => x"85", + 952 => x"05", + 953 => x"51", + 954 => x"f8", + 955 => x"08", + 956 => x"38", + 957 => x"82", + 958 => x"fc", + 959 => x"82", + 960 => x"51", + 961 => x"82", + 962 => x"04", + 963 => x"08", + 964 => x"f8", + 965 => x"0d", + 966 => x"85", + 967 => x"05", + 968 => x"85", + 969 => x"05", + 970 => x"c5", + 971 => x"ec", + 972 => x"85", + 973 => x"85", + 974 => x"85", + 975 => x"82", + 976 => x"02", + 977 => x"0c", + 978 => x"81", + 979 => x"f8", + 980 => x"08", + 981 => x"f8", + 982 => x"08", + 983 => x"82", + 984 => x"70", + 985 => x"0c", + 986 => x"0d", + 987 => x"0c", + 988 => x"f8", + 989 => x"85", + 990 => x"3d", + 991 => x"82", + 992 => x"fc", + 993 => x"0b", + 994 => x"08", + 995 => x"82", + 996 => x"8c", + 997 => x"85", + 998 => x"05", + 999 => x"38", + 1000 => x"08", + 1001 => x"80", + 1002 => x"80", + 1003 => x"f8", + 1004 => x"08", + 1005 => x"82", + 1006 => x"8c", + 1007 => x"82", + 1008 => x"8c", + 1009 => x"85", + 1010 => x"05", + 1011 => x"85", + 1012 => x"05", + 1013 => x"39", + 1014 => x"08", + 1015 => x"80", + 1016 => x"38", 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x"74", + 1076 => x"51", + 1077 => x"82", + 1078 => x"8b", + 1079 => x"33", + 1080 => x"2e", + 1081 => x"81", + 1082 => x"ff", + 1083 => x"99", + 1084 => x"38", + 1085 => x"82", + 1086 => x"89", + 1087 => x"ff", + 1088 => x"52", + 1089 => x"81", + 1090 => x"82", + 1091 => x"e8", + 1092 => x"04", + 1093 => x"51", + 1094 => x"81", + 1095 => x"80", + 1096 => x"eb", + 1097 => x"f2", + 1098 => x"a8", + 1099 => x"39", + 1100 => x"51", + 1101 => x"81", + 1102 => x"80", + 1103 => x"eb", + 1104 => x"d6", + 1105 => x"ec", + 1106 => x"39", + 1107 => x"51", + 1108 => x"81", + 1109 => x"80", + 1110 => x"ec", + 1111 => x"39", + 1112 => x"51", + 1113 => x"ec", + 1114 => x"39", + 1115 => x"51", + 1116 => x"ed", + 1117 => x"39", + 1118 => x"51", + 1119 => x"ed", + 1120 => x"39", + 1121 => x"51", + 1122 => x"ee", + 1123 => x"39", + 1124 => x"51", + 1125 => x"ee", + 1126 => x"d1", + 1127 => x"0d", + 1128 => x"0d", + 1129 => x"56", + 1130 => x"26", + 1131 => x"e8", + 1132 => x"f9", + 1133 => x"52", + 1134 => x"08", + 1135 => x"87", + 1136 => x"51", + 1137 => x"82", + 1138 => x"52", + 1139 => x"bc", + 1140 => x"ec", + 1141 => x"53", + 1142 => x"ee", + 1143 => x"fd", + 1144 => x"0d", + 1145 => x"0d", + 1146 => x"05", + 1147 => x"33", + 1148 => x"68", + 1149 => x"05", + 1150 => x"73", + 1151 => x"59", + 1152 => x"77", + 1153 => x"83", + 1154 => x"74", + 1155 => x"81", + 1156 => x"55", + 1157 => x"81", + 1158 => x"53", + 1159 => x"3d", + 1160 => x"81", + 1161 => x"82", + 1162 => x"57", + 1163 => x"08", + 1164 => x"85", + 1165 => x"c0", + 1166 => x"82", + 1167 => x"59", + 1168 => x"05", + 1169 => x"53", + 1170 => x"51", + 1171 => x"3f", + 1172 => x"08", + 1173 => x"ec", + 1174 => x"7a", + 1175 => x"2e", + 1176 => x"19", + 1177 => x"59", + 1178 => x"3d", + 1179 => x"81", + 1180 => x"76", + 1181 => x"70", + 1182 => x"25", + 1183 => x"05", + 1184 => x"72", + 1185 => x"51", + 1186 => x"2e", + 1187 => x"ee", + 1188 => x"c0", + 1189 => x"52", + 1190 => x"85", + 1191 => x"75", + 1192 => x"0c", + 1193 => x"04", + 1194 => x"7b", + 1195 => x"b3", + 1196 => x"58", + 1197 => x"53", + 1198 => x"51", + 1199 => x"82", + 1200 => x"a4", + 1201 => x"2e", + 1202 => x"81", + 1203 => x"98", + 1204 => x"7f", + 1205 => x"ec", + 1206 => x"7d", + 1207 => x"82", + 1208 => x"57", + 1209 => x"04", + 1210 => x"ec", + 1211 => x"0d", + 1212 => x"0d", + 1213 => x"02", + 1214 => x"cf", + 1215 => x"73", + 1216 => x"5f", + 1217 => x"5e", + 1218 => x"81", + 1219 => x"ae", + 1220 => x"ee", + 1221 => x"d5", + 1222 => x"74", + 1223 => x"f4", + 1224 => x"2e", + 1225 => x"a0", + 1226 => x"80", + 1227 => x"18", + 1228 => x"27", + 1229 => x"22", + 1230 => x"f4", + 1231 => x"3f", + 1232 => x"ef", + 1233 => x"a5", + 1234 => x"55", + 1235 => x"18", + 1236 => x"27", + 1237 => x"08", + 1238 => x"e8", + 1239 => x"3f", + 1240 => x"ee", + 1241 => x"85", + 1242 => x"55", + 1243 => x"18", + 1244 => x"27", + 1245 => x"33", + 1246 => x"88", + 1247 => x"3f", + 1248 => x"ef", + 1249 => x"e5", + 1250 => x"55", + 1251 => x"80", + 1252 => x"39", + 1253 => x"51", + 1254 => x"80", + 1255 => x"27", + 1256 => x"18", + 1257 => x"53", + 1258 => x"7a", + 1259 => x"81", + 1260 => x"9f", + 1261 => x"38", + 1262 => x"73", + 1263 => x"ff", + 1264 => x"72", + 1265 => x"38", + 1266 => x"26", + 1267 => x"51", + 1268 => x"51", + 1269 => x"81", + 1270 => x"39", + 1271 => x"51", + 1272 => x"78", + 1273 => x"5c", + 1274 => x"3f", + 1275 => x"08", + 1276 => x"98", + 1277 => x"76", + 1278 => x"81", + 1279 => x"9b", + 1280 => x"85", + 1281 => x"2b", + 1282 => x"70", + 1283 => x"09", + 1284 => x"9b", + 1285 => x"81", + 1286 => x"07", + 1287 => x"06", + 1288 => x"59", + 1289 => x"80", + 1290 => x"38", + 1291 => x"09", + 1292 => x"38", + 1293 => x"39", + 1294 => x"72", + 1295 => x"c9", + 1296 => x"72", + 1297 => x"0c", + 1298 => x"04", + 1299 => x"02", + 1300 => x"81", + 1301 => x"81", + 1302 => x"55", + 1303 => x"82", + 1304 => x"51", + 1305 => x"81", + 1306 => x"81", + 1307 => x"82", + 1308 => x"52", + 1309 => x"51", + 1310 => x"74", + 1311 => x"38", + 1312 => x"86", + 1313 => x"fe", + 1314 => x"c0", + 1315 => x"53", + 1316 => x"81", + 1317 => x"3f", + 1318 => x"51", + 1319 => x"80", + 1320 => x"3f", + 1321 => x"70", + 1322 => x"52", + 1323 => x"92", + 1324 => x"96", + 1325 => x"ef", + 1326 => x"c2", + 1327 => x"96", + 1328 => x"82", + 1329 => x"06", + 1330 => x"80", + 1331 => x"81", + 1332 => x"3f", + 1333 => x"51", + 1334 => x"80", + 1335 => x"3f", + 1336 => x"70", + 1337 => x"52", + 1338 => x"92", + 1339 => x"96", + 1340 => x"f0", + 1341 => x"86", + 1342 => x"96", + 1343 => x"84", + 1344 => x"06", + 1345 => x"80", + 1346 => x"81", + 1347 => x"3f", + 1348 => x"51", + 1349 => x"80", + 1350 => x"3f", + 1351 => x"70", + 1352 => x"52", + 1353 => x"92", + 1354 => x"95", + 1355 => x"f0", + 1356 => x"ca", + 1357 => x"95", + 1358 => x"86", + 1359 => x"06", + 1360 => x"80", + 1361 => x"81", + 1362 => x"3f", + 1363 => x"51", + 1364 => x"80", + 1365 => x"3f", + 1366 => x"70", + 1367 => x"52", + 1368 => x"92", + 1369 => x"95", + 1370 => x"f0", + 1371 => x"8e", + 1372 => x"95", + 1373 => x"88", + 1374 => x"06", + 1375 => x"80", + 1376 => x"81", + 1377 => x"3f", + 1378 => x"51", + 1379 => x"80", + 1380 => x"3f", + 1381 => x"84", + 1382 => x"fb", + 1383 => x"02", + 1384 => x"05", + 1385 => x"56", + 1386 => x"75", + 1387 => x"3f", + 1388 => x"80", + 1389 => x"73", + 1390 => x"53", + 1391 => x"52", + 1392 => x"51", + 1393 => x"3f", + 1394 => x"08", + 1395 => x"70", + 1396 => x"08", + 1397 => x"82", + 1398 => x"51", + 1399 => x"0b", + 1400 => x"34", + 1401 => x"80", + 1402 => x"73", + 1403 => x"81", + 1404 => x"82", + 1405 => x"74", + 1406 => x"81", + 1407 => x"82", + 1408 => x"80", + 1409 => x"82", + 1410 => x"51", + 1411 => x"91", + 1412 => x"cc", + 1413 => x"99", + 1414 => x"0b", + 1415 => x"e8", + 1416 => x"82", + 1417 => x"54", + 1418 => x"09", + 1419 => x"38", + 1420 => x"53", + 1421 => x"51", + 1422 => x"80", + 1423 => x"ec", + 1424 => x"0d", + 1425 => x"0d", + 1426 => x"82", + 1427 => x"5f", + 1428 => x"7c", + 1429 => x"93", + 1430 => x"ec", + 1431 => x"06", + 1432 => x"2e", + 1433 => x"a1", + 1434 => x"d4", + 1435 => x"70", + 1436 => x"ff", + 1437 => x"78", + 1438 => x"f8", + 1439 => x"dd", + 1440 => x"ec", + 1441 => x"88", + 1442 => x"d8", + 1443 => x"39", + 1444 => x"5d", + 1445 => x"51", + 1446 => x"96", + 1447 => x"5a", + 1448 => x"79", + 1449 => x"3f", + 1450 => x"84", + 1451 => x"d4", + 1452 => x"ec", + 1453 => x"70", + 1454 => x"59", + 1455 => x"2e", + 1456 => x"78", + 1457 => x"b2", + 1458 => x"2e", + 1459 => x"78", + 1460 => x"38", + 1461 => x"ff", + 1462 => x"bc", + 1463 => x"38", + 1464 => x"78", + 1465 => x"83", + 1466 => x"80", + 1467 => x"cd", + 1468 => x"2e", + 1469 => x"8a", + 1470 => x"80", + 1471 => x"c3", + 1472 => x"f9", + 1473 => x"78", + 1474 => x"87", + 1475 => x"80", + 1476 => x"8c", + 1477 => x"39", + 1478 => x"2e", + 1479 => x"78", + 1480 => x"8b", + 1481 => x"82", + 1482 => x"38", + 1483 => x"78", + 1484 => x"89", + 1485 => x"e5", + 1486 => x"ff", + 1487 => x"ff", + 1488 => x"a8", + 1489 => x"85", + 1490 => x"2e", + 1491 => x"b4", + 1492 => x"11", + 1493 => x"05", + 1494 => x"3f", + 1495 => x"08", + 1496 => x"b0", + 1497 => x"fe", + 1498 => x"ff", + 1499 => x"a7", + 1500 => x"85", + 1501 => x"38", + 1502 => x"08", + 1503 => x"94", + 1504 => x"3f", + 1505 => x"5a", + 1506 => x"81", + 1507 => x"59", + 1508 => x"84", + 1509 => x"7a", + 1510 => x"38", + 1511 => x"b4", + 1512 => x"11", + 1513 => x"05", + 1514 => x"3f", + 1515 => x"08", + 1516 => x"e0", + 1517 => x"fe", + 1518 => x"ff", + 1519 => x"a7", + 1520 => x"85", + 1521 => x"2e", + 1522 => x"b4", + 1523 => x"11", + 1524 => x"05", + 1525 => x"3f", + 1526 => x"08", + 1527 => x"b4", + 1528 => x"a4", + 1529 => x"3f", + 1530 => x"63", + 1531 => x"38", + 1532 => x"70", + 1533 => x"33", + 1534 => x"81", + 1535 => x"39", + 1536 => x"80", + 1537 => x"84", + 1538 => x"c9", + 1539 => x"ec", + 1540 => x"fc", + 1541 => x"3d", + 1542 => x"53", + 1543 => x"51", + 1544 => x"82", + 1545 => x"80", + 1546 => x"38", + 1547 => x"f8", + 1548 => x"84", + 1549 => x"9d", + 1550 => x"ec", + 1551 => x"fc", + 1552 => x"f2", + 1553 => x"a5", + 1554 => x"79", + 1555 => x"38", + 1556 => x"7b", + 1557 => x"5b", + 1558 => x"91", + 1559 => x"7a", + 1560 => x"53", + 1561 => x"f2", + 1562 => x"f1", + 1563 => x"62", + 1564 => x"5a", + 1565 => x"f2", + 1566 => x"bb", + 1567 => x"ff", + 1568 => x"ff", + 1569 => x"a5", + 1570 => x"85", + 1571 => x"df", + 1572 => x"d8", + 1573 => x"80", + 1574 => x"82", + 1575 => x"44", + 1576 => x"82", + 1577 => x"59", + 1578 => x"88", + 1579 => x"98", + 1580 => x"39", + 1581 => x"33", + 1582 => x"2e", + 1583 => x"84", + 1584 => x"ab", + 1585 => x"db", + 1586 => x"80", + 1587 => x"82", + 1588 => x"44", + 1589 => x"84", + 1590 => x"78", + 1591 => x"38", + 1592 => x"08", + 1593 => x"82", + 1594 => x"fc", + 1595 => x"b4", + 1596 => x"11", + 1597 => x"05", + 1598 => x"3f", + 1599 => x"08", + 1600 => x"82", + 1601 => x"59", + 1602 => x"89", + 1603 => x"94", + 1604 => x"cc", + 1605 => x"d9", + 1606 => x"80", + 1607 => x"82", + 1608 => x"43", + 1609 => x"84", + 1610 => x"78", + 1611 => x"38", + 1612 => x"08", + 1613 => x"82", + 1614 => x"59", + 1615 => x"88", + 1616 => x"ac", + 1617 => x"39", + 1618 => x"33", + 1619 => x"2e", + 1620 => x"84", + 1621 => x"88", + 1622 => x"c0", + 1623 => x"43", + 1624 => x"f8", + 1625 => x"84", + 1626 => x"e9", + 1627 => x"ec", + 1628 => x"a9", + 1629 => x"5c", + 1630 => x"2e", + 1631 => x"5c", + 1632 => x"70", + 1633 => x"70", + 1634 => x"2a", + 1635 => x"51", + 1636 => x"78", + 1637 => x"38", + 1638 => x"83", + 1639 => x"81", + 1640 => x"9b", + 1641 => x"55", + 1642 => x"53", + 1643 => x"51", + 1644 => x"81", + 1645 => x"9b", + 1646 => x"d8", + 1647 => x"ff", + 1648 => x"ff", + 1649 => x"a3", + 1650 => x"85", + 1651 => x"2e", + 1652 => x"b4", + 1653 => x"11", + 1654 => x"05", + 1655 => x"3f", + 1656 => x"08", + 1657 => x"38", + 1658 => x"80", + 1659 => x"79", + 1660 => x"05", + 1661 => x"fe", + 1662 => x"ff", + 1663 => x"a2", + 1664 => x"85", + 1665 => x"38", + 1666 => x"63", + 1667 => x"52", + 1668 => x"51", + 1669 => x"80", + 1670 => x"51", + 1671 => x"79", + 1672 => x"59", + 1673 => x"f8", + 1674 => x"79", + 1675 => x"b4", + 1676 => x"11", + 1677 => x"05", + 1678 => x"3f", + 1679 => x"08", + 1680 => x"38", + 1681 => x"80", + 1682 => x"79", + 1683 => x"05", + 1684 => x"39", + 1685 => x"51", + 1686 => x"ff", + 1687 => x"3d", + 1688 => x"53", + 1689 => x"51", + 1690 => x"82", + 1691 => x"80", + 1692 => x"38", + 1693 => x"f0", + 1694 => x"84", + 1695 => x"d1", + 1696 => x"ec", + 1697 => x"a5", + 1698 => x"02", + 1699 => x"79", + 1700 => x"5b", + 1701 => x"b4", + 1702 => x"11", + 1703 => x"05", + 1704 => x"3f", + 1705 => x"08", + 1706 => x"e8", + 1707 => x"22", + 1708 => x"f3", + 1709 => x"a5", + 1710 => x"52", + 1711 => x"f7", + 1712 => x"79", + 1713 => x"ae", + 1714 => x"38", + 1715 => x"87", + 1716 => x"05", + 1717 => x"b4", + 1718 => x"11", + 1719 => x"05", + 1720 => x"3f", + 1721 => x"08", + 1722 => x"38", + 1723 => x"be", + 1724 => x"70", + 1725 => x"23", + 1726 => x"b1", + 1727 => x"84", + 1728 => x"3f", + 1729 => x"b4", + 1730 => x"11", + 1731 => x"05", + 1732 => x"3f", + 1733 => x"08", + 1734 => x"f8", + 1735 => x"fe", + 1736 => x"ff", + 1737 => x"a2", + 1738 => x"85", + 1739 => x"2e", + 1740 => x"60", + 1741 => x"60", + 1742 => x"b4", + 1743 => x"11", + 1744 => x"05", + 1745 => x"3f", + 1746 => x"08", + 1747 => x"c4", + 1748 => x"08", + 1749 => x"f3", + 1750 => x"81", + 1751 => x"52", + 1752 => x"d3", + 1753 => x"79", + 1754 => x"ae", + 1755 => x"38", + 1756 => x"9b", + 1757 => x"fe", + 1758 => x"ff", + 1759 => x"a1", + 1760 => x"85", + 1761 => x"2e", + 1762 => x"60", + 1763 => x"60", + 1764 => x"ff", + 1765 => x"f3", + 1766 => x"d1", + 1767 => x"39", + 1768 => x"80", + 1769 => x"84", + 1770 => x"a9", + 1771 => x"ec", + 1772 => x"f5", + 1773 => x"52", + 1774 => x"51", + 1775 => x"63", + 1776 => x"b4", + 1777 => x"11", + 1778 => x"05", + 1779 => x"3f", + 1780 => x"08", + 1781 => x"bc", + 1782 => x"81", + 1783 => x"9c", + 1784 => x"59", + 1785 => x"85", + 1786 => x"2e", + 1787 => x"82", + 1788 => x"52", + 1789 => x"51", + 1790 => x"f5", + 1791 => x"f3", + 1792 => x"e9", + 1793 => x"3f", + 1794 => x"81", + 1795 => x"96", + 1796 => x"59", + 1797 => x"90", + 1798 => x"f8", + 1799 => x"79", + 1800 => x"80", + 1801 => x"38", + 1802 => x"59", + 1803 => x"81", + 1804 => x"3d", + 1805 => x"51", + 1806 => x"82", + 1807 => x"5c", + 1808 => x"82", + 1809 => x"7a", + 1810 => x"38", + 1811 => x"8c", + 1812 => x"39", + 1813 => x"ae", + 1814 => x"39", + 1815 => x"56", + 1816 => x"f4", + 1817 => x"53", + 1818 => x"52", + 1819 => x"b0", + 1820 => x"ff", + 1821 => x"81", + 1822 => x"b4", + 1823 => x"05", + 1824 => x"3f", + 1825 => x"55", + 1826 => x"54", + 1827 => x"f4", + 1828 => x"3d", + 1829 => x"51", + 1830 => x"92", + 1831 => x"80", + 1832 => x"cc", + 1833 => x"ff", + 1834 => x"9b", + 1835 => x"84", + 1836 => x"85", + 1837 => x"56", + 1838 => x"54", + 1839 => x"53", + 1840 => x"52", + 1841 => x"b0", + 1842 => x"dc", + 1843 => x"ec", + 1844 => x"ec", + 1845 => x"09", + 1846 => x"72", + 1847 => x"51", + 1848 => x"80", + 1849 => x"26", + 1850 => x"5a", + 1851 => x"59", + 1852 => x"8d", + 1853 => x"70", + 1854 => x"5c", + 1855 => x"c2", + 1856 => x"32", + 1857 => x"07", + 1858 => x"38", + 1859 => x"09", + 1860 => x"80", + 1861 => x"d4", + 1862 => x"3f", + 1863 => x"fc", + 1864 => x"0b", + 1865 => x"34", + 1866 => x"8c", + 1867 => x"55", + 1868 => x"52", + 1869 => x"d4", + 1870 => x"ec", + 1871 => x"75", + 1872 => x"87", + 1873 => x"73", + 1874 => x"3f", + 1875 => x"ec", + 1876 => x"0c", + 1877 => x"9c", + 1878 => x"55", + 1879 => x"52", + 1880 => x"a8", + 1881 => x"ec", + 1882 => x"75", + 1883 => x"87", + 1884 => x"73", + 1885 => x"3f", + 1886 => x"ec", + 1887 => x"0c", + 1888 => x"0b", + 1889 => x"84", + 1890 => x"83", + 1891 => x"94", + 1892 => x"c0", + 1893 => x"9c", + 1894 => x"c3", + 1895 => x"9c", + 1896 => x"98", + 1897 => x"3f", + 1898 => x"51", + 1899 => x"81", + 1900 => x"93", + 1901 => x"85", + 1902 => x"3f", + 1903 => x"8c", + 1904 => x"3f", + 1905 => x"3d", + 1906 => x"83", + 1907 => x"2b", + 1908 => x"3f", + 1909 => x"08", + 1910 => x"72", + 1911 => x"54", + 1912 => x"25", + 1913 => x"82", + 1914 => x"84", + 1915 => x"fc", + 1916 => x"70", + 1917 => x"80", + 1918 => x"72", + 1919 => x"8c", + 1920 => x"51", + 1921 => x"09", + 1922 => x"38", + 1923 => x"f1", + 1924 => x"51", + 1925 => x"09", + 1926 => x"38", + 1927 => x"81", + 1928 => x"73", + 1929 => x"81", + 1930 => x"84", + 1931 => x"52", + 1932 => x"52", + 1933 => x"2e", + 1934 => x"54", + 1935 => x"9d", + 1936 => x"38", + 1937 => x"12", + 1938 => x"33", + 1939 => x"a0", + 1940 => x"81", + 1941 => x"2e", + 1942 => x"ea", + 1943 => x"33", + 1944 => x"a0", + 1945 => x"06", + 1946 => x"54", + 1947 => x"70", + 1948 => x"70", + 1949 => x"07", + 1950 => x"70", + 1951 => x"38", + 1952 => x"81", + 1953 => x"71", + 1954 => x"51", + 1955 => x"ec", + 1956 => x"0d", + 1957 => x"0d", + 1958 => x"08", + 1959 => x"38", + 1960 => x"05", + 1961 => x"9b", + 1962 => x"85", + 1963 => x"38", + 1964 => x"39", + 1965 => x"82", + 1966 => x"86", + 1967 => x"fc", + 1968 => x"82", + 1969 => x"05", + 1970 => x"52", + 1971 => x"81", + 1972 => x"13", + 1973 => x"51", + 1974 => x"9e", + 1975 => x"38", + 1976 => x"51", + 1977 => x"97", + 1978 => x"38", + 1979 => x"51", + 1980 => x"bb", + 1981 => x"38", + 1982 => x"51", + 1983 => x"bb", + 1984 => x"38", + 1985 => x"55", + 1986 => x"87", + 1987 => x"d9", + 1988 => x"22", + 1989 => x"73", + 1990 => x"80", + 1991 => x"0b", + 1992 => x"9c", + 1993 => x"87", + 1994 => x"0c", + 1995 => x"87", + 1996 => x"0c", + 1997 => x"87", + 1998 => x"0c", + 1999 => x"87", + 2000 => x"0c", + 2001 => x"87", + 2002 => x"0c", + 2003 => x"87", + 2004 => x"0c", + 2005 => x"98", + 2006 => x"87", + 2007 => x"0c", + 2008 => x"c0", + 2009 => x"80", + 2010 => x"85", + 2011 => x"3d", + 2012 => x"3d", + 2013 => x"87", + 2014 => x"5d", + 2015 => x"87", + 2016 => x"08", + 2017 => x"23", + 2018 => x"b8", + 2019 => x"82", + 2020 => x"c0", + 2021 => x"5a", + 2022 => x"34", + 2023 => x"b0", + 2024 => x"84", + 2025 => x"c0", + 2026 => x"5a", + 2027 => x"34", + 2028 => x"a8", + 2029 => x"86", + 2030 => x"c0", + 2031 => x"5c", + 2032 => x"23", + 2033 => x"a0", + 2034 => x"8a", + 2035 => x"7d", + 2036 => x"ff", + 2037 => x"7b", + 2038 => x"06", + 2039 => x"33", + 2040 => x"33", + 2041 => x"33", + 2042 => x"33", + 2043 => x"33", + 2044 => x"ff", + 2045 => x"81", + 2046 => x"94", + 2047 => x"3d", + 2048 => x"3d", + 2049 => x"05", + 2050 => x"81", + 2051 => x"2a", + 2052 => x"70", + 2053 => x"34", + 2054 => x"04", + 2055 => x"77", + 2056 => x"33", + 2057 => x"06", + 2058 => x"87", + 2059 => x"51", + 2060 => x"86", + 2061 => x"94", + 2062 => x"08", + 2063 => x"70", + 2064 => x"54", + 2065 => x"2e", + 2066 => x"91", + 2067 => x"06", + 2068 => x"d7", + 2069 => x"32", + 2070 => x"51", + 2071 => x"2e", + 2072 => x"93", + 2073 => x"06", + 2074 => x"ff", + 2075 => x"81", + 2076 => x"87", + 2077 => x"52", + 2078 => x"86", + 2079 => x"94", + 2080 => x"72", + 2081 => x"85", + 2082 => x"3d", + 2083 => x"3d", + 2084 => x"05", + 2085 => x"8c", + 2086 => x"ff", + 2087 => x"56", + 2088 => x"84", + 2089 => x"2e", + 2090 => x"c0", + 2091 => x"70", + 2092 => x"2a", + 2093 => x"53", + 2094 => x"80", + 2095 => x"71", + 2096 => x"81", + 2097 => x"70", + 2098 => x"81", + 2099 => x"06", + 2100 => x"80", + 2101 => x"71", + 2102 => x"81", + 2103 => x"70", + 2104 => x"73", + 2105 => x"51", + 2106 => x"80", + 2107 => x"2e", + 2108 => x"c0", + 2109 => x"75", + 2110 => x"3d", + 2111 => x"3d", + 2112 => x"80", + 2113 => x"81", + 2114 => x"53", + 2115 => x"2e", + 2116 => x"71", + 2117 => x"81", + 2118 => x"8c", + 2119 => x"ff", + 2120 => x"55", + 2121 => x"94", + 2122 => x"80", + 2123 => x"87", + 2124 => x"51", + 2125 => x"96", + 2126 => x"06", + 2127 => x"70", + 2128 => x"38", + 2129 => x"70", + 2130 => x"51", + 2131 => x"72", + 2132 => x"81", + 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x"c0", + 2251 => x"70", + 2252 => x"06", + 2253 => x"70", + 2254 => x"38", + 2255 => x"82", + 2256 => x"80", + 2257 => x"9e", + 2258 => x"88", + 2259 => x"51", + 2260 => x"80", + 2261 => x"81", + 2262 => x"84", + 2263 => x"0b", + 2264 => x"90", + 2265 => x"80", + 2266 => x"52", + 2267 => x"2e", + 2268 => x"52", + 2269 => x"d9", + 2270 => x"87", + 2271 => x"08", + 2272 => x"80", + 2273 => x"52", + 2274 => x"83", + 2275 => x"71", + 2276 => x"34", + 2277 => x"c0", + 2278 => x"70", + 2279 => x"06", + 2280 => x"70", + 2281 => x"38", + 2282 => x"82", + 2283 => x"80", + 2284 => x"9e", + 2285 => x"82", + 2286 => x"51", + 2287 => x"80", + 2288 => x"81", + 2289 => x"84", + 2290 => x"0b", + 2291 => x"90", + 2292 => x"80", + 2293 => x"52", + 2294 => x"2e", + 2295 => x"52", + 2296 => x"dd", + 2297 => x"87", + 2298 => x"08", + 2299 => x"80", + 2300 => x"52", + 2301 => x"83", + 2302 => x"71", + 2303 => x"34", + 2304 => x"c0", + 2305 => x"70", + 2306 => x"51", + 2307 => x"80", + 2308 => x"81", + 2309 => x"84", + 2310 => x"c0", + 2311 => x"70", + 2312 => x"70", + 2313 => x"51", + 2314 => x"84", + 2315 => x"0b", + 2316 => x"90", + 2317 => x"80", + 2318 => x"52", + 2319 => x"83", + 2320 => x"71", + 2321 => x"34", + 2322 => x"90", + 2323 => x"f0", + 2324 => x"2a", + 2325 => x"70", + 2326 => x"34", + 2327 => x"c0", + 2328 => x"70", + 2329 => x"52", + 2330 => x"2e", + 2331 => x"52", + 2332 => x"e3", + 2333 => x"9e", + 2334 => x"87", + 2335 => x"70", + 2336 => x"34", + 2337 => x"04", + 2338 => x"81", + 2339 => x"85", + 2340 => x"84", + 2341 => x"73", + 2342 => x"38", + 2343 => x"51", + 2344 => x"81", + 2345 => x"85", + 2346 => x"84", + 2347 => x"73", + 2348 => x"38", + 2349 => x"08", + 2350 => x"08", + 2351 => x"81", + 2352 => x"8b", + 2353 => x"84", + 2354 => x"73", + 2355 => x"38", + 2356 => x"08", + 2357 => x"08", + 2358 => x"81", + 2359 => x"8a", + 2360 => x"84", + 2361 => x"73", + 2362 => x"38", + 2363 => x"08", + 2364 => x"08", + 2365 => x"81", + 2366 => x"8a", + 2367 => x"84", + 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x"fa", + 2486 => x"39", + 2487 => x"51", + 2488 => x"fa", + 2489 => x"39", + 2490 => x"51", + 2491 => x"fa", + 2492 => x"f9", + 2493 => x"0d", + 2494 => x"80", + 2495 => x"0b", + 2496 => x"84", + 2497 => x"84", + 2498 => x"c0", + 2499 => x"04", + 2500 => x"02", + 2501 => x"53", + 2502 => x"09", + 2503 => x"38", + 2504 => x"3f", + 2505 => x"08", + 2506 => x"2e", + 2507 => x"72", + 2508 => x"fc", + 2509 => x"82", + 2510 => x"8f", + 2511 => x"f4", + 2512 => x"80", + 2513 => x"72", + 2514 => x"84", + 2515 => x"fe", + 2516 => x"97", + 2517 => x"9c", + 2518 => x"82", + 2519 => x"54", + 2520 => x"3f", + 2521 => x"f4", + 2522 => x"0d", + 2523 => x"0d", + 2524 => x"33", + 2525 => x"06", + 2526 => x"80", + 2527 => x"72", + 2528 => x"51", + 2529 => x"ff", + 2530 => x"39", + 2531 => x"04", + 2532 => x"77", + 2533 => x"08", + 2534 => x"f4", + 2535 => x"73", + 2536 => x"ff", + 2537 => x"71", + 2538 => x"38", + 2539 => x"06", + 2540 => x"54", + 2541 => x"e7", + 2542 => x"9c", + 2543 => x"3d", + 2544 => x"3d", + 2545 => x"59", + 2546 => x"81", + 2547 => x"56", + 2548 => x"85", + 2549 => x"a5", + 2550 => x"06", + 2551 => x"80", + 2552 => x"81", + 2553 => x"58", + 2554 => x"b0", + 2555 => x"06", + 2556 => x"5a", + 2557 => x"ad", + 2558 => x"06", + 2559 => x"5a", + 2560 => x"05", + 2561 => x"75", + 2562 => x"81", + 2563 => x"77", + 2564 => x"08", + 2565 => x"05", + 2566 => x"5d", + 2567 => x"39", + 2568 => x"72", + 2569 => x"38", + 2570 => x"7b", + 2571 => x"18", + 2572 => x"70", + 2573 => x"33", + 2574 => x"53", + 2575 => x"80", + 2576 => x"09", + 2577 => x"72", + 2578 => x"78", + 2579 => x"70", + 2580 => x"70", + 2581 => x"25", + 2582 => x"54", + 2583 => x"53", + 2584 => x"8c", + 2585 => x"07", + 2586 => x"05", + 2587 => x"5a", + 2588 => x"83", + 2589 => x"54", + 2590 => x"27", + 2591 => x"16", + 2592 => x"06", + 2593 => x"80", + 2594 => x"aa", + 2595 => x"cf", + 2596 => x"73", + 2597 => x"81", + 2598 => x"80", + 2599 => x"38", + 2600 => x"2e", + 2601 => x"81", + 2602 => x"80", + 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x"be", + 2721 => x"fc", + 2722 => x"73", + 2723 => x"82", + 2724 => x"84", + 2725 => x"fd", + 2726 => x"9c", + 2727 => x"82", + 2728 => x"87", + 2729 => x"53", + 2730 => x"fa", + 2731 => x"82", + 2732 => x"85", + 2733 => x"fb", + 2734 => x"79", + 2735 => x"08", + 2736 => x"57", + 2737 => x"71", + 2738 => x"e3", + 2739 => x"f8", + 2740 => x"2d", + 2741 => x"08", + 2742 => x"53", + 2743 => x"80", + 2744 => x"8d", + 2745 => x"72", + 2746 => x"09", + 2747 => x"80", + 2748 => x"52", + 2749 => x"8b", + 2750 => x"2e", + 2751 => x"14", + 2752 => x"9f", + 2753 => x"38", + 2754 => x"73", + 2755 => x"bd", + 2756 => x"52", + 2757 => x"81", + 2758 => x"51", + 2759 => x"ff", + 2760 => x"15", + 2761 => x"34", + 2762 => x"e4", + 2763 => x"72", + 2764 => x"0c", + 2765 => x"04", + 2766 => x"82", + 2767 => x"75", + 2768 => x"0c", + 2769 => x"52", + 2770 => x"3f", + 2771 => x"f8", + 2772 => x"0d", + 2773 => x"0d", + 2774 => x"56", + 2775 => x"0c", + 2776 => x"70", + 2777 => x"73", + 2778 => x"81", + 2779 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2838 => x"0c", + 2839 => x"70", + 2840 => x"73", + 2841 => x"81", + 2842 => x"81", + 2843 => x"ed", + 2844 => x"2e", + 2845 => x"8e", + 2846 => x"08", + 2847 => x"76", + 2848 => x"56", + 2849 => x"b0", + 2850 => x"06", + 2851 => x"75", + 2852 => x"76", + 2853 => x"70", + 2854 => x"73", + 2855 => x"8b", + 2856 => x"73", + 2857 => x"85", + 2858 => x"82", + 2859 => x"76", + 2860 => x"70", + 2861 => x"ac", + 2862 => x"a0", + 2863 => x"84", + 2864 => x"53", + 2865 => x"57", + 2866 => x"98", + 2867 => x"39", + 2868 => x"80", + 2869 => x"26", + 2870 => x"86", + 2871 => x"80", + 2872 => x"57", + 2873 => x"74", + 2874 => x"38", + 2875 => x"27", + 2876 => x"14", + 2877 => x"06", + 2878 => x"14", + 2879 => x"06", + 2880 => x"74", + 2881 => x"f9", + 2882 => x"ff", + 2883 => x"89", + 2884 => x"38", + 2885 => x"c5", + 2886 => x"74", + 2887 => x"3f", + 2888 => x"08", + 2889 => x"81", + 2890 => x"76", + 2891 => x"56", + 2892 => x"b2", + 2893 => x"2e", + 2894 => x"09", + 2895 => x"74", + 2896 => x"55", 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x"08", + 2956 => x"74", + 2957 => x"38", + 2958 => x"52", + 2959 => x"b8", + 2960 => x"85", + 2961 => x"05", + 2962 => x"85", + 2963 => x"81", + 2964 => x"93", + 2965 => x"38", + 2966 => x"85", + 2967 => x"80", + 2968 => x"82", + 2969 => x"56", + 2970 => x"ac", + 2971 => x"bc", + 2972 => x"a4", + 2973 => x"fc", + 2974 => x"53", + 2975 => x"51", + 2976 => x"3f", + 2977 => x"08", + 2978 => x"81", + 2979 => x"82", + 2980 => x"51", + 2981 => x"3f", + 2982 => x"04", + 2983 => x"82", + 2984 => x"93", + 2985 => x"52", + 2986 => x"89", + 2987 => x"98", + 2988 => x"73", + 2989 => x"84", + 2990 => x"73", + 2991 => x"38", + 2992 => x"85", + 2993 => x"85", + 2994 => x"71", + 2995 => x"38", + 2996 => x"d9", + 2997 => x"85", + 2998 => x"98", + 2999 => x"0b", + 3000 => x"0c", + 3001 => x"04", + 3002 => x"81", + 3003 => x"82", + 3004 => x"51", + 3005 => x"3f", + 3006 => x"08", + 3007 => x"82", + 3008 => x"53", + 3009 => x"88", + 3010 => x"56", + 3011 => x"3f", + 3012 => x"08", + 3013 => x"38", + 3014 => x"b5", + 3015 => x"85", + 3016 => x"80", + 3017 => x"ec", + 3018 => x"38", + 3019 => x"08", + 3020 => x"17", + 3021 => x"74", + 3022 => x"76", + 3023 => x"81", + 3024 => x"57", + 3025 => x"74", + 3026 => x"81", + 3027 => x"38", + 3028 => x"04", + 3029 => x"aa", + 3030 => x"3d", + 3031 => x"81", + 3032 => x"80", + 3033 => x"c0", + 3034 => x"dd", + 3035 => x"85", + 3036 => x"96", + 3037 => x"82", + 3038 => x"54", + 3039 => x"52", + 3040 => x"52", + 3041 => x"ba", + 3042 => x"ec", + 3043 => x"a5", + 3044 => x"ff", + 3045 => x"82", + 3046 => x"81", + 3047 => x"80", + 3048 => x"ec", + 3049 => x"38", + 3050 => x"08", + 3051 => x"17", + 3052 => x"74", + 3053 => x"70", + 3054 => x"70", + 3055 => x"2a", + 3056 => x"78", + 3057 => x"38", + 3058 => x"38", + 3059 => x"08", + 3060 => x"53", + 3061 => x"e7", + 3062 => x"ec", + 3063 => x"88", + 3064 => x"f4", + 3065 => x"3f", + 3066 => x"09", + 3067 => x"38", + 3068 => x"51", + 3069 => x"3f", + 3070 => x"b3", + 3071 => x"3d", + 3072 => x"85", + 3073 => x"34", + 3074 => x"82", + 3075 => x"a9", + 3076 => x"f6", + 3077 => x"7e", + 3078 => x"72", + 3079 => x"5a", + 3080 => x"2e", + 3081 => x"a2", + 3082 => x"78", + 3083 => x"76", + 3084 => x"81", + 3085 => x"70", + 3086 => x"58", + 3087 => x"2e", + 3088 => x"86", + 3089 => x"26", + 3090 => x"55", + 3091 => x"82", + 3092 => x"70", + 3093 => x"54", + 3094 => x"3f", + 3095 => x"08", + 3096 => x"73", + 3097 => x"b5", + 3098 => x"85", + 3099 => x"c3", + 3100 => x"33", + 3101 => x"2e", + 3102 => x"82", + 3103 => x"b3", + 3104 => x"3f", + 3105 => x"1a", + 3106 => x"fc", + 3107 => x"05", + 3108 => x"3f", + 3109 => x"08", + 3110 => x"38", + 3111 => x"78", + 3112 => x"fd", + 3113 => x"85", + 3114 => x"ff", + 3115 => x"80", + 3116 => x"81", + 3117 => x"ff", + 3118 => x"82", + 3119 => x"8c", + 3120 => x"73", + 3121 => x"0c", + 3122 => x"04", + 3123 => x"b0", + 3124 => x"3d", + 3125 => x"08", + 3126 => x"80", + 3127 => x"34", + 3128 => x"33", + 3129 => x"08", + 3130 => x"81", + 3131 => x"82", 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x"78", + 3191 => x"82", + 3192 => x"70", + 3193 => x"98", + 3194 => x"80", + 3195 => x"2b", + 3196 => x"71", + 3197 => x"70", + 3198 => x"fa", + 3199 => x"15", + 3200 => x"51", + 3201 => x"59", + 3202 => x"58", + 3203 => x"78", + 3204 => x"38", + 3205 => x"b1", + 3206 => x"70", + 3207 => x"98", + 3208 => x"54", + 3209 => x"80", + 3210 => x"53", + 3211 => x"51", + 3212 => x"82", + 3213 => x"81", + 3214 => x"73", + 3215 => x"38", + 3216 => x"80", + 3217 => x"ae", + 3218 => x"70", + 3219 => x"98", + 3220 => x"ff", + 3221 => x"56", + 3222 => x"26", + 3223 => x"53", + 3224 => x"51", + 3225 => x"82", + 3226 => x"81", + 3227 => x"73", + 3228 => x"39", + 3229 => x"80", + 3230 => x"38", + 3231 => x"73", + 3232 => x"34", + 3233 => x"70", + 3234 => x"9d", + 3235 => x"98", + 3236 => x"2c", + 3237 => x"11", + 3238 => x"fa", + 3239 => x"5e", + 3240 => x"58", + 3241 => x"73", + 3242 => x"81", + 3243 => x"38", + 3244 => x"15", + 3245 => x"80", + 3246 => x"84", + 3247 => x"82", + 3248 => x"92", + 3249 => x"9d", + 3250 => x"82", + 3251 => x"78", + 3252 => x"75", + 3253 => x"54", + 3254 => x"fd", + 3255 => x"82", + 3256 => x"e8", + 3257 => x"04", + 3258 => x"33", + 3259 => x"2e", + 3260 => x"82", + 3261 => x"54", + 3262 => x"ab", + 3263 => x"2b", + 3264 => x"51", + 3265 => x"24", + 3266 => x"1a", + 3267 => x"81", + 3268 => x"15", + 3269 => x"70", + 3270 => x"9d", + 3271 => x"51", + 3272 => x"74", + 3273 => x"82", + 3274 => x"81", + 3275 => x"74", + 3276 => x"34", + 3277 => x"ae", + 3278 => x"34", + 3279 => x"33", + 3280 => x"25", + 3281 => x"14", + 3282 => x"9d", + 3283 => x"9d", + 3284 => x"05", + 3285 => x"70", + 3286 => x"9d", + 3287 => x"51", + 3288 => x"76", + 3289 => x"74", + 3290 => x"52", + 3291 => x"3f", + 3292 => x"98", + 3293 => x"2c", + 3294 => x"33", + 3295 => x"54", + 3296 => x"e3", + 3297 => x"8c", + 3298 => x"2b", + 3299 => x"82", + 3300 => x"59", + 3301 => x"74", + 3302 => x"a9", + 3303 => x"e6", + 3304 => x"15", + 3305 => x"70", + 3306 => x"9d", + 3307 => x"51", + 3308 => x"75", + 3309 => x"fc", + 3310 => x"7a", + 3311 => x"81", + 3312 => x"9d", + 3313 => x"52", + 3314 => x"51", + 3315 => x"81", + 3316 => x"9d", + 3317 => x"81", + 3318 => x"55", + 3319 => x"fb", + 3320 => x"9d", + 3321 => x"05", + 3322 => x"9d", + 3323 => x"15", + 3324 => x"9d", + 3325 => x"51", + 3326 => x"82", + 3327 => x"70", + 3328 => x"98", + 3329 => x"88", + 3330 => x"56", + 3331 => x"25", + 3332 => x"1a", + 3333 => x"33", + 3334 => x"33", + 3335 => x"3f", + 3336 => x"98", + 3337 => x"2c", + 3338 => x"33", + 3339 => x"54", + 3340 => x"de", + 3341 => x"e5", + 3342 => x"9d", + 3343 => x"98", + 3344 => x"2c", + 3345 => x"33", + 3346 => x"57", + 3347 => x"fa", + 3348 => x"51", + 3349 => x"81", + 3350 => x"2b", + 3351 => x"82", + 3352 => x"59", + 3353 => x"75", + 3354 => x"38", + 3355 => x"82", + 3356 => x"7a", + 3357 => x"74", + 3358 => x"e5", + 3359 => x"9d", + 3360 => x"51", + 3361 => x"82", + 3362 => x"81", + 3363 => x"73", + 3364 => x"9d", + 3365 => x"73", + 3366 => x"38", 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x"1a", + 3426 => x"54", + 3427 => x"82", + 3428 => x"70", + 3429 => x"82", + 3430 => x"58", + 3431 => x"75", + 3432 => x"f8", + 3433 => x"9d", + 3434 => x"52", + 3435 => x"51", + 3436 => x"80", + 3437 => x"8c", + 3438 => x"82", + 3439 => x"f8", + 3440 => x"b0", + 3441 => x"b8", + 3442 => x"80", + 3443 => x"74", + 3444 => x"e7", + 3445 => x"ec", + 3446 => x"88", + 3447 => x"ec", + 3448 => x"06", + 3449 => x"74", + 3450 => x"ff", + 3451 => x"93", + 3452 => x"39", + 3453 => x"82", + 3454 => x"fc", + 3455 => x"51", + 3456 => x"2e", + 3457 => x"51", + 3458 => x"3f", + 3459 => x"08", + 3460 => x"34", + 3461 => x"08", + 3462 => x"81", + 3463 => x"52", + 3464 => x"a8", + 3465 => x"1b", + 3466 => x"39", + 3467 => x"74", + 3468 => x"91", + 3469 => x"ff", + 3470 => x"99", + 3471 => x"2e", + 3472 => x"ae", + 3473 => x"ec", + 3474 => x"80", + 3475 => x"74", + 3476 => x"e7", + 3477 => x"ec", + 3478 => x"88", + 3479 => x"ec", + 3480 => x"06", + 3481 => x"74", + 3482 => x"ff", + 3483 => x"80", + 3484 => x"82", + 3485 => x"f0", + 3486 => x"54", + 3487 => x"ab", + 3488 => x"ff", + 3489 => x"82", + 3490 => x"82", + 3491 => x"82", + 3492 => x"81", + 3493 => x"05", + 3494 => x"79", + 3495 => x"fb", + 3496 => x"54", + 3497 => x"06", + 3498 => x"74", + 3499 => x"34", + 3500 => x"82", + 3501 => x"82", + 3502 => x"52", + 3503 => x"de", + 3504 => x"39", + 3505 => x"33", + 3506 => x"06", + 3507 => x"33", + 3508 => x"74", + 3509 => x"ed", + 3510 => x"54", + 3511 => x"8c", + 3512 => x"70", + 3513 => x"e0", + 3514 => x"d9", + 3515 => x"8c", + 3516 => x"80", + 3517 => x"38", + 3518 => x"94", + 3519 => x"8c", + 3520 => x"54", + 3521 => x"8c", + 3522 => x"39", + 3523 => x"83", + 3524 => x"82", + 3525 => x"82", + 3526 => x"85", + 3527 => x"80", + 3528 => x"83", + 3529 => x"ff", + 3530 => x"82", + 3531 => x"54", + 3532 => x"74", + 3533 => x"76", + 3534 => x"82", + 3535 => x"54", + 3536 => x"34", + 3537 => x"34", + 3538 => x"08", + 3539 => x"15", + 3540 => x"15", + 3541 => x"e4", + 3542 => x"e0", + 3543 => x"fe", + 3544 => x"70", + 3545 => x"06", + 3546 => x"58", + 3547 => x"74", + 3548 => x"73", + 3549 => x"82", + 3550 => x"70", + 3551 => x"85", + 3552 => x"f8", + 3553 => x"55", + 3554 => x"34", + 3555 => x"34", + 3556 => x"04", + 3557 => x"73", + 3558 => x"84", + 3559 => x"38", + 3560 => x"2a", + 3561 => x"83", + 3562 => x"51", + 3563 => x"82", + 3564 => x"83", + 3565 => x"f9", + 3566 => x"a6", + 3567 => x"84", + 3568 => x"22", + 3569 => x"85", + 3570 => x"83", + 3571 => x"74", + 3572 => x"11", + 3573 => x"12", + 3574 => x"2b", + 3575 => x"05", + 3576 => x"71", + 3577 => x"06", + 3578 => x"2a", + 3579 => x"59", + 3580 => x"57", + 3581 => x"71", + 3582 => x"81", + 3583 => x"85", + 3584 => x"75", + 3585 => x"54", + 3586 => x"34", + 3587 => x"34", + 3588 => x"08", + 3589 => x"33", + 3590 => x"71", + 3591 => x"70", + 3592 => x"ff", + 3593 => x"52", + 3594 => x"05", + 3595 => x"ff", + 3596 => x"2a", + 3597 => x"71", + 3598 => x"72", + 3599 => x"53", + 3600 => x"34", + 3601 => x"08", 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x"33", + 3661 => x"71", + 3662 => x"83", + 3663 => x"11", + 3664 => x"12", + 3665 => x"2b", + 3666 => x"2b", + 3667 => x"06", + 3668 => x"51", + 3669 => x"53", + 3670 => x"88", + 3671 => x"72", + 3672 => x"74", + 3673 => x"82", + 3674 => x"70", + 3675 => x"81", + 3676 => x"8b", + 3677 => x"2b", + 3678 => x"57", + 3679 => x"70", + 3680 => x"33", + 3681 => x"07", + 3682 => x"ff", + 3683 => x"2a", + 3684 => x"58", + 3685 => x"34", + 3686 => x"34", + 3687 => x"04", + 3688 => x"82", + 3689 => x"02", + 3690 => x"05", + 3691 => x"2b", + 3692 => x"11", + 3693 => x"33", + 3694 => x"71", + 3695 => x"59", + 3696 => x"56", + 3697 => x"71", + 3698 => x"33", + 3699 => x"07", + 3700 => x"a2", + 3701 => x"07", + 3702 => x"53", + 3703 => x"53", + 3704 => x"70", + 3705 => x"82", + 3706 => x"70", + 3707 => x"81", + 3708 => x"8b", + 3709 => x"2b", + 3710 => x"57", + 3711 => x"82", + 3712 => x"13", + 3713 => x"2b", + 3714 => x"2a", + 3715 => x"52", + 3716 => x"34", + 3717 => x"34", + 3718 => x"08", + 3719 => x"33", + 3720 => x"71", + 3721 => x"82", + 3722 => x"52", + 3723 => x"0d", + 3724 => x"0d", + 3725 => x"e4", + 3726 => x"2a", + 3727 => x"ff", + 3728 => x"57", + 3729 => x"3f", + 3730 => x"08", + 3731 => x"71", + 3732 => x"33", + 3733 => x"71", + 3734 => x"83", + 3735 => x"11", + 3736 => x"12", + 3737 => x"2b", + 3738 => x"07", + 3739 => x"51", + 3740 => x"55", + 3741 => x"80", + 3742 => x"82", + 3743 => x"75", + 3744 => x"3f", + 3745 => x"84", + 3746 => x"15", + 3747 => x"2b", + 3748 => x"07", + 3749 => x"88", + 3750 => x"55", + 3751 => x"86", + 3752 => x"81", + 3753 => x"75", + 3754 => x"82", + 3755 => x"70", + 3756 => x"33", + 3757 => x"71", + 3758 => x"70", + 3759 => x"57", + 3760 => x"72", + 3761 => x"73", + 3762 => x"82", + 3763 => x"18", + 3764 => x"86", + 3765 => x"0b", + 3766 => x"82", + 3767 => x"53", + 3768 => x"34", + 3769 => x"34", + 3770 => x"08", + 3771 => x"81", + 3772 => x"88", + 3773 => x"82", + 3774 => x"70", + 3775 => x"51", + 3776 => x"74", + 3777 => x"81", + 3778 => x"3d", + 3779 => x"3d", + 3780 => x"82", + 3781 => x"84", + 3782 => x"3f", + 3783 => x"86", + 3784 => x"fe", + 3785 => x"3d", + 3786 => x"3d", + 3787 => x"52", + 3788 => x"3f", + 3789 => x"08", + 3790 => x"06", + 3791 => x"08", + 3792 => x"85", + 3793 => x"88", + 3794 => x"5f", + 3795 => x"5a", + 3796 => x"59", + 3797 => x"80", + 3798 => x"83", + 3799 => x"70", + 3800 => x"33", + 3801 => x"07", + 3802 => x"ff", + 3803 => x"70", + 3804 => x"06", + 3805 => x"52", + 3806 => x"59", + 3807 => x"27", + 3808 => x"80", + 3809 => x"75", + 3810 => x"84", + 3811 => x"16", + 3812 => x"2b", + 3813 => x"75", + 3814 => x"81", + 3815 => x"85", + 3816 => x"59", + 3817 => x"83", + 3818 => x"e4", + 3819 => x"33", + 3820 => x"71", + 3821 => x"70", + 3822 => x"06", + 3823 => x"56", + 3824 => x"75", + 3825 => x"81", + 3826 => x"79", + 3827 => x"cc", + 3828 => x"74", + 3829 => x"c4", + 3830 => x"2e", + 3831 => x"89", + 3832 => x"f8", + 3833 => x"ac", + 3834 => x"80", + 3835 => x"75", + 3836 => x"3f", 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x"11", + 3896 => x"82", + 3897 => x"83", + 3898 => x"fc", + 3899 => x"9b", + 3900 => x"84", + 3901 => x"33", + 3902 => x"51", + 3903 => x"80", + 3904 => x"84", + 3905 => x"92", + 3906 => x"51", + 3907 => x"80", + 3908 => x"81", + 3909 => x"72", + 3910 => x"92", + 3911 => x"81", + 3912 => x"0b", + 3913 => x"8c", + 3914 => x"71", + 3915 => x"06", + 3916 => x"80", + 3917 => x"87", + 3918 => x"08", + 3919 => x"38", + 3920 => x"80", + 3921 => x"71", + 3922 => x"c0", + 3923 => x"51", + 3924 => x"87", + 3925 => x"85", + 3926 => x"82", + 3927 => x"33", + 3928 => x"85", + 3929 => x"3d", + 3930 => x"3d", + 3931 => x"64", + 3932 => x"bf", + 3933 => x"40", + 3934 => x"74", + 3935 => x"cd", + 3936 => x"ec", + 3937 => x"7a", + 3938 => x"81", + 3939 => x"72", + 3940 => x"87", + 3941 => x"11", + 3942 => x"8c", + 3943 => x"92", + 3944 => x"5a", + 3945 => x"58", + 3946 => x"c0", + 3947 => x"76", + 3948 => x"76", + 3949 => x"70", + 3950 => x"81", + 3951 => x"54", + 3952 => x"8e", + 3953 => x"52", + 3954 => x"81", + 3955 => x"81", + 3956 => x"74", + 3957 => x"53", + 3958 => x"83", + 3959 => x"78", + 3960 => x"8f", + 3961 => x"2e", + 3962 => x"c0", + 3963 => x"52", + 3964 => x"87", + 3965 => x"08", + 3966 => x"2e", + 3967 => x"84", + 3968 => x"38", + 3969 => x"87", + 3970 => x"15", + 3971 => x"70", + 3972 => x"52", + 3973 => x"ff", + 3974 => x"39", + 3975 => x"81", + 3976 => x"ff", + 3977 => x"57", + 3978 => x"90", + 3979 => x"80", + 3980 => x"71", + 3981 => x"78", + 3982 => x"38", + 3983 => x"80", + 3984 => x"80", + 3985 => x"81", + 3986 => x"72", + 3987 => x"0c", + 3988 => x"04", + 3989 => x"60", + 3990 => x"8c", + 3991 => x"33", + 3992 => x"5b", + 3993 => x"74", + 3994 => x"e1", + 3995 => x"ec", + 3996 => x"79", + 3997 => x"78", + 3998 => x"06", + 3999 => x"77", + 4000 => x"87", + 4001 => x"11", + 4002 => x"8c", + 4003 => x"92", + 4004 => x"59", + 4005 => x"85", + 4006 => x"98", + 4007 => x"7d", + 4008 => x"0c", + 4009 => x"08", + 4010 => x"70", + 4011 => x"53", + 4012 => x"2e", + 4013 => x"70", + 4014 => x"33", + 4015 => x"18", + 4016 => x"2a", + 4017 => x"51", + 4018 => x"2e", + 4019 => x"c0", + 4020 => x"52", + 4021 => x"87", + 4022 => x"08", + 4023 => x"2e", + 4024 => x"84", + 4025 => x"38", + 4026 => x"87", + 4027 => x"15", + 4028 => x"70", + 4029 => x"52", + 4030 => x"ff", + 4031 => x"39", + 4032 => x"81", + 4033 => x"80", + 4034 => x"52", + 4035 => x"90", + 4036 => x"80", + 4037 => x"71", + 4038 => x"7a", + 4039 => x"38", + 4040 => x"80", + 4041 => x"80", + 4042 => x"81", + 4043 => x"72", + 4044 => x"0c", + 4045 => x"04", + 4046 => x"7a", + 4047 => x"a3", + 4048 => x"88", + 4049 => x"33", + 4050 => x"56", + 4051 => x"3f", + 4052 => x"08", + 4053 => x"83", + 4054 => x"fe", + 4055 => x"87", + 4056 => x"0c", + 4057 => x"76", + 4058 => x"38", + 4059 => x"93", + 4060 => x"2b", + 4061 => x"8c", + 4062 => x"71", + 4063 => x"38", + 4064 => x"71", + 4065 => x"c6", + 4066 => x"39", + 4067 => x"81", + 4068 => x"06", + 4069 => x"71", + 4070 => x"38", + 4071 => x"8c", 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x"34", + 4131 => x"eb", + 4132 => x"0d", + 4133 => x"0d", + 4134 => x"54", + 4135 => x"72", + 4136 => x"54", + 4137 => x"51", + 4138 => x"84", + 4139 => x"fc", + 4140 => x"77", + 4141 => x"53", + 4142 => x"05", + 4143 => x"70", + 4144 => x"33", + 4145 => x"ff", + 4146 => x"52", + 4147 => x"2e", + 4148 => x"80", + 4149 => x"71", + 4150 => x"0c", + 4151 => x"04", + 4152 => x"74", + 4153 => x"89", + 4154 => x"2e", + 4155 => x"11", + 4156 => x"52", + 4157 => x"70", + 4158 => x"ec", + 4159 => x"0d", + 4160 => x"82", + 4161 => x"04", + 4162 => x"85", + 4163 => x"f7", + 4164 => x"56", + 4165 => x"17", + 4166 => x"74", + 4167 => x"d6", + 4168 => x"b0", + 4169 => x"b4", + 4170 => x"81", + 4171 => x"59", + 4172 => x"82", + 4173 => x"7a", + 4174 => x"06", + 4175 => x"85", + 4176 => x"17", + 4177 => x"08", + 4178 => x"08", + 4179 => x"08", + 4180 => x"74", + 4181 => x"38", + 4182 => x"55", + 4183 => x"09", + 4184 => x"38", + 4185 => x"18", + 4186 => x"81", + 4187 => x"f9", + 4188 => x"39", + 4189 => x"82", + 4190 => x"8b", + 4191 => x"fa", + 4192 => x"7a", + 4193 => x"57", + 4194 => x"08", + 4195 => x"75", + 4196 => x"3f", + 4197 => x"08", + 4198 => x"ec", + 4199 => x"81", + 4200 => x"b4", + 4201 => x"16", + 4202 => x"be", + 4203 => x"ec", + 4204 => x"85", + 4205 => x"81", + 4206 => x"17", + 4207 => x"85", + 4208 => x"3d", + 4209 => x"3d", + 4210 => x"52", + 4211 => x"3f", + 4212 => x"08", + 4213 => x"ec", + 4214 => x"38", + 4215 => x"74", + 4216 => x"81", + 4217 => x"38", + 4218 => x"59", + 4219 => x"09", + 4220 => x"e3", + 4221 => x"53", + 4222 => x"08", + 4223 => x"70", + 4224 => x"91", + 4225 => x"d5", + 4226 => x"17", + 4227 => x"3f", + 4228 => x"a4", + 4229 => x"51", + 4230 => x"86", + 4231 => x"f2", + 4232 => x"17", + 4233 => x"3f", + 4234 => x"52", + 4235 => x"51", + 4236 => x"8c", + 4237 => x"84", + 4238 => x"fc", + 4239 => x"17", + 4240 => x"70", + 4241 => x"79", + 4242 => x"52", + 4243 => x"51", + 4244 => x"77", + 4245 => x"80", + 4246 => x"81", + 4247 => x"f9", + 4248 => x"85", + 4249 => x"2e", + 4250 => x"58", + 4251 => x"ec", + 4252 => x"0d", + 4253 => x"0d", + 4254 => x"98", + 4255 => x"05", + 4256 => x"80", + 4257 => x"27", + 4258 => x"15", + 4259 => x"51", + 4260 => x"3f", + 4261 => x"82", + 4262 => x"05", + 4263 => x"85", + 4264 => x"3d", + 4265 => x"3d", + 4266 => x"70", + 4267 => x"57", + 4268 => x"81", + 4269 => x"98", + 4270 => x"81", + 4271 => x"74", + 4272 => x"72", + 4273 => x"f5", + 4274 => x"24", + 4275 => x"81", + 4276 => x"81", + 4277 => x"83", + 4278 => x"38", + 4279 => x"76", + 4280 => x"70", + 4281 => x"16", + 4282 => x"74", + 4283 => x"8f", + 4284 => x"ec", + 4285 => x"38", + 4286 => x"06", + 4287 => x"33", + 4288 => x"89", + 4289 => x"08", + 4290 => x"54", + 4291 => x"fc", + 4292 => x"85", + 4293 => x"fe", + 4294 => x"ff", + 4295 => x"11", + 4296 => x"2b", + 4297 => x"81", + 4298 => x"2a", + 4299 => x"51", + 4300 => x"e2", + 4301 => x"ff", + 4302 => x"da", + 4303 => x"2a", + 4304 => x"05", + 4305 => x"fc", + 4306 => x"85", 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x"81", + 4366 => x"83", + 4367 => x"b4", + 4368 => x"2a", + 4369 => x"8f", + 4370 => x"2a", + 4371 => x"f0", + 4372 => x"06", + 4373 => x"72", + 4374 => x"ec", + 4375 => x"2a", + 4376 => x"05", + 4377 => x"fa", + 4378 => x"85", + 4379 => x"82", + 4380 => x"80", + 4381 => x"83", + 4382 => x"52", + 4383 => x"fe", + 4384 => x"b4", + 4385 => x"9d", + 4386 => x"76", + 4387 => x"17", + 4388 => x"75", + 4389 => x"3f", + 4390 => x"08", + 4391 => x"ec", + 4392 => x"77", + 4393 => x"77", + 4394 => x"fc", + 4395 => x"b4", + 4396 => x"51", + 4397 => x"c2", + 4398 => x"ec", + 4399 => x"06", + 4400 => x"72", + 4401 => x"3f", + 4402 => x"17", + 4403 => x"85", + 4404 => x"3d", + 4405 => x"3d", + 4406 => x"7e", + 4407 => x"56", + 4408 => x"75", + 4409 => x"74", + 4410 => x"27", + 4411 => x"80", + 4412 => x"ff", + 4413 => x"75", + 4414 => x"3f", + 4415 => x"08", + 4416 => x"ec", + 4417 => x"38", + 4418 => x"54", + 4419 => x"81", + 4420 => x"39", + 4421 => x"08", + 4422 => x"39", + 4423 => x"51", + 4424 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4483 => x"70", + 4484 => x"70", + 4485 => x"25", + 4486 => x"82", + 4487 => x"54", + 4488 => x"55", + 4489 => x"38", + 4490 => x"08", + 4491 => x"38", + 4492 => x"54", + 4493 => x"90", + 4494 => x"18", + 4495 => x"38", + 4496 => x"39", + 4497 => x"38", + 4498 => x"16", + 4499 => x"08", + 4500 => x"38", + 4501 => x"78", + 4502 => x"38", + 4503 => x"51", + 4504 => x"82", + 4505 => x"80", + 4506 => x"80", + 4507 => x"ec", + 4508 => x"09", + 4509 => x"38", + 4510 => x"08", + 4511 => x"ec", + 4512 => x"09", + 4513 => x"72", + 4514 => x"70", + 4515 => x"51", + 4516 => x"80", + 4517 => x"78", + 4518 => x"06", + 4519 => x"73", + 4520 => x"39", + 4521 => x"52", + 4522 => x"f3", + 4523 => x"ec", + 4524 => x"ec", + 4525 => x"05", + 4526 => x"ec", + 4527 => x"25", + 4528 => x"79", + 4529 => x"38", + 4530 => x"8f", + 4531 => x"79", + 4532 => x"f9", + 4533 => x"85", + 4534 => x"74", + 4535 => x"8c", + 4536 => x"17", + 4537 => x"90", + 4538 => x"54", + 4539 => x"86", + 4540 => x"90", + 4541 => x"17", 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x"16", + 4601 => x"0c", + 4602 => x"8a", + 4603 => x"89", + 4604 => x"72", + 4605 => x"38", + 4606 => x"51", + 4607 => x"82", + 4608 => x"54", + 4609 => x"08", + 4610 => x"38", + 4611 => x"85", + 4612 => x"8b", + 4613 => x"08", + 4614 => x"08", + 4615 => x"82", + 4616 => x"74", + 4617 => x"cb", + 4618 => x"75", + 4619 => x"3f", + 4620 => x"08", + 4621 => x"73", + 4622 => x"98", + 4623 => x"82", + 4624 => x"2e", + 4625 => x"39", + 4626 => x"39", + 4627 => x"13", + 4628 => x"74", + 4629 => x"16", + 4630 => x"18", + 4631 => x"77", + 4632 => x"0c", + 4633 => x"04", + 4634 => x"7a", + 4635 => x"12", + 4636 => x"59", + 4637 => x"80", + 4638 => x"86", + 4639 => x"98", + 4640 => x"14", + 4641 => x"55", + 4642 => x"81", + 4643 => x"83", + 4644 => x"77", + 4645 => x"81", + 4646 => x"0c", + 4647 => x"55", + 4648 => x"76", + 4649 => x"17", + 4650 => x"74", + 4651 => x"9b", + 4652 => x"39", + 4653 => x"ff", + 4654 => x"2a", + 4655 => x"81", + 4656 => x"52", + 4657 => x"de", + 4658 => x"ec", + 4659 => x"55", + 4660 => x"85", + 4661 => x"80", + 4662 => x"55", + 4663 => x"08", + 4664 => x"f4", + 4665 => x"08", + 4666 => x"08", + 4667 => x"38", + 4668 => x"77", + 4669 => x"84", + 4670 => x"39", + 4671 => x"52", + 4672 => x"fe", + 4673 => x"ec", + 4674 => x"55", + 4675 => x"08", + 4676 => x"c4", + 4677 => x"82", + 4678 => x"81", + 4679 => x"81", + 4680 => x"ec", + 4681 => x"b0", + 4682 => x"ec", + 4683 => x"51", + 4684 => x"82", + 4685 => x"a0", + 4686 => x"15", + 4687 => x"75", + 4688 => x"3f", + 4689 => x"08", + 4690 => x"76", + 4691 => x"77", + 4692 => x"9c", + 4693 => x"55", + 4694 => x"ec", + 4695 => x"0d", + 4696 => x"0d", + 4697 => x"08", + 4698 => x"80", + 4699 => x"fc", + 4700 => x"85", + 4701 => x"82", + 4702 => x"80", + 4703 => x"85", + 4704 => x"98", + 4705 => x"78", + 4706 => x"3f", + 4707 => x"08", + 4708 => x"ec", + 4709 => x"38", + 4710 => x"08", + 4711 => x"70", + 4712 => x"58", + 4713 => x"2e", + 4714 => x"83", + 4715 => x"82", + 4716 => x"55", + 4717 => x"81", + 4718 => x"07", + 4719 => x"2e", + 4720 => x"16", + 4721 => x"2e", + 4722 => x"88", + 4723 => x"82", + 4724 => x"56", + 4725 => x"51", + 4726 => x"82", + 4727 => x"54", + 4728 => x"08", + 4729 => x"9b", + 4730 => x"2e", + 4731 => x"83", + 4732 => x"73", + 4733 => x"0c", + 4734 => x"04", + 4735 => x"76", + 4736 => x"54", + 4737 => x"82", + 4738 => x"83", + 4739 => x"76", + 4740 => x"53", + 4741 => x"2e", + 4742 => x"90", + 4743 => x"51", + 4744 => x"82", + 4745 => x"90", + 4746 => x"53", + 4747 => x"ec", + 4748 => x"0d", + 4749 => x"0d", + 4750 => x"83", + 4751 => x"54", + 4752 => x"55", + 4753 => x"3f", + 4754 => x"51", + 4755 => x"2e", + 4756 => x"8b", + 4757 => x"2a", + 4758 => x"51", + 4759 => x"86", + 4760 => x"f7", + 4761 => x"7d", + 4762 => x"75", + 4763 => x"98", + 4764 => x"2e", + 4765 => x"98", + 4766 => x"78", + 4767 => x"3f", + 4768 => x"08", + 4769 => x"ec", + 4770 => x"38", + 4771 => x"70", + 4772 => x"73", + 4773 => x"58", + 4774 => x"8b", + 4775 => x"bf", + 4776 => x"ff", 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x"7a", + 4836 => x"0b", + 4837 => x"98", + 4838 => x"2e", + 4839 => x"80", + 4840 => x"55", + 4841 => x"17", + 4842 => x"33", + 4843 => x"51", + 4844 => x"2e", + 4845 => x"85", + 4846 => x"06", + 4847 => x"e5", + 4848 => x"2e", + 4849 => x"8b", + 4850 => x"70", + 4851 => x"34", + 4852 => x"71", + 4853 => x"05", + 4854 => x"15", + 4855 => x"27", + 4856 => x"15", + 4857 => x"80", + 4858 => x"34", + 4859 => x"52", + 4860 => x"88", + 4861 => x"17", + 4862 => x"52", + 4863 => x"3f", + 4864 => x"08", + 4865 => x"12", + 4866 => x"3f", + 4867 => x"08", + 4868 => x"98", + 4869 => x"cb", + 4870 => x"ec", + 4871 => x"23", + 4872 => x"04", + 4873 => x"7f", + 4874 => x"5b", + 4875 => x"33", + 4876 => x"73", + 4877 => x"38", + 4878 => x"80", + 4879 => x"38", + 4880 => x"8c", + 4881 => x"08", + 4882 => x"ac", + 4883 => x"41", + 4884 => x"33", + 4885 => x"73", + 4886 => x"81", + 4887 => x"81", + 4888 => x"dc", + 4889 => x"81", + 4890 => x"25", + 4891 => x"51", + 4892 => x"38", + 4893 => x"0c", + 4894 => x"51", + 4895 => x"26", + 4896 => x"80", + 4897 => x"34", + 4898 => x"51", + 4899 => x"82", + 4900 => x"55", + 4901 => x"91", + 4902 => x"1d", + 4903 => x"8b", + 4904 => x"79", + 4905 => x"3f", + 4906 => x"57", + 4907 => x"55", + 4908 => x"2e", + 4909 => x"80", + 4910 => x"18", + 4911 => x"1a", + 4912 => x"70", + 4913 => x"70", + 4914 => x"82", + 4915 => x"51", + 4916 => x"54", + 4917 => x"79", + 4918 => x"74", + 4919 => x"57", + 4920 => x"af", + 4921 => x"81", + 4922 => x"2a", + 4923 => x"75", + 4924 => x"8c", + 4925 => x"2e", + 4926 => x"a0", + 4927 => x"38", + 4928 => x"0c", + 4929 => x"76", + 4930 => x"38", + 4931 => x"c2", + 4932 => x"70", + 4933 => x"5a", + 4934 => x"76", + 4935 => x"38", + 4936 => x"70", + 4937 => x"77", + 4938 => x"70", + 4939 => x"72", + 4940 => x"80", + 4941 => x"51", + 4942 => x"73", + 4943 => x"38", + 4944 => x"18", + 4945 => x"1a", + 4946 => x"55", + 4947 => x"2e", + 4948 => x"83", + 4949 => x"73", + 4950 => x"70", + 4951 => x"70", + 4952 => x"07", + 4953 => x"73", + 4954 => x"b9", + 4955 => x"2e", + 4956 => x"83", + 4957 => x"76", + 4958 => x"07", + 4959 => x"2e", + 4960 => x"8b", + 4961 => x"81", + 4962 => x"32", + 4963 => x"05", + 4964 => x"71", + 4965 => x"53", + 4966 => x"55", + 4967 => x"38", + 4968 => x"5c", + 4969 => x"75", + 4970 => x"73", + 4971 => x"38", + 4972 => x"06", + 4973 => x"11", + 4974 => x"75", + 4975 => x"3f", + 4976 => x"08", + 4977 => x"38", + 4978 => x"33", + 4979 => x"54", + 4980 => x"e6", + 4981 => x"85", + 4982 => x"2e", + 4983 => x"ff", + 4984 => x"74", + 4985 => x"38", + 4986 => x"75", + 4987 => x"17", + 4988 => x"57", + 4989 => x"a7", + 4990 => x"81", + 4991 => x"e5", + 4992 => x"85", + 4993 => x"38", + 4994 => x"54", + 4995 => x"89", + 4996 => x"70", + 4997 => x"57", + 4998 => x"54", + 4999 => x"81", + 5000 => x"ed", + 5001 => x"7e", + 5002 => x"2e", + 5003 => x"33", + 5004 => x"e5", + 5005 => x"06", + 5006 => x"7a", + 5007 => x"a0", + 5008 => x"38", + 5009 => x"55", + 5010 => x"84", + 5011 => x"39", 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x"39", + 5071 => x"ec", + 5072 => x"0d", + 5073 => x"0d", + 5074 => x"7b", + 5075 => x"73", + 5076 => x"55", + 5077 => x"2e", + 5078 => x"75", + 5079 => x"57", + 5080 => x"26", + 5081 => x"ba", + 5082 => x"70", + 5083 => x"ba", + 5084 => x"06", + 5085 => x"73", + 5086 => x"70", + 5087 => x"51", + 5088 => x"89", + 5089 => x"82", + 5090 => x"ff", + 5091 => x"56", + 5092 => x"2e", + 5093 => x"80", + 5094 => x"a4", + 5095 => x"08", + 5096 => x"76", + 5097 => x"58", + 5098 => x"81", + 5099 => x"ff", + 5100 => x"53", + 5101 => x"26", + 5102 => x"13", + 5103 => x"06", + 5104 => x"9f", + 5105 => x"99", + 5106 => x"e0", + 5107 => x"ff", + 5108 => x"72", + 5109 => x"70", + 5110 => x"51", + 5111 => x"09", + 5112 => x"38", + 5113 => x"38", + 5114 => x"05", + 5115 => x"70", + 5116 => x"70", + 5117 => x"2a", + 5118 => x"07", + 5119 => x"51", + 5120 => x"8f", + 5121 => x"84", + 5122 => x"83", + 5123 => x"8e", + 5124 => x"74", + 5125 => x"38", + 5126 => x"0c", + 5127 => x"86", + 5128 => x"a4", + 5129 => x"82", + 5130 => x"8c", + 5131 => x"fa", + 5132 => x"56", + 5133 => x"17", + 5134 => x"b0", + 5135 => x"52", + 5136 => x"bb", + 5137 => x"82", + 5138 => x"81", + 5139 => x"b2", + 5140 => x"8f", + 5141 => x"ec", + 5142 => x"ff", + 5143 => x"55", + 5144 => x"d5", + 5145 => x"06", + 5146 => x"80", + 5147 => x"33", + 5148 => x"81", + 5149 => x"81", + 5150 => x"81", + 5151 => x"eb", + 5152 => x"81", + 5153 => x"25", + 5154 => x"51", + 5155 => x"38", + 5156 => x"2e", + 5157 => x"b5", + 5158 => x"81", + 5159 => x"80", + 5160 => x"e0", + 5161 => x"85", + 5162 => x"82", + 5163 => x"80", + 5164 => x"85", + 5165 => x"e8", + 5166 => x"16", + 5167 => x"3f", + 5168 => x"08", + 5169 => x"ec", + 5170 => x"83", + 5171 => x"74", + 5172 => x"0c", + 5173 => x"04", + 5174 => x"62", + 5175 => x"80", + 5176 => x"58", + 5177 => x"0c", + 5178 => x"d9", + 5179 => x"ec", + 5180 => x"56", + 5181 => x"85", + 5182 => x"87", + 5183 => x"85", + 5184 => x"2b", + 5185 => x"11", + 5186 => x"8c", + 5187 => x"2e", + 5188 => x"73", + 5189 => x"81", + 5190 => x"33", + 5191 => x"80", + 5192 => x"81", + 5193 => x"d7", + 5194 => x"85", + 5195 => x"ff", + 5196 => x"06", + 5197 => x"98", + 5198 => x"2e", + 5199 => x"74", + 5200 => x"81", + 5201 => x"8a", + 5202 => x"b4", + 5203 => x"39", + 5204 => x"77", + 5205 => x"81", + 5206 => x"33", + 5207 => x"3f", + 5208 => x"08", + 5209 => x"70", + 5210 => x"55", + 5211 => x"86", + 5212 => x"80", + 5213 => x"74", + 5214 => x"81", + 5215 => x"8a", + 5216 => x"fc", + 5217 => x"53", + 5218 => x"fd", + 5219 => x"85", + 5220 => x"ff", + 5221 => x"82", + 5222 => x"06", + 5223 => x"8d", + 5224 => x"58", + 5225 => x"f6", + 5226 => x"58", + 5227 => x"2e", + 5228 => x"fa", + 5229 => x"c2", + 5230 => x"ec", + 5231 => x"78", + 5232 => x"5a", + 5233 => x"90", + 5234 => x"75", + 5235 => x"38", + 5236 => x"3d", + 5237 => x"70", + 5238 => x"08", + 5239 => x"7b", + 5240 => x"38", + 5241 => x"51", + 5242 => x"82", + 5243 => x"81", + 5244 => x"81", + 5245 => x"38", + 5246 => x"83", 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x"98", + 5306 => x"22", + 5307 => x"84", + 5308 => x"5b", + 5309 => x"83", + 5310 => x"14", + 5311 => x"79", + 5312 => x"f8", + 5313 => x"85", + 5314 => x"82", + 5315 => x"80", + 5316 => x"38", + 5317 => x"08", + 5318 => x"ff", + 5319 => x"38", + 5320 => x"83", + 5321 => x"83", + 5322 => x"72", + 5323 => x"85", + 5324 => x"89", + 5325 => x"76", + 5326 => x"c4", + 5327 => x"70", + 5328 => x"7c", + 5329 => x"7a", + 5330 => x"17", + 5331 => x"ac", + 5332 => x"55", + 5333 => x"09", + 5334 => x"38", + 5335 => x"51", + 5336 => x"82", + 5337 => x"83", + 5338 => x"53", + 5339 => x"82", + 5340 => x"82", + 5341 => x"e0", + 5342 => x"fe", + 5343 => x"ec", + 5344 => x"0c", + 5345 => x"53", + 5346 => x"56", + 5347 => x"81", + 5348 => x"13", + 5349 => x"74", + 5350 => x"82", + 5351 => x"74", + 5352 => x"81", + 5353 => x"06", + 5354 => x"53", + 5355 => x"89", + 5356 => x"56", + 5357 => x"08", + 5358 => x"38", + 5359 => x"15", + 5360 => x"8c", + 5361 => x"80", + 5362 => x"34", + 5363 => x"09", + 5364 => x"92", + 5365 => x"14", + 5366 => x"3f", + 5367 => x"08", + 5368 => x"06", + 5369 => x"2e", + 5370 => x"80", + 5371 => x"1c", + 5372 => x"db", + 5373 => x"85", + 5374 => x"ea", + 5375 => x"ec", + 5376 => x"34", + 5377 => x"51", + 5378 => x"82", + 5379 => x"83", + 5380 => x"53", + 5381 => x"d5", + 5382 => x"06", + 5383 => x"b4", + 5384 => x"d6", + 5385 => x"ec", + 5386 => x"85", + 5387 => x"09", + 5388 => x"38", + 5389 => x"51", + 5390 => x"82", + 5391 => x"86", + 5392 => x"f2", + 5393 => x"06", + 5394 => x"9c", + 5395 => x"aa", + 5396 => x"ec", + 5397 => x"0c", + 5398 => x"51", + 5399 => x"82", + 5400 => x"8c", + 5401 => x"74", + 5402 => x"a0", + 5403 => x"53", + 5404 => x"a0", + 5405 => x"15", + 5406 => x"94", + 5407 => x"56", + 5408 => x"ec", + 5409 => x"0d", + 5410 => x"0d", + 5411 => x"55", + 5412 => x"b9", + 5413 => x"53", + 5414 => x"b1", + 5415 => x"52", + 5416 => x"a9", + 5417 => x"22", + 5418 => x"57", + 5419 => x"2e", + 5420 => x"99", + 5421 => x"33", + 5422 => x"3f", + 5423 => x"08", + 5424 => x"71", + 5425 => x"74", + 5426 => x"83", + 5427 => x"78", + 5428 => x"52", + 5429 => x"ec", + 5430 => x"0d", + 5431 => x"0d", + 5432 => x"33", + 5433 => x"3d", + 5434 => x"56", + 5435 => x"8b", + 5436 => x"82", + 5437 => x"24", + 5438 => x"85", + 5439 => x"2b", + 5440 => x"05", + 5441 => x"55", + 5442 => x"84", + 5443 => x"34", + 5444 => x"80", + 5445 => x"80", + 5446 => x"75", + 5447 => x"75", + 5448 => x"38", + 5449 => x"3d", + 5450 => x"05", + 5451 => x"3f", + 5452 => x"08", + 5453 => x"85", + 5454 => x"3d", + 5455 => x"3d", + 5456 => x"84", + 5457 => x"05", + 5458 => x"89", + 5459 => x"2e", + 5460 => x"77", + 5461 => x"54", + 5462 => x"05", + 5463 => x"84", + 5464 => x"f6", + 5465 => x"85", + 5466 => x"82", + 5467 => x"84", + 5468 => x"5c", + 5469 => x"3d", + 5470 => x"ed", + 5471 => x"85", + 5472 => x"82", + 5473 => x"92", + 5474 => x"d7", + 5475 => x"98", + 5476 => x"73", + 5477 => x"38", + 5478 => x"9c", + 5479 => x"80", + 5480 => x"38", + 5481 => x"95", + 5482 => x"2e", + 5483 => x"aa", + 5484 => x"ea", + 5485 => x"85", + 5486 => x"9e", + 5487 => x"05", + 5488 => x"54", + 5489 => x"38", + 5490 => x"70", + 5491 => x"54", + 5492 => x"8e", + 5493 => x"83", + 5494 => x"88", + 5495 => x"83", + 5496 => x"83", + 5497 => x"06", + 5498 => x"80", + 5499 => x"38", + 5500 => x"51", + 5501 => x"82", + 5502 => x"56", + 5503 => x"0a", + 5504 => x"05", + 5505 => x"3f", + 5506 => x"0b", + 5507 => x"80", + 5508 => x"7a", + 5509 => x"3f", + 5510 => x"9c", + 5511 => x"a3", + 5512 => x"81", + 5513 => x"34", + 5514 => x"80", + 5515 => x"b0", + 5516 => x"54", + 5517 => x"52", + 5518 => x"05", + 5519 => x"3f", + 5520 => x"08", + 5521 => x"ec", + 5522 => x"38", + 5523 => x"82", + 5524 => x"b2", + 5525 => x"84", + 5526 => x"06", + 5527 => x"73", + 5528 => x"38", + 5529 => x"af", + 5530 => x"2a", + 5531 => x"51", + 5532 => x"2e", + 5533 => x"81", + 5534 => x"80", + 5535 => x"87", + 5536 => x"39", + 5537 => x"51", + 5538 => x"82", + 5539 => x"7b", + 5540 => x"12", + 5541 => x"82", + 5542 => x"81", + 5543 => x"83", + 5544 => x"06", + 5545 => x"80", + 5546 => x"77", + 5547 => x"58", + 5548 => x"08", + 5549 => x"63", + 5550 => x"63", + 5551 => x"57", + 5552 => x"82", + 5553 => x"82", + 5554 => x"88", + 5555 => x"9c", + 5556 => x"d2", + 5557 => x"85", + 5558 => x"85", + 5559 => x"1b", + 5560 => x"0c", + 5561 => x"22", + 5562 => x"77", + 5563 => x"80", + 5564 => x"34", + 5565 => x"1a", + 5566 => x"94", + 5567 => x"85", + 5568 => x"06", + 5569 => x"80", + 5570 => x"38", + 5571 => x"08", + 5572 => x"86", + 5573 => x"ec", + 5574 => x"0c", + 5575 => x"70", + 5576 => x"52", + 5577 => x"39", + 5578 => x"51", + 5579 => x"82", + 5580 => x"57", + 5581 => x"08", + 5582 => x"38", + 5583 => x"85", + 5584 => x"2e", + 5585 => x"83", + 5586 => x"75", + 5587 => x"74", + 5588 => x"70", + 5589 => x"25", + 5590 => x"76", + 5591 => x"81", + 5592 => x"55", + 5593 => x"38", + 5594 => x"0c", + 5595 => x"75", + 5596 => x"54", + 5597 => x"a2", + 5598 => x"7a", + 5599 => x"3f", + 5600 => x"08", + 5601 => x"55", + 5602 => x"89", + 5603 => x"ec", + 5604 => x"1a", + 5605 => x"80", + 5606 => x"54", + 5607 => x"ec", + 5608 => x"0d", + 5609 => x"0d", + 5610 => x"64", + 5611 => x"59", + 5612 => x"90", + 5613 => x"52", + 5614 => x"cd", + 5615 => x"ec", + 5616 => x"85", + 5617 => x"38", + 5618 => x"55", + 5619 => x"86", + 5620 => x"82", + 5621 => x"19", + 5622 => x"55", + 5623 => x"80", + 5624 => x"38", + 5625 => x"0b", + 5626 => x"82", + 5627 => x"39", + 5628 => x"1a", + 5629 => x"82", + 5630 => x"19", + 5631 => x"08", + 5632 => x"7c", + 5633 => x"74", + 5634 => x"2e", + 5635 => x"94", + 5636 => x"83", + 5637 => x"56", + 5638 => x"38", + 5639 => x"22", + 5640 => x"89", + 5641 => x"55", + 5642 => x"75", + 5643 => x"19", + 5644 => x"39", + 5645 => x"52", + 5646 => x"ea", + 5647 => x"ec", + 5648 => x"75", + 5649 => x"38", + 5650 => x"ff", + 5651 => x"98", + 5652 => x"19", + 5653 => x"51", + 5654 => x"82", + 5655 => x"80", + 5656 => x"38", + 5657 => x"08", + 5658 => x"2a", + 5659 => x"80", + 5660 => x"38", + 5661 => x"8a", + 5662 => x"5c", + 5663 => x"27", + 5664 => x"7a", + 5665 => x"54", + 5666 => x"52", + 5667 => x"51", + 5668 => x"82", + 5669 => x"fe", + 5670 => x"83", + 5671 => x"56", + 5672 => x"9f", + 5673 => x"08", + 5674 => x"74", + 5675 => x"38", + 5676 => x"b4", + 5677 => x"16", + 5678 => x"89", + 5679 => x"51", + 5680 => x"77", + 5681 => x"b9", + 5682 => x"1a", + 5683 => x"08", + 5684 => x"84", + 5685 => x"57", + 5686 => x"27", + 5687 => x"56", + 5688 => x"52", + 5689 => x"97", + 5690 => x"ec", + 5691 => x"38", + 5692 => x"19", + 5693 => x"06", + 5694 => x"52", + 5695 => x"f2", + 5696 => x"31", + 5697 => x"7f", + 5698 => x"94", + 5699 => x"94", + 5700 => x"5c", + 5701 => x"80", + 5702 => x"85", + 5703 => x"3d", + 5704 => x"3d", + 5705 => x"65", + 5706 => x"5d", + 5707 => x"0c", + 5708 => x"05", + 5709 => x"f6", + 5710 => x"85", + 5711 => x"82", + 5712 => x"8a", + 5713 => x"33", + 5714 => x"2e", + 5715 => x"56", + 5716 => x"90", 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x"52", + 5776 => x"51", + 5777 => x"82", + 5778 => x"fe", + 5779 => x"b0", + 5780 => x"31", + 5781 => x"79", + 5782 => x"84", + 5783 => x"16", + 5784 => x"89", + 5785 => x"52", + 5786 => x"cc", + 5787 => x"55", + 5788 => x"16", + 5789 => x"2b", + 5790 => x"39", + 5791 => x"94", + 5792 => x"93", + 5793 => x"cd", + 5794 => x"85", + 5795 => x"e3", + 5796 => x"b0", + 5797 => x"76", + 5798 => x"94", + 5799 => x"ff", + 5800 => x"71", + 5801 => x"7b", + 5802 => x"38", + 5803 => x"18", + 5804 => x"51", + 5805 => x"82", + 5806 => x"fd", + 5807 => x"53", + 5808 => x"18", + 5809 => x"06", + 5810 => x"51", + 5811 => x"7e", + 5812 => x"83", + 5813 => x"76", + 5814 => x"17", + 5815 => x"1e", + 5816 => x"18", + 5817 => x"0c", + 5818 => x"58", + 5819 => x"74", + 5820 => x"38", + 5821 => x"8c", + 5822 => x"90", + 5823 => x"33", + 5824 => x"55", + 5825 => x"34", + 5826 => x"82", + 5827 => x"90", + 5828 => x"f8", + 5829 => x"8b", + 5830 => x"53", + 5831 => x"f2", + 5832 => x"85", + 5833 => x"82", + 5834 => x"80", + 5835 => x"16", + 5836 => x"2a", + 5837 => x"51", + 5838 => x"80", + 5839 => x"38", + 5840 => x"52", + 5841 => x"b7", + 5842 => x"ec", + 5843 => x"85", + 5844 => x"d4", + 5845 => x"08", + 5846 => x"a0", + 5847 => x"73", + 5848 => x"88", + 5849 => x"74", + 5850 => x"51", + 5851 => x"8c", + 5852 => x"9c", + 5853 => x"cb", + 5854 => x"b2", + 5855 => x"15", + 5856 => x"3f", + 5857 => x"15", + 5858 => x"3f", + 5859 => x"0b", + 5860 => x"78", + 5861 => x"3f", + 5862 => x"08", + 5863 => x"81", + 5864 => x"57", + 5865 => x"34", + 5866 => x"ec", + 5867 => x"0d", + 5868 => x"0d", + 5869 => x"54", + 5870 => x"82", + 5871 => x"53", + 5872 => x"08", + 5873 => x"3d", + 5874 => x"73", + 5875 => x"3f", + 5876 => x"08", + 5877 => x"ec", + 5878 => x"82", + 5879 => x"74", + 5880 => x"85", + 5881 => x"3d", + 5882 => x"3d", + 5883 => x"51", + 5884 => x"8b", + 5885 => x"82", + 5886 => x"24", + 5887 => x"85", + 5888 => x"9d", + 5889 => x"52", + 5890 => x"ec", + 5891 => x"0d", + 5892 => x"0d", + 5893 => x"3d", + 5894 => x"94", + 5895 => x"b8", + 5896 => x"ec", + 5897 => x"85", + 5898 => x"e0", + 5899 => x"63", + 5900 => x"d4", + 5901 => x"ec", + 5902 => x"ec", + 5903 => x"85", + 5904 => x"38", + 5905 => x"05", + 5906 => x"2b", + 5907 => x"80", + 5908 => x"76", + 5909 => x"0c", + 5910 => x"02", + 5911 => x"70", + 5912 => x"81", + 5913 => x"56", + 5914 => x"9e", + 5915 => x"53", + 5916 => x"db", + 5917 => x"85", + 5918 => x"15", + 5919 => x"82", + 5920 => x"84", + 5921 => x"06", + 5922 => x"55", + 5923 => x"ec", + 5924 => x"0d", + 5925 => x"0d", + 5926 => x"5b", + 5927 => x"80", + 5928 => x"ff", + 5929 => x"9f", + 5930 => x"ac", + 5931 => x"ec", + 5932 => x"85", + 5933 => x"fb", + 5934 => x"7a", + 5935 => x"08", + 5936 => x"64", + 5937 => x"2e", + 5938 => x"a0", + 5939 => x"70", + 5940 => x"c9", + 5941 => x"ec", + 5942 => x"85", + 5943 => x"d3", + 5944 => x"7b", + 5945 => x"3f", + 5946 => x"08", + 5947 => x"ec", + 5948 => x"38", + 5949 => x"51", + 5950 => x"82", + 5951 => x"45", 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x"73", + 6011 => x"16", + 6012 => x"26", + 6013 => x"55", + 6014 => x"91", + 6015 => x"54", + 6016 => x"70", + 6017 => x"34", + 6018 => x"ec", + 6019 => x"70", + 6020 => x"34", + 6021 => x"09", + 6022 => x"38", + 6023 => x"39", + 6024 => x"19", + 6025 => x"33", + 6026 => x"05", + 6027 => x"78", + 6028 => x"80", + 6029 => x"82", + 6030 => x"9e", + 6031 => x"f7", + 6032 => x"7d", + 6033 => x"05", + 6034 => x"57", + 6035 => x"3f", + 6036 => x"08", + 6037 => x"ec", + 6038 => x"38", + 6039 => x"53", + 6040 => x"38", + 6041 => x"54", + 6042 => x"92", + 6043 => x"33", + 6044 => x"70", + 6045 => x"54", + 6046 => x"38", + 6047 => x"15", + 6048 => x"70", + 6049 => x"58", + 6050 => x"82", + 6051 => x"8a", + 6052 => x"89", + 6053 => x"53", + 6054 => x"b9", + 6055 => x"ff", + 6056 => x"e0", + 6057 => x"85", + 6058 => x"15", + 6059 => x"53", + 6060 => x"e0", + 6061 => x"85", + 6062 => x"26", + 6063 => x"09", + 6064 => x"75", + 6065 => x"18", + 6066 => x"31", + 6067 => x"57", + 6068 => x"b1", + 6069 => x"08", + 6070 => x"38", + 6071 => x"51", + 6072 => x"82", + 6073 => x"54", + 6074 => x"08", + 6075 => x"9a", + 6076 => x"ec", + 6077 => x"81", + 6078 => x"85", + 6079 => x"16", + 6080 => x"16", + 6081 => x"2e", + 6082 => x"76", + 6083 => x"dc", + 6084 => x"31", + 6085 => x"18", + 6086 => x"90", + 6087 => x"81", + 6088 => x"06", + 6089 => x"56", + 6090 => x"9a", + 6091 => x"74", + 6092 => x"3f", + 6093 => x"08", + 6094 => x"ec", + 6095 => x"82", + 6096 => x"56", + 6097 => x"52", + 6098 => x"da", + 6099 => x"ec", + 6100 => x"ff", + 6101 => x"81", + 6102 => x"38", + 6103 => x"98", + 6104 => x"a6", + 6105 => x"16", + 6106 => x"39", + 6107 => x"16", + 6108 => x"75", + 6109 => x"53", + 6110 => x"aa", + 6111 => x"79", + 6112 => x"3f", + 6113 => x"08", + 6114 => x"0b", + 6115 => x"82", + 6116 => x"39", + 6117 => x"16", + 6118 => x"bb", + 6119 => x"2a", + 6120 => x"08", + 6121 => x"15", + 6122 => x"15", + 6123 => x"90", + 6124 => x"16", + 6125 => x"33", + 6126 => x"53", + 6127 => x"34", + 6128 => x"06", + 6129 => x"2e", + 6130 => x"9c", + 6131 => x"85", + 6132 => x"16", + 6133 => x"72", + 6134 => x"0c", + 6135 => x"04", + 6136 => x"79", + 6137 => x"75", + 6138 => x"8a", + 6139 => x"89", + 6140 => x"52", + 6141 => x"05", + 6142 => x"3f", + 6143 => x"08", + 6144 => x"ec", + 6145 => x"38", + 6146 => x"7a", + 6147 => x"d8", + 6148 => x"85", + 6149 => x"82", + 6150 => x"80", + 6151 => x"16", + 6152 => x"2b", + 6153 => x"74", + 6154 => x"86", + 6155 => x"84", + 6156 => x"06", + 6157 => x"73", + 6158 => x"38", + 6159 => x"52", + 6160 => x"b8", + 6161 => x"ec", + 6162 => x"0c", + 6163 => x"14", + 6164 => x"23", + 6165 => x"51", + 6166 => x"82", + 6167 => x"55", + 6168 => x"09", + 6169 => x"38", + 6170 => x"39", + 6171 => x"84", + 6172 => x"0c", + 6173 => x"82", + 6174 => x"89", + 6175 => x"fc", + 6176 => x"87", + 6177 => x"53", + 6178 => x"e7", + 6179 => x"85", + 6180 => x"38", + 6181 => x"08", + 6182 => x"3d", + 6183 => x"3d", + 6184 => x"89", + 6185 => x"54", + 6186 => x"54", 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x"08", + 6246 => x"7c", + 6247 => x"08", + 6248 => x"fe", + 6249 => x"08", + 6250 => x"55", + 6251 => x"91", + 6252 => x"0c", + 6253 => x"81", + 6254 => x"39", + 6255 => x"ce", + 6256 => x"ec", + 6257 => x"55", + 6258 => x"2e", + 6259 => x"80", + 6260 => x"75", + 6261 => x"52", + 6262 => x"05", + 6263 => x"3f", + 6264 => x"08", + 6265 => x"38", + 6266 => x"08", + 6267 => x"38", + 6268 => x"08", + 6269 => x"70", + 6270 => x"08", + 6271 => x"7a", + 6272 => x"7f", + 6273 => x"54", + 6274 => x"77", + 6275 => x"80", + 6276 => x"15", + 6277 => x"ec", + 6278 => x"75", + 6279 => x"52", + 6280 => x"52", + 6281 => x"d7", + 6282 => x"ec", + 6283 => x"85", + 6284 => x"da", + 6285 => x"33", + 6286 => x"1a", + 6287 => x"54", + 6288 => x"09", + 6289 => x"38", + 6290 => x"ff", + 6291 => x"82", + 6292 => x"83", + 6293 => x"70", + 6294 => x"70", + 6295 => x"82", + 6296 => x"51", + 6297 => x"b4", + 6298 => x"bb", + 6299 => x"85", + 6300 => x"0a", + 6301 => x"81", + 6302 => x"25", + 6303 => x"59", + 6304 => x"75", + 6305 => x"7a", + 6306 => x"ff", + 6307 => x"7c", + 6308 => x"90", + 6309 => x"11", + 6310 => x"56", + 6311 => x"15", + 6312 => x"85", + 6313 => x"3d", + 6314 => x"3d", + 6315 => x"3d", + 6316 => x"70", + 6317 => x"d1", + 6318 => x"ec", + 6319 => x"85", + 6320 => x"a8", + 6321 => x"33", + 6322 => x"a0", + 6323 => x"33", + 6324 => x"70", + 6325 => x"55", + 6326 => x"73", + 6327 => x"8e", + 6328 => x"08", + 6329 => x"18", + 6330 => x"80", + 6331 => x"38", + 6332 => x"08", + 6333 => x"08", + 6334 => x"c3", + 6335 => x"85", + 6336 => x"88", + 6337 => x"80", + 6338 => x"17", + 6339 => x"51", + 6340 => x"3f", + 6341 => x"08", + 6342 => x"81", + 6343 => x"81", + 6344 => x"ec", + 6345 => x"09", + 6346 => x"38", + 6347 => x"39", + 6348 => x"77", + 6349 => x"ec", + 6350 => x"08", + 6351 => x"98", + 6352 => x"82", + 6353 => x"52", + 6354 => x"8a", + 6355 => x"ec", + 6356 => x"17", + 6357 => x"0c", + 6358 => x"80", + 6359 => x"73", + 6360 => x"75", + 6361 => x"38", + 6362 => x"34", + 6363 => x"82", + 6364 => x"89", + 6365 => x"e2", + 6366 => x"53", + 6367 => x"a4", + 6368 => x"3d", + 6369 => x"3f", + 6370 => x"08", + 6371 => x"ec", + 6372 => x"38", + 6373 => x"3d", + 6374 => x"3d", + 6375 => x"d1", + 6376 => x"85", + 6377 => x"82", + 6378 => x"81", + 6379 => x"80", + 6380 => x"70", + 6381 => x"81", + 6382 => x"56", + 6383 => x"81", + 6384 => x"98", + 6385 => x"74", + 6386 => x"38", + 6387 => x"05", + 6388 => x"06", + 6389 => x"55", + 6390 => x"38", + 6391 => x"51", + 6392 => x"82", + 6393 => x"74", + 6394 => x"81", + 6395 => x"56", + 6396 => x"80", + 6397 => x"54", + 6398 => x"08", + 6399 => x"2e", + 6400 => x"73", + 6401 => x"ec", + 6402 => x"52", + 6403 => x"52", + 6404 => x"3f", + 6405 => x"08", + 6406 => x"ec", + 6407 => x"38", + 6408 => x"08", + 6409 => x"cc", + 6410 => x"85", + 6411 => x"82", + 6412 => x"86", + 6413 => x"80", + 6414 => x"85", + 6415 => x"2e", + 6416 => x"85", + 6417 => x"c2", + 6418 => x"ce", + 6419 => x"85", + 6420 => x"85", + 6421 => x"81", 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x"b6", + 6481 => x"54", + 6482 => x"15", + 6483 => x"90", + 6484 => x"34", + 6485 => x"0a", + 6486 => x"19", + 6487 => x"e3", + 6488 => x"78", + 6489 => x"51", + 6490 => x"a0", + 6491 => x"11", + 6492 => x"05", + 6493 => x"fa", + 6494 => x"ae", + 6495 => x"15", + 6496 => x"78", + 6497 => x"53", + 6498 => x"3f", + 6499 => x"0b", + 6500 => x"77", + 6501 => x"3f", + 6502 => x"08", + 6503 => x"ec", + 6504 => x"82", + 6505 => x"52", + 6506 => x"51", + 6507 => x"3f", + 6508 => x"52", + 6509 => x"fd", + 6510 => x"90", + 6511 => x"34", + 6512 => x"0b", + 6513 => x"78", + 6514 => x"fa", + 6515 => x"ec", + 6516 => x"39", + 6517 => x"52", + 6518 => x"bd", + 6519 => x"82", + 6520 => x"99", + 6521 => x"da", + 6522 => x"3d", + 6523 => x"d2", + 6524 => x"53", + 6525 => x"84", + 6526 => x"3d", + 6527 => x"3f", + 6528 => x"08", + 6529 => x"ec", + 6530 => x"38", + 6531 => x"3d", + 6532 => x"3d", + 6533 => x"cc", + 6534 => x"85", + 6535 => x"82", + 6536 => x"82", + 6537 => x"81", + 6538 => x"81", + 6539 => x"86", + 6540 => x"aa", + 6541 => x"a4", + 6542 => x"a8", + 6543 => x"05", + 6544 => x"ae", + 6545 => x"77", + 6546 => x"70", + 6547 => x"b4", + 6548 => x"3d", + 6549 => x"51", + 6550 => x"82", + 6551 => x"55", + 6552 => x"08", + 6553 => x"6f", + 6554 => x"06", + 6555 => x"a2", + 6556 => x"92", + 6557 => x"81", + 6558 => x"85", + 6559 => x"2e", + 6560 => x"81", + 6561 => x"51", + 6562 => x"82", + 6563 => x"55", + 6564 => x"08", + 6565 => x"68", + 6566 => x"a8", + 6567 => x"05", + 6568 => x"51", + 6569 => x"3f", + 6570 => x"33", + 6571 => x"8b", + 6572 => x"84", + 6573 => x"06", + 6574 => x"73", + 6575 => x"a0", + 6576 => x"8b", + 6577 => x"54", + 6578 => x"15", + 6579 => x"33", + 6580 => x"70", + 6581 => x"55", + 6582 => x"2e", + 6583 => x"6e", + 6584 => x"df", + 6585 => x"78", + 6586 => x"3f", + 6587 => x"08", + 6588 => x"ff", + 6589 => x"82", + 6590 => x"ec", + 6591 => x"80", + 6592 => x"85", + 6593 => x"78", + 6594 => x"f3", + 6595 => x"ec", + 6596 => x"d4", + 6597 => x"55", + 6598 => x"08", + 6599 => x"81", + 6600 => x"73", + 6601 => x"81", + 6602 => x"63", + 6603 => x"76", + 6604 => x"3f", + 6605 => x"0b", + 6606 => x"87", + 6607 => x"ec", + 6608 => x"77", + 6609 => x"3f", + 6610 => x"08", + 6611 => x"ec", + 6612 => x"78", + 6613 => x"ee", + 6614 => x"ec", + 6615 => x"82", + 6616 => x"a8", + 6617 => x"ed", + 6618 => x"80", + 6619 => x"02", + 6620 => x"df", + 6621 => x"57", + 6622 => x"3d", + 6623 => x"96", + 6624 => x"d4", + 6625 => x"ec", + 6626 => x"85", + 6627 => x"cf", + 6628 => x"65", + 6629 => x"d4", + 6630 => x"88", + 6631 => x"ec", + 6632 => x"85", + 6633 => x"38", + 6634 => x"05", + 6635 => x"06", + 6636 => x"73", + 6637 => x"a7", + 6638 => x"09", + 6639 => x"71", + 6640 => x"06", + 6641 => x"55", + 6642 => x"15", + 6643 => x"81", + 6644 => x"34", + 6645 => x"b3", + 6646 => x"85", + 6647 => x"74", + 6648 => x"0c", + 6649 => x"04", + 6650 => x"64", + 6651 => x"93", + 6652 => x"52", + 6653 => x"d1", + 6654 => x"85", + 6655 => x"82", + 6656 => x"80", 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x"38", + 6716 => x"1b", + 6717 => x"55", + 6718 => x"2e", + 6719 => x"39", + 6720 => x"09", + 6721 => x"38", + 6722 => x"80", + 6723 => x"81", + 6724 => x"07", + 6725 => x"54", + 6726 => x"80", + 6727 => x"80", + 6728 => x"7b", + 6729 => x"53", + 6730 => x"d3", + 6731 => x"ec", + 6732 => x"85", + 6733 => x"38", + 6734 => x"55", + 6735 => x"56", + 6736 => x"8b", + 6737 => x"56", + 6738 => x"83", + 6739 => x"75", + 6740 => x"51", + 6741 => x"3f", + 6742 => x"08", + 6743 => x"82", + 6744 => x"98", + 6745 => x"e6", + 6746 => x"53", + 6747 => x"b8", + 6748 => x"3d", + 6749 => x"3f", + 6750 => x"08", + 6751 => x"08", + 6752 => x"85", + 6753 => x"98", + 6754 => x"a0", + 6755 => x"70", + 6756 => x"ae", + 6757 => x"6d", + 6758 => x"81", + 6759 => x"57", + 6760 => x"74", + 6761 => x"38", + 6762 => x"81", + 6763 => x"81", + 6764 => x"52", + 6765 => x"c9", + 6766 => x"ec", + 6767 => x"a5", + 6768 => x"33", + 6769 => x"54", + 6770 => x"3f", + 6771 => x"08", + 6772 => x"38", + 6773 => x"76", + 6774 => x"05", + 6775 => x"39", + 6776 => x"08", + 6777 => x"15", + 6778 => x"ff", + 6779 => x"73", + 6780 => x"38", + 6781 => x"83", + 6782 => x"56", + 6783 => x"75", + 6784 => x"81", + 6785 => x"33", + 6786 => x"2e", + 6787 => x"52", + 6788 => x"51", + 6789 => x"3f", + 6790 => x"08", + 6791 => x"ff", + 6792 => x"38", + 6793 => x"88", + 6794 => x"8a", + 6795 => x"38", + 6796 => x"ec", + 6797 => x"75", + 6798 => x"74", + 6799 => x"73", + 6800 => x"05", + 6801 => x"17", + 6802 => x"70", + 6803 => x"34", + 6804 => x"70", + 6805 => x"ff", + 6806 => x"55", + 6807 => x"26", + 6808 => x"8b", + 6809 => x"86", + 6810 => x"e5", + 6811 => x"38", + 6812 => x"99", + 6813 => x"05", + 6814 => x"70", + 6815 => x"73", + 6816 => x"81", + 6817 => x"ff", + 6818 => x"ed", + 6819 => x"80", + 6820 => x"91", + 6821 => x"55", + 6822 => x"3f", + 6823 => x"08", + 6824 => x"ec", + 6825 => x"38", + 6826 => x"51", + 6827 => x"3f", + 6828 => x"08", + 6829 => x"ec", + 6830 => x"76", + 6831 => x"67", + 6832 => x"34", + 6833 => x"82", + 6834 => x"84", + 6835 => x"06", + 6836 => x"80", + 6837 => x"2e", + 6838 => x"81", + 6839 => x"ff", + 6840 => x"82", + 6841 => x"54", + 6842 => x"08", + 6843 => x"53", + 6844 => x"08", + 6845 => x"ff", + 6846 => x"67", + 6847 => x"8b", + 6848 => x"53", + 6849 => x"51", + 6850 => x"3f", + 6851 => x"0b", + 6852 => x"79", + 6853 => x"ae", + 6854 => x"ec", + 6855 => x"55", + 6856 => x"ec", + 6857 => x"0d", + 6858 => x"0d", + 6859 => x"88", + 6860 => x"05", + 6861 => x"fc", + 6862 => x"54", + 6863 => x"d2", + 6864 => x"85", + 6865 => x"82", + 6866 => x"82", + 6867 => x"1a", + 6868 => x"82", + 6869 => x"80", + 6870 => x"8c", + 6871 => x"78", + 6872 => x"1a", + 6873 => x"2a", + 6874 => x"51", + 6875 => x"90", + 6876 => x"82", + 6877 => x"58", + 6878 => x"81", + 6879 => x"39", + 6880 => x"22", + 6881 => x"70", + 6882 => x"56", + 6883 => x"c6", + 6884 => x"14", + 6885 => x"09", + 6886 => x"72", + 6887 => x"82", + 6888 => x"05", + 6889 => x"7c", + 6890 => x"55", + 6891 => x"27", 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x"30", + 7891 => x"2e", + 7892 => x"20", + 7893 => x"41", + 7894 => x"20", + 7895 => x"20", + 7896 => x"38", + 7897 => x"30", + 7898 => x"2e", + 7899 => x"20", + 7900 => x"44", + 7901 => x"52", + 7902 => x"20", + 7903 => x"76", + 7904 => x"73", + 7905 => x"30", + 7906 => x"2e", + 7907 => x"20", + 7908 => x"49", + 7909 => x"31", + 7910 => x"20", + 7911 => x"6d", + 7912 => x"20", + 7913 => x"30", + 7914 => x"2e", + 7915 => x"20", + 7916 => x"4e", + 7917 => x"43", + 7918 => x"20", + 7919 => x"61", + 7920 => x"6c", + 7921 => x"30", + 7922 => x"2e", + 7923 => x"20", + 7924 => x"49", + 7925 => x"4f", + 7926 => x"42", + 7927 => x"00", + 7928 => x"20", + 7929 => x"42", + 7930 => x"43", + 7931 => x"20", + 7932 => x"4f", + 7933 => x"0a", + 7934 => x"20", + 7935 => x"53", + 7936 => x"00", + 7937 => x"20", + 7938 => x"50", + 7939 => x"00", + 7940 => x"64", + 7941 => x"73", + 7942 => x"3a", + 7943 => x"20", + 7944 => x"50", + 7945 => x"65", + 7946 => x"20", + 7947 => x"74", + 7948 => x"41", + 7949 => x"65", + 7950 => x"3d", + 7951 => x"38", + 7952 => x"00", + 7953 => x"20", + 7954 => x"50", + 7955 => x"65", + 7956 => x"79", + 7957 => x"61", + 7958 => x"41", + 7959 => x"65", + 7960 => x"3d", + 7961 => x"38", + 7962 => x"00", + 7963 => x"20", + 7964 => x"74", + 7965 => x"20", + 7966 => x"72", + 7967 => x"64", + 7968 => x"73", + 7969 => x"20", + 7970 => x"3d", + 7971 => x"38", + 7972 => x"00", + 7973 => x"69", + 7974 => x"0a", + 7975 => x"20", + 7976 => x"50", + 7977 => x"64", + 7978 => x"20", + 7979 => x"20", + 7980 => x"20", + 7981 => x"20", + 7982 => x"3d", + 7983 => x"34", + 7984 => x"00", + 7985 => x"20", + 7986 => x"79", + 7987 => x"6d", + 7988 => x"6f", + 7989 => x"46", + 7990 => x"20", + 7991 => x"20", + 7992 => x"3d", + 7993 => x"2e", + 7994 => x"64", + 7995 => x"0a", + 7996 => x"20", + 7997 => x"44", + 7998 => x"20", + 7999 => x"63", + 8000 => x"72", + 8001 => x"20", + 8002 => x"20", + 8003 => x"3d", + 8004 => x"2e", + 8005 => x"64", + 8006 => x"0a", + 8007 => x"20", + 8008 => x"69", + 8009 => x"6f", + 8010 => x"53", + 8011 => x"4d", + 8012 => x"6f", + 8013 => x"46", + 8014 => x"3d", + 8015 => x"2e", + 8016 => x"64", + 8017 => x"0a", + 8018 => x"6d", + 8019 => x"00", + 8020 => x"65", + 8021 => x"6d", + 8022 => x"6c", + 8023 => x"00", + 8024 => x"56", + 8025 => x"56", + 8026 => x"6e", + 8027 => x"6e", + 8028 => x"77", + 8029 => x"00", + 8030 => x"00", + 8031 => x"00", + 8032 => x"00", + 8033 => x"00", + 8034 => x"00", + 8035 => x"00", + 8036 => x"00", + 8037 => x"00", + 8038 => x"00", + 8039 => x"00", + 8040 => x"00", + 8041 => x"00", + 8042 => x"00", + 8043 => x"00", + 8044 => x"00", + 8045 => x"00", + 8046 => x"00", + 8047 => x"00", + 8048 => x"00", + 8049 => x"00", + 8050 => x"00", + 8051 => x"00", + 8052 => x"00", + 8053 => x"00", + 8054 => x"00", + 8055 => x"00", + 8056 => x"00", + 8057 => x"00", + 8058 => x"00", + 8059 => x"00", + 8060 => x"00", + 8061 => x"00", + 8062 => x"00", + 8063 => x"00", + 8064 => x"00", + 8065 => x"00", + 8066 => x"00", + 8067 => x"00", + 8068 => x"00", + 8069 => x"00", + 8070 => x"00", + 8071 => x"00", + 8072 => x"00", + 8073 => x"00", + 8074 => x"00", + 8075 => x"00", + 8076 => x"00", + 8077 => x"00", + 8078 => x"00", + 8079 => x"00", + 8080 => x"00", + 8081 => x"00", + 8082 => x"00", + 8083 => x"00", + 8084 => x"00", + 8085 => x"00", + 8086 => x"00", + 8087 => x"00", + 8088 => x"00", + 8089 => x"00", + 8090 => x"00", + 8091 => x"00", + 8092 => x"00", + 8093 => x"00", + 8094 => x"00", + 8095 => x"5b", + 8096 => x"5b", + 8097 => x"5b", + 8098 => x"5b", + 8099 => x"5b", + 8100 => x"5b", + 8101 => x"5b", + 8102 => x"30", + 8103 => x"5b", + 8104 => x"5b", + 8105 => x"5b", + 8106 => x"00", + 8107 => x"00", + 8108 => x"00", + 8109 => x"00", + 8110 => x"00", + 8111 => x"00", + 8112 => x"00", + 8113 => x"00", + 8114 => x"00", + 8115 => x"00", + 8116 => x"00", + 8117 => x"69", + 8118 => x"72", + 8119 => x"69", + 8120 => x"00", + 8121 => x"00", + 8122 => x"30", + 8123 => x"20", + 8124 => x"00", + 8125 => x"61", + 8126 => x"64", + 8127 => x"20", + 8128 => x"65", + 8129 => x"68", + 8130 => x"69", + 8131 => x"72", + 8132 => x"69", + 8133 => x"74", + 8134 => x"4f", + 8135 => x"00", + 8136 => x"61", + 8137 => x"74", + 8138 => x"65", + 8139 => x"72", + 8140 => x"65", + 8141 => x"73", + 8142 => x"79", + 8143 => x"6c", + 8144 => x"64", + 8145 => x"62", + 8146 => x"67", + 8147 => x"00", + 8148 => x"44", + 8149 => x"2a", + 8150 => x"3b", + 8151 => x"3f", + 8152 => x"7f", + 8153 => x"41", + 8154 => x"41", + 8155 => x"00", + 8156 => x"fe", + 8157 => x"44", + 8158 => x"2e", + 8159 => x"4f", + 8160 => x"4d", + 8161 => x"20", + 8162 => x"54", + 8163 => x"20", + 8164 => x"4f", + 8165 => x"4d", + 8166 => x"20", + 8167 => x"54", + 8168 => x"20", + 8169 => x"00", + 8170 => x"00", + 8171 => x"00", + 8172 => x"00", + 8173 => x"9a", + 8174 => x"41", + 8175 => x"45", + 8176 => x"49", + 8177 => x"92", + 8178 => x"4f", + 8179 => x"99", + 8180 => x"9d", + 8181 => x"49", + 8182 => x"a5", + 8183 => x"a9", + 8184 => x"ad", + 8185 => x"b1", + 8186 => x"b5", + 8187 => x"b9", + 8188 => x"bd", + 8189 => x"c1", + 8190 => x"c5", + 8191 => x"c9", + 8192 => x"cd", + 8193 => x"d1", + 8194 => x"d5", + 8195 => x"d9", + 8196 => x"dd", + 8197 => x"e1", + 8198 => x"e5", + 8199 => x"e9", + 8200 => x"ed", + 8201 => x"f1", + 8202 => x"f5", + 8203 => x"f9", + 8204 => x"fd", + 8205 => x"2e", + 8206 => x"5b", + 8207 => x"22", + 8208 => x"3e", + 8209 => x"00", + 8210 => x"01", + 8211 => x"10", + 8212 => x"00", + 8213 => x"00", + 8214 => x"01", + 8215 => x"04", + 8216 => x"10", + 8217 => x"00", + 8218 => x"00", + 8219 => x"00", + 8220 => x"02", + 8221 => x"00", + 8222 => x"00", + 8223 => x"00", + 8224 => x"04", + 8225 => x"00", + 8226 => x"00", + 8227 => x"00", + 8228 => x"14", + 8229 => x"00", + 8230 => x"00", + 8231 => x"00", + 8232 => x"2b", + 8233 => x"00", + 8234 => x"00", + 8235 => x"00", + 8236 => x"30", + 8237 => x"00", + 8238 => x"00", + 8239 => x"00", + 8240 => x"3c", + 8241 => x"00", + 8242 => x"00", + 8243 => x"00", + 8244 => x"3d", + 8245 => x"00", + 8246 => x"00", + 8247 => x"00", + 8248 => x"3f", + 8249 => x"00", + 8250 => x"00", + 8251 => x"00", + 8252 => x"40", + 8253 => x"00", + 8254 => x"00", + 8255 => x"00", + 8256 => x"41", + 8257 => x"00", + 8258 => x"00", + 8259 => x"00", + 8260 => x"42", + 8261 => x"00", + 8262 => x"00", + 8263 => x"00", + 8264 => x"43", + 8265 => x"00", + 8266 => x"00", + 8267 => x"00", + 8268 => x"50", + 8269 => x"00", + 8270 => x"00", + 8271 => x"00", + 8272 => x"51", + 8273 => x"00", + 8274 => x"00", + 8275 => x"00", + 8276 => x"54", + 8277 => x"00", + 8278 => x"00", + 8279 => x"00", + 8280 => x"55", + 8281 => x"00", + 8282 => x"00", + 8283 => x"00", + 8284 => x"79", + 8285 => x"00", + 8286 => x"00", + 8287 => x"00", + 8288 => x"78", + 8289 => x"00", + 8290 => x"00", + 8291 => x"00", + 8292 => x"82", + 8293 => x"00", + 8294 => x"00", + 8295 => x"00", + 8296 => x"83", + 8297 => x"00", + 8298 => x"00", + 8299 => x"00", + 8300 => x"85", + 8301 => x"00", + 8302 => x"00", + 8303 => x"00", + 8304 => x"87", + 8305 => x"00", + 8306 => x"00", + 8307 => x"00", + 8308 => x"8c", + 8309 => x"00", + 8310 => x"00", + 8311 => x"00", + 8312 => x"8d", + 8313 => x"00", + 8314 => x"00", + 8315 => x"00", + 8316 => x"8e", + 8317 => x"00", + 8318 => x"00", + 8319 => x"00", + 8320 => x"8f", + 8321 => x"00", + 8322 => x"00", + 8323 => x"00", + 8324 => x"00", + 8325 => x"00", + 8326 => x"00", + 8327 => x"00", + 8328 => x"01", + 8329 => x"00", + 8330 => x"01", + 8331 => x"81", + 8332 => x"00", + 8333 => x"7f", + 8334 => x"00", + 8335 => x"00", + 8336 => x"00", + 8337 => x"00", + 8338 => x"f5", + 8339 => x"f5", + 8340 => x"f5", + 8341 => x"00", + 8342 => x"01", + 8343 => x"01", + 8344 => x"01", + 8345 => x"00", + 8346 => x"00", + 8347 => x"00", + 8348 => x"00", + 8349 => x"00", + 8350 => x"00", + 8351 => x"00", + 8352 => x"00", + 8353 => x"00", + 8354 => x"00", + 8355 => x"00", + 8356 => x"00", + 8357 => x"00", + 8358 => x"00", + 8359 => x"00", + 8360 => x"00", + 8361 => x"00", + 8362 => x"00", + 8363 => x"00", + 8364 => x"00", + 8365 => x"00", + 8366 => x"00", + 8367 => x"00", + 8368 => x"00", + 8369 => x"00", + 8370 => x"00", + 8371 => x"00", + 8372 => x"00", + 8373 => x"00", + 8374 => x"00", + 8375 => x"00", + 8376 => x"00", + 8377 => x"00", + 8378 => x"00", + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + 0 => x"0b", + 1 => x"f8", + 2 => x"0b", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"88", + 9 => x"90", + 10 => x"08", + 11 => x"8c", + 12 => x"04", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"71", + 17 => x"72", + 18 => x"81", + 19 => x"83", + 20 => x"ff", + 21 => x"04", + 22 => x"00", + 23 => x"00", + 24 => x"71", + 25 => x"83", + 26 => x"83", + 27 => x"05", + 28 => x"2b", + 29 => x"73", + 30 => x"0b", + 31 => x"83", + 32 => x"72", + 33 => x"72", + 34 => x"09", + 35 => x"73", + 36 => x"07", + 37 => x"53", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"73", + 42 => x"51", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"71", + 50 => x"09", + 51 => x"0a", + 52 => x"0a", + 53 => x"05", + 54 => x"51", + 55 => x"04", + 56 => x"72", + 57 => x"73", + 58 => x"51", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"ff", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"0a", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"09", + 90 => x"0b", + 91 => x"05", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"73", + 98 => x"09", + 99 => x"81", + 100 => x"06", + 101 => x"04", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"04", + 106 => x"06", + 107 => x"82", + 108 => x"0b", + 109 => x"fc", + 110 => x"51", + 111 => x"00", + 112 => x"72", + 113 => x"72", + 114 => x"81", + 115 => x"0a", + 116 => x"51", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"72", + 121 => x"72", + 122 => x"81", + 123 => x"0a", + 124 => x"53", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"71", + 129 => x"52", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"04", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"73", + 146 => x"07", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"71", + 153 => x"72", + 154 => x"81", + 155 => x"10", + 156 => x"81", + 157 => x"04", + 158 => x"00", + 159 => x"00", + 160 => x"71", + 161 => x"0b", + 162 => x"fc", + 163 => x"10", + 164 => x"06", + 165 => x"92", + 166 => x"00", + 167 => x"00", + 168 => x"88", + 169 => x"90", + 170 => x"0b", + 171 => x"fb", + 172 => x"88", + 173 => x"0c", + 174 => x"0c", + 175 => x"00", + 176 => x"88", + 177 => x"90", + 178 => x"0b", + 179 => x"e7", + 180 => x"88", + 181 => x"0c", + 182 => x"0c", + 183 => x"00", + 184 => x"72", + 185 => x"05", + 186 => x"81", + 187 => x"70", + 188 => x"73", + 189 => x"05", + 190 => x"07", + 191 => x"04", + 192 => x"72", + 193 => x"05", + 194 => x"09", + 195 => x"05", + 196 => x"06", + 197 => x"74", + 198 => x"06", + 199 => x"51", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"04", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"71", + 217 => x"04", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"04", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"02", + 233 => x"10", + 234 => x"04", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"05", + 250 => x"02", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"00", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"0b", + 265 => x"81", + 266 => x"0b", + 267 => x"0b", + 268 => x"95", + 269 => x"0b", + 270 => x"0b", + 271 => x"b5", + 272 => x"0b", + 273 => x"0b", + 274 => x"d5", + 275 => x"0b", + 276 => x"0b", + 277 => x"f5", + 278 => x"0b", + 279 => x"0b", + 280 => x"95", + 281 => x"0b", + 282 => x"0b", + 283 => x"b5", + 284 => x"0b", + 285 => x"0b", + 286 => x"d5", + 287 => x"0b", + 288 => x"0b", + 289 => x"f5", + 290 => x"0b", + 291 => x"0b", + 292 => x"93", + 293 => x"0b", + 294 => x"0b", + 295 => x"b2", + 296 => x"0b", + 297 => x"0b", + 298 => x"d2", + 299 => x"0b", + 300 => x"0b", + 301 => x"f2", + 302 => x"0b", + 303 => x"0b", + 304 => x"92", + 305 => x"0b", + 306 => x"0b", + 307 => x"b2", + 308 => x"0b", + 309 => x"0b", + 310 => x"d2", + 311 => x"0b", + 312 => x"0b", + 313 => x"f2", + 314 => x"0b", + 315 => x"0b", + 316 => x"92", + 317 => x"0b", + 318 => x"0b", + 319 => x"b2", + 320 => x"0b", + 321 => x"0b", + 322 => x"d2", + 323 => x"0b", + 324 => x"0b", + 325 => x"f2", + 326 => x"0b", + 327 => x"0b", + 328 => x"92", + 329 => x"0b", + 330 => x"0b", + 331 => x"b2", + 332 => x"0b", + 333 => x"0b", + 334 => x"d2", + 335 => x"0b", + 336 => x"0b", + 337 => x"f2", + 338 => x"0b", + 339 => x"0b", + 340 => x"91", + 341 => x"0b", + 342 => x"0b", + 343 => x"b0", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"04", + 385 => x"04", + 386 => x"0c", + 387 => x"2d", + 388 => x"08", + 389 => x"04", + 390 => x"0c", + 391 => x"2d", + 392 => x"08", + 393 => x"04", + 394 => x"0c", + 395 => x"2d", + 396 => x"08", + 397 => x"04", + 398 => x"0c", + 399 => x"2d", + 400 => x"08", + 401 => x"04", + 402 => x"0c", + 403 => x"2d", + 404 => x"08", + 405 => x"04", + 406 => x"0c", + 407 => x"2d", + 408 => x"08", + 409 => x"04", + 410 => x"0c", + 411 => x"2d", + 412 => x"08", + 413 => x"04", + 414 => x"0c", + 415 => x"2d", + 416 => x"08", + 417 => x"04", + 418 => x"0c", + 419 => x"2d", + 420 => x"08", + 421 => x"04", + 422 => x"0c", + 423 => x"2d", + 424 => x"08", + 425 => x"04", + 426 => x"0c", + 427 => x"2d", + 428 => x"08", + 429 => x"04", + 430 => x"0c", + 431 => x"2d", + 432 => x"08", + 433 => x"04", + 434 => x"0c", + 435 => x"2d", + 436 => x"08", + 437 => x"04", + 438 => x"0c", + 439 => x"2d", + 440 => x"08", + 441 => x"04", + 442 => x"0c", + 443 => x"2d", + 444 => x"08", + 445 => x"04", + 446 => x"0c", + 447 => x"82", + 448 => x"82", + 449 => x"82", + 450 => x"bd", + 451 => x"85", + 452 => x"a0", + 453 => x"85", + 454 => x"f0", + 455 => x"f8", + 456 => x"90", + 457 => x"f8", + 458 => x"bc", + 459 => x"f8", + 460 => x"90", + 461 => x"f8", + 462 => x"af", + 463 => x"f8", + 464 => x"90", + 465 => x"f8", + 466 => x"a3", + 467 => x"f8", + 468 => x"90", + 469 => x"f8", + 470 => x"a0", + 471 => x"f8", + 472 => x"90", + 473 => x"f8", + 474 => x"bd", + 475 => x"f8", + 476 => x"90", + 477 => x"f8", + 478 => x"a8", + 479 => x"f8", + 480 => x"90", + 481 => x"f8", + 482 => x"91", + 483 => x"f8", + 484 => x"90", + 485 => x"f8", + 486 => x"de", + 487 => x"f8", + 488 => x"90", + 489 => x"f8", + 490 => x"fd", + 491 => x"f8", + 492 => x"90", + 493 => x"f8", + 494 => x"9c", + 495 => x"f8", + 496 => x"90", + 497 => x"f8", + 498 => x"91", + 499 => x"f8", + 500 => x"90", + 501 => x"f8", + 502 => x"f5", + 503 => x"f8", + 504 => x"90", + 505 => x"f8", + 506 => x"e5", + 507 => x"f8", + 508 => x"90", + 509 => x"f8", + 510 => x"a2", + 511 => x"f8", + 512 => x"90", + 513 => x"f8", + 514 => x"e5", + 515 => x"f8", + 516 => x"90", + 517 => x"f8", + 518 => x"e6", + 519 => x"f8", + 520 => x"90", + 521 => x"f8", + 522 => x"8f", + 523 => x"f8", + 524 => x"90", + 525 => x"f8", + 526 => x"e8", + 527 => x"f8", + 528 => x"90", + 529 => x"f8", + 530 => x"93", + 531 => x"f8", + 532 => x"90", + 533 => x"f8", + 534 => x"f9", + 535 => x"f8", + 536 => x"90", + 537 => x"f8", + 538 => x"d7", + 539 => x"f8", + 540 => x"90", + 541 => x"f8", + 542 => x"e5", + 543 => x"f8", + 544 => x"90", + 545 => x"f8", + 546 => x"a7", + 547 => x"f8", + 548 => x"90", + 549 => x"f8", + 550 => x"db", + 551 => x"f8", + 552 => x"90", + 553 => x"f8", + 554 => x"95", + 555 => x"f8", + 556 => x"90", + 557 => x"f8", + 558 => x"d9", + 559 => x"f8", + 560 => x"90", + 561 => x"f8", + 562 => x"c0", + 563 => x"f8", + 564 => x"90", + 565 => x"f8", + 566 => x"e8", + 567 => x"f8", + 568 => x"90", + 569 => x"f8", + 570 => x"d2", + 571 => x"f8", + 572 => x"90", + 573 => x"f8", + 574 => x"b6", + 575 => x"f8", + 576 => x"90", + 577 => x"f8", + 578 => x"2d", + 579 => x"08", + 580 => x"04", + 581 => x"0c", + 582 => x"82", + 583 => x"82", + 584 => x"82", + 585 => x"80", + 586 => x"82", + 587 => x"82", + 588 => x"82", + 589 => x"a1", + 590 => x"85", + 591 => x"a0", + 592 => x"04", + 593 => x"10", + 594 => x"10", + 595 => x"10", + 596 => x"10", + 597 => x"10", + 598 => x"10", + 599 => x"10", + 600 => x"10", + 601 => x"04", + 602 => x"81", + 603 => x"83", + 604 => x"05", + 605 => x"10", + 606 => x"72", + 607 => x"51", + 608 => x"72", + 609 => x"06", + 610 => x"72", + 611 => x"10", + 612 => x"10", + 613 => x"ed", + 614 => x"53", + 615 => x"85", + 616 => x"9d", + 617 => x"38", + 618 => x"84", + 619 => x"0b", + 620 => x"9e", + 621 => x"51", + 622 => x"00", + 623 => x"08", + 624 => x"f8", + 625 => x"0d", + 626 => x"08", + 627 => x"82", + 628 => x"fc", + 629 => x"85", + 630 => x"05", + 631 => x"33", + 632 => x"08", + 633 => x"81", + 634 => x"f8", + 635 => x"0c", + 636 => x"06", + 637 => x"80", + 638 => x"da", + 639 => x"f8", + 640 => x"08", + 641 => x"85", + 642 => x"05", + 643 => x"f8", + 644 => x"08", + 645 => x"08", + 646 => x"31", + 647 => x"ec", + 648 => x"3d", + 649 => x"f8", + 650 => x"85", + 651 => x"82", + 652 => x"fe", + 653 => x"85", + 654 => x"05", + 655 => x"f8", + 656 => x"0c", + 657 => x"08", + 658 => x"52", + 659 => x"85", + 660 => x"05", + 661 => x"82", + 662 => x"8c", + 663 => x"85", + 664 => x"05", + 665 => x"70", + 666 => x"85", + 667 => x"05", + 668 => x"82", + 669 => x"fc", + 670 => x"81", + 671 => x"70", + 672 => x"38", + 673 => x"82", + 674 => x"88", + 675 => x"82", + 676 => x"51", + 677 => x"82", + 678 => x"04", + 679 => x"08", + 680 => x"f8", + 681 => x"0d", + 682 => x"08", + 683 => x"82", + 684 => x"fc", + 685 => x"85", + 686 => x"05", + 687 => x"f8", + 688 => x"0c", + 689 => x"08", + 690 => x"80", + 691 => x"38", + 692 => x"08", + 693 => x"81", + 694 => x"f8", + 695 => x"0c", + 696 => x"08", + 697 => x"ff", + 698 => x"f8", + 699 => x"0c", + 700 => x"08", + 701 => x"80", + 702 => x"82", + 703 => x"f8", + 704 => x"70", + 705 => x"f8", + 706 => x"08", + 707 => x"85", + 708 => x"05", + 709 => x"f8", + 710 => x"08", + 711 => x"71", + 712 => x"f8", + 713 => x"08", + 714 => x"85", + 715 => x"05", + 716 => x"39", + 717 => x"08", + 718 => x"70", + 719 => x"0c", + 720 => x"0d", + 721 => x"0c", + 722 => x"f8", + 723 => x"85", + 724 => x"3d", + 725 => x"f8", + 726 => x"08", + 727 => x"f4", + 728 => x"f8", + 729 => x"08", + 730 => x"82", + 731 => x"8c", + 732 => x"05", + 733 => x"08", + 734 => x"82", + 735 => x"88", + 736 => x"33", + 737 => x"06", + 738 => x"51", + 739 => x"84", + 740 => x"39", + 741 => x"08", + 742 => x"52", + 743 => x"85", + 744 => x"05", + 745 => x"82", + 746 => x"88", + 747 => x"81", + 748 => x"51", + 749 => x"80", + 750 => x"f8", + 751 => x"0c", + 752 => x"82", + 753 => x"90", + 754 => x"05", + 755 => x"08", + 756 => x"82", + 757 => x"90", + 758 => x"2e", + 759 => x"81", + 760 => x"f8", + 761 => x"08", + 762 => x"e8", + 763 => x"f8", + 764 => x"08", + 765 => x"53", + 766 => x"ff", + 767 => x"f8", + 768 => x"0c", + 769 => x"82", + 770 => x"8c", + 771 => x"05", + 772 => x"08", + 773 => x"82", + 774 => x"8c", + 775 => x"33", + 776 => x"8c", + 777 => x"82", + 778 => x"fc", + 779 => x"39", + 780 => x"08", + 781 => x"70", + 782 => x"f8", + 783 => x"08", + 784 => x"71", + 785 => x"85", + 786 => x"05", + 787 => x"52", + 788 => x"39", + 789 => x"85", + 790 => x"05", + 791 => x"f8", + 792 => x"08", + 793 => x"0c", + 794 => x"82", + 795 => x"04", + 796 => x"08", + 797 => x"f8", + 798 => x"0d", + 799 => x"08", + 800 => x"82", + 801 => x"fc", + 802 => x"85", + 803 => x"05", + 804 => x"80", + 805 => x"85", + 806 => x"05", + 807 => x"82", + 808 => x"90", + 809 => x"85", + 810 => x"05", + 811 => x"82", + 812 => x"90", + 813 => x"85", + 814 => x"05", + 815 => x"a9", + 816 => x"f8", + 817 => x"08", + 818 => x"85", + 819 => x"05", + 820 => x"71", + 821 => x"85", + 822 => x"05", + 823 => x"82", + 824 => x"fc", + 825 => x"be", + 826 => x"f8", + 827 => x"08", + 828 => x"ec", + 829 => x"3d", + 830 => x"f8", + 831 => x"85", + 832 => x"82", + 833 => x"f9", + 834 => x"0b", + 835 => x"08", + 836 => x"82", + 837 => x"88", + 838 => x"25", + 839 => x"85", + 840 => x"05", + 841 => x"85", + 842 => x"05", + 843 => x"82", + 844 => x"f4", + 845 => x"85", + 846 => x"05", + 847 => x"81", + 848 => x"f8", + 849 => x"0c", + 850 => x"08", + 851 => x"82", + 852 => x"fc", + 853 => x"85", + 854 => x"05", + 855 => x"b9", + 856 => x"f8", + 857 => x"08", + 858 => x"f8", + 859 => x"0c", + 860 => x"85", + 861 => x"05", + 862 => x"f8", + 863 => x"08", + 864 => x"0b", + 865 => x"08", + 866 => x"82", + 867 => x"f0", + 868 => x"85", + 869 => x"05", + 870 => x"82", + 871 => x"8c", + 872 => x"82", + 873 => x"88", + 874 => x"83", + 875 => x"85", + 876 => x"82", + 877 => x"f8", + 878 => x"82", + 879 => x"fc", + 880 => x"2e", + 881 => x"85", + 882 => x"05", + 883 => x"85", + 884 => x"05", + 885 => x"f8", + 886 => x"08", + 887 => x"ec", + 888 => x"3d", + 889 => x"f8", + 890 => x"85", + 891 => x"82", + 892 => x"fb", + 893 => x"0b", + 894 => x"08", + 895 => x"82", + 896 => x"88", + 897 => x"25", + 898 => x"85", + 899 => x"05", + 900 => x"85", + 901 => x"05", + 902 => x"82", + 903 => x"fc", + 904 => x"85", + 905 => x"05", + 906 => x"90", + 907 => x"f8", + 908 => x"08", + 909 => x"f8", + 910 => x"0c", + 911 => x"85", + 912 => x"05", + 913 => x"85", + 914 => x"05", + 915 => x"a2", + 916 => x"ec", + 917 => x"85", + 918 => x"05", + 919 => x"85", + 920 => x"05", + 921 => x"90", + 922 => x"f8", + 923 => x"08", + 924 => x"f8", + 925 => x"0c", + 926 => x"08", + 927 => x"70", + 928 => x"0c", + 929 => x"0d", + 930 => x"0c", + 931 => x"f8", + 932 => x"85", + 933 => x"3d", + 934 => x"82", + 935 => x"fc", + 936 => x"85", + 937 => x"05", + 938 => x"ff", + 939 => x"70", + 940 => x"08", + 941 => x"06", + 942 => x"08", + 943 => x"11", + 944 => x"08", + 945 => x"82", + 946 => x"88", + 947 => x"2a", + 948 => x"08", + 949 => x"82", + 950 => x"8c", + 951 => x"82", + 952 => x"8c", + 953 => x"51", + 954 => x"85", + 955 => x"05", + 956 => x"84", + 957 => x"39", + 958 => x"08", + 959 => x"70", + 960 => x"0c", + 961 => x"0d", + 962 => x"0c", + 963 => x"f8", + 964 => x"85", + 965 => x"3d", + 966 => x"82", + 967 => x"8c", + 968 => x"82", + 969 => x"88", + 970 => x"80", + 971 => x"85", + 972 => x"82", + 973 => x"54", + 974 => x"82", + 975 => x"04", + 976 => x"08", + 977 => x"f8", + 978 => x"0d", + 979 => x"85", + 980 => x"05", + 981 => x"85", + 982 => x"05", + 983 => x"3f", + 984 => x"08", + 985 => x"ec", + 986 => x"3d", + 987 => x"f8", + 988 => x"85", + 989 => x"82", + 990 => x"fd", + 991 => x"0b", + 992 => x"08", + 993 => x"80", + 994 => x"f8", + 995 => x"0c", + 996 => x"08", + 997 => x"82", + 998 => x"88", + 999 => x"b9", + 1000 => x"f8", + 1001 => x"08", + 1002 => x"38", + 1003 => x"85", + 1004 => x"05", + 1005 => x"38", + 1006 => x"08", + 1007 => x"10", + 1008 => x"08", + 1009 => x"82", + 1010 => x"fc", + 1011 => x"82", + 1012 => x"fc", + 1013 => x"b8", + 1014 => x"f8", + 1015 => x"08", + 1016 => x"e1", + 1017 => x"f8", + 1018 => x"08", + 1019 => x"08", + 1020 => x"26", + 1021 => x"85", + 1022 => x"05", + 1023 => x"f8", + 1024 => x"08", + 1025 => x"f8", + 1026 => x"0c", + 1027 => x"08", + 1028 => x"82", + 1029 => x"fc", + 1030 => x"82", + 1031 => x"f8", + 1032 => x"85", + 1033 => x"05", + 1034 => x"82", + 1035 => x"fc", + 1036 => x"85", + 1037 => x"05", + 1038 => x"82", + 1039 => x"8c", + 1040 => x"95", + 1041 => x"f8", + 1042 => x"08", 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x"39", + 1102 => x"51", + 1103 => x"81", + 1104 => x"80", + 1105 => x"eb", + 1106 => x"cf", + 1107 => x"84", + 1108 => x"39", + 1109 => x"51", + 1110 => x"81", + 1111 => x"bb", + 1112 => x"d0", + 1113 => x"81", + 1114 => x"af", + 1115 => x"90", + 1116 => x"81", + 1117 => x"a3", + 1118 => x"c4", + 1119 => x"81", + 1120 => x"97", + 1121 => x"f0", + 1122 => x"81", + 1123 => x"8b", + 1124 => x"a0", + 1125 => x"81", + 1126 => x"ab", + 1127 => x"3d", + 1128 => x"3d", + 1129 => x"56", + 1130 => x"e7", + 1131 => x"87", + 1132 => x"51", + 1133 => x"74", + 1134 => x"ec", + 1135 => x"39", + 1136 => x"74", + 1137 => x"3f", + 1138 => x"08", + 1139 => x"fa", + 1140 => x"85", + 1141 => x"79", + 1142 => x"81", + 1143 => x"b0", + 1144 => x"3d", + 1145 => x"3d", + 1146 => x"84", + 1147 => x"05", + 1148 => x"80", + 1149 => x"81", + 1150 => x"07", + 1151 => x"57", + 1152 => x"56", + 1153 => x"26", + 1154 => x"56", + 1155 => x"70", + 1156 => x"51", + 1157 => x"74", + 1158 => x"81", + 1159 => x"8c", + 1160 => x"56", + 1161 => x"3f", + 1162 => x"08", + 1163 => x"ec", + 1164 => x"82", + 1165 => x"87", + 1166 => x"0c", + 1167 => x"08", + 1168 => x"d4", + 1169 => x"80", + 1170 => x"75", + 1171 => x"d6", + 1172 => x"ec", + 1173 => x"85", + 1174 => x"38", + 1175 => x"80", + 1176 => x"74", + 1177 => x"59", + 1178 => x"96", + 1179 => x"51", + 1180 => x"3f", + 1181 => x"05", + 1182 => x"80", + 1183 => x"81", + 1184 => x"2a", + 1185 => x"57", + 1186 => x"80", + 1187 => x"81", + 1188 => x"87", + 1189 => x"08", + 1190 => x"fe", + 1191 => x"56", + 1192 => x"ec", + 1193 => x"0d", + 1194 => x"0d", + 1195 => x"05", + 1196 => x"57", + 1197 => x"80", + 1198 => x"79", + 1199 => x"3f", + 1200 => x"08", + 1201 => x"80", + 1202 => x"75", + 1203 => x"38", + 1204 => x"55", + 1205 => x"85", + 1206 => x"52", + 1207 => x"2d", + 1208 => x"08", + 1209 => x"77", + 1210 => x"85", + 1211 => x"3d", + 1212 => x"3d", + 1213 => x"63", + 1214 => x"80", + 1215 => x"73", + 1216 => x"41", + 1217 => x"5e", + 1218 => x"52", + 1219 => x"51", + 1220 => x"81", + 1221 => x"a8", + 1222 => x"55", + 1223 => x"80", + 1224 => x"90", + 1225 => x"7b", + 1226 => x"38", + 1227 => x"74", + 1228 => x"7a", + 1229 => x"72", + 1230 => x"ee", + 1231 => x"9e", + 1232 => x"81", + 1233 => x"a8", + 1234 => x"15", + 1235 => x"74", + 1236 => x"7a", + 1237 => x"72", + 1238 => x"ee", + 1239 => x"fe", + 1240 => x"81", + 1241 => x"a8", + 1242 => x"15", + 1243 => x"74", + 1244 => x"7a", + 1245 => x"72", + 1246 => x"ef", + 1247 => x"de", + 1248 => x"81", + 1249 => x"a7", + 1250 => x"15", + 1251 => x"a7", + 1252 => x"88", + 1253 => x"94", + 1254 => x"3f", + 1255 => x"79", + 1256 => x"74", + 1257 => x"55", + 1258 => x"72", + 1259 => x"38", + 1260 => x"53", + 1261 => x"83", + 1262 => x"75", + 1263 => x"81", + 1264 => x"53", + 1265 => x"8b", + 1266 => x"fe", + 1267 => x"73", + 1268 => x"a0", + 1269 => x"3f", + 1270 => x"c2", + 1271 => x"98", + 1272 => x"3f", + 1273 => x"1c", + 1274 => x"fb", + 1275 => x"ec", + 1276 => x"70", + 1277 => x"57", + 1278 => x"09", + 1279 => x"38", + 1280 => x"82", + 1281 => x"98", + 1282 => x"2c", + 1283 => x"70", + 1284 => x"72", + 1285 => x"09", + 1286 => x"72", + 1287 => x"07", + 1288 => x"58", + 1289 => x"57", + 1290 => x"d4", + 1291 => x"2e", + 1292 => x"85", + 1293 => x"8c", + 1294 => x"53", + 1295 => x"fd", + 1296 => x"53", + 1297 => x"ec", + 1298 => x"0d", + 1299 => x"0d", + 1300 => x"33", + 1301 => x"53", + 1302 => x"52", + 1303 => x"3f", + 1304 => x"22", + 1305 => x"3f", + 1306 => x"54", + 1307 => x"53", + 1308 => x"33", + 1309 => x"c0", + 1310 => x"3f", + 1311 => x"84", + 1312 => x"3f", + 1313 => x"04", + 1314 => x"87", + 1315 => x"08", + 1316 => x"3f", + 1317 => x"eb", + 1318 => x"dc", + 1319 => x"3f", + 1320 => x"df", + 1321 => x"2a", + 1322 => x"51", + 1323 => x"2e", + 1324 => x"51", + 1325 => x"81", + 1326 => x"98", + 1327 => x"51", + 1328 => x"72", + 1329 => x"81", + 1330 => x"71", + 1331 => x"38", + 1332 => x"af", + 1333 => x"88", + 1334 => x"3f", + 1335 => x"a3", + 1336 => x"2a", + 1337 => x"51", + 1338 => x"2e", + 1339 => x"51", + 1340 => x"81", + 1341 => x"98", + 1342 => x"51", + 1343 => x"72", + 1344 => x"81", + 1345 => x"71", + 1346 => x"38", + 1347 => x"f3", + 1348 => x"ac", + 1349 => x"3f", + 1350 => x"e7", + 1351 => x"2a", + 1352 => x"51", + 1353 => x"2e", + 1354 => x"51", + 1355 => x"81", + 1356 => x"97", + 1357 => x"51", + 1358 => x"72", + 1359 => x"81", + 1360 => x"71", + 1361 => x"38", + 1362 => x"b7", + 1363 => x"d4", + 1364 => x"3f", + 1365 => x"ab", + 1366 => x"2a", + 1367 => x"51", + 1368 => x"2e", + 1369 => x"51", + 1370 => x"81", + 1371 => x"97", + 1372 => x"51", + 1373 => x"72", + 1374 => x"81", + 1375 => x"71", + 1376 => x"38", + 1377 => x"fb", + 1378 => x"fc", + 1379 => x"3f", + 1380 => x"ef", + 1381 => x"3f", + 1382 => x"04", + 1383 => x"77", + 1384 => x"a3", + 1385 => x"55", + 1386 => x"52", + 1387 => x"c0", + 1388 => x"82", + 1389 => x"54", + 1390 => x"81", + 1391 => x"bc", + 1392 => x"cc", + 1393 => x"f7", + 1394 => x"ec", + 1395 => x"05", + 1396 => x"ec", + 1397 => x"25", + 1398 => x"51", + 1399 => x"0b", + 1400 => x"e8", + 1401 => x"82", + 1402 => x"54", + 1403 => x"09", + 1404 => x"38", + 1405 => x"53", + 1406 => x"51", + 1407 => x"3f", + 1408 => x"08", + 1409 => x"38", + 1410 => x"08", + 1411 => x"3f", + 1412 => x"9c", + 1413 => x"8b", + 1414 => x"0b", + 1415 => x"80", + 1416 => x"0b", + 1417 => x"33", + 1418 => x"2e", + 1419 => x"8c", + 1420 => x"cc", + 1421 => x"75", + 1422 => x"3f", + 1423 => x"85", + 1424 => x"3d", + 1425 => x"3d", + 1426 => x"71", + 1427 => x"0c", + 1428 => x"52", + 1429 => x"cd", + 1430 => x"85", + 1431 => x"ff", + 1432 => x"7d", + 1433 => x"06", + 1434 => x"f1", + 1435 => x"3d", + 1436 => x"a7", + 1437 => x"53", + 1438 => x"86", + 1439 => x"fc", + 1440 => x"85", + 1441 => x"2e", + 1442 => x"f1", + 1443 => x"8a", + 1444 => x"5f", + 1445 => x"90", + 1446 => x"3f", + 1447 => x"46", + 1448 => x"52", + 1449 => x"f4", + 1450 => x"ff", + 1451 => x"f3", + 1452 => x"85", + 1453 => x"2b", + 1454 => x"51", + 1455 => x"c2", + 1456 => x"38", + 1457 => x"24", + 1458 => x"bd", + 1459 => x"38", + 1460 => x"90", + 1461 => x"2e", + 1462 => x"78", + 1463 => x"da", + 1464 => x"39", + 1465 => x"2e", + 1466 => x"78", + 1467 => x"85", + 1468 => x"bf", + 1469 => x"38", + 1470 => x"78", + 1471 => x"89", + 1472 => x"80", + 1473 => x"38", + 1474 => x"2e", + 1475 => x"78", + 1476 => x"89", + 1477 => x"86", + 1478 => x"83", + 1479 => x"38", + 1480 => x"24", + 1481 => x"81", + 1482 => x"d3", + 1483 => x"39", + 1484 => x"2e", + 1485 => x"89", + 1486 => x"3d", + 1487 => x"53", + 1488 => x"51", + 1489 => x"82", + 1490 => x"80", + 1491 => x"38", + 1492 => x"fc", + 1493 => x"84", + 1494 => x"fa", + 1495 => x"ec", + 1496 => x"fe", + 1497 => x"3d", + 1498 => x"53", + 1499 => x"51", + 1500 => x"82", + 1501 => x"86", + 1502 => x"ec", + 1503 => x"f2", + 1504 => x"ea", + 1505 => x"5c", + 1506 => x"27", + 1507 => x"61", + 1508 => x"70", + 1509 => x"0c", + 1510 => x"f5", + 1511 => x"39", + 1512 => x"80", + 1513 => x"84", + 1514 => x"aa", + 1515 => x"ec", + 1516 => x"fd", + 1517 => x"3d", + 1518 => x"53", + 1519 => x"51", + 1520 => x"82", + 1521 => x"80", + 1522 => x"38", + 1523 => x"f8", + 1524 => x"84", + 1525 => x"fe", + 1526 => x"ec", + 1527 => x"fd", + 1528 => x"f2", + 1529 => x"86", + 1530 => x"79", + 1531 => x"87", + 1532 => x"79", + 1533 => x"5b", + 1534 => x"61", + 1535 => x"eb", + 1536 => x"ff", + 1537 => x"ff", + 1538 => x"a6", + 1539 => x"85", + 1540 => x"2e", + 1541 => x"b4", + 1542 => x"11", + 1543 => x"05", + 1544 => x"3f", + 1545 => x"08", + 1546 => x"e9", + 1547 => x"fe", + 1548 => x"ff", + 1549 => x"a6", + 1550 => x"85", + 1551 => x"2e", + 1552 => x"81", + 1553 => x"9e", + 1554 => x"5a", + 1555 => x"a7", + 1556 => x"33", + 1557 => x"5a", + 1558 => x"2e", + 1559 => x"55", + 1560 => x"33", + 1561 => x"81", + 1562 => x"a3", + 1563 => x"1a", + 1564 => x"43", + 1565 => x"81", + 1566 => x"82", + 1567 => x"3d", + 1568 => x"53", + 1569 => x"51", + 1570 => x"82", + 1571 => x"80", + 1572 => x"84", + 1573 => x"78", + 1574 => x"38", + 1575 => x"08", + 1576 => x"39", + 1577 => x"33", + 1578 => x"2e", + 1579 => x"84", + 1580 => x"bc", + 1581 => x"da", + 1582 => x"80", + 1583 => x"82", + 1584 => x"44", + 1585 => x"84", + 1586 => x"78", + 1587 => x"38", + 1588 => x"08", + 1589 => x"82", + 1590 => x"59", + 1591 => x"88", + 1592 => x"b0", + 1593 => x"39", + 1594 => x"08", + 1595 => x"44", + 1596 => x"fc", + 1597 => x"84", + 1598 => x"da", + 1599 => x"ec", + 1600 => x"38", + 1601 => x"33", + 1602 => x"2e", + 1603 => x"84", + 1604 => x"80", + 1605 => x"84", + 1606 => x"78", + 1607 => x"38", + 1608 => x"08", + 1609 => x"82", + 1610 => x"59", + 1611 => x"88", + 1612 => x"a4", + 1613 => x"39", + 1614 => x"33", + 1615 => x"2e", + 1616 => x"84", + 1617 => x"99", + 1618 => x"d6", + 1619 => x"80", + 1620 => x"82", + 1621 => x"43", + 1622 => x"84", + 1623 => x"05", + 1624 => x"fe", + 1625 => x"ff", + 1626 => x"a3", + 1627 => x"85", + 1628 => x"2e", + 1629 => x"62", + 1630 => x"88", + 1631 => x"81", + 1632 => x"32", + 1633 => x"05", + 1634 => x"9f", + 1635 => x"06", + 1636 => x"5a", + 1637 => x"88", + 1638 => x"2e", + 1639 => x"42", + 1640 => x"51", + 1641 => x"a0", + 1642 => x"61", + 1643 => x"63", + 1644 => x"3f", + 1645 => x"51", + 1646 => x"f9", + 1647 => x"3d", + 1648 => x"53", + 1649 => x"51", + 1650 => x"82", + 1651 => x"80", + 1652 => x"38", + 1653 => x"fc", + 1654 => x"84", + 1655 => x"f6", + 1656 => x"ec", + 1657 => x"a4", + 1658 => x"02", + 1659 => x"33", + 1660 => x"81", + 1661 => x"3d", + 1662 => x"53", + 1663 => x"51", + 1664 => x"82", + 1665 => x"e1", + 1666 => x"39", + 1667 => x"54", + 1668 => x"f8", + 1669 => x"3f", + 1670 => x"79", + 1671 => x"3f", + 1672 => x"33", + 1673 => x"2e", + 1674 => x"9f", + 1675 => x"38", + 1676 => x"fc", + 1677 => x"84", + 1678 => x"9a", + 1679 => x"ec", + 1680 => x"91", + 1681 => x"02", + 1682 => x"33", + 1683 => x"81", + 1684 => x"b8", + 1685 => x"84", + 1686 => x"3f", + 1687 => x"b4", + 1688 => x"11", + 1689 => x"05", + 1690 => x"3f", + 1691 => x"08", + 1692 => x"a1", + 1693 => x"fe", + 1694 => x"ff", + 1695 => x"a3", + 1696 => x"85", + 1697 => x"2e", + 1698 => x"59", + 1699 => x"22", + 1700 => x"05", + 1701 => x"41", + 1702 => x"f0", + 1703 => x"84", + 1704 => x"ae", + 1705 => x"ec", + 1706 => x"f7", + 1707 => x"70", + 1708 => x"81", + 1709 => x"9f", + 1710 => x"f8", + 1711 => x"9f", + 1712 => x"45", + 1713 => x"78", + 1714 => x"c9", + 1715 => x"26", + 1716 => x"82", + 1717 => x"39", + 1718 => x"f0", + 1719 => x"84", + 1720 => x"ee", + 1721 => x"ec", + 1722 => x"92", + 1723 => x"02", + 1724 => x"79", + 1725 => x"5b", + 1726 => x"ff", + 1727 => x"f3", + 1728 => x"ea", + 1729 => x"39", + 1730 => x"f4", + 1731 => x"84", + 1732 => x"be", + 1733 => x"ec", + 1734 => x"f6", + 1735 => x"3d", + 1736 => x"53", + 1737 => x"51", + 1738 => x"82", + 1739 => x"80", + 1740 => x"60", + 1741 => x"59", + 1742 => x"41", + 1743 => x"f0", + 1744 => x"84", + 1745 => x"8a", + 1746 => x"ec", + 1747 => x"f6", + 1748 => x"70", + 1749 => x"81", + 1750 => x"9e", + 1751 => x"f8", + 1752 => x"9e", + 1753 => x"45", + 1754 => x"78", + 1755 => x"a5", + 1756 => x"27", + 1757 => x"3d", + 1758 => x"53", + 1759 => x"51", + 1760 => x"82", + 1761 => x"80", + 1762 => x"60", + 1763 => x"59", + 1764 => x"41", + 1765 => x"81", + 1766 => x"97", + 1767 => x"b2", + 1768 => x"ff", + 1769 => x"ff", + 1770 => x"9f", + 1771 => x"85", + 1772 => x"2e", + 1773 => x"63", + 1774 => x"a4", + 1775 => x"3f", + 1776 => x"04", + 1777 => x"80", + 1778 => x"84", + 1779 => x"86", + 1780 => x"ec", + 1781 => x"f5", + 1782 => x"52", + 1783 => x"51", + 1784 => x"63", + 1785 => x"82", + 1786 => x"80", + 1787 => x"38", + 1788 => x"08", + 1789 => x"dc", + 1790 => x"3f", + 1791 => x"81", + 1792 => x"96", + 1793 => x"96", + 1794 => x"39", + 1795 => x"51", + 1796 => x"80", + 1797 => x"39", + 1798 => x"f4", + 1799 => x"45", + 1800 => x"78", + 1801 => x"ed", + 1802 => x"06", + 1803 => x"2e", + 1804 => x"b4", + 1805 => x"05", + 1806 => x"3f", + 1807 => x"08", + 1808 => x"7a", + 1809 => x"38", + 1810 => x"89", + 1811 => x"2e", + 1812 => x"ca", + 1813 => x"2e", + 1814 => x"c2", + 1815 => x"a8", + 1816 => x"81", + 1817 => x"80", + 1818 => x"b0", + 1819 => x"ff", + 1820 => x"9b", + 1821 => x"39", + 1822 => x"52", + 1823 => x"b0", + 1824 => x"f0", + 1825 => x"7b", + 1826 => x"ac", + 1827 => x"81", + 1828 => x"b4", + 1829 => x"05", + 1830 => x"3f", + 1831 => x"54", + 1832 => x"f4", + 1833 => x"3d", + 1834 => x"51", + 1835 => x"82", + 1836 => x"82", + 1837 => x"80", + 1838 => x"80", + 1839 => x"80", + 1840 => x"80", + 1841 => x"ff", + 1842 => x"eb", + 1843 => x"85", + 1844 => x"85", + 1845 => x"70", + 1846 => x"70", + 1847 => x"25", + 1848 => x"5f", + 1849 => x"83", + 1850 => x"81", + 1851 => x"06", + 1852 => x"2e", + 1853 => x"1b", + 1854 => x"06", + 1855 => x"fe", + 1856 => x"81", + 1857 => x"32", + 1858 => x"8a", + 1859 => x"2e", + 1860 => x"f3", + 1861 => x"f4", + 1862 => x"c2", + 1863 => x"39", + 1864 => x"80", + 1865 => x"fc", + 1866 => x"94", + 1867 => x"54", + 1868 => x"80", + 1869 => x"e3", + 1870 => x"85", + 1871 => x"2b", + 1872 => x"53", + 1873 => x"52", + 1874 => x"c1", + 1875 => x"85", + 1876 => x"75", + 1877 => x"94", + 1878 => x"54", + 1879 => x"80", + 1880 => x"e3", + 1881 => x"85", + 1882 => x"2b", + 1883 => x"53", + 1884 => x"52", + 1885 => x"95", + 1886 => x"85", + 1887 => x"75", + 1888 => x"83", + 1889 => x"94", + 1890 => x"80", + 1891 => x"c0", + 1892 => x"80", + 1893 => x"82", + 1894 => x"80", + 1895 => x"82", + 1896 => x"89", + 1897 => x"d7", + 1898 => x"e4", + 1899 => x"3f", + 1900 => x"51", + 1901 => x"a9", + 1902 => x"be", + 1903 => x"ed", + 1904 => x"82", + 1905 => x"fe", + 1906 => x"52", + 1907 => x"88", + 1908 => x"c4", + 1909 => x"ec", + 1910 => x"06", + 1911 => x"14", + 1912 => x"80", + 1913 => x"71", + 1914 => x"0c", + 1915 => x"04", + 1916 => x"76", + 1917 => x"55", + 1918 => x"54", + 1919 => x"81", + 1920 => x"33", + 1921 => x"2e", + 1922 => x"86", + 1923 => x"53", + 1924 => x"33", + 1925 => x"2e", + 1926 => x"86", + 1927 => x"53", + 1928 => x"52", + 1929 => x"09", + 1930 => x"38", + 1931 => x"12", + 1932 => x"33", + 1933 => x"a2", + 1934 => x"81", + 1935 => x"2e", + 1936 => x"ea", + 1937 => x"81", + 1938 => x"72", + 1939 => x"70", + 1940 => x"38", + 1941 => x"80", + 1942 => x"73", + 1943 => x"72", + 1944 => x"70", + 1945 => x"81", + 1946 => x"81", + 1947 => x"32", + 1948 => x"05", + 1949 => x"76", + 1950 => x"51", + 1951 => x"88", + 1952 => x"70", + 1953 => x"34", + 1954 => x"72", + 1955 => x"85", + 1956 => x"3d", + 1957 => x"3d", + 1958 => x"72", + 1959 => x"91", + 1960 => x"fc", + 1961 => x"51", + 1962 => x"82", + 1963 => x"85", + 1964 => x"83", + 1965 => x"72", + 1966 => x"0c", + 1967 => x"04", + 1968 => x"76", + 1969 => x"ff", + 1970 => x"81", + 1971 => x"26", + 1972 => x"83", + 1973 => x"05", + 1974 => x"70", + 1975 => x"8a", + 1976 => x"33", + 1977 => x"70", + 1978 => x"fe", + 1979 => x"33", + 1980 => x"70", + 1981 => x"f2", + 1982 => x"33", + 1983 => x"70", + 1984 => x"e6", + 1985 => x"22", + 1986 => x"74", + 1987 => x"80", + 1988 => x"13", + 1989 => x"52", + 1990 => x"26", + 1991 => x"81", + 1992 => x"98", + 1993 => x"22", + 1994 => x"bc", + 1995 => x"33", + 1996 => x"b8", + 1997 => x"33", + 1998 => x"b4", + 1999 => x"33", + 2000 => x"b0", + 2001 => x"33", + 2002 => x"ac", + 2003 => x"33", + 2004 => x"a8", + 2005 => x"c0", + 2006 => x"73", + 2007 => x"a0", + 2008 => x"87", + 2009 => x"0c", + 2010 => x"82", + 2011 => x"86", + 2012 => x"f3", + 2013 => x"5b", + 2014 => x"9c", + 2015 => x"0c", + 2016 => x"bc", + 2017 => x"7b", + 2018 => x"98", + 2019 => x"79", + 2020 => x"87", + 2021 => x"08", + 2022 => x"1c", + 2023 => x"98", + 2024 => x"79", + 2025 => x"87", + 2026 => x"08", + 2027 => x"1c", + 2028 => x"98", + 2029 => x"79", + 2030 => x"87", + 2031 => x"08", + 2032 => x"1c", + 2033 => x"98", + 2034 => x"79", + 2035 => x"80", + 2036 => x"83", + 2037 => x"59", + 2038 => x"ff", + 2039 => x"1b", + 2040 => x"1b", + 2041 => x"1b", + 2042 => x"1b", + 2043 => x"1b", + 2044 => x"83", + 2045 => x"52", + 2046 => x"51", + 2047 => x"8f", + 2048 => x"ff", + 2049 => x"8f", + 2050 => x"09", + 2051 => x"9f", + 2052 => x"52", + 2053 => x"8c", + 2054 => x"0d", + 2055 => x"0d", + 2056 => x"8c", + 2057 => x"ff", + 2058 => x"56", + 2059 => x"84", + 2060 => x"2e", + 2061 => x"c0", + 2062 => x"70", + 2063 => x"2a", + 2064 => x"53", + 2065 => x"80", + 2066 => x"71", + 2067 => x"81", + 2068 => x"70", + 2069 => x"81", + 2070 => x"06", + 2071 => x"80", + 2072 => x"71", + 2073 => x"81", + 2074 => x"70", + 2075 => x"73", + 2076 => x"51", + 2077 => x"80", + 2078 => x"2e", + 2079 => x"c0", + 2080 => x"75", + 2081 => x"82", + 2082 => x"87", + 2083 => x"fb", + 2084 => x"9f", + 2085 => x"84", + 2086 => x"81", + 2087 => x"55", + 2088 => x"94", + 2089 => x"80", + 2090 => x"87", + 2091 => x"51", + 2092 => x"96", + 2093 => x"06", + 2094 => x"70", + 2095 => x"38", + 2096 => x"70", + 2097 => x"51", + 2098 => x"72", + 2099 => x"81", + 2100 => x"70", + 2101 => x"38", + 2102 => x"70", + 2103 => x"51", + 2104 => x"38", + 2105 => x"06", + 2106 => x"94", + 2107 => x"80", + 2108 => x"87", + 2109 => x"52", + 2110 => x"87", + 2111 => x"f9", + 2112 => x"54", + 2113 => x"70", + 2114 => x"53", + 2115 => x"77", + 2116 => x"38", + 2117 => x"06", + 2118 => x"84", + 2119 => x"81", + 2120 => x"57", + 2121 => x"c0", + 2122 => x"75", + 2123 => x"38", + 2124 => x"94", + 2125 => x"70", + 2126 => x"81", + 2127 => x"52", + 2128 => x"8c", + 2129 => x"2a", + 2130 => x"51", + 2131 => x"38", + 2132 => x"70", + 2133 => x"51", + 2134 => x"8d", + 2135 => x"2a", + 2136 => x"51", + 2137 => x"be", + 2138 => x"ff", + 2139 => x"c0", + 2140 => x"70", + 2141 => x"38", + 2142 => x"90", + 2143 => x"0c", + 2144 => x"33", + 2145 => x"06", + 2146 => x"70", + 2147 => x"76", + 2148 => x"0c", + 2149 => x"04", + 2150 => x"82", + 2151 => x"70", + 2152 => x"54", + 2153 => x"94", + 2154 => x"80", + 2155 => x"87", + 2156 => x"51", + 2157 => x"82", + 2158 => x"06", + 2159 => x"70", + 2160 => x"38", + 2161 => x"06", + 2162 => x"94", + 2163 => x"80", + 2164 => x"87", + 2165 => x"52", + 2166 => x"81", + 2167 => x"85", + 2168 => x"84", + 2169 => x"fe", + 2170 => x"84", + 2171 => x"81", + 2172 => x"53", + 2173 => x"84", + 2174 => x"2e", + 2175 => x"c0", + 2176 => x"71", + 2177 => x"2a", + 2178 => x"51", + 2179 => x"52", + 2180 => x"a0", + 2181 => x"ff", + 2182 => x"c0", + 2183 => x"70", + 2184 => x"38", + 2185 => x"90", + 2186 => x"70", + 2187 => x"98", + 2188 => x"51", + 2189 => x"ec", + 2190 => x"0d", + 2191 => x"0d", + 2192 => x"80", + 2193 => x"2a", + 2194 => x"51", + 2195 => x"84", + 2196 => x"c0", + 2197 => x"82", + 2198 => x"87", + 2199 => x"08", + 2200 => x"0c", + 2201 => x"94", + 2202 => x"98", + 2203 => x"9e", + 2204 => x"84", + 2205 => x"c0", + 2206 => x"82", + 2207 => x"87", + 2208 => x"08", + 2209 => x"0c", + 2210 => x"ac", + 2211 => x"a8", + 2212 => x"9e", + 2213 => x"84", + 2214 => x"c0", + 2215 => x"82", + 2216 => x"87", + 2217 => x"08", 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x"da", + 2277 => x"87", + 2278 => x"08", + 2279 => x"80", + 2280 => x"52", + 2281 => x"83", + 2282 => x"71", + 2283 => x"34", + 2284 => x"c0", + 2285 => x"70", + 2286 => x"06", + 2287 => x"70", + 2288 => x"38", + 2289 => x"82", + 2290 => x"80", + 2291 => x"9e", + 2292 => x"81", + 2293 => x"51", + 2294 => x"80", + 2295 => x"81", + 2296 => x"84", + 2297 => x"0b", + 2298 => x"90", + 2299 => x"c0", + 2300 => x"52", + 2301 => x"2e", + 2302 => x"52", + 2303 => x"de", + 2304 => x"87", + 2305 => x"08", + 2306 => x"06", + 2307 => x"70", + 2308 => x"38", + 2309 => x"82", + 2310 => x"87", + 2311 => x"08", + 2312 => x"06", + 2313 => x"51", + 2314 => x"82", + 2315 => x"80", + 2316 => x"9e", + 2317 => x"84", + 2318 => x"52", + 2319 => x"2e", + 2320 => x"52", + 2321 => x"e1", + 2322 => x"9e", + 2323 => x"83", + 2324 => x"84", + 2325 => x"51", + 2326 => x"e2", + 2327 => x"87", + 2328 => x"08", + 2329 => x"51", + 2330 => x"80", + 2331 => x"81", + 2332 => x"84", + 2333 => x"c0", + 2334 => x"70", + 2335 => x"51", + 2336 => x"e4", + 2337 => x"0d", + 2338 => x"0d", + 2339 => x"51", + 2340 => x"82", + 2341 => x"54", + 2342 => x"88", + 2343 => x"b4", + 2344 => x"3f", + 2345 => x"51", + 2346 => x"82", + 2347 => x"54", + 2348 => x"93", + 2349 => x"b0", + 2350 => x"b4", + 2351 => x"52", + 2352 => x"51", + 2353 => x"82", + 2354 => x"54", + 2355 => x"93", + 2356 => x"a8", + 2357 => x"ac", + 2358 => x"52", + 2359 => x"51", + 2360 => x"82", + 2361 => x"54", + 2362 => x"93", + 2363 => x"90", + 2364 => x"94", + 2365 => x"52", + 2366 => x"51", + 2367 => x"82", + 2368 => x"54", + 2369 => x"93", + 2370 => x"98", + 2371 => x"9c", + 2372 => x"52", + 2373 => x"51", + 2374 => x"82", + 2375 => x"54", + 2376 => x"93", + 2377 => x"a0", + 2378 => x"a4", + 2379 => x"52", + 2380 => x"51", + 2381 => x"82", + 2382 => x"54", + 2383 => x"8d", + 2384 => x"e0", + 2385 => x"f6", + 2386 => x"92", + 2387 => x"e3", + 2388 => x"80", + 2389 => x"82", + 2390 => x"52", + 2391 => x"51", + 2392 => x"82", + 2393 => x"54", + 2394 => x"8d", + 2395 => x"e2", + 2396 => x"f7", + 2397 => x"e6", + 2398 => x"d5", + 2399 => x"80", + 2400 => x"81", + 2401 => x"83", + 2402 => x"84", + 2403 => x"73", + 2404 => x"38", + 2405 => x"51", + 2406 => x"82", + 2407 => x"54", + 2408 => x"88", + 2409 => x"ec", + 2410 => x"3f", + 2411 => x"33", + 2412 => x"2e", + 2413 => x"f7", + 2414 => x"b2", + 2415 => x"de", + 2416 => x"80", + 2417 => x"81", + 2418 => x"83", + 2419 => x"f8", + 2420 => x"9a", + 2421 => x"b8", + 2422 => x"f8", + 2423 => x"fe", + 2424 => x"bc", + 2425 => x"f8", + 2426 => x"f2", + 2427 => x"c0", + 2428 => x"f8", + 2429 => x"e6", + 2430 => x"94", + 2431 => x"3f", + 2432 => x"22", + 2433 => x"9c", + 2434 => x"3f", + 2435 => x"08", + 2436 => x"c0", + 2437 => x"d1", + 2438 => x"85", + 2439 => x"bd", + 2440 => x"82", + 2441 => x"51", + 2442 => x"74", + 2443 => x"08", + 2444 => x"52", + 2445 => x"51", + 2446 => x"82", + 2447 => x"54", + 2448 => x"b0", + 2449 => x"cc", + 2450 => x"84", + 2451 => x"51", + 2452 => x"82", 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x"9c", + 2512 => x"71", + 2513 => x"38", + 2514 => x"2d", + 2515 => x"04", + 2516 => x"02", + 2517 => x"82", + 2518 => x"76", + 2519 => x"0c", + 2520 => x"ad", + 2521 => x"9c", + 2522 => x"3d", + 2523 => x"3d", + 2524 => x"73", + 2525 => x"ff", + 2526 => x"71", + 2527 => x"38", + 2528 => x"06", + 2529 => x"54", + 2530 => x"e7", + 2531 => x"0d", + 2532 => x"0d", + 2533 => x"f4", + 2534 => x"9c", + 2535 => x"54", + 2536 => x"81", + 2537 => x"53", + 2538 => x"8e", + 2539 => x"ff", + 2540 => x"14", + 2541 => x"3f", + 2542 => x"82", + 2543 => x"86", + 2544 => x"ec", + 2545 => x"68", + 2546 => x"70", + 2547 => x"33", + 2548 => x"2e", + 2549 => x"75", + 2550 => x"81", + 2551 => x"38", + 2552 => x"70", + 2553 => x"33", + 2554 => x"75", + 2555 => x"81", + 2556 => x"81", + 2557 => x"75", + 2558 => x"81", + 2559 => x"82", + 2560 => x"81", + 2561 => x"56", + 2562 => x"09", + 2563 => x"38", + 2564 => x"71", + 2565 => x"81", + 2566 => x"59", + 2567 => x"9f", + 2568 => x"53", + 2569 => x"97", + 2570 => x"2b", + 2571 => x"11", + 2572 => x"7b", + 2573 => x"5d", + 2574 => x"51", + 2575 => x"75", + 2576 => x"70", + 2577 => x"70", + 2578 => x"25", + 2579 => x"32", + 2580 => x"05", + 2581 => x"80", + 2582 => x"53", + 2583 => x"55", + 2584 => x"2e", + 2585 => x"84", + 2586 => x"81", + 2587 => x"57", + 2588 => x"2e", + 2589 => x"75", + 2590 => x"76", + 2591 => x"e0", + 2592 => x"ff", + 2593 => x"73", + 2594 => x"81", + 2595 => x"80", + 2596 => x"38", + 2597 => x"2e", + 2598 => x"73", + 2599 => x"8b", + 2600 => x"c2", + 2601 => x"38", + 2602 => x"73", + 2603 => x"81", + 2604 => x"8f", + 2605 => x"d5", + 2606 => x"38", + 2607 => x"24", + 2608 => x"80", + 2609 => x"38", + 2610 => x"73", + 2611 => x"80", + 2612 => x"ef", + 2613 => x"19", + 2614 => x"59", + 2615 => x"33", + 2616 => x"75", + 2617 => x"81", + 2618 => x"70", + 2619 => x"55", + 2620 => x"79", + 2621 => x"90", + 2622 => x"16", + 2623 => x"7b", + 2624 => x"a0", + 2625 => x"3f", + 2626 => x"53", + 2627 => x"e9", + 2628 => x"fc", + 2629 => x"81", + 2630 => x"72", + 2631 => x"aa", + 2632 => x"fb", + 2633 => x"39", + 2634 => x"83", + 2635 => x"59", + 2636 => x"82", + 2637 => x"88", + 2638 => x"8a", + 2639 => x"90", + 2640 => x"75", + 2641 => x"3f", + 2642 => x"79", + 2643 => x"81", + 2644 => x"72", + 2645 => x"38", + 2646 => x"59", + 2647 => x"84", + 2648 => x"58", + 2649 => x"80", + 2650 => x"09", + 2651 => x"72", + 2652 => x"51", + 2653 => x"74", + 2654 => x"38", + 2655 => x"8a", + 2656 => x"81", + 2657 => x"07", + 2658 => x"0b", + 2659 => x"57", + 2660 => x"51", + 2661 => x"82", + 2662 => x"81", + 2663 => x"53", + 2664 => x"ca", + 2665 => x"85", + 2666 => x"89", + 2667 => x"38", + 2668 => x"75", + 2669 => x"84", + 2670 => x"53", + 2671 => x"06", + 2672 => x"53", + 2673 => x"81", + 2674 => x"81", + 2675 => x"81", + 2676 => x"07", + 2677 => x"54", + 2678 => x"26", + 2679 => x"ff", + 2680 => x"84", + 2681 => x"06", + 2682 => x"80", + 2683 => x"96", + 2684 => x"e0", + 2685 => x"73", + 2686 => x"57", + 2687 => x"06", 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x"70", + 2747 => x"70", + 2748 => x"51", + 2749 => x"2e", + 2750 => x"80", + 2751 => x"ff", + 2752 => x"39", + 2753 => x"c6", + 2754 => x"52", + 2755 => x"ff", + 2756 => x"14", + 2757 => x"34", + 2758 => x"72", + 2759 => x"3f", + 2760 => x"73", + 2761 => x"72", + 2762 => x"f7", + 2763 => x"53", + 2764 => x"ec", + 2765 => x"0d", + 2766 => x"0d", + 2767 => x"08", + 2768 => x"f8", + 2769 => x"76", + 2770 => x"ec", + 2771 => x"9c", + 2772 => x"3d", + 2773 => x"3d", + 2774 => x"5a", + 2775 => x"7a", + 2776 => x"08", + 2777 => x"53", + 2778 => x"09", + 2779 => x"38", + 2780 => x"0c", + 2781 => x"ad", + 2782 => x"06", + 2783 => x"76", + 2784 => x"0c", + 2785 => x"33", + 2786 => x"73", + 2787 => x"81", + 2788 => x"38", + 2789 => x"05", + 2790 => x"08", + 2791 => x"53", + 2792 => x"2e", + 2793 => x"57", + 2794 => x"2e", + 2795 => x"39", + 2796 => x"13", + 2797 => x"08", + 2798 => x"53", + 2799 => x"55", + 2800 => x"81", + 2801 => x"14", + 2802 => x"88", + 2803 => x"27", + 2804 => x"f5", + 2805 => x"53", + 2806 => x"89", + 2807 => x"38", + 2808 => x"55", + 2809 => x"8a", + 2810 => x"a0", + 2811 => x"ca", + 2812 => x"74", + 2813 => x"e0", + 2814 => x"ff", + 2815 => x"d0", + 2816 => x"ff", + 2817 => x"90", + 2818 => x"38", + 2819 => x"81", + 2820 => x"53", + 2821 => x"ca", + 2822 => x"27", + 2823 => x"52", + 2824 => x"e9", + 2825 => x"ec", + 2826 => x"08", + 2827 => x"0c", + 2828 => x"33", + 2829 => x"ff", + 2830 => x"80", + 2831 => x"74", + 2832 => x"55", + 2833 => x"81", + 2834 => x"85", + 2835 => x"3d", + 2836 => x"3d", + 2837 => x"5a", + 2838 => x"7a", + 2839 => x"08", + 2840 => x"53", + 2841 => x"09", + 2842 => x"38", + 2843 => x"0c", + 2844 => x"ad", + 2845 => x"06", + 2846 => x"76", + 2847 => x"0c", + 2848 => x"33", + 2849 => x"73", + 2850 => x"81", + 2851 => x"38", + 2852 => x"05", + 2853 => x"08", + 2854 => x"53", + 2855 => x"2e", + 2856 => x"57", + 2857 => x"2e", + 2858 => x"39", + 2859 => x"13", + 2860 => x"08", + 2861 => x"53", + 2862 => x"55", + 2863 => x"81", + 2864 => x"14", + 2865 => x"88", + 2866 => x"27", + 2867 => x"f5", + 2868 => x"53", + 2869 => x"89", + 2870 => x"38", + 2871 => x"55", + 2872 => x"8a", + 2873 => x"a0", + 2874 => x"ca", + 2875 => x"74", + 2876 => x"e0", + 2877 => x"ff", + 2878 => x"d0", + 2879 => x"ff", + 2880 => x"90", + 2881 => x"38", + 2882 => x"81", + 2883 => x"53", + 2884 => x"ca", + 2885 => x"27", + 2886 => x"52", + 2887 => x"ed", + 2888 => x"ec", + 2889 => x"08", + 2890 => x"0c", + 2891 => x"33", + 2892 => x"ff", + 2893 => x"80", + 2894 => x"74", + 2895 => x"55", + 2896 => x"81", + 2897 => x"85", + 2898 => x"3d", + 2899 => x"3d", + 2900 => x"2b", + 2901 => x"79", + 2902 => x"98", + 2903 => x"73", + 2904 => x"54", + 2905 => x"51", + 2906 => x"81", + 2907 => x"33", + 2908 => x"74", + 2909 => x"71", + 2910 => x"12", + 2911 => x"88", + 2912 => x"33", + 2913 => x"53", + 2914 => x"72", + 2915 => x"06", + 2916 => x"54", + 2917 => x"82", + 2918 => x"85", + 2919 => x"fc", + 2920 => x"02", + 2921 => x"05", + 2922 => x"54", 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x"fc", + 2982 => x"0d", + 2983 => x"0d", + 2984 => x"53", + 2985 => x"08", + 2986 => x"2e", + 2987 => x"51", + 2988 => x"80", + 2989 => x"14", + 2990 => x"54", + 2991 => x"e6", + 2992 => x"82", + 2993 => x"82", + 2994 => x"52", + 2995 => x"95", + 2996 => x"80", + 2997 => x"82", + 2998 => x"51", + 2999 => x"80", + 3000 => x"c0", + 3001 => x"0d", + 3002 => x"0d", + 3003 => x"52", + 3004 => x"08", + 3005 => x"c8", + 3006 => x"ec", + 3007 => x"38", + 3008 => x"08", + 3009 => x"52", + 3010 => x"52", + 3011 => x"b3", + 3012 => x"ec", + 3013 => x"b9", + 3014 => x"ff", + 3015 => x"82", + 3016 => x"55", + 3017 => x"85", + 3018 => x"9c", + 3019 => x"ec", + 3020 => x"70", + 3021 => x"80", + 3022 => x"53", + 3023 => x"17", + 3024 => x"52", + 3025 => x"3f", + 3026 => x"09", + 3027 => x"b0", + 3028 => x"0d", + 3029 => x"0d", + 3030 => x"ad", + 3031 => x"5a", + 3032 => x"58", + 3033 => x"85", + 3034 => x"80", + 3035 => x"82", + 3036 => x"81", + 3037 => x"0b", + 3038 => x"08", + 3039 => x"f8", + 3040 => x"70", + 3041 => x"86", + 3042 => x"85", + 3043 => x"2e", + 3044 => x"51", + 3045 => x"3f", + 3046 => x"08", + 3047 => x"55", + 3048 => x"85", + 3049 => x"8e", + 3050 => x"ec", + 3051 => x"70", + 3052 => x"80", + 3053 => x"09", + 3054 => x"05", + 3055 => x"9f", + 3056 => x"55", + 3057 => x"85", + 3058 => x"aa", + 3059 => x"c0", + 3060 => x"08", + 3061 => x"dc", + 3062 => x"85", + 3063 => x"2e", + 3064 => x"fd", + 3065 => x"86", + 3066 => x"2e", + 3067 => x"9b", + 3068 => x"79", + 3069 => x"b2", + 3070 => x"ff", + 3071 => x"ab", + 3072 => x"82", + 3073 => x"74", + 3074 => x"77", + 3075 => x"0c", + 3076 => x"04", + 3077 => x"7c", + 3078 => x"71", + 3079 => x"59", + 3080 => x"a0", + 3081 => x"06", + 3082 => x"33", + 3083 => x"77", + 3084 => x"38", + 3085 => x"5b", + 3086 => x"56", + 3087 => x"a0", + 3088 => x"06", + 3089 => x"75", + 3090 => x"80", + 3091 => x"2b", + 3092 => x"11", + 3093 => x"51", + 3094 => x"e0", + 3095 => x"ec", + 3096 => x"52", + 3097 => x"ff", + 3098 => x"82", + 3099 => x"80", + 3100 => x"14", + 3101 => x"81", + 3102 => x"73", + 3103 => x"38", + 3104 => x"e5", + 3105 => x"81", + 3106 => x"3d", + 3107 => x"f8", + 3108 => x"c2", + 3109 => x"ec", + 3110 => x"98", + 3111 => x"53", + 3112 => x"51", + 3113 => x"82", + 3114 => x"81", + 3115 => x"73", + 3116 => x"38", + 3117 => x"81", + 3118 => x"54", + 3119 => x"ff", + 3120 => x"54", + 3121 => x"ec", + 3122 => x"0d", + 3123 => x"0d", + 3124 => x"b2", + 3125 => x"3d", + 3126 => x"5a", + 3127 => x"3d", + 3128 => x"c4", + 3129 => x"c0", + 3130 => x"73", + 3131 => x"73", + 3132 => x"33", + 3133 => x"83", + 3134 => x"76", + 3135 => x"bb", + 3136 => x"76", + 3137 => x"73", + 3138 => x"ac", + 3139 => x"97", + 3140 => x"85", + 3141 => x"85", + 3142 => x"85", + 3143 => x"2e", + 3144 => x"93", + 3145 => x"82", + 3146 => x"51", + 3147 => x"3f", + 3148 => x"08", + 3149 => x"38", + 3150 => x"51", + 3151 => x"80", + 3152 => x"85", + 3153 => x"82", + 3154 => x"53", + 3155 => x"90", + 3156 => x"54", + 3157 => x"3f", + 3158 => x"08", + 3159 => x"ec", + 3160 => x"09", + 3161 => x"d0", + 3162 => x"ec", + 3163 => x"b0", + 3164 => x"85", + 3165 => x"80", + 3166 => x"ec", + 3167 => x"38", + 3168 => x"08", + 3169 => x"17", + 3170 => x"74", + 3171 => x"74", + 3172 => x"52", + 3173 => x"c5", + 3174 => x"70", + 3175 => x"5c", + 3176 => x"27", + 3177 => x"5b", + 3178 => x"09", + 3179 => x"97", + 3180 => x"75", + 3181 => x"34", + 3182 => x"82", + 3183 => x"80", + 3184 => x"f9", + 3185 => x"3d", + 3186 => x"3f", + 3187 => x"08", + 3188 => x"98", + 3189 => x"78", + 3190 => x"38", + 3191 => x"06", + 3192 => x"33", + 3193 => x"70", + 3194 => x"9d", + 3195 => x"98", + 3196 => x"2c", + 3197 => x"05", + 3198 => x"81", + 3199 => x"08", + 3200 => x"51", + 3201 => x"59", + 3202 => x"5d", + 3203 => x"73", + 3204 => x"e3", + 3205 => x"27", + 3206 => x"15", + 3207 => x"70", + 3208 => x"56", + 3209 => x"24", + 3210 => x"76", + 3211 => x"77", + 3212 => x"3f", + 3213 => x"08", + 3214 => x"54", + 3215 => x"da", + 3216 => x"9d", + 3217 => x"56", + 3218 => x"15", + 3219 => x"70", + 3220 => x"81", + 3221 => x"51", + 3222 => x"95", + 3223 => x"76", + 3224 => x"77", + 3225 => x"3f", + 3226 => x"08", + 3227 => x"54", + 3228 => x"d6", + 3229 => x"75", + 3230 => x"ca", + 3231 => x"54", + 3232 => x"84", + 3233 => x"2b", + 3234 => x"82", + 3235 => x"70", + 3236 => x"98", + 3237 => x"71", + 3238 => x"81", + 3239 => x"33", + 3240 => x"51", + 3241 => x"54", + 3242 => x"09", + 3243 => x"99", + 3244 => x"fc", + 3245 => x"0c", + 3246 => x"9d", + 3247 => x"0b", + 3248 => x"34", + 3249 => x"82", + 3250 => x"75", + 3251 => x"34", + 3252 => x"34", + 3253 => x"7e", + 3254 => x"26", + 3255 => x"73", + 3256 => x"81", + 3257 => x"08", + 3258 => x"8c", + 3259 => x"7e", + 3260 => x"38", + 3261 => x"33", + 3262 => x"27", + 3263 => x"98", + 3264 => x"2c", + 3265 => x"75", + 3266 => x"74", + 3267 => x"33", + 3268 => x"ff", + 3269 => x"2b", + 3270 => x"82", + 3271 => x"53", + 3272 => x"74", + 3273 => x"38", + 3274 => x"33", + 3275 => x"54", + 3276 => x"8c", + 3277 => x"54", + 3278 => x"74", + 3279 => x"88", + 3280 => x"7e", + 3281 => x"81", + 3282 => x"82", + 3283 => x"82", + 3284 => x"ff", + 3285 => x"2b", + 3286 => x"82", + 3287 => x"59", + 3288 => x"74", + 3289 => x"38", + 3290 => x"33", + 3291 => x"a1", + 3292 => x"70", + 3293 => x"98", + 3294 => x"88", + 3295 => x"56", + 3296 => x"24", + 3297 => x"9d", + 3298 => x"98", + 3299 => x"2c", + 3300 => x"33", + 3301 => x"54", + 3302 => x"fc", + 3303 => x"51", + 3304 => x"81", + 3305 => x"2b", + 3306 => x"82", + 3307 => x"5a", + 3308 => x"76", + 3309 => x"38", + 3310 => x"83", + 3311 => x"0b", + 3312 => x"82", + 3313 => x"80", + 3314 => x"d8", + 3315 => x"3f", + 3316 => x"82", + 3317 => x"70", + 3318 => x"55", + 3319 => x"2e", + 3320 => x"82", + 3321 => x"ff", + 3322 => x"82", + 3323 => x"ff", + 3324 => x"82", + 3325 => x"88", + 3326 => x"3f", + 3327 => x"33", + 3328 => x"70", + 3329 => x"9d", + 3330 => x"51", + 3331 => x"74", + 3332 => x"74", + 3333 => x"14", + 3334 => x"73", + 3335 => x"f1", + 3336 => x"70", + 3337 => x"98", + 3338 => x"88", + 3339 => x"56", + 3340 => x"24", + 3341 => x"51", + 3342 => x"82", + 3343 => x"70", + 3344 => x"98", + 3345 => x"88", + 3346 => x"56", + 3347 => x"24", + 3348 => x"88", + 3349 => x"3f", + 3350 => x"98", + 3351 => x"2c", + 3352 => x"33", + 3353 => x"54", + 3354 => x"e7", + 3355 => x"39", + 3356 => x"33", + 3357 => x"80", + 3358 => x"51", + 3359 => x"82", + 3360 => x"79", + 3361 => x"3f", + 3362 => x"08", + 3363 => x"54", + 3364 => x"82", + 3365 => x"54", + 3366 => x"8f", + 3367 => x"73", + 3368 => x"f2", + 3369 => x"39", + 3370 => x"80", + 3371 => x"8c", + 3372 => x"82", + 3373 => x"79", + 3374 => x"0c", + 3375 => x"04", + 3376 => x"33", + 3377 => x"2e", + 3378 => x"88", + 3379 => x"3f", + 3380 => x"33", + 3381 => x"73", + 3382 => x"34", + 3383 => x"06", + 3384 => x"82", + 3385 => x"82", + 3386 => x"55", + 3387 => x"2e", + 3388 => x"ff", + 3389 => x"82", + 3390 => x"74", + 3391 => x"98", + 3392 => x"ff", + 3393 => x"55", + 3394 => x"a4", + 3395 => x"54", + 3396 => x"74", + 3397 => x"51", + 3398 => x"81", + 3399 => x"2b", + 3400 => x"82", + 3401 => x"59", + 3402 => x"75", + 3403 => x"38", + 3404 => x"dd", + 3405 => x"8c", + 3406 => x"2b", + 3407 => x"82", + 3408 => x"57", + 3409 => x"74", + 3410 => x"fa", + 3411 => x"e3", + 3412 => x"15", + 3413 => x"70", + 3414 => x"9d", + 3415 => x"51", + 3416 => x"75", + 3417 => x"f8", + 3418 => x"9d", + 3419 => x"81", + 3420 => x"9d", + 3421 => x"56", + 3422 => x"27", + 3423 => x"81", + 3424 => x"82", + 3425 => x"74", + 3426 => x"52", + 3427 => x"3f", + 3428 => x"33", + 3429 => x"06", + 3430 => x"33", + 3431 => x"75", + 3432 => x"38", + 3433 => x"82", + 3434 => x"80", + 3435 => x"d8", + 3436 => x"3f", + 3437 => x"9d", + 3438 => x"0b", + 3439 => x"34", + 3440 => x"7a", + 3441 => x"85", + 3442 => x"74", + 3443 => x"38", + 3444 => x"a7", + 3445 => x"85", + 3446 => x"9d", + 3447 => x"85", + 3448 => x"ff", + 3449 => x"53", + 3450 => x"51", + 3451 => x"3f", + 3452 => x"c0", + 3453 => x"2b", + 3454 => x"11", + 3455 => x"57", + 3456 => x"80", + 3457 => x"74", + 3458 => x"b0", + 3459 => x"ec", + 3460 => x"88", + 3461 => x"ec", + 3462 => x"06", + 3463 => x"74", + 3464 => x"ff", + 3465 => x"ff", + 3466 => x"f9", + 3467 => x"55", + 3468 => x"f7", + 3469 => x"51", + 3470 => x"3f", + 3471 => x"93", + 3472 => x"06", + 3473 => x"84", + 3474 => x"74", + 3475 => x"38", + 3476 => x"a6", + 3477 => x"85", + 3478 => x"9d", + 3479 => x"85", + 3480 => x"ff", + 3481 => x"53", + 3482 => x"51", + 3483 => x"3f", + 3484 => x"7a", + 3485 => x"84", + 3486 => x"56", + 3487 => x"2e", + 3488 => x"51", + 3489 => x"3f", + 3490 => x"08", + 3491 => x"34", + 3492 => x"08", + 3493 => x"81", + 3494 => x"52", + 3495 => x"a7", + 3496 => x"1b", + 3497 => x"ff", + 3498 => x"39", + 3499 => x"88", + 3500 => x"34", + 3501 => x"53", + 3502 => x"33", + 3503 => x"ed", + 3504 => x"82", + 3505 => x"8c", + 3506 => x"ff", + 3507 => x"88", + 3508 => x"54", + 3509 => x"f5", + 3510 => x"14", + 3511 => x"9d", + 3512 => x"1a", + 3513 => x"54", + 3514 => x"f5", + 3515 => x"9d", + 3516 => x"73", + 3517 => x"ce", + 3518 => x"e0", + 3519 => x"9d", + 3520 => x"05", + 3521 => x"9d", + 3522 => x"ba", + 3523 => x"0d", + 3524 => x"0b", + 3525 => x"0c", + 3526 => x"82", + 3527 => x"90", + 3528 => x"52", + 3529 => x"51", + 3530 => x"3f", + 3531 => x"08", + 3532 => x"77", + 3533 => x"57", + 3534 => x"34", + 3535 => x"08", + 3536 => x"15", + 3537 => x"15", + 3538 => x"e4", + 3539 => x"86", + 3540 => x"87", + 3541 => x"85", + 3542 => x"85", + 3543 => x"05", + 3544 => x"07", + 3545 => x"ff", + 3546 => x"2a", + 3547 => x"56", + 3548 => x"34", + 3549 => x"34", + 3550 => x"22", + 3551 => x"82", + 3552 => x"11", + 3553 => x"55", + 3554 => x"15", + 3555 => x"15", + 3556 => x"0d", + 3557 => x"0d", + 3558 => x"51", + 3559 => x"8f", + 3560 => x"83", + 3561 => x"70", + 3562 => x"06", + 3563 => x"70", + 3564 => x"0c", + 3565 => x"04", + 3566 => x"02", + 3567 => x"02", + 3568 => x"05", + 3569 => x"82", + 3570 => x"71", + 3571 => x"11", + 3572 => x"73", + 3573 => x"81", + 3574 => x"88", + 3575 => x"a4", + 3576 => x"22", + 3577 => x"ff", + 3578 => x"88", + 3579 => x"52", + 3580 => x"5b", + 3581 => x"55", + 3582 => x"70", + 3583 => x"82", + 3584 => x"14", + 3585 => x"52", + 3586 => x"15", + 3587 => x"15", + 3588 => x"e4", + 3589 => x"70", + 3590 => x"33", + 3591 => x"07", + 3592 => x"8f", + 3593 => x"51", + 3594 => x"71", + 3595 => x"ff", + 3596 => x"88", + 3597 => x"51", + 3598 => x"34", + 3599 => x"06", + 3600 => x"12", + 3601 => x"e4", + 3602 => x"71", + 3603 => x"81", + 3604 => x"3d", + 3605 => x"3d", + 3606 => x"e4", + 3607 => x"05", + 3608 => x"70", + 3609 => x"11", + 3610 => x"87", + 3611 => x"8b", + 3612 => x"2b", + 3613 => x"59", + 3614 => x"72", + 3615 => x"33", + 3616 => x"71", + 3617 => x"70", + 3618 => x"56", + 3619 => x"84", + 3620 => x"85", + 3621 => x"85", + 3622 => x"14", + 3623 => x"85", + 3624 => x"8b", + 3625 => x"2b", + 3626 => x"57", + 3627 => x"86", + 3628 => x"13", + 3629 => x"2b", + 3630 => x"2a", + 3631 => x"52", + 3632 => x"34", + 3633 => x"34", + 3634 => x"08", + 3635 => x"81", + 3636 => x"88", + 3637 => x"81", + 3638 => x"70", + 3639 => x"51", + 3640 => x"71", + 3641 => x"81", + 3642 => x"3d", + 3643 => x"3d", + 3644 => x"05", + 3645 => x"e4", + 3646 => x"2b", + 3647 => x"33", + 3648 => x"71", + 3649 => x"70", + 3650 => x"59", + 3651 => x"73", + 3652 => x"81", + 3653 => x"98", + 3654 => x"2b", + 3655 => x"55", + 3656 => x"80", + 3657 => x"38", + 3658 => x"aa", + 3659 => x"e4", + 3660 => x"70", + 3661 => x"33", + 3662 => x"71", + 3663 => x"74", + 3664 => x"81", + 3665 => x"88", + 3666 => x"83", + 3667 => x"f8", + 3668 => x"5d", + 3669 => x"5a", + 3670 => x"75", + 3671 => x"52", + 3672 => x"34", + 3673 => x"34", + 3674 => x"08", + 3675 => x"33", + 3676 => x"71", + 3677 => x"83", + 3678 => x"59", + 3679 => x"05", + 3680 => x"12", + 3681 => x"2b", + 3682 => x"ff", + 3683 => x"88", + 3684 => x"52", + 3685 => x"74", + 3686 => x"15", + 3687 => x"0d", + 3688 => x"0d", + 3689 => x"08", + 3690 => x"9e", + 3691 => x"83", + 3692 => x"82", + 3693 => x"12", + 3694 => x"2b", + 3695 => x"07", + 3696 => x"52", + 3697 => x"05", + 3698 => x"13", + 3699 => x"2b", + 3700 => x"05", + 3701 => x"71", + 3702 => x"2a", + 3703 => x"53", + 3704 => x"34", + 3705 => x"34", + 3706 => x"08", + 3707 => x"33", + 3708 => x"71", + 3709 => x"83", + 3710 => x"59", + 3711 => x"05", + 3712 => x"83", + 3713 => x"88", + 3714 => x"88", + 3715 => x"56", + 3716 => x"13", + 3717 => x"13", + 3718 => x"e4", + 3719 => x"11", + 3720 => x"33", + 3721 => x"07", + 3722 => x"0c", + 3723 => x"3d", + 3724 => x"3d", + 3725 => x"85", + 3726 => x"83", + 3727 => x"ff", + 3728 => x"53", + 3729 => x"a6", + 3730 => x"e4", + 3731 => x"2b", + 3732 => x"11", + 3733 => x"33", + 3734 => x"71", + 3735 => x"75", + 3736 => x"81", + 3737 => x"98", + 3738 => x"2b", + 3739 => x"40", + 3740 => x"58", + 3741 => x"72", + 3742 => x"38", + 3743 => x"52", + 3744 => x"9d", + 3745 => x"39", + 3746 => x"85", + 3747 => x"8b", + 3748 => x"2b", + 3749 => x"79", + 3750 => x"51", + 3751 => x"76", + 3752 => x"75", + 3753 => x"56", + 3754 => x"34", + 3755 => x"08", + 3756 => x"12", + 3757 => x"33", + 3758 => x"07", + 3759 => x"54", + 3760 => x"53", + 3761 => x"34", + 3762 => x"34", + 3763 => x"08", + 3764 => x"0b", + 3765 => x"80", + 3766 => x"34", + 3767 => x"08", + 3768 => x"14", + 3769 => x"14", + 3770 => x"e4", + 3771 => x"33", + 3772 => x"71", + 3773 => x"70", + 3774 => x"07", + 3775 => x"53", + 3776 => x"54", + 3777 => x"72", + 3778 => x"8b", + 3779 => x"ff", + 3780 => x"52", + 3781 => x"08", + 3782 => x"f1", + 3783 => x"2e", + 3784 => x"51", + 3785 => x"83", + 3786 => x"f5", + 3787 => x"7e", + 3788 => x"e1", + 3789 => x"ec", + 3790 => x"ff", + 3791 => x"e4", + 3792 => x"33", + 3793 => x"71", + 3794 => x"70", + 3795 => x"58", + 3796 => x"ff", + 3797 => x"2e", + 3798 => x"75", + 3799 => x"05", + 3800 => x"12", + 3801 => x"2b", + 3802 => x"ff", + 3803 => x"31", + 3804 => x"ff", + 3805 => x"27", + 3806 => x"56", + 3807 => x"79", + 3808 => x"73", + 3809 => x"38", + 3810 => x"5b", + 3811 => x"85", + 3812 => x"88", + 3813 => x"54", + 3814 => x"78", + 3815 => x"2e", + 3816 => x"79", + 3817 => x"76", + 3818 => x"85", + 3819 => x"70", + 3820 => x"33", + 3821 => x"07", + 3822 => x"ff", + 3823 => x"5a", + 3824 => x"73", + 3825 => x"38", + 3826 => x"54", + 3827 => x"81", + 3828 => x"54", + 3829 => x"81", + 3830 => x"7a", + 3831 => x"06", + 3832 => x"51", + 3833 => x"81", + 3834 => x"80", + 3835 => x"52", + 3836 => x"c4", + 3837 => x"e4", + 3838 => x"86", + 3839 => x"12", + 3840 => x"2b", + 3841 => x"07", + 3842 => x"55", + 3843 => x"17", + 3844 => x"ff", + 3845 => x"2a", + 3846 => x"54", + 3847 => x"34", + 3848 => x"06", + 3849 => x"15", + 3850 => x"e4", + 3851 => x"2b", + 3852 => x"1e", + 3853 => x"87", + 3854 => x"88", + 3855 => x"88", + 3856 => x"5e", + 3857 => x"54", + 3858 => x"34", + 3859 => x"34", + 3860 => x"08", + 3861 => x"11", + 3862 => x"33", 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x"52", + 3922 => x"87", + 3923 => x"08", + 3924 => x"2e", + 3925 => x"82", + 3926 => x"34", + 3927 => x"13", + 3928 => x"82", + 3929 => x"86", + 3930 => x"f3", + 3931 => x"62", + 3932 => x"05", + 3933 => x"57", + 3934 => x"83", + 3935 => x"fe", + 3936 => x"85", + 3937 => x"06", + 3938 => x"71", + 3939 => x"71", + 3940 => x"2b", + 3941 => x"80", + 3942 => x"92", + 3943 => x"c0", + 3944 => x"41", + 3945 => x"5a", + 3946 => x"87", + 3947 => x"0c", + 3948 => x"84", + 3949 => x"08", + 3950 => x"70", + 3951 => x"53", + 3952 => x"2e", + 3953 => x"08", + 3954 => x"70", + 3955 => x"34", + 3956 => x"80", + 3957 => x"53", + 3958 => x"2e", + 3959 => x"53", + 3960 => x"26", + 3961 => x"80", + 3962 => x"87", + 3963 => x"08", + 3964 => x"38", + 3965 => x"8c", + 3966 => x"80", + 3967 => x"78", + 3968 => x"99", + 3969 => x"0c", + 3970 => x"8c", + 3971 => x"08", + 3972 => x"51", + 3973 => x"38", + 3974 => x"8d", + 3975 => x"17", + 3976 => x"81", + 3977 => x"53", + 3978 => x"2e", + 3979 => x"fc", + 3980 => x"52", + 3981 => x"7d", + 3982 => x"ed", + 3983 => x"80", + 3984 => x"71", + 3985 => x"38", + 3986 => x"53", + 3987 => x"ec", + 3988 => x"0d", + 3989 => x"0d", + 3990 => x"02", + 3991 => x"05", + 3992 => x"58", + 3993 => x"80", + 3994 => x"fc", + 3995 => x"85", + 3996 => x"06", + 3997 => x"71", + 3998 => x"81", + 3999 => x"38", + 4000 => x"2b", + 4001 => x"80", + 4002 => x"92", + 4003 => x"c0", + 4004 => x"40", + 4005 => x"5a", + 4006 => x"c0", + 4007 => x"76", + 4008 => x"76", + 4009 => x"75", + 4010 => x"2a", + 4011 => x"51", + 4012 => x"80", + 4013 => x"7a", + 4014 => x"5c", + 4015 => x"81", + 4016 => x"81", + 4017 => x"06", + 4018 => x"80", + 4019 => x"87", + 4020 => x"08", + 4021 => x"38", + 4022 => x"8c", + 4023 => x"80", + 4024 => x"77", + 4025 => x"99", + 4026 => x"0c", + 4027 => x"8c", + 4028 => x"08", + 4029 => x"51", + 4030 => x"38", + 4031 => x"8d", + 4032 => x"70", + 4033 => x"84", + 4034 => x"5b", + 4035 => x"2e", + 4036 => x"fc", + 4037 => x"52", + 4038 => x"7d", + 4039 => x"f8", + 4040 => x"80", + 4041 => x"71", + 4042 => x"38", + 4043 => x"53", + 4044 => x"ec", + 4045 => x"0d", + 4046 => x"0d", + 4047 => x"05", + 4048 => x"02", + 4049 => x"05", + 4050 => x"54", + 4051 => x"fe", + 4052 => x"ec", + 4053 => x"53", + 4054 => x"80", + 4055 => x"0b", + 4056 => x"8c", + 4057 => x"71", + 4058 => x"dc", + 4059 => x"24", + 4060 => x"84", + 4061 => x"92", + 4062 => x"54", + 4063 => x"8d", + 4064 => x"39", + 4065 => x"80", + 4066 => x"cb", + 4067 => x"70", + 4068 => x"81", + 4069 => x"52", + 4070 => x"8a", + 4071 => x"98", + 4072 => x"71", + 4073 => x"c0", + 4074 => x"52", + 4075 => x"81", + 4076 => x"c0", + 4077 => x"53", + 4078 => x"82", + 4079 => x"71", + 4080 => x"39", + 4081 => x"39", + 4082 => x"77", + 4083 => x"81", + 4084 => x"72", + 4085 => x"84", + 4086 => x"73", + 4087 => x"0c", + 4088 => x"04", + 4089 => x"74", + 4090 => x"71", + 4091 => x"2b", + 4092 => x"ec", + 4093 => x"84", + 4094 => x"fd", + 4095 => x"83", + 4096 => x"12", + 4097 => x"2b", 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x"33", + 4157 => x"38", + 4158 => x"85", + 4159 => x"3d", + 4160 => x"0b", + 4161 => x"0c", + 4162 => x"82", + 4163 => x"04", + 4164 => x"7b", + 4165 => x"83", + 4166 => x"5a", + 4167 => x"80", + 4168 => x"54", + 4169 => x"53", + 4170 => x"53", + 4171 => x"52", + 4172 => x"3f", + 4173 => x"08", + 4174 => x"81", + 4175 => x"82", + 4176 => x"83", + 4177 => x"16", + 4178 => x"18", + 4179 => x"18", + 4180 => x"58", + 4181 => x"9f", + 4182 => x"33", + 4183 => x"2e", + 4184 => x"93", + 4185 => x"76", + 4186 => x"52", + 4187 => x"51", + 4188 => x"83", + 4189 => x"79", + 4190 => x"0c", + 4191 => x"04", + 4192 => x"78", + 4193 => x"80", + 4194 => x"17", + 4195 => x"38", + 4196 => x"fc", + 4197 => x"ec", + 4198 => x"85", + 4199 => x"38", + 4200 => x"53", + 4201 => x"81", + 4202 => x"f7", + 4203 => x"85", + 4204 => x"2e", + 4205 => x"55", + 4206 => x"b0", + 4207 => x"82", + 4208 => x"88", + 4209 => x"f8", + 4210 => x"70", + 4211 => x"c0", + 4212 => x"ec", + 4213 => x"85", + 4214 => x"91", + 4215 => x"55", + 4216 => x"09", + 4217 => x"f0", + 4218 => x"33", + 4219 => x"2e", + 4220 => x"80", + 4221 => x"80", + 4222 => x"ec", + 4223 => x"17", + 4224 => x"fd", + 4225 => x"d4", + 4226 => x"b2", + 4227 => x"96", + 4228 => x"85", + 4229 => x"75", + 4230 => x"3f", + 4231 => x"e4", + 4232 => x"98", + 4233 => x"9c", + 4234 => x"08", + 4235 => x"17", + 4236 => x"3f", + 4237 => x"52", + 4238 => x"51", + 4239 => x"a0", + 4240 => x"05", + 4241 => x"0c", + 4242 => x"75", + 4243 => x"33", + 4244 => x"3f", + 4245 => x"34", + 4246 => x"52", + 4247 => x"51", + 4248 => x"82", + 4249 => x"80", + 4250 => x"81", + 4251 => x"85", + 4252 => x"3d", + 4253 => x"3d", + 4254 => x"1a", + 4255 => x"fe", + 4256 => x"55", + 4257 => x"73", + 4258 => x"8a", + 4259 => x"53", + 4260 => x"f9", + 4261 => x"08", + 4262 => x"08", + 4263 => x"82", + 4264 => x"87", + 4265 => x"f9", + 4266 => x"7a", + 4267 => x"54", + 4268 => x"27", + 4269 => x"76", + 4270 => x"27", + 4271 => x"ff", + 4272 => x"58", + 4273 => x"80", + 4274 => x"82", + 4275 => x"72", + 4276 => x"38", + 4277 => x"72", + 4278 => x"8e", + 4279 => x"39", + 4280 => x"17", + 4281 => x"a4", + 4282 => x"53", + 4283 => x"fd", + 4284 => x"85", + 4285 => x"9f", + 4286 => x"ff", + 4287 => x"11", + 4288 => x"70", + 4289 => x"18", + 4290 => x"76", + 4291 => x"53", + 4292 => x"82", + 4293 => x"80", + 4294 => x"83", + 4295 => x"b4", + 4296 => x"88", + 4297 => x"79", + 4298 => x"84", + 4299 => x"58", + 4300 => x"80", + 4301 => x"9f", + 4302 => x"80", + 4303 => x"88", + 4304 => x"08", + 4305 => x"51", + 4306 => x"82", + 4307 => x"80", + 4308 => x"10", + 4309 => x"74", + 4310 => x"51", + 4311 => x"82", + 4312 => x"83", + 4313 => x"58", + 4314 => x"87", + 4315 => x"08", + 4316 => x"51", + 4317 => x"82", + 4318 => x"9b", + 4319 => x"2b", + 4320 => x"74", + 4321 => x"51", + 4322 => x"82", + 4323 => x"f0", + 4324 => x"83", + 4325 => x"77", + 4326 => x"0c", + 4327 => x"04", + 4328 => x"7a", + 4329 => x"58", + 4330 => x"81", + 4331 => x"9e", + 4332 => x"17", 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x"85", + 4392 => x"38", + 4393 => x"06", + 4394 => x"83", + 4395 => x"18", + 4396 => x"54", + 4397 => x"f6", + 4398 => x"85", + 4399 => x"0a", + 4400 => x"52", + 4401 => x"fc", + 4402 => x"83", + 4403 => x"82", + 4404 => x"8a", + 4405 => x"f8", + 4406 => x"7c", + 4407 => x"59", + 4408 => x"81", + 4409 => x"38", + 4410 => x"08", + 4411 => x"73", + 4412 => x"38", + 4413 => x"52", + 4414 => x"a4", + 4415 => x"ec", + 4416 => x"85", + 4417 => x"f2", + 4418 => x"82", + 4419 => x"39", + 4420 => x"e6", + 4421 => x"ec", + 4422 => x"de", + 4423 => x"78", + 4424 => x"3f", + 4425 => x"08", + 4426 => x"ec", + 4427 => x"80", + 4428 => x"85", + 4429 => x"2e", + 4430 => x"85", + 4431 => x"2e", + 4432 => x"53", + 4433 => x"51", + 4434 => x"82", + 4435 => x"c5", + 4436 => x"08", + 4437 => x"18", + 4438 => x"57", + 4439 => x"90", + 4440 => x"90", + 4441 => x"16", + 4442 => x"54", + 4443 => x"34", + 4444 => x"78", + 4445 => x"38", + 4446 => x"82", + 4447 => x"8a", + 4448 => x"f6", + 4449 => x"7e", + 4450 => x"5b", + 4451 => x"38", + 4452 => x"58", + 4453 => x"88", + 4454 => x"08", + 4455 => x"38", + 4456 => x"39", + 4457 => x"51", + 4458 => x"81", + 4459 => x"85", + 4460 => x"82", + 4461 => x"85", + 4462 => x"82", + 4463 => x"ff", + 4464 => x"38", + 4465 => x"82", + 4466 => x"26", + 4467 => x"79", + 4468 => x"08", + 4469 => x"73", + 4470 => x"bf", + 4471 => x"2e", + 4472 => x"80", + 4473 => x"1a", + 4474 => x"08", + 4475 => x"38", + 4476 => x"52", + 4477 => x"af", + 4478 => x"82", + 4479 => x"81", + 4480 => x"06", + 4481 => x"85", + 4482 => x"82", + 4483 => x"09", + 4484 => x"05", + 4485 => x"80", + 4486 => x"07", + 4487 => x"08", + 4488 => x"55", + 4489 => x"f3", + 4490 => x"ec", + 4491 => x"95", + 4492 => x"08", + 4493 => x"27", + 4494 => x"98", + 4495 => x"89", + 4496 => x"85", + 4497 => x"dd", + 4498 => x"81", + 4499 => x"17", + 4500 => x"89", + 4501 => x"75", + 4502 => x"b0", + 4503 => x"7a", + 4504 => x"3f", + 4505 => x"08", + 4506 => x"38", + 4507 => x"85", + 4508 => x"2e", + 4509 => x"86", + 4510 => x"ec", + 4511 => x"85", + 4512 => x"70", + 4513 => x"70", + 4514 => x"25", + 4515 => x"51", + 4516 => x"73", + 4517 => x"75", + 4518 => x"81", + 4519 => x"38", + 4520 => x"f7", + 4521 => x"75", + 4522 => x"f9", + 4523 => x"85", + 4524 => x"85", + 4525 => x"81", + 4526 => x"85", + 4527 => x"80", + 4528 => x"55", + 4529 => x"94", + 4530 => x"2e", + 4531 => x"53", + 4532 => x"51", + 4533 => x"82", + 4534 => x"55", + 4535 => x"75", + 4536 => x"98", + 4537 => x"05", + 4538 => x"56", + 4539 => x"26", + 4540 => x"15", + 4541 => x"84", + 4542 => x"07", + 4543 => x"18", + 4544 => x"ff", + 4545 => x"2e", + 4546 => x"39", + 4547 => x"39", + 4548 => x"08", + 4549 => x"81", + 4550 => x"74", + 4551 => x"0c", + 4552 => x"04", + 4553 => x"7a", + 4554 => x"f3", + 4555 => x"85", + 4556 => x"81", + 4557 => x"ec", + 4558 => x"38", + 4559 => x"51", + 4560 => x"82", + 4561 => x"82", + 4562 => x"b0", + 4563 => x"84", + 4564 => x"52", + 4565 => x"52", + 4566 => x"3f", + 4567 => x"39", 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x"94", + 4627 => x"2a", + 4628 => x"0c", + 4629 => x"06", + 4630 => x"9c", + 4631 => x"58", + 4632 => x"ec", + 4633 => x"0d", + 4634 => x"0d", + 4635 => x"90", + 4636 => x"05", + 4637 => x"f0", + 4638 => x"27", + 4639 => x"0b", + 4640 => x"98", + 4641 => x"84", + 4642 => x"2e", + 4643 => x"76", + 4644 => x"58", + 4645 => x"38", + 4646 => x"15", + 4647 => x"08", + 4648 => x"38", + 4649 => x"88", + 4650 => x"53", + 4651 => x"81", + 4652 => x"c0", + 4653 => x"22", + 4654 => x"89", + 4655 => x"72", + 4656 => x"74", + 4657 => x"f3", + 4658 => x"85", + 4659 => x"82", + 4660 => x"82", + 4661 => x"27", + 4662 => x"81", + 4663 => x"ec", + 4664 => x"80", + 4665 => x"16", + 4666 => x"ec", + 4667 => x"ca", + 4668 => x"38", + 4669 => x"0c", + 4670 => x"dd", + 4671 => x"08", + 4672 => x"f8", + 4673 => x"85", + 4674 => x"87", + 4675 => x"ec", + 4676 => x"80", + 4677 => x"55", + 4678 => x"08", + 4679 => x"38", + 4680 => x"85", + 4681 => x"2e", + 4682 => x"85", + 4683 => x"75", + 4684 => x"3f", + 4685 => x"08", + 4686 => x"94", + 4687 => x"52", + 4688 => x"b2", + 4689 => x"ec", + 4690 => x"0c", + 4691 => x"0c", + 4692 => x"05", + 4693 => x"80", + 4694 => x"85", + 4695 => x"3d", + 4696 => x"3d", + 4697 => x"71", + 4698 => x"57", + 4699 => x"51", + 4700 => x"82", + 4701 => x"54", + 4702 => x"08", + 4703 => x"82", + 4704 => x"56", + 4705 => x"52", + 4706 => x"f4", + 4707 => x"ec", + 4708 => x"85", + 4709 => x"d2", + 4710 => x"ec", + 4711 => x"08", + 4712 => x"54", + 4713 => x"e5", + 4714 => x"06", + 4715 => x"58", + 4716 => x"08", + 4717 => x"38", + 4718 => x"75", + 4719 => x"80", + 4720 => x"81", + 4721 => x"7a", + 4722 => x"06", + 4723 => x"39", + 4724 => x"08", + 4725 => x"76", + 4726 => x"3f", + 4727 => x"08", + 4728 => x"ec", + 4729 => x"ff", + 4730 => x"84", + 4731 => x"06", + 4732 => x"54", + 4733 => x"ec", + 4734 => x"0d", + 4735 => x"0d", + 4736 => x"52", + 4737 => x"3f", + 4738 => x"08", + 4739 => x"06", + 4740 => x"51", + 4741 => x"83", + 4742 => x"06", + 4743 => x"14", + 4744 => x"3f", + 4745 => x"08", + 4746 => x"07", + 4747 => x"85", + 4748 => x"3d", + 4749 => x"3d", + 4750 => x"70", + 4751 => x"06", + 4752 => x"53", + 4753 => x"de", + 4754 => x"33", + 4755 => x"83", + 4756 => x"06", + 4757 => x"90", + 4758 => x"15", + 4759 => x"3f", + 4760 => x"04", + 4761 => x"7b", + 4762 => x"84", + 4763 => x"58", + 4764 => x"80", + 4765 => x"38", + 4766 => x"52", + 4767 => x"80", + 4768 => x"ec", + 4769 => x"85", + 4770 => x"f5", + 4771 => x"08", + 4772 => x"53", + 4773 => x"84", + 4774 => x"39", + 4775 => x"70", + 4776 => x"81", + 4777 => x"51", + 4778 => x"16", + 4779 => x"ec", + 4780 => x"81", + 4781 => x"38", + 4782 => x"ae", + 4783 => x"81", + 4784 => x"54", + 4785 => x"2e", + 4786 => x"8f", + 4787 => x"82", + 4788 => x"76", + 4789 => x"54", + 4790 => x"09", + 4791 => x"38", + 4792 => x"7a", + 4793 => x"80", + 4794 => x"fa", + 4795 => x"85", + 4796 => x"82", + 4797 => x"89", + 4798 => x"08", + 4799 => x"86", + 4800 => x"98", + 4801 => x"82", + 4802 => x"8b", + 4803 => x"fb", + 4804 => x"70", + 4805 => x"81", + 4806 => x"fc", + 4807 => x"85", + 4808 => x"82", + 4809 => x"b4", + 4810 => x"08", + 4811 => x"ec", + 4812 => x"85", + 4813 => x"82", + 4814 => x"a0", + 4815 => x"82", + 4816 => x"52", + 4817 => x"51", + 4818 => x"8b", + 4819 => x"52", + 4820 => x"51", + 4821 => x"81", + 4822 => x"34", + 4823 => x"ec", + 4824 => x"0d", + 4825 => x"0d", + 4826 => x"98", + 4827 => x"70", + 4828 => x"ec", + 4829 => x"85", + 4830 => x"38", + 4831 => x"53", + 4832 => x"81", + 4833 => x"34", + 4834 => x"04", + 4835 => x"78", + 4836 => x"80", + 4837 => x"34", + 4838 => x"80", + 4839 => x"38", + 4840 => x"18", + 4841 => x"9c", + 4842 => x"70", + 4843 => x"56", + 4844 => x"a0", + 4845 => x"71", + 4846 => x"81", + 4847 => x"81", + 4848 => x"89", + 4849 => x"06", + 4850 => x"73", + 4851 => x"55", + 4852 => x"55", + 4853 => x"81", + 4854 => x"81", + 4855 => x"74", + 4856 => x"75", + 4857 => x"52", + 4858 => x"13", + 4859 => x"08", + 4860 => x"33", + 4861 => x"9c", + 4862 => x"11", + 4863 => x"fb", + 4864 => x"ec", + 4865 => x"96", + 4866 => x"d8", + 4867 => x"ec", + 4868 => x"23", + 4869 => x"e7", + 4870 => x"85", + 4871 => x"17", + 4872 => x"0d", + 4873 => x"0d", + 4874 => x"5e", + 4875 => x"70", + 4876 => x"55", + 4877 => x"83", + 4878 => x"73", + 4879 => x"91", + 4880 => x"2e", + 4881 => x"1d", + 4882 => x"0c", + 4883 => x"15", + 4884 => x"70", + 4885 => x"56", + 4886 => x"09", + 4887 => x"38", + 4888 => x"80", + 4889 => x"09", + 4890 => x"80", + 4891 => x"51", + 4892 => x"da", + 4893 => x"1c", + 4894 => x"33", + 4895 => x"9f", + 4896 => x"ff", + 4897 => x"1c", + 4898 => x"7a", + 4899 => x"3f", + 4900 => x"08", + 4901 => x"39", + 4902 => x"a0", + 4903 => x"5e", + 4904 => x"52", + 4905 => x"ee", + 4906 => x"59", + 4907 => x"33", + 4908 => x"ae", + 4909 => x"06", + 4910 => x"78", + 4911 => x"81", + 4912 => x"32", + 4913 => x"05", + 4914 => x"73", + 4915 => x"51", + 4916 => x"57", + 4917 => x"38", + 4918 => x"75", + 4919 => x"17", + 4920 => x"75", + 4921 => x"09", + 4922 => x"9f", + 4923 => x"54", + 4924 => x"2e", + 4925 => x"80", + 4926 => x"75", + 4927 => x"c7", + 4928 => x"7e", + 4929 => x"a0", + 4930 => x"c7", + 4931 => x"82", + 4932 => x"18", + 4933 => x"1a", + 4934 => x"a0", + 4935 => x"86", + 4936 => x"32", + 4937 => x"05", + 4938 => x"32", + 4939 => x"05", + 4940 => x"71", + 4941 => x"51", + 4942 => x"55", + 4943 => x"ae", + 4944 => x"81", + 4945 => x"78", + 4946 => x"51", + 4947 => x"af", + 4948 => x"06", + 4949 => x"55", + 4950 => x"32", + 4951 => x"05", + 4952 => x"77", + 4953 => x"54", + 4954 => x"81", + 4955 => x"ae", + 4956 => x"06", + 4957 => x"54", + 4958 => x"74", + 4959 => x"80", + 4960 => x"7b", + 4961 => x"09", + 4962 => x"ae", + 4963 => x"81", + 4964 => x"25", + 4965 => x"07", + 4966 => x"51", + 4967 => x"a7", + 4968 => x"8b", + 4969 => x"39", + 4970 => x"54", + 4971 => x"8c", + 4972 => x"ff", + 4973 => x"b4", + 4974 => x"54", + 4975 => x"c2", + 4976 => x"ec", + 4977 => x"b2", + 4978 => x"70", + 4979 => x"71", + 4980 => x"54", + 4981 => x"82", + 4982 => x"80", + 4983 => x"38", + 4984 => x"76", + 4985 => x"df", + 4986 => x"54", + 4987 => x"81", + 4988 => x"55", + 4989 => x"34", + 4990 => x"52", + 4991 => x"51", + 4992 => x"82", + 4993 => x"bf", + 4994 => x"16", + 4995 => x"26", + 4996 => x"16", + 4997 => x"06", + 4998 => x"17", + 4999 => x"34", + 5000 => x"fd", + 5001 => x"19", + 5002 => x"80", + 5003 => x"79", + 5004 => x"81", + 5005 => x"81", + 5006 => x"85", + 5007 => x"54", + 5008 => x"8f", + 5009 => x"86", + 5010 => x"39", + 5011 => x"f3", + 5012 => x"73", + 5013 => x"80", + 5014 => x"52", + 5015 => x"be", + 5016 => x"ec", + 5017 => x"85", + 5018 => x"d7", + 5019 => x"08", + 5020 => x"e6", + 5021 => x"85", + 5022 => x"82", + 5023 => x"80", + 5024 => x"1b", + 5025 => x"55", + 5026 => x"2e", + 5027 => x"8b", + 5028 => x"06", + 5029 => x"1c", + 5030 => x"33", + 5031 => x"70", + 5032 => x"55", + 5033 => x"38", + 5034 => x"52", + 5035 => x"80", + 5036 => x"ec", + 5037 => x"8b", + 5038 => x"7a", + 5039 => x"3f", + 5040 => x"75", + 5041 => x"57", + 5042 => x"2e", + 5043 => x"84", + 5044 => x"06", + 5045 => x"75", + 5046 => x"81", + 5047 => x"2a", + 5048 => x"73", + 5049 => x"38", + 5050 => x"54", + 5051 => x"fb", + 5052 => x"80", + 5053 => x"34", + 5054 => x"c1", + 5055 => x"06", + 5056 => x"38", + 5057 => x"39", + 5058 => x"70", + 5059 => x"54", + 5060 => x"86", + 5061 => x"84", + 5062 => x"06", + 5063 => x"73", + 5064 => x"38", + 5065 => x"83", + 5066 => x"b4", + 5067 => x"51", + 5068 => x"82", + 5069 => x"88", + 5070 => x"dc", + 5071 => x"85", + 5072 => x"3d", + 5073 => x"3d", + 5074 => x"ff", + 5075 => x"71", + 5076 => x"5c", + 5077 => x"80", + 5078 => x"38", + 5079 => x"05", + 5080 => x"a0", + 5081 => x"71", + 5082 => x"38", + 5083 => x"71", + 5084 => x"81", + 5085 => x"38", + 5086 => x"11", + 5087 => x"06", + 5088 => x"70", + 5089 => x"38", + 5090 => x"81", + 5091 => x"05", + 5092 => x"76", + 5093 => x"38", + 5094 => x"ff", + 5095 => x"77", + 5096 => x"57", + 5097 => x"05", + 5098 => x"70", + 5099 => x"33", + 5100 => x"53", + 5101 => x"99", + 5102 => x"e0", + 5103 => x"ff", + 5104 => x"ff", + 5105 => x"70", + 5106 => x"38", + 5107 => x"81", + 5108 => x"51", + 5109 => x"05", + 5110 => x"51", + 5111 => x"2e", + 5112 => x"85", + 5113 => x"bc", + 5114 => x"81", + 5115 => x"32", + 5116 => x"05", + 5117 => x"9f", + 5118 => x"2a", + 5119 => x"54", + 5120 => x"2e", + 5121 => x"15", + 5122 => x"55", + 5123 => x"ff", + 5124 => x"39", + 5125 => x"86", + 5126 => x"7c", + 5127 => x"51", + 5128 => x"9d", + 5129 => x"70", + 5130 => x"0c", + 5131 => x"04", + 5132 => x"78", + 5133 => x"83", + 5134 => x"0b", + 5135 => x"79", + 5136 => x"e2", + 5137 => x"55", + 5138 => x"08", + 5139 => x"84", + 5140 => x"df", + 5141 => x"85", + 5142 => x"ff", + 5143 => x"83", + 5144 => x"d4", + 5145 => x"81", + 5146 => x"38", + 5147 => x"17", + 5148 => x"74", + 5149 => x"09", + 5150 => x"38", + 5151 => x"81", + 5152 => x"09", + 5153 => x"80", + 5154 => x"51", + 5155 => x"8a", + 5156 => x"e8", + 5157 => x"06", + 5158 => x"53", + 5159 => x"52", + 5160 => x"51", + 5161 => x"82", + 5162 => x"55", + 5163 => x"08", + 5164 => x"38", + 5165 => x"fe", + 5166 => x"86", + 5167 => x"f0", + 5168 => x"ec", + 5169 => x"85", + 5170 => x"2e", + 5171 => x"55", + 5172 => x"ec", + 5173 => x"0d", + 5174 => x"0d", + 5175 => x"05", + 5176 => x"33", + 5177 => x"75", + 5178 => x"fc", + 5179 => x"85", + 5180 => x"8b", + 5181 => x"82", + 5182 => x"24", + 5183 => x"82", + 5184 => x"82", + 5185 => x"90", + 5186 => x"53", + 5187 => x"80", + 5188 => x"38", + 5189 => x"76", + 5190 => x"74", + 5191 => x"72", + 5192 => x"38", + 5193 => x"51", + 5194 => x"82", + 5195 => x"81", + 5196 => x"81", + 5197 => x"72", + 5198 => x"80", + 5199 => x"38", + 5200 => x"70", + 5201 => x"53", + 5202 => x"86", + 5203 => x"af", + 5204 => x"34", + 5205 => x"34", + 5206 => x"14", + 5207 => x"8c", + 5208 => x"ec", + 5209 => x"06", + 5210 => x"54", + 5211 => x"72", + 5212 => x"76", + 5213 => x"38", + 5214 => x"70", + 5215 => x"53", + 5216 => x"85", + 5217 => x"70", + 5218 => x"5c", + 5219 => x"82", + 5220 => x"81", + 5221 => x"76", + 5222 => x"81", + 5223 => x"38", + 5224 => x"56", + 5225 => x"83", + 5226 => x"70", + 5227 => x"80", + 5228 => x"83", + 5229 => x"dc", + 5230 => x"85", + 5231 => x"76", + 5232 => x"05", + 5233 => x"16", + 5234 => x"56", + 5235 => x"d7", + 5236 => x"8e", + 5237 => x"72", + 5238 => x"54", + 5239 => x"57", + 5240 => x"95", + 5241 => x"73", + 5242 => x"3f", + 5243 => x"08", + 5244 => x"57", + 5245 => x"89", + 5246 => x"56", + 5247 => x"d7", + 5248 => x"76", + 5249 => x"f9", + 5250 => x"76", + 5251 => x"f1", + 5252 => x"51", + 5253 => x"82", + 5254 => x"83", + 5255 => x"53", + 5256 => x"2e", + 5257 => x"84", + 5258 => x"ca", + 5259 => x"b4", + 5260 => x"ec", + 5261 => x"ff", + 5262 => x"8d", + 5263 => x"14", + 5264 => x"3f", + 5265 => x"08", + 5266 => x"15", + 5267 => x"14", + 5268 => x"34", + 5269 => x"33", + 5270 => x"81", + 5271 => x"54", + 5272 => x"72", + 5273 => x"99", + 5274 => x"ff", + 5275 => x"51", + 5276 => x"3f", + 5277 => x"08", + 5278 => x"33", + 5279 => x"8a", + 5280 => x"80", + 5281 => x"ff", + 5282 => x"53", + 5283 => x"86", + 5284 => x"83", + 5285 => x"c5", + 5286 => x"c8", + 5287 => x"ec", + 5288 => x"85", + 5289 => x"15", + 5290 => x"06", + 5291 => x"76", + 5292 => x"80", + 5293 => x"da", + 5294 => x"85", + 5295 => x"ff", + 5296 => x"74", + 5297 => x"d4", + 5298 => x"af", + 5299 => x"ec", + 5300 => x"c2", + 5301 => x"8c", + 5302 => x"ec", + 5303 => x"ff", + 5304 => x"56", + 5305 => x"83", + 5306 => x"14", + 5307 => x"71", + 5308 => x"5a", + 5309 => x"26", + 5310 => x"8a", + 5311 => x"74", + 5312 => x"fe", + 5313 => x"82", + 5314 => x"53", + 5315 => x"08", + 5316 => x"ed", + 5317 => x"ec", + 5318 => x"ff", + 5319 => x"83", + 5320 => x"72", + 5321 => x"26", + 5322 => x"57", + 5323 => x"26", + 5324 => x"57", + 5325 => x"56", + 5326 => x"82", + 5327 => x"13", + 5328 => x"0c", + 5329 => x"0c", + 5330 => x"a4", + 5331 => x"1e", + 5332 => x"54", + 5333 => x"2e", + 5334 => x"af", + 5335 => x"14", + 5336 => x"3f", + 5337 => x"08", + 5338 => x"06", + 5339 => x"72", + 5340 => x"7a", + 5341 => x"80", + 5342 => x"d8", + 5343 => x"85", + 5344 => x"15", + 5345 => x"2b", + 5346 => x"8d", + 5347 => x"2e", + 5348 => x"77", + 5349 => x"0c", + 5350 => x"76", + 5351 => x"38", + 5352 => x"11", + 5353 => x"81", + 5354 => x"51", + 5355 => x"13", + 5356 => x"8d", + 5357 => x"15", + 5358 => x"c5", + 5359 => x"90", + 5360 => x"0b", + 5361 => x"ff", + 5362 => x"15", + 5363 => x"2e", + 5364 => x"81", + 5365 => x"e4", + 5366 => x"88", + 5367 => x"ec", + 5368 => x"ff", + 5369 => x"81", + 5370 => x"06", + 5371 => x"81", + 5372 => x"51", + 5373 => x"82", + 5374 => x"80", + 5375 => x"85", + 5376 => x"15", + 5377 => x"14", + 5378 => x"3f", + 5379 => x"08", + 5380 => x"06", + 5381 => x"d4", + 5382 => x"81", + 5383 => x"38", + 5384 => x"d7", + 5385 => x"85", + 5386 => x"8b", + 5387 => x"2e", + 5388 => x"b3", + 5389 => x"14", + 5390 => x"3f", + 5391 => x"08", + 5392 => x"e4", + 5393 => x"81", + 5394 => x"84", + 5395 => x"d7", + 5396 => x"85", + 5397 => x"15", + 5398 => x"14", + 5399 => x"3f", + 5400 => x"08", + 5401 => x"76", + 5402 => x"9d", + 5403 => x"05", + 5404 => x"9d", + 5405 => x"86", + 5406 => x"0b", + 5407 => x"80", + 5408 => x"85", + 5409 => x"3d", + 5410 => x"3d", + 5411 => x"89", + 5412 => x"2e", + 5413 => x"08", + 5414 => x"2e", + 5415 => x"33", + 5416 => x"2e", + 5417 => x"13", + 5418 => x"22", + 5419 => x"76", + 5420 => x"06", + 5421 => x"13", + 5422 => x"92", + 5423 => x"ec", + 5424 => x"52", + 5425 => x"71", + 5426 => x"55", + 5427 => x"53", + 5428 => x"0c", + 5429 => x"85", + 5430 => x"3d", + 5431 => x"3d", + 5432 => x"05", + 5433 => x"89", + 5434 => x"52", + 5435 => x"3f", + 5436 => x"0b", + 5437 => x"08", + 5438 => x"82", + 5439 => x"82", + 5440 => x"90", + 5441 => x"55", + 5442 => x"2e", + 5443 => x"74", + 5444 => x"73", + 5445 => x"38", + 5446 => x"78", + 5447 => x"54", + 5448 => x"92", + 5449 => x"89", + 5450 => x"84", + 5451 => x"a9", + 5452 => x"ec", + 5453 => x"82", + 5454 => x"88", + 5455 => x"eb", + 5456 => x"02", + 5457 => x"e7", + 5458 => x"59", + 5459 => x"80", + 5460 => x"38", + 5461 => x"70", + 5462 => x"d0", + 5463 => x"3d", + 5464 => x"58", + 5465 => x"82", + 5466 => x"55", + 5467 => x"08", + 5468 => x"7a", + 5469 => x"8c", + 5470 => x"56", + 5471 => x"82", + 5472 => x"55", + 5473 => x"08", + 5474 => x"80", + 5475 => x"70", + 5476 => x"57", + 5477 => x"83", + 5478 => x"77", + 5479 => x"73", + 5480 => x"ab", + 5481 => x"2e", + 5482 => x"84", + 5483 => x"06", + 5484 => x"51", + 5485 => x"82", + 5486 => x"55", + 5487 => x"b2", + 5488 => x"06", + 5489 => x"b8", + 5490 => x"2a", + 5491 => x"51", + 5492 => x"2e", + 5493 => x"55", + 5494 => x"77", + 5495 => x"74", + 5496 => x"77", + 5497 => x"81", + 5498 => x"73", + 5499 => x"af", + 5500 => x"7a", + 5501 => x"3f", + 5502 => x"08", + 5503 => x"b2", + 5504 => x"8e", + 5505 => x"bc", + 5506 => x"a0", + 5507 => x"34", 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x"0b", + 5567 => x"77", + 5568 => x"81", + 5569 => x"73", + 5570 => x"8f", + 5571 => x"ec", + 5572 => x"81", + 5573 => x"85", + 5574 => x"1a", + 5575 => x"22", + 5576 => x"7b", + 5577 => x"a8", + 5578 => x"78", + 5579 => x"3f", + 5580 => x"08", + 5581 => x"ec", + 5582 => x"83", + 5583 => x"82", + 5584 => x"ff", + 5585 => x"06", + 5586 => x"55", + 5587 => x"56", + 5588 => x"05", + 5589 => x"80", + 5590 => x"77", + 5591 => x"38", + 5592 => x"06", + 5593 => x"c1", + 5594 => x"1a", + 5595 => x"38", + 5596 => x"06", + 5597 => x"2e", + 5598 => x"52", + 5599 => x"f6", + 5600 => x"ec", + 5601 => x"82", + 5602 => x"75", + 5603 => x"85", + 5604 => x"9c", + 5605 => x"39", + 5606 => x"74", + 5607 => x"85", + 5608 => x"3d", + 5609 => x"3d", + 5610 => x"65", + 5611 => x"5d", + 5612 => x"0c", + 5613 => x"05", + 5614 => x"f9", + 5615 => x"85", + 5616 => x"82", + 5617 => x"8a", + 5618 => x"33", + 5619 => x"2e", + 5620 => x"56", + 5621 => x"90", + 5622 => x"06", + 5623 => x"74", + 5624 => x"b6", + 5625 => x"82", + 5626 => x"34", + 5627 => x"aa", + 5628 => x"91", + 5629 => x"56", + 5630 => x"8c", + 5631 => x"1a", + 5632 => x"74", + 5633 => x"38", + 5634 => x"80", + 5635 => x"38", + 5636 => x"70", + 5637 => x"56", + 5638 => x"b2", + 5639 => x"11", + 5640 => x"77", + 5641 => x"5b", + 5642 => x"38", + 5643 => x"88", + 5644 => x"8f", + 5645 => x"08", + 5646 => x"d4", + 5647 => x"85", + 5648 => x"81", + 5649 => x"9f", + 5650 => x"2e", + 5651 => x"74", + 5652 => x"98", + 5653 => x"7e", + 5654 => x"3f", + 5655 => x"08", + 5656 => x"83", + 5657 => x"ec", + 5658 => x"89", + 5659 => x"77", + 5660 => x"d6", + 5661 => x"7f", + 5662 => x"58", + 5663 => x"75", + 5664 => x"75", + 5665 => x"77", + 5666 => x"7c", + 5667 => x"33", + 5668 => x"3f", + 5669 => x"08", + 5670 => x"7e", + 5671 => x"56", + 5672 => x"2e", + 5673 => x"16", + 5674 => x"55", + 5675 => x"94", + 5676 => x"53", + 5677 => x"b0", + 5678 => x"31", + 5679 => x"05", + 5680 => x"3f", + 5681 => x"56", + 5682 => x"9c", + 5683 => x"19", + 5684 => x"06", + 5685 => x"31", + 5686 => x"76", + 5687 => x"7b", + 5688 => x"08", + 5689 => x"d1", + 5690 => x"85", + 5691 => x"81", + 5692 => x"94", + 5693 => x"ff", + 5694 => x"05", + 5695 => x"ce", + 5696 => x"76", + 5697 => x"17", + 5698 => x"1e", + 5699 => x"18", + 5700 => x"5e", + 5701 => x"39", + 5702 => x"82", + 5703 => x"90", + 5704 => x"f2", + 5705 => x"63", + 5706 => x"40", + 5707 => x"7e", + 5708 => x"fc", + 5709 => x"51", + 5710 => x"82", + 5711 => x"55", + 5712 => x"08", + 5713 => x"18", + 5714 => x"80", + 5715 => x"74", + 5716 => x"39", + 5717 => x"70", + 5718 => x"81", + 5719 => x"56", + 5720 => x"80", + 5721 => x"38", + 5722 => x"0b", + 5723 => x"82", + 5724 => x"39", + 5725 => x"19", + 5726 => x"83", + 5727 => x"18", + 5728 => x"56", + 5729 => x"27", + 5730 => x"09", + 5731 => x"2e", + 5732 => x"94", + 5733 => x"83", + 5734 => x"56", + 5735 => x"38", + 5736 => x"22", + 5737 => x"89", + 5738 => x"55", + 5739 => x"75", + 5740 => x"18", + 5741 => x"9c", + 5742 => x"85", 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x"55", + 5802 => x"83", + 5803 => x"9c", + 5804 => x"7e", + 5805 => x"3f", + 5806 => x"08", + 5807 => x"75", + 5808 => x"94", + 5809 => x"ff", + 5810 => x"05", + 5811 => x"3f", + 5812 => x"0b", + 5813 => x"7b", + 5814 => x"08", + 5815 => x"76", + 5816 => x"08", + 5817 => x"1c", + 5818 => x"08", + 5819 => x"5c", + 5820 => x"83", + 5821 => x"74", + 5822 => x"fd", + 5823 => x"18", + 5824 => x"07", + 5825 => x"19", + 5826 => x"75", + 5827 => x"0c", + 5828 => x"04", + 5829 => x"7a", + 5830 => x"05", + 5831 => x"56", + 5832 => x"82", + 5833 => x"57", + 5834 => x"08", + 5835 => x"90", + 5836 => x"86", + 5837 => x"06", + 5838 => x"73", + 5839 => x"e9", + 5840 => x"08", + 5841 => x"cc", + 5842 => x"85", + 5843 => x"82", + 5844 => x"80", + 5845 => x"16", + 5846 => x"33", + 5847 => x"55", + 5848 => x"34", + 5849 => x"53", + 5850 => x"08", + 5851 => x"3f", + 5852 => x"52", + 5853 => x"c9", + 5854 => x"88", + 5855 => x"96", + 5856 => x"c0", + 5857 => x"92", + 5858 => x"9a", + 5859 => x"81", + 5860 => x"34", + 5861 => x"af", + 5862 => x"ec", + 5863 => x"33", + 5864 => x"55", + 5865 => x"17", + 5866 => x"85", + 5867 => x"3d", + 5868 => x"3d", + 5869 => x"52", + 5870 => x"3f", + 5871 => x"08", + 5872 => x"ec", + 5873 => x"86", + 5874 => x"52", + 5875 => x"ba", + 5876 => x"ec", + 5877 => x"85", + 5878 => x"38", + 5879 => x"08", + 5880 => x"82", + 5881 => x"86", + 5882 => x"ff", + 5883 => x"3d", + 5884 => x"3f", + 5885 => x"0b", + 5886 => x"08", + 5887 => x"82", + 5888 => x"82", + 5889 => x"80", + 5890 => x"85", + 5891 => x"3d", + 5892 => x"3d", + 5893 => x"93", + 5894 => x"52", + 5895 => x"e9", + 5896 => x"85", + 5897 => x"82", + 5898 => x"80", + 5899 => x"58", + 5900 => x"3d", + 5901 => x"df", + 5902 => x"85", + 5903 => x"82", + 5904 => x"bc", + 5905 => x"c7", + 5906 => x"98", + 5907 => x"73", + 5908 => x"38", + 5909 => x"12", + 5910 => x"39", + 5911 => x"33", + 5912 => x"70", + 5913 => x"55", + 5914 => x"2e", + 5915 => x"7f", + 5916 => x"54", + 5917 => x"82", + 5918 => x"94", + 5919 => x"39", + 5920 => x"08", + 5921 => x"81", + 5922 => x"85", + 5923 => x"85", + 5924 => x"3d", + 5925 => x"3d", + 5926 => x"5b", + 5927 => x"34", + 5928 => x"3d", + 5929 => x"52", + 5930 => x"e8", + 5931 => x"85", + 5932 => x"82", + 5933 => x"82", + 5934 => x"43", + 5935 => x"11", + 5936 => x"58", + 5937 => x"80", + 5938 => x"38", + 5939 => x"3d", + 5940 => x"d5", + 5941 => x"85", + 5942 => x"82", + 5943 => x"82", + 5944 => x"52", + 5945 => x"98", + 5946 => x"ec", + 5947 => x"85", + 5948 => x"c0", + 5949 => x"7b", + 5950 => x"3f", + 5951 => x"08", + 5952 => x"74", + 5953 => x"3f", + 5954 => x"08", + 5955 => x"ec", + 5956 => x"38", + 5957 => x"51", + 5958 => x"82", + 5959 => x"57", + 5960 => x"08", + 5961 => x"52", + 5962 => x"d1", + 5963 => x"85", + 5964 => x"a6", + 5965 => x"74", + 5966 => x"3f", + 5967 => x"08", + 5968 => x"ec", + 5969 => x"cc", + 5970 => x"2e", + 5971 => x"86", + 5972 => x"81", + 5973 => x"81", + 5974 => x"3d", + 5975 => x"52", + 5976 => x"a8", + 5977 => x"3d", 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x"ec", + 6037 => x"85", + 6038 => x"fc", + 6039 => x"33", + 6040 => x"f4", + 6041 => x"08", + 6042 => x"27", + 6043 => x"15", + 6044 => x"2a", + 6045 => x"51", + 6046 => x"83", + 6047 => x"94", + 6048 => x"80", + 6049 => x"0c", + 6050 => x"2e", + 6051 => x"79", + 6052 => x"70", + 6053 => x"51", + 6054 => x"2e", + 6055 => x"52", + 6056 => x"fe", + 6057 => x"82", + 6058 => x"ff", + 6059 => x"70", + 6060 => x"fe", + 6061 => x"82", + 6062 => x"73", + 6063 => x"76", + 6064 => x"70", + 6065 => x"94", + 6066 => x"71", + 6067 => x"08", + 6068 => x"53", + 6069 => x"15", + 6070 => x"a6", + 6071 => x"74", + 6072 => x"3f", + 6073 => x"08", + 6074 => x"ec", + 6075 => x"81", + 6076 => x"85", + 6077 => x"2e", + 6078 => x"82", + 6079 => x"88", + 6080 => x"98", + 6081 => x"80", + 6082 => x"38", + 6083 => x"80", + 6084 => x"77", + 6085 => x"08", + 6086 => x"0c", + 6087 => x"70", + 6088 => x"81", + 6089 => x"5a", + 6090 => x"2e", + 6091 => x"52", + 6092 => x"cf", + 6093 => x"ec", + 6094 => x"85", + 6095 => x"38", + 6096 => x"08", + 6097 => x"73", + 6098 => x"c6", + 6099 => x"85", + 6100 => x"73", + 6101 => x"38", + 6102 => x"af", + 6103 => x"73", + 6104 => x"27", + 6105 => x"98", + 6106 => x"a0", + 6107 => x"08", + 6108 => x"0c", + 6109 => x"06", + 6110 => x"2e", + 6111 => x"52", + 6112 => x"f2", + 6113 => x"ec", + 6114 => x"82", + 6115 => x"34", + 6116 => x"c4", + 6117 => x"91", + 6118 => x"53", + 6119 => x"89", + 6120 => x"ec", + 6121 => x"94", + 6122 => x"8c", + 6123 => x"27", + 6124 => x"8c", + 6125 => x"15", + 6126 => x"07", + 6127 => x"16", + 6128 => x"ff", + 6129 => x"80", + 6130 => x"77", + 6131 => x"2e", + 6132 => x"9c", + 6133 => x"53", + 6134 => x"ec", + 6135 => x"0d", + 6136 => x"0d", + 6137 => x"54", + 6138 => x"81", + 6139 => x"53", + 6140 => x"05", + 6141 => x"84", + 6142 => x"dd", + 6143 => x"ec", + 6144 => x"85", + 6145 => x"ea", + 6146 => x"0c", + 6147 => x"51", + 6148 => x"82", + 6149 => x"55", + 6150 => x"08", + 6151 => x"ab", + 6152 => x"98", + 6153 => x"80", + 6154 => x"38", + 6155 => x"70", + 6156 => x"81", + 6157 => x"57", + 6158 => x"ad", + 6159 => x"08", + 6160 => x"d3", + 6161 => x"85", + 6162 => x"17", + 6163 => x"86", + 6164 => x"17", + 6165 => x"75", + 6166 => x"3f", + 6167 => x"08", + 6168 => x"2e", + 6169 => x"85", + 6170 => x"86", + 6171 => x"2e", + 6172 => x"76", + 6173 => x"73", + 6174 => x"0c", + 6175 => x"04", + 6176 => x"76", + 6177 => x"05", + 6178 => x"53", + 6179 => x"82", + 6180 => x"87", + 6181 => x"ec", + 6182 => x"86", + 6183 => x"fb", + 6184 => x"79", + 6185 => x"05", + 6186 => x"56", + 6187 => x"3f", + 6188 => x"08", + 6189 => x"ec", + 6190 => x"38", + 6191 => x"82", + 6192 => x"52", + 6193 => x"d6", + 6194 => x"ec", + 6195 => x"cc", + 6196 => x"ec", + 6197 => x"51", + 6198 => x"82", + 6199 => x"53", + 6200 => x"08", + 6201 => x"81", + 6202 => x"80", + 6203 => x"82", + 6204 => x"a8", + 6205 => x"73", + 6206 => x"3f", + 6207 => x"51", + 6208 => x"82", + 6209 => x"84", + 6210 => x"81", + 6211 => x"07", + 6212 => x"82", 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x"25", + 6272 => x"19", + 6273 => x"5a", + 6274 => x"08", + 6275 => x"38", + 6276 => x"a4", + 6277 => x"85", + 6278 => x"58", + 6279 => x"77", + 6280 => x"7d", + 6281 => x"be", + 6282 => x"85", + 6283 => x"82", + 6284 => x"80", + 6285 => x"70", + 6286 => x"ff", + 6287 => x"56", + 6288 => x"2e", + 6289 => x"a0", + 6290 => x"51", + 6291 => x"3f", + 6292 => x"08", + 6293 => x"06", + 6294 => x"05", + 6295 => x"1b", + 6296 => x"5b", + 6297 => x"39", + 6298 => x"ff", + 6299 => x"82", + 6300 => x"f0", + 6301 => x"09", + 6302 => x"80", + 6303 => x"19", + 6304 => x"54", + 6305 => x"06", + 6306 => x"79", + 6307 => x"78", + 6308 => x"79", + 6309 => x"84", + 6310 => x"07", + 6311 => x"84", + 6312 => x"82", + 6313 => x"92", + 6314 => x"f9", + 6315 => x"8a", + 6316 => x"53", + 6317 => x"e3", + 6318 => x"85", + 6319 => x"82", + 6320 => x"81", + 6321 => x"17", + 6322 => x"81", + 6323 => x"17", + 6324 => x"2a", + 6325 => x"51", + 6326 => x"55", + 6327 => x"81", + 6328 => x"17", + 6329 => x"8c", + 6330 => x"81", + 6331 => x"9b", + 6332 => x"ec", + 6333 => x"17", + 6334 => x"51", + 6335 => x"82", + 6336 => x"74", + 6337 => x"56", + 6338 => x"98", + 6339 => x"76", + 6340 => x"93", + 6341 => x"ec", + 6342 => x"09", + 6343 => x"38", + 6344 => x"85", + 6345 => x"2e", + 6346 => x"85", + 6347 => x"a3", + 6348 => x"38", + 6349 => x"85", + 6350 => x"15", + 6351 => x"38", + 6352 => x"53", + 6353 => x"08", + 6354 => x"c3", + 6355 => x"85", + 6356 => x"94", + 6357 => x"18", + 6358 => x"33", + 6359 => x"54", + 6360 => x"34", + 6361 => x"85", + 6362 => x"18", + 6363 => x"74", + 6364 => x"0c", + 6365 => x"04", + 6366 => x"82", + 6367 => x"ff", + 6368 => x"a1", + 6369 => x"d1", + 6370 => x"ec", + 6371 => x"85", + 6372 => x"f7", + 6373 => x"a1", + 6374 => x"95", + 6375 => x"58", + 6376 => x"82", + 6377 => x"55", + 6378 => x"08", + 6379 => x"02", + 6380 => x"33", + 6381 => x"70", + 6382 => x"55", + 6383 => x"73", + 6384 => x"75", + 6385 => x"80", + 6386 => x"bf", + 6387 => x"d6", + 6388 => x"81", + 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x"05", + 6507 => x"94", + 6508 => x"64", + 6509 => x"c8", + 6510 => x"54", + 6511 => x"15", + 6512 => x"81", + 6513 => x"34", + 6514 => x"b7", + 6515 => x"85", + 6516 => x"8b", + 6517 => x"75", + 6518 => x"ff", + 6519 => x"73", + 6520 => x"0c", + 6521 => x"04", + 6522 => x"a9", + 6523 => x"51", + 6524 => x"82", + 6525 => x"ff", + 6526 => x"a9", + 6527 => x"d9", + 6528 => x"ec", + 6529 => x"85", + 6530 => x"d3", + 6531 => x"a9", + 6532 => x"9d", + 6533 => x"58", + 6534 => x"82", + 6535 => x"55", + 6536 => x"08", + 6537 => x"02", + 6538 => x"33", + 6539 => x"54", + 6540 => x"82", + 6541 => x"53", + 6542 => x"52", + 6543 => x"88", + 6544 => x"b4", + 6545 => x"53", + 6546 => x"3d", + 6547 => x"ff", + 6548 => x"aa", + 6549 => x"73", + 6550 => x"3f", + 6551 => x"08", + 6552 => x"ec", + 6553 => x"63", + 6554 => x"81", + 6555 => x"65", + 6556 => x"2e", + 6557 => x"55", + 6558 => x"82", + 6559 => x"84", + 6560 => x"06", + 6561 => x"73", + 6562 => x"3f", + 6563 => x"08", + 6564 => x"ec", + 6565 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x"a3", + 6742 => x"ec", + 6743 => x"76", + 6744 => x"0c", + 6745 => x"04", + 6746 => x"82", + 6747 => x"ff", + 6748 => x"9d", + 6749 => x"e1", + 6750 => x"ec", + 6751 => x"ec", + 6752 => x"82", + 6753 => x"83", + 6754 => x"53", + 6755 => x"3d", + 6756 => x"ff", + 6757 => x"73", + 6758 => x"70", + 6759 => x"52", + 6760 => x"9f", + 6761 => x"bc", + 6762 => x"74", + 6763 => x"6d", + 6764 => x"70", + 6765 => x"ae", + 6766 => x"85", + 6767 => x"2e", + 6768 => x"70", + 6769 => x"57", + 6770 => x"bd", + 6771 => x"ec", + 6772 => x"8d", + 6773 => x"2b", + 6774 => x"81", + 6775 => x"86", + 6776 => x"ec", + 6777 => x"9f", + 6778 => x"ff", + 6779 => x"54", + 6780 => x"8a", + 6781 => x"70", + 6782 => x"06", + 6783 => x"ff", + 6784 => x"38", + 6785 => x"15", + 6786 => x"80", + 6787 => x"74", + 6788 => x"b4", + 6789 => x"c9", + 6790 => x"ec", + 6791 => x"81", + 6792 => x"88", + 6793 => x"26", + 6794 => x"39", + 6795 => x"86", + 6796 => x"81", + 6797 => x"ff", + 6798 => x"38", + 6799 => x"54", + 6800 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7799 => x"43", + 7800 => x"20", + 7801 => x"75", + 7802 => x"64", + 7803 => x"64", + 7804 => x"25", + 7805 => x"0a", + 7806 => x"52", + 7807 => x"61", + 7808 => x"6e", + 7809 => x"70", + 7810 => x"63", + 7811 => x"6f", + 7812 => x"2e", + 7813 => x"43", + 7814 => x"20", + 7815 => x"6f", + 7816 => x"6e", + 7817 => x"2e", + 7818 => x"5a", + 7819 => x"62", + 7820 => x"25", + 7821 => x"25", + 7822 => x"73", + 7823 => x"00", + 7824 => x"25", + 7825 => x"25", + 7826 => x"73", + 7827 => x"25", + 7828 => x"25", + 7829 => x"42", + 7830 => x"63", + 7831 => x"61", + 7832 => x"0a", + 7833 => x"52", + 7834 => x"69", + 7835 => x"2e", + 7836 => x"45", + 7837 => x"6c", + 7838 => x"20", + 7839 => x"65", + 7840 => x"70", + 7841 => x"2e", + 7842 => x"25", + 7843 => x"64", + 7844 => x"20", + 7845 => x"25", + 7846 => x"64", + 7847 => x"25", + 7848 => x"53", + 7849 => x"43", + 7850 => x"69", + 7851 => x"61", + 7852 => x"6e", + 7853 => x"20", + 7854 => x"6f", + 7855 => x"6f", + 7856 => x"6f", + 7857 => x"67", + 7858 => x"3a", + 7859 => x"76", + 7860 => x"73", + 7861 => x"70", + 7862 => x"65", + 7863 => x"64", + 7864 => x"20", + 7865 => x"57", + 7866 => x"44", + 7867 => x"20", + 7868 => x"30", + 7869 => x"25", + 7870 => x"29", + 7871 => x"20", + 7872 => x"53", + 7873 => x"4d", + 7874 => x"20", + 7875 => x"30", + 7876 => x"25", + 7877 => x"29", + 7878 => x"20", + 7879 => x"49", + 7880 => x"20", + 7881 => x"4d", + 7882 => x"30", + 7883 => x"25", + 7884 => x"29", + 7885 => x"20", + 7886 => x"42", + 7887 => x"20", + 7888 => x"20", + 7889 => x"30", + 7890 => x"25", + 7891 => x"29", + 7892 => x"20", + 7893 => x"52", + 7894 => x"20", + 7895 => x"20", + 7896 => x"30", + 7897 => x"25", + 7898 => x"29", + 7899 => x"20", + 7900 => x"53", + 7901 => x"41", + 7902 => x"20", + 7903 => x"65", + 7904 => x"65", + 7905 => x"25", + 7906 => x"29", + 7907 => x"20", + 7908 => x"54", + 7909 => x"52", + 7910 => x"20", + 7911 => x"69", + 7912 => x"73", + 7913 => x"25", + 7914 => x"29", + 7915 => x"20", + 7916 => x"49", + 7917 => x"20", + 7918 => x"4c", + 7919 => x"68", + 7920 => x"65", + 7921 => x"25", + 7922 => x"29", + 7923 => x"20", + 7924 => x"57", + 7925 => x"42", + 7926 => x"20", + 7927 => x"0a", + 7928 => x"20", + 7929 => x"57", + 7930 => x"32", + 7931 => x"20", + 7932 => x"49", + 7933 => x"4c", + 7934 => x"20", + 7935 => x"50", + 7936 => x"00", + 7937 => x"20", + 7938 => x"53", + 7939 => x"00", + 7940 => x"41", + 7941 => x"65", + 7942 => x"73", + 7943 => x"20", + 7944 => x"43", + 7945 => x"52", + 7946 => x"74", + 7947 => x"63", + 7948 => x"20", + 7949 => x"72", + 7950 => x"20", + 7951 => x"30", + 7952 => x"00", + 7953 => x"20", + 7954 => x"43", + 7955 => x"4d", + 7956 => x"72", + 7957 => x"74", + 7958 => x"20", + 7959 => x"72", + 7960 => x"20", + 7961 => x"30", + 7962 => x"00", + 7963 => x"20", + 7964 => x"53", + 7965 => x"6b", + 7966 => x"61", + 7967 => x"41", + 7968 => x"65", + 7969 => x"20", + 7970 => x"20", + 7971 => x"30", + 7972 => x"00", + 7973 => x"4d", + 7974 => x"3a", + 7975 => x"20", + 7976 => x"5a", + 7977 => x"49", + 7978 => x"20", + 7979 => x"20", + 7980 => x"20", + 7981 => x"20", + 7982 => x"20", + 7983 => x"30", + 7984 => x"00", + 7985 => x"20", + 7986 => x"53", + 7987 => x"65", + 7988 => x"6c", + 7989 => x"20", + 7990 => x"71", + 7991 => x"20", + 7992 => x"20", + 7993 => x"64", + 7994 => x"34", + 7995 => x"7a", + 7996 => x"20", + 7997 => x"53", + 7998 => x"4d", + 7999 => x"6f", + 8000 => x"46", + 8001 => x"20", + 8002 => x"20", + 8003 => x"20", + 8004 => x"64", + 8005 => x"34", + 8006 => x"7a", + 8007 => x"20", + 8008 => x"57", + 8009 => x"62", + 8010 => x"20", + 8011 => x"41", + 8012 => x"6c", + 8013 => x"20", + 8014 => x"71", + 8015 => x"64", + 8016 => x"34", + 8017 => x"7a", + 8018 => x"53", + 8019 => x"6c", + 8020 => x"4d", + 8021 => x"75", + 8022 => x"46", + 8023 => x"00", + 8024 => x"45", + 8025 => x"45", + 8026 => x"69", + 8027 => x"55", + 8028 => x"6f", + 8029 => x"00", + 8030 => x"01", + 8031 => x"00", + 8032 => x"00", + 8033 => x"01", + 8034 => x"00", + 8035 => x"00", + 8036 => x"01", + 8037 => x"00", + 8038 => x"00", + 8039 => x"01", + 8040 => x"00", + 8041 => x"00", + 8042 => x"01", + 8043 => x"00", + 8044 => x"00", + 8045 => x"01", + 8046 => x"00", + 8047 => x"00", + 8048 => x"01", + 8049 => x"00", + 8050 => x"00", + 8051 => x"01", + 8052 => x"00", + 8053 => x"00", + 8054 => x"01", + 8055 => x"00", + 8056 => x"00", + 8057 => x"01", + 8058 => x"00", + 8059 => x"00", + 8060 => x"01", + 8061 => x"00", + 8062 => x"00", + 8063 => x"04", + 8064 => x"00", + 8065 => x"00", + 8066 => x"04", + 8067 => x"00", + 8068 => x"00", + 8069 => x"04", + 8070 => x"00", + 8071 => x"00", + 8072 => x"03", + 8073 => x"00", + 8074 => x"00", + 8075 => x"04", + 8076 => x"00", + 8077 => x"00", + 8078 => x"04", + 8079 => x"00", + 8080 => x"00", + 8081 => x"04", + 8082 => x"00", + 8083 => x"00", + 8084 => x"03", + 8085 => x"00", + 8086 => x"00", + 8087 => x"03", + 8088 => x"00", + 8089 => x"00", + 8090 => x"03", + 8091 => x"00", + 8092 => x"00", + 8093 => x"03", + 8094 => x"00", + 8095 => x"1b", + 8096 => x"1b", + 8097 => x"1b", + 8098 => x"1b", + 8099 => x"1b", + 8100 => x"1b", + 8101 => x"1b", + 8102 => x"1b", + 8103 => x"1b", + 8104 => x"1b", + 8105 => x"1b", + 8106 => x"10", + 8107 => x"0e", + 8108 => x"0d", + 8109 => x"0b", + 8110 => x"08", + 8111 => x"06", + 8112 => x"05", + 8113 => x"04", + 8114 => x"03", + 8115 => x"02", + 8116 => x"01", + 8117 => x"68", + 8118 => x"6f", + 8119 => x"68", + 8120 => x"00", + 8121 => x"21", + 8122 => x"25", + 8123 => x"20", + 8124 => x"0a", + 8125 => x"46", + 8126 => x"65", + 8127 => x"6f", + 8128 => x"73", + 8129 => x"74", + 8130 => x"68", + 8131 => x"6f", + 8132 => x"66", + 8133 => x"20", + 8134 => x"45", + 8135 => x"0a", + 8136 => x"43", + 8137 => x"6f", + 8138 => x"70", + 8139 => x"63", + 8140 => x"74", + 8141 => x"69", + 8142 => x"72", + 8143 => x"69", + 8144 => x"20", + 8145 => x"61", + 8146 => x"6e", + 8147 => x"00", + 8148 => x"53", + 8149 => x"22", + 8150 => x"3a", + 8151 => x"3e", + 8152 => x"7c", + 8153 => x"46", + 8154 => x"46", + 8155 => x"32", + 8156 => x"eb", + 8157 => x"53", + 8158 => x"35", + 8159 => x"4e", + 8160 => x"41", + 8161 => x"20", + 8162 => x"41", + 8163 => x"20", + 8164 => x"4e", + 8165 => x"41", + 8166 => x"20", + 8167 => x"41", + 8168 => x"20", + 8169 => x"00", + 8170 => x"00", + 8171 => x"00", + 8172 => x"00", + 8173 => x"80", + 8174 => x"8e", + 8175 => x"45", + 8176 => x"49", + 8177 => x"90", + 8178 => x"99", + 8179 => x"59", + 8180 => x"9c", + 8181 => x"41", + 8182 => x"a5", + 8183 => x"a8", + 8184 => x"ac", + 8185 => x"b0", + 8186 => x"b4", + 8187 => x"b8", + 8188 => x"bc", + 8189 => x"c0", + 8190 => x"c4", + 8191 => x"c8", + 8192 => x"cc", + 8193 => x"d0", + 8194 => x"d4", + 8195 => x"d8", + 8196 => x"dc", + 8197 => x"e0", + 8198 => x"e4", + 8199 => x"e8", + 8200 => x"ec", + 8201 => x"f0", + 8202 => x"f4", + 8203 => x"f8", + 8204 => x"fc", + 8205 => x"2b", + 8206 => x"3d", + 8207 => x"5c", + 8208 => x"3c", + 8209 => x"7f", + 8210 => x"00", + 8211 => x"00", + 8212 => x"01", + 8213 => x"00", + 8214 => x"00", + 8215 => x"00", + 8216 => x"00", + 8217 => x"00", + 8218 => x"00", + 8219 => x"00", + 8220 => x"01", + 8221 => x"00", + 8222 => x"00", + 8223 => x"00", + 8224 => x"01", + 8225 => x"00", + 8226 => x"00", + 8227 => x"00", + 8228 => x"01", + 8229 => x"00", + 8230 => x"00", + 8231 => x"00", + 8232 => x"01", + 8233 => x"00", + 8234 => x"00", + 8235 => x"00", + 8236 => x"01", + 8237 => x"00", + 8238 => x"00", + 8239 => x"00", + 8240 => x"01", + 8241 => x"00", + 8242 => x"00", + 8243 => x"00", + 8244 => x"01", + 8245 => x"00", + 8246 => x"00", + 8247 => x"00", + 8248 => x"01", + 8249 => x"00", + 8250 => x"00", + 8251 => x"00", + 8252 => x"01", + 8253 => x"00", + 8254 => x"00", + 8255 => x"00", + 8256 => x"01", + 8257 => x"00", + 8258 => x"00", + 8259 => x"00", + 8260 => x"01", + 8261 => x"00", + 8262 => x"00", + 8263 => x"00", + 8264 => x"01", + 8265 => x"00", + 8266 => x"00", + 8267 => x"00", + 8268 => x"01", + 8269 => x"00", + 8270 => x"00", + 8271 => x"00", + 8272 => x"01", + 8273 => x"00", + 8274 => x"00", + 8275 => x"00", + 8276 => x"01", + 8277 => x"00", + 8278 => x"00", + 8279 => x"00", + 8280 => x"01", + 8281 => x"00", + 8282 => x"00", + 8283 => x"00", + 8284 => x"01", + 8285 => x"00", + 8286 => x"00", + 8287 => x"00", + 8288 => x"01", + 8289 => x"00", + 8290 => x"00", + 8291 => x"00", + 8292 => x"01", + 8293 => x"00", + 8294 => x"00", + 8295 => x"00", + 8296 => x"01", + 8297 => x"00", + 8298 => x"00", + 8299 => x"00", + 8300 => x"01", + 8301 => x"00", + 8302 => x"00", + 8303 => x"00", + 8304 => x"01", + 8305 => x"00", + 8306 => x"00", + 8307 => x"00", + 8308 => x"01", + 8309 => x"00", + 8310 => x"00", + 8311 => x"00", + 8312 => x"01", + 8313 => x"00", + 8314 => x"00", + 8315 => x"00", + 8316 => x"01", + 8317 => x"00", + 8318 => x"00", + 8319 => x"00", + 8320 => x"01", + 8321 => x"00", + 8322 => x"00", + 8323 => x"00", + 8324 => x"00", + 8325 => x"00", + 8326 => x"00", + 8327 => x"00", + 8328 => x"00", + 8329 => x"00", + 8330 => x"00", + 8331 => x"00", + 8332 => x"01", + 8333 => x"01", + 8334 => x"00", + 8335 => x"00", + 8336 => x"00", + 8337 => x"00", + 8338 => x"05", + 8339 => x"05", + 8340 => x"05", + 8341 => x"00", + 8342 => x"01", + 8343 => x"01", + 8344 => x"01", + 8345 => x"01", + 8346 => x"00", + 8347 => x"00", + 8348 => x"00", + 8349 => x"00", + 8350 => x"00", + 8351 => x"00", + 8352 => x"00", + 8353 => x"00", + 8354 => x"00", + 8355 => x"00", + 8356 => x"00", + 8357 => x"00", + 8358 => x"00", + 8359 => x"00", + 8360 => x"00", + 8361 => x"00", + 8362 => x"00", + 8363 => x"00", + 8364 => x"00", + 8365 => x"00", + 8366 => x"00", + 8367 => x"00", + 8368 => x"00", + 8369 => x"00", + 8370 => x"00", + 8371 => x"01", + 8372 => x"00", + 8373 => x"01", + 8374 => x"00", + 8375 => x"02", + 8376 => x"00", + 8377 => x"00", + 8378 => x"01", + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 0 - Port B - bits 7 downto 0 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM0(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(7 downto 0); + memBRead(7 downto 0) <= memBWrite(7 downto 0); + else + memBRead(7 downto 0) <= RAM0(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 1 - Port B - bits 15 downto 8 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM1(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(15 downto 8); + memBRead(15 downto 8) <= memBWrite(15 downto 8); + else + memBRead(15 downto 8) <= RAM1(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 2 - Port B - bits 23 downto 16 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM2(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(23 downto 16); + memBRead(23 downto 16) <= memBWrite(23 downto 16); + else + memBRead(23 downto 16) <= RAM2(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- BRAM Byte 3 - Port B - bits 31 downto 24 + process(clk) + begin + if rising_edge(clk) then + if memBWriteEnable = '1' then + RAM3(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))) := memBWrite(31 downto 24); + memBRead(31 downto 24) <= memBWrite(31 downto 24); + else + memBRead(31 downto 24) <= RAM3(to_integer(unsigned(memBAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + +end arch; diff --git a/zpu/devices/sysbus/BRAM/zOS_SinglePortBootBRAM.vhd b/zpu/devices/sysbus/BRAM/zOS_SinglePortBootBRAM.vhd new file mode 100644 index 0000000..f9e1132 --- /dev/null +++ b/zpu/devices/sysbus/BRAM/zOS_SinglePortBootBRAM.vhd @@ -0,0 +1,33680 @@ +-- Byte Addressed 32bit BRAM module for the ZPU Evo implementation. +-- +-- Copyright 2018-2019 - Philip Smart for the ZPU Evo implementation. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +entity SinglePortBootBRAM is + generic + ( + addrbits : integer := 16 + ); + port + ( + clk : in std_logic; + memAAddr : in std_logic_vector(addrbits-1 downto 0); + memAWriteEnable : in std_logic; + memAWriteByte : in std_logic; + memAWriteHalfWord : in std_logic; + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE) + ); +end SinglePortBootBRAM; + +architecture arch of SinglePortBootBRAM is + + type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0); + + shared variable RAM0 : ramArray := + ( + 0 => x"ff", + 1 => x"0b", + 2 => x"04", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"80", + 10 => x"0c", + 11 => x"0c", + 12 => x"00", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"08", + 17 => x"09", + 18 => x"05", + 19 => x"83", + 20 => x"52", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"08", + 25 => x"73", + 26 => x"81", + 27 => x"83", + 28 => x"06", + 29 => x"ff", + 30 => x"0b", + 31 => x"00", + 32 => x"05", + 33 => x"73", + 34 => x"06", + 35 => x"06", + 36 => x"06", + 37 => x"00", + 38 => x"00", + 39 => x"00", + 40 => x"73", + 41 => x"53", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"09", + 49 => x"06", + 50 => x"72", + 51 => x"72", + 52 => x"31", + 53 => x"06", + 54 => x"51", + 55 => x"00", + 56 => x"73", + 57 => x"53", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"92", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"2b", + 81 => x"04", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"06", + 89 => x"0b", + 90 => x"e2", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"ff", + 97 => x"2a", + 98 => x"0a", + 99 => x"05", + 100 => x"51", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"51", + 105 => x"83", + 106 => x"05", + 107 => x"2b", + 108 => x"72", + 109 => x"51", + 110 => x"00", + 111 => x"00", + 112 => x"05", + 113 => x"70", + 114 => x"06", + 115 => x"53", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"05", + 121 => x"70", + 122 => x"06", + 123 => x"06", + 124 => x"00", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"05", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"81", + 137 => x"51", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"06", + 145 => x"06", + 146 => x"04", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"08", + 153 => x"09", + 154 => x"05", + 155 => x"2a", + 156 => x"52", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"08", + 161 => x"e7", + 162 => x"06", + 163 => x"08", + 164 => x"0b", + 165 => x"00", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"75", + 170 => x"99", + 171 => x"50", + 172 => x"90", + 173 => x"88", + 174 => x"00", + 175 => x"00", + 176 => x"08", + 177 => x"75", + 178 => x"9b", + 179 => x"50", + 180 => x"90", + 181 => x"88", + 182 => x"00", + 183 => x"00", + 184 => x"81", + 185 => x"0a", + 186 => x"05", + 187 => x"06", + 188 => x"74", + 189 => x"06", + 190 => x"51", + 191 => x"00", + 192 => x"81", + 193 => x"0a", + 194 => x"ff", + 195 => x"71", + 196 => x"72", + 197 => x"05", + 198 => x"51", + 199 => x"00", + 200 => x"04", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"52", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"72", + 233 => x"52", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"ff", + 249 => x"51", + 250 => x"ff", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"00", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"8c", + 265 => x"0b", + 266 => x"04", + 267 => x"8c", + 268 => x"0b", + 269 => x"04", + 270 => x"8c", + 271 => x"0b", + 272 => x"04", + 273 => x"8c", + 274 => x"0b", + 275 => x"04", + 276 => x"8c", + 277 => x"0b", + 278 => x"04", + 279 => x"8d", + 280 => x"0b", + 281 => x"04", + 282 => x"8d", + 283 => x"0b", + 284 => x"04", + 285 => x"8d", + 286 => x"0b", + 287 => x"04", + 288 => x"8d", + 289 => x"0b", + 290 => x"04", + 291 => x"8e", + 292 => x"0b", + 293 => x"04", + 294 => x"8e", + 295 => x"0b", + 296 => x"04", + 297 => x"8e", + 298 => x"0b", + 299 => x"04", + 300 => x"8e", + 301 => x"0b", + 302 => x"04", + 303 => x"8f", + 304 => x"0b", + 305 => x"04", + 306 => x"8f", + 307 => x"0b", + 308 => x"04", + 309 => x"8f", + 310 => x"0b", + 311 => x"04", + 312 => x"8f", + 313 => x"0b", + 314 => x"04", + 315 => x"90", + 316 => x"0b", + 317 => x"04", + 318 => x"90", + 319 => x"0b", + 320 => x"04", + 321 => x"90", + 322 => x"0b", + 323 => x"04", + 324 => x"90", + 325 => x"0b", + 326 => x"04", + 327 => x"91", + 328 => x"0b", + 329 => x"04", + 330 => x"91", + 331 => x"0b", + 332 => x"04", + 333 => x"91", + 334 => x"0b", + 335 => x"04", + 336 => x"91", + 337 => x"0b", + 338 => x"04", + 339 => x"92", + 340 => x"0b", + 341 => x"04", + 342 => x"92", + 343 => x"ff", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"81", + 385 => x"f8", + 386 => x"8c", + 387 => x"f8", + 388 => x"90", + 389 => x"f8", + 390 => x"8e", + 391 => x"f8", + 392 => x"90", + 393 => x"f8", + 394 => x"cd", + 395 => x"f8", + 396 => x"90", + 397 => x"f8", + 398 => x"eb", + 399 => x"f8", + 400 => x"90", + 401 => x"f8", + 402 => x"b5", + 403 => x"f8", + 404 => x"90", + 405 => x"f8", + 406 => x"b6", + 407 => x"f8", + 408 => x"90", + 409 => x"f8", + 410 => x"8e", + 411 => x"f8", + 412 => x"90", + 413 => x"f8", + 414 => x"d3", + 415 => x"f8", + 416 => x"90", + 417 => x"f8", + 418 => x"cf", + 419 => x"f8", + 420 => x"90", + 421 => x"f8", + 422 => x"db", + 423 => x"f8", + 424 => x"90", + 425 => x"f8", + 426 => x"c0", + 427 => x"f8", + 428 => x"90", + 429 => x"f8", + 430 => x"f1", + 431 => x"f8", + 432 => x"90", + 433 => x"f8", + 434 => x"95", + 435 => x"f8", + 436 => x"90", + 437 => x"f8", + 438 => x"95", + 439 => x"f8", + 440 => x"90", + 441 => x"f8", + 442 => x"e4", + 443 => x"f8", + 444 => x"90", + 445 => x"f8", + 446 => x"2d", + 447 => x"08", + 448 => x"04", + 449 => x"0c", + 450 => x"82", + 451 => x"82", + 452 => x"82", + 453 => x"be", + 454 => x"85", + 455 => x"a0", + 456 => x"85", + 457 => x"aa", + 458 => x"85", + 459 => x"a0", + 460 => x"85", + 461 => x"b7", + 462 => x"85", + 463 => x"a0", + 464 => x"85", + 465 => x"af", + 466 => x"85", + 467 => x"a0", + 468 => x"85", + 469 => x"b2", + 470 => x"85", + 471 => x"a0", + 472 => x"85", + 473 => x"bc", + 474 => x"85", + 475 => x"a0", + 476 => x"85", + 477 => x"c5", + 478 => x"85", + 479 => x"a0", + 480 => x"85", + 481 => x"b6", + 482 => x"85", + 483 => x"a0", + 484 => x"85", + 485 => x"bf", + 486 => x"85", + 487 => x"a0", + 488 => x"85", + 489 => x"c0", + 490 => x"85", + 491 => x"a0", + 492 => x"85", + 493 => x"c1", + 494 => x"85", + 495 => x"a0", + 496 => x"85", + 497 => x"c9", + 498 => x"85", + 499 => x"a0", + 500 => x"85", + 501 => x"c6", + 502 => x"85", + 503 => x"a0", + 504 => x"85", + 505 => x"cb", + 506 => x"85", + 507 => x"a0", + 508 => x"85", + 509 => x"c2", + 510 => x"85", + 511 => x"a0", + 512 => x"85", + 513 => x"ce", + 514 => x"85", + 515 => x"a0", + 516 => x"85", + 517 => x"cf", + 518 => x"85", + 519 => x"a0", + 520 => x"85", + 521 => x"b8", + 522 => x"85", + 523 => x"a0", + 524 => x"85", + 525 => x"b7", + 526 => x"85", + 527 => x"a0", + 528 => x"85", + 529 => x"b9", + 530 => x"85", + 531 => x"a0", + 532 => x"85", + 533 => x"c2", + 534 => x"85", + 535 => x"a0", + 536 => x"85", + 537 => x"d0", + 538 => x"85", + 539 => x"a0", + 540 => x"85", + 541 => x"d2", + 542 => x"85", + 543 => x"a0", + 544 => x"85", + 545 => x"d6", + 546 => x"85", + 547 => x"a0", + 548 => x"85", + 549 => x"a9", + 550 => x"85", + 551 => x"a0", + 552 => x"85", + 553 => x"d9", + 554 => x"85", + 555 => x"a0", + 556 => x"85", + 557 => x"e7", + 558 => x"85", + 559 => x"a0", + 560 => x"85", + 561 => x"e5", + 562 => x"85", + 563 => x"a0", + 564 => x"85", + 565 => x"fa", + 566 => x"85", + 567 => x"a0", + 568 => x"85", + 569 => x"fc", + 570 => x"85", + 571 => x"a0", + 572 => x"85", + 573 => x"fe", + 574 => x"85", + 575 => x"a0", + 576 => x"85", + 577 => x"ed", + 578 => x"f8", + 579 => x"90", + 580 => x"f8", + 581 => x"2d", + 582 => x"08", + 583 => x"04", + 584 => x"0c", + 585 => x"2d", + 586 => x"08", + 587 => x"04", + 588 => x"0c", + 589 => x"82", + 590 => x"82", + 591 => x"3c", + 592 => x"10", + 593 => x"10", + 594 => x"10", + 595 => x"10", + 596 => x"10", + 597 => x"10", + 598 => x"10", + 599 => x"10", + 600 => x"51", + 601 => x"73", + 602 => x"73", + 603 => x"81", + 604 => x"10", + 605 => x"07", + 606 => x"0c", + 607 => x"72", + 608 => x"81", + 609 => x"09", + 610 => x"71", + 611 => x"0a", + 612 => x"72", + 613 => x"51", + 614 => x"82", + 615 => x"82", + 616 => x"8e", + 617 => x"70", + 618 => x"0c", + 619 => x"93", + 620 => x"81", + 621 => x"04", + 622 => x"f8", + 623 => x"85", + 624 => x"3d", + 625 => x"f8", + 626 => x"08", + 627 => x"08", + 628 => x"82", + 629 => x"fc", + 630 => x"71", + 631 => x"f8", + 632 => x"08", + 633 => x"85", + 634 => x"05", + 635 => x"ff", + 636 => x"70", + 637 => x"38", + 638 => x"85", + 639 => x"05", + 640 => x"82", + 641 => x"fc", + 642 => x"85", + 643 => x"05", + 644 => x"f8", + 645 => x"08", + 646 => x"85", + 647 => x"84", + 648 => x"85", + 649 => x"82", + 650 => x"02", + 651 => x"0c", + 652 => x"82", + 653 => x"88", + 654 => x"85", + 655 => x"05", + 656 => x"f8", + 657 => x"08", + 658 => x"82", + 659 => x"8c", + 660 => x"05", + 661 => x"08", + 662 => x"82", + 663 => x"fc", + 664 => x"51", + 665 => x"82", + 666 => x"fc", + 667 => x"05", + 668 => x"08", + 669 => x"70", + 670 => x"51", + 671 => x"84", + 672 => x"39", + 673 => x"08", + 674 => x"70", + 675 => x"0c", + 676 => x"0d", + 677 => x"0c", + 678 => x"f8", + 679 => x"85", + 680 => x"3d", + 681 => x"f8", + 682 => x"08", + 683 => x"08", + 684 => x"82", + 685 => x"8c", + 686 => x"85", + 687 => x"05", + 688 => x"f8", + 689 => x"08", + 690 => x"e5", + 691 => x"f8", + 692 => x"08", + 693 => x"85", + 694 => x"05", + 695 => x"f8", + 696 => x"08", + 697 => x"85", + 698 => x"05", + 699 => x"f8", + 700 => x"08", + 701 => x"38", + 702 => x"08", + 703 => x"51", + 704 => x"85", + 705 => x"05", + 706 => x"82", + 707 => x"f8", + 708 => x"85", + 709 => x"05", + 710 => x"71", + 711 => x"85", + 712 => x"05", + 713 => x"82", + 714 => x"fc", + 715 => x"ad", + 716 => x"f8", + 717 => x"08", + 718 => x"ec", + 719 => x"3d", + 720 => x"f8", + 721 => x"85", + 722 => x"82", + 723 => x"fd", + 724 => x"85", + 725 => x"05", + 726 => x"81", + 727 => x"85", + 728 => x"05", + 729 => x"33", + 730 => x"08", + 731 => x"81", + 732 => x"f8", + 733 => x"0c", + 734 => x"08", + 735 => x"70", + 736 => x"ff", + 737 => x"54", + 738 => x"2e", + 739 => x"ce", + 740 => x"f8", + 741 => x"08", + 742 => x"82", + 743 => x"88", + 744 => x"05", + 745 => x"08", + 746 => x"70", + 747 => x"51", + 748 => x"38", + 749 => x"85", + 750 => x"05", + 751 => x"39", + 752 => x"08", + 753 => x"ff", + 754 => x"f8", + 755 => x"0c", + 756 => x"08", + 757 => x"80", + 758 => x"ff", + 759 => x"85", + 760 => x"05", + 761 => x"80", + 762 => x"85", + 763 => x"05", + 764 => x"52", + 765 => x"38", + 766 => x"85", + 767 => x"05", + 768 => x"39", + 769 => x"08", + 770 => x"ff", + 771 => x"f8", + 772 => x"0c", + 773 => x"08", + 774 => x"70", + 775 => x"70", + 776 => x"0b", + 777 => x"08", + 778 => x"ae", + 779 => x"f8", + 780 => x"08", + 781 => x"85", + 782 => x"05", + 783 => x"72", + 784 => x"82", + 785 => x"fc", + 786 => x"55", + 787 => x"8a", + 788 => x"82", + 789 => x"fc", + 790 => x"85", + 791 => x"05", + 792 => x"ec", + 793 => x"0d", + 794 => x"0c", + 795 => x"f8", + 796 => x"85", + 797 => x"3d", + 798 => x"f8", + 799 => x"08", + 800 => x"08", + 801 => x"82", + 802 => x"90", + 803 => x"2e", + 804 => x"82", + 805 => x"90", + 806 => x"05", + 807 => x"08", + 808 => x"82", + 809 => x"90", + 810 => x"05", + 811 => x"08", + 812 => x"82", + 813 => x"90", + 814 => x"2e", + 815 => x"85", + 816 => x"05", + 817 => x"82", + 818 => x"fc", + 819 => x"52", + 820 => x"82", + 821 => x"fc", + 822 => x"05", + 823 => x"08", + 824 => x"ff", + 825 => x"85", + 826 => x"05", + 827 => x"85", + 828 => x"84", + 829 => x"85", + 830 => x"82", + 831 => x"02", + 832 => x"0c", + 833 => x"80", + 834 => x"f8", + 835 => x"0c", + 836 => x"08", + 837 => x"80", + 838 => x"82", + 839 => x"88", + 840 => x"82", + 841 => x"88", + 842 => x"0b", + 843 => x"08", + 844 => x"82", + 845 => x"fc", + 846 => x"38", + 847 => x"85", + 848 => x"05", + 849 => x"f8", + 850 => x"08", + 851 => x"08", + 852 => x"82", + 853 => x"8c", + 854 => x"25", + 855 => x"85", + 856 => x"05", + 857 => x"85", + 858 => x"05", + 859 => x"82", + 860 => x"f0", + 861 => x"85", + 862 => x"05", + 863 => x"81", + 864 => x"f8", + 865 => x"0c", + 866 => x"08", + 867 => x"82", + 868 => x"fc", + 869 => x"53", + 870 => x"08", + 871 => x"52", + 872 => x"08", + 873 => x"51", + 874 => x"82", + 875 => x"70", + 876 => x"08", + 877 => x"54", + 878 => x"08", + 879 => x"80", + 880 => x"82", + 881 => x"f8", + 882 => x"82", + 883 => x"f8", + 884 => x"85", + 885 => x"05", + 886 => x"85", + 887 => x"89", + 888 => x"85", + 889 => x"82", + 890 => x"02", + 891 => x"0c", + 892 => x"80", + 893 => x"f8", + 894 => x"0c", + 895 => x"08", + 896 => x"80", + 897 => x"82", + 898 => x"88", + 899 => x"82", + 900 => x"88", + 901 => x"0b", + 902 => x"08", + 903 => x"82", + 904 => x"8c", + 905 => x"25", + 906 => x"85", + 907 => x"05", + 908 => x"85", + 909 => x"05", + 910 => x"82", + 911 => x"8c", + 912 => x"82", + 913 => x"88", + 914 => x"82", + 915 => x"85", + 916 => x"82", + 917 => x"f8", + 918 => x"82", + 919 => x"fc", + 920 => x"2e", + 921 => x"85", + 922 => x"05", + 923 => x"85", + 924 => x"05", + 925 => x"f8", + 926 => x"08", + 927 => x"ec", + 928 => x"3d", + 929 => x"f8", + 930 => x"85", + 931 => x"82", + 932 => x"ff", + 933 => x"0b", + 934 => x"08", + 935 => x"82", + 936 => x"88", + 937 => x"06", + 938 => x"09", + 939 => x"f8", + 940 => x"08", + 941 => x"f8", + 942 => x"08", + 943 => x"f8", + 944 => x"0c", + 945 => x"08", + 946 => x"81", + 947 => x"f8", + 948 => x"0c", + 949 => x"08", + 950 => x"10", + 951 => x"08", + 952 => x"51", + 953 => x"82", + 954 => x"88", + 955 => x"2e", + 956 => x"ab", + 957 => x"f8", + 958 => x"08", + 959 => x"ec", + 960 => x"3d", + 961 => x"f8", + 962 => x"85", + 963 => x"82", + 964 => x"fd", + 965 => x"53", + 966 => x"08", + 967 => x"52", + 968 => x"08", + 969 => x"51", + 970 => x"82", + 971 => x"70", + 972 => x"0c", + 973 => x"0d", + 974 => x"0c", + 975 => x"f8", + 976 => x"85", + 977 => x"3d", + 978 => x"82", + 979 => x"8c", + 980 => x"82", + 981 => x"88", + 982 => x"93", + 983 => x"ec", + 984 => x"85", + 985 => x"85", + 986 => x"85", + 987 => x"82", + 988 => x"02", + 989 => x"0c", + 990 => x"81", + 991 => x"f8", + 992 => x"0c", + 993 => x"85", + 994 => x"05", + 995 => x"f8", + 996 => x"08", + 997 => x"08", + 998 => x"27", + 999 => x"85", + 1000 => x"05", + 1001 => x"ae", + 1002 => x"82", + 1003 => x"8c", + 1004 => x"a2", + 1005 => x"f8", + 1006 => x"08", + 1007 => x"f8", + 1008 => x"0c", + 1009 => x"08", + 1010 => x"10", + 1011 => x"08", + 1012 => x"ff", + 1013 => x"85", + 1014 => x"05", + 1015 => x"80", + 1016 => x"85", + 1017 => x"05", + 1018 => x"f8", + 1019 => x"08", + 1020 => x"82", + 1021 => x"88", + 1022 => x"85", + 1023 => x"05", + 1024 => x"85", + 1025 => x"05", + 1026 => x"f8", + 1027 => x"08", + 1028 => x"08", + 1029 => x"07", + 1030 => x"08", + 1031 => x"82", + 1032 => x"fc", + 1033 => x"2a", + 1034 => x"08", + 1035 => x"82", + 1036 => x"8c", + 1037 => x"2a", + 1038 => x"08", + 1039 => x"ff", + 1040 => x"85", + 1041 => x"05", + 1042 => x"93", + 1043 => x"f8", + 1044 => x"08", + 1045 => x"f8", + 1046 => x"0c", + 1047 => x"82", + 1048 => x"f8", + 1049 => x"82", + 1050 => x"f4", + 1051 => x"82", + 1052 => x"f4", + 1053 => x"85", + 1054 => x"3d", + 1055 => x"f8", + 1056 => x"3d", + 1057 => x"08", + 1058 => x"58", + 1059 => x"80", + 1060 => x"39", + 1061 => x"f2", + 1062 => x"85", + 1063 => x"78", + 1064 => x"33", + 1065 => x"39", + 1066 => x"73", + 1067 => x"81", + 1068 => x"81", + 1069 => x"39", + 1070 => x"84", + 1071 => x"ec", + 1072 => x"52", + 1073 => x"3f", + 1074 => x"08", + 1075 => x"75", + 1076 => x"f2", + 1077 => x"ec", + 1078 => x"84", + 1079 => x"73", + 1080 => x"b0", + 1081 => x"70", + 1082 => x"58", + 1083 => x"27", + 1084 => x"54", + 1085 => x"ec", + 1086 => x"0d", + 1087 => x"0d", + 1088 => x"93", + 1089 => x"38", + 1090 => x"52", + 1091 => x"12", + 1092 => x"ea", + 1093 => x"80", + 1094 => x"80", + 1095 => x"39", + 1096 => x"51", + 1097 => x"81", + 1098 => x"80", + 1099 => x"eb", + 1100 => x"e4", + 1101 => x"c8", + 1102 => x"39", + 1103 => x"51", + 1104 => x"81", + 1105 => x"80", + 1106 => x"ec", + 1107 => x"c8", + 1108 => x"9c", + 1109 => x"39", + 1110 => x"51", + 1111 => x"ec", + 1112 => x"39", + 1113 => x"51", + 1114 => x"ed", + 1115 => x"39", + 1116 => x"51", + 1117 => x"ed", + 1118 => x"39", + 1119 => x"51", + 1120 => x"ed", + 1121 => x"39", + 1122 => x"51", + 1123 => x"ee", + 1124 => x"39", + 1125 => x"51", + 1126 => x"83", + 1127 => x"fb", + 1128 => x"79", + 1129 => x"87", + 1130 => x"38", + 1131 => x"75", + 1132 => x"3f", + 1133 => x"85", + 1134 => x"90", + 1135 => x"52", + 1136 => x"c6", + 1137 => x"ec", + 1138 => x"51", + 1139 => x"82", + 1140 => x"54", + 1141 => x"52", + 1142 => x"51", + 1143 => x"87", + 1144 => x"ec", + 1145 => x"02", + 1146 => x"e3", + 1147 => x"57", + 1148 => x"09", + 1149 => x"7a", + 1150 => x"51", + 1151 => x"78", + 1152 => x"ff", + 1153 => x"81", + 1154 => x"07", + 1155 => x"06", + 1156 => x"56", + 1157 => x"38", + 1158 => x"52", + 1159 => x"52", + 1160 => x"98", + 1161 => x"ec", + 1162 => x"85", + 1163 => x"38", + 1164 => x"08", + 1165 => x"88", + 1166 => x"ec", + 1167 => x"3d", + 1168 => x"84", + 1169 => x"52", + 1170 => x"8a", + 1171 => x"85", + 1172 => x"82", + 1173 => x"90", + 1174 => x"74", + 1175 => x"38", + 1176 => x"19", + 1177 => x"39", + 1178 => x"05", + 1179 => x"bf", + 1180 => x"81", + 1181 => x"07", + 1182 => x"09", + 1183 => x"9f", + 1184 => x"51", + 1185 => x"74", + 1186 => x"38", + 1187 => x"53", + 1188 => x"88", + 1189 => x"51", + 1190 => x"76", + 1191 => x"85", + 1192 => x"3d", + 1193 => x"3d", + 1194 => x"84", + 1195 => x"33", + 1196 => x"57", + 1197 => x"52", + 1198 => x"a7", + 1199 => x"ec", + 1200 => x"75", + 1201 => x"38", + 1202 => x"98", + 1203 => x"60", + 1204 => x"82", + 1205 => x"7e", + 1206 => x"77", + 1207 => x"ec", + 1208 => x"39", + 1209 => x"82", + 1210 => x"89", + 1211 => x"f3", + 1212 => x"61", + 1213 => x"05", + 1214 => x"33", + 1215 => x"68", + 1216 => x"5c", + 1217 => x"7a", + 1218 => x"e8", + 1219 => x"3f", + 1220 => x"51", + 1221 => x"80", + 1222 => x"27", + 1223 => x"7b", + 1224 => x"38", + 1225 => x"a4", + 1226 => x"39", + 1227 => x"72", + 1228 => x"38", + 1229 => x"81", + 1230 => x"ae", + 1231 => x"39", + 1232 => x"51", + 1233 => x"82", + 1234 => x"39", + 1235 => x"72", + 1236 => x"38", + 1237 => x"81", + 1238 => x"ad", + 1239 => x"39", + 1240 => x"51", + 1241 => x"84", + 1242 => x"39", + 1243 => x"72", + 1244 => x"38", + 1245 => x"81", + 1246 => x"ad", + 1247 => x"39", + 1248 => x"51", + 1249 => x"81", + 1250 => x"51", + 1251 => x"ff", + 1252 => x"ef", + 1253 => x"d3", + 1254 => x"74", + 1255 => x"38", + 1256 => x"33", + 1257 => x"56", + 1258 => x"83", + 1259 => x"80", + 1260 => x"27", + 1261 => x"53", + 1262 => x"70", + 1263 => x"51", + 1264 => x"2e", + 1265 => x"80", + 1266 => x"38", + 1267 => x"39", + 1268 => x"ba", + 1269 => x"55", + 1270 => x"ef", + 1271 => x"8b", + 1272 => x"79", + 1273 => x"9b", + 1274 => x"85", + 1275 => x"2b", + 1276 => x"51", + 1277 => x"2e", + 1278 => x"ae", + 1279 => x"3f", + 1280 => x"08", + 1281 => x"98", + 1282 => x"32", + 1283 => x"05", + 1284 => x"70", + 1285 => x"70", + 1286 => x"75", + 1287 => x"58", + 1288 => x"51", + 1289 => x"24", + 1290 => x"9b", + 1291 => x"06", + 1292 => x"53", + 1293 => x"1e", + 1294 => x"26", + 1295 => x"ff", + 1296 => x"85", + 1297 => x"3d", + 1298 => x"3d", + 1299 => x"05", + 1300 => x"9c", + 1301 => x"a0", + 1302 => x"ff", + 1303 => x"c4", + 1304 => x"d1", + 1305 => x"ac", + 1306 => x"b8", + 1307 => x"c5", + 1308 => x"ef", + 1309 => x"e3", + 1310 => x"2e", + 1311 => x"86", + 1312 => x"0d", + 1313 => x"0d", + 1314 => x"80", + 1315 => x"ec", + 1316 => x"96", + 1317 => x"ef", + 1318 => x"e0", + 1319 => x"96", + 1320 => x"81", + 1321 => x"06", + 1322 => x"80", + 1323 => x"81", + 1324 => x"3f", + 1325 => x"51", + 1326 => x"80", + 1327 => x"3f", + 1328 => x"70", + 1329 => x"52", + 1330 => x"92", + 1331 => x"96", + 1332 => x"f0", + 1333 => x"a4", + 1334 => x"96", + 1335 => x"83", + 1336 => x"06", + 1337 => x"80", + 1338 => x"81", + 1339 => x"3f", + 1340 => x"51", + 1341 => x"80", + 1342 => x"3f", + 1343 => x"70", + 1344 => x"52", + 1345 => x"92", + 1346 => x"95", + 1347 => x"f0", + 1348 => x"e8", + 1349 => x"95", + 1350 => x"85", + 1351 => x"06", + 1352 => x"80", + 1353 => x"81", + 1354 => x"3f", + 1355 => x"51", + 1356 => x"80", + 1357 => x"3f", + 1358 => x"70", + 1359 => x"52", + 1360 => x"92", + 1361 => x"95", + 1362 => x"f0", + 1363 => x"ac", + 1364 => x"95", + 1365 => x"87", + 1366 => x"06", + 1367 => x"80", + 1368 => x"81", + 1369 => x"3f", + 1370 => x"51", + 1371 => x"80", + 1372 => x"3f", + 1373 => x"70", + 1374 => x"52", + 1375 => x"92", + 1376 => x"94", + 1377 => x"f0", + 1378 => x"f0", + 1379 => x"94", + 1380 => x"f0", + 1381 => x"0d", + 1382 => x"0d", + 1383 => x"05", + 1384 => x"70", + 1385 => x"80", + 1386 => x"ed", + 1387 => x"0b", + 1388 => x"33", + 1389 => x"38", + 1390 => x"f1", + 1391 => x"9c", + 1392 => x"fe", + 1393 => x"85", + 1394 => x"81", + 1395 => x"85", + 1396 => x"80", + 1397 => x"31", + 1398 => x"73", + 1399 => x"80", + 1400 => x"0b", + 1401 => x"33", + 1402 => x"2e", + 1403 => x"af", + 1404 => x"cc", + 1405 => x"75", + 1406 => x"c4", + 1407 => x"ec", + 1408 => x"8b", + 1409 => x"ec", + 1410 => x"df", + 1411 => x"82", + 1412 => x"81", + 1413 => x"82", + 1414 => x"82", + 1415 => x"0b", + 1416 => x"e8", + 1417 => x"82", + 1418 => x"06", + 1419 => x"f1", + 1420 => x"52", + 1421 => x"92", + 1422 => x"82", + 1423 => x"87", + 1424 => x"ce", + 1425 => x"70", + 1426 => x"c8", + 1427 => x"81", + 1428 => x"80", + 1429 => x"82", + 1430 => x"81", + 1431 => x"78", + 1432 => x"81", + 1433 => x"81", + 1434 => x"96", + 1435 => x"59", + 1436 => x"7c", + 1437 => x"82", + 1438 => x"80", + 1439 => x"82", + 1440 => x"7d", + 1441 => x"81", + 1442 => x"8d", + 1443 => x"70", + 1444 => x"f2", + 1445 => x"d3", + 1446 => x"70", + 1447 => x"f8", + 1448 => x"fd", + 1449 => x"3d", + 1450 => x"51", + 1451 => x"82", + 1452 => x"90", + 1453 => x"2c", + 1454 => x"80", + 1455 => x"9c", + 1456 => x"c2", + 1457 => x"78", + 1458 => x"d1", + 1459 => x"24", + 1460 => x"80", + 1461 => x"38", + 1462 => x"80", + 1463 => x"bb", + 1464 => x"c0", + 1465 => x"38", + 1466 => x"24", + 1467 => x"78", + 1468 => x"8a", + 1469 => x"39", + 1470 => x"2e", + 1471 => x"78", + 1472 => x"92", + 1473 => x"c3", + 1474 => x"38", + 1475 => x"2e", + 1476 => x"8a", + 1477 => x"81", + 1478 => x"ed", + 1479 => x"83", + 1480 => x"78", + 1481 => x"89", + 1482 => x"ef", + 1483 => x"85", + 1484 => x"38", + 1485 => x"b4", + 1486 => x"11", + 1487 => x"05", + 1488 => x"3f", + 1489 => x"08", + 1490 => x"c6", + 1491 => x"fe", + 1492 => x"ff", + 1493 => x"a7", + 1494 => x"85", + 1495 => x"2e", + 1496 => x"b4", + 1497 => x"11", + 1498 => x"05", + 1499 => x"3f", + 1500 => x"08", + 1501 => x"85", + 1502 => x"81", + 1503 => x"9f", + 1504 => x"63", + 1505 => x"7b", + 1506 => x"38", + 1507 => x"7a", + 1508 => x"5c", + 1509 => x"26", + 1510 => x"d8", + 1511 => x"ff", + 1512 => x"ff", + 1513 => x"a7", + 1514 => x"85", + 1515 => x"2e", + 1516 => x"b4", + 1517 => x"11", + 1518 => x"05", + 1519 => x"3f", + 1520 => x"08", + 1521 => x"ca", + 1522 => x"fe", + 1523 => x"ff", + 1524 => x"a6", + 1525 => x"85", + 1526 => x"2e", + 1527 => x"81", + 1528 => x"9f", + 1529 => x"5a", + 1530 => x"81", + 1531 => x"59", + 1532 => x"05", + 1533 => x"34", + 1534 => x"42", + 1535 => x"3d", + 1536 => x"53", + 1537 => x"51", + 1538 => x"82", + 1539 => x"80", + 1540 => x"38", + 1541 => x"fc", + 1542 => x"84", + 1543 => x"b3", + 1544 => x"ec", + 1545 => x"fc", + 1546 => x"3d", + 1547 => x"53", + 1548 => x"51", + 1549 => x"82", + 1550 => x"80", + 1551 => x"38", + 1552 => x"51", + 1553 => x"63", + 1554 => x"27", + 1555 => x"70", + 1556 => x"5e", + 1557 => x"7c", + 1558 => x"78", + 1559 => x"79", + 1560 => x"52", + 1561 => x"51", + 1562 => x"81", + 1563 => x"05", + 1564 => x"39", + 1565 => x"51", + 1566 => x"b4", + 1567 => x"11", + 1568 => x"05", + 1569 => x"3f", + 1570 => x"08", + 1571 => x"82", + 1572 => x"59", + 1573 => x"89", + 1574 => x"90", + 1575 => x"cd", + 1576 => x"d9", + 1577 => x"80", + 1578 => x"82", + 1579 => x"44", + 1580 => x"84", + 1581 => x"78", + 1582 => x"38", + 1583 => x"08", + 1584 => x"82", + 1585 => x"59", + 1586 => x"88", + 1587 => x"a8", + 1588 => x"39", + 1589 => x"33", + 1590 => x"2e", + 1591 => x"84", + 1592 => x"89", + 1593 => x"c0", + 1594 => x"05", + 1595 => x"fe", + 1596 => x"ff", + 1597 => x"a4", + 1598 => x"85", + 1599 => x"de", + 1600 => x"d8", + 1601 => x"80", + 1602 => x"82", + 1603 => x"43", + 1604 => x"82", + 1605 => x"59", + 1606 => x"88", + 1607 => x"9c", + 1608 => x"39", + 1609 => x"33", + 1610 => x"2e", + 1611 => x"84", + 1612 => x"aa", + 1613 => x"db", + 1614 => x"80", + 1615 => x"82", + 1616 => x"43", + 1617 => x"84", + 1618 => x"78", + 1619 => x"38", + 1620 => x"08", + 1621 => x"82", + 1622 => x"88", + 1623 => x"3d", + 1624 => x"53", + 1625 => x"51", + 1626 => x"82", + 1627 => x"80", + 1628 => x"80", + 1629 => x"7a", + 1630 => x"38", + 1631 => x"90", + 1632 => x"81", + 1633 => x"07", + 1634 => x"7f", + 1635 => x"5a", + 1636 => x"2e", + 1637 => x"a0", + 1638 => x"88", + 1639 => x"dc", + 1640 => x"3f", + 1641 => x"54", + 1642 => x"52", + 1643 => x"bf", + 1644 => x"ec", + 1645 => x"3f", + 1646 => x"b4", + 1647 => x"11", + 1648 => x"05", + 1649 => x"3f", + 1650 => x"08", + 1651 => x"c2", + 1652 => x"fe", + 1653 => x"ff", + 1654 => x"a2", + 1655 => x"85", + 1656 => x"2e", + 1657 => x"59", + 1658 => x"05", + 1659 => x"63", + 1660 => x"b4", + 1661 => x"11", + 1662 => x"05", + 1663 => x"3f", + 1664 => x"08", + 1665 => x"8a", + 1666 => x"33", + 1667 => x"f2", + 1668 => x"c7", + 1669 => x"52", + 1670 => x"99", + 1671 => x"79", + 1672 => x"ae", + 1673 => x"38", + 1674 => x"9f", + 1675 => x"fe", + 1676 => x"ff", + 1677 => x"a2", + 1678 => x"85", + 1679 => x"2e", + 1680 => x"59", + 1681 => x"05", + 1682 => x"63", + 1683 => x"ff", + 1684 => x"f3", + 1685 => x"93", + 1686 => x"39", + 1687 => x"f4", + 1688 => x"84", + 1689 => x"e7", + 1690 => x"ec", + 1691 => x"f8", + 1692 => x"3d", + 1693 => x"53", + 1694 => x"51", + 1695 => x"82", + 1696 => x"80", + 1697 => x"60", + 1698 => x"05", + 1699 => x"82", + 1700 => x"78", + 1701 => x"fe", + 1702 => x"ff", + 1703 => x"a3", + 1704 => x"85", + 1705 => x"38", + 1706 => x"60", + 1707 => x"52", + 1708 => x"51", + 1709 => x"80", + 1710 => x"51", + 1711 => x"79", + 1712 => x"59", + 1713 => x"f7", + 1714 => x"9f", + 1715 => x"60", + 1716 => x"d7", + 1717 => x"fe", + 1718 => x"ff", + 1719 => x"a2", + 1720 => x"85", + 1721 => x"2e", + 1722 => x"59", + 1723 => x"22", + 1724 => x"05", + 1725 => x"41", + 1726 => x"81", + 1727 => x"98", + 1728 => x"a7", + 1729 => x"fe", + 1730 => x"ff", + 1731 => x"a2", + 1732 => x"85", + 1733 => x"2e", + 1734 => x"b4", + 1735 => x"11", + 1736 => x"05", + 1737 => x"3f", + 1738 => x"08", + 1739 => x"38", + 1740 => x"0c", + 1741 => x"05", + 1742 => x"fe", + 1743 => x"ff", + 1744 => x"a2", + 1745 => x"85", + 1746 => x"38", + 1747 => x"60", + 1748 => x"52", + 1749 => x"51", + 1750 => x"80", + 1751 => x"51", + 1752 => x"79", + 1753 => x"59", + 1754 => x"f6", + 1755 => x"79", + 1756 => x"b4", + 1757 => x"11", + 1758 => x"05", + 1759 => x"3f", + 1760 => x"08", + 1761 => x"38", + 1762 => x"0c", + 1763 => x"05", + 1764 => x"39", + 1765 => x"51", + 1766 => x"ff", + 1767 => x"3d", + 1768 => x"53", + 1769 => x"51", + 1770 => x"82", + 1771 => x"80", + 1772 => x"38", + 1773 => x"f3", + 1774 => x"9f", + 1775 => x"78", + 1776 => x"ff", + 1777 => x"ff", + 1778 => x"9f", + 1779 => x"85", + 1780 => x"2e", + 1781 => x"63", + 1782 => x"c0", + 1783 => x"3f", + 1784 => x"2d", + 1785 => x"08", + 1786 => x"a6", + 1787 => x"ec", + 1788 => x"f3", + 1789 => x"e3", + 1790 => x"39", + 1791 => x"51", + 1792 => x"db", + 1793 => x"8a", + 1794 => x"94", + 1795 => x"3f", + 1796 => x"ab", + 1797 => x"3f", + 1798 => x"79", + 1799 => x"59", + 1800 => x"f4", + 1801 => x"7d", + 1802 => x"80", + 1803 => x"38", + 1804 => x"84", + 1805 => x"b5", + 1806 => x"ec", + 1807 => x"5b", + 1808 => x"b1", + 1809 => x"24", + 1810 => x"81", + 1811 => x"80", + 1812 => x"83", + 1813 => x"80", + 1814 => x"f4", + 1815 => x"55", + 1816 => x"54", + 1817 => x"f4", + 1818 => x"3d", + 1819 => x"51", + 1820 => x"b8", + 1821 => x"d0", + 1822 => x"ff", + 1823 => x"9b", + 1824 => x"39", + 1825 => x"f4", + 1826 => x"53", + 1827 => x"52", + 1828 => x"b0", + 1829 => x"d9", + 1830 => x"7b", + 1831 => x"81", + 1832 => x"b4", + 1833 => x"05", + 1834 => x"3f", + 1835 => x"58", + 1836 => x"57", + 1837 => x"55", + 1838 => x"a0", + 1839 => x"a0", + 1840 => x"3d", + 1841 => x"51", + 1842 => x"82", + 1843 => x"82", + 1844 => x"09", + 1845 => x"05", + 1846 => x"80", + 1847 => x"5b", + 1848 => x"7a", + 1849 => x"38", + 1850 => x"7a", + 1851 => x"80", + 1852 => x"81", + 1853 => x"ff", + 1854 => x"7a", + 1855 => x"7d", + 1856 => x"81", + 1857 => x"78", + 1858 => x"ff", + 1859 => x"06", + 1860 => x"81", + 1861 => x"9a", + 1862 => x"f6", + 1863 => x"0d", + 1864 => x"85", + 1865 => x"c0", + 1866 => x"08", + 1867 => x"84", + 1868 => x"51", + 1869 => x"82", + 1870 => x"90", + 1871 => x"55", + 1872 => x"80", + 1873 => x"e3", + 1874 => x"82", + 1875 => x"07", + 1876 => x"c0", + 1877 => x"08", + 1878 => x"84", + 1879 => x"51", + 1880 => x"82", + 1881 => x"90", + 1882 => x"55", + 1883 => x"80", + 1884 => x"e3", + 1885 => x"82", + 1886 => x"07", + 1887 => x"80", + 1888 => x"c0", + 1889 => x"8c", + 1890 => x"87", + 1891 => x"0c", + 1892 => x"0b", + 1893 => x"0c", + 1894 => x"0b", + 1895 => x"0c", + 1896 => x"92", + 1897 => x"f4", + 1898 => x"bf", + 1899 => x"f0", + 1900 => x"3f", + 1901 => x"92", + 1902 => x"51", + 1903 => x"f1", + 1904 => x"04", + 1905 => x"80", + 1906 => x"71", + 1907 => x"87", + 1908 => x"85", + 1909 => x"ff", + 1910 => x"ff", + 1911 => x"72", + 1912 => x"38", + 1913 => x"ec", + 1914 => x"0d", + 1915 => x"0d", + 1916 => x"54", + 1917 => x"52", + 1918 => x"2e", + 1919 => x"72", + 1920 => x"a0", + 1921 => x"06", + 1922 => x"13", + 1923 => x"72", + 1924 => x"a2", + 1925 => x"06", + 1926 => x"13", + 1927 => x"72", + 1928 => x"2e", + 1929 => x"9f", + 1930 => x"81", + 1931 => x"72", + 1932 => x"70", + 1933 => x"38", + 1934 => x"80", + 1935 => x"73", + 1936 => x"39", + 1937 => x"80", + 1938 => x"54", + 1939 => x"83", + 1940 => x"70", + 1941 => x"38", + 1942 => x"80", + 1943 => x"54", + 1944 => x"09", + 1945 => x"38", + 1946 => x"a2", + 1947 => x"81", + 1948 => x"25", + 1949 => x"51", + 1950 => x"2e", + 1951 => x"72", + 1952 => x"54", + 1953 => x"0c", + 1954 => x"82", + 1955 => x"86", + 1956 => x"fc", + 1957 => x"53", + 1958 => x"2e", + 1959 => x"3d", + 1960 => x"72", + 1961 => x"3f", + 1962 => x"08", + 1963 => x"53", + 1964 => x"53", + 1965 => x"ec", + 1966 => x"0d", + 1967 => x"0d", + 1968 => x"33", + 1969 => x"53", + 1970 => x"8b", + 1971 => x"38", + 1972 => x"ff", + 1973 => x"52", + 1974 => x"81", + 1975 => x"13", + 1976 => x"52", + 1977 => x"80", + 1978 => x"13", + 1979 => x"52", + 1980 => x"80", + 1981 => x"13", + 1982 => x"52", + 1983 => x"80", + 1984 => x"13", + 1985 => x"52", + 1986 => x"26", + 1987 => x"8a", + 1988 => x"87", + 1989 => x"e7", + 1990 => x"38", + 1991 => x"c0", + 1992 => x"72", + 1993 => x"98", + 1994 => x"13", + 1995 => x"98", + 1996 => x"13", + 1997 => x"98", + 1998 => x"13", + 1999 => x"98", + 2000 => x"13", + 2001 => x"98", + 2002 => x"13", + 2003 => x"98", + 2004 => x"87", + 2005 => x"0c", + 2006 => x"98", + 2007 => x"0b", + 2008 => x"9c", + 2009 => x"71", + 2010 => x"0c", + 2011 => x"04", + 2012 => x"7f", + 2013 => x"98", + 2014 => x"7d", + 2015 => x"98", + 2016 => x"7d", + 2017 => x"c0", + 2018 => x"5a", + 2019 => x"34", + 2020 => x"b4", + 2021 => x"83", + 2022 => x"c0", + 2023 => x"5a", + 2024 => x"34", + 2025 => x"ac", + 2026 => x"85", + 2027 => x"c0", + 2028 => x"5a", + 2029 => x"34", + 2030 => x"a4", + 2031 => x"88", + 2032 => x"c0", + 2033 => x"5a", + 2034 => x"23", + 2035 => x"79", + 2036 => x"06", + 2037 => x"ff", + 2038 => x"86", + 2039 => x"85", + 2040 => x"84", + 2041 => x"83", + 2042 => x"82", + 2043 => x"7d", + 2044 => x"06", + 2045 => x"88", + 2046 => x"3f", + 2047 => x"04", + 2048 => x"02", + 2049 => x"70", + 2050 => x"70", + 2051 => x"52", + 2052 => x"84", + 2053 => x"3d", + 2054 => x"3d", + 2055 => x"84", + 2056 => x"81", + 2057 => x"55", + 2058 => x"94", + 2059 => x"80", + 2060 => x"87", + 2061 => x"51", + 2062 => x"96", + 2063 => x"06", + 2064 => x"70", + 2065 => x"38", + 2066 => x"70", + 2067 => x"51", + 2068 => x"72", + 2069 => x"81", + 2070 => x"70", + 2071 => x"38", + 2072 => x"70", + 2073 => x"51", + 2074 => x"38", + 2075 => x"06", + 2076 => x"94", + 2077 => x"80", + 2078 => x"87", + 2079 => x"52", + 2080 => x"75", + 2081 => x"0c", + 2082 => x"04", + 2083 => x"02", + 2084 => x"82", + 2085 => x"70", + 2086 => x"57", + 2087 => x"c0", + 2088 => x"74", + 2089 => x"38", + 2090 => x"94", + 2091 => x"70", + 2092 => x"81", + 2093 => x"52", + 2094 => x"8c", + 2095 => x"2a", + 2096 => x"51", + 2097 => x"38", + 2098 => x"70", + 2099 => x"51", + 2100 => x"8d", + 2101 => x"2a", + 2102 => x"51", + 2103 => x"be", + 2104 => x"ff", + 2105 => x"c0", + 2106 => x"70", + 2107 => x"38", + 2108 => x"90", + 2109 => x"0c", + 2110 => x"04", + 2111 => x"79", + 2112 => x"33", + 2113 => x"06", + 2114 => x"70", + 2115 => x"fc", + 2116 => x"ff", + 2117 => x"82", + 2118 => x"70", + 2119 => x"59", + 2120 => x"87", + 2121 => x"51", + 2122 => x"86", + 2123 => x"94", + 2124 => x"08", + 2125 => x"70", + 2126 => x"54", + 2127 => x"2e", + 2128 => x"91", + 2129 => x"06", + 2130 => x"d7", + 2131 => x"32", + 2132 => x"51", + 2133 => x"2e", + 2134 => x"93", + 2135 => x"06", + 2136 => x"ff", + 2137 => x"81", + 2138 => x"87", + 2139 => x"52", + 2140 => x"86", + 2141 => x"94", + 2142 => x"72", + 2143 => x"74", + 2144 => x"ff", + 2145 => x"57", + 2146 => x"38", + 2147 => x"ec", + 2148 => x"0d", + 2149 => x"0d", + 2150 => x"33", + 2151 => x"06", + 2152 => x"c0", + 2153 => x"72", + 2154 => x"38", + 2155 => x"94", + 2156 => x"70", + 2157 => x"81", + 2158 => x"51", + 2159 => x"e2", + 2160 => x"ff", + 2161 => x"c0", + 2162 => x"70", + 2163 => x"38", + 2164 => x"90", + 2165 => x"70", + 2166 => x"82", + 2167 => x"51", + 2168 => x"04", + 2169 => x"82", + 2170 => x"70", + 2171 => x"52", + 2172 => x"94", + 2173 => x"80", + 2174 => x"87", + 2175 => x"52", + 2176 => x"82", + 2177 => x"06", + 2178 => x"ff", + 2179 => x"2e", + 2180 => x"81", + 2181 => x"87", + 2182 => x"52", + 2183 => x"86", + 2184 => x"94", + 2185 => x"08", + 2186 => x"70", + 2187 => x"53", + 2188 => x"85", + 2189 => x"3d", + 2190 => x"3d", + 2191 => x"9e", + 2192 => x"9c", + 2193 => x"51", + 2194 => x"2e", + 2195 => x"87", + 2196 => x"08", + 2197 => x"0c", + 2198 => x"a8", + 2199 => x"94", + 2200 => x"9e", + 2201 => x"84", + 2202 => x"c0", + 2203 => x"82", + 2204 => x"87", + 2205 => x"08", + 2206 => x"0c", + 2207 => x"a0", + 2208 => x"a4", + 2209 => x"9e", + 2210 => x"84", + 2211 => x"c0", + 2212 => x"82", + 2213 => x"87", + 2214 => x"08", + 2215 => x"0c", + 2216 => x"b8", + 2217 => x"b4", + 2218 => x"9e", + 2219 => x"84", + 2220 => x"c0", + 2221 => x"82", + 2222 => x"87", + 2223 => x"08", + 2224 => x"0c", + 2225 => x"80", + 2226 => x"82", + 2227 => x"87", + 2228 => x"08", + 2229 => x"0c", + 2230 => x"88", + 2231 => x"cc", + 2232 => x"9e", + 2233 => x"84", + 2234 => x"0b", + 2235 => x"34", + 2236 => x"c0", + 2237 => x"70", + 2238 => x"06", + 2239 => x"70", + 2240 => x"38", + 2241 => x"82", + 2242 => x"80", + 2243 => x"9e", + 2244 => x"88", + 2245 => x"51", + 2246 => x"80", + 2247 => x"81", + 2248 => x"84", + 2249 => x"0b", + 2250 => x"90", + 2251 => x"80", + 2252 => x"52", + 2253 => x"2e", + 2254 => x"52", + 2255 => x"d7", + 2256 => x"87", + 2257 => x"08", + 2258 => x"80", + 2259 => x"52", + 2260 => x"83", + 2261 => x"71", + 2262 => x"34", + 2263 => x"c0", + 2264 => x"70", + 2265 => x"06", + 2266 => x"70", + 2267 => x"38", + 2268 => x"82", + 2269 => x"80", + 2270 => x"9e", + 2271 => x"90", + 2272 => x"51", + 2273 => x"80", + 2274 => x"81", + 2275 => x"84", + 2276 => x"0b", + 2277 => x"90", + 2278 => x"80", + 2279 => x"52", + 2280 => x"2e", + 2281 => x"52", + 2282 => x"db", + 2283 => x"87", + 2284 => x"08", + 2285 => x"80", + 2286 => x"52", + 2287 => x"83", + 2288 => x"71", + 2289 => x"34", + 2290 => x"c0", + 2291 => x"70", + 2292 => x"06", + 2293 => x"70", + 2294 => x"38", + 2295 => x"82", + 2296 => x"80", + 2297 => x"9e", + 2298 => x"80", + 2299 => x"51", + 2300 => x"80", + 2301 => x"81", + 2302 => x"84", + 2303 => x"0b", + 2304 => x"90", + 2305 => x"80", + 2306 => x"52", + 2307 => x"83", + 2308 => x"71", + 2309 => x"34", + 2310 => x"90", + 2311 => x"80", + 2312 => x"2a", + 2313 => x"70", + 2314 => x"34", + 2315 => x"c0", + 2316 => x"70", + 2317 => x"51", + 2318 => x"80", + 2319 => x"81", + 2320 => x"84", + 2321 => x"c0", + 2322 => x"70", + 2323 => x"70", + 2324 => x"51", + 2325 => x"84", + 2326 => x"0b", + 2327 => x"90", + 2328 => x"06", + 2329 => x"70", + 2330 => x"38", + 2331 => x"82", + 2332 => x"87", + 2333 => x"08", + 2334 => x"51", + 2335 => x"84", + 2336 => x"3d", + 2337 => x"3d", + 2338 => x"a0", + 2339 => x"3f", + 2340 => x"33", + 2341 => x"2e", + 2342 => x"f5", + 2343 => x"cb", + 2344 => x"c8", + 2345 => x"3f", + 2346 => x"33", + 2347 => x"2e", + 2348 => x"84", + 2349 => x"84", + 2350 => x"54", + 2351 => x"e0", + 2352 => x"3f", + 2353 => x"33", + 2354 => x"2e", + 2355 => x"84", + 2356 => x"84", + 2357 => x"54", + 2358 => x"fc", + 2359 => x"3f", + 2360 => x"33", + 2361 => x"2e", + 2362 => x"84", + 2363 => x"84", + 2364 => x"54", + 2365 => x"98", + 2366 => x"3f", + 2367 => x"33", + 2368 => x"2e", + 2369 => x"84", + 2370 => x"84", + 2371 => x"54", + 2372 => x"b4", + 2373 => x"3f", + 2374 => x"33", + 2375 => x"2e", + 2376 => x"84", + 2377 => x"84", + 2378 => x"54", + 2379 => x"d0", + 2380 => x"3f", + 2381 => x"33", + 2382 => x"2e", + 2383 => x"84", + 2384 => x"81", + 2385 => x"8a", + 2386 => x"84", + 2387 => x"73", + 2388 => x"38", + 2389 => x"33", + 2390 => x"8c", + 2391 => x"3f", + 2392 => x"33", + 2393 => x"2e", + 2394 => x"84", + 2395 => x"81", + 2396 => x"89", + 2397 => x"84", + 2398 => x"73", + 2399 => x"38", + 2400 => x"51", + 2401 => x"82", + 2402 => x"54", + 2403 => x"88", + 2404 => x"e0", + 2405 => x"3f", + 2406 => x"33", + 2407 => x"2e", + 2408 => x"f7", + 2409 => x"c3", + 2410 => x"dd", + 2411 => x"80", + 2412 => x"81", + 2413 => x"83", + 2414 => x"84", + 2415 => x"73", + 2416 => x"38", + 2417 => x"51", + 2418 => x"81", + 2419 => x"83", + 2420 => x"84", + 2421 => x"81", + 2422 => x"88", + 2423 => x"84", + 2424 => x"81", + 2425 => x"88", + 2426 => x"84", + 2427 => x"81", + 2428 => x"88", + 2429 => x"f9", + 2430 => x"ef", + 2431 => x"c4", + 2432 => x"f9", + 2433 => x"d3", + 2434 => x"c8", + 2435 => x"84", + 2436 => x"51", + 2437 => x"82", + 2438 => x"54", + 2439 => x"52", + 2440 => x"08", + 2441 => x"3f", + 2442 => x"ec", + 2443 => x"73", + 2444 => x"c4", + 2445 => x"3f", + 2446 => x"33", + 2447 => x"2e", + 2448 => x"84", + 2449 => x"bd", + 2450 => x"74", + 2451 => x"3f", + 2452 => x"08", + 2453 => x"c0", + 2454 => x"ec", + 2455 => x"aa", + 2456 => x"85", + 2457 => x"53", + 2458 => x"f9", + 2459 => x"eb", + 2460 => x"d6", + 2461 => x"80", + 2462 => x"82", + 2463 => x"55", + 2464 => x"52", + 2465 => x"82", + 2466 => x"ec", + 2467 => x"84", + 2468 => x"85", + 2469 => x"cf", + 2470 => x"82", + 2471 => x"31", + 2472 => x"81", + 2473 => x"87", + 2474 => x"f2", + 2475 => x"bb", + 2476 => x"0d", + 2477 => x"0d", + 2478 => x"33", + 2479 => x"71", + 2480 => x"38", + 2481 => x"52", + 2482 => x"12", + 2483 => x"fa", + 2484 => x"39", + 2485 => x"51", + 2486 => x"fa", + 2487 => x"39", + 2488 => x"51", + 2489 => x"fa", + 2490 => x"39", + 2491 => x"51", + 2492 => x"84", + 2493 => x"71", + 2494 => x"04", + 2495 => x"c0", + 2496 => x"04", + 2497 => x"08", + 2498 => x"84", + 2499 => x"3d", + 2500 => x"05", + 2501 => x"8a", + 2502 => x"06", + 2503 => x"51", + 2504 => x"9c", + 2505 => x"71", + 2506 => x"38", + 2507 => x"82", + 2508 => x"81", + 2509 => x"fc", + 2510 => x"82", + 2511 => x"52", + 2512 => x"85", + 2513 => x"71", + 2514 => x"0d", + 2515 => x"0d", + 2516 => x"33", + 2517 => x"08", + 2518 => x"f4", + 2519 => x"ff", + 2520 => x"82", + 2521 => x"84", + 2522 => x"fd", + 2523 => x"54", + 2524 => x"81", + 2525 => x"53", + 2526 => x"8e", + 2527 => x"ff", + 2528 => x"14", + 2529 => x"3f", + 2530 => x"3d", + 2531 => x"3d", + 2532 => x"9c", + 2533 => x"82", + 2534 => x"56", + 2535 => x"70", + 2536 => x"53", + 2537 => x"2e", + 2538 => x"81", + 2539 => x"81", + 2540 => x"da", + 2541 => x"74", + 2542 => x"0c", + 2543 => x"04", + 2544 => x"66", + 2545 => x"78", + 2546 => x"5a", + 2547 => x"80", + 2548 => x"38", + 2549 => x"09", + 2550 => x"e4", + 2551 => x"7a", + 2552 => x"5c", + 2553 => x"5b", + 2554 => x"09", + 2555 => x"38", + 2556 => x"39", + 2557 => x"09", + 2558 => x"38", + 2559 => x"70", + 2560 => x"33", + 2561 => x"2e", + 2562 => x"92", + 2563 => x"19", + 2564 => x"70", + 2565 => x"33", + 2566 => x"53", + 2567 => x"16", + 2568 => x"26", + 2569 => x"83", + 2570 => x"7c", + 2571 => x"05", + 2572 => x"05", + 2573 => x"5d", + 2574 => x"39", + 2575 => x"32", + 2576 => x"05", + 2577 => x"80", + 2578 => x"cc", + 2579 => x"81", + 2580 => x"07", + 2581 => x"07", + 2582 => x"51", + 2583 => x"80", + 2584 => x"79", + 2585 => x"70", + 2586 => x"33", + 2587 => x"80", + 2588 => x"38", + 2589 => x"e0", + 2590 => x"38", + 2591 => x"81", + 2592 => x"53", + 2593 => x"2e", + 2594 => x"73", + 2595 => x"a2", + 2596 => x"c3", + 2597 => x"38", + 2598 => x"24", + 2599 => x"80", + 2600 => x"8c", + 2601 => x"39", + 2602 => x"2e", + 2603 => x"81", + 2604 => x"80", + 2605 => x"80", + 2606 => x"d5", + 2607 => x"73", + 2608 => x"8e", + 2609 => x"39", + 2610 => x"2e", + 2611 => x"80", + 2612 => x"84", + 2613 => x"56", + 2614 => x"74", + 2615 => x"72", + 2616 => x"38", + 2617 => x"15", + 2618 => x"54", + 2619 => x"38", + 2620 => x"56", + 2621 => x"81", + 2622 => x"72", + 2623 => x"38", + 2624 => x"8a", + 2625 => x"06", + 2626 => x"2e", + 2627 => x"51", + 2628 => x"74", + 2629 => x"53", + 2630 => x"fd", + 2631 => x"51", + 2632 => x"ef", + 2633 => x"19", + 2634 => x"53", + 2635 => x"39", + 2636 => x"39", + 2637 => x"39", + 2638 => x"39", + 2639 => x"39", + 2640 => x"ca", + 2641 => x"39", + 2642 => x"70", + 2643 => x"53", + 2644 => x"88", + 2645 => x"19", + 2646 => x"39", + 2647 => x"54", + 2648 => x"74", + 2649 => x"70", + 2650 => x"70", + 2651 => x"25", + 2652 => x"55", + 2653 => x"8f", + 2654 => x"2e", + 2655 => x"09", + 2656 => x"90", + 2657 => x"80", + 2658 => x"5e", + 2659 => x"74", + 2660 => x"3f", + 2661 => x"08", + 2662 => x"7c", + 2663 => x"54", + 2664 => x"82", + 2665 => x"55", + 2666 => x"92", + 2667 => x"53", + 2668 => x"2e", + 2669 => x"14", + 2670 => x"ff", + 2671 => x"14", + 2672 => x"70", + 2673 => x"34", + 2674 => x"09", + 2675 => x"77", + 2676 => x"51", + 2677 => x"9f", + 2678 => x"72", + 2679 => x"79", + 2680 => x"81", + 2681 => x"72", + 2682 => x"38", + 2683 => x"05", + 2684 => x"ad", + 2685 => x"17", + 2686 => x"81", + 2687 => x"b0", + 2688 => x"38", + 2689 => x"81", + 2690 => x"06", + 2691 => x"9f", + 2692 => x"55", + 2693 => x"97", + 2694 => x"f9", + 2695 => x"81", + 2696 => x"8b", + 2697 => x"16", + 2698 => x"73", + 2699 => x"96", + 2700 => x"e0", + 2701 => x"17", + 2702 => x"33", + 2703 => x"f9", + 2704 => x"f2", + 2705 => x"16", + 2706 => x"7b", + 2707 => x"38", + 2708 => x"ba", + 2709 => x"96", + 2710 => x"fd", + 2711 => x"3d", + 2712 => x"05", + 2713 => x"52", + 2714 => x"d4", + 2715 => x"0d", + 2716 => x"0d", + 2717 => x"fc", + 2718 => x"88", + 2719 => x"51", + 2720 => x"82", + 2721 => x"53", + 2722 => x"80", + 2723 => x"fc", + 2724 => x"0d", + 2725 => x"0d", + 2726 => x"08", + 2727 => x"f4", + 2728 => x"88", + 2729 => x"52", + 2730 => x"3f", + 2731 => x"f4", + 2732 => x"0d", + 2733 => x"0d", + 2734 => x"9c", + 2735 => x"56", + 2736 => x"80", + 2737 => x"2e", + 2738 => x"82", + 2739 => x"52", + 2740 => x"85", + 2741 => x"ff", + 2742 => x"80", + 2743 => x"38", + 2744 => x"bc", + 2745 => x"32", + 2746 => x"05", + 2747 => x"51", + 2748 => x"80", + 2749 => x"71", + 2750 => x"38", + 2751 => x"98", + 2752 => x"25", + 2753 => x"16", + 2754 => x"25", + 2755 => x"74", + 2756 => x"72", + 2757 => x"54", + 2758 => x"f2", + 2759 => x"39", + 2760 => x"80", + 2761 => x"51", + 2762 => x"81", + 2763 => x"85", + 2764 => x"3d", + 2765 => x"3d", + 2766 => x"f8", + 2767 => x"9c", + 2768 => x"53", + 2769 => x"fe", + 2770 => x"82", + 2771 => x"84", + 2772 => x"f8", + 2773 => x"7c", + 2774 => x"70", + 2775 => x"75", + 2776 => x"55", + 2777 => x"2e", + 2778 => x"87", + 2779 => x"76", + 2780 => x"73", + 2781 => x"81", + 2782 => x"81", + 2783 => x"77", + 2784 => x"70", + 2785 => x"58", + 2786 => x"09", + 2787 => x"c2", + 2788 => x"81", + 2789 => x"75", + 2790 => x"55", + 2791 => x"e2", + 2792 => x"90", + 2793 => x"f8", + 2794 => x"8f", + 2795 => x"81", + 2796 => x"75", + 2797 => x"55", + 2798 => x"81", + 2799 => x"27", + 2800 => x"d0", + 2801 => x"55", + 2802 => x"73", + 2803 => x"80", + 2804 => x"14", + 2805 => x"72", + 2806 => x"ea", + 2807 => x"80", + 2808 => x"39", + 2809 => x"55", + 2810 => x"80", + 2811 => x"e0", + 2812 => x"38", + 2813 => x"81", + 2814 => x"53", + 2815 => x"81", + 2816 => x"53", + 2817 => x"8e", + 2818 => x"70", + 2819 => x"55", + 2820 => x"27", + 2821 => x"77", + 2822 => x"76", + 2823 => x"c4", + 2824 => x"85", + 2825 => x"76", + 2826 => x"77", + 2827 => x"70", + 2828 => x"55", + 2829 => x"77", + 2830 => x"38", + 2831 => x"05", + 2832 => x"0c", + 2833 => x"82", + 2834 => x"8a", + 2835 => x"f8", + 2836 => x"7c", + 2837 => x"70", + 2838 => x"75", + 2839 => x"55", + 2840 => x"2e", + 2841 => x"87", + 2842 => x"76", + 2843 => x"73", + 2844 => x"81", + 2845 => x"81", + 2846 => x"77", + 2847 => x"70", + 2848 => x"58", + 2849 => x"09", + 2850 => x"c2", + 2851 => x"81", + 2852 => x"75", + 2853 => x"55", + 2854 => x"e2", + 2855 => x"90", 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x"81", + 2915 => x"81", + 2916 => x"71", + 2917 => x"0c", + 2918 => x"04", + 2919 => x"78", + 2920 => x"9f", + 2921 => x"33", + 2922 => x"71", + 2923 => x"38", + 2924 => x"da", + 2925 => x"f2", + 2926 => x"51", + 2927 => x"72", + 2928 => x"52", + 2929 => x"71", + 2930 => x"52", + 2931 => x"51", + 2932 => x"73", + 2933 => x"3d", + 2934 => x"3d", + 2935 => x"84", + 2936 => x"33", + 2937 => x"bb", + 2938 => x"85", + 2939 => x"82", + 2940 => x"ec", + 2941 => x"59", + 2942 => x"59", + 2943 => x"86", + 2944 => x"9a", + 2945 => x"85", + 2946 => x"82", + 2947 => x"ec", + 2948 => x"70", + 2949 => x"56", + 2950 => x"3f", + 2951 => x"08", + 2952 => x"85", + 2953 => x"82", + 2954 => x"ec", + 2955 => x"56", + 2956 => x"2e", + 2957 => x"53", + 2958 => x"51", + 2959 => x"3f", + 2960 => x"33", + 2961 => x"74", + 2962 => x"34", + 2963 => x"06", + 2964 => x"27", + 2965 => x"0b", + 2966 => x"34", + 2967 => x"b6", + 2968 => x"c0", + 2969 => x"80", + 2970 => x"82", + 2971 => x"55", + 2972 => x"8c", + 2973 => x"54", + 2974 => x"52", + 2975 => x"d5", + 2976 => x"85", + 2977 => x"8a", + 2978 => x"cd", + 2979 => x"c0", + 2980 => x"d8", + 2981 => x"3d", + 2982 => x"3d", + 2983 => x"ec", + 2984 => x"72", + 2985 => x"80", + 2986 => x"71", + 2987 => x"3f", + 2988 => x"ff", + 2989 => x"54", + 2990 => x"25", + 2991 => x"0b", + 2992 => x"34", + 2993 => x"08", + 2994 => x"2e", + 2995 => x"51", + 2996 => x"3f", + 2997 => x"08", + 2998 => x"3f", + 2999 => x"85", + 3000 => x"3d", + 3001 => x"3d", + 3002 => x"80", + 3003 => x"c0", + 3004 => x"de", + 3005 => x"85", + 3006 => x"d2", + 3007 => x"c0", + 3008 => x"f8", + 3009 => x"70", + 3010 => x"87", + 3011 => x"85", + 3012 => x"2e", + 3013 => x"51", + 3014 => x"3f", + 3015 => x"08", + 3016 => x"82", + 3017 => x"25", + 3018 => x"85", + 3019 => x"05", + 3020 => x"55", + 3021 => x"75", + 3022 => x"81", + 3023 => x"e8", + 3024 => x"97", + 3025 => x"2e", + 3026 => x"ff", + 3027 => x"3d", + 3028 => x"3d", + 3029 => x"08", + 3030 => x"5a", + 3031 => x"58", + 3032 => x"82", + 3033 => x"51", + 3034 => x"3f", + 3035 => x"08", + 3036 => x"ff", + 3037 => x"c0", + 3038 => x"80", + 3039 => x"3d", + 3040 => x"81", + 3041 => x"82", + 3042 => x"80", + 3043 => x"75", + 3044 => x"a5", + 3045 => x"ec", + 3046 => x"58", + 3047 => x"82", + 3048 => x"25", + 3049 => x"85", + 3050 => x"05", + 3051 => x"55", + 3052 => x"74", + 3053 => x"81", + 3054 => x"07", + 3055 => x"55", + 3056 => x"2e", + 3057 => x"ff", + 3058 => x"85", + 3059 => x"11", + 3060 => x"80", + 3061 => x"82", + 3062 => x"80", + 3063 => x"81", + 3064 => x"ef", + 3065 => x"77", + 3066 => x"06", + 3067 => x"52", + 3068 => x"b4", + 3069 => x"51", + 3070 => x"3f", + 3071 => x"54", + 3072 => x"08", + 3073 => x"58", + 3074 => x"ec", + 3075 => x"0d", + 3076 => x"0d", + 3077 => x"5c", + 3078 => x"57", + 3079 => x"73", + 3080 => x"81", + 3081 => x"78", + 3082 => x"56", + 3083 => x"98", + 3084 => x"70", + 3085 => x"33", + 3086 => x"73", + 3087 => x"81", + 3088 => x"75", + 3089 => x"38", + 3090 => x"83", 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x"a0", + 3150 => x"3f", + 3151 => x"82", + 3152 => x"5b", + 3153 => x"08", + 3154 => x"52", + 3155 => x"52", + 3156 => x"ec", + 3157 => x"ec", + 3158 => x"85", + 3159 => x"2e", + 3160 => x"80", + 3161 => x"85", + 3162 => x"ff", + 3163 => x"82", + 3164 => x"55", + 3165 => x"85", + 3166 => x"a9", + 3167 => x"ec", + 3168 => x"70", + 3169 => x"80", + 3170 => x"53", + 3171 => x"06", + 3172 => x"f8", + 3173 => x"1b", + 3174 => x"06", + 3175 => x"7b", + 3176 => x"80", + 3177 => x"2e", + 3178 => x"ff", + 3179 => x"39", + 3180 => x"bc", + 3181 => x"38", + 3182 => x"08", + 3183 => x"38", + 3184 => x"8f", + 3185 => x"9c", + 3186 => x"ec", + 3187 => x"70", + 3188 => x"59", + 3189 => x"ee", + 3190 => x"ff", + 3191 => x"84", + 3192 => x"2b", + 3193 => x"82", + 3194 => x"70", + 3195 => x"97", + 3196 => x"2c", + 3197 => x"2b", + 3198 => x"11", + 3199 => x"33", + 3200 => x"51", + 3201 => x"59", + 3202 => x"56", + 3203 => x"80", + 3204 => x"74", + 3205 => x"ff", + 3206 => x"2b", + 3207 => x"51", + 3208 => x"75", + 3209 => x"38", + 3210 => x"52", + 3211 => x"9b", + 3212 => x"ec", + 3213 => x"06", + 3214 => x"2e", + 3215 => x"82", + 3216 => x"81", + 3217 => x"81", + 3218 => x"2b", + 3219 => x"70", + 3220 => x"53", + 3221 => x"73", + 3222 => x"38", + 3223 => x"52", + 3224 => x"e7", + 3225 => x"ec", + 3226 => x"06", + 3227 => x"38", + 3228 => x"56", + 3229 => x"80", + 3230 => x"1c", + 3231 => x"9d", + 3232 => x"98", + 3233 => x"2c", + 3234 => x"33", + 3235 => x"70", + 3236 => x"10", + 3237 => x"2b", + 3238 => x"11", + 3239 => x"53", + 3240 => x"51", + 3241 => x"2e", + 3242 => x"fe", + 3243 => x"fa", + 3244 => x"7d", + 3245 => x"82", + 3246 => x"80", + 3247 => x"80", + 3248 => x"75", + 3249 => x"34", + 3250 => x"80", + 3251 => x"3d", + 3252 => x"0c", + 3253 => x"95", + 3254 => x"38", + 3255 => x"54", + 3256 => x"14", + 3257 => x"9d", + 3258 => x"75", + 3259 => x"d3", + 3260 => x"88", + 3261 => x"74", + 3262 => x"73", + 3263 => x"98", + 3264 => x"75", + 3265 => x"38", + 3266 => x"73", + 3267 => x"34", + 3268 => x"98", + 3269 => x"2c", + 3270 => x"33", + 3271 => x"54", + 3272 => x"e4", + 3273 => x"8c", + 3274 => x"56", + 3275 => x"9d", + 3276 => x"1a", + 3277 => x"33", + 3278 => x"9d", + 3279 => x"73", + 3280 => x"38", + 3281 => x"73", + 3282 => x"34", + 3283 => x"33", + 3284 => x"98", + 3285 => x"2c", + 3286 => x"33", + 3287 => x"54", + 3288 => x"9f", + 3289 => x"70", + 3290 => x"e7", + 3291 => x"15", + 3292 => x"70", + 3293 => x"9d", + 3294 => x"51", + 3295 => x"75", + 3296 => x"82", + 3297 => x"70", + 3298 => x"98", + 3299 => x"88", + 3300 => x"56", + 3301 => x"25", + 3302 => x"88", + 3303 => x"3f", + 3304 => x"98", + 3305 => x"2c", + 3306 => x"33", + 3307 => x"54", + 3308 => x"e7", + 3309 => x"39", + 3310 => x"80", + 3311 => x"34", + 3312 => x"53", + 3313 => x"f3", + 3314 => x"d0", + 3315 => x"39", + 3316 => x"33", + 3317 => x"06", + 3318 => x"80", + 3319 => x"38", + 3320 => x"33", + 3321 => x"73", + 3322 => x"34", + 3323 => x"73", + 3324 => x"34", + 3325 => x"96", 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x"33", + 3385 => x"33", + 3386 => x"75", + 3387 => x"38", + 3388 => x"73", + 3389 => x"34", + 3390 => x"70", + 3391 => x"81", + 3392 => x"51", + 3393 => x"25", + 3394 => x"1a", + 3395 => x"33", + 3396 => x"33", + 3397 => x"3f", + 3398 => x"98", + 3399 => x"2c", + 3400 => x"33", + 3401 => x"54", + 3402 => x"de", + 3403 => x"e3", + 3404 => x"9d", + 3405 => x"98", + 3406 => x"2c", + 3407 => x"33", + 3408 => x"57", + 3409 => x"f8", + 3410 => x"51", + 3411 => x"81", + 3412 => x"2b", + 3413 => x"82", + 3414 => x"59", + 3415 => x"75", + 3416 => x"38", + 3417 => x"82", + 3418 => x"70", + 3419 => x"82", + 3420 => x"59", + 3421 => x"77", + 3422 => x"38", + 3423 => x"73", + 3424 => x"34", + 3425 => x"33", + 3426 => x"82", + 3427 => x"8c", + 3428 => x"ff", + 3429 => x"88", + 3430 => x"54", + 3431 => x"dc", + 3432 => x"39", + 3433 => x"53", + 3434 => x"f3", + 3435 => x"ec", + 3436 => x"82", + 3437 => x"80", + 3438 => x"88", + 3439 => x"39", + 3440 => x"82", + 3441 => x"55", + 3442 => x"a6", + 3443 => x"ff", + 3444 => x"82", + 3445 => x"82", + 3446 => x"82", + 3447 => x"81", + 3448 => x"05", + 3449 => x"79", + 3450 => x"ad", + 3451 => x"81", + 3452 => x"82", + 3453 => x"ec", + 3454 => x"08", + 3455 => x"74", + 3456 => x"38", + 3457 => x"a7", + 3458 => x"85", + 3459 => x"9d", + 3460 => x"85", + 3461 => x"ff", + 3462 => x"53", + 3463 => x"51", + 3464 => x"3f", + 3465 => x"80", + 3466 => x"08", + 3467 => x"2e", + 3468 => x"74", + 3469 => x"81", + 3470 => x"7a", + 3471 => x"81", + 3472 => x"82", + 3473 => x"55", + 3474 => x"a4", + 3475 => x"ff", + 3476 => x"82", + 3477 => x"82", + 3478 => x"82", + 3479 => x"81", + 3480 => x"05", + 3481 => x"79", + 3482 => x"ad", + 3483 => x"39", + 3484 => x"82", + 3485 => x"08", + 3486 => x"80", + 3487 => x"74", + 3488 => x"b5", + 3489 => x"ec", + 3490 => x"88", + 3491 => x"ec", + 3492 => x"06", + 3493 => x"74", + 3494 => x"ff", + 3495 => x"81", + 3496 => x"81", + 3497 => x"89", + 3498 => x"9d", + 3499 => x"7a", + 3500 => x"8c", + 3501 => x"88", + 3502 => x"51", + 3503 => x"f6", + 3504 => x"9d", + 3505 => x"81", + 3506 => x"9d", + 3507 => x"56", + 3508 => x"27", + 3509 => x"81", + 3510 => x"82", + 3511 => x"74", + 3512 => x"52", + 3513 => x"3f", + 3514 => x"82", + 3515 => x"54", + 3516 => x"f5", + 3517 => x"51", + 3518 => x"82", + 3519 => x"ff", + 3520 => x"82", + 3521 => x"f5", + 3522 => x"3d", + 3523 => x"f4", + 3524 => x"e4", + 3525 => x"0b", + 3526 => x"23", + 3527 => x"80", + 3528 => x"f4", + 3529 => x"c5", + 3530 => x"e4", + 3531 => x"58", + 3532 => x"81", + 3533 => x"15", + 3534 => x"e4", + 3535 => x"84", + 3536 => x"85", + 3537 => x"85", + 3538 => x"77", + 3539 => x"76", + 3540 => x"82", + 3541 => x"82", + 3542 => x"ff", + 3543 => x"80", + 3544 => x"ff", + 3545 => x"88", + 3546 => x"55", + 3547 => x"17", + 3548 => x"17", + 3549 => x"e0", + 3550 => x"2b", + 3551 => x"08", + 3552 => x"51", + 3553 => x"82", + 3554 => x"83", + 3555 => x"3d", + 3556 => x"3d", + 3557 => x"81", + 3558 => x"27", + 3559 => x"12", + 3560 => x"11", + 3561 => x"ff", + 3562 => x"51", + 3563 => x"ec", + 3564 => x"0d", + 3565 => x"0d", + 3566 => x"22", + 3567 => x"aa", + 3568 => x"05", + 3569 => x"08", + 3570 => x"71", + 3571 => x"2b", + 3572 => x"33", + 3573 => x"71", + 3574 => x"02", + 3575 => x"05", + 3576 => x"ff", + 3577 => x"70", + 3578 => x"51", + 3579 => x"5b", + 3580 => x"54", + 3581 => x"34", + 3582 => x"34", + 3583 => x"08", + 3584 => x"2a", + 3585 => x"82", + 3586 => x"83", + 3587 => x"85", + 3588 => x"17", + 3589 => x"12", + 3590 => x"2b", + 3591 => x"2b", + 3592 => x"06", + 3593 => x"52", + 3594 => x"83", + 3595 => x"70", + 3596 => x"54", + 3597 => x"12", + 3598 => x"ff", + 3599 => x"83", + 3600 => x"85", + 3601 => x"56", + 3602 => x"72", + 3603 => x"89", + 3604 => x"fb", + 3605 => x"85", + 3606 => x"84", + 3607 => x"22", + 3608 => x"72", + 3609 => x"33", + 3610 => x"71", + 3611 => x"83", + 3612 => x"5b", + 3613 => x"52", + 3614 => x"12", + 3615 => x"33", + 3616 => x"07", + 3617 => x"54", + 3618 => x"70", + 3619 => x"73", + 3620 => x"82", + 3621 => x"70", + 3622 => x"33", + 3623 => x"71", + 3624 => x"83", + 3625 => x"59", + 3626 => x"05", + 3627 => x"87", + 3628 => x"88", + 3629 => x"88", + 3630 => x"56", + 3631 => x"13", + 3632 => x"13", + 3633 => x"e4", + 3634 => x"33", + 3635 => x"71", + 3636 => x"70", + 3637 => x"06", + 3638 => x"53", + 3639 => x"53", + 3640 => x"70", + 3641 => x"87", + 3642 => x"f9", + 3643 => x"a6", + 3644 => x"85", + 3645 => x"83", + 3646 => x"70", + 3647 => x"33", + 3648 => x"07", + 3649 => x"53", + 3650 => x"58", + 3651 => x"33", + 3652 => x"71", + 3653 => x"90", + 3654 => x"5a", + 3655 => x"71", + 3656 => x"f6", + 3657 => x"fe", + 3658 => x"85", + 3659 => x"17", + 3660 => x"12", + 3661 => x"2b", + 3662 => x"07", + 3663 => x"33", + 3664 => x"71", + 3665 => x"70", + 3666 => x"ff", + 3667 => x"52", + 3668 => x"57", + 3669 => x"05", + 3670 => x"54", + 3671 => x"13", + 3672 => x"13", + 3673 => x"e4", + 3674 => x"70", + 3675 => x"33", + 3676 => x"71", + 3677 => x"56", + 3678 => x"72", + 3679 => x"81", + 3680 => x"88", + 3681 => x"81", + 3682 => x"70", + 3683 => x"51", + 3684 => x"72", + 3685 => x"81", + 3686 => x"3d", + 3687 => x"3d", + 3688 => x"e4", + 3689 => x"05", + 3690 => x"70", + 3691 => x"11", + 3692 => x"83", + 3693 => x"8b", + 3694 => x"2b", + 3695 => x"59", + 3696 => x"73", + 3697 => x"81", + 3698 => x"88", + 3699 => x"8c", + 3700 => x"22", + 3701 => x"88", + 3702 => x"53", + 3703 => x"73", + 3704 => x"14", + 3705 => x"e4", + 3706 => x"70", + 3707 => x"33", + 3708 => x"71", + 3709 => x"56", + 3710 => x"72", + 3711 => x"33", + 3712 => x"71", + 3713 => x"70", + 3714 => x"55", + 3715 => x"82", + 3716 => x"83", + 3717 => x"85", + 3718 => x"82", + 3719 => x"12", + 3720 => x"2b", + 3721 => x"ec", + 3722 => x"87", + 3723 => x"f7", + 3724 => x"82", + 3725 => x"31", + 3726 => x"83", + 3727 => x"70", + 3728 => x"fd", + 3729 => x"85", + 3730 => x"83", + 3731 => x"82", + 3732 => x"12", + 3733 => x"2b", + 3734 => x"07", + 3735 => x"33", + 3736 => x"71", + 3737 => x"90", + 3738 => x"42", + 3739 => x"5b", + 3740 => x"54", + 3741 => x"8d", + 3742 => x"80", + 3743 => x"fe", + 3744 => x"84", + 3745 => x"33", + 3746 => x"71", + 3747 => x"83", + 3748 => x"11", + 3749 => x"53", + 3750 => x"55", + 3751 => x"34", + 3752 => x"06", + 3753 => x"14", + 3754 => x"e4", + 3755 => x"84", + 3756 => x"13", + 3757 => x"2b", + 3758 => x"2a", + 3759 => x"56", + 3760 => x"16", + 3761 => x"16", + 3762 => x"e4", + 3763 => x"80", + 3764 => x"34", + 3765 => x"14", + 3766 => x"e4", + 3767 => x"84", + 3768 => x"85", + 3769 => x"85", + 3770 => x"70", + 3771 => x"33", + 3772 => x"07", + 3773 => x"80", + 3774 => x"2a", + 3775 => x"56", + 3776 => x"34", + 3777 => x"34", + 3778 => x"04", + 3779 => x"73", + 3780 => x"e4", + 3781 => x"f7", + 3782 => x"80", + 3783 => x"71", + 3784 => x"3f", + 3785 => x"04", + 3786 => x"80", + 3787 => x"f8", + 3788 => x"85", + 3789 => x"ff", + 3790 => x"85", + 3791 => x"11", + 3792 => x"33", + 3793 => x"07", + 3794 => x"56", + 3795 => x"ff", + 3796 => x"78", + 3797 => x"38", + 3798 => x"77", + 3799 => x"81", + 3800 => x"88", + 3801 => x"81", + 3802 => x"79", + 3803 => x"ff", + 3804 => x"7f", + 3805 => x"51", + 3806 => x"77", + 3807 => x"38", + 3808 => x"85", + 3809 => x"5a", + 3810 => x"33", + 3811 => x"71", + 3812 => x"57", + 3813 => x"38", + 3814 => x"ff", + 3815 => x"7a", + 3816 => x"80", + 3817 => x"82", + 3818 => x"11", + 3819 => x"12", + 3820 => x"2b", + 3821 => x"ff", + 3822 => x"52", + 3823 => x"55", + 3824 => x"83", + 3825 => x"80", + 3826 => x"26", + 3827 => x"74", + 3828 => x"2e", + 3829 => x"77", + 3830 => x"81", + 3831 => x"75", + 3832 => x"3f", + 3833 => x"82", + 3834 => x"79", + 3835 => x"f7", + 3836 => x"85", + 3837 => x"1c", + 3838 => x"87", + 3839 => x"8b", + 3840 => x"2b", + 3841 => x"5e", + 3842 => x"7a", + 3843 => x"ff", + 3844 => x"88", + 3845 => x"56", + 3846 => x"15", + 3847 => x"ff", + 3848 => x"85", + 3849 => x"85", + 3850 => x"83", + 3851 => x"72", + 3852 => x"33", + 3853 => x"71", + 3854 => x"70", + 3855 => x"5b", + 3856 => x"56", + 3857 => x"19", + 3858 => x"19", + 3859 => x"e4", + 3860 => x"84", + 3861 => x"12", + 3862 => x"2b", + 3863 => x"07", + 3864 => x"55", + 3865 => x"78", + 3866 => x"76", + 3867 => x"82", + 3868 => x"70", + 3869 => x"84", + 3870 => x"12", + 3871 => x"2b", + 3872 => x"2a", + 3873 => x"52", + 3874 => x"84", + 3875 => x"85", + 3876 => x"85", + 3877 => x"84", + 3878 => x"82", + 3879 => x"8d", + 3880 => x"fe", + 3881 => x"52", + 3882 => x"08", + 3883 => x"da", + 3884 => x"71", + 3885 => x"38", + 3886 => x"ec", + 3887 => x"ec", + 3888 => x"82", + 3889 => x"84", + 3890 => x"ff", + 3891 => x"8f", + 3892 => x"81", + 3893 => x"26", + 3894 => x"85", + 3895 => x"52", + 3896 => x"ec", + 3897 => x"0d", + 3898 => x"0d", + 3899 => x"33", + 3900 => x"9f", + 3901 => x"53", + 3902 => x"81", + 3903 => x"38", + 3904 => x"87", + 3905 => x"11", + 3906 => x"54", + 3907 => x"84", + 3908 => x"54", + 3909 => x"87", + 3910 => x"11", + 3911 => x"0c", + 3912 => x"c0", + 3913 => x"70", + 3914 => x"70", + 3915 => x"51", + 3916 => x"8a", + 3917 => x"98", + 3918 => x"70", + 3919 => x"08", + 3920 => x"06", + 3921 => x"38", + 3922 => x"8c", + 3923 => x"80", + 3924 => x"71", + 3925 => x"14", + 3926 => x"e8", + 3927 => x"70", + 3928 => x"0c", + 3929 => x"04", + 3930 => x"60", + 3931 => x"8c", + 3932 => x"33", + 3933 => x"5b", + 3934 => x"5a", + 3935 => x"82", + 3936 => x"81", + 3937 => x"52", + 3938 => x"38", + 3939 => x"84", + 3940 => x"92", + 3941 => x"c0", + 3942 => x"87", + 3943 => x"13", + 3944 => x"57", + 3945 => x"0b", + 3946 => x"8c", + 3947 => x"0c", + 3948 => x"75", + 3949 => x"2a", + 3950 => x"51", + 3951 => x"80", + 3952 => x"7b", + 3953 => x"7b", + 3954 => x"5d", + 3955 => x"59", + 3956 => x"06", + 3957 => x"73", + 3958 => x"81", + 3959 => x"ff", + 3960 => x"72", + 3961 => x"38", + 3962 => x"8c", + 3963 => x"c3", + 3964 => x"98", + 3965 => x"71", + 3966 => x"38", + 3967 => x"2e", + 3968 => x"76", + 3969 => x"92", + 3970 => x"72", + 3971 => x"06", + 3972 => x"f7", + 3973 => x"5a", + 3974 => x"80", + 3975 => x"70", + 3976 => x"5a", + 3977 => x"80", + 3978 => x"73", + 3979 => x"06", + 3980 => x"38", + 3981 => x"fe", + 3982 => x"fc", + 3983 => x"52", + 3984 => x"83", + 3985 => x"71", + 3986 => x"85", + 3987 => x"3d", + 3988 => x"3d", + 3989 => x"64", + 3990 => x"bf", + 3991 => x"40", + 3992 => x"59", + 3993 => x"58", + 3994 => x"82", + 3995 => x"81", + 3996 => x"52", + 3997 => x"09", + 3998 => x"b1", + 3999 => x"84", + 4000 => x"92", + 4001 => x"c0", + 4002 => x"87", + 4003 => x"13", + 4004 => x"56", + 4005 => x"87", + 4006 => x"0c", + 4007 => x"82", + 4008 => x"58", + 4009 => x"84", + 4010 => x"06", + 4011 => x"71", + 4012 => x"38", + 4013 => x"05", + 4014 => x"0c", + 4015 => x"73", + 4016 => x"81", + 4017 => x"71", + 4018 => x"38", + 4019 => x"8c", + 4020 => x"d0", + 4021 => x"98", + 4022 => x"71", + 4023 => x"38", + 4024 => x"2e", + 4025 => x"76", + 4026 => x"92", + 4027 => x"72", + 4028 => x"06", + 4029 => x"f7", + 4030 => x"59", + 4031 => x"1a", + 4032 => x"06", + 4033 => x"59", + 4034 => x"80", + 4035 => x"73", + 4036 => x"06", + 4037 => x"38", + 4038 => x"fe", + 4039 => x"fc", + 4040 => x"52", + 4041 => x"83", + 4042 => x"71", + 4043 => x"85", + 4044 => x"3d", + 4045 => x"3d", + 4046 => x"84", + 4047 => x"33", + 4048 => x"a7", + 4049 => x"54", + 4050 => x"fa", + 4051 => x"85", + 4052 => x"06", + 4053 => x"72", + 4054 => x"85", + 4055 => x"98", + 4056 => x"56", + 4057 => x"80", + 4058 => x"76", + 4059 => x"74", + 4060 => x"c0", + 4061 => x"54", + 4062 => x"2e", + 4063 => x"d4", + 4064 => x"2e", + 4065 => x"80", + 4066 => x"08", + 4067 => x"70", + 4068 => x"51", + 4069 => x"2e", + 4070 => x"c0", + 4071 => x"52", + 4072 => x"87", + 4073 => x"08", + 4074 => x"38", + 4075 => x"87", + 4076 => x"14", + 4077 => x"70", + 4078 => x"52", + 4079 => x"96", + 4080 => x"92", + 4081 => x"0a", + 4082 => x"39", + 4083 => x"0c", + 4084 => x"39", + 4085 => x"54", + 4086 => x"ec", + 4087 => x"0d", + 4088 => x"0d", + 4089 => x"33", + 4090 => x"88", + 4091 => x"85", + 4092 => x"51", + 4093 => x"04", + 4094 => x"75", + 4095 => x"82", + 4096 => x"90", + 4097 => x"2b", + 4098 => x"33", + 4099 => x"88", + 4100 => x"71", + 4101 => x"ec", + 4102 => x"54", + 4103 => x"85", + 4104 => x"ff", + 4105 => x"02", + 4106 => x"05", + 4107 => x"70", + 4108 => x"05", + 4109 => x"88", + 4110 => x"72", + 4111 => x"0d", + 4112 => x"0d", + 4113 => x"52", + 4114 => x"81", + 4115 => x"70", + 4116 => x"70", + 4117 => x"05", + 4118 => x"88", + 4119 => x"72", + 4120 => x"54", + 4121 => x"2a", + 4122 => x"34", + 4123 => x"04", + 4124 => x"76", + 4125 => x"54", + 4126 => x"2e", + 4127 => x"70", + 4128 => x"33", + 4129 => x"05", + 4130 => x"11", + 4131 => x"84", + 4132 => x"fe", + 4133 => x"77", + 4134 => x"53", + 4135 => x"81", + 4136 => x"ff", + 4137 => x"f4", + 4138 => x"0d", + 4139 => x"0d", + 4140 => x"56", + 4141 => x"70", + 4142 => x"33", + 4143 => x"05", + 4144 => x"71", + 4145 => x"56", + 4146 => x"72", + 4147 => x"38", + 4148 => x"e2", + 4149 => x"85", + 4150 => x"3d", + 4151 => x"3d", + 4152 => x"54", + 4153 => x"71", + 4154 => x"38", + 4155 => x"70", + 4156 => x"f3", + 4157 => x"82", + 4158 => x"84", + 4159 => x"80", + 4160 => x"ec", + 4161 => x"0b", + 4162 => x"0c", + 4163 => x"0d", + 4164 => x"0b", + 4165 => x"56", + 4166 => x"2e", + 4167 => x"81", + 4168 => x"08", + 4169 => x"70", + 4170 => x"33", + 4171 => x"a2", + 4172 => x"ec", + 4173 => x"09", + 4174 => x"38", + 4175 => x"08", + 4176 => x"b0", + 4177 => x"a4", + 4178 => x"9c", + 4179 => x"56", + 4180 => x"27", + 4181 => x"16", + 4182 => x"82", + 4183 => x"06", + 4184 => x"54", + 4185 => x"78", + 4186 => x"33", + 4187 => x"3f", + 4188 => x"5a", + 4189 => x"ec", + 4190 => x"0d", + 4191 => x"0d", + 4192 => x"56", + 4193 => x"b0", + 4194 => x"af", + 4195 => x"fe", + 4196 => x"85", + 4197 => x"82", + 4198 => x"9f", + 4199 => x"74", + 4200 => x"52", + 4201 => x"51", + 4202 => x"82", + 4203 => x"80", + 4204 => x"ff", + 4205 => x"74", + 4206 => x"76", + 4207 => x"0c", + 4208 => x"04", + 4209 => x"7a", + 4210 => x"fe", + 4211 => x"85", + 4212 => x"82", + 4213 => x"81", + 4214 => x"33", + 4215 => x"2e", + 4216 => x"80", + 4217 => x"17", + 4218 => x"81", + 4219 => x"06", + 4220 => x"84", + 4221 => x"85", + 4222 => x"b4", + 4223 => x"56", + 4224 => x"82", + 4225 => x"84", + 4226 => x"fc", + 4227 => x"8b", + 4228 => x"52", + 4229 => x"a9", + 4230 => x"85", + 4231 => x"84", + 4232 => x"fc", + 4233 => x"17", + 4234 => x"9c", + 4235 => x"91", + 4236 => x"08", + 4237 => x"17", + 4238 => x"3f", + 4239 => x"81", + 4240 => x"19", + 4241 => x"53", + 4242 => x"17", + 4243 => x"82", + 4244 => x"18", + 4245 => x"80", + 4246 => x"33", + 4247 => x"3f", + 4248 => x"08", + 4249 => x"38", + 4250 => x"82", + 4251 => x"8a", + 4252 => x"fb", + 4253 => x"fe", + 4254 => x"08", + 4255 => x"55", + 4256 => x"73", + 4257 => x"38", + 4258 => x"74", + 4259 => x"97", + 4260 => x"15", + 4261 => x"ec", + 4262 => x"75", + 4263 => x"0c", + 4264 => x"04", + 4265 => x"7a", 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x"58", + 4325 => x"ec", + 4326 => x"0d", + 4327 => x"0d", + 4328 => x"5a", + 4329 => x"59", + 4330 => x"82", + 4331 => x"98", + 4332 => x"82", + 4333 => x"33", + 4334 => x"2e", + 4335 => x"72", + 4336 => x"38", + 4337 => x"8d", + 4338 => x"39", + 4339 => x"81", + 4340 => x"f7", + 4341 => x"2a", + 4342 => x"2a", + 4343 => x"05", + 4344 => x"55", + 4345 => x"82", + 4346 => x"59", + 4347 => x"08", + 4348 => x"74", + 4349 => x"16", + 4350 => x"16", + 4351 => x"59", + 4352 => x"53", + 4353 => x"8f", + 4354 => x"2b", + 4355 => x"74", + 4356 => x"71", + 4357 => x"72", + 4358 => x"0b", + 4359 => x"74", + 4360 => x"17", + 4361 => x"75", + 4362 => x"3f", + 4363 => x"08", + 4364 => x"ec", + 4365 => x"38", + 4366 => x"06", + 4367 => x"78", + 4368 => x"54", + 4369 => x"77", + 4370 => x"33", + 4371 => x"71", + 4372 => x"51", + 4373 => x"34", + 4374 => x"76", + 4375 => x"17", + 4376 => x"75", + 4377 => x"3f", + 4378 => x"08", + 4379 => x"ec", + 4380 => x"38", + 4381 => x"ff", + 4382 => x"10", + 4383 => x"76", + 4384 => x"51", + 4385 => x"be", + 4386 => x"2a", + 4387 => x"05", + 4388 => x"f9", + 4389 => x"85", + 4390 => x"82", + 4391 => x"ab", + 4392 => x"0a", + 4393 => x"2b", + 4394 => x"70", + 4395 => x"70", + 4396 => x"54", + 4397 => x"82", + 4398 => x"8f", + 4399 => x"07", + 4400 => x"f6", + 4401 => x"0b", + 4402 => x"78", + 4403 => x"0c", + 4404 => x"04", + 4405 => x"7a", + 4406 => x"08", + 4407 => x"59", + 4408 => x"a4", + 4409 => x"17", + 4410 => x"38", + 4411 => x"aa", + 4412 => x"73", + 4413 => x"fd", + 4414 => x"85", + 4415 => x"82", + 4416 => x"80", + 4417 => x"39", + 4418 => x"eb", + 4419 => x"80", + 4420 => x"85", + 4421 => x"80", + 4422 => x"52", + 4423 => x"84", + 4424 => x"ec", + 4425 => x"85", + 4426 => x"2e", + 4427 => x"82", + 4428 => x"81", + 4429 => x"82", + 4430 => x"ff", + 4431 => x"80", + 4432 => x"75", + 4433 => x"3f", + 4434 => x"08", + 4435 => x"16", + 4436 => x"90", + 4437 => x"55", + 4438 => x"27", + 4439 => x"15", + 4440 => x"84", + 4441 => x"07", + 4442 => x"17", + 4443 => x"76", + 4444 => x"a6", + 4445 => x"73", + 4446 => x"0c", + 4447 => x"04", + 4448 => x"7c", + 4449 => x"59", + 4450 => x"95", + 4451 => x"08", + 4452 => x"2e", + 4453 => x"17", + 4454 => x"b2", + 4455 => x"ae", + 4456 => x"7a", + 4457 => x"3f", + 4458 => x"82", + 4459 => x"27", + 4460 => x"82", + 4461 => x"55", + 4462 => x"08", + 4463 => x"d8", + 4464 => x"08", + 4465 => x"08", + 4466 => x"38", + 4467 => x"17", + 4468 => x"54", + 4469 => x"82", + 4470 => x"7a", + 4471 => x"06", + 4472 => x"81", + 4473 => x"17", + 4474 => x"83", + 4475 => x"75", + 4476 => x"f9", + 4477 => x"59", + 4478 => x"08", + 4479 => x"81", + 4480 => x"82", + 4481 => x"59", + 4482 => x"08", + 4483 => x"81", + 4484 => x"07", + 4485 => x"7c", + 4486 => x"ec", + 4487 => x"51", + 4488 => x"81", + 4489 => x"85", + 4490 => x"2e", + 4491 => x"17", + 4492 => x"74", + 4493 => x"73", + 4494 => x"27", + 4495 => x"58", + 4496 => x"80", + 4497 => x"56", + 4498 => x"98", + 4499 => x"26", + 4500 => x"56", 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x"3f", + 4560 => x"08", + 4561 => x"08", + 4562 => x"59", + 4563 => x"77", + 4564 => x"70", + 4565 => x"bb", + 4566 => x"84", + 4567 => x"56", + 4568 => x"58", + 4569 => x"97", + 4570 => x"75", + 4571 => x"52", + 4572 => x"51", + 4573 => x"82", + 4574 => x"80", + 4575 => x"8a", + 4576 => x"32", + 4577 => x"05", + 4578 => x"70", + 4579 => x"51", + 4580 => x"82", + 4581 => x"8a", + 4582 => x"f8", + 4583 => x"7c", + 4584 => x"56", + 4585 => x"80", + 4586 => x"f1", + 4587 => x"06", + 4588 => x"e9", + 4589 => x"18", + 4590 => x"08", + 4591 => x"38", + 4592 => x"82", + 4593 => x"38", + 4594 => x"54", + 4595 => x"74", + 4596 => x"82", + 4597 => x"22", + 4598 => x"79", + 4599 => x"38", + 4600 => x"98", + 4601 => x"cd", + 4602 => x"22", + 4603 => x"54", + 4604 => x"26", + 4605 => x"52", + 4606 => x"a8", + 4607 => x"ec", + 4608 => x"85", + 4609 => x"2e", + 4610 => x"0b", + 4611 => x"08", + 4612 => x"98", + 4613 => x"85", + 4614 => x"85", + 4615 => x"bd", + 4616 => x"31", + 4617 => x"73", + 4618 => x"f4", + 4619 => x"85", + 4620 => x"18", + 4621 => x"18", + 4622 => x"08", + 4623 => x"72", + 4624 => x"38", + 4625 => x"58", + 4626 => x"89", + 4627 => x"18", + 4628 => x"ff", + 4629 => x"05", + 4630 => x"80", + 4631 => x"85", + 4632 => x"3d", + 4633 => x"3d", + 4634 => x"08", + 4635 => x"a0", + 4636 => x"54", + 4637 => x"77", + 4638 => x"80", + 4639 => x"0c", + 4640 => x"53", + 4641 => x"80", + 4642 => x"38", + 4643 => x"06", + 4644 => x"b5", + 4645 => x"98", + 4646 => x"14", + 4647 => x"92", + 4648 => x"2a", + 4649 => x"56", + 4650 => x"26", + 4651 => x"80", + 4652 => x"16", + 4653 => x"77", + 4654 => x"53", + 4655 => x"38", + 4656 => x"51", + 4657 => x"82", + 4658 => x"53", + 4659 => x"0b", + 4660 => x"08", + 4661 => x"38", + 4662 => x"85", + 4663 => x"2e", + 4664 => x"98", + 4665 => x"85", + 4666 => x"80", + 4667 => x"8a", + 4668 => x"15", + 4669 => x"80", + 4670 => x"14", + 4671 => x"51", + 4672 => x"82", + 4673 => x"53", + 4674 => x"85", + 4675 => x"2e", + 4676 => x"82", + 4677 => x"ec", + 4678 => x"ba", + 4679 => x"82", + 4680 => x"ff", + 4681 => x"82", + 4682 => x"52", + 4683 => x"f1", + 4684 => x"ec", + 4685 => x"72", + 4686 => x"72", + 4687 => x"f2", + 4688 => x"85", + 4689 => x"15", + 4690 => x"15", + 4691 => x"b4", + 4692 => x"0c", + 4693 => x"82", + 4694 => x"8a", + 4695 => x"f7", + 4696 => x"7d", + 4697 => x"5b", + 4698 => x"76", + 4699 => x"3f", + 4700 => x"08", + 4701 => x"ec", + 4702 => x"38", + 4703 => x"08", + 4704 => x"08", + 4705 => x"ef", + 4706 => x"85", + 4707 => x"82", + 4708 => x"80", + 4709 => x"85", + 4710 => x"18", + 4711 => x"51", + 4712 => x"81", + 4713 => x"81", + 4714 => x"81", + 4715 => x"ec", + 4716 => x"83", + 4717 => x"77", + 4718 => x"72", + 4719 => x"38", + 4720 => x"75", + 4721 => x"81", + 4722 => x"a5", + 4723 => x"ec", + 4724 => x"52", + 4725 => x"8e", + 4726 => x"ec", + 4727 => x"85", + 4728 => x"2e", + 4729 => x"73", + 4730 => x"81", + 4731 => x"87", + 4732 => x"85", + 4733 => x"3d", + 4734 => x"3d", + 4735 => x"11", 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x"82", + 4795 => x"58", + 4796 => x"08", + 4797 => x"15", + 4798 => x"38", + 4799 => x"0b", + 4800 => x"77", + 4801 => x"0c", + 4802 => x"04", + 4803 => x"77", + 4804 => x"54", + 4805 => x"51", + 4806 => x"82", + 4807 => x"55", + 4808 => x"08", + 4809 => x"14", + 4810 => x"51", + 4811 => x"82", + 4812 => x"55", + 4813 => x"08", + 4814 => x"53", + 4815 => x"08", + 4816 => x"08", + 4817 => x"3f", + 4818 => x"14", + 4819 => x"08", + 4820 => x"3f", + 4821 => x"17", + 4822 => x"85", + 4823 => x"3d", + 4824 => x"3d", + 4825 => x"08", + 4826 => x"54", + 4827 => x"53", + 4828 => x"82", + 4829 => x"8d", + 4830 => x"08", + 4831 => x"34", + 4832 => x"15", + 4833 => x"0d", + 4834 => x"0d", + 4835 => x"57", + 4836 => x"17", + 4837 => x"08", + 4838 => x"82", + 4839 => x"89", + 4840 => x"55", + 4841 => x"14", + 4842 => x"16", + 4843 => x"71", + 4844 => x"38", + 4845 => x"09", + 4846 => x"38", + 4847 => x"73", + 4848 => x"81", + 4849 => x"ae", + 4850 => x"05", + 4851 => x"15", + 4852 => x"70", + 4853 => x"34", + 4854 => x"8a", + 4855 => x"38", + 4856 => x"05", + 4857 => x"81", + 4858 => x"17", + 4859 => x"12", + 4860 => x"34", + 4861 => x"9c", + 4862 => x"e7", + 4863 => x"85", + 4864 => x"0c", + 4865 => x"e7", + 4866 => x"85", + 4867 => x"17", + 4868 => x"51", + 4869 => x"82", + 4870 => x"84", + 4871 => x"3d", + 4872 => x"3d", + 4873 => x"08", + 4874 => x"61", + 4875 => x"55", + 4876 => x"2e", + 4877 => x"55", + 4878 => x"2e", + 4879 => x"80", + 4880 => x"94", + 4881 => x"1c", + 4882 => x"81", + 4883 => x"61", + 4884 => x"56", + 4885 => x"2e", + 4886 => x"83", + 4887 => x"73", + 4888 => x"70", + 4889 => x"70", + 4890 => x"07", + 4891 => x"73", + 4892 => x"88", + 4893 => x"70", + 4894 => x"73", + 4895 => x"38", + 4896 => x"ab", + 4897 => x"52", + 4898 => x"8f", + 4899 => x"ec", + 4900 => x"a6", + 4901 => x"61", + 4902 => x"5a", + 4903 => x"a0", + 4904 => x"e7", + 4905 => x"70", + 4906 => x"79", + 4907 => x"73", + 4908 => x"81", + 4909 => x"38", + 4910 => x"33", + 4911 => x"ae", + 4912 => x"81", + 4913 => x"2a", + 4914 => x"07", + 4915 => x"5a", + 4916 => x"8c", + 4917 => x"54", + 4918 => x"81", + 4919 => x"39", + 4920 => x"70", + 4921 => x"70", + 4922 => x"51", + 4923 => x"dc", + 4924 => x"73", + 4925 => x"38", + 4926 => x"82", + 4927 => x"19", + 4928 => x"54", + 4929 => x"82", + 4930 => x"54", + 4931 => x"78", + 4932 => x"81", + 4933 => x"54", + 4934 => x"82", + 4935 => x"af", + 4936 => x"81", + 4937 => x"dc", + 4938 => x"81", + 4939 => x"25", + 4940 => x"07", + 4941 => x"51", + 4942 => x"2e", + 4943 => x"39", + 4944 => x"80", + 4945 => x"33", + 4946 => x"73", + 4947 => x"81", + 4948 => x"81", + 4949 => x"dc", + 4950 => x"81", + 4951 => x"25", + 4952 => x"51", + 4953 => x"38", + 4954 => x"75", + 4955 => x"81", + 4956 => x"81", + 4957 => x"27", + 4958 => x"73", + 4959 => x"38", + 4960 => x"70", + 4961 => x"77", + 4962 => x"09", + 4963 => x"80", + 4964 => x"2a", + 4965 => x"56", + 4966 => x"81", + 4967 => x"57", + 4968 => x"eb", + 4969 => x"2b", + 4970 => x"25", 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x"15", + 5030 => x"2a", + 5031 => x"51", + 5032 => x"92", + 5033 => x"79", + 5034 => x"e4", + 5035 => x"85", + 5036 => x"2e", + 5037 => x"52", + 5038 => x"aa", + 5039 => x"39", + 5040 => x"33", + 5041 => x"80", + 5042 => x"74", + 5043 => x"81", + 5044 => x"38", + 5045 => x"70", + 5046 => x"82", + 5047 => x"54", + 5048 => x"96", + 5049 => x"06", + 5050 => x"2e", + 5051 => x"ff", + 5052 => x"1c", + 5053 => x"80", + 5054 => x"81", + 5055 => x"ba", + 5056 => x"b6", + 5057 => x"2a", + 5058 => x"51", + 5059 => x"38", + 5060 => x"70", + 5061 => x"81", + 5062 => x"55", + 5063 => x"e1", + 5064 => x"08", + 5065 => x"1d", + 5066 => x"7c", + 5067 => x"3f", + 5068 => x"08", + 5069 => x"fa", + 5070 => x"82", + 5071 => x"8f", + 5072 => x"f6", + 5073 => x"5b", + 5074 => x"70", + 5075 => x"59", + 5076 => x"73", + 5077 => x"cc", + 5078 => x"81", + 5079 => x"70", + 5080 => x"52", + 5081 => x"8d", + 5082 => x"38", + 5083 => x"09", + 5084 => x"ab", + 5085 => x"d0", + 5086 => x"ff", + 5087 => x"53", + 5088 => x"91", + 5089 => x"73", + 5090 => x"d0", + 5091 => x"71", + 5092 => x"fd", + 5093 => x"81", + 5094 => x"55", + 5095 => x"55", + 5096 => x"81", + 5097 => x"74", + 5098 => x"56", + 5099 => x"12", + 5100 => x"70", + 5101 => x"38", + 5102 => x"81", + 5103 => x"51", + 5104 => x"51", + 5105 => x"89", + 5106 => x"70", + 5107 => x"53", + 5108 => x"81", + 5109 => x"2a", + 5110 => x"72", + 5111 => x"06", + 5112 => x"ff", + 5113 => x"09", + 5114 => x"77", + 5115 => x"81", + 5116 => x"07", + 5117 => x"9f", + 5118 => x"54", + 5119 => x"80", + 5120 => x"81", + 5121 => x"59", + 5122 => x"25", + 5123 => x"8b", + 5124 => x"24", + 5125 => x"76", + 5126 => x"78", + 5127 => x"82", + 5128 => x"51", + 5129 => x"ec", + 5130 => x"0d", + 5131 => x"0d", + 5132 => x"0b", + 5133 => x"ff", + 5134 => x"0c", + 5135 => x"51", + 5136 => x"84", + 5137 => x"ec", + 5138 => x"38", + 5139 => x"51", + 5140 => x"82", + 5141 => x"83", + 5142 => x"54", + 5143 => x"82", + 5144 => x"09", + 5145 => x"e5", + 5146 => x"b4", + 5147 => x"57", + 5148 => x"2e", + 5149 => x"83", + 5150 => x"74", + 5151 => x"70", + 5152 => x"70", + 5153 => x"07", + 5154 => x"73", + 5155 => x"81", + 5156 => x"81", + 5157 => x"83", + 5158 => x"e4", + 5159 => x"16", + 5160 => x"3f", + 5161 => x"08", + 5162 => x"ec", + 5163 => x"9d", + 5164 => x"81", + 5165 => x"81", + 5166 => x"df", + 5167 => x"85", + 5168 => x"82", + 5169 => x"80", + 5170 => x"82", + 5171 => x"85", + 5172 => x"3d", + 5173 => x"3d", + 5174 => x"84", + 5175 => x"05", + 5176 => x"80", + 5177 => x"51", + 5178 => x"82", + 5179 => x"58", + 5180 => x"0b", + 5181 => x"08", + 5182 => x"38", + 5183 => x"08", + 5184 => x"9d", + 5185 => x"55", + 5186 => x"73", + 5187 => x"ee", + 5188 => x"0c", + 5189 => x"06", + 5190 => x"57", + 5191 => x"ae", + 5192 => x"33", + 5193 => x"3f", + 5194 => x"08", + 5195 => x"70", + 5196 => x"55", + 5197 => x"76", + 5198 => x"c0", + 5199 => x"2a", + 5200 => x"51", + 5201 => x"72", + 5202 => x"86", + 5203 => x"74", + 5204 => x"15", + 5205 => x"81", + 5206 => x"d7", + 5207 => x"85", + 5208 => x"ff", + 5209 => x"06", + 5210 => x"56", + 5211 => x"38", + 5212 => x"8f", + 5213 => x"2a", + 5214 => x"51", + 5215 => x"72", + 5216 => x"80", + 5217 => x"52", + 5218 => x"3f", + 5219 => x"08", + 5220 => x"57", + 5221 => x"09", + 5222 => x"e2", + 5223 => x"74", + 5224 => x"56", + 5225 => x"33", + 5226 => x"72", + 5227 => x"38", + 5228 => x"51", + 5229 => x"82", + 5230 => x"57", + 5231 => x"84", + 5232 => x"ff", + 5233 => x"56", + 5234 => x"25", + 5235 => x"0b", + 5236 => x"56", + 5237 => x"05", + 5238 => x"83", + 5239 => x"2e", + 5240 => x"52", + 5241 => x"c5", + 5242 => x"ec", + 5243 => x"06", + 5244 => x"27", + 5245 => x"16", + 5246 => x"27", + 5247 => x"56", + 5248 => x"84", + 5249 => x"56", + 5250 => x"84", + 5251 => x"14", + 5252 => x"3f", + 5253 => x"08", + 5254 => x"06", + 5255 => x"80", + 5256 => x"06", + 5257 => x"80", + 5258 => x"db", + 5259 => x"85", + 5260 => x"ff", + 5261 => x"77", + 5262 => x"d8", + 5263 => x"b8", + 5264 => x"ec", + 5265 => x"9c", + 5266 => x"c4", + 5267 => x"15", + 5268 => x"14", + 5269 => x"70", + 5270 => x"51", + 5271 => x"56", + 5272 => x"84", + 5273 => x"81", + 5274 => x"77", + 5275 => x"9a", + 5276 => x"ec", + 5277 => x"15", + 5278 => x"72", + 5279 => x"72", + 5280 => x"38", + 5281 => x"06", + 5282 => x"2e", + 5283 => x"56", + 5284 => x"80", + 5285 => x"da", + 5286 => x"85", + 5287 => x"82", + 5288 => x"88", + 5289 => x"8f", + 5290 => x"56", + 5291 => x"38", + 5292 => x"51", + 5293 => x"82", + 5294 => x"83", + 5295 => x"55", + 5296 => x"80", + 5297 => x"da", + 5298 => x"85", + 5299 => x"80", + 5300 => x"da", + 5301 => x"85", + 5302 => x"ff", + 5303 => x"8d", + 5304 => x"2e", + 5305 => x"88", + 5306 => x"1b", + 5307 => x"05", + 5308 => x"75", + 5309 => x"38", + 5310 => x"52", + 5311 => x"51", + 5312 => x"3f", + 5313 => x"08", + 5314 => x"ec", + 5315 => x"82", + 5316 => x"85", + 5317 => x"ff", + 5318 => x"26", + 5319 => x"57", + 5320 => x"f5", + 5321 => x"82", + 5322 => x"f5", + 5323 => x"81", + 5324 => x"8d", + 5325 => x"2e", + 5326 => x"82", + 5327 => x"16", + 5328 => x"16", + 5329 => x"70", + 5330 => x"7a", + 5331 => x"0c", + 5332 => x"83", + 5333 => x"06", + 5334 => x"de", + 5335 => x"81", + 5336 => x"ec", + 5337 => x"ff", + 5338 => x"56", + 5339 => x"38", + 5340 => x"38", + 5341 => x"51", + 5342 => x"82", + 5343 => x"a8", + 5344 => x"82", + 5345 => x"39", + 5346 => x"80", + 5347 => x"38", + 5348 => x"15", + 5349 => x"53", + 5350 => x"8e", + 5351 => x"75", + 5352 => x"76", + 5353 => x"51", + 5354 => x"ff", + 5355 => x"53", + 5356 => x"9c", + 5357 => x"81", + 5358 => x"0b", + 5359 => x"ff", + 5360 => x"0c", + 5361 => x"84", + 5362 => x"83", + 5363 => x"06", + 5364 => x"80", + 5365 => x"d8", + 5366 => x"85", + 5367 => x"ff", + 5368 => x"72", + 5369 => x"81", + 5370 => x"38", + 5371 => x"73", + 5372 => x"3f", + 5373 => x"08", + 5374 => x"82", + 5375 => x"84", + 5376 => x"b2", + 5377 => x"d9", + 5378 => x"ec", + 5379 => x"ff", + 5380 => x"82", + 5381 => x"09", + 5382 => x"c8", + 5383 => x"51", + 5384 => x"82", + 5385 => x"84", + 5386 => x"d2", + 5387 => x"06", + 5388 => x"98", + 5389 => x"c0", + 5390 => x"ec", + 5391 => x"85", + 5392 => x"09", + 5393 => x"38", + 5394 => x"51", + 5395 => x"82", + 5396 => x"90", + 5397 => x"a0", + 5398 => x"9c", + 5399 => x"ec", + 5400 => x"0c", + 5401 => x"82", + 5402 => x"81", + 5403 => x"82", + 5404 => x"72", + 5405 => x"80", + 5406 => x"0c", + 5407 => x"82", + 5408 => x"91", + 5409 => x"fb", + 5410 => x"54", + 5411 => x"80", + 5412 => x"73", + 5413 => x"80", + 5414 => x"72", + 5415 => x"80", + 5416 => x"86", + 5417 => x"15", + 5418 => x"71", + 5419 => x"81", + 5420 => x"81", + 5421 => x"d0", + 5422 => x"85", + 5423 => x"06", + 5424 => x"38", + 5425 => x"54", + 5426 => x"80", + 5427 => x"71", + 5428 => x"82", + 5429 => x"87", + 5430 => x"fa", + 5431 => x"ab", + 5432 => x"58", + 5433 => x"05", + 5434 => x"d7", + 5435 => x"80", + 5436 => x"ec", + 5437 => x"38", + 5438 => x"08", + 5439 => x"9d", + 5440 => x"08", + 5441 => x"80", + 5442 => x"80", + 5443 => x"54", + 5444 => x"84", + 5445 => x"34", + 5446 => x"75", + 5447 => x"2e", + 5448 => x"53", + 5449 => x"53", + 5450 => x"f7", + 5451 => x"85", + 5452 => x"73", + 5453 => x"0c", + 5454 => x"04", + 5455 => x"67", + 5456 => x"80", + 5457 => x"59", + 5458 => x"78", + 5459 => x"ca", + 5460 => x"06", + 5461 => x"3d", + 5462 => x"99", + 5463 => x"52", + 5464 => x"3f", + 5465 => x"08", + 5466 => x"ec", + 5467 => x"38", + 5468 => x"52", + 5469 => x"52", + 5470 => x"3f", + 5471 => x"08", + 5472 => x"ec", + 5473 => x"02", + 5474 => x"33", + 5475 => x"55", + 5476 => x"25", + 5477 => x"55", + 5478 => x"54", + 5479 => x"81", + 5480 => x"80", + 5481 => x"74", + 5482 => x"81", + 5483 => x"75", + 5484 => x"3f", + 5485 => x"08", + 5486 => x"02", + 5487 => x"91", + 5488 => x"81", + 5489 => x"82", + 5490 => x"06", + 5491 => x"80", + 5492 => x"88", + 5493 => x"39", + 5494 => x"58", + 5495 => x"38", + 5496 => x"70", + 5497 => x"54", + 5498 => x"81", + 5499 => x"52", + 5500 => x"86", + 5501 => x"ec", + 5502 => x"88", + 5503 => x"62", + 5504 => x"d4", + 5505 => x"54", + 5506 => x"15", + 5507 => x"62", + 5508 => x"e8", + 5509 => x"52", + 5510 => x"51", + 5511 => x"7a", + 5512 => x"83", + 5513 => x"80", + 5514 => x"38", + 5515 => x"08", + 5516 => x"53", + 5517 => x"3d", + 5518 => x"dd", + 5519 => x"85", + 5520 => x"82", + 5521 => x"82", + 5522 => x"39", + 5523 => x"38", + 5524 => x"33", + 5525 => x"70", + 5526 => x"55", + 5527 => x"2e", + 5528 => x"55", + 5529 => x"77", + 5530 => x"81", + 5531 => x"73", + 5532 => x"38", + 5533 => x"54", + 5534 => x"a0", + 5535 => x"82", + 5536 => x"52", + 5537 => x"f5", + 5538 => x"ec", + 5539 => x"18", + 5540 => x"55", + 5541 => x"ec", + 5542 => x"38", + 5543 => x"70", + 5544 => x"54", + 5545 => x"86", + 5546 => x"c0", + 5547 => x"b0", + 5548 => x"1b", + 5549 => x"1b", + 5550 => x"70", + 5551 => x"ba", + 5552 => x"ec", + 5553 => x"ec", + 5554 => x"0c", + 5555 => x"52", + 5556 => x"3f", + 5557 => x"08", + 5558 => x"08", + 5559 => x"77", + 5560 => x"86", + 5561 => x"1a", + 5562 => x"1a", + 5563 => x"91", + 5564 => x"0b", + 5565 => x"80", + 5566 => x"0c", + 5567 => x"70", + 5568 => x"54", + 5569 => x"81", + 5570 => x"85", + 5571 => x"2e", + 5572 => x"82", + 5573 => x"94", + 5574 => x"17", + 5575 => x"2b", + 5576 => x"57", + 5577 => x"52", + 5578 => x"f8", + 5579 => x"ec", + 5580 => x"85", + 5581 => x"26", + 5582 => x"55", + 5583 => x"08", + 5584 => x"81", + 5585 => x"79", + 5586 => x"31", + 5587 => x"81", + 5588 => x"07", + 5589 => x"54", + 5590 => x"8a", + 5591 => x"75", + 5592 => x"73", + 5593 => x"98", + 5594 => x"a9", + 5595 => x"ff", + 5596 => x"80", + 5597 => x"76", + 5598 => x"d5", + 5599 => x"85", + 5600 => x"38", + 5601 => x"39", + 5602 => x"82", + 5603 => x"05", + 5604 => x"84", + 5605 => x"0c", + 5606 => x"82", + 5607 => x"97", + 5608 => x"f2", + 5609 => x"63", + 5610 => x"40", + 5611 => x"7e", + 5612 => x"fc", + 5613 => x"51", + 5614 => x"82", + 5615 => x"55", + 5616 => x"08", + 5617 => x"19", + 5618 => x"80", + 5619 => x"74", + 5620 => x"39", + 5621 => x"81", + 5622 => x"56", + 5623 => x"82", + 5624 => x"39", + 5625 => x"1a", + 5626 => x"82", + 5627 => x"0b", + 5628 => x"81", + 5629 => x"39", + 5630 => x"94", + 5631 => x"55", + 5632 => x"83", + 5633 => x"7b", + 5634 => x"89", + 5635 => x"08", + 5636 => x"06", + 5637 => x"81", + 5638 => x"8a", + 5639 => x"05", + 5640 => x"06", + 5641 => x"a8", + 5642 => x"38", + 5643 => x"55", + 5644 => x"19", + 5645 => x"51", + 5646 => x"82", + 5647 => x"55", + 5648 => x"ff", + 5649 => x"ff", + 5650 => x"38", + 5651 => x"0c", + 5652 => x"52", + 5653 => x"9b", + 5654 => x"ec", + 5655 => x"ff", + 5656 => x"85", + 5657 => x"7c", + 5658 => x"57", + 5659 => x"80", + 5660 => x"1a", + 5661 => x"22", + 5662 => x"75", + 5663 => x"38", + 5664 => x"58", + 5665 => x"53", + 5666 => x"1b", + 5667 => x"d8", + 5668 => x"ec", + 5669 => x"38", + 5670 => x"33", + 5671 => x"80", + 5672 => x"b0", + 5673 => x"31", + 5674 => x"27", + 5675 => x"80", + 5676 => x"52", + 5677 => x"77", + 5678 => x"7d", + 5679 => x"b0", + 5680 => x"2b", + 5681 => x"76", + 5682 => x"94", + 5683 => x"ff", + 5684 => x"71", + 5685 => x"7b", + 5686 => x"38", + 5687 => x"19", + 5688 => x"51", + 5689 => x"82", + 5690 => x"fe", + 5691 => x"53", + 5692 => x"83", + 5693 => x"b4", + 5694 => x"51", + 5695 => x"7b", + 5696 => x"08", + 5697 => x"76", + 5698 => x"08", + 5699 => x"0c", + 5700 => x"f3", + 5701 => x"75", + 5702 => x"0c", + 5703 => x"04", + 5704 => x"60", + 5705 => x"40", + 5706 => x"80", + 5707 => x"3d", + 5708 => x"77", + 5709 => x"3f", + 5710 => x"08", + 5711 => x"ec", + 5712 => x"91", + 5713 => x"74", + 5714 => x"38", + 5715 => x"b8", + 5716 => x"33", + 5717 => x"70", + 5718 => x"56", + 5719 => x"74", + 5720 => x"a4", + 5721 => x"82", + 5722 => x"34", + 5723 => x"98", + 5724 => x"91", + 5725 => x"56", + 5726 => x"94", + 5727 => x"11", + 5728 => x"76", + 5729 => x"75", + 5730 => x"80", + 5731 => x"38", + 5732 => x"70", + 5733 => x"56", + 5734 => x"fd", + 5735 => x"11", + 5736 => x"77", + 5737 => x"5c", + 5738 => x"38", + 5739 => x"88", + 5740 => x"74", + 5741 => x"52", + 5742 => x"18", + 5743 => x"51", + 5744 => x"82", + 5745 => x"55", + 5746 => x"08", + 5747 => x"ab", + 5748 => x"2e", + 5749 => x"74", + 5750 => x"95", + 5751 => x"19", + 5752 => x"08", + 5753 => x"88", + 5754 => x"55", + 5755 => x"9c", + 5756 => x"09", + 5757 => x"38", + 5758 => x"91", + 5759 => x"ec", + 5760 => x"38", + 5761 => x"52", + 5762 => x"e7", + 5763 => x"ec", + 5764 => x"fe", + 5765 => x"85", + 5766 => x"7c", + 5767 => x"57", + 5768 => x"80", + 5769 => x"1b", + 5770 => x"22", + 5771 => x"75", + 5772 => x"38", + 5773 => x"59", + 5774 => x"53", + 5775 => x"1a", + 5776 => x"8e", + 5777 => x"ec", + 5778 => x"38", + 5779 => x"08", + 5780 => x"56", + 5781 => x"9b", + 5782 => x"53", + 5783 => x"77", + 5784 => x"7d", + 5785 => x"16", + 5786 => x"3f", + 5787 => x"0b", + 5788 => x"78", + 5789 => x"80", + 5790 => x"18", + 5791 => x"08", + 5792 => x"7e", + 5793 => x"3f", + 5794 => x"08", + 5795 => x"7e", + 5796 => x"0c", + 5797 => x"19", + 5798 => x"08", + 5799 => x"84", + 5800 => x"57", + 5801 => x"27", + 5802 => x"56", + 5803 => x"52", + 5804 => x"c9", + 5805 => x"ec", + 5806 => x"38", + 5807 => x"52", + 5808 => x"83", + 5809 => x"b4", + 5810 => x"a4", + 5811 => x"81", + 5812 => x"34", + 5813 => x"7e", + 5814 => x"0c", + 5815 => x"1a", + 5816 => x"94", + 5817 => x"1b", + 5818 => x"5e", + 5819 => x"27", + 5820 => x"55", + 5821 => x"0c", + 5822 => x"90", + 5823 => x"c0", + 5824 => x"90", + 5825 => x"56", + 5826 => x"ec", + 5827 => x"0d", + 5828 => x"0d", + 5829 => x"fc", + 5830 => x"52", + 5831 => x"3f", + 5832 => x"08", + 5833 => x"ec", + 5834 => x"38", + 5835 => x"70", + 5836 => x"81", + 5837 => x"55", + 5838 => x"80", + 5839 => x"16", + 5840 => x"51", + 5841 => x"82", + 5842 => x"57", + 5843 => x"08", + 5844 => x"a4", + 5845 => x"11", + 5846 => x"55", + 5847 => x"16", + 5848 => x"08", + 5849 => x"75", + 5850 => x"c7", + 5851 => x"08", + 5852 => x"51", + 5853 => x"82", + 5854 => x"52", + 5855 => x"c9", + 5856 => x"52", + 5857 => x"c9", + 5858 => x"54", + 5859 => x"15", + 5860 => x"cc", + 5861 => x"85", + 5862 => x"17", + 5863 => x"06", + 5864 => x"90", + 5865 => x"82", + 5866 => x"8a", + 5867 => x"fc", + 5868 => x"70", + 5869 => x"d9", + 5870 => x"ec", + 5871 => x"85", + 5872 => x"38", + 5873 => x"05", + 5874 => x"f1", + 5875 => x"85", + 5876 => x"82", + 5877 => x"87", + 5878 => x"ec", + 5879 => x"72", + 5880 => x"0c", + 5881 => x"04", + 5882 => x"84", + 5883 => x"d3", + 5884 => x"80", + 5885 => x"ec", + 5886 => x"38", + 5887 => x"08", + 5888 => x"34", + 5889 => x"82", + 5890 => x"83", + 5891 => x"ef", + 5892 => x"53", + 5893 => x"05", + 5894 => x"51", + 5895 => x"82", + 5896 => x"55", + 5897 => x"08", + 5898 => x"76", + 5899 => x"93", + 5900 => x"51", + 5901 => x"82", + 5902 => x"55", + 5903 => x"08", + 5904 => x"80", + 5905 => x"70", + 5906 => x"56", + 5907 => x"89", + 5908 => x"94", + 5909 => x"b2", + 5910 => x"05", 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x"84", + 5970 => x"06", + 5971 => x"57", + 5972 => x"76", + 5973 => x"9e", + 5974 => x"05", + 5975 => x"dc", + 5976 => x"90", + 5977 => x"81", + 5978 => x"56", + 5979 => x"80", + 5980 => x"02", + 5981 => x"81", + 5982 => x"70", + 5983 => x"56", + 5984 => x"81", + 5985 => x"78", + 5986 => x"38", + 5987 => x"99", + 5988 => x"81", + 5989 => x"18", + 5990 => x"18", + 5991 => x"58", + 5992 => x"33", + 5993 => x"ee", + 5994 => x"6f", + 5995 => x"af", + 5996 => x"8d", + 5997 => x"2e", + 5998 => x"8a", + 5999 => x"6f", + 6000 => x"af", + 6001 => x"0b", + 6002 => x"33", + 6003 => x"81", + 6004 => x"08", + 6005 => x"5c", + 6006 => x"73", + 6007 => x"38", + 6008 => x"1a", + 6009 => x"55", + 6010 => x"38", + 6011 => x"73", + 6012 => x"38", + 6013 => x"76", + 6014 => x"74", + 6015 => x"33", + 6016 => x"05", + 6017 => x"15", + 6018 => x"ba", + 6019 => x"05", + 6020 => x"ff", + 6021 => x"06", + 6022 => x"57", + 6023 => x"18", + 6024 => x"54", + 6025 => x"70", + 6026 => x"34", + 6027 => x"ee", + 6028 => x"34", + 6029 => x"ec", + 6030 => x"0d", + 6031 => x"0d", + 6032 => x"3d", + 6033 => x"71", + 6034 => x"ec", + 6035 => x"85", + 6036 => x"82", + 6037 => x"82", + 6038 => x"15", + 6039 => x"82", + 6040 => x"15", + 6041 => x"76", + 6042 => x"90", + 6043 => x"81", + 6044 => x"06", + 6045 => x"72", + 6046 => x"56", + 6047 => x"54", + 6048 => x"17", + 6049 => x"78", + 6050 => x"38", + 6051 => x"22", + 6052 => x"59", + 6053 => x"78", + 6054 => x"76", + 6055 => x"51", + 6056 => x"3f", + 6057 => x"08", + 6058 => x"54", + 6059 => x"53", + 6060 => x"3f", + 6061 => x"08", + 6062 => x"38", + 6063 => x"05", + 6064 => x"70", + 6065 => x"77", + 6066 => x"18", + 6067 => x"51", + 6068 => x"88", + 6069 => x"73", + 6070 => x"52", + 6071 => x"a0", + 6072 => x"ec", + 6073 => x"85", + 6074 => x"2e", + 6075 => x"82", + 6076 => x"ff", + 6077 => x"38", + 6078 => x"08", + 6079 => x"73", + 6080 => x"73", + 6081 => x"9c", + 6082 => x"27", + 6083 => x"75", + 6084 => x"16", + 6085 => x"17", + 6086 => x"33", + 6087 => x"70", + 6088 => x"55", + 6089 => x"80", + 6090 => x"73", + 6091 => x"cc", + 6092 => x"85", + 6093 => x"82", + 6094 => x"94", + 6095 => x"ec", + 6096 => x"39", + 6097 => x"51", + 6098 => x"82", + 6099 => x"54", + 6100 => x"be", + 6101 => x"27", + 6102 => x"53", + 6103 => x"08", + 6104 => x"73", + 6105 => x"ff", + 6106 => x"15", + 6107 => x"16", + 6108 => x"ff", + 6109 => x"80", + 6110 => x"73", + 6111 => x"c5", + 6112 => x"85", + 6113 => x"38", + 6114 => x"16", + 6115 => x"80", + 6116 => x"0b", + 6117 => x"81", + 6118 => x"75", + 6119 => x"85", + 6120 => x"58", + 6121 => x"54", + 6122 => x"74", + 6123 => x"73", + 6124 => x"90", + 6125 => x"c0", + 6126 => x"90", + 6127 => x"83", + 6128 => x"72", + 6129 => x"38", + 6130 => x"08", + 6131 => x"77", + 6132 => x"80", + 6133 => x"85", + 6134 => x"3d", + 6135 => x"3d", + 6136 => x"89", + 6137 => x"2e", + 6138 => x"80", + 6139 => x"fc", + 6140 => x"3d", + 6141 => x"e1", + 6142 => x"85", + 6143 => x"82", + 6144 => x"80", + 6145 => x"76", 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x"52", + 6205 => x"91", + 6206 => x"73", + 6207 => x"3f", + 6208 => x"08", + 6209 => x"09", + 6210 => x"72", + 6211 => x"70", + 6212 => x"08", + 6213 => x"54", + 6214 => x"85", + 6215 => x"3d", + 6216 => x"3d", + 6217 => x"80", + 6218 => x"70", + 6219 => x"52", + 6220 => x"3f", + 6221 => x"08", + 6222 => x"ec", + 6223 => x"64", + 6224 => x"d5", + 6225 => x"85", + 6226 => x"82", + 6227 => x"a0", + 6228 => x"cb", + 6229 => x"98", + 6230 => x"73", + 6231 => x"38", + 6232 => x"39", + 6233 => x"88", + 6234 => x"75", + 6235 => x"3f", + 6236 => x"ec", + 6237 => x"0d", + 6238 => x"0d", + 6239 => x"5c", + 6240 => x"3d", + 6241 => x"93", + 6242 => x"ca", + 6243 => x"ec", + 6244 => x"85", + 6245 => x"87", + 6246 => x"0c", + 6247 => x"11", + 6248 => x"90", + 6249 => x"56", + 6250 => x"74", + 6251 => x"75", + 6252 => x"eb", + 6253 => x"81", + 6254 => x"5b", + 6255 => x"82", + 6256 => x"75", + 6257 => x"73", + 6258 => x"81", + 6259 => x"38", + 6260 => x"57", + 6261 => x"3d", + 6262 => x"c1", + 6263 => x"85", + 6264 => x"2e", + 6265 => x"85", + 6266 => x"2e", + 6267 => x"85", + 6268 => x"81", + 6269 => x"85", + 6270 => x"80", + 6271 => x"81", + 6272 => x"59", + 6273 => x"14", + 6274 => x"c8", + 6275 => x"39", + 6276 => x"82", + 6277 => x"57", + 6278 => x"38", + 6279 => x"18", + 6280 => x"ff", + 6281 => x"82", + 6282 => x"5b", + 6283 => x"08", + 6284 => x"7c", + 6285 => x"12", + 6286 => x"52", + 6287 => x"82", + 6288 => x"06", + 6289 => x"14", + 6290 => x"95", + 6291 => x"ec", + 6292 => x"ff", + 6293 => x"81", + 6294 => x"25", + 6295 => x"59", + 6296 => x"9d", + 6297 => x"51", + 6298 => x"3f", + 6299 => x"08", + 6300 => x"70", + 6301 => x"70", + 6302 => x"84", + 6303 => x"51", + 6304 => x"ff", + 6305 => x"56", + 6306 => x"38", + 6307 => x"7c", + 6308 => x"0c", + 6309 => x"81", + 6310 => x"74", + 6311 => x"7a", + 6312 => x"0c", + 6313 => x"04", + 6314 => x"79", + 6315 => x"05", + 6316 => x"57", + 6317 => x"82", + 6318 => x"56", + 6319 => x"08", + 6320 => x"91", + 6321 => x"75", + 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x"b6", + 6440 => x"ec", + 6441 => x"85", + 6442 => x"b0", + 6443 => x"69", + 6444 => x"70", + 6445 => x"ea", + 6446 => x"ec", + 6447 => x"85", + 6448 => x"38", + 6449 => x"94", + 6450 => x"ec", + 6451 => x"09", + 6452 => x"88", + 6453 => x"df", + 6454 => x"85", + 6455 => x"51", + 6456 => x"74", + 6457 => x"78", + 6458 => x"8a", + 6459 => x"57", + 6460 => x"82", + 6461 => x"75", + 6462 => x"85", + 6463 => x"38", + 6464 => x"85", + 6465 => x"2e", + 6466 => x"83", + 6467 => x"82", + 6468 => x"ff", + 6469 => x"06", + 6470 => x"54", + 6471 => x"73", + 6472 => x"82", + 6473 => x"52", + 6474 => x"f5", + 6475 => x"ec", + 6476 => x"85", + 6477 => x"9a", + 6478 => x"a0", + 6479 => x"51", + 6480 => x"3f", + 6481 => x"0b", + 6482 => x"78", + 6483 => x"bf", + 6484 => x"88", + 6485 => x"80", + 6486 => x"ff", + 6487 => x"75", + 6488 => x"11", + 6489 => x"cb", + 6490 => x"78", + 6491 => x"80", + 6492 => x"ff", + 6493 => x"78", + 6494 => x"80", + 6495 => x"7f", + 6496 => x"d4", + 6497 => x"c9", + 6498 => x"54", + 6499 => x"15", + 6500 => x"ca", + 6501 => x"85", + 6502 => x"82", + 6503 => x"b2", + 6504 => x"b2", + 6505 => x"96", + 6506 => x"b5", + 6507 => x"53", + 6508 => x"51", + 6509 => x"64", + 6510 => x"8b", + 6511 => x"54", + 6512 => x"15", + 6513 => x"ff", + 6514 => x"82", + 6515 => x"54", + 6516 => x"53", + 6517 => x"51", + 6518 => x"3f", + 6519 => x"ec", + 6520 => x"0d", + 6521 => x"0d", + 6522 => x"05", + 6523 => x"3f", + 6524 => x"3d", + 6525 => x"52", + 6526 => x"d5", + 6527 => x"85", + 6528 => x"82", + 6529 => x"82", + 6530 => x"4d", + 6531 => x"52", + 6532 => x"52", + 6533 => x"3f", + 6534 => x"08", + 6535 => x"ec", + 6536 => x"38", + 6537 => x"05", + 6538 => x"06", + 6539 => x"73", + 6540 => x"a0", + 6541 => x"08", + 6542 => x"ff", + 6543 => x"ff", + 6544 => x"ac", + 6545 => x"92", + 6546 => x"54", + 6547 => x"3f", + 6548 => x"52", + 6549 => x"ca", + 6550 => x"ec", + 6551 => x"85", + 6552 => x"38", + 6553 => x"09", + 6554 => x"38", + 6555 => x"08", + 6556 => x"88", + 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x"ec", + 6675 => x"82", + 6676 => x"93", + 6677 => x"ea", + 6678 => x"6b", + 6679 => x"53", + 6680 => x"05", + 6681 => x"51", + 6682 => x"82", + 6683 => x"82", + 6684 => x"09", + 6685 => x"82", + 6686 => x"07", + 6687 => x"55", + 6688 => x"2e", + 6689 => x"81", + 6690 => x"55", + 6691 => x"2e", + 6692 => x"7b", + 6693 => x"80", + 6694 => x"70", + 6695 => x"bd", + 6696 => x"85", + 6697 => x"82", + 6698 => x"80", + 6699 => x"52", + 6700 => x"ad", + 6701 => x"ec", + 6702 => x"85", + 6703 => x"38", + 6704 => x"08", + 6705 => x"08", + 6706 => x"56", + 6707 => x"19", + 6708 => x"59", + 6709 => x"74", + 6710 => x"56", + 6711 => x"ec", + 6712 => x"75", + 6713 => x"74", + 6714 => x"2e", + 6715 => x"16", + 6716 => x"33", + 6717 => x"73", + 6718 => x"38", + 6719 => x"84", + 6720 => x"06", + 6721 => x"7a", + 6722 => x"76", + 6723 => x"70", + 6724 => x"25", + 6725 => x"80", + 6726 => x"38", + 6727 => x"bc", + 6728 => x"11", + 6729 => x"ff", + 6730 => x"82", + 6731 => x"57", + 6732 => x"08", + 6733 => x"70", + 6734 => x"80", + 6735 => x"83", + 6736 => x"80", + 6737 => x"84", + 6738 => x"a7", + 6739 => x"b4", + 6740 => x"ad", + 6741 => x"85", + 6742 => x"0c", + 6743 => x"ec", + 6744 => x"0d", + 6745 => x"0d", + 6746 => x"3d", + 6747 => x"52", + 6748 => x"ce", + 6749 => x"85", + 6750 => x"85", + 6751 => x"54", + 6752 => x"08", + 6753 => x"8b", + 6754 => x"8b", + 6755 => x"59", + 6756 => x"3f", + 6757 => x"33", + 6758 => x"06", + 6759 => x"57", + 6760 => x"81", + 6761 => x"58", + 6762 => x"06", + 6763 => x"4e", + 6764 => x"ff", + 6765 => x"82", + 6766 => x"80", + 6767 => x"6c", + 6768 => x"53", + 6769 => x"ae", + 6770 => x"85", + 6771 => x"2e", + 6772 => x"88", + 6773 => x"6d", + 6774 => x"55", + 6775 => x"85", + 6776 => x"ff", + 6777 => x"83", + 6778 => x"51", + 6779 => x"26", + 6780 => x"15", + 6781 => x"ff", + 6782 => x"80", + 6783 => x"87", + 6784 => x"b4", + 6785 => x"74", + 6786 => x"38", + 6787 => x"80", + 6788 => x"ad", + 6789 => x"85", + 6790 => x"38", + 6791 => x"27", + 6792 => x"89", + 6793 => x"8b", + 6794 => x"27", + 6795 => x"55", + 6796 => x"81", + 6797 => x"8f", + 6798 => x"2a", + 6799 => x"70", + 6800 => x"34", + 6801 => x"74", + 6802 => x"05", + 6803 => x"17", + 6804 => x"70", + 6805 => x"52", + 6806 => x"73", + 6807 => x"c8", + 6808 => x"33", + 6809 => x"73", + 6810 => x"81", + 6811 => x"80", + 6812 => x"02", + 6813 => x"76", + 6814 => x"51", + 6815 => x"2e", + 6816 => x"87", + 6817 => x"57", + 6818 => x"79", + 6819 => x"80", + 6820 => x"70", + 6821 => x"ba", + 6822 => x"85", + 6823 => x"82", + 6824 => x"80", + 6825 => x"52", + 6826 => x"bf", + 6827 => x"85", + 6828 => x"82", + 6829 => x"8d", + 6830 => x"c4", + 6831 => x"e5", + 6832 => x"c6", + 6833 => x"ec", + 6834 => x"09", + 6835 => x"cc", + 6836 => x"76", + 6837 => x"c4", + 6838 => x"74", + 6839 => x"ff", + 6840 => x"ec", + 6841 => x"85", + 6842 => x"38", + 6843 => x"85", + 6844 => x"67", + 6845 => x"9b", + 6846 => x"88", + 6847 => x"34", + 6848 => x"52", + 6849 => x"aa", + 6850 => x"54", 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x"38", + 6910 => x"59", + 6911 => x"77", + 6912 => x"06", + 6913 => x"87", + 6914 => x"39", + 6915 => x"ba", + 6916 => x"55", + 6917 => x"2e", + 6918 => x"15", + 6919 => x"2e", + 6920 => x"83", + 6921 => x"75", + 6922 => x"7e", + 6923 => x"ed", + 6924 => x"ec", + 6925 => x"85", + 6926 => x"ce", + 6927 => x"16", + 6928 => x"56", + 6929 => x"38", + 6930 => x"19", + 6931 => x"8c", + 6932 => x"7d", + 6933 => x"38", + 6934 => x"0c", + 6935 => x"0c", + 6936 => x"80", + 6937 => x"73", + 6938 => x"98", + 6939 => x"05", + 6940 => x"57", + 6941 => x"26", + 6942 => x"7b", + 6943 => x"0c", + 6944 => x"81", + 6945 => x"84", + 6946 => x"54", + 6947 => x"ec", + 6948 => x"0d", + 6949 => x"0d", + 6950 => x"88", + 6951 => x"05", + 6952 => x"54", + 6953 => x"c5", + 6954 => x"56", + 6955 => x"85", + 6956 => x"8c", + 6957 => x"85", + 6958 => x"2b", + 6959 => x"11", + 6960 => x"74", + 6961 => x"38", + 6962 => x"82", + 6963 => x"81", + 6964 => x"81", + 6965 => x"ff", + 6966 => x"82", + 6967 => x"81", + 6968 => x"81", + 6969 => x"83", + 6970 => x"cb", + 6971 => x"2a", + 6972 => x"51", + 6973 => x"74", + 6974 => x"99", + 6975 => x"53", + 6976 => x"51", + 6977 => x"3f", + 6978 => x"08", + 6979 => x"55", + 6980 => x"92", + 6981 => x"80", + 6982 => x"38", + 6983 => x"06", + 6984 => x"2e", + 6985 => x"48", + 6986 => x"87", + 6987 => x"79", + 6988 => x"78", + 6989 => x"26", + 6990 => x"19", + 6991 => x"74", + 6992 => x"38", + 6993 => x"ef", + 6994 => x"2a", + 6995 => x"70", + 6996 => x"59", + 6997 => x"7a", + 6998 => x"56", + 6999 => x"05", + 7000 => x"77", + 7001 => x"91", + 7002 => x"cb", + 7003 => x"f8", + 7004 => x"52", + 7005 => x"a3", + 7006 => x"56", + 7007 => x"08", + 7008 => x"77", + 7009 => x"77", + 7010 => x"ec", + 7011 => x"45", + 7012 => x"bf", + 7013 => x"8e", + 7014 => x"26", + 7015 => x"74", + 7016 => x"48", + 7017 => x"75", + 7018 => x"38", + 7019 => x"81", + 7020 => x"83", + 7021 => x"2a", + 7022 => x"56", + 7023 => x"2e", + 7024 => x"87", + 7025 => x"82", + 7026 => x"38", + 7027 => x"55", + 7028 => x"83", + 7029 => x"81", + 7030 => x"56", + 7031 => x"80", + 7032 => x"38", + 7033 => x"83", + 7034 => x"06", + 7035 => x"78", + 7036 => x"91", + 7037 => x"0b", + 7038 => x"22", + 7039 => x"80", + 7040 => x"74", + 7041 => x"38", + 7042 => x"56", + 7043 => x"17", + 7044 => x"57", + 7045 => x"2e", + 7046 => x"75", + 7047 => x"79", + 7048 => x"fe", + 7049 => x"82", + 7050 => x"82", + 7051 => x"11", + 7052 => x"55", + 7053 => x"0b", + 7054 => x"08", + 7055 => x"05", + 7056 => x"ff", + 7057 => x"27", + 7058 => x"88", + 7059 => x"ae", + 7060 => x"2a", + 7061 => x"82", + 7062 => x"56", + 7063 => x"2e", + 7064 => x"77", + 7065 => x"82", + 7066 => x"79", + 7067 => x"70", + 7068 => x"5a", + 7069 => x"86", + 7070 => x"27", + 7071 => x"52", + 7072 => x"c1", + 7073 => x"85", + 7074 => x"85", + 7075 => x"84", + 7076 => x"85", + 7077 => x"f5", + 7078 => x"81", + 7079 => x"ec", + 7080 => x"82", + 7081 => x"11", + 7082 => x"2a", + 7083 => x"51", + 7084 => x"ff", + 7085 => x"5d", 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x"ef", + 7145 => x"81", + 7146 => x"7a", + 7147 => x"c0", + 7148 => x"52", + 7149 => x"ff", + 7150 => x"79", + 7151 => x"7b", + 7152 => x"06", + 7153 => x"51", + 7154 => x"3f", + 7155 => x"1c", + 7156 => x"32", + 7157 => x"05", + 7158 => x"84", + 7159 => x"51", + 7160 => x"51", + 7161 => x"3f", + 7162 => x"83", + 7163 => x"90", + 7164 => x"ff", + 7165 => x"93", + 7166 => x"a0", + 7167 => x"39", + 7168 => x"1b", + 7169 => x"b9", + 7170 => x"95", + 7171 => x"52", + 7172 => x"ff", + 7173 => x"81", + 7174 => x"1b", + 7175 => x"83", + 7176 => x"9c", + 7177 => x"a0", + 7178 => x"83", + 7179 => x"06", + 7180 => x"82", + 7181 => x"52", + 7182 => x"51", + 7183 => x"3f", + 7184 => x"1b", + 7185 => x"f9", + 7186 => x"ac", + 7187 => x"9f", + 7188 => x"52", + 7189 => x"ff", + 7190 => x"86", + 7191 => x"51", + 7192 => x"3f", + 7193 => x"80", + 7194 => x"a9", + 7195 => x"1c", + 7196 => x"81", + 7197 => x"80", + 7198 => x"ae", + 7199 => x"b2", + 7200 => x"1b", + 7201 => x"b9", + 7202 => x"ff", + 7203 => x"96", + 7204 => x"9f", + 7205 => x"80", + 7206 => x"34", + 7207 => x"1c", + 7208 => x"81", + 7209 => x"ab", + 7210 => x"9f", + 7211 => x"d4", + 7212 => x"fe", + 7213 => x"59", + 7214 => x"3f", + 7215 => x"53", + 7216 => x"51", + 7217 => x"3f", + 7218 => x"85", + 7219 => x"e7", + 7220 => x"2e", + 7221 => x"80", + 7222 => x"54", + 7223 => x"53", + 7224 => x"51", + 7225 => x"3f", + 7226 => x"80", + 7227 => x"ff", + 7228 => x"84", + 7229 => x"d2", + 7230 => x"ff", + 7231 => x"86", + 7232 => x"f2", + 7233 => x"1b", + 7234 => x"b5", + 7235 => x"52", + 7236 => x"51", + 7237 => x"3f", + 7238 => x"ec", + 7239 => x"9e", + 7240 => x"d4", + 7241 => x"51", + 7242 => x"3f", + 7243 => x"87", + 7244 => x"52", + 7245 => x"9a", + 7246 => x"54", + 7247 => x"7a", + 7248 => x"ff", + 7249 => x"65", + 7250 => x"7a", + 7251 => x"c3", + 7252 => x"80", + 7253 => x"2e", + 7254 => x"9a", + 7255 => x"7a", + 7256 => x"dd", + 7257 => x"84", + 7258 => x"9d", + 7259 => x"0a", + 7260 => x"51", + 7261 => x"ff", + 7262 => x"7d", + 7263 => x"38", + 7264 => x"52", + 7265 => x"9d", + 7266 => x"55", + 7267 => x"62", + 7268 => x"74", + 7269 => x"75", + 7270 => x"7e", + 7271 => x"b2", + 7272 => x"ec", + 7273 => x"38", + 7274 => x"82", + 7275 => x"52", + 7276 => x"9d", + 7277 => x"16", + 7278 => x"56", + 7279 => x"38", + 7280 => x"77", + 7281 => x"8d", + 7282 => x"7d", + 7283 => x"38", + 7284 => x"57", + 7285 => x"83", + 7286 => x"76", + 7287 => x"7a", + 7288 => x"ff", + 7289 => x"82", + 7290 => x"81", + 7291 => x"16", + 7292 => x"56", + 7293 => x"38", + 7294 => x"83", + 7295 => x"86", + 7296 => x"ff", + 7297 => x"38", + 7298 => x"82", + 7299 => x"81", + 7300 => x"06", + 7301 => x"fe", + 7302 => x"53", + 7303 => x"51", + 7304 => x"3f", + 7305 => x"52", + 7306 => x"9b", + 7307 => x"be", + 7308 => x"75", + 7309 => x"81", + 7310 => x"0b", + 7311 => x"77", + 7312 => x"75", + 7313 => x"60", + 7314 => x"80", + 7315 => x"75", + 7316 => x"b6", + 7317 => x"85", + 7318 => x"85", + 7319 => x"2a", + 7320 => x"75", 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x"25", + 7380 => x"3d", + 7381 => x"75", + 7382 => x"52", + 7383 => x"cb", + 7384 => x"76", + 7385 => x"81", + 7386 => x"07", + 7387 => x"09", + 7388 => x"51", + 7389 => x"84", + 7390 => x"19", + 7391 => x"8b", + 7392 => x"f9", + 7393 => x"84", + 7394 => x"56", + 7395 => x"a7", + 7396 => x"fc", + 7397 => x"53", + 7398 => x"75", + 7399 => x"80", + 7400 => x"ec", + 7401 => x"84", + 7402 => x"2e", + 7403 => x"87", + 7404 => x"08", + 7405 => x"ff", + 7406 => x"85", + 7407 => x"3d", + 7408 => x"3d", + 7409 => x"80", + 7410 => x"52", + 7411 => x"99", + 7412 => x"74", + 7413 => x"0d", + 7414 => x"0d", + 7415 => x"05", + 7416 => x"86", + 7417 => x"54", + 7418 => x"73", + 7419 => x"fe", + 7420 => x"51", + 7421 => x"98", + 7422 => x"00", + 7423 => x"ff", + 7424 => x"ff", + 7425 => x"ff", + 7426 => x"00", + 7427 => x"8e", + 7428 => x"12", + 7429 => x"19", + 7430 => x"20", + 7431 => x"27", + 7432 => x"2e", + 7433 => x"35", + 7434 => x"3c", + 7435 => x"43", + 7436 => x"4a", + 7437 => x"51", + 7438 => x"58", + 7439 => x"5e", + 7440 => x"64", + 7441 => x"6a", + 7442 => x"70", + 7443 => x"76", + 7444 => x"7c", + 7445 => x"82", + 7446 => x"88", + 7447 => x"ce", + 7448 => x"d4", + 7449 => x"da", + 7450 => x"e0", + 7451 => x"e6", + 7452 => x"e6", + 7453 => x"d0", + 7454 => x"bd", + 7455 => x"eb", + 7456 => x"b8", + 7457 => x"c3", + 7458 => x"67", + 7459 => x"c2", + 7460 => x"a4", + 7461 => x"3b", + 7462 => x"c0", + 7463 => x"6d", + 7464 => x"c3", + 7465 => x"bd", + 7466 => x"e0", + 7467 => x"67", + 7468 => x"c3", + 7469 => x"c3", + 7470 => x"c0", + 7471 => x"3b", + 7472 => x"c2", + 7473 => x"eb", + 7474 => x"69", + 7475 => x"00", + 7476 => x"63", + 7477 => x"00", + 7478 => x"69", + 7479 => x"00", + 7480 => x"61", + 7481 => x"00", + 7482 => x"65", + 7483 => x"00", + 7484 => x"65", + 7485 => x"00", + 7486 => x"70", + 7487 => x"00", + 7488 => x"66", + 7489 => x"00", + 7490 => x"6d", + 7491 => x"00", + 7492 => x"00", + 7493 => x"00", + 7494 => x"00", + 7495 => x"00", + 7496 => x"00", + 7497 => x"00", + 7498 => x"00", + 7499 => x"6c", + 7500 => x"00", + 7501 => x"00", + 7502 => x"74", + 7503 => x"00", + 7504 => x"65", + 7505 => x"00", + 7506 => x"6f", + 7507 => x"00", + 7508 => x"74", + 7509 => x"00", + 7510 => x"73", + 7511 => x"00", + 7512 => x"73", + 7513 => x"00", + 7514 => x"6f", + 7515 => x"00", + 7516 => x"00", + 7517 => x"6b", + 7518 => x"72", + 7519 => x"00", + 7520 => x"65", + 7521 => x"6c", + 7522 => x"72", + 7523 => x"0a", + 7524 => x"00", + 7525 => x"6b", + 7526 => x"74", + 7527 => x"61", + 7528 => x"0a", + 7529 => x"00", + 7530 => x"66", + 7531 => x"20", + 7532 => x"6e", + 7533 => x"00", + 7534 => x"70", + 7535 => x"20", + 7536 => x"6e", + 7537 => x"00", + 7538 => x"61", + 7539 => x"20", + 7540 => x"65", + 7541 => x"65", + 7542 => x"00", + 7543 => x"65", + 7544 => x"64", + 7545 => x"65", + 7546 => x"00", + 7547 => x"65", + 7548 => x"72", + 7549 => x"79", + 7550 => x"69", + 7551 => x"2e", + 7552 => x"00", + 7553 => x"65", + 7554 => x"6e", + 7555 => x"20", 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x"65", + 7615 => x"69", + 7616 => x"2e", + 7617 => x"00", + 7618 => x"61", + 7619 => x"65", + 7620 => x"69", + 7621 => x"72", + 7622 => x"74", + 7623 => x"00", + 7624 => x"63", + 7625 => x"2e", + 7626 => x"00", + 7627 => x"6e", + 7628 => x"20", + 7629 => x"6f", + 7630 => x"00", + 7631 => x"75", + 7632 => x"74", + 7633 => x"25", + 7634 => x"74", + 7635 => x"75", + 7636 => x"74", + 7637 => x"73", + 7638 => x"0a", + 7639 => x"00", + 7640 => x"64", + 7641 => x"00", + 7642 => x"58", + 7643 => x"00", + 7644 => x"00", + 7645 => x"58", + 7646 => x"00", + 7647 => x"20", + 7648 => x"20", + 7649 => x"00", + 7650 => x"58", + 7651 => x"00", + 7652 => x"00", + 7653 => x"00", + 7654 => x"00", + 7655 => x"00", + 7656 => x"20", + 7657 => x"28", + 7658 => x"00", + 7659 => x"30", + 7660 => x"30", + 7661 => x"00", + 7662 => x"30", + 7663 => x"00", + 7664 => x"55", + 7665 => x"65", + 7666 => x"30", + 7667 => x"20", + 7668 => x"25", + 7669 => x"2a", + 7670 => x"00", + 7671 => x"20", + 7672 => x"65", + 7673 => x"70", + 7674 => x"61", + 7675 => x"65", + 7676 => x"00", + 7677 => x"65", + 7678 => x"6e", + 7679 => x"72", + 7680 => x"0a", + 7681 => x"00", + 7682 => x"20", + 7683 => x"65", + 7684 => x"70", + 7685 => x"00", + 7686 => x"54", + 7687 => x"44", + 7688 => x"74", + 7689 => x"75", + 7690 => x"00", + 7691 => x"54", + 7692 => x"52", + 7693 => x"74", + 7694 => x"75", + 7695 => x"00", + 7696 => x"54", + 7697 => x"58", + 7698 => x"74", + 7699 => x"75", + 7700 => x"00", + 7701 => x"54", + 7702 => x"58", + 7703 => x"74", + 7704 => x"75", + 7705 => x"00", + 7706 => x"54", + 7707 => x"58", + 7708 => x"74", + 7709 => x"75", + 7710 => x"00", + 7711 => x"54", + 7712 => x"58", + 7713 => x"74", + 7714 => x"75", + 7715 => x"00", + 7716 => x"74", + 7717 => x"20", + 7718 => x"74", + 7719 => x"72", + 7720 => x"0a", + 7721 => x"00", + 7722 => x"62", + 7723 => x"67", + 7724 => x"6d", + 7725 => x"2e", + 7726 => x"00", + 7727 => x"6f", + 7728 => x"63", + 7729 => x"74", + 7730 => x"00", + 7731 => x"2e", + 7732 => x"00", + 7733 => x"00", + 7734 => x"6c", + 7735 => x"74", + 7736 => x"6e", + 7737 => x"61", + 7738 => x"65", + 7739 => x"20", + 7740 => x"64", + 7741 => x"20", + 7742 => x"61", + 7743 => x"69", + 7744 => x"20", + 7745 => x"75", + 7746 => x"79", + 7747 => x"00", + 7748 => x"00", + 7749 => x"61", + 7750 => x"67", + 7751 => x"2e", + 7752 => x"00", + 7753 => x"79", + 7754 => x"2e", + 7755 => x"00", + 7756 => x"70", + 7757 => x"6e", + 7758 => x"2e", + 7759 => x"00", + 7760 => x"6c", + 7761 => x"30", + 7762 => x"2d", + 7763 => x"38", + 7764 => x"25", + 7765 => x"29", + 7766 => x"00", + 7767 => x"70", + 7768 => x"6d", + 7769 => x"0a", + 7770 => x"00", + 7771 => x"6d", + 7772 => x"74", + 7773 => x"00", + 7774 => x"58", + 7775 => x"32", + 7776 => x"00", + 7777 => x"0a", + 7778 => x"00", + 7779 => x"58", + 7780 => x"34", + 7781 => x"00", + 7782 => x"58", + 7783 => x"38", + 7784 => x"00", + 7785 => x"63", + 7786 => x"6e", + 7787 => x"6f", + 7788 => x"40", + 7789 => x"38", + 7790 => x"2e", + 7791 => x"00", + 7792 => x"6c", + 7793 => x"20", + 7794 => x"65", + 7795 => x"25", + 7796 => x"20", + 7797 => x"0a", + 7798 => x"00", + 7799 => x"6c", + 7800 => x"74", + 7801 => x"65", + 7802 => x"6f", + 7803 => x"28", + 7804 => x"2e", + 7805 => x"00", + 7806 => x"74", + 7807 => x"69", + 7808 => x"61", + 7809 => x"69", + 7810 => x"69", + 7811 => x"2e", + 7812 => x"00", + 7813 => x"64", + 7814 => x"62", + 7815 => x"69", + 7816 => x"2e", + 7817 => x"00", + 7818 => x"00", + 7819 => x"00", + 7820 => x"5c", + 7821 => x"25", + 7822 => x"73", + 7823 => x"00", + 7824 => x"5c", + 7825 => x"25", + 7826 => x"00", + 7827 => x"5c", + 7828 => x"00", + 7829 => x"20", + 7830 => x"6d", + 7831 => x"2e", + 7832 => x"00", + 7833 => x"6e", + 7834 => x"2e", + 7835 => x"00", + 7836 => x"62", + 7837 => x"67", + 7838 => x"74", + 7839 => x"75", + 7840 => x"2e", + 7841 => x"00", + 7842 => x"25", + 7843 => x"64", + 7844 => x"3a", + 7845 => x"25", + 7846 => x"64", + 7847 => x"00", + 7848 => x"20", + 7849 => x"66", + 7850 => x"72", + 7851 => x"6f", + 7852 => x"00", + 7853 => x"72", + 7854 => x"53", + 7855 => x"63", + 7856 => x"69", + 7857 => x"00", + 7858 => x"65", + 7859 => x"65", + 7860 => x"6d", + 7861 => x"6d", + 7862 => x"65", + 7863 => x"00", + 7864 => x"20", + 7865 => x"53", + 7866 => x"4d", + 7867 => x"25", + 7868 => x"3a", + 7869 => x"58", + 7870 => x"00", + 7871 => x"20", + 7872 => x"41", + 7873 => x"20", + 7874 => x"25", + 7875 => x"3a", + 7876 => x"58", + 7877 => x"00", + 7878 => x"20", + 7879 => x"4e", + 7880 => x"41", + 7881 => x"25", + 7882 => x"3a", + 7883 => x"58", + 7884 => x"00", + 7885 => x"20", + 7886 => x"4d", + 7887 => x"20", + 7888 => x"25", + 7889 => x"3a", + 7890 => x"58", + 7891 => x"00", + 7892 => x"20", + 7893 => x"20", + 7894 => x"20", + 7895 => x"25", + 7896 => x"3a", + 7897 => x"58", + 7898 => x"00", + 7899 => x"20", + 7900 => x"43", + 7901 => x"20", + 7902 => x"44", + 7903 => x"63", + 7904 => x"3d", + 7905 => x"64", + 7906 => x"00", + 7907 => x"20", + 7908 => x"45", + 7909 => x"20", + 7910 => x"54", + 7911 => x"72", + 7912 => x"3d", + 7913 => x"64", + 7914 => x"00", + 7915 => x"20", + 7916 => x"52", + 7917 => x"52", + 7918 => x"43", + 7919 => x"6e", + 7920 => x"3d", + 7921 => x"64", + 7922 => x"00", + 7923 => x"20", + 7924 => x"48", + 7925 => x"45", + 7926 => x"53", + 7927 => x"00", + 7928 => x"20", + 7929 => x"49", + 7930 => x"00", + 7931 => x"20", + 7932 => x"54", + 7933 => x"00", + 7934 => x"20", + 7935 => x"0a", + 7936 => x"00", + 7937 => x"20", + 7938 => x"0a", + 7939 => x"00", + 7940 => x"72", + 7941 => x"65", + 7942 => x"00", + 7943 => x"20", + 7944 => x"20", + 7945 => x"65", + 7946 => x"65", + 7947 => x"72", + 7948 => x"64", + 7949 => x"73", + 7950 => x"25", + 7951 => x"0a", + 7952 => x"00", + 7953 => x"20", + 7954 => x"20", + 7955 => x"6f", + 7956 => x"53", + 7957 => x"74", + 7958 => x"64", + 7959 => x"73", + 7960 => x"25", + 7961 => x"0a", + 7962 => x"00", + 7963 => x"20", + 7964 => x"63", + 7965 => x"74", + 7966 => x"20", + 7967 => x"72", + 7968 => x"20", + 7969 => x"20", + 7970 => x"25", + 7971 => x"0a", + 7972 => x"00", + 7973 => x"63", + 7974 => x"00", + 7975 => x"20", + 7976 => x"20", + 7977 => x"20", + 7978 => x"20", + 7979 => x"20", + 7980 => x"20", + 7981 => x"20", + 7982 => x"25", + 7983 => x"0a", + 7984 => x"00", + 7985 => x"20", + 7986 => x"74", + 7987 => x"43", + 7988 => x"6b", + 7989 => x"65", + 7990 => x"20", + 7991 => x"20", + 7992 => x"25", + 7993 => x"30", + 7994 => x"48", + 7995 => x"00", + 7996 => x"20", + 7997 => x"41", + 7998 => x"6c", + 7999 => x"20", + 8000 => x"71", + 8001 => x"20", + 8002 => x"20", + 8003 => x"25", + 8004 => x"30", + 8005 => x"48", + 8006 => x"00", + 8007 => x"20", + 8008 => x"68", + 8009 => x"65", + 8010 => x"52", + 8011 => x"43", + 8012 => x"6b", + 8013 => x"65", + 8014 => x"25", + 8015 => x"30", + 8016 => x"48", + 8017 => x"00", + 8018 => x"6c", + 8019 => x"00", + 8020 => x"69", + 8021 => x"00", + 8022 => x"78", + 8023 => x"00", + 8024 => x"00", + 8025 => x"6d", + 8026 => x"00", + 8027 => x"6e", + 8028 => x"00", + 8029 => x"d0", + 8030 => x"00", + 8031 => x"02", + 8032 => x"cc", + 8033 => x"00", + 8034 => x"03", + 8035 => x"c8", + 8036 => x"00", + 8037 => x"04", + 8038 => x"c4", + 8039 => x"00", + 8040 => x"05", + 8041 => x"c0", + 8042 => x"00", + 8043 => x"06", + 8044 => x"bc", + 8045 => x"00", + 8046 => x"07", + 8047 => x"b8", + 8048 => x"00", + 8049 => x"01", + 8050 => x"b4", + 8051 => x"00", + 8052 => x"08", + 8053 => x"b0", + 8054 => x"00", + 8055 => x"0b", + 8056 => x"ac", + 8057 => x"00", + 8058 => x"09", + 8059 => x"a8", + 8060 => x"00", + 8061 => x"0a", + 8062 => x"a4", + 8063 => x"00", + 8064 => x"0d", + 8065 => x"a0", + 8066 => x"00", + 8067 => x"0c", + 8068 => x"9c", + 8069 => x"00", + 8070 => x"0e", + 8071 => x"98", + 8072 => x"00", + 8073 => x"0f", + 8074 => x"94", + 8075 => x"00", + 8076 => x"0f", + 8077 => x"90", + 8078 => x"00", + 8079 => x"10", + 8080 => x"8c", + 8081 => x"00", + 8082 => x"11", + 8083 => x"88", + 8084 => x"00", + 8085 => x"12", + 8086 => x"84", + 8087 => x"00", + 8088 => x"13", + 8089 => x"80", + 8090 => x"00", + 8091 => x"14", + 8092 => x"7c", + 8093 => x"00", + 8094 => x"15", + 8095 => x"00", + 8096 => x"00", + 8097 => x"00", + 8098 => x"00", + 8099 => x"7e", + 8100 => x"7e", + 8101 => x"7e", + 8102 => x"00", + 8103 => x"7e", + 8104 => x"7e", + 8105 => x"7e", + 8106 => x"00", + 8107 => x"00", + 8108 => x"00", + 8109 => x"00", + 8110 => x"00", + 8111 => x"00", + 8112 => x"00", + 8113 => x"00", + 8114 => x"00", + 8115 => x"00", + 8116 => x"00", + 8117 => x"74", + 8118 => x"00", + 8119 => x"74", + 8120 => x"00", + 8121 => x"00", + 8122 => x"64", + 8123 => x"73", + 8124 => x"00", + 8125 => x"6c", + 8126 => x"74", + 8127 => x"65", + 8128 => x"20", + 8129 => x"20", + 8130 => x"74", + 8131 => x"20", + 8132 => x"65", + 8133 => x"20", + 8134 => x"2e", + 8135 => x"00", + 8136 => x"6e", + 8137 => x"6f", + 8138 => x"2f", + 8139 => x"61", + 8140 => x"68", + 8141 => x"6f", + 8142 => x"66", + 8143 => x"2c", + 8144 => x"73", + 8145 => x"69", + 8146 => x"0a", + 8147 => x"00", + 8148 => x"00", + 8149 => x"2c", + 8150 => x"3d", + 8151 => x"5d", + 8152 => x"00", + 8153 => x"00", + 8154 => x"33", + 8155 => x"00", + 8156 => x"4d", + 8157 => x"53", + 8158 => x"00", + 8159 => x"4e", + 8160 => x"20", + 8161 => x"46", + 8162 => x"32", + 8163 => x"00", + 8164 => x"4e", + 8165 => x"20", + 8166 => x"46", + 8167 => x"20", + 8168 => x"00", + 8169 => x"50", + 8170 => x"00", + 8171 => x"00", + 8172 => x"00", + 8173 => x"41", + 8174 => x"80", + 8175 => x"49", + 8176 => x"8f", + 8177 => x"4f", + 8178 => x"55", + 8179 => x"9b", + 8180 => x"9f", + 8181 => x"55", + 8182 => x"a7", + 8183 => x"ab", + 8184 => x"af", + 8185 => x"b3", + 8186 => x"b7", + 8187 => x"bb", + 8188 => x"bf", + 8189 => x"c3", + 8190 => x"c7", + 8191 => x"cb", + 8192 => x"cf", + 8193 => x"d3", + 8194 => x"d7", + 8195 => x"db", + 8196 => x"df", + 8197 => x"e3", + 8198 => x"e7", + 8199 => x"eb", + 8200 => x"ef", + 8201 => x"f3", + 8202 => x"f7", + 8203 => x"fb", + 8204 => x"ff", + 8205 => x"3b", + 8206 => x"2f", + 8207 => x"3a", + 8208 => x"7c", + 8209 => x"00", + 8210 => x"04", + 8211 => x"40", + 8212 => x"00", + 8213 => x"00", + 8214 => x"02", + 8215 => x"08", + 8216 => x"20", + 8217 => x"00", + 8218 => x"00", + 8219 => x"c8", + 8220 => x"00", + 8221 => x"00", + 8222 => x"00", + 8223 => x"d0", + 8224 => x"00", + 8225 => x"00", + 8226 => x"00", + 8227 => x"d8", + 8228 => x"00", + 8229 => x"00", + 8230 => x"00", + 8231 => x"e0", + 8232 => x"00", + 8233 => x"00", + 8234 => x"00", + 8235 => x"e8", + 8236 => x"00", + 8237 => x"00", + 8238 => x"00", + 8239 => x"f0", + 8240 => x"00", + 8241 => x"00", + 8242 => x"00", + 8243 => x"f8", + 8244 => x"00", + 8245 => x"00", + 8246 => x"00", + 8247 => x"00", + 8248 => x"00", + 8249 => x"00", + 8250 => x"00", + 8251 => x"08", + 8252 => x"00", + 8253 => x"00", + 8254 => x"00", + 8255 => x"10", + 8256 => x"00", + 8257 => x"00", + 8258 => x"00", + 8259 => x"14", + 8260 => x"00", + 8261 => x"00", + 8262 => x"00", + 8263 => x"18", + 8264 => x"00", + 8265 => x"00", + 8266 => x"00", + 8267 => x"1c", + 8268 => x"00", + 8269 => x"00", + 8270 => x"00", + 8271 => x"20", + 8272 => x"00", + 8273 => x"00", + 8274 => x"00", + 8275 => x"24", + 8276 => x"00", + 8277 => x"00", + 8278 => x"00", + 8279 => x"28", + 8280 => x"00", + 8281 => x"00", + 8282 => x"00", + 8283 => x"2c", + 8284 => x"00", + 8285 => x"00", + 8286 => x"00", + 8287 => x"34", + 8288 => x"00", + 8289 => x"00", + 8290 => x"00", + 8291 => x"38", + 8292 => x"00", + 8293 => x"00", + 8294 => x"00", + 8295 => x"40", + 8296 => x"00", + 8297 => x"00", + 8298 => x"00", + 8299 => x"48", + 8300 => x"00", + 8301 => x"00", + 8302 => x"00", + 8303 => x"50", + 8304 => x"00", + 8305 => x"00", + 8306 => x"00", + 8307 => x"58", + 8308 => x"00", + 8309 => x"00", + 8310 => x"00", + 8311 => x"60", + 8312 => x"00", + 8313 => x"00", + 8314 => x"00", + 8315 => x"68", + 8316 => x"00", + 8317 => x"00", + 8318 => x"00", + 8319 => x"70", + 8320 => x"00", + 8321 => x"00", + 8322 => x"00", + 8323 => x"00", + 8324 => x"00", + 8325 => x"ff", + 8326 => x"00", + 8327 => x"ff", + 8328 => x"00", + 8329 => x"ff", + 8330 => x"00", + 8331 => x"00", + 8332 => x"00", + 8333 => x"ff", + 8334 => x"00", + 8335 => x"00", + 8336 => x"00", + 8337 => x"00", + 8338 => x"00", + 8339 => x"00", + 8340 => x"00", + 8341 => x"00", + 8342 => x"01", + 8343 => x"01", + 8344 => x"01", + 8345 => x"00", + 8346 => x"00", + 8347 => x"00", + 8348 => x"00", + 8349 => x"00", + 8350 => x"00", + 8351 => x"00", + 8352 => x"00", + 8353 => x"00", + 8354 => x"00", + 8355 => x"00", + 8356 => x"00", + 8357 => x"00", + 8358 => x"00", + 8359 => x"00", + 8360 => x"00", + 8361 => x"00", + 8362 => x"00", + 8363 => x"00", + 8364 => x"00", + 8365 => x"00", + 8366 => x"00", + 8367 => x"00", + 8368 => x"00", + 8369 => x"00", + 8370 => x"d4", + 8371 => x"00", + 8372 => x"dc", + 8373 => x"00", + 8374 => x"e4", + 8375 => x"00", + 8376 => x"00", + 8377 => x"00", + 8378 => x"00", + others => X"00" + ); + + shared variable RAM1 : ramArray := + ( + 0 => x"83", + 1 => x"0b", + 2 => x"9b", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"8c", + 9 => x"88", + 10 => x"90", + 11 => x"88", + 12 => x"00", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"06", + 17 => x"06", + 18 => x"82", + 19 => x"2a", + 20 => x"06", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"06", + 25 => x"ff", + 26 => x"09", + 27 => x"05", + 28 => x"09", + 29 => x"ff", + 30 => x"0b", + 31 => x"04", + 32 => x"81", + 33 => x"73", + 34 => x"09", + 35 => x"73", + 36 => x"81", + 37 => x"04", + 38 => x"00", + 39 => x"00", + 40 => x"24", + 41 => x"07", + 42 => x"00", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"81", + 50 => x"05", + 51 => x"0a", + 52 => x"0a", + 53 => x"81", + 54 => x"53", + 55 => x"00", + 56 => x"26", + 57 => x"07", + 58 => x"00", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"00", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"51", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"9f", + 89 => x"05", + 90 => x"92", + 91 => x"00", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"2a", + 97 => x"06", + 98 => x"09", + 99 => x"ff", + 100 => x"53", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"53", + 105 => x"73", + 106 => x"81", + 107 => x"83", + 108 => x"07", + 109 => x"0c", + 110 => x"00", + 111 => x"00", + 112 => x"81", + 113 => x"09", + 114 => x"09", + 115 => x"06", + 116 => x"00", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"81", + 121 => x"09", + 122 => x"09", + 123 => x"81", + 124 => x"04", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"81", + 129 => x"00", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"09", + 137 => x"53", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"09", + 146 => x"51", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"06", + 153 => x"06", + 154 => x"83", + 155 => x"10", + 156 => x"06", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"06", + 161 => x"81", + 162 => x"83", + 163 => x"05", + 164 => x"0b", + 165 => x"04", + 166 => x"00", + 167 => x"00", + 168 => x"8c", + 169 => x"75", + 170 => x"0b", + 171 => x"50", + 172 => x"56", + 173 => x"0c", + 174 => x"04", + 175 => x"00", + 176 => x"8c", + 177 => x"75", + 178 => x"0b", + 179 => x"50", + 180 => x"56", + 181 => x"0c", + 182 => x"04", + 183 => x"00", + 184 => x"70", + 185 => x"06", + 186 => x"ff", + 187 => x"71", + 188 => x"72", + 189 => x"05", + 190 => x"51", + 191 => x"00", + 192 => x"70", + 193 => x"06", + 194 => x"06", + 195 => x"54", + 196 => x"09", + 197 => x"ff", + 198 => x"51", + 199 => x"00", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"05", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"05", + 233 => x"05", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"05", + 249 => x"53", + 250 => x"04", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"06", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"0b", + 265 => x"0b", + 266 => x"85", + 267 => x"0b", + 268 => x"0b", + 269 => x"a5", + 270 => x"0b", + 271 => x"0b", + 272 => x"c5", + 273 => x"0b", + 274 => x"0b", + 275 => x"e5", + 276 => x"0b", + 277 => x"0b", + 278 => x"85", + 279 => x"0b", + 280 => x"0b", + 281 => x"a5", + 282 => x"0b", + 283 => x"0b", + 284 => x"c5", + 285 => x"0b", + 286 => x"0b", + 287 => x"e5", + 288 => x"0b", + 289 => x"0b", + 290 => x"84", + 291 => x"0b", + 292 => x"0b", + 293 => x"a2", + 294 => x"0b", + 295 => x"0b", + 296 => x"c2", + 297 => x"0b", + 298 => x"0b", + 299 => x"e2", + 300 => x"0b", + 301 => x"0b", + 302 => x"82", + 303 => x"0b", + 304 => x"0b", + 305 => x"a2", + 306 => x"0b", + 307 => x"0b", + 308 => x"c2", + 309 => x"0b", + 310 => x"0b", + 311 => x"e2", + 312 => x"0b", + 313 => x"0b", + 314 => x"82", + 315 => x"0b", + 316 => x"0b", + 317 => x"a2", + 318 => x"0b", + 319 => x"0b", + 320 => x"c2", + 321 => x"0b", + 322 => x"0b", + 323 => x"e2", + 324 => x"0b", + 325 => x"0b", + 326 => x"82", + 327 => x"0b", + 328 => x"0b", + 329 => x"a2", + 330 => x"0b", + 331 => x"0b", + 332 => x"c2", + 333 => x"0b", + 334 => x"0b", + 335 => x"e2", + 336 => x"0b", + 337 => x"0b", + 338 => x"82", + 339 => x"0b", + 340 => x"0b", + 341 => x"a0", + 342 => x"0b", + 343 => x"ff", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"8c", + 385 => x"85", + 386 => x"c1", + 387 => x"85", + 388 => x"a0", + 389 => x"85", + 390 => x"ce", + 391 => x"85", + 392 => x"a0", + 393 => x"85", + 394 => x"ce", + 395 => x"85", + 396 => x"a0", + 397 => x"85", + 398 => x"ce", + 399 => x"85", + 400 => x"a0", + 401 => x"85", + 402 => x"d5", + 403 => x"85", + 404 => x"a0", + 405 => x"85", + 406 => x"d6", + 407 => x"85", + 408 => x"a0", + 409 => x"85", + 410 => x"cf", + 411 => x"85", + 412 => x"a0", + 413 => x"85", + 414 => x"d6", + 415 => x"85", + 416 => x"a0", + 417 => x"85", + 418 => x"d8", + 419 => x"85", + 420 => x"a0", + 421 => x"85", + 422 => x"d4", + 423 => x"85", + 424 => x"a0", + 425 => x"85", + 426 => x"cf", + 427 => x"85", + 428 => x"a0", + 429 => x"85", + 430 => x"d4", + 431 => x"85", + 432 => x"a0", + 433 => x"85", + 434 => x"d5", + 435 => x"85", + 436 => x"a0", + 437 => x"85", + 438 => x"c3", + 439 => x"85", + 440 => x"a0", + 441 => x"85", + 442 => x"c3", + 443 => x"85", + 444 => x"a0", + 445 => x"85", + 446 => x"c4", + 447 => x"f8", + 448 => x"90", + 449 => x"f8", + 450 => x"2d", + 451 => x"08", + 452 => x"04", + 453 => x"0c", + 454 => x"82", + 455 => x"82", + 456 => x"82", + 457 => x"81", + 458 => x"82", + 459 => x"82", + 460 => x"82", + 461 => x"81", + 462 => x"82", + 463 => x"82", + 464 => x"82", + 465 => x"81", + 466 => x"82", + 467 => x"82", + 468 => x"82", + 469 => x"81", + 470 => x"82", + 471 => x"82", + 472 => x"82", + 473 => x"81", + 474 => x"82", + 475 => x"82", + 476 => x"82", + 477 => x"81", + 478 => x"82", + 479 => x"82", + 480 => x"82", + 481 => x"81", + 482 => x"82", + 483 => x"82", + 484 => x"82", + 485 => x"81", + 486 => x"82", + 487 => x"82", + 488 => x"82", + 489 => x"81", + 490 => x"82", + 491 => x"82", + 492 => x"82", + 493 => x"81", + 494 => x"82", + 495 => x"82", + 496 => x"82", + 497 => x"81", + 498 => x"82", + 499 => x"82", + 500 => x"82", + 501 => x"81", + 502 => x"82", + 503 => x"82", + 504 => x"82", + 505 => x"81", + 506 => x"82", + 507 => x"82", + 508 => x"82", + 509 => x"81", + 510 => x"82", + 511 => x"82", + 512 => x"82", + 513 => x"81", + 514 => x"82", + 515 => x"82", + 516 => x"82", + 517 => x"81", + 518 => x"82", + 519 => x"82", + 520 => x"82", + 521 => x"81", + 522 => x"82", + 523 => x"82", + 524 => x"82", + 525 => x"81", + 526 => x"82", + 527 => x"82", + 528 => x"82", + 529 => x"81", + 530 => x"82", + 531 => x"82", + 532 => x"82", + 533 => x"81", + 534 => x"82", + 535 => x"82", + 536 => x"82", + 537 => x"81", + 538 => x"82", + 539 => x"82", + 540 => x"82", + 541 => x"81", + 542 => x"82", + 543 => x"82", + 544 => x"82", + 545 => x"81", + 546 => x"82", + 547 => x"82", + 548 => x"82", + 549 => x"81", + 550 => x"82", + 551 => x"82", + 552 => x"82", + 553 => x"81", + 554 => x"82", + 555 => x"82", + 556 => x"82", + 557 => x"81", + 558 => x"82", + 559 => x"82", + 560 => x"82", + 561 => x"81", + 562 => x"82", + 563 => x"82", + 564 => x"82", + 565 => x"80", + 566 => x"82", + 567 => x"82", + 568 => x"82", + 569 => x"80", + 570 => x"82", + 571 => x"82", + 572 => x"82", + 573 => x"80", + 574 => x"82", + 575 => x"82", + 576 => x"82", + 577 => x"bb", + 578 => x"85", + 579 => x"a0", + 580 => x"85", + 581 => x"93", + 582 => x"f8", + 583 => x"90", + 584 => x"f8", + 585 => x"80", + 586 => x"f8", + 587 => x"90", + 588 => x"f8", + 589 => x"2d", + 590 => x"08", + 591 => x"04", + 592 => x"00", + 593 => x"10", + 594 => x"10", + 595 => x"10", + 596 => x"10", + 597 => x"10", + 598 => x"10", + 599 => x"10", + 600 => x"53", + 601 => x"00", + 602 => x"06", + 603 => x"09", + 604 => x"05", + 605 => x"2b", + 606 => x"06", + 607 => x"04", + 608 => x"72", + 609 => x"05", + 610 => x"05", + 611 => x"72", + 612 => x"53", + 613 => x"51", + 614 => x"04", + 615 => x"70", + 616 => x"27", + 617 => x"71", + 618 => x"53", + 619 => x"0b", + 620 => x"8c", + 621 => x"9d", + 622 => x"85", + 623 => x"82", + 624 => x"fe", + 625 => x"85", + 626 => x"05", + 627 => x"f8", + 628 => x"0c", + 629 => x"08", + 630 => x"52", + 631 => x"85", + 632 => x"05", + 633 => x"82", + 634 => x"fc", + 635 => x"81", + 636 => x"51", + 637 => x"83", + 638 => x"82", + 639 => x"fc", + 640 => x"05", + 641 => x"08", + 642 => x"82", + 643 => x"fc", + 644 => x"85", + 645 => x"05", + 646 => x"82", + 647 => x"51", + 648 => x"82", + 649 => x"04", + 650 => x"08", + 651 => x"f8", + 652 => x"0d", + 653 => x"08", + 654 => x"82", + 655 => x"fc", + 656 => x"85", + 657 => x"05", + 658 => x"33", + 659 => x"08", + 660 => x"81", + 661 => x"f8", + 662 => x"0c", + 663 => x"08", + 664 => x"53", + 665 => x"34", + 666 => x"08", + 667 => x"81", + 668 => x"f8", + 669 => x"0c", + 670 => x"06", + 671 => x"2e", + 672 => x"be", + 673 => x"f8", + 674 => x"08", + 675 => x"ec", + 676 => x"3d", + 677 => x"f8", + 678 => x"85", + 679 => x"82", + 680 => x"fd", + 681 => x"85", + 682 => x"05", + 683 => x"f8", + 684 => x"0c", + 685 => x"08", + 686 => x"82", + 687 => x"f8", + 688 => x"85", + 689 => x"05", + 690 => x"80", + 691 => x"85", + 692 => x"05", + 693 => x"82", + 694 => x"90", + 695 => x"85", + 696 => x"05", + 697 => x"82", + 698 => x"90", + 699 => x"85", + 700 => x"05", + 701 => x"ba", + 702 => x"f8", + 703 => x"08", + 704 => x"82", + 705 => x"f8", + 706 => x"05", + 707 => x"08", + 708 => x"82", + 709 => x"fc", + 710 => x"52", + 711 => x"82", + 712 => x"fc", + 713 => x"05", + 714 => x"08", + 715 => x"ff", + 716 => x"85", + 717 => x"05", + 718 => x"85", + 719 => x"85", + 720 => x"85", + 721 => x"82", + 722 => x"02", + 723 => x"0c", + 724 => x"82", + 725 => x"90", + 726 => x"2e", + 727 => x"82", + 728 => x"8c", + 729 => x"71", + 730 => x"f8", + 731 => x"08", + 732 => x"85", + 733 => x"05", + 734 => x"f8", + 735 => x"08", + 736 => x"81", + 737 => x"54", + 738 => x"71", + 739 => x"80", + 740 => x"85", + 741 => x"05", + 742 => x"33", + 743 => x"08", + 744 => x"81", + 745 => x"f8", + 746 => x"0c", + 747 => x"06", + 748 => x"8d", + 749 => x"82", + 750 => x"fc", + 751 => x"9b", + 752 => x"f8", + 753 => x"08", + 754 => x"85", + 755 => x"05", + 756 => x"f8", + 757 => x"08", + 758 => x"38", + 759 => x"82", + 760 => x"90", + 761 => x"2e", + 762 => x"82", + 763 => x"88", + 764 => x"33", + 765 => x"8d", + 766 => x"82", + 767 => x"fc", + 768 => x"d7", + 769 => x"f8", + 770 => x"08", + 771 => x"85", + 772 => x"05", + 773 => x"f8", + 774 => x"08", + 775 => x"52", + 776 => x"81", + 777 => x"f8", + 778 => x"0c", + 779 => x"85", + 780 => x"05", + 781 => x"82", + 782 => x"8c", + 783 => x"33", + 784 => x"70", + 785 => x"08", + 786 => x"53", + 787 => x"53", + 788 => x"0b", + 789 => x"08", + 790 => x"82", + 791 => x"fc", + 792 => x"85", + 793 => x"3d", + 794 => x"f8", + 795 => x"85", + 796 => x"82", + 797 => x"fe", + 798 => x"85", + 799 => x"05", + 800 => x"f8", + 801 => x"0c", + 802 => x"08", + 803 => x"80", + 804 => x"38", + 805 => x"08", + 806 => x"81", + 807 => x"f8", + 808 => x"0c", + 809 => x"08", + 810 => x"ff", + 811 => x"f8", + 812 => x"0c", + 813 => x"08", + 814 => x"80", + 815 => x"82", + 816 => x"8c", + 817 => x"70", + 818 => x"08", + 819 => x"52", + 820 => x"34", + 821 => x"08", + 822 => x"81", + 823 => x"f8", + 824 => x"0c", + 825 => x"82", + 826 => x"88", + 827 => x"82", + 828 => x"51", + 829 => x"82", + 830 => x"04", + 831 => x"08", + 832 => x"f8", + 833 => x"0d", + 834 => x"85", + 835 => x"05", + 836 => x"f8", + 837 => x"08", + 838 => x"38", + 839 => x"08", + 840 => x"30", + 841 => x"08", + 842 => x"80", + 843 => x"f8", + 844 => x"0c", + 845 => x"08", + 846 => x"8a", + 847 => x"82", + 848 => x"f4", + 849 => x"85", + 850 => x"05", + 851 => x"f8", + 852 => x"0c", + 853 => x"08", + 854 => x"80", + 855 => x"82", + 856 => x"8c", + 857 => x"82", + 858 => x"8c", + 859 => x"0b", + 860 => x"08", + 861 => x"82", + 862 => x"fc", + 863 => x"38", + 864 => x"85", + 865 => x"05", + 866 => x"f8", + 867 => x"08", + 868 => x"08", + 869 => x"80", + 870 => x"f8", + 871 => x"08", + 872 => x"f8", + 873 => x"08", + 874 => x"3f", + 875 => x"08", + 876 => x"f8", + 877 => x"0c", + 878 => x"f8", + 879 => x"08", + 880 => x"38", + 881 => x"08", + 882 => x"30", + 883 => x"08", + 884 => x"82", + 885 => x"f8", + 886 => x"82", + 887 => x"54", + 888 => x"82", + 889 => x"04", + 890 => x"08", + 891 => x"f8", + 892 => x"0d", + 893 => x"85", + 894 => x"05", + 895 => x"f8", + 896 => x"08", + 897 => x"38", + 898 => x"08", + 899 => x"30", + 900 => x"08", + 901 => x"81", + 902 => x"f8", + 903 => x"0c", + 904 => x"08", + 905 => x"80", + 906 => x"82", + 907 => x"8c", + 908 => x"82", + 909 => x"8c", + 910 => x"53", + 911 => x"08", + 912 => x"52", + 913 => x"08", + 914 => x"51", + 915 => x"82", + 916 => x"70", + 917 => x"08", + 918 => x"54", + 919 => x"08", + 920 => x"80", + 921 => x"82", + 922 => x"f8", + 923 => x"82", + 924 => x"f8", + 925 => x"85", + 926 => x"05", + 927 => x"85", + 928 => x"87", + 929 => x"85", + 930 => x"82", + 931 => x"02", + 932 => x"0c", + 933 => x"80", + 934 => x"f8", + 935 => x"0c", + 936 => x"08", + 937 => x"81", + 938 => x"70", + 939 => x"85", + 940 => x"05", + 941 => x"85", + 942 => x"05", + 943 => x"85", + 944 => x"05", + 945 => x"f8", + 946 => x"08", + 947 => x"85", + 948 => x"05", + 949 => x"f8", + 950 => x"08", + 951 => x"f8", + 952 => x"0c", + 953 => x"51", + 954 => x"08", + 955 => x"80", + 956 => x"ff", + 957 => x"85", + 958 => x"05", + 959 => x"85", + 960 => x"83", + 961 => x"85", + 962 => x"82", + 963 => x"02", + 964 => x"0c", + 965 => x"80", + 966 => x"f8", + 967 => x"08", + 968 => x"f8", + 969 => x"08", + 970 => x"3f", + 971 => x"08", + 972 => x"ec", + 973 => x"3d", + 974 => x"f8", + 975 => x"85", + 976 => x"82", + 977 => x"fd", + 978 => x"53", + 979 => x"08", + 980 => x"52", + 981 => x"08", + 982 => x"51", + 983 => x"85", + 984 => x"82", + 985 => x"54", + 986 => x"82", + 987 => x"04", + 988 => x"08", + 989 => x"f8", + 990 => x"0d", + 991 => x"85", + 992 => x"05", + 993 => x"82", + 994 => x"f8", + 995 => x"85", + 996 => x"05", + 997 => x"f8", + 998 => x"08", + 999 => x"82", + 1000 => x"fc", + 1001 => x"2e", + 1002 => x"0b", + 1003 => x"08", + 1004 => x"24", + 1005 => x"85", + 1006 => x"05", + 1007 => x"85", + 1008 => x"05", + 1009 => x"f8", + 1010 => x"08", + 1011 => x"f8", + 1012 => x"0c", + 1013 => x"82", + 1014 => x"fc", + 1015 => x"2e", + 1016 => x"82", + 1017 => x"8c", + 1018 => x"85", + 1019 => x"05", + 1020 => x"38", + 1021 => x"08", + 1022 => x"82", + 1023 => x"8c", + 1024 => x"82", + 1025 => x"88", + 1026 => x"85", + 1027 => x"05", + 1028 => x"f8", + 1029 => x"08", + 1030 => x"f8", + 1031 => x"0c", + 1032 => x"08", + 1033 => x"81", + 1034 => x"f8", + 1035 => x"0c", + 1036 => x"08", + 1037 => x"81", + 1038 => x"f8", + 1039 => x"0c", + 1040 => x"82", + 1041 => x"90", + 1042 => x"2e", + 1043 => x"85", + 1044 => x"05", + 1045 => x"85", + 1046 => x"05", + 1047 => x"39", + 1048 => x"08", + 1049 => x"70", + 1050 => x"08", + 1051 => x"51", + 1052 => x"08", + 1053 => x"82", + 1054 => x"85", + 1055 => x"85", + 1056 => x"f9", + 1057 => x"70", + 1058 => x"56", + 1059 => x"2e", + 1060 => x"95", + 1061 => x"51", + 1062 => x"82", + 1063 => x"15", + 1064 => x"16", + 1065 => x"cd", + 1066 => x"54", + 1067 => x"09", + 1068 => x"38", + 1069 => x"f1", + 1070 => x"76", + 1071 => x"80", + 1072 => x"08", + 1073 => x"f2", + 1074 => x"ec", + 1075 => x"52", + 1076 => x"f4", + 1077 => x"85", + 1078 => x"38", + 1079 => x"54", + 1080 => x"ff", + 1081 => x"17", + 1082 => x"06", + 1083 => x"77", + 1084 => x"ff", + 1085 => x"85", + 1086 => x"3d", + 1087 => x"3d", + 1088 => x"71", + 1089 => x"8d", + 1090 => x"2b", + 1091 => x"8c", + 1092 => x"81", + 1093 => x"81", + 1094 => x"eb", + 1095 => x"f9", + 1096 => x"94", + 1097 => x"39", + 1098 => x"51", + 1099 => x"81", + 1100 => x"80", + 1101 => x"eb", + 1102 => x"dd", + 1103 => x"dc", + 1104 => x"39", + 1105 => x"51", + 1106 => x"81", + 1107 => x"80", + 1108 => x"ec", + 1109 => x"c1", + 1110 => x"b4", + 1111 => x"81", + 1112 => x"b5", + 1113 => x"e4", + 1114 => x"81", + 1115 => x"a9", + 1116 => x"a4", + 1117 => x"81", + 1118 => x"9d", + 1119 => x"d8", + 1120 => x"81", + 1121 => x"91", + 1122 => x"88", + 1123 => x"81", + 1124 => x"85", + 1125 => x"ac", + 1126 => x"3f", + 1127 => x"04", + 1128 => x"77", + 1129 => x"74", + 1130 => x"92", + 1131 => x"52", + 1132 => x"d7", + 1133 => x"82", + 1134 => x"51", + 1135 => x"e8", + 1136 => x"fa", + 1137 => x"85", + 1138 => x"75", + 1139 => x"3f", + 1140 => x"08", + 1141 => x"75", + 1142 => x"bc", + 1143 => x"3f", + 1144 => x"04", + 1145 => x"66", + 1146 => x"80", + 1147 => x"5b", + 1148 => x"78", + 1149 => x"70", + 1150 => x"25", + 1151 => x"59", + 1152 => x"87", + 1153 => x"38", + 1154 => x"76", + 1155 => x"ff", + 1156 => x"93", + 1157 => x"86", + 1158 => x"76", + 1159 => x"70", + 1160 => x"86", + 1161 => x"85", + 1162 => x"82", + 1163 => x"b9", + 1164 => x"ec", + 1165 => x"98", + 1166 => x"85", + 1167 => x"96", + 1168 => x"54", + 1169 => x"77", + 1170 => x"81", + 1171 => x"82", + 1172 => x"57", + 1173 => x"08", + 1174 => x"55", + 1175 => x"89", + 1176 => x"75", + 1177 => x"d7", + 1178 => x"d8", + 1179 => x"92", + 1180 => x"09", + 1181 => x"78", + 1182 => x"7b", + 1183 => x"70", + 1184 => x"06", + 1185 => x"56", + 1186 => x"90", + 1187 => x"e0", + 1188 => x"98", + 1189 => x"78", + 1190 => x"3f", + 1191 => x"82", + 1192 => x"96", + 1193 => x"f9", + 1194 => x"02", + 1195 => x"05", + 1196 => x"ff", + 1197 => x"7a", + 1198 => x"fe", + 1199 => x"85", + 1200 => x"38", + 1201 => x"88", + 1202 => x"2e", + 1203 => x"39", + 1204 => x"54", + 1205 => x"53", + 1206 => x"51", + 1207 => x"85", + 1208 => x"83", + 1209 => x"76", + 1210 => x"0c", + 1211 => x"04", + 1212 => x"7f", + 1213 => x"8c", + 1214 => x"05", + 1215 => x"15", + 1216 => x"5c", + 1217 => x"5e", + 1218 => x"ee", + 1219 => x"cc", + 1220 => x"f0", + 1221 => x"3f", + 1222 => x"79", + 1223 => x"38", + 1224 => x"89", + 1225 => x"2e", + 1226 => x"c1", + 1227 => x"53", + 1228 => x"8d", + 1229 => x"52", + 1230 => x"51", + 1231 => x"88", + 1232 => x"80", + 1233 => x"3f", + 1234 => x"bf", + 1235 => x"53", + 1236 => x"8d", + 1237 => x"52", + 1238 => x"51", + 1239 => x"88", + 1240 => x"fc", + 1241 => x"3f", + 1242 => x"9f", + 1243 => x"53", + 1244 => x"8d", + 1245 => x"52", + 1246 => x"51", + 1247 => x"88", + 1248 => x"90", + 1249 => x"3f", + 1250 => x"a0", + 1251 => x"3f", + 1252 => x"81", + 1253 => x"a7", + 1254 => x"55", + 1255 => x"bb", + 1256 => x"70", + 1257 => x"80", + 1258 => x"27", + 1259 => x"56", + 1260 => x"74", + 1261 => x"81", + 1262 => x"06", + 1263 => x"06", + 1264 => x"80", + 1265 => x"73", + 1266 => x"85", + 1267 => x"83", + 1268 => x"a6", + 1269 => x"15", + 1270 => x"81", + 1271 => x"a7", + 1272 => x"18", + 1273 => x"58", + 1274 => x"82", + 1275 => x"98", + 1276 => x"2c", + 1277 => x"a0", + 1278 => x"06", + 1279 => x"e5", + 1280 => x"ec", + 1281 => x"70", + 1282 => x"a0", + 1283 => x"81", + 1284 => x"32", + 1285 => x"05", + 1286 => x"73", + 1287 => x"51", + 1288 => x"57", + 1289 => x"73", + 1290 => x"76", + 1291 => x"81", + 1292 => x"80", + 1293 => x"7c", + 1294 => x"78", + 1295 => x"38", + 1296 => x"82", + 1297 => x"8f", + 1298 => x"fc", + 1299 => x"9b", + 1300 => x"ef", + 1301 => x"ef", + 1302 => x"ab", + 1303 => x"84", + 1304 => x"a4", + 1305 => x"ef", + 1306 => x"ef", + 1307 => x"84", + 1308 => x"81", + 1309 => x"ab", + 1310 => x"80", + 1311 => x"a0", + 1312 => x"3d", + 1313 => x"3d", + 1314 => x"96", + 1315 => x"a4", + 1316 => x"51", + 1317 => x"81", + 1318 => x"98", + 1319 => x"51", + 1320 => x"72", + 1321 => x"81", + 1322 => x"71", + 1323 => x"38", + 1324 => x"cd", + 1325 => x"f4", + 1326 => x"3f", + 1327 => x"c1", + 1328 => x"2a", + 1329 => x"51", + 1330 => x"2e", + 1331 => x"51", + 1332 => x"81", + 1333 => x"98", + 1334 => x"51", + 1335 => x"72", + 1336 => x"81", + 1337 => x"71", + 1338 => x"38", + 1339 => x"91", + 1340 => x"98", + 1341 => x"3f", + 1342 => x"85", + 1343 => x"2a", + 1344 => x"51", + 1345 => x"2e", + 1346 => x"51", + 1347 => x"81", + 1348 => x"97", + 1349 => x"51", + 1350 => x"72", + 1351 => x"81", + 1352 => x"71", + 1353 => x"38", + 1354 => x"d5", + 1355 => x"c0", + 1356 => x"3f", + 1357 => x"c9", + 1358 => x"2a", + 1359 => x"51", + 1360 => x"2e", + 1361 => x"51", + 1362 => x"81", + 1363 => x"97", + 1364 => x"51", + 1365 => x"72", + 1366 => x"81", + 1367 => x"71", + 1368 => x"38", + 1369 => x"99", + 1370 => x"e8", + 1371 => x"3f", + 1372 => x"8d", + 1373 => x"2a", + 1374 => x"51", + 1375 => x"2e", + 1376 => x"51", + 1377 => x"81", + 1378 => x"96", + 1379 => x"51", + 1380 => x"a2", + 1381 => x"3d", + 1382 => x"3d", + 1383 => x"84", + 1384 => x"33", + 1385 => x"56", + 1386 => x"51", + 1387 => x"0b", + 1388 => x"e8", + 1389 => x"ab", + 1390 => x"81", + 1391 => x"82", + 1392 => x"80", + 1393 => x"82", + 1394 => x"09", + 1395 => x"82", + 1396 => x"07", + 1397 => x"71", + 1398 => x"54", + 1399 => x"82", + 1400 => x"0b", + 1401 => x"e8", + 1402 => x"81", + 1403 => x"06", + 1404 => x"9c", + 1405 => x"52", + 1406 => x"b9", + 1407 => x"85", + 1408 => x"2e", + 1409 => x"85", + 1410 => x"a2", + 1411 => x"39", + 1412 => x"51", + 1413 => x"3f", + 1414 => x"0b", + 1415 => x"34", + 1416 => x"80", + 1417 => x"73", + 1418 => x"81", + 1419 => x"81", + 1420 => x"74", + 1421 => x"b5", + 1422 => x"0b", + 1423 => x"0c", + 1424 => x"04", + 1425 => x"80", + 1426 => x"9c", + 1427 => x"5d", + 1428 => x"51", + 1429 => x"3f", + 1430 => x"08", + 1431 => x"59", + 1432 => x"09", + 1433 => x"38", + 1434 => x"52", + 1435 => x"52", + 1436 => x"3f", + 1437 => x"52", + 1438 => x"51", + 1439 => x"3f", + 1440 => x"08", + 1441 => x"38", + 1442 => x"51", + 1443 => x"81", + 1444 => x"81", + 1445 => x"a1", + 1446 => x"3d", + 1447 => x"80", + 1448 => x"51", + 1449 => x"b4", + 1450 => x"05", + 1451 => x"3f", + 1452 => x"08", + 1453 => x"90", + 1454 => x"78", + 1455 => x"87", + 1456 => x"80", + 1457 => x"38", + 1458 => x"81", + 1459 => x"bd", + 1460 => x"78", + 1461 => x"bb", + 1462 => x"2e", + 1463 => x"8a", + 1464 => x"80", + 1465 => x"94", + 1466 => x"c0", + 1467 => x"38", + 1468 => x"82", + 1469 => x"a4", + 1470 => x"f9", + 1471 => x"38", + 1472 => x"24", + 1473 => x"80", + 1474 => x"fa", + 1475 => x"f8", + 1476 => x"38", + 1477 => x"78", + 1478 => x"89", + 1479 => x"81", + 1480 => x"38", + 1481 => x"2e", + 1482 => x"89", + 1483 => x"81", + 1484 => x"e2", + 1485 => x"39", + 1486 => x"80", + 1487 => x"84", + 1488 => x"90", + 1489 => x"ec", + 1490 => x"fe", + 1491 => x"3d", + 1492 => x"53", + 1493 => x"51", + 1494 => x"82", + 1495 => x"80", + 1496 => x"38", + 1497 => x"f8", + 1498 => x"84", + 1499 => x"e4", + 1500 => x"ec", + 1501 => x"82", + 1502 => x"42", + 1503 => x"51", + 1504 => x"63", + 1505 => x"79", + 1506 => x"e9", + 1507 => x"78", + 1508 => x"05", + 1509 => x"7a", + 1510 => x"81", + 1511 => x"3d", + 1512 => x"53", + 1513 => x"51", + 1514 => x"82", + 1515 => x"80", + 1516 => x"38", + 1517 => x"fc", + 1518 => x"84", + 1519 => x"94", + 1520 => x"ec", + 1521 => x"fd", + 1522 => x"3d", + 1523 => x"53", + 1524 => x"51", + 1525 => x"82", + 1526 => x"80", + 1527 => x"38", + 1528 => x"51", + 1529 => x"63", + 1530 => x"27", + 1531 => x"61", + 1532 => x"81", + 1533 => x"79", + 1534 => x"05", + 1535 => x"b4", + 1536 => x"11", + 1537 => x"05", + 1538 => x"3f", + 1539 => x"08", + 1540 => x"ff", + 1541 => x"fe", + 1542 => x"ff", + 1543 => x"a6", + 1544 => x"85", + 1545 => x"2e", + 1546 => x"b4", + 1547 => x"11", + 1548 => x"05", + 1549 => x"3f", + 1550 => x"08", + 1551 => x"d3", + 1552 => x"b0", + 1553 => x"3f", + 1554 => x"63", + 1555 => x"61", + 1556 => x"33", + 1557 => x"78", + 1558 => x"38", + 1559 => x"54", + 1560 => x"79", + 1561 => x"c0", + 1562 => x"3f", + 1563 => x"81", + 1564 => x"d6", + 1565 => x"d8", + 1566 => x"39", + 1567 => x"80", + 1568 => x"84", + 1569 => x"cc", + 1570 => x"ec", + 1571 => x"38", + 1572 => x"33", + 1573 => x"2e", + 1574 => x"84", + 1575 => x"80", + 1576 => x"84", + 1577 => x"78", + 1578 => x"38", + 1579 => x"08", + 1580 => x"82", + 1581 => x"59", + 1582 => x"88", + 1583 => x"a0", + 1584 => x"39", + 1585 => x"33", + 1586 => x"2e", + 1587 => x"84", + 1588 => x"9a", + 1589 => x"d6", + 1590 => x"80", + 1591 => x"82", + 1592 => x"44", + 1593 => x"84", + 1594 => x"80", + 1595 => x"3d", + 1596 => x"53", + 1597 => x"51", + 1598 => x"82", + 1599 => x"80", + 1600 => x"84", + 1601 => x"78", + 1602 => x"38", + 1603 => x"08", + 1604 => x"39", + 1605 => x"33", + 1606 => x"2e", + 1607 => x"84", + 1608 => x"bb", + 1609 => x"da", + 1610 => x"80", + 1611 => x"82", + 1612 => x"43", + 1613 => x"84", + 1614 => x"78", + 1615 => x"38", + 1616 => x"08", + 1617 => x"82", + 1618 => x"59", + 1619 => x"88", + 1620 => x"b4", + 1621 => x"39", + 1622 => x"08", + 1623 => x"b4", + 1624 => x"11", + 1625 => x"05", + 1626 => x"3f", + 1627 => x"08", + 1628 => x"38", + 1629 => x"5c", + 1630 => x"83", + 1631 => x"7a", + 1632 => x"09", + 1633 => x"72", + 1634 => x"70", + 1635 => x"51", + 1636 => x"80", + 1637 => x"7a", + 1638 => x"38", + 1639 => x"f2", + 1640 => x"c8", + 1641 => x"63", + 1642 => x"62", + 1643 => x"f2", + 1644 => x"f2", + 1645 => x"b4", + 1646 => x"39", + 1647 => x"80", + 1648 => x"84", + 1649 => x"8c", + 1650 => x"ec", + 1651 => x"f9", + 1652 => x"3d", + 1653 => x"53", + 1654 => x"51", + 1655 => x"82", + 1656 => x"80", + 1657 => x"63", + 1658 => x"cb", + 1659 => x"34", + 1660 => x"44", + 1661 => x"fc", + 1662 => x"84", + 1663 => x"d4", + 1664 => x"ec", + 1665 => x"f9", + 1666 => x"70", + 1667 => x"81", + 1668 => x"a0", + 1669 => x"f8", + 1670 => x"a1", + 1671 => x"45", + 1672 => x"78", + 1673 => x"eb", + 1674 => x"27", + 1675 => x"3d", + 1676 => x"53", + 1677 => x"51", + 1678 => x"82", + 1679 => x"80", + 1680 => x"63", + 1681 => x"cb", + 1682 => x"34", + 1683 => x"44", + 1684 => x"81", + 1685 => x"9a", + 1686 => x"ae", + 1687 => x"fe", + 1688 => x"ff", + 1689 => x"a3", + 1690 => x"85", + 1691 => x"2e", + 1692 => x"b4", + 1693 => x"11", + 1694 => x"05", + 1695 => x"3f", + 1696 => x"08", + 1697 => x"38", + 1698 => x"be", + 1699 => x"70", + 1700 => x"23", + 1701 => x"3d", + 1702 => x"53", + 1703 => x"51", + 1704 => x"82", + 1705 => x"e0", + 1706 => x"39", + 1707 => x"54", + 1708 => x"8c", + 1709 => x"3f", + 1710 => x"79", + 1711 => x"3f", + 1712 => x"33", + 1713 => x"2e", + 1714 => x"78", + 1715 => x"38", + 1716 => x"41", + 1717 => x"3d", + 1718 => x"53", + 1719 => x"51", + 1720 => x"82", + 1721 => x"80", + 1722 => x"60", + 1723 => x"05", + 1724 => x"82", + 1725 => x"78", + 1726 => x"39", + 1727 => x"51", + 1728 => x"ff", + 1729 => x"3d", + 1730 => x"53", + 1731 => x"51", + 1732 => x"82", + 1733 => x"80", + 1734 => x"38", + 1735 => x"f0", + 1736 => x"84", + 1737 => x"a8", + 1738 => x"ec", + 1739 => x"a0", + 1740 => x"71", + 1741 => x"84", + 1742 => x"3d", + 1743 => x"53", + 1744 => x"51", + 1745 => x"82", + 1746 => x"e5", + 1747 => x"39", + 1748 => x"54", + 1749 => x"98", + 1750 => x"3f", + 1751 => x"79", + 1752 => x"3f", + 1753 => x"33", + 1754 => x"2e", + 1755 => x"9f", + 1756 => x"38", + 1757 => x"f0", + 1758 => x"84", + 1759 => x"d0", + 1760 => x"ec", + 1761 => x"8d", + 1762 => x"71", + 1763 => x"84", + 1764 => x"bc", + 1765 => x"84", + 1766 => x"3f", + 1767 => x"b4", + 1768 => x"11", + 1769 => x"05", + 1770 => x"3f", + 1771 => x"08", + 1772 => x"df", + 1773 => x"81", + 1774 => x"9d", + 1775 => x"59", + 1776 => x"3d", + 1777 => x"53", + 1778 => x"51", + 1779 => x"82", + 1780 => x"80", + 1781 => x"38", + 1782 => x"f3", + 1783 => x"fc", + 1784 => x"78", + 1785 => x"ec", + 1786 => x"f5", + 1787 => x"85", + 1788 => x"81", + 1789 => x"9c", + 1790 => x"97", + 1791 => x"f8", + 1792 => x"3f", + 1793 => x"f5", + 1794 => x"f4", + 1795 => x"dc", + 1796 => x"ff", + 1797 => x"ef", + 1798 => x"39", + 1799 => x"33", + 1800 => x"2e", + 1801 => x"7d", + 1802 => x"78", + 1803 => x"d0", + 1804 => x"ff", + 1805 => x"83", + 1806 => x"85", + 1807 => x"81", + 1808 => x"2e", + 1809 => x"82", + 1810 => x"7a", + 1811 => x"38", + 1812 => x"7a", + 1813 => x"38", + 1814 => x"81", + 1815 => x"7b", + 1816 => x"ac", + 1817 => x"81", + 1818 => x"b4", + 1819 => x"05", + 1820 => x"3f", + 1821 => x"f4", + 1822 => x"3d", + 1823 => x"51", + 1824 => x"a9", + 1825 => x"81", + 1826 => x"80", + 1827 => x"c0", + 1828 => x"ff", + 1829 => x"9b", + 1830 => x"39", + 1831 => x"53", + 1832 => x"52", + 1833 => x"b0", + 1834 => x"c6", + 1835 => x"90", + 1836 => x"fc", + 1837 => x"64", + 1838 => x"82", + 1839 => x"82", + 1840 => x"b4", + 1841 => x"05", + 1842 => x"3f", + 1843 => x"08", + 1844 => x"08", + 1845 => x"81", + 1846 => x"07", + 1847 => x"5b", + 1848 => x"5a", + 1849 => x"83", + 1850 => x"78", + 1851 => x"78", + 1852 => x"38", + 1853 => x"81", + 1854 => x"59", + 1855 => x"38", + 1856 => x"7d", + 1857 => x"59", + 1858 => x"7e", + 1859 => x"81", + 1860 => x"38", + 1861 => x"51", + 1862 => x"f2", + 1863 => x"3d", + 1864 => x"82", + 1865 => x"87", + 1866 => x"70", + 1867 => x"87", + 1868 => x"72", + 1869 => x"3f", + 1870 => x"08", + 1871 => x"08", + 1872 => x"84", + 1873 => x"51", + 1874 => x"72", + 1875 => x"08", + 1876 => x"87", + 1877 => x"70", + 1878 => x"87", + 1879 => x"72", + 1880 => x"3f", + 1881 => x"08", + 1882 => x"08", + 1883 => x"84", + 1884 => x"51", + 1885 => x"72", + 1886 => x"08", + 1887 => x"8c", + 1888 => x"87", + 1889 => x"0c", + 1890 => x"0b", + 1891 => x"94", + 1892 => x"9a", + 1893 => x"f4", + 1894 => x"95", + 1895 => x"f8", + 1896 => x"3f", + 1897 => x"81", + 1898 => x"93", + 1899 => x"f4", + 1900 => x"b8", + 1901 => x"51", + 1902 => x"81", + 1903 => x"3f", + 1904 => x"80", + 1905 => x"0d", + 1906 => x"53", + 1907 => x"52", + 1908 => x"82", + 1909 => x"81", + 1910 => x"07", + 1911 => x"52", + 1912 => x"e8", + 1913 => x"85", + 1914 => x"3d", + 1915 => x"3d", + 1916 => x"08", + 1917 => x"73", + 1918 => x"74", + 1919 => x"38", + 1920 => x"70", + 1921 => x"81", + 1922 => x"81", + 1923 => x"39", + 1924 => x"70", + 1925 => x"81", + 1926 => x"81", + 1927 => x"54", + 1928 => x"81", + 1929 => x"06", + 1930 => x"39", + 1931 => x"80", + 1932 => x"54", + 1933 => x"83", + 1934 => x"70", + 1935 => x"38", + 1936 => x"98", + 1937 => x"52", + 1938 => x"52", + 1939 => x"2e", + 1940 => x"54", + 1941 => x"84", + 1942 => x"38", + 1943 => x"52", + 1944 => x"2e", + 1945 => x"83", + 1946 => x"70", + 1947 => x"09", + 1948 => x"80", + 1949 => x"51", + 1950 => x"80", + 1951 => x"80", + 1952 => x"05", + 1953 => x"75", + 1954 => x"70", + 1955 => x"0c", + 1956 => x"04", + 1957 => x"76", + 1958 => x"80", + 1959 => x"86", + 1960 => x"52", + 1961 => x"a8", + 1962 => x"ec", + 1963 => x"80", + 1964 => x"74", + 1965 => x"85", + 1966 => x"3d", + 1967 => x"3d", + 1968 => x"11", + 1969 => x"52", + 1970 => x"70", + 1971 => x"98", + 1972 => x"33", + 1973 => x"82", + 1974 => x"26", + 1975 => x"84", + 1976 => x"83", + 1977 => x"26", + 1978 => x"85", + 1979 => x"84", + 1980 => x"26", + 1981 => x"86", + 1982 => x"85", + 1983 => x"26", + 1984 => x"88", + 1985 => x"86", + 1986 => x"e7", + 1987 => x"38", + 1988 => x"54", + 1989 => x"87", + 1990 => x"cc", + 1991 => x"87", + 1992 => x"0c", + 1993 => x"c0", + 1994 => x"82", + 1995 => x"c0", + 1996 => x"83", + 1997 => x"c0", + 1998 => x"84", + 1999 => x"c0", + 2000 => x"85", + 2001 => x"c0", + 2002 => x"86", + 2003 => x"c0", + 2004 => x"74", + 2005 => x"a4", + 2006 => x"c0", + 2007 => x"80", + 2008 => x"98", + 2009 => x"52", + 2010 => x"ec", + 2011 => x"0d", + 2012 => x"0d", + 2013 => x"c0", + 2014 => x"81", + 2015 => x"c0", + 2016 => x"5e", + 2017 => x"87", + 2018 => x"08", + 2019 => x"1c", + 2020 => x"98", + 2021 => x"79", + 2022 => x"87", + 2023 => x"08", + 2024 => x"1c", + 2025 => x"98", + 2026 => x"79", + 2027 => x"87", + 2028 => x"08", + 2029 => x"1c", + 2030 => x"98", + 2031 => x"7b", + 2032 => x"87", + 2033 => x"08", + 2034 => x"1c", + 2035 => x"0c", + 2036 => x"ff", + 2037 => x"83", + 2038 => x"58", + 2039 => x"57", + 2040 => x"56", + 2041 => x"55", + 2042 => x"54", + 2043 => x"53", + 2044 => x"ff", + 2045 => x"f5", + 2046 => x"e0", + 2047 => x"0d", + 2048 => x"0d", + 2049 => x"33", + 2050 => x"05", + 2051 => x"51", + 2052 => x"82", + 2053 => x"83", + 2054 => x"fb", + 2055 => x"82", + 2056 => x"70", + 2057 => x"57", + 2058 => x"c0", + 2059 => x"74", + 2060 => x"38", + 2061 => x"94", + 2062 => x"70", + 2063 => x"81", + 2064 => x"52", + 2065 => x"8c", + 2066 => x"2a", + 2067 => x"51", + 2068 => x"38", + 2069 => x"70", + 2070 => x"51", + 2071 => x"8d", + 2072 => x"2a", + 2073 => x"51", + 2074 => x"be", + 2075 => x"ff", + 2076 => x"c0", + 2077 => x"70", + 2078 => x"38", + 2079 => x"90", + 2080 => x"0c", + 2081 => x"ec", + 2082 => x"0d", + 2083 => x"0d", + 2084 => x"33", + 2085 => x"33", + 2086 => x"06", + 2087 => x"87", + 2088 => x"51", + 2089 => x"86", + 2090 => x"94", + 2091 => x"08", + 2092 => x"70", + 2093 => x"54", + 2094 => x"2e", + 2095 => x"91", + 2096 => x"06", + 2097 => x"d7", + 2098 => x"32", + 2099 => x"51", + 2100 => x"2e", + 2101 => x"93", + 2102 => x"06", + 2103 => x"ff", + 2104 => x"81", + 2105 => x"87", + 2106 => x"52", + 2107 => x"86", + 2108 => x"94", + 2109 => x"72", + 2110 => x"0d", + 2111 => x"0d", + 2112 => x"74", + 2113 => x"ff", + 2114 => x"57", + 2115 => x"80", + 2116 => x"81", + 2117 => x"15", + 2118 => x"33", + 2119 => x"06", + 2120 => x"58", + 2121 => x"84", + 2122 => x"2e", + 2123 => x"c0", + 2124 => x"70", + 2125 => x"2a", + 2126 => x"53", + 2127 => x"80", + 2128 => x"71", + 2129 => x"81", + 2130 => x"70", + 2131 => x"81", + 2132 => x"06", + 2133 => x"80", + 2134 => x"71", + 2135 => x"81", + 2136 => x"70", + 2137 => x"74", + 2138 => x"51", + 2139 => x"80", + 2140 => x"2e", + 2141 => x"c0", + 2142 => x"77", + 2143 => x"17", + 2144 => x"81", + 2145 => x"53", + 2146 => x"86", + 2147 => x"85", + 2148 => x"3d", + 2149 => x"3d", + 2150 => x"8c", + 2151 => x"ff", + 2152 => x"87", + 2153 => x"51", + 2154 => x"86", + 2155 => x"94", + 2156 => x"08", + 2157 => x"70", + 2158 => x"51", + 2159 => x"2e", + 2160 => x"81", + 2161 => x"87", + 2162 => x"52", + 2163 => x"86", + 2164 => x"94", + 2165 => x"08", + 2166 => x"06", + 2167 => x"0c", + 2168 => x"0d", + 2169 => x"0d", + 2170 => x"33", + 2171 => x"06", + 2172 => x"c0", + 2173 => x"70", + 2174 => x"38", + 2175 => x"94", + 2176 => x"70", + 2177 => x"81", + 2178 => x"51", + 2179 => x"80", + 2180 => x"72", + 2181 => x"51", + 2182 => x"80", + 2183 => x"2e", + 2184 => x"c0", + 2185 => x"71", + 2186 => x"2b", + 2187 => x"51", + 2188 => x"82", + 2189 => x"84", + 2190 => x"ff", + 2191 => x"c0", + 2192 => x"70", + 2193 => x"06", + 2194 => x"80", + 2195 => x"38", + 2196 => x"a4", + 2197 => x"90", + 2198 => x"9e", + 2199 => x"84", + 2200 => x"c0", + 2201 => x"82", + 2202 => x"87", + 2203 => x"08", + 2204 => x"0c", + 2205 => x"9c", + 2206 => x"a0", + 2207 => x"9e", + 2208 => x"84", + 2209 => x"c0", + 2210 => x"82", + 2211 => x"87", + 2212 => x"08", + 2213 => x"0c", + 2214 => x"b4", + 2215 => x"b0", + 2216 => x"9e", + 2217 => x"84", + 2218 => x"c0", + 2219 => x"82", + 2220 => x"87", + 2221 => x"08", + 2222 => x"0c", + 2223 => x"c4", + 2224 => x"c0", + 2225 => x"9e", + 2226 => x"70", + 2227 => x"23", + 2228 => x"84", + 2229 => x"c8", + 2230 => x"9e", + 2231 => x"84", + 2232 => x"c0", + 2233 => x"82", + 2234 => x"81", + 2235 => x"d4", + 2236 => x"87", + 2237 => x"08", + 2238 => x"0a", + 2239 => x"52", + 2240 => x"83", + 2241 => x"71", + 2242 => x"34", + 2243 => x"c0", + 2244 => x"70", + 2245 => x"06", + 2246 => x"70", + 2247 => x"38", + 2248 => x"82", + 2249 => x"80", + 2250 => x"9e", + 2251 => x"90", + 2252 => x"51", + 2253 => x"80", + 2254 => x"81", + 2255 => x"84", + 2256 => x"0b", + 2257 => x"90", + 2258 => x"80", + 2259 => x"52", + 2260 => x"2e", + 2261 => x"52", + 2262 => x"d8", + 2263 => x"87", + 2264 => x"08", + 2265 => x"80", + 2266 => x"52", + 2267 => x"83", + 2268 => x"71", + 2269 => x"34", + 2270 => x"c0", + 2271 => x"70", + 2272 => x"06", + 2273 => x"70", + 2274 => x"38", + 2275 => x"82", + 2276 => x"80", + 2277 => x"9e", + 2278 => x"84", + 2279 => x"51", + 2280 => x"80", + 2281 => x"81", + 2282 => x"84", + 2283 => x"0b", + 2284 => x"90", + 2285 => x"80", + 2286 => x"52", + 2287 => x"2e", + 2288 => x"52", + 2289 => x"dc", + 2290 => x"87", + 2291 => x"08", + 2292 => x"80", + 2293 => x"52", + 2294 => x"83", + 2295 => x"71", + 2296 => x"34", + 2297 => x"c0", + 2298 => x"70", + 2299 => x"06", + 2300 => x"70", + 2301 => x"38", + 2302 => x"82", + 2303 => x"80", + 2304 => x"9e", + 2305 => x"a0", + 2306 => x"52", + 2307 => x"2e", + 2308 => x"52", + 2309 => x"df", + 2310 => x"9e", + 2311 => x"98", + 2312 => x"8a", + 2313 => x"51", + 2314 => x"e0", + 2315 => x"87", + 2316 => x"08", + 2317 => x"06", + 2318 => x"70", + 2319 => x"38", + 2320 => x"82", + 2321 => x"87", + 2322 => x"08", + 2323 => x"06", + 2324 => x"51", + 2325 => x"82", + 2326 => x"80", + 2327 => x"9e", + 2328 => x"88", + 2329 => x"52", + 2330 => x"83", + 2331 => x"71", + 2332 => x"34", + 2333 => x"90", + 2334 => x"06", + 2335 => x"82", + 2336 => x"83", + 2337 => x"fc", + 2338 => x"f5", + 2339 => x"dc", + 2340 => x"d4", + 2341 => x"80", + 2342 => x"81", + 2343 => x"85", + 2344 => x"f5", + 2345 => x"c4", + 2346 => x"d6", + 2347 => x"80", + 2348 => x"82", + 2349 => x"82", + 2350 => x"11", + 2351 => x"f5", + 2352 => x"98", + 2353 => x"db", + 2354 => x"80", + 2355 => x"82", + 2356 => x"82", + 2357 => x"11", + 2358 => x"f5", + 2359 => x"fc", + 2360 => x"d8", + 2361 => x"80", + 2362 => x"82", + 2363 => x"82", + 2364 => x"11", + 2365 => x"f6", + 2366 => x"e0", + 2367 => x"d9", + 2368 => x"80", + 2369 => x"82", + 2370 => x"82", + 2371 => x"11", + 2372 => x"f6", + 2373 => x"c4", + 2374 => x"da", + 2375 => x"80", + 2376 => x"82", + 2377 => x"82", + 2378 => x"11", + 2379 => x"f6", + 2380 => x"a8", + 2381 => x"df", + 2382 => x"80", + 2383 => x"82", + 2384 => x"52", + 2385 => x"51", + 2386 => x"82", + 2387 => x"54", + 2388 => x"8d", + 2389 => x"e4", + 2390 => x"f7", + 2391 => x"fc", + 2392 => x"e1", + 2393 => x"80", + 2394 => x"82", + 2395 => x"52", + 2396 => x"51", + 2397 => x"82", + 2398 => x"54", + 2399 => x"88", + 2400 => x"cc", + 2401 => x"3f", + 2402 => x"33", + 2403 => x"2e", + 2404 => x"f7", + 2405 => x"d4", + 2406 => x"dc", + 2407 => x"80", + 2408 => x"81", + 2409 => x"83", + 2410 => x"84", + 2411 => x"73", + 2412 => x"38", + 2413 => x"51", + 2414 => x"82", + 2415 => x"54", + 2416 => x"88", + 2417 => x"84", + 2418 => x"3f", + 2419 => x"51", + 2420 => x"82", + 2421 => x"52", + 2422 => x"51", + 2423 => x"82", + 2424 => x"52", + 2425 => x"51", + 2426 => x"82", + 2427 => x"52", + 2428 => x"51", + 2429 => x"81", + 2430 => x"82", + 2431 => x"84", + 2432 => x"81", + 2433 => x"88", + 2434 => x"84", + 2435 => x"bd", + 2436 => x"74", + 2437 => x"3f", + 2438 => x"08", + 2439 => x"c0", + 2440 => x"ec", + 2441 => x"e3", + 2442 => x"85", + 2443 => x"53", + 2444 => x"f9", + 2445 => x"a4", + 2446 => x"db", + 2447 => x"80", + 2448 => x"82", + 2449 => x"55", + 2450 => x"52", + 2451 => x"bb", + 2452 => x"ec", + 2453 => x"84", + 2454 => x"85", + 2455 => x"d0", + 2456 => x"82", + 2457 => x"31", + 2458 => x"81", + 2459 => x"87", + 2460 => x"84", + 2461 => x"73", + 2462 => x"38", + 2463 => x"08", + 2464 => x"c0", + 2465 => x"d1", + 2466 => x"85", + 2467 => x"bd", + 2468 => x"82", + 2469 => x"51", + 2470 => x"74", + 2471 => x"08", + 2472 => x"52", + 2473 => x"51", + 2474 => x"81", + 2475 => x"81", + 2476 => x"3d", + 2477 => x"3d", + 2478 => x"05", + 2479 => x"52", + 2480 => x"a9", + 2481 => x"2b", + 2482 => x"dc", + 2483 => x"81", + 2484 => x"9d", + 2485 => x"d0", + 2486 => x"81", + 2487 => x"91", + 2488 => x"e0", + 2489 => x"81", + 2490 => x"85", + 2491 => x"ec", + 2492 => x"3f", + 2493 => x"04", + 2494 => x"0c", + 2495 => x"87", + 2496 => x"0c", + 2497 => x"e8", + 2498 => x"96", + 2499 => x"fe", + 2500 => x"93", + 2501 => x"72", + 2502 => x"81", + 2503 => x"8d", + 2504 => x"82", + 2505 => x"52", + 2506 => x"90", + 2507 => x"34", + 2508 => x"08", + 2509 => x"9c", + 2510 => x"39", + 2511 => x"08", + 2512 => x"2e", + 2513 => x"51", + 2514 => x"3d", + 2515 => x"3d", + 2516 => x"05", + 2517 => x"f4", + 2518 => x"9c", + 2519 => x"51", + 2520 => x"72", + 2521 => x"0c", + 2522 => x"04", + 2523 => x"75", + 2524 => x"70", + 2525 => x"53", + 2526 => x"2e", + 2527 => x"81", + 2528 => x"81", + 2529 => x"87", + 2530 => x"85", + 2531 => x"fc", + 2532 => x"82", + 2533 => x"78", + 2534 => x"0c", + 2535 => x"33", + 2536 => x"06", + 2537 => x"80", + 2538 => x"72", + 2539 => x"51", + 2540 => x"fe", + 2541 => x"39", + 2542 => x"f4", + 2543 => x"0d", + 2544 => x"0d", + 2545 => x"59", + 2546 => x"05", + 2547 => x"75", + 2548 => x"84", + 2549 => x"2e", + 2550 => x"82", + 2551 => x"70", + 2552 => x"05", + 2553 => x"5b", + 2554 => x"2e", + 2555 => x"85", + 2556 => x"8b", + 2557 => x"2e", + 2558 => x"8a", + 2559 => x"78", + 2560 => x"5a", + 2561 => x"aa", + 2562 => x"06", + 2563 => x"84", + 2564 => x"7b", + 2565 => x"5d", + 2566 => x"59", + 2567 => x"d0", + 2568 => x"89", + 2569 => x"7a", + 2570 => x"11", + 2571 => x"d0", + 2572 => x"81", + 2573 => x"59", + 2574 => x"e3", + 2575 => x"ec", + 2576 => x"81", + 2577 => x"07", + 2578 => x"80", + 2579 => x"09", + 2580 => x"72", + 2581 => x"73", + 2582 => x"58", + 2583 => x"73", + 2584 => x"38", + 2585 => x"79", + 2586 => x"5b", + 2587 => x"75", + 2588 => x"e4", + 2589 => x"80", + 2590 => x"89", + 2591 => x"70", + 2592 => x"55", + 2593 => x"cf", + 2594 => x"38", + 2595 => x"24", + 2596 => x"80", + 2597 => x"8e", + 2598 => x"c3", + 2599 => x"73", + 2600 => x"81", + 2601 => x"99", + 2602 => x"c4", + 2603 => x"38", + 2604 => x"73", + 2605 => x"81", + 2606 => x"80", + 2607 => x"38", + 2608 => x"2e", + 2609 => x"f9", + 2610 => x"d8", + 2611 => x"38", + 2612 => x"77", + 2613 => x"08", + 2614 => x"80", + 2615 => x"55", + 2616 => x"8d", + 2617 => x"70", + 2618 => x"51", + 2619 => x"f5", + 2620 => x"2a", + 2621 => x"74", + 2622 => x"53", + 2623 => x"8f", + 2624 => x"fc", + 2625 => x"81", + 2626 => x"80", + 2627 => x"73", + 2628 => x"3f", + 2629 => x"56", + 2630 => x"27", + 2631 => x"a0", + 2632 => x"3f", + 2633 => x"84", + 2634 => x"33", + 2635 => x"93", + 2636 => x"95", + 2637 => x"91", + 2638 => x"8d", + 2639 => x"89", + 2640 => x"fb", + 2641 => x"80", + 2642 => x"2a", + 2643 => x"51", + 2644 => x"2e", + 2645 => x"84", + 2646 => x"86", + 2647 => x"78", + 2648 => x"08", + 2649 => x"32", + 2650 => x"05", + 2651 => x"80", + 2652 => x"55", + 2653 => x"25", + 2654 => x"80", + 2655 => x"74", + 2656 => x"7a", + 2657 => x"55", + 2658 => x"3d", + 2659 => x"52", + 2660 => x"aa", + 2661 => x"ec", + 2662 => x"06", + 2663 => x"52", + 2664 => x"3f", + 2665 => x"08", + 2666 => x"27", + 2667 => x"14", + 2668 => x"f8", + 2669 => x"87", + 2670 => x"81", + 2671 => x"b0", + 2672 => x"7d", + 2673 => x"5f", + 2674 => x"75", + 2675 => x"70", + 2676 => x"2a", + 2677 => x"76", + 2678 => x"38", + 2679 => x"38", + 2680 => x"70", + 2681 => x"53", + 2682 => x"8e", + 2683 => x"77", + 2684 => x"53", + 2685 => x"81", + 2686 => x"7a", + 2687 => x"55", + 2688 => x"83", + 2689 => x"79", + 2690 => x"81", + 2691 => x"72", + 2692 => x"17", + 2693 => x"27", + 2694 => x"51", + 2695 => x"75", + 2696 => x"72", + 2697 => x"81", + 2698 => x"7a", + 2699 => x"38", + 2700 => x"05", + 2701 => x"ff", + 2702 => x"70", + 2703 => x"57", + 2704 => x"76", + 2705 => x"81", + 2706 => x"72", + 2707 => x"f8", + 2708 => x"f9", + 2709 => x"39", + 2710 => x"04", + 2711 => x"86", + 2712 => x"84", + 2713 => x"55", + 2714 => x"fa", + 2715 => x"3d", + 2716 => x"3d", + 2717 => x"9c", + 2718 => x"3d", + 2719 => x"75", + 2720 => x"3f", + 2721 => x"08", + 2722 => x"34", + 2723 => x"9c", + 2724 => x"3d", + 2725 => x"3d", + 2726 => x"f4", + 2727 => x"9c", + 2728 => x"3d", + 2729 => x"77", + 2730 => x"95", + 2731 => x"9c", + 2732 => x"3d", + 2733 => x"3d", + 2734 => x"82", + 2735 => x"70", + 2736 => x"55", + 2737 => x"80", + 2738 => x"38", + 2739 => x"08", + 2740 => x"82", + 2741 => x"81", + 2742 => x"72", + 2743 => x"ce", + 2744 => x"2e", + 2745 => x"88", + 2746 => x"81", + 2747 => x"25", + 2748 => x"73", + 2749 => x"38", + 2750 => x"86", + 2751 => x"54", + 2752 => x"73", + 2753 => x"ff", + 2754 => x"72", + 2755 => x"38", + 2756 => x"72", + 2757 => x"14", + 2758 => x"f7", + 2759 => x"ac", + 2760 => x"52", + 2761 => x"8a", + 2762 => x"3f", + 2763 => x"82", + 2764 => x"87", + 2765 => x"fe", + 2766 => x"9c", + 2767 => x"82", + 2768 => x"77", + 2769 => x"53", + 2770 => x"72", + 2771 => x"0c", + 2772 => x"04", + 2773 => x"7a", + 2774 => x"80", + 2775 => x"58", + 2776 => x"33", + 2777 => x"a0", + 2778 => x"06", + 2779 => x"13", + 2780 => x"39", + 2781 => x"09", + 2782 => x"38", + 2783 => x"11", + 2784 => x"08", + 2785 => x"54", + 2786 => x"2e", + 2787 => x"80", + 2788 => x"08", + 2789 => x"0c", + 2790 => x"33", + 2791 => x"80", + 2792 => x"38", + 2793 => x"80", + 2794 => x"38", + 2795 => x"57", + 2796 => x"0c", + 2797 => x"33", + 2798 => x"39", + 2799 => x"74", + 2800 => x"38", + 2801 => x"80", + 2802 => x"89", + 2803 => x"38", + 2804 => x"d0", + 2805 => x"55", + 2806 => x"80", + 2807 => x"39", + 2808 => x"e3", + 2809 => x"80", + 2810 => x"27", + 2811 => x"80", + 2812 => x"89", + 2813 => x"70", + 2814 => x"55", + 2815 => x"70", + 2816 => x"55", + 2817 => x"27", + 2818 => x"14", + 2819 => x"06", + 2820 => x"74", + 2821 => x"73", + 2822 => x"38", + 2823 => x"51", + 2824 => x"82", + 2825 => x"14", + 2826 => x"05", + 2827 => x"08", + 2828 => x"54", + 2829 => x"39", + 2830 => x"86", + 2831 => x"81", + 2832 => x"79", + 2833 => x"74", + 2834 => x"0c", + 2835 => x"04", + 2836 => x"7a", + 2837 => x"80", + 2838 => x"58", + 2839 => x"33", + 2840 => x"a0", + 2841 => x"06", + 2842 => x"13", + 2843 => x"39", + 2844 => x"09", + 2845 => x"38", + 2846 => x"11", + 2847 => x"08", + 2848 => x"54", + 2849 => x"2e", + 2850 => x"80", + 2851 => x"08", + 2852 => x"0c", + 2853 => x"33", + 2854 => x"80", + 2855 => x"38", + 2856 => x"80", + 2857 => x"38", + 2858 => x"57", + 2859 => x"0c", + 2860 => x"33", + 2861 => x"39", + 2862 => x"74", + 2863 => x"38", + 2864 => x"80", + 2865 => x"89", + 2866 => x"38", + 2867 => x"d0", + 2868 => x"55", + 2869 => x"80", + 2870 => x"39", + 2871 => x"e3", + 2872 => x"80", + 2873 => x"27", + 2874 => x"80", + 2875 => x"89", + 2876 => x"70", + 2877 => x"55", + 2878 => x"70", + 2879 => x"55", + 2880 => x"27", + 2881 => x"14", + 2882 => x"06", + 2883 => x"74", + 2884 => x"73", + 2885 => x"38", + 2886 => x"51", + 2887 => x"82", + 2888 => x"14", + 2889 => x"05", + 2890 => x"08", + 2891 => x"54", + 2892 => x"39", + 2893 => x"86", + 2894 => x"81", + 2895 => x"79", + 2896 => x"74", + 2897 => x"0c", + 2898 => x"04", + 2899 => x"76", + 2900 => x"98", + 2901 => x"2b", + 2902 => x"72", + 2903 => x"82", + 2904 => x"51", + 2905 => x"80", + 2906 => x"f8", + 2907 => x"52", + 2908 => x"a0", + 2909 => x"fa", + 2910 => x"14", + 2911 => x"97", + 2912 => x"33", + 2913 => x"54", + 2914 => x"09", + 2915 => x"38", + 2916 => x"52", + 2917 => x"ec", + 2918 => x"0d", + 2919 => x"0d", + 2920 => x"05", + 2921 => x"71", + 2922 => x"53", + 2923 => x"9f", + 2924 => x"f2", + 2925 => x"51", + 2926 => x"88", + 2927 => x"3f", + 2928 => x"05", + 2929 => x"34", + 2930 => x"06", + 2931 => x"76", + 2932 => x"3f", + 2933 => x"86", + 2934 => x"f6", + 2935 => x"02", + 2936 => x"05", + 2937 => x"05", + 2938 => x"82", + 2939 => x"70", + 2940 => x"84", + 2941 => x"51", + 2942 => x"58", + 2943 => x"2e", + 2944 => x"51", + 2945 => x"82", + 2946 => x"70", + 2947 => x"84", + 2948 => x"1a", + 2949 => x"51", + 2950 => x"88", + 2951 => x"ec", + 2952 => x"82", + 2953 => x"70", + 2954 => x"84", + 2955 => x"51", + 2956 => x"80", + 2957 => x"75", + 2958 => x"74", + 2959 => x"da", + 2960 => x"c4", + 2961 => x"55", + 2962 => x"c4", + 2963 => x"ff", + 2964 => x"75", + 2965 => x"80", + 2966 => x"c4", + 2967 => x"2e", + 2968 => x"85", + 2969 => x"75", + 2970 => x"38", + 2971 => x"33", + 2972 => x"38", + 2973 => x"05", + 2974 => x"78", + 2975 => x"80", + 2976 => x"82", + 2977 => x"52", + 2978 => x"8a", + 2979 => x"85", + 2980 => x"80", + 2981 => x"8c", + 2982 => x"fd", + 2983 => x"84", + 2984 => x"54", + 2985 => x"71", + 2986 => x"38", + 2987 => x"dd", + 2988 => x"0c", + 2989 => x"14", + 2990 => x"80", + 2991 => x"80", + 2992 => x"c4", + 2993 => x"c0", + 2994 => x"80", + 2995 => x"71", + 2996 => x"dc", + 2997 => x"c0", + 2998 => x"b1", + 2999 => x"82", + 3000 => x"85", + 3001 => x"dc", + 3002 => x"57", + 3003 => x"85", + 3004 => x"80", + 3005 => x"82", + 3006 => x"80", + 3007 => x"85", + 3008 => x"80", + 3009 => x"3d", + 3010 => x"81", + 3011 => x"82", + 3012 => x"80", + 3013 => x"75", + 3014 => x"9e", + 3015 => x"ec", + 3016 => x"0b", + 3017 => x"08", + 3018 => x"82", + 3019 => x"ff", + 3020 => x"55", + 3021 => x"34", + 3022 => x"52", + 3023 => x"fd", + 3024 => x"f6", + 3025 => x"ff", + 3026 => x"06", + 3027 => x"a6", + 3028 => x"d9", + 3029 => x"3d", + 3030 => x"08", + 3031 => x"70", + 3032 => x"52", + 3033 => x"08", + 3034 => x"d2", + 3035 => x"ec", + 3036 => x"38", + 3037 => x"85", + 3038 => x"55", + 3039 => x"8b", + 3040 => x"56", + 3041 => x"3f", + 3042 => x"08", + 3043 => x"38", + 3044 => x"b4", + 3045 => x"85", + 3046 => x"18", + 3047 => x"0b", + 3048 => x"08", + 3049 => x"82", + 3050 => x"ff", + 3051 => x"55", + 3052 => x"34", + 3053 => x"09", + 3054 => x"72", + 3055 => x"51", + 3056 => x"77", + 3057 => x"73", + 3058 => x"82", + 3059 => x"8c", + 3060 => x"51", + 3061 => x"3f", + 3062 => x"08", + 3063 => x"38", + 3064 => x"51", + 3065 => x"78", + 3066 => x"81", + 3067 => x"75", + 3068 => x"ff", + 3069 => x"79", + 3070 => x"be", + 3071 => x"08", + 3072 => x"ec", + 3073 => x"80", + 3074 => x"85", + 3075 => x"3d", + 3076 => x"3d", + 3077 => x"71", + 3078 => x"33", + 3079 => x"58", + 3080 => x"09", + 3081 => x"38", + 3082 => x"05", + 3083 => x"27", + 3084 => x"17", + 3085 => x"71", + 3086 => x"55", + 3087 => x"09", + 3088 => x"38", + 3089 => x"ea", + 3090 => x"74", + 3091 => x"85", + 3092 => x"08", + 3093 => x"ff", + 3094 => x"82", + 3095 => x"53", + 3096 => x"08", + 3097 => x"df", + 3098 => x"ec", + 3099 => x"38", + 3100 => x"54", + 3101 => x"88", + 3102 => x"2e", + 3103 => x"39", + 3104 => x"be", + 3105 => x"5a", + 3106 => x"11", + 3107 => x"51", + 3108 => x"82", + 3109 => x"80", + 3110 => x"ff", + 3111 => x"52", + 3112 => x"af", + 3113 => x"ec", + 3114 => x"06", + 3115 => x"2e", + 3116 => x"15", + 3117 => x"06", + 3118 => x"75", + 3119 => x"38", + 3120 => x"82", + 3121 => x"8c", + 3122 => x"d3", + 3123 => x"3d", + 3124 => x"08", + 3125 => x"59", + 3126 => x"0b", + 3127 => x"82", + 3128 => x"82", + 3129 => x"55", + 3130 => x"ca", + 3131 => x"85", + 3132 => x"55", + 3133 => x"81", + 3134 => x"2e", + 3135 => x"81", + 3136 => x"55", + 3137 => x"2e", + 3138 => x"a8", + 3139 => x"3f", + 3140 => x"08", + 3141 => x"0c", + 3142 => x"08", + 3143 => x"91", + 3144 => x"76", + 3145 => x"ec", + 3146 => x"c8", + 3147 => x"85", + 3148 => x"2e", + 3149 => x"fe", + 3150 => x"a0", + 3151 => x"39", + 3152 => x"08", + 3153 => x"c0", + 3154 => x"f8", + 3155 => x"70", + 3156 => x"82", + 3157 => x"85", + 3158 => x"82", + 3159 => x"74", + 3160 => x"06", + 3161 => x"82", + 3162 => x"51", + 3163 => x"3f", + 3164 => x"08", + 3165 => x"82", + 3166 => x"25", + 3167 => x"85", + 3168 => x"05", + 3169 => x"55", + 3170 => x"80", + 3171 => x"ff", + 3172 => x"51", + 3173 => x"81", + 3174 => x"ff", + 3175 => x"93", + 3176 => x"38", + 3177 => x"ff", + 3178 => x"06", + 3179 => x"86", + 3180 => x"85", + 3181 => x"8c", + 3182 => x"c0", + 3183 => x"84", + 3184 => x"3f", + 3185 => x"e0", + 3186 => x"85", + 3187 => x"2b", + 3188 => x"51", + 3189 => x"2e", + 3190 => x"81", + 3191 => x"9d", + 3192 => x"98", + 3193 => x"2c", + 3194 => x"33", + 3195 => x"70", + 3196 => x"98", + 3197 => x"82", + 3198 => x"f4", + 3199 => x"70", + 3200 => x"51", + 3201 => x"51", + 3202 => x"81", + 3203 => x"2e", + 3204 => x"77", + 3205 => x"38", + 3206 => x"98", + 3207 => x"2c", + 3208 => x"80", + 3209 => x"cb", + 3210 => x"74", + 3211 => x"f6", + 3212 => x"85", + 3213 => x"ff", + 3214 => x"80", + 3215 => x"74", + 3216 => x"34", + 3217 => x"39", + 3218 => x"98", + 3219 => x"2c", + 3220 => x"06", + 3221 => x"54", + 3222 => x"97", + 3223 => x"74", + 3224 => x"f5", + 3225 => x"85", + 3226 => x"ff", + 3227 => x"cf", + 3228 => x"80", + 3229 => x"2e", + 3230 => x"81", + 3231 => x"82", + 3232 => x"73", + 3233 => x"98", + 3234 => x"80", + 3235 => x"2b", + 3236 => x"70", + 3237 => x"82", + 3238 => x"f8", + 3239 => x"52", + 3240 => x"58", + 3241 => x"77", + 3242 => x"06", + 3243 => x"81", + 3244 => x"08", + 3245 => x"0b", + 3246 => x"34", + 3247 => x"9d", + 3248 => x"39", + 3249 => x"84", + 3250 => x"9d", + 3251 => x"af", + 3252 => x"7d", + 3253 => x"73", + 3254 => x"e8", + 3255 => x"2b", + 3256 => x"f0", + 3257 => x"82", + 3258 => x"56", + 3259 => x"fd", + 3260 => x"9d", + 3261 => x"75", + 3262 => x"38", + 3263 => x"70", + 3264 => x"55", + 3265 => x"9e", + 3266 => x"54", + 3267 => x"15", + 3268 => x"70", + 3269 => x"98", + 3270 => x"8c", + 3271 => x"56", + 3272 => x"25", + 3273 => x"9d", + 3274 => x"11", + 3275 => x"82", + 3276 => x"73", + 3277 => x"3d", + 3278 => x"82", + 3279 => x"54", + 3280 => x"89", + 3281 => x"54", + 3282 => x"88", + 3283 => x"8c", + 3284 => x"70", + 3285 => x"98", + 3286 => x"88", + 3287 => x"56", + 3288 => x"25", + 3289 => x"1a", + 3290 => x"54", + 3291 => x"81", + 3292 => x"2b", + 3293 => x"82", + 3294 => x"5a", + 3295 => x"76", + 3296 => x"38", + 3297 => x"33", + 3298 => x"70", + 3299 => x"9d", + 3300 => x"51", + 3301 => x"76", + 3302 => x"38", + 3303 => x"ef", + 3304 => x"70", + 3305 => x"98", + 3306 => x"88", + 3307 => x"56", + 3308 => x"24", + 3309 => x"8c", + 3310 => x"34", + 3311 => x"1b", + 3312 => x"8c", + 3313 => x"81", + 3314 => x"f3", + 3315 => x"d9", + 3316 => x"8c", + 3317 => x"ff", + 3318 => x"73", + 3319 => x"e4", + 3320 => x"88", + 3321 => x"54", + 3322 => x"88", + 3323 => x"54", + 3324 => x"8c", + 3325 => x"e6", + 3326 => x"9d", + 3327 => x"98", + 3328 => x"2c", + 3329 => x"33", + 3330 => x"57", + 3331 => x"a4", + 3332 => x"54", + 3333 => x"74", + 3334 => x"51", + 3335 => x"81", + 3336 => x"2b", + 3337 => x"82", + 3338 => x"59", + 3339 => x"75", + 3340 => x"38", + 3341 => x"d7", + 3342 => x"8c", + 3343 => x"2b", + 3344 => x"82", + 3345 => x"57", + 3346 => x"74", + 3347 => x"f4", + 3348 => x"e5", + 3349 => x"15", + 3350 => x"70", + 3351 => x"9d", + 3352 => x"51", + 3353 => x"75", + 3354 => x"fa", + 3355 => x"9d", + 3356 => x"05", + 3357 => x"34", + 3358 => x"93", + 3359 => x"88", + 3360 => x"f7", + 3361 => x"85", + 3362 => x"ff", + 3363 => x"96", + 3364 => x"88", + 3365 => x"80", + 3366 => x"81", + 3367 => x"79", + 3368 => x"3f", + 3369 => x"7a", + 3370 => x"82", + 3371 => x"80", + 3372 => x"88", + 3373 => x"85", + 3374 => x"3d", + 3375 => x"9d", + 3376 => x"73", + 3377 => x"fc", + 3378 => x"e4", + 3379 => x"9d", + 3380 => x"05", + 3381 => x"9d", + 3382 => x"81", + 3383 => x"e3", + 3384 => x"8c", + 3385 => x"88", + 3386 => x"73", + 3387 => x"d4", + 3388 => x"54", + 3389 => x"88", + 3390 => x"2b", + 3391 => x"75", + 3392 => x"56", + 3393 => x"74", + 3394 => x"74", + 3395 => x"14", + 3396 => x"73", + 3397 => x"f7", + 3398 => x"70", + 3399 => x"98", + 3400 => x"88", + 3401 => x"56", + 3402 => x"24", + 3403 => x"51", + 3404 => x"82", + 3405 => x"70", + 3406 => x"98", + 3407 => x"88", + 3408 => x"56", + 3409 => x"24", + 3410 => x"88", + 3411 => x"3f", + 3412 => x"98", + 3413 => x"2c", + 3414 => x"33", + 3415 => x"54", + 3416 => x"e7", + 3417 => x"39", + 3418 => x"33", + 3419 => x"06", + 3420 => x"33", + 3421 => x"74", + 3422 => x"c8", + 3423 => x"54", + 3424 => x"8c", + 3425 => x"70", + 3426 => x"e3", + 3427 => x"9d", + 3428 => x"81", + 3429 => x"9d", + 3430 => x"56", + 3431 => x"26", + 3432 => x"a0", + 3433 => x"8c", + 3434 => x"81", + 3435 => x"ef", + 3436 => x"0b", + 3437 => x"34", + 3438 => x"9d", + 3439 => x"84", + 3440 => x"38", + 3441 => x"08", + 3442 => x"2e", + 3443 => x"51", + 3444 => x"3f", + 3445 => x"08", + 3446 => x"34", + 3447 => x"08", + 3448 => x"81", + 3449 => x"52", + 3450 => x"a9", + 3451 => x"5b", + 3452 => x"7a", + 3453 => x"84", + 3454 => x"11", + 3455 => x"54", + 3456 => x"a7", + 3457 => x"ff", + 3458 => x"82", + 3459 => x"82", + 3460 => x"82", + 3461 => x"81", + 3462 => x"05", + 3463 => x"79", + 3464 => x"f6", + 3465 => x"54", + 3466 => x"73", + 3467 => x"80", + 3468 => x"38", + 3469 => x"a7", + 3470 => x"39", + 3471 => x"09", + 3472 => x"38", + 3473 => x"08", + 3474 => x"2e", + 3475 => x"51", + 3476 => x"3f", + 3477 => x"08", + 3478 => x"34", + 3479 => x"08", + 3480 => x"81", + 3481 => x"52", + 3482 => x"a8", + 3483 => x"c2", + 3484 => x"2b", + 3485 => x"11", + 3486 => x"74", + 3487 => x"38", + 3488 => x"a6", + 3489 => x"85", + 3490 => x"9d", + 3491 => x"85", + 3492 => x"ff", + 3493 => x"53", + 3494 => x"51", + 3495 => x"3f", + 3496 => x"73", + 3497 => x"5b", + 3498 => x"82", + 3499 => x"74", + 3500 => x"9d", + 3501 => x"9d", + 3502 => x"79", + 3503 => x"3f", + 3504 => x"82", + 3505 => x"70", + 3506 => x"82", + 3507 => x"59", + 3508 => x"77", + 3509 => x"38", + 3510 => x"73", + 3511 => x"34", + 3512 => x"33", + 3513 => x"a7", + 3514 => x"39", + 3515 => x"33", + 3516 => x"2e", + 3517 => x"88", + 3518 => x"3f", + 3519 => x"33", + 3520 => x"73", + 3521 => x"34", + 3522 => x"f9", + 3523 => x"df", + 3524 => x"85", + 3525 => x"80", + 3526 => x"e0", + 3527 => x"53", + 3528 => x"df", + 3529 => x"aa", + 3530 => x"85", + 3531 => x"80", + 3532 => x"34", + 3533 => x"81", + 3534 => x"85", + 3535 => x"77", + 3536 => x"76", + 3537 => x"82", + 3538 => x"54", + 3539 => x"34", + 3540 => x"34", + 3541 => x"08", + 3542 => x"22", + 3543 => x"80", + 3544 => x"83", + 3545 => x"70", + 3546 => x"51", + 3547 => x"88", + 3548 => x"89", + 3549 => x"85", + 3550 => x"83", + 3551 => x"e4", + 3552 => x"05", + 3553 => x"77", + 3554 => x"76", + 3555 => x"89", + 3556 => x"ff", + 3557 => x"52", + 3558 => x"72", + 3559 => x"fb", + 3560 => x"82", + 3561 => x"ff", + 3562 => x"51", + 3563 => x"85", + 3564 => x"3d", + 3565 => x"3d", + 3566 => x"05", + 3567 => x"05", + 3568 => x"71", + 3569 => x"e4", + 3570 => x"2b", + 3571 => x"83", + 3572 => x"70", + 3573 => x"33", + 3574 => x"07", + 3575 => x"ae", + 3576 => x"81", + 3577 => x"07", + 3578 => x"53", + 3579 => x"54", + 3580 => x"53", + 3581 => x"77", + 3582 => x"18", + 3583 => x"e4", + 3584 => x"88", + 3585 => x"70", + 3586 => x"74", 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x"71", + 3646 => x"11", + 3647 => x"12", + 3648 => x"2b", + 3649 => x"2b", + 3650 => x"55", + 3651 => x"70", + 3652 => x"33", + 3653 => x"71", + 3654 => x"53", + 3655 => x"55", + 3656 => x"80", + 3657 => x"51", + 3658 => x"82", + 3659 => x"70", + 3660 => x"81", + 3661 => x"8b", + 3662 => x"2b", + 3663 => x"70", + 3664 => x"33", + 3665 => x"07", + 3666 => x"8f", + 3667 => x"51", + 3668 => x"53", + 3669 => x"72", + 3670 => x"2a", + 3671 => x"82", + 3672 => x"83", + 3673 => x"85", + 3674 => x"17", + 3675 => x"12", + 3676 => x"2b", + 3677 => x"07", + 3678 => x"55", + 3679 => x"33", + 3680 => x"71", + 3681 => x"70", + 3682 => x"06", + 3683 => x"57", + 3684 => x"52", + 3685 => x"71", + 3686 => x"89", + 3687 => x"fb", + 3688 => x"85", + 3689 => x"84", + 3690 => x"22", + 3691 => x"72", + 3692 => x"33", + 3693 => x"71", + 3694 => x"83", + 3695 => x"5b", + 3696 => x"52", + 3697 => x"33", + 3698 => x"71", + 3699 => x"02", + 3700 => x"05", + 3701 => x"70", + 3702 => x"51", + 3703 => x"71", + 3704 => x"81", + 3705 => x"85", + 3706 => x"15", + 3707 => x"12", + 3708 => x"2b", + 3709 => x"07", + 3710 => x"52", + 3711 => x"12", + 3712 => x"33", + 3713 => x"07", + 3714 => x"54", + 3715 => x"70", + 3716 => x"72", + 3717 => x"82", + 3718 => x"14", + 3719 => x"83", + 3720 => x"88", + 3721 => x"85", + 3722 => x"54", + 3723 => x"04", + 3724 => x"7b", + 3725 => x"08", + 3726 => x"70", + 3727 => x"06", + 3728 => x"53", + 3729 => x"82", + 3730 => x"76", + 3731 => x"11", + 3732 => x"83", + 3733 => x"8b", + 3734 => x"2b", + 3735 => x"70", + 3736 => x"33", + 3737 => x"71", + 3738 => x"53", + 3739 => x"53", + 3740 => x"59", + 3741 => x"25", + 3742 => x"80", + 3743 => x"51", + 3744 => x"81", + 3745 => x"14", + 3746 => x"33", + 3747 => x"71", + 3748 => x"76", + 3749 => x"2a", + 3750 => x"58", + 3751 => x"14", + 3752 => x"ff", + 3753 => x"87", + 3754 => x"85", + 3755 => x"19", + 3756 => x"85", + 3757 => x"88", + 3758 => x"88", + 3759 => x"5b", + 3760 => x"84", + 3761 => x"85", + 3762 => x"85", + 3763 => x"53", + 3764 => x"14", + 3765 => x"87", + 3766 => x"85", + 3767 => x"76", + 3768 => x"75", + 3769 => x"82", + 3770 => x"18", + 3771 => x"12", + 3772 => x"2b", + 3773 => x"80", + 3774 => x"88", + 3775 => x"55", + 3776 => x"74", + 3777 => x"15", + 3778 => x"0d", + 3779 => x"0d", + 3780 => x"85", + 3781 => x"38", + 3782 => x"71", + 3783 => x"38", + 3784 => x"8c", + 3785 => x"0d", + 3786 => x"0d", + 3787 => x"58", + 3788 => x"82", + 3789 => x"83", + 3790 => x"82", + 3791 => x"84", + 3792 => x"12", + 3793 => x"2b", + 3794 => x"59", + 3795 => x"81", + 3796 => x"75", + 3797 => x"cc", + 3798 => x"2b", + 3799 => x"33", + 3800 => x"71", + 3801 => x"70", + 3802 => x"06", + 3803 => x"83", + 3804 => x"70", + 3805 => x"53", + 3806 => x"55", + 3807 => x"8a", + 3808 => x"2e", + 3809 => x"78", + 3810 => x"15", + 3811 => x"33", + 3812 => x"07", + 3813 => x"c1", + 3814 => x"ff", + 3815 => x"38", + 3816 => x"56", + 3817 => x"2b", + 3818 => x"08", + 3819 => x"81", + 3820 => x"88", + 3821 => x"81", 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x"04", + 3881 => x"74", + 3882 => x"e4", + 3883 => x"f4", + 3884 => x"53", + 3885 => x"8b", + 3886 => x"fc", + 3887 => x"85", + 3888 => x"72", + 3889 => x"0c", + 3890 => x"04", + 3891 => x"02", + 3892 => x"51", + 3893 => x"72", + 3894 => x"82", + 3895 => x"33", + 3896 => x"85", + 3897 => x"3d", + 3898 => x"3d", + 3899 => x"05", + 3900 => x"05", + 3901 => x"56", + 3902 => x"72", + 3903 => x"e0", + 3904 => x"2b", + 3905 => x"8c", + 3906 => x"88", + 3907 => x"2e", + 3908 => x"88", + 3909 => x"0c", + 3910 => x"8c", + 3911 => x"71", + 3912 => x"87", + 3913 => x"0c", + 3914 => x"08", + 3915 => x"51", + 3916 => x"2e", + 3917 => x"c0", + 3918 => x"51", + 3919 => x"71", + 3920 => x"80", + 3921 => x"92", + 3922 => x"98", + 3923 => x"70", + 3924 => x"38", + 3925 => x"e8", + 3926 => x"85", + 3927 => x"51", + 3928 => x"ec", + 3929 => x"0d", + 3930 => x"0d", + 3931 => x"02", + 3932 => x"05", + 3933 => x"58", + 3934 => x"52", + 3935 => x"3f", + 3936 => x"08", + 3937 => x"54", + 3938 => x"be", + 3939 => x"75", + 3940 => x"c0", + 3941 => x"87", + 3942 => x"12", + 3943 => x"84", + 3944 => x"40", + 3945 => x"85", + 3946 => x"98", + 3947 => x"7d", + 3948 => x"0c", + 3949 => x"85", + 3950 => x"06", + 3951 => x"71", + 3952 => x"38", + 3953 => x"71", + 3954 => x"05", + 3955 => x"19", + 3956 => x"a2", + 3957 => x"71", + 3958 => x"38", + 3959 => x"83", + 3960 => x"38", + 3961 => x"8a", + 3962 => x"98", + 3963 => x"71", + 3964 => x"c0", + 3965 => x"52", + 3966 => x"87", + 3967 => x"80", + 3968 => x"81", + 3969 => x"c0", + 3970 => x"53", + 3971 => x"82", + 3972 => x"71", + 3973 => x"1a", + 3974 => x"84", + 3975 => x"19", + 3976 => x"06", + 3977 => x"79", + 3978 => x"38", + 3979 => x"80", + 3980 => x"87", + 3981 => x"26", + 3982 => x"73", + 3983 => x"06", + 3984 => x"2e", + 3985 => x"52", + 3986 => x"82", + 3987 => x"8f", + 3988 => x"f3", + 3989 => x"62", + 3990 => x"05", + 3991 => x"57", + 3992 => x"83", + 3993 => x"52", + 3994 => x"3f", + 3995 => x"08", + 3996 => x"54", + 3997 => x"2e", + 3998 => x"81", + 3999 => x"74", + 4000 => x"c0", + 4001 => x"87", + 4002 => x"12", + 4003 => x"84", + 4004 => x"5f", + 4005 => x"0b", + 4006 => x"8c", + 4007 => x"0c", + 4008 => x"80", + 4009 => x"70", + 4010 => x"81", + 4011 => x"54", + 4012 => x"8c", + 4013 => x"81", + 4014 => x"7c", + 4015 => x"58", + 4016 => x"70", + 4017 => x"52", + 4018 => x"8a", + 4019 => x"98", + 4020 => x"71", + 4021 => x"c0", + 4022 => x"52", + 4023 => x"87", + 4024 => x"80", + 4025 => x"81", + 4026 => x"c0", + 4027 => x"53", + 4028 => x"82", + 4029 => x"71", + 4030 => x"19", + 4031 => x"81", + 4032 => x"ff", + 4033 => x"19", + 4034 => x"78", + 4035 => x"38", + 4036 => x"80", + 4037 => x"87", + 4038 => x"26", + 4039 => x"73", + 4040 => x"06", + 4041 => x"2e", + 4042 => x"52", + 4043 => x"82", + 4044 => x"8f", + 4045 => x"fa", + 4046 => x"02", + 4047 => x"05", + 4048 => x"05", + 4049 => x"71", + 4050 => x"57", + 4051 => x"82", + 4052 => x"81", + 4053 => x"54", + 4054 => x"38", + 4055 => x"c0", + 4056 => x"81", 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x"34", + 4116 => x"51", + 4117 => x"81", + 4118 => x"70", + 4119 => x"70", + 4120 => x"05", + 4121 => x"88", + 4122 => x"72", + 4123 => x"0d", + 4124 => x"0d", + 4125 => x"54", + 4126 => x"80", + 4127 => x"71", + 4128 => x"53", + 4129 => x"81", + 4130 => x"ff", + 4131 => x"39", + 4132 => x"04", + 4133 => x"75", + 4134 => x"52", + 4135 => x"70", + 4136 => x"34", + 4137 => x"70", + 4138 => x"3d", + 4139 => x"3d", + 4140 => x"79", + 4141 => x"74", + 4142 => x"56", + 4143 => x"81", + 4144 => x"71", + 4145 => x"16", + 4146 => x"52", + 4147 => x"86", + 4148 => x"2e", + 4149 => x"82", + 4150 => x"86", + 4151 => x"fe", + 4152 => x"76", + 4153 => x"39", + 4154 => x"8a", + 4155 => x"51", + 4156 => x"71", + 4157 => x"33", + 4158 => x"0c", + 4159 => x"04", + 4160 => x"85", + 4161 => x"80", + 4162 => x"ec", + 4163 => x"3d", + 4164 => x"80", + 4165 => x"33", + 4166 => x"7a", + 4167 => x"38", + 4168 => x"16", + 4169 => x"16", + 4170 => x"17", + 4171 => x"fa", + 4172 => x"85", + 4173 => x"2e", + 4174 => x"b7", + 4175 => x"ec", + 4176 => x"34", + 4177 => x"70", + 4178 => x"31", + 4179 => x"59", + 4180 => x"77", + 4181 => x"82", + 4182 => x"74", + 4183 => x"81", + 4184 => x"81", + 4185 => x"53", + 4186 => x"16", + 4187 => x"e3", + 4188 => x"81", + 4189 => x"85", + 4190 => x"3d", + 4191 => x"3d", + 4192 => x"56", + 4193 => x"74", + 4194 => x"2e", + 4195 => x"51", + 4196 => x"82", + 4197 => x"57", + 4198 => x"08", + 4199 => x"54", + 4200 => x"16", + 4201 => x"33", + 4202 => x"3f", + 4203 => x"08", + 4204 => x"38", + 4205 => x"57", + 4206 => x"0c", + 4207 => x"ec", + 4208 => x"0d", + 4209 => x"0d", + 4210 => x"57", + 4211 => x"82", + 4212 => x"58", + 4213 => x"08", + 4214 => x"76", + 4215 => x"83", + 4216 => x"06", + 4217 => x"84", + 4218 => x"78", + 4219 => x"81", + 4220 => x"38", + 4221 => x"82", + 4222 => x"52", + 4223 => x"52", + 4224 => x"3f", + 4225 => x"52", + 4226 => x"51", + 4227 => x"84", + 4228 => x"d2", + 4229 => x"fc", + 4230 => x"8a", + 4231 => x"52", + 4232 => x"51", + 4233 => x"90", + 4234 => x"84", + 4235 => x"fc", + 4236 => x"17", + 4237 => x"a0", + 4238 => x"86", + 4239 => x"08", + 4240 => x"b0", + 4241 => x"55", + 4242 => x"81", + 4243 => x"f8", + 4244 => x"84", + 4245 => x"53", + 4246 => x"17", + 4247 => x"d7", + 4248 => x"ec", + 4249 => x"83", + 4250 => x"77", + 4251 => x"0c", + 4252 => x"04", + 4253 => x"77", + 4254 => x"12", + 4255 => x"55", + 4256 => x"56", + 4257 => x"94", + 4258 => x"22", + 4259 => x"ff", + 4260 => x"ac", + 4261 => x"85", + 4262 => x"56", + 4263 => x"ec", + 4264 => x"0d", + 4265 => x"0d", + 4266 => x"08", + 4267 => x"81", + 4268 => x"df", + 4269 => x"15", + 4270 => x"d7", + 4271 => x"33", + 4272 => x"82", + 4273 => x"38", + 4274 => x"89", + 4275 => x"2e", + 4276 => x"bf", + 4277 => x"2e", + 4278 => x"81", + 4279 => x"81", + 4280 => x"89", + 4281 => x"08", + 4282 => x"52", + 4283 => x"3f", + 4284 => x"08", + 4285 => x"74", + 4286 => x"14", + 4287 => x"81", + 4288 => x"2a", + 4289 => x"05", + 4290 => x"57", + 4291 => x"ee", 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x"81", + 4351 => x"06", + 4352 => x"77", + 4353 => x"2e", + 4354 => x"84", + 4355 => x"06", + 4356 => x"06", + 4357 => x"53", + 4358 => x"81", + 4359 => x"34", + 4360 => x"a4", + 4361 => x"52", + 4362 => x"d2", + 4363 => x"ec", + 4364 => x"85", + 4365 => x"94", + 4366 => x"ff", + 4367 => x"05", + 4368 => x"54", + 4369 => x"38", + 4370 => x"74", + 4371 => x"06", + 4372 => x"07", + 4373 => x"74", + 4374 => x"39", + 4375 => x"a4", + 4376 => x"52", + 4377 => x"96", + 4378 => x"ec", + 4379 => x"85", + 4380 => x"d8", + 4381 => x"ff", + 4382 => x"76", + 4383 => x"06", + 4384 => x"05", + 4385 => x"3f", + 4386 => x"87", + 4387 => x"08", + 4388 => x"51", + 4389 => x"82", + 4390 => x"59", + 4391 => x"08", + 4392 => x"f0", + 4393 => x"82", + 4394 => x"06", + 4395 => x"05", + 4396 => x"54", + 4397 => x"3f", + 4398 => x"08", + 4399 => x"74", + 4400 => x"51", + 4401 => x"81", + 4402 => x"34", + 4403 => x"ec", + 4404 => x"0d", + 4405 => x"0d", + 4406 => x"72", + 4407 => x"56", + 4408 => x"27", + 4409 => x"98", + 4410 => x"9d", + 4411 => x"2e", + 4412 => x"53", + 4413 => x"51", + 4414 => x"82", + 4415 => x"54", + 4416 => x"08", + 4417 => x"93", + 4418 => x"80", + 4419 => x"54", + 4420 => x"82", + 4421 => x"54", + 4422 => x"74", + 4423 => x"fb", + 4424 => x"85", + 4425 => x"82", + 4426 => x"80", + 4427 => x"38", + 4428 => x"08", + 4429 => x"38", + 4430 => x"08", + 4431 => x"38", + 4432 => x"52", + 4433 => x"d6", + 4434 => x"ec", + 4435 => x"98", + 4436 => x"11", + 4437 => x"57", + 4438 => x"74", + 4439 => x"81", + 4440 => x"0c", + 4441 => x"81", + 4442 => x"84", + 4443 => x"55", + 4444 => x"ff", + 4445 => x"54", + 4446 => x"ec", + 4447 => x"0d", + 4448 => x"0d", + 4449 => x"08", + 4450 => x"79", + 4451 => x"17", + 4452 => x"80", + 4453 => x"98", + 4454 => x"26", + 4455 => x"58", + 4456 => x"52", + 4457 => x"fd", + 4458 => x"74", + 4459 => x"08", + 4460 => x"38", + 4461 => x"08", + 4462 => x"ec", + 4463 => x"82", + 4464 => x"17", + 4465 => x"ec", + 4466 => x"cd", + 4467 => x"90", + 4468 => x"56", + 4469 => x"2e", + 4470 => x"77", + 4471 => x"81", + 4472 => x"38", + 4473 => x"98", + 4474 => x"26", + 4475 => x"56", + 4476 => x"51", + 4477 => x"80", + 4478 => x"ec", + 4479 => x"09", + 4480 => x"38", + 4481 => x"08", + 4482 => x"ec", + 4483 => x"09", + 4484 => x"72", + 4485 => x"70", + 4486 => x"85", + 4487 => x"51", + 4488 => x"73", + 4489 => x"82", + 4490 => x"80", + 4491 => x"8c", + 4492 => x"81", + 4493 => x"38", + 4494 => x"08", + 4495 => x"73", + 4496 => x"75", + 4497 => x"77", + 4498 => x"56", + 4499 => x"76", + 4500 => x"82", + 4501 => x"26", + 4502 => x"75", + 4503 => x"f8", + 4504 => x"85", + 4505 => x"2e", + 4506 => x"59", + 4507 => x"08", + 4508 => x"81", + 4509 => x"82", + 4510 => x"59", + 4511 => x"08", + 4512 => x"81", + 4513 => x"07", + 4514 => x"7c", + 4515 => x"55", + 4516 => x"fa", + 4517 => x"2e", + 4518 => x"ff", + 4519 => x"55", + 4520 => x"ff", + 4521 => x"76", + 4522 => x"3f", + 4523 => x"08", + 4524 => x"08", + 4525 => x"70", + 4526 => x"08", + 4527 => x"51", + 4528 => x"80", + 4529 => x"73", + 4530 => x"38", + 4531 => x"52", + 4532 => x"ca", + 4533 => x"ec", + 4534 => x"a5", + 4535 => x"18", + 4536 => x"08", + 4537 => x"18", + 4538 => x"74", + 4539 => x"38", + 4540 => x"18", + 4541 => x"33", + 4542 => x"73", + 4543 => x"97", + 4544 => x"74", + 4545 => x"38", + 4546 => x"55", + 4547 => x"85", + 4548 => x"85", + 4549 => x"75", + 4550 => x"85", + 4551 => x"3d", + 4552 => x"3d", + 4553 => x"52", + 4554 => x"3f", + 4555 => x"08", + 4556 => x"82", + 4557 => x"80", + 4558 => x"52", + 4559 => x"b4", + 4560 => x"ec", + 4561 => x"ec", + 4562 => x"0c", + 4563 => x"53", + 4564 => x"15", + 4565 => x"f2", + 4566 => x"56", + 4567 => x"16", + 4568 => x"22", + 4569 => x"27", + 4570 => x"54", + 4571 => x"76", + 4572 => x"33", + 4573 => x"3f", + 4574 => x"08", + 4575 => x"38", + 4576 => x"76", + 4577 => x"81", + 4578 => x"07", + 4579 => x"53", + 4580 => x"75", + 4581 => x"0c", + 4582 => x"04", + 4583 => x"7a", + 4584 => x"58", + 4585 => x"f0", + 4586 => x"80", + 4587 => x"9f", + 4588 => x"80", + 4589 => x"90", + 4590 => x"17", + 4591 => x"aa", + 4592 => x"53", + 4593 => x"88", + 4594 => x"08", + 4595 => x"38", + 4596 => x"53", + 4597 => x"17", + 4598 => x"72", + 4599 => x"fe", + 4600 => x"08", + 4601 => x"80", + 4602 => x"16", + 4603 => x"2b", + 4604 => x"75", + 4605 => x"73", + 4606 => x"f5", + 4607 => x"85", + 4608 => x"82", + 4609 => x"ff", + 4610 => x"81", + 4611 => x"ec", + 4612 => x"38", + 4613 => x"82", + 4614 => x"26", + 4615 => x"58", + 4616 => x"73", + 4617 => x"39", + 4618 => x"51", + 4619 => x"82", + 4620 => x"98", + 4621 => x"94", + 4622 => x"17", + 4623 => x"58", + 4624 => x"9a", + 4625 => x"81", + 4626 => x"74", + 4627 => x"98", + 4628 => x"83", + 4629 => x"b4", + 4630 => x"0c", + 4631 => x"82", + 4632 => x"8a", + 4633 => x"f8", + 4634 => x"70", + 4635 => x"08", + 4636 => x"57", + 4637 => x"0a", + 4638 => x"38", + 4639 => x"15", + 4640 => x"08", + 4641 => x"72", + 4642 => x"cb", + 4643 => x"ff", + 4644 => x"81", + 4645 => x"13", + 4646 => x"94", + 4647 => x"74", + 4648 => x"85", + 4649 => x"22", + 4650 => x"73", + 4651 => x"38", + 4652 => x"8a", + 4653 => x"05", + 4654 => x"06", + 4655 => x"8a", + 4656 => x"73", + 4657 => x"3f", + 4658 => x"08", + 4659 => x"81", + 4660 => x"ec", + 4661 => x"ff", + 4662 => x"82", + 4663 => x"ff", + 4664 => x"38", + 4665 => x"82", + 4666 => x"26", + 4667 => x"7b", + 4668 => x"98", + 4669 => x"55", + 4670 => x"94", + 4671 => x"73", + 4672 => x"3f", + 4673 => x"08", + 4674 => x"82", + 4675 => x"80", + 4676 => x"38", + 4677 => x"85", + 4678 => x"2e", + 4679 => x"55", + 4680 => x"08", + 4681 => x"38", + 4682 => x"08", + 4683 => x"fb", + 4684 => x"85", + 4685 => x"38", + 4686 => x"0c", + 4687 => x"51", + 4688 => x"82", + 4689 => x"98", + 4690 => x"90", + 4691 => x"16", + 4692 => x"15", + 4693 => x"74", + 4694 => x"0c", + 4695 => x"04", + 4696 => x"7b", + 4697 => x"5b", + 4698 => x"52", + 4699 => x"ac", + 4700 => x"ec", + 4701 => x"85", + 4702 => x"ec", + 4703 => x"ec", + 4704 => x"17", + 4705 => x"51", + 4706 => x"82", + 4707 => x"54", + 4708 => x"08", + 4709 => x"82", + 4710 => x"9c", + 4711 => x"33", + 4712 => x"72", + 4713 => x"09", + 4714 => x"38", + 4715 => x"85", + 4716 => x"72", + 4717 => x"55", + 4718 => x"53", + 4719 => x"8e", + 4720 => x"56", + 4721 => x"09", + 4722 => x"38", + 4723 => x"85", + 4724 => x"81", + 4725 => x"fd", + 4726 => x"85", + 4727 => x"82", + 4728 => x"80", + 4729 => x"38", + 4730 => x"09", + 4731 => x"38", + 4732 => x"82", + 4733 => x"8b", + 4734 => x"fd", + 4735 => x"9a", + 4736 => x"eb", + 4737 => x"85", + 4738 => x"ff", + 4739 => x"70", + 4740 => x"53", + 4741 => x"09", + 4742 => x"38", + 4743 => x"eb", + 4744 => x"85", + 4745 => x"2b", + 4746 => x"72", + 4747 => x"0c", + 4748 => x"04", + 4749 => x"77", + 4750 => x"ff", + 4751 => x"9a", + 4752 => x"55", + 4753 => x"76", + 4754 => x"53", + 4755 => x"09", + 4756 => x"38", + 4757 => x"52", + 4758 => x"eb", + 4759 => x"3d", + 4760 => x"3d", + 4761 => x"5b", + 4762 => x"08", + 4763 => x"15", + 4764 => x"81", + 4765 => x"15", + 4766 => x"51", + 4767 => x"82", + 4768 => x"58", + 4769 => x"08", + 4770 => x"9c", + 4771 => x"33", + 4772 => x"86", + 4773 => x"80", + 4774 => x"13", + 4775 => x"06", + 4776 => x"06", + 4777 => x"72", + 4778 => x"82", + 4779 => x"53", + 4780 => x"2e", + 4781 => x"53", + 4782 => x"a9", + 4783 => x"74", + 4784 => x"72", + 4785 => x"38", + 4786 => x"99", + 4787 => x"ec", + 4788 => x"06", + 4789 => x"88", + 4790 => x"06", + 4791 => x"54", + 4792 => x"a0", + 4793 => x"74", + 4794 => x"3f", + 4795 => x"08", + 4796 => x"ec", + 4797 => x"98", + 4798 => x"fa", + 4799 => x"80", + 4800 => x"0c", + 4801 => x"ec", + 4802 => x"0d", + 4803 => x"0d", + 4804 => x"57", + 4805 => x"73", + 4806 => x"3f", + 4807 => x"08", + 4808 => x"ec", + 4809 => x"98", + 4810 => x"75", + 4811 => x"3f", + 4812 => x"08", + 4813 => x"ec", + 4814 => x"a0", + 4815 => x"ec", + 4816 => x"14", + 4817 => x"cc", + 4818 => x"a0", + 4819 => x"14", + 4820 => x"9d", + 4821 => x"83", + 4822 => x"82", + 4823 => x"87", + 4824 => x"fd", + 4825 => x"70", + 4826 => x"08", + 4827 => x"55", + 4828 => x"3f", + 4829 => x"08", + 4830 => x"13", + 4831 => x"73", + 4832 => x"83", + 4833 => x"3d", + 4834 => x"3d", + 4835 => x"57", + 4836 => x"89", + 4837 => x"17", + 4838 => x"81", + 4839 => x"70", + 4840 => x"55", + 4841 => x"08", + 4842 => x"81", + 4843 => x"52", + 4844 => x"a8", + 4845 => x"2e", + 4846 => x"84", + 4847 => x"52", + 4848 => x"09", + 4849 => x"38", + 4850 => x"81", + 4851 => x"81", + 4852 => x"73", + 4853 => x"55", + 4854 => x"55", + 4855 => x"c5", + 4856 => x"88", + 4857 => x"0b", + 4858 => x"9c", + 4859 => x"8b", + 4860 => x"17", + 4861 => x"08", + 4862 => x"52", + 4863 => x"82", + 4864 => x"76", + 4865 => x"51", + 4866 => x"82", + 4867 => x"86", + 4868 => x"12", + 4869 => x"3f", + 4870 => x"08", + 4871 => x"88", + 4872 => x"f3", + 4873 => x"70", + 4874 => x"80", + 4875 => x"51", + 4876 => x"af", + 4877 => x"81", + 4878 => x"dc", + 4879 => x"74", + 4880 => x"38", + 4881 => x"88", + 4882 => x"39", + 4883 => x"80", + 4884 => x"56", + 4885 => x"af", + 4886 => x"06", + 4887 => x"56", + 4888 => x"32", + 4889 => x"05", + 4890 => x"78", + 4891 => x"54", + 4892 => x"73", + 4893 => x"60", + 4894 => x"54", + 4895 => x"96", + 4896 => x"0b", + 4897 => x"80", + 4898 => x"f6", + 4899 => x"85", + 4900 => x"85", + 4901 => x"3d", + 4902 => x"5c", + 4903 => x"53", + 4904 => x"51", + 4905 => x"80", + 4906 => x"88", + 4907 => x"5c", + 4908 => x"09", + 4909 => x"d8", + 4910 => x"70", + 4911 => x"71", + 4912 => x"09", + 4913 => x"9f", + 4914 => x"26", + 4915 => x"53", + 4916 => x"73", + 4917 => x"17", + 4918 => x"34", + 4919 => x"d9", + 4920 => x"32", + 4921 => x"05", + 4922 => x"51", + 4923 => x"80", + 4924 => x"38", + 4925 => x"87", + 4926 => x"26", + 4927 => x"77", + 4928 => x"a4", + 4929 => x"27", + 4930 => x"a0", + 4931 => x"39", + 4932 => x"33", + 4933 => x"57", + 4934 => x"27", + 4935 => x"75", + 4936 => x"09", + 4937 => x"80", + 4938 => x"09", + 4939 => x"80", + 4940 => x"25", + 4941 => x"56", + 4942 => x"80", + 4943 => x"84", + 4944 => x"58", + 4945 => x"70", + 4946 => x"55", + 4947 => x"09", + 4948 => x"38", + 4949 => x"80", + 4950 => x"09", + 4951 => x"80", + 4952 => x"51", + 4953 => x"d9", + 4954 => x"39", + 4955 => x"09", + 4956 => x"38", + 4957 => x"7c", + 4958 => x"54", + 4959 => x"a6", + 4960 => x"32", + 4961 => x"05", + 4962 => x"70", + 4963 => x"72", + 4964 => x"9f", + 4965 => x"51", + 4966 => x"74", + 4967 => x"88", + 4968 => x"fe", + 4969 => x"98", + 4970 => x"80", + 4971 => x"75", + 4972 => x"81", + 4973 => x"33", + 4974 => x"51", + 4975 => x"82", + 4976 => x"80", + 4977 => x"78", + 4978 => x"81", + 4979 => x"5a", + 4980 => x"b3", + 4981 => x"ec", + 4982 => x"80", + 4983 => x"1c", + 4984 => x"27", + 4985 => x"79", + 4986 => x"74", + 4987 => x"7a", + 4988 => x"74", + 4989 => x"39", + 4990 => x"fe", + 4991 => x"df", + 4992 => x"ec", + 4993 => x"ff", + 4994 => x"73", + 4995 => x"38", + 4996 => x"81", + 4997 => x"54", + 4998 => x"75", + 4999 => x"17", + 5000 => x"39", + 5001 => x"0c", + 5002 => x"99", + 5003 => x"54", + 5004 => x"2e", + 5005 => x"84", + 5006 => x"34", + 5007 => x"76", + 5008 => x"8b", + 5009 => x"81", + 5010 => x"56", + 5011 => x"80", + 5012 => x"1b", + 5013 => x"08", + 5014 => x"51", + 5015 => x"82", + 5016 => x"56", + 5017 => x"08", + 5018 => x"98", + 5019 => x"76", + 5020 => x"3f", + 5021 => x"08", + 5022 => x"ec", + 5023 => x"38", + 5024 => x"70", + 5025 => x"73", + 5026 => x"be", + 5027 => x"33", + 5028 => x"73", + 5029 => x"8b", + 5030 => x"83", + 5031 => x"06", + 5032 => x"73", + 5033 => x"53", + 5034 => x"51", + 5035 => x"82", + 5036 => x"80", + 5037 => x"75", + 5038 => x"f3", + 5039 => x"9f", + 5040 => x"1c", + 5041 => x"74", + 5042 => x"38", + 5043 => x"09", + 5044 => x"e7", + 5045 => x"2a", + 5046 => x"77", + 5047 => x"51", + 5048 => x"2e", + 5049 => x"81", + 5050 => x"80", + 5051 => x"38", + 5052 => x"ab", + 5053 => x"55", + 5054 => x"75", + 5055 => x"73", + 5056 => x"55", + 5057 => x"82", + 5058 => x"06", + 5059 => x"ab", + 5060 => x"33", + 5061 => x"70", + 5062 => x"55", + 5063 => x"2e", + 5064 => x"1b", + 5065 => x"06", + 5066 => x"52", + 5067 => x"cb", + 5068 => x"ec", + 5069 => x"0c", + 5070 => x"74", + 5071 => x"0c", + 5072 => x"04", + 5073 => x"7c", + 5074 => x"08", + 5075 => x"55", + 5076 => x"59", + 5077 => x"81", + 5078 => x"70", + 5079 => x"33", + 5080 => x"52", + 5081 => x"2e", + 5082 => x"ee", + 5083 => x"2e", + 5084 => x"81", + 5085 => x"33", + 5086 => x"81", + 5087 => x"52", + 5088 => x"26", + 5089 => x"14", + 5090 => x"06", + 5091 => x"52", + 5092 => x"80", + 5093 => x"0b", + 5094 => x"59", + 5095 => x"7a", + 5096 => x"70", + 5097 => x"33", + 5098 => x"05", + 5099 => x"9f", + 5100 => x"53", + 5101 => x"89", + 5102 => x"70", + 5103 => x"54", + 5104 => x"12", + 5105 => x"26", + 5106 => x"12", + 5107 => x"06", + 5108 => x"09", + 5109 => x"9f", + 5110 => x"72", + 5111 => x"81", + 5112 => x"70", + 5113 => x"72", + 5114 => x"74", + 5115 => x"09", + 5116 => x"72", + 5117 => x"73", + 5118 => x"53", + 5119 => x"70", + 5120 => x"38", + 5121 => x"19", + 5122 => x"75", + 5123 => x"38", + 5124 => x"83", + 5125 => x"74", + 5126 => x"59", + 5127 => x"39", + 5128 => x"33", + 5129 => x"85", + 5130 => x"3d", + 5131 => x"3d", + 5132 => x"80", + 5133 => x"34", + 5134 => x"17", + 5135 => x"75", + 5136 => x"3f", + 5137 => x"85", + 5138 => x"82", + 5139 => x"16", + 5140 => x"3f", + 5141 => x"08", + 5142 => x"06", + 5143 => x"73", + 5144 => x"2e", + 5145 => x"80", + 5146 => x"0b", + 5147 => x"56", + 5148 => x"e9", + 5149 => x"06", + 5150 => x"57", + 5151 => x"32", + 5152 => x"05", + 5153 => x"79", + 5154 => x"54", + 5155 => x"74", + 5156 => x"09", + 5157 => x"38", + 5158 => x"fe", + 5159 => x"ea", + 5160 => x"8a", + 5161 => x"ec", + 5162 => x"85", + 5163 => x"2e", + 5164 => x"53", + 5165 => x"52", + 5166 => x"51", + 5167 => x"82", + 5168 => x"55", + 5169 => x"08", + 5170 => x"38", + 5171 => x"82", + 5172 => x"88", + 5173 => x"f1", + 5174 => x"02", + 5175 => x"cf", + 5176 => x"55", + 5177 => x"61", + 5178 => x"3f", + 5179 => x"08", + 5180 => x"80", + 5181 => x"ec", + 5182 => x"83", + 5183 => x"ec", + 5184 => x"82", + 5185 => x"08", + 5186 => x"56", + 5187 => x"86", + 5188 => x"75", + 5189 => x"fe", + 5190 => x"54", + 5191 => x"2e", + 5192 => x"14", + 5193 => x"a4", + 5194 => x"ec", + 5195 => x"06", + 5196 => x"54", + 5197 => x"38", + 5198 => x"86", + 5199 => x"82", + 5200 => x"06", + 5201 => x"56", + 5202 => x"38", + 5203 => x"80", + 5204 => x"81", + 5205 => x"52", + 5206 => x"51", + 5207 => x"82", + 5208 => x"81", + 5209 => x"81", + 5210 => x"83", + 5211 => x"8f", + 5212 => x"2e", + 5213 => x"82", + 5214 => x"06", + 5215 => x"56", + 5216 => x"38", + 5217 => x"74", + 5218 => x"a2", + 5219 => x"ec", + 5220 => x"06", + 5221 => x"2e", + 5222 => x"80", + 5223 => x"3d", + 5224 => x"83", + 5225 => x"15", + 5226 => x"53", + 5227 => x"8d", + 5228 => x"15", + 5229 => x"3f", + 5230 => x"08", + 5231 => x"70", + 5232 => x"0c", + 5233 => x"16", + 5234 => x"80", + 5235 => x"80", + 5236 => x"54", + 5237 => x"84", + 5238 => x"5c", + 5239 => x"80", + 5240 => x"7b", + 5241 => x"fc", + 5242 => x"85", + 5243 => x"ff", + 5244 => x"77", + 5245 => x"81", + 5246 => x"76", + 5247 => x"81", + 5248 => x"2e", + 5249 => x"8d", + 5250 => x"26", + 5251 => x"bf", + 5252 => x"ce", + 5253 => x"ec", + 5254 => x"ff", + 5255 => x"84", + 5256 => x"81", + 5257 => x"38", + 5258 => x"51", + 5259 => x"82", + 5260 => x"83", + 5261 => x"58", + 5262 => x"80", + 5263 => x"db", + 5264 => x"85", + 5265 => x"77", + 5266 => x"80", + 5267 => x"82", + 5268 => x"c4", + 5269 => x"11", + 5270 => x"06", + 5271 => x"8d", + 5272 => x"26", + 5273 => x"74", + 5274 => x"52", + 5275 => x"f8", + 5276 => x"85", + 5277 => x"c1", + 5278 => x"58", + 5279 => x"23", + 5280 => x"8b", + 5281 => x"73", + 5282 => x"80", + 5283 => x"8d", + 5284 => x"39", + 5285 => x"51", + 5286 => x"82", + 5287 => x"53", + 5288 => x"08", + 5289 => x"72", + 5290 => x"8d", + 5291 => x"cf", + 5292 => x"14", + 5293 => x"3f", + 5294 => x"08", + 5295 => x"06", + 5296 => x"38", + 5297 => x"51", + 5298 => x"82", + 5299 => x"55", + 5300 => x"51", + 5301 => x"82", + 5302 => x"83", + 5303 => x"5a", + 5304 => x"80", + 5305 => x"38", + 5306 => x"78", + 5307 => x"2a", + 5308 => x"78", + 5309 => x"87", + 5310 => x"22", + 5311 => x"31", + 5312 => x"87", + 5313 => x"ec", + 5314 => x"85", + 5315 => x"2e", + 5316 => x"82", + 5317 => x"80", + 5318 => x"f5", + 5319 => x"83", + 5320 => x"ff", + 5321 => x"38", + 5322 => x"9f", + 5323 => x"38", + 5324 => x"39", + 5325 => x"80", + 5326 => x"38", + 5327 => x"98", + 5328 => x"a0", + 5329 => x"1d", + 5330 => x"0c", + 5331 => x"17", + 5332 => x"76", + 5333 => x"81", + 5334 => x"80", + 5335 => x"d9", + 5336 => x"85", + 5337 => x"ff", + 5338 => x"8d", + 5339 => x"8f", + 5340 => x"8b", + 5341 => x"14", + 5342 => x"3f", + 5343 => x"08", + 5344 => x"74", + 5345 => x"a3", + 5346 => x"7a", + 5347 => x"ef", + 5348 => x"a8", + 5349 => x"15", + 5350 => x"2e", + 5351 => x"10", + 5352 => x"2a", + 5353 => x"11", + 5354 => x"83", + 5355 => x"2a", + 5356 => x"72", + 5357 => x"26", + 5358 => x"ff", + 5359 => x"0c", + 5360 => x"15", + 5361 => x"0b", + 5362 => x"76", + 5363 => x"81", + 5364 => x"38", + 5365 => x"51", + 5366 => x"82", + 5367 => x"83", + 5368 => x"53", + 5369 => x"09", + 5370 => x"f9", + 5371 => x"52", + 5372 => x"8a", + 5373 => x"ec", + 5374 => x"38", + 5375 => x"08", + 5376 => x"84", + 5377 => x"d7", + 5378 => x"85", + 5379 => x"ff", + 5380 => x"72", + 5381 => x"2e", + 5382 => x"80", + 5383 => x"14", + 5384 => x"3f", + 5385 => x"08", + 5386 => x"a4", + 5387 => x"81", + 5388 => x"84", + 5389 => x"d7", + 5390 => x"85", + 5391 => x"8a", + 5392 => x"2e", + 5393 => x"9d", + 5394 => x"14", + 5395 => x"3f", + 5396 => x"08", + 5397 => x"84", + 5398 => x"d7", + 5399 => x"85", + 5400 => x"15", + 5401 => x"34", + 5402 => x"22", + 5403 => x"72", + 5404 => x"23", + 5405 => x"23", + 5406 => x"15", + 5407 => x"75", + 5408 => x"0c", + 5409 => x"04", + 5410 => x"77", + 5411 => x"73", + 5412 => x"38", + 5413 => x"72", + 5414 => x"38", + 5415 => x"71", + 5416 => x"38", + 5417 => x"84", + 5418 => x"52", + 5419 => x"09", + 5420 => x"38", + 5421 => x"51", + 5422 => x"82", + 5423 => x"81", + 5424 => x"88", + 5425 => x"08", + 5426 => x"39", + 5427 => x"73", + 5428 => x"74", + 5429 => x"0c", + 5430 => x"04", + 5431 => x"02", + 5432 => x"7a", + 5433 => x"fc", + 5434 => x"f4", + 5435 => x"54", + 5436 => x"85", + 5437 => x"bc", + 5438 => x"ec", + 5439 => x"82", + 5440 => x"70", + 5441 => x"73", + 5442 => x"38", + 5443 => x"78", + 5444 => x"2e", + 5445 => x"74", + 5446 => x"0c", + 5447 => x"80", + 5448 => x"80", + 5449 => x"70", + 5450 => x"51", + 5451 => x"82", + 5452 => x"54", + 5453 => x"ec", + 5454 => x"0d", + 5455 => x"0d", + 5456 => x"05", + 5457 => x"33", + 5458 => x"54", + 5459 => x"84", + 5460 => x"bf", + 5461 => x"98", + 5462 => x"53", + 5463 => x"05", + 5464 => x"f3", + 5465 => x"ec", + 5466 => x"85", + 5467 => x"a6", + 5468 => x"68", + 5469 => x"70", + 5470 => x"a7", + 5471 => x"ec", + 5472 => x"85", + 5473 => x"38", + 5474 => x"05", + 5475 => x"2b", + 5476 => x"80", + 5477 => x"86", + 5478 => x"06", + 5479 => x"2e", + 5480 => x"74", + 5481 => x"38", + 5482 => x"09", + 5483 => x"38", + 5484 => x"d9", + 5485 => x"ec", + 5486 => x"39", + 5487 => x"33", + 5488 => x"73", + 5489 => x"77", + 5490 => x"81", + 5491 => x"73", + 5492 => x"38", + 5493 => x"be", + 5494 => x"07", + 5495 => x"b6", + 5496 => x"2a", + 5497 => x"51", + 5498 => x"2e", + 5499 => x"62", + 5500 => x"e8", + 5501 => x"85", + 5502 => x"82", + 5503 => x"52", + 5504 => x"51", + 5505 => x"62", + 5506 => x"8b", + 5507 => x"53", + 5508 => x"51", + 5509 => x"80", + 5510 => x"05", + 5511 => x"3f", + 5512 => x"0b", + 5513 => x"75", + 5514 => x"f1", + 5515 => x"11", + 5516 => x"80", + 5517 => x"97", + 5518 => x"51", + 5519 => x"82", + 5520 => x"55", + 5521 => x"08", + 5522 => x"b7", + 5523 => x"c6", + 5524 => x"05", + 5525 => x"2a", + 5526 => x"51", + 5527 => x"80", + 5528 => x"84", + 5529 => x"39", + 5530 => x"70", + 5531 => x"54", + 5532 => x"a9", + 5533 => x"06", + 5534 => x"2e", + 5535 => x"55", + 5536 => x"73", + 5537 => x"d5", + 5538 => x"85", + 5539 => x"ff", + 5540 => x"0c", + 5541 => x"85", + 5542 => x"fa", + 5543 => x"2a", + 5544 => x"51", + 5545 => x"2e", + 5546 => x"80", + 5547 => x"7a", + 5548 => x"a0", + 5549 => x"a4", + 5550 => x"53", + 5551 => x"e6", + 5552 => x"85", + 5553 => x"85", + 5554 => x"1b", + 5555 => x"05", + 5556 => x"a5", + 5557 => x"ec", + 5558 => x"ec", + 5559 => x"0c", + 5560 => x"56", + 5561 => x"84", + 5562 => x"90", + 5563 => x"0b", + 5564 => x"80", + 5565 => x"0c", + 5566 => x"1a", + 5567 => x"2a", + 5568 => x"51", + 5569 => x"2e", + 5570 => x"82", + 5571 => x"80", + 5572 => x"38", + 5573 => x"08", + 5574 => x"8a", + 5575 => x"89", + 5576 => x"59", + 5577 => x"76", + 5578 => x"d6", + 5579 => x"85", + 5580 => x"82", + 5581 => x"81", + 5582 => x"82", + 5583 => x"ec", + 5584 => x"09", + 5585 => x"38", + 5586 => x"78", + 5587 => x"09", + 5588 => x"76", + 5589 => x"51", + 5590 => x"27", + 5591 => x"70", + 5592 => x"5a", + 5593 => x"76", + 5594 => x"74", + 5595 => x"83", + 5596 => x"73", + 5597 => x"38", + 5598 => x"51", + 5599 => x"82", + 5600 => x"85", + 5601 => x"8e", + 5602 => x"2a", + 5603 => x"08", + 5604 => x"0c", + 5605 => x"79", + 5606 => x"73", + 5607 => x"0c", + 5608 => x"04", + 5609 => x"60", + 5610 => x"40", + 5611 => x"80", + 5612 => x"3d", + 5613 => x"78", + 5614 => x"3f", + 5615 => x"08", + 5616 => x"ec", + 5617 => x"91", + 5618 => x"74", + 5619 => x"38", + 5620 => x"c4", + 5621 => x"33", + 5622 => x"87", + 5623 => x"2e", + 5624 => x"95", + 5625 => x"91", + 5626 => x"56", + 5627 => x"81", + 5628 => x"34", + 5629 => x"a0", + 5630 => x"08", + 5631 => x"31", + 5632 => x"27", + 5633 => x"5c", + 5634 => x"82", + 5635 => x"19", + 5636 => x"ff", + 5637 => x"74", + 5638 => x"7e", + 5639 => x"ff", + 5640 => x"2a", + 5641 => x"79", + 5642 => x"87", + 5643 => x"08", + 5644 => x"98", + 5645 => x"78", + 5646 => x"3f", + 5647 => x"08", + 5648 => x"27", + 5649 => x"74", + 5650 => x"a3", + 5651 => x"1a", + 5652 => x"08", + 5653 => x"d4", + 5654 => x"85", + 5655 => x"2e", + 5656 => x"82", + 5657 => x"1a", + 5658 => x"59", + 5659 => x"2e", + 5660 => x"77", + 5661 => x"11", + 5662 => x"55", + 5663 => x"85", + 5664 => x"31", + 5665 => x"76", + 5666 => x"81", + 5667 => x"c9", + 5668 => x"85", + 5669 => x"d7", + 5670 => x"11", + 5671 => x"74", + 5672 => x"38", + 5673 => x"77", + 5674 => x"78", + 5675 => x"84", + 5676 => x"16", + 5677 => x"08", + 5678 => x"2b", + 5679 => x"cf", + 5680 => x"89", + 5681 => x"39", + 5682 => x"0c", + 5683 => x"83", + 5684 => x"80", + 5685 => x"55", + 5686 => x"83", + 5687 => x"9c", + 5688 => x"7e", + 5689 => x"3f", + 5690 => x"08", + 5691 => x"75", + 5692 => x"08", + 5693 => x"1f", + 5694 => x"7c", + 5695 => x"3f", + 5696 => x"7e", + 5697 => x"0c", + 5698 => x"1b", + 5699 => x"1c", + 5700 => x"fd", + 5701 => x"56", + 5702 => x"ec", + 5703 => x"0d", + 5704 => x"0d", + 5705 => x"64", + 5706 => x"58", + 5707 => x"90", + 5708 => x"52", + 5709 => x"d0", + 5710 => x"ec", + 5711 => x"85", + 5712 => x"38", + 5713 => x"55", + 5714 => x"86", + 5715 => x"83", + 5716 => x"18", + 5717 => x"2a", + 5718 => x"51", + 5719 => x"56", + 5720 => x"83", + 5721 => x"39", + 5722 => x"19", + 5723 => x"83", + 5724 => x"0b", + 5725 => x"81", + 5726 => x"39", + 5727 => x"7c", + 5728 => x"74", + 5729 => x"38", + 5730 => x"7b", + 5731 => x"ec", + 5732 => x"08", + 5733 => x"06", + 5734 => x"81", + 5735 => x"8a", + 5736 => x"05", + 5737 => x"06", + 5738 => x"bf", + 5739 => x"38", + 5740 => x"55", + 5741 => x"7a", + 5742 => x"98", + 5743 => x"77", + 5744 => x"3f", + 5745 => x"08", + 5746 => x"ec", + 5747 => x"82", + 5748 => x"81", + 5749 => x"38", + 5750 => x"ff", + 5751 => x"98", + 5752 => x"18", + 5753 => x"74", + 5754 => x"7e", + 5755 => x"08", + 5756 => x"2e", + 5757 => x"8d", + 5758 => x"ce", + 5759 => x"85", + 5760 => x"ee", + 5761 => x"08", + 5762 => x"d0", + 5763 => x"85", + 5764 => x"2e", + 5765 => x"82", + 5766 => x"1b", + 5767 => x"5a", + 5768 => x"2e", + 5769 => x"78", + 5770 => x"11", + 5771 => x"55", + 5772 => x"85", + 5773 => x"31", + 5774 => x"76", + 5775 => x"81", + 5776 => x"c8", + 5777 => x"85", + 5778 => x"a6", + 5779 => x"11", + 5780 => x"56", + 5781 => x"27", + 5782 => x"80", + 5783 => x"08", + 5784 => x"2b", + 5785 => x"b4", + 5786 => x"85", + 5787 => x"80", + 5788 => x"34", + 5789 => x"56", + 5790 => x"8c", + 5791 => x"19", + 5792 => x"38", + 5793 => x"86", + 5794 => x"ec", + 5795 => x"38", + 5796 => x"12", + 5797 => x"9c", + 5798 => x"18", + 5799 => x"06", + 5800 => x"31", + 5801 => x"76", + 5802 => x"7b", + 5803 => x"08", + 5804 => x"cd", + 5805 => x"85", + 5806 => x"b6", + 5807 => x"7c", + 5808 => x"08", + 5809 => x"1f", + 5810 => x"cb", + 5811 => x"55", + 5812 => x"16", + 5813 => x"31", + 5814 => x"7f", + 5815 => x"94", + 5816 => x"70", + 5817 => x"8c", + 5818 => x"58", + 5819 => x"76", + 5820 => x"75", + 5821 => x"19", + 5822 => x"39", + 5823 => x"80", + 5824 => x"74", + 5825 => x"80", + 5826 => x"85", + 5827 => x"3d", + 5828 => x"3d", + 5829 => x"3d", + 5830 => x"70", + 5831 => x"e8", + 5832 => x"ec", + 5833 => x"85", + 5834 => x"fb", + 5835 => x"33", + 5836 => x"70", + 5837 => x"55", + 5838 => x"2e", + 5839 => x"a0", + 5840 => x"78", + 5841 => x"3f", + 5842 => x"08", + 5843 => x"ec", + 5844 => x"38", + 5845 => x"8b", + 5846 => x"07", + 5847 => x"8b", + 5848 => x"16", + 5849 => x"52", + 5850 => x"dd", + 5851 => x"16", + 5852 => x"15", + 5853 => x"3f", + 5854 => x"0a", + 5855 => x"51", + 5856 => x"76", + 5857 => x"51", + 5858 => x"78", + 5859 => x"83", + 5860 => x"51", + 5861 => x"82", + 5862 => x"90", + 5863 => x"bf", + 5864 => x"73", + 5865 => x"76", + 5866 => x"0c", + 5867 => x"04", + 5868 => x"76", + 5869 => x"fe", + 5870 => x"85", + 5871 => x"82", + 5872 => x"9c", + 5873 => x"fc", + 5874 => x"51", + 5875 => x"82", + 5876 => x"53", + 5877 => x"08", + 5878 => x"85", + 5879 => x"0c", + 5880 => x"ec", + 5881 => x"0d", + 5882 => x"0d", + 5883 => x"e6", + 5884 => x"52", + 5885 => x"85", + 5886 => x"8b", + 5887 => x"ec", + 5888 => x"a4", + 5889 => x"71", + 5890 => x"0c", + 5891 => x"04", + 5892 => x"80", + 5893 => x"d0", + 5894 => x"3d", + 5895 => x"3f", + 5896 => x"08", + 5897 => x"ec", + 5898 => x"38", + 5899 => x"52", + 5900 => x"05", + 5901 => x"3f", + 5902 => x"08", + 5903 => x"ec", + 5904 => x"02", + 5905 => x"33", + 5906 => x"55", + 5907 => x"25", + 5908 => x"7a", + 5909 => x"54", + 5910 => x"a2", + 5911 => x"84", + 5912 => x"06", + 5913 => x"73", + 5914 => x"38", + 5915 => x"70", + 5916 => x"87", + 5917 => x"ec", + 5918 => x"0c", + 5919 => x"85", + 5920 => x"2e", + 5921 => x"83", + 5922 => x"74", + 5923 => x"0c", + 5924 => x"04", + 5925 => x"6f", + 5926 => x"80", + 5927 => x"53", + 5928 => x"b8", + 5929 => x"3d", + 5930 => x"3f", + 5931 => x"08", + 5932 => x"ec", + 5933 => x"38", + 5934 => x"7c", + 5935 => x"47", + 5936 => x"54", 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x"58", + 5996 => x"fe", + 5997 => x"7b", + 5998 => x"06", + 5999 => x"18", + 6000 => x"58", + 6001 => x"80", + 6002 => x"a4", + 6003 => x"2b", + 6004 => x"11", + 6005 => x"52", + 6006 => x"56", + 6007 => x"8d", + 6008 => x"70", + 6009 => x"51", + 6010 => x"f5", + 6011 => x"54", + 6012 => x"a7", + 6013 => x"74", + 6014 => x"38", + 6015 => x"73", + 6016 => x"81", + 6017 => x"81", + 6018 => x"39", + 6019 => x"81", + 6020 => x"74", + 6021 => x"81", + 6022 => x"91", + 6023 => x"6e", + 6024 => x"59", + 6025 => x"7a", + 6026 => x"5c", + 6027 => x"26", + 6028 => x"7a", + 6029 => x"85", + 6030 => x"3d", + 6031 => x"3d", + 6032 => x"8d", + 6033 => x"54", + 6034 => x"55", + 6035 => x"82", + 6036 => x"53", + 6037 => x"08", + 6038 => x"91", + 6039 => x"72", + 6040 => x"8c", + 6041 => x"73", + 6042 => x"38", + 6043 => x"70", + 6044 => x"81", + 6045 => x"57", + 6046 => x"73", + 6047 => x"08", + 6048 => x"94", + 6049 => x"75", + 6050 => x"99", + 6051 => x"11", + 6052 => x"2b", + 6053 => x"73", + 6054 => x"38", + 6055 => x"16", + 6056 => x"e7", + 6057 => x"ec", + 6058 => x"78", + 6059 => x"55", + 6060 => x"d7", + 6061 => x"ec", + 6062 => x"98", + 6063 => x"81", + 6064 => x"06", + 6065 => x"0c", + 6066 => x"98", + 6067 => x"58", + 6068 => x"39", + 6069 => x"54", + 6070 => x"73", + 6071 => x"cd", + 6072 => x"85", + 6073 => x"82", + 6074 => x"81", + 6075 => x"38", + 6076 => x"08", + 6077 => x"9b", + 6078 => x"ec", + 6079 => x"0c", + 6080 => x"0c", + 6081 => x"81", + 6082 => x"76", + 6083 => x"38", + 6084 => x"94", + 6085 => x"94", + 6086 => x"16", + 6087 => x"2a", + 6088 => x"51", + 6089 => x"72", + 6090 => x"38", + 6091 => x"51", + 6092 => x"82", + 6093 => x"54", + 6094 => x"08", + 6095 => x"85", + 6096 => x"a7", + 6097 => x"74", + 6098 => x"3f", + 6099 => x"08", + 6100 => x"2e", + 6101 => x"74", + 6102 => x"79", + 6103 => x"14", + 6104 => x"38", + 6105 => x"0c", + 6106 => x"94", + 6107 => x"94", + 6108 => x"83", + 6109 => x"72", + 6110 => x"38", + 6111 => x"51", + 6112 => x"82", + 6113 => x"94", + 6114 => x"91", + 6115 => x"53", + 6116 => x"81", + 6117 => x"34", + 6118 => x"39", + 6119 => x"82", + 6120 => x"05", + 6121 => x"08", + 6122 => x"08", + 6123 => x"38", + 6124 => x"0c", + 6125 => x"80", + 6126 => x"72", + 6127 => x"73", + 6128 => x"53", + 6129 => x"8c", + 6130 => x"16", + 6131 => x"38", + 6132 => x"0c", + 6133 => x"82", + 6134 => x"8b", + 6135 => x"f9", + 6136 => x"56", + 6137 => x"80", + 6138 => x"38", + 6139 => x"3d", + 6140 => x"8a", + 6141 => x"51", + 6142 => x"82", + 6143 => x"55", + 6144 => x"08", + 6145 => x"77", + 6146 => x"52", + 6147 => x"93", + 6148 => x"ec", + 6149 => x"85", + 6150 => x"c3", + 6151 => x"33", + 6152 => x"55", + 6153 => x"24", + 6154 => x"16", + 6155 => x"2a", + 6156 => x"51", + 6157 => x"80", + 6158 => x"9c", + 6159 => x"77", + 6160 => x"3f", + 6161 => x"08", + 6162 => x"77", + 6163 => x"22", + 6164 => x"74", + 6165 => x"ce", + 6166 => x"85", + 6167 => x"74", + 6168 => x"81", + 6169 => x"85", + 6170 => x"74", + 6171 => x"38", + 6172 => x"74", + 6173 => x"85", + 6174 => x"3d", + 6175 => x"3d", + 6176 => x"3d", + 6177 => x"70", + 6178 => x"fc", + 6179 => x"ec", + 6180 => x"82", + 6181 => x"73", + 6182 => x"0d", + 6183 => x"0d", + 6184 => x"3d", + 6185 => x"71", + 6186 => x"e7", + 6187 => x"85", + 6188 => x"82", + 6189 => x"80", + 6190 => x"93", + 6191 => x"ec", + 6192 => x"51", + 6193 => x"82", + 6194 => x"53", + 6195 => x"82", + 6196 => x"52", + 6197 => x"8a", + 6198 => x"ec", + 6199 => x"85", + 6200 => x"2e", + 6201 => x"85", + 6202 => x"87", + 6203 => x"ec", + 6204 => x"74", + 6205 => x"d5", + 6206 => x"52", + 6207 => x"e7", + 6208 => x"ec", + 6209 => x"70", + 6210 => x"70", + 6211 => x"2c", + 6212 => x"ec", + 6213 => x"51", + 6214 => x"82", + 6215 => x"87", + 6216 => x"ee", + 6217 => x"57", + 6218 => x"3d", + 6219 => x"3d", + 6220 => x"a3", + 6221 => x"ec", + 6222 => x"85", + 6223 => x"38", + 6224 => x"51", + 6225 => x"82", + 6226 => x"55", + 6227 => x"08", + 6228 => x"80", + 6229 => x"70", + 6230 => x"58", + 6231 => x"85", + 6232 => x"8d", + 6233 => x"2e", + 6234 => x"52", + 6235 => x"9a", + 6236 => x"85", + 6237 => x"3d", + 6238 => x"3d", + 6239 => x"55", + 6240 => x"92", + 6241 => x"52", + 6242 => x"de", + 6243 => x"85", + 6244 => x"82", + 6245 => x"82", + 6246 => x"74", + 6247 => x"98", + 6248 => x"11", + 6249 => x"59", + 6250 => x"75", + 6251 => x"38", + 6252 => x"81", + 6253 => x"5b", + 6254 => x"82", + 6255 => x"39", + 6256 => x"08", + 6257 => x"59", + 6258 => x"09", + 6259 => x"c1", + 6260 => x"5f", + 6261 => x"92", + 6262 => x"51", + 6263 => x"82", + 6264 => x"ff", + 6265 => x"82", + 6266 => x"81", + 6267 => x"82", + 6268 => x"09", + 6269 => x"82", + 6270 => x"07", + 6271 => x"05", + 6272 => x"53", + 6273 => x"98", + 6274 => x"26", + 6275 => x"fd", + 6276 => x"08", + 6277 => x"08", + 6278 => x"98", + 6279 => x"81", + 6280 => x"58", + 6281 => x"3f", + 6282 => x"08", + 6283 => x"ec", + 6284 => x"38", + 6285 => x"77", + 6286 => x"5d", + 6287 => x"74", + 6288 => x"81", + 6289 => x"b4", + 6290 => x"bb", + 6291 => x"85", + 6292 => x"ff", + 6293 => x"09", + 6294 => x"80", + 6295 => x"19", + 6296 => x"54", + 6297 => x"14", + 6298 => x"8d", + 6299 => x"ec", + 6300 => x"06", + 6301 => x"05", + 6302 => x"1b", + 6303 => x"5b", + 6304 => x"83", + 6305 => x"58", + 6306 => x"8e", + 6307 => x"0c", + 6308 => x"12", + 6309 => x"33", + 6310 => x"54", + 6311 => x"34", + 6312 => x"ec", + 6313 => x"0d", + 6314 => x"0d", + 6315 => x"fc", + 6316 => x"52", + 6317 => x"3f", + 6318 => x"08", + 6319 => x"ec", + 6320 => x"38", + 6321 => x"56", + 6322 => x"38", + 6323 => x"70", + 6324 => x"81", + 6325 => x"55", + 6326 => x"80", + 6327 => x"38", + 6328 => x"54", + 6329 => x"08", + 6330 => x"38", + 6331 => x"82", + 6332 => x"53", + 6333 => x"52", + 6334 => x"d9", + 6335 => x"ec", + 6336 => x"19", + 6337 => x"c9", + 6338 => x"08", + 6339 => x"ff", + 6340 => x"82", + 6341 => x"ff", + 6342 => x"06", + 6343 => x"56", + 6344 => x"08", + 6345 => x"81", + 6346 => x"82", + 6347 => x"75", + 6348 => x"54", + 6349 => x"08", + 6350 => x"27", + 6351 => x"17", + 6352 => x"85", + 6353 => x"76", + 6354 => x"3f", + 6355 => x"08", + 6356 => x"08", + 6357 => x"90", + 6358 => x"c0", + 6359 => x"90", + 6360 => x"80", + 6361 => x"75", + 6362 => x"75", + 6363 => x"85", + 6364 => x"3d", + 6365 => x"3d", + 6366 => x"a0", + 6367 => x"05", + 6368 => x"51", + 6369 => x"82", + 6370 => x"55", + 6371 => x"08", + 6372 => x"78", + 6373 => x"08", + 6374 => x"70", + 6375 => x"83", + 6376 => x"ec", + 6377 => x"85", + 6378 => x"dd", + 6379 => x"fb", + 6380 => x"85", + 6381 => x"06", + 6382 => x"86", + 6383 => x"c9", + 6384 => x"2b", + 6385 => x"24", + 6386 => x"02", + 6387 => x"33", + 6388 => x"58", + 6389 => x"76", + 6390 => x"6b", + 6391 => x"cc", + 6392 => x"85", + 6393 => x"84", + 6394 => x"06", + 6395 => x"73", + 6396 => x"d4", + 6397 => x"82", + 6398 => x"94", + 6399 => x"81", + 6400 => x"5a", + 6401 => x"08", + 6402 => x"8a", + 6403 => x"54", + 6404 => x"82", + 6405 => x"55", + 6406 => x"08", + 6407 => x"82", + 6408 => x"52", + 6409 => x"ba", + 6410 => x"ec", + 6411 => x"85", + 6412 => x"38", + 6413 => x"d1", + 6414 => x"ec", + 6415 => x"88", + 6416 => x"ec", + 6417 => x"38", + 6418 => x"97", + 6419 => x"ec", + 6420 => x"ec", + 6421 => x"05", + 6422 => x"ec", + 6423 => x"25", + 6424 => x"75", + 6425 => x"38", + 6426 => x"8f", + 6427 => x"75", + 6428 => x"c0", + 6429 => x"85", + 6430 => x"74", + 6431 => x"51", + 6432 => x"3f", + 6433 => x"08", + 6434 => x"85", + 6435 => x"3d", + 6436 => x"3d", + 6437 => x"99", + 6438 => x"52", + 6439 => x"d8", + 6440 => x"85", + 6441 => x"82", + 6442 => x"82", + 6443 => x"5e", + 6444 => x"3d", + 6445 => x"ce", + 6446 => x"85", + 6447 => x"82", + 6448 => x"86", + 6449 => x"82", + 6450 => x"85", + 6451 => x"2e", + 6452 => x"82", + 6453 => x"80", + 6454 => x"70", + 6455 => x"06", + 6456 => x"54", + 6457 => x"38", + 6458 => x"52", + 6459 => x"52", + 6460 => x"3f", + 6461 => x"08", + 6462 => x"82", + 6463 => x"83", + 6464 => x"82", + 6465 => x"81", + 6466 => x"06", + 6467 => x"54", + 6468 => x"08", + 6469 => x"81", + 6470 => x"81", + 6471 => x"39", + 6472 => x"38", + 6473 => x"08", + 6474 => x"c3", + 6475 => x"85", + 6476 => x"82", + 6477 => x"81", + 6478 => x"53", + 6479 => x"19", + 6480 => x"d0", + 6481 => x"ae", + 6482 => x"34", + 6483 => x"0b", + 6484 => x"82", + 6485 => x"52", + 6486 => x"51", + 6487 => x"3f", + 6488 => x"b4", + 6489 => x"c9", + 6490 => x"53", + 6491 => x"53", + 6492 => x"51", + 6493 => x"3f", + 6494 => x"0b", + 6495 => x"34", + 6496 => x"80", + 6497 => x"51", + 6498 => x"78", + 6499 => x"83", + 6500 => x"51", + 6501 => x"82", + 6502 => x"54", + 6503 => x"08", + 6504 => x"88", + 6505 => x"64", + 6506 => x"ff", + 6507 => x"75", + 6508 => x"78", + 6509 => x"3f", + 6510 => x"0b", + 6511 => x"78", + 6512 => x"83", + 6513 => x"51", + 6514 => x"3f", + 6515 => x"08", + 6516 => x"80", + 6517 => x"76", + 6518 => x"f9", + 6519 => x"85", + 6520 => x"3d", + 6521 => x"3d", + 6522 => x"84", + 6523 => x"d4", + 6524 => x"a8", + 6525 => x"05", + 6526 => x"51", + 6527 => x"82", + 6528 => x"55", + 6529 => x"08", + 6530 => x"78", + 6531 => x"08", + 6532 => x"70", + 6533 => x"8b", + 6534 => x"ec", + 6535 => x"85", + 6536 => x"b9", + 6537 => x"9b", + 6538 => x"a0", + 6539 => x"55", + 6540 => x"38", + 6541 => x"3d", + 6542 => x"3d", + 6543 => x"51", + 6544 => x"3f", + 6545 => x"52", + 6546 => x"52", + 6547 => x"a1", + 6548 => x"08", + 6549 => x"cb", + 6550 => x"85", + 6551 => x"82", + 6552 => x"95", + 6553 => x"2e", + 6554 => x"88", + 6555 => x"3d", + 6556 => x"38", + 6557 => x"e5", + 6558 => x"ec", + 6559 => x"09", + 6560 => x"b8", + 6561 => x"c9", + 6562 => x"85", + 6563 => x"82", + 6564 => x"81", + 6565 => x"56", + 6566 => x"3d", + 6567 => x"52", + 6568 => x"ff", + 6569 => x"02", + 6570 => x"8b", + 6571 => x"16", + 6572 => x"2a", + 6573 => x"51", + 6574 => x"89", + 6575 => x"07", + 6576 => x"17", + 6577 => x"81", + 6578 => x"34", + 6579 => x"70", + 6580 => x"81", + 6581 => x"55", + 6582 => x"80", + 6583 => x"64", + 6584 => x"38", + 6585 => x"51", + 6586 => x"82", + 6587 => x"52", + 6588 => x"b6", + 6589 => x"55", + 6590 => x"08", + 6591 => x"dd", + 6592 => x"ec", + 6593 => x"51", + 6594 => x"3f", + 6595 => x"08", + 6596 => x"11", + 6597 => x"82", + 6598 => x"80", + 6599 => x"16", + 6600 => x"ae", + 6601 => x"06", + 6602 => x"53", + 6603 => x"51", + 6604 => x"78", + 6605 => x"83", + 6606 => x"39", + 6607 => x"08", + 6608 => x"51", + 6609 => x"82", + 6610 => x"55", + 6611 => x"08", + 6612 => x"51", + 6613 => x"3f", + 6614 => x"08", + 6615 => x"85", + 6616 => x"3d", + 6617 => x"3d", + 6618 => x"db", + 6619 => x"84", + 6620 => x"05", + 6621 => x"82", + 6622 => x"d0", + 6623 => x"3d", + 6624 => x"3f", + 6625 => x"08", + 6626 => x"ec", + 6627 => x"38", + 6628 => x"52", + 6629 => x"05", + 6630 => x"3f", + 6631 => x"08", + 6632 => x"ec", + 6633 => x"02", + 6634 => x"33", + 6635 => x"54", + 6636 => x"aa", + 6637 => x"06", + 6638 => x"8b", + 6639 => x"06", + 6640 => x"07", + 6641 => x"56", + 6642 => x"34", + 6643 => x"0b", + 6644 => x"78", + 6645 => x"ed", + 6646 => x"ec", + 6647 => x"82", + 6648 => x"95", + 6649 => x"ef", + 6650 => x"56", + 6651 => x"3d", + 6652 => x"94", + 6653 => x"df", + 6654 => x"ec", + 6655 => x"85", + 6656 => x"cb", + 6657 => x"63", + 6658 => x"d4", + 6659 => x"93", + 6660 => x"ec", + 6661 => x"85", + 6662 => x"38", + 6663 => x"05", + 6664 => x"06", + 6665 => x"73", + 6666 => x"16", + 6667 => x"22", + 6668 => x"07", + 6669 => x"1f", + 6670 => x"86", + 6671 => x"81", + 6672 => x"34", + 6673 => x"b2", + 6674 => x"85", + 6675 => x"74", + 6676 => x"0c", + 6677 => x"04", + 6678 => x"69", + 6679 => x"80", + 6680 => x"d0", + 6681 => x"3d", + 6682 => x"3f", + 6683 => x"08", + 6684 => x"08", + 6685 => x"70", + 6686 => x"08", + 6687 => x"51", + 6688 => x"80", + 6689 => x"38", + 6690 => x"06", + 6691 => x"80", + 6692 => x"38", + 6693 => x"5f", + 6694 => x"3d", + 6695 => x"ff", + 6696 => x"82", + 6697 => x"57", + 6698 => x"08", + 6699 => x"74", + 6700 => x"c3", + 6701 => x"85", + 6702 => x"82", + 6703 => x"bf", + 6704 => x"ec", + 6705 => x"ec", + 6706 => x"59", + 6707 => x"81", + 6708 => x"56", + 6709 => x"33", + 6710 => x"16", + 6711 => x"27", + 6712 => x"56", + 6713 => x"80", + 6714 => x"80", + 6715 => x"ff", + 6716 => x"70", + 6717 => x"56", + 6718 => x"e8", + 6719 => x"76", + 6720 => x"81", + 6721 => x"80", + 6722 => x"57", + 6723 => x"05", + 6724 => x"80", + 6725 => x"7a", + 6726 => x"c1", + 6727 => x"2e", + 6728 => x"a0", + 6729 => x"51", + 6730 => x"3f", + 6731 => x"08", + 6732 => x"ec", + 6733 => x"7b", + 6734 => x"55", + 6735 => x"73", + 6736 => x"38", + 6737 => x"73", + 6738 => x"38", + 6739 => x"15", + 6740 => x"ff", + 6741 => x"82", + 6742 => x"7b", + 6743 => x"85", + 6744 => x"3d", + 6745 => x"3d", + 6746 => x"9c", + 6747 => x"05", + 6748 => x"51", + 6749 => x"82", + 6750 => x"82", + 6751 => x"56", + 6752 => x"ec", + 6753 => x"38", + 6754 => x"52", + 6755 => x"52", + 6756 => x"80", + 6757 => x"70", + 6758 => x"ff", + 6759 => x"55", + 6760 => x"27", + 6761 => x"78", + 6762 => x"ff", + 6763 => x"05", + 6764 => x"55", + 6765 => x"3f", + 6766 => x"08", + 6767 => x"38", + 6768 => x"70", + 6769 => x"ff", + 6770 => x"82", + 6771 => x"80", + 6772 => x"74", + 6773 => x"07", + 6774 => x"4e", + 6775 => x"82", + 6776 => x"55", + 6777 => x"70", + 6778 => x"06", + 6779 => x"99", + 6780 => x"e0", + 6781 => x"ff", + 6782 => x"54", + 6783 => x"27", + 6784 => x"fe", + 6785 => x"55", + 6786 => x"a3", + 6787 => x"82", + 6788 => x"ff", + 6789 => x"82", + 6790 => x"93", + 6791 => x"75", + 6792 => x"76", + 6793 => x"38", + 6794 => x"77", + 6795 => x"86", + 6796 => x"39", + 6797 => x"27", + 6798 => x"88", + 6799 => x"78", + 6800 => x"5a", + 6801 => x"57", + 6802 => x"81", + 6803 => x"81", + 6804 => x"33", + 6805 => x"06", + 6806 => x"57", + 6807 => x"fe", + 6808 => x"3d", + 6809 => x"55", + 6810 => x"2e", + 6811 => x"76", + 6812 => x"38", + 6813 => x"55", + 6814 => x"33", + 6815 => x"a0", + 6816 => x"06", + 6817 => x"17", + 6818 => x"38", + 6819 => x"43", + 6820 => x"3d", + 6821 => x"ff", + 6822 => x"82", + 6823 => x"54", + 6824 => x"08", + 6825 => x"81", + 6826 => x"ff", + 6827 => x"82", + 6828 => x"54", + 6829 => x"08", + 6830 => x"80", + 6831 => x"54", + 6832 => x"80", + 6833 => x"85", + 6834 => x"2e", + 6835 => x"80", + 6836 => x"54", + 6837 => x"80", + 6838 => x"52", + 6839 => x"bc", + 6840 => x"85", + 6841 => x"82", + 6842 => x"b1", + 6843 => x"82", + 6844 => x"52", + 6845 => x"ab", + 6846 => x"54", + 6847 => x"15", + 6848 => x"78", + 6849 => x"ff", + 6850 => x"79", + 6851 => x"83", + 6852 => x"51", + 6853 => x"3f", + 6854 => x"08", + 6855 => x"74", + 6856 => x"0c", + 6857 => x"04", + 6858 => x"60", + 6859 => x"05", + 6860 => x"33", + 6861 => x"05", + 6862 => x"40", + 6863 => x"c8", + 6864 => x"ec", + 6865 => x"85", + 6866 => x"bf", + 6867 => x"33", + 6868 => x"b7", + 6869 => x"2e", + 6870 => x"1a", + 6871 => x"90", + 6872 => x"33", + 6873 => x"70", + 6874 => x"55", + 6875 => x"38", + 6876 => x"99", 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x"1b", + 6936 => x"33", + 6937 => x"54", + 6938 => x"34", + 6939 => x"fe", + 6940 => x"08", + 6941 => x"74", + 6942 => x"75", + 6943 => x"16", + 6944 => x"33", + 6945 => x"73", + 6946 => x"77", + 6947 => x"85", + 6948 => x"3d", + 6949 => x"3d", + 6950 => x"02", + 6951 => x"eb", + 6952 => x"3d", + 6953 => x"59", + 6954 => x"8b", + 6955 => x"82", + 6956 => x"24", + 6957 => x"82", + 6958 => x"82", + 6959 => x"90", + 6960 => x"55", + 6961 => x"84", + 6962 => x"34", + 6963 => x"08", + 6964 => x"5f", + 6965 => x"51", + 6966 => x"3f", + 6967 => x"08", + 6968 => x"70", + 6969 => x"57", + 6970 => x"8b", + 6971 => x"82", + 6972 => x"06", + 6973 => x"56", + 6974 => x"38", + 6975 => x"05", + 6976 => x"7e", + 6977 => x"af", + 6978 => x"ec", + 6979 => x"67", + 6980 => x"2e", + 6981 => x"82", + 6982 => x"8b", + 6983 => x"75", + 6984 => x"80", + 6985 => x"81", + 6986 => x"2e", + 6987 => x"80", + 6988 => x"38", + 6989 => x"0a", + 6990 => x"ff", + 6991 => x"55", + 6992 => x"86", + 6993 => x"8a", + 6994 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=> x"72", + 7700 => x"0a", + 7701 => x"52", + 7702 => x"54", + 7703 => x"6e", + 7704 => x"72", + 7705 => x"0a", + 7706 => x"52", + 7707 => x"52", + 7708 => x"6e", + 7709 => x"72", + 7710 => x"0a", + 7711 => x"52", + 7712 => x"54", + 7713 => x"6e", + 7714 => x"72", + 7715 => x"0a", + 7716 => x"74", + 7717 => x"67", + 7718 => x"20", + 7719 => x"65", + 7720 => x"2e", + 7721 => x"00", + 7722 => x"61", + 7723 => x"6e", + 7724 => x"69", + 7725 => x"2e", + 7726 => x"00", + 7727 => x"74", + 7728 => x"65", + 7729 => x"61", + 7730 => x"00", + 7731 => x"53", + 7732 => x"74", + 7733 => x"00", + 7734 => x"69", + 7735 => x"20", + 7736 => x"69", + 7737 => x"69", + 7738 => x"73", + 7739 => x"64", + 7740 => x"72", + 7741 => x"2c", + 7742 => x"65", + 7743 => x"20", + 7744 => x"74", + 7745 => x"6e", + 7746 => x"6c", + 7747 => x"00", + 7748 => x"00", + 7749 => x"65", + 7750 => x"6e", + 7751 => x"2e", + 7752 => x"00", + 7753 => x"70", + 7754 => x"67", + 7755 => x"00", + 7756 => x"6d", + 7757 => x"69", + 7758 => x"2e", + 7759 => x"00", + 7760 => x"38", + 7761 => x"25", + 7762 => x"29", + 7763 => x"30", + 7764 => x"28", + 7765 => x"78", + 7766 => x"00", + 7767 => x"6d", + 7768 => x"65", + 7769 => x"79", + 7770 => x"00", + 7771 => x"6f", + 7772 => x"65", + 7773 => x"0a", + 7774 => x"38", + 7775 => x"30", + 7776 => x"00", + 7777 => x"3f", + 7778 => x"00", + 7779 => x"38", + 7780 => x"30", + 7781 => x"00", + 7782 => x"38", + 7783 => x"30", + 7784 => x"00", + 7785 => x"65", + 7786 => x"69", + 7787 => x"63", + 7788 => x"20", + 7789 => x"30", + 7790 => x"2e", + 7791 => x"00", + 7792 => x"6c", + 7793 => x"67", + 7794 => x"64", + 7795 => x"20", + 7796 => x"78", + 7797 => x"2e", + 7798 => x"00", + 7799 => x"6c", + 7800 => x"65", + 7801 => x"6e", + 7802 => x"63", + 7803 => x"20", + 7804 => x"29", + 7805 => x"00", + 7806 => x"73", + 7807 => x"74", + 7808 => x"20", + 7809 => x"6c", + 7810 => x"74", + 7811 => x"2e", + 7812 => x"00", + 7813 => x"6c", + 7814 => x"65", + 7815 => x"74", + 7816 => x"2e", + 7817 => x"00", + 7818 => x"55", + 7819 => x"6e", + 7820 => x"3a", + 7821 => x"5c", + 7822 => x"25", + 7823 => x"00", + 7824 => x"3a", + 7825 => x"5c", + 7826 => x"00", + 7827 => x"3a", + 7828 => x"00", + 7829 => x"64", + 7830 => x"6d", + 7831 => x"64", + 7832 => x"00", + 7833 => x"6e", + 7834 => x"67", + 7835 => x"0a", + 7836 => x"61", + 7837 => x"6e", + 7838 => x"6e", + 7839 => x"72", + 7840 => x"73", + 7841 => x"0a", + 7842 => x"2f", + 7843 => x"25", + 7844 => x"64", + 7845 => x"3a", + 7846 => x"25", + 7847 => x"0a", + 7848 => x"43", + 7849 => x"6e", + 7850 => x"75", + 7851 => x"69", + 7852 => x"00", + 7853 => x"66", + 7854 => x"20", + 7855 => x"20", + 7856 => x"66", + 7857 => x"00", + 7858 => x"44", + 7859 => x"63", + 7860 => x"69", + 7861 => x"65", + 7862 => x"74", + 7863 => x"0a", + 7864 => x"20", + 7865 => x"20", + 7866 => x"41", + 7867 => x"28", + 7868 => x"58", + 7869 => x"38", + 7870 => x"0a", + 7871 => x"20", + 7872 => x"52", + 7873 => x"20", + 7874 => x"28", + 7875 => x"58", + 7876 => x"38", + 7877 => x"0a", + 7878 => x"20", + 7879 => x"53", + 7880 => x"52", + 7881 => x"28", + 7882 => x"58", + 7883 => x"38", + 7884 => x"0a", + 7885 => x"20", + 7886 => x"41", + 7887 => x"20", + 7888 => x"28", + 7889 => x"58", + 7890 => x"38", + 7891 => x"0a", + 7892 => x"20", + 7893 => x"4d", + 7894 => x"20", + 7895 => x"28", + 7896 => x"58", + 7897 => x"38", + 7898 => x"0a", + 7899 => x"20", + 7900 => x"20", + 7901 => x"44", + 7902 => x"28", + 7903 => x"69", + 7904 => x"20", + 7905 => x"32", + 7906 => x"0a", + 7907 => x"20", + 7908 => x"4d", + 7909 => x"20", + 7910 => x"28", + 7911 => x"65", + 7912 => x"20", + 7913 => x"32", + 7914 => x"0a", + 7915 => x"20", + 7916 => x"54", + 7917 => x"54", + 7918 => x"28", + 7919 => x"6e", + 7920 => x"73", + 7921 => x"32", + 7922 => x"0a", + 7923 => x"20", + 7924 => x"53", + 7925 => x"4e", + 7926 => x"55", + 7927 => x"00", + 7928 => x"20", + 7929 => x"20", + 7930 => x"0a", + 7931 => x"20", + 7932 => x"43", + 7933 => x"00", + 7934 => x"20", + 7935 => x"32", + 7936 => x"00", + 7937 => x"20", + 7938 => x"49", + 7939 => x"00", + 7940 => x"64", + 7941 => x"73", + 7942 => x"0a", + 7943 => x"20", + 7944 => x"55", + 7945 => x"73", + 7946 => x"56", + 7947 => x"6f", + 7948 => x"64", + 7949 => x"73", + 7950 => x"20", + 7951 => x"58", + 7952 => x"00", + 7953 => x"20", + 7954 => x"55", + 7955 => x"6d", + 7956 => x"20", + 7957 => x"72", + 7958 => x"64", + 7959 => x"73", + 7960 => x"20", + 7961 => x"58", + 7962 => x"00", + 7963 => x"20", + 7964 => x"61", + 7965 => x"53", + 7966 => x"74", + 7967 => x"64", + 7968 => x"73", + 7969 => x"20", + 7970 => x"20", + 7971 => x"58", + 7972 => x"00", + 7973 => x"73", + 7974 => x"00", + 7975 => x"20", + 7976 => x"55", + 7977 => x"20", + 7978 => x"20", + 7979 => x"20", + 7980 => x"20", + 7981 => x"20", + 7982 => x"20", + 7983 => x"58", + 7984 => x"00", + 7985 => x"20", + 7986 => x"73", + 7987 => x"20", + 7988 => x"63", + 7989 => x"72", + 7990 => x"20", + 7991 => x"20", + 7992 => x"20", + 7993 => x"25", + 7994 => x"4d", + 7995 => x"00", + 7996 => x"20", + 7997 => x"52", + 7998 => x"43", + 7999 => x"6b", + 8000 => x"65", + 8001 => x"20", + 8002 => x"20", + 8003 => x"20", + 8004 => x"25", + 8005 => x"4d", + 8006 => x"00", + 8007 => x"20", + 8008 => x"73", + 8009 => x"6e", + 8010 => x"44", + 8011 => x"20", + 8012 => x"63", + 8013 => x"72", + 8014 => x"20", + 8015 => x"25", + 8016 => x"4d", + 8017 => x"00", + 8018 => x"61", + 8019 => x"00", + 8020 => x"64", + 8021 => x"00", + 8022 => x"65", + 8023 => x"00", + 8024 => x"4f", + 8025 => x"4f", + 8026 => x"00", + 8027 => x"6b", + 8028 => x"6e", + 8029 => x"7e", + 8030 => x"00", + 8031 => x"00", + 8032 => x"7e", + 8033 => x"00", + 8034 => x"00", + 8035 => x"7e", + 8036 => x"00", + 8037 => x"00", + 8038 => x"7e", + 8039 => x"00", + 8040 => x"00", + 8041 => x"7e", + 8042 => x"00", + 8043 => x"00", + 8044 => x"7e", + 8045 => x"00", + 8046 => x"00", + 8047 => x"7e", + 8048 => x"00", + 8049 => x"00", + 8050 => x"7e", + 8051 => x"00", + 8052 => x"00", + 8053 => x"7e", + 8054 => x"00", + 8055 => x"00", + 8056 => x"7e", + 8057 => x"00", + 8058 => x"00", + 8059 => x"7e", + 8060 => x"00", + 8061 => x"00", + 8062 => x"7e", + 8063 => x"00", + 8064 => x"00", + 8065 => x"7e", + 8066 => x"00", + 8067 => x"00", + 8068 => x"7e", + 8069 => x"00", + 8070 => x"00", + 8071 => x"7e", + 8072 => x"00", + 8073 => x"00", + 8074 => x"7e", + 8075 => x"00", + 8076 => x"00", + 8077 => x"7e", + 8078 => x"00", + 8079 => x"00", + 8080 => x"7e", + 8081 => x"00", + 8082 => x"00", + 8083 => x"7e", + 8084 => x"00", + 8085 => x"00", + 8086 => x"7e", + 8087 => x"00", + 8088 => x"00", + 8089 => x"7e", + 8090 => x"00", + 8091 => x"00", + 8092 => x"7e", + 8093 => x"00", + 8094 => x"00", + 8095 => x"44", + 8096 => x"43", + 8097 => x"42", + 8098 => x"41", + 8099 => x"36", + 8100 => x"35", + 8101 => x"34", + 8102 => x"46", + 8103 => x"33", + 8104 => x"32", + 8105 => x"31", + 8106 => x"00", + 8107 => x"00", + 8108 => x"00", + 8109 => x"00", + 8110 => x"00", + 8111 => x"00", + 8112 => x"00", + 8113 => x"00", + 8114 => x"00", + 8115 => x"00", + 8116 => x"00", + 8117 => x"73", + 8118 => x"79", + 8119 => x"73", + 8120 => x"00", + 8121 => x"00", + 8122 => x"34", + 8123 => x"25", + 8124 => x"00", + 8125 => x"69", + 8126 => x"20", + 8127 => x"72", + 8128 => x"74", + 8129 => x"65", + 8130 => x"73", + 8131 => x"79", + 8132 => x"6c", + 8133 => x"6f", + 8134 => x"46", + 8135 => x"00", + 8136 => x"6e", + 8137 => x"20", + 8138 => x"6e", + 8139 => x"65", + 8140 => x"20", + 8141 => x"74", + 8142 => x"20", + 8143 => x"65", + 8144 => x"69", + 8145 => x"6c", + 8146 => x"2e", + 8147 => x"00", + 8148 => x"00", + 8149 => x"2b", + 8150 => x"3c", + 8151 => x"5b", + 8152 => x"00", + 8153 => x"54", + 8154 => x"54", + 8155 => x"00", + 8156 => x"90", + 8157 => x"4f", + 8158 => x"30", + 8159 => x"20", + 8160 => x"45", + 8161 => x"20", + 8162 => x"33", + 8163 => x"20", + 8164 => x"20", + 8165 => x"45", + 8166 => x"20", + 8167 => x"20", + 8168 => x"20", + 8169 => x"7f", + 8170 => x"00", + 8171 => x"00", + 8172 => x"00", + 8173 => x"45", + 8174 => x"8f", + 8175 => x"45", + 8176 => x"8e", + 8177 => x"92", + 8178 => x"55", + 8179 => x"9a", + 8180 => x"9e", + 8181 => x"4f", + 8182 => x"a6", + 8183 => x"aa", + 8184 => x"ae", + 8185 => x"b2", + 8186 => x"b6", + 8187 => x"ba", + 8188 => x"be", + 8189 => x"c2", + 8190 => x"c6", + 8191 => x"ca", + 8192 => x"ce", + 8193 => x"d2", + 8194 => x"d6", + 8195 => x"da", + 8196 => x"de", + 8197 => x"e2", + 8198 => x"e6", + 8199 => x"ea", + 8200 => x"ee", + 8201 => x"f2", + 8202 => x"f6", + 8203 => x"fa", + 8204 => x"fe", + 8205 => x"2c", + 8206 => x"5d", + 8207 => x"2a", + 8208 => x"3f", + 8209 => x"00", + 8210 => x"00", + 8211 => x"00", + 8212 => x"02", + 8213 => x"00", + 8214 => x"00", + 8215 => x"00", + 8216 => x"00", + 8217 => x"00", + 8218 => x"00", + 8219 => x"74", + 8220 => x"01", + 8221 => x"00", + 8222 => x"00", + 8223 => x"74", + 8224 => x"01", + 8225 => x"00", + 8226 => x"00", + 8227 => x"74", + 8228 => x"03", + 8229 => x"00", + 8230 => x"00", + 8231 => x"74", + 8232 => x"03", + 8233 => x"00", + 8234 => x"00", + 8235 => x"74", + 8236 => x"03", + 8237 => x"00", + 8238 => x"00", + 8239 => x"74", + 8240 => x"04", + 8241 => x"00", + 8242 => x"00", + 8243 => x"74", + 8244 => x"04", + 8245 => x"00", + 8246 => x"00", + 8247 => x"75", + 8248 => x"04", + 8249 => x"00", + 8250 => x"00", + 8251 => x"75", + 8252 => x"04", + 8253 => x"00", + 8254 => x"00", + 8255 => x"75", + 8256 => x"04", + 8257 => x"00", + 8258 => x"00", + 8259 => x"75", + 8260 => x"04", + 8261 => x"00", + 8262 => x"00", + 8263 => x"75", + 8264 => x"04", + 8265 => x"00", + 8266 => x"00", + 8267 => x"75", + 8268 => x"05", + 8269 => x"00", + 8270 => x"00", + 8271 => x"75", + 8272 => x"05", + 8273 => x"00", + 8274 => x"00", + 8275 => x"75", + 8276 => x"05", + 8277 => x"00", + 8278 => x"00", + 8279 => x"75", + 8280 => x"05", + 8281 => x"00", + 8282 => x"00", + 8283 => x"75", + 8284 => x"07", + 8285 => x"00", + 8286 => x"00", + 8287 => x"75", + 8288 => x"07", + 8289 => x"00", + 8290 => x"00", + 8291 => x"75", + 8292 => x"08", + 8293 => x"00", + 8294 => x"00", + 8295 => x"75", + 8296 => x"08", + 8297 => x"00", + 8298 => x"00", + 8299 => x"75", + 8300 => x"08", + 8301 => x"00", + 8302 => x"00", + 8303 => x"75", + 8304 => x"08", + 8305 => x"00", + 8306 => x"00", + 8307 => x"75", + 8308 => x"09", + 8309 => x"00", + 8310 => x"00", + 8311 => x"75", + 8312 => x"09", + 8313 => x"00", + 8314 => x"00", + 8315 => x"75", + 8316 => x"09", + 8317 => x"00", + 8318 => x"00", + 8319 => x"75", + 8320 => x"09", + 8321 => x"00", + 8322 => x"00", + 8323 => x"00", + 8324 => x"00", + 8325 => x"7f", + 8326 => x"00", + 8327 => x"7f", + 8328 => x"00", + 8329 => x"7f", + 8330 => x"00", + 8331 => x"00", + 8332 => x"00", + 8333 => x"ff", + 8334 => x"00", + 8335 => x"00", + 8336 => x"78", + 8337 => x"00", + 8338 => x"e1", + 8339 => x"e1", + 8340 => x"e1", + 8341 => x"00", + 8342 => x"01", + 8343 => x"01", + 8344 => x"10", + 8345 => x"00", + 8346 => x"00", + 8347 => x"00", + 8348 => x"00", + 8349 => x"00", + 8350 => x"00", + 8351 => x"00", + 8352 => x"00", + 8353 => x"00", + 8354 => x"00", + 8355 => x"00", + 8356 => x"00", + 8357 => x"00", + 8358 => x"00", + 8359 => x"00", + 8360 => x"00", + 8361 => x"00", + 8362 => x"00", + 8363 => x"00", + 8364 => x"00", + 8365 => x"00", + 8366 => x"00", + 8367 => x"00", + 8368 => x"00", + 8369 => x"00", + 8370 => x"7e", + 8371 => x"00", + 8372 => x"7e", + 8373 => x"00", + 8374 => x"7e", + 8375 => x"00", + 8376 => x"00", + 8377 => x"00", + 8378 => x"00", + others => X"00" + ); + + shared variable RAM2 : ramArray := + ( + 0 => x"0b", + 1 => x"0d", + 2 => x"93", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"08", + 9 => x"08", + 10 => x"2d", + 11 => x"0c", + 12 => x"00", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"fd", + 17 => x"83", + 18 => x"05", + 19 => x"2b", + 20 => x"ff", + 21 => x"00", + 22 => x"00", + 23 => x"00", + 24 => x"fd", + 25 => x"ff", + 26 => x"06", + 27 => x"82", + 28 => x"2b", + 29 => x"83", + 30 => x"0b", + 31 => x"a5", + 32 => x"09", + 33 => x"05", + 34 => x"06", + 35 => x"09", + 36 => x"0a", + 37 => x"51", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"2e", + 42 => x"04", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"73", + 49 => x"06", + 50 => x"81", + 51 => x"10", + 52 => x"10", + 53 => x"0a", + 54 => x"51", + 55 => x"00", + 56 => x"72", + 57 => x"2e", + 58 => x"04", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"04", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"0a", + 81 => x"53", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"81", + 90 => x"0b", + 91 => x"04", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"9f", + 98 => x"74", + 99 => x"06", + 100 => x"07", + 101 => x"00", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"06", + 106 => x"09", + 107 => x"05", + 108 => x"2b", + 109 => x"06", + 110 => x"04", + 111 => x"00", + 112 => x"09", + 113 => x"05", + 114 => x"05", + 115 => x"81", + 116 => x"04", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"09", + 121 => x"05", + 122 => x"05", + 123 => x"09", + 124 => x"51", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"09", + 129 => x"04", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"00", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"09", + 145 => x"73", + 146 => x"53", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"fc", + 153 => x"83", + 154 => x"05", + 155 => x"10", + 156 => x"ff", + 157 => x"00", + 158 => x"00", + 159 => x"00", + 160 => x"fc", + 161 => x"0b", + 162 => x"73", + 163 => x"10", + 164 => x"0b", + 165 => x"e7", + 166 => x"00", + 167 => x"00", + 168 => x"08", + 169 => x"08", + 170 => x"0b", + 171 => x"2d", + 172 => x"08", + 173 => x"8c", + 174 => x"51", + 175 => x"00", + 176 => x"08", + 177 => x"08", + 178 => x"0b", + 179 => x"2d", + 180 => x"08", + 181 => x"8c", + 182 => x"51", + 183 => x"00", + 184 => x"09", + 185 => x"09", + 186 => x"06", + 187 => x"54", + 188 => x"09", + 189 => x"ff", + 190 => x"51", + 191 => x"00", + 192 => x"09", + 193 => x"09", + 194 => x"81", + 195 => x"70", + 196 => x"73", + 197 => x"05", + 198 => x"07", + 199 => x"04", + 200 => x"ff", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"00", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"81", + 217 => x"00", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"00", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"84", + 233 => x"10", + 234 => x"00", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"71", + 250 => x"0d", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"00", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"0b", + 265 => x"04", + 266 => x"8c", + 267 => x"0b", + 268 => x"04", + 269 => x"8c", + 270 => x"0b", + 271 => x"04", + 272 => x"8c", + 273 => x"0b", + 274 => x"04", + 275 => x"8c", + 276 => x"0b", + 277 => x"04", + 278 => x"8d", + 279 => x"0b", + 280 => x"04", + 281 => x"8d", + 282 => x"0b", + 283 => x"04", + 284 => x"8d", + 285 => x"0b", + 286 => x"04", + 287 => x"8d", + 288 => x"0b", + 289 => x"04", + 290 => x"8e", + 291 => x"0b", + 292 => x"04", + 293 => x"8e", + 294 => x"0b", + 295 => x"04", + 296 => x"8e", + 297 => x"0b", + 298 => x"04", + 299 => x"8e", + 300 => x"0b", + 301 => x"04", + 302 => x"8f", + 303 => x"0b", + 304 => x"04", + 305 => x"8f", + 306 => x"0b", + 307 => x"04", + 308 => x"8f", + 309 => x"0b", + 310 => x"04", + 311 => x"8f", + 312 => x"0b", + 313 => x"04", + 314 => x"90", + 315 => x"0b", + 316 => x"04", + 317 => x"90", + 318 => x"0b", + 319 => x"04", + 320 => x"90", + 321 => x"0b", + 322 => x"04", + 323 => x"90", + 324 => x"0b", + 325 => x"04", + 326 => x"91", + 327 => x"0b", + 328 => x"04", + 329 => x"91", + 330 => x"0b", + 331 => x"04", + 332 => x"91", + 333 => x"0b", + 334 => x"04", + 335 => x"91", + 336 => x"0b", + 337 => x"04", + 338 => x"92", + 339 => x"0b", + 340 => x"04", + 341 => x"92", + 342 => x"0b", + 343 => x"04", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"00", + 385 => x"82", + 386 => x"80", + 387 => x"82", + 388 => x"82", + 389 => x"82", + 390 => x"80", + 391 => x"82", + 392 => x"82", + 393 => x"82", + 394 => x"80", + 395 => x"82", + 396 => x"82", + 397 => x"82", + 398 => x"80", + 399 => x"82", + 400 => x"82", + 401 => x"82", + 402 => x"80", + 403 => x"82", + 404 => x"82", + 405 => x"82", + 406 => x"80", + 407 => x"82", + 408 => x"82", + 409 => x"82", + 410 => x"80", + 411 => x"82", + 412 => x"82", + 413 => x"82", + 414 => x"80", + 415 => x"82", + 416 => x"82", + 417 => x"82", + 418 => x"80", + 419 => x"82", + 420 => x"82", + 421 => x"82", + 422 => x"80", + 423 => x"82", + 424 => x"82", + 425 => x"82", + 426 => x"80", + 427 => x"82", + 428 => x"82", + 429 => x"82", + 430 => x"80", + 431 => x"82", + 432 => x"82", + 433 => x"82", + 434 => x"80", + 435 => x"82", + 436 => x"82", + 437 => x"82", + 438 => x"80", + 439 => x"82", + 440 => x"82", + 441 => x"82", + 442 => x"80", + 443 => x"82", + 444 => x"82", + 445 => x"82", + 446 => x"bb", + 447 => x"85", + 448 => x"a0", + 449 => x"85", + 450 => x"bd", + 451 => x"f8", + 452 => x"90", + 453 => x"f8", + 454 => x"2d", + 455 => x"08", + 456 => x"04", + 457 => x"0c", + 458 => x"2d", + 459 => x"08", + 460 => x"04", + 461 => x"0c", + 462 => x"2d", + 463 => x"08", + 464 => x"04", + 465 => x"0c", + 466 => x"2d", + 467 => x"08", + 468 => x"04", + 469 => x"0c", + 470 => x"2d", + 471 => x"08", + 472 => x"04", + 473 => x"0c", + 474 => x"2d", + 475 => x"08", + 476 => x"04", + 477 => x"0c", + 478 => x"2d", + 479 => x"08", + 480 => x"04", + 481 => x"0c", + 482 => x"2d", + 483 => x"08", + 484 => x"04", + 485 => x"0c", + 486 => x"2d", + 487 => x"08", + 488 => x"04", + 489 => x"0c", + 490 => x"2d", + 491 => x"08", + 492 => x"04", + 493 => x"0c", + 494 => x"2d", + 495 => x"08", + 496 => x"04", + 497 => x"0c", + 498 => x"2d", + 499 => x"08", + 500 => x"04", + 501 => x"0c", + 502 => x"2d", + 503 => x"08", + 504 => x"04", + 505 => x"0c", + 506 => x"2d", + 507 => x"08", + 508 => x"04", + 509 => x"0c", + 510 => x"2d", + 511 => x"08", + 512 => x"04", + 513 => x"0c", + 514 => x"2d", + 515 => x"08", + 516 => x"04", + 517 => x"0c", + 518 => x"2d", + 519 => x"08", + 520 => x"04", + 521 => x"0c", + 522 => x"2d", + 523 => x"08", + 524 => x"04", + 525 => x"0c", + 526 => x"2d", + 527 => x"08", + 528 => x"04", + 529 => x"0c", + 530 => x"2d", + 531 => x"08", + 532 => x"04", + 533 => x"0c", + 534 => x"2d", + 535 => x"08", + 536 => x"04", + 537 => x"0c", + 538 => x"2d", + 539 => x"08", + 540 => x"04", + 541 => x"0c", + 542 => x"2d", + 543 => x"08", + 544 => x"04", + 545 => x"0c", + 546 => x"2d", + 547 => x"08", + 548 => x"04", + 549 => x"0c", + 550 => x"2d", + 551 => x"08", + 552 => x"04", + 553 => x"0c", + 554 => x"2d", + 555 => x"08", + 556 => x"04", + 557 => x"0c", + 558 => x"2d", + 559 => x"08", + 560 => x"04", + 561 => x"0c", + 562 => x"2d", + 563 => x"08", + 564 => x"04", + 565 => x"0c", + 566 => x"2d", + 567 => x"08", + 568 => x"04", + 569 => x"0c", + 570 => x"2d", + 571 => x"08", + 572 => x"04", + 573 => x"0c", + 574 => x"2d", + 575 => x"08", + 576 => x"04", + 577 => x"0c", + 578 => x"82", + 579 => x"82", + 580 => x"82", + 581 => x"bd", + 582 => x"85", + 583 => x"a0", + 584 => x"85", + 585 => x"c0", + 586 => x"85", + 587 => x"a0", + 588 => x"85", + 589 => x"fd", + 590 => x"f8", + 591 => x"90", + 592 => x"00", + 593 => x"10", + 594 => x"10", + 595 => x"10", + 596 => x"10", + 597 => x"10", + 598 => x"10", + 599 => x"10", + 600 => x"10", + 601 => x"00", + 602 => x"ff", + 603 => x"06", + 604 => x"83", + 605 => x"10", + 606 => x"fc", + 607 => x"51", + 608 => x"80", + 609 => x"ff", + 610 => x"06", + 611 => x"52", + 612 => x"0a", + 613 => x"38", + 614 => x"51", + 615 => x"ec", + 616 => x"a8", + 617 => x"80", + 618 => x"05", + 619 => x"0b", + 620 => x"04", + 621 => x"ba", + 622 => x"82", + 623 => x"02", + 624 => x"0c", + 625 => x"82", + 626 => x"88", + 627 => x"85", + 628 => x"05", + 629 => x"f8", + 630 => x"08", + 631 => x"82", + 632 => x"fc", + 633 => x"05", + 634 => x"08", + 635 => x"70", + 636 => x"51", + 637 => x"2e", + 638 => x"39", + 639 => x"08", + 640 => x"ff", + 641 => x"f8", + 642 => x"0c", + 643 => x"08", + 644 => x"82", + 645 => x"88", + 646 => x"70", + 647 => x"0c", + 648 => x"0d", + 649 => x"0c", + 650 => x"f8", + 651 => x"85", + 652 => x"3d", + 653 => x"f8", + 654 => x"08", + 655 => x"08", + 656 => x"82", + 657 => x"8c", + 658 => x"71", + 659 => x"f8", + 660 => x"08", + 661 => x"85", + 662 => x"05", + 663 => x"f8", + 664 => x"08", + 665 => x"72", + 666 => x"f8", + 667 => x"08", + 668 => x"85", + 669 => x"05", + 670 => x"ff", + 671 => x"80", + 672 => x"ff", + 673 => x"85", + 674 => x"05", + 675 => x"85", + 676 => x"84", + 677 => x"85", + 678 => x"82", + 679 => x"02", + 680 => x"0c", + 681 => x"82", + 682 => x"88", + 683 => x"85", + 684 => x"05", + 685 => x"f8", + 686 => x"08", + 687 => x"08", + 688 => x"82", + 689 => x"90", + 690 => x"2e", + 691 => x"82", + 692 => x"90", + 693 => x"05", + 694 => x"08", + 695 => x"82", + 696 => x"90", + 697 => x"05", + 698 => x"08", + 699 => x"82", + 700 => x"90", + 701 => x"2e", + 702 => x"85", + 703 => x"05", + 704 => x"33", + 705 => x"08", + 706 => x"81", + 707 => x"f8", + 708 => x"0c", + 709 => x"08", + 710 => x"52", + 711 => x"34", + 712 => x"08", + 713 => x"81", + 714 => x"f8", + 715 => x"0c", + 716 => x"82", + 717 => x"88", + 718 => x"82", + 719 => x"51", + 720 => x"82", + 721 => x"04", + 722 => x"08", + 723 => x"f8", + 724 => x"0d", + 725 => x"08", + 726 => x"80", + 727 => x"38", + 728 => x"08", + 729 => x"52", + 730 => x"85", + 731 => x"05", + 732 => x"82", + 733 => x"8c", + 734 => x"85", + 735 => x"05", + 736 => x"72", + 737 => x"53", + 738 => x"71", + 739 => x"38", + 740 => x"82", + 741 => x"88", + 742 => x"71", + 743 => x"f8", + 744 => x"08", + 745 => x"85", + 746 => x"05", + 747 => x"ff", + 748 => x"70", + 749 => x"0b", + 750 => x"08", + 751 => x"81", + 752 => x"85", + 753 => x"05", + 754 => x"82", + 755 => x"90", + 756 => x"85", + 757 => x"05", + 758 => x"84", + 759 => x"39", + 760 => x"08", + 761 => x"80", + 762 => x"38", + 763 => x"08", + 764 => x"70", + 765 => x"70", + 766 => x"0b", + 767 => x"08", + 768 => x"80", + 769 => x"85", + 770 => x"05", + 771 => x"82", + 772 => x"8c", + 773 => x"85", + 774 => x"05", + 775 => x"52", + 776 => x"38", + 777 => x"85", + 778 => x"05", + 779 => x"82", + 780 => x"88", + 781 => x"33", + 782 => x"08", + 783 => x"70", + 784 => x"31", + 785 => x"f8", + 786 => x"0c", + 787 => x"52", + 788 => x"80", + 789 => x"f8", + 790 => x"0c", + 791 => x"08", + 792 => x"82", + 793 => x"85", + 794 => x"85", + 795 => x"82", + 796 => x"02", + 797 => x"0c", + 798 => x"82", + 799 => x"88", + 800 => x"85", + 801 => x"05", + 802 => x"f8", + 803 => x"08", + 804 => x"d4", + 805 => x"f8", + 806 => x"08", + 807 => x"85", + 808 => x"05", + 809 => x"f8", + 810 => x"08", + 811 => x"85", + 812 => x"05", + 813 => x"f8", + 814 => x"08", + 815 => x"38", + 816 => x"08", + 817 => x"51", + 818 => x"f8", + 819 => x"08", + 820 => x"71", + 821 => x"f8", + 822 => x"08", + 823 => x"85", + 824 => x"05", + 825 => x"39", + 826 => x"08", + 827 => x"70", + 828 => x"0c", + 829 => x"0d", + 830 => x"0c", + 831 => x"f8", + 832 => x"85", + 833 => x"3d", + 834 => x"82", + 835 => x"fc", + 836 => x"85", + 837 => x"05", + 838 => x"b9", + 839 => x"f8", + 840 => x"08", + 841 => x"f8", + 842 => x"0c", + 843 => x"85", + 844 => x"05", + 845 => x"f8", + 846 => x"08", + 847 => x"0b", + 848 => x"08", + 849 => x"82", + 850 => x"f4", + 851 => x"85", + 852 => x"05", + 853 => x"f8", + 854 => x"08", + 855 => x"38", + 856 => x"08", + 857 => x"30", + 858 => x"08", + 859 => x"80", + 860 => x"f8", + 861 => x"0c", + 862 => x"08", + 863 => x"8a", + 864 => x"82", + 865 => x"f0", + 866 => x"85", + 867 => x"05", + 868 => x"f8", + 869 => x"0c", + 870 => x"85", + 871 => x"05", + 872 => x"85", + 873 => x"05", + 874 => x"c5", + 875 => x"ec", + 876 => x"85", + 877 => x"05", + 878 => x"85", + 879 => x"05", + 880 => x"90", + 881 => x"f8", + 882 => x"08", + 883 => x"f8", + 884 => x"0c", + 885 => x"08", + 886 => x"70", + 887 => x"0c", + 888 => x"0d", + 889 => x"0c", + 890 => x"f8", + 891 => x"85", + 892 => x"3d", + 893 => x"82", + 894 => x"fc", + 895 => x"85", + 896 => x"05", + 897 => x"99", + 898 => x"f8", + 899 => x"08", + 900 => x"f8", + 901 => x"0c", + 902 => x"85", + 903 => x"05", + 904 => x"f8", + 905 => x"08", + 906 => x"38", + 907 => x"08", + 908 => x"30", + 909 => x"08", + 910 => x"81", + 911 => x"f8", + 912 => x"08", + 913 => x"f8", + 914 => x"08", + 915 => x"3f", + 916 => x"08", + 917 => x"f8", + 918 => x"0c", + 919 => x"f8", + 920 => x"08", + 921 => x"38", + 922 => x"08", + 923 => x"30", + 924 => x"08", + 925 => x"82", + 926 => x"f8", + 927 => x"82", + 928 => x"54", + 929 => x"82", + 930 => x"04", + 931 => x"08", + 932 => x"f8", + 933 => x"0d", + 934 => x"85", + 935 => x"05", + 936 => x"f8", + 937 => x"08", + 938 => x"11", + 939 => x"82", + 940 => x"8c", + 941 => x"82", + 942 => x"fc", + 943 => x"82", + 944 => x"fc", + 945 => x"85", + 946 => x"05", + 947 => x"82", + 948 => x"88", + 949 => x"85", + 950 => x"05", + 951 => x"85", + 952 => x"05", + 953 => x"51", + 954 => x"f8", + 955 => x"08", + 956 => x"38", + 957 => x"82", + 958 => x"fc", + 959 => x"82", + 960 => x"51", + 961 => x"82", + 962 => x"04", + 963 => x"08", + 964 => x"f8", + 965 => x"0d", + 966 => x"85", + 967 => x"05", + 968 => x"85", + 969 => x"05", + 970 => x"c5", + 971 => x"ec", + 972 => x"85", + 973 => x"85", + 974 => x"85", + 975 => x"82", + 976 => x"02", + 977 => x"0c", + 978 => x"81", + 979 => x"f8", + 980 => x"08", + 981 => x"f8", + 982 => x"08", + 983 => x"82", + 984 => x"70", + 985 => x"0c", + 986 => x"0d", + 987 => x"0c", + 988 => x"f8", + 989 => x"85", + 990 => x"3d", + 991 => x"82", + 992 => x"fc", + 993 => x"0b", + 994 => x"08", + 995 => x"82", + 996 => x"8c", + 997 => x"85", + 998 => x"05", + 999 => x"38", + 1000 => x"08", + 1001 => x"80", + 1002 => x"80", + 1003 => x"f8", + 1004 => x"08", + 1005 => x"82", + 1006 => x"8c", + 1007 => x"82", + 1008 => x"8c", + 1009 => x"85", + 1010 => x"05", + 1011 => x"85", + 1012 => x"05", + 1013 => x"39", + 1014 => x"08", + 1015 => x"80", + 1016 => x"38", + 1017 => x"08", + 1018 => x"82", + 1019 => x"88", + 1020 => x"ad", + 1021 => x"f8", + 1022 => x"08", + 1023 => x"08", + 1024 => x"31", + 1025 => x"08", + 1026 => x"82", + 1027 => x"f8", + 1028 => x"85", + 1029 => x"05", + 1030 => x"85", + 1031 => x"05", + 1032 => x"f8", + 1033 => x"08", + 1034 => x"85", + 1035 => x"05", + 1036 => x"f8", + 1037 => x"08", + 1038 => x"85", + 1039 => x"05", + 1040 => x"39", + 1041 => x"08", + 1042 => x"80", + 1043 => x"82", + 1044 => x"88", + 1045 => x"82", + 1046 => x"f4", + 1047 => x"91", + 1048 => x"f8", + 1049 => x"08", + 1050 => x"f8", + 1051 => x"0c", + 1052 => x"f8", + 1053 => x"08", + 1054 => x"0c", + 1055 => x"82", + 1056 => x"04", + 1057 => x"79", + 1058 => x"56", + 1059 => x"80", + 1060 => x"38", + 1061 => x"08", + 1062 => x"3f", + 1063 => x"08", + 1064 => x"85", + 1065 => x"80", + 1066 => x"33", + 1067 => x"2e", + 1068 => x"86", + 1069 => x"55", + 1070 => x"57", + 1071 => x"82", + 1072 => x"70", + 1073 => x"f1", + 1074 => x"85", + 1075 => x"74", + 1076 => x"51", + 1077 => x"82", + 1078 => x"8b", + 1079 => x"33", + 1080 => x"2e", + 1081 => x"81", + 1082 => x"ff", + 1083 => x"99", + 1084 => x"38", + 1085 => x"82", + 1086 => x"89", + 1087 => x"ff", + 1088 => x"52", + 1089 => x"81", + 1090 => x"82", + 1091 => x"e8", + 1092 => x"04", + 1093 => x"51", + 1094 => x"81", + 1095 => x"80", + 1096 => x"eb", + 1097 => x"f2", + 1098 => x"a8", + 1099 => x"39", + 1100 => x"51", + 1101 => x"81", + 1102 => x"80", + 1103 => x"eb", + 1104 => x"d6", + 1105 => x"ec", + 1106 => x"39", + 1107 => x"51", + 1108 => x"81", + 1109 => x"80", + 1110 => x"ec", + 1111 => x"39", + 1112 => x"51", + 1113 => x"ec", + 1114 => x"39", + 1115 => x"51", + 1116 => x"ed", + 1117 => x"39", + 1118 => x"51", + 1119 => x"ed", + 1120 => x"39", + 1121 => x"51", + 1122 => x"ee", + 1123 => x"39", + 1124 => x"51", + 1125 => x"ee", + 1126 => x"d1", + 1127 => x"0d", + 1128 => x"0d", + 1129 => x"56", + 1130 => x"26", + 1131 => x"e8", + 1132 => x"f9", + 1133 => x"52", + 1134 => x"08", + 1135 => x"87", + 1136 => x"51", + 1137 => x"82", + 1138 => x"52", + 1139 => x"bc", + 1140 => x"ec", + 1141 => x"53", + 1142 => x"ee", + 1143 => x"fd", + 1144 => x"0d", + 1145 => x"0d", + 1146 => x"05", + 1147 => x"33", + 1148 => x"68", + 1149 => x"05", + 1150 => x"73", + 1151 => x"59", + 1152 => x"77", + 1153 => x"83", + 1154 => x"74", + 1155 => x"81", + 1156 => x"55", + 1157 => x"81", + 1158 => x"53", + 1159 => x"3d", + 1160 => x"81", + 1161 => x"82", + 1162 => x"57", + 1163 => x"08", + 1164 => x"85", + 1165 => x"c0", + 1166 => x"82", + 1167 => x"59", + 1168 => x"05", + 1169 => x"53", + 1170 => x"51", + 1171 => x"3f", + 1172 => x"08", + 1173 => x"ec", + 1174 => x"7a", + 1175 => x"2e", + 1176 => x"19", + 1177 => x"59", + 1178 => x"3d", + 1179 => x"81", + 1180 => x"76", + 1181 => x"70", + 1182 => x"25", + 1183 => x"05", + 1184 => x"72", + 1185 => x"51", + 1186 => x"2e", + 1187 => x"ee", + 1188 => x"c0", + 1189 => x"52", + 1190 => x"85", + 1191 => x"75", + 1192 => x"0c", + 1193 => x"04", + 1194 => x"7b", + 1195 => x"b3", + 1196 => x"58", + 1197 => x"53", + 1198 => x"51", + 1199 => x"82", + 1200 => x"a4", + 1201 => x"2e", + 1202 => x"81", + 1203 => x"98", + 1204 => x"7f", + 1205 => x"ec", + 1206 => x"7d", + 1207 => x"82", + 1208 => x"57", + 1209 => x"04", + 1210 => x"ec", + 1211 => x"0d", + 1212 => x"0d", + 1213 => x"02", + 1214 => x"cf", + 1215 => x"73", + 1216 => x"5f", + 1217 => x"5e", + 1218 => x"81", + 1219 => x"ae", + 1220 => x"ee", + 1221 => x"d5", + 1222 => x"74", + 1223 => x"f4", + 1224 => x"2e", + 1225 => x"a0", + 1226 => x"80", + 1227 => x"18", + 1228 => x"27", + 1229 => x"22", + 1230 => x"f4", + 1231 => x"3f", + 1232 => x"ef", + 1233 => x"a5", + 1234 => x"55", + 1235 => x"18", + 1236 => x"27", + 1237 => x"08", + 1238 => x"e8", + 1239 => x"3f", + 1240 => x"ee", + 1241 => x"85", + 1242 => x"55", + 1243 => x"18", + 1244 => x"27", + 1245 => x"33", + 1246 => x"88", + 1247 => x"3f", + 1248 => x"ef", + 1249 => x"e5", + 1250 => x"55", + 1251 => x"80", + 1252 => x"39", + 1253 => x"51", + 1254 => x"80", + 1255 => x"27", + 1256 => x"18", + 1257 => x"53", + 1258 => x"7a", + 1259 => x"81", + 1260 => x"9f", + 1261 => x"38", + 1262 => x"73", + 1263 => x"ff", + 1264 => x"72", + 1265 => x"38", + 1266 => x"26", + 1267 => x"51", + 1268 => x"51", + 1269 => x"81", + 1270 => x"39", + 1271 => x"51", + 1272 => x"78", + 1273 => x"5c", + 1274 => x"3f", + 1275 => x"08", + 1276 => x"98", + 1277 => x"76", + 1278 => x"81", + 1279 => x"9b", + 1280 => x"85", + 1281 => x"2b", + 1282 => x"70", + 1283 => x"09", + 1284 => x"9b", + 1285 => x"81", + 1286 => x"07", + 1287 => x"06", + 1288 => x"59", + 1289 => x"80", + 1290 => x"38", + 1291 => x"09", + 1292 => x"38", + 1293 => x"39", + 1294 => x"72", + 1295 => x"c9", + 1296 => x"72", + 1297 => x"0c", + 1298 => x"04", + 1299 => x"02", + 1300 => x"81", + 1301 => x"81", + 1302 => x"55", + 1303 => x"82", + 1304 => x"51", + 1305 => x"81", + 1306 => x"81", + 1307 => x"82", + 1308 => x"52", + 1309 => x"51", + 1310 => x"74", + 1311 => x"38", + 1312 => x"86", + 1313 => x"fe", + 1314 => x"c0", + 1315 => x"53", + 1316 => x"81", + 1317 => x"3f", + 1318 => x"51", + 1319 => x"80", + 1320 => x"3f", + 1321 => x"70", + 1322 => x"52", + 1323 => x"92", + 1324 => x"96", + 1325 => x"ef", + 1326 => x"c2", + 1327 => x"96", + 1328 => x"82", + 1329 => x"06", + 1330 => x"80", + 1331 => x"81", + 1332 => x"3f", + 1333 => x"51", + 1334 => x"80", + 1335 => x"3f", + 1336 => x"70", + 1337 => x"52", + 1338 => x"92", + 1339 => x"96", + 1340 => x"f0", + 1341 => x"86", + 1342 => x"96", + 1343 => x"84", + 1344 => x"06", + 1345 => x"80", + 1346 => x"81", + 1347 => x"3f", + 1348 => x"51", + 1349 => x"80", + 1350 => x"3f", + 1351 => x"70", + 1352 => x"52", + 1353 => x"92", + 1354 => x"95", + 1355 => x"f0", + 1356 => x"ca", + 1357 => x"95", + 1358 => x"86", + 1359 => x"06", + 1360 => x"80", + 1361 => x"81", + 1362 => x"3f", + 1363 => x"51", + 1364 => x"80", + 1365 => x"3f", + 1366 => x"70", + 1367 => x"52", + 1368 => x"92", + 1369 => x"95", + 1370 => x"f0", + 1371 => x"8e", + 1372 => x"95", + 1373 => x"88", + 1374 => x"06", + 1375 => x"80", + 1376 => x"81", + 1377 => x"3f", + 1378 => x"51", + 1379 => x"80", + 1380 => x"3f", + 1381 => x"84", + 1382 => x"fb", + 1383 => x"02", + 1384 => x"05", + 1385 => x"56", + 1386 => x"75", + 1387 => x"3f", + 1388 => x"80", + 1389 => x"73", + 1390 => x"53", + 1391 => x"52", + 1392 => x"51", + 1393 => x"3f", + 1394 => x"08", + 1395 => x"70", + 1396 => x"08", + 1397 => x"82", + 1398 => x"51", + 1399 => x"0b", + 1400 => x"34", + 1401 => x"80", + 1402 => x"73", + 1403 => x"81", + 1404 => x"82", + 1405 => x"74", + 1406 => x"81", + 1407 => x"82", + 1408 => x"80", + 1409 => x"82", + 1410 => x"51", + 1411 => x"91", + 1412 => x"cc", + 1413 => x"99", + 1414 => x"0b", + 1415 => x"e8", + 1416 => x"82", + 1417 => x"54", + 1418 => x"09", + 1419 => x"38", + 1420 => x"53", + 1421 => x"51", + 1422 => x"80", + 1423 => x"ec", + 1424 => x"0d", + 1425 => x"0d", + 1426 => x"82", + 1427 => x"5f", + 1428 => x"7c", + 1429 => x"93", + 1430 => x"ec", + 1431 => x"06", + 1432 => x"2e", + 1433 => x"a1", + 1434 => x"d4", + 1435 => x"70", + 1436 => x"ff", + 1437 => x"78", + 1438 => x"f8", + 1439 => x"dd", + 1440 => x"ec", + 1441 => x"88", + 1442 => x"d8", + 1443 => x"39", + 1444 => x"5d", + 1445 => x"51", + 1446 => x"96", + 1447 => x"5a", + 1448 => x"79", + 1449 => x"3f", + 1450 => x"84", + 1451 => x"d4", + 1452 => x"ec", + 1453 => x"70", + 1454 => x"59", + 1455 => x"2e", + 1456 => x"78", + 1457 => x"b2", + 1458 => x"2e", + 1459 => x"78", + 1460 => x"38", + 1461 => x"ff", + 1462 => x"bc", + 1463 => x"38", + 1464 => x"78", + 1465 => x"83", + 1466 => x"80", + 1467 => x"cd", + 1468 => x"2e", + 1469 => x"8a", + 1470 => x"80", + 1471 => x"c3", + 1472 => x"f9", + 1473 => x"78", + 1474 => x"87", + 1475 => x"80", + 1476 => x"8c", + 1477 => x"39", + 1478 => x"2e", + 1479 => x"78", + 1480 => x"8b", + 1481 => x"82", + 1482 => x"38", + 1483 => x"78", + 1484 => x"89", + 1485 => x"e5", + 1486 => x"ff", + 1487 => x"ff", + 1488 => x"a8", + 1489 => x"85", + 1490 => x"2e", + 1491 => x"b4", + 1492 => x"11", + 1493 => x"05", + 1494 => x"3f", + 1495 => x"08", + 1496 => x"b0", + 1497 => x"fe", + 1498 => x"ff", + 1499 => x"a7", + 1500 => x"85", + 1501 => x"38", + 1502 => x"08", + 1503 => x"94", + 1504 => x"3f", + 1505 => x"5a", + 1506 => x"81", + 1507 => x"59", + 1508 => x"84", + 1509 => x"7a", + 1510 => x"38", + 1511 => x"b4", + 1512 => x"11", + 1513 => x"05", + 1514 => x"3f", + 1515 => x"08", + 1516 => x"e0", + 1517 => x"fe", + 1518 => x"ff", + 1519 => x"a7", + 1520 => x"85", + 1521 => x"2e", + 1522 => x"b4", + 1523 => x"11", + 1524 => x"05", + 1525 => x"3f", + 1526 => x"08", + 1527 => x"b4", + 1528 => x"a4", + 1529 => x"3f", + 1530 => x"63", + 1531 => x"38", + 1532 => x"70", + 1533 => x"33", + 1534 => x"81", + 1535 => x"39", + 1536 => x"80", + 1537 => x"84", + 1538 => x"c9", + 1539 => x"ec", + 1540 => x"fc", + 1541 => x"3d", + 1542 => x"53", + 1543 => x"51", + 1544 => x"82", + 1545 => x"80", + 1546 => x"38", + 1547 => x"f8", + 1548 => x"84", + 1549 => x"9d", + 1550 => x"ec", + 1551 => x"fc", + 1552 => x"f2", + 1553 => x"a5", + 1554 => x"79", + 1555 => x"38", + 1556 => x"7b", + 1557 => x"5b", + 1558 => x"91", + 1559 => x"7a", + 1560 => x"53", + 1561 => x"f2", + 1562 => x"f1", + 1563 => x"62", + 1564 => x"5a", + 1565 => x"f2", + 1566 => x"bb", + 1567 => x"ff", + 1568 => x"ff", + 1569 => x"a5", + 1570 => x"85", + 1571 => x"df", + 1572 => x"d8", + 1573 => x"80", + 1574 => x"82", + 1575 => x"44", + 1576 => x"82", + 1577 => x"59", + 1578 => x"88", + 1579 => x"98", + 1580 => x"39", + 1581 => x"33", + 1582 => x"2e", + 1583 => x"84", + 1584 => x"ab", + 1585 => x"db", + 1586 => x"80", + 1587 => x"82", + 1588 => x"44", + 1589 => x"84", + 1590 => x"78", + 1591 => x"38", + 1592 => x"08", + 1593 => x"82", + 1594 => x"fc", + 1595 => x"b4", + 1596 => x"11", + 1597 => x"05", + 1598 => x"3f", + 1599 => x"08", + 1600 => x"82", + 1601 => x"59", + 1602 => x"89", + 1603 => x"94", + 1604 => x"cc", + 1605 => x"d9", + 1606 => x"80", + 1607 => x"82", + 1608 => x"43", + 1609 => x"84", + 1610 => x"78", + 1611 => x"38", + 1612 => x"08", + 1613 => x"82", + 1614 => x"59", + 1615 => x"88", + 1616 => x"ac", + 1617 => x"39", + 1618 => x"33", + 1619 => x"2e", + 1620 => x"84", + 1621 => x"88", + 1622 => x"c0", + 1623 => x"43", + 1624 => x"f8", + 1625 => x"84", + 1626 => x"e9", + 1627 => x"ec", + 1628 => x"a9", + 1629 => x"5c", + 1630 => x"2e", + 1631 => x"5c", + 1632 => x"70", + 1633 => x"70", + 1634 => x"2a", + 1635 => x"51", + 1636 => x"78", + 1637 => x"38", + 1638 => x"83", + 1639 => x"81", + 1640 => x"9b", + 1641 => x"55", + 1642 => x"53", + 1643 => x"51", + 1644 => x"81", + 1645 => x"9b", + 1646 => x"d8", + 1647 => x"ff", + 1648 => x"ff", + 1649 => x"a3", + 1650 => x"85", + 1651 => x"2e", + 1652 => x"b4", + 1653 => x"11", + 1654 => x"05", + 1655 => x"3f", + 1656 => x"08", + 1657 => x"38", + 1658 => x"80", + 1659 => x"79", + 1660 => x"05", + 1661 => x"fe", + 1662 => x"ff", + 1663 => x"a2", + 1664 => x"85", + 1665 => x"38", + 1666 => x"63", + 1667 => x"52", + 1668 => x"51", + 1669 => x"80", + 1670 => x"51", + 1671 => x"79", + 1672 => x"59", + 1673 => x"f8", + 1674 => x"79", + 1675 => x"b4", + 1676 => x"11", + 1677 => x"05", + 1678 => x"3f", + 1679 => x"08", + 1680 => x"38", + 1681 => x"80", + 1682 => x"79", + 1683 => x"05", + 1684 => x"39", + 1685 => x"51", + 1686 => x"ff", + 1687 => x"3d", + 1688 => x"53", + 1689 => x"51", + 1690 => x"82", + 1691 => x"80", + 1692 => x"38", + 1693 => x"f0", + 1694 => x"84", + 1695 => x"d1", + 1696 => x"ec", + 1697 => x"a5", + 1698 => x"02", + 1699 => x"79", + 1700 => x"5b", + 1701 => x"b4", + 1702 => x"11", + 1703 => x"05", + 1704 => x"3f", + 1705 => x"08", + 1706 => x"e8", + 1707 => x"22", + 1708 => x"f3", + 1709 => x"a5", + 1710 => x"52", + 1711 => x"f7", + 1712 => x"79", + 1713 => x"ae", + 1714 => x"38", + 1715 => x"87", + 1716 => x"05", + 1717 => x"b4", + 1718 => x"11", + 1719 => x"05", + 1720 => x"3f", + 1721 => x"08", + 1722 => x"38", + 1723 => x"be", + 1724 => x"70", + 1725 => x"23", + 1726 => x"b1", + 1727 => x"84", + 1728 => x"3f", + 1729 => x"b4", + 1730 => x"11", + 1731 => x"05", + 1732 => x"3f", + 1733 => x"08", + 1734 => x"f8", + 1735 => x"fe", + 1736 => x"ff", + 1737 => x"a2", + 1738 => x"85", + 1739 => x"2e", + 1740 => x"60", + 1741 => x"60", + 1742 => x"b4", + 1743 => x"11", + 1744 => x"05", + 1745 => x"3f", + 1746 => x"08", + 1747 => x"c4", + 1748 => x"08", + 1749 => x"f3", + 1750 => x"81", + 1751 => x"52", + 1752 => x"d3", + 1753 => x"79", + 1754 => x"ae", + 1755 => x"38", + 1756 => x"9b", + 1757 => x"fe", + 1758 => x"ff", + 1759 => x"a1", + 1760 => x"85", + 1761 => x"2e", + 1762 => x"60", + 1763 => x"60", + 1764 => x"ff", + 1765 => x"f3", + 1766 => x"d1", + 1767 => x"39", + 1768 => x"80", + 1769 => x"84", + 1770 => x"a9", + 1771 => x"ec", + 1772 => x"f5", + 1773 => x"52", + 1774 => x"51", + 1775 => x"63", + 1776 => x"b4", + 1777 => x"11", + 1778 => x"05", + 1779 => x"3f", + 1780 => x"08", + 1781 => x"bc", + 1782 => x"81", + 1783 => x"9c", + 1784 => x"59", + 1785 => x"85", + 1786 => x"2e", + 1787 => x"82", + 1788 => x"52", + 1789 => x"51", + 1790 => x"f5", + 1791 => x"f3", + 1792 => x"e9", + 1793 => x"3f", + 1794 => x"81", + 1795 => x"96", + 1796 => x"59", + 1797 => x"90", + 1798 => x"f8", + 1799 => x"79", + 1800 => x"80", + 1801 => x"38", + 1802 => x"59", + 1803 => x"81", + 1804 => x"3d", + 1805 => x"51", + 1806 => x"82", + 1807 => x"5c", + 1808 => x"82", + 1809 => x"7a", + 1810 => x"38", + 1811 => x"8c", + 1812 => x"39", + 1813 => x"ae", + 1814 => x"39", + 1815 => x"56", + 1816 => x"f4", + 1817 => x"53", + 1818 => x"52", + 1819 => x"b0", + 1820 => x"ff", + 1821 => x"81", + 1822 => x"b4", + 1823 => x"05", + 1824 => x"3f", + 1825 => x"55", + 1826 => x"54", + 1827 => x"f4", + 1828 => x"3d", + 1829 => x"51", + 1830 => x"92", + 1831 => x"80", + 1832 => x"cc", + 1833 => x"ff", + 1834 => x"9b", + 1835 => x"84", + 1836 => x"85", + 1837 => x"56", + 1838 => x"54", + 1839 => x"53", + 1840 => x"52", + 1841 => x"b0", + 1842 => x"dc", + 1843 => x"ec", + 1844 => x"ec", + 1845 => x"09", + 1846 => x"72", + 1847 => x"51", + 1848 => x"80", + 1849 => x"26", + 1850 => x"5a", + 1851 => x"59", + 1852 => x"8d", + 1853 => x"70", + 1854 => x"5c", + 1855 => x"c2", + 1856 => x"32", + 1857 => x"07", + 1858 => x"38", + 1859 => x"09", + 1860 => x"80", + 1861 => x"d4", + 1862 => x"3f", + 1863 => x"fc", + 1864 => x"0b", + 1865 => x"34", + 1866 => x"8c", + 1867 => x"55", + 1868 => x"52", + 1869 => x"d4", + 1870 => x"ec", + 1871 => x"75", + 1872 => x"87", + 1873 => x"73", + 1874 => x"3f", + 1875 => x"ec", + 1876 => x"0c", + 1877 => x"9c", + 1878 => x"55", + 1879 => x"52", + 1880 => x"a8", + 1881 => x"ec", + 1882 => x"75", + 1883 => x"87", + 1884 => x"73", + 1885 => x"3f", + 1886 => x"ec", + 1887 => x"0c", + 1888 => x"0b", + 1889 => x"84", + 1890 => x"83", + 1891 => x"94", + 1892 => x"c0", + 1893 => x"9c", + 1894 => x"c3", + 1895 => x"9c", + 1896 => x"98", + 1897 => x"3f", + 1898 => x"51", + 1899 => x"81", + 1900 => x"93", + 1901 => x"85", + 1902 => x"3f", + 1903 => x"8c", + 1904 => x"3f", + 1905 => x"3d", + 1906 => x"83", + 1907 => x"2b", + 1908 => x"3f", + 1909 => x"08", + 1910 => x"72", + 1911 => x"54", + 1912 => x"25", + 1913 => x"82", + 1914 => x"84", + 1915 => x"fc", + 1916 => x"70", + 1917 => x"80", + 1918 => x"72", + 1919 => x"8c", + 1920 => x"51", + 1921 => x"09", + 1922 => x"38", + 1923 => x"f1", + 1924 => x"51", + 1925 => x"09", + 1926 => x"38", + 1927 => x"81", + 1928 => x"73", + 1929 => x"81", + 1930 => x"84", + 1931 => x"52", + 1932 => x"52", + 1933 => x"2e", + 1934 => x"54", + 1935 => x"9d", + 1936 => x"38", + 1937 => x"12", + 1938 => x"33", + 1939 => x"a0", + 1940 => x"81", + 1941 => x"2e", + 1942 => x"ea", + 1943 => x"33", + 1944 => x"a0", + 1945 => x"06", + 1946 => x"54", + 1947 => x"70", + 1948 => x"70", + 1949 => x"07", + 1950 => x"70", + 1951 => x"38", + 1952 => x"81", + 1953 => x"71", + 1954 => x"51", + 1955 => x"ec", + 1956 => x"0d", + 1957 => x"0d", + 1958 => x"08", + 1959 => x"38", + 1960 => x"05", + 1961 => x"9b", + 1962 => x"85", + 1963 => x"38", + 1964 => x"39", + 1965 => x"82", + 1966 => x"86", + 1967 => x"fc", + 1968 => x"82", + 1969 => x"05", + 1970 => x"52", + 1971 => x"81", + 1972 => x"13", + 1973 => x"51", + 1974 => x"9e", + 1975 => x"38", + 1976 => x"51", + 1977 => x"97", + 1978 => x"38", + 1979 => x"51", + 1980 => x"bb", + 1981 => x"38", + 1982 => x"51", + 1983 => x"bb", + 1984 => x"38", + 1985 => x"55", + 1986 => x"87", + 1987 => x"d9", + 1988 => x"22", + 1989 => x"73", + 1990 => x"80", + 1991 => x"0b", + 1992 => x"9c", + 1993 => x"87", + 1994 => x"0c", + 1995 => x"87", + 1996 => x"0c", + 1997 => x"87", + 1998 => x"0c", + 1999 => x"87", + 2000 => x"0c", + 2001 => x"87", + 2002 => x"0c", + 2003 => x"87", + 2004 => x"0c", + 2005 => x"98", + 2006 => x"87", + 2007 => x"0c", + 2008 => x"c0", + 2009 => x"80", + 2010 => x"85", + 2011 => x"3d", + 2012 => x"3d", + 2013 => x"87", + 2014 => x"5d", + 2015 => x"87", + 2016 => x"08", + 2017 => x"23", + 2018 => x"b8", + 2019 => x"82", + 2020 => x"c0", + 2021 => x"5a", + 2022 => x"34", + 2023 => x"b0", + 2024 => x"84", + 2025 => x"c0", + 2026 => x"5a", + 2027 => x"34", + 2028 => x"a8", + 2029 => x"86", + 2030 => x"c0", + 2031 => x"5c", + 2032 => x"23", + 2033 => x"a0", + 2034 => x"8a", + 2035 => x"7d", + 2036 => x"ff", + 2037 => x"7b", + 2038 => x"06", + 2039 => x"33", + 2040 => x"33", + 2041 => x"33", + 2042 => x"33", + 2043 => x"33", + 2044 => x"ff", + 2045 => x"81", + 2046 => x"94", + 2047 => x"3d", + 2048 => x"3d", + 2049 => x"05", + 2050 => x"81", + 2051 => x"2a", + 2052 => x"70", + 2053 => x"34", + 2054 => x"04", + 2055 => x"77", + 2056 => x"33", + 2057 => x"06", + 2058 => x"87", + 2059 => x"51", + 2060 => x"86", + 2061 => x"94", + 2062 => x"08", + 2063 => x"70", + 2064 => x"54", + 2065 => x"2e", + 2066 => x"91", + 2067 => x"06", + 2068 => x"d7", + 2069 => x"32", + 2070 => x"51", + 2071 => x"2e", + 2072 => x"93", + 2073 => x"06", + 2074 => x"ff", + 2075 => x"81", + 2076 => x"87", + 2077 => x"52", + 2078 => x"86", + 2079 => x"94", + 2080 => x"72", + 2081 => x"85", + 2082 => x"3d", + 2083 => x"3d", + 2084 => x"05", + 2085 => x"8c", + 2086 => x"ff", + 2087 => x"56", + 2088 => x"84", + 2089 => x"2e", + 2090 => x"c0", + 2091 => x"70", + 2092 => x"2a", + 2093 => x"53", + 2094 => x"80", + 2095 => x"71", + 2096 => x"81", + 2097 => x"70", + 2098 => x"81", + 2099 => x"06", + 2100 => x"80", + 2101 => x"71", + 2102 => x"81", + 2103 => x"70", + 2104 => x"73", + 2105 => x"51", + 2106 => x"80", + 2107 => x"2e", + 2108 => x"c0", + 2109 => x"75", + 2110 => x"3d", + 2111 => x"3d", + 2112 => x"80", + 2113 => x"81", + 2114 => x"53", + 2115 => x"2e", + 2116 => x"71", + 2117 => x"81", + 2118 => x"8c", + 2119 => x"ff", + 2120 => x"55", + 2121 => x"94", + 2122 => x"80", + 2123 => x"87", + 2124 => x"51", + 2125 => x"96", + 2126 => x"06", + 2127 => x"70", + 2128 => x"38", + 2129 => x"70", + 2130 => x"51", + 2131 => x"72", + 2132 => x"81", + 2133 => x"70", + 2134 => x"38", + 2135 => x"70", + 2136 => x"51", + 2137 => x"38", + 2138 => x"06", + 2139 => x"94", + 2140 => x"80", + 2141 => x"87", + 2142 => x"52", + 2143 => x"81", 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x"0c", + 2203 => x"98", + 2204 => x"9c", + 2205 => x"9e", + 2206 => x"84", + 2207 => x"c0", + 2208 => x"82", + 2209 => x"87", + 2210 => x"08", + 2211 => x"0c", + 2212 => x"b0", + 2213 => x"ac", + 2214 => x"9e", + 2215 => x"84", + 2216 => x"c0", + 2217 => x"82", + 2218 => x"87", + 2219 => x"08", + 2220 => x"0c", + 2221 => x"c0", + 2222 => x"bc", + 2223 => x"9e", + 2224 => x"84", + 2225 => x"c0", + 2226 => x"51", + 2227 => x"c4", + 2228 => x"9e", + 2229 => x"84", + 2230 => x"c0", + 2231 => x"82", + 2232 => x"87", + 2233 => x"08", + 2234 => x"0c", + 2235 => x"84", + 2236 => x"0b", + 2237 => x"90", + 2238 => x"80", + 2239 => x"52", + 2240 => x"2e", + 2241 => x"52", + 2242 => x"d5", + 2243 => x"87", + 2244 => x"08", + 2245 => x"0a", + 2246 => x"52", + 2247 => x"83", + 2248 => x"71", + 2249 => x"34", + 2250 => x"c0", + 2251 => x"70", + 2252 => x"06", + 2253 => x"70", + 2254 => x"38", + 2255 => x"82", + 2256 => x"80", + 2257 => x"9e", + 2258 => x"88", + 2259 => x"51", + 2260 => x"80", + 2261 => x"81", + 2262 => x"84", + 2263 => x"0b", + 2264 => x"90", + 2265 => x"80", + 2266 => x"52", + 2267 => x"2e", + 2268 => x"52", + 2269 => x"d9", + 2270 => x"87", + 2271 => x"08", + 2272 => x"80", + 2273 => x"52", + 2274 => x"83", + 2275 => x"71", + 2276 => x"34", + 2277 => x"c0", + 2278 => x"70", + 2279 => x"06", + 2280 => x"70", + 2281 => x"38", + 2282 => x"82", + 2283 => x"80", + 2284 => x"9e", + 2285 => x"82", + 2286 => x"51", + 2287 => x"80", + 2288 => x"81", + 2289 => x"84", + 2290 => x"0b", + 2291 => x"90", + 2292 => x"80", + 2293 => x"52", + 2294 => x"2e", + 2295 => x"52", + 2296 => x"dd", + 2297 => x"87", + 2298 => x"08", + 2299 => x"80", + 2300 => x"52", + 2301 => x"83", + 2302 => x"71", + 2303 => x"34", + 2304 => x"c0", + 2305 => x"70", + 2306 => x"51", + 2307 => x"80", + 2308 => x"81", + 2309 => x"84", + 2310 => x"c0", + 2311 => x"70", + 2312 => x"70", + 2313 => x"51", + 2314 => x"84", + 2315 => x"0b", + 2316 => x"90", + 2317 => x"80", + 2318 => x"52", + 2319 => x"83", + 2320 => x"71", + 2321 => x"34", + 2322 => x"90", + 2323 => x"f0", + 2324 => x"2a", + 2325 => x"70", + 2326 => x"34", + 2327 => x"c0", + 2328 => x"70", + 2329 => x"52", + 2330 => x"2e", + 2331 => x"52", + 2332 => x"e3", + 2333 => x"9e", + 2334 => x"87", + 2335 => x"70", + 2336 => x"34", + 2337 => x"04", + 2338 => x"81", + 2339 => x"85", + 2340 => x"84", + 2341 => x"73", + 2342 => x"38", + 2343 => x"51", + 2344 => x"81", + 2345 => x"85", + 2346 => x"84", + 2347 => x"73", + 2348 => x"38", + 2349 => x"08", + 2350 => x"08", + 2351 => x"81", + 2352 => x"8b", + 2353 => x"84", + 2354 => x"73", + 2355 => x"38", + 2356 => x"08", + 2357 => x"08", + 2358 => x"81", + 2359 => x"8a", + 2360 => x"84", + 2361 => x"73", + 2362 => x"38", + 2363 => x"08", + 2364 => x"08", + 2365 => x"81", + 2366 => x"8a", + 2367 => x"84", + 2368 => x"73", + 2369 => x"38", + 2370 => x"08", + 2371 => x"08", + 2372 => x"81", + 2373 => x"8a", + 2374 => x"84", + 2375 => x"73", + 2376 => x"38", + 2377 => x"08", + 2378 => x"08", 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x"f4", + 2438 => x"ec", + 2439 => x"84", + 2440 => x"85", + 2441 => x"d0", + 2442 => x"82", + 2443 => x"31", + 2444 => x"81", + 2445 => x"88", + 2446 => x"84", + 2447 => x"73", + 2448 => x"38", + 2449 => x"08", + 2450 => x"c0", + 2451 => x"d1", + 2452 => x"85", + 2453 => x"bd", + 2454 => x"82", + 2455 => x"51", + 2456 => x"74", + 2457 => x"08", + 2458 => x"52", + 2459 => x"51", + 2460 => x"82", + 2461 => x"54", + 2462 => x"b0", + 2463 => x"d0", + 2464 => x"84", + 2465 => x"51", + 2466 => x"82", + 2467 => x"54", + 2468 => x"52", + 2469 => x"08", + 2470 => x"3f", + 2471 => x"ec", + 2472 => x"73", + 2473 => x"9c", + 2474 => x"3f", + 2475 => x"51", + 2476 => x"86", + 2477 => x"fe", + 2478 => x"92", + 2479 => x"05", + 2480 => x"26", + 2481 => x"82", + 2482 => x"e8", + 2483 => x"04", + 2484 => x"51", + 2485 => x"fa", + 2486 => x"39", + 2487 => x"51", + 2488 => x"fa", + 2489 => x"39", + 2490 => x"51", + 2491 => x"fa", + 2492 => x"f9", + 2493 => x"0d", + 2494 => x"80", + 2495 => x"0b", + 2496 => x"84", + 2497 => x"84", + 2498 => x"c0", + 2499 => x"04", + 2500 => x"02", + 2501 => x"53", + 2502 => x"09", + 2503 => x"38", + 2504 => x"3f", + 2505 => x"08", + 2506 => x"2e", + 2507 => x"72", + 2508 => x"fc", + 2509 => x"82", + 2510 => x"8f", + 2511 => x"f4", + 2512 => x"80", + 2513 => x"72", + 2514 => x"84", + 2515 => x"fe", + 2516 => x"97", + 2517 => x"9c", + 2518 => x"82", + 2519 => x"54", + 2520 => x"3f", + 2521 => x"f4", + 2522 => x"0d", + 2523 => x"0d", + 2524 => x"33", + 2525 => x"06", + 2526 => x"80", + 2527 => x"72", + 2528 => x"51", + 2529 => x"ff", + 2530 => x"39", + 2531 => x"04", + 2532 => x"77", + 2533 => x"08", + 2534 => x"f4", + 2535 => x"73", + 2536 => x"ff", + 2537 => x"71", + 2538 => x"38", + 2539 => x"06", + 2540 => x"54", + 2541 => x"e7", + 2542 => x"9c", + 2543 => x"3d", + 2544 => x"3d", + 2545 => x"59", + 2546 => x"81", + 2547 => x"56", + 2548 => x"85", + 2549 => x"a5", + 2550 => x"06", + 2551 => x"80", + 2552 => x"81", + 2553 => x"58", + 2554 => x"b0", + 2555 => x"06", + 2556 => x"5a", + 2557 => x"ad", + 2558 => x"06", + 2559 => x"5a", + 2560 => x"05", + 2561 => x"75", + 2562 => x"81", + 2563 => x"77", + 2564 => x"08", + 2565 => x"05", + 2566 => x"5d", + 2567 => x"39", + 2568 => x"72", + 2569 => x"38", + 2570 => x"7b", + 2571 => x"18", + 2572 => x"70", + 2573 => x"33", + 2574 => x"53", + 2575 => x"80", + 2576 => x"09", + 2577 => x"72", + 2578 => x"78", + 2579 => x"70", + 2580 => x"70", + 2581 => x"25", + 2582 => x"54", + 2583 => x"53", + 2584 => x"8c", + 2585 => x"07", + 2586 => x"05", + 2587 => x"5a", + 2588 => x"83", + 2589 => x"54", + 2590 => x"27", + 2591 => x"16", + 2592 => x"06", + 2593 => x"80", + 2594 => x"aa", + 2595 => x"cf", + 2596 => x"73", + 2597 => x"81", + 2598 => x"80", + 2599 => x"38", + 2600 => x"2e", + 2601 => x"81", + 2602 => x"80", + 2603 => x"8a", + 2604 => x"39", + 2605 => x"2e", + 2606 => x"73", + 2607 => x"8a", + 2608 => x"d3", + 2609 => x"80", + 2610 => x"80", + 2611 => x"ee", + 2612 => x"39", + 2613 => x"71", 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x"72", + 2673 => x"05", + 2674 => x"17", + 2675 => x"05", + 2676 => x"9f", + 2677 => x"57", + 2678 => x"85", + 2679 => x"af", + 2680 => x"2a", + 2681 => x"51", + 2682 => x"2e", + 2683 => x"3d", + 2684 => x"05", + 2685 => x"34", + 2686 => x"76", + 2687 => x"54", + 2688 => x"72", + 2689 => x"54", + 2690 => x"70", + 2691 => x"56", + 2692 => x"81", + 2693 => x"7b", + 2694 => x"73", + 2695 => x"3f", + 2696 => x"53", + 2697 => x"74", + 2698 => x"53", + 2699 => x"eb", + 2700 => x"77", + 2701 => x"53", + 2702 => x"14", + 2703 => x"54", + 2704 => x"3f", + 2705 => x"74", + 2706 => x"53", + 2707 => x"fa", + 2708 => x"51", + 2709 => x"ef", + 2710 => x"0d", + 2711 => x"0d", + 2712 => x"70", + 2713 => x"08", + 2714 => x"51", + 2715 => x"85", + 2716 => x"fe", + 2717 => x"82", + 2718 => x"85", + 2719 => x"52", + 2720 => x"be", + 2721 => x"fc", + 2722 => x"73", + 2723 => x"82", + 2724 => x"84", + 2725 => x"fd", + 2726 => x"9c", + 2727 => x"82", + 2728 => x"87", + 2729 => x"53", + 2730 => x"fa", + 2731 => x"82", + 2732 => x"85", + 2733 => x"fb", + 2734 => x"79", + 2735 => x"08", + 2736 => x"57", + 2737 => x"71", + 2738 => x"e3", + 2739 => x"f8", + 2740 => x"2d", + 2741 => x"08", + 2742 => x"53", + 2743 => x"80", + 2744 => x"8d", + 2745 => x"72", + 2746 => x"09", + 2747 => x"80", + 2748 => x"52", + 2749 => x"8b", + 2750 => x"2e", + 2751 => x"14", + 2752 => x"9f", + 2753 => x"38", + 2754 => x"73", + 2755 => x"bd", + 2756 => x"52", + 2757 => x"81", + 2758 => x"51", + 2759 => x"ff", + 2760 => x"15", + 2761 => x"34", + 2762 => x"e4", + 2763 => x"72", + 2764 => x"0c", + 2765 => x"04", + 2766 => x"82", + 2767 => x"75", + 2768 => x"0c", + 2769 => x"52", + 2770 => x"3f", + 2771 => x"f8", + 2772 => x"0d", + 2773 => x"0d", + 2774 => x"56", + 2775 => x"0c", + 2776 => x"70", + 2777 => x"73", + 2778 => x"81", + 2779 => x"81", + 2780 => x"ed", + 2781 => x"2e", + 2782 => x"8e", + 2783 => x"08", + 2784 => x"76", + 2785 => x"56", + 2786 => x"b0", + 2787 => x"06", + 2788 => x"75", + 2789 => x"76", + 2790 => x"70", + 2791 => x"73", + 2792 => x"8b", + 2793 => x"73", + 2794 => x"85", + 2795 => x"82", + 2796 => x"76", + 2797 => x"70", + 2798 => x"ac", + 2799 => x"a0", + 2800 => x"84", + 2801 => x"53", + 2802 => x"57", + 2803 => x"98", + 2804 => x"39", + 2805 => x"80", + 2806 => x"26", + 2807 => x"86", + 2808 => x"80", + 2809 => x"57", + 2810 => x"74", + 2811 => x"38", + 2812 => x"27", + 2813 => x"14", + 2814 => x"06", + 2815 => x"14", + 2816 => x"06", + 2817 => x"74", + 2818 => x"f9", + 2819 => x"ff", + 2820 => x"89", + 2821 => x"38", + 2822 => x"c5", + 2823 => x"74", + 2824 => x"3f", + 2825 => x"08", + 2826 => x"81", + 2827 => x"76", + 2828 => x"56", + 2829 => x"b2", + 2830 => x"2e", + 2831 => x"09", + 2832 => x"74", + 2833 => x"55", + 2834 => x"ec", + 2835 => x"0d", + 2836 => x"0d", + 2837 => x"56", + 2838 => x"0c", + 2839 => x"70", + 2840 => x"73", + 2841 => x"81", + 2842 => x"81", + 2843 => x"ed", + 2844 => x"2e", + 2845 => x"8e", + 2846 => x"08", + 2847 => x"76", + 2848 => x"56", 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x"55", + 2908 => x"25", + 2909 => x"81", + 2910 => x"08", + 2911 => x"05", + 2912 => x"71", + 2913 => x"53", + 2914 => x"2e", + 2915 => x"83", + 2916 => x"73", + 2917 => x"85", + 2918 => x"3d", + 2919 => x"3d", + 2920 => x"84", + 2921 => x"33", + 2922 => x"55", + 2923 => x"2e", + 2924 => x"51", + 2925 => x"a0", + 2926 => x"3f", + 2927 => x"d0", + 2928 => x"ff", + 2929 => x"73", + 2930 => x"ff", + 2931 => x"39", + 2932 => x"99", + 2933 => x"34", + 2934 => x"04", + 2935 => x"7c", + 2936 => x"b7", + 2937 => x"88", + 2938 => x"33", + 2939 => x"33", + 2940 => x"82", + 2941 => x"08", + 2942 => x"5a", + 2943 => x"80", + 2944 => x"74", + 2945 => x"3f", + 2946 => x"33", + 2947 => x"82", + 2948 => x"81", + 2949 => x"59", + 2950 => x"9d", + 2951 => x"85", + 2952 => x"0c", + 2953 => x"33", + 2954 => x"82", + 2955 => x"08", + 2956 => x"74", + 2957 => x"38", + 2958 => x"52", + 2959 => x"b8", + 2960 => x"85", + 2961 => x"05", + 2962 => x"85", + 2963 => x"81", + 2964 => x"93", + 2965 => x"38", + 2966 => x"85", + 2967 => x"80", + 2968 => x"82", + 2969 => x"56", + 2970 => x"ac", + 2971 => x"bc", + 2972 => x"a4", + 2973 => x"fc", + 2974 => x"53", + 2975 => x"51", + 2976 => x"3f", + 2977 => x"08", + 2978 => x"81", + 2979 => x"82", + 2980 => x"51", + 2981 => x"3f", + 2982 => x"04", + 2983 => x"82", + 2984 => x"93", + 2985 => x"52", + 2986 => x"89", + 2987 => x"98", + 2988 => x"73", + 2989 => x"84", + 2990 => x"73", + 2991 => x"38", + 2992 => x"85", + 2993 => x"85", + 2994 => x"71", + 2995 => x"38", + 2996 => x"d9", + 2997 => x"85", + 2998 => x"98", + 2999 => x"0b", + 3000 => x"0c", + 3001 => x"04", + 3002 => x"81", + 3003 => x"82", + 3004 => x"51", + 3005 => x"3f", + 3006 => x"08", + 3007 => x"82", + 3008 => x"53", + 3009 => x"88", + 3010 => x"56", + 3011 => x"3f", + 3012 => x"08", + 3013 => x"38", + 3014 => x"b5", + 3015 => x"85", + 3016 => x"80", + 3017 => x"ec", + 3018 => x"38", + 3019 => x"08", + 3020 => x"17", + 3021 => x"74", + 3022 => x"76", + 3023 => x"81", + 3024 => x"57", + 3025 => x"74", + 3026 => x"81", + 3027 => x"38", + 3028 => x"04", + 3029 => x"aa", + 3030 => x"3d", + 3031 => x"81", + 3032 => x"80", + 3033 => x"c0", + 3034 => x"dd", + 3035 => x"85", + 3036 => x"96", + 3037 => x"82", + 3038 => x"54", + 3039 => x"52", + 3040 => x"52", + 3041 => x"ba", + 3042 => x"ec", + 3043 => x"a5", + 3044 => x"ff", + 3045 => x"82", + 3046 => x"81", + 3047 => x"80", + 3048 => x"ec", + 3049 => x"38", + 3050 => x"08", + 3051 => x"17", + 3052 => x"74", + 3053 => x"70", + 3054 => x"70", + 3055 => x"2a", + 3056 => x"78", + 3057 => x"38", + 3058 => x"38", + 3059 => x"08", + 3060 => x"53", + 3061 => x"e7", + 3062 => x"ec", + 3063 => x"88", + 3064 => x"f4", + 3065 => x"3f", + 3066 => x"09", + 3067 => x"38", + 3068 => x"51", + 3069 => x"3f", + 3070 => x"b3", + 3071 => x"3d", + 3072 => x"85", + 3073 => x"34", + 3074 => x"82", + 3075 => x"a9", + 3076 => x"f6", + 3077 => x"7e", + 3078 => x"72", + 3079 => x"5a", + 3080 => x"2e", + 3081 => x"a2", + 3082 => x"78", + 3083 => x"76", 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x"ec", + 3143 => x"81", + 3144 => x"53", + 3145 => x"85", + 3146 => x"80", + 3147 => x"82", + 3148 => x"80", + 3149 => x"81", + 3150 => x"f2", + 3151 => x"f7", + 3152 => x"ec", + 3153 => x"85", + 3154 => x"80", + 3155 => x"3d", + 3156 => x"81", + 3157 => x"82", + 3158 => x"56", + 3159 => x"08", + 3160 => x"81", + 3161 => x"38", + 3162 => x"08", + 3163 => x"cb", + 3164 => x"ec", + 3165 => x"0b", + 3166 => x"08", + 3167 => x"82", + 3168 => x"ff", + 3169 => x"55", + 3170 => x"34", + 3171 => x"81", + 3172 => x"75", + 3173 => x"3f", + 3174 => x"81", + 3175 => x"54", + 3176 => x"83", + 3177 => x"74", + 3178 => x"81", + 3179 => x"38", + 3180 => x"82", + 3181 => x"76", + 3182 => x"85", + 3183 => x"2e", + 3184 => x"d8", + 3185 => x"5d", + 3186 => x"82", + 3187 => x"98", + 3188 => x"2c", + 3189 => x"ff", + 3190 => x"78", + 3191 => x"82", + 3192 => x"70", + 3193 => x"98", + 3194 => x"80", + 3195 => x"2b", + 3196 => x"71", + 3197 => x"70", + 3198 => x"fa", + 3199 => x"15", + 3200 => x"51", + 3201 => x"59", + 3202 => x"58", + 3203 => x"78", + 3204 => x"38", + 3205 => x"b1", + 3206 => x"70", + 3207 => x"98", + 3208 => x"54", + 3209 => x"80", + 3210 => x"53", + 3211 => x"51", + 3212 => x"82", + 3213 => x"81", + 3214 => x"73", + 3215 => x"38", + 3216 => x"80", + 3217 => x"ae", + 3218 => x"70", + 3219 => x"98", + 3220 => x"ff", + 3221 => x"56", + 3222 => x"26", + 3223 => x"53", + 3224 => x"51", + 3225 => x"82", + 3226 => x"81", + 3227 => x"73", + 3228 => x"39", + 3229 => x"80", + 3230 => x"38", + 3231 => x"73", + 3232 => x"34", + 3233 => x"70", + 3234 => x"9d", + 3235 => x"98", + 3236 => x"2c", + 3237 => x"11", + 3238 => x"fa", + 3239 => x"5e", + 3240 => x"58", + 3241 => x"73", + 3242 => x"81", + 3243 => x"38", + 3244 => x"15", + 3245 => x"80", + 3246 => x"84", + 3247 => x"82", + 3248 => x"92", + 3249 => x"9d", + 3250 => x"82", + 3251 => x"78", + 3252 => x"75", + 3253 => x"54", + 3254 => x"fd", + 3255 => x"82", + 3256 => x"e8", + 3257 => x"04", + 3258 => x"33", + 3259 => x"2e", + 3260 => x"82", + 3261 => x"54", + 3262 => x"ab", + 3263 => x"2b", + 3264 => x"51", + 3265 => x"24", + 3266 => x"1a", + 3267 => x"81", + 3268 => x"15", + 3269 => x"70", + 3270 => x"9d", + 3271 => x"51", + 3272 => x"74", + 3273 => x"82", + 3274 => x"81", + 3275 => x"74", + 3276 => x"34", + 3277 => x"ae", + 3278 => x"34", + 3279 => x"33", + 3280 => x"25", + 3281 => x"14", + 3282 => x"9d", + 3283 => x"9d", + 3284 => x"05", + 3285 => x"70", + 3286 => x"9d", + 3287 => x"51", + 3288 => x"76", + 3289 => x"74", + 3290 => x"52", + 3291 => x"3f", + 3292 => x"98", + 3293 => x"2c", + 3294 => x"33", + 3295 => x"54", + 3296 => x"e3", + 3297 => x"8c", + 3298 => x"2b", + 3299 => x"82", + 3300 => x"59", + 3301 => x"74", + 3302 => x"a9", + 3303 => x"e6", + 3304 => x"15", + 3305 => x"70", + 3306 => x"9d", + 3307 => x"51", + 3308 => x"75", + 3309 => x"fc", + 3310 => x"7a", + 3311 => x"81", + 3312 => x"9d", + 3313 => x"52", + 3314 => x"51", + 3315 => x"81", + 3316 => x"9d", + 3317 => x"81", + 3318 => x"55", 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x"f9", + 3378 => x"51", + 3379 => x"82", + 3380 => x"ff", + 3381 => x"82", + 3382 => x"73", + 3383 => x"54", + 3384 => x"9d", + 3385 => x"9d", + 3386 => x"55", + 3387 => x"f9", + 3388 => x"14", + 3389 => x"9d", + 3390 => x"98", + 3391 => x"2c", + 3392 => x"06", + 3393 => x"74", + 3394 => x"38", + 3395 => x"81", + 3396 => x"34", + 3397 => x"e3", + 3398 => x"15", + 3399 => x"70", + 3400 => x"9d", + 3401 => x"51", + 3402 => x"75", + 3403 => x"a0", + 3404 => x"3f", + 3405 => x"33", + 3406 => x"70", + 3407 => x"9d", + 3408 => x"51", + 3409 => x"74", + 3410 => x"38", + 3411 => x"c0", + 3412 => x"70", + 3413 => x"98", + 3414 => x"88", + 3415 => x"56", + 3416 => x"25", + 3417 => x"dd", + 3418 => x"8c", + 3419 => x"ff", + 3420 => x"88", + 3421 => x"54", + 3422 => x"f8", + 3423 => x"14", + 3424 => x"9d", + 3425 => x"1a", + 3426 => x"54", + 3427 => x"82", + 3428 => x"70", + 3429 => x"82", + 3430 => x"58", + 3431 => x"75", + 3432 => x"f8", + 3433 => x"9d", + 3434 => x"52", + 3435 => x"51", + 3436 => x"80", + 3437 => x"8c", + 3438 => x"82", + 3439 => x"f8", + 3440 => x"b0", + 3441 => x"b8", + 3442 => x"80", + 3443 => x"74", + 3444 => x"e7", + 3445 => x"ec", + 3446 => x"88", + 3447 => x"ec", + 3448 => x"06", + 3449 => x"74", + 3450 => x"ff", + 3451 => x"93", + 3452 => x"39", + 3453 => x"82", + 3454 => x"fc", + 3455 => x"51", + 3456 => x"2e", + 3457 => x"51", + 3458 => x"3f", + 3459 => x"08", + 3460 => x"34", + 3461 => x"08", + 3462 => x"81", + 3463 => x"52", + 3464 => x"a8", + 3465 => x"1b", + 3466 => x"39", + 3467 => x"74", + 3468 => x"91", + 3469 => x"ff", + 3470 => x"99", + 3471 => x"2e", + 3472 => x"ae", + 3473 => x"ec", + 3474 => x"80", + 3475 => x"74", + 3476 => x"e7", + 3477 => x"ec", + 3478 => x"88", + 3479 => x"ec", + 3480 => x"06", + 3481 => x"74", + 3482 => x"ff", + 3483 => x"80", + 3484 => x"82", + 3485 => x"f0", + 3486 => x"54", + 3487 => x"ab", + 3488 => x"ff", + 3489 => x"82", + 3490 => x"82", + 3491 => x"82", + 3492 => x"81", + 3493 => x"05", + 3494 => x"79", + 3495 => x"fb", + 3496 => x"54", + 3497 => x"06", + 3498 => x"74", + 3499 => x"34", + 3500 => x"82", + 3501 => x"82", + 3502 => x"52", + 3503 => x"de", + 3504 => x"39", + 3505 => x"33", + 3506 => x"06", + 3507 => x"33", + 3508 => x"74", + 3509 => x"ed", + 3510 => x"54", + 3511 => x"8c", + 3512 => x"70", + 3513 => x"e0", + 3514 => x"d9", + 3515 => x"8c", + 3516 => x"80", + 3517 => x"38", + 3518 => x"94", + 3519 => x"8c", + 3520 => x"54", + 3521 => x"8c", + 3522 => x"39", + 3523 => x"83", + 3524 => x"82", + 3525 => x"82", + 3526 => x"85", + 3527 => x"80", + 3528 => x"83", + 3529 => x"ff", + 3530 => x"82", + 3531 => x"54", + 3532 => x"74", + 3533 => x"76", + 3534 => x"82", + 3535 => x"54", + 3536 => x"34", + 3537 => x"34", + 3538 => x"08", + 3539 => x"15", + 3540 => x"15", + 3541 => x"e4", + 3542 => x"e0", + 3543 => x"fe", + 3544 => x"70", + 3545 => x"06", + 3546 => x"58", + 3547 => x"74", + 3548 => x"73", + 3549 => x"82", + 3550 => x"70", + 3551 => x"85", + 3552 => x"f8", + 3553 => x"55", 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x"07", + 3613 => x"52", + 3614 => x"05", + 3615 => x"85", + 3616 => x"88", + 3617 => x"88", + 3618 => x"56", + 3619 => x"13", + 3620 => x"13", + 3621 => x"e4", + 3622 => x"84", + 3623 => x"12", + 3624 => x"2b", + 3625 => x"07", + 3626 => x"52", + 3627 => x"12", + 3628 => x"33", + 3629 => x"07", + 3630 => x"54", + 3631 => x"70", + 3632 => x"73", + 3633 => x"82", + 3634 => x"13", + 3635 => x"12", + 3636 => x"2b", + 3637 => x"ff", + 3638 => x"88", + 3639 => x"53", + 3640 => x"73", + 3641 => x"14", + 3642 => x"0d", + 3643 => x"0d", + 3644 => x"22", + 3645 => x"08", + 3646 => x"71", + 3647 => x"81", + 3648 => x"88", + 3649 => x"83", + 3650 => x"5b", + 3651 => x"05", + 3652 => x"12", + 3653 => x"2b", + 3654 => x"07", + 3655 => x"53", + 3656 => x"25", + 3657 => x"73", + 3658 => x"3f", + 3659 => x"08", + 3660 => x"33", + 3661 => x"71", + 3662 => x"83", + 3663 => x"11", + 3664 => x"12", + 3665 => x"2b", + 3666 => x"2b", + 3667 => x"06", + 3668 => x"51", + 3669 => x"53", + 3670 => x"88", + 3671 => x"72", + 3672 => x"74", + 3673 => x"82", + 3674 => x"70", + 3675 => x"81", + 3676 => x"8b", + 3677 => x"2b", + 3678 => x"57", + 3679 => x"70", + 3680 => x"33", + 3681 => x"07", + 3682 => x"ff", + 3683 => x"2a", + 3684 => x"58", + 3685 => x"34", + 3686 => x"34", + 3687 => x"04", + 3688 => x"82", + 3689 => x"02", + 3690 => x"05", + 3691 => x"2b", + 3692 => x"11", + 3693 => x"33", + 3694 => x"71", + 3695 => x"59", + 3696 => x"56", + 3697 => x"71", + 3698 => x"33", + 3699 => x"07", + 3700 => x"a2", + 3701 => x"07", + 3702 => x"53", + 3703 => x"53", + 3704 => x"70", + 3705 => x"82", + 3706 => x"70", + 3707 => x"81", + 3708 => x"8b", + 3709 => x"2b", + 3710 => x"57", + 3711 => x"82", + 3712 => x"13", + 3713 => x"2b", + 3714 => x"2a", + 3715 => x"52", + 3716 => x"34", + 3717 => x"34", + 3718 => x"08", + 3719 => x"33", + 3720 => x"71", + 3721 => x"82", + 3722 => x"52", + 3723 => x"0d", + 3724 => x"0d", + 3725 => x"e4", + 3726 => x"2a", + 3727 => x"ff", + 3728 => x"57", + 3729 => x"3f", + 3730 => x"08", + 3731 => x"71", + 3732 => x"33", + 3733 => x"71", + 3734 => x"83", + 3735 => x"11", + 3736 => x"12", + 3737 => x"2b", + 3738 => x"07", + 3739 => x"51", + 3740 => x"55", + 3741 => x"80", + 3742 => x"82", + 3743 => x"75", + 3744 => x"3f", + 3745 => x"84", + 3746 => x"15", + 3747 => x"2b", + 3748 => x"07", + 3749 => x"88", + 3750 => x"55", + 3751 => x"86", + 3752 => x"81", + 3753 => x"75", + 3754 => x"82", + 3755 => x"70", + 3756 => x"33", + 3757 => x"71", + 3758 => x"70", + 3759 => x"57", + 3760 => x"72", + 3761 => x"73", + 3762 => x"82", + 3763 => x"18", + 3764 => x"86", + 3765 => x"0b", + 3766 => x"82", + 3767 => x"53", + 3768 => x"34", + 3769 => x"34", + 3770 => x"08", + 3771 => x"81", + 3772 => x"88", + 3773 => x"82", + 3774 => x"70", + 3775 => x"51", + 3776 => x"74", + 3777 => x"81", + 3778 => x"3d", + 3779 => x"3d", + 3780 => x"82", + 3781 => x"84", + 3782 => x"3f", + 3783 => x"86", + 3784 => x"fe", + 3785 => x"3d", + 3786 => x"3d", + 3787 => x"52", + 3788 => x"3f", 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x"76", + 3848 => x"57", + 3849 => x"34", + 3850 => x"08", + 3851 => x"71", + 3852 => x"86", + 3853 => x"12", + 3854 => x"2b", + 3855 => x"2a", + 3856 => x"53", + 3857 => x"73", + 3858 => x"75", + 3859 => x"82", + 3860 => x"70", + 3861 => x"33", + 3862 => x"71", + 3863 => x"83", + 3864 => x"5d", + 3865 => x"05", + 3866 => x"15", + 3867 => x"15", + 3868 => x"e4", + 3869 => x"71", + 3870 => x"33", + 3871 => x"71", + 3872 => x"70", + 3873 => x"5a", + 3874 => x"54", + 3875 => x"34", + 3876 => x"34", + 3877 => x"08", + 3878 => x"54", + 3879 => x"ec", + 3880 => x"0d", + 3881 => x"0d", + 3882 => x"85", + 3883 => x"38", + 3884 => x"71", + 3885 => x"2e", + 3886 => x"51", + 3887 => x"82", + 3888 => x"53", + 3889 => x"ec", + 3890 => x"0d", + 3891 => x"0d", + 3892 => x"33", + 3893 => x"70", + 3894 => x"38", + 3895 => x"11", + 3896 => x"82", + 3897 => x"83", + 3898 => x"fc", + 3899 => x"9b", + 3900 => x"84", + 3901 => x"33", + 3902 => x"51", + 3903 => x"80", + 3904 => x"84", + 3905 => x"92", + 3906 => x"51", + 3907 => x"80", + 3908 => x"81", + 3909 => x"72", + 3910 => x"92", + 3911 => x"81", + 3912 => x"0b", + 3913 => x"8c", + 3914 => x"71", + 3915 => x"06", + 3916 => x"80", + 3917 => x"87", + 3918 => x"08", + 3919 => x"38", + 3920 => x"80", + 3921 => x"71", + 3922 => x"c0", + 3923 => x"51", + 3924 => x"87", + 3925 => x"85", + 3926 => x"82", + 3927 => x"33", + 3928 => x"85", + 3929 => x"3d", + 3930 => x"3d", + 3931 => x"64", + 3932 => x"bf", + 3933 => x"40", + 3934 => x"74", + 3935 => x"cd", + 3936 => x"ec", + 3937 => x"7a", + 3938 => x"81", + 3939 => x"72", + 3940 => x"87", + 3941 => x"11", + 3942 => x"8c", + 3943 => x"92", + 3944 => x"5a", + 3945 => x"58", + 3946 => x"c0", + 3947 => x"76", + 3948 => x"76", + 3949 => x"70", + 3950 => x"81", + 3951 => x"54", + 3952 => x"8e", + 3953 => x"52", + 3954 => x"81", + 3955 => x"81", + 3956 => x"74", + 3957 => x"53", + 3958 => x"83", + 3959 => x"78", + 3960 => x"8f", + 3961 => x"2e", + 3962 => x"c0", + 3963 => x"52", + 3964 => x"87", + 3965 => x"08", + 3966 => x"2e", + 3967 => x"84", + 3968 => x"38", + 3969 => x"87", + 3970 => x"15", + 3971 => x"70", + 3972 => x"52", + 3973 => x"ff", + 3974 => x"39", + 3975 => x"81", + 3976 => x"ff", + 3977 => x"57", + 3978 => x"90", + 3979 => x"80", + 3980 => x"71", + 3981 => x"78", + 3982 => x"38", + 3983 => x"80", + 3984 => x"80", + 3985 => x"81", + 3986 => x"72", + 3987 => x"0c", + 3988 => x"04", + 3989 => x"60", + 3990 => x"8c", + 3991 => x"33", + 3992 => x"5b", + 3993 => x"74", + 3994 => x"e1", + 3995 => x"ec", + 3996 => x"79", + 3997 => x"78", + 3998 => x"06", + 3999 => x"77", + 4000 => x"87", + 4001 => x"11", + 4002 => x"8c", + 4003 => x"92", + 4004 => x"59", + 4005 => x"85", + 4006 => x"98", + 4007 => x"7d", + 4008 => x"0c", + 4009 => x"08", + 4010 => x"70", + 4011 => x"53", + 4012 => x"2e", + 4013 => x"70", + 4014 => x"33", + 4015 => x"18", + 4016 => x"2a", + 4017 => x"51", + 4018 => x"2e", + 4019 => x"c0", + 4020 => x"52", + 4021 => x"87", + 4022 => x"08", + 4023 => x"2e", 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x"0c", + 4083 => x"80", + 4084 => x"56", + 4085 => x"56", + 4086 => x"82", + 4087 => x"88", + 4088 => x"fe", + 4089 => x"81", + 4090 => x"33", + 4091 => x"07", + 4092 => x"0c", + 4093 => x"3d", + 4094 => x"3d", + 4095 => x"11", + 4096 => x"33", + 4097 => x"71", + 4098 => x"81", + 4099 => x"72", + 4100 => x"75", + 4101 => x"82", + 4102 => x"52", + 4103 => x"54", + 4104 => x"0d", + 4105 => x"0d", + 4106 => x"05", + 4107 => x"52", + 4108 => x"70", + 4109 => x"34", + 4110 => x"51", + 4111 => x"83", + 4112 => x"ff", + 4113 => x"75", + 4114 => x"72", + 4115 => x"54", + 4116 => x"2a", + 4117 => x"70", + 4118 => x"34", + 4119 => x"51", + 4120 => x"81", + 4121 => x"70", + 4122 => x"70", + 4123 => x"3d", + 4124 => x"3d", + 4125 => x"77", + 4126 => x"70", + 4127 => x"38", + 4128 => x"05", + 4129 => x"70", + 4130 => x"34", + 4131 => x"eb", + 4132 => x"0d", + 4133 => x"0d", + 4134 => x"54", + 4135 => x"72", + 4136 => x"54", + 4137 => x"51", + 4138 => x"84", + 4139 => x"fc", + 4140 => x"77", + 4141 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x"85", + 4318 => x"38", + 4319 => x"83", + 4320 => x"05", + 4321 => x"f8", + 4322 => x"85", + 4323 => x"0a", + 4324 => x"39", + 4325 => x"82", + 4326 => x"89", + 4327 => x"f8", + 4328 => x"7c", + 4329 => x"56", + 4330 => x"77", + 4331 => x"38", + 4332 => x"08", + 4333 => x"38", + 4334 => x"72", + 4335 => x"9d", + 4336 => x"24", + 4337 => x"81", + 4338 => x"82", + 4339 => x"83", + 4340 => x"38", + 4341 => x"76", + 4342 => x"70", + 4343 => x"18", + 4344 => x"76", + 4345 => x"97", + 4346 => x"ec", + 4347 => x"85", + 4348 => x"d9", + 4349 => x"ff", + 4350 => x"05", + 4351 => x"81", + 4352 => x"54", + 4353 => x"80", + 4354 => x"77", + 4355 => x"f0", + 4356 => x"8f", + 4357 => x"51", + 4358 => x"34", + 4359 => x"17", + 4360 => x"2a", + 4361 => x"05", + 4362 => x"fa", + 4363 => x"85", + 4364 => x"82", + 4365 => x"81", + 4366 => x"83", + 4367 => x"b4", + 4368 => x"2a", + 4369 => x"8f", + 4370 => x"2a", + 4371 => x"f0", + 4372 => x"06", + 4373 => x"72", + 4374 => x"ec", + 4375 => x"2a", + 4376 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4435 => x"38", + 4436 => x"fe", + 4437 => x"08", + 4438 => x"74", + 4439 => x"38", + 4440 => x"17", + 4441 => x"33", + 4442 => x"73", + 4443 => x"77", + 4444 => x"26", + 4445 => x"80", + 4446 => x"85", + 4447 => x"3d", + 4448 => x"3d", + 4449 => x"71", + 4450 => x"5b", + 4451 => x"8c", + 4452 => x"77", + 4453 => x"38", + 4454 => x"78", + 4455 => x"81", + 4456 => x"79", + 4457 => x"f9", + 4458 => x"55", + 4459 => x"ec", + 4460 => x"e6", + 4461 => x"ec", + 4462 => x"85", + 4463 => x"2e", + 4464 => x"98", + 4465 => x"85", + 4466 => x"82", + 4467 => x"58", + 4468 => x"70", + 4469 => x"80", + 4470 => x"38", + 4471 => x"09", + 4472 => x"e4", + 4473 => x"56", + 4474 => x"76", + 4475 => x"82", + 4476 => x"7a", + 4477 => x"3f", + 4478 => x"85", + 4479 => x"2e", + 4480 => x"86", + 4481 => x"ec", + 4482 => x"85", + 4483 => x"70", + 4484 => x"70", + 4485 => x"25", + 4486 => x"82", + 4487 => x"54", + 4488 => x"55", + 4489 => x"38", + 4490 => x"08", + 4491 => x"38", + 4492 => x"54", + 4493 => x"90", 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x"f8", + 4553 => x"70", + 4554 => x"e3", + 4555 => x"ec", + 4556 => x"56", + 4557 => x"08", + 4558 => x"7b", + 4559 => x"f6", + 4560 => x"85", + 4561 => x"85", + 4562 => x"17", + 4563 => x"80", + 4564 => x"b4", + 4565 => x"57", + 4566 => x"77", + 4567 => x"81", + 4568 => x"15", + 4569 => x"78", + 4570 => x"81", + 4571 => x"53", + 4572 => x"15", + 4573 => x"dc", + 4574 => x"ec", + 4575 => x"df", + 4576 => x"22", + 4577 => x"09", + 4578 => x"72", + 4579 => x"2a", + 4580 => x"56", + 4581 => x"ec", + 4582 => x"0d", + 4583 => x"0d", + 4584 => x"08", + 4585 => x"74", + 4586 => x"26", + 4587 => x"74", + 4588 => x"72", + 4589 => x"74", + 4590 => x"88", + 4591 => x"73", + 4592 => x"33", + 4593 => x"27", + 4594 => x"16", + 4595 => x"9b", + 4596 => x"2a", + 4597 => x"88", + 4598 => x"58", + 4599 => x"80", + 4600 => x"16", + 4601 => x"0c", + 4602 => x"8a", + 4603 => x"89", + 4604 => x"72", + 4605 => x"38", + 4606 => x"51", + 4607 => x"82", + 4608 => x"54", + 4609 => x"08", + 4610 => x"38", + 4611 => x"85", + 4612 => x"8b", + 4613 => x"08", + 4614 => x"08", + 4615 => x"82", + 4616 => x"74", + 4617 => x"cb", + 4618 => x"75", + 4619 => x"3f", + 4620 => x"08", + 4621 => x"73", + 4622 => x"98", + 4623 => x"82", + 4624 => x"2e", + 4625 => x"39", + 4626 => x"39", + 4627 => x"13", + 4628 => x"74", + 4629 => x"16", + 4630 => x"18", + 4631 => x"77", + 4632 => x"0c", + 4633 => x"04", + 4634 => x"7a", + 4635 => x"12", + 4636 => x"59", + 4637 => x"80", + 4638 => x"86", + 4639 => x"98", + 4640 => x"14", + 4641 => x"55", + 4642 => x"81", + 4643 => x"83", + 4644 => x"77", + 4645 => x"81", + 4646 => x"0c", + 4647 => x"55", + 4648 => x"76", + 4649 => x"17", + 4650 => x"74", + 4651 => x"9b", + 4652 => x"39", + 4653 => x"ff", + 4654 => x"2a", + 4655 => x"81", + 4656 => x"52", + 4657 => x"de", + 4658 => x"ec", + 4659 => x"55", + 4660 => x"85", + 4661 => x"80", + 4662 => x"55", + 4663 => x"08", + 4664 => x"f4", + 4665 => x"08", + 4666 => x"08", + 4667 => x"38", + 4668 => x"77", + 4669 => x"84", + 4670 => x"39", + 4671 => x"52", + 4672 => x"fe", + 4673 => x"ec", + 4674 => x"55", + 4675 => x"08", + 4676 => x"c4", + 4677 => x"82", + 4678 => x"81", + 4679 => x"81", + 4680 => x"ec", + 4681 => x"b0", + 4682 => x"ec", + 4683 => x"51", + 4684 => x"82", + 4685 => x"a0", + 4686 => x"15", + 4687 => x"75", + 4688 => x"3f", + 4689 => x"08", + 4690 => x"76", + 4691 => x"77", + 4692 => x"9c", + 4693 => x"55", + 4694 => x"ec", + 4695 => x"0d", + 4696 => x"0d", + 4697 => x"08", + 4698 => x"80", + 4699 => x"fc", + 4700 => x"85", + 4701 => x"82", + 4702 => x"80", + 4703 => x"85", + 4704 => x"98", + 4705 => x"78", + 4706 => x"3f", + 4707 => x"08", + 4708 => x"ec", + 4709 => x"38", + 4710 => x"08", + 4711 => x"70", + 4712 => x"58", + 4713 => x"2e", + 4714 => x"83", + 4715 => x"82", + 4716 => x"55", + 4717 => x"81", + 4718 => x"07", + 4719 => x"2e", + 4720 => x"16", + 4721 => x"2e", + 4722 => x"88", + 4723 => x"82", + 4724 => x"56", + 4725 => x"51", + 4726 => x"82", + 4727 => x"54", + 4728 => x"08", + 4729 => x"9b", + 4730 => x"2e", + 4731 => x"83", + 4732 => x"73", + 4733 => x"0c", + 4734 => x"04", + 4735 => x"76", + 4736 => x"54", + 4737 => x"82", + 4738 => x"83", + 4739 => x"76", + 4740 => x"53", + 4741 => x"2e", + 4742 => x"90", + 4743 => x"51", + 4744 => x"82", + 4745 => x"90", + 4746 => x"53", + 4747 => x"ec", + 4748 => x"0d", + 4749 => x"0d", + 4750 => x"83", + 4751 => x"54", + 4752 => x"55", + 4753 => x"3f", + 4754 => x"51", + 4755 => x"2e", + 4756 => x"8b", + 4757 => x"2a", + 4758 => x"51", + 4759 => x"86", + 4760 => x"f7", + 4761 => x"7d", + 4762 => x"75", + 4763 => x"98", + 4764 => x"2e", + 4765 => x"98", + 4766 => x"78", + 4767 => x"3f", + 4768 => x"08", + 4769 => x"ec", + 4770 => x"38", + 4771 => x"70", + 4772 => x"73", + 4773 => x"58", + 4774 => x"8b", + 4775 => x"bf", + 4776 => x"ff", + 4777 => x"53", + 4778 => x"34", + 4779 => x"08", + 4780 => x"e5", + 4781 => x"81", + 4782 => x"2e", + 4783 => x"70", + 4784 => x"57", + 4785 => x"9e", + 4786 => x"2e", + 4787 => x"85", + 4788 => x"df", + 4789 => x"72", + 4790 => x"81", + 4791 => x"76", + 4792 => x"2e", + 4793 => x"52", + 4794 => x"fc", + 4795 => x"ec", + 4796 => x"85", + 4797 => x"38", + 4798 => x"fe", + 4799 => x"39", + 4800 => x"16", + 4801 => x"85", + 4802 => x"3d", + 4803 => x"3d", + 4804 => x"08", + 4805 => x"52", + 4806 => x"c5", + 4807 => x"ec", + 4808 => x"85", + 4809 => x"38", + 4810 => x"52", + 4811 => x"cf", + 4812 => x"ec", + 4813 => x"85", + 4814 => x"38", + 4815 => x"85", + 4816 => x"9c", + 4817 => x"ea", + 4818 => x"53", + 4819 => x"9c", + 4820 => x"ea", + 4821 => x"0b", + 4822 => x"74", + 4823 => x"0c", + 4824 => x"04", + 4825 => x"75", + 4826 => x"12", + 4827 => x"53", + 4828 => x"8b", + 4829 => x"ec", + 4830 => x"9c", + 4831 => x"e5", + 4832 => x"0b", + 4833 => x"85", + 4834 => x"fa", + 4835 => x"7a", + 4836 => x"0b", + 4837 => x"98", + 4838 => x"2e", + 4839 => x"80", + 4840 => x"55", + 4841 => x"17", + 4842 => x"33", + 4843 => x"51", + 4844 => x"2e", + 4845 => x"85", + 4846 => x"06", + 4847 => x"e5", + 4848 => x"2e", + 4849 => x"8b", + 4850 => x"70", + 4851 => x"34", + 4852 => x"71", + 4853 => x"05", + 4854 => x"15", + 4855 => x"27", + 4856 => x"15", + 4857 => x"80", + 4858 => x"34", + 4859 => x"52", + 4860 => x"88", + 4861 => x"17", + 4862 => x"52", + 4863 => x"3f", + 4864 => x"08", + 4865 => x"12", + 4866 => x"3f", + 4867 => x"08", + 4868 => x"98", + 4869 => x"cb", + 4870 => x"ec", + 4871 => x"23", + 4872 => x"04", + 4873 => x"7f", + 4874 => x"5b", + 4875 => x"33", + 4876 => x"73", + 4877 => x"38", + 4878 => x"80", + 4879 => x"38", + 4880 => x"8c", + 4881 => x"08", + 4882 => x"ac", + 4883 => x"41", + 4884 => x"33", + 4885 => x"73", + 4886 => x"81", + 4887 => x"81", + 4888 => x"dc", + 4889 => x"81", + 4890 => x"25", + 4891 => x"51", + 4892 => x"38", + 4893 => x"0c", + 4894 => x"51", + 4895 => x"26", + 4896 => x"80", + 4897 => x"34", + 4898 => x"51", + 4899 => x"82", + 4900 => x"55", + 4901 => x"91", + 4902 => x"1d", + 4903 => x"8b", + 4904 => x"79", + 4905 => x"3f", + 4906 => x"57", + 4907 => x"55", + 4908 => x"2e", + 4909 => x"80", + 4910 => x"18", + 4911 => x"1a", + 4912 => x"70", + 4913 => x"70", + 4914 => x"82", + 4915 => x"51", + 4916 => x"54", + 4917 => x"79", + 4918 => x"74", + 4919 => x"57", + 4920 => x"af", + 4921 => x"81", + 4922 => x"2a", + 4923 => x"75", + 4924 => x"8c", + 4925 => x"2e", + 4926 => x"a0", + 4927 => x"38", + 4928 => x"0c", + 4929 => x"76", + 4930 => x"38", + 4931 => x"c2", + 4932 => x"70", + 4933 => x"5a", + 4934 => x"76", + 4935 => x"38", + 4936 => x"70", + 4937 => x"77", + 4938 => x"70", + 4939 => x"72", + 4940 => x"80", + 4941 => x"51", + 4942 => x"73", + 4943 => x"38", + 4944 => x"18", + 4945 => x"1a", + 4946 => x"55", + 4947 => x"2e", + 4948 => x"83", + 4949 => x"73", + 4950 => x"70", + 4951 => x"70", + 4952 => x"07", + 4953 => x"73", + 4954 => x"b9", + 4955 => x"2e", + 4956 => x"83", + 4957 => x"76", + 4958 => x"07", + 4959 => x"2e", + 4960 => x"8b", + 4961 => x"81", + 4962 => x"32", + 4963 => x"05", + 4964 => x"71", + 4965 => x"53", + 4966 => x"55", + 4967 => x"38", + 4968 => x"5c", + 4969 => x"75", + 4970 => x"73", + 4971 => x"38", + 4972 => x"06", + 4973 => x"11", + 4974 => x"75", + 4975 => x"3f", + 4976 => x"08", + 4977 => x"38", + 4978 => x"33", + 4979 => x"54", + 4980 => x"e6", + 4981 => x"85", + 4982 => x"2e", + 4983 => x"ff", + 4984 => x"74", + 4985 => x"38", + 4986 => x"75", + 4987 => x"17", + 4988 => x"57", + 4989 => x"a7", + 4990 => x"81", + 4991 => x"e5", + 4992 => x"85", + 4993 => x"38", + 4994 => x"54", + 4995 => x"89", + 4996 => x"70", + 4997 => x"57", + 4998 => x"54", + 4999 => x"81", + 5000 => x"ed", + 5001 => x"7e", + 5002 => x"2e", + 5003 => x"33", + 5004 => x"e5", + 5005 => x"06", + 5006 => x"7a", + 5007 => x"a0", + 5008 => x"38", + 5009 => x"55", + 5010 => x"84", + 5011 => x"39", + 5012 => x"8b", + 5013 => x"7b", + 5014 => x"7a", + 5015 => x"3f", + 5016 => x"08", + 5017 => x"ec", + 5018 => x"38", + 5019 => x"52", + 5020 => x"8b", + 5021 => x"ec", + 5022 => x"85", + 5023 => x"c2", + 5024 => x"08", + 5025 => x"55", + 5026 => x"ff", + 5027 => x"15", + 5028 => x"54", + 5029 => x"34", + 5030 => x"70", + 5031 => x"81", + 5032 => x"58", + 5033 => x"8b", + 5034 => x"74", + 5035 => x"3f", + 5036 => x"08", + 5037 => x"38", + 5038 => x"51", + 5039 => x"ff", + 5040 => x"ab", + 5041 => x"55", + 5042 => x"bb", + 5043 => x"2e", + 5044 => x"80", + 5045 => x"85", + 5046 => x"06", + 5047 => x"58", + 5048 => x"80", + 5049 => x"75", + 5050 => x"73", + 5051 => x"a7", + 5052 => x"0b", + 5053 => x"80", + 5054 => x"39", + 5055 => x"54", + 5056 => x"85", + 5057 => x"75", + 5058 => x"81", + 5059 => x"73", + 5060 => x"1b", + 5061 => x"2a", + 5062 => x"51", + 5063 => x"80", + 5064 => x"90", + 5065 => x"ff", + 5066 => x"05", + 5067 => x"f5", + 5068 => x"85", + 5069 => x"1c", + 5070 => x"39", + 5071 => x"ec", + 5072 => x"0d", + 5073 => x"0d", + 5074 => x"7b", + 5075 => x"73", + 5076 => x"55", + 5077 => x"2e", + 5078 => x"75", + 5079 => x"57", + 5080 => x"26", + 5081 => x"ba", + 5082 => x"70", + 5083 => x"ba", + 5084 => x"06", + 5085 => x"73", + 5086 => x"70", + 5087 => x"51", + 5088 => x"89", + 5089 => x"82", + 5090 => x"ff", + 5091 => x"56", + 5092 => x"2e", + 5093 => x"80", + 5094 => x"a4", + 5095 => x"08", + 5096 => x"76", + 5097 => x"58", + 5098 => x"81", + 5099 => x"ff", + 5100 => x"53", + 5101 => x"26", + 5102 => x"13", + 5103 => x"06", + 5104 => x"9f", + 5105 => x"99", + 5106 => x"e0", + 5107 => x"ff", + 5108 => x"72", + 5109 => x"70", + 5110 => x"51", + 5111 => x"09", + 5112 => x"38", + 5113 => x"38", + 5114 => x"05", + 5115 => x"70", + 5116 => x"70", + 5117 => x"2a", + 5118 => x"07", + 5119 => x"51", + 5120 => x"8f", + 5121 => x"84", + 5122 => x"83", + 5123 => x"8e", + 5124 => x"74", + 5125 => x"38", + 5126 => x"0c", + 5127 => x"86", + 5128 => x"a4", + 5129 => x"82", + 5130 => x"8c", + 5131 => x"fa", + 5132 => x"56", + 5133 => x"17", + 5134 => x"b0", + 5135 => x"52", + 5136 => x"bb", + 5137 => x"82", + 5138 => x"81", + 5139 => x"b2", + 5140 => x"8f", + 5141 => x"ec", + 5142 => x"ff", + 5143 => x"55", + 5144 => x"d5", + 5145 => x"06", + 5146 => x"80", + 5147 => x"33", + 5148 => x"81", + 5149 => x"81", + 5150 => x"81", + 5151 => x"eb", + 5152 => x"81", + 5153 => x"25", + 5154 => x"51", + 5155 => x"38", + 5156 => x"2e", + 5157 => x"b5", + 5158 => x"81", + 5159 => x"80", + 5160 => x"e0", + 5161 => x"85", + 5162 => x"82", + 5163 => x"80", + 5164 => x"85", + 5165 => x"e8", + 5166 => x"16", + 5167 => x"3f", + 5168 => x"08", + 5169 => x"ec", + 5170 => x"83", + 5171 => x"74", + 5172 => x"0c", + 5173 => x"04", + 5174 => x"62", + 5175 => x"80", + 5176 => x"58", + 5177 => x"0c", + 5178 => x"d9", + 5179 => x"ec", + 5180 => x"56", + 5181 => x"85", + 5182 => x"87", + 5183 => x"85", + 5184 => x"2b", + 5185 => x"11", + 5186 => x"8c", + 5187 => x"2e", + 5188 => x"73", + 5189 => x"81", + 5190 => x"33", + 5191 => x"80", + 5192 => x"81", + 5193 => x"d7", + 5194 => x"85", + 5195 => x"ff", + 5196 => x"06", + 5197 => x"98", + 5198 => x"2e", + 5199 => x"74", + 5200 => x"81", + 5201 => x"8a", + 5202 => x"b4", + 5203 => x"39", + 5204 => x"77", + 5205 => x"81", + 5206 => x"33", + 5207 => x"3f", + 5208 => x"08", + 5209 => x"70", + 5210 => x"55", + 5211 => x"86", + 5212 => x"80", + 5213 => x"74", + 5214 => x"81", + 5215 => x"8a", + 5216 => x"fc", + 5217 => x"53", + 5218 => x"fd", + 5219 => x"85", + 5220 => x"ff", + 5221 => x"82", + 5222 => x"06", + 5223 => x"8d", + 5224 => x"58", + 5225 => x"f6", + 5226 => x"58", + 5227 => x"2e", + 5228 => x"fa", + 5229 => x"c2", + 5230 => x"ec", + 5231 => x"78", + 5232 => x"5a", + 5233 => x"90", + 5234 => x"75", + 5235 => x"38", + 5236 => x"3d", + 5237 => x"70", + 5238 => x"08", + 5239 => x"7b", + 5240 => x"38", + 5241 => x"51", + 5242 => x"82", + 5243 => x"81", + 5244 => x"81", + 5245 => x"38", + 5246 => x"83", + 5247 => x"38", + 5248 => x"84", + 5249 => x"38", + 5250 => x"81", + 5251 => x"38", + 5252 => x"db", + 5253 => x"85", + 5254 => x"ff", + 5255 => x"72", + 5256 => x"09", + 5257 => x"d8", + 5258 => x"14", + 5259 => x"3f", + 5260 => x"08", + 5261 => x"06", + 5262 => x"38", + 5263 => x"51", + 5264 => x"82", + 5265 => x"58", + 5266 => x"0c", + 5267 => x"33", + 5268 => x"80", + 5269 => x"ff", + 5270 => x"ff", + 5271 => x"55", + 5272 => x"81", + 5273 => x"38", + 5274 => x"06", + 5275 => x"fe", + 5276 => x"82", + 5277 => x"80", + 5278 => x"54", + 5279 => x"15", + 5280 => x"2e", + 5281 => x"13", + 5282 => x"72", + 5283 => x"38", + 5284 => x"ec", + 5285 => x"14", + 5286 => x"3f", + 5287 => x"08", + 5288 => x"ec", + 5289 => x"23", + 5290 => x"57", + 5291 => x"83", + 5292 => x"c7", + 5293 => x"ab", + 5294 => x"ec", + 5295 => x"ff", + 5296 => x"8d", + 5297 => x"14", + 5298 => x"3f", + 5299 => x"08", + 5300 => x"14", + 5301 => x"3f", + 5302 => x"08", + 5303 => x"06", + 5304 => x"79", + 5305 => x"98", + 5306 => x"22", + 5307 => x"84", + 5308 => x"5b", + 5309 => x"83", + 5310 => x"14", + 5311 => x"79", + 5312 => x"f8", + 5313 => x"85", + 5314 => x"82", + 5315 => x"80", + 5316 => x"38", + 5317 => x"08", + 5318 => x"ff", + 5319 => x"38", + 5320 => x"83", + 5321 => x"83", + 5322 => x"72", + 5323 => x"85", + 5324 => x"89", + 5325 => x"76", + 5326 => x"c4", + 5327 => x"70", + 5328 => x"7c", + 5329 => x"7a", + 5330 => x"17", + 5331 => x"ac", + 5332 => x"55", + 5333 => x"09", + 5334 => x"38", + 5335 => x"51", + 5336 => x"82", + 5337 => x"83", + 5338 => x"53", + 5339 => x"82", + 5340 => x"82", + 5341 => x"e0", + 5342 => x"fe", + 5343 => x"ec", + 5344 => x"0c", + 5345 => x"53", + 5346 => x"56", + 5347 => x"81", + 5348 => x"13", + 5349 => x"74", + 5350 => x"82", + 5351 => x"74", + 5352 => x"81", + 5353 => x"06", + 5354 => x"53", + 5355 => x"89", + 5356 => x"56", + 5357 => x"08", + 5358 => x"38", + 5359 => x"15", + 5360 => x"8c", + 5361 => x"80", + 5362 => x"34", + 5363 => x"09", + 5364 => x"92", + 5365 => x"14", + 5366 => x"3f", + 5367 => x"08", + 5368 => x"06", + 5369 => x"2e", + 5370 => x"80", + 5371 => x"1c", + 5372 => x"db", + 5373 => x"85", + 5374 => x"ea", + 5375 => x"ec", + 5376 => x"34", + 5377 => x"51", + 5378 => x"82", + 5379 => x"83", + 5380 => x"53", + 5381 => x"d5", + 5382 => x"06", + 5383 => x"b4", + 5384 => x"d6", + 5385 => x"ec", + 5386 => x"85", + 5387 => x"09", + 5388 => x"38", + 5389 => x"51", + 5390 => x"82", + 5391 => x"86", + 5392 => x"f2", + 5393 => x"06", + 5394 => x"9c", + 5395 => x"aa", + 5396 => x"ec", + 5397 => x"0c", + 5398 => x"51", + 5399 => x"82", + 5400 => x"8c", + 5401 => x"74", + 5402 => x"a0", + 5403 => x"53", + 5404 => x"a0", + 5405 => x"15", + 5406 => x"94", + 5407 => x"56", + 5408 => x"ec", + 5409 => x"0d", + 5410 => x"0d", + 5411 => x"55", + 5412 => x"b9", + 5413 => x"53", + 5414 => x"b1", + 5415 => x"52", + 5416 => x"a9", + 5417 => x"22", + 5418 => x"57", + 5419 => x"2e", + 5420 => x"99", + 5421 => x"33", + 5422 => x"3f", + 5423 => x"08", + 5424 => x"71", + 5425 => x"74", + 5426 => x"83", + 5427 => x"78", + 5428 => x"52", + 5429 => x"ec", + 5430 => x"0d", + 5431 => x"0d", + 5432 => x"33", + 5433 => x"3d", + 5434 => x"56", + 5435 => x"8b", + 5436 => x"82", + 5437 => x"24", + 5438 => x"85", + 5439 => x"2b", + 5440 => x"05", + 5441 => x"55", + 5442 => x"84", + 5443 => x"34", + 5444 => x"80", + 5445 => x"80", + 5446 => x"75", + 5447 => x"75", + 5448 => x"38", + 5449 => x"3d", + 5450 => x"05", + 5451 => x"3f", + 5452 => x"08", + 5453 => x"85", + 5454 => x"3d", + 5455 => x"3d", + 5456 => x"84", + 5457 => x"05", + 5458 => x"89", + 5459 => x"2e", + 5460 => x"77", + 5461 => x"54", + 5462 => x"05", + 5463 => x"84", + 5464 => x"f6", + 5465 => x"85", + 5466 => x"82", + 5467 => x"84", + 5468 => x"5c", + 5469 => x"3d", + 5470 => x"ed", + 5471 => x"85", + 5472 => x"82", + 5473 => x"92", + 5474 => x"d7", + 5475 => x"98", + 5476 => x"73", + 5477 => x"38", + 5478 => x"9c", + 5479 => x"80", + 5480 => x"38", + 5481 => x"95", + 5482 => x"2e", + 5483 => x"aa", + 5484 => x"ea", + 5485 => x"85", + 5486 => x"9e", + 5487 => x"05", + 5488 => x"54", + 5489 => x"38", + 5490 => x"70", + 5491 => x"54", + 5492 => x"8e", + 5493 => x"83", + 5494 => x"88", + 5495 => x"83", + 5496 => x"83", + 5497 => x"06", + 5498 => x"80", + 5499 => x"38", + 5500 => x"51", + 5501 => x"82", + 5502 => x"56", + 5503 => x"0a", + 5504 => x"05", + 5505 => x"3f", + 5506 => x"0b", + 5507 => x"80", + 5508 => x"7a", + 5509 => x"3f", + 5510 => x"9c", + 5511 => x"a3", + 5512 => x"81", + 5513 => x"34", + 5514 => x"80", + 5515 => x"b0", + 5516 => x"54", + 5517 => x"52", + 5518 => x"05", + 5519 => x"3f", + 5520 => x"08", + 5521 => x"ec", + 5522 => x"38", + 5523 => x"82", + 5524 => x"b2", + 5525 => x"84", + 5526 => x"06", + 5527 => x"73", + 5528 => x"38", + 5529 => x"af", + 5530 => x"2a", + 5531 => x"51", + 5532 => x"2e", + 5533 => x"81", + 5534 => x"80", + 5535 => x"87", + 5536 => x"39", + 5537 => x"51", + 5538 => x"82", + 5539 => x"7b", + 5540 => x"12", + 5541 => x"82", + 5542 => x"81", + 5543 => x"83", + 5544 => x"06", + 5545 => x"80", + 5546 => x"77", + 5547 => x"58", + 5548 => x"08", + 5549 => x"63", + 5550 => x"63", + 5551 => x"57", + 5552 => x"82", + 5553 => x"82", + 5554 => x"88", + 5555 => x"9c", + 5556 => x"d2", + 5557 => x"85", + 5558 => x"85", + 5559 => x"1b", + 5560 => x"0c", + 5561 => x"22", + 5562 => x"77", + 5563 => x"80", + 5564 => x"34", + 5565 => x"1a", + 5566 => x"94", + 5567 => x"85", + 5568 => x"06", + 5569 => x"80", + 5570 => x"38", + 5571 => x"08", + 5572 => x"86", + 5573 => x"ec", + 5574 => x"0c", + 5575 => x"70", + 5576 => x"52", + 5577 => x"39", + 5578 => x"51", + 5579 => x"82", + 5580 => x"57", + 5581 => x"08", + 5582 => x"38", + 5583 => x"85", + 5584 => x"2e", + 5585 => x"83", + 5586 => x"75", + 5587 => x"74", + 5588 => x"70", + 5589 => x"25", + 5590 => x"76", + 5591 => x"81", + 5592 => x"55", + 5593 => x"38", + 5594 => x"0c", + 5595 => x"75", + 5596 => x"54", + 5597 => x"a2", + 5598 => x"7a", + 5599 => x"3f", + 5600 => x"08", + 5601 => x"55", + 5602 => x"89", + 5603 => x"ec", + 5604 => x"1a", + 5605 => x"80", + 5606 => x"54", + 5607 => x"ec", + 5608 => x"0d", + 5609 => x"0d", + 5610 => x"64", + 5611 => x"59", + 5612 => x"90", + 5613 => x"52", + 5614 => x"cd", + 5615 => x"ec", + 5616 => x"85", + 5617 => x"38", + 5618 => x"55", + 5619 => x"86", + 5620 => x"82", + 5621 => x"19", + 5622 => x"55", + 5623 => x"80", + 5624 => x"38", + 5625 => x"0b", + 5626 => x"82", + 5627 => x"39", + 5628 => x"1a", + 5629 => x"82", + 5630 => x"19", + 5631 => x"08", + 5632 => x"7c", + 5633 => x"74", + 5634 => x"2e", + 5635 => x"94", + 5636 => x"83", + 5637 => x"56", + 5638 => x"38", + 5639 => x"22", + 5640 => x"89", + 5641 => x"55", + 5642 => x"75", + 5643 => x"19", + 5644 => x"39", + 5645 => x"52", + 5646 => x"ea", + 5647 => x"ec", + 5648 => x"75", + 5649 => x"38", + 5650 => x"ff", + 5651 => x"98", + 5652 => x"19", + 5653 => x"51", + 5654 => x"82", + 5655 => x"80", + 5656 => x"38", + 5657 => x"08", + 5658 => x"2a", + 5659 => x"80", + 5660 => x"38", + 5661 => x"8a", + 5662 => x"5c", + 5663 => x"27", + 5664 => x"7a", + 5665 => x"54", + 5666 => x"52", + 5667 => x"51", + 5668 => x"82", + 5669 => x"fe", + 5670 => x"83", + 5671 => x"56", + 5672 => x"9f", + 5673 => x"08", + 5674 => x"74", + 5675 => x"38", + 5676 => x"b4", + 5677 => x"16", + 5678 => x"89", + 5679 => x"51", + 5680 => x"77", + 5681 => x"b9", + 5682 => x"1a", + 5683 => x"08", + 5684 => x"84", + 5685 => x"57", + 5686 => x"27", + 5687 => x"56", + 5688 => x"52", + 5689 => x"97", + 5690 => x"ec", + 5691 => x"38", + 5692 => x"19", + 5693 => x"06", + 5694 => x"52", + 5695 => x"f2", + 5696 => x"31", + 5697 => x"7f", + 5698 => x"94", + 5699 => x"94", + 5700 => x"5c", + 5701 => x"80", + 5702 => x"85", + 5703 => x"3d", + 5704 => x"3d", + 5705 => x"65", + 5706 => x"5d", + 5707 => x"0c", + 5708 => x"05", + 5709 => x"f6", + 5710 => x"85", + 5711 => x"82", + 5712 => x"8a", + 5713 => x"33", + 5714 => x"2e", + 5715 => x"56", + 5716 => x"90", + 5717 => x"81", + 5718 => x"06", + 5719 => x"87", + 5720 => x"2e", + 5721 => x"95", + 5722 => x"91", + 5723 => x"56", + 5724 => x"81", + 5725 => x"34", + 5726 => x"8e", + 5727 => x"08", + 5728 => x"56", + 5729 => x"84", + 5730 => x"5c", + 5731 => x"82", + 5732 => x"18", + 5733 => x"ff", + 5734 => x"74", + 5735 => x"7e", + 5736 => x"ff", + 5737 => x"2a", + 5738 => x"7a", + 5739 => x"8c", + 5740 => x"08", + 5741 => x"38", + 5742 => x"39", + 5743 => x"52", + 5744 => x"be", + 5745 => x"ec", + 5746 => x"85", + 5747 => x"2e", + 5748 => x"74", + 5749 => x"91", + 5750 => x"2e", + 5751 => x"74", + 5752 => x"88", + 5753 => x"38", + 5754 => x"0c", + 5755 => x"15", + 5756 => x"08", + 5757 => x"06", + 5758 => x"51", + 5759 => x"82", + 5760 => x"fe", + 5761 => x"18", + 5762 => x"51", + 5763 => x"82", + 5764 => x"80", + 5765 => x"38", + 5766 => x"08", + 5767 => x"2a", + 5768 => x"80", + 5769 => x"38", + 5770 => x"8a", + 5771 => x"5b", + 5772 => x"27", + 5773 => x"7b", + 5774 => x"54", + 5775 => x"52", + 5776 => x"51", + 5777 => x"82", + 5778 => x"fe", + 5779 => x"b0", + 5780 => x"31", + 5781 => x"79", + 5782 => x"84", + 5783 => x"16", + 5784 => x"89", + 5785 => x"52", + 5786 => x"cc", + 5787 => x"55", + 5788 => x"16", + 5789 => x"2b", + 5790 => x"39", + 5791 => x"94", + 5792 => x"93", + 5793 => x"cd", + 5794 => x"85", + 5795 => x"e3", + 5796 => x"b0", + 5797 => x"76", + 5798 => x"94", + 5799 => x"ff", + 5800 => x"71", + 5801 => x"7b", + 5802 => x"38", + 5803 => x"18", + 5804 => x"51", + 5805 => x"82", + 5806 => x"fd", + 5807 => x"53", + 5808 => x"18", + 5809 => x"06", + 5810 => x"51", + 5811 => x"7e", + 5812 => x"83", + 5813 => x"76", + 5814 => x"17", + 5815 => x"1e", + 5816 => x"18", + 5817 => x"0c", + 5818 => x"58", + 5819 => x"74", + 5820 => x"38", + 5821 => x"8c", + 5822 => x"90", + 5823 => x"33", + 5824 => x"55", + 5825 => x"34", + 5826 => x"82", + 5827 => x"90", + 5828 => x"f8", + 5829 => x"8b", + 5830 => x"53", + 5831 => x"f2", + 5832 => x"85", + 5833 => x"82", + 5834 => x"80", + 5835 => x"16", + 5836 => x"2a", + 5837 => x"51", + 5838 => x"80", + 5839 => x"38", + 5840 => x"52", + 5841 => x"b7", + 5842 => x"ec", + 5843 => x"85", + 5844 => x"d4", + 5845 => x"08", + 5846 => x"a0", + 5847 => x"73", + 5848 => x"88", + 5849 => x"74", + 5850 => x"51", + 5851 => x"8c", + 5852 => x"9c", + 5853 => x"cb", + 5854 => x"b2", + 5855 => x"15", + 5856 => x"3f", + 5857 => x"15", + 5858 => x"3f", + 5859 => x"0b", + 5860 => x"78", + 5861 => x"3f", + 5862 => x"08", + 5863 => x"81", + 5864 => x"57", + 5865 => x"34", + 5866 => x"ec", + 5867 => x"0d", + 5868 => x"0d", + 5869 => x"54", + 5870 => x"82", + 5871 => x"53", + 5872 => x"08", + 5873 => x"3d", + 5874 => x"73", + 5875 => x"3f", + 5876 => x"08", + 5877 => x"ec", + 5878 => x"82", + 5879 => x"74", + 5880 => x"85", + 5881 => x"3d", + 5882 => x"3d", + 5883 => x"51", + 5884 => x"8b", + 5885 => x"82", + 5886 => x"24", + 5887 => x"85", + 5888 => x"9d", + 5889 => x"52", + 5890 => x"ec", + 5891 => x"0d", + 5892 => x"0d", + 5893 => x"3d", + 5894 => x"94", + 5895 => x"b8", + 5896 => x"ec", + 5897 => x"85", + 5898 => x"e0", + 5899 => x"63", + 5900 => x"d4", + 5901 => x"ec", + 5902 => x"ec", + 5903 => x"85", + 5904 => x"38", + 5905 => x"05", + 5906 => x"2b", + 5907 => x"80", + 5908 => x"76", + 5909 => x"0c", + 5910 => x"02", + 5911 => x"70", + 5912 => x"81", + 5913 => x"56", + 5914 => x"9e", + 5915 => x"53", + 5916 => x"db", + 5917 => x"85", + 5918 => x"15", + 5919 => x"82", + 5920 => x"84", + 5921 => x"06", + 5922 => x"55", + 5923 => x"ec", + 5924 => x"0d", + 5925 => x"0d", + 5926 => x"5b", + 5927 => x"80", + 5928 => x"ff", + 5929 => x"9f", + 5930 => x"ac", + 5931 => x"ec", + 5932 => x"85", + 5933 => x"fb", + 5934 => x"7a", + 5935 => x"08", + 5936 => x"64", + 5937 => x"2e", + 5938 => x"a0", + 5939 => x"70", + 5940 => x"c9", + 5941 => x"ec", + 5942 => x"85", + 5943 => x"d3", + 5944 => x"7b", + 5945 => x"3f", + 5946 => x"08", + 5947 => x"ec", + 5948 => x"38", + 5949 => x"51", + 5950 => x"82", + 5951 => x"45", + 5952 => x"51", + 5953 => x"82", + 5954 => x"57", + 5955 => x"08", + 5956 => x"80", + 5957 => x"da", + 5958 => x"85", + 5959 => x"82", + 5960 => x"a4", + 5961 => x"7b", + 5962 => x"3f", + 5963 => x"ec", + 5964 => x"38", + 5965 => x"51", + 5966 => x"82", + 5967 => x"57", + 5968 => x"08", + 5969 => x"38", + 5970 => x"09", + 5971 => x"38", + 5972 => x"df", + 5973 => x"db", + 5974 => x"ff", + 5975 => x"74", + 5976 => x"3f", + 5977 => x"78", + 5978 => x"33", + 5979 => x"56", + 5980 => x"91", + 5981 => x"05", + 5982 => x"81", + 5983 => x"56", + 5984 => x"f5", + 5985 => x"54", + 5986 => x"81", + 5987 => x"80", + 5988 => x"78", + 5989 => x"55", + 5990 => x"11", + 5991 => x"18", + 5992 => x"58", + 5993 => x"34", + 5994 => x"ff", + 5995 => x"55", + 5996 => x"34", + 5997 => x"77", + 5998 => x"81", + 5999 => x"ff", + 6000 => x"55", + 6001 => x"34", + 6002 => x"9d", + 6003 => x"82", + 6004 => x"a4", + 6005 => x"33", + 6006 => x"56", + 6007 => x"2e", + 6008 => x"16", + 6009 => x"33", + 6010 => x"73", + 6011 => x"16", + 6012 => x"26", + 6013 => x"55", + 6014 => x"91", + 6015 => x"54", + 6016 => x"70", + 6017 => x"34", + 6018 => x"ec", + 6019 => x"70", + 6020 => x"34", + 6021 => x"09", + 6022 => x"38", + 6023 => x"39", + 6024 => x"19", + 6025 => x"33", + 6026 => x"05", + 6027 => x"78", + 6028 => x"80", + 6029 => x"82", + 6030 => x"9e", + 6031 => x"f7", + 6032 => x"7d", + 6033 => x"05", + 6034 => x"57", + 6035 => x"3f", + 6036 => x"08", + 6037 => x"ec", + 6038 => x"38", + 6039 => x"53", + 6040 => x"38", + 6041 => x"54", + 6042 => x"92", + 6043 => x"33", + 6044 => x"70", + 6045 => x"54", + 6046 => x"38", + 6047 => x"15", + 6048 => x"70", + 6049 => x"58", + 6050 => x"82", + 6051 => x"8a", + 6052 => x"89", + 6053 => x"53", + 6054 => x"b9", + 6055 => x"ff", + 6056 => x"e0", + 6057 => x"85", + 6058 => x"15", + 6059 => x"53", + 6060 => x"e0", + 6061 => x"85", + 6062 => x"26", + 6063 => x"09", + 6064 => x"75", + 6065 => x"18", + 6066 => x"31", + 6067 => x"57", + 6068 => x"b1", + 6069 => x"08", + 6070 => x"38", + 6071 => x"51", + 6072 => x"82", + 6073 => x"54", + 6074 => x"08", + 6075 => x"9a", + 6076 => x"ec", + 6077 => x"81", + 6078 => x"85", + 6079 => x"16", + 6080 => x"16", + 6081 => x"2e", + 6082 => x"76", + 6083 => x"dc", + 6084 => x"31", + 6085 => x"18", + 6086 => x"90", + 6087 => x"81", + 6088 => x"06", + 6089 => x"56", + 6090 => x"9a", + 6091 => x"74", + 6092 => x"3f", + 6093 => x"08", + 6094 => x"ec", + 6095 => x"82", + 6096 => x"56", + 6097 => x"52", + 6098 => x"da", + 6099 => x"ec", + 6100 => x"ff", + 6101 => x"81", + 6102 => x"38", + 6103 => x"98", + 6104 => x"a6", + 6105 => x"16", + 6106 => x"39", + 6107 => x"16", + 6108 => x"75", + 6109 => x"53", + 6110 => x"aa", + 6111 => x"79", + 6112 => x"3f", + 6113 => x"08", + 6114 => x"0b", + 6115 => x"82", + 6116 => x"39", + 6117 => x"16", + 6118 => x"bb", + 6119 => x"2a", + 6120 => x"08", + 6121 => x"15", + 6122 => x"15", + 6123 => x"90", + 6124 => x"16", + 6125 => x"33", + 6126 => x"53", + 6127 => x"34", + 6128 => x"06", + 6129 => x"2e", + 6130 => x"9c", + 6131 => x"85", + 6132 => x"16", + 6133 => x"72", + 6134 => x"0c", + 6135 => x"04", + 6136 => x"79", + 6137 => x"75", + 6138 => x"8a", + 6139 => x"89", + 6140 => x"52", + 6141 => x"05", + 6142 => x"3f", + 6143 => x"08", + 6144 => x"ec", + 6145 => x"38", + 6146 => x"7a", + 6147 => x"d8", + 6148 => x"85", + 6149 => x"82", + 6150 => x"80", + 6151 => x"16", + 6152 => x"2b", + 6153 => x"74", + 6154 => x"86", + 6155 => x"84", + 6156 => x"06", + 6157 => x"73", + 6158 => x"38", + 6159 => x"52", + 6160 => x"b8", + 6161 => x"ec", + 6162 => x"0c", + 6163 => x"14", + 6164 => x"23", + 6165 => x"51", + 6166 => x"82", + 6167 => x"55", + 6168 => x"09", + 6169 => x"38", + 6170 => x"39", + 6171 => x"84", + 6172 => x"0c", + 6173 => x"82", + 6174 => x"89", + 6175 => x"fc", + 6176 => x"87", + 6177 => x"53", + 6178 => x"e7", + 6179 => x"85", + 6180 => x"38", + 6181 => x"08", + 6182 => x"3d", + 6183 => x"3d", + 6184 => x"89", + 6185 => x"54", + 6186 => x"54", + 6187 => x"82", + 6188 => x"53", + 6189 => x"08", + 6190 => x"74", + 6191 => x"85", + 6192 => x"73", + 6193 => x"3f", + 6194 => x"08", + 6195 => x"39", + 6196 => x"08", + 6197 => x"d3", + 6198 => x"85", + 6199 => x"82", + 6200 => x"84", + 6201 => x"06", + 6202 => x"53", + 6203 => x"85", + 6204 => x"38", + 6205 => x"51", + 6206 => x"72", + 6207 => x"ce", + 6208 => x"85", + 6209 => x"32", + 6210 => x"05", + 6211 => x"9f", + 6212 => x"85", + 6213 => x"51", + 6214 => x"72", + 6215 => x"0c", + 6216 => x"04", + 6217 => x"65", + 6218 => x"89", + 6219 => x"96", + 6220 => x"df", + 6221 => x"85", + 6222 => x"82", + 6223 => x"b2", + 6224 => x"75", + 6225 => x"3f", + 6226 => x"08", + 6227 => x"ec", + 6228 => x"02", + 6229 => x"33", + 6230 => x"55", + 6231 => x"25", + 6232 => x"55", + 6233 => x"80", + 6234 => x"76", + 6235 => x"d4", + 6236 => x"82", + 6237 => x"94", + 6238 => x"f0", + 6239 => x"65", + 6240 => x"53", + 6241 => x"05", + 6242 => x"51", + 6243 => x"82", + 6244 => x"5b", + 6245 => x"08", + 6246 => x"7c", + 6247 => x"08", + 6248 => x"fe", + 6249 => x"08", + 6250 => x"55", + 6251 => x"91", + 6252 => x"0c", + 6253 => x"81", + 6254 => x"39", + 6255 => x"ce", + 6256 => x"ec", + 6257 => x"55", + 6258 => x"2e", + 6259 => x"80", + 6260 => x"75", + 6261 => x"52", + 6262 => x"05", + 6263 => x"3f", + 6264 => x"08", + 6265 => x"38", + 6266 => x"08", + 6267 => x"38", + 6268 => x"08", + 6269 => x"70", + 6270 => x"08", + 6271 => x"7a", + 6272 => x"7f", + 6273 => x"54", + 6274 => x"77", + 6275 => x"80", + 6276 => x"15", + 6277 => x"ec", + 6278 => x"75", + 6279 => x"52", + 6280 => x"52", + 6281 => x"d7", + 6282 => x"ec", + 6283 => x"85", + 6284 => x"da", + 6285 => x"33", + 6286 => x"1a", + 6287 => x"54", + 6288 => x"09", + 6289 => x"38", + 6290 => x"ff", + 6291 => x"82", + 6292 => x"83", + 6293 => x"70", + 6294 => x"70", + 6295 => x"82", + 6296 => x"51", + 6297 => x"b4", + 6298 => x"bb", + 6299 => x"85", + 6300 => x"0a", + 6301 => x"81", + 6302 => x"25", + 6303 => x"59", + 6304 => x"75", + 6305 => x"7a", + 6306 => x"ff", + 6307 => x"7c", + 6308 => x"90", + 6309 => x"11", + 6310 => x"56", + 6311 => x"15", + 6312 => x"85", + 6313 => x"3d", + 6314 => x"3d", + 6315 => x"3d", + 6316 => x"70", + 6317 => x"d1", + 6318 => x"ec", + 6319 => x"85", + 6320 => x"a8", + 6321 => x"33", + 6322 => x"a0", + 6323 => x"33", + 6324 => x"70", + 6325 => x"55", + 6326 => x"73", + 6327 => x"8e", + 6328 => x"08", + 6329 => x"18", + 6330 => x"80", + 6331 => x"38", + 6332 => x"08", + 6333 => x"08", + 6334 => x"c3", + 6335 => x"85", + 6336 => x"88", + 6337 => x"80", + 6338 => x"17", + 6339 => x"51", + 6340 => x"3f", + 6341 => x"08", + 6342 => x"81", + 6343 => x"81", + 6344 => x"ec", + 6345 => x"09", + 6346 => x"38", + 6347 => x"39", + 6348 => x"77", + 6349 => x"ec", + 6350 => x"08", + 6351 => x"98", + 6352 => x"82", + 6353 => x"52", + 6354 => x"8a", + 6355 => x"ec", + 6356 => x"17", + 6357 => x"0c", + 6358 => x"80", + 6359 => x"73", + 6360 => x"75", + 6361 => x"38", + 6362 => x"34", + 6363 => x"82", + 6364 => x"89", + 6365 => x"e2", + 6366 => x"53", + 6367 => x"a4", + 6368 => x"3d", + 6369 => x"3f", + 6370 => x"08", + 6371 => x"ec", + 6372 => x"38", + 6373 => x"3d", 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x"c2", + 6433 => x"ec", + 6434 => x"82", + 6435 => x"a0", + 6436 => x"e9", + 6437 => x"53", + 6438 => x"05", + 6439 => x"51", + 6440 => x"82", + 6441 => x"54", + 6442 => x"08", + 6443 => x"78", + 6444 => x"8e", + 6445 => x"58", + 6446 => x"82", + 6447 => x"54", + 6448 => x"08", + 6449 => x"54", + 6450 => x"82", + 6451 => x"84", + 6452 => x"06", + 6453 => x"02", + 6454 => x"33", + 6455 => x"81", + 6456 => x"86", + 6457 => x"f6", + 6458 => x"74", + 6459 => x"70", + 6460 => x"8e", + 6461 => x"ec", + 6462 => x"56", + 6463 => x"08", + 6464 => x"54", + 6465 => x"08", + 6466 => x"81", + 6467 => x"82", + 6468 => x"ec", + 6469 => x"09", + 6470 => x"38", + 6471 => x"b4", + 6472 => x"b0", + 6473 => x"ec", + 6474 => x"51", + 6475 => x"82", + 6476 => x"54", + 6477 => x"08", + 6478 => x"8b", + 6479 => x"b4", + 6480 => x"b6", + 6481 => x"54", + 6482 => x"15", + 6483 => x"90", + 6484 => x"34", + 6485 => x"0a", + 6486 => x"19", + 6487 => x"e3", + 6488 => x"78", + 6489 => x"51", + 6490 => x"a0", + 6491 => x"11", + 6492 => x"05", + 6493 => x"fa", + 6494 => x"ae", + 6495 => x"15", + 6496 => x"78", + 6497 => x"53", + 6498 => x"3f", + 6499 => x"0b", + 6500 => x"77", + 6501 => x"3f", + 6502 => x"08", + 6503 => x"ec", + 6504 => x"82", + 6505 => x"52", + 6506 => x"51", + 6507 => x"3f", + 6508 => x"52", + 6509 => x"fd", + 6510 => x"90", + 6511 => x"34", + 6512 => x"0b", + 6513 => x"78", + 6514 => x"fa", + 6515 => x"ec", + 6516 => x"39", + 6517 => x"52", + 6518 => x"bd", + 6519 => x"82", + 6520 => x"99", + 6521 => x"da", + 6522 => x"3d", + 6523 => x"d2", + 6524 => x"53", + 6525 => x"84", + 6526 => x"3d", + 6527 => x"3f", + 6528 => x"08", + 6529 => x"ec", + 6530 => x"38", + 6531 => x"3d", + 6532 => x"3d", + 6533 => x"cc", + 6534 => x"85", + 6535 => x"82", + 6536 => x"82", + 6537 => x"81", + 6538 => x"81", + 6539 => x"86", + 6540 => x"aa", + 6541 => x"a4", + 6542 => x"a8", + 6543 => x"05", + 6544 => x"ae", + 6545 => x"77", + 6546 => x"70", + 6547 => x"b4", + 6548 => x"3d", + 6549 => x"51", + 6550 => x"82", + 6551 => x"55", + 6552 => x"08", + 6553 => x"6f", + 6554 => x"06", + 6555 => x"a2", + 6556 => x"92", + 6557 => x"81", + 6558 => x"85", + 6559 => x"2e", + 6560 => x"81", + 6561 => x"51", + 6562 => x"82", + 6563 => x"55", + 6564 => x"08", + 6565 => x"68", + 6566 => x"a8", + 6567 => x"05", + 6568 => x"51", + 6569 => x"3f", + 6570 => x"33", + 6571 => x"8b", + 6572 => x"84", + 6573 => x"06", + 6574 => x"73", + 6575 => x"a0", + 6576 => x"8b", + 6577 => x"54", + 6578 => x"15", + 6579 => x"33", + 6580 => x"70", + 6581 => x"55", + 6582 => x"2e", + 6583 => x"6e", + 6584 => x"df", + 6585 => x"78", + 6586 => x"3f", + 6587 => x"08", + 6588 => x"ff", + 6589 => x"82", + 6590 => x"ec", + 6591 => x"80", + 6592 => x"85", + 6593 => x"78", + 6594 => x"f3", + 6595 => x"ec", + 6596 => x"d4", + 6597 => x"55", + 6598 => x"08", + 6599 => x"81", + 6600 => x"73", + 6601 => x"81", + 6602 => x"63", + 6603 => x"76", + 6604 => x"3f", + 6605 => x"0b", + 6606 => x"87", + 6607 => x"ec", + 6608 => x"77", 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x"17", + 6668 => x"2b", + 6669 => x"96", + 6670 => x"b0", + 6671 => x"54", + 6672 => x"15", + 6673 => x"ff", + 6674 => x"82", + 6675 => x"55", + 6676 => x"ec", + 6677 => x"0d", + 6678 => x"0d", + 6679 => x"5a", + 6680 => x"3d", + 6681 => x"99", + 6682 => x"ec", + 6683 => x"ec", + 6684 => x"ec", + 6685 => x"05", + 6686 => x"ec", + 6687 => x"25", + 6688 => x"79", + 6689 => x"85", + 6690 => x"75", + 6691 => x"73", + 6692 => x"f9", + 6693 => x"80", + 6694 => x"8d", + 6695 => x"54", + 6696 => x"3f", + 6697 => x"08", + 6698 => x"ec", + 6699 => x"38", + 6700 => x"51", + 6701 => x"82", + 6702 => x"57", + 6703 => x"08", + 6704 => x"85", + 6705 => x"85", + 6706 => x"5b", + 6707 => x"18", + 6708 => x"18", + 6709 => x"74", + 6710 => x"81", + 6711 => x"78", + 6712 => x"8b", + 6713 => x"54", + 6714 => x"75", + 6715 => x"38", + 6716 => x"1b", + 6717 => x"55", + 6718 => x"2e", + 6719 => x"39", + 6720 => x"09", + 6721 => x"38", + 6722 => x"80", + 6723 => x"81", + 6724 => x"07", + 6725 => x"54", + 6726 => x"80", + 6727 => x"80", + 6728 => x"7b", + 6729 => x"53", + 6730 => x"d3", + 6731 => x"ec", + 6732 => x"85", + 6733 => x"38", + 6734 => x"55", + 6735 => x"56", + 6736 => x"8b", + 6737 => x"56", + 6738 => x"83", + 6739 => x"75", + 6740 => x"51", + 6741 => x"3f", + 6742 => x"08", + 6743 => x"82", + 6744 => x"98", + 6745 => x"e6", + 6746 => x"53", + 6747 => x"b8", + 6748 => x"3d", + 6749 => x"3f", + 6750 => x"08", + 6751 => x"08", + 6752 => x"85", + 6753 => x"98", + 6754 => x"a0", + 6755 => x"70", + 6756 => x"ae", + 6757 => x"6d", + 6758 => x"81", + 6759 => x"57", + 6760 => x"74", + 6761 => x"38", + 6762 => x"81", + 6763 => x"81", + 6764 => x"52", + 6765 => x"c9", + 6766 => x"ec", + 6767 => x"a5", + 6768 => x"33", + 6769 => x"54", + 6770 => x"3f", + 6771 => x"08", + 6772 => x"38", + 6773 => x"76", + 6774 => x"05", + 6775 => x"39", + 6776 => x"08", + 6777 => x"15", + 6778 => x"ff", + 6779 => x"73", + 6780 => x"38", + 6781 => x"83", + 6782 => x"56", + 6783 => x"75", + 6784 => x"81", + 6785 => x"33", + 6786 => x"2e", + 6787 => x"52", + 6788 => x"51", + 6789 => x"3f", + 6790 => x"08", + 6791 => x"ff", + 6792 => x"38", + 6793 => x"88", + 6794 => x"8a", + 6795 => x"38", + 6796 => x"ec", + 6797 => x"75", + 6798 => x"74", + 6799 => x"73", + 6800 => x"05", + 6801 => x"17", + 6802 => x"70", + 6803 => x"34", + 6804 => x"70", + 6805 => x"ff", + 6806 => x"55", + 6807 => x"26", + 6808 => x"8b", + 6809 => x"86", + 6810 => x"e5", + 6811 => x"38", + 6812 => x"99", + 6813 => x"05", + 6814 => x"70", + 6815 => x"73", + 6816 => x"81", + 6817 => x"ff", + 6818 => x"ed", + 6819 => x"80", + 6820 => x"91", + 6821 => x"55", + 6822 => x"3f", + 6823 => x"08", + 6824 => x"ec", + 6825 => x"38", + 6826 => x"51", + 6827 => x"3f", + 6828 => x"08", + 6829 => x"ec", + 6830 => x"76", + 6831 => x"67", + 6832 => x"34", + 6833 => x"82", + 6834 => x"84", + 6835 => x"06", + 6836 => x"80", + 6837 => x"2e", + 6838 => x"81", + 6839 => x"ff", + 6840 => x"82", + 6841 => x"54", + 6842 => x"08", + 6843 => x"53", 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x"64", + 7843 => x"2f", + 7844 => x"25", + 7845 => x"64", + 7846 => x"2e", + 7847 => x"64", + 7848 => x"6f", + 7849 => x"6f", + 7850 => x"67", + 7851 => x"74", + 7852 => x"00", + 7853 => x"28", + 7854 => x"6d", + 7855 => x"43", + 7856 => x"6e", + 7857 => x"29", + 7858 => x"0a", + 7859 => x"69", + 7860 => x"20", + 7861 => x"6c", + 7862 => x"6e", + 7863 => x"3a", + 7864 => x"20", + 7865 => x"42", + 7866 => x"52", + 7867 => x"20", + 7868 => x"38", + 7869 => x"30", + 7870 => x"2e", + 7871 => x"20", + 7872 => x"44", + 7873 => x"20", + 7874 => x"20", + 7875 => x"38", + 7876 => x"30", + 7877 => x"2e", + 7878 => x"20", + 7879 => x"4e", + 7880 => x"42", + 7881 => x"20", + 7882 => x"38", + 7883 => x"30", + 7884 => x"2e", + 7885 => x"20", + 7886 => x"52", + 7887 => x"20", + 7888 => x"20", + 7889 => x"38", + 7890 => x"30", + 7891 => x"2e", + 7892 => x"20", + 7893 => x"41", + 7894 => x"20", + 7895 => x"20", + 7896 => x"38", + 7897 => x"30", + 7898 => x"2e", + 7899 => x"20", + 7900 => x"44", + 7901 => x"52", + 7902 => x"20", + 7903 => x"76", + 7904 => x"73", + 7905 => x"30", + 7906 => x"2e", + 7907 => x"20", + 7908 => x"49", + 7909 => x"31", + 7910 => x"20", + 7911 => x"6d", + 7912 => x"20", + 7913 => x"30", + 7914 => x"2e", + 7915 => x"20", + 7916 => x"4e", + 7917 => x"43", + 7918 => x"20", + 7919 => x"61", + 7920 => x"6c", + 7921 => x"30", + 7922 => x"2e", + 7923 => x"20", + 7924 => x"49", + 7925 => x"4f", + 7926 => x"42", + 7927 => x"00", + 7928 => x"20", + 7929 => x"42", + 7930 => x"43", + 7931 => x"20", + 7932 => x"4f", + 7933 => x"0a", + 7934 => x"20", + 7935 => x"53", + 7936 => x"00", + 7937 => x"20", + 7938 => x"50", + 7939 => x"00", + 7940 => x"64", + 7941 => x"73", + 7942 => x"3a", + 7943 => x"20", + 7944 => x"50", + 7945 => x"65", + 7946 => x"20", + 7947 => x"74", + 7948 => x"41", + 7949 => x"65", + 7950 => x"3d", + 7951 => x"38", + 7952 => x"00", + 7953 => x"20", + 7954 => x"50", + 7955 => x"65", + 7956 => x"79", + 7957 => x"61", + 7958 => x"41", + 7959 => x"65", + 7960 => x"3d", + 7961 => x"38", + 7962 => x"00", + 7963 => x"20", + 7964 => x"74", + 7965 => x"20", + 7966 => x"72", + 7967 => x"64", + 7968 => x"73", + 7969 => x"20", + 7970 => x"3d", + 7971 => x"38", + 7972 => x"00", + 7973 => x"69", + 7974 => x"0a", + 7975 => x"20", + 7976 => x"50", + 7977 => x"64", + 7978 => x"20", + 7979 => x"20", + 7980 => x"20", + 7981 => x"20", + 7982 => x"3d", + 7983 => x"34", + 7984 => x"00", + 7985 => x"20", + 7986 => x"79", + 7987 => x"6d", + 7988 => x"6f", + 7989 => x"46", + 7990 => x"20", + 7991 => x"20", + 7992 => x"3d", + 7993 => x"2e", + 7994 => x"64", + 7995 => x"0a", + 7996 => x"20", + 7997 => x"44", + 7998 => x"20", + 7999 => x"63", + 8000 => x"72", + 8001 => x"20", + 8002 => x"20", + 8003 => x"3d", + 8004 => x"2e", + 8005 => x"64", + 8006 => x"0a", + 8007 => x"20", + 8008 => x"69", + 8009 => x"6f", + 8010 => x"53", + 8011 => x"4d", + 8012 => x"6f", + 8013 => x"46", + 8014 => x"3d", + 8015 => x"2e", + 8016 => x"64", + 8017 => x"0a", + 8018 => x"6d", + 8019 => x"00", + 8020 => x"65", + 8021 => x"6d", + 8022 => x"6c", + 8023 => x"00", + 8024 => x"56", + 8025 => x"56", + 8026 => x"6e", + 8027 => x"6e", + 8028 => x"77", + 8029 => x"00", + 8030 => x"00", + 8031 => x"00", + 8032 => x"00", + 8033 => x"00", + 8034 => x"00", + 8035 => x"00", + 8036 => x"00", + 8037 => x"00", + 8038 => x"00", + 8039 => x"00", + 8040 => x"00", + 8041 => x"00", + 8042 => x"00", + 8043 => x"00", + 8044 => x"00", + 8045 => x"00", + 8046 => x"00", + 8047 => x"00", + 8048 => x"00", + 8049 => x"00", + 8050 => x"00", + 8051 => x"00", + 8052 => x"00", + 8053 => x"00", + 8054 => x"00", + 8055 => x"00", + 8056 => x"00", + 8057 => x"00", + 8058 => x"00", + 8059 => x"00", + 8060 => x"00", + 8061 => x"00", + 8062 => x"00", + 8063 => x"00", + 8064 => x"00", + 8065 => x"00", + 8066 => x"00", + 8067 => x"00", + 8068 => x"00", + 8069 => x"00", + 8070 => x"00", + 8071 => x"00", + 8072 => x"00", + 8073 => x"00", + 8074 => x"00", + 8075 => x"00", + 8076 => x"00", + 8077 => x"00", + 8078 => x"00", + 8079 => x"00", + 8080 => x"00", + 8081 => x"00", + 8082 => x"00", + 8083 => x"00", + 8084 => x"00", + 8085 => x"00", + 8086 => x"00", + 8087 => x"00", + 8088 => x"00", + 8089 => x"00", + 8090 => x"00", + 8091 => x"00", + 8092 => x"00", + 8093 => x"00", + 8094 => x"00", + 8095 => x"5b", + 8096 => x"5b", + 8097 => x"5b", + 8098 => x"5b", + 8099 => x"5b", + 8100 => x"5b", + 8101 => x"5b", + 8102 => x"30", + 8103 => x"5b", + 8104 => x"5b", + 8105 => x"5b", + 8106 => x"00", + 8107 => x"00", + 8108 => x"00", + 8109 => x"00", + 8110 => x"00", + 8111 => x"00", + 8112 => x"00", + 8113 => x"00", + 8114 => x"00", + 8115 => x"00", + 8116 => x"00", + 8117 => x"69", + 8118 => x"72", + 8119 => x"69", + 8120 => x"00", + 8121 => x"00", + 8122 => x"30", + 8123 => x"20", + 8124 => x"00", + 8125 => x"61", + 8126 => x"64", + 8127 => x"20", + 8128 => x"65", + 8129 => x"68", + 8130 => x"69", + 8131 => x"72", + 8132 => x"69", + 8133 => x"74", + 8134 => x"4f", + 8135 => x"00", + 8136 => x"61", + 8137 => x"74", + 8138 => x"65", + 8139 => x"72", + 8140 => x"65", + 8141 => x"73", + 8142 => x"79", + 8143 => x"6c", + 8144 => x"64", + 8145 => x"62", + 8146 => x"67", + 8147 => x"00", + 8148 => x"44", + 8149 => x"2a", + 8150 => x"3b", + 8151 => x"3f", + 8152 => x"7f", + 8153 => x"41", + 8154 => x"41", + 8155 => x"00", + 8156 => x"fe", + 8157 => x"44", + 8158 => x"2e", + 8159 => x"4f", + 8160 => x"4d", + 8161 => x"20", + 8162 => x"54", + 8163 => x"20", + 8164 => x"4f", + 8165 => x"4d", + 8166 => x"20", + 8167 => x"54", + 8168 => x"20", + 8169 => x"00", + 8170 => x"00", + 8171 => x"00", + 8172 => x"00", + 8173 => x"9a", + 8174 => x"41", + 8175 => x"45", + 8176 => x"49", + 8177 => x"92", + 8178 => x"4f", + 8179 => x"99", + 8180 => x"9d", + 8181 => x"49", + 8182 => x"a5", + 8183 => x"a9", + 8184 => x"ad", + 8185 => x"b1", + 8186 => x"b5", + 8187 => x"b9", + 8188 => x"bd", + 8189 => x"c1", + 8190 => x"c5", + 8191 => x"c9", + 8192 => x"cd", + 8193 => x"d1", + 8194 => x"d5", + 8195 => x"d9", + 8196 => x"dd", + 8197 => x"e1", + 8198 => x"e5", + 8199 => x"e9", + 8200 => x"ed", + 8201 => x"f1", + 8202 => x"f5", + 8203 => x"f9", + 8204 => x"fd", + 8205 => x"2e", + 8206 => x"5b", + 8207 => x"22", + 8208 => x"3e", + 8209 => x"00", + 8210 => x"01", + 8211 => x"10", + 8212 => x"00", + 8213 => x"00", + 8214 => x"01", + 8215 => x"04", + 8216 => x"10", + 8217 => x"00", + 8218 => x"00", + 8219 => x"00", + 8220 => x"02", + 8221 => x"00", + 8222 => x"00", + 8223 => x"00", + 8224 => x"04", + 8225 => x"00", + 8226 => x"00", + 8227 => x"00", + 8228 => x"14", + 8229 => x"00", + 8230 => x"00", + 8231 => x"00", + 8232 => x"2b", + 8233 => x"00", + 8234 => x"00", + 8235 => x"00", + 8236 => x"30", + 8237 => x"00", + 8238 => x"00", + 8239 => x"00", + 8240 => x"3c", + 8241 => x"00", + 8242 => x"00", + 8243 => x"00", + 8244 => x"3d", + 8245 => x"00", + 8246 => x"00", + 8247 => x"00", + 8248 => x"3f", + 8249 => x"00", + 8250 => x"00", + 8251 => x"00", + 8252 => x"40", + 8253 => x"00", + 8254 => x"00", + 8255 => x"00", + 8256 => x"41", + 8257 => x"00", + 8258 => x"00", + 8259 => x"00", + 8260 => x"42", + 8261 => x"00", + 8262 => x"00", + 8263 => x"00", + 8264 => x"43", + 8265 => x"00", + 8266 => x"00", + 8267 => x"00", + 8268 => x"50", + 8269 => x"00", + 8270 => x"00", + 8271 => x"00", + 8272 => x"51", + 8273 => x"00", + 8274 => x"00", + 8275 => x"00", + 8276 => x"54", + 8277 => x"00", + 8278 => x"00", + 8279 => x"00", + 8280 => x"55", + 8281 => x"00", + 8282 => x"00", + 8283 => x"00", + 8284 => x"79", + 8285 => x"00", + 8286 => x"00", + 8287 => x"00", + 8288 => x"78", + 8289 => x"00", + 8290 => x"00", + 8291 => x"00", + 8292 => x"82", + 8293 => x"00", + 8294 => x"00", + 8295 => x"00", + 8296 => x"83", + 8297 => x"00", + 8298 => x"00", + 8299 => x"00", + 8300 => x"85", + 8301 => x"00", + 8302 => x"00", + 8303 => x"00", + 8304 => x"87", + 8305 => x"00", + 8306 => x"00", + 8307 => x"00", + 8308 => x"8c", + 8309 => x"00", + 8310 => x"00", + 8311 => x"00", + 8312 => x"8d", + 8313 => x"00", + 8314 => x"00", + 8315 => x"00", + 8316 => x"8e", + 8317 => x"00", + 8318 => x"00", + 8319 => x"00", + 8320 => x"8f", + 8321 => x"00", + 8322 => x"00", + 8323 => x"00", + 8324 => x"00", + 8325 => x"00", + 8326 => x"00", + 8327 => x"00", + 8328 => x"01", + 8329 => x"00", + 8330 => x"01", + 8331 => x"81", + 8332 => x"00", + 8333 => x"7f", + 8334 => x"00", + 8335 => x"00", + 8336 => x"00", + 8337 => x"00", + 8338 => x"f5", + 8339 => x"f5", + 8340 => x"f5", + 8341 => x"00", + 8342 => x"01", + 8343 => x"01", + 8344 => x"01", + 8345 => x"00", + 8346 => x"00", + 8347 => x"00", + 8348 => x"00", + 8349 => x"00", + 8350 => x"00", + 8351 => x"00", + 8352 => x"00", + 8353 => x"00", + 8354 => x"00", + 8355 => x"00", + 8356 => x"00", + 8357 => x"00", + 8358 => x"00", + 8359 => x"00", + 8360 => x"00", + 8361 => x"00", + 8362 => x"00", + 8363 => x"00", + 8364 => x"00", + 8365 => x"00", + 8366 => x"00", + 8367 => x"00", + 8368 => x"00", + 8369 => x"00", + 8370 => x"00", + 8371 => x"00", + 8372 => x"00", + 8373 => x"00", + 8374 => x"00", + 8375 => x"00", + 8376 => x"00", + 8377 => x"00", + 8378 => x"00", + others => X"00" + ); + + shared variable RAM3 : ramArray := + ( + 0 => x"0b", + 1 => x"f8", + 2 => x"0b", + 3 => x"00", + 4 => x"00", + 5 => x"00", + 6 => x"00", + 7 => x"00", + 8 => x"88", + 9 => x"90", + 10 => x"08", + 11 => x"8c", + 12 => x"04", + 13 => x"00", + 14 => x"00", + 15 => x"00", + 16 => x"71", + 17 => x"72", + 18 => x"81", + 19 => x"83", + 20 => x"ff", + 21 => x"04", + 22 => x"00", + 23 => x"00", + 24 => x"71", + 25 => x"83", + 26 => x"83", + 27 => x"05", + 28 => x"2b", + 29 => x"73", + 30 => x"0b", + 31 => x"83", + 32 => x"72", + 33 => x"72", + 34 => x"09", + 35 => x"73", + 36 => x"07", + 37 => x"53", + 38 => x"00", + 39 => x"00", + 40 => x"72", + 41 => x"73", + 42 => x"51", + 43 => x"00", + 44 => x"00", + 45 => x"00", + 46 => x"00", + 47 => x"00", + 48 => x"71", + 49 => x"71", + 50 => x"09", + 51 => x"0a", + 52 => x"0a", + 53 => x"05", + 54 => x"51", + 55 => x"04", + 56 => x"72", + 57 => x"73", + 58 => x"51", + 59 => x"00", + 60 => x"00", + 61 => x"00", + 62 => x"00", + 63 => x"00", + 64 => x"00", + 65 => x"00", + 66 => x"00", + 67 => x"00", + 68 => x"00", + 69 => x"00", + 70 => x"00", + 71 => x"00", + 72 => x"0b", + 73 => x"ff", + 74 => x"00", + 75 => x"00", + 76 => x"00", + 77 => x"00", + 78 => x"00", + 79 => x"00", + 80 => x"72", + 81 => x"0a", + 82 => x"00", + 83 => x"00", + 84 => x"00", + 85 => x"00", + 86 => x"00", + 87 => x"00", + 88 => x"72", + 89 => x"09", + 90 => x"0b", + 91 => x"05", + 92 => x"00", + 93 => x"00", + 94 => x"00", + 95 => x"00", + 96 => x"72", + 97 => x"73", + 98 => x"09", + 99 => x"81", + 100 => x"06", + 101 => x"04", + 102 => x"00", + 103 => x"00", + 104 => x"71", + 105 => x"04", + 106 => x"06", + 107 => x"82", + 108 => x"0b", + 109 => x"fc", + 110 => x"51", + 111 => x"00", + 112 => x"72", + 113 => x"72", + 114 => x"81", + 115 => x"0a", + 116 => x"51", + 117 => x"00", + 118 => x"00", + 119 => x"00", + 120 => x"72", + 121 => x"72", + 122 => x"81", + 123 => x"0a", + 124 => x"53", + 125 => x"00", + 126 => x"00", + 127 => x"00", + 128 => x"71", + 129 => x"52", + 130 => x"00", + 131 => x"00", + 132 => x"00", + 133 => x"00", + 134 => x"00", + 135 => x"00", + 136 => x"72", + 137 => x"05", + 138 => x"04", + 139 => x"00", + 140 => x"00", + 141 => x"00", + 142 => x"00", + 143 => x"00", + 144 => x"72", + 145 => x"73", + 146 => x"07", + 147 => x"00", + 148 => x"00", + 149 => x"00", + 150 => x"00", + 151 => x"00", + 152 => x"71", + 153 => x"72", + 154 => x"81", + 155 => x"10", + 156 => x"81", + 157 => x"04", + 158 => x"00", + 159 => x"00", + 160 => x"71", + 161 => x"0b", + 162 => x"fc", + 163 => x"10", + 164 => x"06", + 165 => x"92", + 166 => x"00", + 167 => x"00", + 168 => x"88", + 169 => x"90", + 170 => x"0b", + 171 => x"fb", + 172 => x"88", + 173 => x"0c", + 174 => x"0c", + 175 => x"00", + 176 => x"88", + 177 => x"90", + 178 => x"0b", + 179 => x"e7", + 180 => x"88", + 181 => x"0c", + 182 => x"0c", + 183 => x"00", + 184 => x"72", + 185 => x"05", + 186 => x"81", + 187 => x"70", + 188 => x"73", + 189 => x"05", + 190 => x"07", + 191 => x"04", + 192 => x"72", + 193 => x"05", + 194 => x"09", + 195 => x"05", + 196 => x"06", + 197 => x"74", + 198 => x"06", + 199 => x"51", + 200 => x"05", + 201 => x"00", + 202 => x"00", + 203 => x"00", + 204 => x"00", + 205 => x"00", + 206 => x"00", + 207 => x"00", + 208 => x"04", + 209 => x"00", + 210 => x"00", + 211 => x"00", + 212 => x"00", + 213 => x"00", + 214 => x"00", + 215 => x"00", + 216 => x"71", + 217 => x"04", + 218 => x"00", + 219 => x"00", + 220 => x"00", + 221 => x"00", + 222 => x"00", + 223 => x"00", + 224 => x"04", + 225 => x"00", + 226 => x"00", + 227 => x"00", + 228 => x"00", + 229 => x"00", + 230 => x"00", + 231 => x"00", + 232 => x"02", + 233 => x"10", + 234 => x"04", + 235 => x"00", + 236 => x"00", + 237 => x"00", + 238 => x"00", + 239 => x"00", + 240 => x"00", + 241 => x"00", + 242 => x"00", + 243 => x"00", + 244 => x"00", + 245 => x"00", + 246 => x"00", + 247 => x"00", + 248 => x"71", + 249 => x"05", + 250 => x"02", + 251 => x"ff", + 252 => x"ff", + 253 => x"ff", + 254 => x"ff", + 255 => x"ff", + 256 => x"00", + 257 => x"ff", + 258 => x"ff", + 259 => x"ff", + 260 => x"ff", + 261 => x"ff", + 262 => x"ff", + 263 => x"ff", + 264 => x"0b", + 265 => x"81", + 266 => x"0b", + 267 => x"0b", + 268 => x"95", + 269 => x"0b", + 270 => x"0b", + 271 => x"b5", + 272 => x"0b", + 273 => x"0b", + 274 => x"d5", + 275 => x"0b", + 276 => x"0b", + 277 => x"f5", + 278 => x"0b", + 279 => x"0b", + 280 => x"95", + 281 => x"0b", + 282 => x"0b", + 283 => x"b5", + 284 => x"0b", + 285 => x"0b", + 286 => x"d5", + 287 => x"0b", + 288 => x"0b", + 289 => x"f5", + 290 => x"0b", + 291 => x"0b", + 292 => x"93", + 293 => x"0b", + 294 => x"0b", + 295 => x"b2", + 296 => x"0b", + 297 => x"0b", + 298 => x"d2", + 299 => x"0b", + 300 => x"0b", + 301 => x"f2", + 302 => x"0b", + 303 => x"0b", + 304 => x"92", + 305 => x"0b", + 306 => x"0b", + 307 => x"b2", + 308 => x"0b", + 309 => x"0b", + 310 => x"d2", + 311 => x"0b", + 312 => x"0b", + 313 => x"f2", + 314 => x"0b", + 315 => x"0b", + 316 => x"92", + 317 => x"0b", + 318 => x"0b", + 319 => x"b2", + 320 => x"0b", + 321 => x"0b", + 322 => x"d2", + 323 => x"0b", + 324 => x"0b", + 325 => x"f2", + 326 => x"0b", + 327 => x"0b", + 328 => x"92", + 329 => x"0b", + 330 => x"0b", + 331 => x"b2", + 332 => x"0b", + 333 => x"0b", + 334 => x"d2", + 335 => x"0b", + 336 => x"0b", + 337 => x"f2", + 338 => x"0b", + 339 => x"0b", + 340 => x"91", + 341 => x"0b", + 342 => x"0b", + 343 => x"b0", + 344 => x"ff", + 345 => x"ff", + 346 => x"ff", + 347 => x"ff", + 348 => x"ff", + 349 => x"ff", + 350 => x"ff", + 351 => x"ff", + 352 => x"ff", + 353 => x"ff", + 354 => x"ff", + 355 => x"ff", + 356 => x"ff", + 357 => x"ff", + 358 => x"ff", + 359 => x"ff", + 360 => x"ff", + 361 => x"ff", + 362 => x"ff", + 363 => x"ff", + 364 => x"ff", + 365 => x"ff", + 366 => x"ff", + 367 => x"ff", + 368 => x"ff", + 369 => x"ff", + 370 => x"ff", + 371 => x"ff", + 372 => x"ff", + 373 => x"ff", + 374 => x"ff", + 375 => x"ff", + 376 => x"ff", + 377 => x"ff", + 378 => x"ff", + 379 => x"ff", + 380 => x"ff", + 381 => x"ff", + 382 => x"ff", + 383 => x"ff", + 384 => x"04", + 385 => x"04", + 386 => x"0c", + 387 => x"2d", + 388 => x"08", + 389 => x"04", + 390 => x"0c", + 391 => x"2d", + 392 => x"08", + 393 => x"04", + 394 => x"0c", + 395 => x"2d", + 396 => x"08", + 397 => x"04", + 398 => x"0c", + 399 => x"2d", + 400 => x"08", + 401 => x"04", + 402 => x"0c", + 403 => x"2d", + 404 => x"08", + 405 => x"04", + 406 => x"0c", + 407 => x"2d", + 408 => x"08", + 409 => x"04", + 410 => x"0c", + 411 => x"2d", + 412 => x"08", + 413 => x"04", + 414 => x"0c", + 415 => x"2d", + 416 => x"08", + 417 => x"04", + 418 => x"0c", + 419 => x"2d", + 420 => x"08", + 421 => x"04", + 422 => x"0c", + 423 => x"2d", + 424 => x"08", + 425 => x"04", + 426 => x"0c", + 427 => x"2d", + 428 => x"08", + 429 => x"04", + 430 => x"0c", + 431 => x"2d", + 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932 => x"85", + 933 => x"3d", + 934 => x"82", + 935 => x"fc", + 936 => x"85", + 937 => x"05", + 938 => x"ff", + 939 => x"70", + 940 => x"08", + 941 => x"06", + 942 => x"08", + 943 => x"11", + 944 => x"08", + 945 => x"82", + 946 => x"88", + 947 => x"2a", + 948 => x"08", + 949 => x"82", + 950 => x"8c", + 951 => x"82", + 952 => x"8c", + 953 => x"51", + 954 => x"85", + 955 => x"05", + 956 => x"84", + 957 => x"39", + 958 => x"08", + 959 => x"70", + 960 => x"0c", + 961 => x"0d", + 962 => x"0c", + 963 => x"f8", + 964 => x"85", + 965 => x"3d", + 966 => x"82", + 967 => x"8c", + 968 => x"82", + 969 => x"88", + 970 => x"80", + 971 => x"85", + 972 => x"82", + 973 => x"54", + 974 => x"82", + 975 => x"04", + 976 => x"08", + 977 => x"f8", + 978 => x"0d", + 979 => x"85", + 980 => x"05", + 981 => x"85", + 982 => x"05", + 983 => x"3f", + 984 => x"08", + 985 => x"ec", + 986 => x"3d", + 987 => x"f8", + 988 => x"85", + 989 => x"82", + 990 => x"fd", + 991 => x"0b", + 992 => x"08", + 993 => x"80", + 994 => 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=> x"d0", + 1113 => x"81", + 1114 => x"af", + 1115 => x"90", + 1116 => x"81", + 1117 => x"a3", + 1118 => x"c4", + 1119 => x"81", + 1120 => x"97", + 1121 => x"f0", + 1122 => x"81", + 1123 => x"8b", + 1124 => x"a0", + 1125 => x"81", + 1126 => x"ab", + 1127 => x"3d", + 1128 => x"3d", + 1129 => x"56", + 1130 => x"e7", + 1131 => x"87", + 1132 => x"51", + 1133 => x"74", + 1134 => x"ec", + 1135 => x"39", + 1136 => x"74", + 1137 => x"3f", + 1138 => x"08", + 1139 => x"fa", + 1140 => x"85", + 1141 => x"79", + 1142 => x"81", + 1143 => x"b0", + 1144 => x"3d", + 1145 => x"3d", + 1146 => x"84", + 1147 => x"05", + 1148 => x"80", + 1149 => x"81", + 1150 => x"07", + 1151 => x"57", + 1152 => x"56", + 1153 => x"26", + 1154 => x"56", + 1155 => x"70", + 1156 => x"51", + 1157 => x"74", + 1158 => x"81", + 1159 => x"8c", + 1160 => x"56", + 1161 => x"3f", + 1162 => x"08", + 1163 => x"ec", + 1164 => x"82", + 1165 => x"87", + 1166 => x"0c", + 1167 => x"08", + 1168 => x"d4", + 1169 => x"80", + 1170 => x"75", + 1171 => x"d6", + 1172 => x"ec", + 1173 => x"85", + 1174 => x"38", + 1175 => x"80", + 1176 => x"74", + 1177 => x"59", + 1178 => x"96", + 1179 => x"51", + 1180 => x"3f", + 1181 => x"05", + 1182 => x"80", + 1183 => x"81", + 1184 => x"2a", + 1185 => x"57", + 1186 => x"80", + 1187 => x"81", + 1188 => x"87", + 1189 => x"08", + 1190 => x"fe", + 1191 => x"56", + 1192 => x"ec", + 1193 => x"0d", + 1194 => x"0d", + 1195 => x"05", + 1196 => x"57", + 1197 => x"80", + 1198 => x"79", + 1199 => x"3f", + 1200 => x"08", + 1201 => x"80", + 1202 => x"75", + 1203 => x"38", + 1204 => x"55", + 1205 => x"85", + 1206 => x"52", + 1207 => x"2d", + 1208 => x"08", + 1209 => x"77", + 1210 => x"85", + 1211 => x"3d", + 1212 => x"3d", + 1213 => x"63", + 1214 => x"80", + 1215 => x"73", + 1216 => x"41", + 1217 => x"5e", + 1218 => x"52", + 1219 => x"51", + 1220 => x"81", + 1221 => x"a8", + 1222 => x"55", + 1223 => x"80", + 1224 => x"90", + 1225 => x"7b", + 1226 => x"38", + 1227 => x"74", + 1228 => x"7a", + 1229 => x"72", + 1230 => x"ee", + 1231 => x"9e", + 1232 => x"81", + 1233 => x"a8", + 1234 => x"15", + 1235 => x"74", + 1236 => x"7a", + 1237 => x"72", + 1238 => x"ee", + 1239 => x"fe", + 1240 => x"81", + 1241 => x"a8", + 1242 => x"15", + 1243 => x"74", + 1244 => x"7a", + 1245 => x"72", + 1246 => x"ef", + 1247 => x"de", + 1248 => x"81", + 1249 => x"a7", + 1250 => x"15", + 1251 => x"a7", + 1252 => x"88", + 1253 => x"94", + 1254 => x"3f", + 1255 => x"79", + 1256 => x"74", + 1257 => x"55", + 1258 => x"72", + 1259 => x"38", + 1260 => x"53", + 1261 => x"83", + 1262 => x"75", + 1263 => x"81", + 1264 => x"53", + 1265 => x"8b", + 1266 => x"fe", + 1267 => x"73", + 1268 => x"a0", + 1269 => x"3f", + 1270 => x"c2", + 1271 => x"98", + 1272 => x"3f", + 1273 => x"1c", + 1274 => x"fb", + 1275 => x"ec", + 1276 => x"70", + 1277 => x"57", + 1278 => x"09", + 1279 => x"38", + 1280 => x"82", + 1281 => x"98", + 1282 => x"2c", + 1283 => x"70", + 1284 => x"72", + 1285 => x"09", + 1286 => x"72", + 1287 => x"07", + 1288 => x"58", + 1289 => x"57", + 1290 => x"d4", + 1291 => x"2e", + 1292 => x"85", + 1293 => x"8c", + 1294 => x"53", + 1295 => x"fd", + 1296 => x"53", + 1297 => x"ec", + 1298 => x"0d", + 1299 => x"0d", + 1300 => x"33", + 1301 => x"53", + 1302 => x"52", + 1303 => x"3f", + 1304 => x"22", + 1305 => x"3f", + 1306 => x"54", + 1307 => x"53", + 1308 => x"33", + 1309 => x"c0", + 1310 => x"3f", + 1311 => x"84", + 1312 => x"3f", + 1313 => x"04", + 1314 => x"87", + 1315 => x"08", + 1316 => x"3f", + 1317 => x"eb", + 1318 => x"dc", + 1319 => x"3f", + 1320 => x"df", + 1321 => x"2a", + 1322 => x"51", + 1323 => x"2e", + 1324 => x"51", + 1325 => x"81", + 1326 => x"98", + 1327 => x"51", + 1328 => x"72", + 1329 => x"81", + 1330 => x"71", + 1331 => x"38", + 1332 => x"af", + 1333 => x"88", + 1334 => x"3f", + 1335 => x"a3", + 1336 => x"2a", + 1337 => x"51", + 1338 => x"2e", + 1339 => x"51", + 1340 => x"81", + 1341 => x"98", + 1342 => x"51", + 1343 => x"72", + 1344 => x"81", + 1345 => x"71", + 1346 => x"38", + 1347 => x"f3", + 1348 => x"ac", + 1349 => x"3f", + 1350 => x"e7", + 1351 => x"2a", + 1352 => x"51", + 1353 => x"2e", + 1354 => x"51", + 1355 => x"81", + 1356 => x"97", + 1357 => x"51", + 1358 => x"72", + 1359 => x"81", + 1360 => x"71", + 1361 => x"38", + 1362 => x"b7", + 1363 => x"d4", + 1364 => x"3f", + 1365 => x"ab", + 1366 => x"2a", + 1367 => x"51", + 1368 => x"2e", + 1369 => x"51", + 1370 => x"81", + 1371 => x"97", + 1372 => x"51", + 1373 => x"72", + 1374 => x"81", + 1375 => x"71", + 1376 => x"38", + 1377 => x"fb", + 1378 => x"fc", + 1379 => x"3f", + 1380 => x"ef", + 1381 => x"3f", + 1382 => x"04", + 1383 => x"77", + 1384 => x"a3", + 1385 => x"55", + 1386 => x"52", + 1387 => x"c0", + 1388 => x"82", + 1389 => x"54", + 1390 => x"81", + 1391 => x"bc", + 1392 => x"cc", + 1393 => x"f7", + 1394 => x"ec", + 1395 => x"05", + 1396 => x"ec", + 1397 => x"25", + 1398 => x"51", + 1399 => x"0b", + 1400 => x"e8", + 1401 => x"82", + 1402 => x"54", + 1403 => x"09", + 1404 => x"38", + 1405 => x"53", + 1406 => x"51", + 1407 => x"3f", + 1408 => x"08", + 1409 => x"38", + 1410 => x"08", + 1411 => x"3f", + 1412 => x"9c", + 1413 => x"8b", + 1414 => x"0b", + 1415 => x"80", + 1416 => x"0b", + 1417 => x"33", + 1418 => x"2e", + 1419 => x"8c", + 1420 => x"cc", + 1421 => x"75", + 1422 => x"3f", + 1423 => x"85", + 1424 => x"3d", + 1425 => x"3d", + 1426 => x"71", + 1427 => x"0c", + 1428 => x"52", + 1429 => x"cd", + 1430 => x"85", + 1431 => x"ff", + 1432 => x"7d", + 1433 => x"06", + 1434 => x"f1", + 1435 => x"3d", + 1436 => x"a7", + 1437 => x"53", + 1438 => x"86", + 1439 => x"fc", + 1440 => x"85", + 1441 => x"2e", + 1442 => x"f1", + 1443 => x"8a", + 1444 => x"5f", + 1445 => x"90", + 1446 => x"3f", + 1447 => x"46", + 1448 => x"52", + 1449 => x"f4", + 1450 => x"ff", + 1451 => x"f3", + 1452 => x"85", + 1453 => x"2b", + 1454 => x"51", + 1455 => x"c2", + 1456 => x"38", + 1457 => x"24", + 1458 => x"bd", + 1459 => x"38", + 1460 => x"90", + 1461 => x"2e", + 1462 => x"78", + 1463 => x"da", + 1464 => x"39", + 1465 => x"2e", + 1466 => x"78", + 1467 => x"85", + 1468 => x"bf", + 1469 => x"38", + 1470 => x"78", + 1471 => x"89", + 1472 => x"80", + 1473 => x"38", + 1474 => x"2e", + 1475 => x"78", + 1476 => x"89", + 1477 => x"86", + 1478 => x"83", + 1479 => x"38", + 1480 => x"24", + 1481 => x"81", + 1482 => x"d3", + 1483 => x"39", + 1484 => x"2e", + 1485 => x"89", + 1486 => x"3d", + 1487 => x"53", + 1488 => x"51", + 1489 => x"82", + 1490 => x"80", + 1491 => x"38", + 1492 => x"fc", + 1493 => x"84", + 1494 => x"fa", + 1495 => x"ec", + 1496 => x"fe", + 1497 => x"3d", + 1498 => x"53", + 1499 => x"51", + 1500 => x"82", + 1501 => x"86", + 1502 => x"ec", + 1503 => x"f2", + 1504 => x"ea", + 1505 => x"5c", + 1506 => x"27", + 1507 => x"61", + 1508 => x"70", + 1509 => x"0c", + 1510 => x"f5", + 1511 => x"39", + 1512 => x"80", + 1513 => x"84", + 1514 => x"aa", + 1515 => x"ec", + 1516 => x"fd", + 1517 => x"3d", + 1518 => x"53", + 1519 => x"51", + 1520 => x"82", + 1521 => x"80", + 1522 => x"38", + 1523 => x"f8", + 1524 => x"84", + 1525 => x"fe", + 1526 => x"ec", + 1527 => x"fd", + 1528 => x"f2", + 1529 => x"86", + 1530 => x"79", + 1531 => x"87", + 1532 => x"79", + 1533 => x"5b", + 1534 => x"61", + 1535 => x"eb", + 1536 => x"ff", + 1537 => x"ff", + 1538 => x"a6", + 1539 => x"85", + 1540 => x"2e", + 1541 => x"b4", + 1542 => x"11", + 1543 => x"05", + 1544 => x"3f", + 1545 => x"08", + 1546 => x"e9", + 1547 => x"fe", + 1548 => x"ff", + 1549 => x"a6", + 1550 => x"85", + 1551 => x"2e", + 1552 => x"81", + 1553 => x"9e", + 1554 => x"5a", + 1555 => x"a7", + 1556 => x"33", + 1557 => x"5a", + 1558 => x"2e", + 1559 => x"55", + 1560 => x"33", + 1561 => x"81", + 1562 => x"a3", + 1563 => x"1a", + 1564 => x"43", + 1565 => x"81", + 1566 => x"82", + 1567 => x"3d", + 1568 => x"53", + 1569 => x"51", + 1570 => x"82", + 1571 => x"80", + 1572 => x"84", + 1573 => x"78", + 1574 => x"38", + 1575 => x"08", + 1576 => x"39", + 1577 => x"33", + 1578 => x"2e", + 1579 => x"84", + 1580 => x"bc", + 1581 => x"da", + 1582 => x"80", + 1583 => x"82", + 1584 => x"44", + 1585 => x"84", + 1586 => x"78", + 1587 => x"38", + 1588 => x"08", + 1589 => x"82", + 1590 => x"59", + 1591 => x"88", + 1592 => x"b0", + 1593 => x"39", + 1594 => x"08", + 1595 => x"44", + 1596 => x"fc", + 1597 => x"84", + 1598 => x"da", + 1599 => x"ec", + 1600 => x"38", + 1601 => x"33", + 1602 => x"2e", + 1603 => x"84", + 1604 => x"80", + 1605 => x"84", + 1606 => x"78", + 1607 => x"38", + 1608 => x"08", + 1609 => x"82", + 1610 => x"59", + 1611 => x"88", + 1612 => x"a4", + 1613 => x"39", + 1614 => x"33", + 1615 => x"2e", + 1616 => x"84", + 1617 => x"99", + 1618 => x"d6", + 1619 => x"80", + 1620 => x"82", + 1621 => x"43", + 1622 => x"84", + 1623 => x"05", + 1624 => x"fe", + 1625 => x"ff", + 1626 => x"a3", + 1627 => x"85", + 1628 => x"2e", + 1629 => x"62", + 1630 => x"88", + 1631 => x"81", + 1632 => x"32", + 1633 => x"05", + 1634 => x"9f", + 1635 => x"06", + 1636 => x"5a", + 1637 => x"88", + 1638 => x"2e", + 1639 => x"42", + 1640 => x"51", + 1641 => x"a0", + 1642 => x"61", + 1643 => x"63", + 1644 => x"3f", + 1645 => x"51", + 1646 => x"f9", + 1647 => x"3d", + 1648 => x"53", + 1649 => x"51", + 1650 => x"82", + 1651 => x"80", + 1652 => x"38", + 1653 => x"fc", + 1654 => x"84", + 1655 => x"f6", + 1656 => x"ec", + 1657 => x"a4", + 1658 => x"02", + 1659 => x"33", + 1660 => x"81", + 1661 => x"3d", + 1662 => x"53", + 1663 => x"51", + 1664 => x"82", + 1665 => x"e1", + 1666 => x"39", + 1667 => x"54", + 1668 => x"f8", + 1669 => x"3f", + 1670 => x"79", + 1671 => x"3f", + 1672 => x"33", + 1673 => x"2e", + 1674 => x"9f", + 1675 => x"38", + 1676 => x"fc", + 1677 => x"84", + 1678 => x"9a", + 1679 => x"ec", + 1680 => x"91", + 1681 => x"02", + 1682 => x"33", + 1683 => x"81", + 1684 => x"b8", + 1685 => x"84", + 1686 => x"3f", + 1687 => x"b4", + 1688 => x"11", + 1689 => x"05", + 1690 => x"3f", + 1691 => x"08", + 1692 => x"a1", + 1693 => x"fe", + 1694 => x"ff", + 1695 => x"a3", + 1696 => x"85", + 1697 => x"2e", + 1698 => x"59", + 1699 => x"22", + 1700 => x"05", + 1701 => x"41", + 1702 => x"f0", + 1703 => x"84", + 1704 => x"ae", + 1705 => x"ec", + 1706 => x"f7", + 1707 => x"70", + 1708 => x"81", + 1709 => x"9f", + 1710 => x"f8", + 1711 => x"9f", + 1712 => x"45", + 1713 => x"78", + 1714 => x"c9", + 1715 => x"26", + 1716 => x"82", + 1717 => x"39", + 1718 => x"f0", + 1719 => x"84", + 1720 => x"ee", + 1721 => x"ec", + 1722 => x"92", + 1723 => x"02", + 1724 => x"79", + 1725 => x"5b", + 1726 => x"ff", + 1727 => x"f3", + 1728 => x"ea", + 1729 => x"39", + 1730 => x"f4", + 1731 => x"84", + 1732 => x"be", + 1733 => x"ec", + 1734 => x"f6", + 1735 => x"3d", + 1736 => x"53", + 1737 => x"51", + 1738 => x"82", + 1739 => x"80", + 1740 => x"60", + 1741 => x"59", + 1742 => x"41", + 1743 => x"f0", + 1744 => x"84", + 1745 => x"8a", + 1746 => x"ec", + 1747 => x"f6", + 1748 => x"70", + 1749 => x"81", + 1750 => x"9e", + 1751 => x"f8", + 1752 => x"9e", + 1753 => x"45", + 1754 => x"78", + 1755 => x"a5", + 1756 => x"27", + 1757 => x"3d", + 1758 => x"53", + 1759 => x"51", + 1760 => x"82", + 1761 => x"80", + 1762 => x"60", + 1763 => x"59", + 1764 => x"41", + 1765 => x"81", + 1766 => x"97", + 1767 => x"b2", + 1768 => x"ff", + 1769 => x"ff", + 1770 => x"9f", + 1771 => x"85", + 1772 => x"2e", + 1773 => x"63", + 1774 => x"a4", + 1775 => x"3f", + 1776 => x"04", + 1777 => x"80", + 1778 => x"84", + 1779 => x"86", + 1780 => x"ec", + 1781 => x"f5", + 1782 => x"52", + 1783 => x"51", + 1784 => x"63", + 1785 => x"82", + 1786 => x"80", + 1787 => x"38", + 1788 => x"08", + 1789 => x"dc", + 1790 => x"3f", + 1791 => x"81", + 1792 => x"96", + 1793 => x"96", + 1794 => x"39", + 1795 => x"51", + 1796 => x"80", + 1797 => x"39", + 1798 => x"f4", + 1799 => x"45", + 1800 => x"78", + 1801 => x"ed", + 1802 => x"06", + 1803 => x"2e", + 1804 => x"b4", + 1805 => x"05", + 1806 => x"3f", + 1807 => x"08", + 1808 => x"7a", + 1809 => x"38", + 1810 => x"89", + 1811 => x"2e", + 1812 => x"ca", + 1813 => x"2e", + 1814 => x"c2", + 1815 => x"a8", + 1816 => x"81", + 1817 => x"80", + 1818 => x"b0", + 1819 => x"ff", + 1820 => x"9b", + 1821 => x"39", + 1822 => x"52", + 1823 => x"b0", + 1824 => x"f0", + 1825 => x"7b", + 1826 => x"ac", + 1827 => x"81", + 1828 => x"b4", + 1829 => x"05", + 1830 => x"3f", + 1831 => x"54", + 1832 => x"f4", + 1833 => x"3d", + 1834 => x"51", + 1835 => x"82", + 1836 => x"82", + 1837 => x"80", + 1838 => x"80", + 1839 => x"80", + 1840 => x"80", + 1841 => x"ff", + 1842 => x"eb", + 1843 => x"85", + 1844 => x"85", + 1845 => x"70", + 1846 => x"70", + 1847 => x"25", + 1848 => x"5f", + 1849 => x"83", + 1850 => x"81", + 1851 => x"06", + 1852 => x"2e", + 1853 => x"1b", + 1854 => x"06", + 1855 => x"fe", + 1856 => x"81", + 1857 => x"32", + 1858 => x"8a", + 1859 => x"2e", + 1860 => x"f3", + 1861 => x"f4", + 1862 => x"c2", + 1863 => x"39", + 1864 => x"80", + 1865 => x"fc", + 1866 => x"94", + 1867 => x"54", + 1868 => x"80", + 1869 => x"e3", + 1870 => x"85", + 1871 => x"2b", + 1872 => x"53", + 1873 => x"52", + 1874 => x"c1", + 1875 => x"85", + 1876 => x"75", + 1877 => x"94", + 1878 => x"54", + 1879 => x"80", + 1880 => x"e3", + 1881 => x"85", + 1882 => x"2b", + 1883 => x"53", + 1884 => x"52", + 1885 => x"95", + 1886 => x"85", + 1887 => x"75", + 1888 => x"83", + 1889 => x"94", + 1890 => x"80", + 1891 => x"c0", + 1892 => x"80", + 1893 => x"82", + 1894 => x"80", + 1895 => x"82", + 1896 => x"89", + 1897 => x"d7", + 1898 => x"e4", + 1899 => x"3f", + 1900 => x"51", + 1901 => x"a9", + 1902 => x"be", + 1903 => x"ed", + 1904 => x"82", + 1905 => x"fe", + 1906 => x"52", + 1907 => x"88", + 1908 => x"c4", + 1909 => x"ec", + 1910 => x"06", + 1911 => x"14", + 1912 => x"80", + 1913 => x"71", + 1914 => x"0c", + 1915 => x"04", + 1916 => x"76", + 1917 => x"55", + 1918 => x"54", + 1919 => x"81", + 1920 => x"33", + 1921 => x"2e", + 1922 => x"86", + 1923 => x"53", + 1924 => x"33", + 1925 => x"2e", + 1926 => x"86", + 1927 => x"53", + 1928 => x"52", + 1929 => x"09", + 1930 => x"38", + 1931 => x"12", + 1932 => x"33", + 1933 => x"a2", + 1934 => x"81", + 1935 => x"2e", + 1936 => x"ea", + 1937 => x"81", + 1938 => x"72", + 1939 => x"70", + 1940 => x"38", + 1941 => x"80", + 1942 => x"73", + 1943 => x"72", + 1944 => x"70", + 1945 => x"81", + 1946 => x"81", + 1947 => x"32", + 1948 => x"05", + 1949 => x"76", + 1950 => x"51", + 1951 => x"88", + 1952 => x"70", + 1953 => x"34", + 1954 => x"72", + 1955 => x"85", + 1956 => x"3d", + 1957 => x"3d", + 1958 => x"72", + 1959 => x"91", + 1960 => x"fc", + 1961 => x"51", + 1962 => x"82", + 1963 => x"85", + 1964 => x"83", + 1965 => x"72", + 1966 => x"0c", + 1967 => x"04", + 1968 => x"76", + 1969 => x"ff", + 1970 => x"81", + 1971 => x"26", + 1972 => x"83", + 1973 => x"05", + 1974 => x"70", + 1975 => x"8a", + 1976 => x"33", + 1977 => x"70", + 1978 => x"fe", + 1979 => x"33", + 1980 => x"70", + 1981 => x"f2", + 1982 => x"33", + 1983 => x"70", + 1984 => x"e6", + 1985 => x"22", + 1986 => x"74", + 1987 => x"80", + 1988 => x"13", + 1989 => x"52", + 1990 => x"26", + 1991 => x"81", + 1992 => x"98", + 1993 => x"22", + 1994 => x"bc", + 1995 => x"33", + 1996 => x"b8", + 1997 => x"33", + 1998 => x"b4", + 1999 => x"33", + 2000 => x"b0", + 2001 => x"33", + 2002 => x"ac", + 2003 => x"33", + 2004 => x"a8", + 2005 => x"c0", + 2006 => x"73", + 2007 => x"a0", + 2008 => x"87", + 2009 => x"0c", + 2010 => x"82", + 2011 => x"86", + 2012 => x"f3", + 2013 => x"5b", + 2014 => x"9c", + 2015 => x"0c", + 2016 => x"bc", + 2017 => x"7b", + 2018 => x"98", + 2019 => x"79", + 2020 => x"87", + 2021 => x"08", + 2022 => x"1c", + 2023 => x"98", + 2024 => x"79", + 2025 => x"87", + 2026 => x"08", + 2027 => x"1c", + 2028 => x"98", + 2029 => x"79", + 2030 => x"87", + 2031 => x"08", + 2032 => x"1c", + 2033 => x"98", + 2034 => x"79", + 2035 => x"80", + 2036 => x"83", + 2037 => x"59", + 2038 => x"ff", + 2039 => x"1b", + 2040 => x"1b", + 2041 => x"1b", + 2042 => x"1b", + 2043 => x"1b", + 2044 => x"83", + 2045 => x"52", + 2046 => x"51", + 2047 => x"8f", + 2048 => x"ff", + 2049 => x"8f", + 2050 => x"09", + 2051 => x"9f", + 2052 => x"52", + 2053 => x"8c", + 2054 => x"0d", + 2055 => x"0d", + 2056 => x"8c", + 2057 => x"ff", + 2058 => x"56", + 2059 => x"84", + 2060 => x"2e", + 2061 => x"c0", + 2062 => x"70", + 2063 => x"2a", + 2064 => x"53", + 2065 => x"80", + 2066 => x"71", + 2067 => x"81", + 2068 => x"70", + 2069 => x"81", + 2070 => x"06", + 2071 => x"80", + 2072 => x"71", + 2073 => x"81", + 2074 => x"70", + 2075 => x"73", + 2076 => x"51", + 2077 => x"80", + 2078 => x"2e", + 2079 => x"c0", + 2080 => x"75", + 2081 => x"82", + 2082 => x"87", + 2083 => x"fb", + 2084 => x"9f", + 2085 => x"84", + 2086 => x"81", + 2087 => x"55", + 2088 => x"94", + 2089 => x"80", + 2090 => x"87", + 2091 => x"51", + 2092 => x"96", + 2093 => x"06", + 2094 => x"70", + 2095 => x"38", + 2096 => x"70", + 2097 => x"51", + 2098 => x"72", + 2099 => x"81", + 2100 => x"70", + 2101 => x"38", + 2102 => x"70", + 2103 => x"51", + 2104 => x"38", + 2105 => x"06", + 2106 => x"94", + 2107 => x"80", + 2108 => x"87", + 2109 => x"52", + 2110 => x"87", + 2111 => x"f9", + 2112 => x"54", + 2113 => x"70", + 2114 => x"53", + 2115 => x"77", + 2116 => x"38", + 2117 => x"06", + 2118 => x"84", + 2119 => x"81", + 2120 => x"57", + 2121 => x"c0", + 2122 => x"75", + 2123 => x"38", + 2124 => x"94", + 2125 => x"70", + 2126 => x"81", + 2127 => x"52", + 2128 => x"8c", + 2129 => x"2a", + 2130 => x"51", + 2131 => x"38", + 2132 => x"70", + 2133 => x"51", + 2134 => x"8d", + 2135 => x"2a", + 2136 => x"51", + 2137 => x"be", + 2138 => x"ff", + 2139 => x"c0", + 2140 => x"70", + 2141 => x"38", + 2142 => x"90", + 2143 => x"0c", + 2144 => x"33", + 2145 => x"06", + 2146 => x"70", + 2147 => x"76", + 2148 => x"0c", + 2149 => x"04", + 2150 => x"82", + 2151 => x"70", + 2152 => x"54", + 2153 => x"94", + 2154 => x"80", + 2155 => x"87", + 2156 => x"51", + 2157 => x"82", + 2158 => x"06", + 2159 => x"70", + 2160 => x"38", + 2161 => x"06", + 2162 => x"94", + 2163 => x"80", + 2164 => x"87", + 2165 => x"52", + 2166 => x"81", + 2167 => x"85", + 2168 => x"84", + 2169 => x"fe", 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x"c0", + 2229 => x"82", + 2230 => x"87", + 2231 => x"08", + 2232 => x"0c", + 2233 => x"8c", + 2234 => x"d0", + 2235 => x"82", + 2236 => x"80", + 2237 => x"9e", + 2238 => x"84", + 2239 => x"51", + 2240 => x"80", + 2241 => x"81", + 2242 => x"84", + 2243 => x"0b", + 2244 => x"90", + 2245 => x"80", + 2246 => x"52", + 2247 => x"2e", + 2248 => x"52", + 2249 => x"d6", + 2250 => x"87", + 2251 => x"08", + 2252 => x"0a", + 2253 => x"52", + 2254 => x"83", + 2255 => x"71", + 2256 => x"34", + 2257 => x"c0", + 2258 => x"70", + 2259 => x"06", + 2260 => x"70", + 2261 => x"38", + 2262 => x"82", + 2263 => x"80", + 2264 => x"9e", + 2265 => x"a0", + 2266 => x"51", + 2267 => x"80", + 2268 => x"81", + 2269 => x"84", + 2270 => x"0b", + 2271 => x"90", + 2272 => x"80", + 2273 => x"52", + 2274 => x"2e", + 2275 => x"52", + 2276 => x"da", + 2277 => x"87", + 2278 => x"08", + 2279 => x"80", + 2280 => x"52", + 2281 => x"83", + 2282 => x"71", + 2283 => x"34", + 2284 => x"c0", + 2285 => x"70", + 2286 => x"06", + 2287 => x"70", + 2288 => x"38", + 2289 => x"82", + 2290 => x"80", + 2291 => x"9e", + 2292 => x"81", + 2293 => x"51", + 2294 => x"80", + 2295 => x"81", + 2296 => x"84", + 2297 => x"0b", + 2298 => x"90", + 2299 => x"c0", + 2300 => x"52", + 2301 => x"2e", + 2302 => x"52", + 2303 => x"de", + 2304 => x"87", + 2305 => x"08", + 2306 => x"06", + 2307 => x"70", + 2308 => x"38", + 2309 => x"82", + 2310 => x"87", + 2311 => x"08", + 2312 => x"06", + 2313 => x"51", + 2314 => x"82", + 2315 => x"80", + 2316 => x"9e", + 2317 => x"84", + 2318 => x"52", + 2319 => x"2e", + 2320 => x"52", + 2321 => x"e1", + 2322 => x"9e", + 2323 => x"83", + 2324 => x"84", + 2325 => x"51", + 2326 => x"e2", + 2327 => x"87", + 2328 => x"08", + 2329 => x"51", + 2330 => x"80", + 2331 => x"81", + 2332 => x"84", + 2333 => x"c0", + 2334 => x"70", + 2335 => x"51", + 2336 => x"e4", + 2337 => x"0d", + 2338 => x"0d", + 2339 => x"51", + 2340 => x"82", + 2341 => x"54", + 2342 => x"88", + 2343 => x"b4", + 2344 => x"3f", + 2345 => x"51", + 2346 => x"82", + 2347 => x"54", + 2348 => x"93", + 2349 => x"b0", + 2350 => x"b4", + 2351 => x"52", + 2352 => x"51", + 2353 => x"82", + 2354 => x"54", + 2355 => x"93", + 2356 => x"a8", + 2357 => x"ac", + 2358 => x"52", + 2359 => x"51", + 2360 => x"82", + 2361 => x"54", + 2362 => x"93", + 2363 => x"90", + 2364 => x"94", + 2365 => x"52", + 2366 => x"51", + 2367 => x"82", + 2368 => x"54", + 2369 => x"93", + 2370 => x"98", + 2371 => x"9c", + 2372 => x"52", + 2373 => x"51", + 2374 => x"82", + 2375 => x"54", + 2376 => x"93", + 2377 => x"a0", + 2378 => x"a4", + 2379 => x"52", + 2380 => x"51", + 2381 => x"82", + 2382 => x"54", + 2383 => x"8d", + 2384 => x"e0", + 2385 => x"f6", + 2386 => x"92", + 2387 => x"e3", + 2388 => x"80", + 2389 => x"82", + 2390 => x"52", + 2391 => x"51", + 2392 => x"82", + 2393 => x"54", + 2394 => x"8d", + 2395 => x"e2", + 2396 => x"f7", + 2397 => x"e6", + 2398 => x"d5", + 2399 => x"80", + 2400 => x"81", + 2401 => x"83", + 2402 => x"84", + 2403 => x"73", + 2404 => x"38", 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x"84", + 2464 => x"bd", + 2465 => x"74", + 2466 => x"3f", + 2467 => x"08", + 2468 => x"c0", + 2469 => x"ec", + 2470 => x"f1", + 2471 => x"85", + 2472 => x"53", + 2473 => x"fa", + 2474 => x"b2", + 2475 => x"d8", + 2476 => x"3f", + 2477 => x"04", + 2478 => x"02", + 2479 => x"ff", + 2480 => x"84", + 2481 => x"71", + 2482 => x"81", + 2483 => x"08", + 2484 => x"c8", + 2485 => x"81", + 2486 => x"97", + 2487 => x"d8", + 2488 => x"81", + 2489 => x"8b", + 2490 => x"e4", + 2491 => x"81", + 2492 => x"80", + 2493 => x"3d", + 2494 => x"88", + 2495 => x"80", + 2496 => x"96", + 2497 => x"82", + 2498 => x"87", + 2499 => x"0c", + 2500 => x"0d", + 2501 => x"33", + 2502 => x"2e", + 2503 => x"85", + 2504 => x"ed", + 2505 => x"fc", + 2506 => x"80", + 2507 => x"72", + 2508 => x"9c", + 2509 => x"05", + 2510 => x"0c", + 2511 => x"9c", + 2512 => x"71", + 2513 => x"38", + 2514 => x"2d", + 2515 => x"04", + 2516 => x"02", + 2517 => x"82", + 2518 => x"76", + 2519 => x"0c", + 2520 => x"ad", + 2521 => x"9c", + 2522 => x"3d", + 2523 => x"3d", + 2524 => x"73", + 2525 => x"ff", + 2526 => x"71", + 2527 => x"38", + 2528 => x"06", + 2529 => x"54", + 2530 => x"e7", + 2531 => x"0d", + 2532 => x"0d", + 2533 => x"f4", + 2534 => x"9c", + 2535 => x"54", + 2536 => x"81", + 2537 => x"53", + 2538 => x"8e", + 2539 => x"ff", + 2540 => x"14", + 2541 => x"3f", + 2542 => x"82", + 2543 => x"86", + 2544 => x"ec", + 2545 => x"68", + 2546 => x"70", + 2547 => x"33", + 2548 => x"2e", + 2549 => x"75", + 2550 => x"81", + 2551 => x"38", + 2552 => x"70", + 2553 => x"33", + 2554 => x"75", + 2555 => x"81", + 2556 => x"81", + 2557 => x"75", + 2558 => x"81", + 2559 => x"82", + 2560 => x"81", + 2561 => x"56", + 2562 => x"09", + 2563 => x"38", + 2564 => x"71", + 2565 => x"81", + 2566 => x"59", + 2567 => x"9f", + 2568 => x"53", + 2569 => x"97", + 2570 => x"2b", + 2571 => x"11", + 2572 => x"7b", + 2573 => x"5d", + 2574 => x"51", + 2575 => x"75", + 2576 => x"70", + 2577 => x"70", + 2578 => x"25", + 2579 => x"32", + 2580 => x"05", + 2581 => x"80", + 2582 => x"53", + 2583 => x"55", + 2584 => x"2e", + 2585 => x"84", + 2586 => x"81", + 2587 => x"57", + 2588 => x"2e", + 2589 => x"75", + 2590 => x"76", + 2591 => x"e0", + 2592 => x"ff", + 2593 => x"73", + 2594 => x"81", + 2595 => x"80", + 2596 => x"38", + 2597 => x"2e", + 2598 => x"73", + 2599 => x"8b", + 2600 => x"c2", + 2601 => x"38", + 2602 => x"73", + 2603 => x"81", + 2604 => x"8f", + 2605 => x"d5", + 2606 => x"38", + 2607 => x"24", + 2608 => x"80", + 2609 => x"38", + 2610 => x"73", + 2611 => x"80", + 2612 => x"ef", + 2613 => x"19", + 2614 => x"59", + 2615 => x"33", + 2616 => x"75", + 2617 => x"81", + 2618 => x"70", + 2619 => x"55", + 2620 => x"79", + 2621 => x"90", + 2622 => x"16", + 2623 => x"7b", + 2624 => x"a0", + 2625 => x"3f", + 2626 => x"53", + 2627 => x"e9", + 2628 => x"fc", + 2629 => x"81", + 2630 => x"72", + 2631 => x"aa", + 2632 => x"fb", + 2633 => x"39", + 2634 => x"83", + 2635 => x"59", + 2636 => x"82", + 2637 => x"88", + 2638 => x"8a", + 2639 => x"90", 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x"56", + 2699 => x"26", + 2700 => x"3d", + 2701 => x"05", + 2702 => x"ff", + 2703 => x"53", + 2704 => x"cd", + 2705 => x"38", + 2706 => x"56", + 2707 => x"27", + 2708 => x"a0", + 2709 => x"3f", + 2710 => x"3d", + 2711 => x"3d", + 2712 => x"70", + 2713 => x"52", + 2714 => x"73", + 2715 => x"3f", + 2716 => x"04", + 2717 => x"74", + 2718 => x"0c", + 2719 => x"05", + 2720 => x"fa", + 2721 => x"9c", + 2722 => x"80", + 2723 => x"0b", + 2724 => x"0c", + 2725 => x"04", + 2726 => x"82", + 2727 => x"76", + 2728 => x"0c", + 2729 => x"05", + 2730 => x"53", + 2731 => x"72", + 2732 => x"0c", + 2733 => x"04", + 2734 => x"77", + 2735 => x"f8", + 2736 => x"54", + 2737 => x"54", + 2738 => x"80", + 2739 => x"9c", + 2740 => x"71", + 2741 => x"ec", + 2742 => x"06", + 2743 => x"2e", + 2744 => x"72", + 2745 => x"38", + 2746 => x"70", + 2747 => x"70", + 2748 => x"51", + 2749 => x"2e", + 2750 => x"80", + 2751 => x"ff", + 2752 => x"39", + 2753 => x"c6", + 2754 => x"52", + 2755 => x"ff", + 2756 => x"14", + 2757 => x"34", + 2758 => x"72", + 2759 => x"3f", + 2760 => x"73", + 2761 => x"72", + 2762 => x"f7", + 2763 => x"53", + 2764 => x"ec", + 2765 => x"0d", + 2766 => x"0d", + 2767 => x"08", + 2768 => x"f8", + 2769 => x"76", + 2770 => x"ec", + 2771 => x"9c", + 2772 => x"3d", + 2773 => x"3d", + 2774 => x"5a", + 2775 => x"7a", + 2776 => x"08", + 2777 => x"53", + 2778 => x"09", + 2779 => x"38", + 2780 => x"0c", + 2781 => x"ad", + 2782 => x"06", + 2783 => x"76", + 2784 => x"0c", + 2785 => x"33", + 2786 => x"73", + 2787 => x"81", + 2788 => x"38", + 2789 => x"05", + 2790 => x"08", + 2791 => x"53", + 2792 => x"2e", + 2793 => x"57", + 2794 => x"2e", + 2795 => x"39", + 2796 => x"13", + 2797 => x"08", + 2798 => x"53", + 2799 => x"55", + 2800 => x"81", + 2801 => x"14", + 2802 => x"88", + 2803 => x"27", + 2804 => x"f5", + 2805 => x"53", + 2806 => x"89", + 2807 => x"38", + 2808 => x"55", + 2809 => x"8a", + 2810 => x"a0", + 2811 => x"ca", + 2812 => x"74", + 2813 => x"e0", + 2814 => x"ff", + 2815 => x"d0", + 2816 => x"ff", + 2817 => x"90", + 2818 => x"38", + 2819 => x"81", + 2820 => x"53", + 2821 => x"ca", + 2822 => x"27", + 2823 => x"52", + 2824 => x"e9", + 2825 => x"ec", + 2826 => x"08", + 2827 => x"0c", + 2828 => x"33", + 2829 => x"ff", + 2830 => x"80", + 2831 => x"74", + 2832 => x"55", + 2833 => x"81", + 2834 => x"85", + 2835 => x"3d", + 2836 => x"3d", + 2837 => x"5a", + 2838 => x"7a", + 2839 => x"08", + 2840 => x"53", + 2841 => x"09", + 2842 => x"38", + 2843 => x"0c", + 2844 => x"ad", + 2845 => x"06", + 2846 => x"76", + 2847 => x"0c", + 2848 => x"33", + 2849 => x"73", + 2850 => x"81", + 2851 => x"38", + 2852 => x"05", + 2853 => x"08", + 2854 => x"53", + 2855 => x"2e", + 2856 => x"57", + 2857 => x"2e", + 2858 => x"39", + 2859 => x"13", + 2860 => x"08", + 2861 => x"53", + 2862 => x"55", + 2863 => x"81", + 2864 => x"14", + 2865 => x"88", + 2866 => x"27", + 2867 => x"f5", + 2868 => x"53", + 2869 => x"89", + 2870 => x"38", + 2871 => x"55", + 2872 => x"8a", + 2873 => x"a0", + 2874 => x"ca", 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x"73", + 2934 => x"0d", + 2935 => x"0d", + 2936 => x"05", + 2937 => x"02", + 2938 => x"05", + 2939 => x"c4", + 2940 => x"2b", + 2941 => x"11", + 2942 => x"59", + 2943 => x"74", + 2944 => x"38", + 2945 => x"87", + 2946 => x"c4", + 2947 => x"2b", + 2948 => x"11", + 2949 => x"55", + 2950 => x"5a", + 2951 => x"82", + 2952 => x"75", + 2953 => x"c4", + 2954 => x"2b", + 2955 => x"11", + 2956 => x"5a", + 2957 => x"a7", + 2958 => x"78", + 2959 => x"ff", + 2960 => x"82", + 2961 => x"81", + 2962 => x"82", + 2963 => x"74", + 2964 => x"55", + 2965 => x"87", + 2966 => x"82", + 2967 => x"77", + 2968 => x"38", + 2969 => x"08", + 2970 => x"2e", + 2971 => x"85", + 2972 => x"74", + 2973 => x"3d", + 2974 => x"76", + 2975 => x"75", + 2976 => x"9f", + 2977 => x"c0", + 2978 => x"51", + 2979 => x"3f", + 2980 => x"08", + 2981 => x"fc", + 2982 => x"0d", + 2983 => x"0d", + 2984 => x"53", + 2985 => x"08", + 2986 => x"2e", + 2987 => x"51", + 2988 => x"80", + 2989 => x"14", + 2990 => x"54", + 2991 => x"e6", + 2992 => x"82", + 2993 => x"82", + 2994 => x"52", + 2995 => x"95", + 2996 => x"80", + 2997 => x"82", + 2998 => x"51", + 2999 => x"80", + 3000 => x"c0", + 3001 => x"0d", + 3002 => x"0d", + 3003 => x"52", + 3004 => x"08", + 3005 => x"c8", + 3006 => x"ec", + 3007 => x"38", + 3008 => x"08", + 3009 => x"52", + 3010 => x"52", + 3011 => x"b3", + 3012 => x"ec", + 3013 => x"b9", + 3014 => x"ff", + 3015 => x"82", + 3016 => x"55", + 3017 => x"85", + 3018 => x"9c", + 3019 => x"ec", + 3020 => x"70", + 3021 => x"80", + 3022 => x"53", + 3023 => x"17", + 3024 => x"52", + 3025 => x"3f", + 3026 => x"09", + 3027 => x"b0", + 3028 => x"0d", + 3029 => x"0d", + 3030 => x"ad", + 3031 => x"5a", + 3032 => x"58", + 3033 => x"85", + 3034 => x"80", + 3035 => x"82", + 3036 => x"81", + 3037 => x"0b", + 3038 => x"08", + 3039 => x"f8", + 3040 => x"70", + 3041 => x"86", + 3042 => x"85", + 3043 => x"2e", + 3044 => x"51", + 3045 => x"3f", + 3046 => x"08", + 3047 => x"55", + 3048 => x"85", + 3049 => x"8e", + 3050 => x"ec", + 3051 => x"70", + 3052 => x"80", + 3053 => x"09", + 3054 => x"05", + 3055 => x"9f", + 3056 => x"55", + 3057 => x"85", + 3058 => x"aa", + 3059 => x"c0", + 3060 => x"08", + 3061 => x"dc", + 3062 => x"85", + 3063 => x"2e", + 3064 => x"fd", + 3065 => x"86", + 3066 => x"2e", + 3067 => x"9b", + 3068 => x"79", + 3069 => x"b2", + 3070 => x"ff", + 3071 => x"ab", + 3072 => x"82", + 3073 => x"74", + 3074 => x"77", + 3075 => x"0c", + 3076 => x"04", + 3077 => x"7c", + 3078 => x"71", + 3079 => x"59", + 3080 => x"a0", + 3081 => x"06", + 3082 => x"33", + 3083 => x"77", + 3084 => x"38", + 3085 => x"5b", + 3086 => x"56", + 3087 => x"a0", + 3088 => x"06", + 3089 => x"75", + 3090 => x"80", + 3091 => x"2b", + 3092 => x"11", + 3093 => x"51", + 3094 => x"e0", + 3095 => x"ec", + 3096 => x"52", + 3097 => x"ff", + 3098 => x"82", + 3099 => x"80", + 3100 => x"14", + 3101 => x"81", + 3102 => x"73", + 3103 => x"38", + 3104 => x"e5", + 3105 => x"81", + 3106 => x"3d", + 3107 => x"f8", + 3108 => x"c2", + 3109 => x"ec", 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x"08", + 3169 => x"17", + 3170 => x"74", + 3171 => x"74", + 3172 => x"52", + 3173 => x"c5", + 3174 => x"70", + 3175 => x"5c", + 3176 => x"27", + 3177 => x"5b", + 3178 => x"09", + 3179 => x"97", + 3180 => x"75", + 3181 => x"34", + 3182 => x"82", + 3183 => x"80", + 3184 => x"f9", + 3185 => x"3d", + 3186 => x"3f", + 3187 => x"08", + 3188 => x"98", + 3189 => x"78", + 3190 => x"38", + 3191 => x"06", + 3192 => x"33", + 3193 => x"70", + 3194 => x"9d", + 3195 => x"98", + 3196 => x"2c", + 3197 => x"05", + 3198 => x"81", + 3199 => x"08", + 3200 => x"51", + 3201 => x"59", + 3202 => x"5d", + 3203 => x"73", + 3204 => x"e3", + 3205 => x"27", + 3206 => x"15", + 3207 => x"70", + 3208 => x"56", + 3209 => x"24", + 3210 => x"76", + 3211 => x"77", + 3212 => x"3f", + 3213 => x"08", + 3214 => x"54", + 3215 => x"da", + 3216 => x"9d", + 3217 => x"56", + 3218 => x"15", + 3219 => x"70", + 3220 => x"81", + 3221 => x"51", + 3222 => x"95", + 3223 => x"76", + 3224 => x"77", + 3225 => x"3f", + 3226 => x"08", + 3227 => x"54", + 3228 => x"d6", + 3229 => x"75", + 3230 => x"ca", + 3231 => x"54", + 3232 => x"84", + 3233 => x"2b", + 3234 => x"82", + 3235 => x"70", + 3236 => x"98", + 3237 => x"71", + 3238 => x"81", + 3239 => x"33", + 3240 => x"51", + 3241 => x"54", + 3242 => x"09", + 3243 => x"99", + 3244 => x"fc", + 3245 => x"0c", + 3246 => x"9d", + 3247 => x"0b", + 3248 => x"34", + 3249 => x"82", + 3250 => x"75", + 3251 => x"34", + 3252 => x"34", + 3253 => x"7e", + 3254 => x"26", + 3255 => x"73", + 3256 => x"81", + 3257 => x"08", + 3258 => x"8c", + 3259 => x"7e", + 3260 => x"38", + 3261 => x"33", + 3262 => x"27", + 3263 => x"98", + 3264 => x"2c", + 3265 => x"75", + 3266 => x"74", + 3267 => x"33", + 3268 => x"ff", + 3269 => x"2b", + 3270 => x"82", + 3271 => x"53", + 3272 => x"74", + 3273 => x"38", + 3274 => x"33", + 3275 => x"54", + 3276 => x"8c", + 3277 => x"54", + 3278 => x"74", + 3279 => x"88", + 3280 => x"7e", + 3281 => x"81", + 3282 => x"82", + 3283 => x"82", + 3284 => x"ff", + 3285 => x"2b", + 3286 => x"82", + 3287 => x"59", + 3288 => x"74", + 3289 => x"38", + 3290 => x"33", + 3291 => x"a1", + 3292 => x"70", + 3293 => x"98", + 3294 => x"88", + 3295 => x"56", + 3296 => x"24", + 3297 => x"9d", + 3298 => x"98", + 3299 => x"2c", + 3300 => x"33", + 3301 => x"54", + 3302 => x"fc", + 3303 => x"51", + 3304 => x"81", + 3305 => x"2b", + 3306 => x"82", + 3307 => x"5a", + 3308 => x"76", + 3309 => x"38", + 3310 => x"83", + 3311 => x"0b", + 3312 => x"82", + 3313 => x"80", + 3314 => x"d8", + 3315 => x"3f", + 3316 => x"82", + 3317 => x"70", + 3318 => x"55", + 3319 => x"2e", + 3320 => x"82", + 3321 => x"ff", + 3322 => x"82", + 3323 => x"ff", + 3324 => x"82", + 3325 => x"88", + 3326 => x"3f", + 3327 => x"33", + 3328 => x"70", + 3329 => x"9d", + 3330 => x"51", + 3331 => x"74", + 3332 => x"74", + 3333 => x"14", + 3334 => x"73", + 3335 => x"f1", + 3336 => x"70", + 3337 => x"98", + 3338 => x"88", + 3339 => x"56", + 3340 => x"24", + 3341 => x"51", + 3342 => x"82", + 3343 => x"70", + 3344 => x"98", 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x"38", + 3404 => x"dd", + 3405 => x"8c", + 3406 => x"2b", + 3407 => x"82", + 3408 => x"57", + 3409 => x"74", + 3410 => x"fa", + 3411 => x"e3", + 3412 => x"15", + 3413 => x"70", + 3414 => x"9d", + 3415 => x"51", + 3416 => x"75", + 3417 => x"f8", + 3418 => x"9d", + 3419 => x"81", + 3420 => x"9d", + 3421 => x"56", + 3422 => x"27", + 3423 => x"81", + 3424 => x"82", + 3425 => x"74", + 3426 => x"52", + 3427 => x"3f", + 3428 => x"33", + 3429 => x"06", + 3430 => x"33", + 3431 => x"75", + 3432 => x"38", + 3433 => x"82", + 3434 => x"80", + 3435 => x"d8", + 3436 => x"3f", + 3437 => x"9d", + 3438 => x"0b", + 3439 => x"34", + 3440 => x"7a", + 3441 => x"85", + 3442 => x"74", + 3443 => x"38", + 3444 => x"a7", + 3445 => x"85", + 3446 => x"9d", + 3447 => x"85", + 3448 => x"ff", + 3449 => x"53", + 3450 => x"51", + 3451 => x"3f", + 3452 => x"c0", + 3453 => x"2b", + 3454 => x"11", + 3455 => x"57", + 3456 => x"80", + 3457 => x"74", + 3458 => x"b0", + 3459 => x"ec", + 3460 => x"88", + 3461 => x"ec", + 3462 => x"06", + 3463 => x"74", + 3464 => x"ff", + 3465 => x"ff", + 3466 => x"f9", + 3467 => x"55", + 3468 => x"f7", + 3469 => x"51", + 3470 => x"3f", + 3471 => x"93", + 3472 => x"06", + 3473 => x"84", + 3474 => x"74", + 3475 => x"38", + 3476 => x"a6", + 3477 => x"85", + 3478 => x"9d", + 3479 => x"85", + 3480 => x"ff", + 3481 => x"53", + 3482 => x"51", + 3483 => x"3f", + 3484 => x"7a", + 3485 => x"84", + 3486 => x"56", + 3487 => x"2e", + 3488 => x"51", + 3489 => x"3f", + 3490 => x"08", + 3491 => x"34", + 3492 => x"08", + 3493 => x"81", + 3494 => x"52", + 3495 => x"a7", + 3496 => x"1b", + 3497 => x"ff", + 3498 => x"39", + 3499 => x"88", + 3500 => x"34", + 3501 => x"53", + 3502 => x"33", + 3503 => x"ed", + 3504 => x"82", + 3505 => x"8c", + 3506 => x"ff", + 3507 => x"88", + 3508 => x"54", + 3509 => x"f5", + 3510 => x"14", + 3511 => x"9d", + 3512 => x"1a", + 3513 => x"54", + 3514 => x"f5", + 3515 => x"9d", + 3516 => x"73", + 3517 => x"ce", + 3518 => x"e0", + 3519 => x"9d", + 3520 => x"05", + 3521 => x"9d", + 3522 => x"ba", + 3523 => x"0d", + 3524 => x"0b", + 3525 => x"0c", + 3526 => x"82", + 3527 => x"90", + 3528 => x"52", + 3529 => x"51", + 3530 => x"3f", + 3531 => x"08", + 3532 => x"77", + 3533 => x"57", + 3534 => x"34", + 3535 => x"08", + 3536 => x"15", + 3537 => x"15", + 3538 => x"e4", + 3539 => x"86", + 3540 => x"87", + 3541 => x"85", + 3542 => x"85", + 3543 => x"05", + 3544 => x"07", + 3545 => x"ff", + 3546 => x"2a", + 3547 => x"56", + 3548 => x"34", + 3549 => x"34", + 3550 => x"22", + 3551 => x"82", + 3552 => x"11", + 3553 => x"55", + 3554 => x"15", + 3555 => x"15", + 3556 => x"0d", + 3557 => x"0d", + 3558 => x"51", + 3559 => x"8f", + 3560 => x"83", + 3561 => x"70", + 3562 => x"06", + 3563 => x"70", + 3564 => x"0c", + 3565 => x"04", + 3566 => x"02", + 3567 => x"02", + 3568 => x"05", + 3569 => x"82", + 3570 => x"71", + 3571 => x"11", + 3572 => x"73", + 3573 => x"81", + 3574 => x"88", + 3575 => x"a4", + 3576 => x"22", + 3577 => x"ff", + 3578 => x"88", + 3579 => x"52", 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x"70", + 3639 => x"51", + 3640 => x"71", + 3641 => x"81", + 3642 => x"3d", + 3643 => x"3d", + 3644 => x"05", + 3645 => x"e4", + 3646 => x"2b", + 3647 => x"33", + 3648 => x"71", + 3649 => x"70", + 3650 => x"59", + 3651 => x"73", + 3652 => x"81", + 3653 => x"98", + 3654 => x"2b", + 3655 => x"55", + 3656 => x"80", + 3657 => x"38", + 3658 => x"aa", + 3659 => x"e4", + 3660 => x"70", + 3661 => x"33", + 3662 => x"71", + 3663 => x"74", + 3664 => x"81", + 3665 => x"88", + 3666 => x"83", + 3667 => x"f8", + 3668 => x"5d", + 3669 => x"5a", + 3670 => x"75", + 3671 => x"52", + 3672 => x"34", + 3673 => x"34", + 3674 => x"08", + 3675 => x"33", + 3676 => x"71", + 3677 => x"83", + 3678 => x"59", + 3679 => x"05", + 3680 => x"12", + 3681 => x"2b", + 3682 => x"ff", + 3683 => x"88", + 3684 => x"52", + 3685 => x"74", + 3686 => x"15", + 3687 => x"0d", + 3688 => x"0d", + 3689 => x"08", + 3690 => x"9e", + 3691 => x"83", + 3692 => x"82", + 3693 => x"12", + 3694 => x"2b", + 3695 => x"07", + 3696 => x"52", + 3697 => x"05", + 3698 => x"13", + 3699 => x"2b", + 3700 => x"05", + 3701 => x"71", + 3702 => x"2a", + 3703 => x"53", + 3704 => x"34", + 3705 => x"34", + 3706 => x"08", + 3707 => x"33", + 3708 => x"71", + 3709 => x"83", + 3710 => x"59", + 3711 => x"05", + 3712 => x"83", + 3713 => x"88", + 3714 => x"88", + 3715 => x"56", + 3716 => x"13", + 3717 => x"13", + 3718 => x"e4", + 3719 => x"11", + 3720 => x"33", + 3721 => x"07", + 3722 => x"0c", + 3723 => x"3d", + 3724 => x"3d", + 3725 => x"85", + 3726 => x"83", + 3727 => x"ff", + 3728 => x"53", + 3729 => x"a6", + 3730 => x"e4", + 3731 => x"2b", + 3732 => x"11", + 3733 => x"33", + 3734 => x"71", + 3735 => x"75", + 3736 => x"81", + 3737 => x"98", + 3738 => x"2b", + 3739 => x"40", + 3740 => x"58", + 3741 => x"72", + 3742 => x"38", + 3743 => x"52", + 3744 => x"9d", + 3745 => x"39", + 3746 => x"85", + 3747 => x"8b", + 3748 => x"2b", + 3749 => x"79", + 3750 => x"51", + 3751 => x"76", + 3752 => x"75", + 3753 => x"56", + 3754 => x"34", + 3755 => x"08", + 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x"53", + 3874 => x"56", + 3875 => x"16", + 3876 => x"16", + 3877 => x"e4", + 3878 => x"05", + 3879 => x"85", + 3880 => x"3d", + 3881 => x"3d", + 3882 => x"82", + 3883 => x"84", + 3884 => x"3f", + 3885 => x"80", + 3886 => x"71", + 3887 => x"3f", + 3888 => x"08", + 3889 => x"85", + 3890 => x"3d", + 3891 => x"3d", + 3892 => x"05", + 3893 => x"52", + 3894 => x"87", + 3895 => x"e8", + 3896 => x"71", + 3897 => x"0c", + 3898 => x"04", + 3899 => x"02", + 3900 => x"02", + 3901 => x"05", + 3902 => x"83", + 3903 => x"26", + 3904 => x"72", + 3905 => x"c0", + 3906 => x"53", + 3907 => x"74", + 3908 => x"38", + 3909 => x"73", + 3910 => x"c0", + 3911 => x"51", + 3912 => x"85", + 3913 => x"98", + 3914 => x"52", + 3915 => x"82", + 3916 => x"70", + 3917 => x"38", + 3918 => x"8c", + 3919 => x"ec", + 3920 => x"fc", + 3921 => x"52", + 3922 => x"87", + 3923 => x"08", + 3924 => x"2e", + 3925 => x"82", + 3926 => x"34", + 3927 => x"13", + 3928 => x"82", + 3929 => x"86", + 3930 => x"f3", + 3931 => x"62", + 3932 => x"05", + 3933 => x"57", + 3934 => x"83", + 3935 => x"fe", + 3936 => x"85", + 3937 => x"06", + 3938 => x"71", + 3939 => x"71", + 3940 => x"2b", + 3941 => x"80", + 3942 => x"92", + 3943 => x"c0", + 3944 => x"41", + 3945 => x"5a", + 3946 => x"87", + 3947 => x"0c", + 3948 => x"84", + 3949 => x"08", + 3950 => x"70", + 3951 => x"53", + 3952 => x"2e", + 3953 => x"08", + 3954 => x"70", + 3955 => x"34", + 3956 => x"80", + 3957 => x"53", + 3958 => x"2e", + 3959 => x"53", + 3960 => x"26", + 3961 => x"80", + 3962 => x"87", + 3963 => x"08", + 3964 => x"38", + 3965 => x"8c", + 3966 => x"80", + 3967 => x"78", + 3968 => x"99", + 3969 => x"0c", + 3970 => x"8c", + 3971 => x"08", + 3972 => x"51", + 3973 => x"38", + 3974 => x"8d", + 3975 => x"17", + 3976 => x"81", + 3977 => x"53", + 3978 => x"2e", + 3979 => x"fc", + 3980 => x"52", + 3981 => x"7d", + 3982 => x"ed", + 3983 => x"80", + 3984 => x"71", + 3985 => x"38", + 3986 => x"53", + 3987 => x"ec", + 3988 => x"0d", + 3989 => x"0d", + 3990 => x"02", + 3991 => x"05", + 3992 => x"58", + 3993 => x"80", + 3994 => x"fc", + 3995 => x"85", + 3996 => x"06", + 3997 => x"71", + 3998 => x"81", + 3999 => x"38", + 4000 => x"2b", + 4001 => x"80", + 4002 => x"92", + 4003 => x"c0", + 4004 => x"40", + 4005 => x"5a", + 4006 => x"c0", + 4007 => x"76", + 4008 => x"76", + 4009 => x"75", + 4010 => x"2a", + 4011 => x"51", + 4012 => x"80", + 4013 => x"7a", + 4014 => x"5c", + 4015 => x"81", + 4016 => x"81", + 4017 => x"06", + 4018 => x"80", + 4019 => x"87", + 4020 => x"08", + 4021 => x"38", + 4022 => x"8c", + 4023 => x"80", + 4024 => x"77", + 4025 => x"99", + 4026 => x"0c", + 4027 => x"8c", + 4028 => x"08", + 4029 => x"51", + 4030 => x"38", + 4031 => x"8d", + 4032 => x"70", + 4033 => x"84", + 4034 => x"5b", + 4035 => x"2e", + 4036 => x"fc", + 4037 => x"52", + 4038 => x"7d", + 4039 => x"f8", + 4040 => x"80", + 4041 => x"71", + 4042 => x"38", + 4043 => x"53", + 4044 => x"ec", + 4045 => x"0d", + 4046 => x"0d", + 4047 => x"05", + 4048 => x"02", + 4049 => x"05", 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x"72", + 4109 => x"54", + 4110 => x"2a", + 4111 => x"34", + 4112 => x"04", + 4113 => x"73", + 4114 => x"70", + 4115 => x"05", + 4116 => x"88", + 4117 => x"72", + 4118 => x"54", + 4119 => x"2a", + 4120 => x"70", + 4121 => x"34", + 4122 => x"51", + 4123 => x"83", + 4124 => x"fe", + 4125 => x"75", + 4126 => x"51", + 4127 => x"92", + 4128 => x"81", + 4129 => x"73", + 4130 => x"55", + 4131 => x"51", + 4132 => x"3d", + 4133 => x"3d", + 4134 => x"76", + 4135 => x"72", + 4136 => x"05", + 4137 => x"11", + 4138 => x"38", + 4139 => x"04", + 4140 => x"78", + 4141 => x"56", + 4142 => x"81", + 4143 => x"74", + 4144 => x"56", + 4145 => x"31", + 4146 => x"52", + 4147 => x"80", + 4148 => x"71", + 4149 => x"38", + 4150 => x"ec", + 4151 => x"0d", + 4152 => x"0d", + 4153 => x"51", + 4154 => x"73", + 4155 => x"81", + 4156 => x"33", + 4157 => x"38", + 4158 => x"85", + 4159 => x"3d", + 4160 => x"0b", + 4161 => x"0c", + 4162 => x"82", + 4163 => x"04", + 4164 => x"7b", + 4165 => x"83", + 4166 => x"5a", + 4167 => x"80", + 4168 => x"54", + 4169 => x"53", + 4170 => x"53", + 4171 => x"52", + 4172 => x"3f", + 4173 => x"08", + 4174 => x"81", + 4175 => x"82", + 4176 => x"83", + 4177 => x"16", + 4178 => x"18", + 4179 => x"18", + 4180 => x"58", + 4181 => x"9f", + 4182 => x"33", + 4183 => x"2e", + 4184 => x"93", + 4185 => x"76", + 4186 => x"52", + 4187 => x"51", + 4188 => x"83", + 4189 => x"79", + 4190 => x"0c", + 4191 => x"04", + 4192 => x"78", + 4193 => x"80", + 4194 => x"17", + 4195 => x"38", + 4196 => x"fc", + 4197 => x"ec", + 4198 => x"85", + 4199 => x"38", + 4200 => x"53", + 4201 => x"81", + 4202 => x"f7", + 4203 => x"85", + 4204 => x"2e", + 4205 => x"55", + 4206 => x"b0", + 4207 => x"82", + 4208 => x"88", + 4209 => x"f8", + 4210 => x"70", + 4211 => x"c0", + 4212 => x"ec", + 4213 => x"85", + 4214 => x"91", + 4215 => x"55", + 4216 => x"09", + 4217 => x"f0", + 4218 => x"33", + 4219 => x"2e", + 4220 => x"80", + 4221 => x"80", + 4222 => x"ec", + 4223 => x"17", + 4224 => x"fd", + 4225 => x"d4", + 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x"a4", + 4344 => x"53", + 4345 => x"fb", + 4346 => x"85", + 4347 => x"82", + 4348 => x"81", + 4349 => x"83", + 4350 => x"b4", + 4351 => x"78", + 4352 => x"56", + 4353 => x"76", + 4354 => x"38", + 4355 => x"9f", + 4356 => x"33", + 4357 => x"07", + 4358 => x"74", + 4359 => x"83", + 4360 => x"89", + 4361 => x"08", + 4362 => x"51", + 4363 => x"82", + 4364 => x"59", + 4365 => x"08", + 4366 => x"74", + 4367 => x"16", + 4368 => x"84", + 4369 => x"76", + 4370 => x"88", + 4371 => x"81", + 4372 => x"8f", + 4373 => x"53", + 4374 => x"80", + 4375 => x"88", + 4376 => x"08", + 4377 => x"51", + 4378 => x"82", + 4379 => x"59", + 4380 => x"08", + 4381 => x"77", + 4382 => x"06", + 4383 => x"83", + 4384 => x"05", + 4385 => x"f7", + 4386 => x"39", + 4387 => x"a4", + 4388 => x"52", + 4389 => x"e8", + 4390 => x"ec", + 4391 => x"85", + 4392 => x"38", + 4393 => x"06", + 4394 => x"83", + 4395 => x"18", + 4396 => x"54", + 4397 => x"f6", + 4398 => x"85", + 4399 => x"0a", + 4400 => x"52", + 4401 => x"fc", + 4402 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4461 => x"85", + 4462 => x"82", + 4463 => x"ff", + 4464 => x"38", + 4465 => x"82", + 4466 => x"26", + 4467 => x"79", + 4468 => x"08", + 4469 => x"73", + 4470 => x"bf", + 4471 => x"2e", + 4472 => x"80", + 4473 => x"1a", + 4474 => x"08", + 4475 => x"38", + 4476 => x"52", + 4477 => x"af", + 4478 => x"82", + 4479 => x"81", + 4480 => x"06", + 4481 => x"85", + 4482 => x"82", + 4483 => x"09", + 4484 => x"05", + 4485 => x"80", + 4486 => x"07", + 4487 => x"08", + 4488 => x"55", + 4489 => x"f3", + 4490 => x"ec", + 4491 => x"95", + 4492 => x"08", + 4493 => x"27", + 4494 => x"98", + 4495 => x"89", + 4496 => x"85", + 4497 => x"dd", + 4498 => x"81", + 4499 => x"17", + 4500 => x"89", + 4501 => x"75", + 4502 => x"b0", + 4503 => x"7a", + 4504 => x"3f", + 4505 => x"08", + 4506 => x"38", + 4507 => x"85", + 4508 => x"2e", + 4509 => x"86", + 4510 => x"ec", + 4511 => x"85", + 4512 => x"70", + 4513 => x"70", + 4514 => x"25", + 4515 => x"51", + 4516 => x"73", + 4517 => x"75", + 4518 => x"81", + 4519 => x"38", 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x"70", + 4579 => x"9f", + 4580 => x"56", + 4581 => x"85", + 4582 => x"3d", + 4583 => x"3d", + 4584 => x"71", + 4585 => x"57", + 4586 => x"0a", + 4587 => x"38", + 4588 => x"53", + 4589 => x"38", + 4590 => x"0c", + 4591 => x"54", + 4592 => x"75", + 4593 => x"73", + 4594 => x"a8", + 4595 => x"73", + 4596 => x"85", + 4597 => x"0b", + 4598 => x"5a", + 4599 => x"27", + 4600 => x"a8", + 4601 => x"18", + 4602 => x"39", + 4603 => x"70", + 4604 => x"58", + 4605 => x"b2", + 4606 => x"76", + 4607 => x"3f", + 4608 => x"08", + 4609 => x"ec", + 4610 => x"bd", + 4611 => x"82", + 4612 => x"27", + 4613 => x"16", + 4614 => x"ec", + 4615 => x"38", + 4616 => x"39", + 4617 => x"55", + 4618 => x"52", + 4619 => x"c6", + 4620 => x"ec", + 4621 => x"0c", + 4622 => x"0c", + 4623 => x"53", + 4624 => x"80", + 4625 => x"85", + 4626 => x"94", + 4627 => x"2a", + 4628 => x"0c", + 4629 => x"06", + 4630 => x"9c", + 4631 => x"58", + 4632 => x"ec", + 4633 => x"0d", + 4634 => x"0d", + 4635 => x"90", + 4636 => x"05", + 4637 => x"f0", + 4638 => x"27", + 4639 => x"0b", + 4640 => x"98", + 4641 => x"84", + 4642 => x"2e", + 4643 => x"76", + 4644 => x"58", + 4645 => x"38", + 4646 => x"15", + 4647 => x"08", + 4648 => x"38", + 4649 => x"88", + 4650 => x"53", + 4651 => x"81", + 4652 => x"c0", + 4653 => x"22", + 4654 => x"89", + 4655 => x"72", + 4656 => x"74", + 4657 => x"f3", + 4658 => x"85", + 4659 => x"82", + 4660 => x"82", + 4661 => x"27", + 4662 => x"81", + 4663 => x"ec", + 4664 => x"80", + 4665 => x"16", + 4666 => x"ec", + 4667 => x"ca", + 4668 => x"38", + 4669 => x"0c", + 4670 => x"dd", + 4671 => x"08", + 4672 => x"f8", + 4673 => x"85", + 4674 => x"87", + 4675 => x"ec", + 4676 => x"80", + 4677 => x"55", + 4678 => x"08", + 4679 => x"38", + 4680 => x"85", + 4681 => x"2e", + 4682 => x"85", + 4683 => x"75", + 4684 => x"3f", + 4685 => x"08", + 4686 => x"94", + 4687 => x"52", + 4688 => x"b2", + 4689 => x"ec", + 4690 => x"0c", + 4691 => x"0c", + 4692 => x"05", + 4693 => x"80", + 4694 => x"85", + 4695 => x"3d", + 4696 => x"3d", + 4697 => x"71", + 4698 => x"57", + 4699 => x"51", + 4700 => x"82", + 4701 => x"54", + 4702 => x"08", + 4703 => x"82", + 4704 => x"56", + 4705 => x"52", + 4706 => x"f4", + 4707 => x"ec", + 4708 => x"85", + 4709 => x"d2", + 4710 => x"ec", + 4711 => x"08", + 4712 => x"54", + 4713 => x"e5", + 4714 => x"06", + 4715 => x"58", + 4716 => x"08", + 4717 => x"38", + 4718 => x"75", + 4719 => x"80", + 4720 => x"81", + 4721 => x"7a", + 4722 => x"06", + 4723 => x"39", + 4724 => x"08", + 4725 => x"76", + 4726 => x"3f", + 4727 => x"08", + 4728 => x"ec", + 4729 => x"ff", + 4730 => x"84", + 4731 => x"06", + 4732 => x"54", + 4733 => x"ec", + 4734 => x"0d", + 4735 => x"0d", + 4736 => x"52", + 4737 => x"3f", + 4738 => x"08", + 4739 => x"06", + 4740 => x"51", + 4741 => x"83", + 4742 => x"06", + 4743 => x"14", + 4744 => x"3f", + 4745 => x"08", + 4746 => x"07", + 4747 => x"85", + 4748 => x"3d", + 4749 => x"3d", + 4750 => x"70", + 4751 => x"06", + 4752 => x"53", + 4753 => x"de", + 4754 => x"33", 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x"82", + 4814 => x"a0", + 4815 => x"82", + 4816 => x"52", + 4817 => x"51", + 4818 => x"8b", + 4819 => x"52", + 4820 => x"51", + 4821 => x"81", + 4822 => x"34", + 4823 => x"ec", + 4824 => x"0d", + 4825 => x"0d", + 4826 => x"98", + 4827 => x"70", + 4828 => x"ec", + 4829 => x"85", + 4830 => x"38", + 4831 => x"53", + 4832 => x"81", + 4833 => x"34", + 4834 => x"04", + 4835 => x"78", + 4836 => x"80", + 4837 => x"34", + 4838 => x"80", + 4839 => x"38", + 4840 => x"18", + 4841 => x"9c", + 4842 => x"70", + 4843 => x"56", + 4844 => x"a0", + 4845 => x"71", + 4846 => x"81", + 4847 => x"81", + 4848 => x"89", + 4849 => x"06", + 4850 => x"73", + 4851 => x"55", + 4852 => x"55", + 4853 => x"81", + 4854 => x"81", + 4855 => x"74", + 4856 => x"75", + 4857 => x"52", + 4858 => x"13", + 4859 => x"08", + 4860 => x"33", + 4861 => x"9c", + 4862 => x"11", + 4863 => x"fb", + 4864 => x"ec", + 4865 => x"96", + 4866 => x"d8", + 4867 => x"ec", + 4868 => x"23", + 4869 => x"e7", + 4870 => x"85", + 4871 => x"17", + 4872 => x"0d", + 4873 => x"0d", + 4874 => x"5e", + 4875 => x"70", + 4876 => x"55", + 4877 => x"83", + 4878 => x"73", + 4879 => x"91", + 4880 => x"2e", + 4881 => x"1d", + 4882 => x"0c", + 4883 => x"15", + 4884 => x"70", + 4885 => x"56", + 4886 => x"09", + 4887 => x"38", + 4888 => x"80", + 4889 => x"09", + 4890 => x"80", + 4891 => x"51", + 4892 => x"da", + 4893 => x"1c", + 4894 => x"33", + 4895 => x"9f", + 4896 => x"ff", + 4897 => x"1c", + 4898 => x"7a", + 4899 => x"3f", + 4900 => x"08", + 4901 => x"39", + 4902 => x"a0", + 4903 => x"5e", + 4904 => x"52", + 4905 => x"ee", + 4906 => x"59", + 4907 => x"33", + 4908 => x"ae", + 4909 => x"06", + 4910 => x"78", + 4911 => x"81", + 4912 => x"32", + 4913 => x"05", + 4914 => x"73", + 4915 => x"51", + 4916 => x"57", + 4917 => x"38", + 4918 => x"75", + 4919 => x"17", + 4920 => x"75", + 4921 => x"09", + 4922 => x"9f", + 4923 => x"54", + 4924 => x"2e", + 4925 => x"80", + 4926 => x"75", + 4927 => x"c7", + 4928 => x"7e", + 4929 => x"a0", + 4930 => x"c7", + 4931 => x"82", + 4932 => x"18", + 4933 => x"1a", + 4934 => x"a0", + 4935 => x"86", + 4936 => x"32", + 4937 => x"05", + 4938 => x"32", + 4939 => x"05", + 4940 => x"71", + 4941 => x"51", + 4942 => x"55", + 4943 => x"ae", + 4944 => x"81", + 4945 => x"78", + 4946 => x"51", + 4947 => x"af", + 4948 => x"06", + 4949 => x"55", + 4950 => x"32", + 4951 => x"05", + 4952 => x"77", + 4953 => x"54", + 4954 => x"81", + 4955 => x"ae", + 4956 => x"06", + 4957 => x"54", + 4958 => x"74", + 4959 => x"80", + 4960 => x"7b", + 4961 => x"09", + 4962 => x"ae", + 4963 => x"81", + 4964 => x"25", + 4965 => x"07", + 4966 => x"51", + 4967 => x"a7", + 4968 => x"8b", + 4969 => x"39", + 4970 => x"54", + 4971 => x"8c", + 4972 => x"ff", + 4973 => x"b4", + 4974 => x"54", + 4975 => x"c2", + 4976 => x"ec", + 4977 => x"b2", + 4978 => x"70", + 4979 => x"71", + 4980 => x"54", + 4981 => x"82", + 4982 => x"80", + 4983 => x"38", + 4984 => x"76", + 4985 => x"df", + 4986 => x"54", + 4987 => x"81", + 4988 => x"55", + 4989 => x"34", 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x"73", + 5049 => x"38", + 5050 => x"54", + 5051 => x"fb", + 5052 => x"80", + 5053 => x"34", + 5054 => x"c1", + 5055 => x"06", + 5056 => x"38", + 5057 => x"39", + 5058 => x"70", + 5059 => x"54", + 5060 => x"86", + 5061 => x"84", + 5062 => x"06", + 5063 => x"73", + 5064 => x"38", + 5065 => x"83", + 5066 => x"b4", + 5067 => x"51", + 5068 => x"82", + 5069 => x"88", + 5070 => x"dc", + 5071 => x"85", + 5072 => x"3d", + 5073 => x"3d", + 5074 => x"ff", + 5075 => x"71", + 5076 => x"5c", + 5077 => x"80", + 5078 => x"38", + 5079 => x"05", + 5080 => x"a0", + 5081 => x"71", + 5082 => x"38", + 5083 => x"71", + 5084 => x"81", + 5085 => x"38", + 5086 => x"11", + 5087 => x"06", + 5088 => x"70", + 5089 => x"38", + 5090 => x"81", + 5091 => x"05", + 5092 => x"76", + 5093 => x"38", + 5094 => x"ff", + 5095 => x"77", + 5096 => x"57", + 5097 => x"05", + 5098 => x"70", + 5099 => x"33", + 5100 => x"53", + 5101 => x"99", + 5102 => x"e0", + 5103 => x"ff", + 5104 => x"ff", + 5105 => x"70", + 5106 => x"38", + 5107 => x"81", + 5108 => x"51", + 5109 => x"05", + 5110 => x"51", + 5111 => x"2e", + 5112 => x"85", + 5113 => x"bc", + 5114 => x"81", + 5115 => x"32", + 5116 => x"05", + 5117 => x"9f", + 5118 => x"2a", + 5119 => x"54", + 5120 => x"2e", + 5121 => x"15", + 5122 => x"55", + 5123 => x"ff", + 5124 => x"39", + 5125 => x"86", + 5126 => x"7c", + 5127 => x"51", + 5128 => x"9d", + 5129 => x"70", + 5130 => x"0c", + 5131 => x"04", + 5132 => x"78", + 5133 => x"83", + 5134 => x"0b", + 5135 => x"79", + 5136 => x"e2", + 5137 => x"55", + 5138 => x"08", + 5139 => x"84", + 5140 => x"df", + 5141 => x"85", + 5142 => x"ff", + 5143 => x"83", + 5144 => x"d4", + 5145 => x"81", + 5146 => x"38", + 5147 => x"17", + 5148 => x"74", + 5149 => x"09", + 5150 => x"38", + 5151 => x"81", + 5152 => x"09", + 5153 => x"80", + 5154 => x"51", + 5155 => x"8a", + 5156 => x"e8", + 5157 => x"06", + 5158 => x"53", + 5159 => x"52", + 5160 => x"51", + 5161 => x"82", + 5162 => x"55", + 5163 => x"08", + 5164 => x"38", + 5165 => x"fe", + 5166 => x"86", + 5167 => x"f0", + 5168 => x"ec", + 5169 => x"85", + 5170 => x"2e", + 5171 => x"55", + 5172 => x"ec", + 5173 => x"0d", + 5174 => x"0d", + 5175 => x"05", + 5176 => x"33", + 5177 => x"75", + 5178 => x"fc", + 5179 => x"85", + 5180 => x"8b", + 5181 => x"82", + 5182 => x"24", + 5183 => x"82", + 5184 => x"82", + 5185 => x"90", + 5186 => x"53", + 5187 => x"80", + 5188 => x"38", + 5189 => x"76", + 5190 => x"74", + 5191 => x"72", + 5192 => x"38", + 5193 => x"51", + 5194 => x"82", + 5195 => x"81", + 5196 => x"81", + 5197 => x"72", + 5198 => x"80", + 5199 => x"38", + 5200 => x"70", + 5201 => x"53", + 5202 => x"86", + 5203 => x"af", + 5204 => x"34", + 5205 => x"34", + 5206 => x"14", + 5207 => x"8c", + 5208 => x"ec", + 5209 => x"06", + 5210 => x"54", + 5211 => x"72", + 5212 => x"76", + 5213 => x"38", + 5214 => x"70", + 5215 => x"53", + 5216 => x"85", + 5217 => x"70", + 5218 => x"5c", + 5219 => x"82", + 5220 => x"81", + 5221 => x"76", + 5222 => x"81", + 5223 => x"38", + 5224 => x"56", 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x"86", + 5284 => x"83", + 5285 => x"c5", + 5286 => x"c8", + 5287 => x"ec", + 5288 => x"85", + 5289 => x"15", + 5290 => x"06", + 5291 => x"76", + 5292 => x"80", + 5293 => x"da", + 5294 => x"85", + 5295 => x"ff", + 5296 => x"74", + 5297 => x"d4", + 5298 => x"af", + 5299 => x"ec", + 5300 => x"c2", + 5301 => x"8c", + 5302 => x"ec", + 5303 => x"ff", + 5304 => x"56", + 5305 => x"83", + 5306 => x"14", + 5307 => x"71", + 5308 => x"5a", + 5309 => x"26", + 5310 => x"8a", + 5311 => x"74", + 5312 => x"fe", + 5313 => x"82", + 5314 => x"53", + 5315 => x"08", + 5316 => x"ed", + 5317 => x"ec", + 5318 => x"ff", + 5319 => x"83", + 5320 => x"72", + 5321 => x"26", + 5322 => x"57", + 5323 => x"26", + 5324 => x"57", + 5325 => x"56", + 5326 => x"82", + 5327 => x"13", + 5328 => x"0c", + 5329 => x"0c", + 5330 => x"a4", + 5331 => x"1e", + 5332 => x"54", + 5333 => x"2e", + 5334 => x"af", + 5335 => x"14", + 5336 => x"3f", + 5337 => x"08", + 5338 => x"06", + 5339 => x"72", + 5340 => x"7a", + 5341 => x"80", + 5342 => x"d8", + 5343 => x"85", + 5344 => x"15", + 5345 => x"2b", + 5346 => x"8d", + 5347 => x"2e", + 5348 => x"77", + 5349 => x"0c", + 5350 => x"76", + 5351 => x"38", + 5352 => x"11", + 5353 => x"81", + 5354 => x"51", + 5355 => x"13", + 5356 => x"8d", + 5357 => x"15", + 5358 => x"c5", + 5359 => x"90", + 5360 => x"0b", + 5361 => x"ff", + 5362 => x"15", + 5363 => x"2e", + 5364 => x"81", + 5365 => x"e4", + 5366 => x"88", + 5367 => x"ec", + 5368 => x"ff", + 5369 => x"81", + 5370 => x"06", + 5371 => x"81", + 5372 => x"51", + 5373 => x"82", + 5374 => x"80", + 5375 => x"85", + 5376 => x"15", + 5377 => x"14", + 5378 => x"3f", + 5379 => x"08", + 5380 => x"06", + 5381 => x"d4", + 5382 => x"81", + 5383 => x"38", + 5384 => x"d7", + 5385 => x"85", + 5386 => x"8b", + 5387 => x"2e", + 5388 => x"b3", + 5389 => x"14", + 5390 => x"3f", + 5391 => x"08", + 5392 => x"e4", + 5393 => x"81", + 5394 => x"84", + 5395 => x"d7", + 5396 => x"85", + 5397 => x"15", + 5398 => x"14", + 5399 => x"3f", + 5400 => x"08", + 5401 => x"76", + 5402 => x"9d", + 5403 => x"05", + 5404 => x"9d", + 5405 => x"86", + 5406 => x"0b", + 5407 => x"80", + 5408 => x"85", + 5409 => x"3d", + 5410 => x"3d", + 5411 => x"89", + 5412 => x"2e", + 5413 => x"08", + 5414 => x"2e", + 5415 => x"33", + 5416 => x"2e", + 5417 => x"13", + 5418 => x"22", + 5419 => x"76", + 5420 => x"06", + 5421 => x"13", + 5422 => x"92", + 5423 => x"ec", + 5424 => x"52", + 5425 => x"71", + 5426 => x"55", + 5427 => x"53", + 5428 => x"0c", + 5429 => x"85", + 5430 => x"3d", + 5431 => x"3d", + 5432 => x"05", + 5433 => x"89", + 5434 => x"52", + 5435 => x"3f", + 5436 => x"0b", + 5437 => x"08", + 5438 => x"82", + 5439 => x"82", + 5440 => x"90", + 5441 => x"55", + 5442 => x"2e", + 5443 => x"74", + 5444 => x"73", + 5445 => x"38", + 5446 => x"78", + 5447 => x"54", + 5448 => x"92", + 5449 => x"89", + 5450 => x"84", + 5451 => x"a9", + 5452 => x"ec", + 5453 => x"82", + 5454 => x"88", + 5455 => x"eb", + 5456 => x"02", + 5457 => x"e7", + 5458 => x"59", + 5459 => x"80", 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x"d4", + 5519 => x"97", + 5520 => x"ec", + 5521 => x"85", + 5522 => x"cc", + 5523 => x"74", + 5524 => x"02", + 5525 => x"70", + 5526 => x"81", + 5527 => x"56", + 5528 => x"86", + 5529 => x"82", + 5530 => x"81", + 5531 => x"06", + 5532 => x"80", + 5533 => x"75", + 5534 => x"73", + 5535 => x"38", + 5536 => x"94", + 5537 => x"7a", + 5538 => x"3f", + 5539 => x"08", + 5540 => x"8c", + 5541 => x"55", + 5542 => x"08", + 5543 => x"77", + 5544 => x"81", + 5545 => x"73", + 5546 => x"38", + 5547 => x"07", + 5548 => x"11", + 5549 => x"0c", + 5550 => x"0c", + 5551 => x"52", + 5552 => x"3f", + 5553 => x"08", + 5554 => x"08", + 5555 => x"63", + 5556 => x"5a", + 5557 => x"82", + 5558 => x"82", + 5559 => x"8c", + 5560 => x"7a", + 5561 => x"17", + 5562 => x"23", + 5563 => x"34", + 5564 => x"1a", + 5565 => x"9c", + 5566 => x"0b", + 5567 => x"77", + 5568 => x"81", + 5569 => x"73", + 5570 => x"8f", + 5571 => x"ec", + 5572 => x"81", + 5573 => x"85", + 5574 => x"1a", + 5575 => x"22", + 5576 => x"7b", + 5577 => x"a8", + 5578 => x"78", + 5579 => x"3f", + 5580 => x"08", + 5581 => x"ec", + 5582 => x"83", + 5583 => x"82", + 5584 => x"ff", + 5585 => x"06", + 5586 => x"55", + 5587 => x"56", + 5588 => x"05", + 5589 => x"80", + 5590 => x"77", + 5591 => x"38", + 5592 => x"06", + 5593 => x"c1", + 5594 => x"1a", + 5595 => x"38", + 5596 => x"06", + 5597 => x"2e", + 5598 => x"52", + 5599 => x"f6", + 5600 => x"ec", + 5601 => x"82", + 5602 => x"75", + 5603 => x"85", + 5604 => x"9c", + 5605 => x"39", + 5606 => x"74", + 5607 => x"85", + 5608 => x"3d", + 5609 => x"3d", + 5610 => x"65", + 5611 => x"5d", + 5612 => x"0c", + 5613 => x"05", + 5614 => x"f9", + 5615 => x"85", + 5616 => x"82", + 5617 => x"8a", + 5618 => x"33", + 5619 => x"2e", + 5620 => x"56", + 5621 => x"90", + 5622 => x"06", + 5623 => x"74", + 5624 => x"b6", + 5625 => x"82", + 5626 => x"34", + 5627 => x"aa", + 5628 => x"91", + 5629 => x"56", + 5630 => x"8c", + 5631 => x"1a", + 5632 => x"74", + 5633 => x"38", + 5634 => x"80", + 5635 => x"38", + 5636 => x"70", + 5637 => x"56", + 5638 => x"b2", + 5639 => x"11", + 5640 => x"77", + 5641 => x"5b", + 5642 => x"38", + 5643 => x"88", + 5644 => x"8f", + 5645 => x"08", + 5646 => x"d4", + 5647 => x"85", + 5648 => x"81", + 5649 => x"9f", + 5650 => x"2e", + 5651 => x"74", + 5652 => x"98", + 5653 => x"7e", + 5654 => x"3f", + 5655 => x"08", + 5656 => x"83", + 5657 => x"ec", + 5658 => x"89", + 5659 => x"77", + 5660 => x"d6", + 5661 => x"7f", + 5662 => x"58", + 5663 => x"75", + 5664 => x"75", + 5665 => x"77", + 5666 => x"7c", + 5667 => x"33", + 5668 => x"3f", + 5669 => x"08", + 5670 => x"7e", + 5671 => x"56", + 5672 => x"2e", + 5673 => x"16", + 5674 => x"55", + 5675 => x"94", + 5676 => x"53", + 5677 => x"b0", + 5678 => x"31", + 5679 => x"05", + 5680 => x"3f", + 5681 => x"56", + 5682 => x"9c", + 5683 => x"19", + 5684 => x"06", + 5685 => x"31", + 5686 => x"76", + 5687 => x"7b", + 5688 => x"08", + 5689 => x"d1", + 5690 => x"85", + 5691 => x"81", + 5692 => x"94", + 5693 => x"ff", + 5694 => x"05", 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x"85", + 5754 => x"19", + 5755 => x"b0", + 5756 => x"19", + 5757 => x"81", + 5758 => x"74", + 5759 => x"3f", + 5760 => x"08", + 5761 => x"98", + 5762 => x"7e", + 5763 => x"3f", + 5764 => x"08", + 5765 => x"d2", + 5766 => x"ec", + 5767 => x"89", + 5768 => x"78", + 5769 => x"d5", + 5770 => x"7f", + 5771 => x"58", + 5772 => x"75", + 5773 => x"75", + 5774 => x"78", + 5775 => x"7c", + 5776 => x"33", + 5777 => x"3f", + 5778 => x"08", + 5779 => x"7e", + 5780 => x"78", + 5781 => x"74", + 5782 => x"38", + 5783 => x"b0", + 5784 => x"31", + 5785 => x"05", + 5786 => x"51", + 5787 => x"7e", + 5788 => x"83", + 5789 => x"89", + 5790 => x"db", + 5791 => x"08", + 5792 => x"26", + 5793 => x"51", + 5794 => x"82", + 5795 => x"fd", + 5796 => x"77", + 5797 => x"55", + 5798 => x"0c", + 5799 => x"83", + 5800 => x"80", + 5801 => x"55", + 5802 => x"83", + 5803 => x"9c", + 5804 => x"7e", + 5805 => x"3f", + 5806 => x"08", + 5807 => x"75", + 5808 => x"94", + 5809 => x"ff", + 5810 => x"05", + 5811 => x"3f", + 5812 => x"0b", + 5813 => x"7b", + 5814 => x"08", + 5815 => x"76", + 5816 => x"08", + 5817 => x"1c", + 5818 => x"08", + 5819 => x"5c", + 5820 => x"83", + 5821 => x"74", + 5822 => x"fd", + 5823 => x"18", + 5824 => x"07", + 5825 => x"19", + 5826 => x"75", + 5827 => x"0c", + 5828 => x"04", + 5829 => x"7a", + 5830 => x"05", + 5831 => x"56", + 5832 => x"82", + 5833 => x"57", + 5834 => x"08", + 5835 => x"90", + 5836 => x"86", + 5837 => x"06", + 5838 => x"73", + 5839 => x"e9", + 5840 => x"08", + 5841 => x"cc", + 5842 => x"85", + 5843 => x"82", + 5844 => x"80", + 5845 => x"16", + 5846 => x"33", + 5847 => x"55", + 5848 => x"34", + 5849 => x"53", + 5850 => x"08", + 5851 => x"3f", + 5852 => x"52", + 5853 => x"c9", + 5854 => x"88", + 5855 => x"96", + 5856 => x"c0", + 5857 => x"92", + 5858 => x"9a", + 5859 => x"81", + 5860 => x"34", + 5861 => x"af", + 5862 => x"ec", + 5863 => x"33", + 5864 => x"55", + 5865 => x"17", + 5866 => x"85", + 5867 => x"3d", + 5868 => x"3d", + 5869 => x"52", + 5870 => x"3f", + 5871 => x"08", + 5872 => x"ec", + 5873 => x"86", + 5874 => x"52", + 5875 => x"ba", + 5876 => x"ec", + 5877 => x"85", + 5878 => x"38", + 5879 => x"08", + 5880 => x"82", + 5881 => x"86", + 5882 => x"ff", + 5883 => x"3d", + 5884 => x"3f", + 5885 => x"0b", + 5886 => x"08", + 5887 => x"82", + 5888 => x"82", + 5889 => x"80", + 5890 => x"85", + 5891 => x"3d", + 5892 => x"3d", + 5893 => x"93", + 5894 => x"52", + 5895 => x"e9", + 5896 => x"85", + 5897 => x"82", + 5898 => x"80", + 5899 => x"58", + 5900 => x"3d", + 5901 => x"df", + 5902 => x"85", + 5903 => x"82", + 5904 => x"bc", + 5905 => x"c7", + 5906 => x"98", + 5907 => x"73", + 5908 => x"38", + 5909 => x"12", + 5910 => x"39", + 5911 => x"33", + 5912 => x"70", + 5913 => x"55", + 5914 => x"2e", + 5915 => x"7f", + 5916 => x"54", + 5917 => x"82", + 5918 => x"94", + 5919 => x"39", + 5920 => x"08", + 5921 => x"81", + 5922 => x"85", + 5923 => x"85", + 5924 => x"3d", + 5925 => x"3d", + 5926 => x"5b", + 5927 => x"34", + 5928 => x"3d", + 5929 => x"52", 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x"38", + 5989 => x"05", + 5990 => x"6f", + 5991 => x"ff", + 5992 => x"55", + 5993 => x"74", + 5994 => x"38", + 5995 => x"11", + 5996 => x"74", + 5997 => x"39", + 5998 => x"09", + 5999 => x"38", + 6000 => x"11", + 6001 => x"74", + 6002 => x"82", + 6003 => x"70", + 6004 => x"ff", + 6005 => x"70", + 6006 => x"56", + 6007 => x"76", + 6008 => x"81", + 6009 => x"70", + 6010 => x"56", + 6011 => x"82", + 6012 => x"78", + 6013 => x"80", + 6014 => x"27", + 6015 => x"19", + 6016 => x"7a", + 6017 => x"5c", + 6018 => x"55", + 6019 => x"7a", + 6020 => x"5c", + 6021 => x"2e", + 6022 => x"85", + 6023 => x"94", + 6024 => x"81", + 6025 => x"73", + 6026 => x"81", + 6027 => x"7a", + 6028 => x"38", + 6029 => x"76", + 6030 => x"0c", + 6031 => x"04", + 6032 => x"7b", + 6033 => x"fc", + 6034 => x"53", + 6035 => x"ba", + 6036 => x"ec", + 6037 => x"85", + 6038 => x"fc", + 6039 => x"33", + 6040 => x"f4", + 6041 => x"08", + 6042 => x"27", + 6043 => x"15", + 6044 => x"2a", + 6045 => x"51", + 6046 => x"83", + 6047 => x"94", + 6048 => x"80", + 6049 => x"0c", + 6050 => x"2e", + 6051 => x"79", + 6052 => x"70", + 6053 => x"51", + 6054 => x"2e", + 6055 => x"52", + 6056 => x"fe", + 6057 => x"82", + 6058 => x"ff", + 6059 => x"70", + 6060 => x"fe", + 6061 => x"82", + 6062 => x"73", + 6063 => x"76", + 6064 => x"70", + 6065 => x"94", + 6066 => x"71", + 6067 => x"08", + 6068 => x"53", + 6069 => x"15", + 6070 => x"a6", + 6071 => x"74", + 6072 => x"3f", + 6073 => x"08", + 6074 => x"ec", + 6075 => x"81", + 6076 => x"85", + 6077 => x"2e", + 6078 => x"82", + 6079 => x"88", + 6080 => x"98", + 6081 => x"80", + 6082 => x"38", + 6083 => x"80", + 6084 => x"77", + 6085 => x"08", + 6086 => x"0c", + 6087 => x"70", + 6088 => x"81", + 6089 => x"5a", + 6090 => x"2e", + 6091 => x"52", + 6092 => x"cf", + 6093 => x"ec", + 6094 => x"85", + 6095 => x"38", + 6096 => x"08", + 6097 => x"73", + 6098 => x"c6", + 6099 => x"85", + 6100 => x"73", + 6101 => x"38", + 6102 => x"af", + 6103 => x"73", + 6104 => x"27", + 6105 => x"98", + 6106 => x"a0", + 6107 => x"08", + 6108 => x"0c", + 6109 => x"06", + 6110 => x"2e", + 6111 => x"52", + 6112 => x"f2", + 6113 => x"ec", + 6114 => x"82", + 6115 => x"34", + 6116 => x"c4", + 6117 => x"91", + 6118 => x"53", + 6119 => x"89", + 6120 => x"ec", + 6121 => x"94", + 6122 => x"8c", + 6123 => x"27", + 6124 => x"8c", + 6125 => x"15", + 6126 => x"07", + 6127 => x"16", + 6128 => x"ff", + 6129 => x"80", + 6130 => x"77", + 6131 => x"2e", + 6132 => x"9c", + 6133 => x"53", + 6134 => x"ec", + 6135 => x"0d", + 6136 => x"0d", + 6137 => x"54", + 6138 => x"81", + 6139 => x"53", + 6140 => x"05", + 6141 => x"84", + 6142 => x"dd", + 6143 => x"ec", + 6144 => x"85", + 6145 => x"ea", + 6146 => x"0c", + 6147 => x"51", + 6148 => x"82", + 6149 => x"55", + 6150 => x"08", + 6151 => x"ab", + 6152 => x"98", + 6153 => x"80", + 6154 => x"38", + 6155 => x"70", + 6156 => x"81", + 6157 => x"57", + 6158 => x"ad", + 6159 => x"08", + 6160 => x"d3", + 6161 => x"85", + 6162 => x"17", + 6163 => x"86", + 6164 => x"17", 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x"08", + 6224 => x"52", + 6225 => x"dd", + 6226 => x"ec", + 6227 => x"85", + 6228 => x"38", + 6229 => x"05", + 6230 => x"2b", + 6231 => x"80", + 6232 => x"86", + 6233 => x"76", + 6234 => x"38", + 6235 => x"51", + 6236 => x"74", + 6237 => x"0c", + 6238 => x"04", + 6239 => x"63", + 6240 => x"80", + 6241 => x"ec", + 6242 => x"3d", + 6243 => x"3f", + 6244 => x"08", + 6245 => x"ec", + 6246 => x"38", + 6247 => x"73", + 6248 => x"08", + 6249 => x"13", + 6250 => x"58", + 6251 => x"26", + 6252 => x"7c", + 6253 => x"39", + 6254 => x"d3", + 6255 => x"81", + 6256 => x"85", + 6257 => x"33", + 6258 => x"81", + 6259 => x"06", + 6260 => x"82", + 6261 => x"76", + 6262 => x"f0", + 6263 => x"c7", + 6264 => x"ec", + 6265 => x"d0", + 6266 => x"ec", + 6267 => x"cd", + 6268 => x"ec", + 6269 => x"05", + 6270 => x"ec", + 6271 => x"25", + 6272 => x"19", + 6273 => x"5a", + 6274 => x"08", + 6275 => x"38", + 6276 => x"a4", + 6277 => x"85", + 6278 => x"58", + 6279 => x"77", + 6280 => x"7d", + 6281 => x"be", + 6282 => x"85", + 6283 => x"82", + 6284 => x"80", + 6285 => x"70", + 6286 => x"ff", + 6287 => x"56", + 6288 => x"2e", + 6289 => x"a0", + 6290 => x"51", + 6291 => x"3f", + 6292 => x"08", + 6293 => x"06", + 6294 => x"05", + 6295 => x"1b", + 6296 => x"5b", + 6297 => x"39", + 6298 => x"ff", + 6299 => x"82", + 6300 => x"f0", + 6301 => x"09", + 6302 => x"80", + 6303 => x"19", + 6304 => x"54", + 6305 => x"06", + 6306 => x"79", + 6307 => x"78", + 6308 => x"79", + 6309 => x"84", + 6310 => x"07", + 6311 => x"84", + 6312 => x"82", + 6313 => x"92", + 6314 => x"f9", + 6315 => x"8a", + 6316 => x"53", + 6317 => x"e3", + 6318 => x"85", + 6319 => x"82", + 6320 => x"81", + 6321 => x"17", + 6322 => x"81", + 6323 => x"17", + 6324 => x"2a", + 6325 => x"51", + 6326 => x"55", + 6327 => x"81", + 6328 => x"17", + 6329 => x"8c", + 6330 => x"81", + 6331 => x"9b", + 6332 => x"ec", + 6333 => x"17", + 6334 => x"51", + 6335 => x"82", + 6336 => x"74", + 6337 => x"56", + 6338 => x"98", + 6339 => x"76", + 6340 => x"93", + 6341 => x"ec", + 6342 => x"09", + 6343 => x"38", + 6344 => x"85", + 6345 => x"2e", + 6346 => x"85", + 6347 => x"a3", + 6348 => x"38", + 6349 => x"85", + 6350 => x"15", + 6351 => x"38", + 6352 => x"53", + 6353 => x"08", + 6354 => x"c3", + 6355 => x"85", + 6356 => x"94", + 6357 => x"18", + 6358 => x"33", + 6359 => x"54", + 6360 => x"34", + 6361 => x"85", + 6362 => x"18", + 6363 => x"74", + 6364 => x"0c", + 6365 => x"04", + 6366 => x"82", + 6367 => x"ff", + 6368 => x"a1", + 6369 => x"d1", + 6370 => x"ec", + 6371 => x"85", + 6372 => x"f7", + 6373 => x"a1", + 6374 => x"95", + 6375 => x"58", + 6376 => x"82", + 6377 => x"55", + 6378 => x"08", + 6379 => x"02", + 6380 => x"33", + 6381 => x"70", + 6382 => x"55", + 6383 => x"73", + 6384 => x"75", + 6385 => x"80", + 6386 => x"bf", + 6387 => x"d6", + 6388 => x"81", + 6389 => x"87", + 6390 => x"af", + 6391 => x"78", + 6392 => x"3f", + 6393 => x"08", + 6394 => x"70", + 6395 => x"55", + 6396 => x"2e", + 6397 => x"78", + 6398 => x"ec", + 6399 => x"08", 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x"5a", + 6459 => x"3d", + 6460 => x"c1", + 6461 => x"85", + 6462 => x"55", + 6463 => x"ec", + 6464 => x"87", + 6465 => x"ec", + 6466 => x"09", + 6467 => x"38", + 6468 => x"85", + 6469 => x"2e", + 6470 => x"86", + 6471 => x"81", + 6472 => x"81", + 6473 => x"85", + 6474 => x"78", + 6475 => x"3f", + 6476 => x"08", + 6477 => x"ec", + 6478 => x"38", + 6479 => x"52", + 6480 => x"ff", + 6481 => x"78", + 6482 => x"b4", + 6483 => x"54", + 6484 => x"15", + 6485 => x"b2", + 6486 => x"ca", + 6487 => x"b5", + 6488 => x"53", + 6489 => x"53", + 6490 => x"3f", + 6491 => x"b4", + 6492 => x"d4", + 6493 => x"b5", + 6494 => x"54", + 6495 => x"d5", + 6496 => x"53", + 6497 => x"11", + 6498 => x"aa", + 6499 => x"81", + 6500 => x"34", + 6501 => x"f7", + 6502 => x"ec", + 6503 => x"85", + 6504 => x"38", + 6505 => x"0a", + 6506 => x"05", + 6507 => x"94", + 6508 => x"64", + 6509 => x"c8", + 6510 => x"54", + 6511 => x"15", + 6512 => x"81", + 6513 => x"34", + 6514 => x"b7", + 6515 => x"85", + 6516 => x"8b", + 6517 => x"75", + 6518 => x"ff", + 6519 => x"73", + 6520 => x"0c", + 6521 => x"04", + 6522 => x"a9", + 6523 => x"51", + 6524 => x"82", + 6525 => x"ff", + 6526 => x"a9", + 6527 => x"d9", + 6528 => x"ec", + 6529 => x"85", + 6530 => x"d3", + 6531 => x"a9", + 6532 => x"9d", + 6533 => x"58", + 6534 => x"82", + 6535 => x"55", + 6536 => x"08", + 6537 => x"02", + 6538 => x"33", + 6539 => x"54", + 6540 => x"82", + 6541 => x"53", + 6542 => x"52", + 6543 => x"88", + 6544 => x"b4", + 6545 => x"53", + 6546 => x"3d", + 6547 => x"ff", + 6548 => x"aa", + 6549 => x"73", + 6550 => x"3f", + 6551 => x"08", + 6552 => x"ec", + 6553 => x"63", + 6554 => x"81", + 6555 => x"65", + 6556 => x"2e", + 6557 => x"55", + 6558 => x"82", + 6559 => x"84", + 6560 => x"06", + 6561 => x"73", + 6562 => x"3f", + 6563 => x"08", + 6564 => x"ec", + 6565 => x"38", + 6566 => x"53", + 6567 => x"95", + 6568 => x"16", + 6569 => x"cb", + 6570 => x"05", + 6571 => x"34", + 6572 => x"70", + 6573 => x"81", + 6574 => x"55", + 6575 => x"74", + 6576 => x"73", + 6577 => x"78", + 6578 => x"83", + 6579 => x"16", + 6580 => x"2a", + 6581 => x"51", + 6582 => x"80", + 6583 => x"38", + 6584 => x"80", + 6585 => x"52", + 6586 => x"91", + 6587 => x"ec", + 6588 => x"51", + 6589 => x"3f", + 6590 => x"85", + 6591 => x"2e", + 6592 => x"82", + 6593 => x"52", + 6594 => x"b4", + 6595 => x"85", + 6596 => x"80", + 6597 => x"58", + 6598 => x"ec", + 6599 => x"38", + 6600 => x"54", + 6601 => x"09", + 6602 => x"38", + 6603 => x"52", + 6604 => x"82", + 6605 => x"81", + 6606 => x"34", + 6607 => x"85", + 6608 => x"38", + 6609 => x"9d", + 6610 => x"ec", + 6611 => x"85", + 6612 => x"38", + 6613 => x"b4", + 6614 => x"85", + 6615 => x"74", + 6616 => x"0c", + 6617 => x"04", + 6618 => x"02", + 6619 => x"33", + 6620 => x"80", + 6621 => x"57", + 6622 => x"95", + 6623 => x"52", + 6624 => x"d2", + 6625 => x"85", + 6626 => x"82", + 6627 => x"80", + 6628 => x"5a", + 6629 => x"3d", + 6630 => x"c9", + 6631 => x"85", + 6632 => x"82", + 6633 => x"b8", + 6634 => x"cf", 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x"5d", + 6694 => x"52", + 6695 => x"52", + 6696 => x"fa", + 6697 => x"ec", + 6698 => x"85", + 6699 => x"d1", + 6700 => x"73", + 6701 => x"3f", + 6702 => x"08", + 6703 => x"ec", + 6704 => x"82", + 6705 => x"82", + 6706 => x"65", + 6707 => x"78", + 6708 => x"7b", + 6709 => x"55", + 6710 => x"34", + 6711 => x"8a", + 6712 => x"38", + 6713 => x"1a", + 6714 => x"34", + 6715 => x"9e", + 6716 => x"70", + 6717 => x"51", + 6718 => x"a0", + 6719 => x"8e", + 6720 => x"2e", + 6721 => x"86", + 6722 => x"34", + 6723 => x"09", + 6724 => x"78", + 6725 => x"51", + 6726 => x"2e", + 6727 => x"73", + 6728 => x"38", + 6729 => x"08", + 6730 => x"b0", + 6731 => x"85", + 6732 => x"82", + 6733 => x"a7", + 6734 => x"33", + 6735 => x"c3", + 6736 => x"2e", + 6737 => x"e4", + 6738 => x"2e", + 6739 => x"56", + 6740 => x"05", + 6741 => x"a3", + 6742 => x"ec", + 6743 => x"76", + 6744 => x"0c", + 6745 => x"04", + 6746 => x"82", + 6747 => x"ff", + 6748 => x"9d", + 6749 => x"e1", + 6750 => x"ec", + 6751 => x"ec", + 6752 => x"82", + 6753 => x"83", + 6754 => x"53", + 6755 => x"3d", + 6756 => x"ff", + 6757 => x"73", + 6758 => x"70", + 6759 => x"52", + 6760 => x"9f", + 6761 => x"bc", + 6762 => x"74", + 6763 => x"6d", + 6764 => x"70", + 6765 => x"ae", + 6766 => x"85", + 6767 => x"2e", + 6768 => x"70", + 6769 => x"57", + 6770 => x"bd", + 6771 => x"ec", + 6772 => x"8d", + 6773 => x"2b", + 6774 => x"81", + 6775 => x"86", + 6776 => x"ec", + 6777 => x"9f", + 6778 => x"ff", + 6779 => x"54", + 6780 => x"8a", + 6781 => x"70", + 6782 => x"06", + 6783 => x"ff", + 6784 => x"38", + 6785 => x"15", + 6786 => x"80", + 6787 => x"74", + 6788 => x"b4", + 6789 => x"c9", + 6790 => x"ec", + 6791 => x"81", + 6792 => x"88", + 6793 => x"26", + 6794 => x"39", + 6795 => x"86", + 6796 => x"81", + 6797 => x"ff", + 6798 => x"38", + 6799 => x"54", + 6800 => x"81", + 6801 => x"81", + 6802 => x"78", + 6803 => x"5a", + 6804 => x"6d", + 6805 => x"81", + 6806 => x"57", + 6807 => x"9f", + 6808 => x"38", + 6809 => x"54", + 6810 => x"81", + 6811 => x"b1", + 6812 => x"2e", + 6813 => x"a7", + 6814 => x"15", + 6815 => x"54", + 6816 => x"09", + 6817 => x"38", + 6818 => x"76", + 6819 => x"41", + 6820 => x"52", + 6821 => x"52", + 6822 => x"82", + 6823 => x"ec", + 6824 => x"85", + 6825 => x"f7", + 6826 => x"74", + 6827 => x"b4", + 6828 => x"ec", + 6829 => x"85", + 6830 => x"38", + 6831 => x"38", + 6832 => x"74", + 6833 => x"39", + 6834 => x"08", + 6835 => x"81", + 6836 => x"38", + 6837 => x"74", + 6838 => x"38", + 6839 => x"51", + 6840 => x"3f", + 6841 => x"08", + 6842 => x"ec", + 6843 => x"a0", + 6844 => x"ec", + 6845 => x"51", + 6846 => x"3f", + 6847 => x"0b", + 6848 => x"8b", + 6849 => x"67", + 6850 => x"e7", + 6851 => x"81", + 6852 => x"34", + 6853 => x"ad", + 6854 => x"85", + 6855 => x"73", + 6856 => x"85", + 6857 => x"3d", + 6858 => x"3d", + 6859 => x"02", + 6860 => x"cb", + 6861 => x"3d", + 6862 => x"72", + 6863 => x"5a", + 6864 => x"82", + 6865 => x"58", + 6866 => x"08", + 6867 => x"91", + 6868 => x"77", + 6869 => x"7c", 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7751 => x"2e", + 7752 => x"00", + 7753 => x"43", + 7754 => x"69", + 7755 => x"2e", + 7756 => x"43", + 7757 => x"61", + 7758 => x"67", + 7759 => x"00", + 7760 => x"25", + 7761 => x"78", + 7762 => x"38", + 7763 => x"3e", + 7764 => x"6c", + 7765 => x"30", + 7766 => x"0a", + 7767 => x"44", + 7768 => x"20", + 7769 => x"6f", + 7770 => x"00", + 7771 => x"0a", + 7772 => x"70", + 7773 => x"65", + 7774 => x"25", + 7775 => x"20", + 7776 => x"58", + 7777 => x"3f", + 7778 => x"00", + 7779 => x"25", + 7780 => x"20", + 7781 => x"58", + 7782 => x"25", + 7783 => x"20", + 7784 => x"58", + 7785 => x"45", + 7786 => x"75", + 7787 => x"67", + 7788 => x"64", + 7789 => x"20", + 7790 => x"78", + 7791 => x"2e", + 7792 => x"43", + 7793 => x"69", + 7794 => x"63", + 7795 => x"20", + 7796 => x"30", + 7797 => x"2e", + 7798 => x"00", + 7799 => x"43", + 7800 => x"20", + 7801 => x"75", + 7802 => x"64", + 7803 => x"64", + 7804 => x"25", + 7805 => x"0a", + 7806 => x"52", + 7807 => x"61", + 7808 => x"6e", + 7809 => x"70", + 7810 => x"63", + 7811 => x"6f", + 7812 => x"2e", + 7813 => x"43", + 7814 => x"20", + 7815 => x"6f", + 7816 => x"6e", + 7817 => x"2e", + 7818 => x"5a", + 7819 => x"62", + 7820 => x"25", + 7821 => x"25", + 7822 => x"73", + 7823 => x"00", + 7824 => x"25", + 7825 => x"25", + 7826 => x"73", + 7827 => x"25", + 7828 => x"25", + 7829 => x"42", + 7830 => x"63", + 7831 => x"61", + 7832 => x"0a", + 7833 => x"52", + 7834 => x"69", + 7835 => x"2e", + 7836 => x"45", + 7837 => x"6c", + 7838 => x"20", + 7839 => x"65", + 7840 => x"70", + 7841 => x"2e", + 7842 => x"25", + 7843 => x"64", + 7844 => x"20", + 7845 => x"25", + 7846 => x"64", + 7847 => x"25", + 7848 => x"53", + 7849 => x"43", + 7850 => x"69", + 7851 => x"61", + 7852 => x"6e", + 7853 => x"20", + 7854 => x"6f", + 7855 => x"6f", + 7856 => x"6f", + 7857 => x"67", + 7858 => x"3a", + 7859 => x"76", + 7860 => x"73", + 7861 => x"70", + 7862 => x"65", + 7863 => x"64", + 7864 => x"20", + 7865 => x"57", + 7866 => x"44", + 7867 => x"20", + 7868 => x"30", + 7869 => x"25", + 7870 => x"29", + 7871 => x"20", + 7872 => x"53", + 7873 => x"4d", + 7874 => x"20", + 7875 => x"30", + 7876 => x"25", + 7877 => x"29", + 7878 => x"20", + 7879 => x"49", + 7880 => x"20", + 7881 => x"4d", + 7882 => x"30", + 7883 => x"25", + 7884 => x"29", + 7885 => x"20", + 7886 => x"42", + 7887 => x"20", + 7888 => x"20", + 7889 => x"30", + 7890 => x"25", + 7891 => x"29", + 7892 => x"20", + 7893 => x"52", + 7894 => x"20", + 7895 => x"20", + 7896 => x"30", + 7897 => x"25", + 7898 => x"29", + 7899 => x"20", + 7900 => x"53", + 7901 => x"41", + 7902 => x"20", + 7903 => x"65", + 7904 => x"65", + 7905 => x"25", + 7906 => x"29", + 7907 => x"20", + 7908 => x"54", + 7909 => x"52", + 7910 => x"20", + 7911 => x"69", + 7912 => x"73", + 7913 => x"25", + 7914 => x"29", + 7915 => x"20", + 7916 => x"49", + 7917 => x"20", + 7918 => x"4c", + 7919 => x"68", + 7920 => x"65", + 7921 => x"25", + 7922 => x"29", + 7923 => x"20", + 7924 => x"57", + 7925 => x"42", + 7926 => x"20", + 7927 => x"0a", + 7928 => x"20", + 7929 => x"57", + 7930 => x"32", + 7931 => x"20", + 7932 => x"49", + 7933 => x"4c", + 7934 => x"20", + 7935 => x"50", + 7936 => x"00", + 7937 => x"20", + 7938 => x"53", + 7939 => x"00", + 7940 => x"41", + 7941 => x"65", + 7942 => x"73", + 7943 => x"20", + 7944 => x"43", + 7945 => x"52", + 7946 => x"74", + 7947 => x"63", + 7948 => x"20", + 7949 => x"72", + 7950 => x"20", + 7951 => x"30", + 7952 => x"00", + 7953 => x"20", + 7954 => x"43", + 7955 => x"4d", + 7956 => x"72", + 7957 => x"74", + 7958 => x"20", + 7959 => x"72", + 7960 => x"20", + 7961 => x"30", + 7962 => x"00", + 7963 => x"20", + 7964 => x"53", + 7965 => x"6b", + 7966 => x"61", + 7967 => x"41", + 7968 => x"65", + 7969 => x"20", + 7970 => x"20", + 7971 => x"30", + 7972 => x"00", + 7973 => x"4d", + 7974 => x"3a", + 7975 => x"20", + 7976 => x"5a", + 7977 => x"49", + 7978 => x"20", + 7979 => x"20", + 7980 => x"20", + 7981 => x"20", + 7982 => x"20", + 7983 => x"30", + 7984 => x"00", + 7985 => x"20", + 7986 => x"53", + 7987 => x"65", + 7988 => x"6c", + 7989 => x"20", + 7990 => x"71", + 7991 => x"20", + 7992 => x"20", + 7993 => x"64", + 7994 => x"34", + 7995 => x"7a", + 7996 => x"20", + 7997 => x"53", + 7998 => x"4d", + 7999 => x"6f", + 8000 => x"46", + 8001 => x"20", + 8002 => x"20", + 8003 => x"20", + 8004 => x"64", + 8005 => x"34", + 8006 => x"7a", + 8007 => x"20", + 8008 => x"57", + 8009 => x"62", + 8010 => x"20", + 8011 => x"41", + 8012 => x"6c", + 8013 => x"20", + 8014 => x"71", + 8015 => x"64", + 8016 => x"34", + 8017 => x"7a", + 8018 => x"53", + 8019 => x"6c", + 8020 => x"4d", + 8021 => x"75", + 8022 => x"46", + 8023 => x"00", + 8024 => x"45", + 8025 => x"45", + 8026 => x"69", + 8027 => x"55", + 8028 => x"6f", + 8029 => x"00", + 8030 => x"01", + 8031 => x"00", + 8032 => x"00", + 8033 => x"01", + 8034 => x"00", + 8035 => x"00", + 8036 => x"01", + 8037 => x"00", + 8038 => x"00", + 8039 => x"01", + 8040 => x"00", + 8041 => x"00", + 8042 => x"01", + 8043 => x"00", + 8044 => x"00", + 8045 => x"01", + 8046 => x"00", + 8047 => x"00", + 8048 => x"01", + 8049 => x"00", + 8050 => x"00", + 8051 => x"01", + 8052 => x"00", + 8053 => x"00", + 8054 => x"01", + 8055 => x"00", + 8056 => x"00", + 8057 => x"01", + 8058 => x"00", + 8059 => x"00", + 8060 => x"01", + 8061 => x"00", + 8062 => x"00", + 8063 => x"04", + 8064 => x"00", + 8065 => x"00", + 8066 => x"04", + 8067 => x"00", + 8068 => x"00", + 8069 => x"04", + 8070 => x"00", + 8071 => x"00", + 8072 => x"03", + 8073 => x"00", + 8074 => x"00", + 8075 => x"04", + 8076 => x"00", + 8077 => x"00", + 8078 => x"04", + 8079 => x"00", + 8080 => x"00", + 8081 => x"04", + 8082 => x"00", + 8083 => x"00", + 8084 => x"03", + 8085 => x"00", + 8086 => x"00", + 8087 => x"03", + 8088 => x"00", + 8089 => x"00", + 8090 => x"03", + 8091 => x"00", + 8092 => x"00", + 8093 => x"03", + 8094 => x"00", + 8095 => x"1b", + 8096 => x"1b", + 8097 => x"1b", + 8098 => x"1b", + 8099 => x"1b", + 8100 => x"1b", + 8101 => x"1b", + 8102 => x"1b", + 8103 => x"1b", + 8104 => x"1b", + 8105 => x"1b", + 8106 => x"10", + 8107 => x"0e", + 8108 => x"0d", + 8109 => x"0b", + 8110 => x"08", + 8111 => x"06", + 8112 => x"05", + 8113 => x"04", + 8114 => x"03", + 8115 => x"02", + 8116 => x"01", + 8117 => x"68", + 8118 => x"6f", + 8119 => x"68", + 8120 => x"00", + 8121 => x"21", + 8122 => x"25", + 8123 => x"20", + 8124 => x"0a", + 8125 => x"46", + 8126 => x"65", + 8127 => x"6f", + 8128 => x"73", + 8129 => x"74", + 8130 => x"68", + 8131 => x"6f", + 8132 => x"66", + 8133 => x"20", + 8134 => x"45", + 8135 => x"0a", + 8136 => x"43", + 8137 => x"6f", + 8138 => x"70", + 8139 => x"63", + 8140 => x"74", + 8141 => x"69", + 8142 => x"72", + 8143 => x"69", + 8144 => x"20", + 8145 => x"61", + 8146 => x"6e", + 8147 => x"00", + 8148 => x"53", + 8149 => x"22", + 8150 => x"3a", + 8151 => x"3e", + 8152 => x"7c", + 8153 => x"46", + 8154 => x"46", + 8155 => x"32", + 8156 => x"eb", + 8157 => x"53", + 8158 => x"35", + 8159 => x"4e", + 8160 => x"41", + 8161 => x"20", + 8162 => x"41", + 8163 => x"20", + 8164 => x"4e", + 8165 => x"41", + 8166 => x"20", + 8167 => x"41", + 8168 => x"20", + 8169 => x"00", + 8170 => x"00", + 8171 => x"00", + 8172 => x"00", + 8173 => x"80", + 8174 => x"8e", + 8175 => x"45", + 8176 => x"49", + 8177 => x"90", + 8178 => x"99", + 8179 => x"59", + 8180 => x"9c", + 8181 => x"41", + 8182 => x"a5", + 8183 => x"a8", + 8184 => x"ac", + 8185 => x"b0", + 8186 => x"b4", + 8187 => x"b8", + 8188 => x"bc", + 8189 => x"c0", + 8190 => x"c4", + 8191 => x"c8", + 8192 => x"cc", + 8193 => x"d0", + 8194 => x"d4", + 8195 => x"d8", + 8196 => x"dc", + 8197 => x"e0", + 8198 => x"e4", + 8199 => x"e8", + 8200 => x"ec", + 8201 => x"f0", + 8202 => x"f4", + 8203 => x"f8", + 8204 => x"fc", + 8205 => x"2b", + 8206 => x"3d", + 8207 => x"5c", + 8208 => x"3c", + 8209 => x"7f", + 8210 => x"00", + 8211 => x"00", + 8212 => x"01", + 8213 => x"00", + 8214 => x"00", + 8215 => x"00", + 8216 => x"00", + 8217 => x"00", + 8218 => x"00", + 8219 => x"00", + 8220 => x"01", + 8221 => x"00", + 8222 => x"00", + 8223 => x"00", + 8224 => x"01", + 8225 => x"00", + 8226 => x"00", + 8227 => x"00", + 8228 => x"01", + 8229 => x"00", + 8230 => x"00", + 8231 => x"00", + 8232 => x"01", + 8233 => x"00", + 8234 => x"00", + 8235 => x"00", + 8236 => x"01", + 8237 => x"00", + 8238 => x"00", + 8239 => x"00", + 8240 => x"01", + 8241 => x"00", + 8242 => x"00", + 8243 => x"00", + 8244 => x"01", + 8245 => x"00", + 8246 => x"00", + 8247 => x"00", + 8248 => x"01", + 8249 => x"00", + 8250 => x"00", + 8251 => x"00", + 8252 => x"01", + 8253 => x"00", + 8254 => x"00", + 8255 => x"00", + 8256 => x"01", + 8257 => x"00", + 8258 => x"00", + 8259 => x"00", + 8260 => x"01", + 8261 => x"00", + 8262 => x"00", + 8263 => x"00", + 8264 => x"01", + 8265 => x"00", + 8266 => x"00", + 8267 => x"00", + 8268 => x"01", + 8269 => x"00", + 8270 => x"00", + 8271 => x"00", + 8272 => x"01", + 8273 => x"00", + 8274 => x"00", + 8275 => x"00", + 8276 => x"01", + 8277 => x"00", + 8278 => x"00", + 8279 => x"00", + 8280 => x"01", + 8281 => x"00", + 8282 => x"00", + 8283 => x"00", + 8284 => x"01", + 8285 => x"00", + 8286 => x"00", + 8287 => x"00", + 8288 => x"01", + 8289 => x"00", + 8290 => x"00", + 8291 => x"00", + 8292 => x"01", + 8293 => x"00", + 8294 => x"00", + 8295 => x"00", + 8296 => x"01", + 8297 => x"00", + 8298 => x"00", + 8299 => x"00", + 8300 => x"01", + 8301 => x"00", + 8302 => x"00", + 8303 => x"00", + 8304 => x"01", + 8305 => x"00", + 8306 => x"00", + 8307 => x"00", + 8308 => x"01", + 8309 => x"00", + 8310 => x"00", + 8311 => x"00", + 8312 => x"01", + 8313 => x"00", + 8314 => x"00", + 8315 => x"00", + 8316 => x"01", + 8317 => x"00", + 8318 => x"00", + 8319 => x"00", + 8320 => x"01", + 8321 => x"00", + 8322 => x"00", + 8323 => x"00", + 8324 => x"00", + 8325 => x"00", + 8326 => x"00", + 8327 => x"00", + 8328 => x"00", + 8329 => x"00", + 8330 => x"00", + 8331 => x"00", + 8332 => x"01", + 8333 => x"01", + 8334 => x"00", + 8335 => x"00", + 8336 => x"00", + 8337 => x"00", + 8338 => x"05", + 8339 => x"05", + 8340 => x"05", + 8341 => x"00", + 8342 => x"01", + 8343 => x"01", + 8344 => x"01", + 8345 => x"01", + 8346 => x"00", + 8347 => x"00", + 8348 => x"00", + 8349 => x"00", + 8350 => x"00", + 8351 => x"00", + 8352 => x"00", + 8353 => x"00", + 8354 => x"00", + 8355 => x"00", + 8356 => x"00", + 8357 => x"00", + 8358 => x"00", + 8359 => x"00", + 8360 => x"00", + 8361 => x"00", + 8362 => x"00", + 8363 => x"00", + 8364 => x"00", + 8365 => x"00", + 8366 => x"00", + 8367 => x"00", + 8368 => x"00", + 8369 => x"00", + 8370 => x"00", + 8371 => x"01", + 8372 => x"00", + 8373 => x"01", + 8374 => x"00", + 8375 => x"02", + 8376 => x"00", + 8377 => x"00", + 8378 => x"01", + others => X"00" + ); + + signal RAM0_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM1_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM2_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM3_DATA : std_logic_vector(7 downto 0); -- Buffer for byte in word to be written. + signal RAM0_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM1_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM2_WREN : std_logic; -- Write Enable for this particular byte in word. + signal RAM3_WREN : std_logic; -- Write Enable for this particular byte in word. + +begin + + RAM0_DATA <= memAWrite(7 downto 0); + RAM1_DATA <= memAWrite(15 downto 8) when (memAWriteByte = '0' and memAWriteHalfWord = '0') or memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + RAM2_DATA <= memAWrite(23 downto 16) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(7 downto 0); + RAM3_DATA <= memAWrite(31 downto 24) when (memAWriteByte = '0' and memAWriteHalfWord = '0') + else + memAWrite(15 downto 8) when memAWriteHalfWord = '1' + else + memAWrite(7 downto 0); + + RAM0_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "11") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM1_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "10") or (memAWriteHalfWord = '1' and memAAddr(1) = '1')) + else '0'; + RAM2_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "01") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + RAM3_WREN <= '1' when memAWriteEnable = '1' and ((memAWriteByte = '0' and memAWriteHalfWord = '0') or (memAWriteByte = '1' and memAAddr(1 downto 0) = "00") or (memAWriteHalfWord = '1' and memAAddr(1) = '0')) + else '0'; + + -- RAM Byte 0 - Port A - bits 7 to 0 + process(clk) + begin + if rising_edge(clk) then + if RAM0_WREN = '1' then + RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM0_DATA; + else + memARead(7 downto 0) <= RAM0(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 1 - Port A - bits 15 to 8 + process(clk) + begin + if rising_edge(clk) then + if RAM1_WREN = '1' then + RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM1_DATA; + else + memARead(15 downto 8) <= RAM1(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 2 - Port A - bits 23 to 16 + process(clk) + begin + if rising_edge(clk) then + if RAM2_WREN = '1' then + RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM2_DATA; + else + memARead(23 downto 16) <= RAM2(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; + + -- RAM Byte 3 - Port A - bits 31 to 24 + process(clk) + begin + if rising_edge(clk) then + if RAM3_WREN = '1' then + RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))) := RAM3_DATA; + else + memARead(31 downto 24) <= RAM3(to_integer(unsigned(memAAddr(addrbits-1 downto 2)))); + end if; + end if; + end process; +end arch; diff --git a/zpu/devices/sysbus/RAM/dpram.vhd b/zpu/devices/sysbus/RAM/dpram.vhd new file mode 100644 index 0000000..339374e --- /dev/null +++ b/zpu/devices/sysbus/RAM/dpram.vhd @@ -0,0 +1,154 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: dpram.vhd +-- Created: January 2019 +-- Author(s): Altera/Intel Quartus II - refactored by Philip Smart for the ZPU Evo +-- Description: Dual Port RAM as provided by Altera in the Megafunctions suite. +-- +-- Credits: +-- Copyright: (c) Altera/Intel +-- +-- History: January 2019 - Initial module taken and refactored, customizing for the ZPU Evo. +-- +--------------------------------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dpram IS + GENERIC + ( + init_file : string := ""; + widthad_a : natural; + width_a : natural := 8; + widthad_b : natural; + width_b : natural := 8; +-- clock_en_a : string := "NORMAL"; +-- clock_en_b : string := "NORMAL"; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + clock_a : IN STD_LOGIC; + clocken_a : IN STD_LOGIC := '1'; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + clock_b : IN STD_LOGIC; + clocken_b : IN STD_LOGIC := '1'; + address_b : IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0); + wren_b : IN STD_LOGIC := '1'; + q_b : OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_b-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + read_during_write_mode_port_b : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + clock0 : IN STD_LOGIC ; + clocken0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC ; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + clock1 : IN STD_LOGIC ; + clocken1 : IN STD_LOGIC ; + address_b : IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0); + wren_b : IN STD_LOGIC ; + q_b : OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(width_a-1 DOWNTO 0); + q_b <= sub_wire1(width_b-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => init_file, + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + numwords_b => 2**widthad_b, + operation_mode => "BIDIR_DUAL_PORT", + --operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_b, + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => widthad_a, + widthad_b => widthad_b, + width_a => width_a, + width_b => width_b, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + clock0 => clock_a, + clocken0 => clocken_a, + address_a => address_a, + data_a => data_a, + wren_a => wren_a, + q_a => sub_wire0, + + clock1 => clock_b, + clocken1 => clocken_b, + address_b => address_b, + wren_b => wren_b, + data_b => data_b, + q_b => sub_wire1 + ); + +END SYN; diff --git a/zpu/devices/sysbus/SDMMC/SDCard.vhd b/zpu/devices/sysbus/SDMMC/SDCard.vhd new file mode 100644 index 0000000..6362bcb --- /dev/null +++ b/zpu/devices/sysbus/SDMMC/SDCard.vhd @@ -0,0 +1,567 @@ +--********************************************************************** +-- Copyright (c) 2012-2014 by XESS Corp . +-- All rights reserved. +-- +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 3.0 of the License, or (at your option) any later version. +-- +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library. If not, see +-- . +--********************************************************************** + +--********************************************************************* +-- SD MEMORY CARD INTERFACE +-- +-- Reads/writes a single or multiple blocks of data to/from an SD Flash card. +-- +-- Based on XESS by by Steven J. Merrifield, June 2008: +-- http : //stevenmerrifield.com/tools/sd.vhd +-- +-- Most of what I learned about interfacing to SD/SDHC cards came from here: +-- http://elm-chan.org/docs/mmc/mmc_e.html +-- +-- OPERATION +-- +-- Set-up: +-- First of all, you have to give the controller a clock signal on the clk_i +-- input with a higher frequency than the serial clock sent to the SD card +-- through the sclk_o output. You can set generic parameters for the +-- controller to tell it the master clock frequency (100 MHz), the SCLK +-- frequency for initialization (400 KHz), the SCLK frequency for normal +-- operation (25 MHz), the size of data sectors in the Flash memory (512 bytes), +-- and the type of card (either SD or SDHC). I typically use a 100 MHz +-- clock if I'm running an SD card with a 25 Mbps serial data stream. +-- +-- Initialize it: +-- Pulsing the reset_i input high and then bringing it low again will make +-- the controller initialize the SD card so it will XESS in SPI mode. +-- Basically, it sends the card the commands CMD0, CMD8 and then ACMD41 (which +-- is CMD55 followed by CMD41). The busy_o output will be high during the +-- initialization and will go low once it is done. +-- +-- After the initialization command sequence, the SD card will send back an R1 +-- response byte. If only the IDLE bit of the R1 response is set, then the +-- controller will repeatedly re-try the ACMD41 command while busy_o remains +-- high. +-- +-- If any other bit of the R1 response is set, then an error occurred. The +-- controller will stall, lower busy_o, and output the R1 response code on the +-- error_o bus. You'll have to pulse reset_i to unfreeze the controller. +-- +-- If the R1 response is all zeroes (i.e., no errors occurred during the +-- initialization), then the controller will lower busy_o and wait for a +-- read or write operation from the host. The controller will only accept new +-- operations when busy_o is low. +-- +-- Write data: +-- To write a data block to the SD card, the address of a block is placed +-- on the addr_i input bus and the wr_i input is raised. The address and +-- write strobe can be removed once busy_o goes high to indicate the write +-- operation is underway. The data to be written to the SD card is passed as +-- follows: +-- +-- 1. The controller requests a byte of data by raising the hndShk_o output. +-- 2. The host applies the next byte to the data_i input bus and raises the +-- hndShk_i input. +-- 3. The controller accepts the byte and lowers the hndShk_o output. +-- 4. The host lowers the hndShk_i input. +-- +-- This sequence of steps is repeated until all BLOCK_SIZE_G bytes of the +-- data block are passed from the host to the controller. Once all the data +-- is passed, the sector on the SD card will be written and the busy_o output +-- will be lowered. +-- +-- Read data: +-- To read a block of data from the SD card, the address of a block is +-- placed on the addr_i input bus and the rd_i input is raised. The address +-- and read strobe can be removed once busy_o goes high to indicate the read +-- operation is underway. The data read from the SD card is passed to the +-- host as follows: +-- +-- 1. The controller raises the hndShk_o output when the next data byte is available. +-- 2. The host reads the byte from the data_o output bus and raises the hndShk_i input. +-- 3. The controller lowers the hndShk_o output. +-- 4. The host lowers the hndShk_i input. +-- +-- This sequence of steps is repeated until all BLOCK_SIZE_G bytes of the +-- data block are passed from the controller to the host. Once all the data +-- is read, the busy_o output will be lowered. +-- +-- Handle errors: +-- If an error is detected during either a read or write operation, then the +-- controller will stall, lower busy_o, and output an error code on the +-- error_o bus. You'll have to pulse reset_i to unfreeze the controller. That +-- may seem a bit excessive, but it does guarantee that you can't ignore any +-- errors that occur. +-- +-- TODO: +-- +-- * Implement multi-block read and write commands. +-- * Allow host to send/receive SPI commands/data directly to +-- the SD card through the controller. +-- ********************************************************************* + +library IEEE; +library pkgs; +use IEEE.math_real.all; +use IEEE.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use IEEE.numeric_std.all; +use work.zpu_soc_pkg.all; +use work.zpu_pkg.all; + +entity SDCard is + generic ( + FREQ_G : real := 100.0; -- Master clock frequency (MHz). + INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz). + SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz). + BLOCK_SIZE_G : natural := 512 -- Number of bytes in an SD card block or sector. + ); + port ( + -- Host-side interface signals. + clk_i : in std_logic; -- Master clock. + reset_i : in std_logic := NO; -- active-high, synchronous reset. + cardtype : in std_logic := '0'; -- 0 = SD, 1 = SDHC + rd_i : in std_logic := NO; -- active-high read block request. + wr_i : in std_logic := NO; -- active-high write block request. + continue_i : in std_logic := NO; -- If true, inc address and continue R/W. + addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address. + data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block. + data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block. + busy_o : out std_logic; -- High when controller is busy performing some operation. + hndShk_i : in std_logic; -- High when host has data to give or has taken data. + hndShk_o : out std_logic; -- High when controller has taken data or has data to give. + error_o : out std_logic_vector(15 downto 0) := (others => NO); + -- I/O signals to the external SD card. + cs_bo : out std_logic := HI; -- Active-low chip-select. + sclk_o : out std_logic := LO; -- Serial clock to SD card. + mosi_o : out std_logic := HI; -- Serial data output to SD card. + miso_i : in std_logic := ZERO -- Serial data input from SD card. + ); +end entity; + + + +architecture arch of SDCard is + + signal sclk_r : std_logic := ZERO; -- Register output drives SD card clock. + signal hndShk_r : std_logic := NO; -- Register output drives handshake output to host. + +begin + + process(clk_i) -- FSM process for the SD card controller. + + type FsmState_t is ( -- States of the SD card controller FSM. + START_INIT, -- Send initialization clock pulses to the deselected SD card. + SEND_CMD0, -- Put the SD card in the IDLE state. + CHK_CMD0_RESPONSE, -- Check card's R1 response to the CMD0. + SEND_CMD8, -- This command is needed to initialize SDHC cards. + GET_CMD8_RESPONSE, -- Get the R7 response to CMD8. + SEND_CMD55, -- Send CMD55 to the SD card. + SEND_CMD41, -- Send CMD41 to the SD card. + CHK_ACMD41_RESPONSE, -- Check if the SD card has left the IDLE state. + WAIT_FOR_HOST_RW, -- Wait for the host to issue a read or write command. + RD_BLK, -- Read a block of data from the SD card. + WR_BLK, -- Write a block of data to the SD card. + WR_WAIT, -- Wait for SD card to finish writing the data block. + START_TX, -- Start sending command/data. + TX_BITS, -- Shift out remaining command/data bits. + GET_CMD_RESPONSE, -- Get the R1 response of the SD card to a command. + RX_BITS, -- Receive response/data from the SD card. + DESELECT, -- De-select the SD card and send some clock pulses (Must enter with sclk at zero.) + PULSE_SCLK, -- Issue some clock pulses. (Must enter with sclk at zero.) + REPORT_ERROR -- Report error and stall until reset. + ); + variable state_v : FsmState_t := START_INIT; -- Current state of the FSM. + variable rtnState_v : FsmState_t; -- State FSM returns to when FSM subroutine completes. + + -- Timing constants based on the master clock frequency and the SPI SCLK frequencies. + constant CLKS_PER_INIT_SCLK_C : real := FREQ_G / INIT_SPI_FREQ_G; + constant CLKS_PER_SCLK_C : real := FREQ_G / SPI_FREQ_G; + constant MAX_CLKS_PER_SCLK_C : real := realmax(CLKS_PER_INIT_SCLK_C, CLKS_PER_SCLK_C); + constant MAX_CLKS_PER_SCLK_PHASE_C : natural := integer(round(MAX_CLKS_PER_SCLK_C / 2.0)); + constant INIT_SCLK_PHASE_PERIOD_C : natural := integer(round(CLKS_PER_INIT_SCLK_C / 2.0)); + constant SCLK_PHASE_PERIOD_C : natural := integer(round(CLKS_PER_SCLK_C / 2.0)); + constant DELAY_BETWEEN_BLOCK_RW_C : natural := SCLK_PHASE_PERIOD_C; + + -- Registers for generating slow SPI SCLK from the faster master clock. + variable clkDivider_v : natural range 0 to MAX_CLKS_PER_SCLK_PHASE_C; -- Holds the SCLK period. + variable sclkPhaseTimer_v : natural range 0 to MAX_CLKS_PER_SCLK_PHASE_C; -- Counts down to zero, then SCLK toggles. + + constant NUM_INIT_CLKS_C : natural := 160; -- Number of initialization clocks to SD card. + variable bitCnt_v : natural range 0 to NUM_INIT_CLKS_C; -- Tx/Rx bit counter. + + constant CRC_SZ_C : natural := 2; -- Number of CRC bytes for read/write blocks. + -- When reading blocks of data, get 0xFE + [DATA_BLOCK] + [CRC]. + constant RD_BLK_SZ_C : natural := 1 + BLOCK_SIZE_G + CRC_SZ_C; + -- When writing blocks of data, send 0xFF + 0xFE + [DATA BLOCK] + [CRC] then receive response byte. + constant WR_BLK_SZ_C : natural := 1 + 1 + BLOCK_SIZE_G + CRC_SZ_C + 1; + variable byteCnt_v : natural range 0 to IntMax(WR_BLK_SZ_C, RD_BLK_SZ_C); -- Tx/Rx byte counter. + + -- Command bytes for various SD card operations. + subtype Cmd_t is std_logic_vector(7 downto 0); + constant CMD0_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 0, Cmd_t'length)); + constant CMD8_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 8, Cmd_t'length)); + constant CMD55_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 55, Cmd_t'length)); + constant CMD41_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 41, Cmd_t'length)); + constant READ_BLK_CMD_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 17, Cmd_t'length)); + constant WRITE_BLK_CMD_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 24, Cmd_t'length)); + + -- Except for CMD0 and CMD8, SD card ops don't need a CRC, so use a fake one for that slot in the command. + constant FAKE_CRC_C : std_logic_vector(7 downto 0) := x"FF"; + + variable addr_v : unsigned(addr_i'range); -- Address of current block for R/W operations. + + -- Maximum Tx to SD card consists of command + address + CRC. Data Tx is just a single byte. + variable tx_v : std_logic_vector(CMD0_C'length + addr_v'length + FAKE_CRC_C'length - 1 downto 0); -- Data/command to SD card. + alias txCmd_v is tx_v; -- Command transmission shift register. + alias txData_v is tx_v(tx_v'high downto tx_v'high - data_i'length + 1); -- Data byte transmission shift register. + + variable rx_v : std_logic_vector(data_i'range); -- Data/response byte received from SD card. + -- Various response codes. + subtype Response_t is std_logic_vector(rx_v'range); + constant ACTIVE_NO_ERRORS_C : Response_t := "00000000"; -- Normal R1 code after initialization. + constant IDLE_NO_ERRORS_C : Response_t := "00000001"; -- Normal R1 code after CMD0. + constant DATA_ACCEPTED_C : Response_t := "---00101"; -- SD card accepts data block from host. + constant DATA_REJ_CRC_C : Response_t := "---01011"; -- SD card rejects data block from host due to CRC error. + constant DATA_REJ_WERR_C : Response_t := "---01101"; -- SD card rejects data block from host due to write error. + -- Various tokens. + subtype Token_t is std_logic_vector(rx_v'range); + constant NO_TOKEN_C : Token_t := x"FF"; -- Received before the SD card responds to a block read command. + constant START_TOKEN_C : Token_t := x"FE"; -- Starting byte preceding a data block. + + -- Flags that are set/cleared to affect the operation of the FSM. + variable getCmdResponse_v : boolean; -- When true, get R1 response to command sent to SD card. + variable rtnData_v : boolean; -- When true, signal to host when a data byte arrives from SD card. + variable doDeselect_v : boolean; -- When true, de-select SD card after a command is issued. + + begin + if rising_edge(clk_i) then + + if reset_i = YES then -- Perform a reset. + state_v := START_INIT; -- Send the FSM to the initialization entry-point. + sclkPhaseTimer_v := 0; -- Don't delay the initialization right after reset. + busy_o <= YES; -- Busy while the SD card interface is being initialized. + + elsif sclkPhaseTimer_v /= 0 then + -- Setting the clock phase timer to a non-zero value delays any further actions + -- and generates the slower SPI clock from the faster master clock. + sclkPhaseTimer_v := sclkPhaseTimer_v - 1; + + -- Clock phase timer has reached zero, so check handshaking sync. between host and controller. + + -- Handshaking lets the host control the flow of data to/from the SD card controller. + -- Handshaking between the SD card controller and the host proceeds as follows: + -- 1: Controller raises its handshake and waits. + -- 2: Host sees controller handshake and raises its handshake in acknowledgement. + -- 3: Controller sees host handshake acknowledgement and lowers its handshake. + -- 4: Host sees controller lower its handshake and removes its handshake. + -- + -- Handshaking is bypassed when the controller FSM is initializing the SD card. + + elsif state_v /= START_INIT and hndShk_r = HI and hndShk_i = LO then + null; -- Waiting for the host to acknowledge handshake. + elsif state_v /= START_INIT and hndShk_r = HI and hndShk_i = HI then + txData_v := data_i; -- Get any data passed from the host. + hndShk_r <= LO; -- The host acknowledged, so lower the controller handshake. + elsif state_v /= START_INIT and hndShk_r = LO and hndShk_i = HI then + null; -- Waiting for the host to lower its handshake. + elsif (state_v = START_INIT) or (hndShk_r = LO and hndShk_i = LO) then + -- Both handshakes are low, so the controller operations can proceed. + + busy_o <= YES; -- Busy by default. Only false when waiting for R/W from host or stalled by error. + + case state_v is + + when START_INIT => -- Deselect the SD card and send it a bunch of clock pulses with MOSI high. + error_o <= (others => ZERO); -- Clear error flags. + clkDivider_v := INIT_SCLK_PHASE_PERIOD_C - 1; -- Use slow SPI clock freq during init. + sclkPhaseTimer_v := INIT_SCLK_PHASE_PERIOD_C - 1; -- and set the duration of the next clock phase. + sclk_r <= LO; -- Start with low clock to the SD card. + hndShk_r <= LO; -- Initialize handshake signal. + addr_v := (others => ZERO); -- Initialize address. + rtnData_v := false; -- No data is returned to host during initialization. + bitCnt_v := NUM_INIT_CLKS_C; -- Generate this many clock pulses. + state_v := DESELECT; -- De-select the SD card and pulse SCLK. + rtnState_v := SEND_CMD0; -- Then go to this state after the clock pulses are done. + + when SEND_CMD0 => -- Put the SD card in the IDLE state. + cs_bo <= LO; -- Enable the SD card. + txCmd_v := CMD0_C & x"00000000" & x"95"; -- 0x95 is the correct CRC for this command. + bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command. + getCmdResponse_v := true; -- Sending a command that generates a response. + doDeselect_v := true; -- De-select SD card after this command finishes. + state_v := START_TX; -- Go to FSM subroutine to send the command. + rtnState_v := CHK_CMD0_RESPONSE; -- Then check the response to the command. + + when CHK_CMD0_RESPONSE => -- Check card's R1 response to the CMD0. + if rx_v = IDLE_NO_ERRORS_C then + state_v := SEND_CMD8; -- Continue init if SD card is in IDLE state with no errors + else + state_v := SEND_CMD0; -- Otherwise, try CMD0 again. + end if; + + when SEND_CMD8 => -- This command is needed to initialize SDHC cards. + cs_bo <= LO; -- Enable the SD card. + txCmd_v := CMD8_C & x"000001aa" & x"87"; -- 0x87 is the correct CRC for this command. + bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command. + getCmdResponse_v := true; -- Sending a command that generates a response. + doDeselect_v := false; -- Don't de-select, need to get the R7 response sent from the SD card. + state_v := START_TX; -- Go to FSM subroutine to send the command. + rtnState_v := GET_CMD8_RESPONSE; -- Then go to this state after the command is sent. + + when GET_CMD8_RESPONSE => -- Get the R7 response to CMD8. + cs_bo <= LO; -- The SD card should already be enabled, but let's be explicit. + bitCnt_v := 31; -- Four bytes (32 bits) in R7 response. + getCmdResponse_v := false; -- Not sending a command that generates a response. + doDeselect_v := true; -- De-select card to end the command after getting the four bytes. + state_v := RX_BITS; -- Go to FSM subroutine to get the R7 response. + rtnState_v := SEND_CMD55; -- Then go here (we don't care what the actual R7 response is). + + when SEND_CMD55 => -- Send CMD55 as preamble of ACMD41 initialization command. + cs_bo <= LO; -- Enable the SD card. + txCmd_v := CMD55_C & x"00000000" & FAKE_CRC_C; + bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command. + getCmdResponse_v := true; -- Sending a command that generates a response. + doDeselect_v := true; -- De-select SD card after this command finishes. + state_v := START_TX; -- Go to FSM subroutine to send the command. + rtnState_v := SEND_CMD41; -- Then go to this state after the command is sent. + + when SEND_CMD41 => -- Send the SD card the initialization command. + cs_bo <= LO; -- Enable the SD card. + txCmd_v := CMD41_C & x"40000000" & FAKE_CRC_C; + bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command. + getCmdResponse_v := true; -- Sending a command that generates a response. + doDeselect_v := true; -- De-select SD card after this command finishes. + state_v := START_TX; -- Go to FSM subroutine to send the command. + rtnState_v := CHK_ACMD41_RESPONSE; -- Then check the response to the command. + + when CHK_ACMD41_RESPONSE => + -- The CMD55, CMD41 sequence should cause the SD card to leave the IDLE state + -- and become ready for SPI read/write operations. If still IDLE, then repeat the CMD55, CMD41 sequence. + -- If one of the R1 error flags is set, then report the error and stall. + if rx_v = ACTIVE_NO_ERRORS_C then -- Not IDLE, no errors. + state_v := WAIT_FOR_HOST_RW; -- Start processing R/W commands from the host. + elsif rx_v = IDLE_NO_ERRORS_C then -- Still IDLE but no errors. + state_v := SEND_CMD55; -- Repeat the CMD55, CMD41 sequence. + else -- Some error occurred. + state_v := REPORT_ERROR; -- Report the error and stall. + end if; + + when WAIT_FOR_HOST_RW => -- Wait for the host to read or write a block of data from the SD card. + clkDivider_v := SCLK_PHASE_PERIOD_C - 1; -- Set SPI clock frequency for normal operation. + getCmdResponse_v := true; -- Get R1 response to any commands issued to the SD card. + if rd_i = YES then -- send READ command and address to the SD card. + cs_bo <= LO; -- Enable the SD card. + if continue_i = YES then -- Multi-block read. Use stored address. + if cardtype = '0' then -- SD cards use byte-addressing, + addr_v := addr_v + BLOCK_SIZE_G; -- so add block-size to get next block address. + else -- SDHC cards use block-addressing, + addr_v := addr_v + 1; -- so just increment current block address. + end if; + txCmd_v := READ_BLK_CMD_C & std_logic_vector(addr_v) & FAKE_CRC_C; + else -- Single-block read. + txCmd_v := READ_BLK_CMD_C & addr_i & FAKE_CRC_C; -- Use address supplied by host. + addr_v := unsigned(addr_i); -- Store address for multi-block operations. + end if; + bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command. + byteCnt_v := RD_BLK_SZ_C; + state_v := START_TX; -- Go to FSM subroutine to send the command. + rtnState_v := RD_BLK; -- Then go to this state to read the data block. + elsif wr_i = YES then -- send WRITE command and address to the SD card. + cs_bo <= LO; -- Enable the SD card. + if continue_i = YES then -- Multi-block write. Use stored address. + if cardtype = '0' then -- SD cards use byte-addressing, + addr_v := addr_v + BLOCK_SIZE_G; -- so add block-size to get next block address. + else -- SDHC cards use block-addressing, + addr_v := addr_v + 1; -- so just increment current block address. + end if; + txCmd_v := WRITE_BLK_CMD_C & std_logic_vector(addr_v) & FAKE_CRC_C; + else -- Single-block write. + txCmd_v := WRITE_BLK_CMD_C & addr_i & FAKE_CRC_C; -- Use address supplied by host. + addr_v := unsigned(addr_i); -- Store address for multi-block operations. + end if; + bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command. + byteCnt_v := WR_BLK_SZ_C; -- Set number of bytes to write. + state_v := START_TX; -- Go to this FSM subroutine to send the command ... + rtnState_v := WR_BLK; -- then go to this state to write the data block. + else -- Do nothing and wait for command from host. + cs_bo <= HI; -- Deselect the SD card. + busy_o <= NO; -- SD card interface is waiting for R/W from host, so it's not busy. + state_v := WAIT_FOR_HOST_RW; -- Keep waiting for command from host. + end if; + + when RD_BLK => -- Read a block of data from the SD card. + -- Some default values for these... + rtnData_v := false; -- Data is only returned to host in one place. + bitCnt_v := rx_v'length - 1; -- Receiving byte-sized data. + state_v := RX_BITS; -- Call the bit receiver routine. + rtnState_v := RD_BLK; -- Return here when done receiving a byte. + if byteCnt_v = RD_BLK_SZ_C then -- Initial read to prime the pump. + byteCnt_v := byteCnt_v - 1; + elsif byteCnt_v = RD_BLK_SZ_C -1 then -- Then look for the data block start token. + if rx_v = NO_TOKEN_C then -- Receiving 0xFF means the card hasn't responded yet. Keep trying. + null; + elsif rx_v = START_TOKEN_C then + rtnData_v := true; -- Found the start token, so now start returning data byes to the host. + byteCnt_v := byteCnt_v - 1; + else -- Getting anything else means something strange has happened. + state_v := REPORT_ERROR; + end if; + elsif byteCnt_v >= 3 then -- Now bytes of data from the SD card are received. + rtnData_v := true; -- Return this data to the host. + byteCnt_v := byteCnt_v - 1; + elsif byteCnt_v = 2 then -- Receive the 1st CRC byte at the end of the data block. + byteCnt_v := byteCnt_v - 1; + elsif byteCnt_v = 1 then -- Receive the 2nd + byteCnt_v := byteCnt_v - 1; + else -- Reading is done, so deselect the SD card. + sclk_r <= LO; + bitCnt_v := 2; + state_v := DESELECT; + rtnState_v := WAIT_FOR_HOST_RW; + end if; + + when WR_BLK => -- Write a block of data to the SD card. + -- Some default values for these... + getCmdResponse_v := false; -- Sending data bytes so there's no command response from SD card. + bitCnt_v := txData_v'length; -- Transmitting byte-sized data. + state_v := START_TX; -- Call the bit transmitter routine. + rtnState_v := WR_BLK; -- Return here when done transmitting a byte. + if byteCnt_v = WR_BLK_SZ_C then + txData_v := NO_TOKEN_C; -- Hold MOSI high for one byte before data block goes out. + elsif byteCnt_v = WR_BLK_SZ_C - 1 then -- Send start token. + txData_v := START_TOKEN_C; -- Starting token for data block. + elsif byteCnt_v >= 4 then -- Now send bytes in the data block. + hndShk_r <= HI; -- Signal host to provide data. + -- The transmit shift register is loaded with data from host in the handshaking section above. + elsif byteCnt_v = 3 or byteCnt_v = 2 then -- Send two phony CRC bytes at end of packet. + txData_v := FAKE_CRC_C; + elsif byteCnt_v = 1 then + bitCnt_v := rx_v'length - 1; + state_v := RX_BITS; -- Get response of SD card to the write operation. + rtnState_v := WR_WAIT; + else -- Check received response byte. + if std_match(rx_v, DATA_ACCEPTED_C) then -- Data block was accepted. + state_v := WR_WAIT; -- Wait for the SD card to finish writing the data into Flash. + else -- Data block was rejected. + error_o(15 downto 8) <= rx_v; + state_v := REPORT_ERROR; -- Report the error. + end if; + end if; + byteCnt_v := byteCnt_v - 1; + + when WR_WAIT => -- Wait for SD card to finish writing the data block. + -- The SD card will pull MISO low while it is busy, and raise it when it is done. + sclk_r <= not sclk_r; -- Toggle the SPI clock... + sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase. + if sclk_r = HI and miso_i = HI then -- Data block has been written, so deselect the SD card. + bitCnt_v := 2; + state_v := DESELECT; + rtnState_v := WAIT_FOR_HOST_RW; + end if; + + when START_TX => + -- Start sending command/data by lowering SCLK and outputing MSB of command/data + -- so it has plenty of setup before the rising edge of SCLK. + sclk_r <= LO; -- Lower the SCLK (although it should already be low). + sclkPhaseTimer_v := clkDivider_v; -- Set the duration of the low SCLK. + mosi_o <= tx_v(tx_v'high); -- Output MSB of command/data. + tx_v := tx_v(tx_v'high-1 downto 0) & ONE; -- Shift command/data register by one bit. + bitCnt_v := bitCnt_v - 1; -- The first bit has been sent, so decrement bit counter. + state_v := TX_BITS; -- Go here to shift out the rest of the command/data bits. + + when TX_BITS => -- Shift out remaining command/data bits and (possibly) get response from SD card. + sclk_r <= not sclk_r; -- Toggle the SPI clock... + sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase. + if sclk_r = HI then + -- SCLK is going to be flipped from high to low, so output the next command/data bit + -- so it can setup while SCLK is low. + if bitCnt_v /= 0 then -- Keep sending bits until the bit counter hits zero. + mosi_o <= tx_v(tx_v'high); + tx_v := tx_v(tx_v'high-1 downto 0) & ONE; + bitCnt_v := bitCnt_v - 1; + else + if getCmdResponse_v then + state_v := GET_CMD_RESPONSE; -- Get a response to the command from the SD card. + bitCnt_v := Response_t'length - 1; -- Length of the expected response. + else + state_v := rtnState_v; -- Return to calling state (no need to get a response). + sclkPhaseTimer_v := 0; -- Clear timer so next SPI op can begin ASAP with SCLK low. + end if; + end if; + end if; + + when GET_CMD_RESPONSE => -- Get the response of the SD card to a command. + if sclk_r = HI and miso_i = LO then -- MISO will be held high by SD card until 1st bit of R1 response, which is 0. + -- Shift in the MSB bit of the response. + rx_v := rx_v(rx_v'high-1 downto 0) & miso_i; + bitCnt_v := bitCnt_v - 1; + state_v := RX_BITS; -- Now receive the reset of the response. + end if; + sclk_r <= not sclk_r; -- Toggle the SPI clock... + sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase. + + when RX_BITS => -- Receive bits from the SD card. + if sclk_r = HI then -- Bits enter after the rising edge of SCLK. + rx_v := rx_v(rx_v'high-1 downto 0) & miso_i; + if bitCnt_v /= 0 then -- More bits left to receive. + bitCnt_v := bitCnt_v - 1; + else -- Last bit has been received. + if rtnData_v then -- Send the received data to the host. + data_o <= rx_v; -- Output received data to the host. + hndShk_r <= HI; -- Signal to the host that the data is ready. + end if; + if doDeselect_v then + bitCnt_v := 1; + state_v := DESELECT; -- De-select SD card before returning. + else + state_v := rtnState_v; -- Otherwise, return to calling state without de-selecting. + end if; + end if; + end if; + sclk_r <= not sclk_r; -- Toggle the SPI clock... + sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase. + + when DESELECT => -- De-select the SD card and send some clock pulses (Must enter with sclk at zero.) + doDeselect_v := false; -- Once the de-select is done, clear the flag that caused it. + cs_bo <= HI; -- De-select the SD card. + mosi_o <= HI; -- Keep the data input of the SD card pulled high. + state_v := PULSE_SCLK; -- Pulse the clock so the SD card will see the de-select. + sclk_r <= LO; -- Clock is set low so the next rising edge will see the new CS and MOSI + sclkPhaseTimer_v := clkDivider_v; -- Set the duration of the next clock phase. + + when PULSE_SCLK => -- Issue some clock pulses. (Must enter with sclk at zero.) + if sclk_r = HI then + if bitCnt_v /= 0 then + bitCnt_v := bitCnt_v - 1; + else -- Return to the calling routine when the pulse counter reaches zero. + state_v := rtnState_v; + end if; + end if; + sclk_r <= not sclk_r; -- Toggle the SPI clock... + sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase. + + when REPORT_ERROR => -- Report the error code and stall here until a reset occurs. + error_o(rx_v'range) <= rx_v; -- Output the SD card response as the error code. + busy_o <= NO; -- Not busy. + + when others => + state_v := START_INIT; + end case; + end if; + end if; + end process; + + sclk_o <= sclk_r; -- Output the generated SPI clock for the SD card. + hndShk_o <= hndShk_r; -- Output the generated handshake to the host. + +end architecture; diff --git a/zpu/devices/sysbus/SDRAM.bak/oddrff.vhd b/zpu/devices/sysbus/SDRAM.bak/oddrff.vhd new file mode 100644 index 0000000..19b832e --- /dev/null +++ b/zpu/devices/sysbus/SDRAM.bak/oddrff.vhd @@ -0,0 +1,50 @@ +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_soc_pkg.all; +use work.zpu_pkg.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity oddrff is + port ( + CLK: in std_ulogic; + D0: in std_logic; + D1: in std_logic; + O: out std_ulogic + ); + +end entity oddrff; + +architecture behave of oddrff is + signal D0_v, D1_v, O_v: std_logic_vector(0 downto 0); + + +begin + + ALTDDIO_OUT_component : ALTDDIO_OUT + GENERIC MAP ( + extend_oe_disable => "OFF", + intended_device_family => "Cyclone IV E", + invert_output => "OFF", + lpm_hint => "UNUSED", + lpm_type => "altddio_out", + oe_reg => "UNREGISTERED", + power_up_high => "OFF", + width => 1 + ) + PORT MAP ( + datain_h => D1_v, + datain_l => D0_v, + outclock => CLK, + dataout => O_v + ); + + D1_v(0) <= D0; + D0_v(0) <= D1; + O <= O_v(0); + +end behave; diff --git a/zpu/devices/sysbus/SDRAM.bak/sdram.qip b/zpu/devices/sysbus/SDRAM.bak/sdram.qip new file mode 100644 index 0000000..a0e34f0 --- /dev/null +++ b/zpu/devices/sysbus/SDRAM.bak/sdram.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sdram.vhd ] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sdram.sdc ] diff --git a/zpu/devices/sysbus/SDRAM.bak/sdram.sdc b/zpu/devices/sysbus/SDRAM.bak/sdram.sdc new file mode 100644 index 0000000..eb2dd4e --- /dev/null +++ b/zpu/devices/sysbus/SDRAM.bak/sdram.sdc @@ -0,0 +1,26 @@ +derive_pll_clocks + +#create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] +#{*mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] \ + +#create_generated_clock -source [get_pins -compatibility_mode {mypll|altpll_component|pll|clk[1]}] \ +# -name MEMCLK [get_ports {MEMCLK}] +#create_generated_clock -source [get_pins -compatibility_mode {mypll|altpll_component|pll|clk[1]}] -multiply_by 1 \ +# -name MEMCLK [get_ports {MEMCLK}] +#create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 25 -divide_by 2 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk1}] +#create_generated_clock -name {MEMCLK} -source [get_pins -compatibility_mode {mypll|altpll_component|pll|clk[1]}] -master_clock {MEMCLK} [get_ports {MEMCLK}] + +derive_clock_uncertainty + +# Set acceptable delays for SDRAM chip (See correspondent chip datasheet) +set_input_delay -max -clock MEMCLK 6.4ns [get_ports SDRAM_DQ[*]] +set_input_delay -min -clock MEMCLK 3.7ns [get_ports SDRAM_DQ[*]] + +# -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] +#set_multicycle_path -from [get_clocks {MEMCLK}] \ +# -to [get_clocks {SYSCLK}] \ +# -setup 2 + + +set_output_delay -max -clock MEMCLK 1.6ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}] +set_output_delay -min -clock MEMCLK -0.9ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}] diff --git a/zpu/devices/sysbus/SDRAM.bak/sdram.sdc.hold b/zpu/devices/sysbus/SDRAM.bak/sdram.sdc.hold new file mode 100644 index 0000000..74d40c3 --- /dev/null +++ b/zpu/devices/sysbus/SDRAM.bak/sdram.sdc.hold @@ -0,0 +1,19 @@ +derive_pll_clocks + +#create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_generated_clock -source [get_pins -compatibility_mode {*mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] \ + -name SDRAM_CLK [get_ports {SDRAM_CLK}] + +derive_clock_uncertainty + +# Set acceptable delays for SDRAM chip (See correspondent chip datasheet) +set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]] +set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]] + +# -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] +#set_multicycle_path -from [get_clocks {SDRAM_CLK}] \ +# -to [get_clocks {*mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] \ +# -setup 2 + +set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}] +set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}] diff --git a/zpu/devices/sysbus/SDRAM.bak/sdram.vhd b/zpu/devices/sysbus/SDRAM.bak/sdram.vhd new file mode 100644 index 0000000..b4c8690 --- /dev/null +++ b/zpu/devices/sysbus/SDRAM.bak/sdram.vhd @@ -0,0 +1,488 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: sdram.vhd +-- Created: September 2019 +-- Original Author: Stephen J. Leary 2013-2014 +-- VHDL Author: Philip Smart +-- Description: Original Wishbone module written by Stephen J. Leary 2013-2014 in Verilog for use +-- with the MT48LC16M16 chip. +-- It has been translated into VHDL and adapted for the system bus and undergoing +-- extensive modifications to work with the ZPU EVO processor, specifically burst +-- tuning to enhance L2 Cache Fill performance. +-- Credits: +-- Copyright: Copyright (c) 2013-2014, Stephen J. Leary, All rights reserved. +-- VHDL translation, sysbus adaptation and enhancements (c) 2019 Philip Smart +-- +-- +-- History: September 2019 - Initial module translation to VHDL based on Stephen J. Leary's Verilog +-- source code. +-- November 2019 - Adapted for the system bus for use when no Wishbone interface is +-- instantiated in the ZPU Evo. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_soc_pkg.all; +use work.zpu_pkg.all; + +entity SDRAM is + generic ( + MAX_DATACACHE_BITS : integer := 4; -- Maximum size in addr bits of 32bit datacache for burst transactions. + SDRAM_COLUMNS : integer := 256; -- Number of Columns in an SDRAM page (ie. 1 row). + SDRAM_ROWS : integer := 4096; -- Number of Rows in the SDRAM. + SDRAM_BANKS : integer := 4 -- Number of banks in the SDRAM. + ); + port ( + -- SDRAM Interface + SDRAM_CLK : in std_logic; -- sdram is accessed at 100MHz + SDRAM_RST : in std_logic; -- reset the sdram controller. + SDRAM_CKE : out std_logic; -- clock enable. + SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus + SDRAM_ADDR : out std_logic_vector(log2ceil(SDRAM_ROWS) - 1 downto 0); -- Multiplexed address bus + SDRAM_DQM : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of byte masks dependent on number of banks. + SDRAM_BA : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of banks in SDRAM + SDRAM_CS_n : out std_logic; -- Single chip select + SDRAM_WE_n : out std_logic; -- write enable + SDRAM_RAS_n : out std_logic; -- row address select + SDRAM_CAS_n : out std_logic; -- columns address select + SDRAM_READY : out std_logic; -- sd ready. + + -- CPU Interface + CLK : in std_logic; -- System master clock + RESET : in std_logic; -- high active sync reset + ADDR : in std_logic_vector(21 downto 0); + DATA_IN : in std_logic_vector(31 downto 0); -- write data + DATA_OUT : out std_logic_vector(31 downto 0); -- read data + WRITE_BYTE : in std_logic; -- write a single byte as specified in A1:A0 + WRITE_HWORD : in std_logic; -- write a 16bit word as specified in A1 + CS : in std_logic; -- Chip Select. + WREN : in std_logic; -- Write enable. + RDEN : in std_logic; -- Read enable. + BUSY : out std_logic -- Memory is busy, hold CPU. + ); +end SDRAM; + +architecture Structure of SDRAM is + + -- Constants to define the structure of the SDRAM in bits for provisioning of signals. + constant SDRAM_ROW_BITS : integer := log2ceil(SDRAM_ROWS); + constant SDRAM_COLUMN_BITS: integer := log2ceil(SDRAM_COLUMNS); + constant SDRAM_ARRAY_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS); + constant SDRAM_BANK_BITS : integer := log2ceil(SDRAM_BANKS); + constant SDRAM_ADDR_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS); + + -- Constants for correct operation of the SDRAM, these values are taken from the datasheet of the target device. + -- + constant tRCD : integer := 4; -- tRCD - RAS to CAS minimum period, ie. 20ns -> 2 cycles@100MHz + constant tRP : integer := 4; -- tRP - Precharge delay, min time for a precharge command to complete, ie. 15ns -> 2 cycles@100MHz + constant tRFC : integer := 70; -- tRFC - Auto-refresh minimum time to complete, ie. 66ns + constant tREF : integer := 64; -- tREF - period of time a complete refresh of all rows is made within. + constant RAM_CLK : integer := 50000000; -- SDRAM Clock in Hertz + + -- Command table for a standard SDRAM. + -- + -- Name (Function) CS# RAS# CAS# WE# DQM ADDR DQ + -- COMMAND INHIBIT (NOP) H X X X X X X + -- NO OPERATION (NOP) L H H H X X X + -- ACTIVE (select bank and activate row) L L H H X Bank/row X + -- READ (select bank and column, and start READ burst) L H L H L/H Bank/col X + -- WRITE (select bank and column, and start WRITE burst) L H L L L/H Bank/col Valid + -- BURST TERMINATE L H H L X X Active + -- PRECHARGE (Deactivate row in bank or banks) L L H L X Code X + -- AUTO REFRESH or SELF REFRESH (enter self refresh mode) L L L H X X X + -- LOAD MODE REGISTER L L L L X Op-code X + -- Write enable/output enable X X X X L X Active + -- Write inhibit/output High-Z X X X X H X High-Z + constant CMD_INHIBIT : std_logic_vector(3 downto 0) := "1111"; + constant CMD_NOP : std_logic_vector(3 downto 0) := "0111"; + constant CMD_ACTIVE : std_logic_vector(3 downto 0) := "0011"; + constant CMD_READ : std_logic_vector(3 downto 0) := "0101"; + constant CMD_WRITE : std_logic_vector(3 downto 0) := "0100"; + constant CMD_BURST_TERMINATE : std_logic_vector(3 downto 0) := "0110"; + constant CMD_PRECHARGE : std_logic_vector(3 downto 0) := "0010"; + constant CMD_AUTO_REFRESH : std_logic_vector(3 downto 0) := "0001"; + constant CMD_LOAD_MODE : std_logic_vector(3 downto 0) := "0000"; + + -- Load Mode Register setting for a standard SDRAM. + -- + -- xx:10 = Reserved : + -- 9 = Write Burst Mode : 0 = Programmed Burst Length, 1 = Single Location Access + -- 8:7 = Operating Mode : 00 = Standard Operation, all other values reserved. + -- 6:4 = CAS Latency : 010 = 2, 011 = 3, all other values reserved. + -- 3 = Burst Type : 0 = Sequential, 1 = Interleaved. + -- 2:0 = Burst Length : When 000 = 1, 001 = 2, 010 = 4, 011 = 8, all others reserved except 111 when BT = 0 sets full page access. + -- | A12-A10 | A9  A8-A7 | A6 A5 A4 | A3  A2 A1 A0 | + -- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len| + constant WRITE_BURST_MODE : std_logic := '1'; + constant OP_MODE : std_logic_vector(1 downto 0) := "00"; + constant CAS_LATENCY : std_logic_vector(2 downto 0) := "011"; + constant BURST_TYPE : std_logic := '0'; + constant BURST_LENGTH : std_logic_vector(2 downto 0) := "000"; + constant MODE : std_logic_vector(SDRAM_ROW_BITS-1 downto 0) := std_logic_vector(to_unsigned(to_integer(unsigned("00" & WRITE_BURST_MODE & OP_MODE & CAS_LATENCY & BURST_TYPE & BURST_LENGTH)), SDRAM_ROW_BITS)); + + -- FSM Cycle States governed in units of time, the state changes location according to the configurable parameters to ensure correct actuation at the correct time. + -- + constant CYCLE_PRECHARGE : integer := 0; -- 0 + constant CYCLE_RAS_START : integer := tRP; -- 3 + constant CYCLE_RAS_NEXT : integer := CYCLE_RAS_START + 1; -- 4 + constant CYCLE_CAS0 : integer := CYCLE_RAS_START + tRCD; -- 3 + tRCD + constant CYCLE_CAS1 : integer := CYCLE_CAS0 + 1; -- 4 + tRCD + constant CYCLE_READ0 : integer := CYCLE_CAS0 + to_integer(unsigned(CAS_LATENCY)) + 1; -- 3 + tRCD + CAS_LATENCY + constant CYCLE_READ1 : integer := CYCLE_READ0 + 1; -- 4 + tRCD + CAS_LATENCY + constant CYCLE_END : integer := CYCLE_READ1 + 4; -- 9 + tRCD + CAS_LATENCY + constant CYCLE_RFSH_START : integer := CYCLE_RAS_START; -- 3 + constant CYCLE_RFSH_END : integer := CYCLE_RFSH_START + ((tRFC/RAM_CLK) * 10000000) + 1; -- 3 + tRFC in clock ticks. + + -- Period in clock cycles between SDRAM refresh cycles. + constant REFRESH_PERIOD : integer := (RAM_CLK / (tREF * SDRAM_ROWS)) - CYCLE_END; + + type BankArray is array(natural range 0 to 3) of std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + + -- Cache for holding burst reads to allow for differing speeds of WishBone Master. + type DataCacheArray is array(natural range 0 to ((2**(MAX_DATACACHE_BITS))-1)) of std_logic_vector(WORD_32BIT_RANGE); + signal readCache : DataCacheArray; + attribute ramstyle : string; + attribute ramstyle of readCache : signal is "logic"; + signal cacheReadAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0); + signal cacheWriteAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0); + + signal sbBusy : std_logic; + signal sdCycle : integer range 0 to 31; + signal sdDone : std_logic; + signal sdCmd : std_logic_vector(3 downto 0); + signal sdRefreshCount : unsigned(9 downto 0); + signal sdAutoRefresh : std_logic; + + signal sdResetTimer : unsigned(7 downto 0); + signal sdMuxAddr : std_logic_vector(SDRAM_ROW_BITS-1 downto 0); -- 12 bit multiplexed address bus + signal sdDoneLast : std_logic; + signal sdInResetCounter : unsigned(7 downto 0); + signal sdIsWriting : std_logic; + signal isReady : std_logic; + signal sdDataOut : std_logic_vector(15 downto 0); + signal sdDataIn : std_logic_vector(15 downto 0); + signal sdActiveRow : BankArray; + signal sdActiveBank : std_logic_vector(1 downto 0); + signal sdBank : natural range 0 to 3; + signal sdRow : std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + signal sdCol : std_logic_vector(SDRAM_COLUMN_BITS-1 downto 0); + signal sdDQM : std_logic_vector(1 downto 0); + signal sdCKE : std_logic; + + signal cpuDQM : std_logic_vector(3 downto 0); + + signal dout : std_logic_vector(31 downto 0); + signal cpuDataIn : std_logic_vector(31 downto 0); +begin + + -- Tri-state control of the SDRAM data bus. + process(sdIsWriting, SDRAM_DQ, sdDataOut) + begin + if (sdIsWriting = '1') then + SDRAM_DQ <= sdDataOut; + sdDataIn <= SDRAM_DQ; + else + SDRAM_DQ <= (others => 'Z'); + sdDataIn <= SDRAM_DQ; + end if; + end process; + + -- Main FSM for SDRAM control and refresh. + process(SDRAM_CLK, SDRAM_RST) + begin + if (SDRAM_RST = '1') then + sdResetTimer <= (others => '0'); -- 0 upto 127 + sdInResetCounter <= (others => '1'); -- 255 downto 0 + sdMuxAddr <= (others => '0'); + sdAutoRefresh <= '0'; + sdRefreshCount <= (others => '0'); + sdActiveBank <= (others => '0'); + sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0')); + isReady <= '0'; + sdCmd <= CMD_AUTO_REFRESH; + sdCKE <= '1'; + sdDQM <= (others => '1'); + sdCycle <= 0; + sdDone <= '0'; + cacheWriteAddr <= (others => '0'); + + elsif rising_edge(SDRAM_CLK) then + + -- If no specific command given the default is NOP. + sdCmd <= CMD_NOP; + + -- Initialisation on power up or reset. The SDRAM must be given at least 200uS to initialise and a fixed setup pattern applied. + if (isReady = '0') then + sdResetTimer <= sdResetTimer + 1; + + -- 1uS timer. + if (sdResetTimer = RAM_CLK/1000000) then + sdResetTimer <= (others => '0'); + sdInResetCounter <= sdInResetCounter - 1; + end if; + + -- Every 1uS check for the next init action. + if (sdResetTimer = 0) then + + -- 200uS wait, no action as the SDRAM starts up. + -- ie. 255 downto 55 + + -- Precharge all banks + if(sdInResetCounter = 55) then + sdCmd <= CMD_PRECHARGE; + sdMuxAddr(10) <= '1'; + end if; + + -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after + -- the other. + if(sdInResetCounter >= 40 and sdInResetCounter <= 48) then + sdCmd <= CMD_AUTO_REFRESH; + end if; + + -- Load the Mode register with our parameters. + if(sdInResetCounter = 39) then + sdCmd <= CMD_LOAD_MODE; + sdMuxAddr <= MODE; + end if; + + -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after + -- the other. + if(sdInResetCounter >= 30 and sdInResetCounter <= 38) then + sdCmd <= CMD_AUTO_REFRESH; + end if; + + -- SDRAM ready. + if(sdInResetCounter = 20) then + isReady <= '1'; + end if; + end if; + else + + sdRefreshCount <= sdRefreshCount + 1; + + -- Auto refresh. On timeout it kicks in so that 8192 auto refreshes are + -- issued in a 64ms period. Other bus operations are stalled during this period. + if (sdRefreshCount > REFRESH_PERIOD and sdCycle = 0) then + sdAutoRefresh <= '1'; + sdRefreshCount <= (others => '0'); + sdCmd <= CMD_PRECHARGE; + sdMuxAddr(10) <= '1'; + sdActiveBank <= (others => '0'); + sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0')); + + -- In auto refresh period. + elsif (sdAutoRefresh = '1') then + + -- while the cycle is active count. + sdCycle <= sdCycle + 1; + case (sdCycle) is + when CYCLE_RFSH_START => + sdCmd <= CMD_AUTO_REFRESH; + + when CYCLE_RFSH_END => + -- reset the count. + sdAutoRefresh <= '0'; + sdCycle <= 0; + + when others => + end case; + + elsif ((sbBusy = '1' and sdCycle = 0) or sdCycle /= 0) then -- or (sdCycle = 0 and CS = '1')) then + + -- while the cycle is active count. + sdCycle <= sdCycle + 1; + case (sdCycle) is + + when CYCLE_PRECHARGE => + -- If the bank is not open then no need to precharge, move onto RAS. + if (sdActiveBank(sdBank) = '0') then + sdCycle <= CYCLE_RAS_START; + + -- If the requested row is already active, go to CAS for immediate access to this row. + elsif (sdActiveRow(sdBank) = sdRow) then + sdCycle <= CYCLE_CAS0; + + -- Otherwise we close out the open bank by issuing a PRECHARGE. + else + sdCmd <= CMD_PRECHARGE; + sdMuxAddr(10) <= '0'; + SDRAM_BA <= std_logic_vector(to_unsigned(sdBank, SDRAM_BA'length)); + sdActiveBank(sdBank) <= '0'; -- Store flag to indicate which bank is being made active. + end if; + + -- Open the requested row. + when CYCLE_RAS_START => + sdCmd <= CMD_ACTIVE; + sdMuxAddr <= sdRow; -- Addr presented to SDRAM as row address. + SDRAM_BA <= std_logic_vector(to_unsigned(sdBank, SDRAM_BA'length)); -- Addr presented to SDRAM as bank select. + sdActiveRow(sdBank) <= sdRow; -- Store number of row being made active + sdActiveBank(sdBank) <= '1'; -- Store flag to indicate which bank is being made active. + + when CYCLE_RAS_NEXT => + sdDQM <= "11"; -- Set DQ to tri--state. + + -- this is the first CAS cycle + when CYCLE_CAS0 => + -- Process on a 32bit boundary, as this is a 16bit chip we need 2 accesses for a 32bit alignment. + sdMuxAddr <= std_logic_vector(to_unsigned(to_integer(unsigned(sdCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge + SDRAM_BA <= std_logic_vector(to_unsigned(sdBank, SDRAM_BA'length)); -- Ensure bank is the correct one opened. + + -- If writing, setup for a write with preset mask. + if (sdIsWriting = '1') then + sdCmd <= CMD_WRITE; + sdDQM <= not cpuDQM(3 downto 2); + sdDataOut <= cpuDataIn(31 downto 16); -- Assign corresponding data to the SDRAM databus. + else + -- Setup for a read. + sdCmd <= CMD_READ; + sdDQM <= "00"; -- For reads dont mask the data output. + end if; + + when CYCLE_CAS1 => + sdMuxAddr <= std_logic_vector(to_unsigned(to_integer(unsigned(sdCol(SDRAM_COLUMN_BITS-1 downto 1) & '1')), SDRAM_ROW_BITS)); -- CAS address = Next address accessing second 16bit location within the 32bit external alignment with no auto precharge + SDRAM_BA <= std_logic_vector(to_unsigned(sdBank, SDRAM_BA'length)); -- Ensure bank is the correct one opened. + + -- If writing, setup for a write with preset mask. + if (sdIsWriting = '1') then + sdCmd <= CMD_WRITE; + sdDQM <= not cpuDQM(1 downto 0); + sdDone <= not sdDone; + sdDataOut <= cpuDataIn(15 downto 0); + sdCycle <= CYCLE_END; + else + -- Setup for a read, change to write if flag set. + sdCmd <= CMD_READ; + sdDQM <= "00"; -- For reads dont mask the data output. + end if; + + -- Data is available CAS Latency clocks after the read request. + when CYCLE_READ0 => + -- If writing, then we are complete, exit else read the first word. + if (sdIsWriting = '1') then + sdCycle <= CYCLE_END; + else + dout(31 downto 16) <= sdDataIn; + end if; + + when CYCLE_READ1 => + -- If writing, then we are complete, exit else read the first word. + if (sdIsWriting = '1') then + sdCycle <= CYCLE_END; + else + dout(15 downto 0) <= sdDataIn; + sdDone <= not sdDone; + end if; + + when CYCLE_END => + + when others => + end case; + else + sdCycle <= 0; + end if; + end if; + end if; + end process; + + -- CPU/BUS side logic. When the CPU initiates a transaction, capture the signals and the captured values are used within the SDRAM domain. This is to prevent + -- any changes CPU side or differing signal lengths due to CPU architecture or clock being propogated into the SDRAM domain. The CPU only needs to know + -- when the transation is complete and data read. + -- + process(RESET, CLK, CS, WRITE_BYTE, WRITE_HWORD, ADDR, WREN, RDEN, isReady) + begin + if (RESET = '1') then + sdDoneLast <= '0'; + sbBusy <= '0'; + sdBank <= 0; + sdRow <= (others => '0'); + sdCol <= (others => '0'); + cpuDQM <= (others => '1'); + sdIsWriting <= '0'; + + -- If the SDRAM isnt ready, we can only wait. + elsif isReady = '0' then + + elsif rising_edge(CLK) then + + -- Detect a Chip Select state change signalling access. + if CS = '1' and (WREN='1' or RDEN='1') then + sbBusy <= '1'; + sdIsWriting <= WREN; + sdBank <= to_integer(unsigned(ADDR(SDRAM_ADDR_BITS-1 downto SDRAM_ARRAY_BITS))); + sdRow <= std_logic_vector(to_unsigned(to_integer(unsigned(ADDR(SDRAM_ARRAY_BITS + 1 - SDRAM_BANK_BITS downto SDRAM_COLUMN_BITS))), SDRAM_ROW_BITS)); + sdCol <= ADDR(SDRAM_COLUMN_BITS-1 downto 0); + + -- Preset the write selects according to the CPU signals. Let Quartus optimize as easier to read seeing all mask values. + if(WRITE_BYTE = '1') then + case ADDR(1 downto 0) is + when "00" => cpuDQM <= "1000"; + cpuDataIn <= DATA_IN(7 downto 0) & X"000000"; + when "01" => cpuDQM <= "0100"; + cpuDataIn <= X"00" & DATA_IN(7 downto 0) & X"0000"; + when "10" => cpuDQM <= "0010"; + cpuDataIn <= X"0000" & DATA_IN(7 downto 0) & X"00"; + when "11" => cpuDQM <= "0001"; + cpuDataIn <= X"000000" & DATA_IN(7 downto 0); + when others => + end case; + + elsif(WRITE_HWORD = '1') then + + case ADDR(1) is + when '0' => cpuDQM <= "1100"; + cpuDataIn <= DATA_IN(15 downto 0) & X"0000"; + when '1' => cpuDQM <= "0011"; + cpuDataIn <= X"0000" & DATA_IN(15 downto 0); + end case; + + else + -- Reads are always 32bit wide and if no part word signal is asserted, writes are 32bit. + cpuDataIn <= DATA_IN(31 downto 0); + cpuDQM <= "1111"; + end if; + end if; + + -- Note SDRAM activity via a previous/last signal. + sdDoneLast <= sdDone; + + -- If there has been a change in the SDRAM activity reset the signals as initiated transaction is complete. + if (sdDone xor sdDoneLast) = '1' then + sbBusy <= '0'; + sdIsWriting <= '0'; + end if; + + end if; + end process; + + DATA_OUT <= dout; + + -- drive control signals according to current command + SDRAM_CS_n <= sdCmd(3); + SDRAM_RAS_n <= sdCmd(2); + SDRAM_CAS_n <= sdCmd(1); + SDRAM_WE_n <= sdCmd(0); + SDRAM_CKE <= sdCKE; + SDRAM_DQM <= sdDQM; + SDRAM_ADDR <= sdMuxAddr; + + -- System bus control signals. + BUSY <= sbBusy; + SDRAM_READY <= isReady; + +end Structure; diff --git a/zpu/devices/sysbus/SDRAM.bak/sdram_controller.vhd b/zpu/devices/sysbus/SDRAM.bak/sdram_controller.vhd new file mode 100644 index 0000000..0572d1d --- /dev/null +++ b/zpu/devices/sysbus/SDRAM.bak/sdram_controller.vhd @@ -0,0 +1,728 @@ +------------------------------------------------------ +-- FSM for a SDRAM controller +-- +-- Version 0.1 - Ready to simulate +-- +-- Authors: Mike Field (hamster@snap.net.nz) +-- Alvaro Lopes (alvieboy@alvie.com) +-- +-- Feel free to use it however you would like, but +-- just drop us an email to say thanks. +------------------------------------------------------- +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_soc_pkg.all; +use work.zpu_pkg.all; + +entity sdram_controller is + generic ( + HIGH_BIT: integer := 24; + MHZ: integer := 96; + REFRESH_CYCLES: integer := 4096; + ADDRESS_BITS: integer := 12 + ); + PORT ( + clock_100: in std_logic; + clock_100_delayed_3ns: in std_logic; + rst: in std_logic; + + -- Signals to/from the SDRAM chip + DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0); + DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); + DRAM_CAS_N : OUT STD_LOGIC; + DRAM_CKE : OUT STD_LOGIC; + DRAM_CLK : OUT STD_LOGIC; + DRAM_CS_N : OUT STD_LOGIC; + DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); + DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); + DRAM_RAS_N : OUT STD_LOGIC; + DRAM_WE_N : OUT STD_LOGIC; + + pending: out std_logic; + + --- Inputs from rest of the system + address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2); + req_read : IN STD_LOGIC; + req_write : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR (31 downto 0); + data_out_valid : OUT STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR (31 downto 0); + data_mask : IN STD_LOGIC_VECTOR (3 downto 0) + ); +end entity; + + +architecture rtl of sdram_controller is + + type reg is record + address : std_logic_vector(ADDRESS_BITS-1 downto 0); + bank : std_logic_vector( 1 downto 0); + init_counter : unsigned(14 downto 0); + rf_counter : integer; + rf_pending : std_logic; + rd_pending : std_logic; + wr_pending : std_logic; + act_row : std_logic_vector(ADDRESS_BITS-1 downto 0); + act_ba : std_logic_vector(1 downto 0); + data_out_low : std_logic_vector(15 downto 0); + req_addr_q : std_logic_vector(HIGH_BIT downto 2); + req_data_write: std_logic_vector(31 downto 0); + req_mask : std_logic_vector(3 downto 0); + data_out_valid: std_logic; + dq_masks : std_logic_vector(1 downto 0); + tristate : std_logic; + end record; + + signal r : reg; + signal n : reg; + + signal rstate : std_logic_vector(8 downto 0); + signal nstate : std_logic_vector(8 downto 0); + signal rdata_write : std_logic_vector(15 downto 0); + signal ndata_write : std_logic_vector(15 downto 0); + + + -- Vectors for each SDRAM 'command' + --- CS_N, RAS_N, CAS_N, WE_N + constant cmd_nop : std_logic_vector(3 downto 0) := "0111"; + constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low. + constant cmd_write : std_logic_vector(3 downto 0) := "0100"; + constant cmd_act : std_logic_vector(3 downto 0) := "0011"; + constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'. + constant cmd_ref : std_logic_vector(3 downto 0) := "0001"; + constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set + + -- State assignments + constant s_init_nop_id: std_logic_vector(4 downto 0) := "00000"; + + constant s_init_nop : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_nop; + constant s_init_pre : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_pre; + constant s_init_ref : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_ref; + constant s_init_mrs : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_mrs; + + constant s_idle_id: std_logic_vector(4 downto 0) := "00001"; + constant s_idle : std_logic_vector(8 downto 0) := s_idle_id & cmd_nop; + + constant s_rf0_id: std_logic_vector(4 downto 0) := "00010"; + constant s_rf0 : std_logic_vector(8 downto 0) := s_rf0_id & cmd_ref; + + constant s_rf1_id: std_logic_vector(4 downto 0) := "00011"; + constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop; + + constant s_rf2_id: std_logic_vector(4 downto 0) := "00100"; + constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop; + + constant s_rf3_id: std_logic_vector(4 downto 0) := "00101"; + constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop; + + constant s_rf4_id: std_logic_vector(4 downto 0) := "00110"; + constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop; + + constant s_rf5_id: std_logic_vector(4 downto 0) := "00111"; + constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop; + + + constant s_ra0_id: std_logic_vector(4 downto 0) := "01000"; + constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act; + + constant s_ra1_id: std_logic_vector(4 downto 0) := "01001"; + constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop; + + constant s_ra2_id: std_logic_vector(4 downto 0) := "01010"; + constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop; + + + constant s_dr0_id: std_logic_vector(4 downto 0) := "01011"; + constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre; + + constant s_dr1_id: std_logic_vector(4 downto 0) := "01100"; + constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop; + + constant s_wr0_id: std_logic_vector(4 downto 0) := "01101"; + constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write; + + constant s_wr1_id: std_logic_vector(4 downto 0) := "01110"; + constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop; + + constant s_wr2_id: std_logic_vector(4 downto 0) := "01111"; + constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop; + + constant s_wr3_id: std_logic_vector(4 downto 0) := "10000"; + constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_write; + + + constant s_rd0_id: std_logic_vector(4 downto 0) := "10001"; + constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read; + + constant s_rd1_id: std_logic_vector(4 downto 0) := "10010"; + constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_read; + + constant s_rd2_id: std_logic_vector(4 downto 0) := "10011"; + constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop; + + constant s_rd3_id: std_logic_vector(4 downto 0) := "10100"; + constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_read; + + constant s_rd4_id: std_logic_vector(4 downto 0) := "10101"; + constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read; + + constant s_rd5_id: std_logic_vector(4 downto 0) := "10110"; + constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_read; + + constant s_rd6_id: std_logic_vector(4 downto 0) := "10111"; + constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop; + + constant s_rd7_id: std_logic_vector(4 downto 0) := "11000"; + constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop; + + constant s_rd8_id: std_logic_vector(4 downto 0) := "11001"; + constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop; + + constant s_rd9_id: std_logic_vector(4 downto 0) := "11011"; + constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop; + + + constant s_drdr0_id: std_logic_vector(4 downto 0) := "11101"; + constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre; + + constant s_drdr1_id: std_logic_vector(4 downto 0) := "11110"; + constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop; + + constant s_drdr2_id: std_logic_vector(4 downto 0) := "11111"; + constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop; + + signal addr_row : std_logic_vector(ADDRESS_BITS-1 downto 0); + signal addr_bank: std_logic_vector(1 downto 0); + + constant COLUMN_HIGH: integer := HIGH_BIT - addr_row'LENGTH - addr_bank'LENGTH - 1; -- last 1 means 16 bit width + + + signal addr_col : std_logic_vector(7 downto 0); + signal captured : std_logic_vector(15 downto 0); + signal busy: std_logic; + + constant tOPD: time := 1.4 ns; + constant tHZ: time := 8 ns; + + signal dram_dq_dly : std_logic_vector(15 downto 0); + + -- Debug only + signal debug_cmd: std_logic_vector(3 downto 0); + + constant RELOAD: integer := (((64000000/REFRESH_CYCLES)*MHZ)/1000) - 10; + + attribute IOB: string; + + signal i_DRAM_CS_N: std_logic; + attribute IOB of i_DRAM_CS_N: signal is "true"; + + signal i_DRAM_RAS_N: std_logic; + attribute IOB of i_DRAM_RAS_N: signal is "true"; + + signal i_DRAM_CAS_N: std_logic; + attribute IOB of i_DRAM_CAS_N: signal is "true"; + + signal i_DRAM_WE_N: std_logic; + attribute IOB of i_DRAM_WE_N: signal is "true"; + + signal i_DRAM_ADDR: std_logic_vector(ADDRESS_BITS-1 downto 0); + attribute IOB of i_DRAM_ADDR: signal is "true"; + + signal i_DRAM_BA: std_logic_vector(1 downto 0); + attribute IOB of i_DRAM_BA: signal is "true"; + + signal i_DRAM_DQM: std_logic_vector(1 downto 0); + attribute IOB of i_DRAM_DQM: signal is "true"; + + attribute IOB of rdata_write: signal is "true"; + attribute IOB of captured: signal is "true"; + + signal i_DRAM_CLK: std_logic; + + attribute fsm_encoding: string; + attribute fsm_encoding of nstate: signal is "user"; + attribute fsm_encoding of rstate: signal is "user"; + +begin + + debug_cmd <= rstate(3 downto 0); + + -- Addressing is in 32 bit words - twice that of the DRAM width, + -- so each burst of four access two system words. + --addr_row <= address(23 downto 11); + --addr_bank <= address(10 downto 9); + process(r.req_addr_q) + begin + addr_bank <= r.req_addr_q(HIGH_BIT downto (HIGH_BIT-addr_bank'LENGTH)+1); + -- (24-2) downto (24-2 - 2 - 13 - 1) + -- 22 downto 6 + addr_row <= --r.req_addr_q(HIGH_BIT-addr_bank'LENGTH downto COLUMN_HIGH+2); + r.req_addr_q(ADDRESS_BITS-1+9 downto 9); + addr_col <= (others => '0'); + + addr_col <= --r.req_addr_q(COLUMN_HIGH+1 downto 2) & "0"; + r.req_addr_q(8 downto 2) & "0"; + end process; + + clock: entity work.oddrff + port map ( + D0 => '0', + D1 => '1', + O => i_DRAM_CLK, + CLK => clock_100 + ); + + DRAM_CKE <= '1'; + + DRAM_CLK <= clock_100; -- transport i_DRAM_CLK after tOPD; + + i_DRAM_CS_N <= transport rstate(3) after tOPD; + DRAM_CS_N <= i_DRAM_CS_N; + + i_DRAM_RAS_N <= transport rstate(2) after tOPD; + DRAM_RAS_N <= i_DRAM_RAS_N; + + i_DRAM_CAS_N <= transport rstate(1) after tOPD; + DRAM_CAS_N <= i_DRAM_CAS_N; + + i_DRAM_WE_N <= transport rstate(0) after tOPD; + DRAM_WE_N <= i_DRAM_WE_N; + + i_DRAM_ADDR <= transport r.address after tOPD; + DRAM_ADDR <= i_DRAM_ADDR; + + i_DRAM_BA <= transport r.bank after tOPD; + DRAM_BA <= i_DRAM_BA; + + i_DRAM_DQM <= transport r.dq_masks after tOPD; + DRAM_DQM <= i_DRAM_DQM; + + DATA_OUT <= r.data_out_low & captured;--r.data_out_low & captured; + data_out_valid <= r.data_out_valid; + + DRAM_DQ <= (others => 'Z') after tHZ when r.tristate='1' else rdata_write; + + pending <= '1' when r.wr_pending='1' or r.rd_pending='1' else '0'; + + process (r, rstate, address, req_read, rdata_write, req_write, addr_row, addr_bank, addr_col, data_in, captured) + begin + -- copy the existing values + n <= r; + nstate <= rstate; + ndata_write <= rdata_write; + + if req_read = '1' then + n.rd_pending <= '1'; + if r.rd_pending='0' then + n.req_addr_q <= address; + end if; + end if; + + if req_write = '1' then + n.wr_pending <= '1'; + if r.wr_pending='0' then + n.req_addr_q <= address; + -- Queue data here + n.req_data_write <= data_in; + n.req_mask <= data_mask; + end if; + end if; + + n.dq_masks <= "11"; + + -- first off, do we need to perform a refresh cycle ASAP? + if r.rf_counter = RELOAD then -- 781 = 64,000,000ns / 8192 / 10ns + n.rf_counter <= 0; + n.rf_pending <= '1'; + else + -- only start looking for refreshes outside of the initialisation state. + if not(rstate(8 downto 4) = s_init_nop(8 downto 4)) then + n.rf_counter <= r.rf_counter + 1; + end if; + end if; + + -- Set the data bus into HIZ, high and low bytes masked + --DRAM_DQ <= (others => 'Z'); + n.tristate <= '0'; + + n.init_counter <= r.init_counter - 1; + + --ndata_write <= (others => DontCareValue); + + n.data_out_valid <= '0'; -- alvie- here, no ? + + -- Process the FSM + case rstate(8 downto 4) is + when s_init_nop_id => --s_init_nop(8 downto 4) => + nstate <= s_init_nop; + n.address <= (others => '0'); + n.bank <= (others => '0'); + n.act_ba <= (others => '0'); + n.rf_counter <= 0; + -- n.data_out_valid <= '1'; -- alvie- not here + + -- T-130, precharge all banks. + if r.init_counter = "000000010000010" then + nstate <= s_init_pre; + n.address(10) <= '1'; + end if; + + -- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes + + if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then + nstate <= s_init_ref; + end if; + + -- T-3, the load mode register + if r.init_counter = 3 then + nstate <= s_init_mrs; + -- Mode register is as follows: + -- resvd wr_b OpMd CAS=3 Seq bust=1 + n.address <= "00" & "0" & "00" & "011" & "0" & "000"; + -- resvd + n.bank <= "00"; + end if; + + -- T-1 The switch to the FSM (first command will be a NOP + if r.init_counter = 1 then + nstate <= s_idle; + end if; + + ------------------------------ + -- The Idle section + ------------------------------ + when s_idle_id => + nstate <= s_idle; + + -- do we have to activate a row? + if r.rd_pending = '1' or r.wr_pending = '1' then + nstate <= s_ra0; + n.address <= addr_row; + n.act_row <= addr_row; + n.bank <= addr_bank; + end if; + + -- refreshes take priority over everything + if r.rf_pending = '1' then + nstate <= s_rf0; + n.rf_pending <= '0'; + end if; + ------------------------------ + -- Row activation + -- s_ra2 is also the "idle with active row" state and provides + -- a resting point between operations on the same row + ------------------------------ + when s_ra0_id => + nstate <= s_ra1; + when s_ra1_id => + nstate <= s_ra2; + + + when s_ra2_id=> + -- we can stay in this state until we have something to do + nstate <= s_ra2; + n.tristate<='0'; + + if r.rf_pending = '1' then + nstate <= s_dr0; + n.address(10) <= '1'; + else + + -- If there is a read pending, deactivate the row + if r.rd_pending = '1' or r.wr_pending = '1' then + nstate <= s_dr0; + n.address(10) <= '1'; + end if; + + -- unless we have a read to perform on the same row? do that instead + if r.rd_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then + nstate <= s_rd0; + n.address <= (others => '0'); + n.address(addr_col'HIGH downto 0) <= addr_col; + n.bank <= addr_bank; + n.act_ba <= addr_bank; + n.dq_masks <= "00"; + n.rd_pending <= '0'; + --n.tristate<='1'; + end if; + + -- unless we have a write on the same row? writes take priroty over reads + if r.wr_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then + nstate <= s_wr0; + n.address <= (others => '0'); + n.address(addr_col'HIGH downto 0) <= addr_col; + ndata_write <= r.req_data_write(31 downto 16); + n.bank <= addr_bank; + n.act_ba <= addr_bank; + n.dq_masks<= not r.req_mask(3 downto 2); + n.wr_pending <= '0'; + --n.tristate <= '0'; + end if; + + + end if; + -- nstate <= s_dr0; + -- n.address(10) <= '1'; + -- n.rd_pending <= r.rd_pending; + -- n.wr_pending <= r.wr_pending; + --n.tristate <= '0'; + --end if; + + ------------------------------------------------------ + -- Deactivate the current row and return to idle state + ------------------------------------------------------ + when s_dr0_id => + nstate <= s_dr1; + when s_dr1_id => + nstate <= s_idle; + + ------------------------------ + -- The Refresh section + ------------------------------ + when s_rf0_id => + nstate <= s_rf1; + when s_rf1_id => + nstate <= s_rf2; + when s_rf2_id => + nstate <= s_rf3; + when s_rf3_id => + nstate <= s_rf4; + when s_rf4_id => + nstate <= s_rf5; + when s_rf5_id => + nstate <= s_idle; + ------------------------------ + -- The Write section + ------------------------------ + when s_wr0_id => + nstate <= s_wr3; + n.bank <= addr_bank; + n.address(0) <= '1'; + ndata_write <= r.req_data_write(15 downto 0);--data_in(31 downto 16); + --DRAM_DQ <= rdata_write; + n.dq_masks<= not r.req_mask(1 downto 0); + n.tristate <= '0'; + + when s_wr1_id => null; + when s_wr2_id => + nstate <= s_dr0; + n.address(10) <= '1'; + + + when s_wr3_id => + -- Default to the idle+row active state + nstate <= s_ra2; + --DRAM_DQ <= rdata_write; + n.data_out_valid<='1'; -- alvie- ack write + n.tristate <= '0'; + n.dq_masks<= "11"; + + -- If there is a read or write then deactivate the row + --if r.rd_pending = '1' or r.wr_pending = '1' then + -- nstate <= s_dr0; + -- n.address(10) <= '1'; + --end if; + + -- But if there is a read pending in the same row, do that + --if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then + -- nstate <= s_rd0; + -- n.address <= (others => '0'); + -- n.address(addr_col'HIGH downto 0) <= addr_col; + -- n.bank <= addr_bank; + -- --n.act_ba <= addr_bank; + -- n.dq_masks <= "00"; + -- n.rd_pending <= '0'; + --end if; + + -- unless there is a write pending in the same row, do that + --if r.wr_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then + -- nstate <= s_wr0; + -- n.address <= (others => '0'); + -- n.address(addr_col'HIGH downto 0) <= addr_col; + -- n.bank <= addr_bank; + --n.act_ba <= addr_bank; + -- n.dq_masks<= "00"; + -- n.wr_pending <= '0'; + --end if; + + -- But always try and refresh if one is pending! + if r.rf_pending = '1' then + nstate <= s_wr2; --dr0; + --n.address(10) <= '1'; + end if; + + ------------------------------ + -- The Read section + ------------------------------ + when s_rd0_id => -- 10001 + nstate <= s_rd1; + n.tristate<='1'; + n.dq_masks <= "00"; + n.address(0)<='1'; + + when s_rd1_id => -- 10010 + nstate <= s_rd2; + n.dq_masks <= "00"; + n.tristate<='1'; + if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then + + nstate <= s_rd3; -- Another request came, and we can pipeline - + n.address <= (others => '0'); + n.address(addr_col'HIGH downto 0) <= addr_col; + n.bank <= addr_bank; + n.act_ba <= addr_bank; + n.dq_masks<= "00"; + n.rd_pending <= '0'; + + end if; + + when s_rd2_id => -- 10011 + nstate <= s_rd7; + n.dq_masks <= "00"; + n.tristate<='1'; + + + when s_rd3_id => -- 10100 + + nstate <= s_rd4; + n.dq_masks <= "00"; + n.address(0) <= '1'; + n.tristate<='1'; + + + -- Data is still not ready... + + when s_rd4_id => -- 10101 + nstate <= s_rd5; + n.dq_masks <= "00"; + --n.address(0)<='1'; + n.tristate<='1'; + + if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then + nstate <= s_rd5; -- Another request came, and we can pipeline - + + n.address <= (others => '0'); + n.address(addr_col'HIGH downto 0) <= addr_col; + n.bank <= addr_bank; + n.act_ba <= addr_bank; + n.dq_masks<= "00"; + n.rd_pending <= '0'; + + else + nstate <= s_rd6; -- NOTE: not correct + end if; + + --if r.rf_pending = '1' then + -- nstate <= s_drdr0; + -- n.address(10) <= '1'; + -- n.rd_pending <= r.rd_pending; -- Keep request + --end if; + + + n.data_out_low <= captured; + n.data_out_valid <= '1'; + + + when s_rd5_id => + -- If a refresh is pending then always deactivate the row + --if r.rf_pending = '1' then + -- nstate <= s_drdr0; + -- n.address(10) <= '1'; + --end if; + + n.address(0) <= '1'; + nstate <= s_rd4; -- Another request came, and we can pipeline - + n.dq_masks <= "00"; + n.tristate<='1'; + + when s_rd6_id => + nstate <= s_rd7; + n.dq_masks<= "00"; + n.tristate<='1'; + + when s_rd7_id => + nstate <= s_ra2; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + n.tristate<='1'; + + when s_rd8_id => null; + + when s_rd9_id => null; + + -- The Deactivate row during read section + ------------------------------ + when s_drdr0_id => + nstate <= s_drdr1; + when s_drdr1_id => + nstate <= s_drdr2; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + when s_drdr2_id => + nstate <= s_idle; + + if r.rf_pending = '1' then + nstate <= s_rf0; + end if; + + if r.rd_pending = '1' or r.wr_pending = '1' then + nstate <= s_ra0; + n.address <= addr_row; + n.act_row <= addr_row; + n.bank <= addr_bank; + end if; + + when others => + nstate <= s_init_nop; + end case; + end process; + + --- The clock driven logic + process (clock_100, n) + begin + if clock_100'event and clock_100 = '1' then + if rst='1' then + rstate <= (others => '0'); + r.address <= (others => '0'); + r.bank <= (others => '0'); + r.init_counter <= "100000000000000"; + -- synopsys translate_off + r.init_counter <= "000000100000000"; + -- synopsys translate_on + r.rf_counter <= 0; + r.rf_pending <= '0'; + r.rd_pending <= '0'; + r.wr_pending <= '0'; + r.act_row <= (others => '0'); + r.data_out_low <= (others => '0'); + r.data_out_valid <= '0'; + r.dq_masks <= "11"; + r.tristate<='1'; + else + r <= n; + rstate <= nstate; + rdata_write <= ndata_write; + end if; + end if; + end process; + + dram_dq_dly <= transport dram_dq after 3.6 ns;--1.9 ns; + +-- process (clock_100_delayed_3ns, dram_dq_dly) +-- begin +-- if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then +-- captured <= dram_dq_dly; +-- end if; +-- end process; + + process (clock_100_delayed_3ns) + begin + if falling_edge(clock_100_delayed_3ns) then + captured <= dram_dq_dly; + end if; + end process; + +end rtl; diff --git a/zpu/devices/sysbus/SDRAM/48LC16M16.qip b/zpu/devices/sysbus/SDRAM/48LC16M16.qip new file mode 100644 index 0000000..4ebc57b --- /dev/null +++ b/zpu/devices/sysbus/SDRAM/48LC16M16.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sdram.vhd ] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) 48LC16M16.sdc ] diff --git a/zpu/devices/sysbus/SDRAM/48LC16M16.sdc b/zpu/devices/sysbus/SDRAM/48LC16M16.sdc new file mode 100644 index 0000000..130d03f --- /dev/null +++ b/zpu/devices/sysbus/SDRAM/48LC16M16.sdc @@ -0,0 +1,91 @@ +derive_pll_clocks + +# ------------------------------------------------------------------------------ +# Constraints definition original author: +# 8/19/2014 D. W. Hawkings (dwh@ovro.caltech.edu) +# Adapted and enhanced for the Micron 48LC16M16 SDRAM by Philip Smart Dec 2019. +# ------------------------------------------------------------------------------ + +# ----------------------------------------------------------------- +# SDRAM Clock +# Set these variables to the system and memory clock PLL paths for +# your board. +# ----------------------------------------------------------------- +set sysclk_pll "mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk" +set memclk_pll "mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk" +create_generated_clock -name SDRAM_CLK -source $memclk_pll [get_ports {SDRAM_CLK}] +derive_clock_uncertainty + +# ----------------------------------------------------------------- +# SDRAM Constraints +# ----------------------------------------------------------------- +# +# SDRAM timing parameters +# +# Generally, the command/address/data all have the same setup/hold +# time. +# +# SDRAM clock can lead System clock by min: +# tlead = tcoutmin(FPGA) – th(SDRAM) +# +# SDRAM clock can lag System clock by min: +# tlag = toh(SDRAM) – th(FPGA) +# +# tSU = Data Setup time (ie. tDS, tAS) on falling edge. +# tH = Hold time (ie. tDH, tAH) for SDRAM. +# tCOUT (min) = Data out hold time (ie. tOH) +# tCOUT (max) = Access time for CL in use (ie. tAC3). +# +set sdram_tsu 1.5 +set sdram_th 0.8 +set sdram_tco_min 3.0 +set sdram_tco_max 5.4 + +# FPGA timing constraints +set sdram_input_delay_min $sdram_tco_min +set sdram_input_delay_max $sdram_tco_max +set sdram_output_delay_min -$sdram_th +set sdram_output_delay_max $sdram_tsu + +# PLL to FPGA output (clear the unconstrained path warning) +#set_min_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 1 +#set_max_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 6 + +# FPGA Outputs +set sdram_outputs [get_ports { + SDRAM_CKE + SDRAM_CS + SDRAM_RAS + SDRAM_CAS + SDRAM_WE + SDRAM_DQM[*] + SDRAM_BA[*] + SDRAM_ADDR[*] + SDRAM_DQ[*] +}] +set_output_delay -clock SDRAM_CLK -min $sdram_output_delay_min $sdram_outputs +set_output_delay -clock SDRAM_CLK -max $sdram_output_delay_max $sdram_outputs + +# FPGA Inputs +set sdram_inputs [get_ports { + SDRAM_DQ[*] +}] +set_input_delay -clock SDRAM_CLK -min $sdram_input_delay_min $sdram_inputs +set_input_delay -clock SDRAM_CLK -max $sdram_input_delay_max $sdram_inputs + +# ----------------------------------------------------------------- +# SDRAM-to-FPGA multi-cycle constraint +# ----------------------------------------------------------------- + +# The PLL is configured so that SDRAM clock leads the system +# clock by ~90-degrees (0.25 period or 2.5ns for 100MHz clock). +# This will need changing for different clocks, in the PLL +# RTL file and the SoC contraints file. + +# The following multi-cycle constraint declares to TimeQuest that +# the path between the SDRAM_CLK and the System Clock can be an +# extra clock period to the read path to ensure that the latch +# clock that occurs 1.25 periods after the launch clock is used in +# the timing analysis. +# +set_multicycle_path -setup -end -from SDRAM_CLK -to $sysclk_pll 2 diff --git a/zpu/devices/sysbus/SDRAM/48LC16M16_cached.qip b/zpu/devices/sysbus/SDRAM/48LC16M16_cached.qip new file mode 100644 index 0000000..68ab3dd --- /dev/null +++ b/zpu/devices/sysbus/SDRAM/48LC16M16_cached.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sdram_cached.vhd ] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) 48LC16M16.sdc ] diff --git a/zpu/devices/sysbus/SDRAM/AS4C16M16SA.qip b/zpu/devices/sysbus/SDRAM/AS4C16M16SA.qip new file mode 100644 index 0000000..f31da60 --- /dev/null +++ b/zpu/devices/sysbus/SDRAM/AS4C16M16SA.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sdram.vhd ] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) AS4C16M16SA.sdc ] diff --git a/zpu/devices/sysbus/SDRAM/AS4C16M16SA.sdc b/zpu/devices/sysbus/SDRAM/AS4C16M16SA.sdc new file mode 100644 index 0000000..e37520a --- /dev/null +++ b/zpu/devices/sysbus/SDRAM/AS4C16M16SA.sdc @@ -0,0 +1,92 @@ +derive_pll_clocks + +# ------------------------------------------------------------------------------ +# Constraints definition original author: +# 8/19/2014 D. W. Hawkings (dwh@ovro.caltech.edu) +# Adapted and enhanced for the Alliance Memory AS4C16M16SA SDRAM by Philip Smart +# Apr 2020. +# ------------------------------------------------------------------------------ + +# ----------------------------------------------------------------- +# SDRAM Clock +# Set these variables to the system and memory clock PLL paths for +# your board. +# ----------------------------------------------------------------- +set sysclk_pll "IOPCLK|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk" +set memclk_pll "IOPCLK|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk" +create_generated_clock -name SDRAM_CLK -source $memclk_pll [get_ports {SDRAM_CLK}] +derive_clock_uncertainty + +# ----------------------------------------------------------------- +# SDRAM Constraints +# ----------------------------------------------------------------- +# +# SDRAM timing parameters +# +# Generally, the command/address/data all have the same setup/hold +# time. +# +# SDRAM clock can lead System clock by min: +# tlead = tcoutmin(FPGA) – th(SDRAM) +# +# SDRAM clock can lag System clock by min: +# tlag = toh(SDRAM) – th(FPGA) +# +# tSU = Data Setup time (ie. tDS, tAS) on falling edge. +# tH = Hold time (ie. tDH, tAH) for SDRAM. +# tCOUT (min) = Data out hold time (ie. tOH) +# tCOUT (max) = Access time for CL in use (ie. tAC3). +# +set sdram_tsu 1.5 +set sdram_th 0.8 +set sdram_tco_min 3.0 +set sdram_tco_max 5.4 + +# FPGA timing constraints +set sdram_input_delay_min $sdram_tco_min +set sdram_input_delay_max $sdram_tco_max +set sdram_output_delay_min -$sdram_th +set sdram_output_delay_max $sdram_tsu + +# PLL to FPGA output (clear the unconstrained path warning) +#set_min_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 1 +#set_max_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 6 + +# FPGA Outputs +set sdram_outputs [get_ports { + SDRAM_CKE + SDRAM_nCS + SDRAM_nRAS + SDRAM_nCAS + SDRAM_nWE + SDRAM_DQM[*] + SDRAM_BA[*] + SDRAM_A[*] + SDRAM_DQ[*] +}] +set_output_delay -clock SDRAM_CLK -min $sdram_output_delay_min $sdram_outputs +set_output_delay -clock SDRAM_CLK -max $sdram_output_delay_max $sdram_outputs + +# FPGA Inputs +set sdram_inputs [get_ports { + SDRAM_DQ[*] +}] +set_input_delay -clock SDRAM_CLK -min $sdram_input_delay_min $sdram_inputs +set_input_delay -clock SDRAM_CLK -max $sdram_input_delay_max $sdram_inputs + +# ----------------------------------------------------------------- +# SDRAM-to-FPGA multi-cycle constraint +# ----------------------------------------------------------------- + +# The PLL is configured so that SDRAM clock leads the system +# clock by ~90-degrees (0.25 period or 2.5ns for 100MHz clock). +# This will need changing for different clocks, in the PLL +# RTL file and the SoC contraints file. + +# The following multi-cycle constraint declares to TimeQuest that +# the path between the SDRAM_CLK and the System Clock can be an +# extra clock period to the read path to ensure that the latch +# clock that occurs 1.25 periods after the launch clock is used in +# the timing analysis. +# +set_multicycle_path -setup -end -from SDRAM_CLK -to $sysclk_pll 2 diff --git a/zpu/devices/sysbus/SDRAM/AS4C16M16SA_cached.qip b/zpu/devices/sysbus/SDRAM/AS4C16M16SA_cached.qip new file mode 100644 index 0000000..83a976f --- /dev/null +++ b/zpu/devices/sysbus/SDRAM/AS4C16M16SA_cached.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sdram_cached.vhd ] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) AS4C16M16SA.sdc ] diff --git a/zpu/devices/sysbus/SDRAM/W9864G6.qip b/zpu/devices/sysbus/SDRAM/W9864G6.qip new file mode 100644 index 0000000..29c8973 --- /dev/null +++ b/zpu/devices/sysbus/SDRAM/W9864G6.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sdram.vhd ] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) W9864G6.sdc ] diff --git a/zpu/devices/sysbus/SDRAM/W9864G6.sdc b/zpu/devices/sysbus/SDRAM/W9864G6.sdc new file mode 100644 index 0000000..b335274 --- /dev/null +++ b/zpu/devices/sysbus/SDRAM/W9864G6.sdc @@ -0,0 +1,91 @@ +derive_pll_clocks + +# ------------------------------------------------------------------------------ +# Constraints definition original author: +# 8/19/2014 D. W. Hawkings (dwh@ovro.caltech.edu) +# Adapted and enhanced for the Winbond W9864G6 SDRAM by Philip Smart Dec 2019. +# ------------------------------------------------------------------------------ + +# ----------------------------------------------------------------- +# SDRAM Clock +# Set these variables to the system and memory clock PLL paths for +# your board. +# ----------------------------------------------------------------- +set sysclk_pll "mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk" +set memclk_pll "mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk" +create_generated_clock -name SDRAM_CLK -source $memclk_pll [get_ports {SDRAM_CLK}] +derive_clock_uncertainty + +# ----------------------------------------------------------------- +# SDRAM Constraints +# ----------------------------------------------------------------- +# +# SDRAM timing parameters +# +# Generally, the command/address/data all have the same setup/hold +# time. +# +# SDRAM clock can lead System clock by min: +# tlead = tcoutmin(FPGA) – th(SDRAM) +# +# SDRAM clock can lag System clock by min: +# tlag = toh(SDRAM) – th(FPGA) +# +# tSU = Data Setup time (ie. tDS, tAS) on falling edge. +# tH = Hold time (ie. tDH, tAH) for SDRAM. +# tCOUT (min) = Data out hold time (ie. tOH) +# tCOUT (max) = Access time for CL in use (ie. tAC3). +# +set sdram_tsu 1.5 +set sdram_th 0.8 +set sdram_tco_min 3.0 +set sdram_tco_max 5.0 + +# FPGA timing constraints +set sdram_input_delay_min $sdram_tco_min +set sdram_input_delay_max $sdram_tco_max +set sdram_output_delay_min -$sdram_th +set sdram_output_delay_max $sdram_tsu + +# PLL to FPGA output (clear the unconstrained path warning) +#set_min_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 1 +#set_max_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 6 + +# FPGA Outputs +set sdram_outputs [get_ports { + SDRAM_CKE + SDRAM_CS + SDRAM_RAS + SDRAM_CAS + SDRAM_WE + SDRAM_DQM[*] + SDRAM_BA[*] + SDRAM_ADDR[*] + SDRAM_DQ[*] +}] +set_output_delay -clock SDRAM_CLK -min $sdram_output_delay_min $sdram_outputs +set_output_delay -clock SDRAM_CLK -max $sdram_output_delay_max $sdram_outputs + +# FPGA Inputs +set sdram_inputs [get_ports { + SDRAM_DQ[*] +}] +set_input_delay -clock SDRAM_CLK -min $sdram_input_delay_min $sdram_inputs +set_input_delay -clock SDRAM_CLK -max $sdram_input_delay_max $sdram_inputs + +# ----------------------------------------------------------------- +# SDRAM-to-FPGA multi-cycle constraint +# ----------------------------------------------------------------- + +# The PLL is configured so that SDRAM clock leads the system +# clock by ~90-degrees (0.25 period or 2.5ns for 100MHz clock). +# This will need changing for different clocks, in the PLL +# RTL file and the SoC contraints file. + +# The following multi-cycle constraint declares to TimeQuest that +# the path between the SDRAM_CLK and the System Clock can be an +# extra clock period to the read path to ensure that the latch +# clock that occurs 1.25 periods after the launch clock is used in +# the timing analysis. +# +set_multicycle_path -setup -end -from SDRAM_CLK -to $sysclk_pll 2 diff --git a/zpu/devices/sysbus/SDRAM/W9864G6_cached.qip b/zpu/devices/sysbus/SDRAM/W9864G6_cached.qip new file mode 100644 index 0000000..52de1d4 --- /dev/null +++ b/zpu/devices/sysbus/SDRAM/W9864G6_cached.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sdram_cached.vhd ] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) W9864G6.sdc ] diff --git a/zpu/devices/sysbus/SDRAM/sdram.vhd b/zpu/devices/sysbus/SDRAM/sdram.vhd new file mode 100644 index 0000000..84801b3 --- /dev/null +++ b/zpu/devices/sysbus/SDRAM/sdram.vhd @@ -0,0 +1,517 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: sdram.vhd +-- Created: September 2019 +-- Author: Philip Smart +-- Description: A configurable cached sdram controller for use with the ZPU EVO Processor and SoC. +-- The module is instantiated with the parameters to describe the underlying SDRAM chip +-- and in theory should work with most 16/32 bit SDRAM chips if they adhere to the SDRAM +-- standard. +-- Credits: Stephen J. Leary 2013-2014 - Basic sdram cycle structure of this module was based on +-- the verilog MT48LC16M16 chip controller written by Stephen. +-- Copyright: (c) 2019-2020 Philip Smart +-- +-- History: September 2019 - Initial module translation to VHDL based on Stephen J. Leary's Verilog +-- source code. +-- November 2019 - Adapted for the system bus for use when no Wishbone interface is +-- instantiated in the ZPU Evo. +-- December 2019 - Extensive changes, metability stability, autorefresh to ACTIVE timing +-- and parameterisation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_soc_pkg.all; +use work.zpu_pkg.all; + +entity SDRAM is + generic ( + MAX_DATACACHE_BITS : integer := 4; -- Maximum size in addr bits of 32bit datacache for burst transactions. + SDRAM_ROWS : integer := 4096; -- Number of Rows in the SDRAM. + SDRAM_COLUMNS : integer := 256; -- Number of Columns in an SDRAM page (ie. 1 row). + SDRAM_BANKS : integer := 4; -- Number of banks in the SDRAM. + SDRAM_DATAWIDTH : integer := 16; -- Data width of SDRAM chip (16, 32). + SDRAM_CLK_FREQ : integer := 100000000; -- Frequency of the SDRAM clock in Hertz. + SDRAM_tRCD : integer := 20; -- tRCD - RAS to CAS minimum period (in ns). + SDRAM_tRP : integer := 20; -- tRP - Precharge delay, min time for a precharge command to complete (in ns). + SDRAM_tRFC : integer := 70; -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns + SDRAM_tREF : integer := 64 -- tREF - period of time a complete refresh of all rows is made within (in ms). + ); + port ( + -- SDRAM Interface + SDRAM_CLK : in std_logic; -- SDRAM is accessed at given clock, frequency specified in RAM_CLK. + SDRAM_RST : in std_logic; -- Reset the sdram controller. + SDRAM_CKE : out std_logic; -- Clock enable. + SDRAM_DQ : inout std_logic_vector(SDRAM_DATAWIDTH-1 downto 0); -- Bidirectional data bus + SDRAM_ADDR : out std_logic_vector(log2ceil(SDRAM_ROWS) - 1 downto 0); -- Multiplexed address bus + SDRAM_DQM : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of byte masks dependent on number of banks. + SDRAM_BA : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of banks in SDRAM + SDRAM_CS_n : out std_logic; -- Single chip select + SDRAM_WE_n : out std_logic; -- Write enable + SDRAM_RAS_n : out std_logic; -- Row address select + SDRAM_CAS_n : out std_logic; -- Columns address select + SDRAM_READY : out std_logic; -- SD ready. + + -- CPU Interface + CLK : in std_logic; -- System master clock + RESET : in std_logic; -- High active sync reset + ADDR : in std_logic_vector(log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS) downto 0); + DATA_IN : in std_logic_vector(WORD_32BIT_RANGE); -- Write data + DATA_OUT : out std_logic_vector(WORD_32BIT_RANGE); -- Read data + WRITE_BYTE : in std_logic; -- Write a single byte as specified in A1:A0 + WRITE_HWORD : in std_logic; -- Write a 16bit word as specified in A1 + CS : in std_logic; -- Chip Select. + WREN : in std_logic; -- Write enable. + RDEN : in std_logic; -- Read enable. + BUSY : out std_logic -- Memory is busy, hold CPU. + ); +end SDRAM; + +architecture Structure of SDRAM is + + -- Constants to define the structure of the SDRAM in bits for provisioning of signals. + constant SDRAM_ROW_BITS : integer := log2ceil(SDRAM_ROWS); + constant SDRAM_COLUMN_BITS : integer := log2ceil(SDRAM_COLUMNS); + constant SDRAM_ARRAY_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS); + constant SDRAM_BANK_BITS : integer := log2ceil(SDRAM_BANKS); + constant SDRAM_ADDR_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS * (SDRAM_DATAWIDTH/8)); + + -- Command table for a standard SDRAM. + -- + -- Name (Function) CKE CS# RAS# CAS# WE# DQM ADDR DQ + -- COMMAND INHIBIT (NOP) H H X X X X X X + -- NO OPERATION (NOP) H L H H H X X X + -- ACTIVE (select bank and activate row) H L L H H X Bank/row X + -- READ (select bank and column, and start READ burst) H L H L H L/H Bank/col X + -- WRITE (select bank and column, and start WRITE burst) H L H L L L/H Bank/col Valid + -- BURST TERMINATE H L H H L X X Active + -- PRECHARGE (Deactivate row in bank or banks) H L L H L X Code X + -- AUTO REFRESH or SELF REFRESH (enter self refresh mode) H L L L H X X X + -- LOAD MODE REGISTER H L L L L X Op-code X + -- Write enable/output enable H X X X X L X Active + -- Write inhibit/output High-Z H X X X X H X High-Z + -- Self Refresh Entry L L L L H X X X + -- Self Refresh Exit (Device is idle) H H X X X X X X + -- Self Refresh Exit (Device is in Self Refresh state) H L H H X X X X + -- Clock suspend mode Entry L X X X X X X X + -- Clock suspend mode Exit H X X X X X X X + -- Power down mode Entry (Device is idle) L H X X X X X X + -- Power down mode Entry (Device is Active) L L H H X X X X + -- Power down mode Exit (Any state) H H X X X X X X + -- Power down mode Exit (Device is powered down) H L H H X X X X + + constant CMD_INHIBIT : std_logic_vector(4 downto 0) := "11111"; + constant CMD_NOP : std_logic_vector(4 downto 0) := "10111"; + constant CMD_ACTIVE : std_logic_vector(4 downto 0) := "10011"; + constant CMD_READ : std_logic_vector(4 downto 0) := "10101"; + constant CMD_WRITE : std_logic_vector(4 downto 0) := "10100"; + constant CMD_BURST_TERMINATE : std_logic_vector(4 downto 0) := "10110"; + constant CMD_PRECHARGE : std_logic_vector(4 downto 0) := "10010"; + constant CMD_AUTO_REFRESH : std_logic_vector(4 downto 0) := "10001"; + constant CMD_LOAD_MODE : std_logic_vector(4 downto 0) := "10000"; + constant CMD_SELF_REFRESH_START : std_logic_vector(4 downto 0) := "00001"; + constant CMD_SELF_REFRESH_END : std_logic_vector(4 downto 0) := "10110"; + constant CMD_CLOCK_SUSPEND : std_logic_vector(4 downto 0) := "00000"; + constant CMD_CLOCK_RESTORE : std_logic_vector(4 downto 0) := "10000"; + constant CMD_POWER_DOWN : std_logic_vector(4 downto 0) := "01000"; + constant CMD_POWER_RESTORE : std_logic_vector(4 downto 0) := "01100"; + + -- Load Mode Register setting for a standard SDRAM. + -- + -- xx:10 = Reserved : + -- 9 = Write Burst Mode : 0 = Programmed Burst Length, 1 = Single Location Access + -- 8:7 = Operating Mode : 00 = Standard Operation, all other values reserved. + -- 6:4 = CAS Latency : 010 = 2, 011 = 3, all other values reserved. + -- 3 = Burst Type : 0 = Sequential, 1 = Interleaved. + -- 2:0 = Burst Length : When 000 = 1, 001 = 2, 010 = 4, 011 = 8, all others reserved except 111 when BT = 0 sets full page access. + -- | A12-A10 | A9  A8-A7 | A6 A5 A4 | A3  A2 A1 A0 | + -- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len| + constant WRITE_BURST_MODE : std_logic := '1'; + constant OP_MODE : std_logic_vector(1 downto 0) := "00"; + constant CAS_LATENCY : std_logic_vector(2 downto 0) := "011"; + constant BURST_TYPE : std_logic := '0'; + constant BURST_LENGTH : std_logic_vector(2 downto 0) := "000"; + constant MODE : std_logic_vector(SDRAM_ROW_BITS-1 downto 0) := std_logic_vector(to_unsigned(to_integer(unsigned("00" & WRITE_BURST_MODE & OP_MODE & CAS_LATENCY & BURST_TYPE & BURST_LENGTH)), SDRAM_ROW_BITS)); + + -- FSM Cycle States governed in units of time, the state changes location according to the configurable parameters to ensure correct actuation at the correct time. + -- + constant CYCLE_PRECHARGE : integer := 0; -- ~0 + constant CYCLE_RAS_START : integer := clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ); -- ~3 + constant CYCLE_CAS_START : integer := CYCLE_RAS_START + clockTicks(SDRAM_tRCD, SDRAM_CLK_FREQ); -- ~3 + tRCD + constant CYCLE_CAS_END : integer := CYCLE_CAS_START + 1; -- ~4 + tRCD + constant CYCLE_READ_START : integer := CYCLE_CAS_START + to_integer(unsigned(CAS_LATENCY)) + 1; -- ~3 + tRCD + CAS_LATENCY + constant CYCLE_READ_END : integer := CYCLE_READ_START + 1; -- ~4 + tRCD + CAS_LATENCY + constant CYCLE_END : integer := CYCLE_READ_END + 1; -- ~9 + tRCD + CAS_LATENCY + constant CYCLE_RFSH_START : integer := clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ); -- ~tRP + constant CYCLE_RFSH_END : integer := CYCLE_RFSH_START + clockTicks(SDRAM_tRFC, SDRAM_CLK_FREQ) + clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ) + 1; -- ~tRP (start) + tRFC (min autorefresh time) + tRP (end) in clock ticks. + + -- Period in clock cycles between SDRAM refresh cycles. This equates to tREF / SDRAM_ROWS to evenly divide the time, then subtract the length of the refresh period as this is + -- the time it takes when a refresh starts until completion. + constant REFRESH_PERIOD : integer := (((SDRAM_tREF * SDRAM_CLK_FREQ ) / SDRAM_ROWS) - (SDRAM_tRFC * 1000)) / 1000; + + -- Array of row addresses, one per bank, to indicate the row in use per bank. + type BankArray is array(natural range 0 to SDRAM_BANKS-1) of std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + + -- SDRAM domain signals. + signal sdBusy : std_logic; + signal sdCycle : integer range 0 to 31; + signal sdDataOut : std_logic_vector(WORD_32BIT_RANGE); + signal sdDone : std_logic; + shared variable sdCmd : std_logic_vector(4 downto 0); + signal sdRefreshCount : unsigned(11 downto 0); + signal sdAutoRefresh : std_logic; + signal sdResetTimer : unsigned(WORD_8BIT_RANGE); + signal sdInResetCounter : unsigned(WORD_8BIT_RANGE); + signal sdIsReady : std_logic; + signal sdActiveRow : BankArray; + signal sdActiveBank : std_logic_vector(1 downto 0); + + -- CPU domain signals. + signal cpuBusy : std_logic; + signal cpuDQM : std_logic_vector(3 downto 0); + signal cpuDoneLast : std_logic; + signal cpuBank : natural range 0 to SDRAM_BANKS-1; + signal cpuRow : std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + signal cpuCol : std_logic_vector(SDRAM_COLUMN_BITS-1 downto 0); + signal cpuDataIn : std_logic_vector(WORD_32BIT_RANGE); + signal cpuIsWriting : std_logic; + signal cpuLastEN : std_logic; + +begin + + -- Main FSM for SDRAM control and refresh. + process(ALL) + begin + + if (SDRAM_RST = '1') then + sdResetTimer <= (others => '0'); -- 0 upto 255 + sdInResetCounter <= (others => '1'); -- 255 downto 0 + sdAutoRefresh <= '0'; + sdRefreshCount <= (others => '0'); + sdActiveBank <= (others => '0'); + sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0')); + sdIsReady <= '0'; + sdCmd := CMD_AUTO_REFRESH; + SDRAM_DQM <= (others => '1'); + sdCycle <= 0; + sdDone <= '0'; + + elsif rising_edge(SDRAM_CLK) then + + -- Tri-state control of the SDRAM databus, when reading, the output drivers are disabled. + if (cpuIsWriting = '0') then + SDRAM_DQ <= (others => 'Z'); + end if; + + -- If no specific command given the default is NOP. + sdCmd := CMD_NOP; + + -- Initialisation on power up or reset. The SDRAM must be given at least 200uS to initialise and a fixed setup pattern applied. + if (sdIsReady = '0') then + sdResetTimer <= sdResetTimer + 1; + + -- 1uS timer. + if (sdResetTimer = SDRAM_CLK_FREQ/1000000) then + sdResetTimer <= (others => '0'); + sdInResetCounter <= sdInResetCounter - 1; + end if; + + -- Every 1uS check for the next init action. + if (sdResetTimer = 0) then + + -- 200uS wait, no action as the SDRAM starts up. + -- ie. 255 downto 55 + + -- Precharge all banks + if(sdInResetCounter = 55) then + sdCmd := CMD_PRECHARGE; + SDRAM_ADDR(10) <= '1'; + end if; + + -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after + -- the other. + if(sdInResetCounter >= 40 and sdInResetCounter <= 48) then + sdCmd := CMD_AUTO_REFRESH; + end if; + + -- Load the Mode register with our parameters. + if(sdInResetCounter = 39) then + sdCmd := CMD_LOAD_MODE; + SDRAM_ADDR <= MODE; + end if; + + -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after + -- the other. + if(sdInResetCounter >= 30 and sdInResetCounter <= 38) then + sdCmd := CMD_AUTO_REFRESH; + end if; + + -- SDRAM ready. + if(sdInResetCounter = 20) then + sdIsReady <= '1'; + end if; + end if; + + else + + -- Counter to time periods between autorefresh. + sdRefreshCount <= sdRefreshCount + 1; + + -- This mechanism is used to reduce the possibility of metastability issues due to differing clocks. + -- We only act after both Busy signals are high, thus one SDRAM clock after cpuBusy goes high. + sdBusy <= cpuBusy; + + -- If the SDRAM has completed its request, reset the done indicator as it is only 1 cycle wide. + -- if sdDone = '1' then + -- sdDone <= '0'; + -- end if; + + -- Auto refresh. On timeout it kicks in so that ROWS auto refreshes are + -- issued in a tRFC period. Other bus operations are stalled during this period. + if (sdRefreshCount > REFRESH_PERIOD and sdCycle = 0) then + sdAutoRefresh <= '1'; + sdRefreshCount <= (others => '0'); + sdCmd := CMD_PRECHARGE; + SDRAM_ADDR(10) <= '1'; + sdActiveBank <= (others => '0'); + sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0')); + + -- In auto refresh period. + elsif (sdAutoRefresh = '1') then + + -- while the cycle is active count. + sdCycle <= sdCycle + 1; + case (sdCycle) is + when CYCLE_RFSH_START => + sdCmd := CMD_AUTO_REFRESH; + + when CYCLE_RFSH_END => + -- reset the count. + sdAutoRefresh <= '0'; + sdCycle <= 0; + + when others => + end case; + + elsif (((cpuBusy = '1' and sdBusy = '1') and sdCycle = 0) or sdCycle /= 0) then + + -- while the cycle is active count. + sdCycle <= sdCycle + 1; + case (sdCycle) is + + when CYCLE_PRECHARGE => + -- If the bank is not open then no need to precharge, move onto RAS. + if (sdActiveBank(cpuBank) = '0') then + sdCycle <= CYCLE_RAS_START; + + -- If the requested row is already active, go to CAS for immediate access to this row. + elsif (sdActiveRow(cpuBank) = cpuRow) then + sdCycle <= CYCLE_CAS_START; + + -- Otherwise we close out the open bank by issuing a PRECHARGE. + else + sdCmd := CMD_PRECHARGE; + SDRAM_ADDR(10) <= '0'; + SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); + sdActiveBank(cpuBank) <= '0'; -- Store flag to indicate which bank is being made active. + end if; + + -- Open the requested row. + when CYCLE_RAS_START => + sdCmd := CMD_ACTIVE; + SDRAM_ADDR <= cpuRow; -- Addr presented to SDRAM as row address. + SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Addr presented to SDRAM as bank select. + sdActiveRow(cpuBank) <= cpuRow; -- Store number of row being made active + sdActiveBank(cpuBank) <= '1'; -- Store flag to indicate which bank is being made active. + + -- CAS start, for 32 bit chips, only 1 CAS cycle is needed, for 16bit chips we need 2 to read/write 2x16bit words. + when CYCLE_CAS_START => + + -- If writing, setup for a write with preset mask. + if (cpuIsWriting = '1') then + + if SDRAM_DATAWIDTH = 32 then + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 2) & '0' & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing 32bit data with no auto precharge + SDRAM_DQ <= cpuDataIn; -- Assign corresponding data to the SDRAM databus. + SDRAM_DQM <= not cpuDQM(3 downto 0); + sdCycle <= CYCLE_END; + sdDone <= '1'; + + elsif SDRAM_DATAWIDTH = 16 then + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge + SDRAM_DQ <= cpuDataIn((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH); -- Assign corresponding data to the SDRAM databus. + SDRAM_DQM <= not cpuDQM(3 downto 2); + else + report "SDRAM datawidth parameter invalid, should be 16 or 32!" severity error; + end if; + sdCmd := CMD_WRITE; + + else + -- Setup for a read. + sdCmd := CMD_READ; + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge + SDRAM_DQM <= "00"; -- For reads dont mask the data output. + end if; + + when CYCLE_CAS_END => + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '1')), SDRAM_ROW_BITS)); -- CAS address = Next address accessing second 16bit location within the 32bit external alignment with no auto precharge + + -- When writing, setup for a write with preset mask with the correct word. + if (cpuIsWriting = '1') then + SDRAM_DQM <= not cpuDQM(1 downto 0); + SDRAM_DQ <= cpuDataIn(SDRAM_DATAWIDTH-1 downto 0); + sdDone <= '1'; + sdCycle <= CYCLE_END; + sdCmd := CMD_WRITE; + else + -- Setup for a read, change to write if flag set. + sdCmd := CMD_READ; + SDRAM_DQM <= "00"; -- For reads dont mask the data output. + end if; + + -- Data is available CAS Latency clocks after the read request. For 32bit chips, only 1 cycle is needed, for 16bit we need 2 read cycles of + -- 16 bits each. + when CYCLE_READ_START => + + if SDRAM_DATAWIDTH = 32 then + --sdDataOut <= SDRAM_DQ; + DATA_OUT <= SDRAM_DQ; + sdCycle <= CYCLE_END; + sdDone <= '1'; + + elsif SDRAM_DATAWIDTH = 16 then + -- sdDataOut((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH) <= SDRAM_DQ; + DATA_OUT((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH) <= SDRAM_DQ; + else + report "SDRAM datawidth parameter invalid, should be 16 or 32!" severity error; + end if; + + -- Second and final read cycle for 16bit SDRAM chips to create a 32bit word. + when CYCLE_READ_END => + --sdDataOut(SDRAM_DATAWIDTH-1 downto 0) <= SDRAM_DQ; + DATA_OUT(SDRAM_DATAWIDTH-1 downto 0) <= SDRAM_DQ; + sdDone <= '1'; + + when CYCLE_END => + sdDone <= '0'; + sdCycle <= 0; + + -- Other states are wait states, waiting for the correct time slot for SDRAM access. + when others => + end case; + else + sdCycle <= 0; + end if; + end if; + + -- drive control signals according to current command + SDRAM_CKE <= sdCmd(4); + SDRAM_CS_n <= sdCmd(3); + SDRAM_RAS_n <= sdCmd(2); + SDRAM_CAS_n <= sdCmd(1); + SDRAM_WE_n <= sdCmd(0); + end if; + + end process; + + + -- CPU/BUS side logic. When the CPU initiates a transaction, capture the signals and the captured values are used within the SDRAM domain. This is to prevent + -- any changes CPU side or differing signal lengths due to CPU architecture or clock being propogated into the SDRAM domain. The CPU only needs to know + -- when the transation is complete and data read. + -- + process(ALL) + begin + if (RESET = '1') then + cpuDoneLast <= '0'; + cpuBusy <= '0'; + cpuBank <= 0; + cpuRow <= (others => '0'); + cpuCol <= (others => '0'); + cpuDQM <= (others => '1'); + cpuLastEN <= '0'; + + -- Wait for the SDRAM to become ready by holding the CPU in a wait state. + elsif sdIsReady = '0' then + cpuBusy <= '1'; + + elsif rising_edge(CLK) then + + -- Preserve current enable state to detect activation. + cpuLastEN <= (RDEN or WREN) and CS; + + -- Detect a Chip Select state change signalling access. + if cpuLastEN = '0' and ((RDEN = '1' or WREN = '1') and CS = '1') then + cpuBusy <= '1'; + cpuIsWriting <= WREN; + cpuBank <= to_integer(unsigned(ADDR(SDRAM_ADDR_BITS-1 downto SDRAM_ARRAY_BITS+1))); + cpuRow <= std_logic_vector(to_unsigned(to_integer(unsigned(ADDR(SDRAM_ARRAY_BITS downto SDRAM_COLUMN_BITS+1))), SDRAM_ROW_BITS)); + cpuCol <= ADDR(SDRAM_COLUMN_BITS downto 2) & '0'; + + -- Preset the write selects according to the CPU signals. Let Quartus optimize as easier to read seeing all mask values. + if(WRITE_BYTE = '1') then + case ADDR(1 downto 0) is + when "00" => cpuDQM <= "1000"; + cpuDataIn <= DATA_IN(WORD_8BIT_RANGE) & X"000000"; + when "01" => cpuDQM <= "0100"; + cpuDataIn <= X"00" & DATA_IN(WORD_8BIT_RANGE) & X"0000"; + when "10" => cpuDQM <= "0010"; + cpuDataIn <= X"0000" & DATA_IN(WORD_8BIT_RANGE) & X"00"; + when "11" => cpuDQM <= "0001"; + cpuDataIn <= X"000000" & DATA_IN(WORD_8BIT_RANGE); + when others => + end case; + + elsif(WRITE_HWORD = '1') then + + case ADDR(1) is + when '0' => cpuDQM <= "1100"; + cpuDataIn <= DATA_IN(WORD_16BIT_RANGE) & X"0000"; + when '1' => cpuDQM <= "0011"; + cpuDataIn <= X"0000" & DATA_IN(WORD_16BIT_RANGE); + end case; + + else + -- Reads are always 32bit wide and if no part word signal is asserted, writes are 32bit. + cpuDataIn <= DATA_IN(WORD_32BIT_RANGE); + cpuDQM <= "1111"; + end if; + end if; + + -- Note SDRAM activity via a previous/last signal. + cpuDoneLast <= sdDone; + + -- A change in the Done signal indicates the end of the SDRAM request so read the data (read request) and release the CPU. + -- if (cpuDoneLast = '0' and sdDone = '1') then + -- DATA_OUT <= sdDataOut; + -- end if; + if (cpuDoneLast = '0' and sdDone = '1') or CS = '0' or (RDEN = '0' and WREN = '0') then + -- DATA_OUT <= sdDataOut; + cpuBusy <= '0'; + cpuIsWriting <= '0'; + end if; + + end if; + end process; + + -- System bus control signals. + BUSY <= '1' when (cpuLastEN = '0' and (RDEN = '1' or WREN = '1') and CS = '1') else cpuBusy; + --BUSY <= cpuBusy; + SDRAM_READY <= sdIsReady; + +end Structure; diff --git a/zpu/devices/sysbus/SDRAM/sdram_cached.vhd b/zpu/devices/sysbus/SDRAM/sdram_cached.vhd new file mode 100644 index 0000000..83fb1fa --- /dev/null +++ b/zpu/devices/sysbus/SDRAM/sdram_cached.vhd @@ -0,0 +1,737 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: sdram_cached.vhd +-- Created: September 2019 +-- Author: Philip Smart +-- Description: A configurable cached sdram controller for use with the ZPU EVO Processor and SoC. +-- The module is instantiated with the parameters to describe the underlying SDRAM chip +-- and in theory should work with most 16/32 bit SDRAM chips if they adhere to the SDRAM +-- standard. +-- Credits: Stephen J. Leary 2013-2014 - Basic sdram cycle structure of this module was based on +-- the verilog MT48LC16M16 chip controller written by Stephen. +-- Copyright: (c) 2019-2020 Philip Smart +-- +-- History: September 2019 - Initial module translation to VHDL based on Stephen J. Leary's Verilog +-- source code. +-- November 2019 - Adapted for the system bus for use when no Wishbone interface is +-- instantiated in the ZPU Evo. +-- December 2019 - Extensive changes, metability stability, autorefresh to ACTIVE timing +-- and parameterisation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_soc_pkg.all; +use work.zpu_pkg.all; + +entity SDRAM is + generic ( + MAX_DATACACHE_BITS : integer := 4; -- Maximum size in addr bits of 32bit datacache for burst transactions. + SDRAM_ROWS : integer := 4096; -- Number of Rows in the SDRAM. + SDRAM_COLUMNS : integer := 256; -- Number of Columns in an SDRAM page (ie. 1 row). + SDRAM_BANKS : integer := 4; -- Number of banks in the SDRAM. + SDRAM_DATAWIDTH : integer := 16; -- Data width of SDRAM chip (16, 32). + SDRAM_CLK_FREQ : integer := 100000000; -- Frequency of the SDRAM clock in Hertz. + SDRAM_tRCD : integer := 20; -- tRCD - RAS to CAS minimum period (in ns). + SDRAM_tRP : integer := 20; -- tRP - Precharge delay, min time for a precharge command to complete (in ns). + SDRAM_tRFC : integer := 70; -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns + SDRAM_tREF : integer := 64 -- tREF - period of time a complete refresh of all rows is made within (in ms). + ); + port ( + -- SDRAM Interface + SDRAM_CLK : in std_logic; -- SDRAM is accessed at given clock, frequency specified in RAM_CLK. + SDRAM_RST : in std_logic; -- Reset the sdram controller. + SDRAM_CKE : out std_logic; -- Clock enable. + SDRAM_DQ : inout std_logic_vector(SDRAM_DATAWIDTH-1 downto 0); -- Bidirectional data bus + SDRAM_ADDR : out std_logic_vector(log2ceil(SDRAM_ROWS) - 1 downto 0); -- Multiplexed address bus + SDRAM_DQM : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of byte masks dependent on number of banks. + SDRAM_BA : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of banks in SDRAM + SDRAM_CS_n : out std_logic; -- Single chip select + SDRAM_WE_n : out std_logic; -- Write enable + SDRAM_RAS_n : out std_logic; -- Row address select + SDRAM_CAS_n : out std_logic; -- Columns address select + SDRAM_READY : out std_logic; -- SD ready. + + -- CPU Interface + CLK : in std_logic; -- System master clock + RESET : in std_logic; -- High active sync reset + ADDR : in std_logic_vector(log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS) downto 0); + DATA_IN : in std_logic_vector(WORD_32BIT_RANGE); -- Write data + DATA_OUT : out std_logic_vector(WORD_32BIT_RANGE); -- Read data + WRITE_BYTE : in std_logic; -- Write a single byte as specified in A1:A0 + WRITE_HWORD : in std_logic; -- Write a 16bit word as specified in A1 + CS : in std_logic; -- Chip Select. + WREN : in std_logic; -- Write enable. + RDEN : in std_logic; -- Read enable. + BUSY : out std_logic -- Memory is busy, hold CPU. + ); +end SDRAM; + +architecture Structure of SDRAM is + + -- Constants to define the structure of the SDRAM in bits for provisioning of signals. + constant SDRAM_ROW_BITS : integer := log2ceil(SDRAM_ROWS); + constant SDRAM_COLUMN_BITS : integer := log2ceil(SDRAM_COLUMNS); + constant SDRAM_ARRAY_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS); + constant SDRAM_BANK_BITS : integer := log2ceil(SDRAM_BANKS); + constant SDRAM_ADDR_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS * (SDRAM_DATAWIDTH/8)); + + -- Command table for a standard SDRAM. + -- + -- Name (Function) CKE CS# RAS# CAS# WE# DQM ADDR DQ + -- COMMAND INHIBIT (NOP) H H X X X X X X + -- NO OPERATION (NOP) H L H H H X X X + -- ACTIVE (select bank and activate row) H L L H H X Bank/row X + -- READ (select bank and column, and start READ burst) H L H L H L/H Bank/col X + -- WRITE (select bank and column, and start WRITE burst) H L H L L L/H Bank/col Valid + -- BURST TERMINATE H L H H L X X Active + -- PRECHARGE (Deactivate row in bank or banks) H L L H L X Code X + -- AUTO REFRESH or SELF REFRESH (enter self refresh mode) H L L L H X X X + -- LOAD MODE REGISTER H L L L L X Op-code X + -- Write enable/output enable H X X X X L X Active + -- Write inhibit/output High-Z H X X X X H X High-Z + -- Self Refresh Entry L L L L H X X X + -- Self Refresh Exit (Device is idle) H H X X X X X X + -- Self Refresh Exit (Device is in Self Refresh state) H L H H X X X X + -- Clock suspend mode Entry L X X X X X X X + -- Clock suspend mode Exit H X X X X X X X + -- Power down mode Entry (Device is idle) L H X X X X X X + -- Power down mode Entry (Device is Active) L L H H X X X X + -- Power down mode Exit (Any state) H H X X X X X X + -- Power down mode Exit (Device is powered down) H L H H X X X X + + constant CMD_INHIBIT : std_logic_vector(4 downto 0) := "11111"; + constant CMD_NOP : std_logic_vector(4 downto 0) := "10111"; + constant CMD_ACTIVE : std_logic_vector(4 downto 0) := "10011"; + constant CMD_READ : std_logic_vector(4 downto 0) := "10101"; + constant CMD_WRITE : std_logic_vector(4 downto 0) := "10100"; + constant CMD_BURST_TERMINATE : std_logic_vector(4 downto 0) := "10110"; + constant CMD_PRECHARGE : std_logic_vector(4 downto 0) := "10010"; + constant CMD_AUTO_REFRESH : std_logic_vector(4 downto 0) := "10001"; + constant CMD_LOAD_MODE : std_logic_vector(4 downto 0) := "10000"; + constant CMD_SELF_REFRESH_START : std_logic_vector(4 downto 0) := "00001"; + constant CMD_SELF_REFRESH_END : std_logic_vector(4 downto 0) := "10110"; + constant CMD_CLOCK_SUSPEND : std_logic_vector(4 downto 0) := "00000"; + constant CMD_CLOCK_RESTORE : std_logic_vector(4 downto 0) := "10000"; + constant CMD_POWER_DOWN : std_logic_vector(4 downto 0) := "01000"; + constant CMD_POWER_RESTORE : std_logic_vector(4 downto 0) := "01100"; + + -- Load Mode Register setting for a standard SDRAM. + -- + -- xx:10 = Reserved : + -- 9 = Write Burst Mode : 0 = Programmed Burst Length, 1 = Single Location Access + -- 8:7 = Operating Mode : 00 = Standard Operation, all other values reserved. + -- 6:4 = CAS Latency : 010 = 2, 011 = 3, all other values reserved. + -- 3 = Burst Type : 0 = Sequential, 1 = Interleaved. + -- 2:0 = Burst Length : When 000 = 1, 001 = 2, 010 = 4, 011 = 8, all others reserved except 111 when BT = 0 sets full page access. + -- | A12-A10 | A9  A8-A7 | A6 A5 A4 | A3  A2 A1 A0 | + -- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len| + constant WRITE_BURST_MODE : std_logic := '1'; + constant OP_MODE : std_logic_vector(1 downto 0) := "00"; + constant CAS_LATENCY : std_logic_vector(2 downto 0) := "011"; + constant BURST_TYPE : std_logic := '0'; + constant BURST_LENGTH : std_logic_vector(2 downto 0) := "111"; + constant MODE : std_logic_vector(SDRAM_ROW_BITS-1 downto 0) := std_logic_vector(to_unsigned(to_integer(unsigned("00" & WRITE_BURST_MODE & OP_MODE & CAS_LATENCY & BURST_TYPE & BURST_LENGTH)), SDRAM_ROW_BITS)); + + -- FSM Cycle States governed in units of time, the state changes location according to the configurable parameters to ensure correct actuation at the correct time. + -- + constant CYCLE_PRECHARGE : integer := 0; -- ~0 + constant CYCLE_RAS_START : integer := clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ); -- ~3 + constant CYCLE_CAS_START : integer := CYCLE_RAS_START + clockTicks(SDRAM_tRCD, SDRAM_CLK_FREQ); -- ~3 + tRCD + constant CYCLE_WRITE_END : integer := CYCLE_CAS_START + 1; -- ~4 + tRCD + constant CYCLE_READ_START : integer := CYCLE_CAS_START + to_integer(unsigned(CAS_LATENCY)) + 1; -- ~3 + tRCD + CAS_LATENCY + constant CYCLE_READ_END : integer := CYCLE_READ_START + 1; -- ~4 + tRCD + CAS_LATENCY + constant CYCLE_END : integer := CYCLE_READ_END + 1; -- ~9 + tRCD + CAS_LATENCY + constant CYCLE_RFSH_START : integer := clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ); -- ~tRP + constant CYCLE_RFSH_END : integer := CYCLE_RFSH_START + clockTicks(SDRAM_tRFC, SDRAM_CLK_FREQ) + clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ) + 1; -- ~tRP (start) + tRFC (min autorefresh time) + tRP (end) in clock ticks. + + -- Period in clock cycles between SDRAM refresh cycles. This equates to tREF / SDRAM_ROWS to evenly divide the time, then subtract the length of the refresh period as this is + -- the time it takes when a refresh starts until completion. + constant REFRESH_PERIOD : integer := (((SDRAM_tREF * SDRAM_CLK_FREQ ) / SDRAM_ROWS) - (SDRAM_tRFC * 1000)) / 1000; + + -- Array of row addresses, one per bank, to indicate the row in use per bank. + type BankArray is array(natural range 0 to SDRAM_BANKS-1) of std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + type BankCacheArray is array(natural range 0 to SDRAM_BANKS-1) of std_logic_vector(((SDRAM_ROW_BITS-1)+SDRAM_BANK_BITS) downto 0); + + -- SDRAM domain signals. + signal sdBusy : std_logic; + signal sdCycle : integer range 0 to 31; + signal sdDone : std_logic; + shared variable sdCmd : std_logic_vector(4 downto 0); + signal sdRefreshCount : unsigned(11 downto 0); + signal sdAutoRefresh : std_logic; + signal sdResetTimer : unsigned(WORD_8BIT_RANGE); + signal sdInResetCounter : unsigned(WORD_8BIT_RANGE); + signal sdIsReady : std_logic; + signal sdActiveRow : BankArray; + signal sdActiveBank : std_logic_vector(1 downto 0); + signal sdWriteColumnAddr : unsigned(SDRAM_COLUMN_BITS-1 downto 0); -- Address at byte level as bit 0 is used as part of the fifo write enable. + signal sdWriteCnt : integer range 0 to SDRAM_COLUMNS-1; + + -- CPU domain signals. + signal cpuBusy : std_logic; + signal cpuDQM : std_logic_vector(3 downto 0); + signal cpuBank : natural range 0 to SDRAM_BANKS-1; + signal cpuRow : std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + signal cpuCol : std_logic_vector(SDRAM_COLUMN_BITS-1 downto 0); + signal cpuDataOut : std_logic_vector(WORD_32BIT_RANGE); + signal cpuDataIn : std_logic_vector(WORD_32BIT_RANGE); + signal cpuDoneLast : std_logic; + signal cpuIsWriting : std_logic; + signal cpuLastEN : std_logic; + signal cpuCachedBank : std_logic_vector(SDRAM_BANK_BITS-1 downto 0); + signal cpuCachedRow : BankCacheArray; + + -- Infer a BRAM array for 4 banks of 16bit words. 32bit is created by 2 arrays. + type ramArray is array(natural range 0 to ((SDRAM_COLUMNS/2)*4)-1) of std_logic_vector(WORD_8BIT_RANGE); + + -- Declare the BRAM arrays for 32bit as a set of 4 x 8bit banks. + shared variable fifoCache_3 : ramArray := + ( + others => X"00" + ); + shared variable fifoCache_2 : ramArray := + ( + others => X"00" + ); + shared variable fifoCache_1 : ramArray := + ( + others => X"00" + ); + shared variable fifoCache_0 : ramArray := + ( + others => X"00" + ); + + -- Fifo control signals. + signal fifoDataOutHi : std_logic_vector(WORD_16BIT_RANGE); + signal fifoDataOutLo : std_logic_vector(WORD_16BIT_RANGE); + signal fifoDataInHi : std_logic_vector(WORD_16BIT_RANGE); + signal fifoDataInLo : std_logic_vector(WORD_16BIT_RANGE); + signal fifoSdWREN_1 : std_logic; + signal fifoSdWREN_0 : std_logic; + signal fifoCPUWREN_3 : std_logic; + signal fifoCPUWREN_2 : std_logic; + signal fifoCPUWREN_1 : std_logic; + signal fifoCPUWREN_0 : std_logic; +begin + + -- Main FSM for SDRAM control and refresh. + process(ALL) + begin + + if (SDRAM_RST = '1') then + sdResetTimer <= (others => '0'); -- 0 upto 127 + sdInResetCounter <= (others => '1'); -- 255 downto 0 + sdAutoRefresh <= '0'; + sdRefreshCount <= (others => '0'); + sdActiveBank <= (others => '0'); + sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0')); + sdIsReady <= '0'; + sdCmd := CMD_AUTO_REFRESH; + SDRAM_DQM <= (others => '1'); + sdCycle <= 0; + sdDone <= '0'; + fifoSdWREN_0 <= '0'; + fifoSdWREN_1 <= '0'; + sdWriteColumnAddr <= (others => '0'); + + elsif rising_edge(SDRAM_CLK) then + + -- Write Enables are only 1 clock wide, clear on each cycle. + fifoSdWREN_1 <= '0'; + fifoSdWREN_0 <= '0'; + + -- Tri-state control, set the SDRAM databus to tri-state if we are not in write mode. + if (cpuIsWriting = '0') then + SDRAM_DQ <= (others => 'Z'); + end if; + + -- If no specific command given the default is NOP. + sdCmd := CMD_NOP; + + -- Initialisation on power up or reset. The SDRAM must be given at least 200uS to initialise and a fixed setup pattern applied. + if (sdIsReady = '0') then + sdResetTimer <= sdResetTimer + 1; + + -- 1uS timer. + if (sdResetTimer = SDRAM_CLK_FREQ/1000000) then + sdResetTimer <= (others => '0'); + sdInResetCounter <= sdInResetCounter - 1; + end if; + + -- Every 1uS check for the next init action. + if (sdResetTimer = 0) then + + -- 200uS wait, no action as the SDRAM starts up. + -- ie. 255 downto 55 + + -- Precharge all banks + if(sdInResetCounter = 55) then + sdCmd := CMD_PRECHARGE; + SDRAM_ADDR(10) <= '1'; + end if; + + -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after + -- the other. + if(sdInResetCounter >= 40 and sdInResetCounter <= 48) then + sdCmd := CMD_AUTO_REFRESH; + end if; + + -- Load the Mode register with our parameters. + if(sdInResetCounter = 39) then + sdCmd := CMD_LOAD_MODE; + SDRAM_ADDR <= MODE; + end if; + + -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after + -- the other. + if(sdInResetCounter >= 30 and sdInResetCounter <= 38) then + sdCmd := CMD_AUTO_REFRESH; + end if; + + -- SDRAM ready. + if(sdInResetCounter = 20) then + sdIsReady <= '1'; + end if; + end if; + + else + + -- Counter to time periods between autorefresh. + sdRefreshCount <= sdRefreshCount + 1; + + -- This mechanism is used to reduce the possibility of metastability issues due to differing clocks. + -- We only act after both Busy signals are high, thus one SDRAM clock after cpuBusy goes high. + sdBusy <= cpuBusy; + + -- Auto refresh. On timeout it kicks in so that ROWS auto refreshes are + -- issued in a tRFC period. Other bus operations are stalled during this period. + if (sdRefreshCount > REFRESH_PERIOD and sdCycle = 0) then + sdAutoRefresh <= '1'; + sdRefreshCount <= (others => '0'); + sdCmd := CMD_PRECHARGE; + SDRAM_ADDR(10) <= '1'; + sdActiveBank <= (others => '0'); + sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0')); + + -- In auto refresh period. + elsif (sdAutoRefresh = '1') then + + -- while the cycle is active count. + sdCycle <= sdCycle + 1; + case (sdCycle) is + when CYCLE_RFSH_START => + sdCmd := CMD_AUTO_REFRESH; + + when CYCLE_RFSH_END => + -- reset the count. + sdAutoRefresh <= '0'; + sdCycle <= 0; + + when others => + end case; + + elsif ((cpuBusy = '1' and sdCycle = 0) or sdCycle /= 0) then -- or (sdCycle = 0 and CS = '1')) then + + -- while the cycle is active count. + sdCycle <= sdCycle + 1; + case (sdCycle) is + + when CYCLE_PRECHARGE => + -- If the bank is not open then no need to precharge, move onto RAS. + if (sdActiveBank(cpuBank) = '0') then + sdCycle <= CYCLE_RAS_START; + + -- If the requested row is already active, go to CAS for immediate access to this row. + elsif (sdActiveRow(cpuBank) = cpuRow) then + sdCycle <= CYCLE_CAS_START; + + -- Otherwise we close out the open bank by issuing a PRECHARGE. + else + sdCmd := CMD_PRECHARGE; + SDRAM_ADDR(10) <= '0'; + SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); + sdActiveBank(cpuBank) <= '0'; -- Store flag to indicate which bank is being made active. + end if; + + -- Open the requested row. + when CYCLE_RAS_START => + sdCmd := CMD_ACTIVE; + SDRAM_ADDR <= cpuRow; -- Addr presented to SDRAM as row address. + SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Addr presented to SDRAM as bank select. + sdActiveRow(cpuBank) <= cpuRow; -- Store number of row being made active + sdActiveBank(cpuBank) <= '1'; -- Store flag to indicate which bank is being made active. + + -- CAS start, for 32 bit chips, only 1 CAS cycle is needed, for 16bit chips we need 2 to read/write 2x16bit words. + when CYCLE_CAS_START => + -- If writing, setup for a write with preset mask. + if (cpuIsWriting = '1') then + sdCmd := CMD_WRITE; + if SDRAM_DATAWIDTH = 32 then + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 2) & '0' & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing 32bit data with no auto precharge + SDRAM_DQ <= cpuDataIn; -- Assign corresponding data to the SDRAM databus. + SDRAM_DQM <= not cpuDQM(3 downto 0); + sdDone <= '1'; + sdCycle <= CYCLE_END; + + -- A fake statement used to convince Quartus Prime to infer block ram for the fifo and not use registers. + fifoDataInHi <= fifoDataOutHi; + fifoDataInLo <= fifoDataOutLo; + + elsif SDRAM_DATAWIDTH = 16 then + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge + SDRAM_DQ <= cpuDataIn((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH); -- Assign corresponding data to the SDRAM databus. + SDRAM_DQM <= not cpuDQM(3 downto 2); + + -- A fake statement used to convince Quartus Prime to infer block ram for the fifo and not use registers. + fifoDataInHi <= fifoDataOutHi; + else + report "SDRAM datawidth parameter invalid, should be 16 or 32!" severity error; + end if; + + else + -- Setup for a read. + sdCmd := CMD_READ; + SDRAM_ADDR <= (others => '0'); + SDRAM_DQM <= "00"; -- For reads dont mask the data output. + sdWriteCnt <= SDRAM_COLUMNS-1; + sdWriteColumnAddr <= (others => '1'); + end if; + + -- For writes, this state writes out the second word of a 32bit word if we have a 16bit wide SDRAM chip. + -- + when CYCLE_WRITE_END => + -- When writing, setup for a write with preset mask with the correct word. + if (cpuIsWriting = '1') then + SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '1')), SDRAM_ROW_BITS)); -- CAS address = Next address accessing second 16bit location within the 32bit external alignment with no auto precharge + sdCmd := CMD_WRITE; + SDRAM_DQM <= not cpuDQM(1 downto 0); + SDRAM_DQ <= cpuDataIn(SDRAM_DATAWIDTH-1 downto 0); + sdDone <= '1'; + sdCycle <= CYCLE_END; + + -- A fake statement used to convince Quartus Prime to infer block ram for the fifo and not use registers. + fifoDataInLo <= fifoDataOutLo; + end if; + + -- Data is available after CAS Latency (2 or 3) clocks after the read request. + -- The data is read as a full page burst, 1 clock per word. + when CYCLE_READ_START => + + if SDRAM_DATAWIDTH = 32 then + fifoSdWREN_1 <= '1'; + fifoSdWREN_0 <= '1'; + sdWriteCnt <= sdWriteCnt - 2; + sdWriteColumnAddr <= sdWriteColumnAddr + 2; + fifoDataInHi <= SDRAM_DQ(WORD_UPPER_16BIT_RANGE); + fifoDataInLo <= SDRAM_DQ(WORD_LOWER_16BIT_RANGE); + + if sdWriteCnt > 1 then + sdCycle <= CYCLE_READ_START; + end if; + + elsif SDRAM_DATAWIDTH = 16 then + if fifoSdWREN_1 = '0' then + fifoSdWREN_1 <= '1'; + fifoDataInHi <= SDRAM_DQ; + else + fifoSdWREN_0 <= '1'; + fifoDataInLo <= SDRAM_DQ; + end if; + sdWriteCnt <= sdWriteCnt - 1; + sdWriteColumnAddr <= sdWriteColumnAddr + 1; + + if sdWriteCnt > 0 then + sdCycle <= CYCLE_READ_START; + end if; + + else + report "SDRAM datawidth parameter invalid, should be 16 or 32!" severity error; + end if; + + when CYCLE_READ_END => + sdDone <= '1'; + + when CYCLE_END => + sdCycle <= 0; + sdDone <= '0'; + + -- Other states are wait states, waiting for the correct time slot for SDRAM access. + when others => + end case; + else + sdCycle <= 0; + end if; + end if; + + -- drive control signals according to current command + SDRAM_CKE <= sdCmd(4); + SDRAM_CS_n <= sdCmd(3); + SDRAM_RAS_n <= sdCmd(2); + SDRAM_CAS_n <= sdCmd(1); + SDRAM_WE_n <= sdCmd(0); + end if; + end process; + + + -- CPU/BUS side logic. When the CPU initiates a transaction, capture the signals and the captured values are used within the SDRAM domain. This is to prevent + -- any changes CPU side or differing signal lengths due to CPU architecture or clock being propogated into the SDRAM domain. The CPU only needs to know + -- when the transation is complete and data read. + -- + process(ALL) + variable bank : std_logic_vector(1 downto 0); + variable row : std_logic_vector(SDRAM_ROW_BITS-1 downto 0); + variable writeThru : std_logic; + begin + + -- Setup the bank and row as variables to make code reading easier. + bank := ADDR(SDRAM_ADDR_BITS-1) & ADDR((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) downto (SDRAM_COLUMN_BITS+1)); + row := ADDR(SDRAM_ADDR_BITS-2 downto (SDRAM_COLUMN_BITS+SDRAM_BANK_BITS)); + + -- For write operations, if the cached page row for the current bank is the same as the row given by the cpu then we write to both the SDRAM and to the cache. + if cpuCachedBank(to_integer(unsigned(bank))) = '1' and cpuCachedRow(to_integer(unsigned(bank))) = ADDR(SDRAM_ADDR_BITS-1) & ADDR((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) downto (SDRAM_COLUMN_BITS+1)) & row then + writeThru := '1'; + else + writeThru := '0'; + end if; + + -- Setup signals to initial state, critical they start at the right values. + if (RESET = '1') then + cpuDoneLast <= '0'; + cpuBusy <= '0'; + cpuBank <= 0; + cpuRow <= (others => '0'); + cpuCol <= (others => '0'); + cpuDQM <= (others => '1'); + cpuLastEN <= '0'; + cpuCachedBank <= (others => '0'); + cpuCachedRow <= ( others => (others => '0') ); + fifoCPUWREN_3 <= '0'; + fifoCPUWREN_2 <= '0'; + fifoCPUWREN_1 <= '0'; + fifoCPUWREN_0 <= '0'; + + -- Wait for the SDRAM to become ready by holding the CPU in a wait state. + elsif sdIsReady = '0' then + cpuBusy <= '1'; + + elsif rising_edge(CLK) then + + -- CPU Cache writes are only 1 cycle wide, so clear any asserted write. + fifoCPUWREN_3 <= '0'; + fifoCPUWREN_2 <= '0'; + fifoCPUWREN_1 <= '0'; + fifoCPUWREN_0 <= '0'; + + -- Preserve current enable state to detect activation. + cpuLastEN <= (RDEN or WREN) and CS; + + -- Detect a Chip Select state change signalling access. + if cpuLastEN = '0' and (RDEN = '1' or WREN = '1') and CS = '1' then + + -- Organisation of the memory is as follows: + -- + -- Bank: [(SDRAM_ADDR_BITS-1) .. (SDRAM_ADDR_BITS-1)] & [((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) .. (SDRAM_COLUMN_BITS+1)] + -- Row: [(SDRAM_ADDR_BITS-2) .. (SDRAM_COLUMN_BITS+SDRAM_BANK_BITS)] + -- Column: [(SDRAM_COLUMN_BITS downto 2)] + -- The bank is split so that the Bank MSB splits the SDRAM in 2, upper and lower segment, this is because Stack normally resides in the top upper + -- segment and code in the bottom lower segment. The remaining bank bits are split at the page level such that 2 or more pages residing in different + -- banks are contiguous, hoping to gain a little performance benefit through having a wider spread for code caching and stack caching and write thru. + -- + cpuBank <= to_integer(unsigned(bank)); + cpuRow <= row; + cpuCol <= ADDR(SDRAM_COLUMN_BITS downto 2) & '0'; + + -- For write operations, we write direct to memory. If the data is in cache then a write-thru is performed to preserve the cached bank. + if WREN = '1' then + + -- Preset the write selects according to the CPU signals. Let Quartus optimize as easier to read seeing all mask values. + if(WRITE_BYTE = '1') then + case ADDR(1 downto 0) is + when "00" => + cpuDQM <= "1000"; + cpuDataIn <= DATA_IN(WORD_8BIT_RANGE) & X"000000"; + if writeThru = '1' then + fifoCPUWREN_3 <= '1'; + end if; + when "01" => + cpuDQM <= "0100"; + cpuDataIn <= X"00" & DATA_IN(WORD_8BIT_RANGE) & X"0000"; + if writeThru = '1' then + fifoCPUWREN_2 <= '1'; + end if; + when "10" => + cpuDQM <= "0010"; + cpuDataIn <= X"0000" & DATA_IN(WORD_8BIT_RANGE) & X"00"; + if writeThru = '1' then + fifoCPUWREN_1 <= '1'; + end if; + when "11" => + cpuDQM <= "0001"; + cpuDataIn <= X"000000" & DATA_IN(WORD_8BIT_RANGE); + if writeThru = '1' then + fifoCPUWREN_0 <= '1'; + end if; + when others => + end case; + + elsif(WRITE_HWORD = '1') then + + case ADDR(1) is + when '0' => + cpuDQM <= "1100"; + cpuDataIn <= DATA_IN(WORD_16BIT_RANGE) & X"0000"; + if writeThru = '1' then + fifoCPUWREN_3 <= '1'; + fifoCPUWREN_2 <= '1'; + end if; + when '1' => + cpuDQM <= "0011"; + cpuDataIn <= X"0000" & DATA_IN(WORD_16BIT_RANGE); + if writeThru = '1' then + fifoCPUWREN_1 <= '1'; + fifoCPUWREN_0 <= '1'; + end if; + end case; + + else + -- Reads are always 32bit wide and if no part word signal is asserted, writes are 32bit. + cpuDataIn <= DATA_IN(31 downto 0); + cpuDQM <= "1111"; + if writeThru = '1' then + fifoCPUWREN_3 <= '1'; + fifoCPUWREN_2 <= '1'; + fifoCPUWREN_1 <= '1'; + fifoCPUWREN_0 <= '1'; + end if; + end if; + + -- Set the flags, cpuBusy indicates to the SDRAM FSM to perform an operation, it also halts the CPU. + cpuIsWriting <= WREN; + cpuBusy <= '1'; + + -- For reads, if the row is cached then we just fall through to perform a read operation from cache otherwise the + -- SDRAM needs to be instructed to read a page into cache before reading. + -- + elsif cpuCachedBank(to_integer(unsigned(bank))) = '0' or cpuCachedRow(to_integer(unsigned(bank))) /= ADDR(SDRAM_ADDR_BITS-1) & ADDR((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) downto (SDRAM_COLUMN_BITS+1)) & row then + + cpuCachedBank(to_integer(unsigned(bank))) <= '1'; + cpuCachedRow (to_integer(unsigned(bank))) <= ADDR(SDRAM_ADDR_BITS-1) & ADDR((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) downto (SDRAM_COLUMN_BITS+1)) & row; + + -- Set the flags, cpuBusy indicates to the SDRAM FSM to perform an operation, it also halts the CPU. + cpuBusy <= '1'; + end if; + end if; + + -- Note SDRAM activity via a previous/last signal. + cpuDoneLast <= sdDone; + + -- A change in the Done signal then we end the SDRAM request and release the CPU. + --if (cpuDoneLast xor sdDone) = '1' then + if (cpuDoneLast ='0' and sdDone = '1') then + cpuBusy <= '0'; + cpuIsWriting <= '0'; + end if; + end if; + end process; + + -- System bus control signals. + BUSY <= '1' when (cpuLastEN = '0' and (RDEN = '1' or WREN = '1') and CS = '1') else cpuBusy; + SDRAM_READY <= sdIsReady; + + ------------------------------------------------------------------------------------------------------------------------- + -- Inferred Dual Port RAM. + -- + -- The dual port ram is used to buffer a full page within the SDRAM, one buffer for each bank. The addressing is such + -- that half of the banks appear in the lower segment of the address space and half in the top segment, the MSB of the + -- SDRAM address is used for the split. This is to cater for stack where typically, on the ZPU, the stack would reside + -- in the very top of memory working down and the applications would reside at the bottom of the memory working up. + -- + ------------------------------------------------------------------------------------------------------------------------- + + -- SDRAM Side of dual port RAM. + -- For Read: fifoDataOutHi <= fifoCache_3(sdWriteColumnAddr) + -- fifoDataOutLo <= fifoCache_0(sdWriteColumnAddr) + -- For Write: fifoCache_3 _1 <= fifoDataIn when sdWriteColumnAddr(0) = '0' + -- fifoCache_2 _0 <= fifoDataIn when sdWriteColumnAddr(0) = '1' + -- fifoSdWREN must be asserted ('1') for write operations. + process(ALL) + variable cacheAddr : unsigned(SDRAM_COLUMN_BITS-2+SDRAM_BANK_BITS downto 0); + begin + -- Setup the address based on the index (sdWriteColumnAddr) and the bank (cpuBank) as the cache is linear for 4 banks. + -- + cacheAddr := to_unsigned(cpuBank, SDRAM_BANK_BITS) & sdWriteColumnAddr(SDRAM_COLUMN_BITS-1 downto 1); + + if rising_edge(SDRAM_CLK) then + if fifoSdWREN_1 = '1' then + fifoCache_3(to_integer(cacheAddr)) := fifoDataInHi(WORD_UPPER_16BIT_RANGE); + fifoCache_2(to_integer(cacheAddr)) := fifoDataInHi(WORD_LOWER_16BIT_RANGE); + else + fifoDataOutHi(WORD_UPPER_16BIT_RANGE) <= fifoCache_3(to_integer(cacheAddr)); + fifoDataOutHi(WORD_LOWER_16BIT_RANGE) <= fifoCache_2(to_integer(cacheAddr)); + end if; + + if fifoSdWREN_0 = '1' then + fifoCache_1(to_integer(cacheAddr)) := fifoDataInLo(WORD_UPPER_16BIT_RANGE); + fifoCache_0(to_integer(cacheAddr)) := fifoDataInLo(WORD_LOWER_16BIT_RANGE); + else + fifoDataOutLo(WORD_UPPER_16BIT_RANGE) <= fifoCache_1(to_integer(cacheAddr)); + fifoDataOutLo(WORD_LOWER_16BIT_RANGE) <= fifoCache_0(to_integer(cacheAddr)); + end if; + end if; + end process; + + -- CPU Side of dual port RAM, byte addressable. + -- For Read: DATA_OUT <= fifoCache(bank + ADDR(COLUMN_BITS .. 2)) + -- For Write: fifoCache(0..3) <= cpuDataIn + process(ALL) + variable cacheAddr : unsigned(SDRAM_COLUMN_BITS-2+SDRAM_BANK_BITS downto 0); + begin + -- Setup the address based on the column address bits, 32 bit aligned and the bank (cpuBank) as the cache is linear for 4 banks. + -- + cacheAddr := to_unsigned(cpuBank, SDRAM_BANK_BITS) & unsigned(ADDR(SDRAM_COLUMN_BITS downto 2)); + + if rising_edge(CLK) then + if fifoCPUWREN_3 = '1' then + fifoCache_3(to_integer(cacheAddr)) := cpuDataIn(31 downto 24); + else + DATA_OUT((SDRAM_DATAWIDTH*2)-1 downto ((SDRAM_DATAWIDTH*2)-(SDRAM_DATAWIDTH/2))) <= fifoCache_3(to_integer(unsigned(cacheAddr))); + end if; + + if fifoCPUWREN_2 = '1' then + fifoCache_2(to_integer(cacheAddr)) := cpuDataIn(23 downto 16); + else + DATA_OUT(((SDRAM_DATAWIDTH*2)-(SDRAM_DATAWIDTH/2))-1 downto SDRAM_DATAWIDTH) <= fifoCache_2(to_integer(unsigned(cacheAddr))); + end if; + + if fifoCPUWREN_1 = '1' then + fifoCache_1(to_integer(cacheAddr)) := cpuDataIn(15 downto 8); + else + DATA_OUT(SDRAM_DATAWIDTH-1 downto SDRAM_DATAWIDTH/2) <= fifoCache_1(to_integer(unsigned(cacheAddr))); + end if; + + if fifoCPUWREN_0 = '1' then + fifoCache_0(to_integer(cacheAddr)) := cpuDataIn(7 downto 0); + else + DATA_OUT((SDRAM_DATAWIDTH/2)-1 downto 0) <= fifoCache_0(to_integer(unsigned(cacheAddr))); + end if; + end if; + end process; +end Structure; diff --git a/zpu/devices/sysbus/intr/interrupt_controller.vhd b/zpu/devices/sysbus/intr/interrupt_controller.vhd new file mode 100644 index 0000000..65af208 --- /dev/null +++ b/zpu/devices/sysbus/intr/interrupt_controller.vhd @@ -0,0 +1,67 @@ +-- Interrupt Controller +-- Copyright © 2013 by Alastair M. Robinson +-- Released under the terms of the GNU General Public License +-- version 3 or later. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +entity interrupt_controller is +generic ( + max_int : integer :=15 -- Specify here how many interrupts should be handled. +); +port ( + clk : in std_logic; + reset_n : in std_logic; -- active low + trigger : in std_logic_vector(max_int downto 0) := (others => '0'); -- Unused inputs will be optimised awayby the synthesis tools + enable_mask : in std_logic_vector(max_int downto 0) := (others => '0'); -- Unused inputs will be optimised awayby the synthesis tools + ack : in std_logic; + int : buffer std_logic; -- 1 if an interrupt is pending + status : out std_logic_vector(max_int downto 0) -- Bitfield with a set bit for each pending interrupt +); +end entity; + +architecture rtl of interrupt_controller is + +signal pending : std_logic_vector(max_int+1 downto 0) := (others => '0'); -- highest bit is set if any other bit is set. +begin + + process(clk, reset_n) + begin + if reset_n = '0' then + int <= '0'; + status <= (others => '0'); + + elsif rising_edge(clk) then + + -- Clear the int bit if the interrupt is acknowledged. + -- While int is 1, the status is frozen, and new interrupts + -- are held pending, which prevents them being lost. + if ack='1' then + int<='0'; + end if; + + -- If no interrupts are currently signalled + -- copy any pending interrupts to status. + -- We clear the pending signal at the same time. + if int='0' then + status<=pending(status'high downto 0); + int<=pending(pending'high); + pending<=(others => '0'); + end if; + + -- Latch any incoming interrupt pulses in the pending signal + -- If no interrupts are already pending this will be propagated + -- on the next clock edge; otherwise it will be stored until + -- the pending interrupt is acknowledged. + for I in trigger'low to trigger'high loop + if trigger(I) = '1' and enable_mask(I) = '1' then + pending(I) <= '1'; + pending(pending'high) <= '1'; + end if; + end loop; + end if; + end process; + +end architecture; diff --git a/zpu/devices/sysbus/ioctl/ioctl.vhd b/zpu/devices/sysbus/ioctl/ioctl.vhd new file mode 100644 index 0000000..ff183bf --- /dev/null +++ b/zpu/devices/sysbus/ioctl/ioctl.vhd @@ -0,0 +1,528 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: ioctl.vhd +-- Created: November 2018 +-- Author(s): Philip Smart +-- Description: ZPU SOC IOCTL Interface to an Emulator (Sharp MZ series). +-- This module interfaces the ZPU IO processor to the Emulator IO Control backdoor +-- for updating ROM/RAM, OSD and providing IO services. +-- Credits: +-- Copyright: (c) 2018 Philip Smart +-- +-- History: November 2019 - Initial module written for STORM Wishbone interface, then adapted to +-- work with the ZPU in non-WB direct access. +-- September 2019- Still needs completion, not yet fully operable. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_soc_pkg.all; + +entity IOCTL is + port ( + -- CPU Interface + CLK : in std_logic; -- memory master clock + RESET : in std_logic; -- high active sync reset + ADDR : in std_logic_vector(2 downto 0); + DATA_IN : in std_logic_vector(31 downto 0); -- write data + DATA_OUT : out std_logic_vector(31 downto 0); -- read data + CS : in std_logic; -- Chip Select. + WREN : in std_logic; -- Write enable. + RDEN : in std_logic; -- Read enable. + + -- IRQ outputs -- + IRQ_RD_O : out std_logic; + IRQ_WR_O : out std_logic; + + -- IOCTL Bus -- + IOCTL_DOWNLOAD : out std_logic; -- Downloading to FPGA. + IOCTL_UPLOAD : out std_logic; -- Uploading from FPGA. + IOCTL_CLK : out std_logic; -- I/O Clock. + IOCTL_WR : out std_logic; -- Write Enable to FPGA. + IOCTL_RD : out std_logic; -- Read Enable from FPGA. + IOCTL_SENSE : in std_logic; -- Sense to see if HPS accessing ioctl bus. + IOCTL_SELECT : out std_logic; -- Enable IOP control over ioctl bus. + IOCTL_ADDR : out std_logic_vector(24 downto 0); -- Address in FPGA to write into. + IOCTL_DOUT : out std_logic_vector(31 downto 0); -- Data to be written into FPGA. + IOCTL_DIN : in std_logic_vector(31 downto 0) -- Data to be read into HPS. + ); +end IOCTL; + +architecture Structure of IOCTL is + + -- Constants for register access. + -- + constant MODE_FG_BLUE : integer := 31; + constant MODE_FG_RED : integer := 30; + constant MODE_FG_GREEN : integer := 29; + constant MODE_BG_BLUE : integer := 28; + constant MODE_BG_RED : integer := 27; + constant MODE_BG_GREEN : integer := 26; + subtype MODE_ROTATION is integer range 25 downto 24; + constant MODE_H2X : integer := 23; + constant MODE_V2X : integer := 22; + constant MODE_HALFPIXEL : integer := 21; + + signal DATA_AVAIL : std_logic; + signal WRITE_BUSY : std_logic; + signal WRITE_CHAR_BUSY : std_logic; + signal CLR_RD_CMD : std_logic; + signal CLR_WR_CMD : std_logic; + signal CLR_WR_CHAR_CMD : std_logic; + signal CLR_DATA_AVAIL : std_logic; + signal RD_CMD_STATE : integer range 0 to 5; + signal WR_CMD_STATE : integer range 0 to 5; + signal WR_CHAR_CMD_STATE : integer range 0 to 9; + signal DST_RAM_ADDR : std_logic_vector(24 downto 0); + signal DST_CHAR : std_logic_vector(15 downto 0); + signal DST_HX2 : std_logic; + signal DST_VX2 : std_logic; + signal CG_BYTE : std_logic_vector(7 downto 0); + signal CG_ROW : std_logic_vector(2 downto 0); + signal REGISTER_CMDADDR : std_logic_vector(31 downto 0); + signal REGISTER_DOUT : std_logic_vector(31 downto 0); + signal REGISTER_DIN : std_logic_vector(31 downto 0); + signal REGISTER_CHRCOLS : std_logic_vector(7 downto 0); + signal REGISTER_CGADDR : std_logic_vector(24 downto 0); + signal CON_IOCTL_WR : std_logic; + signal CON_IOCTL_RD : std_logic; + signal CON_IOCTL_SELECT : std_logic; + + -- Array to hold a single character for rotation. + -- + type CGARRAY is array (7 downto 0, 7 downto 0) of std_logic; + signal CGCHAR : CGARRAY; + +begin + + -- REGISTER_CMDADDR: W -> 0 - 24 = IOCTL Address + -- 28 - 25 = Unused + -- 29 = Write Character to address. + -- 30 = Execute IOCTL READ + -- 31 = Execute IOCTL WRITE + -- if 30 and 31 are active ('1') execute WRITE then READ. + -- REGISTER_CMDADDR: R -> 0 - 24 = IOCTL Address + -- 29 = BUSY WITH CHAR WRITE + -- 30 = DATA AVAILABLE + -- 31 = BUSY WITH WRITE + -- + -- REGISTER__DOUT W -> 0 - 23 = IOCTL DOUT + -- 24 = Zoom vertical size character 2x. + -- 25 = Zoom horizontal size character 2x. + -- 26 - 27 = Rotation: 00 - Normal, 01 90' Left, 02 90' Right, 11 180' + -- 28 = Write Menu Character = 1, write Status Character = 0. + -- 29 = Status char Blue. + -- 30 = Status char Red. + -- 31 = Status char Green. + -- REGISTER_DIN R -> 0 - 31 = IOCTL DIN + -- REGISTER_CHRCOLS W -> 0 - 7 = Columns + -- REGISTER_CHRCOLS R -> 0 - 7 = Columns + -- REGISTER_CGADDR W -> 0 - 24 = Start/Base address of CG ROM/RAM. + -- REGISTER_CGADDR R -> 0 - 24 = Start/Base address of CG ROM/RAM. + + -- Input Interface + process(CLK) + begin + if rising_edge(CLK) then + + if (RESET = '1') then + REGISTER_CMDADDR <= (others => '0'); + REGISTER_DOUT <= (others => '0'); + REGISTER_CHRCOLS <= (others => '0'); + REGISTER_CGADDR <= (others => '0'); + + elsif CLR_WR_CMD = '1' then + REGISTER_CMDADDR(31) <= '0'; + + elsif CLR_RD_CMD = '1' then + REGISTER_CMDADDR(30) <= '0'; + + elsif CLR_WR_CHAR_CMD = '1' then + REGISTER_CMDADDR(29) <= '0'; + + elsif CS = '1' and WREN = '1' then -- valid register write access + + case ADDR is + -- Address and Command + when "000" => + REGISTER_CMDADDR <= DATA_IN; + + -- Data Out (DOUT) + when "001" => + REGISTER_DOUT <= DATA_IN; + + -- Character columns per row (CHRCOLS) + when "010" => + REGISTER_CHRCOLS <= DATA_IN(7 downto 0); + + -- CG ROM/RAM Address (CGADDR) + when "011" => + REGISTER_CGADDR <= DATA_IN(24 downto 0); + + when others => + + end case; + end if; + end if; + end process; + + -- Output Interface + process(CLK) + begin + if rising_edge(CLK) then + if (RESET = '1') then + DATA_OUT <= (others => '0'); + CLR_DATA_AVAIL <= '0'; + else + if CLR_DATA_AVAIL = '1' then + CLR_DATA_AVAIL <= '0'; + end if; + + --- Data Output --- + if CS = '1' and RDEN = '1' then -- valid register read request + case ADDR is + + -- Address and Command + when "000" => + DATA_OUT <= WRITE_BUSY & DATA_AVAIL & WRITE_CHAR_BUSY & CON_IOCTL_SELECT & IOCTL_SENSE & "00" & REGISTER_CMDADDR(24 downto 0); + + -- Data in (DIN) + when "001" => + DATA_OUT <= REGISTER_DIN(31 downto 0); + CLR_DATA_AVAIL <= '1'; + + -- Character columns per row (CHRCOLS) + when "010" => + DATA_OUT <= X"000000" & REGISTER_CHRCOLS(7 downto 0); + + -- Start/Base address of CG ROM/RAM (CGADDR) + when "011" => + DATA_OUT <= "0000000" & REGISTER_CGADDR(24 downto 0); + + when others => + DATA_OUT <= (others => '0'); + end case; + else + DATA_OUT <= (others => '0'); + end if; + end if; + end if; + end process; + + -- Process to convert the requested command into an IOCTL transaction. + -- + process(RESET, CLK) + begin + if rising_edge(CLK) then + + if RESET = '1' then + WRITE_BUSY <= '0'; + DATA_AVAIL <= '0'; + CLR_RD_CMD <= '0'; + CLR_WR_CMD <= '0'; + CLR_WR_CHAR_CMD <= '0'; + WR_CMD_STATE <= 0; + WR_CHAR_CMD_STATE <= 0; + RD_CMD_STATE <= 0; + CON_IOCTL_WR <= '0'; + CON_IOCTL_RD <= '0'; + CON_IOCTL_SELECT <= '0'; + IOCTL_DOWNLOAD <= '0'; + IOCTL_UPLOAD <= '0'; + IOCTL_ADDR <= (others => '0'); + DST_RAM_ADDR <= (others => '0'); + DST_CHAR <= (others => '0'); + DST_HX2 <= '0'; + DST_VX2 <= '0'; + + else + if CLR_DATA_AVAIL = '1' then + DATA_AVAIL <= '0'; + end if; + + -- If the IOCTL bus is inactive or becomes externally active during a transaction, process this modules transaction first, else relinquish control. + -- + if IOCTL_SENSE = '0' or (IOCTL_SENSE = '1' and CON_IOCTL_SELECT = '1' and (WR_CMD_STATE /= 0 or RD_CMD_STATE /= 0 or WR_CHAR_CMD_STATE /= 0)) then + + -- Ensure a write transaction can only occur when there is no ongoing read transaction. + if REGISTER_CMDADDR(31) = '1' and WR_CMD_STATE = 0 and RD_CMD_STATE = 0 and WR_CHAR_CMD_STATE = 0 then + CON_IOCTL_SELECT <= '1'; + CLR_WR_CMD <= '1'; + WRITE_BUSY <= '1'; + WR_CMD_STATE <= 1; + + -- Ensure that a read transaction can only occur when there is no ongoing write transaction. + elsif REGISTER_CMDADDR(31 downto 30) = "01" and RD_CMD_STATE = 0 and WR_CMD_STATE = 0 and WR_CHAR_CMD_STATE = 0 then + CON_IOCTL_SELECT <= '1'; + CLR_RD_CMD <= '1'; + DATA_AVAIL <= '0'; + RD_CMD_STATE <= 1; + + -- Ensure that a write char transaction can only occur when there is no ongoing read/write transaction. + elsif REGISTER_CMDADDR(31 downto 29) = "001" and WR_CHAR_CMD_STATE = 0 and WR_CMD_STATE = 0 and RD_CMD_STATE = 0 then + CON_IOCTL_SELECT <= '1'; + CLR_WR_CHAR_CMD <= '1'; + WRITE_CHAR_BUSY <= '1'; + WR_CHAR_CMD_STATE <= 1; + end if; + + -- If we have control of the bus, process. + if CON_IOCTL_SELECT = '1' then + + case WR_CMD_STATE is + -- Holding state. + when 0 => + CLR_WR_CMD <= '0'; + + when 1 => + IOCTL_ADDR <= REGISTER_CMDADDR(24 downto 0); + IOCTL_DOUT <= REGISTER_DOUT; + IOCTL_DOWNLOAD <= '1'; + IOCTL_UPLOAD <= '0'; + WR_CMD_STATE <= 2; + + when 2 => + CON_IOCTL_WR <= '1'; + WR_CMD_STATE <= 3; + + when 3 => + CON_IOCTL_WR <= '0'; + WR_CMD_STATE <= 4; + + when 4 => + WRITE_BUSY <= '0'; + IOCTL_DOWNLOAD <= '0'; + WR_CMD_STATE <= 0; + + when others => + end case; + + case RD_CMD_STATE is + -- Holding state. + when 0 => + CLR_RD_CMD <= '0'; + + when 1 => + IOCTL_ADDR <= REGISTER_CMDADDR(24 downto 0); + IOCTL_UPLOAD <= '1'; + IOCTL_DOWNLOAD <= '0'; + CON_IOCTL_RD <= '1'; + RD_CMD_STATE <= 2; + + when 2 => + REGISTER_DIN <= IOCTL_DIN; + RD_CMD_STATE <= 3; + + when 3 => + CON_IOCTL_RD <= '0'; + IOCTL_UPLOAD <= '0'; + DATA_AVAIL <= '1'; + RD_CMD_STATE <= 0; + + when others => + end case; + + case WR_CHAR_CMD_STATE is + -- Holding state. + when 0 => + CLR_WR_CHAR_CMD <= '0'; + + when 1 => + CG_ROW <= (others => '0'); + WR_CHAR_CMD_STATE <= 2; + + when 2 => + IOCTL_UPLOAD <= '1'; + IOCTL_ADDR <= std_logic_vector(unsigned(REGISTER_CGADDR(24 downto 0)) + unsigned(REGISTER_DOUT(7 downto 0) & "000") + unsigned(CG_ROW)); + CON_IOCTL_RD <= '1'; + WR_CHAR_CMD_STATE <= 3; + + when 3 => -- delay to allow valid read from CGROM. + WR_CHAR_CMD_STATE <= 4; + + when 4 => + for i in 0 to 7 loop + CGCHAR(to_integer(unsigned(CG_ROW)), i) <= IOCTL_DIN(i); + end loop; + CON_IOCTL_RD <= '0'; + CG_ROW <= std_logic_vector(unsigned(CG_ROW) + 1); + + if CG_ROW = "111" then + IOCTL_UPLOAD <= '0'; + WR_CHAR_CMD_STATE <= 5; + else + WR_CHAR_CMD_STATE <= 2; + end if; + + when 5 => + DST_RAM_ADDR <= REGISTER_CMDADDR(24 downto 0); + CG_ROW <= (others => '0'); + IOCTL_DOWNLOAD <= '1'; + WR_CHAR_CMD_STATE <= 6; + + when 6 => + DST_CHAR <= X"0000"; + DST_HX2 <= '1'; + DST_VX2 <= '1'; + + -- Rotation of character. + case REGISTER_DOUT(MODE_ROTATION) is + when "00" => -- Normal + for i in 0 to 7 loop + if REGISTER_DOUT(MODE_H2X) = '0' then + DST_CHAR(i+8) <= CGCHAR(to_integer(unsigned(CG_ROW)), i); + else + DST_CHAR(i*2) <= CGCHAR(to_integer(unsigned(CG_ROW)), i); + if REGISTER_DOUT(MODE_HALFPIXEL) = '0' then + DST_CHAR((i*2)+1) <= CGCHAR(to_integer(unsigned(CG_ROW)), i); + end if; + end if; + end loop; + when "01" => -- Rotate 90' Left + for i in 7 downto 0 loop + if REGISTER_DOUT(MODE_H2X) = '0' then + DST_CHAR(15-i) <= CGCHAR(i, to_integer(unsigned(CG_ROW))); + else + DST_CHAR(15-((i*2)+1)) <= CGCHAR(i, to_integer(unsigned(CG_ROW))); + if REGISTER_DOUT(MODE_HALFPIXEL) = '0' then + DST_CHAR(15-(i*2)) <= CGCHAR(i, to_integer(unsigned(CG_ROW))); + end if; + end if; + end loop; + when "10" => -- Rotate 90' Right + for i in 0 to 7 loop + if REGISTER_DOUT(MODE_H2X) = '0' then + DST_CHAR(i+8) <= CGCHAR(i, 7-to_integer(unsigned(CG_ROW))); + else + DST_CHAR(i*2) <= CGCHAR(i, 7-to_integer(unsigned(CG_ROW))); + if REGISTER_DOUT(MODE_HALFPIXEL) = '0' then + DST_CHAR((i*2)+1) <= CGCHAR(i, 7-to_integer(unsigned(CG_ROW))); + end if; + end if; + end loop; + when "11" => -- Rotate 180' + for i in 0 to 7 loop + if REGISTER_DOUT(MODE_H2X) = '0' then + DST_CHAR(i+8) <= CGCHAR(7-to_integer(unsigned(CG_ROW)), i); + else + DST_CHAR(i*2) <= CGCHAR(7-to_integer(unsigned(CG_ROW)), i); + if REGISTER_DOUT(MODE_HALFPIXEL) = '0' then + DST_CHAR((i*2)+1) <= CGCHAR(7-to_integer(unsigned(CG_ROW)), i); + end if; + end if; + end loop; + end case; + WR_CHAR_CMD_STATE <= 7; + + when 7 => + IOCTL_ADDR <= DST_RAM_ADDR; + + -- For vertical half pixels, each 2nd row is blank only if we are not skipping horizontal pixels due to horizontal doubling. + if REGISTER_DOUT(MODE_HALFPIXEL) = '0' or REGISTER_DOUT(MODE_H2X) = '1' or (REGISTER_DOUT(MODE_HALFPIXEL) = '1' and REGISTER_DOUT(MODE_H2X) = '0' and DST_VX2 = '1') then + for i in 7 downto 0 loop + if REGISTER_DOUT(MODE_FG_GREEN) = '1' and DST_CHAR(i+8) = '1' then + IOCTL_DOUT(i) <= DST_CHAR(i+8); + elsif REGISTER_DOUT(MODE_BG_GREEN) = '1' and DST_CHAR(i+8) = '0' then + IOCTL_DOUT(i) <= '1'; --DST_CHAR(i+8); + else + IOCTL_DOUT(i) <= '0'; + end if; + + if REGISTER_DOUT(MODE_FG_RED) = '1' and DST_CHAR(i+8) = '1' then + IOCTL_DOUT(i+8) <= DST_CHAR(i+8); + elsif REGISTER_DOUT(MODE_BG_RED) = '1' and DST_CHAR(i+8) = '0' then + IOCTL_DOUT(i+8) <= '1'; --DST_CHAR(i+8); + else + IOCTL_DOUT(i+8) <= '0'; + end if; + + if REGISTER_DOUT(MODE_FG_BLUE) = '1' and DST_CHAR(i+8) = '1' then + IOCTL_DOUT(i+16) <= DST_CHAR(i+8); + elsif REGISTER_DOUT(MODE_BG_BLUE) = '1' and DST_CHAR(i+8) = '0' then + IOCTL_DOUT(i+16) <= '1'; --DST_CHAR(i+8); + else + IOCTL_DOUT(i+16) <= '0'; + end if; + end loop; + else + IOCTL_DOUT <= X"00000000"; + end if; + WR_CHAR_CMD_STATE <= 8; + + when 8 => + CON_IOCTL_WR <= '1'; + WR_CHAR_CMD_STATE <= 9; + + when 9 => + CON_IOCTL_WR <= '0'; + if REGISTER_DOUT(MODE_V2X) = '1' and DST_VX2 = '1' then + DST_VX2 <= '0'; + DST_RAM_ADDR <= std_logic_vector(unsigned(DST_RAM_ADDR) + unsigned(REGISTER_CHRCOLS(7 downto 0))); + WR_CHAR_CMD_STATE <= 7; + elsif REGISTER_DOUT(MODE_H2X) = '1' and DST_HX2 = '1' then + if REGISTER_DOUT(MODE_V2X) = '1' then + DST_VX2 <= '1'; + DST_RAM_ADDR <= std_logic_vector(unsigned(DST_RAM_ADDR) - unsigned(REGISTER_CHRCOLS(7 downto 0)) + 1); + else + DST_RAM_ADDR <= std_logic_vector(unsigned(DST_RAM_ADDR) + 1); + end if; + DST_CHAR(15 downto 8) <= DST_CHAR(7 downto 0); + DST_HX2 <= '0'; + WR_CHAR_CMD_STATE <= 7; + elsif CG_ROW = "111" then + WRITE_CHAR_BUSY <= '0'; + IOCTL_DOWNLOAD <= '0'; + WR_CHAR_CMD_STATE <= 0; + else + CG_ROW <= std_logic_vector(unsigned(CG_ROW) + 1); + if REGISTER_DOUT(MODE_H2X) = '1' then + DST_RAM_ADDR <= std_logic_vector(unsigned(DST_RAM_ADDR) -1 + unsigned(REGISTER_CHRCOLS(7 downto 0))); + else + DST_RAM_ADDR <= std_logic_vector(unsigned(DST_RAM_ADDR) + unsigned(REGISTER_CHRCOLS(7 downto 0))); + end if; + WR_CHAR_CMD_STATE <= 6; + end if; + + when others => + end case; + end if; + else + -- Relinquish control of bus. + CON_IOCTL_SELECT <= '0'; + end if; + end if; + end if; + end process; + + -- IOCTL clock uses system clock. + -- + IOCTL_CLK <= CLK; + + -- Interrupt lines + -- + IRQ_RD_O <= '0'; + IRQ_WR_O <= '0'; + + -- Buffers to enable signal state read. + -- + IOCTL_WR <= CON_IOCTL_WR; + IOCTL_RD <= CON_IOCTL_RD; + IOCTL_SELECT <= CON_IOCTL_SELECT; + +end Structure; diff --git a/zpu/devices/sysbus/ps2/io_ps2_com.vhd b/zpu/devices/sysbus/ps2/io_ps2_com.vhd new file mode 100644 index 0000000..f487fee --- /dev/null +++ b/zpu/devices/sysbus/ps2/io_ps2_com.vhd @@ -0,0 +1,236 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2009 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com +-- +-- A few tweaks by Alastair M. Robinson +-- +-- This source file is free software: you can redistribute it and/or modify +-- it under the terms of the GNU Lesser General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- ----------------------------------------------------------------------- +-- +-- PS/2 lowlevel driver +-- +-- ----------------------------------------------------------------------- +-- +-- clockFilter - Number of clock cycles used in filtering the PS/2 clock. +-- This suppresses transient and echo effects on the cable. +-- Recommended value is 15. +-- ticksPerUsec - Fill in the system clock speed in Mhz. +-- clk - system clock input +-- ps2_clk_in - Clock input from the ps/2 port +-- ps2_dat_in - Data input from the ps/2 port +-- ps2_clk_out - Generated ps/2 clock route to open-collector logic. +-- ps2_dat_out - Generated ps/2 data line route to open-collector logic. +-- inIdle - Output is high when driver is waiting/idle. +-- sendTrigger - Make this signal 1 clock cycle high to send byte +-- sendByte - Actual byte send when sendTrigger is given +-- sendDone - High for 1 clock when send complete. (AMR) +-- recvTrigger - Is 1 clock cycle high when byte is received. +-- recvByte - Last byte received from the ps/2 interface +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity io_ps2_com is + generic ( + clockFilter : integer; + ticksPerUsec : integer + ); + port ( + clk: in std_logic; + reset : in std_logic; + ps2_clk_in: in std_logic; + ps2_dat_in: in std_logic; + ps2_clk_out: out std_logic; + ps2_dat_out: out std_logic; + + inIdle : out std_logic; + + sendTrigger : in std_logic; + sendByte : in std_logic_vector(7 downto 0); + sendBusy : out std_logic; + sendDone : out std_logic; + recvTrigger : out std_logic; + recvByte : out std_logic_vector(10 downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of io_ps2_com is + constant ticksPer100Usec : integer := ticksPerUsec * 100; + type comStateDef is ( + stateIdle, stateWait100, stateWaitClockLow, stateWaitClockHigh, stateClockAndDataLow, stateWaitAck, + stateRecvBit, stateWaitHighRecv); + signal comState : comStateDef := stateIdle; + + signal sendTriggerLoc : std_logic := '0'; + signal clkReg: std_logic := '1'; + signal clkFilterCnt: integer range 0 to clockFilter; + + signal waitCount : integer range 0 to ticksPer100Usec := 0; + signal currentBit : std_logic; + signal bitCount : unsigned(3 downto 0); + signal parity : std_logic; + + signal recvByteLoc : std_logic_vector(10 downto 0); + signal ena : std_logic; +begin + inIdle <= '1' when comState = stateIdle else '0'; + sendBusy <= sendTrigger or sendTriggerLoc; +-- +-- Noise and glitch filter on the clock-line + process(clk) + begin + if rising_edge(clk) then + ena <= not ena; + clkReg <= ps2_clk_in; + if clkReg /= ps2_clk_in then + clkFilterCnt <= clockFilter; + elsif clkFilterCnt /= 0 then + clkFilterCnt <= clkFilterCnt - 1; + end if; + end if; + end process; + +-- +-- Lowlevel send and receive state machines + process(clk) + begin + if rising_edge(clk) then + sendDone <= '0'; + recvTrigger <= '0'; + if ena='1' then + ps2_clk_out <= '1'; + ps2_dat_out <= '1'; + if waitCount /= 0 then + waitCount <= waitCount - 1; + end if; + + if sendTrigger = '1' then + sendTriggerLoc <= '1'; + end if; + + case comState is + when stateIdle => + bitCount <= (others => '0'); + parity <= '1'; + if sendTriggerLoc = '1' then + waitCount <= ticksPer100Usec; + comState <= stateWait100; + end if; + if (clkReg = '0') and (clkFilterCnt = 0) then + comState <= stateRecvBit; + end if; + -- + -- Host announces its wish to send by pulling clock low for 100us + when stateWait100 => + ps2_clk_out <= '0'; + if waitCount = 0 then + comState <= stateClockAndDataLow; + waitCount <= ticksPerUsec * 10; + end if; + -- + -- Pull data low while keeping clock low. This is host->device start bit. + -- Now the device will take over and provide the clock so host must release. + -- Next state is waitClockHigh to check that clock indeed is released + when stateClockAndDataLow => + ps2_clk_out <= '0'; + ps2_dat_out <= '0'; + if waitCount = 0 then + currentBit <= '0'; + comState <= stateWaitClockHigh; + end if; + -- + -- Wait for 0->1 transition on clock for send. + -- The device reads current bit while clock is low. + when stateWaitClockHigh => + ps2_dat_out <= currentBit; + if (clkReg = '1') and (clkFilterCnt = 0) then + comState <= stateWaitClockLow; + end if; + -- + -- Wait for 1->0 transition on clock for send + -- Host can now change the data line for next bit. + when stateWaitClockLow => + ps2_dat_out <= currentBit; + if (clkReg = '0') and (clkFilterCnt = 0) then + if bitCount = 10 then + comState <= stateWaitAck; + elsif bitCount = 9 then + -- Send stop bit + currentBit <= '1'; + comState <= stateWaitClockHigh; + bitCount <= bitCount + 1; + elsif bitCount = 8 then + -- Send parity bit + currentBit <= parity; + comState <= stateWaitClockHigh; + bitCount <= bitCount + 1; + else + currentBit <= sendByte(to_integer(bitCount)); + parity <= parity xor sendByte(to_integer(bitCount)); + comState <= stateWaitClockHigh; + bitCount <= bitCount + 1; + end if; + end if; + -- + -- Transmission of byte done, wait for ack from device then return to idle. + when stateWaitAck => + if (clkReg = '1') and (clkFilterCnt = 0) then + sendTriggerLoc <= '0'; + sendDone<='1'; + comState <= stateIdle; + end if; + -- + -- Receive a single bit. + when stateRecvBit => + if (clkReg = '0') and (clkFilterCnt = 0) then + recvByteLoc <= ps2_dat_in & recvByteLoc(recvByteLoc'high downto 1); + bitCount <= bitCount + 1; + comState <= stateWaitHighRecv; + end if; + -- + -- Wait for 0->1 transition on clock for receive. + when stateWaitHighRecv => + if (clkReg = '1') and (clkFilterCnt = 0) then + comState <= stateRecvBit; + if bitCount = 11 then + recvTrigger <= '1'; + recvByte <= recvByteLoc; + comState <= stateIdle; + end if; + end if; + end case; + + if reset = '1' then + comState <= stateIdle; + sendTriggerLoc <= '0'; + end if; + end if; + end if; + end process; +end architecture; + + + diff --git a/zpu/devices/sysbus/spi/spi.vhd b/zpu/devices/sysbus/spi/spi.vhd new file mode 100644 index 0000000..6a0527e --- /dev/null +++ b/zpu/devices/sysbus/spi/spi.vhd @@ -0,0 +1,105 @@ +-- Adapted by AMR from the Chameleon Minimig cfide.vhd file, +-- originally by Tobias Gubener. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. +-- +-- +-- spi_to_host contains data received from slave device. +-- Busy bit now has a signal of its own. + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + + +entity spi_interface is + port ( + sysclk : in std_logic; + reset : in std_logic; + + -- Host interface + spiclk_in : in std_logic; -- Momentary high pulse + host_to_spi : in std_logic_vector(7 downto 0); + spi_to_host : out std_logic_vector(31 downto 0); +-- wide : in std_logic; -- 16-bit transfer (in only, 0xff will be transmitted for the second byte) + trigger : in std_logic; -- Momentary high pulse + busy : buffer std_logic; + + -- Hardware interface + miso : in std_logic; + mosi : out std_logic; + spiclk_out : out std_logic -- 50% duty cycle + ); +end entity; + +architecture rtl of spi_interface is +signal sck : std_logic; +signal sd_shift : std_logic_vector(7 downto 0); +--signal sd_shift : std_logic_vector(31 downto 0); +signal shiftcnt : std_logic_vector(5 downto 0); +begin + +----------------------------------------------------------------- +-- SPI-Interface +----------------------------------------------------------------- + spiclk_out <= sck; + busy <= shiftcnt(5) or trigger; + spi_to_host <= X"000000"&sd_shift; + + PROCESS (sysclk, reset) BEGIN + + IF reset ='0' THEN + shiftcnt(5)<='0'; + sck <= '0'; + ELSIF rising_edge(sysclk) then + IF trigger='1' then +-- shiftcnt <= "1" & wide & wide & "111"; -- shift out 8 (or 32) bits, underflow will clear bit 5, mapped to busy + shiftcnt <= "100111"; -- shift out 8 (or 32) bits, underflow will clear bit 5, mapped to busy + sd_shift <= host_to_spi(7 downto 0); -- & X"FFFFFF"; + sck <= '1'; + ELSE + IF spiclk_in='1' and busy='1' THEN + IF sck='1' THEN +-- mosi<=sd_shift(31); + mosi<=sd_shift(7); + sck <='0'; + ELSE + sck <='1'; +-- sd_shift <= sd_shift(30 downto 0)&miso; + sd_shift <= sd_shift(6 downto 0)&miso; + shiftcnt <= shiftcnt-1; + END IF; + END IF; + END IF; + end if; + END PROCESS; + +end architecture; diff --git a/zpu/devices/sysbus/timer/timer_controller.vhd b/zpu/devices/sysbus/timer/timer_controller.vhd new file mode 100644 index 0000000..0b61772 --- /dev/null +++ b/zpu/devices/sysbus/timer/timer_controller.vhd @@ -0,0 +1,131 @@ +-- 32bit prescaled Timer +-- +-- Original Author unknown. +-- Updated for ZPU SoC use: Philip Smart, 2019. +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. +library ieee; +use ieee.std_logic_1164.all; +use IEEE.numeric_std.ALL; + +library work; + +-- Timer controller module + +entity timer_controller is + generic( + prescale : integer := 1; -- Prescale incoming clock + timers : integer := 0 -- This is a power of 2, so zero means 1 counter, 4 means 16 counters... + ); + port ( + clk : in std_logic; + reset : in std_logic; -- active low + + reg_addr_in : in std_logic_vector(7 downto 0); -- from host CPU + reg_data_in : in std_logic_vector(31 downto 0); + reg_rw : in std_logic; + reg_req : in std_logic; + + ticks : out std_logic_vector(2**timers-1 downto 0) + ); +end entity; + +architecture rtl of timer_controller is + constant prescale_adj : integer := prescale-1; + signal prescale_counter : unsigned(15 downto 0); + signal prescaled_tick : std_logic; + type timer_counters is array (2**timers-1 downto 0) of unsigned(31 downto 0); + signal timer_counter : timer_counters; + signal timer_limit : timer_counters; + signal timer_enabled : std_logic_vector(2**timers-1 downto 0); + signal timer_index : unsigned(7 downto 0); +begin + + -- Prescaled tick + process(clk, reset) + begin + if reset='0' then + prescale_counter <=(others => '0'); + elsif rising_edge(clk) then + prescaled_tick <='0'; + prescale_counter <=prescale_counter-1; + if prescale_counter=X"00" then + prescaled_tick <='1'; + prescale_counter <=to_unsigned(prescale_adj,16); + end if; + end if; + end process; + + -- The timers proper; + process(clk,reset) + begin + if reset='0' then + for I in 0 to (2**timers-1) loop + timer_counter(I) <= (others => '0'); + end loop; + elsif rising_edge(clk) then + ticks <= (others => '0'); + if prescaled_tick='1' then + for I in 0 to (2**timers-1) loop + if timer_enabled(I)='1' then + timer_counter(I) <=timer_counter(I)-1; + if timer_counter(I)=X"00000000" then + timer_counter(I)<=timer_limit(I); + ticks(I) <='1'; + end if; + end if; + end loop; + end if; + end if; + end process; + + -- Handle CPU access to hardware registers + process(clk,reset) + begin + if reset='0' then + timer_enabled <= (others => '0'); + elsif rising_edge(clk) then + if reg_req='1' and reg_rw='0' then -- Write access + case reg_addr_in is + when X"00" => + timer_enabled <= reg_data_in(2**timers-1 downto 0); + when X"04" => + timer_index <= unsigned(reg_data_in(7 downto 0)); + when X"08" => + timer_limit(to_integer(timer_index(timers downto 0)))<= unsigned(reg_data_in(31 downto 0)); + when others => + null; + end case; + end if; + end if; + end process; + +end architecture; diff --git a/zpu/devices/sysbus/uart/uart.vhd b/zpu/devices/sysbus/uart/uart.vhd new file mode 100644 index 0000000..cac2657 --- /dev/null +++ b/zpu/devices/sysbus/uart/uart.vhd @@ -0,0 +1,511 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: uart.vhd +-- Created: January 2019 +-- Author(s): Philip Smart +-- Description: A simplistic UART fixed at 8N1 but with configurable baud rate and RX/TX FifoÅ›. +-- Credits: Originally using the simplistic UART as a guide, which was written by the following +-- authors:- +-- Philippe Carton, philippe.carton2 libertysurf.fr +-- Juan Pablo Daniel Borgna, jpdborgna gmail.com +-- Salvador E. Tropea, salvador inti.gob.ar +-- Copyright: (c) 2019 Philip Smart +-- +-- History: January 2019 - Initial module written using the simplistic UART as a guide but +-- adding cache and more control. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; +use work.zpu_soc_pkg.all; + +-- Based on the simplistic UART, handles 8N1 RS232 Rx/Tx with independent programmable baud rate and selectable FIFO buffers. +entity uart is + generic ( + RX_FIFO_BIT_DEPTH : integer := 10; + TX_FIFO_BIT_DEPTH : integer := 8; + COUNTER_BITS : natural := 16; + BAUDCLK_FREQUENCY : integer := SYSTEM_FREQUENCY -- Baud rate clock frequency, used so a program can determine the clocking frequency and set divisor accordingly. + ); + port ( + -- CPU Interface + CLK : in std_logic; -- memory master clock + RESET : in std_logic; -- high active sync reset + ADDR : in std_logic_vector(1 downto 0); -- 0 = Read/Write Data, 1 = Control Register, 3 = Baud Register + DATA_IN : in std_logic_vector(wordSize-1 downto 0); -- write data + DATA_OUT : out std_logic_vector(wordSize-1 downto 0); -- read data + CS : in std_logic; -- Chip Select. + WREN : in std_logic; -- Write enable. + RDEN : in std_logic; -- Read enable. + + -- IRQ outputs + TXINTR : out std_logic; -- Tx buffer empty interrupt. + RXINTR : out std_logic; -- Rx buffer full interrupt. + + -- Serial data + TXD : out std_logic; + RXD : in std_logic + ); +end uart; + +architecture rtl of uart is + +signal RXD_SYNC : std_logic; +signal RXD_SYNC2 : std_logic; + +type RXSTATES is (idle, start, bits, stop); +signal RX_STATE : RXSTATES := idle; + +signal RX_CLOCK_DIVISOR : unsigned(COUNTER_BITS-1 downto 0) := X"043D"; -- Main clock divisor to create RX Clock. +signal RX_COUNTER : unsigned(COUNTER_BITS-1 downto 0); -- RX Clock generator counter. +signal RX_CLOCK : std_logic; -- RX Clock. +signal RX_BUFFER : std_logic_vector(8 downto 0); -- Receive deserialisation buffer. +signal RX_DATA : std_logic_vector(7 downto 0); -- Received data holding register. +signal RX_DATA_READY : std_logic; -- Byte available to read = 1 +signal RX_OVERRUN : std_logic; -- New byte received before previous read by CPU, old value lost. +signal RX_INTR : std_logic; -- Rx buffer full interrupt. +signal RX_ENABLE : std_logic; -- Enable RX unit. +signal RX_ENABLE_FIFO : std_logic; -- Enable RX FIFO. +signal RX_RESET : std_logic; -- Reset RX unit. +signal RX_FIFO_EMPTY : std_logic; -- RX FIFO is empty = 1. +signal RX_FIFO_FULL : std_logic; -- RX FIFO is full = 1. + +type TXSTATES is (idle, bits); +signal TX_STATE : TXSTATES := idle; + +signal TX_CLOCK_DIVISOR : unsigned(COUNTER_BITS-1 downto 0) := X"043D"; -- Main clock divisor to create TX Clock. +signal TX_BUFFER : std_logic_vector(17 downto 0); -- Transmit serialisation buffer. +signal TX_DATA : std_logic_vector(7 downto 0); -- Transmit holding register. +signal TX_DATA_LOADED : std_logic; -- Data loaded into transmit buffer. +signal TX_BUSY : std_logic; -- Transmit in progress. +signal TX_OVERRUN : std_logic; -- TX write when last byte not sent or fifo full. +signal TX_COUNTER : unsigned(COUNTER_BITS-1 downto 0); -- TX Clock generator counter. +signal TX_CLOCK : std_logic; -- TX Clock. +signal TX_INTR : std_logic; -- Tx buffer empty interrupt. +signal TX_ENABLE : std_logic; -- Enable TX unit. +signal TX_ENABLE_FIFO : std_logic; -- Enable TX FIFO. +signal TX_RESET : std_logic; -- Reset TX unit. +signal TX_FIFO_EMPTY : std_logic; -- TX FIFO is empty = 1. +signal TX_FIFO_FULL : std_logic; -- TX FIFO is full = 1. + +-- FIFO buffers. +type RX_MEM_T is array (0 to ((2**RX_FIFO_BIT_DEPTH)-1)) of std_logic_vector(7 downto 0); +type TX_MEM_T is array (0 to ((2**TX_FIFO_BIT_DEPTH)-1)) of std_logic_vector(7 downto 0); +signal RX_FIFO : RX_MEM_T; +signal TX_FIFO : TX_MEM_T; +-- RX Fifo address pointers. +signal RX_FIFO_WR_ADDR : unsigned(RX_FIFO_BIT_DEPTH-1 downto 0); +signal RX_FIFO_RD_ADDR : unsigned(RX_FIFO_BIT_DEPTH-1 downto 0); +-- TX Fifo address pointers. +signal TX_FIFO_WR_ADDR : unsigned(TX_FIFO_BIT_DEPTH-1 downto 0); +signal TX_FIFO_RD_ADDR : unsigned(TX_FIFO_BIT_DEPTH-1 downto 0); + +begin + + -- Signal synchronisation for rxd. + -- Without this, the state machine can get messed up. The change from one state + -- to another is not an atomic operation; leaving one state and entering the next + -- are distinct, and it's possible (and, in fact, common) for one + -- to happen without the other if inputs aren't properly synchronised. + process(CLK, RXD, RX_ENABLE) + begin + if RX_ENABLE = '1' and rising_edge(CLK) then + RXD_SYNC2 <= RXD; + RXD_SYNC <= RXD_SYNC2; + end if; + end process; + + + -- Clock generators. + -- We have independent Rx and Tx clocks, generated from counters which count down from clock_divisor to zero. + -- At zero, we generate a momentary high pulse which is used as the serial clock signal. + + -- Tx Clock generation + -- Very simple - the counter is reset when either it reaches zero or + -- the Tx is idle, and counts down once per system clock tick. + process(CLK, TX_ENABLE, TX_CLOCK_DIVISOR) + begin + if TX_ENABLE = '1' and rising_edge(CLK) then + TX_CLOCK <= '0'; + + if TX_STATE = idle then + TX_COUNTER <= TX_CLOCK_DIVISOR; + else + TX_COUNTER <= TX_COUNTER-1; + if TX_COUNTER = 0 then + TX_CLOCK <= '1'; + TX_COUNTER <= TX_CLOCK_DIVISOR; + end if; + end if; + end if; + end process; + + + -- Rx Clock generation + -- The Rx clock is slightly more complicated. When idle we detect the leading edge of the + -- start bit, and set the counter to half a bit width. When it reaches zero, the counter is + -- set to a full bit width, so clock ticks should land in the centre of each bit. + process(clk,RXD_SYNC,RX_COUNTER,RX_STATE,RX_ENABLE) + begin + if RX_ENABLE = '1' and rising_edge(clk) then + RX_CLOCK <= '0'; + + if RX_STATE=idle then + if RXD_SYNC='0' then -- Start bit? Set counter to half a bit width + RX_COUNTER <= '0' & RX_CLOCK_DIVISOR(COUNTER_BITS-1 downto 1); + end if; + else + RX_COUNTER<=RX_COUNTER-1; + if RX_COUNTER=0 then + RX_CLOCK <= '1'; + RX_COUNTER <= RX_CLOCK_DIVISOR; + end if; + end if; + end if; + end process; + + + -- Data Rx + -- We use a 9-bit shift register here. Upon detection of the start bit, we + -- load the shift register with "100000000". + -- As each bit is received we shift the register one bit to the right, and load new data + -- into bit 8. + -- When the 1 initially in bit 8 reaches bit zero we know we've received the entire word. + process(clk,RX_RESET,RXD_SYNC,RX_STATE,RX_FIFO_RD_ADDR,RX_FIFO_WR_ADDR,RX_ENABLE,RX_INTR) + variable RX_FULL_V : std_logic; + variable RX_EMPTY_V : std_logic; + begin + + if RX_RESET='1' then + RX_STATE <= idle; + RX_INTR <= '0'; + RX_DATA_READY <= '0'; + RX_OVERRUN <= '0'; + RX_FIFO_WR_ADDR <= (others => '0'); + RX_FIFO_RD_ADDR <= (others => '0'); + RX_FIFO_EMPTY <= '1'; + RX_FIFO_FULL <= '0'; + + elsif RX_ENABLE = '1' and rising_edge(clk) then + + -- Interrupts only last 1 clock cycle, clear any active interrupt. + RX_INTR <= '0'; + + -- When Read and Write FIFO addresses are equal, FIFO is empty. + if RX_FIFO_RD_ADDR = RX_FIFO_WR_ADDR then + RX_EMPTY_V := '1'; + else + RX_EMPTY_V := '0'; + end if; + + -- When Write address is 1 behind the read address, FIFO is full. + if RX_FIFO_WR_ADDR = RX_FIFO_RD_ADDR-1 then + RX_FULL_V := '1'; + else + RX_FULL_V := '0'; + end if; + + -- If CPU requests to read data, clear the DATA_READY flag. + -- + if CS = '1' and RDEN = '1' and ADDR = "00" and RX_DATA_READY = '1' then + RX_DATA_READY <= '0'; + end if; + + -- If fifo enabled and RX_DATA register is empty, pop the next byte off the stack for the CPU to read. + -- + if RX_ENABLE_FIFO = '1' and RX_DATA_READY = '0' and RX_EMPTY_V ='0' then + RX_DATA <= RX_FIFO( to_integer(RX_FIFO_RD_ADDR) ); + RX_FIFO_RD_ADDR <= RX_FIFO_RD_ADDR + 1; + RX_DATA_READY <= '1'; + end if; + + case RX_STATE is + when idle => + if RXD_SYNC='0' then + RX_STATE <= start; + end if; + when start => + if RX_CLOCK='1' then + if RXD_SYNC='0' then + RX_BUFFER <= "100000000"; -- Set marker bit. + RX_STATE <= bits; + else + RX_STATE <= idle; + end if; + end if; + when bits => + if RX_CLOCK='1' then + RX_BUFFER <= RXD_SYNC & RX_BUFFER(8 downto 1); + end if; + if RX_BUFFER(0)='1' then -- Marker bit has reached bit 0 + RX_STATE <= stop; + end if; + when stop => + if RX_CLOCK='1' then + if RXD_SYNC='1' then -- valid stop bit? + + -- If fifo enabled and space available, write otherwise discard. + if RX_ENABLE_FIFO = '1' then + if RX_FULL_V = '0' then + RX_FIFO(to_integer(RX_FIFO_WR_ADDR)) <= RX_BUFFER(8 downto 1); + RX_FIFO_WR_ADDR <= RX_FIFO_WR_ADDR + 1; + else + RX_OVERRUN <= '1'; + end if; + + -- Interrupt if first byte or buffer becoming full. + if (RX_EMPTY_V = '1' and RX_DATA_READY = '0') or RX_FIFO_WR_ADDR = RX_FIFO_RD_ADDR - 2 then + RX_INTR <= '1'; + end if; + else + if RX_DATA_READY = '0' then + RX_DATA <= RX_BUFFER(8 downto 1); + RX_DATA_READY <= '1'; + else + RX_OVERRUN <= '1'; + end if; + + -- Always interrupt if fifo disabled. + RX_INTR <= '1'; + end if; + end if; + RX_STATE <= idle; + end if; + when others => + RX_STATE <= idle; + end case; + end if; + + -- Put variables onto external signals. + RX_FIFO_EMPTY <= RX_EMPTY_V; + RX_FIFO_FULL <= RX_FULL_V; + + -- Put internal interrupt status onto bus. + RXINTR <= RX_INTR; + end process; + + -- Process to read data from the receive buffer/fifo when selected. + process(clk, RX_RESET, RX_ENABLE) + begin + if RX_RESET = '1' then + + elsif RX_ENABLE = '1' and rising_edge(clk) then + + end if; + end process; + + + -- Data Tx + -- Similarly to the Rx routine, we use a shift register larger than the word, + -- which also includes a marker bit. This time the marker bit is a zero, and when + -- the zero reaches bit 8, we know we've transmitted the entire word plus one stop bit. + process(clk,TX_RESET,TX_STATE,TX_FIFO_RD_ADDR,TX_FIFO_WR_ADDR,TX_ENABLE,TX_INTR) + variable TX_FULL_V : std_logic; + variable TX_EMPTY_V : std_logic; + begin + if TX_FIFO_RD_ADDR=TX_FIFO_WR_ADDR then + TX_EMPTY_V := '1'; + else + TX_EMPTY_V := '0'; + end if; + + if TX_FIFO_WR_ADDR = TX_FIFO_RD_ADDR-1 then + TX_FULL_V := '1'; + else + TX_FULL_V := '0'; + end if; + + if TX_RESET='1' then + TX_STATE <= idle; + TX_BUSY <= '0'; + TX_DATA_LOADED <= '0'; + TXD <= '1'; + TX_INTR <= '0'; + TX_OVERRUN <= '0'; + TX_FIFO_WR_ADDR <= (others => '0'); + TX_FIFO_RD_ADDR <= (others => '0'); + TX_FIFO_EMPTY <= '1'; + TX_FIFO_FULL <= '0'; + + elsif TX_ENABLE = '1' and rising_edge(clk) then + + TX_INTR <= '0'; + + -- If CPU writes data, load into FIFO or direct into TX Data register. + -- + if CS = '1' and WREN = '1' and ADDR = "00" then + -- Store data in FIFO if enabled and not full. + -- + if TX_ENABLE_FIFO = '1' then + if TX_FULL_V = '0' then + TX_FIFO(to_integer(TX_FIFO_WR_ADDR)) <= DATA_IN(7 downto 0); + TX_FIFO_WR_ADDR<= TX_FIFO_WR_ADDR + 1; + else + TX_OVERRUN <= '1'; + end if; + else + -- Else load TX Data register with data. + if TX_DATA_LOADED = '0' then + TX_DATA <= DATA_IN(7 downto 0); + TX_DATA_LOADED <= '1'; + else + TX_OVERRUN <= '1'; + end if; + end if; + end if; + + -- If FIFO enabled, pop the next byte into the TX holding register. + if TX_ENABLE_FIFO = '1' and TX_DATA_LOADED = '0' and TX_EMPTY_V = '0' then + TX_DATA <= TX_FIFO(to_integer(TX_FIFO_RD_ADDR)); + TX_FIFO_RD_ADDR <= TX_FIFO_RD_ADDR + 1; + TX_DATA_LOADED <= '1'; + end if; + + -- TX state machine, serialise the TX buffer. + case TX_STATE is + when idle => + -- If data loaded into the TX holding register and we are at idle (ie last byte transmitted), + -- load into the transmit buffer and commence transmission. + -- + if TX_DATA_LOADED = '1' then + TX_BUFFER <="0111111111" & TX_DATA; -- marker bit + data + TX_STATE <=bits; + TX_BUSY <='1'; + TXD <='0'; -- Start bit + TX_DATA_LOADED <= '0'; + end if; + when bits => + if TX_CLOCK='1' then + txd <= TX_BUFFER(0); + TX_BUFFER <= '0' & TX_BUFFER(17 downto 1); + + if TX_BUFFER(8) = '0' then -- Marker bit has reached bit 8 + TX_STATE <= idle; + TX_BUSY <= '0'; + + -- Interrupt if there is no data loaded into holding register, either from fifo or direct. + if TX_DATA_LOADED = '0' then + TX_INTR<= '1'; + end if; + end if; + end if; + when others => + TX_STATE <=idle; + end case; + end if; + + -- Put variables onto external signals. + TX_FIFO_EMPTY <= TX_EMPTY_V; + TX_FIFO_FULL <= TX_FULL_V; + + -- Put internal interrupt status onto bus. + TXINTR <= TX_INTR; + end process; + + -- Process to pack the data and status onto a buffer ready to be read by the CPU. + -- + process(ADDR, RX_FIFO_EMPTY, RX_FIFO_FULL, RX_DATA_READY, RX_OVERRUN, RX_INTR, RX_ENABLE_FIFO, RX_ENABLE, RX_RESET, + TX_FIFO_EMPTY, TX_FIFO_FULL, TX_BUSY, TX_DATA_LOADED, TX_OVERRUN, TX_INTR, TX_ENABLE_FIFO, TX_ENABLE, TX_RESET, + TX_CLOCK_DIVISOR, RX_CLOCK_DIVISOR, RX_DATA, RX_FIFO_RD_ADDR, RX_FIFO_WR_ADDR, TX_FIFO_RD_ADDR, TX_FIFO_WR_ADDR) + begin + case ADDR is + when "00" => + DATA_OUT <= X"000000" & RX_DATA; + + -- Status. + when "01" => + DATA_OUT <= (others => '0'); + DATA_OUT(0) <= RX_FIFO_EMPTY; -- RX Fifo empty = 1 + DATA_OUT(1) <= RX_FIFO_FULL; -- RX Fifo full = 1 + DATA_OUT(2) <= RX_DATA_READY; -- RX Byte received in holding register = 1 + DATA_OUT(3) <= RX_OVERRUN; -- RX received next data before last was read = 1 + DATA_OUT(4) <= RX_INTR; -- RX Interrupt = 1 + DATA_OUT(5) <= RX_ENABLE_FIFO; -- RX Fifo enabled = 1 + DATA_OUT(6) <= RX_ENABLE; -- RX enabled = 1 + DATA_OUT(7) <= RX_RESET; -- RX is in reset = 1 + -- TX Shadow copy, non invasive. + DATA_OUT(16+0) <= TX_FIFO_EMPTY; -- TX Idle = 1 + DATA_OUT(16+1) <= TX_FIFO_FULL; -- TX Fifo full = 1 + DATA_OUT(16+2) <= TX_BUSY; -- TX Busy serialising = 1 + DATA_OUT(16+3) <= TX_DATA_LOADED; -- TX data loaded into holding register = 1 + DATA_OUT(16+4) <= TX_OVERRUN; -- TX written to when last byte not sent or fifo full. + DATA_OUT(16+5) <= TX_INTR; -- TX Interrupt = 1 + DATA_OUT(16+6) <= TX_ENABLE_FIFO; -- TX Fifo enabled = 1 + DATA_OUT(16+7) <= TX_ENABLE; -- TX enabled = 1 + DATA_OUT(16+8) <= TX_RESET; -- TX is in reset = 1 + + -- FIFO Status. + when "10" => + DATA_OUT <= (others => '0'); + DATA_OUT( RX_FIFO_BIT_DEPTH-1 downto 0) <= std_logic_vector(RX_FIFO_WR_ADDR - RX_FIFO_RD_ADDR); + DATA_OUT(16+TX_FIFO_BIT_DEPTH-1 downto 16) <= std_logic_vector(TX_FIFO_WR_ADDR - TX_FIFO_RD_ADDR); + + -- System clock frequency. + when "11" => + DATA_OUT <= std_logic_vector(to_unsigned(BAUDCLK_FREQUENCY, wordSize)); + end case; + end process; + + -- Write process. Accept data from the CPU and program the unit accordingly. + process(CLK,RESET) + begin + if RESET='1' then + RX_CLOCK_DIVISOR <= X"043D"; -- Default 115200 assuming 100MHz clock. + TX_CLOCK_DIVISOR <= X"043D"; + RX_ENABLE <= '1'; + TX_ENABLE <= '1'; + RX_ENABLE_FIFO <= '1'; + TX_ENABLE_FIFO <= '1'; + RX_RESET <= '1'; + TX_RESET <= '1'; + + elsif rising_edge(CLK) then + RX_RESET <= '0'; + TX_RESET <= '0'; + if CS = '1' and WREN = '1' then + case ADDR is + -- Data, written direct to fifo or TX unit. + when "00" => + + -- RX/TX Control + when "01" => -- RX CTL + RX_ENABLE <= DATA_IN(0); + RX_ENABLE_FIFO <= DATA_IN(1); + RX_RESET <= DATA_IN(2); + -- + TX_ENABLE <= DATA_IN(16+0); + TX_ENABLE_FIFO <= DATA_IN(16+1); + TX_RESET <= DATA_IN(16+2); + + -- Unused + when "10" => + + -- Baud Rate Generate setup. + when "11" => + RX_CLOCK_DIVISOR <= unsigned(DATA_IN(15 downto 0)); + TX_CLOCK_DIVISOR <= unsigned(DATA_IN(31 downto 16)); + RX_RESET <= '1'; + TX_RESET <= '1'; + end case; + end if; + end if; + end process; + +end architecture; diff --git a/zpu/zpu_soc.vhd b/zpu/zpu_soc.vhd new file mode 100644 index 0000000..d1209b2 --- /dev/null +++ b/zpu/zpu_soc.vhd @@ -0,0 +1,2333 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: zpu_soc.vhd +-- Created: January 2019 +-- Author(s): Philip Smart +-- Description: ZPU System On a Chip +-- This module contains the System on a Chip definition for the ZPU. +-- ItÅ› purpose is to provide a functional eco-system around the ZPU to actually perform +-- real tasks. As a basic, boot and stack RAM, UART I/O and Timers are needed to at least +-- present a monitor via UART for interaction. Upon this can be added an SD card for +-- disk storage using the Fat FileSystem, SPI etc. Also, as the Wishbone interface is +-- used in the Evo CPU, any number of 3rd party device IP Cores can be added relatively +-- easily. +-- +-- Credits: +-- Copyright: (c) 2018 Philip Smart +-- +-- History: January 2019 - Initial creation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +use work.zpu_soc_pkg.all; +use work.zpu_pkg.all; + +entity zpu_soc is + generic ( + SYSCLK_FREQUENCY : integer := SYSTEM_FREQUENCY -- System clock frequency + ); + port ( + -- Global Control -- + SYSCLK : in std_logic; -- System clock, running at frequency indicated in SYSCLK_FREQUENCY + MEMCLK : in std_logic; -- Memory clock, running at twice frequency indicated in SYSCLK_FREQUENCY + RESET_IN : in std_logic; + + -- UART 0 & 1 + UART_RX_0 : in std_logic; + UART_TX_0 : out std_logic; + UART_RX_1 : in std_logic; + UART_TX_1 : out std_logic; + + -- SPI signals + SPI_MISO : in std_logic := '1'; -- Allow the SPI interface not to be plumbed in. + SPI_MOSI : out std_logic; + SPI_CLK : out std_logic; + SPI_CS : out std_logic; + + -- SD Card (SPI) signals + SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0) := (others => '1'); + SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0); + + -- PS/2 signals + PS2K_CLK_IN : in std_logic := '1'; + PS2K_DAT_IN : in std_logic := '1'; + PS2K_CLK_OUT : out std_logic; + PS2K_DAT_OUT : out std_logic; + PS2M_CLK_IN : in std_logic := '1'; + PS2M_DAT_IN : in std_logic := '1'; + PS2M_CLK_OUT : out std_logic; + PS2M_DAT_OUT : out std_logic; + + -- I²C signals + I2C_SCL_IO : inout std_logic; + I2C_SDA_IO : inout std_logic; + + -- IOCTL Bus + IOCTL_DOWNLOAD : out std_logic; -- Downloading to FPGA. + IOCTL_UPLOAD : out std_logic; -- Uploading from FPGA. + IOCTL_CLK : out std_logic; -- I/O Clock. + IOCTL_WR : out std_logic; -- Write Enable to FPGA. + IOCTL_RD : out std_logic; -- Read Enable from FPGA. + IOCTL_SENSE : in std_logic; -- Sense to see if HPS accessing ioctl bus. + IOCTL_SELECT : out std_logic; -- Enable IOP control over ioctl bus. + IOCTL_ADDR : out std_logic_vector(24 downto 0); -- Address in FPGA to write into. + IOCTL_DOUT : out std_logic_vector(31 downto 0); -- Data to be written into FPGA. + IOCTL_DIN : in std_logic_vector(31 downto 0); -- Data to be read into HPS. + + -- SDRAM signals + SDRAM_CLK : out std_logic; -- sdram is accessed at 100MHz + SDRAM_CKE : out std_logic; -- clock enable. + SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus + SDRAM_ADDR : out std_logic_vector(12 downto 0); -- 12 bit multiplexed address bus + SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks + SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks + SDRAM_CS_n : out std_logic; -- a single chip select + SDRAM_WE_n : out std_logic; -- write enable + SDRAM_RAS_n : out std_logic; -- row address select + SDRAM_CAS_n : out std_logic; -- columns address select + SDRAM_READY : out std_logic -- sd ready. + + -- DDR2 DRAM + --DDR2_ADDR : out std_logic_vector(13 downto 0); -- 14 bit multiplexed address bus + --DDR2_DQ : inout std_logic_vector(63 downto 0); -- 64 bit bidirectional data bus + --DDR2_DQS : inout std_logic_vector(7 downto 0); -- 8 bit bidirectional data bus + --DDR2_DQM : out std_logic_vector(17 downto 0); -- eight byte masks + --DDR2_ODT : out std_logic_vector(1 downto 0); -- 14 bit multiplexed address bus + --DDR2_BA : out std_logic_vector(2 downto 0); -- 8 banks + --DDR2_CS : out std_logic_vector(1 downto 0); -- 2 chip selects. + --DDR2_WE : out std_logic; -- write enable + --DDR2_RAS : out std_logic; -- row address select + --DDR2_CAS : out std_logic; -- columns address select + --DDR2_CKE : out std_logic_vector(1 downto 0); -- 2 clock enable. + --DDR2_CLK : out std_logic_vector(1 downto 0) -- 2 clocks. +); +end entity; + +architecture rtl of zpu_soc is + + -- FSM States for the SD card to interface with the controller. + type SDStateType is + ( + SD_STATE_IDLE, + SD_STATE_RESET, + SD_STATE_RESET_1, + SD_STATE_WRITE, + SD_STATE_WRITE_1, + SD_STATE_WRITE_2, + SD_STATE_READ, + SD_STATE_READ_1, + SD_STATE_READ_2 + ); + + -- Reset processing. + signal RESET_n : std_logic := '0'; + signal RESET_COUNTER : unsigned(15 downto 0); + signal RESET_COUNTER_RX : unsigned(15 downto 0); + + -- Millisecond counter + signal MICROSEC_DOWN_COUNTER : unsigned(23 downto 0); -- Allow for 16 seconds delay. + signal MILLISEC_DOWN_COUNTER : unsigned(17 downto 0); -- Allow for 262 seconds delay. + signal MILLISEC_UP_COUNTER : unsigned(31 downto 0); -- Up counter allowing for 49 days count in milliseconds. + signal SECOND_DOWN_COUNTER : unsigned(11 downto 0); -- Allow for 1 hour in seconds delay. + signal MICROSEC_DOWN_TICK : integer range 0 to 150; -- Independent tick register to ensure down counter is accurate. + signal MILLISEC_DOWN_TICK : integer range 0 to 150*1000; -- Independent tick register to ensure down counter is accurate. + signal SECOND_DOWN_TICK : integer range 0 to 150*1000000; -- Independent tick register to ensure down counter is accurate. + signal MILLISEC_UP_TICK : integer range 0 to 150*1000; -- Independent tick register to ensure up counter is accurate. + signal MICROSEC_DOWN_INTR : std_logic; -- Interrupt when counter reaches 0. + signal MICROSEC_DOWN_INTR_EN : std_logic; -- Interrupt enable for microsecond down counter. + signal MILLISEC_DOWN_INTR : std_logic; -- Interrupt when counter reaches 0. + signal MILLISEC_DOWN_INTR_EN : std_logic; -- Interrupt enable for millisecond down counter. + signal SECOND_DOWN_INTR : std_logic; -- Interrupt when counter reaches 0. + signal SECOND_DOWN_INTR_EN : std_logic; -- Interrupt enable for second down counter. + signal RTC_MICROSEC_TICK : integer range 0 to 150; -- Allow for frequencies upto 150MHz. + signal RTC_MICROSEC_COUNTER : integer range 0 to 1000; -- Real Time Clock counters. + signal RTC_MILLISEC_COUNTER : integer range 0 to 1000; + signal RTC_SECOND_COUNTER : integer range 0 to 60; + signal RTC_MINUTE_COUNTER : integer range 0 to 60; + signal RTC_HOUR_COUNTER : integer range 0 to 24; + signal RTC_DAY_COUNTER : integer range 1 to 32; + signal RTC_MONTH_COUNTER : integer range 1 to 13; + signal RTC_YEAR_COUNTER : integer range 0 to 4095; + signal RTC_TICK_HALT : std_logic; + + -- Timer register block signals + signal TIMER_REG_REQ : std_logic; + signal TIMER1_TICK : std_logic; + + -- SPI Clock counter + signal SPI_TICK : unsigned(8 downto 0); + signal SPICLK_IN : std_logic; + signal SPI_FAST : std_logic; + + -- SPI signals + signal HOST_TO_SPI : std_logic_vector(7 downto 0); + signal SPI_TO_HOST : std_logic_vector(31 downto 0); + signal SPI_WIDE : std_logic; + signal SPI_TRIGGER : std_logic; + signal SPI_BUSY : std_logic; + signal SPI_ACTIVE : std_logic; + + -- SD Card signals + type SDAddrArray is array(natural range 0 to SOC_SD_DEVICES-1) of std_logic_vector(WORD_32BIT_RANGE); + type SDDataArray is array(natural range 0 to SOC_SD_DEVICES-1) of std_logic_vector(7 downto 0); + type SDErrorArray is array(natural range 0 to SOC_SD_DEVICES-1) of std_logic_vector(15 downto 0); + -- + signal SD_RESET : std_logic_vector(SOC_SD_DEVICES-1 downto 0); -- active-high, synchronous reset. + signal SD_RD : std_logic_vector(SOC_SD_DEVICES-1 downto 0); -- active-high read block request. + signal SD_WR : std_logic_vector(SOC_SD_DEVICES-1 downto 0); -- active-high write block request. + signal SD_CONTINUE : std_logic_vector(SOC_SD_DEVICES-1 downto 0); -- If true, inc address and continue R/W. + signal SD_CARD_TYPE : std_logic_vector(SOC_SD_DEVICES-1 downto 0); -- Type of card, 0 = SD, 1 = SDHC + signal SD_ADDR : SDAddrArray; -- Block address. + signal SD_DATA_READ : SDDataArray; -- Data read from block. + signal SD_DATA_WRITE : std_logic_vector(7 downto 0); -- Data byte to write to block. + signal SD_DATA_VALID : std_logic; -- Flag to indicate when data has been received (rx). + signal SD_DATA_REQ : std_logic; -- Flag to indicate when data is valid for tx. + signal SD_CHANNEL : integer range 0 to SOC_SD_DEVICES-1; -- Active channel in the state machine. + signal SD_BUSY : std_logic_vector(SOC_SD_DEVICES-1 downto 0); -- High when controller is busy performing some operation. + signal SD_HNDSHK_IN : std_logic_vector(SOC_SD_DEVICES-1 downto 0); -- High when host has data to give or has taken data. + signal SD_HNDSHK_OUT : std_logic_vector(SOC_SD_DEVICES-1 downto 0); -- High when controller has taken data or has data to give. + signal SD_ERROR : SDErrorArray; -- Card error occurred (1). + signal SD_OVERRUN : std_logic; -- Receive data overrun flag. + signal SD_STATE : SDStateType; -- State machine states. + signal SD_RESET_TIMER : integer range 0 to 100; -- 100ns reset timer, allows for SYSFREQ = 10 .. 100MHz. + + -- UART signals + signal UART0_WR : std_logic; + signal UART0_ADDR : std_logic; + signal UART0_DATA_OUT : std_logic_vector(31 downto 0); + signal UART0_TX_INTR : std_logic; + signal UART0_RX_INTR : std_logic; + signal UART1_WR : std_logic; + signal UART1_ADDR : std_logic; + signal UART1_DATA_OUT : std_logic_vector(31 downto 0); + signal UART1_TX_INTR : std_logic; + signal UART1_RX_INTR : std_logic; + signal UART1_TX : std_logic; + signal UART2_TX : std_logic; + + -- PS2 signals + signal PS2_INT : std_logic; + + -- PS2 Keyboard Signals. + signal KBD_IDLE : std_logic; + signal KBD_RECV : std_logic; + signal KBD_RECV_REG : std_logic; + signal KBD_SEND_BUSY : std_logic; + signal KBD_SEND_TRIGGER : std_logic; + signal KBD_SEND_DONE : std_logic; + signal KBD_SEND_BYTE : std_logic_vector(7 downto 0); + signal KBD_RECV_BYTE : std_logic_vector(10 downto 0); + + -- I²C Signals. + signal SCL_PAD_IN : std_logic; -- i2c clock line input + signal SCL_PAD_OUT : std_logic; -- i2c clock line output + signal SCL_PAD_OE : std_logic; -- i2c clock line output enable, active low + signal SDA_PAD_IN : std_logic; -- i2c data line input + signal SDA_PAD_OUT : std_logic; -- i2c data line output + signal SDA_PAD_OE : std_logic; -- i2c data line output enable, active low +-- signal WB_DATA_READ_I2C : std_logic_vector(WORD_32BIT_RANGE); -- i2c data as 32bit word for placing on WB bus. +-- signal WB_I2C_ACK : std_logic; +-- signal WB_I2C_HALT : std_logic; +-- signal WB_I2C_ERR : std_logic; +-- signal WB_I2C_CS : std_logic; +-- signal WB_I2C_IRQ : std_logic; + + +-- -- Wishbone control signals. +-- signal WB_SDRAM_ACK : std_logic; +-- signal WB_SDRAM_STB : std_logic; +-- signal WB_DATA_READ_SDRAM : std_logic_vector(WORD_32BIT_RANGE); +-- signal WB_SDRAM_SELECT : std_logic; +-- signal WB_SDRAM_WREN : std_logic; + + -- ZPU signals + signal MEM_BUSY : std_logic; + signal IO_WAIT_SD : std_logic; + signal IO_WAIT_SPI : std_logic; + signal IO_WAIT_PS2 : std_logic; + signal IO_WAIT_INTR : std_logic; + signal IO_WAIT_TIMER1 : std_logic; + signal IO_WAIT_IOCTL : std_logic; + signal MEM_DATA_READ : std_logic_vector(WORD_32BIT_RANGE); + signal MEM_DATA_WRITE : std_logic_vector(WORD_32BIT_RANGE); + signal MEM_ADDR : std_logic_vector(ADDR_BIT_RANGE); + signal MEM_WRITE_ENABLE : std_logic; + signal MEM_WRITE_BYTE_ENABLE : std_logic; + signal MEM_WRITE_HWORD_ENABLE : std_logic; + signal MEM_READ_ENABLE : std_logic; + signal MEM_READ_ENABLE_LAST : std_logic; + signal MEM_DATA_READ_INSN : std_logic_vector(WORD_32BIT_RANGE); + signal MEM_ADDR_INSN : std_logic_vector(ADDR_BIT_RANGE); + signal MEM_READ_ENABLE_INSN : std_logic; + signal IO_DATA_READ : std_logic_vector(WORD_32BIT_RANGE); + signal IO_DATA_READ_SPI : std_logic_vector(WORD_32BIT_RANGE); + signal IO_DATA_READ_SD : std_logic_vector(WORD_32BIT_RANGE); + signal IO_DATA_READ_PS2 : std_logic_vector(WORD_32BIT_RANGE); + signal IO_DATA_READ_INTRCTL : std_logic_vector(WORD_32BIT_RANGE); + signal IO_DATA_READ_SOCCFG : std_logic_vector(WORD_32BIT_RANGE); + signal IO_DATA_READ_IOCTL : std_logic_vector(WORD_32BIT_RANGE); + + -- ZPU ROM/BRAM/RAM/Stack signals. + signal MEM_A_WRITE_ENABLE : std_logic; + signal MEM_A_ADDR : std_logic_vector(ADDR_32BIT_RANGE); + signal MEM_A_WRITE : std_logic_vector(WORD_32BIT_RANGE); + signal MEM_B_WRITE_ENABLE : std_logic; + signal MEM_B_ADDR : std_logic_vector(ADDR_32BIT_RANGE); + signal MEM_B_WRITE : std_logic_vector(WORD_32BIT_RANGE); + signal MEM_A_READ : std_logic_vector(WORD_32BIT_RANGE); + signal MEM_B_READ : std_logic_vector(WORD_32BIT_RANGE); + +-- -- Master Wishbone Memory/IO bus interface. +-- signal WB_CLK_I : std_logic; +-- signal WB_RST_I : std_logic; +-- signal WB_ACK_I : std_logic; +-- signal WB_DAT_I : std_logic_vector(WORD_32BIT_RANGE); +-- signal WB_DAT_O : std_logic_vector(WORD_32BIT_RANGE); +-- signal WB_ADR_O : std_logic_vector(ADDR_BIT_RANGE); +-- signal WB_CYC_O : std_logic; +-- signal WB_STB_O : std_logic; +-- signal WB_CTI_O : std_logic_vector(2 downto 0); +-- signal WB_WE_O : std_logic; +-- signal WB_SEL_O : std_logic_vector(WORD_4BYTE_RANGE); +-- signal WB_HALT_I : std_logic; +-- signal WB_ERR_I : std_logic; +-- signal WB_INTA_I : std_logic; + + -- Interrupt signals + signal INT_TRIGGERS : std_logic_vector(SOC_INTR_MAX downto 0); + signal INT_ENABLE : std_logic_vector(SOC_INTR_MAX downto 0); + signal INT_STATUS : std_logic_vector(SOC_INTR_MAX downto 0); + signal INT_REQ : std_logic; + signal INT_TRIGGER : std_logic; + signal INT_ACK : std_logic; + signal INT_DONE : std_logic; + + -- ZPU ROM/BRAM/RAM + signal BRAM_SELECT : std_logic; + signal RAM_SELECT : std_logic; + signal SDRAM_SELECT : std_logic; + signal BRAM_WREN : std_logic; + signal RAM_WREN : std_logic; + signal SDRAM_WREN : std_logic; + signal SDRAM_RDEN : std_logic; + signal SDRAM_MEM_BUSY : std_logic; + signal BRAM_DATA_READ : std_logic_vector(WORD_32BIT_RANGE); + signal RAM_DATA_READ : std_logic_vector(WORD_32BIT_RANGE); + signal SDRAM_DATA_READ : std_logic_vector(WORD_32BIT_RANGE); + + -- IOCTL + signal IOCTL_RDINT : std_logic; + signal IOCTL_WRINT : std_logic; + signal IOCTL_DATA_OUT : std_logic_vector(31 downto 0); + + -- IO Chip selects + signal IO_SELECT : std_logic; -- IO Range 0x7FFFFxxx of devices connected to the ZPU system bus. +-- signal WB_IO_SELECT : std_logic; -- IO Range of the ZPU CPU 0xF00000 .. 0xFFFFFF +-- signal WB_IO_SOC_SELECT : std_logic; -- IO Range used within the SoC for small devices, upto 256 locations per device. 0x1F000xx + signal IO_UART_SELECT : std_logic; -- Uart Range 0xFFFFFAxx + signal IO_INTR_SELECT : std_logic; -- Interrupt Range 0xFFFFFBxx + signal IO_TIMER_SELECT : std_logic; -- Timer Range 0xFFFFFCxx + signal IO_SPI_SELECT : std_logic; -- SPI Range 0xFFFFFDxx + signal IO_PS2_SELECT : std_logic; -- PS2 Range 0xFFFFFExx + signal IOCTL_CS : std_logic; -- 0x800-80F + signal SD_CS : std_logic; -- 0x900-93F + signal UART0_CS : std_logic; -- 0xA00-C0F + signal UART1_CS : std_logic; -- 0xA10-A1F + signal INTR0_CS : std_logic; -- 0xB00-B0F + signal TIMER0_CS : std_logic; -- 0xC00-C0F Millisecond timer. + signal TIMER1_CS : std_logic; -- 0xC10-C1F + signal SPI0_CS : std_logic; -- 0xD00-D0F + signal PS2_CS : std_logic; -- 0xE00-E0F + signal SOCCFG_CS : std_logic; -- 0xF00-F0F + + function to_std_logic(L: boolean) return std_logic is + begin + if L then + return('1'); + else + return('0'); + end if; + end function to_std_logic; +begin + + -- + -- Instantiation + -- + -- Main CPU + ZPUFLEX: if ZPU_FLEX = 1 generate + ZPU0 : zpu_core_flex + generic map ( + IMPL_MULTIPLY => true, + IMPL_COMPARISON_SUB => true, + IMPL_EQBRANCH => true, + IMPL_STOREBH => false, + IMPL_LOADBH => false, + IMPL_CALL => true, + IMPL_SHIFT => true, + IMPL_XOR => true, + CACHE => true, + -- IMPL_EMULATION => minimal, + -- REMAP_STACK => false --true, -- We need to remap the Boot ROM / Stack RAM so we can access SDRAM + CLK_FREQ => SYSCLK_FREQUENCY, + STACK_ADDR => SOC_STACK_ADDR -- Initial stack address on CPU start. + ) + port map ( + clk => SYSCLK, + reset => not RESET_n, + enable => '1', + in_mem_busy => MEM_BUSY, + mem_read => MEM_DATA_READ, + mem_write => MEM_DATA_WRITE, + out_mem_addr => MEM_ADDR, + out_mem_writeEnable => MEM_WRITE_ENABLE, + out_mem_hEnable => MEM_WRITE_HWORD_ENABLE, + out_mem_bEnable => MEM_WRITE_BYTE_ENABLE, + out_mem_readEnable => MEM_READ_ENABLE, + interrupt_request => INT_TRIGGER, + interrupt_ack => INT_ACK, -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + interrupt_done => INT_DONE, -- Interrupt service routine completed/done. + break => open, + debug_txd => UART2_TX, -- Debug serial output. + -- + MEM_A_WRITE_ENABLE => MEM_A_WRITE_ENABLE, + MEM_A_ADDR => MEM_A_ADDR, + MEM_A_WRITE => MEM_A_WRITE, + MEM_B_WRITE_ENABLE => MEM_B_WRITE_ENABLE, + MEM_B_ADDR => MEM_B_ADDR, + MEM_B_WRITE => MEM_B_WRITE, + MEM_A_READ => MEM_A_READ, + MEM_B_READ => MEM_B_READ + ); + end generate; + ZPUSMALL: if ZPU_SMALL = 1 generate + ZPU0 : zpu_core_small + generic map ( + CLK_FREQ => SYSCLK_FREQUENCY, + STACK_ADDR => SOC_STACK_ADDR -- Initial stack address on CPU start. + ) + port map ( + clk => SYSCLK, + areset => not RESET_n, + enable => '1', + in_mem_busy => MEM_BUSY, + mem_read => MEM_DATA_READ, + mem_write => MEM_DATA_WRITE, + out_mem_addr => MEM_ADDR, + out_mem_writeEnable => MEM_WRITE_ENABLE, + out_mem_hEnable => MEM_WRITE_HWORD_ENABLE, + out_mem_bEnable => MEM_WRITE_BYTE_ENABLE, + out_mem_readEnable => MEM_READ_ENABLE, + mem_writeMask => open, + interrupt_request => INT_TRIGGER, + interrupt_ack => INT_ACK, -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + interrupt_done => INT_DONE, -- Interrupt service routine completed/done. + break => open, + debug_txd => UART2_TX, -- Debug serial output. + -- + MEM_A_WRITE_ENABLE => MEM_A_WRITE_ENABLE, + MEM_A_ADDR => MEM_A_ADDR, + MEM_A_WRITE => MEM_A_WRITE, + MEM_B_WRITE_ENABLE => MEM_B_WRITE_ENABLE, + MEM_B_ADDR => MEM_B_ADDR, + MEM_B_WRITE => MEM_B_WRITE, + MEM_A_READ => MEM_A_READ, + MEM_B_READ => MEM_B_READ + ); + end generate; + ZPUMEDIUM: if ZPU_MEDIUM = 1 generate + ZPU0 : zpu_core_medium + generic map ( + CLK_FREQ => SYSCLK_FREQUENCY, + STACK_ADDR => SOC_STACK_ADDR -- Initial stack address on CPU start. + ) + port map ( + clk => SYSCLK, + areset => not RESET_n, + enable => '1', + in_mem_busy => MEM_BUSY, + mem_read => MEM_DATA_READ, + mem_write => MEM_DATA_WRITE, + out_mem_addr => MEM_ADDR, + out_mem_writeEnable => MEM_WRITE_ENABLE, + out_mem_hEnable => MEM_WRITE_HWORD_ENABLE, + out_mem_bEnable => MEM_WRITE_BYTE_ENABLE, + out_mem_readEnable => MEM_READ_ENABLE, + mem_writeMask => open, + interrupt_request => INT_TRIGGER, + interrupt_ack => INT_ACK, -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + interrupt_done => INT_DONE, -- Interrupt service routine completed/done. + break => open, + debug_txd => UART2_TX -- Debug serial output. + ); + end generate; + ZPUEVO: if ZPU_EVO = 1 generate + ZPU0 : zpu_core_evo + generic map ( + -- Optional hardware features to be implemented. + IMPL_HW_BYTE_WRITE => EVO_USE_HW_BYTE_WRITE, -- Enable use of hardware direct byte write rather than read 33bits-modify 8 bits-write 32bits. + IMPL_HW_WORD_WRITE => EVO_USE_HW_WORD_WRITE, -- Enable use of hardware direct byte write rather than read 32bits-modify 16 bits-write 32bits. + IMPL_OPTIMIZE_IM => IMPL_EVO_OPTIMIZE_IM, -- If the instruction cache is enabled, optimise Im instructions to gain speed. + IMPL_USE_INSN_BUS => SOC_IMPL_INSN_BRAM, -- Use a seperate bus to read instruction memory, normally implemented in BRAM. + IMPL_USE_WB_BUS => EVO_USE_WB_BUS, -- Use the wishbone interface in addition to direct access bus. + -- Optional instructions to be implemented in hardware: + IMPL_ASHIFTLEFT => IMPL_EVO_ASHIFTLEFT, -- Arithmetic Shift Left (uses same logic so normally combined with ASHIFTRIGHT and LSHIFTRIGHT). + IMPL_ASHIFTRIGHT => IMPL_EVO_ASHIFTRIGHT, -- Arithmetic Shift Right. + IMPL_CALL => IMPL_EVO_CALL, -- Call to direct address. + IMPL_CALLPCREL => IMPL_EVO_CALLPCREL, -- Call to indirect address (add offset to program counter). + IMPL_DIV => IMPL_EVO_DIV, -- 32bit signed division. + IMPL_EQ => IMPL_EVO_EQ, -- Equality test. + IMPL_EXTENDED_INSN => IMPL_EVO_EXTENDED_INSN, -- Extended multibyte instruction set. + IMPL_FIADD32 => IMPL_EVO_FIADD32, -- Fixed point Q17.15 addition. + IMPL_FIDIV32 => IMPL_EVO_FIDIV32, -- Fixed point Q17.15 division. + IMPL_FIMULT32 => IMPL_EVO_FIMULT32, -- Fixed point Q17.15 multiplication. + IMPL_LOADB => IMPL_EVO_LOADB, -- Load single byte from memory. + IMPL_LOADH => IMPL_EVO_LOADH, -- Load half word (16bit) from memory. + IMPL_LSHIFTRIGHT => IMPL_EVO_LSHIFTRIGHT, -- Logical shift right. + IMPL_MOD => IMPL_EVO_MOD, -- 32bit modulo (remainder after division). + IMPL_MULT => IMPL_EVO_MULT, -- 32bit signed multiplication. + IMPL_NEG => IMPL_EVO_NEG, -- Negate value in TOS. + IMPL_NEQ => IMPL_EVO_NEQ, -- Not equal test. + IMPL_POPPCREL => IMPL_EVO_POPPCREL, -- Pop a value into the Program Counter from a location relative to the Stack Pointer. + IMPL_PUSHSPADD => IMPL_EVO_PUSHSPADD, -- Add a value to the Stack pointer and push it onto the stack. + IMPL_STOREB => IMPL_EVO_STOREB, -- Store/Write a single byte to memory/IO. + IMPL_STOREH => IMPL_EVO_STOREH, -- Store/Write a half word (16bit) to memory/IO. + IMPL_SUB => IMPL_EVO_SUB, -- 32bit signed subtract. + IMPL_XOR => IMPL_EVO_XOR, -- Exclusive or of value in TOS. + -- Size/Control parameters for the optional hardware. + MAX_INSNRAM_SIZE => (2**(SOC_MAX_ADDR_INSN_BRAM_BIT)), -- Maximum size of the optional instruction BRAM on the INSN Bus. + MAX_L1CACHE_BITS => MAX_EVO_L1CACHE_BITS, -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache. + MAX_L2CACHE_BITS => MAX_EVO_L2CACHE_BITS, -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache. + MAX_MXCACHE_BITS => MAX_EVO_MXCACHE_BITS, -- Maximum size of the memory transaction cache governed by the number of bits. + RESET_ADDR_CPU => SOC_RESET_ADDR_CPU, -- Initial start address of the CPU. + START_ADDR_MEM => SOC_START_ADDR_MEM, -- Start address of program memory. + STACK_ADDR => SOC_STACK_ADDR, -- Initial stack address on CPU start. + CLK_FREQ => SYSCLK_FREQUENCY -- System clock frequency. + ) + port map ( + CLK => SYSCLK, + RESET => not RESET_n, + ENABLE => '1', + MEM_BUSY => MEM_BUSY, + MEM_DATA_IN => MEM_DATA_READ, + MEM_DATA_OUT => MEM_DATA_WRITE, + MEM_ADDR => MEM_ADDR, + MEM_WRITE_ENABLE => MEM_WRITE_ENABLE, + MEM_READ_ENABLE => MEM_READ_ENABLE, + MEM_WRITE_BYTE => MEM_WRITE_BYTE_ENABLE, + MEM_WRITE_HWORD => MEM_WRITE_HWORD_ENABLE, + -- Instruction memory path. + MEM_BUSY_INSN => '0', + MEM_DATA_IN_INSN => MEM_DATA_READ_INSN, + MEM_ADDR_INSN => MEM_ADDR_INSN, + MEM_READ_ENABLE_INSN => MEM_READ_ENABLE_INSN, + -- Master Wishbone Memory/IO bus interface. + WB_CLK_I => '0', -- WB_CLK_I, + WB_RST_I => '0', -- not RESET_n, + WB_ACK_I => '0', -- WB_ACK_I, + WB_DAT_I => (others => '0'), -- WB_DAT_I, + WB_DAT_O => open, -- WB_DAT_O, + WB_ADR_O => open, -- WB_ADR_O, + WB_CYC_O => open, -- WB_CYC_O, + WB_STB_O => open, -- WB_STB_O, + WB_CTI_O => open, -- WB_CTI_O, + WB_WE_O => open, -- WB_WE_O, + WB_SEL_O => open, -- WB_SEL_O, + WB_HALT_I => '0', -- WB_HALT_I, + WB_ERR_I => '0', -- WB_ERR_I, + WB_INTA_I => '0', -- WB_INTA_I, + -- + INT_REQ => INT_TRIGGER, + INT_ACK => INT_ACK, -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + INT_DONE => INT_DONE, -- Interrupt service routine completed/done. + BREAK => open, -- A break instruction encountered. + CONTINUE => '1', -- When break activated, processing stops. Setting CONTINUE to logic 1 resumes processing with next instruction. + DEBUG_TXD => UART2_TX -- Debug serial output. + ); + end generate; + ZPUEVOMIN: if ZPU_EVO_MINIMAL = 1 generate + ZPU0 : zpu_core_evo + generic map ( + -- Optional hardware features to be implemented. + IMPL_HW_BYTE_WRITE => EVO_USE_HW_BYTE_WRITE, -- Enable use of hardware direct byte write rather than read 33bits-modify 8 bits-write 32bits. + IMPL_HW_WORD_WRITE => EVO_USE_HW_WORD_WRITE, -- Enable use of hardware direct byte write rather than read 32bits-modify 16 bits-write 32bits. + IMPL_OPTIMIZE_IM => IMPL_EVOM_OPTIMIZE_IM, -- If the instruction cache is enabled, optimise Im instructions to gain speed. + IMPL_USE_INSN_BUS => SOC_IMPL_INSN_BRAM, -- Use a seperate bus to read instruction memory, normally implemented in BRAM. + IMPL_USE_WB_BUS => EVO_USE_WB_BUS, -- Use the wishbone interface in addition to direct access bus. + -- Optional instructions to be implemented in hardware: + IMPL_ASHIFTLEFT => IMPL_EVOM_ASHIFTLEFT, -- Arithmetic Shift Left (uses same logic so normally combined with ASHIFTRIGHT and LSHIFTRIGHT). + IMPL_ASHIFTRIGHT => IMPL_EVOM_ASHIFTRIGHT, -- Arithmetic Shift Right. + IMPL_CALL => IMPL_EVOM_CALL, -- Call to direct address. + IMPL_CALLPCREL => IMPL_EVOM_CALLPCREL, -- Call to indirect address (add offset to program counter). + IMPL_DIV => IMPL_EVOM_DIV, -- 32bit signed division. + IMPL_EQ => IMPL_EVOM_EQ, -- Equality test. + IMPL_EXTENDED_INSN => IMPL_EVOM_EXTENDED_INSN, -- Extended multibyte instruction set. + IMPL_FIADD32 => IMPL_EVOM_FIADD32, -- Fixed point Q17.15 addition. + IMPL_FIDIV32 => IMPL_EVOM_FIDIV32, -- Fixed point Q17.15 division. + IMPL_FIMULT32 => IMPL_EVOM_FIMULT32, -- Fixed point Q17.15 multiplication. + IMPL_LOADB => IMPL_EVOM_LOADB, -- Load single byte from memory. + IMPL_LOADH => IMPL_EVOM_LOADH, -- Load half word (16bit) from memory. + IMPL_LSHIFTRIGHT => IMPL_EVOM_LSHIFTRIGHT, -- Logical shift right. + IMPL_MOD => IMPL_EVOM_MOD, -- 32bit modulo (remainder after division). + IMPL_MULT => IMPL_EVOM_MULT, -- 32bit signed multiplication. + IMPL_NEG => IMPL_EVOM_NEG, -- Negate value in TOS. + IMPL_NEQ => IMPL_EVOM_NEQ, -- Not equal test. + IMPL_POPPCREL => IMPL_EVOM_POPPCREL, -- Pop a value into the Program Counter from a location relative to the Stack Pointer. + IMPL_PUSHSPADD => IMPL_EVOM_PUSHSPADD, -- Add a value to the Stack pointer and push it onto the stack. + IMPL_STOREB => IMPL_EVOM_STOREB, -- Store/Write a single byte to memory/IO. + IMPL_STOREH => IMPL_EVOM_STOREH, -- Store/Write a half word (16bit) to memory/IO. + IMPL_SUB => IMPL_EVOM_SUB, -- 32bit signed subtract. + IMPL_XOR => IMPL_EVOM_XOR, -- Exclusive or of value in TOS. + -- Size/Control parameters for the optional hardware. + MAX_INSNRAM_SIZE => (2**(SOC_MAX_ADDR_INSN_BRAM_BIT)), -- Maximum size of the optional instruction BRAM on the INSN Bus. + MAX_L1CACHE_BITS => MAX_EVO_MIN_L1CACHE_BITS, -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache. + MAX_L2CACHE_BITS => MAX_EVO_MIN_L2CACHE_BITS, -- Maximum size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache. + MAX_MXCACHE_BITS => MAX_EVO_MIN_MXCACHE_BITS, -- Maximum size of the memory transaction cache governed by the number of bits. + RESET_ADDR_CPU => SOC_RESET_ADDR_CPU, -- Initial start address of the CPU. + START_ADDR_MEM => SOC_START_ADDR_MEM, -- Start address of program memory. + STACK_ADDR => SOC_STACK_ADDR, -- Initial stack address on CPU start. + CLK_FREQ => SYSCLK_FREQUENCY -- System clock frequency. + ) + port map ( + CLK => SYSCLK, + RESET => not RESET_n, + ENABLE => '1', + MEM_BUSY => MEM_BUSY, + MEM_DATA_IN => MEM_DATA_READ, + MEM_DATA_OUT => MEM_DATA_WRITE, + MEM_ADDR => MEM_ADDR, + MEM_WRITE_ENABLE => MEM_WRITE_ENABLE, + MEM_READ_ENABLE => MEM_READ_ENABLE, + MEM_WRITE_BYTE => MEM_WRITE_BYTE_ENABLE, + MEM_WRITE_HWORD => MEM_WRITE_HWORD_ENABLE, + -- Instruction memory path. + MEM_BUSY_INSN => '0', + MEM_DATA_IN_INSN => MEM_DATA_READ_INSN, + MEM_ADDR_INSN => MEM_ADDR_INSN, + MEM_READ_ENABLE_INSN => MEM_READ_ENABLE_INSN, + -- Master Wishbone Memory/IO bus interface. + WB_CLK_I => '0', -- WB_CLK_I, + WB_RST_I => '0', -- not RESET_n, + WB_ACK_I => '0', -- WB_ACK_I, + WB_DAT_I => (others => '0'), -- WB_DAT_I, + WB_DAT_O => open, -- WB_DAT_O, + WB_ADR_O => open, -- WB_ADR_O, + WB_CYC_O => open, -- WB_CYC_O, + WB_STB_O => open, -- WB_STB_O, + WB_CTI_O => open, -- WB_CTI_O, + WB_WE_O => open, -- WB_WE_O, + WB_SEL_O => open, -- WB_SEL_O, + WB_HALT_I => '0', -- WB_HALT_I, + WB_ERR_I => '0', -- WB_ERR_I, + WB_INTA_I => '0', -- WB_INTA_I, + -- + INT_REQ => INT_TRIGGER, + INT_ACK => INT_ACK, -- Interrupt acknowledge, ZPU has entered Interrupt Service Routine. + INT_DONE => INT_DONE, -- Interrupt service routine completed/done. + BREAK => open, -- A break instruction encountered. + CONTINUE => '1', -- When break activated, processing stops. Setting CONTINUE to logic 1 resumes processing with next instruction. + DEBUG_TXD => UART2_TX -- Debug serial output. + ); + end generate; + + -- ROM + ZPUROMSMALL : if (ZPU_SMALL = 1 or ZPU_FLEX = 1) and SOC_IMPL_BRAM = true generate + ZPUROM : entity work.BootROM + port map ( + clk => SYSCLK, + memAWriteEnable => MEM_A_WRITE_ENABLE, + memAAddr => MEM_A_ADDR(ADDR_32BIT_BRAM_RANGE), + memAWrite => MEM_A_WRITE, + memBWriteEnable => MEM_B_WRITE_ENABLE, + memBAddr => MEM_B_ADDR(ADDR_32BIT_BRAM_RANGE), + memBWrite => MEM_B_WRITE, + memARead => MEM_A_READ, + memBRead => MEM_B_READ + ); + end generate; + + -- This block should provide byte addressable dual port BRAM for the Flex but for some reason Quartus quarks when compiling when the B port is used for writes. Not sure why + -- but needs revisiting as it will gain some performance improvements for the flex core. + --ZPUROMFLEX : if ZPU_FLEX = 1 and SOC_IMPL_BRAM = true generate + -- ZPUROM : entity work.DualPortBootBRAM + -- generic map ( + -- addrbits => SOC_MAX_ADDR_BRAM_BIT + -- ) + -- port map ( + -- clk => SYSCLK, + -- memAAddr => MEM_A_ADDR(17 downto 2), + -- memAWriteEnable => MEM_A_WRITE_ENABLE, + -- memAWriteByte => MEM_WRITE_BYTE_ENABLE, + -- memAWriteHalfWord => MEM_WRITE_HWORD_ENABLE, + -- memAWrite => MEM_A_WRITE, + -- memARead => MEM_A_READ, + + -- memBAddr => MEM_B_ADDR(ADDR_32BIT_BRAM_RANGE), + -- memBWrite => MEM_B_WRITE, + -- memBWriteEnable => MEM_B_WRITE_ENABLE, + -- memBRead => MEM_B_READ + -- ); + --end generate; + + ZPUROMMEDIUM : if ZPU_MEDIUM = 1 and SOC_IMPL_BRAM = true generate + ZPUROM : entity work.BootROM + port map ( + clk => SYSCLK, + memAWriteEnable => BRAM_WREN, + memAAddr => MEM_ADDR(ADDR_32BIT_BRAM_RANGE), + memAWrite => MEM_DATA_WRITE, + memBWriteEnable => '0', + memBAddr => MEM_ADDR(ADDR_32BIT_BRAM_RANGE), + memBWrite => (others => '0'), + memARead => open, + memBRead => BRAM_DATA_READ + ); + end generate; + + -- Evo system BRAM, dual port to allow for seperate instruction bus read. + ZPUDPBRAMEVO : if (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and SOC_IMPL_INSN_BRAM = true and SOC_IMPL_BRAM = true generate + ZPUBRAM : entity work.DualPortBootBRAM + generic map ( + addrbits => SOC_MAX_ADDR_BRAM_BIT + ) + port map ( + clk => SYSCLK, + memAAddr => MEM_ADDR(ADDR_BIT_BRAM_RANGE), + memAWriteEnable => BRAM_WREN, + memAWriteByte => MEM_WRITE_BYTE_ENABLE, + memAWriteHalfWord => MEM_WRITE_HWORD_ENABLE, + memAWrite => MEM_DATA_WRITE, + memARead => BRAM_DATA_READ, + + memBAddr => MEM_ADDR_INSN(ADDR_32BIT_BRAM_RANGE), + memBWrite => (others => '0'), + memBWriteEnable => '0', + memBRead => MEM_DATA_READ_INSN + ); + end generate; + -- Evo system BRAM, single port as no seperate instruction bus configured. + ZPUBRAMEVO : if (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and SOC_IMPL_INSN_BRAM = false and SOC_IMPL_BRAM = true generate + ZPUBRAM : entity work.SinglePortBootBRAM + generic map ( + addrbits => SOC_MAX_ADDR_BRAM_BIT + ) + port map ( + clk => SYSCLK, + memAAddr => MEM_ADDR(ADDR_BIT_BRAM_RANGE), + memAWriteEnable => BRAM_WREN, + memAWriteByte => MEM_WRITE_BYTE_ENABLE, + memAWriteHalfWord => MEM_WRITE_HWORD_ENABLE, + memAWrite => MEM_DATA_WRITE, + memARead => BRAM_DATA_READ + ); + end generate; + + -- Evo RAM, a seperate block of RAM created in BRAM in addition to the main system BRAM, generally used for applications and termed RAM in this module. + ZPURAMEVO : if (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and SOC_IMPL_RAM = true generate + ZPURAM : entity work.SinglePortBRAM + generic map ( + addrbits => SOC_MAX_ADDR_RAM_BIT + ) + port map ( + clk => SYSCLK, + memAAddr => MEM_ADDR(ADDR_BIT_RAM_RANGE), + memAWriteEnable => RAM_WREN, + memAWriteByte => MEM_WRITE_BYTE_ENABLE, + memAWriteHalfWord => MEM_WRITE_HWORD_ENABLE, + memAWrite => MEM_DATA_WRITE, + memARead => RAM_DATA_READ + ); + + -- RAM Range SOC_ADDR_RAM_START) -> SOC_ADDR_RAM_END + RAM_SELECT <= '1' when (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and (MEM_ADDR >= std_logic_vector(to_unsigned(SOC_ADDR_RAM_START, MEM_ADDR'LENGTH)) and MEM_ADDR < std_logic_vector(to_unsigned(SOC_ADDR_RAM_END, MEM_ADDR'LENGTH))) + else '0'; + + -- Enable write to RAM when selected and CPU in write state. + RAM_WREN <= '1' when RAM_SELECT = '1' and MEM_WRITE_ENABLE = '1' + else '0'; + end generate; + + -- SDRAM over System bus. + ZPUSDRAMEVO : if (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1 or ZPU_MEDIUM = 1) and SOC_IMPL_SDRAM = true and (BOARD_QMV = true or BOARD_CYC1000 = true) generate + + ZPUSDRAM : entity work.SDRAM + generic map ( + SDRAM_ROWS => SOC_SDRAM_ROWS, -- Number of Rows in the SDRAM. + SDRAM_COLUMNS => SOC_SDRAM_COLUMNS, -- Number of Columns in an SDRAM page (ie. 1 row). + SDRAM_BANKS => SOC_SDRAM_BANKS, -- Number of banks in the SDRAM. + SDRAM_DATAWIDTH => SOC_SDRAM_DATAWIDTH, -- Data width of SDRAM chip (ie. 16, 32). + SDRAM_CLK_FREQ => SOC_SDRAM_CLK_FREQ, -- Frequency of SDRAM clock in Hertz. + SDRAM_tRCD => SOC_SDRAM_tRCD, -- tRCD - RAS to CAS minimum period (in ns), ie. 20ns -> 2 cycles@100MHz + SDRAM_tRP => SOC_SDRAM_tRP, -- tRP - Precharge delay, min time for a precharge command to complete (in ns), ie. 15ns -> 2 cycles@100MHz + SDRAM_tRFC => SOC_SDRAM_tRFC, -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns + SDRAM_tREF => SOC_SDRAM_tREF -- tREF - period of time a complete refresh of all rows is made within (in ms). + ) + port map ( + -- SDRAM Interface + SDRAM_CLK => MEMCLK, -- sdram clock running at an offset from system clock. + SDRAM_RST => not RESET_n, -- reset the sdram controller. + SDRAM_CKE => SDRAM_CKE, -- clock enable. + SDRAM_DQ => SDRAM_DQ, -- 16 bit bidirectional data bus + SDRAM_ADDR => SDRAM_ADDR, -- 12 bit multiplexed address bus + SDRAM_DQM => SDRAM_DQM, -- two byte masks + SDRAM_BA => SDRAM_BA, -- two banks + SDRAM_CS_n => SDRAM_CS_n, -- a single chip select + SDRAM_WE_n => SDRAM_WE_n, -- write enable + SDRAM_RAS_n => SDRAM_RAS_n, -- row address select + SDRAM_CAS_n => SDRAM_CAS_n, -- columns address select + SDRAM_READY => SDRAM_READY, -- sd ready. + + -- CPU Interface + CLK => SYSCLK, -- System master clock + RESET => not RESET_n, -- high active sync reset + ADDR => MEM_ADDR(ADDR_BIT_SDRAM_RANGE), + DATA_IN => MEM_DATA_WRITE, -- write data + DATA_OUT => SDRAM_DATA_READ, -- read data + WRITE_BYTE => MEM_WRITE_BYTE_ENABLE, -- Write a single byte. + WRITE_HWORD => MEM_WRITE_HWORD_ENABLE, -- Write a 16 bit word. + CS => SDRAM_SELECT, -- Chip Select. + WREN => MEM_WRITE_ENABLE, --SDRAM_WREN, -- Write enable. + RDEN => MEM_READ_ENABLE, --SDRAM_RDEN, -- Read enable. + BUSY => SDRAM_MEM_BUSY + ); + + -- SDRAM clock based on system clock. + SDRAM_CLK <= MEMCLK; + + -- RAM Range SOC_ADDR_SDRAM_START) -> SOC_ADDR_SDRAM_END + SDRAM_SELECT <= '1' when (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1 or ZPU_MEDIUM = 1) and (MEM_ADDR >= std_logic_vector(to_unsigned(SOC_ADDR_SDRAM_START, MEM_ADDR'LENGTH)) and MEM_ADDR < std_logic_vector(to_unsigned(SOC_ADDR_SDRAM_END, MEM_ADDR'LENGTH))) + --SDRAM_SELECT <= '1' when (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and (MEM_ADDR >= std_logic_vector(to_unsigned(SOC_ADDR_RAM_START, MEM_ADDR'LENGTH)) and MEM_ADDR < std_logic_vector(to_unsigned(SOC_ADDR_RAM_END, MEM_ADDR'LENGTH))) + else '0'; + end generate; + + -- Force the CPU to wait when slower memory/IO is accessed and it cant deliver an immediate result. + MEM_BUSY <= '1' when (UART0_CS = '1' or UART1_CS = '1' or TIMER0_CS = '1') and MEM_READ_ENABLE_LAST = '0' and MEM_READ_ENABLE = '1' + else + '1' when SOC_IMPL_SDRAM = true and (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1 or ZPU_MEDIUM = 1) and SDRAM_MEM_BUSY = '1' and (BOARD_QMV = true or BOARD_CYC1000 = true) + else + -- '1' when BRAM_SELECT = '1' and (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and (MEM_READ_ENABLE = '1') + -- else + -- '1' when IO_SELECT = '1' and (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and (MEM_READ_ENABLE = '1') + -- else + '1' when SOC_IMPL_SD = true and SD_CS = '1' and MEM_READ_ENABLE_LAST = '0' and MEM_READ_ENABLE = '1' + else + '1' when SOC_IMPL_SPI = true and SPI_CS = '1' and MEM_READ_ENABLE_LAST = '0' and MEM_READ_ENABLE = '1' and IO_WAIT_SPI = '1' + else + '1' when SOC_IMPL_PS2 = true and PS2_CS = '1' and MEM_READ_ENABLE_LAST = '0' and MEM_READ_ENABLE = '1' and IO_WAIT_PS2 = '1' + else + '1' when SOC_IMPL_INTRCTL = true and INTR0_CS = '1' and MEM_READ_ENABLE_LAST = '0' and MEM_READ_ENABLE = '1' and IO_WAIT_INTR = '1' + else + '1' when SOC_IMPL_TIMER1 = true and TIMER1_CS = '1' and MEM_READ_ENABLE_LAST = '0' and MEM_READ_ENABLE = '1' and IO_WAIT_TIMER1 = '1' + else + '1' when SOC_IMPL_IOCTL = true and IOCTL_CS = '1' and MEM_READ_ENABLE_LAST = '0' and MEM_READ_ENABLE = '1' and IO_WAIT_IOCTL = '1' and (BOARD_CYC1000 = true or BOARD_DE10 = true) + else + '1' when SOC_IMPL_SOCCFG = true and SOCCFG_CS = '1' and MEM_READ_ENABLE_LAST = '0' and MEM_READ_ENABLE = '1' + else + '0'; + + -- Select CPU input source, memory or IO. + MEM_DATA_READ <= BRAM_DATA_READ when BRAM_SELECT = '1' + else + RAM_DATA_READ when SOC_IMPL_RAM = true and RAM_SELECT = '1' + else + SDRAM_DATA_READ when SOC_IMPL_SDRAM = true and SDRAM_SELECT = '1' and (BOARD_QMV = true or BOARD_CYC1000 = true) + else + IO_DATA_READ_SD when SOC_IMPL_SD = true and SD_CS = '1' + else + IO_DATA_READ_SPI when SOC_IMPL_SPI = true and SPI0_CS = '1' + else + IO_DATA_READ_PS2 when SOC_IMPL_PS2 = true and PS2_CS = '1' + else + IO_DATA_READ_INTRCTL when SOC_IMPL_INTRCTL = true and INTR0_CS = '1' + else + IO_DATA_READ_SOCCFG when SOC_IMPL_SOCCFG = true and SOCCFG_CS = '1' + else + IO_DATA_READ_IOCTL when SOC_IMPL_IOCTL = true and IOCTL_CS = '1' and (BOARD_CYC1000 = true or BOARD_DE10 = true) + else + IO_DATA_READ when IO_SELECT = '1' + else + (others => '1'); + +-- -- If the wishbone interface is implemented, generate the control and decode logic. +-- WISHBONE_CTRL: if SOC_IMPL_WB = true generate +-- WB_DAT_I <= WB_DATA_READ_SDRAM when (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and SOC_IMPL_WB_SDRAM = true and WB_SDRAM_STB = '1' +-- else +-- X"000000" & WB_DATA_READ_I2C(BYTE_RANGE) when SOC_IMPL_WB_I2C = true and WB_I2C_CS = '1' +-- else +-- (others => '0'); +-- +-- -- Acknowledge is a chain of all enabled device acknowledges as only the addressed device in any given occasion should generate an ACK. +-- WB_ACK_I <= WB_SDRAM_ACK when SOC_IMPL_WB_SDRAM = true and WB_SDRAM_STB = '1' +-- else +-- WB_I2C_ACK when SOC_IMPL_WB_I2C = true and WB_I2C_CS = '1' +-- -- access to an unimplemented area of memory, just ACK as there is nothing to handle the request. +-- else '1'; +-- +-- -- Halt/Wait signal is a chain of all enabled devices requiring additional bus transaction time. +-- WB_HALT_I <= WB_I2C_HALT when SOC_IMPL_WB_I2C = true and WB_I2C_HALT = '1' +-- else '0'; +-- +-- -- Error signal is a chain of all enabled device error condition signals. +-- WB_ERR_I <= WB_I2C_ERR when SOC_IMPL_WB_I2C = true and WB_I2C_ERR = '1' +-- else '0'; +-- +-- -- Interrupt signals are chained with the actual interrupt being stored in the main interrupt controller. +-- WB_INTA_I <= WB_I2C_IRQ when SOC_IMPL_WB_I2C = true and WB_I2C_IRQ = '1' +-- else '0'; +-- +-- -- Like direct I/O, place peripherals in upper range of wishbone address space. +-- WB_IO_SELECT <= '1' when (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and WB_STB_O = '1' and (WB_ADR_O >= std_logic_vector(to_unsigned(SOC_WB_IO_START, WB_ADR_O'LENGTH)) and WB_ADR_O < std_logic_vector(to_unsigned(SOC_WB_IO_END, WB_ADR_O'LENGTH))) +-- else '0'; +-- +-- WB_IO_SOC_SELECT <= WB_IO_SELECT when WB_ADR_O(19 downto 12) = X"00" +-- else '0'; +-- +-- WB_I2C_CS <= '1' when WB_IO_SOC_SELECT = '1' and WB_ADR_O(11 downto 8) = "0000" -- I2C Range 0xF000xx +-- else '0'; +-- +-- WB_CLK_I <= SYSCLK; +-- +-- else generate +-- WB_DAT_I <= (others => '0'); +-- WB_ACK_I <= '0'; +-- WB_HALT_I <= '0'; +-- WB_ERR_I <= '0'; +-- end generate; + + -- Enable write to System BRAM when selected and CPU in write state. + BRAM_WREN <= '1' when (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and MEM_WRITE_ENABLE = '1' and (MEM_ADDR >= std_logic_vector(to_unsigned(SOC_ADDR_BRAM_START, MEM_ADDR'LENGTH)) and MEM_ADDR <= std_logic_vector(to_unsigned(SOC_ADDR_BRAM_END, MEM_ADDR'LENGTH))) + else + '1' when ZPU_MEDIUM = 1 and MEM_WRITE_ENABLE = '1' and MEM_ADDR(ioBit) = '0' and (MEM_ADDR >= std_logic_vector(to_unsigned(SOC_ADDR_BRAM_START, MEM_ADDR'LENGTH)) and MEM_ADDR <= std_logic_vector(to_unsigned(SOC_ADDR_BRAM_END, MEM_ADDR'LENGTH))) + else + '0'; + + -- Were not interested in the mouse, so pass through connection. + PS2M_CLK_OUT <= PS2M_CLK_IN; + PS2M_DAT_OUT <= PS2M_DAT_IN; + + -- Fixed peripheral Decoding. + -- BRAM Range 0x00000000 - (2^SOC_MAX_ADDR_INSN_BRAM_BIT)-1 + BRAM_SELECT <= '1' when (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and (MEM_ADDR >= std_logic_vector(to_unsigned(SOC_ADDR_BRAM_START, MEM_ADDR'LENGTH)) and MEM_ADDR < std_logic_vector(to_unsigned(SOC_ADDR_BRAM_END, MEM_ADDR'LENGTH))) + else + '1' when ZPU_MEDIUM = 1 and (MEM_ADDR >= std_logic_vector(to_unsigned(SOC_ADDR_BRAM_START, MEM_ADDR'LENGTH)) and MEM_ADDR < std_logic_vector(to_unsigned(SOC_ADDR_BRAM_END, MEM_ADDR'LENGTH))) + else + '1' when (ZPU_FLEX = 1 or ZPU_SMALL = 1) and MEM_ADDR(ioBit) = '0' + else '0'; + -- IO Range for EVO CPU + IO_SELECT <= '1' when (ZPU_SMALL = 1 or ZPU_MEDIUM = 1 or ZPU_FLEX = 1) and MEM_ADDR(ioBit) = '1' -- IO Range for Small, Medium and Flex CPU + else + -- '1' when (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and MEM_ADDR(IO_DECODE_RANGE) = std_logic_vector(to_unsigned(255, maxAddrBit - maxIOBit)) and MEM_ADDR(maxIOBit -1 downto 12) = std_logic_vector(to_unsigned(0, maxIOBit-12)) + '1' when (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and ((SOC_IMPL_WB = true and MEM_ADDR(WB_SELECT_BIT) = '0') or SOC_IMPL_WB = false) and MEM_ADDR(IO_DECODE_RANGE) = std_logic_vector(to_unsigned(255, maxAddrBit-WB_ACTIVE - maxIOBit)) and MEM_ADDR(maxIOBit -1 downto 12) = std_logic_vector(to_unsigned(0, maxIOBit-12)) + else '0'; + IO_TIMER_SELECT <= '1' when IO_SELECT = '1' and MEM_ADDR(11 downto 8) = X"C" -- Timer Range 0xFFFFCxx + else '0'; + UART0_CS <= '1' when IO_SELECT = '1' and MEM_ADDR(11 downto 4) = "10100000" -- Uart Range 0xFFFFAxx, 0xA00-C0F + else '0'; + UART1_CS <= '1' when IO_SELECT = '1' and MEM_ADDR(11 downto 4) = "10100001" -- Uart Range 0xFFFFAxx, 0xA10-A1F + else '0'; + TIMER0_CS <= '1' when IO_TIMER_SELECT = '1' and MEM_ADDR(7 downto 6) = "00" -- 0xC00-C3F Millisecond timer. + else '0'; + SD_CS <= '1' when IO_SELECT = '1' and MEM_ADDR(11 downto 7) = "10010" -- 0x900-90F 0xFFFF9xx, 0x900 - 0x90f First SD Card address range + else '0'; + + -- Mux the UART debug channel outputs. DBG1 is from the software controlled UART, DBG2 from the cpu channel. + DEBUGUART: if DEBUG_CPU = true generate + UART_TX_1 <= UART2_TX; + else generate + UART_TX_1 <= UART1_TX; + end generate; + + ------------------------------------------------------------------------------------ + -- Direct Memory I/O devices + ------------------------------------------------------------------------------------ + + TIMER : if SOC_IMPL_TIMER1 = true generate + -- TIMER + TIMER1 : entity work.timer_controller + generic map( + prescale => 1, -- Prescale incoming clock + timers => SOC_TIMER1_COUNTERS + ) + port map ( + clk => SYSCLK, + reset => RESET_n, + + reg_addr_in => MEM_ADDR(7 downto 0), + reg_data_in => MEM_DATA_WRITE, + reg_rw => '0', -- we never read from the timers + reg_req => TIMER_REG_REQ, + + ticks(0) => TIMER1_TICK -- Tick signal is used to trigger an interrupt + ); + + process(SYSCLK, RESET_n) + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if RESET_n='0' then + TIMER_REG_REQ <= '0'; + IO_WAIT_TIMER1 <= '0'; + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(SYSCLK) then + + IO_WAIT_TIMER1 <= '0'; + + -- CPU Write? + if MEM_WRITE_ENABLE = '1' and TIMER1_CS = '1' then + + -- Write to Timer. + TIMER_REG_REQ <= '1'; + + -- IO Read? + elsif MEM_READ_ENABLE = '1' and TIMER1_CS = '1' then + + end if; + end if; -- rising-edge(SYSCLK) + end process; + + TIMER1_CS <= '1' when IO_TIMER_SELECT = '1' and MEM_ADDR(7 downto 6) = "01" -- 0xC40-C7F + else '0'; + else generate + TIMER_REG_REQ <= '0'; + IO_WAIT_TIMER1 <= '0'; + end generate; + + -- PS2 devices + PS2 : if SOC_IMPL_PS2 = true generate + PS2KEYBOARD : entity work.io_ps2_com + generic map ( + clockFilter => 15, + ticksPerUsec => SYSCLK_FREQUENCY/1000000 + ) + port map ( + clk => SYSCLK, + reset => not RESET_n, + ps2_clk_in => PS2K_CLK_IN, + ps2_dat_in => PS2K_DAT_IN, + ps2_clk_out => PS2K_CLK_OUT, + ps2_dat_out => PS2K_DAT_OUT, + + inIdle => open, + sendTrigger => KBD_SEND_TRIGGER, + sendByte => KBD_SEND_BYTE, + sendBusy => KBD_SEND_BUSY, + sendDone => KBD_SEND_DONE, + recvTrigger => KBD_RECV, + recvByte => KBD_RECV_BYTE + ); + + process(SYSCLK, RESET_n) + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if RESET_n='0' then + KBD_SEND_TRIGGER <= '0'; + KBD_RECV_REG <= '0'; + IO_WAIT_PS2 <= '0'; + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(SYSCLK) then + + KBD_SEND_TRIGGER <= '0'; + IO_WAIT_PS2 <= '0'; + + -- CPU Write? + if MEM_WRITE_ENABLE = '1' and PS2_CS = '1' then + + -- Write to PS2 Controller. + KBD_SEND_BYTE <= MEM_DATA_WRITE(7 downto 0); + KBD_SEND_TRIGGER <='1'; + + -- IO Read? + elsif MEM_READ_ENABLE = '1' and PS2_CS = '1' then + + -- Read from PS2. + IO_DATA_READ_PS2 <=(others =>'0'); + IO_DATA_READ_PS2(11 downto 0) <= KBD_RECV_REG & not KBD_SEND_BUSY & KBD_RECV_BYTE(10 downto 1); + KBD_RECV_REG <='0'; + end if; + + -- PS2 interrupt + PS2_INT <= KBD_RECV or KBD_SEND_DONE; + if KBD_RECV='1' then + KBD_RECV_REG <= '1'; -- remains high until cleared by a read + end if; + + end if; -- rising-edge(SYSCLK) + end process; + + PS2_CS <= '1' when IO_SELECT = '1' and MEM_ADDR(11 downto 4) = "11010000" -- PS2 Range 0xFFFFFExx, 0xE00-E0F + else '0'; + else generate + PS2_INT <= '0'; + PS2_CS <= '0'; + KBD_SEND_TRIGGER <= '0'; + KBD_RECV_REG <= '0'; + IO_WAIT_PS2 <= '0'; + end generate; + + -- SPI host + SPI : if SOC_IMPL_SPI = true generate + + SPI0 : entity work.spi_interface + port map( + sysclk => SYSCLK, + reset => RESET_n, + + -- Host interface + SPICLK_IN => SPICLK_IN, + HOST_TO_SPI => HOST_TO_SPI, + SPI_TO_HOST => SPI_TO_HOST, + trigger => SPI_TRIGGER, + busy => SPI_BUSY, + + -- Hardware interface + miso => SPI_MISO, + mosi => SPI_MOSI, + spiclk_out => SPI_CLK + ); + + -- SPI Timer + process(SYSCLK) + begin + if rising_edge(SYSCLK) then + SPICLK_IN <= '0'; + SPI_TICK <= SPI_TICK+1; + if (SPI_FAST='1' and SPI_TICK(5)='1') or SPI_TICK(8)='1' then + SPICLK_IN <= '1'; -- Momentary pulse for SPI host. + SPI_TICK <= '0' & X"00"; + end if; + end if; + end process; + + process(SYSCLK, RESET_n) + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if RESET_n='0' then + SPI_CS <= '1'; + SPI_ACTIVE <= '0'; + IO_WAIT_SPI <= '0'; + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(SYSCLK) then + + SPI_TRIGGER <= '0'; + IO_WAIT_SPI <= '0'; + + -- CPU Write? + if MEM_WRITE_ENABLE = '1' and SPI0_CS = '1' then + + -- Write to the SPI. + case MEM_ADDR(3 downto 2) is + when "00" => -- SPI CS + SPI_CS <= not MEM_DATA_WRITE(0); + SPI_FAST <= MEM_DATA_WRITE(8); + + when "01" => -- SPI Data + SPI_WIDE <='0'; + SPI_TRIGGER <= '1'; + HOST_TO_SPI <= MEM_DATA_WRITE(7 downto 0); + SPI_ACTIVE <= '1'; + IO_WAIT_SPI <= '1'; + + when "10" => -- SPI Pump (32-bit read) + SPI_WIDE <= '1'; + SPI_TRIGGER <= '1'; + HOST_TO_SPI <= MEM_DATA_WRITE(7 downto 0); + SPI_ACTIVE <= '1'; + IO_WAIT_SPI <= '1'; + + when others => + end case; + + -- IO Read? + elsif MEM_READ_ENABLE = '1' and SPI0_CS = '1' then + + -- Read from SPI. + case MEM_ADDR(3 downto 2) is + when "00" => -- SPI CS + IO_DATA_READ_SPI <= (others =>'X'); + IO_DATA_READ_SPI(15) <= SPI_BUSY; + + when "01" => -- SPI Data + SPI_ACTIVE <= '1'; + IO_WAIT_SPI <= '1'; + + when "10" => -- SPI Pump (32-bit read) + SPI_WIDE <= '1'; + SPI_TRIGGER <= '1'; + SPI_ACTIVE <= '1'; + HOST_TO_SPI <= X"FF"; + IO_WAIT_SPI <= '1'; + + when others => + end case; + end if; + + -- SPI cycles + if SPI_ACTIVE='1' then + IO_WAIT_SPI <= SPI_BUSY; + if SPI_BUSY = '0' then + IO_DATA_READ_SPI <= SPI_TO_HOST; + SPI_ACTIVE <= '0'; + end if; + end if; + end if; -- rising-edge(SYSCLK) + end process; + + SPI0_CS <= '1' when IO_SELECT = '1' and MEM_ADDR(11 downto 4) = "11010000" -- SPI Range 0xFFFFFDxx, 0xD00-D0F + else '0'; + else generate + SPI_CS <= '1'; + SPI_ACTIVE <= '0'; + IO_WAIT_SPI <= '0'; + end generate; + + -- SD Card interface. Upto 4 SD Cards can be configured, add an entity for each and set the generics to the values required. + -- The signals are in the form of an array, so device 0 uses signals in array element 0. + SDCARD0: if SOC_IMPL_SD = true and SOC_SD_DEVICES >= 1 generate + + SDCARDS: for I in 0 to SOC_SD_DEVICES-1 generate + SDCARD : entity work.SDCard + generic map + ( + FREQ_G => (Real(SYSCLK_FREQUENCY / 1000000)), -- Master clock frequency (MHz). + INIT_SPI_FREQ_G => 0.4, -- Slow SPI clock freq. during initialization (MHz). + SPI_FREQ_G => 25.0, -- Operational SPI freq. to the SD card (MHz). + BLOCK_SIZE_G => 512 -- Number of bytes in an SD card block or sector. + ) + port map + ( + -- Host-side interface signals. + clk_i => SYSCLK, -- Master clock. + reset_i => SD_RESET(I), -- active-high, synchronous reset. + cardtype => SD_CARD_TYPE(I), -- 0 = SD, 1 = SDHC. + rd_i => SD_RD(I), -- active-high read block request. + wr_i => SD_WR(I), -- active-high write block request. + continue_i => SD_CONTINUE(I), -- If true, inc address and continue R/W. + addr_i => SD_ADDR(I), -- Block address. + data_i => SD_DATA_WRITE(7 downto 0), -- Data to write to block. + data_o => SD_DATA_READ(I)(7 downto 0), -- Data read from block. + busy_o => SD_BUSY(I), -- High when controller is busy performing some operation. + hndShk_i => SD_HNDSHK_IN(I), -- High when host has data to give or has taken data. + hndShk_o => SD_HNDSHK_OUT(I), -- High when controller has taken data or has data to give. + error_o => SD_ERROR(I), -- Card error occurred (1). + -- I/O signals to the external SD card. + cs_bo => SDCARD_CS(I), -- Active-low chip-select. + sclk_o => SDCARD_CLK(I), -- Serial clock to SD card. + mosi_o => SDCARD_MOSI(I), -- Serial data output to SD card. + miso_i => SDCARD_MISO(I) -- Serial data input from SD card. + ); + end generate; + end generate; + -- + SDCARDCTL: if SOC_IMPL_SD = true and SOC_SD_DEVICES >= 1 generate + + process(SYSCLK, RESET_n, MEM_ADDR) + variable tChannel : integer range 0 to SOC_SD_DEVICES-1; + begin + + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + -- Channel being accessed is in addr bits 5:4. + tChannel := to_integer(unsigned(MEM_ADDR(6 downto 4))); + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if RESET_n='0' then + SD_ADDR <= (others => (others => DontCareValue)); + SD_RD <= (others => '0'); + SD_WR <= (others => '0'); + SD_RESET <= (others => '0'); + SD_CARD_TYPE <= (others => '0'); + SD_CONTINUE <= (others => '0'); + SD_HNDSHK_IN <= (others => '0'); + SD_OVERRUN <= '0'; + SD_DATA_REQ <= '0'; + SD_DATA_VALID <= '0'; + SD_RESET_TIMER <= 0; + SD_STATE <= SD_STATE_RESET; + IO_WAIT_SD <= '0'; + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(SYSCLK) then + + -- Reset wait state, only 1 cycle long under normal circumstances. + IO_WAIT_SD <= '0'; + + -- CPU Write? + if MEM_WRITE_ENABLE = '1' and SD_CS = '1' then + + -- Write to the SPI. + case MEM_ADDR(3 downto 2) is + when "00" => -- Store address for next block operation. + SD_ADDR(tChannel) <= MEM_DATA_WRITE; + + -- Write data latch, the host writes data to be written into this register when + -- the status register SD_DATA_REQ is set. + when "01" => + SD_DATA_WRITE <= MEM_DATA_WRITE(7 downto 0); + SD_DATA_REQ <= '0'; + + -- Command register, initiate transactions by setting the control bits. + when "11" => -- Command + if MEM_DATA_WRITE(0) = '1' then + SD_STATE <= SD_STATE_RESET; + elsif MEM_DATA_WRITE(1) = '1' then + SD_STATE <= SD_STATE_WRITE; + elsif MEM_DATA_WRITE(2) = '1' then + SD_STATE <= SD_STATE_READ; + elsif MEM_DATA_WRITE(3) = '1' then + SD_CARD_TYPE(tChannel) <= MEM_DATA_WRITE(7); + end if; + SD_CHANNEL <= tChannel; + + when others => + end case; + + -- IO Read? + elsif MEM_READ_ENABLE = '1' and SD_CS = '1' then + + -- Read from SPI. + IO_DATA_READ_SD <= (others => '0'); + case MEM_ADDR(3 downto 2) is + -- Read back stored address. + when "00" => + IO_DATA_READ_SD <= SD_ADDR(tChannel); + IO_WAIT_SD <= '0'; + + -- Read Data, only valid if the SD_DATA_VALID bit is set. + when "01" => + IO_WAIT_SD <= '0'; + IO_DATA_READ_SD(31 downto 16) <= SD_ERROR(tChannel); + IO_DATA_READ_SD(7 downto 0) <= SD_DATA_READ(tChannel); + SD_DATA_VALID <= '0'; + + -- Card status + when "11" => + IO_DATA_READ_SD(0) <= SD_CONTINUE(tChannel); + IO_DATA_READ_SD(1) <= SD_BUSY(tChannel); + IO_DATA_READ_SD(2) <= SD_HNDSHK_OUT(tChannel); + IO_DATA_READ_SD(3) <= SD_HNDSHK_IN(tChannel); + IO_DATA_READ_SD(4) <= SD_DATA_REQ; -- 1 when data needed for transmission. + IO_DATA_READ_SD(5) <= SD_DATA_VALID; -- 1 when data available. + IO_DATA_READ_SD(6) <= SD_OVERRUN; + IO_DATA_READ_SD(12 downto 8) <= std_logic_vector(to_unsigned(SDStateType'POS(SD_STATE), 5)); + IO_DATA_READ_SD(13) <= SD_RD(tChannel); + IO_DATA_READ_SD(14) <= SD_WR(tChannel); + IO_DATA_READ_SD(15) <= SD_RESET(tChannel); + IO_DATA_READ_SD(31 downto 16) <= SD_ERROR(tChannel); + IO_WAIT_SD <= '0'; + SD_OVERRUN <= '0'; + + when others => + end case; + end if; + + -- State machine to process requests. + case SD_STATE is + when SD_STATE_IDLE => + SD_RESET <= (others => '0'); + SD_WR <= (others => '0'); + SD_RD <= (others => '0'); + + ----------------------------------------- + -- RESET SD card + ----------------------------------------- + + -- To reset the card we apply a 100ns reset pulse, the card will then go through the reset procedure, asserting + -- BUSY until it is ready when BUSY will be deasserted. + when SD_STATE_RESET => + SD_RESET_TIMER <= SYSCLK_FREQUENCY/10000000; + SD_RESET(SD_CHANNEL) <= '1'; + SD_STATE <= SD_STATE_RESET_1; + + when SD_STATE_RESET_1 => + if SD_RESET_TIMER = 0 then + SD_RESET(SD_CHANNEL) <= '0'; + SD_STATE <= SD_STATE_IDLE; + else + SD_RESET_TIMER <= SD_RESET_TIMER - 1; + end if; + + ----------------------------------------- + -- WRITE a sector + ----------------------------------------- + + -- Address of byte (SD)/block (SDHC) already applied to address input. Set SD_WR high and wait + -- wait until SD_BUSY goes high. + when SD_STATE_WRITE => + SD_WR(SD_CHANNEL) <= '1'; + SD_DATA_REQ <= '0'; + if SD_BUSY(SD_CHANNEL) = '1' then + SD_WR(SD_CHANNEL) <= '0'; + SD_STATE <= SD_STATE_WRITE_1; + end if; + + -- We now enter a loop, we wait for a byte to be written into the data register, then wait for the controller + -- to assert HNDSHK_OUT, we raise the handshake line HNDSHK_IN and wait for the deassertion of HNDSHK_OUT to indicate completion. + -- If SD_BUSY is reset then it indicates completion, either due to an error or because the entire sector was written. + when SD_STATE_WRITE_1 => + -- When DATA Request is clear and the controller starts a handshake, request from the host a byte. + if SD_DATA_REQ = '0' and SD_HNDSHK_OUT(SD_CHANNEL) = '1' then + SD_DATA_REQ <= '1'; + SD_STATE <= SD_STATE_WRITE_2; + + -- If Busy goes inactive then we have completed, either due to an error or completion of the write. + elsif SD_BUSY(SD_CHANNEL) = '0' then + SD_STATE <= SD_STATE_IDLE; + end if; + + when SD_STATE_WRITE_2 => + -- When the data byte is loaded by the host, we raise our handshake line to show data available. + if SD_DATA_REQ = '0' and SD_HNDSHK_OUT(SD_CHANNEL) = '1' then + SD_HNDSHK_IN(SD_CHANNEL) <= '1'; + + -- When the controller acknowledges, lower the handshake line to complete the transaction. + elsif SD_HNDSHK_OUT(SD_CHANNEL) = '0' then + SD_HNDSHK_IN(SD_CHANNEL) <= '0'; + SD_STATE <= SD_STATE_WRITE_1; + + elsif SD_BUSY(SD_CHANNEL) = '0' then + SD_STATE <= SD_STATE_IDLE; + end if; + + ----------------------------------------- + -- READ a sector + ----------------------------------------- + + -- For a read, we raise the SD_RD line and wait for SD_BUSY to go high. Once SD_BUSY is high, SD_RD is deasserted and we + -- now wait for data. + when SD_STATE_READ => + SD_RD(SD_CHANNEL) <= '1'; + SD_DATA_VALID <= '0'; + if SD_BUSY(SD_CHANNEL) = '1' then + SD_RD(SD_CHANNEL) <= '0'; + SD_STATE <= SD_STATE_READ_1; + end if; + + -- If SD_BUSY is ever deasserted, we are either at the end of a read or an error occurred, in either case exit to IDLE. + -- We wait for the HNDSHK_OUT to be asserted, read the data, and then move to the next state. In between, if the timeout + -- timer expires because the controller hasnt sent data, abort as it may have locked up. + when SD_STATE_READ_1 => + + if SD_HNDSHK_OUT(SD_CHANNEL) = '1' then + SD_DATA_VALID <= '1'; + SD_HNDSHK_IN(SD_CHANNEL) <= '1'; + SD_STATE <= SD_STATE_READ_2; + + elsif SD_BUSY(SD_CHANNEL) = '0' then + SD_STATE <= SD_STATE_IDLE; + + elsif SD_DATA_VALID = '1' and SD_OVERRUN = '0' then + SD_OVERRUN <= '1'; + end if; + + -- Wait until the host reads the data, then assert HNDSHK_IN, the controller acknowledges by deasserting HNDSHK_OUT and at this + -- point the byte read cycle is complete so we deassert HNDSHK_IN. If the timeut expires during this operation or SD_BUSY is + -- deasserted, exit to IDLE due to error. + when SD_STATE_READ_2 => + + if SD_HNDSHK_OUT(SD_CHANNEL) = '0' and SD_DATA_VALID = '0' then + SD_HNDSHK_IN(SD_CHANNEL) <= '0'; + SD_STATE <= SD_STATE_READ_1; + + elsif SD_BUSY(SD_CHANNEL) = '0' then + SD_STATE <= SD_STATE_IDLE; + + end if; + + when others => + end case; + end if; + end process; + else generate + SD_ADDR <= (others => (others => DontCareValue)); + SD_RD <= (others => '0'); + SD_WR <= (others => '0'); + SD_RESET <= (others => '0'); + SD_CARD_TYPE <= (others => '0'); + SD_CONTINUE <= (others => '0'); + SD_HNDSHK_IN <= (others => '0'); + SD_OVERRUN <= '0'; + SD_DATA_REQ <= '0'; + SD_DATA_VALID <= '0'; + SD_RESET_TIMER <= 0; + SD_STATE <= SD_STATE_RESET; + IO_WAIT_SD <= '0'; + end generate; + + -- Interrupt controller + INTRCTL: if SOC_IMPL_INTRCTL = true generate + INTCONTROLLER : entity work.interrupt_controller + generic map ( + max_int => SOC_INTR_MAX + ) + port map ( + clk => SYSCLK, + reset_n => RESET_n, + trigger => INT_TRIGGERS, + enable_mask => INT_ENABLE, + ack => INT_DONE, + int => INT_REQ, + status => INT_STATUS + ); + + process(SYSCLK, RESET_n) + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if RESET_n='0' then + INT_ENABLE <= (others => '0'); + IO_WAIT_INTR <= '0'; + IO_DATA_READ_INTRCTL <= (others => 'X'); + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(SYSCLK) then + + IO_WAIT_INTR <= '0'; + + -- CPU Write? + if MEM_WRITE_ENABLE = '1' and INTR0_CS = '1' then + + -- Write to interrupt controller sets the enable mask bits. + case MEM_ADDR(2) is + when '0' => + + when '1' => + INT_ENABLE <= MEM_DATA_WRITE(SOC_INTR_MAX downto 0); + end case; + + -- IO Read? + elsif MEM_READ_ENABLE = '1' and INTR0_CS = '1' then + + -- Read interrupt status, 32 bits showing which interrupts have been triggered. + IO_DATA_READ_INTRCTL <= (others => 'X'); + if MEM_ADDR(2) = '0' then + IO_DATA_READ_INTRCTL(SOC_INTR_MAX downto 0) <= INT_STATUS; + else + Io_DATA_READ_INTRCTL(SOC_INTR_MAX downto 0) <= INT_ENABLE; + end if; + + end if; + end if; -- rising-edge(SYSCLK) + end process; + + INT_TRIGGERS <= ( 0 => '0', + 1 => MICROSEC_DOWN_INTR, + 2 => MILLISEC_DOWN_INTR, + 3 => SECOND_DOWN_INTR, + 4 => TIMER1_TICK, + 5 => PS2_INT, + 6 => IOCTL_RDINT, + 7 => IOCTL_WRINT, + 8 => UART0_RX_INTR, + 9 => UART0_TX_INTR, + 10 => UART1_RX_INTR, + 11 => UART1_TX_INTR, + others => '0'); + INT_TRIGGER <= INT_REQ; + + INTR0_CS <= '1' when IO_SELECT = '1' and MEM_ADDR(11 downto 4) = "10110000" -- Interrupt Range 0xFFFFFBxx, 0xB00-B0F + else '0'; + + else generate + IO_DATA_READ_INTRCTL <= (others => 'X'); + INT_TRIGGER <= '0'; + INT_ENABLE <= (others => '0'); + IO_WAIT_INTR <= '0'; + end generate; + + -- UART + UART0 : entity work.uart + generic map ( + RX_FIFO_BIT_DEPTH => MAX_RX_FIFO_BITS, + TX_FIFO_BIT_DEPTH => MAX_TX_FIFO_BITS, + COUNTER_BITS => 16, + BAUDCLK_FREQUENCY => SYSCLK_FREQUENCY + ) + port map ( + -- CPU Interface + CLK => SYSCLK, -- memory master clock + RESET => not RESET_n, -- high active sync reset + ADDR => MEM_ADDR(3 downto 2), -- 0 = Read/Write Data, 1 = Control Register, 3 = Baud Register + DATA_IN => MEM_DATA_WRITE, -- write data + DATA_OUT => UART0_DATA_OUT, -- read data + CS => UART0_CS, -- Chip Select. + WREN => MEM_WRITE_ENABLE, -- Write enable. + RDEN => MEM_READ_ENABLE, -- Read enable. + + -- IRQ outputs + TXINTR => UART0_TX_INTR, -- Tx buffer empty interrupt. + RXINTR => UART0_RX_INTR, -- Rx buffer full interrupt. + + -- Serial data + TXD => UART_TX_0, + RXD => UART_RX_0 + ); + + UART1 : entity work.uart + generic map ( + RX_FIFO_BIT_DEPTH => MAX_RX_FIFO_BITS, + TX_FIFO_BIT_DEPTH => MAX_TX_FIFO_BITS, + COUNTER_BITS => 16, + BAUDCLK_FREQUENCY => SYSCLK_FREQUENCY + ) + port map ( + -- CPU Interface + CLK => SYSCLK, -- memory master clock + RESET => not RESET_n, -- high active sync reset + ADDR => MEM_ADDR(3 downto 2), -- 0 = Read/Write Data, 1 = Control Register, 3 = Baud Register + DATA_IN => MEM_DATA_WRITE, -- write data + DATA_OUT => UART1_DATA_OUT, -- read data + CS => UART1_CS, -- Chip Select. + WREN => MEM_WRITE_ENABLE, -- Write enable. + RDEN => MEM_READ_ENABLE, -- Read enable. + + -- IRQ outputs + TXINTR => UART1_TX_INTR, -- Tx buffer empty interrupt. + RXINTR => UART1_RX_INTR, -- Rx buffer full interrupt. + + -- Serial data + TXD => UART1_TX, + RXD => UART_RX_1 + ); + + -- IO Control Bus controller. + IOCTL: if SOC_IMPL_IOCTL = true and (BOARD_DE10 = true or BOARD_CYC1000 = true) generate + IOCTL0 : entity work.IOCTL + port map ( + CLK => SYSCLK, -- memory master clock + RESET => not RESET_n, -- high active sync reset + ADDR => MEM_ADDR(4 downto 2), -- address bus. + DATA_IN => MEM_DATA_WRITE, -- write data + DATA_OUT => IOCTL_DATA_OUT, -- read data + CS => IOCTL_CS, -- Chip Select. + WREN => MEM_WRITE_ENABLE, -- Write enable. + RDEN => MEM_READ_ENABLE, -- Read enable. + + -- IRQ outputs -- + IRQ_RD_O => IOCTL_RDINT, -- Read Interrupts from IOCTL. + IRQ_WR_O => IOCTL_WRINT, -- Write Interrupts from IOCTL. + + -- IOCTL Bus -- + IOCTL_DOWNLOAD => IOCTL_DOWNLOAD, -- Downloading to FPGA. + IOCTL_UPLOAD => IOCTL_UPLOAD, -- Uploading from FPGA. + IOCTL_CLK => IOCTL_CLK, -- I/O Clock. + IOCTL_WR => IOCTL_WR, -- Write Enable to FPGA. + IOCTL_RD => IOCTL_RD, -- Read Enable from FPGA. + IOCTL_SENSE => IOCTL_SENSE, -- Sense to see if HPS accessing ioctl bus. + IOCTL_SELECT => IOCTL_SELECT, -- Enable IOP control over ioctl bus. + IOCTL_ADDR => IOCTL_ADDR, -- Address in FPGA to write into. + IOCTL_DOUT => IOCTL_DOUT, -- Data to be written into FPGA. + IOCTL_DIN => IOCTL_DIN -- Data to be read into HPS. + ); + + process(SYSCLK, RESET_n) + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if RESET_n='0' then + IO_WAIT_IOCTL <= '0'; + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(SYSCLK) then + + IO_WAIT_IOCTL <= '0'; + + -- CPU Write? + if MEM_WRITE_ENABLE = '1' and IO_SELECT = '1' then + + -- IO Read? + elsif MEM_READ_ENABLE = '1' and IO_SELECT = '1' then + + if IOCTL_CS = '1' then + IO_DATA_READ_IOCTL <= IOCTL_DATA_OUT; + end if; + + end if; + end if; -- rising-edge(SYSCLK) + end process; + + IOCTL_CS <= '1' when IO_SELECT = '1' and MEM_ADDR(11 downto 4) = "10000000" -- Ioctl Range 0xFFFFF8xx 0x800-80F + else '0'; + else generate + IOCTL_CS <= '0'; + IO_WAIT_IOCTL <= '0'; + IOCTL_RDINT <= '0'; + IOCTL_WRINT <= '0'; + end generate; + + IMPLSOCCFG: if SOC_IMPL_SOCCFG = true generate + process(SYSCLK, RESET_n) + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if RESET_n='0' then + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(SYSCLK) then + + -- SoC Configuration. + IO_DATA_READ_SOCCFG <= (others => 'X'); + case MEM_ADDR(7 downto 2) is + when "000000" => -- ZPU Id + IO_DATA_READ_SOCCFG(31 downto 28) <= "1010"; -- Identifier to show SoC Configuration registers are implemented. + if ZPU_SMALL = 1 then + IO_DATA_READ_SOCCFG(15 downto 0) <= std_logic_vector(to_unsigned(ZPU_ID_SMALL, 16)); + elsif ZPU_MEDIUM = 1 then + IO_DATA_READ_SOCCFG(15 downto 0) <= std_logic_vector(to_unsigned(ZPU_ID_MEDIUM, 16)); + elsif ZPU_FLEX = 1 then + IO_DATA_READ_SOCCFG(15 downto 0) <= std_logic_vector(to_unsigned(ZPU_ID_FLEX, 16)); + elsif ZPU_EVO = 1 then + IO_DATA_READ_SOCCFG(15 downto 0) <= std_logic_vector(to_unsigned(ZPU_ID_EVO, 16)); + elsif ZPU_EVO_MINIMAL = 1 then + IO_DATA_READ_SOCCFG(15 downto 0) <= std_logic_vector(to_unsigned(ZPU_ID_EVO_MINIMAL, 16)); + else + IO_DATA_READ_SOCCFG(15 downto 0) <= (others => '0'); + end if; + + when "000001" => -- System Frequency + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SYSCLK_FREQUENCY, wordSize)); + + when "000010" => -- Sysbus Memory Frequency + if (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1 or ZPU_MEDIUM = 1) and SOC_IMPL_SDRAM = true then + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_SDRAM_CLK_FREQ, wordSize)); + else + IO_DATA_READ_SOCCFG <= (others => '0'); + end if; + + when "000011" => -- Wishbone Memory Frequency + if (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and SOC_IMPL_WB = true and SOC_IMPL_WB_SDRAM = true then + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_WB_SDRAM_CLK_FREQ, wordSize)); + else + IO_DATA_READ_SOCCFG <= (others => '0'); + end if; + + when "000100" => -- Devices Implemented + IO_DATA_READ_SOCCFG(22 downto 0) <= to_std_logic(SOC_IMPL_WB) & + to_std_logic(SOC_IMPL_WB_SDRAM) & + to_std_logic(SOC_IMPL_WB_I2C) & + to_std_logic(SOC_IMPL_BRAM) & + to_std_logic(SOC_IMPL_RAM) & + to_std_logic(SOC_IMPL_INSN_BRAM) & + to_std_logic(SOC_IMPL_SDRAM) & + to_std_logic(SOC_IMPL_IOCTL) & + to_std_logic(SOC_IMPL_PS2) & + to_std_logic(SOC_IMPL_SPI) & + to_std_logic(SOC_IMPL_SD) & + std_logic_vector(to_unsigned(SOC_SD_DEVICES, 2)) & + to_std_logic(SOC_IMPL_INTRCTL) & + std_logic_vector(to_unsigned(SOC_INTR_MAX, 5)) & + to_std_logic(SOC_IMPL_TIMER1) & + std_logic_vector(to_unsigned(2**SOC_TIMER1_COUNTERS, 3)); + + when "000101" => -- BRAM Address + if SOC_IMPL_BRAM = true then + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_ADDR_BRAM_START, wordSize)); + end if; + + when "000110" => -- BRAM Size + if SOC_IMPL_BRAM = true then + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_ADDR_BRAM_END - SOC_ADDR_BRAM_START, wordSize)); + else + IO_DATA_READ_SOCCFG <= (others => 'X'); + end if; + + when "000111" => -- RAM Address + if SOC_IMPL_RAM = true then + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_ADDR_RAM_START, wordSize)); + else + IO_DATA_READ_SOCCFG <= (others => 'X'); + end if; + + when "001000" => -- RAM Size + if SOC_IMPL_RAM = true then + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_ADDR_RAM_END - SOC_ADDR_RAM_START, wordSize)); + else + IO_DATA_READ_SOCCFG <= (others => 'X'); + end if; + + when "001001" => -- Instruction BRAM Address + if SOC_IMPL_INSN_BRAM = true then + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_ADDR_INSN_BRAM_START, wordSize)); + else + IO_DATA_READ_SOCCFG <= (others => 'X'); + end if; + + when "001010" => -- Instruction BRAM Size + if SOC_IMPL_INSN_BRAM = true then + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_ADDR_INSN_BRAM_END - SOC_ADDR_INSN_BRAM_START, wordSize)); + else + IO_DATA_READ_SOCCFG <= (others => 'X'); + end if; + + when "001011" => -- SDRAM Address + if (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1 or ZPU_MEDIUM = 1) and SOC_IMPL_SDRAM = true then + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_ADDR_SDRAM_START, wordSize)); + else + IO_DATA_READ_SOCCFG <= (others => '0'); + end if; + + when "001100" => -- SDRAM Size + if (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1 or ZPU_MEDIUM = 1) and SOC_IMPL_SDRAM = true then + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_ADDR_SDRAM_END - SOC_ADDR_SDRAM_START, wordSize)); + else + IO_DATA_READ_SOCCFG <= (others => '0'); + end if; + + when "001101" => -- WB SDRAM Address + if (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and SOC_IMPL_WB = true and SOC_IMPL_WB_SDRAM = true then + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_ADDR_WB_SDRAM_START, wordSize)); + else + IO_DATA_READ_SOCCFG <= (others => 'X'); + end if; + + when "001110" => -- WB SDRAM Size + if (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and SOC_IMPL_WB = true and SOC_IMPL_WB_SDRAM = true then + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_ADDR_WB_SDRAM_END - SOC_ADDR_WB_SDRAM_START, wordSize)); + else + IO_DATA_READ_SOCCFG <= (others => 'X'); + end if; + + when "001111" => -- CPU Reset Address + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_RESET_ADDR_CPU, wordSize)); + + when "010000" => -- CPU Memory Start Address + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_START_ADDR_MEM, wordSize)); + + when "010001" => -- Stack Start Address + IO_DATA_READ_SOCCFG <= std_logic_vector(to_unsigned(SOC_STACK_ADDR, wordSize)); + + when others => + end case; + end if; -- rising-edge(SYSCLK) + end process; + + SOCCFG_CS <= '1' when IO_SELECT = '1' and MEM_ADDR(11 downto 8) = "1111" -- SoC Config Range 0xF00-FF0, step 4 for 32 bit registers. + else '0'; + else generate + IO_DATA_READ_SOCCFG <= (others => '0'); + end generate; + ------------------------------------------------------------------------------------ + -- END Direct I/O devices + ------------------------------------------------------------------------------------ + +-- ------------------------------------------------------------------------------------ +-- -- WISHBONE devices +-- ------------------------------------------------------------------------------------ +-- +-- I2C : if (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and EVO_USE_WB_BUS = true and SOC_IMPL_WB_I2C = true generate +-- I2C_MASTER_0: work.i2c_master_top +-- generic map ( +-- ARST_LVL => '1' -- asynchronous reset level +-- ) +-- port map ( +-- -- Wishbone Bus +-- wb_clk_i => SYSCLK, -- master clock input +-- wb_rst_i => not RESET_n, -- synchronous active high reset +-- arst_i => '0', -- asynchronous reset - not used. +-- wb_adr_i => WB_ADR_O(4 downto 2), -- lower address bits +-- wb_dat_i => WB_DAT_O(BYTE_RANGE), -- Databus input (lowest 8 bit) +-- wb_dat_o => WB_DATA_READ_I2C(BYTE_RANGE), -- Databus output +-- wb_we_i => WB_WE_O, -- Write enable input +-- wb_stb_i => WB_I2C_CS, -- Strobe signal using chip select. +-- wb_cyc_i => WB_CYC_O, -- Valid bus cycle input +-- wb_ack_o => WB_I2C_ACK, -- Bus cycle acknowledge output +-- wb_inta_o => WB_I2C_IRQ, -- interrupt request output signal +-- +-- -- I²C lines +-- scl_pad_i => SCL_PAD_IN, -- i2c clock line input +-- scl_pad_o => SCL_PAD_OUT, -- i2c clock line output +-- scl_padoen_o => SCL_PAD_OE, -- i2c clock line output enable, active low +-- sda_pad_i => SDA_PAD_IN, -- i2c data line input +-- sda_pad_o => SDA_PAD_OUT, -- i2c data line output +-- sda_padoen_o => SDA_PAD_OE -- i2c data line output enable, active low +-- ); +-- +-- -- Data Width Adaption, I2C is only 8 bits so expand to 32bits. +-- --WB_DATA_READ_I2C <= x"000000" & I2C_DATA_OUT; +-- +-- -- IO Buffer +-- I2C_SCL_IO <= SCL_PAD_OUT when (SCL_PAD_OE = '0') else 'Z'; +-- I2C_SDA_IO <= SDA_PAD_OUT when (SDA_PAD_OE = '0') else 'Z'; +-- SCL_PAD_IN <= I2C_SCL_IO; +-- SDA_PAD_IN <= I2C_SDA_IO; +-- +-- -- Halt / Error +-- WB_I2C_HALT <= '0'; -- no throttle -> full speed +-- WB_I2C_ERR <= '0'; -- nothing can go wrong - never ever! +-- else generate +-- I2C_SCL_IO <= 'Z'; +-- I2C_SDA_IO <= 'Z'; +-- SCL_PAD_IN <= 'X'; +-- SDA_PAD_IN <= 'X'; +-- WB_I2C_HALT <= '0'; +-- WB_I2C_ERR <= '0'; +-- end generate; +-- +-- -- SDRAM over WishBone bus. +-- ZPUWBSDRAMEVO : if (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and SOC_IMPL_WB = true and SOC_IMPL_WB_SDRAM = true and (BOARD_QMV = true or BOARD_CYC1000 = true) generate +-- +-- ZPUWBSDRAM : entity work.WBSDRAM +-- generic map ( +-- SDRAM_ROWS => SOC_WB_SDRAM_ROWS, -- Number of Rows in the SDRAM. +-- SDRAM_COLUMNS => SOC_WB_SDRAM_COLUMNS, -- Number of Columns in an SDRAM page (ie. 1 row). +-- SDRAM_BANKS => SOC_WB_SDRAM_BANKS, -- Number of banks in the SDRAM. +-- SDRAM_DATAWIDTH => SOC_WB_SDRAM_DATAWIDTH, -- Data width of SDRAM chip (ie. 16, 32). +-- SDRAM_CLK_FREQ => SOC_WB_SDRAM_CLK_FREQ, -- Frequency of SDRAM clock in Hertz. +-- SDRAM_tRCD => SOC_WB_SDRAM_tRCD, -- tRCD - RAS to CAS minimum period (in ns), ie. 20ns -> 2 cycles@100MHz +-- SDRAM_tRP => SOC_WB_SDRAM_tRP, -- tRP - Precharge delay, min time for a precharge command to complete (in ns), ie. 15ns -> 2 cycles@100MHz +-- SDRAM_tRFC => SOC_WB_SDRAM_tRFC, -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns +-- SDRAM_tREF => SOC_WB_SDRAM_tREF -- tREF - period of time a complete refresh of all rows is made within (in ms). +-- ) +-- port map ( +-- -- SDRAM Interface +-- SDRAM_CLK => MEMCLK, -- sdram clock running at an offset from system clock. +-- SDRAM_RST => not RESET_n, -- reset the sdram controller. +-- SDRAM_CKE => SDRAM_CKE, -- clock enable. +-- SDRAM_DQ => SDRAM_DQ, -- 16 bit bidirectional data bus +-- SDRAM_ADDR => SDRAM_ADDR, -- 12 bit multiplexed address bus +-- SDRAM_DQM => SDRAM_DQM, -- two byte masks +-- SDRAM_BA => SDRAM_BA, -- two banks +-- SDRAM_CS_n => SDRAM_CS_n, -- a single chip select +-- SDRAM_WE_n => SDRAM_WE_n, -- write enable +-- SDRAM_RAS_n => SDRAM_RAS_n, -- row address select +-- SDRAM_CAS_n => SDRAM_CAS_n, -- columns address select +-- SDRAM_READY => SDRAM_READY, -- sd ready. +-- +-- -- WishBone interface. +-- WB_CLK => WB_CLK_I, -- clock to which sdram state machine is synchonized +-- WB_RST_I => not RESET_n, -- Reset baased on CPU reset active high. +-- WB_DATA_I => WB_DAT_O, -- data input from chipset/cpu +-- WB_DATA_O => WB_DATA_READ_SDRAM, -- data output to chipset/cpu +-- WB_ACK_O => WB_SDRAM_ACK, +-- WB_ADR_I => WB_ADR_O(ADDR_BIT_WB_SDRAM_RANGE), -- lower 2 bits are ignored. +-- WB_SEL_I => WB_SEL_O, +-- WB_CTI_I => WB_CTI_O, -- cycle type. +-- WB_STB_I => WB_SDRAM_STB, +-- WB_CYC_I => WB_CYC_O, -- cpu/chipset requests cycle +-- WB_WE_I => WB_SDRAM_WREN, -- cpu/chipset requests write +-- WB_TGC_I => "0000000", -- cycle tag +-- WB_HALT_O => open, +-- WB_ERR_O => open +-- ); +---- +---- ZPUSRAM: entity work.SRAM +---- generic map ( +---- addrbits => 14 +---- ) +---- port map ( +---- -- WishBone interface. +---- WB_CLK_I => WB_CLK_I, -- 100MHz chipset clock to which sdram state machine is synchonized +---- WB_RST_I => not RESET_n, -- high active sync reset +---- WB_DATA_I => WB_DAT_O, -- data input from chipset/cpu +---- WB_DATA_O => WB_DATA_READ_SDRAM, -- data output to chipset/cpu +---- WB_ACK_O => WB_SDRAM_ACK, +---- WB_ADR_I => WB_ADR_O(13 downto 0), -- lower 2 bits are ignored. +---- WB_SEL_I => WB_SEL_O, +---- WB_CTI_I => WB_CTI_O, -- cycle type. +---- WB_STB_I => WB_SDRAM_STB, +---- WB_CYC_I => WB_CYC_O, -- cpu/chipset requests cycle +---- WB_WE_I => RAM_WREN, -- cpu/chipset requests write +---- WB_TGC_I => "0000000", -- cycle tag +---- WB_HALT_O => open, +---- WB_ERR_O => open +---- ); +-- +-- -- RAM Range SOC_ADDR_RAM_START) -> SOC_ADDR_RAM_END +-- WB_SDRAM_SELECT <= '1' when (ZPU_EVO = 1 or ZPU_EVO_MINIMAL = 1) and (WB_ADR_O >= std_logic_vector(to_unsigned(SOC_ADDR_WB_SDRAM_START, WB_ADR_O'LENGTH)) and WB_ADR_O < std_logic_vector(to_unsigned(SOC_ADDR_WB_SDRAM_END, WB_ADR_O'LENGTH))) +-- else '0'; +-- +-- -- Enable write to RAM when selected and CPU in write state. +-- WB_SDRAM_WREN <= '1' when WB_SDRAM_SELECT = '1' and WB_WE_O = '1' +-- else +-- '0'; +-- +-- -- Wishbone strobe based on the RAM Select signal which limits the address range. +-- WB_SDRAM_STB <= '1' when WB_SDRAM_SELECT = '1' and WB_STB_O = '1' +-- else '0'; +-- +-- -- SDRAM clock based on system clock. +-- SDRAM_CLK <= MEMCLK; +-- else generate +-- WB_SDRAM_SELECT <= '0'; +-- WB_SDRAM_WREN <= '0'; +-- WB_SDRAM_STB <= '0'; +-- SDRAM_CLK <= MEMCLK; +-- end generate; +-- +-- ------------------------------------------------------------------------------------ +-- -- END WISHBONE devices +-- ------------------------------------------------------------------------------------ + + + -- Reset counter. Incoming reset toggles reset and holds it low for a fixed period. Additionally, if the primary UART RX receives a break + -- signal, then the reset is triggered. + -- + process(SYSCLK, RESET_IN) + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if RESET_IN='0' then + RESET_COUNTER <= X"FFFF"; + RESET_COUNTER_RX <= to_unsigned(((SYSCLK_FREQUENCY)/300), 16); + RESET_n <= '0'; + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(SYSCLK) then + + MEM_READ_ENABLE_LAST <= MEM_READ_ENABLE; + + -- If the RX receives a break signal, count down to ensure it is held low for correct period, when the count reaches + -- zero, start a reset. + -- + if UART_RX_0 = '0' or UART_RX_1 = '0' then + RESET_COUNTER_RX <= RESET_COUNTER_RX - 1; + else + RESET_COUNTER_RX <= to_unsigned(((SYSCLK_FREQUENCY)/300), 16); + end if; + + if RESET_COUNTER_RX = X"0000" then + RESET_COUNTER <= X"FFFF"; + RESET_COUNTER_RX <= to_unsigned(((SYSCLK_FREQUENCY)/300), 16); + RESET_n <= '0'; + end if; + + RESET_COUNTER <= RESET_COUNTER - 1; + if RESET_COUNTER = X"0000" then + RESET_n <= '1'; + end if; + end if; + end process; + + -- Main peripheral process, decode address and activate memory/peripheral accordingly. + process(SYSCLK, RESET_n) + begin + ------------------------ + -- HIGH LEVEL -- + ------------------------ + + ------------------------ + -- ASYNCHRONOUS RESET -- + ------------------------ + if RESET_n='0' then + MICROSEC_DOWN_COUNTER <= (others => '0'); + MILLISEC_DOWN_COUNTER <= (others => '0'); + MILLISEC_UP_COUNTER <= (others => '0'); + SECOND_DOWN_COUNTER <= (others => '0'); + MICROSEC_DOWN_TICK <= 0; + MILLISEC_DOWN_TICK <= 0; + SECOND_DOWN_TICK <= 0; + MILLISEC_UP_TICK <= 0; + MICROSEC_DOWN_INTR <= '0'; + MICROSEC_DOWN_INTR_EN <= '0'; + MILLISEC_DOWN_INTR <= '0'; + MILLISEC_DOWN_INTR_EN <= '0'; + SECOND_DOWN_INTR <= '0'; + SECOND_DOWN_INTR_EN <= '0'; + RTC_MICROSEC_TICK <= 0; + RTC_MICROSEC_COUNTER <= 0; + RTC_MILLISEC_COUNTER <= 0; + RTC_SECOND_COUNTER <= 0; + RTC_MINUTE_COUNTER <= 0; + RTC_HOUR_COUNTER <= 0; + RTC_DAY_COUNTER <= 1; + RTC_MONTH_COUNTER <= 1; + RTC_YEAR_COUNTER <= 0; + RTC_TICK_HALT <= '0'; + + ----------------------- + -- RISING CLOCK EDGE -- + ----------------------- + elsif rising_edge(SYSCLK) then + + -- CPU Write? + if MEM_WRITE_ENABLE = '1' and IO_SELECT = '1' then + + -- Write to Millisecond Timer - set current time and day. + if TIMER0_CS = '1' then + case MEM_ADDR(5 downto 2) is + when "0000" => + MICROSEC_DOWN_COUNTER(23 downto 0) <= unsigned(MEM_DATA_WRITE(23 downto 0)); + MICROSEC_DOWN_TICK <= 0; + + when "0001" => + MILLISEC_DOWN_COUNTER(17 downto 0) <= unsigned(MEM_DATA_WRITE(17 downto 0)); + MILLISEC_DOWN_TICK <= 0; + + when "0010" => + MILLISEC_UP_COUNTER(31 downto 0) <= unsigned(MEM_DATA_WRITE(31 downto 0)); + MILLISEC_UP_TICK <= 0; + + when "0011" => + SECOND_DOWN_COUNTER(11 downto 0) <= unsigned(MEM_DATA_WRITE(11 downto 0)); + SECOND_DOWN_TICK <= 0; + + when "0111" => + RTC_TICK_HALT <= MEM_DATA_WRITE(0); + + when "1000" => + RTC_MICROSEC_COUNTER <= to_integer(unsigned(MEM_DATA_WRITE(9 downto 0))); + RTC_MICROSEC_TICK <= 0; + + when "1001" => + RTC_MILLISEC_COUNTER <= to_integer(unsigned(MEM_DATA_WRITE(9 downto 0))); + RTC_MICROSEC_TICK <= 0; + + when "1010" => + RTC_SECOND_COUNTER <= to_integer(unsigned(MEM_DATA_WRITE(5 downto 0))); + RTC_MICROSEC_TICK <= 0; + + when "1011" => + RTC_MINUTE_COUNTER <= to_integer(unsigned(MEM_DATA_WRITE(5 downto 0))); + RTC_MICROSEC_TICK <= 0; + + when "1100" => + RTC_HOUR_COUNTER <= to_integer(unsigned(MEM_DATA_WRITE(4 downto 0))); + RTC_MICROSEC_TICK <= 0; + + when "1101" => + RTC_DAY_COUNTER <= to_integer(unsigned(MEM_DATA_WRITE(3 downto 0))); + RTC_MICROSEC_TICK <= 0; + + when "1110" => + RTC_MONTH_COUNTER <= to_integer(unsigned(MEM_DATA_WRITE(3 downto 0))); + RTC_MICROSEC_TICK <= 0; + + when "1111" => + RTC_YEAR_COUNTER <= to_integer(unsigned(MEM_DATA_WRITE(11 downto 0))); + RTC_MICROSEC_TICK <= 0; + + when others => + end case; + end if; + end if; + + -- Read from UART. + if UART0_CS = '1' then + IO_DATA_READ <= UART0_DATA_OUT; + end if; + if UART1_CS = '1' then + IO_DATA_READ <= UART1_DATA_OUT; + end if; + + -- Read from millisecond timer, read milliseconds in last 24 hours and number of elapsed days. + if TIMER0_CS = '1' then + IO_DATA_READ <= (others => '0'); + case MEM_ADDR(5 downto 2) is + when "0000" => + IO_DATA_READ(23 downto 0) <= std_logic_vector(MICROSEC_DOWN_COUNTER(23 downto 0)); + + when "0001" => + IO_DATA_READ(17 downto 0) <= std_logic_vector(MILLISEC_DOWN_COUNTER(17 downto 0)); + + when "0010" => + IO_DATA_READ(31 downto 0) <= std_logic_vector(MILLISEC_UP_COUNTER(31 downto 0)); + + when "0011" => + IO_DATA_READ(11 downto 0) <= std_logic_vector(SECOND_DOWN_COUNTER(11 downto 0)); + + when "1000" => + IO_DATA_READ(9 downto 0) <= std_logic_vector(to_unsigned(RTC_MICROSEC_COUNTER, 10)); + + when "1001" => + IO_DATA_READ(9 downto 0) <= std_logic_vector(to_unsigned(RTC_MILLISEC_COUNTER, 10)); + + when "1010" => + IO_DATA_READ(5 downto 0) <= std_logic_vector(to_unsigned(RTC_SECOND_COUNTER, 6)); + + when "1011" => + IO_DATA_READ(5 downto 0) <= std_logic_vector(to_unsigned(RTC_MINUTE_COUNTER, 6)); + + when "1100" => + IO_DATA_READ(4 downto 0) <= std_logic_vector(to_unsigned(RTC_HOUR_COUNTER, 5)); + + when "1101" => + IO_DATA_READ(4 downto 0) <= std_logic_vector(to_unsigned(RTC_DAY_COUNTER, 5)); + + when "1110" => + IO_DATA_READ(3 downto 0) <= std_logic_vector(to_unsigned(RTC_MONTH_COUNTER, 4)); + + when "1111" => + IO_DATA_READ(11 downto 0) <= std_logic_vector(to_unsigned(RTC_YEAR_COUNTER, 12)); + + when others => + end case; + end if; + + -- Timer in microseconds, Each 24 hours the timer is zeroed and the day counter incremented. Used for delay loops + -- and RTC. + if RTC_TICK_HALT = '0' then + RTC_MICROSEC_TICK <= RTC_MICROSEC_TICK+1; + end if; + if RTC_MICROSEC_TICK = ((SYSCLK_FREQUENCY/1000000) -1) then -- Sys clock has to be > 1MHz or will not be accurate. + RTC_MICROSEC_TICK <= 0; + RTC_MICROSEC_COUNTER <= RTC_MICROSEC_COUNTER + 1; + + if RTC_MICROSEC_COUNTER = (1000 - 1) then + RTC_MICROSEC_COUNTER <= 0; + RTC_MILLISEC_COUNTER <= RTC_MILLISEC_COUNTER + 1; + + if RTC_MILLISEC_COUNTER = (1000 - 1) then + RTC_SECOND_COUNTER <= RTC_SECOND_COUNTER + 1; + RTC_MILLISEC_COUNTER <= 0; + + if RTC_SECOND_COUNTER = (60 - 1) then + RTC_MINUTE_COUNTER <= RTC_MINUTE_COUNTER + 1; + RTC_SECOND_COUNTER <= 0; + + if RTC_MINUTE_COUNTER = (60 - 1) then + RTC_HOUR_COUNTER <= RTC_HOUR_COUNTER + 1; + RTC_MINUTE_COUNTER <= 0; + + if RTC_HOUR_COUNTER = (24 - 1) then + RTC_DAY_COUNTER <= RTC_DAY_COUNTER + 1; + RTC_HOUR_COUNTER <= 0; + + if (RTC_DAY_COUNTER = 31 and (RTC_MONTH_COUNTER = 4 or RTC_MONTH_COUNTER = 6 or RTC_MONTH_COUNTER = 9 or RTC_MONTH_COUNTER = 11)) + or + (RTC_DAY_COUNTER = 32 and RTC_MONTH_COUNTER /= 4 and RTC_MONTH_COUNTER /= 6 and RTC_MONTH_COUNTER /= 9 and RTC_MONTH_COUNTER /= 11) + or + (RTC_DAY_COUNTER = 29 and RTC_MONTH_COUNTER = 2 and std_logic_vector(to_unsigned(RTC_YEAR_COUNTER, 2)) /= "00") + or + (RTC_DAY_COUNTER = 30 and RTC_MONTH_COUNTER = 2 and std_logic_vector(to_unsigned(RTC_YEAR_COUNTER, 2)) = "00") + then + RTC_MONTH_COUNTER <= RTC_MONTH_COUNTER + 1; + RTC_DAY_COUNTER <= 1; + + if RTC_MONTH_COUNTER = 13 then + RTC_YEAR_COUNTER <= RTC_YEAR_COUNTER + 1; + RTC_MONTH_COUNTER <= 1; + end if; + end if; + end if; + end if; + end if; + end if; + end if; + end if; + + -- Down and up counters, each have independent ticks which reset on counter set, this guarantees timer is accurate. + MICROSEC_DOWN_TICK <= MICROSEC_DOWN_TICK+1; + if MICROSEC_DOWN_TICK = ((SYSCLK_FREQUENCY/1000000) -1) then -- Sys clock has to be > 1MHz or will not be accurate. + MICROSEC_DOWN_TICK <= 0; + + -- Decrement microsecond down counter if not yet zero. + if MICROSEC_DOWN_COUNTER /= 0 then + MICROSEC_DOWN_COUNTER <= MICROSEC_DOWN_COUNTER - 1; + end if; + if MICROSEC_DOWN_COUNTER = 0 and MICROSEC_DOWN_INTR_EN = '1' then + MICROSEC_DOWN_INTR <= '1'; + end if; + end if; + + MILLISEC_DOWN_TICK <= MILLISEC_DOWN_TICK+1; + if MILLISEC_DOWN_TICK = (((SYSCLK_FREQUENCY/1000000)*1000) -1) then -- Sys clock has to be > 1MHz or will not be accurate. + MILLISEC_DOWN_TICK <= 0; + + -- Decrement millisecond down counter if not yet zero. + if MILLISEC_DOWN_COUNTER /= 0 then + MILLISEC_DOWN_COUNTER <= MILLISEC_DOWN_COUNTER - 1; + end if; + if MILLISEC_DOWN_COUNTER = 0 and MILLISEC_DOWN_INTR_EN = '1' then + MILLISEC_DOWN_INTR <= '1'; + end if; + end if; + + MILLISEC_UP_TICK <= MILLISEC_UP_TICK+1; + if MILLISEC_UP_TICK = (((SYSCLK_FREQUENCY/1000000)*1000) - 1) then -- Sys clock has to be > 1MHz or will not be accurate. + MILLISEC_UP_TICK <= 0; + MILLISEC_UP_COUNTER <= MILLISEC_UP_COUNTER + 1; + end if; + + SECOND_DOWN_TICK <= SECOND_DOWN_TICK+1; + if SECOND_DOWN_TICK = (((SYSCLK_FREQUENCY/1000000)*1000000) - 1) then -- Sys clock has to be > 1MHz or will not be accurate. + SECOND_DOWN_TICK <= 0; + + -- Decrement second down counter if not yet zero. + if SECOND_DOWN_COUNTER /= 0 then + SECOND_DOWN_COUNTER <= SECOND_DOWN_COUNTER - 1; + end if; + if SECOND_DOWN_COUNTER = 0 and SECOND_DOWN_INTR_EN = '1' then + SECOND_DOWN_INTR <= '1'; + end if; + end if; + end if; -- rising-edge(SYSCLK) + end process; + +end architecture; diff --git a/zpu/zpu_soc_pkg.tmpl.vhd b/zpu/zpu_soc_pkg.tmpl.vhd new file mode 100644 index 0000000..97ff238 --- /dev/null +++ b/zpu/zpu_soc_pkg.tmpl.vhd @@ -0,0 +1,246 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: zpu_soc_pkg.vhd +-- Created: January 2019 +-- Author(s): Philip Smart +-- Description: ZPU System On a Chip Configuration +-- +-- This module contains the System on a Chip configuration for the ZPU. +-- +-- Credits: +-- Copyright: (c) 2018 Philip Smart +-- +-- History: January 2019 - Initial creation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.zpu_pkg.all; + +package zpu_soc_pkg is + + -- Choose which CPU to instantiate depending on requirements. Warning, keep the below 5 lines exactly the same + -- or ensure you update the Makefile as they are set by the Makefile to generate zpu_soc_pkg.vhd + -- + constant ZPU_SMALL : integer := 0; -- Use the SMALL CPU. + constant ZPU_MEDIUM : integer := 0; -- Use the MEDIUM CPU. + constant ZPU_FLEX : integer := 0; -- Use the FLEX CPU. + constant ZPU_EVO : integer := 0; -- Use the EVOLUTION CPU. + constant ZPU_EVO_MINIMAL : integer := 0; -- Use the Minimalist EVOLUTION CPU. + + -- Frequencies for the various boards. + -- + constant SYSCLK_E115_FREQ : integer := 100000000; -- E115 FPGA Board + constant SYSCLK_QMV_FREQ : integer := 100000000; -- QMTECH Cyclone V FPGA Board + constant SYSCLK_DE0_FREQ : integer := 100000000; -- DE0-Nano FPGA Board + constant SYSCLK_DE10_FREQ : integer := 100000000; -- DE10-Nano FPGA Board + constant SYSCLK_CYC1000_FREQ : integer := 100000000; -- Trenz CYC1000 FPGA Board + + -- ID for the various ZPU models. The format is 2 bytes, MSB=, LSB= + constant ZPU_ID_SMALL : integer := 16#0101#; -- ID for the ZPU Small in this package. + constant ZPU_ID_MEDIUM : integer := 16#0201#; -- ID for the ZPU Medium in this package. + constant ZPU_ID_FLEX : integer := 16#0301#; -- ID for the ZPU Flex in this package. + constant ZPU_ID_EVO : integer := 16#0401#; -- ID for the ZPU Evo in this package. + constant ZPU_ID_EVO_MINIMAL : integer := 16#0501#; -- ID for the ZPU Evo Minimal in this package. + + -- EVO CPU specific configuration. + constant MAX_EVO_L1CACHE_BITS : integer := 5; -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache. + constant MAX_EVO_L2CACHE_BITS : integer := 12; -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache. + constant MAX_EVO_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits. + constant MAX_EVO_MIN_L1CACHE_BITS : integer := 4; -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache. + constant MAX_EVO_MIN_L2CACHE_BITS : integer := 12; -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache. + constant MAX_EVO_MIN_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits. + + -- Settings for various IO devices. + -- + constant MAX_RX_FIFO_BITS : integer := 8; -- Size of UART RX Fifo. + constant MAX_TX_FIFO_BITS : integer := 8; -- Size of UART TX Fifo. + constant MAX_UART_DIVISOR_BITS : integer := 16; -- Maximum number of bits for the UART clock rate generator divisor. + constant INTR_MAX : integer := 16; -- Maximum number of interrupt inputs. + constant SYSTEM_FREQUENCY : integer := 100000000; -- Default system clock frequency if not overriden by top level. +-- constant SYSCLK_FREQUENCY : integer := 1000; -- System clock in MHz x 10 +-- constant SYSCLK_HZ : integer := SYSCLK_FREQUENCY*100000; -- System clock in Hertz +-- constant UART_RESET_COUNT : integer := ((SYSCLK_FREQUENCY*100000)/300)*8; -- Count of system clock ticks for a UART break to be recognised as a system reset. + + -- SoC specific options. + -- + constant SOC_IMPL_WB : boolean := EVO_USE_WB_BUS; -- Implement the Wishbone bus and all enabled devices. + constant SOC_IMPL_WB_I2C : boolean := true; -- Implement I2C over wishbone interface. + constant SOC_IMPL_WB_SDRAM : boolean := true; -- Implement SDRAM over wishbone interface. + constant SOC_IMPL_TIMER1 : boolean := true; -- Implement Timer 1, an array of prescaled downcounter with enable. + constant SOC_TIMER1_COUNTERS : integer := 0; -- Number of downcounters in Timer 1. Value is a 2^ array of counters, so 0 = 1 counter. + constant SOC_IMPL_PS2 : boolean := true; -- Implement PS2 keyboard and mouse hardware. + constant SOC_IMPL_SPI : boolean := true; -- Implement Serial Peripheral Inteface(s). + constant SOC_IMPL_SD : boolean := true; -- Implement SD Card interface. + constant SOC_SD_DEVICES : integer := 1; -- Number of SD card channels implemented. + constant SOC_IMPL_INTRCTL : boolean := true; -- Implement the prioritised interrupt controller. + constant SOC_IMPL_IOCTL : boolean := false; -- Implement the IOCTL controller (specific to the MiSTer project). + constant SOC_IMPL_SOCCFG : boolean := true; -- Implement the SoC Configuration information registers. + constant SOC_IMPL_BRAM : boolean := true; -- Implement BRAM for the BIOS and initial Stack. + constant SOC_IMPL_RAM : boolean := false; -- Implement RAM using BRAM, typically for Application programs seperate to BIOS. + constant SOC_IMPL_DRAM : boolean := false; -- Implement Dynamic RAM and controller. + constant SOC_IMPL_INSN_BRAM : boolean := true; -- Implement dedicated instruction BRAM for the EVO CPU. Any addr access beyond the BRAM size goes to normal memory. + constant SOC_MAX_ADDR_BRAM_BIT : integer := 16; -- Max address bit of the System BRAM ROM/Stack in bytes, ie. 15 = 32KB or 8K 32bit words. NB. For non evo CPUS you must adjust the maxMemBit parameter in zpu_pkg.vhd to be the same. + constant SOC_ADDR_BRAM_START : integer := 0; -- Start address of BRAM. + constant SOC_ADDR_BRAM_END : integer := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_BRAM_BIT); -- End address of BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT. + constant SOC_MAX_ADDR_RAM_BIT : integer := 23; -- Max address bit of the System RAM. + constant SOC_ADDR_RAM_START : integer := 16777216; -- Start address of RAM. + constant SOC_ADDR_RAM_END : integer := SOC_ADDR_RAM_START+(2**SOC_MAX_ADDR_RAM_BIT); -- End address of RAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT. + constant SOC_MAX_ADDR_INSN_BRAM_BIT: integer := SOC_MAX_ADDR_BRAM_BIT; -- Max address bit of the dedicated instruction BRAM in bytes, ie. 15 = 32KB or 8K 32bit words. + constant SOC_ADDR_INSN_BRAM_START : integer := 0; -- Start address of dedicated instrution BRAM. + constant SOC_ADDR_INSN_BRAM_END : integer := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_INSN_BRAM_BIT); -- End address of dedicated instruction BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT. + constant SOC_RESET_ADDR_CPU : integer := SOC_ADDR_BRAM_START; -- Initial address to start execution from after reset. + constant SOC_START_ADDR_MEM : integer := SOC_ADDR_BRAM_START; -- Start location of program memory (BRAM/ROM/RAM). + constant SOC_STACK_ADDR : integer := SOC_ADDR_BRAM_END - 8; -- Stack start address (BRAM/RAM). + constant SOC_ADDR_IO_START : integer := (2**(maxAddrBit-WB_ACTIVE)) - (2**maxIOBit); -- Start address of the Evo Direct Memory Mapped IO region. + constant SOC_ADDR_IO_END : integer := (2**(maxAddrBit-WB_ACTIVE)) - 1; -- End address of the Evo Direct Memory Mapped IO region. + constant SOC_WB_IO_START : integer := 32505856; -- Start address of IO range. + constant SOC_WB_IO_END : integer := 33554431; -- End address of IO range. + + -- Ranges used throughout the SOC source. + subtype ADDR_BIT_BRAM_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 0; -- Address range of the onboard B(lock)RAM - 1 byte aligned + subtype ADDR_BIT_BRAM_16BIT_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 1; -- Address range of the onboard B(lock)RAM - 2 bytes aligned + subtype ADDR_BIT_BRAM_32BIT_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto minAddrBit; -- Address range of the onboard B(lock)RAM - 4 bytes aligned + subtype ADDR_BIT_RAM_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto 0; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 1 byte aligned + subtype ADDR_BIT_RAM_16BIT_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto 1; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 2 bytes aligned + subtype ADDR_BIT_RAM_32BIT_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto minAddrBit; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 4 bytes aligned +-- subtype ADDR_DECODE_BRAM_RANGE is natural range maxAddrBit-1 downto SOC_MAX_ADDR_BRAM_BIT;-- Decode range for selection of the BRAM within the address space. +-- subtype ADDR_DECODE_RAM_RANGE is natural range maxAddrBit-1 downto SOC_MAX_ADDR_RAM_BIT; -- Decode range for selection of the RAM within the address space. + subtype IO_DECODE_RANGE is natural range maxAddrBit-WB_ACTIVE-1 downto maxIOBit; -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit. +-- subtype WB_IO_DECODE_RANGE is natural range maxAddrBit-1 downto maxIOBit; -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit. + + -- Device options + type CardType_t is (SD_CARD_E, SDHC_CARD_E); -- Define the different types of SD cards. + + + ------------------------------------------------------------ + -- Constants + ------------------------------------------------------------ + + constant YES : std_logic := '1'; + constant NO : std_logic := '0'; + constant HI : std_logic := '1'; + constant LO : std_logic := '0'; + constant ONE : std_logic := '1'; + constant ZERO : std_logic := '0'; + constant HIZ : std_logic := 'Z'; + + ------------------------------------------------------------ + -- Function prototypes + ------------------------------------------------------------ + -- Find the maximum of two integers. + function IntMax(a : in integer; b : in integer) return integer; + + ------------------------------------------------------------ + -- Records + ------------------------------------------------------------ + + ------------------------------------------------------------ + -- Components + ------------------------------------------------------------ + component dualport_ram is + port ( + clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(ADDR_32BIT_RANGE); + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(ADDR_32BIT_RANGE); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBRead : out std_logic_vector(WORD_32BIT_RANGE) + ); + end component; + + component dpram + generic ( + init_file : string; + widthad_a : natural; + width_a : natural; + widthad_b : natural; + width_b : natural; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + port ( + clock_a : in std_logic := '1'; + clocken_a : in std_logic := '1'; + address_a : in std_logic_vector (widthad_a-1 downto 0); + data_a : in std_logic_vector (width_a-1 downto 0); + wren_a : in std_logic := '0'; + q_a : out std_logic_vector (width_a-1 downto 0); + + clock_b : in std_logic; + clocken_b : in std_logic := '1'; + address_b : in std_logic_vector (widthad_b-1 downto 0); + data_b : in std_logic_vector (width_b-1 downto 0); + wren_b : in std_logic := '0'; + q_b : out std_logic_vector (width_b-1 downto 0) + ); + end component; + + component SDCard is + generic ( + FREQ_G : real := 100.0; -- Master clock frequency (MHz). + INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz). + SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz). + BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector. + CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller. + ); + port ( + -- Host-side interface signals. + clk_i : in std_logic; -- Master clock. + reset_i : in std_logic := NO; -- active-high, synchronous reset. + rd_i : in std_logic := NO; -- active-high read block request. + wr_i : in std_logic := NO; -- active-high write block request. + continue_i : in std_logic := NO; -- If true, inc address and continue R/W. + addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address. + data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block. + data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block. + busy_o : out std_logic; -- High when controller is busy performing some operation. + hndShk_i : in std_logic; -- High when host has data to give or has taken data. + hndShk_o : out std_logic; -- High when controller has taken data or has data to give. + error_o : out std_logic_vector(15 downto 0) := (others => NO); + -- I/O signals to the external SD card. + cs_bo : out std_logic := HI; -- Active-low chip-select. + sclk_o : out std_logic := LO; -- Serial clock to SD card. + mosi_o : out std_logic := HI; -- Serial data output to SD card. + miso_i : in std_logic := ZERO -- Serial data input from SD card. + ); + end component; + +end zpu_soc_pkg; + +------------------------------------------------------------ +-- Function definitions. +------------------------------------------------------------ +package body zpu_soc_pkg is + + -- Find the maximum of two integers. + function IntMax(a : in integer; b : in integer) return integer is + begin + if a > b then + return a; + else + return b; + end if; + return a; + end function IntMax; + +end package body; diff --git a/zpu/zpu_soc_pkg.vhd b/zpu/zpu_soc_pkg.vhd new file mode 100644 index 0000000..90c53fb --- /dev/null +++ b/zpu/zpu_soc_pkg.vhd @@ -0,0 +1,386 @@ +--------------------------------------------------------------------------------------------------------- +-- +-- Name: zpu_soc_pkg.vhd +-- Created: January 2019 +-- Author(s): Philip Smart +-- Description: ZPU System On a Chip Configuration +-- +-- This module contains the System on a Chip configuration for the ZPU. +-- +-- Credits: +-- Copyright: (c) 2018 Philip Smart +-- +-- History: January 2019 - Initial creation. +-- +--------------------------------------------------------------------------------------------------------- +-- This source file is free software: you can redistribute it and-or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--------------------------------------------------------------------------------------------------------- + +library ieee; +library pkgs; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use work.zpu_pkg.all; + +package zpu_soc_pkg is + ------------------------------------------------------------ + -- Function prototypes + ------------------------------------------------------------ + -- Find the maximum of two integers. + function IntMax(a : in integer; b : in integer) return integer; + + -- Find the number of bits required to represent an integer. + function log2ceil(arg : positive) return natural; + + -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns. + function clockTicks(period : in integer; clock : in integer) return integer; + + ------------------------------------------------------------ + -- Constants + ------------------------------------------------------------ + + -- Choose which CPU to instantiate depending on requirements. Warning, keep the below 5 lines exactly the same + -- or ensure you update the Makefile as they are set by the Makefile to generate zpu_soc_pkg.vhd + -- + constant ZPU_SMALL : integer := 0; -- Use the SMALL CPU. + constant ZPU_MEDIUM : integer := 0; -- Use the MEDIUM CPU. + constant ZPU_FLEX : integer := 0; -- Use the FLEX CPU. + constant ZPU_EVO : integer := 0; -- Use the EVOLUTION CPU. + constant ZPU_EVO_MINIMAL : integer := 1; -- Use the Minimalist EVOLUTION CPU. + + -- Target board declaration. + -- + constant BOARD_E115 : boolean := false; -- E115 FPGA Board + constant BOARD_QMV : boolean := false; -- QMTECH Cyclone V FPGA Board + constant BOARD_DE0 : boolean := false; -- DE0-Nano FPGA Board + constant BOARD_DE10 : boolean := false; -- DE10-Nano FPGA Board + constant BOARD_DE10_MISTER : boolean := true; -- DE10-Nano FPGA Board used for the MiSTer project. + constant BOARD_CYC1000 : boolean := false; -- Trenz CYC1000 FPGA Board + + -- Frequencies for the various boards. + -- + constant SYSCLK_E115_FREQ : integer := 100000000; -- E115 FPGA Board + constant SYSCLK_QMV_FREQ : integer := 100000000; -- QMTECH Cyclone V FPGA Board + constant SYSCLK_DE0_FREQ : integer := 100000000; -- DE0-Nano FPGA Board + constant SYSCLK_DE10_FREQ : integer := 100000000; -- DE10-Nano FPGA Board + constant SYSCLK_DE10_MISTER_FREQ : integer := 100000000; -- DE10-Nano FPGA Board for MiSTer project. + constant SYSCLK_CYC1000_FREQ : integer := 100000000; -- Trenz CYC1000 FPGA Board + + -- ID for the various ZPU models. The format is 2 bytes, MSB=, LSB= + constant ZPU_ID_SMALL : integer := 16#0101#; -- ID for the ZPU Small in this package. + constant ZPU_ID_MEDIUM : integer := 16#0201#; -- ID for the ZPU Medium in this package. + constant ZPU_ID_FLEX : integer := 16#0301#; -- ID for the ZPU Flex in this package. + constant ZPU_ID_EVO : integer := 16#0401#; -- ID for the ZPU Evo in this package. + constant ZPU_ID_EVO_MINIMAL : integer := 16#0501#; -- ID for the ZPU Evo Minimal in this package. + + -- EVO CPU specific configuration. + constant MAX_EVO_L1CACHE_BITS : integer := 5; -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache. + constant MAX_EVO_L2CACHE_BITS : integer := 12; -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache. + constant MAX_EVO_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits. + constant MAX_EVO_MIN_L1CACHE_BITS : integer := 4; -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache. + constant MAX_EVO_MIN_L2CACHE_BITS : integer := 12; -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache. + constant MAX_EVO_MIN_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits. + + -- Settings for various IO devices. + -- + constant MAX_RX_FIFO_BITS : integer := 8; -- Size of UART RX Fifo. + constant MAX_TX_FIFO_BITS : integer := 8; -- Size of UART TX Fifo. + constant MAX_UART_DIVISOR_BITS : integer := 16; -- Maximum number of bits for the UART clock rate generator divisor. + constant SYSTEM_FREQUENCY : integer := 100000000; -- Default system clock frequency if not overriden in top level. + + -- SoC specific options. + -- + constant SOC_IMPL_WB : boolean := EVO_USE_WB_BUS; -- Implement the Wishbone bus and all enabled devices. + constant SOC_IMPL_WB_I2C : boolean := false; -- Implement I2C over wishbone interface. + constant SOC_IMPL_TIMER1 : boolean := true; -- Implement Timer 1, an array of prescaled downcounter with enable. + constant SOC_TIMER1_COUNTERS : integer := 0; -- Number of downcounters in Timer 1. Value is a 2^ array of counters, so 0 = 1 counter. + constant SOC_IMPL_PS2 : boolean := false; -- Implement PS2 keyboard and mouse hardware. + constant SOC_IMPL_SPI : boolean := false; -- Implement Serial Peripheral Inteface(s). + constant SOC_IMPL_SD : boolean := true; -- Implement SD Card interface. + constant SOC_SD_DEVICES : integer := 1; -- Number of SD card channels implemented. + constant SOC_IMPL_INTRCTL : boolean := true; -- Implement the prioritised interrupt controller. + constant SOC_INTR_MAX : integer := 16; -- Maximum number of interrupt inputs. + constant SOC_IMPL_IOCTL : boolean := false; -- Implement the IOCTL controller (specific to the MiSTer project). + constant SOC_IMPL_SOCCFG : boolean := true; -- Implement the SoC Configuration information registers. + -- Main Boot BRAM on sysbus, contains startup firmware. + constant SOC_IMPL_BRAM : boolean := true; -- Implement BRAM for the BIOS and initial Stack. + constant SOC_IMPL_INSN_BRAM : boolean := EVO_USE_INSN_BUS; -- Implement dedicated instruction BRAM for the EVO CPU. Any addr access beyond the BRAM size goes to normal memory. + constant SOC_MAX_ADDR_BRAM_BIT : integer := 16; -- Max address bit of the System BRAM ROM/Stack in bytes, ie. 15 = 32KB or 8K 32bit words. NB. For non evo CPUS you must adjust the maxMemBit parameter in zpu_pkg.vhd to be the same. + constant SOC_ADDR_BRAM_START : integer := 0; -- Start address of BRAM. + constant SOC_ADDR_BRAM_END : integer := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_BRAM_BIT); -- End address of BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT. + -- Secondary block of sysbus RAM, typically implemented in BRAM. + constant SOC_IMPL_RAM : boolean := false; -- Implement RAM using BRAM, typically for Application programs seperate to BIOS. + constant SOC_MAX_ADDR_RAM_BIT : integer := 14; -- Max address bit of the System RAM. + constant SOC_ADDR_RAM_START : integer := 65536; -- Start address of RAM. + constant SOC_ADDR_RAM_END : integer := SOC_ADDR_RAM_START+(2**SOC_MAX_ADDR_RAM_BIT); -- End address of RAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT. + -- SDRAM on sysbus. + constant SOC_IMPL_SDRAM : boolean := false; -- Implement Dynamic RAM and controller. + constant SOC_SDRAM_ROWS : integer := 8192; -- 4096; -- Number of Rows within the SDRAM. + constant SOC_SDRAM_COLUMNS : integer := 512; -- 256; -- Number of Columns within the SDRAM. + constant SOC_SDRAM_BANKS : integer := 4; -- Number of Banks within the SDRAM. + constant SOC_SDRAM_DATAWIDTH : integer := 16; -- Data width of SDRAM (ie. 16, 32bit). + constant SOC_SDRAM_CLK_FREQ : integer := 100000000; -- Frequency of the SDRAM clock. + constant SOC_SDRAM_tRCD : integer := 20; -- tRCD - RAS to CAS minimum period (in ns). + constant SOC_SDRAM_tRP : integer := 20; -- tRP - Precharge delay, min time for a precharge command to complete (in ns). + constant SOC_SDRAM_tRFC : integer := 70; -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns + constant SOC_SDRAM_tREF : integer := 64; -- tREF - period of time a complete refresh of all rows is made within (in ms). + constant SOC_MAX_ADDR_SDRAM_BIT : integer := log2ceil(SOC_SDRAM_ROWS * SOC_SDRAM_COLUMNS * SOC_SDRAM_BANKS)+1; -- Max address bit of the System SDRAM. + constant SOC_ADDR_SDRAM_START : integer := 1048576; --65536; -- Start address of RAM. + constant SOC_ADDR_SDRAM_END : integer := SOC_ADDR_SDRAM_START+(2**SOC_MAX_ADDR_SDRAM_BIT); -- End address of RAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT. + -- SDRAM on Wishbone bus. + constant SOC_IMPL_WB_SDRAM : boolean := false; -- Implement SDRAM over wishbone interface. + constant SOC_WB_SDRAM_ROWS : integer := 4096; -- Number of Rows within the SDRAM. + constant SOC_WB_SDRAM_COLUMNS : integer := 256; -- Number of Columns within the SDRAM. + constant SOC_WB_SDRAM_BANKS : integer := 4; -- Number of Banks within the SDRAM. + constant SOC_WB_SDRAM_DATAWIDTH : integer := 16; -- Data width of SDRAM (ie. 16, 32bit). + constant SOC_WB_SDRAM_CLK_FREQ : integer := 100000000; -- Frequency of the SDRAM clock. + constant SOC_WB_SDRAM_tRCD : integer := 20; -- tRCD - RAS to CAS minimum period (in ns). + constant SOC_WB_SDRAM_tRP : integer := 20; -- tRP - Precharge delay, min time for a precharge command to complete (in ns). + constant SOC_WB_SDRAM_tRFC : integer := 70; -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns + constant SOC_WB_SDRAM_tREF : integer := 64; -- tREF - period of time a complete refresh of all rows is made within (in ms). + constant SOC_MAX_ADDR_WB_SDRAM_BIT: integer := log2ceil(SOC_WB_SDRAM_ROWS * SOC_WB_SDRAM_COLUMNS * SOC_WB_SDRAM_BANKS)+1; -- Max address bit of the System SDRAM. + constant SOC_ADDR_WB_SDRAM_START : integer := 16777216; -- Start address of RAM. + constant SOC_ADDR_WB_SDRAM_END : integer := SOC_ADDR_WB_SDRAM_START+(2**SOC_MAX_ADDR_WB_SDRAM_BIT); -- End address of RAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT. + -- Instruction BRAM on sysbus, typically as a 2nd port on the main Boot BRAM (ie. dualport). + constant SOC_MAX_ADDR_INSN_BRAM_BIT: integer := SOC_MAX_ADDR_BRAM_BIT; -- Max address bit of the dedicated instruction BRAM in bytes, ie. 15 = 32KB or 8K 32bit words. + constant SOC_ADDR_INSN_BRAM_START : integer := 0; -- Start address of dedicated instrution BRAM. + constant SOC_ADDR_INSN_BRAM_END : integer := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_INSN_BRAM_BIT); -- End address of dedicated instruction BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT. + + -- CPU specific settings. + -- Define the address which is first executed upon reset, stack address, Sysbus I/O Region, Wishbone I/O Region. + constant SOC_RESET_ADDR_CPU : integer := SOC_ADDR_BRAM_START; -- Initial address to start execution from after reset. + constant SOC_START_ADDR_MEM : integer := SOC_ADDR_BRAM_START; -- Start location of program memory (BRAM/ROM/RAM). + constant SOC_STACK_ADDR : integer := SOC_ADDR_BRAM_END - 8; -- Stack start address (BRAM/RAM). + constant SOC_ADDR_IO_START : integer := (2**(maxAddrBit-WB_ACTIVE)) - (2**maxIOBit); -- Start address of the Evo Direct Memory Mapped IO region. + constant SOC_ADDR_IO_END : integer := (2**(maxAddrBit-WB_ACTIVE)) - 1; -- End address of the Evo Direct Memory Mapped IO region. + constant SOC_WB_IO_START : integer := 32505856; -- Start address of IO range. + constant SOC_WB_IO_END : integer := 33554431; -- End address of IO range. + + -- ZPU Evo configuration + -- + -- Optional Evo CPU hardware features to be implemented. + constant IMPL_EVO_OPTIMIZE_IM : boolean := true; -- If the instruction cache is enabled, optimise Im instructions to gain speed. + -- Optional Evo CPU instructions to be implemented in hardware: + constant IMPL_EVO_ASHIFTLEFT : boolean := true; -- Arithmetic Shift Left (uses same logic so normally combined with ASHIFTRIGHT and LSHIFTRIGHT). + constant IMPL_EVO_ASHIFTRIGHT : boolean := true; -- Arithmetic Shift Right. + constant IMPL_EVO_CALL : boolean := true; -- Call to direct address. + constant IMPL_EVO_CALLPCREL : boolean := true; -- Call to indirect address (add offset to program counter). + constant IMPL_EVO_DIV : boolean := true; -- 32bit signed division. + constant IMPL_EVO_EQ : boolean := true; -- Equality test. + constant IMPL_EVO_EXTENDED_INSN : boolean := true; -- Extended multibyte instruction set. + constant IMPL_EVO_FIADD32 : boolean := false; -- Fixed point Q17.15 addition. + constant IMPL_EVO_FIDIV32 : boolean := false; -- Fixed point Q17.15 division. + constant IMPL_EVO_FIMULT32 : boolean := false; -- Fixed point Q17.15 multiplication. + constant IMPL_EVO_LOADB : boolean := true; -- Load single byte from memory. + constant IMPL_EVO_LOADH : boolean := true; -- Load half word (16bit) from memory. + constant IMPL_EVO_LSHIFTRIGHT : boolean := true; -- Logical shift right. + constant IMPL_EVO_MOD : boolean := true; -- 32bit modulo (remainder after division). + constant IMPL_EVO_MULT : boolean := true; -- 32bit signed multiplication. + constant IMPL_EVO_NEG : boolean := true; -- Negate value in TOS. + constant IMPL_EVO_NEQ : boolean := true; -- Not equal test. + constant IMPL_EVO_POPPCREL : boolean := true; -- Pop a value into the Program Counter from a location relative to the Stack Pointer. + constant IMPL_EVO_PUSHSPADD : boolean := true; -- Add a value to the Stack pointer and push it onto the stack. + constant IMPL_EVO_STOREB : boolean := true; -- Store/Write a single byte to memory/IO. + constant IMPL_EVO_STOREH : boolean := true; -- Store/Write a half word (16bit) to memory/IO. + constant IMPL_EVO_SUB : boolean := true; -- 32bit signed subtract. + constant IMPL_EVO_XOR : boolean := true; -- Exclusive or of value in TOS. + + -- ZPU Evo Minimal configuration + -- + -- Optional Evo Minimal CPU hardware features to be implemented. + constant IMPL_EVOM_OPTIMIZE_IM : boolean := true; -- If the instruction cache is enabled, optimise Im instructions to gain speed. + -- Optional Evo Minimal CPU instructions to be implemented in hardware: + constant IMPL_EVOM_ASHIFTLEFT : boolean := false; -- Arithmetic Shift Left (uses same logic so normally combined with ASHIFTRIGHT and LSHIFTRIGHT). + constant IMPL_EVOM_ASHIFTRIGHT : boolean := false; -- Arithmetic Shift Right. + constant IMPL_EVOM_CALL : boolean := false; -- Call to direct address. + constant IMPL_EVOM_CALLPCREL : boolean := false; -- Call to indirect address (add offset to program counter). + constant IMPL_EVOM_DIV : boolean := false; -- 32bit signed division. + constant IMPL_EVOM_EQ : boolean := false; -- Equality test. + constant IMPL_EVOM_EXTENDED_INSN : boolean := false; -- Extended multibyte instruction set. + constant IMPL_EVOM_FIADD32 : boolean := false; -- Fixed point Q17.15 addition. + constant IMPL_EVOM_FIDIV32 : boolean := false; -- Fixed point Q17.15 division. + constant IMPL_EVOM_FIMULT32 : boolean := false; -- Fixed point Q17.15 multiplication. + constant IMPL_EVOM_LOADB : boolean := true; -- Load single byte from memory. + constant IMPL_EVOM_LOADH : boolean := true; -- Load half word (16bit) from memory. + constant IMPL_EVOM_LSHIFTRIGHT : boolean := false; -- Logical shift right. + constant IMPL_EVOM_MOD : boolean := false; -- 32bit modulo (remainder after division). + constant IMPL_EVOM_MULT : boolean := false; -- 32bit signed multiplication. + constant IMPL_EVOM_NEG : boolean := false; -- Negate value in TOS. + constant IMPL_EVOM_NEQ : boolean := false; -- Not equal test. + constant IMPL_EVOM_POPPCREL : boolean := false; -- Pop a value into the Program Counter from a location relative to the Stack Pointer. + constant IMPL_EVOM_PUSHSPADD : boolean := false; -- Add a value to the Stack pointer and push it onto the stack. + constant IMPL_EVOM_STOREB : boolean := true; -- Store/Write a single byte to memory/IO. + constant IMPL_EVOM_STOREH : boolean := true; -- Store/Write a half word (16bit) to memory/IO. + constant IMPL_EVOM_SUB : boolean := false; -- 32bit signed subtract. + constant IMPL_EVOM_XOR : boolean := false; -- Exclusive or of value in TOS. + + -- Ranges used throughout the SOC source. + subtype ADDR_BIT_BRAM_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 0; -- Address range of the onboard B(lock)RAM - 1 byte aligned + subtype ADDR_16BIT_BRAM_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 1; -- Address range of the onboard B(lock)RAM - 2 bytes aligned + subtype ADDR_32BIT_BRAM_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto minAddrBit; -- Address range of the onboard B(lock)RAM - 4 bytes aligned + subtype ADDR_BIT_RAM_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto 0; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 1 byte aligned + subtype ADDR_16BIT_RAM_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto 1; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 2 bytes aligned + subtype ADDR_32BIT_RAM_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto minAddrBit; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 4 bytes aligned + subtype ADDR_BIT_SDRAM_RANGE is natural range SOC_MAX_ADDR_SDRAM_BIT-1 downto 0; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 1 byte aligned + subtype ADDR_16BIT_SDRAM_RANGE is natural range SOC_MAX_ADDR_SDRAM_BIT-1 downto 1; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 2 bytes aligned + subtype ADDR_32BIT_SDRAM_RANGE is natural range SOC_MAX_ADDR_SDRAM_BIT-1 downto minAddrBit; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 4 bytes aligned + subtype ADDR_BIT_WB_SDRAM_RANGE is natural range SOC_MAX_ADDR_WB_SDRAM_BIT-1 downto 0; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 1 byte aligned + subtype ADDR_16BIT_WB_SDRAM_RANGE is natural range SOC_MAX_ADDR_WB_SDRAM_BIT-1 downto 1; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 2 bytes aligned + subtype ADDR_32BIT_WB_SDRAM_RANGE is natural range SOC_MAX_ADDR_WB_SDRAM_BIT-1 downto minAddrBit; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 4 bytes aligned +-- subtype ADDR_DECODE_BRAM_RANGE is natural range maxAddrBit-1 downto SOC_MAX_ADDR_BRAM_BIT; -- Decode range for selection of the BRAM within the address space. +-- subtype ADDR_DECODE_RAM_RANGE is natural range maxAddrBit-1 downto SOC_MAX_ADDR_RAM_BIT; -- Decode range for selection of the RAM within the address space. + subtype IO_DECODE_RANGE is natural range maxAddrBit-WB_ACTIVE-1 downto maxIOBit; -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit. +-- subtype WB_IO_DECODE_RANGE is natural range maxAddrBit-1 downto maxIOBit; -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit. + + -- Device options + type CardType_t is (SD_CARD_E, SDHC_CARD_E); -- Define the different types of SD cards. + + -- Potential logic state constants. + constant YES : std_logic := '1'; + constant NO : std_logic := '0'; + constant HI : std_logic := '1'; + constant LO : std_logic := '0'; + constant ONE : std_logic := '1'; + constant ZERO : std_logic := '0'; + constant HIZ : std_logic := 'Z'; + + + ------------------------------------------------------------ + -- Records + ------------------------------------------------------------ + + ------------------------------------------------------------ + -- Components + ------------------------------------------------------------ + component dualport_ram is + port ( + clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(ADDR_32BIT_RANGE); + memAWrite : in std_logic_vector(WORD_32BIT_RANGE); + memARead : out std_logic_vector(WORD_32BIT_RANGE); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(ADDR_32BIT_RANGE); + memBWrite : in std_logic_vector(WORD_32BIT_RANGE); + memBRead : out std_logic_vector(WORD_32BIT_RANGE) + ); + end component; + + component dpram + generic ( + init_file : string; + widthad_a : natural; + width_a : natural; + widthad_b : natural; + width_b : natural; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + port ( + clock_a : in std_logic := '1'; + clocken_a : in std_logic := '1'; + address_a : in std_logic_vector (widthad_a-1 downto 0); + data_a : in std_logic_vector (width_a-1 downto 0); + wren_a : in std_logic := '0'; + q_a : out std_logic_vector (width_a-1 downto 0); + + clock_b : in std_logic; + clocken_b : in std_logic := '1'; + address_b : in std_logic_vector (widthad_b-1 downto 0); + data_b : in std_logic_vector (width_b-1 downto 0); + wren_b : in std_logic := '0'; + q_b : out std_logic_vector (width_b-1 downto 0) + ); + end component; + + component SDCard is + generic ( + FREQ_G : real := 100.0; -- Master clock frequency (MHz). + INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz). + SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz). + BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector. + CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller. + ); + port ( + -- Host-side interface signals. + clk_i : in std_logic; -- Master clock. + reset_i : in std_logic := NO; -- active-high, synchronous reset. + rd_i : in std_logic := NO; -- active-high read block request. + wr_i : in std_logic := NO; -- active-high write block request. + continue_i : in std_logic := NO; -- If true, inc address and continue R/W. + addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address. + data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block. + data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block. + busy_o : out std_logic; -- High when controller is busy performing some operation. + hndShk_i : in std_logic; -- High when host has data to give or has taken data. + hndShk_o : out std_logic; -- High when controller has taken data or has data to give. + error_o : out std_logic_vector(15 downto 0) := (others => NO); + -- I/O signals to the external SD card. + cs_bo : out std_logic := HI; -- Active-low chip-select. + sclk_o : out std_logic := LO; -- Serial clock to SD card. + mosi_o : out std_logic := HI; -- Serial data output to SD card. + miso_i : in std_logic := ZERO -- Serial data input from SD card. + ); + end component; + +end zpu_soc_pkg; + +------------------------------------------------------------ +-- Function definitions. +------------------------------------------------------------ +package body zpu_soc_pkg is + + -- Find the maximum of two integers. + function IntMax(a : in integer; b : in integer) return integer is + begin + if a > b then + return a; + else + return b; + end if; + return a; + end function IntMax; + + -- Find the number of bits required to represent an integer. + function log2ceil(arg : positive) return natural is + variable tmp : positive := 1; + variable log : natural := 0; + begin + if arg = 1 then + return 0; + end if; + + while arg > tmp loop + tmp := tmp * 2; + log := log + 1; + end loop; + return log; + end function; + + -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns. + function clockTicks(period : in integer; clock : in integer) return integer is + variable ticks : real; + variable fracTicks : real; + begin + ticks := (Real(period) * Real(clock)) / 1000000000.0; + fracTicks := ticks - CEIL(ticks); + if fracTicks > 0.0001 then + return Integer(CEIL(ticks + 1.0)); + else + return Integer(CEIL(ticks)); + end if; + end function; + +end package body;